diff --git a/Documentation/DocBook/mtdnand.tmpl b/Documentation/DocBook/mtdnand.tmpl
index 0c674be..e0aedb7 100644
--- a/Documentation/DocBook/mtdnand.tmpl
+++ b/Documentation/DocBook/mtdnand.tmpl
@@ -1119,8 +1119,6 @@ in this page</entry>
 		These constants are defined in nand.h. They are ored together to describe
 		the chip functionality.
      		<programlisting>
-/* Chip can not auto increment pages */
-#define NAND_NO_AUTOINCR	0x00000001
 /* Buswitdh is 16 bit */
 #define NAND_BUSWIDTH_16	0x00000002
 /* Device supports partial programming without padding */
diff --git a/Documentation/devicetree/bindings/i2c/ina2xx.txt b/Documentation/devicetree/bindings/i2c/ina2xx.txt
new file mode 100644
index 0000000..a2ad85d
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/ina2xx.txt
@@ -0,0 +1,22 @@
+ina2xx properties
+
+Required properties:
+- compatible: Must be one of the following:
+	- "ti,ina219" for ina219
+	- "ti,ina220" for ina220
+	- "ti,ina226" for ina226
+	- "ti,ina230" for ina230
+- reg: I2C address
+
+Optional properties:
+
+- shunt-resistor
+	Shunt resistor value in micro-Ohm
+
+Example:
+
+ina220@44 {
+	compatible = "ti,ina220";
+	reg = <0x44>;
+	shunt-resistor = <1000>;
+};
diff --git a/Documentation/dma-buf-sharing.txt b/Documentation/dma-buf-sharing.txt
index 3bbd5c5..5ff4d2b 100644
--- a/Documentation/dma-buf-sharing.txt
+++ b/Documentation/dma-buf-sharing.txt
@@ -29,13 +29,6 @@ The buffer-user
    in memory, mapped into its own address space, so it can access the same area
    of memory.
 
-*IMPORTANT*: [see https://lkml.org/lkml/2011/12/20/211 for more details]
-For this first version, A buffer shared using the dma_buf sharing API:
-- *may* be exported to user space using "mmap" *ONLY* by exporter, outside of
-  this framework.
-- with this new iteration of the dma-buf api cpu access from the kernel has been
-  enable, see below for the details.
-
 dma-buf operations for device dma only
 --------------------------------------
 
@@ -313,6 +306,83 @@ Access to a dma_buf from the kernel context involves three steps:
 				  enum dma_data_direction dir);
 
 
+Direct Userspace Access/mmap Support
+------------------------------------
+
+Being able to mmap an export dma-buf buffer object has 2 main use-cases:
+- CPU fallback processing in a pipeline and
+- supporting existing mmap interfaces in importers.
+
+1. CPU fallback processing in a pipeline
+
+   In many processing pipelines it is sometimes required that the cpu can access
+   the data in a dma-buf (e.g. for thumbnail creation, snapshots, ...). To avoid
+   the need to handle this specially in userspace frameworks for buffer sharing
+   it's ideal if the dma_buf fd itself can be used to access the backing storage
+   from userspace using mmap.
+
+   Furthermore Android's ION framework already supports this (and is otherwise
+   rather similar to dma-buf from a userspace consumer side with using fds as
+   handles, too). So it's beneficial to support this in a similar fashion on
+   dma-buf to have a good transition path for existing Android userspace.
+
+   No special interfaces, userspace simply calls mmap on the dma-buf fd.
+
+2. Supporting existing mmap interfaces in exporters
+
+   Similar to the motivation for kernel cpu access it is again important that
+   the userspace code of a given importing subsystem can use the same interfaces
+   with a imported dma-buf buffer object as with a native buffer object. This is
+   especially important for drm where the userspace part of contemporary OpenGL,
+   X, and other drivers is huge, and reworking them to use a different way to
+   mmap a buffer rather invasive.
+
+   The assumption in the current dma-buf interfaces is that redirecting the
+   initial mmap is all that's needed. A survey of some of the existing
+   subsystems shows that no driver seems to do any nefarious thing like syncing
+   up with outstanding asynchronous processing on the device or allocating
+   special resources at fault time. So hopefully this is good enough, since
+   adding interfaces to intercept pagefaults and allow pte shootdowns would
+   increase the complexity quite a bit.
+
+   Interface:
+      int dma_buf_mmap(struct dma_buf *, struct vm_area_struct *,
+		       unsigned long);
+
+   If the importing subsystem simply provides a special-purpose mmap call to set
+   up a mapping in userspace, calling do_mmap with dma_buf->file will equally
+   achieve that for a dma-buf object.
+
+3. Implementation notes for exporters
+
+   Because dma-buf buffers have invariant size over their lifetime, the dma-buf
+   core checks whether a vma is too large and rejects such mappings. The
+   exporter hence does not need to duplicate this check.
+
+   Because existing importing subsystems might presume coherent mappings for
+   userspace, the exporter needs to set up a coherent mapping. If that's not
+   possible, it needs to fake coherency by manually shooting down ptes when
+   leaving the cpu domain and flushing caches at fault time. Note that all the
+   dma_buf files share the same anon inode, hence the exporter needs to replace
+   the dma_buf file stored in vma->vm_file with it's own if pte shootdown is
+   requred. This is because the kernel uses the underlying inode's address_space
+   for vma tracking (and hence pte tracking at shootdown time with
+   unmap_mapping_range).
+
+   If the above shootdown dance turns out to be too expensive in certain
+   scenarios, we can extend dma-buf with a more explicit cache tracking scheme
+   for userspace mappings. But the current assumption is that using mmap is
+   always a slower path, so some inefficiencies should be acceptable.
+
+   Exporters that shoot down mappings (for any reasons) shall not do any
+   synchronization at fault time with outstanding device operations.
+   Synchronization is an orthogonal issue to sharing the backing storage of a
+   buffer and hence should not be handled by dma-buf itself. This is explictly
+   mentioned here because many people seem to want something like this, but if
+   different exporters handle this differently, buffer sharing can fail in
+   interesting ways depending upong the exporter (if userspace starts depending
+   upon this implicit synchronization).
+
 Miscellaneous notes
 -------------------
 
@@ -336,6 +406,20 @@ Miscellaneous notes
   the exporting driver to create a dmabuf fd must provide a way to let
   userspace control setting of O_CLOEXEC flag passed in to dma_buf_fd().
 
+- If an exporter needs to manually flush caches and hence needs to fake
+  coherency for mmap support, it needs to be able to zap all the ptes pointing
+  at the backing storage. Now linux mm needs a struct address_space associated
+  with the struct file stored in vma->vm_file to do that with the function
+  unmap_mapping_range. But the dma_buf framework only backs every dma_buf fd
+  with the anon_file struct file, i.e. all dma_bufs share the same file.
+
+  Hence exporters need to setup their own file (and address_space) association
+  by setting vma->vm_file and adjusting vma->vm_pgoff in the dma_buf mmap
+  callback. In the specific case of a gem driver the exporter could use the
+  shmem file already provided by gem (and set vm_pgoff = 0). Exporters can then
+  zap ptes by unmapping the corresponding range of the struct address_space
+  associated with their own file.
+
 References:
 [1] struct dma_buf_ops in include/linux/dma-buf.h
 [2] All interfaces mentioned above defined in include/linux/dma-buf.h
diff --git a/Documentation/hwmon/adc128d818 b/Documentation/hwmon/adc128d818
new file mode 100644
index 0000000..39c9500
--- /dev/null
+++ b/Documentation/hwmon/adc128d818
@@ -0,0 +1,47 @@
+Kernel driver adc128d818
+========================
+
+Supported chips:
+  * Texas Instruments ADC818D818
+    Prefix: 'adc818d818'
+    Addresses scanned: I2C 0x1d, 0x1e, 0x1f, 0x2d, 0x2e, 0x2f
+    Datasheet: Publicly available at the TI website
+               http://www.ti.com/
+
+Author: Guenter Roeck
+
+Description
+-----------
+
+This driver implements support for the Texas Instruments ADC128D818.
+It is described as 'ADC System Monitor with Temperature Sensor'.
+
+The ADC128D818 implements one temperature sensor and seven voltage sensors.
+
+Temperatures are measured in degrees Celsius. There is one set of limits.
+When the HOT Temperature Limit is crossed, this will cause an alarm that will
+be reasserted until the temperature drops below the HOT Hysteresis.
+Measurements are guaranteed between -55 and +125 degrees. The temperature
+measurement has a resolution of 0.5 degrees; the limits have a resolution
+of 1 degree.
+
+Voltage sensors (also known as IN sensors) report their values in volts.
+An alarm is triggered if the voltage has crossed a programmable minimum
+or maximum limit. Note that minimum in this case always means 'closest to
+zero'; this is important for negative voltage measurements. All voltage
+inputs can measure voltages between 0 and 2.55 volts, with a resolution
+of 0.625 mV.
+
+If an alarm triggers, it will remain triggered until the hardware register
+is read at least once. This means that the cause for the alarm may
+already have disappeared by the time the alarm is read. The driver
+caches the alarm status for each sensor until it is at least reported
+once, to ensure that alarms are reported to user space.
+
+The ADC128D818 only updates its values approximately once per second;
+reading it more often will do no harm, but will return 'old' values.
+
+In addition to the scanned address list, the chip can also be configured for
+addresses 0x35 to 0x37. Those addresses are not scanned. You have to instantiate
+the driver explicitly if the chip is configured for any of those addresses in
+your system.
diff --git a/Documentation/hwmon/ina2xx b/Documentation/hwmon/ina2xx
new file mode 100644
index 0000000..4223c2d
--- /dev/null
+++ b/Documentation/hwmon/ina2xx
@@ -0,0 +1,49 @@
+Kernel driver ina2xx
+====================
+
+Supported chips:
+  * Texas Instruments INA219
+    Prefix: 'ina219'
+    Addresses: I2C 0x40 - 0x4f
+    Datasheet: Publicly available at the Texas Instruments website
+               http://www.ti.com/
+
+  * Texas Instruments INA220
+    Prefix: 'ina220'
+    Addresses: I2C 0x40 - 0x4f
+    Datasheet: Publicly available at the Texas Instruments website
+               http://www.ti.com/
+
+  * Texas Instruments INA226
+    Prefix: 'ina226'
+    Addresses: I2C 0x40 - 0x4f
+    Datasheet: Publicly available at the Texas Instruments website
+               http://www.ti.com/
+
+  * Texas Instruments INA230
+    Prefix: 'ina230'
+    Addresses: I2C 0x40 - 0x4f
+    Datasheet: Publicly available at the Texas Instruments website
+               http://www.ti.com/
+
+Author: Lothar Felten <l-felten@ti.com>
+
+Description
+-----------
+
+The INA219 is a high-side current shunt and power monitor with an I2C
+interface. The INA219 monitors both shunt drop and supply voltage, with
+programmable conversion times and filtering.
+
+The INA220 is a high or low side current shunt and power monitor with an I2C
+interface. The INA220 monitors both shunt drop and supply voltage.
+
+The INA226 is a current shunt and power monitor with an I2C interface.
+The INA226 monitors both a shunt voltage drop and bus supply voltage.
+
+The INA230 is a high or low side current shunt and power monitor with an I2C
+interface. The INA230 monitors both a shunt voltage drop and bus supply voltage.
+
+The shunt value in micro-ohms can be set via platform data or device tree.
+Please refer to the Documentation/devicetree/bindings/i2c/ina2xx.txt for bindings
+if the device tree is used.
diff --git a/Makefile b/Makefile
index 564196d..63dd72f 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,8 @@
 VERSION = 3
 PATCHLEVEL = 4
 SUBLEVEL = 113
-EXTRAVERSION =
+#EXTRAVERSION =
+EXTRAVERSION = -4.0
 NAME = Saber-toothed Squirrel
 
 # *DOCUMENTATION*
@@ -192,7 +193,7 @@ SUBARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \
 # Default value for CROSS_COMPILE is not to prefix executables
 # Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile
 export KBUILD_BUILDHOST := $(SUBARCH)
-ARCH		?= $(SUBARCH)
+ARCH		?= mips
 CROSS_COMPILE	?= $(CONFIG_CROSS_COMPILE:"%"=%)
 
 # Architecture as present in compile.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index eeba63d..b52a81c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -244,6 +244,8 @@ config GENERIC_BUG
 	def_bool y
 	depends on BUG
 
+source "drivers/brcmstb/Kconfig"
+
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
@@ -354,6 +356,11 @@ config ARCH_BCMRING
 	help
 	  Support for Broadcom's BCMRing platform.
 
+config BRCMSTB
+	bool "Broadcom BCM7XXX based boards"
+	help
+	  Support for BCM7XXX based boards
+
 config ARCH_HIGHBANK
 	bool "Calxeda Highbank-based"
 	select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 4533386..ebc1d26 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -144,6 +144,7 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
 # by CONFIG_* macro name.
 machine-$(CONFIG_ARCH_AT91)		:= at91
 machine-$(CONFIG_ARCH_BCMRING)		:= bcmring
+machine-$(CONFIG_BRCMSTB)		:= brcmstb
 machine-$(CONFIG_ARCH_CLPS711X)		:= clps711x
 machine-$(CONFIG_ARCH_CNS3XXX)		:= cns3xxx
 machine-$(CONFIG_ARCH_DAVINCI)		:= davinci
@@ -285,10 +286,15 @@ archprepare:
 # Convert bzImage to zImage
 bzImage: zImage
 
-zImage Image xipImage bootpImage uImage: vmlinux
+BOOT_TARGETS	= zImage Image xipImage bootpImage uImage
+INSTALL_TARGETS	= zinstall uinstall install
+
+PHONY += bzImage $(BOOT_TARGETS) $(INSTALL_TARGETS)
+
+$(BOOT_TARGETS): vmlinux
 	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
 
-zinstall uinstall install: vmlinux
+$(INSTALL_TARGETS):
 	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@
 
 %.dtb: scripts
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index c877087..5319714 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -105,24 +105,24 @@ initrd:
 	@test "$(INITRD)" != "" || \
 	(echo You must specify INITRD; exit -1)
 
-install: $(obj)/Image
-	$(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
+install:
+	$(CONFIG_SHELL) $(srctree)/$(src)/install.sh "$(KERNELRELEASE)" \
 	$(obj)/Image System.map "$(INSTALL_PATH)"
 
-zinstall: $(obj)/zImage
-	$(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
+zinstall:
+	$(CONFIG_SHELL) $(srctree)/$(src)/install.sh "$(KERNELRELEASE)" \
 	$(obj)/zImage System.map "$(INSTALL_PATH)"
 
-uinstall: $(obj)/uImage
-	$(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
+uinstall:
+	$(CONFIG_SHELL) $(srctree)/$(src)/install.sh "$(KERNELRELEASE)" \
 	$(obj)/uImage System.map "$(INSTALL_PATH)"
 
 zi:
-	$(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
+	$(CONFIG_SHELL) $(srctree)/$(src)/install.sh "$(KERNELRELEASE)" \
 	$(obj)/zImage System.map "$(INSTALL_PATH)"
 
 i:
-	$(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
+	$(CONFIG_SHELL) $(srctree)/$(src)/install.sh "$(KERNELRELEASE)" \
 	$(obj)/Image System.map "$(INSTALL_PATH)"
 
 subdir-	    := bootp compressed
diff --git a/arch/arm/boot/dts/bcm7445a0.dts b/arch/arm/boot/dts/bcm7445a0.dts
new file mode 100644
index 0000000..4756c9f
--- /dev/null
+++ b/arch/arm/boot/dts/bcm7445a0.dts
@@ -0,0 +1,129 @@
+/dts-v1/;
+
+/ {
+	model = "Broadcom STB (7445a0)";
+	compatible = "brcm,brcmstb";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&gic>;
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlyprintk";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>; /* 256 MB */
+	};
+
+	// ARM GIC
+	gic: interrupt-controller@FFD00000 {
+		compatible = "arm,cortex-a15-gic";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		reg = <0xFFD01000 0x1000>,
+		      <0xFFD02000 0x2000>;
+	};
+
+	//
+	// UARTS
+	//
+
+	// UART A (0)
+	uart0: serial@F0406B00 {
+		compatible = "ns16550a";
+		reg = <0xF0406B00 0x20>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <0 75 0x4>;
+		clock-frequency = <81000000>;
+	};
+
+	// UART B (1)
+	uart1: serial@F0406B40 {
+		compatible = "ns16550a";
+		reg = <0xF0406B40 0x20>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <0 76 0x4>;
+		clock-frequency = <81000000>;
+	};
+
+	// UART C (2)
+	uart2: serial@F0406B80 {
+		compatible = "ns16550a";
+		reg = <0xF0406B80 0x20>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <0 77 0x4>;
+		clock-frequency = <81000000>;
+	};
+
+	usb0: usb@f0470000 {
+		compatible = "brcm,usb-instance";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0xf0470200 0x100>;
+		ipp = <1>;
+		ioc = <1>;
+		ranges;
+
+		ehci0: ehci@f0470300 {
+			compatible = "brcm,ehci-brcm";
+			reg = <0xf0470300 0x100>;
+			interrupts = <0 79 0>;
+		};
+
+		ohci0: ehci@f0470400 {
+			compatible = "brcm,ohci-brcm";
+			reg = <0xf0470400 0x100>;
+			interrupts = <0 81 0>;
+		};
+
+		ehci1: ehci@f0470500 {
+			compatible = "brcm,ehci-brcm";
+			reg = <0xf0470500 0x100>;
+			interrupts = <0 80 0>;
+		};
+
+		ohci1: ehci@f0470600 {
+			compatible = "brcm,ohci-brcm";
+			reg = <0xf0470600 0x100>;
+			interrupts = <0 82 0>;
+		};
+	};
+
+	usb1: usb@f0480000 {
+		compatible = "brcm,usb-instance";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0xf0480200 0x100>;
+		ipp = <1>;
+		ioc = <1>;
+		ranges;
+
+		ehci2: ehci@f0480300 {
+			compatible = "brcm,ehci-brcm";
+			reg = <0xf0480300 0x100>;
+			interrupts = <0 86 0>;
+		};
+
+		ohci2: ehci@f0480400 {
+			compatible = "brcm,ohci-brcm";
+			reg = <0xf0480400 0x100>;
+			interrupts = <0 88 0>;
+		};
+
+		ehci3: ehci@f0480500 {
+			compatible = "brcm,ehci-brcm";
+			reg = <0xf0480500 0x100>;
+			interrupts = <0 87 0>;
+		};
+
+		ohci3: ehci@f0480600 {
+			compatible = "brcm,ohci-brcm";
+			reg = <0xf0480600 0x100>;
+			interrupts = <0 89 0>;
+		};
+	};
+};
diff --git a/arch/arm/boot/install.sh b/arch/arm/boot/install.sh
index 06ea7d4..2a45092 100644
--- a/arch/arm/boot/install.sh
+++ b/arch/arm/boot/install.sh
@@ -20,6 +20,20 @@
 #   $4 - default install path (blank if root directory)
 #
 
+verify () {
+	if [ ! -f "$1" ]; then
+		echo ""                                                   1>&2
+		echo " *** Missing file: $1"                              1>&2
+		echo ' *** You need to run "make" before "make install".' 1>&2
+		echo ""                                                   1>&2
+		exit 1
+	fi
+}
+
+# Make sure the files actually exist
+verify "$2"
+verify "$3"
+
 # User may have a custom install script
 if [ -x ~/bin/${INSTALLKERNEL} ]; then exec ~/bin/${INSTALLKERNEL} "$@"; fi
 if [ -x /sbin/${INSTALLKERNEL} ]; then exec /sbin/${INSTALLKERNEL} "$@"; fi
diff --git a/arch/arm/configs/bcm7445a0_defconfig b/arch/arm/configs/bcm7445a0_defconfig
new file mode 100644
index 0000000..907210c
--- /dev/null
+++ b/arch/arm/configs/bcm7445a0_defconfig
@@ -0,0 +1,125 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_CROSS_COMPILE="arm-linux-"
+CONFIG_KERNEL_LZMA=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_BRCMSTB=y
+# CONFIG_SWP_EMULATE is not set
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk"
+CONFIG_VFP=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 7b787d6..720f9e3 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -33,7 +33,9 @@ obj-$(CONFIG_PCI)		+= bios32.o isa.o
 obj-$(CONFIG_ARM_CPU_SUSPEND)	+= sleep.o suspend.o
 obj-$(CONFIG_SMP)		+= smp.o smp_tlb.o
 obj-$(CONFIG_HAVE_ARM_SCU)	+= smp_scu.o
+ifndef CONFIG_BRCMSTB
 obj-$(CONFIG_HAVE_ARM_TWD)	+= smp_twd.o
+endif
 obj-$(CONFIG_DYNAMIC_FTRACE)	+= ftrace.o insn.o
 obj-$(CONFIG_FUNCTION_GRAPH_TRACER)	+= ftrace.o insn.o
 obj-$(CONFIG_JUMP_LABEL)	+= jump_label.o insn.o patch.o
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 8f14a1b..65b14a7 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -127,7 +127,7 @@ static void percpu_timer_stop(void);
 /*
  * __cpu_disable runs on the processor to be shutdown.
  */
-int __cpu_disable(void)
+int __cpuinit __cpu_disable(void)
 {
 	unsigned int cpu = smp_processor_id();
 	struct task_struct *p;
@@ -176,7 +176,7 @@ static DECLARE_COMPLETION(cpu_died);
  * called on the thread which is asking for a CPU to be shutdown -
  * waits until shutdown has completed, or it is timed out.
  */
-void __cpu_die(unsigned int cpu)
+void __cpuinit __cpu_die(unsigned int cpu)
 {
 	if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) {
 		pr_err("CPU%u: cpu didn't die\n", cpu);
diff --git a/arch/arm/mach-brcmstb/Makefile b/arch/arm/mach-brcmstb/Makefile
new file mode 100644
index 0000000..157db0e
--- /dev/null
+++ b/arch/arm/mach-brcmstb/Makefile
@@ -0,0 +1 @@
+obj-y	+= common.o time.o platsmp.o headsmp.o
diff --git a/arch/arm/mach-brcmstb/Makefile.boot b/arch/arm/mach-brcmstb/Makefile.boot
new file mode 100644
index 0000000..5b9c54d
--- /dev/null
+++ b/arch/arm/mach-brcmstb/Makefile.boot
@@ -0,0 +1,3 @@
+zreladdr-y := 0x00008000
+
+dtb-$(CONFIG_BCM7445A0) += bcm7445a0.dtb
diff --git a/arch/arm/mach-brcmstb/common.c b/arch/arm/mach-brcmstb/common.c
new file mode 100644
index 0000000..377e79a
--- /dev/null
+++ b/arch/arm/mach-brcmstb/common.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/clk.h>
+#include <linux/serial_8250.h>
+#include <linux/if_ether.h>
+#include <linux/platform_device.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/gic.h>
+
+#include <mach/irqs.h>
+#include <mach/hardware.h>
+
+#include "common.h"
+
+static struct map_desc io_map[] __initdata = {
+	{
+	.virtual = (unsigned long)BRCMSTB_PERIPH_VIRT,
+	.pfn     = __phys_to_pfn(BRCMSTB_PERIPH_PHYS),
+	.length  = BRCMSTB_PERIPH_LENGTH,
+	.type    = MT_DEVICE,
+	},
+};
+
+static const char *brcmstb_match[] __initdata = {
+	"brcm,brcmstb",
+	NULL
+};
+
+static const struct of_device_id brcmstb_dt_irq_match[] __initconst = {
+	{ .compatible = "arm,cortex-a15-gic", .data = gic_of_init },
+	{ }
+};
+
+static void __init brcmstb_map_io(void)
+{
+	iotable_init(io_map, ARRAY_SIZE(io_map));
+}
+
+static void __init brcmstb_machine_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+
+	/*
+	 * FIXME: In 3.8+ the bchip_* calls should go away; DT will tell us
+	 * which peripherals are enabled
+	 */
+	bchip_set_features();
+
+	printk(KERN_INFO "Options: moca=%d sata=%d pcie=%d usb=%d\n",
+		brcm_moca_enabled, brcm_sata_enabled,
+		brcm_pcie_enabled, brcm_usb_enabled);
+
+	bchip_early_setup();
+}
+
+static void brcmstb_restart(char mode, const char *cmd)
+{
+	brcm_machine_restart(cmd);
+}
+
+void __init brcmstb_dt_init_irq(void)
+{
+	BDEV_WR(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uarta_irqen_MASK
+		| BCHP_IRQ0_IRQEN_uartb_irqen_MASK
+		| BCHP_IRQ0_IRQEN_uartc_irqen_MASK
+		);
+	of_irq_init(brcmstb_dt_irq_match);
+}
+
+extern asmlinkage void brcmstb_handle_irq(struct pt_regs *regs);
+
+DT_MACHINE_START(BRCMSTB, "Broadcom STB (Flattened Device Tree)")
+	.map_io		= brcmstb_map_io,
+	.init_irq	= brcmstb_dt_init_irq,
+	.handle_irq	= gic_handle_irq,
+	.timer		= &brcmstb_timer,
+	.init_machine	= brcmstb_machine_init,
+	.dt_compat	= brcmstb_match,
+	.restart	= brcmstb_restart,
+MACHINE_END
diff --git a/arch/arm/mach-brcmstb/common.h b/arch/arm/mach-brcmstb/common.h
new file mode 100644
index 0000000..b892125
--- /dev/null
+++ b/arch/arm/mach-brcmstb/common.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef __BRCMSTB_COMMON_H__
+#define __BRCMSTB_COMMON_H__
+
+#include <asm/mach/time.h>
+
+extern struct sys_timer brcmstb_timer;
+extern void brcmstb_secondary_startup(void);
+
+#endif /* __BRCMSTB_COMMON_H__ */
diff --git a/arch/arm/mach-brcmstb/headsmp.S b/arch/arm/mach-brcmstb/headsmp.S
new file mode 100644
index 0000000..2cc8c27
--- /dev/null
+++ b/arch/arm/mach-brcmstb/headsmp.S
@@ -0,0 +1,75 @@
+/*
+ * SMP boot code for secondary CPUs
+ * Based on arch/arm/mach-tegra/headsmp.S
+ *
+ * Copyright (C) 2010 NVIDIA, Inc.
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+        .section ".text.head", "ax"
+	__CPUINIT
+
+/*
+ * Entry point for secondary CPUs.
+ *   The secondary kernel init calls v7_flush_dcache_all before it enables
+ *   the L1; however, the L1 comes out of reset in an undefined state, so
+ *   the clean + invalidate performed by v7_flush_dcache_all causes a bunch
+ *   of cache lines with uninitialized data and uninitialized tags to get
+ *   written out to memory, which does really unpleasant things to the main
+ *   processor.  We fix this by performing an invalidate, rather than a
+ *   clean + invalidate, before jumping into the kernel.
+ */
+ENTRY(v7_invalidate_l1)
+        mov     r0, #0
+        mcr     p15, 2, r0, c0, c0, 0
+        mrc     p15, 1, r0, c0, c0, 0
+
+        ldr     r1, =0x7fff
+        and     r2, r1, r0, lsr #13
+
+        ldr     r1, =0x3ff
+
+        and     r3, r1, r0, lsr #3  @ NumWays - 1
+        add     r2, r2, #1          @ NumSets
+
+        and     r0, r0, #0x7
+        add     r0, r0, #4          @ SetShift
+
+        clz     r1, r3              @ WayShift
+        add     r4, r3, #1          @ NumWays
+1:      sub     r2, r2, #1          @ NumSets--
+        mov     r3, r4              @ Temp = NumWays
+2:      subs    r3, r3, #1          @ Temp--
+        mov     r5, r3, lsl r1
+        mov     r6, r2, lsl r0
+        orr     r5, r5, r6          @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
+        mcr     p15, 0, r5, c7, c6, 2
+        bgt     2b
+        cmp     r2, #0
+        bgt     1b
+        dsb
+        isb
+        mov     pc, lr
+ENDPROC(v7_invalidate_l1)
+
+ENTRY(brcmstb_secondary_startup)
+        msr     cpsr_fsxc, #0xd3
+        bl      v7_invalidate_l1
+        b       secondary_startup
+ENDPROC(brcmstb_secondary_startup)
diff --git a/arch/arm/mach-brcmstb/include/mach/debug-macro.S b/arch/arm/mach-brcmstb/include/mach/debug-macro.S
new file mode 100644
index 0000000..a64e420
--- /dev/null
+++ b/arch/arm/mach-brcmstb/include/mach/debug-macro.S
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ * Copyright (c) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Derived from arch/arm/mach-davinci/include/mach/debug-macro.S to use 32-bit
+ * accesses to the 8250.
+ */
+
+#include <linux/serial_reg.h>
+#include <mach/hardware.h>
+
+#define UART_SHIFT 2
+
+		.macro	addruart, rp, rv, tmp
+		ldr	\rv, =PHYS_TO_IO(BRCMSTB_UARTA_BASE)
+		ldr	\rp, =BRCMSTB_UARTA_BASE
+		.endm
+
+		.macro	senduart,rd,rx
+		str	\rd, [\rx, #UART_TX << UART_SHIFT]
+		.endm
+
+		.macro	busyuart,rd,rx
+1002:		ldr	\rd, [\rx, #UART_LSR << UART_SHIFT]
+		and	\rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
+		teq	\rd, #UART_LSR_TEMT | UART_LSR_THRE
+		bne	1002b
+		.endm
+
+		/* The UART's don't have any flow control IO's wired up. */
+		.macro	waituart,rd,rx
+		.endm
diff --git a/arch/arm/mach-brcmstb/include/mach/entry-macro.S b/arch/arm/mach-brcmstb/include/mach/entry-macro.S
new file mode 100644
index 0000000..9b505ac
--- /dev/null
+++ b/arch/arm/mach-brcmstb/include/mach/entry-macro.S
@@ -0,0 +1,16 @@
+/*
+ * entry-macro.S
+ *
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * Low-level IRQ helper macros for picoXcell platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+	.macro  disable_fiq
+	.endm
+
+	.macro  arch_ret_to_user, tmp1, tmp2
+	.endm
diff --git a/arch/arm/mach-brcmstb/include/mach/gpio.h b/arch/arm/mach-brcmstb/include/mach/gpio.h
new file mode 100644
index 0000000..40a8c17
--- /dev/null
+++ b/arch/arm/mach-brcmstb/include/mach/gpio.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/arch/arm/mach-brcmstb/include/mach/hardware.h b/arch/arm/mach-brcmstb/include/mach/hardware.h
new file mode 100644
index 0000000..09c7fa8
--- /dev/null
+++ b/arch/arm/mach-brcmstb/include/mach/hardware.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <linux/brcmstb/brcmstb.h>
+#include <linux/compiler.h>
+
+/* FIXME: Read this from device tree */
+#define BRCMSTB_UARTA_BASE	BPHYSADDR(BCHP_UARTA_REG_START)
+
+#define __BRCMSTB_PERIPH_VIRT	0xfd000000
+#define BRCMSTB_PERIPH_VIRT	((void __iomem *)__BRCMSTB_PERIPH_VIRT)
+#define BRCMSTB_PERIPH_PHYS	BPHYSADDR(0)
+#define BRCMSTB_PERIPH_LENGTH	SZ_32M
+
+#define PHYS_TO_IO(x)		(((x) & 0x00ffffff) | __BRCMSTB_PERIPH_VIRT)
+
+#ifdef __ASSEMBLY__
+#define IO_ADDRESS(x)		PHYS_TO_IO((x))
+#else
+#define IO_ADDRESS(x)		(void __iomem __force *)(PHYS_TO_IO((x)))
+#endif
+
+#endif
diff --git a/arch/arm/mach-brcmstb/include/mach/io.h b/arch/arm/mach-brcmstb/include/mach/io.h
new file mode 100644
index 0000000..7573ec7
--- /dev/null
+++ b/arch/arm/mach-brcmstb/include/mach/io.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+/* No ioports, but needed for driver compatibility. */
+#define __io(a)			__typesafe_io(a)
+/* No PCI possible on picoxcell. */
+#define __mem_pci(a)		(a)
+
+#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-brcmstb/include/mach/irqs.h b/arch/arm/mach-brcmstb/include/mach/irqs.h
new file mode 100644
index 0000000..87be8d4
--- /dev/null
+++ b/arch/arm/mach-brcmstb/include/mach/irqs.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+/* We dynamically allocate our irq_desc's. */
+#define NR_IRQS				0
+
+#define IRQ_LOCALTIMER			29
+#define BRCMSTB_GIC_START		31
+
+#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-brcmstb/include/mach/system.h b/arch/arm/mach-brcmstb/include/mach/system.h
new file mode 100644
index 0000000..1a5d8cb
--- /dev/null
+++ b/arch/arm/mach-brcmstb/include/mach/system.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+static inline void arch_idle(void)
+{
+	/*
+	 * This should do all the clock switching and wait for interrupt
+	 * tricks.
+	 */
+	cpu_do_idle();
+}
+
+#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-brcmstb/include/mach/timex.h b/arch/arm/mach-brcmstb/include/mach/timex.h
new file mode 100644
index 0000000..6c540a6
--- /dev/null
+++ b/arch/arm/mach-brcmstb/include/mach/timex.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __TIMEX_H__
+#define __TIMEX_H__
+
+/* Bogus value to allow the kernel to compile. */
+#define CLOCK_TICK_RATE		1000000
+
+#endif /* __TIMEX_H__ */
+
diff --git a/arch/arm/mach-brcmstb/include/mach/uncompress.h b/arch/arm/mach-brcmstb/include/mach/uncompress.h
new file mode 100644
index 0000000..b4d74ce
--- /dev/null
+++ b/arch/arm/mach-brcmstb/include/mach/uncompress.h
@@ -0,0 +1,49 @@
+/*
+ *  arch/arm/mach-brcmstb/include/mach/uncompress.h
+ *  Derived from: arch/arm/mach-ebsa110/include/mach/uncompress.h
+ *
+ *  Copyright (C) 1996,1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/serial_reg.h>
+#include <linux/types.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#define SERIAL_BASE	((void __iomem *)BPHYSADDR(BCHP_UARTA_REG_START))
+
+/*
+ * This does not append a newline
+ */
+static inline void putc(int c)
+{
+	u32 v;
+	u32 *base = SERIAL_BASE;
+
+	do {
+		v = base[UART_LSR];
+		barrier();
+	} while (!(v & UART_LSR_THRE));
+
+	base[UART_TX] = c;
+}
+
+static inline void flush(void)
+{
+	unsigned char v, *base = SERIAL_BASE;
+
+	do {
+		v = base[UART_LSR << 2];
+		barrier();
+	} while ((v & (UART_LSR_TEMT|UART_LSR_THRE)) !=
+		 (UART_LSR_TEMT|UART_LSR_THRE));
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-brcmstb/platsmp.c b/arch/arm/mach-brcmstb/platsmp.c
new file mode 100644
index 0000000..75e2528
--- /dev/null
+++ b/arch/arm/mach-brcmstb/platsmp.c
@@ -0,0 +1,133 @@
+/*
+ * Broadcom STB SMP support for ARM
+ * Based on arch/arm/mach-tegra/platsmp.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ *  Copyright (C) 2009 Palm
+ *  All Rights Reserved
+ *
+ *  Copyright (C) 2013 Broadcom Corporation
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/jiffies.h>
+#include <linux/printk.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach-types.h>
+
+#include <mach/hardware.h>
+#include "common.h"
+
+static DEFINE_SPINLOCK(boot_lock);
+
+/***********************************************************************
+ * SMP boot
+ ***********************************************************************/
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+	/*
+	 * if any interrupts are already enabled for the primary
+	 * core (e.g. timer irq), then they will not have been enabled
+	 * for us: do so
+	 */
+	gic_secondary_init(0);
+
+	/*
+	 * Synchronise with the boot thread.
+	 */
+	spin_lock(&boot_lock);
+	spin_unlock(&boot_lock);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	unsigned long boot_vector;
+
+	pr_info("SMP: Booting CPU%d...\n", cpu);
+
+	/*
+	 * set synchronisation state between this boot processor
+	 * and the secondary one
+	 */
+	spin_lock(&boot_lock);
+
+	/* set the reset vector to point to the secondary_startup routine */
+	boot_vector = virt_to_phys(brcmstb_secondary_startup);
+	BDEV_WR(BCHP_HIF_CONTINUATION_STB_BOOT_ADDR0 + cpu * 8, boot_vector);
+
+	smp_wmb();
+
+	flush_cache_all();
+
+	/* unhalt the cpu */
+	BDEV_UNSET(BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG, BIT(cpu));
+
+	/*
+	 * now the secondary core is starting up let it run its
+	 * calibrations, then wait for it to finish
+	 */
+	spin_unlock(&boot_lock);
+
+	return 0;
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+void __init smp_init_cpus(void)
+{
+	/* FIXME: ncores needs to come from DT */
+	unsigned int i, ncores = 4;
+
+	if (ncores > nr_cpu_ids) {
+		pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+			ncores, nr_cpu_ids);
+		ncores = nr_cpu_ids;
+	}
+
+	for (i = 0; i < ncores; i++)
+		set_cpu_possible(i, true);
+
+	set_smp_cross_call(gic_raise_softirq);
+}
+
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+}
+
+/***********************************************************************
+ * CPU Hotplug
+ ***********************************************************************/
+
+int platform_cpu_disable(unsigned int cpu)
+{
+	/* FIXME: not currently implemented */
+	return -EPERM;
+}
+
+void platform_cpu_die(unsigned int cpu)
+{
+	BUG();
+}
+
+int platform_cpu_kill(unsigned int cpu)
+{
+	return 0;
+}
diff --git a/arch/arm/mach-brcmstb/time.c b/arch/arm/mach-brcmstb/time.c
new file mode 100644
index 0000000..f9d759c
--- /dev/null
+++ b/arch/arm/mach-brcmstb/time.c
@@ -0,0 +1,364 @@
+/*
+ * Rudimentary ARM architected timer support
+ * Derived from arch/arm/kernel/arch_timer.c in mainline
+ *
+ * Copyright (C) 2011 ARM Ltd.
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/smp.h>
+#include <linux/cpu.h>
+#include <linux/jiffies.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/of_irq.h>
+#include <linux/io.h>
+
+#include <asm/cputype.h>
+#include <asm/localtimer.h>
+#include <asm/sched_clock.h>
+#include <asm/mach/time.h>
+#include <asm/smp_plat.h>
+#include <mach/irqs.h>
+
+#include <linux/brcmstb/brcmstb.h>
+
+static unsigned long arch_timer_rate;
+static int arch_timer_ppi;
+static int arch_timer_ppi2;
+
+static struct clock_event_device __percpu **arch_timer_evt;
+
+/*
+ * Architected system timer support.
+ */
+
+#define ARCH_TIMER_CTRL_ENABLE		(1 << 0)
+#define ARCH_TIMER_CTRL_IT_MASK		(1 << 1)
+#define ARCH_TIMER_CTRL_IT_STAT		(1 << 2)
+
+#define ARCH_TIMER_REG_CTRL		0
+#define ARCH_TIMER_REG_FREQ		1
+#define ARCH_TIMER_REG_TVAL		2
+
+static void arch_timer_reg_write(int reg, u32 val)
+{
+	switch (reg) {
+	case ARCH_TIMER_REG_CTRL:
+		asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
+		break;
+	case ARCH_TIMER_REG_TVAL:
+		asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
+		break;
+	}
+
+	isb();
+}
+
+static u32 arch_timer_reg_read(int reg)
+{
+	u32 val;
+
+	switch (reg) {
+	case ARCH_TIMER_REG_CTRL:
+		asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
+		break;
+	case ARCH_TIMER_REG_FREQ:
+		asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
+		break;
+	case ARCH_TIMER_REG_TVAL:
+		asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
+		break;
+	default:
+		BUG();
+	}
+
+	return val;
+}
+
+static irqreturn_t arch_timer_handler(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
+	unsigned long ctrl;
+
+	ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+	if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
+		ctrl |= ARCH_TIMER_CTRL_IT_MASK;
+		arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+		evt->event_handler(evt);
+		return IRQ_HANDLED;
+	}
+
+	return IRQ_NONE;
+}
+
+static void arch_timer_disable(void)
+{
+	unsigned long ctrl;
+
+	ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+	ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
+	arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+}
+
+static void arch_timer_set_mode(enum clock_event_mode mode,
+				struct clock_event_device *clk)
+{
+	switch (mode) {
+	case CLOCK_EVT_MODE_UNUSED:
+	case CLOCK_EVT_MODE_SHUTDOWN:
+		arch_timer_disable();
+		break;
+	default:
+		break;
+	}
+}
+
+static int arch_timer_set_next_event(unsigned long evt,
+				     struct clock_event_device *unused)
+{
+	unsigned long ctrl;
+
+	ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+	ctrl |= ARCH_TIMER_CTRL_ENABLE;
+	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
+
+	arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt);
+	arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+
+	return 0;
+}
+
+int __cpuinit local_timer_setup(struct clock_event_device *clk)
+{
+	/* Be safe... */
+	arch_timer_disable();
+
+	clk->features = CLOCK_EVT_FEAT_ONESHOT;
+	clk->name = "arch_sys_timer";
+	clk->rating = 450;
+	clk->set_mode = arch_timer_set_mode;
+	clk->set_next_event = arch_timer_set_next_event;
+	clk->irq = arch_timer_ppi;
+
+	clockevents_config_and_register(clk, arch_timer_rate,
+					0xf, 0x7fffffff);
+
+	*__this_cpu_ptr(arch_timer_evt) = clk;
+
+	enable_percpu_irq(clk->irq, 0);
+	if (arch_timer_ppi2)
+		enable_percpu_irq(arch_timer_ppi2, 0);
+
+	return 0;
+}
+
+/* Is the optional system timer available? */
+static int local_timer_is_architected(void)
+{
+	return (cpu_architecture() >= CPU_ARCH_ARMv7) &&
+	       ((read_cpuid_ext(CPUID_EXT_PFR1) >> 16) & 0xf) == 1;
+}
+
+static int arch_timer_available(void)
+{
+	unsigned long freq;
+
+	if (!local_timer_is_architected())
+		return -ENXIO;
+
+	if (arch_timer_rate == 0) {
+		arch_timer_reg_write(ARCH_TIMER_REG_CTRL, 0);
+		freq = arch_timer_reg_read(ARCH_TIMER_REG_FREQ);
+
+		/* Check the timer frequency. */
+		if (freq == 0) {
+			pr_warn("Architected timer frequency not available\n");
+			return -EINVAL;
+		}
+
+		arch_timer_rate = freq;
+	}
+
+	pr_info_once("Architected local timer running at %lu.%02luMHz.\n",
+		     arch_timer_rate / 1000000,
+		     (arch_timer_rate / 10000) % 100);
+	return 0;
+}
+
+static inline cycle_t arch_counter_get_cntpct(void)
+{
+	u32 cvall, cvalh;
+
+	asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
+
+	return ((cycle_t) cvalh << 32) | cvall;
+}
+
+static inline cycle_t arch_counter_get_cntvct(void)
+{
+	u32 cvall, cvalh;
+
+	asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
+
+	return ((cycle_t) cvalh << 32) | cvall;
+}
+
+static u32 notrace arch_counter_get_cntvct32(void)
+{
+	cycle_t cntvct = arch_counter_get_cntvct();
+
+	/*
+	 * The sched_clock infrastructure only knows about counters
+	 * with at most 32bits. Forget about the upper 24 bits for the
+	 * time being...
+	 */
+	return (u32)(cntvct & (u32)~0);
+}
+
+static cycle_t arch_counter_read(struct clocksource *cs)
+{
+	return arch_counter_get_cntpct();
+}
+
+static struct clocksource clocksource_counter = {
+	.name	= "arch_sys_counter",
+	.rating	= 400,
+	.read	= arch_counter_read,
+	.mask	= CLOCKSOURCE_MASK(56),
+	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+void __cpuinit local_timer_stop(struct clock_event_device *clk)
+{
+	pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
+		 clk->irq, smp_processor_id());
+	disable_percpu_irq(clk->irq);
+	if (arch_timer_ppi2)
+		disable_percpu_irq(arch_timer_ppi2);
+	arch_timer_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
+}
+
+static struct clock_event_device arch_timer_global_evt;
+
+static int __init arch_timer_register(void)
+{
+	int err;
+
+	err = arch_timer_available();
+	if (err)
+		return err;
+
+	arch_timer_evt = alloc_percpu(struct clock_event_device *);
+	if (!arch_timer_evt)
+		return -ENOMEM;
+
+	clocksource_register_hz(&clocksource_counter, arch_timer_rate);
+
+	err = request_percpu_irq(arch_timer_ppi, arch_timer_handler,
+				 "arch_timer", arch_timer_evt);
+	if (err) {
+		pr_err("arch_timer: can't register interrupt %d (%d)\n",
+		       arch_timer_ppi, err);
+		goto out_free;
+	}
+
+	if (arch_timer_ppi2) {
+		err = request_percpu_irq(arch_timer_ppi2, arch_timer_handler,
+					 "arch_timer", arch_timer_evt);
+		if (err) {
+			pr_err("arch_timer: can't register interrupt %d (%d)\n",
+			       arch_timer_ppi2, err);
+			arch_timer_ppi2 = 0;
+			goto out_free_irq;
+		}
+	}
+
+	/* Execute if 'nosmp' or UP configured */
+	if (setup_max_cpus <= 1) {
+		/*
+		 * We couldn't register as a local timer (could be
+		 * because we're on a UP platform, or because some
+		 * other local timer is already present...). Try as a
+		 * global timer instead.
+		 */
+		arch_timer_global_evt.cpumask = cpumask_of(0);
+		err = local_timer_setup(&arch_timer_global_evt);
+
+		if (err)
+			goto out_free_irq;
+	}
+
+	return 0;
+
+out_free_irq:
+	free_percpu_irq(arch_timer_ppi, arch_timer_evt);
+	if (arch_timer_ppi2)
+		free_percpu_irq(arch_timer_ppi2, arch_timer_evt);
+
+out_free:
+	free_percpu(arch_timer_evt);
+
+	return err;
+}
+
+static const struct of_device_id arch_timer_of_match[] __initconst = {
+	{.compatible	= "arm,armv7-timer",},
+	{},
+};
+
+int __init arch_timer_of_register(void)
+{
+	struct device_node *np;
+	u32 freq;
+
+	np = of_find_matching_node(NULL, arch_timer_of_match);
+	if (!np) {
+		pr_err("arch_timer: can't find DT node\n");
+		return -ENODEV;
+	}
+
+	/* Try to determine the frequency from the device tree or CNTFRQ */
+	if (!of_property_read_u32(np, "clock-frequency", &freq))
+		arch_timer_rate = freq;
+
+	arch_timer_ppi = irq_of_parse_and_map(np, 0);
+	arch_timer_ppi2 = irq_of_parse_and_map(np, 1);
+	pr_info("arch_timer: found %s irqs %d %d\n",
+		np->name, arch_timer_ppi, arch_timer_ppi2);
+
+	return arch_timer_register();
+}
+
+int __init arch_timer_sched_clock_init(void)
+{
+	int err;
+
+	err = arch_timer_available();
+	if (err)
+		return err;
+
+	setup_sched_clock(arch_counter_get_cntvct32, 32, arch_timer_rate);
+	return 0;
+}
+
+void __init brcmstb_timer_init(void)
+{
+	BUG_ON(arch_timer_of_register() != 0);
+	BUG_ON(arch_timer_sched_clock_init());
+
+	/* Calibrate the delay loop directly */
+	lpj_fine = arch_timer_rate / HZ;
+}
+
+struct sys_timer brcmstb_timer = {
+	.init = brcmstb_timer_init,
+};
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
index 0c00852..a457df9 100644
--- a/arch/arm/mach-ep93xx/snappercl15.c
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -103,7 +103,6 @@ static struct platform_nand_data snappercl15_nand_data = {
 		.part_probe_types	= snappercl15_nand_part_probes,
 		.partitions		= snappercl15_nand_parts,
 		.nr_partitions		= ARRAY_SIZE(snappercl15_nand_parts),
-		.options		= NAND_NO_AUTOINCR,
 		.chip_delay		= 25,
 	},
 	.ctrl = {
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index 3d742ae..f68110ed 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -100,7 +100,6 @@ static struct platform_nand_data ixdp425_flash_nand_data = {
 	.chip = {
 		.nr_chips		= 1,
 		.chip_delay		= 30,
-		.options		= NAND_NO_AUTOINCR,
 		.part_probe_types 	= part_probes,
 		.partitions	 	= ixdp425_partitions,
 		.nr_partitions	 	= ARRAY_SIZE(ixdp425_partitions),
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
index 58cacaf..2e8d3e1 100644
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -111,7 +111,7 @@ static struct nomadik_nand_platform_data nhk8815_nand_data = {
 	.parts		= nhk8815_partitions,
 	.nparts		= ARRAY_SIZE(nhk8815_partitions),
 	.options	= NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING \
-			| NAND_NO_READRDY | NAND_NO_AUTOINCR,
+			| NAND_NO_READRDY,
 	.init		= nhk8815_nand_init,
 };
 
diff --git a/arch/arm/mach-picoxcell/irq.c b/arch/arm/mach-picoxcell/irq.c
new file mode 100644
index 0000000..b9c97b9
--- /dev/null
+++ b/arch/arm/mach-picoxcell/irq.c
@@ -0,0 +1,93 @@
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/syscore_ops.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/bitops.h>
+
+#include <asm/exception.h>
+
+#include <mach/irqs.h>
+
+static const void __iomem *base = (void *)0xee41a400;
+
+#define IRQBIT(irq)		BIT((irq) & 0x1f)
+#define IRQWD(irq)		(base + (((irq) >> 5) << 2))
+
+void brcmstb_mask_irq(struct irq_data *d)
+{
+	__raw_writel(IRQBIT(d->irq), IRQWD(d->irq) + 0x18);
+}
+
+void brcmstb_unmask_irq(struct irq_data *d)
+{
+	__raw_writel(IRQBIT(d->irq), IRQWD(d->irq) + 0x24);
+}
+
+static struct irq_chip brcmstb_internal_irq_chip = {
+	.name		= "HIF_L1",
+	.irq_ack	= brcmstb_mask_irq,
+	.irq_mask	= brcmstb_mask_irq,
+	.irq_unmask	= brcmstb_unmask_irq,
+};
+
+#define do_IRQ(x)		handle_IRQ((x) - 1, regs)
+#define flip_tp(x)		do { } while (0)
+
+asmlinkage void __exception_irq_entry brcmstb_handle_irq(struct pt_regs *regs)
+{
+	u32 pend, shift;
+
+	pend = __raw_readl(IRQWD(0) + 0x00) & ~__raw_readl(IRQWD(0) + 0x0c);
+	while ((shift = ffs(pend)) != 0) {
+		pend ^= (1 << (shift - 1));
+		do_IRQ(shift);
+		flip_tp(shift);
+	}
+
+	pend = __raw_readl(IRQWD(32) + 0x00) & ~__raw_readl(IRQWD(32) + 0x0c);
+	while ((shift = ffs(pend)) != 0) {
+		pend ^= (1 << (shift - 1));
+		shift += 32;
+		do_IRQ(shift);
+		flip_tp(shift);
+	}
+
+	pend = __raw_readl(IRQWD(64) + 0x00) & ~__raw_readl(IRQWD(64) + 0x0c);
+	while ((shift = ffs(pend)) != 0) {
+		pend ^= (1 << (shift - 1));
+		shift += 64;
+		do_IRQ(shift);
+		flip_tp(shift);
+	}
+}
+
+#define BPHYSADDR(x)		((x) + 0xe0000000)
+
+static struct resource irq_resource = {
+	.name	= "HIF_L1",
+	.start	= BPHYSADDR(0x0041a400),
+	.end	= BPHYSADDR(0x0041a42f),
+};
+
+void __init brcmstb_init_irq(void)
+{
+	int i, n;
+
+	request_resource(&iomem_resource, &irq_resource);
+
+	for (n = 0; n < NR_IRQS; n += 32) {
+		__raw_writel(0xffffffff, IRQWD(n) + 0x18);
+
+		for (i = n; (i < (n + 32)) && (i < NR_IRQS); i++) {
+			irq_set_chip_and_handler(i, &brcmstb_internal_irq_chip,
+						 handle_level_irq);
+			//irq_set_chip_data(i, base);
+			set_irq_flags(i, IRQF_VALID);
+		}
+	}
+}
+
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 5ce8029..cc008f2 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -5,6 +5,7 @@ platforms += ar7
 platforms += ath79
 platforms += bcm47xx
 platforms += bcm63xx
+platforms += brcmstb
 platforms += cavium-octeon
 platforms += cobalt
 platforms += dec
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 7d36f6e..b841bbb 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -121,6 +121,11 @@ config BCM63XX
 	help
 	 Support for BCM63XX based boards
 
+config BRCMSTB
+	bool "Broadcom BCM7XXX based boards"
+	help
+	  Support for BCM7XXX based boards
+
 config MIPS_COBALT
 	bool "Cobalt Server"
 	select CEVT_R4K
@@ -235,6 +240,7 @@ config LANTIQ
 config LASAT
 	bool "LASAT Networks platforms"
 	select CEVT_R4K
+	select CRC32
 	select CSRC_R4K
 	select DMA_NONCOHERENT
 	select SYS_HAS_EARLY_PRINTK
@@ -508,6 +514,7 @@ config SGI_IP28
 	# select SYS_HAS_EARLY_PRINTK
 	select SYS_SUPPORTS_64BIT_KERNEL
 	select SYS_SUPPORTS_BIG_ENDIAN
+	select MIPS_L1_CACHE_SHIFT_7
       help
         This is the SGI Indigo2 with R10000 processor.  To compile a Linux
         kernel that runs on these, say Y here.
@@ -834,6 +841,8 @@ source "arch/mips/netlogic/Kconfig"
 
 endmenu
 
+source "drivers/brcmstb/Kconfig"
+
 config RWSEM_GENERIC_SPINLOCK
 	bool
 	default y
@@ -1161,8 +1170,10 @@ config BOOT_ELF32
 config MIPS_L1_CACHE_SHIFT
 	int
 	default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL
+	default "7" if BRCM_ZSCM_L2
 	default "6" if MIPS_CPU_SCACHE
 	default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
+	default "6" if CPU_BMIPS4380
 	default "5"
 
 config HAVE_STD_PC_SERIAL_PORT
@@ -1433,6 +1444,7 @@ config CPU_CAVIUM_OCTEON
 	select WEAK_ORDERING
 	select CPU_SUPPORTS_HIGHMEM
 	select CPU_SUPPORTS_HUGEPAGES
+	select ARCH_SPARSEMEM_ENABLE
 	help
 	  The Cavium Octeon processor is a highly integrated chip containing
 	  many ethernet hardware widgets for networking tasks. The processor
@@ -1472,6 +1484,7 @@ config CPU_BMIPS5000
 	select MIPS_CPU_SCACHE
 	select SYS_SUPPORTS_SMP
 	select SYS_SUPPORTS_HOTPLUG_CPU
+	select MIPS_PERF_SHARED_TC_COUNTERS
 	help
 	  Broadcom BMIPS5000 processors.
 
@@ -1787,10 +1800,12 @@ endchoice
 
 config FORCE_MAX_ZONEORDER
 	int "Maximum zone order"
-	range 13 64 if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_32KB
-	default "13" if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_32KB
-	range 12 64 if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_16KB
-	default "12" if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_16KB
+	range 14 64 if HUGETLB_PAGE && PAGE_SIZE_64KB
+	default "14" if HUGETLB_PAGE && PAGE_SIZE_64KB
+	range 13 64 if HUGETLB_PAGE && PAGE_SIZE_32KB
+	default "13" if HUGETLB_PAGE && PAGE_SIZE_32KB
+	range 12 64 if HUGETLB_PAGE && PAGE_SIZE_16KB
+	default "12" if HUGETLB_PAGE && PAGE_SIZE_16KB
 	range 11 64
 	default "11"
 	help
@@ -1862,6 +1877,7 @@ config MIPS_MT_SMP
 	select SYS_SUPPORTS_SCHED_SMT if SMP
 	select SYS_SUPPORTS_SMP
 	select SMP_UP
+	select MIPS_PERF_SHARED_TC_COUNTERS
 	help
 	  This is a kernel model which is known a VSMP but lately has been
 	  marketesed into SMVP.
@@ -1986,6 +2002,7 @@ config MIPS_APSP_KSPD
 config MIPS_CMP
 	bool "MIPS CMP framework support"
 	depends on SYS_SUPPORTS_MIPS_CMP
+	select SMP
 	select SYNC_R4K
 	select SYS_SUPPORTS_SMP
 	select SYS_SUPPORTS_SCHED_SMT if SMP
@@ -2215,6 +2232,9 @@ config NR_CPUS
 	  performance should round up your number of processors to the next
 	  power of two.
 
+config MIPS_PERF_SHARED_TC_COUNTERS
+       bool
+
 source "kernel/time/Kconfig"
 
 #
@@ -2324,6 +2344,19 @@ config SECCOMP
 
 	  If unsure, say Y. Only embedded should say N here.
 
+config CC_STACKPROTECTOR
+	bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
+	help
+	  This option turns on the -fstack-protector GCC feature. This
+	  feature puts, at the beginning of functions, a canary value on
+	  the stack just before the return address, and validates
+	  the value just before actually returning.  Stack based buffer
+	  overflows (that need to overwrite this return address) now also
+	  overwrite the canary, which gets detected and the attack is then
+	  neutralized via a kernel panic.
+
+	  This feature requires gcc version 4.2 or above.
+
 config USE_OF
 	bool "Flattened Device Tree support"
 	select OF
diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index 83ed00a..e18a947 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -56,6 +56,14 @@ config CMDLINE
 	  For more information, see the CMDLINE_BOOL and CMDLINE_OVERRIDE
 	  options.
 
+config CMDLINE_EXTEND
+	bool "Extend bootloader kernel arguments"
+	default y
+	depends on CMDLINE_BOOL
+	help
+	  The command-line arguments provided by the boot loader will be
+	  appended to the default kernel command string.
+
 config CMDLINE_OVERRIDE
 	bool "Built-in command line overrides firware arguments"
 	default n
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 5c1e75d..130e264 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -93,6 +93,15 @@ LDFLAGS_vmlinux			+= -G 0 -static -n -nostdlib
 KBUILD_AFLAGS_MODULE		+= -mlong-calls
 KBUILD_CFLAGS_MODULE		+= -mlong-calls
 
+#
+# pass -msoft-float to GAS if it supports it.  However on newer binutils
+# (specifically newer than 2.24.51.20140728) we then also need to explicitly
+# set ".set hardfloat" in all files which manipulate floating point registers.
+#
+ifneq ($(call as-option,-Wa$(comma)-msoft-float,),)
+	cflags-y		+= -DGAS_HAS_SET_HARDFLOAT -Wa,-msoft-float
+endif
+
 cflags-y += -ffreestanding
 
 #
@@ -165,8 +174,12 @@ cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS)	+= $(call cc-option,-mno-daddi,)
 
 ifdef CONFIG_CPU_SB1
 ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
-KBUILD_AFLAGS_MODULE += -msb1-pass1-workarounds
-KBUILD_CFLAGS_MODULE += -msb1-pass1-workarounds
+#
+# -msb1-pass1-workarounds is only supported by Broadcom's Montavista toolchain
+# but not FSF gcc.
+#
+KBUILD_AFLAGS_MODULE += $(call cc-option,-msb1-pass1-workarounds)
+KBUILD_CFLAGS_MODULE += $(call cc-option,-msb1-pass1-workarounds)
 endif
 endif
 
@@ -224,6 +237,10 @@ KBUILD_CPPFLAGS += -D"DATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)"
 
 LDFLAGS			+= -m $(ld-emul)
 
+ifdef CONFIG_CC_STACKPROTECTOR
+  KBUILD_CFLAGS += -fstack-protector
+endif
+
 ifdef CONFIG_MIPS
 CHECKFLAGS += $(shell $(CC) $(KBUILD_CFLAGS) -dM -E -x c /dev/null | \
 	egrep -vw '__GNUC_(|MINOR_|PATCHLEVEL_)_' | \
diff --git a/arch/mips/alchemy/board-gpr.c b/arch/mips/alchemy/board-gpr.c
index ba32590..6b88675 100644
--- a/arch/mips/alchemy/board-gpr.c
+++ b/arch/mips/alchemy/board-gpr.c
@@ -52,10 +52,8 @@ void __init prom_init(void)
 	prom_init_cmdline();
 
 	memsize_str = prom_getenv("memsize");
-	if (!memsize_str)
+	if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
 		memsize = 0x04000000;
-	else
-		strict_strtoul(memsize_str, 0, &memsize);
 	add_memory_region(0, memsize, BOOT_MEM_RAM);
 }
 
diff --git a/arch/mips/alchemy/board-mtx1.c b/arch/mips/alchemy/board-mtx1.c
index 295f1a9..189c018 100644
--- a/arch/mips/alchemy/board-mtx1.c
+++ b/arch/mips/alchemy/board-mtx1.c
@@ -52,10 +52,8 @@ void __init prom_init(void)
 	prom_init_cmdline();
 
 	memsize_str = prom_getenv("memsize");
-	if (!memsize_str)
+	if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
 		memsize = 0x04000000;
-	else
-		strict_strtoul(memsize_str, 0, &memsize);
 	add_memory_region(0, memsize, BOOT_MEM_RAM);
 }
 
diff --git a/arch/mips/alchemy/devboards/db1000.c b/arch/mips/alchemy/devboards/db1000.c
index 1b81dbf..d74b65a 100644
--- a/arch/mips/alchemy/devboards/db1000.c
+++ b/arch/mips/alchemy/devboards/db1000.c
@@ -504,13 +504,10 @@ static int __init db1000_dev_init(void)
 		s0 = AU1100_GPIO1_INT;
 		s1 = AU1100_GPIO4_INT;
 
+		gpio_request(19, "sd0_cd");
+		gpio_request(20, "sd1_cd");
 		gpio_direction_input(19);	/* sd0 cd# */
 		gpio_direction_input(20);	/* sd1 cd# */
-		gpio_direction_input(21);	/* touch pendown# */
-		gpio_direction_input(207);	/* SPI MISO */
-		gpio_direction_output(208, 0);	/* SPI MOSI */
-		gpio_direction_output(209, 1);	/* SPI SCK */
-		gpio_direction_output(210, 1);	/* SPI CS# */
 
 		/* spi_gpio on SSI0 pins */
 		pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
diff --git a/arch/mips/ath79/early_printk.c b/arch/mips/ath79/early_printk.c
index 6a51ced..208dda4 100644
--- a/arch/mips/ath79/early_printk.c
+++ b/arch/mips/ath79/early_printk.c
@@ -31,13 +31,15 @@ static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val)
 	} while (1);
 }
 
+#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
+
 static void prom_putchar_ar71xx(unsigned char ch)
 {
 	void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE));
 
-	prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
+	prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY);
 	__raw_writel(ch, base + UART_TX * 4);
-	prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
+	prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY);
 }
 
 static void prom_putchar_ar933x(unsigned char ch)
diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile
index 6dfdc69..4049cd5 100644
--- a/arch/mips/bcm63xx/Makefile
+++ b/arch/mips/bcm63xx/Makefile
@@ -1,5 +1,6 @@
 obj-y		+= clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
-		   dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o
+		   dev-dsp.o dev-enet.o dev-pcmcia.o dev-spi.o dev-uart.o \
+		   dev-wdt.o
 obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
 
 obj-y		+= boards/
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index 2f1773f..ea65c0f 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -25,6 +25,7 @@
 #include <bcm63xx_dev_enet.h>
 #include <bcm63xx_dev_dsp.h>
 #include <bcm63xx_dev_pcmcia.h>
+#include <bcm63xx_dev_spi.h>
 #include <board_bcm963xx.h>
 
 #define PFX	"board_bcm963xx: "
@@ -890,6 +891,8 @@ int __init board_register_devices(void)
 	}
 #endif
 
+	bcm63xx_spi_register();
+
 	/* read base address of boot chip select (0) */
 	val = bcm_mpi_readl(MPI_CSBASE_REG(0));
 	val &= MPI_CSBASE_BASE_MASK;
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index 9d57c71..be49b9a 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -120,7 +120,7 @@ static void enetsw_set(struct clk *clk, int enable)
 {
 	if (!BCMCPU_IS_6368())
 		return;
-	bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN |
+	bcm_hwclock_set(CKCTL_6368_ROBOSW_EN |
 			CKCTL_6368_SWPKT_USB_EN |
 			CKCTL_6368_SWPKT_SAR_EN, enable);
 	if (enable) {
@@ -163,7 +163,7 @@ static void usbh_set(struct clk *clk, int enable)
 	if (BCMCPU_IS_6348())
 		bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
 	else if (BCMCPU_IS_6368())
-		bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable);
+		bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
 }
 
 static struct clk clk_usbh = {
@@ -181,9 +181,11 @@ static void spi_set(struct clk *clk, int enable)
 		mask = CKCTL_6338_SPI_EN;
 	else if (BCMCPU_IS_6348())
 		mask = CKCTL_6348_SPI_EN;
-	else
-		/* BCMCPU_IS_6358 */
+	else if (BCMCPU_IS_6358())
 		mask = CKCTL_6358_SPI_EN;
+	else
+		/* BCMCPU_IS_6368 */
+		mask = CKCTL_6368_SPI_EN;
 	bcm_hwclock_set(mask, enable);
 }
 
@@ -199,7 +201,7 @@ static void xtm_set(struct clk *clk, int enable)
 	if (!BCMCPU_IS_6368())
 		return;
 
-	bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN |
+	bcm_hwclock_set(CKCTL_6368_SAR_EN |
 			CKCTL_6368_SWPKT_SAR_EN, enable);
 
 	if (enable) {
diff --git a/arch/mips/bcm63xx/dev-spi.c b/arch/mips/bcm63xx/dev-spi.c
new file mode 100644
index 0000000..67fa45b
--- /dev/null
+++ b/arch/mips/bcm63xx/dev-spi.c
@@ -0,0 +1,119 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2009-2011 Florian Fainelli <florian@openwrt.org>
+ * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/export.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+
+#include <bcm63xx_cpu.h>
+#include <bcm63xx_dev_spi.h>
+#include <bcm63xx_regs.h>
+
+#ifdef BCMCPU_RUNTIME_DETECT
+/*
+ * register offsets
+ */
+static const unsigned long bcm6338_regs_spi[] = {
+	__GEN_SPI_REGS_TABLE(6338)
+};
+
+static const unsigned long bcm6348_regs_spi[] = {
+	__GEN_SPI_REGS_TABLE(6348)
+};
+
+static const unsigned long bcm6358_regs_spi[] = {
+	__GEN_SPI_REGS_TABLE(6358)
+};
+
+static const unsigned long bcm6368_regs_spi[] = {
+	__GEN_SPI_REGS_TABLE(6368)
+};
+
+const unsigned long *bcm63xx_regs_spi;
+EXPORT_SYMBOL(bcm63xx_regs_spi);
+
+static __init void bcm63xx_spi_regs_init(void)
+{
+	if (BCMCPU_IS_6338())
+		bcm63xx_regs_spi = bcm6338_regs_spi;
+	if (BCMCPU_IS_6348())
+		bcm63xx_regs_spi = bcm6348_regs_spi;
+	if (BCMCPU_IS_6358())
+		bcm63xx_regs_spi = bcm6358_regs_spi;
+	if (BCMCPU_IS_6368())
+		bcm63xx_regs_spi = bcm6368_regs_spi;
+}
+#else
+static __init void bcm63xx_spi_regs_init(void) { }
+#endif
+
+static struct resource spi_resources[] = {
+	{
+		.start		= -1, /* filled at runtime */
+		.end		= -1, /* filled at runtime */
+		.flags		= IORESOURCE_MEM,
+	},
+	{
+		.start		= -1, /* filled at runtime */
+		.flags		= IORESOURCE_IRQ,
+	},
+};
+
+static struct bcm63xx_spi_pdata spi_pdata = {
+	.bus_num		= 0,
+	.num_chipselect		= 8,
+};
+
+static struct platform_device bcm63xx_spi_device = {
+	.name		= "bcm63xx-spi",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(spi_resources),
+	.resource	= spi_resources,
+	.dev		= {
+		.platform_data = &spi_pdata,
+	},
+};
+
+int __init bcm63xx_spi_register(void)
+{
+	struct clk *periph_clk;
+
+	if (BCMCPU_IS_6345())
+		return -ENODEV;
+
+	periph_clk = clk_get(NULL, "periph");
+	if (IS_ERR(periph_clk)) {
+		pr_err("unable to get periph clock\n");
+		return -ENODEV;
+	}
+
+	/* Set bus frequency */
+	spi_pdata.speed_hz = clk_get_rate(periph_clk);
+
+	spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
+	spi_resources[0].end = spi_resources[0].start;
+	spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
+
+	if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
+		spi_resources[0].end += BCM_6338_RSET_SPI_SIZE - 1;
+		spi_pdata.fifo_size = SPI_6338_MSG_DATA_SIZE;
+	}
+
+	if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
+		spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
+		spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
+	}
+
+	bcm63xx_spi_regs_init();
+
+	return platform_device_register(&bcm63xx_spi_device);
+}
diff --git a/arch/mips/bcm63xx/early_printk.c b/arch/mips/bcm63xx/early_printk.c
index bf353c9..aa8f7f9 100644
--- a/arch/mips/bcm63xx/early_printk.c
+++ b/arch/mips/bcm63xx/early_printk.c
@@ -10,7 +10,7 @@
 #include <bcm63xx_io.h>
 #include <bcm63xx_regs.h>
 
-static void __init wait_xfered(void)
+static void wait_xfered(void)
 {
 	unsigned int val;
 
@@ -22,7 +22,7 @@ static void __init wait_xfered(void)
 	} while (1);
 }
 
-void __init prom_putchar(char c)
+void prom_putchar(char c)
 {
 	wait_xfered();
 	bcm_uart0_writel(c, UART_FIFO_REG);
diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile
index 5042d51..21450c6 100644
--- a/arch/mips/boot/compressed/Makefile
+++ b/arch/mips/boot/compressed/Makefile
@@ -18,6 +18,8 @@ BOOT_HEAP_SIZE := 0x400000
 # Disable Function Tracer
 KBUILD_CFLAGS := $(shell echo $(KBUILD_CFLAGS) | sed -e "s/-pg//")
 
+KBUILD_CFLAGS := $(filter-out -fstack-protector, $(KBUILD_CFLAGS))
+
 KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \
 	-DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) -D"VMLINUX_LOAD_ADDRESS_ULL=$(VMLINUX_LOAD_ADDRESS)ull"
 
diff --git a/arch/mips/boot/elf2ecoff.c b/arch/mips/boot/elf2ecoff.c
index e19d906..7a91d8c 100644
--- a/arch/mips/boot/elf2ecoff.c
+++ b/arch/mips/boot/elf2ecoff.c
@@ -49,7 +49,8 @@
 /*
  * Some extra ELF definitions
  */
-#define PT_MIPS_REGINFO 0x70000000	/* Register usage information */
+#define PT_MIPS_REGINFO 	0x70000000	/* Register usage information */
+#define PT_MIPS_ABIFLAGS	0x70000003	/* Records ABI related flags  */
 
 /* -------------------------------------------------------------------- */
 
@@ -267,7 +268,6 @@ int main(int argc, char *argv[])
 	Elf32_Ehdr ex;
 	Elf32_Phdr *ph;
 	Elf32_Shdr *sh;
-	char *shstrtab;
 	int i, pad;
 	struct sect text, data, bss;
 	struct filehdr efh;
@@ -335,9 +335,6 @@ int main(int argc, char *argv[])
 				     "sh");
 	if (must_convert_endian)
 		convert_elf_shdrs(sh, ex.e_shnum);
-	/* Read in the section string table. */
-	shstrtab = saveRead(infile, sh[ex.e_shstrndx].sh_offset,
-			    sh[ex.e_shstrndx].sh_size, "shstrtab");
 
 	/* Figure out if we can cram the program header into an ECOFF
 	   header...  Basically, we can't handle anything but loadable
@@ -349,39 +346,46 @@ int main(int argc, char *argv[])
 
 	for (i = 0; i < ex.e_phnum; i++) {
 		/* Section types we can ignore... */
-		if (ph[i].p_type == PT_NULL || ph[i].p_type == PT_NOTE ||
-		    ph[i].p_type == PT_PHDR
-		    || ph[i].p_type == PT_MIPS_REGINFO)
+		switch (ph[i].p_type) {
+		case PT_NULL:
+		case PT_NOTE:
+		case PT_PHDR:
+		case PT_MIPS_REGINFO:
+		case PT_MIPS_ABIFLAGS:
 			continue;
-		/* Section types we can't handle... */
-		else if (ph[i].p_type != PT_LOAD) {
-			fprintf(stderr,
-				"Program header %d type %d can't be converted.\n",
-				ex.e_phnum, ph[i].p_type);
-			exit(1);
-		}
-		/* Writable (data) segment? */
-		if (ph[i].p_flags & PF_W) {
-			struct sect ndata, nbss;
 
-			ndata.vaddr = ph[i].p_vaddr;
-			ndata.len = ph[i].p_filesz;
-			nbss.vaddr = ph[i].p_vaddr + ph[i].p_filesz;
-			nbss.len = ph[i].p_memsz - ph[i].p_filesz;
+		case PT_LOAD:
+			/* Writable (data) segment? */
+			if (ph[i].p_flags & PF_W) {
+				struct sect ndata, nbss;
+
+				ndata.vaddr = ph[i].p_vaddr;
+				ndata.len = ph[i].p_filesz;
+				nbss.vaddr = ph[i].p_vaddr + ph[i].p_filesz;
+				nbss.len = ph[i].p_memsz - ph[i].p_filesz;
 
-			combine(&data, &ndata, 0);
-			combine(&bss, &nbss, 1);
-		} else {
-			struct sect ntxt;
+				combine(&data, &ndata, 0);
+				combine(&bss, &nbss, 1);
+			} else {
+				struct sect ntxt;
 
-			ntxt.vaddr = ph[i].p_vaddr;
-			ntxt.len = ph[i].p_filesz;
+				ntxt.vaddr = ph[i].p_vaddr;
+				ntxt.len = ph[i].p_filesz;
 
-			combine(&text, &ntxt, 0);
+				combine(&text, &ntxt, 0);
+			}
+			/* Remember the lowest segment start address. */
+			if (ph[i].p_vaddr < cur_vma)
+				cur_vma = ph[i].p_vaddr;
+			break;
+
+		default:
+			/* Section types we can't handle... */
+			fprintf(stderr,
+				"Program header %d type %d can't be converted.\n",
+				ex.e_phnum, ph[i].p_type);
+			exit(1);
 		}
-		/* Remember the lowest segment start address. */
-		if (ph[i].p_vaddr < cur_vma)
-			cur_vma = ph[i].p_vaddr;
 	}
 
 	/* Sections must be in order to be converted... */
diff --git a/arch/mips/brcmstb/Makefile b/arch/mips/brcmstb/Makefile
new file mode 100644
index 0000000..182bd8f
--- /dev/null
+++ b/arch/mips/brcmstb/Makefile
@@ -0,0 +1,2 @@
+obj-y			+= prom.o bmips.o memory.o irq.o time.o standby.o s3_standby.o
+obj-$(CONFIG_BCM7435) += bmips_5xxx_init.o
diff --git a/arch/mips/brcmstb/Platform b/arch/mips/brcmstb/Platform
new file mode 100644
index 0000000..d1f844e
--- /dev/null
+++ b/arch/mips/brcmstb/Platform
@@ -0,0 +1,8 @@
+#
+# Broadcom set-top platforms
+#
+platform-$(CONFIG_BRCMSTB)	+= brcmstb/
+cflags-$(CONFIG_BRCMSTB)	+= -I$(srctree)/arch/mips/include/asm/mach-brcmstb -Wno-error=array-bounds
+load-$(CONFIG_BRCMSTB)		+= 0x80001000
+
+cflags-$(CONFIG_NO_INLINE)	+= -fno-inline
diff --git a/arch/mips/brcmstb/bmips.c b/arch/mips/brcmstb/bmips.c
new file mode 100644
index 0000000..8fc1380
--- /dev/null
+++ b/arch/mips/brcmstb/bmips.c
@@ -0,0 +1,596 @@
+/*
+ * Copyright (C) 2012 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/dma-mapping.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/bitops.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/compiler.h>
+
+#include <asm/cpu-info.h>
+#include <asm/mipsregs.h>
+#include <asm/barrier.h>
+#include <asm/cacheflush.h>
+#include <asm/r4kcache.h>
+#include <asm/asm-offsets.h>
+#include <asm/inst.h>
+#include <asm/fpu.h>
+#include <asm/hazards.h>
+#include <asm/cpu-features.h>
+#include <linux/brcmstb/brcmstb.h>
+#include <dma-coherence.h>
+
+/***********************************************************************
+ * MIPS features, caches, and bus interface
+ ***********************************************************************/
+
+void brcmstb_cpu_setup(void)
+{
+#if   defined(CONFIG_CPU_BMIPS3300)
+
+	unsigned long cbr = __BMIPS_GET_CBR();
+
+	/* Set BIU to async mode */
+	set_c0_brcm_bus_pll(BIT(22));
+	__sync();
+
+#ifdef BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT
+	/* Enable write gathering */
+	BDEV_WR_RB(BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT, 0x264);
+
+	/* Enable split mode */
+	BDEV_WR_RB(BCHP_MISB_BRIDGE_MISB_SPLIT_MODE, 0x1);
+	__sync();
+#endif
+
+	/* put the BIU back in sync mode */
+	clear_c0_brcm_bus_pll(BIT(22));
+
+	/* clear BHTD to enable branch history table */
+	clear_c0_brcm_reset(BIT(16));
+
+	/* Flush and enable RAC */
+	DEV_WR_RB(cbr + BMIPS_RAC_CONFIG, 0x100);
+	DEV_WR_RB(cbr + BMIPS_RAC_CONFIG, 0xf);
+	DEV_WR_RB(cbr + BMIPS_RAC_ADDRESS_RANGE, 0x0fff0000);
+
+#elif defined(CONFIG_CPU_BMIPS4380)
+
+	unsigned long cbr = __BMIPS_GET_CBR();
+
+	/* CRBMIPS438X-164: CBG workaround */
+	switch (read_c0_prid()) {
+	case 0x2a040:
+	case 0x2a042:
+	case 0x2a044:
+	case 0x2a060:
+		DEV_UNSET(cbr + BMIPS_L2_CONFIG, 0x07000000);
+	}
+
+	/* clear BHTD to enable branch history table */
+	clear_c0_brcm_config_0(BIT(21));
+
+	/* XI/ROTR enable */
+	if (kernel_uses_smartmips_rixi) {
+		set_c0_brcm_config_0(BIT(23));
+		set_c0_brcm_cmt_ctrl(BIT(15));
+	}
+
+#elif defined(CONFIG_CPU_BMIPS5000)
+
+	/* enable RDHWR, BRDHWR */
+	set_c0_brcm_config(BIT(17) | BIT(21));
+
+	/* Disable JTB */
+	__asm__ __volatile__(
+	"	.set	noreorder\n"
+	"	li	$8, 0x5a455048\n"
+	"	.word	0x4088b00f\n"	/* mtc0	t0, $22, 15 */
+	"	.word	0x4008b008\n"	/* mfc0	t0, $22, 8 */
+	"	li	$9, 0x00008000\n"
+	"	or	$8, $8, $9\n"
+	"	.word	0x4088b008\n"	/* mtc0	t0, $22, 8 */
+	"	sync\n"
+	"	li	$8, 0x0\n"
+	"	.word	0x4088b00f\n"	/* mtc0	t0, $22, 15 */
+	"	.set	reorder\n"
+	: : : "$8", "$9");
+
+	if (kernel_uses_smartmips_rixi) {
+		/* XI enable */
+		set_c0_brcm_config(BIT(27));
+
+		/* enable MIPS32R2 ROR instruction for XI TLB handlers */
+		__asm__ __volatile__(
+		"	li	$8, 0x5a455048\n"
+		"	.word	0x4088b00f\n"	/* mtc0 $8, $22, 15 */
+		"	nop; nop; nop\n"
+		"	.word	0x4008b008\n"	/* mfc0 $8, $22, 8 */
+		"	lui	$9, 0x0100\n"
+		"	or	$8, $9\n"
+#if defined(CONFIG_BCM7425) || defined(CONFIG_BCM7344) || \
+	defined(CONFIG_BCM7346)
+		/* SWLINUX-2712: disable "pref 30" on buggy CPUs */
+		"	lui	$9, 0x0800\n"
+		"	or	$8, $9\n"
+#endif
+		"	.word	0x4088b008\n"	/* mtc0 $8, $22, 8 */
+		: : : "$8", "$9");
+	}
+
+#endif
+}
+
+/***********************************************************************
+ * Simulate privileged instructions (RDHWR, MFC0) and unaligned accesses
+ ***********************************************************************/
+
+#define OPCODE 0xfc000000
+#define BASE   0x03e00000
+#define RT     0x001f0000
+#define OFFSET 0x0000ffff
+#define LL     0xc0000000
+#define SC     0xe0000000
+#define SPEC0  0x00000000
+#define SPEC3  0x7c000000
+#define RD     0x0000f800
+#define FUNC   0x0000003f
+#define SYNC   0x0000000f
+#define RDHWR  0x0000003b
+
+#define BRDHWR 0xec000000
+#define OP_MFC0 0x40000000
+
+int brcm_simulate_opcode(struct pt_regs *regs, unsigned int opcode)
+{
+	struct thread_info *ti = task_thread_info(current);
+	int rd = (opcode & RD) >> 11;
+	int rt = (opcode & RT) >> 16;
+
+	/* PR34054: use alternate RDHWR instruction encoding */
+	if (((opcode & OPCODE) == BRDHWR && (opcode & FUNC) == RDHWR)
+	    || ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR)) {
+
+		if (rd == 29) {
+			regs->regs[rt] = ti->tp_value;
+			atomic_inc(&brcm_rdhwr_count);
+			return 0;
+		}
+	}
+
+	/* emulate MFC0 $15 for optimized memcpy() CPU detection */
+	if ((opcode & OPCODE) == OP_MFC0 &&
+	    (opcode & OFFSET) == (15 << 11)) {
+		regs->regs[rt] = read_c0_prid();
+		return 0;
+	}
+
+	return -1;	/* unhandled */
+}
+
+int brcm_unaligned_fp(void __user *addr, union mips_instruction *insn,
+	struct pt_regs *regs)
+{
+	unsigned int op = insn->i_format.opcode;
+	unsigned int rt = insn->i_format.rt;
+	unsigned int res;
+	int wordlen = 8;
+
+	/* on r4k, only the even slots ($f0, $f2, ...) are used */
+	u8 *fprptr = (u8 *)current + THREAD_FPR0 + (rt >> 1) *
+		(THREAD_FPR2 - THREAD_FPR0);
+
+	if (op == lwc1_op || op == swc1_op) {
+		wordlen = 4;
+#ifdef __LITTLE_ENDIAN
+		/* LE: LSW ($f0) precedes MSW ($f1) */
+		fprptr += (rt & 1) ? 4 : 0;
+#else
+		/* BE: MSW ($f1) precedes LSW ($f0) */
+		fprptr += (rt & 1) ? 0 : 4;
+#endif
+	}
+
+	preempt_disable();
+	if (is_fpu_owner())
+		save_fp(current);
+	else
+		own_fpu(1);
+
+	if (op == lwc1_op || op == ldc1_op) {
+		if (!access_ok(VERIFY_READ, addr, wordlen))
+			goto sigbus;
+		/*
+		 * FPR load: copy from user struct to kernel saved
+		 * register struct, then restore all FPRs
+		 */
+		__asm__ __volatile__ (
+		"1:	lb	%0, 0(%3)\n"
+		"	sb	%0, 0(%2)\n"
+		"	addiu	%2, 1\n"
+		"	addiu	%3, 1\n"
+		"	addiu	%1, -1\n"
+		"	bnez	%1, 1b\n"
+		"	li	%0, 0\n"
+		"3:\n"
+		"	.section .fixup,\"ax\"\n"
+		"4:	li	%0, %4\n"
+		"	j	3b\n"
+		"	.previous\n"
+		"	.section __ex_table,\"a\"\n"
+		STR(PTR)" 1b,4b\n"
+		"	.previous\n"
+			: "=&r" (res), "+r" (wordlen),
+			  "+r" (fprptr), "+r" (addr)
+			: "i" (-EFAULT));
+		if (res)
+			goto fault;
+
+		restore_fp(current);
+	} else {
+		if (!access_ok(VERIFY_WRITE, addr, wordlen))
+			goto sigbus;
+		/*
+		 * FPR store: copy from kernel saved register struct
+		 * to user struct
+		 */
+		__asm__ __volatile__ (
+		"2:	lb	%0, 0(%2)\n"
+		"1:	sb	%0, 0(%3)\n"
+		"	addiu	%2, 1\n"
+		"	addiu	%3, 1\n"
+		"	addiu	%1, -1\n"
+		"	bnez	%1, 2b\n"
+		"	li	%0, 0\n"
+		"3:\n"
+		"	.section .fixup,\"ax\"\n"
+		"4:	li	%0, %4\n"
+		"	j	3b\n"
+		"	.previous\n"
+		"	.section __ex_table,\"a\"\n"
+		STR(PTR)" 1b,4b\n"
+		"	.previous\n"
+			: "=&r" (res), "+r" (wordlen),
+			  "+r" (fprptr), "+r" (addr)
+			: "i" (-EFAULT));
+		if (res)
+			goto fault;
+	}
+	preempt_enable();
+
+	atomic_inc(&brcm_unaligned_fp_count);
+	return 0;
+
+sigbus:
+	preempt_enable();
+	return -EINVAL;
+
+fault:
+	preempt_enable();
+	return -EFAULT;
+}
+
+/***********************************************************************
+ * CPU divisor / PLL manipulation
+ ***********************************************************************/
+/*
+ * 0: CP0 COUNT/COMPARE frequency depends on divisor
+ * 1: CP0 COUNT/COMPARE frequency does not depend on divisor
+ */
+static int fixed_counter_freq;
+
+#if defined(CONFIG_BCM7425B0) || defined(CONFIG_BCM7344B0) || \
+	defined(CONFIG_BCM7346B0)
+/* SWLINUX-2063: MIPS cannot enter divide-by-N mode */
+#define	BROKEN_MIPS_DIVIDER
+#endif
+
+/* MIPS active standby on 7550 */
+#define CPU_PLL_MODE1		216000
+
+/*
+ * current ADJUSTED base frequency (reflects the current PLL settings)
+ * brcm_cpu_khz (in time.c) always has the ORIGINAL clock frequency and
+ *   is never changed after bootup
+ */
+unsigned long brcm_adj_cpu_khz;
+
+/* multiplier used in brcm_fixup_ticks to scale the # of ticks
+ * 0               - no fixup needed
+ * any other value - factor * 2^16 */
+static unsigned long fixup_ticks_ratio;
+
+/* current CPU divisor, as set by the user */
+static __maybe_unused int cpu_div = 1;
+
+/*
+ * MIPS clockevent code always assumes the original boot-time CP0 clock rate.
+ * This function scales the number of ticks according to the current HW
+ * settings.
+ */
+unsigned long brcm_fixup_ticks(unsigned long delta)
+{
+	unsigned long long tmp = delta;
+
+	if (unlikely(!brcm_adj_cpu_khz))
+		brcm_adj_cpu_khz = brcm_cpu_khz;
+
+	if (likely(!fixup_ticks_ratio))
+		return delta;
+
+	tmp *= fixup_ticks_ratio;
+	tmp >>= 16;
+
+	return (unsigned long)tmp;
+}
+
+static unsigned int orig_udelay_val[NR_CPUS];
+
+struct spd_change {
+	int			old_div;
+	int			new_div;
+	int			old_base;
+	int			new_base;
+};
+
+void brcm_set_cpu_speed(void *arg)
+{
+	struct spd_change *c = arg;
+	uint32_t new_div = (uint32_t)c->new_div;
+	unsigned long __maybe_unused count, compare, delta;
+	signed long sdelta;
+	int cpu = smp_processor_id();
+	uint32_t __maybe_unused tmp0, tmp1, tmp2, tmp3;
+
+	/* scale udelay_val */
+	if (!orig_udelay_val[cpu])
+		orig_udelay_val[cpu] = current_cpu_data.udelay_val;
+
+	if (c->new_base == brcm_cpu_khz)
+		current_cpu_data.udelay_val = orig_udelay_val[cpu] / new_div;
+	else
+		current_cpu_data.udelay_val =
+			(unsigned long long)orig_udelay_val[cpu] *
+			c->new_base / (new_div * c->old_base);
+
+	/* scale any pending timer events */
+	compare = read_c0_compare();
+	count = read_c0_count();
+
+	sdelta = (long)compare - (long)count;
+	if (sdelta > 0) {
+		if (!fixed_counter_freq)
+			delta = ((unsigned long long)sdelta *
+				c->old_div * c->new_base) /
+				(new_div * c->old_base);
+		else
+			delta = ((unsigned long long)sdelta *
+				c->new_base) / c->old_base;
+	write_c0_compare(read_c0_count() + delta);
+	}
+
+	if (cpu != 0)
+		return;
+
+#if defined(CONFIG_BRCM_CPU_PLL)
+	brcm_adj_cpu_khz = c->new_base;
+#if defined(CONFIG_BCM7550)
+	if (brcm_adj_cpu_khz == CPU_PLL_MODE1) {
+		/* 216Mhz */
+		BDEV_WR_RB(BCHP_VCXO_CTL_CONFIG_FSM_PLL_NEXT_CFG_3A,
+			0x801b2806);
+		BDEV_WR_RB(BCHP_VCXO_CTL_CONFIG_FSM_PLL_NEXT_CFG_3B,
+			0x00300618);
+	} else {
+		/* 324Mhz */
+		BDEV_WR_RB(BCHP_VCXO_CTL_CONFIG_FSM_PLL_NEXT_CFG_3A,
+			0x801b2806);
+		BDEV_WR_RB(BCHP_VCXO_CTL_CONFIG_FSM_PLL_NEXT_CFG_3B,
+			0x00300418);
+	}
+	BDEV_WR_RB(BCHP_VCXO_CTL_CONFIG_FSM_PLL_UPDATE, 1);
+#else
+#error CPU PLL adjustment not supported on this chip
+#endif
+#endif
+
+	if ((brcm_adj_cpu_khz == brcm_cpu_khz) &&
+	    (fixed_counter_freq || new_div == 1)) {
+		fixup_ticks_ratio = 0;
+	} else {
+		fixup_ticks_ratio =
+			((unsigned long long)brcm_adj_cpu_khz << 16) /
+			 (unsigned long long)brcm_cpu_khz;
+		if (!fixed_counter_freq)
+			fixup_ticks_ratio /= new_div;
+	}
+
+	printk(KERN_DEBUG "ratio=%lu adj=%lu freq=%lu new_div=%d\n",
+	       fixup_ticks_ratio, brcm_adj_cpu_khz, brcm_cpu_khz, new_div);
+	new_div = ffs(new_div) - 1;
+
+	/* see BMIPS datasheet, CP0 register $22 */
+
+#if defined(CONFIG_CPU_BMIPS3300)
+	change_c0_brcm_bus_pll(0x07 << 22, (new_div << 23) | (0 << 22));
+#elif defined(CONFIG_CPU_BMIPS5000)
+	change_c0_brcm_mode(0x0f << 4, (1 << 7) | (new_div << 4));
+#elif defined(CONFIG_CPU_BMIPS4380)
+	__asm__ __volatile__(
+	"	.set	push\n"
+	"	.set	noreorder\n"
+	"	.set	nomacro\n"
+	"	.set	mips32\n"
+	/* get kseg1 address for CBA into %3 */
+	"	mfc0	%3, $22, 6\n"
+	"	li	%2, 0xfffc0000\n"
+	"	and	%3, %2\n"
+	"	li	%2, 0xa0000000\n"
+	"	add	%3, %2\n"
+	/* %1 = async bit, %2 = mask out everything but 30:28 */
+	"	lui	%1, 0x1000\n"
+	"	lui	%2, 0x8fff\n"
+	"	beqz	%0, 1f\n"
+	"	ori	%2, 0xffff\n"
+	/* handle SYNC to ASYNC */
+	"	sync\n"
+	"	mfc0	%4, $22, 5\n"
+	"	and	%4, %2\n"
+	"	or	%4, %1\n"
+	"	mtc0	%4, $22, 5\n"
+	"	nop\n"
+	"	nop\n"
+	"	lw	%2, 4(%3)\n"
+	"	sw	%2, 4(%3)\n"
+	"	sync\n"
+	"	sll	%0, 29\n"
+	"	or	%4, %0\n"
+	"	mtc0	%4, $22, 5\n"
+	"	nop; nop; nop; nop\n"
+	"	nop; nop; nop; nop\n"
+	"	nop; nop; nop; nop\n"
+	"	nop; nop; nop; nop\n"
+	"	b	2f\n"
+	"	nop\n"
+	/* handle ASYNC to SYNC */
+	"1:\n"
+	"	mfc0	%4, $22, 5\n"
+	"	and	%4, %2\n"
+	"	or	%4, %1\n"
+	"	mtc0	%4, $22, 5\n"
+	"	nop; nop; nop; nop\n"
+	"	nop; nop; nop; nop\n"
+	"	sync\n"
+	"	and	%4, %2\n"
+	"	mtc0	%4, $22, 5\n"
+	"	nop\n"
+	"	nop\n"
+	"	lw	%2, 4(%3)\n"
+	"	sw	%2, 4(%3)\n"
+	"	sync\n"
+	"2:\n"
+	"	.set	pop\n"
+	: "+r" (new_div),
+	  "=&r" (tmp0), "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3));
+#endif
+}
+
+#ifdef CONFIG_BRCM_CPU_DIV
+
+ssize_t brcm_pm_show_cpu_div(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%d\n", cpu_div);
+}
+
+ssize_t brcm_pm_store_cpu_div(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	int val;
+	struct spd_change chg;
+
+	if (sscanf(buf, "%d", &val) != 1)
+		return -EINVAL;
+
+	if (val != 1 && val != 2 && val != 4 && val != 8
+#if defined(CONFIG_CPU_BMIPS5000)
+		&& val != 16
+#endif
+			)
+		return -EINVAL;
+
+#if defined(BROKEN_MIPS_DIVIDER)
+	return val == 1 ? count : -EINVAL;
+#endif
+
+	chg.old_div = cpu_div;
+	chg.new_div = val;
+	chg.old_base = brcm_adj_cpu_khz;
+	chg.new_base = brcm_adj_cpu_khz;
+
+	on_each_cpu(brcm_set_cpu_speed, &chg, 1);
+	cpu_div = val;
+	return count;
+}
+
+#endif /* CONFIG_BRCM_CPU_DIV */
+
+#ifdef CONFIG_BRCM_CPU_PLL
+
+static int cpu_pll_mode;
+
+ssize_t brcm_pm_show_cpu_pll(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%d\n", cpu_pll_mode);
+}
+
+ssize_t brcm_pm_store_cpu_pll(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	int val;
+	struct spd_change chg;
+
+	if (sscanf(buf, "%d", &val) != 1)
+		return -EINVAL;
+
+	if (cpu_pll_mode == val)
+		return count;
+
+	switch (val) {
+	case 0:
+		chg.new_base = brcm_cpu_khz;
+		break;
+	case 1:
+		chg.new_base = CPU_PLL_MODE1;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	chg.old_div = cpu_div;
+	chg.new_div = cpu_div;
+	chg.old_base = brcm_adj_cpu_khz;
+	on_each_cpu(brcm_set_cpu_speed, &chg, 1);
+
+	cpu_pll_mode = val;
+	return count;
+}
+
+#endif /* CONFIG_BRCM_CPU_PLL */
+
+static int bmips_check_caps(void)
+{
+	unsigned long __maybe_unused config;
+#ifdef CONFIG_CPU_BMIPS5000
+	fixed_counter_freq = 1;
+#elif defined(CONFIG_CPU_BMIPS4380)
+	config = read_c0_brcm_config();
+	fixed_counter_freq = !!(config & 0x40);
+#else
+	fixed_counter_freq = 0;
+#endif
+	printk(KERN_INFO "PM: CP0 COUNT/COMPARE frequency %s on divisor\n",
+	       fixed_counter_freq ? "does not depend" : "depends");
+	return 0;
+}
+late_initcall(bmips_check_caps);
diff --git a/arch/mips/brcmstb/bmips_5xxx_init.S b/arch/mips/brcmstb/bmips_5xxx_init.S
new file mode 100644
index 0000000..788ebf9
--- /dev/null
+++ b/arch/mips/brcmstb/bmips_5xxx_init.S
@@ -0,0 +1,753 @@
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011-2012 by Broadcom Corporation
+ *
+ * Init for bmips 5000.
+ * Used to init second core in dual core 5000's.
+ */
+
+#include <linux/init.h>
+
+#include <asm/asm.h>
+#include <asm/asmmacro.h>
+#include <asm/cacheops.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/stackframe.h>
+#include <asm/addrspace.h>
+#include <asm/hazards.h>
+#include <asm/bmips.h>
+
+#ifdef CONFIG_CPU_BMIPS5000
+
+
+#define cacheop(kva, size, linesize, op) 	\
+	.set noreorder			;	\
+	addu		t1, kva, size   ;	\
+        subu		t2, linesize, 1 ;	\
+        not		t2		;	\
+        and		t0, kva, t2     ;	\
+        addiu		t1, t1, -1      ;    	\
+        and		t1, t2          ;	\
+9:	cache		op, 0(t0)       ;	\
+        bne		t0, t1, 9b	;	\
+        addu		t0, linesize    ;	\
+        .set reorder			;
+
+
+
+#define	IS_SHIFT	22
+#define	IL_SHIFT	19
+#define	IA_SHIFT	16
+#define	DS_SHIFT	13
+#define	DL_SHIFT	10
+#define	DA_SHIFT	 7
+#define	IS_MASK		 7
+#define	IL_MASK		 7
+#define	IA_MASK		 7
+#define	DS_MASK		 7
+#define	DL_MASK		 7
+#define	DA_MASK		 7
+#define	ICE_MASK	0x80000000
+#define	DCE_MASK	0x40000000
+
+#define CP0_BRCM_CONFIG0	$22, 0
+#define CP0_BRCM_MODE		$22, 1
+#define	CP0_CONFIG_K0_MASK	7
+
+#define CP0_ICACHE_TAG_LO       $28
+#define CP0_ICACHE_DATA_LO      $28, 1
+#define CP0_DCACHE_TAG_LO       $28, 2
+#define CP0_D_SEC_CACHE_DATA_LO	$28, 3
+#define CP0_ICACHE_TAG_HI       $29
+#define CP0_ICACHE_DATA_HI      $29, 1
+#define CP0_DCACHE_TAG_HI       $29, 2
+
+#define CP0_BRCM_MODE_Luc_MASK		(1 << 11)
+#define	CP0_BRCM_CONFIG0_CWF_MASK	(1 << 20)
+#define	CP0_BRCM_CONFIG0_TSE_MASK	(1 << 19)
+#define CP0_BRCM_MODE_SET_MASK		(1 << 7)
+#define CP0_BRCM_MODE_ClkRATIO_MASK	(7 << 4)
+#define CP0_BRCM_MODE_BrPRED_MASK 	(3 << 24)
+#define CP0_BRCM_MODE_BrPRED_SHIFT	24
+#define CP0_BRCM_MODE_BrHIST_MASK 	(0x1f << 20)
+#define CP0_BRCM_MODE_BrHIST_SHIFT	20
+
+/* ZSC L2 Cache Register Access Register Definitions */
+#define BRCM_ZSC_ALL_REGS_SELECT                0x7 << 24
+
+#define BRCM_ZSC_CONFIG_REG			0 << 3
+#define BRCM_ZSC_REQ_BUFFER_REG			2 << 3
+#define BRCM_ZSC_RBUS_ADDR_MAPPING_REG0		4 << 3
+#define BRCM_ZSC_RBUS_ADDR_MAPPING_REG1		6 << 3
+#define BRCM_ZSC_RBUS_ADDR_MAPPING_REG2		8 << 3
+
+#define BRCM_ZSC_SCB0_ADDR_MAPPING_REG0		0xa << 3
+#define BRCM_ZSC_SCB0_ADDR_MAPPING_REG1		0xc << 3
+
+#define BRCM_ZSC_SCB1_ADDR_MAPPING_REG0		0xe << 3
+#define BRCM_ZSC_SCB1_ADDR_MAPPING_REG1		0x10 << 3
+
+#define BRCM_ZSC_CONFIG_LMB1En			1 << (15)
+#define BRCM_ZSC_CONFIG_LMB0En			1 << (14)
+
+/* branch predition values */
+
+#define BRCM_BrPRED_ALL_TAKEN		(0x0)
+#define BRCM_BrPRED_ALL_NOT_TAKEN	(0x1)
+#define BRCM_BrPRED_BHT_ENABLE		(0x2)
+#define BRCM_BrPRED_PREDICT_BACKWARD	(0x3)
+
+
+
+.align 2
+/*
+ * Function: 	size_i_cache
+ * Arguments: 	None
+ * Returns:	v0 = i cache size, v1 = I cache line size
+ * Description: compute the I-cache size and I-cache line size
+ * Trashes:	v0, v1, a0, t0
+ *
+ *	pseudo code:
+ *
+ */
+
+LEAF(size_i_cache)
+	.set    noreorder
+
+	mfc0    a0, CP0_CONFIG, 1
+	move	t0, a0
+
+	/*
+	 * Determine sets per way: IS
+	 *
+	 * This field contains the number of sets (i.e., indices) per way of
+	 * the instruction cache:
+	 * i) 0x0: 64, ii) 0x1: 128, iii) 0x2: 256, iv) 0x3: 512, v) 0x4: 1k
+	 * vi) 0x5 - 0x7: Reserved.
+	 */
+
+	srl     a0, a0, IS_SHIFT
+	and     a0, a0, IS_MASK
+
+	/* sets per way = (64<<IS) */
+
+	li	v0, 0x40
+	sllv    v0, v0, a0
+
+	/*
+	 * Determine line size
+	 *
+	 * This field contains the line size of the instruction cache:
+	 * i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
+	 * 0x5: 64 bytes, iv) the rest: Reserved.
+	 */
+
+	move	a0, t0
+
+	srl	a0, a0, IL_SHIFT
+	and	a0, a0, IL_MASK
+
+	beqz	a0, no_i_cache
+	nop
+
+	/* line size = 2 ^ (IL+1) */
+
+	addi	a0, a0, 1
+	li	v1, 1
+	sll	v1, v1, a0
+
+	/* v0 now have sets per way, multiply it by line size now
+	 * that will give the set size
+	 */
+
+	sll	v0, v0, a0
+
+	/*
+	 * Determine set associativity
+	 *
+	 * This field contains the set associativity of the instruction cache.
+	 * i) 0x0: Direct mapped, ii) 0x1: 2-way, iii) 0x2: 3-way, iv) 0x3:
+	 * 4-way, v) 0x4 - 0x7: Reserved.
+	 */
+
+	move	a0, t0
+
+	srl	a0, a0, IA_SHIFT
+	and	a0, a0, IA_MASK
+	addi	a0, a0, 0x1
+
+	/* v0 has the set size, multiply it by
+	 * set associativiy, to get the cache size
+	 */
+
+	multu	v0, a0	/*multu is interlocked, so no need to insert nops */
+	mflo    v0
+	b	1f
+	nop
+
+no_i_cache:
+	move    v0, zero
+	move	v1, zero
+1:
+	jr       ra
+	nop
+	.set    reorder
+
+END(size_i_cache)
+
+/*
+ * Function: 	size_d_cache
+ * Arguments: 	None
+ * Returns:	v0 = d cache size, v1 = d cache line size
+ * Description: compute the D-cache size and D-cache line size.
+ * Trashes:	v0, v1, a0, t0
+ *
+ */
+
+LEAF(size_d_cache)
+	.set    noreorder
+
+	mfc0    a0, CP0_CONFIG, 1
+	move	t0, a0
+
+	/*
+	 * Determine sets per way: IS
+	 *
+	 * This field contains the number of sets (i.e., indices) per way of
+	 * the instruction cache:
+	 * i) 0x0: 64, ii) 0x1: 128, iii) 0x2: 256, iv) 0x3: 512, v) 0x4: 1k
+	 * vi) 0x5 - 0x7: Reserved.
+	 */
+
+	srl     a0, a0, DS_SHIFT
+	and     a0, a0, DS_MASK
+
+	/* sets per way = (64<<IS) */
+
+	li	v0, 0x40
+	sllv    v0, v0, a0
+
+	/*
+	 * Determine line size
+	 *
+	 * This field contains the line size of the instruction cache:
+	 * i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
+	 * 0x5: 64 bytes, iv) the rest: Reserved.
+	 */
+	move	a0, t0
+
+	srl	a0, a0, DL_SHIFT
+	and	a0, a0, DL_MASK
+
+	beqz	a0, no_d_cache
+	nop
+
+	/* line size = 2 ^ (IL+1) */
+
+	addi	a0, a0, 1
+	li	v1, 1
+	sll	v1, v1, a0
+
+	/* v0 now have sets per way, multiply it by line size now
+	 * that will give the set size
+	 */
+
+	sll	v0, v0, a0
+
+	/* determine set associativity
+	 *
+	 * This field contains the set associativity of the instruction cache.
+	 * i) 0x0: Direct mapped, ii) 0x1: 2-way, iii) 0x2: 3-way, iv) 0x3:
+	 * 4-way, v) 0x4 - 0x7: Reserved.
+	 */
+
+	move	a0, t0
+
+	srl	a0, a0, DA_SHIFT
+	and	a0, a0, DA_MASK
+	addi	a0, a0, 0x1
+
+	/* v0 has the set size, multiply it by
+	 * set associativiy, to get the cache size
+	 */
+
+	multu	v0, a0	/*multu is interlocked, so no need to insert nops */
+	mflo    v0
+
+	b	1f
+	nop
+
+no_d_cache:
+	move    v0, zero
+	move	v1, zero
+1:
+	jr	ra
+	nop
+	.set    reorder
+
+END(size_d_cache)
+
+
+/*
+ * Function: enable_ID
+ * Arguments: 	None
+ * Returns:	None
+ * Description: Enable I and D caches, initialize I and D-caches, also set
+ *                 hardware delay for d-cache (TP0).
+ * Trashes:	t0
+ *
+ */
+	.global	enable_ID
+	.ent	enable_ID
+	.set    noreorder
+enable_ID:
+	mfc0    t0, CP0_BRCM_CONFIG0
+	or	t0, t0, (ICE_MASK | DCE_MASK)
+	mtc0    t0, CP0_BRCM_CONFIG0
+	jr	ra
+	nop
+
+	.end	enable_ID
+	.set    reorder
+
+
+/*
+ * Function: l1_init
+ * Arguments: 	None
+ * Returns:	None
+ * Description: Enable I and D caches, and initialize I and D-caches
+ * Trashes:	a0, v0, v1, t0, t1, t2, t8
+ *
+ */
+	.globl	l1_init
+	.ent	l1_init
+	.set    noreorder
+l1_init:
+
+	/* save return address */
+	move    t8, ra
+
+
+	/* initialize I and D cache Data and Tag registers.  */
+	mtc0    zero, CP0_ICACHE_TAG_LO
+	mtc0    zero, CP0_ICACHE_TAG_HI
+	mtc0	zero, CP0_ICACHE_DATA_LO
+	mtc0	zero, CP0_ICACHE_DATA_HI
+	mtc0	zero, CP0_DCACHE_TAG_LO
+	mtc0	zero, CP0_DCACHE_TAG_HI
+
+	/* Enable Caches before Clearing. If the caches are disabled
+	 * then the cache operations to clear the cache will be ignored
+	 */
+
+	jal	enable_ID
+	nop
+
+	jal	size_i_cache	/* v0 = i-cache size, v1 = i-cache line size */
+	nop
+
+	/* run uncached in kseg 1 */
+	la	k0, 1f
+	lui	k1, 0x2000
+	or	k0, k1, k0
+	jr	k0
+	nop
+1:
+
+	/*
+	 * set K0 cache mode
+	 */
+
+	mfc0    t0, CP0_CONFIG
+	and     t0, t0, ~CP0_CONFIG_K0_MASK
+	or      t0, t0, 3	/* Write Back mode */
+	mtc0    t0, CP0_CONFIG
+
+	/*
+	 * Initialize  instruction cache.
+	 */
+
+	li	a0, KSEG0
+	cacheop(a0, v0, v1, Index_Store_Tag_I)
+
+	/*
+	 * Now we can run from I-$, kseg 0
+	 */
+	la	k0, 1f
+	lui	k1, 0x2000
+	or	k0, k1, k0
+	xor	k0, k1, k0
+	jr	k0
+	nop
+1:
+	/*
+	 * Initialize  data cache.
+	 */
+
+	jal	size_d_cache	/* v0 = d-cache size, v1 = d-cache line size */
+	nop
+
+
+	li      a0, KSEG0
+	cacheop(a0, v0, v1, Index_Store_Tag_D)
+
+	jr	t8
+	nop
+
+	.end 	l1_init
+	.set    reorder
+
+
+/*
+ * Function: 	set_other_config
+ * Arguments:	none
+ * Returns:	None
+ * Description: initialize other remainder configuration to defaults.
+ * Trashes:	t0, t1
+ *
+ *	pseudo code:
+ *
+ */
+LEAF(set_other_config)
+	.set noreorder
+
+        /* enable Bus error for I-fetch */
+        mfc0	t0, CP0_CACHEERR, 0
+        li	t1, 0x4
+        or	t0, t1
+	mtc0	t0, CP0_CACHEERR, 0
+
+        /* enable Bus error for Load */
+        mfc0	t0, CP0_CACHEERR, 1
+        li	t1, 0x4
+        or	t0, t1
+	mtc0	t0, CP0_CACHEERR, 1
+
+	/* enable Bus Error for Store */
+        mfc0	t0, CP0_CACHEERR, 2
+	li	t1, 0x4
+	or	t0, t1
+        mtc0	t0, CP0_CACHEERR, 2
+
+	jr	ra
+	nop
+	.set reorder
+END(set_other_config)
+
+/*
+ * Function: 	set_branch_pred
+ * Arguments:	none
+ * Returns:	None
+ * Description:
+ * Trashes:	t0, t1
+ *
+ *	pseudo code:
+ *
+ */
+
+LEAF(set_branch_pred)
+	.set noreorder
+	mfc0    t0, CP0_BRCM_MODE
+	li	t1, ~(CP0_BRCM_MODE_BrPRED_MASK | CP0_BRCM_MODE_BrHIST_MASK )
+	and	t0, t0, t1
+
+	/* enable Branch prediction */
+	li	t1, BRCM_BrPRED_BHT_ENABLE
+	sll	t1, CP0_BRCM_MODE_BrPRED_SHIFT
+	or	t0, t0, t1
+
+	/* set history count to 8 */
+	li	t1, 8
+	sll	t1, CP0_BRCM_MODE_BrHIST_SHIFT
+	or	t0, t0, t1
+
+	mtc0    t0, CP0_BRCM_MODE
+	jr	ra
+	nop
+	.set    reorder
+END(set_branch_pred)
+
+
+/*
+ * Function: 	set_luc
+ * Arguments:	set link uncached.
+ * Returns:	None
+ * Description:
+ * Trashes:	t0, t1
+ *
+ */
+LEAF(set_luc)
+	.set noreorder
+	mfc0    t0, CP0_BRCM_MODE
+	li	t1, ~(CP0_BRCM_MODE_Luc_MASK)
+	and	t0, t0, t1
+
+	/* set Luc */
+        ori	t0, t0, CP0_BRCM_MODE_Luc_MASK
+
+	mtc0    t0, CP0_BRCM_MODE
+	jr	ra
+	nop
+	.set    reorder
+END(set_luc)
+
+/*
+ * Function: 	set_cwf_tse
+ * Arguments:	set CWF and TSE bits
+ * Returns:	None
+ * Description:
+ * Trashes:	t0, t1
+ *
+ */
+LEAF(set_cwf_tse)
+	.set noreorder
+	mfc0    t0, CP0_BRCM_CONFIG0
+	li	t1, (CP0_BRCM_CONFIG0_CWF_MASK | CP0_BRCM_CONFIG0_TSE_MASK)
+	or	t0, t0, t1
+
+	mtc0    t0, CP0_BRCM_CONFIG0
+	jr	ra
+	nop
+	.set    reorder
+END(set_cwf_tse)
+
+/*
+ * Function: 	set_clock_ratio
+ * Arguments:   set clock ratio specified by a0
+ * Returns:	None
+ * Description:
+ * Trashes:	v0, v1, a0, a1
+ *
+ *	pseudo code:
+ *
+ */
+LEAF(set_clock_ratio)
+	.set noreorder
+
+	mfc0    t0, CP0_BRCM_MODE
+	li	t1, ~(CP0_BRCM_MODE_SET_MASK | CP0_BRCM_MODE_ClkRATIO_MASK)
+	and	t0, t0, t1
+	li	t1, CP0_BRCM_MODE_SET_MASK
+	or	t0, t0, t1
+	or	t0, t0, a0
+	mtc0    t0, CP0_BRCM_MODE
+	jr	ra
+	nop
+	.set    reorder
+END(set_clock_ratio)
+/*
+ * Function: set_zephyr
+ * Arguments:   None
+ * Returns:     None
+ * Description: Set any zephyr bits
+ * Trashes:     t0 & t1
+ *
+ */
+LEAF(set_zephyr)
+        .set    noreorder
+
+        /* enable read/write of CP0 #22 sel. 8 */
+        li      t0, 0x5a455048
+	.word	0x4088b00f      /* mtc0    t0, $22, 15 */
+
+	.word	0x4008b008      /* mfc0    t0, $22, 8 */
+        li      t1, 0x09008000	/* turn off pref, jtb */
+        or      t0, t0, t1
+	.word	0x4088b008      /* mtc0    t0, $22, 8 */
+        sync
+
+	/* disable read/write of CP0 #22 sel 8 */
+        li      t0, 0x0
+	.word	0x4088b00f      /* mtc0    t0, $22, 15 */
+
+
+        jr      ra
+        nop
+	.set reorder
+
+END(set_zephyr)
+
+
+/*
+ * Function:    set_llmb
+ * Arguments:   a0=0 disable llmb, a0=1 enables llmb
+ * Returns:     None
+ * Description:
+ * Trashes:     t0, t1, t2
+ *
+ *      pseudo code:
+ *
+ */
+LEAF(set_llmb)
+	.set noreorder
+
+	li	t2, 0x90000000 | BRCM_ZSC_ALL_REGS_SELECT | BRCM_ZSC_CONFIG_REG
+	sync
+	cache	0x7, 0x0(t2)
+	sync
+	mfc0	t0, CP0_D_SEC_CACHE_DATA_LO
+	li	t1, ~(BRCM_ZSC_CONFIG_LMB1En | BRCM_ZSC_CONFIG_LMB0En)
+	and	t0, t0, t1
+
+	beqz	a0, svlmb
+	nop
+
+enable_lmb:
+	li	t1, (BRCM_ZSC_CONFIG_LMB1En | BRCM_ZSC_CONFIG_LMB0En)
+	or	t0, t0, t1
+
+svlmb:
+	mtc0	t0, CP0_D_SEC_CACHE_DATA_LO
+	sync
+	cache	0xb, 0x0(t2)
+	sync
+
+	jr      ra
+	nop
+	.set reorder
+
+END(set_llmb)
+/*
+ * Function: 	core_init
+ * Arguments:	none
+ * Returns:	None
+ * Description: initialize core related configuration
+ * Trashes:	v0,v1,a0,a1,t8
+ *
+ *	pseudo code:
+ *
+ */
+	.globl	core_init
+	.ent    core_init
+	.set	noreorder
+core_init:
+	move	t8, ra
+
+	/* set Zephyr bits. */
+	bal	set_zephyr
+	nop
+
+#if ENABLE_FPU==1
+	/* initialize the Floating point unit (both TPs) */
+	bal	init_fpu
+	nop
+#endif
+
+	/* set low latency memory bus */
+	li      a0, 1
+	bal     set_llmb
+	nop
+
+	/* set branch prediction (TP0 only) */
+	bal	set_branch_pred
+	nop
+
+	/* set link uncached */
+	bal	set_luc
+	nop
+
+	/* set CWF and TSE */
+	bal     set_cwf_tse
+	nop
+
+	/*
+	 *set clock ratio by setting 1 to 'set'
+	 * and 0 to ClkRatio, (TP0 only)
+	 */
+	li	a0, 0
+	bal	set_clock_ratio
+	nop
+
+	/* set other configuration to defaults */
+	bal	set_other_config
+	nop
+
+	move	ra, t8
+	jr	ra
+	nop
+
+	.set reorder
+	.end	core_init
+
+/*
+ * Function: 	clear_jump_target_buffer
+ * Arguments:   None
+ * Returns:     None
+ * Description:
+ * Trashes:     t0, t1, t2
+ *
+ */
+#define RESET_CALL_RETURN_STACK_THIS_THREAD             (0x06<<16)
+#define RESET_JUMP_TARGET_BUFFER_THIS_THREAD    	(0x04<<16)
+#define JTB_CS_CNTL_MASK				(0xFF<<16)
+
+	.globl  clear_jump_target_buffer
+	.ent    clear_jump_target_buffer
+	.set    noreorder
+clear_jump_target_buffer:
+
+        mfc0    t0, $22, 2
+        nop
+        nop
+
+        li	t1, ~JTB_CS_CNTL_MASK
+        and	t0, t0, t1
+        li	t2, RESET_CALL_RETURN_STACK_THIS_THREAD
+        or	t0, t0, t2
+        mtc0    t0, $22, 2
+        nop
+        nop
+
+        and	t0, t0, t1
+        li	t2, RESET_JUMP_TARGET_BUFFER_THIS_THREAD
+        or	t0, t0, t2
+        mtc0	t0, $22, 2
+        nop
+        nop
+        jr      ra
+        nop
+
+	.end    clear_jump_target_buffer
+	.set    reorder
+/*
+ * Function: 	bmips_cache_init
+ * Arguments: 	None
+ * Returns:	None
+ * Description: Enable I and D caches, and initialize I and D-caches
+ * Trashes:	v0, v1, t0, t1, t2, t5, t7, t8
+ *
+ */
+	.globl	bmips_5xxx_init
+	.ent	bmips_5xxx_init
+	.set    noreorder
+bmips_5xxx_init:
+
+	/* save return address  and A0 */
+	move    t7, ra
+	move	t5, a0
+
+	jal	l1_init
+	nop
+
+	jal	core_init
+	nop
+
+	jal	clear_jump_target_buffer
+	nop
+
+        mtc0    zero, CP0_CAUSE
+
+	move 	a0, t5
+	jr	t7
+	nop
+
+	.end 	bmips_5xxx_init
+	.set    reorder
+
+
+#endif
diff --git a/arch/mips/brcmstb/irq.c b/arch/mips/brcmstb/irq.c
new file mode 100644
index 0000000..be7dab3
--- /dev/null
+++ b/arch/mips/brcmstb/irq.c
@@ -0,0 +1,440 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/cpumask.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <linux/version.h>
+
+#include <asm/irq.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/irq_cpu.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#ifdef CONFIG_SMP
+static int next_cpu[NR_IRQS + 1] = { [0 ... NR_IRQS] = 0 };
+#define NEXT_CPU(irq) next_cpu[irq]
+
+#define TP0_BASE BCHP_HIF_CPU_INTR1_REG_START
+#define TP1_BASE BCHP_HIF_CPU_TP1_INTR1_REG_START
+#define L1_WR_ALL(word, reg, val) do { \
+	L1_WR_##word(TP0_BASE, reg, val); \
+	if (cpu_online(1)) \
+		L1_WR_##word(TP1_BASE, reg, val); \
+	} while (0)
+
+#else
+
+#define TP0_BASE BCHP_HIF_CPU_INTR1_REG_START
+#define TP1_BASE TP0_BASE
+#define L1_WR_ALL(word, reg, val) do { \
+	L1_WR_##word(TP0_BASE, reg, val); \
+	} while (0)
+
+#define NEXT_CPU(irq) 0
+#endif
+
+#define L1_REG(base, off) ((base) + (off) - BCHP_HIF_CPU_INTR1_REG_START)
+
+#define L1_RD_W0(base, reg) \
+	BDEV_RD(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W0_##reg))
+#define L1_RD_W1(base, reg) \
+	BDEV_RD(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W1_##reg))
+
+#define L1_WR_W0(base, reg, val) \
+	BDEV_WR_RB(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W0_##reg), val)
+#define L1_WR_W1(base, reg, val) \
+	BDEV_WR_RB(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W1_##reg), val)
+
+#if defined(BCHP_HIF_CPU_INTR1_INTR_W2_STATUS)
+
+#define L1_RD_W2(base, reg) \
+	BDEV_RD(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W2_##reg))
+#define L1_WR_W2(base, reg, val) \
+	BDEV_WR_RB(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W2_##reg), val)
+
+#else
+/* nop on chips with only 64 L1 interrupts */
+#define L1_RD_W2(base, reg)	0
+#define L1_WR_W2(base, reg, val) do { } while (0)
+#endif
+
+#if defined(BCHP_HIF_CPU_INTR1_INTR_W3_STATUS)
+
+#define L1_RD_W3(base, reg) \
+	BDEV_RD(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W3_##reg))
+#define L1_WR_W3(base, reg, val) \
+	BDEV_WR_RB(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W3_##reg), val)
+
+#else
+/* nop on chips with only 96 L1 interrupts */
+#define L1_RD_W3(base, reg)	0
+#define L1_WR_W3(base, reg, val) do { } while (0)
+#endif
+
+/*
+ * For interrupt map, see include/asm-mips/brcmstb/<plat>/bcmintrnum.h
+ */
+
+/***********************************************************************
+ * INTC (aka L1 interrupt) functions
+ ***********************************************************************/
+
+static void brcm_intc_enable(struct irq_data *d)
+{
+	unsigned int irq = d->irq;
+	unsigned int shift;
+	unsigned long base = NEXT_CPU(irq) ? TP1_BASE : TP0_BASE;
+
+	if (irq > 0 && irq <= 32) {
+		shift = irq - 1;
+		L1_WR_W0(base, MASK_CLEAR, (1UL << shift));
+	} else if (irq > 32 && irq <= 32+32) {
+		shift = irq - 32 - 1;
+		L1_WR_W1(base, MASK_CLEAR, (1UL << shift));
+	} else if (irq > 64 && irq <= 32+32+32) {
+		shift = irq - 64 - 1;
+		L1_WR_W2(base, MASK_CLEAR, (1UL << shift));
+	} else if (irq > 96 && irq <= 32+32+32+32) {
+		shift = irq - 96 - 1;
+		L1_WR_W3(base, MASK_CLEAR, (1UL << shift));
+	} else
+		BUG();
+}
+
+static void brcm_intc_disable(struct irq_data *d)
+{
+	unsigned int irq = d->irq;
+	unsigned int shift;
+
+	if (irq > 0 && irq <= 32) {
+		shift = irq - 1;
+		L1_WR_ALL(W0, MASK_SET, (1UL << shift));
+	} else if (irq > 32 && irq <= 32+32) {
+		shift = irq - 32 - 1;
+		L1_WR_ALL(W1, MASK_SET, (1UL << shift));
+	} else if (irq > 64 && irq <= 32+32+32) {
+		shift = irq - 64 - 1;
+		L1_WR_ALL(W2, MASK_SET, (1UL << shift));
+	} else if (irq > 96 && irq <= 32+32+32+32) {
+		shift = irq - 96 - 1;
+		L1_WR_ALL(W3, MASK_SET, (1UL << shift));
+	} else
+		BUG();
+}
+
+#ifdef CONFIG_SMP
+static int brcm_intc_set_affinity(struct irq_data *d,
+	const struct cpumask *dest, bool force)
+{
+	unsigned int irq = d->irq;
+	unsigned int shift;
+	unsigned long flags;
+
+	local_irq_save(flags);
+	if (irq > 0 && irq <= 32) {
+		shift = irq - 1;
+
+		if (cpu_isset(0, *dest)) {
+			L1_WR_W0(TP1_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W0(TP0_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 0;
+		} else {
+			L1_WR_W0(TP0_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W0(TP1_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 1;
+		}
+	} else if (irq > 32 && irq <= 64) {
+		shift = irq - 32 - 1;
+		next_cpu[irq] = 0;
+
+		if (cpu_isset(0, *dest)) {
+			L1_WR_W1(TP1_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W1(TP0_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 0;
+		} else {
+			L1_WR_W1(TP0_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W1(TP1_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 1;
+		}
+	} else if (irq > 64 && irq <= 96) {
+		shift = irq - 64 - 1;
+		next_cpu[irq] = 0;
+
+		if (cpu_isset(0, *dest)) {
+			L1_WR_W2(TP1_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W2(TP0_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 0;
+		} else {
+			L1_WR_W2(TP0_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W2(TP1_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 1;
+		}
+	} else if (irq > 96 && irq <= 128) {
+		shift = irq - 96 - 1;
+		next_cpu[irq] = 0;
+
+		if (cpu_isset(0, *dest)) {
+			L1_WR_W3(TP1_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W3(TP0_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 0;
+		} else {
+			L1_WR_W3(TP0_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W3(TP1_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 1;
+		}
+	}
+	local_irq_restore(flags);
+	return 0;
+}
+#endif /* CONFIG_SMP */
+
+/*
+ * THT: These INTC disable the interrupt before calling the IRQ handle_irq
+ */
+static struct irq_chip brcm_intc_type = {
+	.name			= "BRCM L1",
+	.irq_ack		= brcm_intc_disable,
+	.irq_mask		= brcm_intc_disable,
+	.irq_mask_ack		= brcm_intc_disable,
+	.irq_unmask		= brcm_intc_enable,
+#ifdef CONFIG_SMP
+	.irq_set_affinity	= brcm_intc_set_affinity,
+#endif /* CONFIG_SMP */
+	NULL
+};
+
+/*
+ * Move the interrupt to the other TP, to balance load (if affinity permits)
+ */
+static void flip_tp(int irq)
+{
+#ifdef CONFIG_SMP
+	int tp = smp_processor_id();
+	unsigned long local_lev1, remote_lev1;
+	unsigned long mask = 1 << ((irq - 1) & 0x1f);
+
+	if (tp == 0) {
+		local_lev1 = TP0_BASE;
+		remote_lev1 = TP1_BASE;
+	} else {
+		local_lev1 = TP1_BASE;
+		remote_lev1 = TP0_BASE;
+	}
+
+	if (cpumask_test_cpu(tp ^ 1, irq_desc[irq].irq_data.affinity)) {
+		next_cpu[irq] = tp ^ 1;
+		if (irq > 0 && irq <= 32) {
+			L1_WR_W0(local_lev1, MASK_SET, mask);
+			L1_WR_W0(remote_lev1, MASK_CLEAR, mask);
+		}
+		if (irq > 32 && irq <= 64) {
+			L1_WR_W1(local_lev1, MASK_SET, mask);
+			L1_WR_W1(remote_lev1, MASK_CLEAR, mask);
+		}
+		if (irq > 64 && irq <= 96) {
+			L1_WR_W2(local_lev1, MASK_SET, mask);
+			L1_WR_W2(remote_lev1, MASK_CLEAR, mask);
+		}
+		if (irq > 96 && irq <= 128) {
+			L1_WR_W3(local_lev1, MASK_SET, mask);
+			L1_WR_W3(remote_lev1, MASK_CLEAR, mask);
+		}
+	}
+#endif /* CONFIG_SMP */
+}
+
+static void brcm_intc_dispatch(struct pt_regs *regs, unsigned long base)
+{
+	u32 pend, shift;
+
+	pend = L1_RD_W0(base, STATUS) & ~L1_RD_W0(base, MASK_STATUS);
+	while ((shift = ffs(pend)) != 0) {
+		pend ^= (1 << (shift - 1));
+		do_IRQ(shift);
+		flip_tp(shift);
+	}
+
+	pend = L1_RD_W1(base, STATUS) & ~L1_RD_W1(base, MASK_STATUS);
+	while ((shift = ffs(pend)) != 0) {
+		pend ^= (1 << (shift - 1));
+		shift += 32;
+		do_IRQ(shift);
+		flip_tp(shift);
+	}
+	pend = L1_RD_W2(base, STATUS) & ~L1_RD_W2(base, MASK_STATUS);
+	while ((shift = ffs(pend)) != 0) {
+		pend ^= (1 << (shift - 1));
+		shift += 64;
+		do_IRQ(shift);
+		flip_tp(shift);
+	}
+	pend = L1_RD_W3(base, STATUS) & ~L1_RD_W3(base, MASK_STATUS);
+	while ((shift = ffs(pend)) != 0) {
+		pend ^= (1 << (shift - 1));
+		shift += 96;
+		do_IRQ(shift);
+		flip_tp(shift);
+	}
+}
+
+/* IRQ2 = L1 interrupt for TP0 */
+static void brcm_mips_int2_dispatch(struct pt_regs *regs)
+{
+	clear_c0_status(STATUSF_IP2);
+	brcm_intc_dispatch(regs, TP0_BASE);
+	set_c0_status(STATUSF_IP2);
+}
+
+#ifdef CONFIG_SMP
+/* IRQ3 = L1 interrupt for TP1 */
+static void brcm_mips_int3_dispatch(struct pt_regs *regs)
+{
+	clear_c0_status(STATUSF_IP3);
+	brcm_intc_dispatch(regs, TP1_BASE);
+	set_c0_status(STATUSF_IP3);
+}
+#endif
+
+/***********************************************************************
+ * IRQ setup / dispatch
+ ***********************************************************************/
+
+void __init arch_init_irq(void)
+{
+	int irq;
+
+	mips_cpu_irq_init();
+
+	L1_WR_ALL(W0, MASK_SET, 0xffffffff);
+	L1_WR_ALL(W1, MASK_SET, 0xffffffff);
+	L1_WR_ALL(W2, MASK_SET, 0xffffffff);
+	L1_WR_ALL(W3, MASK_SET, 0xffffffff);
+
+	clear_c0_status(ST0_IE | ST0_IM);
+
+	/* Set up all L1 IRQs */
+	for (irq = 1; irq < BRCM_VIRTIRQ_BASE; irq++)
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)
+		irq_set_chip_and_handler(irq, &brcm_intc_type,
+			handle_level_irq);
+#else
+		set_irq_chip_and_handler(irq, &brcm_intc_type,
+			handle_level_irq);
+#endif
+
+#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_HARDIRQS)
+	/* default affinity: 1 (TP0 only) */
+	cpumask_clear(irq_default_affinity);
+	cpumask_set_cpu(0, irq_default_affinity);
+#endif
+
+	/* enable IRQ2 (this runs on TP0).  IRQ3 enabled during TP1 boot. */
+	set_c0_status(STATUSF_IP2);
+
+	/* enable non-shared UART interrupts in the L2 */
+
+#if defined(BCHP_IRQ0_UART_IRQEN_uarta_MASK)
+	/* 3548 style - separate register */
+	BDEV_WR(BCHP_IRQ0_UART_IRQEN, BCHP_IRQ0_UART_IRQEN_uarta_MASK |
+		BCHP_IRQ0_UART_IRQEN_uartb_MASK |
+		BCHP_IRQ0_UART_IRQEN_uartc_MASK);
+	BDEV_WR(BCHP_IRQ0_IRQEN, 0);
+#elif defined(BCHP_IRQ0_IRQEN_uarta_irqen_MASK)
+	/* 7405 style - shared with L2 */
+	BDEV_WR(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uarta_irqen_MASK
+		| BCHP_IRQ0_IRQEN_uartb_irqen_MASK
+#if defined(BCHP_IRQ0_IRQEN_uartc_irqen_MASK)
+		| BCHP_IRQ0_IRQEN_uartc_irqen_MASK
+#endif
+		);
+#endif
+
+#if defined(BCHP_HIF_INTR2_CPU_MASK_SET)
+	/* mask and clear all HIF L2 interrupts */
+	BDEV_WR_RB(BCHP_HIF_INTR2_CPU_MASK_SET, 0xffffffff);
+	BDEV_WR_RB(BCHP_HIF_INTR2_CPU_CLEAR, 0xffffffff);
+#endif
+}
+
+asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
+{
+	unsigned int pend = ((read_c0_cause() & read_c0_status()) >> 8) & 0xff;
+	unsigned int shift;
+
+	while ((shift = ffs(pend)) != 0) {
+		shift--;
+		pend ^= 1 << shift;
+		if (shift == 2)
+			brcm_mips_int2_dispatch(regs);
+#ifdef CONFIG_SMP
+		else if (unlikely(shift == 3))
+			brcm_mips_int3_dispatch(regs);
+#endif
+		else
+			do_IRQ(MIPS_CPU_IRQ_BASE + shift);
+	}
+}
+
+/***********************************************************************
+ * Power management
+ ***********************************************************************/
+
+static unsigned long brcm_irq_state[NR_IRQS / 32];
+
+void brcm_irq_standby_enter(int wake_irq)
+{
+	/* save the current state, then mask everything */
+	brcm_irq_state[0] = L1_RD_W0(TP0_BASE, MASK_STATUS);
+	L1_WR_W0(TP0_BASE, MASK_SET, 0xffffffff);
+	brcm_irq_state[1] = L1_RD_W1(TP0_BASE, MASK_STATUS);
+	L1_WR_W1(TP0_BASE, MASK_SET, 0xffffffff);
+	brcm_irq_state[2] = L1_RD_W2(TP0_BASE, MASK_STATUS);
+	L1_WR_W2(TP0_BASE, MASK_SET, 0xffffffff);
+	brcm_irq_state[3] = L1_RD_W3(TP0_BASE, MASK_STATUS);
+	L1_WR_W3(TP0_BASE, MASK_SET, 0xffffffff);
+
+	/* unmask the wakeup IRQ */
+	if (wake_irq > 0 && wake_irq <= 32)
+		L1_WR_W0(TP0_BASE, MASK_CLEAR, 1 << (wake_irq - 1));
+	else if (wake_irq > 32 && wake_irq <= 64)
+		L1_WR_W1(TP0_BASE, MASK_CLEAR, 1 << (wake_irq - 33));
+	else if (wake_irq > 64 && wake_irq <= 96)
+		L1_WR_W2(TP0_BASE, MASK_CLEAR, 1 << (wake_irq - 65));
+	else if (wake_irq > 96 && wake_irq <= 128)
+		L1_WR_W3(TP0_BASE, MASK_CLEAR, 1 << (wake_irq - 97));
+}
+
+void brcm_irq_standby_exit(void)
+{
+	/* restore the saved L1 state */
+	L1_WR_W0(TP0_BASE, MASK_SET, 0xffffffff);
+	L1_WR_W0(TP0_BASE, MASK_CLEAR, ~brcm_irq_state[0]);
+	L1_WR_W1(TP0_BASE, MASK_SET, 0xffffffff);
+	L1_WR_W1(TP0_BASE, MASK_CLEAR, ~brcm_irq_state[1]);
+	L1_WR_W2(TP0_BASE, MASK_SET, 0xffffffff);
+	L1_WR_W2(TP0_BASE, MASK_CLEAR, ~brcm_irq_state[2]);
+	L1_WR_W3(TP0_BASE, MASK_SET, 0xffffffff);
+	L1_WR_W3(TP0_BASE, MASK_CLEAR, ~brcm_irq_state[3]);
+}
diff --git a/arch/mips/brcmstb/memory.c b/arch/mips/brcmstb/memory.c
new file mode 100644
index 0000000..aaa0748
--- /dev/null
+++ b/arch/mips/brcmstb/memory.c
@@ -0,0 +1,565 @@
+/*
+ * Copyright (C) 2000-2004 Russell King
+ * Copyright (C) 2010 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/bootmem.h>
+#include <linux/spinlock.h>
+#include <linux/mm.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/ioport.h>
+#include <linux/list.h>
+#include <linux/vmalloc.h>
+#include <linux/compiler.h>
+#include <linux/atomic.h>
+#include <linux/printk.h>
+#include <linux/module.h>
+
+#include <asm/page.h>
+#include <asm/pgtable-32.h>
+#include <asm/pgtable-bits.h>
+#include <asm/addrspace.h>
+#include <asm/tlbflush.h>
+#include <asm/r4kcache.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#include <spaces.h>
+
+/*
+ * Override default behavior to allow cached access to all valid DRAM ranges
+ */
+int __uncached_access(struct file *file, unsigned long addr)
+{
+	if (file->f_flags & O_SYNC)
+		return 1;
+	if (addr >= BCHP_PHYSICAL_OFFSET && addr < UPPERMEM_START)
+		return 1;
+	if (addr >= PCIE_MEM_START)
+		return 1;
+	return 0;
+}
+
+/***********************************************************************
+ * Wired TLB mappings for upper memory support
+ ***********************************************************************/
+
+#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
+
+/* (PFN << 6) | GLOBAL | VALID | DIRTY | cacheability */
+#define ENTRYLO_CACHED(paddr)	(((paddr) >> 6) | (0x07) | (0x03 << 3))
+#define ENTRYLO_UNCACHED(paddr)	(((paddr) >> 6) | (0x07) | (0x02 << 3))
+
+/* GLOBAL | !VALID */
+#define ENTRYLO_INVALID()	(0x01)
+
+struct tlb_entry {
+	unsigned long entrylo0;
+	unsigned long entrylo1;
+	unsigned long entryhi;
+	unsigned long pagemask;
+};
+
+static struct tlb_entry __maybe_unused uppermem_mappings[] = {
+{
+#if defined(CONFIG_BRCM_UPPER_768MB)
+	.entrylo0		= ENTRYLO_CACHED(TLB_UPPERMEM_PA),
+	.entrylo1		= ENTRYLO_INVALID(),
+	.entryhi		= TLB_UPPERMEM_VA,
+	.pagemask		= PM_256M,
+#endif
+},
+};
+
+static inline void __cpuinit brcm_write_tlb_entry(int idx,
+	unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi,
+	unsigned long pagemask)
+{
+	write_c0_entrylo0(entrylo0);
+	write_c0_entrylo1(entrylo1);
+	write_c0_entryhi(entryhi);
+	write_c0_pagemask(pagemask);
+	write_c0_index(idx);
+	mtc0_tlbw_hazard();
+	tlb_write_indexed();
+	tlbw_use_hazard();
+}
+
+/*
+ * This function is used instead of add_wired_entry(), because it does not
+ * have any external dependencies and is not marked __init
+ */
+static inline void __cpuinit brcm_add_wired_entry(unsigned long entrylo0,
+	unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask)
+{
+	int i = read_c0_wired();
+	write_c0_wired(i + 1);
+	brcm_write_tlb_entry(i, entrylo0, entrylo1, entryhi, pagemask);
+}
+
+extern void tlb_init(void);
+extern void build_tlb_refill_handler(void);
+
+void __cpuinit brcm_tlb_init(void)
+{
+#ifdef CONFIG_BRCM_UPPER_MEMORY
+	if (smp_processor_id() == 0) {
+		int i;
+		struct tlb_entry *e = uppermem_mappings;
+
+		tlb_init();
+		for (i = 0; i < ARRAY_SIZE(uppermem_mappings); i++, e++)
+			brcm_add_wired_entry(e->entrylo0, e->entrylo1,
+				e->entryhi, e->pagemask);
+		write_c0_pagemask(PM_DEFAULT_MASK);
+	} else {
+		/* bypass tlb_init() / probe_tlb() for secondary CPU */
+		cpu_data[smp_processor_id()].tlbsize = cpu_data[0].tlbsize;
+		build_tlb_refill_handler();
+	}
+#else
+	tlb_init();
+#endif
+}
+
+/*
+ * Initialize upper memory TLB entries
+ *
+ * On TP1 this must happen before we set up $sp/$gp .  It is always
+ * possible for stacks, task_structs, thread_info's, and other
+ * important structures to be allocated out of upper memory so
+ * this happens early on.
+ */
+asmlinkage void plat_wired_tlb_setup(void)
+{
+#ifdef CONFIG_BRCM_UPPER_MEMORY
+	int i, tlbsz;
+
+	/* Flush TLB.  local_flush_tlb_all() is not available yet. */
+	write_c0_entrylo0(0);
+	write_c0_entrylo1(0);
+	write_c0_pagemask(PM_DEFAULT_MASK);
+	write_c0_wired(0);
+
+	tlbsz = (read_c0_config1() >> 25) & 0x3f;
+	for (i = 0; i <= tlbsz; i++) {
+		write_c0_entryhi(UNIQUE_ENTRYHI(i));
+		write_c0_index(i);
+		mtc0_tlbw_hazard();
+		tlb_write_indexed();
+		tlbw_use_hazard();
+	}
+
+	write_c0_wired(0);
+	mtc0_tlbw_hazard();
+
+	for (i = 0; i < ARRAY_SIZE(uppermem_mappings); i++) {
+		struct tlb_entry *e = &uppermem_mappings[i];
+		brcm_add_wired_entry(e->entrylo0, e->entrylo1, e->entryhi,
+			e->pagemask);
+	}
+
+	write_c0_pagemask(PM_DEFAULT_MASK);
+#endif
+}
+
+#ifdef CONFIG_BRCM_UPPER_768MB
+
+/***********************************************************************
+ * Special allocator for coherent (uncached) memory
+ * (Required for >256MB upper memory)
+ ***********************************************************************/
+
+#define CONSISTENT_DMA_SIZE	(CONSISTENT_END - CONSISTENT_BASE)
+#define CONSISTENT_OFFSET(x)	(((unsigned long)(x) - CONSISTENT_BASE) >> \
+	PAGE_SHIFT)
+#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> \
+	PGDIR_SHIFT)
+#define NUM_CONSISTENT_PTES	(CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)
+
+/*
+ * These are the page tables (4MB each) covering uncached, DMA consistent
+ * allocations
+ */
+static pte_t *consistent_pte[NUM_CONSISTENT_PTES];
+static DEFINE_SPINLOCK(consistent_lock);
+
+struct arm_vm_region {
+	struct list_head	vm_list;
+	unsigned long		vm_start;
+	unsigned long		vm_end;
+	void			*vm_cac_va;
+	int			vm_active;
+};
+
+static struct arm_vm_region consistent_head = {
+	.vm_list	= LIST_HEAD_INIT(consistent_head.vm_list),
+	.vm_start	= CONSISTENT_BASE,
+	.vm_end		= CONSISTENT_END,
+};
+
+static struct arm_vm_region *
+arm_vm_region_alloc(struct arm_vm_region *head, size_t size, gfp_t gfp)
+{
+	unsigned long addr = head->vm_start, end = head->vm_end - size;
+	unsigned long flags;
+	struct arm_vm_region *c, *new;
+
+	new = kmalloc(sizeof(struct arm_vm_region), gfp);
+	if (!new)
+		goto out;
+
+	spin_lock_irqsave(&consistent_lock, flags);
+
+	list_for_each_entry(c, &head->vm_list, vm_list) {
+		if ((addr + size) < addr)
+			goto nospc;
+		if ((addr + size) <= c->vm_start)
+			goto found;
+		addr = c->vm_end;
+		if (addr > end)
+			goto nospc;
+	}
+
+found:
+	/*
+	 * Insert this entry _before_ the one we found.
+	 */
+	list_add_tail(&new->vm_list, &c->vm_list);
+	new->vm_start = addr;
+	new->vm_end = addr + size;
+	new->vm_active = 1;
+
+	spin_unlock_irqrestore(&consistent_lock, flags);
+	return new;
+
+nospc:
+	spin_unlock_irqrestore(&consistent_lock, flags);
+	kfree(new);
+out:
+	return NULL;
+}
+
+static struct arm_vm_region *arm_vm_region_find(struct arm_vm_region *head,
+	unsigned long addr)
+{
+	struct arm_vm_region *c;
+
+	list_for_each_entry(c, &head->vm_list, vm_list) {
+		if (c->vm_active && c->vm_start == addr)
+			goto out;
+	}
+	c = NULL;
+out:
+	return c;
+}
+
+static int __init consistent_init(void)
+{
+	pgd_t *pgd;
+	pud_t *pud;
+	pmd_t *pmd;
+	pte_t *pte;
+	int ret = 0, i = 0;
+	u32 base = CONSISTENT_BASE;
+
+	do {
+		pgd = pgd_offset(&init_mm, base);
+		pud = pud_alloc(&init_mm, pgd, base);
+		if (!pud) {
+			pr_err("%s: no pud tables\n", __func__);
+			ret = -ENOMEM;
+			break;
+		}
+		pmd = pmd_alloc(&init_mm, pud, base);
+		if (!pmd) {
+			pr_err("%s: no pmd tables\n", __func__);
+			ret = -ENOMEM;
+			break;
+		}
+
+		pte = pte_alloc_kernel(pmd, base);
+		if (!pte) {
+			pr_err("%s: no pte tables\n", __func__);
+			ret = -ENOMEM;
+			break;
+		}
+
+		consistent_pte[i++] = pte;
+		base += (1 << PGDIR_SHIFT);
+	} while (base < CONSISTENT_END);
+
+	return ret;
+}
+
+core_initcall(consistent_init);
+
+int brcm_map_coherent(dma_addr_t dma_handle, void *cac_va, size_t size,
+	void **uncac_va, gfp_t gfp)
+{
+	struct arm_vm_region *c;
+	struct page *page;
+	pte_t *pte;
+	int idx;
+	u32 off;
+
+	c = arm_vm_region_alloc(&consistent_head, size, gfp);
+	if (!c)
+		return -EINVAL;
+
+	c->vm_cac_va = cac_va;
+
+	page = virt_to_page(cac_va);
+	idx = CONSISTENT_PTE_INDEX(c->vm_start);
+	off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1);
+	pte = consistent_pte[idx] + off;
+
+	pr_debug("map addr %08lx idx %x off %x pte %p\n",
+		c->vm_start, idx, off, pte);
+
+	do {
+		if (off >= PTRS_PER_PTE) {
+			off = 0;
+			BUG_ON(idx >= NUM_CONSISTENT_PTES - 1);
+			pte = consistent_pte[++idx];
+		}
+
+		BUG_ON(!pte_none(*pte));
+		set_pte(pte, mk_pte(page, PAGE_KERNEL_UNCACHED));
+		page++;
+		pte++;
+		off++;
+	} while (size -= PAGE_SIZE);
+
+	*uncac_va = (void *)c->vm_start;
+	return 0;
+}
+
+void *brcm_unmap_coherent(void *vaddr)
+{
+	struct arm_vm_region *c;
+	unsigned long flags, addr;
+	void *ret = NULL;
+	pte_t *pte;
+	int idx;
+	u32 off;
+
+	spin_lock_irqsave(&consistent_lock, flags);
+	c = arm_vm_region_find(&consistent_head, (unsigned long)vaddr);
+	if (!c) {
+		spin_unlock_irqrestore(&consistent_lock, flags);
+		pr_err("%s: invalid VA %p\n", __func__, vaddr);
+		return NULL;
+	}
+	c->vm_active = 0;
+	spin_unlock_irqrestore(&consistent_lock, flags);
+
+	ret = c->vm_cac_va;
+	addr = c->vm_start;
+
+	idx = CONSISTENT_PTE_INDEX(addr);
+	off = CONSISTENT_OFFSET(addr) & (PTRS_PER_PTE-1);
+	pte = consistent_pte[idx] + off;
+
+	pr_debug("unmap addr %08lx idx %x off %x pte %p\n",
+		addr, idx, off, pte);
+
+	do {
+		if (off >= PTRS_PER_PTE) {
+			off = 0;
+			BUG_ON(idx >= NUM_CONSISTENT_PTES - 1);
+			pte = consistent_pte[++idx];
+		}
+
+		pte_clear(&init_mm, addr, pte);
+		pte++;
+		off++;
+		addr += PAGE_SIZE;
+	} while (addr < c->vm_end);
+	flush_tlb_kernel_range(c->vm_start, c->vm_end);
+
+	spin_lock_irqsave(&consistent_lock, flags);
+	list_del(&c->vm_list);
+	spin_unlock_irqrestore(&consistent_lock, flags);
+
+	kfree(c);
+
+	return ret;
+}
+
+#endif /* CONFIG_BRCM_UPPER_768MB */
+
+void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+	unsigned long flags)
+{
+	/* sanity check */
+	if ((offset + size - 1) < offset ||
+	    !size ||
+	    offset > max(KSEG0_SIZE, KSEG1_SIZE))
+		return NULL;
+
+	/* !XKS01, XKS01: uncached access to EBI/registers @ PA 1000_0000 */
+	if (offset >= 0x10000000 &&
+	    (offset + size) <= 0x20000000 &&
+	    flags == _CACHE_UNCACHED)
+		return (void *)(KSEG1 + offset);
+
+	/* !XKS01, XKS01: easy cached access to some DRAM */
+	if ((offset + size) <= KSEG0_SIZE &&
+	    flags == _CACHE_CACHABLE_NONCOHERENT)
+		return (void *)(KSEG0 + offset);
+
+	/* !XKS01 only: easy uncached access to some DRAM */
+	if ((offset + size) <= KSEG1_SIZE &&
+	    flags == _CACHE_UNCACHED)
+		return (void *)(KSEG1 + offset);
+
+	/* anything else gets mapped using page tables */
+	return NULL;
+}
+EXPORT_SYMBOL(plat_ioremap);
+
+int plat_iounmap(const volatile void __iomem *addr)
+{
+	phys_t va = (unsigned long)addr;
+
+	if (va >= KSEG0 && va < (KSEG0 + KSEG0_SIZE))
+		return 1;
+	if (va >= KSEG1 && va < (KSEG1 + KSEG1_SIZE))
+		return 1;
+	return 0;
+}
+EXPORT_SYMBOL(plat_iounmap);
+
+/***********************************************************************
+ * RAM configuration
+ ***********************************************************************/
+
+#define MAGIC0		0xdeadbeef
+#define MAGIC1		0xfeedcafe
+
+static inline unsigned int __init probe_ram_size(void)
+{
+	unsigned long addr = KSEG1, taddr;
+	uint32_t olddata;
+	unsigned long flags;
+	unsigned int i, memsize = 256;
+
+	pr_info("Probing system memory size... ");
+
+	local_irq_save(flags);
+	cache_op(Hit_Writeback_Inv_D, KSEG0);
+	olddata = DEV_RD(addr);
+
+	/*
+	 * Try to figure out where memory wraps around.  If it does not
+	 * wrap, assume 256MB
+	*/
+	for (i = 4; i <= 128; i <<= 1) {
+		taddr = KSEG1 + i * 1048576;
+		DEV_WR(addr, MAGIC0);
+		if (DEV_RD(taddr) == MAGIC0) {
+			DEV_WR(addr, MAGIC1);
+			if (DEV_RD(taddr) == MAGIC1) {
+				memsize = i;
+				break;
+			}
+		}
+	}
+
+	DEV_WR(addr, olddata);
+	cache_op(Hit_Writeback_Inv_D, KSEG0);
+	local_irq_restore(flags);
+
+	pr_cont("found %u MB\n", memsize);
+
+	return memsize;
+}
+
+void __init board_get_ram_size(unsigned long *dram0_mb, unsigned long *dram1_mb)
+{
+#if defined(CONFIG_BRCM_OVERRIDE_RAM_SIZE)
+	*dram0_mb = CONFIG_BRCM_FORCED_DRAM0_SIZE;
+#if defined(CONFIG_BRCM_FORCED_DRAM1_SIZE)
+	*dram1_mb = CONFIG_BRCM_FORCED_DRAM1_SIZE;
+#endif
+	pr_info("Using %lu MB + %lu MB RAM (from kernel configuration)\n",
+		*dram0_mb, *dram1_mb);
+#else
+	/* DRAM0_SIZE variable from CFE */
+	if (*dram0_mb) {
+		pr_info("Using %lu MB + %lu MB RAM (from CFE)\n",
+			*dram0_mb, *dram1_mb);
+		return;
+	}
+	*dram0_mb = probe_ram_size();
+#endif
+}
+
+static void __init __brcm_wraparound_check(unsigned long start,
+	unsigned long midpoint, int memc_no)
+{
+	int found = 0, idx = read_c0_wired();
+	unsigned long *a, *b, old_a, va = FIXADDR_TOP - 0x2000;
+
+	brcm_write_tlb_entry(idx, ENTRYLO_UNCACHED(start),
+		ENTRYLO_UNCACHED(midpoint), va, PM_4K);
+
+	a = (unsigned long *)(va);
+	b = (unsigned long *)(va + 0x1000);
+
+	old_a = *a;
+	mb();
+
+	*b ^= 0x55555555;
+	mb();
+
+	if (*a != old_a)
+		found = 1;
+	mb();
+
+	*b ^= 0x55555555;
+	mb();
+
+	/* this should always match, but check anyway */
+	if (*a != old_a)
+		found = 1;
+
+	brcm_write_tlb_entry(idx, ENTRYLO_INVALID(), ENTRYLO_INVALID(),
+		UNIQUE_ENTRYHI(idx), PM_4K);
+
+	if (found)
+		panic("DRAM%d wraparound detected at 0x%lx\n",
+			memc_no, midpoint);
+}
+
+void __init brcm_wraparound_check(void)
+{
+	/*
+	 * Find the middle of the DRAM region, compensating for the memory
+	 * hole at the 256MB mark if necessary.  If there is no wraparound
+	 * at the middle address, everything else should be OK.
+	 */
+	if (brcm_dram0_size_mb >= 512)
+		__brcm_wraparound_check(0,
+			(brcm_dram0_size_mb << 19) + 0x10000000, 0);
+	else
+		__brcm_wraparound_check(0, brcm_dram0_size_mb << 19, 0);
+
+	if (brcm_dram1_size_mb)
+		__brcm_wraparound_check(MEMC1_START,
+			brcm_dram1_size_mb << 19, 1);
+}
diff --git a/arch/mips/brcmstb/prom.c b/arch/mips/brcmstb/prom.c
new file mode 100644
index 0000000..2a2a6dd
--- /dev/null
+++ b/arch/mips/brcmstb/prom.c
@@ -0,0 +1,592 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/ctype.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/root_dev.h>
+#include <linux/types.h>
+#include <linux/smp.h>
+#include <linux/bmoca.h>
+#include <linux/version.h>
+#include <linux/serial_reg.h>
+#include <linux/io.h>
+#include <linux/string.h>
+#include <linux/compiler.h>
+#include <linux/pci.h>
+#include <linux/console.h>
+#include <linux/mtd/mtd.h>
+
+#include <asm/bootinfo.h>
+#include <asm/r4kcache.h>
+#include <asm/traps.h>
+#include <asm/cacheflush.h>
+#include <asm/mipsregs.h>
+#include <asm/hazards.h>
+#include <asm/smp-ops.h>
+#include <asm/reboot.h>
+#include <asm/fw/cfe/cfe_api.h>
+#include <asm/fw/cfe/cfe_error.h>
+
+#include <linux/brcmstb/brcmstb.h>
+#include <spaces.h>
+
+#if defined(CONFIG_DREAMBOX_DM7080) || defined(CONFIG_DREAMBOX_DM820)
+#include <linux/initrd.h>
+
+static inline unsigned long __init aon_read_blob_table(unsigned long idx)
+{
+	return BDEV_RD(AON_RAM_BASE + ((16 + idx) << 2));
+}
+
+static inline unsigned long __init aon_read_mac(unsigned long idx)
+{
+	return BDEV_RD(AON_RAM_BASE + ((126 + idx) << 2));
+}
+
+static void __init parse_blob_table(void)
+{
+	unsigned long len;
+	unsigned long ptr;
+	unsigned long i;
+
+	if (aon_read_blob_table(0) != 0x6c6f6f70)
+		return;
+
+	len = aon_read_blob_table(1);
+	if (len > 8) {
+		printk(KERN_ERR "%s: Invalid length (%#lx), ignoring table\n", __func__, len);
+		return;
+	}
+
+	ptr = 2;
+	for (i = 0; i < len; i++) {
+		unsigned long type = aon_read_blob_table(ptr++);
+		unsigned long addr = aon_read_blob_table(ptr++);
+		unsigned long size = aon_read_blob_table(ptr++);
+
+		if (type == 0 || type == 0xFFFFFFFF ||
+		    addr == 0 || addr == 0xFFFFFFFF ||
+		    size == 0 || size == 0xFFFFFFFF) {
+			printk(KERN_ERR "%s: Invalid entry, aborting\n", __func__);
+			break;
+		}
+
+		if (addr >= BRCM_PCI_HOLE_START)
+			addr += BRCM_PCI_HOLE_SIZE;
+
+		if (addr >= PCIE_MEM_START) {
+			printk(KERN_ERR "%s: Invalid address, aborting\n", __func__);
+			break;
+		}
+
+		switch (type) {
+		case 4:
+		#if defined(CONFIG_BLK_DEV_INITRD)
+			initrd_start = (unsigned long)__va(addr);
+			initrd_end = (unsigned long)__va(addr + size);
+		#endif
+			break;
+		case 5:
+			strlcpy(arcs_cmdline, __va(addr), COMMAND_LINE_SIZE);
+			break;
+		}
+	}
+}
+
+static int parse_dreambox_mac_address(u8 *dest)
+{
+	unsigned long mac[2];
+
+	mac[0] = aon_read_mac(0);
+	mac[1] = aon_read_mac(1);
+
+	dest[0] = 0x00;
+	dest[1] = 0x09;
+	dest[2] = 0x34;
+
+	if (mac[0] != 9 || (mac[1] >> 24) != 0x34)
+		mac[1] = 0xaabbcc;
+
+	dest[3] = mac[1] >> 16;
+	dest[4] = mac[1] >> 8;
+	dest[5] = mac[1];
+
+	return 0;
+}
+#endif
+
+unsigned long __initdata cfe_seal;
+unsigned long __initdata cfe_entry;
+unsigned long __initdata cfe_handle;
+
+/***********************************************************************
+ * CFE bootloader queries
+ ***********************************************************************/
+
+static int __init hex(char ch)
+{
+	if (ch >= 'a' && ch <= 'f')
+		return ch-'a'+10;
+	if (ch >= '0' && ch <= '9')
+		return ch-'0';
+	if (ch >= 'A' && ch <= 'F')
+		return ch-'A'+10;
+	return -1;
+}
+
+static int __init hex16(const char *b)
+{
+	int d0, d1;
+
+	d0 = hex(b[0]);
+	d1 = hex(b[1]);
+	if ((d0 == -1) || (d1 == -1))
+		return -1;
+	return (d0 << 4) | d1;
+}
+
+void __init cfe_die(char *fmt, ...)
+{
+	char msg[128];
+	va_list ap;
+	int handle;
+	unsigned int count;
+
+	va_start(ap, fmt);
+	vsprintf(msg, fmt, ap);
+	strcat(msg, "\r\n");
+
+	if (cfe_seal != CFE_EPTSEAL)
+		goto no_cfe;
+
+	/* disable XKS01 so that CFE can access the registers */
+
+#if defined(CONFIG_CPU_BMIPS4380)
+	__write_32bit_c0_register($22, 3,
+		__read_32bit_c0_register($22, 3) & ~BIT(12));
+#elif defined(CONFIG_CPU_BMIPS5000)
+	__write_32bit_c0_register($22, 5,
+		__read_32bit_c0_register($22, 5) & ~BIT(8));
+#endif
+
+	handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
+	if (handle < 0)
+		goto no_cfe;
+
+	cfe_write(handle, msg, strlen(msg));
+
+	for (count = 0; count < 0x7fffffff; count++)
+		mb();
+	cfe_exit(0, 1);
+	while (1)
+		;
+
+no_cfe:
+	/* probably won't print anywhere useful */
+	printk(KERN_ERR "%s", msg);
+	BUG();
+
+	va_end(ap);
+}
+
+static inline int __init parse_eth0_hwaddr(const char *buf, u8 *out)
+{
+	int i, t;
+	u8 addr[6];
+
+	for (i = 0; i < 6; i++) {
+		t = hex16(buf);
+		if (t == -1)
+			return -1;
+		addr[i] = t;
+		buf += 3;
+	}
+	memcpy(out, addr, 6);
+
+	return 0;
+}
+
+static inline int __init parse_eth0_mdio_mode(const char *buf,
+	unsigned long *val)
+{
+	if (strcmp(buf, "boot") == 0 || strcmp(buf, "0") == 0)
+		*val = 1;
+	return 0;
+}
+
+static inline int __init parse_ulong(const char *buf, unsigned long *val)
+{
+	char *endp;
+	unsigned long tmp;
+
+	tmp = simple_strtoul(buf, &endp, 0);
+	if (*endp == 0) {
+		*val = tmp;
+		return 0;
+	}
+	return -1;
+}
+
+static inline int __init parse_hex(const char *buf, unsigned long *val)
+{
+	char *endp;
+	unsigned long tmp;
+
+	tmp = simple_strtoul(buf, &endp, 16);
+	if (*endp == 0) {
+		*val = tmp;
+		return 0;
+	}
+	return -1;
+}
+
+static inline int __init parse_cmdline(const char *buf, char *dst)
+{
+	strlcpy(dst, buf, COMMAND_LINE_SIZE);
+	return 0;
+}
+
+static inline int __init parse_string(const char *buf, char *dst)
+{
+	strlcpy(dst, buf, CFE_STRING_SIZE);
+	return 0;
+}
+
+static char __initdata cfe_buf[COMMAND_LINE_SIZE];
+
+static void __init __maybe_unused cfe_read_configuration(void)
+{
+	int fetched = 0;
+
+	printk(KERN_INFO "Fetching vars from bootloader... ");
+#if defined(CONFIG_DREAMBOX_DM7080) || defined(CONFIG_DREAMBOX_DM820)
+	parse_dreambox_mac_address(brcm_primary_macaddr);
+#endif
+	if (cfe_seal != CFE_EPTSEAL) {
+		printk(KERN_CONT "none present, using defaults.\n");
+#if defined(CONFIG_DREAMBOX_DM7080) || defined(CONFIG_DREAMBOX_DM820)
+		parse_eth0_mdio_mode("1", &brcm_eth0_no_mdio);
+		parse_string("RGMII_NO_ID", brcm_eth0_phy);
+		parse_string("probe", brcm_eth0_phyaddr);
+		parse_ulong("1000", &brcm_eth0_speed);
+		parse_ulong("1024", &brcm_dram0_size_mb);
+		parse_ulong("1024", &brcm_dram1_size_mb);
+		parse_ulong("768", &brcm_dram1_linux_mb);
+		parse_string("BCM97435B0", brcm_cfe_boardname);
+		parse_ulong("16", &brcm_mtd_flash_size_mb);
+		parse_string("SPI", brcm_mtd_flash_type);
+		parse_blob_table();
+#endif
+		return;
+	}
+
+#define DPRINTK(...) do { } while (0)
+/* #define DPRINTK(...) printk(__VA_ARGS__) */
+
+#define FETCH(name, fn, arg) do { \
+	if (cfe_getenv(name, cfe_buf, COMMAND_LINE_SIZE) == CFE_OK) { \
+		DPRINTK("Fetch var '%s' = '%s'\n", name, cfe_buf); \
+		fn(cfe_buf, arg); \
+		fetched++; \
+	} else { \
+		DPRINTK("Could not fetch var '%s'\n", name); \
+	} \
+	} while (0)
+
+	FETCH("ETH0_HWADDR", parse_eth0_hwaddr, brcm_primary_macaddr);
+	FETCH("ETH0_MDIO_MODE", parse_eth0_mdio_mode, &brcm_eth0_no_mdio);
+	FETCH("ETH0_PHY", parse_string, brcm_eth0_phy);
+	FETCH("ETH0_PHYADDR", parse_string, brcm_eth0_phyaddr);
+	FETCH("ETH0_SPEED", parse_ulong, &brcm_eth0_speed);
+
+	FETCH("DRAM0_SIZE", parse_ulong, &brcm_dram0_size_mb);
+	FETCH("DRAM1_SIZE", parse_ulong, &brcm_dram1_size_mb);
+	FETCH("CFE_BOARDNAME", parse_string, brcm_cfe_boardname);
+	FETCH("BOOT_FLAGS", parse_cmdline, arcs_cmdline);
+
+	FETCH("LINUX_FFS_STARTAD", parse_hex, &brcm_mtd_rootfs_start);
+	FETCH("LINUX_FFS_SIZE", parse_hex, &brcm_mtd_rootfs_len);
+	FETCH("LINUX_PART_STARTAD", parse_hex, &brcm_mtd_kernel_start);
+	FETCH("LINUX_PART_SIZE", parse_hex, &brcm_mtd_kernel_len);
+	FETCH("OCAP_PART_STARTAD", parse_hex, &brcm_mtd_ocap_start);
+	FETCH("OCAP_PART_SIZE", parse_hex, &brcm_mtd_ocap_len);
+	FETCH("FLASH_SIZE", parse_ulong, &brcm_mtd_flash_size_mb);
+	FETCH("FLASH_TYPE", parse_string, brcm_mtd_flash_type);
+
+	printk(KERN_CONT "found %d vars.\n", fetched);
+}
+
+/***********************************************************************
+ * Early printk
+ ***********************************************************************/
+
+static unsigned long brcm_early_uart;
+
+#define UART_REG(x)		(brcm_early_uart + ((x) << 2))
+#if defined(CONFIG_DREAMBOX_DM7080) || defined(CONFIG_DREAMBOX_DM820)
+#define BAUD			1000000
+#else
+#define BAUD			115200
+#endif
+
+static void __init init_port(unsigned int baud)
+{
+	unsigned int divisor;
+
+	BDEV_WR(UART_REG(UART_LCR), 0x3);	/* 8n1 */
+	BDEV_WR(UART_REG(UART_IER), 0);		/* no interrupt */
+	BDEV_WR(UART_REG(UART_FCR), 0);		/* no fifo */
+	BDEV_WR(UART_REG(UART_MCR), 0x3);	/* DTR + RTS */
+
+	BDEV_SET(UART_REG(UART_LCR), UART_LCR_DLAB);
+#if defined(CONFIG_BRCM_IKOS)
+	/* Reverse-engineer brcm_base_baud0 from the bootloader's setting */
+
+	divisor = (BDEV_RD(UART_REG(UART_DLM)) << 8) |
+		BDEV_RD(UART_REG(UART_DLL));
+	brcm_base_baud0 = divisor * baud;
+#endif
+	divisor = (brcm_base_baud0 + baud/2) / baud;
+	BDEV_WR(UART_REG(UART_DLL), divisor & 0xff);
+	BDEV_WR(UART_REG(UART_DLM), (divisor >> 8) & 0xff);
+	BDEV_UNSET(UART_REG(UART_LCR), UART_LCR_DLAB);
+}
+
+void prom_putchar(char x)
+{
+	while (!(BDEV_RD(UART_REG(UART_LSR)) & UART_LSR_THRE))
+		;
+	BDEV_WR(UART_REG(UART_TX), x);
+}
+
+static void __init brcm_setup_early_printk(void)
+{
+	char *arg = strstr(arcs_cmdline, "console=");
+	int dev = CONFIG_BRCM_CONSOLE_DEVICE;
+	const unsigned long base[] = {
+		BCHP_UARTA_REG_START, BCHP_UARTB_REG_START,
+#ifdef CONFIG_BRCM_HAS_UARTC
+		BCHP_UARTC_REG_START,
+#endif
+	};
+	unsigned int baud = 0;
+	unsigned int field = 0;
+
+	/*
+	 * quick command line parse to pick the early printk console
+	 * valid formats:
+	 *   console=ttyS0,115200
+	 *   console=0,115200
+	 */
+	while (arg && *arg != '\0' && *arg != ' ') {
+		if ((*arg >= '0') && (*arg <= (field ? '9' : '3'))) {
+			unsigned int digit = *arg - '0';
+			if (field == 0 && digit < ARRAY_SIZE(base)) {
+				dev = digit;
+			} else if (field == 1) {
+				baud *= 10;
+				baud += digit;
+			} else {
+				break;
+			}
+		} else if (*arg == ',') {
+			field++;
+		}
+		arg++;
+	}
+	brcm_early_uart = base[dev];
+	init_port(baud ? baud : BAUD);
+}
+
+/***********************************************************************
+ * Main entry point
+ ***********************************************************************/
+
+void __init prom_init(void)
+{
+	char *ptr;
+
+	cfe_init(cfe_handle, cfe_entry);
+
+	bchip_check_compat();
+	brcmstb_cpu_setup();
+
+	/* default to SATA (where available) or MTD rootfs */
+#ifdef CONFIG_BRCM_HAS_SATA
+	ROOT_DEV = Root_SDA1;
+#else
+	ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, 0);
+#endif
+	root_mountflags &= ~MS_RDONLY;
+
+	bchip_set_features();
+
+#if defined(CONFIG_BRCM_IKOS_DEBUG)
+	strcpy(arcs_cmdline, "debug initcall_debug");
+#elif !defined(CONFIG_BRCM_IKOS)
+	cfe_read_configuration();
+#endif
+	brcm_setup_early_printk();
+
+	/* provide "ubiroot" alias to reduce typing */
+	if (strstr(arcs_cmdline, "ubiroot"))
+		strcat(arcs_cmdline, " ubi.mtd=rootfs rootfstype=ubifs "
+			"root=ubi0:rootfs");
+
+	ptr = strstr(arcs_cmdline, "memc1=");
+	if (ptr)
+		brcm_dram1_linux_mb = memparse(ptr + 6, &ptr) >> 20;
+
+	printk(KERN_INFO "Options: moca=%d sata=%d pcie=%d usb=%d\n",
+		brcm_moca_enabled, brcm_sata_enabled,
+		brcm_pcie_enabled, brcm_usb_enabled);
+
+	bchip_early_setup();
+	board_pinmux_setup();
+
+	board_get_ram_size(&brcm_dram0_size_mb, &brcm_dram1_size_mb);
+
+	do {
+		unsigned long dram0_mb = brcm_dram0_size_mb, mb;
+
+		mb = min(dram0_mb, BRCM_MAX_LOWER_MB);
+		dram0_mb -= mb;
+
+		add_memory_region(0, mb << 20, BOOT_MEM_RAM);
+		if (!dram0_mb)
+			break;
+
+#ifdef CONFIG_BRCM_UPPER_MEMORY
+		mb = min(dram0_mb, BRCM_MAX_UPPER_MB);
+		dram0_mb -= mb;
+
+		plat_wired_tlb_setup();
+		add_memory_region(UPPERMEM_START, mb << 20, BOOT_MEM_RAM);
+		if (!dram0_mb)
+			break;
+#endif
+
+#if defined(CONFIG_HIGHMEM)
+		add_memory_region(HIGHMEM_START, dram0_mb << 20, BOOT_MEM_RAM);
+		break;
+#endif
+		/*
+		 * We wound up here because the chip's architecture cannot
+		 * make use of all MEMC0 RAM in Linux.  i.e. no suitable
+		 * HIGHMEM or upper memory options are supported by the CPU.
+		 *
+		 * But we can still report the excess memory as a "bonus"
+		 * reserved (bmem) region, so the application can manage it.
+		 */
+		mb = brcm_dram0_size_mb - dram0_mb;	/* Linux memory */
+		if (!brcm_dram1_size_mb) {
+			printk(KERN_INFO "MEMC0 split: %lu MB -> Linux; "
+				"%lu MB -> extra bmem\n", mb, dram0_mb);
+			brcm_dram1_size_mb = dram0_mb;
+			brcm_dram1_start = UPPERMEM_START;
+		}
+	} while (0);
+
+#if defined(CONFIG_HIGHMEM) && defined(CONFIG_BRCM_HAS_1GB_MEMC1)
+	if (brcm_dram1_linux_mb > brcm_dram1_size_mb) {
+		printk(KERN_WARNING "warning: 'memc1=%luM' exceeds "
+			"available memory (%lu MB); ignoring\n",
+			brcm_dram1_linux_mb, brcm_dram1_size_mb);
+		brcm_dram1_linux_mb = 0;
+	} else if (brcm_dram1_linux_mb)
+		add_memory_region(MEMC1_START, brcm_dram1_linux_mb << 20,
+			BOOT_MEM_RAM);
+#else
+	if (brcm_dram1_linux_mb) {
+		printk(KERN_WARNING "warning: MEMC1 is not available on this "
+			"system; ignoring\n");
+		brcm_dram1_linux_mb = 0;
+	}
+#endif
+
+	board_ebase_setup = &bmips_ebase_setup;
+	register_smp_ops(&bmips_smp_ops);
+}
+
+/***********************************************************************
+ * NMI hook
+ ***********************************************************************/
+
+static void (*nmi_fn)(struct pt_regs *);
+
+static int brcm_nmi_notifier(struct notifier_block *nb,
+	unsigned long val, void *v)
+{
+	nmi_fn(NULL);
+	return 0;
+}
+
+void brcm_set_nmi_handler(void (*fn)(struct pt_regs *))
+{
+	nmi_notifier(brcm_nmi_notifier, 0);
+}
+EXPORT_SYMBOL(brcm_set_nmi_handler);
+
+/***********************************************************************
+ * Miscellaneous utility functions
+ ***********************************************************************/
+
+static char brcm_system_type[64];
+
+const char *get_system_type(void)
+{
+	u32 class = BRCM_CHIP_ID();
+
+	if (class >> 16 == 0)
+		class >>= 8;
+	else
+		class >>= 12;
+
+	snprintf(brcm_system_type, 64, "BCM%04x%02X %s platform",
+		BRCM_CHIP_ID(), BRCM_CHIP_REV() + 0xa0,
+		class == 0x35 ? "DTV" :
+		(class == 0x76 ? "DVD" : "STB"));
+
+	return (const char *)brcm_system_type;
+}
+
+void __init prom_free_prom_memory(void) {}
+
+static void brcm_machine_restart_mips(char *command)
+{
+	/* On ARM the argument needs to be const */
+	brcm_machine_restart(command);
+}
+
+void __init plat_mem_setup(void)
+{
+	_machine_restart = brcm_machine_restart_mips;
+	_machine_halt = brcm_machine_halt;
+	pm_power_off = brcm_machine_halt;
+
+	brcm_wraparound_check();
+	panic_timeout = 180;
+
+#ifdef CONFIG_PCI
+	pcibios_plat_setup = brcmstb_pcibios_setup;
+#endif
+
+	add_preferred_console("ttyS", CONFIG_BRCM_CONSOLE_DEVICE, "115200");
+}
diff --git a/arch/mips/brcmstb/s3_standby.S b/arch/mips/brcmstb/s3_standby.S
new file mode 100644
index 0000000..971b432
--- /dev/null
+++ b/arch/mips/brcmstb/s3_standby.S
@@ -0,0 +1,279 @@
+/*
+ * Copyright (C) 2011 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+#include <asm/addrspace.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#define REG_OFFSET		(KSEG1 | BCHP_PHYSICAL_OFFSET)
+#define REG(x)			(REG_OFFSET + (x))
+
+/*
+ * Bootloader parameters for warm boot:
+ *	byte offset	value
+ *	0-3:		magic word
+ *	4-7:		reentry address
+ *	8-11:		m2m descriptors PA
+ *	12-15:		encryption slot
+ *	16-19:		address of hash
+ *	20-35:		hash
+ */
+	.text
+	.set		noreorder
+	.align		5
+	.global		s3_reentry
+
+#if defined(CONFIG_CPU_BMIPS5000)
+#define CACHE_WRITEBACK_CMD	Hit_Writeback_Inv_SD
+#else
+#define CACHE_WRITEBACK_CMD	Hit_Writeback_Inv_D
+#endif
+
+/*
+ * We do not need stack frame, the entire context gets saved
+ * in a dedicated structure brcm_pm_s3_context
+ * Upon warm reboot the context gets restored from this structure
+ * Parameters:
+ *	a0: options
+ *	a1: dram encoder start function or NULL if not installed
+ *	a2: d-cache line size
+ */
+	LEAF(brcm_pm_s3_standby_asm)
+
+	la	t0, s3_context
+	/* general purpose registers */
+	sw	ra, 0(t0)
+	sw	s0, 4(t0)
+	sw	s1, 8(t0)
+	sw	s2, 12(t0)
+	sw	s3, 16(t0)
+	sw	s4, 20(t0)
+	sw	s5, 24(t0)
+	sw	s6, 28(t0)
+	sw	s7, 32(t0)
+	sw	gp, 36(t0)
+	sw	sp, 40(t0)
+	sw	fp, 44(t0)
+
+	mfc0	t1, CP0_STATUS
+# save cp0 sr
+	sw	t1, 48(t0)
+
+# Write-back gp registers - cache will be gone after wakeup
+# align context area address to the cache line
+	addiu	t1, a2, -1
+	not	t1
+	and	t0, t1
+
+# flush at least 64 bytes
+	addiu	t2, t0, 64
+	and	t2, t1
+
+1:	cache	CACHE_WRITEBACK_CMD, 0(t0)
+	bne	t0, t2, 1b
+	addu	t0, a2
+
+	beqz	a1, skip_dram_encode
+	nop
+
+	/*
+	 * Call DRAM encoder start method if it was installed
+	 * Nobody can modify DRAM content by now.
+	 */
+	jal	a1
+	nop
+
+/* NOTE: Uncommenting this block will force hash mismatch
+ * if .data segment is in the authentication region.
+ * Use for CFE secure warm boot testing.
+ */
+#	la	t0, secure_s3_dummy_data
+#	lw	t1, 0(t0)
+#	addi	t1, 1
+#	sw	t1, 0(t0)
+#	cache	CACHE_WRITEBACK_CMD, 0(t0)
+#	nop
+
+skip_dram_encode:
+
+	li	t0, REG(BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT)
+	li	t1, 0xffff
+	sw	t1, 0(t0)
+	lw	zero, 0(t0)
+
+# deep power down request
+pd_request:
+	li	t0, REG(BCHP_AON_CTRL_PM_CTRL)
+# SET: pm_deep_standby, pm_warm_boot, pm_enable_pll_pwrdn
+	li	t1, 0x32
+	sw	zero, 0(t0)
+	lw	zero, 0(t0)
+	sw	t1, 0(t0)
+	lw	zero, 0(t0)
+
+# SET: pm_start_pwrdn
+	li	t1, 0x33
+	sw	t1, 0(t0)
+	lw	zero, 0(t0)
+
+/***********************************************************************
+ * Wait for interrupt
+ ***********************************************************************/
+wait_loop:
+# enable int2 and then wait for an interrupt
+	mfc0	t0, CP0_STATUS
+
+	li	t1, ~(ST0_IM | ST0_IE)
+	and	t0, t1
+	ori	t0, STATUSF_IP2
+	mtc0	t0, CP0_STATUS
+	nop
+	nop
+	nop
+	ori	t0, ST0_IE
+	mtc0	t0, CP0_STATUS
+	wait
+	nop
+
+s3_reentry:
+
+#ifdef CONFIG_CPU_BMIPS5000
+# clear CRS and JTB
+	li	t0, (0x06 << 16)
+	mtc0	t0, $22, 2
+	ssnop
+	ssnop
+	ssnop
+
+	li	t0, (0x04 << 16)
+	mtc0	t0, $22, 2
+	ssnop
+	ssnop
+	ssnop
+#endif
+
+#ifdef CONFIG_CPU_BMIPS4380
+# flush 4-entry call/return stack
+	jal	1f
+	nop
+1:	jal	1f
+	nop
+1:	jal	1f
+	nop
+1:	jal	1f
+	nop
+1:
+#endif
+
+# restore sr
+	sync
+	nop
+
+s3_standby_exit:
+#ifdef CONFIG_BRCM_UPPER_768MB
+#if defined(CONFIG_CPU_BMIPS4380)
+	mfc0	t0, $22, 3
+	li	t1, 0x1ff0
+	li	t2, (1 << 12) | (1 << 9)
+	or	t0, t1
+	xor	t0, t1
+	or	t0, t2
+	mtc0	t0, $22, 3
+#elif defined(CONFIG_CPU_BMIPS5000)
+	mfc0	t0, $22, 5
+	li	t1, 0x01ff
+	li	t2, (1 << 8) | (1 << 5)
+	or	t0, t1
+	xor	t0, t1
+	or	t0, t2
+	mtc0	t0, $22, 5
+#endif
+#endif
+	sync
+	nop
+
+	/* setup mmu defaults */
+	mtc0	zero, CP0_WIRED
+	mtc0	zero, CP0_ENTRYHI
+	li	k0, PM_DEFAULT_MASK
+	mtc0	k0, CP0_PAGEMASK
+
+#ifdef CONFIG_BRCM_UPPER_MEMORY
+	li	sp, BMIPS_WARM_RESTART_VEC
+	la	k0, plat_wired_tlb_setup
+	jalr	k0
+	nop
+#endif
+
+# return to caller
+	/* general purpose registers */
+	la	t0, s3_context
+	lw	ra, 0(t0)
+	lw	s0, 4(t0)
+	lw	s1, 8(t0)
+	lw	s2, 12(t0)
+	lw	s3, 16(t0)
+	lw	s4, 20(t0)
+	lw	s5, 24(t0)
+	lw	s6, 28(t0)
+	lw	s7, 32(t0)
+	lw	gp, 36(t0)
+	lw	sp, 40(t0)
+	lw	fp, 44(t0)
+
+# restore cp0 sr
+	lw	t1, 48(t0)
+	mtc0	t1, CP0_STATUS
+
+	li	v0, 1
+	jr	ra
+	nop
+
+
+	END(brcm_pm_s3_standby_asm)
+
+	.align 4
+	.data
+secure_s3_dummy_data:	.word 0
+
+#define UART_LSR_OFFSET		0x14
+#define UART_LSR_MASK		BCHP_UARTA_LSR_THRE_MASK
+#define UART_TX_OFFSET		0x00
+
+__dputc:
+
+	li	t1, REG(BCHP_UARTA_REG_START)
+1:
+	lw	t2, UART_LSR_OFFSET(t1)
+	andi	t2, UART_LSR_MASK
+	beqz	t2, 1b
+	nop
+
+	sw	a0, UART_TX_OFFSET(t1)
+
+1:	lw	t2, UART_LSR_OFFSET(t1)
+	andi	t2, UART_LSR_MASK
+	beqz	t2, 1b
+	nop
+	jr	ra
+	nop
+
+s3_standby_section_end:
+	nop
diff --git a/arch/mips/brcmstb/standby.S b/arch/mips/brcmstb/standby.S
new file mode 100644
index 0000000..869e9cf
--- /dev/null
+++ b/arch/mips/brcmstb/standby.S
@@ -0,0 +1,1170 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+#include <asm/addrspace.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#define REG_OFFSET		(KSEG1 | BCHP_PHYSICAL_OFFSET)
+#define REG(x)			(REG_OFFSET + (x))
+#define UPG_USEC_TICKS		(UPGTMR_FREQ / 1000000)
+
+/* debug output - BRCM_STANDBY_VERBOSE */
+#define UART_BASE		BCHP_UARTA_REG_START
+#define UART_LSR_OFFSET		0x14
+#define UART_LSR_MASK		BCHP_UARTA_LSR_THRE_MASK
+#define UART_TX_OFFSET		0x00
+
+#define USE_WATCHDOG		0
+
+#if defined(BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK) || \
+ defined(BCHP_SUN_TOP_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK)
+#define PM_CMD_BASE		0x0b
+#else
+#define PM_CMD_BASE		0x03
+#endif
+
+#if defined(CONFIG_CPU_BMIPS5000)
+#define PM_USE_MIPS_READY	0x04
+#else
+#define PM_USE_MIPS_READY	0x00
+#endif
+
+#define PM_STANDBY_COMMAND	(PM_CMD_BASE|PM_USE_MIPS_READY)
+
+#ifdef BCHP_MEMC_DDR23_APHY_WL0_0_BYTE0_VCDL_PHASE_CNTL
+#define VCDL_SAVE_REG		BCHP_MEMC_DDR23_APHY_WL1_0_SPARE0_RW
+#define RELOAD_VCDL		1
+#else
+#define RELOAD_VCDL		0
+#endif
+
+#define PM_WAIT_COUNT		BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT
+#define PM_CONTROL		BCHP_AON_CTRL_PM_CTRL
+#define PM_STATUS		BCHP_AON_CTRL_PM_STATUS
+#define PM_STATUS_bsp_ready	BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK
+
+#define FLAGREG			s5
+
+	.text
+	.set	noreorder
+	.align	5
+
+# a0 is icache line size
+# a1 is the interrupt vector (or general exception base)
+# a2 is the interrupt vector size
+# a3 is brcm_pm_standby_flags
+
+	LEAF(brcm_pm_standby_asm)
+	subu	sp, 64
+	sw	ra, 0(sp)
+	sw	s0, 4(sp)
+	sw	s1, 8(sp)
+	sw	s2, 12(sp)
+	sw	s3, 16(sp)
+	sw	s4, 20(sp)
+	sw	s5, 24(sp)
+	sw	s6, 28(sp)
+	sw	s7, 32(sp)
+
+	move	FLAGREG, a3
+
+	bal	memc_settings_valid
+	nop
+	bnez	v0, standby_exit
+	nop
+
+#ifdef BCHP_MEMC_DDR23_APHY_WL0_0_BYTE0_VCDL_PHASE_CNTL
+	/*
+	 * Save VCDL values:
+	 * WL0_0_BYTE0 -> bits 07:00
+	 * WL0_0_BYTE1 -> bits 15:08
+	 * WL1_0_BYTE0 -> bits 23:16
+	 * WL1_0_BYTE1 -> bits 31:24
+	 */
+	li	t0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_BYTE0_VCDL_PHASE_CNTL)
+	lw	t1, 0(t0)
+	andi	t2, t1, 0x1f
+	lw	t1, 4(t0)
+	andi	t1, t1, 0x1f
+	sll	t1, 8
+	or	t2, t1
+
+	li	t0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_BYTE0_VCDL_PHASE_CNTL)
+	lw	t1, 0(t0)
+	andi	t1, t1, 0x1f
+	sll	t1, 16
+	or	t2, t1
+	lw	t1, 4(t0)
+	andi	t1, t1, 0x1f
+	sll	t1, 24
+	or	t2, t1
+
+	li	t0, REG(VCDL_SAVE_REG)
+	sw	t2, 0(t0)
+	lw	zero, 0(t0)
+#endif
+
+#ifdef CONFIG_CPU_BMIPS5000
+	/*
+	 * reset jump target buffer and call/return stack, to avoid
+	 * unexpected accesses to DRAM
+	 */
+	li	t0, 0x00040000
+	mtc0	t0, $22, 2
+	mfc0	t0, $22, 2
+
+	li	t0, 0x00060000
+	mtc0	t0, $22, 2
+	mfc0	t0, $22, 2
+
+	ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ;
+	ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ;
+	ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ;
+	ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop
+#endif
+
+# lock the asm section into the I-cache
+	move	s0, a0
+	addiu	t1, s0, -1
+	not	t1
+
+	la	t0, brcm_pm_standby_asm
+	and	t0, t1
+
+	la	t2, passiveIRQ_end
+	and	t2, t1
+
+1:	cache	0x1c, 0(t0)
+	bne	t0, t2, 1b
+	addu	t0, s0
+
+# now lock the interrupt vector
+	move	t0, zero
+2:
+	cache	0x1c, 0(a1)
+	addu	a1, s0
+	addu	t0, s0
+	ble	t0, a2, 2b
+	nop
+
+	bal	dputc
+	li	a0, 's'
+
+/***********************************************************************
+ * Flush memory transactions and put MEMC into standby
+ ***********************************************************************/
+	sync
+
+#ifdef CONFIG_BRCM_HAS_ANALOG_DDR_PHY
+	li	t0, BRCM_STANDBY_DDR_PLL_ON
+	and	t0, FLAGREG
+	beqz	t0, 2f
+	nop
+
+	bal	set_pll_frequency
+	li	a0, 0x3d43
+
+	bal	set_pll_frequency
+	li	a0, 0x2d43
+2:
+#endif
+
+#if !defined(CONFIG_BRCM_PWR_HANDSHAKE)
+	li	t0, REG(BCHP_MEMC_DDR_0_SSPD_CMD)
+	li	t1, BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK
+	sw	t1, 0(t0)
+
+	li	t0, REG(BCHP_MEMC_DDR_0_POWER_DOWN_STATUS)
+1:	lw	t1, 0(t0)
+	andi	t1, BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK
+	beqz	t1, 1b
+	nop
+
+	bal	dputc
+	li	a0, 'd'
+
+#endif
+
+/*
+ * enable power down of MEMSYS PLL
+ * 7436 and 7425 only
+ */
+#if defined(CONFIG_BCM7346)
+	li	t0, REG(BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT)
+	li	t1, BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_MASK
+	sw	t1, 0(t0)
+#endif
+
+#if defined(CONFIG_BCM7425)
+	li	t0, REG(BCHP_CLKGEN_MEMSYS_0_32_POWER_MANAGEMENT)
+	li	t1, BCHP_CLKGEN_MEMSYS_0_32_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_MASK
+	sw	t1, 0(t0)
+#endif
+
+# power down request
+2:
+	/* delay if requested by the user: 4 * 30s */
+	li	t0, BRCM_STANDBY_DELAY
+	and	t0, FLAGREG
+	beqz	t0, 2f
+	nop
+
+	bal	dputc
+	li	a0, 'w'
+
+	li	v1, 4
+1:	li	a0, (UPGTMR_FREQ * 30)
+	bal	delay
+	addiu	v1, -1
+	bnez	v1, 1b
+	nop
+
+	bal	dputc
+	li	a0, 'W'
+
+# power down request
+2:
+	/* set wait count */
+	li	t0, REG(PM_WAIT_COUNT)
+	li	t1, 0xffff
+	sw	t1, 0(t0)
+	lw	zero, 0(t0)
+
+	li	t0, REG(PM_CONTROL)
+	li	t1, PM_STANDBY_COMMAND
+	sw	zero, 0(t0)
+	lw	zero, 0(t0)
+	sw	t1, 0(t0)
+	lw	t1, 0(t0)
+
+/***********************************************************************
+ * Wait for interrupt
+ ***********************************************************************/
+
+wait_loop:
+# enable int2 and then wait for an interrupt
+	mfc0	t0, CP0_STATUS
+# save cp0 sr
+	move	s2, t0
+
+	li	t1, ~(ST0_IM | ST0_IE)
+	and	t0, t1
+	ori	t0, STATUSF_IP2
+	mtc0	t0, CP0_STATUS
+	nop
+	nop
+	nop
+	ori	t0, ST0_IE
+	mtc0	t0, CP0_STATUS
+	wait
+	nop
+
+/***********************************************************************
+ * Save wakeup timestamp in AON
+ ***********************************************************************/
+	li	t0, REG(BCHP_WKTMR_COUNTER)
+	lw	a0, 0(t0)	/* WKTMR_COUNTER */
+	lw	a1, 12(t0)	/* WKTMR_PRESCALER_VAL */
+	li	t0, REG(AON_RAM_BASE)
+	sw	a0, 0(t0)
+	sw	a1, 4(t0)
+
+/***********************************************************************
+ * Bring MEMC back up
+ ***********************************************************************/
+	bal	dputc
+	li	a0, 'M'
+
+#if USE_WATCHDOG
+# arm the watchdog timer
+	li	t0, REG(BCHP_TIMER_WDTIMEOUT)
+	li	t1, 3 * UPGTMR_FREQ
+	sw	t1, 0(t0)
+	lw	t1, 0(t0)
+
+	li	t0, REG(BCHP_TIMER_WDCMD)
+	li	t1, 0xff00
+	sw	t1, 0(t0)
+	lw	t1, 0(t0)
+	li	t1, 0x00ff
+	sw	t1, 0(t0)
+	lw	t1, 0(t0)
+#endif
+
+	/*
+	 * Bypass MEMC wakeup if DDR PLL is on
+	 */
+	li	t0, BRCM_STANDBY_DDR_PLL_ON
+	and	t0, FLAGREG
+	bnez	t0, 2f
+	nop
+
+	bal	wake_up_memc_0
+	nop
+
+2:
+	bal	dputc
+	li	a0, 'm'
+
+#if defined(CONFIG_BRCM_PWR_HANDSHAKE_V0)
+# disarm the BSP
+	li	t0, REG(BCHP_BSP_GLB_CONTROL_REG_START + 0x38)
+	lw	t1, 0(t0)
+	ori	t1, 0xff00
+	xori	t1, 0xfe00
+	sw	t1, 0(t0)
+
+	bal	dputc
+	li	a0, 'B'
+
+	li	t0, REG(PM_STATUS)
+	li	t2, PM_STATUS_bsp_ready
+1:
+	lw	t1, 0(t0)
+	and	t1, t2
+	bnez	t1, 1b
+	nop
+
+	bal	dputc
+	li	a0, 'b'
+#elif defined(CONFIG_BRCM_PWR_HANDSHAKE_V1)
+	li	t0, REG(BCHP_AON_CTRL_HOST_MISC_CMDS)
+	li	t1, BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_MASK
+	sw	t1, 0(t0)
+	lw	t1, 0(t0)
+#endif /* CONFIG_BRCM_PWR_HANDSHAKE_V0/V1 */
+
+	li	t0, REG(PM_CONTROL)
+	sw	zero, 0(t0)
+	lw	zero, 0(t0)
+
+#ifdef CONFIG_BRCM_HAS_ANALOG_DDR_PHY
+	li	t0, BRCM_STANDBY_DDR_PLL_ON
+	and	t0, FLAGREG
+	beqz	t0, 2f
+	nop
+
+	bal	set_pll_frequency
+	li	a0, 0x3d43
+
+	bal	set_pll_frequency
+	li	a0, 0x4a43
+2:
+#endif
+
+/***********************************************************************
+ * Unlock I$ lines and resume execution
+ ***********************************************************************/
+	sync
+
+rtn_from_wait:
+	bal	dputc
+	li	a0, 'S'
+
+# unlock I$ lines
+	addiu	t1, s0, -1
+	not	t1
+
+	la	t0, brcm_pm_standby_asm
+	and	t0, t1
+
+	la	t2, passiveIRQ_end
+	and	t2, t1
+
+1:	cache	Hit_Invalidate_I, 0(t0)
+	bne	t0, t2, 1b
+	addu	t0, s0
+
+	bal	dputc
+	li	a0, 'L'
+
+# restore sr
+	sync
+	nop
+
+	bal	dputc
+	li	a0, 'l'
+	bal	dputc
+	li	a0, 0x0d
+	bal	dputc
+	li	a0, 0x0a
+
+	mtc0	s2, CP0_STATUS
+	nop
+
+	li	v0, 0
+
+standby_exit:
+
+# return to caller
+	lw	s7, 32(sp)
+	lw	s6, 28(sp)
+	lw	s5, 24(sp)
+	lw	s4, 20(sp)
+	lw	s3, 16(sp)
+	lw	s2, 12(sp)
+	lw	s1, 8(sp)
+	lw	s0, 4(sp)
+	lw	ra, 0(sp)
+	addiu	sp, 64
+
+	jr	ra
+	nop
+	END(brcm_pm_standby_asm)
+
+# debug character output
+
+dputc:
+	/* INPUT: char in a0 */
+	/* USES: t1, t2 */
+
+	li	t1, BRCM_STANDBY_VERBOSE
+	and	t1, FLAGREG
+	bnez	t1, 1f
+	nop
+	jr	ra
+	nop
+
+1:
+	li	t1, REG(UART_BASE)
+1:
+	lw	t2, UART_LSR_OFFSET(t1)
+	andi	t2, UART_LSR_MASK
+	beqz	t2, 1b
+	nop
+
+	sw	a0, UART_TX_OFFSET(t1)
+
+1:	lw	t2, UART_LSR_OFFSET(t1)
+	andi	t2, UART_LSR_MASK
+	beqz	t2, 1b
+	nop
+	jr	ra
+	nop
+
+/***********************************************************************
+ * Delay loop
+ ***********************************************************************/
+
+delay:
+# need to reset TIMER1 since it is not normally used
+	li	t2, 0x0
+	li	t1, REG(BCHP_TIMER_TIMER1_CTRL)
+	sw	t2, 0(t1)
+	lw	t2, 0(t1)
+
+	li	t2, 0xbfffffff
+	sw	t2, 0(t1)
+	lw	t2, 0(t1)
+
+	li	t2, 0x3fffffff
+	li	t1, REG(BCHP_TIMER_TIMER1_STAT)
+	lw	t0, 0(t1)
+	and	t0, t2
+	add	t0, a0
+	not	t2
+	and	t2, t0
+	bnez	t2, delay_overflow
+	nop
+
+# wait for timer value (t2) to exceed expiry time (t0)
+1:	lw	t2, 0(t1)
+	sltu	t2, t2, t0
+	bnez	t2, 1b
+	nop
+
+	jr	ra
+	nop
+
+# timer1 overflow (this should never happen)
+delay_overflow:
+	move	t4, ra
+	bal	dputc
+	li	a0, 'O'
+
+	jr	t4
+	nop
+
+/***********************************************************************
+ * MEMC wakeup
+ ***********************************************************************/
+
+#ifdef CONFIG_BRCM_HAS_ANALOG_DDR_PHY
+
+#define SLEEP_1_MILLI_SEC		27000
+
+/***********************************************************************
+ * Delay routine
+ ***********************************************************************/
+LEAF(upg_sleep)
+
+	li	t0, REG(BCHP_TIMER_TIMER0_CTRL)
+	lw	t1, 0(t0)
+
+	/* TIMER_TIMER0_CTRL.MODE  = 1 => count down mode */
+	li	t2, BCHP_TIMER_TIMER0_CTRL_MODE_MASK
+	or	t1, t1, t2
+
+	/* TIMER_TIMER0_CTRL.TIMEOUT_VAL = a0 */
+
+	li	t2, BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_MASK
+	li	t3, BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_SHIFT
+
+	not	t2, t2
+	and	t1, t1, t2
+	sll	a0, a0, t3
+	or	t1, t1, a0
+
+	sw	t1, 0(t0)
+
+	li	t0, REG(BCHP_TIMER_TIMER_IS)
+	lw	t1, 0(t0)
+
+	/* TIMER_TIMER_IS.TMR0TO = 1 => clears this bit, resets time count */
+
+	#li	t2, ~BCHP_TIMER_TIMER_IS_TMR0TO_MASK
+	#and	t1, t1, t2
+	sw	t1, 0(t0)
+
+	/* TIMER_TIMER0_CTRL.ENA = 1 => start counting */
+
+	li	t0, REG(BCHP_TIMER_TIMER0_CTRL)
+	lw	t1, 0(t0)
+
+	li	t2, BCHP_TIMER_TIMER0_CTRL_ENA_MASK
+	or	t1, t1, t2
+	sw	t1, 0(t0)
+
+	li	t0, REG(BCHP_TIMER_TIMER_IS)
+	li	t2, BCHP_TIMER_TIMER_IS_TMR0TO_MASK
+
+1:	lw	t1, 0(t0)
+	and	t1, t1, t2
+	beq	zero, t1, 1b
+	nop
+
+	/* TIMER_TIMER0_CTRL.ENA = 0 => stop counting */
+
+	li	t0, REG(BCHP_TIMER_TIMER0_CTRL)
+	lw	t1, 0(t0)
+	li	t2, ~BCHP_TIMER_TIMER0_CTRL_ENA_MASK
+	and	t1, t1, t2
+	sw	t1, 0(t0)
+
+	jr	ra
+	nop
+
+END(upg_sleep)
+
+/***********************************************************************
+ * Main MEMC0 recovery function
+ ***********************************************************************/
+LEAF(wake_up_memc_0)
+
+	move	s7, ra
+
+	li	a0, 0
+	bal	set_memc_0_write_dqs_phase_cntl_direct
+	nop
+
+	li	a0, 0
+	bal	set_memc_0_write_dq_phase_cntl_direct
+	nop
+
+	li	a0, 0
+	bal	set_memc_0_pll_ch2_clk_phase_cntrl
+	nop
+
+	li	a0, 0
+	bal	set_memc_0_deskew_bypass_phase
+	nop
+
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_DDR_PAD_CNTRL)
+	lw	a1, 0(a0)
+	li	a2, ~(BCHP_MEMC_DDR23_APHY_WL0_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK)
+	and	a1, a1, a2
+	sw	a1, 0(a0)
+
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_DDR_PAD_CNTRL)
+	lw	a1, 0(a0)
+	li	a2, ~(BCHP_MEMC_DDR23_APHY_WL1_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK)
+	and	a1, a1, a2
+	sw	a1, 0(a0)
+
+
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_WORDSLICE_CNTRL_1)
+	lw	a1, 0(a0)
+	li	a2, ~(BCHP_MEMC_DDR23_APHY_WL0_0_WORDSLICE_CNTRL_1_PWRDN_DLL_ON_SELFREF_MASK)
+	and	a1, a1, a2
+	sw	a1, 0(a0)
+
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_WORDSLICE_CNTRL_1)
+	lw	a1, 0(a0)
+	li	a2, ~(BCHP_MEMC_DDR23_APHY_WL1_0_WORDSLICE_CNTRL_1_PWRDN_DLL_ON_SELFREF_MASK)
+	and	a1, a1, a2
+	sw	a1, 0(a0)
+
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_AC_0_POWERDOWN)
+	lw	a1, 0(a0)
+	li	a2, ~(BCHP_MEMC_DDR23_APHY_AC_0_POWERDOWN_PLLCLKS_OFF_ON_SELFREF_MASK)
+	and	a1, a1, a2
+	sw	a1, 0(a0)
+
+	bal	reprogram_ddr_pll
+	nop
+
+	jr	s7
+	nop
+
+END(wake_up_memc_0)
+
+/***********************************************************************
+ * VCDL incremental reload
+ * a0 - VCDL register
+ * a1 - maximum value
+ ***********************************************************************/
+reload_vcdl:
+	sll	v0, a1, 8
+	or	a1, v0		# max value to load
+
+	move	v1, zero
+vcdl_loop:
+	addi	v1, 0x0101
+	sw	v1, 0(a0)
+	lw	zero, 0(a0)
+	bne	v1, a1, vcdl_loop
+	nop
+
+	jr	ra
+	nop
+
+/***********************************************************************
+ * Set new DDR PLL frequency divider
+ * Used when suspending with DDR PLL on
+ * a0 - Frequency divider value
+ ***********************************************************************/
+LEAF(set_pll_frequency)
+
+	move	s3, ra
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_FREQ_CNTL)
+	sw	a0, 0(v0)
+	lw	zero, 0(v0)
+
+	li	a0, (27000)
+	bal	upg_sleep
+	nop
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_DDR_PLL_LOCK_STATUS)
+	li	a0, BCHP_MEMC_DDR23_APHY_AC_0_DDR_PLL_LOCK_STATUS_LOCK_STATUS_MASK
+1:
+	lw	v1, 0(v0)
+	and	v1, v1, a0
+
+	beqz	v1, 1b
+	nop
+
+	jr	s3
+	nop
+END(set_pll_frequency)
+
+/***********************************************************************
+ * DDR PLL reset and reconfiguration
+ ***********************************************************************/
+LEAF(reprogram_ddr_pll)
+
+	move	s6, ra
+
+	/* reset the freq divider */
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_RESET)
+	li	v1, BCHP_MEMC_DDR23_APHY_AC_0_RESET_FREQ_DIV_RESET_MASK
+	lw	a0, 0(v0)
+	or	a0, a0, v1
+	sw	a0, 0(v0)
+
+	li	a0, (SLEEP_1_MILLI_SEC)
+	bal	upg_sleep
+	nop
+
+	/* reset the vcxo */
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_RESET)
+	li	v1, BCHP_MEMC_DDR23_APHY_AC_0_RESET_VCXO_RESET_MASK
+	lw	a0, 0(v0)
+	or	a0, a0, v1
+	sw	a0, 0(v0)
+
+	li	a0, (SLEEP_1_MILLI_SEC)
+	bal	upg_sleep
+	nop
+
+	/* reset DATAPATH_216, RD_DATAPATH_RESET, RESET_DATAPATH_DDR  */
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_RESET)
+	li	v1, (BCHP_MEMC_DDR23_APHY_AC_0_RESET_DATAPATH_216_RESET_MASK | \
+		     BCHP_MEMC_DDR23_APHY_AC_0_RESET_RD_DATAPATH_RESET_MASK | \
+		     BCHP_MEMC_DDR23_APHY_AC_0_RESET_DATAPATH_DDR_RESET_MASK)
+	lw	a0, 0(v0)
+	or	a0, a0, v1
+	sw	a0, 0(v0)
+
+	/* de-assert reset from vcxo */
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_RESET)
+	li	v1, ~BCHP_MEMC_DDR23_APHY_AC_0_RESET_VCXO_RESET_MASK
+	lw	a0, 0(v0)
+	and	a0, a0, v1
+	sw	a0, 0(v0)
+
+	/* de-assert reset from freq divider */
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_RESET)
+	li	v1, ~BCHP_MEMC_DDR23_APHY_AC_0_RESET_FREQ_DIV_RESET_MASK
+	lw	a0, 0(v0)
+	and	a0, a0, v1
+	sw	a0, 0(v0)
+
+	/* wait for 1ms for stable clock */
+	li	a0, (SLEEP_1_MILLI_SEC)
+	bal	upg_sleep
+	nop
+
+	/* check for pll lock */
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_DDR_PLL_LOCK_STATUS)
+	li	a0, BCHP_MEMC_DDR23_APHY_AC_0_DDR_PLL_LOCK_STATUS_LOCK_STATUS_MASK
+1:
+	lw	v1, 0(v0)
+	and	v1, v1, a0
+
+	beqz	v1, 1b
+	nop
+
+	li	a1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA4)
+	lw	a0, 0(a1)
+
+	bal	set_memc_0_wl0_dq_phase
+	nop
+
+	/* set wl1_dq phase */
+	li	a1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA5)
+	lw	a0, 0(a1)
+
+	bal	set_memc_0_wl1_dq_phase
+	nop
+
+	/* set ch2 phase */
+	li	a1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA6)
+	lw	a0, 0(a1)
+
+	move	a1, a0
+	and	a0, a0, zero
+1:
+	bal	set_memc_0_pll_ch2_clk_phase_cntrl
+	nop
+	add	a0, a0, 1
+
+	bne	a0, a1, 1b
+	nop
+
+	/* set ch6 phase */
+	li	a1, REG(BCHP_MEMC_MISC_0_SCRATCH_0)
+	lw	a0, 0(a1)
+
+	move	a1, a0
+	and	a0, a0, zero
+1:
+	bal	set_memc_0_deskew_bypass_phase
+	nop
+
+	add	a0, a0, 1
+
+	bne	a0, a1, 1b
+	nop
+
+	/* set wl0_dqs0 phases */
+	li	a1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA0)
+	lw	a0, 0(a1)
+
+	bal	set_memc_0_dqs0_phase
+	nop
+
+	/* set wl0_dqs1 phases */
+
+	li	a1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA1)
+	lw	a0, 0(a1)
+
+	bal	set_memc_0_dqs1_phase
+	nop
+
+	/* set wl1_dqs0 phases */
+
+	li	a1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA2)
+	lw	a0, 0(a1)
+
+	bal	set_memc_0_dqs2_phase
+	nop
+	/* set wl1_dqs1 phases */
+
+	li	a1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA3)
+	lw	a0, 0(a1)
+
+	bal	set_memc_0_dqs3_phase
+	nop
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL)
+	lw	v1, 0(v0)
+	ori     v1, (BCHP_MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL_DEVCLK_OFF_ON_SELFREF_MASK | BCHP_MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK)
+	xori	v1, (BCHP_MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL_DEVCLK_OFF_ON_SELFREF_MASK | BCHP_MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK)
+	sw	v1, 0(v0)
+	lw	zero, 0(v0)
+
+	li	a0, (SLEEP_1_MILLI_SEC)
+	bal	upg_sleep
+	nop
+
+	/* reset the word slice dll */
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_WORD_SLICE_DLL_RESET)
+	li	v1, 1
+	sw	v1, 0(v0)
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_WORD_SLICE_DLL_RESET)
+	sw	v1, 0(v0)
+
+	li	a0, (SLEEP_1_MILLI_SEC)
+	bal	upg_sleep
+	nop
+
+	/* reset VCDL values */
+	li	t0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_BYTE0_VCDL_PHASE_CNTL)
+	sw	zero, 0(t0)
+	lw	zero, 0(t0)
+	sw	zero, 4(t0)
+	lw	zero, 4(t0)
+
+	li	t0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_BYTE0_VCDL_PHASE_CNTL)
+	sw	zero, 0(t0)
+	lw	zero, 0(t0)
+	sw	zero, 4(t0)
+	lw	zero, 4(t0)
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_WORD_SLICE_DLL_RESET)
+	li	v1, 0
+	sw	v1, 0(v0)
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_WORD_SLICE_DLL_RESET)
+	sw	v1, 0(v0)
+
+	li	a0, (SLEEP_1_MILLI_SEC)
+	bal	upg_sleep
+	nop
+
+	/* de-assert reset from DATAPATH_216 and DATAPATH_DDR */
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_RESET)
+	lw	v1, 0(v0)
+
+	/* de-assert reset from DATAPATH_216_RESET */
+	li	a0, ~(BCHP_MEMC_DDR23_APHY_AC_0_RESET_DATAPATH_216_RESET_MASK)
+	and	v1, v1, a0
+	sw	v1, 0(v0)
+
+	/* de-assert reset from RD_DATAPATH_RESET */
+	li	a0, ~(BCHP_MEMC_DDR23_APHY_AC_0_RESET_RD_DATAPATH_RESET_MASK)
+	and	v1, v1, a0
+	sw	v1, 0(v0)
+
+	/* de-assert reset from DATAPATH_DDR_RESET */
+	li	a0, ~(BCHP_MEMC_DDR23_APHY_AC_0_RESET_DATAPATH_DDR_RESET_MASK)
+	and	v1, v1, a0
+	sw	v1, 0(v0)
+
+	li	a0, (SLEEP_1_MILLI_SEC)
+	bal	upg_sleep
+	nop
+
+	/*
+	 * Reload VCDL values:
+	 * WL0_0_BYTE0 <- bits 07:00
+	 * WL0_0_BYTE1 <- bits 15:08
+	 * WL1_0_BYTE0 <- bits 23:16
+	 * WL1_0_BYTE1 <- bits 31:24
+	 */
+
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_BYTE0_VCDL_PHASE_CNTL)
+	li	t0, REG(VCDL_SAVE_REG)
+	lw	t0, 0(t0)
+	bal	reload_vcdl
+	andi	a1, t0, 0x1f
+
+	srl	a1, t0, 8
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_BYTE1_VCDL_PHASE_CNTL)
+	bal	reload_vcdl
+	andi	a1, 0x1f
+
+	srl	a1, t0, 16
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_BYTE0_VCDL_PHASE_CNTL)
+	bal	reload_vcdl
+	andi	a1, 0x1f
+
+	srl	a1, t0, 24
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_BYTE1_VCDL_PHASE_CNTL)
+	bal	reload_vcdl
+	andi	a1, 0x1f
+
+	jr	s6
+	nop
+
+END(reprogram_ddr_pll)
+
+LEAF(set_memc_0_write_dqs_phase_cntl_direct)
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH4_WL0_DQS0_PHASE_CNTRL)
+	sw	a0, 0(v0)
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH5_WL0_DQS1_PHASE_CNTRL)
+	sw	a0, 0(v0)
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH8_WL1_DQS0_PHASE_CNTRL)
+	sw	a0, 0(v0)
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH9_WL1_DQS1_PHASE_CNTRL)
+	sw	a0, 0(v0)
+
+	jr	ra
+	nop
+
+END(set_memc_0_write_dqs_phase_cntl_direct)
+
+LEAF(set_memc_0_write_dq_phase_cntl_direct)
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH3_WL0_DQ_PHASE_CNTRL)
+	sw	a0, 0(v0)
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH7_WL1_DQ_PHASE_CNTRL)
+	sw	a0, 0(v0)
+
+	jr	ra
+	nop
+
+END(set_memc_0_write_dq_phase_cntl_direct)
+
+LEAF(set_memc_0_pll_ch2_clk_phase_cntrl)
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH2_CLOCK_PHASE_CNTRL)
+	sw	a0, 0(v0)
+
+	jr	ra
+	nop
+END(set_memc_0_pll_ch2_clk_phase_cntrl)
+
+LEAF(set_memc_0_deskew_bypass_phase)
+
+	li	t8, REG(BCHP_MEMC_DDR23_APHY_AC_0_DESKEW_DLL_CNTRL)
+	lw	t7, 0(t8)
+
+	li	t6, ~BCHP_MEMC_DDR23_APHY_AC_0_DESKEW_DLL_CNTRL_BYPASS_PHASE_MASK
+	and	t7, t7, t6
+
+	li	t6, BCHP_MEMC_DDR23_APHY_AC_0_DESKEW_DLL_CNTRL_BYPASS_PHASE_SHIFT
+	sll	t5, a0, t6
+	or	t7, t7, t5
+	sw	t7, 0(t8)
+
+	jr	ra
+	nop
+END(set_memc_0_deskew_bypass_phase)
+
+LEAF(set_memc_0_wl0_dq_phase)
+
+	addi	a0, a0, 1
+	and	a1, a1, zero
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH3_WL0_DQ_PHASE_CNTRL)
+2:
+	sw	a1, 0(v0)
+	addi	a1, a1, 1
+	bne	a1, a0, 2b
+	nop
+
+	jr	ra
+	nop
+END(set_memc_0_wl0_dq_phase)
+
+LEAF(set_memc_0_wl1_dq_phase)
+
+	addi	a0, a0, 1
+	and	a1, a1, zero
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH7_WL1_DQ_PHASE_CNTRL)
+2:
+	sw	a1, 0(v0)
+	addi	a1, a1, 1
+	bne	a1, a0, 2b
+	nop
+
+	jr	ra
+	nop
+END(set_memc_0_wl1_dq_phase)
+
+
+LEAF(set_memc_0_dqs0_phase)
+
+	li	a2, -1
+	blt	a0, zero, 1f
+	nop
+
+	li	a2, 1
+1:
+	and	a1, a1, zero
+	add	a0, a0, a2
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH4_WL0_DQS0_PHASE_CNTRL)
+2:
+	sw	a1, 0(v0)
+	add	a1, a1, a2
+	bne	a1, a0, 2b
+	nop
+
+	jr	ra
+	nop
+
+END(set_memc_0_dqs0_phase)
+
+LEAF(set_memc_0_dqs1_phase)
+
+	li	a2, -1
+	blt	a0, zero, 1f
+	nop
+
+	li	a2, 1
+1:
+	and	a1, a1, zero
+	add	a0, a0, a2
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH5_WL0_DQS1_PHASE_CNTRL)
+2:
+	sw	a1, 0(v0)
+	add	a1, a1, a2
+	bne	a1, a0, 2b
+	nop
+
+	jr	ra
+	nop
+
+
+END(set_memc_0_dqs1_phase)
+
+LEAF(set_memc_0_dqs2_phase)
+
+	li	a2, -1
+	blt	a0, zero, 1f
+	nop
+
+	li	a2, 1
+1:
+	and	a1, a1, zero
+	add	a0, a0, a2
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH8_WL1_DQS0_PHASE_CNTRL)
+2:
+	sw	a1, 0(v0)
+	add	a1, a1, a2
+	bne	a1, a0, 2b
+	nop
+
+	jr	ra
+	nop
+
+END(set_memc_0_dqs2_phase)
+
+LEAF(set_memc_0_dqs3_phase)
+
+	li	a2, -1
+	blt	a0, zero, 1f
+	nop
+
+	li	a2, 1
+1:
+	and	a1, a1, zero
+	add	a0, a0, a2
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH9_WL1_DQS1_PHASE_CNTRL)
+2:
+	sw	a1, 0(v0)
+	add	a1, a1, a2
+	bne	a1, a0, 2b
+	nop
+
+	jr	ra
+	nop
+
+END(set_memc_0_dqs3_phase)
+
+LEAF(memc_settings_valid)
+
+	li	t2, 0xdeadbeef
+	li	t1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA7)
+	lw	t0, 0(t1)
+	li	v0, 0
+	beq	t0, t2, 1f
+	nop
+	li	v0, -1
+
+1:	jr	ra
+	nop
+
+END(memc_settings_valid)
+
+#endif /* CONFIG_BRCM_HAS_ANALOG_DDR_PHY */
+
+#ifdef CONFIG_BRCM_HAS_DIGITAL_DDR_PHY
+
+LEAF(memc_settings_valid)
+
+1:	jr	ra
+	li	v0, 0
+
+END(memc_settings_valid)
+
+LEAF(wake_up_memc_0)
+
+	move	s7, ra
+
+#if !defined(CONFIG_BRCM_PWR_HANDSHAKE)
+	li	t0, REG(BCHP_MEMC_DDR_0_SSPD_CMD)
+	li	t1, 0
+	sw	t1, 0(t0)
+#endif
+
+#ifdef BCHP_DDR23_PHY_CONTROL_REGS_0_PLL_STATUS
+	li	t0, REG(BCHP_DDR23_PHY_CONTROL_REGS_0_PLL_STATUS)
+#elif defined(BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS)
+	li	t0, REG(BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS)
+#else
+#error No MEMC phy control register defined
+#endif
+
+1:	lw	t1, 0(t0)
+	andi	t1, 1
+	beqz	t1, 1b
+	nop
+
+# 1 ms delay - needed on 7552/7358 for stable recovery
+	li	a0, (27000)
+	bal	delay
+	nop
+
+	jr	s7
+	nop
+
+END(wake_up_memc_0)
+
+#endif /* CONFIG_BRCM_HAS_DIGITAL_DDR_PHY */
+
+	.globl passiveIRQ_end
+passiveIRQ_end:
+	nop
diff --git a/arch/mips/brcmstb/time.c b/arch/mips/brcmstb/time.c
new file mode 100644
index 0000000..c38f56a
--- /dev/null
+++ b/arch/mips/brcmstb/time.c
@@ -0,0 +1,185 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/clocksource.h>
+#include <linux/printk.h>
+#include <linux/spinlock.h>
+
+#include <asm/time.h>
+#include <linux/brcmstb/brcmstb.h>
+
+/* MIPS clock measured at boot time.  Value is not changed by PM. */
+unsigned long brcm_cpu_khz;
+
+/* Sampling period for MIPS calibration.  50 = 1/50 of a second. */
+#define SAMPLE_PERIOD		50
+
+/***********************************************************************
+ * UPG clocksource
+ ***********************************************************************/
+
+static cycle_t upg_cs_read(struct clocksource *cs)
+{
+	return BDEV_RD_F(TIMER_TIMER3_STAT, COUNTER_VAL);
+}
+
+static struct clocksource clocksource_upg = {
+	.name		= "upg",
+	.read		= upg_cs_read,
+	.mask		= CLOCKSOURCE_MASK(30),
+	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static inline void __init init_upg_clocksource(void)
+{
+	BDEV_WR_RB(BCHP_TIMER_TIMER3_CTRL, 0);
+	BDEV_WR_F_RB(TIMER_TIMER_IS, TMR3TO, 1);
+	BDEV_WR_RB(BCHP_TIMER_TIMER3_CTRL, 0xbfffffff);
+
+	clocksource_upg.rating = 250;
+	clocksource_register_hz(&clocksource_upg, UPGTMR_FREQ);
+}
+
+#ifdef CONFIG_BRCM_HAS_WKTMR
+
+/***********************************************************************
+ * WKTMR clocksource
+ ***********************************************************************/
+
+static DEFINE_SPINLOCK(wktmr_lock);
+
+static cycle_t wktmr_cs_read(struct clocksource *cs)
+{
+	static struct wktmr_time offs = { (uint32_t)-1, (uint32_t)-1 };
+	struct wktmr_time t;
+	unsigned long flags;
+
+	spin_lock_irqsave(&wktmr_lock, flags);
+	wktmr_read(&t);
+	if (offs.pre == (uint32_t)-1 && offs.sec == offs.pre)
+		offs = t;
+	spin_unlock_irqrestore(&wktmr_lock, flags);
+
+	t.sec -= offs.sec;
+	t.pre -= offs.pre;
+	if ((int32_t)t.pre < 0) {
+		t.pre += WKTMR_FREQ;
+		--t.sec;
+	}
+
+	return (t.sec * (cycle_t)WKTMR_FREQ) + t.pre;
+}
+
+static struct clocksource clocksource_wktmr = {
+	.name		= "wktmr",
+	.read		= wktmr_cs_read,
+	.mask		= CLOCKSOURCE_MASK(64),
+	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static inline void __init init_wktmr_clocksource(void)
+{
+	clocksource_wktmr.rating = 250;
+	clocksource_register_hz(&clocksource_wktmr, WKTMR_FREQ);
+}
+
+/*
+ * MIPS frequency calibration (WKTMR)
+ */
+
+static __init unsigned long brcm_mips_freq(void)
+{
+	struct wktmr_time start;
+
+	wktmr_read(&start);
+	write_c0_count(0);
+
+	while (wktmr_elapsed(&start) < (WKTMR_FREQ / SAMPLE_PERIOD))
+		;
+
+	return read_c0_count() * SAMPLE_PERIOD;
+}
+
+void read_persistent_clock(struct timespec *ts)
+{
+	struct wktmr_time now;
+
+	wktmr_read(&now);
+
+	ts->tv_sec = now.sec;
+	ts->tv_nsec = now.pre * (1000000000/WKTMR_FREQ);
+}
+
+
+#else /* CONFIG_BRCM_HAS_WKTMR */
+
+/*
+ * MIPS frequency calibration (UPG TIMER3)
+ */
+
+static __init unsigned long brcm_mips_freq(void)
+{
+	unsigned long ret;
+
+	/* reset countdown timer */
+	BDEV_WR_RB(BCHP_TIMER_TIMER3_CTRL, 0);
+	BDEV_WR_F_RB(TIMER_TIMER_IS, TMR3TO, 1);
+
+	/* set up for countdown */
+	BDEV_WR(BCHP_TIMER_TIMER0_CTRL, 0xc0000000 |
+		(UPGTMR_FREQ / SAMPLE_PERIOD));
+	write_c0_count(0);
+
+	while ((BDEV_RD(BCHP_TIMER_TIMER_IS) & 1) == 0)
+		;
+
+	ret = read_c0_count();
+	BDEV_WR(BCHP_TIMER_TIMER0_CTRL, 0);
+
+	return ret * SAMPLE_PERIOD;
+}
+
+#endif /* CONFIG_BRCM_HAS_WKTMR */
+
+/***********************************************************************
+ * Timer setup
+ ***********************************************************************/
+
+void __init plat_time_init(void)
+{
+	unsigned int khz;
+
+	pr_info("Measuring MIPS counter frequency...\n");
+	mips_hpt_frequency = brcm_mips_freq();
+	khz = mips_hpt_frequency / 1000;
+#ifdef CONFIG_CPU_BMIPS5000
+	brcm_cpu_khz = mips_hpt_frequency * 8 / 1000;
+#else
+	brcm_cpu_khz = mips_hpt_frequency * 2 / 1000;
+#endif
+
+	pr_info("Detected MIPS clock frequency: %lu MHz (%u.%03u MHz counter)\n",
+		brcm_cpu_khz / 1000, khz / 1000, khz % 1000);
+
+#ifdef CONFIG_CSRC_WKTMR
+	init_wktmr_clocksource();
+#endif
+#ifdef CONFIG_CSRC_UPG
+	init_upg_clocksource();
+#endif
+}
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index f9e275a..2f4f6d5 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -82,10 +82,6 @@ config CAVIUM_OCTEON_LOCK_L2_MEMCPY
 	help
 	  Lock the kernel's implementation of memcpy() into L2.
 
-config ARCH_SPARSEMEM_ENABLE
-	def_bool y
-	select SPARSEMEM_STATIC
-
 config IOMMU_HELPER
 	bool
 
diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
index d38246e..33b7214 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-l2c.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
@@ -30,6 +30,8 @@
  * measurement, and debugging facilities.
  */
 
+#include <linux/compiler.h>
+#include <linux/irqflags.h>
 #include <asm/octeon/cvmx.h>
 #include <asm/octeon/cvmx-l2c.h>
 #include <asm/octeon/cvmx-spinlock.h>
@@ -284,22 +286,22 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter)
  */
 static void fault_in(uint64_t addr, int len)
 {
-	volatile char *ptr;
-	volatile char dummy;
+	char *ptr;
+
 	/*
 	 * Adjust addr and length so we get all cache lines even for
 	 * small ranges spanning two cache lines.
 	 */
 	len += addr & CVMX_CACHE_LINE_MASK;
 	addr &= ~CVMX_CACHE_LINE_MASK;
-	ptr = (volatile char *)cvmx_phys_to_ptr(addr);
+	ptr = cvmx_phys_to_ptr(addr);
 	/*
 	 * Invalidate L1 cache to make sure all loads result in data
 	 * being in L2.
 	 */
 	CVMX_DCACHE_INVALIDATE;
 	while (len > 0) {
-		dummy += *ptr;
+		ACCESS_ONCE(*ptr);
 		len -= CVMX_CACHE_LINE_SIZE;
 		ptr += CVMX_CACHE_LINE_SIZE;
 	}
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index 97e7ce9..ef9c34a 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -185,7 +185,6 @@ static void __cpuinit octeon_init_secondary(void)
 	octeon_init_cvmcount();
 
 	octeon_irq_setup_secondary();
-	raw_local_irq_enable();
 }
 
 /**
@@ -233,6 +232,7 @@ static void octeon_smp_finish(void)
 
 	/* to generate the first CPU timer interrupt */
 	write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
+	local_irq_enable();
 }
 
 /**
diff --git a/arch/mips/cobalt/Makefile b/arch/mips/cobalt/Makefile
index 61a334a..350f8ac 100644
--- a/arch/mips/cobalt/Makefile
+++ b/arch/mips/cobalt/Makefile
@@ -2,8 +2,7 @@
 # Makefile for the Cobalt micro systems family specific parts of the kernel
 #
 
-obj-y := buttons.o irq.o lcd.o led.o reset.o rtc.o serial.o setup.o time.o
+obj-y := buttons.o irq.o lcd.o led.o mtd.o reset.o rtc.o serial.o setup.o time.o
 
 obj-$(CONFIG_PCI)		+= pci.o
 obj-$(CONFIG_EARLY_PRINTK)	+= console.o
-obj-$(CONFIG_MTD_PHYSMAP)	+= mtd.o
diff --git a/arch/mips/configs/bcm7228a0_defconfig b/arch/mips/configs/bcm7228a0_defconfig
new file mode 100644
index 0000000..9b83972
--- /dev/null
+++ b/arch/mips/configs/bcm7228a0_defconfig
@@ -0,0 +1,115 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7228A0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7231b0_defconfig b/arch/mips/configs/bcm7231b0_defconfig
new file mode 100644
index 0000000..b2759b5
--- /dev/null
+++ b/arch/mips/configs/bcm7231b0_defconfig
@@ -0,0 +1,117 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7231B0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7344b0_defconfig b/arch/mips/configs/bcm7344b0_defconfig
new file mode 100644
index 0000000..756c0fe
--- /dev/null
+++ b/arch/mips/configs/bcm7344b0_defconfig
@@ -0,0 +1,115 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7344B0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7346b0_defconfig b/arch/mips/configs/bcm7346b0_defconfig
new file mode 100644
index 0000000..e11da1c
--- /dev/null
+++ b/arch/mips/configs/bcm7346b0_defconfig
@@ -0,0 +1,117 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7346B0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7358a0_defconfig b/arch/mips/configs/bcm7358a0_defconfig
new file mode 100644
index 0000000..8f37492
--- /dev/null
+++ b/arch/mips/configs/bcm7358a0_defconfig
@@ -0,0 +1,112 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7358A0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7360a0_defconfig b/arch/mips/configs/bcm7360a0_defconfig
new file mode 100644
index 0000000..255edea
--- /dev/null
+++ b/arch/mips/configs/bcm7360a0_defconfig
@@ -0,0 +1,113 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7360A0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7362a0_defconfig b/arch/mips/configs/bcm7362a0_defconfig
new file mode 100644
index 0000000..2753452
--- /dev/null
+++ b/arch/mips/configs/bcm7362a0_defconfig
@@ -0,0 +1,115 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7362A0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7425b0_defconfig b/arch/mips/configs/bcm7425b0_defconfig
new file mode 100644
index 0000000..fe815e3
--- /dev/null
+++ b/arch/mips/configs/bcm7425b0_defconfig
@@ -0,0 +1,121 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7425B0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_HIGHMEM=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_PCI=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7429b0_defconfig b/arch/mips/configs/bcm7429b0_defconfig
new file mode 100644
index 0000000..b2a8465
--- /dev/null
+++ b/arch/mips/configs/bcm7429b0_defconfig
@@ -0,0 +1,116 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7429B0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7435b0_defconfig b/arch/mips/configs/bcm7435b0_defconfig
new file mode 100644
index 0000000..df5c75c
--- /dev/null
+++ b/arch/mips/configs/bcm7435b0_defconfig
@@ -0,0 +1,119 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7435B0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_HIGHMEM=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=4
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_PCI=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7543a0_defconfig b/arch/mips/configs/bcm7543a0_defconfig
new file mode 100644
index 0000000..4291719
--- /dev/null
+++ b/arch/mips/configs/bcm7543a0_defconfig
@@ -0,0 +1,115 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7543A0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7552b0_defconfig b/arch/mips/configs/bcm7552b0_defconfig
new file mode 100644
index 0000000..1ed9703
--- /dev/null
+++ b/arch/mips/configs/bcm7552b0_defconfig
@@ -0,0 +1,115 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7552B0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7563a0_defconfig b/arch/mips/configs/bcm7563a0_defconfig
new file mode 100644
index 0000000..df562f7
--- /dev/null
+++ b/arch/mips/configs/bcm7563a0_defconfig
@@ -0,0 +1,118 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7563A0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7584a0_defconfig b/arch/mips/configs/bcm7584a0_defconfig
new file mode 100644
index 0000000..b75d11f
--- /dev/null
+++ b/arch/mips/configs/bcm7584a0_defconfig
@@ -0,0 +1,117 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7584A0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/dm520_defconfig b/arch/mips/configs/dm520_defconfig
new file mode 100644
index 0000000..c6e8b4b
--- /dev/null
+++ b/arch/mips/configs/dm520_defconfig
@@ -0,0 +1,2895 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/mips 3.4-4.0 Kernel Configuration
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MIPS_ALCHEMY is not set
+# CONFIG_AR7 is not set
+# CONFIG_ATH79 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
+CONFIG_BRCMSTB=y
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_MACH_JZ4740 is not set
+# CONFIG_LANTIQ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MACH_LOONGSON is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_POWERTV is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+# CONFIG_NLM_XLR_BOARD is not set
+# CONFIG_NLM_XLP_BOARD is not set
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+
+#
+# Broadcom STB options
+#
+CONFIG_BRCM_LEGACY=y
+# CONFIG_BCM7228A0 is not set
+# CONFIG_BCM7231B0 is not set
+# CONFIG_BCM7344B0 is not set
+# CONFIG_BCM7346B0 is not set
+# CONFIG_BCM7358A0 is not set
+# CONFIG_BCM7360A0 is not set
+CONFIG_BCM7362A0=y
+# CONFIG_BCM7425B0 is not set
+# CONFIG_BCM7429B0 is not set
+# CONFIG_BCM7435B0 is not set
+# CONFIG_BCM7543A0 is not set
+# CONFIG_BCM7552B0 is not set
+# CONFIG_BCM7563A0 is not set
+# CONFIG_BCM7584A0 is not set
+CONFIG_DREAMBOX=y
+CONFIG_DREAMBOX_DM520=y
+
+#
+# Memory map
+#
+CONFIG_BRCM_UPPER_MEMORY=y
+# CONFIG_BRCM_OVERRIDE_RAM_SIZE is not set
+
+#
+# Onchip peripherals
+#
+CONFIG_BRCM_CONSOLE_DEVICE=0
+CONFIG_BRCM_FLASH=y
+# CONFIG_BRCM_FIXED_MTD_PARTITIONS is not set
+CONFIG_MTD_BRCMNAND=y
+CONFIG_SPI_BRCMSTB=y
+CONFIG_BCMGENET=y
+
+#
+# BCMGENET options
+#
+# CONFIG_BCMGENET_RX_DESC_THROTTLE is not set
+CONFIG_BCMGENET_NAPI=y
+# CONFIG_BCMGENET_RX_CSUM is not set
+# CONFIG_BCMGENET_TX_CSUM is not set
+# CONFIG_BCMGENET_DUMP_DATA is not set
+# CONFIG_BCMGENET_DUMP_TRACE is not set
+CONFIG_BRCM_USB=y
+# CONFIG_BRCM_OVERRIDE_USB is not set
+CONFIG_BRCM_PM=y
+CONFIG_CSRC_WKTMR=y
+# CONFIG_CSRC_UPG is not set
+
+#
+# Miscellaneous options
+#
+CONFIG_BRCM_LIBGCC=y
+# CONFIG_BRCM_SCSI_NO_RW10_RETRIES is not set
+CONFIG_BRCM_WLAN_MODULES=y
+# CONFIG_BRCM_DEBUG_OPTIONS is not set
+CONFIG_BRCM_HAS_BMIPS4380=y
+CONFIG_BRCM_HAS_16550=y
+CONFIG_BRCM_HAS_UARTA=y
+CONFIG_BRCM_UARTA_IS_16550=y
+CONFIG_BRCM_GENET_V2=y
+CONFIG_BRCM_GENET_VERSION=2
+CONFIG_BRCM_HAS_GENET=y
+CONFIG_BRCM_HAS_GENET_0=y
+# CONFIG_BRCM_SATA_75MHZ_PLL is not set
+# CONFIG_BRCM_SATA_SINGLE_PORT is not set
+CONFIG_BRCM_HAS_NOR=y
+CONFIG_BRCM_HAS_NAND_MINOR_0=y
+CONFIG_BRCM_HAS_NAND_MAJOR_5=y
+CONFIG_BRCMNAND_MAJOR_VERS=5
+CONFIG_BRCMNAND_MINOR_VERS=0
+CONFIG_BRCM_HAS_NAND=y
+CONFIG_BRCM_HAS_SPI=y
+CONFIG_BRCM_HAS_BSPI_V4=y
+CONFIG_BRCM_BSPI_MAJOR_VERS=4
+CONFIG_BRCM_HAS_WKTMR=y
+CONFIG_BRCM_HAS_SDIO=y
+CONFIG_BRCM_HAS_SDIO_V1=y
+CONFIG_BRCM_CPU_DIV=y
+CONFIG_BRCM_HAS_XKS01=y
+CONFIG_BRCM_HAS_UPPER_MEMORY=y
+CONFIG_BRCM_UPPER_768MB=y
+CONFIG_BRCM_HAS_DIGITAL_DDR_PHY=y
+CONFIG_BRCM_PWR_HANDSHAKE=y
+CONFIG_BRCM_PWR_HANDSHAKE_V1=y
+CONFIG_BRCM_MIPS_DEFAULTS=y
+CONFIG_BCM7362=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_BOOT_RAW=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CEVT_R4K=y
+CONFIG_CFE=y
+# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
+# CONFIG_MIPS_MACHINE is not set
+# CONFIG_NO_IOPORT is not set
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_MIPS_L1_CACHE_SHIFT=6
+
+#
+# CPU selection
+#
+CONFIG_CPU_BMIPS4380=y
+CONFIG_CPU_BMIPS=y
+CONFIG_SYS_HAS_CPU_BMIPS4380=y
+CONFIG_WEAK_ORDERING=y
+CONFIG_CPU_MIPS32=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_XKS01=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_COMPACTION is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_CLEANCACHE=y
+CONFIG_SMP=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_256 is not set
+CONFIG_HZ_1000=y
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=1000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_KEXEC=y
+CONFIG_SECCOMP=y
+CONFIG_CC_STACKPROTECTOR=y
+# CONFIG_USE_OF is not set
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_HAVE_IRQ_WORK=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION="-dm520"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_DEFAULT_HOSTNAME="dm520"
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_FHANDLE=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_IRQ_FORCED_THREADING=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_RCU_FAST_NO_HZ is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+# CONFIG_CGROUP_MEM_RES_CTLR is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_CFS_BANDWIDTH is not set
+# CONFIG_RT_GROUP_SCHED is not set
+# CONFIG_BLK_CGROUP is not set
+# CONFIG_CHECKPOINT_RESTORE is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_NET_NS=y
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EXPERT=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+# CONFIG_JUMP_LABEL is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+
+#
+# GCOV-based kernel profiling
+#
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+CONFIG_LDM_PARTITION=y
+# CONFIG_LDM_DEBUG is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_FREEZER=y
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_MMU=y
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_TRAD_SIGNALS=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_SUSPEND is not set
+# CONFIG_HIBERNATION is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+# CONFIG_UNIX_DIAG is not set
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_ROUTE_CLASSID=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=y
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_ACCT=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_PROCFS=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_TIMEOUT=y
+# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
+CONFIG_NF_CT_PROTO_DCCP=m
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_BROADCAST=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NF_CT_NETLINK_TIMEOUT=m
+CONFIG_NETFILTER_TPROXY=m
+CONFIG_NETFILTER_XTABLES=m
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=m
+CONFIG_NETFILTER_XT_CONNMARK=m
+CONFIG_NETFILTER_XT_SET=m
+
+#
+# Xtables targets
+#
+# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+# CONFIG_NETFILTER_XT_TARGET_CT is not set
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HL=m
+# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
+CONFIG_NETFILTER_XT_TARGET_LED=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+
+#
+# Xtables matches
+#
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ECN=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_HL=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_MAX=256
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+# CONFIG_NF_NAT_SNMP_BASIC is not set
+CONFIG_NF_NAT_PROTO_DCCP=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_PROTO_UDPLITE=m
+CONFIG_NF_NAT_PROTO_SCTP=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV6=m
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_QUEUE=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+# CONFIG_BRIDGE_NF_EBTABLES is not set
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_L2TP=y
+# CONFIG_L2TP_V3 is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=m
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+CONFIG_NET_SCH_SFB=m
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+# CONFIG_NET_SCH_MQPRIO is not set
+# CONFIG_NET_SCH_CHOKE is not set
+# CONFIG_NET_SCH_QFQ is not set
+CONFIG_NET_SCH_PLUG=m
+
+#
+# Classification
+#
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_CLS_CGROUP is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+CONFIG_DNS_RESOLVER=y
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_OPENVSWITCH is not set
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+# CONFIG_NETPRIO_CGROUP is not set
+CONFIG_BQL=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=y
+# CONFIG_BT_HCIUART is not set
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+CONFIG_BT_ATH3K=m
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_PRIV=y
+CONFIG_CFG80211=y
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+# CONFIG_CFG80211_DEFAULT_PS is not set
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=y
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_RC_PID=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL_HT=y
+# CONFIG_MAC80211_RC_DEFAULT_PID is not set
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+CONFIG_CEPH_LIB=m
+# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
+# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
+# CONFIG_NFC is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_GENERIC_CPU_DEVICES is not set
+CONFIG_DMA_SHARED_BUFFER=y
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+# CONFIG_MTD_SWAP is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+CONFIG_MTD_MTDRAM=m
+CONFIG_MTDRAM_TOTAL_SIZE=4096
+CONFIG_MTDRAM_ERASE_SIZE=128
+CONFIG_MTD_BLOCK2MTD=y
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_DOCG3 is not set
+CONFIG_MTD_NAND_ECC=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_BCH is not set
+# CONFIG_MTD_SM_COMMON is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_DOCG4 is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+CONFIG_MTD_UBI_GLUEBI=y
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_UB=m
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+CONFIG_ATA_OVER_ETH=m
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_BLK_DEV_RBD is not set
+
+#
+# Misc devices
+#
+# CONFIG_SENSORS_LIS3LV02D is not set
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_BMP085 is not set
+# CONFIG_USB_SWITCH_FSA9480 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+CONFIG_EEPROM_93CX6=m
+# CONFIG_EEPROM_93XX46 is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+
+#
+# Altera FPGA firmware download module
+#
+# CONFIG_ALTERA_STAPL is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+CONFIG_MD=y
+# CONFIG_BLK_DEV_MD is not set
+CONFIG_BLK_DEV_DM_BUILTIN=y
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_THIN_PROVISIONING is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_RAID is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+# CONFIG_DM_UEVENT is not set
+# CONFIG_DM_FLAKEY is not set
+# CONFIG_DM_VERITY is not set
+# CONFIG_TARGET_CORE is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+# CONFIG_DUMMY is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_MII=y
+# CONFIG_NET_TEAM is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+CONFIG_TUN=y
+# CONFIG_VETH is not set
+
+#
+# CAIF transport drivers
+#
+CONFIG_ETHERNET=y
+CONFIG_NET_VENDOR_BROADCOM=y
+# CONFIG_B44 is not set
+# CONFIG_NET_CALXEDA_XGMAC is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_DM9000 is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+CONFIG_NET_VENDOR_MICROCHIP=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_ETHOC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_PHYLIB is not set
+# CONFIG_MICREL_KS8995MA is not set
+CONFIG_PPP=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOE=m
+# CONFIG_PPPOL2TP is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_EEM=m
+CONFIG_USB_NET_CDC_NCM=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_NET_CX82310_ETH=m
+CONFIG_USB_NET_KALMIA=m
+CONFIG_USB_NET_QMI_WWAN=m
+CONFIG_USB_NET_INT51X1=m
+CONFIG_USB_IPHETH=m
+CONFIG_USB_SIERRA_NET=m
+CONFIG_USB_VL600=m
+CONFIG_WLAN=y
+# CONFIG_LIBERTAS_THINFIRM is not set
+CONFIG_AT76C50X_USB=m
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+CONFIG_RTL8187=m
+CONFIG_RTL8187_LEDS=y
+# CONFIG_MAC80211_HWSIM is not set
+CONFIG_ATH_COMMON=m
+# CONFIG_ATH_DEBUG is not set
+CONFIG_ATH9K_HW=m
+CONFIG_ATH9K_COMMON=m
+# CONFIG_ATH9K_BTCOEX_SUPPORT is not set
+CONFIG_ATH9K=m
+# CONFIG_ATH9K_AHB is not set
+# CONFIG_ATH9K_DFS_CERTIFIED is not set
+# CONFIG_ATH9K_LEGACY_RATE_CONTROL is not set
+# CONFIG_ATH9K_HTC is not set
+CONFIG_CARL9170=m
+CONFIG_CARL9170_LEDS=y
+CONFIG_CARL9170_WPC=y
+# CONFIG_ATH6KL is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_BRCMFMAC is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_LIBERTAS is not set
+CONFIG_P54_COMMON=m
+CONFIG_P54_USB=m
+# CONFIG_P54_SPI is not set
+CONFIG_P54_LEDS=y
+CONFIG_RT2X00=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT35XX=y
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RT2800_LIB=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
+CONFIG_RTL8192CU=m
+CONFIG_RTLWIFI=m
+# CONFIG_RTLWIFI_DEBUG is not set
+CONFIG_RTL8192C_COMMON=m
+# CONFIG_WL1251 is not set
+# CONFIG_WL12XX_MENU is not set
+CONFIG_ZD1211RW=m
+# CONFIG_ZD1211RW_DEBUG is not set
+# CONFIG_MWIFIEX is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=m
+CONFIG_INPUT_POLLDEV=m
+CONFIG_INPUT_SPARSEKMAP=m
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_BMA150 is not set
+# CONFIG_INPUT_MMA8450 is not set
+# CONFIG_INPUT_MPU3050 is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_KXTJ9 is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=m
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_CMA3000 is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+# CONFIG_DEVKMEM is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX3107 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_TTY_PRINTK is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_RAMOOPS=m
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_MUX is not set
+# CONFIG_I2C_HELPER_AUTO is not set
+# CONFIG_I2C_SMBUS is not set
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_BRCMSTB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_HSI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+
+#
+# Enable Device Drivers -> PPS to see the PTP clock options.
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=m
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2781 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_SBS is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_LP8727 is not set
+# CONFIG_CHARGER_SMB347 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7314 is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_MCP3021 is not set
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_PMBUS is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SCH56XX_COMMON is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_SCH5636 is not set
+CONFIG_SENSORS_ADC128D818=y
+# CONFIG_SENSORS_ADS1015 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+CONFIG_SENSORS_INA2XX=y
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+
+#
+# Broadcom specific AMBA
+#
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS65217 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_TWL6040_CORE is not set
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_DA9052_SPI is not set
+# CONFIG_MFD_DA9052_I2C is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_S5M_CORE is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13XXX is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_TPS65090 is not set
+# CONFIG_MFD_RC5T583 is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+# CONFIG_MEDIA_CONTROLLER is not set
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_DVB_CORE=y
+CONFIG_DVB_NET=y
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+CONFIG_RC_CORE=y
+CONFIG_LIRC=y
+CONFIG_RC_MAP=m
+CONFIG_IR_NEC_DECODER=m
+CONFIG_IR_RC5_DECODER=m
+CONFIG_IR_RC6_DECODER=m
+CONFIG_IR_JVC_DECODER=m
+CONFIG_IR_SONY_DECODER=m
+CONFIG_IR_RC5_SZ_DECODER=m
+CONFIG_IR_SANYO_DECODER=m
+CONFIG_IR_MCE_KBD_DECODER=m
+CONFIG_IR_LIRC_CODEC=m
+CONFIG_RC_ATI_REMOTE=m
+CONFIG_IR_IMON=m
+CONFIG_IR_MCEUSB=m
+CONFIG_IR_REDRAT3=m
+CONFIG_IR_STREAMZAP=m
+CONFIG_RC_LOOPBACK=m
+# CONFIG_IR_GPIO_CIR is not set
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=m
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_TUNER_XC4000=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_MEDIA_TUNER_MXL5007T=m
+CONFIG_MEDIA_TUNER_MC44S803=m
+CONFIG_MEDIA_TUNER_MAX2165=m
+CONFIG_MEDIA_TUNER_TDA18218=m
+CONFIG_MEDIA_TUNER_TUA9001=m
+CONFIG_MEDIA_TUNER_TDA18212=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEOBUF_VMALLOC=m
+CONFIG_VIDEOBUF_DVB=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEOBUF2_CORE=m
+CONFIG_VIDEOBUF2_MEMOPS=m
+CONFIG_VIDEOBUF2_VMALLOC=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_VIDEO_IR_I2C=m
+
+#
+# Audio decoders, processors and mixers
+#
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_WM8775=m
+
+#
+# RDS decoders
+#
+
+#
+# Video decoders
+#
+CONFIG_VIDEO_SAA711X=m
+CONFIG_VIDEO_TVP5150=m
+
+#
+# Video and audio decoders
+#
+CONFIG_VIDEO_CX25840=m
+
+#
+# MPEG video encoders
+#
+CONFIG_VIDEO_CX2341X=m
+
+#
+# Video encoders
+#
+
+#
+# Camera sensor devices
+#
+CONFIG_VIDEO_MT9V011=m
+
+#
+# Flash devices
+#
+
+#
+# Video improvement chips
+#
+
+#
+# Miscelaneous helper chips
+#
+# CONFIG_VIDEO_VIVI is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+# CONFIG_USB_M5602 is not set
+# CONFIG_USB_STV06XX is not set
+# CONFIG_USB_GL860 is not set
+# CONFIG_USB_GSPCA_BENQ is not set
+# CONFIG_USB_GSPCA_CONEX is not set
+# CONFIG_USB_GSPCA_CPIA1 is not set
+# CONFIG_USB_GSPCA_ETOMS is not set
+# CONFIG_USB_GSPCA_FINEPIX is not set
+# CONFIG_USB_GSPCA_JEILINJ is not set
+# CONFIG_USB_GSPCA_JL2005BCD is not set
+# CONFIG_USB_GSPCA_KINECT is not set
+# CONFIG_USB_GSPCA_KONICA is not set
+# CONFIG_USB_GSPCA_MARS is not set
+# CONFIG_USB_GSPCA_MR97310A is not set
+# CONFIG_USB_GSPCA_NW80X is not set
+# CONFIG_USB_GSPCA_OV519 is not set
+# CONFIG_USB_GSPCA_OV534 is not set
+# CONFIG_USB_GSPCA_OV534_9 is not set
+# CONFIG_USB_GSPCA_PAC207 is not set
+# CONFIG_USB_GSPCA_PAC7302 is not set
+# CONFIG_USB_GSPCA_PAC7311 is not set
+# CONFIG_USB_GSPCA_SE401 is not set
+# CONFIG_USB_GSPCA_SN9C2028 is not set
+# CONFIG_USB_GSPCA_SN9C20X is not set
+# CONFIG_USB_GSPCA_SONIXB is not set
+# CONFIG_USB_GSPCA_SONIXJ is not set
+# CONFIG_USB_GSPCA_SPCA500 is not set
+# CONFIG_USB_GSPCA_SPCA501 is not set
+# CONFIG_USB_GSPCA_SPCA505 is not set
+# CONFIG_USB_GSPCA_SPCA506 is not set
+# CONFIG_USB_GSPCA_SPCA508 is not set
+# CONFIG_USB_GSPCA_SPCA561 is not set
+# CONFIG_USB_GSPCA_SPCA1528 is not set
+# CONFIG_USB_GSPCA_SQ905 is not set
+# CONFIG_USB_GSPCA_SQ905C is not set
+# CONFIG_USB_GSPCA_SQ930X is not set
+# CONFIG_USB_GSPCA_STK014 is not set
+# CONFIG_USB_GSPCA_STV0680 is not set
+# CONFIG_USB_GSPCA_SUNPLUS is not set
+# CONFIG_USB_GSPCA_T613 is not set
+# CONFIG_USB_GSPCA_TOPRO is not set
+# CONFIG_USB_GSPCA_TV8532 is not set
+# CONFIG_USB_GSPCA_VC032X is not set
+# CONFIG_USB_GSPCA_VICAM is not set
+# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
+# CONFIG_USB_GSPCA_ZC3XX is not set
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_PVRUSB2_DVB=y
+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
+CONFIG_VIDEO_HDPVR=m
+CONFIG_VIDEO_EM28XX=m
+CONFIG_VIDEO_EM28XX_ALSA=m
+CONFIG_VIDEO_EM28XX_DVB=m
+# CONFIG_VIDEO_EM28XX_RC is not set
+CONFIG_VIDEO_TLG2300=m
+CONFIG_VIDEO_CX231XX=m
+CONFIG_VIDEO_CX231XX_RC=y
+CONFIG_VIDEO_CX231XX_ALSA=m
+CONFIG_VIDEO_CX231XX_DVB=m
+CONFIG_VIDEO_TM6000=m
+CONFIG_VIDEO_TM6000_ALSA=m
+CONFIG_VIDEO_TM6000_DVB=m
+CONFIG_VIDEO_USBVISION=m
+CONFIG_USB_ET61X251=m
+CONFIG_USB_SN9C102=m
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+CONFIG_USB_PWC_INPUT_EVDEV=y
+# CONFIG_VIDEO_CPIA2 is not set
+CONFIG_USB_ZR364XX=m
+CONFIG_USB_STKWEBCAM=m
+CONFIG_USB_S2255=m
+# CONFIG_V4L_PLATFORM_DRIVERS is not set
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+# CONFIG_VIDEO_MEM2MEM_TESTDEV is not set
+# CONFIG_RADIO_ADAPTERS is not set
+CONFIG_DVB_MAX_ADAPTERS=8
+CONFIG_DVB_DYNAMIC_MINORS=y
+CONFIG_DVB_CAPTURE_DRIVERS=y
+CONFIG_TTPCI_EEPROM=m
+
+#
+# Supported USB Adapters
+#
+CONFIG_DVB_USB=m
+# CONFIG_DVB_USB_DEBUG is not set
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_DIBUSB_MB=m
+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+CONFIG_DVB_USB_PCTV452E=m
+CONFIG_DVB_USB_DW2102=m
+CONFIG_DVB_USB_CINERGY_T2=m
+CONFIG_DVB_USB_ANYSEE=m
+CONFIG_DVB_USB_DTV5100=m
+CONFIG_DVB_USB_AF9015=m
+CONFIG_DVB_USB_A867=m
+CONFIG_DVB_USB_AF9035=m
+CONFIG_DVB_USB_CE6230=m
+CONFIG_DVB_USB_FRIIO=m
+CONFIG_DVB_USB_EC168=m
+CONFIG_DVB_USB_AZ6007=m
+CONFIG_DVB_USB_AZ6027=m
+CONFIG_DVB_USB_LME2510=m
+CONFIG_DVB_USB_TECHNISAT_USB2=m
+CONFIG_DVB_USB_IT913X=m
+CONFIG_DVB_USB_MXL111SF=m
+CONFIG_DVB_USB_RTL28XXU=m
+CONFIG_SMS_SIANO_MDTV=m
+
+#
+# Siano module components
+#
+CONFIG_SMS_USB_DRV=m
+
+#
+# Supported FlexCopII (B2C2) Adapters
+#
+CONFIG_DVB_B2C2_FLEXCOP=m
+CONFIG_DVB_B2C2_FLEXCOP_USB=m
+# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set
+
+#
+# Supported DVB Frontends
+#
+CONFIG_DVB_FE_CUSTOMISE=y
+
+#
+# Customise DVB Frontends
+#
+
+#
+# Multistandard (satellite) frontends
+#
+CONFIG_DVB_STB0899=m
+CONFIG_DVB_STB6100=m
+CONFIG_DVB_STV090x=m
+CONFIG_DVB_STV6110x=m
+
+#
+# Multistandard (cable + terrestrial) frontends
+#
+CONFIG_DVB_DRXK=m
+CONFIG_DVB_TDA18271C2DD=m
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_ZL10036=m
+CONFIG_DVB_ZL10039=m
+CONFIG_DVB_S5H1420=m
+CONFIG_DVB_STV0288=m
+CONFIG_DVB_STB6000=m
+CONFIG_DVB_STV0299=y
+CONFIG_DVB_STV6110=m
+CONFIG_DVB_STV0900=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_TDA8261=m
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_TUNER_CX24113=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TUA6100=m
+CONFIG_DVB_CX24116=m
+CONFIG_DVB_SI21XX=m
+CONFIG_DVB_DS3000=m
+CONFIG_DVB_MB86A16=m
+CONFIG_DVB_TDA10071=m
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_SP8870=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+CONFIG_DVB_S5H1432=m
+CONFIG_DVB_DRXD=m
+CONFIG_DVB_L64781=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_DIB9000=m
+CONFIG_DVB_TDA10048=m
+CONFIG_DVB_AF9013=m
+CONFIG_DVB_AF9033=m
+CONFIG_DVB_EC100=m
+CONFIG_DVB_HD29L2=m
+CONFIG_DVB_STV0367=m
+CONFIG_DVB_CXD2820R=m
+CONFIG_DVB_RTL2830=m
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_STV0297=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_NXT200X=m
+CONFIG_DVB_OR51211=m
+CONFIG_DVB_OR51132=m
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_LGDT3305=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_S5H1411=m
+
+#
+# ISDB-T (terrestrial) frontends
+#
+CONFIG_DVB_S921=m
+CONFIG_DVB_DIB8000=m
+CONFIG_DVB_MB86A20S=m
+
+#
+# Digital terrestrial only tuners/PLL
+#
+CONFIG_DVB_PLL=m
+CONFIG_DVB_TUNER_DIB0070=m
+CONFIG_DVB_TUNER_DIB0090=m
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_LNBP21=m
+CONFIG_DVB_LNBP22=m
+CONFIG_DVB_ISL6405=m
+CONFIG_DVB_ISL6421=m
+CONFIG_DVB_ISL6423=m
+CONFIG_DVB_A8293=m
+CONFIG_DVB_LGS8GL5=m
+CONFIG_DVB_LGS8GXX=m
+CONFIG_DVB_ATBM8830=m
+CONFIG_DVB_TDA665x=m
+CONFIG_DVB_IX2505V=m
+CONFIG_DVB_IT913X_FE=m
+CONFIG_DVB_M88RS2000=m
+
+#
+# Tools to develop new frontends
+#
+CONFIG_DVB_DUMMY_FE=m
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_WMT_GE_ROPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_SMSCUFX is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_EXYNOS_VIDEO is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=m
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_HRTIMER is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_SPI=y
+# CONFIG_SND_MIPS is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+# CONFIG_SND_USB_UA101 is not set
+CONFIG_SND_USB_CAIAQ=m
+# CONFIG_SND_USB_CAIAQ_INPUT is not set
+# CONFIG_SND_USB_6FIRE is not set
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# USB HID Boot Protocol drivers
+#
+CONFIG_USB_KBD=m
+CONFIG_USB_MOUSE=m
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_ACRUX is not set
+CONFIG_HID_APPLE=m
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_PRODIKEYS is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EMS_FF is not set
+# CONFIG_HID_ELECOM is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_HOLTEK is not set
+# CONFIG_HID_KEYTOUCH is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LCPOWER is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_PRIMAX is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_SAITEK is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SPEEDLINK is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TIVO is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_WACOM is not set
+CONFIG_HID_WIIMOTE=m
+CONFIG_HID_WIIMOTE_EXT=y
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB_ARCH_HAS_XHCI is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_REALTEK=m
+CONFIG_REALTEK_AUTOPM=y
+CONFIG_USB_STORAGE_DATAFAB=m
+CONFIG_USB_STORAGE_FREECOM=m
+CONFIG_USB_STORAGE_ISD200=m
+CONFIG_USB_STORAGE_USBAT=m
+CONFIG_USB_STORAGE_SDDR09=m
+CONFIG_USB_STORAGE_SDDR55=m
+CONFIG_USB_STORAGE_JUMPSHOT=m
+CONFIG_USB_STORAGE_ALAUDA=m
+CONFIG_USB_STORAGE_ONETOUCH=m
+CONFIG_USB_STORAGE_KARMA=m
+CONFIG_USB_STORAGE_CYPRESS_ATACB=m
+CONFIG_USB_STORAGE_ENE_UB6250=m
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_FUNSOFT=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_F81232=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+# CONFIG_USB_SERIAL_METRO is not set
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MOTOROLA=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_QCAUX=m
+CONFIG_USB_SERIAL_QUALCOMM=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_HP4X=m
+CONFIG_USB_SERIAL_SAFE=m
+# CONFIG_USB_SERIAL_SAFE_PADDED is not set
+CONFIG_USB_SERIAL_SIEMENS_MPI=m
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_SYMBOL=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_WWAN=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_OPTICON=m
+CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
+CONFIG_USB_SERIAL_ZIO=m
+CONFIG_USB_SERIAL_SSU100=m
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP5523 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_PCA9633 is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_TCA6507 is not set
+# CONFIG_LEDS_OT200 is not set
+CONFIG_LEDS_TRIGGERS=y
+
+#
+# LED Triggers
+#
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=m
+CONFIG_UIO_PDRV=m
+CONFIG_UIO_PDRV_GENIRQ=m
+
+#
+# Virtio drivers
+#
+# CONFIG_VIRTIO_BALLOON is not set
+# CONFIG_VIRTIO_MMIO is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+CONFIG_STAGING=y
+CONFIG_USBIP_CORE=m
+CONFIG_USBIP_VHCI_HCD=m
+CONFIG_USBIP_HOST=m
+# CONFIG_USBIP_DEBUG is not set
+# CONFIG_W35UND is not set
+CONFIG_PRISM2_USB=m
+# CONFIG_ECHO is not set
+# CONFIG_ASUS_OLED is not set
+CONFIG_RTLLIB=m
+CONFIG_RTLLIB_CRYPTO_CCMP=m
+CONFIG_RTLLIB_CRYPTO_TKIP=m
+CONFIG_RTLLIB_CRYPTO_WEP=m
+CONFIG_R8712U=m
+CONFIG_RTS5139=m
+# CONFIG_RTS5139_DEBUG is not set
+CONFIG_TRANZPORT=m
+CONFIG_LINE6_USB=m
+# CONFIG_LINE6_USB_DEBUG is not set
+# CONFIG_LINE6_USB_DUMP_CTRL is not set
+# CONFIG_LINE6_USB_DUMP_MIDI is not set
+# CONFIG_LINE6_USB_DUMP_PCM is not set
+# CONFIG_LINE6_USB_RAW is not set
+# CONFIG_LINE6_USB_IMPULSE_RESPONSE is not set
+CONFIG_USB_SERIAL_QUATECH2=m
+CONFIG_USB_SERIAL_QUATECH_USB2=m
+# CONFIG_VT6656 is not set
+# CONFIG_IIO is not set
+# CONFIG_FB_SM7XX is not set
+CONFIG_USB_ENESTORAGE=m
+CONFIG_BCM_WIMAX=m
+# CONFIG_FT1000 is not set
+
+#
+# Speakup console speech
+#
+# CONFIG_SPEAKUP is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
+CONFIG_STAGING_MEDIA=y
+CONFIG_DVB_AS102=m
+CONFIG_EASYCAP=m
+# CONFIG_EASYCAP_DEBUG is not set
+CONFIG_LIRC_STAGING=y
+CONFIG_LIRC_IGORPLUGUSB=m
+CONFIG_LIRC_IMON=m
+CONFIG_LIRC_SASEM=m
+CONFIG_LIRC_SERIAL=m
+CONFIG_LIRC_SERIAL_TRANSMITTER=y
+# CONFIG_LIRC_SIR is not set
+CONFIG_LIRC_TTUSBIR=m
+# CONFIG_LIRC_ZILOG is not set
+
+#
+# Android
+#
+CONFIG_ANDROID=y
+# CONFIG_ANDROID_BINDER_IPC is not set
+# CONFIG_ASHMEM is not set
+# CONFIG_ANDROID_LOGGER is not set
+# CONFIG_ANDROID_RAM_CONSOLE is not set
+# CONFIG_ANDROID_TIMED_OUTPUT is not set
+# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set
+# CONFIG_ANDROID_SWITCH is not set
+CONFIG_ION=y
+# CONFIG_ION_TEST is not set
+# CONFIG_ION_DUMMY is not set
+# CONFIG_PHONE is not set
+# CONFIG_USB_WPAN_HCD is not set
+
+#
+# Hardware Spinlock drivers
+#
+CONFIG_IOMMU_SUPPORT=y
+
+#
+# Remoteproc drivers (EXPERIMENTAL)
+#
+
+#
+# Rpmsg drivers (EXPERIMENTAL)
+#
+# CONFIG_VIRT_DRIVERS is not set
+# CONFIG_PM_DEVFREQ is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+CONFIG_JBD2=y
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_REISERFS_FS_XATTR is not set
+CONFIG_JFS_FS=m
+# CONFIG_JFS_POSIX_ACL is not set
+# CONFIG_JFS_SECURITY is not set
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_STATISTICS is not set
+CONFIG_XFS_FS=y
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_BTRFS_FS=m
+# CONFIG_BTRFS_FS_POSIX_ACL is not set
+# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_FANOTIFY=y
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
+CONFIG_GENERIC_ACL=y
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+# CONFIG_NTFS_RW is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+CONFIG_HFS_FS=m
+CONFIG_HFSPLUS_FS=m
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_XATTR is not set
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+# CONFIG_LOGFS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX6FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=m
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+CONFIG_NFSD_V4=y
+# CONFIG_NFSD_FAULT_INJECTION is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=m
+# CONFIG_SUNRPC_DEBUG is not set
+CONFIG_CEPH_FS=m
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_DFS_UPCALL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=y
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_STRIP_ASM_SYMS=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_LOCKUP_DETECTOR=y
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RCU_CPU_STALL_INFO=y
+# CONFIG_RCU_TRACE is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_TEST_KSTRTOX is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="bmem=192M@64M console=ttyS0,1000000 ubi.mtd=rootfs root=ubi0:dreambox-rootfs rootfstype=ubifs rw"
+# CONFIG_CMDLINE_EXTEND is not set
+# CONFIG_CMDLINE_OVERRIDE is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_RUNTIME_DEBUG is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+CONFIG_ENCRYPTED_KEYS=m
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+CONFIG_SECURITYFS=y
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=m
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_USER=m
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_SEQIV=m
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=m
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_VMAC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_GHASH=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_BLOWFISH_COMMON=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SALSA20=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_ZLIB=m
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_USER_API=m
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_IO=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=m
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=m
+CONFIG_CRC8=m
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_ARM is not set
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+# CONFIG_XZ_DEC_SPARC is not set
+# CONFIG_XZ_DEC_BCJ is not set
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_AVERAGE=y
+# CONFIG_CORDIC is not set
diff --git a/arch/mips/configs/dm7080_defconfig b/arch/mips/configs/dm7080_defconfig
new file mode 100644
index 0000000..a453bd5
--- /dev/null
+++ b/arch/mips/configs/dm7080_defconfig
@@ -0,0 +1,3239 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/mips 3.4-4.0 Kernel Configuration
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MIPS_ALCHEMY is not set
+# CONFIG_AR7 is not set
+# CONFIG_ATH79 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
+CONFIG_BRCMSTB=y
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_MACH_JZ4740 is not set
+# CONFIG_LANTIQ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MACH_LOONGSON is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_POWERTV is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+# CONFIG_NLM_XLR_BOARD is not set
+# CONFIG_NLM_XLP_BOARD is not set
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+
+#
+# Broadcom STB options
+#
+# CONFIG_BRCM_LEGACY is not set
+# CONFIG_BCM7228A0 is not set
+# CONFIG_BCM7231B0 is not set
+# CONFIG_BCM7344B0 is not set
+# CONFIG_BCM7346B0 is not set
+# CONFIG_BCM7358A0 is not set
+# CONFIG_BCM7360A0 is not set
+# CONFIG_BCM7362A0 is not set
+# CONFIG_BCM7425B0 is not set
+# CONFIG_BCM7429B0 is not set
+CONFIG_BCM7435B0=y
+# CONFIG_BCM7543A0 is not set
+# CONFIG_BCM7552B0 is not set
+# CONFIG_BCM7563A0 is not set
+# CONFIG_BCM7584A0 is not set
+CONFIG_DREAMBOX=y
+# CONFIG_DREAMBOX_DM820 is not set
+CONFIG_DREAMBOX_DM7080=y
+
+#
+# Memory map
+#
+CONFIG_BRCM_UPPER_MEMORY=y
+# CONFIG_BRCM_OVERRIDE_RAM_SIZE is not set
+
+#
+# Onchip peripherals
+#
+CONFIG_BRCM_CONSOLE_DEVICE=0
+CONFIG_BRCM_FLASH=y
+CONFIG_BRCM_FIXED_MTD_PARTITIONS=y
+# CONFIG_MTD_BRCMNAND is not set
+CONFIG_SPI_BRCMSTB=y
+CONFIG_BCMGENET=y
+
+#
+# BCMGENET options
+#
+# CONFIG_BCMGENET_RX_DESC_THROTTLE is not set
+CONFIG_BCMGENET_NAPI=y
+# CONFIG_BCMGENET_RX_CSUM is not set
+# CONFIG_BCMGENET_TX_CSUM is not set
+# CONFIG_BCMGENET_DUMP_DATA is not set
+# CONFIG_BCMGENET_DUMP_TRACE is not set
+# CONFIG_BRCM_MOCA is not set
+CONFIG_BRCM_USB=y
+CONFIG_BRCM_OVERRIDE_USB=y
+# CONFIG_BRCM_FORCE_USB_PWR_LO is not set
+CONFIG_BRCM_FORCE_USB_PWR_HI=y
+CONFIG_BRCM_FORCE_USB_OC_LO=y
+# CONFIG_BRCM_FORCE_USB_OC_HI is not set
+CONFIG_BRCM_USB_DISABLE_MASK=0x00
+CONFIG_BRCM_SDIO=y
+CONFIG_BRCM_PM=y
+CONFIG_CSRC_WKTMR=y
+# CONFIG_CSRC_UPG is not set
+
+#
+# Miscellaneous options
+#
+CONFIG_BRCM_LIBGCC=y
+CONFIG_BRCM_SCSI_NO_RW10_RETRIES=y
+# CONFIG_BRCM_WLAN_MODULES is not set
+# CONFIG_BRCM_DEBUG_OPTIONS is not set
+CONFIG_BRCM_HAS_BMIPS5000=y
+CONFIG_BRCM_HAS_16550=y
+CONFIG_BRCM_HAS_UARTA=y
+CONFIG_BRCM_UARTA_IS_16550=y
+CONFIG_BRCM_HAS_PCIE=y
+CONFIG_BRCM_GENET_V3=y
+CONFIG_BRCM_GENET_VERSION=3
+CONFIG_BRCM_HAS_GENET=y
+CONFIG_BRCM_HAS_GENET_0=y
+CONFIG_BRCM_HAS_MOCA=y
+CONFIG_BRCM_HAS_MOCA_20_GEN22=y
+CONFIG_BRCM_MOCA_VERS=0x2002
+CONFIG_BRCM_HAS_SATA=y
+CONFIG_BRCM_HAS_SATA3=y
+# CONFIG_BRCM_SATA_75MHZ_PLL is not set
+# CONFIG_BRCM_SATA_SINGLE_PORT is not set
+CONFIG_BRCM_HAS_NOR=y
+CONFIG_BRCM_HAS_NAND_MINOR_2=y
+CONFIG_BRCM_HAS_NAND_MAJOR_6=y
+CONFIG_BRCMNAND_MAJOR_VERS=6
+CONFIG_BRCMNAND_MINOR_VERS=2
+CONFIG_BRCM_HAS_NAND=y
+CONFIG_BRCM_HAS_FLASH_DMA=y
+CONFIG_BRCM_HAS_SPI=y
+CONFIG_BRCM_HAS_BSPI_V4=y
+CONFIG_BRCM_BSPI_MAJOR_VERS=4
+CONFIG_BRCM_HAS_WKTMR=y
+CONFIG_BRCM_HAS_SDIO=y
+CONFIG_BRCM_HAS_SDIO_V1=y
+CONFIG_BRCM_HAS_EMMC=y
+CONFIG_BRCM_ZSCM_L2=y
+CONFIG_BRCM_CPU_DIV=y
+CONFIG_BRCM_HAS_XKS01=y
+CONFIG_BRCM_HAS_XI=y
+CONFIG_BRCM_HAS_DUALCORE=y
+CONFIG_BRCM_HAS_UPPER_MEMORY=y
+CONFIG_BRCM_UPPER_768MB=y
+CONFIG_BRCM_HAS_2GB_MEMC0=y
+CONFIG_BRCM_HAS_1GB_MEMC1=y
+CONFIG_BRCM_HAS_DIGITAL_DDR_PHY=y
+CONFIG_BRCM_PWR_HANDSHAKE=y
+CONFIG_BRCM_PWR_HANDSHAKE_V1=y
+CONFIG_BRCM_HAS_USB_CAPS=y
+CONFIG_BRCM_MIPS_DEFAULTS=y
+CONFIG_BCM7435=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_BOOT_RAW=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CEVT_R4K=y
+CONFIG_CFE=y
+# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
+# CONFIG_MIPS_MACHINE is not set
+# CONFIG_NO_IOPORT is not set
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_MIPS_L1_CACHE_SHIFT=7
+
+#
+# CPU selection
+#
+CONFIG_CPU_BMIPS5000=y
+CONFIG_CPU_BMIPS=y
+CONFIG_SYS_HAS_CPU_BMIPS5000=y
+CONFIG_WEAK_ORDERING=y
+CONFIG_CPU_MIPS32=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_BOARD_SCACHE=y
+CONFIG_MIPS_CPU_SCACHE=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_XKS01=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM=y
+CONFIG_HAVE_MEMORY_PRESENT=y
+CONFIG_SPARSEMEM_STATIC=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_COMPACTION is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_CLEANCACHE=y
+CONFIG_SMP=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_NR_CPUS=4
+CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_256 is not set
+CONFIG_HZ_1000=y
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=1000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_KEXEC=y
+CONFIG_SECCOMP=y
+CONFIG_CC_STACKPROTECTOR=y
+# CONFIG_USE_OF is not set
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_HAVE_IRQ_WORK=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION="-dm7080"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_DEFAULT_HOSTNAME="dm7080"
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_FHANDLE=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_IRQ_FORCED_THREADING=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_RCU_FAST_NO_HZ is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+# CONFIG_CGROUP_MEM_RES_CTLR is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_CFS_BANDWIDTH is not set
+# CONFIG_RT_GROUP_SCHED is not set
+# CONFIG_BLK_CGROUP is not set
+# CONFIG_CHECKPOINT_RESTORE is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_NET_NS=y
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EXPERT=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_PCI_QUIRKS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+# CONFIG_JUMP_LABEL is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+
+#
+# GCOV-based kernel profiling
+#
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+CONFIG_LDM_PARTITION=y
+# CONFIG_LDM_DEBUG is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_FREEZER=y
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+# CONFIG_PCI_PRI is not set
+# CONFIG_PCI_PASID is not set
+CONFIG_MMU=y
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+# CONFIG_RAPIDIO is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_TRAD_SIGNALS=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_SUSPEND is not set
+# CONFIG_HIBERNATION is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+# CONFIG_UNIX_DIAG is not set
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_ROUTE_CLASSID=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=y
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_ACCT=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_PROCFS=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_TIMEOUT=y
+# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
+CONFIG_NF_CT_PROTO_DCCP=m
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_BROADCAST=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NF_CT_NETLINK_TIMEOUT=m
+CONFIG_NETFILTER_TPROXY=m
+CONFIG_NETFILTER_XTABLES=m
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=m
+CONFIG_NETFILTER_XT_CONNMARK=m
+CONFIG_NETFILTER_XT_SET=m
+
+#
+# Xtables targets
+#
+# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+# CONFIG_NETFILTER_XT_TARGET_CT is not set
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HL=m
+# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
+CONFIG_NETFILTER_XT_TARGET_LED=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+
+#
+# Xtables matches
+#
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ECN=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_HL=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_MAX=256
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+# CONFIG_NF_NAT_SNMP_BASIC is not set
+CONFIG_NF_NAT_PROTO_DCCP=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_PROTO_UDPLITE=m
+CONFIG_NF_NAT_PROTO_SCTP=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV6=m
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_QUEUE=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+# CONFIG_BRIDGE_NF_EBTABLES is not set
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_L2TP=y
+# CONFIG_L2TP_V3 is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=m
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+CONFIG_NET_SCH_SFB=m
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+# CONFIG_NET_SCH_MQPRIO is not set
+# CONFIG_NET_SCH_CHOKE is not set
+# CONFIG_NET_SCH_QFQ is not set
+CONFIG_NET_SCH_PLUG=m
+
+#
+# Classification
+#
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_CLS_CGROUP is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+CONFIG_DNS_RESOLVER=y
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_OPENVSWITCH is not set
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+# CONFIG_NETPRIO_CGROUP is not set
+CONFIG_BQL=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=y
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIUART is not set
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+CONFIG_BT_ATH3K=m
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_PRIV=y
+CONFIG_CFG80211=y
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+# CONFIG_CFG80211_DEFAULT_PS is not set
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=y
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_RC_PID=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL_HT=y
+# CONFIG_MAC80211_RC_DEFAULT_PID is not set
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+CONFIG_CEPH_LIB=m
+# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
+# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
+# CONFIG_NFC is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_GENERIC_CPU_DEVICES is not set
+CONFIG_DMA_SHARED_BUFFER=y
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+# CONFIG_MTD_CHAR is not set
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+# CONFIG_MTD_SWAP is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOCG3 is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=2
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_NVME is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_UB=m
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+CONFIG_ATA_OVER_ETH=m
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_BLK_DEV_RBD is not set
+
+#
+# Misc devices
+#
+# CONFIG_SENSORS_LIS3LV02D is not set
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_INTEL_MID_PTI is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_BMP085 is not set
+# CONFIG_PCH_PHUB is not set
+# CONFIG_USB_SWITCH_FSA9480 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+CONFIG_EEPROM_93CX6=m
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_CB710_CORE is not set
+# CONFIG_IWMC3200TOP is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+
+#
+# Altera FPGA firmware download module
+#
+# CONFIG_ALTERA_STAPL is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+# CONFIG_SATA_PMP is not set
+
+#
+# Controllers with non-SFF native interface
+#
+# CONFIG_SATA_AHCI is not set
+CONFIG_SATA_AHCI_PLATFORM=y
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_ACARD_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+
+#
+# SFF controllers with custom DMA interface
+#
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SX4 is not set
+CONFIG_ATA_BMDMA=y
+
+#
+# SATA SFF controllers with BMDMA
+#
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+
+#
+# PATA SFF controllers with BMDMA
+#
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CS5536 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RDC is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+
+#
+# PIO-only SFF controllers
+#
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_RZ1000 is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_LEGACY is not set
+CONFIG_MD=y
+# CONFIG_BLK_DEV_MD is not set
+CONFIG_BLK_DEV_DM_BUILTIN=y
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_THIN_PROVISIONING is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_RAID is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+# CONFIG_DM_UEVENT is not set
+# CONFIG_DM_FLAKEY is not set
+# CONFIG_DM_VERITY is not set
+# CONFIG_TARGET_CORE is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_FIREWIRE_NOSY is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+# CONFIG_DUMMY is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_NET_FC is not set
+CONFIG_MII=y
+# CONFIG_NET_TEAM is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+CONFIG_TUN=y
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+
+#
+# CAIF transport drivers
+#
+CONFIG_ETHERNET=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+CONFIG_NET_VENDOR_BROADCOM=y
+# CONFIG_B44 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_CNIC is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2X is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_CALXEDA_XGMAC is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_DM9000 is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_HP is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_IP1000 is not set
+# CONFIG_JME is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+CONFIG_NET_VENDOR_MICROCHIP=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_ETHOC is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_SFC is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_TOSHIBA is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PHYLIB is not set
+# CONFIG_MICREL_KS8995MA is not set
+CONFIG_PPP=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOE=m
+# CONFIG_PPPOL2TP is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_TR is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_EEM=m
+CONFIG_USB_NET_CDC_NCM=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_NET_CX82310_ETH=m
+CONFIG_USB_NET_KALMIA=m
+CONFIG_USB_NET_QMI_WWAN=m
+CONFIG_USB_NET_INT51X1=m
+CONFIG_USB_IPHETH=m
+CONFIG_USB_SIERRA_NET=m
+CONFIG_USB_VL600=m
+CONFIG_WLAN=y
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_ATMEL is not set
+CONFIG_AT76C50X_USB=m
+# CONFIG_PRISM54 is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_RTL8180 is not set
+CONFIG_RTL8187=m
+CONFIG_RTL8187_LEDS=y
+# CONFIG_ADM8211 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_MWL8K is not set
+CONFIG_ATH_COMMON=m
+# CONFIG_ATH_DEBUG is not set
+CONFIG_ATH5K=m
+# CONFIG_ATH5K_DEBUG is not set
+CONFIG_ATH5K_PCI=y
+CONFIG_ATH9K_HW=m
+CONFIG_ATH9K_COMMON=m
+# CONFIG_ATH9K_BTCOEX_SUPPORT is not set
+CONFIG_ATH9K=m
+# CONFIG_ATH9K_PCI is not set
+# CONFIG_ATH9K_AHB is not set
+# CONFIG_ATH9K_DFS_CERTIFIED is not set
+# CONFIG_ATH9K_LEGACY_RATE_CONTROL is not set
+# CONFIG_ATH9K_HTC is not set
+CONFIG_CARL9170=m
+CONFIG_CARL9170_LEDS=y
+CONFIG_CARL9170_WPC=y
+# CONFIG_ATH6KL is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_BRCMFMAC is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_IWLWIFI is not set
+# CONFIG_IWL4965 is not set
+# CONFIG_IWL3945 is not set
+# CONFIG_IWM is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+CONFIG_P54_COMMON=m
+CONFIG_P54_USB=m
+# CONFIG_P54_PCI is not set
+# CONFIG_P54_SPI is not set
+CONFIG_P54_LEDS=y
+CONFIG_RT2X00=m
+# CONFIG_RT2400PCI is not set
+# CONFIG_RT2500PCI is not set
+# CONFIG_RT61PCI is not set
+# CONFIG_RT2800PCI is not set
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT35XX=y
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RT2800_LIB=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
+# CONFIG_RTL8192CE is not set
+# CONFIG_RTL8192SE is not set
+# CONFIG_RTL8192DE is not set
+CONFIG_RTL8192CU=m
+CONFIG_RTLWIFI=m
+# CONFIG_RTLWIFI_DEBUG is not set
+CONFIG_RTL8192C_COMMON=m
+# CONFIG_WL1251 is not set
+# CONFIG_WL12XX_MENU is not set
+CONFIG_ZD1211RW=m
+# CONFIG_ZD1211RW_DEBUG is not set
+# CONFIG_MWIFIEX is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_VMXNET3 is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=m
+CONFIG_INPUT_POLLDEV=m
+CONFIG_INPUT_SPARSEKMAP=m
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_BMA150 is not set
+# CONFIG_INPUT_MMA8450 is not set
+# CONFIG_INPUT_MPU3050 is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_KXTJ9 is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=m
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_CMA3000 is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+# CONFIG_DEVKMEM is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX3107 is not set
+# CONFIG_SERIAL_MFD_HSU is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_PCH_UART is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_TTY_PRINTK is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_RAMOOPS=m
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_MUX is not set
+# CONFIG_I2C_HELPER_AUTO is not set
+# CONFIG_I2C_SMBUS is not set
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE_PCI is not set
+# CONFIG_I2C_EG20T is not set
+# CONFIG_I2C_INTEL_MID is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+CONFIG_I2C_BRCMSTB=m
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_TOPCLIFF_PCH is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_HSI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+
+#
+# Enable Device Drivers -> PPS to see the PTP clock options.
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=m
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2781 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_SBS is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_LP8727 is not set
+# CONFIG_CHARGER_SMB347 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7314 is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_MCP3021 is not set
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_PMBUS is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SCH56XX_COMMON is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_SCH5636 is not set
+CONFIG_SENSORS_ADC128D818=y
+# CONFIG_SENSORS_ADS1015 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+CONFIG_SENSORS_INA2XX=y
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+
+#
+# Broadcom specific AMBA
+#
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS65217 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_TWL6040_CORE is not set
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_DA9052_SPI is not set
+# CONFIG_MFD_DA9052_I2C is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_S5M_CORE is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13XXX is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_TPS65090 is not set
+# CONFIG_MFD_RC5T583 is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+# CONFIG_MEDIA_CONTROLLER is not set
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_DVB_CORE=y
+CONFIG_DVB_NET=y
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+CONFIG_RC_CORE=y
+CONFIG_LIRC=y
+CONFIG_RC_MAP=m
+CONFIG_IR_NEC_DECODER=m
+CONFIG_IR_RC5_DECODER=m
+CONFIG_IR_RC6_DECODER=m
+CONFIG_IR_JVC_DECODER=m
+CONFIG_IR_SONY_DECODER=m
+CONFIG_IR_RC5_SZ_DECODER=m
+CONFIG_IR_SANYO_DECODER=m
+CONFIG_IR_MCE_KBD_DECODER=m
+CONFIG_IR_LIRC_CODEC=m
+CONFIG_RC_ATI_REMOTE=m
+CONFIG_IR_IMON=m
+CONFIG_IR_MCEUSB=m
+CONFIG_IR_REDRAT3=m
+CONFIG_IR_STREAMZAP=m
+CONFIG_RC_LOOPBACK=m
+# CONFIG_IR_GPIO_CIR is not set
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=m
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_TUNER_XC4000=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_MEDIA_TUNER_MXL5007T=m
+CONFIG_MEDIA_TUNER_MC44S803=m
+CONFIG_MEDIA_TUNER_MAX2165=m
+CONFIG_MEDIA_TUNER_TDA18218=m
+CONFIG_MEDIA_TUNER_TUA9001=m
+CONFIG_MEDIA_TUNER_TDA18212=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEOBUF_VMALLOC=m
+CONFIG_VIDEOBUF_DVB=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEOBUF2_CORE=m
+CONFIG_VIDEOBUF2_MEMOPS=m
+CONFIG_VIDEOBUF2_VMALLOC=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_VIDEO_IR_I2C=m
+
+#
+# Audio decoders, processors and mixers
+#
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_WM8775=m
+
+#
+# RDS decoders
+#
+
+#
+# Video decoders
+#
+CONFIG_VIDEO_SAA711X=m
+CONFIG_VIDEO_TVP5150=m
+
+#
+# Video and audio decoders
+#
+CONFIG_VIDEO_CX25840=m
+
+#
+# MPEG video encoders
+#
+CONFIG_VIDEO_CX2341X=m
+
+#
+# Video encoders
+#
+
+#
+# Camera sensor devices
+#
+CONFIG_VIDEO_MT9V011=m
+
+#
+# Flash devices
+#
+
+#
+# Video improvement chips
+#
+
+#
+# Miscelaneous helper chips
+#
+# CONFIG_VIDEO_VIVI is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+# CONFIG_USB_M5602 is not set
+# CONFIG_USB_STV06XX is not set
+# CONFIG_USB_GL860 is not set
+# CONFIG_USB_GSPCA_BENQ is not set
+# CONFIG_USB_GSPCA_CONEX is not set
+# CONFIG_USB_GSPCA_CPIA1 is not set
+# CONFIG_USB_GSPCA_ETOMS is not set
+# CONFIG_USB_GSPCA_FINEPIX is not set
+# CONFIG_USB_GSPCA_JEILINJ is not set
+# CONFIG_USB_GSPCA_JL2005BCD is not set
+# CONFIG_USB_GSPCA_KINECT is not set
+# CONFIG_USB_GSPCA_KONICA is not set
+# CONFIG_USB_GSPCA_MARS is not set
+# CONFIG_USB_GSPCA_MR97310A is not set
+# CONFIG_USB_GSPCA_NW80X is not set
+# CONFIG_USB_GSPCA_OV519 is not set
+# CONFIG_USB_GSPCA_OV534 is not set
+# CONFIG_USB_GSPCA_OV534_9 is not set
+# CONFIG_USB_GSPCA_PAC207 is not set
+# CONFIG_USB_GSPCA_PAC7302 is not set
+# CONFIG_USB_GSPCA_PAC7311 is not set
+# CONFIG_USB_GSPCA_SE401 is not set
+# CONFIG_USB_GSPCA_SN9C2028 is not set
+# CONFIG_USB_GSPCA_SN9C20X is not set
+# CONFIG_USB_GSPCA_SONIXB is not set
+# CONFIG_USB_GSPCA_SONIXJ is not set
+# CONFIG_USB_GSPCA_SPCA500 is not set
+# CONFIG_USB_GSPCA_SPCA501 is not set
+# CONFIG_USB_GSPCA_SPCA505 is not set
+# CONFIG_USB_GSPCA_SPCA506 is not set
+# CONFIG_USB_GSPCA_SPCA508 is not set
+# CONFIG_USB_GSPCA_SPCA561 is not set
+# CONFIG_USB_GSPCA_SPCA1528 is not set
+# CONFIG_USB_GSPCA_SQ905 is not set
+# CONFIG_USB_GSPCA_SQ905C is not set
+# CONFIG_USB_GSPCA_SQ930X is not set
+# CONFIG_USB_GSPCA_STK014 is not set
+# CONFIG_USB_GSPCA_STV0680 is not set
+# CONFIG_USB_GSPCA_SUNPLUS is not set
+# CONFIG_USB_GSPCA_T613 is not set
+# CONFIG_USB_GSPCA_TOPRO is not set
+# CONFIG_USB_GSPCA_TV8532 is not set
+# CONFIG_USB_GSPCA_VC032X is not set
+# CONFIG_USB_GSPCA_VICAM is not set
+# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
+# CONFIG_USB_GSPCA_ZC3XX is not set
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_PVRUSB2_DVB=y
+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
+CONFIG_VIDEO_HDPVR=m
+CONFIG_VIDEO_EM28XX=m
+CONFIG_VIDEO_EM28XX_ALSA=m
+CONFIG_VIDEO_EM28XX_DVB=m
+# CONFIG_VIDEO_EM28XX_RC is not set
+CONFIG_VIDEO_TLG2300=m
+CONFIG_VIDEO_CX231XX=m
+CONFIG_VIDEO_CX231XX_RC=y
+CONFIG_VIDEO_CX231XX_ALSA=m
+CONFIG_VIDEO_CX231XX_DVB=m
+CONFIG_VIDEO_TM6000=m
+CONFIG_VIDEO_TM6000_ALSA=m
+CONFIG_VIDEO_TM6000_DVB=m
+CONFIG_VIDEO_USBVISION=m
+CONFIG_USB_ET61X251=m
+CONFIG_USB_SN9C102=m
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+CONFIG_USB_PWC_INPUT_EVDEV=y
+# CONFIG_VIDEO_CPIA2 is not set
+CONFIG_USB_ZR364XX=m
+CONFIG_USB_STKWEBCAM=m
+CONFIG_USB_S2255=m
+# CONFIG_V4L_PCI_DRIVERS is not set
+# CONFIG_V4L_PLATFORM_DRIVERS is not set
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+# CONFIG_VIDEO_MEM2MEM_TESTDEV is not set
+# CONFIG_RADIO_ADAPTERS is not set
+CONFIG_DVB_MAX_ADAPTERS=8
+CONFIG_DVB_DYNAMIC_MINORS=y
+CONFIG_DVB_CAPTURE_DRIVERS=y
+
+#
+# Supported SAA7146 based PCI Adapters
+#
+CONFIG_TTPCI_EEPROM=m
+# CONFIG_DVB_AV7110 is not set
+# CONFIG_DVB_BUDGET_CORE is not set
+
+#
+# Supported USB Adapters
+#
+CONFIG_DVB_USB=m
+# CONFIG_DVB_USB_DEBUG is not set
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_DIBUSB_MB=m
+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+CONFIG_DVB_USB_PCTV452E=m
+CONFIG_DVB_USB_DW2102=m
+CONFIG_DVB_USB_CINERGY_T2=m
+CONFIG_DVB_USB_ANYSEE=m
+CONFIG_DVB_USB_DTV5100=m
+CONFIG_DVB_USB_AF9015=m
+CONFIG_DVB_USB_A867=m
+CONFIG_DVB_USB_AF9035=m
+CONFIG_DVB_USB_CE6230=m
+CONFIG_DVB_USB_FRIIO=m
+CONFIG_DVB_USB_EC168=m
+CONFIG_DVB_USB_AZ6007=m
+CONFIG_DVB_USB_AZ6027=m
+CONFIG_DVB_USB_LME2510=m
+CONFIG_DVB_USB_TECHNISAT_USB2=m
+CONFIG_DVB_USB_IT913X=m
+CONFIG_DVB_USB_MXL111SF=m
+CONFIG_DVB_USB_RTL28XXU=m
+CONFIG_DVB_TTUSB_BUDGET=m
+CONFIG_DVB_TTUSB_DEC=m
+CONFIG_SMS_SIANO_MDTV=m
+
+#
+# Siano module components
+#
+CONFIG_SMS_USB_DRV=m
+# CONFIG_SMS_SDIO_DRV is not set
+
+#
+# Supported FlexCopII (B2C2) Adapters
+#
+CONFIG_DVB_B2C2_FLEXCOP=m
+# CONFIG_DVB_B2C2_FLEXCOP_PCI is not set
+CONFIG_DVB_B2C2_FLEXCOP_USB=m
+# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set
+
+#
+# Supported BT878 Adapters
+#
+
+#
+# Supported Pluto2 Adapters
+#
+# CONFIG_DVB_PLUTO2 is not set
+
+#
+# Supported SDMC DM1105 Adapters
+#
+# CONFIG_DVB_DM1105 is not set
+
+#
+# Supported Earthsoft PT1 Adapters
+#
+# CONFIG_DVB_PT1 is not set
+
+#
+# Supported Mantis Adapters
+#
+# CONFIG_MANTIS_CORE is not set
+
+#
+# Supported nGene Adapters
+#
+# CONFIG_DVB_NGENE is not set
+
+#
+# Supported ddbridge ('Octopus') Adapters
+#
+# CONFIG_DVB_DDBRIDGE is not set
+
+#
+# Supported DVB Frontends
+#
+CONFIG_DVB_FE_CUSTOMISE=y
+
+#
+# Customise DVB Frontends
+#
+
+#
+# Multistandard (satellite) frontends
+#
+CONFIG_DVB_STB0899=m
+CONFIG_DVB_STB6100=m
+CONFIG_DVB_STV090x=m
+CONFIG_DVB_STV6110x=m
+
+#
+# Multistandard (cable + terrestrial) frontends
+#
+CONFIG_DVB_DRXK=m
+CONFIG_DVB_TDA18271C2DD=m
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_ZL10036=m
+CONFIG_DVB_ZL10039=m
+CONFIG_DVB_S5H1420=m
+CONFIG_DVB_STV0288=m
+CONFIG_DVB_STB6000=m
+CONFIG_DVB_STV0299=y
+CONFIG_DVB_STV6110=m
+CONFIG_DVB_STV0900=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_TDA8261=m
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_TUNER_CX24113=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TUA6100=m
+CONFIG_DVB_CX24116=m
+CONFIG_DVB_SI21XX=m
+CONFIG_DVB_DS3000=m
+CONFIG_DVB_MB86A16=m
+CONFIG_DVB_TDA10071=m
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_SP8870=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+CONFIG_DVB_S5H1432=m
+CONFIG_DVB_DRXD=m
+CONFIG_DVB_L64781=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_DIB9000=m
+CONFIG_DVB_TDA10048=m
+CONFIG_DVB_AF9013=m
+CONFIG_DVB_AF9033=m
+CONFIG_DVB_EC100=m
+CONFIG_DVB_HD29L2=m
+CONFIG_DVB_STV0367=m
+CONFIG_DVB_CXD2820R=m
+CONFIG_DVB_RTL2830=m
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_STV0297=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_NXT200X=m
+CONFIG_DVB_OR51211=m
+CONFIG_DVB_OR51132=m
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_LGDT3305=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_S5H1411=m
+
+#
+# ISDB-T (terrestrial) frontends
+#
+CONFIG_DVB_S921=m
+CONFIG_DVB_DIB8000=m
+CONFIG_DVB_MB86A20S=m
+
+#
+# Digital terrestrial only tuners/PLL
+#
+CONFIG_DVB_PLL=m
+CONFIG_DVB_TUNER_DIB0070=m
+CONFIG_DVB_TUNER_DIB0090=m
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_LNBP21=m
+CONFIG_DVB_LNBP22=m
+CONFIG_DVB_ISL6405=m
+CONFIG_DVB_ISL6421=m
+CONFIG_DVB_ISL6423=m
+CONFIG_DVB_A8293=m
+CONFIG_DVB_LGS8GL5=m
+CONFIG_DVB_LGS8GXX=m
+CONFIG_DVB_ATBM8830=m
+CONFIG_DVB_TDA665x=m
+CONFIG_DVB_IX2505V=m
+CONFIG_DVB_IT913X_FE=m
+CONFIG_DVB_M88RS2000=m
+
+#
+# Tools to develop new frontends
+#
+CONFIG_DVB_DUMMY_FE=m
+
+#
+# Graphics support
+#
+# CONFIG_VGA_ARB is not set
+# CONFIG_DRM is not set
+# CONFIG_STUB_POULSBO is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_WMT_GE_ROPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_I740 is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SMSCUFX is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_EXYNOS_VIDEO is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=m
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_HRTIMER is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_PCI is not set
+CONFIG_SND_SPI=y
+# CONFIG_SND_MIPS is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+# CONFIG_SND_USB_UA101 is not set
+CONFIG_SND_USB_CAIAQ=m
+# CONFIG_SND_USB_CAIAQ_INPUT is not set
+# CONFIG_SND_USB_6FIRE is not set
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# USB HID Boot Protocol drivers
+#
+CONFIG_USB_KBD=m
+CONFIG_USB_MOUSE=m
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_ACRUX is not set
+CONFIG_HID_APPLE=m
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_PRODIKEYS is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EMS_FF is not set
+# CONFIG_HID_ELECOM is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_HOLTEK is not set
+# CONFIG_HID_KEYTOUCH is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LCPOWER is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_PRIMAX is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_SAITEK is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SPEEDLINK is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TIVO is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_WACOM is not set
+CONFIG_HID_WIIMOTE=m
+CONFIG_HID_WIIMOTE_EXT=y
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB_ARCH_HAS_XHCI=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_XHCI_HCD=y
+# CONFIG_USB_XHCI_HCD_DEBUGGING is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_REALTEK=m
+CONFIG_REALTEK_AUTOPM=y
+CONFIG_USB_STORAGE_DATAFAB=m
+CONFIG_USB_STORAGE_FREECOM=m
+CONFIG_USB_STORAGE_ISD200=m
+CONFIG_USB_STORAGE_USBAT=m
+CONFIG_USB_STORAGE_SDDR09=m
+CONFIG_USB_STORAGE_SDDR55=m
+CONFIG_USB_STORAGE_JUMPSHOT=m
+CONFIG_USB_STORAGE_ALAUDA=m
+CONFIG_USB_STORAGE_ONETOUCH=m
+CONFIG_USB_STORAGE_KARMA=m
+CONFIG_USB_STORAGE_CYPRESS_ATACB=m
+CONFIG_USB_STORAGE_ENE_UB6250=m
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_FUNSOFT=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_F81232=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+# CONFIG_USB_SERIAL_METRO is not set
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MOTOROLA=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_QCAUX=m
+CONFIG_USB_SERIAL_QUALCOMM=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_HP4X=m
+CONFIG_USB_SERIAL_SAFE=m
+# CONFIG_USB_SERIAL_SAFE_PADDED is not set
+CONFIG_USB_SERIAL_SIEMENS_MPI=m
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_SYMBOL=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_WWAN=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_OPTICON=m
+CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
+CONFIG_USB_SERIAL_ZIO=m
+CONFIG_USB_SERIAL_SSU100=m
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_UWB is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+# CONFIG_MMC_CLKGATE is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_TIFM_SD is not set
+# CONFIG_MMC_CB710 is not set
+# CONFIG_MMC_VIA_SDMMC is not set
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP5523 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_PCA9633 is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_TCA6507 is not set
+# CONFIG_LEDS_OT200 is not set
+CONFIG_LEDS_TRIGGERS=y
+
+#
+# LED Triggers
+#
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=m
+# CONFIG_UIO_CIF is not set
+CONFIG_UIO_PDRV=m
+CONFIG_UIO_PDRV_GENIRQ=m
+# CONFIG_UIO_AEC is not set
+# CONFIG_UIO_SERCOS3 is not set
+# CONFIG_UIO_PCI_GENERIC is not set
+# CONFIG_UIO_NETX is not set
+
+#
+# Virtio drivers
+#
+# CONFIG_VIRTIO_PCI is not set
+# CONFIG_VIRTIO_BALLOON is not set
+# CONFIG_VIRTIO_MMIO is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+CONFIG_STAGING=y
+# CONFIG_ET131X is not set
+CONFIG_USBIP_CORE=m
+CONFIG_USBIP_VHCI_HCD=m
+CONFIG_USBIP_HOST=m
+# CONFIG_USBIP_DEBUG is not set
+# CONFIG_W35UND is not set
+CONFIG_PRISM2_USB=m
+# CONFIG_ECHO is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_R8187SE is not set
+CONFIG_RTL8192U=m
+CONFIG_RTLLIB=m
+CONFIG_RTLLIB_CRYPTO_CCMP=m
+CONFIG_RTLLIB_CRYPTO_TKIP=m
+CONFIG_RTLLIB_CRYPTO_WEP=m
+# CONFIG_RTL8192E is not set
+CONFIG_R8712U=m
+# CONFIG_RTS_PSTOR is not set
+CONFIG_RTS5139=m
+# CONFIG_RTS5139_DEBUG is not set
+CONFIG_TRANZPORT=m
+# CONFIG_IDE_PHISON is not set
+CONFIG_LINE6_USB=m
+# CONFIG_LINE6_USB_DEBUG is not set
+# CONFIG_LINE6_USB_DUMP_CTRL is not set
+# CONFIG_LINE6_USB_DUMP_MIDI is not set
+# CONFIG_LINE6_USB_DUMP_PCM is not set
+# CONFIG_LINE6_USB_RAW is not set
+# CONFIG_LINE6_USB_IMPULSE_RESPONSE is not set
+CONFIG_USB_SERIAL_QUATECH2=m
+CONFIG_USB_SERIAL_QUATECH_USB2=m
+# CONFIG_VT6655 is not set
+# CONFIG_VT6656 is not set
+# CONFIG_VME_BUS is not set
+# CONFIG_DX_SEP is not set
+# CONFIG_IIO is not set
+# CONFIG_FB_SM7XX is not set
+# CONFIG_CRYSTALHD is not set
+# CONFIG_FB_XGI is not set
+CONFIG_USB_ENESTORAGE=m
+CONFIG_BCM_WIMAX=m
+# CONFIG_FT1000 is not set
+
+#
+# Speakup console speech
+#
+# CONFIG_SPEAKUP is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
+CONFIG_STAGING_MEDIA=y
+CONFIG_DVB_AS102=m
+CONFIG_DVB_CXD2099=m
+# CONFIG_VIDEO_DT3155 is not set
+CONFIG_EASYCAP=m
+# CONFIG_EASYCAP_DEBUG is not set
+# CONFIG_VIDEO_GO7007 is not set
+# CONFIG_SOLO6X10 is not set
+CONFIG_LIRC_STAGING=y
+# CONFIG_LIRC_BT829 is not set
+CONFIG_LIRC_IGORPLUGUSB=m
+CONFIG_LIRC_IMON=m
+CONFIG_LIRC_SASEM=m
+CONFIG_LIRC_SERIAL=m
+CONFIG_LIRC_SERIAL_TRANSMITTER=y
+# CONFIG_LIRC_SIR is not set
+CONFIG_LIRC_TTUSBIR=m
+# CONFIG_LIRC_ZILOG is not set
+
+#
+# Android
+#
+CONFIG_ANDROID=y
+# CONFIG_ANDROID_BINDER_IPC is not set
+# CONFIG_ASHMEM is not set
+# CONFIG_ANDROID_LOGGER is not set
+# CONFIG_ANDROID_RAM_CONSOLE is not set
+# CONFIG_ANDROID_TIMED_OUTPUT is not set
+# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set
+# CONFIG_ANDROID_SWITCH is not set
+CONFIG_ION=y
+# CONFIG_ION_TEST is not set
+# CONFIG_ION_DUMMY is not set
+# CONFIG_PHONE is not set
+# CONFIG_USB_WPAN_HCD is not set
+
+#
+# Hardware Spinlock drivers
+#
+CONFIG_IOMMU_SUPPORT=y
+
+#
+# Remoteproc drivers (EXPERIMENTAL)
+#
+
+#
+# Rpmsg drivers (EXPERIMENTAL)
+#
+# CONFIG_VIRT_DRIVERS is not set
+# CONFIG_PM_DEVFREQ is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+CONFIG_JBD2=y
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_REISERFS_FS_XATTR is not set
+CONFIG_JFS_FS=m
+# CONFIG_JFS_POSIX_ACL is not set
+# CONFIG_JFS_SECURITY is not set
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_STATISTICS is not set
+CONFIG_XFS_FS=y
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_BTRFS_FS=m
+# CONFIG_BTRFS_FS_POSIX_ACL is not set
+# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_FANOTIFY=y
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
+CONFIG_GENERIC_ACL=y
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+# CONFIG_NTFS_RW is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+CONFIG_HFS_FS=m
+CONFIG_HFSPLUS_FS=m
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_LOGFS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX6FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=m
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+CONFIG_NFSD_V4=y
+# CONFIG_NFSD_FAULT_INJECTION is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=m
+# CONFIG_SUNRPC_DEBUG is not set
+CONFIG_CEPH_FS=m
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_DFS_UPCALL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=y
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_STRIP_ASM_SYMS=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_LOCKUP_DETECTOR=y
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RCU_CPU_STALL_INFO=y
+# CONFIG_RCU_TRACE is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_TEST_KSTRTOX is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="bmem=512M@512M memc1=768M console=ttyS0,1000000 root=/dev/mmcblk0p1 rootwait rootfstype=ext4"
+# CONFIG_CMDLINE_EXTEND is not set
+# CONFIG_CMDLINE_OVERRIDE is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_RUNTIME_DEBUG is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+CONFIG_ENCRYPTED_KEYS=m
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+CONFIG_SECURITYFS=y
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=m
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_USER=m
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_SEQIV=m
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=m
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_VMAC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_GHASH=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_BLOWFISH_COMMON=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SALSA20=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_ZLIB=m
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_USER_API=m
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_IO=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=m
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=m
+CONFIG_CRC8=m
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_ARM is not set
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+# CONFIG_XZ_DEC_SPARC is not set
+# CONFIG_XZ_DEC_BCJ is not set
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_AVERAGE=y
+# CONFIG_CORDIC is not set
diff --git a/arch/mips/configs/dm820_defconfig b/arch/mips/configs/dm820_defconfig
new file mode 100644
index 0000000..5b9482f
--- /dev/null
+++ b/arch/mips/configs/dm820_defconfig
@@ -0,0 +1,3239 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/mips 3.4-4.0 Kernel Configuration
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MIPS_ALCHEMY is not set
+# CONFIG_AR7 is not set
+# CONFIG_ATH79 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
+CONFIG_BRCMSTB=y
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_MACH_JZ4740 is not set
+# CONFIG_LANTIQ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MACH_LOONGSON is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_POWERTV is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+# CONFIG_NLM_XLR_BOARD is not set
+# CONFIG_NLM_XLP_BOARD is not set
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+
+#
+# Broadcom STB options
+#
+# CONFIG_BRCM_LEGACY is not set
+# CONFIG_BCM7228A0 is not set
+# CONFIG_BCM7231B0 is not set
+# CONFIG_BCM7344B0 is not set
+# CONFIG_BCM7346B0 is not set
+# CONFIG_BCM7358A0 is not set
+# CONFIG_BCM7360A0 is not set
+# CONFIG_BCM7362A0 is not set
+# CONFIG_BCM7425B0 is not set
+# CONFIG_BCM7429B0 is not set
+CONFIG_BCM7435B0=y
+# CONFIG_BCM7543A0 is not set
+# CONFIG_BCM7552B0 is not set
+# CONFIG_BCM7563A0 is not set
+# CONFIG_BCM7584A0 is not set
+CONFIG_DREAMBOX=y
+CONFIG_DREAMBOX_DM820=y
+# CONFIG_DREAMBOX_DM7080 is not set
+
+#
+# Memory map
+#
+CONFIG_BRCM_UPPER_MEMORY=y
+# CONFIG_BRCM_OVERRIDE_RAM_SIZE is not set
+
+#
+# Onchip peripherals
+#
+CONFIG_BRCM_CONSOLE_DEVICE=0
+CONFIG_BRCM_FLASH=y
+CONFIG_BRCM_FIXED_MTD_PARTITIONS=y
+# CONFIG_MTD_BRCMNAND is not set
+CONFIG_SPI_BRCMSTB=y
+CONFIG_BCMGENET=y
+
+#
+# BCMGENET options
+#
+# CONFIG_BCMGENET_RX_DESC_THROTTLE is not set
+CONFIG_BCMGENET_NAPI=y
+# CONFIG_BCMGENET_RX_CSUM is not set
+# CONFIG_BCMGENET_TX_CSUM is not set
+# CONFIG_BCMGENET_DUMP_DATA is not set
+# CONFIG_BCMGENET_DUMP_TRACE is not set
+# CONFIG_BRCM_MOCA is not set
+CONFIG_BRCM_USB=y
+CONFIG_BRCM_OVERRIDE_USB=y
+# CONFIG_BRCM_FORCE_USB_PWR_LO is not set
+CONFIG_BRCM_FORCE_USB_PWR_HI=y
+CONFIG_BRCM_FORCE_USB_OC_LO=y
+# CONFIG_BRCM_FORCE_USB_OC_HI is not set
+CONFIG_BRCM_USB_DISABLE_MASK=0x00
+CONFIG_BRCM_SDIO=y
+CONFIG_BRCM_PM=y
+CONFIG_CSRC_WKTMR=y
+# CONFIG_CSRC_UPG is not set
+
+#
+# Miscellaneous options
+#
+CONFIG_BRCM_LIBGCC=y
+CONFIG_BRCM_SCSI_NO_RW10_RETRIES=y
+# CONFIG_BRCM_WLAN_MODULES is not set
+# CONFIG_BRCM_DEBUG_OPTIONS is not set
+CONFIG_BRCM_HAS_BMIPS5000=y
+CONFIG_BRCM_HAS_16550=y
+CONFIG_BRCM_HAS_UARTA=y
+CONFIG_BRCM_UARTA_IS_16550=y
+CONFIG_BRCM_HAS_PCIE=y
+CONFIG_BRCM_GENET_V3=y
+CONFIG_BRCM_GENET_VERSION=3
+CONFIG_BRCM_HAS_GENET=y
+CONFIG_BRCM_HAS_GENET_0=y
+CONFIG_BRCM_HAS_MOCA=y
+CONFIG_BRCM_HAS_MOCA_20_GEN22=y
+CONFIG_BRCM_MOCA_VERS=0x2002
+CONFIG_BRCM_HAS_SATA=y
+CONFIG_BRCM_HAS_SATA3=y
+# CONFIG_BRCM_SATA_75MHZ_PLL is not set
+# CONFIG_BRCM_SATA_SINGLE_PORT is not set
+CONFIG_BRCM_HAS_NOR=y
+CONFIG_BRCM_HAS_NAND_MINOR_2=y
+CONFIG_BRCM_HAS_NAND_MAJOR_6=y
+CONFIG_BRCMNAND_MAJOR_VERS=6
+CONFIG_BRCMNAND_MINOR_VERS=2
+CONFIG_BRCM_HAS_NAND=y
+CONFIG_BRCM_HAS_FLASH_DMA=y
+CONFIG_BRCM_HAS_SPI=y
+CONFIG_BRCM_HAS_BSPI_V4=y
+CONFIG_BRCM_BSPI_MAJOR_VERS=4
+CONFIG_BRCM_HAS_WKTMR=y
+CONFIG_BRCM_HAS_SDIO=y
+CONFIG_BRCM_HAS_SDIO_V1=y
+CONFIG_BRCM_HAS_EMMC=y
+CONFIG_BRCM_ZSCM_L2=y
+CONFIG_BRCM_CPU_DIV=y
+CONFIG_BRCM_HAS_XKS01=y
+CONFIG_BRCM_HAS_XI=y
+CONFIG_BRCM_HAS_DUALCORE=y
+CONFIG_BRCM_HAS_UPPER_MEMORY=y
+CONFIG_BRCM_UPPER_768MB=y
+CONFIG_BRCM_HAS_2GB_MEMC0=y
+CONFIG_BRCM_HAS_1GB_MEMC1=y
+CONFIG_BRCM_HAS_DIGITAL_DDR_PHY=y
+CONFIG_BRCM_PWR_HANDSHAKE=y
+CONFIG_BRCM_PWR_HANDSHAKE_V1=y
+CONFIG_BRCM_HAS_USB_CAPS=y
+CONFIG_BRCM_MIPS_DEFAULTS=y
+CONFIG_BCM7435=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_BOOT_RAW=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CEVT_R4K=y
+CONFIG_CFE=y
+# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
+# CONFIG_MIPS_MACHINE is not set
+# CONFIG_NO_IOPORT is not set
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_MIPS_L1_CACHE_SHIFT=7
+
+#
+# CPU selection
+#
+CONFIG_CPU_BMIPS5000=y
+CONFIG_CPU_BMIPS=y
+CONFIG_SYS_HAS_CPU_BMIPS5000=y
+CONFIG_WEAK_ORDERING=y
+CONFIG_CPU_MIPS32=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_BOARD_SCACHE=y
+CONFIG_MIPS_CPU_SCACHE=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_XKS01=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM=y
+CONFIG_HAVE_MEMORY_PRESENT=y
+CONFIG_SPARSEMEM_STATIC=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_COMPACTION is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_CLEANCACHE=y
+CONFIG_SMP=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_NR_CPUS=4
+CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_256 is not set
+CONFIG_HZ_1000=y
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=1000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_KEXEC=y
+CONFIG_SECCOMP=y
+CONFIG_CC_STACKPROTECTOR=y
+# CONFIG_USE_OF is not set
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_HAVE_IRQ_WORK=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION="-dm820"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_DEFAULT_HOSTNAME="dm820"
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_FHANDLE=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_IRQ_FORCED_THREADING=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_RCU_FAST_NO_HZ is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+# CONFIG_CGROUP_MEM_RES_CTLR is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_CFS_BANDWIDTH is not set
+# CONFIG_RT_GROUP_SCHED is not set
+# CONFIG_BLK_CGROUP is not set
+# CONFIG_CHECKPOINT_RESTORE is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_NET_NS=y
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EXPERT=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_PCI_QUIRKS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+# CONFIG_JUMP_LABEL is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+
+#
+# GCOV-based kernel profiling
+#
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+CONFIG_LDM_PARTITION=y
+# CONFIG_LDM_DEBUG is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_FREEZER=y
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+# CONFIG_PCI_PRI is not set
+# CONFIG_PCI_PASID is not set
+CONFIG_MMU=y
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+# CONFIG_RAPIDIO is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_TRAD_SIGNALS=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_SUSPEND is not set
+# CONFIG_HIBERNATION is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+# CONFIG_UNIX_DIAG is not set
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_ROUTE_CLASSID=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=y
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_ACCT=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_PROCFS=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_TIMEOUT=y
+# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
+CONFIG_NF_CT_PROTO_DCCP=m
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_BROADCAST=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NF_CT_NETLINK_TIMEOUT=m
+CONFIG_NETFILTER_TPROXY=m
+CONFIG_NETFILTER_XTABLES=m
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=m
+CONFIG_NETFILTER_XT_CONNMARK=m
+CONFIG_NETFILTER_XT_SET=m
+
+#
+# Xtables targets
+#
+# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+# CONFIG_NETFILTER_XT_TARGET_CT is not set
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HL=m
+# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
+CONFIG_NETFILTER_XT_TARGET_LED=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+
+#
+# Xtables matches
+#
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ECN=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_HL=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_MAX=256
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+# CONFIG_NF_NAT_SNMP_BASIC is not set
+CONFIG_NF_NAT_PROTO_DCCP=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_PROTO_UDPLITE=m
+CONFIG_NF_NAT_PROTO_SCTP=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV6=m
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_QUEUE=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+# CONFIG_BRIDGE_NF_EBTABLES is not set
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_L2TP=y
+# CONFIG_L2TP_V3 is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=m
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+CONFIG_NET_SCH_SFB=m
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+# CONFIG_NET_SCH_MQPRIO is not set
+# CONFIG_NET_SCH_CHOKE is not set
+# CONFIG_NET_SCH_QFQ is not set
+CONFIG_NET_SCH_PLUG=m
+
+#
+# Classification
+#
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_CLS_CGROUP is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+CONFIG_DNS_RESOLVER=y
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_OPENVSWITCH is not set
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+# CONFIG_NETPRIO_CGROUP is not set
+CONFIG_BQL=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=y
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIUART is not set
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+CONFIG_BT_ATH3K=m
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_PRIV=y
+CONFIG_CFG80211=y
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+# CONFIG_CFG80211_DEFAULT_PS is not set
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=y
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_RC_PID=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL_HT=y
+# CONFIG_MAC80211_RC_DEFAULT_PID is not set
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+CONFIG_CEPH_LIB=m
+# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
+# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
+# CONFIG_NFC is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_GENERIC_CPU_DEVICES is not set
+CONFIG_DMA_SHARED_BUFFER=y
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+# CONFIG_MTD_CHAR is not set
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+# CONFIG_MTD_SWAP is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOCG3 is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=2
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_NVME is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_UB=m
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+CONFIG_ATA_OVER_ETH=m
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_BLK_DEV_RBD is not set
+
+#
+# Misc devices
+#
+# CONFIG_SENSORS_LIS3LV02D is not set
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_INTEL_MID_PTI is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_BMP085 is not set
+# CONFIG_PCH_PHUB is not set
+# CONFIG_USB_SWITCH_FSA9480 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+CONFIG_EEPROM_93CX6=m
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_CB710_CORE is not set
+# CONFIG_IWMC3200TOP is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+
+#
+# Altera FPGA firmware download module
+#
+# CONFIG_ALTERA_STAPL is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+# CONFIG_SATA_PMP is not set
+
+#
+# Controllers with non-SFF native interface
+#
+# CONFIG_SATA_AHCI is not set
+CONFIG_SATA_AHCI_PLATFORM=y
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_ACARD_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+
+#
+# SFF controllers with custom DMA interface
+#
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SX4 is not set
+CONFIG_ATA_BMDMA=y
+
+#
+# SATA SFF controllers with BMDMA
+#
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+
+#
+# PATA SFF controllers with BMDMA
+#
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CS5536 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RDC is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+
+#
+# PIO-only SFF controllers
+#
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_RZ1000 is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_LEGACY is not set
+CONFIG_MD=y
+# CONFIG_BLK_DEV_MD is not set
+CONFIG_BLK_DEV_DM_BUILTIN=y
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_THIN_PROVISIONING is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_RAID is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+# CONFIG_DM_UEVENT is not set
+# CONFIG_DM_FLAKEY is not set
+# CONFIG_DM_VERITY is not set
+# CONFIG_TARGET_CORE is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_FIREWIRE_NOSY is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+# CONFIG_DUMMY is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_NET_FC is not set
+CONFIG_MII=y
+# CONFIG_NET_TEAM is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+CONFIG_TUN=y
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+
+#
+# CAIF transport drivers
+#
+CONFIG_ETHERNET=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+CONFIG_NET_VENDOR_BROADCOM=y
+# CONFIG_B44 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_CNIC is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2X is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_CALXEDA_XGMAC is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_DM9000 is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_HP is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_IP1000 is not set
+# CONFIG_JME is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+CONFIG_NET_VENDOR_MICROCHIP=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_ETHOC is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_SFC is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_TOSHIBA is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PHYLIB is not set
+# CONFIG_MICREL_KS8995MA is not set
+CONFIG_PPP=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOE=m
+# CONFIG_PPPOL2TP is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_TR is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_EEM=m
+CONFIG_USB_NET_CDC_NCM=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_NET_CX82310_ETH=m
+CONFIG_USB_NET_KALMIA=m
+CONFIG_USB_NET_QMI_WWAN=m
+CONFIG_USB_NET_INT51X1=m
+CONFIG_USB_IPHETH=m
+CONFIG_USB_SIERRA_NET=m
+CONFIG_USB_VL600=m
+CONFIG_WLAN=y
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_ATMEL is not set
+CONFIG_AT76C50X_USB=m
+# CONFIG_PRISM54 is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_RTL8180 is not set
+CONFIG_RTL8187=m
+CONFIG_RTL8187_LEDS=y
+# CONFIG_ADM8211 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_MWL8K is not set
+CONFIG_ATH_COMMON=m
+# CONFIG_ATH_DEBUG is not set
+CONFIG_ATH5K=m
+# CONFIG_ATH5K_DEBUG is not set
+CONFIG_ATH5K_PCI=y
+CONFIG_ATH9K_HW=m
+CONFIG_ATH9K_COMMON=m
+# CONFIG_ATH9K_BTCOEX_SUPPORT is not set
+CONFIG_ATH9K=m
+# CONFIG_ATH9K_PCI is not set
+# CONFIG_ATH9K_AHB is not set
+# CONFIG_ATH9K_DFS_CERTIFIED is not set
+# CONFIG_ATH9K_LEGACY_RATE_CONTROL is not set
+# CONFIG_ATH9K_HTC is not set
+CONFIG_CARL9170=m
+CONFIG_CARL9170_LEDS=y
+CONFIG_CARL9170_WPC=y
+# CONFIG_ATH6KL is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_BRCMFMAC is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_IWLWIFI is not set
+# CONFIG_IWL4965 is not set
+# CONFIG_IWL3945 is not set
+# CONFIG_IWM is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+CONFIG_P54_COMMON=m
+CONFIG_P54_USB=m
+# CONFIG_P54_PCI is not set
+# CONFIG_P54_SPI is not set
+CONFIG_P54_LEDS=y
+CONFIG_RT2X00=m
+# CONFIG_RT2400PCI is not set
+# CONFIG_RT2500PCI is not set
+# CONFIG_RT61PCI is not set
+# CONFIG_RT2800PCI is not set
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT35XX=y
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RT2800_LIB=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
+# CONFIG_RTL8192CE is not set
+# CONFIG_RTL8192SE is not set
+# CONFIG_RTL8192DE is not set
+CONFIG_RTL8192CU=m
+CONFIG_RTLWIFI=m
+# CONFIG_RTLWIFI_DEBUG is not set
+CONFIG_RTL8192C_COMMON=m
+# CONFIG_WL1251 is not set
+# CONFIG_WL12XX_MENU is not set
+CONFIG_ZD1211RW=m
+# CONFIG_ZD1211RW_DEBUG is not set
+# CONFIG_MWIFIEX is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_VMXNET3 is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=m
+CONFIG_INPUT_POLLDEV=m
+CONFIG_INPUT_SPARSEKMAP=m
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_BMA150 is not set
+# CONFIG_INPUT_MMA8450 is not set
+# CONFIG_INPUT_MPU3050 is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_KXTJ9 is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=m
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_CMA3000 is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+# CONFIG_DEVKMEM is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX3107 is not set
+# CONFIG_SERIAL_MFD_HSU is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_PCH_UART is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_TTY_PRINTK is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_RAMOOPS=m
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_MUX is not set
+# CONFIG_I2C_HELPER_AUTO is not set
+# CONFIG_I2C_SMBUS is not set
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE_PCI is not set
+# CONFIG_I2C_EG20T is not set
+# CONFIG_I2C_INTEL_MID is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+CONFIG_I2C_BRCMSTB=m
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_TOPCLIFF_PCH is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_HSI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+
+#
+# Enable Device Drivers -> PPS to see the PTP clock options.
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=m
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2781 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_SBS is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_LP8727 is not set
+# CONFIG_CHARGER_SMB347 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7314 is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_MCP3021 is not set
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_PMBUS is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SCH56XX_COMMON is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_SCH5636 is not set
+CONFIG_SENSORS_ADC128D818=y
+# CONFIG_SENSORS_ADS1015 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+CONFIG_SENSORS_INA2XX=y
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+
+#
+# Broadcom specific AMBA
+#
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS65217 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_TWL6040_CORE is not set
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_DA9052_SPI is not set
+# CONFIG_MFD_DA9052_I2C is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_S5M_CORE is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13XXX is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_TPS65090 is not set
+# CONFIG_MFD_RC5T583 is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+# CONFIG_MEDIA_CONTROLLER is not set
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_DVB_CORE=y
+CONFIG_DVB_NET=y
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+CONFIG_RC_CORE=y
+CONFIG_LIRC=y
+CONFIG_RC_MAP=m
+CONFIG_IR_NEC_DECODER=m
+CONFIG_IR_RC5_DECODER=m
+CONFIG_IR_RC6_DECODER=m
+CONFIG_IR_JVC_DECODER=m
+CONFIG_IR_SONY_DECODER=m
+CONFIG_IR_RC5_SZ_DECODER=m
+CONFIG_IR_SANYO_DECODER=m
+CONFIG_IR_MCE_KBD_DECODER=m
+CONFIG_IR_LIRC_CODEC=m
+CONFIG_RC_ATI_REMOTE=m
+CONFIG_IR_IMON=m
+CONFIG_IR_MCEUSB=m
+CONFIG_IR_REDRAT3=m
+CONFIG_IR_STREAMZAP=m
+CONFIG_RC_LOOPBACK=m
+# CONFIG_IR_GPIO_CIR is not set
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=m
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_TUNER_XC4000=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_MEDIA_TUNER_MXL5007T=m
+CONFIG_MEDIA_TUNER_MC44S803=m
+CONFIG_MEDIA_TUNER_MAX2165=m
+CONFIG_MEDIA_TUNER_TDA18218=m
+CONFIG_MEDIA_TUNER_TUA9001=m
+CONFIG_MEDIA_TUNER_TDA18212=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEOBUF_VMALLOC=m
+CONFIG_VIDEOBUF_DVB=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEOBUF2_CORE=m
+CONFIG_VIDEOBUF2_MEMOPS=m
+CONFIG_VIDEOBUF2_VMALLOC=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_VIDEO_IR_I2C=m
+
+#
+# Audio decoders, processors and mixers
+#
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_WM8775=m
+
+#
+# RDS decoders
+#
+
+#
+# Video decoders
+#
+CONFIG_VIDEO_SAA711X=m
+CONFIG_VIDEO_TVP5150=m
+
+#
+# Video and audio decoders
+#
+CONFIG_VIDEO_CX25840=m
+
+#
+# MPEG video encoders
+#
+CONFIG_VIDEO_CX2341X=m
+
+#
+# Video encoders
+#
+
+#
+# Camera sensor devices
+#
+CONFIG_VIDEO_MT9V011=m
+
+#
+# Flash devices
+#
+
+#
+# Video improvement chips
+#
+
+#
+# Miscelaneous helper chips
+#
+# CONFIG_VIDEO_VIVI is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+# CONFIG_USB_M5602 is not set
+# CONFIG_USB_STV06XX is not set
+# CONFIG_USB_GL860 is not set
+# CONFIG_USB_GSPCA_BENQ is not set
+# CONFIG_USB_GSPCA_CONEX is not set
+# CONFIG_USB_GSPCA_CPIA1 is not set
+# CONFIG_USB_GSPCA_ETOMS is not set
+# CONFIG_USB_GSPCA_FINEPIX is not set
+# CONFIG_USB_GSPCA_JEILINJ is not set
+# CONFIG_USB_GSPCA_JL2005BCD is not set
+# CONFIG_USB_GSPCA_KINECT is not set
+# CONFIG_USB_GSPCA_KONICA is not set
+# CONFIG_USB_GSPCA_MARS is not set
+# CONFIG_USB_GSPCA_MR97310A is not set
+# CONFIG_USB_GSPCA_NW80X is not set
+# CONFIG_USB_GSPCA_OV519 is not set
+# CONFIG_USB_GSPCA_OV534 is not set
+# CONFIG_USB_GSPCA_OV534_9 is not set
+# CONFIG_USB_GSPCA_PAC207 is not set
+# CONFIG_USB_GSPCA_PAC7302 is not set
+# CONFIG_USB_GSPCA_PAC7311 is not set
+# CONFIG_USB_GSPCA_SE401 is not set
+# CONFIG_USB_GSPCA_SN9C2028 is not set
+# CONFIG_USB_GSPCA_SN9C20X is not set
+# CONFIG_USB_GSPCA_SONIXB is not set
+# CONFIG_USB_GSPCA_SONIXJ is not set
+# CONFIG_USB_GSPCA_SPCA500 is not set
+# CONFIG_USB_GSPCA_SPCA501 is not set
+# CONFIG_USB_GSPCA_SPCA505 is not set
+# CONFIG_USB_GSPCA_SPCA506 is not set
+# CONFIG_USB_GSPCA_SPCA508 is not set
+# CONFIG_USB_GSPCA_SPCA561 is not set
+# CONFIG_USB_GSPCA_SPCA1528 is not set
+# CONFIG_USB_GSPCA_SQ905 is not set
+# CONFIG_USB_GSPCA_SQ905C is not set
+# CONFIG_USB_GSPCA_SQ930X is not set
+# CONFIG_USB_GSPCA_STK014 is not set
+# CONFIG_USB_GSPCA_STV0680 is not set
+# CONFIG_USB_GSPCA_SUNPLUS is not set
+# CONFIG_USB_GSPCA_T613 is not set
+# CONFIG_USB_GSPCA_TOPRO is not set
+# CONFIG_USB_GSPCA_TV8532 is not set
+# CONFIG_USB_GSPCA_VC032X is not set
+# CONFIG_USB_GSPCA_VICAM is not set
+# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
+# CONFIG_USB_GSPCA_ZC3XX is not set
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_PVRUSB2_DVB=y
+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
+CONFIG_VIDEO_HDPVR=m
+CONFIG_VIDEO_EM28XX=m
+CONFIG_VIDEO_EM28XX_ALSA=m
+CONFIG_VIDEO_EM28XX_DVB=m
+# CONFIG_VIDEO_EM28XX_RC is not set
+CONFIG_VIDEO_TLG2300=m
+CONFIG_VIDEO_CX231XX=m
+CONFIG_VIDEO_CX231XX_RC=y
+CONFIG_VIDEO_CX231XX_ALSA=m
+CONFIG_VIDEO_CX231XX_DVB=m
+CONFIG_VIDEO_TM6000=m
+CONFIG_VIDEO_TM6000_ALSA=m
+CONFIG_VIDEO_TM6000_DVB=m
+CONFIG_VIDEO_USBVISION=m
+CONFIG_USB_ET61X251=m
+CONFIG_USB_SN9C102=m
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+CONFIG_USB_PWC_INPUT_EVDEV=y
+# CONFIG_VIDEO_CPIA2 is not set
+CONFIG_USB_ZR364XX=m
+CONFIG_USB_STKWEBCAM=m
+CONFIG_USB_S2255=m
+# CONFIG_V4L_PCI_DRIVERS is not set
+# CONFIG_V4L_PLATFORM_DRIVERS is not set
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+# CONFIG_VIDEO_MEM2MEM_TESTDEV is not set
+# CONFIG_RADIO_ADAPTERS is not set
+CONFIG_DVB_MAX_ADAPTERS=8
+CONFIG_DVB_DYNAMIC_MINORS=y
+CONFIG_DVB_CAPTURE_DRIVERS=y
+
+#
+# Supported SAA7146 based PCI Adapters
+#
+CONFIG_TTPCI_EEPROM=m
+# CONFIG_DVB_AV7110 is not set
+# CONFIG_DVB_BUDGET_CORE is not set
+
+#
+# Supported USB Adapters
+#
+CONFIG_DVB_USB=m
+# CONFIG_DVB_USB_DEBUG is not set
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_DIBUSB_MB=m
+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+CONFIG_DVB_USB_PCTV452E=m
+CONFIG_DVB_USB_DW2102=m
+CONFIG_DVB_USB_CINERGY_T2=m
+CONFIG_DVB_USB_ANYSEE=m
+CONFIG_DVB_USB_DTV5100=m
+CONFIG_DVB_USB_AF9015=m
+CONFIG_DVB_USB_A867=m
+CONFIG_DVB_USB_AF9035=m
+CONFIG_DVB_USB_CE6230=m
+CONFIG_DVB_USB_FRIIO=m
+CONFIG_DVB_USB_EC168=m
+CONFIG_DVB_USB_AZ6007=m
+CONFIG_DVB_USB_AZ6027=m
+CONFIG_DVB_USB_LME2510=m
+CONFIG_DVB_USB_TECHNISAT_USB2=m
+CONFIG_DVB_USB_IT913X=m
+CONFIG_DVB_USB_MXL111SF=m
+CONFIG_DVB_USB_RTL28XXU=m
+CONFIG_DVB_TTUSB_BUDGET=m
+CONFIG_DVB_TTUSB_DEC=m
+CONFIG_SMS_SIANO_MDTV=m
+
+#
+# Siano module components
+#
+CONFIG_SMS_USB_DRV=m
+# CONFIG_SMS_SDIO_DRV is not set
+
+#
+# Supported FlexCopII (B2C2) Adapters
+#
+CONFIG_DVB_B2C2_FLEXCOP=m
+# CONFIG_DVB_B2C2_FLEXCOP_PCI is not set
+CONFIG_DVB_B2C2_FLEXCOP_USB=m
+# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set
+
+#
+# Supported BT878 Adapters
+#
+
+#
+# Supported Pluto2 Adapters
+#
+# CONFIG_DVB_PLUTO2 is not set
+
+#
+# Supported SDMC DM1105 Adapters
+#
+# CONFIG_DVB_DM1105 is not set
+
+#
+# Supported Earthsoft PT1 Adapters
+#
+# CONFIG_DVB_PT1 is not set
+
+#
+# Supported Mantis Adapters
+#
+# CONFIG_MANTIS_CORE is not set
+
+#
+# Supported nGene Adapters
+#
+# CONFIG_DVB_NGENE is not set
+
+#
+# Supported ddbridge ('Octopus') Adapters
+#
+# CONFIG_DVB_DDBRIDGE is not set
+
+#
+# Supported DVB Frontends
+#
+CONFIG_DVB_FE_CUSTOMISE=y
+
+#
+# Customise DVB Frontends
+#
+
+#
+# Multistandard (satellite) frontends
+#
+CONFIG_DVB_STB0899=m
+CONFIG_DVB_STB6100=m
+CONFIG_DVB_STV090x=m
+CONFIG_DVB_STV6110x=m
+
+#
+# Multistandard (cable + terrestrial) frontends
+#
+CONFIG_DVB_DRXK=m
+CONFIG_DVB_TDA18271C2DD=m
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_ZL10036=m
+CONFIG_DVB_ZL10039=m
+CONFIG_DVB_S5H1420=m
+CONFIG_DVB_STV0288=m
+CONFIG_DVB_STB6000=m
+CONFIG_DVB_STV0299=y
+CONFIG_DVB_STV6110=m
+CONFIG_DVB_STV0900=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_TDA8261=m
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_TUNER_CX24113=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TUA6100=m
+CONFIG_DVB_CX24116=m
+CONFIG_DVB_SI21XX=m
+CONFIG_DVB_DS3000=m
+CONFIG_DVB_MB86A16=m
+CONFIG_DVB_TDA10071=m
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_SP8870=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+CONFIG_DVB_S5H1432=m
+CONFIG_DVB_DRXD=m
+CONFIG_DVB_L64781=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_DIB9000=m
+CONFIG_DVB_TDA10048=m
+CONFIG_DVB_AF9013=m
+CONFIG_DVB_AF9033=m
+CONFIG_DVB_EC100=m
+CONFIG_DVB_HD29L2=m
+CONFIG_DVB_STV0367=m
+CONFIG_DVB_CXD2820R=m
+CONFIG_DVB_RTL2830=m
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_STV0297=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_NXT200X=m
+CONFIG_DVB_OR51211=m
+CONFIG_DVB_OR51132=m
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_LGDT3305=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_S5H1411=m
+
+#
+# ISDB-T (terrestrial) frontends
+#
+CONFIG_DVB_S921=m
+CONFIG_DVB_DIB8000=m
+CONFIG_DVB_MB86A20S=m
+
+#
+# Digital terrestrial only tuners/PLL
+#
+CONFIG_DVB_PLL=m
+CONFIG_DVB_TUNER_DIB0070=m
+CONFIG_DVB_TUNER_DIB0090=m
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_LNBP21=m
+CONFIG_DVB_LNBP22=m
+CONFIG_DVB_ISL6405=m
+CONFIG_DVB_ISL6421=m
+CONFIG_DVB_ISL6423=m
+CONFIG_DVB_A8293=m
+CONFIG_DVB_LGS8GL5=m
+CONFIG_DVB_LGS8GXX=m
+CONFIG_DVB_ATBM8830=m
+CONFIG_DVB_TDA665x=m
+CONFIG_DVB_IX2505V=m
+CONFIG_DVB_IT913X_FE=m
+CONFIG_DVB_M88RS2000=m
+
+#
+# Tools to develop new frontends
+#
+CONFIG_DVB_DUMMY_FE=m
+
+#
+# Graphics support
+#
+# CONFIG_VGA_ARB is not set
+# CONFIG_DRM is not set
+# CONFIG_STUB_POULSBO is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_WMT_GE_ROPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_I740 is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SMSCUFX is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_EXYNOS_VIDEO is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=m
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_HRTIMER is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_PCI is not set
+CONFIG_SND_SPI=y
+# CONFIG_SND_MIPS is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+# CONFIG_SND_USB_UA101 is not set
+CONFIG_SND_USB_CAIAQ=m
+# CONFIG_SND_USB_CAIAQ_INPUT is not set
+# CONFIG_SND_USB_6FIRE is not set
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# USB HID Boot Protocol drivers
+#
+CONFIG_USB_KBD=m
+CONFIG_USB_MOUSE=m
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_ACRUX is not set
+CONFIG_HID_APPLE=m
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_PRODIKEYS is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EMS_FF is not set
+# CONFIG_HID_ELECOM is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_HOLTEK is not set
+# CONFIG_HID_KEYTOUCH is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LCPOWER is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_PRIMAX is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_SAITEK is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SPEEDLINK is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TIVO is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_WACOM is not set
+CONFIG_HID_WIIMOTE=m
+CONFIG_HID_WIIMOTE_EXT=y
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB_ARCH_HAS_XHCI=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_XHCI_HCD=y
+# CONFIG_USB_XHCI_HCD_DEBUGGING is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_REALTEK=m
+CONFIG_REALTEK_AUTOPM=y
+CONFIG_USB_STORAGE_DATAFAB=m
+CONFIG_USB_STORAGE_FREECOM=m
+CONFIG_USB_STORAGE_ISD200=m
+CONFIG_USB_STORAGE_USBAT=m
+CONFIG_USB_STORAGE_SDDR09=m
+CONFIG_USB_STORAGE_SDDR55=m
+CONFIG_USB_STORAGE_JUMPSHOT=m
+CONFIG_USB_STORAGE_ALAUDA=m
+CONFIG_USB_STORAGE_ONETOUCH=m
+CONFIG_USB_STORAGE_KARMA=m
+CONFIG_USB_STORAGE_CYPRESS_ATACB=m
+CONFIG_USB_STORAGE_ENE_UB6250=m
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_FUNSOFT=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_F81232=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+# CONFIG_USB_SERIAL_METRO is not set
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MOTOROLA=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_QCAUX=m
+CONFIG_USB_SERIAL_QUALCOMM=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_HP4X=m
+CONFIG_USB_SERIAL_SAFE=m
+# CONFIG_USB_SERIAL_SAFE_PADDED is not set
+CONFIG_USB_SERIAL_SIEMENS_MPI=m
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_SYMBOL=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_WWAN=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_OPTICON=m
+CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
+CONFIG_USB_SERIAL_ZIO=m
+CONFIG_USB_SERIAL_SSU100=m
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_UWB is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+# CONFIG_MMC_CLKGATE is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_TIFM_SD is not set
+# CONFIG_MMC_CB710 is not set
+# CONFIG_MMC_VIA_SDMMC is not set
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP5523 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_PCA9633 is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_TCA6507 is not set
+# CONFIG_LEDS_OT200 is not set
+CONFIG_LEDS_TRIGGERS=y
+
+#
+# LED Triggers
+#
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=m
+# CONFIG_UIO_CIF is not set
+CONFIG_UIO_PDRV=m
+CONFIG_UIO_PDRV_GENIRQ=m
+# CONFIG_UIO_AEC is not set
+# CONFIG_UIO_SERCOS3 is not set
+# CONFIG_UIO_PCI_GENERIC is not set
+# CONFIG_UIO_NETX is not set
+
+#
+# Virtio drivers
+#
+# CONFIG_VIRTIO_PCI is not set
+# CONFIG_VIRTIO_BALLOON is not set
+# CONFIG_VIRTIO_MMIO is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+CONFIG_STAGING=y
+# CONFIG_ET131X is not set
+CONFIG_USBIP_CORE=m
+CONFIG_USBIP_VHCI_HCD=m
+CONFIG_USBIP_HOST=m
+# CONFIG_USBIP_DEBUG is not set
+# CONFIG_W35UND is not set
+CONFIG_PRISM2_USB=m
+# CONFIG_ECHO is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_R8187SE is not set
+CONFIG_RTL8192U=m
+CONFIG_RTLLIB=m
+CONFIG_RTLLIB_CRYPTO_CCMP=m
+CONFIG_RTLLIB_CRYPTO_TKIP=m
+CONFIG_RTLLIB_CRYPTO_WEP=m
+# CONFIG_RTL8192E is not set
+CONFIG_R8712U=m
+# CONFIG_RTS_PSTOR is not set
+CONFIG_RTS5139=m
+# CONFIG_RTS5139_DEBUG is not set
+CONFIG_TRANZPORT=m
+# CONFIG_IDE_PHISON is not set
+CONFIG_LINE6_USB=m
+# CONFIG_LINE6_USB_DEBUG is not set
+# CONFIG_LINE6_USB_DUMP_CTRL is not set
+# CONFIG_LINE6_USB_DUMP_MIDI is not set
+# CONFIG_LINE6_USB_DUMP_PCM is not set
+# CONFIG_LINE6_USB_RAW is not set
+# CONFIG_LINE6_USB_IMPULSE_RESPONSE is not set
+CONFIG_USB_SERIAL_QUATECH2=m
+CONFIG_USB_SERIAL_QUATECH_USB2=m
+# CONFIG_VT6655 is not set
+# CONFIG_VT6656 is not set
+# CONFIG_VME_BUS is not set
+# CONFIG_DX_SEP is not set
+# CONFIG_IIO is not set
+# CONFIG_FB_SM7XX is not set
+# CONFIG_CRYSTALHD is not set
+# CONFIG_FB_XGI is not set
+CONFIG_USB_ENESTORAGE=m
+CONFIG_BCM_WIMAX=m
+# CONFIG_FT1000 is not set
+
+#
+# Speakup console speech
+#
+# CONFIG_SPEAKUP is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
+CONFIG_STAGING_MEDIA=y
+CONFIG_DVB_AS102=m
+CONFIG_DVB_CXD2099=m
+# CONFIG_VIDEO_DT3155 is not set
+CONFIG_EASYCAP=m
+# CONFIG_EASYCAP_DEBUG is not set
+# CONFIG_VIDEO_GO7007 is not set
+# CONFIG_SOLO6X10 is not set
+CONFIG_LIRC_STAGING=y
+# CONFIG_LIRC_BT829 is not set
+CONFIG_LIRC_IGORPLUGUSB=m
+CONFIG_LIRC_IMON=m
+CONFIG_LIRC_SASEM=m
+CONFIG_LIRC_SERIAL=m
+CONFIG_LIRC_SERIAL_TRANSMITTER=y
+# CONFIG_LIRC_SIR is not set
+CONFIG_LIRC_TTUSBIR=m
+# CONFIG_LIRC_ZILOG is not set
+
+#
+# Android
+#
+CONFIG_ANDROID=y
+# CONFIG_ANDROID_BINDER_IPC is not set
+# CONFIG_ASHMEM is not set
+# CONFIG_ANDROID_LOGGER is not set
+# CONFIG_ANDROID_RAM_CONSOLE is not set
+# CONFIG_ANDROID_TIMED_OUTPUT is not set
+# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set
+# CONFIG_ANDROID_SWITCH is not set
+CONFIG_ION=y
+# CONFIG_ION_TEST is not set
+# CONFIG_ION_DUMMY is not set
+# CONFIG_PHONE is not set
+# CONFIG_USB_WPAN_HCD is not set
+
+#
+# Hardware Spinlock drivers
+#
+CONFIG_IOMMU_SUPPORT=y
+
+#
+# Remoteproc drivers (EXPERIMENTAL)
+#
+
+#
+# Rpmsg drivers (EXPERIMENTAL)
+#
+# CONFIG_VIRT_DRIVERS is not set
+# CONFIG_PM_DEVFREQ is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+CONFIG_JBD2=y
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_REISERFS_FS_XATTR is not set
+CONFIG_JFS_FS=m
+# CONFIG_JFS_POSIX_ACL is not set
+# CONFIG_JFS_SECURITY is not set
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_STATISTICS is not set
+CONFIG_XFS_FS=y
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_BTRFS_FS=m
+# CONFIG_BTRFS_FS_POSIX_ACL is not set
+# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_FANOTIFY=y
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
+CONFIG_GENERIC_ACL=y
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+# CONFIG_NTFS_RW is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+CONFIG_HFS_FS=m
+CONFIG_HFSPLUS_FS=m
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_LOGFS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX6FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=m
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+CONFIG_NFSD_V4=y
+# CONFIG_NFSD_FAULT_INJECTION is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=m
+# CONFIG_SUNRPC_DEBUG is not set
+CONFIG_CEPH_FS=m
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_DFS_UPCALL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=y
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_STRIP_ASM_SYMS=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_LOCKUP_DETECTOR=y
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RCU_CPU_STALL_INFO=y
+# CONFIG_RCU_TRACE is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_TEST_KSTRTOX is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="bmem=384M@640M memc1=768M console=ttyS0,1000000 root=/dev/mmcblk0p1 rootwait rootfstype=ext4"
+# CONFIG_CMDLINE_EXTEND is not set
+# CONFIG_CMDLINE_OVERRIDE is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_RUNTIME_DEBUG is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+CONFIG_ENCRYPTED_KEYS=m
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+CONFIG_SECURITYFS=y
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=m
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_USER=m
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_SEQIV=m
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=m
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_VMAC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_GHASH=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_BLOWFISH_COMMON=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SALSA20=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_ZLIB=m
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_USER_API=m
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_IO=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=m
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=m
+CONFIG_CRC8=m
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_ARM is not set
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+# CONFIG_XZ_DEC_SPARC is not set
+# CONFIG_XZ_DEC_BCJ is not set
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_AVERAGE=y
+# CONFIG_CORDIC is not set
diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c
index ea57f39..56ebc7f 100644
--- a/arch/mips/dec/time.c
+++ b/arch/mips/dec/time.c
@@ -126,12 +126,13 @@ int rtc_mips_set_mmss(unsigned long nowtime)
 void __init plat_time_init(void)
 {
 	u32 start, end;
-	int i = HZ / 10;
+	int i = HZ / 8;
 
 	/* Set up the rate of periodic DS1287 interrupts. */
 	ds1287_set_base_clock(HZ);
 
 	if (cpu_has_counter) {
+		ds1287_timer_state();
 		while (!ds1287_timer_state())
 			;
 
@@ -143,7 +144,7 @@ void __init plat_time_init(void)
 
 		end = read_c0_count();
 
-		mips_hpt_frequency = (end - start) * 10;
+		mips_hpt_frequency = (end - start) * 8;
 		printk(KERN_INFO "MIPS counter frequency %dHz\n",
 			mips_hpt_frequency);
 	} else if (IOASIC)
diff --git a/arch/mips/fw/arc/misc.c b/arch/mips/fw/arc/misc.c
index 7cf80ca..f9f5307 100644
--- a/arch/mips/fw/arc/misc.c
+++ b/arch/mips/fw/arc/misc.c
@@ -11,6 +11,7 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/irqflags.h>
 
 #include <asm/bcache.h>
 
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index 569f80a..f109eeb 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -96,13 +96,21 @@
  */
 #define KUSEG			0x00000000
 #define KSEG0			0x80000000
+#if defined(CONFIG_BRCM_UPPER_768MB)
+#define KSEG1			KSEG0
+#else
 #define KSEG1			0xa0000000
+#endif
 #define KSEG2			0xc0000000
 #define KSEG3			0xe0000000
 
 #define CKUSEG			0x00000000
 #define CKSEG0			0x80000000
+#if defined(CONFIG_BRCM_UPPER_768MB)
+#define CKSEG1			CKSEG0
+#else
 #define CKSEG1			0xa0000000
+#endif
 #define CKSEG2			0xc0000000
 #define CKSEG3			0xe0000000
 
diff --git a/arch/mips/include/asm/asmmacro-32.h b/arch/mips/include/asm/asmmacro-32.h
index 2413afe..e494a0d 100644
--- a/arch/mips/include/asm/asmmacro-32.h
+++ b/arch/mips/include/asm/asmmacro-32.h
@@ -13,6 +13,8 @@
 #include <asm/mipsregs.h>
 
 	.macro	fpu_save_double thread status tmp1=t0
+	.set	push
+	SET_HARDFLOAT
 	cfc1	\tmp1,  fcr31
 	sdc1	$f0,  THREAD_FPR0(\thread)
 	sdc1	$f2,  THREAD_FPR2(\thread)
@@ -31,9 +33,12 @@
 	sdc1	$f28, THREAD_FPR28(\thread)
 	sdc1	$f30, THREAD_FPR30(\thread)
 	sw	\tmp1, THREAD_FCR31(\thread)
+	.set	pop
 	.endm
 
 	.macro	fpu_save_single thread tmp=t0
+	.set	push
+	SET_HARDFLOAT
 	cfc1	\tmp,  fcr31
 	swc1	$f0,  THREAD_FPR0(\thread)
 	swc1	$f1,  THREAD_FPR1(\thread)
@@ -68,9 +73,12 @@
 	swc1	$f30, THREAD_FPR30(\thread)
 	swc1	$f31, THREAD_FPR31(\thread)
 	sw	\tmp, THREAD_FCR31(\thread)
+	.set	pop
 	.endm
 
 	.macro	fpu_restore_double thread status tmp=t0
+	.set	push
+	SET_HARDFLOAT
 	lw	\tmp, THREAD_FCR31(\thread)
 	ldc1	$f0,  THREAD_FPR0(\thread)
 	ldc1	$f2,  THREAD_FPR2(\thread)
@@ -89,9 +97,12 @@
 	ldc1	$f28, THREAD_FPR28(\thread)
 	ldc1	$f30, THREAD_FPR30(\thread)
 	ctc1	\tmp, fcr31
+	.set	pop
 	.endm
 
 	.macro	fpu_restore_single thread tmp=t0
+	.set	push
+	SET_HARDFLOAT
 	lw	\tmp, THREAD_FCR31(\thread)
 	lwc1	$f0,  THREAD_FPR0(\thread)
 	lwc1	$f1,  THREAD_FPR1(\thread)
@@ -126,6 +137,7 @@
 	lwc1	$f30, THREAD_FPR30(\thread)
 	lwc1	$f31, THREAD_FPR31(\thread)
 	ctc1	\tmp, fcr31
+	.set	pop
 	.endm
 
 	.macro	cpu_save_nonscratch thread
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 2e1ad4c..31e9d34 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -14,7 +14,6 @@
 #endif
 
 #include <linux/compiler.h>
-#include <linux/irqflags.h>
 #include <linux/types.h>
 #include <asm/barrier.h>
 #include <asm/bug.h>
@@ -45,6 +44,24 @@
 #define smp_mb__before_clear_bit()	smp_mb__before_llsc()
 #define smp_mb__after_clear_bit()	smp_llsc_mb()
 
+
+/*
+ * These are the "slower" versions of the functions and are in bitops.c.
+ * These functions call raw_local_irq_{save,restore}().
+ */
+void __mips_set_bit(unsigned long nr, volatile unsigned long *addr);
+void __mips_clear_bit(unsigned long nr, volatile unsigned long *addr);
+void __mips_change_bit(unsigned long nr, volatile unsigned long *addr);
+int __mips_test_and_set_bit(unsigned long nr,
+			    volatile unsigned long *addr);
+int __mips_test_and_set_bit_lock(unsigned long nr,
+				 volatile unsigned long *addr);
+int __mips_test_and_clear_bit(unsigned long nr,
+			      volatile unsigned long *addr);
+int __mips_test_and_change_bit(unsigned long nr,
+			       volatile unsigned long *addr);
+
+
 /*
  * set_bit - Atomically set a bit in memory
  * @nr: the bit to set
@@ -58,7 +75,7 @@
 static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
 {
 	unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-	unsigned short bit = nr & SZLONG_MASK;
+	int bit = nr & SZLONG_MASK;
 	unsigned long temp;
 
 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
@@ -93,17 +110,8 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
 			: "=&r" (temp), "+m" (*m)
 			: "ir" (1UL << bit));
 		} while (unlikely(!temp));
-	} else {
-		volatile unsigned long *a = addr;
-		unsigned long mask;
-		unsigned long flags;
-
-		a += nr >> SZLONG_LOG;
-		mask = 1UL << bit;
-		raw_local_irq_save(flags);
-		*a |= mask;
-		raw_local_irq_restore(flags);
-	}
+	} else
+		__mips_set_bit(nr, addr);
 }
 
 /*
@@ -119,7 +127,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
 static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
 {
 	unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-	unsigned short bit = nr & SZLONG_MASK;
+	int bit = nr & SZLONG_MASK;
 	unsigned long temp;
 
 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
@@ -154,17 +162,8 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
 			: "=&r" (temp), "+m" (*m)
 			: "ir" (~(1UL << bit)));
 		} while (unlikely(!temp));
-	} else {
-		volatile unsigned long *a = addr;
-		unsigned long mask;
-		unsigned long flags;
-
-		a += nr >> SZLONG_LOG;
-		mask = 1UL << bit;
-		raw_local_irq_save(flags);
-		*a &= ~mask;
-		raw_local_irq_restore(flags);
-	}
+	} else
+		__mips_clear_bit(nr, addr);
 }
 
 /*
@@ -192,7 +191,7 @@ static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *ad
  */
 static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
 {
-	unsigned short bit = nr & SZLONG_MASK;
+	int bit = nr & SZLONG_MASK;
 
 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
@@ -221,17 +220,8 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
 			: "=&r" (temp), "+m" (*m)
 			: "ir" (1UL << bit));
 		} while (unlikely(!temp));
-	} else {
-		volatile unsigned long *a = addr;
-		unsigned long mask;
-		unsigned long flags;
-
-		a += nr >> SZLONG_LOG;
-		mask = 1UL << bit;
-		raw_local_irq_save(flags);
-		*a ^= mask;
-		raw_local_irq_restore(flags);
-	}
+	} else
+		__mips_change_bit(nr, addr);
 }
 
 /*
@@ -245,7 +235,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
 static inline int test_and_set_bit(unsigned long nr,
 	volatile unsigned long *addr)
 {
-	unsigned short bit = nr & SZLONG_MASK;
+	int bit = nr & SZLONG_MASK;
 	unsigned long res;
 
 	smp_mb__before_llsc();
@@ -282,18 +272,8 @@ static inline int test_and_set_bit(unsigned long nr,
 		} while (unlikely(!res));
 
 		res = temp & (1UL << bit);
-	} else {
-		volatile unsigned long *a = addr;
-		unsigned long mask;
-		unsigned long flags;
-
-		a += nr >> SZLONG_LOG;
-		mask = 1UL << bit;
-		raw_local_irq_save(flags);
-		res = (mask & *a);
-		*a |= mask;
-		raw_local_irq_restore(flags);
-	}
+	} else
+		res = __mips_test_and_set_bit(nr, addr);
 
 	smp_llsc_mb();
 
@@ -311,7 +291,7 @@ static inline int test_and_set_bit(unsigned long nr,
 static inline int test_and_set_bit_lock(unsigned long nr,
 	volatile unsigned long *addr)
 {
-	unsigned short bit = nr & SZLONG_MASK;
+	int bit = nr & SZLONG_MASK;
 	unsigned long res;
 
 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
@@ -346,18 +326,8 @@ static inline int test_and_set_bit_lock(unsigned long nr,
 		} while (unlikely(!res));
 
 		res = temp & (1UL << bit);
-	} else {
-		volatile unsigned long *a = addr;
-		unsigned long mask;
-		unsigned long flags;
-
-		a += nr >> SZLONG_LOG;
-		mask = 1UL << bit;
-		raw_local_irq_save(flags);
-		res = (mask & *a);
-		*a |= mask;
-		raw_local_irq_restore(flags);
-	}
+	} else
+		res = __mips_test_and_set_bit_lock(nr, addr);
 
 	smp_llsc_mb();
 
@@ -374,7 +344,7 @@ static inline int test_and_set_bit_lock(unsigned long nr,
 static inline int test_and_clear_bit(unsigned long nr,
 	volatile unsigned long *addr)
 {
-	unsigned short bit = nr & SZLONG_MASK;
+	int bit = nr & SZLONG_MASK;
 	unsigned long res;
 
 	smp_mb__before_llsc();
@@ -429,18 +399,8 @@ static inline int test_and_clear_bit(unsigned long nr,
 		} while (unlikely(!res));
 
 		res = temp & (1UL << bit);
-	} else {
-		volatile unsigned long *a = addr;
-		unsigned long mask;
-		unsigned long flags;
-
-		a += nr >> SZLONG_LOG;
-		mask = 1UL << bit;
-		raw_local_irq_save(flags);
-		res = (mask & *a);
-		*a &= ~mask;
-		raw_local_irq_restore(flags);
-	}
+	} else
+		res = __mips_test_and_clear_bit(nr, addr);
 
 	smp_llsc_mb();
 
@@ -458,7 +418,7 @@ static inline int test_and_clear_bit(unsigned long nr,
 static inline int test_and_change_bit(unsigned long nr,
 	volatile unsigned long *addr)
 {
-	unsigned short bit = nr & SZLONG_MASK;
+	int bit = nr & SZLONG_MASK;
 	unsigned long res;
 
 	smp_mb__before_llsc();
@@ -495,18 +455,8 @@ static inline int test_and_change_bit(unsigned long nr,
 		} while (unlikely(!res));
 
 		res = temp & (1UL << bit);
-	} else {
-		volatile unsigned long *a = addr;
-		unsigned long mask;
-		unsigned long flags;
-
-		a += nr >> SZLONG_LOG;
-		mask = 1UL << bit;
-		raw_local_irq_save(flags);
-		res = (mask & *a);
-		*a ^= mask;
-		raw_local_irq_restore(flags);
-	}
+	} else
+		res = __mips_test_and_change_bit(nr, addr);
 
 	smp_llsc_mb();
 
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
index 552a65a..72b34b8 100644
--- a/arch/mips/include/asm/bmips.h
+++ b/arch/mips/include/asm/bmips.h
@@ -99,6 +99,7 @@ static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
 		"_ssnop\n"
 		"_ssnop\n"
 		"_ssnop\n"
+		".set pop\n"
 		: /* no outputs */
 		: "r" (data),
 		  "i" (Index_Store_Tag_S), "r" (ZSCM_REG_BASE + offset)
diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h
index b77df03..1f9b711 100644
--- a/arch/mips/include/asm/compat.h
+++ b/arch/mips/include/asm/compat.h
@@ -223,7 +223,7 @@ struct compat_shmid64_ds {
 
 static inline int is_compat_task(void)
 {
-	return test_thread_flag(TIF_32BIT);
+	return test_thread_flag(TIF_32BIT_ADDR);
 }
 
 #endif /* _ASM_COMPAT_H */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index ca400f7..55db8e1 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -252,4 +252,8 @@
 #define cpu_hwrena_impl_bits		0
 #endif
 
+#ifndef cpu_has_perf_cntr_intr_bit
+#define cpu_has_perf_cntr_intr_bit	(cpu_data[0].options & MIPS_CPU_PCI)
+#endif
+
 #endif /* __ASM_CPU_FEATURES_H */
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index c454550..6766179 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -39,14 +39,14 @@ struct cache_desc {
 #define MIPS_CACHE_PINDEX	0x00000020	/* Physically indexed cache */
 
 struct cpuinfo_mips {
-	unsigned int		udelay_val;
-	unsigned int		asid_cache;
+	unsigned long		asid_cache;
 
 	/*
 	 * Capability and feature descriptor structure for MIPS CPU
 	 */
 	unsigned long		options;
 	unsigned long		ases;
+	unsigned int		udelay_val;
 	unsigned int		processor_id;
 	unsigned int		fpu_id;
 	unsigned int		cputype;
@@ -89,6 +89,6 @@ extern void cpu_probe(void);
 extern void cpu_report(void);
 
 extern const char *__cpu_name[];
-#define cpu_name_string()	__cpu_name[smp_processor_id()]
+#define cpu_name_string()	__cpu_name[raw_smp_processor_id()]
 
 #endif /* __ASM_CPU_INFO_H */
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index f9fa2a4..638749a 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -119,6 +119,7 @@
 #define PRID_IMP_BMIPS3300_BUG	0x0000
 #define PRID_IMP_BMIPS43XX	0xa000
 #define PRID_IMP_BMIPS5000	0x5a00
+#define PRID_IMP_BMIPS5200	0x5b00
 
 #define PRID_REV_BMIPS4380_LO	0x0040
 #define PRID_REV_BMIPS4380_HI	0x006f
@@ -317,6 +318,7 @@ enum cpu_type_enum {
 #define MIPS_CPU_VINT		0x00080000 /* CPU supports MIPSR2 vectored interrupts */
 #define MIPS_CPU_VEIC		0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
 #define MIPS_CPU_ULRI		0x00200000 /* CPU has ULRI feature */
+#define MIPS_CPU_PCI		0x00400000 /* CPU has Perf Ctr Int indicator */
 
 /*
  * CPU ASE encodings
diff --git a/arch/mips/include/asm/dsp.h b/arch/mips/include/asm/dsp.h
index e9bfc08..7bfad05 100644
--- a/arch/mips/include/asm/dsp.h
+++ b/arch/mips/include/asm/dsp.h
@@ -16,7 +16,7 @@
 #include <asm/mipsregs.h>
 
 #define DSP_DEFAULT	0x00000000
-#define DSP_MASK	0x3ff
+#define DSP_MASK	0x3f
 
 #define __enable_dsp_hazard()						\
 do {									\
diff --git a/arch/mips/include/asm/fpregdef.h b/arch/mips/include/asm/fpregdef.h
index 2b5fddc..4b002bf 100644
--- a/arch/mips/include/asm/fpregdef.h
+++ b/arch/mips/include/asm/fpregdef.h
@@ -14,6 +14,20 @@
 
 #include <asm/sgidefs.h>
 
+/*
+ * starting with binutils 2.24.51.20140729, MIPS binutils warn about mixing
+ * hardfloat and softfloat object files.  The kernel build uses soft-float by
+ * default, so we also need to pass -msoft-float along to GAS if it supports it.
+ * But this in turn causes assembler errors in files which access hardfloat
+ * registers.  We detect if GAS supports "-msoft-float" in the Makefile and
+ * explicitly put ".set hardfloat" where floating point registers are touched.
+ */
+#ifdef GAS_HAS_SET_HARDFLOAT
+#define SET_HARDFLOAT .set hardfloat
+#else
+#define SET_HARDFLOAT
+#endif
+
 #if _MIPS_SIM == _MIPS_SIM_ABI32
 
 /*
diff --git a/arch/mips/include/asm/fw/arc/hinv.h b/arch/mips/include/asm/fw/arc/hinv.h
index e6ff4ad..b7244a0 100644
--- a/arch/mips/include/asm/fw/arc/hinv.h
+++ b/arch/mips/include/asm/fw/arc/hinv.h
@@ -119,7 +119,7 @@ union key_u {
 #define SGI_ARCS_REV	10			/* rev .10, 3/04/92 */
 #endif
 
-typedef struct component {
+typedef struct {
 	CONFIGCLASS	Class;
 	CONFIGTYPE	Type;
 	IDENTIFIERFLAG	Flags;
@@ -140,7 +140,7 @@ struct cfgdata {
 };
 
 /* System ID */
-typedef struct systemid {
+typedef struct {
 	CHAR VendorId[8];
 	CHAR ProductId[8];
 } SYSTEMID;
@@ -166,7 +166,7 @@ typedef enum memorytype {
 #endif	/* _NT_PROM */
 } MEMORYTYPE;
 
-typedef struct memorydescriptor {
+typedef struct {
 	MEMORYTYPE	Type;
 	LONG		BasePage;
 	LONG		PageCount;
diff --git a/arch/mips/include/asm/hugetlb.h b/arch/mips/include/asm/hugetlb.h
index 58d3688..68670b1 100644
--- a/arch/mips/include/asm/hugetlb.h
+++ b/arch/mips/include/asm/hugetlb.h
@@ -95,7 +95,17 @@ static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
 					     pte_t *ptep, pte_t pte,
 					     int dirty)
 {
-	return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+	int changed = !pte_same(*ptep, pte);
+
+	if (changed) {
+		set_pte_at(vma->vm_mm, addr, ptep, pte);
+		/*
+		 * There could be some standard sized pages in there,
+		 * get them all.
+		 */
+		flush_tlb_range(vma, addr, addr + HPAGE_SIZE);
+	}
+	return changed;
 }
 
 static inline pte_t huge_ptep_get(pte_t *ptep)
diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h
index 7ebfc39..4bcbaac 100644
--- a/arch/mips/include/asm/inst.h
+++ b/arch/mips/include/asm/inst.h
@@ -161,8 +161,8 @@ enum cop1_sdw_func {
  */
 enum cop1x_func {
 	lwxc1_op     =  0x00, ldxc1_op     =  0x01,
-	pfetch_op    =  0x07, swxc1_op     =  0x08,
-	sdxc1_op     =  0x09, madd_s_op    =  0x20,
+	swxc1_op     =  0x08, sdxc1_op     =  0x09,
+	pfetch_op    =  0x0f, madd_s_op    =  0x20,
 	madd_d_op    =  0x21, madd_e_op    =  0x22,
 	msub_s_op    =  0x28, msub_d_op    =  0x29,
 	msub_e_op    =  0x2a, nmadd_s_op   =  0x30,
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index f7b3e1c..c433d19 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -15,6 +15,7 @@
 #include <linux/compiler.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
+#include <linux/irqflags.h>
 
 #include <asm/addrspace.h>
 #include <asm/byteorder.h>
@@ -204,6 +205,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
 		if (!size || last_addr < phys_addr)
 			return NULL;
 
+#if !defined(CONFIG_BRCM_UPPER_768MB)
 		/*
 		 * Map uncached objects in the low 512MB of address
 		 * space using KSEG1.
@@ -212,6 +214,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
 		    flags == _CACHE_UNCACHED)
 			return (void __iomem *)
 				(unsigned long)CKSEG1ADDR(phys_addr);
+#endif
 	}
 
 	return __ioremap(offset, size, flags);
diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h
index 309cbcd..016d2bd 100644
--- a/arch/mips/include/asm/irqflags.h
+++ b/arch/mips/include/asm/irqflags.h
@@ -16,136 +16,38 @@
 #include <linux/compiler.h>
 #include <asm/hazards.h>
 
-__asm__(
-	"	.macro	arch_local_irq_enable				\n"
-	"	.set	push						\n"
-	"	.set	reorder						\n"
-	"	.set	noat						\n"
-#ifdef CONFIG_MIPS_MT_SMTC
-	"	mfc0	$1, $2, 1	# SMTC - clear TCStatus.IXMT	\n"
-	"	ori	$1, 0x400					\n"
-	"	xori	$1, 0x400					\n"
-	"	mtc0	$1, $2, 1					\n"
-#elif defined(CONFIG_CPU_MIPSR2)
-	"	ei							\n"
-#else
-	"	mfc0	$1,$12						\n"
-	"	ori	$1,0x1f						\n"
-	"	xori	$1,0x1e						\n"
-	"	mtc0	$1,$12						\n"
-#endif
-	"	irq_enable_hazard					\n"
-	"	.set	pop						\n"
-	"	.endm");
+#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC)
 
-extern void smtc_ipi_replay(void);
-
-static inline void arch_local_irq_enable(void)
-{
-#ifdef CONFIG_MIPS_MT_SMTC
-	/*
-	 * SMTC kernel needs to do a software replay of queued
-	 * IPIs, at the cost of call overhead on each local_irq_enable()
-	 */
-	smtc_ipi_replay();
-#endif
-	__asm__ __volatile__(
-		"arch_local_irq_enable"
-		: /* no outputs */
-		: /* no inputs */
-		: "memory");
-}
-
-
-/*
- * For cli() we have to insert nops to make sure that the new value
- * has actually arrived in the status register before the end of this
- * macro.
- * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
- * no nops at all.
- */
-/*
- * For TX49, operating only IE bit is not enough.
- *
- * If mfc0 $12 follows store and the mfc0 is last instruction of a
- * page and fetching the next instruction causes TLB miss, the result
- * of the mfc0 might wrongly contain EXL bit.
- *
- * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
- *
- * Workaround: mask EXL bit of the result or place a nop before mfc0.
- */
 __asm__(
 	"	.macro	arch_local_irq_disable\n"
 	"	.set	push						\n"
 	"	.set	noat						\n"
-#ifdef CONFIG_MIPS_MT_SMTC
-	"	mfc0	$1, $2, 1					\n"
-	"	ori	$1, 0x400					\n"
-	"	.set	noreorder					\n"
-	"	mtc0	$1, $2, 1					\n"
-#elif defined(CONFIG_CPU_MIPSR2)
 	"	di							\n"
-#else
-	"	mfc0	$1,$12						\n"
-	"	ori	$1,0x1f						\n"
-	"	xori	$1,0x1f						\n"
-	"	.set	noreorder					\n"
-	"	mtc0	$1,$12						\n"
-#endif
 	"	irq_disable_hazard					\n"
 	"	.set	pop						\n"
 	"	.endm							\n");
 
 static inline void arch_local_irq_disable(void)
 {
+	arch_local_preempt_disable();
+
 	__asm__ __volatile__(
 		"arch_local_irq_disable"
 		: /* no outputs */
 		: /* no inputs */
 		: "memory");
-}
-
-__asm__(
-	"	.macro	arch_local_save_flags flags			\n"
-	"	.set	push						\n"
-	"	.set	reorder						\n"
-#ifdef CONFIG_MIPS_MT_SMTC
-	"	mfc0	\\flags, $2, 1					\n"
-#else
-	"	mfc0	\\flags, $12					\n"
-#endif
-	"	.set	pop						\n"
-	"	.endm							\n");
 
-static inline unsigned long arch_local_save_flags(void)
-{
-	unsigned long flags;
-	asm volatile("arch_local_save_flags %0" : "=r" (flags));
-	return flags;
+	arch_local_preempt_enable();
 }
 
+
 __asm__(
 	"	.macro	arch_local_irq_save result			\n"
 	"	.set	push						\n"
 	"	.set	reorder						\n"
 	"	.set	noat						\n"
-#ifdef CONFIG_MIPS_MT_SMTC
-	"	mfc0	\\result, $2, 1					\n"
-	"	ori	$1, \\result, 0x400				\n"
-	"	.set	noreorder					\n"
-	"	mtc0	$1, $2, 1					\n"
-	"	andi	\\result, \\result, 0x400			\n"
-#elif defined(CONFIG_CPU_MIPSR2)
 	"	di	\\result					\n"
 	"	andi	\\result, 1					\n"
-#else
-	"	mfc0	\\result, $12					\n"
-	"	ori	$1, \\result, 0x1f				\n"
-	"	xori	$1, 0x1f					\n"
-	"	.set	noreorder					\n"
-	"	mtc0	$1, $12						\n"
-#endif
 	"	irq_disable_hazard					\n"
 	"	.set	pop						\n"
 	"	.endm							\n");
@@ -153,85 +55,141 @@ __asm__(
 static inline unsigned long arch_local_irq_save(void)
 {
 	unsigned long flags;
+
+	arch_local_preempt_disable();
+
 	asm volatile("arch_local_irq_save\t%0"
 		     : "=r" (flags)
 		     : /* no inputs */
 		     : "memory");
+
+	arch_local_preempt_enable();
 	return flags;
 }
 
+
 __asm__(
 	"	.macro	arch_local_irq_restore flags			\n"
 	"	.set	push						\n"
 	"	.set	noreorder					\n"
 	"	.set	noat						\n"
-#ifdef CONFIG_MIPS_MT_SMTC
-	"mfc0	$1, $2, 1						\n"
-	"andi	\\flags, 0x400						\n"
-	"ori	$1, 0x400						\n"
-	"xori	$1, 0x400						\n"
-	"or	\\flags, $1						\n"
-	"mtc0	\\flags, $2, 1						\n"
-#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
+#if defined(CONFIG_IRQ_CPU)
 	/*
 	 * Slow, but doesn't suffer from a relatively unlikely race
 	 * condition we're having since days 1.
 	 */
 	"	beqz	\\flags, 1f					\n"
-	"	 di							\n"
+	"	di							\n"
 	"	ei							\n"
 	"1:								\n"
-#elif defined(CONFIG_CPU_MIPSR2)
+#else
 	/*
 	 * Fast, dangerous.  Life is fun, life is good.
 	 */
 	"	mfc0	$1, $12						\n"
 	"	ins	$1, \\flags, 0, 1				\n"
 	"	mtc0	$1, $12						\n"
-#else
-	"	mfc0	$1, $12						\n"
-	"	andi	\\flags, 1					\n"
-	"	ori	$1, 0x1f					\n"
-	"	xori	$1, 0x1f					\n"
-	"	or	\\flags, $1					\n"
-	"	mtc0	\\flags, $12					\n"
 #endif
 	"	irq_disable_hazard					\n"
 	"	.set	pop						\n"
 	"	.endm							\n");
 
-
 static inline void arch_local_irq_restore(unsigned long flags)
 {
 	unsigned long __tmp1;
 
-#ifdef CONFIG_MIPS_MT_SMTC
-	/*
-	 * SMTC kernel needs to do a software replay of queued
-	 * IPIs, at the cost of branch and call overhead on each
-	 * local_irq_restore()
-	 */
-	if (unlikely(!(flags & 0x0400)))
-		smtc_ipi_replay();
-#endif
-
 	__asm__ __volatile__(
 		"arch_local_irq_restore\t%0"
 		: "=r" (__tmp1)
 		: "0" (flags)
 		: "memory");
+
+	arch_local_preempt_enable();
 }
 
 static inline void __arch_local_irq_restore(unsigned long flags)
 {
 	unsigned long __tmp1;
 
+	arch_local_preempt_disable();
+
 	__asm__ __volatile__(
 		"arch_local_irq_restore\t%0"
 		: "=r" (__tmp1)
 		: "0" (flags)
 		: "memory");
+
+	arch_local_preempt_enable();
 }
+#else
+/* Functions that require preempt_{dis,en}able() are in mips-atomic.c */
+void arch_local_irq_disable(void);
+unsigned long arch_local_irq_save(void);
+void arch_local_irq_restore(unsigned long flags);
+void __arch_local_irq_restore(unsigned long flags);
+#endif /* if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC) */
+
+
+__asm__(
+	"	.macro	arch_local_irq_enable				\n"
+	"	.set	push						\n"
+	"	.set	reorder						\n"
+	"	.set	noat						\n"
+#ifdef CONFIG_MIPS_MT_SMTC
+	"	mfc0	$1, $2, 1	# SMTC - clear TCStatus.IXMT	\n"
+	"	ori	$1, 0x400					\n"
+	"	xori	$1, 0x400					\n"
+	"	mtc0	$1, $2, 1					\n"
+#elif defined(CONFIG_CPU_MIPSR2)
+	"	ei							\n"
+#else
+	"	mfc0	$1,$12						\n"
+	"	ori	$1,0x1f						\n"
+	"	xori	$1,0x1e						\n"
+	"	mtc0	$1,$12						\n"
+#endif
+	"	irq_enable_hazard					\n"
+	"	.set	pop						\n"
+	"	.endm");
+
+extern void smtc_ipi_replay(void);
+
+static inline void arch_local_irq_enable(void)
+{
+#ifdef CONFIG_MIPS_MT_SMTC
+	/*
+	 * SMTC kernel needs to do a software replay of queued
+	 * IPIs, at the cost of call overhead on each local_irq_enable()
+	 */
+	smtc_ipi_replay();
+#endif
+	__asm__ __volatile__(
+		"arch_local_irq_enable"
+		: /* no outputs */
+		: /* no inputs */
+		: "memory");
+}
+
+
+__asm__(
+	"	.macro	arch_local_save_flags flags			\n"
+	"	.set	push						\n"
+	"	.set	reorder						\n"
+#ifdef CONFIG_MIPS_MT_SMTC
+	"	mfc0	\\flags, $2, 1					\n"
+#else
+	"	mfc0	\\flags, $12					\n"
+#endif
+	"	.set	pop						\n"
+	"	.endm							\n");
+
+static inline unsigned long arch_local_save_flags(void)
+{
+	unsigned long flags;
+	asm volatile("arch_local_save_flags %0" : "=r" (flags));
+	return flags;
+}
+
 
 static inline int arch_irqs_disabled_flags(unsigned long flags)
 {
@@ -245,7 +203,7 @@ static inline int arch_irqs_disabled_flags(unsigned long flags)
 #endif
 }
 
-#endif
+#endif /* #ifndef __ASSEMBLY__ */
 
 /*
  * Do the CPU's IRQ-state tracing from assembly code.
diff --git a/arch/mips/include/asm/jump_label.h b/arch/mips/include/asm/jump_label.h
index e194f95..fdbff44 100644
--- a/arch/mips/include/asm/jump_label.h
+++ b/arch/mips/include/asm/jump_label.h
@@ -20,9 +20,15 @@
 #define WORD_INSN ".word"
 #endif
 
+#ifdef CONFIG_CPU_MICROMIPS
+#define NOP_INSN "nop32"
+#else
+#define NOP_INSN "nop"
+#endif
+
 static __always_inline bool arch_static_branch(struct static_key *key)
 {
-	asm_volatile_goto("1:\tnop\n\t"
+	asm_volatile_goto("1:\t" NOP_INSN "\n\t"
 		"nop\n\t"
 		".pushsection __jump_table,  \"aw\"\n\t"
 		WORD_INSN " 1b, %l[l_yes], %0\n\t"
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 5b8d15b..82a8175 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -102,7 +102,6 @@ enum bcm63xx_regs_set {
 	RSET_UART1,
 	RSET_GPIO,
 	RSET_SPI,
-	RSET_SPI2,
 	RSET_UDC0,
 	RSET_OHCI0,
 	RSET_OHCI_PRIV,
@@ -135,6 +134,10 @@ enum bcm63xx_regs_set {
 #define RSET_DSL_LMEM_SIZE		(64 * 1024 * 4)
 #define RSET_DSL_SIZE			4096
 #define RSET_WDT_SIZE			12
+#define BCM_6338_RSET_SPI_SIZE		64
+#define BCM_6348_RSET_SPI_SIZE		64
+#define BCM_6358_RSET_SPI_SIZE		1804
+#define BCM_6368_RSET_SPI_SIZE		1804
 #define RSET_ENET_SIZE			2048
 #define RSET_ENETDMA_SIZE		2048
 #define RSET_ENETSW_SIZE		65536
@@ -162,7 +165,6 @@ enum bcm63xx_regs_set {
 #define BCM_6338_UART1_BASE		(0xdeadbeef)
 #define BCM_6338_GPIO_BASE		(0xfffe0400)
 #define BCM_6338_SPI_BASE		(0xfffe0c00)
-#define BCM_6338_SPI2_BASE		(0xdeadbeef)
 #define BCM_6338_UDC0_BASE		(0xdeadbeef)
 #define BCM_6338_USBDMA_BASE		(0xfffe2400)
 #define BCM_6338_OHCI0_BASE		(0xdeadbeef)
@@ -206,7 +208,6 @@ enum bcm63xx_regs_set {
 #define BCM_6345_UART1_BASE		(0xdeadbeef)
 #define BCM_6345_GPIO_BASE		(0xfffe0400)
 #define BCM_6345_SPI_BASE		(0xdeadbeef)
-#define BCM_6345_SPI2_BASE		(0xdeadbeef)
 #define BCM_6345_UDC0_BASE		(0xdeadbeef)
 #define BCM_6345_USBDMA_BASE		(0xfffe2800)
 #define BCM_6345_ENET0_BASE		(0xfffe1800)
@@ -249,7 +250,6 @@ enum bcm63xx_regs_set {
 #define BCM_6348_UART1_BASE		(0xdeadbeef)
 #define BCM_6348_GPIO_BASE		(0xfffe0400)
 #define BCM_6348_SPI_BASE		(0xfffe0c00)
-#define BCM_6348_SPI2_BASE		(0xdeadbeef)
 #define BCM_6348_UDC0_BASE		(0xfffe1000)
 #define BCM_6348_OHCI0_BASE		(0xfffe1b00)
 #define BCM_6348_OHCI_PRIV_BASE		(0xfffe1c00)
@@ -289,8 +289,7 @@ enum bcm63xx_regs_set {
 #define BCM_6358_UART0_BASE		(0xfffe0100)
 #define BCM_6358_UART1_BASE		(0xfffe0120)
 #define BCM_6358_GPIO_BASE		(0xfffe0080)
-#define BCM_6358_SPI_BASE		(0xdeadbeef)
-#define BCM_6358_SPI2_BASE		(0xfffe0800)
+#define BCM_6358_SPI_BASE		(0xfffe0800)
 #define BCM_6358_UDC0_BASE		(0xfffe0800)
 #define BCM_6358_OHCI0_BASE		(0xfffe1400)
 #define BCM_6358_OHCI_PRIV_BASE		(0xdeadbeef)
@@ -331,8 +330,7 @@ enum bcm63xx_regs_set {
 #define BCM_6368_UART0_BASE		(0xb0000100)
 #define BCM_6368_UART1_BASE		(0xb0000120)
 #define BCM_6368_GPIO_BASE		(0xb0000080)
-#define BCM_6368_SPI_BASE		(0xdeadbeef)
-#define BCM_6368_SPI2_BASE		(0xb0000800)
+#define BCM_6368_SPI_BASE		(0xb0000800)
 #define BCM_6368_UDC0_BASE		(0xdeadbeef)
 #define BCM_6368_OHCI0_BASE		(0xb0001600)
 #define BCM_6368_OHCI_PRIV_BASE		(0xdeadbeef)
@@ -379,7 +377,6 @@ extern const unsigned long *bcm63xx_regs_base;
 	__GEN_RSET_BASE(__cpu, UART1)					\
 	__GEN_RSET_BASE(__cpu, GPIO)					\
 	__GEN_RSET_BASE(__cpu, SPI)					\
-	__GEN_RSET_BASE(__cpu, SPI2)					\
 	__GEN_RSET_BASE(__cpu, UDC0)					\
 	__GEN_RSET_BASE(__cpu, OHCI0)					\
 	__GEN_RSET_BASE(__cpu, OHCI_PRIV)				\
@@ -418,7 +415,6 @@ extern const unsigned long *bcm63xx_regs_base;
 	[RSET_UART1]		= BCM_## __cpu ##_UART1_BASE,		\
 	[RSET_GPIO]		= BCM_## __cpu ##_GPIO_BASE,		\
 	[RSET_SPI]		= BCM_## __cpu ##_SPI_BASE,		\
-	[RSET_SPI2]		= BCM_## __cpu ##_SPI2_BASE,		\
 	[RSET_UDC0]		= BCM_## __cpu ##_UDC0_BASE,		\
 	[RSET_OHCI0]		= BCM_## __cpu ##_OHCI0_BASE,		\
 	[RSET_OHCI_PRIV]	= BCM_## __cpu ##_OHCI_PRIV_BASE,	\
@@ -478,6 +474,7 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
  */
 enum bcm63xx_irq {
 	IRQ_TIMER = 0,
+	IRQ_SPI,
 	IRQ_UART0,
 	IRQ_UART1,
 	IRQ_DSL,
@@ -509,6 +506,7 @@ enum bcm63xx_irq {
  * 6338 irqs
  */
 #define BCM_6338_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
+#define BCM_6338_SPI_IRQ		(IRQ_INTERNAL_BASE + 1)
 #define BCM_6338_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
 #define BCM_6338_UART1_IRQ		0
 #define BCM_6338_DSL_IRQ		(IRQ_INTERNAL_BASE + 5)
@@ -539,6 +537,7 @@ enum bcm63xx_irq {
  * 6345 irqs
  */
 #define BCM_6345_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
+#define BCM_6345_SPI_IRQ		0
 #define BCM_6345_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
 #define BCM_6345_UART1_IRQ		0
 #define BCM_6345_DSL_IRQ		(IRQ_INTERNAL_BASE + 3)
@@ -569,6 +568,7 @@ enum bcm63xx_irq {
  * 6348 irqs
  */
 #define BCM_6348_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
+#define BCM_6348_SPI_IRQ		(IRQ_INTERNAL_BASE + 1)
 #define BCM_6348_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
 #define BCM_6348_UART1_IRQ		0
 #define BCM_6348_DSL_IRQ		(IRQ_INTERNAL_BASE + 4)
@@ -599,6 +599,7 @@ enum bcm63xx_irq {
  * 6358 irqs
  */
 #define BCM_6358_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
+#define BCM_6358_SPI_IRQ		(IRQ_INTERNAL_BASE + 1)
 #define BCM_6358_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
 #define BCM_6358_UART1_IRQ		(IRQ_INTERNAL_BASE + 3)
 #define BCM_6358_DSL_IRQ		(IRQ_INTERNAL_BASE + 29)
@@ -638,6 +639,7 @@ enum bcm63xx_irq {
 #define BCM_6368_HIGH_IRQ_BASE		(IRQ_INTERNAL_BASE + 32)
 
 #define BCM_6368_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
+#define BCM_6368_SPI_IRQ		(IRQ_INTERNAL_BASE + 1)
 #define BCM_6368_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
 #define BCM_6368_UART1_IRQ		(IRQ_INTERNAL_BASE + 3)
 #define BCM_6368_DSL_IRQ		(IRQ_INTERNAL_BASE + 4)
@@ -677,6 +679,7 @@ extern const int *bcm63xx_irqs;
 
 #define __GEN_CPU_IRQ_TABLE(__cpu)					\
 	[IRQ_TIMER]		= BCM_## __cpu ##_TIMER_IRQ,		\
+	[IRQ_SPI]		= BCM_## __cpu ##_SPI_IRQ,		\
 	[IRQ_UART0]		= BCM_## __cpu ##_UART0_IRQ,		\
 	[IRQ_UART1]		= BCM_## __cpu ##_UART1_IRQ,		\
 	[IRQ_DSL]		= BCM_## __cpu ##_DSL_IRQ,		\
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
new file mode 100644
index 0000000..7d98dbe
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
@@ -0,0 +1,89 @@
+#ifndef BCM63XX_DEV_SPI_H
+#define BCM63XX_DEV_SPI_H
+
+#include <linux/types.h>
+#include <bcm63xx_io.h>
+#include <bcm63xx_regs.h>
+
+int __init bcm63xx_spi_register(void);
+
+struct bcm63xx_spi_pdata {
+	unsigned int	fifo_size;
+	int		bus_num;
+	int		num_chipselect;
+	u32		speed_hz;
+};
+
+enum bcm63xx_regs_spi {
+	SPI_CMD,
+	SPI_INT_STATUS,
+	SPI_INT_MASK_ST,
+	SPI_INT_MASK,
+	SPI_ST,
+	SPI_CLK_CFG,
+	SPI_FILL_BYTE,
+	SPI_MSG_TAIL,
+	SPI_RX_TAIL,
+	SPI_MSG_CTL,
+	SPI_MSG_DATA,
+	SPI_RX_DATA,
+};
+
+#define __GEN_SPI_RSET_BASE(__cpu, __rset)				\
+	case SPI_## __rset:						\
+		return SPI_## __cpu ##_## __rset;
+
+#define __GEN_SPI_RSET(__cpu)						\
+	switch (reg) {							\
+	__GEN_SPI_RSET_BASE(__cpu, CMD)					\
+	__GEN_SPI_RSET_BASE(__cpu, INT_STATUS)				\
+	__GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST)				\
+	__GEN_SPI_RSET_BASE(__cpu, INT_MASK)				\
+	__GEN_SPI_RSET_BASE(__cpu, ST)					\
+	__GEN_SPI_RSET_BASE(__cpu, CLK_CFG)				\
+	__GEN_SPI_RSET_BASE(__cpu, FILL_BYTE)				\
+	__GEN_SPI_RSET_BASE(__cpu, MSG_TAIL)				\
+	__GEN_SPI_RSET_BASE(__cpu, RX_TAIL)				\
+	__GEN_SPI_RSET_BASE(__cpu, MSG_CTL)				\
+	__GEN_SPI_RSET_BASE(__cpu, MSG_DATA)				\
+	__GEN_SPI_RSET_BASE(__cpu, RX_DATA)				\
+	}
+
+#define __GEN_SPI_REGS_TABLE(__cpu)					\
+	[SPI_CMD]		= SPI_## __cpu ##_CMD,			\
+	[SPI_INT_STATUS]	= SPI_## __cpu ##_INT_STATUS,		\
+	[SPI_INT_MASK_ST]	= SPI_## __cpu ##_INT_MASK_ST,		\
+	[SPI_INT_MASK]		= SPI_## __cpu ##_INT_MASK,		\
+	[SPI_ST]		= SPI_## __cpu ##_ST,			\
+	[SPI_CLK_CFG]		= SPI_## __cpu ##_CLK_CFG,		\
+	[SPI_FILL_BYTE]		= SPI_## __cpu ##_FILL_BYTE,		\
+	[SPI_MSG_TAIL]		= SPI_## __cpu ##_MSG_TAIL,		\
+	[SPI_RX_TAIL]		= SPI_## __cpu ##_RX_TAIL,		\
+	[SPI_MSG_CTL]		= SPI_## __cpu ##_MSG_CTL,		\
+	[SPI_MSG_DATA]		= SPI_## __cpu ##_MSG_DATA,		\
+	[SPI_RX_DATA]		= SPI_## __cpu ##_RX_DATA,
+
+static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
+{
+#ifdef BCMCPU_RUNTIME_DETECT
+	extern const unsigned long *bcm63xx_regs_spi;
+
+	return bcm63xx_regs_spi[reg];
+#else
+#ifdef CONFIG_BCM63XX_CPU_6338
+	__GEN_SPI_RSET(6338)
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6348
+	__GEN_SPI_RSET(6348)
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6358
+	__GEN_SPI_RSET(6358)
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6368
+	__GEN_SPI_RSET(6368)
+#endif
+#endif
+	return 0;
+}
+
+#endif /* BCM63XX_DEV_SPI_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 94d4faa..be107e9 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -90,29 +90,29 @@
 #define CKCTL_6368_PHYMIPS_EN		(1 << 6)
 #define CKCTL_6368_SWPKT_USB_EN		(1 << 7)
 #define CKCTL_6368_SWPKT_SAR_EN		(1 << 8)
-#define CKCTL_6368_SPI_CLK_EN		(1 << 9)
-#define CKCTL_6368_USBD_CLK_EN		(1 << 10)
-#define CKCTL_6368_SAR_CLK_EN		(1 << 11)
-#define CKCTL_6368_ROBOSW_CLK_EN	(1 << 12)
-#define CKCTL_6368_UTOPIA_CLK_EN	(1 << 13)
-#define CKCTL_6368_PCM_CLK_EN		(1 << 14)
-#define CKCTL_6368_USBH_CLK_EN		(1 << 15)
+#define CKCTL_6368_SPI_EN		(1 << 9)
+#define CKCTL_6368_USBD_EN		(1 << 10)
+#define CKCTL_6368_SAR_EN		(1 << 11)
+#define CKCTL_6368_ROBOSW_EN		(1 << 12)
+#define CKCTL_6368_UTOPIA_EN		(1 << 13)
+#define CKCTL_6368_PCM_EN		(1 << 14)
+#define CKCTL_6368_USBH_EN		(1 << 15)
 #define CKCTL_6368_DISABLE_GLESS_EN	(1 << 16)
-#define CKCTL_6368_NAND_CLK_EN		(1 << 17)
-#define CKCTL_6368_IPSEC_CLK_EN		(1 << 17)
+#define CKCTL_6368_NAND_EN		(1 << 17)
+#define CKCTL_6368_IPSEC_EN		(1 << 18)
 
 #define CKCTL_6368_ALL_SAFE_EN		(CKCTL_6368_SWPKT_USB_EN |	\
 					CKCTL_6368_SWPKT_SAR_EN |	\
-					CKCTL_6368_SPI_CLK_EN |		\
-					CKCTL_6368_USBD_CLK_EN |	\
-					CKCTL_6368_SAR_CLK_EN |		\
-					CKCTL_6368_ROBOSW_CLK_EN |	\
-					CKCTL_6368_UTOPIA_CLK_EN |	\
-					CKCTL_6368_PCM_CLK_EN |		\
-					CKCTL_6368_USBH_CLK_EN |	\
+					CKCTL_6368_SPI_EN |		\
+					CKCTL_6368_USBD_EN |		\
+					CKCTL_6368_SAR_EN |		\
+					CKCTL_6368_ROBOSW_EN |		\
+					CKCTL_6368_UTOPIA_EN |		\
+					CKCTL_6368_PCM_EN |		\
+					CKCTL_6368_USBH_EN |		\
 					CKCTL_6368_DISABLE_GLESS_EN |	\
-					CKCTL_6368_NAND_CLK_EN |	\
-					CKCTL_6368_IPSEC_CLK_EN)
+					CKCTL_6368_NAND_EN |		\
+					CKCTL_6368_IPSEC_EN)
 
 /* System PLL Control register  */
 #define PERF_SYS_PLL_CTL_REG		0x8
@@ -973,4 +973,123 @@
 #define M2M_SRCID_REG(x)		((x) * 0x40 + 0x14)
 #define M2M_DSTID_REG(x)		((x) * 0x40 + 0x18)
 
+/*************************************************************************
+ * _REG relative to RSET_SPI
+ *************************************************************************/
+
+/* BCM 6338 SPI core */
+#define SPI_6338_CMD			0x00	/* 16-bits register */
+#define SPI_6338_INT_STATUS		0x02
+#define SPI_6338_INT_MASK_ST		0x03
+#define SPI_6338_INT_MASK		0x04
+#define SPI_6338_ST			0x05
+#define SPI_6338_CLK_CFG		0x06
+#define SPI_6338_FILL_BYTE		0x07
+#define SPI_6338_MSG_TAIL		0x09
+#define SPI_6338_RX_TAIL		0x0b
+#define SPI_6338_MSG_CTL		0x40
+#define SPI_6338_MSG_DATA		0x41
+#define SPI_6338_MSG_DATA_SIZE		0x3f
+#define SPI_6338_RX_DATA		0x80
+#define SPI_6338_RX_DATA_SIZE		0x3f
+
+/* BCM 6348 SPI core */
+#define SPI_6348_CMD			0x00	/* 16-bits register */
+#define SPI_6348_INT_STATUS		0x02
+#define SPI_6348_INT_MASK_ST		0x03
+#define SPI_6348_INT_MASK		0x04
+#define SPI_6348_ST			0x05
+#define SPI_6348_CLK_CFG		0x06
+#define SPI_6348_FILL_BYTE		0x07
+#define SPI_6348_MSG_TAIL		0x09
+#define SPI_6348_RX_TAIL		0x0b
+#define SPI_6348_MSG_CTL		0x40
+#define SPI_6348_MSG_DATA		0x41
+#define SPI_6348_MSG_DATA_SIZE		0x3f
+#define SPI_6348_RX_DATA		0x80
+#define SPI_6348_RX_DATA_SIZE		0x3f
+
+/* BCM 6358 SPI core */
+#define SPI_6358_MSG_CTL		0x00	/* 16-bits register */
+#define SPI_6358_MSG_DATA		0x02
+#define SPI_6358_MSG_DATA_SIZE		0x21e
+#define SPI_6358_RX_DATA		0x400
+#define SPI_6358_RX_DATA_SIZE		0x220
+#define SPI_6358_CMD			0x700	/* 16-bits register */
+#define SPI_6358_INT_STATUS		0x702
+#define SPI_6358_INT_MASK_ST		0x703
+#define SPI_6358_INT_MASK		0x704
+#define SPI_6358_ST			0x705
+#define SPI_6358_CLK_CFG		0x706
+#define SPI_6358_FILL_BYTE		0x707
+#define SPI_6358_MSG_TAIL		0x709
+#define SPI_6358_RX_TAIL		0x70B
+
+/* BCM 6358 SPI core */
+#define SPI_6368_MSG_CTL		0x00	/* 16-bits register */
+#define SPI_6368_MSG_DATA		0x02
+#define SPI_6368_MSG_DATA_SIZE		0x21e
+#define SPI_6368_RX_DATA		0x400
+#define SPI_6368_RX_DATA_SIZE		0x220
+#define SPI_6368_CMD			0x700	/* 16-bits register */
+#define SPI_6368_INT_STATUS		0x702
+#define SPI_6368_INT_MASK_ST		0x703
+#define SPI_6368_INT_MASK		0x704
+#define SPI_6368_ST			0x705
+#define SPI_6368_CLK_CFG		0x706
+#define SPI_6368_FILL_BYTE		0x707
+#define SPI_6368_MSG_TAIL		0x709
+#define SPI_6368_RX_TAIL		0x70B
+
+/* Shared SPI definitions */
+
+/* Message configuration */
+#define SPI_FD_RW			0x00
+#define SPI_HD_W			0x01
+#define SPI_HD_R			0x02
+#define SPI_BYTE_CNT_SHIFT		0
+#define SPI_MSG_TYPE_SHIFT		14
+
+/* Command */
+#define SPI_CMD_NOOP			0x00
+#define SPI_CMD_SOFT_RESET		0x01
+#define SPI_CMD_HARD_RESET		0x02
+#define SPI_CMD_START_IMMEDIATE		0x03
+#define SPI_CMD_COMMAND_SHIFT		0
+#define SPI_CMD_COMMAND_MASK		0x000f
+#define SPI_CMD_DEVICE_ID_SHIFT		4
+#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT	8
+#define SPI_CMD_ONE_BYTE_SHIFT		11
+#define SPI_CMD_ONE_WIRE_SHIFT		12
+#define SPI_DEV_ID_0			0
+#define SPI_DEV_ID_1			1
+#define SPI_DEV_ID_2			2
+#define SPI_DEV_ID_3			3
+
+/* Interrupt mask */
+#define SPI_INTR_CMD_DONE		0x01
+#define SPI_INTR_RX_OVERFLOW		0x02
+#define SPI_INTR_TX_UNDERFLOW		0x04
+#define SPI_INTR_TX_OVERFLOW		0x08
+#define SPI_INTR_RX_UNDERFLOW		0x10
+#define SPI_INTR_CLEAR_ALL		0x1f
+
+/* Status */
+#define SPI_RX_EMPTY			0x02
+#define SPI_CMD_BUSY			0x04
+#define SPI_SERIAL_BUSY			0x08
+
+/* Clock configuration */
+#define SPI_CLK_20MHZ			0x00
+#define SPI_CLK_0_391MHZ		0x01
+#define SPI_CLK_0_781MHZ		0x02 /* default */
+#define SPI_CLK_1_563MHZ		0x03
+#define SPI_CLK_3_125MHZ		0x04
+#define SPI_CLK_6_250MHZ		0x05
+#define SPI_CLK_12_50MHZ		0x06
+#define SPI_CLK_MASK			0x07
+#define SPI_SSOFFTIME_MASK		0x38
+#define SPI_SSOFFTIME_SHIFT		3
+#define SPI_BYTE_SWAP			0x80
+
 #endif /* BCM63XX_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-brcmstb/cpu-feature-overrides.h b/arch/mips/include/asm/mach-brcmstb/cpu-feature-overrides.h
new file mode 100644
index 0000000..96253be
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/cpu-feature-overrides.h
@@ -0,0 +1,63 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ralf Baechle
+ * Copyright (C) 2009 Broadcom Corporation
+ */
+#ifndef __ASM_MACH_BRCMSTB_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_BRCMSTB_CPU_FEATURE_OVERRIDES_H
+
+#if defined(CONFIG_CPU_BMIPS4380)
+
+#define cpu_has_dc_aliases		1
+#define cpu_has_ic_fills_f_dc		0
+#define cpu_has_vtag_icache		0
+#define cpu_has_inclusive_pcaches	0
+#define cpu_icache_snoops_remote_store	1
+#define cpu_has_mips32r1		1
+#define cpu_has_mips32r2		0
+#define cpu_has_mips64r1		0
+#define cpu_has_mips64r2		0
+#define cpu_dcache_line_size()		64
+#define cpu_icache_line_size()		64
+#define cpu_scache_line_size()		0
+
+#elif defined(CONFIG_CPU_BMIPS3300)
+
+#define cpu_has_dc_aliases		1
+#define cpu_has_ic_fills_f_dc		0
+#define cpu_has_vtag_icache		0
+#define cpu_has_inclusive_pcaches	0
+#define cpu_icache_snoops_remote_store	1
+#define cpu_has_mips32r1		1
+#define cpu_has_mips32r2		0
+#define cpu_has_mips64r1		0
+#define cpu_has_mips64r2		0
+#define cpu_dcache_line_size()		16
+#define cpu_icache_line_size()		16
+#define cpu_scache_line_size()		0
+
+#elif defined(CONFIG_CPU_BMIPS5000)
+
+#define cpu_has_dc_aliases		0
+#define cpu_has_ic_fills_f_dc		1
+#define cpu_has_vtag_icache		0
+#define cpu_has_inclusive_pcaches	1
+#define cpu_icache_snoops_remote_store	1
+#define cpu_has_mips32r1		1
+#define cpu_has_mips32r2		0
+#define cpu_has_mips64r1		0
+#define cpu_has_mips64r2		0
+#define cpu_dcache_line_size()		32
+#define cpu_icache_line_size()		64
+#define cpu_scache_line_size()		128
+
+#endif
+
+#if defined(CONFIG_BRCM_HAS_XI)
+#define kernel_uses_smartmips_rixi	1
+#endif
+
+#endif /* __ASM_MACH_BRCMSTB_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-brcmstb/dma-coherence.h b/arch/mips/include/asm/mach-brcmstb/dma-coherence.h
new file mode 100644
index 0000000..b63153b
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/dma-coherence.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef __ASM_MACH_BRCMSTB_DMA_COHERENCE_H
+#define __ASM_MACH_BRCMSTB_DMA_COHERENCE_H
+
+struct device;
+
+#if defined(CONFIG_PCI)
+
+extern dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size);
+extern dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page);
+extern unsigned long plat_dma_addr_to_phys(struct device *dev,
+	dma_addr_t dma_addr);
+
+#else
+
+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
+	size_t size)
+{
+	return virt_to_phys(addr);
+}
+
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+	struct page *page)
+{
+	return page_to_phys(page);
+}
+
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
+	dma_addr_t dma_addr)
+{
+	return dma_addr;
+}
+
+#endif
+
+extern void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+	size_t size, int dir);
+
+static inline int plat_dma_supported(struct device *dev, u64 mask)
+{
+	/*
+	 * we fall back to GFP_DMA when the mask isn't all 1s,
+	 * so we can't guarantee allocations that must be
+	 * within a tighter range than GFP_DMA..
+	 */
+	if (mask < DMA_BIT_MASK(24))
+		return 0;
+
+	return 1;
+}
+
+static inline void plat_extra_sync_for_device(struct device *dev)
+{
+	return;
+}
+
+static inline int plat_dma_mapping_error(struct device *dev,
+					 dma_addr_t dma_addr)
+{
+	return 0;
+}
+
+static inline int plat_device_is_coherent(struct device *dev)
+{
+	return 0;
+}
+
+#endif /* __ASM_MACH_BRCMSTB_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-brcmstb/ioremap.h b/arch/mips/include/asm/mach-brcmstb/ioremap.h
new file mode 100644
index 0000000..bf9ce3d
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/ioremap.h
@@ -0,0 +1,27 @@
+/*
+ *	include/asm-mips/mach-brcmstb/ioremap.h
+ *
+ *	This program is free software; you can redistribute it and/or
+ *	modify it under the terms of the GNU General Public License
+ *	as published by the Free Software Foundation; either version
+ *	2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MACH_BRCMSTB_IOREMAP_H
+#define __ASM_MACH_BRCMSTB_IOREMAP_H
+
+#include <linux/types.h>
+
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+	return phys_addr;
+}
+
+extern void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+	unsigned long flags);
+extern int plat_iounmap(const volatile void __iomem *addr);
+
+#endif /* __ASM_MACH_BRCMSTB_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-brcmstb/irq.h b/arch/mips/include/asm/mach-brcmstb/irq.h
new file mode 100644
index 0000000..8d44f84
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/irq.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef __ASM_MACH_BRCMSTB_IRQ_H
+#define __ASM_MACH_BRCMSTB_IRQ_H
+
+/*
+ * This file has IRQ definitions that DO NOT depend on the BCHP headers
+ * See also: linux/brcmstb/brcmstb.h
+ */
+
+/* IRQs 1-128 are used for HIF L1 */
+#define BRCM_VIRTIRQ_BASE	(1 + 128)
+
+/* virtual (non-L1) IRQs */
+
+#define BRCM_CPUIRQ_BASE	(BRCM_VIRTIRQ_BASE + 0)
+#define BRCM_OTHERIRQ_BASE	(BRCM_VIRTIRQ_BASE + 8)
+
+/* MIPS interrupts 0-7 */
+#define BRCM_IRQ_CPU0		(BRCM_CPUIRQ_BASE + 0)
+#define BRCM_IRQ_CPU1		(BRCM_CPUIRQ_BASE + 1)
+#define BRCM_IRQ_CPU2		(BRCM_CPUIRQ_BASE + 2)
+#define BRCM_IRQ_CPU3		(BRCM_CPUIRQ_BASE + 3)
+#define BRCM_IRQ_CPU4		(BRCM_CPUIRQ_BASE + 4)
+#define BRCM_IRQ_CPU5		(BRCM_CPUIRQ_BASE + 5)
+#define BRCM_IRQ_CPU6		(BRCM_CPUIRQ_BASE + 6)
+#define BRCM_IRQ_CPU7		(BRCM_CPUIRQ_BASE + 7)
+
+#define BRCM_IRQ_IPI0		BRCM_IRQ_CPU0
+#define BRCM_IRQ_IPI1		BRCM_IRQ_CPU1
+#define BRCM_IRQ_HW0		BRCM_IRQ_CPU2
+#define BRCM_IRQ_HW1		BRCM_IRQ_CPU3
+
+/* performance counter */
+
+#define BRCM_IRQ_PERF		(BRCM_OTHERIRQ_BASE + 0)
+
+#define NR_IRQS			160
+#define MIPS_CPU_IRQ_BASE	BRCM_CPUIRQ_BASE
+
+#endif /* __ASM_MACH_BRCMSTB_IRQ_H */
diff --git a/arch/mips/include/asm/mach-brcmstb/kernel-entry-init.h b/arch/mips/include/asm/mach-brcmstb/kernel-entry-init.h
new file mode 100644
index 0000000..3133784
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/kernel-entry-init.h
@@ -0,0 +1,36 @@
+/***************************************************************************
+ *     Copyright (c) 2008, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ ***************************************************************************/
+
+#ifndef __ASM_MACH_BRCMSTB_KERNEL_ENTRY_H
+#define __ASM_MACH_BRCMSTB_KERNEL_ENTRY_H
+
+	.macro kernel_entry_setup
+
+	# save arguments for CFE callback
+	sw	a0, cfe_handle
+	sw	a2, cfe_entry
+	sw	a3, cfe_seal
+
+	jal	bmips_enable_xks01
+
+	.endm
+
+        .macro  smp_slave_setup
+        .endm
+
+#endif /* __ASM_MACH_BRCMSTB_KERNEL_ENTRY_H */
diff --git a/arch/mips/include/asm/mach-brcmstb/mangle-port.h b/arch/mips/include/asm/mach-brcmstb/mangle-port.h
new file mode 100644
index 0000000..8440103
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/mangle-port.h
@@ -0,0 +1,53 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2009 Broadcom Corporation
+ */
+#ifndef __ASM_MACH_BRCMSTB_MANGLE_PORT_H
+#define __ASM_MACH_BRCMSTB_MANGLE_PORT_H
+
+#define __swizzle_addr_b(port)	(port)
+#define __swizzle_addr_w(port)	(port)
+#define __swizzle_addr_l(port)	(port)
+#define __swizzle_addr_q(port)	(port)
+
+/*
+ * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
+ * less sane hardware forces software to fiddle with this...
+ *
+ * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
+ * you can't have the numerical value of data and byte addresses within
+ * multibyte quantities both preserved at the same time.  Hence two
+ * variations of functions: non-prefixed ones that preserve the value
+ * and prefixed ones that preserve byte addresses.  The latters are
+ * typically used for moving raw data between a peripheral and memory (cf.
+ * string I/O functions), hence the "__mem_" prefix.
+ */
+#if defined(CONFIG_SWAP_IO_SPACE)
+
+# define ioswabb(a, x)		(x)
+# define __mem_ioswabb(a, x)	(x)
+# define ioswabw(a, x)		le16_to_cpu(x)
+# define __mem_ioswabw(a, x)	(x)
+# define ioswabl(a, x)		le32_to_cpu(x)
+# define __mem_ioswabl(a, x)	(x)
+# define ioswabq(a, x)		le64_to_cpu(x)
+# define __mem_ioswabq(a, x)	(x)
+
+#else
+
+# define ioswabb(a, x)		(x)
+# define __mem_ioswabb(a, x)	(x)
+# define ioswabw(a, x)		(x)
+# define __mem_ioswabw(a, x)	cpu_to_le16(x)
+# define ioswabl(a, x)		(x)
+# define __mem_ioswabl(a, x)	cpu_to_le32(x)
+# define ioswabq(a, x)		(x)
+# define __mem_ioswabq(a, x)	cpu_to_le32(x)
+
+#endif
+
+#endif /* __ASM_MACH_BRCMSTB_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-brcmstb/spaces.h b/arch/mips/include/asm/mach-brcmstb/spaces.h
new file mode 100644
index 0000000..23a1bd7
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/spaces.h
@@ -0,0 +1,151 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2009 Broadcom Corporation
+ */
+
+#ifndef _ASM_MACH_BRCMSTB_SPACES_H
+#define _ASM_MACH_BRCMSTB_SPACES_H
+
+#include <linux/const.h>
+
+/***********************************************************************
+ * Kernel virtual address space
+ ***********************************************************************/
+
+#if !defined(CONFIG_BRCM_UPPER_MEMORY)
+
+/*
+ * 256MB standard MIPS32 virtual address map
+ *
+ * 8000_0000 - 8fff_ffff: lower 256MB, cached mapping
+ * 9000_0000 - 9fff_ffff: EBI/registers, cached mapping (unused)
+ * a000_0000 - afff_ffff: lower 256MB, uncached mapping
+ * b000_0000 - bfff_ffff: EBI/registers, uncached mapping
+ * c000_0000 - ff1f_7fff: vmalloc region
+ * ff1f_8000 - ff1f_ffff: FIXMAP
+ */
+
+#define KSEG0_SIZE		_AC(0x20000000, UL)
+#define KSEG1_SIZE		_AC(0x20000000, UL)
+#define MAP_BASE		_AC(0xc0000000, UL)
+#define FIXADDR_TOP		_AC(0xff200000, UL)
+#define BRCM_MAX_UPPER_MB	_AC(0, UL)
+
+#elif defined(CONFIG_BRCM_UPPER_768MB)
+
+/*
+ * 1024MB Broadcom 256+768 virtual address map
+ *
+ * 8000_0000 - 8fff_ffff: 256MB RAM @ 0000_0000, cached
+ * 9000_0000 - 9fff_ffff: 256MB EBI/Registers @ 1000_0000, uncached
+ * a000_0000 - cfff_ffff: 768MB RAM @ 2000_0000, cached
+ * d000_0000 - dfff_ffff: TBD
+ * e000_0000 - ff1f_7fff: vmalloc region
+ * ff1f_8000 - ff1f_ffff: FIXMAP
+ * ff40_0000 - ff7f_ffff: CONSISTENT region
+ *
+ * PA 5000_0000 and above are accessed through HIGHMEM (BMIPS5000 only).
+ */
+
+#define TLB_UPPERMEM_VA		_AC(0xc0000000, UL)
+#define TLB_UPPERMEM_PA		_AC(0x40000000, UL)
+#define KSEG0_SIZE		_AC(0x40000000, UL)
+#define KSEG1_SIZE		_AC(0x00000000, UL)
+#define MAP_BASE		_AC(0xe0000000, UL)
+#define FIXADDR_TOP		_AC(0xff200000, UL)
+/* BASE and END must be 4MB-aligned (PGDIR_SIZE) */
+#define CONSISTENT_BASE		_AC(0xff400000, UL)
+#define CONSISTENT_END		_AC(0xff800000, UL)
+#define BRCM_MAX_UPPER_MB	_AC(768, UL)
+
+#endif /* CONFIG_BRCM_UPPER_MEMORY */
+
+/***********************************************************************
+ * Physical / PCI address space
+ ***********************************************************************/
+
+#ifdef CONFIG_BRCM_HAS_2GB_MEMC0
+
+/*
+ * Physical address map for 2GB MEMC0
+ *
+ * 0000_0000 - 0fff_ffff: MEMC0 (256MB)
+ * 1000_0000 - 1fff_ffff: EBI/Registers (256MB)
+ * 2000_0000 - 8fff_ffff: MEMC0 (1792MB)
+ * 9000_0000 - cfff_ffff: MEMC1 (1024MB)
+ * d000_0000 - efff_ffff: PCIe MEM BARs (512MB)
+ *
+ * PCIe inbound BAR:
+ *
+ * 0000_0000 - 0fff_ffff: MEMC0 (256MB  @ 0000_0000)
+ * 1000_0000 - 7fff_ffff: MEMC0 (1792MB @ 2000_0000)
+ * 8000_0000 - bfff_ffff: MEMC1 (1024MB @ 9000_0000)
+ */
+
+#define PCI_MEM_START		_AC(0xdeadbeef, UL)
+#define PCI_MEM_SIZE		_AC(0xdeadbeef, UL)
+
+#define PCI_IO_START		_AC(0xffff0000, UL)
+#define PCI_IO_SIZE		_AC(0x00001000, UL)
+
+#define PCIE_MEM_START		_AC(0xd0000000, UL)
+#define PCIE_MEM_SIZE		_AC(0x20000000, UL)
+
+#define MEMC1_START		_AC(0x90000000, UL)
+#define MEMC1_PCI_OFFSET	_AC(0x10000000, UL)
+
+#else /* CONFIG_BRCM_HAS_2GB_MEMC0 */
+
+/*
+ * Physical address map for <= 1GB MEMC0
+ *
+ * 0000_0000 - 0fff_ffff: MEMC0 (256MB)
+ * 1000_0000 - 1fff_ffff: EBI/Registers (256MB)
+ * 2000_0000 - 4fff_ffff: MEMC0 (768MB)
+ * 6000_0000 - 7fff_ffff: MEMC1 (512MB)
+ * a000_0000 - bfff_ffff: PCIe MEM BARs (512MB)
+ * d000_0000 - efff_ffff: PCI2.3 MEM BARs (512MB)
+ * f000_0000 - f05f_ffff: PCI2.3 IO BARs (6MB)
+ * f000_0000 - f060_000b: PCI2.3 Configuration access (12B)
+ * f100_0000 - f100_001f: PCIe Configuration access - 7420 only (32B)
+ *
+ * PCI2.3/PCIe inbound BAR:
+ *
+ * 0000_0000 - 0fff_ffff: MEMC0 (256MB  @ 0000_0000)
+ * 1000_0000 - 3fff_ffff: MEMC0 (768MB  @ 2000_0000)
+ * 4000_0000 - 7fff_ffff: MEMC1 (1024MB @ 6000_0000) (not currently implemented)
+ */
+
+#define PCI_MEM_START		_AC(0xd0000000, UL)
+#define PCI_MEM_SIZE		_AC(0x20000000, UL)
+
+/* this is really 6MB long, but 32k ought to be enough for anyone */
+#define PCI_IO_START		_AC(0xf0000000, UL)
+#define PCI_IO_SIZE		_AC(0x00008000, UL)
+#define PCI_IO_ACTUAL_SIZE	_AC(0x00600000, UL)
+
+#define PCI_IO_REG_START	_AC(0xf0600000, UL)
+#define PCI_IO_REG_SIZE		_AC(0x0000000c, UL)
+
+#define PCIE_MEM_START		_AC(0xa0000000, UL)
+#define PCIE_MEM_SIZE		_AC(0x20000000, UL)
+
+#define MEMC1_START		_AC(0x60000000, UL)
+#define MEMC1_PCI_OFFSET	_AC(0x20000000, UL)
+
+#endif /* CONFIG_BRCM_HAS_2GB_MEMC0 */
+
+#define UPPERMEM_START		_AC(0x20000000, UL)
+#define HIGHMEM_START		(UPPERMEM_START + (BRCM_MAX_UPPER_MB << 20))
+
+#define BRCM_PCI_HOLE_START	_AC(0x10000000, UL)
+#define BRCM_PCI_HOLE_SIZE	_AC(0x10000000, UL)
+
+#define BRCM_MAX_LOWER_MB	_AC(256, UL)
+
+#include <asm/mach-generic/spaces.h>
+
+#endif /* _ASM_MACH_BRCMSTB_SPACES_H */
diff --git a/arch/mips/include/asm/mach-brcmstb/war.h b/arch/mips/include/asm/mach-brcmstb/war.h
new file mode 100644
index 0000000..ebb8f2b
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_BRCMSTB_WAR_H
+#define __ASM_MIPS_MACH_BRCMSTB_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR	0
+#define R4600_V1_HIT_CACHEOP_WAR	0
+#define R4600_V2_HIT_CACHEOP_WAR	0
+#define R5432_CP0_INTERRUPT_WAR		0
+#define BCM1250_M3_WAR			0
+#define SIBYTE_1956_WAR			0
+#define MIPS4K_ICACHE_REFILL_WAR	0
+#define MIPS_CACHE_SYNC_WAR		0
+#define TX49XX_ICACHE_INDEX_INV_WAR	0
+#define RM9000_CDEX_SMP_WAR		0
+#define ICACHE_REFILLS_WORKAROUND_WAR	0
+#define R10000_LLSC_WAR			0
+#define MIPS34K_MISSED_ITLB_WAR		0
+
+#endif /* __ASM_MIPS_MACH_BRCMSTB_WAR_H */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/spaces.h b/arch/mips/include/asm/mach-cavium-octeon/spaces.h
new file mode 100644
index 0000000..daa91ac
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/spaces.h
@@ -0,0 +1,24 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2012 Cavium, Inc.
+ */
+#ifndef _ASM_MACH_CAVIUM_OCTEON_SPACES_H
+#define _ASM_MACH_CAVIUM_OCTEON_SPACES_H
+
+#include <linux/const.h>
+
+#ifdef CONFIG_64BIT
+/* They are all the same and some OCTEON II cores cannot handle 0xa8.. */
+#define CAC_BASE		_AC(0x8000000000000000, UL)
+#define UNCAC_BASE		_AC(0x8000000000000000, UL)
+#define IO_BASE			_AC(0x8000000000000000, UL)
+
+
+#endif /* CONFIG_64BIT */
+
+#include <asm/mach-generic/spaces.h>
+
+#endif /* _ASM_MACH_CAVIUM_OCTEON_SPACES_H */
diff --git a/arch/mips/include/asm/mach-ip28/spaces.h b/arch/mips/include/asm/mach-ip28/spaces.h
index 05aabb2..53ba5b3 100644
--- a/arch/mips/include/asm/mach-ip28/spaces.h
+++ b/arch/mips/include/asm/mach-ip28/spaces.h
@@ -11,10 +11,6 @@
 #ifndef _ASM_MACH_IP28_SPACES_H
 #define _ASM_MACH_IP28_SPACES_H
 
-#define CAC_BASE		0xa800000000000000
-
-#define HIGHMEM_START		(~0UL)
-
 #define PHYS_OFFSET		_AC(0x20000000, UL)
 
 #include <asm/mach-generic/spaces.h>
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 7f87d82..818ac6c 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -458,6 +458,8 @@
 #define  CAUSEF_IP7		(_ULCAST_(1)   << 15)
 #define  CAUSEB_IV		23
 #define  CAUSEF_IV		(_ULCAST_(1)   << 23)
+#define  CAUSEB_PCI		26
+#define  CAUSEF_PCI		(_ULCAST_(1)   << 26)
 #define  CAUSEB_CE		28
 #define  CAUSEF_CE		(_ULCAST_(3)   << 28)
 #define  CAUSEB_TI		30
@@ -1144,18 +1146,27 @@ do {									\
 /*
  * Macros to access the floating point coprocessor control registers
  */
-#define read_32bit_cp1_register(source)                         \
+#define _read_32bit_cp1_register(source, gas_hardfloat)         \
 ({ int __res;                                                   \
 	__asm__ __volatile__(                                   \
 	".set\tpush\n\t"					\
 	".set\treorder\n\t"					\
 	/* gas fails to assemble cfc1 for some archs (octeon).*/ \
 	".set\tmips1\n\t"					\
+	STR(gas_hardfloat)"\n\t"                                \
         "cfc1\t%0,"STR(source)"\n\t"                            \
 	".set\tpop"						\
         : "=r" (__res));                                        \
         __res;})
 
+#ifdef GAS_HAS_SET_HARDFLOAT
+#define read_32bit_cp1_register(source)					\
+	_read_32bit_cp1_register(source, .set hardfloat)
+#else
+#define read_32bit_cp1_register(source)					\
+	_read_32bit_cp1_register(source, )
+#endif
+
 #define rddsp(mask)							\
 ({									\
 	unsigned int __res;						\
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index 7467d1d..10b7b89 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -9,6 +9,7 @@ struct mod_arch_specific {
 	struct list_head dbe_list;
 	const struct exception_table_entry *dbe_start;
 	const struct exception_table_entry *dbe_end;
+	struct mips_hi16 *r_mips_hi16_list;
 };
 
 typedef uint8_t Elf64_Byte;		/* Type for a 8-bit quantity.  */
diff --git a/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h b/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h
deleted file mode 100644
index d553f8e..0000000
--- a/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h
+++ /dev/null
@@ -1,1365 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_PCIEEP_DEFS_H__
-#define __CVMX_PCIEEP_DEFS_H__
-
-#define CVMX_PCIEEP_CFG000 \
-	 (0x0000000000000000ull)
-#define CVMX_PCIEEP_CFG001 \
-	 (0x0000000000000004ull)
-#define CVMX_PCIEEP_CFG002 \
-	 (0x0000000000000008ull)
-#define CVMX_PCIEEP_CFG003 \
-	 (0x000000000000000Cull)
-#define CVMX_PCIEEP_CFG004 \
-	 (0x0000000000000010ull)
-#define CVMX_PCIEEP_CFG004_MASK \
-	 (0x0000000080000010ull)
-#define CVMX_PCIEEP_CFG005 \
-	 (0x0000000000000014ull)
-#define CVMX_PCIEEP_CFG005_MASK \
-	 (0x0000000080000014ull)
-#define CVMX_PCIEEP_CFG006 \
-	 (0x0000000000000018ull)
-#define CVMX_PCIEEP_CFG006_MASK \
-	 (0x0000000080000018ull)
-#define CVMX_PCIEEP_CFG007 \
-	 (0x000000000000001Cull)
-#define CVMX_PCIEEP_CFG007_MASK \
-	 (0x000000008000001Cull)
-#define CVMX_PCIEEP_CFG008 \
-	 (0x0000000000000020ull)
-#define CVMX_PCIEEP_CFG008_MASK \
-	 (0x0000000080000020ull)
-#define CVMX_PCIEEP_CFG009 \
-	 (0x0000000000000024ull)
-#define CVMX_PCIEEP_CFG009_MASK \
-	 (0x0000000080000024ull)
-#define CVMX_PCIEEP_CFG010 \
-	 (0x0000000000000028ull)
-#define CVMX_PCIEEP_CFG011 \
-	 (0x000000000000002Cull)
-#define CVMX_PCIEEP_CFG012 \
-	 (0x0000000000000030ull)
-#define CVMX_PCIEEP_CFG012_MASK \
-	 (0x0000000080000030ull)
-#define CVMX_PCIEEP_CFG013 \
-	 (0x0000000000000034ull)
-#define CVMX_PCIEEP_CFG015 \
-	 (0x000000000000003Cull)
-#define CVMX_PCIEEP_CFG016 \
-	 (0x0000000000000040ull)
-#define CVMX_PCIEEP_CFG017 \
-	 (0x0000000000000044ull)
-#define CVMX_PCIEEP_CFG020 \
-	 (0x0000000000000050ull)
-#define CVMX_PCIEEP_CFG021 \
-	 (0x0000000000000054ull)
-#define CVMX_PCIEEP_CFG022 \
-	 (0x0000000000000058ull)
-#define CVMX_PCIEEP_CFG023 \
-	 (0x000000000000005Cull)
-#define CVMX_PCIEEP_CFG028 \
-	 (0x0000000000000070ull)
-#define CVMX_PCIEEP_CFG029 \
-	 (0x0000000000000074ull)
-#define CVMX_PCIEEP_CFG030 \
-	 (0x0000000000000078ull)
-#define CVMX_PCIEEP_CFG031 \
-	 (0x000000000000007Cull)
-#define CVMX_PCIEEP_CFG032 \
-	 (0x0000000000000080ull)
-#define CVMX_PCIEEP_CFG033 \
-	 (0x0000000000000084ull)
-#define CVMX_PCIEEP_CFG034 \
-	 (0x0000000000000088ull)
-#define CVMX_PCIEEP_CFG037 \
-	 (0x0000000000000094ull)
-#define CVMX_PCIEEP_CFG038 \
-	 (0x0000000000000098ull)
-#define CVMX_PCIEEP_CFG039 \
-	 (0x000000000000009Cull)
-#define CVMX_PCIEEP_CFG040 \
-	 (0x00000000000000A0ull)
-#define CVMX_PCIEEP_CFG041 \
-	 (0x00000000000000A4ull)
-#define CVMX_PCIEEP_CFG042 \
-	 (0x00000000000000A8ull)
-#define CVMX_PCIEEP_CFG064 \
-	 (0x0000000000000100ull)
-#define CVMX_PCIEEP_CFG065 \
-	 (0x0000000000000104ull)
-#define CVMX_PCIEEP_CFG066 \
-	 (0x0000000000000108ull)
-#define CVMX_PCIEEP_CFG067 \
-	 (0x000000000000010Cull)
-#define CVMX_PCIEEP_CFG068 \
-	 (0x0000000000000110ull)
-#define CVMX_PCIEEP_CFG069 \
-	 (0x0000000000000114ull)
-#define CVMX_PCIEEP_CFG070 \
-	 (0x0000000000000118ull)
-#define CVMX_PCIEEP_CFG071 \
-	 (0x000000000000011Cull)
-#define CVMX_PCIEEP_CFG072 \
-	 (0x0000000000000120ull)
-#define CVMX_PCIEEP_CFG073 \
-	 (0x0000000000000124ull)
-#define CVMX_PCIEEP_CFG074 \
-	 (0x0000000000000128ull)
-#define CVMX_PCIEEP_CFG448 \
-	 (0x0000000000000700ull)
-#define CVMX_PCIEEP_CFG449 \
-	 (0x0000000000000704ull)
-#define CVMX_PCIEEP_CFG450 \
-	 (0x0000000000000708ull)
-#define CVMX_PCIEEP_CFG451 \
-	 (0x000000000000070Cull)
-#define CVMX_PCIEEP_CFG452 \
-	 (0x0000000000000710ull)
-#define CVMX_PCIEEP_CFG453 \
-	 (0x0000000000000714ull)
-#define CVMX_PCIEEP_CFG454 \
-	 (0x0000000000000718ull)
-#define CVMX_PCIEEP_CFG455 \
-	 (0x000000000000071Cull)
-#define CVMX_PCIEEP_CFG456 \
-	 (0x0000000000000720ull)
-#define CVMX_PCIEEP_CFG458 \
-	 (0x0000000000000728ull)
-#define CVMX_PCIEEP_CFG459 \
-	 (0x000000000000072Cull)
-#define CVMX_PCIEEP_CFG460 \
-	 (0x0000000000000730ull)
-#define CVMX_PCIEEP_CFG461 \
-	 (0x0000000000000734ull)
-#define CVMX_PCIEEP_CFG462 \
-	 (0x0000000000000738ull)
-#define CVMX_PCIEEP_CFG463 \
-	 (0x000000000000073Cull)
-#define CVMX_PCIEEP_CFG464 \
-	 (0x0000000000000740ull)
-#define CVMX_PCIEEP_CFG465 \
-	 (0x0000000000000744ull)
-#define CVMX_PCIEEP_CFG466 \
-	 (0x0000000000000748ull)
-#define CVMX_PCIEEP_CFG467 \
-	 (0x000000000000074Cull)
-#define CVMX_PCIEEP_CFG468 \
-	 (0x0000000000000750ull)
-#define CVMX_PCIEEP_CFG490 \
-	 (0x00000000000007A8ull)
-#define CVMX_PCIEEP_CFG491 \
-	 (0x00000000000007ACull)
-#define CVMX_PCIEEP_CFG492 \
-	 (0x00000000000007B0ull)
-#define CVMX_PCIEEP_CFG516 \
-	 (0x0000000000000810ull)
-#define CVMX_PCIEEP_CFG517 \
-	 (0x0000000000000814ull)
-
-union cvmx_pcieep_cfg000 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg000_s {
-		uint32_t devid:16;
-		uint32_t vendid:16;
-	} s;
-	struct cvmx_pcieep_cfg000_s cn52xx;
-	struct cvmx_pcieep_cfg000_s cn52xxp1;
-	struct cvmx_pcieep_cfg000_s cn56xx;
-	struct cvmx_pcieep_cfg000_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg001 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg001_s {
-		uint32_t dpe:1;
-		uint32_t sse:1;
-		uint32_t rma:1;
-		uint32_t rta:1;
-		uint32_t sta:1;
-		uint32_t devt:2;
-		uint32_t mdpe:1;
-		uint32_t fbb:1;
-		uint32_t reserved_22_22:1;
-		uint32_t m66:1;
-		uint32_t cl:1;
-		uint32_t i_stat:1;
-		uint32_t reserved_11_18:8;
-		uint32_t i_dis:1;
-		uint32_t fbbe:1;
-		uint32_t see:1;
-		uint32_t ids_wcc:1;
-		uint32_t per:1;
-		uint32_t vps:1;
-		uint32_t mwice:1;
-		uint32_t scse:1;
-		uint32_t me:1;
-		uint32_t msae:1;
-		uint32_t isae:1;
-	} s;
-	struct cvmx_pcieep_cfg001_s cn52xx;
-	struct cvmx_pcieep_cfg001_s cn52xxp1;
-	struct cvmx_pcieep_cfg001_s cn56xx;
-	struct cvmx_pcieep_cfg001_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg002 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg002_s {
-		uint32_t bcc:8;
-		uint32_t sc:8;
-		uint32_t pi:8;
-		uint32_t rid:8;
-	} s;
-	struct cvmx_pcieep_cfg002_s cn52xx;
-	struct cvmx_pcieep_cfg002_s cn52xxp1;
-	struct cvmx_pcieep_cfg002_s cn56xx;
-	struct cvmx_pcieep_cfg002_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg003 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg003_s {
-		uint32_t bist:8;
-		uint32_t mfd:1;
-		uint32_t chf:7;
-		uint32_t lt:8;
-		uint32_t cls:8;
-	} s;
-	struct cvmx_pcieep_cfg003_s cn52xx;
-	struct cvmx_pcieep_cfg003_s cn52xxp1;
-	struct cvmx_pcieep_cfg003_s cn56xx;
-	struct cvmx_pcieep_cfg003_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg004 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg004_s {
-		uint32_t lbab:18;
-		uint32_t reserved_4_13:10;
-		uint32_t pf:1;
-		uint32_t typ:2;
-		uint32_t mspc:1;
-	} s;
-	struct cvmx_pcieep_cfg004_s cn52xx;
-	struct cvmx_pcieep_cfg004_s cn52xxp1;
-	struct cvmx_pcieep_cfg004_s cn56xx;
-	struct cvmx_pcieep_cfg004_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg004_mask {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg004_mask_s {
-		uint32_t lmask:31;
-		uint32_t enb:1;
-	} s;
-	struct cvmx_pcieep_cfg004_mask_s cn52xx;
-	struct cvmx_pcieep_cfg004_mask_s cn52xxp1;
-	struct cvmx_pcieep_cfg004_mask_s cn56xx;
-	struct cvmx_pcieep_cfg004_mask_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg005 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg005_s {
-		uint32_t ubab:32;
-	} s;
-	struct cvmx_pcieep_cfg005_s cn52xx;
-	struct cvmx_pcieep_cfg005_s cn52xxp1;
-	struct cvmx_pcieep_cfg005_s cn56xx;
-	struct cvmx_pcieep_cfg005_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg005_mask {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg005_mask_s {
-		uint32_t umask:32;
-	} s;
-	struct cvmx_pcieep_cfg005_mask_s cn52xx;
-	struct cvmx_pcieep_cfg005_mask_s cn52xxp1;
-	struct cvmx_pcieep_cfg005_mask_s cn56xx;
-	struct cvmx_pcieep_cfg005_mask_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg006 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg006_s {
-		uint32_t lbab:6;
-		uint32_t reserved_4_25:22;
-		uint32_t pf:1;
-		uint32_t typ:2;
-		uint32_t mspc:1;
-	} s;
-	struct cvmx_pcieep_cfg006_s cn52xx;
-	struct cvmx_pcieep_cfg006_s cn52xxp1;
-	struct cvmx_pcieep_cfg006_s cn56xx;
-	struct cvmx_pcieep_cfg006_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg006_mask {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg006_mask_s {
-		uint32_t lmask:31;
-		uint32_t enb:1;
-	} s;
-	struct cvmx_pcieep_cfg006_mask_s cn52xx;
-	struct cvmx_pcieep_cfg006_mask_s cn52xxp1;
-	struct cvmx_pcieep_cfg006_mask_s cn56xx;
-	struct cvmx_pcieep_cfg006_mask_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg007 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg007_s {
-		uint32_t ubab:32;
-	} s;
-	struct cvmx_pcieep_cfg007_s cn52xx;
-	struct cvmx_pcieep_cfg007_s cn52xxp1;
-	struct cvmx_pcieep_cfg007_s cn56xx;
-	struct cvmx_pcieep_cfg007_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg007_mask {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg007_mask_s {
-		uint32_t umask:32;
-	} s;
-	struct cvmx_pcieep_cfg007_mask_s cn52xx;
-	struct cvmx_pcieep_cfg007_mask_s cn52xxp1;
-	struct cvmx_pcieep_cfg007_mask_s cn56xx;
-	struct cvmx_pcieep_cfg007_mask_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg008 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg008_s {
-		uint32_t reserved_4_31:28;
-		uint32_t pf:1;
-		uint32_t typ:2;
-		uint32_t mspc:1;
-	} s;
-	struct cvmx_pcieep_cfg008_s cn52xx;
-	struct cvmx_pcieep_cfg008_s cn52xxp1;
-	struct cvmx_pcieep_cfg008_s cn56xx;
-	struct cvmx_pcieep_cfg008_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg008_mask {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg008_mask_s {
-		uint32_t lmask:31;
-		uint32_t enb:1;
-	} s;
-	struct cvmx_pcieep_cfg008_mask_s cn52xx;
-	struct cvmx_pcieep_cfg008_mask_s cn52xxp1;
-	struct cvmx_pcieep_cfg008_mask_s cn56xx;
-	struct cvmx_pcieep_cfg008_mask_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg009 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg009_s {
-		uint32_t ubab:25;
-		uint32_t reserved_0_6:7;
-	} s;
-	struct cvmx_pcieep_cfg009_s cn52xx;
-	struct cvmx_pcieep_cfg009_s cn52xxp1;
-	struct cvmx_pcieep_cfg009_s cn56xx;
-	struct cvmx_pcieep_cfg009_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg009_mask {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg009_mask_s {
-		uint32_t umask:32;
-	} s;
-	struct cvmx_pcieep_cfg009_mask_s cn52xx;
-	struct cvmx_pcieep_cfg009_mask_s cn52xxp1;
-	struct cvmx_pcieep_cfg009_mask_s cn56xx;
-	struct cvmx_pcieep_cfg009_mask_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg010 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg010_s {
-		uint32_t cisp:32;
-	} s;
-	struct cvmx_pcieep_cfg010_s cn52xx;
-	struct cvmx_pcieep_cfg010_s cn52xxp1;
-	struct cvmx_pcieep_cfg010_s cn56xx;
-	struct cvmx_pcieep_cfg010_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg011 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg011_s {
-		uint32_t ssid:16;
-		uint32_t ssvid:16;
-	} s;
-	struct cvmx_pcieep_cfg011_s cn52xx;
-	struct cvmx_pcieep_cfg011_s cn52xxp1;
-	struct cvmx_pcieep_cfg011_s cn56xx;
-	struct cvmx_pcieep_cfg011_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg012 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg012_s {
-		uint32_t eraddr:16;
-		uint32_t reserved_1_15:15;
-		uint32_t er_en:1;
-	} s;
-	struct cvmx_pcieep_cfg012_s cn52xx;
-	struct cvmx_pcieep_cfg012_s cn52xxp1;
-	struct cvmx_pcieep_cfg012_s cn56xx;
-	struct cvmx_pcieep_cfg012_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg012_mask {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg012_mask_s {
-		uint32_t mask:31;
-		uint32_t enb:1;
-	} s;
-	struct cvmx_pcieep_cfg012_mask_s cn52xx;
-	struct cvmx_pcieep_cfg012_mask_s cn52xxp1;
-	struct cvmx_pcieep_cfg012_mask_s cn56xx;
-	struct cvmx_pcieep_cfg012_mask_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg013 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg013_s {
-		uint32_t reserved_8_31:24;
-		uint32_t cp:8;
-	} s;
-	struct cvmx_pcieep_cfg013_s cn52xx;
-	struct cvmx_pcieep_cfg013_s cn52xxp1;
-	struct cvmx_pcieep_cfg013_s cn56xx;
-	struct cvmx_pcieep_cfg013_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg015 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg015_s {
-		uint32_t ml:8;
-		uint32_t mg:8;
-		uint32_t inta:8;
-		uint32_t il:8;
-	} s;
-	struct cvmx_pcieep_cfg015_s cn52xx;
-	struct cvmx_pcieep_cfg015_s cn52xxp1;
-	struct cvmx_pcieep_cfg015_s cn56xx;
-	struct cvmx_pcieep_cfg015_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg016 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg016_s {
-		uint32_t pmes:5;
-		uint32_t d2s:1;
-		uint32_t d1s:1;
-		uint32_t auxc:3;
-		uint32_t dsi:1;
-		uint32_t reserved_20_20:1;
-		uint32_t pme_clock:1;
-		uint32_t pmsv:3;
-		uint32_t ncp:8;
-		uint32_t pmcid:8;
-	} s;
-	struct cvmx_pcieep_cfg016_s cn52xx;
-	struct cvmx_pcieep_cfg016_s cn52xxp1;
-	struct cvmx_pcieep_cfg016_s cn56xx;
-	struct cvmx_pcieep_cfg016_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg017 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg017_s {
-		uint32_t pmdia:8;
-		uint32_t bpccee:1;
-		uint32_t bd3h:1;
-		uint32_t reserved_16_21:6;
-		uint32_t pmess:1;
-		uint32_t pmedsia:2;
-		uint32_t pmds:4;
-		uint32_t pmeens:1;
-		uint32_t reserved_4_7:4;
-		uint32_t nsr:1;
-		uint32_t reserved_2_2:1;
-		uint32_t ps:2;
-	} s;
-	struct cvmx_pcieep_cfg017_s cn52xx;
-	struct cvmx_pcieep_cfg017_s cn52xxp1;
-	struct cvmx_pcieep_cfg017_s cn56xx;
-	struct cvmx_pcieep_cfg017_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg020 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg020_s {
-		uint32_t reserved_24_31:8;
-		uint32_t m64:1;
-		uint32_t mme:3;
-		uint32_t mmc:3;
-		uint32_t msien:1;
-		uint32_t ncp:8;
-		uint32_t msicid:8;
-	} s;
-	struct cvmx_pcieep_cfg020_s cn52xx;
-	struct cvmx_pcieep_cfg020_s cn52xxp1;
-	struct cvmx_pcieep_cfg020_s cn56xx;
-	struct cvmx_pcieep_cfg020_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg021 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg021_s {
-		uint32_t lmsi:30;
-		uint32_t reserved_0_1:2;
-	} s;
-	struct cvmx_pcieep_cfg021_s cn52xx;
-	struct cvmx_pcieep_cfg021_s cn52xxp1;
-	struct cvmx_pcieep_cfg021_s cn56xx;
-	struct cvmx_pcieep_cfg021_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg022 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg022_s {
-		uint32_t umsi:32;
-	} s;
-	struct cvmx_pcieep_cfg022_s cn52xx;
-	struct cvmx_pcieep_cfg022_s cn52xxp1;
-	struct cvmx_pcieep_cfg022_s cn56xx;
-	struct cvmx_pcieep_cfg022_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg023 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg023_s {
-		uint32_t reserved_16_31:16;
-		uint32_t msimd:16;
-	} s;
-	struct cvmx_pcieep_cfg023_s cn52xx;
-	struct cvmx_pcieep_cfg023_s cn52xxp1;
-	struct cvmx_pcieep_cfg023_s cn56xx;
-	struct cvmx_pcieep_cfg023_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg028 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg028_s {
-		uint32_t reserved_30_31:2;
-		uint32_t imn:5;
-		uint32_t si:1;
-		uint32_t dpt:4;
-		uint32_t pciecv:4;
-		uint32_t ncp:8;
-		uint32_t pcieid:8;
-	} s;
-	struct cvmx_pcieep_cfg028_s cn52xx;
-	struct cvmx_pcieep_cfg028_s cn52xxp1;
-	struct cvmx_pcieep_cfg028_s cn56xx;
-	struct cvmx_pcieep_cfg028_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg029 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg029_s {
-		uint32_t reserved_28_31:4;
-		uint32_t cspls:2;
-		uint32_t csplv:8;
-		uint32_t reserved_16_17:2;
-		uint32_t rber:1;
-		uint32_t reserved_12_14:3;
-		uint32_t el1al:3;
-		uint32_t el0al:3;
-		uint32_t etfs:1;
-		uint32_t pfs:2;
-		uint32_t mpss:3;
-	} s;
-	struct cvmx_pcieep_cfg029_s cn52xx;
-	struct cvmx_pcieep_cfg029_s cn52xxp1;
-	struct cvmx_pcieep_cfg029_s cn56xx;
-	struct cvmx_pcieep_cfg029_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg030 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg030_s {
-		uint32_t reserved_22_31:10;
-		uint32_t tp:1;
-		uint32_t ap_d:1;
-		uint32_t ur_d:1;
-		uint32_t fe_d:1;
-		uint32_t nfe_d:1;
-		uint32_t ce_d:1;
-		uint32_t reserved_15_15:1;
-		uint32_t mrrs:3;
-		uint32_t ns_en:1;
-		uint32_t ap_en:1;
-		uint32_t pf_en:1;
-		uint32_t etf_en:1;
-		uint32_t mps:3;
-		uint32_t ro_en:1;
-		uint32_t ur_en:1;
-		uint32_t fe_en:1;
-		uint32_t nfe_en:1;
-		uint32_t ce_en:1;
-	} s;
-	struct cvmx_pcieep_cfg030_s cn52xx;
-	struct cvmx_pcieep_cfg030_s cn52xxp1;
-	struct cvmx_pcieep_cfg030_s cn56xx;
-	struct cvmx_pcieep_cfg030_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg031 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg031_s {
-		uint32_t pnum:8;
-		uint32_t reserved_22_23:2;
-		uint32_t lbnc:1;
-		uint32_t dllarc:1;
-		uint32_t sderc:1;
-		uint32_t cpm:1;
-		uint32_t l1el:3;
-		uint32_t l0el:3;
-		uint32_t aslpms:2;
-		uint32_t mlw:6;
-		uint32_t mls:4;
-	} s;
-	struct cvmx_pcieep_cfg031_s cn52xx;
-	struct cvmx_pcieep_cfg031_s cn52xxp1;
-	struct cvmx_pcieep_cfg031_s cn56xx;
-	struct cvmx_pcieep_cfg031_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg032 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg032_s {
-		uint32_t reserved_30_31:2;
-		uint32_t dlla:1;
-		uint32_t scc:1;
-		uint32_t lt:1;
-		uint32_t reserved_26_26:1;
-		uint32_t nlw:6;
-		uint32_t ls:4;
-		uint32_t reserved_10_15:6;
-		uint32_t hawd:1;
-		uint32_t ecpm:1;
-		uint32_t es:1;
-		uint32_t ccc:1;
-		uint32_t rl:1;
-		uint32_t ld:1;
-		uint32_t rcb:1;
-		uint32_t reserved_2_2:1;
-		uint32_t aslpc:2;
-	} s;
-	struct cvmx_pcieep_cfg032_s cn52xx;
-	struct cvmx_pcieep_cfg032_s cn52xxp1;
-	struct cvmx_pcieep_cfg032_s cn56xx;
-	struct cvmx_pcieep_cfg032_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg033 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg033_s {
-		uint32_t ps_num:13;
-		uint32_t nccs:1;
-		uint32_t emip:1;
-		uint32_t sp_ls:2;
-		uint32_t sp_lv:8;
-		uint32_t hp_c:1;
-		uint32_t hp_s:1;
-		uint32_t pip:1;
-		uint32_t aip:1;
-		uint32_t mrlsp:1;
-		uint32_t pcp:1;
-		uint32_t abp:1;
-	} s;
-	struct cvmx_pcieep_cfg033_s cn52xx;
-	struct cvmx_pcieep_cfg033_s cn52xxp1;
-	struct cvmx_pcieep_cfg033_s cn56xx;
-	struct cvmx_pcieep_cfg033_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg034 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg034_s {
-		uint32_t reserved_25_31:7;
-		uint32_t dlls_c:1;
-		uint32_t emis:1;
-		uint32_t pds:1;
-		uint32_t mrlss:1;
-		uint32_t ccint_d:1;
-		uint32_t pd_c:1;
-		uint32_t mrls_c:1;
-		uint32_t pf_d:1;
-		uint32_t abp_d:1;
-		uint32_t reserved_13_15:3;
-		uint32_t dlls_en:1;
-		uint32_t emic:1;
-		uint32_t pcc:1;
-		uint32_t pic:2;
-		uint32_t aic:2;
-		uint32_t hpint_en:1;
-		uint32_t ccint_en:1;
-		uint32_t pd_en:1;
-		uint32_t mrls_en:1;
-		uint32_t pf_en:1;
-		uint32_t abp_en:1;
-	} s;
-	struct cvmx_pcieep_cfg034_s cn52xx;
-	struct cvmx_pcieep_cfg034_s cn52xxp1;
-	struct cvmx_pcieep_cfg034_s cn56xx;
-	struct cvmx_pcieep_cfg034_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg037 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg037_s {
-		uint32_t reserved_5_31:27;
-		uint32_t ctds:1;
-		uint32_t ctrs:4;
-	} s;
-	struct cvmx_pcieep_cfg037_s cn52xx;
-	struct cvmx_pcieep_cfg037_s cn52xxp1;
-	struct cvmx_pcieep_cfg037_s cn56xx;
-	struct cvmx_pcieep_cfg037_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg038 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg038_s {
-		uint32_t reserved_5_31:27;
-		uint32_t ctd:1;
-		uint32_t ctv:4;
-	} s;
-	struct cvmx_pcieep_cfg038_s cn52xx;
-	struct cvmx_pcieep_cfg038_s cn52xxp1;
-	struct cvmx_pcieep_cfg038_s cn56xx;
-	struct cvmx_pcieep_cfg038_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg039 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg039_s {
-		uint32_t reserved_0_31:32;
-	} s;
-	struct cvmx_pcieep_cfg039_s cn52xx;
-	struct cvmx_pcieep_cfg039_s cn52xxp1;
-	struct cvmx_pcieep_cfg039_s cn56xx;
-	struct cvmx_pcieep_cfg039_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg040 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg040_s {
-		uint32_t reserved_0_31:32;
-	} s;
-	struct cvmx_pcieep_cfg040_s cn52xx;
-	struct cvmx_pcieep_cfg040_s cn52xxp1;
-	struct cvmx_pcieep_cfg040_s cn56xx;
-	struct cvmx_pcieep_cfg040_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg041 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg041_s {
-		uint32_t reserved_0_31:32;
-	} s;
-	struct cvmx_pcieep_cfg041_s cn52xx;
-	struct cvmx_pcieep_cfg041_s cn52xxp1;
-	struct cvmx_pcieep_cfg041_s cn56xx;
-	struct cvmx_pcieep_cfg041_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg042 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg042_s {
-		uint32_t reserved_0_31:32;
-	} s;
-	struct cvmx_pcieep_cfg042_s cn52xx;
-	struct cvmx_pcieep_cfg042_s cn52xxp1;
-	struct cvmx_pcieep_cfg042_s cn56xx;
-	struct cvmx_pcieep_cfg042_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg064 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg064_s {
-		uint32_t nco:12;
-		uint32_t cv:4;
-		uint32_t pcieec:16;
-	} s;
-	struct cvmx_pcieep_cfg064_s cn52xx;
-	struct cvmx_pcieep_cfg064_s cn52xxp1;
-	struct cvmx_pcieep_cfg064_s cn56xx;
-	struct cvmx_pcieep_cfg064_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg065 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg065_s {
-		uint32_t reserved_21_31:11;
-		uint32_t ures:1;
-		uint32_t ecrces:1;
-		uint32_t mtlps:1;
-		uint32_t ros:1;
-		uint32_t ucs:1;
-		uint32_t cas:1;
-		uint32_t cts:1;
-		uint32_t fcpes:1;
-		uint32_t ptlps:1;
-		uint32_t reserved_6_11:6;
-		uint32_t sdes:1;
-		uint32_t dlpes:1;
-		uint32_t reserved_0_3:4;
-	} s;
-	struct cvmx_pcieep_cfg065_s cn52xx;
-	struct cvmx_pcieep_cfg065_s cn52xxp1;
-	struct cvmx_pcieep_cfg065_s cn56xx;
-	struct cvmx_pcieep_cfg065_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg066 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg066_s {
-		uint32_t reserved_21_31:11;
-		uint32_t urem:1;
-		uint32_t ecrcem:1;
-		uint32_t mtlpm:1;
-		uint32_t rom:1;
-		uint32_t ucm:1;
-		uint32_t cam:1;
-		uint32_t ctm:1;
-		uint32_t fcpem:1;
-		uint32_t ptlpm:1;
-		uint32_t reserved_6_11:6;
-		uint32_t sdem:1;
-		uint32_t dlpem:1;
-		uint32_t reserved_0_3:4;
-	} s;
-	struct cvmx_pcieep_cfg066_s cn52xx;
-	struct cvmx_pcieep_cfg066_s cn52xxp1;
-	struct cvmx_pcieep_cfg066_s cn56xx;
-	struct cvmx_pcieep_cfg066_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg067 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg067_s {
-		uint32_t reserved_21_31:11;
-		uint32_t ures:1;
-		uint32_t ecrces:1;
-		uint32_t mtlps:1;
-		uint32_t ros:1;
-		uint32_t ucs:1;
-		uint32_t cas:1;
-		uint32_t cts:1;
-		uint32_t fcpes:1;
-		uint32_t ptlps:1;
-		uint32_t reserved_6_11:6;
-		uint32_t sdes:1;
-		uint32_t dlpes:1;
-		uint32_t reserved_0_3:4;
-	} s;
-	struct cvmx_pcieep_cfg067_s cn52xx;
-	struct cvmx_pcieep_cfg067_s cn52xxp1;
-	struct cvmx_pcieep_cfg067_s cn56xx;
-	struct cvmx_pcieep_cfg067_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg068 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg068_s {
-		uint32_t reserved_14_31:18;
-		uint32_t anfes:1;
-		uint32_t rtts:1;
-		uint32_t reserved_9_11:3;
-		uint32_t rnrs:1;
-		uint32_t bdllps:1;
-		uint32_t btlps:1;
-		uint32_t reserved_1_5:5;
-		uint32_t res:1;
-	} s;
-	struct cvmx_pcieep_cfg068_s cn52xx;
-	struct cvmx_pcieep_cfg068_s cn52xxp1;
-	struct cvmx_pcieep_cfg068_s cn56xx;
-	struct cvmx_pcieep_cfg068_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg069 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg069_s {
-		uint32_t reserved_14_31:18;
-		uint32_t anfem:1;
-		uint32_t rttm:1;
-		uint32_t reserved_9_11:3;
-		uint32_t rnrm:1;
-		uint32_t bdllpm:1;
-		uint32_t btlpm:1;
-		uint32_t reserved_1_5:5;
-		uint32_t rem:1;
-	} s;
-	struct cvmx_pcieep_cfg069_s cn52xx;
-	struct cvmx_pcieep_cfg069_s cn52xxp1;
-	struct cvmx_pcieep_cfg069_s cn56xx;
-	struct cvmx_pcieep_cfg069_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg070 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg070_s {
-		uint32_t reserved_9_31:23;
-		uint32_t ce:1;
-		uint32_t cc:1;
-		uint32_t ge:1;
-		uint32_t gc:1;
-		uint32_t fep:5;
-	} s;
-	struct cvmx_pcieep_cfg070_s cn52xx;
-	struct cvmx_pcieep_cfg070_s cn52xxp1;
-	struct cvmx_pcieep_cfg070_s cn56xx;
-	struct cvmx_pcieep_cfg070_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg071 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg071_s {
-		uint32_t dword1:32;
-	} s;
-	struct cvmx_pcieep_cfg071_s cn52xx;
-	struct cvmx_pcieep_cfg071_s cn52xxp1;
-	struct cvmx_pcieep_cfg071_s cn56xx;
-	struct cvmx_pcieep_cfg071_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg072 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg072_s {
-		uint32_t dword2:32;
-	} s;
-	struct cvmx_pcieep_cfg072_s cn52xx;
-	struct cvmx_pcieep_cfg072_s cn52xxp1;
-	struct cvmx_pcieep_cfg072_s cn56xx;
-	struct cvmx_pcieep_cfg072_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg073 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg073_s {
-		uint32_t dword3:32;
-	} s;
-	struct cvmx_pcieep_cfg073_s cn52xx;
-	struct cvmx_pcieep_cfg073_s cn52xxp1;
-	struct cvmx_pcieep_cfg073_s cn56xx;
-	struct cvmx_pcieep_cfg073_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg074 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg074_s {
-		uint32_t dword4:32;
-	} s;
-	struct cvmx_pcieep_cfg074_s cn52xx;
-	struct cvmx_pcieep_cfg074_s cn52xxp1;
-	struct cvmx_pcieep_cfg074_s cn56xx;
-	struct cvmx_pcieep_cfg074_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg448 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg448_s {
-		uint32_t rtl:16;
-		uint32_t rtltl:16;
-	} s;
-	struct cvmx_pcieep_cfg448_s cn52xx;
-	struct cvmx_pcieep_cfg448_s cn52xxp1;
-	struct cvmx_pcieep_cfg448_s cn56xx;
-	struct cvmx_pcieep_cfg448_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg449 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg449_s {
-		uint32_t omr:32;
-	} s;
-	struct cvmx_pcieep_cfg449_s cn52xx;
-	struct cvmx_pcieep_cfg449_s cn52xxp1;
-	struct cvmx_pcieep_cfg449_s cn56xx;
-	struct cvmx_pcieep_cfg449_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg450 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg450_s {
-		uint32_t lpec:8;
-		uint32_t reserved_22_23:2;
-		uint32_t link_state:6;
-		uint32_t force_link:1;
-		uint32_t reserved_8_14:7;
-		uint32_t link_num:8;
-	} s;
-	struct cvmx_pcieep_cfg450_s cn52xx;
-	struct cvmx_pcieep_cfg450_s cn52xxp1;
-	struct cvmx_pcieep_cfg450_s cn56xx;
-	struct cvmx_pcieep_cfg450_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg451 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg451_s {
-		uint32_t reserved_30_31:2;
-		uint32_t l1el:3;
-		uint32_t l0el:3;
-		uint32_t n_fts_cc:8;
-		uint32_t n_fts:8;
-		uint32_t ack_freq:8;
-	} s;
-	struct cvmx_pcieep_cfg451_s cn52xx;
-	struct cvmx_pcieep_cfg451_s cn52xxp1;
-	struct cvmx_pcieep_cfg451_s cn56xx;
-	struct cvmx_pcieep_cfg451_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg452 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg452_s {
-		uint32_t reserved_26_31:6;
-		uint32_t eccrc:1;
-		uint32_t reserved_22_24:3;
-		uint32_t lme:6;
-		uint32_t reserved_8_15:8;
-		uint32_t flm:1;
-		uint32_t reserved_6_6:1;
-		uint32_t dllle:1;
-		uint32_t reserved_4_4:1;
-		uint32_t ra:1;
-		uint32_t le:1;
-		uint32_t sd:1;
-		uint32_t omr:1;
-	} s;
-	struct cvmx_pcieep_cfg452_s cn52xx;
-	struct cvmx_pcieep_cfg452_s cn52xxp1;
-	struct cvmx_pcieep_cfg452_s cn56xx;
-	struct cvmx_pcieep_cfg452_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg453 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg453_s {
-		uint32_t dlld:1;
-		uint32_t reserved_26_30:5;
-		uint32_t ack_nak:1;
-		uint32_t fcd:1;
-		uint32_t ilst:24;
-	} s;
-	struct cvmx_pcieep_cfg453_s cn52xx;
-	struct cvmx_pcieep_cfg453_s cn52xxp1;
-	struct cvmx_pcieep_cfg453_s cn56xx;
-	struct cvmx_pcieep_cfg453_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg454 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg454_s {
-		uint32_t reserved_29_31:3;
-		uint32_t tmfcwt:5;
-		uint32_t tmanlt:5;
-		uint32_t tmrt:5;
-		uint32_t reserved_11_13:3;
-		uint32_t nskps:3;
-		uint32_t reserved_4_7:4;
-		uint32_t ntss:4;
-	} s;
-	struct cvmx_pcieep_cfg454_s cn52xx;
-	struct cvmx_pcieep_cfg454_s cn52xxp1;
-	struct cvmx_pcieep_cfg454_s cn56xx;
-	struct cvmx_pcieep_cfg454_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg455 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg455_s {
-		uint32_t m_cfg0_filt:1;
-		uint32_t m_io_filt:1;
-		uint32_t msg_ctrl:1;
-		uint32_t m_cpl_ecrc_filt:1;
-		uint32_t m_ecrc_filt:1;
-		uint32_t m_cpl_len_err:1;
-		uint32_t m_cpl_attr_err:1;
-		uint32_t m_cpl_tc_err:1;
-		uint32_t m_cpl_fun_err:1;
-		uint32_t m_cpl_rid_err:1;
-		uint32_t m_cpl_tag_err:1;
-		uint32_t m_lk_filt:1;
-		uint32_t m_cfg1_filt:1;
-		uint32_t m_bar_match:1;
-		uint32_t m_pois_filt:1;
-		uint32_t m_fun:1;
-		uint32_t dfcwt:1;
-		uint32_t reserved_11_14:4;
-		uint32_t skpiv:11;
-	} s;
-	struct cvmx_pcieep_cfg455_s cn52xx;
-	struct cvmx_pcieep_cfg455_s cn52xxp1;
-	struct cvmx_pcieep_cfg455_s cn56xx;
-	struct cvmx_pcieep_cfg455_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg456 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg456_s {
-		uint32_t reserved_2_31:30;
-		uint32_t m_vend1_drp:1;
-		uint32_t m_vend0_drp:1;
-	} s;
-	struct cvmx_pcieep_cfg456_s cn52xx;
-	struct cvmx_pcieep_cfg456_s cn52xxp1;
-	struct cvmx_pcieep_cfg456_s cn56xx;
-	struct cvmx_pcieep_cfg456_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg458 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg458_s {
-		uint32_t dbg_info_l32:32;
-	} s;
-	struct cvmx_pcieep_cfg458_s cn52xx;
-	struct cvmx_pcieep_cfg458_s cn52xxp1;
-	struct cvmx_pcieep_cfg458_s cn56xx;
-	struct cvmx_pcieep_cfg458_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg459 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg459_s {
-		uint32_t dbg_info_u32:32;
-	} s;
-	struct cvmx_pcieep_cfg459_s cn52xx;
-	struct cvmx_pcieep_cfg459_s cn52xxp1;
-	struct cvmx_pcieep_cfg459_s cn56xx;
-	struct cvmx_pcieep_cfg459_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg460 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg460_s {
-		uint32_t reserved_20_31:12;
-		uint32_t tphfcc:8;
-		uint32_t tpdfcc:12;
-	} s;
-	struct cvmx_pcieep_cfg460_s cn52xx;
-	struct cvmx_pcieep_cfg460_s cn52xxp1;
-	struct cvmx_pcieep_cfg460_s cn56xx;
-	struct cvmx_pcieep_cfg460_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg461 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg461_s {
-		uint32_t reserved_20_31:12;
-		uint32_t tchfcc:8;
-		uint32_t tcdfcc:12;
-	} s;
-	struct cvmx_pcieep_cfg461_s cn52xx;
-	struct cvmx_pcieep_cfg461_s cn52xxp1;
-	struct cvmx_pcieep_cfg461_s cn56xx;
-	struct cvmx_pcieep_cfg461_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg462 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg462_s {
-		uint32_t reserved_20_31:12;
-		uint32_t tchfcc:8;
-		uint32_t tcdfcc:12;
-	} s;
-	struct cvmx_pcieep_cfg462_s cn52xx;
-	struct cvmx_pcieep_cfg462_s cn52xxp1;
-	struct cvmx_pcieep_cfg462_s cn56xx;
-	struct cvmx_pcieep_cfg462_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg463 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg463_s {
-		uint32_t reserved_3_31:29;
-		uint32_t rqne:1;
-		uint32_t trbne:1;
-		uint32_t rtlpfccnr:1;
-	} s;
-	struct cvmx_pcieep_cfg463_s cn52xx;
-	struct cvmx_pcieep_cfg463_s cn52xxp1;
-	struct cvmx_pcieep_cfg463_s cn56xx;
-	struct cvmx_pcieep_cfg463_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg464 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg464_s {
-		uint32_t wrr_vc3:8;
-		uint32_t wrr_vc2:8;
-		uint32_t wrr_vc1:8;
-		uint32_t wrr_vc0:8;
-	} s;
-	struct cvmx_pcieep_cfg464_s cn52xx;
-	struct cvmx_pcieep_cfg464_s cn52xxp1;
-	struct cvmx_pcieep_cfg464_s cn56xx;
-	struct cvmx_pcieep_cfg464_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg465 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg465_s {
-		uint32_t wrr_vc7:8;
-		uint32_t wrr_vc6:8;
-		uint32_t wrr_vc5:8;
-		uint32_t wrr_vc4:8;
-	} s;
-	struct cvmx_pcieep_cfg465_s cn52xx;
-	struct cvmx_pcieep_cfg465_s cn52xxp1;
-	struct cvmx_pcieep_cfg465_s cn56xx;
-	struct cvmx_pcieep_cfg465_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg466 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg466_s {
-		uint32_t rx_queue_order:1;
-		uint32_t type_ordering:1;
-		uint32_t reserved_24_29:6;
-		uint32_t queue_mode:3;
-		uint32_t reserved_20_20:1;
-		uint32_t header_credits:8;
-		uint32_t data_credits:12;
-	} s;
-	struct cvmx_pcieep_cfg466_s cn52xx;
-	struct cvmx_pcieep_cfg466_s cn52xxp1;
-	struct cvmx_pcieep_cfg466_s cn56xx;
-	struct cvmx_pcieep_cfg466_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg467 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg467_s {
-		uint32_t reserved_24_31:8;
-		uint32_t queue_mode:3;
-		uint32_t reserved_20_20:1;
-		uint32_t header_credits:8;
-		uint32_t data_credits:12;
-	} s;
-	struct cvmx_pcieep_cfg467_s cn52xx;
-	struct cvmx_pcieep_cfg467_s cn52xxp1;
-	struct cvmx_pcieep_cfg467_s cn56xx;
-	struct cvmx_pcieep_cfg467_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg468 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg468_s {
-		uint32_t reserved_24_31:8;
-		uint32_t queue_mode:3;
-		uint32_t reserved_20_20:1;
-		uint32_t header_credits:8;
-		uint32_t data_credits:12;
-	} s;
-	struct cvmx_pcieep_cfg468_s cn52xx;
-	struct cvmx_pcieep_cfg468_s cn52xxp1;
-	struct cvmx_pcieep_cfg468_s cn56xx;
-	struct cvmx_pcieep_cfg468_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg490 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg490_s {
-		uint32_t reserved_26_31:6;
-		uint32_t header_depth:10;
-		uint32_t reserved_14_15:2;
-		uint32_t data_depth:14;
-	} s;
-	struct cvmx_pcieep_cfg490_s cn52xx;
-	struct cvmx_pcieep_cfg490_s cn52xxp1;
-	struct cvmx_pcieep_cfg490_s cn56xx;
-	struct cvmx_pcieep_cfg490_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg491 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg491_s {
-		uint32_t reserved_26_31:6;
-		uint32_t header_depth:10;
-		uint32_t reserved_14_15:2;
-		uint32_t data_depth:14;
-	} s;
-	struct cvmx_pcieep_cfg491_s cn52xx;
-	struct cvmx_pcieep_cfg491_s cn52xxp1;
-	struct cvmx_pcieep_cfg491_s cn56xx;
-	struct cvmx_pcieep_cfg491_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg492 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg492_s {
-		uint32_t reserved_26_31:6;
-		uint32_t header_depth:10;
-		uint32_t reserved_14_15:2;
-		uint32_t data_depth:14;
-	} s;
-	struct cvmx_pcieep_cfg492_s cn52xx;
-	struct cvmx_pcieep_cfg492_s cn52xxp1;
-	struct cvmx_pcieep_cfg492_s cn56xx;
-	struct cvmx_pcieep_cfg492_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg516 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg516_s {
-		uint32_t phy_stat:32;
-	} s;
-	struct cvmx_pcieep_cfg516_s cn52xx;
-	struct cvmx_pcieep_cfg516_s cn52xxp1;
-	struct cvmx_pcieep_cfg516_s cn56xx;
-	struct cvmx_pcieep_cfg516_s cn56xxp1;
-};
-
-union cvmx_pcieep_cfg517 {
-	uint32_t u32;
-	struct cvmx_pcieep_cfg517_s {
-		uint32_t phy_ctrl:32;
-	} s;
-	struct cvmx_pcieep_cfg517_s cn52xx;
-	struct cvmx_pcieep_cfg517_s cn52xxp1;
-	struct cvmx_pcieep_cfg517_s cn56xx;
-	struct cvmx_pcieep_cfg517_s cn56xxp1;
-};
-
-#endif
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index 0913b4f..2dbfd73 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -208,10 +208,18 @@ static inline int pfn_valid(unsigned long pfn)
 #define VM_DATA_DEFAULT_FLAGS	(VM_READ | VM_WRITE | VM_EXEC | \
 				 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
 
+#if defined(CONFIG_BRCM_UPPER_768MB)
+
+/* uncached kseg1 does not exist in this configuration */
+
+#define CAC_ADDR(addr)		({ BUG(); NULL; })
+
+#else
 #define UNCAC_ADDR(addr)	((addr) - PAGE_OFFSET + UNCAC_BASE + 	\
 								PHYS_OFFSET)
 #define CAC_ADDR(addr)		((addr) - UNCAC_BASE + PAGE_OFFSET -	\
 								PHYS_OFFSET)
+#endif
 
 #include <asm-generic/memory_model.h>
 #include <asm-generic/getorder.h>
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index fcd4060..2f8acd7 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -82,6 +82,18 @@ static inline void pcibios_penalize_isa_irq(int irq, int active)
 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 	enum pci_mmap_state mmap_state, int write_combine);
 
+#define HAVE_ARCH_PCI_RESOURCE_TO_USER
+
+static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
+		const struct resource *rsrc, resource_size_t *start,
+		resource_size_t *end)
+{
+	phys_t size = resource_size(rsrc);
+
+	*start = fixup_bigphys_addr(rsrc->start, size);
+	*end = rsrc->start + size;
+}
+
 /*
  * Dynamic DMA mapping stuff.
  * MIPS has everything mapped statically.
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index 95bcedb..c47ea55 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -21,7 +21,7 @@
 struct mm_struct;
 struct vm_area_struct;
 
-#define PAGE_NONE	__pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
+#define PAGE_NONE	__pgprot(_PAGE_PRESENT | _page_cachable_default)
 #define PAGE_SHARED	__pgprot(_PAGE_PRESENT | _PAGE_WRITE | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
 				 _page_cachable_default)
 #define PAGE_COPY	__pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
@@ -97,6 +97,9 @@ extern void paging_init(void);
 #define pmd_page(pmd)		(pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
 #define pmd_page_vaddr(pmd)	pmd_val(pmd)
 
+extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
+	pte_t pteval);
+
 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 
 #define pte_none(pte)		(!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
@@ -121,7 +124,6 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
 		}
 	}
 }
-#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
 
 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 {
@@ -189,7 +191,6 @@ static inline void set_pte(pte_t *ptep, pte_t pteval)
 	}
 #endif
 }
-#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
 
 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 {
@@ -388,22 +389,20 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 #else
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
-	return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
+	return __pte((pte_val(pte) & _PAGE_CHG_MASK) |
+		     (pgprot_val(newprot) & ~_PAGE_CHG_MASK));
 }
 #endif
 
 
 extern void __update_tlb(struct vm_area_struct *vma, unsigned long address,
 	pte_t pte);
-extern void __update_cache(struct vm_area_struct *vma, unsigned long address,
-	pte_t pte);
 
 static inline void update_mmu_cache(struct vm_area_struct *vma,
 	unsigned long address, pte_t *ptep)
 {
 	pte_t pte = *ptep;
 	__update_tlb(vma, address, pte);
-	__update_cache(vma, address, pte);
 }
 
 #define kern_addr_valid(addr)	(1)
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 20e9dcf..bbf00d5 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -48,7 +48,7 @@ extern unsigned int vced_count, vcei_count;
  * User space process size: 2GB. This is hardcoded into a few places,
  * so don't change it unless you know what you are doing.
  */
-#define TASK_SIZE	0x7fff8000UL
+#define TASK_SIZE	0x80000000UL
 
 #ifdef __KERNEL__
 #define STACK_TOP_MAX	TASK_SIZE
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index 4b7f525..5f841b4e 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -144,7 +144,7 @@ static inline int is_syscall_success(struct pt_regs *regs)
 
 static inline long regs_return_value(struct pt_regs *regs)
 {
-	if (is_syscall_success(regs))
+	if (is_syscall_success(regs) || !user_mode(regs))
 		return regs->regs[2];
 	else
 		return -regs->regs[2];
diff --git a/arch/mips/include/asm/siginfo.h b/arch/mips/include/asm/siginfo.h
index 20ebeb8..c121b4b 100644
--- a/arch/mips/include/asm/siginfo.h
+++ b/arch/mips/include/asm/siginfo.h
@@ -45,13 +45,13 @@ typedef struct siginfo {
 
 		/* kill() */
 		struct {
-			pid_t _pid;		/* sender's pid */
+			__kernel_pid_t _pid;	/* sender's pid */
 			__ARCH_SI_UID_T _uid;	/* sender's uid */
 		} _kill;
 
 		/* POSIX.1b timers */
 		struct {
-			timer_t _tid;		/* timer id */
+			__kernel_timer_t _tid;	/* timer id */
 			int _overrun;		/* overrun count */
 			char _pad[sizeof( __ARCH_SI_UID_T) - sizeof(int)];
 			sigval_t _sigval;	/* same as below */
@@ -60,26 +60,26 @@ typedef struct siginfo {
 
 		/* POSIX.1b signals */
 		struct {
-			pid_t _pid;		/* sender's pid */
+			__kernel_pid_t _pid;	/* sender's pid */
 			__ARCH_SI_UID_T _uid;	/* sender's uid */
 			sigval_t _sigval;
 		} _rt;
 
 		/* SIGCHLD */
 		struct {
-			pid_t _pid;		/* which child */
+			__kernel_pid_t _pid;	/* which child */
 			__ARCH_SI_UID_T _uid;	/* sender's uid */
 			int _status;		/* exit code */
-			clock_t _utime;
-			clock_t _stime;
+			__kernel_clock_t _utime;
+			__kernel_clock_t _stime;
 		} _sigchld;
 
 		/* IRIX SIGCHLD */
 		struct {
-			pid_t _pid;		/* which child */
-			clock_t _utime;
+			__kernel_pid_t _pid;	/* which child */
+			__kernel_clock_t _utime;
 			int _status;		/* exit code */
-			clock_t _stime;
+			__kernel_clock_t _stime;
 		} _irix_sigchld;
 
 		/* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h
index 7165333..4461198 100644
--- a/arch/mips/include/asm/sparsemem.h
+++ b/arch/mips/include/asm/sparsemem.h
@@ -6,7 +6,11 @@
  * SECTION_SIZE_BITS		2^N: how big each section will be
  * MAX_PHYSMEM_BITS		2^N: how much memory we can have in that space
  */
-#define SECTION_SIZE_BITS       28
+#if defined(CONFIG_HUGETLB_PAGE) && defined(CONFIG_PAGE_SIZE_64KB)
+# define SECTION_SIZE_BITS	29
+#else
+# define SECTION_SIZE_BITS	28
+#endif
 #define MAX_PHYSMEM_BITS        35
 
 #endif /* CONFIG_SPARSEMEM */
diff --git a/arch/mips/include/asm/stackprotector.h b/arch/mips/include/asm/stackprotector.h
new file mode 100644
index 0000000..eb9b103
--- /dev/null
+++ b/arch/mips/include/asm/stackprotector.h
@@ -0,0 +1,40 @@
+/*
+ * GCC stack protector support.
+ *
+ * (This is directly adopted from the ARM implementation)
+ *
+ * Stack protector works by putting predefined pattern at the start of
+ * the stack frame and verifying that it hasn't been overwritten when
+ * returning from the function.  The pattern is called stack canary
+ * and gcc expects it to be defined by a global variable called
+ * "__stack_chk_guard" on MIPS.  This unfortunately means that on SMP
+ * we cannot have a different canary value per task.
+ */
+
+#ifndef _ASM_STACKPROTECTOR_H
+#define _ASM_STACKPROTECTOR_H 1
+
+#include <linux/random.h>
+#include <linux/version.h>
+
+extern unsigned long __stack_chk_guard;
+
+/*
+ * Initialize the stackprotector canary value.
+ *
+ * NOTE: this must only be called from functions that never return,
+ * and it must always be inlined.
+ */
+static __always_inline void boot_init_stack_canary(void)
+{
+	unsigned long canary;
+
+	/* Try to get a semi random initial value. */
+	get_random_bytes(&canary, sizeof(canary));
+	canary ^= LINUX_VERSION_CODE;
+
+	current->stack_canary = canary;
+	__stack_chk_guard = current->stack_canary;
+}
+
+#endif	/* _ASM_STACKPROTECTOR_H */
diff --git a/arch/mips/include/asm/swab.h b/arch/mips/include/asm/swab.h
index 97c2f81..d842842 100644
--- a/arch/mips/include/asm/swab.h
+++ b/arch/mips/include/asm/swab.h
@@ -15,10 +15,15 @@
 
 #ifdef CONFIG_CPU_MIPSR2
 
-static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
+static inline __attribute__((nomips16)) __attribute_const__
+		__u16 __arch_swab16(__u16 x)
 {
 	__asm__(
+	"	.set	push			\n"
+	"	.set	arch=mips32r2		\n"
+	"	.set	nomips16		\n"
 	"	wsbh	%0, %1			\n"
+	"	.set	pop			\n"
 	: "=r" (x)
 	: "r" (x));
 
@@ -26,11 +31,16 @@ static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
 }
 #define __arch_swab16 __arch_swab16
 
-static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
+static inline __attribute__((nomips16)) __attribute_const__
+		__u32 __arch_swab32(__u32 x)
 {
 	__asm__(
+	"	.set	push			\n"
+	"	.set	arch=mips32r2		\n"
+	"	.set	nomips16		\n"
 	"	wsbh	%0, %1			\n"
 	"	rotr	%0, %0, 16		\n"
+	"	.set	pop			\n"
 	: "=r" (x)
 	: "r" (x));
 
@@ -43,11 +53,15 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
  * optimized version for 64-bit kernel on r2 CPUs.
  */
 #ifdef CONFIG_64BIT
-static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
+static inline __attribute_const__ __attribute__((nomips16))
+	__u64 __arch_swab64(__u64 x)
 {
 	__asm__(
-	"	dsbh	%0, %1\n"
-	"	dshd	%0, %0"
+	"	.set	push			\n"
+	"	.set	nomips16		\n"
+	"	dsbh	%0, %1			\n"
+	"	dshd	%0, %0			\n"
+	"	.set	pop			\n"
 	: "=r" (x)
 	: "r" (x));
 
diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h
index 5d33621..4f8ddba8 100644
--- a/arch/mips/include/asm/switch_to.h
+++ b/arch/mips/include/asm/switch_to.h
@@ -22,7 +22,7 @@ struct task_struct;
  * switch_to(n) should switch tasks to task nr n, first
  * checking that n isn't the current task, in which case it does nothing.
  */
-extern asmlinkage void *resume(void *last, void *next, void *next_ti);
+extern asmlinkage void *resume(void *last, void *next, void *next_ti, u32 __usedfpu);
 
 extern unsigned int ll_bit;
 extern struct task_struct *ll_task;
@@ -66,11 +66,13 @@ do {									\
 
 #define switch_to(prev, next, last)					\
 do {									\
+	u32 __usedfpu;							\
 	__mips_mt_fpaff_switch_to(prev);				\
 	if (cpu_has_dsp)						\
 		__save_dsp(prev);					\
 	__clear_software_ll_bit();					\
-	(last) = resume(prev, next, task_thread_info(next));		\
+	__usedfpu = test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU);	\
+	(last) = resume(prev, next, task_thread_info(next), __usedfpu);	\
 } while (0)
 
 #define finish_arch_switch(prev)					\
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index abb13e8..5da4b7f 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -125,12 +125,6 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define TIF_LOAD_WATCH		25	/* If set, load watch registers */
 #define TIF_SYSCALL_TRACE	31	/* syscall trace active */
 
-#ifdef CONFIG_MIPS32_O32
-#define TIF_32BIT TIF_32BIT_REGS
-#elif defined(CONFIG_MIPS32_N32)
-#define TIF_32BIT _TIF_32BIT_ADDR
-#endif /* CONFIG_MIPS32_O32 */
-
 #define _TIF_SYSCALL_TRACE	(1<<TIF_SYSCALL_TRACE)
 #define _TIF_SIGPENDING		(1<<TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED	(1<<TIF_NEED_RESCHED)
@@ -147,6 +141,9 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define _TIF_FPUBOUND		(1<<TIF_FPUBOUND)
 #define _TIF_LOAD_WATCH		(1<<TIF_LOAD_WATCH)
 
+#define _TIF_WORK_SYSCALL_ENTRY	(_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | \
+				 _TIF_SECCOMP)
+
 /* work to do in syscall_trace_leave() */
 #define _TIF_WORK_SYSCALL_EXIT	(_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT)
 
diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h
index 653a412..0ded06b 100644
--- a/arch/mips/include/asm/uaccess.h
+++ b/arch/mips/include/asm/uaccess.h
@@ -250,6 +250,8 @@ do {									\
 	might_fault();							\
 	if (likely(access_ok(VERIFY_READ,  __gu_ptr, size)))		\
 		__get_user_common((x), size, __gu_ptr);			\
+	else								\
+		(x) = 0;						\
 									\
 	__gu_err;							\
 })
@@ -263,6 +265,7 @@ do {									\
 	"2:							\n"	\
 	"	.section .fixup,\"ax\"				\n"	\
 	"3:	li	%0, %4					\n"	\
+	"	move	%1, $0					\n"	\
 	"	j	2b					\n"	\
 	"	.previous					\n"	\
 	"	.section __ex_table,\"a\"			\n"	\
@@ -526,6 +529,7 @@ do {									\
 	"2:							\n"	\
 	"	.section .fixup,\"ax\"				\n"	\
 	"3:	li	%0, %4					\n"	\
+	"	move	%1, $0					\n"	\
 	"	j	2b					\n"	\
 	"	.previous					\n"	\
 	"	.section __ex_table,\"a\"			\n"	\
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index 6b30fb2..3fd3681 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -8,6 +8,7 @@
  * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 2000 MIPS Technologies, Inc.
  */
+#define __GENERATING_OFFSETS_S
 #include <linux/compat.h>
 #include <linux/types.h>
 #include <linux/sched.h>
@@ -81,6 +82,9 @@ void output_task_defines(void)
 	OFFSET(TASK_FLAGS, task_struct, flags);
 	OFFSET(TASK_MM, task_struct, mm);
 	OFFSET(TASK_PID, task_struct, pid);
+#if defined(CONFIG_CC_STACKPROTECTOR)
+	OFFSET(TASK_STACK_CANARY, task_struct, stack_canary);
+#endif
 	DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct));
 	BLANK();
 }
diff --git a/arch/mips/kernel/bmips_vec.S b/arch/mips/kernel/bmips_vec.S
index e908e81..771660a 100644
--- a/arch/mips/kernel/bmips_vec.S
+++ b/arch/mips/kernel/bmips_vec.S
@@ -82,11 +82,11 @@ NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
 	.align	4
 
 #ifdef CONFIG_SMP
-	/* if the NMI bit is clear, assume this is a CPU1 reset instead */
+	/* if the NMI bit is clear, assume this is a soft reset */
 	li	k1, (1 << 19)
 	mfc0	k0, CP0_STATUS
 	and	k0, k1
-	beqz	k0, bmips_smp_entry
+	beqz	k0, soft_reset
 
 #if defined(CONFIG_CPU_BMIPS5000)
 	/* if we're not on core 0, this must be the SMP boot signal */
@@ -118,12 +118,44 @@ NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
 	eret
 
 /***********************************************************************
- * CPU1 reset vector (used for the initial boot only)
+ * CPU1 reset vector (used for the initial and warm boot only)
  * This is still part of bmips_reset_nmi_vec().
  ***********************************************************************/
 
 #ifdef CONFIG_SMP
 
+soft_reset:
+
+#if defined(CONFIG_CPU_BMIPS5000) && defined(CONFIG_BCM7435)
+	/* if running on TP 1, jump  to  bmips_smp_entry */
+	mfc0	k0, $22
+	li	k1, (1 << 24)
+	and	k1, k0
+	bnez	k1, bmips_smp_entry
+	nop
+
+	/*
+	 * running on TP0, can not be core 0 (the boot core).
+	 * Check for soft reset.  Indicates a warm boot
+	 */
+	mfc0	k0, $12
+	li	k1, (1 << 20)
+	and	k0, k1
+	beqz	k0, bmips_smp_entry
+
+	/*
+	 * Warm boot.
+	 * Cache init is only done on TP0
+	 */
+	la	k0, bmips_5xxx_init
+	jalr	k0
+	nop
+
+	b	bmips_smp_entry
+	nop
+#endif
+
+
 bmips_smp_entry:
 
 	/* set up CP0 STATUS; enable FPU */
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 4d735d0..1d3ffba 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -139,7 +139,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
 		if (regs->regs[insn.i_format.rs] ==
 		    regs->regs[insn.i_format.rt]) {
 			epc = epc + 4 + (insn.i_format.simmediate << 2);
-			if (insn.i_format.rt == beql_op)
+			if (insn.i_format.opcode == beql_op)
 				ret = BRANCH_LIKELY_TAKEN;
 		} else
 			epc += 8;
@@ -151,7 +151,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
 		if (regs->regs[insn.i_format.rs] !=
 		    regs->regs[insn.i_format.rt]) {
 			epc = epc + 4 + (insn.i_format.simmediate << 2);
-			if (insn.i_format.rt == bnel_op)
+			if (insn.i_format.opcode == bnel_op)
 				ret = BRANCH_LIKELY_TAKEN;
 		} else
 			epc += 8;
@@ -163,7 +163,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
 		/* rt field assumed to be zero */
 		if ((long)regs->regs[insn.i_format.rs] <= 0) {
 			epc = epc + 4 + (insn.i_format.simmediate << 2);
-			if (insn.i_format.rt == bnel_op)
+			if (insn.i_format.opcode == blezl_op)
 				ret = BRANCH_LIKELY_TAKEN;
 		} else
 			epc += 8;
@@ -175,7 +175,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
 		/* rt field assumed to be zero */
 		if ((long)regs->regs[insn.i_format.rs] > 0) {
 			epc = epc + 4 + (insn.i_format.simmediate << 2);
-			if (insn.i_format.rt == bnel_op)
+			if (insn.i_format.opcode == bgtzl_op)
 				ret = BRANCH_LIKELY_TAKEN;
 		} else
 			epc += 8;
@@ -188,7 +188,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
 	case cop1_op:
 		preempt_disable();
 		if (is_fpu_owner())
-			asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
+			fcr31 = read_32bit_cp1_register(CP1_STATUS);
 		else
 			fcr31 = current->thread.fpu.fcr31;
 		preempt_enable();
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 51095dd9..fbe7680 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -16,6 +16,10 @@
 #include <asm/time.h>
 #include <asm/cevt-r4k.h>
 
+#ifdef CONFIG_BRCMSTB
+#include <linux/brcmstb/brcmapi.h>
+#endif
+
 /*
  * The SMTC Kernel for the 34K, 1004K, et. al. replaces several
  * of these routines with SMTC-specific variants.
@@ -30,7 +34,11 @@ static int mips_next_event(unsigned long delta,
 	int res;
 
 	cnt = read_c0_count();
+#ifdef CONFIG_BRCMSTB
+	cnt += brcm_fixup_ticks(delta);
+#else
 	cnt += delta;
+#endif
 	write_c0_compare(cnt);
 	res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0;
 	return res;
@@ -44,6 +52,83 @@ void mips_set_clock_mode(enum clock_event_mode mode,
 	/* Nothing to do ...  */
 }
 
+/**
+ * calculate_min_delta() - Calculate a good minimum delta for mips_next_event().
+ *
+ * Running under virtualisation can introduce overhead into mips_next_event() in
+ * the form of hypervisor emulation of CP0_Count/CP0_Compare registers,
+ * potentially with an unnatural frequency, which makes a fixed min_delta_ns
+ * value inappropriate as it may be too small.
+ *
+ * It can also introduce occasional latency from the guest being descheduled.
+ *
+ * This function calculates a good minimum delta based roughly on the 75th
+ * percentile of the time taken to do the mips_next_event() sequence, in order
+ * to handle potentially higher overhead while also eliminating outliers due to
+ * unpredictable hypervisor latency (which can be handled by retries).
+ *
+ * Return:	An appropriate minimum delta for the clock event device.
+ */
+static unsigned int calculate_min_delta(void)
+{
+	unsigned int cnt, i, j, k, l;
+	unsigned int buf1[4], buf2[3];
+	unsigned int min_delta;
+
+	/*
+	 * Calculate the median of 5 75th percentiles of 5 samples of how long
+	 * it takes to set CP0_Compare = CP0_Count + delta.
+	 */
+	for (i = 0; i < 5; ++i) {
+		for (j = 0; j < 5; ++j) {
+			/*
+			 * This is like the code in mips_next_event(), and
+			 * directly measures the borderline "safe" delta.
+			 */
+			cnt = read_c0_count();
+			write_c0_compare(cnt);
+			cnt = read_c0_count() - cnt;
+
+			/* Sorted insert into buf1 */
+			for (k = 0; k < j; ++k) {
+				if (cnt < buf1[k]) {
+					l = min_t(unsigned int,
+						  j, ARRAY_SIZE(buf1) - 1);
+					for (; l > k; --l)
+						buf1[l] = buf1[l - 1];
+					break;
+				}
+			}
+			if (k < ARRAY_SIZE(buf1))
+				buf1[k] = cnt;
+		}
+
+		/* Sorted insert of 75th percentile into buf2 */
+		for (k = 0; k < i; ++k) {
+			if (buf1[ARRAY_SIZE(buf1) - 1] < buf2[k]) {
+				l = min_t(unsigned int,
+					  i, ARRAY_SIZE(buf2) - 1);
+				for (; l > k; --l)
+					buf2[l] = buf2[l - 1];
+				break;
+			}
+		}
+		if (k < ARRAY_SIZE(buf2))
+			buf2[k] = buf1[ARRAY_SIZE(buf1) - 1];
+	}
+
+	/* Use 2 * median of 75th percentiles */
+	min_delta = buf2[ARRAY_SIZE(buf2) - 1] * 2;
+
+	/* Don't go too low */
+	if (min_delta < 0x300)
+		min_delta = 0x300;
+
+	pr_debug("%s: median 75th percentile=%#x, min_delta=%#x\n",
+		 __func__, buf2[ARRAY_SIZE(buf2) - 1], min_delta);
+	return min_delta;
+}
+
 DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
 int cp0_timer_irq_installed;
 
@@ -166,7 +251,7 @@ int __cpuinit r4k_clockevent_init(void)
 {
 	unsigned int cpu = smp_processor_id();
 	struct clock_event_device *cd;
-	unsigned int irq;
+	unsigned int irq, min_delta;
 
 	if (!cpu_has_counter || !mips_hpt_frequency)
 		return -ENXIO;
@@ -188,11 +273,7 @@ int __cpuinit r4k_clockevent_init(void)
 	cd->name		= "MIPS";
 	cd->features		= CLOCK_EVT_FEAT_ONESHOT;
 
-	clockevent_set_clock(cd, mips_hpt_frequency);
-
-	/* Calculate the min / max delta */
-	cd->max_delta_ns	= clockevent_delta2ns(0x7fffffff, cd);
-	cd->min_delta_ns	= clockevent_delta2ns(0x300, cd);
+	min_delta		= calculate_min_delta();
 
 	cd->rating		= 300;
 	cd->irq			= irq;
@@ -201,7 +282,7 @@ int __cpuinit r4k_clockevent_init(void)
 	cd->set_mode		= mips_set_clock_mode;
 	cd->event_handler	= mips_event_handler;
 
-	clockevents_register_device(cd);
+	clockevents_config_and_register(cd, mips_hpt_frequency, min_delta, 0x7fffffff);
 
 	if (cp0_timer_irq_installed)
 		return 0;
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 5099201..b1c0193 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -354,7 +354,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 				c->cputype = CPU_R3000A;
 				__cpu_name[cpu] = "R3000A";
 			}
-			break;
 		} else {
 			c->cputype = CPU_R3000;
 			__cpu_name[cpu] = "R3000";
@@ -392,6 +391,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 		c->tlbsize = 48;
 		break;
 	case PRID_IMP_VR41XX:
+		c->isa_level = MIPS_CPU_ISA_III;
+		c->options = R4K_OPTS;
+		c->tlbsize = 32;
 		switch (c->processor_id & 0xf0) {
 		case PRID_REV_VR4111:
 			c->cputype = CPU_VR4111;
@@ -416,6 +418,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 				__cpu_name[cpu] = "NEC VR4131";
 			} else {
 				c->cputype = CPU_VR4133;
+				c->options |= MIPS_CPU_LLSC;
 				__cpu_name[cpu] = "NEC VR4133";
 			}
 			break;
@@ -425,9 +428,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 			__cpu_name[cpu] = "NEC Vr41xx";
 			break;
 		}
-		c->isa_level = MIPS_CPU_ISA_III;
-		c->options = R4K_OPTS;
-		c->tlbsize = 32;
 		break;
 	case PRID_IMP_R4300:
 		c->cputype = CPU_R4300;
@@ -815,10 +815,13 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 		__cpu_name[cpu] = "MIPS 20Kc";
 		break;
 	case PRID_IMP_24K:
-	case PRID_IMP_24KE:
 		c->cputype = CPU_24K;
 		__cpu_name[cpu] = "MIPS 24Kc";
 		break;
+	case PRID_IMP_24KE:
+		c->cputype = CPU_24K;
+		__cpu_name[cpu] = "MIPS 24KEc";
+		break;
 	case PRID_IMP_25KF:
 		c->cputype = CPU_25KF;
 		__cpu_name[cpu] = "MIPS 25Kc";
@@ -953,6 +956,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 		break;
 	}
 	case PRID_IMP_BMIPS5000:
+	case PRID_IMP_BMIPS5200:
 		c->cputype = CPU_BMIPS5000;
 		__cpu_name[cpu] = "Broadcom BMIPS5000";
 		set_elf_platform(cpu, "bmips5000");
@@ -1164,8 +1168,11 @@ __cpuinit void cpu_probe(void)
 		}
 	}
 
-	if (cpu_has_mips_r2)
+	if (cpu_has_mips_r2) {
 		c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
+		/* R2 has Performance Counter Interrupt indicator */
+		c->options |= MIPS_CPU_PCI;
+	}
 	else
 		c->srsets = 1;
 
diff --git a/arch/mips/kernel/csrc-ioasic.c b/arch/mips/kernel/csrc-ioasic.c
index 46bd7fa..c75085c 100644
--- a/arch/mips/kernel/csrc-ioasic.c
+++ b/arch/mips/kernel/csrc-ioasic.c
@@ -41,9 +41,9 @@ void __init dec_ioasic_clocksource_init(void)
 {
 	unsigned int freq;
 	u32 start, end;
-	int i = HZ / 10;
-
+	int i = HZ / 8;
 
+	ds1287_timer_state();
 	while (!ds1287_timer_state())
 		;
 
@@ -55,7 +55,7 @@ void __init dec_ioasic_clocksource_init(void)
 
 	end = dec_ioasic_hpt_read(&clocksource_dec);
 
-	freq = (end - start) * 10;
+	freq = (end - start) * 8;
 	printk(KERN_INFO "I/O ASIC clock frequency %dHz\n", freq);
 
 	clocksource_dec.rating = 200 + freq / 10000000;
diff --git a/arch/mips/kernel/early_printk.c b/arch/mips/kernel/early_printk.c
index 9ae813e..9e6440e 100644
--- a/arch/mips/kernel/early_printk.c
+++ b/arch/mips/kernel/early_printk.c
@@ -14,8 +14,7 @@
 
 extern void prom_putchar(char);
 
-static void __init
-early_console_write(struct console *con, const char *s, unsigned n)
+static void early_console_write(struct console *con, const char *s, unsigned n)
 {
 	while (n-- && *s) {
 		if (*s == '\n')
@@ -25,7 +24,7 @@ early_console_write(struct console *con, const char *s, unsigned n)
 	}
 }
 
-static struct console early_console __initdata = {
+static struct console early_console = {
 	.name	= "early",
 	.write	= early_console_write,
 	.flags	= CON_PRINTBUFFER | CON_BOOT,
diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S
index 37acfa0..8090efc 100644
--- a/arch/mips/kernel/entry.S
+++ b/arch/mips/kernel/entry.S
@@ -36,6 +36,11 @@ FEXPORT(ret_from_exception)
 FEXPORT(ret_from_irq)
 	LONG_S	s0, TI_REGS($28)
 FEXPORT(__ret_from_irq)
+/*
+ * We can be coming here from a syscall done in the kernel space,
+ * e.g. a failed kernel_execve().
+ */
+resume_userspace_check:
 	LONG_L	t0, PT_STATUS(sp)		# returning to kernel mode?
 	andi	t0, t0, KU_USER
 	beqz	t0, resume_kernel
@@ -162,7 +167,7 @@ work_notifysig:				# deal with pending signals and
 	move	a0, sp
 	li	a1, 0
 	jal	do_notify_resume	# a2 already loaded
-	j	resume_userspace
+	j	resume_userspace_check
 
 FEXPORT(syscall_exit_work_partial)
 	SAVE_STATIC
diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
index 6a2d758..8e8cbaf 100644
--- a/arch/mips/kernel/ftrace.c
+++ b/arch/mips/kernel/ftrace.c
@@ -25,6 +25,12 @@
 #define MCOUNT_OFFSET_INSNS 4
 #endif
 
+/* Arch override because MIPS doesn't need to run this from stop_machine() */
+void arch_ftrace_update_code(int command)
+{
+	ftrace_modify_all_code(command);
+}
+
 /*
  * Check if the address is in kernel space
  *
@@ -89,6 +95,30 @@ static int ftrace_modify_code(unsigned long ip, unsigned int new_code)
 	return 0;
 }
 
+#ifndef CONFIG_64BIT
+/*
+ * When 2 instructions are being changed, you can't do 2 calls to
+ * a subroutine that is traced because eventually it will be modifying
+ * itself and on the second call it will execute with only the first
+ * instruction changed and it will crash.
+ */
+static int ftrace_modify_code_2(unsigned long ip, unsigned int new_code1,
+				unsigned int new_code2)
+{
+	int faulted;
+
+	safe_store_code(new_code1, ip, faulted);
+	if (unlikely(faulted))
+		return -EFAULT;
+	ip += 4;
+	safe_store_code(new_code2, ip, faulted);
+	if (unlikely(faulted))
+		return -EFAULT;
+	flush_icache_range(ip, ip + 8); /* original ip + 12 */
+	return 0;
+}
+#endif
+
 /*
  * The details about the calling site of mcount on MIPS
  *
@@ -123,16 +153,27 @@ static int ftrace_modify_code(unsigned long ip, unsigned int new_code)
 int ftrace_make_nop(struct module *mod,
 		    struct dyn_ftrace *rec, unsigned long addr)
 {
-	unsigned int new;
 	unsigned long ip = rec->ip;
 
 	/*
 	 * If ip is in kernel space, no long call, otherwise, long call is
 	 * needed.
 	 */
-	new = in_kernel_space(ip) ? INSN_NOP : INSN_B_1F;
-
-	return ftrace_modify_code(ip, new);
+	if (!in_kernel_space(ip))
+		return(ftrace_modify_code(ip, INSN_B_1F));
+	
+#ifdef CONFIG_64BIT
+	return ftrace_modify_code(ip, INSN_NOP);
+#else
+	/*
+	 * For non-module kernel functions on 32 bit MIPS platforms,
+	 * gcc adds a stack adjust instruction in the delay slot
+	 * after the branch to mcount and expects mcount to restore
+	 * the sp on return. This is based on a legacy API and does
+	 * nothing but waste instructions so it's being removed at runtime.
+	 */
+	return ftrace_modify_code_2(ip, INSN_NOP, INSN_NOP);
+#endif
 }
 
 int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index 8882e57..69542ce 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -388,6 +388,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
 	.set	push
 	/* gas fails to assemble cfc1 for some archs (octeon).*/ \
 	.set	mips1
+	SET_HARDFLOAT
 	cfc1	a1, fcr31
 	li	a2, ~(0x3f << 12)
 	and	a2, a1
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c
index 0c527f6..e132bfd 100644
--- a/arch/mips/kernel/irq-gic.c
+++ b/arch/mips/kernel/irq-gic.c
@@ -166,11 +166,13 @@ static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
 {
 	/* Setup Intr to Pin mapping */
 	if (pin & GIC_MAP_TO_NMI_MSK) {
+		int i;
+
 		GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
 		/* FIXME: hack to route NMI to all cpu's */
-		for (cpu = 0; cpu < NR_CPUS; cpu += 32) {
+		for (i = 0; i < NR_CPUS; i += 32) {
 			GICWRITE(GIC_REG_ADDR(SHARED,
-					  GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)),
+					  GIC_SH_MAP_TO_VPE_REG_OFF(intr, i)),
 				 0xffffffff);
 		}
 	} else {
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 9cd8cbf..962f0b0 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -29,7 +29,7 @@
 int kgdb_early_setup;
 #endif
 
-static unsigned long irq_map[NR_IRQS / BITS_PER_LONG];
+static DECLARE_BITMAP(irq_map, NR_IRQS);
 
 int allocate_irqno(void)
 {
diff --git a/arch/mips/kernel/jump_label.c b/arch/mips/kernel/jump_label.c
index 6001610..dda800e 100644
--- a/arch/mips/kernel/jump_label.c
+++ b/arch/mips/kernel/jump_label.c
@@ -18,31 +18,53 @@
 
 #ifdef HAVE_JUMP_LABEL
 
-#define J_RANGE_MASK ((1ul << 28) - 1)
+/*
+ * Define parameters for the standard MIPS and the microMIPS jump
+ * instruction encoding respectively:
+ *
+ * - the ISA bit of the target, either 0 or 1 respectively,
+ *
+ * - the amount the jump target address is shifted right to fit in the
+ *   immediate field of the machine instruction, either 2 or 1,
+ *
+ * - the mask determining the size of the jump region relative to the
+ *   delay-slot instruction, either 256MB or 128MB,
+ *
+ * - the jump target alignment, either 4 or 2 bytes.
+ */
+#define J_ISA_BIT	IS_ENABLED(CONFIG_CPU_MICROMIPS)
+#define J_RANGE_SHIFT	(2 - J_ISA_BIT)
+#define J_RANGE_MASK	((1ul << (26 + J_RANGE_SHIFT)) - 1)
+#define J_ALIGN_MASK	((1ul << J_RANGE_SHIFT) - 1)
 
 void arch_jump_label_transform(struct jump_entry *e,
 			       enum jump_label_type type)
 {
+	union mips_instruction *insn_p;
 	union mips_instruction insn;
-	union mips_instruction *insn_p =
-		(union mips_instruction *)(unsigned long)e->code;
 
-	/* Jump only works within a 256MB aligned region. */
-	BUG_ON((e->target & ~J_RANGE_MASK) != (e->code & ~J_RANGE_MASK));
+	insn_p = (union mips_instruction *)msk_isa16_mode(e->code);
+
+	/* Jump only works within an aligned region its delay slot is in. */
+	BUG_ON((e->target & ~J_RANGE_MASK) != ((e->code + 4) & ~J_RANGE_MASK));
 
-	/* Target must have 4 byte alignment. */
-	BUG_ON((e->target & 3) != 0);
+	/* Target must have the right alignment and ISA must be preserved. */
+	BUG_ON((e->target & J_ALIGN_MASK) != J_ISA_BIT);
 
 	if (type == JUMP_LABEL_ENABLE) {
-		insn.j_format.opcode = j_op;
-		insn.j_format.target = (e->target & J_RANGE_MASK) >> 2;
+		insn.j_format.opcode = J_ISA_BIT ? mm_j32_op : j_op;
+		insn.j_format.target = e->target >> J_RANGE_SHIFT;
 	} else {
 		insn.word = 0; /* nop */
 	}
 
 	get_online_cpus();
 	mutex_lock(&text_mutex);
-	*insn_p = insn;
+	if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) {
+		insn_p->halfword[0] = insn.word >> 16;
+		insn_p->halfword[1] = insn.word;
+	} else
+		*insn_p = insn;
 
 	flush_icache_range((unsigned long)insn_p,
 			   (unsigned long)insn_p + sizeof(*insn_p));
diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c
index 158467d..58afb42 100644
--- a/arch/mips/kernel/kprobes.c
+++ b/arch/mips/kernel/kprobes.c
@@ -207,7 +207,10 @@ void __kprobes arch_disarm_kprobe(struct kprobe *p)
 
 void __kprobes arch_remove_kprobe(struct kprobe *p)
 {
-	free_insn_slot(p->ainsn.insn, 0);
+	if (p->ainsn.insn) {
+		free_insn_slot(p->ainsn.insn, 0);
+		p->ainsn.insn = NULL;
+	}
 }
 
 static void save_previous_kprobe(struct kprobe_ctlblk *kcb)
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 922a554..440b100 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -208,7 +208,7 @@ SYSCALL_DEFINE6(32_ipc, u32, call, long, first, long, second, long, third,
 		err = compat_sys_shmctl(first, second, compat_ptr(ptr));
 		break;
 	default:
-		err = -EINVAL;
+		err = -ENOSYS;
 		break;
 	}
 
diff --git a/arch/mips/kernel/machine_kexec.c b/arch/mips/kernel/machine_kexec.c
index 85beb9b..27cf662 100644
--- a/arch/mips/kernel/machine_kexec.c
+++ b/arch/mips/kernel/machine_kexec.c
@@ -52,7 +52,9 @@ machine_kexec(struct kimage *image)
 	reboot_code_buffer =
 	  (unsigned long)page_address(image->control_code_page);
 
-	kexec_start_address = image->start;
+	kexec_start_address =
+		(unsigned long) phys_to_virt(image->start);
+
 	kexec_indirection_page =
 		(unsigned long) phys_to_virt(image->head & PAGE_MASK);
 
diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S
index 55eca41..4f8975d 100644
--- a/arch/mips/kernel/mcount.S
+++ b/arch/mips/kernel/mcount.S
@@ -46,11 +46,9 @@
 	PTR_L	a5, PT_R9(sp)
 	PTR_L	a6, PT_R10(sp)
 	PTR_L	a7, PT_R11(sp)
-	PTR_ADDIU	sp, PT_SIZE
-#else
-	PTR_ADDIU	sp, (PT_SIZE + 8)
 #endif
-.endm
+	PTR_ADDIU	sp, PT_SIZE
+	.endm
 
 	.macro RETURN_BACK
 	jr ra
@@ -65,11 +63,22 @@
 
 #ifdef CONFIG_DYNAMIC_FTRACE
 
+/*
+ * There are actually 2 entry points to this routine, _mcount and
+ * _mcount + 8. gcc generates a "jalr _mcount", "addui sp,sp,-8" at the
+ * start of every tracable function. Eventually all enabled, non-module
+ * functions are modified at run time to remove the usless stack adjust and
+ * they become "jalr _mcount+8", "nop".
+ */
 NESTED(ftrace_caller, PT_SIZE, ra)
 	.globl _mcount
 _mcount:
 	b	ftrace_stub
-	 nop
+#ifdef CONFIG_32BIT
+	addiu sp,sp,8
+#else
+	nop
+#endif
 	lw	t1, function_trace_stop
 	bnez	t1, ftrace_stub
 	 nop
diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c
index 57ba13e..3fc1691 100644
--- a/arch/mips/kernel/mips_ksyms.c
+++ b/arch/mips/kernel/mips_ksyms.c
@@ -5,7 +5,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1996, 97, 98, 99, 2000, 01, 03, 04, 05 by Ralf Baechle
+ * Copyright (C) 1996, 97, 98, 99, 2000, 01, 03, 04, 05, 12 by Ralf Baechle
  * Copyright (C) 1999, 2000, 01 Silicon Graphics, Inc.
  */
 #include <linux/interrupt.h>
@@ -35,6 +35,12 @@ EXPORT_SYMBOL(memmove);
 EXPORT_SYMBOL(kernel_thread);
 
 /*
+ * Functions that operate on entire pages.  Mostly used by memory management.
+ */
+EXPORT_SYMBOL(clear_page);
+EXPORT_SYMBOL(copy_page);
+
+/*
  * Userspace access stuff.
  */
 EXPORT_SYMBOL(__copy_user);
diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c
index a5066b1..4f8c3cb 100644
--- a/arch/mips/kernel/module.c
+++ b/arch/mips/kernel/module.c
@@ -39,8 +39,6 @@ struct mips_hi16 {
 	Elf_Addr value;
 };
 
-static struct mips_hi16 *mips_hi16_list;
-
 static LIST_HEAD(dbe_list);
 static DEFINE_SPINLOCK(dbe_lock);
 
@@ -128,8 +126,8 @@ static int apply_r_mips_hi16_rel(struct module *me, u32 *location, Elf_Addr v)
 
 	n->addr = (Elf_Addr *)location;
 	n->value = v;
-	n->next = mips_hi16_list;
-	mips_hi16_list = n;
+	n->next = me->arch.r_mips_hi16_list;
+	me->arch.r_mips_hi16_list = n;
 
 	return 0;
 }
@@ -142,18 +140,28 @@ static int apply_r_mips_hi16_rela(struct module *me, u32 *location, Elf_Addr v)
 	return 0;
 }
 
+static void free_relocation_chain(struct mips_hi16 *l)
+{
+	struct mips_hi16 *next;
+
+	while (l) {
+		next = l->next;
+		kfree(l);
+		l = next;
+	}
+}
+
 static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v)
 {
 	unsigned long insnlo = *location;
+	struct mips_hi16 *l;
 	Elf_Addr val, vallo;
 
 	/* Sign extend the addend we extract from the lo insn.  */
 	vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000;
 
-	if (mips_hi16_list != NULL) {
-		struct mips_hi16 *l;
-
-		l = mips_hi16_list;
+	if (me->arch.r_mips_hi16_list != NULL) {
+		l = me->arch.r_mips_hi16_list;
 		while (l != NULL) {
 			struct mips_hi16 *next;
 			unsigned long insn;
@@ -188,7 +196,7 @@ static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v)
 			l = next;
 		}
 
-		mips_hi16_list = NULL;
+		me->arch.r_mips_hi16_list = NULL;
 	}
 
 	/*
@@ -201,6 +209,9 @@ static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v)
 	return 0;
 
 out_danger:
+	free_relocation_chain(l);
+	me->arch.r_mips_hi16_list = NULL;
+
 	pr_err("module %s: dangerous R_MIPS_LO16 REL relocation\n", me->name);
 
 	return -ENOEXEC;
@@ -273,6 +284,7 @@ int apply_relocate(Elf_Shdr *sechdrs, const char *strtab,
 	pr_debug("Applying relocate section %u to %u\n", relsec,
 	       sechdrs[relsec].sh_info);
 
+	me->arch.r_mips_hi16_list = NULL;
 	for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
 		/* This is where to make the change */
 		location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
@@ -296,6 +308,19 @@ int apply_relocate(Elf_Shdr *sechdrs, const char *strtab,
 			return res;
 	}
 
+	/*
+	 * Normally the hi16 list should be deallocated at this point.  A
+	 * malformed binary however could contain a series of R_MIPS_HI16
+	 * relocations not followed by a R_MIPS_LO16 relocation.  In that
+	 * case, free up the list and return an error.
+	 */
+	if (me->arch.r_mips_hi16_list) {
+		free_relocation_chain(me->arch.r_mips_hi16_list);
+		me->arch.r_mips_hi16_list = NULL;
+
+		return -ENOEXEC;
+	}
+
 	return 0;
 }
 
diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S
index ce89c80..7c90e72 100644
--- a/arch/mips/kernel/octeon_switch.S
+++ b/arch/mips/kernel/octeon_switch.S
@@ -31,7 +31,7 @@
 
 /*
  * task_struct *resume(task_struct *prev, task_struct *next,
- *                     struct thread_info *next_ti)
+ *                     struct thread_info *next_ti, int usedfpu)
  */
 	.align	7
 	LEAF(resume)
@@ -99,6 +99,13 @@
 	mtc0	t0, $11,7 	/* CvmMemCtl */
 #endif
 3:
+
+#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
+	PTR_LA	t8, __stack_chk_guard
+	LONG_L	t9, TASK_STACK_CANARY(a1)
+	LONG_S	t9, 0(t8)
+#endif
+
 	/*
 	 * The order of restoring the registers takes care of the race
 	 * updating $28, $29 and kernelsp without disabling ints.
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 52f60e5..95763f3 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -28,6 +28,8 @@
 #include <asm/time.h> /* For perf_irq */
 
 #define MIPS_MAX_HWEVENTS 4
+#define MIPS_TCS_PER_COUNTER 2
+#define MIPS_CPUID_TO_COUNTER_MASK (MIPS_TCS_PER_COUNTER - 1)
 
 struct cpu_hw_events {
 	/* Array of events on this cpu. */
@@ -78,7 +80,6 @@ struct mips_perf_event {
 static struct mips_perf_event raw_event;
 static DEFINE_MUTEX(raw_event_mutex);
 
-#define UNSUPPORTED_PERF_EVENT_ID 0xffffffff
 #define C(x) PERF_COUNT_HW_CACHE_##x
 
 struct mips_pmu {
@@ -109,13 +110,20 @@ static struct mips_pmu mipspmu;
 #define M_PERFCTL_INTERRUPT_ENABLE	(1      <<  4)
 #define M_PERFCTL_EVENT(event)		(((event) & 0x3ff)  << 5)
 #define M_PERFCTL_VPEID(vpe)		((vpe)    << 16)
+
+#ifdef CONFIG_CPU_BMIPS5000
+#define M_PERFCTL_MT_EN(filter)		0
+#else /* !CONFIG_CPU_BMIPS5000 */
 #define M_PERFCTL_MT_EN(filter)		((filter) << 20)
+#endif /* CONFIG_CPU_BMIPS5000 */
+
 #define    M_TC_EN_ALL			M_PERFCTL_MT_EN(0)
 #define    M_TC_EN_VPE			M_PERFCTL_MT_EN(1)
 #define    M_TC_EN_TC			M_PERFCTL_MT_EN(2)
 #define M_PERFCTL_TCID(tcid)		((tcid)   << 22)
 #define M_PERFCTL_WIDE			(1      << 30)
 #define M_PERFCTL_MORE			(1      << 31)
+#define M_PERFCTL_TC			(1      << 30)
 
 #define M_PERFCTL_COUNT_EVENT_WHENEVER	(M_PERFCTL_EXL |		\
 					M_PERFCTL_KERNEL |		\
@@ -131,21 +139,21 @@ static struct mips_pmu mipspmu;
 #define M_PERFCTL_EVENT_MASK		0xfe0
 
 
-#ifdef CONFIG_MIPS_MT_SMP
+#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
 static int cpu_has_mipsmt_pertccounters;
 
 static DEFINE_RWLOCK(pmuint_rwlock);
 
+#if defined(CONFIG_CPU_BMIPS5000)
+#define vpe_id()	(cpu_has_mipsmt_pertccounters ? \
+			 0 : (smp_processor_id() & MIPS_CPUID_TO_COUNTER_MASK))
+#else
 /*
  * FIXME: For VSMP, vpe_id() is redefined for Perf-events, because
  * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs.
  */
-#if defined(CONFIG_HW_PERF_EVENTS)
-#define vpe_id()	(cpu_has_mipsmt_pertccounters ? \
-			0 : smp_processor_id())
-#else
 #define vpe_id()	(cpu_has_mipsmt_pertccounters ? \
-			0 : cpu_data[smp_processor_id()].vpe_id)
+			 0 : smp_processor_id())
 #endif
 
 /* Copied from op_model_mipsxx.c */
@@ -162,10 +170,10 @@ static unsigned int counters_total_to_per_cpu(unsigned int counters)
 	return counters >> vpe_shift();
 }
 
-#else /* !CONFIG_MIPS_MT_SMP */
+#else /* !CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */
 #define vpe_id()	0
 
-#endif /* CONFIG_MIPS_MT_SMP */
+#endif /* CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */
 
 static void resume_local_counters(void);
 static void pause_local_counters(void);
@@ -340,6 +348,11 @@ static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
 		(evt->config_base & M_PERFCTL_CONFIG_MASK) |
 		/* Make sure interrupt enabled. */
 		M_PERFCTL_INTERRUPT_ENABLE;
+	if (IS_ENABLED(CONFIG_CPU_BMIPS5000))
+		/* enable the counter for the calling thread */
+		cpuc->saved_ctrl[idx] |=
+			(1 << (12 + vpe_id())) | M_PERFCTL_TC;
+
 	/*
 	 * We do not actually let the counter run. Leave it until start().
 	 */
@@ -509,7 +522,7 @@ static void mipspmu_read(struct perf_event *event)
 
 static void mipspmu_enable(struct pmu *pmu)
 {
-#ifdef CONFIG_MIPS_MT_SMP
+#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
 	write_unlock(&pmuint_rwlock);
 #endif
 	resume_local_counters();
@@ -529,7 +542,7 @@ static void mipspmu_enable(struct pmu *pmu)
 static void mipspmu_disable(struct pmu *pmu)
 {
 	pause_local_counters();
-#ifdef CONFIG_MIPS_MT_SMP
+#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
 	write_lock(&pmuint_rwlock);
 #endif
 }
@@ -545,7 +558,7 @@ static int mipspmu_get_irq(void)
 	if (mipspmu.irq >= 0) {
 		/* Request my own irq handler. */
 		err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq,
-			IRQF_PERCPU | IRQF_NOBALANCING,
+			IRQF_PERCPU | IRQF_NOBALANCING | IRQF_NO_THREAD,
 			"mips_perf_pmu", NULL);
 		if (err) {
 			pr_warning("Unable to request IRQ%d for MIPS "
@@ -664,13 +677,10 @@ static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev)
 
 static const struct mips_perf_event *mipspmu_map_general_event(int idx)
 {
-	const struct mips_perf_event *pev;
-
-	pev = ((*mipspmu.general_event_map)[idx].event_id ==
-		UNSUPPORTED_PERF_EVENT_ID ? ERR_PTR(-EOPNOTSUPP) :
-		&(*mipspmu.general_event_map)[idx]);
 
-	return pev;
+	if ((*mipspmu.general_event_map)[idx].cntr_mask == 0)
+		return ERR_PTR(-EOPNOTSUPP);
+	return &(*mipspmu.general_event_map)[idx];
 }
 
 static const struct mips_perf_event *mipspmu_map_cache_event(u64 config)
@@ -695,7 +705,7 @@ static const struct mips_perf_event *mipspmu_map_cache_event(u64 config)
 					[cache_op]
 					[cache_result]);
 
-	if (pev->event_id == UNSUPPORTED_PERF_EVENT_ID)
+	if (pev->cntr_mask == 0)
 		return ERR_PTR(-EOPNOTSUPP);
 
 	return pev;
@@ -800,11 +810,8 @@ static const struct mips_perf_event mipsxxcore_event_map
 				[PERF_COUNT_HW_MAX] = {
 	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
-	[PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID },
-	[PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID },
 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
 	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
-	[PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
 };
 
 /* 74K core has different branch event code. */
@@ -812,11 +819,8 @@ static const struct mips_perf_event mipsxx74Kcore_event_map
 				[PERF_COUNT_HW_MAX] = {
 	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
-	[PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID },
-	[PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID },
 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
 	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
-	[PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
 };
 
 static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = {
@@ -829,6 +833,13 @@ static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = {
 	[PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL },
 };
 
+static const struct mips_perf_event bmips5000_event_map
+				[PERF_COUNT_HW_MAX] = {
+	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T },
+	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
+	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
+};
+
 /* 24K/34K/1004K cores can share the same cache event map. */
 static const struct mips_perf_event mipsxxcore_cache_map
 				[PERF_COUNT_HW_CACHE_MAX]
@@ -849,10 +860,6 @@ static const struct mips_perf_event mipsxxcore_cache_map
 		[C(RESULT_ACCESS)]	= { 0x0a, CNTR_EVEN, T },
 		[C(RESULT_MISS)]	= { 0x0b, CNTR_EVEN | CNTR_ODD, T },
 	},
-	[C(OP_PREFETCH)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
 },
 [C(L1I)] = {
 	[C(OP_READ)] = {
@@ -869,7 +876,6 @@ static const struct mips_perf_event mipsxxcore_cache_map
 		 * Note that MIPS has only "hit" events countable for
 		 * the prefetch operation.
 		 */
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
 	},
 },
 [C(LL)] = {
@@ -881,10 +887,6 @@ static const struct mips_perf_event mipsxxcore_cache_map
 		[C(RESULT_ACCESS)]	= { 0x15, CNTR_ODD, P },
 		[C(RESULT_MISS)]	= { 0x16, CNTR_EVEN, P },
 	},
-	[C(OP_PREFETCH)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
 },
 [C(DTLB)] = {
 	[C(OP_READ)] = {
@@ -895,10 +897,6 @@ static const struct mips_perf_event mipsxxcore_cache_map
 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
 	},
-	[C(OP_PREFETCH)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
 },
 [C(ITLB)] = {
 	[C(OP_READ)] = {
@@ -909,10 +907,6 @@ static const struct mips_perf_event mipsxxcore_cache_map
 		[C(RESULT_ACCESS)]	= { 0x05, CNTR_EVEN, T },
 		[C(RESULT_MISS)]	= { 0x05, CNTR_ODD, T },
 	},
-	[C(OP_PREFETCH)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
 },
 [C(BPU)] = {
 	/* Using the same code for *HW_BRANCH* */
@@ -924,24 +918,6 @@ static const struct mips_perf_event mipsxxcore_cache_map
 		[C(RESULT_ACCESS)]	= { 0x02, CNTR_EVEN, T },
 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
 	},
-	[C(OP_PREFETCH)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
-},
-[C(NODE)] = {
-	[C(OP_READ)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
-	[C(OP_WRITE)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
-	[C(OP_PREFETCH)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
 },
 };
 
@@ -965,10 +941,6 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map
 		[C(RESULT_ACCESS)]	= { 0x17, CNTR_ODD, T },
 		[C(RESULT_MISS)]	= { 0x18, CNTR_ODD, T },
 	},
-	[C(OP_PREFETCH)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
 },
 [C(L1I)] = {
 	[C(OP_READ)] = {
@@ -985,7 +957,6 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map
 		 * Note that MIPS has only "hit" events countable for
 		 * the prefetch operation.
 		 */
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
 	},
 },
 [C(LL)] = {
@@ -997,25 +968,6 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map
 		[C(RESULT_ACCESS)]	= { 0x1c, CNTR_ODD, P },
 		[C(RESULT_MISS)]	= { 0x1d, CNTR_EVEN | CNTR_ODD, P },
 	},
-	[C(OP_PREFETCH)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
-},
-[C(DTLB)] = {
-	/* 74K core does not have specific DTLB events. */
-	[C(OP_READ)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
-	[C(OP_WRITE)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
-	[C(OP_PREFETCH)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
 },
 [C(ITLB)] = {
 	[C(OP_READ)] = {
@@ -1026,10 +978,6 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map
 		[C(RESULT_ACCESS)]	= { 0x04, CNTR_EVEN, T },
 		[C(RESULT_MISS)]	= { 0x04, CNTR_ODD, T },
 	},
-	[C(OP_PREFETCH)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
 },
 [C(BPU)] = {
 	/* Using the same code for *HW_BRANCH* */
@@ -1041,23 +989,64 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map
 		[C(RESULT_ACCESS)]	= { 0x27, CNTR_EVEN, T },
 		[C(RESULT_MISS)]	= { 0x27, CNTR_ODD, T },
 	},
-	[C(OP_PREFETCH)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+},
+};
+
+/* BMIPS5000 */
+static const struct mips_perf_event bmips5000_cache_map
+				[PERF_COUNT_HW_CACHE_MAX]
+				[PERF_COUNT_HW_CACHE_OP_MAX]
+				[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+[C(L1D)] = {
+	/*
+	 * Like some other architectures (e.g. ARM), the performance
+	 * counters don't differentiate between read and write
+	 * accesses/misses, so this isn't strictly correct, but it's the
+	 * best we can do. Writes and reads get combined.
+	 */
+	[C(OP_READ)] = {
+		[C(RESULT_ACCESS)]	= { 12, CNTR_EVEN, T },
+		[C(RESULT_MISS)]	= { 12, CNTR_ODD, T },
+	},
+	[C(OP_WRITE)] = {
+		[C(RESULT_ACCESS)]	= { 12, CNTR_EVEN, T },
+		[C(RESULT_MISS)]	= { 12, CNTR_ODD, T },
 	},
 },
-[C(NODE)] = {
+[C(L1I)] = {
 	[C(OP_READ)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+		[C(RESULT_ACCESS)]	= { 10, CNTR_EVEN, T },
+		[C(RESULT_MISS)]	= { 10, CNTR_ODD, T },
 	},
 	[C(OP_WRITE)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+		[C(RESULT_ACCESS)]	= { 10, CNTR_EVEN, T },
+		[C(RESULT_MISS)]	= { 10, CNTR_ODD, T },
 	},
 	[C(OP_PREFETCH)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
+		[C(RESULT_ACCESS)]	= { 23, CNTR_EVEN, T },
+		/*
+		 * Note that MIPS has only "hit" events countable for
+		 * the prefetch operation.
+		 */
+	},
+},
+[C(LL)] = {
+	[C(OP_READ)] = {
+		[C(RESULT_ACCESS)]	= { 28, CNTR_EVEN, P },
+		[C(RESULT_MISS)]	= { 28, CNTR_ODD, P },
+	},
+	[C(OP_WRITE)] = {
+		[C(RESULT_ACCESS)]	= { 28, CNTR_EVEN, P },
+		[C(RESULT_MISS)]	= { 28, CNTR_ODD, P },
+	},
+},
+[C(BPU)] = {
+	/* Using the same code for *HW_BRANCH* */
+	[C(OP_READ)] = {
+		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
+	},
+	[C(OP_WRITE)] = {
+		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
 	},
 },
 };
@@ -1074,39 +1063,14 @@ static const struct mips_perf_event octeon_cache_map
 	},
 	[C(OP_WRITE)] = {
 		[C(RESULT_ACCESS)]	= { 0x30, CNTR_ALL },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
-	[C(OP_PREFETCH)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
 	},
 },
 [C(L1I)] = {
 	[C(OP_READ)] = {
 		[C(RESULT_ACCESS)]	= { 0x18, CNTR_ALL },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
-	[C(OP_WRITE)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
 	},
 	[C(OP_PREFETCH)] = {
 		[C(RESULT_ACCESS)]	= { 0x19, CNTR_ALL },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
-},
-[C(LL)] = {
-	[C(OP_READ)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
-	[C(OP_WRITE)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
-	[C(OP_PREFETCH)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
 	},
 },
 [C(DTLB)] = {
@@ -1115,46 +1079,16 @@ static const struct mips_perf_event octeon_cache_map
 	 * read and write.
 	 */
 	[C(OP_READ)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
 		[C(RESULT_MISS)]	= { 0x35, CNTR_ALL },
 	},
 	[C(OP_WRITE)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
 		[C(RESULT_MISS)]	= { 0x35, CNTR_ALL },
 	},
-	[C(OP_PREFETCH)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
 },
 [C(ITLB)] = {
 	[C(OP_READ)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
 		[C(RESULT_MISS)]	= { 0x37, CNTR_ALL },
 	},
-	[C(OP_WRITE)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
-	[C(OP_PREFETCH)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
-},
-[C(BPU)] = {
-	/* Using the same code for *HW_BRANCH* */
-	[C(OP_READ)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
-	[C(OP_WRITE)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
-	[C(OP_PREFETCH)] = {
-		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },
-	},
 },
 };
 
@@ -1304,7 +1238,7 @@ static int mipsxx_pmu_handle_shared_irq(void)
 	int handled = IRQ_NONE;
 	struct pt_regs *regs;
 
-	if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
+	if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI))
 		return handled;
 	/*
 	 * First we pause the local counters, so that when we are locked
@@ -1314,7 +1248,7 @@ static int mipsxx_pmu_handle_shared_irq(void)
 	 * See also mipsxx_pmu_start().
 	 */
 	pause_local_counters();
-#ifdef CONFIG_MIPS_MT_SMP
+#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
 	read_lock(&pmuint_rwlock);
 #endif
 
@@ -1346,7 +1280,7 @@ static int mipsxx_pmu_handle_shared_irq(void)
 	if (handled == IRQ_HANDLED)
 		irq_work_run();
 
-#ifdef CONFIG_MIPS_MT_SMP
+#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
 	read_unlock(&pmuint_rwlock);
 #endif
 	resume_local_counters();
@@ -1391,6 +1325,11 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
 #define IS_RANGE_V_1004K_EVENT(r)	((r) == 47)
 #endif
 
+/* BMIPS5000 */
+#define IS_BOTH_COUNTERS_BMIPS5000_EVENT(b)				\
+	((b) == 0 || (b) == 1)
+
+
 /*
  * User can use 0-255 raw events, where 0-127 for the events of even
  * counters, and 128-255 for odd counters. Note that bit 7 is used to
@@ -1461,6 +1400,12 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
 			raw_event.range = T;
 #endif
 		break;
+	case CPU_BMIPS5000:
+		if (IS_BOTH_COUNTERS_BMIPS5000_EVENT(base_id))
+			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+		else
+			raw_event.cntr_mask =
+				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
 	}
 
 	return &raw_event;
@@ -1513,7 +1458,7 @@ init_hw_perf_events(void)
 		return -ENODEV;
 	}
 
-#ifdef CONFIG_MIPS_MT_SMP
+#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
 	cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
 	if (!cpu_has_mipsmt_pertccounters)
 		counters = counters_total_to_per_cpu(counters);
@@ -1566,6 +1511,11 @@ init_hw_perf_events(void)
 		mipspmu.cache_event_map = &octeon_cache_map;
 		mipspmu.map_raw_event = octeon_pmu_map_raw_event;
 		break;
+	case CPU_BMIPS5000:
+		mipspmu.name = "BMIPS5000";
+		mipspmu.general_event_map = &bmips5000_event_map;
+		mipspmu.cache_event_map = &bmips5000_cache_map;
+		break;
 	default:
 		pr_cont("Either hardware does not support performance "
 			"counters, or not yet implemented.\n");
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index f8b2c59..a6dc0fb 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -14,6 +14,10 @@
 #include <asm/processor.h>
 #include <asm/mips_machine.h>
 
+#ifdef CONFIG_BRCMSTB
+#include <linux/brcmstb/brcmapi.h>
+#endif
+
 unsigned int vced_count, vcei_count;
 
 static int show_cpuinfo(struct seq_file *m, void *v)
@@ -48,6 +52,11 @@ static int show_cpuinfo(struct seq_file *m, void *v)
 	seq_printf(m, "BogoMIPS\t\t: %u.%02u\n",
 	              cpu_data[n].udelay_val / (500000/HZ),
 	              (cpu_data[n].udelay_val / (5000/HZ)) % 100);
+#ifdef CONFIG_BRCMSTB
+	/* for Oprofile opreport */
+	seq_printf(m, "cpu MHz\t\t\t: %lu.%03lu\n", brcm_adj_cpu_khz / 1000,
+		brcm_adj_cpu_khz % 1000);
+#endif
 	seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
 	seq_printf(m, "microsecond timers\t: %s\n",
 	              cpu_has_counter ? "yes" : "no");
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 69b17a9..093470e 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -248,6 +248,12 @@ long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
 	return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
 }
 
+#ifdef CONFIG_CC_STACKPROTECTOR
+#include <linux/stackprotector.h>
+unsigned long __stack_chk_guard __read_mostly;
+EXPORT_SYMBOL(__stack_chk_guard);
+#endif
+
 /*
  *
  */
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index 7c24c29..900d9a9 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -161,6 +161,7 @@ int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
 		__get_user(fregs[i], i + (__u64 __user *) data);
 
 	__get_user(child->thread.fpu.fcr31, data + 64);
+	child->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
 
 	/* FIR may not be written.  */
 
@@ -451,7 +452,7 @@ long arch_ptrace(struct task_struct *child, long request,
 			break;
 #endif
 		case FPC_CSR:
-			child->thread.fpu.fcr31 = data;
+			child->thread.fpu.fcr31 = data & ~FPU_CSR_ALL_X;
 			break;
 		case DSP_BASE ... DSP_BASE + 5: {
 			dspreg_t *dregs;
diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S
index 2938983..c965778 100644
--- a/arch/mips/kernel/r2300_switch.S
+++ b/arch/mips/kernel/r2300_switch.S
@@ -43,7 +43,7 @@
 
 /*
  * task_struct *resume(task_struct *prev, task_struct *next,
- *                     struct thread_info *next_ti) )
+ *                     struct thread_info *next_ti, int usedfpu)
  */
 LEAF(resume)
 	mfc0	t1, CP0_STATUS
@@ -51,18 +51,9 @@ LEAF(resume)
 	cpu_save_nonscratch a0
 	sw	ra, THREAD_REG31(a0)
 
-	/*
-	 * check if we need to save FPU registers
-	 */
-	lw	t3, TASK_THREAD_INFO(a0)
-	lw	t0, TI_FLAGS(t3)
-	li	t1, _TIF_USEDFPU
-	and	t2, t0, t1
-	beqz	t2, 1f
-	nor	t1, zero, t1
+	beqz	a3, 1f
 
-	and	t0, t0, t1
-	sw	t0, TI_FLAGS(t3)
+	PTR_L	t3, TASK_THREAD_INFO(a0)
 
 	/*
 	 * clear saved user stack CU1 bit
@@ -75,6 +66,13 @@ LEAF(resume)
 	fpu_save_single a0, t0			# clobbers t0
 
 1:
+
+#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
+	PTR_LA	t8, __stack_chk_guard
+	LONG_L	t9, TASK_STACK_CANARY(a1)
+	LONG_S	t9, 0(t8)
+#endif
+
 	/*
 	 * The order of restoring the registers takes care of the race
 	 * updating $28, $29 and kernelsp without disabling ints.
diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
index 55ffe14..72a29b7 100644
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -33,6 +33,8 @@
 	.set	mips3
 
 LEAF(_save_fp_context)
+	.set	push
+	SET_HARDFLOAT
 	cfc1	t1, fcr31
 
 #ifdef CONFIG_64BIT
@@ -75,6 +77,7 @@ LEAF(_save_fp_context)
 	EX	sw t1, SC_FPC_CSR(a0)
 	jr	ra
 	 li	v0, 0					# success
+	.set	pop
 	END(_save_fp_context)
 
 #ifdef CONFIG_MIPS32_COMPAT
@@ -113,6 +116,8 @@ LEAF(_save_fp_context32)
  *  - cp1 status/control register
  */
 LEAF(_restore_fp_context)
+	.set	push
+	SET_HARDFLOAT
 	EX	lw t0, SC_FPC_CSR(a0)
 #ifdef CONFIG_64BIT
 	EX	ldc1 $f1, SC_FPREGS+8(a0)
@@ -151,6 +156,7 @@ LEAF(_restore_fp_context)
 	ctc1	t0, fcr31
 	jr	ra
 	 li	v0, 0					# success
+	.set	pop
 	END(_restore_fp_context)
 
 #ifdef CONFIG_MIPS32_COMPAT
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 9414f93..d839b76 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -41,7 +41,7 @@
 
 /*
  * task_struct *resume(task_struct *prev, task_struct *next,
- *                     struct thread_info *next_ti)
+ *                     struct thread_info *next_ti, int usedfpu)
  */
 	.align	5
 	LEAF(resume)
@@ -53,16 +53,10 @@
 	/*
 	 * check if we need to save FPU registers
 	 */
-	PTR_L	t3, TASK_THREAD_INFO(a0)
-	LONG_L	t0, TI_FLAGS(t3)
-	li	t1, _TIF_USEDFPU
-	and	t2, t0, t1
-	beqz	t2, 1f
-	nor	t1, zero, t1
 
-	and	t0, t0, t1
-	LONG_S	t0, TI_FLAGS(t3)
+	beqz    a3, 1f
 
+	PTR_L	t3, TASK_THREAD_INFO(a0)
 	/*
 	 * clear saved user stack CU1 bit
 	 */
@@ -75,6 +69,12 @@
 						# clobbers t1
 1:
 
+#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
+	PTR_LA	t8, __stack_chk_guard
+	LONG_L	t9, TASK_STACK_CANARY(a1)
+	LONG_S	t9, 0(t8)
+#endif
+
 	/*
 	 * The order of restoring the registers takes care of the race
 	 * updating $28, $29 and kernelsp without disabling ints.
@@ -152,6 +152,9 @@ LEAF(_restore_fp)
 
 #define FPU_DEFAULT  0x00000000
 
+	.set push
+	SET_HARDFLOAT
+
 LEAF(_init_fpu)
 #ifdef CONFIG_MIPS_MT_SMTC
 	/* Rather than manipulate per-VPE Status, set per-TC bit in TCStatus */
@@ -250,3 +253,5 @@ LEAF(_init_fpu)
 #endif
 	jr	ra
 	END(_init_fpu)
+
+	.set pop
diff --git a/arch/mips/kernel/relocate_kernel.S b/arch/mips/kernel/relocate_kernel.S
index 87481f9..80c2a24 100644
--- a/arch/mips/kernel/relocate_kernel.S
+++ b/arch/mips/kernel/relocate_kernel.S
@@ -22,6 +22,12 @@ process_entry:
 	PTR_L		s2, (s0)
 	PTR_ADD		s0, s0, SZREG
 
+	/*
+	 * In case of a kdump/crash kernel, the indirection page is not
+	 * populated as the kernel is directly copied to a reserved location
+	 */
+	beqz		s2, done
+
 	/* destination page */
 	and		s3, s2, 0x1
 	beq		s3, zero, 1f
diff --git a/arch/mips/kernel/reset.c b/arch/mips/kernel/reset.c
index 07fc524..9060ac0 100644
--- a/arch/mips/kernel/reset.c
+++ b/arch/mips/kernel/reset.c
@@ -20,7 +20,13 @@
  * functions.
  */
 void (*_machine_restart)(char *command);
+
+EXPORT_SYMBOL(_machine_restart);
+
 void (*_machine_halt)(void);
+
+EXPORT_SYMBOL(_machine_halt);
+
 void (*pm_power_off)(void);
 
 EXPORT_SYMBOL(pm_power_off);
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index a632bc1..532a330 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -52,7 +52,7 @@ NESTED(handle_sys, PT_SIZE, sp)
 
 stack_done:
 	lw	t0, TI_FLAGS($28)	# syscall tracing enabled?
-	li	t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT
+	li	t1, _TIF_WORK_SYSCALL_ENTRY
 	and	t0, t1
 	bnez	t0, syscall_trace_entry	# -> yes
 
@@ -192,6 +192,7 @@ illegal_syscall:
 	sll	t1, t0, 3
 	beqz	v0, einval
 	lw	t2, sys_call_table(t1)		# syscall routine
+	sw	a0, PT_R2(sp)			# call routine directly on restart
 
 	/* Some syscalls like execve get their arguments from struct pt_regs
 	   and claim zero arguments in the syscall table. Thus we have to
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 3b5a5e9..53e65ff 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -54,7 +54,7 @@ NESTED(handle_sys64, PT_SIZE, sp)
 
 	sd	a3, PT_R26(sp)		# save a3 for syscall restarting
 
-	li	t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT
+	li	t1, _TIF_WORK_SYSCALL_ENTRY
 	LONG_L	t0, TI_FLAGS($28)	# syscall tracing enabled?
 	and	t0, t1, t0
 	bnez	t0, syscall_trace_entry
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index 6be6f70..51fd34b 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -53,7 +53,7 @@ NESTED(handle_sysn32, PT_SIZE, sp)
 
 	sd	a3, PT_R26(sp)		# save a3 for syscall restarting
 
-	li	t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT
+	li	t1, _TIF_WORK_SYSCALL_ENTRY
 	LONG_L	t0, TI_FLAGS($28)	# syscall tracing enabled?
 	and	t0, t1, t0
 	bnez	t0, n32_syscall_trace_entry
@@ -366,7 +366,7 @@ EXPORT(sysn32_call_table)
 	PTR	sys_ni_syscall			/* available, was setaltroot */
 	PTR	sys_add_key
 	PTR	sys_request_key
-	PTR	sys_keyctl			/* 6245 */
+	PTR	compat_sys_keyctl		/* 6245 */
 	PTR	sys_set_thread_area
 	PTR	sys_inotify_init
 	PTR	sys_inotify_add_watch
@@ -408,14 +408,14 @@ EXPORT(sysn32_call_table)
 	PTR	sys_timerfd_create
 	PTR	compat_sys_timerfd_gettime	/* 6285 */
 	PTR	compat_sys_timerfd_settime
-	PTR	sys_signalfd4
+	PTR	compat_sys_signalfd4
 	PTR	sys_eventfd2
 	PTR	sys_epoll_create1
 	PTR	sys_dup3			/* 6290 */
 	PTR	sys_pipe2
 	PTR	sys_inotify_init1
-	PTR	sys_preadv
-	PTR	sys_pwritev
+	PTR	compat_sys_preadv
+	PTR	compat_sys_pwritev
 	PTR	compat_sys_rt_tgsigqueueinfo	/* 6295 */
 	PTR	sys_perf_event_open
 	PTR	sys_accept4
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 5422855..b5f1c09 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -81,7 +81,7 @@ NESTED(handle_sys, PT_SIZE, sp)
 	PTR	4b, bad_stack
 	.previous
 
-	li	t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT
+	li	t1, _TIF_WORK_SYSCALL_ENTRY
 	LONG_L	t0, TI_FLAGS($28)	# syscall tracing enabled?
 	and	t0, t1, t0
 	bnez	t0, trace_a_syscall
@@ -180,6 +180,7 @@ LEAF(sys32_syscall)
 	dsll	t1, t0, 3
 	beqz	v0, einval
 	ld	t2, sys_call_table(t1)		# syscall routine
+	sd	a0, PT_R2(sp)		# call routine directly on restart
 
 	move	a0, a1			# shift argument registers
 	move	a1, a2
@@ -376,7 +377,7 @@ sys_call_table:
 	PTR	sys_connect			/* 4170 */
 	PTR	sys_getpeername
 	PTR	sys_getsockname
-	PTR	sys_getsockopt
+	PTR	compat_sys_getsockopt
 	PTR	sys_listen
 	PTR	compat_sys_recv			/* 4175 */
 	PTR	compat_sys_recvfrom
@@ -485,7 +486,7 @@ sys_call_table:
 	PTR	sys_ni_syscall			/* available, was setaltroot */
 	PTR	sys_add_key			/* 4280 */
 	PTR	sys_request_key
-	PTR	sys_keyctl
+	PTR	compat_sys_keyctl
 	PTR	sys_set_thread_area
 	PTR	sys_inotify_init
 	PTR	sys_inotify_add_watch		/* 4285 */
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index c504b21..fd7aa60 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -33,6 +33,10 @@
 #include <asm/smp-ops.h>
 #include <asm/prom.h>
 
+#ifdef CONFIG_BRCMSTB
+#include <linux/brcmstb/brcmapi.h>
+#endif
+
 struct cpuinfo_mips cpu_data[NR_CPUS] __read_mostly;
 
 EXPORT_SYMBOL(cpu_data);
@@ -79,7 +83,7 @@ static struct resource data_resource = { .name = "Kernel data", };
 void __init add_memory_region(phys_t start, phys_t size, long type)
 {
 	int x = boot_mem_map.nr_map;
-	struct boot_mem_map_entry *prev = boot_mem_map.map + x - 1;
+	int i;
 
 	/* Sanity check */
 	if (start + size < start) {
@@ -88,15 +92,29 @@ void __init add_memory_region(phys_t start, phys_t size, long type)
 	}
 
 	/*
-	 * Try to merge with previous entry if any.  This is far less than
-	 * perfect but is sufficient for most real world cases.
+	 * Try to merge with existing entry, if any.
 	 */
-	if (x && prev->addr + prev->size == start && prev->type == type) {
-		prev->size += size;
+	for (i = 0; i < boot_mem_map.nr_map; i++) {
+		struct boot_mem_map_entry *entry = boot_mem_map.map + i;
+		unsigned long top;
+
+		if (entry->type != type)
+			continue;
+
+		if (start + size < entry->addr)
+			continue;			/* no overlap */
+
+		if (entry->addr + entry->size < start)
+			continue;			/* no overlap */
+
+		top = max(entry->addr + entry->size, start + size);
+		entry->addr = min(entry->addr, start);
+		entry->size = top - entry->addr;
+
 		return;
 	}
 
-	if (x == BOOT_MEM_MAP_MAX) {
+	if (boot_mem_map.nr_map == BOOT_MEM_MAP_MAX) {
 		pr_err("Ooops! Too many entries in the memory map!\n");
 		return;
 	}
@@ -401,8 +419,12 @@ static void __init bootmem_init(void)
 		size = end - start;
 
 		/* Register lowmem ranges */
+#ifdef CONFIG_BRCMSTB
+		/* carve out space for bmem */
+		brcm_free_bootmem(PFN_PHYS(start), size << PAGE_SHIFT);
+#else
 		free_bootmem(PFN_PHYS(start), size << PAGE_SHIFT);
-		memory_present(0, start, end);
+#endif
 	}
 
 	/*
@@ -414,6 +436,23 @@ static void __init bootmem_init(void)
 	 * Reserve initrd memory if needed.
 	 */
 	finalize_initrd();
+
+	/*
+	 * Call memory_present() on all valid ranges, for SPARSEMEM.
+	 * This must be done after setting up bootmem, since memory_present()
+	 * may allocate bootmem.
+	 */
+	for (i = 0; i < boot_mem_map.nr_map; i++) {
+		unsigned long start, end;
+
+		if (boot_mem_map.map[i].type != BOOT_MEM_RAM)
+			continue;
+
+		start = PFN_UP(boot_mem_map.map[i].addr);
+		end   = PFN_DOWN(boot_mem_map.map[i].addr
+				    + boot_mem_map.map[i].size);
+		memory_present(0, start, end);
+	}
 }
 
 #endif	/* CONFIG_SGI_IP27 */
@@ -501,11 +540,18 @@ static void __init arch_mem_init(char **cmdline_p)
 #ifdef CONFIG_CMDLINE_OVERRIDE
 	strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
 #else
+#ifdef CONFIG_CMDLINE_EXTEND
 	if (builtin_cmdline[0]) {
 		strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
 		strlcat(arcs_cmdline, builtin_cmdline, COMMAND_LINE_SIZE);
 	}
 	strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
+#else
+	if (arcs_cmdline[0])
+		strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
+	else
+		strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
+#endif
 #endif
 #else
 	strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 3046e29..b5dd8ac 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -36,6 +36,7 @@
 #include <asm/bmips.h>
 #include <asm/traps.h>
 #include <asm/barrier.h>
+#include <asm/cpu-features.h>
 
 static int __maybe_unused max_cpus = 1;
 
@@ -44,6 +45,11 @@ int bmips_smp_enabled = 1;
 int bmips_cpu_offset;
 cpumask_t bmips_booted_mask;
 
+#define RESET_FROM_KSEG0		0x80080800
+#define RESET_FROM_KSEG1		0xa0080800
+
+static void bmips_set_reset_vec(int cpu, u32 val);
+
 #ifdef CONFIG_SMP
 
 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
@@ -154,23 +160,17 @@ static void bmips_boot_secondary(int cpu, struct task_struct *idle)
 
 	pr_info("SMP: Booting CPU%d...\n", cpu);
 
-	if (cpumask_test_cpu(cpu, &bmips_booted_mask))
+	if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {
+		/* kseg1 might not exist if this CPU enabled XKS01 */
+		bmips_set_reset_vec(cpu, RESET_FROM_KSEG0);
 		bmips_send_ipi_single(cpu, 0);
-	else {
+	} else {
+		bmips_set_reset_vec(cpu, RESET_FROM_KSEG1);
+
 #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
 		set_c0_brcm_cmt_ctrl(0x01);
 #elif defined(CONFIG_CPU_BMIPS5000)
-		if (cpu & 0x01)
-			write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
-		else {
-			/*
-			 * core N thread 0 was already booted; just
-			 * pulse the NMI line
-			 */
-			bmips_write_zscm_reg(0x210, 0xc0000000);
-			udelay(10);
-			bmips_write_zscm_reg(0x210, 0x00);
-		}
+		write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
 #endif
 		cpumask_set_cpu(cpu, &bmips_booted_mask);
 	}
@@ -184,26 +184,10 @@ static void bmips_init_secondary(void)
 	/* move NMI vector to kseg0, in case XKS01 is enabled */
 
 #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
-	void __iomem *cbr = BMIPS_GET_CBR();
-	unsigned long old_vec;
-
-	old_vec = __raw_readl(cbr + BMIPS_RELO_VECTOR_CONTROL_1);
-	__raw_writel(old_vec & ~0x20000000, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
-
 	clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
 #elif defined(CONFIG_CPU_BMIPS5000)
-	write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
-		(smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
-
 	write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
 #endif
-
-	/* make sure there won't be a timer interrupt for a little while */
-	write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
-
-	irq_enable_hazard();
-	set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
-	irq_enable_hazard();
 }
 
 /*
@@ -212,6 +196,13 @@ static void bmips_init_secondary(void)
 static void bmips_smp_finish(void)
 {
 	pr_info("SMP: CPU%d is running\n", smp_processor_id());
+
+	/* make sure there won't be a timer interrupt for a little while */
+	write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
+
+	irq_enable_hazard();
+	set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
+	irq_enable_hazard();
 }
 
 /*
@@ -307,6 +298,24 @@ static void bmips_send_ipi_mask(const struct cpumask *mask,
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
+static void bmips_fixup_irqs(void)
+{
+	/*
+	 *  All interrupts for this cpu must be disabled.
+	 *  If an interrupt was only routed to this cpu,
+	 *  it must be migrated to another cpu.
+	 *  Code TBD, see SWLINUX-2624
+	 */
+
+	/*
+	 * MIPS CPUs have a per-processor counter compare register.
+	 * This is typically used as the clock event interrupt.
+	 * On current STB SoCs, this is interrupt 7.
+	 * Disable the interrupt.
+	 */
+	clear_c0_status(IE_IRQ5);
+
+}
 
 static int bmips_cpu_disable(void)
 {
@@ -320,6 +329,12 @@ static int bmips_cpu_disable(void)
 	set_cpu_online(cpu, false);
 	cpu_clear(cpu, cpu_callin_map);
 
+	/*
+	 *  all interrupts for this cpu must be disabled
+	 *  at this point.
+	 */
+	bmips_fixup_irqs();
+
 	local_flush_tlb_all();
 	local_flush_icache_range(0, ~0);
 
@@ -385,7 +400,7 @@ struct plat_smp_ops bmips_smp_ops = {
 static void __cpuinit bmips_wr_vec(unsigned long dst, char *start, char *end)
 {
 	memcpy((void *)dst, start, end - start);
-	dma_cache_wback((unsigned long)start, end - start);
+	dma_cache_wback(dst, end - start);
 	local_flush_icache_range(dst, dst + (end - start));
 	instruction_hazard();
 }
@@ -398,12 +413,61 @@ static inline void __cpuinit bmips_nmi_handler_setup(void)
 		&bmips_smp_int_vec_end);
 }
 
+struct reset_vec_info {
+	int cpu;
+	u32 val;
+};
+
+static void bmips_set_reset_vec_remote(void *vinfo)
+{
+	struct reset_vec_info *info = vinfo;
+	int shift = info->cpu & 0x01 ? 16 : 0;
+	u32 mask = ~(0xffff << shift), val = info->val >> 16;
+
+	preempt_disable();
+	if (smp_processor_id() > 0) {
+		smp_call_function_single(0, &bmips_set_reset_vec_remote,
+					 info, 1);
+	} else {
+		if (info->cpu & 0x02) {
+			/* BMIPS5200 "should" use mask/shift, but it's buggy */
+			bmips_write_zscm_reg(0xa0, (val << 16) | val);
+			bmips_read_zscm_reg(0xa0);
+		} else {
+			write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) |
+					      (val << shift));
+		}
+	}
+	preempt_enable();
+}
+
+static void bmips_set_reset_vec(int cpu, u32 val)
+{
+	struct reset_vec_info info;
+
+	if (current_cpu_type() == CPU_BMIPS5000) {
+		/* this needs to run from CPU0 (which is always online) */
+		info.cpu = cpu;
+		info.val = val;
+		bmips_set_reset_vec_remote(&info);
+	} else {
+		void __iomem *cbr = BMIPS_GET_CBR();
+
+		if (cpu == 0)
+			__raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
+		else {
+			if (current_cpu_type() != CPU_BMIPS4380)
+				return;
+			__raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
+		}
+	}
+	__sync();
+	back_to_back_c0_hazard();
+}
+
 void __cpuinit bmips_ebase_setup(void)
 {
 	unsigned long new_ebase = ebase;
-	void __iomem __maybe_unused *cbr;
-
-	BUG_ON(ebase != CKSEG0);
 
 #if defined(CONFIG_CPU_BMIPS4350)
 	/*
@@ -420,25 +484,21 @@ void __cpuinit bmips_ebase_setup(void)
 		&bmips_smp_int_vec, 0x80);
 	__sync();
 	return;
-#elif defined(CONFIG_CPU_BMIPS4380)
+#elif defined(CONFIG_CPU_BMIPS3300) || defined(CONFIG_CPU_BMIPS4380)
 	/*
 	 * 0x8000_0000: reset/NMI (initially in kseg1)
 	 * 0x8000_0400: normal vectors
 	 */
 	new_ebase = 0x80000400;
-	cbr = BMIPS_GET_CBR();
-	__raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
-	__raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
+	bmips_set_reset_vec(0, RESET_FROM_KSEG0);
 #elif defined(CONFIG_CPU_BMIPS5000)
 	/*
 	 * 0x8000_0000: reset/NMI (initially in kseg1)
 	 * 0x8000_1000: normal vectors
 	 */
 	new_ebase = 0x80001000;
-	write_c0_brcm_bootvec(0xa0088008);
+	bmips_set_reset_vec(0, RESET_FROM_KSEG0);
 	write_c0_ebase(new_ebase);
-	if (max_cpus > 2)
-		bmips_write_zscm_reg(0xa0, 0xa008a008);
 #else
 	return;
 #endif
diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c
index e7e03ec..afc379c 100644
--- a/arch/mips/kernel/smp-cmp.c
+++ b/arch/mips/kernel/smp-cmp.c
@@ -102,7 +102,7 @@ static void cmp_init_secondary(void)
 	c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE;
 #endif
 #ifdef CONFIG_MIPS_MT_SMTC
-	c->tc_id  = (read_c0_tcbind() >> TCBIND_CURTC_SHIFT) & TCBIND_CURTC;
+	c->tc_id  = (read_c0_tcbind() & TCBIND_CURTC) >> TCBIND_CURTC_SHIFT;
 #endif
 }
 
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 7c2c1af..94e3e0e 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -122,13 +122,21 @@ asmlinkage __cpuinit void start_secondary(void)
 
 	notify_cpu_starting(cpu);
 
-	mp_ops->smp_finish();
+	set_cpu_online(cpu, true);
+
 	set_cpu_sibling_map(cpu);
 
 	cpu_set(cpu, cpu_callin_map);
 
 	synchronise_count_slave();
 
+	/*
+	 * irq will be enabled in ->smp_finish(), enabling it too early
+	 * is dangerous.
+	 */
+	WARN_ON_ONCE(!irqs_disabled());
+	mp_ops->smp_finish();
+
 	cpu_idle();
 }
 
@@ -248,8 +256,6 @@ int __cpuinit __cpu_up(unsigned int cpu)
 	while (!cpu_isset(cpu, cpu_callin_map))
 		udelay(100);
 
-	set_cpu_online(cpu, true);
-
 	return 0;
 }
 
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index f5dd38f..af46fdd 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -615,7 +615,6 @@ void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle)
 
 void smtc_init_secondary(void)
 {
-	local_irq_enable();
 }
 
 void smtc_smp_finish(void)
@@ -631,6 +630,8 @@ void smtc_smp_finish(void)
 	if (cpu > 0 && (cpu_data[cpu].vpe_id != cpu_data[cpu - 1].vpe_id))
 		write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
 
+	local_irq_enable();
+
 	printk("TC %d going on-line as CPU %d\n",
 		cpu_data[smp_processor_id()].tc_id, smp_processor_id());
 }
diff --git a/arch/mips/kernel/sync-r4k.c b/arch/mips/kernel/sync-r4k.c
index 99f913c..842d55e 100644
--- a/arch/mips/kernel/sync-r4k.c
+++ b/arch/mips/kernel/sync-r4k.c
@@ -111,7 +111,6 @@ void __cpuinit synchronise_count_master(void)
 void __cpuinit synchronise_count_slave(void)
 {
 	int i;
-	unsigned long flags;
 	unsigned int initcount;
 	int ncpus;
 
@@ -123,8 +122,6 @@ void __cpuinit synchronise_count_slave(void)
 	return;
 #endif
 
-	local_irq_save(flags);
-
 	/*
 	 * Not every cpu is online at the time this gets called,
 	 * so we first wait for the master to say everyone is ready
@@ -154,7 +151,5 @@ void __cpuinit synchronise_count_slave(void)
 	}
 	/* Arrange for an interrupt in a short while */
 	write_c0_compare(read_c0_count() + COUNTON);
-
-	local_irq_restore(flags);
 }
 #undef NR_LOOPS
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index cfdaaa4..4019349 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -54,6 +54,10 @@
 #include <asm/stacktrace.h>
 #include <asm/uasm.h>
 
+#ifdef CONFIG_BRCMSTB
+#include <linux/brcmstb/brcmapi.h>
+#endif
+
 extern void check_wait(void);
 extern asmlinkage void r4k_wait(void);
 extern asmlinkage void rollback_handle_int(void);
@@ -131,6 +135,9 @@ static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
 	unsigned long ra = regs->regs[31];
 	unsigned long pc = regs->cp0_epc;
 
+	if (!task)
+		task = current;
+
 	if (raw_show_trace || !__kernel_text_address(pc)) {
 		show_raw_backtrace(sp);
 		return;
@@ -605,6 +612,10 @@ static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
 {
 	struct thread_info *ti = task_thread_info(current);
 
+#ifdef CONFIG_BRCMSTB
+	if (brcm_simulate_opcode(regs, opcode) == 0)
+		return 0;
+#endif
 	if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
 		int rd = (opcode & RD) >> 11;
 		int rt = (opcode & RT) >> 16;
@@ -656,28 +667,33 @@ static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
 
 asmlinkage void do_ov(struct pt_regs *regs)
 {
-	siginfo_t info;
+	siginfo_t info = {
+		.si_signo = SIGFPE,
+		.si_code = FPE_INTOVF,
+		.si_addr = (void __user *)regs->cp0_epc,
+	};
 
 	die_if_kernel("Integer overflow", regs);
 
-	info.si_code = FPE_INTOVF;
-	info.si_signo = SIGFPE;
-	info.si_errno = 0;
-	info.si_addr = (void __user *) regs->cp0_epc;
 	force_sig_info(SIGFPE, &info, current);
 }
 
 static int process_fpemu_return(int sig, void __user *fault_addr)
 {
+	struct vm_area_struct *vma;
+
 	if (sig == SIGSEGV || sig == SIGBUS) {
 		struct siginfo si = {0};
 		si.si_addr = fault_addr;
 		si.si_signo = sig;
 		if (sig == SIGSEGV) {
-			if (find_vma(current->mm, (unsigned long)fault_addr))
+			down_read(&current->mm->mmap_sem);
+			vma = find_vma(current->mm, (unsigned long)fault_addr);
+			if (vma && (vma->vm_start <= (unsigned long)fault_addr))
 				si.si_code = SEGV_ACCERR;
 			else
 				si.si_code = SEGV_MAPERR;
+			up_read(&current->mm->mmap_sem);
 		} else {
 			si.si_code = BUS_ADRERR;
 		}
@@ -758,7 +774,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
 	const char *str)
 {
-	siginfo_t info;
+	siginfo_t info = { 0 };
 	char b[40];
 
 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
@@ -785,7 +801,6 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
 		else
 			info.si_code = FPE_INTOVF;
 		info.si_signo = SIGFPE;
-		info.si_errno = 0;
 		info.si_addr = (void __user *) regs->cp0_epc;
 		force_sig_info(SIGFPE, &info, current);
 		break;
@@ -1017,6 +1032,24 @@ asmlinkage void do_cpu(struct pt_regs *regs)
 
 		return;
 
+	case 3:
+		/*
+		 * Old (MIPS I and MIPS II) processors will set this code
+		 * for COP1X opcode instructions that replaced the original
+		 * COP3 space.  We don't limit COP1 space instructions in
+		 * the emulator according to the CPU ISA, so we want to
+		 * treat COP1X instructions consistently regardless of which
+		 * code the CPU chose.  Therefore we redirect this trap to
+		 * the FP emulator too.
+		 *
+		 * Then some newer FPU-less processors use this code
+		 * erroneously too, so they are covered by this choice
+		 * as well.
+		 */
+		if (raw_cpu_has_fpu)
+			break;
+		/* Fall through.  */
+
 	case 1:
 		if (used_math())	/* Using the FPU again.  */
 			own_fpu(1);
@@ -1040,9 +1073,6 @@ asmlinkage void do_cpu(struct pt_regs *regs)
 	case 2:
 		raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
 		return;
-
-	case 3:
-		break;
 	}
 
 	force_sig(SIGILL, current);
@@ -1498,6 +1528,7 @@ extern void flush_tlb_handlers(void);
  * Timer interrupt
  */
 int cp0_compare_irq;
+EXPORT_SYMBOL_GPL(cp0_compare_irq);
 int cp0_compare_irq_shift;
 
 /*
@@ -1617,7 +1648,11 @@ void __cpuinit per_cpu_trap_init(void)
 	if (bootTC) {
 #endif /* CONFIG_MIPS_MT_SMTC */
 		cpu_cache_init();
+#ifdef CONFIG_BRCMSTB
+		brcm_tlb_init();
+#else
 		tlb_init();
+#endif
 #ifdef CONFIG_MIPS_MT_SMTC
 	} else if (!secondaryTC) {
 		/*
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 9c58bdf..232458c 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -86,6 +86,10 @@
 #include <asm/inst.h>
 #include <asm/uaccess.h>
 
+#ifdef CONFIG_BRCMSTB
+#include <linux/brcmstb/brcmapi.h>
+#endif
+
 #define STR(x)  __STR(x)
 #define __STR(x)  #x
 
@@ -447,10 +451,21 @@ static void emulate_load_store_insn(struct pt_regs *regs,
 	case ldc1_op:
 	case swc1_op:
 	case sdc1_op:
+#ifdef CONFIG_BRCMSTB
+		switch (brcm_unaligned_fp(addr, &insn, regs)) {
+		case -EINVAL:
+			goto sigbus;
+		case -EFAULT:
+			goto fault;
+		}
+		compute_return_epc(regs);
+		break;
+#else
 		/*
 		 * I herewith declare: this does not happen.  So send SIGBUS.
 		 */
 		goto sigbus;
+#endif
 
 	/*
 	 * COP2 is available to implementor for application specific use.
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index d673731..271d581 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -159,7 +159,7 @@ static void ltq_shutdown_eiu_irq(struct irq_data *d)
 }
 
 static struct irq_chip ltq_irq_type = {
-	"icu",
+	.name = "icu",
 	.irq_enable = ltq_enable_irq,
 	.irq_disable = ltq_disable_irq,
 	.irq_unmask = ltq_enable_irq,
@@ -169,7 +169,7 @@ static struct irq_chip ltq_irq_type = {
 };
 
 static struct irq_chip ltq_eiu_type = {
-	"eiu",
+	.name = "eiu",
 	.irq_startup = ltq_startup_eiu_irq,
 	.irq_shutdown = ltq_shutdown_eiu_irq,
 	.irq_enable = ltq_enable_irq,
diff --git a/arch/mips/lasat/Kconfig b/arch/mips/lasat/Kconfig
index 1d2ee8a..8776d0a 100644
--- a/arch/mips/lasat/Kconfig
+++ b/arch/mips/lasat/Kconfig
@@ -4,7 +4,7 @@ config PICVUE
 
 config PICVUE_PROC
 	tristate "PICVUE LCD display driver /proc interface"
-	depends on PICVUE
+	depends on PICVUE && PROC_FS
 
 config DS1603
 	bool "DS1603 RTC driver"
diff --git a/arch/mips/lasat/picvue_proc.c b/arch/mips/lasat/picvue_proc.c
index 8e388da..ed803be 100644
--- a/arch/mips/lasat/picvue_proc.c
+++ b/arch/mips/lasat/picvue_proc.c
@@ -44,7 +44,7 @@ static int pvc_line_proc_show(struct seq_file *m, void *v)
 {
 	int lineno = *(int *)m->private;
 
-	if (lineno < 0 || lineno > PVC_NLINES) {
+	if (lineno < 0 || lineno >= PVC_NLINES) {
 		printk(KERN_WARNING "proc_read_line: invalid lineno %d\n", lineno);
 		return 0;
 	}
@@ -68,7 +68,7 @@ static ssize_t pvc_line_proc_write(struct file *file, const char __user *buf,
 	char kbuf[PVC_LINELEN];
 	size_t len;
 
-	BUG_ON(lineno < 0 || lineno > PVC_NLINES);
+	BUG_ON(lineno < 0 || lineno >= PVC_NLINES);
 
 	len = min(count, sizeof(kbuf) - 1);
 	if (copy_from_user(kbuf, buf, len))
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 2a7c74f..af37581 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -2,8 +2,8 @@
 # Makefile for MIPS-specific library files..
 #
 
-lib-y	+= csum_partial.o delay.o memcpy.o memcpy-inatomic.o memset.o \
-	   strlen_user.o strncpy_user.o strnlen_user.o uncached.o
+lib-y	+= bitops.o csum_partial.o delay.o memcpy.o memcpy-inatomic.o memset.o \
+	   mips-atomic.o strlen_user.o strncpy_user.o strnlen_user.o uncached.o
 
 obj-y			+= iomap.o
 obj-$(CONFIG_PCI)	+= iomap-pci.o
@@ -32,4 +32,5 @@ obj-$(CONFIG_CPU_XLR)		+= dump_tlb.o
 obj-$(CONFIG_CPU_XLP)		+= dump_tlb.o
 
 # libgcc-style stuff needed in the kernel
-obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o
+obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o udivdi3.o
+obj-$(CONFIG_BRCM_LIBGCC)	+= udivdi3.o
diff --git a/arch/mips/lib/bitops.c b/arch/mips/lib/bitops.c
new file mode 100644
index 0000000..239a9c9
--- /dev/null
+++ b/arch/mips/lib/bitops.c
@@ -0,0 +1,179 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1994-1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (c) 1999, 2000  Silicon Graphics, Inc.
+ */
+#include <linux/bitops.h>
+#include <linux/irqflags.h>
+#include <linux/export.h>
+
+
+/**
+ * __mips_set_bit - Atomically set a bit in memory.  This is called by
+ * set_bit() if it cannot find a faster solution.
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ */
+void __mips_set_bit(unsigned long nr, volatile unsigned long *addr)
+{
+	volatile unsigned long *a = addr;
+	unsigned bit = nr & SZLONG_MASK;
+	unsigned long mask;
+	unsigned long flags;
+
+	a += nr >> SZLONG_LOG;
+	mask = 1UL << bit;
+	raw_local_irq_save(flags);
+	*a |= mask;
+	raw_local_irq_restore(flags);
+}
+EXPORT_SYMBOL(__mips_set_bit);
+
+
+/**
+ * __mips_clear_bit - Clears a bit in memory.  This is called by clear_bit() if
+ * it cannot find a faster solution.
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ */
+void __mips_clear_bit(unsigned long nr, volatile unsigned long *addr)
+{
+	volatile unsigned long *a = addr;
+	unsigned bit = nr & SZLONG_MASK;
+	unsigned long mask;
+	unsigned long flags;
+
+	a += nr >> SZLONG_LOG;
+	mask = 1UL << bit;
+	raw_local_irq_save(flags);
+	*a &= ~mask;
+	raw_local_irq_restore(flags);
+}
+EXPORT_SYMBOL(__mips_clear_bit);
+
+
+/**
+ * __mips_change_bit - Toggle a bit in memory.  This is called by change_bit()
+ * if it cannot find a faster solution.
+ * @nr: Bit to change
+ * @addr: Address to start counting from
+ */
+void __mips_change_bit(unsigned long nr, volatile unsigned long *addr)
+{
+	volatile unsigned long *a = addr;
+	unsigned bit = nr & SZLONG_MASK;
+	unsigned long mask;
+	unsigned long flags;
+
+	a += nr >> SZLONG_LOG;
+	mask = 1UL << bit;
+	raw_local_irq_save(flags);
+	*a ^= mask;
+	raw_local_irq_restore(flags);
+}
+EXPORT_SYMBOL(__mips_change_bit);
+
+
+/**
+ * __mips_test_and_set_bit - Set a bit and return its old value.  This is
+ * called by test_and_set_bit() if it cannot find a faster solution.
+ * @nr: Bit to set
+ * @addr: Address to count from
+ */
+int __mips_test_and_set_bit(unsigned long nr,
+			    volatile unsigned long *addr)
+{
+	volatile unsigned long *a = addr;
+	unsigned bit = nr & SZLONG_MASK;
+	unsigned long mask;
+	unsigned long flags;
+	unsigned long res;
+
+	a += nr >> SZLONG_LOG;
+	mask = 1UL << bit;
+	raw_local_irq_save(flags);
+	res = (mask & *a);
+	*a |= mask;
+	raw_local_irq_restore(flags);
+	return res;
+}
+EXPORT_SYMBOL(__mips_test_and_set_bit);
+
+
+/**
+ * __mips_test_and_set_bit_lock - Set a bit and return its old value.  This is
+ * called by test_and_set_bit_lock() if it cannot find a faster solution.
+ * @nr: Bit to set
+ * @addr: Address to count from
+ */
+int __mips_test_and_set_bit_lock(unsigned long nr,
+				 volatile unsigned long *addr)
+{
+	volatile unsigned long *a = addr;
+	unsigned bit = nr & SZLONG_MASK;
+	unsigned long mask;
+	unsigned long flags;
+	unsigned long res;
+
+	a += nr >> SZLONG_LOG;
+	mask = 1UL << bit;
+	raw_local_irq_save(flags);
+	res = (mask & *a);
+	*a |= mask;
+	raw_local_irq_restore(flags);
+	return res;
+}
+EXPORT_SYMBOL(__mips_test_and_set_bit_lock);
+
+
+/**
+ * __mips_test_and_clear_bit - Clear a bit and return its old value.  This is
+ * called by test_and_clear_bit() if it cannot find a faster solution.
+ * @nr: Bit to clear
+ * @addr: Address to count from
+ */
+int __mips_test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
+{
+	volatile unsigned long *a = addr;
+	unsigned bit = nr & SZLONG_MASK;
+	unsigned long mask;
+	unsigned long flags;
+	unsigned long res;
+
+	a += nr >> SZLONG_LOG;
+	mask = 1UL << bit;
+	raw_local_irq_save(flags);
+	res = (mask & *a);
+	*a &= ~mask;
+	raw_local_irq_restore(flags);
+	return res;
+}
+EXPORT_SYMBOL(__mips_test_and_clear_bit);
+
+
+/**
+ * __mips_test_and_change_bit - Change a bit and return its old value.  This is
+ * called by test_and_change_bit() if it cannot find a faster solution.
+ * @nr: Bit to change
+ * @addr: Address to count from
+ */
+int __mips_test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
+{
+	volatile unsigned long *a = addr;
+	unsigned bit = nr & SZLONG_MASK;
+	unsigned long mask;
+	unsigned long flags;
+	unsigned long res;
+
+	a += nr >> SZLONG_LOG;
+	mask = 1UL << bit;
+	raw_local_irq_save(flags);
+	res = (mask & *a);
+	*a ^= mask;
+	raw_local_irq_restore(flags);
+	return res;
+}
+EXPORT_SYMBOL(__mips_test_and_change_bit);
diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
index 6b876ca..d48da78 100644
--- a/arch/mips/lib/csum_partial.S
+++ b/arch/mips/lib/csum_partial.S
@@ -55,14 +55,20 @@
 #define UNIT(unit)  ((unit)*NBYTES)
 
 #define ADDC(sum,reg)						\
+	.set	push;						\
+	.set	noat;						\
 	ADD	sum, reg;					\
 	sltu	v1, sum, reg;					\
 	ADD	sum, v1;					\
+	.set	pop
 
 #define ADDC32(sum,reg)						\
+	.set	push;						\
+	.set	noat;						\
 	addu	sum, reg;					\
 	sltu	v1, sum, reg;					\
 	addu	sum, v1;					\
+	.set	pop
 
 #define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3)	\
 	LOAD	_t0, (offset + UNIT(0))(src);			\
@@ -270,7 +276,7 @@ LEAF(csum_partial)
 #endif
 
 	/* odd buffer alignment? */
-#ifdef CPU_MIPSR2
+#ifdef CONFIG_CPU_MIPSR2
 	wsbh	v1, sum
 	movn	sum, v1, t7
 #else
@@ -662,6 +668,8 @@ EXC(	sb	t0, NBYTES-2(dst), .Ls_exc)
 	ADDC(sum, t2)
 .Ldone:
 	/* fold checksum */
+	.set	push
+	.set	noat
 #ifdef USE_DOUBLE
 	dsll32	v1, sum, 0
 	daddu	sum, v1
@@ -670,7 +678,7 @@ EXC(	sb	t0, NBYTES-2(dst), .Ls_exc)
 	addu	sum, v1
 #endif
 
-#ifdef CPU_MIPSR2
+#ifdef CONFIG_CPU_MIPSR2
 	wsbh	v1, sum
 	movn	sum, v1, odd
 #else
@@ -684,6 +692,7 @@ EXC(	sb	t0, NBYTES-2(dst), .Ls_exc)
 	or	sum, sum, t0
 1:
 #endif
+	.set	pop
 	.set reorder
 	ADDC32(sum, psum)
 	jr	ra
diff --git a/arch/mips/lib/delay.c b/arch/mips/lib/delay.c
index 5995969..2507a5c 100644
--- a/arch/mips/lib/delay.c
+++ b/arch/mips/lib/delay.c
@@ -6,7 +6,7 @@
  * Copyright (C) 1994 by Waldorf Electronics
  * Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle
  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2007  Maciej W. Rozycki
+ * Copyright (C) 2007, 2014 Maciej W. Rozycki
  */
 #include <linux/module.h>
 #include <linux/param.h>
@@ -15,16 +15,22 @@
 #include <asm/compiler.h>
 #include <asm/war.h>
 
+#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
+#define GCC_DADDI_IMM_ASM() "I"
+#else
+#define GCC_DADDI_IMM_ASM() "r"
+#endif
+
 inline void __delay(unsigned int loops)
 {
 	__asm__ __volatile__ (
 	"	.set	noreorder				\n"
 	"	.align	3					\n"
 	"1:	bnez	%0, 1b					\n"
-	"	subu	%0, 1					\n"
+	"	subu	%0, %1					\n"
 	"	.set	reorder					\n"
 	: "=r" (loops)
-	: "0" (loops));
+	: GCC_DADDI_IMM_ASM() (1), "0" (loops));
 }
 EXPORT_SYMBOL(__delay);
 
diff --git a/arch/mips/lib/longlong.h b/arch/mips/lib/longlong.h
new file mode 100644
index 0000000..d7d7398
--- /dev/null
+++ b/arch/mips/lib/longlong.h
@@ -0,0 +1,1350 @@
+/* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
+   Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000
+   Free Software Foundation, Inc.
+
+   This definition file is free software; you can redistribute it
+   and/or modify it under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either
+   version 2, or (at your option) any later version.
+
+   This definition file is distributed in the hope that it will be
+   useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+   See the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+/* You have to define the following before including this file:
+
+   UWtype -- An unsigned type, default type for operations (typically a "word")
+   UHWtype -- An unsigned type, at least half the size of UWtype.
+   UDWtype -- An unsigned type, at least twice as large a UWtype
+   W_TYPE_SIZE -- size in bits of UWtype
+
+   UQItype -- Unsigned 8 bit type.
+   SItype, USItype -- Signed and unsigned 32 bit types.
+   DItype, UDItype -- Signed and unsigned 64 bit types.
+
+   On a 32 bit machine UWtype should typically be USItype;
+   on a 64 bit machine, UWtype should typically be UDItype.
+*/
+
+#define __BITS4 (W_TYPE_SIZE / 4)
+#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
+#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
+#define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
+
+#ifndef W_TYPE_SIZE
+#define W_TYPE_SIZE	32
+#define UWtype		USItype
+#define UHWtype		USItype
+#define UDWtype		UDItype
+#endif
+
+/* Define auxiliary asm macros.
+
+   1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) multiplies two
+   UWtype integers MULTIPLER and MULTIPLICAND, and generates a two UWtype
+   word product in HIGH_PROD and LOW_PROD.
+
+   2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
+   UDWtype product.  This is just a variant of umul_ppmm.
+
+   3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
+   denominator) divides a UDWtype, composed by the UWtype integers
+   HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
+   in QUOTIENT and the remainder in REMAINDER.  HIGH_NUMERATOR must be less
+   than DENOMINATOR for correct operation.  If, in addition, the most
+   significant bit of DENOMINATOR must be 1, then the pre-processor symbol
+   UDIV_NEEDS_NORMALIZATION is defined to 1.
+
+   4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
+   denominator).  Like udiv_qrnnd but the numbers are signed.  The quotient
+   is rounded towards 0.
+
+   5) count_leading_zeros(count, x) counts the number of zero-bits from the
+   msb to the first nonzero bit in the UWtype X.  This is the number of
+   steps X needs to be shifted left to set the msb.  Undefined for X == 0,
+   unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
+
+   6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
+   from the least significant end.
+
+   7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
+   high_addend_2, low_addend_2) adds two UWtype integers, composed by
+   HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
+   respectively.  The result is placed in HIGH_SUM and LOW_SUM.  Overflow
+   (i.e. carry out) is not stored anywhere, and is lost.
+
+   8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
+   high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
+   composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
+   LOW_SUBTRAHEND_2 respectively.  The result is placed in HIGH_DIFFERENCE
+   and LOW_DIFFERENCE.  Overflow (i.e. carry out) is not stored anywhere,
+   and is lost.
+
+   If any of these macros are left undefined for a particular CPU,
+   C macros are used.  */
+
+/* The CPUs come in alphabetical order below.
+
+   Please add support for more CPUs here, or improve the current support
+   for the CPUs below!
+   (E.g. WE32100, IBM360.)  */
+
+#if defined (__GNUC__) && !defined (NO_ASM)
+
+/* We sometimes need to clobber "cc" with gcc2, but that would not be
+   understood by gcc1.  Use cpp to avoid major code duplication.  */
+#if __GNUC__ < 2
+#define __CLOBBER_CC
+#define __AND_CLOBBER_CC
+#else /* __GNUC__ >= 2 */
+#define __CLOBBER_CC : "cc"
+#define __AND_CLOBBER_CC , "cc"
+#endif /* __GNUC__ < 2 */
+
+#if defined (__alpha) && W_TYPE_SIZE == 64
+#define umul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    UDItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("umulh %r1,%2,%0"						\
+	     : "=r" ((UDItype) ph)					\
+	     : "%rJ" (__m0),						\
+	       "rI" (__m1));						\
+    (pl) = __m0 * __m1;							\
+  } while (0)
+#define UMUL_TIME 46
+#ifndef LONGLONG_STANDALONE
+#define udiv_qrnnd(q, r, n1, n0, d) \
+  do { UDItype __r;							\
+    (q) = __udiv_qrnnd (&__r, (n1), (n0), (d));				\
+    (r) = __r;								\
+  } while (0)
+extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
+#define UDIV_TIME 220
+#endif /* LONGLONG_STANDALONE */
+#ifdef __alpha_cix__
+#define count_leading_zeros(COUNT,X) \
+  __asm__("ctlz %1,%0" : "=r"(COUNT) : "r"(X))
+#define count_trailing_zeros(COUNT,X) \
+  __asm__("cttz %1,%0" : "=r"(COUNT) : "r"(X))
+#define COUNT_LEADING_ZEROS_0 64
+#else
+extern const UQItype __clz_tab[];
+#define count_leading_zeros(COUNT,X) \
+  do {									\
+    UDItype __xr = (X), __t, __a;					\
+    __asm__("cmpbge $31,%1,%0" : "=r"(__t) : "r"(__xr));		\
+    __a = __clz_tab[__t ^ 0xff] - 1;					\
+    __asm__("extbl %1,%2,%0" : "=r"(__t) : "r"(__xr), "r"(__a));	\
+    (COUNT) = 64 - (__clz_tab[__t] + __a*8);				\
+  } while (0)
+#define count_trailing_zeros(COUNT,X) \
+  do {									\
+    UDItype __xr = (X), __t, __a;					\
+    __asm__("cmpbge $31,%1,%0" : "=r"(__t) : "r"(__xr));		\
+    __t = ~__t & -~__t;							\
+    __a = ((__t & 0xCC) != 0) * 2;					\
+    __a += ((__t & 0xF0) != 0) * 4;					\
+    __a += ((__t & 0xAA) != 0);						\
+    __asm__("extbl %1,%2,%0" : "=r"(__t) : "r"(__xr), "r"(__a));	\
+    __a <<= 3;								\
+    __t &= -__t;							\
+    __a += ((__t & 0xCC) != 0) * 2;					\
+    __a += ((__t & 0xF0) != 0) * 4;					\
+    __a += ((__t & 0xAA) != 0);						\
+    (COUNT) = __a;							\
+  } while (0)
+#endif /* __alpha_cix__ */
+#endif /* __alpha */
+
+#if defined (__arc__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("add.f	%1, %4, %5\n\tadc	%0, %2, %3"		\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%r" ((USItype) (ah)),					\
+	     "rIJ" ((USItype) (bh)),					\
+	     "%r" ((USItype) (al)),					\
+	     "rIJ" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("sub.f	%1, %4, %5\n\tsbc	%0, %2, %3"		\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "r" ((USItype) (ah)),					\
+	     "rIJ" ((USItype) (bh)),					\
+	     "r" ((USItype) (al)),					\
+	     "rIJ" ((USItype) (bl)))
+/* Call libgcc routine.  */
+#define umul_ppmm(w1, w0, u, v) \
+do {									\
+  DWunion __w;								\
+  __w.ll = __umulsidi3 (u, v);						\
+  w1 = __w.s.high;							\
+  w0 = __w.s.low;							\
+} while (0)
+#define __umulsidi3 __umulsidi3
+UDItype __umulsidi3 (USItype, USItype);
+#endif
+
+#if defined (__arm__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("adds	%1, %4, %5\n\tadc	%0, %2, %3"		\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%r" ((USItype) (ah)),					\
+	     "rI" ((USItype) (bh)),					\
+	     "%r" ((USItype) (al)),					\
+	     "rI" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("subs	%1, %4, %5\n\tsbc	%0, %2, %3"		\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "r" ((USItype) (ah)),					\
+	     "rI" ((USItype) (bh)),					\
+	     "r" ((USItype) (al)),					\
+	     "rI" ((USItype) (bl)))
+#define umul_ppmm(xh, xl, a, b) \
+{register USItype __t0, __t1, __t2;					\
+  __asm__ ("%@ Inlined umul_ppmm\n"					\
+	   "	mov	%2, %5, lsr #16\n"				\
+	   "	mov	%0, %6, lsr #16\n"				\
+	   "	bic	%3, %5, %2, lsl #16\n"				\
+	   "	bic	%4, %6, %0, lsl #16\n"				\
+	   "	mul	%1, %3, %4\n"					\
+	   "	mul	%4, %2, %4\n"					\
+	   "	mul	%3, %0, %3\n"					\
+	   "	mul	%0, %2, %0\n"					\
+	   "	adds	%3, %4, %3\n"					\
+	   "	addcs	%0, %0, #65536\n"				\
+	   "	adds	%1, %1, %3, lsl #16\n"				\
+	   "	adc	%0, %0, %3, lsr #16"				\
+	   : "=&r" ((USItype) (xh)),					\
+	     "=r" ((USItype) (xl)),					\
+	     "=&r" (__t0), "=&r" (__t1), "=r" (__t2)			\
+	   : "r" ((USItype) (a)),					\
+	     "r" ((USItype) (b)));}
+#define UMUL_TIME 20
+#define UDIV_TIME 100
+#endif /* __arm__ */
+
+#if defined (__hppa) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0"				\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%rM" ((USItype) (ah)),					\
+	     "rM" ((USItype) (bh)),					\
+	     "%rM" ((USItype) (al)),					\
+	     "rM" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0"				\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "rM" ((USItype) (ah)),					\
+	     "rM" ((USItype) (bh)),					\
+	     "rM" ((USItype) (al)),					\
+	     "rM" ((USItype) (bl)))
+#if defined (_PA_RISC1_1)
+#define umul_ppmm(w1, w0, u, v) \
+  do {									\
+    union								\
+      {									\
+	UDItype __f;							\
+	struct {USItype __w1, __w0;} __w1w0;				\
+      } __t;								\
+    __asm__ ("xmpyu %1,%2,%0"						\
+	     : "=x" (__t.__f)						\
+	     : "x" ((USItype) (u)),					\
+	       "x" ((USItype) (v)));					\
+    (w1) = __t.__w1w0.__w1;						\
+    (w0) = __t.__w1w0.__w0;						\
+     } while (0)
+#define UMUL_TIME 8
+#else
+#define UMUL_TIME 30
+#endif
+#define UDIV_TIME 40
+#define count_leading_zeros(count, x) \
+  do {									\
+    USItype __tmp;							\
+    __asm__ (								\
+       "ldi		1,%0\n"						\
+"	extru,=		%1,15,16,%%r0		; Bits 31..16 zero?\n"	\
+"	extru,tr	%1,15,16,%1		; No.  Shift down, skip add.\n"\
+"	ldo		16(%0),%0		; Yes.  Perform add.\n"	\
+"	extru,=		%1,23,8,%%r0		; Bits 15..8 zero?\n"	\
+"	extru,tr	%1,23,8,%1		; No.  Shift down, skip add.\n"\
+"	ldo		8(%0),%0		; Yes.  Perform add.\n"	\
+"	extru,=		%1,27,4,%%r0		; Bits 7..4 zero?\n"	\
+"	extru,tr	%1,27,4,%1		; No.  Shift down, skip add.\n"\
+"	ldo		4(%0),%0		; Yes.  Perform add.\n"	\
+"	extru,=		%1,29,2,%%r0		; Bits 3..2 zero?\n"	\
+"	extru,tr	%1,29,2,%1		; No.  Shift down, skip add.\n"\
+"	ldo		2(%0),%0		; Yes.  Perform add.\n"	\
+"	extru		%1,30,1,%1		; Extract bit 1.\n"	\
+"	sub		%0,%1,%0		; Subtract it.\n"	\
+	: "=r" (count), "=r" (__tmp) : "1" (x));			\
+  } while (0)
+#endif
+
+#if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
+#define smul_ppmm(xh, xl, m0, m1) \
+  do {									\
+    union {DItype __ll;							\
+	   struct {USItype __h, __l;} __i;				\
+	  } __x;							\
+    __asm__ ("lr %N0,%1\n\tmr %0,%2"					\
+	     : "=&r" (__x.__ll)						\
+	     : "r" (m0), "r" (m1));					\
+    (xh) = __x.__i.__h; (xl) = __x.__i.__l;				\
+  } while (0)
+#define sdiv_qrnnd(q, r, n1, n0, d) \
+  do {									\
+    union {DItype __ll;							\
+	   struct {USItype __h, __l;} __i;				\
+	  } __x;							\
+    __x.__i.__h = n1; __x.__i.__l = n0;					\
+    __asm__ ("dr %0,%2"							\
+	     : "=r" (__x.__ll)						\
+	     : "0" (__x.__ll), "r" (d));				\
+    (q) = __x.__i.__l; (r) = __x.__i.__h;				\
+  } while (0)
+#endif
+
+#if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("addl %5,%1\n\tadcl %3,%0"					\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%0" ((USItype) (ah)),					\
+	     "g" ((USItype) (bh)),					\
+	     "%1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("subl %5,%1\n\tsbbl %3,%0"					\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "0" ((USItype) (ah)),					\
+	     "g" ((USItype) (bh)),					\
+	     "1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("mull %3"							\
+	   : "=a" ((USItype) (w0)),					\
+	     "=d" ((USItype) (w1))					\
+	   : "%0" ((USItype) (u)),					\
+	     "rm" ((USItype) (v)))
+#define udiv_qrnnd(q, r, n1, n0, dv) \
+  __asm__ ("divl %4"							\
+	   : "=a" ((USItype) (q)),					\
+	     "=d" ((USItype) (r))					\
+	   : "0" ((USItype) (n0)),					\
+	     "1" ((USItype) (n1)),					\
+	     "rm" ((USItype) (dv)))
+#define count_leading_zeros(count, x) \
+  do {									\
+    USItype __cbtmp;							\
+    __asm__ ("bsrl %1,%0"						\
+	     : "=r" (__cbtmp) : "rm" ((USItype) (x)));			\
+    (count) = __cbtmp ^ 31;						\
+  } while (0)
+#define count_trailing_zeros(count, x) \
+  __asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x)))
+#define UMUL_TIME 40
+#define UDIV_TIME 40
+#endif /* 80x86 */
+
+#if defined (__i960__) && W_TYPE_SIZE == 32
+#define umul_ppmm(w1, w0, u, v) \
+  ({union {UDItype __ll;						\
+	   struct {USItype __l, __h;} __i;				\
+	  } __xx;							\
+  __asm__ ("emul	%2,%1,%0"					\
+	   : "=d" (__xx.__ll)						\
+	   : "%dI" ((USItype) (u)),					\
+	     "dI" ((USItype) (v)));					\
+  (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
+#define __umulsidi3(u, v) \
+  ({UDItype __w;							\
+    __asm__ ("emul	%2,%1,%0"					\
+	     : "=d" (__w)						\
+	     : "%dI" ((USItype) (u)),					\
+	       "dI" ((USItype) (v)));					\
+    __w; })
+#endif /* __i960__ */
+
+#if defined (__M32R__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  /* The cmp clears the condition bit.  */ \
+  __asm__ ("cmp %0,%0\n\taddx %%5,%1\n\taddx %%3,%0"			\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%0" ((USItype) (ah)),					\
+	     "r" ((USItype) (bh)),					\
+	     "%1" ((USItype) (al)),					\
+	     "r" ((USItype) (bl))					\
+	   : "cbit")
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  /* The cmp clears the condition bit.  */ \
+  __asm__ ("cmp %0,%0\n\tsubx %5,%1\n\tsubx %3,%0"			\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "0" ((USItype) (ah)),					\
+	     "r" ((USItype) (bh)),					\
+	     "1" ((USItype) (al)),					\
+	     "r" ((USItype) (bl))					\
+	   : "cbit")
+#endif /* __M32R__ */
+
+#if defined (__mc68000__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"				\
+	   : "=d" ((USItype) (sh)),					\
+	     "=&d" ((USItype) (sl))					\
+	   : "%0" ((USItype) (ah)),					\
+	     "d" ((USItype) (bh)),					\
+	     "%1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0"				\
+	   : "=d" ((USItype) (sh)),					\
+	     "=&d" ((USItype) (sl))					\
+	   : "0" ((USItype) (ah)),					\
+	     "d" ((USItype) (bh)),					\
+	     "1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+
+/* The '020, '030, '040 and CPU32 have 32x32->64 and 64/32->32q-32r.  */
+#if defined (__mc68020__) || defined(mc68020) \
+	|| defined(__mc68030__) || defined(mc68030) \
+	|| defined(__mc68040__) || defined(mc68040) \
+	|| defined(__mcpu32__) || defined(mcpu32)
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("mulu%.l %3,%1:%0"						\
+	   : "=d" ((USItype) (w0)),					\
+	     "=d" ((USItype) (w1))					\
+	   : "%0" ((USItype) (u)),					\
+	     "dmi" ((USItype) (v)))
+#define UMUL_TIME 45
+#define udiv_qrnnd(q, r, n1, n0, d) \
+  __asm__ ("divu%.l %4,%1:%0"						\
+	   : "=d" ((USItype) (q)),					\
+	     "=d" ((USItype) (r))					\
+	   : "0" ((USItype) (n0)),					\
+	     "1" ((USItype) (n1)),					\
+	     "dmi" ((USItype) (d)))
+#define UDIV_TIME 90
+#define sdiv_qrnnd(q, r, n1, n0, d) \
+  __asm__ ("divs%.l %4,%1:%0"						\
+	   : "=d" ((USItype) (q)),					\
+	     "=d" ((USItype) (r))					\
+	   : "0" ((USItype) (n0)),					\
+	     "1" ((USItype) (n1)),					\
+	     "dmi" ((USItype) (d)))
+
+#else /* not mc68020 */
+#if !defined(__mcf5200__)
+/* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX.  */
+#define umul_ppmm(xh, xl, a, b) \
+  __asm__ ("| Inlined umul_ppmm\n"					\
+	   "	move%.l	%2,%/d0\n"					\
+	   "	move%.l	%3,%/d1\n"					\
+	   "	move%.l	%/d0,%/d2\n"					\
+	   "	swap	%/d0\n"						\
+	   "	move%.l	%/d1,%/d3\n"					\
+	   "	swap	%/d1\n"						\
+	   "	move%.w	%/d2,%/d4\n"					\
+	   "	mulu	%/d3,%/d4\n"					\
+	   "	mulu	%/d1,%/d2\n"					\
+	   "	mulu	%/d0,%/d3\n"					\
+	   "	mulu	%/d0,%/d1\n"					\
+	   "	move%.l	%/d4,%/d0\n"					\
+	   "	eor%.w	%/d0,%/d0\n"					\
+	   "	swap	%/d0\n"						\
+	   "	add%.l	%/d0,%/d2\n"					\
+	   "	add%.l	%/d3,%/d2\n"					\
+	   "	jcc	1f\n"						\
+	   "	add%.l	%#65536,%/d1\n"					\
+	   "1:	swap	%/d2\n"						\
+	   "	moveq	%#0,%/d0\n"					\
+	   "	move%.w	%/d2,%/d0\n"					\
+	   "	move%.w	%/d4,%/d2\n"					\
+	   "	move%.l	%/d2,%1\n"					\
+	   "	add%.l	%/d1,%/d0\n"					\
+	   "	move%.l	%/d0,%0"					\
+	   : "=g" ((USItype) (xh)),					\
+	     "=g" ((USItype) (xl))					\
+	   : "g" ((USItype) (a)),					\
+	     "g" ((USItype) (b))					\
+	   : "d0", "d1", "d2", "d3", "d4")
+#define UMUL_TIME 100
+#define UDIV_TIME 400
+#endif /* not mcf5200 */
+#endif /* not mc68020 */
+
+/* The '020, '030, '040 and '060 have bitfield insns.  */
+#if defined (__mc68020__) || defined(mc68020) \
+	|| defined(__mc68030__) || defined(mc68030) \
+	|| defined(__mc68040__) || defined(mc68040) \
+	|| defined(__mc68060__) || defined(mc68060)
+#define count_leading_zeros(count, x) \
+  __asm__ ("bfffo %1{%b2:%b2},%0"					\
+	   : "=d" ((USItype) (count))					\
+	   : "od" ((USItype) (x)), "n" (0))
+#endif
+#endif /* mc68000 */
+
+#if defined (__m88000__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3"			\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%rJ" ((USItype) (ah)),					\
+	     "rJ" ((USItype) (bh)),					\
+	     "%rJ" ((USItype) (al)),					\
+	     "rJ" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3"			\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "rJ" ((USItype) (ah)),					\
+	     "rJ" ((USItype) (bh)),					\
+	     "rJ" ((USItype) (al)),					\
+	     "rJ" ((USItype) (bl)))
+#define count_leading_zeros(count, x) \
+  do {									\
+    USItype __cbtmp;							\
+    __asm__ ("ff1 %0,%1"						\
+	     : "=r" (__cbtmp)						\
+	     : "r" ((USItype) (x)));					\
+    (count) = __cbtmp ^ 31;						\
+  } while (0)
+#define COUNT_LEADING_ZEROS_0 63 /* sic */
+#if defined (__mc88110__)
+#define umul_ppmm(wh, wl, u, v) \
+  do {									\
+    union {UDItype __ll;						\
+	   struct {USItype __h, __l;} __i;				\
+	  } __xx;							\
+    __asm__ ("mulu.d	%0,%1,%2"					\
+	     : "=r" (__xx.__ll)						\
+	     : "r" ((USItype) (u)),					\
+	       "r" ((USItype) (v)));					\
+    (wh) = __xx.__i.__h;						\
+    (wl) = __xx.__i.__l;						\
+  } while (0)
+#define udiv_qrnnd(q, r, n1, n0, d) \
+  ({union {UDItype __ll;						\
+	   struct {USItype __h, __l;} __i;				\
+	  } __xx;							\
+  USItype __q;								\
+  __xx.__i.__h = (n1); __xx.__i.__l = (n0);				\
+  __asm__ ("divu.d %0,%1,%2"						\
+	   : "=r" (__q)							\
+	   : "r" (__xx.__ll),						\
+	     "r" ((USItype) (d)));					\
+  (r) = (n0) - __q * (d); (q) = __q; })
+#define UMUL_TIME 5
+#define UDIV_TIME 25
+#else
+#define UMUL_TIME 17
+#define UDIV_TIME 150
+#endif /* __mc88110__ */
+#endif /* __m88000__ */
+
+/* Test for gcc >= maj.min, as per __GNUC_PREREQ in glibc */
+#if defined (__GNUC__) && defined (__GNUC_MINOR__)
+#define __GNUC_PREREQ(maj, min) \
+	((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min))
+#else
+#define __GNUC_PREREQ(maj, min)  0
+#endif
+
+/***************************************
+ **************  MIPS  *****************
+ ***************************************/
+#if defined (__mips__) && W_TYPE_SIZE == 32
+#if __GNUC_PREREQ (4,4)
+/* adapted from OpenWRT 001-mips-h-constraint.patch */
+#define umul_ppmm(w1, w0, u, v) \
+  do {                                                                  \
+    UDItype __ll = (UDItype)(u) * (v);                                  \
+    w1 = __ll >> 32;                                                    \
+    w0 = __ll;                                                          \
+  } while (0)
+#else
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("multu %2,%3"                                                \
+	   : "=l" ((USItype)(w0)),                                      \
+	     "=h" ((USItype)(w1))                                       \
+	   : "d" ((USItype)(u)),                                        \
+	     "d" ((USItype)(v)))
+#endif
+
+#define UMUL_TIME 10
+#define UDIV_TIME 100
+#endif /* __mips__ */
+
+#if defined (__ns32000__) && W_TYPE_SIZE == 32
+#define umul_ppmm(w1, w0, u, v) \
+  ({union {UDItype __ll;						\
+	   struct {USItype __l, __h;} __i;				\
+	  } __xx;							\
+  __asm__ ("meid %2,%0"							\
+	   : "=g" (__xx.__ll)						\
+	   : "%0" ((USItype) (u)),					\
+	     "g" ((USItype) (v)));					\
+  (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
+#define __umulsidi3(u, v) \
+  ({UDItype __w;							\
+    __asm__ ("meid %2,%0"						\
+	     : "=g" (__w)						\
+	     : "%0" ((USItype) (u)),					\
+	       "g" ((USItype) (v)));					\
+    __w; })
+#define udiv_qrnnd(q, r, n1, n0, d) \
+  ({union {UDItype __ll;						\
+	   struct {USItype __l, __h;} __i;				\
+	  } __xx;							\
+  __xx.__i.__h = (n1); __xx.__i.__l = (n0);				\
+  __asm__ ("deid %2,%0"							\
+	   : "=g" (__xx.__ll)						\
+	   : "0" (__xx.__ll),						\
+	     "g" ((USItype) (d)));					\
+  (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
+#define count_trailing_zeros(count,x) \
+  do {									\
+    __asm__ ("ffsd     %2,%0"						\
+            : "=r" ((USItype) (count))					\
+            : "0" ((USItype) 0),					\
+              "r" ((USItype) (x)));					\
+  } while (0)
+#endif /* __ns32000__ */
+
+/* FIXME: We should test _IBMR2 here when we add assembly support for the
+   system vendor compilers.
+   FIXME: What's needed for gcc PowerPC VxWorks?  __vxworks__ is not good
+   enough, since that hits ARM and m68k too.  */
+#if (defined (_ARCH_PPC)	/* AIX */				\
+     || defined (_ARCH_PWR)	/* AIX */				\
+     || defined (_ARCH_COM)	/* AIX */				\
+     || defined (__powerpc__)	/* gcc */				\
+     || defined (__POWERPC__)	/* BEOS */				\
+     || defined (__ppc__)	/* Darwin */				\
+     || defined (PPC)		/* GNU/Linux, SysV */			\
+     ) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  do {									\
+    if (__builtin_constant_p (bh) && (bh) == 0)				\
+      __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2"		\
+	     : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0)		\
+      __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2"		\
+	     : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
+    else								\
+      __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3"		\
+	     : "=r" (sh), "=&r" (sl)					\
+	     : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl));		\
+  } while (0)
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  do {									\
+    if (__builtin_constant_p (ah) && (ah) == 0)				\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2"	\
+	       : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0)		\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2"	\
+	       : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == 0)			\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2"		\
+	       : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0)		\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2"		\
+	       : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
+    else								\
+      __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2"	\
+	       : "=r" (sh), "=&r" (sl)					\
+	       : "r" (ah), "r" (bh), "rI" (al), "r" (bl));		\
+  } while (0)
+#define count_leading_zeros(count, x) \
+  __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
+#define COUNT_LEADING_ZEROS_0 32
+#if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
+  || defined (__ppc__) || defined (PPC) || defined (__vxworks__)
+#define umul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    USItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1));	\
+    (pl) = __m0 * __m1;							\
+  } while (0)
+#define UMUL_TIME 15
+#define smul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    SItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1));	\
+    (pl) = __m0 * __m1;							\
+  } while (0)
+#define SMUL_TIME 14
+#define UDIV_TIME 120
+#elif defined (_ARCH_PWR)
+#define UMUL_TIME 8
+#define smul_ppmm(xh, xl, m0, m1) \
+  __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
+#define SMUL_TIME 4
+#define sdiv_qrnnd(q, r, nh, nl, d) \
+  __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
+#define UDIV_TIME 100
+#endif
+#endif /* 32-bit POWER architecture variants.  */
+
+/* We should test _IBMR2 here when we add assembly support for the system
+   vendor compilers.  */
+#if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  do {									\
+    if (__builtin_constant_p (bh) && (bh) == 0)				\
+      __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2"		\
+	     : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0)		\
+      __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2"		\
+	     : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
+    else								\
+      __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3"		\
+	     : "=r" (sh), "=&r" (sl)					\
+	     : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl));		\
+  } while (0)
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  do {									\
+    if (__builtin_constant_p (ah) && (ah) == 0)				\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2"	\
+	       : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0)		\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2"	\
+	       : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == 0)			\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2"		\
+	       : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0)		\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2"		\
+	       : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
+    else								\
+      __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2"	\
+	       : "=r" (sh), "=&r" (sl)					\
+	       : "r" (ah), "r" (bh), "rI" (al), "r" (bl));		\
+  } while (0)
+#define count_leading_zeros(count, x) \
+  __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
+#define COUNT_LEADING_ZEROS_0 64
+#define umul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    UDItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1));	\
+    (pl) = __m0 * __m1;							\
+  } while (0)
+#define UMUL_TIME 15
+#define smul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    DItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1));	\
+    (pl) = __m0 * __m1;							\
+  } while (0)
+#define SMUL_TIME 14  /* ??? */
+#define UDIV_TIME 120 /* ??? */
+#endif /* 64-bit PowerPC.  */
+
+#if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("a %1,%5\n\tae %0,%3"					\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%0" ((USItype) (ah)),					\
+	     "r" ((USItype) (bh)),					\
+	     "%1" ((USItype) (al)),					\
+	     "r" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("s %1,%5\n\tse %0,%3"					\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "0" ((USItype) (ah)),					\
+	     "r" ((USItype) (bh)),					\
+	     "1" ((USItype) (al)),					\
+	     "r" ((USItype) (bl)))
+#define umul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    USItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ (								\
+       "s	r2,r2\n"						\
+"	mts	r10,%2\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	cas	%0,r2,r0\n"						\
+"	mfs	r10,%1"							\
+	     : "=r" ((USItype) (ph)),					\
+	       "=r" ((USItype) (pl))					\
+	     : "%r" (__m0),						\
+		"r" (__m1)						\
+	     : "r2");							\
+    (ph) += ((((SItype) __m0 >> 31) & __m1)				\
+	     + (((SItype) __m1 >> 31) & __m0));				\
+  } while (0)
+#define UMUL_TIME 20
+#define UDIV_TIME 200
+#define count_leading_zeros(count, x) \
+  do {									\
+    if ((x) >= 0x10000)							\
+      __asm__ ("clz	%0,%1"						\
+	       : "=r" ((USItype) (count))				\
+	       : "r" ((USItype) (x) >> 16));				\
+    else								\
+      {									\
+	__asm__ ("clz	%0,%1"						\
+		 : "=r" ((USItype) (count))				\
+		 : "r" ((USItype) (x)));					\
+	(count) += 16;							\
+      }									\
+  } while (0)
+#endif
+
+#if defined (__sh2__) && W_TYPE_SIZE == 32
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ (								\
+       "dmulu.l	%2,%3\n\tsts	macl,%1\n\tsts	mach,%0"		\
+	   : "=r" ((USItype)(w1)),					\
+	     "=r" ((USItype)(w0))					\
+	   : "r" ((USItype)(u)),					\
+	     "r" ((USItype)(v))						\
+	   : "macl", "mach")
+#define UMUL_TIME 5
+#endif
+
+#if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
+#define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
+#define count_leading_zeros(count, x) \
+  do									\
+    {									\
+      UDItype x_ = (USItype)(x);					\
+      SItype c_;							\
+									\
+      __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_));			\
+      (count) = c_ - 31;						\
+    }									\
+  while (0)
+#define COUNT_LEADING_ZEROS_0 32
+#endif
+
+#if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
+    && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0"				\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%rJ" ((USItype) (ah)),					\
+	     "rI" ((USItype) (bh)),					\
+	     "%rJ" ((USItype) (al)),					\
+	     "rI" ((USItype) (bl))					\
+	   __CLOBBER_CC)
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0"				\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "rJ" ((USItype) (ah)),					\
+	     "rI" ((USItype) (bh)),					\
+	     "rJ" ((USItype) (al)),					\
+	     "rI" ((USItype) (bl))					\
+	   __CLOBBER_CC)
+#if defined (__sparc_v8__)
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
+	   : "=r" ((USItype) (w1)),					\
+	     "=r" ((USItype) (w0))					\
+	   : "r" ((USItype) (u)),					\
+	     "r" ((USItype) (v)))
+#define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
+  __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
+	   : "=&r" ((USItype) (__q)),					\
+	     "=&r" ((USItype) (__r))					\
+	   : "r" ((USItype) (__n1)),					\
+	     "r" ((USItype) (__n0)),					\
+	     "r" ((USItype) (__d)))
+#else
+#if defined (__sparclite__)
+/* This has hardware multiply but not divide.  It also has two additional
+   instructions scan (ffs from high bit) and divscc.  */
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
+	   : "=r" ((USItype) (w1)),					\
+	     "=r" ((USItype) (w0))					\
+	   : "r" ((USItype) (u)),					\
+	     "r" ((USItype) (v)))
+#define udiv_qrnnd(q, r, n1, n0, d) \
+  __asm__ ("! Inlined udiv_qrnnd\n"					\
+"	wr	%%g0,%2,%%y	! Not a delayed write for sparclite\n"	\
+"	tst	%%g0\n"							\
+"	divscc	%3,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%0\n"						\
+"	rd	%%y,%1\n"						\
+"	bl,a 1f\n"							\
+"	add	%1,%4,%1\n"						\
+"1:	! End of inline udiv_qrnnd"					\
+	   : "=r" ((USItype) (q)),					\
+	     "=r" ((USItype) (r))					\
+	   : "r" ((USItype) (n1)),					\
+	     "r" ((USItype) (n0)),					\
+	     "rI" ((USItype) (d))					\
+	   : "g1" __AND_CLOBBER_CC)
+#define UDIV_TIME 37
+#define count_leading_zeros(count, x) \
+  do {                                                                  \
+  __asm__ ("scan %1,1,%0"                                               \
+           : "=r" ((USItype) (count))                                   \
+           : "r" ((USItype) (x)));					\
+  } while (0)
+/* Early sparclites return 63 for an argument of 0, but they warn that future
+   implementations might change this.  Therefore, leave COUNT_LEADING_ZEROS_0
+   undefined.  */
+#else
+/* SPARC without integer multiplication and divide instructions.
+   (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("! Inlined umul_ppmm\n"					\
+"	wr	%%g0,%2,%%y	! SPARC has 0-3 delay insn after a wr\n"\
+"	sra	%3,31,%%o5	! Don't move this insn\n"		\
+"	and	%2,%%o5,%%o5	! Don't move this insn\n"		\
+"	andcc	%%g0,0,%%g1	! Don't move this insn\n"		\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,0,%%g1\n"						\
+"	add	%%g1,%%o5,%0\n"						\
+"	rd	%%y,%1"							\
+	   : "=r" ((USItype) (w1)),					\
+	     "=r" ((USItype) (w0))					\
+	   : "%rI" ((USItype) (u)),					\
+	     "r" ((USItype) (v))						\
+	   : "g1", "o5" __AND_CLOBBER_CC)
+#define UMUL_TIME 39		/* 39 instructions */
+/* It's quite necessary to add this much assembler for the sparc.
+   The default udiv_qrnnd (in C) is more than 10 times slower!  */
+#define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
+  __asm__ ("! Inlined udiv_qrnnd\n"					\
+"	mov	32,%%g1\n"						\
+"	subcc	%1,%2,%%g0\n"						\
+"1:	bcs	5f\n"							\
+"	 addxcc %0,%0,%0	! shift n1n0 and a q-bit in lsb\n"	\
+"	sub	%1,%2,%1	! this kills msb of n\n"		\
+"	addx	%1,%1,%1	! so this can't give carry\n"		\
+"	subcc	%%g1,1,%%g1\n"						\
+"2:	bne	1b\n"							\
+"	 subcc	%1,%2,%%g0\n"						\
+"	bcs	3f\n"							\
+"	 addxcc %0,%0,%0	! shift n1n0 and a q-bit in lsb\n"	\
+"	b	3f\n"							\
+"	 sub	%1,%2,%1	! this kills msb of n\n"		\
+"4:	sub	%1,%2,%1\n"						\
+"5:	addxcc	%1,%1,%1\n"						\
+"	bcc	2b\n"							\
+"	 subcc	%%g1,1,%%g1\n"						\
+"! Got carry from n.  Subtract next step to cancel this carry.\n"	\
+"	bne	4b\n"							\
+"	 addcc	%0,%0,%0	! shift n1n0 and a 0-bit in lsb\n"	\
+"	sub	%1,%2,%1\n"						\
+"3:	xnor	%0,0,%0\n"						\
+"	! End of inline udiv_qrnnd"					\
+	   : "=&r" ((USItype) (__q)),					\
+	     "=&r" ((USItype) (__r))					\
+	   : "r" ((USItype) (__d)),					\
+	     "1" ((USItype) (__n1)),					\
+	     "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
+#define UDIV_TIME (3+7*32)	/* 7 instructions/iteration. 32 iterations.  */
+#endif /* __sparclite__ */
+#endif /* __sparc_v8__ */
+#endif /* sparc32 */
+
+#if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
+    && W_TYPE_SIZE == 64
+#define add_ssaaaa(sh, sl, ah, al, bh, bl)				\
+  __asm__ ("addcc %r4,%5,%1\n\t"					\
+   	   "add %r2,%3,%0\n\t"						\
+   	   "bcs,a,pn %%xcc, 1f\n\t"					\
+   	   "add %0, 1, %0\n"						\
+	   "1:"								\
+	   : "=r" ((UDItype)(sh)),				      	\
+	     "=&r" ((UDItype)(sl))				      	\
+	   : "%rJ" ((UDItype)(ah)),				     	\
+	     "rI" ((UDItype)(bh)),				      	\
+	     "%rJ" ((UDItype)(al)),				     	\
+	     "rI" ((UDItype)(bl))				       	\
+	   __CLOBBER_CC)
+
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) 				\
+  __asm__ ("subcc %r4,%5,%1\n\t"					\
+   	   "sub %r2,%3,%0\n\t"						\
+   	   "bcs,a,pn %%xcc, 1f\n\t"					\
+   	   "sub %0, 1, %0\n\t"						\
+	   "1:"								\
+	   : "=r" ((UDItype)(sh)),				      	\
+	     "=&r" ((UDItype)(sl))				      	\
+	   : "rJ" ((UDItype)(ah)),				     	\
+	     "rI" ((UDItype)(bh)),				      	\
+	     "rJ" ((UDItype)(al)),				     	\
+	     "rI" ((UDItype)(bl))				       	\
+	   __CLOBBER_CC)
+
+#define umul_ppmm(wh, wl, u, v)						\
+  do {									\
+	  UDItype tmp1, tmp2, tmp3, tmp4;				\
+	  __asm__ __volatile__ (					\
+		   "srl %7,0,%3\n\t"					\
+		   "mulx %3,%6,%1\n\t"					\
+		   "srlx %6,32,%2\n\t"					\
+		   "mulx %2,%3,%4\n\t"					\
+		   "sllx %4,32,%5\n\t"					\
+		   "srl %6,0,%3\n\t"					\
+		   "sub %1,%5,%5\n\t"					\
+		   "srlx %5,32,%5\n\t"					\
+		   "addcc %4,%5,%4\n\t"					\
+		   "srlx %7,32,%5\n\t"					\
+		   "mulx %3,%5,%3\n\t"					\
+		   "mulx %2,%5,%5\n\t"					\
+		   "sethi %%hi(0x80000000),%2\n\t"			\
+		   "addcc %4,%3,%4\n\t"					\
+		   "srlx %4,32,%4\n\t"					\
+		   "add %2,%2,%2\n\t"					\
+		   "movcc %%xcc,%%g0,%2\n\t"				\
+		   "addcc %5,%4,%5\n\t"					\
+		   "sllx %3,32,%3\n\t"					\
+		   "add %1,%3,%1\n\t"					\
+		   "add %5,%2,%0"					\
+	   : "=r" ((UDItype)(wh)),					\
+	     "=&r" ((UDItype)(wl)),					\
+	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4)	\
+	   : "r" ((UDItype)(u)),					\
+	     "r" ((UDItype)(v))						\
+	   __CLOBBER_CC);						\
+  } while (0)
+#define UMUL_TIME 96
+#define UDIV_TIME 230
+#endif /* sparc64 */
+
+#if defined (__vax__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("addl2 %5,%1\n\tadwc %3,%0"					\
+	   : "=g" ((USItype) (sh)),					\
+	     "=&g" ((USItype) (sl))					\
+	   : "%0" ((USItype) (ah)),					\
+	     "g" ((USItype) (bh)),					\
+	     "%1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("subl2 %5,%1\n\tsbwc %3,%0"					\
+	   : "=g" ((USItype) (sh)),					\
+	     "=&g" ((USItype) (sl))					\
+	   : "0" ((USItype) (ah)),					\
+	     "g" ((USItype) (bh)),					\
+	     "1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+#define umul_ppmm(xh, xl, m0, m1) \
+  do {									\
+    union {								\
+	UDItype __ll;							\
+	struct {USItype __l, __h;} __i;					\
+      } __xx;								\
+    USItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("emul %1,%2,$0,%0"						\
+	     : "=r" (__xx.__ll)						\
+	     : "g" (__m0),						\
+	       "g" (__m1));						\
+    (xh) = __xx.__i.__h;						\
+    (xl) = __xx.__i.__l;						\
+    (xh) += ((((SItype) __m0 >> 31) & __m1)				\
+	     + (((SItype) __m1 >> 31) & __m0));				\
+  } while (0)
+#define sdiv_qrnnd(q, r, n1, n0, d) \
+  do {									\
+    union {DItype __ll;							\
+	   struct {SItype __l, __h;} __i;				\
+	  } __xx;							\
+    __xx.__i.__h = n1; __xx.__i.__l = n0;				\
+    __asm__ ("ediv %3,%2,%0,%1"						\
+	     : "=g" (q), "=g" (r)					\
+	     : "g" (__xx.__ll), "g" (d));				\
+  } while (0)
+#endif /* __vax__ */
+
+#if defined (__z8000__) && W_TYPE_SIZE == 16
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("add	%H1,%H5\n\tadc	%H0,%H3"				\
+	   : "=r" ((unsigned int)(sh)),					\
+	     "=&r" ((unsigned int)(sl))					\
+	   : "%0" ((unsigned int)(ah)),					\
+	     "r" ((unsigned int)(bh)),					\
+	     "%1" ((unsigned int)(al)),					\
+	     "rQR" ((unsigned int)(bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("sub	%H1,%H5\n\tsbc	%H0,%H3"				\
+	   : "=r" ((unsigned int)(sh)),					\
+	     "=&r" ((unsigned int)(sl))					\
+	   : "0" ((unsigned int)(ah)),					\
+	     "r" ((unsigned int)(bh)),					\
+	     "1" ((unsigned int)(al)),					\
+	     "rQR" ((unsigned int)(bl)))
+#define umul_ppmm(xh, xl, m0, m1) \
+  do {									\
+    union {long int __ll;						\
+	   struct {unsigned int __h, __l;} __i;				\
+	  } __xx;							\
+    unsigned int __m0 = (m0), __m1 = (m1);				\
+    __asm__ ("mult	%S0,%H3"					\
+	     : "=r" (__xx.__i.__h),					\
+	       "=r" (__xx.__i.__l)					\
+	     : "%1" (__m0),						\
+	       "rQR" (__m1));						\
+    (xh) = __xx.__i.__h; (xl) = __xx.__i.__l;				\
+    (xh) += ((((signed int) __m0 >> 15) & __m1)				\
+	     + (((signed int) __m1 >> 15) & __m0));			\
+  } while (0)
+#endif /* __z8000__ */
+
+#endif /* __GNUC__ */
+
+/* If this machine has no inline assembler, use C macros.  */
+
+#if !defined (add_ssaaaa)
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  do {									\
+    UWtype __x;								\
+    __x = (al) + (bl);							\
+    (sh) = (ah) + (bh) + (__x < (al));					\
+    (sl) = __x;								\
+  } while (0)
+#endif
+
+#if !defined (sub_ddmmss)
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  do {									\
+    UWtype __x;								\
+    __x = (al) - (bl);							\
+    (sh) = (ah) - (bh) - (__x > (al));					\
+    (sl) = __x;								\
+  } while (0)
+#endif
+
+/* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
+   smul_ppmm.  */
+#if !defined (umul_ppmm) && defined (smul_ppmm)
+#define umul_ppmm(w1, w0, u, v)						\
+  do {									\
+    UWtype __w1;							\
+    UWtype __xm0 = (u), __xm1 = (v);					\
+    smul_ppmm (__w1, w0, __xm0, __xm1);					\
+    (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1)		\
+		+ (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0);		\
+  } while (0)
+#endif
+
+/* If we still don't have umul_ppmm, define it using plain C.  */
+#if !defined (umul_ppmm)
+#define umul_ppmm(w1, w0, u, v)						\
+  do {									\
+    UWtype __x0, __x1, __x2, __x3;					\
+    UHWtype __ul, __vl, __uh, __vh;					\
+									\
+    __ul = __ll_lowpart (u);						\
+    __uh = __ll_highpart (u);						\
+    __vl = __ll_lowpart (v);						\
+    __vh = __ll_highpart (v);						\
+									\
+    __x0 = (UWtype) __ul * __vl;					\
+    __x1 = (UWtype) __ul * __vh;					\
+    __x2 = (UWtype) __uh * __vl;					\
+    __x3 = (UWtype) __uh * __vh;					\
+									\
+    __x1 += __ll_highpart (__x0);/* this can't give carry */		\
+    __x1 += __x2;		/* but this indeed can */		\
+    if (__x1 < __x2)		/* did we get it? */			\
+      __x3 += __ll_B;		/* yes, add it in the proper pos.  */	\
+									\
+    (w1) = __x3 + __ll_highpart (__x1);					\
+    (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0);		\
+  } while (0)
+#endif
+
+#if !defined (__umulsidi3)
+#define __umulsidi3(u, v) \
+  ({DWunion __w;							\
+    umul_ppmm (__w.s.high, __w.s.low, u, v);				\
+    __w.ll; })
+#endif
+
+/* Define this unconditionally, so it can be used for debugging.  */
+#define __udiv_qrnnd_c(q, r, n1, n0, d) \
+  do {									\
+    UWtype __d1, __d0, __q1, __q0;					\
+    UWtype __r1, __r0, __m;						\
+    __d1 = __ll_highpart (d);						\
+    __d0 = __ll_lowpart (d);						\
+									\
+    __r1 = (n1) % __d1;							\
+    __q1 = (n1) / __d1;							\
+    __m = (UWtype) __q1 * __d0;						\
+    __r1 = __r1 * __ll_B | __ll_highpart (n0);				\
+    if (__r1 < __m)							\
+      {									\
+	__q1--, __r1 += (d);						\
+	if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
+	  if (__r1 < __m)						\
+	    __q1--, __r1 += (d);					\
+      }									\
+    __r1 -= __m;							\
+									\
+    __r0 = __r1 % __d1;							\
+    __q0 = __r1 / __d1;							\
+    __m = (UWtype) __q0 * __d0;						\
+    __r0 = __r0 * __ll_B | __ll_lowpart (n0);				\
+    if (__r0 < __m)							\
+      {									\
+	__q0--, __r0 += (d);						\
+	if (__r0 >= (d))						\
+	  if (__r0 < __m)						\
+	    __q0--, __r0 += (d);					\
+      }									\
+    __r0 -= __m;							\
+									\
+    (q) = (UWtype) __q1 * __ll_B | __q0;				\
+    (r) = __r0;								\
+  } while (0)
+
+/* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
+   __udiv_w_sdiv (defined in libgcc or elsewhere).  */
+#if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
+#define udiv_qrnnd(q, r, nh, nl, d) \
+  do {									\
+    USItype __r;							\
+    (q) = __udiv_w_sdiv (&__r, nh, nl, d);				\
+    (r) = __r;								\
+  } while (0)
+#endif
+
+/* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c.  */
+#if !defined (udiv_qrnnd)
+#define UDIV_NEEDS_NORMALIZATION 1
+#define udiv_qrnnd __udiv_qrnnd_c
+#endif
+
+#if !defined (count_leading_zeros)
+extern const UQItype __clz_tab[];
+#define count_leading_zeros(count, x) \
+  do {									\
+    UWtype __xr = (x);							\
+    UWtype __a;								\
+									\
+    if (W_TYPE_SIZE <= 32)						\
+      {									\
+	__a = __xr < ((UWtype)1<<2*__BITS4)				\
+	  ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4)			\
+	  : (__xr < ((UWtype)1<<3*__BITS4) ?  2*__BITS4 : 3*__BITS4);	\
+      }									\
+    else								\
+      {									\
+	for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8)			\
+	  if (((__xr >> __a) & 0xff) != 0)				\
+	    break;							\
+      }									\
+									\
+    (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a);		\
+  } while (0)
+#define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
+#endif
+
+#if !defined (count_trailing_zeros)
+/* Define count_trailing_zeros using count_leading_zeros.  The latter might be
+   defined in asm, but if it is not, the C version above is good enough.  */
+#define count_trailing_zeros(count, x) \
+  do {									\
+    UWtype __ctz_x = (x);						\
+    UWtype __ctz_c;							\
+    count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x);			\
+    (count) = W_TYPE_SIZE - 1 - __ctz_c;				\
+  } while (0)
+#endif
+
+#ifndef UDIV_NEEDS_NORMALIZATION
+#define UDIV_NEEDS_NORMALIZATION 0
+#endif
diff --git a/arch/mips/lib/mips-atomic.c b/arch/mips/lib/mips-atomic.c
new file mode 100644
index 0000000..cd160be
--- /dev/null
+++ b/arch/mips/lib/mips-atomic.c
@@ -0,0 +1,176 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
+ * Copyright (C) 1996 by Paul M. Antoine
+ * Copyright (C) 1999 Silicon Graphics
+ * Copyright (C) 2000 MIPS Technologies, Inc.
+ */
+#include <asm/irqflags.h>
+#include <asm/hazards.h>
+#include <linux/compiler.h>
+#include <linux/preempt.h>
+#include <linux/export.h>
+
+#if !defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT_SMTC)
+
+/*
+ * For cli() we have to insert nops to make sure that the new value
+ * has actually arrived in the status register before the end of this
+ * macro.
+ * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
+ * no nops at all.
+ */
+/*
+ * For TX49, operating only IE bit is not enough.
+ *
+ * If mfc0 $12 follows store and the mfc0 is last instruction of a
+ * page and fetching the next instruction causes TLB miss, the result
+ * of the mfc0 might wrongly contain EXL bit.
+ *
+ * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
+ *
+ * Workaround: mask EXL bit of the result or place a nop before mfc0.
+ */
+__asm__(
+	"	.macro	arch_local_irq_disable\n"
+	"	.set	push						\n"
+	"	.set	noat						\n"
+#ifdef CONFIG_MIPS_MT_SMTC
+	"	mfc0	$1, $2, 1					\n"
+	"	ori	$1, 0x400					\n"
+	"	.set	noreorder					\n"
+	"	mtc0	$1, $2, 1					\n"
+#elif defined(CONFIG_CPU_MIPSR2)
+	/* see irqflags.h for inline function */
+#else
+	"	mfc0	$1,$12						\n"
+	"	ori	$1,0x1f						\n"
+	"	xori	$1,0x1f						\n"
+	"	.set	noreorder					\n"
+	"	mtc0	$1,$12						\n"
+#endif
+	"	irq_disable_hazard					\n"
+	"	.set	pop						\n"
+	"	.endm							\n");
+
+notrace void arch_local_irq_disable(void)
+{
+	preempt_disable();
+	__asm__ __volatile__(
+		"arch_local_irq_disable"
+		: /* no outputs */
+		: /* no inputs */
+		: "memory");
+	preempt_enable();
+}
+EXPORT_SYMBOL(arch_local_irq_disable);
+
+
+__asm__(
+	"	.macro	arch_local_irq_save result			\n"
+	"	.set	push						\n"
+	"	.set	reorder						\n"
+	"	.set	noat						\n"
+#ifdef CONFIG_MIPS_MT_SMTC
+	"	mfc0	\\result, $2, 1					\n"
+	"	ori	$1, \\result, 0x400				\n"
+	"	.set	noreorder					\n"
+	"	mtc0	$1, $2, 1					\n"
+	"	andi	\\result, \\result, 0x400			\n"
+#elif defined(CONFIG_CPU_MIPSR2)
+	/* see irqflags.h for inline function */
+#else
+	"	mfc0	\\result, $12					\n"
+	"	ori	$1, \\result, 0x1f				\n"
+	"	xori	$1, 0x1f					\n"
+	"	.set	noreorder					\n"
+	"	mtc0	$1, $12						\n"
+#endif
+	"	irq_disable_hazard					\n"
+	"	.set	pop						\n"
+	"	.endm							\n");
+
+notrace unsigned long arch_local_irq_save(void)
+{
+	unsigned long flags;
+	preempt_disable();
+	asm volatile("arch_local_irq_save\t%0"
+		     : "=r" (flags)
+		     : /* no inputs */
+		     : "memory");
+	preempt_enable();
+	return flags;
+}
+EXPORT_SYMBOL(arch_local_irq_save);
+
+
+__asm__(
+	"	.macro	arch_local_irq_restore flags			\n"
+	"	.set	push						\n"
+	"	.set	noreorder					\n"
+	"	.set	noat						\n"
+#ifdef CONFIG_MIPS_MT_SMTC
+	"mfc0	$1, $2, 1						\n"
+	"andi	\\flags, 0x400						\n"
+	"ori	$1, 0x400						\n"
+	"xori	$1, 0x400						\n"
+	"or	\\flags, $1						\n"
+	"mtc0	\\flags, $2, 1						\n"
+#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
+	/* see irqflags.h for inline function */
+#elif defined(CONFIG_CPU_MIPSR2)
+	/* see irqflags.h for inline function */
+#else
+	"	mfc0	$1, $12						\n"
+	"	andi	\\flags, 1					\n"
+	"	ori	$1, 0x1f					\n"
+	"	xori	$1, 0x1f					\n"
+	"	or	\\flags, $1					\n"
+	"	mtc0	\\flags, $12					\n"
+#endif
+	"	irq_disable_hazard					\n"
+	"	.set	pop						\n"
+	"	.endm							\n");
+
+notrace void arch_local_irq_restore(unsigned long flags)
+{
+	unsigned long __tmp1;
+
+#ifdef CONFIG_MIPS_MT_SMTC
+	/*
+	 * SMTC kernel needs to do a software replay of queued
+	 * IPIs, at the cost of branch and call overhead on each
+	 * local_irq_restore()
+	 */
+	if (unlikely(!(flags & 0x0400)))
+		smtc_ipi_replay();
+#endif
+	preempt_disable();
+	__asm__ __volatile__(
+		"arch_local_irq_restore\t%0"
+		: "=r" (__tmp1)
+		: "0" (flags)
+		: "memory");
+	preempt_enable();
+}
+EXPORT_SYMBOL(arch_local_irq_restore);
+
+
+notrace void __arch_local_irq_restore(unsigned long flags)
+{
+	unsigned long __tmp1;
+
+	preempt_disable();
+	__asm__ __volatile__(
+		"arch_local_irq_restore\t%0"
+		: "=r" (__tmp1)
+		: "0" (flags)
+		: "memory");
+	preempt_enable();
+}
+EXPORT_SYMBOL(__arch_local_irq_restore);
+
+#endif /* !defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT_SMTC) */
diff --git a/arch/mips/lib/r3k_dump_tlb.c b/arch/mips/lib/r3k_dump_tlb.c
index 9cee907..b58ab11 100644
--- a/arch/mips/lib/r3k_dump_tlb.c
+++ b/arch/mips/lib/r3k_dump_tlb.c
@@ -34,7 +34,7 @@ static void dump_tlb(int first, int last)
 		entrylo0 = read_c0_entrylo0();
 
 		/* Unused entries have a virtual address of KSEG0.  */
-		if ((entryhi & 0xffffe000) != 0x80000000
+		if ((entryhi & 0xfffff000) != 0x80000000
 		    && (entryhi & 0xfc0) == asid) {
 			/*
 			 * Only print entries in use
@@ -43,7 +43,7 @@ static void dump_tlb(int first, int last)
 
 			printk("va=%08lx asid=%08lx"
 			       "  [pa=%06lx n=%d d=%d v=%d g=%d]",
-			       (entryhi & 0xffffe000),
+			       (entryhi & 0xfffff000),
 			       entryhi & 0xfc0,
 			       entrylo0 & PAGE_MASK,
 			       (entrylo0 & (1 << 11)) ? 1 : 0,
diff --git a/arch/mips/lib/strncpy_user.S b/arch/mips/lib/strncpy_user.S
index 7201b2f..502a6ea 100644
--- a/arch/mips/lib/strncpy_user.S
+++ b/arch/mips/lib/strncpy_user.S
@@ -3,7 +3,8 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (c) 1996, 1999 by Ralf Baechle
+ * Copyright (C) 1996, 1999 by Ralf Baechle
+ * Copyright (C) 2011 MIPS Technologies, Inc.
  */
 #include <linux/errno.h>
 #include <asm/asm.h>
@@ -33,25 +34,25 @@ LEAF(__strncpy_from_user_asm)
 	bnez		v0, .Lfault
 
 FEXPORT(__strncpy_from_user_nocheck_asm)
-	move		v0, zero
+	move		t0, zero
 	move		v1, a1
-	.set		noreorder
-1:	EX(lbu, t0, (v1), .Lfault)
+1:	EX(lbu, v0, (v1), .Lfault)
 	PTR_ADDIU	v1, 1
 	R10KCBARRIER(0(ra))
-	beqz		t0, 2f
-	 sb		t0, (a0)
-	PTR_ADDIU	v0, 1
-	.set		reorder
+	sb		v0, (a0)
+	beqz		v0, 2f
+	PTR_ADDIU	t0, 1
 	PTR_ADDIU	a0, 1
-	bne		v0, a2, 1b
-2:	PTR_ADDU	t0, a1, v0
-	xor		t0, a1
-	bltz		t0, .Lfault
+	bne		t0, a2, 1b
+2:	PTR_ADDU	v0, a1, t0
+	xor		v0, a1
+	bltz		v0, .Lfault
+	move		v0, t0
 	jr		ra			# return n
 	END(__strncpy_from_user_asm)
 
-.Lfault:	li		v0, -EFAULT
+.Lfault:
+	li		v0, -EFAULT
 	jr		ra
 
 	.section	__ex_table,"a"
diff --git a/arch/mips/lib/strnlen_user.S b/arch/mips/lib/strnlen_user.S
index 6445716..7febbac 100644
--- a/arch/mips/lib/strnlen_user.S
+++ b/arch/mips/lib/strnlen_user.S
@@ -35,9 +35,11 @@ FEXPORT(__strnlen_user_nocheck_asm)
 	PTR_ADDU	a1, a0			# stop pointer
 1:	beq		v0, a1, 1f		# limit reached?
 	EX(lb, t0, (v0), .Lfault)
-	PTR_ADDU	v0, 1
+	.set		noreorder
 	bnez		t0, 1b
-1:	PTR_SUBU	v0, a0
+1:	 PTR_ADDU	v0, 1
+	.set		reorder
+	PTR_SUBU	v0, a0
 	jr		ra
 	END(__strnlen_user_asm)
 
diff --git a/arch/mips/lib/udivdi3.c b/arch/mips/lib/udivdi3.c
new file mode 100644
index 0000000..828fc20
--- /dev/null
+++ b/arch/mips/lib/udivdi3.c
@@ -0,0 +1,266 @@
+/* More subroutines needed by GCC output code on some machines.  */
+/* Compile this one with gcc.  */
+/* Copyright (C) 1989, 92-98, 1999 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* As a special exception, if you link this library with other files,
+   some of which are compiled with GCC, to produce an executable,
+   this library does not by itself cause the resulting executable
+   to be covered by the GNU General Public License.
+   This exception does not however invalidate any other reasons why
+   the executable file might be covered by the GNU General Public License.
+ */
+/* support functions required by the kernel. based on code from gcc-2.95.3 */
+/* I Molton     29/07/01 */
+
+#include <linux/module.h>
+
+#define BITS_PER_UNIT  8
+#define SI_TYPE_SIZE (sizeof (SItype) * BITS_PER_UNIT)
+
+typedef unsigned int UQItype    __attribute__ ((mode (QI)));
+typedef          int SItype     __attribute__ ((mode (SI)));
+typedef unsigned int USItype    __attribute__ ((mode (SI)));
+typedef          int DItype     __attribute__ ((mode (DI)));
+typedef          int word_type 	__attribute__ ((mode (__word__)));
+typedef unsigned int UDItype    __attribute__ ((mode (DI)));
+
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+  struct DIstruct {USItype low; SItype high;};
+#else
+  struct DIstruct {SItype high; USItype low;};
+#endif
+
+typedef union
+{
+  struct DIstruct s;
+  DItype ll;
+} DIunion;
+
+#include "longlong.h"
+
+const UQItype __clz_tab[] =
+{
+  0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
+  6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
+  7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
+  7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
+  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
+  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
+  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
+  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
+};
+
+UDItype
+__udivmoddi4 (UDItype n, UDItype d, UDItype *rp)
+{
+  DIunion ww;
+  DIunion nn, dd;
+  DIunion rr;
+  USItype d0, d1, n0, n1, n2;
+  USItype q0, q1;
+  USItype b, bm;
+
+  nn.ll = n;
+  dd.ll = d;
+
+  d0 = dd.s.low;
+  d1 = dd.s.high;
+  n0 = nn.s.low;
+  n1 = nn.s.high;
+
+  if (d1 == 0)
+    {
+      if (d0 > n1)
+        {
+          /* 0q = nn / 0D */
+
+          count_leading_zeros (bm, d0);
+
+          if (bm != 0)
+            {
+              /* Normalize, i.e. make the most significant bit of the
+                 denominator set.  */
+
+              d0 = d0 << bm;
+              n1 = (n1 << bm) | (n0 >> (SI_TYPE_SIZE - bm));
+              n0 = n0 << bm;
+            }
+
+          udiv_qrnnd (q0, n0, n1, n0, d0);
+          q1 = 0;
+
+          /* Remainder in n0 >> bm.  */
+        }
+      else
+        {
+          /* qq = NN / 0d */
+
+          if (d0 == 0)
+            d0 = 1 / d0;        /* Divide intentionally by zero.  */
+
+          count_leading_zeros (bm, d0);
+
+          if (bm == 0)
+            {
+              /* From (n1 >= d0) /\ (the most significant bit of d0 is set),
+                 conclude (the most significant bit of n1 is set) /\ (the
+                 leading quotient digit q1 = 1).
+
+                 This special case is necessary, not an optimization.
+                 (Shifts counts of SI_TYPE_SIZE are undefined.)  */
+
+              n1 -= d0;
+              q1 = 1;
+            }
+          else
+            {
+              /* Normalize.  */
+
+              b = SI_TYPE_SIZE - bm;
+
+              d0 = d0 << bm;
+              n2 = n1 >> b;
+              n1 = (n1 << bm) | (n0 >> b);
+              n0 = n0 << bm;
+
+              udiv_qrnnd (q1, n1, n2, n1, d0);
+            }
+
+          /* n1 != d0...  */
+
+          udiv_qrnnd (q0, n0, n1, n0, d0);
+
+          /* Remainder in n0 >> bm.  */
+        }
+
+      if (rp != 0)
+        {
+          rr.s.low = n0 >> bm;
+          rr.s.high = 0;
+          *rp = rr.ll;
+        }
+    }
+  else
+    {
+      if (d1 > n1)
+        {
+          /* 00 = nn / DD */
+
+          q0 = 0;
+          q1 = 0;
+
+          /* Remainder in n1n0.  */
+          if (rp != 0)
+            {
+              rr.s.low = n0;
+              rr.s.high = n1;
+              *rp = rr.ll;
+            }
+        }
+      else
+        {
+          /* 0q = NN / dd */
+
+          count_leading_zeros (bm, d1);
+          if (bm == 0)
+            {
+              /* From (n1 >= d1) /\ (the most significant bit of d1 is set),
+                 conclude (the most significant bit of n1 is set) /\ (the
+                 quotient digit q0 = 0 or 1).
+
+                 This special case is necessary, not an optimization.  */
+
+              /* The condition on the next line takes advantage of that
+                 n1 >= d1 (true due to program flow).  */
+              if (n1 > d1 || n0 >= d0)
+                {
+                  q0 = 1;
+                  sub_ddmmss (n1, n0, n1, n0, d1, d0);
+                }
+              else
+                q0 = 0;
+
+              q1 = 0;
+
+              if (rp != 0)
+                {
+                  rr.s.low = n0;
+                  rr.s.high = n1;
+                  *rp = rr.ll;
+                }
+            }
+          else
+            {
+              USItype m1, m0;
+              /* Normalize.  */
+
+              b = SI_TYPE_SIZE - bm;
+
+              d1 = (d1 << bm) | (d0 >> b);
+              d0 = d0 << bm;
+              n2 = n1 >> b;
+              n1 = (n1 << bm) | (n0 >> b);
+              n0 = n0 << bm;
+
+              udiv_qrnnd (q0, n1, n2, n1, d1);
+              umul_ppmm (m1, m0, q0, d0);
+
+              if (m1 > n1 || (m1 == n1 && m0 > n0))
+                {
+                  q0--;
+                  sub_ddmmss (m1, m0, m1, m0, d1, d0);
+                }
+
+              q1 = 0;
+
+              /* Remainder in (n1n0 - m1m0) >> bm.  */
+              if (rp != 0)
+                {
+                  sub_ddmmss (n1, n0, n1, n0, m1, m0);
+                  rr.s.low = (n1 << b) | (n0 >> bm);
+                  rr.s.high = n1 >> bm;
+                  *rp = rr.ll;
+                }
+            }
+        }
+    }
+
+  ww.s.low = q0;
+  ww.s.high = q1;
+  return ww.ll;
+}
+
+UDItype
+__udivdi3 (UDItype n, UDItype d)
+{
+  return __udivmoddi4 (n, d, (UDItype *) 0);
+}
+EXPORT_SYMBOL(__udivdi3);
+
+UDItype
+__umoddi3 (UDItype u, UDItype v)
+{
+  UDItype w;
+
+  (void) __udivmoddi4 (u ,v, &w);
+
+  return w;
+}
+
diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile
index ce415f7..4fc66f5 100644
--- a/arch/mips/loongson/common/Makefile
+++ b/arch/mips/loongson/common/Makefile
@@ -3,15 +3,13 @@
 #
 
 obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \
-    pci.o bonito-irq.o mem.o machtype.o platform.o
+    pci.o bonito-irq.o mem.o machtype.o platform.o serial.o
 obj-$(CONFIG_GENERIC_GPIO) += gpio.o
 
 #
 # Serial port support
 #
 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
-loongson-serial-$(CONFIG_SERIAL_8250) := serial.o
-obj-y += $(loongson-serial-m) $(loongson-serial-y)
 obj-$(CONFIG_LOONGSON_UART_BASE) += uart_base.o
 obj-$(CONFIG_LOONGSON_MC146818) += rtc.o
 
diff --git a/arch/mips/loongson/common/cs5536/cs5536_isa.c b/arch/mips/loongson/common/cs5536/cs5536_isa.c
index 4d9f65a..7b31ea7 100644
--- a/arch/mips/loongson/common/cs5536/cs5536_isa.c
+++ b/arch/mips/loongson/common/cs5536/cs5536_isa.c
@@ -13,6 +13,7 @@
  * option) any later version.
  */
 
+#include <linux/pci.h>
 #include <cs5536/cs5536.h>
 #include <cs5536/cs5536_pci.h>
 
@@ -314,3 +315,16 @@ u32 pci_isa_read_reg(int reg)
 
 	return conf_data;
 }
+
+/*
+ * The mfgpt timer interrupt is running early, so we must keep the south bridge
+ * mmio always enabled. Otherwise we may race with the PCI configuration which
+ * may temporarily disable it. When that happens and the timer interrupt fires,
+ * we are not able to clear it and the system will hang.
+ */
+static void cs5536_isa_mmio_always_on(struct pci_dev *dev)
+{
+	dev->mmio_always_on = 1;
+}
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA,
+	PCI_CLASS_BRIDGE_ISA, 8, cs5536_isa_mmio_always_on);
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index a03bf00..91630dd 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -171,16 +171,17 @@ static int isBranchInstr(mips_instruction * i)
  * In the Linux kernel, we support selection of FPR format on the
  * basis of the Status.FR bit.  If an FPU is not present, the FR bit
  * is hardwired to zero, which would imply a 32-bit FPU even for
- * 64-bit CPUs.  For 64-bit kernels with no FPU we use TIF_32BIT_REGS
- * as a proxy for the FR bit so that a 64-bit FPU is emulated.  In any
- * case, for a 32-bit kernel which uses the O32 MIPS ABI, only the
- * even FPRs are used (Status.FR = 0).
+ * 64-bit CPUs so we rather look at TIF_32BIT_REGS.
+ * FPU emu is slow and bulky and optimizing this function offers fairly
+ * sizeable benefits so we try to be clever and make this function return
+ * a constant whenever possible, that is on 64-bit kernels without O32
+ * compatibility enabled and on 32-bit kernels.
  */
 static inline int cop1_64bit(struct pt_regs *xcp)
 {
-	if (cpu_has_fpu)
-		return xcp->cp0_status & ST0_FR;
-#ifdef CONFIG_64BIT
+#if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32)
+	return 1;
+#elif defined(CONFIG_64BIT) && defined(CONFIG_MIPS32_O32)
 	return !test_thread_flag(TIF_32BIT_REGS);
 #else
 	return 0;
@@ -814,10 +815,10 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 		break;
 	}
 
-	case 0x7:		/* 7 */
-		if (MIPSInst_FUNC(ir) != pfetch_op) {
+	case 0x3:
+		if (MIPSInst_FUNC(ir) != pfetch_op)
 			return SIGILL;
-		}
+
 		/* ignore prefx operation */
 		break;
 
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 4aa2028..18a41b1 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -3,8 +3,8 @@
 #
 
 obj-y				+= cache.o dma-default.o extable.o fault.o \
-				   gup.o init.o mmap.o page.o tlbex.o \
-				   tlbex-fault.o uasm.o
+				   gup.o init.o mmap.o page.o page-funcs.o \
+				   tlbex.o tlbex-fault.o uasm.o
 
 obj-$(CONFIG_32BIT)		+= ioremap.o pgtable-32.o
 obj-$(CONFIG_64BIT)		+= pgtable-64.o
@@ -12,7 +12,11 @@ obj-$(CONFIG_HIGHMEM)		+= highmem.o
 obj-$(CONFIG_HUGETLB_PAGE)	+= hugetlbpage.o
 
 obj-$(CONFIG_CPU_LOONGSON2)	+= c-r4k.o cex-gen.o tlb-r4k.o
+ifeq ($(CONFIG_BRCMSTB),y)
+obj-y				+= c-brcmstb.o cex-gen.o tlb-r4k.o
+else
 obj-$(CONFIG_CPU_MIPS32)	+= c-r4k.o cex-gen.o tlb-r4k.o
+endif
 obj-$(CONFIG_CPU_MIPS64)	+= c-r4k.o cex-gen.o tlb-r4k.o
 obj-$(CONFIG_CPU_NEVADA)	+= c-r4k.o cex-gen.o tlb-r4k.o
 obj-$(CONFIG_CPU_R10000)	+= c-r4k.o cex-gen.o tlb-r4k.o
diff --git a/arch/mips/mm/c-brcmstb.c b/arch/mips/mm/c-brcmstb.c
new file mode 100644
index 0000000..a5b3b1e
--- /dev/null
+++ b/arch/mips/mm/c-brcmstb.c
@@ -0,0 +1,490 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/pfn.h>
+#include <linux/bitops.h>
+#include <linux/module.h>
+#include <linux/seq_file.h>
+#include <linux/highmem.h>
+
+#include <asm/barrier.h>
+#include <asm/bcache.h>
+#include <asm/bootinfo.h>
+#include <asm/cache.h>
+#include <asm/cacheops.h>
+#include <asm/cpu.h>
+#include <asm/cpu-features.h>
+#include <asm/io.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/r4kcache.h>
+#include <asm/mmu_context.h>
+#include <asm/war.h>
+#include <asm/cacheflush.h>
+#include <linux/brcmstb/brcmstb.h>
+#include <dma-coherence.h>
+
+/*
+ * R4K-style cache flush functions
+ *
+ * BMIPS5000 uses an optimized implementation from this file
+ * Everything uses uses a mostly-stock c-r4k.c
+ */
+
+#if !defined(CONFIG_CPU_BMIPS5000)
+#include "c-r4k.c"
+#else /* !defined(CONFIG_CPU_BMIPS5000) */
+
+static unsigned long icache_size __read_mostly;
+static unsigned long dcache_size __read_mostly;
+static unsigned long scache_size __read_mostly;
+
+/*
+ * Dummy cache handling routines for machines without boardcaches
+ */
+static void cache_noop(void) {}
+
+static struct bcache_ops no_sc_ops = {
+	.bc_enable = (void *)cache_noop,
+	.bc_disable = (void *)cache_noop,
+	.bc_wback_inv = (void *)cache_noop,
+	.bc_inv = (void *)cache_noop,
+};
+
+struct bcache_ops *bcops = &no_sc_ops;
+
+static void (* r4k_blast_dcache_page)(unsigned long addr);
+static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
+static void (* r4k_blast_dcache)(void);
+static void (* r4k_blast_icache_page)(unsigned long addr);
+static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
+static void (* r4k_blast_icache)(void);
+static void (* r4k_blast_scache_page)(unsigned long addr);
+static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
+static void (* r4k_blast_scache)(void);
+
+static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
+{
+	blast_dcache32_page(addr);
+}
+
+static void r4k___flush_cache_all(void)
+{
+	/* L2 flush implicitly flushes L1 */
+	r4k_blast_scache();
+	__sync();
+}
+
+static void r4k_noop(void)
+{
+}
+
+static void r4k_instruction_hazard(void)
+{
+	__sync();
+	__sync();
+	__asm__ __volatile__(
+	"	nop; nop; nop; nop; nop; nop; nop; nop\n"
+	"	nop; nop; nop; nop; nop; nop; nop; nop\n"
+	"	nop; nop; nop; nop; nop; nop; nop; nop\n"
+	"	nop; nop; nop; nop; nop; nop; nop; nop\n"
+	: : : "memory");
+}
+
+static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
+{
+	/* Catch bad driver code */
+	BUG_ON(size == 0);
+
+	/* L2 flush implicitly flushes L1 */
+	if (size >= scache_size)
+		r4k_blast_scache();
+	else
+		bc_wback_inv(addr, size);
+
+	__sync();
+}
+
+static char *way_string[] __cpuinitdata = { NULL, "direct mapped", "2-way",
+	"3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
+};
+
+static void __cpuinit probe_pcache(void)
+{
+	struct cpuinfo_mips *c = &current_cpu_data;
+	unsigned int config = read_c0_config();
+	unsigned long config1;
+	unsigned int lsize;
+
+	switch (c->cputype) {
+	default:
+		if (!(config & MIPS_CONF_M))
+			panic("Don't know how to probe P-caches on this cpu.");
+
+		/*
+		 * So we seem to be a MIPS32 or MIPS64 CPU
+		 * So let's probe the I-cache ...
+		 */
+		config1 = read_c0_config1();
+
+		if ((lsize = ((config1 >> 19) & 7)))
+			c->icache.linesz = 2 << lsize;
+		else
+			c->icache.linesz = lsize;
+		c->icache.sets = 64 << ((config1 >> 22) & 7);
+		c->icache.ways = 1 + ((config1 >> 16) & 7);
+
+		icache_size = c->icache.sets *
+		              c->icache.ways *
+		              c->icache.linesz;
+		c->icache.waybit = __ffs(icache_size/c->icache.ways);
+
+		if (config & 0x8)		/* VI bit */
+			c->icache.flags |= MIPS_CACHE_VTAG;
+
+		/*
+		 * Now probe the MIPS32 / MIPS64 data cache.
+		 */
+		c->dcache.flags = 0;
+
+		if ((lsize = ((config1 >> 10) & 7)))
+			c->dcache.linesz = 2 << lsize;
+		else
+			c->dcache.linesz= lsize;
+		c->dcache.sets = 64 << ((config1 >> 13) & 7);
+		c->dcache.ways = 1 + ((config1 >> 7) & 7);
+
+		dcache_size = c->dcache.sets *
+		              c->dcache.ways *
+		              c->dcache.linesz;
+		c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
+
+		c->options |= MIPS_CPU_PREFETCH;
+		break;
+	}
+
+	/* compute a couple of other cache variables */
+	c->icache.waysize = icache_size / c->icache.ways;
+	c->dcache.waysize = dcache_size / c->dcache.ways;
+
+	c->icache.sets = c->icache.linesz ?
+		icache_size / (c->icache.linesz * c->icache.ways) : 0;
+	c->dcache.sets = c->dcache.linesz ?
+		dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
+
+	printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
+	       icache_size >> 10,
+	       cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
+	       way_string[c->icache.ways], c->icache.linesz);
+
+	printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
+	       dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz);
+}
+
+extern int mips_sc_init(void);
+
+static void __cpuinit setup_scache(void)
+{
+	struct cpuinfo_mips *c = &current_cpu_data;
+
+	if (mips_sc_init ()) {
+		scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
+		printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
+		       scache_size >> 10,
+		       way_string[c->scache.ways], c->scache.linesz);
+	} else {
+		panic("c-r4k cache functions require L2 enabled");
+	}
+	return;
+}
+
+static int __cpuinitdata cca = -1;
+
+static int __init cca_setup(char *str)
+{
+	get_option(&str, &cca);
+
+	return 1;
+}
+
+__setup("cca=", cca_setup);
+
+static void __cpuinit coherency_setup(void)
+{
+	if (cca < 0 || cca > 7)
+		cca = read_c0_config() & CONF_CM_CMASK;
+	_page_cachable_default = cca << _CACHE_SHIFT;
+
+	pr_debug("Using cache attribute %d\n", cca);
+	change_c0_config(CONF_CM_CMASK, cca);
+}
+
+void __cpuinit r4k_cache_init(void)
+{
+	extern void build_clear_page(void);
+	extern void build_copy_page(void);
+	extern char except_vec2_generic;
+
+	/* Default cache error handler for R4000 and R5000 family */
+	set_uncached_handler (0x100, &except_vec2_generic, 0x80);
+
+	probe_pcache();
+	setup_scache();
+
+	BUG_ON(cpu_icache_line_size() != 64);
+	BUG_ON(cpu_dcache_line_size() != 32);
+	BUG_ON(cpu_scache_line_size() != 128);
+
+	r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
+	r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
+	r4k_blast_dcache = blast_dcache32;
+	r4k_blast_icache_page = blast_icache64_page;
+	r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
+	r4k_blast_icache = blast_icache64;
+	r4k_blast_scache_page = blast_scache128_page;
+	r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
+	r4k_blast_scache = blast_scache128;
+
+	/* SWLINUX-2630: align to the way size (8KB) on Zephyr */
+	shm_align_mask = max_t(unsigned long,
+			       current_cpu_data.dcache.waysize, PAGE_SIZE) - 1;
+
+	__flush_cache_vmap	= r4k___flush_cache_all;
+	__flush_cache_vunmap	= r4k___flush_cache_all;
+
+	flush_cache_all		= (void *)r4k_noop;
+	__flush_cache_all	= r4k___flush_cache_all;
+	flush_cache_mm		= (void *)r4k_noop;
+	flush_cache_page	= (void *)r4k_instruction_hazard;
+	flush_cache_range	= (void *)r4k_instruction_hazard;
+
+	flush_cache_sigtramp	= (void *)r4k_noop;
+	flush_icache_all	= (void *)r4k_noop;
+	local_flush_data_cache_page	= (void *)r4k_instruction_hazard;
+	flush_data_cache_page	= (void *)r4k_instruction_hazard;
+	flush_icache_range	= (void *)r4k_instruction_hazard;
+	local_flush_icache_range	= (void *)r4k_instruction_hazard;
+
+	_dma_cache_wback_inv	= r4k_dma_cache_wback_inv;
+	_dma_cache_wback	= r4k_dma_cache_wback_inv;
+	_dma_cache_inv		= r4k_dma_cache_wback_inv;
+
+	build_clear_page();
+	build_copy_page();
+	r4k___flush_cache_all();
+	coherency_setup();
+}
+
+#endif /* !defined(CONFIG_CPU_BMIPS5000) */
+
+/*
+ * Fine-grained cacheflush() syscall for usermode Nexus
+ */
+int brcm_cacheflush(unsigned long addr, unsigned long bytes,
+	unsigned int cache)
+{
+#if !defined(CONFIG_BRCM_ZSCM_L2)
+	/* partial RAC invalidate is not supported */
+	if (cache == RACACHE) {
+		brcm_inv_prefetch(0, 0);
+		return 0;
+	}
+#else
+	/*
+	 * SWLINUX-2607, BMIPS5000_5200-ES100-R: Flush JTB and CRS on
+	 * user-initiated invalidations, in case a JIT buffer with mixed
+	 * code+data is getting rewritten.  This helps prevent a possible
+	 * CPU hang from prefetching invalid instructions.
+	 */
+	write_c0_brcm_action(4 << 16); /* reset JTB this thread */
+	write_c0_brcm_action(5 << 16); /* reset JTB other thread */
+	write_c0_brcm_action(6 << 16); /* reset CRS this thread */
+	write_c0_brcm_action(7 << 16); /* reset CRS other thread */
+#endif
+	/* ICACHE/BCACHE is handled by the standard implementation */
+	if (cache & ICACHE) {
+		flush_icache_range(addr, addr + bytes);
+		return 0;
+	}
+
+	/* New DCACHE implementation flushes D$/L2 out to RAM for DMA */
+	if (cache & DCACHE) {
+		unsigned long pg = addr & PAGE_MASK, end = addr + bytes;
+
+		if (bytes == 0 || (bytes >= dcache_size)) {
+			r4k_blast_dcache();
+			r4k_blast_scache();
+			__sync();
+			return 0;
+		}
+
+		down_read(&current->mm->mmap_sem);
+		while (pg < end) {
+			pgd_t *pgdp = pgd_offset(current->mm, pg);
+			pud_t *pudp = pud_offset(pgdp, pg);
+			pmd_t *pmdp = pmd_offset(pudp, pg);
+			pte_t *ptep = pte_offset(pmdp, pg);
+
+			if (!(pte_val(*ptep) & _PAGE_PRESENT)) {
+				up_read(&current->mm->mmap_sem);
+				return -EFAULT;
+			}
+
+#if !defined(CONFIG_BRCM_ZSCM_L2)
+			r4k_blast_dcache_page(pg);
+#endif
+			r4k_blast_scache_page(pg);
+			pg += PAGE_SIZE;
+		}
+		up_read(&current->mm->mmap_sem);
+	}
+
+	if (cache & RACACHE)
+		brcm_inv_prefetch(addr, bytes);
+
+	__sync();
+	return 0;
+}
+EXPORT_SYMBOL(brcm_cacheflush);
+
+/*
+ * Flush RAC or prefetch lines after DMA from device
+ */
+void brcm_inv_prefetch(unsigned long addr, unsigned long size)
+{
+#if defined(CONFIG_CPU_BMIPS3300)
+	DEV_SET_RB(__BMIPS_GET_CBR() + BMIPS_RAC_CONFIG, 0x100);
+#elif defined(CONFIG_CPU_BMIPS4380)
+	DEV_SET_RB(__BMIPS_GET_CBR() + BMIPS_RAC_CONFIG, 0x100);
+#elif defined(CONFIG_BRCM_ZSCM_L2)
+	unsigned int linesz = cpu_scache_line_size();
+	unsigned long addr0 = addr, addr1;
+
+	BUG_ON(size == 0);
+
+	addr0 &= ~(linesz - 1);
+	addr1 = (addr0 + size - 1) & ~(linesz - 1);
+
+	protected_writeback_scache_line(addr0);
+	if (likely(addr1 != addr0))
+		protected_writeback_scache_line(addr1);
+	else
+		return;
+
+	addr0 += linesz;
+	if (likely(addr1 != addr0))
+		protected_writeback_scache_line(addr0);
+	else
+		return;
+
+	addr1 -= linesz;
+	if (likely(addr1 > addr0))
+		protected_writeback_scache_line(addr0);
+#endif
+}
+EXPORT_SYMBOL(brcm_inv_prefetch);
+
+/*
+ * Hooks for extra RAC/prefetch flush after DMA
+ */
+static inline void __brcm_sync(struct page *page,
+	unsigned long offset, size_t size, enum dma_data_direction direction)
+{
+	size_t left = size;
+
+	if (direction == DMA_TO_DEVICE)
+		return;
+
+	do {
+		size_t len = left;
+
+		if (PageHighMem(page)) {
+			void *addr;
+
+			if (offset + len > PAGE_SIZE) {
+				if (offset >= PAGE_SIZE) {
+					page += offset >> PAGE_SHIFT;
+					offset &= ~PAGE_MASK;
+				}
+				len = PAGE_SIZE - offset;
+			}
+
+			addr = kmap_atomic(page);
+			brcm_inv_prefetch((unsigned long)addr + offset, len);
+			kunmap_atomic(addr);
+		} else
+			brcm_inv_prefetch((unsigned long)page_address(page) +
+				offset, size);
+		offset = 0;
+		page++;
+		left -= len;
+	} while (left);
+}
+
+void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+	size_t size, int dir)
+{
+	unsigned long pa = plat_dma_addr_to_phys(dev, dma_addr);
+	__brcm_sync(pfn_to_page(PFN_DOWN(pa)), pa & ~PAGE_MASK, size, dir);
+}
+
+static void brcm_dma_sync_single_for_cpu(struct device *dev,
+	dma_addr_t dma_handle, size_t size, enum dma_data_direction dir)
+{
+	unsigned long pa = plat_dma_addr_to_phys(dev, dma_handle);
+	__brcm_sync(pfn_to_page(PFN_DOWN(pa)), pa & ~PAGE_MASK, size, dir);
+}
+
+static void brcm_dma_sync_sg_for_cpu(struct device *dev,
+	struct scatterlist *sg, int nelems, enum dma_data_direction direction)
+{
+	int i;
+	for (i = 0; i < nelems; i++, sg++)
+		__brcm_sync(sg_page(sg), sg->offset, sg->length, direction);
+}
+
+static int __init brcm_setup_dma_ops(void)
+{
+	mips_dma_map_ops->sync_single_for_cpu = brcm_dma_sync_single_for_cpu;
+	mips_dma_map_ops->sync_sg_for_cpu = brcm_dma_sync_sg_for_cpu;
+	return 0;
+}
+core_initcall(brcm_setup_dma_ops);
+
+/*
+ * Provide cache details for PI/Nexus
+ */
+void brcm_get_cache_info(struct brcm_cache_info *info)
+{
+	info->max_writeback = cpu_scache_line_size() ? : cpu_dcache_line_size();
+	info->max_writethrough = 0;
+	info->prefetch_enabled = 0;
+
+#if defined(CONFIG_BRCM_ZSCM_L2)
+	/* chips with prefetching L2 */
+	info->prefetch_enabled = 1;
+#elif defined(CONFIG_CPU_BMIPS3300) || defined(CONFIG_CPU_BMIPS4380)
+	/* chips with write-through RAC */
+	info->max_writethrough = info->max_writeback * 4;
+	info->prefetch_enabled = 1;
+#endif
+}
+EXPORT_SYMBOL(brcm_get_cache_info);
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index 47037ec..109a2cf 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -134,8 +134,10 @@ static void octeon_flush_cache_sigtramp(unsigned long addr)
 {
 	struct vm_area_struct *vma;
 
+	down_read(&current->mm->mmap_sem);
 	vma = find_vma(current->mm, addr);
 	octeon_flush_icache_all_cores(vma);
+	up_read(&current->mm->mmap_sem);
 }
 
 
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index fdd6042..0191c5f7 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -544,7 +544,11 @@ static inline void local_r4k_flush_data_cache_page(void * addr)
 
 static void r4k_flush_data_cache_page(unsigned long addr)
 {
+#ifdef CONFIG_CPU_BMIPS4380
+	if (1) /* TP0/TP1 share the same D$ */
+#else
 	if (in_atomic())
+#endif
 		local_r4k_flush_data_cache_page((void *)addr);
 	else
 		r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr);
@@ -982,7 +986,7 @@ static void __cpuinit probe_pcache(void)
 			c->icache.linesz = 2 << lsize;
 		else
 			c->icache.linesz = lsize;
-		c->icache.sets = 64 << ((config1 >> 22) & 7);
+		c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
 		c->icache.ways = 1 + ((config1 >> 16) & 7);
 
 		icache_size = c->icache.sets *
@@ -1002,7 +1006,7 @@ static void __cpuinit probe_pcache(void)
 			c->dcache.linesz = 2 << lsize;
 		else
 			c->dcache.linesz= lsize;
-		c->dcache.sets = 64 << ((config1 >> 13) & 7);
+		c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
 		c->dcache.ways = 1 + ((config1 >> 7) & 7);
 
 		dcache_size = c->dcache.sets *
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 829320c..a95b75b 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -21,6 +21,10 @@
 #include <asm/cpu.h>
 #include <asm/cpu-features.h>
 
+#ifdef CONFIG_BRCMSTB
+#include <linux/brcmstb/brcmapi.h>
+#endif
+
 /* Cache operations. */
 void (*flush_cache_all)(void);
 void (*__flush_cache_all)(void);
@@ -72,9 +76,12 @@ SYSCALL_DEFINE3(cacheflush, unsigned long, addr, unsigned long, bytes,
 	if (!access_ok(VERIFY_WRITE, (void __user *) addr, bytes))
 		return -EFAULT;
 
+#ifdef CONFIG_BRCMSTB
+	return brcm_cacheflush(addr, bytes, cache);
+#else
 	flush_icache_range(addr, addr + bytes);
-
 	return 0;
+#endif
 }
 
 void __flush_dcache_page(struct page *page)
@@ -118,25 +125,36 @@ void __flush_anon_page(struct page *page, unsigned long vmaddr)
 
 EXPORT_SYMBOL(__flush_anon_page);
 
-void __update_cache(struct vm_area_struct *vma, unsigned long address,
-	pte_t pte)
+static void mips_flush_dcache_from_pte(pte_t pteval, unsigned long address)
 {
 	struct page *page;
-	unsigned long pfn, addr;
-	int exec = (vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc;
+	unsigned long pfn = pte_pfn(pteval);
 
-	pfn = pte_pfn(pte);
 	if (unlikely(!pfn_valid(pfn)))
 		return;
+
 	page = pfn_to_page(pfn);
 	if (page_mapping(page) && Page_dcache_dirty(page)) {
-		addr = (unsigned long) page_address(page);
-		if (exec || pages_do_alias(addr, address & PAGE_MASK))
-			flush_data_cache_page(addr);
+		unsigned long page_addr = (unsigned long) page_address(page);
+
+		if (!cpu_has_ic_fills_f_dc ||
+		    pages_do_alias(page_addr, address & PAGE_MASK))
+			flush_data_cache_page(page_addr);
 		ClearPageDcacheDirty(page);
 	}
 }
 
+void set_pte_at(struct mm_struct *mm, unsigned long addr,
+        pte_t *ptep, pte_t pteval)
+{
+        if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) {
+                if (pte_present(pteval))
+                        mips_flush_dcache_from_pte(pteval, addr);
+        }
+
+        set_pte(ptep, pteval);
+}
+
 unsigned long _page_cachable_default;
 EXPORT_SYMBOL(_page_cachable_default);
 
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index f395d5d..2d7b3a4 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -22,6 +22,10 @@
 
 #include <dma-coherence.h>
 
+#ifdef CONFIG_BRCMSTB
+#include <linux/brcmstb/brcmapi.h>
+#endif
+
 static inline struct page *dma_addr_to_page(struct device *dev,
 	dma_addr_t dma_addr)
 {
@@ -59,19 +63,20 @@ static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp)
 	else
 #endif
 #if defined(CONFIG_ZONE_DMA32) && defined(CONFIG_ZONE_DMA)
-	     if (dev->coherent_dma_mask < DMA_BIT_MASK(32))
+	     if (dev == NULL || dev->coherent_dma_mask < DMA_BIT_MASK(32))
 			dma_flag = __GFP_DMA;
 	else if (dev->coherent_dma_mask < DMA_BIT_MASK(64))
 			dma_flag = __GFP_DMA32;
 	else
 #endif
 #if defined(CONFIG_ZONE_DMA32) && !defined(CONFIG_ZONE_DMA)
-	     if (dev->coherent_dma_mask < DMA_BIT_MASK(64))
+	     if (dev == NULL || dev->coherent_dma_mask < DMA_BIT_MASK(64))
 		dma_flag = __GFP_DMA32;
 	else
 #endif
 #if defined(CONFIG_ZONE_DMA) && !defined(CONFIG_ZONE_DMA32)
-	     if (dev->coherent_dma_mask < DMA_BIT_MASK(sizeof(phys_addr_t) * 8))
+	     if (dev == NULL ||
+		 dev->coherent_dma_mask < DMA_BIT_MASK(sizeof(phys_addr_t) * 8))
 		dma_flag = __GFP_DMA;
 	else
 #endif
@@ -119,7 +124,15 @@ static void *mips_dma_alloc_coherent(struct device *dev, size_t size,
 
 		if (!plat_device_is_coherent(dev)) {
 			dma_cache_wback_inv((unsigned long) ret, size);
+#ifdef CONFIG_BRCM_UPPER_768MB
+			if (brcm_map_coherent(*dma_handle, ret, PFN_ALIGN(size),
+					&ret, gfp)) {
+				free_pages((unsigned long)ret, size);
+				ret = NULL;
+			}
+#else
 			ret = UNCAC_ADDR(ret);
+#endif
 		}
 	}
 
@@ -146,8 +159,12 @@ static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr,
 
 	plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL);
 
+#ifdef CONFIG_BRCM_UPPER_768MB
+	addr = (unsigned long)brcm_unmap_coherent(vaddr);
+#else
 	if (!plat_device_is_coherent(dev))
 		addr = CAC_ADDR(addr);
+#endif
 
 	free_pages(addr, get_order(size));
 }
diff --git a/arch/mips/mm/gup.c b/arch/mips/mm/gup.c
index dcfd573..0c832ea 100644
--- a/arch/mips/mm/gup.c
+++ b/arch/mips/mm/gup.c
@@ -12,6 +12,7 @@
 #include <linux/swap.h>
 #include <linux/hugetlb.h>
 
+#include <asm/cpu-features.h>
 #include <asm/pgtable.h>
 
 static inline pte_t gup_get_pte(pte_t *ptep)
@@ -273,7 +274,7 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write,
 	len = (unsigned long) nr_pages << PAGE_SHIFT;
 
 	end = start + len;
-	if (end < start)
+	if (end < start || cpu_has_dc_aliases)
 		goto slow_irqon;
 
 	/* XXX: batch / limit 'nr' */
diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c
index aff5705..da815d2 100644
--- a/arch/mips/mm/highmem.c
+++ b/arch/mips/mm/highmem.c
@@ -1,3 +1,4 @@
+#include <linux/compiler.h>
 #include <linux/module.h>
 #include <linux/highmem.h>
 #include <linux/sched.h>
@@ -67,7 +68,7 @@ EXPORT_SYMBOL(kmap_atomic);
 void __kunmap_atomic(void *kvaddr)
 {
 	unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
-	int type;
+	int type __maybe_unused;
 
 	if (vaddr < FIXADDR_START) { // FIXME
 		pagefault_enable();
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 1a85ba9..e5d0d8a 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -395,6 +395,9 @@ void __init mem_init(void)
 	for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) {
 		struct page *page = pfn_to_page(tmp);
 
+		if (!pfn_valid(tmp))
+			continue;
+
 		if (!page_is_ram(tmp)) {
 			SetPageReserved(page);
 			continue;
diff --git a/arch/mips/mm/ioremap.c b/arch/mips/mm/ioremap.c
index cacfd31..270dfa3 100644
--- a/arch/mips/mm/ioremap.c
+++ b/arch/mips/mm/ioremap.c
@@ -127,6 +127,7 @@ void __iomem * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags)
 	if (!size || last_addr < phys_addr)
 		return NULL;
 
+#if !defined(CONFIG_BRCM_UPPER_768MB)
 	/*
 	 * Map uncached objects in the low 512mb of address space using KSEG1,
 	 * otherwise map using page tables.
@@ -134,6 +135,7 @@ void __iomem * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags)
 	if (IS_LOW512(phys_addr) && IS_LOW512(last_addr) &&
 	    flags == _CACHE_UNCACHED)
 		return (void __iomem *) CKSEG1ADDR(phys_addr);
+#endif
 
 	/*
 	 * Don't allow anybody to remap normal RAM that we're using..
diff --git a/arch/mips/mm/page-funcs.S b/arch/mips/mm/page-funcs.S
new file mode 100644
index 0000000..48a6b38
--- /dev/null
+++ b/arch/mips/mm/page-funcs.S
@@ -0,0 +1,50 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Micro-assembler generated clear_page/copy_page functions.
+ *
+ * Copyright (C) 2012  MIPS Technologies, Inc.
+ * Copyright (C) 2012  Ralf Baechle <ralf@linux-mips.org>
+ */
+#include <asm/asm.h>
+#include <asm/regdef.h>
+
+#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
+#define cpu_clear_page_function_name	clear_page_cpu
+#define cpu_copy_page_function_name	copy_page_cpu
+#else
+#define cpu_clear_page_function_name	clear_page
+#define cpu_copy_page_function_name	copy_page
+#endif
+
+/*
+ * Maximum sizes:
+ *
+ * R4000 128 bytes S-cache:		0x058 bytes
+ * R4600 v1.7:				0x05c bytes
+ * R4600 v2.0:				0x060 bytes
+ * With prefetching, 16 word strides	0x120 bytes
+ */
+EXPORT(__clear_page_start)
+LEAF(cpu_clear_page_function_name)
+1:	j	1b		/* Dummy, will be replaced. */
+	.space 288
+END(cpu_clear_page_function_name)
+EXPORT(__clear_page_end)
+
+/*
+ * Maximum sizes:
+ *
+ * R4000 128 bytes S-cache:		0x11c bytes
+ * R4600 v1.7:				0x080 bytes
+ * R4600 v2.0:				0x07c bytes
+ * With prefetching, 16 word strides	0x540 bytes
+ */
+EXPORT(__copy_page_start)
+LEAF(cpu_copy_page_function_name)
+1:	j	1b		/* Dummy, will be replaced. */
+	.space 1344
+END(cpu_copy_page_function_name)
+EXPORT(__copy_page_end)
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index cc0b6268..98f530e 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -6,6 +6,7 @@
  * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org)
  * Copyright (C) 2007  Maciej W. Rozycki
  * Copyright (C) 2008  Thiemo Seufer
+ * Copyright (C) 2012  MIPS Technologies, Inc.
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
@@ -71,45 +72,6 @@ static struct uasm_reloc __cpuinitdata relocs[5];
 #define cpu_is_r4600_v1_x()	((read_c0_prid() & 0xfffffff0) == 0x00002010)
 #define cpu_is_r4600_v2_x()	((read_c0_prid() & 0xfffffff0) == 0x00002020)
 
-/*
- * Maximum sizes:
- *
- * R4000 128 bytes S-cache:		0x058 bytes
- * R4600 v1.7:				0x05c bytes
- * R4600 v2.0:				0x060 bytes
- * With prefetching, 16 word strides	0x120 bytes
- */
-
-static u32 clear_page_array[0x120 / 4];
-
-#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
-void clear_page_cpu(void *page) __attribute__((alias("clear_page_array")));
-#else
-void clear_page(void *page) __attribute__((alias("clear_page_array")));
-#endif
-
-EXPORT_SYMBOL(clear_page);
-
-/*
- * Maximum sizes:
- *
- * R4000 128 bytes S-cache:		0x11c bytes
- * R4600 v1.7:				0x080 bytes
- * R4600 v2.0:				0x07c bytes
- * With prefetching, 16 word strides	0x540 bytes
- */
-static u32 copy_page_array[0x540 / 4];
-
-#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
-void
-copy_page_cpu(void *to, void *from) __attribute__((alias("copy_page_array")));
-#else
-void copy_page(void *to, void *from) __attribute__((alias("copy_page_array")));
-#endif
-
-EXPORT_SYMBOL(copy_page);
-
-
 static int pref_bias_clear_store __cpuinitdata;
 static int pref_bias_copy_load __cpuinitdata;
 static int pref_bias_copy_store __cpuinitdata;
@@ -282,10 +244,15 @@ static inline void __cpuinit build_clear_pref(u32 **buf, int off)
 		}
 }
 
+extern u32 __clear_page_start;
+extern u32 __clear_page_end;
+extern u32 __copy_page_start;
+extern u32 __copy_page_end;
+
 void __cpuinit build_clear_page(void)
 {
 	int off;
-	u32 *buf = (u32 *)&clear_page_array;
+	u32 *buf = &__clear_page_start;
 	struct uasm_label *l = labels;
 	struct uasm_reloc *r = relocs;
 	int i;
@@ -356,17 +323,17 @@ void __cpuinit build_clear_page(void)
 	uasm_i_jr(&buf, RA);
 	uasm_i_nop(&buf);
 
-	BUG_ON(buf > clear_page_array + ARRAY_SIZE(clear_page_array));
+	BUG_ON(buf > &__clear_page_end);
 
 	uasm_resolve_relocs(relocs, labels);
 
 	pr_debug("Synthesized clear page handler (%u instructions).\n",
-		 (u32)(buf - clear_page_array));
+		 (u32)(buf - &__clear_page_start));
 
 	pr_debug("\t.set push\n");
 	pr_debug("\t.set noreorder\n");
-	for (i = 0; i < (buf - clear_page_array); i++)
-		pr_debug("\t.word 0x%08x\n", clear_page_array[i]);
+	for (i = 0; i < (buf - &__clear_page_start); i++)
+		pr_debug("\t.word 0x%08x\n", (&__clear_page_start)[i]);
 	pr_debug("\t.set pop\n");
 }
 
@@ -427,7 +394,7 @@ static inline void build_copy_store_pref(u32 **buf, int off)
 void __cpuinit build_copy_page(void)
 {
 	int off;
-	u32 *buf = (u32 *)&copy_page_array;
+	u32 *buf = &__copy_page_start;
 	struct uasm_label *l = labels;
 	struct uasm_reloc *r = relocs;
 	int i;
@@ -595,21 +562,23 @@ void __cpuinit build_copy_page(void)
 	uasm_i_jr(&buf, RA);
 	uasm_i_nop(&buf);
 
-	BUG_ON(buf > copy_page_array + ARRAY_SIZE(copy_page_array));
+	BUG_ON(buf > &__copy_page_end);
 
 	uasm_resolve_relocs(relocs, labels);
 
 	pr_debug("Synthesized copy page handler (%u instructions).\n",
-		 (u32)(buf - copy_page_array));
+		 (u32)(buf - &__copy_page_start));
 
 	pr_debug("\t.set push\n");
 	pr_debug("\t.set noreorder\n");
-	for (i = 0; i < (buf - copy_page_array); i++)
-		pr_debug("\t.word 0x%08x\n", copy_page_array[i]);
+	for (i = 0; i < (buf - &__copy_page_start); i++)
+		pr_debug("\t.word 0x%08x\n", (&__copy_page_start)[i]);
 	pr_debug("\t.set pop\n");
 }
 
 #ifdef CONFIG_SIBYTE_DMA_PAGEOPS
+extern void clear_page_cpu(void *page);
+extern void copy_page_cpu(void *to, void *from);
 
 /*
  * Pad descriptors to cacheline, since each is exclusively owned by a
diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c
index 274af3b..a30eb5d 100644
--- a/arch/mips/mm/sc-rm7k.c
+++ b/arch/mips/mm/sc-rm7k.c
@@ -162,7 +162,7 @@ static void rm7k_tc_disable(void)
 	local_irq_save(flags);
 	blast_rm7k_tcache();
 	clear_c0_config(RM7K_CONF_TE);
-	local_irq_save(flags);
+	local_irq_restore(flags);
 }
 
 static void rm7k_sc_disable(void)
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index d2572cb..1df4d2f 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -120,18 +120,11 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 
 	if (cpu_context(cpu, mm) != 0) {
 		unsigned long size, flags;
-		int huge = is_vm_hugetlb_page(vma);
 
 		ENTER_CRITICAL(flags);
-		if (huge) {
-			start = round_down(start, HPAGE_SIZE);
-			end = round_up(end, HPAGE_SIZE);
-			size = (end - start) >> HPAGE_SHIFT;
-		} else {
-			start = round_down(start, PAGE_SIZE << 1);
-			end = round_up(end, PAGE_SIZE << 1);
-			size = (end - start) >> (PAGE_SHIFT + 1);
-		}
+		start = round_down(start, PAGE_SIZE << 1);
+		end = round_up(end, PAGE_SIZE << 1);
+		size = (end - start) >> (PAGE_SHIFT + 1);
 		if (size <= current_cpu_data.tlbsize/2) {
 			int oldpid = read_c0_entryhi();
 			int newpid = cpu_asid(cpu, mm);
@@ -140,10 +133,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 				int idx;
 
 				write_c0_entryhi(start | newpid);
-				if (huge)
-					start += HPAGE_SIZE;
-				else
-					start += (PAGE_SIZE << 1);
+				start += (PAGE_SIZE << 1);
 				mtc0_tlbw_hazard();
 				tlb_probe();
 				tlb_probe_hazard();
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 6d64efe..54ecdaf 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -147,8 +147,8 @@ enum label_id {
 	label_leave,
 	label_vmalloc,
 	label_vmalloc_done,
-	label_tlbw_hazard,
-	label_split,
+	label_tlbw_hazard_0,
+	label_split = label_tlbw_hazard_0 + 8,
 	label_tlbl_goaround1,
 	label_tlbl_goaround2,
 	label_nopage_tlbl,
@@ -166,7 +166,7 @@ UASM_L_LA(_second_part)
 UASM_L_LA(_leave)
 UASM_L_LA(_vmalloc)
 UASM_L_LA(_vmalloc_done)
-UASM_L_LA(_tlbw_hazard)
+/* _tlbw_hazard_x is handled differently.  */
 UASM_L_LA(_split)
 UASM_L_LA(_tlbl_goaround1)
 UASM_L_LA(_tlbl_goaround2)
@@ -180,6 +180,30 @@ UASM_L_LA(_large_segbits_fault)
 UASM_L_LA(_tlb_huge_update)
 #endif
 
+static int __cpuinitdata hazard_instance;
+
+static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance)
+{
+	switch (instance) {
+	case 0 ... 7:
+		uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance);
+		return;
+	default:
+		BUG();
+	}
+}
+
+static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance)
+{
+	switch (instance) {
+	case 0 ... 7:
+		uasm_build_label(l, *p, label_tlbw_hazard_0 + instance);
+		break;
+	default:
+		BUG();
+	}
+}
+
 /*
  * For debug purposes.
  */
@@ -465,21 +489,35 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
 		 * This branch uses up a mtc0 hazard nop slot and saves
 		 * two nops after the tlbw instruction.
 		 */
-		uasm_il_bgezl(p, r, 0, label_tlbw_hazard);
+		uasm_bgezl_hazard(p, r, hazard_instance);
 		tlbw(p);
-		uasm_l_tlbw_hazard(l, *p);
+		uasm_bgezl_label(l, p, hazard_instance);
+		hazard_instance++;
 		uasm_i_nop(p);
 		break;
 
 	case CPU_R4600:
 	case CPU_R4700:
-	case CPU_R5000:
-	case CPU_R5000A:
 		uasm_i_nop(p);
 		tlbw(p);
 		uasm_i_nop(p);
 		break;
 
+	case CPU_R5000:
+	case CPU_R5000A:
+	case CPU_NEVADA:
+		uasm_i_nop(p); /* QED specifies 2 nops hazard */
+		uasm_i_nop(p); /* QED specifies 2 nops hazard */
+		/*
+		 * This branch uses up a mtc0 hazard nop slot and saves
+		 * a nop after the tlbw instruction.
+		 */
+		uasm_bgezl_hazard(p, r, hazard_instance);
+		tlbw(p);
+		uasm_bgezl_label(l, p, hazard_instance);
+		hazard_instance++;
+		break;
+
 	case CPU_R4300:
 	case CPU_5KC:
 	case CPU_TX49XX:
@@ -512,17 +550,6 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
 		tlbw(p);
 		break;
 
-	case CPU_NEVADA:
-		uasm_i_nop(p); /* QED specifies 2 nops hazard */
-		/*
-		 * This branch uses up a mtc0 hazard nop slot and saves
-		 * a nop after the tlbw instruction.
-		 */
-		uasm_il_bgezl(p, r, 0, label_tlbw_hazard);
-		tlbw(p);
-		uasm_l_tlbw_hazard(l, *p);
-		break;
-
 	case CPU_RM7000:
 		uasm_i_nop(p);
 		uasm_i_nop(p);
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index 7b13a4c..fea823f 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -273,16 +273,19 @@ asmlinkage void plat_irq_dispatch(void)
 	unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
 	int irq;
 
+	if (unlikely(!pending)) {
+		spurious_interrupt();
+		return;
+	}
+
 	irq = irq_ffs(pending);
 
 	if (irq == MIPSCPU_INT_I8259A)
 		malta_hw0_irqdispatch();
 	else if (gic_present && ((1 << irq) & ipi_map[smp_processor_id()]))
 		malta_ipi_irqdispatch();
-	else if (irq >= 0)
-		do_IRQ(MIPS_CPU_IRQ_BASE + irq);
 	else
-		spurious_interrupt();
+		do_IRQ(MIPS_CPU_IRQ_BASE + irq);
 }
 
 #ifdef CONFIG_MIPS_MT_SMP
diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c
index bf80921..284dea5 100644
--- a/arch/mips/mti-malta/malta-pci.c
+++ b/arch/mips/mti-malta/malta-pci.c
@@ -241,8 +241,9 @@ void __init mips_pcibios_init(void)
 		return;
 	}
 
-	if (controller->io_resource->start < 0x00001000UL)	/* FIXME */
-		controller->io_resource->start = 0x00001000UL;
+	/* Change start address to avoid conflicts with ACPI and SMB devices */
+	if (controller->io_resource->start < 0x00002000UL)
+		controller->io_resource->start = 0x00002000UL;
 
 	iomem_resource.end &= 0xfffffffffULL;			/* 64 GB */
 	ioport_resource.end = controller->io_resource->end;
@@ -253,7 +254,7 @@ void __init mips_pcibios_init(void)
 }
 
 /* Enable PCI 2.1 compatibility in PIIX4 */
-static void __init quirk_dlcsetup(struct pci_dev *dev)
+static void __devinit quirk_dlcsetup(struct pci_dev *dev)
 {
 	u8 odlc, ndlc;
 	(void) pci_read_config_byte(dev, 0x82, &odlc);
diff --git a/arch/mips/mti-malta/malta-platform.c b/arch/mips/mti-malta/malta-platform.c
index 4c35301..7473217 100644
--- a/arch/mips/mti-malta/malta-platform.c
+++ b/arch/mips/mti-malta/malta-platform.c
@@ -29,6 +29,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
+#include <asm/mips-boards/maltaint.h>
 #include <mtd/mtd-abi.h>
 
 #define SMC_PORT(base, int)						\
@@ -48,7 +49,7 @@ static struct plat_serial8250_port uart8250_data[] = {
 	SMC_PORT(0x2F8, 3),
 	{
 		.mapbase	= 0x1f000900,	/* The CBUS UART */
-		.irq		= MIPS_CPU_IRQ_BASE + 2,
+		.irq		= MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB2,
 		.uartclk	= 3686400,	/* Twice the usual clk! */
 		.iotype		= UPIO_MEM32,
 		.flags		= CBUS_UART_FLAGS,
@@ -138,11 +139,6 @@ static int __init malta_add_devices(void)
 	if (err)
 		return err;
 
-	/*
-	 * Set RTC to BCD mode to support current alarm code.
-	 */
-	CMOS_WRITE(CMOS_READ(RTC_CONTROL) & ~RTC_DM_BINARY, RTC_CONTROL);
-
 	return 0;
 }
 
diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile
index 29f2f13..9754ece 100644
--- a/arch/mips/oprofile/Makefile
+++ b/arch/mips/oprofile/Makefile
@@ -16,3 +16,5 @@ oprofile-$(CONFIG_CPU_R10000)		+= op_model_mipsxx.o
 oprofile-$(CONFIG_CPU_SB1)		+= op_model_mipsxx.o
 oprofile-$(CONFIG_CPU_RM9000)		+= op_model_rm9000.o
 oprofile-$(CONFIG_CPU_LOONGSON2)	+= op_model_loongson2.o
+oprofile-$(CONFIG_CPU_BMIPS3300)		+= op_model_bmips.o
+oprofile-$(CONFIG_CPU_BMIPS4380)		+= op_model_bmips.o
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index d1f2d4c..e17213c 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -18,6 +18,9 @@
 extern struct op_mips_model op_model_mipsxx_ops __weak;
 extern struct op_mips_model op_model_rm9000_ops __weak;
 extern struct op_mips_model op_model_loongson2_ops __weak;
+#ifdef CONFIG_BRCMSTB
+extern struct op_mips_model op_model_bmips_ops __attribute__((weak));
+#endif
 
 static struct op_mips_model *model;
 
@@ -92,6 +95,17 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
 		lmodel = &op_model_mipsxx_ops;
 		break;
 
+#ifdef CONFIG_BRCMSTB
+	case CPU_BMIPS3300:
+	case CPU_BMIPS4380:
+		lmodel = &op_model_bmips_ops;
+		break;
+
+	case CPU_BMIPS5000:
+		lmodel = &op_model_mipsxx_ops;
+		break;
+#endif
+
 	case CPU_RM9000:
 		lmodel = &op_model_rm9000_ops;
 		break;
diff --git a/arch/mips/oprofile/op_model_bmips.c b/arch/mips/oprofile/op_model_bmips.c
new file mode 100644
index 0000000..e82638a
--- /dev/null
+++ b/arch/mips/oprofile/op_model_bmips.c
@@ -0,0 +1,244 @@
+/*
+ * Copyright (C) 2010 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/oprofile.h>
+#include <linux/interrupt.h>
+#include <linux/smp.h>
+#include <linux/compiler.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#include "op_impl.h"
+
+/*
+ * Events coming from opcontrol look like: 0xXYZZ
+ *   X = ModuleID
+ *   Y = SetID
+ *   ZZ = EventID
+ *
+ * ModuleID and SetID are set globally so they must match for all events.
+ * Exception: events with ModuleID 0 can be used regardless of the
+ * ModuleID / SetID settings.
+ */
+
+#define BMIPS_MOD_SET(event)		(((event) >> 8) & 0xff)
+#define BMIPS_MOD(event)		(((event) >> 12) & 0x0f)
+#define BMIPS_SET(event)		(((event) >> 8) & 0x03)
+#define BMIPS_EVENT(event)		((event) & 0x7f)
+
+/* Default to using TP0 (HW can only profile one thread at a time) */
+#define PMU_TP				0
+
+#define NUM_COUNTERS			4
+
+#define GLOB_ENABLE			0x80000000
+#define GLOB_SET_SHIFT			0
+#define GLOB_MOD_SHIFT			2
+
+#define CTRL_ENABLE			0x8001
+#define CTRL_EVENT_SHIFT		2
+
+#define CNTR_OVERFLOW			0x80000000
+
+#if defined(CONFIG_CPU_BMIPS3300)
+
+/* These registers do not conform to any known MIPS standard */
+#define r_perfcntr0()			__read_32bit_c0_register($25, 0)
+#define r_perfcntr1()			__read_32bit_c0_register($25, 1)
+#define r_perfcntr2()			__read_32bit_c0_register($25, 2)
+#define r_perfcntr3()			__read_32bit_c0_register($25, 3)
+
+#define w_perfcntr0(x)			__write_32bit_c0_register($25, 0, x)
+#define w_perfcntr1(x)			__write_32bit_c0_register($25, 1, x)
+#define w_perfcntr2(x)			__write_32bit_c0_register($25, 2, x)
+#define w_perfcntr3(x)			__write_32bit_c0_register($25, 3, x)
+
+#define w_perfctrl0(x)			__write_32bit_c0_register($25, 4, x)
+#define w_perfctrl1(x)			__write_32bit_c0_register($25, 5, x)
+
+#define r_glob()			__read_32bit_c0_register($25, 6)
+#define w_glob(x)			__write_32bit_c0_register($25, 6, x)
+
+#elif defined(CONFIG_CPU_BMIPS4380)
+
+static unsigned long bmips_cbr;
+
+#define PERF_RD(x)			DEV_RD(bmips_cbr + BMIPS_PERF_ ## x)
+#define PERF_WR(x, y)			DEV_WR_RB(bmips_cbr + \
+						BMIPS_PERF_ ## x, (y))
+
+#define r_perfcntr0()			PERF_RD(COUNTER_0)
+#define r_perfcntr1()			PERF_RD(COUNTER_1)
+#define r_perfcntr2()			PERF_RD(COUNTER_2)
+#define r_perfcntr3()			PERF_RD(COUNTER_3)
+
+#define w_perfcntr0(x)			PERF_WR(COUNTER_0, (x))
+#define w_perfcntr1(x)			PERF_WR(COUNTER_1, (x))
+#define w_perfcntr2(x)			PERF_WR(COUNTER_2, (x))
+#define w_perfcntr3(x)			PERF_WR(COUNTER_3, (x))
+
+#define w_perfctrl0(x)			PERF_WR(CONTROL_0, (x))
+#define w_perfctrl1(x)			PERF_WR(CONTROL_1, (x))
+
+#define r_glob()			PERF_RD(GLOBAL_CONTROL)
+#define w_glob(x)			PERF_WR(GLOBAL_CONTROL, (x))
+
+#endif
+
+static int (*save_perf_irq)(void);
+
+struct op_mips_model op_model_bmips_ops;
+
+static struct bmips_register_config {
+	unsigned int globctrl;
+	unsigned int control[4];
+	unsigned int counter[4];
+} reg;
+
+/* Compute all of the registers in preparation for enabling profiling.  */
+
+static void bmips_reg_setup(struct op_counter_config *ctr)
+{
+	int i;
+	unsigned int mod_set = 0;
+	unsigned int ev;
+
+	memset(&reg, 0, sizeof(reg));
+	reg.globctrl = GLOB_ENABLE;
+
+	for (i = 0; i < NUM_COUNTERS; i++) {
+		if (!ctr[i].enabled)
+			continue;
+		ev = ctr[i].event;
+
+		if (mod_set && BMIPS_MOD_SET(ev) &&
+				mod_set != BMIPS_MOD_SET(ev)) {
+			printk(KERN_WARNING "%s: profiling event 0x%x "
+				"conflicts with another event, disabling\n",
+				__FUNCTION__, ev);
+			continue;
+		}
+		reg.counter[i] = ctr[i].count;
+		reg.control[i] = CTRL_ENABLE |
+			(BMIPS_EVENT(ev) << CTRL_EVENT_SHIFT);
+		if (BMIPS_MOD_SET(ev))
+			mod_set = BMIPS_MOD_SET(ev);
+		reg.globctrl |= (BMIPS_MOD(ev) << GLOB_MOD_SHIFT) |
+			(BMIPS_SET(ev) << GLOB_SET_SHIFT);
+	}
+}
+
+/* Program all of the registers in preparation for enabling profiling.  */
+
+static void bmips_cpu_setup(void *args)
+{
+	w_perfcntr0(reg.counter[0]);
+	w_perfcntr1(reg.counter[1]);
+	w_perfcntr2(reg.counter[2]);
+	w_perfcntr3(reg.counter[3]);
+}
+
+static void bmips_cpu_start(void *args)
+{
+	w_perfctrl0(reg.control[0] | (reg.control[1] << 16));
+	w_perfctrl1(reg.control[2] | (reg.control[3] << 16));
+	w_glob(reg.globctrl);
+}
+
+static void bmips_cpu_stop(void *args)
+{
+	w_perfctrl0(0);
+	w_perfctrl1(0);
+}
+
+static int bmips_perfcount_handler(void)
+{
+	int handled = IRQ_NONE;
+
+	if (!(r_glob() & GLOB_ENABLE))
+		return handled;
+
+#define HANDLE_COUNTER(n) \
+	if (r_perfcntr ## n() & CNTR_OVERFLOW) { \
+		oprofile_add_sample(get_irq_regs(), n); \
+		w_perfcntr ## n(reg.counter[n]); \
+		handled = IRQ_HANDLED; \
+	}
+
+	HANDLE_COUNTER(0)
+	HANDLE_COUNTER(1)
+	HANDLE_COUNTER(2)
+	HANDLE_COUNTER(3)
+
+	if (handled == IRQ_HANDLED)
+		bmips_cpu_start(NULL);
+
+	return handled;
+}
+
+static void bmips_perf_reset(void)
+{
+#ifdef CONFIG_CPU_BMIPS4380
+	bmips_cbr = __BMIPS_GET_CBR();
+	change_c0_brcm_cmt_ctrl(0x3 << 30, PMU_TP << 30);
+#endif
+
+	w_glob(GLOB_ENABLE);
+	w_perfctrl0(0);
+	w_perfctrl1(0);
+	w_perfcntr0(0);
+	w_perfcntr1(0);
+	w_perfcntr2(0);
+	w_perfcntr3(0);
+}
+
+static int __init bmips_init(void)
+{
+	bmips_perf_reset();
+
+	switch (current_cpu_type()) {
+	case CPU_BMIPS3300:
+		op_model_bmips_ops.cpu_type = "mips/bmips3300";
+		break;
+	case CPU_BMIPS4380:
+		op_model_bmips_ops.cpu_type = "mips/bmips4380";
+		break;
+	default:
+		BUG();
+	}
+	save_perf_irq = perf_irq;
+	perf_irq = bmips_perfcount_handler;
+
+	return 0;
+}
+
+static void bmips_exit(void)
+{
+	bmips_perf_reset();
+	w_glob(0);
+	perf_irq = save_perf_irq;
+}
+
+struct op_mips_model op_model_bmips_ops = {
+	.reg_setup	= bmips_reg_setup,
+	.cpu_setup	= bmips_cpu_setup,
+	.init		= bmips_init,
+	.exit		= bmips_exit,
+	.cpu_start	= bmips_cpu_start,
+	.cpu_stop	= bmips_cpu_stop,
+	.num_counters	= 4
+};
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 54759f1..3188d21 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -152,6 +152,14 @@ static void mipsxx_reg_setup(struct op_counter_config *ctr)
 			reg.control[i] |= M_PERFCTL_USER;
 		if (ctr[i].exl)
 			reg.control[i] |= M_PERFCTL_EXL;
+#ifdef CONFIG_CPU_BMIPS5000
+		/* unit mask selects the TP(s) to count */
+		reg.control[i] |= ((ctr->unit_mask & 0x3) << 12) | (1 << 30);
+
+		/* default is TP0 + TP1 */
+		if (!ctr->unit_mask)
+			reg.control[i] |= 0x3 << 12;
+#endif
 		reg.counter[i] = 0x80000000 - ctr[i].count;
 	}
 }
@@ -242,6 +250,13 @@ static int mipsxx_perfcount_handler(void)
 	return handled;
 }
 
+#ifdef CONFIG_BRCMSTB
+static irqreturn_t mipsxx_perfcount_isr(int irq, void *dev_id)
+{
+	return mipsxx_perfcount_handler();
+}
+#endif
+
 #define M_CONFIG1_PC	(1 << 4)
 
 static inline int __n_counters(void)
@@ -365,6 +380,12 @@ static int __init mipsxx_init(void)
 		op_model_mipsxx_ops.cpu_type = "mips/sb1";
 		break;
 
+#ifdef CONFIG_CPU_BMIPS5000
+	case CPU_BMIPS5000:
+		op_model_mipsxx_ops.cpu_type = "mips/bmips5000";
+		break;
+#endif
+
 	default:
 		printk(KERN_ERR "Profiling unsupported for this CPU\n");
 
@@ -374,7 +395,13 @@ static int __init mipsxx_init(void)
 	save_perf_irq = perf_irq;
 	perf_irq = mipsxx_perfcount_handler;
 
-	return 0;
+#ifdef CONFIG_BRCMSTB
+	if (cp0_perfcount_irq >= 0)
+		return request_irq(MIPS_CPU_IRQ_BASE + cp0_perfcount_irq,
+			mipsxx_perfcount_isr, 0, "Perfcounter", NULL);
+	else
+#endif
+		return 0;
 }
 
 static void mipsxx_exit(void)
@@ -384,6 +411,11 @@ static void mipsxx_exit(void)
 	counters = counters_per_cpu_to_total(counters);
 	on_each_cpu(reset_counters, (void *)(long)counters, 1);
 
+#ifdef CONFIG_BRCMSTB
+	if (cp0_perfcount_irq >= 0)
+		free_irq(MIPS_CPU_IRQ_BASE + cp0_perfcount_irq, NULL);
+#endif
+
 	perf_irq = save_perf_irq;
 }
 
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index 9553b14..3e7ce65 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -37,7 +37,7 @@
 #define VIA_COBALT_BRD_ID_REG  0x94
 #define VIA_COBALT_BRD_REG_to_ID(reg)	((unsigned char)(reg) >> 4)
 
-static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
+static void __devinit qube_raq_galileo_early_fixup(struct pci_dev *dev)
 {
 	if (dev->devfn == PCI_DEVFN(0, 0) &&
 		(dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
@@ -51,7 +51,7 @@ static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
 	 qube_raq_galileo_early_fixup);
 
-static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
+static void __devinit qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
 {
 	unsigned short cfgword;
 	unsigned char lt;
@@ -74,7 +74,7 @@ static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
 	 qube_raq_via_bmIDE_fixup);
 
-static void qube_raq_galileo_fixup(struct pci_dev *dev)
+static void __devinit qube_raq_galileo_fixup(struct pci_dev *dev)
 {
 	if (dev->devfn != PCI_DEVFN(0, 0))
 		return;
@@ -129,7 +129,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
 
 int cobalt_board_id;
 
-static void qube_raq_via_board_id_fixup(struct pci_dev *dev)
+static void __devinit qube_raq_via_board_id_fixup(struct pci_dev *dev)
 {
 	u8 id;
 	int retval;
diff --git a/arch/mips/pci/fixup-fuloong2e.c b/arch/mips/pci/fixup-fuloong2e.c
index d5d4c01..0857ab8 100644
--- a/arch/mips/pci/fixup-fuloong2e.c
+++ b/arch/mips/pci/fixup-fuloong2e.c
@@ -48,7 +48,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
 	return 0;
 }
 
-static void __init loongson2e_nec_fixup(struct pci_dev *pdev)
+static void __devinit loongson2e_nec_fixup(struct pci_dev *pdev)
 {
 	unsigned int val;
 
@@ -60,7 +60,7 @@ static void __init loongson2e_nec_fixup(struct pci_dev *pdev)
 	pci_write_config_dword(pdev, 0xe4, 1 << 5);
 }
 
-static void __init loongson2e_686b_func0_fixup(struct pci_dev *pdev)
+static void __devinit loongson2e_686b_func0_fixup(struct pci_dev *pdev)
 {
 	unsigned char c;
 
@@ -135,7 +135,7 @@ static void __init loongson2e_686b_func0_fixup(struct pci_dev *pdev)
 	printk(KERN_INFO"via686b fix: ISA bridge done\n");
 }
 
-static void __init loongson2e_686b_func1_fixup(struct pci_dev *pdev)
+static void __devinit loongson2e_686b_func1_fixup(struct pci_dev *pdev)
 {
 	printk(KERN_INFO"via686b fix: IDE\n");
 
@@ -168,19 +168,19 @@ static void __init loongson2e_686b_func1_fixup(struct pci_dev *pdev)
 	printk(KERN_INFO"via686b fix: IDE done\n");
 }
 
-static void __init loongson2e_686b_func2_fixup(struct pci_dev *pdev)
+static void __devinit loongson2e_686b_func2_fixup(struct pci_dev *pdev)
 {
 	/* irq routing */
 	pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 10);
 }
 
-static void __init loongson2e_686b_func3_fixup(struct pci_dev *pdev)
+static void __devinit loongson2e_686b_func3_fixup(struct pci_dev *pdev)
 {
 	/* irq routing */
 	pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 11);
 }
 
-static void __init loongson2e_686b_func5_fixup(struct pci_dev *pdev)
+static void __devinit loongson2e_686b_func5_fixup(struct pci_dev *pdev)
 {
 	unsigned int val;
 	unsigned char c;
diff --git a/arch/mips/pci/fixup-lemote2f.c b/arch/mips/pci/fixup-lemote2f.c
index 4b9768d..a7b917dcf 100644
--- a/arch/mips/pci/fixup-lemote2f.c
+++ b/arch/mips/pci/fixup-lemote2f.c
@@ -96,21 +96,21 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
 }
 
 /* CS5536 SPEC. fixup */
-static void __init loongson_cs5536_isa_fixup(struct pci_dev *pdev)
+static void __devinit loongson_cs5536_isa_fixup(struct pci_dev *pdev)
 {
 	/* the uart1 and uart2 interrupt in PIC is enabled as default */
 	pci_write_config_dword(pdev, PCI_UART1_INT_REG, 1);
 	pci_write_config_dword(pdev, PCI_UART2_INT_REG, 1);
 }
 
-static void __init loongson_cs5536_ide_fixup(struct pci_dev *pdev)
+static void __devinit loongson_cs5536_ide_fixup(struct pci_dev *pdev)
 {
 	/* setting the mutex pin as IDE function */
 	pci_write_config_dword(pdev, PCI_IDE_CFG_REG,
 			       CS5536_IDE_FLASH_SIGNATURE);
 }
 
-static void __init loongson_cs5536_acc_fixup(struct pci_dev *pdev)
+static void __devinit loongson_cs5536_acc_fixup(struct pci_dev *pdev)
 {
 	/* enable the AUDIO interrupt in PIC  */
 	pci_write_config_dword(pdev, PCI_ACC_INT_REG, 1);
@@ -118,14 +118,14 @@ static void __init loongson_cs5536_acc_fixup(struct pci_dev *pdev)
 	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0);
 }
 
-static void __init loongson_cs5536_ohci_fixup(struct pci_dev *pdev)
+static void __devinit loongson_cs5536_ohci_fixup(struct pci_dev *pdev)
 {
 	/* enable the OHCI interrupt in PIC */
 	/* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */
 	pci_write_config_dword(pdev, PCI_OHCI_INT_REG, 1);
 }
 
-static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev)
+static void __devinit loongson_cs5536_ehci_fixup(struct pci_dev *pdev)
 {
 	u32 hi, lo;
 
@@ -137,7 +137,7 @@ static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev)
 	pci_write_config_dword(pdev, PCI_EHCI_FLADJ_REG, 0x2000);
 }
 
-static void __init loongson_nec_fixup(struct pci_dev *pdev)
+static void __devinit loongson_nec_fixup(struct pci_dev *pdev)
 {
 	unsigned int val;
 
diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c
index 0f48498..59cfbc8 100644
--- a/arch/mips/pci/fixup-malta.c
+++ b/arch/mips/pci/fixup-malta.c
@@ -49,7 +49,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
 	return 0;
 }
 
-static void __init malta_piix_func0_fixup(struct pci_dev *pdev)
+static void __devinit malta_piix_func0_fixup(struct pci_dev *pdev)
 {
 	unsigned char reg_val;
 	static int piixirqmap[16] __initdata = {  /* PIIX PIRQC[A:D] irq mappings */
@@ -83,7 +83,7 @@ static void __init malta_piix_func0_fixup(struct pci_dev *pdev)
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
 	 malta_piix_func0_fixup);
 
-static void __init malta_piix_func1_fixup(struct pci_dev *pdev)
+static void __devinit malta_piix_func1_fixup(struct pci_dev *pdev)
 {
 	unsigned char reg_val;
 
diff --git a/arch/mips/pci/fixup-rc32434.c b/arch/mips/pci/fixup-rc32434.c
index 3d86823..76bb1be 100644
--- a/arch/mips/pci/fixup-rc32434.c
+++ b/arch/mips/pci/fixup-rc32434.c
@@ -47,7 +47,7 @@ int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 	return irq + GROUP4_IRQ_BASE + 4;
 }
 
-static void rc32434_pci_early_fixup(struct pci_dev *dev)
+static void __devinit rc32434_pci_early_fixup(struct pci_dev *dev)
 {
 	if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
 		/* disable prefetched memory range */
diff --git a/arch/mips/pci/fixup-sb1250.c b/arch/mips/pci/fixup-sb1250.c
index f0bb914..d02900a 100644
--- a/arch/mips/pci/fixup-sb1250.c
+++ b/arch/mips/pci/fixup-sb1250.c
@@ -15,7 +15,7 @@
  * Set the BCM1250, etc. PCI host bridge's TRDY timeout
  * to the finite max.
  */
-static void __init quirk_sb1250_pci(struct pci_dev *dev)
+static void __devinit quirk_sb1250_pci(struct pci_dev *dev)
 {
 	pci_write_config_byte(dev, 0x40, 0xff);
 }
@@ -25,7 +25,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_PCI,
 /*
  * The BCM1250, etc. PCI/HT bridge reports as a host bridge.
  */
-static void __init quirk_sb1250_ht(struct pci_dev *dev)
+static void __devinit quirk_sb1250_ht(struct pci_dev *dev)
 {
 	dev->class = PCI_CLASS_BRIDGE_PCI << 8;
 }
@@ -35,7 +35,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_HT,
 /*
  * Set the SP1011 HT/PCI bridge's TRDY timeout to the finite max.
  */
-static void __init quirk_sp1011(struct pci_dev *dev)
+static void __devinit quirk_sp1011(struct pci_dev *dev)
 {
 	pci_write_config_byte(dev, 0x64, 0xff);
 }
diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c
index d37be36..2b91b0e 100644
--- a/arch/mips/pci/msi-octeon.c
+++ b/arch/mips/pci/msi-octeon.c
@@ -150,6 +150,7 @@ msi_irq_allocated:
 		msg.address_lo =
 			((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff;
 		msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32;
+		break;
 	case OCTEON_DMA_BAR_TYPE_BIG:
 		/* When using big bar, Bar 0 is based at 0 */
 		msg.address_lo = (0 + CVMX_PCI_MSI_RCV) & 0xffffffff;
diff --git a/arch/mips/pci/ops-bcm63xx.c b/arch/mips/pci/ops-bcm63xx.c
index 822ae17..097239b 100644
--- a/arch/mips/pci/ops-bcm63xx.c
+++ b/arch/mips/pci/ops-bcm63xx.c
@@ -411,7 +411,7 @@ struct pci_ops bcm63xx_cb_ops = {
  * only one IO window, so it  cannot be shared by PCI and cardbus, use
  * fixup to choose and detect unhandled configuration
  */
-static void bcm63xx_fixup(struct pci_dev *dev)
+static void __devinit bcm63xx_fixup(struct pci_dev *dev)
 {
 	static int io_window = -1;
 	int i, found, new_io_window;
diff --git a/arch/mips/pci/ops-loongson2.c b/arch/mips/pci/ops-loongson2.c
index d657ee0..afd2211 100644
--- a/arch/mips/pci/ops-loongson2.c
+++ b/arch/mips/pci/ops-loongson2.c
@@ -15,6 +15,7 @@
 #include <linux/pci.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/export.h>
 
 #include <loongson.h>
 
diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c
index a1e7e6d..bc13e29 100644
--- a/arch/mips/pci/ops-tx4927.c
+++ b/arch/mips/pci/ops-tx4927.c
@@ -495,7 +495,7 @@ irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id)
 }
 
 #ifdef CONFIG_TOSHIBA_FPCIB0
-static void __init tx4927_quirk_slc90e66_bridge(struct pci_dev *dev)
+static void __devinit tx4927_quirk_slc90e66_bridge(struct pci_dev *dev)
 {
 	struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(dev->bus);
 
diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c
index ec125bed..fe14daf 100644
--- a/arch/mips/pci/pci-alchemy.c
+++ b/arch/mips/pci/pci-alchemy.c
@@ -19,7 +19,7 @@
 #include <asm/mach-au1x00/au1000.h>
 #include <asm/tlbmisc.h>
 
-#ifdef CONFIG_DEBUG_PCI
+#ifdef CONFIG_PCI_DEBUG
 #define DBG(x...) printk(KERN_DEBUG x)
 #else
 #define DBG(x...) do {} while (0)
@@ -162,7 +162,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
 	if (status & (1 << 29)) {
 		*data = 0xffffffff;
 		error = -1;
-		DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d",
+		DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d\n",
 		    access_type, bus->number, device);
 	} else if ((status >> 28) & 0xf) {
 		DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n",
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index 0fbe4c0..fdc2444 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -212,7 +212,7 @@ static inline void pci_enable_swapping(struct pci_dev *dev)
 	bridge->b_widget.w_tflush;	/* Flush */
 }
 
-static void __init pci_fixup_ioc3(struct pci_dev *d)
+static void __devinit pci_fixup_ioc3(struct pci_dev *d)
 {
 	pci_disable_swapping(d);
 }
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 0514866..9d49e60 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -85,7 +85,12 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose)
 	if (!hose->iommu)
 		PCI_DMA_BUS_IS_PHYS = 1;
 
+#ifdef CONFIG_BRCMSTB
+	/* BSP code needs to assign bus numbers */
+	if (hose->get_busno)
+#else
 	if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
+#endif
 		next_busno = (*hose->get_busno)();
 
 	pci_add_resource_offset(&resources,
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq.c b/arch/mips/pmc-sierra/msp71xx/msp_irq.c
index d3c3d81..331e080 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_irq.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq.c
@@ -16,6 +16,7 @@
 #include <linux/time.h>
 
 #include <asm/irq_cpu.h>
+#include <asm/setup.h>
 
 #include <msp_int.h>
 
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_prom.c b/arch/mips/pmc-sierra/msp71xx/msp_prom.c
index db00deb..c65b46b 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_prom.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_prom.c
@@ -83,7 +83,7 @@ static inline unsigned char str2hexnum(unsigned char c)
 	return 0; /* foo */
 }
 
-static inline int str2eaddr(unsigned char *ea, unsigned char *str)
+int str2eaddr(unsigned char *ea, unsigned char *str)
 {
 	int index = 0;
 	unsigned char num = 0;
diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c
index b71fae2..5edab2b 100644
--- a/arch/mips/pmc-sierra/yosemite/smp.c
+++ b/arch/mips/pmc-sierra/yosemite/smp.c
@@ -115,11 +115,11 @@ static void yos_send_ipi_mask(const struct cpumask *mask, unsigned int action)
  */
 static void __cpuinit yos_init_secondary(void)
 {
-	set_c0_status(ST0_CO | ST0_IE | ST0_IM);
 }
 
 static void __cpuinit yos_smp_finish(void)
 {
+	set_c0_status(ST0_CO | ST0_IM | ST0_IE);
 }
 
 /* Hook for after all CPUs are online */
diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c
index 1cf5abb..c697935 100644
--- a/arch/mips/powertv/init.c
+++ b/arch/mips/powertv/init.c
@@ -69,40 +69,6 @@ char *prom_getenv(char *envname)
 	return result;
 }
 
-/* TODO: Verify on linux-mips mailing list that the following two  */
-/* functions are correct                                           */
-/* TODO: Copy NMI and EJTAG exception vectors to memory from the   */
-/* BootROM exception vectors. Flush their cache entries. test it.  */
-
-static void __init mips_nmi_setup(void)
-{
-	void *base;
-#if defined(CONFIG_CPU_MIPS32_R1)
-	base = cpu_has_veic ?
-		(void *)(CAC_BASE + 0xa80) :
-		(void *)(CAC_BASE + 0x380);
-#elif defined(CONFIG_CPU_MIPS32_R2)
-	base = (void *)0xbfc00000;
-#else
-#error NMI exception handler address not defined
-#endif
-}
-
-static void __init mips_ejtag_setup(void)
-{
-	void *base;
-
-#if defined(CONFIG_CPU_MIPS32_R1)
-	base = cpu_has_veic ?
-		(void *)(CAC_BASE + 0xa00) :
-		(void *)(CAC_BASE + 0x300);
-#elif defined(CONFIG_CPU_MIPS32_R2)
-	base = (void *)0xbfc00480;
-#else
-#error EJTAG exception handler address not defined
-#endif
-}
-
 void __init prom_init(void)
 {
 	int prom_argc;
@@ -113,9 +79,6 @@ void __init prom_init(void)
 	_prom_envp = (int *) fw_arg2;
 	_prom_memsize = (unsigned long) fw_arg3;
 
-	board_nmi_handler_setup = mips_nmi_setup;
-	board_ejtag_handler_setup = mips_ejtag_setup;
-
 	if (prom_argc == 1) {
 		strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
 		strlcat(arcs_cmdline, prom_argv, COMMAND_LINE_SIZE);
diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c
index a969eb82..b46953c 100644
--- a/arch/mips/rb532/devices.c
+++ b/arch/mips/rb532/devices.c
@@ -222,6 +222,7 @@ static struct platform_device rb532_wdt = {
 
 static struct plat_serial8250_port rb532_uart_res[] = {
 	{
+		.type           = PORT_16550A,
 		.membase	= (char *)KSEG1ADDR(REGBASE + UART0BASE),
 		.irq		= UART0_IRQ,
 		.regshift	= 2,
@@ -292,7 +293,6 @@ static void __init rb532_nand_setup(void)
 	rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info);
 	rb532_nand_data.chip.partitions = rb532_partition_info;
 	rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
-	rb532_nand_data.chip.options = NAND_NO_AUTOINCR;
 }
 
 
diff --git a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c
index d7c26d0..a757ded 100644
--- a/arch/mips/rb532/prom.c
+++ b/arch/mips/rb532/prom.c
@@ -72,12 +72,11 @@ void __init prom_setup_cmdline(void)
 	static char cmd_line[COMMAND_LINE_SIZE] __initdata;
 	char *cp, *board;
 	int prom_argc;
-	char **prom_argv, **prom_envp;
+	char **prom_argv;
 	int i;
 
 	prom_argc = fw_arg0;
 	prom_argv = (char **) fw_arg1;
-	prom_envp = (char **) fw_arg2;
 
 	cp = cmd_line;
 		/* Note: it is common that parameters start
diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c
index da44ccb..4a6057b 100644
--- a/arch/mips/sgi-ip22/ip22-eisa.c
+++ b/arch/mips/sgi-ip22/ip22-eisa.c
@@ -73,12 +73,10 @@ static char __init *decode_eisa_sig(unsigned long addr)
 
 static irqreturn_t ip22_eisa_intr(int irq, void *dev_id)
 {
-	u8 eisa_irq;
-	u8 dma1, dma2;
+	u8 eisa_irq = inb(EIU_INTRPT_ACK);
 
-	eisa_irq = inb(EIU_INTRPT_ACK);
-	dma1 = inb(EISA_DMA1_STATUS);
-	dma2 = inb(EISA_DMA2_STATUS);
+	inb(EISA_DMA1_STATUS);
+	inb(EISA_DMA2_STATUS);
 
 	if (eisa_irq < EISA_MAX_IRQ) {
 		do_IRQ(eisa_irq);
diff --git a/arch/mips/sgi-ip27/ip27-console.c b/arch/mips/sgi-ip27/ip27-console.c
index 984e561..b952d5b 100644
--- a/arch/mips/sgi-ip27/ip27-console.c
+++ b/arch/mips/sgi-ip27/ip27-console.c
@@ -31,7 +31,7 @@ static inline struct ioc3_uartregs *console_uart(void)
 	return &ioc3->sregs.uarta;
 }
 
-void __init prom_putchar(char c)
+void prom_putchar(char c)
 {
 	struct ioc3_uartregs *uart = console_uart();
 
diff --git a/arch/mips/sibyte/Makefile b/arch/mips/sibyte/Makefile
index c8ed2c8..455c40d 100644
--- a/arch/mips/sibyte/Makefile
+++ b/arch/mips/sibyte/Makefile
@@ -25,3 +25,4 @@ obj-$(CONFIG_SIBYTE_RHONE)	+= swarm/
 obj-$(CONFIG_SIBYTE_SENTOSA)	+= swarm/
 obj-$(CONFIG_SIBYTE_SWARM)	+= swarm/
 obj-$(CONFIG_SIBYTE_BIGSUR)	+= swarm/
+obj-$(CONFIG_SIBYTE_LITTLESUR)	+= swarm/
diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c
index 682efb0..bab4953 100644
--- a/arch/mips/txx9/generic/pci.c
+++ b/arch/mips/txx9/generic/pci.c
@@ -269,7 +269,7 @@ txx9_i8259_irq_setup(int irq)
 	return err;
 }
 
-static void __init quirk_slc90e66_bridge(struct pci_dev *dev)
+static void __devinit quirk_slc90e66_bridge(struct pci_dev *dev)
 {
 	int irq;	/* PCI/ISA Bridge interrupt */
 	u8 reg_64;
@@ -304,7 +304,7 @@ static void __init quirk_slc90e66_bridge(struct pci_dev *dev)
 	smsc_fdc37m81x_config_end();
 }
 
-static void quirk_slc90e66_ide(struct pci_dev *dev)
+static void __devinit quirk_slc90e66_ide(struct pci_dev *dev)
 {
 	unsigned char dat;
 	int regs[2] = {0x41, 0x43};
@@ -339,7 +339,7 @@ static void quirk_slc90e66_ide(struct pci_dev *dev)
 }
 #endif /* CONFIG_TOSHIBA_FPCIB0 */
 
-static void tc35815_fixup(struct pci_dev *dev)
+static void __devinit tc35815_fixup(struct pci_dev *dev)
 {
 	/* This device may have PM registers but not they are not suported. */
 	if (dev->pm_cap) {
@@ -348,7 +348,7 @@ static void tc35815_fixup(struct pci_dev *dev)
 	}
 }
 
-static void final_fixup(struct pci_dev *dev)
+static void __devinit final_fixup(struct pci_dev *dev)
 {
 	unsigned char bist;
 
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index ae77a79..c2c5e8a 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -513,19 +513,19 @@ void __init txx9_sio_init(unsigned long baseaddr, int irq,
 }
 
 #ifdef CONFIG_EARLY_PRINTK
-static void __init null_prom_putchar(char c)
+static void null_prom_putchar(char c)
 {
 }
-void (*txx9_prom_putchar)(char c) __initdata = null_prom_putchar;
+void (*txx9_prom_putchar)(char c) = null_prom_putchar;
 
-void __init prom_putchar(char c)
+void prom_putchar(char c)
 {
 	txx9_prom_putchar(c);
 }
 
 static void __iomem *early_txx9_sio_port;
 
-static void __init early_txx9_sio_putchar(char c)
+static void early_txx9_sio_putchar(char c)
 {
 #define TXX9_SICISR	0x0c
 #define TXX9_SITFIFO	0x1c
diff --git a/arch/mips/wrppmc/pci.c b/arch/mips/wrppmc/pci.c
index d06192f..8b8a0e1 100644
--- a/arch/mips/wrppmc/pci.c
+++ b/arch/mips/wrppmc/pci.c
@@ -38,10 +38,8 @@ static struct pci_controller hose_0 = {
 
 static int __init gt64120_pci_init(void)
 {
-	u32 tmp;
-
-	tmp = GT_READ(GT_PCI0_CMD_OFS);		/* Huh??? -- Ralf  */
-	tmp = GT_READ(GT_PCI0_BARE_OFS);
+	(void) GT_READ(GT_PCI0_CMD_OFS);	/* Huh??? -- Ralf  */
+	(void) GT_READ(GT_PCI0_BARE_OFS);
 
 	/* reset the whole PCI I/O space range */
 	ioport_resource.start = GT_PCI_IO_BASE;
diff --git a/block/elevator.c b/block/elevator.c
index dcef5d1..22ad8b4 100644
--- a/block/elevator.c
+++ b/block/elevator.c
@@ -99,14 +99,14 @@ static void elevator_put(struct elevator_type *e)
 	module_put(e->elevator_owner);
 }
 
-static struct elevator_type *elevator_get(const char *name)
+static struct elevator_type *elevator_get(const char *name, bool try_loading)
 {
 	struct elevator_type *e;
 
 	spin_lock(&elv_list_lock);
 
 	e = elevator_find(name);
-	if (!e) {
+	if (!e && try_loading) {
 		spin_unlock(&elv_list_lock);
 		request_module("%s-iosched", name);
 		spin_lock(&elv_list_lock);
@@ -200,25 +200,30 @@ int elevator_init(struct request_queue *q, char *name)
 	q->boundary_rq = NULL;
 
 	if (name) {
-		e = elevator_get(name);
+		e = elevator_get(name, true);
 		if (!e)
 			return -EINVAL;
 	}
 
+	/*
+	 * Use the default elevator specified by config boot param or
+	 * config option.  Don't try to load modules as we could be running
+	 * off async and request_module() isn't allowed from async.
+	 */
 	if (!e && *chosen_elevator) {
-		e = elevator_get(chosen_elevator);
+		e = elevator_get(chosen_elevator, false);
 		if (!e)
 			printk(KERN_ERR "I/O scheduler %s not found\n",
 							chosen_elevator);
 	}
 
 	if (!e) {
-		e = elevator_get(CONFIG_DEFAULT_IOSCHED);
+		e = elevator_get(CONFIG_DEFAULT_IOSCHED, false);
 		if (!e) {
 			printk(KERN_ERR
 				"Default I/O scheduler not found. " \
 				"Using noop.\n");
-			e = elevator_get("noop");
+			e = elevator_get("noop", false);
 		}
 	}
 
@@ -970,7 +975,7 @@ static int __elevator_change(struct request_queue *q, const char *name)
 		return -ENXIO;
 
 	strlcpy(elevator_name, name, sizeof(elevator_name));
-	e = elevator_get(strstrip(elevator_name));
+	e = elevator_get(strstrip(elevator_name), true);
 	if (!e) {
 		printk(KERN_ERR "elevator: type %s not found\n", elevator_name);
 		return -EINVAL;
diff --git a/drivers/Makefile b/drivers/Makefile
index 95952c8..13c4085 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -5,6 +5,7 @@
 # Rewritten to use lists instead of if-statements.
 #
 
+obj-$(CONFIG_BRCMSTB)		+= brcmstb/
 # GPIO must come after pinctrl as gpios may need to mux pins etc
 obj-y				+= pinctrl/
 obj-y				+= gpio/
diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
index 9e419e1..cb1b21a 100644
--- a/drivers/ata/ahci_platform.c
+++ b/drivers/ata/ahci_platform.c
@@ -15,6 +15,7 @@
 #include <linux/kernel.h>
 #include <linux/gfp.h>
 #include <linux/module.h>
+#include <linux/pm.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/device.h>
@@ -23,6 +24,8 @@
 #include <linux/ahci_platform.h>
 #include "ahci.h"
 
+static void ahci_host_stop(struct ata_host *host);
+
 enum ahci_type {
 	AHCI,		/* standard platform ahci */
 	IMX53_AHCI,	/* ahci on i.mx53 */
@@ -45,6 +48,15 @@ static struct platform_device_id ahci_devtype[] = {
 };
 MODULE_DEVICE_TABLE(platform, ahci_devtype);
 
+static struct ata_port_operations ahci_platform_ops = {
+	.inherits	= &ahci_ops,
+	.host_stop	= ahci_host_stop,
+};
+
+static struct ata_port_operations ahci_platform_retry_srst_ops = {
+	.inherits	= &ahci_pmp_retry_srst_ops,
+	.host_stop	= ahci_host_stop,
+};
 
 static const struct ata_port_info ahci_port_info[] = {
 	/* by features */
@@ -52,20 +64,20 @@ static const struct ata_port_info ahci_port_info[] = {
 		.flags		= AHCI_FLAG_COMMON,
 		.pio_mask	= ATA_PIO4,
 		.udma_mask	= ATA_UDMA6,
-		.port_ops	= &ahci_ops,
+		.port_ops	= &ahci_platform_ops,
 	},
 	[IMX53_AHCI] = {
 		.flags		= AHCI_FLAG_COMMON,
 		.pio_mask	= ATA_PIO4,
 		.udma_mask	= ATA_UDMA6,
-		.port_ops	= &ahci_pmp_retry_srst_ops,
+		.port_ops	= &ahci_platform_retry_srst_ops,
 	},
 	[STRICT_AHCI] = {
 		AHCI_HFLAGS	(AHCI_HFLAG_DELAY_ENGINE),
 		.flags		= AHCI_FLAG_COMMON,
 		.pio_mask	= ATA_PIO4,
 		.udma_mask	= ATA_UDMA6,
-		.port_ops	= &ahci_ops,
+		.port_ops	= &ahci_platform_ops,
 	},
 };
 
@@ -73,7 +85,7 @@ static struct scsi_host_template ahci_platform_sht = {
 	AHCI_SHT("ahci_platform"),
 };
 
-static int __init ahci_probe(struct platform_device *pdev)
+static int __devinit ahci_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct ahci_platform_data *pdata = dev_get_platdata(dev);
@@ -199,18 +211,13 @@ err0:
 	return rc;
 }
 
-static int __devexit ahci_remove(struct platform_device *pdev)
+static void ahci_host_stop(struct ata_host *host)
 {
-	struct device *dev = &pdev->dev;
+	struct device *dev = host->dev;
 	struct ahci_platform_data *pdata = dev_get_platdata(dev);
-	struct ata_host *host = dev_get_drvdata(dev);
-
-	ata_host_detach(host);
 
 	if (pdata && pdata->exit)
 		pdata->exit(dev);
-
-	return 0;
 }
 
 #ifdef CONFIG_PM
@@ -271,13 +278,10 @@ static int ahci_resume(struct device *dev)
 
 	return 0;
 }
-
-static struct dev_pm_ops ahci_pm_ops = {
-	.suspend		= &ahci_suspend,
-	.resume			= &ahci_resume,
-};
 #endif
 
+static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_suspend, ahci_resume);
+
 static const struct of_device_id ahci_of_match[] = {
 	{ .compatible = "calxeda,hb-ahci", },
 	{ .compatible = "snps,spear-ahci", },
@@ -286,29 +290,17 @@ static const struct of_device_id ahci_of_match[] = {
 MODULE_DEVICE_TABLE(of, ahci_of_match);
 
 static struct platform_driver ahci_driver = {
-	.remove = __devexit_p(ahci_remove),
+	.probe = ahci_probe,
+	.remove = ata_platform_remove_one,
 	.driver = {
 		.name = "ahci",
 		.owner = THIS_MODULE,
 		.of_match_table = ahci_of_match,
-#ifdef CONFIG_PM
 		.pm = &ahci_pm_ops,
-#endif
 	},
 	.id_table	= ahci_devtype,
 };
-
-static int __init ahci_init(void)
-{
-	return platform_driver_probe(&ahci_driver, ahci_probe);
-}
-module_init(ahci_init);
-
-static void __exit ahci_exit(void)
-{
-	platform_driver_unregister(&ahci_driver);
-}
-module_exit(ahci_exit);
+module_platform_driver(ahci_driver);
 
 MODULE_DESCRIPTION("AHCI SATA platform driver");
 MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>");
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 68bdd59..13c2ac3 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -67,6 +67,7 @@
 #include <linux/cdrom.h>
 #include <linux/ratelimit.h>
 #include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
 
 #include "libata.h"
 #include "libata-transport.h"
@@ -6365,6 +6366,26 @@ int ata_pci_device_resume(struct pci_dev *pdev)
 
 #endif /* CONFIG_PCI */
 
+/**
+ *      ata_platform_remove_one- Platform layer callback for device removal
+ *      @pdev: Platform device that was removed
+ *
+ *      Platform layer indicates to libata via this hook that hot-unplug or
+ *      module unload event has occurred.  Detach all ports.  Resource
+ *      release is handled via devres.
+ *
+ *      LOCKING:
+ *      Inherited from platform layer (may sleep).
+ */
+int ata_platform_remove_one(struct platform_device *pdev)
+{
+	struct ata_host *host = platform_get_drvdata(pdev);
+
+	ata_host_detach(host);
+
+	return 0;
+}
+
 static int __init ata_parse_force_one(char **cur,
 				      struct ata_force_ent *force_ent,
 				      const char **reason)
@@ -6886,6 +6907,8 @@ EXPORT_SYMBOL_GPL(ata_pci_device_resume);
 #endif /* CONFIG_PM */
 #endif /* CONFIG_PCI */
 
+EXPORT_SYMBOL_GPL(ata_platform_remove_one);
+
 EXPORT_SYMBOL_GPL(__ata_ehi_push_desc);
 EXPORT_SYMBOL_GPL(ata_ehi_push_desc);
 EXPORT_SYMBOL_GPL(ata_ehi_clear_desc);
diff --git a/drivers/base/core.c b/drivers/base/core.c
index aeaf0e1..0fa0ecb 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -460,9 +460,12 @@ static int device_add_attrs(struct device *dev)
 	int error;
 
 	if (class) {
-		error = device_add_attributes(dev, class->dev_attrs);
+		error = device_add_groups(dev, class->dev_groups);
 		if (error)
 			return error;
+		error = device_add_attributes(dev, class->dev_attrs);
+		if (error)
+			goto err_remove_class_groups;
 		error = device_add_bin_attributes(dev, class->dev_bin_attrs);
 		if (error)
 			goto err_remove_class_attrs;
@@ -489,6 +492,9 @@ static int device_add_attrs(struct device *dev)
  err_remove_class_attrs:
 	if (class)
 		device_remove_attributes(dev, class->dev_attrs);
+ err_remove_class_groups:
+	if (class)
+		device_remove_groups(dev, class->dev_groups);
 
 	return error;
 }
@@ -506,6 +512,7 @@ static void device_remove_attrs(struct device *dev)
 	if (class) {
 		device_remove_attributes(dev, class->dev_attrs);
 		device_remove_bin_attributes(dev, class->dev_bin_attrs);
+		device_remove_groups(dev, class->dev_groups);
 	}
 }
 
diff --git a/drivers/base/devres.c b/drivers/base/devres.c
index 06c541d..ea94c66 100644
--- a/drivers/base/devres.c
+++ b/drivers/base/devres.c
@@ -326,6 +326,37 @@ int devres_destroy(struct device *dev, dr_release_t release,
 }
 EXPORT_SYMBOL_GPL(devres_destroy);
 
+
+/**
+ * devres_release - Find a device resource and destroy it, calling release
+ * @dev: Device to find resource from
+ * @release: Look for resources associated with this release function
+ * @match: Match function (optional)
+ * @match_data: Data for the match function
+ *
+ * Find the latest devres of @dev associated with @release and for
+ * which @match returns 1.  If @match is NULL, it's considered to
+ * match all.  If found, the resource is removed atomically, the
+ * release function called and the resource freed.
+ *
+ * RETURNS:
+ * 0 if devres is found and freed, -ENOENT if not found.
+ */
+int devres_release(struct device *dev, dr_release_t release,
+		   dr_match_t match, void *match_data)
+{
+	void *res;
+
+	res = devres_remove(dev, release, match, match_data);
+	if (unlikely(!res))
+		return -ENOENT;
+
+	(*release)(dev, res);
+	devres_free(res);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(devres_release);
+
 static int remove_nodes(struct device *dev,
 			struct list_head *first, struct list_head *end,
 			struct list_head *todo)
diff --git a/drivers/base/dma-buf.c b/drivers/base/dma-buf.c
index 07cbbc6..7cfb405 100644
--- a/drivers/base/dma-buf.c
+++ b/drivers/base/dma-buf.c
@@ -44,8 +44,26 @@ static int dma_buf_release(struct inode *inode, struct file *file)
 	return 0;
 }
 
+static int dma_buf_mmap_internal(struct file *file, struct vm_area_struct *vma)
+{
+	struct dma_buf *dmabuf;
+
+	if (!is_dma_buf_file(file))
+		return -EINVAL;
+
+	dmabuf = file->private_data;
+
+	/* check for overflowing the buffer's size */
+	if (vma->vm_pgoff + ((vma->vm_end - vma->vm_start) >> PAGE_SHIFT) >
+	    dmabuf->size >> PAGE_SHIFT)
+		return -EINVAL;
+
+	return dmabuf->ops->mmap(dmabuf, vma);
+}
+
 static const struct file_operations dma_buf_fops = {
 	.release	= dma_buf_release,
+	.mmap		= dma_buf_mmap_internal,
 };
 
 /*
@@ -82,7 +100,8 @@ struct dma_buf *dma_buf_export(void *priv, const struct dma_buf_ops *ops,
 			  || !ops->unmap_dma_buf
 			  || !ops->release
 			  || !ops->kmap_atomic
-			  || !ops->kmap)) {
+			  || !ops->kmap
+			  || !ops->mmap)) {
 		return ERR_PTR(-EINVAL);
 	}
 
@@ -406,3 +425,46 @@ void dma_buf_kunmap(struct dma_buf *dmabuf, unsigned long page_num,
 		dmabuf->ops->kunmap(dmabuf, page_num, vaddr);
 }
 EXPORT_SYMBOL_GPL(dma_buf_kunmap);
+
+
+/**
+ * dma_buf_mmap - Setup up a userspace mmap with the given vma
+ * @dma_buf:	[in]	buffer that should back the vma
+ * @vma:	[in]	vma for the mmap
+ * @pgoff:	[in]	offset in pages where this mmap should start within the
+ * 			dma-buf buffer.
+ *
+ * This function adjusts the passed in vma so that it points at the file of the
+ * dma_buf operation. It alsog adjusts the starting pgoff and does bounds
+ * checking on the size of the vma. Then it calls the exporters mmap function to
+ * set up the mapping.
+ *
+ * Can return negative error values, returns 0 on success.
+ */
+int dma_buf_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma,
+		 unsigned long pgoff)
+{
+	if (WARN_ON(!dmabuf || !vma))
+		return -EINVAL;
+
+	/* check for offset overflow */
+	if (pgoff + ((vma->vm_end - vma->vm_start) >> PAGE_SHIFT) < pgoff)
+		return -EOVERFLOW;
+
+	/* check for overflowing the buffer's size */
+	if (pgoff + ((vma->vm_end - vma->vm_start) >> PAGE_SHIFT) >
+	    dmabuf->size >> PAGE_SHIFT)
+		return -EINVAL;
+
+	/* readjust the vma */
+	if (vma->vm_file)
+		fput(vma->vm_file);
+
+	vma->vm_file = dmabuf->file;
+	get_file(vma->vm_file);
+
+	vma->vm_pgoff = pgoff;
+
+	return dmabuf->ops->mmap(dmabuf, vma);
+}
+EXPORT_SYMBOL_GPL(dma_buf_mmap);
diff --git a/drivers/base/dma-coherent.c b/drivers/base/dma-coherent.c
index bb0025c..1b85949 100644
--- a/drivers/base/dma-coherent.c
+++ b/drivers/base/dma-coherent.c
@@ -10,6 +10,7 @@
 struct dma_coherent_mem {
 	void		*virt_base;
 	dma_addr_t	device_base;
+	phys_addr_t	pfn_base;
 	int		size;
 	int		flags;
 	unsigned long	*bitmap;
@@ -44,6 +45,7 @@ int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
 
 	dev->dma_mem->virt_base = mem_base;
 	dev->dma_mem->device_base = device_addr;
+	dev->dma_mem->pfn_base = PFN_DOWN(bus_addr);
 	dev->dma_mem->size = pages;
 	dev->dma_mem->flags = flags;
 
@@ -176,3 +178,43 @@ int dma_release_from_coherent(struct device *dev, int order, void *vaddr)
 	return 0;
 }
 EXPORT_SYMBOL(dma_release_from_coherent);
+
+/**
+ * dma_mmap_from_coherent() - try to mmap the memory allocated from
+ * per-device coherent memory pool to userspace
+ * @dev:	device from which the memory was allocated
+ * @vma:	vm_area for the userspace memory
+ * @vaddr:	cpu address returned by dma_alloc_from_coherent
+ * @size:	size of the memory buffer allocated by dma_alloc_from_coherent
+ *
+ * This checks whether the memory was allocated from the per-device
+ * coherent memory pool and if so, maps that memory to the provided vma.
+ *
+ * Returns 1 if we correctly mapped the memory, or 0 if
+ * dma_release_coherent() should proceed with mapping memory from
+ * generic pools.
+ */
+int dma_mmap_from_coherent(struct device *dev, struct vm_area_struct *vma,
+			   void *vaddr, size_t size, int *ret)
+{
+	struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
+
+	if (mem && vaddr >= mem->virt_base && vaddr + size <=
+		   (mem->virt_base + (mem->size << PAGE_SHIFT))) {
+		unsigned long off = vma->vm_pgoff;
+		int start = (vaddr - mem->virt_base) >> PAGE_SHIFT;
+		int user_count = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
+		int count = size >> PAGE_SHIFT;
+
+		*ret = -ENXIO;
+		if (off < count && user_count <= count - off) {
+			unsigned pfn = mem->pfn_base + start + off;
+			*ret = remap_pfn_range(vma, vma->vm_start, pfn,
+					       user_count << PAGE_SHIFT,
+					       vma->vm_page_prot);
+		}
+		return 1;
+	}
+	return 0;
+}
+EXPORT_SYMBOL(dma_mmap_from_coherent);
diff --git a/drivers/base/dma-mapping.c b/drivers/base/dma-mapping.c
index 6f3676f..db5db02 100644
--- a/drivers/base/dma-mapping.c
+++ b/drivers/base/dma-mapping.c
@@ -10,6 +10,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/export.h>
 #include <linux/gfp.h>
+#include <asm-generic/dma-coherent.h>
 
 /*
  * Managed DMA API
@@ -218,3 +219,33 @@ void dmam_release_declared_memory(struct device *dev)
 EXPORT_SYMBOL(dmam_release_declared_memory);
 
 #endif
+
+/*
+ * Create userspace mapping for the DMA-coherent memory.
+ */
+int dma_common_mmap(struct device *dev, struct vm_area_struct *vma,
+		    void *cpu_addr, dma_addr_t dma_addr, size_t size)
+{
+	int ret = -ENXIO;
+#ifdef CONFIG_MMU
+	unsigned long user_count = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
+	unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
+	unsigned long pfn = page_to_pfn(virt_to_page(cpu_addr));
+	unsigned long off = vma->vm_pgoff;
+
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+	if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
+		return ret;
+
+	if (off < count && user_count <= (count - off)) {
+		ret = remap_pfn_range(vma, vma->vm_start,
+				      pfn + off,
+				      user_count << PAGE_SHIFT,
+				      vma->vm_page_prot);
+	}
+#endif	/* CONFIG_MMU */
+
+	return ret;
+}
+EXPORT_SYMBOL(dma_common_mmap);
diff --git a/drivers/brcmstb/Kconfig b/drivers/brcmstb/Kconfig
new file mode 100644
index 0000000..46aa9d1
--- /dev/null
+++ b/drivers/brcmstb/Kconfig
@@ -0,0 +1,1267 @@
+menu "Broadcom STB options"
+	depends on BRCMSTB
+
+
+#####################################################################
+# User options: Chipset selection
+#####################################################################
+
+
+config BRCM_LEGACY
+	bool "Enable legacy platforms"
+	depends on BRCMSTB
+	default n
+	help
+	  Reserved for future use.  Say N.
+
+
+choice
+	prompt "Chipset selection"
+	depends on BRCMSTB
+	help
+	  Select the Broadcom chipset you are building for.
+
+config BCM7228A0
+	bool "7228 Ax"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7228
+	select BRCM_HAS_BMIPS4380
+	select BRCM_HAS_XKS01
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_GENET_0
+	select BRCM_GENET_V2
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_SATA3
+	select BRCM_HAS_WKTMR
+	select BRCM_HAS_UPPER_MEMORY
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7231B0
+	bool "7231 Bx"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7231
+	select BRCM_HAS_BMIPS4380
+	select BRCM_HAS_XKS01
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_USB_CAPS
+	select BRCM_HAS_GENET_0
+	select BRCM_HAS_GENET_1
+	select BRCM_GENET_V2
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_SATA3
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_WKTMR
+	select BRCM_HAS_UPPER_MEMORY
+	select BRCM_HAS_1GB_MEMC0
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7344B0
+	bool "7344 Bx"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7344
+	select BRCM_HAS_BMIPS5000
+	select BRCM_HAS_XKS01
+	select BRCM_HAS_XI
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_USB_CAPS
+	select BRCM_HAS_GENET_0
+	select BRCM_HAS_MOCA_11_PLUS
+	select BRCM_HAS_MOCA_MIDRF
+	select BRCM_MOCA_ON_GENET_1
+	select BRCM_GENET_V2
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_WKTMR
+	select BRCM_HAS_UPPER_MEMORY
+	select BRCM_HAS_1GB_MEMC0
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7346B0
+	bool "7346 Bx"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7346
+	select BRCM_HAS_BMIPS5000
+	select BRCM_HAS_XKS01
+	select BRCM_HAS_XI
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_USB_CAPS
+	select BRCM_HAS_GENET_0
+	select BRCM_HAS_MOCA_11_PLUS
+	select BRCM_HAS_MOCA_MIDRF
+	select BRCM_MOCA_ON_GENET_1
+	select BRCM_GENET_V2
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_SATA3
+	select BRCM_HAS_WKTMR
+	select BRCM_HAS_UPPER_MEMORY
+	select BRCM_HAS_1GB_MEMC0
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7358A0
+	bool "7358 Ax"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7358
+	select BRCM_HAS_BMIPS3300
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_GENET_0
+	select BRCM_GENET_V2
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_WKTMR
+	select BRCM_PWR_HANDSHAKE_V0
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7360A0
+	bool "7360 Ax"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7360
+	select BRCM_HAS_BMIPS3300
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_GENET_0
+	select BRCM_GENET_V2
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_SATA3
+	select BRCM_HAS_WKTMR
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7362A0
+	bool "7362 Ax"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7362
+	select BRCM_HAS_BMIPS4380
+	select BRCM_HAS_XKS01
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550 if !DREAMBOX
+	select BRCM_UARTC_IS_16550 if !DREAMBOX
+	select BRCM_HAS_GENET_0
+	select BRCM_GENET_V2
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_SATA3 if !DREAMBOX_DM520
+	select BRCM_HAS_WKTMR
+	select BRCM_HAS_UPPER_MEMORY
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7425B0
+	bool "7425 Bx"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7425
+	select BRCM_HAS_BMIPS5000
+	select BRCM_HAS_XKS01
+	select BRCM_HAS_XI
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_PCIE
+	select BRCM_HAS_GENET_0
+	select BRCM_HAS_MOCA_20_GEN21
+	select BRCM_MOCA_ON_GENET_1
+	select BRCM_GENET_V3
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_EDU
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_EMMC
+	select BRCM_HAS_SATA3
+	select BRCM_HAS_WKTMR
+	select BRCM_HAS_UPPER_MEMORY
+	select BRCM_HAS_2GB_MEMC0
+	select BRCM_HAS_1GB_MEMC1
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7429B0
+	bool "7429 Bx"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7429
+	select BRCM_HAS_BMIPS5000
+	select BRCM_HAS_XKS01
+	select BRCM_HAS_XI
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_USB_CAPS
+	select BRCM_HAS_GENET_0
+	select BRCM_HAS_MOCA_20_GEN22
+	select BRCM_MOCA_ON_GENET_1
+	select BRCM_GENET_V3
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_6
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_EDU
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_EMMC
+	select BRCM_HAS_SATA3
+	select BRCM_HAS_WKTMR
+	select BRCM_HAS_UPPER_MEMORY
+	select BRCM_HAS_2GB_MEMC0
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7435B0
+	bool "7435 Bx"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7435
+	select BRCM_HAS_BMIPS5000
+	select BRCM_HAS_XKS01
+	select BRCM_HAS_XI
+	select BRCM_HAS_DUALCORE
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550 if !DREAMBOX
+	select BRCM_UARTC_IS_16550 if !DREAMBOX
+	select BRCM_HAS_USB_CAPS
+	select BRCM_HAS_PCIE
+	select BRCM_HAS_GENET_0
+	select BRCM_HAS_MOCA_20_GEN22
+	select BRCM_MOCA_ON_GENET_1 if !DREAMBOX
+	select BRCM_GENET_V3
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_6
+	select BRCM_HAS_NAND_MINOR_2
+	#select BRCM_HAS_EDU
+	select BRCM_HAS_FLASH_DMA
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_EMMC
+	select BRCM_HAS_SATA3
+	select BRCM_HAS_WKTMR
+	select BRCM_HAS_UPPER_MEMORY
+	select BRCM_HAS_2GB_MEMC0
+	select BRCM_HAS_1GB_MEMC1
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7543A0
+	bool "7543 Ax"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7543
+	select BRCM_HAS_BMIPS3300
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_WKTMR
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7552B0
+	bool "7552 Bx"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7552
+	select BRCM_HAS_BMIPS3300
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_GENET_0
+	select BRCM_GENET_V2
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_WKTMR
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7563A0
+	bool "7563 Ax"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7563
+	select BRCM_HAS_BMIPS4380
+	select BRCM_HAS_XKS01
+	select BRCM_HAS_XI
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_USB_CAPS
+	select BRCM_HAS_GENET_0
+	select BRCM_GENET_V2
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_MSPI_64B_WORDS
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_EMMC
+	select BRCM_HAS_WKTMR
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+	select BRCM_HAS_UPPER_MEMORY
+
+config BCM7584A0
+	bool "7584 Ax"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7584
+	select BRCM_HAS_BMIPS4380
+	select BRCM_HAS_XKS01
+	select BRCM_HAS_XI
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_USB_CAPS
+	select BRCM_HAS_GENET_0
+	select BRCM_HAS_GENET_1
+	select BRCM_GENET_V2
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_MSPI_64B_WORDS
+	select BRCM_HAS_SATA3
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_EMMC
+	select BRCM_HAS_WKTMR
+	select BRCM_HAS_UPPER_MEMORY
+	select BRCM_HAS_1GB_MEMC0
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+endchoice
+
+config DREAMBOX
+	bool "Dreambox"
+	select FB_CFB_COPYAREA
+	select FB_CFB_FILLRECT
+	select FB_CFB_IMAGEBLIT
+	select SND_PCM
+
+choice
+	prompt "Dreambox model selection"
+	depends on DREAMBOX
+
+config DREAMBOX_DM520
+	bool "Dreambox DM520"
+	depends on BCM7362A0
+
+config DREAMBOX_DM820
+	bool "Dreambox DM820"
+	depends on BCM7435B0
+
+config DREAMBOX_DM7080
+	bool "Dreambox DM7080"
+	depends on BCM7435B0
+
+endchoice
+
+#####################################################################
+# User options: Memory configuration
+#####################################################################
+
+
+comment "Memory map"
+
+
+config BRCM_UPPER_MEMORY
+	bool "Large (>256MB) memory support"
+	depends on BRCM_HAS_UPPER_MEMORY
+	select ARCH_SPARSEMEM_ENABLE
+	select BRCM_UPPER_768MB if BRCM_HAS_XKS01
+	default y
+	help
+	  Say Y to use a special mapping scheme to access the STB's
+	  upper memory (all RAM above 256MB).  This supports up to 512MB
+	  of ZONE_NORMAL memory on 65nm chips, and 1024MB of ZONE_NORMAL
+	  memory on 40nm chips.
+
+	  On chips where HIGHMEM is available, this option should remain
+	  enabled since it will maximize the amount of memory in ZONE_NORMAL.
+
+	  If this option is disabled, you will only be able to use the
+	  first 256MB of RAM on the system (without HIGHMEM).  HIGHMEM is
+	  not available on most STB chips.
+
+	  It is recommended that this option be used in conjuction with
+	  SPARSEMEM (Kernel type -> Memory model -> Sparse memory).
+	  SPARSEMEM conserves about 2MB by omitting the page tables for the
+	  memory hole.
+
+
+config BRCM_OVERRIDE_RAM_SIZE
+	bool "Override memory size detection"
+	depends on BRCMSTB && MIPS
+	default n
+	help
+	  Say Y to use a compile-time default rather than detecting the
+	  RAM size from strap options or reading it from the bootloader.
+
+	  If unsure, say N.
+
+
+config BRCM_FORCED_DRAM0_SIZE
+	int "RAM on primary DRAM controller (MB)"
+	depends on BRCM_OVERRIDE_RAM_SIZE
+	default 32
+	help
+	  How many megabytes of RAM are on the primary DRAM controller?
+
+config BRCM_FORCED_DRAM1_SIZE
+	int "RAM on secondary DRAM controller (MB)"
+	depends on BRCM_OVERRIDE_RAM_SIZE && BRCM_HAS_1GB_MEMC1
+	default 256
+	help
+	  How many megabytes of RAM are on the secondary DRAM controller?
+
+
+#####################################################################
+# User options: Onchip peripherals
+#####################################################################
+
+
+comment "Onchip peripherals"
+	depends on BRCMSTB
+
+
+config BRCM_CONSOLE_DEVICE
+	int "Default serial console device"
+	depends on BRCMSTB
+	default 0
+	range 0 2
+	help
+	  Default UART to use for console output.  This can be overridden with
+	  "console=" on the kernel command line.
+
+	   0 = /dev/ttyS0 or /dev/ttyBCM0 (UARTA)
+	   1 = /dev/ttyS1 or /dev/ttyBCM1 (UARTB)
+	   2 = /dev/ttyS2 or /dev/ttyBCM2 (UARTC)
+
+	  If unsure, choose 0.
+
+
+config BRCM_FLASH
+	bool "Enable onboard flash devices"
+	depends on (BRCM_HAS_NOR || BRCM_HAS_NAND || BRCM_HAS_SPI) && MTD && \
+		!BRCM_IKOS
+	default y
+	help
+	  Say Y to enable NOR/ROM, NAND, and SPI flash devices.  The EBI
+	  and NAND chip select registers will be scanned at boot time to
+	  determine which devices are configured.
+
+	  NOR/ROM will be handled by the standard physmap driver
+	  (CONFIG_MTD_PHYSMAP) in the MTD menus.  NAND is handled by
+	  CONFIG_MTD_BRCMNAND in this menu.
+
+config BRCM_FIXED_MTD_PARTITIONS
+	bool "Use fixed MTD partition map"
+	depends on BRCM_FLASH
+	default n
+	help
+	  Say Y to use the hard-coded flash partition map from
+	  arch/mips/brcmstb/board.c .
+
+	  The default setting (N) constructs the rootfs/kernel partition
+	  boundaries from CFE environment variables.
+
+	  To use this option, please edit board_get_partition_map() and
+	  review brcmstb_mtd_setup().
+
+	  If unsure, say N.
+
+
+config MTD_BRCMNAND
+	tristate "Broadcom NAND controller support"
+	depends on BRCM_HAS_NAND && BRCM_FLASH
+	default y
+	help
+	  Say Y to enable the onchip NAND controller.
+
+
+config SPI_BRCMSTB
+	tristate "Broadcom HIF SPI controller support"
+	default y
+	depends on BRCM_HAS_SPI && BRCM_FLASH && SPI_MASTER
+	help
+	  Say Y to enable support for SPI (serial) flash devices.
+
+
+config BCMGENET
+	tristate "Broadcom STB 10/100/1000 MAC/PHY support"
+	depends on ETHERNET
+	depends on BRCMSTB && (BRCM_HAS_GENET || BRCM_HAS_MOCA) && !BRCM_IKOS
+	default y
+	select CRC32
+	select MII
+	help
+	  Say Y to support the internal 10/100/1000 GENET MAC/PHY on
+	  Broadcom set-top chips.  This driver also supports the datapath
+	  for the onchip MoCA transceiver.
+
+	  If your chipset supports power management, disabling this driver
+	  will keep the device permanently powered down.
+
+if BCMGENET
+	source drivers/net/ethernet/broadcom/genet/Kconfig
+endif
+
+config BCMGENET_NG
+	tristate "Broadcom STB 10/100/1000 MAC/PHY support"
+	depends on ETHERNET && BRCMSTB && OF
+	default y
+	select CRC32
+	select MII
+	help
+	  Say Y to support the internal 10/100/1000 GENET MAC/PHY on
+	  Broadcom set-top chips.  This driver also supports the datapath
+	  for the onchip MoCA transceiver.
+
+	  If your chipset supports power management, disabling this driver
+	  will keep the device permanently powered down.
+
+if BCMGENET_NG
+	source drivers/net/ethernet/broadcom/genet-ng/Kconfig
+endif
+
+config BRCM_MOCA
+	tristate "Broadcom MoCA character driver"
+	depends on BRCMSTB && BRCM_HAS_MOCA && !BRCM_IKOS
+	default y
+	help
+	  Say Y to build the MoCA control path driver.  This is a simple
+	  character driver that allows the MoCA daemon (mocad) to
+	  initialize and configure the MoCA interface.
+
+	  If your chipset supports power management, disabling this driver
+	  will keep the device permanently powered down.
+
+
+config SATA_BRCMSTB
+	tristate "Broadcom STB SATA support"
+	depends on BRCMSTB && PCI && ATA_SFF && !BRCM_IKOS && \
+		BRCM_HAS_SATA2
+	default y
+	help
+	  This option enables support for STB/DVD onchip SATA cores.
+
+	  If your chipset supports power management, disabling this driver
+	  will keep the device permanently powered down.
+
+	  If unsure, say Y.
+
+
+config BRCM_USB
+	tristate "Broadcom STB USB support"
+	depends on BRCMSTB && USB && !BRCM_IKOS
+	default y
+	help
+	  Say Y to enable the drivers for the onchip USB controllers.
+
+	  If your chipset supports power management, disabling this driver
+	  will keep the device permanently powered down.
+
+config BRCM_OVERRIDE_USB
+	bool "Override USB defaults"
+	depends on BRCM_USB
+	default n
+	help
+	  Say Y to see advanced USB configuration options.
+
+	  Normally the USB driver in the bootloader will enable the
+	  appropriate settings prior to Linux boot, but this step may be
+	  skipped if a customized bootloader is in use.
+
+	  If unsure, say N.
+
+choice
+	prompt "USB VBUS power enable polarity"
+	depends on BRCM_OVERRIDE_USB
+	default BRCM_FORCE_USB_PWR_LO
+
+config BRCM_FORCE_USB_PWR_LO
+	bool "Active low"
+	help
+	  The board's USB VBUS control IC will have either an active low
+	  or an active high enable.  On most Broadcom reference boards,
+	  active low is used; however, on customer designs this may vary.
+	  The output of the hardware signal USBx_PWRON is affected by
+	  this setting, and it applies to all ports and controllers.
+
+config BRCM_FORCE_USB_PWR_HI
+	bool "Active high"
+
+endchoice
+
+choice
+	prompt "USB overcurrent polarity"
+	depends on BRCM_OVERRIDE_USB
+	default BRCM_FORCE_USB_OC_LO
+
+config BRCM_FORCE_USB_OC_LO
+	bool "Active low"
+	help
+	  Controls the handling of the overcurrent indicator line (input
+	  to BCM7xxx).  Active low is typically used when USBx_PWRFLT is
+	  connected to a power switch chip, as is the case on Broadcom
+	  reference boards.  Active high may be used if USBx_PWRFLT is
+	  connected "downstream" from a fuse.
+
+	  This setting applies to all USB ports and controllers.
+
+config BRCM_FORCE_USB_OC_HI
+	bool "Active high"
+
+endchoice
+
+config BRCM_USB_DISABLE_MASK
+	hex "Bitmask of disabled USB hosts"
+	depends on BRCM_OVERRIDE_USB
+	default 0x00
+	help
+	  This is a bitmask to indicate which controllers should be
+	  disabled.  Disabling unused controllers may reduce boot time
+	  and free up system resources.
+
+	  Setting bit 0 will disable the first USB host.
+	  Setting bit 1 will disable the second USB host.
+	  Setting bit 2 will disable the third USB host.
+	  ...
+
+	  If unsure, say 0x00.
+
+
+# NOTE: SDIO_V1 hardware only (vanilla kernel driver sdhci-pltfm.c)
+config BRCM_SDIO
+	bool "Broadcom SDHCI (SDIO) support"
+	depends on BRCM_HAS_SDIO_V1 && MMC_SDHCI && !BRCM_IKOS
+	default y
+	select MMC_SDHCI_IO_ACCESSORS
+	help
+	  Say Y to enable the driver for the onchip SDIO controller.
+
+	  If you do not plan on using this device, disabling CONFIG_MMC
+	  will save about 75KB.
+
+	  If unsure, say Y.
+
+
+config BRCM_PM
+	bool "Power management for onchip peripherals"
+	default y
+	help
+	  Say Y to enable power management (clock gating) for onchip
+	  peripherals like USB, ENET/GENET, MoCA, and SATA.
+
+
+choice
+	prompt "System clocksource"
+	depends on BRCMSTB && MIPS
+	default CSRC_R4K_BRCMSTB if !SMP && !BRCM_CPU_DIV
+	default CSRC_WKTMR if BRCM_HAS_WKTMR
+	default CSRC_UPG
+	help
+	  The clocksource is used to maintain the real-time clock and
+	  calculate delays.
+
+config CSRC_WKTMR
+	bool "WKTMR"
+	depends on BRCM_HAS_WKTMR
+	help
+	  Say Y to use the 27Mhz "WKTMR" clocksource.  This is usually
+	  the best choice.
+
+config CSRC_R4K_BRCMSTB
+	bool "CP0 COUNT/COMPARE"
+	depends on !BRCM_CPU_DIV
+	select CSRC_R4K
+	help
+	  Say Y to use the CP0 COUNT/COMPARE timer.  This should not be
+	  used in SMP mode because each CPU (TP) has its own independent
+	  counter which is not coherent with the other TP's counter.
+
+config CSRC_UPG
+	bool "UPG TIMER3"
+	help
+	  Say Y to use the 27Mhz UPG TIMER3 as the system clocksource.
+	  On most older chips with no WKTMR, this is the best
+	  choice.  However, this timer will be owned by the kernel
+	  so applications will not be able to use it.
+
+endchoice
+
+
+#####################################################################
+# User options: Miscellaneous options
+#####################################################################
+
+
+comment "Miscellaneous options"
+	depends on BRCMSTB
+
+# PR10860 - Allow long long types to be used in modules
+config BRCM_LIBGCC
+	bool "Enable libgcc functions"
+	depends on BRCMSTB && MIPS
+	default y
+	help
+	  This will build and export several libgcc functions that are
+	  useful for 64-bit (long long) arithmetic.
+
+	  If unsure, say Y.
+
+
+config BRCM_SCSI_NO_RW10_RETRIES
+	bool "No retries on SCSI READ/WRITE10 command"
+	depends on SCSI
+	default n
+	help
+	  Certain applications prefer minimal retries on reading/writing
+	  bad sectors that will be performed at lower level like libata.
+	  Say Y to abort the transaction early instead of attempting
+	  potentially time-consuming retries.
+
+config BRCM_WLAN_MODULES
+	bool "Enable wireless extensions for external modules"
+	default y
+	select WIRELESS_EXT
+	select WEXT_PRIV
+	help
+	  Say Y to enable support for wireless drivers compiled out of tree.
+
+
+#####################################################################
+# User options: Debugging options
+#####################################################################
+
+
+config BRCM_DEBUG_OPTIONS
+	bool "Debugging options"
+	depends on BRCMSTB
+	default n
+	help
+	  Show extra debugging options.
+
+
+config NO_INLINE
+	bool "Disable inlining"
+	depends on BRCM_DEBUG_OPTIONS
+	default n
+	help
+	  Say Y here if you want to disable inlining.  This can make it easier
+	  to step through disassembled code.
+
+
+config BRCM_IKOS
+	bool "Enable IKOS/Veloce emulation"
+	depends on BRCM_DEBUG_OPTIONS
+	select BRCM_OVERRIDE_RAM_SIZE
+	help
+	  Configure kernel for IKOS/Veloce emulation.  This has the
+	  following effects:
+
+	  Disable any drivers not supported in emulation
+	  Prevent UART drivers from changing the divisor set by the bootloader
+
+config BRCM_IKOS_DEBUG
+	bool "Extra debug output during boot"
+	depends on BRCM_IKOS
+	default y
+	help
+	  Enable additional debugging output on the console by adding
+	  "initcall_debug debug" to the kernel command line.  This will slow
+	  down the emulation but can help troubleshoot boot failures.
+
+
+#####################################################################
+# Hidden options: MIPS
+#####################################################################
+
+
+config BRCM_HAS_BMIPS3300
+	bool
+	select SYS_HAS_CPU_BMIPS3300
+	select BRCM_CPU_DIV
+
+config BRCM_HAS_BMIPS4380
+	bool
+	select SYS_HAS_CPU_BMIPS4380
+	select BRCM_CPU_DIV
+
+config BRCM_HAS_BMIPS5000
+	bool
+	select SYS_HAS_CPU_BMIPS5000
+	select BRCM_CPU_DIV
+	select BRCM_ZSCM_L2
+	select SYS_SUPPORTS_HIGHMEM
+
+
+#####################################################################
+# Hidden options: UART
+#####################################################################
+
+
+config BRCM_HAS_16550
+	bool
+	select SERIAL_8250
+	select SERIAL_8250_CONSOLE
+
+config BRCM_HAS_UARTA
+	bool
+
+config BRCM_HAS_UARTB
+	bool
+
+config BRCM_HAS_UARTC
+	bool
+
+config BRCM_UARTA_IS_16550
+	bool
+	select BRCM_HAS_16550
+	select BRCM_HAS_UARTA
+
+config BRCM_UARTB_IS_16550
+	bool
+	select BRCM_HAS_16550
+	select BRCM_HAS_UARTB
+
+config BRCM_UARTC_IS_16550
+	bool
+	select BRCM_HAS_16550
+	select BRCM_HAS_UARTC
+
+
+#####################################################################
+# Hidden options: Onchip peripherals/capabilities
+#####################################################################
+
+
+config BRCM_HAS_PCIE
+	bool
+	select HW_HAS_PCI if !BRCM_IKOS
+
+config BRCM_GENET_V1
+	bool
+
+config BRCM_GENET_V2
+	bool
+
+config BRCM_GENET_V3
+	bool
+
+config BRCM_GENET_V4
+	bool
+
+config BRCM_GENET_VERSION
+	int
+	default 1 if BRCM_GENET_V1
+	default 2 if BRCM_GENET_V2
+	default 3 if BRCM_GENET_V3
+	default 4 if BRCM_GENET_V4
+
+# standalone or MoCA GENET controller
+config BRCM_HAS_GENET
+	bool
+
+# select for standalone GENET_0
+config BRCM_HAS_GENET_0
+	bool
+	select BRCM_HAS_GENET
+
+# select for standalone GENET_1
+config BRCM_HAS_GENET_1
+	bool
+	select BRCM_HAS_GENET
+
+# MoCA controller
+config BRCM_HAS_MOCA
+	bool
+
+# Original MoCA 1.1 (gen1 firmware)
+config BRCM_HAS_MOCA_11
+	bool
+	select BRCM_HAS_MOCA
+
+# Cost-reduced MoCA 1.1 with limited TX RAM (gen1 firmware)
+config BRCM_HAS_MOCA_11_LITE
+	bool
+	select BRCM_HAS_MOCA
+
+# MoCA 1.1 with selected 2.0 features (gen2 firmware)
+config BRCM_HAS_MOCA_11_PLUS
+	bool
+	select BRCM_HAS_MOCA
+
+# MoCA 2.0 (gen3 firmware for 1.1, gen2x firmware for 2.0)
+config BRCM_HAS_MOCA_20_GEN21
+	bool
+	select BRCM_HAS_MOCA
+
+config BRCM_HAS_MOCA_20_GEN22
+	bool
+	select BRCM_HAS_MOCA
+
+config BRCM_HAS_MOCA_20_GEN23
+	bool
+	select BRCM_HAS_MOCA
+
+config BRCM_MOCA_VERS
+	hex
+	default 0x1100 if BRCM_HAS_MOCA_11
+	default 0x1101 if BRCM_HAS_MOCA_11_LITE
+	default 0x1102 if BRCM_HAS_MOCA_11_PLUS
+	default 0x2001 if BRCM_HAS_MOCA_20_GEN21
+	default 0x2002 if BRCM_HAS_MOCA_20_GEN22
+	default 0x2003 if BRCM_HAS_MOCA_20_GEN23
+
+# select for MoCA on GENET_0
+config BRCM_MOCA_ON_GENET_0
+	bool
+	select BRCM_HAS_GENET_0
+
+# select for MoCA on GENET_1
+config BRCM_MOCA_ON_GENET_1
+	bool
+	select BRCM_HAS_GENET_1
+
+# MoCA is MidRF (default is HighRF)
+config BRCM_HAS_MOCA_MIDRF
+	bool
+
+config BRCM_HAS_DVD
+	bool
+
+config BRCM_HAS_SATA
+	bool
+
+config BRCM_HAS_SATA2
+	bool
+	select BRCM_HAS_SATA
+	select HW_HAS_PCI if !BRCM_IKOS
+
+config BRCM_HAS_SATA3
+	bool
+	select BRCM_HAS_SATA
+	select SATA_AHCI_PLATFORM if ATA
+
+config BRCM_SATA_75MHZ_PLL
+	bool
+	default n
+
+config BRCM_SATA_SINGLE_PORT
+	bool
+	default n
+
+config BRCM_HAS_NOR
+	bool
+
+config BRCM_HAS_NAND_MINOR_0
+	bool
+
+config BRCM_HAS_NAND_MINOR_1
+	bool
+
+config BRCM_HAS_NAND_MINOR_2
+	bool
+
+config BRCM_HAS_NAND_MINOR_3
+	bool
+
+config BRCM_HAS_NAND_MINOR_4
+	bool
+
+# major versions 0, 1, 2 are unsupported.
+config BRCM_HAS_NAND_MAJOR_0
+	bool
+
+config BRCM_HAS_NAND_MAJOR_1
+	bool
+
+config BRCM_HAS_NAND_MAJOR_2
+	bool
+
+config BRCM_HAS_NAND_MAJOR_3
+	bool
+	select BRCM_HAS_NAND
+
+config BRCM_HAS_NAND_MAJOR_4
+	bool
+	select BRCM_HAS_NAND
+
+config BRCM_HAS_NAND_MAJOR_5
+	bool
+	select BRCM_HAS_NAND
+
+config BRCM_HAS_NAND_MAJOR_6
+	bool
+	select BRCM_HAS_NAND
+
+config BRCM_HAS_NAND_MAJOR_7
+	bool
+	select BRCM_HAS_NAND
+
+
+config BRCMNAND_MAJOR_VERS
+	int
+	default "7" if BRCM_HAS_NAND_MAJOR_7
+	default "6" if BRCM_HAS_NAND_MAJOR_6
+	default "5" if BRCM_HAS_NAND_MAJOR_5
+	default "4" if BRCM_HAS_NAND_MAJOR_4
+	default "3" if BRCM_HAS_NAND_MAJOR_3
+	default "2" if BRCM_HAS_NAND_MAJOR_2
+	default "1" if BRCM_HAS_NAND_MAJOR_1
+	default "0" if BRCM_HAS_NAND_MAJOR_0
+
+config BRCMNAND_MINOR_VERS
+	int
+	default "4" if BRCM_HAS_NAND_MINOR_4
+	default "3" if BRCM_HAS_NAND_MINOR_3
+	default "2" if BRCM_HAS_NAND_MINOR_2
+	default "1" if BRCM_HAS_NAND_MINOR_1
+	default "0" if BRCM_HAS_NAND_MINOR_0
+
+config BRCM_HAS_NAND
+	bool
+
+config BRCM_HAS_EDU
+	bool
+	depends on !BRCM_HAS_FLASH_DMA
+
+config BRCM_HAS_FLASH_DMA
+	bool
+
+config BRCM_HAS_SPI
+	bool
+
+# v2 is not supported on 2.6.31
+config BRCM_HAS_BSPI_V2
+	bool
+
+config BRCM_HAS_BSPI_V3
+	bool
+	select BRCM_HAS_SPI
+
+config BRCM_HAS_BSPI_V4
+	bool
+	select BRCM_HAS_SPI
+
+config BRCM_BSPI_MAJOR_VERS
+	int
+	default "4" if BRCM_HAS_BSPI_V4
+	default "3" if BRCM_HAS_BSPI_V3
+	default "2" if BRCM_HAS_BSPI_V2
+
+# MSPI can transfer either 64b or 8b per slot
+config BRCM_MSPI_64B_WORDS
+	bool
+
+config BRCM_HAS_WKTMR
+	bool
+
+config BRCM_HAS_SDIO
+	bool
+
+# V0 hardware is ignored on 2.6.37+
+config BRCM_HAS_SDIO_V0
+	bool
+
+config BRCM_HAS_SDIO_V1
+	bool
+	select BRCM_HAS_SDIO
+
+config BRCM_HAS_EMMC
+	bool
+
+config BRCM_ZSCM_L2
+	bool
+	select MIPS_CPU_SCACHE
+
+# PM: adjustable CPU clock divisor
+config BRCM_CPU_DIV
+	bool
+
+# PM: low power "halt" state with IR wakeup
+config BRCM_IRW_HALT
+	bool
+
+# MIPS: extended kseg0/kseg1 feature
+config BRCM_HAS_XKS01
+	bool
+
+# MIPS: eXecute Inhibit (for no-exec stack)
+config BRCM_HAS_XI
+	bool
+
+# MIPS: 2-core * 2-thread = 4-way SMP (BMIPS5200)
+config BRCM_HAS_DUALCORE
+	bool
+
+config BRCM_HAS_UPPER_MEMORY
+	bool
+
+config BRCM_UPPER_768MB
+	bool
+	select XKS01
+
+# physical address maps supporting 256MB, 512MB, or 1GB on MEMC0
+config BRCM_HAS_1GB_MEMC0
+	bool
+
+# physical address map supporting 2GB on MEMC0
+config BRCM_HAS_2GB_MEMC0
+	bool
+
+# MEMC1 is accessible to the CPU and all Linux peripherals
+config BRCM_HAS_1GB_MEMC1
+	bool
+
+config BRCM_HAS_ANALOG_DDR_PHY
+	bool
+
+config BRCM_HAS_DIGITAL_DDR_PHY
+	bool
+
+
+# no handshake (no bsp_rdy signal) means the SW has to manually set SSPD
+config BRCM_PWR_HANDSHAKE
+	bool
+
+# 40nm A0; 65nm
+config BRCM_PWR_HANDSHAKE_V0
+	bool
+	select BRCM_PWR_HANDSHAKE
+
+# 40nm B0
+config BRCM_PWR_HANDSHAKE_V1
+	bool
+	select BRCM_PWR_HANDSHAKE
+
+# USB_CAPS controller enumeration - 40nm
+config BRCM_HAS_USB_CAPS
+	bool
+
+config BRCM_MIPS_DEFAULTS
+	bool
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_BIG_ENDIAN
+	select SYS_SUPPORTS_LITTLE_ENDIAN
+	select SYS_HAS_EARLY_PRINTK
+	select SERIAL
+	select SYS_SUPPORTS_KGDB
+	select CEVT_R4K
+	select BOOT_RAW
+	select CFE
+	# select ARCH_SUSPEND_POSSIBLE
+
+config BRCM_ARM_DEFAULTS
+	bool
+	select ARCH_REQUIRE_GPIOLIB
+	select ARM_PATCH_PHYS_VIRT
+	select ARM_GIC
+	select CPU_V7
+	select DW_APB_TIMER
+	select GENERIC_CLOCKEVENTS
+	select GENERIC_GPIO
+	select HAVE_SCHED_CLOCK
+	select HAVE_TCM
+	select NO_IOPORT
+	select SPARSE_IRQ
+	select USE_OF
+	select HAVE_SMP
+
+
+#####################################################################
+# Hidden options: Chip shortcuts
+#####################################################################
+
+config BCM7228
+	bool
+
+config BCM7231
+	bool
+
+config BCM7344
+	bool
+
+config BCM7346
+	bool
+
+config BCM7358
+	bool
+
+config BCM7360
+	bool
+
+config BCM7362
+	bool
+
+config BCM7425
+	bool
+
+config BCM7429
+	bool
+
+config BCM7435
+	bool
+
+config BCM7543
+	bool
+
+config BCM7552
+	bool
+
+config BCM7563
+	bool
+
+config BCM7584
+	bool
+
+endmenu
diff --git a/drivers/brcmstb/Makefile b/drivers/brcmstb/Makefile
new file mode 100644
index 0000000..f173970
--- /dev/null
+++ b/drivers/brcmstb/Makefile
@@ -0,0 +1,4 @@
+obj-y			+= bchip.o bmem.o board.o setup.o \
+	sysfs.o power.o memc1.o m2m.o s3.o
+
+obj-$(CONFIG_PCI)	+= pci.o
diff --git a/drivers/brcmstb/bchip.c b/drivers/brcmstb/bchip.c
new file mode 100644
index 0000000..7bae487
--- /dev/null
+++ b/drivers/brcmstb/bchip.c
@@ -0,0 +1,561 @@
+/*
+ * Copyright (C) 2009 - 2012 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/dma-mapping.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/bitops.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/compiler.h>
+
+#include <linux/brcmstb/brcmstb.h>
+
+#include "../drivers/mmc/host/sdhci.h"
+#include "../drivers/mmc/host/sdhci-pltfm.h"
+
+/* chip features */
+int brcm_sata_enabled;
+int brcm_pcie_enabled;
+int brcm_moca_enabled;
+int brcm_usb_enabled;
+int brcm_pm_enabled;
+
+/* synchronize writes to shared registers */
+DEFINE_SPINLOCK(brcm_magnum_spinlock);
+EXPORT_SYMBOL(brcm_magnum_spinlock);
+
+/* system / device settings */
+unsigned long brcm_dram0_size_mb;
+unsigned long brcm_dram1_size_mb;
+unsigned long brcm_dram1_linux_mb;
+unsigned long brcm_dram1_start = MEMC1_START;
+unsigned long brcm_min_auth_region_size = 0x1000;
+
+unsigned char brcm_eth0_phy[CFE_STRING_SIZE];
+unsigned long brcm_eth0_speed;
+unsigned long brcm_eth0_no_mdio;
+unsigned char brcm_eth0_phyaddr[CFE_STRING_SIZE];
+
+u8 brcm_primary_macaddr[IFHWADDRLEN] = { 0x00, 0x00, 0xde, 0xad, 0xbe, 0xef };
+
+unsigned long brcm_base_baud0 = BRCM_BASE_BAUD_STB;	/* UPG UARTA */
+unsigned long brcm_base_baud = BRCM_BASE_BAUD_STB;	/* UPG_UART[BC] */
+
+struct bcmemac_platform_data genet_pdata[BRCM_MAX_GENET];
+
+/***********************************************************************
+ * Per-chip operations
+ ***********************************************************************/
+
+#define ALT_CHIP_ID(chip, rev) do { \
+	u32 arg_id = 0x ## chip; \
+	const u8 rev_name[] = #rev; \
+	u32 arg_rev = ((rev_name[0] - 'a') << 4) | (rev_name[1] - '0'); \
+	if (!kernel_chip_id && arg_id == chip_id) { \
+		kernel_chip_id = arg_id; \
+		kernel_chip_rev = arg_rev; \
+	} \
+	} while (0)
+
+#define MAIN_CHIP_ID(chip, rev) do { \
+	u32 arg_id = 0x ## chip; \
+	const u8 rev_name[] = #rev; \
+	u32 arg_rev = ((rev_name[0] - 'a') << 4) | (rev_name[1] - '0'); \
+	if (!kernel_chip_id) { \
+		kernel_chip_id = arg_id; \
+		kernel_chip_rev = arg_rev; \
+	} \
+	} while (0)
+
+/*
+ * NOTE: This is a quick sanity test to catch known incompatibilities and
+ * obvious chip ID mismatches.  It is not comprehensive.  Higher revs may
+ * or may not maintain software compatibility.
+ *
+ * MAIN_CHIP_ID() must always be the final entry.
+ */
+
+void __init bchip_check_compat(void)
+{
+	u32 chip_id = BRCM_CHIP_ID(), chip_rev = BRCM_CHIP_REV();
+	u32 kernel_chip_id = 0, kernel_chip_rev = 0;
+
+#if defined(CONFIG_BCM7231)
+	MAIN_CHIP_ID(7231, b0);
+#elif defined(CONFIG_BCM7344)
+	MAIN_CHIP_ID(7344, b0);
+#elif defined(CONFIG_BCM7346)
+	ALT_CHIP_ID(73465, a0);
+	MAIN_CHIP_ID(7346, b0);
+#elif defined(CONFIG_BCM7358)
+	/* 7358 kernel can boot on 7552, but not vice-versa */
+	ALT_CHIP_ID(7552, a0);
+	MAIN_CHIP_ID(7358, a0);
+#elif defined(CONFIG_BCM7360)
+	MAIN_CHIP_ID(7360, a0);
+#elif defined(CONFIG_BCM7362)
+	ALT_CHIP_ID(73625, a0);
+	MAIN_CHIP_ID(7362, a0);
+#elif defined(CONFIG_BCM7425)
+	MAIN_CHIP_ID(7425, b0);
+#elif defined(CONFIG_BCM7429)
+	ALT_CHIP_ID(74295, a0);
+	MAIN_CHIP_ID(7429, a0);
+#elif defined(CONFIG_BCM7435)
+	MAIN_CHIP_ID(7435, a0);
+#elif defined(CONFIG_BCM7552)
+	MAIN_CHIP_ID(7552, b0);
+#elif defined(CONFIG_BCM7563)
+	ALT_CHIP_ID(75525, a0);
+	ALT_CHIP_ID(75635, a0);
+	MAIN_CHIP_ID(7563, a0);
+#elif defined(CONFIG_BCM7584)
+	ALT_CHIP_ID(75845, a0);
+	MAIN_CHIP_ID(7584, a0);
+#endif
+	if (!kernel_chip_id)
+		return;
+
+	if (chip_id != kernel_chip_id)
+		cfe_die("PANIC: BCM%04x kernel cannot boot on "
+			"BCM%04x chip.\n", kernel_chip_id, chip_id);
+
+	if (chip_rev < kernel_chip_rev)
+		cfe_die("PANIC: This kernel requires BCM%04x rev >= %02X "
+			"(P%02x)\n", kernel_chip_id,
+			kernel_chip_rev + 0xa0, kernel_chip_rev + 0x10);
+}
+
+/***********************************************************************
+ * Common operations for all chips
+ ***********************************************************************/
+
+#ifdef CONFIG_BRCM_HAS_SATA3
+
+#ifdef __BIG_ENDIAN
+#define DATA_ENDIAN             2       /* AHCI->DDR inbound accesses */
+#define MMIO_ENDIAN             2       /* MIPS->AHCI outbound accesses */
+#else
+#define DATA_ENDIAN             0
+#define MMIO_ENDIAN             0
+#endif /* __BIG_ENDIAN */
+
+/* SATA3 SSC per-port bitfield */
+static u32 sata3_enable_ssc;
+
+#define SATA3_MDIO_TXPMD_0_REG_BANK	0x1A0
+#define SATA3_MDIO_BRIDGE_BASE		(BCHP_SATA_GRB_REG_START + 0x100)
+#define SATA3_MDIO_BASE_REG_ADDR	(SATA3_MDIO_BRIDGE_BASE + 0x8F * 4)
+
+#define SATA_AHCI_GHC_CAP		(BCHP_SATA_AHCI_GHC_REG_START + 0x0)
+#define SATA_AHCI_GHC_PORTS_IMPLEMENTED	(BCHP_SATA_AHCI_GHC_REG_START + 0xC)
+
+#define HOST_CAP_NCQ			(1 << 30)
+
+#define SATA_TOP_CTRL_BUS_CTRL			0x4
+#define SATA_TOP_CTRL_BUS_CTRL_OVERRIDE_HWINIT	(1 << 16)
+
+#define SATA3_TXPMD_CONTROL1			0x81
+#define SATA3_TXPMD_TX_FREQ_CTRL_CONTROL1	0x82
+#define SATA3_TXPMD_TX_FREQ_CTRL_CONTROL2	0x83
+#define SATA3_TXPMD_TX_FREQ_CTRL_CONTROL3	0x84
+
+static inline void brcm_sata3_mdio_wr_reg(u32 bank, unsigned int ofs, u32 msk,
+		u32 enable)
+{
+	u32 tmp;
+	BDEV_WR(SATA3_MDIO_BASE_REG_ADDR, bank);
+	/* Read, mask, enable */
+	tmp = BDEV_RD(ofs * 4 + SATA3_MDIO_BRIDGE_BASE);
+	tmp = (tmp & msk) | enable;
+	/* Write */
+	BDEV_WR(ofs * 4 + SATA3_MDIO_BRIDGE_BASE, tmp);
+}
+
+static void brcm_sata3_init_freq(int port, int ssc_enable)
+{
+	u32 bank = SATA3_MDIO_TXPMD_0_REG_BANK + port * 0x10;
+
+	if (ssc_enable)
+		pr_info("SATA3: enabling SSC on port %d\n", port);
+
+	/* TXPMD_control1 - enable SSC force */
+	brcm_sata3_mdio_wr_reg(bank, SATA3_TXPMD_CONTROL1, 0xFFFFFFFC,
+			0x00000003);
+
+	/* TXPMD_tx_freq_ctrl_control2 - set fixed min freq */
+	brcm_sata3_mdio_wr_reg(bank, SATA3_TXPMD_TX_FREQ_CTRL_CONTROL2,
+			0xFFFFFC00, 0x000003DF);
+
+	/*
+	 * TXPMD_tx_freq_ctrl_control3 - set fixed max freq
+	 *  If ssc_enable == 0, center frequencies
+	 *  Otherwise, spread spectrum frequencies
+	 */
+	if (ssc_enable)
+		brcm_sata3_mdio_wr_reg(bank, SATA3_TXPMD_TX_FREQ_CTRL_CONTROL3,
+				0xFFFFFC00, 0x00000083);
+	else
+		brcm_sata3_mdio_wr_reg(bank, SATA3_TXPMD_TX_FREQ_CTRL_CONTROL3,
+				0xFFFFFC00, 0x000003DF);
+}
+
+/* Check up to 32 ports, although we typically only have 2 */
+#define SATA_MAX_CHECK_PORTS	32
+
+/*
+ * Check commandline for 'sata3_ssc' options. They can be specified in 2 ways:
+ *  (1) 'sata3_ssc'     -> enable SSC on all ports
+ *  (2) 'sata3_ssc=x,y' -> enable SSC on specific port(s), given a comma-
+ *                         separated list of port numbers
+ */
+static int __init sata3_ssc_setup(char *str)
+{
+	int opts[SATA_MAX_CHECK_PORTS + 1], i;
+
+	if (*str == '\0') {
+		/* enable SSC on all ports */
+		sata3_enable_ssc = ~0;
+		return 0;
+	}
+	get_options(str + 1, SATA_MAX_CHECK_PORTS, opts);
+
+	for (i = 0; i < opts[0]; i++) {
+		int port = opts[i + 1];
+		if ((port >= 0) && (port < SATA_MAX_CHECK_PORTS))
+			sata3_enable_ssc |= 1 << port;
+	}
+
+	return 0;
+}
+
+__setup("sata3_ssc", sata3_ssc_setup);
+
+/*
+ * Disables NCQ at the SATA AHCI core level by clearing the bit that indicates
+ * support for it.
+ */
+static void brcm_sata3_disable_ncq(void)
+{
+	u32 top_ctrl = BCHP_SATA_TOP_CTRL_REG_START + SATA_TOP_CTRL_BUS_CTRL;
+
+	BDEV_SET(top_ctrl, SATA_TOP_CTRL_BUS_CTRL_OVERRIDE_HWINIT);
+
+	/*
+	 * Clear out the NCQ bit so the AHCI driver will not issue FPDMA/NCQ
+	 * commands.
+	 */
+	BDEV_UNSET(SATA_AHCI_GHC_CAP, HOST_CAP_NCQ);
+
+	BDEV_UNSET(top_ctrl, SATA_TOP_CTRL_BUS_CTRL_OVERRIDE_HWINIT);
+}
+#endif /* CONFIG_BRCM_HAS_SATA3 */
+
+void bchip_sata3_init(void)
+{
+#ifdef CONFIG_BRCM_HAS_SATA3
+	int i, ports = fls(BDEV_RD(SATA_AHCI_GHC_PORTS_IMPLEMENTED));
+
+	brcm_sata3_disable_ncq();
+
+	/*
+	 * On BE systems, the AHCI register data is endian-swapped past
+	 * this point.  This affects SATA_AHCI_GHC_* and other ranges,
+	 * but not SATA_TOP_CONTROL or MDIO.
+	 */
+	BDEV_WR(BCHP_SATA_TOP_CTRL_BUS_CTRL, (DATA_ENDIAN << 4) |
+			(DATA_ENDIAN << 2) | (MMIO_ENDIAN << 0));
+
+	for (i = 0; i < ports; i++)
+		brcm_sata3_init_freq(i, sata3_enable_ssc & (1 << i));
+#endif
+}
+
+#ifdef __LITTLE_ENDIAN
+#define USB_ENDIAN		0x03 /* !WABO !FNBO FNHW BABO */
+#else
+#define USB_ENDIAN		0x0e /* WABO FNBO FNHW !BABO */
+#endif
+
+#define USB_ENDIAN_MASK		0x0f
+#define USB_IOC			BCHP_USB_CTRL_SETUP_IOC_MASK
+#define USB_IPP			BCHP_USB_CTRL_SETUP_IPP_MASK
+
+#define USB_REG(x, y)		(x + BCHP_USB_CTRL_##y - \
+				 BCHP_USB_CTRL_REG_START)
+
+static void bchip_usb_init_one(int id, uintptr_t base)
+{
+	/* endianness setup */
+	BDEV_UNSET_RB(USB_REG(base, SETUP), USB_ENDIAN_MASK);
+	BDEV_SET_RB(USB_REG(base, SETUP), USB_ENDIAN);
+
+	/* power control setup */
+#ifdef CONFIG_BRCM_OVERRIDE_USB
+
+#ifdef CONFIG_BRCM_FORCE_USB_OC_LO
+	BDEV_SET(USB_REG(base, SETUP), USB_IOC);
+#else
+	BDEV_UNSET(USB_REG(base, SETUP), USB_IOC);
+#endif
+
+#ifdef CONFIG_BRCM_FORCE_USB_PWR_LO
+	BDEV_SET(USB_REG(base, SETUP), USB_IPP);
+#else
+	BDEV_UNSET(USB_REG(base, SETUP), USB_IPP);
+#endif
+
+#else /* CONFIG_BRCM_OVERRIDE_USB */
+	if ((BDEV_RD(USB_REG(base, SETUP)) & USB_IOC) == 0) {
+		printk(KERN_WARNING "USB%d: IOC was not set by the bootloader;"
+			" forcing default settings\n", id);
+		BDEV_SET(USB_REG(base, SETUP), USB_IOC);
+		BDEV_SET(USB_REG(base, SETUP), USB_IPP);
+	}
+#endif /* CONFIG_BRCM_OVERRIDE_USB */
+
+	printk(KERN_INFO "USB%d: power enable is active %s; overcurrent is "
+		"active %s\n", id,
+		BDEV_RD(USB_REG(base, SETUP)) & USB_IPP ? "low" : "high",
+		BDEV_RD(USB_REG(base, SETUP)) & USB_IOC ? "low" : "high");
+
+	/* PR45703 - for OHCI->SCB bridge lockup */
+	BDEV_UNSET(USB_REG(base, OBRIDGE),
+		BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK);
+
+	/* Disable EHCI transaction combining */
+	BDEV_UNSET(USB_REG(base, EBRIDGE),
+		BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK);
+
+	/* SWLINUX-1705: Avoid OUT packet underflows */
+	BDEV_UNSET(USB_REG(base, EBRIDGE),
+		BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK);
+	BDEV_SET(USB_REG(base, EBRIDGE),
+		0x08 << BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT);
+
+#if defined(CONFIG_BRCM_HAS_1GB_MEMC1)
+	/* enable access to SCB1 */
+	BDEV_SET(USB_REG(base, SETUP), BIT(14));
+
+#if defined(CONFIG_BCM7425B0) || defined(CONFIG_BCM7435B0)
+	/* SWLINUX-2259 - Work around a USB DMA to memc1 arbitration bug */
+	BDEV_SET(USB_REG(base, SETUP), BIT(13));
+#endif
+
+#endif
+
+#if defined(BCHP_USB_CTRL_GENERIC_CTL_1_PLL_SUSPEND_EN_MASK)
+	BDEV_SET(USB_REG(base, GENERIC_CTL_1),
+		BCHP_USB_CTRL_GENERIC_CTL_1_PLL_SUSPEND_EN_MASK);
+#elif defined(BCHP_USB_CTRL_GENERIC_CTL_PLL_SUSPEND_EN_MASK)
+	BDEV_SET(USB_REG(base, GENERIC_CTL),
+		BCHP_USB_CTRL_GENERIC_CTL_PLL_SUSPEND_EN_MASK);
+#elif defined(BCHP_USB_CTRL_PLL_CTL_1_PLL_SUSPEND_EN_MASK)
+	BDEV_SET(USB_REG(base, PLL_CTL_1),
+		BCHP_USB_CTRL_PLL_CTL_1_PLL_SUSPEND_EN_MASK);
+#elif defined(BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK)
+	BDEV_SET(USB_REG(base, PLL_CTL),
+		BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK);
+#endif
+
+}
+
+void bchip_usb_init(void)
+{
+	bchip_usb_init_one(0, BCHP_USB_CTRL_REG_START);
+#ifdef BCHP_USB1_CTRL_REG_START
+	if (BRCM_PROD_ID() != 0x74285)
+		bchip_usb_init_one(1, BCHP_USB1_CTRL_REG_START);
+#endif
+}
+
+#if defined(CONFIG_BRCM_HAS_MOCA)
+void bchip_moca_init(void)
+{
+#ifdef BCHP_SUN_TOP_CTRL_SW_RESET
+	BDEV_WR_F_RB(SUN_TOP_CTRL_SW_RESET, moca_sw_reset, 0);
+#else
+	BDEV_WR_F_RB(SUN_TOP_CTRL_SW_INIT_0_CLEAR, moca_sw_init, 1);
+#endif
+
+#ifdef BCHP_MOCA_HOSTMISC_SW_RESET_moca_enet_reset_MASK
+	BDEV_WR_F_RB(MOCA_HOSTMISC_SW_RESET, moca_enet_reset, 0);
+#endif
+}
+#endif
+
+void __init bchip_set_features(void)
+{
+#if defined(CONFIG_BRCM_HAS_SATA)
+	brcm_sata_enabled = 1;
+#endif
+#if defined(CONFIG_BRCM_HAS_PCIE)
+	brcm_pcie_enabled = 1;
+#endif
+#if defined(CONFIG_SMP) && defined(CONFIG_MIPS)
+	bmips_smp_enabled = 1;
+#endif
+#if defined(CONFIG_BRCM_HAS_MOCA)
+	brcm_moca_enabled = 1;
+#endif
+#if defined(CONFIG_BRCM_PM)
+	brcm_pm_enabled = 1;
+#endif
+	brcm_usb_enabled = 1;
+
+	/* now remove any features disabled in hardware */
+
+#ifdef BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_MASK
+	if (BDEV_RD_F(SUN_TOP_CTRL_OTP_OPTION_STATUS_0,
+			otp_option_sata_disable) == 1)
+		brcm_sata_enabled = 0;
+#endif
+
+#ifdef BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_MASK
+	if (BDEV_RD_F(SUN_TOP_CTRL_OTP_OPTION_STATUS_0,
+			otp_option_usb_disable) == 1)
+		brcm_usb_enabled = 0;
+#endif
+
+#ifdef BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_MASK
+	if (BDEV_RD_F(SUN_TOP_CTRL_OTP_OPTION_STATUS_0,
+			otp_option_moca_disable) == 1)
+		brcm_moca_enabled = 0;
+#endif
+
+#ifdef BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pcie_disable_MASK
+	if (BDEV_RD_F(SUN_TOP_CTRL_OTP_OPTION_STATUS_0,
+			otp_option_pcie_disable) == 1)
+		brcm_pcie_enabled = 0;
+#endif
+
+#ifdef CONFIG_BCM7425
+	/* disable PCIe initialization in EP mode */
+	if (BDEV_RD_F(SUN_TOP_CTRL_STRAP_VALUE_0, strap_rc_ep) == 0)
+		brcm_pcie_enabled = 0;
+#endif
+}
+
+void __init bchip_early_setup(void)
+{
+#if defined(CONFIG_BRCM_HAS_WKTMR)
+	struct wktmr_time t;
+
+	if (!(BDEV_RD(AON_RAM(122)) & (3<<30))) {
+		BDEV_WR_F_RB(WKTMR_EVENT, wktmr_alarm_event, 1);
+		BDEV_WR_F_RB(WKTMR_PRESCALER, wktmr_prescaler, WKTMR_FREQ);
+		BDEV_WR_F_RB(WKTMR_COUNTER, wktmr_counter, 0);
+
+		/* wait for first tick so we know the counter is ready to use */
+		wktmr_read(&t);
+		while (wktmr_elapsed(&t) == 0)
+			;
+	}
+#endif
+
+#ifdef CONFIG_PCI
+	if (brcm_pcie_enabled)
+		brcm_early_pcie_setup();
+#endif
+
+	/*
+	 * Initial GENET defaults
+	 * These can be overridden by board_pinmux_setup() or by CFE vars
+	 */
+#if defined(CONFIG_BRCM_HAS_GENET_0)
+
+	genet_pdata[0].base_reg = BCHP_GENET_0_SYS_REG_START;
+	genet_pdata[0].irq0 = BRCM_IRQ_GENET_0_A;
+	genet_pdata[0].irq1 = BRCM_IRQ_GENET_0_B;
+
+#if defined(CONFIG_BRCM_MOCA_ON_GENET_0)
+	if (brcm_moca_enabled) {
+		genet_pdata[0].phy_type = BRCM_PHY_TYPE_MOCA;
+		genet_pdata[0].phy_id = BRCM_PHY_ID_NONE;
+	} else {
+		genet_pdata[0].phy_type = BRCM_PHY_TYPE_EXT_RGMII;
+		genet_pdata[0].phy_id = BRCM_PHY_ID_AUTO;
+	}
+#else
+	genet_pdata[0].phy_type = BRCM_PHY_TYPE_INT;
+	genet_pdata[0].phy_id = 1;
+#endif
+
+#endif
+
+#if defined(CONFIG_BRCM_HAS_GENET_1)
+
+	genet_pdata[1].base_reg = BCHP_GENET_1_SYS_REG_START;
+	genet_pdata[1].irq0 = BRCM_IRQ_GENET_1_A;
+	genet_pdata[1].irq1 = BRCM_IRQ_GENET_1_B;
+
+	genet_pdata[1].phy_type = BRCM_PHY_TYPE_EXT_RGMII;
+	genet_pdata[1].phy_id = BRCM_PHY_ID_AUTO;
+
+#if defined(CONFIG_BRCM_MOCA_ON_GENET_1)
+	if (brcm_moca_enabled) {
+		genet_pdata[1].phy_type = BRCM_PHY_TYPE_MOCA;
+		genet_pdata[1].phy_id = BRCM_PHY_ID_NONE;
+	}
+#endif
+
+#endif
+}
+
+int brcm_alloc_macaddr(u8 *buf)
+{
+	memcpy(buf, brcm_primary_macaddr, ETH_ALEN);
+	brcm_primary_macaddr[4]++;
+	return 0;
+}
+EXPORT_SYMBOL(brcm_alloc_macaddr);
+
+/***********************************************************************
+ * WKTMR utility functions (boot time only)
+ ***********************************************************************/
+
+void wktmr_read(struct wktmr_time *t)
+{
+	uint32_t tmp;
+
+	do {
+		t->sec = BDEV_RD(BCHP_WKTMR_COUNTER);
+		tmp = BDEV_RD(BCHP_WKTMR_PRESCALER_VAL);
+	} while (tmp >= WKTMR_FREQ);
+
+	t->pre = WKTMR_FREQ - tmp;
+}
+
+unsigned long wktmr_elapsed(struct wktmr_time *t)
+{
+	struct wktmr_time now;
+
+	wktmr_read(&now);
+	now.sec -= t->sec;
+	if (now.pre >= t->pre) {
+		now.pre -= t->pre;
+	} else {
+		now.pre = WKTMR_FREQ + now.pre - t->pre;
+		now.sec--;
+	}
+	return (now.sec * WKTMR_FREQ) + now.pre;
+}
+
diff --git a/drivers/brcmstb/bmem.c b/drivers/brcmstb/bmem.c
new file mode 100644
index 0000000..57f9b76
--- /dev/null
+++ b/drivers/brcmstb/bmem.c
@@ -0,0 +1,376 @@
+/*
+ * Copyright (C) 2012 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/bootmem.h>
+#include <linux/spinlock.h>
+#include <linux/mm.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/ioport.h>
+#include <linux/list.h>
+#include <linux/vmalloc.h>
+#include <linux/compiler.h>
+#include <linux/module.h>
+
+#include <linux/brcmstb/brcmstb.h>
+
+#if 0
+#define DBG printk
+#else
+#define DBG(...) /* */
+#endif
+
+#define LINUX_MIN_MEM		64
+#define MAX_BMEM_REGIONS	4
+
+struct bmem_region {
+	unsigned long		addr;
+	unsigned long		size;
+	int			valid;
+};
+
+static struct bmem_region bmem_regions[MAX_BMEM_REGIONS];
+static unsigned int n_bmem_regions;
+
+#if defined(CONFIG_BRCM_IKOS)
+static unsigned int bmem_disabled = 1;
+#else
+static unsigned int bmem_disabled;
+#endif
+
+/***********************************************************************
+ * MEMC1 handling
+ ***********************************************************************/
+
+static int __init brcm_memc1_bmem(void)
+{
+	struct bmem_region *r = NULL;
+
+	if (brcm_dram1_size_mb &&
+			brcm_dram1_size_mb > brcm_dram1_linux_mb &&
+			n_bmem_regions < MAX_BMEM_REGIONS) {
+		r = &bmem_regions[n_bmem_regions++];
+		r->addr = brcm_dram1_start + (brcm_dram1_linux_mb << 20);
+		r->size = (brcm_dram1_size_mb - brcm_dram1_linux_mb) << 20;
+		r->valid = 1;
+		printk(KERN_INFO "bmem: adding extra %lu MB RESERVED region at "
+			"%lu MB (0x%08lx@0x%08lx)\n", r->size >> 20,
+			r->addr >> 20, r->size, r->addr);
+	}
+	return 0;
+}
+
+core_initcall(brcm_memc1_bmem);
+
+/***********************************************************************
+ * BMEM (reserved A/V buffer memory) support
+ ***********************************************************************/
+
+/*
+ * Parses command line for bmem= options
+ */
+static int __init bmem_setup(char *str)
+{
+	unsigned long addr = 0, size;
+	unsigned long lower_mem_bytes;
+	char *orig_str = str;
+
+	lower_mem_bytes = (brcm_dram0_size_mb > BRCM_MAX_LOWER_MB) ?
+		(BRCM_MAX_LOWER_MB << 20) : (brcm_dram0_size_mb << 20);
+
+	size = (unsigned long)memparse(str, &str);
+	if (*str == '@')
+		addr = (unsigned long)memparse(str + 1, &str);
+
+	if ((size > 0x40000000) || (addr > 0x80000000)) {
+		printk(KERN_WARNING "bmem: argument '%s' "
+			"is out of range, ignoring\n", orig_str);
+		return 0;
+	}
+
+	if (size == 0) {
+		printk(KERN_INFO "bmem: disabling reserved memory\n");
+		bmem_disabled = 1;
+		return 0;
+	}
+
+	if ((addr & ~PAGE_MASK) || (size & ~PAGE_MASK)) {
+		printk(KERN_WARNING "bmem: ignoring invalid range '%s' "
+			"(is it missing an 'M' suffix?)\n", orig_str);
+		return 0;
+	}
+
+	if (addr == 0) {
+		/*
+		 * default: bmem=xxM allocates xx megabytes at the end of
+		 * lower memory
+		 */
+		if (size >= lower_mem_bytes) {
+			printk(KERN_WARNING "bmem: '%s' is larger than "
+				"lower memory (%lu MB), ignoring\n",
+				orig_str, brcm_dram0_size_mb);
+			return 0;
+		}
+		addr = lower_mem_bytes - size;
+	}
+
+	if (n_bmem_regions == MAX_BMEM_REGIONS) {
+		printk(KERN_WARNING "bmem: too many regions, "
+			"ignoring extras\n");
+		return 0;
+	}
+
+	bmem_regions[n_bmem_regions].addr = addr;
+	bmem_regions[n_bmem_regions].size = size;
+	n_bmem_regions++;
+
+	return 0;
+}
+
+early_param("bmem", bmem_setup);
+
+/*
+ * Returns index if the supplied range falls entirely within a bmem region
+ */
+int bmem_find_region(unsigned long addr, unsigned long size)
+{
+	int i, idx = 0;
+
+	for (i = 0; i < n_bmem_regions; i++) {
+		if (!bmem_regions[i].valid)
+			continue;
+		if ((addr >= bmem_regions[i].addr) &&
+		    ((addr + size) <=
+			(bmem_regions[i].addr + bmem_regions[i].size))) {
+			return idx;
+		}
+		idx++;
+	}
+	return -ENOENT;
+}
+EXPORT_SYMBOL(bmem_find_region);
+
+/*
+ * Finds the IDX'th valid bmem region, and fills in addr/size if it exists.
+ * Returns 0 on success, <0 on failure.
+ */
+int bmem_region_info(int idx, unsigned long *addr, unsigned long *size)
+{
+	int i;
+
+	for (i = 0; i < n_bmem_regions; i++) {
+		if (!bmem_regions[i].valid)
+			continue;
+		if (!idx) {
+			*addr = bmem_regions[i].addr;
+			*size = bmem_regions[i].size;
+			return 0;
+		}
+		idx--;
+	}
+	return -ENOENT;
+}
+EXPORT_SYMBOL(bmem_region_info);
+
+/*
+ * Special handling for __get_user_pages() on BMEM reserved memory:
+ *
+ * 1) Override the VM_IO | VM_PFNMAP sanity checks
+ * 2) No cache flushes (this is explicitly under application control)
+ * 3) vm_normal_page() does not work on these regions
+ * 4) Don't need to worry about any kinds of faults; pages are always present
+ *
+ * The vanilla kernel behavior was to prohibit O_DIRECT operations on our
+ * BMEM regions, but direct I/O is absolutely required for PVR and video
+ * playback from SATA/USB.
+ */
+int bmem_get_page(struct mm_struct *mm, struct vm_area_struct *vma,
+	unsigned long start, struct page **page)
+{
+	unsigned long pg = start & PAGE_MASK, pfn;
+	int ret = -EFAULT;
+	pgd_t *pgd;
+	pud_t *pud;
+	pmd_t *pmd;
+	pte_t *pte;
+
+	pgd = pgd_offset(mm, pg);
+	BUG_ON(pgd_none(*pgd));
+	pud = pud_offset(pgd, pg);
+	BUG_ON(pud_none(*pud));
+	pmd = pmd_offset(pud, pg);
+	if (pmd_none(*pmd))
+		return ret;
+
+	pte = pte_offset_map(pmd, pg);
+	if (pte_none(*pte))
+		goto out;
+
+	pfn = pte_pfn(*pte);
+	if (!pfn_valid(pfn))
+		goto out;
+
+	if (likely(bmem_find_region(pfn << PAGE_SHIFT, PAGE_SIZE) < 0))
+		goto out;
+
+	if (page) {
+		*page = pfn_to_page(pfn);
+		get_page(*page);
+	}
+	ret = 0;
+
+out:
+	pte_unmap(pte);
+	return ret;
+}
+
+static int __initdata bmem_defaults_set;
+
+static void __init brcm_set_default_bmem(void)
+{
+	/*
+	 * Default: (no valid bmem= options specified)
+	 *
+	 * Lower memory is the first 256MB of system RAM.
+	 * bmem gets all but (LINUX_MIN_MEM) megabytes of lower memory.
+	 * Linux gets all upper and high memory (if present).
+	 *
+	 * Options:
+	 *
+	 * Define one or more custom bmem regions, e.g.:
+	 *   bmem=128M (128MB region at the end of lower memory)
+	 *   bmem=128M@64M (128MB hole at 64MB mark)
+	 *   bmem=16M@64M bmem=4M@128M bmem=16M@200M (multiple holes)
+	 *
+	 * Disable bmem; give all system RAM to the Linux VM:
+	 *   bmem=0
+	 *
+	 * Overlapping or invalid regions will usually be silently dropped.
+	 * If you are doing something tricky, watch the boot messages to
+	 * make sure it turns out the way you intended.
+	 */
+	if (bmem_disabled) {
+		n_bmem_regions = 0;
+	} else {
+		if (n_bmem_regions == 0 &&
+		    (brcm_dram0_size_mb > LINUX_MIN_MEM)) {
+			n_bmem_regions = 1;
+			bmem_regions[0].addr = LINUX_MIN_MEM << 20;
+			bmem_regions[0].size =
+				(((brcm_dram0_size_mb <= BRCM_MAX_LOWER_MB) ?
+				  brcm_dram0_size_mb : BRCM_MAX_LOWER_MB) -
+				 LINUX_MIN_MEM) << 20;
+		}
+	}
+}
+
+/*
+ * Invokes free_bootmem(), but truncates ranges where necessary to
+ * avoid releasing the bmem region(s) back to the VM
+ */
+void __init brcm_free_bootmem(unsigned long addr, unsigned long size)
+{
+	if (!bmem_defaults_set) {
+		brcm_set_default_bmem();
+		bmem_defaults_set = 1;
+	}
+
+	while (size) {
+		unsigned long chunksize = size;
+		int i;
+		struct bmem_region *r = NULL;
+
+		/*
+		 * Find the first bmem region (if any) that fits entirely
+		 * within the current bootmem address range.
+		 */
+		for (i = 0; i < n_bmem_regions; i++) {
+			if ((bmem_regions[i].addr >= addr) &&
+			    ((bmem_regions[i].addr + bmem_regions[i].size) <=
+			     (addr + size))) {
+				if (!r || (r->addr > bmem_regions[i].addr))
+					r = &bmem_regions[i];
+			}
+		}
+
+		/*
+		 * Skip over every bmem region; call free_bootmem() for
+		 * every Linux region.  A Linux region is created for
+		 * each chunk of the memory map that is not reserved
+		 * for bmem.
+		 */
+		if (r) {
+			if (addr == r->addr) {
+				printk(KERN_INFO "bmem: adding %lu MB "
+					"RESERVED region at %lu MB "
+					"(0x%08lx@0x%08lx)\n",
+					r->size >> 20, r->addr >> 20,
+					r->size, r->addr);
+				chunksize = r->size;
+				r->valid = 1;
+				goto skip;
+			} else {
+				BUG_ON(addr > r->addr);
+				chunksize = r->addr - addr;
+			}
+		}
+		BUG_ON(chunksize > size);
+
+		printk(KERN_DEBUG "bmem: adding %lu MB LINUX region at %lu MB "
+			"(0x%08lx@0x%08lx)\n", chunksize >> 20, addr >> 20,
+			chunksize, addr);
+		free_bootmem(addr, chunksize);
+
+skip:
+		addr += chunksize;
+		size -= chunksize;
+	}
+}
+
+/*
+ * Create /proc/iomem entries for bmem
+ */
+static int __init bmem_region_setup(void)
+{
+	int i, idx = 0;
+
+	for (i = 0; i < n_bmem_regions; i++) {
+		struct resource *r;
+		char *name;
+
+		if (!bmem_regions[i].valid)
+			continue;
+
+		r = kzalloc(sizeof(*r), GFP_KERNEL);
+		name = kzalloc(16, GFP_KERNEL);
+		if (!r || !name)
+			break;
+
+		sprintf(name, "bmem.%d", idx);
+		r->start = bmem_regions[i].addr;
+		r->end = bmem_regions[i].addr + bmem_regions[i].size - 1;
+		r->flags = IORESOURCE_MEM;
+		r->name = name;
+
+		insert_resource(&iomem_resource, r);
+		idx++;
+	}
+	return 0;
+}
+
+arch_initcall(bmem_region_setup);
+
diff --git a/drivers/brcmstb/board.c b/drivers/brcmstb/board.c
new file mode 100644
index 0000000..2cc19bb
--- /dev/null
+++ b/drivers/brcmstb/board.c
@@ -0,0 +1,839 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/smp.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/bitops.h>
+#include <linux/bmoca.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/brcmstb/brcmstb.h>
+
+/* board features */
+int brcm_docsis_platform;
+char brcm_cfe_boardname[CFE_STRING_SIZE];
+
+/* MTD partition layout */
+unsigned long brcm_mtd_rootfs_start;
+unsigned long brcm_mtd_rootfs_len;
+unsigned long brcm_mtd_kernel_start;
+unsigned long brcm_mtd_kernel_len;
+unsigned long brcm_mtd_ocap_start;
+unsigned long brcm_mtd_ocap_len;
+unsigned long brcm_mtd_flash_size_mb;
+char brcm_mtd_flash_type[CFE_STRING_SIZE];
+
+/* MoCA 3450 I2C port */
+unsigned long brcm_moca_i2c_base;
+
+/* Default MoCA RF band (can be overridden in board_pinmux_setup) */
+#ifdef CONFIG_BRCM_HAS_MOCA_MIDRF
+unsigned long brcm_moca_rf_band = MOCA_BAND_MIDRF;
+#else
+unsigned long brcm_moca_rf_band = MOCA_BAND_HIGHRF;
+#endif
+
+/***********************************************************************
+ * PIN_MUX setup
+ *
+ * NOTE: This code assumes that the bootloader already set up the pinmux
+ * for the primary UART (almost always UARTA) and EBI.
+ *
+ * This code is free to modify genet_pdata[].  For example, to set up an
+ * external RGMII PHY on GENET_0, set up your pinmux / pad voltages /
+ * pulldowns then add:
+ *
+ *   genet_pdata[0].phy_type = BRCM_PHY_TYPE_EXT_RGMII;
+ *   genet_pdata[0].phy_id = BRCM_PHY_ID_AUTO;
+ ***********************************************************************/
+
+#define PINMUX(reg, field, val) do { \
+	BDEV_WR(BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_##reg, \
+		(BDEV_RD(BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_##reg) & \
+		 ~BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_##reg##_##field##_MASK) | \
+		((val) << \
+		 BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_##reg##_##field##_SHIFT)); \
+	} while (0)
+
+#define AON_PINMUX(reg, field, val) do { \
+	BDEV_WR(BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_##reg, \
+		(BDEV_RD(BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_##reg) & \
+		 ~BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_##reg##_##field##_MASK) | \
+		((val) << \
+		 BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_##reg##_##field##_SHIFT)); \
+	} while (0)
+
+#define PADCTRL(reg, field, val) do { \
+	BDEV_WR(BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_##reg, \
+		(BDEV_RD(BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_##reg) & \
+		 ~BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_##reg##_##field##_MASK) | \
+		((val) << \
+		 BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_##reg##_##field##_SHIFT)); \
+	} while (0)
+
+#define AON_PADCTRL(reg, field, val) do { \
+	BDEV_WR(BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_##reg, \
+		(BDEV_RD(BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_##reg) & \
+		 ~BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_##reg##_##field##_MASK) | \
+		((val) << \
+		 BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_##reg##_##field##_SHIFT)); \
+	} while (0)
+
+
+#define SDIO_CFG_REG(x, y)	(BCHP_SDIO_##x##_CFG_REG_START + \
+				 (BCHP_SDIO_0_CFG_##y - \
+				  BCHP_SDIO_0_CFG_REG_START))
+
+void board_pinmux_setup(void)
+{
+	static int __maybe_unused sdio_0_disabled = -1;
+	static int __maybe_unused sdio_1_disabled = -1;
+
+#if !defined(CONFIG_BRCM_IKOS)
+#if defined(CONFIG_BCM7231)
+
+	PINMUX(11, gpio_94, 1);		/* UARTB TX */
+	PINMUX(11, gpio_95, 1);		/* UARTB RX */
+
+	if (BRCM_PROD_ID() == 0x7230) {
+		/* 7230 is not the same ballout as 7231 */
+		AON_PINMUX(0, aon_gpio_04, 6);	/* SDIO */
+		AON_PINMUX(0, aon_gpio_05, 6);
+		AON_PINMUX(1, aon_gpio_12, 5);
+		AON_PINMUX(1, aon_gpio_13, 5);
+		AON_PINMUX(2, aon_gpio_14, 5);
+		AON_PINMUX(2, aon_gpio_15, 6);
+		AON_PINMUX(2, aon_gpio_16, 6);
+		AON_PINMUX(2, aon_gpio_17, 6);
+		AON_PINMUX(2, aon_gpio_18, 6);
+		AON_PINMUX(2, aon_gpio_19, 6);
+
+		/* disable GPIO pulldowns */
+		BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0,
+			aon_gpio_04_pad_ctrl, 0);
+		BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0,
+			aon_gpio_05_pad_ctrl, 0);
+		BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
+			aon_gpio_12_pad_ctrl, 0);
+		BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
+			aon_gpio_13_pad_ctrl, 0);
+		BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
+			aon_gpio_14_pad_ctrl, 0);
+		BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
+			aon_gpio_15_pad_ctrl, 0);
+		BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
+			aon_gpio_16_pad_ctrl, 0);
+		BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
+			aon_gpio_17_pad_ctrl, 0);
+		BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
+			aon_gpio_18_pad_ctrl, 0);
+		BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
+			aon_gpio_19_pad_ctrl, 0);
+	} else {
+		/* set RGMII lines to 2.5V */
+		BDEV_WR_F(SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0,
+			rgmii_0_pad_mode, 1);
+
+		PINMUX(15, gpio_132, 1);	/* RGMII RX */
+		PINMUX(15, gpio_133, 1);
+		PINMUX(15, gpio_134, 1);
+		PINMUX(16, gpio_139, 1);
+		PINMUX(16, gpio_140, 1);
+		PINMUX(16, gpio_141, 1);
+		PINMUX(16, gpio_142, 1);
+
+		PINMUX(16, gpio_138, 1);	/* RGMII TX */
+		PINMUX(17, gpio_143, 1);
+		PINMUX(17, gpio_144, 1);
+		PINMUX(17, gpio_145, 1);
+		PINMUX(17, gpio_146, 1);
+		PINMUX(17, gpio_147, 1);
+
+		PINMUX(17, gpio_149, 1);	/* RGMII MDIO */
+		PINMUX(16, gpio_137, 1);
+
+		/* no pulldown on RGMII lines */
+		PADCTRL(8, gpio_132_pad_ctrl, 0);
+		PADCTRL(8, gpio_133_pad_ctrl, 0);
+		PADCTRL(8, gpio_134_pad_ctrl, 0);
+		PADCTRL(8, gpio_137_pad_ctrl, 0);
+		PADCTRL(8, gpio_138_pad_ctrl, 0);
+		PADCTRL(9, gpio_139_pad_ctrl, 0);
+		PADCTRL(9, gpio_140_pad_ctrl, 0);
+		PADCTRL(9, gpio_141_pad_ctrl, 0);
+		PADCTRL(9, gpio_142_pad_ctrl, 0);
+		PADCTRL(9, gpio_143_pad_ctrl, 0);
+		PADCTRL(9, gpio_144_pad_ctrl, 0);
+		PADCTRL(9, gpio_145_pad_ctrl, 0);
+		PADCTRL(9, gpio_146_pad_ctrl, 0);
+		PADCTRL(9, gpio_147_pad_ctrl, 0);
+		PADCTRL(9, gpio_149_pad_ctrl, 0);
+
+		PINMUX(14, gpio_122, 1);	/* SDIO */
+		PINMUX(14, gpio_123, 1);
+		PINMUX(14, gpio_124, 1);
+		PINMUX(14, gpio_125, 1);
+		PINMUX(14, gpio_126, 1);
+		PINMUX(15, gpio_127, 1);
+		PINMUX(15, gpio_128, 1);
+		PINMUX(15, gpio_129, 1);
+		PINMUX(15, gpio_130, 1);
+		PINMUX(15, gpio_131, 1);
+
+		/* no pulldown on SDIO lines */
+		PADCTRL(7, gpio_122_pad_ctrl, 0);
+		PADCTRL(7, gpio_123_pad_ctrl, 0);
+		PADCTRL(8, gpio_124_pad_ctrl, 0);
+		PADCTRL(8, gpio_125_pad_ctrl, 0);
+		PADCTRL(8, gpio_126_pad_ctrl, 0);
+		PADCTRL(8, gpio_127_pad_ctrl, 0);
+		PADCTRL(8, gpio_128_pad_ctrl, 0);
+		PADCTRL(8, gpio_129_pad_ctrl, 0);
+		PADCTRL(8, gpio_130_pad_ctrl, 0);
+		PADCTRL(8, gpio_131_pad_ctrl, 0);
+
+		genet_pdata[1].phy_speed = SPEED_1000;
+		genet_pdata[1].phy_type = BRCM_PHY_TYPE_EXT_RGMII_NO_ID;
+	}
+
+#elif defined(CONFIG_BCM7344)
+
+	PINMUX(15, gpio_79, 1);		/* MoCA link */
+	PINMUX(15, gpio_80, 1);		/* MoCA activity */
+
+	PINMUX(17, uart_rxdb, 0);	/* UARTB RX */
+	PINMUX(17, uart_txdb, 0);	/* UARTB TX */
+
+	PINMUX(0, gpio_68, 3);		/* SDIO */
+	PINMUX(0, gpio_69, 3);
+	PINMUX(0, gpio_70, 3);
+	PINMUX(0, gpio_71, 2);
+	PINMUX(0, gpio_72, 2);
+	PINMUX(0, gpio_73, 2);
+	PINMUX(0, gpio_74, 2);
+	PINMUX(0, gpio_75, 2);
+	PINMUX(1, gpio_76, 2);
+	PINMUX(1, gpio_77, 2);
+
+	/* enable pullup on SDIO lines */
+	PADCTRL(0, gpio_68_pad_ctrl, 2);
+	PADCTRL(0, gpio_69_pad_ctrl, 2);
+	PADCTRL(0, gpio_70_pad_ctrl, 2);
+	PADCTRL(0, gpio_71_pad_ctrl, 2);
+	PADCTRL(0, gpio_72_pad_ctrl, 2);
+	PADCTRL(0, gpio_73_pad_ctrl, 2);
+	PADCTRL(0, gpio_74_pad_ctrl, 2);
+	PADCTRL(0, gpio_75_pad_ctrl, 2);
+	PADCTRL(0, gpio_76_pad_ctrl, 2);
+	PADCTRL(0, gpio_77_pad_ctrl, 2);
+
+	AON_PINMUX(0, aon_gpio_00, 3);	/* UARTC RX (NC) */
+	AON_PINMUX(0, aon_gpio_01, 3);	/* UARTC TX (NC) */
+
+	PINMUX(16, sgpio_04, 1);	/* MoCA I2C */
+	PINMUX(16, sgpio_05, 1);
+	brcm_moca_i2c_base = BPHYSADDR(BCHP_BSCD_REG_START);
+
+	/* 7344 is normally MidRF, but some 7418 boards are HighRF */
+	if (strstarts(brcm_cfe_boardname, "BCM97418SAT") ||
+	    strstarts(brcm_cfe_boardname, "BCM97418SFF_RVU"))
+		brcm_moca_rf_band = MOCA_BAND_MIDRF;
+	else if (strstarts(brcm_cfe_boardname, "BCM97418"))
+		brcm_moca_rf_band = MOCA_BAND_HIGHRF;
+
+#elif defined(CONFIG_BCM7346)
+
+	PINMUX(15, gpio_068, 2);	/* MoCA link */
+	PINMUX(16, gpio_069, 1);	/* MoCA activity */
+
+	PINMUX(9, gpio_017, 1);		/* UARTB TX */
+	PINMUX(9, gpio_018, 1);		/* UARTB RX */
+	PINMUX(10, gpio_021, 1);	/* UARTC TX */
+	PINMUX(10, gpio_022, 1);	/* UARTC RX */
+
+	PINMUX(16, sgpio_02, 1);	/* MoCA I2C on BSCB */
+	PINMUX(16, sgpio_03, 1);
+	brcm_moca_i2c_base = BPHYSADDR(BCHP_BSCB_REG_START);
+
+	/*
+	 * To enable SDIO_LED (activity LED) on the BCM97346 reference boards:
+	 * install R1127, remove R1120, uncomment this line, and don't use MoCA
+	 */
+	/* PINMUX(16, sgpio_02, 3); */
+
+	PINMUX(17, vo_656_5, 2);	/* SDIO_PRES */
+	PINMUX(17, vo_656_4, 1);	/* SDIO_PWR0 */
+	PINMUX(17, vo_656_3, 2);	/* SDIO_DAT3 */
+	PINMUX(17, vo_656_2, 2);	/* SDIO_DAT1 */
+	PINMUX(17, vo_656_1, 2);	/* SDIO_DAT1 */
+	PINMUX(17, vo_656_0, 2);	/* SDIO_DAT0 */
+
+	PINMUX(18, vo_656_clk, 1);	/* SDIO_CLK */
+	PINMUX(18, vo_656_7, 1);	/* SDIO_CMD */
+	PINMUX(18, vo_656_6, 2);	/* SDIO_WPROT */
+
+#elif	defined(CONFIG_BCM7228) || \
+	defined(CONFIG_BCM7358) || \
+	defined(CONFIG_BCM7552) || \
+	defined(CONFIG_BCM7360) || \
+	defined(CONFIG_BCM7362)
+
+    #if !defined(CONFIG_DREAMBOX_DM520)
+	PINMUX(11, gpio_89, 1);		/* UARTB TX */
+	PINMUX(11, gpio_90, 1);		/* UARTB RX */
+	PINMUX(11, gpio_91, 1);		/* UARTC TX */
+	PINMUX(11, gpio_92, 1);		/* UARTC RX */
+
+	AON_PINMUX(1, aon_gpio_08, 6);	/* SDIO */
+	AON_PINMUX(1, aon_gpio_12, 5);
+	AON_PINMUX(1, aon_gpio_13, 5);
+	AON_PINMUX(2, aon_gpio_14, 4);
+	AON_PINMUX(2, aon_gpio_15, 5);
+	AON_PINMUX(2, aon_gpio_16, 5);
+	AON_PINMUX(2, aon_gpio_17, 5);
+	AON_PINMUX(2, aon_gpio_18, 5);
+	AON_PINMUX(2, aon_gpio_19, 5);
+	AON_PINMUX(2, aon_gpio_20, 5);
+
+	/* enable SDIO pullups */
+	AON_PADCTRL(0, aon_gpio_08_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_12_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_13_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_14_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_15_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_16_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_17_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_18_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_19_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_20_pad_ctrl, 2);
+    #else
+	/* add dm520 specific pinmux needed for kernel here... */
+    #endif
+
+#elif defined(CONFIG_BCM7425)
+
+	if (sdio_0_disabled < 0)
+		/* Bootloader indicates availability of SDIO_0 in SCRATCH reg */
+		sdio_0_disabled = BDEV_RD(SDIO_CFG_REG(0, SCRATCH)) & 0x01;
+
+	if (!sdio_0_disabled) {
+		PINMUX(14, gpio_072, 2);
+		PINMUX(14, gpio_073, 2);
+		PINMUX(14, gpio_074, 2);
+		PINMUX(14, gpio_075, 2);
+		PINMUX(15, gpio_076, 2);
+		PINMUX(15, gpio_077, 2);
+		PINMUX(15, gpio_078, 2);
+		PINMUX(15, gpio_079, 2);
+		PINMUX(15, gpio_080, 2);
+		PINMUX(15, gpio_081, 2);
+
+		/* enable internal pullups */
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9,
+			gpio_072_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			gpio_073_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			gpio_074_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			gpio_075_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			gpio_076_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			gpio_077_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			gpio_078_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			gpio_079_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			gpio_080_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			gpio_081_pad_ctrl, 2);
+
+		/* always use 3.3V (SDIO0_LOW_V_SEL_N=1) */
+		/* V00 boards or A0 parts */
+		BDEV_UNSET(BCHP_GIO_AON_IODIR_LO, 1 << 4);
+		BDEV_SET(BCHP_GIO_AON_DATA_LO, 1 << 4);
+		/* V10 boards with B parts use SDIO0_VOLT signal */
+		AON_PINMUX(2, gpio_100, 5);
+	}
+
+	PINMUX(18, sgpio_00, 1);	/* MoCA I2C */
+	PINMUX(19, sgpio_01, 1);
+#if defined(CONFIG_BCM7425B0)
+	brcm_moca_i2c_base = BPHYSADDR(BCHP_BSCC_REG_START);
+#else
+	brcm_moca_i2c_base = BPHYSADDR(BCHP_BSCA_REG_START);
+#endif
+
+#elif defined(CONFIG_BCM7435)
+
+#if 0
+	PINMUX(16, gpio_088, 1);        /* MoCA LEDs */
+	PINMUX(16, gpio_087, 1);
+
+	PINMUX(18, sgpio_00, 1);        /* MoCA I2C */
+	PINMUX(19, sgpio_01, 1);
+	brcm_moca_i2c_base = BPHYSADDR(BCHP_BSCC_REG_START);
+#endif
+
+	if (sdio_0_disabled < 0)
+		/* Bootloader indicates availability of SDIO_0 in SCRATCH reg */
+		sdio_0_disabled = BDEV_RD(SDIO_CFG_REG(0, SCRATCH)) & 0x01;
+
+	/* always enabled because of dm820/dm7080 fastboot */
+	if (1 || !sdio_0_disabled) {
+		PINMUX(14, gpio_072, 2);
+		PINMUX(14, gpio_073, 2);
+		PINMUX(14, gpio_074, 2);
+		PINMUX(14, gpio_075, 2);
+		PINMUX(15, gpio_076, 2);
+		PINMUX(15, gpio_077, 2);
+		PINMUX(15, gpio_078, 2);
+		PINMUX(15, gpio_079, 2);
+		PINMUX(15, gpio_080, 2);
+		PINMUX(15, gpio_081, 2);
+
+		/* enable internal pullups */
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			     gpio_072_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			     gpio_073_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			     gpio_074_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			     gpio_075_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			     gpio_076_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			     gpio_077_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			     gpio_078_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			     gpio_079_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			     gpio_080_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			     gpio_081_pad_ctrl, 2);
+
+		/* SDIO0_VOLT signal */
+//		AON_PINMUX(2, gpio_100, 5);
+	}
+
+	/* set RGMII lines to 2.5V */
+	BDEV_WR_F(SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0, rgmii_0_pad_sel, 1);
+
+	/* If GENET_0 is not configured for internal mode, set
+	 * the pins in EMAC0_ mode
+	 */
+	if (strcmp(brcm_eth0_phy, "INT")) {
+		PINMUX(5, gpio_003, 1);	/* RX_EN_CTL */
+		PINMUX(5, gpio_002, 1); /* RX_CLK */
+		PINMUX(5, gpio_001, 1); /* ENET_LINK */
+		PINMUX(5, gpio_000, 1); /* ENET_ACTIVITY */
+		PINMUX(6, gpio_011, 1); /* TXD_01 */
+		PINMUX(6, gpio_010, 1); /* TXD_00 */
+		PINMUX(6, gpio_009, 1); /* TX_EN_CTL */
+		PINMUX(6, gpio_008, 1); /* TX_CLK */
+		PINMUX(6, gpio_007, 1); /* RXD_03 */
+		PINMUX(6, gpio_006, 1); /* RXD_02 */
+		PINMUX(6, gpio_005, 1); /* RXD_01 */
+		PINMUX(6, gpio_004, 1); /* RXD_00 */
+		PINMUX(7, gpio_015, 2); /* EMAC0_MDC */
+		PINMUX(7, gpio_014, 2); /* EMAC0_MDIO */
+		PINMUX(7, gpio_013, 1); /* TXD_03 */
+		PINMUX(7, gpio_012, 1); /* TXD_02 */
+	}
+
+
+#elif defined(CONFIG_BCM7429)
+
+	PINMUX(11, gpio_094, 1);	/* UARTB TX */
+	PINMUX(11, gpio_095, 1);	/* UARTB RX */
+	PINMUX(12, gpio_096, 1);	/* UARTC TX */
+	PINMUX(12, gpio_097, 1);	/* UARTC RX */
+
+	AON_PINMUX(1, aon_gpio_11, 7);	/* MoCA LEDs */
+	AON_PINMUX(2, aon_gpio_14, 5);
+
+	PINMUX(18, sgpio_00, 1);	/* MoCA I2C */
+	PINMUX(18, sgpio_01, 1);
+	brcm_moca_i2c_base = BPHYSADDR(BCHP_BSCD_REG_START);
+
+	if (sdio_0_disabled < 0)
+		/* Bootloader indicates availability of SDIO_0 in SCRATCH reg */
+		sdio_0_disabled = BDEV_RD(SDIO_CFG_REG(0, SCRATCH)) & 0x01;
+
+	if (!sdio_0_disabled) {
+		/*
+		 * 7241[5] uses GPIO_092 for UART_TX0 instead of SDIO0_VCTL so
+		 * leave it alone. We don't need SDIO0_VCTL because the board
+		 * is 3.3V only and doesn't use it.
+		 */
+		if (!(BRCM_PROD_ID() == 0x7241 ||
+		      BRCM_PROD_ID() == 0x7242 ||
+		      BRCM_PROD_ID() == 0x72415 ||
+		      BRCM_PROD_ID() == 0x72425))
+			PINMUX(11, gpio_092, 5);
+		PINMUX(14, gpio_122, 1);
+		PINMUX(14, gpio_123, 1);
+		PINMUX(14, gpio_124, 1);
+		PINMUX(15, gpio_125, 1);
+		PINMUX(15, gpio_126, 1);
+		PINMUX(15, gpio_127, 1);
+		PINMUX(15, gpio_128, 1);
+		PINMUX(15, gpio_129, 1);
+		PINMUX(15, gpio_131, 1);
+		/*
+		 * 7428[5] pinout uses GPIO_93 for SDIO0_PRES
+		 * 7429[5] pinout uses GPIO_130 for SDIO0_PRES
+		 */
+		if (BRCM_PROD_ID() == 0x7428 || BRCM_PROD_ID() == 0x74285) {
+			PINMUX(11, gpio_093, 5);
+		} else
+			PINMUX(15, gpio_130, 1);
+
+		/* enable internal pullups */
+		if (!(BRCM_PROD_ID() == 0x7241 ||
+		      BRCM_PROD_ID() == 0x7242 ||
+		      BRCM_PROD_ID() == 0x72415 ||
+		      BRCM_PROD_ID() == 0x72425))
+			BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6,
+						 gpio_092_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8,
+			gpio_122_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8,
+			gpio_123_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8,
+			gpio_124_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8,
+			gpio_125_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8,
+			gpio_126_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8,
+			gpio_127_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8,
+			gpio_128_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8,
+			gpio_129_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9,
+			gpio_130_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9,
+			gpio_131_pad_ctrl, 2);
+	}
+
+	if (sdio_1_disabled < 0)
+		/* Bootloader indicates availability of SDIO_1 in SCRATCH reg */
+		sdio_1_disabled = BDEV_RD(SDIO_CFG_REG(1, SCRATCH)) & 0x01;
+
+	if (!sdio_1_disabled)
+		/* default SDIO1 to eMMC */
+		BDEV_SET(BCHP_HIF_TOP_CTRL_EMMC_PIN_CTRL, 0x00000001);
+
+	/* GENET_1 is connected to BCM60321 via EXT_MII on BCM97241PLC
+	 * and GENET_1 is connected to a BCM53101 on BCM97241DCSFBTSFF
+	 */
+	if (!strcmp(brcm_cfe_boardname, "BCM97241PLC") ||
+		!strcmp(brcm_cfe_boardname, "BCM97241DCSFBTSFF")) {
+		/* set GENET_1 MII pinmuxing */
+		PINMUX(15, gpio_132, 1);	/* MII_RX_DV */
+		PINMUX(16, gpio_133, 1);	/* MII_RX_ER */
+		PINMUX(16, gpio_134, 1);	/* MII_RX_CLK */
+		PINMUX(16, gpio_135, 1);	/* MII_COL */
+		PINMUX(16, gpio_136, 1);	/* MII_CRS */
+		PINMUX(16, gpio_137, 1);	/* MII_MDIO */
+		PINMUX(16, gpio_138, 1);	/* MII_TX_CLK */
+		PINMUX(16, gpio_139, 1);	/* MII_RXD_03 */
+		PINMUX(16, gpio_140, 1);	/* MII_RXD_02 */
+		PINMUX(17, gpio_141, 1);	/* MII_RXD_01 */
+		PINMUX(17, gpio_142, 1);	/* MII_RXD_00 */
+		PINMUX(17, gpio_143, 1);	/* MII_TXD_03 */
+		PINMUX(17, gpio_144, 1);	/* MII_TXD_02 */
+		PINMUX(17, gpio_145, 1);	/* MII_TXD_01 */
+		PINMUX(17, gpio_146, 1);	/* MII_TXD_00 */
+		PINMUX(17, gpio_147, 1);	/* MII_TX_EN */
+		PINMUX(17, gpio_148, 1);	/* MII_TX_ER */
+		PINMUX(18, gpio_149, 1);	/* MII_MDC */
+
+		/* Switch MII control over GENET_1 */
+		BDEV_WR(BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0,
+			(BDEV_RD(BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0) |
+			BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_genet_mac_select_MASK));
+
+		/*
+		 * BCM60321 firmware will snoop MII bus, but avoid any MDIO
+		 * transaction to be safe. The same applies for the BCM53101.
+		 */
+		genet_pdata[1].phy_type = BRCM_PHY_TYPE_EXT_MII;
+		genet_pdata[1].phy_id = BRCM_PHY_ID_NONE;
+		genet_pdata[1].phy_speed = 100;
+
+		if (!strcmp(brcm_cfe_boardname, "BCM97241DCSFBTSFF"))
+			genet_pdata[1].sw_type = 0x53101;
+	}
+
+#elif defined(CONFIG_BCM7563)
+
+	/* NOTE: UARTB and UARTC are disabled by default */
+
+	AON_PINMUX(0, aon_gpio_01, 1);		/* ENET link */
+	PINMUX(4, gpio_105, 1);			/* ENET activity */
+
+	/* SDIO pinmux + pullups */
+	AON_PINMUX(1, aon_gpio_08, 6);
+	AON_PINMUX(1, aon_gpio_12, 5);
+	AON_PINMUX(1, aon_gpio_13, 5);
+	AON_PINMUX(2, aon_gpio_14, 5);
+	AON_PINMUX(2, aon_gpio_15, 5);
+	AON_PINMUX(2, aon_gpio_16, 5);
+	AON_PINMUX(2, aon_gpio_17, 5);
+	AON_PINMUX(2, aon_gpio_18, 5);
+	AON_PINMUX(2, aon_gpio_19, 5);
+	AON_PINMUX(2, aon_gpio_20, 5);
+
+	AON_PADCTRL(0, aon_gpio_08_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_12_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_13_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_14_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_15_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_16_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_17_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_18_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_19_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_20_pad_ctrl, 2);
+
+/*
+ * 75525 workarounds are needed because the RDB has changed but
+ * 75525 support is done using ALT_CHIP_ID() for the 7563 which
+ * means we can't included the proper RDB header files.
+ * 1. Locally define the new SD_PIN_SEL register.
+ * 2. The BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0 has a new field,
+ *    "sdio1_alt_pin_sel", which needs to be cleared when
+ *    selecting the AON pins via pinmux.
+ */
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL 0x00410354
+	if (BRCM_CHIP_ID() == 0x75525) {
+		BDEV_WR(SDIO_CFG_REG(0, SD_PIN_SEL), 0x00000002);
+		BDEV_UNSET(BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0, 0x00000001);
+	}
+#elif defined(CONFIG_BCM7584)
+
+	if (BRCM_PROD_ID() == 0x7583) {
+		/* 7583 ballout - SD card on alt pins, GENET_1 disabled */
+		AON_PINMUX(1, aon_gpio_12, 5);
+		AON_PINMUX(1, aon_gpio_13, 5);
+		AON_PINMUX(2, aon_gpio_14, 4);
+		AON_PINMUX(2, aon_gpio_15, 5);
+		AON_PINMUX(2, aon_gpio_16, 5);
+		AON_PINMUX(2, aon_gpio_17, 5);
+		AON_PINMUX(2, aon_gpio_18, 5);
+		AON_PINMUX(2, aon_gpio_19, 5);
+		AON_PINMUX(2, aon_gpio_20, 5);
+
+		AON_PADCTRL(1, aon_gpio_12_pad_ctrl, 2);
+		AON_PADCTRL(1, aon_gpio_13_pad_ctrl, 2);
+		AON_PADCTRL(1, aon_gpio_14_pad_ctrl, 2);
+		AON_PADCTRL(1, aon_gpio_15_pad_ctrl, 2);
+		AON_PADCTRL(1, aon_gpio_16_pad_ctrl, 2);
+		AON_PADCTRL(1, aon_gpio_17_pad_ctrl, 2);
+		AON_PADCTRL(1, aon_gpio_18_pad_ctrl, 2);
+		AON_PADCTRL(1, aon_gpio_19_pad_ctrl, 2);
+		AON_PADCTRL(1, aon_gpio_20_pad_ctrl, 2);
+	} else {
+		/* external BCM3349 on GENET_1 using reverse MII */
+		PINMUX(0, gpio_00, 2);
+		PINMUX(0, gpio_01, 2);
+		PINMUX(0, gpio_02, 2);
+		PINMUX(1, gpio_03, 2);
+		PINMUX(1, gpio_04, 2);
+		PINMUX(1, gpio_05, 2);
+		PINMUX(1, gpio_06, 2);
+		PINMUX(1, gpio_07, 2);
+		PINMUX(1, gpio_08, 2);
+		PINMUX(1, gpio_09, 2);
+		PINMUX(1, gpio_10, 2);
+		PINMUX(2, gpio_11, 2);
+		PINMUX(2, gpio_12, 2);
+		PINMUX(2, gpio_13, 2);
+		PINMUX(2, gpio_14, 2);
+		PINMUX(13, gpio_110, 1);
+
+		/* no MDIO in RvMII mode; avoid driving these pins */
+		PINMUX(15, gpio_123, 0);
+		PINMUX(15, gpio_124, 0);
+
+		/* no pulldowns on MII */
+		PADCTRL(0, gpio_00_pad_ctrl, 0);
+		PADCTRL(0, gpio_01_pad_ctrl, 0);
+		PADCTRL(0, gpio_02_pad_ctrl, 0);
+		PADCTRL(0, gpio_03_pad_ctrl, 0);
+		PADCTRL(0, gpio_04_pad_ctrl, 0);
+		PADCTRL(0, gpio_05_pad_ctrl, 0);
+		PADCTRL(0, gpio_06_pad_ctrl, 0);
+		PADCTRL(0, gpio_07_pad_ctrl, 0);
+		PADCTRL(0, gpio_08_pad_ctrl, 0);
+		PADCTRL(1, gpio_09_pad_ctrl, 0);
+		PADCTRL(1, gpio_10_pad_ctrl, 0);
+		PADCTRL(1, gpio_11_pad_ctrl, 0);
+		PADCTRL(1, gpio_12_pad_ctrl, 0);
+		PADCTRL(1, gpio_13_pad_ctrl, 0);
+		PADCTRL(1, gpio_14_pad_ctrl, 0);
+		PADCTRL(7, gpio_110_pad_ctrl, 0);
+		PADCTRL(8, gpio_123_pad_ctrl, 0);
+		PADCTRL(8, gpio_124_pad_ctrl, 0);
+
+		genet_pdata[1].phy_type = BRCM_PHY_TYPE_EXT_RVMII;
+		genet_pdata[1].phy_id = BRCM_PHY_ID_NONE;
+		genet_pdata[1].phy_speed = 100;
+
+		/* SD card mux + pullups */
+		PINMUX(14, gpio_112, 3);
+		PINMUX(14, gpio_113, 3);
+		PINMUX(14, gpio_114, 3);
+		PINMUX(14, gpio_115, 3);
+		PINMUX(14, gpio_116, 3);
+		PINMUX(14, gpio_117, 3);
+		PINMUX(14, gpio_118, 3);
+		PINMUX(15, gpio_119, 3);
+		PINMUX(15, gpio_120, 3);
+		PINMUX(15, gpio_121, 3);
+		PINMUX(15, gpio_122, 3);
+
+		PADCTRL(7, gpio_112_pad_ctrl, 2);
+		PADCTRL(7, gpio_113_pad_ctrl, 2);
+		PADCTRL(7, gpio_114_pad_ctrl, 2);
+		PADCTRL(7, gpio_115_pad_ctrl, 2);
+		PADCTRL(7, gpio_116_pad_ctrl, 2);
+		PADCTRL(7, gpio_117_pad_ctrl, 2);
+		PADCTRL(8, gpio_118_pad_ctrl, 2);
+		PADCTRL(8, gpio_119_pad_ctrl, 2);
+		PADCTRL(8, gpio_120_pad_ctrl, 2);
+		PADCTRL(8, gpio_121_pad_ctrl, 2);
+		PADCTRL(8, gpio_122_pad_ctrl, 2);
+	}
+
+	PINMUX(11, gpio_89, 1);		/* UARTB TX */
+	PINMUX(11, gpio_90, 1);		/* UARTB RX */
+
+	AON_PINMUX(1, aon_gpio_07, 4);	/* UARTC RX */
+	AON_PINMUX(1, aon_gpio_09, 4);	/* UARTC TX */
+
+	AON_PINMUX(0, aon_gpio_01, 1);	/* ENET link */
+	PINMUX(13, gpio_105, 1);	/* ENET activity */
+
+	/* Bootloader indicates disable of SDIO_1 in SCRATCH reg */
+	if ((BDEV_RD(SDIO_CFG_REG(1, SCRATCH)) & 0x01) == 0)
+		/* Set SDIO1 to eMMC */
+		BDEV_SET(BCHP_HIF_TOP_CTRL_EMMC_PIN_CTRL, 0x00000001);
+
+#endif /* chip type */
+#if defined(BCHP_SDIO_1_BOOT_REG_START)
+	BDEV_UNSET(BCHP_SDIO_1_BOOT_REG_START, 1);
+#endif
+#endif /* !defined(CONFIG_BRCM_IKOS) */
+}
+
+/***********************************************************************
+ * FLASH configuration
+ ***********************************************************************/
+
+#if defined(CONFIG_BRCM_FIXED_MTD_PARTITIONS)
+
+static struct mtd_partition fixed_partition_map[] = {
+	{
+		.name = "entire_device",
+		.size = MTDPART_SIZ_FULL,
+		.offset = 0x00000000,
+    #if defined(CONFIG_DREAMBOX)
+		.mask_flags = MTD_WRITEABLE,
+	}, {
+		.name = "bootloader",
+		.size = 0x00100000,
+		.offset = 0x00000000,
+		.mask_flags = MTD_WRITEABLE,
+	}, {
+		.name = "recovery",
+		.size = MTDPART_SIZ_FULL,
+		.offset = 0x00100000,
+    #endif
+	},
+};
+
+/*
+ * Use the partition map defined at compile time
+ */
+int __init board_get_partition_map(struct mtd_partition **p)
+{
+	*p = fixed_partition_map;
+	return ARRAY_SIZE(fixed_partition_map);
+}
+
+#else /* defined(CONFIG_BRCM_FIXED_MTD_PARTITIONS) */
+
+/*
+ * Construct the partition map for the primary flash device, based on
+ * CFE environment variables that were read from prom.c
+ *
+ * Note that this does NOT have all of the partitions that CFE recognizes
+ * (e.g. macadr, nvram).  It only has the rootfs, entire_device, and
+ * optionally the kernel image partition.
+ */
+int __init board_get_partition_map(struct mtd_partition **p)
+{
+	struct mtd_partition *ret;
+	int nr_parts;
+
+	if (brcm_mtd_rootfs_len == 0)
+		return -ENODEV;
+
+	nr_parts = 2;
+	if (brcm_mtd_kernel_len != 0)
+		nr_parts++;
+
+	ret = kzalloc(nr_parts * sizeof(struct mtd_partition), GFP_KERNEL);
+	if (!ret)
+		return -ENOMEM;
+
+	ret[0].offset = brcm_mtd_rootfs_start;
+	ret[0].size = brcm_mtd_rootfs_len;
+	ret[0].name = "rootfs";
+
+	ret[1].offset = 0;
+	ret[1].size = MTDPART_SIZ_FULL;
+	ret[1].name = "entire_device";
+
+	if (brcm_mtd_kernel_len != 0) {
+		ret[2].offset = brcm_mtd_kernel_start;
+		ret[2].size = brcm_mtd_kernel_len;
+		ret[2].name = "kernel";
+	}
+
+	*p = ret;
+	return nr_parts;
+}
+#endif /* defined(CONFIG_BRCM_FIXED_MTD_PARTITIONS) */
+
+void brcm_get_ocap_info(struct brcm_ocap_info *info)
+{
+	info->ocap_part_start = brcm_mtd_ocap_start;
+	info->ocap_part_len = brcm_mtd_ocap_len;
+	info->docsis_platform = brcm_docsis_platform;
+}
+EXPORT_SYMBOL(brcm_get_ocap_info);
diff --git a/drivers/brcmstb/m2m.c b/drivers/brcmstb/m2m.c
new file mode 100644
index 0000000..61ce3bb
--- /dev/null
+++ b/drivers/brcmstb/m2m.c
@@ -0,0 +1,585 @@
+/*
+ * Copyright (C) 2011 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#ifdef BCHP_MEM_DMA_0_CTRL
+
+struct brcm_mem_dma_descr {
+	u32     read_addr;
+	u32     write_addr;
+	u32     word[6];
+};
+
+#define DESCR_WORD2     0
+#define DESCR_WORD3     1
+#define DESCR_WORD4     2
+
+#define BRCM_MEM_DMA_TIMEOUT	(0)	/* no timeout */
+
+#define BRCM_MEM_DMA_DEBUG	(0)
+
+static int brcm_mem_dma_prepare_transfer(struct brcm_mem_transfer *xfer);
+static int brcm_mem_dma_complete_transfer(struct brcm_mem_transfer *xfer);
+static void brcm_mem_dma_start_transfer(void);
+
+#if BRCM_MEM_DMA_DEBUG
+#define DBG			printk
+static void brcm_mem_dma_dump_regs(const char *title)
+{
+	printk(KERN_DEBUG "=== MEM DMA registers ===\n");
+	printk(KERN_DEBUG
+	       "FIRST_DESC = 0x%08x CTRL       = 0x%08x WAKE_CTRL  = 0x%08x\n",
+	       (unsigned int)BDEV_RD(BCHP_MEM_DMA_0_FIRST_DESC),
+	       (unsigned int)BDEV_RD(BCHP_MEM_DMA_0_CTRL),
+	       (unsigned int)BDEV_RD(BCHP_MEM_DMA_0_WAKE_CTRL));
+	printk(KERN_DEBUG
+	       "STATUS     = 0x%08x CUR_DESC   = 0x%08x CUR_BYTE   = 0x%08x\n",
+	       (unsigned int)BDEV_RD(BCHP_MEM_DMA_0_STATUS),
+	       (unsigned int)BDEV_RD(BCHP_MEM_DMA_0_CUR_DESC),
+	       (unsigned int)BDEV_RD(BCHP_MEM_DMA_0_CUR_BYTE));
+}
+
+static void brcm_mem_dma_dump_descr(struct brcm_mem_dma_descr *d, int num)
+{
+	int index = 0, last = 0;
+	printk(KERN_DEBUG "=== MEM DMA descriptors [%p] ===\n", d);
+	do {
+		last = d->word[DESCR_WORD2] &
+			BCHP_MEM_DMA_DESC_WORD2_LAST_MASK;
+		printk(KERN_DEBUG "[%02d]: s  = 0x%08x d  = 0x%08x "
+			"w2 = 0x%08x w3 = 0x%08x w4 = 0x%08x\n",
+			index++, d->read_addr, d->write_addr,
+			d->word[0], d->word[1], d->word[2]);
+		d++;
+		if (!--num)
+			break;
+	} while (!last);
+}
+#else
+#define DBG(...)		do { } while (0)
+static inline void brcm_mem_dma_dump_regs(const char *title) {}
+static inline void brcm_mem_dma_dump_descr(struct brcm_mem_dma_descr *d,
+	int num) {}
+#endif
+
+/***********************************************************************
+ * Low-level M2M utilities
+ ***********************************************************************/
+static inline void brcm_mem_dma_set_raddr(struct brcm_mem_dma_descr *descr,
+	u32 addr)
+{
+	descr->read_addr = addr;
+}
+
+static inline void brcm_mem_dma_set_waddr(struct brcm_mem_dma_descr *descr,
+	u32 addr)
+{
+	descr->write_addr = addr;
+}
+
+/***********************************************************************
+ * Enable/disable completion interrupt for descriptor
+ ***********************************************************************/
+static inline void brcm_mem_dma_interrupt_enable(
+	struct brcm_mem_dma_descr *descr, int enable)
+{
+	if (enable)
+		descr->word[DESCR_WORD2] |=
+			BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK;
+	else
+		descr->word[DESCR_WORD2] &=
+			~BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK;
+}
+
+/***********************************************************************
+ * Set transfer size for descriptor
+ ***********************************************************************/
+static inline void brcm_mem_dma_set_xfer_size(struct brcm_mem_dma_descr *descr,
+	u32 len)
+{
+	len &= BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK;
+	descr->word[DESCR_WORD2] &=
+		~BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK;
+	descr->word[DESCR_WORD2] |= len;
+}
+
+/***********************************************************************
+ * Link to the next descriptor
+ * next - virtual address of the descriptor to link with
+ ***********************************************************************/
+static inline void brcm_mem_dma_link_next(struct brcm_mem_dma_descr *descr,
+	struct brcm_mem_dma_descr *next)
+{
+	u32 pa_next = 0;
+
+	if (next) {
+		pa_next = virt_to_phys(next) &
+			BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK;
+		descr->word[DESCR_WORD2] &= ~BCHP_MEM_DMA_DESC_WORD2_LAST_MASK;
+	} else
+		descr->word[DESCR_WORD2] |= BCHP_MEM_DMA_DESC_WORD2_LAST_MASK;
+
+	descr->word[DESCR_WORD3] &=
+		~BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK;
+	descr->word[DESCR_WORD3] |= pa_next;
+
+}
+
+/***********************************************************************
+ * Configure SCRAM
+ * TODO: encoder/decoder init bit ???
+ ***********************************************************************/
+static inline void brcm_mem_dma_set_scram(struct brcm_mem_dma_descr *descr,
+	int enable, int start, int end, int mode, u8 slot, int init)
+{
+	u32 word4 = 0;
+	word4 |= enable ? BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK : 0;
+	word4 |= start  ? BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK : 0;
+	word4 |= end    ? BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK : 0;
+	word4 |= (mode << BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT) &
+		BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_MASK;
+	word4 |= (slot * 6) & BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_MASK;
+
+	if (mode && init)
+		word4 |= BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_MASK;
+
+	descr->word[DESCR_WORD4] = word4;
+}
+
+/***********************************************************************
+ * Poll for transfer completion
+ ***********************************************************************/
+static int brcm_mem_dma_wait_for_ready(int timeout)
+{
+	while (BDEV_RD_F(MEM_DMA_0_STATUS, DMA_STATUS) == 1) {
+		if (timeout > 0)
+			if (!--timeout)
+				return -1;
+		mdelay(1);
+	}
+	return 0;
+}
+
+static int brcm_mem_dma_num_descriptors(struct brcm_mem_transfer *xfer)
+{
+	int xfer_cnt = 0;
+
+	do {
+		xfer_cnt++;
+	} while ((xfer = xfer->next));
+
+	return xfer_cnt;
+}
+
+/***********************************************************************
+ * Generate descriptor according to transfer request
+ * Returns 0 on success, -1 on incorrect request parameters
+ ***********************************************************************/
+static int brcm_mem_dma_gen_descriptor(struct brcm_mem_transfer *xfer,
+	struct brcm_mem_dma_descr *d, int index, int total)
+{
+	int last = index == total - 1;
+
+	/* sanity checks */
+	if (xfer->len > 0x1000000) {
+		printk(KERN_ERR "MEM DMA "
+			"does not support transfers bigger than 16 MByte\n");
+		return -1;
+	}
+	if ((xfer->pa_dst > xfer->pa_src) &&
+	    (xfer->pa_dst < (xfer->pa_src + xfer->len))) {
+		printk(KERN_ERR "MEM DMA "
+		"does not support overlapping read-write regions\n");
+		return -1;
+	}
+
+	/* set up mem-dma descriptor */
+	brcm_mem_dma_set_raddr(d, xfer->pa_src);
+	brcm_mem_dma_set_waddr(d, xfer->pa_dst);
+	brcm_mem_dma_set_xfer_size(d, xfer->len);
+	brcm_mem_dma_set_scram(d, 1, index == 0, last,
+		xfer->mode, xfer->key, index == 0);
+	brcm_mem_dma_link_next(d, last ? NULL : d + 1);
+
+	return 0;
+}
+
+/***********************************************************************
+ * If caller remapped the buffers, it set pa_src and pa_dst fields
+ * of transfer request. If these fields are not set, we need to remap
+ * them here.
+ * To properly unmap the buffers after the transfer, set bit flags
+ * in the transfer if we are doing remapping. Caller should never touch
+ * these flags.
+ ***********************************************************************/
+static int brcm_mem_dma_map_buffers(struct brcm_mem_transfer *xfer)
+{
+	if (!xfer->len)
+		return -1;
+
+	if (!xfer->pa_src && !xfer->pa_dst && (xfer->src == xfer->dst)) {
+		xfer->pa_dst = xfer->pa_src =
+			dma_map_single(NULL, xfer->src, xfer->len,
+				DMA_BIDIRECTIONAL);
+		if (dma_mapping_error(NULL, xfer->pa_dst))
+			return -1;
+		xfer->src_dst_remapped = 1;
+	}
+
+	if (!xfer->pa_src) {
+		xfer->pa_src = dma_map_single(NULL, xfer->src, xfer->len,
+			DMA_TO_DEVICE);
+		if (dma_mapping_error(NULL, xfer->pa_src))
+			return -1;
+		xfer->src_remapped = 1;
+	}
+
+	if (!xfer->pa_dst) {
+		xfer->pa_dst = dma_map_single(NULL, xfer->dst, xfer->len,
+			DMA_FROM_DEVICE);
+		if (dma_mapping_error(NULL, xfer->pa_dst))
+			return -1;
+		xfer->dst_remapped = 1;
+	}
+
+	return 0;
+}
+
+/***********************************************************************
+ * Unmap the buffers if we mapped them before
+ ***********************************************************************/
+static void brcm_mem_dma_unmap_buffers(struct brcm_mem_transfer *xfer)
+{
+	if (xfer->src_dst_remapped) {
+		dma_unmap_single(NULL, xfer->pa_src, xfer->len,
+				DMA_BIDIRECTIONAL);
+		return;
+	}
+
+	if (xfer->src_remapped) {
+		dma_unmap_single(NULL, xfer->pa_src, xfer->len,
+			DMA_TO_DEVICE);
+	}
+	if (xfer->dst_remapped) {
+		dma_unmap_single(NULL, xfer->pa_dst, xfer->len,
+			DMA_FROM_DEVICE);
+	}
+}
+
+/***********************************************************************
+ * Map the descriptors and write the first descriptor address to the
+ * M2M register. Do not initiate transfer yet.
+ ***********************************************************************/
+static dma_addr_t brcm_mem_dma_prepare_descriptors(
+	struct brcm_mem_dma_descr *d, int size)
+{
+	dma_addr_t pa_d;
+	pa_d = dma_map_single(NULL, d, size, DMA_TO_DEVICE);
+	brcm_mem_dma_wait_for_ready(0);
+	BDEV_WR_RB(BCHP_MEM_DMA_0_FIRST_DESC, pa_d);
+
+	return pa_d;
+}
+
+/***********************************************************************
+ * Unmap the descriptor after completion
+ ***********************************************************************/
+static void brcm_mem_dma_free_descriptors(dma_addr_t pa, int size)
+{
+	brcm_mem_dma_wait_for_ready(0);
+	dma_unmap_single(NULL, pa, size, DMA_TO_DEVICE);
+}
+
+static struct brcm_mem_dma_descr *cur_descr;
+static int cur_total_size;
+static dma_addr_t cur_pa_d;
+
+/***********************************************************************
+ * _brcm_mem_dma_start_transfer
+ * Initiate M2M transfer. If sync is set, wait for completion with timeout.
+ ***********************************************************************/
+static void _brcm_mem_dma_start_transfer(int on, int sync)
+{
+	/* clear RUN bit and wait for IDLE */
+	BDEV_WR_F_RB(MEM_DMA_0_CTRL, RUN, 0);
+	brcm_mem_dma_wait_for_ready(BRCM_MEM_DMA_TIMEOUT);
+
+	if (on) {
+		BDEV_WR_F_RB(MEM_DMA_0_CTRL, RUN, 1);
+		if (sync)
+			brcm_mem_dma_wait_for_ready(BRCM_MEM_DMA_TIMEOUT);
+	}
+}
+
+/***********************************************************************
+ * brcm_mem_dma_start_transfer
+ * Initiate M2M transfer
+ ***********************************************************************/
+static void brcm_mem_dma_start_transfer(void)
+{
+	DBG("%s:%d\n", __func__, __LINE__);
+	_brcm_mem_dma_start_transfer(1, 1);
+}
+
+/***********************************************************************
+ * brcm_mem_dma_prepare_transfer
+ * Generates mem dma descriptors, flushes them to memory
+ * and sets up M2M registers, but _DOES NOT_ initiate the transfer.
+ * Use brcm_mem_dma_start_transfer() to start transfer/encoding
+ * This allows S3 standby code to be sure code does not attempt to change
+ * memory content after it has been encoded
+ ***********************************************************************/
+static int brcm_mem_dma_prepare_transfer(struct brcm_mem_transfer *xfer)
+{
+	int xfer_cnt = brcm_mem_dma_num_descriptors(xfer);
+	int total_size = xfer_cnt * sizeof(struct brcm_mem_dma_descr);
+	int index = 0;
+	struct brcm_mem_transfer *save_xfer = xfer;
+	struct brcm_mem_dma_descr *d =
+		kzalloc(total_size, GFP_ATOMIC), *cur_d;
+
+	DBG("%s:%d\n", __func__, __LINE__);
+
+	WARN_ON(cur_descr);
+
+	if (unlikely(!d))
+		return -1;
+
+	cur_descr = cur_d = d;
+
+	do {
+		if (brcm_mem_dma_map_buffers(xfer)) {
+			printk(KERN_ERR "%s: cannot map buffers", __func__);
+			goto _error;
+		}
+
+		if (brcm_mem_dma_gen_descriptor(xfer, cur_d,
+		    index++, xfer_cnt)) {
+			printk(KERN_ERR "%s: cannot generate descr", __func__);
+			goto _error;
+		}
+
+		xfer = xfer->next;
+		cur_d++;
+	} while (xfer);
+
+	brcm_mem_dma_dump_descr(d, xfer_cnt);
+	/* flush the descriptors */
+	cur_pa_d = brcm_mem_dma_prepare_descriptors(d, total_size);
+	cur_total_size = total_size;
+
+	return 0;
+
+_error:
+	brcm_mem_dma_complete_transfer(save_xfer);
+	return -1;
+}
+
+/***********************************************************************
+ * brcm_mem_dma_complete_transfer
+ * Must be called after M2M transfer was complete
+ * Unmaps everything that was mapped in brcm_mem_dma_prepare_transfer,
+ * frees up all memory
+ ***********************************************************************/
+static int brcm_mem_dma_complete_transfer(struct brcm_mem_transfer *xfer)
+{
+	WARN_ON(cur_descr == NULL);
+	WARN_ON(!cur_pa_d);
+	WARN_ON(!cur_total_size);
+
+	DBG("%s:%d\n", __func__, __LINE__);
+
+	/* clear RUN bit and wait for IDLE */
+	_brcm_mem_dma_start_transfer(0, 1);
+
+	brcm_mem_dma_free_descriptors(cur_pa_d, cur_total_size);
+
+	do {
+		brcm_mem_dma_unmap_buffers(xfer);
+		xfer = xfer->next;
+	} while (xfer);
+
+	kfree(cur_descr);
+
+	cur_descr = NULL;
+	cur_total_size = 0;
+	cur_pa_d = 0;
+
+	return 0;
+}
+
+/***********************************************************************
+ * brcm_mem_dma_simple_transfer
+ * Initiates a single M2M tranfser according to transfer request
+ ***********************************************************************/
+int brcm_mem_dma_simple_transfer(struct brcm_mem_transfer *xfer)
+{
+	int retval = 0;
+	struct brcm_mem_dma_descr *d =
+		kzalloc(sizeof(struct brcm_mem_dma_descr), GFP_ATOMIC);
+
+	DBG("%s:%d\n", __func__, __LINE__);
+
+	WARN_ON(brcm_mem_dma_num_descriptors(xfer) != 1);
+
+	if (d) {
+		u32 pa_d;
+
+		/* remap the buffers unless the caller has done that */
+		if (brcm_mem_dma_map_buffers(xfer)) {
+			retval = -1;
+			goto _error;
+		}
+		/* set up mem-dma descriptor */
+		if (!brcm_mem_dma_gen_descriptor(xfer, d, 0, 1)) {
+
+			brcm_mem_dma_dump_descr(d, 1);
+			/* flush the descriptor */
+			pa_d = brcm_mem_dma_prepare_descriptors(d,
+				sizeof(struct brcm_mem_dma_descr));
+			_brcm_mem_dma_start_transfer(1, 1);
+			brcm_mem_dma_dump_regs(__func__);
+			_brcm_mem_dma_start_transfer(0, 0);
+			brcm_mem_dma_free_descriptors(pa_d,
+				sizeof(struct brcm_mem_dma_descr));
+		}
+
+		brcm_mem_dma_unmap_buffers(xfer);
+_error:
+		kfree(d);
+		return retval;
+	}
+
+	return -1;
+}
+
+/***********************************************************************
+ * brcm_mem_dma_transfer_sg
+ * Scatter-gather version of M2M tranfser
+ ***********************************************************************/
+int brcm_mem_dma_transfer_sg(struct brcm_mem_transfer *xfer)
+{
+	printk(KERN_WARNING "%s: NOT IMPLEMENTED YET\n", __func__);
+	return -1;
+}
+
+/***********************************************************************
+ * brcm_mem_dma_transfer
+ * Initiates a M2M tranfser according to transfer request. Chained transfer
+ * will generate several descriptors.
+ ***********************************************************************/
+int brcm_mem_dma_transfer(struct brcm_mem_transfer *xfer)
+{
+	struct brcm_mem_dma_descr *d;
+	int index = 0, retval = 0;
+	struct brcm_mem_dma_descr *cur_d;
+	int xfer_cnt = brcm_mem_dma_num_descriptors(xfer), total_size;
+	struct brcm_mem_transfer *xfer_save = xfer;
+	dma_addr_t pa_d;
+
+	DBG("%s:%d\n", __func__, __LINE__);
+
+	total_size = xfer_cnt * sizeof(struct brcm_mem_dma_descr);
+
+	d = kzalloc(total_size, GFP_ATOMIC);
+	if (!d)
+		return -1;
+
+	cur_d = d;
+	do {
+		/* remap the buffers unless the caller has done that */
+		if (brcm_mem_dma_map_buffers(xfer)) {
+			retval = -1;
+			goto _done;
+		}
+
+		if (brcm_mem_dma_gen_descriptor(xfer, cur_d,
+		    index++, xfer_cnt)) {
+			retval = -1;
+			goto _done;
+		}
+
+		xfer = xfer->next;
+		cur_d++;
+	} while (xfer);
+
+	brcm_mem_dma_dump_descr(d, xfer_cnt);
+
+	/* flush the descriptors */
+	pa_d = brcm_mem_dma_prepare_descriptors(d, total_size);
+	brcm_mem_dma_dump_regs(__func__);
+	_brcm_mem_dma_start_transfer(1, 1);
+	_brcm_mem_dma_start_transfer(0, 0);
+
+	brcm_mem_dma_free_descriptors(pa_d, total_size);
+
+_done:
+	xfer = xfer_save;
+	do {
+		brcm_mem_dma_unmap_buffers(xfer);
+		xfer = xfer->next;
+	} while (xfer);
+
+	kfree(d);
+
+	return retval;
+}
+#else
+static int brcm_mem_dma_prepare_transfer(struct brcm_mem_transfer *xfer)
+{
+	return -1;
+}
+static int brcm_mem_dma_complete_transfer(struct brcm_mem_transfer *xfer)
+{
+	return -1;
+}
+static void brcm_mem_dma_start_transfer(void) {}
+
+int brcm_mem_dma_simple_transfer(struct brcm_mem_transfer *xfer)
+{
+	return -1;
+}
+
+int brcm_mem_dma_transfer(struct brcm_mem_transfer *xfer)
+{
+	return -1;
+}
+
+#endif /* BCHP_MEM_DMA_0_CTRL */
+
+static struct brcm_dram_encoder_ops m2m_ops = {
+	.prepare = brcm_mem_dma_prepare_transfer,
+	.start = brcm_mem_dma_start_transfer,
+	.complete = brcm_mem_dma_complete_transfer,
+};
+
+static int brcm_mem_dma_init(void)
+{
+	/* TODO: request interrupt */
+	/* register encoder with power management subsystem */
+	brcm_pm_set_dram_encoder(&m2m_ops);
+	return 0;
+}
+late_initcall(brcm_mem_dma_init);
diff --git a/drivers/brcmstb/memc1.c b/drivers/brcmstb/memc1.c
new file mode 100644
index 0000000..034b7bf
--- /dev/null
+++ b/drivers/brcmstb/memc1.c
@@ -0,0 +1,424 @@
+/*
+ * Copyright (C) 2011 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+#include <stdarg.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+#include <linux/brcmstb/brcmstb.h>
+
+#if 1
+#define DBG	printk
+#else
+#define DBG(...)		do { } while (0)
+#endif
+
+#if defined(BCHP_MEMC_DDR_1_SSPD_CMD)
+
+#define MAX_CLIENT_INFO_NUM		NUM_MEMC_CLIENTS
+#define MAX_DDR_PARAMS_NUM		16
+#define MAX_DDR_APHY_PARAMS_NUM		16
+#define MAX_ARB_PARAMS_NUM		2
+
+#define MEMC_STATE_UNKNOWN		0
+#define MEMC_STATE_ON			1
+#define MEMC_STATE_OFF			2
+
+static int  __brcm_pm_memc1_initialized(void);
+static void __brcm_pm_memc1_clock_start(void);
+static void __brcm_pm_memc1_clock_stop(void);
+static int  __brcm_pm_memc1_clock_running(void);
+static void brcm_pm_memc1_enable_idle_pad(void);
+static void brcm_pm_memc1_disable_idle_pad(void);
+static void brcm_pm_memc1_enable_plls(void);
+static void brcm_pm_memc1_disable_plls(void);
+
+struct memc_config {
+	u32	client_info[MAX_CLIENT_INFO_NUM];
+	u32	ddr23_aphy_params[MAX_DDR_APHY_PARAMS_NUM];
+	u32	ddr_params[MAX_DDR_PARAMS_NUM];
+	u32	arb_params[MAX_ARB_PARAMS_NUM];
+
+	u32	vcdl[4];
+	int	shmoo_value[8];
+
+	int	shmoo_valid;
+	int	valid;
+	/* if CFE did not initialize non-primary MEMC we cannot touch it
+	  because we do not have calibration capabilities.
+	  _initalized_ and _clock_active_ are initially set to
+	  0: unknown
+	  The first time any method is called it will set _initialized_ to
+	  one of the following values:
+	  1: on
+	  2: off - unusable
+	 */
+	int	initialized;
+	int	clock_active;
+};
+
+static struct memc_config __maybe_unused memc1_config;
+
+static void brcm_pm_memc1_sspd_control(int enable)
+{
+	if (enable) {
+		BDEV_WR_F_RB(MEMC_DDR_1_SSPD_CMD, SSPD, 1);
+		while (!BDEV_RD_F(MEMC_DDR_1_POWER_DOWN_STATUS, SSPD))
+			udelay(1);
+	} else {
+		BDEV_WR_F_RB(MEMC_DDR_1_SSPD_CMD, SSPD, 0);
+		while (BDEV_RD_F(MEMC_DDR_1_POWER_DOWN_STATUS, SSPD))
+			udelay(1);
+	}
+}
+
+static void brcm_pm_memc1_suspend_s3(void)
+{
+	/* clear standby field */
+	BDEV_UNSET(BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL, 0x0f);
+	/* inhibit DDR_RSTb pulse, Arm for standby */
+	BDEV_SET(BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL, BIT(5) | 0x05);
+}
+
+static void brcm_pm_memc1_ddr_params(int restore)
+{
+	int ii = 0;
+
+	if (restore) {
+		/* program ddr iobuf registers */
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_MODE_2,
+			memc1_config.ddr_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_MODE_3,
+			memc1_config.ddr_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_5,
+			memc1_config.ddr_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_MODE_0,
+			memc1_config.ddr_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_MODE_1,
+			memc1_config.ddr_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_0,
+			memc1_config.ddr_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_1,
+			memc1_config.ddr_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_2,
+			memc1_config.ddr_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_3,
+			memc1_config.ddr_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_4,
+			memc1_config.ddr_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_CNTRLR_CONFIG,
+			memc1_config.ddr_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL,
+			memc1_config.ddr_params[ii++]);
+	} else {
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_MODE_2);
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_MODE_3);
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_5);
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_MODE_0);
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_MODE_1);
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_0);
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_1);
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_2);
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_3);
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_4);
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_CNTRLR_CONFIG);
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL);
+	}
+	BUG_ON(ii > MAX_DDR_PARAMS_NUM);
+}
+
+static void brcm_pm_memc1_arb_params(int restore)
+{
+	int ii = 0;
+
+	if (restore) {
+		BDEV_WR_RB(BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD,
+			memc1_config.arb_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE,
+			memc1_config.arb_params[ii++]);
+	} else {
+		memc1_config.arb_params[ii++] =
+			BDEV_RD(BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD);
+		memc1_config.arb_params[ii++] =
+			BDEV_RD(BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE);
+	}
+
+	BUG_ON(ii > MAX_ARB_PARAMS_NUM);
+}
+
+static int brcm_pm_memc1_clock_running(void)
+{
+	if (memc1_config.clock_active == MEMC_STATE_UNKNOWN) {
+		/* do this only once */
+		memc1_config.clock_active = __brcm_pm_memc1_clock_running() ?
+			MEMC_STATE_ON : MEMC_STATE_OFF;
+	}
+	return memc1_config.clock_active == MEMC_STATE_ON;
+}
+
+static void brcm_pm_memc1_clock_start(void)
+{
+	if (!brcm_pm_memc1_clock_running())
+		__brcm_pm_memc1_clock_start();
+	memc1_config.clock_active = MEMC_STATE_ON;
+}
+
+static void brcm_pm_memc1_clock_stop(void)
+{
+	if (brcm_pm_memc1_clock_running())
+		__brcm_pm_memc1_clock_stop();
+	memc1_config.clock_active = MEMC_STATE_OFF;
+}
+
+static int brcm_pm_memc1_initialized(void)
+{
+	if (memc1_config.initialized == MEMC_STATE_UNKNOWN) {
+		brcm_pm_memc1_clock_start();
+		/* do this only once */
+		memc1_config.initialized = __brcm_pm_memc1_initialized() ?
+			MEMC_STATE_ON : MEMC_STATE_OFF;
+	}
+	return memc1_config.initialized == MEMC_STATE_ON;
+}
+
+#define CHECK_MEMC1_INIT() \
+	if (!brcm_pm_memc1_initialized()) { \
+		printk(KERN_ERR "%s: not initialized\n", __func__); \
+		return -1; \
+	}
+
+int brcm_pm_memc1_suspend(int is_s3)
+{
+	CHECK_MEMC1_INIT();
+
+	/*
+	 * Force all dirty cache lines to be written
+	 * If a dirty cache line for memc1 were to be written later,
+	 * it might hang the cache unit and/or cpu.
+	 */
+	_dma_cache_wback_inv(0, ~0);
+	if (is_s3)
+		brcm_pm_memc1_suspend_s3();
+	else
+		brcm_pm_memc1_sspd_control(1);
+
+	return 0;
+}
+
+int brcm_pm_memc1_resume(int is_s3)
+{
+	CHECK_MEMC1_INIT();
+
+	if (is_s3 == 0)
+		brcm_pm_memc1_sspd_control(0);
+
+	return 0;
+}
+
+
+int brcm_pm_memc1_powerdown(void)
+{
+	CHECK_MEMC1_INIT();
+
+	DBG(KERN_DEBUG "%s\n", __func__);
+
+	brcm_pm_save_restore_rts(BCHP_MEMC_ARB_1_REG_START,
+		memc1_config.client_info, 0);
+	brcm_pm_memc1_ddr_params(0);
+	brcm_pm_memc1_arb_params(0);
+	brcm_pm_memc1_enable_idle_pad();
+
+	memc1_config.shmoo_valid = 1;
+	memc1_config.valid = 1;
+
+	/*
+	 * Force all dirty cache lines to be written
+	 * If a dirty cache line for memc1 were to be written later,
+	 * it might hang the cache unit and/or cpu.
+	 */
+	_dma_cache_wback_inv(0, ~0);
+	brcm_pm_memc1_sspd_control(1);
+
+	brcm_pm_memc1_disable_plls();
+
+	DBG(KERN_DEBUG "%s reset\n", __func__);
+	BDEV_WR_F_RB(MEMC_MISC_1_SOFT_RESET, MEMC_DRAM_INIT, 1);
+	BDEV_WR_F_RB(MEMC_MISC_1_SOFT_RESET, MEMC_CORE, 1);
+	BDEV_WR_F_RB(MEMC_DDR_1_DRAM_INIT_CNTRL, DDR3_INIT_MODE, 1);
+	mdelay(1);
+
+	/* Stop the clocks */
+	brcm_pm_memc1_clock_stop();
+	memc1_config.valid = 1;
+
+	return 0;
+}
+
+int brcm_pm_memc1_powerup(void)
+{
+	CHECK_MEMC1_INIT();
+
+	if (!memc1_config.valid || !memc1_config.shmoo_valid) {
+		printk(KERN_ERR "%s: no valid saved configuration %d %d\n",
+		       __func__, memc1_config.valid, memc1_config.shmoo_valid);
+		return -1;
+	}
+
+	DBG(KERN_DEBUG "%s\n", __func__);
+
+	/* Restart the clocks */
+	brcm_pm_memc1_clock_start();
+	brcm_pm_memc1_enable_plls();
+	brcm_pm_memc1_disable_idle_pad();
+
+	brcm_pm_memc1_sspd_control(0);
+	BDEV_WR_F_RB(MEMC_MISC_1_SOFT_RESET, MEMC_DRAM_INIT, 0);
+	BDEV_WR_F_RB(MEMC_MISC_1_SOFT_RESET, MEMC_CORE, 0);
+	mdelay(1);
+	printk(KERN_DEBUG "memc1: powered up\n");
+
+	brcm_pm_memc1_ddr_params(1);
+	brcm_pm_memc1_arb_params(1);
+	brcm_pm_save_restore_rts(BCHP_MEMC_ARB_1_REG_START,
+		memc1_config.client_info, 1);
+	brcm_pm_memc1_sspd_control(0);
+
+	return 0;
+}
+
+#if defined(CONFIG_BCM7425) || defined(CONFIG_BCM7435)
+static int __brcm_pm_memc1_initialized(void)
+{
+	return BDEV_RD_F(MEMC_DDR_1_DRAM_INIT_STATUS, INIT_DONE);
+}
+
+static void __brcm_pm_memc1_clock_start(void)
+{
+	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE,
+		DDR1_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE,
+		DDR1_108_CLOCK_ENABLE, 1);
+}
+
+static void __brcm_pm_memc1_clock_stop(void)
+{
+	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE,
+		DDR1_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE,
+		DDR1_108_CLOCK_ENABLE, 0);
+}
+
+static int __brcm_pm_memc1_clock_running(void)
+{
+	return BDEV_RD_F(CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE,
+			DDR1_SCB_CLOCK_ENABLE) &&
+		BDEV_RD_F(CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE,
+			DDR1_108_CLOCK_ENABLE);
+}
+
+static void brcm_pm_memc1_enable_idle_pad(void)
+{
+	/* enable idle pad powerdown */
+	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL,
+		IDDQ_MODE_ON_SELFREF, 0);
+	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL,
+		PHY_IDLE_ENABLE, 1);
+	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL,
+		HIZ_ON_SELFREF, 1);
+	BDEV_WR_RB(BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL,
+		0x132);
+	BDEV_WR_RB(BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL,
+		BDEV_RD(BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL) |
+			0xFFFFF);
+	BDEV_WR_RB(BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL,
+		BDEV_RD(BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL) |
+			0xFFFFF);
+	DBG(KERN_DEBUG "%s\n", __func__);
+}
+
+static void brcm_pm_memc1_disable_idle_pad(void)
+{
+	/* disable idle pad powerdown */
+	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL,
+		IDDQ_MODE_ON_SELFREF, 0);
+	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL,
+		HIZ_ON_SELFREF, 0);
+	BDEV_WR_RB(BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL,
+		0);
+	BDEV_WR_RB(BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL,
+		BDEV_RD(BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL) |
+			0);
+	BDEV_WR_RB(BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL,
+		BDEV_RD(BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL) |
+			0);
+
+}
+
+static void brcm_pm_memc1_enable_plls(void)
+{
+	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel,
+		PWRDN, 0);
+	BDEV_WR_RB(BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG, 0);
+
+	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY,
+		DDR1_POWER_SWITCH_MEMORY, 2);
+	mdelay(1);
+	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY,
+		DDR1_POWER_SWITCH_MEMORY, 0);
+
+	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE,
+		DDR1_MEMORY_STANDBY_ENABLE, 0);
+#if defined(BCHP_CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT)
+	BDEV_WR_F_RB(CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT,
+		MEMSYS_PLL_PWRDN_POWER_MANAGEMENT, 0);
+#endif
+
+}
+static void brcm_pm_memc1_disable_plls(void)
+{
+	/* power down the PLLs */
+	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel,
+		PWRDN, 1);
+	BDEV_WR_RB(BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG, 3);
+
+	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY,
+		DDR1_POWER_SWITCH_MEMORY, 3);
+	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE,
+		DDR1_MEMORY_STANDBY_ENABLE, 1);
+
+#if defined(BCHP_CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT)
+	BDEV_WR_F_RB(CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT,
+		MEMSYS_PLL_PWRDN_POWER_MANAGEMENT, 1);
+#endif
+}
+
+
+
+#endif
+
+#endif
diff --git a/drivers/brcmstb/pci.c b/drivers/brcmstb/pci.c
new file mode 100644
index 0000000..afe6e99
--- /dev/null
+++ b/drivers/brcmstb/pci.c
@@ -0,0 +1,481 @@
+/*
+ * Copyright (C) 2009 - 2012 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#define pr_fmt(fmt)		"PCI: " fmt
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/compiler.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/printk.h>
+#include <linux/syscore_ops.h>
+#include <linux/brcmstb/brcmstb.h>
+
+/* NOTE: all PHYSICAL addresses */
+
+/* Use assigned bus numbers so "ops" can tell the controllers apart */
+#define BRCM_BUSNO_PCIE		0x00
+
+#define PCIE_OUTBOUND_WIN(win, start, len) do { \
+	BDEV_WR(BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN##win##_LO, \
+		(start) + MMIO_ENDIAN); \
+	BDEV_WR(BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN##win##_HI, 0); \
+	BDEV_WR(BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN##win##_BASE_LIMIT, \
+		(((start) >> 20) << 4) | \
+		 ((((start) + (len) - 1) >> 20) << 20)); \
+	} while (0)
+
+static int brcm_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+	int where, int size, u32 *data);
+static int brcm_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+	int where, int size, u32 data);
+
+static inline int get_busno_pcie(void)  { return BRCM_BUSNO_PCIE;  }
+
+static struct pci_ops brcmstb_pci_ops = {
+	.read = brcm_pci_read_config,
+	.write = brcm_pci_write_config,
+};
+
+/*
+ * Note: our PCIe core does not support IO BARs at all.  MEM only.
+ * The Linux PCI code insists on having IO resources and io_map_base for
+ * all PCI controllers, so those values are totally bogus.
+ */
+#define IO_ADDR_PCIE		0x400
+#define PCIE_IO_SIZE		0x400
+#define BOGUS_IO_MAP_BASE	1
+
+/* pci_controller resources */
+
+static struct resource pcie_mem_resource = {
+	.name			= "External PCIe MEM",
+	.start			= PCIE_MEM_START,
+	.end			= PCIE_MEM_START + PCIE_MEM_SIZE - 1,
+	.flags			= IORESOURCE_MEM,
+};
+
+static struct resource pcie_io_resource = {
+	.name			= "External PCIe IO (unavailable)",
+	.start			= IO_ADDR_PCIE,
+	.end			= IO_ADDR_PCIE + PCIE_IO_SIZE - 1,
+	.flags			= IORESOURCE_MEM,
+};
+
+static struct pci_controller brcmstb_pcie_controller = {
+	.pci_ops		= &brcmstb_pci_ops,
+	.io_resource		= &pcie_io_resource,
+	.mem_resource		= &pcie_mem_resource,
+	.get_busno		= &get_busno_pcie,
+	.io_map_base		= BOGUS_IO_MAP_BASE,
+};
+
+struct brcm_pci_bus {
+	struct pci_controller	*controller;
+	char			*name;
+	unsigned int		hw_busnum;
+	unsigned int		busnum_shift;
+	unsigned int		slot_shift;
+	unsigned int		func_shift;
+	int			memory_hole;
+	unsigned long		idx_reg;
+	unsigned long		data_reg;
+	struct clk		*clk;
+};
+
+static struct brcm_pci_bus brcm_buses[] = {
+	[BRCM_BUSNO_PCIE] = {
+		&brcmstb_pcie_controller, "PCIe",    1, 20, 15, 12, 0 },
+};
+
+
+/***********************************************************************
+ * PCIe Bridge setup
+ ***********************************************************************/
+
+#if defined(__BIG_ENDIAN)
+#define	DATA_ENDIAN		2	/* PCI->DDR inbound accesses */
+#define MMIO_ENDIAN		2	/* MIPS->PCI outbound accesses */
+#else
+#define	DATA_ENDIAN		0
+#define MMIO_ENDIAN		0
+#endif
+
+static struct wktmr_time pcie_reset_started;
+
+#define PCIE_LINK_UP() \
+	(((BDEV_RD(BCHP_PCIE_MISC_PCIE_STATUS) & 0x30) == 0x30) ? 1 : 0)
+
+void brcm_early_pcie_setup(void)
+{
+	/*
+	 * Called from bchip_early_setup() in order to start PCIe link
+	 * negotiation immediately at kernel boot time.  The RC is supposed
+	 * to give the endpoint device 100ms to settle down before
+	 * attempting configuration accesses.  So we let the link negotiation
+	 * happen in the background instead of busy-waiting.
+	 */
+
+	struct wktmr_time tmp;
+
+	/* reset the bridge and the endpoint device */
+	BDEV_WR_F_RB(HIF_RGR1_SW_INIT_1, PCIE_BRIDGE_SW_INIT, 1);
+	BDEV_WR_F_RB(HIF_RGR1_SW_INIT_1, PCIE_SW_PERST, 1);
+
+	/* delay 100us */
+	wktmr_read(&tmp);
+	while (wktmr_elapsed(&tmp) < (100 * WKTMR_1US))
+		;
+
+	/* take the bridge out of reset */
+	BDEV_WR_F_RB(HIF_RGR1_SW_INIT_1, PCIE_BRIDGE_SW_INIT, 0);
+
+	/* enable SCB_MAX_BURST_SIZE | CSR_READ_UR_MODE | SCB_ACCESS_EN */
+	BDEV_WR(BCHP_PCIE_MISC_MISC_CTRL, 0x00103000);
+
+	/* set up MIPS->PCIE memory windows (4x 128MB) */
+	PCIE_OUTBOUND_WIN(0, PCIE_MEM_START + 0x00000000, 0x08000000);
+	PCIE_OUTBOUND_WIN(1, PCIE_MEM_START + 0x08000000, 0x08000000);
+	PCIE_OUTBOUND_WIN(2, PCIE_MEM_START + 0x10000000, 0x08000000);
+	PCIE_OUTBOUND_WIN(3, PCIE_MEM_START + 0x18000000, 0x08000000);
+
+#if defined(CONFIG_BRCM_HAS_2GB_MEMC0)
+	/* set up 4GB PCIE->SCB memory window on BAR2 */
+	BDEV_WR(BCHP_PCIE_MISC_RC_BAR2_CONFIG_LO, 0x00000011);
+	BDEV_WR(BCHP_PCIE_MISC_RC_BAR2_CONFIG_HI, 0x00000000);
+	BDEV_WR_F(PCIE_MISC_MISC_CTRL, SCB0_SIZE, 0x10);
+	BDEV_WR_F(PCIE_MISC_MISC_CTRL, SCB1_SIZE, 0x0f);
+#else
+	/* set up 1GB PCIE->SCB memory window on BAR2 */
+	BDEV_WR(BCHP_PCIE_MISC_RC_BAR2_CONFIG_LO, 0x0000000f);
+	BDEV_WR(BCHP_PCIE_MISC_RC_BAR2_CONFIG_HI, 0x00000000);
+#endif
+
+	/* disable PCIE->GISB window */
+	BDEV_WR(BCHP_PCIE_MISC_RC_BAR1_CONFIG_LO, 0x00000000);
+	/* disable the other PCIE->SCB memory window */
+	BDEV_WR(BCHP_PCIE_MISC_RC_BAR3_CONFIG_LO, 0x00000000);
+
+	/* disable MSI (for now...) */
+	BDEV_WR(BCHP_PCIE_MISC_MSI_BAR_CONFIG_LO, 0);
+
+	/* set up L2 interrupt masks */
+	BDEV_WR_RB(BCHP_PCIE_INTR2_CPU_CLEAR, 0);
+	BDEV_WR_RB(BCHP_PCIE_INTR2_CPU_MASK_CLEAR, 0);
+	BDEV_WR_RB(BCHP_PCIE_INTR2_CPU_MASK_SET, 0xffffffff);
+
+	/* take the EP device out of reset */
+	BDEV_WR_F_RB(HIF_RGR1_SW_INIT_1, PCIE_SW_PERST, 0);
+
+	/* record the current time */
+	wktmr_read(&pcie_reset_started);
+}
+
+void brcm_setup_pcie_bridge(void)
+{
+	/* give the RC/EP time to wake up, before trying to configure RC */
+	while (wktmr_elapsed(&pcie_reset_started) < (100 * WKTMR_1MS))
+		;
+
+	if (!PCIE_LINK_UP()) {
+		struct clk *clk;
+
+		brcm_pcie_enabled = 0;
+		clk = brcm_buses[BRCM_BUSNO_PCIE].clk;
+		if (clk) {
+			clk_disable(clk);
+			clk_put(clk);
+		}
+		pr_info("PCIe link down\n");
+		return;
+	}
+	pr_info("PCIe link up, %sGbps x%lu\n",
+		BDEV_RD_F(PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL,
+			  NEG_LINK_SPEED) == 0x2 ? "5.0" : "2.5",
+		BDEV_RD_F(PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL,
+			  NEG_LINK_WIDTH));
+
+	/* enable MEM_SPACE and BUS_MASTER for RC */
+	BDEV_WR(BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND, 0x6);
+
+	/* set base/limit for outbound transactions */
+#if defined(CONFIG_BRCM_HAS_2GB_MEMC0)
+	BDEV_WR(BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT, 0xeff0d000);
+#else
+	BDEV_WR(BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT, 0xbff0a000);
+#endif
+
+	/* disable the prefetch range */
+	BDEV_WR(BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT, 0x0000fff0);
+
+	/* set pri/sec bus numbers */
+	BDEV_WR(BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO, 0x00010100);
+
+	/* enable configuration request retry (see pci_scan_device()) */
+	BDEV_WR_F(PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL, RC_CRS_EN, 1);
+
+	/* PCIE->SCB endian mode for BAR2 */
+	BDEV_WR_F_RB(PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1, ENDIAN_MODE_BAR2,
+		DATA_ENDIAN);
+}
+
+#if defined(CONFIG_PM)
+/*
+ * syscore device to handle PCIe bus suspend and resume
+ */
+static inline void pcie_enable(int enable)
+{
+	struct clk *clk;
+
+	if (!brcm_pcie_enabled)
+		return;
+
+	clk = brcm_buses[BRCM_BUSNO_PCIE].clk;
+	if (clk)
+		enable ? clk_enable(clk) : clk_disable(clk);
+}
+
+static int pcie_suspend(void)
+{
+	pcie_enable(0);
+	return 0;
+}
+
+static void pcie_resume(void)
+{
+	pcie_enable(1);
+}
+
+static struct syscore_ops pcie_pm_ops = {
+	.suspend        = pcie_suspend,
+	.resume         = pcie_resume,
+};
+#endif
+
+/***********************************************************************
+ * PCI controller registration
+ ***********************************************************************/
+
+static int __init brcmstb_pci_init(void)
+{
+	if (brcm_pcie_enabled) {
+		brcm_buses[BRCM_BUSNO_PCIE].clk = clk_get(NULL, "pcie");
+		brcm_setup_pcie_bridge();
+		brcm_buses[BRCM_BUSNO_PCIE].idx_reg =
+			BVIRTADDR(BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX);
+		brcm_buses[BRCM_BUSNO_PCIE].data_reg =
+			BVIRTADDR(BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_DATA);
+
+		register_pci_controller(&brcmstb_pcie_controller);
+#if defined(CONFIG_PM)
+		register_syscore_ops(&pcie_pm_ops);
+#endif
+	}
+	return 0;
+}
+
+arch_initcall(brcmstb_pci_init);
+
+/***********************************************************************
+ * Read/write PCI configuration registers
+ ***********************************************************************/
+
+#define CFG_INDEX(bus, devfn, reg) \
+	(((PCI_SLOT(devfn) & 0x1f) << (brcm_buses[bus->number].slot_shift)) | \
+	 ((PCI_FUNC(devfn) & 0x07) << (brcm_buses[bus->number].func_shift)) | \
+	 (brcm_buses[bus->number].hw_busnum << \
+	  brcm_buses[bus->number].busnum_shift) | \
+	 (reg))
+
+static int devfn_ok(struct pci_bus *bus, unsigned int devfn)
+{
+	/* PCIe: check for link down or invalid slot number */
+	if (bus->number == BRCM_BUSNO_PCIE &&
+	    (!PCIE_LINK_UP() || PCI_SLOT(devfn) != 0))
+		return 0;
+
+	return 1;	/* OK */
+}
+
+static int brcm_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+	int where, int size, u32 data)
+{
+	u32 val = 0, mask, shift;
+
+	if (!devfn_ok(bus, devfn))
+		return PCIBIOS_FUNC_NOT_SUPPORTED;
+
+	BUG_ON(((where & 3) + size) > 4);
+
+	if (size < 4) {
+		/* partial word - read, modify, write */
+		DEV_WR_RB(brcm_buses[bus->number].idx_reg,
+			CFG_INDEX(bus, devfn, where & ~3));
+		val = DEV_RD(brcm_buses[bus->number].data_reg);
+	}
+
+	shift = (where & 3) << 3;
+	mask = (0xffffffff >> ((4 - size) << 3)) << shift;
+
+	DEV_WR_RB(brcm_buses[bus->number].idx_reg,
+		CFG_INDEX(bus, devfn, where & ~3));
+	val = (val & ~mask) | ((data << shift) & mask);
+	DEV_WR_RB(brcm_buses[bus->number].data_reg, val);
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int brcm_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+	int where, int size, u32 *data)
+{
+	u32 val, mask, shift;
+
+	if (!devfn_ok(bus, devfn))
+		return PCIBIOS_FUNC_NOT_SUPPORTED;
+
+	BUG_ON(((where & 3) + size) > 4);
+
+	DEV_WR_RB(brcm_buses[bus->number].idx_reg,
+		CFG_INDEX(bus, devfn, where & ~3));
+	val = DEV_RD(brcm_buses[bus->number].data_reg);
+
+	shift = (where & 3) << 3;
+	mask = (0xffffffff >> ((4 - size) << 3)) << shift;
+
+	*data = (val & mask) >> shift;
+	return PCIBIOS_SUCCESSFUL;
+}
+
+/***********************************************************************
+ * PCI slot to IRQ mappings (aka "fixup")
+ ***********************************************************************/
+
+int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+	if (dev->bus->number == BRCM_BUSNO_PCIE) {
+		const int pcie_irq[] = {
+			BRCM_IRQ_PCIE_INTA, BRCM_IRQ_PCIE_INTB,
+			BRCM_IRQ_PCIE_INTC, BRCM_IRQ_PCIE_INTD,
+		};
+		if ((pin - 1) > 3)
+			return 0;
+		return pcie_irq[pin - 1];
+	}
+	return 0;
+}
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+	return 0;
+}
+
+
+/***********************************************************************
+ * Per-device initialization
+ ***********************************************************************/
+
+static void __devinit brcm_pcibios_fixup(struct pci_dev *dev)
+{
+	int slot = PCI_SLOT(dev->devfn);
+
+	pr_info("found device %04x:%04x on %s bus, slot %d (irq %d)\n",
+		dev->vendor, dev->device, brcm_buses[dev->bus->number].name,
+		slot, pcibios_map_irq(dev, slot, 1));
+
+	/* zero out the BARs and let Linux assign an address */
+	pci_write_config_dword(dev, PCI_COMMAND, 0);
+	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
+	pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
+	pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, 0);
+	pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, 0);
+	pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0);
+	pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0);
+	pci_write_config_dword(dev, PCI_INTERRUPT_LINE, 0);
+}
+
+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, brcm_pcibios_fixup);
+
+/***********************************************************************
+ * DMA address remapping
+ ***********************************************************************/
+
+/*
+ * PCIe inbound BARs collapse the "holes" in the chip's SCB address space.
+ * Therefore the PCI addresses need to be adjusted as they will not match
+ * the SCB addresses (MIPS physical addresses).
+ *
+ * The address maps can be found in <asm/mach-brcmstb/spaces.h> .
+ */
+
+static int dev_collapses_memory_hole(struct device *dev)
+{
+#if defined(CONFIG_BRCM_UPPER_MEMORY) || defined(CONFIG_HIGHMEM)
+
+	struct pci_dev *pdev;
+
+	if (unlikely(dev == NULL) ||
+	    likely(dev->bus != &pci_bus_type))
+		return 0;
+
+	pdev = to_pci_dev(dev);
+	if (unlikely(pdev == NULL) ||
+	    brcm_buses[pdev->bus->number].memory_hole)
+		return 0;
+
+	return 1;
+#else
+	return 0;
+#endif
+}
+
+static dma_addr_t brcm_phys_to_pci(struct device *dev, unsigned long phys)
+{
+	if (!dev_collapses_memory_hole(dev))
+		return phys;
+	if (phys >= MEMC1_START)
+		return phys - MEMC1_PCI_OFFSET;
+	if (phys >= (BRCM_PCI_HOLE_START + BRCM_PCI_HOLE_SIZE))
+		return phys - BRCM_PCI_HOLE_SIZE;
+	return phys;
+}
+
+dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
+{
+	return brcm_phys_to_pci(dev, virt_to_phys(addr));
+}
+
+dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
+{
+	return brcm_phys_to_pci(dev, page_to_phys(page));
+}
+
+unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
+{
+	if (!dev_collapses_memory_hole(dev))
+		return dma_addr;
+	if (dma_addr >= (MEMC1_START - MEMC1_PCI_OFFSET))
+		return dma_addr + MEMC1_PCI_OFFSET;
+	if (dma_addr >= BRCM_PCI_HOLE_START)
+		return dma_addr + BRCM_PCI_HOLE_SIZE;
+	return dma_addr;
+}
diff --git a/drivers/brcmstb/power.c b/drivers/brcmstb/power.c
new file mode 100644
index 0000000..4488139
--- /dev/null
+++ b/drivers/brcmstb/power.c
@@ -0,0 +1,4532 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <stdarg.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/sysfs.h>
+#include <linux/device.h>
+#include <linux/ctype.h>
+#include <linux/smp.h>
+#include <linux/platform_device.h>
+#include <linux/suspend.h>
+#include <linux/mii.h>
+#include <linux/spinlock.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/compiler.h>
+#include <linux/brcmstb/brcmstb.h>
+
+/* Wakeup on timeout (20 sec) even if standby_flags does not request this */
+#define WATCHDOG_TIMER_WAKEUP_ALWAYS		(0)
+
+#define PRINT_PM_CALLBACK		printk(KERN_DEBUG "%s %02x\n", \
+	__func__, (u8)flags)
+#if 0
+#define DBG			printk
+#else
+#define DBG(...)		do { } while (0)
+#endif
+
+/***********************************************************************
+ * USB / ENET / GENET / MoCA / SATA PM common internal functions
+ ***********************************************************************/
+struct clk {
+	char		name[16];
+	int             refcnt;
+	struct clk     *parent;
+	int		(*cb)(int, void *);
+	void		*cb_arg;
+	void		(*disable)(u32 flags);
+	void		(*enable)(u32 flags);
+	int		(*set_rate)(unsigned long rate);
+	u32		flags;
+	struct list_head list;
+};
+/*
+ * Flags:
+ * BRCM_PM_FLAG_S3		- S3 standby inititated. Since all blocks lose
+ *	power, there is no need to preserve state.
+ *	On-chip SRAM can be unconditionally powered down.
+ * BRCM_PM_FLAG_ENET_WOL	- Ethernet WOL is a wake-up event
+ * BRCM_PM_FLAG_MOCA_WOL	- MoCA WOL is a wake-up event
+ * BRCM_PM_FLAG_USB_WAKEUP	- USB insertion/removal is a wake-up event
+ */
+#define BRCM_PM_FLAG_S3		0x01 /* set when suspend begins */
+#define BRCM_PM_FLAG_ENET_WOL	0x02 /* ENET WOL is enabled */
+#define BRCM_PM_FLAG_MOCA_WOL	0x04 /* MoCA WOL is enabled */
+#define BRCM_PM_FLAG_USB_WAKEUP	0x08 /* USB insertion/removal wakeup */
+
+#define ANY_WOL(flags) (flags & (BRCM_PM_FLAG_ENET_WOL|BRCM_PM_FLAG_MOCA_WOL))
+#define ENET_WOL(flags) (flags & BRCM_PM_FLAG_ENET_WOL)
+#define MOCA_WOL(flags) (flags & BRCM_PM_FLAG_MOCA_WOL)
+
+static DEFINE_SPINLOCK(brcm_pm_clk_lock);
+
+static void brcm_pm_sata_disable(u32 flags);
+static void brcm_pm_sata_enable(u32 flags);
+static void brcm_pm_genet_disable(u32 flags);
+static void brcm_pm_genet_enable(u32 flags);
+static void brcm_pm_genet_disable_wol(u32 flags);
+static void brcm_pm_genet_enable_wol(u32 flags);
+static void brcm_pm_moca_disable(u32 flags);
+static void brcm_pm_moca_enable(u32 flags);
+static void brcm_pm_moca_disable_wol(u32 flags);
+static void brcm_pm_moca_enable_wol(u32 flags);
+static void brcm_pm_genet1_disable(u32 flags);
+static void brcm_pm_genet1_enable(u32 flags);
+static void brcm_pm_network_disable(u32 flags);
+static void brcm_pm_network_enable(u32 flags);
+static void brcm_pm_usb_disable(u32 flags);
+static void brcm_pm_usb_enable(u32 flags);
+static void brcm_pm_set_ddr_timeout(int);
+static void brcm_pm_initialize(void);
+static int  brcm_pm_moca_cpu_set_rate(unsigned long rate);
+static int  brcm_pm_moca_phy_set_rate(unsigned long rate);
+
+static int brcm_pm_ddr_timeout;
+static unsigned long brcm_pm_standby_flags;
+static unsigned long brcm_pm_standby_timeout;
+
+enum {
+	BRCM_CLK_SATA,
+	BRCM_CLK_GENET,
+	BRCM_CLK_MOCA,
+	BRCM_CLK_USB,
+	BRCM_CLK_GENET1,
+	BRCM_CLK_NETWORK,	/* PLLs/clocks common to all GENETs */
+	BRCM_CLK_GENET_WOL,
+	BRCM_CLK_MOCA_WOL,
+	BRCM_CLK_MOCA_PHY,
+	BRCM_CLK_MOCA_CPU,
+};
+
+static struct clk brcm_clk_table[] = {
+	[BRCM_CLK_SATA] = {
+		.name		= "sata",
+		.disable	= &brcm_pm_sata_disable,
+		.enable		= &brcm_pm_sata_enable,
+	},
+	[BRCM_CLK_GENET] = {
+		.name		= "enet",
+		.disable	= &brcm_pm_genet_disable,
+		.enable		= &brcm_pm_genet_enable,
+		.parent		= &brcm_clk_table[BRCM_CLK_NETWORK],
+	},
+	[BRCM_CLK_MOCA] = {
+		.name		= "moca",
+		.disable	= &brcm_pm_moca_disable,
+		.enable		= &brcm_pm_moca_enable,
+		.parent		= &brcm_clk_table[BRCM_CLK_GENET1],
+	},
+	[BRCM_CLK_USB] = {
+		.name		= "usb",
+		.disable	= &brcm_pm_usb_disable,
+		.enable		= &brcm_pm_usb_enable,
+	},
+	[BRCM_CLK_GENET1] = {
+		.name		= "moca_genet",
+		.disable	= &brcm_pm_genet1_disable,
+		.enable		= &brcm_pm_genet1_enable,
+		.parent		= &brcm_clk_table[BRCM_CLK_NETWORK],
+	},
+	[BRCM_CLK_NETWORK] = {
+		.name		= "network",
+		.disable	= &brcm_pm_network_disable,
+		.enable		= &brcm_pm_network_enable,
+	},
+	[BRCM_CLK_GENET_WOL] = {
+		.name		= "enet-wol",
+		.disable	= &brcm_pm_genet_disable_wol,
+		.enable		= &brcm_pm_genet_enable_wol,
+	},
+	[BRCM_CLK_MOCA_WOL] = {
+		.name		= "moca-wol",
+		.disable	= &brcm_pm_moca_disable_wol,
+		.enable		= &brcm_pm_moca_enable_wol,
+	},
+	[BRCM_CLK_MOCA_CPU] = {
+		.name		= "moca-cpu",
+		.set_rate	= &brcm_pm_moca_cpu_set_rate,
+	},
+	[BRCM_CLK_MOCA_PHY] = {
+		.name		= "moca-phy",
+		.set_rate	= &brcm_pm_moca_phy_set_rate,
+	},
+};
+
+/* These clocks are chip specific - each .initialize()
+  method will add them if needed */
+static LIST_HEAD(brcm_dyn_clk_list);
+
+static __maybe_unused void __clk_dyn_add(struct clk *clk)
+{
+	struct clk *clk_p;
+	list_for_each_entry(clk_p, &brcm_dyn_clk_list, list) {
+		if (clk_p == clk)
+			return;
+	}
+	list_add(&clk->list, &brcm_dyn_clk_list);
+}
+
+static __maybe_unused void __clk_dyn_del(struct clk *clk)
+{
+	list_del(&clk->list);
+}
+
+static struct clk *brcm_pm_clk_find(const char *name)
+{
+	int i;
+	struct clk *clk = brcm_clk_table;
+
+	BUG_ON(!name);
+	/* first check static clocks */
+	for (i = 0; i < ARRAY_SIZE(brcm_clk_table); i++, clk++)
+		if (!strncmp(name, clk->name, strlen(name)))
+			return clk;
+
+	/* check dynamic clocks */
+	list_for_each_entry(clk, &brcm_dyn_clk_list, list) {
+		if (!strncmp(name, clk->name, strlen(name)))
+			return clk;
+	}
+	return NULL;
+}
+
+/* sysfs attributes */
+
+ssize_t brcm_pm_show_sata_power(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	struct clk *clk = brcm_pm_clk_find("sata");
+	return snprintf(buf, PAGE_SIZE, "%d\n", !!clk->refcnt);
+}
+
+ssize_t brcm_pm_store_sata_power(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct clk *clk = brcm_pm_clk_find("sata");
+	int val;
+
+	if (!clk || !clk->cb || sscanf(buf, "%d", &val) != 1)
+		return -EINVAL;
+
+	return clk->cb(val ? PM_EVENT_RESUME : PM_EVENT_SUSPEND,
+		clk->cb_arg) ? : count;
+}
+
+ssize_t brcm_pm_show_ddr_timeout(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%d\n", brcm_pm_ddr_timeout);
+}
+
+ssize_t brcm_pm_store_ddr_timeout(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	int val;
+	if (sscanf(buf, "%d", &val) != 1)
+		return -EINVAL;
+
+	brcm_pm_ddr_timeout = val;
+	if (brcm_pm_enabled)
+		brcm_pm_set_ddr_timeout(val);
+	return count;
+}
+
+ssize_t brcm_pm_show_standby_flags(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "0x%lx\n", brcm_pm_standby_flags);
+}
+
+ssize_t brcm_pm_store_standby_flags(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	unsigned long val;
+	if (sscanf(buf, "%lx", &val) != 1)
+		return -EINVAL;
+
+	brcm_pm_standby_flags = val;
+	return count;
+}
+
+ssize_t brcm_pm_show_standby_timeout(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%lu\n", brcm_pm_standby_timeout);
+}
+
+ssize_t brcm_pm_store_standby_timeout(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	unsigned long val;
+	if (sscanf(buf, "%lu", &val) != 1)
+		return -EINVAL;
+
+	brcm_pm_standby_timeout = val;
+	return count;
+}
+#if defined(CONFIG_BRCM_HAS_1GB_MEMC1)
+/*
+ * brcm_pm_memc1_power
+ * Power state of secondary memory controller
+ * 0 - complete power down (with loss of content)
+ * 1 - full power mode
+ * 2 - SSPD (content preserved)
+ * Direct transition between 0 and 2 is not supported
+ */
+#define BRCM_PM_MEMC1_OFF	0
+#define BRCM_PM_MEMC1_ON	1
+#define BRCM_PM_MEMC1_SSPD	2
+
+static int brcm_pm_memc1_power = BRCM_PM_MEMC1_ON;
+int __weak brcm_pm_memc1_suspend(int is_s3) { return 0; }
+int __weak brcm_pm_memc1_resume(int is_s3) { return 0; }
+int __weak brcm_pm_memc1_powerdown(void) { return 0; }
+int  __weak brcm_pm_memc1_powerup(void) { return 0; }
+
+ssize_t brcm_pm_show_memc1_power(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%d\n", brcm_pm_memc1_power);
+}
+
+ssize_t brcm_pm_store_memc1_power(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	int val;
+
+	/*
+	 * if memc1 memory has been added to system memory pool,
+	 * disable memc1 dynamic PM
+	 */
+	if (brcm_dram1_linux_mb && brcm_dram1_linux_mb <= brcm_dram1_size_mb) {
+		sysfs_chmod_file(&dev->kobj,
+			&attr->attr, attr->attr.mode & ~S_IWUGO);
+		return -EINVAL;
+	}
+
+	if (sscanf(buf, "%d", &val) != 1)
+		return -EINVAL;
+
+	/* check for no change */
+	if (val == brcm_pm_memc1_power)
+		return count;
+
+	switch (val) {
+	case BRCM_PM_MEMC1_OFF:
+		if (brcm_pm_memc1_power == BRCM_PM_MEMC1_ON)
+			brcm_pm_memc1_powerdown();
+		else
+			return -EINVAL;
+		break;
+	case BRCM_PM_MEMC1_ON:
+		if (brcm_pm_memc1_power == BRCM_PM_MEMC1_OFF) {
+			if (brcm_pm_memc1_powerup())
+				return -EINVAL;
+		} else if (brcm_pm_memc1_power == BRCM_PM_MEMC1_SSPD)
+			brcm_pm_memc1_resume(0);
+		else
+			return -EINVAL;
+		break;
+	case BRCM_PM_MEMC1_SSPD:
+		if (brcm_pm_memc1_power == BRCM_PM_MEMC1_ON)
+			brcm_pm_memc1_suspend(0);
+		else
+			return -EINVAL;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	brcm_pm_memc1_power = val;
+	return count;
+}
+
+#endif
+
+static u32 brcm_pm_time_at_wakeup[2];
+ssize_t brcm_pm_show_time_at_wakeup(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "0x%x 0x%x\n",
+		brcm_pm_time_at_wakeup[0], brcm_pm_time_at_wakeup[1]);
+}
+
+static int brcm_pm_halt_mode=1;
+
+#if 0
+ssize_t brcm_pm_show_halt_mode(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%d\n", brcm_pm_halt_mode);
+}
+
+ssize_t brcm_pm_store_halt_mode(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	int val;
+	if (sscanf(buf, "%d", &val) != 1)
+		return -EINVAL;
+
+	brcm_pm_halt_mode = !!val;
+	return count;
+}
+#endif
+
+/* Boot time functions */
+
+static int __init brcm_pm_init(void)
+{
+	if (!brcm_pm_enabled)
+		return 0;
+	if (!brcm_moca_enabled)
+		brcm_pm_moca_disable(0);
+	/* chip specific initialization */
+	brcm_pm_initialize();
+	return 0;
+}
+
+early_initcall(brcm_pm_init);
+
+static int nopm_setup(char *str)
+{
+	brcm_pm_enabled = 0;
+	return 0;
+}
+
+__setup("nopm", nopm_setup);
+
+int brcm_pm_hash_enabled = 1;
+
+static int nohash_setup(char *str)
+{
+	brcm_pm_hash_enabled = 0;
+	return 0;
+}
+
+__setup("nohash", nohash_setup);
+
+/***********************************************************************
+ * USB / ENET / GENET / MoCA / SATA PM external API
+ ***********************************************************************/
+
+/* internal functions assume the lock is held */
+static int __clk_enable(struct clk *clk, u32 flags)
+{
+	BUG_ON(clk->refcnt < 0);
+	if (++(clk->refcnt) == 1 && brcm_pm_enabled) {
+		if (clk->parent)
+			__clk_enable(clk->parent, clk->flags | flags);
+		printk(KERN_DEBUG "%s: %s [%d]\n",
+			__func__, clk->name, clk->refcnt);
+		if (clk->enable)
+			clk->enable(clk->flags | flags);
+	}
+	return 0;
+}
+
+static void __clk_disable(struct clk *clk, u32 flags)
+{
+	if (--(clk->refcnt) == 0 && brcm_pm_enabled) {
+		printk(KERN_DEBUG "%s: %s [%d]\n",
+			__func__, clk->name, clk->refcnt);
+		if (clk->disable)
+			clk->disable(clk->flags | flags);
+		if (clk->parent)
+			__clk_disable(clk->parent, clk->flags | flags);
+	}
+	BUG_ON(clk->refcnt < 0);
+}
+
+int clk_enable(struct clk *clk)
+{
+	unsigned long flags;
+
+	if (clk && !IS_ERR(clk)) {
+		spin_lock_irqsave(&brcm_pm_clk_lock, flags);
+		__clk_enable(clk, 0);
+		spin_unlock_irqrestore(&brcm_pm_clk_lock, flags);
+		return 0;
+	} else {
+		return -EINVAL;
+	}
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+	unsigned long flags;
+
+	if (clk && !IS_ERR(clk)) {
+		spin_lock_irqsave(&brcm_pm_clk_lock, flags);
+		__clk_disable(clk, 0);
+		spin_unlock_irqrestore(&brcm_pm_clk_lock, flags);
+	}
+}
+EXPORT_SYMBOL(clk_disable);
+
+void clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_put);
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	unsigned long flags;
+	spinlock_t *lock = &brcm_pm_clk_lock;
+	if (clk && !IS_ERR(clk)) {
+		spin_lock_irqsave(lock, flags);
+		clk->parent = parent;
+		spin_unlock_irqrestore(lock, flags);
+		return 0;
+	}
+	return -EINVAL;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+	if (clk && !IS_ERR(clk))
+		return clk->parent;
+
+	return NULL;
+}
+EXPORT_SYMBOL(clk_get_parent);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long flags;
+	int ret;
+	spinlock_t *lock = &brcm_pm_clk_lock;
+
+	if (clk && !IS_ERR(clk) && clk->set_rate) {
+		spin_lock_irqsave(lock, flags);
+		ret = clk->set_rate(rate);
+		spin_unlock_irqrestore(lock, flags);
+		return ret;
+	}
+	return -EINVAL;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+int brcm_pm_register_cb(char *name, int (*fn)(int, void *), void *arg)
+{
+	struct clk *clk = brcm_pm_clk_find(name);
+	unsigned long flags;
+
+	if (!clk)
+		return -ENOENT;
+
+	spin_lock_irqsave(&brcm_pm_clk_lock, flags);
+	BUG_ON(fn && clk->cb);
+	clk->cb = fn;
+	clk->cb_arg = arg;
+	spin_unlock_irqrestore(&brcm_pm_clk_lock, flags);
+
+	return 0;
+}
+EXPORT_SYMBOL(brcm_pm_register_cb);
+
+int brcm_pm_unregister_cb(char *name)
+{
+	return brcm_pm_register_cb(name, NULL, NULL);
+}
+EXPORT_SYMBOL(brcm_pm_unregister_cb);
+
+/***********************************************************************
+ * Wakeup source management
+ *   All kernel drivers can use this api to register their wakeup
+ *   sources. This will enable 'lightweight' resume feature, when
+ *   wakeup event is quickly qualified immediately after resume using
+ *   driver-supplied poll() method. If none of registered poll() method
+ *   recognize the wakeup event, system may be brought back to sleep.
+ *   To allow for other components to use their wakeup capabilities, system
+ *   suspend code will save the pre-suspend PM_L2 mask and, if all poll()
+ *   callbacks deny the wakeup event, check if one of events enabled in the
+ *   saved mask has occurred.
+ ***********************************************************************/
+struct brcm_wakeup_source {
+	struct brcm_wakeup_ops		*ops;
+	void				*ref;
+	struct list_head		list;
+	struct kref			kref;
+	char				name[16];
+};
+
+struct brcm_wakeup_control {
+	spinlock_t			lock;
+	struct list_head		head;
+	int				count;
+};
+
+static struct brcm_wakeup_control bwc;
+
+int brcm_pm_wakeup_register(struct brcm_wakeup_ops *ops, void *ref, char *name)
+{
+	struct brcm_wakeup_source *bws;
+	unsigned long flags;
+
+	list_for_each_entry(bws, &bwc.head, list) {
+		if (bws->ops == ops && bws->ref == ref) {
+			/* already registered */
+			spin_lock_irqsave(&bwc.lock, flags);
+			kref_get(&bws->kref);
+			spin_unlock_irqrestore(&bwc.lock, flags);
+			return 0;
+		}
+	}
+
+	bws = kmalloc(sizeof(struct brcm_wakeup_source), GFP_ATOMIC);
+	if (!bws)
+		return -1;
+
+	bws->ops = ops;
+	bws->ref = ref;
+	if (name)
+		strncpy(bws->name, name, 16);
+
+	kref_init(&bws->kref);
+	kref_get(&bws->kref);
+
+	spin_lock_irqsave(&bwc.lock, flags);
+	list_add_tail(&bws->list, &bwc.head);
+	spin_unlock_irqrestore(&bwc.lock, flags);
+
+	return 0;
+}
+EXPORT_SYMBOL(brcm_pm_wakeup_register);
+
+/* This function is called with bwc lock held*/
+static void brcm_pm_wakeup_cleanup(struct kref *kref)
+{
+	struct brcm_wakeup_source *bws =
+		container_of(kref, struct brcm_wakeup_source, kref);
+	list_del(&bws->list);
+	kfree(bws);
+}
+
+int brcm_pm_wakeup_unregister(struct brcm_wakeup_ops *ops, void *ref)
+{
+	struct brcm_wakeup_source *bws;
+	unsigned long flags;
+
+	spin_lock_irqsave(&bwc.lock, flags);
+
+	list_for_each_entry(bws, &bwc.head, list)
+		if (bws->ops == ops && bws->ref == ref)
+			kref_put(&bws->kref, brcm_pm_wakeup_cleanup);
+
+	spin_unlock_irqrestore(&bwc.lock, flags);
+
+	return 0;
+}
+
+static int brcm_pm_wakeup_enable(void)
+{
+	struct brcm_wakeup_source *bws;
+	unsigned long flags;
+
+	spin_lock_irqsave(&bwc.lock, flags);
+
+	list_for_each_entry(bws, &bwc.head, list) {
+		if (bws->ops && bws->ops->enable)
+			bws->ops->enable(bws->ref);
+	}
+	spin_unlock_irqrestore(&bwc.lock, flags);
+	return 0;
+}
+
+static int brcm_pm_wakeup_disable(void)
+{
+	struct brcm_wakeup_source *bws;
+	unsigned long flags;
+
+	spin_lock_irqsave(&bwc.lock, flags);
+
+	list_for_each_entry(bws, &bwc.head, list) {
+		if (bws->ops && bws->ops->disable)
+			bws->ops->disable(bws->ref);
+	}
+	spin_unlock_irqrestore(&bwc.lock, flags);
+	return 0;
+}
+
+/*
+Function asks all registered objects if a wakeup event has happened.
+If no registered object claims the event, it checks for all interrupts
+enabled prior to suspend.
+It returns 0 if no valid wake up event has occurred, 1 otherwise.
+*/
+static int brcm_pm_wakeup_poll(u32 mask)
+{
+	int ev_occurred = 0;
+	struct brcm_wakeup_source *bws;
+	unsigned long flags;
+
+	spin_lock_irqsave(&bwc.lock, flags);
+
+	list_for_each_entry(bws, &bwc.head, list) {
+		if (bws->ops && bws->ops->poll)
+			ev_occurred |= bws->ops->poll(bws->ref);
+	}
+	spin_unlock_irqrestore(&bwc.lock, flags);
+
+	/* Check for events outside of kernel control */
+	if (!ev_occurred)
+		ev_occurred |= brcm_pm_wakeup_get_status(~mask);
+
+	return ev_occurred;
+}
+
+int brcm_pm_wakeup_init(void)
+{
+	spin_lock_init(&bwc.lock);
+	INIT_LIST_HEAD(&bwc.head);
+	return 0;
+}
+early_initcall(brcm_pm_wakeup_init);
+
+/***********************************************************************
+ * USB / ENET / GENET / MoCA / SATA PM implementations (per-chip)
+ ***********************************************************************/
+static __maybe_unused void brcm_ddr_phy_initialize(void);
+
+/*
+ * Per-block power management operations pair.
+ * Parameter flags is used to control wake-up capabilities
+ */
+
+struct brcm_chip_pm_block_ops {
+	void (*enable)(u32 flags);
+	void (*disable)(u32 flags);
+	int (*set_cpu_rate)(unsigned long rate);
+	int (*set_phy_rate)(unsigned long rate);
+};
+
+static u32 brcm_pm_flags;
+
+struct brcm_chip_pm_ops {
+	/* SATA power/clock gating */
+	struct brcm_chip_pm_block_ops sata;
+	/* genet0 power/clock gating */
+	struct brcm_chip_pm_block_ops genet;
+	/* genet1 power/clock gating */
+	struct brcm_chip_pm_block_ops genet1;
+	/* MoCA power/clock gating */
+	struct brcm_chip_pm_block_ops moca;
+	/* USB power/clock gating */
+	struct brcm_chip_pm_block_ops usb;
+	/* genet0/genet1/MoCA common power/clock gating */
+	struct brcm_chip_pm_block_ops network;
+	/* system-wide initialization code */
+	void (*initialize)(void);
+	/* system suspend code */
+	void (*suspend)(u32 flags);
+	/* system resume code */
+	void (*resume)(u32 flags);
+	/*
+	 * System suspend code executed immediately before
+	 * initiating low-level suspend sequence.
+	 * For example, shutting down secondary memory controller
+	 * can be done here when system no longer uses highmem regions
+	 */
+	void (*late_suspend)(int is_s3);
+	void (*early_resume)(int is_s3);
+	/* for chip specific clock mappings ( see #SWLINUX-1764 ) */
+	struct clk* (*clk_get)(struct device *dev, const char *id);
+};
+
+#define DEF_BLOCK_PM_OP(block, chip) \
+	.block.enable	= bcm##chip##_pm_##block##_enable, \
+	.block.disable	= bcm##chip##_pm_##block##_disable
+#define DEF_SYSTEM_PM_OP(chip) \
+	.suspend	= bcm##chip##_pm_suspend, \
+	.resume		= bcm##chip##_pm_resume
+#define DEF_SYSTEM_LATE_PM_OP(chip) \
+	.late_suspend	= bcm##chip##_pm_late_suspend, \
+	.early_resume	= bcm##chip##_pm_early_resume
+
+#define PLL_CH_DIS(x)		BDEV_WR_RB(BCHP_##x, 0x04)
+#define PLL_CH_ENA(x)		do { \
+					BDEV_WR_RB(BCHP_##x, 0x03); \
+					mdelay(1); \
+				} while (0)
+
+#define PLL_DIS(x)		BDEV_WR_RB(BCHP_##x, 0x04)
+#define PLL_ENA(x)		do { \
+					BDEV_WR_RB(BCHP_##x, 0x03); \
+					mdelay(1); \
+				} while (0)
+
+static __maybe_unused struct clk *brcm_pm_clk_get(struct device *dev,
+	const char *id)
+{
+	if (!strncmp(id, "enet", 4) && dev) {
+		struct platform_device *pdev = to_platform_device(dev);
+		if (pdev->id == 0) /* enet */
+			return brcm_pm_clk_find(id);
+		if (pdev->id == 1) /* moca_genet */ {
+			if (strstr(id, "-wol"))
+				return brcm_pm_clk_find("moca-wol");
+			return brcm_pm_clk_find("moca");
+		}
+	}
+	return NULL;
+}
+
+/***********************************************************************
+ * Encryption setup for S3 suspend
+ ***********************************************************************/
+static struct brcm_dram_encoder_ops *dram_encoder_ops;
+
+void brcm_pm_set_dram_encoder(struct brcm_dram_encoder_ops *ops)
+{
+	dram_encoder_ops = ops;
+}
+EXPORT_SYMBOL(brcm_pm_set_dram_encoder);
+
+int brcm_pm_dram_encoder_prepare(struct brcm_mem_transfer *param)
+{
+	if (dram_encoder_ops && dram_encoder_ops->prepare)
+		return dram_encoder_ops->prepare(param);
+	return -1;
+}
+EXPORT_SYMBOL(brcm_pm_dram_encoder_prepare);
+
+int brcm_pm_dram_encoder_complete(struct brcm_mem_transfer *param)
+{
+	if (dram_encoder_ops && dram_encoder_ops->complete)
+		return dram_encoder_ops->complete(param);
+	return -1;
+}
+EXPORT_SYMBOL(brcm_pm_dram_encoder_complete);
+
+void brcm_pm_dram_encoder_start(void)
+{
+	if (dram_encoder_ops && dram_encoder_ops->start)
+		dram_encoder_ops->start();
+}
+EXPORT_SYMBOL(brcm_pm_dram_encoder_start);
+
+#if defined(CONFIG_BCM7125)
+static void bcm7125_pm_sata_disable(u32 flags)
+{
+	BDEV_WR_F_RB(SUN_TOP_CTRL_GENERAL_CTRL_1, sata_ana_pwrdn, 1);
+	BDEV_WR_F_RB(CLKGEN_SATA_CLK_PM_CTRL, DIS_CLK_99P7, 1);
+	BDEV_WR_F_RB(CLKGEN_SATA_CLK_PM_CTRL, DIS_CLK_216, 1);
+	BDEV_WR_F_RB(CLKGEN_SATA_CLK_PM_CTRL, DIS_CLK_108, 1);
+	PLL_CH_DIS(VCXO_CTL_MISC_RAP_AVD_PLL_CHL_4);
+}
+
+static void bcm7125_pm_sata_enable(u32 flags)
+{
+	PLL_CH_ENA(VCXO_CTL_MISC_RAP_AVD_PLL_CHL_4);
+	BDEV_WR_F_RB(CLKGEN_SATA_CLK_PM_CTRL, DIS_CLK_108, 0);
+	BDEV_WR_F_RB(CLKGEN_SATA_CLK_PM_CTRL, DIS_CLK_216, 0);
+	BDEV_WR_F_RB(CLKGEN_SATA_CLK_PM_CTRL, DIS_CLK_99P7, 0);
+	BDEV_WR_F_RB(SUN_TOP_CTRL_GENERAL_CTRL_1, sata_ana_pwrdn, 0);
+}
+
+static void bcm7125_pm_network_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (MOCA_WOL(flags)) {
+		BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS,
+			CLOCK_SEL_ENET_CG_MOCA, 1);
+		BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS,
+			CLOCK_SEL_GMII_CG_MOCA, 1);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL, DIS_CLK_HFB, 0);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL, DIS_CLK_L2_INTR, 1);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL,
+			DIS_CLK_UNIMAC_SYS_TX, 1);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL, DIS_CLK_216, 1);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL,
+			DIS_CLK_250_GENET_MOCA, 1);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL, DIS_CLK_54, 1);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL, DIS_CLK_108, 1);
+		return;
+	}
+	BDEV_SET_RB(BCHP_CLKGEN_MOCA_CLK_PM_CTRL, 0xf77);
+	BDEV_WR_RB(BCHP_CLKGEN_PLL_MOCA_CH3_PM_CTRL, 0x04);
+	BDEV_WR_RB(BCHP_CLKGEN_PLL_MOCA_CH4_PM_CTRL, 0x04);
+	BDEV_WR_RB(BCHP_CLKGEN_PLL_MOCA_CH5_PM_CTRL, 0x04);
+	BDEV_WR_RB(BCHP_CLKGEN_PLL_MOCA_CH6_PM_CTRL, 0x04);
+	BDEV_SET_RB(BCHP_CLKGEN_PLL_MOCA_CTRL, 0x13);
+}
+
+static void bcm7125_pm_network_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (MOCA_WOL(flags)) {
+		BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS,
+			CLOCK_SEL_ENET_CG_MOCA, 0);
+		BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS,
+			CLOCK_SEL_GMII_CG_MOCA, 0);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL, DIS_CLK_L2_INTR, 0);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL,
+			DIS_CLK_UNIMAC_SYS_TX, 0);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL, DIS_CLK_216, 0);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL,
+			DIS_CLK_250_GENET_MOCA, 0);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL, DIS_CLK_54, 0);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL, DIS_CLK_108, 0);
+		return;
+	}
+	BDEV_UNSET_RB(BCHP_CLKGEN_PLL_MOCA_CTRL, 0x13);
+	BDEV_WR_RB(BCHP_CLKGEN_PLL_MOCA_CH6_PM_CTRL, 0x01);
+	BDEV_WR_RB(BCHP_CLKGEN_PLL_MOCA_CH5_PM_CTRL, 0x01);
+	BDEV_WR_RB(BCHP_CLKGEN_PLL_MOCA_CH4_PM_CTRL, 0x01);
+	BDEV_WR_RB(BCHP_CLKGEN_PLL_MOCA_CH3_PM_CTRL, 0x01);
+	BDEV_UNSET_RB(BCHP_CLKGEN_MOCA_CLK_PM_CTRL, 0xf77);
+}
+
+static void bcm7125_pm_usb_disable(u32 flags)
+{
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, PLL_PWRDWNB, 0);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_IDDQ, 1);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, PHY_PWDNB, 0x00);
+	BDEV_WR_F_RB(CLKGEN_USB_CLK_PM_CTRL, DIS_CLK_216, 1);
+	BDEV_WR_F_RB(CLKGEN_USB_CLK_PM_CTRL, DIS_CLK_108, 1);
+	PLL_CH_DIS(CLKGEN_PLL_MAIN_CH4_PM_CTRL);
+}
+
+static void bcm7125_pm_usb_enable(u32 flags)
+{
+	PLL_CH_ENA(CLKGEN_PLL_MAIN_CH4_PM_CTRL);
+	BDEV_WR_F_RB(CLKGEN_USB_CLK_PM_CTRL, DIS_CLK_108, 0);
+	BDEV_WR_F_RB(CLKGEN_USB_CLK_PM_CTRL, DIS_CLK_216, 0);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, PHY_PWDNB, 0x0f);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_IDDQ, 0);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, PLL_PWRDWNB, 1);
+}
+
+static void bcm7125_pm_suspend(u32 flags)
+{
+	/* PCI/EBI */
+	BDEV_WR_RB(BCHP_HIF_TOP_CTRL_PM_CTRL, 0x3ff8);
+	BDEV_WR_F_RB(CLKGEN_CLK_27_OUT_PM_CTRL, DIS_CLK_27_OUT, 1);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_PM_DIS_CHL_1, DIS_CH, 1);
+	BDEV_SET_RB(BCHP_CLKGEN_HIF_CLK_PM_CTRL, 0x3c);
+
+	/* system PLLs */
+	BDEV_SET_RB(BCHP_VCXO_CTL_MISC_VC0_CTRL, 0x0b);
+	BDEV_UNSET_RB(BCHP_VCXO_CTL_MISC_VC0_CTRL, 0x04);
+	BDEV_SET_RB(BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL, 0x07);
+	BDEV_WR_F_RB(CLKGEN_VCXO_CLK_PM_CTRL, DIS_CLK_216, 1);
+	BDEV_WR_F_RB(CLKGEN_VCXO_CLK_PM_CTRL, DIS_CLK_108, 1);
+
+	/* disable self-refresh since it interferes with suspend */
+	brcm_pm_set_ddr_timeout(0);
+}
+
+static void bcm7125_pm_resume(u32 flags)
+{
+	/* system PLLs */
+	BDEV_WR_F_RB(CLKGEN_VCXO_CLK_PM_CTRL, DIS_CLK_108, 0);
+	BDEV_WR_F_RB(CLKGEN_VCXO_CLK_PM_CTRL, DIS_CLK_216, 0);
+	BDEV_UNSET_RB(BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL, 0x07);
+	BDEV_SET_RB(BCHP_VCXO_CTL_MISC_VC0_CTRL, 0x04);
+	BDEV_UNSET_RB(BCHP_VCXO_CTL_MISC_VC0_CTRL, 0x0b);
+
+	/* PCI/EBI */
+	BDEV_UNSET_RB(BCHP_CLKGEN_HIF_CLK_PM_CTRL, 0x3c);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_PM_DIS_CHL_1, DIS_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_CLK_27_OUT_PM_CTRL, DIS_CLK_27_OUT, 0);
+	BDEV_WR_RB(BCHP_HIF_TOP_CTRL_PM_CTRL, 0x00);
+
+	brcm_ddr_phy_initialize();
+}
+
+/* There is no non-MoCA GENET on 7125, so any request for 'enet' clock is
+ * redirected to 'moca'
+ */
+static struct clk *bcm7125_pm_clk_get(struct device *dev, const char *id)
+{
+	if (!strncmp(id, "enet", 4)) {
+		if (strstr(id, "-wol"))
+			return brcm_pm_clk_find("moca-wol");
+		else
+			return brcm_pm_clk_find("moca");
+	}
+	return NULL;
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(usb, 7125),
+	DEF_BLOCK_PM_OP(sata, 7125),
+	DEF_BLOCK_PM_OP(network, 7125),
+	DEF_SYSTEM_PM_OP(7125),
+	.clk_get		= bcm7125_pm_clk_get,
+	.initialize		= brcm_ddr_phy_initialize,
+};
+#endif
+
+#if defined(CONFIG_BCM7340)
+
+static void bcm7340_pm_genet_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		/*
+		 * TODO: Stop HFB clock and switch to 27MHz if ACPI
+		 * detector is disabled
+		 */
+#if 0
+		/* TODO: on 1000Mbit link use 54MHz clock and MAIN PLL */
+		BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, MAIN_PLL, 1);
+		mdelay(1);
+		BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS,
+			CLOCK_SEL_CG_GENET, 1);
+#endif
+		/* switch to slower 27MHz clocks */
+		BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS,
+			CLOCK_SEL_CG_GENET, 0);
+
+		BDEV_SET_RB(BCHP_CLKGEN_GENET_CLK_PM_CTRL,
+		    BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_GMII_MASK|
+		    BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_216_MASK|
+		    BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_TX_MASK|
+		    BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_L2_INTR_MASK);
+		return;
+	}
+
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH4_PM_CTRL, PWRDN_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH4_PM_CTRL, ENB_CLOCKOUT_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH4_PM_CTRL, EN_CMLBUF_CH4, 0);
+	BDEV_SET_RB(BCHP_CLKGEN_GENET_CLK_PM_CTRL,
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_250_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_RX_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_TX_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_L2_INTR_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_HFB_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_25_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_GMII_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_54_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_108_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_216_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_27X_PM_MASK);
+}
+
+static void bcm7340_pm_genet_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		BDEV_UNSET_RB(BCHP_CLKGEN_GENET_CLK_PM_CTRL,
+		    BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_GMII_MASK|
+		    BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_HFB_MASK|
+		    BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_216_MASK|
+		    BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_TX_MASK|
+		    BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_L2_INTR_MASK);
+		/* switch to faster 54MHz clocks */
+		BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS,	CLOCK_SEL_CG_GENET, 1);
+		return;
+	}
+
+	BDEV_UNSET_RB(BCHP_CLKGEN_GENET_CLK_PM_CTRL,
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_250_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_RX_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_TX_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_L2_INTR_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_HFB_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_25_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_GMII_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_54_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_108_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_216_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_27X_PM_MASK);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH4_PM_CTRL, EN_CMLBUF_CH4, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH4_PM_CTRL, ENB_CLOCKOUT_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH4_PM_CTRL, PWRDN_CH, 0);
+}
+
+static void bcm7340_pm_moca_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (MOCA_WOL(flags)) {
+#if 0
+		/* TODO: on 1000Mbit link use 54MHz clock and MAIN PLL */
+		BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, MAIN_PLL, 1);
+		mdelay(1);
+		BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS, CLOCK_SEL_ENET_CG_MOCA,
+			1);
+		BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS, CLOCK_SEL_GMII_CG_MOCA,
+			0);
+#endif
+		/* switch to slower 27MHz clocks */
+		BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS, CLOCK_SEL_ENET_CG_MOCA,
+			0);
+		BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS, CLOCK_SEL_GMII_CG_MOCA,
+			1);
+	    BDEV_SET_RB(BCHP_CLKGEN_MOCA_CLK_PM_CTRL,
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_250_GENET_RGMII_MOCA_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_216_GENET_RGMII_CG_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_TX_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_L2_INTR_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_54_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_108_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_216_MASK);
+	    return;
+	}
+
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH1_PM_CTRL, PWRDN_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH1_PM_CTRL, ENB_CLOCKOUT_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH1_PM_CTRL, EN_CMLBUF_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH2_PM_CTRL, PWRDN_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH2_PM_CTRL, ENB_CLOCKOUT_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH2_PM_CTRL, EN_CMLBUF_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH3_PM_CTRL, PWRDN_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH3_PM_CTRL, ENB_CLOCKOUT_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH3_PM_CTRL, EN_CMLBUF_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH6_PM_CTRL, PWRDN_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH6_PM_CTRL, ENB_CLOCKOUT_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH6_PM_CTRL, EN_CMLBUF_CH6, 0);
+	BDEV_SET_RB(BCHP_CLKGEN_MOCA_CLK_PM_CTRL,
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_250_GENET_RGMII_MOCA_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_216_GENET_RGMII_CG_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_RX_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_TX_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_L2_INTR_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_HFB_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_GMII_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_27X_PM_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_54_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_108_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_216_MASK);
+}
+
+static void bcm7340_pm_moca_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (MOCA_WOL(flags)) {
+		BDEV_UNSET_RB(BCHP_CLKGEN_MOCA_CLK_PM_CTRL,
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_250_GENET_RGMII_MOCA_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_216_GENET_RGMII_CG_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_RX_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_TX_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_L2_INTR_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_HFB_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_GMII_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_27X_PM_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_54_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_108_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_216_MASK);
+
+	    /* Restore fast clocks */
+	    BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS, CLOCK_SEL_ENET_CG_MOCA, 1);
+	    BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS, CLOCK_SEL_GMII_CG_MOCA, 0);
+
+	    return;
+	}
+
+	BDEV_UNSET_RB(BCHP_CLKGEN_MOCA_CLK_PM_CTRL,
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_250_GENET_RGMII_MOCA_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_216_GENET_RGMII_CG_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_RX_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_TX_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_L2_INTR_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_HFB_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_GMII_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_27X_PM_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_54_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_108_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_216_MASK);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH6_PM_CTRL, EN_CMLBUF_CH6, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH6_PM_CTRL, ENB_CLOCKOUT_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH6_PM_CTRL, PWRDN_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH3_PM_CTRL, EN_CMLBUF_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH3_PM_CTRL, ENB_CLOCKOUT_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH3_PM_CTRL, PWRDN_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH2_PM_CTRL, EN_CMLBUF_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH2_PM_CTRL, ENB_CLOCKOUT_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH2_PM_CTRL, PWRDN_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH1_PM_CTRL, EN_CMLBUF_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH1_PM_CTRL, ENB_CLOCKOUT_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH1_PM_CTRL, PWRDN_CH, 0);
+}
+
+static void bcm7340_pm_usb_disable(u32 flags)
+{
+	/* reset and power down all 4 ports */
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, PHY_PWDNB, 0x0);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_IDDQ, 1);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_SOFT_RESETB, 0x0);
+
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, PLL_PWRDWNB, 0);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, XTAL_PWRDWNB, 0);
+	/* disable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB_CLK_PM_CTRL, DIS_CLK_216, 1);
+	BDEV_WR_F_RB(CLKGEN_USB_CLK_PM_CTRL, DIS_CLK_108, 1);
+	/* disable PLL */
+	BDEV_WR_F_RB(CLKGEN_PLLMAIN_CH4_PM_CTRL, PWRDN_CH4_PLLMAIN, 1);
+}
+
+static void bcm7340_pm_usb_enable(u32 flags)
+{
+	BDEV_WR_F_RB(CLKGEN_PLLMAIN_CH4_PM_CTRL, PWRDN_CH4_PLLMAIN, 0);
+	BDEV_WR_F_RB(CLKGEN_USB_CLK_PM_CTRL, DIS_CLK_108, 0);
+	BDEV_WR_F_RB(CLKGEN_USB_CLK_PM_CTRL, DIS_CLK_216, 0);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, PLL_PWRDWNB, 1);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, XTAL_PWRDWNB, 1);
+
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_SOFT_RESETB, 0xF);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_IDDQ, 0);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, PHY_PWDNB, 0xF);
+}
+
+static void bcm7340_pm_network_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ANY_WOL(flags))
+		return;
+
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CTRL, DRESET, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CTRL, ARESET, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CTRL, PWRDN, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CTRL, PWRDN_LDO, 1);
+}
+
+static void bcm7340_pm_network_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ANY_WOL(flags))
+		return;
+
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CTRL, PWRDN_LDO, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CTRL, PWRDN, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CTRL, ARESET, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CTRL, DRESET, 0);
+}
+
+static void bcm7340_pm_suspend(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	/* PCI/EBI */
+	BDEV_WR_F_RB(CLKGEN_PAD_CLK_PM_CTRL, DIS_CLK_33_27_PCI, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMAIN_CH5_PM_CTRL, PWRDN_CH5_PLLMAIN, 1);
+	BDEV_WR_F_RB(CLKGEN_CG_CLK_PM_CTRL, DIS_CLK_81, 1);
+	BDEV_WR_F_RB(CLKGEN_CG_CLK_PM_CTRL, DIS_CLK_27, 1);
+	BDEV_WR_F_RB(CLKGEN_CG_CLK_PM_CTRL, DIS_CLK_54, 1);
+	BDEV_WR_F_RB(CLKGEN_CG_CLK_PM_CTRL, DIS_CLK_216_CG, 1);
+	BDEV_WR_F_RB(CLKGEN_HIF_CLK_PM_CTRL, DIS_CLK_SPI, 1);
+
+	/* system PLLs */
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, DRESET, 1);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, ARESET, 1);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, POWERDOWN, 1);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC1_CTRL, DRESET, 1);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC1_CTRL, ARESET, 1);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC1_CTRL, POWERDOWN, 1);
+
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_PM_CH2_CTRL, EN_CMLBUF, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_PM_CH2_CTRL, PWRDN, 1);
+
+	BDEV_WR_F_RB(VCXO_CTL_MISC_RAP_AVD_PLL_CTRL, RESET, 1);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_RAP_AVD_PLL_CTRL, POWERDOWN, 1);
+
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_CTRL, ENB_CLOCKOUT, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_CTRL, DRESET, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_CTRL, ARESET, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_CTRL, PWRDN, 1);
+
+	BDEV_WR_F_RB(CLKGEN_VCXO_CLK_PM_CTRL, DIS_CLK_216, 1);
+	BDEV_WR_F_RB(CLKGEN_VCXO_CLK_PM_CTRL, DIS_CLK_108, 1);
+
+	/* disable self-refresh since it interferes with suspend */
+	brcm_pm_set_ddr_timeout(0);
+}
+
+static void bcm7340_pm_resume(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	/* system PLLs */
+	BDEV_WR_F_RB(CLKGEN_VCXO_CLK_PM_CTRL, DIS_CLK_108, 0);
+	BDEV_WR_F_RB(CLKGEN_VCXO_CLK_PM_CTRL, DIS_CLK_216, 0);
+
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_CTRL, PWRDN, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_CTRL, ARESET, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_CTRL, DRESET, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_CTRL, ENB_CLOCKOUT, 0);
+
+	BDEV_WR_F_RB(VCXO_CTL_MISC_RAP_AVD_PLL_CTRL, RESET, 0);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_RAP_AVD_PLL_CTRL, POWERDOWN, 0);
+
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_PM_CH2_CTRL, PWRDN, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_PM_CH2_CTRL, EN_CMLBUF, 0);
+
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC1_CTRL, POWERDOWN, 0);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC1_CTRL, ARESET, 0);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC1_CTRL, DRESET, 0);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, POWERDOWN, 0);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, ARESET, 0);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, DRESET, 0);
+
+	/* PCI/EBI */
+	BDEV_WR_F_RB(CLKGEN_HIF_CLK_PM_CTRL, DIS_CLK_SPI, 0);
+	BDEV_WR_F_RB(CLKGEN_CG_CLK_PM_CTRL, DIS_CLK_216_CG, 0);
+	BDEV_WR_F_RB(CLKGEN_CG_CLK_PM_CTRL, DIS_CLK_54, 0);
+	BDEV_WR_F_RB(CLKGEN_CG_CLK_PM_CTRL, DIS_CLK_27, 0);
+	BDEV_WR_F_RB(CLKGEN_CG_CLK_PM_CTRL, DIS_CLK_81, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMAIN_CH5_PM_CTRL, PWRDN_CH5_PLLMAIN, 0);
+	BDEV_WR_F_RB(CLKGEN_PAD_CLK_PM_CTRL, DIS_CLK_33_27_PCI, 0);
+
+	brcm_ddr_phy_initialize();
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(usb, 7340),
+	DEF_BLOCK_PM_OP(moca, 7340),
+	DEF_BLOCK_PM_OP(genet, 7340),
+	DEF_BLOCK_PM_OP(network, 7340),
+	DEF_SYSTEM_PM_OP(7340),
+	.clk_get		= brcm_pm_clk_get,
+	.initialize		= brcm_ddr_phy_initialize,
+};
+#endif
+
+#if defined(CONFIG_BCM7408)
+static void bcm7408_pm_network_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	/*
+	 * 7408B0 does not support MoCA WOL due to a h/w bug. The
+	 * following code is added in case the bug is fixed in the next
+	 * revision
+	 * http://jira.broadcom.com/browse/HW7408-186
+	 */
+	if (MOCA_WOL(flags)) {
+		BDEV_WR_F_RB(CLK_MISC, MOCA_ENET_CLK_SEL, 1);
+		BDEV_WR_F_RB(CLK_MISC, MOCA_ENET_GMII_TX_CLK_SEL, 1);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL,
+			DIS_GENET_RGMII_216M_CLK, 1);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL,
+			DIS_MOCA_ENET_UNIMAC_SYS_TX_27_108M_CLK, 1);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL,
+			DIS_MOCA_ENET_L2_INTR_27_108M_CLK, 1);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL,
+			DIS_MOCA_ENET_GMII_TX_27_108M_CLK, 1);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL, DIS_MOCA_54M_CLK, 1);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL, DIS_216M_CLK, 1);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL, DIS_108M_CLK, 1);
+		return;
+	}
+	BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL, DIS_MOCA_ENET_HFB_27_108M_CLK, 1);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_3, DIS_CH, 1);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_3, EN_CMLBUF, 0);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_4, DIS_CH, 1);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_4, EN_CMLBUF, 0);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_5, DIS_CH, 1);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_5, EN_CMLBUF, 0);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_6, DIS_CH, 1);
+	BDEV_SET_RB(BCHP_CLK_MOCA_CLK_PM_CTRL, 0x6ab);
+}
+
+static void bcm7408_pm_network_enable(u32 flags)
+{
+	if (MOCA_WOL(flags)) {
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL,
+			DIS_GENET_RGMII_216M_CLK, 0);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL,
+			DIS_MOCA_ENET_UNIMAC_SYS_TX_27_108M_CLK, 0);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL,
+			DIS_MOCA_ENET_L2_INTR_27_108M_CLK, 0);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL,
+			DIS_MOCA_ENET_GMII_TX_27_108M_CLK, 0);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL, DIS_MOCA_54M_CLK, 0);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL, DIS_216M_CLK, 0);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL, DIS_108M_CLK, 0);
+		BDEV_WR_F_RB(CLK_MISC, MOCA_ENET_CLK_SEL, 0);
+		BDEV_WR_F_RB(CLK_MISC, MOCA_ENET_GMII_TX_CLK_SEL, 0);
+		return;
+	}
+	BDEV_UNSET_RB(BCHP_CLK_MOCA_CLK_PM_CTRL, 0x6ab);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_6, DIS_CH, 0);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_5, DIS_CH, 0);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_5, EN_CMLBUF, 1);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_4, DIS_CH, 0);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_4, EN_CMLBUF, 1);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_3, DIS_CH, 0);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_3, EN_CMLBUF, 1);
+	BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL, DIS_MOCA_ENET_HFB_27_108M_CLK, 0);
+}
+
+static void bcm7408_pm_usb_disable(u32 flags)
+{
+	/* reset and power down all 4 ports */
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, PHY_PWDNB, 0x0);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_IDDQ, 1);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_SOFT_RESETB, 0x0);
+
+	/* disable the clocks */
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, PLL_PWRDWNB, 0);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, XTAL_PWRDWNB, 0);
+	BDEV_SET_RB(BCHP_CLK_USB_CLK_PM_CTRL,
+		BCHP_CLK_USB_CLK_PM_CTRL_DIS_54M_CLK_MASK|
+		BCHP_CLK_USB_CLK_PM_CTRL_DIS_108M_CLK_MASK|
+		BCHP_CLK_USB_CLK_PM_CTRL_DIS_216M_CLK_MASK);
+
+	/* disable PLL */
+	BDEV_WR_F_RB(CLK_SYS_PLL_0_4, DIS_CH, 1);
+	BDEV_WR_F_RB(CLK_SYS_PLL_0_4, EN_CMLBUF, 0);
+}
+
+static void bcm7408_pm_usb_enable(u32 flags)
+{
+	/* enable PLL */
+	BDEV_WR_F_RB(CLK_SYS_PLL_0_4, EN_CMLBUF, 1);
+	BDEV_WR_F_RB(CLK_SYS_PLL_0_4, DIS_CH, 0);
+	/* enable the clocks */
+	BDEV_UNSET_RB(BCHP_CLK_USB_CLK_PM_CTRL,
+		BCHP_CLK_USB_CLK_PM_CTRL_DIS_54M_CLK_MASK|
+		BCHP_CLK_USB_CLK_PM_CTRL_DIS_108M_CLK_MASK|
+		BCHP_CLK_USB_CLK_PM_CTRL_DIS_216M_CLK_MASK);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, XTAL_PWRDWNB, 1);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, PLL_PWRDWNB, 1);
+
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_SOFT_RESETB, 0xE);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_IDDQ, 0);
+	/* power up all 4 ports */
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, PHY_PWDNB, 0xF);
+}
+
+static void bcm7408_pm_suspend(u32 flags)
+{
+	/* UART */
+	if (!(brcm_pm_standby_flags & BRCM_STANDBY_VERBOSE)) {
+		BDEV_WR_F_RB(CLK_SUN_27M_CLK_PM_CTRL,
+			DIS_SUN_27M_CLK, 1);
+		BDEV_WR_F_RB(CLK_SUN_UART_CLK_PM_CTRL,
+			DIS_SUN_UART_108M_CLK, 1);
+	}
+	/* PAD clocks */
+	BDEV_WR_F_RB(CLK_MISC, VCXOA_OUTCLK_ENABLE, 0);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_PM_DIS_CHL_1, DIS_CH, 1);
+
+	/* system PLLs */
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, DRESET, 1);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, ARESET, 1);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, POWERDOWN, 1);
+	BDEV_WR_F_RB(CLK_THIRD_OT_CONTROL_1,
+		CML_2_N_P_EN, 1);
+	BDEV_WR_F_RB(CLK_THIRD_OT_CONTROL_1,
+		FREQ_DOUBLER_POWER_DOWN, 1);
+
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_CTRL, DRESET, 1);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_CTRL, ARESET, 1);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_CTRL, POWERDOWN, 1);
+
+	/* MEMC0 */
+	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PAD_CNTRL,
+		IDDQ_MODE_ON_SELFREF, 0);
+	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PAD_CNTRL,
+		HIZ_ON_SELFREF, 1);
+	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PAD_CNTRL,
+		DEVCLK_OFF_ON_SELFREF, 1);
+	BDEV_WR_RB(BCHP_DDR23_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL, 0x132);
+	BDEV_SET_RB(BCHP_DDR23_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL, 0xfffff);
+	BDEV_SET_RB(BCHP_DDR23_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL, 0xfffff);
+
+}
+
+static void bcm7408_pm_resume(u32 flags)
+{
+	/* system PLLs */
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_CTRL, DRESET, 0);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_CTRL, ARESET, 0);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_CTRL, POWERDOWN, 0);
+
+	BDEV_WR_F_RB(CLK_THIRD_OT_CONTROL_1,
+		CML_2_N_P_EN, 0);
+	BDEV_WR_F_RB(CLK_THIRD_OT_CONTROL_1,
+		FREQ_DOUBLER_POWER_DOWN, 0);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, DRESET, 0);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, ARESET, 0);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, POWERDOWN, 0);
+
+	/* PAD clocks */
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_PM_DIS_CHL_1, DIS_CH, 0);
+	BDEV_WR_F_RB(CLK_MISC, VCXOA_OUTCLK_ENABLE, 1);
+
+	/* UART */
+	if (!(brcm_pm_standby_flags & BRCM_STANDBY_VERBOSE)) {
+		BDEV_WR_F_RB(CLK_SUN_UART_CLK_PM_CTRL,
+			DIS_SUN_UART_108M_CLK, 0);
+		BDEV_WR_F_RB(CLK_SUN_27M_CLK_PM_CTRL,
+			DIS_SUN_27M_CLK, 0);
+	}
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(network, 7408),
+	DEF_BLOCK_PM_OP(usb, 7408),
+	DEF_SYSTEM_PM_OP(7408),
+};
+#endif
+
+#if defined(CONFIG_BCM7468)
+
+static void bcm7468_pm_genet_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		/* switch to slower 27MHz clocks */
+		BDEV_WR_F_RB(CLK_MISC, GENET_CLK_SEL, 1);
+		BDEV_WR_F_RB(CLK_MISC, GENET_GMII_TX_CLK_SEL, 1);
+		BDEV_SET_RB(BCHP_CLK_GENET_CLK_PM_CTRL, 0x503);
+		return;
+	}
+
+	BDEV_WR_RB(BCHP_CLK_SYS_PLL_1_4, 1);
+	BDEV_SET_RB(BCHP_CLK_GENET_CLK_PM_CTRL, 0x767);
+}
+
+static void bcm7468_pm_genet_enable(u32 flags)
+{
+	if (ENET_WOL(flags)) {
+		BDEV_UNSET_RB(BCHP_CLK_GENET_CLK_PM_CTRL, 0x503);
+		BDEV_WR_F_RB(CLK_MISC, GENET_CLK_SEL, 0);
+		BDEV_WR_F_RB(CLK_MISC, GENET_GMII_TX_CLK_SEL, 0);
+		return;
+	}
+
+	BDEV_UNSET_RB(BCHP_CLK_GENET_CLK_PM_CTRL, 0x767);
+	BDEV_WR_RB(BCHP_CLK_SYS_PLL_1_4, 0);
+}
+
+static void bcm7468_pm_usb_disable(u32 flags)
+{
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, PHY_PWDNB, 0x00);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_IDDQ, 1);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_SOFT_RESETB, 0x00);
+
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, PLL_PWRDWNB, 0);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, XTAL_PWRDWNB, 0);
+	BDEV_SET_RB(BCHP_CLK_USB_CLK_PM_CTRL, 0x07);
+}
+
+static void bcm7468_pm_usb_enable(u32 flags)
+{
+	BDEV_UNSET_RB(BCHP_CLK_USB_CLK_PM_CTRL, 0x07);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, XTAL_PWRDWNB, 1);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, PLL_PWRDWNB, 1);
+
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_SOFT_RESETB, 0xF);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_IDDQ, 0);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, PHY_PWDNB, 0xF);
+}
+
+static void bcm7468_pm_suspend(u32 flags)
+{
+	/* SDIO */
+	BDEV_WR_F_RB(CLK_HIF_SDIO_CLK_PM_CTRL, DIS_HIF_SDIO_48M_CLK, 1);
+	BDEV_WR_RB(BCHP_CLK_SYS_PLL_1_1, 1);
+
+	/* EBI */
+	BDEV_SET_RB(BCHP_HIF_TOP_CTRL_PM_CTRL, 0x2ff0);
+
+	/* system PLLs */
+	BDEV_WR_RB(BCHP_CLK_SYS_PLL_0_3, 0x02);
+
+	if (!ENET_WOL(flags))
+		/* this PLL is needed for EPHY */
+		BDEV_SET_RB(BCHP_CLK_SYS_PLL_1_CTRL, 0x83);
+
+	BDEV_WR_RB(BCHP_VCXO_CTL_MISC_AC1_CTRL, 0x06);
+	BDEV_SET_RB(BCHP_VCXO_CTL_MISC_VC0_CTRL, 0x0b);
+}
+
+static void bcm7468_pm_resume(u32 flags)
+{
+	/* system PLLs */
+	BDEV_UNSET_RB(BCHP_VCXO_CTL_MISC_VC0_CTRL, 0x0b);
+	BDEV_WR_RB(BCHP_VCXO_CTL_MISC_AC1_CTRL, 0x00);
+	BDEV_UNSET_RB(BCHP_CLK_SYS_PLL_1_CTRL, 0x83);
+	BDEV_WR_RB(BCHP_CLK_SYS_PLL_0_3, 0x01);
+
+	/* EBI */
+	BDEV_UNSET_RB(BCHP_HIF_TOP_CTRL_PM_CTRL, 0x2ff0);
+
+	/* SDIO */
+	BDEV_WR_RB(BCHP_CLK_SYS_PLL_1_1, 0);
+	BDEV_WR_F_RB(CLK_HIF_SDIO_CLK_PM_CTRL, DIS_HIF_SDIO_48M_CLK, 0);
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(usb, 7468),
+	DEF_BLOCK_PM_OP(genet, 7468),
+	DEF_SYSTEM_PM_OP(7468),
+};
+#endif
+
+/* 40nm chips start here */
+
+#if	defined(CONFIG_BCM7228) || \
+	defined(CONFIG_BCM7425) || \
+	defined(CONFIG_BCM7429) || \
+	defined(CONFIG_BCM7435) || \
+	defined(CONFIG_BCM7346) || \
+	defined(CONFIG_BCM7231) || \
+	defined(CONFIG_BCM7552) || \
+	defined(CONFIG_BCM7584) || \
+	defined(CONFIG_BCM7563) || \
+	defined(CONFIG_BCM7344) || \
+	defined(CONFIG_BCM7358) || \
+	defined(CONFIG_BCM7360) || \
+	defined(CONFIG_BCM7362)
+static __maybe_unused int mem_power_down = 1;
+
+#undef PLL_CH_ENA
+#undef PLL_CH_DIS
+#undef PLL_ENA
+#undef PLL_DIS
+
+#define PLL_CH_DIS(pll, ch) do { \
+	BDEV_WR_F_RB(pll ## _CH_ ## ch, POST_DIVIDER_HOLD_CH ## ch, 1); \
+	BDEV_WR_F_RB(pll ## _CH_ ## ch, CLOCK_DIS_CH ## ch, 1); \
+} while (0)
+
+#define PLL_CH_ENA(pll, ch) do { \
+	BDEV_WR_F_RB(pll ## _CH_ ## ch, CLOCK_DIS_CH ## ch, 0); \
+	BDEV_WR_F_RB(pll ## _CH_ ## ch, POST_DIVIDER_HOLD_CH ## ch, 0); \
+} while (0)
+
+#define PLL_DIS(pll) do { \
+	BDEV_WR_F_RB(pll ## _RESET, RESETD, 1); \
+	BDEV_WR_F_RB(pll ## _RESET, RESETA, 1); \
+	BDEV_WR_F_RB(pll ## _PWRDN, PWRDN_PLL, 1); \
+} while (0)
+
+#define PLL_ENA(pll) do { \
+	BDEV_WR_F_RB(pll ## _PWRDN, PWRDN_PLL, 0); \
+	BDEV_WR_F_RB(pll ## _RESET, RESETA, 0); \
+	BDEV_WR_F_RB(pll ## _RESET, RESETD, 0); \
+	do { \
+		mdelay(1); \
+	} while (!BDEV_RD_F(pll ## _LOCK_STATUS, LOCK)); \
+} while (0)
+
+
+/* IMPORTANT: must be done in TWO steps per RDB note */
+#define POWER_UP_MEMORY_3(core, mask, inst) \
+do { \
+	BDEV_WR_F_RB(CLKGEN_ ## core ## _POWER_SWITCH_MEMORY ## inst,\
+		mask ## _POWER_SWITCH_MEMORY ## inst, 2); \
+	udelay(10); \
+	BDEV_WR_F_RB(CLKGEN_ ## core ## _POWER_SWITCH_MEMORY ## inst,\
+		mask ## _POWER_SWITCH_MEMORY ## inst, 0); \
+} while (0)
+
+#define POWER_UP_MEMORY_1(core) POWER_UP_MEMORY_3(core, core, \
+	)
+#define POWER_UP_MEMORY_1ii(core) \
+	POWER_UP_MEMORY_2(core ## _INST, core ## _INST)
+#define POWER_UP_MEMORY_2(core, mask) POWER_UP_MEMORY_3(core, mask, \
+	)
+#define POWER_UP_MEMORY_2i(core, mask) POWER_UP_MEMORY_3(core ## _INST, mask, \
+	)
+#define POWER_UP_MEMORY_3i(core, mask, inst) \
+	POWER_UP_MEMORY_3(core ## _INST, mask, inst)
+
+#define SRAM_OFF_3(core, mask, inst) \
+do { \
+	if (mem_power_down) \
+		BDEV_WR_F_RB( \
+			CLKGEN_ ## core ## _POWER_SWITCH_MEMORY ## inst, \
+			mask ## _POWER_SWITCH_MEMORY ## inst, 3); \
+	else \
+		BDEV_WR_F_RB( \
+			CLKGEN_ ## core ## _MEMORY_STANDBY_ENABLE ## inst, \
+			mask ## _MEMORY_STANDBY_ENABLE ## inst, 1); \
+} while (0)
+
+#define SRAM_OFF_1i(core) SRAM_OFF_3(core ## _INST, core, \
+	)
+#define SRAM_OFF_1(core) SRAM_OFF_3(core, core, \
+	)
+#define SRAM_OFF_2i(core, mask) SRAM_OFF_3(core ## _INST, mask, \
+	)
+#define SRAM_OFF_3i(core, mask, inst) SRAM_OFF_3(core ## _INST, mask, inst)
+#define SRAM_OFF_2(core, mask) SRAM_OFF_3(core, mask, \
+	)
+
+#define SRAM_ON_3(core, mask, inst) \
+do { \
+	if (mem_power_down) \
+		POWER_UP_MEMORY_3(core, mask, inst); \
+	else \
+	BDEV_WR_F_RB(CLKGEN_ ## core ## _MEMORY_STANDBY_ENABLE ## inst, \
+		mask ## _MEMORY_STANDBY_ENABLE ## inst, 0); \
+} while (0)
+
+#define SRAM_ON_1i(core) SRAM_ON_3(core ## _INST, core, \
+	)
+#define SRAM_ON_1(core) SRAM_ON_3(core, core, \
+	)
+#define SRAM_ON_2i(core, mask) SRAM_ON_3(core ## _INST, mask, \
+	)
+#define SRAM_ON_2(core, mask) SRAM_ON_3(core, mask, \
+	)
+#define SRAM_ON_3i(core, mask, inst) SRAM_ON_3(core ## _INST, mask, inst)
+#endif
+
+/******************************************************************
+ *   USB recovery after S3 warm boot
+ * These parameters are mostly configured by CFE on cold boot, some
+ * of them are set during HC reset code which we do not execute on
+ * warm boot because it re-allocates memory.
+ * The code will probably work on all 40nm chips, but we will see...
+ ******************************************************************/
+static u32 usb_cfg[4];
+
+static __maybe_unused void bcm40nm_pm_usb_disable_s3(void)
+{
+	if (!brcm_pm_deep_sleep())
+		return;
+#ifdef BCHP_USB_CTRL_SETUP
+	usb_cfg[0] = BDEV_RD(BCHP_USB_CTRL_SETUP);
+	usb_cfg[1] = BDEV_RD(BCHP_USB_CTRL_EBRIDGE);
+#endif
+#ifdef BCHP_USB1_CTRL_SETUP
+	if (BRCM_PROD_ID() != 0x74285) {
+		usb_cfg[2] = BDEV_RD(BCHP_USB1_CTRL_SETUP);
+		usb_cfg[3] = BDEV_RD(BCHP_USB1_CTRL_EBRIDGE);
+	}
+#endif
+}
+
+static __maybe_unused void bcm40nm_pm_usb_enable_s3(void)
+{
+	if (!brcm_pm_deep_sleep())
+		return;
+	printk(KERN_DEBUG "Restoring USB HC state from S3 suspend\n");
+#ifdef BCHP_USB_CTRL_SETUP
+	BDEV_WR_RB(BCHP_USB_CTRL_SETUP, usb_cfg[0]);
+	BDEV_WR_RB(BCHP_USB_CTRL_EBRIDGE, usb_cfg[1]);
+#endif
+#ifdef BCHP_USB1_CTRL_SETUP
+	if (BRCM_PROD_ID() != 0x74285) {
+		BDEV_WR_RB(BCHP_USB1_CTRL_SETUP, usb_cfg[2]);
+		BDEV_WR_RB(BCHP_USB1_CTRL_EBRIDGE, usb_cfg[3]);
+	}
+#endif
+	mdelay(500);
+	bchip_usb_init();
+}
+
+#if defined(CONFIG_BCM7425) || defined(CONFIG_BCM7429) \
+	|| defined(CONFIG_BCM7346) || defined(CONFIG_BCM7435)
+
+#define BRCM_BASE_CLK		3600 /* base clock in MHz */
+
+/*
+ * work around RDB name inconsistencies.
+ */
+#if defined(BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK)
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_MASK \
+	BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_SHIFT \
+	BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT
+#endif
+
+#if defined(BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK)
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_MASK \
+	BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_SHIFT \
+	BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT
+#endif
+
+#if defined(BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB_SCB_CLOCK_ENABLE_MASK)
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK \
+	BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB_SCB_CLOCK_ENABLE_MASK
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT \
+	BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB_SCB_CLOCK_ENABLE_SHIFT
+
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK \
+	BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB_108_CLOCK_ENABLE_MASK
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT \
+	BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB_108_CLOCK_ENABLE_SHIFT
+#endif
+
+#if defined(BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE)
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE \
+	BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_MASK \
+	BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_MASK
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_SHIFT \
+	BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_SHIFT
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_MASK \
+	BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_MASK
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_SHIFT \
+	BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_SHIFT
+#endif
+
+static void bcm40nm_pm_usb_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	bcm40nm_pm_usb_disable_s3();
+
+	/* USB0 */
+	/* power down USB PHY */
+	BDEV_SET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+	/* power down USB PLL */
+	BDEV_UNSET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+
+	SRAM_OFF_1i(USB0);
+
+	/* disable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_DISABLE,
+		DISABLE_USB0_54_MDIO_CLOCK, 1);
+
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 0);
+
+	/* USB1 */
+	/* power down USB PHY */
+	if (BRCM_PROD_ID() != 0x74285) {
+		BDEV_SET(BCHP_USB1_CTRL_PLL_CTL,
+			BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+		/* power down USB PLL */
+		BDEV_UNSET(BCHP_USB1_CTRL_PLL_CTL,
+			BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+	}
+
+	SRAM_OFF_1i(USB1);
+
+	/* disable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_DISABLE,
+		DISABLE_USB1_54_MDIO_CLOCK, 1);
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_ENABLE, USB1_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_ENABLE, USB1_108_CLOCK_ENABLE, 0);
+
+#if defined(BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4)
+	/* power down PLL */
+	PLL_CH_DIS(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 4);
+#endif
+}
+
+static void bcm40nm_pm_usb_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+	/* power up PLL */
+#if defined(BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4)
+	PLL_CH_ENA(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 4);
+#endif
+
+	/* USB0 */
+	/* enable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_DISABLE,
+		DISABLE_USB0_54_MDIO_CLOCK, 0);
+
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 1);
+
+	SRAM_ON_1i(USB0);
+
+	/* power up USB PLL */
+	BDEV_SET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+	/* power up USB PHY */
+	BDEV_UNSET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+
+	/* USB1 */
+	/* enable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_DISABLE,
+		DISABLE_USB1_54_MDIO_CLOCK, 0);
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_ENABLE, USB1_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_ENABLE, USB1_108_CLOCK_ENABLE, 1);
+
+	SRAM_ON_1i(USB1);
+
+	/* power up USB PLL */
+	if (BRCM_PROD_ID() != 0x74285) {
+		BDEV_SET(BCHP_USB1_CTRL_PLL_CTL,
+			BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+		/* power up USB PHY */
+		BDEV_UNSET(BCHP_USB1_CTRL_PLL_CTL,
+			BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+	}
+
+	bcm40nm_pm_usb_enable_s3();
+}
+
+/* These are not defined in the RDB headers for any 40nm chips. */
+#define SATA_TOP_CTRL_PHY_CTRL_1_DIS_HW_SLUMBER_MASK	BIT(8)
+#define SATA_TOP_CTRL_PHY_CTRL_2_SW_TX0_SLUMBER_MASK	BIT(12)
+#define SATA_TOP_CTRL_PHY_CTRL_3_SW_TX1_SLUMBER_MASK	BIT(12)
+
+static void bcm40nm_pm_sata_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	/* put PHY into slumber mode */
+	BDEV_SET(BCHP_SATA_TOP_CTRL_PHY_CTRL_1,
+		SATA_TOP_CTRL_PHY_CTRL_1_DIS_HW_SLUMBER_MASK);
+	BDEV_SET(BCHP_SATA_TOP_CTRL_PHY_CTRL_2,
+		SATA_TOP_CTRL_PHY_CTRL_2_SW_TX0_SLUMBER_MASK);
+	BDEV_SET(BCHP_SATA_TOP_CTRL_PHY_CTRL_3,
+		SATA_TOP_CTRL_PHY_CTRL_3_SW_TX1_SLUMBER_MASK);
+
+	SRAM_OFF_2i(SATA3_TOP, SATA3);
+
+	/* gate the clocks */
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE,
+		SATA3_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE,
+		SATA3_108_CLOCK_ENABLE, 0);
+#if !(defined(CONFIG_BCM7429B0) || defined(CONFIG_BCM7435B0))
+	BDEV_WR_F_RB(CLKGEN_SATA3_INST_CLOCK_DISABLE,
+		DISABLE_27_FUNC_CLK_30, 1);
+#endif
+}
+
+static void bcm40nm_pm_sata_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	/* reenable the clocks */
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE,
+		SATA3_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE,
+		SATA3_108_CLOCK_ENABLE, 1);
+#if !(defined(CONFIG_BCM7429B0) || defined(CONFIG_BCM7435B0))
+	BDEV_WR_F_RB(CLKGEN_SATA3_INST_CLOCK_DISABLE,
+		DISABLE_27_FUNC_CLK_30, 0);
+#endif
+
+	SRAM_ON_2i(SATA3_TOP, SATA3);
+
+	/* take PHY out from slumber */
+	BDEV_UNSET(BCHP_SATA_TOP_CTRL_PHY_CTRL_3,
+		SATA_TOP_CTRL_PHY_CTRL_3_SW_TX1_SLUMBER_MASK);
+	BDEV_UNSET(BCHP_SATA_TOP_CTRL_PHY_CTRL_2,
+		SATA_TOP_CTRL_PHY_CTRL_2_SW_TX0_SLUMBER_MASK);
+	BDEV_UNSET(BCHP_SATA_TOP_CTRL_PHY_CTRL_1,
+		SATA_TOP_CTRL_PHY_CTRL_1_DIS_HW_SLUMBER_MASK);
+}
+
+/* If GENET_1 uses the RGMII_0 pad which is controlled by GENET_0's
+ * clocks, then we need to make sure we do not disable that clock
+ */
+static inline unsigned int genet_needs_clk_250(void)
+{
+	u32 mac_select = 0;
+
+#ifdef BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_genet_mac_select_MASK
+	mac_select = BDEV_RD_F(SUN_TOP_CTRL_GENERAL_CTRL_0,
+			mii_genet_mac_select);
+#endif
+	/* GENET_1 does not use the RGMII_0 pad */
+	if (mac_select == 0)
+		return 0;
+
+	/* MoCA and internal PHY do not use the RGMII pad */
+	switch (genet_pdata[1].phy_type) {
+	case BRCM_PHY_TYPE_INT:
+	case BRCM_PHY_TYPE_MOCA:
+		return 0;
+	default:
+		return 1;
+	}
+}
+
+static void bcm40nm_pm_genet_disable(u32 flags)
+{
+	unsigned int __maybe_unused needs_clk_250 = genet_needs_clk_250();
+	PRINT_PM_CALLBACK;
+
+#if defined(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A)
+	SRAM_OFF_3i(DUAL_GENET_TOP_DUAL_RGMII, GENET0, _A);
+#endif
+
+#if defined(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0)
+	if (ENET_WOL(flags)) {
+		/* switch to slow clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0,
+		    GENET0_CLOCK_SELECT_GENET0, 1);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0,
+		    GENET0_GMII_CLOCK_SELECT_GENET0, 1);
+
+		/*
+		 * Do not clear GENET0_L2INTR_CLOCK_ENABLE - it screws up
+		 * receiver after resume !!!
+		 */
+		/* 250, EEE, UNIMAC-TX */
+		BDEV_UNSET(
+		 BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0,
+		    0x106);
+	} else {
+		/* every clock except AON */
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		    0xe);
+
+		/* Every genet0 clock except 108 or 250 for RGMII */
+		if (!needs_clk_250)
+			BDEV_UNSET(
+			  BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0,
+			  0x1fe);
+		else
+			BDEV_UNSET(
+			  BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0,
+			  0x1fc);
+	}
+
+#elif defined(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0)
+
+	if (ENET_WOL(flags)) {
+		/* switch to slow clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0,
+		    GENET0_CLOCK_SELECT_GENET0, 1);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0,
+		    GENET0_GMII_CLOCK_SELECT_GENET0, 1);
+		/*
+		 * Do not clear GENET0_L2INTR_CLOCK_ENABLE - it screws up
+		 * receiver after resume !!!
+		 */
+		/* 250, EEE, UNIMAC-TX */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0,
+		    0x106);
+	} else {
+		/* every clock except AON */
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0,
+		    0x1e);
+
+		/* Every genet0 clock except 108 or 250 */
+		if (!needs_clk_250)
+			BDEV_UNSET(
+			  BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0,
+			  0x1fe);
+		else
+			BDEV_UNSET(
+			  BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0,
+			  0x1fc);
+	}
+#else
+
+	if (ENET_WOL(flags)) {
+		/* switch to slow clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT,
+		    GENET0_CLOCK_SELECT, 1);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT,
+		    GENET0_GMII_CLOCK_SELECT, 1);
+
+		/*
+		 * Do not clear GENET0_L2INTR_CLOCK_ENABLE - it screws up
+		 * receiver after resume !!!
+		 */
+		/* 250, EEE, UNIMAC-TX */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		    0x43); /* used to be 0x53 */
+	} else {
+		/* system slow clock, pm clock */
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		    3);
+
+		/* Every gnet0 clock */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		    0x7F);
+	}
+#endif
+}
+
+static void bcm40nm_pm_genet_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+#if defined(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A)
+	SRAM_ON_3i(DUAL_GENET_TOP_DUAL_RGMII, GENET0, _A);
+#endif
+
+#if defined(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0)
+	if (ENET_WOL(flags)) {
+		/* switch to fast clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0,
+		    GENET0_CLOCK_SELECT_GENET0, 0);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0,
+		    GENET0_GMII_CLOCK_SELECT_GENET0, 0);
+
+		/* 250, EEE, UNIMAC-TX */
+		BDEV_SET(
+		 BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0,
+		    0x106);
+	} else {
+		/* every genet0 clock */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		    0xf);
+
+		/* Every genet0 clock */
+		BDEV_SET(
+		 BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0,
+		    0x1ff);
+	}
+#elif defined(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0)
+	if (ENET_WOL(flags)) {
+		/* switch to fast clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0,
+		    GENET0_CLOCK_SELECT_GENET0, 0);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0,
+		    GENET0_GMII_CLOCK_SELECT_GENET0, 0);
+		/*
+		 * Do not clear GENET0_L2INTR_CLOCK_ENABLE - it screws up
+		 * receiver after resume !!!
+		 */
+		/* 250, EEE, UNIMAC-TX */
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0,
+		    0x106);
+	} else {
+		/* every genet0 clock */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0,
+		    0x1f);
+
+		/* Every genet0 clock */
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0,
+		    0x1ff);
+	}
+#else
+	if (ENET_WOL(flags)) {
+		/* switch to fast clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT,
+		    GENET0_CLOCK_SELECT, 0);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT,
+		    GENET0_GMII_CLOCK_SELECT, 0);
+
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		    0x43);
+	} else {
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		    3);
+
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		    0x7F);
+	}
+#endif
+
+}
+
+static void bcm40nm_pm_genet1_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+#if defined(CONFIG_BCM7425)
+	if (mem_power_down)
+		/* power down memory */
+	    BDEV_WR_F_RB(
+		CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_B,
+		GENET1_POWER_SWITCH_MEMORY_B, 3);
+	else
+		/* memory to standby */
+	    BDEV_WR_F_RB(
+		CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A,
+		GENET1_MEMORY_STANDBY_ENABLE_A, 1);
+#endif
+
+#if defined(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1)
+	if (MOCA_WOL(flags)) {
+		/* switch to slow clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1,
+		    GENET1_CLOCK_SELECT_GENET1, 1);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1,
+		    GENET1_GMII_CLOCK_SELECT_GENET1, 1);
+		/*
+		 * Do not clear GENET0_L2INTR_CLOCK_ENABLE - it screws up
+		 * receiver after resume !!!
+		 */
+		/* 250, EEE, UNIMAC-TX */
+		BDEV_UNSET(
+		 BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1,
+		    0x106);
+	} else {
+		/* every clock except AON */
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		    0xe0);
+
+		/* Every genet1 clock except 108 */
+		BDEV_UNSET(
+		 BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1,
+		    0x1fe);
+	}
+#elif defined(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1)
+	if (MOCA_WOL(flags)) {
+		/* switch to slow clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1,
+		    GENET1_CLOCK_SELECT_GENET1, 1);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1,
+		    GENET1_GMII_CLOCK_SELECT_GENET1, 1);
+		/*
+		 * Do not clear GENET0_L2INTR_CLOCK_ENABLE - it screws up
+		 * receiver after resume !!!
+		 */
+		/* 250, EEE, UNIMAC-TX */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1,
+		    0x106);
+	} else {
+		/* every clock except AON */
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1,
+		    0x1e);
+
+		/* Every genet1 clock except 108 */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1,
+		    0x1fe);
+	}
+#else
+	if (MOCA_WOL(flags)) {
+		/* switch to slow clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT,
+		    GENET1_CLOCK_SELECT, 1);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT,
+		    GENET1_GMII_CLOCK_SELECT, 1);
+
+		/*
+		 * Do not clear GENET1_L2INTR_CLOCK_ENABLE - it screws up
+		 * receiver after resume !!!
+		 */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		    0x2180); /* 0x2980 */
+	} else {
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		    0x3F80);
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		    0xC);
+	}
+#endif
+}
+
+static void bcm40nm_pm_genet1_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+#if defined(CONFIG_BCM7425)
+	if (mem_power_down)
+		/* power up memory */
+		POWER_UP_MEMORY_3i(DUAL_GENET_TOP_DUAL_RGMII, GENET1, _B);
+	else
+		/* memory from standby */
+BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A,
+		GENET1_MEMORY_STANDBY_ENABLE_A, 0);
+#endif
+
+#if defined(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1)
+	if (MOCA_WOL(flags)) {
+		/* switch to fast clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1,
+		    GENET1_CLOCK_SELECT_GENET1, 0);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1,
+		    GENET1_GMII_CLOCK_SELECT_GENET1, 0);
+
+		/* 250, EEE, UNIMAC-TX */
+		BDEV_SET(
+		 BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1,
+		    0x106);
+	} else {
+		/* every genet 1 clock */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		    0xf0);
+
+		/* Every genet 1 clock */
+		BDEV_SET(
+		 BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1,
+		    0x1ff);
+	}
+#elif defined(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1)
+	if (MOCA_WOL(flags)) {
+		/* switch to fast clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1,
+		    GENET1_CLOCK_SELECT_GENET1, 0);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1,
+		    GENET1_GMII_CLOCK_SELECT_GENET1, 0);
+		/*
+		 * Do not clear GENET0_L2INTR_CLOCK_ENABLE - it screws up
+		 * receiver after resume !!!
+		 */
+		/* 250, EEE, UNIMAC-TX */
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1,
+		    0x106);
+	} else {
+		/* every genet 1 clock */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1,
+		    0x1f);
+
+		/* Every genet 1 clock */
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1,
+		    0x1ff);
+	}
+#else
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		0xC);
+
+	if (MOCA_WOL(flags)) {
+		/* switch to fast clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT,
+		    GENET1_CLOCK_SELECT, 0);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT,
+		    GENET1_GMII_CLOCK_SELECT, 0);
+
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		    0x2180);
+	} else {
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		    0x3F80);
+	}
+#endif
+
+}
+
+static void bcm40nm_pm_moca_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+#if defined(BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY)
+	SRAM_OFF_2i(MOCA_TOP, MOCA);
+#endif
+
+	BDEV_WR_F_RB(CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE,
+		MOCA_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE,
+		MOCA_108_CLOCK_ENABLE, 0);
+
+	if (!MOCA_WOL(flags)) {
+		PLL_CH_DIS(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 0);
+		PLL_CH_DIS(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 1);
+		PLL_CH_DIS(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 2);
+#if !defined(CONFIG_BCM7435)
+		PLL_CH_DIS(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 3);
+#endif
+	}
+}
+
+static void bcm40nm_pm_moca_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (!MOCA_WOL(flags)) {
+		PLL_CH_ENA(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 0);
+		PLL_CH_ENA(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 1);
+		PLL_CH_ENA(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 2);
+#if !defined(CONFIG_BCM7435)
+		PLL_CH_ENA(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 3);
+#endif
+	}
+
+	BDEV_WR_F_RB(CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE,
+		MOCA_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE,
+		MOCA_108_CLOCK_ENABLE, 1);
+
+#if defined(BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY)
+	SRAM_ON_2i(MOCA_TOP, MOCA);
+#endif
+}
+
+static int bcm40nm_pm_set_moca_cpu_rate(unsigned long rate)
+{
+#ifdef BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0
+	BDEV_WR_F(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0,
+		MDIV_CH0, BRCM_BASE_CLK/(rate/1000000));
+	return 0;
+#else
+	return -EINVAL;
+#endif
+}
+
+static int bcm40nm_pm_set_moca_phy_rate(unsigned long rate)
+{
+#ifdef BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1
+	BDEV_WR_F(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1,
+		MDIV_CH1, BRCM_BASE_CLK/(rate/1000000));
+	return 0;
+#else
+	return -ENOENT;
+#endif
+}
+
+#endif
+
+#if defined(CONFIG_BCM7231)
+
+static void bcm7231_pm_usb_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	bcm40nm_pm_usb_disable_s3();
+	/* USB0 */
+	/* power down USB PHY */
+	BDEV_SET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+	/* power down USB PLL */
+	BDEV_UNSET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+
+	SRAM_OFF_1(USB0);
+
+	/* disable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB0_CLOCK_DISABLE,
+		DISABLE_USB_54_MDIO_CLOCK, 1);
+	BDEV_WR_F_RB(CLKGEN_USB0_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_USB0_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 0);
+
+	/* USB1 */
+	/* power down USB PHY */
+	BDEV_SET(BCHP_USB1_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+	/* power down USB PLL */
+	BDEV_UNSET(BCHP_USB1_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+
+	SRAM_OFF_1(USB1);
+
+	/* disable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB1_CLOCK_DISABLE,
+		DISABLE_USB_54_MDIO_CLOCK, 1);
+	BDEV_WR_F_RB(CLKGEN_USB1_CLOCK_ENABLE, USB1_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_USB1_CLOCK_ENABLE, USB1_108_CLOCK_ENABLE, 0);
+
+	/* power down PLL */
+	PLL_CH_DIS(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 4);
+}
+
+static void bcm7231_pm_usb_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+	/* power up PLL */
+	PLL_CH_ENA(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 4);
+
+	/* USB0 */
+	/* enable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB0_CLOCK_DISABLE,
+		DISABLE_USB_54_MDIO_CLOCK, 0);
+	BDEV_WR_F_RB(CLKGEN_USB0_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_USB0_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 1);
+
+	SRAM_ON_1(USB0);
+
+	/* power up USB PLL */
+	BDEV_SET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+	/* power up USB PHY */
+	BDEV_UNSET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+
+	/* USB1 */
+	/* enable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB1_CLOCK_DISABLE,
+		DISABLE_USB_54_MDIO_CLOCK, 0);
+	BDEV_WR_F_RB(CLKGEN_USB1_CLOCK_ENABLE, USB1_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_USB1_CLOCK_ENABLE, USB1_108_CLOCK_ENABLE, 1);
+
+	SRAM_ON_1(USB1);
+
+	/* power up USB PLL */
+	BDEV_SET(BCHP_USB1_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+	/* power up USB PHY */
+	BDEV_UNSET(BCHP_USB1_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+
+	bcm40nm_pm_usb_enable_s3();
+}
+
+static void bcm7231_pm_sata_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	SRAM_OFF_2(SATA3_TOP, SATA3);
+
+	/* gate the clocks */
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_CLOCK_ENABLE,
+		SATA3_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_CLOCK_ENABLE,
+		SATA3_108_CLOCK_ENABLE, 0);
+}
+
+static void bcm7231_pm_sata_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	/* reenable the clocks */
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_CLOCK_ENABLE,
+		SATA3_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_CLOCK_ENABLE,
+		SATA3_108_CLOCK_ENABLE, 1);
+
+	SRAM_ON_2(SATA3_TOP, SATA3);
+
+}
+
+static void bcm7231_pm_genet_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+			GENET0_CLOCK_SELECT, 1);
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+			GENET0_GMII_CLOCK_SELECT, 1);
+		/* Disabling L2_INTR clock breaks HFB pattern matching ??? */
+		BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+			   0x43); /* used to be 0x53 */
+		return;
+	}
+
+	SRAM_OFF_2(DUAL_GENET_TOP_DUAL_RGMII, GENET0);
+
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE, 7);
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE, 0x7F);
+}
+
+static void bcm7231_pm_genet_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+			   0x43); /* used to be 0x53 */
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+			GENET0_CLOCK_SELECT, 0);
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+			GENET0_GMII_CLOCK_SELECT, 0);
+		return;
+	}
+
+	SRAM_ON_2(DUAL_GENET_TOP_DUAL_RGMII, GENET0);
+
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE, 7);
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE, 0x7F);
+}
+
+static void bcm7231_pm_genet1_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (MOCA_WOL(flags)) {
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+			GENET1_CLOCK_SELECT, 1);
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+			GENET1_GMII_CLOCK_SELECT, 1);
+		BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+			   0x2980);
+		return;
+	}
+
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE, 0x38);
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE, 0x3F80);
+}
+
+static void bcm7231_pm_genet1_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (MOCA_WOL(flags)) {
+		BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+			   0x2980);
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+			GENET1_CLOCK_SELECT, 0);
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+			GENET1_GMII_CLOCK_SELECT, 0);
+		return;
+	}
+
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE, 0x38);
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE, 0x3F80);
+}
+
+static void bcm7231_pm_suspend(u32 flags)
+{
+}
+
+static void bcm7231_pm_resume(u32 flags)
+{
+}
+
+static void bcm7231_pm_initialize(void)
+{
+	/* test scan clocks */
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE, 0xC0);
+	brcm_ddr_phy_initialize();
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(usb, 7231),
+	DEF_BLOCK_PM_OP(sata, 7231),
+	DEF_BLOCK_PM_OP(genet, 7231),
+	DEF_BLOCK_PM_OP(genet1, 7231),
+	DEF_SYSTEM_PM_OP(7231),
+	.clk_get		= brcm_pm_clk_get,
+	.initialize		= bcm7231_pm_initialize,
+};
+#endif
+
+#if defined(CONFIG_BCM7344)
+static void bcm7344_pm_network_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ANY_WOL(flags))
+		return;
+
+	PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 0);
+	PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 3);
+
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0xE0);
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE, 0xC000);
+}
+
+static void bcm7344_pm_network_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ANY_WOL(flags))
+		return;
+
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE, 0xC000);
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0xE0);
+
+	PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 0);
+	PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 3);
+}
+
+static void bcm7344_pm_genet_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		/* switch to slow clock */
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_CLOCK_SELECT, 1);
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_GMII_CLOCK_SELECT, 1);
+		/*
+		 * NOTE: disabling L2INTR clock
+		 * breaks ACPI pattern detection
+		 */
+		BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+			   0x43);
+		return;
+	}
+
+	SRAM_OFF_3(DUAL_GENET_TOP_RGMII_INST, GENET0, _A);
+
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0x3);
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE, 0x7F);
+}
+
+static void bcm7344_pm_genet_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		/* switch to fast clock */
+		BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+			   0x43);
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_CLOCK_SELECT, 0);
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_GMII_CLOCK_SELECT, 0);
+		return;
+	}
+
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0x3);
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE, 0x7F);
+
+	SRAM_ON_3(DUAL_GENET_TOP_RGMII_INST, GENET0, _A);
+}
+
+static void bcm7344_pm_genet1_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (MOCA_WOL(flags)) {
+		/* TODO */
+		return;
+	}
+
+/*	SRAM_OFF_3(DUAL_GENET_TOP_RGMII_INST, GENET1, _B); */
+
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0x1C);
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE, 0x1F80);
+}
+
+static void bcm7344_pm_genet1_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (MOCA_WOL(flags)) {
+		/* TODO */
+		return;
+	}
+
+/*	SRAM_ON_3(DUAL_GENET_TOP_RGMII_INST, GENET1, _B); */
+
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0x1C);
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE, 0x1F80);
+}
+
+static void bcm7344_pm_usb_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	bcm40nm_pm_usb_disable_s3();
+
+	/* USB0 */
+
+	/* power down PHY and PLL */
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL, PLL_PWRDWNB, 0);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL, PLL_IDDQ_PWRDN, 1);
+
+	/* power down memory */
+	SRAM_OFF_2i(USB0, USB0);
+
+	/* disable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_DISABLE,
+		DISABLE_USB_54_MDIO_CLOCK, 1);
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 0);
+
+	/* USB1 */
+
+	/* power down PHY and PLL */
+	BDEV_UNSET(BCHP_USB1_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+	BDEV_SET(BCHP_USB1_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+
+	/* power down memory */
+	SRAM_OFF_2i(USB1, USB1);
+
+	/* disable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_DISABLE,
+		DISABLE_USB_54_MDIO_CLOCK, 1);
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_ENABLE, USB1_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_ENABLE, USB1_108_CLOCK_ENABLE, 0);
+
+	PLL_CH_DIS(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 5);
+}
+
+static void bcm7344_pm_usb_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	PLL_CH_ENA(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 5);
+
+	/* USB0 */
+	/* enable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_DISABLE,
+		DISABLE_USB_54_MDIO_CLOCK, 0);
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 1);
+
+	/* power up memory */
+	SRAM_ON_2i(USB0, USB0);
+
+	/* power up PHY and PLL */
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL, PLL_PWRDWNB, 1);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL, PLL_IDDQ_PWRDN, 0);
+
+	/* USB1 */
+	/* enable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_DISABLE,
+		DISABLE_USB_54_MDIO_CLOCK, 0);
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_ENABLE, USB1_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_ENABLE, USB1_108_CLOCK_ENABLE, 1);
+
+	/* power up memory */
+	SRAM_ON_2i(USB1, USB1);
+
+	/* power up PHY and PLL */
+	BDEV_SET(BCHP_USB1_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+	BDEV_UNSET(BCHP_USB1_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+
+	bcm40nm_pm_usb_enable_s3();
+}
+
+static void bcm7344_pm_moca_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (MOCA_WOL(flags)) {
+		/* TODO */
+		return;
+	}
+
+	SRAM_OFF_2i(MOCA_TOP, MOCA);
+
+	BDEV_WR_F_RB(CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE,
+		MOCA_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE,
+		MOCA_108_CLOCK_ENABLE, 0);
+
+	PLL_CH_DIS(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_DIS(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 2);
+	PLL_CH_DIS(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 3);
+}
+
+static void bcm7344_pm_moca_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (MOCA_WOL(flags)) {
+		/* TODO */
+		return;
+	}
+
+	PLL_CH_ENA(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_ENA(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 2);
+	PLL_CH_ENA(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 3);
+
+	BDEV_WR_F_RB(CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE,
+		MOCA_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE,
+		MOCA_108_CLOCK_ENABLE, 1);
+
+	SRAM_ON_2i(MOCA_TOP, MOCA);
+}
+
+static void bcm7344_pm_suspend(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	PLL_DIS(CLKGEN_PLL_RAAGA_PLL);
+	PLL_CH_DIS(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 0);
+	PLL_CH_DIS(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_DIS(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 2);
+	PLL_DIS(CLKGEN_PLL_VCXO_PLL);
+
+	if (!ANY_WOL(flags))
+		PLL_DIS(CLKGEN_PLL_SYS1_PLL);
+
+	if (!MOCA_WOL(flags))
+		PLL_DIS(CLKGEN_PLL_MOCA_PLL);
+
+	PLL_CH_DIS(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 2);
+	PLL_CH_DIS(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 4);
+	PLL_CH_DIS(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 5);
+}
+
+static void bcm7344_pm_resume(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	PLL_CH_ENA(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 5);
+	PLL_CH_ENA(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 4);
+	PLL_CH_ENA(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 2);
+
+	if (!MOCA_WOL(flags))
+		PLL_ENA(CLKGEN_PLL_MOCA_PLL);
+
+	if (!ANY_WOL(flags))
+		PLL_ENA(CLKGEN_PLL_SYS1_PLL);
+
+	PLL_ENA(CLKGEN_PLL_VCXO_PLL);
+	PLL_CH_ENA(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 0);
+	PLL_CH_ENA(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_ENA(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 2);
+	PLL_ENA(CLKGEN_PLL_RAAGA_PLL);
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(usb, 7344),
+	DEF_BLOCK_PM_OP(network, 7344),
+	DEF_BLOCK_PM_OP(genet, 7344),
+	DEF_BLOCK_PM_OP(genet1, 7344),
+	DEF_BLOCK_PM_OP(moca, 7344),
+	DEF_SYSTEM_PM_OP(7344),
+	.clk_get		= brcm_pm_clk_get,
+	.initialize		= brcm_ddr_phy_initialize,
+};
+#endif
+
+#if defined(CONFIG_BCM7346)
+
+static void bcm7346_pm_network_disable(u32 flags)
+{
+	if (ANY_WOL(flags))
+		return;
+
+	PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 0);
+	PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 3);
+
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		GENET_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		GENET_108_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		DISABLE_GENET_ALWAYSON_CLOCK, 1);
+}
+
+static void bcm7346_pm_network_enable(u32 flags)
+{
+	if (ANY_WOL(flags))
+		return;
+
+	PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 0);
+	PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 3);
+
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		DISABLE_GENET_ALWAYSON_CLOCK, 0);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		GENET_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		GENET_108_CLOCK_ENABLE, 1);
+
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(usb, 40nm),
+	DEF_BLOCK_PM_OP(sata, 40nm),
+	DEF_BLOCK_PM_OP(network, 7346),
+	DEF_BLOCK_PM_OP(moca, 40nm),
+	DEF_BLOCK_PM_OP(genet, 40nm),
+	DEF_BLOCK_PM_OP(genet1, 40nm),
+	.clk_get		= brcm_pm_clk_get,
+	.initialize		= brcm_ddr_phy_initialize,
+};
+
+#endif
+
+#if defined(CONFIG_BCM7425) || defined(CONFIG_BCM7435)
+
+static void bcm7425_pm_network_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ANY_WOL(flags))
+		return;
+
+
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		GENET_SCB_CLOCK_ENABLE, 0);
+#if defined(CONFIG_BCM7435)
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0,
+		GENET0_108_CLOCK_ENABLE_GENET0, 0);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1,
+		GENET1_108_CLOCK_ENABLE_GENET1, 0);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		DISABLE_GENET0_ALWAYSON_CLOCK, 1);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		DISABLE_GENET1_ALWAYSON_CLOCK, 1);
+#else
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		GENET_108_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		DISABLE_GENET_ALWAYSON_CLOCK, 1);
+#endif
+}
+
+static void bcm7425_pm_network_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ANY_WOL(flags))
+		return;
+
+#if defined(CONFIG_BCM7435)
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		DISABLE_GENET0_ALWAYSON_CLOCK, 0);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		DISABLE_GENET1_ALWAYSON_CLOCK, 0);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0,
+		GENET0_108_CLOCK_ENABLE_GENET0, 1);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1,
+		GENET1_108_CLOCK_ENABLE_GENET1, 1);
+#else
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		DISABLE_GENET_ALWAYSON_CLOCK, 0);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		GENET_108_CLOCK_ENABLE, 1);
+#endif
+
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		GENET_SCB_CLOCK_ENABLE, 1);
+}
+
+/*
+ * shared PLL usage.
+ *
+ * PLL  7429    7425    7435
+ * moca
+ *  0   moca    moca    moca
+ *  1   moca    moca    moca
+ *  2   moca    moca    moca
+ *  3   moca    moca    v3d
+ *  4   sdio    sdio    m2mc,sdio
+ *  5   usb0    spi     unused
+ *
+ * net
+ *  0   genet   genet   genet
+ *  1   genet   genet   genet
+ *  2   genet   genet   genet
+ *  3   spi     unused  spi
+ */
+
+static void bcm7425_pm_suspend(u32 flags)
+{
+	/*
+	 * Some PLLs are shared between blocks, so disable them last.
+	 * Do not disable network PLLs if we need WOL.
+	 */
+#if defined(CONFIG_BCM7435)
+	PLL_CH_DIS(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 3);
+#endif
+
+	PLL_CH_DIS(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 4);
+
+#if defined(BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5)
+	PLL_CH_DIS(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 5);
+#endif
+
+#if defined(BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3)
+	PLL_CH_DIS(CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL, 3);
+#endif
+
+	if (ANY_WOL(flags) == 0) {
+		PLL_CH_DIS(CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL, 0);
+		PLL_CH_DIS(CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL, 1);
+		PLL_CH_DIS(CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL, 2);
+		PLL_DIS(CLKGEN_PLL_NETWORK_PLL);
+	}
+}
+
+static void bcm7425_pm_resume(u32 flags)
+{
+	/*
+	 * some PLLs are shared between blocks, so enable them early
+	 */
+	PLL_ENA(CLKGEN_PLL_NETWORK_PLL);
+	PLL_CH_ENA(CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL, 0);
+	PLL_CH_ENA(CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_ENA(CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL, 2);
+#if defined(BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3)
+	PLL_CH_ENA(CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL, 3);
+#endif
+
+#if defined(CONFIG_BCM7435)
+	PLL_CH_ENA(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 3);
+#endif
+	PLL_CH_ENA(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 4);
+
+#if defined(BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5)
+	PLL_CH_ENA(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 5);
+#endif
+}
+
+static void bcm7425_pm_late_suspend(int is_s3)
+{
+	/*
+	 * 7425 will not go to S2/S3 standby unless both memory controllers
+	 * are in SSPD mode. MEMC0 is handled by AON/BSP, but MEMC1 must
+	 * be put to SSPD by the software.
+	 * So, if MEMC1 was previously powered down, power it up and then
+	 * suspend
+	 */
+	if (brcm_pm_memc1_power == BRCM_PM_MEMC1_OFF) {
+		brcm_pm_memc1_powerup();
+		brcm_pm_memc1_power = BRCM_PM_MEMC1_ON;
+	}
+	if (brcm_pm_memc1_power == BRCM_PM_MEMC1_ON) {
+		brcm_pm_memc1_suspend(is_s3);
+		brcm_pm_memc1_power = BRCM_PM_MEMC1_SSPD;
+	}
+}
+
+static void bcm7425_pm_early_resume(int is_s3)
+{
+	if (brcm_pm_memc1_power == BRCM_PM_MEMC1_SSPD) {
+		brcm_pm_memc1_resume(is_s3);
+		brcm_pm_memc1_power = BRCM_PM_MEMC1_ON;
+	}
+}
+
+static void bcm7425_pm_pcie_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	BDEV_WR_F(PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
+	PLL_CH_DIS(CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL, 0);
+#if defined(BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1)
+	PLL_CH_DIS(CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL, 1);
+#endif
+	PLL_DIS(CLKGEN_PLL_HIF_PLL);
+}
+
+static void bcm7425_pm_pcie_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	PLL_ENA(CLKGEN_PLL_HIF_PLL);
+	PLL_CH_ENA(CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL, 0);
+#if defined(BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1)
+	PLL_CH_ENA(CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL, 1);
+#endif
+	/* take the bridge out of reset to be able to write serdes */
+	BDEV_WR_F_RB(HIF_RGR1_SW_INIT_1, PCIE_BRIDGE_SW_INIT, 0);
+	BDEV_WR_F(PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
+	/* delay to allow SERDES to be stable */
+	udelay(100);
+
+#if defined(CONFIG_BRCM_HAS_PCIE) && defined(CONFIG_PCI)
+	BDEV_WR_F_RB(WKTMR_EVENT, wktmr_alarm_event, 1);
+	BDEV_WR_F_RB(WKTMR_PRESCALER, wktmr_prescaler, WKTMR_FREQ);
+
+	if (brcm_pcie_enabled) {
+		brcm_early_pcie_setup();
+		brcm_setup_pcie_bridge();
+	}
+#endif
+}
+
+static struct clk clk_pcie = {
+	.name		= "pcie",
+	.disable	= &bcm7425_pm_pcie_disable,
+	.enable		= &bcm7425_pm_pcie_enable,
+	.refcnt		= 1, /* enabled on boot */
+};
+
+static void bcm7425_initialize(void)
+{
+	brcm_ddr_phy_initialize();
+	__clk_dyn_add(&clk_pcie);
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(usb, 40nm),
+	DEF_BLOCK_PM_OP(sata, 40nm),
+	DEF_BLOCK_PM_OP(network, 7425),
+	DEF_BLOCK_PM_OP(moca, 40nm),
+	DEF_BLOCK_PM_OP(genet, 40nm),
+	DEF_BLOCK_PM_OP(genet1, 40nm),
+	DEF_SYSTEM_PM_OP(7425),
+	DEF_SYSTEM_LATE_PM_OP(7425),
+	.moca.set_cpu_rate	= bcm40nm_pm_set_moca_cpu_rate,
+	.moca.set_phy_rate	= bcm40nm_pm_set_moca_phy_rate,
+	.clk_get		= brcm_pm_clk_get,
+	.initialize		= bcm7425_initialize,
+};
+#endif
+
+#if defined(CONFIG_BCM7429)
+
+static void bcm7429_pm_network_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ANY_WOL(flags))
+		return;
+
+	/* need to control network PLLs for 7429 */
+
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+		GENET_SCB_CLOCK_ENABLE, 0);
+
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0,
+		GENET0_108_CLOCK_ENABLE_GENET0, 0);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1,
+		GENET1_108_CLOCK_ENABLE_GENET1, 0);
+
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0,
+		DISABLE_GENET0_ALWAYSON_CLOCK, 1);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1,
+		DISABLE_GENET1_ALWAYSON_CLOCK, 1);
+}
+
+static void bcm7429_pm_network_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ANY_WOL(flags))
+		return;
+
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0,
+		DISABLE_GENET0_ALWAYSON_CLOCK, 0);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1,
+		DISABLE_GENET1_ALWAYSON_CLOCK, 0);
+
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0,
+		GENET0_108_CLOCK_ENABLE_GENET0, 1);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1,
+		GENET1_108_CLOCK_ENABLE_GENET1, 1);
+
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+		GENET_SCB_CLOCK_ENABLE, 1);
+
+	/* need to control network PLLs for 7429 */
+}
+static void bcm7429_initialize(void)
+{
+	brcm_ddr_phy_initialize();
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(usb, 40nm),
+	DEF_BLOCK_PM_OP(sata, 40nm),
+	DEF_BLOCK_PM_OP(network, 7429),
+	DEF_BLOCK_PM_OP(moca, 40nm),
+	DEF_BLOCK_PM_OP(genet, 40nm),
+	DEF_BLOCK_PM_OP(genet1, 40nm),
+	.moca.set_cpu_rate	= bcm40nm_pm_set_moca_cpu_rate,
+	.moca.set_phy_rate	= bcm40nm_pm_set_moca_phy_rate,
+	.clk_get		= brcm_pm_clk_get,
+	.initialize		= bcm7429_initialize,
+};
+#endif
+
+#if	defined(CONFIG_BCM7228) || \
+	defined(CONFIG_BCM7552) || \
+	defined(CONFIG_BCM7358) || \
+	defined(CONFIG_BCM7360) || \
+	defined(CONFIG_BCM7362)
+static void bcm7552_pm_usb_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	bcm40nm_pm_usb_disable_s3();
+
+	/* power down PHY and PLL */
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL, PLL_PWRDWNB, 0);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL, PLL_IDDQ_PWRDN, 1);
+
+	/* power down memory */
+	SRAM_OFF_2(USB, USB0);
+
+	/* disable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_DISABLE, DISABLE_USB_54_MDIO_CLOCK, 1);
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 0);
+}
+
+static void bcm7552_pm_usb_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+	/* enable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_DISABLE, DISABLE_USB_54_MDIO_CLOCK, 0);
+
+	/* power up memory */
+	SRAM_ON_2(USB, USB0);
+
+	/* power up PHY and PLL */
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL, PLL_IDDQ_PWRDN, 0);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL, PLL_PWRDWNB, 1);
+
+	bcm40nm_pm_usb_enable_s3();
+}
+
+static void bcm7552_pm_genet_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_GMII_CLOCK_SELECT, 1);
+		BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_CLOCK_SELECT, 1);
+		BDEV_SET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0xB);
+		/*
+		 * NOTE: disabling L2INTR clock breaks ACPI pattern detection
+		 */
+		BDEV_UNSET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+			0x1C7);
+		PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+		return;
+	}
+
+	/* Stop GENET clocks */
+	BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+		GENET_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+		GENET_108_CLOCK_ENABLE, 0);
+	BDEV_SET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0xF);
+
+	/* Power down PLL channels */
+	PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 2);
+}
+
+static void bcm7552_pm_genet_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+		BDEV_SET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE, 0x1C7);
+		BDEV_UNSET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0xB);
+		BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_GMII_CLOCK_SELECT, 0);
+		BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_CLOCK_SELECT, 0);
+		return;
+	}
+
+	/* Power up PLL channels */
+	PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 2);
+
+	/* Restart GENET clocks */
+	BDEV_UNSET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0xF);
+	BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+		GENET_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+		GENET_108_CLOCK_ENABLE, 1);
+}
+
+static void bcm7552_pm_suspend(u32 flags)
+{
+	/* VCXO channel 0, 1, 2 and PLL 0 */
+	PLL_CH_DIS(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 0);
+	PLL_CH_DIS(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_DIS(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 2);
+	PLL_DIS(CLKGEN_PLL_VCXO_PLL);
+	/* SYS PLL 1 */
+	if (!ENET_WOL(flags))
+		PLL_DIS(CLKGEN_PLL_SYS1_PLL);
+
+	/* SYS PLL 0 channels 2, 4, 5 */
+	PLL_CH_DIS(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 2);
+	PLL_CH_DIS(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 4);
+	PLL_CH_DIS(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 5);
+}
+
+static void bcm7552_pm_resume(u32 flags)
+{
+	/* SYS PLL 0 channels 2, 4, 5 */
+	PLL_CH_ENA(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 2);
+	PLL_CH_ENA(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 4);
+	PLL_CH_ENA(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 5);
+	/* SYS PLL 1 */
+	if (!ENET_WOL(flags))
+		PLL_ENA(CLKGEN_PLL_SYS1_PLL);
+
+	/* VCX0 channel 0, 1, 2 and PLL 0 */
+	PLL_ENA(CLKGEN_PLL_VCXO_PLL);
+	PLL_CH_ENA(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 0);
+	PLL_CH_ENA(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_ENA(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 2);
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(usb, 7552),
+	DEF_BLOCK_PM_OP(genet, 7552),
+	DEF_SYSTEM_PM_OP(7552),
+	.clk_get		= brcm_pm_clk_get,
+	.initialize		= brcm_ddr_phy_initialize,
+};
+#endif
+
+#if	defined(CONFIG_BCM7584)
+
+static void bcm7584_pm_usb_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+	bcm40nm_pm_usb_disable_s3();
+
+	/* power down USB PHY */
+	BDEV_SET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+	/* power down USB PLL */
+	BDEV_UNSET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+
+	/* power down memory */
+	SRAM_OFF_2(USB, USB0);
+
+	/* disable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 0);
+}
+
+static void bcm7584_pm_usb_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	/* enable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 1);
+
+	/* power down memory */
+	SRAM_ON_2(USB, USB0);
+
+	/* power up USB PLL */
+	BDEV_SET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+
+	/* power up USB PHY */
+	BDEV_UNSET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+
+	bcm40nm_pm_usb_enable_s3();
+}
+
+static void bcm7584_pm_genet_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		/* switch to slow clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+		    GENET0_CLOCK_SELECT, 1);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+		    GENET0_GMII_CLOCK_SELECT, 1);
+
+		/*
+		 * Do not clear GENET0_L2INTR_CLOCK_ENABLE - it screws up
+		 * receiver after resume !!!
+		 */
+		/* 250, EEE, UNIMAC-TX */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+		    0x83);
+	} else {
+		/* disable genet0 clocks */
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE,
+		    0xf);
+
+		/* Every genet0 clock */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+		    0xFF);
+	}
+
+}
+static void bcm7584_pm_genet_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+		    0x83);
+
+		/* switch to fast clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+		    GENET0_CLOCK_SELECT, 0);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+		    GENET0_GMII_CLOCK_SELECT, 0);
+
+	} else {
+		/* enable genet0 clocks */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE,
+		    0xf);
+
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+		    0xFF);
+	}
+
+}
+
+static void bcm7584_pm_genet1_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+	if (ENET_WOL(flags)) {
+		/* switch to slow clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+		    GENET1_CLOCK_SELECT, 1);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+		    GENET1_GMII_CLOCK_SELECT, 1);
+
+		/*
+		 * Do not clear GENET1_L2INTR_CLOCK_ENABLE - it screws up
+		 * receiver after resume !!!
+		 */
+		/* 250, EEE, UNIMAC-TX */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+		    0x4300);
+	} else {
+		/* Disable all genet1 clocks */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+		    0x7F00);
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE,
+		    0xf0);
+	}
+}
+
+static void bcm7584_pm_genet1_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+		    0x4300);
+
+		/* switch to fast clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+		    GENET1_CLOCK_SELECT, 0);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+		    GENET1_GMII_CLOCK_SELECT, 0);
+
+	} else {
+		/* enable genet1 clocks */
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+		    0x7F00);
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE,
+		    0xf0);
+	}
+}
+static void bcm7584_pm_network_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ANY_WOL(flags))
+		return;
+
+	/* SCB, 108 clocks */
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+		0x18000);
+
+	SRAM_OFF_3(DUAL_GENET_TOP_DUAL_RGMII, GENET0, _A);
+}
+
+static void bcm7584_pm_network_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ANY_WOL(flags))
+		return;
+
+	SRAM_ON_3(DUAL_GENET_TOP_DUAL_RGMII, GENET0, _A);
+
+	/* SCB, 108 clocks */
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+		0x18000);
+}
+
+static void bcm7584_pm_sata_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	SRAM_OFF_2(SATA3_TOP, SATA3);
+
+	/* gate the clocks */
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_CLOCK_ENABLE,
+		SATA3_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_CLOCK_ENABLE,
+		SATA3_108_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_CLOCK_DISABLE,
+		DISABLE_SATA_LV_CLK_30, 1);
+}
+
+static void bcm7584_pm_sata_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+	/* reenable the clocks */
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_CLOCK_DISABLE,
+		DISABLE_SATA_LV_CLK_30, 0);
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_CLOCK_ENABLE,
+		SATA3_108_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_CLOCK_ENABLE,
+		SATA3_SCB_CLOCK_ENABLE, 1);
+
+	SRAM_ON_2(SATA3_TOP, SATA3);
+
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(usb, 7584),
+	DEF_BLOCK_PM_OP(genet, 7584),
+	DEF_BLOCK_PM_OP(genet1, 7584),
+	DEF_BLOCK_PM_OP(network, 7584),
+	DEF_BLOCK_PM_OP(sata, 7584),
+	.clk_get		= brcm_pm_clk_get,
+};
+#endif
+
+#if	defined(CONFIG_BCM7563)
+
+static void bcm7563_pm_usb_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+	bcm40nm_pm_usb_disable_s3();
+
+	/* power down USB PHY */
+	BDEV_SET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+	/* power down USB PLL */
+	BDEV_UNSET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+
+	/* power down memory */
+	SRAM_OFF_2(USB, USB0);
+
+	/* disable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 0);
+}
+
+static void bcm7563_pm_usb_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	/* enable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 1);
+
+	/* power down memory */
+	SRAM_ON_2(USB, USB0);
+
+	/* power up USB PLL */
+	BDEV_SET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+
+	/* power up USB PHY */
+	BDEV_UNSET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+
+	bcm40nm_pm_usb_enable_s3();
+}
+
+static void bcm7563_pm_genet_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_GMII_CLOCK_SELECT, 1);
+		BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_CLOCK_SELECT, 1);
+		BDEV_SET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0xB);
+		/*
+		 * NOTE: disabling L2INTR clock breaks ACPI pattern detection
+		 */
+		BDEV_UNSET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+			0x1C7);
+		PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+		return;
+	}
+
+	/* Stop GENET clocks */
+	BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+		GENET_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+		GENET_108_CLOCK_ENABLE, 0);
+	BDEV_SET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0xF);
+
+	/* Power down PLL channels */
+	PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 0);
+	PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 2);
+}
+static void bcm7563_pm_genet_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+		BDEV_SET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE, 0x1C7);
+		BDEV_UNSET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0xB);
+		BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_GMII_CLOCK_SELECT, 0);
+		BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_CLOCK_SELECT, 0);
+		return;
+	}
+
+	/* Power up PLL channels */
+	PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 0);
+	PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 2);
+
+	/* Restart GENET clocks */
+	BDEV_UNSET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0xF);
+	BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+		GENET_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+		GENET_108_CLOCK_ENABLE, 1);
+}
+
+static void bcm7563_pm_suspend(u32 flags)
+{
+	/* disable self-refresh since it interferes with suspend */
+	brcm_pm_set_ddr_timeout(0);
+}
+
+static void bcm7563_pm_resume(u32 flags)
+{
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(usb, 7563),
+	DEF_BLOCK_PM_OP(genet, 7563),
+	DEF_SYSTEM_PM_OP(7563),
+	.clk_get		= brcm_pm_clk_get,
+};
+#endif
+
+#ifndef PM_OPS_DEFINED
+/* default structure - no pm callbacks available */
+static struct brcm_chip_pm_ops chip_pm_ops;
+#endif
+
+static __maybe_unused void brcm_ddr_phy_initialize(void)
+{
+#ifdef BCHP_MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL
+	/* MEMC0 */
+	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL,
+		DEVCLK_OFF_ON_SELFREF, 1);
+	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL,
+		IDDQ_MODE_ON_SELFREF, 1);
+	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_0_POWERDOWN,
+		PLLCLKS_OFF_ON_SELFREF, 1);
+	BDEV_WR_F_RB(MEMC_DDR23_APHY_WL0_0_DDR_PAD_CNTRL,
+		IDDQ_MODE_ON_SELFREF, 1);
+	BDEV_WR_F_RB(MEMC_DDR23_APHY_WL1_0_DDR_PAD_CNTRL,
+		IDDQ_MODE_ON_SELFREF, 1);
+#endif
+#ifdef BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL
+	/* MEMC1 */
+	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL,
+		DEVCLK_OFF_ON_SELFREF, 1);
+	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL,
+		HIZ_ON_SELFREF, 1);
+	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL,
+		IDDQ_MODE_ON_SELFREF, 1);
+	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_POWERDOWN,
+		PLLCLKS_OFF_ON_SELFREF, 1);
+	BDEV_WR_F_RB(MEMC_DDR23_APHY_WL0_1_DDR_PAD_CNTRL,
+		IDDQ_MODE_ON_SELFREF, 1);
+	BDEV_WR_F_RB(MEMC_DDR23_APHY_WL1_1_DDR_PAD_CNTRL,
+		IDDQ_MODE_ON_SELFREF, 1);
+#endif
+	/* restore self-refresh mode */
+	brcm_pm_set_ddr_timeout(brcm_pm_ddr_timeout);
+}
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+	if (chip_pm_ops.clk_get) {
+		struct clk *c = chip_pm_ops.clk_get(dev, id);
+		if (c)
+			return c;
+	}
+
+	return brcm_pm_clk_find(id) ? : ERR_PTR(-ENOENT);
+}
+EXPORT_SYMBOL(clk_get);
+
+static void brcm_pm_sata_disable(u32 flags)
+{
+	if (chip_pm_ops.sata.disable)
+		chip_pm_ops.sata.disable(brcm_pm_flags | flags);
+}
+
+static void brcm_pm_sata_enable(u32 flags)
+{
+	if (chip_pm_ops.sata.enable)
+		chip_pm_ops.sata.enable(brcm_pm_flags | flags);
+}
+
+static void brcm_pm_genet1_disable(u32 flags)
+{
+	if (chip_pm_ops.genet1.disable)
+		chip_pm_ops.genet1.disable(brcm_pm_flags | flags);
+}
+
+static void brcm_pm_genet1_enable(u32 flags)
+{
+	if (chip_pm_ops.genet1.enable)
+		chip_pm_ops.genet1.enable(brcm_pm_flags | flags);
+}
+
+static void brcm_pm_network_disable(u32 flags)
+{
+	if (chip_pm_ops.network.disable)
+		chip_pm_ops.network.disable(brcm_pm_flags | flags);
+}
+
+static void brcm_pm_network_enable(u32 flags)
+{
+	if (chip_pm_ops.network.enable)
+		chip_pm_ops.network.enable(brcm_pm_flags | flags);
+}
+
+static void brcm_pm_genet_disable(u32 flags)
+{
+	if (chip_pm_ops.genet.disable)
+		chip_pm_ops.genet.disable(brcm_pm_flags | flags);
+}
+
+static void brcm_pm_genet_enable(u32 flags)
+{
+	if (chip_pm_ops.genet.enable)
+		chip_pm_ops.genet.enable(brcm_pm_flags | flags);
+}
+
+static void brcm_pm_genet_disable_wol(u32 flags)
+{
+	brcm_pm_flags &= ~BRCM_PM_FLAG_ENET_WOL;
+}
+
+static void brcm_pm_genet_enable_wol(u32 flags)
+{
+	brcm_pm_flags |= BRCM_PM_FLAG_ENET_WOL;
+}
+
+static void brcm_pm_moca_disable(u32 flags)
+{
+	if (chip_pm_ops.moca.disable)
+		chip_pm_ops.moca.disable(brcm_pm_flags | flags);
+}
+
+static void brcm_pm_moca_enable(u32 flags)
+{
+	if (chip_pm_ops.moca.enable)
+		chip_pm_ops.moca.enable(brcm_pm_flags | flags);
+}
+
+static int brcm_pm_moca_cpu_set_rate(unsigned long rate)
+{
+	if (chip_pm_ops.moca.set_cpu_rate)
+		return chip_pm_ops.moca.set_cpu_rate(rate);
+
+	return -ENOENT;
+}
+
+static int brcm_pm_moca_phy_set_rate(unsigned long rate)
+{
+	if (chip_pm_ops.moca.set_phy_rate)
+		return chip_pm_ops.moca.set_phy_rate(rate);
+
+	return -ENOENT;
+}
+
+static void brcm_pm_moca_disable_wol(u32 flags)
+{
+	brcm_pm_flags &= ~BRCM_PM_FLAG_MOCA_WOL;
+}
+
+static void brcm_pm_moca_enable_wol(u32 flags)
+{
+	brcm_pm_flags |= BRCM_PM_FLAG_MOCA_WOL;
+}
+
+static void brcm_pm_usb_disable(u32 flags)
+{
+	if (chip_pm_ops.usb.disable)
+		chip_pm_ops.usb.disable(brcm_pm_flags | flags);
+}
+
+static void brcm_pm_usb_enable(u32 flags)
+{
+	if (chip_pm_ops.usb.enable)
+		chip_pm_ops.usb.enable(brcm_pm_flags | flags);
+}
+
+static void brcm_pm_initialize(void)
+{
+	if (chip_pm_ops.initialize)
+		chip_pm_ops.initialize();
+}
+
+static void brcm_pm_set_ddr_timeout(int val)
+{
+#if defined(BCHP_MEMC_DDR_0_SRPD_CONFIG) && defined(CONFIG_MIPS)
+	if (val) {
+#if defined(BCHP_MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL)
+		BDEV_WR_F(MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL,
+			IDDQ_MODE_ON_SELFREF, 1);
+		BDEV_WR_F(MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL,
+			HIZ_ON_SELFREF, 1);
+		BDEV_WR_F(MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL,
+			DEVCLK_OFF_ON_SELFREF, 1);
+		BDEV_WR_F(MEMC_DDR23_APHY_AC_0_POWERDOWN,
+			PLLCLKS_OFF_ON_SELFREF, 1);
+		BDEV_WR_F(MEMC_DDR23_APHY_WL0_0_DDR_PAD_CNTRL,
+			IDDQ_MODE_ON_SELFREF, 1);
+		BDEV_WR_F(MEMC_DDR23_APHY_WL1_0_DDR_PAD_CNTRL,
+			IDDQ_MODE_ON_SELFREF, 1);
+#endif
+		BDEV_WR_F_RB(MEMC_DDR_0_SRPD_CONFIG, INACT_COUNT, 0xdff);
+		BDEV_WR_F(MEMC_DDR_0_SRPD_CONFIG, SRPD_EN, 1);
+	} else {
+		unsigned long flags;
+
+		local_irq_save(flags);
+		BDEV_WR_F(MEMC_DDR_0_SRPD_CONFIG, INACT_COUNT, 0xffff);
+		do {
+			DEV_RD(KSEG1);
+		} while (BDEV_RD_F(MEMC_DDR_0_POWER_DOWN_STATUS, SRPD));
+		BDEV_WR_F(MEMC_DDR_0_SRPD_CONFIG, SRPD_EN, 0);
+		local_irq_restore(flags);
+	}
+#endif
+}
+
+/***********************************************************************
+ * Passive standby - per-chip
+ ***********************************************************************/
+static void brcm_system_standby(void)
+{
+	if (chip_pm_ops.suspend)
+		chip_pm_ops.suspend(brcm_pm_flags);
+}
+
+static void brcm_system_resume(void)
+{
+	if (chip_pm_ops.resume)
+		chip_pm_ops.resume(brcm_pm_flags);
+}
+
+static void brcm_system_late_standby(int is_s3)
+{
+	if (chip_pm_ops.late_suspend)
+		chip_pm_ops.late_suspend(is_s3);
+}
+
+static void brcm_system_early_resume(int is_s3)
+{
+	if (chip_pm_ops.early_resume)
+		chip_pm_ops.early_resume(is_s3);
+}
+
+/***********************************************************************
+ * Passive standby - common functions
+ ***********************************************************************/
+
+static suspend_state_t suspend_state;
+
+static void brcm_pm_handshake(void)
+{
+#if defined(CONFIG_BRCM_PWR_HANDSHAKE_V0)
+	int i;
+	unsigned long base = BCHP_BSP_CMDBUF_REG_START & ~0xffff;
+	unsigned long cmdbuf = BCHP_BSP_CMDBUF_REG_START;
+	u32 tmp;
+
+	i = 0;
+	while (!(BDEV_RD(base + 0xb008) & 0x02)) {
+		if (i++ == 10) {
+			printk(KERN_WARNING "%s: CMD_IDRY2 timeout\n",
+				__func__);
+			break;
+		}
+		msleep(20);
+	}
+	BDEV_WR_RB(cmdbuf + 0x180, 0x00000010);
+	BDEV_WR_RB(cmdbuf + 0x184, 0x00000098);
+	BDEV_WR_RB(cmdbuf + 0x188, 0xabcdef00);
+	BDEV_WR_RB(cmdbuf + 0x18c, 0xb055aa4f);
+	BDEV_WR_RB(cmdbuf + 0x190, 0x789a0004);
+	BDEV_WR_RB(cmdbuf + 0x194, 0x00000000);
+
+	BDEV_WR_RB(base + 0xb028, 1);
+
+	i = 0;
+	while (!(BDEV_RD(base + 0xb020) & 0x01)) {
+		if (i++ == 10) {
+			printk(KERN_WARNING "%s: CMD_OLOAD2 timeout\n",
+				__func__);
+			break;
+		}
+		mdelay(10);
+	}
+
+	BDEV_WR_RB(base + 0xb010, 0);
+	BDEV_WR_RB(base + 0xb020, 0);
+	tmp = BDEV_RD(cmdbuf + 0x494);
+	if (tmp != 0 && tmp != 1) {
+		printk(KERN_WARNING "%s: command failed: %08lx\n",
+			__func__, (unsigned long)tmp);
+		mdelay(10);
+		return;
+	}
+	BDEV_UNSET_RB(base + 0xb038, 0xff00);
+	printk(KERN_DEBUG "BSP power handshake complete OK: %x\n", tmp);
+#elif defined(CONFIG_BRCM_PWR_HANDSHAKE_V1)
+	BDEV_WR_F_RB(AON_CTRL_HOST_MISC_CMDS, pm_restore, 0);
+	BDEV_WR_F_RB(AON_CTRL_PM_INITIATE, pm_initiate_0, 0);
+	BDEV_WR_F_RB(AON_CTRL_PM_INITIATE, pm_initiate_0, 1);
+	mdelay(10);
+#endif /* CONFIG_BRCM_PWR_HANDSHAKE_V0 */
+}
+
+static int brcm_pm_prepare(void)
+{
+	DBG("%s:%d\n", __func__, __LINE__);
+	return 0;
+}
+
+static void brcm_pm_set_pll_on(void)
+{
+	int mips_pll_on = !!(brcm_pm_standby_flags & BRCM_STANDBY_MIPS_PLL_ON);
+	int ddr_pll_on = !!(brcm_pm_standby_flags & BRCM_STANDBY_DDR_PLL_ON);
+
+#if defined(BCHP_CLK_PM_PLL_ALIVE_SEL_MIPS_PLL_MASK)
+	BDEV_WR_F_RB(CLK_PM_PLL_ALIVE_SEL, MIPS_PLL, mips_pll_on);
+#elif defined(BCHP_CLKGEN_PM_PLL_ALIVE_SEL_MIPS_PLL_MASK)
+	BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, MIPS_PLL, mips_pll_on);
+#elif defined(BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_MASK)
+	BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, PLL_MIPS, mips_pll_on);
+#elif defined(BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_MASK)
+	BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, PLL_AVD_MIPS, mips_pll_on);
+#endif
+
+#if defined(BCHP_CLK_PM_PLL_ALIVE_SEL_DDR_PLL_MASK)
+	BDEV_WR_F_RB(CLK_PM_PLL_ALIVE_SEL, DDR_PLL, ddr_pll_on);
+#elif defined(BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DDR_PLL_MASK)
+	BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, DDR_PLL, ddr_pll_on);
+#elif defined(BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR0_MASK)
+	BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, PLL_DDR0, ddr_pll_on);
+	BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, PLL_DDR1, ddr_pll_on);
+#elif defined(BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR_MASK)
+	BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, PLL_DDR, ddr_pll_on);
+#elif defined(BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_MASK)
+	BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, memsys_PLL, ddr_pll_on);
+#elif defined(BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_MASK)
+	BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, memsys0_PLL, ddr_pll_on);
+	BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, memsys1_PLL, ddr_pll_on);
+#endif
+}
+
+void brcm_pm_wakeup_source_enable(u32 mask, int enable)
+{
+#ifdef BCHP_PM_L2_CPU_MASK_SET
+	if (enable) {
+		BDEV_WR_RB(BCHP_PM_L2_CPU_CLEAR, mask);
+		BDEV_WR_RB(BCHP_PM_L2_PCI_CLEAR, mask);
+		BDEV_WR_RB(BCHP_PM_L2_CPU_MASK_CLEAR, mask);
+		BDEV_WR_RB(BCHP_PM_L2_PCI_MASK_CLEAR, mask);
+	} else {
+		BDEV_WR_RB(BCHP_PM_L2_CPU_MASK_SET, mask);
+		BDEV_WR_RB(BCHP_PM_L2_PCI_MASK_SET, mask);
+	}
+#else
+	if (enable) {
+		BDEV_WR_RB(BCHP_AON_PM_L2_CPU_CLEAR, mask);
+		BDEV_WR_RB(BCHP_AON_PM_L2_PCI_CLEAR, mask);
+		BDEV_WR_RB(BCHP_AON_PM_L2_CPU_MASK_CLEAR, mask);
+		BDEV_WR_RB(BCHP_AON_PM_L2_PCI_MASK_CLEAR, mask);
+	} else {
+		BDEV_WR_RB(BCHP_AON_PM_L2_CPU_MASK_SET, mask);
+		BDEV_WR_RB(BCHP_AON_PM_L2_PCI_MASK_SET, mask);
+	}
+#endif
+}
+EXPORT_SYMBOL(brcm_pm_wakeup_source_enable);
+
+int brcm_pm_wakeup_get_status(u32 mask)
+{
+#ifdef BCHP_PM_L2_CPU_STATUS
+	return !!(BDEV_RD(BCHP_PM_L2_CPU_STATUS) & mask);
+#else
+	return !!(BDEV_RD(BCHP_AON_PM_L2_CPU_STATUS) &
+		   ~BDEV_RD(BCHP_AON_PM_L2_CPU_MASK_STATUS)
+		   & mask);
+#endif
+}
+EXPORT_SYMBOL(brcm_pm_wakeup_get_status);
+
+static u32 brcm_pm_wakeup_get_mask(void)
+{
+#ifdef BCHP_PM_L2_CPU_STATUS
+	return BDEV_RD(BCHP_PM_L2_CPU_MASK_STATUS);
+#else
+	return BDEV_RD(BCHP_AON_PM_L2_CPU_MASK_STATUS);
+#endif
+}
+
+static int brcm_pm_timer_wakeup_enable(void *ref)
+{
+#if !WATCHDOG_TIMER_WAKEUP_ALWAYS
+	if (brcm_pm_standby_flags & BRCM_STANDBY_TEST)
+#endif
+		brcm_pm_wakeup_source_enable(TIMER_INTR_MASK, 1);
+	return 0;
+}
+
+static int brcm_pm_timer_wakeup_disable(void *ref)
+{
+	brcm_pm_wakeup_source_enable(TIMER_INTR_MASK, 0);
+	return 0;
+}
+
+static int brcm_pm_timer_wakeup_poll(void *ref)
+{
+	int retval = brcm_pm_wakeup_get_status(TIMER_INTR_MASK);
+	printk(KERN_DEBUG "%s:  %d\n", __func__, retval);
+	return retval;
+}
+
+static struct brcm_wakeup_ops brcm_timer_wakeup_ops = {
+	.enable = brcm_pm_timer_wakeup_enable,
+	.disable = brcm_pm_timer_wakeup_disable,
+	.poll = brcm_pm_timer_wakeup_poll,
+};
+
+static void brcm_pm_set_alarm(int timeout)
+{
+	u32 tmp;
+	BDEV_WR_RB(BCHP_WKTMR_EVENT, 1);
+	if (timeout == 1) {
+		/* Wait for next second to start - if too little time left
+		 * before the counter increment we may receive WKTMR interrupt
+		 * before system is fully suspended.
+		 * One second should be enough to complete suspend
+		 * from this point
+		 */
+		tmp = BDEV_RD(BCHP_WKTMR_COUNTER);
+		while (BDEV_RD(BCHP_WKTMR_COUNTER) == tmp)
+			;
+	}
+	BDEV_WR_RB(BCHP_WKTMR_ALARM, BDEV_RD(BCHP_WKTMR_COUNTER) + timeout);
+}
+
+static void brcm_pm_clear_alarm(void)
+{
+	BDEV_WR_RB(BCHP_WKTMR_EVENT, 1);
+}
+
+#if defined(CONFIG_BCM7468) || defined(CONFIG_BCM7550)
+#define NON_RELOCATABLE_VEC
+#endif
+static int brcm_pm_standby(int is_s3)
+{
+	int ret = 0, valid_event = 1;
+	u32 l2_mask;
+	unsigned long restart_vec = BMIPS_WARM_RESTART_VEC;
+	unsigned long restart_vec_size = bmips_smp_int_vec_end -
+		bmips_smp_int_vec;
+
+	DBG("%s:%d\n", __func__, __LINE__);
+
+	if (brcm_pm_standby_flags & BRCM_STANDBY_TEST)
+		printk(KERN_INFO "%s: timeout %ld\n",
+			__func__, brcm_pm_standby_timeout);
+
+	do {
+
+		brcm_irq_standby_enter(BRCM_IRQ_STANDBY);
+
+#if defined(NON_RELOCATABLE_VEC)
+	{
+	u32 oldvec[5];
+	const int vecsize = 0x14;
+	void *vec = (void *)ebase + 0x200;
+
+	restart_vec = (unsigned long)vec;
+
+	memcpy(oldvec, vec, vecsize);
+	memcpy(vec, bmips_smp_int_vec, vecsize);
+	flush_icache_range(restart_vec, restart_vec + vecsize);
+#else
+	/* send all IRQs to BMIPS_WARM_RESTART_VEC */
+	clear_c0_cause(CAUSEF_IV);
+	irq_disable_hazard();
+	set_c0_status(ST0_BEV);
+	irq_disable_hazard();
+#endif
+
+	brcm_system_standby();
+	/*
+	 * Save current wakeup mask -
+	 * it may have been changed by usermode or drivers without
+	 * brcm_pm_wakeup API
+	 */
+	l2_mask = brcm_pm_wakeup_get_mask();
+	brcm_pm_wakeup_enable();
+
+#ifdef DEBUG_M2M_DMA
+	if (brcm_pm_standby_flags & 0x40) {
+		unsigned char *tb = kzalloc(PAGE_SIZE*16, GFP_ATOMIC);
+		int result, ii;
+		/* Test 1: simple copy */
+		if (1) {
+			struct brcm_mem_transfer xfer = {
+			.src		= tb,
+			.dst		= tb+PAGE_SIZE,
+			.pa_src		= 0,
+			.pa_dst		= 0,
+			.len		= PAGE_SIZE,
+			.mode		= BRCM_MEM_DMA_SCRAM_NONE,
+			.key		= 0,
+			.next		= NULL
+		};
+		memset(tb, 0xa3, PAGE_SIZE);
+		memset(tb+PAGE_SIZE, 0, PAGE_SIZE);
+
+		brcm_mem_dma_simple_transfer(&xfer);
+		result = memcmp(tb, tb+PAGE_SIZE, PAGE_SIZE);
+		DBG("MEM DMA TEST 1: result %d\n", result);
+		}
+		/* Test 2: encryption/decryption */
+		if (1) {
+			struct brcm_mem_transfer xfer[] = {
+			[0] = {
+				.src		= tb,
+				.dst		= tb+PAGE_SIZE*2,
+				.pa_src		= 0,
+				.pa_dst		= 0,
+				.len		= PAGE_SIZE,
+				.mode		= BRCM_MEM_DMA_SCRAM_BLOCK,
+				.key		= 5,
+				.next		= &xfer[1],
+			},
+			[1] = {
+				.src		= tb+PAGE_SIZE,
+				.dst		= tb+PAGE_SIZE*3,
+				.pa_src		= 0,
+				.pa_dst		= 0,
+				.len		= PAGE_SIZE,
+				.mode		= BRCM_MEM_DMA_SCRAM_BLOCK,
+				.key		= 5,
+				.next		= NULL,
+			},
+			[2] = {
+				.src		= tb+PAGE_SIZE*2,
+				.dst		= tb+PAGE_SIZE*4,
+				.pa_src		= 0,
+				.pa_dst		= 0,
+				.len		= PAGE_SIZE,
+				.mode		= BRCM_MEM_DMA_SCRAM_BLOCK,
+				.key		= 6,
+				.next		= &xfer[3],
+			},
+			[3] = {
+				.src		= tb+PAGE_SIZE*3,
+				.dst		= tb+PAGE_SIZE*5,
+				.pa_src		= 0,
+				.pa_dst		= 0,
+				.len		= PAGE_SIZE,
+				.mode		= BRCM_MEM_DMA_SCRAM_BLOCK,
+				.key		= 6,
+				.next		= NULL,
+			},
+		};
+		memset(tb, 0xa3, PAGE_SIZE*2);
+		memset(tb+PAGE_SIZE*2, 0x45, PAGE_SIZE*4);
+
+		DBG("MEM DMA TEST 2:\ninput\n");
+		for (ii = 0; ii < PAGE_SIZE; ii++) {
+			DBG("%02x ", *(tb+ii));
+			if (ii%32 == 31) {
+				DBG("\n"); break;
+			}
+		}
+		brcm_mem_dma_transfer(&xfer[0]);
+		DBG("encrypted\n");
+		for (ii = 0; ii < PAGE_SIZE; ii++) {
+			DBG("%02x ", *(tb+PAGE_SIZE*2+ii));
+			if (ii%32 == 31) {
+				DBG("\n"); break;
+			}
+		}
+		brcm_mem_dma_transfer(&xfer[2]);
+		DBG("decrypted\n");
+		for (ii = 0; ii < PAGE_SIZE; ii++) {
+			DBG("%02x ", *(tb+PAGE_SIZE*4+ii));
+			if (ii%32 == 31) {
+				DBG("\n"); break;
+			}
+		}
+		result = memcmp(tb, tb+(PAGE_SIZE*4), PAGE_SIZE*2);
+		DBG("result %02x\n", (unsigned char)result);
+		}
+		kfree(tb);
+	} else
+#endif
+	if (brcm_pm_standby_flags & BRCM_STANDBY_NO_SLEEP) {
+		if (brcm_pm_standby_flags & BRCM_STANDBY_DELAY)
+			mdelay(120000);
+		else
+			mdelay(5000);
+	} else {
+		if (brcm_pm_standby_flags & BRCM_STANDBY_TEST)
+			brcm_pm_set_alarm(brcm_pm_standby_timeout ? : 1);
+#if WATCHDOG_TIMER_WAKEUP_ALWAYS
+		else
+			brcm_pm_set_alarm(20);
+#endif
+		brcm_pm_set_pll_on();
+		brcm_pm_handshake();
+		brcm_system_late_standby(is_s3);
+
+		if (is_s3)
+			ret = brcm_pm_s3_standby(
+				current_cpu_data.dcache.linesz,
+				brcm_pm_standby_flags);
+		else
+			ret = brcm_pm_standby_asm(
+				current_cpu_data.icache.linesz,
+				restart_vec, restart_vec_size,
+				brcm_pm_standby_flags);
+		brcm_system_early_resume(is_s3);
+		brcm_pm_clear_alarm();
+		valid_event = brcm_pm_wakeup_poll(l2_mask);
+	}
+	brcm_pm_wakeup_disable();
+	brcm_system_resume();
+
+#if defined(NON_RELOCATABLE_VEC)
+	memcpy(vec, oldvec, vecsize);
+	flush_icache_range(restart_vec, restart_vec + vecsize);
+	}
+#else
+	/* send IRQs back to the normal runtime vectors */
+	clear_c0_status(ST0_BEV);
+	irq_disable_hazard();
+	set_c0_cause(CAUSEF_IV);
+	irq_disable_hazard();
+#endif
+	brcm_irq_standby_exit();
+	} while (!ret && !valid_event);
+
+	if (ret && !is_s3)
+		printk(KERN_WARNING "%s: standby failed with code %d\n",
+			__func__, ret);
+
+	brcm_pm_time_at_wakeup[0] = BDEV_RD(AON_RAM(0));
+	brcm_pm_time_at_wakeup[1] = BDEV_RD(AON_RAM(1));
+	return 0;
+}
+
+#if defined(BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK) || \
+defined(BCHP_SUN_TOP_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK)
+#define PM_CMD_BASE		0x1A
+#else
+#define PM_CMD_BASE		0x12
+#endif
+
+#if defined(CONFIG_CPU_BMIPS5000)
+#define PM_USE_MIPS_READY	0x04
+#else
+#define PM_USE_MIPS_READY	0x00
+#endif
+
+#define PM_STANDBY_CONFIG	(PM_CMD_BASE|PM_USE_MIPS_READY)
+#define PM_STANDBY_COMMAND	(PM_STANDBY_CONFIG|1)
+
+void brcm_pm_s3_cold_boot(void)
+{
+	if (!brcm_pm_halt_mode)
+		/* regular halt, go back */
+		return;
+
+	brcm_irq_standby_enter(BRCM_IRQ_STANDBY);
+	brcm_pm_wakeup_enable();
+	if (brcm_pm_standby_flags & BRCM_STANDBY_TEST)
+		brcm_pm_set_alarm(brcm_pm_standby_timeout ? : 3);
+	brcm_pm_handshake();
+	BDEV_WR_RB(AON_RAM(0), 0);
+	BDEV_WR_RB(BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT, 0xffff);
+
+	/* PD request is initiated on pm_start_pwrdn transition 0->1 */
+	BDEV_WR_RB(BCHP_AON_CTRL_PM_CTRL, 0);
+	BDEV_WR_RB(BCHP_AON_CTRL_PM_CTRL, PM_STANDBY_CONFIG);
+	/* Separate PD request from the rest of PMSM setup */
+	BDEV_WR_RB(BCHP_AON_CTRL_PM_CTRL, PM_STANDBY_COMMAND);
+
+	__asm__ __volatile__(
+	"	wait\n"
+	: : : "memory");
+}
+
+static int brcm_pm_enter(suspend_state_t unused)
+{
+	int ret = 0;
+
+	DBG("%s:%d\n", __func__, __LINE__);
+	switch (suspend_state) {
+	case PM_SUSPEND_STANDBY:
+		ret = brcm_pm_standby(0);
+		break;
+	case PM_SUSPEND_MEM:
+		ret = brcm_pm_standby(1);
+		break;
+	default:
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static void brcm_pm_finish(void)
+{
+	DBG("%s:%d\n", __func__, __LINE__);
+	BDEV_WR_RB(AON_RAM(0), 0);
+}
+
+static int brcm_pm_begin(suspend_state_t state)
+{
+	DBG("%s:%d\n", __func__, __LINE__);
+	suspend_state = state;
+	if (state == PM_SUSPEND_MEM)
+		brcm_pm_flags |= BRCM_PM_FLAG_S3;
+	else
+		brcm_pm_flags &= ~BRCM_PM_FLAG_S3;
+	return 0;
+}
+
+static void brcm_pm_end(void)
+{
+	DBG("%s:%d\n", __func__, __LINE__);
+	suspend_state = PM_SUSPEND_ON;
+	return;
+}
+
+static int brcm_pm_valid(suspend_state_t state)
+{
+	return (state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM);
+}
+
+static const struct platform_suspend_ops brcm_pm_ops = {
+	.begin		= brcm_pm_begin,
+	.end		= brcm_pm_end,
+	.prepare	= brcm_pm_prepare,
+	.enter		= brcm_pm_enter,
+	.finish		= brcm_pm_finish,
+	.valid		= brcm_pm_valid,
+};
+
+static int brcm_suspend_init(void)
+{
+	DBG("%s:%d\n", __func__, __LINE__);
+	suspend_set_ops(&brcm_pm_ops);
+	brcm_pm_wakeup_register(&brcm_timer_wakeup_ops, NULL, "WKTMR");
+	return 0;
+}
+late_initcall(brcm_suspend_init);
+
+int brcm_pm_deep_sleep(void)
+{
+	return suspend_state == PM_SUSPEND_MEM;
+}
+EXPORT_SYMBOL(brcm_pm_deep_sleep);
+
+void brcm_pm_sata3(int enable)
+{
+	struct clk *clk = brcm_pm_clk_find("sata");
+	if (clk)
+		enable ? clk_enable(clk) : clk_disable(clk);
+}
+
+void brcm_pm_save_restore_rts(unsigned long reg_addr, u32 *data, int restore)
+{
+	int ii = 0;
+
+	reg_addr += 4;		/* skip debug register */
+	if (restore)
+		for (ii = 0; ii < NUM_MEMC_CLIENTS; ii++) {
+			BDEV_WR_RB(reg_addr, data[ii]);
+			reg_addr += 4;
+		}
+	else
+		/* Save MEMC1 configuration */
+		for (ii = 0; ii < NUM_MEMC_CLIENTS; ii++) {
+			data[ii] = BDEV_RD(reg_addr);
+			reg_addr += 4;
+		}
+}
diff --git a/drivers/brcmstb/s3.c b/drivers/brcmstb/s3.c
new file mode 100644
index 0000000..2b31422
--- /dev/null
+++ b/drivers/brcmstb/s3.c
@@ -0,0 +1,552 @@
+/*
+ * Copyright (C) 2011 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/compiler.h>
+
+#include <asm/mipsregs.h>
+#include <linux/brcmstb/brcmstb.h>
+#include <asm/tlbflush.h>
+#include <asm/sections.h>
+#include <asm/cpu-features.h>
+#include <asm/bmips.h>
+
+#define MAX_GP_REGS	16
+#define MAX_CP0_REGS	32
+#define MAX_IO_REGS	(256 - MAX_GP_REGS - MAX_CP0_REGS)
+
+#if 0
+#define DBG		printk
+#else
+#define DBG(...)	do { } while (0)
+#endif
+
+#define CALCULATE_MEM_HASH		(1)
+#define WARM_BOOT_MAGIC_WORD		(0x5AFEB007)
+#define CFE_PARAMETER_BLOCK		(0)
+#define AUTHENTICATION_REGION_SIZE	(16*1024*1024)
+
+#define AON_CTRL_HASH_START_INDEX	(CFE_PARAMETER_BLOCK+5)
+#define AON_SAVE_CPB(idx, val) \
+	BDEV_WR_RB(AON_RAM_BASE + ((CFE_PARAMETER_BLOCK+idx)<<2), val)
+#define AON_READ_CPB(idx) \
+	BDEV_RD(AON_RAM_BASE + ((CFE_PARAMETER_BLOCK+idx)<<2))
+#define AON_SAVE_HASH(idx, val) \
+	BDEV_WR_RB(AON_RAM_BASE + ((AON_CTRL_HASH_START_INDEX+idx)<<2), val)
+#define AON_READ_HASH(idx) \
+	BDEV_RD(AON_RAM_BASE + ((AON_CTRL_HASH_START_INDEX+idx)<<2))
+
+struct cp0_value {
+	u32	value;
+	u32	index;
+	u32	select;
+};
+
+struct	brcm_pm_s3_context {
+	u32			gp_regs[MAX_GP_REGS];
+	struct cp0_value	cp0_regs[MAX_CP0_REGS];
+	int			cp0_regs_idx;
+	u32			memc0_rts[NUM_MEMC_CLIENTS];
+	u32			relo_vector_control_0;
+	u32			relo_vector_control_1;
+	u32			sc_boot_vec;
+};
+
+struct brcm_pm_s3_context s3_context;
+
+asmlinkage int brcm_pm_s3_standby_asm(unsigned long options,
+	void (*dram_encoder_start)(void), int dcache_linesz);
+extern int s3_reentry;
+
+extern void bmips_enable_xks01(void);
+
+static void __raw_uart_putc(char c);
+
+static void brcm_pm_dump_context(struct brcm_pm_s3_context *cxt);
+
+#define CPO_SAVE_INFO(cxt, ci, idx, _select) \
+do { \
+	cxt->cp0_regs[ci].index = idx; \
+	cxt->cp0_regs[ci].select = _select; \
+	cxt->cp0_regs[ci++].value = read_c0_reg(idx, _select); \
+} while (0);
+#define read_c0_reg(n, s)	__read_32bit_c0_register($##n, s)
+#define write_c0_reg(n, s, v)	__write_32bit_c0_register($##n, s, v)
+
+static __maybe_unused void brcm_pm_init_cp0_context(
+		struct brcm_pm_s3_context *cxt)
+{
+	cxt->cp0_regs_idx = 0;
+}
+
+static __maybe_unused void brcm_pm_save_cp0_context(
+		struct brcm_pm_s3_context *cxt)
+{
+	int ci = cxt->cp0_regs_idx;
+	void __iomem *cbr;
+
+	/* Generic MIPS */
+
+	CPO_SAVE_INFO(cxt, ci, 4, 0); /* context */
+	CPO_SAVE_INFO(cxt, ci, 4, 2); /* userlocal */
+	CPO_SAVE_INFO(cxt, ci, 5, 0); /* pagemask */
+	CPO_SAVE_INFO(cxt, ci, 7, 0); /* hwrena */
+	CPO_SAVE_INFO(cxt, ci, 11, 0); /* compare */
+	CPO_SAVE_INFO(cxt, ci, 12, 0); /* status */
+
+	/* Broadcom specific */
+
+	CPO_SAVE_INFO(cxt, ci, 22, 0); /* config */
+	CPO_SAVE_INFO(cxt, ci, 22, 1); /* mode */
+	CPO_SAVE_INFO(cxt, ci, 22, 3); /* eDSP */
+
+	switch (current_cpu_type()) {
+	case CPU_BMIPS4380:
+		cbr = BMIPS_GET_CBR();
+		cxt->relo_vector_control_1 =
+			__raw_readl(cbr + BMIPS_RELO_VECTOR_CONTROL_1);
+		/* falls through */
+	case CPU_BMIPS3300:
+	case CPU_BMIPS4350:
+		cbr = BMIPS_GET_CBR();
+		cxt->relo_vector_control_0 =
+			__raw_readl(cbr + BMIPS_RELO_VECTOR_CONTROL_0);
+		break;
+	case CPU_BMIPS5000:
+		CPO_SAVE_INFO(cxt, ci, 22, 4); /* bootvec */
+		CPO_SAVE_INFO(cxt, ci, 15, 1); /* ebase */
+		cxt->sc_boot_vec = bmips_read_zscm_reg(0xa0);
+		break;
+	}
+
+	cxt->cp0_regs_idx = ci;
+}
+
+static __maybe_unused void brcm_pm_restore_cp0_context(
+		struct brcm_pm_s3_context *cxt)
+{
+	int ci = cxt->cp0_regs_idx;
+	void __iomem *cbr;
+
+	/* Broadcom specific */
+
+	switch (current_cpu_type()) {
+	case CPU_BMIPS4380:
+		cbr = BMIPS_GET_CBR();
+		__raw_writel(cxt->relo_vector_control_1,
+			cbr + BMIPS_RELO_VECTOR_CONTROL_1);
+		/* falls through */
+	case CPU_BMIPS3300:
+	case CPU_BMIPS4350:
+		cbr = BMIPS_GET_CBR();
+		__raw_writel(cxt->relo_vector_control_0,
+			cbr + BMIPS_RELO_VECTOR_CONTROL_0);
+		break;
+	case CPU_BMIPS5000:
+		bmips_write_zscm_reg(0xa0, cxt->sc_boot_vec);
+		write_c0_reg(15, 1, cxt->cp0_regs[--ci].value); /* ebase */
+		write_c0_reg(22, 4, cxt->cp0_regs[--ci].value); /* bootvec */
+		break;
+	}
+
+	write_c0_reg(22, 3, cxt->cp0_regs[--ci].value); /* eDSP */
+	write_c0_reg(22, 1, cxt->cp0_regs[--ci].value); /* mode */
+	write_c0_reg(22, 0, cxt->cp0_regs[--ci].value); /* config */
+
+	/* Generic MIPS */
+
+	write_c0_reg(12, 0, cxt->cp0_regs[--ci].value); /* status */
+	write_c0_reg(11, 0, cxt->cp0_regs[--ci].value); /* compare */
+	write_c0_reg(7, 0, cxt->cp0_regs[--ci].value); /* hwrena */
+	write_c0_reg(5, 0, cxt->cp0_regs[--ci].value); /* pagemask */
+	write_c0_reg(4, 2, cxt->cp0_regs[--ci].value); /* userlocal */
+	write_c0_reg(4, 0, cxt->cp0_regs[--ci].value); /* context */
+}
+
+static __maybe_unused void brcm_pm_cmp_context(
+		struct brcm_pm_s3_context *cxt,
+		struct brcm_pm_s3_context *cxt2, const char* title)
+{
+	int i;
+	int identical = 1;
+	if (title)
+		DBG("%s\n", title);
+	if (cxt->cp0_regs_idx != cxt2->cp0_regs_idx) {
+		identical = 0;
+		DBG("CP0 reg # is different: %d %d\n",
+			cxt->cp0_regs_idx, cxt2->cp0_regs_idx);
+	} else {
+		for (i = 0; i < cxt->cp0_regs_idx; i++) {
+			if (cxt->cp0_regs[i].value
+					!= cxt2->cp0_regs[i].value) {
+				identical = 0;
+				DBG("\tCP0[%02d.%01d]:  %08x != %08x\n",
+					cxt->cp0_regs[i].index,
+					cxt->cp0_regs[i].select,
+					cxt->cp0_regs[i].value,
+					cxt2->cp0_regs[i].value);
+			}
+		}
+	}
+	if (identical)
+		DBG("Contexts are identical\n");
+	else {
+		brcm_pm_dump_context(cxt);
+		brcm_pm_dump_context(cxt2);
+	}
+}
+
+static void brcm_pm_dump_context(struct brcm_pm_s3_context *cxt)
+{
+	int i;
+	DBG("CPO:\n");
+	for (i = 0; i < cxt->cp0_regs_idx; i++) {
+		DBG("[%02d.%0d]=%08x ",
+			cxt->cp0_regs[i].index,
+			cxt->cp0_regs[i].select,
+			cxt->cp0_regs[i].value);
+		if (i%8 == 7)
+			DBG("\n");
+	}
+	DBG("\n\n");
+}
+
+/***********************************************************************
+ * Encryption setup for S3 suspend
+ ***********************************************************************/
+#if CALCULATE_MEM_HASH
+/*
+ * Default scheme encrypts specified memory region and writes encoded data
+ * to a temporary buffer, overwriting previous data on every block write.
+ * Upon encoding final block, last 16 bytes are stored into AON, then
+ * entire temporary buffer is wiped out
+ * Bootloader will repeat encoding immediately after S3 wakeup to see
+ * if hash value matches.
+ * brcm_pm_s3_tmpbuf - temporary buffer
+ * hash_pointer - pointer to location in memory where hash value is located
+ * after encoding
+ */
+static char __section(.s3_enc_tmpbuf) brcm_pm_s3_tmpbuf[PAGE_SIZE*16];
+static u32 *hash_pointer;
+
+#define MEM_ENCRYPTED_START_ADDR	(0x80000000)
+#define MEM_ENCRYPTED_LEN		(1*1024*1024)
+#define	S3_HASH_LEN			16
+
+#define MAX_TRANSFER_SIZE_MB		(16)
+#define MAX_TRANSFER_SIZE		(MAX_TRANSFER_SIZE_MB*1024*1024)
+
+#define AES_CBC_ENCRYPTION_KEY_SLOT	(5)
+#define AES_CBC_DECRYPTION_KEY_SLOT	(6)
+
+/*
+ * brcm_pm_dram_encoder_set_area
+ * Generates a list of descriptors needed to encrypt area
+ * VA _begin.._begin+len-1 into PA outbuf..outbuf+out_len-1
+ * On return out_len is the length of the last transfer, this
+ * can be used as an offset into the outbuf to extract hash
+ */
+static struct brcm_mem_transfer *brcm_pm_dram_encoder_set_area(void *_begin,
+	u32 len, dma_addr_t outbuf, u32 *out_len,
+	struct brcm_mem_transfer *next)
+{
+	int num_descr = (len + *out_len - 1) / *out_len;
+	struct brcm_mem_transfer *xfer, *x, *last_x;
+	void *_end = _begin + len;
+
+	BUG_ON(*out_len > MAX_TRANSFER_SIZE);
+
+	xfer = kzalloc(num_descr * sizeof(struct brcm_mem_transfer),
+		GFP_ATOMIC);
+
+	if (!xfer) {
+		printk(KERN_ERR "%s: out of memory\n", __func__);
+		return NULL;
+	}
+
+	last_x = x = xfer;
+	while (_begin < _end) {
+		dma_addr_t pa_src = virt_to_phys(_begin);
+		if (_begin + *out_len > _end)
+			*out_len = _end - _begin;
+		/* workaround - M2M DMA does not like 0 address */
+		x->len		= *out_len;
+		if (!pa_src) {
+			pa_src += 0x10;
+			x->len -= 0x10;
+		}
+		x->pa_src	= pa_src;
+		x->pa_dst	= outbuf;
+		x->mode		= BRCM_MEM_DMA_SCRAM_BLOCK;
+		x->key		= AES_CBC_ENCRYPTION_KEY_SLOT;
+		x->next		= x + 1;
+		last_x = x;
+		x++;
+		_begin += *out_len;
+	}
+	last_x->next = next;
+
+	return xfer;
+}
+
+static void brcm_pm_dram_encoder_free_area(struct brcm_mem_transfer *xfer)
+{
+	kfree(xfer);
+}
+
+/* Memory region over which M2M DMA calculates MAC cannot be modified
+   after a call to brcm_pm_dram_encoder_start() */
+void brcm_pm_dram_encode(void)
+{
+	u32 *hp = hash_pointer;
+	u32 outbuflen = sizeof(brcm_pm_s3_tmpbuf);
+	uint32_t tmp0, tmp1;
+	/* clear temporary buffer */
+	memset(brcm_pm_s3_tmpbuf, 0, sizeof(brcm_pm_s3_tmpbuf));
+	_dma_cache_wback_inv(0, ~0);
+	/* start M2M encoder */
+	brcm_pm_dram_encoder_start();
+	/* save hash in AON register */
+	AON_SAVE_HASH(0, *hp++);
+	AON_SAVE_HASH(1, *hp++);
+	AON_SAVE_HASH(2, *hp++);
+	AON_SAVE_HASH(3, *hp++);
+
+	/* clear temporary buffer
+	 * cannot use library function because it will use memory (stack) */
+	__asm__ __volatile__(
+	"	.set	noreorder\n"
+	"	la	%0, brcm_pm_s3_tmpbuf\n"
+	"	move	%1, $0\n"
+	"1:	sw	$0, 0(%0)\n"
+	"	addi	%0, 4\n"
+	"	addi	%1, 4\n"
+	"	bne	%2, %1, 1b\n"
+	"	nop\n"
+	: "=&r" (tmp0), "=&r" (tmp1)
+	: "r" (outbuflen));
+}
+#else
+#define brcm_pm_dram_encode	NULL
+#endif
+
+int brcm_pm_s3_standby(int dcache_linesz, unsigned long options)
+{
+	int retval = 0;
+	unsigned long flags;
+#if CALCULATE_MEM_HASH
+	int r1_len, r2_len, total_len;
+	struct brcm_mem_transfer *xfer[3] = {0};
+	u32 outlen = sizeof(brcm_pm_s3_tmpbuf);
+	u32 outbuflen = outlen, tmp, ii;
+	u32 region_size = AUTHENTICATION_REGION_SIZE;
+	void *src;
+	u32 hash[4];
+
+	/*
+	 * We are using bi-directional mapping to avoid synchronizing cache
+	 * after encoding
+	 */
+	dma_addr_t pa_dst = dma_map_single(NULL, brcm_pm_s3_tmpbuf,
+		outbuflen, DMA_BIDIRECTIONAL);
+
+	if (dma_mapping_error(NULL, pa_dst)) {
+		printk(KERN_ERR "%s: cannot remap temp buffer\n", __func__);
+		return -1;
+	}
+
+	if (region_size < brcm_min_auth_region_size)
+		region_size = brcm_min_auth_region_size;
+
+	printk(KERN_DEBUG "Authentication region size: 0x%08x\n", region_size);
+	printk(KERN_DEBUG "Output buffer  : 0x%08x-0x%08x (0x%08x)\n",
+	       (u32)brcm_pm_s3_tmpbuf,
+	       (u32)brcm_pm_s3_tmpbuf + outlen, outlen);
+
+	/* We add areas to the head of the list - in reverse order
+	 * of M2M DMA execution */
+
+	/* This region starts from _text and bypasses temporary
+	 * output buffer */
+	src = _text;
+	/* check if in/out regions overlap */
+	if (brcm_pm_s3_tmpbuf >= (char *)(src + region_size) ||
+	    brcm_pm_s3_tmpbuf + outlen <= (char *)src) {
+		/* non-overlapping case */
+		r1_len = region_size;
+		r2_len = 0;
+	} else {
+		/* need to cut out the output buffer */
+		r1_len = (int)(brcm_pm_s3_tmpbuf - (char *)src);
+		r2_len = region_size - r1_len;
+	}
+	total_len = r1_len + r2_len;
+
+	xfer[0] = brcm_pm_dram_encoder_set_area((void *)src, r1_len,
+		pa_dst, &outlen, NULL);
+	if (!xfer[0]) {
+		printk(KERN_ERR "%s: cannot setup M2M DMA [0]\n", __func__);
+		goto _failed;
+	}
+
+	printk(KERN_DEBUG "Region 0       : 0x%08x-0x%08x (0x%08x)\n",
+		(u32)src, (u32)src + r1_len, r1_len);
+
+	if (r2_len > 0) {
+		outlen = outbuflen;
+		src = (void *)((u32)(brcm_pm_s3_tmpbuf + outbuflen));
+		xfer[1] = xfer[0];
+		xfer[0] = brcm_pm_dram_encoder_set_area(src, r2_len,
+			pa_dst, &outlen, xfer[1]);
+		if (!xfer[0]) {
+			printk(KERN_ERR "%s: cannot setup M2M DMA [1]\n",
+			       __func__);
+			goto _failed;
+		}
+		printk(KERN_DEBUG "Region 1       : 0x%08x-0x%08x (0x%08x)\n",
+			(u32)src, (u32)(src + r2_len), r2_len);
+	}
+
+	/* First descriptor must include kernel reentry point
+	 * We are processing one output buffer worth of data */
+	src = (void *)((u32)(&s3_reentry) & ~(PAGE_SIZE-1));
+	tmp = outbuflen;
+	xfer[2] = brcm_pm_dram_encoder_set_area((void *)src, outbuflen,
+		pa_dst, &tmp, xfer[0]);
+	if (!xfer[2]) {
+		printk(KERN_ERR "%s: cannot setup M2M DMA [2]\n", __func__);
+		goto _failed;
+	}
+	printk(KERN_DEBUG "Region 2       : 0x%08x-0x%08x (0x%08x)\n",
+		(u32)src, (u32)src + outbuflen, outbuflen);
+	total_len += outbuflen;
+	if (brcm_pm_dram_encoder_prepare(xfer[2])) {
+		printk(KERN_ERR "%s: cannot initialize M2M DMA\n", __func__);
+		goto _failed;
+	}
+
+	hash_pointer = (u32 *)(brcm_pm_s3_tmpbuf +
+		(outlen - S3_HASH_LEN + outbuflen) % outbuflen);
+
+	/* M2M DMA descriptor address */
+	if (brcm_pm_hash_enabled)
+		AON_SAVE_CPB(2, BDEV_RD(BCHP_MEM_DMA_0_FIRST_DESC));
+	else
+		AON_SAVE_CPB(2, 0);
+	/* Encryption key slot */
+	AON_SAVE_CPB(3, AES_CBC_ENCRYPTION_KEY_SLOT);
+	/* Address of hash */
+	AON_SAVE_CPB(4, (u32)hash_pointer);
+	/* Total authentication region size */
+	AON_SAVE_CPB(9, total_len);
+	printk(KERN_DEBUG "Encryption slot: %d\n",
+	       AES_CBC_ENCRYPTION_KEY_SLOT);
+	printk(KERN_DEBUG "Hash pointer   : 0x%p\n", hash_pointer);
+	printk(KERN_DEBUG "Total length   : 0x%08x\n", (u32)total_len);
+	printk(KERN_DEBUG "Reentry point  : 0x%p\n", &s3_reentry);
+#else
+	AON_SAVE_CPB(2, 0);
+#endif
+
+	/* Warm Boot Magic Word */
+	AON_SAVE_CPB(0, WARM_BOOT_MAGIC_WORD);
+	/* Kernel Reentry Address */
+	AON_SAVE_CPB(1, (u32)&s3_reentry);
+
+	/* clear RESET_HISTORY */
+	BDEV_WR_F_RB(AON_CTRL_RESET_CTRL, clear_reset_history, 1);
+
+	local_irq_save(flags);
+	/* save CP0 context */
+	brcm_pm_init_cp0_context(&s3_context);
+	brcm_pm_save_cp0_context(&s3_context);
+
+	/* inhibit DDR_RSTb pulse */
+	BDEV_UNSET(BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL, 0x0f);
+	BDEV_SET(BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL, BIT(5) | 0x05);
+
+	/* save RTS */
+	brcm_pm_save_restore_rts(BCHP_MEMC_ARB_0_REG_START,
+		s3_context.memc0_rts, 0);
+
+	/* save I/O context */
+
+	local_flush_tlb_all();
+	_dma_cache_wback_inv(0, ~0);
+
+	retval = brcm_pm_s3_standby_asm(options, brcm_pm_dram_encode,
+		dcache_linesz);
+
+	/* CPU reconfiguration */
+	local_flush_tlb_all();
+	brcmstb_cpu_setup();
+	cpumask_clear(&bmips_booted_mask);
+
+	/* restore RTS */
+	brcm_pm_save_restore_rts(BCHP_MEMC_ARB_0_REG_START,
+		s3_context.memc0_rts, 1);
+
+	/* restore I/O context */
+	board_pinmux_setup();
+	ebi_restore_settings();
+
+	/* restore CP0 context */
+	brcm_pm_restore_cp0_context(&s3_context);
+
+#if defined(BCHP_IRQ0_UART_IRQEN_uarta_MASK)
+	/* 3548 style - separate register */
+	BDEV_WR(BCHP_IRQ0_UART_IRQEN, BCHP_IRQ0_UART_IRQEN_uarta_MASK |
+		BCHP_IRQ0_UART_IRQEN_uartb_MASK |
+		BCHP_IRQ0_UART_IRQEN_uartc_MASK);
+	BDEV_WR(BCHP_IRQ0_IRQEN, 0);
+#elif defined(BCHP_IRQ0_IRQEN_uarta_irqen_MASK)
+	/* 7405 style - shared with L2 */
+	BDEV_WR(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uarta_irqen_MASK
+		| BCHP_IRQ0_IRQEN_uartb_irqen_MASK
+#if defined(BCHP_IRQ0_IRQEN_uartc_irqen_MASK)
+		| BCHP_IRQ0_IRQEN_uartc_irqen_MASK
+#endif
+		);
+#endif
+
+	local_irq_restore(flags);
+
+
+#if CALCULATE_MEM_HASH
+	for (ii = 0; ii < 4; ii++)
+		hash[ii] = AON_READ_HASH(ii);
+	printk(KERN_DEBUG "hash: %08x:%08x:%08x:%08x\n",
+	       hash[0], hash[1], hash[2], hash[3]);
+
+	brcm_pm_dram_encoder_complete(xfer[0]);
+_failed:
+	for (ii = 0; ii < 3; ii++)
+		brcm_pm_dram_encoder_free_area(xfer[ii]);
+	dma_unmap_single(NULL, pa_dst, outbuflen, DMA_BIDIRECTIONAL);
+
+#endif
+
+	return retval;
+}
+
+static void __maybe_unused __raw_uart_putc(char c)
+{
+	while (!(BDEV_RD(BCHP_UARTA_LSR) & BCHP_UARTA_LSR_THRE_MASK))
+		;
+	BDEV_WR_RB(BCHP_UARTA_THR, (u32)c);
+}
diff --git a/drivers/brcmstb/setup.c b/drivers/brcmstb/setup.c
new file mode 100644
index 0000000..ce47249
--- /dev/null
+++ b/drivers/brcmstb/setup.c
@@ -0,0 +1,1119 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/console.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/serial_8250.h>
+#include <linux/platform_device.h>
+#include <linux/ahci_platform.h>
+#include <linux/bootmem.h>
+#include <linux/spinlock.h>
+#include <linux/irqflags.h>
+#include <linux/mm.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/ioport.h>
+#include <linux/compiler.h>
+#include <linux/bmoca.h>
+#include <linux/io.h>
+#include <linux/i2c/i2c-brcmstb.h>
+#include <linux/delay.h>
+#include <linux/time.h>
+#include <linux/version.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/mmc/host.h>
+#include "../drivers/mmc/host/sdhci-brcmstb.h"
+
+#include <linux/brcmstb/brcmstb.h>
+
+#ifndef CONFIG_MTD
+/* squash MTD warning on IKOS builds */
+#define CONFIG_MTD_MAP_BANK_WIDTH_1 1
+#endif
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/map.h>
+
+/* Default SPI flash chip selects to scan at boot time
+   Can be overriden with spics=N kernel boot argument
+*/
+#define EXTRA_SPI_CS		0x00
+
+/***********************************************************************
+ * Platform device setup
+ ***********************************************************************/
+
+#ifdef CONFIG_BRCM_HAS_SATA3
+
+#define SATA_MEM_START		BPHYSADDR(BCHP_SATA_AHCI_GHC_REG_START)
+#define SATA_MEM_SIZE		0x00010000
+
+static struct resource brcm_ahci_resource[] = {
+	[0] = {
+		.start	= SATA_MEM_START,
+		.end	= SATA_MEM_START + SATA_MEM_SIZE - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= BRCM_IRQ_SATA,
+		.end	= BRCM_IRQ_SATA,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static u64 brcm_ahci_dmamask = DMA_BIT_MASK(32);
+
+static int brcm_ahci_init(struct device *dev, void __iomem *addr)
+{
+	brcm_pm_sata3(1);
+	bchip_sata3_init();
+	return 0;
+}
+
+static void brcm_ahci_exit(struct device *dev)
+{
+	brcm_pm_sata3(0);
+}
+
+static int brcm_ahci_suspend(struct device *dev)
+{
+	brcm_pm_sata3(0);
+	return 0;
+}
+
+static int brcm_ahci_resume(struct device *dev)
+{
+	brcm_pm_sata3(1);
+	bchip_sata3_init();
+	return 0;
+}
+
+static struct ahci_platform_data brcm_ahci_pdata = {
+	.init = &brcm_ahci_init,
+	.exit = &brcm_ahci_exit,
+	.suspend = &brcm_ahci_suspend,
+	.resume = &brcm_ahci_resume,
+};
+
+static struct platform_device brcm_ahci_pdev = {
+	.name		= "strict-ahci",
+	.id		= 0,
+	.resource	= brcm_ahci_resource,
+	.num_resources	= ARRAY_SIZE(brcm_ahci_resource),
+	.dev		= {
+		.dma_mask		= &brcm_ahci_dmamask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+		.platform_data		= &brcm_ahci_pdata,
+	},
+};
+
+#endif /* CONFIG_BRCM_HAS_SATA3 */
+
+#define BRCM_16550_PLAT_DEVICE(uart_addr, uart_irq) \
+	{ \
+		.mapbase = BPHYSADDR(uart_addr), \
+		.irq = (uart_irq), \
+		.regshift = 2, \
+		.iotype = UPIO_MEM32, \
+		.flags = UPF_IOREMAP | UPF_SKIP_TEST | UPF_FIXED_TYPE, \
+		.type = PORT_16550A, \
+	},
+
+static struct plat_serial8250_port brcm_16550_ports[] = {
+#ifdef CONFIG_BRCM_UARTA_IS_16550
+BRCM_16550_PLAT_DEVICE(BCHP_UARTA_REG_START, BRCM_IRQ_UARTA)
+#endif
+#ifdef CONFIG_BRCM_UARTB_IS_16550
+BRCM_16550_PLAT_DEVICE(BCHP_UARTB_REG_START, BRCM_IRQ_UARTB)
+#endif
+#ifdef CONFIG_BRCM_UARTC_IS_16550
+BRCM_16550_PLAT_DEVICE(BCHP_UARTC_REG_START, BRCM_IRQ_UARTC)
+#endif
+	{
+		.flags = 0,
+	}
+};
+
+static struct platform_device brcm_16550_uarts = {
+	.name = "serial8250",
+	.dev = {
+		.platform_data = &brcm_16550_ports,
+	},
+};
+
+static inline void brcm_bogus_release(struct device *dev)
+{
+}
+
+#if defined(CONFIG_I2C_BRCMSTB)
+
+static const char bsc_pdev_name[] = "brcmstb-i2c";
+
+#define BRCM_PLAT_DEVICE_DATA(_base, _end, _name, _id, _irq)	\
+	{							\
+			.reg_start = (_base),			\
+			.reg_end  = (_end),			\
+			.clk_rate = 375000,			\
+			.bus_name = (_name),			\
+			.flags = BRCMSTB_I2C_BUS_ENABLE,	\
+			.bus_id = (_id),			\
+			.irq = (_irq),				\
+	},
+
+static struct brcmstb_i2c_platform_data bsc_pdata[] = {
+#ifdef BCHP_BSCA_REG_START
+	BRCM_PLAT_DEVICE_DATA(BCHP_BSCA_REG_START, BCHP_BSCA_REG_END, "BSC_A",
+			      0, -1)
+#endif
+
+#ifdef BCHP_BSCB_REG_START
+	BRCM_PLAT_DEVICE_DATA(BCHP_BSCB_REG_START, BCHP_BSCB_REG_END, "BSC_B",
+			      1, -1)
+#endif
+
+#ifdef BCHP_BSCC_REG_START
+	BRCM_PLAT_DEVICE_DATA(BCHP_BSCC_REG_START, BCHP_BSCC_REG_END, "BSC_C",
+			      2, -1)
+#endif
+
+#ifdef BCHP_BSCD_REG_START
+	BRCM_PLAT_DEVICE_DATA(BCHP_BSCD_REG_START, BCHP_BSCD_REG_END, "BSC_D",
+			      3, -1)
+#endif
+
+#ifdef BCHP_BSCE_REG_START
+	BRCM_PLAT_DEVICE_DATA(BCHP_BSCE_REG_START, BCHP_BSCE_REG_END, "BSC_E",
+			      4, -1)
+#endif
+};
+
+static int __init brcm_add_bsc_master(int pdev_id,
+				struct brcmstb_i2c_platform_data *pdata)
+{
+	struct resource res[2];
+	struct platform_device *pdev;
+
+	memset(&res, 0, sizeof(res));
+	res[0].start = BPHYSADDR(pdata->reg_start);
+	res[0].end = BPHYSADDR(pdata->reg_end);
+	res[0].flags = IORESOURCE_MEM;
+
+	res[1].start = res[1].end = pdata->irq;
+	res[1].flags = IORESOURCE_IRQ;
+
+	pdev = platform_device_alloc("brcmstb-i2c", pdev_id);
+	if (!pdev ||
+	    platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
+	    platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
+	    platform_device_add(pdev)) {
+		platform_device_put(pdev);
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+/*
+ * This function allow to override the default I2C bus speed for given I2C
+ * bus with a command line option.
+ * Format: i2c_bus=bus_id,clkrate (in hz)
+ */
+static int __init brcm_i2c_bus_cmdline(char *str)
+{
+	int ports;
+	int ints[3];
+	int i;
+
+	ports = ARRAY_SIZE(bsc_pdata);
+	get_options(str, 3, ints);
+	if (ints[0] < 2 || ints[1] < 0 || ints[1] > BRCMSTB_I2C_MAX_BUS_ID)
+		return 0;
+
+	for (i = 0; i < ports; i++) {
+		if (bsc_pdata[i].bus_id == ints[1]) {
+			bsc_pdata[ints[1]].clk_rate = ints[2];
+			bsc_pdata[ints[1]].flags =
+				BRCMSTB_I2C_BUS_ENABLE_CMDLINE;
+		} else {
+			/* disable other channels if we have a cmdline argument
+			   let the user choose the channels */
+			if (bsc_pdata[i].flags & BRCMSTB_I2C_BUS_ENABLE)
+				bsc_pdata[i].flags = BRCMSTB_I2C_BUS_DISABLE;
+		}
+	}
+
+	return 1;
+}
+__setup("i2c_bus=", brcm_i2c_bus_cmdline);
+
+#endif /* CONFIG_I2C_BRCMSTB */
+
+#if defined(CONFIG_BRCM_SDIO)
+
+static int nommc;
+
+static int __init nommc_setup(char *str)
+{
+	nommc = 1;
+	return 0;
+}
+
+__setup("nommc", nommc_setup);
+
+static void __init brcm_add_sdio_host(int id, uintptr_t cfg_base,
+	uintptr_t host_base, int irq)
+{
+	struct resource res[3];
+	struct sdhci_brcmstb_pdata pdata;
+
+	if (nommc) {
+		printk(KERN_INFO "SDIO_%d: disabled via command line\n", id);
+		return;
+	}
+	memset(&res, 0, sizeof(res));
+	memset(&pdata, 0, sizeof(pdata));
+	res[0].start = BPHYSADDR(host_base);
+	res[0].end = BPHYSADDR(host_base + 0xff);
+	res[0].flags = IORESOURCE_MEM;
+
+	res[1].start = BPHYSADDR(cfg_base);
+	res[1].end = BPHYSADDR(cfg_base + 0xff);
+	res[1].flags = IORESOURCE_MEM;
+
+	res[2].start = res[2].end = irq;
+	res[2].flags = IORESOURCE_IRQ;
+
+	/* second controller is for eMMC */
+	if (id == 1) {
+		pdata.caps |= (MMC_CAP_NONREMOVABLE | MMC_CAP_8_BIT_DATA);
+		pdata.caps2 |= MMC_CAP2_NO_SLEEP_CMD;
+	}
+	platform_device_register_resndata(NULL, "sdhci-brcmstb", id, res,
+					ARRAY_SIZE(res), &pdata,
+					sizeof(pdata));
+}
+
+#endif /* defined(CONFIG_BRCM_SDIO) */
+
+#define CAP_ACTIVE		0x01
+#define CAP_LAST		0x02
+#define CAP_TYPE		0x0c
+#define CAP_TYPE_SHIFT		0x02
+#define CAP_TYPE_EHCI		0x00
+#define CAP_TYPE_OHCI		0x01
+#define CAP_ADDR		0xffffff00
+
+static void __init brcm_add_usb_host(int type, int id, uintptr_t base)
+{
+	struct resource res[2];
+	struct platform_device *pdev;
+	static const u64 usb_dmamask = ~(u32)0;
+#ifdef CONFIG_BRCM_USB_DISABLE_MASK
+	const unsigned long usb_disable_mask = CONFIG_BRCM_USB_DISABLE_MASK;
+#else
+	const unsigned long usb_disable_mask = 0x00;
+#endif
+	const int ehci_irqlist[] = BRCM_IRQLIST_EHCI;
+	const int ohci_irqlist[] = BRCM_IRQLIST_OHCI;
+
+	if (usb_disable_mask & (1 << id))
+		return;
+
+	memset(&res, 0, sizeof(res));
+	res[0].start = BPHYSADDR(base);
+	res[0].end = BPHYSADDR(base + 0xff);
+	res[0].flags = IORESOURCE_MEM;
+
+	res[1].flags = IORESOURCE_IRQ;
+
+	if (type == CAP_TYPE_EHCI) {
+		res[1].start = res[1].end = ehci_irqlist[id];
+		pdev = platform_device_alloc("ehci-brcm", id);
+	} else {
+		res[1].start = res[1].end = ohci_irqlist[id];
+		pdev = platform_device_alloc("ohci-brcm", id);
+	}
+
+	platform_device_add_resources(pdev, res, 2);
+
+	pdev->dev.dma_mask = (u64 *)&usb_dmamask;
+	pdev->dev.coherent_dma_mask = 0xffffffff;
+
+#if defined(CONFIG_BCM7425B0) || defined(CONFIG_BCM7435B0)
+	/* SWLINUX-2259: Prevent OHCI from doing DMA to memc1 */
+	if (type == CAP_TYPE_OHCI) {
+		static const u64 lowmem_dma_mask = DMA_BIT_MASK(31);
+		pdev->dev.dma_mask = (u64 *)&lowmem_dma_mask;
+		pdev->dev.coherent_dma_mask = (u32)lowmem_dma_mask;
+	}
+#endif
+
+	platform_device_add(pdev);
+}
+
+static void __init brcm_add_usb_hosts(void)
+{
+#if defined(CONFIG_BRCM_HAS_USB_CAPS)
+	unsigned long caplist[] = { BCHP_USB_CAPS_REG_START,
+#if defined(BCHP_USB1_CAPS_REG_START)
+				    BCHP_USB1_CAPS_REG_START,
+#endif
+				    0 };
+	unsigned long capp, cap;
+	int i, ehci_id = 0, ohci_id = 0;
+
+	/* The second USB is OTP'd out */
+	if (BRCM_PROD_ID() == 0x74285)
+		caplist[1] = 0;
+
+	for (i = 0; caplist[i] != 0; i++) {
+		capp = caplist[i];
+		do {
+			cap = BDEV_RD(capp);
+			capp += 4;
+
+			switch ((cap & CAP_TYPE) >> CAP_TYPE_SHIFT) {
+			case CAP_TYPE_EHCI:
+				if (cap & CAP_ACTIVE)
+					brcm_add_usb_host(CAP_TYPE_EHCI,
+						ehci_id, cap & CAP_ADDR);
+				ehci_id++;
+				break;
+			case CAP_TYPE_OHCI:
+				if (cap & CAP_ACTIVE)
+					brcm_add_usb_host(CAP_TYPE_OHCI,
+						ohci_id, cap & CAP_ADDR);
+				ohci_id++;
+				break;
+			}
+#if defined(CONFIG_BCM7425B0) || defined(CONFIG_BCM7231B0) || \
+	defined(CONFIG_BCM7344B0) || defined(CONFIG_BCM7346B0) || \
+	defined(CONFIG_BCM7584A0)
+		/* bug: incorrect CAP_LAST bit on some chips */
+		} while (capp != (caplist[i] + 0x20));
+#else
+		} while (!(cap & CAP_LAST));
+#endif
+	}
+
+#else /* CONFIG_BRCM_HAS_USB_CAPS */
+
+#define USB_BASE(shortname)	BCHP_##shortname##_REG_START
+
+#if defined(BCHP_USB_EHCI_REG_START)
+	brcm_add_usb_host(CAP_TYPE_EHCI, 0, USB_BASE(USB_EHCI));
+#endif
+#if defined(BCHP_USB_EHCI1_REG_START)
+	brcm_add_usb_host(CAP_TYPE_EHCI, 1, USB_BASE(USB_EHCI1));
+#endif
+#if defined(BCHP_USB_EHCI2_REG_START)
+	brcm_add_usb_host(CAP_TYPE_EHCI, 2, USB_BASE(USB_EHCI2));
+#endif
+#if defined(BCHP_USB_OHCI_REG_START)
+	brcm_add_usb_host(CAP_TYPE_OHCI, 0, USB_BASE(USB_OHCI));
+#endif
+#if defined(BCHP_USB_OHCI1_REG_START)
+	brcm_add_usb_host(CAP_TYPE_OHCI, 1, USB_BASE(USB_OHCI1));
+#endif
+#if defined(BCHP_USB_OHCI2_REG_START)
+	brcm_add_usb_host(CAP_TYPE_OHCI, 2, USB_BASE(USB_OHCI2));
+#endif
+#if defined(BCHP_USB1_EHCI_REG_START)
+	brcm_add_usb_host(CAP_TYPE_EHCI, 2, USB_BASE(USB1_EHCI));
+#endif
+#if defined(BCHP_USB1_EHCI1_REG_START)
+	brcm_add_usb_host(CAP_TYPE_EHCI, 3, USB_BASE(USB1_EHCI1));
+#endif
+#if defined(BCHP_USB1_OHCI_REG_START)
+	brcm_add_usb_host(CAP_TYPE_OHCI, 2, USB_BASE(USB1_OHCI));
+#endif
+#if defined(BCHP_USB1_OHCI1_REG_START)
+	brcm_add_usb_host(CAP_TYPE_OHCI, 3, USB_BASE(USB1_OHCI1));
+#endif
+
+#endif /* CONFIG_BRCM_HAS_USB_CAPS */
+}
+
+#if defined(CONFIG_BRCM_HAS_GENET)
+static void __init brcm_override_genet_settings(
+	struct bcmemac_platform_data *pd)
+{
+	/* update platform_data with any settings from CFE */
+
+	if (strcmp(brcm_eth0_phy, "INT") == 0)
+		pd->phy_type = BRCM_PHY_TYPE_INT;
+	else if (strcmp(brcm_eth0_phy, "MII") == 0)
+		pd->phy_type = BRCM_PHY_TYPE_EXT_MII;
+	else if (strcmp(brcm_eth0_phy, "RVMII") == 0)
+		pd->phy_type = BRCM_PHY_TYPE_EXT_RVMII;
+	else if (strcmp(brcm_eth0_phy, "RGMII") == 0)
+		pd->phy_type = BRCM_PHY_TYPE_EXT_RGMII;
+	else if (strcmp(brcm_eth0_phy, "RGMII_NO_ID") == 0)
+		pd->phy_type = BRCM_PHY_TYPE_EXT_RGMII_NO_ID;
+
+	if (brcm_eth0_speed)
+		pd->phy_speed = brcm_eth0_speed;
+#if defined(CONFIG_DREAMBOX_DM7080) || defined(CONFIG_DREAMBOX_DM820)
+	BDEV_UNSET(0xb80e18, 0x3f << 4);
+	BDEV_SET(0xb80e18, 0x14 << 4);
+#endif
+	/* note: this completely bypasses probing for a "live" PHY chip */
+	if (brcm_eth0_no_mdio)
+		pd->phy_id = BRCM_PHY_ID_NONE;
+	else if (pd->phy_type != BRCM_PHY_TYPE_INT) {
+		if (strcmp(brcm_eth0_phyaddr, "probe") == 0)
+			pd->phy_id = BRCM_PHY_ID_AUTO;
+		else {
+			if (kstrtoint(brcm_eth0_phyaddr, 10, &pd->phy_id) ||
+			    pd->phy_id < 0 || pd->phy_id > 31) {
+				pr_warn("Invalid ETH0_PHYADDR, ignoring\n");
+				pd->phy_id = 1;
+			}
+		}
+	}
+}
+
+static void __init brcm_register_genet(int id, struct bcmemac_platform_data *pd)
+{
+	struct resource res[3];
+	struct platform_device *pdev;
+
+	memset(&res, 0, sizeof(res));
+	res[0].start = BPHYSADDR(pd->base_reg);
+	res[0].end = BPHYSADDR(pd->base_reg + 0x4fff);
+	res[0].flags = IORESOURCE_MEM;
+
+	res[1].start = res[1].end = pd->irq0;
+	res[1].flags = IORESOURCE_IRQ;
+
+	res[2].start = res[2].end = pd->irq1;
+	res[2].flags = IORESOURCE_IRQ;
+
+	brcm_alloc_macaddr(pd->macaddr);
+
+	pdev = platform_device_alloc("bcmgenet", id);
+	platform_device_add_resources(pdev, res, 3);
+	platform_device_add_data(pdev, pd, sizeof(*pd));
+	platform_device_add(pdev);
+}
+#endif /* defined(CONFIG_BRCM_HAS_GENET) */
+
+#if defined(CONFIG_BRCM_HAS_MOCA)
+static void __init brcm_register_moca(int enet_id)
+{
+	struct resource res[2];
+	struct platform_device *pdev;
+	struct moca_platform_data pdata;
+	u8 macaddr[ETH_ALEN];
+	u32 val;
+
+	bchip_moca_init();
+
+	memset(&res, 0, sizeof(res));
+	res[0].start = BPHYSADDR(BCHP_DATA_MEM_REG_START);
+#ifdef BCHP_MOCA_HOSTMISC_MMP_REG_END
+	res[0].end = BPHYSADDR(BCHP_MOCA_HOSTMISC_MMP_REG_END) + 3;
+#else
+	res[0].end = BPHYSADDR(BCHP_MOCA_HOSTMISC_REG_END) + 3;
+#endif
+	res[0].flags = IORESOURCE_MEM;
+
+	res[1].start = BRCM_IRQ_MOCA;
+	res[1].flags = IORESOURCE_IRQ;
+
+	brcm_alloc_macaddr(macaddr);
+	mac_to_u32(&pdata.macaddr_hi, &pdata.macaddr_lo, macaddr);
+
+	strcpy(pdata.enet_name, "bcmgenet");
+	pdata.enet_id = enet_id;
+	pdata.bcm3450_i2c_addr = 0x70;
+	pdata.bcm3450_i2c_base = brcm_moca_i2c_base;
+
+	val = BDEV_RD(BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID);
+	/* Handle 4 vs. 5 digits chip ID */
+	if (val >> 28)
+		pdata.chip_id = (val >> 16) << 16;
+	else
+		pdata.chip_id = (val >> 8) << 8;
+	pdata.chip_id |= (BRCM_CHIP_REV() + 0xa0);
+	pdata.hw_rev = CONFIG_BRCM_MOCA_VERS;
+	pdata.rf_band = brcm_moca_rf_band;
+
+	if (brcm_moca_i2c_base == 0) {
+		printk(KERN_WARNING
+			"error: bmoca I2C base addr is not set\n");
+		return;
+	}
+
+	pdev = platform_device_alloc("bmoca", 0);
+	platform_device_add_resources(pdev, res, 2);
+	platform_device_add_data(pdev, &pdata, sizeof(pdata));
+	platform_device_add(pdev);
+}
+#else /* defined(CONFIG_BRCM_HAS_MOCA) */
+static inline void brcm_register_moca(int enet_id) { }
+#endif /* defined(CONFIG_BRCM_HAS_MOCA) */
+
+static int __init platform_devices_setup(void)
+{
+	int i;
+
+#ifdef CONFIG_I2C_BRCMSTB
+	int j = 0;
+	int ret = 0;
+#endif
+
+#ifdef CONFIG_OF
+	return 0;
+#endif
+
+	/* UARTs */
+
+	brcm_16550_ports[0].uartclk = brcm_base_baud0 * 16;
+	for (i = 1; i < ARRAY_SIZE(brcm_16550_ports) - 1; i++)
+		brcm_16550_ports[i].uartclk = brcm_base_baud * 16;
+	platform_device_register(&brcm_16550_uarts);
+
+#if defined(CONFIG_BRCM_IKOS)
+	/* the remaining devices do not exist in emulation */
+	return 0;
+#endif
+
+	/* USB controllers */
+
+	if (brcm_usb_enabled) {
+		bchip_usb_init();
+		brcm_add_usb_hosts();
+	}
+
+	/* Network interfaces */
+
+#if defined(CONFIG_BRCM_HAS_GENET)
+	brcm_override_genet_settings(&genet_pdata[0]);
+
+	for (i = 0; i < BRCM_MAX_GENET; i++) {
+		struct bcmemac_platform_data *pd = &genet_pdata[i];
+
+		if (pd->phy_type == BRCM_PHY_TYPE_MOCA)
+			brcm_register_moca(i);
+		if (pd->base_reg)
+			brcm_register_genet(i, pd);
+	}
+#endif /* defined(CONFIG_BRCM_HAS_GENET) */
+
+#if defined(CONFIG_BRCM_SDIO)
+	i = 0;
+#if defined(CONFIG_DREAMBOX)
+	/* Need to reverse the probe order */
+	brcm_add_sdio_host(i++, BCHP_SDIO_1_CFG_REG_START,
+		BCHP_SDIO_1_HOST_REG_START, BRCM_IRQ_SDIO1);
+#endif /* defined(CONFIG_DREAMBOX) */
+
+	brcm_add_sdio_host(i++, BCHP_SDIO_0_CFG_REG_START,
+		BCHP_SDIO_0_HOST_REG_START, BRCM_IRQ_SDIO0);
+
+#if !defined(CONFIG_DREAMBOX) && defined(BCHP_SDIO_1_CFG_REG_START)
+	brcm_add_sdio_host(i++, BCHP_SDIO_1_CFG_REG_START,
+		BCHP_SDIO_1_HOST_REG_START, BRCM_IRQ_SDIO1);
+#endif /* defined(BCHP_SDIO_1_CFG_REG_START) */
+
+#endif /* defined(CONFIG_BRCM_SDIO) */
+
+	/* AHCI */
+#if defined(CONFIG_BRCM_HAS_SATA3)
+	if (brcm_sata_enabled)
+		platform_device_register(&brcm_ahci_pdev);
+#endif
+
+#if defined(CONFIG_I2C_BRCMSTB)
+	for (i = 0; i < ARRAY_SIZE(bsc_pdata); i++) {
+		if (bsc_pdata[i].flags & (BRCMSTB_I2C_BUS_ENABLE |
+					 BRCMSTB_I2C_BUS_ENABLE_CMDLINE)) {
+			ret = brcm_add_bsc_master(j++, &bsc_pdata[i]);
+			if (ret < 0) {
+				printk(KERN_WARNING
+					"%s: cannot register bsc master chan %d"
+				       "(error %d)\n", __func__, i, ret);
+				break;
+			}
+
+		}
+	}
+#endif
+
+	return 0;
+}
+
+arch_initcall(platform_devices_setup);
+
+#if defined(CONFIG_BRCM_FLASH)
+
+/***********************************************************************
+ * Flash device setup
+ ***********************************************************************/
+
+#if defined(BCHP_EBI_CS_BASE_5)
+#define NUM_CS			6
+#elif defined(BCHP_EBI_CS_BASE_4)
+#define NUM_CS			5
+#elif defined(BCHP_EBI_CS_BASE_3)
+#define NUM_CS			4
+#elif defined(BCHP_EBI_CS_BASE_2)
+#define NUM_CS			3
+#else
+#define NUM_CS			2
+#endif
+
+#define TYPE_NONE		0
+#define TYPE_NOR		1
+#define TYPE_NAND		2
+#define TYPE_SPI		3
+#define TYPE_MAX		TYPE_SPI
+
+static const char type_names[][8] = { "NONE", "NOR", "NAND", "SPI" };
+
+struct ebi_cs_info {
+	int			type;
+	unsigned long		start;
+	unsigned long		len;
+	int			width;
+	unsigned long		base_reg;
+	unsigned long		config_reg;
+};
+
+static struct ebi_cs_info cs_info[NUM_CS];
+
+#ifdef CONFIG_BRCM_HAS_SPI
+static int __init brcm_setup_spi_flash(int cs, int bus_num, int nr_parts,
+	struct mtd_partition *parts)
+{
+	struct spi_board_info board_info;
+	struct flash_platform_data *pdata;
+	struct spi_master *master;
+
+	master = spi_busnum_to_master(bus_num);
+	if (!master) {
+		printk(KERN_WARNING "%s: can't locate SPI master\n",
+			__func__);
+		return -ENODEV;
+	}
+
+	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
+
+	pdata->nr_parts = nr_parts;
+	pdata->parts = parts;
+
+	memset(&board_info, 0, sizeof(board_info));
+
+#if defined(CONFIG_DREAMBOX)
+    #if defined(CONFIG_DREAMBOX_DM520)
+	strcpy(board_info.modalias, "w25q128bv");
+    #else
+	strcpy(board_info.modalias, "mx25l12805d");
+    #endif
+#else
+	strcpy(board_info.modalias, "m25p80");
+#endif
+	board_info.bus_num = bus_num;
+	board_info.chip_select = cs;
+	board_info.mode = SPI_MODE_3;
+	board_info.platform_data = pdata;
+
+	if (spi_new_device(master, &board_info) == NULL) {
+		printk(KERN_WARNING "%s: can't add SPI device\n",
+			__func__);
+		kfree(pdata);
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static int __init brcm_setup_spi_master(int cs, int bus_id)
+{
+	struct resource res[4];
+	struct brcmspi_platform_data pdata;
+	struct platform_device *pdev;
+	memset(&pdata, 0, sizeof(pdata));
+
+	pdata.flash_cs = cs;
+
+	memset(&res, 0, sizeof(res));
+	res[0].start = BPHYSADDR(BCHP_HIF_MSPI_REG_START);
+	res[0].end = BPHYSADDR(BCHP_HIF_MSPI_REG_END) + 3;
+	res[0].flags = IORESOURCE_MEM;
+
+	res[1].start = BRCM_IRQ_HIF_SPI;
+	res[1].end = BRCM_IRQ_HIF_SPI;
+	res[1].flags = IORESOURCE_IRQ;
+
+	res[2].start = BPHYSADDR(BCHP_BSPI_REG_START);
+	res[2].end = BPHYSADDR(BCHP_BSPI_REG_END) + 3;
+	res[2].flags = IORESOURCE_MEM;
+
+	res[3].start = BPHYSADDR(BCHP_BSPI_RAF_REG_START);
+	res[3].end = BPHYSADDR(BCHP_BSPI_RAF_REG_END) + 3;
+	res[3].flags = IORESOURCE_MEM;
+
+	pdev = platform_device_alloc("spi_brcmstb", bus_id);
+	if (!pdev ||
+	    platform_device_add_resources(pdev, res, 4) ||
+	    platform_device_add_data(pdev, &pdata, sizeof(pdata)) ||
+	    platform_device_add(pdev)) {
+		platform_device_put(pdev);
+		return -ENODEV;
+	}
+	return 0;
+}
+#endif
+
+static int __initdata extra_spi_cs = EXTRA_SPI_CS;
+
+static int __init spics_setup(char *str)
+{
+	if (!*str || !*(str+1))
+		return 0;
+	str++;
+	get_option(&str, &extra_spi_cs);
+	return 0;
+}
+
+__setup("spics", spics_setup);
+
+static void __init brcm_setup_cs(int cs, int nr_parts,
+	struct mtd_partition *parts)
+{
+	struct platform_device *pdev;
+
+	switch (cs_info[cs].type) {
+	case TYPE_NOR: {
+#ifdef CONFIG_BRCM_HAS_NOR
+		struct physmap_flash_data pdata;
+		struct resource res;
+		static int nor_id;
+
+		memset(&res, 0, sizeof(res));
+		memset(&pdata, 0, sizeof(pdata));
+
+		pdata.width = cs_info[cs].width;
+		pdata.nr_parts = nr_parts;
+		pdata.parts = parts;
+
+		res.start = cs_info[cs].start;
+		res.end = cs_info[cs].start + cs_info[cs].len - 1;
+		res.flags = IORESOURCE_MEM;
+
+		pdev = platform_device_alloc("physmap-flash", nor_id++);
+		if (!pdev ||
+		    platform_device_add_resources(pdev, &res, 1) ||
+		    platform_device_add_data(pdev, &pdata, sizeof(pdata)) ||
+		    platform_device_add(pdev))
+			platform_device_put(pdev);
+#endif
+		break;
+	}
+	case TYPE_NAND: {
+		struct brcmnand_platform_data pdata;
+		static int nand_id;
+
+		pdata.chip_select = cs;
+		pdata.nr_parts = nr_parts;
+		pdata.parts = parts;
+
+		pdev = platform_device_alloc("brcmnand", nand_id++);
+		if (!pdev ||
+		    platform_device_add_data(pdev, &pdata, sizeof(pdata)) ||
+		    platform_device_add(pdev))
+			platform_device_put(pdev);
+		break;
+	}
+	case TYPE_SPI: {
+#ifdef CONFIG_BRCM_HAS_SPI
+		const int bus_num = 0;
+		static int spi_master_registered;
+		int ret;
+
+		if (!spi_master_registered) {
+			/* spi master must know about all CSs used by
+			   spi interface */
+			int spi_cs = (1 << cs) | extra_spi_cs;
+			ret = brcm_setup_spi_master(spi_cs, bus_num);
+			if (ret) {
+				printk(KERN_WARNING
+					"%s: can't register SPI master "
+					"(error %d)\n", __func__, ret);
+				break;
+			}
+			spi_master_registered = 1;
+		}
+
+		ret = brcm_setup_spi_flash(cs, bus_num, nr_parts, parts);
+		if (ret < 0) {
+			printk(KERN_WARNING
+				"%s: can't register SPI flash (error %d)\n",
+				__func__, ret);
+			break;
+		}
+#endif
+		break;
+	}
+	default:
+		BUG();
+	}
+}
+
+static int __initdata noflash;
+static int __initdata nandcs[NUM_CS];
+
+void ebi_restore_settings(void)
+{
+	int i;
+	for (i = 0; i < NUM_CS; i++) {
+		BDEV_WR(BCHP_EBI_CS_BASE_0 + (i * 8), cs_info[i].base_reg);
+#ifdef BCHP_EBI_CS_CONFIG_0
+		BDEV_WR(BCHP_EBI_CS_CONFIG_0 + (i * 8), cs_info[i].config_reg);
+#endif
+	}
+}
+
+static struct map_info brcm_dummy_map = {
+	.name			= "DUMMY",
+};
+
+static int __init brcmstb_mtd_setup(void)
+{
+	struct mtd_partition *parts;
+	int nr_parts;
+	int i, first = -1, primary = -1, primary_type = TYPE_NAND;
+
+#ifdef CONFIG_OF
+	return 0;
+#endif
+	if (noflash)
+		return 0;
+
+	nr_parts = board_get_partition_map(&parts);
+	if (nr_parts <= 0) {
+		struct mtd_info *mtd;
+
+		/*
+		 * mtd0 is normally the rootfs partition.  If it is missing,
+		 * create a dummy partition so that any person or script
+		 * trying to mount or erase mtd0 does not corrupt the
+		 * whole flash device.
+		 */
+		mtd = do_map_probe("map_absent", &brcm_dummy_map);
+		if (mtd)
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)
+			mtd_device_register(mtd, NULL, 0);
+#else
+			add_mtd_device(mtd);
+#endif
+
+		printk(KERN_WARNING
+			"warning: unable to build a flash partition map, "
+			"using entire device\n");
+
+		nr_parts = 0;
+		parts = NULL;
+	}
+
+	/* parse CFE FLASH_TYPE variable */
+	for (i = TYPE_NOR; i <= TYPE_MAX; i++)
+		if (strcmp(brcm_mtd_flash_type, type_names[i]) == 0)
+			primary_type = i;
+
+	/* scan each chip select to see what (if anything) lives there */
+	for (i = 0; i < NUM_CS; i++) {
+		u32 base, size, config __maybe_unused;
+
+		cs_info[i].type = TYPE_NONE;
+
+		base = BDEV_RD(BCHP_EBI_CS_BASE_0 + (i * 8));
+		size = base & 0x0f;
+
+		cs_info[i].base_reg = base;
+		cs_info[i].start = (base >> (13 + size)) << (13 + size);
+		cs_info[i].len = 8192UL << (base & 0xf);
+
+#ifdef BCHP_EBI_CS_CONFIG_0
+		config = BDEV_RD(BCHP_EBI_CS_CONFIG_0 + (i * 8));
+		cs_info[i].config_reg = config;
+		if (config & BCHP_EBI_CS_CONFIG_0_enable_MASK)
+			cs_info[i].type = TYPE_NOR;
+
+		if (config & BCHP_EBI_CS_CONFIG_0_dest_size_MASK)
+			cs_info[i].width = 2;
+		else
+			cs_info[i].width = 1;
+#endif
+#ifdef BCHP_EBI_CS_SPI_SELECT
+		/*
+		 * bits 7:0 - owned by HW (at most one bit active)
+		 * bits 23:16 - owned by SW (any number of '1' bits OK)
+		 * A '1' in either position means there is a SPI chip there.
+		 *
+		 * 65nm chips don't have SW bits 15:8 so EXTRA_SPI_CS
+		 * should be set at compile time for multiple SPI flashes.
+		 */
+		if ((BDEV_RD(BCHP_EBI_CS_SPI_SELECT) & (0x101 << i)) ||
+				(extra_spi_cs & (0x01 << i)))
+			cs_info[i].type = TYPE_SPI;
+#endif
+#ifdef BCHP_NAND_CS_NAND_SELECT
+		if (BDEV_RD(BCHP_NAND_CS_NAND_SELECT) & (0x100 << i))
+			cs_info[i].type = TYPE_NAND;
+#endif
+
+		if (cs_info[i].type != TYPE_NAND && nandcs[i] != 0) {
+			cs_info[i].type = TYPE_NAND;
+		} else {
+			/*
+			 * nandcs = ineligible to be primary.  The partition
+			 * information reported by CFE is not for the NAND
+			 * flash if CFE doesn't know the system has a
+			 * NAND flash.
+			 */
+			if (primary == -1 && primary_type == cs_info[i].type)
+				primary = i;
+		}
+		if (first == -1 && cs_info[i].type != TYPE_NONE)
+			first = i;
+	}
+
+	if (primary == -1) {
+		if (first == -1) {
+			printk(KERN_INFO "EBI: No flash devices detected\n");
+			return -ENODEV;
+		}
+		primary = first;
+		primary_type = cs_info[primary].type;
+	}
+
+	/* set up primary first, so that it owns mtd0/mtd1/(mtd2) */
+	printk(KERN_INFO "EBI CS%d: setting up %s flash (primary)\n", primary,
+		type_names[primary_type]);
+	brcm_setup_cs(primary, nr_parts, parts);
+
+	for (i = 0; i < NUM_CS; i++) {
+		if (i != primary && cs_info[i].type != TYPE_NONE) {
+			printk(KERN_INFO "EBI CS%d: setting up %s flash\n", i,
+				type_names[cs_info[i].type]);
+			brcm_setup_cs(i, 0, NULL);
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * late_initcall means the flash drivers are already loaded, so we control
+ * the order in which the /dev/mtd* devices get created.
+ */
+late_initcall(brcmstb_mtd_setup);
+
+static int __init noflash_setup(char *str)
+{
+	noflash = 1;
+	return 0;
+}
+
+__setup("noflash", noflash_setup);
+
+static int __init nandcs_setup(char *str)
+{
+	int opts[NUM_CS + 1], i;
+
+	if (*str == 0)
+		return 0;
+	get_options(str + 1, NUM_CS, opts);
+
+	for (i = 0; i < opts[0]; i++) {
+		int cs = opts[i + 1];
+		if ((cs >= 0) && (cs < NUM_CS))
+			nandcs[cs] = 1;
+	}
+	return 0;
+}
+
+__setup("nandcs", nandcs_setup);
+
+#else /* defined(CONFIG_BRCM_FLASH) */
+
+void ebi_restore_settings(void)
+{
+}
+
+#endif /* defined(CONFIG_BRCM_FLASH) */
+
+/***********************************************************************
+ * Miscellaneous platform-specific functions
+ ***********************************************************************/
+
+void __init bus_error_init(void)
+{
+}
+
+void brcm_machine_restart(const char *command)
+{
+/* PR21527 - Fix SMP reboot problem */
+#ifdef CONFIG_SMP
+	smp_send_stop();
+	udelay(10);
+#endif
+
+#ifdef BCHP_SUN_TOP_CTRL_SW_RESET
+	BDEV_WR_F_RB(SUN_TOP_CTRL_RESET_CTRL, master_reset_en, 1);
+	BDEV_WR_F_RB(SUN_TOP_CTRL_SW_RESET, chip_master_reset, 1);
+#else
+	BDEV_WR_F_RB(SUN_TOP_CTRL_RESET_SOURCE_ENABLE,
+		sw_master_reset_enable, 1);
+	BDEV_WR_F_RB(SUN_TOP_CTRL_SW_MASTER_RESET, chip_master_reset, 1);
+#endif
+
+	while (1)
+		;
+}
+
+void brcm_machine_halt(void)
+{
+	/* may be S3 cold boot */
+	brcm_pm_s3_cold_boot();
+
+	local_irq_disable();
+	while (1)
+		;
+}
+
+char *__devinit brcmstb_pcibios_setup(char *str)
+{
+	/* implement "pci=off" command line option */
+	if (!strcmp(str, "off")) {
+		brcm_sata_enabled = 0;
+		brcm_pcie_enabled = 0;
+		return NULL;
+	}
+	return str;
+}
diff --git a/drivers/brcmstb/sysfs.c b/drivers/brcmstb/sysfs.c
new file mode 100644
index 0000000..7e65ecf
--- /dev/null
+++ b/drivers/brcmstb/sysfs.c
@@ -0,0 +1,316 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/sysfs.h>
+#include <linux/device.h>
+#include <linux/ctype.h>
+#include <linux/platform_device.h>
+
+#ifdef CONFIG_MIPS
+#include <asm/cpu-info.h>
+#include <asm/r4kcache.h>
+#include <asm/mipsregs.h>
+#endif
+
+#include <linux/brcmstb/brcmstb.h>
+
+atomic_t brcm_unaligned_fp_count = ATOMIC_INIT(0);
+atomic_t brcm_rdhwr_count = ATOMIC_INIT(0);
+
+static struct platform_device *brcmstb_pdev;
+
+static ssize_t show_unaligned_fp_count(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%d\n",
+		atomic_read(&brcm_unaligned_fp_count));
+}
+
+static ssize_t show_rdhwr_count(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%d\n",
+		atomic_read(&brcm_rdhwr_count));
+}
+
+static ssize_t show_chip_id(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%04x\n", BRCM_CHIP_ID());
+}
+
+static ssize_t show_chip_rev(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%02X\n", BRCM_CHIP_REV() + 0xa0);
+}
+
+static ssize_t show_bmem(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	int idx = 0;
+	unsigned long addr = 0, size = 0;
+	const char *name = attr->attr.name;
+
+	while (*name != 0) {
+		if (isdigit(*name)) {
+			idx = simple_strtoul(name, NULL, 10);
+			break;
+		}
+		name++;
+	}
+	bmem_region_info(idx, &addr, &size);
+
+	return snprintf(buf, PAGE_SIZE, "0x%08lx 0x%08lx\n", addr, size);
+}
+
+static ssize_t show_ocap_partition(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "0x%08lx 0x%08lx\n",
+		brcm_mtd_ocap_start, brcm_mtd_ocap_len);
+}
+
+static ssize_t show_cfe_boardname(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%s\n", brcm_cfe_boardname);
+}
+
+#ifdef CONFIG_MIPS
+static ssize_t show_cache_max_writeback(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	struct brcm_cache_info info;
+	brcm_get_cache_info(&info);
+	return snprintf(buf, PAGE_SIZE, "%d\n", info.max_writeback);
+}
+
+static ssize_t show_cache_max_writethrough(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	struct brcm_cache_info info;
+	brcm_get_cache_info(&info);
+	return snprintf(buf, PAGE_SIZE, "%d\n", info.max_writethrough);
+}
+
+static ssize_t show_cache_prefetch_enabled(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	struct brcm_cache_info info;
+	brcm_get_cache_info(&info);
+	return snprintf(buf, PAGE_SIZE, "%d\n", info.prefetch_enabled);
+}
+
+static ssize_t show_cpu_name(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%s\n", __cpu_name[0]);
+}
+
+static ssize_t show_cp0_config_regs(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "0x%08x 0x%08x 0x%08x\n",
+		__read_32bit_c0_register($16, 0),
+		__read_32bit_c0_register($16, 1),
+		__read_32bit_c0_register($16, 7));
+}
+
+static inline ssize_t show_cp0_brcm_regs(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE,
+		"0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
+		__read_32bit_c0_register($22, 0),
+		__read_32bit_c0_register($22, 1),
+		__read_32bit_c0_register($22, 2),
+		__read_32bit_c0_register($22, 3),
+		__read_32bit_c0_register($22, 4),
+		__read_32bit_c0_register($22, 5),
+		__read_32bit_c0_register($22, 6),
+		__read_32bit_c0_register($22, 7));
+}
+
+static ssize_t show_cpu_khz(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%ld\n", brcm_adj_cpu_khz);
+}
+#endif
+
+static inline ssize_t dump_core_regs(unsigned long cbr,
+	const int *regs, int n_regs, char *buf)
+{
+	int i, bytes = 0;
+
+	for (i = 0; i < n_regs; i++)
+		bytes += snprintf(&buf[bytes], PAGE_SIZE - bytes, "0x%08lx ",
+			DEV_RD(cbr + regs[i]));
+	buf[bytes - 1] = '\n';
+	return bytes;
+}
+
+#ifdef CONFIG_CPU_BMIPS3300
+static ssize_t show_bmips3300_core_regs(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	const int regs[] = { BMIPS_RAC_CONFIG, BMIPS_RAC_ADDRESS_RANGE };
+
+	return dump_core_regs(__BMIPS_GET_CBR(), regs, ARRAY_SIZE(regs), buf);
+}
+#endif
+
+#ifdef CONFIG_CPU_BMIPS4380
+static ssize_t show_bmips4380_core_regs(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	const int regs[] = {
+		BMIPS_RAC_CONFIG, BMIPS_RAC_ADDRESS_RANGE, BMIPS_RAC_CONFIG_1,
+		BMIPS_L2_CONFIG, BMIPS_LMB_CONTROL, BMIPS_SYSTEM_BASE,
+		BMIPS_PERF_GLOBAL_CONTROL, BMIPS_PERF_CONTROL_0,
+		BMIPS_PERF_CONTROL_1, BMIPS_PERF_COUNTER_0,
+		BMIPS_PERF_COUNTER_1, BMIPS_PERF_COUNTER_2,
+		BMIPS_PERF_COUNTER_3, BMIPS_RELO_VECTOR_CONTROL_0,
+		BMIPS_RELO_VECTOR_CONTROL_1 };
+
+	return dump_core_regs(__BMIPS_GET_CBR(), regs, ARRAY_SIZE(regs), buf);
+}
+#endif
+
+/* Display secondary cache module settings */
+
+#if defined(CONFIG_BRCM_ZSCM_L2)
+
+static ssize_t show_zscm_regs(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE,
+		"0x%08lx 0x%08lx 0x%08lx 0x%08lx 0x%08lx "
+		"0x%08lx 0x%08lx 0x%08lx 0x%08lx 0x%08lx\n",
+		bmips_read_zscm_reg(0x00), bmips_read_zscm_reg(0x10),
+		bmips_read_zscm_reg(0x20), bmips_read_zscm_reg(0x30),
+		bmips_read_zscm_reg(0x40), bmips_read_zscm_reg(0x50),
+		bmips_read_zscm_reg(0x60), bmips_read_zscm_reg(0x70),
+		bmips_read_zscm_reg(0x80), bmips_read_zscm_reg(0x90));
+}
+#endif
+
+static struct device_attribute brcmstb_attr_list[] = {
+	__ATTR(unaligned_fp_count, 0444, show_unaligned_fp_count, NULL),
+	__ATTR(rdhwr_count, 0444, show_rdhwr_count, NULL),
+	__ATTR(chip_id, 0444, show_chip_id, NULL),
+	__ATTR(chip_rev, 0444, show_chip_rev, NULL),
+	__ATTR(ocap_partition, 0444, show_ocap_partition, NULL),
+	__ATTR(cfe_boardname, 0444, show_cfe_boardname, NULL),
+#if defined(CONFIG_MIPS)
+	__ATTR(cache_max_writeback, 0444, show_cache_max_writeback, NULL),
+	__ATTR(cache_max_writethrough, 0444, show_cache_max_writethrough, NULL),
+	__ATTR(cache_prefetch_enabled, 0444, show_cache_prefetch_enabled, NULL),
+	__ATTR(cpu_name, 0444, show_cpu_name, NULL),
+	__ATTR(cp0_config_regs, 0444, show_cp0_config_regs, NULL),
+	__ATTR(cpu_khz, 0444, show_cpu_khz, NULL),
+#endif
+#if   defined(CONFIG_CPU_BMIPS3300)
+	__ATTR(cp0_brcm_regs, 0444, show_cp0_brcm_regs, NULL),
+	__ATTR(bmips3300_core_regs, 0444, show_bmips3300_core_regs, NULL),
+#elif defined(CONFIG_CPU_BMIPS4380)
+	__ATTR(cp0_brcm_regs, 0444, show_cp0_brcm_regs, NULL),
+	__ATTR(bmips4380_core_regs, 0444, show_bmips4380_core_regs, NULL),
+#elif defined(CONFIG_CPU_BMIPS5000)
+	__ATTR(cp0_brcm_regs, 0444, show_cp0_brcm_regs, NULL),
+#endif
+#if defined(CONFIG_BRCM_ZSCM_L2)
+	__ATTR(zscm_regs, 0444, show_zscm_regs, NULL),
+#endif
+#if defined(CONFIG_BRCM_CPU_DIV)
+	__ATTR(cpu_div, 0644, brcm_pm_show_cpu_div, brcm_pm_store_cpu_div),
+#endif
+#if defined(CONFIG_BRCM_CPU_PLL)
+	__ATTR(cpu_pll, 0644, brcm_pm_show_cpu_pll, brcm_pm_store_cpu_pll),
+#endif
+	__ATTR(sata_power, 0644, brcm_pm_show_sata_power,
+		brcm_pm_store_sata_power),
+	__ATTR(ddr_timeout, 0644, brcm_pm_show_ddr_timeout,
+		brcm_pm_store_ddr_timeout),
+	__ATTR(standby_flags, 0644, brcm_pm_show_standby_flags,
+		brcm_pm_store_standby_flags),
+	__ATTR(standby_timeout, 0644, brcm_pm_show_standby_timeout,
+		brcm_pm_store_standby_timeout),
+	__ATTR(time_at_wakeup, 0444, brcm_pm_show_time_at_wakeup, NULL),
+#if defined(CONFIG_BRCM_HAS_1GB_MEMC1)
+	__ATTR(memc1_power, 0644, brcm_pm_show_memc1_power,
+		brcm_pm_store_memc1_power),
+#endif
+//	__ATTR(halt_mode, 0644, brcm_pm_show_halt_mode,
+//		brcm_pm_store_halt_mode),
+	__ATTR_NULL,
+};
+
+static int __init brcm_pdev_init(void)
+{
+	struct device *dev;
+	int i;
+	struct device_attribute *attr;
+
+	brcmstb_pdev = platform_device_alloc("brcmstb", -1);
+	if (brcmstb_pdev == NULL) {
+		printk(KERN_WARNING "%s: can't allocate device\n",
+			__func__);
+		return -ENODEV;
+	}
+	platform_device_add(brcmstb_pdev);
+	dev = &brcmstb_pdev->dev;
+
+	for (attr = brcmstb_attr_list; attr->attr.name != NULL; attr++)
+		if (device_create_file(dev, attr) != 0)
+			WARN(1, "Can't create sysfs file\n");
+
+	/* create an attribute for each bmem region */
+	for (i = 0; ; i++) {
+		unsigned long addr, size;
+		struct device_attribute *attr;
+		char *name;
+
+		if (bmem_region_info(i, &addr, &size) < 0)
+			break;
+		attr = kzalloc(sizeof(*attr), GFP_KERNEL);
+		if (attr == NULL)
+			break;
+
+		name = kzalloc(16, GFP_KERNEL);
+		if (name == NULL)
+			break;
+		snprintf(name, 16, "bmem.%d", i);
+
+		sysfs_attr_init(&attr->attr);
+		attr->attr.name = name;
+		attr->attr.mode = 0444;
+		attr->show = show_bmem;
+
+		if (device_create_file(dev, attr) != 0)
+			WARN(1, "Can't create sysfs file\n");
+	}
+
+	return 0;
+}
+
+arch_initcall(brcm_pdev_init);
diff --git a/drivers/char/Makefile b/drivers/char/Makefile
index 0dc5d7c..06eeb7e 100644
--- a/drivers/char/Makefile
+++ b/drivers/char/Makefile
@@ -64,3 +64,5 @@ obj-$(CONFIG_JS_RTC)		+= js-rtc.o
 js-rtc-y = rtc.o
 
 obj-$(CONFIG_TILE_SROM)		+= tile-srom.o
+
+obj-$(CONFIG_BRCM_MOCA)		+= bmoca.o
diff --git a/drivers/char/bmoca.c b/drivers/char/bmoca.c
new file mode 100644
index 0000000..8190bc3
--- /dev/null
+++ b/drivers/char/bmoca.c
@@ -0,0 +1,2442 @@
+/*
+ * Copyright (C) 2010 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#define pr_fmt(fmt)		KBUILD_MODNAME ": " fmt
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/workqueue.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/pagemap.h>
+#include <linux/poll.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/version.h>
+#include <linux/scatterlist.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <linux/printk.h>
+
+#define DRV_VERSION		0x00040000
+#define DRV_BUILD_NUMBER	0x20110831
+
+#if defined(CONFIG_BRCMSTB)
+#define MOCA6816		0
+#include <linux/bmoca.h>
+#elif defined(DSL_MOCA)
+#define MOCA6816		1
+#include "bmoca.h"
+#include <boardparms.h>
+#include <bcm3450.h>
+#include <linux/netdevice.h>
+#else
+#define MOCA6816		1
+#include <linux/bmoca.h>
+#endif
+
+#if defined(CONFIG_BRCMSTB)
+#include <linux/brcmstb/brcmstb.h>
+#endif
+
+#define MOCA_ENABLE		1
+#define MOCA_DISABLE		0
+
+#define OFF_PKT_REINIT_MEM	0x00a08000
+#define PKT_REINIT_MEM_SIZE	(32 * 1024)
+#define PKT_REINIT_MEM_END	(OFF_PKT_REINIT_MEM  + PKT_REINIT_MEM_SIZE)
+
+/* The mailbox layout is different for MoCA 2.0 compared to
+   MoCA 1.1 */
+
+/* MoCA 1.1 mailbox layout */
+#define HOST_REQ_SIZE_11        304
+#define HOST_RESP_SIZE_11       256
+#define CORE_REQ_SIZE_11        400
+#define CORE_RESP_SIZE_11       64
+
+/* MoCA 1.1 offsets from the mailbox pointer */
+#define HOST_REQ_OFFSET_11      0
+#define HOST_RESP_OFFSET_11     (HOST_REQ_OFFSET_11 + HOST_REQ_SIZE_11)
+#define CORE_REQ_OFFSET_11      (HOST_RESP_OFFSET_11 + HOST_RESP_SIZE_11)
+#define CORE_RESP_OFFSET_11     (CORE_REQ_OFFSET_11 + CORE_REQ_SIZE_11)
+
+/* MoCA 2.0 mailbox layout */
+#define HOST_REQ_SIZE_20        512
+#define HOST_RESP_SIZE_20       512
+#define CORE_REQ_SIZE_20        512
+#define CORE_RESP_SIZE_20       512
+
+/* MoCA 2.0 offsets from the mailbox pointer */
+#define HOST_REQ_OFFSET_20      0
+#define HOST_RESP_OFFSET_20     (HOST_REQ_OFFSET_20 + 0)
+#define CORE_REQ_OFFSET_20      (HOST_RESP_OFFSET_20 + HOST_RESP_SIZE_20)
+#define CORE_RESP_OFFSET_20     (CORE_REQ_OFFSET_20 + 0)
+
+#define HOST_REQ_SIZE_MAX       HOST_REQ_SIZE_20
+#define CORE_REQ_SIZE_MAX       CORE_REQ_SIZE_20
+#define CORE_RESP_SIZE_MAX      CORE_RESP_SIZE_20
+
+/* local H2M, M2H buffers */
+#define NUM_CORE_MSG		32
+#define NUM_HOST_MSG		8
+
+#define FW_CHUNK_SIZE		4096
+#define MAX_BL_CHUNKS		8
+#define MAX_FW_SIZE		(1024 * 1024)
+#define MAX_FW_PAGES		((MAX_FW_SIZE >> PAGE_SHIFT) + 1)
+#define MAX_LAB_PRINTF		104
+
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+#define M2M_WRITE		(BIT(31) | BIT(27) | BIT(28))
+#define M2M_READ		(BIT(30) | BIT(27) | BIT(28))
+#else
+#define M2M_WRITE		(BIT(31) | BIT(27))
+#define M2M_READ		(BIT(30) | BIT(27))
+#endif
+
+#define M2M_TIMEOUT_MS		10
+
+#define NO_FLUSH_IRQ		0
+#define FLUSH_IRQ		1
+#define FLUSH_DMA_ONLY		2
+#define FLUSH_REQRESP_ONLY	3
+
+#define DEFAULT_PHY_CLOCK	(300 * 1000000)
+
+/* DMA buffers may not share a cache line with anything else */
+#define __DMA_ALIGN__		__attribute__((__aligned__(L1_CACHE_BYTES)))
+
+struct moca_host_msg {
+	u32			data[HOST_REQ_SIZE_MAX / 4] __DMA_ALIGN__;
+	struct list_head	chain __DMA_ALIGN__;
+	u32			len;
+};
+
+struct moca_core_msg {
+	u32			data[CORE_REQ_SIZE_MAX / 4] __DMA_ALIGN__;
+	struct list_head	chain __DMA_ALIGN__;
+	u32			len;
+};
+
+struct moca_regs {
+	unsigned int		data_mem_offset;
+	unsigned int		data_mem_size;
+	unsigned int		cntl_mem_size;
+	unsigned int		cntl_mem_offset;
+	unsigned int		gp0_offset;
+	unsigned int		gp1_offset;
+	unsigned int		ringbell_offset;
+	unsigned int		l2_status_offset;
+	unsigned int		l2_clear_offset;
+	unsigned int		l2_mask_set_offset;
+	unsigned int		l2_mask_clear_offset;
+	unsigned int		sw_reset_offset;
+	unsigned int		led_ctrl_offset;
+	unsigned int		m2m_src_offset;
+	unsigned int		m2m_dst_offset;
+	unsigned int		m2m_cmd_offset;
+	unsigned int		m2m_status_offset;
+	unsigned int		moca2host_mmp_inbox_0_offset;
+	unsigned int		moca2host_mmp_inbox_1_offset;
+	unsigned int		moca2host_mmp_inbox_2_offset;
+	unsigned int		h2m_resp_bit[2]; /* indexed by cpu */
+	unsigned int		h2m_req_bit[2]; /* indexed by cpu */
+	unsigned int		sideband_gmii_fc_offset;
+};
+
+struct moca_priv_data {
+	struct platform_device	*pdev;
+	struct device		*dev;
+
+	unsigned int		minor;
+	int			irq;
+	struct work_struct	work;
+	void __iomem		*base;
+	void __iomem		*i2c_base;
+	void __iomem		*proc_base;
+
+	unsigned int		mbx_offset[2]; /* indexed by MoCA cpu */
+	struct page		*fw_pages[MAX_FW_PAGES];
+	struct scatterlist	fw_sg[MAX_FW_PAGES];
+	struct completion	copy_complete;
+	struct completion	chunk_complete;
+
+	struct list_head	host_msg_free_list;
+	struct list_head	host_msg_pend_list;
+	struct moca_host_msg	host_msg_queue[NUM_HOST_MSG] __DMA_ALIGN__;
+	wait_queue_head_t	host_msg_wq;
+
+	struct list_head	core_msg_free_list;
+	struct list_head	core_msg_pend_list;
+	u32		core_resp_buf[CORE_RESP_SIZE_MAX / 4] __DMA_ALIGN__;
+	struct moca_core_msg	core_msg_queue[NUM_CORE_MSG] __DMA_ALIGN__;
+	struct moca_core_msg	core_msg_temp __DMA_ALIGN__;
+	wait_queue_head_t	core_msg_wq;
+
+	spinlock_t		list_lock;
+	spinlock_t		clock_lock;
+	spinlock_t		irq_status_lock;
+	struct mutex		dev_mutex;
+	struct mutex		copy_mutex;
+	struct mutex		moca_i2c_mutex;
+	int			host_mbx_busy;
+	int			host_resp_pending;
+	int			core_req_pending;
+	int			assert_pending;
+	int			wdt_pending;
+
+	int			enabled;
+	int			running;
+	int			wol_enabled;
+	struct clk		*clk;
+	struct clk		*phy_clk;
+	struct clk		*cpu_clk;
+
+	int			refcount;
+	unsigned long		start_time;
+	dma_addr_t		tpcapBufPhys;
+
+	unsigned int		bonded_mode;
+	unsigned int		phy_freq;
+
+	unsigned int		hw_rev;
+
+	const struct moca_regs	*regs;
+
+	/* MMP Parameters */
+	unsigned int		mmp_20;
+	unsigned int		host_req_size;
+	unsigned int		host_resp_size;
+	unsigned int		core_req_size;
+	unsigned int		core_resp_size;
+	unsigned int		host_req_offset;
+	unsigned int		host_resp_offset;
+	unsigned int		core_req_offset;
+	unsigned int		core_resp_offset;
+};
+
+static const struct moca_regs regs_11_plus = {
+	.data_mem_offset		= 0,
+	.data_mem_size			= (256 * 1024),
+	.cntl_mem_offset		= 0x00040000,
+	.cntl_mem_size			= (128 * 1024),
+	.gp0_offset			= 0x000a2050,
+	.gp1_offset			= 0x000a2054,
+	.ringbell_offset		= 0x000a2060,
+	.l2_status_offset		= 0x000a2080,
+	.l2_clear_offset		= 0x000a2088,
+	.l2_mask_set_offset		= 0x000a2090,
+	.l2_mask_clear_offset		= 0x000a2094,
+	.sw_reset_offset		= 0x000a2040,
+	.led_ctrl_offset		= 0x000a204c,
+	.led_ctrl_offset		= 0x000a204c,
+	.m2m_src_offset			= 0x000a2000,
+	.m2m_dst_offset			= 0x000a2004,
+	.m2m_cmd_offset			= 0x000a2008,
+	.m2m_status_offset		= 0x000a200c,
+	.h2m_resp_bit[1]		= 0x1,
+	.h2m_req_bit[1]			= 0x2,
+	.sideband_gmii_fc_offset	= 0x000a1420
+};
+
+static const struct moca_regs regs_11_lite = {
+	.data_mem_offset		= 0,
+	.data_mem_size			= (96 * 1024),
+	.cntl_mem_offset		= 0x0004c000,
+	.cntl_mem_size			= (80 * 1024),
+	.gp0_offset			= 0x000a2050,
+	.gp1_offset			= 0x000a2054,
+	.ringbell_offset		= 0x000a2060,
+	.l2_status_offset		= 0x000a2080,
+	.l2_clear_offset		= 0x000a2088,
+	.l2_mask_set_offset		= 0x000a2090,
+	.l2_mask_clear_offset		= 0x000a2094,
+	.sw_reset_offset		= 0x000a2040,
+	.led_ctrl_offset		= 0x000a204c,
+	.led_ctrl_offset		= 0x000a204c,
+	.m2m_src_offset			= 0x000a2000,
+	.m2m_dst_offset			= 0x000a2004,
+	.m2m_cmd_offset			= 0x000a2008,
+	.m2m_status_offset		= 0x000a200c,
+	.h2m_resp_bit[1]		= 0x1,
+	.h2m_req_bit[1]			= 0x2,
+	.sideband_gmii_fc_offset	= 0x000a1420
+};
+
+static const struct moca_regs regs_11 = {
+	.data_mem_offset		= 0,
+	.data_mem_size			= (256 * 1024),
+	.cntl_mem_offset		= 0x0004c000,
+	.cntl_mem_size			= (80 * 1024),
+	.gp0_offset			= 0x000a2050,
+	.gp1_offset			= 0x000a2054,
+	.ringbell_offset		= 0x000a2060,
+	.l2_status_offset		= 0x000a2080,
+	.l2_clear_offset		= 0x000a2088,
+	.l2_mask_set_offset		= 0x000a2090,
+	.l2_mask_clear_offset		= 0x000a2094,
+	.sw_reset_offset		= 0x000a2040,
+	.led_ctrl_offset		= 0x000a204c,
+	.m2m_src_offset			= 0x000a2000,
+	.m2m_dst_offset			= 0x000a2004,
+	.m2m_cmd_offset			= 0x000a2008,
+	.m2m_status_offset		= 0x000a200c,
+	.h2m_resp_bit[1]		= 0x1,
+	.h2m_req_bit[1]			= 0x2,
+	.sideband_gmii_fc_offset	= 0x000a1420
+};
+
+static const struct moca_regs regs_20 = {
+	.data_mem_offset		= 0,
+	.data_mem_size			= (288 * 1024),
+	.cntl_mem_offset		= 0x00120000,
+	.cntl_mem_size			= (384 * 1024),
+	.gp0_offset			= 0,
+	.gp1_offset			= 0,
+	.ringbell_offset		= 0x001ffd0c,
+	.l2_status_offset		= 0x001ffc40,
+	.l2_clear_offset		= 0x001ffc48,
+	.l2_mask_set_offset		= 0x001ffc50,
+	.l2_mask_clear_offset		= 0x001ffc54,
+	.sw_reset_offset		= 0x001ffd00,
+	.led_ctrl_offset		= 0,
+	.m2m_src_offset			= 0x001ffc00,
+	.m2m_dst_offset			= 0x001ffc04,
+	.m2m_cmd_offset			= 0x001ffc08,
+	.m2m_status_offset		= 0x001ffc0c,
+	.moca2host_mmp_inbox_0_offset	= 0x001ffd58,
+	.moca2host_mmp_inbox_1_offset	= 0x001ffd5c,
+	.moca2host_mmp_inbox_2_offset	= 0x001ffd60,
+	.h2m_resp_bit[1]		= 0x10,
+	.h2m_req_bit[1]			= 0x20,
+	.h2m_resp_bit[0]		= 0x1,
+	.h2m_req_bit[0]			= 0x2,
+	.sideband_gmii_fc_offset	= 0x001fec18
+};
+
+#define MOCA_FW_MAGIC		0x4d6f4341
+
+struct moca_fw_hdr {
+	uint32_t		jump[2];
+	uint32_t		length;
+	uint32_t		cpuid;
+	uint32_t		magic;
+	uint32_t		hw_rev;
+	uint32_t		bl_chunks;
+	uint32_t		res1;
+};
+
+struct bsc_regs {
+	u32			chip_address;
+	u32			data_in[8];
+	u32			cnt_reg;
+	u32			ctl_reg;
+	u32			iic_enable;
+	u32			data_out[8];
+	u32			ctlhi_reg;
+	u32			scl_param;
+};
+
+/* support for multiple MoCA devices */
+#define NUM_MINORS		8
+static struct moca_priv_data *minor_tbl[NUM_MINORS];
+static struct class *moca_class;
+
+/* character major device number */
+#define MOCA_MAJOR		234
+#define MOCA_CLASS		"bmoca"
+
+#define M2H_RESP		BIT(0)
+#define M2H_REQ			BIT(1)
+#define M2H_ASSERT		BIT(2)
+#define M2H_NEXTCHUNK		BIT(3)
+#define M2H_NEXTCHUNK_CPU0	BIT(4)
+#define M2H_WDT_CPU0		BIT(6)
+#define M2H_WDT_CPU1		BIT(10)
+#define M2H_DMA			BIT(11)
+
+#define M2H_RESP_CPU0		BIT(13)
+#define M2H_REQ_CPU0		BIT(14)
+#define M2H_ASSERT_CPU0		BIT(15)
+
+/* does this word contain a NIL byte (i.e. end of string)? */
+#define HAS0(x)			((((x) & 0xff) == 0) || \
+				 (((x) & 0xff00) == 0) || \
+				 (((x) & 0xff0000) == 0) || \
+				 (((x) & 0xff000000) == 0))
+
+#define MOCA_SET(x, y)		do { \
+	MOCA_WR(x, MOCA_RD(x) | (y)); \
+} while (0)
+#define MOCA_UNSET(x, y)	do { \
+	MOCA_WR(x, MOCA_RD(x) & ~(y)); \
+} while (0)
+
+static void moca_3450_write_i2c(struct moca_priv_data *priv, u8 addr, u32 data);
+static u32 moca_3450_read_i2c(struct moca_priv_data *priv, u8 addr);
+static int moca_get_mbx_offset(struct moca_priv_data *priv);
+
+#define INRANGE(x, a, b)	(((x) >= (a)) && ((x) < (b)))
+
+static inline int moca_range_ok(struct moca_priv_data *priv,
+	unsigned long offset, unsigned long len)
+{
+	const struct moca_regs *r = priv->regs;
+	unsigned long lastad = offset + len - 1;
+
+	if (lastad < offset)
+		return -EINVAL;
+
+	if (INRANGE(offset, r->cntl_mem_offset,
+		    r->cntl_mem_offset + r->cntl_mem_size) &&
+	    INRANGE(lastad, r->cntl_mem_offset,
+		    r->cntl_mem_offset + r->cntl_mem_size))
+		return 0;
+
+	if (INRANGE(offset, r->data_mem_offset,
+		    r->data_mem_offset + r->data_mem_size) &&
+	    INRANGE(lastad, r->data_mem_offset,
+		    r->data_mem_offset + r->data_mem_size))
+		return 0;
+
+	if (INRANGE(offset, OFF_PKT_REINIT_MEM, PKT_REINIT_MEM_END) &&
+	    INRANGE(lastad, OFF_PKT_REINIT_MEM, PKT_REINIT_MEM_END))
+		return 0;
+
+	return -EINVAL;
+}
+
+static void moca_mmp_init(struct moca_priv_data *priv, int is20)
+{
+	if (is20) {
+		priv->host_req_size    = HOST_REQ_SIZE_20;
+		priv->host_resp_size   = HOST_RESP_SIZE_20;
+		priv->core_req_size    = CORE_REQ_SIZE_20;
+		priv->core_resp_size   = CORE_RESP_SIZE_20;
+		priv->host_req_offset  = HOST_REQ_OFFSET_20;
+		priv->host_resp_offset = HOST_RESP_OFFSET_20;
+		priv->core_req_offset  = CORE_REQ_OFFSET_20;
+		priv->core_resp_offset = CORE_RESP_OFFSET_20;
+		priv->mmp_20 = 1;
+	} else {
+		priv->host_req_size    = HOST_REQ_SIZE_11;
+		priv->host_resp_size   = HOST_RESP_SIZE_11;
+		priv->core_req_size    = CORE_REQ_SIZE_11;
+		priv->core_resp_size   = CORE_RESP_SIZE_11;
+		priv->host_req_offset  = HOST_REQ_OFFSET_11;
+		priv->host_resp_offset = HOST_RESP_OFFSET_11;
+		priv->core_req_offset  = CORE_REQ_OFFSET_11;
+		priv->core_resp_offset = CORE_RESP_OFFSET_11;
+		priv->mmp_20 = 0;
+	}
+}
+
+static int moca_is_20(struct moca_priv_data *priv)
+{
+	return (priv->hw_rev & MOCA_PROTVER_MASK) == MOCA_PROTVER_20;
+}
+
+#ifdef CONFIG_BRCM_MOCA_BUILTIN_FW
+#error Not supported in this version
+#else
+static const char *bmoca_fw_image;
+#endif
+
+/*
+ * LOW-LEVEL DEVICE OPERATIONS
+ */
+
+#define MOCA_RD(x)		__raw_readl((void __iomem *)(x))
+#define MOCA_WR(x, y)		__raw_writel((y), (void __iomem *)(x))
+
+#define I2C_RD(x)		MOCA_RD(x)
+#define I2C_WR(x, y)		MOCA_WR(x, y)
+
+static void moca_hw_reset(struct moca_priv_data *priv)
+{
+	const struct moca_regs *r = priv->regs;
+
+	/* disable and clear all interrupts */
+	MOCA_WR(priv->base + r->l2_mask_set_offset, 0xffffffff);
+	MOCA_RD(priv->base + r->l2_mask_set_offset);
+
+	/* assert resets */
+
+	/* reset CPU first, both CPUs for MoCA 20 HW */
+	if (moca_is_20(priv))
+		MOCA_SET(priv->base + r->sw_reset_offset, 5);
+	else
+		MOCA_SET(priv->base + r->sw_reset_offset, 1);
+
+	MOCA_RD(priv->base + r->sw_reset_offset);
+
+	udelay(20);
+
+	/* reset everything else except clocks */
+	MOCA_SET(priv->base + r->sw_reset_offset, ~(BIT(3) | BIT(7)));
+	MOCA_RD(priv->base + r->sw_reset_offset);
+
+	udelay(20);
+
+	/* disable clocks */
+	MOCA_SET(priv->base + r->sw_reset_offset, ~BIT(3));
+	MOCA_RD(priv->base + r->sw_reset_offset);
+
+	MOCA_WR(priv->base + r->l2_clear_offset, 0xffffffff);
+	MOCA_RD(priv->base + r->l2_clear_offset);
+}
+
+/* called any time we start/restart/stop MoCA */
+static void moca_hw_init(struct moca_priv_data *priv, int action)
+{
+	const struct moca_regs *r = priv->regs;
+
+	if (action == MOCA_ENABLE && !priv->enabled) {
+		clk_enable(priv->clk);
+		clk_enable(priv->phy_clk);
+		clk_enable(priv->cpu_clk);
+		priv->enabled = 1;
+	}
+
+	/* clock not enabled, register accesses will fail with bus error */
+	if (!priv->enabled)
+		return;
+
+	moca_hw_reset(priv);
+	udelay(1);
+
+	if (action == MOCA_ENABLE) {
+		/* deassert moca_sys_reset and clock */
+		MOCA_UNSET(priv->base + r->sw_reset_offset, BIT(1) | BIT(7));
+
+		if (priv->hw_rev >= HWREV_MOCA_20_GEN22) {
+			/* Take PHY0 out of reset and enable clock */
+			MOCA_UNSET(priv->base + r->sw_reset_offset,
+				   BIT(4) | BIT(8));
+
+			if (priv->bonded_mode) {
+				/* Take PHY1 out of reset and enable clock */
+				MOCA_UNSET(priv->base + r->sw_reset_offset,
+					   BIT(5) | BIT(9));
+			}
+		}
+		MOCA_RD(priv->base + r->sw_reset_offset);
+	}
+
+	if (!moca_is_20(priv)) {
+		/* clear junk out of GP0/GP1 */
+		MOCA_WR(priv->base + r->gp0_offset, 0xffffffff);
+		MOCA_WR(priv->base + r->gp1_offset, 0x0);
+		/* set up activity LED for 50% duty cycle */
+		MOCA_WR(priv->base + r->led_ctrl_offset, 0x40004000);
+	}
+
+	/* enable DMA completion interrupts */
+	MOCA_WR(priv->base + r->ringbell_offset, 0);
+	MOCA_WR(priv->base + r->l2_mask_clear_offset, M2H_DMA);
+	MOCA_RD(priv->base + r->l2_mask_clear_offset);
+
+	if (action == MOCA_DISABLE && priv->enabled) {
+		priv->enabled = 0;
+		clk_disable(priv->cpu_clk);
+		clk_disable(priv->phy_clk);
+		clk_disable(priv->clk);
+	}
+}
+
+static void moca_ringbell(struct moca_priv_data *priv, u32 mask)
+{
+	const struct moca_regs *r = priv->regs;
+
+	MOCA_WR(priv->base + r->ringbell_offset, mask);
+	MOCA_RD(priv->base + r->ringbell_offset);
+}
+
+static u32 moca_irq_status(struct moca_priv_data *priv, int flush)
+{
+	const struct moca_regs *r = priv->regs;
+	u32 stat, dma_mask = M2H_DMA | M2H_NEXTCHUNK;
+	unsigned long flags;
+
+	if (moca_is_20(priv))
+		dma_mask |= M2H_NEXTCHUNK_CPU0;
+
+	spin_lock_irqsave(&priv->irq_status_lock, flags);
+
+	stat = MOCA_RD(priv->base + priv->regs->l2_status_offset);
+
+	if (flush == FLUSH_IRQ) {
+		MOCA_WR(priv->base + r->l2_clear_offset, stat);
+		MOCA_RD(priv->base + r->l2_clear_offset);
+	}
+	if (flush == FLUSH_DMA_ONLY) {
+		MOCA_WR(priv->base + r->l2_clear_offset,
+			stat & dma_mask);
+		MOCA_RD(priv->base + r->l2_clear_offset);
+	}
+	if (flush == FLUSH_REQRESP_ONLY) {
+		MOCA_WR(priv->base + r->l2_clear_offset,
+			stat & (M2H_RESP | M2H_REQ |
+			M2H_RESP_CPU0 | M2H_REQ_CPU0));
+		MOCA_RD(priv->base + r->l2_clear_offset);
+	}
+
+	spin_unlock_irqrestore(&priv->irq_status_lock, flags);
+
+	return stat;
+}
+
+static void moca_enable_irq(struct moca_priv_data *priv)
+{
+	const struct moca_regs *r = priv->regs;
+
+	/* unmask everything */
+	u32 mask = M2H_REQ | M2H_RESP | M2H_ASSERT | M2H_WDT_CPU1 |
+		M2H_NEXTCHUNK | M2H_DMA;
+
+	if (moca_is_20(priv))
+		mask |= M2H_WDT_CPU0 | M2H_NEXTCHUNK_CPU0 |
+			M2H_REQ_CPU0 | M2H_RESP_CPU0 | M2H_ASSERT_CPU0;
+
+	MOCA_WR(priv->base + r->l2_mask_clear_offset, mask);
+	MOCA_RD(priv->base + r->l2_mask_clear_offset);
+}
+
+static void moca_disable_irq(struct moca_priv_data *priv)
+{
+	const struct moca_regs *r = priv->regs;
+
+	/* mask everything except DMA completions */
+	u32 mask = M2H_REQ | M2H_RESP | M2H_ASSERT | M2H_WDT_CPU1 |
+		M2H_NEXTCHUNK;
+
+	if (moca_is_20(priv))
+		mask |= M2H_WDT_CPU0 | M2H_NEXTCHUNK_CPU0 |
+			M2H_REQ_CPU0 | M2H_RESP_CPU0 | M2H_ASSERT_CPU0;
+
+	MOCA_WR(priv->base + r->l2_mask_set_offset, mask);
+	MOCA_RD(priv->base + r->l2_mask_set_offset);
+}
+
+static u32 moca_start_mips(struct moca_priv_data *priv, u32 cpu)
+{
+	const struct moca_regs *r = priv->regs;
+
+	if (moca_is_20(priv)) {
+		if (cpu == 1)
+			MOCA_UNSET(priv->base + r->sw_reset_offset, BIT(0));
+		else {
+			moca_mmp_init(priv, 1);
+			MOCA_UNSET(priv->base + r->sw_reset_offset, BIT(2));
+		}
+	} else
+		MOCA_UNSET(priv->base + r->sw_reset_offset, BIT(0));
+	MOCA_RD(priv->base + r->sw_reset_offset);
+	return 0;
+}
+
+static void moca_m2m_xfer(struct moca_priv_data *priv,
+	u32 dst, u32 src, u32 ctl)
+{
+	const struct moca_regs *r = priv->regs;
+	u32 status;
+
+	MOCA_WR(priv->base + r->m2m_src_offset, src);
+	MOCA_WR(priv->base + r->m2m_dst_offset, dst);
+	MOCA_WR(priv->base + r->m2m_status_offset, 0);
+	MOCA_RD(priv->base + r->m2m_status_offset);
+	MOCA_WR(priv->base + r->m2m_cmd_offset, ctl);
+
+	if (wait_for_completion_timeout(&priv->copy_complete,
+		1000 * M2M_TIMEOUT_MS) <= 0) {
+		dev_warn(priv->dev, "DMA interrupt timed out, status %x\n",
+			 moca_irq_status(priv, NO_FLUSH_IRQ));
+	}
+
+	status = MOCA_RD(priv->base + r->m2m_status_offset);
+
+	if (status & (3 << 29))
+		dev_warn(priv->dev, "bad status %08x (s/d/c %08x %08x %08x)\n",
+			 status, src, dst, ctl);
+}
+
+static void moca_write_mem(struct moca_priv_data *priv,
+	u32 dst_offset, void *src, unsigned int len)
+{
+	dma_addr_t pa;
+
+	if (moca_range_ok(priv, dst_offset, len) < 0) {
+		dev_warn(priv->dev, "copy past end of cntl memory: %08x\n",
+			 dst_offset);
+		return;
+	}
+
+	pa = dma_map_single(&priv->pdev->dev, src, len, DMA_TO_DEVICE);
+	moca_m2m_xfer(priv, dst_offset + priv->regs->data_mem_offset, (u32)pa,
+		len | M2M_WRITE);
+	dma_unmap_single(&priv->pdev->dev, pa, len, DMA_TO_DEVICE);
+}
+
+static void moca_read_mem(struct moca_priv_data *priv,
+	void *dst, u32 src_offset, unsigned int len)
+{
+	int i;
+
+	if (moca_range_ok(priv, src_offset, len) < 0) {
+		dev_warn(priv->dev, "copy past end of cntl memory: %08x\n",
+			 src_offset);
+		return;
+	}
+
+	for (i = 0; i < len; i += 4)
+		DEV_WR(dst + i, cpu_to_be32(
+			MOCA_RD(priv->base + src_offset +
+				priv->regs->data_mem_offset + i)));
+}
+
+static void moca_write_sg(struct moca_priv_data *priv,
+	u32 dst_offset, struct scatterlist *sg, int nents)
+{
+	int j;
+	uintptr_t addr = priv->regs->data_mem_offset + dst_offset;
+
+	dma_map_sg(&priv->pdev->dev, sg, nents, DMA_TO_DEVICE);
+
+	for (j = 0; j < nents; j++) {
+		moca_m2m_xfer(priv, addr, (u32)sg[j].dma_address,
+			sg[j].length | M2M_WRITE);
+
+		addr += sg[j].length;
+	}
+
+	dma_unmap_sg(&priv->pdev->dev, sg, nents, DMA_TO_DEVICE);
+}
+
+static inline void moca_read_sg(struct moca_priv_data *priv,
+	u32 src_offset, struct scatterlist *sg, int nents)
+{
+	int j;
+	uintptr_t addr = priv->regs->data_mem_offset + src_offset;
+
+	dma_map_sg(&priv->pdev->dev, sg, nents, DMA_FROM_DEVICE);
+
+	for (j = 0; j < nents; j++) {
+		moca_m2m_xfer(priv, (u32)sg[j].dma_address, addr,
+			sg[j].length | M2M_READ);
+
+		addr += sg[j].length;
+		SetPageDirty(sg_page(&sg[j]));
+	}
+
+	dma_unmap_sg(&priv->pdev->dev, sg, nents, DMA_FROM_DEVICE);
+}
+
+#define moca_3450_write moca_3450_write_i2c
+#define moca_3450_read moca_3450_read_i2c
+
+static void moca_put_pages(struct moca_priv_data *priv, int pages)
+{
+	int i;
+
+	for (i = 0; i < pages; i++)
+		page_cache_release(priv->fw_pages[i]);
+}
+
+static int moca_get_pages(struct moca_priv_data *priv, unsigned long addr,
+	int size, unsigned int moca_addr, int write)
+{
+	unsigned int pages, chunk_size;
+	int ret, i;
+
+	if (addr & 3)
+		return -EINVAL;
+	if ((size <= 0) || (size > MAX_FW_SIZE))
+		return -EINVAL;
+
+	pages = ((addr & ~PAGE_MASK) + size + PAGE_SIZE - 1) >> PAGE_SHIFT;
+
+	down_read(&current->mm->mmap_sem);
+	ret = get_user_pages(current, current->mm, addr & PAGE_MASK, pages,
+		write, 0, priv->fw_pages, NULL);
+	up_read(&current->mm->mmap_sem);
+
+	if (ret < 0)
+		return ret;
+	BUG_ON((ret > MAX_FW_PAGES) || (pages == 0));
+
+	if (ret < pages) {
+		dev_warn(priv->dev, "get_user_pages returned %d, expecting %d\n",
+			 ret, pages);
+		moca_put_pages(priv, ret);
+		return -EFAULT;
+	}
+
+	chunk_size = PAGE_SIZE - (addr & ~PAGE_MASK);
+	if (size < chunk_size)
+		chunk_size = size;
+
+	sg_set_page(&priv->fw_sg[0], priv->fw_pages[0], chunk_size,
+		addr & ~PAGE_MASK);
+	size -= chunk_size;
+
+	for (i = 1; i < pages; i++) {
+		sg_set_page(&priv->fw_sg[i], priv->fw_pages[i],
+			size > PAGE_SIZE ? PAGE_SIZE : size, 0);
+		size -= PAGE_SIZE;
+	}
+	return ret;
+}
+
+static int moca_write_img(struct moca_priv_data *priv, struct moca_xfer *x)
+{
+	int pages, i, ret = -EINVAL;
+	struct moca_fw_hdr hdr;
+	u32 bl_chunks;
+
+	if (copy_from_user(&hdr, (void __user *)(unsigned long)x->buf,
+			sizeof(hdr)))
+		return -EFAULT;
+
+	bl_chunks = be32_to_cpu(hdr.bl_chunks);
+	if (!bl_chunks || (bl_chunks > MAX_BL_CHUNKS))
+		bl_chunks = 1;
+
+	pages = moca_get_pages(priv, (unsigned long)x->buf, x->len, 0, 0);
+	if (pages < 0)
+		return pages;
+	if (pages < (bl_chunks + 2))
+		goto out;
+
+	/* host must use FW_CHUNK_SIZE MMU pages (for now) */
+	BUG_ON(FW_CHUNK_SIZE != PAGE_SIZE);
+
+	/* write the first two chunks, then start the MIPS */
+	moca_write_sg(priv, 0, &priv->fw_sg[0], bl_chunks + 1);
+	moca_enable_irq(priv);
+	moca_start_mips(priv, be32_to_cpu(hdr.cpuid));
+	ret = 0;
+
+	/* wait for an ACK, then write each successive chunk */
+	for (i = bl_chunks + 1; i < pages; i++) {
+		if (wait_for_completion_timeout(&priv->chunk_complete,
+				1000 * M2M_TIMEOUT_MS) <= 0) {
+			moca_disable_irq(priv);
+			dev_warn(priv->dev, "chunk ack timed out\n");
+			ret = -EIO;
+			break;
+		}
+		moca_write_sg(priv,
+			priv->regs->data_mem_offset + FW_CHUNK_SIZE * bl_chunks,
+			&priv->fw_sg[i], 1);
+	}
+
+  /* wait for ACK of last block.  Older firmware images didn't
+     ACK the last block, so don't return an error */
+	wait_for_completion_timeout(&priv->chunk_complete,
+			1000 * M2M_TIMEOUT_MS / 10);
+
+out:
+	moca_put_pages(priv, pages);
+	return ret;
+}
+
+/*
+ * MESSAGE AND LIST HANDLING
+ */
+
+static void moca_handle_lab_printf(struct moca_priv_data *priv,
+	struct moca_core_msg *m)
+{
+	u32 str_len;
+	u32 str_addr;
+
+	if (priv->mmp_20) {
+		str_len = (be32_to_cpu(m->data[4]) + 3) & ~3;
+		str_addr = be32_to_cpu(m->data[3]) & 0x1fffffff;
+
+		if ((be32_to_cpu(m->data[0]) == 0x3) &&
+		    (be32_to_cpu(m->data[1]) == 12) &&
+		    ((be32_to_cpu(m->data[2]) & 0xffffff) == 0x090801) &&
+		    (be32_to_cpu(m->data[4]) <= MAX_LAB_PRINTF)) {
+			m->len = 3 + str_len;
+			moca_read_mem(priv, &m->data[3], str_addr, str_len);
+
+			m->data[1] = cpu_to_be32(m->len - 8);
+		}
+	} else {
+		str_len = (be32_to_cpu(m->data[3]) + 3) & ~3;
+		str_addr = be32_to_cpu(m->data[2]) & 0x1fffffff;
+
+		if ((be32_to_cpu(m->data[0]) & 0xff0000ff) == 0x09000001 &&
+			be32_to_cpu(m->data[1]) == 0x600b0008 &&
+			(be32_to_cpu(m->data[3]) <= MAX_LAB_PRINTF)) {
+
+			m->len = 8 + str_len;
+			moca_read_mem(priv, &m->data[2], str_addr, str_len);
+
+			m->data[1] = cpu_to_be32((MOCA_IE_DRV_PRINTF << 16) +
+				m->len - 8);
+		}
+	}
+}
+static void moca_msg_reset(struct moca_priv_data *priv)
+{
+	int i;
+
+	if (priv->running)
+		moca_disable_irq(priv);
+	priv->running = 0;
+	priv->host_mbx_busy = 0;
+	priv->host_resp_pending = 0;
+	priv->core_req_pending = 0;
+	priv->assert_pending = 0;
+	priv->mbx_offset[0] = -1;
+	priv->mbx_offset[1] = -1;
+
+	spin_lock_bh(&priv->list_lock);
+	INIT_LIST_HEAD(&priv->core_msg_free_list);
+	INIT_LIST_HEAD(&priv->core_msg_pend_list);
+
+	for (i = 0; i < NUM_CORE_MSG; i++)
+		list_add_tail(&priv->core_msg_queue[i].chain,
+			&priv->core_msg_free_list);
+
+	INIT_LIST_HEAD(&priv->host_msg_free_list);
+	INIT_LIST_HEAD(&priv->host_msg_pend_list);
+
+	for (i = 0; i < NUM_HOST_MSG; i++)
+		list_add_tail(&priv->host_msg_queue[i].chain,
+			&priv->host_msg_free_list);
+	spin_unlock_bh(&priv->list_lock);
+}
+
+static struct list_head *moca_detach_head(struct moca_priv_data *priv,
+	struct list_head *h)
+{
+	struct list_head *r = NULL;
+
+	spin_lock_bh(&priv->list_lock);
+	if (!list_empty(h)) {
+		r = h->next;
+		list_del(r);
+	}
+	spin_unlock_bh(&priv->list_lock);
+
+	return r;
+}
+
+static void moca_attach_tail(struct moca_priv_data *priv,
+	struct list_head *elem, struct list_head *list)
+{
+	spin_lock_bh(&priv->list_lock);
+	list_add_tail(elem, list);
+	spin_unlock_bh(&priv->list_lock);
+}
+
+/* Must have dev_mutex when calling this function */
+static int moca_recvmsg(struct moca_priv_data *priv, uintptr_t offset,
+	u32 max_size, uintptr_t reply_offset, u32 cpuid)
+{
+	struct list_head *ml = NULL;
+	struct moca_core_msg *m;
+	unsigned int w, rw, num_ies;
+	u32 data, size;
+	char *msg;
+	int err = -ENOMEM;
+	u32 *reply = priv->core_resp_buf;
+	int attach = 1;
+
+	m = &priv->core_msg_temp;
+
+	BUG_ON((uintptr_t)m->data & (L1_CACHE_BYTES - 1));
+
+	/* make sure we have the mailbox offset before using it */
+	moca_get_mbx_offset(priv);
+
+	/* read only as much as is necessary.
+	   The second word is the length for mmp_20 */
+	if (priv->mmp_20) {
+		moca_read_mem(priv, m->data,
+			offset + priv->mbx_offset[cpuid], 8);
+
+		size = (be32_to_cpu(m->data[1])+3) & 0xFFFFFFFC;
+		/* if size is too large, this is a protocol error.
+		   mocad will output the error message */
+		if (size > max_size - 8)
+			size = max_size - 8;
+
+		moca_read_mem(priv, &m->data[2],
+			offset + priv->mbx_offset[cpuid] + 8, size);
+	} else
+		moca_read_mem(priv, m->data,
+			offset + priv->mbx_offset[cpuid], max_size);
+
+	data = be32_to_cpu(m->data[0]);
+
+	if (priv->mmp_20) {
+		/* In MoCA 2.0, there is only 1 IE per message */
+		num_ies = 1;
+	} else {
+		num_ies = data & 0xffff;
+	}
+
+	if (reply_offset) {
+		if (priv->mmp_20) {
+			/* In MoCA 2.0, the ACK is to simply set the
+			   MSB in the incoming message and send it
+			   back */
+			reply[0] = cpu_to_be32(data | 0x80000000);
+			rw = 1;
+		} else {
+			/* ACK + seq number + number of IEs */
+			reply[0] = cpu_to_be32((data & 0x00ff0000) |
+				0x04000000 | num_ies);
+			rw = 1;
+		}
+	}
+
+	err = -EINVAL;
+	w = 1;
+	max_size >>= 2;
+	while (num_ies) {
+		if (w >= max_size) {
+			msg = "dropping long message";
+			goto bad;
+		}
+
+		data = be32_to_cpu(m->data[w++]);
+
+		if (reply_offset && !priv->mmp_20) {
+			/*
+			 * ACK each IE in the original message;
+			 * return code is always 0
+			 */
+			if ((rw << 2) >= priv->core_resp_size)
+				dev_warn(priv->dev, "Core ack buffer overflowed\n");
+			else {
+				reply[rw] = cpu_to_be32((data & ~0xffff) | 4);
+				rw++;
+				reply[rw] = cpu_to_be32(0);
+				rw++;
+			}
+		}
+		if (data & 3) {
+			msg = "IE is not a multiple of 4 bytes";
+			goto bad;
+		}
+
+		w += ((data & 0xffff) >> 2);
+
+		if (w > max_size) {
+			msg = "dropping long message";
+			goto bad;
+		}
+		num_ies--;
+	}
+	m->len = w << 2;
+
+	/* special case for lab_printf traps */
+	moca_handle_lab_printf(priv, m);
+
+	/*
+	 * Check to see if we can add this new message to the current queue.
+	 * The result will be a single message with multiple IEs.
+	 */
+	if (!priv->mmp_20) {
+		spin_lock_bh(&priv->list_lock);
+		if (!list_empty(&priv->core_msg_pend_list)) {
+			ml = priv->core_msg_pend_list.prev;
+			m = list_entry(ml, struct moca_core_msg, chain);
+
+			if (m->len + priv->core_msg_temp.len > max_size)
+				ml = NULL;
+			else {
+				u32 d0 = be32_to_cpu(
+						priv->core_msg_temp.data[0]);
+
+				/* Only concatenate traps from the core */
+				if (((be32_to_cpu(m->data[0]) & 0xff000000) !=
+					0x09000000) ||
+					((d0 & 0xff000000) != 0x09000000))
+					ml = NULL;
+				else {
+					/*
+					 * We can add the message to the
+					 * previous one. Update the num of IEs,
+					 * update the length and copy the data.
+					 */
+					data = be32_to_cpu(m->data[0]);
+					num_ies = data & 0xffff;
+					num_ies += d0 & 0xffff;
+					data &= 0xffff0000;
+					data |= num_ies;
+					m->data[0] = cpu_to_be32(data);
+
+					/*
+					 * Subtract 4 bytes from length for
+					   message header
+					 */
+					memcpy(&m->data[m->len >> 2],
+						&priv->core_msg_temp.data[1],
+						priv->core_msg_temp.len - 4);
+					m->len += priv->core_msg_temp.len - 4;
+					attach = 0;
+				}
+			}
+		}
+		spin_unlock_bh(&priv->list_lock);
+	}
+
+	if (ml == NULL) {
+		ml = moca_detach_head(priv, &priv->core_msg_free_list);
+		if (ml == NULL) {
+			msg = "no entries left on core_msg_free_list";
+			err = -ENOMEM;
+			goto bad;
+		}
+		m = list_entry(ml, struct moca_core_msg, chain);
+
+		memcpy(m->data, priv->core_msg_temp.data,
+			priv->core_msg_temp.len);
+		m->len = priv->core_msg_temp.len;
+	}
+
+	if (reply_offset) {
+		if ((cpuid == 1) &&
+			(moca_irq_status(priv, NO_FLUSH_IRQ) & M2H_ASSERT)) {
+			/* do not retry - message is gone forever */
+			err = 0;
+			msg = "core_req overwritten by assertion";
+			goto bad;
+		}
+		if ((cpuid == 0) &&
+			(moca_irq_status(priv, NO_FLUSH_IRQ)
+			& M2H_ASSERT_CPU0)) {
+			/* do not retry - message is gone forever */
+			err = 0;
+			msg = "core_req overwritten by assertion";
+			goto bad;
+		}
+		moca_write_mem(priv, reply_offset + priv->mbx_offset[cpuid],
+			reply, rw << 2);
+		moca_ringbell(priv, priv->regs->h2m_resp_bit[cpuid]);
+	}
+
+	if (attach) {
+		moca_attach_tail(priv, ml, &priv->core_msg_pend_list);
+		wake_up(&priv->core_msg_wq);
+	}
+
+	return 0;
+
+bad:
+	dev_warn(priv->dev, "%s\n", msg);
+
+	if (ml)
+		moca_attach_tail(priv, ml, &priv->core_msg_free_list);
+
+	return err;
+}
+
+static int moca_h2m_sanity_check(struct moca_priv_data *priv,
+	struct moca_host_msg *m)
+{
+	unsigned int w, num_ies;
+	u32 data;
+
+	if (priv->mmp_20) {
+		/* The length is stored in data[1]
+		   plus 8 extra header bytes */
+		data = be32_to_cpu(m->data[1]) + 8;
+		if (data > priv->host_req_size)
+			return -1;
+		else
+			return (int) data;
+	} else {
+		data = be32_to_cpu(m->data[0]);
+		num_ies = data & 0xffff;
+
+		w = 1;
+		while (num_ies) {
+			if (w >= (m->len << 2))
+				return -1;
+
+			data = be32_to_cpu(m->data[w++]);
+
+			if (data & 3)
+				return -1;
+			w += (data & 0xffff) >> 2;
+			num_ies--;
+		}
+		return w << 2;
+	}
+}
+
+/* Must have dev_mutex when calling this function */
+static int moca_sendmsg(struct moca_priv_data *priv, u32 cpuid)
+{
+	struct list_head *ml = NULL;
+	struct moca_host_msg *m;
+
+	if (priv->host_mbx_busy == 1)
+		return -1;
+
+	ml = moca_detach_head(priv, &priv->host_msg_pend_list);
+	if (ml == NULL)
+		return -EAGAIN;
+	m = list_entry(ml, struct moca_host_msg, chain);
+
+	moca_write_mem(priv, priv->mbx_offset[cpuid] + priv->host_req_offset,
+		m->data, m->len);
+
+	moca_ringbell(priv, priv->regs->h2m_req_bit[cpuid]);
+	moca_attach_tail(priv, ml, &priv->host_msg_free_list);
+	wake_up(&priv->host_msg_wq);
+
+	return 0;
+}
+
+/* Must have dev_mutex when calling this function */
+static int moca_wdt(struct moca_priv_data *priv, u32 cpu)
+{
+	struct list_head *ml = NULL;
+	struct moca_core_msg *m;
+
+	ml = moca_detach_head(priv, &priv->core_msg_free_list);
+	if (ml == NULL) {
+		dev_warn(priv->dev, "no entries left on core_msg_free_list\n");
+		return -ENOMEM;
+	}
+
+	if (priv->mmp_20) {
+		/*
+		 * generate phony wdt message to pass to the user
+		 * type = 0x03 (trap)
+		 * IE type = 0x11003 (wdt), 4 bytes length
+		 */
+		m = list_entry(ml, struct moca_core_msg, chain);
+		m->data[0] = cpu_to_be32(0x3);
+		m->data[1] = cpu_to_be32(4);
+		m->data[2] = cpu_to_be32(0x11003);
+		m->len = 12;
+	} else {
+		/*
+		 * generate phony wdt message to pass to the user
+		 * type = 0x09 (trap)
+		 * IE type = 0xff01 (wdt), 4 bytes length
+		 */
+		m = list_entry(ml, struct moca_core_msg, chain);
+		m->data[0] = cpu_to_be32(0x09000001);
+		m->data[1] = cpu_to_be32((MOCA_IE_WDT << 16) | 4);
+		m->data[2] = cpu_to_be32(cpu);
+		m->len = 12;
+	}
+
+	moca_attach_tail(priv, ml, &priv->core_msg_pend_list);
+	wake_up(&priv->core_msg_wq);
+
+	return 0;
+}
+
+static int moca_get_mbx_offset(struct moca_priv_data *priv)
+{
+	const struct moca_regs *r = priv->regs;
+	uintptr_t base;
+
+	if (priv->mbx_offset[1] == -1) {
+		if (moca_is_20(priv))
+			base = MOCA_RD(priv->base +
+				r->moca2host_mmp_inbox_0_offset) &
+				0x1fffffff;
+		else
+			base = MOCA_RD(priv->base + r->gp0_offset) &
+				0x1fffffff;
+
+		if ((base == 0) ||
+			(base >= r->cntl_mem_size + r->cntl_mem_offset) ||
+			(base & 0x07)) {
+			dev_warn(priv->dev, "can't get mailbox base CPU 1 (%X)\n",
+				 (int)base);
+			return -1;
+		}
+		priv->mbx_offset[1] = base;
+	}
+
+	if ((priv->mbx_offset[0] == -1) && moca_is_20(priv) && priv->mmp_20) {
+		base = MOCA_RD(priv->base +
+			r->moca2host_mmp_inbox_2_offset) &
+			0x1fffffff;
+		if ((base == 0) ||
+			(base >= r->cntl_mem_size + r->cntl_mem_offset) ||
+			(base & 0x07)) {
+			dev_warn(priv->dev, "can't get mailbox base CPU 0 (%X)\n",
+				 (int)base);
+			return -1;
+		}
+
+		priv->mbx_offset[0] = base;
+	}
+
+	return 0;
+}
+
+/*
+ * INTERRUPT / WORKQUEUE BH
+ */
+
+static void moca_work_handler(struct work_struct *work)
+{
+	struct moca_priv_data *priv =
+		container_of(work, struct moca_priv_data, work);
+	u32 mask = 0;
+	int ret, stopped = 0;
+
+	if (priv->enabled) {
+		mask = moca_irq_status(priv, FLUSH_IRQ);
+		if (mask & M2H_DMA) {
+			mask &= ~M2H_DMA;
+			complete(&priv->copy_complete);
+		}
+
+		if (mask & M2H_NEXTCHUNK) {
+			mask &= ~M2H_NEXTCHUNK;
+			complete(&priv->chunk_complete);
+		}
+
+		if (moca_is_20(priv) && mask & M2H_NEXTCHUNK_CPU0) {
+			mask &= ~M2H_NEXTCHUNK_CPU0;
+			complete(&priv->chunk_complete);
+		}
+
+		if (mask == 0) {
+			moca_enable_irq(priv);
+			return;
+		}
+
+		if (mask & (M2H_REQ | M2H_RESP |
+			M2H_REQ_CPU0 | M2H_RESP_CPU0)) {
+			if (moca_get_mbx_offset(priv)) {
+				/* mbx interrupt but mbx_offset is bogus?? */
+				moca_enable_irq(priv);
+				return;
+			}
+		}
+	}
+
+	mutex_lock(&priv->dev_mutex);
+
+	if (!priv->running) {
+		stopped = 1;
+	} else {
+		/* fatal events */
+		if (mask & M2H_ASSERT) {
+			ret = moca_recvmsg(priv, priv->core_req_offset,
+				priv->core_req_size, 0, 1);
+			if (ret == -ENOMEM)
+				priv->assert_pending = 2;
+		}
+		if (mask & M2H_ASSERT_CPU0) {
+			ret = moca_recvmsg(priv, priv->core_req_offset,
+				priv->core_req_size, 0, 0);
+			if (ret == -ENOMEM)
+				priv->assert_pending = 1;
+		}
+		/* M2H_WDT_CPU1 is mapped to the only CPU for MoCA11 HW */
+		if (mask & M2H_WDT_CPU1) {
+			ret = moca_wdt(priv, 2);
+			if (ret == -ENOMEM)
+				priv->wdt_pending |= BIT(1);
+			stopped = 1;
+		}
+		if (moca_is_20(priv) && mask & M2H_WDT_CPU0) {
+			ret = moca_wdt(priv, 1);
+			if (ret == -ENOMEM)
+				priv->wdt_pending |= BIT(0);
+			stopped = 1;
+		}
+	}
+	if (stopped) {
+		priv->running = 0;
+		priv->core_req_pending = 0;
+		priv->host_resp_pending = 0;
+		priv->host_mbx_busy = 1;
+		mutex_unlock(&priv->dev_mutex);
+		wake_up(&priv->core_msg_wq);
+		return;
+	}
+
+	/* normal events */
+	if (mask & M2H_REQ) {
+		ret = moca_recvmsg(priv, priv->core_req_offset,
+			priv->core_req_size, priv->core_resp_offset, 1);
+		if (ret == -ENOMEM)
+			priv->core_req_pending = 2;
+	}
+	if (mask & M2H_RESP) {
+		ret = moca_recvmsg(priv, priv->host_resp_offset,
+			priv->host_resp_size, 0, 1);
+		if (ret == -ENOMEM)
+			priv->host_resp_pending = 2;
+		if (ret == 0) {
+			priv->host_mbx_busy = 0;
+			moca_sendmsg(priv, 1);
+		}
+	}
+
+	if (mask & M2H_REQ_CPU0) {
+		ret = moca_recvmsg(priv, priv->core_req_offset,
+			priv->core_req_size, priv->core_resp_offset, 0);
+		if (ret == -ENOMEM)
+			priv->core_req_pending = 1;
+	}
+	if (mask & M2H_RESP_CPU0) {
+		ret = moca_recvmsg(priv, priv->host_resp_offset,
+			priv->host_resp_size, 0, 0);
+		if (ret == -ENOMEM)
+			priv->host_resp_pending = 1;
+		if (ret == 0) {
+			priv->host_mbx_busy = 0;
+			moca_sendmsg(priv, 0);
+		}
+	}
+	mutex_unlock(&priv->dev_mutex);
+
+	moca_enable_irq(priv);
+}
+
+static irqreturn_t moca_interrupt(int irq, void *arg)
+{
+	struct moca_priv_data *priv = arg;
+
+	if (1) {
+		u32 mask = moca_irq_status(priv, FLUSH_DMA_ONLY);
+
+		/* need to handle DMA completions ASAP */
+		if (mask & M2H_DMA) {
+			complete(&priv->copy_complete);
+			mask &= ~M2H_DMA;
+		}
+		if (mask & M2H_NEXTCHUNK) {
+			complete(&priv->chunk_complete);
+			mask &= ~M2H_NEXTCHUNK;
+		}
+
+		if (!mask)
+			return IRQ_HANDLED;
+	}
+	moca_disable_irq(priv);
+	schedule_work(&priv->work);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * BCM3450 ACCESS VIA I2C
+ */
+
+static int moca_3450_wait(struct moca_priv_data *priv)
+{
+	struct bsc_regs *bsc = priv->i2c_base;
+	long timeout = HZ / 1000;	/* 1ms */
+	DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wait);
+	int i = 0;
+
+	do {
+		if (I2C_RD(&bsc->iic_enable) & 2) {
+			I2C_WR(&bsc->iic_enable, 0);
+			return 0;
+		}
+		if (i++ > 50) {
+			I2C_WR(&bsc->iic_enable, 0);
+			dev_warn(priv->dev, "3450 I2C timed out\n");
+			return -1;
+		}
+		sleep_on_timeout(&wait, timeout ? timeout : 1);
+	} while (1);
+}
+
+static void moca_3450_write_i2c(struct moca_priv_data *priv, u8 addr, u32 data)
+{
+	struct bsc_regs *bsc = priv->i2c_base;
+	struct moca_platform_data *pd = priv->pdev->dev.platform_data;
+
+	I2C_WR(&bsc->iic_enable, 0);
+	I2C_WR(&bsc->chip_address, pd->bcm3450_i2c_addr << 1);
+	I2C_WR(&bsc->data_in[0], (addr >> 2) | (data << 8));
+	I2C_WR(&bsc->data_in[1], data >> 24);
+	I2C_WR(&bsc->cnt_reg, (5 << 0) | (0 << 6));	/* 5B out, 0B in */
+	I2C_WR(&bsc->ctl_reg, (1 << 4) | (0 << 0));	/* write only, 390kHz */
+	I2C_WR(&bsc->ctlhi_reg, (1 << 6));		/* 32-bit words */
+	I2C_WR(&bsc->iic_enable, 1);
+
+	moca_3450_wait(priv);
+}
+
+static u32 moca_3450_read_i2c(struct moca_priv_data *priv, u8 addr)
+{
+	struct bsc_regs *bsc = priv->i2c_base;
+	struct moca_platform_data *pd = priv->pdev->dev.platform_data;
+
+	I2C_WR(&bsc->iic_enable, 0);
+	I2C_WR(&bsc->chip_address, pd->bcm3450_i2c_addr << 1);
+	I2C_WR(&bsc->data_in[0], (addr >> 2));
+	I2C_WR(&bsc->cnt_reg, (1 << 0) | (4 << 6));	/* 1B out then 4B in */
+	I2C_WR(&bsc->ctl_reg, (1 << 4) | (3 << 0));	/* write/read, 390kHz */
+	I2C_WR(&bsc->ctlhi_reg, (1 << 6));		/* 32-bit words */
+	I2C_WR(&bsc->iic_enable, 1);
+
+	if (moca_3450_wait(priv) == 0)
+		return I2C_RD(&bsc->data_out[0]);
+	else
+		return 0xffffffff;
+}
+
+#define BCM3450_CHIP_ID		0x00
+#define BCM3450_CHIP_REV	0x04
+#define BCM3450_LNACNTL		0x14
+#define BCM3450_PACNTL		0x18
+#define BCM3450_MISC		0x1c
+
+static int moca_3450_get_reg(struct moca_priv_data *priv, void __user *arg)
+{
+	struct moca_xfer x;
+	u32 *dst;
+	u32 val;
+
+	if (!priv->i2c_base)
+		return -ENODEV;
+
+	if (copy_from_user(&x, arg, sizeof(x)))
+		return -EFAULT;
+
+	dst = (u32 *)(uintptr_t)x.buf;
+
+	mutex_lock(&priv->moca_i2c_mutex);
+	val = moca_3450_read(priv, x.moca_addr);
+	mutex_unlock(&priv->moca_i2c_mutex);
+
+	if (put_user(val, dst))
+		return -EFAULT;
+
+	return 0;
+}
+
+static int moca_3450_set_reg(struct moca_priv_data *priv, void __user *arg)
+{
+	struct moca_xfer x;
+	u32 val, ret = 0;
+
+	if (!priv->i2c_base)
+		return -ENODEV;
+
+	if (copy_from_user(&x, arg, sizeof(x)))
+		return -EFAULT;
+
+	mutex_lock(&priv->moca_i2c_mutex);
+	if (get_user(val, (u32 *)(uintptr_t)x.buf)) {
+		ret = -EFAULT;
+		goto err_out;
+	}
+	moca_3450_write(priv, x.moca_addr, val);
+
+err_out:
+	mutex_unlock(&priv->moca_i2c_mutex);
+
+	return ret;
+}
+
+static void moca_3450_init(struct moca_priv_data *priv, int action)
+{
+	u32 data;
+
+	mutex_lock(&priv->moca_i2c_mutex);
+
+	if (action == MOCA_ENABLE) {
+		/* reset the 3450's I2C block */
+		moca_3450_write(priv, BCM3450_MISC,
+			moca_3450_read(priv, BCM3450_MISC) | 1);
+
+		/* verify chip ID */
+		data = moca_3450_read(priv, BCM3450_CHIP_ID);
+		if (data != 0x3450)
+			dev_warn(priv->dev, "invalid 3450 chip ID 0x%08x\n",
+				 data);
+
+		/* reset the 3450's deserializer */
+		data = moca_3450_read(priv, BCM3450_MISC);
+		data &= ~0x8000; /* power on PA/LNA */
+		moca_3450_write(priv, BCM3450_MISC, data | 2);
+		moca_3450_write(priv, BCM3450_MISC, data & ~2);
+
+		/* set new PA gain */
+		data = moca_3450_read(priv, BCM3450_PACNTL);
+
+		moca_3450_write(priv, BCM3450_PACNTL, (data & ~0x02007ffd) |
+			(0x09 << 11) |		/* RDEG */
+			(0x38 << 5) |		/* CURR_CONT */
+			(0x05 << 2));		/* CURR_FOLLOWER */
+
+		/* Set LNACNTRL to default value */
+		moca_3450_write(priv, BCM3450_LNACNTL, 0x4924);
+
+	} else {
+		/* power down the PA/LNA */
+		data = moca_3450_read(priv, BCM3450_MISC);
+		moca_3450_write(priv, BCM3450_MISC, data | 0x8000);
+
+		data = moca_3450_read(priv, BCM3450_PACNTL);
+		moca_3450_write(priv, BCM3450_PACNTL, data |
+			BIT(0) |	/* PA_PWRDWN */
+			BIT(25));	/* PA_SELECT_PWRUP_BSC */
+
+		data = moca_3450_read(priv, BCM3450_LNACNTL);
+		/* LNA_INBIAS=0, LNA_PWRUP_IIC=0: */
+		data &= ~((7<<12) | (1<<28));
+		/* LNA_SELECT_PWRUP_IIC=1: */
+		moca_3450_write(priv, BCM3450_LNACNTL, data | (1<<29));
+
+	}
+	mutex_unlock(&priv->moca_i2c_mutex);
+}
+
+/*
+ * FILE OPERATIONS
+ */
+
+static int moca_file_open(struct inode *inode, struct file *file)
+{
+	unsigned int minor = iminor(inode);
+	struct moca_priv_data *priv;
+
+	if ((minor > NUM_MINORS) || minor_tbl[minor] == NULL)
+		return -ENODEV;
+
+	file->private_data = priv = minor_tbl[minor];
+
+	mutex_lock(&priv->dev_mutex);
+	priv->refcount++;
+	mutex_unlock(&priv->dev_mutex);
+	return 0;
+}
+
+static int moca_file_release(struct inode *inode, struct file *file)
+{
+	struct moca_priv_data *priv = file->private_data;
+
+	mutex_lock(&priv->dev_mutex);
+	priv->refcount--;
+	if (priv->refcount == 0 && priv->running == 1) {
+		/* last user closed the device */
+		moca_msg_reset(priv);
+		moca_hw_init(priv, MOCA_DISABLE);
+	}
+	mutex_unlock(&priv->dev_mutex);
+	return 0;
+}
+
+static int moca_ioctl_readmem(struct moca_priv_data *priv,
+	unsigned long xfer_uaddr)
+{
+	struct moca_xfer x;
+	uintptr_t i, src;
+	u32 *dst;
+
+	if (copy_from_user(&x, (void __user *)xfer_uaddr, sizeof(x)))
+		return -EFAULT;
+
+	if (moca_range_ok(priv, x.moca_addr, x.len) < 0)
+		return -EINVAL;
+
+	src = (uintptr_t)priv->base + x.moca_addr;
+	dst = (void *)(unsigned long)x.buf;
+
+	for (i = 0; i < x.len; i += 4, src += 4, dst++)
+		if (put_user(cpu_to_be32(MOCA_RD(src)), dst))
+			return -EFAULT;
+
+	return 0;
+}
+
+static int moca_ioctl_writemem(struct moca_priv_data *priv,
+	unsigned long xfer_uaddr)
+{
+	struct moca_xfer x;
+	uintptr_t i, dst;
+	u32 *src;
+
+	if (copy_from_user(&x, (void __user *)xfer_uaddr, sizeof(x)))
+		return -EFAULT;
+
+	if (moca_range_ok(priv, x.moca_addr, x.len) < 0)
+		return -EINVAL;
+
+	dst = (uintptr_t)priv->base + x.moca_addr;
+	src = (void *)(unsigned long)x.buf;
+
+	for (i = 0; i < x.len; i += 4, src++, dst += 4) {
+		unsigned int x;
+		if (get_user(x, src))
+			return -EFAULT;
+
+		MOCA_WR(dst, cpu_to_be32(x));
+	}
+
+	return 0;
+}
+
+/* legacy ioctl - DEPRECATED */
+static int moca_ioctl_get_drv_info_v2(struct moca_priv_data *priv,
+	unsigned long arg)
+{
+	struct moca_kdrv_info_v2 info;
+	struct moca_platform_data *pd = priv->pdev->dev.platform_data;
+
+	memset(&info, 0, sizeof(info));
+	info.version = DRV_VERSION;
+	info.build_number = DRV_BUILD_NUMBER;
+	info.builtin_fw = !!bmoca_fw_image;
+
+	info.uptime = (jiffies - priv->start_time) / HZ;
+	info.refcount = priv->refcount;
+	if (moca_is_20(priv))
+		info.gp1 = priv->running ? MOCA_RD(priv->base +
+			priv->regs->moca2host_mmp_inbox_1_offset) : 0;
+	else
+		info.gp1 = priv->running ?
+			MOCA_RD(priv->base + priv->regs->gp1_offset) : 0;
+
+	memcpy(info.enet_name, pd->enet_name, MOCA_IFNAMSIZ);
+
+	info.enet_id = pd->enet_id;
+	info.macaddr_hi = pd->macaddr_hi;
+	info.macaddr_lo = pd->macaddr_lo;
+	info.hw_rev = pd->chip_id;
+	info.rf_band = pd->rf_band;
+
+	if (copy_to_user((void *)arg, &info, sizeof(info)))
+		return -EFAULT;
+
+	return 0;
+}
+
+static int moca_ioctl_get_drv_info(struct moca_priv_data *priv,
+	unsigned long arg)
+{
+	struct moca_kdrv_info info;
+	struct moca_platform_data *pd = priv->pdev->dev.platform_data;
+
+	memset(&info, 0, sizeof(info));
+	info.version = DRV_VERSION;
+	info.build_number = DRV_BUILD_NUMBER;
+	info.builtin_fw = !!bmoca_fw_image;
+
+	info.uptime = (jiffies - priv->start_time) / HZ;
+	info.refcount = priv->refcount;
+	if (moca_is_20(priv))
+		info.gp1 = priv->running ? MOCA_RD(priv->base +
+			priv->regs->moca2host_mmp_inbox_1_offset) : 0;
+	else
+		info.gp1 = priv->running ?
+			MOCA_RD(priv->base + priv->regs->gp1_offset) : 0;
+
+	memcpy(info.enet_name, pd->enet_name, MOCA_IFNAMSIZ);
+
+	info.enet_id = pd->enet_id;
+	info.macaddr_hi = pd->macaddr_hi;
+	info.macaddr_lo = pd->macaddr_lo;
+	info.chip_id = pd->chip_id;
+	info.hw_rev = pd->hw_rev;
+	info.rf_band = pd->rf_band;
+	info.phy_freq = priv->phy_freq;
+
+	if (copy_to_user((void *)arg, &info, sizeof(info)))
+		return -EFAULT;
+
+	return 0;
+}
+
+static int moca_ioctl_check_for_data(struct moca_priv_data *priv,
+	unsigned long arg)
+{
+	int data_avail = 0;
+	int ret;
+	u32 mask;
+
+	moca_disable_irq(priv);
+
+	moca_get_mbx_offset(priv);
+
+	/* If an IRQ is pending, process it here rather than waiting for it to
+	   ensure the results are ready. Clear the ones we are currently
+	   processing */
+	mask = moca_irq_status(priv, FLUSH_REQRESP_ONLY);
+
+	if (mask & M2H_REQ) {
+		ret = moca_recvmsg(priv, priv->core_req_offset,
+			priv->core_req_size, priv->core_resp_offset, 1);
+		if (ret == -ENOMEM)
+			priv->core_req_pending = 2;
+	}
+	if (mask & M2H_RESP) {
+		ret = moca_recvmsg(priv, priv->host_resp_offset,
+			priv->host_resp_size, 0, 1);
+		if (ret == -ENOMEM)
+			priv->host_resp_pending = 2;
+		if (ret == 0) {
+			priv->host_mbx_busy = 0;
+			moca_sendmsg(priv, 1);
+		}
+	}
+
+	if (mask & M2H_REQ_CPU0) {
+		ret = moca_recvmsg(priv, priv->core_req_offset,
+			priv->core_req_size, priv->core_resp_offset, 0);
+		if (ret == -ENOMEM)
+			priv->core_req_pending = 1;
+	}
+	if (mask & M2H_RESP_CPU0) {
+		ret = moca_recvmsg(priv, priv->host_resp_offset,
+			priv->host_resp_size, 0, 0);
+		if (ret == -ENOMEM)
+			priv->host_resp_pending = 1;
+		if (ret == 0) {
+			priv->host_mbx_busy = 0;
+			moca_sendmsg(priv, 0);
+		}
+	}
+
+	moca_enable_irq(priv);
+
+	spin_lock_bh(&priv->list_lock);
+	data_avail = !list_empty(&priv->core_msg_pend_list);
+	spin_unlock_bh(&priv->list_lock);
+
+	if (copy_to_user((void *)arg, &data_avail, sizeof(data_avail)))
+		return -EFAULT;
+
+	return 0;
+}
+
+unsigned int moca_get_proc_info(struct moca_priv_data *priv,
+		unsigned int *arg)
+{
+#ifdef BCHP_JTAG_OTP_REG_START
+#define JTAG_OTP_GENERAL_CTRL_0_OFFSET		0x0
+#define JTAG_OTP_GENERAL_CTRL_1_OFFSET		0x4
+#define JTAG_OTP_GENERAL_CTRL_3_OFFSET		0xc
+#define JTAG_OTP_GENERAL_STATUS_0_OFFSET	0x14
+#define JTAG_OTP_GENERAL_STATUS_1_OFFSET	0x18
+
+	unsigned int reg;
+	unsigned int read_data = 0;
+	int count = 0;
+
+	if (priv->proc_base) {
+		reg = MOCA_RD(priv->proc_base +
+			      JTAG_OTP_GENERAL_CTRL_1_OFFSET);
+		MOCA_WR(priv->proc_base + JTAG_OTP_GENERAL_CTRL_1_OFFSET,
+			(reg | 1));
+		MOCA_WR(priv->proc_base + JTAG_OTP_GENERAL_CTRL_3_OFFSET,
+			96);
+		MOCA_WR(priv->proc_base + JTAG_OTP_GENERAL_CTRL_0_OFFSET,
+			0);
+		MOCA_WR(priv->proc_base + JTAG_OTP_GENERAL_CTRL_0_OFFSET,
+			0xA00001);
+
+		reg = MOCA_RD(priv->proc_base +
+			      JTAG_OTP_GENERAL_STATUS_1_OFFSET);
+		while ((reg & 1) == 0) {
+			msleep(10);
+			reg = MOCA_RD(priv->proc_base +
+				      JTAG_OTP_GENERAL_STATUS_1_OFFSET);
+			count++;
+		}
+		read_data = MOCA_RD(priv->proc_base +
+				    JTAG_OTP_GENERAL_STATUS_0_OFFSET);
+		MOCA_WR(priv->proc_base + JTAG_OTP_GENERAL_CTRL_0_OFFSET, 0);
+	}
+
+	if (copy_to_user((void *)arg, &read_data, sizeof(read_data)))
+		return -EFAULT;
+
+	return 0;
+#else
+	return -EOPNOTSUPP;
+#endif
+}
+
+static long moca_file_ioctl(struct file *file, unsigned int cmd,
+	unsigned long arg)
+{
+	struct moca_priv_data *priv = file->private_data;
+	struct moca_start start;
+	long ret = -ENOTTY;
+
+	mutex_lock(&priv->dev_mutex);
+
+	switch (cmd) {
+	case MOCA_IOCTL_START:
+		ret = clk_set_rate(priv->phy_clk, DEFAULT_PHY_CLOCK);
+		/* FIXME: this fails on some platforms, so ignore the value */
+		ret = 0;
+		if (ret < 0)
+			break;
+
+		if (copy_from_user(&start, (void __user *)arg, sizeof(start)))
+			ret = -EFAULT;
+
+		if (ret >= 0) {
+			if (!priv->enabled) {
+				moca_msg_reset(priv);
+				moca_hw_init(priv, MOCA_ENABLE);
+				moca_3450_init(priv, MOCA_ENABLE);
+				moca_irq_status(priv, FLUSH_IRQ);
+				moca_mmp_init(priv, 0);
+			}
+			priv->bonded_mode =
+				(start.boot_flags & MOCA_BOOT_FLAGS_BONDED);
+			ret = moca_write_img(priv, &start.x);
+			if (ret >= 0)
+				priv->running = 1;
+		}
+		break;
+	case MOCA_IOCTL_STOP:
+		moca_msg_reset(priv);
+		moca_3450_init(priv, MOCA_DISABLE);
+		moca_hw_init(priv, MOCA_DISABLE);
+		ret = 0;
+		break;
+	case MOCA_IOCTL_READMEM:
+		if (priv->running)
+			ret = moca_ioctl_readmem(priv, arg);
+		break;
+	case MOCA_IOCTL_WRITEMEM:
+		if (priv->running)
+			ret = moca_ioctl_writemem(priv, arg);
+		break;
+	case MOCA_IOCTL_GET_DRV_INFO_V2:
+		ret = moca_ioctl_get_drv_info_v2(priv, arg);
+		break;
+	case MOCA_IOCTL_GET_DRV_INFO:
+		ret = moca_ioctl_get_drv_info(priv, arg);
+		break;
+	case MOCA_IOCTL_CHECK_FOR_DATA:
+		if (priv->running)
+			ret = moca_ioctl_check_for_data(priv, arg);
+		else
+			ret = -EIO;
+		break;
+	case MOCA_IOCTL_WOL:
+		priv->wol_enabled = (int)arg;
+		dev_info(priv->dev, "WOL is %s\n",
+			priv->wol_enabled ? "enabled" : "disabled");
+		ret = 0;
+		break;
+	case MOCA_IOCTL_SET_CPU_RATE:
+		if (!priv->cpu_clk)
+			ret = -EIO;
+		else
+			ret = clk_set_rate(priv->cpu_clk, (unsigned int)arg);
+		break;
+	case MOCA_IOCTL_SET_PHY_RATE:
+		if (!priv->phy_clk)
+			ret = -EIO;
+		else
+			ret = clk_set_rate(priv->phy_clk, (unsigned int)arg);
+		break;
+	case MOCA_IOCTL_GET_PROC_INFO:
+		ret = moca_get_proc_info(priv, (void __user *)arg);
+		break;
+	case MOCA_IOCTL_GET_3450_REG:
+		ret = moca_3450_get_reg(priv, (void __user *)arg);
+		break;
+	case MOCA_IOCTL_SET_3450_REG:
+		ret = moca_3450_set_reg(priv, (void __user *)arg);
+		break;
+	}
+	mutex_unlock(&priv->dev_mutex);
+
+	return ret;
+}
+
+static ssize_t moca_file_read(struct file *file, char __user *buf,
+	size_t count, loff_t *ppos)
+{
+	struct moca_priv_data *priv = file->private_data;
+	DECLARE_WAITQUEUE(wait, current);
+	struct list_head *ml = NULL;
+	struct moca_core_msg *m = NULL;
+	ssize_t ret;
+	int empty_free_list = 0;
+
+	if (count < priv->core_req_size)
+		return -EINVAL;
+
+	add_wait_queue(&priv->core_msg_wq, &wait);
+	do {
+		__set_current_state(TASK_INTERRUPTIBLE);
+
+		ml = moca_detach_head(priv, &priv->core_msg_pend_list);
+		if (ml != NULL) {
+			m = list_entry(ml, struct moca_core_msg, chain);
+			ret = 0;
+			break;
+		}
+		if (file->f_flags & O_NONBLOCK) {
+			ret = -EAGAIN;
+			break;
+		}
+		if (signal_pending(current)) {
+			ret = -ERESTARTSYS;
+			break;
+		}
+		schedule();
+	} while (1);
+	set_current_state(TASK_RUNNING);
+	remove_wait_queue(&priv->core_msg_wq, &wait);
+
+	if (ret < 0)
+		return ret;
+
+	if (copy_to_user(buf, m->data, m->len))
+		ret = -EFAULT;	/* beware: message will be dropped */
+	else
+		ret = m->len;
+
+	spin_lock_bh(&priv->list_lock);
+	if (list_empty(&priv->core_msg_free_list))
+		empty_free_list = 1;
+	list_add_tail(ml, &priv->core_msg_free_list);
+	spin_unlock_bh(&priv->list_lock);
+
+	if (empty_free_list) {
+		/*
+		 * we just freed up space for another message, so if there was
+		 * a backlog, clear it out
+		 */
+		mutex_lock(&priv->dev_mutex);
+
+		if (moca_get_mbx_offset(priv)) {
+			mutex_unlock(&priv->dev_mutex);
+			return -EIO;
+		}
+
+		if (priv->assert_pending & 2) {
+			if (moca_recvmsg(priv, priv->core_req_offset,
+				priv->core_req_size, 0, 1) != -ENOMEM)
+				priv->assert_pending &= ~2;
+			else
+				dev_warn(priv->dev, "moca_recvmsg assert failed\n");
+		}
+		if (priv->assert_pending & 1) {
+			if (moca_recvmsg(priv, priv->core_req_offset,
+				priv->core_req_size, 0, 0) != -ENOMEM)
+				priv->assert_pending &= ~1;
+			else
+				dev_warn(priv->dev, "moca_recvmsg assert failed\n");
+		}
+		if (priv->wdt_pending)
+			if (moca_wdt(priv, priv->wdt_pending) != -ENOMEM)
+				priv->wdt_pending = 0;
+
+		if (priv->core_req_pending & 1) {
+			if (moca_recvmsg(priv, priv->core_req_offset,
+				priv->core_req_size, priv->core_resp_offset, 0)
+				!= -ENOMEM)
+				priv->core_req_pending &= ~1;
+			else
+				dev_warn(priv->dev, "moca_recvmsg core_req failed\n");
+		}
+		if (priv->core_req_pending & 2) {
+			if (moca_recvmsg(priv, priv->core_req_offset,
+				priv->core_req_size, priv->core_resp_offset, 1)
+				!= -ENOMEM)
+				priv->core_req_pending &= ~2;
+			else
+				dev_warn(priv->dev, "moca_recvmsg core_req failed\n");
+		}
+		if (priv->host_resp_pending & 1) {
+			if (moca_recvmsg(priv, priv->host_resp_offset,
+				priv->host_resp_size, 0, 0) != -ENOMEM)
+				priv->host_resp_pending &= ~1;
+			else
+				dev_warn(priv->dev, "moca_recvmsg host_resp failed\n");
+		}
+		if (priv->host_resp_pending & 2) {
+			if (moca_recvmsg(priv, priv->host_resp_offset,
+				priv->host_resp_size, 0, 1) != -ENOMEM)
+				priv->host_resp_pending &= ~2;
+			else
+				dev_warn(priv->dev, "moca_recvmsg host_resp failed\n");
+		}
+		mutex_unlock(&priv->dev_mutex);
+	}
+
+	return ret;
+}
+
+static ssize_t moca_file_write(struct file *file, const char __user *buf,
+	size_t count, loff_t *ppos)
+{
+	struct moca_priv_data *priv = file->private_data;
+	DECLARE_WAITQUEUE(wait, current);
+	struct list_head *ml = NULL;
+	struct moca_host_msg *m = NULL;
+	ssize_t ret;
+	u32 cpuid;
+
+	if (count > priv->host_req_size)
+		return -EINVAL;
+
+	add_wait_queue(&priv->host_msg_wq, &wait);
+	do {
+		__set_current_state(TASK_INTERRUPTIBLE);
+
+		ml = moca_detach_head(priv, &priv->host_msg_free_list);
+		if (ml != NULL) {
+			m = list_entry(ml, struct moca_host_msg, chain);
+			ret = 0;
+			break;
+		}
+		if (file->f_flags & O_NONBLOCK) {
+			ret = -EAGAIN;
+			break;
+		}
+		if (signal_pending(current)) {
+			ret = -ERESTARTSYS;
+			break;
+		}
+		schedule();
+	} while (1);
+	set_current_state(TASK_RUNNING);
+	remove_wait_queue(&priv->host_msg_wq, &wait);
+
+	if (ret < 0)
+		return ret;
+
+	m->len = count;
+
+	if (copy_from_user(m->data, buf, m->len)) {
+		ret = -EFAULT;
+		goto bad;
+	}
+
+	ret = moca_h2m_sanity_check(priv, m);
+	if (ret < 0) {
+		ret = -EINVAL;
+		goto bad;
+	}
+
+	moca_attach_tail(priv, ml, &priv->host_msg_pend_list);
+
+	if (!priv->mmp_20)
+		cpuid = 1;
+	else {
+		if (cpu_to_be32(m->data[0]) & 0x10)
+			cpuid = 0;
+		else
+			cpuid = 1;
+	}
+	mutex_lock(&priv->dev_mutex);
+	if (priv->running) {
+		if (moca_get_mbx_offset(priv))
+			ret = -EIO;
+		else
+			moca_sendmsg(priv, cpuid);
+	} else
+		ret = -EIO;
+	mutex_unlock(&priv->dev_mutex);
+
+	return ret;
+
+bad:
+	moca_attach_tail(priv, ml, &priv->host_msg_free_list);
+
+	return ret;
+}
+
+static unsigned int moca_file_poll(struct file *file, poll_table *wait)
+{
+	struct moca_priv_data *priv = file->private_data;
+	unsigned int ret = 0;
+
+	poll_wait(file, &priv->core_msg_wq, wait);
+	poll_wait(file, &priv->host_msg_wq, wait);
+
+	spin_lock_bh(&priv->list_lock);
+	if (!list_empty(&priv->core_msg_pend_list))
+		ret |= POLLIN | POLLRDNORM;
+	if (!list_empty(&priv->host_msg_free_list))
+		ret |= POLLOUT | POLLWRNORM;
+	spin_unlock_bh(&priv->list_lock);
+
+	return ret;
+}
+
+static const struct file_operations moca_fops = {
+	.owner =		THIS_MODULE,
+	.open =			moca_file_open,
+	.release =		moca_file_release,
+	.unlocked_ioctl =	moca_file_ioctl,
+	.read =			moca_file_read,
+	.write =		moca_file_write,
+	.poll =			moca_file_poll,
+};
+
+/*
+ * PLATFORM DRIVER
+ */
+
+static int moca_probe(struct platform_device *pdev)
+{
+	struct moca_priv_data *priv;
+	struct resource *mres, *ires;
+	int minor, err;
+	struct moca_platform_data *pd = pdev->dev.platform_data;
+
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	if (!priv) {
+		pr_err("out of memory\n");
+		return -ENOMEM;
+	}
+	dev_set_drvdata(&pdev->dev, priv);
+	priv->pdev = pdev;
+	priv->start_time = jiffies;
+
+	priv->clk = clk_get(&pdev->dev, "moca");
+	priv->cpu_clk = clk_get(&pdev->dev, "moca-cpu");
+	priv->phy_clk = clk_get(&pdev->dev, "moca-phy");
+
+	priv->proc_base = NULL;
+
+	priv->hw_rev = pd->hw_rev;
+	if (pd->hw_rev == HWREV_MOCA_11_PLUS)
+		priv->regs = &regs_11_plus;
+	else if (pd->hw_rev == HWREV_MOCA_11_LITE)
+		priv->regs = &regs_11_lite;
+	else if (pd->hw_rev == HWREV_MOCA_11)
+		priv->regs = &regs_11;
+	else if ((pd->hw_rev == HWREV_MOCA_20_GEN21) ||
+		(pd->hw_rev == HWREV_MOCA_20_GEN22)) {
+		priv->regs = &regs_20;
+#ifdef BCHP_JTAG_OTP_REG_START
+		priv->proc_base = ioremap(BCHP_JTAG_OTP_REG_START,
+			(BCHP_JTAG_OTP_REG_END - BCHP_JTAG_OTP_REG_START + 4));
+#endif
+	} else {
+		pr_err("unsupported MoCA HWREV: %x\n", pd->hw_rev);
+		err = -EINVAL;
+		goto bad;
+	}
+
+	init_waitqueue_head(&priv->host_msg_wq);
+	init_waitqueue_head(&priv->core_msg_wq);
+	init_completion(&priv->copy_complete);
+	init_completion(&priv->chunk_complete);
+
+	spin_lock_init(&priv->list_lock);
+	spin_lock_init(&priv->clock_lock);
+	spin_lock_init(&priv->irq_status_lock);
+
+	mutex_init(&priv->dev_mutex);
+	mutex_init(&priv->copy_mutex);
+	mutex_init(&priv->moca_i2c_mutex);
+
+	sg_init_table(priv->fw_sg, MAX_FW_PAGES);
+
+	INIT_WORK(&priv->work, moca_work_handler);
+
+	priv->minor = -1;
+	for (minor = 0; minor < NUM_MINORS; minor++) {
+		if (minor_tbl[minor] == NULL) {
+			priv->minor = minor;
+			break;
+		}
+	}
+
+	if (priv->minor == -1) {
+		pr_err("can't allocate minor device\n");
+		err = -EIO;
+		goto bad;
+	}
+
+	mres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!mres || !ires) {
+		pr_err("can't get resources\n");
+		err = -EIO;
+		goto bad;
+	}
+	priv->base = ioremap(mres->start, mres->end - mres->start + 1);
+	priv->irq = ires->start;
+	priv->i2c_base = ioremap(pd->bcm3450_i2c_base, sizeof(struct bsc_regs));
+
+	/* leave core in reset until we get an ioctl */
+
+	moca_hw_reset(priv);
+
+	if (request_irq(priv->irq, moca_interrupt, 0, "moca", priv) < 0) {
+		pr_err("can't request interrupt\n");
+		err = -EIO;
+		goto bad2;
+	}
+	moca_hw_init(priv, MOCA_ENABLE);
+	moca_disable_irq(priv);
+	moca_msg_reset(priv);
+	moca_hw_init(priv, MOCA_DISABLE);
+
+	pr_info("adding minor #%d at base 0x%08llx, IRQ %d, "
+		"I2C 0x%08llx/0x%02x\n", priv->minor,
+		(unsigned long long)mres->start, ires->start,
+		(unsigned long long)pd->bcm3450_i2c_base, pd->bcm3450_i2c_addr);
+
+	minor_tbl[priv->minor] = priv;
+	priv->dev = device_create(moca_class, NULL,
+		MKDEV(MOCA_MAJOR, priv->minor), NULL, "bmoca%d", priv->minor);
+	if (IS_ERR(priv->dev)) {
+		pr_warn("can't register class device\n");
+		priv->dev = NULL;
+	}
+
+	return 0;
+
+bad2:
+	if (priv->base)
+		iounmap(priv->base);
+	if (priv->i2c_base)
+		iounmap(priv->i2c_base);
+bad:
+	if (priv->proc_base)
+		iounmap(priv->proc_base);
+	kfree(priv);
+	return err;
+}
+
+static int moca_remove(struct platform_device *pdev)
+{
+	struct moca_priv_data *priv = dev_get_drvdata(&pdev->dev);
+	struct clk *clk = priv->clk;
+	struct clk *phy_clk = priv->phy_clk;
+	struct clk *cpu_clk = priv->cpu_clk;
+
+	if (priv->dev)
+		device_destroy(moca_class, MKDEV(MOCA_MAJOR, priv->minor));
+	minor_tbl[priv->minor] = NULL;
+
+	free_irq(priv->irq, priv);
+	iounmap(priv->i2c_base);
+	iounmap(priv->base);
+	if (priv->proc_base)
+		iounmap(priv->proc_base);
+
+	kfree(priv);
+
+	clk_put(cpu_clk);
+	clk_put(phy_clk);
+	clk_put(clk);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int moca_suspend(struct device *dev)
+{
+	/* do not do anything on suspend.
+	MoCA core is not necessarily stopped */
+
+	return 0;
+}
+
+static int moca_resume(struct device *dev)
+{
+	return 0;
+}
+
+static const struct dev_pm_ops moca_pm_ops = {
+	.suspend		= moca_suspend,
+	.resume			= moca_resume,
+};
+
+#endif
+
+static struct platform_driver moca_plat_drv = {
+	.probe =		moca_probe,
+	.remove =		moca_remove,
+	.driver = {
+		.name =		"bmoca",
+		.owner =	THIS_MODULE,
+#ifdef CONFIG_PM
+		.pm =		&moca_pm_ops,
+#endif
+	},
+};
+
+static int moca_init(void)
+{
+	int ret;
+	memset(minor_tbl, 0, sizeof(minor_tbl));
+	ret = register_chrdev(MOCA_MAJOR, MOCA_CLASS, &moca_fops);
+	if (ret < 0) {
+		pr_err("can't register major %d\n", MOCA_MAJOR);
+		goto bad;
+	}
+
+	moca_class = class_create(THIS_MODULE, MOCA_CLASS);
+	if (IS_ERR(moca_class)) {
+		pr_err("can't create device class\n");
+		ret = PTR_ERR(moca_class);
+		goto bad2;
+	}
+
+	ret = platform_driver_register(&moca_plat_drv);
+	if (ret < 0) {
+		pr_err("can't register platform_driver\n");
+		goto bad3;
+	}
+
+	return 0;
+
+bad3:
+	class_destroy(moca_class);
+bad2:
+	unregister_chrdev(MOCA_MAJOR, MOCA_CLASS);
+bad:
+	return ret;
+}
+
+static void moca_exit(void)
+{
+	class_destroy(moca_class);
+	unregister_chrdev(MOCA_MAJOR, MOCA_CLASS);
+	platform_driver_unregister(&moca_plat_drv);
+
+}
+
+module_init(moca_init);
+module_exit(moca_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("MoCA messaging driver");
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 8deedc1..c3f6c94 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -1063,6 +1063,16 @@ config SENSORS_SCH5636
 	  This driver can also be built as a module.  If so, the module
 	  will be called sch5636.
 
+config SENSORS_ADC128D818
+	tristate "Texas Instruments ADC128D818"
+	depends on I2C
+	help
+	  If you say yes here you get support for the Texas Instruments
+	  ADC128D818 System Monitor with Temperature Sensor chip.
+
+	  This driver can also be built as a module. If so, the module
+	  will be called adc128d818.
+
 config SENSORS_ADS1015
 	tristate "Texas Instruments ADS1015"
 	depends on I2C
@@ -1102,6 +1112,19 @@ config SENSORS_AMC6821
 	  This driver can also be build as a module.  If so, the module
 	  will be called amc6821.
 
+config SENSORS_INA2XX
+	tristate "Texas Instruments INA219 and compatibles"
+	depends on I2C && EXPERIMENTAL
+	help
+	  If you say yes here you get support for INA219, INA220, INA226, and
+	  INA230 power monitor chips.
+
+	  The INA2xx driver is configured for the default configuration of
+	  the part as described in the datasheet.
+	  Default value for Rshunt is 10 mOhms.
+	  This driver can also be built as a module.  If so, the module
+	  will be called ina2xx.
+
 config SENSORS_THMC50
 	tristate "Texas Instruments THMC50 / Analog Devices ADM1022"
 	depends on I2C
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 6d3f11f..b11327d 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_SENSORS_ABITUGURU3)+= abituguru3.o
 obj-$(CONFIG_SENSORS_AD7314)	+= ad7314.o
 obj-$(CONFIG_SENSORS_AD7414)	+= ad7414.o
 obj-$(CONFIG_SENSORS_AD7418)	+= ad7418.o
+obj-$(CONFIG_SENSORS_ADC128D818) += adc128d818.o
 obj-$(CONFIG_SENSORS_ADCXX)	+= adcxx.o
 obj-$(CONFIG_SENSORS_ADM1021)	+= adm1021.o
 obj-$(CONFIG_SENSORS_ADM1025)	+= adm1025.o
@@ -62,6 +63,7 @@ obj-$(CONFIG_SENSORS_ULTRA45)	+= ultra45_env.o
 obj-$(CONFIG_SENSORS_I5K_AMB)	+= i5k_amb.o
 obj-$(CONFIG_SENSORS_IBMAEM)	+= ibmaem.o
 obj-$(CONFIG_SENSORS_IBMPEX)	+= ibmpex.o
+obj-$(CONFIG_SENSORS_INA2XX)	+= ina2xx.o
 obj-$(CONFIG_SENSORS_IT87)	+= it87.o
 obj-$(CONFIG_SENSORS_JC42)	+= jc42.o
 obj-$(CONFIG_SENSORS_JZ4740)	+= jz4740-hwmon.o
diff --git a/drivers/hwmon/adc128d818.c b/drivers/hwmon/adc128d818.c
new file mode 100644
index 0000000..1c23cb7
--- /dev/null
+++ b/drivers/hwmon/adc128d818.c
@@ -0,0 +1,577 @@
+/*
+ * Driver for TI ADC128D818 System Monitor with Temperature Sensor
+ *
+ * Copyright (c) 2014 Guenter Roeck
+ * Copyright (c) 2014 Andreas Oberritter
+ *
+ * Derived from lm80.c
+ * Copyright (C) 1998, 1999  Frodo Looijaard <frodol@dds.nl>
+ *			     and Philip Edelbrock <phil@netroedge.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/jiffies.h>
+#include <linux/i2c.h>
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/err.h>
+#include <linux/regulator/consumer.h>
+#include <linux/mutex.h>
+#include <linux/platform_data/adc128d818.h>
+
+/* Addresses to scan
+ * The chip also supports addresses 0x35..0x37. Don't scan those addresses
+ * since they are also used by some EEPROMs, which may result in false
+ * positives.
+ */
+static const unsigned short normal_i2c[] = {
+	0x1d, 0x1e, 0x1f, 0x2d, 0x2e, 0x2f, I2C_CLIENT_END };
+
+/* registers */
+#define ADC128_REG_IN_MAX(nr)		(0x2a + (nr) * 2)
+#define ADC128_REG_IN_MIN(nr)		(0x2b + (nr) * 2)
+#define ADC128_REG_IN(nr)		(0x20 + (nr))
+
+#define ADC128_REG_TEMP			0x27
+#define ADC128_REG_TEMP_MAX		0x38
+#define ADC128_REG_TEMP_HYST		0x39
+
+#define ADC128_REG_CONFIG		0x00
+#define ADC128_REG_ALARM		0x01
+#define ADC128_REG_MASK			0x03
+#define ADC128_REG_CONV_RATE		0x07
+#define ADC128_REG_ONESHOT		0x09
+#define ADC128_REG_SHUTDOWN		0x0a
+#define ADC128_REG_CONFIG_ADV		0x0b
+#define ADC128_REG_BUSY_STATUS		0x0c
+
+#define ADC128_REG_MAN_ID		0x3e
+#define ADC128_REG_DEV_ID		0x3f
+
+struct adc128_data {
+	struct i2c_client *client;
+	struct regulator *regulator;
+	int vref;		/* Reference voltage in mV */
+	struct mutex update_lock;
+	bool valid;		/* true if following fields are valid */
+	unsigned long last_updated;	/* In jiffies */
+	unsigned int mode;	/* Mode of operation */
+	unsigned int vlt_channels;	/* Number of voltage channels */
+
+	u16 in[3][8];		/* Register value, normalized to 12 bit
+				 * 0: input voltage
+				 * 1: min limit
+				 * 2: max limit
+				 */
+	s16 temp[3];		/* Register value, normalized to 9 bit
+				 * 0: sensor 1: limit 2: hyst
+				 */
+	u8 alarms;		/* alarm register value */
+};
+
+static struct adc128_data *adc128_update_device(struct device *dev)
+{
+	struct adc128_data *data = dev_get_drvdata(dev);
+	struct i2c_client *client = data->client;
+	struct adc128_data *ret = data;
+	int i, rv;
+
+	mutex_lock(&data->update_lock);
+
+	if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
+		for (i = 0; i < data->vlt_channels; i++) {
+			rv = i2c_smbus_read_word_swapped(client,
+							 ADC128_REG_IN(i));
+			if (rv < 0)
+				goto abort;
+			data->in[0][i] = rv >> 4;
+
+			rv = i2c_smbus_read_byte_data(client,
+						      ADC128_REG_IN_MIN(i));
+			if (rv < 0)
+				goto abort;
+			data->in[1][i] = rv << 4;
+
+			rv = i2c_smbus_read_byte_data(client,
+						      ADC128_REG_IN_MAX(i));
+			if (rv < 0)
+				goto abort;
+			data->in[2][i] = rv << 4;
+		}
+
+		if (data->vlt_channels < 8) {
+			rv = i2c_smbus_read_word_swapped(client, ADC128_REG_TEMP);
+			if (rv < 0)
+				goto abort;
+			data->temp[0] = rv >> 7;
+
+			rv = i2c_smbus_read_byte_data(client, ADC128_REG_TEMP_MAX);
+			if (rv < 0)
+				goto abort;
+			data->temp[1] = rv << 1;
+
+			rv = i2c_smbus_read_byte_data(client, ADC128_REG_TEMP_HYST);
+			if (rv < 0)
+				goto abort;
+			data->temp[2] = rv << 1;
+		}
+
+		rv = i2c_smbus_read_byte_data(client, ADC128_REG_ALARM);
+		if (rv < 0)
+			goto abort;
+		data->alarms |= rv;
+
+		data->last_updated = jiffies;
+		data->valid = true;
+	}
+	goto done;
+
+abort:
+	ret = ERR_PTR(rv);
+	data->valid = false;
+done:
+	mutex_unlock(&data->update_lock);
+	return ret;
+}
+
+static ssize_t adc128_show_in(struct device *dev, struct device_attribute *attr,
+			      char *buf)
+{
+	struct adc128_data *data = adc128_update_device(dev);
+	int index = to_sensor_dev_attr_2(attr)->index;
+	int nr = to_sensor_dev_attr_2(attr)->nr;
+	int val;
+
+	if (IS_ERR(data))
+		return PTR_ERR(data);
+
+	val = DIV_ROUND_CLOSEST(data->in[index][nr] * data->vref, 4095);
+	return sprintf(buf, "%d\n", val);
+}
+
+static ssize_t adc128_set_in(struct device *dev, struct device_attribute *attr,
+			     const char *buf, size_t count)
+{
+	struct adc128_data *data = dev_get_drvdata(dev);
+	int index = to_sensor_dev_attr_2(attr)->index;
+	int nr = to_sensor_dev_attr_2(attr)->nr;
+	u8 reg, regval;
+	long val;
+	int err;
+
+	err = kstrtol(buf, 10, &val);
+	if (err < 0)
+		return err;
+
+	mutex_lock(&data->update_lock);
+	/* 10 mV LSB on limit registers */
+	regval = clamp_val(DIV_ROUND_CLOSEST(val, 10), 0, 255);
+	data->in[index][nr] = regval << 4;
+	reg = index == 1 ? ADC128_REG_IN_MIN(nr) : ADC128_REG_IN_MAX(nr);
+	i2c_smbus_write_byte_data(data->client, reg, regval);
+	mutex_unlock(&data->update_lock);
+
+	return count;
+}
+
+static ssize_t adc128_show_temp(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct adc128_data *data = adc128_update_device(dev);
+	int index = to_sensor_dev_attr(attr)->index;
+	int temp;
+
+	if (IS_ERR(data))
+		return PTR_ERR(data);
+
+	temp = (data->temp[index] << 7) >> 7;	/* sign extend */
+	return sprintf(buf, "%d\n", temp * 500);/* 0.5 degrees C resolution */
+}
+
+static ssize_t adc128_set_temp(struct device *dev,
+			       struct device_attribute *attr,
+			       const char *buf, size_t count)
+{
+	struct adc128_data *data = dev_get_drvdata(dev);
+	int index = to_sensor_dev_attr(attr)->index;
+	long val;
+	int err;
+	s8 regval;
+
+	err = kstrtol(buf, 10, &val);
+	if (err < 0)
+		return err;
+
+	mutex_lock(&data->update_lock);
+	regval = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
+	data->temp[index] = regval << 1;
+	i2c_smbus_write_byte_data(data->client,
+				  index == 1 ? ADC128_REG_TEMP_MAX
+					     : ADC128_REG_TEMP_HYST,
+				  regval);
+	mutex_unlock(&data->update_lock);
+
+	return count;
+}
+
+static ssize_t adc128_show_alarm(struct device *dev,
+				 struct device_attribute *attr, char *buf)
+{
+	struct adc128_data *data = adc128_update_device(dev);
+	int mask = 1 << to_sensor_dev_attr(attr)->index;
+	u8 alarms;
+
+	if (IS_ERR(data))
+		return PTR_ERR(data);
+
+	/*
+	 * Clear an alarm after reporting it to user space. If it is still
+	 * active, the next update sequence will set the alarm bit again.
+	 */
+	alarms = data->alarms;
+	data->alarms &= ~mask;
+
+	return sprintf(buf, "%u\n", !!(alarms & mask));
+}
+
+static int adc128_set_config_adv(struct adc128_data *data)
+{
+	unsigned int nchannels_lut[] = { 7, 8, 4, 6 };
+	u8 regval;
+	int err;
+
+	BUG_ON(data->mode > 3);
+
+	mutex_lock(&data->update_lock);
+	regval = (data->mode << 1);
+	/* If external vref is selected, configure the chip to use it */
+	if (data->regulator)
+		regval |= 0x01;
+	err = i2c_smbus_write_byte_data(data->client, ADC128_REG_CONFIG_ADV, regval);
+	data->vlt_channels = nchannels_lut[data->mode];
+	memset(data->in, 0, sizeof(data->in));
+	memset(data->temp, 0, sizeof(data->temp));
+	mutex_unlock(&data->update_lock);
+
+	return err;
+}
+
+static ssize_t adc128_show_mode(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct adc128_data *data = adc128_update_device(dev);
+
+	if (IS_ERR(data))
+		return PTR_ERR(data);
+
+	return sprintf(buf, "%u\n", data->mode);
+}
+
+static ssize_t adc128_set_mode(struct device *dev,
+			       struct device_attribute *attr,
+			       const char *buf, size_t count)
+{
+	struct adc128_data *data = dev_get_drvdata(dev);
+	long val;
+	int err;
+
+	if (IS_ERR(data))
+		return PTR_ERR(data);
+
+	err = kstrtol(buf, 10, &val);
+	if (err < 0)
+		return err;
+
+	if (val < 0 || val > 3)
+		return -EINVAL;
+
+	data->mode = val;
+	err = adc128_set_config_adv(data);
+	if (err < 0)
+		return err;
+
+	return count;
+}
+
+static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO,
+			    adc128_show_in, NULL, 0, 0);
+static SENSOR_DEVICE_ATTR_2(in0_min, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 0, 1);
+static SENSOR_DEVICE_ATTR_2(in0_max, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 0, 2);
+
+static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO,
+			    adc128_show_in, NULL, 1, 0);
+static SENSOR_DEVICE_ATTR_2(in1_min, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 1, 1);
+static SENSOR_DEVICE_ATTR_2(in1_max, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 1, 2);
+
+static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO,
+			    adc128_show_in, NULL, 2, 0);
+static SENSOR_DEVICE_ATTR_2(in2_min, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 2, 1);
+static SENSOR_DEVICE_ATTR_2(in2_max, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 2, 2);
+
+static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO,
+			    adc128_show_in, NULL, 3, 0);
+static SENSOR_DEVICE_ATTR_2(in3_min, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 3, 1);
+static SENSOR_DEVICE_ATTR_2(in3_max, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 3, 2);
+
+static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO,
+			    adc128_show_in, NULL, 4, 0);
+static SENSOR_DEVICE_ATTR_2(in4_min, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 4, 1);
+static SENSOR_DEVICE_ATTR_2(in4_max, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 4, 2);
+
+static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO,
+			    adc128_show_in, NULL, 5, 0);
+static SENSOR_DEVICE_ATTR_2(in5_min, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 5, 1);
+static SENSOR_DEVICE_ATTR_2(in5_max, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 5, 2);
+
+static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO,
+			    adc128_show_in, NULL, 6, 0);
+static SENSOR_DEVICE_ATTR_2(in6_min, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 6, 1);
+static SENSOR_DEVICE_ATTR_2(in6_max, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 6, 2);
+
+static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO,
+			    adc128_show_in, NULL, 7, 0);
+static SENSOR_DEVICE_ATTR_2(in7_min, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 7, 1);
+static SENSOR_DEVICE_ATTR_2(in7_max, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 7, 2);
+
+static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, adc128_show_temp, NULL, 0);
+static SENSOR_DEVICE_ATTR(temp1_max, S_IWUSR | S_IRUGO,
+			  adc128_show_temp, adc128_set_temp, 1);
+static SENSOR_DEVICE_ATTR(temp1_max_hyst, S_IWUSR | S_IRUGO,
+			  adc128_show_temp, adc128_set_temp, 2);
+
+static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, adc128_show_alarm, NULL, 0);
+static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, adc128_show_alarm, NULL, 1);
+static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, adc128_show_alarm, NULL, 2);
+static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, adc128_show_alarm, NULL, 3);
+static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, adc128_show_alarm, NULL, 4);
+static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, adc128_show_alarm, NULL, 5);
+static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, adc128_show_alarm, NULL, 6);
+static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, adc128_show_alarm, NULL, 7);
+static SENSOR_DEVICE_ATTR(temp1_max_alarm, S_IRUGO, adc128_show_alarm, NULL, 7);
+
+static SENSOR_DEVICE_ATTR(mode, S_IWUSR | S_IRUGO, adc128_show_mode, adc128_set_mode, 0);
+
+static struct attribute *adc128_attrs[] = {
+	&sensor_dev_attr_in0_min.dev_attr.attr,
+	&sensor_dev_attr_in1_min.dev_attr.attr,
+	&sensor_dev_attr_in2_min.dev_attr.attr,
+	&sensor_dev_attr_in3_min.dev_attr.attr,
+	&sensor_dev_attr_in4_min.dev_attr.attr,
+	&sensor_dev_attr_in5_min.dev_attr.attr,
+	&sensor_dev_attr_in6_min.dev_attr.attr,
+	&sensor_dev_attr_in7_min.dev_attr.attr,
+	&sensor_dev_attr_in0_max.dev_attr.attr,
+	&sensor_dev_attr_in1_max.dev_attr.attr,
+	&sensor_dev_attr_in2_max.dev_attr.attr,
+	&sensor_dev_attr_in3_max.dev_attr.attr,
+	&sensor_dev_attr_in4_max.dev_attr.attr,
+	&sensor_dev_attr_in5_max.dev_attr.attr,
+	&sensor_dev_attr_in6_max.dev_attr.attr,
+	&sensor_dev_attr_in7_max.dev_attr.attr,
+	&sensor_dev_attr_in0_input.dev_attr.attr,
+	&sensor_dev_attr_in1_input.dev_attr.attr,
+	&sensor_dev_attr_in2_input.dev_attr.attr,
+	&sensor_dev_attr_in3_input.dev_attr.attr,
+	&sensor_dev_attr_in4_input.dev_attr.attr,
+	&sensor_dev_attr_in5_input.dev_attr.attr,
+	&sensor_dev_attr_in6_input.dev_attr.attr,
+	&sensor_dev_attr_in7_input.dev_attr.attr,
+	&sensor_dev_attr_temp1_input.dev_attr.attr,
+	&sensor_dev_attr_temp1_max.dev_attr.attr,
+	&sensor_dev_attr_temp1_max_hyst.dev_attr.attr,
+	&sensor_dev_attr_in0_alarm.dev_attr.attr,
+	&sensor_dev_attr_in1_alarm.dev_attr.attr,
+	&sensor_dev_attr_in2_alarm.dev_attr.attr,
+	&sensor_dev_attr_in3_alarm.dev_attr.attr,
+	&sensor_dev_attr_in4_alarm.dev_attr.attr,
+	&sensor_dev_attr_in5_alarm.dev_attr.attr,
+	&sensor_dev_attr_in6_alarm.dev_attr.attr,
+	&sensor_dev_attr_in7_alarm.dev_attr.attr,
+	&sensor_dev_attr_temp1_max_alarm.dev_attr.attr,
+	&sensor_dev_attr_mode.dev_attr.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(adc128);
+
+static int adc128_detect(struct i2c_client *client, struct i2c_board_info *info)
+{
+	int man_id, dev_id;
+
+	if (!i2c_check_functionality(client->adapter,
+				     I2C_FUNC_SMBUS_BYTE_DATA |
+				     I2C_FUNC_SMBUS_WORD_DATA))
+		return -ENODEV;
+
+	man_id = i2c_smbus_read_byte_data(client, ADC128_REG_MAN_ID);
+	dev_id = i2c_smbus_read_byte_data(client, ADC128_REG_DEV_ID);
+	if (man_id != 0x01 || dev_id != 0x09)
+		return -ENODEV;
+
+	/* Check unused bits for confirmation */
+	if (i2c_smbus_read_byte_data(client, ADC128_REG_CONFIG) & 0xf4)
+		return -ENODEV;
+	if (i2c_smbus_read_byte_data(client, ADC128_REG_CONV_RATE) & 0xfe)
+		return -ENODEV;
+	if (i2c_smbus_read_byte_data(client, ADC128_REG_ONESHOT) & 0xfe)
+		return -ENODEV;
+	if (i2c_smbus_read_byte_data(client, ADC128_REG_SHUTDOWN) & 0xfe)
+		return -ENODEV;
+	if (i2c_smbus_read_byte_data(client, ADC128_REG_CONFIG_ADV) & 0xf8)
+		return -ENODEV;
+	if (i2c_smbus_read_byte_data(client, ADC128_REG_BUSY_STATUS) & 0xfc)
+		return -ENODEV;
+
+	strlcpy(info->type, "adc128d818", I2C_NAME_SIZE);
+
+	return 0;
+}
+
+static int adc128_init_client(struct adc128_data *data)
+{
+	struct i2c_client *client = data->client;
+	int err;
+
+	/*
+	 * Reset chip to defaults.
+	 * This makes most other initializations unnecessary.
+	 */
+	err = i2c_smbus_write_byte_data(client, ADC128_REG_CONFIG, 0x80);
+	if (err)
+		return err;
+
+	/* Start monitoring */
+	err = i2c_smbus_write_byte_data(client, ADC128_REG_CONFIG, 0x01);
+	if (err)
+		return err;
+
+	err = adc128_set_config_adv(data);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+static int adc128_probe(struct i2c_client *client,
+			const struct i2c_device_id *id)
+{
+	struct adc128_platform_data *pdata;
+	struct device *dev = &client->dev;
+	struct regulator *regulator;
+	struct device *hwmon_dev;
+	struct adc128_data *data;
+	int err, vref;
+
+	data = devm_kzalloc(dev, sizeof(struct adc128_data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	/* vref is optional. If specified, is used as chip reference voltage */
+	regulator = devm_regulator_get_optional(dev, "vref");
+	if (!IS_ERR(regulator)) {
+		data->regulator = regulator;
+		err = regulator_enable(regulator);
+		if (err < 0)
+			return err;
+		vref = regulator_get_voltage(regulator);
+		if (vref < 0) {
+			err = vref;
+			goto error;
+		}
+		data->vref = DIV_ROUND_CLOSEST(vref, 1000);
+	} else {
+		data->vref = 2560;	/* 2.56V, in mV */
+	}
+
+	pdata = dev_get_platdata(dev);
+	if (pdata) {
+		if (pdata->mode > 3) {
+			err = -EINVAL;
+			goto error;
+		}
+		data->mode = pdata->mode;
+	}
+
+	data->client = client;
+	i2c_set_clientdata(client, data);
+	mutex_init(&data->update_lock);
+
+	/* Initialize the chip */
+	err = adc128_init_client(data);
+	if (err < 0)
+		goto error;
+
+	hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name,
+							   data, adc128_groups);
+	if (IS_ERR(hwmon_dev)) {
+		err = PTR_ERR(hwmon_dev);
+		goto error;
+	}
+
+	return 0;
+
+error:
+	if (data->regulator)
+		regulator_disable(data->regulator);
+	return err;
+}
+
+static int adc128_remove(struct i2c_client *client)
+{
+	struct adc128_data *data = i2c_get_clientdata(client);
+
+	if (data->regulator)
+		regulator_disable(data->regulator);
+
+	return 0;
+}
+
+static const struct i2c_device_id adc128_id[] = {
+	{ "adc128d818", 0 },
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, adc128_id);
+
+static struct i2c_driver adc128_driver = {
+	.class		= I2C_CLASS_HWMON,
+	.driver = {
+		.name	= "adc128d818",
+	},
+	.probe		= adc128_probe,
+	.remove		= adc128_remove,
+	.id_table	= adc128_id,
+	.detect		= adc128_detect,
+	.address_list	= normal_i2c,
+};
+
+module_i2c_driver(adc128_driver);
+
+MODULE_AUTHOR("Guenter Roeck");
+MODULE_DESCRIPTION("Driver for ADC128D818");
+MODULE_LICENSE("GPL");
diff --git a/drivers/hwmon/hwmon.c b/drivers/hwmon/hwmon.c
index c3c471c..0979cd2 100644
--- a/drivers/hwmon/hwmon.c
+++ b/drivers/hwmon/hwmon.c
@@ -15,6 +15,7 @@
 #include <linux/module.h>
 #include <linux/device.h>
 #include <linux/err.h>
+#include <linux/slab.h>
 #include <linux/kdev_t.h>
 #include <linux/idr.h>
 #include <linux/hwmon.h>
@@ -25,35 +26,122 @@
 #define HWMON_ID_PREFIX "hwmon"
 #define HWMON_ID_FORMAT HWMON_ID_PREFIX "%d"
 
-static struct class *hwmon_class;
+struct hwmon_device {
+	const char *name;
+	struct device dev;
+};
+#define to_hwmon_device(d) container_of(d, struct hwmon_device, dev)
+
+static ssize_t
+show_name(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	return sprintf(buf, "%s\n", to_hwmon_device(dev)->name);
+}
+static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
+
+static struct attribute *hwmon_dev_attrs[] = {
+	&dev_attr_name.attr,
+	NULL
+};
+
+static umode_t hwmon_dev_name_is_visible(struct kobject *kobj,
+					 struct attribute *attr, int n)
+{
+	struct device *dev = container_of(kobj, struct device, kobj);
+
+	if (to_hwmon_device(dev)->name == NULL)
+		return 0;
+
+	return attr->mode;
+}
+
+static struct attribute_group hwmon_dev_attr_group = {
+	.attrs		= hwmon_dev_attrs,
+	.is_visible	= hwmon_dev_name_is_visible,
+};
+
+static const struct attribute_group *hwmon_dev_attr_groups[] = {
+	&hwmon_dev_attr_group,
+	NULL
+};
+
+static void hwmon_dev_release(struct device *dev)
+{
+	kfree(to_hwmon_device(dev));
+}
+
+static struct class hwmon_class = {
+	.name = "hwmon",
+	.owner = THIS_MODULE,
+	.dev_groups = hwmon_dev_attr_groups,
+	.dev_release = hwmon_dev_release,
+};
 
 static DEFINE_IDA(hwmon_ida);
 
 /**
- * hwmon_device_register - register w/ hwmon
- * @dev: the device to register
+ * hwmon_device_register_with_groups - register w/ hwmon
+ * @dev: the parent device
+ * @name: hwmon name attribute
+ * @drvdata: driver data to attach to created device
+ * @groups: List of attribute groups to create
  *
  * hwmon_device_unregister() must be called when the device is no
  * longer needed.
  *
  * Returns the pointer to the new device.
  */
-struct device *hwmon_device_register(struct device *dev)
+struct device *
+hwmon_device_register_with_groups(struct device *dev, const char *name,
+				  void *drvdata,
+				  const struct attribute_group **groups)
 {
-	struct device *hwdev;
-	int id;
+	struct hwmon_device *hwdev;
+	int err, id;
 
 	id = ida_simple_get(&hwmon_ida, 0, 0, GFP_KERNEL);
 	if (id < 0)
 		return ERR_PTR(id);
 
-	hwdev = device_create(hwmon_class, dev, MKDEV(0, 0), NULL,
-			      HWMON_ID_FORMAT, id);
+	hwdev = kzalloc(sizeof(*hwdev), GFP_KERNEL);
+	if (hwdev == NULL) {
+		err = -ENOMEM;
+		goto ida_remove;
+	}
 
-	if (IS_ERR(hwdev))
-		ida_simple_remove(&hwmon_ida, id);
+	hwdev->name = name;
+	hwdev->dev.class = &hwmon_class;
+	hwdev->dev.parent = dev;
+	hwdev->dev.groups = groups;
+	hwdev->dev.of_node = dev ? dev->of_node : NULL;
+	dev_set_drvdata(&hwdev->dev, drvdata);
+	dev_set_name(&hwdev->dev, HWMON_ID_FORMAT, id);
+	err = device_register(&hwdev->dev);
+	if (err)
+		goto free;
 
-	return hwdev;
+	return &hwdev->dev;
+
+free:
+	kfree(hwdev);
+ida_remove:
+	ida_simple_remove(&hwmon_ida, id);
+	return ERR_PTR(err);
+}
+EXPORT_SYMBOL_GPL(hwmon_device_register_with_groups);
+
+/**
+ * hwmon_device_register - register w/ hwmon
+ * @dev: the device to register
+ *
+ * hwmon_device_unregister() must be called when the device is no
+ * longer needed.
+ *
+ * Returns the pointer to the new device.
+ */
+struct device *hwmon_device_register(struct device *dev)
+{
+	return hwmon_device_register_with_groups(dev, NULL, NULL, NULL);
 }
 EXPORT_SYMBOL_GPL(hwmon_device_register);
 
@@ -75,6 +163,69 @@ void hwmon_device_unregister(struct device *dev)
 }
 EXPORT_SYMBOL_GPL(hwmon_device_unregister);
 
+static void devm_hwmon_release(struct device *dev, void *res)
+{
+	struct device *hwdev = *(struct device **)res;
+
+	hwmon_device_unregister(hwdev);
+}
+
+/**
+ * devm_hwmon_device_register_with_groups - register w/ hwmon
+ * @dev: the parent device
+ * @name: hwmon name attribute
+ * @drvdata: driver data to attach to created device
+ * @groups: List of attribute groups to create
+ *
+ * Returns the pointer to the new device. The new device is automatically
+ * unregistered with the parent device.
+ */
+struct device *
+devm_hwmon_device_register_with_groups(struct device *dev, const char *name,
+				       void *drvdata,
+				       const struct attribute_group **groups)
+{
+	struct device **ptr, *hwdev;
+
+	if (!dev)
+		return ERR_PTR(-EINVAL);
+
+	ptr = devres_alloc(devm_hwmon_release, sizeof(*ptr), GFP_KERNEL);
+	if (!ptr)
+		return ERR_PTR(-ENOMEM);
+
+	hwdev = hwmon_device_register_with_groups(dev, name, drvdata, groups);
+	if (IS_ERR(hwdev))
+		goto error;
+
+	*ptr = hwdev;
+	devres_add(dev, ptr);
+	return hwdev;
+
+error:
+	devres_free(ptr);
+	return hwdev;
+}
+EXPORT_SYMBOL_GPL(devm_hwmon_device_register_with_groups);
+
+static int devm_hwmon_match(struct device *dev, void *res, void *data)
+{
+	struct device **hwdev = res;
+
+	return *hwdev == data;
+}
+
+/**
+ * devm_hwmon_device_unregister - removes a previously registered hwmon device
+ *
+ * @dev: the parent device of the device to unregister
+ */
+void devm_hwmon_device_unregister(struct device *dev)
+{
+	WARN_ON(devres_release(dev, devm_hwmon_release, devm_hwmon_match, dev));
+}
+EXPORT_SYMBOL_GPL(devm_hwmon_device_unregister);
+
 static void __init hwmon_pci_quirks(void)
 {
 #if defined CONFIG_X86 && defined CONFIG_PCI
@@ -103,19 +254,21 @@ static void __init hwmon_pci_quirks(void)
 
 static int __init hwmon_init(void)
 {
+	int err;
+
 	hwmon_pci_quirks();
 
-	hwmon_class = class_create(THIS_MODULE, "hwmon");
-	if (IS_ERR(hwmon_class)) {
-		pr_err("couldn't create sysfs class\n");
-		return PTR_ERR(hwmon_class);
+	err = class_register(&hwmon_class);
+	if (err) {
+		pr_err("couldn't register hwmon sysfs class\n");
+		return err;
 	}
 	return 0;
 }
 
 static void __exit hwmon_exit(void)
 {
-	class_destroy(hwmon_class);
+	class_unregister(&hwmon_class);
 }
 
 subsys_initcall(hwmon_init);
diff --git a/drivers/hwmon/ina2xx.c b/drivers/hwmon/ina2xx.c
new file mode 100644
index 0000000..4965d35
--- /dev/null
+++ b/drivers/hwmon/ina2xx.c
@@ -0,0 +1,302 @@
+/*
+ * Driver for Texas Instruments INA219, INA226 power monitor chips
+ *
+ * INA219:
+ * Zero Drift Bi-Directional Current/Power Monitor with I2C Interface
+ * Datasheet: http://www.ti.com/product/ina219
+ *
+ * INA220:
+ * Bi-Directional Current/Power Monitor with I2C Interface
+ * Datasheet: http://www.ti.com/product/ina220
+ *
+ * INA226:
+ * Bi-Directional Current/Power Monitor with I2C Interface
+ * Datasheet: http://www.ti.com/product/ina226
+ *
+ * INA230:
+ * Bi-directional Current/Power Monitor with I2C Interface
+ * Datasheet: http://www.ti.com/product/ina230
+ *
+ * Copyright (C) 2012 Lothar Felten <l-felten@ti.com>
+ * Thanks to Jan Volkering
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/of.h>
+
+#include <linux/platform_data/ina2xx.h>
+
+/* common register definitions */
+#define INA2XX_CONFIG			0x00
+#define INA2XX_SHUNT_VOLTAGE		0x01 /* readonly */
+#define INA2XX_BUS_VOLTAGE		0x02 /* readonly */
+#define INA2XX_POWER			0x03 /* readonly */
+#define INA2XX_CURRENT			0x04 /* readonly */
+#define INA2XX_CALIBRATION		0x05
+
+/* INA226 register definitions */
+#define INA226_MASK_ENABLE		0x06
+#define INA226_ALERT_LIMIT		0x07
+#define INA226_DIE_ID			0xFF
+
+
+/* register count */
+#define INA219_REGISTERS		6
+#define INA226_REGISTERS		8
+
+#define INA2XX_MAX_REGISTERS		8
+
+/* settings - depend on use case */
+#define INA219_CONFIG_DEFAULT		0x399F	/* PGA=8 */
+#define INA226_CONFIG_DEFAULT		0x4527	/* averages=16 */
+
+/* worst case is 68.10 ms (~14.6Hz, ina219) */
+#define INA2XX_CONVERSION_RATE		15
+
+enum ina2xx_ids { ina219, ina226 };
+
+struct ina2xx_config {
+	u16 config_default;
+	int calibration_factor;
+	int registers;
+	int shunt_div;
+	int bus_voltage_shift;
+	int bus_voltage_lsb;	/* uV */
+	int power_lsb;		/* uW */
+};
+
+struct ina2xx_data {
+	struct i2c_client *client;
+	const struct ina2xx_config *config;
+
+	struct mutex update_lock;
+	bool valid;
+	unsigned long last_updated;
+
+	int kind;
+	u16 regs[INA2XX_MAX_REGISTERS];
+};
+
+static const struct ina2xx_config ina2xx_config[] = {
+	[ina219] = {
+		.config_default = INA219_CONFIG_DEFAULT,
+		.calibration_factor = 40960000,
+		.registers = INA219_REGISTERS,
+		.shunt_div = 100,
+		.bus_voltage_shift = 3,
+		.bus_voltage_lsb = 4000,
+		.power_lsb = 20000,
+	},
+	[ina226] = {
+		.config_default = INA226_CONFIG_DEFAULT,
+		.calibration_factor = 5120000,
+		.registers = INA226_REGISTERS,
+		.shunt_div = 400,
+		.bus_voltage_shift = 0,
+		.bus_voltage_lsb = 1250,
+		.power_lsb = 25000,
+	},
+};
+
+static struct ina2xx_data *ina2xx_update_device(struct device *dev)
+{
+	struct ina2xx_data *data = dev_get_drvdata(dev);
+	struct i2c_client *client = data->client;
+	struct ina2xx_data *ret = data;
+
+	mutex_lock(&data->update_lock);
+
+	if (time_after(jiffies, data->last_updated +
+		       HZ / INA2XX_CONVERSION_RATE) || !data->valid) {
+
+		int i;
+
+		dev_dbg(&client->dev, "Starting ina2xx update\n");
+
+		/* Read all registers */
+		for (i = 0; i < data->config->registers; i++) {
+			int rv = i2c_smbus_read_word_swapped(client, i);
+			if (rv < 0) {
+				ret = ERR_PTR(rv);
+				goto abort;
+			}
+			data->regs[i] = rv;
+		}
+		data->last_updated = jiffies;
+		data->valid = 1;
+	}
+abort:
+	mutex_unlock(&data->update_lock);
+	return ret;
+}
+
+static int ina2xx_get_value(struct ina2xx_data *data, u8 reg)
+{
+	int val;
+
+	switch (reg) {
+	case INA2XX_SHUNT_VOLTAGE:
+		/* signed register */
+		val = DIV_ROUND_CLOSEST((s16)data->regs[reg],
+					data->config->shunt_div);
+		break;
+	case INA2XX_BUS_VOLTAGE:
+		val = (data->regs[reg] >> data->config->bus_voltage_shift)
+		  * data->config->bus_voltage_lsb;
+		val = DIV_ROUND_CLOSEST(val, 1000);
+		break;
+	case INA2XX_POWER:
+		val = data->regs[reg] * data->config->power_lsb;
+		break;
+	case INA2XX_CURRENT:
+		/* signed register, LSB=1mA (selected), in mA */
+		val = (s16)data->regs[reg];
+		break;
+	default:
+		/* programmer goofed */
+		WARN_ON_ONCE(1);
+		val = 0;
+		break;
+	}
+
+	return val;
+}
+
+static ssize_t ina2xx_show_value(struct device *dev,
+				 struct device_attribute *da, char *buf)
+{
+	struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
+	struct ina2xx_data *data = ina2xx_update_device(dev);
+
+	if (IS_ERR(data))
+		return PTR_ERR(data);
+
+	return snprintf(buf, PAGE_SIZE, "%d\n",
+			ina2xx_get_value(data, attr->index));
+}
+
+/* shunt voltage */
+static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, \
+	ina2xx_show_value, NULL, INA2XX_SHUNT_VOLTAGE);
+
+/* bus voltage */
+static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, \
+	ina2xx_show_value, NULL, INA2XX_BUS_VOLTAGE);
+
+/* calculated current */
+static SENSOR_DEVICE_ATTR(curr1_input, S_IRUGO, \
+	ina2xx_show_value, NULL, INA2XX_CURRENT);
+
+/* calculated power */
+static SENSOR_DEVICE_ATTR(power1_input, S_IRUGO, \
+	ina2xx_show_value, NULL, INA2XX_POWER);
+
+/* pointers to created device attributes */
+static struct attribute *ina2xx_attrs[] = {
+	&sensor_dev_attr_in0_input.dev_attr.attr,
+	&sensor_dev_attr_in1_input.dev_attr.attr,
+	&sensor_dev_attr_curr1_input.dev_attr.attr,
+	&sensor_dev_attr_power1_input.dev_attr.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(ina2xx);
+
+static int ina2xx_probe(struct i2c_client *client,
+			const struct i2c_device_id *id)
+{
+	struct i2c_adapter *adapter = client->adapter;
+	struct ina2xx_platform_data *pdata;
+	struct device *dev = &client->dev;
+	struct ina2xx_data *data;
+	struct device *hwmon_dev;
+	long shunt = 10000; /* default shunt value 10mOhms */
+	u32 val;
+
+	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA))
+		return -ENODEV;
+
+	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	if (dev_get_platdata(dev)) {
+		pdata = dev_get_platdata(dev);
+		shunt = pdata->shunt_uohms;
+	} else if (!of_property_read_u32(dev->of_node,
+					 "shunt-resistor", &val)) {
+		shunt = val;
+	}
+
+	if (shunt <= 0)
+		return -ENODEV;
+
+	/* set the device type */
+	data->kind = id->driver_data;
+	data->config = &ina2xx_config[data->kind];
+
+	/* device configuration */
+	i2c_smbus_write_word_swapped(client, INA2XX_CONFIG,
+				     data->config->config_default);
+	/* set current LSB to 1mA, shunt is in uOhms */
+	/* (equation 13 in datasheet) */
+	i2c_smbus_write_word_swapped(client, INA2XX_CALIBRATION,
+				     data->config->calibration_factor / shunt);
+
+	data->client = client;
+	mutex_init(&data->update_lock);
+
+	hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name,
+							   data, ina2xx_groups);
+	if (IS_ERR(hwmon_dev))
+		return PTR_ERR(hwmon_dev);
+
+	dev_info(dev, "power monitor %s (Rshunt = %li uOhm)\n",
+		 id->name, shunt);
+
+	return 0;
+}
+
+static const struct i2c_device_id ina2xx_id[] = {
+	{ "ina219", ina219 },
+	{ "ina220", ina219 },
+	{ "ina226", ina226 },
+	{ "ina230", ina226 },
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, ina2xx_id);
+
+static struct i2c_driver ina2xx_driver = {
+	.driver = {
+		.name	= "ina2xx",
+	},
+	.probe		= ina2xx_probe,
+	.id_table	= ina2xx_id,
+};
+
+static int __init ina2xx_init(void)
+{
+	return i2c_add_driver(&ina2xx_driver);
+}
+
+static void __exit ina2xx_exit(void)
+{
+	i2c_del_driver(&ina2xx_driver);
+}
+
+MODULE_AUTHOR("Lothar Felten <l-felten@ti.com>");
+MODULE_DESCRIPTION("ina2xx driver");
+MODULE_LICENSE("GPL");
+
+module_init(ina2xx_init);
+module_exit(ina2xx_exit);
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 9494910..b36ba9a 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -915,4 +915,13 @@ config SCx200_ACB
 	  This support is also available as a module.  If so, the module
 	  will be called scx200_acb.
 
+config I2C_BRCMSTB
+       tristate "BRCM Settop I2C adapter"
+       depends on BRCMSTB
+       default m
+       help
+         If you say yes to this option, support will be included for the
+         I2C interface on the Broadcom Settop SoCs.
+
+         If you do not need BRCMSTB I2C inteface, say N.
 endmenu
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 2f05d7b..1c0b223 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_I2C_POWERMAC)	+= i2c-powermac.o
 obj-$(CONFIG_I2C_AT91)		+= i2c-at91.o
 obj-$(CONFIG_I2C_AU1550)	+= i2c-au1550.o
 obj-$(CONFIG_I2C_BLACKFIN_TWI)	+= i2c-bfin-twi.o
+obj-$(CONFIG_I2C_BRCMSTB)	+= i2c-brcmstb.o
 obj-$(CONFIG_I2C_CPM)		+= i2c-cpm.o
 obj-$(CONFIG_I2C_DAVINCI)	+= i2c-davinci.o
 obj-$(CONFIG_I2C_DESIGNWARE_CORE)	+= i2c-designware-core.o
diff --git a/drivers/i2c/busses/i2c-brcmstb.c b/drivers/i2c/busses/i2c-brcmstb.c
new file mode 100644
index 0000000..36da067
--- /dev/null
+++ b/drivers/i2c/busses/i2c-brcmstb.c
@@ -0,0 +1,709 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/slab.h>
+#include <linux/version.h>
+#include <linux/delay.h>
+#include <linux/brcmstb/brcmstb.h>
+#include <linux/i2c/i2c-brcmstb.h>
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 13, 0))
+	#define reinit_completion(x) INIT_COMPLETION(*(x))
+#endif
+
+#define N_DATA_REGS					8
+#define N_DATA_BYTES					(N_DATA_REGS * 4)
+
+/* BSC count register field definitions */
+#define BSC_CNT_REG1_MASK				0x0000003f
+#define BSC_CNT_REG1_SHIFT				0
+#define BSC_CNT_REG2_MASK				0x00000fc0
+#define BSC_CNT_REG2_SHIFT				6
+
+/* BSC CTL register field definitions */
+#define BSC_CTL_REG_DTF_MASK				0x00000003
+#define BSC_CTL_REG_SCL_SEL_MASK			0x00000030
+#define BSC_CTL_REG_SCL_SEL_SHIFT			4
+#define BSC_CTL_REG_INT_EN_MASK				0x00000040
+#define BSC_CTL_REG_INT_EN_SHIFT			6
+#define BSC_CTL_REG_DIV_CLK_MASK			0x00000080
+
+/* BSC_IIC_ENABLE r/w enable and interrupt field defintions */
+#define BSC_IIC_EN_RESTART_MASK				0x00000040
+#define BSC_IIC_EN_NOSTART_MASK				0x00000020
+#define BSC_IIC_EN_NOSTOP_MASK				0x00000010
+#define BSC_IIC_EN_NOACK_MASK				0x00000004
+#define BSC_IIC_EN_INTRP_MASK				0x00000002
+#define BSC_IIC_EN_ENABLE_MASK				0x00000001
+
+/* BSC_CTLHI control register field definitions */
+#define BSC_CTLHI_REG_INPUT_SWITCHING_LEVEL_MASK	0x00000080
+#define BSC_CTLHI_REG_DATAREG_SIZE_MASK			0x00000040
+#define BSC_CTLHI_REG_IGNORE_ACK_MASK			0x00000002
+#define BSC_CTLHI_REG_WAIT_DIS_MASK			0x00000001
+
+#define I2C_TIMEOUT					100 /* msecs */
+
+/* Condition mask used for non combined transfer */
+#define COND_RESTART		BSC_IIC_EN_RESTART_MASK
+#define COND_NOSTART		BSC_IIC_EN_NOSTART_MASK
+#define	COND_NOSTOP		BSC_IIC_EN_NOSTOP_MASK
+#define COND_START_STOP		(COND_RESTART | COND_NOSTART | COND_NOSTOP)
+
+/* BSC data transfer direction */
+#define DTF_WR_MASK		0x00000000
+#define DTF_RD_MASK		0x00000001
+/* BSC data transfer direction combined format */
+#define DTF_RD_WR_MASK		0x00000002
+#define DTF_WR_RD_MASK		0x00000003
+/* default bus speed  */
+#define DEFAULT_BUS_SPEEDHZ     375000
+
+struct bsc_regs {
+	u32	chip_address;
+	u32	data_in[N_DATA_REGS];
+	u32	cnt_reg;
+	u32	ctl_reg;
+	u32	iic_enable;
+	u32	data_out[N_DATA_REGS];
+	u32	ctlhi_reg;
+	u32	scl_param;
+};
+
+struct bsc_clk_param {
+	u32 hz;
+	u32 scl_mask;
+	u32 div_mask;
+};
+
+enum bsc_xfer_cmd {
+	CMD_WR,
+	CMD_RD,
+	CMD_WR_NOACK,
+	CMD_RD_NOACK,
+};
+
+static char const *cmd_string[] = {
+	[CMD_WR] = "WR",
+	[CMD_RD] = "RD",
+	[CMD_WR_NOACK] = "WR NOACK",
+	[CMD_RD_NOACK] = "RD NOACK",
+};
+
+enum bus_speeds {
+	SPD_375K,
+	SPD_390K,
+	SPD_187K,
+	SPD_200K,
+	SPD_93K,
+	SPD_97K,
+	SPD_46K,
+	SPD_50K
+};
+
+static const struct bsc_clk_param  bsc_clk[] = {
+	[SPD_375K] = {
+		.hz = 375000,
+		.scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,
+		.div_mask = 0
+	},
+	[SPD_390K] = {
+		.hz = 390000,
+		.scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,
+		.div_mask = 0
+	},
+	[SPD_187K] = {
+		.hz = 187500,
+		.scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,
+		.div_mask = 0
+	},
+	[SPD_200K] = {
+		.hz = 200000,
+		.scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,
+		.div_mask = 0
+	},
+	[SPD_93K]  = {
+		.hz = 93750,
+		.scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,
+		.div_mask = BSC_CTL_REG_DIV_CLK_MASK
+	},
+	[SPD_97K]  = {
+		.hz = 97500,
+		.scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,
+		.div_mask = BSC_CTL_REG_DIV_CLK_MASK
+	},
+	[SPD_46K]  = {
+		.hz = 46875,
+		.scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,
+		.div_mask = BSC_CTL_REG_DIV_CLK_MASK
+	},
+	[SPD_50K]  = {
+		.hz = 50000,
+		.scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,
+		.div_mask = BSC_CTL_REG_DIV_CLK_MASK
+	}
+};
+
+struct brcmstb_i2c_dev {
+	struct device *device;
+	void __iomem *base;
+	void __iomem *irq_base;
+	int irq;
+	struct bsc_regs *bsc_regmap;
+	struct i2c_adapter adapter;
+	struct completion done;
+	bool is_suspended;
+	u32 clk_freq_hz;
+};
+
+#define bsc_readl(_dev, reg)						\
+	__bsc_readl(_dev, offsetof(struct bsc_regs, reg))
+
+#define bsc_writel(_dev, val, reg)					\
+	__bsc_writel(_dev, val, offsetof(struct bsc_regs, reg))
+
+static inline u32 __bsc_readl(struct brcmstb_i2c_dev *dev, u32 reg)
+{
+	return __raw_readl(dev->base + reg);
+}
+
+static inline void __bsc_writel(struct brcmstb_i2c_dev *dev, u32 val,
+				  u32 reg)
+{
+	__raw_writel(val, dev->base + reg);
+}
+
+static void brcmstb_i2c_disable_irq(struct brcmstb_i2c_dev *dev)
+{
+	/* Disable BSC CTL interrupt line */
+	dev->bsc_regmap->ctl_reg &= ~BSC_CTL_REG_INT_EN_MASK;
+	barrier();
+	bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);
+}
+
+static void brcmstb_i2c_enable_irq(struct brcmstb_i2c_dev *dev)
+{
+	/* Enable BSC  CTL interrupt line */
+	dev->bsc_regmap->ctl_reg |= BSC_CTL_REG_INT_EN_MASK;
+	barrier();
+	bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);
+}
+
+static irqreturn_t brcmstb_i2c_isr(int irq, void *devid)
+{
+	struct brcmstb_i2c_dev *dev = devid;
+	u32 status_bsc_ctl = bsc_readl(dev, ctl_reg);
+	u32 status_iic_intrp = bsc_readl(dev, iic_enable);
+
+	dev_dbg(dev->device, "isr CTL_REG %x IIC_EN %x\n",
+		status_bsc_ctl, status_iic_intrp);
+
+	if (!(status_bsc_ctl & BSC_CTL_REG_INT_EN_MASK))
+		return IRQ_NONE;
+
+	brcmstb_i2c_disable_irq(dev);
+	complete_all(&dev->done);
+
+	dev_dbg(dev->device, "isr handled");
+	return IRQ_HANDLED;
+}
+
+/* Wait for device to be ready */
+static int brcmstb_i2c_wait_if_busy(struct brcmstb_i2c_dev *dev)
+{
+	unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT);
+	while ((bsc_readl(dev, iic_enable) & BSC_IIC_EN_INTRP_MASK)) {
+		if (time_after(jiffies, timeout)) {
+			dev_err(dev->device, "i2c device busy timeout\n");
+			return -ETIMEDOUT;
+		}
+	}
+	return 0;
+}
+
+/* i2c xfer completion function, handles both irq and polling mode
+ */
+static int brcmstb_i2c_waitforcompletion(struct brcmstb_i2c_dev *dev)
+{
+	int ret = 0;
+	unsigned long timeout = msecs_to_jiffies(I2C_TIMEOUT);
+
+	if (dev->irq >= 0) {
+		if (!wait_for_completion_timeout(&dev->done, timeout))
+			ret = -ETIMEDOUT;
+	} else {
+		/* we are in polling mode */
+		u32 bsc_intrp;
+		unsigned long time_left = jiffies + timeout;
+		do {
+			bsc_intrp = bsc_readl(dev, iic_enable) &
+				BSC_IIC_EN_INTRP_MASK;
+			if (time_after(jiffies, time_left)) {
+				ret = -ETIMEDOUT;
+				break;
+			}
+			udelay(100);
+		} while (!bsc_intrp);
+		brcmstb_i2c_disable_irq(dev);
+	}
+
+	return ret;
+}
+
+/* Set xfer START/STOP conditions for subsequent transfer */
+static void brcmstb_set_i2c_start_stop(struct brcmstb_i2c_dev *dev,
+				       u32 cond_flag)
+{
+	u32 regval = dev->bsc_regmap->iic_enable;
+	dev->bsc_regmap->iic_enable = (regval & ~COND_START_STOP) | cond_flag;
+}
+
+/* Send I2C request */
+static int brcmstb_send_i2c_cmd(struct brcmstb_i2c_dev *dev,
+				enum bsc_xfer_cmd cmd)
+{
+	int rc = 0, ignore_ack = 0;
+	struct bsc_regs *pi2creg = dev->bsc_regmap;
+	u32 ctl_reg;
+
+	/* Make sure the hardware is ready */
+	rc = brcmstb_i2c_wait_if_busy(dev);
+	if (rc < 0)
+		return rc;
+
+	dev_dbg(dev->device, "%s, %d\n", __func__, cmd);
+
+	/* see if the transaction needs check NACK conditions */
+	ignore_ack = (cmd == CMD_WR || cmd == CMD_RD) ? 0 : 1;
+	if (ignore_ack)
+		pi2creg->ctlhi_reg |= BSC_CTLHI_REG_IGNORE_ACK_MASK;
+	else
+		pi2creg->ctlhi_reg &= ~BSC_CTLHI_REG_IGNORE_ACK_MASK;
+	bsc_writel(dev, pi2creg->ctlhi_reg, ctlhi_reg);
+
+	if (dev->irq >= 0)
+		reinit_completion(&dev->done);
+
+	/* set data transfer direction */
+	ctl_reg = pi2creg->ctl_reg & ~BSC_CTL_REG_DTF_MASK;
+	if (cmd == CMD_WR || cmd == CMD_WR_NOACK)
+		pi2creg->ctl_reg = ctl_reg | DTF_WR_MASK;
+	else
+		pi2creg->ctl_reg = ctl_reg | DTF_RD_MASK;
+
+	/* enable BSC CTL interrupt line */
+	brcmstb_i2c_enable_irq(dev);
+
+	/* initiate transfer by setting iic_enable */
+	pi2creg->iic_enable |= BSC_IIC_EN_ENABLE_MASK;
+	bsc_writel(dev, pi2creg->iic_enable, iic_enable);
+
+	/* Wait for transaction to finish or timeout */
+	rc = brcmstb_i2c_waitforcompletion(dev);
+	if (rc) {
+		dev_err(dev->device, "intr timeout for cmd %s\n",
+			cmd_string[cmd]);
+		goto cmd_out;
+	}
+
+	if (!ignore_ack && bsc_readl(dev, iic_enable) & BSC_IIC_EN_NOACK_MASK) {
+		rc = -EREMOTEIO;
+		dev_dbg(dev->device, "controller received NOACK intr for %s\n",
+			cmd_string[cmd]);
+	}
+
+cmd_out:
+	bsc_writel(dev, 0, cnt_reg);
+	bsc_writel(dev, 0, iic_enable);
+
+	return rc;
+}
+
+static int brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev *dev,
+				     u8 *buf, unsigned int len,
+				     enum bsc_xfer_cmd cmd)
+{
+	int i, j, rc;
+
+	/* set the read/write length */
+	bsc_writel(dev, BSC_CNT_REG1_MASK & (len << BSC_CNT_REG1_SHIFT),
+		   cnt_reg);
+
+	/* Write data into data_in register */
+	if (cmd == CMD_WR || cmd == CMD_WR_NOACK) {
+		for (i = 0; i < len; i += 4) {
+			u32 word = 0;
+			for (j = 0; j < 4; j++) {
+				word >>= 8;
+				if ((i + j) < len)
+					word |= buf[i + j] << 24;
+			}
+			bsc_writel(dev, word, data_in[i >> 2]);
+		}
+	}
+
+	/* Initiate xfer */
+	rc = brcmstb_send_i2c_cmd(dev, cmd);
+
+	if (rc != 0)
+		return rc;
+
+	if (cmd == CMD_RD || cmd == CMD_RD_NOACK) {
+		for (i = 0; i < len; i += 4) {
+			u32 data = bsc_readl(dev, data_out[i >> 2]);
+			for (j = 0; j < 4 && (j + i) < len; j++) {
+				buf[i + j] = data & 0xff;
+				data >>= 8;
+			}
+		}
+	}
+
+	return 0;
+}
+
+/* Write a single byte of data to the i2c bus */
+static int brcmstb_i2c_write_data_byte(struct brcmstb_i2c_dev *dev,
+				       u8 *buf, unsigned int nak_expected)
+{
+	enum bsc_xfer_cmd cmd = nak_expected ? CMD_WR : CMD_WR_NOACK;
+
+	bsc_writel(dev, 1, cnt_reg);
+	bsc_writel(dev, *buf, data_in);
+
+	return brcmstb_send_i2c_cmd(dev, cmd);
+}
+
+/* Send i2c address */
+static int brcmstb_i2c_do_addr(struct brcmstb_i2c_dev *dev,
+			       struct i2c_msg *msg)
+{
+	unsigned char addr;
+
+	if (msg->flags & I2C_M_TEN) {
+
+		/* First byte is 11110XX0 where XX is upper 2 bits */
+		addr = 0xF0 | ((msg->addr & 0x300) >> 7);
+		bsc_writel(dev, addr, chip_address);
+
+		/* Second byte is the remaining 8 bits */
+		addr = msg->addr & 0xFF;
+		if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0)
+			return -EREMOTEIO;
+
+		if (msg->flags & I2C_M_RD) {
+			/* For read, send restart without stop condition */
+			brcmstb_set_i2c_start_stop(dev, COND_RESTART
+						   | COND_NOSTOP);
+			/* Then re-send the first byte with the read bit set */
+			addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01;
+			if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0)
+				return -EREMOTEIO;
+
+		}
+	} else {
+		addr = msg->addr << 1;
+		if (msg->flags & I2C_M_RD)
+			addr |= 1;
+
+		bsc_writel(dev, addr, chip_address);
+	}
+
+	return 0;
+}
+
+/* Master transfer function */
+static int brcmstb_i2c_xfer(struct i2c_adapter *adapter,
+			    struct i2c_msg msgs[], int num)
+{
+	struct brcmstb_i2c_dev *dev = i2c_get_adapdata(adapter);
+	struct i2c_msg *pmsg;
+	int rc = 0;
+	int i;
+	int bytes_to_xfer;
+	enum bsc_xfer_cmd cmd;
+	u8 *tmp_buf;
+	int len = 0;
+	int ignore_nack = 0;
+
+	if (dev->is_suspended)
+		return -EBUSY;
+
+	/* Loop through all messages */
+	for (i = 0; i < num; i++) {
+		pmsg = &msgs[i];
+		len = pmsg->len;
+		tmp_buf = pmsg->buf;
+		ignore_nack = pmsg->flags & I2C_M_IGNORE_NAK;
+
+		dev_dbg(dev->device,
+			"msg# %d/%d flg %x buf %x len %d\n", i,
+			num - 1, pmsg->flags,
+			pmsg->buf ? pmsg->buf[0] : '0', pmsg->len);
+
+		if (i < (num - 1) && (msgs[i + 1].flags & I2C_M_NOSTART))
+			brcmstb_set_i2c_start_stop(dev, ~(COND_START_STOP));
+		else
+			brcmstb_set_i2c_start_stop(dev,
+						   COND_RESTART | COND_NOSTOP);
+
+		/* Send slave address */
+		if (!(pmsg->flags & I2C_M_NOSTART)) {
+			rc = brcmstb_i2c_do_addr(dev, pmsg);
+			if (rc < 0) {
+				dev_dbg(dev->device,
+					"NACK for addr %2.2x msg#%d rc = %d\n",
+					pmsg->addr, i, rc);
+				goto out;
+			}
+		}
+
+		cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD : CMD_WR;
+
+		/* Perform data transfer */
+		while (len) {
+			bytes_to_xfer = min(len, N_DATA_BYTES);
+
+			if (ignore_nack || len <= N_DATA_BYTES)
+				cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD_NOACK
+					: CMD_WR_NOACK;
+
+			if (len <= N_DATA_BYTES && i == (num - 1))
+				brcmstb_set_i2c_start_stop(dev,
+							   ~(COND_START_STOP));
+
+			rc = brcmstb_i2c_xfer_bsc_data(dev, tmp_buf,
+						       bytes_to_xfer, cmd);
+			if (rc < 0) {
+				dev_dbg(dev->device, "%s failure",
+					cmd_string[cmd]);
+				goto out;
+			}
+
+			len -=  bytes_to_xfer;
+			tmp_buf += bytes_to_xfer;
+		}
+	}
+
+	rc = num;
+out:
+	return rc;
+
+}
+
+static u32 brcmstb_i2c_functionality(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
+		I2C_FUNC_PROTOCOL_MANGLING;
+}
+
+static const struct i2c_algorithm brcmstb_i2c_algo = {
+	.master_xfer = brcmstb_i2c_xfer,
+	.functionality = brcmstb_i2c_functionality,
+};
+
+static void brcmstb_i2c_set_bus_speed(struct brcmstb_i2c_dev *dev)
+{
+	int i = 0, num_speeds = ARRAY_SIZE(bsc_clk);
+	u32 clk_freq_hz = dev->clk_freq_hz;
+
+	for (i = 0; i < num_speeds; i++) {
+		if (bsc_clk[i].hz == clk_freq_hz) {
+			dev->bsc_regmap->ctl_reg &= ~(BSC_CTL_REG_SCL_SEL_MASK
+						| BSC_CTL_REG_DIV_CLK_MASK);
+			dev->bsc_regmap->ctl_reg |= (bsc_clk[i].scl_mask |
+						     bsc_clk[i].div_mask);
+			bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);
+			break;
+		}
+	}
+
+	if (i == num_speeds) {
+		i = (bsc_readl(dev, ctl_reg) & BSC_CTL_REG_SCL_SEL_MASK) >>
+			BSC_CTL_REG_SCL_SEL_SHIFT;
+		dev_warn(dev->device, "invalid input clock-frequency %dHz\n",
+			clk_freq_hz);
+		dev_warn(dev->device, "leaving current clock-frequency @ %dHz\n",
+			bsc_clk[i].hz);
+		dev->clk_freq_hz = bsc_clk[i].hz;
+	}
+}
+
+static void brcmstb_i2c_set_bsc_reg_defaults(struct brcmstb_i2c_dev *dev)
+{
+	/* 4 byte data register */
+	dev->bsc_regmap->ctlhi_reg = BSC_CTLHI_REG_DATAREG_SIZE_MASK;
+	bsc_writel(dev, dev->bsc_regmap->ctlhi_reg, ctlhi_reg);
+	/* set bus speed */
+	brcmstb_i2c_set_bus_speed(dev);
+}
+
+static int brcmstb_i2c_probe(struct platform_device *pdev)
+{
+	int rc = 0;
+	struct brcmstb_i2c_dev *dev;
+	struct i2c_adapter *adap;
+	struct resource *iomem;
+	const char *int_name;
+	struct brcmstb_i2c_platform_data *pdata = pdev->dev.platform_data;
+
+	/* Allocate memory for private data structure */
+	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
+	if (!dev)
+		return -ENOMEM;
+
+	dev->bsc_regmap = kzalloc(sizeof(struct bsc_regs), GFP_KERNEL);
+	if (!dev->bsc_regmap)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, dev);
+	dev->device = &pdev->dev;
+	init_completion(&dev->done);
+
+	/* Map hardware registers */
+	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	dev->base = devm_request_and_ioremap(&pdev->dev, iomem);
+	if (IS_ERR(dev->base)) {
+		rc = -ENOMEM;
+		goto probe_errorout;
+	}
+
+	rc = of_property_read_string(dev->device->of_node, "interrupt-names",
+				     &int_name);
+	if (rc < 0)
+		int_name = NULL;
+
+	/* Get the interrupt number */
+	dev->irq = platform_get_irq(pdev, 0);
+
+	/* disable the bsc interrupt line */
+	brcmstb_i2c_disable_irq(dev);
+
+	/* register the ISR handler */
+	rc = devm_request_irq(&pdev->dev, dev->irq, brcmstb_i2c_isr,
+			      IRQF_SHARED,
+			      int_name ? int_name : pdev->name,
+			      dev);
+
+	if (rc) {
+		dev_dbg(dev->device, "falling back to polling mode");
+		dev->irq = -1;
+	}
+
+	if (pdata && pdata->flags & (BRCMSTB_I2C_BUS_ENABLE_CMDLINE |
+				     BRCMSTB_I2C_BUS_ENABLE))
+		dev->clk_freq_hz = pdata->clk_rate;
+	else if (of_property_read_u32(dev->device->of_node,
+				      "clock-frequency", &dev->clk_freq_hz))
+		dev->clk_freq_hz = bsc_clk[0].hz;
+
+	/* Add the i2c adapter */
+	adap = &dev->adapter;
+	i2c_set_adapdata(adap, dev);
+	adap->owner = THIS_MODULE;
+	strlcpy(adap->name, "Broadcom STB ", sizeof(adap->name));
+
+	if (pdata && pdata->bus_name)
+		int_name = pdata->bus_name;
+
+	if (int_name)
+		strlcat(adap->name, int_name, sizeof(adap->name));
+
+	adap->algo = &brcmstb_i2c_algo;
+	adap->dev.parent = &pdev->dev;
+	adap->dev.of_node = pdev->dev.of_node;
+	rc = i2c_add_adapter(adap);
+	if (rc) {
+		dev_err(dev->device, "failed to add adapter\n");
+		goto probe_errorout;
+	}
+	brcmstb_i2c_set_bsc_reg_defaults(dev);
+	dev_info(dev->device, "%s@%dhz registered in %s mode\n",
+		 int_name ? int_name : " ", dev->clk_freq_hz,
+		 (dev->irq >= 0) ? "interrupt" : "polling");
+
+	return 0;
+
+probe_errorout:
+	kfree(dev->bsc_regmap);
+	return rc;
+}
+
+static int brcmstb_i2c_remove(struct platform_device *pdev)
+{
+	struct brcmstb_i2c_dev *dev = platform_get_drvdata(pdev);
+
+	kfree(dev->bsc_regmap);
+	i2c_del_adapter(&dev->adapter);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int brcmstb_i2c_suspend(struct device *dev)
+{
+	struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);
+
+	i2c_lock_adapter(&i2c_dev->adapter);
+	i2c_dev->is_suspended = true;
+	i2c_unlock_adapter(&i2c_dev->adapter);
+
+	return 0;
+}
+
+static int brcmstb_i2c_resume(struct device *dev)
+{
+	struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);
+
+	i2c_lock_adapter(&i2c_dev->adapter);
+	brcmstb_i2c_set_bsc_reg_defaults(i2c_dev);
+	i2c_dev->is_suspended = false;
+	i2c_unlock_adapter(&i2c_dev->adapter);
+
+	return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(brcmstb_i2c_pm, brcmstb_i2c_suspend,
+			 brcmstb_i2c_resume);
+
+static const struct of_device_id brcmstb_i2c_of_match[] = {
+	{.compatible = "brcm,brcmstb-i2c"},
+	{},
+};
+MODULE_DEVICE_TABLE(of, brcmstb_i2c_of_match);
+
+static struct platform_driver brcmstb_i2c_driver = {
+	.driver = {
+		   .name = "brcmstb-i2c",
+		   .owner = THIS_MODULE,
+		   .of_match_table = brcmstb_i2c_of_match,
+		   .pm = &brcmstb_i2c_pm,
+		   },
+	.probe = brcmstb_i2c_probe,
+	.remove = brcmstb_i2c_remove,
+};
+module_platform_driver(brcmstb_i2c_driver);
+
+MODULE_AUTHOR("Kamal Dasu <kdasu@broadcom.com>");
+MODULE_DESCRIPTION("Broadcom Settop I2C Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/common/tuners/Kconfig b/drivers/media/common/tuners/Kconfig
index 4a6d5ce..feddaf6 100644
--- a/drivers/media/common/tuners/Kconfig
+++ b/drivers/media/common/tuners/Kconfig
@@ -204,6 +204,13 @@ config MEDIA_TUNER_TDA18218
 	help
 	  NXP TDA18218 silicon tuner driver.
 
+config MEDIA_TUNER_TUA9001
+	tristate "Infineon OMNITUNE TUA 9001 silicon tuner"
+	depends on VIDEO_MEDIA && I2C
+	default m
+	help
+	  A driver for the silicon tuner OMNITUNE TUA 9001 from Infineon.
+
 config MEDIA_TUNER_TDA18212
 	tristate "NXP TDA18212 silicon tuner"
 	depends on VIDEO_MEDIA && I2C
diff --git a/drivers/media/common/tuners/Makefile b/drivers/media/common/tuners/Makefile
index f80407e..d134015 100644
--- a/drivers/media/common/tuners/Makefile
+++ b/drivers/media/common/tuners/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_MEDIA_TUNER_MXL5007T) += mxl5007t.o
 obj-$(CONFIG_MEDIA_TUNER_MC44S803) += mc44s803.o
 obj-$(CONFIG_MEDIA_TUNER_MAX2165) += max2165.o
 obj-$(CONFIG_MEDIA_TUNER_TDA18218) += tda18218.o
+obj-$(CONFIG_MEDIA_TUNER_TUA9001) += tua9001.o
 obj-$(CONFIG_MEDIA_TUNER_TDA18212) += tda18212.o
 
 ccflags-y += -I$(srctree)/drivers/media/dvb/dvb-core
diff --git a/drivers/media/common/tuners/mxl5007t.c b/drivers/media/common/tuners/mxl5007t.c
index 69e453e..7886a5a 100644
--- a/drivers/media/common/tuners/mxl5007t.c
+++ b/drivers/media/common/tuners/mxl5007t.c
@@ -374,7 +374,6 @@ static struct reg_pair_t *mxl5007t_calc_init_regs(struct mxl5007t_state *state,
 	mxl5007t_set_if_freq_bits(state, cfg->if_freq_hz, cfg->invert_if);
 	mxl5007t_set_xtal_freq_bits(state, cfg->xtal_freq_hz);
 
-	set_reg_bits(state->tab_init, 0x04, 0x01, cfg->loop_thru_enable);
 	set_reg_bits(state->tab_init, 0x03, 0x08, cfg->clk_out_enable << 3);
 	set_reg_bits(state->tab_init, 0x03, 0x07, cfg->clk_out_amp);
 
@@ -531,9 +530,12 @@ static int mxl5007t_tuner_init(struct mxl5007t_state *state,
 	struct reg_pair_t *init_regs;
 	int ret;
 
-	ret = mxl5007t_soft_reset(state);
-	if (mxl_fail(ret))
+	if (!state->config->no_reset) {
+		ret = mxl5007t_soft_reset(state);
+		if (mxl_fail(ret))
 		goto fail;
+	}
+
 
 	/* calculate initialization reg array */
 	init_regs = mxl5007t_calc_init_regs(state, mode);
@@ -887,7 +889,12 @@ struct dvb_frontend *mxl5007t_attach(struct dvb_frontend *fe,
 		if (fe->ops.i2c_gate_ctrl)
 			fe->ops.i2c_gate_ctrl(fe, 1);
 
-		ret = mxl5007t_get_chip_id(state);
+		if (!state->config->no_probe)
+			ret = mxl5007t_get_chip_id(state);
+
+		ret = mxl5007t_write_reg(state, 0x04,
+			state->config->loop_thru_enable);
+
 
 		if (fe->ops.i2c_gate_ctrl)
 			fe->ops.i2c_gate_ctrl(fe, 0);
diff --git a/drivers/media/common/tuners/mxl5007t.h b/drivers/media/common/tuners/mxl5007t.h
index aa3eea0..d99758f 100644
--- a/drivers/media/common/tuners/mxl5007t.h
+++ b/drivers/media/common/tuners/mxl5007t.h
@@ -73,8 +73,10 @@ struct mxl5007t_config {
 	enum mxl5007t_xtal_freq xtal_freq_hz;
 	enum mxl5007t_if_freq if_freq_hz;
 	unsigned int invert_if:1;
-	unsigned int loop_thru_enable:1;
+	unsigned int loop_thru_enable:3;
 	unsigned int clk_out_enable:1;
+	unsigned int no_probe:1;
+	unsigned int no_reset:1;
 };
 
 #if defined(CONFIG_MEDIA_TUNER_MXL5007T) || (defined(CONFIG_MEDIA_TUNER_MXL5007T_MODULE) && defined(MODULE))
diff --git a/drivers/media/common/tuners/tua9001.c b/drivers/media/common/tuners/tua9001.c
new file mode 100644
index 0000000..9db9362
--- /dev/null
+++ b/drivers/media/common/tuners/tua9001.c
@@ -0,0 +1,286 @@
+/*
+ * Infineon TUA 9001 silicon tuner driver
+ *
+ * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 2 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/slab.h>         /* for kzalloc/kfree */
+#include <linux/version.h>
+#include "tua9001.h"
+#include "tua9001_priv.h"
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0)) || ((defined V4L2_VERSION) && (V4L2_VERSION >= 197120))
+/* all DVB frontend drivers now work directly with the DVBv5
+ * structure. This warrants that all drivers will be
+ * getting/setting frontend parameters on a consistent way, in
+ * order to avoid copying data from/to the DVBv3 structs
+ * without need.
+ */
+#define V4L2_ONLY_DVB_V5
+#endif
+
+static int debug;
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "debug");
+
+/* write register */
+static int tua9001_writereg(struct tua9001_priv *priv, u8 reg, u16 val)
+{
+	u8 buf[3] = {reg, val >> 8, val & 0xff};
+	struct i2c_msg msg = { .addr = priv->cfg->i2c_address,
+		.flags = 0, .buf = buf, .len = 3 };
+
+	if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
+		err("I2C write failed, reg:%02x", reg);
+		return -EREMOTEIO;
+	}
+	return 0;
+}
+
+static int tua9001_release(struct dvb_frontend *fe)
+{
+	kfree(fe->tuner_priv);
+	fe->tuner_priv = NULL;
+	return 0;
+}
+
+static int tua9001_init(struct dvb_frontend *fe)
+{
+	struct tua9001_priv *priv = fe->tuner_priv;
+	int ret = 0;
+	u8 i;
+	struct regdesc data[] = {
+		{0x1e, 0x6512},
+		{0x25, 0xb888},
+		{0x39, 0x5460},
+		{0x3b, 0x00c0},
+		{0x3a, 0xf000},
+		{0x08, 0x0000},
+		{0x32, 0x0030},
+		{0x41, 0x703a},
+		{0x40, 0x1c78},
+		{0x2c, 0x1c00},
+		{0x36, 0xc013},
+		{0x37, 0x6f18},
+		{0x27, 0x0008},
+		{0x2a, 0x0001},
+		{0x34, 0x0a40},
+	};
+
+	if (fe->ops.i2c_gate_ctrl)
+		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c-gate */
+
+	for (i = 0; i < ARRAY_SIZE(data); i++) {
+		ret = tua9001_writereg(priv, data[i].reg, data[i].val);
+		if (ret)
+			break;
+	}
+
+	if (fe->ops.i2c_gate_ctrl)
+		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c-gate */
+
+	if (ret)
+		deb_info("%s: failed:%d\n", __func__, ret);
+
+	return ret;
+}
+
+#ifdef V4L2_ONLY_DVB_V5
+static int tua9001_set_params(struct dvb_frontend *fe)
+{
+	struct dtv_frontend_properties *params = &fe->dtv_property_cache;
+	struct tua9001_priv *priv = fe->tuner_priv;
+	int ret;
+	u16 val;
+	u32 freq;
+	u8 i;
+	struct regdesc data[2];
+
+	switch (params->bandwidth_hz) {
+#if 0
+	case 5000000:
+		val  = 0x3000;
+		break;
+#endif
+	case 6000000:
+		val  = 0x2000;
+		break;
+	case 7000000:
+		val  = 0x1000;
+		break;
+	case 8000000:
+	default:
+		val  = 0x0000;
+		break;
+	}
+
+	data[0].reg = 0x04;
+	data[0].val = val;
+
+freq = params->frequency;
+
+#define OFFSET 150000000
+freq = freq - OFFSET;
+freq  = freq/1000;
+freq  = 48 * freq;
+freq  = freq/1000;
+
+val = freq;
+
+	data[1].reg = 0x1f;
+	data[1].val = val;
+
+
+	deb_info("%s: freq:%d bw:%d freq tuner:%d val:%d\n", __func__,
+		params->frequency, params->bandwidth_hz, priv->frequency,
+		val);
+
+	if (fe->ops.i2c_gate_ctrl)
+		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c-gate */
+
+	for (i = 0; i < ARRAY_SIZE(data); i++) {
+		ret = tua9001_writereg(priv, data[i].reg, data[i].val);
+		if (ret)
+			break;
+	}
+
+	if (fe->ops.i2c_gate_ctrl)
+		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c-gate */
+
+	if (ret)
+		deb_info("%s: failed:%d\n", __func__, ret);
+
+	return ret;
+}
+#else
+static int tua9001_set_params(struct dvb_frontend *fe,
+	struct dvb_frontend_parameters *params)
+{
+	struct tua9001_priv *priv = fe->tuner_priv;
+	int ret;
+	u16 val;
+	u32 freq;
+	u8 i;
+	struct regdesc data[2];
+
+	switch (params->u.ofdm.bandwidth) {
+#if 0
+	case BANDWIDTH_5_MHZ:
+		val  = 0x3000;
+		break;
+#endif
+	case BANDWIDTH_6_MHZ:
+		val  = 0x2000;
+		break;
+	case BANDWIDTH_7_MHZ:
+		val  = 0x1000;
+		break;
+	case BANDWIDTH_8_MHZ:
+	default:
+		val  = 0x0000;
+		break;
+	}
+
+	data[0].reg = 0x04;
+	data[0].val = val;
+
+freq = params->frequency;
+
+#define OFFSET 150000000
+freq = freq - OFFSET;
+freq  = freq/1000;
+freq  = 48 * freq;
+freq  = freq/1000;
+
+val = freq;
+
+	data[1].reg = 0x1f;
+	data[1].val = val;
+
+
+	deb_info("%s: freq:%d bw:%d freq tuner:%d val:%d\n", __func__,
+		params->frequency, params->u.ofdm.bandwidth, priv->frequency,
+		val);
+
+	if (fe->ops.i2c_gate_ctrl)
+		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c-gate */
+
+	for (i = 0; i < ARRAY_SIZE(data); i++) {
+		ret = tua9001_writereg(priv, data[i].reg, data[i].val);
+		if (ret)
+			break;
+	}
+
+	if (fe->ops.i2c_gate_ctrl)
+		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c-gate */
+
+	if (ret)
+		deb_info("%s: failed:%d\n", __func__, ret);
+
+	return ret;
+}
+#endif
+
+static int tua9001_get_frequency(struct dvb_frontend *fe, u32 *frequency)
+{
+	struct tua9001_priv *priv = fe->tuner_priv;
+	*frequency = priv->frequency;
+	return 0;
+}
+
+static const struct dvb_tuner_ops tua9001_tuner_ops = {
+	.info = {
+		.name           = "Infineon TUA 9001",
+
+		.frequency_min  = 170000000,
+		.frequency_max  = 860000000,
+		.frequency_step = 0,
+	},
+
+	.release       = tua9001_release,
+	.init          = tua9001_init,
+
+	.set_params    = tua9001_set_params,
+
+	.get_frequency = tua9001_get_frequency,
+};
+
+struct dvb_frontend * tua9001_attach(struct dvb_frontend *fe,
+	struct i2c_adapter *i2c, struct tua9001_config *cfg)
+{
+	struct tua9001_priv *priv = NULL;
+
+	priv = kzalloc(sizeof(struct tua9001_priv), GFP_KERNEL);
+	if (priv == NULL)
+		return NULL;
+
+	priv->cfg = cfg;
+	priv->i2c = i2c;
+
+	info("Infineon TUA 9001 successfully attached.");
+
+	memcpy(&fe->ops.tuner_ops, &tua9001_tuner_ops,
+		sizeof(struct dvb_tuner_ops));
+
+	fe->tuner_priv = priv;
+	return fe;
+}
+EXPORT_SYMBOL(tua9001_attach);
+
+MODULE_DESCRIPTION("Infineon TUA 9001 silicon tuner driver");
+MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/common/tuners/tua9001.h b/drivers/media/common/tuners/tua9001.h
new file mode 100644
index 0000000..dd7298d
--- /dev/null
+++ b/drivers/media/common/tuners/tua9001.h
@@ -0,0 +1,46 @@
+/*
+ * Infineon TUA 9001 silicon tuner driver
+ *
+ * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 2 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef TUA9001_H
+#define TUA9001_H
+
+#include "dvb_frontend.h"
+
+struct tua9001_config {
+	u8 i2c_address;
+};
+
+#if defined(DETACHED_TERRATEC_MODULES) || \
+    defined(CONFIG_MEDIA_TUNER_TUA9001) || \
+	(defined(CONFIG_MEDIA_TUNER_TUA9001_MODULE) && defined(MODULE))
+extern struct dvb_frontend *tua9001_attach(struct dvb_frontend *fe,
+					struct i2c_adapter *i2c,
+					struct tua9001_config *cfg);
+#else
+static inline struct dvb_frontend *tua9001_attach(struct dvb_frontend *fe,
+						struct i2c_adapter *i2c,
+						struct tua9001_config *cfg)
+{
+	printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+	return NULL;
+}
+#endif
+
+#endif
diff --git a/drivers/media/common/tuners/tua9001_priv.h b/drivers/media/common/tuners/tua9001_priv.h
new file mode 100644
index 0000000..7588df1
--- /dev/null
+++ b/drivers/media/common/tuners/tua9001_priv.h
@@ -0,0 +1,53 @@
+/*
+ * Infineon TUA 9001 silicon tuner driver
+ *
+ * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 2 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef TUA9001_PRIV_H
+#define TUA9001_PRIV_H
+
+#define LOG_PREFIX "tua9001"
+
+#define dprintk(var, level, args...) \
+	do { \
+		if ((var & level)) \
+			printk(args); \
+	} while (0)
+
+#define deb_info(args...) dprintk(debug, 0x01, args)
+
+#undef err
+#define err(f, arg...)  printk(KERN_ERR     LOG_PREFIX": " f "\n" , ## arg)
+#undef info
+#define info(f, arg...) printk(KERN_INFO    LOG_PREFIX": " f "\n" , ## arg)
+#undef warn
+#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg)
+
+struct regdesc {
+	u8 reg;
+	u16 val;
+};
+
+struct tua9001_priv {
+	struct tua9001_config *cfg;
+	struct i2c_adapter *i2c;
+
+	u32 frequency;
+};
+
+#endif
diff --git a/drivers/media/dvb/dvb-core/dmxdev.c b/drivers/media/dvb/dvb-core/dmxdev.c
index 214df76..54c070e 100644
--- a/drivers/media/dvb/dvb-core/dmxdev.c
+++ b/drivers/media/dvb/dvb-core/dmxdev.c
@@ -82,7 +82,11 @@ static ssize_t dvb_dmxdev_buffer_read(struct dvb_ringbuffer *src,
 
 		ret = wait_event_interruptible(src->queue,
 					       !dvb_ringbuffer_empty(src) ||
-					       (src->error != 0));
+					       (src->error != 0) ||
+					       (src->do_wait != 1));
+		if (src->do_wait != 1)
+			ret = -EINTR;
+
 		if (ret < 0)
 			break;
 
@@ -103,6 +107,7 @@ static ssize_t dvb_dmxdev_buffer_read(struct dvb_ringbuffer *src,
 		buf += ret;
 	}
 
+
 	return (count - todo) ? (count - todo) : ret;
 }
 
@@ -958,6 +963,22 @@ dvb_demux_read(struct file *file, char __user *buf, size_t count,
 	return ret;
 }
 
+static int dvb_demux_lock_filter(struct dmxdev_filter *dmxdevfilter)
+{
+	int ret;
+
+	dmxdevfilter->buffer.do_wait = 0;
+
+	if (waitqueue_active(&dmxdevfilter->buffer.queue))
+		wake_up(&dmxdevfilter->buffer.queue);
+
+	ret = mutex_lock_interruptible(&dmxdevfilter->mutex);
+
+	dmxdevfilter->buffer.do_wait = 1;
+
+	return ret;
+}
+
 static int dvb_demux_do_ioctl(struct file *file,
 			      unsigned int cmd, void *parg)
 {
@@ -971,7 +992,7 @@ static int dvb_demux_do_ioctl(struct file *file,
 
 	switch (cmd) {
 	case DMX_START:
-		if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
+		if (dvb_demux_lock_filter(dmxdevfilter)) {
 			mutex_unlock(&dmxdev->mutex);
 			return -ERESTARTSYS;
 		}
@@ -983,7 +1004,7 @@ static int dvb_demux_do_ioctl(struct file *file,
 		break;
 
 	case DMX_STOP:
-		if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
+		if (dvb_demux_lock_filter(dmxdevfilter)) {
 			mutex_unlock(&dmxdev->mutex);
 			return -ERESTARTSYS;
 		}
@@ -992,7 +1013,7 @@ static int dvb_demux_do_ioctl(struct file *file,
 		break;
 
 	case DMX_SET_FILTER:
-		if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
+		if (dvb_demux_lock_filter(dmxdevfilter)) {
 			mutex_unlock(&dmxdev->mutex);
 			return -ERESTARTSYS;
 		}
@@ -1001,7 +1022,7 @@ static int dvb_demux_do_ioctl(struct file *file,
 		break;
 
 	case DMX_SET_PES_FILTER:
-		if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
+		if (dvb_demux_lock_filter(dmxdevfilter)) {
 			mutex_unlock(&dmxdev->mutex);
 			return -ERESTARTSYS;
 		}
@@ -1010,7 +1031,7 @@ static int dvb_demux_do_ioctl(struct file *file,
 		break;
 
 	case DMX_SET_BUFFER_SIZE:
-		if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
+		if (dvb_demux_lock_filter(dmxdevfilter)) {
 			mutex_unlock(&dmxdev->mutex);
 			return -ERESTARTSYS;
 		}
@@ -1054,7 +1075,7 @@ static int dvb_demux_do_ioctl(struct file *file,
 		break;
 
 	case DMX_ADD_PID:
-		if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
+		if (dvb_demux_lock_filter(dmxdevfilter)) {
 			ret = -ERESTARTSYS;
 			break;
 		}
@@ -1063,7 +1084,7 @@ static int dvb_demux_do_ioctl(struct file *file,
 		break;
 
 	case DMX_REMOVE_PID:
-		if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
+		if (dvb_demux_lock_filter(dmxdevfilter)) {
 			ret = -ERESTARTSYS;
 			break;
 		}
diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.c b/drivers/media/dvb/dvb-core/dvb_frontend.c
index cb888d8..53db26d 100644
--- a/drivers/media/dvb/dvb-core/dvb_frontend.c
+++ b/drivers/media/dvb/dvb-core/dvb_frontend.c
@@ -34,7 +34,6 @@
 #include <linux/wait.h>
 #include <linux/slab.h>
 #include <linux/poll.h>
-#include <linux/semaphore.h>
 #include <linux/module.h>
 #include <linux/list.h>
 #include <linux/freezer.h>
@@ -110,7 +109,7 @@ struct dvb_frontend_private {
 	struct dvb_device *dvbdev;
 	struct dvb_frontend_parameters parameters_out;
 	struct dvb_fe_events events;
-	struct semaphore sem;
+	struct mutex lock;
 	struct list_head list_head;
 	wait_queue_head_t wait_queue;
 	struct task_struct *thread;
@@ -250,12 +249,12 @@ static int dvb_frontend_get_event(struct dvb_frontend *fe,
 		if (flags & O_NONBLOCK)
 			return -EWOULDBLOCK;
 
-		up(&fepriv->sem);
+		mutex_unlock(&fepriv->lock);
 
 		ret = wait_event_interruptible (events->wait_queue,
 						events->eventw != events->eventr);
 
-		if (down_interruptible (&fepriv->sem))
+		if (mutex_lock_interruptible(&fepriv->lock))
 			return -ERESTARTSYS;
 
 		if (ret < 0)
@@ -607,19 +606,8 @@ static int dvb_frontend_thread(void *data)
 
 	dprintk("%s\n", __func__);
 
-	fepriv->check_wrapped = 0;
-	fepriv->quality = 0;
-	fepriv->delay = 3*HZ;
-	fepriv->status = 0;
-	fepriv->wakeup = 0;
-	fepriv->reinitialise = 0;
-
-	dvb_frontend_init(fe);
-
 	set_freezable();
 	while (1) {
-		up(&fepriv->sem);	    /* is locked when we enter the thread... */
-restart:
 		wait_event_interruptible_timeout(fepriv->wait_queue,
 			dvb_frontend_should_wakeup(fe) || kthread_should_stop()
 				|| freezing(current),
@@ -632,9 +620,9 @@ restart:
 		}
 
 		if (try_to_freeze())
-			goto restart;
+			continue;
 
-		if (down_interruptible(&fepriv->sem))
+		if (mutex_lock_interruptible(&fepriv->lock))
 			break;
 
 		if (fepriv->reinitialise) {
@@ -719,6 +707,8 @@ restart:
 		} else {
 			dvb_frontend_swzigzag(fe);
 		}
+
+		mutex_unlock(&fepriv->lock);
 	}
 
 	if (dvb_powerdown_on_sleep) {
@@ -760,7 +750,7 @@ static void dvb_frontend_stop(struct dvb_frontend *fe)
 
 	kthread_stop(fepriv->thread);
 
-	sema_init(&fepriv->sem, 1);
+	mutex_init(&fepriv->lock);
 	fepriv->state = FESTATE_IDLE;
 
 	/* paranoia check in case a signal arrived */
@@ -829,12 +819,22 @@ static int dvb_frontend_start(struct dvb_frontend *fe)
 
 	if (signal_pending(current))
 		return -EINTR;
-	if (down_interruptible (&fepriv->sem))
+	if (mutex_lock_interruptible(&fepriv->lock))
 		return -EINTR;
 
 	fepriv->state = FESTATE_IDLE;
 	fepriv->exit = DVB_FE_NO_EXIT;
 	fepriv->thread = NULL;
+
+	fepriv->check_wrapped = 0;
+	fepriv->quality = 0;
+	fepriv->delay = 3*HZ;
+	fepriv->status = 0;
+	fepriv->wakeup = 0;
+	fepriv->reinitialise = 0;
+
+	dvb_frontend_init(fe);
+
 	mb();
 
 	fe_thread = kthread_run(dvb_frontend_thread, fe,
@@ -842,11 +842,12 @@ static int dvb_frontend_start(struct dvb_frontend *fe)
 	if (IS_ERR(fe_thread)) {
 		ret = PTR_ERR(fe_thread);
 		printk("dvb_frontend_start: failed to start kthread (%d)\n", ret);
-		up(&fepriv->sem);
-		return ret;
+	} else {
+		fepriv->thread = fe_thread;
+		ret = 0;
 	}
-	fepriv->thread = fe_thread;
-	return 0;
+	mutex_unlock(&fepriv->lock);
+	return ret;
 }
 
 static void dvb_frontend_get_frequency_limits(struct dvb_frontend *fe,
@@ -1208,11 +1209,9 @@ static int dtv_property_legacy_params_sync(struct dvb_frontend *fe,
 /**
  * dtv_get_frontend - calls a callback for retrieving DTV parameters
  * @fe:		struct dvb_frontend pointer
- * @c:		struct dtv_frontend_properties pointer (DVBv5 cache)
  * @p_out	struct dvb_frontend_parameters pointer (DVBv3 FE struct)
  *
  * This routine calls either the DVBv3 or DVBv5 get_frontend call.
- * If c is not null, it will update the DVBv5 cache struct pointed by it.
  * If p_out is not null, it will update the DVBv3 params pointed by it.
  */
 static int dtv_get_frontend(struct dvb_frontend *fe,
@@ -1224,11 +1223,11 @@ static int dtv_get_frontend(struct dvb_frontend *fe,
 		r = fe->ops.get_frontend(fe);
 		if (unlikely(r < 0))
 			return r;
-		if (p_out)
-			dtv_property_legacy_params_sync(fe, p_out);
-		return 0;
 	}
 
+	if (p_out)
+		dtv_property_legacy_params_sync(fe, p_out);
+
 	/* As everything is in cache, get_frontend fops are always supported */
 	return 0;
 }
@@ -1734,7 +1733,7 @@ static int dvb_frontend_ioctl(struct file *file,
 	     cmd == FE_DISEQC_RECV_SLAVE_REPLY))
 		return -EPERM;
 
-	if (down_interruptible (&fepriv->sem))
+	if (mutex_lock_interruptible(&fepriv->lock))
 		return -ERESTARTSYS;
 
 	if ((cmd == FE_SET_PROPERTY) || (cmd == FE_GET_PROPERTY))
@@ -1744,7 +1743,7 @@ static int dvb_frontend_ioctl(struct file *file,
 		err = dvb_frontend_ioctl_legacy(file, cmd, parg);
 	}
 
-	up(&fepriv->sem);
+	mutex_unlock(&fepriv->lock);
 	return err;
 }
 
@@ -2395,7 +2394,7 @@ int dvb_register_frontend(struct dvb_adapter* dvb,
 	}
 	fepriv = fe->frontend_priv;
 
-	sema_init(&fepriv->sem, 1);
+	mutex_init(&fepriv->lock);
 	init_waitqueue_head (&fepriv->wait_queue);
 	init_waitqueue_head (&fepriv->events.wait_queue);
 	mutex_init(&fepriv->events.mtx);
diff --git a/drivers/media/dvb/dvb-core/dvb_ringbuffer.c b/drivers/media/dvb/dvb-core/dvb_ringbuffer.c
index a5712cd..6b96c83 100644
--- a/drivers/media/dvb/dvb-core/dvb_ringbuffer.c
+++ b/drivers/media/dvb/dvb-core/dvb_ringbuffer.c
@@ -45,6 +45,7 @@ void dvb_ringbuffer_init(struct dvb_ringbuffer *rbuf, void *data, size_t len)
 	rbuf->data=data;
 	rbuf->size=len;
 	rbuf->error=0;
+	rbuf->do_wait=1;
 
 	init_waitqueue_head(&rbuf->queue);
 
@@ -149,19 +150,23 @@ void dvb_ringbuffer_read(struct dvb_ringbuffer *rbuf, u8 *buf, size_t len)
 
 ssize_t dvb_ringbuffer_write(struct dvb_ringbuffer *rbuf, const u8 *buf, size_t len)
 {
+	ssize_t pwrite = rbuf->pwrite;
 	size_t todo = len;
 	size_t split;
 
-	split = (rbuf->pwrite + len > rbuf->size) ? rbuf->size - rbuf->pwrite : 0;
+	split = (pwrite + len > rbuf->size) ? rbuf->size - pwrite : 0;
 
 	if (split > 0) {
-		memcpy(rbuf->data+rbuf->pwrite, buf, split);
+		memcpy(rbuf->data+pwrite, buf, split);
 		buf += split;
 		todo -= split;
-		rbuf->pwrite = 0;
+		pwrite = 0;
 	}
-	memcpy(rbuf->data+rbuf->pwrite, buf, todo);
-	rbuf->pwrite = (rbuf->pwrite + todo) % rbuf->size;
+	memcpy(rbuf->data+pwrite, buf, todo);
+
+	smp_wmb();
+
+	rbuf->pwrite = (pwrite + todo) % rbuf->size;
 
 	return len;
 }
diff --git a/drivers/media/dvb/dvb-core/dvb_ringbuffer.h b/drivers/media/dvb/dvb-core/dvb_ringbuffer.h
index 41f04da..25a853b 100644
--- a/drivers/media/dvb/dvb-core/dvb_ringbuffer.h
+++ b/drivers/media/dvb/dvb-core/dvb_ringbuffer.h
@@ -38,6 +38,7 @@ struct dvb_ringbuffer {
 	int               error;
 
 	wait_queue_head_t queue;
+	int               do_wait;
 	spinlock_t        lock;
 };
 
diff --git a/drivers/media/dvb/dvb-core/dvbdev.c b/drivers/media/dvb/dvb-core/dvbdev.c
index 39eab73..acc666a 100644
--- a/drivers/media/dvb/dvb-core/dvbdev.c
+++ b/drivers/media/dvb/dvb-core/dvbdev.c
@@ -305,7 +305,7 @@ static int dvbdev_check_free_adapter_num(int num)
 
 static int dvbdev_get_free_adapter_num (void)
 {
-	int num = 0;
+	int num = 1;
 
 	while (num < DVB_MAX_ADAPTERS) {
 		if (dvbdev_check_free_adapter_num(num))
diff --git a/drivers/media/dvb/dvb-usb/Kconfig b/drivers/media/dvb/dvb-usb/Kconfig
index 63bf456..cef4dad 100644
--- a/drivers/media/dvb/dvb-usb/Kconfig
+++ b/drivers/media/dvb/dvb-usb/Kconfig
@@ -281,6 +281,7 @@ config DVB_USB_DW2102
 	select DVB_CX24116 if !DVB_FE_CUSTOMISE
 	select DVB_SI21XX if !DVB_FE_CUSTOMISE
 	select DVB_TDA10023 if !DVB_FE_CUSTOMISE
+	select DVB_TDA10021 if !DVB_FE_CUSTOMISE
 	select DVB_MT312 if !DVB_FE_CUSTOMISE
 	select DVB_ZL10039 if !DVB_FE_CUSTOMISE
 	select DVB_DS3000 if !DVB_FE_CUSTOMISE
@@ -339,6 +340,25 @@ config DVB_USB_AF9015
 	help
 	  Say Y here to support the Afatech AF9015 based DVB-T USB2.0 receiver
 
+config DVB_USB_A867
+	tristate "Avermedia A867 DVB receiver"
+	depends on DVB_USB
+	default m
+	help
+	  Choose Y or M here if you have an Avermedia A867 device
+	  To compile this driver as a module, choose M here
+
+config DVB_USB_AF9035
+	tristate "Afatech AF9035 DVB-T USB2.0 support"
+	depends on DVB_USB
+	default m
+	select DVB_AF9033
+	select MEDIA_TUNER_TUA9001  if !MEDIA_TUNER_CUSTOMISE
+	select MEDIA_TUNER_TDA18218 if !MEDIA_TUNER_CUSTOMISE
+	select MEDIA_TUNER_MXL5007T if !MEDIA_TUNER_CUSTOMISE
+	help
+	  Say Y here to support the Afatech AF9035 based DVB-T USB2.0 receiver
+
 config DVB_USB_CE6230
 	tristate "Intel CE6230 DVB-T USB2.0 support"
 	depends on DVB_USB
diff --git a/drivers/media/dvb/dvb-usb/Makefile b/drivers/media/dvb/dvb-usb/Makefile
index b76acb5..77e54a7 100644
--- a/drivers/media/dvb/dvb-usb/Makefile
+++ b/drivers/media/dvb/dvb-usb/Makefile
@@ -1,3 +1,4 @@
+
 dvb-usb-objs = dvb-usb-firmware.o dvb-usb-init.o dvb-usb-urb.o dvb-usb-i2c.o dvb-usb-dvb.o dvb-usb-remote.o usb-urb.o
 obj-$(CONFIG_DVB_USB) += dvb-usb.o
 
@@ -107,6 +108,15 @@ obj-$(CONFIG_DVB_USB_MXL111SF) += dvb-usb-mxl111sf.o
 obj-$(CONFIG_DVB_USB_MXL111SF) += mxl111sf-demod.o
 obj-$(CONFIG_DVB_USB_MXL111SF) += mxl111sf-tuner.o
 
+dvb-usb-af9035-objs = af9035.o
+obj-$(CONFIG_DVB_USB_AF9035) += dvb-usb-af9035.o
+
+dvb-usb-a867-objs := a867_af903x-core.o a867_af903x-devices.o a867_af903x-drv.o \
+	a867_af903x-fe.o a867_af903x-tuner.o a867_cmd.o a867_standard.o \
+	a867_demodulator.o a867_demodulatorextend.o a867_usb2impl.o \
+	a867_user.o a867_mxl5007t.o a867_Maxlinear_MXL5007.o a867_Afa_AF9007.o
+obj-$(CONFIG_DVB_USB_A867) += dvb-usb-a867.o
+
 dvb-usb-rtl28xxu-objs = rtl28xxu.o
 obj-$(CONFIG_DVB_USB_RTL28XXU) += dvb-usb-rtl28xxu.o
 
diff --git a/drivers/media/dvb/dvb-usb/a867_Afa_AF9007.c b/drivers/media/dvb/dvb-usb/a867_Afa_AF9007.c
new file mode 100644
index 0000000..0d65cf9
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_Afa_AF9007.c
@@ -0,0 +1,50 @@
+/*
+ * @(#)Afatech_AF9007_EXT.cpp
+ *
+ * Copyright 2005 Afatech, Inc. All rights reserved.
+ */
+
+//#include <stdio.h>
+#include "a867_type.h"
+#include "a867_error.h"
+#include "a867_user.h"
+#include "a867_register.h"
+#include "a867_standard.h"
+#include "a867_Afa_AF9007_Script.h"
+
+
+Dword AF9007_open (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip
+) {
+	return (Error_NO_ERROR);
+}
+
+Dword AF9007_close (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip
+) {
+	return (Error_NO_ERROR);
+}
+
+Dword AF9007_set (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+	IN  Word			bandwidth,
+	IN  Dword			frequency
+) {
+	return (Error_NO_ERROR);
+}
+
+TunerDescription tuner_AF9007 = {
+    AF9007_open,
+    AF9007_close,
+    AF9007_set,
+    AF9007_scripts,
+    AF9007_scriptSets,
+    0,                              /** tuner i2c address */
+    0,                              /** length of tuner register address */
+    36167000,                       /** tuner if */
+    True,                           /** spectrum inverse */
+    0xFF                            /** tuner id */
+};
diff --git a/drivers/media/dvb/dvb-usb/a867_Afa_AF9007.h b/drivers/media/dvb/dvb-usb/a867_Afa_AF9007.h
new file mode 100644
index 0000000..7f41742
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_Afa_AF9007.h
@@ -0,0 +1,39 @@
+/**
+ * @(#)Afatech_AF9007_EXT.h
+ *
+ * Copyright 2005 Afatech, Inc. All rights reserved.
+ */
+#ifndef __Afatech_AF9007_EXT_H__
+#define __Afatech_AF9007_EXT_H__
+
+
+extern TunerDescription tuner_AF9007;
+
+
+/**
+ *
+ */
+Dword AF9007_open (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip
+);
+
+/**
+ *
+ */
+Dword AF9007_close (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip
+);
+
+/**
+ *
+ */
+Dword AF9007_set (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+    IN  Word			bandwidth,
+    IN  Dword			frequency
+);
+#endif
+
diff --git a/drivers/media/dvb/dvb-usb/a867_Afa_AF9007_Script.h b/drivers/media/dvb/dvb-usb/a867_Afa_AF9007_Script.h
new file mode 100644
index 0000000..7da168b
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_Afa_AF9007_Script.h
@@ -0,0 +1,93 @@
+/** script version */
+
+#define AF9007_ADDRESS 0xC0
+#define AF9007_SCRIPTSETLENGTH	0x00000001
+
+
+Word AF9007_scriptSets[] = {
+	0x50
+};
+
+ValueSet AF9007_scripts[] = {
+ {0xF600, 0x5},
+ {0xF601, 0x8},
+ {0xF602, 0xb},
+ {0xF603, 0x0e},
+ {0xF604, 0x11},
+ {0xF605, 0x14},
+ {0xF606, 0x17},
+ {0xF607, 0x1f},
+ {0xF1E6, 0x01},
+ {0xF001, 0x00},
+ {0xF005, 0x01},
+ {0xF004, 0x00},
+ {0xF00A, 0x1B},
+ {0xF00B, 0x1C},
+ {0xF00C, 0x1B},
+ {0xF00D, 0x1C},
+ {0xF016, 0x10},
+ {0xF017, 0x04},
+ {0xF018, 0x05},
+ {0xF019, 0x04},
+ {0xF01A, 0x05},
+ {0xF021, 0x03},
+ {0xF022, 0x0A},
+ {0xF023, 0x0A},
+ {0xF000, 0x01},
+ {0xF047, 0x00},
+ {0xF007, 0x00},
+ {0xF12F, 0x00},
+ {0xF077, 0x00},
+ {0xF00A, 0x1A},
+ {0xF00B, 0x1B},
+ {0xF00C, 0x1A},
+ {0xF00D, 0x1B},
+ {0xF01F, 0x50},
+ {0xF020, 0x00},
+ {0xF029, 0x46},
+ {0xF02A, 0x00},
+ {0xF010, 0xDF},
+ {0xF011, 0x02},
+ {0xF00E, 0x44},
+ {0xF00F, 0x01},
+ {0xF014, 0xEB},
+ {0xF015, 0x02},
+ {0xF012, 0xF4},
+ {0xF013, 0x01},
+ {0x0066, 0x52},
+ {0xF01B, 0x26},
+ {0xF01C, 0x01},
+ {0xF01D, 0x12},
+ {0xF01E, 0x03},
+ {0xF025, 0xE8},
+ {0xF026, 0x00},
+ {0xF027, 0x5F},
+ {0xF028, 0x03},
+ {0x0044, 0xFF},
+ {0x0045, 0x03},
+ {0x0046, 0xFF},
+ {0x0047, 0x03},
+ {0x0048, 0xFF},
+ {0x0049, 0x03},
+ {0x004a, 0xFF},
+ {0x004b, 0x03},
+ {0x004c, 0xEB},
+ {0x004d, 0x02},
+ {0x0053, 0x68},
+ {0x0054, 0x03},
+ {0x0059, 0x12},
+ {0x005a, 0x03},
+ {0xF02B, 0x00},
+ {0xF02C, 0x01},
+ {0xF03B, 0x9A},
+ {0xF03C, 0x01},
+ {0xF03D, 0x5A},
+ {0xF03E, 0x01},
+ {0xF03F, 0x96},
+ {0xF040, 0x46},
+ {0xF031, 0x0},
+ {0x006b, 0x0A},
+ {0x006c, 0x14},
+ {0x006d, 0x08},
+};
+
diff --git a/drivers/media/dvb/dvb-usb/a867_Common.h b/drivers/media/dvb/dvb-usb/a867_Common.h
new file mode 100644
index 0000000..d6e6fe2
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_Common.h
@@ -0,0 +1,259 @@
+#pragma once
+
+typedef unsigned char		BYTE;						/** At least 1 Byte				*/
+typedef unsigned short		WORD;						/** At least 2 Bytes				*/
+typedef unsigned int		DWORD;						/** At least 4 Bytes				*/
+typedef void *				HANDLE;						/** Pointer to memory location	*/
+
+#define TUNER_REGS_NUM		104
+#define INITCTRL_NUM		38
+#ifdef _MXL_PRODUCTION
+#define CHCTRL_NUM			39
+#else
+#define CHCTRL_NUM			36
+#endif
+
+#define MXLCTRL_NUM			189
+
+#define MASTER_CONTROL_ADDR		9
+
+/** Enumeration of AGC Mode */
+typedef enum
+{
+	MXL_DUAL_AGC = 0 ,
+	MXL_SINGLE_AGC
+} AGC_Mode ;
+
+/**
+ * Enumeration of Master Control Register State
+ */
+typedef enum
+{
+	MC_LOAD_START = 1 ,
+	MC_POWER_DOWN ,
+	MC_SYNTH_RESET ,
+	MC_SEQ_OFF
+} Master_Control_State ;
+
+/**
+ * Enumeration of MXL5005 Tuner Mode
+ */
+typedef enum
+{
+	MXL_ANALOG_MODE = 0 ,
+	MXL_DIGITAL_MODE
+
+} Tuner_Mode ;
+
+/**
+ * Enumeration of MXL5005 Tuner IF Mode
+ */
+typedef enum
+{
+	MXL_ZERO_IF = 0 ,
+	MXL_LOW_IF
+
+} Tuner_IF_Mode ;
+
+/**
+ * Enumeration of MXL5005 Tuner Clock Out Mode
+ */
+typedef enum
+{
+	MXL_CLOCK_OUT_DISABLE = 0 ,
+	MXL_CLOCK_OUT_ENABLE
+} Tuner_Clock_Out ;
+
+/**
+ * Enumeration of MXL5005 Tuner Div Out Mode
+ */
+typedef enum
+{
+	MXL_DIV_OUT_1 = 0 ,
+	MXL_DIV_OUT_4
+
+} Tuner_Div_Out ;
+
+/**
+ * Enumeration of MXL5005 Tuner Pull-up Cap Select Mode
+ */
+typedef enum
+{
+	MXL_CAP_SEL_DISABLE = 0 ,
+	MXL_CAP_SEL_ENABLE
+
+} Tuner_Cap_Select ;
+
+/**
+ * Enumeration of MXL5005 Tuner RSSI Mode
+ */
+typedef enum
+{
+	MXL_RSSI_DISABLE = 0 ,
+	MXL_RSSI_ENABLE
+
+} Tuner_RSSI ;
+
+/**
+ * Enumeration of MXL5005 Tuner Modulation Type
+ */
+typedef enum
+{
+	MXL_DEFAULT_MODULATION = 0 ,
+	MXL_DVBT,
+	MXL_ATSC,
+	MXL_QAM
+
+} Tuner_Modu_Type ;
+
+/**
+ * MXL5005 Tuner Register Struct
+ */
+typedef struct _TunerReg_struct
+{
+	WORD 	Reg_Num ;							/** Tuner Register Address */
+	WORD	Reg_Val ;							/** Current sofware programmed value waiting to be writen */
+} TunerReg_struct ;
+
+/** 
+ * MXL5005 Tuner Control Struct
+ */
+typedef struct _TunerControl_struct {
+/*	char 	Name[40] ; */						/** Control Name */
+	WORD	Ctrl_Num ;							/** Control Number */
+	WORD	size ;								/** Number of bits to represent Value */
+	WORD 	addr[25] ;							/** Array of Tuner Register Address for each bit position */
+	WORD 	bit[25] ;							/** Array of bit position in Register Address for each bit position */
+	WORD 	val[25] ;							/** Binary representation of Value */
+} TunerControl_struct ;
+
+/**
+ * MXL5005 Tuner Struct
+ */
+typedef struct _Tuner_struct
+{
+	BYTE			Mode ;				/** 0: Analog Mode ; 1: Digital Mode */
+	BYTE			IF_Mode ;			/** for Analog Mode, 0: zero IF; 1: low IF */
+	DWORD			Chan_Bandwidth ;	/** filter  channel bandwidth (6, 7, 8) */
+	DWORD			IF_OUT ;			/** Desired IF Out Frequency */
+	WORD			IF_OUT_LOAD ;		/** IF Out Load Resistor (200/300 Ohms) */
+	DWORD			RF_IN ;				/** RF Input Frequency */
+	DWORD			Fxtal ;				/** XTAL Frequency */
+	BYTE			AGC_Mode ;			/** AGC Mode 0: Dual AGC; 1: Single AGC */
+	WORD			TOP ;				/** Value: take over point */
+	BYTE			CLOCK_OUT ;			/** 0: turn off clock out; 1: turn on clock out */
+	BYTE			DIV_OUT ;			/** 4MHz or 16MHz */
+	BYTE			CAPSELECT ;			/** 0: disable On-Chip pulling cap; 1: enable */
+	BYTE			EN_RSSI ;			/** 0: disable RSSI; 1: enable RSSI */
+	BYTE			Mod_Type ;			/** Modulation Type; */
+										/** 0 - Default;		1 - DVB-T */
+
+	/** Calculated Settings */
+	DWORD			RF_LO ;				/** Synth RF LO Frequency */
+	DWORD			IF_LO ;				/** Synth IF LO Frequency */
+	DWORD			TG_LO ;				/** Synth TG_LO Frequency */
+
+	/** Pointers to ControlName Arrays */
+	WORD					Init_Ctrl_Num ;					/** Number of INIT Control Names */
+	TunerControl_struct		Init_Ctrl[INITCTRL_NUM] ;		/** INIT Control Names Array Pointer */
+	WORD					CH_Ctrl_Num ;					/** Number of CH Control Names */
+	TunerControl_struct		CH_Ctrl[CHCTRL_NUM] ;			/** CH Control Name Array Pointer */
+	WORD					MXL_Ctrl_Num ;					/** Number of MXL Control Names */
+	TunerControl_struct		MXL_Ctrl[MXLCTRL_NUM] ;			/** MXL Control Name Array Pointer */
+
+	/** Pointer to Tuner Register Array */
+	WORD					TunerRegs_Num ;		/** Number of Tuner Registers */
+	TunerReg_struct			TunerRegs[TUNER_REGS_NUM] ;			/** Tuner Register Array Pointer */
+} Tuner_struct ;
+
+
+
+typedef enum
+{
+	/**
+	 * Initialization Control Names
+	 */
+	DN_IQTN_AMP_CUT = 1 ,       /** 1  */
+	BB_MODE ,                   /** 2  */
+	BB_BUF ,                    /** 3  */
+	BB_BUF_OA ,	                /** 4  */
+	BB_ALPF_BANDSELECT ,        /** 5  */
+	BB_IQSWAP ,                 /** 6  */
+	BB_DLPF_BANDSEL ,           /** 7  */
+	RFSYN_CHP_GAIN ,            /** 8  */
+	RFSYN_EN_CHP_HIGAIN ,       /** 9  */
+	AGC_IF ,                    /** 10 */
+	AGC_RF ,                    /** 11 */
+	IF_DIVVAL ,                 /** 12 */
+	IF_VCO_BIAS ,               /** 13 */
+	CHCAL_INT_MOD_IF ,          /** 14 */
+	CHCAL_FRAC_MOD_IF ,         /** 15 */
+	DRV_RES_SEL ,               /** 16 */
+	I_DRIVER ,                  /** 17 */
+	EN_AAF ,                    /** 18 */
+	EN_3P ,                     /** 19 */
+	EN_AUX_3P ,                 /** 20 */
+	SEL_AAF_BAND ,              /** 21 */
+	SEQ_ENCLK16_CLK_OUT ,       /** 22 */
+	SEQ_SEL4_16B ,              /** 23 */
+	XTAL_CAPSELECT ,            /** 24 */
+	IF_SEL_DBL ,                /** 25 */
+	RFSYN_R_DIV ,               /** 26 */
+	SEQ_EXTSYNTHCALIF ,         /** 27 */
+	SEQ_EXTDCCAL ,              /** 28 */
+	AGC_EN_RSSI ,               /** 29 */
+	RFA_ENCLKRFAGC ,            /** 30 */
+	RFA_RSSI_REFH ,             /** 31 */
+	RFA_RSSI_REF ,              /** 32 */
+	RFA_RSSI_REFL ,             /** 33 */
+	RFA_FLR ,                   /** 34 */
+	RFA_CEIL ,                  /** 35 */
+	SEQ_EXTIQFSMPULSE ,         /** 36 */
+	OVERRIDE_1 ,                /** 37 */
+	BB_INITSTATE_DLPF_TUNE,     /** 38 */
+	/**
+	 * Channel Change Control Names
+	 */
+	DN_POLY = 51 ,              /** 51 */
+	DN_RFGAIN ,                 /** 52 */
+	DN_CAP_RFLPF ,              /** 53 */
+	DN_EN_VHFUHFBAR ,           /** 54 */
+	DN_GAIN_ADJUST ,            /** 55 */
+	DN_IQTNBUF_AMP ,            /** 56 */
+	DN_IQTNGNBFBIAS_BST ,       /** 57 */
+	RFSYN_EN_OUTMUX ,           /** 58 */
+	RFSYN_SEL_VCO_OUT ,         /** 59 */
+	RFSYN_SEL_VCO_HI ,          /** 60 */
+	RFSYN_SEL_DIVM ,            /** 61 */
+	RFSYN_RF_DIV_BIAS ,         /** 62 */
+	DN_SEL_FREQ ,               /** 63 */
+	RFSYN_VCO_BIAS ,            /** 64 */
+	CHCAL_INT_MOD_RF ,          /** 65 */
+	CHCAL_FRAC_MOD_RF ,         /** 66 */
+	RFSYN_LPF_R ,               /** 67 */
+	CHCAL_EN_INT_RF ,           /** 68 */
+	TG_LO_DIVVAL ,              /** 69 */
+	TG_LO_SELVAL ,              /** 70 */
+	TG_DIV_VAL ,                /** 71 */
+	TG_VCO_BIAS ,               /** 72 */
+	SEQ_EXTPOWERUP ,            /** 73 */
+	OVERRIDE_2 ,                /** 74 */
+	OVERRIDE_3 ,                /** 75 */
+	OVERRIDE_4 ,                /** 76 */
+	SEQ_FSM_PULSE ,             /** 77 */
+	GPIO_4B,                    /** 78 */
+	GPIO_3B,                    /** 79 */
+	GPIO_4,                     /** 80 */
+	GPIO_3,                     /** 81 */
+	GPIO_1B,                    /** 82 */
+	DAC_A_ENABLE ,              /** 83 */
+	DAC_B_ENABLE ,              /** 84 */
+	DAC_DIN_A ,	                /** 85 */
+	DAC_DIN_B ,                 /** 86 */
+#ifdef _MXL_PRODUCTION
+	RFSYN_EN_DIV,				/** 87 */
+	RFSYN_DIVM,					/** 88 */
+	DN_BYPASS_AGC_I2C			/** 89 */
+#endif
+
+} MXL5005_ControlName ;
diff --git a/drivers/media/dvb/dvb-usb/a867_Maxlinear_MXL5007.c b/drivers/media/dvb/dvb-usb/a867_Maxlinear_MXL5007.c
new file mode 100644
index 0000000..1bc1d33
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_Maxlinear_MXL5007.c
@@ -0,0 +1,203 @@
+/**
+ * Maxlinear_MXL5007.cpp
+ *
+ * Interface btw Afa9035 and Mxl5007T
+ */
+
+#include "a867_Maxlinear_MXL5007.h"
+#include "a867_Maxlinear_MXL5007_Script.h"
+#include "a867_mxl5007t.h"
+#include "a867_af903x.h"
+
+//m100 todo MxL5007_TunerConfigS MxL5007_TunerConfig = 0;
+struct mxl5007t_config MxL5007_TunerConfig;
+
+Dword MXL5007_WriteI2C(
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+	IN  Byte*			pAddress,
+	IN  Byte*			pData,
+	IN  Dword			count
+) {
+    Dword error = Error_NO_ERROR;                /* Status to be returned        */
+    Byte buffer[25];
+    //Byte numberOfRegisters = 9;
+    Byte i;
+
+/** single write */
+    for (i = 0; i < count; i++) {
+        buffer[0] = *(pAddress + i);
+        buffer[1] = *(pData + i);
+        //buffer[2] = 0xFE;  /** Latch CMD request by MXL5005 Confidential Datasheet */
+		error = Standard_writeTunerRegisters (demodulator, chip, buffer[0], 1, &buffer[1]);
+		if (error){
+			deb_data("MXL5007_WriteI2C failed");
+			goto exit;
+		}
+    }
+exit:
+    return (error);
+}
+
+
+UINT32 MxL_I2C_Write(UINT8 DeviceAddr, void* pArray, UINT32 ByteCount, struct mxl5007t_config* myTuner)
+{
+    Dword error = Error_NO_ERROR;                /* Status to be returned */
+    // Byte buffer[25];
+    // Byte i;
+	Byte* pData;
+	pData = (Byte*)pArray;
+    
+/** single write */
+    //buffer[2] = 0xFE;  /** Latch CMD request by MXL5005 Confidential Datasheet */
+	if (ByteCount == 1) 
+		error = Standard_writeTunerRegisters ((myTuner->demodulator), (myTuner->chip), pData[0], 0, NULL);
+	else if (ByteCount > 1)
+		error = Standard_writeTunerRegisters ((myTuner->demodulator), (myTuner->chip), pData[0], ByteCount - 1, &pData[1]);
+	else
+	{	
+		error = Error_INVALID_DATA_LENGTH;
+		deb_data("MxL_I2C_Write:: ByteCount = 0"); 
+	}
+
+	if (error){
+		deb_data("MxL_I2C_Write failed");
+		goto exit;
+	}
+
+exit:
+    return (error);
+}
+
+
+UINT32 MxL_I2C_Read(UINT8 DeviceAddr, UINT8 Addr, UINT8* mData, struct mxl5007t_config* myTuner)
+{
+	Dword error = Error_NO_ERROR;
+
+	error = Standard_writeTunerRegisters(myTuner->demodulator, myTuner->chip, 0xFB, 1, &Addr);
+	error = Standard_readTunerRegisters (myTuner->demodulator, myTuner->chip, 0xffff, 1, mData);
+
+	return (error);
+}
+
+void MxL_Delay(UINT32 mSec)
+{
+	User_delay(NULL, mSec);
+}
+
+
+Dword MXL5007_open (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip
+) {
+	Ganymede* ganymede;
+	ganymede = (Ganymede*) demodulator;
+	MxL5007_TunerConfig.demodulator = demodulator;
+	MxL5007_TunerConfig.chip = chip;
+
+	//MxL5007_TunerConfig.I2C_Addr = MxL_I2C_ADDR_096;	// 7-bit address
+	MxL5007_TunerConfig.I2C_Addr = ganymede->tunerDescription->tunerAddress; //Get from tunerDescription
+
+	//MxL5007_TunerConfig.IF_Freq = MxL_IF_4_57_MHZ;
+	switch( ganymede->tunerDescription->ifFrequency ) {
+	case 4000000:
+		MxL5007_TunerConfig.if_freq_hz = MxL_IF_4_MHZ; break;
+	case 4500000:
+		MxL5007_TunerConfig.if_freq_hz = MxL_IF_4_5_MHZ; break;
+	case 4570000:
+		MxL5007_TunerConfig.if_freq_hz = MxL_IF_4_57_MHZ; break;
+	case 5000000:
+		MxL5007_TunerConfig.if_freq_hz = MxL_IF_5_MHZ; break;
+	case 5380000:
+		MxL5007_TunerConfig.if_freq_hz = MxL_IF_5_38_MHZ; break;
+	case 6000000:
+		MxL5007_TunerConfig.if_freq_hz = MxL_IF_6_MHZ; break;
+	case 6280000:
+		MxL5007_TunerConfig.if_freq_hz = MxL_IF_6_28_MHZ; break;
+	case 9191500:
+		MxL5007_TunerConfig.if_freq_hz = MxL_IF_9_1915_MHZ; break;
+	case 35250000:
+		MxL5007_TunerConfig.if_freq_hz = MxL_IF_35_25_MHZ; break;
+	case 36150000:
+		MxL5007_TunerConfig.if_freq_hz = MxL_IF_36_15_MHZ; break;
+	case 44000000:
+		MxL5007_TunerConfig.if_freq_hz = MxL_IF_44_MHZ; break;
+	default:
+		MxL5007_TunerConfig.if_freq_hz = MxL_IF_4_57_MHZ;
+		printk("IF unsupported\n");
+		break;
+	}
+
+	//MxL5007_TunerConfig.IF_Spectrum = MxL_NORMAL_IF;
+	if (ganymede->tunerDescription->inversion == True)
+		MxL5007_TunerConfig.invert_if = 1; //Get from tunerDescription
+	else
+		MxL5007_TunerConfig.invert_if = 0;
+
+	MxL5007_TunerConfig.Mode = MxL_MODE_DVBT;
+	MxL5007_TunerConfig.if_diff_out_level = -8; //Setting for Cable mode only
+	MxL5007_TunerConfig.xtal_freq_hz = MxL_XTAL_24_MHZ;	//24Mhz
+	MxL5007_TunerConfig.clk_out_enable = 0;
+	MxL5007_TunerConfig.clk_out_amp = MxL_CLKOUT_AMP_0_94V;
+	
+	if( ganymede->booted )
+	a867_mxl5007t_attach(&MxL5007_TunerConfig);
+	deb_data("MxL5007 Open");
+
+    return (Error_NO_ERROR);
+}
+
+
+Dword MXL5007_close (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip
+) {
+	a867_mxl5007t_release(MxL5007_TunerConfig.state);
+    return (Error_NO_ERROR);
+}
+
+
+Dword MXL5007_set (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+	IN  Word			bandwidth,
+	IN  Dword			frequency
+) {
+	// Dword status = 0;       
+
+	deb_data("MxL5007 Set");
+	if(	a867_mxl5007t_set_params(MxL5007_TunerConfig.state, (enum mxl5007t_bw_mhz) (bandwidth / 1000), frequency * 1000) ) {
+		deb_data("MxL5007 Set fail");
+		return (Error_WRITE_TUNER_FAIL);
+	}
+
+	return (Error_NO_ERROR);
+}
+
+
+Dword SwPowerCtrlMXL5007(
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+	IN  Byte			control			/** 0 for power down mode, 1 for normal operation mode */
+)
+{
+    return (Error_NO_ERROR);
+}
+
+
+
+TunerDescription tuner_MXL5007 = {
+    MXL5007_open,
+    MXL5007_close,
+    MXL5007_set,
+    MXL5007_scripts,
+    MXL5007_scriptSets,
+    0xC0,                           /** tuner i2c address */
+    1,                              /** length of tuner register address */
+    4570000,				                /* ref. mxl5007t.h/mxl5007t_if_freq */
+    False                           /** spectrum inverse */
+};
+
+
+
+
diff --git a/drivers/media/dvb/dvb-usb/a867_Maxlinear_MXL5007.h b/drivers/media/dvb/dvb-usb/a867_Maxlinear_MXL5007.h
new file mode 100644
index 0000000..46f6fb5
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_Maxlinear_MXL5007.h
@@ -0,0 +1,60 @@
+/**
+ * Maxlinear_MXL5007.h
+ *
+ * Interface btw Afa9035 and Mxl5007T
+ */
+
+#ifndef __Maxlinear_MXL5007_H__
+#define __Maxlinear_MXL5007_H__
+
+#include "a867_type.h"
+#include "a867_error.h"
+#include "a867_user.h"
+#include "a867_register.h"
+#include "a867_standard.h"
+#include "a867_mxl5007t.h"
+#include "a867_Common.h"	//for Tuner_struct
+typedef unsigned int	UINT32;
+typedef unsigned char	UINT8;
+
+extern TunerDescription tuner_MXL5007;
+
+/**
+ *
+ */
+
+UINT32 MxL_I2C_Write(UINT8 DeviceAddr, void* pArray, UINT32 ByteCount, struct mxl5007t_config* myTuner);
+UINT32 MxL_I2C_Read(UINT8 DeviceAddr, UINT8 Addr, UINT8* mData, struct mxl5007t_config* myTuner);
+void MxL_Delay(UINT32 mSec);
+
+
+/**
+ *
+ */
+Dword MXL5007_open (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip
+);
+
+
+/**
+ *
+ */
+Dword MXL5007_close (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip
+);
+
+
+/**
+ *
+ */
+Dword MXL5007_set (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+    IN  Word			bandwidth,
+    IN  Dword			frequency
+);
+
+#endif //__Maxlinear_MXL5007_H__
+
diff --git a/drivers/media/dvb/dvb-usb/a867_Maxlinear_MXL5007_Script.h b/drivers/media/dvb/dvb-usb/a867_Maxlinear_MXL5007_Script.h
new file mode 100644
index 0000000..c5daff6
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_Maxlinear_MXL5007_Script.h
@@ -0,0 +1,64 @@
+/** script version */
+
+#define MXL5007_ADDRESS 0xC0
+#define MXL5007_SCRIPTSETLENGTH	0x00000001
+
+
+Word MXL5007_scriptSets[] = {
+	0x34
+};
+
+ValueSet MXL5007_scripts[] = {
+ {0x0046, 0x04},
+ {0x0057, 0x00},
+ {0x0058, 0x01},
+ {0x005f, 0x00},
+ {0x0060, 0x00},
+ {0x006e, 0x01},
+ {0x0071, 0x0A},
+ {0x0072, 0x02},
+ {0x0074, 0x01},
+ {0x0079, 0x01},
+ {0x0093, 0x00},
+ {0x0094, 0x00},
+ {0x0095, 0x00},
+ {0x0096, 0x00},
+ {0x009b, 0x20},
+ {0x009c, 0x66},
+ {0x00b3, 0x01},
+ {0x00c3, 0x0},
+ {0x00c4, 0x0},
+ {0x00c7, 0x59},
+ {0xF007, 0x00},
+ {0xF00A, 0x1B},
+ {0xF00B, 0x1B},
+ {0xF00C, 0x1B},
+ {0xF00D, 0x1B},
+ {0xF00E, 0xFF},
+ {0xF00F, 0x01},
+ {0xF010, 0x00},
+ {0xF011, 0x02},
+ {0xF012, 0xFF},
+ {0xF013, 0x01},
+ {0xF014, 0x00},
+ {0xF015, 0x02},
+ {0xF01B, 0xEF},
+ {0xF01C, 0x01},
+ {0xF01D, 0x0f},
+ {0xF01E, 0x02},
+ {0xF01F, 0x6e},
+ {0xF020, 0x00},
+ {0xF025, 0xDE},
+ {0xF026, 0x00},
+ {0xF027, 0x0A},
+ {0xF028, 0x03},
+ {0xF029, 0x6e},
+ {0xF02A, 0x00},
+ {0xF047, 0x00},
+ {0xF054, 0x0},
+ {0xF055, 0x0},
+ {0xF077, 0x02},
+ {0xF14F, 0x02},
+ {0xF1E6, 0x00},
+ {0xF163, 0x02},
+};
diff --git a/drivers/media/dvb/dvb-usb/a867_af903x-core.c b/drivers/media/dvb/dvb-usb/a867_af903x-core.c
new file mode 100644
index 0000000..98bb7f5
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_af903x-core.c
@@ -0,0 +1,253 @@
+#include "a867_af903x.h"
+#include "a867_aver_version.h"
+
+DEVICE_CONTEXT DC;
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)
+DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
+#endif
+
+static int map_gpio_by_id(const struct usb_device_id *id, PDEVICE_CONTEXT pdc)
+{
+	if( id->idProduct == 0xa333 ) {
+		pdc->Map.I2C_SLAVE_ADDR = 0x3A;
+		pdc->Map.RF_SW_HOST = 0; //chip0
+		pdc->Map.GPIO_UHF_en = p_reg_top_gpioh2_en;
+		pdc->Map.GPIO_UHF_on = p_reg_top_gpioh2_on;
+		pdc->Map.GPIO_UHF_o  = p_reg_top_gpioh2_o;
+		pdc->Map.GPIO_VHF_en = p_reg_top_gpioh3_en;
+		pdc->Map.GPIO_VHF_on = p_reg_top_gpioh3_on;
+		pdc->Map.GPIO_VHF_o  = p_reg_top_gpioh3_o;
+		pdc->Map.GPIO_WP_en	= p_reg_top_gpioh7_en;
+		pdc->Map.GPIO_WP_on	= p_reg_top_gpioh7_on;
+		pdc->Map.GPIO_WP_o   = p_reg_top_gpioh7_o;
+		pdc->Map.GPIO_OSC_en = p_reg_top_gpioh6_en;
+		pdc->Map.GPIO_OSC_on = p_reg_top_gpioh6_on;
+		pdc->Map.GPIO_OSC_o  = p_reg_top_gpioh6_o;
+		pdc->Map.GPIO_TUR1_en = p_reg_top_gpioh11_en;
+		pdc->Map.GPIO_TUR1_on = p_reg_top_gpioh11_on;
+		pdc->Map.GPIO_TUR1_o  = p_reg_top_gpioh11_o;
+		pdc->Map.GPIO_TUR2_en = p_reg_top_gpioh12_en;
+		pdc->Map.GPIO_TUR2_on = p_reg_top_gpioh12_on;
+		pdc->Map.GPIO_TUR2_o  = p_reg_top_gpioh12_o;
+		pdc->Map.GPIO_DPWR_en = 0xF000;
+		pdc->Map.GPIO_DPWR_on = 0xF000;
+		pdc->Map.GPIO_DPWR_o	 = 0xF000;
+		pdc->Map.GPIO_DRST_en = 0xF000;
+		pdc->Map.GPIO_DRST_on = 0xF000;
+		pdc->Map.GPIO_DRST_o  = 0xF000;
+		pdc->Map.GPIO_STR_en  = p_reg_top_gpioh8_en;
+		pdc->Map.GPIO_STR_on  = p_reg_top_gpioh8_on;
+		pdc->Map.GPIO_STR_o   = p_reg_top_gpioh8_o;
+		pdc->Map.GPIO_STR_i   = r_reg_top_gpioh8_i;
+	}
+	else if( id->idProduct == 0xa825 ) {
+		pdc->Map.I2C_SLAVE_ADDR = 0x3E;
+		//pdc->Map.RF_SW_HOST = 1; //chip1
+		pdc->Map.RF_SW_HOST = 0; //chip0
+		pdc->Map.GPIO_UHF_en = p_reg_top_gpioh3_en;
+		pdc->Map.GPIO_UHF_on = p_reg_top_gpioh3_on;
+		pdc->Map.GPIO_UHF_o  = p_reg_top_gpioh3_o;
+		pdc->Map.GPIO_VHF_en = p_reg_top_gpioh2_en;	//When UHF, this pin low
+		pdc->Map.GPIO_VHF_on = p_reg_top_gpioh2_on;
+		pdc->Map.GPIO_VHF_o  = p_reg_top_gpioh2_o;
+		pdc->Map.GPIO_WP_en	= p_reg_top_gpioh7_en;
+		pdc->Map.GPIO_WP_on	= p_reg_top_gpioh7_on;
+		pdc->Map.GPIO_WP_o   = p_reg_top_gpioh7_o;
+		pdc->Map.GPIO_OSC_en = p_reg_top_gpioh6_en;	//Use GPIO6 for HW test
+		pdc->Map.GPIO_OSC_on = p_reg_top_gpioh6_on;	//GPIO8 can't use.
+		pdc->Map.GPIO_OSC_o  = p_reg_top_gpioh6_o;
+		pdc->Map.GPIO_TUR1_en = p_reg_top_gpioh11_en;	//Use GPIO11,12 will cause hostB fail.
+		pdc->Map.GPIO_TUR1_on = p_reg_top_gpioh11_on;
+		pdc->Map.GPIO_TUR1_o  = p_reg_top_gpioh11_o;
+		pdc->Map.GPIO_TUR2_en = p_reg_top_gpioh12_en;
+		pdc->Map.GPIO_TUR2_on = p_reg_top_gpioh12_on;
+		pdc->Map.GPIO_TUR2_o  = p_reg_top_gpioh12_o;
+		pdc->Map.GPIO_DPWR_en = p_reg_top_gpioh2_en;
+		pdc->Map.GPIO_DPWR_on = p_reg_top_gpioh2_on;
+		pdc->Map.GPIO_DPWR_o	 = p_reg_top_gpioh2_o;
+		pdc->Map.GPIO_DRST_en = p_reg_top_gpioh5_en;
+		pdc->Map.GPIO_DRST_on = p_reg_top_gpioh5_on;
+		pdc->Map.GPIO_DRST_o  = p_reg_top_gpioh5_o;
+		pdc->Map.GPIO_STR_en  = 0xF000;
+		pdc->Map.GPIO_STR_on  = 0xF000;
+		pdc->Map.GPIO_STR_o   = 0xF000;
+		pdc->Map.GPIO_STR_i   = 0xF000;
+	}
+	else if(id->idProduct == 0xa337 
+		|| id->idProduct == 0xF337
+		|| id->idProduct == 0x0337 
+		|| id->idProduct == 0xa867 
+		|| id->idProduct == 0x0867 
+		|| id->idProduct == 0x1867) {
+		deb_data("GPIO Mapping : A867\n");
+		pdc->Map.I2C_SLAVE_ADDR = 0x3A;
+		pdc->Map.RF_SW_HOST = 0; //chip1
+		pdc->Map.GPIO_UHF_en = 0xF000;
+		pdc->Map.GPIO_UHF_on = 0xF000;
+		pdc->Map.GPIO_UHF_o  = 0xF000;
+		pdc->Map.GPIO_VHF_en = 0xF000;
+		pdc->Map.GPIO_VHF_on = 0xF000;
+		pdc->Map.GPIO_VHF_o  = 0xF000;
+		pdc->Map.GPIO_WP_en	= p_reg_top_gpioh7_en;
+		pdc->Map.GPIO_WP_on	= p_reg_top_gpioh7_on;
+		pdc->Map.GPIO_WP_o   = p_reg_top_gpioh7_o;
+		pdc->Map.GPIO_OSC_en = 0xF000;
+		pdc->Map.GPIO_OSC_on = 0xF000;
+		pdc->Map.GPIO_OSC_o  = 0xF000;
+		pdc->Map.GPIO_TUR1_en = p_reg_top_gpioh6_en;	//Use GPIO11,12 will cause hostB fail.
+		pdc->Map.GPIO_TUR1_on = p_reg_top_gpioh6_on;
+		pdc->Map.GPIO_TUR1_o  = p_reg_top_gpioh6_o;
+		pdc->Map.GPIO_TUR2_en = p_reg_top_gpioh11_en;
+		pdc->Map.GPIO_TUR2_on = p_reg_top_gpioh11_on;
+		pdc->Map.GPIO_TUR2_o  = p_reg_top_gpioh11_o;
+		pdc->Map.GPIO_DPWR_en = 0xF000;
+		pdc->Map.GPIO_DPWR_on = 0xF000;
+		pdc->Map.GPIO_DPWR_o	= 0xF000;
+		pdc->Map.GPIO_DRST_en = 0xF000;
+		pdc->Map.GPIO_DRST_on = 0xF000;
+		pdc->Map.GPIO_DRST_o  = 0xF000;
+		pdc->Map.GPIO_STR_en  = 0xF000;
+		pdc->Map.GPIO_STR_on  = 0xF000;
+		pdc->Map.GPIO_STR_o   = 0xF000;
+		pdc->Map.GPIO_STR_i   = 0xF000;
+		pdc->Map.GPIO_LED_en = p_reg_top_gpioh3_en;	
+		pdc->Map.GPIO_LED_on = p_reg_top_gpioh3_on;
+		pdc->Map.GPIO_LED_o  = p_reg_top_gpioh3_o;
+	}
+	else {
+		pdc->Map.I2C_SLAVE_ADDR = 0x3E;
+		pdc->Map.RF_SW_HOST = 1; //chip1
+		pdc->Map.GPIO_UHF_en = p_reg_top_gpioh3_en;
+		pdc->Map.GPIO_UHF_on = p_reg_top_gpioh3_on;
+		pdc->Map.GPIO_UHF_o  = p_reg_top_gpioh3_o;
+		pdc->Map.GPIO_VHF_en = p_reg_top_gpioh2_en;	//When UHF, this pin low
+		pdc->Map.GPIO_VHF_on = p_reg_top_gpioh2_on;
+		pdc->Map.GPIO_VHF_o  = p_reg_top_gpioh2_o;
+		pdc->Map.GPIO_WP_en	= p_reg_top_gpioh7_en;
+		pdc->Map.GPIO_WP_on	= p_reg_top_gpioh7_on;
+		pdc->Map.GPIO_WP_o   = p_reg_top_gpioh7_o;
+		pdc->Map.GPIO_OSC_en = p_reg_top_gpioh6_en;	//Use GPIO6 for HW test
+		pdc->Map.GPIO_OSC_on = p_reg_top_gpioh6_on;	//GPIO8 can't use.
+		pdc->Map.GPIO_OSC_o  = p_reg_top_gpioh6_o;
+		pdc->Map.GPIO_TUR1_en = p_reg_top_gpioh11_en;	//Use GPIO11,12 will cause hostB fail.
+		pdc->Map.GPIO_TUR1_on = p_reg_top_gpioh11_on;
+		pdc->Map.GPIO_TUR1_o  = p_reg_top_gpioh11_o;
+		pdc->Map.GPIO_TUR2_en = p_reg_top_gpioh12_en;
+		pdc->Map.GPIO_TUR2_on = p_reg_top_gpioh12_on;
+		pdc->Map.GPIO_TUR2_o  = p_reg_top_gpioh12_o;
+		pdc->Map.GPIO_DPWR_en = p_reg_top_gpioh2_en;
+		pdc->Map.GPIO_DPWR_on = p_reg_top_gpioh2_on;
+		pdc->Map.GPIO_DPWR_o	 = p_reg_top_gpioh2_o;
+		pdc->Map.GPIO_DRST_en = p_reg_top_gpioh5_en;
+		pdc->Map.GPIO_DRST_on = p_reg_top_gpioh5_on;
+		pdc->Map.GPIO_DRST_o  = p_reg_top_gpioh5_o;
+		pdc->Map.GPIO_STR_en  = 0xF000;
+		pdc->Map.GPIO_STR_on  = 0xF000;
+		pdc->Map.GPIO_STR_o   = 0xF000;
+		pdc->Map.GPIO_STR_i   = 0xF000;
+	}
+	return 0;
+}
+
+static int af903x_probe(struct usb_interface *intf,
+		const struct usb_device_id *id)
+{
+	int retval = -ENOMEM;
+	int i;
+
+	// init GPIO mappings based on device
+	map_gpio_by_id(id, &DC);
+
+	deb_data("===af903x usb device pluged in!! ===\n");
+	retval = Device_init(interface_to_usbdev(intf),intf,&DC, true);
+	if (retval){
+                if(retval) deb_data("Device_init Fail: 0x%08x\n", retval);
+        }
+	
+	for (i = 0; i < af903x_device_count; i++) {
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)
+		if (dvb_usb_device_init(intf, &af903x_properties[i], THIS_MODULE, NULL, adapter_nr) == 0)
+#else
+		if (dvb_usb_device_init(intf, &af903x_properties[i], THIS_MODULE, NULL) == 0)
+#endif
+			{deb_data("dvb_usb_device_init success!!\n");return 0;}
+	}
+
+	return -ENOMEM;
+}
+
+static int af903x_suspend(struct usb_interface *intf, pm_message_t message)
+{
+	int error;
+	deb_data("Enter %s Function, message=0x%ux\n",__FUNCTION__, message.event);
+	error = DL_ApCtrl(0);
+	if (error) deb_data("DL_ApCtrl error : 0x%x\n", error);
+
+// If selective suspend is not supported, this must be a S3/S4 suspend,
+// in which case we choose to reboot AF903x so it can work after resuming on EeePC.
+#if !defined(CONFIG_USB_SUSPEND)
+	DL_Reboot();	
+#endif
+
+	return 0;
+}
+
+static int af903x_resume(struct usb_interface *intf)
+{
+	int retval = -ENOMEM;
+	deb_data("Enter %s Function\n",__FUNCTION__);
+	
+	retval = DL_ApCtrl(1);
+	if (retval) deb_data("DL_ApCtrl error : 0x%x\n", retval);
+
+	retval = Device_init(interface_to_usbdev(intf),intf,&DC, false);
+        if (retval){
+                if(retval) deb_data("Device_init Fail: 0x%08x\n", retval);
+        }
+
+        return 0;
+}
+
+static struct usb_driver af903x_driver = {
+#if LINUX_VERSION_CODE <=  KERNEL_VERSION(2,6,15)
+	.owner = THIS_MODULE,
+#endif
+	.name       = "dvb-usb-a867",
+	.probe      = af903x_probe,
+	.disconnect = dvb_usb_device_exit,
+	.id_table   = af903x_usb_id_table,
+	.suspend    = af903x_suspend,
+	.resume     = af903x_resume,
+#if LINUX_VERSION_CODE >  KERNEL_VERSION(2,6,22)
+	.reset_resume = af903x_resume,
+#endif
+	.supports_autosuspend = 1,
+};
+
+static int __init af903x_module_init(void)
+{
+	int result;
+
+	printk("AVerMedia A867 driver module V%s loaded.\n - By ItalySat.it", DRIVER_VER);
+
+	if ((result = usb_register(&af903x_driver))) {
+		err("usb_register failed. Error number %d",result);
+		return result;
+	}
+	return 0;
+}
+
+static void __exit af903x_module_exit(void)
+{
+	usb_deregister(&af903x_driver);
+	printk("AVerMedia A867 driver module V%s unloaded.\n - By ItalySat.it", DRIVER_VER);
+}
+
+module_init (af903x_module_init);
+module_exit (af903x_module_exit);
+
+MODULE_AUTHOR("MPD Linux Team");
+MODULE_DESCRIPTION("AVerMedia A867 - By ItalySat.it");
+MODULE_VERSION(DRIVER_VER);
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/dvb-usb/a867_af903x-devices.c b/drivers/media/dvb/dvb-usb/a867_af903x-devices.c
new file mode 100644
index 0000000..76fc41b
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_af903x-devices.c
@@ -0,0 +1,278 @@
+#include "a867_af903x.h"
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0)) || ((defined V4L2_VERSION) && (V4L2_VERSION >= 196608))
+#define V4L2_REFACTORED_MFE_CODE
+#endif
+
+int dvb_usb_af903x_hwpid = 1; // enable hw pid filter 
+module_param_named(hwpid,dvb_usb_af903x_hwpid, int, 0644); 
+MODULE_PARM_DESC(debug, "set hw pid filter.(disable=0, enable=1)" DVB_USB_DEBUG_STATUS);
+
+//static u16 gSWPIDTable[32];
+static int gTblUsed = 0;
+
+static int af903x_download_firmware(struct usb_device *udev, const struct firmware *fw)
+{
+	int ret=0;
+	deb_data("- Enter %s Function -\n",__FUNCTION__);
+	
+	return ret;
+}
+
+static int af903x_powerctrl(struct dvb_usb_device *d, int onoff)
+{
+
+	int ret;
+	deb_data("- Enter %s Function - %s\n",__FUNCTION__,onoff?"ON":"OFF");
+
+	// resume device before DL_ApCtrl(on)
+	if( onoff ) {
+		ret = usb_autopm_get_interface(uintfs);
+		if(ret) {
+			deb_data("%s calling usb_autopm_get_interface failed with %d\n", __FUNCTION__, ret);
+			gTblUsed = 0;
+
+			return ret;
+		}
+	}
+
+	ret = DL_ApCtrl(onoff);
+	if(ret) deb_data("	af903x_powerctrl Fail: 0x%04X\n", ret);
+
+	//suspend device after DL_ApCtrl(off)
+	if( !onoff ) {
+		usb_autopm_put_interface(uintfs);	
+	}
+
+	deb_data("- Exit %s Function - %s, ret=%d\n",__FUNCTION__,onoff?"ON":"OFF", ret);
+	return ret;
+}
+
+static int af903x_identify_state(struct usb_device *udev, struct dvb_usb_device_properties *props,
+			struct dvb_usb_device_description **desc, int *cold)
+{
+	deb_data("- Enter %s Function -\n",__FUNCTION__);
+	*cold = 0;
+
+	return 0;
+}
+
+static int af903x_frontend_attach(struct dvb_usb_adapter *adap)
+{
+	deb_data("- Enter %s Function -\n",__FUNCTION__);
+#ifdef V4L2_REFACTORED_MFE_CODE
+	adap->fe_adap[0].fe = af903x_attach(1);
+
+	return adap->fe_adap[0].fe == NULL ? -ENODEV : 0;
+#else
+	adap->fe = af903x_attach(1);
+
+	return adap->fe == NULL ? -ENODEV : 0;
+#endif
+}
+
+static int af903x_tuner_attach(struct dvb_usb_adapter *adap)
+{
+	deb_data("- Enter %s Function -\n",__FUNCTION__);
+#ifdef V4L2_REFACTORED_MFE_CODE
+	tuner_attach(adap->fe_adap[0].fe);
+#else
+	tuner_attach(adap->fe);
+#endif
+	return  0;
+}
+
+static int af903x_streaming_ctrl(struct dvb_usb_adapter *adap, int onoff)
+{
+	deb_data("- Enter %s Function - (%d) streaming state for %d\n",__FUNCTION__,onoff, adap->id);
+	
+
+	return 0;
+}
+
+static int af903x_pid_filter_ctrl(struct dvb_usb_adapter *adap, int onoff)
+{
+    int ret =0;
+    deb_data("%s: onoff:%d\n", __func__, onoff);
+
+    if (!onoff){
+        deb_data("  Reset PID Table\n");
+        DL_ResetPID();
+        PDC->fc[adap->id].ulcPIDs = 0;
+        memset(PDC->fc[adap->id].aulPIDs, 0, sizeof(FILTER_INFO));
+    }
+    PDC->fc[adap->id].bEnPID =  onoff;
+    ret = DL_PIDOnOff(PDC->fc[adap->id].bEnPID);
+
+    deb_data("  set pid onoff ok\n");
+    return ret;
+}
+
+
+static int af903x_pid_filter(struct dvb_usb_adapter *adap, int index, u16 pidnum,
+    int onoff)
+{
+//    if (down_interruptible (&my_sem))
+//            return -ERESTARTSYS;
+
+    int ret = 0;
+    Pid pid;
+    deb_data("- %s: set pid filter, index %d, pid %d, onoff %d.\n",
+    __func__, index, pidnum, onoff);
+
+
+    if (onoff) { //add filter to table
+        PDC->fc[adap->id].aulPIDs[index].filternum = pidnum;
+        if (!PDC->fc[adap->id].aulPIDs[index].onoff ){
+            PDC->fc[adap->id].aulPIDs[index].onoff = true;
+            PDC->fc[adap->id].ulcPIDs ++;
+        }
+    }
+    else{   //del filter from table
+        PDC->fc[adap->id].aulPIDs[index].filternum = 0;
+        if (PDC->fc[adap->id].aulPIDs[index].onoff ){
+            PDC->fc[adap->id].aulPIDs[index].onoff = false;
+            PDC->fc[adap->id].ulcPIDs --;
+        }
+    }
+
+    if (onoff) {
+        /* cannot use it as pid_filter_ctrl since it has to be done
+ *            before setting the first pid */
+        if (adap->feedcount == 1) {
+            deb_data("  first pid set, enable pid table\n");
+
+            pid.sectionType = SectionType_TABLE;
+            pid.table = 0x00;
+            pid.duration = 0xFF;
+
+            ret = af903x_pid_filter_ctrl(adap, onoff);
+            if (ret)
+                return ret;
+        }
+        pid.value = (Word)pidnum;
+        ret = DL_AddPID(index, pid);
+        if (ret)
+            return ret;
+
+    }
+    else{
+
+        pid.value = (Word)pidnum;
+        ret = DL_RemovePID(index, pid);
+        if (ret)
+            return ret;
+
+        if (adap->feedcount == 0) {
+            deb_data("  last pid unset, disable pid table\n");
+            ret = af903x_pid_filter_ctrl(adap, onoff);
+            if (ret)
+                return ret;
+        }
+
+    }
+
+    deb_data("  set pid ok, total pid num :%d\n", PDC->fc[adap->id].ulcPIDs);
+
+	msleep(100);
+	
+//    up(&my_sem);
+    return 0;
+}
+
+
+struct usb_device_id af903x_usb_id_table[] = {
+		{ USB_DEVICE(0x07ca,0xa333) },
+		{ USB_DEVICE(0x07ca,0xb867) },
+		{ USB_DEVICE(0x07ca,0x1867) },
+		{ USB_DEVICE(0x07ca,0x0337) },
+		{ USB_DEVICE(0x07ca,0xa867) },
+		{ USB_DEVICE(0x07ca,0x0867) },
+		{ USB_DEVICE(0x07ca,0xF337) },
+		{ USB_DEVICE(0x07ca,0x3867) },
+#if SUPPORT_AF903X_EVB 
+		{ USB_DEVICE(0x15A4,0x1000) },
+		{ USB_DEVICE(0x15A4,0x1001) },
+		{ USB_DEVICE(0x15A4,0x1002) },
+		{ USB_DEVICE(0x15A4,0x1003) },
+		{ USB_DEVICE(0x15A4,0x9035) },
+#endif //SUPPORT_AF903X_EVB
+		{ 0 }		/* Terminating entry */
+};
+MODULE_DEVICE_TABLE(usb, af903x_usb_id_table);
+
+struct dvb_usb_device_properties af903x_properties[] = {
+	{
+		.usb_ctrl          = DEVICE_SPECIFIC,
+		.download_firmware = af903x_download_firmware,
+		.no_reconnect      = 1,
+		.power_ctrl		   = af903x_powerctrl,
+		.identify_state    = af903x_identify_state,
+		
+		.num_adapters = 1,
+		.adapter = {
+			{
+#ifdef V4L2_REFACTORED_MFE_CODE
+				.num_frontends = 1,
+				.fe = {{
+#endif
+#if ENABLE_HW_PID
+					.caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_NEED_PID_FILTERING,
+#else
+					.caps = DVB_USB_ADAP_HAS_PID_FILTER,
+#endif
+					.pid_filter_count = 32,
+					.frontend_attach  = af903x_frontend_attach,
+					.tuner_attach     = af903x_tuner_attach,
+					.streaming_ctrl   = af903x_streaming_ctrl,
+					.pid_filter_ctrl  = af903x_pid_filter_ctrl,
+					.pid_filter		  = af903x_pid_filter,
+
+					.stream = { 
+					.type = USB_BULK,
+					.count = 10,
+					.endpoint = 0x84,
+					.u = {
+						.bulk = {
+							.buffersize = (188 * TS_PACKET_COUNT),
+							}
+						}
+					}
+#ifdef V4L2_REFACTORED_MFE_CODE
+		    }},
+#endif
+			},
+		},
+#if 0
+		.num_device_descs = 1,
+#else
+		.num_device_descs = 2,
+#endif
+		.devices = {
+			{   "AVerMedia A333 DVB-T Recevier",
+				{ &af903x_usb_id_table[0]
+				 ,&af903x_usb_id_table[1]
+#if SUPPORT_AF903X_EVB 
+				 ,&af903x_usb_id_table[7]
+				 ,&af903x_usb_id_table[8]
+#endif //SUPPORT_AF903X_EVB
+				},
+
+				{ NULL },
+			},
+			{   "AVerMedia A867 DVB-T Recevier",  
+				{ &af903x_usb_id_table[2]
+				 ,&af903x_usb_id_table[3]
+				 ,&af903x_usb_id_table[4]
+				 ,&af903x_usb_id_table[5]
+				 ,&af903x_usb_id_table[6]
+				 ,&af903x_usb_id_table[7]
+				},
+
+				{ NULL },
+			}
+		}
+	}
+};
+
+int af903x_device_count = ARRAY_SIZE(af903x_properties);
diff --git a/drivers/media/dvb/dvb-usb/a867_af903x-drv.c b/drivers/media/dvb/dvb-usb/a867_af903x-drv.c
new file mode 100644
index 0000000..3a030a8
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_af903x-drv.c
@@ -0,0 +1,1238 @@
+#include "a867_af903x.h"
+//#include "a867_firmware.h"
+#include "a867_ofdm.h"
+
+#define true 1
+#define false 0
+
+#define FW_VER         0x08060000
+int dvb_usb_af903x_debug = 0; // disable all level by default
+module_param_named(debug,dvb_usb_af903x_debug, int, 0644);
+MODULE_PARM_DESC(debug, "set debugging level (info=1, deb_fw=2, deb_fwdata=4, deb_data=8 (or-able)), default=0");
+
+int dvb_usb_af903x_snrdb = 0; // output SNR 16bit format
+module_param_named(snrdb,dvb_usb_af903x_snrdb, int, 0644);
+MODULE_PARM_DESC(snrdb, "set SNR format (16bit=0, dB decibel=1), default=0");
+
+struct usb_device *udevs = NULL;
+struct usb_interface *uintfs = NULL;
+PDEVICE_CONTEXT PDC;
+
+  
+//************** DRV_ *************//
+
+static DWORD DRV_ResetPID(
+    IN	void*	handle,
+    IN	BYTE	ucSlaveDemod)
+{
+	DWORD dwError = Error_NO_ERROR;
+    PDEVICE_CONTEXT pdc = (PDEVICE_CONTEXT)handle;
+          
+    //Clear pidTable
+    dwError = Demodulator_resetPid ((Demodulator*) &pdc->Demodulator, ucSlaveDemod);
+
+	return dwError;
+}
+
+static DWORD DRV_PIDOnOff(
+	void	*handle, 
+	BYTE	ucSlaveDemod,
+	DWORD	dwOnOff)
+{
+	DWORD dwError = Error_NO_ERROR;
+	PDEVICE_CONTEXT pdc = (PDEVICE_CONTEXT)handle;
+
+	if(dwOnOff)
+	{
+        dwError = Demodulator_controlPidFilter ((Demodulator*) &pdc->Demodulator, ucSlaveDemod, 1);
+	}
+	else
+	{
+        dwError = Demodulator_controlPidFilter ((Demodulator*) &pdc->Demodulator, ucSlaveDemod, 0);
+	}
+
+	return dwError;
+}
+
+static DWORD DRV_AddPID(
+	void	*handle,
+	BYTE	ucSlaveDemod,
+	DWORD	index,
+	Pid		pid)
+{
+	DWORD dwError = Error_NO_ERROR;
+
+    PDEVICE_CONTEXT pdc = (PDEVICE_CONTEXT)handle;
+          
+    dwError = Demodulator_addPidToFilter ((Demodulator*) &pdc->Demodulator, ucSlaveDemod,index, pid);
+
+	return dwError;
+}
+
+DWORD DRV_RemovePID(
+    IN  void*   handle,
+    IN  BYTE    ucSlaveDemod,
+    IN  Byte    index,
+    IN  Pid     pid
+)
+{
+//    deb_data("- Enter %s Function - , index:%d, pid:%x \n",__FUNCTION__, index, pid.value);
+
+    DWORD   dwError = Error_NO_ERROR;
+
+    PDEVICE_CONTEXT pdc = (PDEVICE_CONTEXT)handle;
+
+    dwError = Demodulator_removePidAt ((Demodulator*) &pdc->Demodulator, ucSlaveDemod,index, pid);
+
+    return(dwError);
+
+}
+
+
+
+static DWORD DRV_IrTblDownload(IN      void * handle)
+{
+        DWORD dwError = Error_NO_ERROR;
+        PDEVICE_CONTEXT pdc = (PDEVICE_CONTEXT)handle;
+        struct file *filp;
+        unsigned char b_buf[512] ;
+        int i, fileSize;
+        mm_segment_t oldfs;
+
+        deb_data("- Enter %s Function -\n",__FUNCTION__);
+
+        oldfs=get_fs();
+        set_fs(KERNEL_DS);
+
+        filp=filp_open("/lib/firmware/af35irtbl.bin", O_RDWR,0644);
+        if ( IS_ERR(filp) ) {
+                deb_data("      LoadIrTable : Can't open file\n");goto exit;}
+
+        if ( (filp->f_op) == NULL ) {
+                deb_data("      LoadIrTable : File Operation Method Error!!\n");goto exit;}
+
+        filp->f_pos=0x00;
+        fileSize = filp->f_op->read(filp,b_buf,sizeof(b_buf),&filp->f_pos);
+
+        for(i=0; i<fileSize; i++)
+        {
+              //deb_data("\n Data %d",i); //
+              //deb_data("0x%x",b_buf[i]);//
+              // dwError = Af901xWriteReg(ucDemod2WireAddr, 0, MERC_IR_TABLE_BASE_ADDR + i, b_buf[i]);
+              //if (dwError) goto exit;
+        }
+
+        dwError = Demodulator_loadIrTable((Demodulator*) &pdc->Demodulator, (Word)fileSize, b_buf);
+        if (dwError) {deb_data("Demodulator_loadIrTable fail"); goto exit;}
+
+        filp_close(filp, NULL);
+        set_fs(oldfs);
+
+        return (dwError);
+exit:
+        deb_data("LoadIrTable fail!\n");
+	return dwError;
+
+}
+
+static DWORD  DRV_GetEEPROMConfig2(
+        void *      handle,
+        BYTE       ucSlaveDemod)
+{
+
+	DWORD dwError = Error_NO_ERROR;
+    	tWORD    shift = 0;
+    	PDEVICE_CONTEXT pdc = (PDEVICE_CONTEXT)handle;
+	BYTE btmp = 0;
+
+	deb_data("- Enter %s Function -",__FUNCTION__);
+	
+    	if(ucSlaveDemod) shift = EEPROM_SHIFT;
+    
+    	dwError = Demodulator_readRegisters((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, EEPROM_TUNERID+shift, 1, &btmp);
+    	if (dwError) goto exit;
+    	deb_data("EEPROM_TUNERID%d  = 0x%02X\n", ucSlaveDemod, btmp);		
+    	PTI.TunerId = btmp;  
+
+exit:
+    
+    return(dwError);     
+}  
+
+static DWORD DRV_SetFreqBw(
+    	void*	handle,      
+     	BYTE 	ucSlaveDemod,
+      	DWORD   dwFreq,      
+      	WORD	ucBw
+)
+{
+	DWORD dwError = Error_NO_ERROR;
+    
+	PDEVICE_CONTEXT pdc = (PDEVICE_CONTEXT)handle;
+
+	//Bool bLock = true;
+
+	deb_data("- Enter %s Function -\n ",__FUNCTION__);
+	deb_data("       ucSlaveDemod = %d, Freq= %d, BW=%d\n", ucSlaveDemod, dwFreq, ucBw);
+
+    if (pdc->fc[ucSlaveDemod].bEnPID)
+    {
+		deb_data("		Reset HW PID table\n ");
+        //Disable PID filter
+		Demodulator_writeRegisterBits ((Demodulator*) &pdc->Demodulator, ucSlaveDemod, Processor_OFDM, p_mp2if_pid_en, mp2if_pid_en_pos, mp2if_pid_en_len, 0);
+		
+    }
+	
+    down(&PDC->tunerLock);
+
+    PDC->fc[0].AVerFlags &= ~(0x08);
+    PDC->fc[0].AVerFlags |= 0x04;
+    PTI.bSettingFreq = true; //before acquireChannel, it is ture;  otherwise, it is false
+
+    if(dwFreq) {
+        pdc->fc[ucSlaveDemod].ulDesiredFrequency = dwFreq;
+    }
+    else {
+        dwFreq = pdc->fc[ucSlaveDemod].ulDesiredFrequency;
+    }
+
+    if(ucBw) {
+        pdc->fc[ucSlaveDemod].ucDesiredBandWidth = ucBw*1000;
+	}
+    else {
+        ucBw = pdc->fc[ucSlaveDemod].ucDesiredBandWidth;
+    	}
+
+    deb_data("Real Freq= %d, BW=%d\n", pdc->fc[ucSlaveDemod].ulDesiredFrequency, pdc->fc[ucSlaveDemod].ucDesiredBandWidth);
+           
+
+    if(!PTI.bTunerInited){
+        deb_data("    Skip SetFreq - Tuner is still off!\n");
+        goto exit;
+    }
+	
+    PTI.bTunerOK = false;        
+
+    if (pdc->fc[ucSlaveDemod].ulDesiredFrequency!=0 && pdc->fc[ucSlaveDemod].ucDesiredBandWidth!=0)	
+    {
+	deb_data("AcquireChannel : Real Freq= %d, BW=%d\n", pdc->fc[ucSlaveDemod].ulDesiredFrequency, pdc->fc[ucSlaveDemod].ucDesiredBandWidth);
+	dwError = Demodulator_acquireChannel ((Demodulator*) &pdc->Demodulator, ucSlaveDemod, pdc->fc[ucSlaveDemod].ucDesiredBandWidth, pdc->fc[ucSlaveDemod].ulDesiredFrequency);  
+	//PTI.bSettingFreq = false;
+    	if (dwError) 
+    	{
+        	deb_data("Demod_acquireChannel fail! 0x%08x\n", dwError);
+        	goto exit;
+    	}	
+	else //when success acquireChannel, record currentFreq/currentBW.
+	{
+		pdc->fc[ucSlaveDemod].ulCurrentFrequency = pdc->fc[ucSlaveDemod].ulDesiredFrequency;	
+		pdc->fc[ucSlaveDemod].ucCurrentBandWidth = pdc->fc[ucSlaveDemod].ucDesiredBandWidth;  
+	}
+    }
+    else {
+       	deb_data("Demod_acquireChannel skipped\n");
+    }
+
+    if(pdc->StreamType == StreamType_DVBT_DATAGRAM) {
+        PDC->fc[ucSlaveDemod].OvrFlwChk = CHECK_LOCK_LOOPS ;
+        PDC->fc[ucSlaveDemod].UnLockCount = 0;
+    }
+
+    PTI.bTunerOK = true;
+
+exit:
+
+    PTI.bSettingFreq = false;
+    up(&PDC->tunerLock);
+
+    return(dwError);  
+}
+
+static DWORD DRV_getFirmwareVersionFromFile( 
+	 	Processor	processor, 
+		DWORD* 		version
+)
+{
+    DWORD OFDM_VER1 = DVB_OFDM_VERSION1;
+    DWORD OFDM_VER2 = DVB_OFDM_VERSION2;
+    DWORD OFDM_VER3 = DVB_OFDM_VERSION3;
+    DWORD OFDM_VER4 = DVB_OFDM_VERSION4;
+
+    DWORD LINK_VER1 = DVB_LL_VERSION1;
+    DWORD LINK_VER2 = DVB_LL_VERSION2;
+    DWORD LINK_VER3 = DVB_LL_VERSION3;    
+    DWORD LINK_VER4 = DVB_LL_VERSION4;    
+
+    if(processor == Processor_OFDM) {
+        *version = (DWORD)( (OFDM_VER1 << 24) + (OFDM_VER2 << 16) + (OFDM_VER3 << 8) + OFDM_VER4);
+    }
+    else { //LINK
+        *version = (DWORD)( (LINK_VER1 << 24) + (LINK_VER2 << 16) + (LINK_VER3 << 8) + LINK_VER4);    
+    }
+    
+    return *version;
+}
+
+static DWORD  DRV_Initialize(
+	    void *      handle
+)
+{
+	DWORD error = Error_NO_ERROR;
+	 
+	PDEVICE_CONTEXT pdc = (PDEVICE_CONTEXT)handle;
+
+	DWORD fileVersion, cmdVersion = 0; 
+
+	deb_data("- Enter %s Function -\n",__FUNCTION__);
+
+	if(pdc->Demodulator.booted) //from Standard_setBusTuner() > Standard_getFirmwareVersion()
+    	{
+        	//use "#define version" to get fw version (from firmware.h title)
+        	error = DRV_getFirmwareVersionFromFile(Processor_OFDM, &fileVersion);
+
+        	//use "Command_QUERYINFO" to get fw version 
+        	error = Demodulator_getFirmwareVersion((Demodulator*) &pdc->Demodulator, Processor_OFDM, &cmdVersion);
+        	if(error) deb_data("DRV_Initialize : Demodulator_getFirmwareVersion : error = 0x%08x\n", error);
+
+        	if(cmdVersion != fileVersion)
+        	{
+            		deb_data("Reboot: Outside Fw = 0x%X, Inside Fw = 0x%X", fileVersion, cmdVersion);               
+            		error = Demodulator_reboot((Demodulator*) &pdc->Demodulator);
+            		pdc->bBootCode = true;
+            		if(error) 
+            		{
+                		deb_data("Demodulator_reboot : error = 0x%08x\n", error);
+                		return error;
+            		}
+            		else {
+                		return Error_NOT_READY;
+            		}
+        	}
+        	else
+        	{
+            		deb_data("	Fw version is the same!\n");
+  	      		error = Error_NO_ERROR;
+        	}
+	}//pdc->Demodulator.booted
+	
+ReInit:  //Patch for NIM fail or disappear, Maggie   
+    error = Demodulator_initialize ((Demodulator*) &pdc->Demodulator, pdc->Demodulator.chipNumber , 8000, pdc->StreamType, pdc->architecture);    
+    if (error) 
+    { 
+        deb_data("Device initialize fail : 0x%08x\n", error);
+        if( ((error&Error_FIRMWARE_STATUS) && (error&0x10)) && (pdc->Demodulator.chipNumber>1) )
+        {
+            pdc->Demodulator.cmdDescription->sendCommand ((Demodulator*) &pdc->Demodulator, Command_FW_DOWNLOAD_END, 0, Processor_LINK, 0, NULL, 0, NULL);
+
+            deb_data("	Retry to download FW with Single TS\n");
+            pdc->Demodulator.chipNumber = 1;
+            pdc->bDualTs = false;
+            error = Demodulator_writeRegister ((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, 0x417F, 0);
+            goto ReInit;
+       }
+    }
+    else {
+        deb_data("    Device initialize Ok!!\n");
+    }
+
+	error = Demodulator_writeRegisterBits ((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, 
+											p_reg_usb_min_len, reg_usb_min_len_pos, reg_usb_min_len_len, 1);
+
+    Demodulator_getFirmwareVersion ((Demodulator*) &pdc->Demodulator, Processor_OFDM, &cmdVersion);
+    deb_data("    FwVer OFDM = 0x%X, ", cmdVersion);
+    Demodulator_getFirmwareVersion ((Demodulator*) &pdc->Demodulator, Processor_LINK, &cmdVersion);
+    deb_data("FwVer LINK = 0x%X\n", cmdVersion);
+    
+    return error;
+	
+}
+
+static DWORD DRV_InitDevInfo(
+    	void *      handle,
+    	BYTE        ucSlaveDemod
+)
+{
+    DWORD dwError = Error_NO_ERROR;    
+ 
+    PDC->fc[ucSlaveDemod].ulCurrentFrequency = 0;  
+    PDC->fc[ucSlaveDemod].ucCurrentBandWidth = 0;
+
+    PDC->fc[ucSlaveDemod].ulDesiredFrequency = 0;	
+    PDC->fc[ucSlaveDemod].ucDesiredBandWidth = 6000;	
+
+    //For PID Filter Setting
+    //PDC->fc[ucSlaveDemod].ulcPIDs = 0;    
+    PDC->fc[ucSlaveDemod].bEnPID = true;
+    PDC->fc[ucSlaveDemod].bApOn = false;
+    PDC->fc[ucSlaveDemod].bResetTs = false;
+
+    PTI.bTunerOK = false;
+    PTI.bSettingFreq = false;
+
+    return dwError;
+}	
+
+static DWORD DRV_GetEEPROMConfig(    
+	void *      handle)
+{
+	DWORD dwError = Error_NO_ERROR;
+	PDEVICE_CONTEXT pdc = (PDEVICE_CONTEXT)handle;
+    	BYTE ucSlaveDemod = 0;
+	BYTE btmp = 0;
+
+	deb_data("- Enter %s Function -",__FUNCTION__);	
+   
+	//bIrTblDownload option
+	dwError =   Demodulator_readRegisters((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, EEPROM_IRMODE, 1, &btmp);
+	if (dwError) return(dwError);
+	PDC->bIrTblDownload = btmp ? true:false;
+	deb_data(	"EEPROM_IRMODE = 0x%02X, ", btmp);
+        deb_data("bIrTblDownload %s\n", PDC->bIrTblDownload?"ON":"OFF");
+ 
+    	PDC->bDualTs = false;
+    	PDC->architecture = Architecture_DCA;
+    	PDC->Demodulator.chipNumber = 1;    
+    	PDC->bDCAPIP = false;
+
+
+        dwError = DRV_GetEEPROMConfig2(pdc, ucSlaveDemod);
+	 if (dwError) return(dwError);  
+        dwError = DRV_InitDevInfo(pdc, ucSlaveDemod);
+    
+   	 return(dwError);     
+}   
+
+static DWORD DRV_SetBusTuner(
+	 void * handle, 
+	 Word busId, 
+	 Word tunerId
+)
+{
+	DWORD dwError = Error_NO_ERROR;
+	DWORD 	 version = 0;
+
+	PDEVICE_CONTEXT pdc = (PDEVICE_CONTEXT)handle;
+
+	deb_data("- Enter %s Function -",__FUNCTION__);
+	deb_data("busId = 0x%x, tunerId =0x%x\n", busId, tunerId);
+
+	if ((pdc->UsbMode==0x0110) && (busId==Bus_USB)) {
+        busId=Bus_USB11;    
+    }
+    
+    	dwError = Demodulator_setBusTuner ((Demodulator*) &pdc->Demodulator, busId, tunerId);
+	if (dwError) {deb_data("Demodulator_setBusTuner error\n");return dwError;}
+	dwError = Demodulator_getFirmwareVersion ((Demodulator*) &pdc->Demodulator, Processor_LINK, &version);
+    	if (version != 0) {
+        	pdc->Demodulator.booted = True;
+    	} 
+    	else {
+        	pdc->Demodulator.booted = False;
+    	}
+    	return(dwError); 
+}
+
+
+DWORD A333TunerPowerControl(
+	PDEVICE_CONTEXT pdc,	
+	BYTE    ucSlaveDemod,
+	bool        bPowerOn
+)
+{
+
+	DWORD dwError = Error_NO_ERROR;
+
+	if(bPowerOn)
+       	PTI.bTunerInited = true;
+	else
+		PTI.bTunerInited = false;    
+
+    //control oscilator	
+   	dwError = Demodulator_writeRegister((Demodulator*) &PDC->Demodulator, 0, Processor_LINK, PDC->Map.GPIO_OSC_en, 1);
+    dwError = Demodulator_writeRegister((Demodulator*) &PDC->Demodulator, 0, Processor_LINK, PDC->Map.GPIO_OSC_on, 1);
+   	dwError = Demodulator_writeRegister((Demodulator*) &PDC->Demodulator, 0, Processor_LINK, PDC->Map.GPIO_OSC_o, 1); 
+
+    dwError = Demodulator_writeRegister((Demodulator*) &PDC->Demodulator, 0, Processor_LINK, PDC->Map.GPIO_TUR1_en, 1);
+   	dwError = Demodulator_writeRegister((Demodulator*) &PDC->Demodulator, 0, Processor_LINK, PDC->Map.GPIO_TUR1_on, 1);
+    dwError = Demodulator_writeRegister((Demodulator*) &PDC->Demodulator, 0, Processor_LINK, PDC->Map.GPIO_TUR1_o, 1); 
+   	dwError = Demodulator_writeRegister((Demodulator*) &PDC->Demodulator, 0, Processor_LINK, PDC->Map.GPIO_TUR2_en, 1);
+    dwError = Demodulator_writeRegister((Demodulator*) &PDC->Demodulator, 0, Processor_LINK, PDC->Map.GPIO_TUR2_on, 1);
+   	dwError = Demodulator_writeRegister((Demodulator*) &PDC->Demodulator, 0, Processor_LINK, PDC->Map.GPIO_TUR2_o, 1);
+
+    if(bPowerOn) 
+	{
+   		dwError=Demodulator_writeRegister((Demodulator*) &PDC->Demodulator, 0, Processor_LINK, PDC->Map.GPIO_OSC_o, 1); 
+       	dwError=Demodulator_writeRegister((Demodulator*) &PDC->Demodulator, 0, Processor_LINK, PDC->Map.GPIO_TUR1_o, 1);
+       	dwError=Demodulator_writeRegister((Demodulator*) &PDC->Demodulator, 0, Processor_LINK, PDC->Map.GPIO_TUR2_o, 1);
+        if(pdc->bTunerPowerOff == true) 
+   	    {
+       	    dwError = Demodulator_initialize ((Demodulator*) &pdc->Demodulator, pdc->Demodulator.chipNumber, 
+											pdc->Demodulator.bandwidth[0], pdc->StreamType, pdc->architecture);  
+			pdc->bTunerPowerOff = false;
+		}              	        
+		
+    }
+	else 
+	{ // power off
+	
+		if(pdc->architecture == Architecture_PIP)
+		{
+			if(pdc->fc[0].tunerinfo.bTunerInited == 0 && pdc->fc[1].tunerinfo.bTunerInited == 0) 
+           	{                                
+               	if(pdc->bTunerPowerOff == false) 
+               	{
+                   	dwError = Demodulator_finalize((Demodulator*) &pdc->Demodulator);
+					pdc->bTunerPowerOff = true;
+				}
+       	        dwError = Demodulator_writeRegister((Demodulator*)&PDC->Demodulator,0,Processor_LINK,PDC->Map.GPIO_TUR1_o, 0);
+           	    dwError = Demodulator_writeRegister((Demodulator*)&PDC->Demodulator,0,Processor_LINK,PDC->Map.GPIO_TUR2_o, 0);
+   	        	dwError = Demodulator_writeRegister((Demodulator*)&PDC->Demodulator,0,Processor_LINK,PDC->Map.GPIO_OSC_o, 0);
+            }
+        }
+		else 
+		{
+			if(pdc->bTunerPowerOff == false) 
+            {                
+               	dwError = Demodulator_finalize((Demodulator*) &pdc->Demodulator);
+	        	pdc->bTunerPowerOff = true;
+			}      
+
+			dwError = Demodulator_writeRegister((Demodulator*) &PDC->Demodulator, 0, Processor_LINK, PDC->Map.GPIO_TUR1_o, 0);
+			dwError = Demodulator_writeRegister((Demodulator*) &PDC->Demodulator, 0, Processor_LINK, PDC->Map.GPIO_TUR2_o, 0);
+			dwError = Demodulator_writeRegister((Demodulator*) &PDC->Demodulator, 0, Processor_LINK, PDC->Map.GPIO_OSC_o, 0);
+		}        	
+	}
+
+	return dwError;
+}
+
+DWORD A337TunerPowerControl(
+	PDEVICE_CONTEXT pdc,	
+	BYTE    ucSlaveDemod,
+	bool        bPowerOn
+)
+{
+
+	DWORD dwError = Error_NO_ERROR;
+
+	if(bPowerOn)
+		PTI.bTunerInited = true;
+	else
+		PTI.bTunerInited = false;    
+
+	if(bPowerOn) //tuner on
+	{
+		if(pdc->bTunerPowerOff == true) 
+		{
+			//use variable to control gpio
+
+			// enable tuner power
+			dwError = Demodulator_writeRegister((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, pdc->Map.GPIO_TUR1_en, 1);
+			dwError = Demodulator_writeRegister((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, pdc->Map.GPIO_TUR1_on, 1);
+			dwError = Demodulator_writeRegister((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, pdc->Map.GPIO_TUR2_en, 1);
+			dwError = Demodulator_writeRegister((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, pdc->Map.GPIO_TUR2_on, 1);
+
+			dwError = Demodulator_writeRegister((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, pdc->Map.GPIO_TUR1_o, 1); 
+			mdelay(100);
+			dwError = Demodulator_writeRegister((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, pdc->Map.GPIO_TUR2_o, 1);
+			mdelay(100);
+			dwError = Demodulator_writeRegister((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, p_reg_top_gpioh12_en, 1);
+			dwError = Demodulator_writeRegister((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, p_reg_top_gpioh12_on, 1);
+
+				
+			// reset tuner
+			deb_data("A337 reset");
+			mdelay(10);
+			dwError = Demodulator_writeRegister((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, p_reg_top_gpioh12_o, 0); 
+			mdelay(30);
+			dwError = Demodulator_writeRegister((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, p_reg_top_gpioh12_o, 1);
+
+			mdelay(300);
+			deb_data("pdc->bTunerPowerOff == true\n");
+			dwError = Demodulator_initialize ((Demodulator*) &pdc->Demodulator, pdc->Demodulator.chipNumber , pdc->Demodulator.bandwidth[0], pdc->StreamType, pdc->architecture);  
+			pdc->bTunerPowerOff = false;
+		}              	        
+	}
+	else //tuner off
+	{
+		// Bugfix: wrong level of tuner i2c whiling plugging in device.
+		dwError = Demodulator_finalize((Demodulator*) &pdc->Demodulator);
+		if(pdc->bTunerPowerOff == false) 
+		{                
+			pdc->bTunerPowerOff = true;
+
+			dwError = Demodulator_writeRegister((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, p_reg_top_gpioh12_o, 0);
+			dwError = Demodulator_writeRegister((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, p_reg_top_gpioh12_en, 0);
+			dwError = Demodulator_writeRegister((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, p_reg_top_gpioh12_on, 0);
+			mdelay(10);
+
+			// disable tuner power
+			dwError = Demodulator_writeRegister((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, pdc->Map.GPIO_TUR1_o, 0);
+			dwError = Demodulator_writeRegister((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, pdc->Map.GPIO_TUR2_o, 0);
+			dwError = Demodulator_writeRegister((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, pdc->Map.GPIO_TUR1_en,0);
+			dwError = Demodulator_writeRegister((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, pdc->Map.GPIO_TUR1_on,0);
+			dwError = Demodulator_writeRegister((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, pdc->Map.GPIO_TUR2_en,0);
+			dwError = Demodulator_writeRegister((Demodulator*) &pdc->Demodulator, 0, Processor_LINK, pdc->Map.GPIO_TUR2_on,0);
+		}      
+	}
+
+	return dwError;
+}
+
+
+static DWORD DRV_TunerPowerCtrl(
+    	void *	handle, 
+     	BYTE	ucSlaveDemod,
+     	bool		bPowerOn
+)
+{ 
+    DWORD dwError = Error_NO_ERROR;	
+
+    PDEVICE_CONTEXT pdc = (PDEVICE_CONTEXT)handle;
+
+    deb_data("- Enter %s Function , bPowerOn=%d -\n",__FUNCTION__, bPowerOn);
+
+	deb_data("Detected tuner ID: 0x%x\n", pdc->fc[0].tunerinfo.TunerId);
+
+	switch(PDC->idProduct)
+	{
+	case 0xa337:	//A337
+	case 0x0337:	//A867
+	case 0xa867:	//A867
+    case 0x0867:
+    case 0x1867:
+	case 0xF337:
+		dwError = A337TunerPowerControl(pdc, ucSlaveDemod, bPowerOn);
+		break;
+	case 0xa333:	//A337 & EVB
+	default:	
+		dwError = A333TunerPowerControl(pdc, ucSlaveDemod, bPowerOn);
+	}
+
+	return dwError;
+}
+
+static DWORD DRV_ApCtrl (
+      void *      handle,
+      Byte        ucSlaveDemod,
+      Bool        bOn
+)
+{
+	DWORD dwError = Error_NO_ERROR;
+
+        PDEVICE_CONTEXT pdc = (PDEVICE_CONTEXT)handle;
+
+	deb_data("enter DRV_ApCtrl: ucSlaveDemod = %d, bOn = %s\n", ucSlaveDemod, bOn?"ON":"OFF"); 
+
+      //deb_data("enter DRV_ApCtrl: Demod[%d].GraphBuilt = %d", ucSlaveDemod, pdc->fc[ucSlaveDemod].GraphBuilt); 
+	
+   	Demodulator_writeRegister((Demodulator*) &PDC->Demodulator, 0, Processor_LINK, PDC->Map.GPIO_LED_en, 1); 
+   	Demodulator_writeRegister((Demodulator*) &PDC->Demodulator, 0, Processor_LINK, PDC->Map.GPIO_LED_on, 1); 
+   	Demodulator_writeRegister((Demodulator*) &PDC->Demodulator, 0, Processor_LINK, PDC->Map.GPIO_LED_o, bOn?1:0); 
+
+
+	dwError = DRV_TunerPowerCtrl(handle, ucSlaveDemod, bOn);
+       	if(dwError) deb_data("DRV_TunerPowerCtrl Fail: 0x%08x\n", dwError); 
+
+	
+    	dwError = Demodulator_controlPowerSaving((Demodulator*) &pdc->Demodulator, ucSlaveDemod, bOn);   
+    	if(dwError) deb_data("DRV_ApCtrl: Demodulator_controlPowerSaving error = 0x%08x\n", dwError);
+	
+    return(dwError);
+}
+
+
+static DWORD DRV_TunerWakeup(
+      void *     handle
+)
+{   
+    	DWORD dwError = Error_NO_ERROR;
+
+    	PDEVICE_CONTEXT pdc = (PDEVICE_CONTEXT) handle;
+
+	deb_data("- Enter %s Function -\n",__FUNCTION__);
+
+	//tuner power on
+	dwError = Demodulator_writeRegisterBits((Demodulator*) &pdc->Demodulator, 0, Processor_LINK,  p_reg_top_gpioh7_o, reg_top_gpioh7_o_pos, reg_top_gpioh7_o_len, 1);	 
+
+    return(dwError);
+
+}
+
+static DWORD DRV_Reboot(
+	void * handle
+)
+{
+    	DWORD dwError = Error_NO_ERROR;
+
+    	PDEVICE_CONTEXT pdc = (PDEVICE_CONTEXT) handle;
+
+	deb_data("- Enter %s Function -\n",__FUNCTION__);
+
+	dwError = Demodulator_reboot((Demodulator*) &pdc->Demodulator);
+
+	return(dwError);
+}
+//s021+e
+
+static DWORD DRV_IsPsbOverflow(
+	void *	handle,
+	Byte	ucSlaveDemod,
+	Bool	*bPsbOverflow
+)
+{
+	DWORD dwError = Error_NO_ERROR;
+	Byte ucValue;
+        PDEVICE_CONTEXT pdc = (PDEVICE_CONTEXT)handle;
+	Bool PsbOverflow;
+
+	deb_data("enter %s: - \n", __FUNCTION__); 
+
+	if( ucSlaveDemod ) { //13
+		dwError = Demodulator_readRegister((Demodulator*) &pdc->Demodulator, 0, Processor_OFDM, p_reg_sys_buf_overflow, &ucValue);
+		if( dwError ) goto exit;
+
+		PsbOverflow = (ucValue&0x01)? 1:0;
+		if( PsbOverflow ) {
+			dwError = Demodulator_writeRegister((Demodulator*) &pdc->Demodulator, 0, Processor_OFDM, p_reg_sys_buf_overflow, ucValue&(~0x01));
+			if( dwError ) goto exit;
+		}
+	}
+	else { //15
+		dwError = Demodulator_readRegister((Demodulator*) &pdc->Demodulator, 0, Processor_OFDM, p_mp2if_psb_overflow, &ucValue);
+		if( dwError ) goto exit;
+
+		PsbOverflow = (ucValue&0x01)? 1:0;
+		if( PsbOverflow ) {
+			dwError = Demodulator_writeRegister((Demodulator*) &pdc->Demodulator, 0, Processor_OFDM, p_mp2if_psb_overflow, ucValue&(~0x01));
+			if( dwError ) goto exit;
+		}
+	}
+
+	if( bPsbOverflow ) *bPsbOverflow = PsbOverflow;
+exit:
+	return dwError;
+}
+
+//************** DL_ *************//
+//
+DWORD DL_ResetPID(void)
+{
+	DWORD dwError = Error_NO_ERROR;
+
+    dwError = DRV_ResetPID(PDC, 0);
+
+	return dwError;
+}
+
+DWORD DL_AddPID(BYTE index, Pid pid)
+{
+	DWORD dwError = Error_NO_ERROR;
+
+	dwError = DRV_AddPID(PDC, 0, index, pid);
+	
+	return dwError;
+}
+
+DWORD DL_PIDOnOff(DWORD OnOff)
+{
+	DWORD dwError = Error_NO_ERROR;
+
+	dwError = DRV_PIDOnOff(PDC, 0, OnOff);
+
+	return dwError;
+}
+
+DWORD DL_RemovePID(
+    IN  Byte    index,
+    IN  Pid     pid
+)
+{
+
+    DWORD dwError = Error_NO_ERROR;
+	
+	dwError = DRV_RemovePID(PDC, 0, index, pid);
+
+    return(dwError);
+}
+
+
+DWORD DL_IsPsbOverflow(
+	void *	handle,
+	Byte	ucSlaveDemod,
+	Bool *	bPsbOverflow
+)
+{
+	DWORD dwError = DRV_IsPsbOverflow(handle, ucSlaveDemod, bPsbOverflow);
+	return dwError;
+}
+
+
+DWORD DL_MonitorReception(Bool *lock)
+{
+	DWORD dwError = Error_NO_ERROR;
+	BYTE    ucSlaveDemod=0;
+	Bool bLock = False;
+	ChannelStatistic stat;
+
+	deb_data("- Enter %s Function , OvrFlwChk=%d, UnLockCount=%d-\n",__FUNCTION__,
+			PDC->fc[ucSlaveDemod].OvrFlwChk,
+			PDC->fc[ucSlaveDemod].UnLockCount);
+
+	down(&PDC->tunerLock);
+
+	if( PDC->fc[ucSlaveDemod].ulDesiredFrequency==0 || PDC->fc[ucSlaveDemod].ucDesiredBandWidth==0 ) {
+		if( lock ) *lock = False;
+		deb_data("- %s Function skipping\n",__FUNCTION__);
+		goto exit;
+	}
+
+	// check lock status
+	dwError= Demodulator_isLocked((Demodulator*) &PDC->Demodulator, ucSlaveDemod, &bLock);
+	if( dwError!=Error_NO_ERROR ) {
+		goto exit;
+	}
+
+	// consider as unlock if UBC is not zero
+	dwError = Demodulator_getChannelStatistic((Demodulator*) &PDC->Demodulator, ucSlaveDemod, &stat);
+	if( dwError!=Error_NO_ERROR ) {
+		goto exit;
+	}
+
+//uncomment this because this causes instability in channel scan.
+
+
+	// report lock status
+	if( lock ) *lock = bLock;
+	deb_data("- %s Function, LOCK = %d\n", __FUNCTION__, bLock);
+
+	// stop monitoring
+	if(PDC->fc[ucSlaveDemod].OvrFlwChk<1) {
+		deb_data("- %s Function end of monitor cycle -\n",__FUNCTION__);
+
+		// if lock is lost for a while, try to reacquire channel
+		if( PDC->fc[ucSlaveDemod].UnLockCount >= CHECK_LOCK_LOOPS*2/3) {
+			WORD bw = PDC->fc[ucSlaveDemod].ucDesiredBandWidth;
+			DWORD freq = PDC->fc[ucSlaveDemod].ulDesiredFrequency;
+	
+
+			deb_data("- %s Function need to reacquire channel, freq=%d, bw=%d-\n",__FUNCTION__,
+					freq, bw);
+
+			// reacquire channel
+			// first power off, then power on
+			DRV_ApCtrl (PDC, 0, 0);
+			User_delay(0, 500);
+			DRV_ApCtrl (PDC, 0, 1);
+			User_delay(0, 500);
+
+			// switch to another frequency, say 500MHz
+			deb_data("- %s Function switch to 500MHz first -\n",__FUNCTION__);
+			Demodulator_acquireChannel ((Demodulator*) &PDC->Demodulator, ucSlaveDemod,
+							bw, 500000);
+			User_delay(0, 500);
+			// now change to original frequency
+			deb_data("- %s Function switch to %d KHz later -\n",__FUNCTION__, freq);
+			Demodulator_acquireChannel ((Demodulator*) &PDC->Demodulator, ucSlaveDemod,
+							bw, freq);
+		}	
+
+		// restart monitor cycle
+		PDC->fc[ucSlaveDemod].OvrFlwChk = CHECK_LOCK_LOOPS;
+		PDC->fc[ucSlaveDemod].UnLockCount = 0;
+
+		dwError = Error_NO_ERROR;
+		goto exit;
+	}
+	
+	PDC->fc[ucSlaveDemod].OvrFlwChk--;
+
+	// maintain lock count
+	if( !bLock ) PDC->fc[ucSlaveDemod].UnLockCount ++;
+
+	deb_data("- Exit %s Function -\n",__FUNCTION__);
+
+	// avoid race with setfreq
+exit:
+	up(&PDC->tunerLock);
+	return dwError;
+}
+
+
+DWORD DL_GetLocked(Bool *bLock)
+{
+	DWORD dwError;
+	BYTE    ucSlaveDemod=0;
+
+	down(&PDC->tunerLock);
+
+	if( bLock ) {
+		dwError= Demodulator_isLocked((Demodulator*) &PDC->Demodulator, ucSlaveDemod, bLock);
+	}
+	else {
+		dwError = Error_NULL_PTR;
+	}
+
+	up(&PDC->tunerLock);
+	return dwError;
+}
+
+
+DWORD DL_GetSignalStrength(u16 *strength)
+{
+	DWORD dwError = Error_NO_ERROR;
+	BYTE    ucSlaveDemod=0;
+	Byte 	str;
+	deb_data("- Enter %s Function -\n",__FUNCTION__);	 	
+
+	dwError = Demodulator_getSignalStrength((Demodulator*) &PDC->Demodulator, ucSlaveDemod, &str);
+
+	if( strength ) *strength = str;
+
+	return dwError;
+}
+
+DWORD DL_GetSignalQuality(u16 *squality)
+{
+	DWORD dwError = Error_NO_ERROR;
+	BYTE    ucSlaveDemod=0;
+	Byte 	str;
+	deb_data("- Enter %s Function -\n",__FUNCTION__);	 	
+
+	dwError = Demodulator_getSignalQuality((Demodulator*) &PDC->Demodulator, ucSlaveDemod, &str);
+
+	if( squality ) *squality = str;
+
+	return dwError;
+}
+
+
+DWORD DL_GetChannelStat(u32 *ber, u32 *berbits, u32 *ubc)
+{
+	DWORD dwError = Error_NO_ERROR;
+	BYTE    ucSlaveDemod=0;
+	ChannelStatistic stat;
+	deb_data("- Enter %s Function -\n",__FUNCTION__);	 	
+
+	dwError = Demodulator_getChannelStatistic((Demodulator*) &PDC->Demodulator, ucSlaveDemod, &stat);
+	// ignore error because saved value is returned in stat
+	if( ber ) *ber = stat.postVitErrorCount;
+	if( berbits ) *berbits = stat.postVitBitCount;
+	if( ubc ) *ubc = stat.abortCount;
+
+	return(dwError);
+}
+
+
+static DWORD DL_Initialize(
+	    void *      handle
+)
+{
+    	DWORD dwError = Error_NO_ERROR;  
+    
+     	dwError = DRV_Initialize(handle);   
+
+	return (dwError); 
+    
+}
+
+static DWORD DL_SetBusTuner(
+	 void * handle, 
+	 Word busId, 
+	 Word tunerId
+)
+{
+
+	DWORD dwError = Error_NO_ERROR;
+	
+    	dwError = DRV_SetBusTuner(handle, busId, tunerId);
+
+	return (dwError);
+
+}
+
+static DWORD  DL_GetEEPROMConfig(
+	 void *      handle
+)
+{   
+    DWORD dwError = Error_NO_ERROR;
+
+    dwError = DRV_GetEEPROMConfig(handle);
+
+    return(dwError);
+} 
+
+static DWORD DL_TunerWakeup(
+      void *     handle
+)
+{    
+	DWORD dwError = Error_NO_ERROR;
+
+	 dwError = DRV_TunerWakeup(handle);
+   
+    	return(dwError);
+}
+static DWORD  DL_IrTblDownload(
+      void *     handle
+)
+{
+        DWORD dwError = Error_NO_ERROR;
+
+	dwError = DRV_IrTblDownload(handle);
+
+        return(dwError);
+}
+
+
+DWORD DL_TunerPowerCtrl(u8 bPowerOn)
+{
+	DWORD dwError = Error_NO_ERROR;
+
+	deb_data("enter DL_TunerPowerCtrl:  bOn = %s\n", bPowerOn?"ON":"OFF");
+
+    	dwError = DRV_TunerPowerCtrl(PDC, 0, bPowerOn);
+
+    	return (dwError);
+}
+//EXPORT_SYMBOL(DL_TunerPowerCtrl);
+
+
+DWORD DL_ApCtrl (
+      Bool        bOn
+)
+{
+        DWORD dwError = Error_NO_ERROR;
+	BYTE    ucSlaveDemod=0;
+	//Bool bLock;
+
+	down(&PDC->powerLock);
+
+	deb_data("Enter DL_ApCtrl:  bOn = %s, use_cnt=%d\n", bOn?"ON":"OFF", PDC->power_use_count);
+
+	// implement power management based on reference counting
+	if( bOn ) PDC->power_use_count++;
+	else PDC->power_use_count--;
+	if( PDC->power_use_count < 0 ) PDC->power_use_count = 0;
+
+	if( bOn && PDC->power_use_count==1 ) {
+
+		deb_data("DL_ApCtrl: call DRV_ApCtrl(ON)\n");
+	    	dwError = DRV_ApCtrl (PDC, 0, 1);
+	}
+	else if( !bOn && PDC->power_use_count==0 ) {
+		deb_data("DL_ApCtrl: call DRV_ApCtrl(OFF)\n");
+
+	    	dwError = DRV_ApCtrl (PDC, 0, 0);
+		PDC->fc[ucSlaveDemod].ulDesiredFrequency = 0;
+		PDC->fc[ucSlaveDemod].ucDesiredBandWidth = 0;
+		PDC->fc[ucSlaveDemod].OvrFlwChk = 0;
+	}
+
+	up(&PDC->powerLock);
+
+	deb_data("Exit DL_ApCtrl:  bOn = %s, dwError = %d\n", bOn?"ON":"OFF", dwError);
+    	return(dwError);
+}
+
+// return 1 if the difference between freq1 & freq2 is smaller or equal than t.
+static inline int Is_Within_Tolerance(u32 freq1, u32 freq2, u32 t)
+{
+	u32 diff = (freq1>freq2)? (freq1-freq2) : (freq2-freq1);
+	if( diff<=t ) return 1;
+	else return 0;
+}
+
+
+DWORD DL_Tuner_SetFreq(u32 dwFreq,u8 ucBw)
+{
+
+	DWORD dwError = Error_NO_ERROR;
+	BYTE    ucSlaveDemod=0;
+	
+	deb_data("- Enter %s Function -\n",__FUNCTION__);
+	if ( (PDC->fc[ucSlaveDemod].ulDesiredFrequency!=dwFreq 
+		&& !Is_Within_Tolerance(PDC->fc[ucSlaveDemod].ulDesiredFrequency, dwFreq, 125) )
+			|| PDC->fc[ucSlaveDemod].ucDesiredBandWidth!=ucBw*1000) 
+	 	dwError = DRV_SetFreqBw(PDC, ucSlaveDemod, dwFreq, ucBw);
+	else
+		deb_data("     the same Frequency & BandWidth\n");
+	 
+    	return(dwError);	
+}
+
+DWORD DL_Tuner_SetBW(u8 ucBw)
+{
+	DWORD dwError = Error_NO_ERROR;
+	BYTE    ucSlaveDemod=0;
+	deb_data("- Enter %s Function -\n",__FUNCTION__);	 	
+	if (PDC->fc[ucSlaveDemod].ucDesiredBandWidth!=ucBw*1000)
+	 	dwError =  DRV_SetFreqBw(PDC, ucSlaveDemod, 0, ucBw);
+	else
+		deb_data("     the same BandWidth\n");
+
+	return(dwError);
+}
+
+DWORD DL_ReSetInterval(void)
+{
+         DWORD dwError = Error_NO_ERROR;
+
+
+         return(dwError);
+}
+
+DWORD DL_Reboot(void)
+{
+	DWORD dwError = Error_NO_ERROR;
+
+	deb_data("- Enter %s Function -\n",__FUNCTION__);	 	
+
+	dwError = DRV_Reboot(PDC);
+
+	return(dwError);
+}
+
+
+DWORD Device_init(struct usb_device *udev,struct usb_interface *uintf, PDEVICE_CONTEXT PDCs, Bool bBoot)
+{
+	 DWORD error = Error_NO_ERROR;
+	 BYTE filterIdx=0;
+	 udevs=udev;
+	 uintfs=uintf;
+	 PDC=PDCs;
+
+	deb_data("- Enter %s Function -\n",__FUNCTION__);
+
+	//************* Set Device init Info *************//
+	PDC->bEnterSuspend = false;
+    	PDC->bSurpriseRemoval = false;
+    	PDC->bDevNotResp = false;
+    	PDC->bSelectiveSuspend = false; 
+	PDC->bTunerPowerOff = false;
+
+	if (bBoot)
+	{
+		PDC->bSupportSelSuspend = false;
+		PDC->Demodulator.userData = (Handle)PDC;
+		PDC->Demodulator.chipNumber =1;
+		PDC->architecture=Architecture_DCA;
+		PDC->Demodulator.frequency[0] = 666000;
+		PDC->Demodulator.bandwidth[0] = 8000;
+		PDC->bIrTblDownload = false;
+		PDC->fc[0].tunerinfo.TunerId = 0;
+		PDC->fc[1].tunerinfo.TunerId = 0;
+		PDC->bDualTs=false;	
+        	PDC->FilterCnt = 0;
+		PDC->StreamType = StreamType_DVBT_DATAGRAM;
+		PDC->UsbCtrlTimeOut = 1;
+
+		//init_MUTEX(&PDC->powerLock);
+		//init_MUTEX(&PDC->tunerLock);
+		sema_init(&PDC->powerLock, 1);
+		sema_init(&PDC->tunerLock, 1);
+		
+		PDC->power_use_count = 0;
+
+		PDC->idVendor = udev->descriptor.idVendor;
+		PDC->idProduct = udev->descriptor.idProduct;
+
+		PDC->Demodulator.GPIO8Value[0] = 2;
+		PDC->Demodulator.GPIO8Value[1] = 2;
+
+		PDC->fc[0].AVerFlags = 0x00;
+		PDC->fc[1].AVerFlags = 0x00;
+		
+		//init_MUTEX(&PDC->regLock);
+		sema_init(&PDC->regLock, 1);
+	}
+	else {
+        	PDC->UsbCtrlTimeOut = 5;
+    	}//bBoot
+
+#ifdef AFA_USB_DEVICE 	
+	if (bBoot) {
+		//************* Set USB Info *************//
+		PDC->MaxPacketSize = 0x0200; //default USB2.0
+		PDC->UsbMode = (PDC->MaxPacketSize == 0x200)?0x0200:0x0110;  
+		deb_data("USB mode= 0x%x\n", PDC->UsbMode);
+
+		PDC->TsPacketCount = (PDC->UsbMode == 0x200)?TS_PACKET_COUNT_HI:TS_PACKET_COUNT_FU;
+		PDC->TsFrames = (PDC->UsbMode == 0x200)?TS_FRAMES_HI:TS_FRAMES_FU;
+		PDC->TsFrameSize = TS_PACKET_SIZE*PDC->TsPacketCount;
+		PDC->TsFrameSizeDw = PDC->TsFrameSize/4;
+	}
+	PDC->bEP12Error = false;
+    	PDC->bEP45Error = false; 
+    	PDC->ForceWrite = false;    
+    	PDC->ulActiveFilter = 0;
+#else
+    	PDC->bSupportSuspend = false; 
+#endif//AFA_USB_DEVICE
+	
+#ifdef AFA_USB_DEVICE
+	if(bBoot)
+    	{
+		//patch for eeepc
+        	error = DL_SetBusTuner (PDC, Bus_USB, Tuner_Afatech_AF9007);
+        	PDC->UsbCtrlTimeOut = 5;
+        
+        	error = DL_SetBusTuner (PDC, Bus_USB, Tuner_Afatech_AF9007);
+        	if (error)
+        	{
+            		deb_data("First DL_SetBusTuner fail : 0x%08x\n",error );
+            		goto Exit;
+        	}
+
+        	error =DL_GetEEPROMConfig(PDC);
+        	if (error)
+        	{
+            		deb_data("DL_GetEEPROMConfig fail : 0x%08x\n", error);
+            		goto Exit;
+        	}
+	}//bBoot
+	
+	error = DL_SetBusTuner(PDC, Bus_USB, PDC->fc[0].tunerinfo.TunerId);
+    	if (error)
+    	{
+        	deb_data("DL_SetBusTuner fail!\n");
+        	goto Exit;
+    	}
+
+	if(PDC->Demodulator.chipNumber == 1 && PDC->Demodulator.booted) //warm-boot/(S1)
+	{
+		error = DL_TunerWakeup(PDC);
+	}
+	if(error) deb_data("DL_NIMReset or DL_NIMSuspend or DL_TunerWakeup fail!\n"); 
+
+	error = DL_Initialize(PDC);
+    	if (error) 
+    	{
+        	deb_data("DL_Initialize fail! 0x%08x\n", error);
+        	goto Exit;
+    	}
+	
+	if (PDC->bIrTblDownload) 
+    	{
+        	error = DL_IrTblDownload(PDC);
+       	 	if (error) deb_data("DL_IrTblDownload fail");
+    	}
+
+    	//for (filterIdx=0; filterIdx< pdc->Demodulator.chipNumber; filterIdx++) 
+    	//{  
+		
+
+        	if (bBoot)
+        	{
+			//Bool bLock;
+            		error = DRV_ApCtrl(PDC, filterIdx, false);
+            		if (error) deb_data("%d: DRV_ApCtrl Fail!\n", filterIdx);
+        	} 
+
+	deb_data("        %s success!! \n",__FUNCTION__);
+
+Exit:
+#endif //AFA_USB_DEVICE
+
+	return (error);
+}
+//EXPORT_SYMBOL(Device_init);
diff --git a/drivers/media/dvb/dvb-usb/a867_af903x-fe.c b/drivers/media/dvb/dvb-usb/a867_af903x-fe.c
new file mode 100644
index 0000000..3c6b9fb
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_af903x-fe.c
@@ -0,0 +1,865 @@
+#include <linux/sched.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/version.h>
+
+#include "a867_af903x.h"
+#include "dvb_frontend.h"
+#include "a867_standard.h"
+
+#define A333_FREQ_MIN	44250000
+#define A333_FREQ_MAX	867250000
+
+DEFINE_MUTEX(mutex);
+
+static int alwayslock; // default to 0
+module_param(alwayslock, int, 0644);
+MODULE_PARM_DESC(alwayslock, "Whether to always report channel as locked (default:no).");
+
+
+struct af903xm_state {
+	struct dvb_frontend demod;
+	uint32_t current_bandwidth;
+	uint32_t current_frequency;
+
+	struct completion thread_exit;
+	int thread_should_stop;
+	atomic_t thread_created;
+
+	u32 ucblocks;
+	u32 ber;
+	u16 strength;
+	
+	int locked;
+};
+
+int test_map_snr(u32 snr_data, u16 *snr, u16 *maxsnr)
+{
+	Dword error = 0;
+	Dword snr_value = 0;
+	Byte constellation = 0;
+	Byte transmission_mode = 0;
+
+	*maxsnr = 0;
+	*snr = 0;
+
+    /** Get constellation type */
+    error = Standard_readRegisterBits ((Demodulator *)&PDC->Demodulator, PDC->Map.RF_SW_HOST, 
+										Processor_OFDM, g_reg_tpsd_const, reg_tpsd_const_pos, reg_tpsd_const_len, &constellation);
+    if (error) goto exit;
+
+    /** Get FFT mode */
+    error = Standard_readRegisterBits ((Demodulator *)&PDC->Demodulator, PDC->Map.RF_SW_HOST, 
+										Processor_OFDM, g_reg_tpsd_txmod, reg_tpsd_txmod_pos, reg_tpsd_txmod_len, &transmission_mode);
+    if (error) goto exit;
+
+	// Adjust snr data by transmission mode
+	if (transmission_mode == 0)
+		snr_value = snr_data * 4;
+	else if (transmission_mode == 2)	
+		snr_value = snr_data * 2;
+	else
+		snr_value = snr_data;
+
+   if( constellation == 0) //Constellation_QPSK
+   {
+           if(snr_value < 0xB4771)    *snr = 0;
+           else if(snr_value < 0xC1AED)   *snr = 1;
+           else if(snr_value < 0xD0D27)   *snr = 2;
+           else if(snr_value < 0xE4D19)   *snr = 3;
+           else if(snr_value < 0xE5DA8)   *snr = 4;
+           else if(snr_value < 0x107097)   *snr = 5;
+           else if(snr_value < 0x116975)   *snr = 6;
+           else if(snr_value < 0x1252D9)   *snr = 7;
+           else if(snr_value < 0x131FA4)   *snr = 8;
+           else if(snr_value < 0x13D5E1)   *snr = 9;
+           else if(snr_value < 0x148E53)   *snr = 10;
+           else if(snr_value < 0x15358B)   *snr = 11;
+           else if(snr_value < 0x15DD29)   *snr = 12;
+           else if(snr_value < 0x168112)   *snr = 13;
+           else if(snr_value < 0x170B61)   *snr = 14;
+           else if(snr_value < 0x17A532)   *snr = 15;
+           else if(snr_value < 0x180F94)   *snr = 16;
+           else if(snr_value < 0x186ED2)   *snr = 17;
+           else if(snr_value < 0x18B271)   *snr = 18;
+           else if(snr_value < 0x18E118)   *snr = 19;
+           else if(snr_value < 0x18FF4B)   *snr = 20;
+           else if(snr_value < 0x190AF1)   *snr = 21;
+           else if(snr_value < 0x191451)   *snr = 22;
+           else   *snr = 23;
+	   *maxsnr = 23;
+    }
+    else if ( constellation == 1) //Constellation_16QAM
+    {
+        if(snr_value < 0x4F0D5)    *snr = 0;
+           else if(snr_value < 0x5387A)   *snr = 1;
+           else if(snr_value < 0x573A4)   *snr = 2;
+           else if(snr_value < 0x5A99E)   *snr = 3;
+           else if(snr_value < 0x5CC80)   *snr = 4;
+           else if(snr_value < 0x5EB62)   *snr = 5;
+           else if(snr_value < 0x5FECF)   *snr = 6;
+           else if(snr_value < 0x60B80)   *snr = 7;
+           else if(snr_value < 0x62501)   *snr = 8;
+           else if(snr_value < 0x64865)   *snr = 9;
+           else if(snr_value < 0x69604)   *snr = 10;
+           else if(snr_value < 0x6F356)   *snr = 11;
+           else if(snr_value < 0x7706A)   *snr = 12;
+           else if(snr_value < 0x804D3)   *snr = 13;
+           else if(snr_value < 0x89D1A)   *snr = 14;
+           else if(snr_value < 0x93E3D)   *snr = 15;
+           else if(snr_value < 0x9E35D)   *snr = 16;
+           else if(snr_value < 0xA7C3C)   *snr = 17;
+           else if(snr_value < 0xAFAF8)   *snr = 18;
+           else if(snr_value < 0xB719D)   *snr = 19;
+           else if(snr_value < 0xBDA6A)   *snr = 20;
+           else if(snr_value < 0xC0C75)   *snr = 21;
+           else if(snr_value < 0xC3F7D)   *snr = 22;
+           else if(snr_value < 0xC5E62)   *snr = 23;
+           else if(snr_value < 0xC6C31)   *snr = 24;
+           else if(snr_value < 0xC7925)   *snr = 25;
+           else    *snr = 26;
+	   *maxsnr = 26;
+    }
+    else if ( constellation == 2) //Constellation_64QAM
+    {
+        if(snr_value < 0x256D0)    *snr = 0;
+           else if(snr_value < 0x27A65)   *snr = 1;
+           else if(snr_value < 0x29873)   *snr = 2;
+           else if(snr_value < 0x2B7FE)   *snr = 3;
+           else if(snr_value < 0x2CF1E)   *snr = 4;
+           else if(snr_value < 0x2E234)   *snr = 5;
+           else if(snr_value < 0x2F409)   *snr = 6;
+           else if(snr_value < 0x30046)   *snr = 7;
+           else if(snr_value < 0x30844)   *snr = 8;
+           else if(snr_value < 0x30A02)   *snr = 9;
+           else if(snr_value < 0x30CDE)   *snr = 10;
+           else if(snr_value < 0x31031)   *snr = 11;
+           else if(snr_value < 0x3144C)   *snr = 12;
+           else if(snr_value < 0x315DD)   *snr = 13;
+           else if(snr_value < 0x31920)   *snr = 14;
+           else if(snr_value < 0x322D0)   *snr = 15;
+           else if(snr_value < 0x339FC)   *snr = 16;
+           else if(snr_value < 0x364A1)   *snr = 17;
+           else if(snr_value < 0x38BCC)   *snr = 18;
+           else if(snr_value < 0x3C7D3)   *snr = 19;
+           else if(snr_value < 0x408CC)   *snr = 20;
+           else if(snr_value < 0x43BED)   *snr = 21;
+           else if(snr_value < 0x48061)   *snr = 22;
+           else if(snr_value < 0x4BE95)   *snr = 23;
+           else if(snr_value < 0x4FA7D)   *snr = 24;
+           else if(snr_value < 0x52405)   *snr = 25;
+           else if(snr_value < 0x5570D)   *snr = 26;
+           else if(snr_value < 0x59FEB)   *snr = 27;
+           else if(snr_value < 0x5BF38)   *snr = 28;
+           else    *snr = 29;
+	   *maxsnr = 29;
+    }
+	
+	
+exit:
+	
+	deb_data(" %s Function, SNR = %d -\n",__FUNCTION__, *snr);
+	return error;
+}
+
+int test_read_strength_dbm(struct dvb_frontend *demod, u32 *str)
+{
+	
+	Dword dwError = 0;
+	Byte str_dbm = 0;
+
+   // Read StrengthDBM
+    dwError = Standard_readRegister ((Demodulator *)&PDC->Demodulator, PDC->Map.RF_SW_HOST, Processor_OFDM, est_rf_level_dbm, &str_dbm);
+    if(dwError) {
+	    deb_data("%s error, ret=0x%x\n", __FUNCTION__, dwError);
+		*str = 0;	
+		goto exit;
+    }
+ 
+	deb_data(" %s Function, StrengthDbm = %d -\n",__FUNCTION__, str_dbm);
+
+exit:
+	return dwError;
+}
+
+
+int test_read_snr(struct dvb_frontend *demod, u32 *snr_data)
+{
+	Byte check1 = 0x0, check2 = 0x0;
+	Byte base1  = 0x0, base2  = 0x0;
+	Byte snr1   = 0x0, snr2   = 0x0, snr3=0x0;			
+	u16 baseAddr = 0x0;
+
+	*snr_data = 0x000000;
+
+    Standard_readRegister ((Demodulator *)&PDC->Demodulator, PDC->Map.RF_SW_HOST, Processor_OFDM, 0xf21b, &check1);
+    Standard_readRegister ((Demodulator *)&PDC->Demodulator, PDC->Map.RF_SW_HOST, Processor_OFDM, 0xf999, &check2);
+
+	deb_data(" %s Function, check1=0x%x -\n",__FUNCTION__, check1);
+
+	if(check1 != 0x0c || check2 != 0x01)	return 1;
+	
+    Standard_readRegister ((Demodulator *)&PDC->Demodulator, PDC->Map.RF_SW_HOST, Processor_OFDM, 0x418b, &base1);
+    Standard_readRegister ((Demodulator *)&PDC->Demodulator, PDC->Map.RF_SW_HOST, Processor_OFDM, 0x418c, &base2);
+
+	baseAddr = (base1<<8) + base2 + 0x2C;
+
+	deb_data(" %s Function, base1 = 0x%x -\n",__FUNCTION__, base1);
+	deb_data(" %s Function, base2 = 0x%x -\n",__FUNCTION__, base2);
+	deb_data(" %s Function, (base1<<8) + base2 + 0x2c = baseAddr = 0x%x -\n",__FUNCTION__, baseAddr);
+	
+    Standard_readRegister ((Demodulator *)&PDC->Demodulator, PDC->Map.RF_SW_HOST, Processor_OFDM, baseAddr,   &snr1);
+    Standard_readRegister ((Demodulator *)&PDC->Demodulator, PDC->Map.RF_SW_HOST, Processor_OFDM, baseAddr+1, &snr2);
+    Standard_readRegister ((Demodulator *)&PDC->Demodulator, PDC->Map.RF_SW_HOST, Processor_OFDM, baseAddr+2, &snr3);
+
+	*snr_data = (snr3<<16)+(snr2<<8)+(snr1);
+
+	deb_data(" %s Function, snr data = 0x%x -\n",__FUNCTION__, *snr_data);
+
+	return 0;
+
+}
+
+
+
+/* unused
+static int af903x_set_bandwidth(struct dvb_frontend *demod, u8 bw_idx)
+{
+	struct af903xm_state *state = demod->demodulator_priv;
+
+	deb_data("- Enter %s Function - bandwidth= %d \n",__FUNCTION__,bw_idx);
+
+//	state->current_bandwidth = bw_idx;
+
+	DL_Tuner_SetBW(bw_idx);
+
+	return 0;
+}
+*/
+
+static void af903x_set_channel(struct af903x_ofdm_channel *ch)
+{
+	deb_data("- Enter %s Function - RF=%d, BW=%d\n",__FUNCTION__,ch->RF_kHz,ch->Bw);
+
+	DL_Tuner_SetFreq(ch->RF_kHz,ch->Bw);
+
+}
+
+static int af903x_tune(struct dvb_frontend *demod, struct af903x_ofdm_channel *ch)
+{
+	if (ch != NULL)
+		af903x_set_channel(ch);
+
+	return 0;
+}
+
+static int af903x_init(struct dvb_frontend *demod)
+{
+	int ret = 0;
+	struct af903xm_state *state = demod->demodulator_priv;
+	deb_data("- Enter %s Function -\n",__FUNCTION__);
+ 
+	ret = usb_autopm_get_interface(uintfs);
+	if(ret) {
+		deb_data("%s calling usb_autopm_get_interface failed with %d\n", __FUNCTION__, ret);
+		return ret;
+	}
+
+	ret = DL_ApCtrl(1);
+	if(ret) {
+		deb_data("af903x_init Fail: 0x%04X", ret);
+		return -EIO;
+	}
+
+	// reset statistics
+	state->ber = 0;
+	state->ucblocks = 0;
+	state->strength = 0;
+	state->locked = 0;
+	
+	// reset values
+	state->current_frequency = 0;
+	state->current_bandwidth = 0;
+
+	af903x_start_monitor_thread(demod);
+
+	deb_data("- Exit %s Function -\n",__FUNCTION__);
+	return 0;
+}
+
+static int af903x_sleep(struct dvb_frontend *demod)
+{
+	int error;
+        deb_data("Enter %s Function\n",__FUNCTION__);
+
+	af903x_stop_monitor_thread(demod);
+
+        error = DL_ApCtrl(0);
+        if (error) {
+		deb_data("%s calling DL_ApCtrl error : 0x%x\n", __FUNCTION__, error);
+		return -EIO;
+	}
+
+	usb_autopm_put_interface(uintfs);	
+
+	deb_data("- Exit %s Function -\n",__FUNCTION__);
+	return 0;
+}
+static int af903x_identify(struct af903xm_state *state)
+{
+	return 0;
+}
+
+static int af903x_get_frontend(struct dvb_frontend* fe)
+{
+	struct af903xm_state *state = fe->demodulator_priv;
+	struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
+
+	deb_data("- Enter %s Function -\n",__FUNCTION__);
+	fep->frequency = state->current_frequency;
+	fep->inversion = INVERSION_AUTO;
+	fep->bandwidth_hz = state->current_bandwidth;
+	return 0;
+}
+
+static int af903x_set_frontend(struct dvb_frontend* fe)
+{
+	struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
+	struct af903xm_state *state = fe->demodulator_priv;
+	struct af903x_ofdm_channel ch;
+	u16 bw=0;
+	int ret=0;
+
+	deb_data("- Enter %s Function -\n",__FUNCTION__);
+
+
+	if( fep->frequency < A333_FREQ_MIN || fep->frequency > A333_FREQ_MAX ) {
+		deb_data("- %s freq=%d Hz out of range(%d~%d)-\n",__FUNCTION__, fep->frequency, 
+				A333_FREQ_MIN, A333_FREQ_MAX);
+		// set to zero so we can report unlock to AP, because return -EINVAL apparently 
+		// does not stop AP from continuing tuning.
+		state->current_frequency = 0;
+		return -EINVAL;
+	}
+
+	switch(fep->bandwidth_hz) {
+	case 8000000: bw=8; break;
+	case 7000000: bw=7; break;
+	case 6000000: bw=6; break;
+
+	//case 6: 
+	//case 7:
+	//case 8:
+	//	bw = fep->u.ofdm.bandwidth;
+	//	deb_data("- %s wrong bw value: %d -\n",__FUNCTION__, fep->u.ofdm.bandwidth);
+	//	break;
+	default:
+
+		deb_data("- %s unknown bw value: %d -\n",__FUNCTION__, fep->bandwidth_hz);
+		return -EINVAL;
+	}
+
+
+	ch.RF_kHz           = fep->frequency / 1000;
+	ch.Bw               = bw;
+	deb_data("- %s freq=%d KHz, bw=%d MHz -\n",__FUNCTION__, ch.RF_kHz,  ch.Bw);
+
+	state->current_bandwidth = fep->bandwidth_hz;
+	state->current_frequency = fep->frequency;
+
+	ret = af903x_tune(fe, &ch);
+
+	// start monitor thread if not yet.
+	af903x_start_monitor_thread(fe);
+	
+	return ret;
+}
+
+static int af903x_read_status(struct dvb_frontend *fe, fe_status_t *stat)
+{
+	//DWORD dwError;
+	Bool bLock;
+	struct af903xm_state *state = fe->demodulator_priv;
+	//u32	snr_data;
+	//u32 str_dbm_data;
+
+	deb_data("- Enter %s Function -\n",__FUNCTION__);
+	*stat = 0;
+
+#if !USE_MONITOR_TH	
+	{	
+	unsigned long j = (HZ*500)/1000;
+	set_current_state(TASK_UNINTERRUPTIBLE);
+	schedule_timeout(j);
+	}
+	dwError = DL_GetLocked(&bLock);
+	if( dwError ) {
+		deb_data("- Function %s error=0x%x\n",__FUNCTION__, dwError);	
+		return -EIO;
+	}
+#else
+	if( alwayslock ) {
+		bLock = True;
+	}
+	else {
+		bLock = state->locked;
+	}
+#endif
+	if( bLock ) {
+		*stat |= FE_HAS_SIGNAL;
+		*stat |= FE_HAS_CARRIER;
+		*stat |= FE_HAS_LOCK;
+		*stat |= FE_HAS_VITERBI;
+		*stat |= FE_HAS_SYNC;
+	}
+
+
+	// report unlock if frequency is out of bound
+	if( 0==state->current_frequency ) {
+		*stat = 0;
+	}
+	
+#if ENABLE_TEST_FUNCTION
+	test_read_snr(fe, &snr_data);
+	test_map_snr(snr_data, &snr);
+	test_read_strength_dbm(fe, &str_dbm_data);
+#endif
+
+	deb_data("- Exit %s Function, status=0x%x -\n",__FUNCTION__, *stat);
+	return 0;
+}
+
+static int af903x_read_ubc(struct dvb_frontend *fe, u32* ucblocks)
+{
+	struct af903xm_state *state = fe->demodulator_priv;
+	//DWORD dwError;
+	//Bool bLock;
+
+	deb_data("- Enter %s Function -\n",__FUNCTION__);	
+
+#if !USE_MONITOR_TH
+	DL_GetChannelStat(NULL, NULL, ucblocks);
+
+	dwError = DL_GetLocked(&bLock);
+	// if signal is not locked, fill with 65535 to indicate loss of signal
+	if( dwError || !bLock ) {
+		deb_data("- Function %s lost lock , error=0x%x, bLock=%d -\n",__FUNCTION__, dwError, bLock);	
+		if( ucblocks ) *ucblocks = 65535;
+		return 0;
+	}
+#else
+	if( ucblocks ) *ucblocks = state->ucblocks;
+#endif
+
+	deb_data("- Exit %s Function, ubc=%d -\n",__FUNCTION__, ucblocks? *ucblocks:-1);
+	return 0;
+}
+
+
+static int af903x_read_ber(struct dvb_frontend *fe, u32 *ber)
+{
+	struct af903xm_state *state = fe->demodulator_priv;
+	//DWORD dwError;
+	//u32 berbits;
+	//Bool bLock;
+	deb_data("- Enter %s Function -\n",__FUNCTION__);	
+
+#if !USE_MONITOR_TH
+	DL_GetChannelStat(ber, &berbits, NULL);
+
+	// if signal is not locked, fill BER with BER total bits
+	dwError = DL_GetLocked(&bLock);
+	if( dwError || !bLock ) {
+		deb_data("- Function %s lost lock , error=0x%x, bLock=%d -\n",__FUNCTION__, dwError, bLock);	
+		if( ber ) *ber = berbits;
+		return 0;
+	}
+#else
+	if( ber ) *ber = state->ber;
+#endif
+	//
+	deb_data("- Exit %s Function , ber=%d-\n",__FUNCTION__, ber? *ber:(-1));
+	return 0;
+}
+
+
+static int af903x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
+{
+	DWORD dwError;
+	Bool bLock;
+	Byte value;
+
+	deb_data("- Enter %s Function -\n",__FUNCTION__);	
+
+	dwError = Standard_readRegister ((Demodulator *)&PDC->Demodulator, PDC->Map.RF_SW_HOST, Processor_OFDM, signal_strength, &value);
+	//dwError = DL_GetSignalStrength(strength);
+	if( dwError ) {
+		deb_data("- Function %s error reading signal strength -\n",__FUNCTION__);	
+		*strength = 0;
+		return 1;
+	}
+
+	dwError = DL_GetLocked(&bLock);
+	if( dwError ) {
+		deb_data("- Function %s error reading signal quality : lost lock -\n",__FUNCTION__);	
+		*strength = 0;
+		return 1;
+	}
+	
+	deb_data("- Exit %s Function, signal strength (0-100)=%d -\n",__FUNCTION__, value);	
+
+	// 16 bit output
+	*strength = value * (0xffff / 100);
+
+	return 0;
+}
+
+/*
+static int af903x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
+{
+	struct af903xm_state *state = fe->demodulator_priv;
+	//DWORD dwError;
+	// Bool bLock;
+	deb_data("- Enter %s Function -\n",__FUNCTION__);	
+
+#if !USE_MONITOR_TH
+	DL_GetSignalStrength(strength);
+
+	dwError = DL_GetLocked(&bLock);
+	if( dwError || !bLock ) {
+		deb_data("- Function %s lost lock , error=0x%x, bLock=%d -\n",__FUNCTION__, dwError, bLock);	
+		if( strength ) *strength = 0;
+		return 0;
+	}
+#else
+	if( strength ) *strength = state->strength;
+#endif
+	
+	deb_data("- Exit %s Function, strength=%d -\n",__FUNCTION__, strength? *strength:-1);	
+	return 0;
+}
+*/
+
+static int af903x_read_snr(struct dvb_frontend* fe, u16 *snr)
+{
+	Byte value_7_0 = 0;
+	Byte value_15_8 = 0;
+	Byte value_23_16 = 0;
+	//Dword addr = 0;
+	Dword dwError = 0;
+	u32 snr_val=0;
+	u16 snr_max=0;
+	u32 snr_16bit = 0;
+
+	*snr = 0;
+
+	deb_data("- Enter %s Function -\n",__FUNCTION__);
+
+	dwError = Standard_readRegister ((Demodulator *)&PDC->Demodulator, PDC->Map.RF_SW_HOST, Processor_OFDM, qnt_vbc_err_7_0, &value_7_0);
+	if(dwError)	{
+		deb_data("- Function %s  qnt_vbc_err_7_0 register read fail ! -\n",__FUNCTION__);
+		return 1;
+	}
+
+	dwError = Standard_readRegister ((Demodulator *)&PDC->Demodulator, PDC->Map.RF_SW_HOST, Processor_OFDM, qnt_vbc_err_15_8, &value_15_8);
+	if(dwError)	{
+		deb_data("- Function %s  qnt_vbc_err_15_8 register read fail ! -\n",__FUNCTION__);
+		return 1;
+	}
+
+	dwError = Standard_readRegister ((Demodulator *)&PDC->Demodulator, PDC->Map.RF_SW_HOST, Processor_OFDM, qnt_vbc_err_23_16, &value_23_16);
+	if(dwError)	{
+		deb_data("- Function %s  qnt_vbc_err_23_16 register read fail ! -\n",__FUNCTION__);
+		return 1;
+	}
+
+	snr_val = (value_23_16 << 16) + (value_15_8 << 8) + value_7_0;
+	deb_data("- Function %s SNR row val 0x%x -\n",__FUNCTION__,snr_val);
+
+	dwError = test_map_snr(snr_val, snr, &snr_max);
+	if(dwError)	{
+		deb_data("- Function %s  map_snr fail ! -\n",__FUNCTION__);
+		*snr = 0;
+		return 1;
+	}
+	snr_16bit = (0xffff * *snr) / snr_max;
+	if (snr_16bit > 0xffff) 
+		snr_16bit = 0xffff;
+
+	deb_data("- Exit %s SNR %d dB , %d 16bit -\n",__FUNCTION__,*snr,snr_16bit);
+
+	if (dvb_usb_af903x_snrdb == 0)
+		*snr = snr_16bit;
+
+	return 0;
+
+}
+
+
+
+static void af903x_release(struct dvb_frontend *demod)
+{
+	struct af903xm_state *st = demod->demodulator_priv;
+	deb_data("- Enter %s Function -\n",__FUNCTION__);
+	af903x_stop_monitor_thread(demod);
+	kfree(st);
+}
+
+static struct dvb_frontend_ops af903x_ops = {
+	.delsys = { SYS_DVBT },
+	.info = {
+		.name = "A867 USB DVB-T",
+		.type = FE_OFDM,
+		.frequency_min      = A333_FREQ_MIN,
+		.frequency_max      = A333_FREQ_MAX,
+		.frequency_stepsize = 62500,
+		.caps = FE_CAN_INVERSION_AUTO |
+			FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
+			FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
+			FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
+			FE_CAN_TRANSMISSION_MODE_AUTO |
+			FE_CAN_GUARD_INTERVAL_AUTO |
+			FE_CAN_RECOVER |
+			FE_CAN_HIERARCHY_AUTO,
+	},
+
+	.release              = af903x_release,
+
+	.init                 = af903x_init,
+	.sleep                = af903x_sleep,
+
+	.set_frontend         = af903x_set_frontend,
+	.get_frontend         = af903x_get_frontend,
+
+	.read_status          = af903x_read_status,
+	.read_ber             = af903x_read_ber,
+	.read_signal_strength = af903x_read_signal_strength,
+	.read_snr             = af903x_read_snr,
+//	.read_snr             = af903x_read_signal_quality,
+	.read_ucblocks	      = af903x_read_ubc,
+};
+
+static struct dvb_frontend_ops af903x_ops;
+struct dvb_frontend * af903x_attach(u8 tmp)
+{
+	struct dvb_frontend *demod;
+	struct af903xm_state *st;
+
+	deb_data("- Enter %s Function -\n",__FUNCTION__);	
+	st = kzalloc(sizeof(struct af903xm_state), GFP_KERNEL);
+	if (st == NULL)
+		return NULL;
+
+	demod                   = &st->demod;
+	demod->demodulator_priv = st;
+	memcpy(&st->demod.ops, &af903x_ops, sizeof(struct dvb_frontend_ops));
+	atomic_set(&st->thread_created, 0);
+
+	af903x_identify(st); 
+
+	return demod;
+}
+
+
+static Dword Monitor_GPIO8(void)
+{
+    Dword error = Error_NO_ERROR;
+    Byte PinValue;
+
+    if ( PDC->idProduct!=0xa333 ) {
+	goto exit;
+    }
+
+    if( PDC->fc[0].AVerFlags&0x04 ) {
+	deb_data("%s, skip read GPIO8\n", __FUNCTION__);
+	PDC->fc[0].AVerFlags &= ~(0x04);
+	goto exit;
+    }
+
+    // read GPIO8
+    error = Standard_readRegister ((Demodulator *)&PDC->Demodulator, 
+			PDC->Map.RF_SW_HOST, 
+			Processor_LINK, 
+			PDC->Map.GPIO_STR_i, 
+			&PinValue);
+    if( error ) goto exit;
+
+    if( PDC->Demodulator.GPIO8Value[0] != PinValue ) {
+
+        if( PinValue == 1 ) {
+	    error = Standard_writeRegister ( (Demodulator *)&PDC->Demodulator, 
+			PDC->Map.RF_SW_HOST, 
+			Processor_LINK, 
+			PDC->Map.GPIO_UHF_o, 
+			1);
+	    error = Standard_writeRegister ( (Demodulator *)&PDC->Demodulator, 
+			PDC->Map.RF_SW_HOST, 
+			Processor_LINK, 
+			PDC->Map.GPIO_VHF_o, 
+			1);
+        }
+        else if (PDC->fc[0].ulDesiredFrequency > 300000)
+        {
+	     //UHF
+	    error = Standard_writeRegister ( (Demodulator *)&PDC->Demodulator, PDC->Map.RF_SW_HOST, 
+					Processor_LINK, PDC->Map.GPIO_UHF_o, 1);
+	    error = Standard_writeRegister ( (Demodulator *)&PDC->Demodulator, PDC->Map.RF_SW_HOST, 
+					Processor_LINK, PDC->Map.GPIO_VHF_o, 0);
+        }
+        else
+        {
+	    //VHF
+	    error = Standard_writeRegister ( (Demodulator *)&PDC->Demodulator, PDC->Map.RF_SW_HOST, 
+					Processor_LINK, PDC->Map.GPIO_UHF_o, 0);
+	    error = Standard_writeRegister ( (Demodulator *)&PDC->Demodulator, PDC->Map.RF_SW_HOST, 
+					Processor_LINK, PDC->Map.GPIO_VHF_o, 1);
+        }
+	 PDC->Demodulator.GPIO8Value[0] = PinValue;
+    }
+    else if( PinValue == 0 ) { // pin value remains 0
+	if( PDC->Demodulator.channelStatistic[0].abortCount > 2500  &&
+		(PDC->fc[0].AVerFlags&0x08)==0 ) {
+		// pull high GPIO8
+		PDC->fc[0].AVerFlags |= 0x08; // pull H flag bit 3
+		Demodulator_writeRegister( (Demodulator *)&PDC->Demodulator, 0, Processor_LINK, PDC->Map.GPIO_STR_en, 1);
+		Demodulator_writeRegister( (Demodulator *)&PDC->Demodulator, 0, Processor_LINK, PDC->Map.GPIO_STR_on, 1);
+		Demodulator_writeRegister( (Demodulator *)&PDC->Demodulator, 0, Processor_LINK, PDC->Map.GPIO_STR_o, 1);
+	}
+    }
+    else if( PinValue == 1 ) { // pin value remains 1
+	if( PDC->Demodulator.channelStatistic[0].abortCount < 2500 &&
+		(PDC->fc[0].AVerFlags&0x08)!=0 ) {
+		// after manual tune and result is good
+		PDC->fc[0].AVerFlags &= ~(0x08);
+	}
+    }
+
+exit:
+    return error;
+}
+
+static int af903x_monitor_thread_func(void *data)
+{
+	struct dvb_frontend *demod = data;
+	struct af903xm_state *state = demod? demod->demodulator_priv:NULL;
+	const char *thread_name = "A867_monitor_thread";
+	unsigned long loopcount = 0;
+	Bool bLock = True;
+
+	deb_data("- Enter %s Function -\n",__FUNCTION__);
+	if( !state ) return -1;
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,39)
+	lock_kernel();
+#else
+	mutex_lock(&mutex);
+#endif
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,61)
+	daemonize();
+	sigfillset(&current->blocked);
+	sprintf(current->comm, "%s", thread_name);
+#else
+	daemonize("%s", thread_name);
+	allow_signal(SIGTERM);
+#endif
+	siginitsetinv(&current->blocked, sigmask(SIGKILL)|sigmask(SIGINT)|\
+			sigmask(SIGTERM));
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,39)
+	unlock_kernel();
+#else
+	mutex_unlock(&mutex);
+#endif
+	while(!state->thread_should_stop && !signal_pending(current)) {
+	
+		//DWORD dwError;
+		u32 ber, berbits, ucblocks;
+		u16 strength;
+
+		loopcount++;
+
+		// sleep for 500 mili seconds
+		set_current_state(TASK_UNINTERRUPTIBLE);
+		schedule_timeout((HZ*500)/1000);
+
+		// monitor lock and return lock status
+		// reacquire channel if lock is lost for quiet a while
+		#if 1
+			DL_MonitorReception(&bLock);
+			state->locked = bLock? 1:0;
+		#endif //0
+		// obtain statistics
+		// do this every 2 loops, which is 1 second
+		if( loopcount%2 == 1  ) {
+			// do not do this if bLock is false, because 
+			//    1. this is not necessary
+			//    2. frequency is not yet set
+			if( bLock ) {
+				DL_GetChannelStat(&ber, &berbits, &ucblocks);
+				DL_GetSignalStrength(&strength);
+
+				// sometimes strength can drop to zero while demod
+				// is still pumping out stream. In which case we
+				// maintain strength to a locked level because 
+				// some AP(kaffeine) seem to rely on strength
+				// for signs of signal lock.
+				//if( strength==0 ) strength = 10;
+				
+				strength = (strength*65535/100);
+			}
+			else {
+				DL_GetChannelStat(NULL, &berbits, NULL);
+				ber = berbits;
+				ucblocks = 65535;
+				strength = 0;
+			}
+
+			state->ber = ber;
+			state->ucblocks = ucblocks;
+			state->strength = strength;
+		}
+		// monitor GPIO8
+	        Monitor_GPIO8();
+	}
+
+	//Firstly, clear thread_created flag so monitor thead can be restored later.
+	atomic_set(&state->thread_created, 0);
+	//Secondly, clear current frequency so we can depent on later set_frequency to restore
+	//this thread.
+	state->current_frequency = 0;
+
+	deb_data("- Exit %s Function -\n",__FUNCTION__);
+	complete_and_exit(&state->thread_exit, 0);
+}
+
+void af903x_start_monitor_thread(struct dvb_frontend *demod)
+{
+	struct af903xm_state *st = demod? demod->demodulator_priv:NULL;
+	if( !st ) return;
+
+#if USE_MONITOR_TH
+	// if st->thread_created is already 1, then skip thread creation
+	if( atomic_add_unless(&st->thread_created, 1, 1) ) {
+		st->thread_should_stop = 0;
+		init_completion(&st->thread_exit); 
+		kernel_thread(af903x_monitor_thread_func, st, 0);
+	}
+#endif //USE_MONITOR_TH
+
+}
+
+void af903x_stop_monitor_thread(struct dvb_frontend *demod)
+{
+	struct af903xm_state *st = demod? demod->demodulator_priv:NULL;
+	deb_data("- Enter %s Function -\n",__FUNCTION__);
+	if( !st ) return;
+
+#if USE_MONITOR_TH
+	// if st->thread_created is alread 0, then skip thread destruction
+	if( atomic_add_unless(&st->thread_created, -1, 0) ) {
+		st->thread_should_stop = 1;
+		wait_for_completion(&st->thread_exit);
+	}
+#endif //USE_MONITOR_TH
+	deb_data("- Exit %s Function -\n",__FUNCTION__);
+}
+
diff --git a/drivers/media/dvb/dvb-usb/a867_af903x-ioctl.h b/drivers/media/dvb/dvb-usb/a867_af903x-ioctl.h
new file mode 100644
index 0000000..14b6df9
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_af903x-ioctl.h
@@ -0,0 +1,29 @@
+#ifndef _AF903X_IOCTL_H_
+#define _AF903X_IOCTL_H_
+
+#include <linux/ioctl.h> /* needed for the _IOW etc stuff used later */
+
+/*
+ * Ioctl definitions
+ */
+
+/* Use 'k' as magic number */
+#define AFA_IOC_MAGIC  'k'
+/* Please use a different 8-bit number in your code */
+
+//#define AFA_IOCRESETINTERVAL    _IO(AFA_IOC_MAGIC, 0)
+
+/*
+ * S means "Set" through a ptr,
+ * T means "Tell" directly with the argument value
+ * G means "Get": reply by setting through a pointer
+ * Q means "Query": response is on the return value
+ * X means "eXchange": switch G and S atomically
+ * H means "sHift": switch T and Q atomically
+ */
+
+
+/* ... more to come */
+
+#define AFA_IOC_MAXNR 14
+#endif /* _AF903X-IOCTL_H_ */
diff --git a/drivers/media/dvb/dvb-usb/a867_af903x-tuner.c b/drivers/media/dvb/dvb-usb/a867_af903x-tuner.c
new file mode 100644
index 0000000..fbebd53
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_af903x-tuner.c
@@ -0,0 +1,108 @@
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/delay.h>
+#include <linux/dvb/frontend.h>
+
+#include "dvb_frontend.h"
+#include "a867_af903x.h"
+
+#define IF2  36150       // IF2 frequency = 36.150 MHz
+#define FREF 16000       // Quartz oscillator 16 MHz
+
+static int tuner_set_params(struct dvb_frontend *fe)
+{
+	struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
+	struct tuner_priv *priv = fe->tuner_priv;
+	DWORD dwError = Error_NO_ERROR;
+	DWORD freq = fep->frequency ;// 1000; // Hz -> kHz
+
+	priv->frequency = freq;
+
+	switch (fep->delivery_system) {
+	case SYS_DVBT:
+	case SYS_DVBT2:
+	case SYS_ISDBT:
+	case SYS_DMBTH:
+		priv->bandwidth = fep->bandwidth_hz;
+		break;
+	default:
+		priv->bandwidth = 0;
+		break;
+	}
+
+	deb_data("%s - freq : %d , bandwidth : %dn",__FUNCTION__, freq, priv->bandwidth);
+
+	/* here, frequency is expressed in KHz and bandwidth in MHz */
+	dwError = DL_Tuner_SetFreq(freq/1000, priv->bandwidth/1000000);
+
+	if (dwError) deb_data("tuner_set_params Fail !\n");
+
+	return 0;
+}
+
+static int tuner_get_frequency(struct dvb_frontend *fe, u32 *frequency)
+{
+	struct tuner_priv *priv = fe->tuner_priv;
+	*frequency = priv->frequency;
+	return 0;
+}
+
+static int tuner_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
+{
+	struct tuner_priv *priv = fe->tuner_priv;
+	*bandwidth = priv->bandwidth;
+	return 0;
+}
+
+static int tuner_init(struct dvb_frontend *fe)
+{
+
+	return 0;
+}
+
+static int tuner_sleep(struct dvb_frontend *fe)
+{
+	return 0;
+}
+
+static int tuner_release(struct dvb_frontend *fe)
+{
+	kfree(fe->tuner_priv);
+	fe->tuner_priv = NULL;
+	return 0;
+}
+
+static const struct dvb_tuner_ops tuner_tuner_ops = {
+	.info = {
+		.name           = "dvb_usb_tuner",
+		.frequency_min  =  48000000,
+		.frequency_max  = 860000000,
+		.frequency_step =     50000,
+	},
+
+	.release       = tuner_release,
+
+	.init          = tuner_init,
+	.sleep         = tuner_sleep,
+
+	.set_params    = tuner_set_params,
+	.get_frequency = tuner_get_frequency,
+	.get_bandwidth = tuner_get_bandwidth
+};
+
+/* This functions tries to identify a MT2060 tuner by reading the PART/REV register. This is hasty. */
+struct dvb_frontend * tuner_attach(struct dvb_frontend *fe)
+{
+	struct tuner_priv *priv = NULL;
+
+	priv = kzalloc(sizeof(struct tuner_priv), GFP_KERNEL);
+	if (priv == NULL)
+		return NULL;
+
+	memcpy(&fe->ops.tuner_ops, &tuner_tuner_ops, sizeof(struct dvb_tuner_ops));
+
+	fe->tuner_priv = priv;
+	
+	return fe;
+}
+
diff --git a/drivers/media/dvb/dvb-usb/a867_af903x.h b/drivers/media/dvb/dvb-usb/a867_af903x.h
new file mode 100644
index 0000000..150403a
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_af903x.h
@@ -0,0 +1,301 @@
+ 
+#ifndef _AF903X_H_
+#define _AF903X_H_
+
+#define DVB_USB_LOG_PREFIX "AF903X"
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/kref.h>
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,39)
+#include <linux/smp_lock.h>
+#else
+#include <linux/mutex.h>
+#endif
+#include <linux/usb.h>
+#include <asm/uaccess.h>
+#include "dvb-usb.h"
+#include "a867_af903x-ioctl.h"
+#include "a867_demodulator.h"
+#include "a867_userdef.h"
+//#include "a867_firmware.h"
+#include "a867_type.h"
+#include "a867_Common.h"
+#include "a867_debug.h"
+
+#define ENABLE_TEST_FUNCTION 0
+#define ENABLE_HW_PID 0
+
+
+//enable snr reading register , default = 0
+#define ENABLE_READ_REG 1
+
+
+#define SUPPORT_AF903X_EVB	0
+
+//***************** from device.h *****************//
+#define AFA_USB_DEVICE
+
+#define SLAVE_DEMOD_2WIREADDR  0x3A
+
+#define TS_PACKET_SIZE              	188
+#define TS_PACKET_COUNT_HI       348
+#define TS_PACKET_COUNT_FU       21
+
+//***************** from driver.h *****************//
+#define TS_FRAMES_HI 16
+#define TS_FRAMES_FU 128
+#define MAX_USB20_IRP_NUM  5
+#define MAX_USB11_IRP_NUM  2
+
+//***************** from afdrv.h *****************//
+#define GANY_ONLY 0x42F5
+#define EEPROM_FLB_OFS  8
+
+#define EEPROM_IRMODE      (GANY_ONLY+EEPROM_FLB_OFS+0x10)   //00:disabled, 01:HID
+#define EEPROM_SELSUSPEND  (GANY_ONLY+EEPROM_FLB_OFS+0x28)   //Selective Suspend Mode
+#define EEPROM_TSMODE      (GANY_ONLY+EEPROM_FLB_OFS+0x28+1) //0:one ts, 1:dual ts
+#define EEPROM_2WIREADDR   (GANY_ONLY+EEPROM_FLB_OFS+0x28+2) //MPEG2 2WireAddr
+#define EEPROM_SUSPEND     (GANY_ONLY+EEPROM_FLB_OFS+0x28+3) //Suspend Mode
+#define EEPROM_IRTYPE      (GANY_ONLY+EEPROM_FLB_OFS+0x28+4) //0:NEC, 1:RC6
+#define EEPROM_SAWBW1      (GANY_ONLY+EEPROM_FLB_OFS+0x28+5)
+#define EEPROM_XTAL1       (GANY_ONLY+EEPROM_FLB_OFS+0x28+6) //0:28800, 1:20480
+#define EEPROM_SPECINV1    (GANY_ONLY+EEPROM_FLB_OFS+0x28+7)
+#define EEPROM_TUNERID     (GANY_ONLY+EEPROM_FLB_OFS+0x30+4) //
+#define EEPROM_IFFREQL     (GANY_ONLY+EEPROM_FLB_OFS+0x30) 
+#define EEPROM_IFFREQH     (GANY_ONLY+EEPROM_FLB_OFS+0x30+1)   
+#define EEPROM_IF1L        (GANY_ONLY+EEPROM_FLB_OFS+0x30+2)   
+#define EEPROM_IF1H        (GANY_ONLY+EEPROM_FLB_OFS+0x30+3)
+#define EEPROM_SHIFT       (0x10)                 //EEPROM Addr Shift for slave front end
+
+#define CHECK_LOCK_LOOPS	(20)
+#define USE_MONITOR_TH		1
+
+
+extern int dvb_usb_af903x_debug;
+extern int dvb_usb_af903x_snrdb;
+/*
+#if CONFIG_DVB_USB_DEBUG
+#define avprintk(dbg, lvl, fmt, args...) \
+		do { \
+			printk(fmt, ## args); \
+		} while(0)
+#else
+#define avprintk(dbg, lvl, fmt, args...) do {} while(0)
+#endif //CONFIG_DVB_USB_DEBUG
+
+#define deb_info(fmt, args...)   avprintk(dvb_usb_af903x_debug,0x01,fmt, ## args)
+#define deb_fw(fmt, args...)     avprintk(dvb_usb_af903x_debug,0x02,fmt, ## args)
+#define deb_fwdata(fmt, args...) avprintk(dvb_usb_af903x_debug,0x04,fmt, ## args)
+#define deb_data(fmt, args...)   avprintk(dvb_usb_af903x_debug,0x08,fmt, ## args)
+*/
+//#define deb_data(args...)   printk(KERN_NOTICE args)
+
+#define deb_force(args...) printk(KERN_DEBUG args);
+#define deb_info(args...) if (dvb_usb_af903x_debug & 1) printk(KERN_DEBUG args);
+#define deb_fw(args...) if (dvb_usb_af903x_debug & 2) printk(KERN_DEBUG args);
+#define deb_fwdata(args...)   if (dvb_usb_af903x_debug & 4) printk(KERN_DEBUG args);
+#define deb_data(args...)   if (dvb_usb_af903x_debug & 8) printk(KERN_DEBUG args);
+
+typedef struct _GPIO_MAPPINGS {
+	unsigned short  I2C_SLAVE_ADDR;
+	unsigned short  RF_SW_HOST;
+	int GPIO_UHF_en;
+	int GPIO_UHF_on;
+	int GPIO_UHF_o;
+	int GPIO_VHF_en;
+	int GPIO_VHF_on;
+	int GPIO_VHF_o;
+	int GPIO_WP_en;
+	int GPIO_WP_on;
+	int GPIO_WP_o;
+	int GPIO_OSC_en;
+	int GPIO_OSC_on;
+	int GPIO_OSC_o;
+	int GPIO_TUR1_en;
+	int GPIO_TUR1_on;
+	int GPIO_TUR1_o;
+	int GPIO_TUR2_en;
+	int GPIO_TUR2_on;
+	int GPIO_TUR2_o;
+	int GPIO_DPWR_en;
+	int GPIO_DPWR_on;
+	int GPIO_DPWR_o;
+	int GPIO_DRST_en;
+	int GPIO_DRST_on;
+	int GPIO_DRST_o;
+	int GPIO_STR_en;
+	int GPIO_STR_on;
+	int GPIO_STR_o;
+	int GPIO_STR_i;
+	int GPIO_LED_en;
+	int GPIO_LED_on;
+	int GPIO_LED_o;
+} GPIO_MAPPINGS, *PGPIO_MAPPINGS;
+
+//***************** from device.h *****************//
+typedef struct _TUNER_INFO {
+
+    Bool bTunerInited;
+    Bool bSettingFreq;
+    BYTE TunerId;
+    Bool bTunerOK;
+    Tuner_struct MXL5005_Info;
+
+} TUNER_INFO, *PTUNER_INFO;
+
+
+typedef struct  _FILTER_INFO{
+    int filternum;
+    Bool onoff;
+}  FILTER_INFO;
+
+
+typedef struct _FILTER_CONTEXT_HW {
+    DWORD ulCurrentFrequency;
+    WORD  ucCurrentBandWidth;  
+    DWORD ulDesiredFrequency;
+    WORD  ucDesiredBandWidth;   
+    //ULONG ulBandWidth;   
+    Bool bTimerOn;
+   // PKSFILTER filter;
+    Byte GraphBuilt;
+    TUNER_INFO tunerinfo; 
+    //SIGNAL_STATISTICS ss;
+    //SIGNAL_RETRAIN sr;  
+    //DWORD   gdwOrigFCW;     //move from AF901x.cpp [global variable]
+    //BYTE    gucOrigUnplugTh; //move from AF901x.cpp [global variable]
+    //BYTE    gucPreShiftIdx;    //move from AF901x.cpp [global variable]    
+   // PKSFILTERFACTORY  pFilterFactory;
+    int  bEnPID;
+    int ulcPIDs;
+    FILTER_INFO aulPIDs[32];
+    Bool bApOn;
+    int bResetTs;
+    Byte OvrFlwChk;
+    Byte UnLockCount;
+
+    BYTE AVerFlags;
+} FILTER_CONTEXT_HW, *PFILTER_CONTEXT_HW;  
+
+typedef struct _DEVICE_CONTEXT {
+    FILTER_CONTEXT_HW fc[2];
+    Byte DeviceNo;
+    Bool bBootCode;
+    Bool bEP12Error;
+    Bool bEP45Error;
+    //bool bDebugMsg;
+    //bool bDevExist;
+    Bool bDualTs;
+    Bool bIrTblDownload;
+    Byte BulkOutData[256];
+    u32 WriteLength;
+    Bool bSurpriseRemoval;
+    Bool bDevNotResp;
+    Bool bEnterSuspend;
+    Bool bSupportSuspend;
+    Bool bSupportSelSuspend;
+    u16 regIdx; 
+    Byte eepromIdx;
+    u16 UsbMode;
+    u16 MaxPacketSize;
+    u32 MaxIrpSize;
+    u32 TsFrames;
+    u32 TsFrameSize;
+    u32 TsFrameSizeDw;
+    u32 TsPacketCount;
+    //BYTE  ucDemod2WireAddr;
+    //USB_IDLE_CALLBACK_INFO cbinfo;          // callback info for selective suspend          // our selective suspend IRP    
+
+    Bool    bSelectiveSuspend;
+    u32   ulActiveFilter;
+    //BYTE    ucSerialNo; 
+    Architecture architecture;
+    //BYTE Tuner_Id;
+    StreamType StreamType;
+    Bool bDCAPIP;
+    Bool bSwapFilter;
+    Byte FilterCnt;
+    Bool  bTunerPowerOff;
+    //PKSPIN PinSave;
+    Byte UsbCtrlTimeOut;
+	
+   Ganymede Demodulator;
+   
+    Bool ForceWrite;
+
+    GPIO_MAPPINGS Map;
+
+    struct semaphore powerLock;
+    int power_use_count;
+    struct semaphore tunerLock;
+
+    unsigned short idVendor;
+    unsigned short idProduct;
+
+    struct semaphore regLock;
+	
+} DEVICE_CONTEXT, *PDEVICE_CONTEXT;
+
+#define PTI             (PDC->fc[ucSlaveDemod].tunerinfo)   //TunerInfo pointer
+
+
+
+struct af903x_ofdm_channel {
+	u32 RF_kHz;
+	u8  Bw;
+	s16 nfft;
+	s16 guard;
+	s16 nqam;
+	s16 vit_hrch;
+	s16 vit_select_hp;
+	s16 vit_alpha;
+	s16 vit_code_rate_hp;
+	s16 vit_code_rate_lp;
+	u8  intlv_native;
+};
+
+struct tuner_priv {
+        struct tuner_config *cfg;
+        struct i2c_adapter   *i2c;
+
+        u32 frequency;
+        u32 bandwidth;
+        u16 if1_freq;
+        u8  fmfreq;
+};
+
+extern struct dvb_frontend * tuner_attach(struct dvb_frontend *fe);
+extern struct dvb_frontend * af903x_attach(u8 TMP);
+extern struct dvb_usb_device_properties af903x_properties[];
+extern struct usb_device_id af903x_usb_id_table[];
+extern struct usb_device *udevs;
+extern struct usb_interface *uintfs;
+extern PDEVICE_CONTEXT PDC;
+extern int af903x_device_count;
+
+extern void af903x_start_monitor_thread(struct dvb_frontend *demod);
+extern void af903x_stop_monitor_thread(struct dvb_frontend *demod);
+
+extern DWORD Device_init(struct usb_device *udev, struct usb_interface *uintf, PDEVICE_CONTEXT PDCs, Bool bBoot);
+extern DWORD DL_ApCtrl (Bool bOn);
+extern DWORD DL_Tuner_SetBW(u8 ucBw);
+extern DWORD DL_Tuner_SetFreq(u32 ucFreq,u8 ucBw);
+extern DWORD DL_ReSetInterval(void);
+extern DWORD DL_GetChannelStat(u32 *ber, u32 *berbits, u32 *ubc);
+extern DWORD DL_GetSignalStrength(u16 *strength);
+extern DWORD DL_GetSignalQuality(u16 *strength);
+extern DWORD DL_GetLocked(Bool *bLock);
+extern DWORD DL_MonitorReception(Bool *bLock);
+extern DWORD DL_IsPsbOverflow(void *handle, Byte ucSlaveDemod, Bool *bPsvOverflow);
+extern DWORD DL_Reboot(void);
+extern DWORD DL_ResetPID(void);
+extern DWORD DL_AddPID(BYTE index, Pid pid);
+extern DWORD DL_PIDOnOff(DWORD OnOff);
+extern DWORD DL_RemovePID(BYTE index, Pid pid);
+
+#endif
+
diff --git a/drivers/media/dvb/dvb-usb/a867_aver_version.h b/drivers/media/dvb/dvb-usb/a867_aver_version.h
new file mode 100644
index 0000000..c3213169
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_aver_version.h
@@ -0,0 +1 @@
+#define DRIVER_VER "1.0.27"
diff --git a/drivers/media/dvb/dvb-usb/a867_cmd.c b/drivers/media/dvb/dvb-usb/a867_cmd.c
new file mode 100644
index 0000000..3f6007e
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_cmd.c
@@ -0,0 +1,1005 @@
+#include "a867_cmd.h"
+
+
+Byte Cmd_sequence = 0;
+
+
+Dword Bus_addChecksum (
+    IN  Demodulator*    demodulator,
+    OUT Dword*          bufferLength,
+    OUT Byte*           buffer
+) {
+    Dword error = Error_NO_ERROR;
+    Dword loop = (*bufferLength - 1) / 2;
+    Dword remain = (*bufferLength - 1) % 2;
+    Dword i;
+    Word checksum = 0;
+
+    for (i = 0; i < loop; i++)
+        checksum += (Word) (buffer[2 * i + 1] << 8) + (Word) (buffer[2 * i + 2]);
+    if (remain)
+        checksum += (Word) (buffer[*bufferLength - 1] << 8);
+    checksum = ~checksum;
+    buffer[*bufferLength] = (Byte) ((checksum & 0xFF00) >> 8);
+    buffer[*bufferLength + 1] = (Byte) (checksum & 0x00FF);
+    buffer[0] = (Byte) (*bufferLength + 1);
+    *bufferLength += 2;
+
+    return (error);
+}
+
+
+Dword Bus_removeChecksum (
+    IN  Demodulator*    demodulator,
+    OUT Dword*          bufferLength,
+    OUT Byte*           buffer
+) {
+    Dword error = Error_NO_ERROR;
+    Dword loop = (*bufferLength - 3) / 2;
+    Dword remain = (*bufferLength - 3) % 2;
+    Dword i;
+    Word checksum = 0;
+
+    for (i = 0; i < loop; i++)
+        checksum += (Word) (buffer[2 * i + 1] << 8) + (Word) (buffer[2 * i + 2]);
+    if (remain)
+        checksum += (Word) (buffer[*bufferLength - 3] << 8);
+    checksum = ~checksum;
+    if (((Word) (buffer[*bufferLength - 2] << 8) + (Word) (buffer[*bufferLength - 1])) != checksum) {
+        error = Error_WRONG_CHECKSUM;
+        goto exit;
+    }
+    if (buffer[2])
+        error = Error_FIRMWARE_STATUS | buffer[2];
+    buffer[0] = (Byte) (*bufferLength - 3);
+    *bufferLength -= 2;
+
+exit :
+    return (error);
+}
+
+
+Dword Cmd_writeRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            registerAddressLength,
+    IN  Dword           writeBufferLength,
+    IN  Byte*           writeBuffer
+) {
+    Dword error = Error_NO_ERROR;
+    Word command;
+    Byte buffer[256];
+    Dword bufferLength;
+    Dword i, j, k;
+    Ganymede* ganymede;
+    CmdDescription*     pcmdDesc;
+    BusDescription*     pbusDesc;
+    Dword maxPktSize;
+
+    User_enterCriticalSection (demodulator);
+
+    if (writeBufferLength == 0) goto exit;
+    if (registerAddressLength > 4) {
+        error  = Error_PROTOCOL_FORMAT_INVALID;
+        goto exit;
+    }
+
+    ganymede = (Ganymede*) demodulator;
+    pcmdDesc = ganymede->cmdDescription;
+    pbusDesc = pcmdDesc->busDescription;
+    maxPktSize = pcmdDesc->mailBoxSize;
+
+    i = 0;
+    while (i < writeBufferLength) {
+
+        j = (writeBufferLength - i) > (maxPktSize - 12) ? (maxPktSize - 12) : (writeBufferLength - i);
+        command = Bus_buildCommand (Command_REG_DEMOD_WRITE, processor, chip);
+        buffer[1] = (Byte) (command >> 8);
+        buffer[2] = (Byte) command;
+        buffer[3] = (Byte) Cmd_sequence++;
+        buffer[4] = (Byte) j;
+        buffer[5] = (Byte) registerAddressLength;
+        buffer[6] = (Byte) ((registerAddress + i) >> 24); /** Get first byte of reg. address  */
+        buffer[7] = (Byte) ((registerAddress + i) >> 16); /** Get second byte of reg. address */
+        buffer[8] = (Byte) ((registerAddress + i) >> 8);  /** Get third byte of reg. address  */
+        buffer[9] = (Byte) (registerAddress + i);         /** Get fourth byte of reg. address */
+
+        for (k = 0; k < j; k++)
+            buffer[10 + k] = writeBuffer[i + k];
+
+        bufferLength = j + 10;
+        error = Bus_addChecksum (demodulator, &bufferLength, buffer);
+        if (error) goto exit;
+
+        error = pbusDesc->busTx (demodulator, bufferLength, buffer);
+        if (error) goto exit;
+
+        bufferLength = 5;
+
+        error = pbusDesc->busRx (demodulator, bufferLength, buffer);
+        if (error) goto exit;
+
+        error = Bus_removeChecksum (demodulator, &bufferLength, buffer);
+        if (error) goto exit;
+
+        i += j;
+    }
+
+exit :
+    User_leaveCriticalSection (demodulator);
+    return (error);
+}
+
+
+Dword Cmd_writeScatterRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Byte            valueSetsAddressLength,
+    IN  Byte            valueSetsLength,
+    IN  ValueSet*       valueSets
+) {
+    Dword error = Error_NO_ERROR;
+    Word command;
+    Byte buffer[256];
+    Dword bufferLength;
+    Dword i, j, k;
+    Ganymede* ganymede;
+    CmdDescription*     pcmdDesc;
+    BusDescription*     pbusDesc;
+    Dword maxPktSize;
+
+    User_enterCriticalSection (demodulator);
+
+    if (valueSetsLength == 0) goto exit;
+    if (valueSetsAddressLength > 4) {
+        error  = Error_PROTOCOL_FORMAT_INVALID;
+        goto exit;
+    }
+
+    ganymede = (Ganymede*) demodulator;
+    pcmdDesc = ganymede->cmdDescription;
+    pbusDesc = pcmdDesc->busDescription;
+    maxPktSize = pcmdDesc->mailBoxSize;
+
+    i = 0;
+    while (i < valueSetsLength) {
+        j = (valueSetsLength - i) > ((maxPktSize - 10) / 3) ? ((maxPktSize - 10) / 3) : (valueSetsLength - i);
+        command = Bus_buildCommand (Command_SCATTER_WRITE, processor, chip);
+        buffer[1] = (Byte) (command >> 8);
+        buffer[2] = (Byte) command;
+        buffer[3] = (Byte) Cmd_sequence++;
+        buffer[4] = (Byte) 2;                       /** Type 2 */
+        if (processor == Processor_LINK)
+            buffer[5] = (Byte) 0;
+        else
+            buffer[5] = (Byte) 1;
+        buffer[6] = (Byte) 0;
+        buffer[7] = (Byte) j;
+
+        for (k = 0; k < j; k++) {
+            buffer[8 + k * 2] = (Byte) (valueSets[k].address >> 8);
+            buffer[9 + k * 2] = (Byte) valueSets[k].address;
+            buffer[8 + j * 2 + k] = (Byte) valueSets[k].value;
+        }
+
+        bufferLength = 8 + j * 3;
+        error = Bus_addChecksum (demodulator, &bufferLength, buffer);
+        if (error) goto exit;
+
+        error = pbusDesc->busTx (demodulator, bufferLength, buffer);
+        if (error) goto exit;
+
+        bufferLength =  5;
+
+        error = pbusDesc->busRx (demodulator, bufferLength, buffer);
+        if (error) goto exit;
+
+        error = Bus_removeChecksum (demodulator, &bufferLength, buffer);
+        if (error) goto exit;
+
+        i += j;
+    }
+
+exit :
+    User_leaveCriticalSection (demodulator);
+    return (error);
+}
+
+
+Dword Cmd_writeTunerRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            tunerAddress,
+    IN  Word            registerAddress,
+    IN  Byte            registerAddressLength,
+    IN  Byte            writeBufferLength,
+    IN  Byte*           writeBuffer
+) {
+
+    Dword error = Error_NO_ERROR;
+    Word command;
+    Byte buffer[256];
+    Dword bufferLength;
+    Dword i, j, k;
+    Ganymede* ganymede;
+    CmdDescription*     pcmdDesc;
+    BusDescription*     pbusDesc;
+    Dword maxPktSize;
+
+    User_enterCriticalSection (demodulator);
+
+    ganymede = (Ganymede*) demodulator;
+    pcmdDesc = ganymede->cmdDescription;
+    pbusDesc = pcmdDesc->busDescription;
+    maxPktSize = pcmdDesc->mailBoxSize;
+
+	if (writeBufferLength == 0)
+	{
+        command = Bus_buildCommand (Command_REG_TUNER_WRITE, Processor_LINK, chip);
+        buffer[1] = (Byte) (command >> 8);
+        buffer[2] = (Byte) command;
+        buffer[3] = (Byte) Cmd_sequence++;
+        buffer[4] = (Byte) 0;
+        buffer[5] = (Byte) tunerAddress;
+        buffer[6] = (Byte) registerAddressLength;
+        buffer[7] = (Byte) ((registerAddress) >> 8);  /** Get high byte of reg. address */
+        buffer[8] = (Byte) (registerAddress);         /** Get low byte of reg. address  */
+
+        bufferLength = 9;
+        error = Bus_addChecksum (demodulator, &bufferLength, buffer);
+        if (error) goto exit;
+
+        error = pbusDesc->busTx (demodulator, bufferLength, buffer);
+        if (error) goto exit;
+
+        bufferLength = 5;
+
+        error = pbusDesc->busRx (demodulator, bufferLength, buffer);
+        if (error) goto exit;
+
+        error = Bus_removeChecksum (demodulator, &bufferLength, buffer);
+        if (error) goto exit;
+
+		goto exit;
+	}
+
+    i = 0;
+    while (i < writeBufferLength) {
+        j = (writeBufferLength - i) > (maxPktSize - 11) ? (maxPktSize - 11) : (writeBufferLength - i);
+        command = Bus_buildCommand (Command_REG_TUNER_WRITE, Processor_LINK, chip);
+        buffer[1] = (Byte) (command >> 8);
+        buffer[2] = (Byte) command;
+        buffer[3] = (Byte) Cmd_sequence++;
+        buffer[4] = (Byte) j;
+        buffer[5] = (Byte) tunerAddress;
+        buffer[6] = (Byte) registerAddressLength;
+        buffer[7] = (Byte) ((registerAddress + i) >> 8);  /** Get high byte of reg. address */
+        buffer[8] = (Byte) (registerAddress + i);         /** Get low byte of reg. address  */
+
+        for (k = 0; k < j; k++)
+            buffer[9 + k] = writeBuffer[ i + k];
+
+        bufferLength = j + 9;
+        error = Bus_addChecksum (demodulator, &bufferLength, buffer);
+        if (error) goto exit;
+
+        error = pbusDesc->busTx (demodulator, bufferLength, buffer);
+        if (error) goto exit;
+
+        bufferLength = 5;
+
+        error = pbusDesc->busRx (demodulator, bufferLength, buffer);
+        if (error) goto exit;
+
+        error = Bus_removeChecksum (demodulator, &bufferLength, buffer);
+        if (error) goto exit;
+
+        i += j;
+    }
+
+
+exit :    
+    User_leaveCriticalSection (demodulator);
+    return (error);
+}
+
+
+Dword Cmd_writeEepromValues (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            eepromAddress,
+    IN  Word            registerAddress,
+    IN  Byte            registerAddressLength,
+    IN  Byte            writeBufferLength,
+    IN  Byte*           writeBuffer
+) {
+    Dword error = Error_NO_ERROR;
+    Word command;
+    Byte buffer[256];
+    Dword bufferLength;
+    Byte i;
+    Ganymede* ganymede;
+    CmdDescription*     pcmdDesc;
+    BusDescription*     pbusDesc;
+    Dword maxPktSize;
+
+    User_enterCriticalSection (demodulator);
+
+    if (writeBufferLength == 0) goto exit;
+
+    ganymede = (Ganymede*) demodulator;
+    pcmdDesc = ganymede->cmdDescription;
+    pbusDesc = pcmdDesc->busDescription;
+    maxPktSize = pcmdDesc->mailBoxSize;
+
+    command = Bus_buildCommand (Command_REG_EEPROM_WRITE, Processor_LINK, chip);
+    buffer[1] = (Byte) (command >> 8);
+    buffer[2] = (Byte) command;
+    buffer[3] = (Byte) Cmd_sequence++;
+    buffer[4] = (Byte) writeBufferLength;
+    buffer[5] = (Byte) eepromAddress;
+    buffer[6] = (Byte) registerAddressLength;
+    buffer[7] = (Byte) (registerAddress >> 8);  /** Get high byte of reg. address */
+    buffer[8] = (Byte) registerAddress;         /** Get low byte of reg. address  */
+
+    for (i = 0; i < writeBufferLength; i++)
+        buffer[9 + i] = writeBuffer[i];
+
+    bufferLength = writeBufferLength + 9;
+    error = Bus_addChecksum (demodulator, &bufferLength, buffer);
+    if (error) goto exit;
+
+    error = pbusDesc->busTx (demodulator, bufferLength, buffer);
+    if (error) goto exit;
+
+    bufferLength = 5;
+
+    error = pbusDesc->busRx (demodulator, bufferLength, buffer);
+    if (error) goto exit;
+
+    error = Bus_removeChecksum (demodulator, &bufferLength, buffer);
+    if (error) goto exit;
+
+exit :
+    User_leaveCriticalSection (demodulator);
+    return (error);
+}
+
+
+Dword Cmd_readRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            registerAddressLength,
+    IN  Dword           readBufferLength,
+    OUT Byte*           readBuffer
+) {
+    Dword error = Error_NO_ERROR;
+    Word command;
+    Byte buffer[256];
+    Dword bufferLength;
+    Dword i, j, k;
+    Ganymede* ganymede;
+    CmdDescription*     pcmdDesc;
+    BusDescription*     pbusDesc;
+    Dword maxPktSize;
+
+    User_enterCriticalSection (demodulator);
+
+    if (readBufferLength == 0) goto exit;
+    if (registerAddressLength > 4) {
+        error  = Error_PROTOCOL_FORMAT_INVALID;
+        goto exit;
+    }
+
+    ganymede = (Ganymede*) demodulator;
+    pcmdDesc = ganymede->cmdDescription;
+    pbusDesc = pcmdDesc->busDescription;
+    maxPktSize = pcmdDesc->mailBoxSize;
+
+    i = 0;
+    while (i < readBufferLength) {
+
+        j = (readBufferLength - i) > (maxPktSize - 5) ? (maxPktSize - 5) : (readBufferLength - i);
+        command = Bus_buildCommand (Command_REG_DEMOD_READ, processor, chip);
+        buffer[1] = (Byte) (command >> 8);
+        buffer[2] = (Byte) command;
+        buffer[3] = (Byte) Cmd_sequence++;
+        buffer[4] = (Byte) j;
+        buffer[5] = (Byte) registerAddressLength;
+        buffer[6] = (Byte) ((registerAddress + i) >> 24); /** Get first byte of reg. address  */
+        buffer[7] = (Byte) ((registerAddress + i) >> 16); /** Get second byte of reg. address */
+        buffer[8] = (Byte) ((registerAddress + i) >> 8);  /** Get third byte of reg. address  */
+        buffer[9] = (Byte) (registerAddress + i);         /** Get fourth byte of reg. address */
+
+        bufferLength = 10;
+        error = Bus_addChecksum (demodulator, &bufferLength, buffer);
+        if (error) goto exit;
+
+        error = pbusDesc->busTx (demodulator, bufferLength, buffer);
+        if (error) goto exit;
+
+        bufferLength = j + 5;
+
+        error = pbusDesc->busRx (demodulator, bufferLength, buffer);
+        if (error) goto exit;
+
+        error = Bus_removeChecksum (demodulator, &bufferLength, buffer);
+        if (error) goto exit;
+        for (k = 0; k < j; k++) {
+            readBuffer[i + k] = buffer[k + 3];
+        }
+
+        i += j;
+    }
+
+exit :
+    User_leaveCriticalSection (demodulator);
+    return (error);
+}
+
+
+Dword Cmd_readScatterRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Byte            valueSetsAddressLength,
+    IN  Byte            valueSetsLength,
+    OUT ValueSet*       valueSets
+) {
+    Dword error = Error_NO_ERROR;
+    Word command;
+    Byte buffer[256];
+    Dword bufferLength;
+    Dword i, j, k;
+    Ganymede* ganymede;
+    CmdDescription*     pcmdDesc;
+    BusDescription*     pbusDesc;
+    Dword maxPktSize;
+
+    User_enterCriticalSection (demodulator);
+
+    if (valueSetsLength == 0) goto exit;
+    if (valueSetsAddressLength > 4) {
+        error  = Error_PROTOCOL_FORMAT_INVALID;
+        goto exit;
+    }
+
+    ganymede = (Ganymede*) demodulator;
+    pcmdDesc = ganymede->cmdDescription;
+    pbusDesc = pcmdDesc->busDescription;
+    maxPktSize = pcmdDesc->mailBoxSize;
+
+    i = 0;
+    while (i < valueSetsLength) {
+        j = (valueSetsLength - i) > ((maxPktSize - 10) / 2) ? ((maxPktSize - 10) / 2) : (valueSetsLength - i);
+        command = Bus_buildCommand (Command_SCATTER_READ, processor, chip);
+        buffer[1] = (Byte) (command >> 8);
+        buffer[2] = (Byte) command;
+        buffer[3] = (Byte) Cmd_sequence++;
+        buffer[4] = (Byte) 2;                       /** Type 2 */
+        if (processor == Processor_LINK)
+            buffer[5] = (Byte) 0;
+        else
+            buffer[5] = (Byte) 1;
+        buffer[6] = (Byte) 0;
+        buffer[7] = (Byte) j;
+
+        for (k = 0; k < j; k++) {
+            buffer[8 + k * 2] = (Byte) (valueSets[k].address >> 8);
+            buffer[9 + k * 2] = (Byte) valueSets[k].address;
+        }
+
+        bufferLength = 8 + j * 2;
+        error = Bus_addChecksum (demodulator, &bufferLength, buffer);
+        if (error) goto exit;
+
+        error = pbusDesc->busTx (demodulator, bufferLength, buffer);
+        if (error) goto exit;
+
+        bufferLength = j + 5;
+
+        error = pbusDesc->busRx (demodulator, bufferLength, buffer);
+        if (error) goto exit;
+
+        error = Bus_removeChecksum (demodulator, &bufferLength, buffer);
+        if (error) goto exit;
+        for (k = 0; k < j; k++) {
+            //(Byte) valueSets[i + k].value = buffer[k + 3];
+	      valueSets[i + k].value = (Byte) buffer[k + 3];
+        }
+
+        i += j;
+    }
+
+exit :
+    User_leaveCriticalSection (demodulator);
+    return (error);
+}
+
+
+Dword Cmd_readTunerRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            tunerAddress,
+    IN  Word            registerAddress,
+    IN  Byte            registerAddressLength,
+    IN  Byte            readBufferLength,
+    IN  Byte*           readBuffer
+) {
+    Dword error = Error_NO_ERROR;
+    Word command;
+    Byte buffer[256];
+    Dword bufferLength;
+    Dword i, j, k;
+    Ganymede* ganymede;
+    CmdDescription*     pcmdDesc;
+    BusDescription*     pbusDesc;
+    Dword maxPktSize;
+
+    User_enterCriticalSection (demodulator);
+
+    if (readBufferLength == 0) goto exit;
+
+    ganymede = (Ganymede*) demodulator;
+    pcmdDesc = ganymede->cmdDescription;
+    pbusDesc = pcmdDesc->busDescription;
+    maxPktSize = pcmdDesc->mailBoxSize;
+
+    i = 0;
+    while (i < readBufferLength) {
+        j = (readBufferLength - i) > (maxPktSize - 5) ? (maxPktSize - 5) : (readBufferLength - i);
+        command = Bus_buildCommand (Command_REG_TUNER_READ, Processor_LINK, chip);
+        buffer[1] = (Byte) (command >> 8);
+        buffer[2] = (Byte) command;
+        buffer[3] = (Byte) Cmd_sequence++;
+        buffer[4] = (Byte) j;
+        buffer[5] = (Byte) tunerAddress;
+        buffer[6] = (Byte) registerAddressLength;
+        buffer[7] = (Byte) ((registerAddress + i) >> 8);  /** Get high byte of reg. address */
+        buffer[8] = (Byte) (registerAddress + i);         /** Get low byte of reg. address  */
+
+        bufferLength = 9;
+        error = Bus_addChecksum (demodulator, &bufferLength, buffer);
+        if (error) goto exit;
+
+        error = pbusDesc->busTx (demodulator, bufferLength, buffer);
+        if (error) goto exit;
+
+        bufferLength = j + 5;
+
+        error = pbusDesc->busRx (demodulator, bufferLength, buffer);
+        if (error) goto exit;
+
+        error = Bus_removeChecksum (demodulator, &bufferLength, buffer);
+        if (error) goto exit;
+        for (k = 0; k < j; k++) {
+            readBuffer[i + k] = buffer[k + 3];
+        }
+
+        i += j;
+    }
+
+exit :
+    User_leaveCriticalSection (demodulator);
+    return (error);
+}
+
+
+Dword Cmd_readEepromValues (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            eepromAddress,
+    IN  Word            registerAddress,
+    IN  Byte            registerAddressLength,
+    IN  Byte            readBufferLength,
+    OUT Byte*           readBuffer
+) {
+    Dword error = Error_NO_ERROR;
+    Word command;
+    Byte buffer[256];
+    Dword bufferLength;
+    Byte i;
+    Ganymede* ganymede;
+    CmdDescription*     pcmdDesc;
+    BusDescription*     pbusDesc;
+    Dword maxPktSize;
+
+    User_enterCriticalSection (demodulator);
+
+    if (readBufferLength == 0) goto exit;
+
+    ganymede = (Ganymede*) demodulator;
+    pcmdDesc = ganymede->cmdDescription;
+    pbusDesc = pcmdDesc->busDescription;
+    maxPktSize = pcmdDesc->mailBoxSize;
+
+    command = Bus_buildCommand (Command_REG_EEPROM_READ, Processor_LINK, chip);
+    buffer[1] = (Byte) (command >> 8);
+    buffer[2] = (Byte) command;
+    buffer[3] = (Byte) Cmd_sequence++;
+    buffer[4] = (Byte) readBufferLength;
+    buffer[5] = (Byte) eepromAddress;
+    buffer[6] = (Byte) registerAddressLength;
+    buffer[7] = (Byte) (registerAddress >> 8);  /** Get high byte of reg. address */
+    buffer[8] = (Byte) registerAddress;         /** Get low byte of reg. address  */
+
+    bufferLength = 9;
+    error = Bus_addChecksum (demodulator, &bufferLength, buffer);
+    if (error) goto exit;
+
+    error = pbusDesc->busTx (demodulator, bufferLength, buffer);
+    if (error) goto exit;
+
+    bufferLength = readBufferLength + 5;
+    error = pbusDesc->busRx (demodulator, bufferLength, buffer);
+    if (error) goto exit;
+
+    error = Bus_removeChecksum (demodulator, &bufferLength, buffer);
+    if (error) goto exit;
+    for (i = 0; i < readBufferLength; i++) {
+        readBuffer[i] = buffer[i + 3];
+    }
+
+exit :
+    User_leaveCriticalSection (demodulator);
+    return (error);
+}
+
+
+Dword Cmd_modifyRegister (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            registerAddressLength,
+    IN  Byte            position,
+    IN  Byte            length,
+    IN  Byte            value
+) {
+    Dword error = Error_NO_ERROR;
+    Word command;
+    Byte buffer[256];
+    Dword bufferLength;
+    Byte temp;
+    Ganymede* ganymede;
+    CmdDescription*     pcmdDesc;
+    BusDescription*     pbusDesc;
+    Dword maxPktSize;
+
+    User_enterCriticalSection (demodulator);
+
+    if (registerAddressLength > 4) {
+        error  = Error_PROTOCOL_FORMAT_INVALID;
+        goto exit;
+    }
+
+    ganymede = (Ganymede*) demodulator;
+    pcmdDesc = ganymede->cmdDescription;
+    pbusDesc = pcmdDesc->busDescription;
+    maxPktSize = pcmdDesc->mailBoxSize;
+
+    command = Bus_buildCommand (Command_REG_DEMOD_READ, processor, chip);
+    buffer[1] = (Byte) (command >> 8);
+    buffer[2] = (Byte) command;
+    buffer[3] = (Byte) Cmd_sequence++;
+    buffer[4] = (Byte) 1;
+    buffer[5] = (Byte) registerAddressLength;
+    buffer[6] = (Byte) (registerAddress >> 24); /** Get first byte of reg. address  */
+    buffer[7] = (Byte) (registerAddress >> 16); /** Get second byte of reg. address */
+    buffer[8] = (Byte) (registerAddress >> 8);  /** Get third byte of reg. address  */
+    buffer[9] = (Byte) registerAddress;         /** Get fourth byte of reg. address */
+
+    bufferLength = 10;
+    error = Bus_addChecksum (demodulator, &bufferLength, buffer);
+    if (error) goto exit;
+
+    error = pbusDesc->busTx (demodulator, bufferLength, buffer);
+    if (error) goto exit;
+
+    bufferLength = 6;
+
+    error = pbusDesc->busRx (demodulator, bufferLength, buffer);
+    if (error) goto exit;
+
+    error = Bus_removeChecksum (demodulator, &bufferLength, buffer);
+    if (error) goto exit;
+    temp = buffer[3];
+    temp = REG_CREATE (value, temp, position, length);
+
+    command = Bus_buildCommand (Command_REG_DEMOD_WRITE, processor, chip);
+    buffer[1] = (Byte) (command >> 8);
+    buffer[2] = (Byte) command;
+    buffer[3] = (Byte) Cmd_sequence++;
+    buffer[4] = (Byte) 1;
+    buffer[5] = (Byte) registerAddressLength;
+    buffer[6] = (Byte) (registerAddress >> 24); /** Get first byte of reg. address  */
+    buffer[7] = (Byte) (registerAddress >> 16); /** Get second byte of reg. address */
+    buffer[8] = (Byte) (registerAddress >> 8);  /** Get third byte of reg. address  */
+    buffer[9] = (Byte) registerAddress;         /** Get fourth byte of reg. address */
+    buffer[10] = temp;
+
+    bufferLength = 11;
+    error = Bus_addChecksum (demodulator, &bufferLength, buffer);
+    if (error) goto exit;
+
+    error = pbusDesc->busTx (demodulator, bufferLength, buffer);
+    if (error) goto exit;
+
+    bufferLength = 5;
+
+    error = pbusDesc->busRx (demodulator, bufferLength, buffer);
+    if (error) goto exit;
+
+    error = Bus_removeChecksum (demodulator, &bufferLength, buffer);
+    if (error) goto exit;
+
+exit :
+    User_leaveCriticalSection (demodulator);
+    return (error);
+}
+
+
+Dword Cmd_loadFirmware (
+    IN  Demodulator*    demodulator,
+    IN  Dword           length,
+    IN  Byte*           firmware
+) {
+    Dword error = Error_NO_ERROR;
+    Word command;
+    Dword loop;
+    Dword remain;
+    Dword i, j, k;
+    Byte buffer[256];
+    Dword bufferLength;
+    Ganymede* ganymede;
+    CmdDescription*     pcmdDesc;
+    BusDescription*     pbusDesc;
+    Dword maxPktSize;
+
+    User_enterCriticalSection (demodulator);
+
+    ganymede = (Ganymede*) demodulator;
+    pcmdDesc = ganymede->cmdDescription;
+    pbusDesc = pcmdDesc->busDescription;
+    maxPktSize = pcmdDesc->mailBoxSize;
+
+    loop = length / (maxPktSize - 6);
+    remain = length % (maxPktSize - 6);
+    k = 0;
+    command = Bus_buildCommand (Command_FW_DOWNLOAD, Processor_LINK, 0);
+    for (i = 0; i < loop; i++) {
+        buffer[1] = (Byte) (command >> 8);
+        buffer[2] = (Byte) command;
+        buffer[3] = (Byte) Cmd_sequence++;
+        for (j = 0; j < (maxPktSize - 6); j++)
+            buffer[4 + j] = firmware[k++];
+        bufferLength = (maxPktSize - 2);
+        error = Bus_addChecksum (demodulator, &bufferLength, buffer);
+        if (error) goto exit;
+
+        error = pbusDesc->busTx (demodulator, bufferLength, buffer);
+        if (error) goto exit;
+    }
+    if (remain) {
+        buffer[1] = (Byte) (command >> 8);
+        buffer[2] = (Byte) command;
+        buffer[3] = (Byte) Cmd_sequence++;
+        for (j = 0; j < remain; j++)
+            buffer[4 + j] = firmware[k++];
+        bufferLength = (Word) (4 + remain);
+        error = Bus_addChecksum (demodulator, &bufferLength, buffer);
+        if (error) goto exit;
+
+        error = pbusDesc->busTx (demodulator, bufferLength, buffer);
+        if (error) goto exit;
+    }
+
+exit :
+    User_leaveCriticalSection (demodulator);
+    return (error);
+}
+
+
+Dword Cmd_reboot (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip
+) {
+    Dword error = Error_NO_ERROR;
+    Word command;
+    Byte buffer[256];
+    Dword bufferLength;
+
+    Ganymede* ganymede;
+    CmdDescription*     pcmdDesc;
+    BusDescription*     pbusDesc;
+    Dword maxPktSize;
+
+    ganymede = (Ganymede*) demodulator;
+    pcmdDesc = ganymede->cmdDescription;
+    pbusDesc = pcmdDesc->busDescription;
+    maxPktSize = pcmdDesc->mailBoxSize;
+
+    User_enterCriticalSection (demodulator);
+
+    command = Bus_buildCommand (Command_REBOOT, Processor_LINK, chip);
+    buffer[1] = (Byte) (command >> 8);
+    buffer[2] = (Byte) command;
+    buffer[3] = (Byte) Cmd_sequence++;
+    bufferLength = 4;
+    error = Bus_addChecksum (demodulator, &bufferLength, buffer);
+    if (error) goto exit;
+
+    error = pbusDesc->busTx (demodulator, bufferLength, buffer);
+    if (error) goto exit;
+
+exit :
+    User_leaveCriticalSection (demodulator);
+    return (error);
+}
+
+
+Dword Cmd_sendCommand (
+    IN  Demodulator*    demodulator,
+    IN  Word            command,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           writeBufferLength,
+    IN  Byte*           writeBuffer,
+    IN  Dword           readBufferLength,
+    OUT Byte*           readBuffer
+) {
+    Dword error = Error_NO_ERROR;
+    Byte buffer[256];
+    Dword bufferLength;
+    Dword i, j, k;
+    Ganymede* ganymede;
+    CmdDescription*     pcmdDesc;
+    BusDescription*     pbusDesc;
+    Dword maxPktSize;
+
+    User_enterCriticalSection (demodulator);
+
+    ganymede = (Ganymede*) demodulator;
+    pcmdDesc = ganymede->cmdDescription;
+    pbusDesc = pcmdDesc->busDescription;
+    maxPktSize = pcmdDesc->mailBoxSize;
+
+    if (writeBufferLength == 0) {
+        command = Bus_buildCommand (command, processor, chip);
+        buffer[1] = (Byte) (command >> 8);
+        buffer[2] = (Byte) command;
+        buffer[3] = (Byte) Cmd_sequence++;
+        bufferLength = 4;
+        error = Bus_addChecksum (demodulator, &bufferLength, buffer);
+        if (error) goto exit;
+
+        error = pbusDesc->busTx (demodulator, bufferLength, buffer);
+        if (error) goto exit;
+    } else {
+        i = 0;
+        while (i < writeBufferLength) {
+            j = (writeBufferLength - i) > (maxPktSize - 6) ? (maxPktSize - 6) : (writeBufferLength - i);
+            command = Bus_buildCommand (command, processor, chip);
+            buffer[1] = (Byte) (command >> 8);
+            buffer[2] = (Byte) command;
+            buffer[3] = (Byte) Cmd_sequence++;
+            for (k = 0; k < j; k++)
+                buffer[k + 4] = writeBuffer[i + k];
+
+            bufferLength = j + 4;
+            error = Bus_addChecksum (demodulator, &bufferLength, buffer);
+            if (error) goto exit;
+
+            error = pbusDesc->busTx (demodulator, bufferLength, buffer);
+            if (error) goto exit;
+
+            i += j;
+        }
+    }
+
+    if (readBufferLength == 0) {
+        bufferLength = 5;
+
+        error = pbusDesc->busRx (demodulator, bufferLength, buffer);
+        if (error) goto exit;
+
+        error = Bus_removeChecksum (demodulator, &bufferLength, buffer);
+        if (error) goto exit;
+    } else {
+        i = 0;
+        while (i < readBufferLength) {
+            j = (readBufferLength - i) > (maxPktSize - 5) ? (maxPktSize - 5) : (readBufferLength - i);
+
+            bufferLength = j + 5;
+
+            error = pbusDesc->busRx (demodulator, bufferLength, buffer);
+            if (error) goto exit;
+
+            error = Bus_removeChecksum (demodulator, &bufferLength, buffer);
+            if (error) goto exit;
+            for (k = 0; k < j; k++)
+                readBuffer[i + k] = buffer[k + 3];
+
+            i += j;
+        }
+    }
+
+exit :
+    User_leaveCriticalSection (demodulator);
+    return (error);
+}
+
+
+Dword Cmd_receiveData (
+    IN  Demodulator*    demodulator,
+    IN  Dword           registerAddress,
+    IN  Dword           readBufferLength,
+    OUT Byte*           readBuffer
+) {
+    Dword error = Error_NO_ERROR;
+    Word command;
+    Byte buffer[256];
+    Dword bufferLength;
+    Ganymede* ganymede;
+    CmdDescription*     pcmdDesc;
+    BusDescription*     pbusDesc;
+    Dword maxPktSize;
+
+    if (readBufferLength == 0) goto exit;
+
+    ganymede = (Ganymede*) demodulator;
+    pcmdDesc = ganymede->cmdDescription;
+    pbusDesc = pcmdDesc->busDescription;
+    maxPktSize = pcmdDesc->mailBoxSize;
+
+    User_enterCriticalSection (demodulator);
+
+    command = Bus_buildCommand (Command_DATA_READ, Processor_LINK, 0);
+    buffer[1] = (Byte) (command >> 8);
+    buffer[2] = (Byte) command;
+    buffer[3] = (Byte) Cmd_sequence++;
+    buffer[4] = (Byte) ((readBufferLength >> 16)  & 0xFF);
+    buffer[5] = (Byte) ((readBufferLength >> 8)  & 0xFF);
+    buffer[6] = (Byte) (readBufferLength  & 0xFF);
+    buffer[7] = (Byte) ((registerAddress >> 16)  & 0xFF);
+    buffer[8] = (Byte) ((registerAddress >> 8)  & 0xFF);
+    buffer[9] = (Byte) (registerAddress  & 0xFF);
+
+    bufferLength = 10;
+    error = Bus_addChecksum (demodulator, &bufferLength, buffer);
+    if (error) goto exit;
+
+    error = pbusDesc->busTx (demodulator, bufferLength, buffer);
+    if (error) goto exit;
+
+    error = pbusDesc->busRxData (demodulator, readBufferLength, readBuffer);
+
+exit :
+    User_leaveCriticalSection (demodulator);
+    return (error);
+}
+
+
+Word Cmd_busId = Bus_USB;
+CmdDescription Cmd_busDescription = {
+    0,
+    NULL,
+    Cmd_writeRegisters,
+    Cmd_writeScatterRegisters,
+    Cmd_writeTunerRegisters,
+    Cmd_writeEepromValues,
+    Cmd_readRegisters,
+    Cmd_readScatterRegisters,
+    Cmd_readTunerRegisters,
+    Cmd_readEepromValues,
+    Cmd_modifyRegister,
+    Cmd_loadFirmware,
+    Cmd_reboot,
+    Cmd_sendCommand,
+    Cmd_receiveData
+};
diff --git a/drivers/media/dvb/dvb-usb/a867_cmd.h b/drivers/media/dvb/dvb-usb/a867_cmd.h
new file mode 100644
index 0000000..d7cb1f6
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_cmd.h
@@ -0,0 +1,246 @@
+#ifndef __CMD_H__
+#define __CMD_H__
+
+
+#include "a867_type.h"
+#include "a867_user.h"
+#include "a867_error.h"
+
+/**
+ * Bus types
+ */
+#define Bus_I2C             1
+#define Bus_USB             2
+#define Bus_SPI             3
+#define Bus_SDIO            4
+#define Bus_USB11           5
+#define Bus_I2M             6  /** I2C bus for Mercury      */
+#define Bus_I2U             7  /** I2C bus for Mercury USB  */
+
+
+/**
+ * Define commands
+ */
+#define Command_REG_DEMOD_READ          0x0000
+#define Command_REG_DEMOD_WRITE         0x0001
+#define Command_REG_TUNER_READ          0x0002
+#define Command_REG_TUNER_WRITE         0x0003
+#define Command_REG_EEPROM_READ         0x0004
+#define Command_REG_EEPROM_WRITE        0x0005
+#define Command_VAR_READ                0x0008
+#define Command_VAR_WRITE               0x0009
+
+#define Command_DATA_READ               0x0006
+
+#define Command_PLATFORM_GET            0x000A
+#define Command_PLATFORM_SET            0x000B
+#define Command_IP_CACHE                0x000D
+#define Command_IP_ADD                  0x000E
+#define Command_IP_REMOVE               0x000F
+#define Command_PID_ADD                 0x0010
+#define Command_PID_REMOVE              0x0011
+#define Command_SIPSI_GET               0x0012  /** Get SI/PSI table for specific PID "once". */
+#define Command_SIPSI_MPE_RESET         0x0013
+#define Command_H_PID_ADD               0x0015
+#define Command_H_PID_REMOVE            0x0016
+#define Command_ABORT                   0x0017
+#define Command_IR_GET                  0x0018
+#define Command_IR_SET                  0x0019
+#define Command_FW_DOWNLOAD_BEGIN       0x0024
+#define Command_FW_DOWNLOAD             0x0021
+#define Command_FW_DOWNLOAD_END         0x0025
+#define Command_QUERYINFO               0x0022
+#define Command_BOOT                    0x0023
+#define Command_REBOOT                  0x0023
+#define Command_RUN_CODE                0x0026
+#define Command_SCATTER_READ            0x0028
+#define Command_SCATTER_WRITE           0x0029
+#define Command_GENERIC_READ            0x002A
+#define Command_GENERIC_WRITE           0x002B
+
+#define Command_SERVICES_GET            0x0083
+#define Command_COMPONENT_ADD           0x0086
+#define Command_COMPONENT_REMOVE        0x0087
+#define Command_FIG_ADD                 0x0088
+#define Command_FIG_REMOVE              0x0089
+
+
+#define Bus_MAX_WRITE_SIZE              254
+#define Bus_MAX_READ_SIZE               254
+
+
+#define Bus_buildCommand(command, processor, chip)  (command + (Word) (processor << 12) + (Word) (chip << 12))
+
+
+/**
+ *
+ */
+Dword Cmd_writeRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            registerAddressLength,
+    IN  Dword           writeBufferLength,
+    IN  Byte*           writeBuffer
+);
+
+
+/**
+ *
+ */
+Dword Cmd_writeScatterRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Byte            valueSetsAddressLength,
+    IN  Byte            valueSetsLength,
+    IN  ValueSet*       valueSets
+);
+
+
+/**
+ *
+ */
+Dword Cmd_writeTunerRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            tunerAddress,
+    IN  Word            registerAddress,
+    IN  Byte            registerAddressLength,
+    IN  Byte            writeBufferLength,
+    IN  Byte*           writeBuffer
+);
+
+
+
+/**
+ *
+ */
+Dword Cmd_writeEepromValues (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            eepromAddress,
+    IN  Word            registerAddress,
+    IN  Byte            registerAddressLength,
+    IN  Byte            writeBufferLength,
+    IN  Byte*           writeBuffer
+);
+
+
+/**
+ *
+ */
+Dword Cmd_readRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            registerAddressLength,
+    IN  Dword           readBufferLength,
+    OUT Byte*           readBuffer
+);
+
+
+/**
+ *
+ */
+Dword Cmd_readScatterRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Byte            valueSetsAddressLength,
+    IN  Byte            valueSetsLength,
+    OUT ValueSet*       valueSets
+);
+
+
+/**
+ *
+ */
+Dword Cmd_readTunerRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            tunerAddress,
+    IN  Word            registerAddress,
+    IN  Byte            registerAddressLength,
+    IN  Byte            readBufferLength,
+    IN  Byte*           readBuffer
+);
+
+
+/**
+ *
+ */
+Dword Cmd_readEepromValues (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            eepromAddress,
+    IN  Word            registerAddress,
+    IN  Byte            registerAddressLength,
+    IN  Byte            readBufferLength,
+    OUT Byte*           readBuffer
+);
+
+
+/**
+ *
+ */
+Dword Cmd_modifyRegister (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            registerAddressLength,
+    IN  Byte            position,
+    IN  Byte            length,
+    IN  Byte            value
+);
+
+
+/**
+ *
+ */
+Dword Cmd_loadFirmware (
+    IN  Demodulator*    demodulator,
+    IN  Dword           length,
+    IN  Byte*           firmware
+);
+
+
+/**
+ *
+ */
+Dword Cmd_reboot (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip
+);
+
+
+/**
+ *
+ */
+Dword Cmd_sendCommand (
+    IN  Demodulator*    demodulator,
+    IN  Word            command,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           writeBufferLength,
+    IN  Byte*           writeBuffer,
+    IN  Dword           readBufferLength,
+    OUT Byte*           readBuffer
+);
+
+
+Dword Cmd_receiveData (
+    IN  Demodulator*    demodulator,
+    IN  Dword           registerAddress,
+    IN  Dword           readBufferLength,
+    OUT Byte*           readBuffer
+);
+
+
+extern Word Cmd_busId;
+extern CmdDescription Cmd_busDescription;
+#endif
+
diff --git a/drivers/media/dvb/dvb-usb/a867_compat.h b/drivers/media/dvb/dvb-usb/a867_compat.h
new file mode 100644
index 0000000..d043287
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_compat.h
@@ -0,0 +1,503 @@
+/*
+ * $Id: compat.h,v 1.1.1.1 2008/07/09 07:30:49 stylon Exp $
+ */
+
+#ifndef _COMPAT_H
+#define _COMPAT_H
+
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)
+#define	KERN_CONT	""
+#endif
+
+/* To allow I2C compatibility code to work */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)
+#include <linux/i2c-dev.h>
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)
+# define set_freezable()
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,18)
+# define minor(x) MINOR(x)
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,13)
+# define DEVICE_ATTR(a,b,c,d) CLASS_DEVICE_ATTR(a,b,c,d)
+# define device_create_file(a,b) class_device_create_file(a,b)
+# define device_remove_file(a,b) class_device_remove_file(a,b)
+# define device_register(a) class_device_register(a)
+# define device_unregister(a) class_device_unregister(a)
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+# include <linux/moduleparam.h>
+# include <linux/delay.h>
+# define need_resched() (current->need_resched)
+# define work_struct tq_struct
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19)
+# define BUG_ON(condition) do { if ((condition)!=0) BUG(); } while(0)
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,23)
+# define irqreturn_t void
+# define IRQ_RETVAL(foobar)
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,71)
+# define strlcpy(dest,src,len) strncpy(dest,src,(len)-1)
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
+# define iminor(inode) minor(inode->i_rdev)
+#endif
+
+#if defined(I2C_ADAP_CLASS_TV_ANALOG) && !defined(I2C_CLASS_TV_ANALOG)
+# define  I2C_CLASS_TV_ANALOG  I2C_ADAP_CLASS_TV_ANALOG
+# define  I2C_CLASS_TV_DIGITAL I2C_ADAP_CLASS_TV_DIGITAL
+#endif
+
+#ifndef __pure
+#  define __pure __attribute__((pure))
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9)
+# define __user
+# define __kernel
+# define __iomem
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
+# define pm_message_t                      u32
+# define pci_choose_state(pci_dev, state)  (state)
+# define PCI_D0                            (0)
+# define assert_spin_locked(foobar)
+#endif
+
+/* Since v4l-dvb now includes it's own copy of linux/i2c-id.h these
+   are no longer necessary */
+/*
+#if !defined(I2C_ALGO_SAA7134)
+#define I2C_ALGO_SAA7134 I2C_HW_B_BT848
+#endif
+#if !defined(I2C_HW_B_CX2388x)
+# define I2C_HW_B_CX2388x I2C_HW_B_BT848
+#endif
+#if !defined(I2C_HW_SAA7134)
+# define I2C_HW_SAA7134 I2C_ALGO_SAA7134
+#endif
+#if !defined(I2C_HW_SAA7146)
+# define I2C_HW_SAA7146 I2C_ALGO_SAA7146
+#endif
+#if !defined(I2C_HW_B_EM2820)
+#define I2C_HW_B_EM2820 0x99
+#endif
+*/
+
+#ifndef I2C_M_IGNORE_NAK
+# define I2C_M_IGNORE_NAK 0x1000
+#endif
+
+/* v4l-dvb uses an out of kernel copy of i2c-id.h, which does not have
+   some stuff that previous versions of i2c-id.h defined. */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) && defined(LINUX_I2C_ID_H)
+# define I2C_ALGO_BIT 0x010000
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9)
+#define __le32 __u32
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7))
+static inline unsigned long msecs_to_jiffies(const unsigned int m)
+{
+#if HZ <= 1000 && !(1000 % HZ)
+	return (m + (1000 / HZ) - 1) / (1000 / HZ);
+#else
+#if HZ > 1000 && !(HZ % 1000)
+	return m * (HZ / 1000);
+#else
+	return (m * HZ + 999) / 1000;
+#endif
+#endif
+}
+static inline unsigned int jiffies_to_msecs(const unsigned long j)
+{
+#if HZ <= 1000 && !(1000 % HZ)
+	return (1000 / HZ) * j;
+#else
+#if HZ > 1000 && !(HZ % 1000)
+	return (j + (HZ / 1000) - 1)/(HZ / 1000);
+#else
+	return (j * 1000) / HZ;
+#endif
+#endif
+}
+static inline void msleep(unsigned int msecs)
+{
+	unsigned long timeout = msecs_to_jiffies(msecs);
+	while (timeout) {
+		set_current_state(TASK_UNINTERRUPTIBLE);
+		timeout = schedule_timeout(timeout);
+	}
+}
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) && LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9)
+static inline unsigned long msleep_interruptible(unsigned int msecs)
+{
+	unsigned long timeout = msecs_to_jiffies(msecs);
+
+	while (timeout) {
+		set_current_state(TASK_INTERRUPTIBLE);
+		timeout = schedule_timeout(timeout);
+	}
+	return jiffies_to_msecs(timeout);
+}
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
+/* some keys from 2.6.x which are not (yet?) in 2.4.x */
+# define KEY_PLAY                207
+# define KEY_PRINT		 210
+# define KEY_EMAIL         215
+# define KEY_SEARCH              217
+# define KEY_SELECT 		 0x161
+# define KEY_GOTO                0x162
+# define KEY_INFO                0x166
+# define KEY_CHANNEL             0x16b
+# define KEY_LANGUAGE            0x170
+# define KEY_SUBTITLE		 0x172
+# define KEY_ZOOM                0x174
+# define KEY_MODE		 0x175
+# define KEY_TV                  0x179
+# define KEY_CD                  0x17f
+# define KEY_TUNER               0x182
+# define KEY_TEXT                0x184
+# define KEY_DVD		 0x185
+# define KEY_AUDIO               0x188
+# define KEY_VIDEO               0x189
+# define KEY_RED                 0x18e
+# define KEY_GREEN               0x18f
+# define KEY_YELLOW              0x190
+# define KEY_BLUE                0x191
+# define KEY_CHANNELUP           0x192
+# define KEY_CHANNELDOWN         0x193
+# define KEY_RESTART		 0x198
+# define KEY_SHUFFLE     	 0x19a
+# define KEY_NEXT                0x197
+# define KEY_RADIO               0x181
+# define KEY_PREVIOUS            0x19c
+# define KEY_MHP                 0x16f
+# define KEY_EPG                 0x16d
+# define KEY_FASTFORWARD         208
+# define KEY_LIST                0x18b
+# define KEY_LAST                0x195
+# define KEY_CLEAR               0x163
+# define KEY_AUX                 0x186
+# define KEY_SCREEN              0x177
+# define KEY_PC                  0x178
+# define KEY_MEDIA               226
+# define KEY_SLOW                0x199
+# define KEY_OK                  0x160
+# define KEY_DIGITS              0x19d
+#endif
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14)
+# define KEY_SEND		231
+# define KEY_REPLY		232
+# define KEY_FORWARDMAIL	233
+# define KEY_SAVE		234
+# define KEY_DOCUMENTS		235
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+#define container_of(ptr, type, member) ({                      \
+	const typeof( ((type *)0)->member ) *__mptr = (ptr);    \
+	(type *)( (char *)__mptr - offsetof(type,member) );})
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10)
+#include <linux/mm.h>
+static inline unsigned long vmalloc_to_pfn(void * vmalloc_addr)
+{
+    return page_to_pfn(vmalloc_to_page(vmalloc_addr));
+}
+
+static unsigned long kvirt_to_pa(unsigned long adr)
+{
+	unsigned long kva, ret;
+
+	kva = (unsigned long) page_address(vmalloc_to_page((void *)adr));
+	kva |= adr & (PAGE_SIZE-1); /* restore the offset */
+	ret = __pa(kva);
+	return ret;
+}
+
+#ifndef wait_event_timeout
+#define wait_event_timeout(wq, condition, timeout)                   	     \
+({                                                                           \
+     long __ret = timeout;                                                   \
+     if (!(condition))                                                       \
+     do {                                                                    \
+	     DEFINE_WAIT(__wait);                                            \
+	     for (;;) {                                                      \
+		     prepare_to_wait(&wq, &__wait, TASK_UNINTERRUPTIBLE);    \
+		     if (condition)                                          \
+			 break;                                              \
+		     __ret = schedule_timeout(__ret);                        \
+		     if (!__ret)                                             \
+			 break;                                              \
+	     }                                                               \
+	     finish_wait(&wq, &__wait);                                      \
+     } while (0);							     \
+     __ret;                                                                  \
+})
+#endif
+
+#define remap_pfn_range remap_page_range
+
+#endif
+
+/* vm_insert_page() was added in 2.6.15 */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15) && defined(_LINUX_MM_H)
+static inline int vm_insert_page(struct vm_area_struct *vma,
+	unsigned long addr, struct page *page)
+{
+	return remap_pfn_range(vma, addr, page_to_pfn(page), PAGE_SIZE,
+			       vma->vm_page_prot);
+}
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9)
+#ifndef kcalloc
+#define kcalloc(n,size,flags)			\
+({						\
+  void * __ret = NULL;				\
+  __ret = kmalloc(n * size, flags);		\
+  if (__ret)					\
+	 memset(__ret, 0, n * size);		\
+  __ret;					\
+})
+#endif
+#endif
+
+/* try_to_freeze() lost its argument.  Must appear after linux/sched.h */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,13) && defined(_LINUX_SCHED_H)
+# if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
+#  define try_to_freeze() try_to_freeze(PF_FREEZE)
+# else
+#  define try_to_freeze() (0)
+# endif
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14)
+#ifndef kzalloc
+#define kzalloc(size, flags)				\
+({							\
+	void *__ret = kmalloc(size, flags);		\
+	if (__ret)					\
+		memset(__ret, 0, size);			\
+	__ret;						\
+})
+#endif
+#endif
+
+/* The class_device system didn't appear until 2.5.69 */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
+#define class_device_create_file(a, b) (0)
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,13)
+# define class_device_create(a, b, c, d, e, f, g, h) class_simple_device_add(a, c, d, e, f, g, h)
+# define class_device_destroy(a, b) class_simple_device_remove(b)
+# define class_create(a, b) class_simple_create(a, b)
+# define class_destroy(a) class_simple_destroy(a)
+#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15)
+# define class_device_create(a, b, c, d, e, f, g, h) class_device_create(a, c, d, e, f, g, h)
+#endif
+/* device_create/destroy added in 2.6.18 */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)
+/* on older kernels, class_device_create will in turn be a compat macro */
+# define device_create(a, b, c, d, e, f, g) class_device_create(a, NULL, c, b, d, e, f, g)
+# define device_destroy(a, b) class_device_destroy(a, b)
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15)
+# define input_allocate_device() kzalloc(sizeof(struct input_dev),GFP_KERNEL);
+# define input_free_device(input_dev) kfree(input_dev)
+# ifdef _INPUT_H  /* input.h must be included _before_ compat.h for this to work */
+   /* input_register_device() was changed to return an error code in 2.6.15 */
+#  define input_register_device(x) (input_register_device(x), 0)
+# endif
+#endif
+
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,15)
+#define DEFINE_MUTEX(a) DECLARE_MUTEX(a)
+#define mutex_lock_interruptible(a) down_interruptible(a)
+#define mutex_unlock(a) up(a)
+#define mutex_lock(a) down(a)
+#define mutex_init(a) init_MUTEX(a)
+#define mutex_trylock(a) down_trylock(a)
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) && defined(_LINUX_SCHED_H)
+static inline signed long __sched
+schedule_timeout_interruptible(signed long timeout)
+{
+	__set_current_state(TASK_INTERRUPTIBLE);
+	return schedule_timeout(timeout);
+}
+#endif
+
+/* New 4GB DMA zone was added in 2.6.15-rc2 */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15)
+#  define __GFP_DMA32	__GFP_DMA
+#endif
+
+/* setup_timer() helper added 10/31/05, 2.6.15-rc1 */
+/* Need linux/timer.h to be included for struct timer_list */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15) && defined(_LINUX_TIMER_H)
+static inline void setup_timer(struct timer_list * timer,
+			       void (*function)(unsigned long),
+			       unsigned long data)
+{
+	timer->function = function;
+	timer->data = data;
+	init_timer(timer);
+}
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)
+#define IRQF_SHARED		SA_SHIRQ
+#define IRQF_DISABLED		SA_INTERRUPT
+#endif
+
+/* linux/usb.h must be included _before_ compat.h for this code to get
+   turned on.  We can not just include usb.h here, because there is a
+   lot of code which will not compile if it has usb.h included, due to
+   conflicts with symbol names.  */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,13) && \
+    defined(__LINUX_USB_H) && defined(_INPUT_H)
+#include <linux/input.h>
+/* Found in linux/usb_input.h in 2.6.13 */
+/* Moved to linux/usb/input.h in 2.6.18 */
+static inline void
+usb_to_input_id(const struct usb_device *dev, struct input_id *id)
+{
+	id->bustype = BUS_USB;
+	id->vendor = le16_to_cpu(dev->descriptor.idVendor);
+	id->product = le16_to_cpu(dev->descriptor.idProduct);
+	id->version = le16_to_cpu(dev->descriptor.bcdDevice);
+}
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
+# define PCIAGP_FAIL 0
+
+#define vmalloc_32_user(a) vmalloc_32(a)
+
+#endif
+
+/* bool type and enum-based definition of true and false was added in 2.6.19 */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
+typedef int bool;
+#define true 1
+#define false 0
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22)
+#define sony_pic_camera_command(a,b) sonypi_camera_command(a,b)
+
+#define SONY_PIC_COMMAND_SETCAMERAAGC        SONYPI_COMMAND_SETCAMERAAGC
+#define SONY_PIC_COMMAND_SETCAMERABRIGHTNESS SONYPI_COMMAND_SETCAMERABRIGHTNESS
+#define SONY_PIC_COMMAND_SETCAMERACOLOR      SONYPI_COMMAND_SETCAMERACOLOR
+#define SONY_PIC_COMMAND_SETCAMERACONTRAST   SONYPI_COMMAND_SETCAMERACONTRAST
+#define SONY_PIC_COMMAND_SETCAMERAHUE        SONYPI_COMMAND_SETCAMERAHUE
+#define SONY_PIC_COMMAND_SETCAMERAPICTURE    SONYPI_COMMAND_SETCAMERAPICTURE
+#define SONY_PIC_COMMAND_SETCAMERASHARPNESS  SONYPI_COMMAND_SETCAMERASHARPNESS
+#define SONY_PIC_COMMAND_SETCAMERA           SONYPI_COMMAND_SETCAMERA
+#endif
+
+/* Parameter to pci_match_device() changed in 2.6.13-rc2 */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,13) && defined(LINUX_PCI_H)
+#define pci_match_device(drv, dev)	pci_match_device((drv)->id_table, dev)
+#endif
+
+/* pci_dev got a new revision field in 2.6.23-rc1 */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) && defined(LINUX_PCI_H)
+/* Just make it easier to subsitute pci_dev->revision with
+ * v4l_compat_pci_rev(pci_dev).  It's too bad there isn't some kind of context
+ * sensitive macro in C that could do this for us.  */
+static inline u8 v4l_compat_pci_rev(struct pci_dev *pci)
+{ u8 rev; pci_read_config_byte(pci, PCI_REVISION_ID, &rev); return rev; }
+#endif
+
+/* ALSA removed a bunch of typedefs and renamed some structs in 2.6.16 */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16)
+# ifdef __SOUND_CORE_H
+#  define snd_card _snd_card /* struct _snd_card became struct snd_card */
+#  define snd_pcm _snd_pcm
+#  undef snd_device
+#  define snd_device _snd_device
+# endif
+# ifdef __SOUND_PCM_H
+#  define snd_pcm_substream _snd_pcm_substream
+#  define snd_pcm_hardware _snd_pcm_hardware
+#  define snd_pcm_runtime _snd_pcm_runtime
+#  define snd_pcm_ops _snd_pcm_ops
+# endif
+# ifdef __SOUND_ASOUND_H
+#  define snd_pcm_hw_params sndrv_pcm_hw_params
+#  define snd_ctl_elem_info sndrv_ctl_elem_info
+#  define snd_ctl_elem_value sndrv_ctl_elem_value
+# endif
+# ifdef __SOUND_CONTROL_H
+#  undef snd_kcontrol
+#  define snd_kcontrol _snd_kcontrol
+#  define snd_kcontrol_new _snd_kcontrol_new
+# endif
+#endif
+
+#if defined(COMPAT_PCM_TO_RATE_BIT) && defined(__SOUND_PCM_H)
+/* New alsa core utility function */
+static inline unsigned int snd_pcm_rate_to_rate_bit(unsigned int rate)
+{
+	static const unsigned int rates[] = { 5512, 8000, 11025, 16000, 22050,
+		32000, 44100, 48000, 64000, 88200, 96000, 176400, 192000 };
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(rates); i++)
+		if (rates[i] == rate)
+			return 1u << i;
+	return SNDRV_PCM_RATE_KNOT;
+}
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
+# define task_pid_nr(current) ((current)->pid)
+
+# define sg_init_table(a,b)
+# define sg_page(p) (sg->page)
+# define sg_set_page(sglist,pg,sz,off)					\
+do {									\
+	struct scatterlist *p=sglist;					\
+	p->page   = pg;							\
+	p->length = sz;							\
+	p->offset = off;						\
+} while (0)
+#endif
+
+#ifndef BIT_MASK
+# define BIT_MASK(nr)            (1UL << ((nr) % BITS_PER_LONG))
+# define BIT_WORD(nr)            ((nr) / BITS_PER_LONG)
+#endif
+
+#endif
+/*
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */
diff --git a/drivers/media/dvb/dvb-usb/a867_debug.h b/drivers/media/dvb/dvb-usb/a867_debug.h
new file mode 100644
index 0000000..bda23fe
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_debug.h
@@ -0,0 +1,4 @@
+
+// turn on/off debug for all modules
+#define	CONFIG_DVB_USB_DEBUG	0	
+
diff --git a/drivers/media/dvb/dvb-usb/a867_demodulator.c b/drivers/media/dvb/dvb-usb/a867_demodulator.c
new file mode 100644
index 0000000..9192004
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_demodulator.c
@@ -0,0 +1,540 @@
+#include "a867_demodulator.h"
+
+
+Dword Demodulator_writeRegister (
+      Demodulator*    demodulator,
+      Byte            chip,
+      Processor       processor,
+      Dword           registerAddress,
+      Byte            value
+) {
+    return (Standard_writeRegister (demodulator, chip, processor, registerAddress, value));
+}
+
+
+Dword Demodulator_writeRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+) {
+    return (Standard_writeRegisters (demodulator, chip, processor, registerAddress, bufferLength, buffer));
+}
+
+
+Dword Demodulator_writeScatterRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Byte            valueSetsLength,
+    IN  ValueSet*       valueSets
+) {
+    return (Standard_writeScatterRegisters (demodulator, chip, processor, valueSetsLength, valueSets));
+}
+
+
+Dword Demodulator_writeTunerRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Word            registerAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+) {
+    return (Standard_writeTunerRegisters (demodulator, chip, registerAddress, bufferLength, buffer));
+}
+
+
+Dword Demodulator_writeGenericRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            interfaceIndex,
+    IN  Byte            slaveAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+) {
+    return (Standard_writeGenericRegisters (demodulator, chip, interfaceIndex, slaveAddress, bufferLength, buffer));
+}
+
+
+Dword Demodulator_writeEepromValues (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Word            registerAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+) {
+    return (Standard_writeEepromValues (demodulator, chip, registerAddress, bufferLength, buffer));
+}
+
+
+Dword Demodulator_writeRegisterBits (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            position,
+    IN  Byte            length,
+    IN  Byte            value
+)
+{
+    return (Standard_writeRegisterBits (demodulator, chip, processor, registerAddress, position, length, value));
+}
+
+
+Dword Demodulator_readRegister (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    OUT Byte*           value
+) {
+    return (Standard_readRegister (demodulator, chip, processor, registerAddress, value));
+}
+
+
+Dword Demodulator_readRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            bufferLength,
+    OUT Byte*           buffer
+) {
+    return (Standard_readRegisters (demodulator, chip, processor, registerAddress, bufferLength, buffer));
+}
+
+
+Dword Demodulator_readScatterRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Byte            valueSetsLength,
+    OUT ValueSet*       valueSets
+) {
+    return (Standard_readScatterRegisters (demodulator, chip, processor, valueSetsLength, valueSets));
+}
+
+
+Dword Demodulator_readTunerRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Word            registerAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+) {
+    return (Standard_readTunerRegisters (demodulator, chip, registerAddress, bufferLength, buffer));
+}
+
+
+Dword Demodulator_readGenericRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            interfaceIndex,
+    IN  Byte            slaveAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+) {
+    return (Standard_readGenericRegisters (demodulator, chip, interfaceIndex, slaveAddress, bufferLength, buffer));
+}
+
+
+Dword Demodulator_readEepromValues (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Word            registerAddress,
+    IN  Byte            bufferLength,
+    OUT Byte*           buffer
+) {
+    return (Standard_readEepromValues (demodulator, chip, registerAddress, bufferLength, buffer));
+}
+
+
+Dword Demodulator_readRegisterBits (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            position,
+    IN  Byte            length,
+    OUT Byte*           value
+) {
+    return (Standard_readRegisterBits (demodulator, chip, processor, registerAddress, position, length, value));
+}
+
+
+Dword Demodulator_getHardwareVersion (
+    IN  Demodulator*    demodulator,
+    OUT Dword*          version
+) {
+    return (Standard_getHardwareVersion (demodulator, version));
+}
+
+
+Dword Demodulator_getFirmwareVersion (
+    IN  Demodulator*    demodulator,
+    IN  Processor       processor,
+    OUT Dword*          version
+) {
+    return (Standard_getFirmwareVersion (demodulator, processor, version));
+}
+
+
+Dword Demodulator_getRfAgcGain (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Byte*           rfAgc
+) {
+    return (Standard_getRfAgcGain (demodulator, chip, rfAgc));
+}
+
+
+Dword Demodulator_getIfAgcGain (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Byte*           ifAgc
+) {
+    return (Standard_getIfAgcGain (demodulator, chip, ifAgc));
+}
+
+
+Dword Demodulator_controlPidFilter (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            control
+) {
+    return (Standard_controlPidFilter (demodulator, chip, control));
+}
+
+
+Dword Demodulator_addPidToFilter (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            index,
+    IN  Pid             pid
+) {
+    return (Standard_addPidToFilter (demodulator, chip, index, pid));
+}
+
+
+Dword Demodulator_resetPidFilter (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip
+) {
+    return (Standard_resetPidFilter (demodulator, chip));
+}
+
+
+Dword Demodulator_loadIrTable (
+    IN  Demodulator*    demodulator,
+    IN  Word            tableLength,
+    IN  Byte*           table
+) {
+    return (Standard_loadIrTable (demodulator, tableLength, table));
+}
+
+
+Dword Demodulator_loadFirmware (
+    IN  Demodulator*    demodulator,
+    IN  Byte*           firmwareCodes,
+    IN  Segment*        firmwareSegments,
+    IN  Byte*           firmwarePartitions
+) {
+
+    return (Standard_loadFirmware (demodulator, firmwareCodes, firmwareSegments, firmwarePartitions));
+}
+
+
+Dword Demodulator_initialize (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chipNumber,
+    IN  Word            sawBandwidth,
+    IN  StreamType      streamType,
+    IN  Architecture    architecture
+) {
+    return (Standard_initialize (demodulator, chipNumber, sawBandwidth, streamType, architecture));
+}
+
+
+Dword Demodulator_finalize (
+    IN  Demodulator*    demodulator
+) {
+    return (Standard_finalize (demodulator));
+}
+
+
+Dword Demodulator_isAgcLocked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+) {
+    return (Standard_isAgcLocked (demodulator, chip, locked));
+}
+
+
+Dword Demodulator_isCfoeLocked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+) {
+    return (Standard_isCfoeLocked (demodulator, chip, locked));
+}
+
+
+Dword Demodulator_isSfoeLocked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+) {
+    return (Standard_isSfoeLocked (demodulator, chip, locked));
+}
+
+
+Dword Demodulator_isTpsLocked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+) {
+    return (Standard_isTpsLocked (demodulator, chip, locked));
+}
+
+
+Dword Demodulator_isMpeg2Locked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+) {
+    return (Standard_isMpeg2Locked (demodulator, chip, locked));
+}
+
+
+Dword Demodulator_isLocked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+)
+{
+    return (Standard_isLocked (demodulator, chip, locked));
+}
+
+
+Dword Demodulator_setPriority (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Priority        priority
+)
+{
+    return (Standard_setPriority (demodulator, chip, priority));
+}
+
+
+Dword Demodulator_reset (
+    IN  Demodulator*    demodulator
+) {
+    return (Standard_reset (demodulator));
+}
+
+
+Dword Demodulator_getChannelModulation (
+    IN  Demodulator*            demodulator,
+    IN  Byte                    chip,
+    OUT ChannelModulation*      channelModulation
+) {
+    return (Standard_getChannelModulation (demodulator, chip, channelModulation));
+}
+
+
+Dword Demodulator_setChannelModulation (
+    IN  Demodulator*            demodulator,
+    IN  Byte                    chip,
+    IN  ChannelModulation*      channelModulation
+) {
+    return (Standard_setChannelModulation (demodulator, chip, channelModulation));
+}
+
+
+Dword Demodulator_acquireChannel (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Word            bandwidth,
+    IN  Dword           frequency
+) {
+    return (Standard_acquireChannel (demodulator, chip, bandwidth, frequency));
+}
+
+
+Dword Demodulator_setStreamType (
+    IN  Demodulator*    demodulator,
+    IN  StreamType      streamType
+) {
+    return (Standard_setStreamType (demodulator, streamType));
+}
+
+
+Dword Demodulator_setArchitecture (
+    IN  Demodulator*    demodulator,
+    IN  Architecture    architecture
+) {
+    return (Standard_setArchitecture (demodulator, architecture));
+}
+
+
+Dword Demodulator_getSignalQuality (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Byte*           quality
+) {
+    return (Standard_getSignalQuality (demodulator, chip, quality));
+}
+
+
+Dword Demodulator_getSignalStrength (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Byte*           strength
+) {
+    return (Standard_getSignalStrength (demodulator, chip, strength));
+}
+
+
+Dword Demodulator_getSignalStrengthDbm (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Long            rfpullUpVolt_X10,     /** RF pull up voltage multiplied by 10 */
+    IN  Long            ifpullUpVolt_X10,     /** IF pull up voltage multiplied by 10 */
+    OUT Long*           strengthDbm           /** DBm                                */
+) {
+    return (Standard_getSignalStrengthDbm (demodulator, chip, rfpullUpVolt_X10, ifpullUpVolt_X10, strengthDbm));
+}
+
+Dword Demodulator_getPostVitBer (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Dword*          postErrorCount,  /** 24 bits */
+    OUT Dword*          postBitCount,    /** 16 bits */
+    OUT Word*           abortCount
+){
+	return (Standard_getPostVitBer(demodulator, chip, postErrorCount, postBitCount, abortCount));
+}
+
+
+Dword Demodulator_setStatisticRange (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            superFrameCount,
+    IN  Word            packetUnit
+) {
+    return (Standard_setStatisticRange (demodulator, chip, superFrameCount, packetUnit));
+}
+
+
+Dword Demodulator_getStatisticRange (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte*           superFrameCount,
+    IN  Word*           packetUnit
+) {
+    return (Standard_getStatisticRange (demodulator, chip, superFrameCount, packetUnit));
+}
+
+
+Dword Demodulator_getStatistic (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Statistic*      statistic
+) {
+    return (Standard_getStatistic (demodulator, chip, statistic));
+}
+
+
+Dword Demodulator_getInterrupts (
+    IN  Demodulator*    demodulator,
+    OUT Interrupts*     interrupts
+) {
+    return (Standard_getInterrupts (demodulator, interrupts));
+}
+
+
+Dword Demodulator_clearInterrupt (
+    IN  Demodulator*    demodulator,
+    IN  Interrupt       interrupt
+) {
+    return (Standard_clearInterrupt (demodulator, interrupt));
+}
+
+
+Dword Demodulator_getDataLength (
+    IN  Demodulator*    demodulator,
+    OUT Dword*          dataLength,
+    OUT Bool*           valid
+) {
+    return (Standard_getDataLength (demodulator, dataLength, valid));
+}
+
+
+//jamie: The function is unused.
+Dword Demodulator_getData (
+    IN  Demodulator*    demodulator,
+    IN  Dword           bufferLength,
+    OUT Byte*           buffer
+) {
+    return (Standard_getData (demodulator, bufferLength, buffer));
+}
+
+//jamie: The function is unused.
+Dword Demodulator_getDatagram (
+    IN  Demodulator*    demodulator,
+    OUT Dword*          bufferLength,
+    OUT Byte*           buffer
+) {
+    return (Standard_getDatagram (demodulator, bufferLength, buffer));
+}
+
+
+Dword Demodulator_getIrCode (
+    IN  Demodulator*    demodulator,
+    OUT Dword*          code
+)  {
+    return (Standard_getIrCode (demodulator, code));
+}
+
+
+Dword Demodulator_reboot (
+    IN  Demodulator*    demodulator
+)  {
+    return (Standard_reboot (demodulator));
+}
+
+
+Dword Demodulator_controlPowerSaving (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            control
+) {
+    return (Standard_controlPowerSaving (demodulator, chip, control));
+}
+
+
+Dword Demodulator_controlTunerPowerSaving (
+    IN  Demodulator*    demodulator,
+    IN  Byte            control
+) {
+    return (Standard_controlTunerPowerSaving (demodulator, control));
+}
+
+
+Dword Demodulator_setBurstSize (
+    IN  Demodulator*    demodulator,
+    IN  BurstSize       burstSize
+) {
+    return (Standard_setBurstSize (demodulator, burstSize));
+}
+
+
+Dword Demodulator_getBurstSize (
+    IN  Demodulator*    demodulator,
+    IN  BurstSize*      burstSize
+) {
+    return (Standard_getBurstSize (demodulator, burstSize));
+}
diff --git a/drivers/media/dvb/dvb-usb/a867_demodulator.h b/drivers/media/dvb/dvb-usb/a867_demodulator.h
new file mode 100644
index 0000000..323cb2b
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_demodulator.h
@@ -0,0 +1,1495 @@
+#ifndef __GANYMEDE_H__
+#define __GANYMEDE_H__
+
+
+#include "a867_type.h"
+#include "a867_user.h"
+#include "a867_error.h"
+#include "a867_register.h"
+#include "a867_variable.h"
+#include "a867_cmd.h"
+#include "a867_standard.h"
+#include "a867_demodulatorextend.h"  /** release1remove */
+#include "a867_version.h"
+
+/**
+ * Write one byte (8 bits) to a specific register in demodulator.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param processor The processor of specified register. Because each chip
+ *        has two processor so user have to specify the processor. The
+ *        possible values are Processor_LINK and Processor_OFDM.
+ * @param registerAddress the address of the register to be written.
+ * @param value the value to be written.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Ganymede ganymede;
+ *
+ *     // Set the value of register 0xA000 in demodulator to 0.
+ *     error = Demodulator_writeRegister ((Demodulator*) &ganymede, 0, Processor_LINK, 0xA000, 0);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_writeRegister (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            value
+);
+
+
+/**
+ * Write a sequence of bytes to the contiguous registers in demodulator.
+ * The maximum burst size is restricted by the capacity of bus. If bus
+ * could transfer N bytes in one cycle, then the maximum value of
+ * bufferLength would be N - 5.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param processor The processor of specified register. Because each chip
+ *        has two processor so user have to specify the processor. The
+ *        possible values are Processor_LINK and Processor_OFDM.
+ * @param registerAddress the start address of the registers to be written.
+ * @param bufferLength the number of registers to be written.
+ * @param buffer a byte array which is used to store values to be written.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Byte buffer[3] = { 0x00, 0x01, 0x02 };
+ *     Ganymede ganymede;
+ *
+ *     // Set the value of register 0xA000 in demodulator to 0.
+ *     // Set the value of register 0xA001 in demodulator to 1.
+ *     // Set the value of register 0xA002 in demodulator to 2.
+ *     error = Demodulator_writeRegisters ((Demodulator*) &ganymede, 0, Processor_LINK, 0xA000, 3, buffer);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_writeRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+);
+
+
+/**
+ * Write a collection of values to discontiguous registers in demodulator.
+ * The maximum burst size is restricted by the capacity of bus. If bus
+ * could transfer N bytes in one cycle, then the maximum value of
+ * bufferLength would be N - 6 (one more byte to specify tuner address).
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param processor The processor of specified register. Because each chip
+ *        has two processor so user have to specify the processor. The
+ *        possible values are Processor_LINK and Processor_OFDM.
+ * @param valueSetsLength the number of values to be written.
+ * @param valueSets a ValueSet array which is used to store values to be
+ *        written.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     ValueSet valueSet[3];
+ *     Ganymede ganymede;
+ *
+ *     // Get the value of register 0xA000, 0xA001 and 0xA002 in demodulator.
+ *     valueSet[0].address = 0xA000;
+ *     valueSet[0].value = 0x00;
+ *     valueSet[1].address = 0xA001;
+ *     valueSet[1].value = 0x01;
+ *     valueSet[2].address = 0xA002;
+ *     valueSet[2].value = 0x02;
+ *     error = Demodulator_writeScatterRegisters ((Demodulator*) &ganymede, 0, Processor_LINK, 3, valueSet);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_writeScatterRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Byte            valueSetsLength,
+    IN  ValueSet*       valueSets
+);
+
+
+/**
+ * Write a sequence of bytes to the contiguous registers in slave device.
+ * The maximum burst size is restricted by the capacity of bus. If bus
+ * could transfer N bytes in one cycle, then the maximum value of
+ * bufferLength would be N - 6 (one more byte to specify tuner address).
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param registerAddress the start address of the registers to be read.
+ * @param bufferLength the number of registers to be read.
+ * @param buffer a byte array which is used to store values to be read.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Byte buffer[3] = { 0x00, 0x01, 0x02 };
+ *     Ganymede ganymede;
+ *
+ *     // Set the value of register 0x0000 in tuner to 0.
+ *     // Set the value of register 0x0001 in tuner to 1.
+ *     // Set the value of register 0x0002 in tuner to 2.
+ *     error = Demodulator_writeTunerRegistersWithAddress ((Demodulator*) &ganymede, 0, 0x38, 0x00, 1, 3, buffer);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_writeTunerRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Word            registerAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+);
+
+
+/**
+ * Write a sequence of bytes to the contiguous registers in slave device
+ * through specified interface (1, 2, 3).
+ * The maximum burst size is restricted by the capacity of bus. If bus
+ * could transfer N bytes in one cycle, then the maximum value of
+ * bufferLength would be N - 6 (one more byte to specify tuner address).
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param interfaceIndex the index of interface. The possible values are
+ *        1~3.
+ * @param slaveAddress the I2c address of slave device.
+ * @param bufferLength the number of registers to be read.
+ * @param buffer a byte array which is used to store values to be read.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Demodulator_writeGenericRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            interfaceIndex,
+    IN  Byte            slaveAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+);
+
+
+/**
+ * Write a sequence of bytes to the contiguous cells in the EEPROM.
+ * The maximum burst size is restricted by the capacity of bus. If bus
+ * could transfer N bytes in one cycle, then the maximum value of
+ * bufferLength would be N - 5 (firmware will detect EEPROM address).
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param registerAddress the start address of the cells to be written.
+ * @param registerAddressLength the valid bytes of registerAddress.
+ * @param bufferLength the number of cells to be written.
+ * @param buffer a byte array which is used to store values to be written.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Byte buffer[3] = { 0x00, 0x01, 0x02 };
+ *     Ganymede ganymede;
+ *
+ *     // Set the value of cell 0x0000 in EEPROM to 0.
+ *     // Set the value of cell 0x0001 in EEPROM to 1.
+ *     // Set the value of cell 0x0002 in EEPROM to 2.
+ *     error = Demodulator_writeEepromValues ((Demodulator*) &ganymede, 0, 0x0000, 3, buffer);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_writeEepromValues (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Word            registerAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+);
+
+
+/**
+ * Modify bits in the specific register.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param processor The processor of specified register. Because each chip
+ *        has two processor so user have to specify the processor. The
+ *        possible values are Processor_LINK and Processor_OFDM.
+ * @param registerAddress the address of the register to be written.
+ * @param position the start position of bits to be modified (0 means the
+ *        LSB of the specifyed register).
+ * @param length the length of bits.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Ganymede ganymede;
+ *
+ *     // Modify the LSB of register 0xA000 in demodulator to 0.
+ *     error = Demodulator_writeRegisterBits ((Demodulator*) &ganymede, 0, Processor_LINK, 0xA000, 0, 1, 0);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_writeRegisterBits (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            position,
+    IN  Byte            length,
+    IN  Byte            value
+);
+
+
+/**
+ * Read one byte (8 bits) from a specific register in demodulator.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param processor The processor of specified register. Because each chip
+ *        has two processor so user have to specify the processor. The
+ *        possible values are Processor_LINK and Processor_OFDM.
+ * @param registerAddress the address of the register to be read.
+ * @param value the pointer used to store the value read from demodulator
+ *        register.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Byte value;
+ *     Ganymede ganymede;
+ *
+ *     // Get the value of register 0xA000 in demodulator.
+ *     error = Demodulator_readRegister ((Demodulator*) &ganymede, 0, Processor_LINK, 0xA000, &value);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ *     printf ("The value of 0xA000 is %2x", value);
+ * </pre>
+ */
+Dword Demodulator_readRegister (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    OUT Byte*           value
+);
+
+
+/**
+ * Read a sequence of bytes from the contiguous registers in demodulator.
+ * The maximum burst size is restricted by the capacity of bus. If bus
+ * could transfer N bytes in one cycle, then the maximum value of
+ * bufferLength would be N - 5.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param processor The processor of specified register. Because each chip
+ *        has two processor so user have to specify the processor. The
+ *        possible values are Processor_LINK and Processor_OFDM.
+ * @param registerAddress the address of the register to be read.
+ * @param bufferLength the number of registers to be read.
+ * @param buffer a byte array which is used to store values to be read.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Byte buffer[3];
+ *     Ganymede ganymede;
+ *
+ *     // Get the value of register 0xA000, 0xA001, 0xA002 in demodulator.
+ *     error = Demodulator_readRegisters ((Demodulator*) &ganymede, 0, Processor_LINK, 0xA000, 3, buffer);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ *     printf ("The value of 0xA000 is %2x", buffer[0]);
+ *     printf ("The value of 0xA001 is %2x", buffer[1]);
+ *     printf ("The value of 0xA002 is %2x", buffer[2]);
+ * </pre>
+ */
+Dword Demodulator_readRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            bufferLength,
+    OUT Byte*           buffer
+);
+
+
+/**
+ * Read a collection of values to discontiguous registers from demodulator.
+ * The maximum burst size is restricted by the capacity of bus. If bus
+ * could transfer N bytes in one cycle, then the maximum value of
+ * bufferLength would be N - 6 (one more byte to specify tuner address).
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param processor The processor of specified register. Because each chip
+ *        has two processor so user have to specify the processor. The
+ *        possible values are Processor_LINK and Processor_OFDM.
+ * @param valueSetsLength the number of values to be read.
+ * @param valueSets a ValueSet array which is used to store values to be
+ *        read.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     ValueSet valueSet[3];
+ *     Ganymede ganymede;
+ *
+ *     // Get the value of register 0xA000, 0xA001 and 0xA002 in demodulator.
+ *     valueSet[0].address = 0xA000;
+ *     valueSet[1].address = 0xA001;
+ *     valueSet[2].address = 0xA002;
+ *     error = Demodulator_readScatterRegisters ((Demodulator*) &ganymede, 0, Processor_LINK, 3, valueSet);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ *     printf ("The value of 0xA000 is %2x", valueSet[0].value);
+ *     printf ("The value of 0xA001 is %2x", valueSet[1].value);
+ *     printf ("The value of 0xA002 is %2x", valueSet[2].value);
+ * </pre>
+ */
+Dword Demodulator_readScatterRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Byte            valueSetsLength,
+    OUT ValueSet*       valueSets
+);
+
+
+/**
+ * Read a sequence of bytes from the contiguous registers in tuner.
+ * The maximum burst size is restricted by the capacity of bus. If bus
+ * could transfer N bytes in one cycle, then the maximum value of
+ * bufferLength would be N - 6 (one more byte to specify tuner address).
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param registerAddress the start address of the registers to be read.
+ * @param registerAddressLength the valid bytes of registerAddress.
+ * @param bufferLength the number of registers to be read.
+ * @param buffer a byte array which is used to store values to be read.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Byte buffer[3];
+ *     Ganymede ganymede;
+ *
+ *     // Get the value of register 0x0000, 0x0001, 0x0002 in tuner.
+ *     error = Demodulator_readTunerRegisters ((Demodulator*) &ganymede, 0, 0x0000, 3, buffer);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ *     printf ("The value of 0x0000 is %2x", buffer[0]);
+ *     printf ("The value of 0x0001 is %2x", buffer[1]);
+ *     printf ("The value of 0x0002 is %2x", buffer[2]);
+ * </pre>
+ */
+Dword Demodulator_readTunerRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Word            registerAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+);
+
+
+/**
+ * Read a sequence of bytes from the contiguous registers in slave device
+ * through specified interface (1, 2, 3).
+ * The maximum burst size is restricted by the capacity of bus. If bus
+ * could transfer N bytes in one cycle, then the maximum value of
+ * bufferLength would be N - 6 (one more byte to specify tuner address).
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param interfaceIndex the index of interface. The possible values are
+ *        1~3.
+ * @param slaveAddress the I2c address of slave device.
+ * @param bufferLength the number of registers to be read.
+ * @param buffer a byte array which is used to store values to be read.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Demodulator_readGenericRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            interfaceIndex,
+    IN  Byte            slaveAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+);
+
+
+/**
+ * Read a sequence of bytes from the contiguous cells in the EEPROM.
+ * The maximum burst size is restricted by the capacity of bus. If bus
+ * could transfer N bytes in one cycle, then the maximum value of
+ * bufferLength would be N - 5 (firmware will detect EEPROM address).
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param registerAddress the start address of the cells to be read.
+ * @param registerAddressLength the valid bytes of registerAddress.
+ * @param bufferLength the number of cells to be read.
+ * @param buffer a byte array which is used to store values to be read.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Byte buffer[3];
+ *     Ganymede ganymede;
+ *
+ *     // Get the value of cell 0x0000, 0x0001, 0x0002 in EEPROM.
+ *     error = Demodulator_readEepromValues ((Demodulator*) &ganymede, 0, 0x0000, 3, buffer);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ *     printf ("The value of 0x0000 is %2x", buffer[0]);
+ *     printf ("The value of 0x0001 is %2x", buffer[1]);
+ *     printf ("The value of 0x0002 is %2x", buffer[2]);
+ * </pre>
+ */
+Dword Demodulator_readEepromValues (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Word            registerAddress,
+    IN  Byte            bufferLength,
+    OUT Byte*           buffer
+);
+
+
+/**
+ * Read bits of the specified register.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param processor The processor of specified register. Because each chip
+ *        has two processor so user have to specify the processor. The
+ *        possible values are Processor_LINK and Processor_OFDM.
+ * @param registerAddress the address of the register to be read.
+ * @param position the start position of bits to be read (0 means the
+ *        LSB of the specifyed register).
+ * @param length the length of bits.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Byte value;
+ *     Ganymede ganymede;
+ *
+ *     // Read the LSB of register 0xA000 in demodulator.
+ *     error = Demodulator_readRegisterBits ((Demodulator*) &ganymede, 0, Processor_LINK, 0xA000, 0, 1, &value);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ *     printf ("The value of LSB of 0xA000 is %2x", value);
+ * </pre>
+ */
+Dword Demodulator_readRegisterBits (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            position,
+    IN  Byte            length,
+    OUT Byte*           value
+);
+
+
+/**
+ * Get the version of hardware.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param version the version of hardware.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Dword version;
+ *     Ganymede ganymede;
+ *
+ *     // Add PID to PID filter.
+ *     error = Demodulator_getHardwareVersion ((Demodulator*) &ganymede, &version);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("The version of hardware is : %X", version);
+ * </pre>
+ */
+Dword Demodulator_getHardwareVersion (
+    IN  Demodulator*    demodulator,
+    OUT Dword*          version
+);
+
+
+/**
+ * Get the version of firmware.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param version the version of firmware.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Dword version;
+ *     Ganymede ganymede;
+ *
+ *     // Get the version of Link layer firmware.
+ *     error = Demodulator_getFirmwareVersion ((Demodulator*) &ganymede, Processor_LINK, &version);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("The version of firmware is : %X", version);
+ * </pre>
+ */
+Dword Demodulator_getFirmwareVersion (
+    IN  Demodulator*    demodulator,
+    IN  Processor       processor,
+    OUT Dword*          version
+);
+
+
+/**
+ * Add PID to PID filter.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param index the index of PID filter.
+ * @param pid the PID that will be add to PID filter.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Pid pid;
+ *     Ganymede ganymede;
+ *
+ *     pid.value = 0x0000;
+ *
+ *     // Add PID to PID filter.
+ *     error = Demodulator_addPidToFilter ((Demodulator*) &ganymede, 0, 1, pid);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_addPidToFilter (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            index,
+    IN  Pid             pid
+);
+
+
+/**
+ * Reset PID filter.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Ganymede ganymede;
+ *
+ *     error = Demodulator_resetPidFilter ((Demodulator*) &ganymede, 0);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_resetPidFilter (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip
+);
+
+
+/**
+ * Get datagram from device.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param bufferLength the number of registers to be read.
+ * @param buffer a byte array which is used to store values to be read.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @return Error_BUFFER_INSUFFICIENT: if buffer is too small.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Word bufferLength;
+ *     Byte buffer[4096];
+ *     Ganymede ganymede;
+ *
+ *     bufferLength = 4096;
+ *     error = Demodulator_getDatagram ((Demodulator*) &ganymede, &bufferLength, buffer);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_getDatagram (
+    IN  Demodulator*    demodulator,
+    OUT Dword*          bufferLength,
+    OUT Byte*           buffer
+);
+
+
+/**
+ * Get RF AGC gain.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param rfAgc the value of RF AGC.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Byte rfAgc;
+ *     Ganymede ganymede;
+ *
+ *     // Set I2C as the control bus.
+ *     error = Demodulator_getRfAgcGain ((Demodulator*) &ganymede, 0, rfAgc);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_getRfAgcGain (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Byte*           rfAgc
+);
+
+
+/**
+ * Get IF AGC.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param ifAgc the value of IF AGC.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Byte ifAgc;
+ *     Ganymede ganymede;
+ *
+ *     // Set I2C as the control bus.
+ *     error = Demodulator_getIfAgcGain ((Demodulator*) &ganymede, 0, ifAgc);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_getIfAgcGain (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Byte*           ifAgc
+);
+
+
+/**
+ * Load the IR table for USB device.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param tableLength The length of IR table.
+ * @param table The content of IR table.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_loadIrTable (
+    IN  Demodulator*    demodulator,
+    IN  Word            tableLength,
+    IN  Byte*           table
+);
+
+
+/**
+ * Load firmware to device
+ *
+ * @param demodulator the handle of demodulator.
+ * @firmwareCodes pointer to fw binary.
+ * @firmwareSegments pointer to fw segments.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Demodulator_loadFirmware (
+    IN  Demodulator*    demodulator,
+    IN  Byte*           firmwareCodes,
+    IN  Segment*        firmwareSegments,
+    IN  Byte*           firmwarePartitions
+);
+
+
+/**
+ * First, download firmware from host to demodulator. Actually, firmware is
+ * put in firmware.h as a part of source code. Therefore, in order to
+ * update firmware the host have to re-compile the source code.
+ * Second, setting all parameters which will be need at the beginning.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chipNumber The total number of demodulators.
+ * @param sawBandwidth SAW filter bandwidth in KHz. The possible values
+ *        are 6000, 7000, and 8000 (KHz).
+ * @param streamType The format of output stream.
+ * @param architecture the architecture of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Ganymede ganymede;
+ *
+ *     // Initialize demodulators.
+ *     // SAW Filter  : 8MHz
+ *     // Stream Type : IP Datagram.
+ *     error = Demodulator_initialize ((Demodulator*) &ganymede, 1, 8, StreamType_IP_DATAGRAM, Architecture_DCA);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_initialize (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chipNumber,
+    IN  Word            sawBandwidth,
+    IN  StreamType      streamType,
+    IN  Architecture    architecture
+);
+
+
+/**
+ * Power off the demodulators.
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Ganymede ganymede;
+ *
+ *     // Finalize demodulators.
+ *     error = Demodulator_finalize ((Demodulator*) &ganymede);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_finalize (
+    IN  Demodulator*    demodulator
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_isAgcLocked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_isCfoeLocked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_isSfoeLocked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_isTpsLocked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_isMpeg2Locked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7. NOTE: When the architecture is set to Architecture_DCA
+ *        this parameter is regard as don't care.
+ * @param locked the result of frequency tuning. True if there is
+ *        demodulator can lock signal, False otherwise.
+ * @see Demodulator_acquireChannel
+ */
+Dword Demodulator_isLocked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+);
+
+
+/**
+ * Set priorty of modulation.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param priority modulation priority.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Ganymede ganymede;
+ *
+ *     // Set priority.
+ *     error = Demodulator_setPriority ((Demodulator*) &ganymede, 0, Priority_HIGH);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_setPriority (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Priority        priority
+);
+
+
+/**
+ * Reset demodulator.
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Ganymede ganymede;
+ *
+ *     // Reset demodulator.
+ *     error = Demodulator_reset ((Demodulator*) &ganymede);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_reset (
+    IN  Demodulator*    demodulator
+);
+
+
+/**
+ * Get channel modulation related information.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param channelModulation The modulation of channel.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getChannelModulation (
+    IN  Demodulator*            demodulator,
+    IN  Byte                    chip,
+    OUT ChannelModulation*      channelModulation
+);
+
+
+/**
+ * Set channel modulation related information.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param channelModulation The modulation of channel.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_setChannelModulation (
+    IN  Demodulator*            demodulator,
+    IN  Byte                    chip,
+    IN  ChannelModulation*      channelModulation
+);
+
+
+/**
+ * Specify the bandwidth of channel and tune the channel to the specific
+ * frequency. Afterwards, host could use output parameter dvbH to determine
+ * if there is a DVB-H signal.
+ * In DVB-T mode, after calling this function the output parameter dvbH
+ * should return False and host could use output parameter "locked" to check
+ * if the channel has correct TS output.
+ * In DVB-H mode, after calling this function the output parameter dvbH should
+ * return True and host could start get platform thereafter.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7. NOTE: When the architecture is set to Architecture_DCA
+ *        this parameter is regard as don't care.
+ * @param bandwidth The channel bandwidth.
+ *        DVB-T: 5000, 6000, 7000, and 8000 (KHz).
+ *        DVB-H: 5000, 6000, 7000, and 8000 (KHz).
+ *        T-DMB: 5000, 6000, 7000, and 8000 (KHz).
+ *        FM: 100, and 200 (KHz).
+ * @param frequency the channel frequency in KHz.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Bool locked;
+ *     Ganymede ganymede;
+ *
+ *     error = Demodulator_acquireChannel ((Demodulator*) &ganymede, 0, 8000, 666000);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ *
+ *     error = Demodulator_isLocked ((Demodulator*) &ganymede, 0, &locked);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ *
+ *     if (locked == True) {
+ *         // In DVB-T mode.
+ *         // Start to process TS
+ *         // Because DVB-T could be multiplex with DVB-H
+ *     }
+ * </pre>
+ */
+Dword Demodulator_acquireChannel (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Word            bandwidth,
+    IN  Dword           frequency
+);
+
+
+
+/**
+ * Set the output stream type of chip. Because the device could output in
+ * many stream type, therefore host have to choose one type before receive
+ * data.
+ *
+ * Note: After host know all the available channels, and want to change to
+ *       specific channel, host have to choose output mode before receive
+ *       data. Please refer the example of Demodulator_setStreamType.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param streamType the possible values are
+ *        DVB-H:    StreamType_DVBH_DATAGRAM
+ *                  StreamType_DVBH_DATABURST
+ *        DVB-T:    StreamType_DVBT_DATAGRAM
+ *                  StreamType_DVBT_PARALLEL
+ *                  StreamType_DVBT_SERIAL
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Ganymede ganymede;
+ *
+ *     error = Demodulator_setStreamType ((Demodulator*) &ganymede, StreamType_DVBT_PARALLEL)
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_setStreamType (
+    IN  Demodulator*    demodulator,
+    IN  StreamType      streamType
+);
+
+
+/**
+ * Set the architecture of chip. When two of our device are using, they could
+ * be operated in Diversity Combine Architecture (DCA) or (PIP). Therefore,
+ * host could decide which mode to be operated.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param architecture the possible values are
+ *        Architecture_DCA
+ *        Architecture_PIP
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Ganymede ganymede;
+ *
+ *     // Set architecture.
+ *     error = Demodulator_setArchitecture ((Demodulator*) &ganymede, Architecture_DCA)
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_setArchitecture (
+    IN  Demodulator*    demodulator,
+    IN  Architecture    architecture
+);
+
+
+/**
+ * Get the length of Data
+ * In DVB-T mode, data length should always equals 2K,
+ * In DVB-H mode, data length would be the length of IP datagram.
+ * NOTE: data can't be transfer via I2C bus, in order to transfer data
+ * host must provide SPI bus.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param dataLength the length of data.
+ * @param valid True if the data length is valid.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @see Demodulator_addIp
+ */
+Dword Demodulator_getDataLength (
+    IN  Demodulator*    demodulator,
+    OUT Dword*          dataLength,
+    OUT Bool*           valid
+);
+
+
+/**
+ * Get the IP datagram of Data.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param bufferLength the length of buffer.
+ * @param buffer buffer used to get Data.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @see Demodulator_addIp
+ */
+Dword Demodulator_getData (
+    IN  Demodulator*    demodulator,
+    IN  Dword           bufferLength,
+    OUT Byte*           buffer
+);
+
+
+/**
+ * Get the type of interrupts.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param interrupts the type of interrupts.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Interrupt interrupts;
+ *     Ganymede ganymede;
+ *
+ *     // Get the type of interrupts.
+ *     error = Demodulator_getInterrupts ((Demodulator*) &ganymede, &interrupts);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ *     if (interrupts & Interrupt_VERSION) {
+ *         // Get IP version
+ *     }
+ *     if (interrupts & Interrupt_DVBH) {
+ *         // Get DVB-H Data
+ *     }
+ *     if (interrupts & Interrupt_DVBT) {
+ *         // Get DVB-T Data
+ *     }
+ *     if (interrupts & Interrupt_SIPSI) {
+ *         // Get SI/PSI
+ *     }
+ * </pre>
+ */
+Dword Demodulator_getInterrupts (
+    IN  Demodulator*    demodulator,
+    OUT Interrupts*     interrupts
+);
+
+
+/**
+ * Clear interrupts flag.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param interrupts interrupts flag.
+ * @param packetUnit the number of packet unit for Post-Viterbi.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Ganymede ganymede;
+ *
+ *     // Set statistic range.
+ *     error = Demodulator_clearInterrupt ((Demodulator*) &ganymede, Interrupt_SIPSI);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_clearInterrupt (
+    IN  Demodulator*    demodulator,
+    IN  Interrupt       interrupt
+);
+
+
+/**
+ * Get siganl quality.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7. NOTE: When the architecture is set to Architecture_DCA
+ *        this parameter is regard as don't care.
+ * @param quality The value of signal quality.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getSignalQuality (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Byte*           quality
+);
+
+
+/**
+ * Get signal strength
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param strength The value of signal strength.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getSignalStrength (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Byte*           strength
+);
+
+
+/**
+ * Get signal strength in dbm
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param rfpullUpVolt_X10 the pullup voltag of RF multiply 10.
+ * @param ifpullUpVolt_X10 the pullup voltag of IF multiply 10.
+ * @param strengthDbm The value of signal strength in DBm.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getSignalStrengthDbm (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Long            rfpullUpVolt_X10,     /** RF pull up voltage multiplied by 10   */
+    IN  Long            ifpullUpVolt_X10,     /** IF pull up voltage multiplied by 10   */
+    OUT Long*           strengthDbm           /** DBm                                   */
+);
+
+
+/**
+ * Get post VitBer
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param postErrorCount error count after viterbi
+ * @param postBitCount total count after viterbi
+ * @param abortCount error count after reed-soloman
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getPostVitBer (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Dword*          postErrorCount,  /** 24 bits */
+    OUT Dword*          postBitCount,    /** 16 bits */
+    OUT Word*           abortCount
+);
+
+
+/**
+ * Set the counting range for Pre-Viterbi and Post-Viterbi.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param frameCount the number of super frame for Pre-Viterbi.
+ * @param packetUnit the number of packet unit for Post-Viterbi.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Ganymede ganymede;
+ *
+ *     // Set statistic range.
+ *     error = Demodulator_setStatisticRange ((Demodulator*) &ganymede, 0, 1, 10000);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_setStatisticRange (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            superFrameCount,
+    IN  Word            packetUnit
+);
+
+
+/**
+ * Get the counting range for Pre-Viterbi and Post-Viterbi.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param frameCount the number of super frame for Pre-Viterbi.
+ * @param packetUnit the number of packet unit for Post-Viterbi.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Byte superFrameCount;
+ *     Word packetUnit;
+ *     Ganymede ganymede;
+ *
+ *     // Set statistic range.
+ *     error = Demodulator_getStatisticRange ((Demodulator*) &ganymede, 0, &superFrameCount, &packetUnit);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_getStatisticRange (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte*           superFrameCount,
+    IN  Word*           packetUnit
+);
+
+
+/**
+ * Get the statistic values of demodulator, it includes Pre-Viterbi BER,
+ * Post-Viterbi BER, Abort Count, Signal Presented Flag, Signal Locked Flag,
+ * Signal Quality, Signal Strength, Delta-T for DVB-H time slicing.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param statistic the structure that store all statistic values.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Statistic statistic;
+ *     double preBer;
+ *     double postBer;
+ *     Ganymede ganymede;
+ *
+ *     // Set statistic range.
+ *     error = Demodulator_getStatistic ((Demodulator*) &ganymede, 0, &statistic);
+ *     if (error)
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ *     preBer = (double) statistic.preVitErrorCount / (double) statistic.preVitBitCount;
+ *     printf ("Pre-Viterbi BER = %f\n", preBer);
+ *     postBer = (double) statistic.postVitErrorCount / (double) statistic.postVitBitCount;
+ *     printf ("Post-Viterbi BER = %f\n", postBer);
+ *     printf ("Abort Count = %d\n", statistic.abortCount);
+ *     if (statistic.signalPresented == True)
+ *         printf ("Signal Presented = True\n");
+ *     else
+ *         printf ("Signal Presented = False\n");
+ *     if (statistic.signalLocked == True)
+ *         printf ("Signal Locked = True\n");
+ *     else
+ *         printf ("Signal Locked = False\n");
+ *     printf ("Signal Quality = %d\n", statistic.signalQuality);
+ *     printf ("Signal Strength = %d\n", statistic.signalStrength);
+ * </pre>
+ */
+Dword Demodulator_getStatistic (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Statistic*      statistic
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @param code the value of IR raw code, the size should be 4 or 6,
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getIrCode (
+    IN  Demodulator*    demodulator,
+    OUT Dword*          code
+);
+
+
+/**
+ * Return to boot code
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_reboot (
+    IN  Demodulator*    demodulator
+);
+
+
+/**
+ * Control PID fileter
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param contorl 0: Disable, 1: Enable.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_controlPidFilter (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            control
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param contorl 1: Power up, 0: Power down;
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_controlPowerSaving (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            control
+);
+
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @param contorl 1: Power up, 0: Power down;
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_controlTunerPowerSaving (
+    IN  Demodulator*    demodulator,
+    IN  Byte            control
+);
+
+
+/**
+ * Set datagram burst size.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param burstSize the burst size.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @return Error_NOT_SUPPORT: if the burst size is not support.
+ */
+Dword Demodulator_setBurstSize (
+    IN  Demodulator*    demodulator,
+    IN  BurstSize       burstSize
+);
+
+
+/**
+ * Get datagram burst size.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param burstSize the burst size.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @return Error_NOT_SUPPORT: if the burst size is not support.
+ */
+Dword Demodulator_getBurstSize (
+    IN  Demodulator*    demodulator,
+    IN  BurstSize*      burstSize
+);
+#endif
diff --git a/drivers/media/dvb/dvb-usb/a867_demodulatorextend.c b/drivers/media/dvb/dvb-usb/a867_demodulatorextend.c
new file mode 100644
index 0000000..594a303
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_demodulatorextend.c
@@ -0,0 +1,607 @@
+#include "a867_demodulatorextend.h"
+/*
+#include "i2cimpl.h"
+#include "spiimpl.h"
+#include "i2uimpl.h"
+#include "i2u.h"
+#include "sdioimpl.h"
+*/
+
+#include "a867_usb2impl.h"
+#include "a867_cmd.h"
+
+#include "a867_Maxlinear_MXL5007.h"
+#include "a867_Afa_AF9007.h"
+
+static PidInfo pidInfo;
+BusDescription busDesc[] =
+{
+    /** 0: NULL bus */
+    {
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+    },
+    /** 1: I2C bus */
+    {
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+    },
+    /** 2: USB bus */
+    {
+        Usb2_getDriver,
+        Usb2_writeControlBus,
+        Usb2_readControlBus,
+        Usb2_readDataBus,
+    },
+    /** 3: SPI bus */
+    {
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+    },
+    /** 4: SDIO bus */
+    {
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+    },
+    /** 5: USB11 bus */
+    {
+        Usb2_getDriver,
+        Usb2_writeControlBus,
+        Usb2_readControlBus,
+        Usb2_readDataBus,
+    },
+    /** 6: I2C for old mail box */
+    {
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+    },
+    /** 7: USB for old mail box */
+    {
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+    },
+};
+
+CmdDescription cmdDesc[] =
+{
+    /** NULL Bus */
+    {
+        0,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL
+    },
+    /** 1:I2C Bus */
+    {
+        255,
+        &busDesc[1],
+        Cmd_writeRegisters,
+        Cmd_writeScatterRegisters,
+        Cmd_writeTunerRegisters,
+        Cmd_writeEepromValues,
+        Cmd_readRegisters,
+        Cmd_readScatterRegisters,
+        Cmd_readTunerRegisters,
+        Cmd_readEepromValues,
+        Cmd_modifyRegister,
+        Cmd_loadFirmware,
+        Cmd_reboot,
+        Cmd_sendCommand,
+        Cmd_receiveData
+    },
+    /** 2:USB Bus */
+    {
+        63,
+        &busDesc[2],
+        Cmd_writeRegisters,
+        Cmd_writeScatterRegisters,
+        Cmd_writeTunerRegisters,
+        Cmd_writeEepromValues,
+        Cmd_readRegisters,
+        Cmd_readScatterRegisters,
+        Cmd_readTunerRegisters,
+        Cmd_readEepromValues,
+        Cmd_modifyRegister,
+        Cmd_loadFirmware,
+        Cmd_reboot,
+        Cmd_sendCommand,
+        Cmd_receiveData
+    },
+    /** 3:SPI Bus */
+    {
+        255,
+        &busDesc[3],
+        Cmd_writeRegisters,
+        Cmd_writeScatterRegisters,
+        Cmd_writeTunerRegisters,
+        Cmd_writeEepromValues,
+        Cmd_readRegisters,
+        Cmd_readScatterRegisters,
+        Cmd_readTunerRegisters,
+        Cmd_readEepromValues,
+        Cmd_modifyRegister,
+        Cmd_loadFirmware,
+        Cmd_reboot,
+        Cmd_sendCommand,
+        Cmd_receiveData
+    },
+    /** 4:SDIO Bus */
+    {
+        255,
+        &busDesc[4],
+        Cmd_writeRegisters,
+        Cmd_writeScatterRegisters,
+        Cmd_writeTunerRegisters,
+        Cmd_writeEepromValues,
+        Cmd_readRegisters,
+        Cmd_readScatterRegisters,
+        Cmd_readTunerRegisters,
+        Cmd_readEepromValues,
+        Cmd_modifyRegister,
+        Cmd_loadFirmware,
+        Cmd_reboot,
+        Cmd_sendCommand,
+        Cmd_receiveData
+    },
+    /** 5:USB11 Bus */
+    {
+        63,
+        &busDesc[5],
+        Cmd_writeRegisters,
+        Cmd_writeScatterRegisters,
+        Cmd_writeTunerRegisters,
+        Cmd_writeEepromValues,
+        Cmd_readRegisters,
+        Cmd_readScatterRegisters,
+        Cmd_readTunerRegisters,
+        Cmd_readEepromValues,
+        Cmd_modifyRegister,
+        Cmd_loadFirmware,
+        Cmd_reboot,
+        Cmd_sendCommand,
+        Cmd_receiveData
+    },
+    /** 6:I2C for old mailbox */
+    {
+        16,
+        &busDesc[6],
+        NULL,
+	    NULL,
+	    NULL,
+	    NULL,
+	    NULL,
+	    NULL,
+	    NULL,
+	    NULL,
+	    NULL,
+	    NULL,
+	    NULL,
+	    NULL,
+	    NULL
+    },
+    /** 7:USB for old mailbox */
+    {
+        16,
+        &busDesc[7],
+        NULL,
+	    NULL,
+	    NULL,
+	    NULL,
+	    NULL,
+	    NULL,
+	    NULL,
+	    NULL,
+	    NULL,
+	    NULL,
+	    NULL,
+	    NULL,
+	    NULL
+    },
+};
+
+Dword Demodulator_setBusTuner (
+    IN  Demodulator*    demodulator,
+    IN  Word            busId,
+    IN  Word            tunerId
+) {
+    Dword error = Error_NO_ERROR;
+
+    Ganymede* ganymede;
+    ganymede = (Ganymede*) demodulator;
+    ganymede->cmdDescription = &cmdDesc[busId];
+    ganymede->busId = busId;
+
+    switch(tunerId) {
+    case Tuner_Afatech_AF9007:
+	ganymede->tunerDescription = &tuner_AF9007;
+	break;
+
+    case Tuner_Maxlinear_MXL5007:
+	ganymede->tunerDescription = &tuner_MXL5007;
+	break;
+
+    default:
+	error = Error_INVALID_TUNER_TYPE;
+	goto exit;
+	break;
+    }
+
+    if (ganymede->tunerDescription->tunerScript == NULL) {
+        ganymede->tunerDescription->tunerScript = NULL;
+        ganymede->tunerDescription->tunerScriptSets = NULL;
+    }
+
+exit:
+    return(error);
+}
+
+Dword Demodulator_getChannelStatistic (
+    IN  Demodulator*            demodulator,
+    IN  Byte                    chip,
+    OUT ChannelStatistic*       channelStatistic
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    GetChannelStatisticRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        request.chip = chip;
+        request.channelStatistic = channelStatistic;
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_GETCHANNELSTATISTIC,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    Dword postErrCnt;
+    Dword postBitCnt;
+    Word rsdAbortCnt;
+    Ganymede* ganymede;
+
+
+    ganymede = (Ganymede*) demodulator;
+
+
+    /** Get BER if couter is ready, error = Error_RSD_COUNTER_NOT_READY if counter is not ready */
+    if (ganymede->architecture == Architecture_PIP) {
+        error = Standard_getPostVitBer (demodulator, chip, &postErrCnt, &postBitCnt, &rsdAbortCnt);
+        if (error == Error_NO_ERROR) {
+            ganymede->channelStatistic[chip].postVitErrorCount = postErrCnt;
+            ganymede->channelStatistic[chip].postVitBitCount = postBitCnt;
+            ganymede->channelStatistic[chip].abortCount = rsdAbortCnt;
+        }
+    } else {
+        error = Standard_getPostVitBer (demodulator, 0, &postErrCnt, &postBitCnt, &rsdAbortCnt);
+        if (error == Error_NO_ERROR) {
+            ganymede->channelStatistic[chip].postVitErrorCount = postErrCnt;
+            ganymede->channelStatistic[chip].postVitBitCount = postBitCnt;
+            ganymede->channelStatistic[chip].abortCount = rsdAbortCnt;
+        }
+    }
+
+    *channelStatistic = ganymede->channelStatistic[chip];
+
+#endif
+
+    return (error);
+}
+Dword Demodulator_addPid (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Pid             pid
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    AddPidRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        request.chip = chip;
+        request.pid = pid;
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_ADDPID,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    Byte writeBuffer[2];
+    Byte i, j;
+    Bool found;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (pidInfo.pidinit == False) {
+        for (i = 0; i < ganymede->chipNumber; i++) {
+            for (j = 0; j < 32; j++) {
+                pidInfo.pidtable[i].pid[j] = 0xFFFF;
+            }
+        }
+        pidInfo.pidinit = True;
+    }
+
+    /** Enable pid filter */
+    if (pidInfo.pidcount == 0) {
+        error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, p_mp2if_pid_en, mp2if_pid_en_pos, mp2if_pid_en_len, 1);
+        if (error) goto exit;
+    } else {
+        found = False;
+        for (i = 0; i < 32; i++) {
+            if (pidInfo.pidtable[chip].pid[i] == pid.value) {
+                found = True;
+                break;
+            }
+        }
+        if (found == True)
+            goto exit;
+    }
+
+    for (i = 0; i < 32; i++) {
+        if (pidInfo.pidtable[chip].pid[i] == 0xFFFF)
+            break;
+    }
+    if (i == 32) {
+        error = Error_PID_FILTER_FULL;
+        goto exit;
+    }
+
+    writeBuffer[0] = (Byte) pid.value;
+    writeBuffer[1] = (Byte) (pid.value >> 8);
+
+    error = Standard_writeRegisters (demodulator, chip, Processor_OFDM, p_mp2if_pid_dat_l, 2, writeBuffer);
+    if (error) goto exit;
+
+    error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, p_mp2if_pid_index_en, mp2if_pid_index_en_pos, mp2if_pid_index_en_len, 1);
+    if (error) goto exit;
+
+    error = Standard_writeRegister (demodulator, chip, Processor_OFDM, p_mp2if_pid_index, i);
+    if (error) goto exit;
+
+    pidInfo.pidtable[chip].pid[i] = pid.value;
+    pidInfo.pidcount++;
+
+exit :
+#endif
+
+    return (error);
+}
+
+
+Dword Demodulator_addPidAt (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            index,
+    IN  Pid             pid
+) {
+	return (Demodulator_addPidToFilter (demodulator, chip, index, pid));
+}
+
+
+Dword Demodulator_removePid (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Pid             pid
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    RemovePidRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        request.chip = chip;
+        request.pid = pid;
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_REMOVEPID,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    Byte i;
+    Bool found;
+    Interrupts interrupts;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    found = False;
+    for (i = 0; i < 32; i++) {
+        if (pidInfo.pidtable[chip].pid[i] == pid.value) {
+            found = True;
+            break;
+        }
+    }
+    if (found == False)
+        goto exit;
+
+    error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, p_mp2if_pid_index_en, mp2if_pid_index_en_pos, mp2if_pid_index_en_len, 0);
+    if (error) goto exit;
+
+    error = Standard_writeRegister (demodulator, chip, Processor_OFDM, p_mp2if_pid_index, i);
+    if (error) goto exit;
+
+    pidInfo.pidtable[chip].pid[i] = 0xFFFF;
+
+    /** Disable pid filter */
+    if (pidInfo.pidcount == 1) {
+        error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, p_mp2if_pid_en, mp2if_pid_en_pos, mp2if_pid_en_len, 0);
+
+        error = Standard_getInterrupts (demodulator, &interrupts);
+        if (error) goto exit;
+        if (interrupts & Interrupt_DVBT) {
+            error = Standard_clearInterrupt (demodulator, Interrupt_DVBT);
+            if (error) goto exit;
+        }
+    }
+
+    pidInfo.pidcount--;
+
+exit :
+#endif
+
+    return (error);
+}
+
+
+Dword Demodulator_removePidAt (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+	IN  Byte			index,
+    IN  Pid             pid
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+	DWORD number;
+	BOOL result;
+	RemovePidAtRequest request;
+	Ganymede* ganymede;
+
+	ganymede = (Ganymede*) demodulator;
+	
+	if (ganymede->driver != NULL) {
+		request.chip = chip;
+		request.index = index;
+		request.pid = pid;
+		result = DeviceIoControl (
+					ganymede->driver,
+					IOCTL_AFA_DEMOD_REMOVEPIDAT,
+					&request,
+					sizeof (request),
+					NULL,
+					0,
+					&number,
+					NULL
+		);
+		error = request.error;
+	} else {
+		error = Error_DRIVER_INVALID;
+	}
+#else
+	Ganymede* ganymede;
+
+	ganymede = (Ganymede*) demodulator;
+
+	error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, p_mp2if_pid_index_en, mp2if_pid_index_en_pos, mp2if_pid_index_en_len, 0);
+	if (error) goto exit;
+
+	error = Standard_writeRegister (demodulator, chip, Processor_OFDM, p_mp2if_pid_index, index);
+	if (error) goto exit;
+exit :
+#endif
+
+	return (error);
+}
+
+
+Dword Demodulator_resetPid (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+#else
+    Byte i;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    for (i = 0; i < 32; i++) {
+        pidInfo.pidtable[chip].pid[i] = 0xFFFF;
+    }
+    error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, p_mp2if_pid_rst, mp2if_pid_rst_pos, mp2if_pid_rst_len, 1);
+    if (error) goto exit;
+
+    pidInfo.pidcount = 0;
+
+exit :
+#endif
+
+    return (error);
+}
+
+
+#ifdef UNDER_CE
+#else
+extern long ActiveSync;
+#endif
+
+Dword Demodulator_controlActiveSync (
+    IN Demodulator* demodulator,
+    IN Byte         control
+) {
+#ifdef UNDER_CE
+    if (control == 0)
+        ActiveSync = 0;
+    else
+        ActiveSync = 1;
+#endif
+
+    return (Error_NO_ERROR);
+}
diff --git a/drivers/media/dvb/dvb-usb/a867_demodulatorextend.h b/drivers/media/dvb/dvb-usb/a867_demodulatorextend.h
new file mode 100644
index 0000000..20d508f
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_demodulatorextend.h
@@ -0,0 +1,1326 @@
+#ifndef __DEMODULATOREXTEND_H__
+#define __DEMODULATOREXTEND_H__
+
+
+//#include <stdio.h>
+//#include <math.h>
+#include "a867_type.h"
+#include "a867_user.h"
+#include "a867_register.h"
+#include "a867_error.h"
+#include "a867_cmd.h"
+/*
+#include "i2cimpl.h"
+#include "spiimpl.h"
+#include "sdioimpl.h"
+*/
+#include "a867_usb2impl.h"
+#include "a867_demodulator.h"
+
+
+#define Tuner_Panasonic_ENV77H11D5			0x01
+#define Tuner_Microtune_MT2060				0x02
+#define Tuner_Maxlinear_MXL5003				0x03
+#define Tuner_Philip_TD1316AFIHP			0x04
+#define Tuner_Freescale_FS803A				0x05
+#define Tuner_Quantek_QT1010				0x06
+#define Tuner_Panasonic_ENV75H10D8			0x07
+#define Tuner_Lg_TDTMG252D					0x08
+#define Tuner_Himax_HTXR03A					0x09
+#define Tuner_Alps_TDQ44M					0x0A
+#define Tuner_Infineon_TUA6045				0x0B
+#define Tuner_Infineon_TUA6034				0x0C
+#define Tuner_Maxlinear_MXL5005				0x0D
+#define Tuner_Thomson_664X					0x0E
+#define Tuner_Thomson_6630					0x0F
+#define Tuner_Samsung_DTOS403				0x10
+#define Tuner_Samsung_DTOS446				0x11
+#define Tuner_Freescale_FS803A_DLNA			0x12
+#define Tuner_Microtune_MT2060_7SAW			0x13
+#define Tuner_Alps_TDQ03					0x14
+#define Tuner_Thomson_759X					0x15
+#define Tuner_Empire_DTN317					0x16
+#define Tuner_Partsnic_PDHTF05D				0x17
+#define Tuner_Panasonic_ENG37A30GF			0x18
+#define Tuner_Philips_FQD1216ME_MK5			0x19
+#define Tuner_Infineon_TUA6041				0x1A
+#define Tuner_Philips_TDA18271				0x1B
+#define Tuner_Alps_TDQD1X001A				0x1C
+#define Tuner_Maxlinear_MXL5005_RSSI		0x1D
+#define Tuner_Thomson_75101					0x1E
+#define Tuner_Sharp_5056					0x1F
+#define Tuner_Freescale_MC44CD02			0x20
+#define Tuner_Microtune_MT2260B0			0x21
+#define Tuner_Philips_TDA18291HN			0x22
+#define Tuner_Microtune_MT2266				0x23
+#define	Tuner_Integrant_ITD3020				0x24
+#define Tuner_Afatech_PEACOCK				0x25
+#define Tuner_Xceive_XC3028L				0x26
+#define Tuner_Infineon_TUA9001				0x27
+#define Tuner_Fitipower_FC0011				0x28
+#define Tuner_Afatech_AF9007				0xFF
+#define Tuner_Maxlinear_MXL5007				0xA0
+
+/**
+ * Define commands for AGC general set function
+ */
+#define APO_AGC_SET_RF_ACQUIRE				1
+#define APO_AGC_SET_RF_TRACK				2
+#define APO_AGC_SET_IF_ACQUIRE				3
+#define APO_AGC_SET_IF_TRACK				4
+#define APO_AGC_SET_ADC_OUT_DESIRED_S		5
+#define APO_AGC_SET_RF_TOP_S				6
+#define APO_AGC_SET_IF_TOP_S				7
+#define APO_AGC_SET_RF_LOCK_TH_ACQUIRE		8
+#define APO_AGC_SET_RF_LOCK_TH_TRACK		9
+#define APO_AGC_SET_IF_LOCK_TH_ACQUIRE		10
+#define APO_AGC_SET_IF_LOCK_TH_TRACK		11
+#define APO_AGC_SET_ADC_OUT_DESIRED_M		12
+#define APO_AGC_SET_RF_TOP_M				13
+#define APO_AGC_SET_IF_TOP_M				14
+#define APO_AGC_SET_RF_TOP					15
+#define APO_AGC_SET_IF_TOP					16
+
+
+/**
+ * Define commands for AGC general set function
+ */
+#define APO_AGC_GET_RF_ACQUIRE				1
+#define APO_AGC_GET_RF_TRACK				2
+#define APO_AGC_GET_IF_ACQUIRE				3
+#define APO_AGC_GET_IF_TRACK				4
+#define APO_AGC_GET_RF_LOCK_TH_ACQUIRE		5
+#define APO_AGC_GET_RF_LOCK_TH_TRACK		6
+#define APO_AGC_GET_IF_LOCK_TH_ACQUIRE		7
+#define APO_AGC_GET_IF_LOCK_TH_TRACK		8
+#define APO_AGC_GET_RF_MAX					9
+#define APO_AGC_GET_RF_MIN					10
+#define APO_AGC_GET_RF_TOP_S				11
+#define APO_AGC_GET_RF_TOP_M				17
+#define APO_AGC_GET_IF_MAX					12
+#define APO_AGC_GET_IF_MIN					13
+#define APO_AGC_GET_IF_TOP_S				14
+#define APO_AGC_GET_IF_TOP_M				18
+#define APO_AGC_GET_RF_TOP					19
+#define APO_AGC_GET_IF_TOP					20
+#define APO_AGC_GET_ADC_OUT_DESIRED_S		15
+#define APO_AGC_GET_ADC_OUT_DESIRED_M		16
+
+
+/**
+ * Define Options
+ */
+#define APO_OPTION_FREQSHIFT				0x00000001
+#define APO_OPTION_DYNATOP					0x00000002
+#define APO_OPTION_RET_NOW					0x00000004
+#define APO_OPTION_REPEAT_RETRAIN			0x00000008
+
+
+/**
+ * Define Demodulator_getDouble index
+ */
+#define APO_GET_FREQ_SHIFT					1
+#define APO_GET_ORIG_RF_TOP					2
+#define APO_GET_ORIG_IF_TOP					3
+#define APO_GET_FINAL_RF_TOP				4
+#define APO_GET_FINAL_IF_TOP				5
+#define APO_GET_BEST_RF_TOP					6
+#define APO_GET_BEST_IF_TOP					7
+
+
+/**
+ * Define commands for general CE information function
+ */
+#define APO_AGC_CLEAR_REGS				1
+#define APO_AGC_STALL_OFSM_ACCESS		2
+#define APO_AGC_RESTORE_OFSM_ACCESS		3
+
+
+#define APO_DCA_EN_UPPER				0x01
+#define APO_DCA_EN_LOWER				0x02
+#define APO_DCA_BOTH					0x00
+
+
+/** keep for internal api release */
+/**
+ * The type defination of PidTable.
+ */
+typedef struct {
+	Word pid[32];
+} PidTable;
+
+typedef struct {
+	PidTable pidtable[2];
+	Byte pidcount;
+	Bool pidinit;
+} PidInfo;
+/** end keep for internal api release */
+
+
+extern Word DemodulatorExtend_diversityMode;
+extern double DemodulatorExtend_crystalFrequency;
+extern Word Tdmb_bitRateTable[64];
+
+
+/**
+ * Set control bus and tuner.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param busId The ID of bus.
+ * @param tunerId The ID of tuner.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Ganymede ganymede;
+ *
+ *     // Set I2C as the control bus. 
+ *     error = Demodulator_setBusTuner ((Demodulator*) &ganymede, Bus_I2C, Tuner_MICROTUNE_MT2060);
+ *     if (error) 
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_setBusTuner (
+	IN  Demodulator*	demodulator,
+	IN  Word			busId,
+	IN  Word			tunerId
+);
+
+
+/**
+ * Set firmware and script.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param crystalFrequency The value of crystal frequency on board (KHz).
+ * @param adcFrequency The value of desire internal ADC frequency (Hz).
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Ganymede ganymede;
+ *
+ *     // Set frequencies. 
+ *     error = Demodulator_setCrystalAdcFrequency ((Demodulator*) &ganymede, 30000, 20156250);
+ *     if (error) 
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_setCrystalAdcFrequency (
+	IN  Demodulator*	demodulator,
+	IN  Dword			crystalFrequency,
+	IN  Dword			adcFrequency
+);
+
+
+/**
+ * Set firmware and script.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param firmwareCodes The byte array of firmware code.
+ * @param firmwareSegments The segments of firmwares.
+ * @param firmwarePartitions The partitions of firmwares.
+ * @param scriptSets The sets of script.
+ * @param scripts The byte array of script.
+ * @param tunerScriptSets The sets of tunerScript.
+ * @param tunerScripts The byte array of tunerScript.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     Byte firmware[65535];
+ *     ValueSet script[256];
+ *     ValueSet tunerScript[256];
+ *     Ganymede ganymede;
+ *
+ *     // Set I2C as the control bus. 
+ *     error = Demodulator_setFirmwareScript ((Demodulator*) &ganymede, firmware, 65535, script, 256, tunerScript, 256);
+ *     if (error) 
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ * </pre>
+ */
+Dword Demodulator_setFirmwareScript (
+	IN  Demodulator*	demodulator,
+	IN  Byte*			firmwareCodes,
+	IN  Segment*		firmwareSegments,
+	IN  Byte*			firmwarePartitions,
+	IN  Word*			scriptSets,
+	IN  ValueSet*		scripts,
+	IN  Word*           tunerScriptSets,
+	IN  ValueSet*       tunerScripts
+);
+
+
+/**
+ * Get the statistic values of demodulator, it includes Pre-Viterbi BER,
+ * Post-Viterbi BER, Abort Count, Signal Presented Flag, Signal Locked Flag,
+ * Signal Quality, Signal Strength, Delta-T for DVB-H time slicing.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @param statistic the structure that store all statistic values.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ *     Dword error = Error_NO_ERROR;
+ *     ChannelStatistic channelStatistic;
+ *     double preBer;
+ *     double postBer;
+ *     Ganymede ganymede;
+ *
+ *     // Set statistic range. 
+ *     error = Demodulator_getChannelStatistic ((Demodulator*) &ganymede, 0, &channelStatistic);
+ *     if (error) 
+ *         printf ("Error Code = %X", error);
+ *     else
+ *         printf ("Success");
+ *     preBer = (double) channelStatistic.preVitErrorCount / (double) channelStatistic.preVitBitCount;
+ *     printf ("Pre-Viterbi BER = %f\n", preBer);
+ *     postBer = (double) channelStatistic.postVitErrorCount / (double) channelStatistic.postVitBitCount;
+ *     printf ("Post-Viterbi BER = %f\n", postBer);
+ *     printf ("Abort Count = %d\n", channelStatistic.abortCount);
+ * </pre>
+ */
+Dword Demodulator_getChannelStatistic (
+	IN  Demodulator*			demodulator,
+	IN  Byte					chip,
+	OUT ChannelStatistic*		channelStatistic
+);
+
+
+/**
+ * Set the counting range for Pre-Viterbi and Post-Viterbi. 
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7. NOTE: When the architecture is set to Architecture_DCA
+ *        this parameter is regard as don't care.
+ * @param preErrorCount the number of super frame for Pre-Viterbi.
+ * @param preBitCount the number of packet unit for Post-Viterbi.
+ * @param snr the signal to noise ratio.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Demodulator_getPreVitBer (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+	OUT Dword*			preErrorCount,
+	OUT Dword*			preBitCount,
+	OUT double*			snr
+);
+
+
+/**
+ * Set the counting range for Pre-Viterbi and Post-Viterbi. 
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7. NOTE: When the architecture is set to Architecture_DCA
+ *        this parameter is regard as don't care.
+ * @param preErrorCount the number of super frame for Pre-Viterbi.
+ * @param preBitCount the number of packet unit for Post-Viterbi.
+ * @param snr the signal to noise ratio.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Demodulator_getSoftBer (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+	OUT Dword*			preErrorCount,
+	OUT Dword*			preBitCount,
+	OUT double*			snr
+);
+
+
+/**
+ * This function is used to get signal quality indicator.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @param sqi signal quality indicator.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ *     Byte sqi;
+ * 
+ *     Demodulator_getSqi (0x38, 0, &sqi);
+ * </pre>
+ */
+Dword Demodulator_getSqi (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+    OUT Byte*			sqi
+);
+
+
+/**
+ * Get IF agc voltage.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param doPullUpVolt The pull up voltage of tunre.
+ * @param dopVolt IF AGC voltage to be returned.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getIfAgcVoltage (
+	IN  Demodulator*	demodulator,
+    IN  double			doPullUpVolt,
+    OUT double*			dopVolt
+);
+
+
+/**
+ * Set maximum RF agc. 
+ *
+ * @param demodulator the handle of demodulator.
+ * @param doMaxRfAgc The maximum value of RF AGC.
+ * @param doVolt RF AGC voltage to be set.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_setMaxRfAgc (
+	IN  Demodulator*	demodulator,
+    IN	double			doMaxRfAgc,
+	IN  double			doVolt
+);
+
+
+/**
+ * Set minimum rf agc.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param doMinRfAgc The minimum value of RF AGC.
+ * @param doVolt RF AGC voltage to be set.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_setMinRfAgc (
+	IN  Demodulator*	demodulator,
+    IN	double			doMinRfAgc,
+	IN  double			doVolt
+);
+
+
+/**
+ * Set max if agc.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param doMaxIfAgc The maximum value of IF AGC.
+ * @param doVolt IF AGC voltage to be set.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_setMaxIfAgc (
+	IN  Demodulator*	demodulator,
+    IN	double			doMaxIfAgc,
+	IN  double			doVolt
+);
+
+
+/**
+ * Set min if agc. 
+ *
+ * @param demodulator the handle of demodulator.
+ * @param doMinIfAgc The minimum value of IF AGC.
+ * @param doVolt IF AGC voltage to be set.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_setMinIfAgc (
+	IN  Demodulator*	demodulator,
+    IN	double			doMinIfAgc,
+	IN  double			doVolt
+);
+
+
+/**
+ * General agc set function.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param ucCmd .
+ * @param vpParams .
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_setAgc (
+	IN  Demodulator*	demodulator,
+	IN  Byte			ucCmd,
+    IN	Word*			vpParams
+);
+
+
+/**
+ * General agc get function.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param ucCmd .
+ * @param vpParams .
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getAgc (
+	IN  Demodulator*	demodulator,
+	IN  Byte			ucCmd,
+    IN	void*			vpParams
+);
+
+
+/**
+ * Check if INR detected.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @param count INR count.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getInrCount (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+    OUT Word*			count
+);
+
+
+/**
+ * Check if CCI happens.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @param cci0 1: CCI happen, 0: CCI doesn't happen.
+ * @param cci1 1: CCI happen, 0: CCI doesn't happen.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_isCci (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+    OUT Bool*			cci0,
+    OUT Bool*			cci1
+);
+
+
+/**
+ * Check if ACI happens
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @param aci0 1: ACI happen, 0: ACI doesn't happen.
+ * @param aci1 1: ACI happen, 0: ACI doesn't happen.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_isAci (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+    OUT Bool*			aci0,
+    OUT Bool*			aci1
+);
+
+
+/**
+ * Get frequency offset.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @param doTs Sampling period.
+ * @param lpNormOffset Normalized frequency offset (carrier spacing).
+ * @param lpOffset Frequency offset (22 bits) (Hz).
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getFrequencyOffset (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+	IN  double			elementaryPeriod,
+	OUT Long*			normalizedOffset,
+	OUT Long*			offset
+);
+
+
+/**
+ * Get sampling clock offset in second
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @param adcFrequency ADC frequency.
+ * @param elementaryPeriod Sampling period.
+ * @param offset ADC sampling clock offset in sec.
+ * @param offsetPpm ADC sampling clock offset in PPM.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getTimeOffset (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+    IN  double			adcFrequency,
+    IN  double			elementaryPeriod,
+    OUT double*			offset,
+    OUT double*			offsetPpm
+);
+
+
+/**
+ * Set IF1 frequency of MT2060.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param dwIf1 The IF1 frequency (KHz).
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_setMT2060If1 (
+	IN  Demodulator*	demodulator,
+    IN  Dword			dwIf1
+);
+
+
+/**
+ * Clear FFT window position valid bit.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_resetFftWinPos (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip
+);
+
+
+/**
+ * Clear FFT window position valid bit.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @param delta Delta value for FFT window position.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getFftWinPos (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+    IN	Long*			delta	
+);
+
+
+/**
+ * Get crystal frequency (KHz).
+ *
+ * @param demodulator the handle of demodulator.
+ * @param fpFreq Crystal frequency.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getXtalFreq (
+	IN  Demodulator*	demodulator,
+    IN	float*			fpFreq
+);
+
+
+/**
+ * Test register.
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_testRegister (
+	IN  Demodulator*	demodulator
+);
+
+
+/**
+ * Dump register.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param cpFileName The name of file to be write.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_dumpRegister (
+	IN  Demodulator*	demodulator,
+    IN  char*			cpFileName
+);
+
+
+/**
+ * Get frequency response from hardware.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @param tone Sub-Carrier Index ( Real Index = 200*wIndex).
+ * @param realPart Real part of Constellation value.
+ * @param imaginaryPart Imaginary part of Constellation value.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getFrequencyResponse (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+	OUT Word*			tone,
+	OUT Long*			realPart,
+	OUT Long*			imaginaryPart
+);
+
+
+/**
+ * Get constellation value.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @param tone Sub-Carrier Index ( Real Index = 200*wIndex).
+ * @param realPart Real part of Constellation value.
+ * @param imaginaryPart Imaginary part of Constellation value.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getConstellation (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+	IN  Word			tone,
+	OUT float*			realPart,
+	OUT float*			imaginaryPart
+);
+
+
+/**
+ * Capture constellation value (2).
+ *
+ * @param demodulator the handle of demodulator.
+ * @param wIndex Sub-Carrier Index ( Real Index = 200*wIndex).
+ * @param wpReal real part of constellation value.
+ * @param wpImag imaginary part of constellation value.
+ * @param wpH2 H2 value.
+ * @param wpRealH real part of H.
+ * @param wpImagH imaginary part of H.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_capConstellation2 (
+	IN  Demodulator*	demodulator,
+    IN  Word			wIndex,
+    OUT Byte*			ucpSymCnt,
+    OUT Byte*			ucpReal,
+    OUT Byte*			ucpImag,
+    OUT Word*			wpRealH,
+    OUT Word*			wpImagH
+);
+
+
+/**
+ * Get status.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param dwpStatus Pointer to system information.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getStatus (
+	IN  Demodulator*	demodulator,
+    OUT Dword*			dwpStatus
+);
+
+
+/**
+ * Get frequency shift.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param index .
+ * @param dopShift .
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getDouble (
+	IN  Demodulator*	demodulator,
+    IN  Byte			index,
+    IN  double*			dopValue
+);
+
+
+/**
+ * Get IR byte.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param ucpIRByte IR packet buffer.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getIr (
+	IN  Demodulator*	demodulator,
+    OUT	Byte*			ucpIRByte
+);
+
+
+/**
+ * Dump EEPROM.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param dwDelay .
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_dumpEeprom (
+	IN  Demodulator*	demodulator,
+    IN  Dword			dwDelay
+);
+
+
+/**
+ * Load file to EEPROM.
+ *
+ * @param fileName File name to load to EEPROM.
+ * @param dwDelay .
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_loadEeprom (
+	IN  Demodulator*	demodulator,
+    IN  char*			fileName,
+    IN  Dword			dwDelay
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_isFecMonEnabled (
+	IN  Demodulator*	demodulator,
+	OUT Bool*			enabled
+);
+
+
+/**
+ * Generate ce information.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @param command .
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_genCeInfoFunc (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+	IN  Byte			command
+);
+
+
+/**
+ * Get ce information.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @param spCentroid .
+ * @param spBias .
+ * @param dwpRh0 .
+ * @param wpM2 .
+ * @param dwpEh2 .
+ * @param ucpM2q .
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getCeInfo (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+	OUT Short*			spCentroid,
+	OUT Short*			spBias,
+	OUT Dword*			dwpRh0,
+	OUT Word*			wpM2,
+	OUT Dword*			dwpEh2,
+	OUT Byte*			ucpM2q
+);
+
+
+/**
+ * Enable/disable retrain.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @param enable .
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_setRetrain (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+	IN  Byte			enable
+);
+
+
+/**
+ * Enable/disable CCIR.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param ucEnable .
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_setCcir (
+	IN  Demodulator*	demodulator,
+	IN  Byte			ucEnable
+);
+
+
+/**
+ * Handle CCIF
+ *
+ * @param demodulator the handle of demodulator.
+ * @param ccifId .
+ * @param ctrl .
+ * @param ucBw .
+ * @param wFreq .
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_handleCcif (
+	IN  Demodulator*	demodulator,
+	IN  Byte			ccifId,
+	IN  Byte			ctrl,
+	IN  Byte			ucBw,
+	IN  Word			wFreq
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @param level .
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getAdcDesiredLevel (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+	OUT Word*			level
+);
+
+	
+/**
+ * Set tuner type
+ *
+ * @param demodulator the handle of demodulator.
+ * @param ucTuner .
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_setTunerType (
+	IN  Demodulator*	demodulator,
+	IN  Byte			ucTuner
+);
+
+
+/**
+ * Set board id
+ *
+ * @param demodulator the handle of demodulator.
+ * @param ucBoard .
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_setBoardId (
+	IN  Demodulator*	demodulator,
+	IN  Byte			ucBoard
+);
+
+
+/**
+ * Get signal strength in Dbm
+ *
+ * @param demodulator the handle of demodulator.
+ * @param ucTunerType tuner type.
+ * @param ucBoardId Board ids.
+ * @param dopStrength signal strength.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getSignalStrengthDBm (
+	IN  Demodulator*	demodulator,
+	IN  Byte			ucTunerType,
+    IN  Byte			ucBoardId,
+    OUT double*			dopStrength		
+);
+
+
+/**
+ * Program CFOE 2.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param ucBw Current channel bandwidth in MHz.
+ * @param dFs ADC sampling frequency.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_programCFOE2 (
+	IN  Demodulator*	demodulator,
+    IN  Byte			ucBw,
+    IN  double			dFs
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_setCalibratAgc (
+	IN  Demodulator*	demodulator
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_setCrystalFrequency (
+	IN  Demodulator*	demodulator,
+	IN  double			crystalFrequency
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_writeMt2060If1 (
+	IN  Demodulator*	demodulator,
+	IN  Dword			dwIF1
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getSnr (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+	OUT double*			snr
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @param speed the I2C speed in KHz.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_setI2cSpeed (
+	IN  Demodulator*	demodulator,
+	IN  Dword			speed
+);
+
+
+/**
+ * Ask fw to go back to boot code
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_backToBootCode (
+	IN  Demodulator*	demodulator
+);
+
+
+/**
+ * Control gpio3 (AF9015 use this pin to turn on/off tuner)
+ * ucOn = 1 => turn on tuner
+ * ucOn = 0 => turn off tuner
+ *
+ * @param demodulator the handle of demodulator.
+ * @param contorl True: Enable, False: Disable;
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_controlTunerPower (
+	IN  Demodulator*	demodulator,
+	IN  Byte			control
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @param multiplier ADC frequency multiplier;
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_setMultiplier (
+	IN  Demodulator*	demodulator,
+	IN  Multiplier		multiplier
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @param multiplier ADC frequency multiplier;
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_getMultiplier (
+	IN  Demodulator*	demodulator,
+	IN  Multiplier*		multiplier
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @param ifFrequency the IF frequency of tuner;
+ * @param inversion True if tuner's pectrum is inversed;
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_modifyTunerDescription (
+	IN  Demodulator*	demodulator,
+	IN  Byte			tunerAddress,
+	IN  Byte			registerAddressLength,
+	IN  Dword			ifFrequency,
+	IN  Bool			inversion
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_writeRawData (
+	IN  Demodulator*	demodulator,
+	IN  Byte			writeBufferLength,
+	IN  Byte*			writeBuffer
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_readRawData (
+	IN  Demodulator*	demodulator,
+	IN  Byte			readBufferLength,
+	OUT Byte*			readBuffer
+);
+
+
+/**
+ * Open tuner.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ */
+Dword Demodulator_openTuner (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip
+);
+
+/**
+ * Set tuner.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @param bandwidth The desired bandwidth.
+ * @param frequency The desired frequency.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ */
+Dword Demodulator_setTuner (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+	IN	Word			bandwidth,
+	IN  Dword			frequency
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @param block How many block (logical frame) to be check.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_setPostVitAllZeroBlock (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+	IN  Word			block
+);
+
+
+/**
+ * Add PID to PID filter.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @param pid the PID that will be add to PID filter.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Demodulator_addPid (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+	IN  Pid				pid
+);
+
+
+/**
+ * Add PID to PID filter by index.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @param index the index of PID filter.
+ * @param pid the PID that will be add to PID filter.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Demodulator_addPidAt (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+    IN  Byte            index,
+	IN  Pid				pid
+);
+
+
+/**
+ * Remove PID from PID filter.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @param pid the PID that will be remove from PID filter.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Demodulator_removePid (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip,
+	IN  Pid				pid
+);
+
+/**
+ * Remove PID from PID filter by index.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @param index the index of PID filter.
+ * @param pid the PID that will be remove from PID filter.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Demodulator_removePidAt (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+	IN  Byte			index,
+    IN  Pid             pid
+);
+
+
+/**
+ * Reset PID filter.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are 
+ *        0~7.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Demodulator_resetPid (
+	IN  Demodulator*	demodulator,
+	IN  Byte			chip
+);
+
+
+/**
+ * Control Active Sync.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param contorl 0: Disable(BDA Extend), 1: Enable (Active Sync)
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Demodulator_controlActiveSync (
+	IN  Demodulator*	demodulator,
+	IN  Byte			control
+);
+#endif
diff --git a/drivers/media/dvb/dvb-usb/a867_error.h b/drivers/media/dvb/dvb-usb/a867_error.h
new file mode 100644
index 0000000..234c03a
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_error.h
@@ -0,0 +1,141 @@
+#ifndef __ERROR_H__
+#define __ERROR_H__
+
+#define Error_NO_ERROR							0x00000000ul
+#define Error_RESET_TIMEOUT						0x00000001ul
+#define Error_WRITE_REG_TIMEOUT					0x00000002ul
+#define Error_WRITE_TUNER_TIMEOUT				0x00000003ul
+#define Error_WRITE_TUNER_FAIL					0x00000004ul
+#define Error_RSD_COUNTER_NOT_READY				0x00000005ul
+#define Error_VTB_COUNTER_NOT_READY				0x00000006ul
+#define Error_FEC_MON_NOT_ENABLED				0x00000007ul
+#define Error_INVALID_DEV_TYPE					0x00000008ul
+#define Error_INVALID_TUNER_TYPE				0x00000009ul
+#define Error_OPEN_FILE_FAIL					0x0000000Aul
+#define Error_WRITEFILE_FAIL					0x0000000Bul
+#define Error_READFILE_FAIL						0x0000000Cul
+#define Error_CREATEFILE_FAIL					0x0000000Dul
+#define Error_MALLOC_FAIL						0x0000000Eul
+#define Error_INVALID_FILE_SIZE					0x0000000Ful
+#define Error_INVALID_READ_SIZE					0x00000010ul
+#define Error_LOAD_FW_DONE_BUT_FAIL				0x00000011ul
+#define Error_NOT_IMPLEMENTED					0x00000012ul
+#define Error_NOT_SUPPORT						0x00000013ul
+#define Error_WRITE_MBX_TUNER_TIMEOUT			0x00000014ul
+#define Error_DIV_MORE_THAN_8_CHIPS				0x00000015ul
+#define Error_DIV_NO_CHIPS						0x00000016ul
+#define Error_SUPER_FRAME_CNT_0					0x00000017ul
+#define Error_INVALID_FFT_MODE					0x00000018ul
+#define Error_INVALID_CONSTELLATION_MODE		0x00000019ul
+#define Error_RSD_PKT_CNT_0						0x0000001Aul
+#define Error_FFT_SHIFT_TIMEOUT					0x0000001Bul
+#define Error_WAIT_TPS_TIMEOUT					0x0000001Cul
+#define Error_INVALID_BW						0x0000001Dul
+#define Error_INVALID_BUF_LEN					0x0000001Eul
+#define Error_NULL_PTR							0x0000001Ful
+#define Error_INVALID_AGC_VOLT					0x00000020ul
+#define Error_MT_OPEN_FAIL						0x00000021ul
+#define Error_MT_TUNE_FAIL						0x00000022ul
+#define Error_CMD_NOT_SUPPORTED					0x00000023ul
+#define Error_CE_NOT_READY						0x00000024ul
+#define Error_EMBX_INT_NOT_CLEARED				0x00000025ul
+#define Error_INV_PULLUP_VOLT					0x00000026ul
+#define Error_FREQ_OUT_OF_RANGE					0x00000027ul
+#define Error_INDEX_OUT_OF_RANGE				0x00000028ul
+#define Error_NULL_SETTUNER_PTR					0x00000029ul
+#define Error_NULL_INITSCRIPT_PTR				0x0000002Aul
+#define Error_INVALID_INITSCRIPT_LEN			0x0000002Bul
+#define Error_INVALID_POS						0x0000002Cul
+#define Error_BACK_TO_BOOTCODE_FAIL				0x0000002Dul
+#define Error_GET_BUFFER_VALUE_FAIL				0x0000002Eul
+#define Error_INVALID_REG_VALUE					0x0000002Ful
+#define Error_INVALID_INDEX						0x00000030ul
+#define Error_READ_TUNER_TIMEOUT				0x00000031ul
+#define Error_READ_TUNER_FAIL					0x00000032ul
+#define Error_UNDEFINED_SAW_BW					0x00000033ul
+#define Error_MT_NOT_AVAILABLE					0x00000034ul
+#define Error_NO_SUCH_TABLE						0x00000035ul
+#define Error_WRONG_CHECKSUM					0x00000036ul
+#define Error_INVALID_XTAL_FREQ					0x00000037ul
+#define Error_COUNTER_NOT_AVAILABLE				0x00000038ul
+#define Error_INVALID_DATA_LENGTH				0x00000039ul
+#define Error_BOOT_FAIL							0x0000003Aul
+#define Error_BUFFER_INSUFFICIENT				0x0000003Bul
+#define Error_NOT_READY							0x0000003Cul
+#define Error_DRIVER_INVALID					0x0000003Dul
+#define Error_INTERFACE_FAIL					0x0000003Eul
+#define Error_PID_FILTER_FULL					0x0000003Ful
+#define Error_OPERATION_TIMEOUT					0x00000040ul
+#define Error_LOADFIRMWARE_SKIPPED				0x00000041ul
+#define Error_REBOOT_FAIL						0x00000042ul
+#define Error_PROTOCOL_FORMAT_INVALID			0x00000043ul
+#define Error_ACTIVESYNC_ERROR					0x00000044ul
+#define Error_CE_READWRITEBUS_ERROR				0x00000045ul
+#define Error_CE_NODATA_ERROR					0x00000046ul
+#define Error_NULL_FW_SCRIPT					0x00000047ul
+#define Error_NULL_TUNER_SCRIPT					0x00000048ul
+
+/** Error Code of Gemini System */
+#define Error_INVALID_INDICATOR_TYPE			0x00000101ul
+#define Error_INVALID_SC_NUMBER					0x00000102ul
+#define Error_INVALID_SC_INFO					0x00000103ul
+#define Error_FIGBYPASS_FAIL					0x00000104ul
+
+/** Error Code of Firmware */
+#define Error_FIRMWARE_STATUS					0x01000000ul
+
+/** Error Code of I2C Module */
+#define Error_I2C_DATA_HIGH_FAIL				0x02001000ul
+#define Error_I2C_CLK_HIGH_FAIL					0x02002000ul
+#define Error_I2C_WRITE_NO_ACK					0x02003000ul
+#define Error_I2C_DATA_LOW_FAIL					0x02004000ul
+
+/** Error Code of USB Module */
+#define Error_USB_NULL_HANDLE					0x03010001ul
+#define Error_USB_WRITEFILE_FAIL				0x03000002ul
+#define Error_USB_READFILE_FAIL					0x03000003ul
+#define Error_USB_INVALID_READ_SIZE				0x03000004ul
+#define Error_USB_INVALID_STATUS				0x03000005ul
+#define Error_USB_INVALID_SN					0x03000006ul
+#define Error_USB_INVALID_PKT_SIZE				0x03000007ul
+#define Error_USB_INVALID_HEADER				0x03000008ul
+#define Error_USB_NO_IR_PKT						0x03000009ul
+#define Error_USB_INVALID_IR_PKT				0x0300000Aul
+#define Error_USB_INVALID_DATA_LEN				0x0300000Bul
+#define Error_USB_EP4_READFILE_FAIL				0x0300000Cul
+#define Error_USB_EP$_INVALID_READ_SIZE			0x0300000Dul
+#define Error_USB_BOOT_INVALID_PKT_TYPE			0x0300000Eul
+#define Error_USB_BOOT_BAD_CONFIG_HEADER		0x0300000Ful
+#define Error_USB_BOOT_BAD_CONFIG_SIZE			0x03000010ul
+#define Error_USB_BOOT_BAD_CONFIG_SN			0x03000011ul
+#define Error_USB_BOOT_BAD_CONFIG_SUBTYPE		0x03000012ul
+#define Error_USB_BOOT_BAD_CONFIG_VALUE			0x03000013ul
+#define Error_USB_BOOT_BAD_CONFIG_CHKSUM		0x03000014ul
+#define Error_USB_BOOT_BAD_CONFIRM_HEADER		0x03000015ul
+#define Error_USB_BOOT_BAD_CONFIRM_SIZE			0x03000016ul
+#define Error_USB_BOOT_BAD_CONFIRM_SN			0x03000017ul
+#define Error_USB_BOOT_BAD_CONFIRM_SUBTYPE		0x03000018ul
+#define Error_USB_BOOT_BAD_CONFIRM_VALUE		0x03000019ul
+#define Error_USB_BOOT_BAD_CONFIRM_CHKSUM		0x03000020ul
+#define Error_USB_BOOT_BAD_BOOT_HEADER			0x03000021ul
+#define Error_USB_BOOT_BAD_BOOT_SIZE			0x03000022ul
+#define Error_USB_BOOT_BAD_BOOT_SN				0x03000023ul
+#define Error_USB_BOOT_BAD_BOOT_PATTERN_01		0x03000024ul
+#define Error_USB_BOOT_BAD_BOOT_PATTERN_10		0x03000025ul
+#define Error_USB_BOOT_BAD_BOOT_CHKSUM			0x03000026ul
+#define Error_USB_INVALID_BOOT_PKT_TYPE			0x03000027ul
+#define Error_USB_BOOT_BAD_CONFIG_VAlUE			0x03000028ul
+#define Error_USB_COINITIALIZEEX_FAIL			0x03000029ul
+#define Error_USB_COCREATEINSTANCE_FAIL			0x0300003Aul
+#define Error_USB_COCREATCLSEENUMERATOR_FAIL    0x0300002Bul
+#define Error_USB_QUERY_INTERFACE_FAIL			0x0300002Cul
+#define Error_USB_PKSCTRL_NULL					0x0300002Dul
+#define Error_USB_INVALID_REGMODE				0x0300002Eul
+#define Error_USB_INVALID_REG_COUNT				0x0300002Ful
+#define Error_USB_INVALID_HANDLE				0x03000100ul
+#define Error_USB_WRITE_FAIL					0x03000200ul
+#define Error_USB_UNEXPECTED_WRITE_LEN			0x03000300ul
+#define Error_USB_READ_FAIL						0x03000400ul
+
+#endif
+
diff --git a/drivers/media/dvb/dvb-usb/a867_firmware.h b/drivers/media/dvb/dvb-usb/a867_firmware.h
new file mode 100644
index 0000000..1562dfa
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_firmware.h
@@ -0,0 +1,10867 @@
+// This file is automatically generated. Do not edit.
+
+#ifndef __FIRMWARE_H__
+
+#define __FIRMWARE_H__
+
+
+/* moved to a867_ofdm.h
+
+#define DVB_LL_VERSION1 10
+
+#define DVB_LL_VERSION2 10
+
+#define DVB_LL_VERSION3 3
+
+#define DVB_LL_VERSION4 0
+
+
+
+#define DVB_OFDM_VERSION1 4
+
+#define DVB_OFDM_VERSION2 21
+
+#define DVB_OFDM_VERSION3 6
+
+#define DVB_OFDM_VERSION4 251
+*/
+
+
+#include "a867_type.h"
+
+
+
+
+
+#define Firmware_CODELENGTH				0x0000A4D6
+
+#define Firmware_SEGMENTLENGTH			0x00000004
+
+#define Firmware_PARTITIONLENGTH		0x00000001
+
+
+
+
+
+static Byte Firmware_codes[] = {
+
+	0x01,0x41,0x00,0x00,0x03,0xFB,0xBE,0x02,
+
+	0x54,0x30,
+
+	0x01,0x47,0x00,0x3A,0x07,0xF7,0x7E,0x32,
+
+	0x32,0xA9,0x07,0x89,0x0E,0xE5,0x0E,0x24,
+
+	0x04,0x90,0xF7,0x00,0xF0,0x90,0xF7,0x03,
+
+	0xE0,0x90,0xF7,0x01,0xF0,0xA3,0xE4,0xF0,
+
+	0xE5,0x0E,0x24,0x05,0x90,0xF4,0x12,0xF0,
+
+	0xA3,0xE4,0xF0,0xA3,0xE0,0x54,0xFC,0xF0,
+
+	0x75,0x0C,0xF7,0x75,0x0D,0x03,0x90,0xF7,
+
+	0x01,0xE0,0xF5,0x08,0xA3,0xE0,0xF5,0x09,
+
+	0xE5,0x0E,0x60,0x57,0xB4,0x01,0x1A,0x8D,
+
+	0x82,0x8C,0x83,0xE0,0x85,0x0D,0x82,0x85,
+
+	0x0C,0x83,0xF0,0xE0,0xFE,0xE4,0x25,0x09,
+
+	0xF5,0x09,0xEE,0x35,0x08,0xF5,0x08,0x80,
+
+	0x3A,0x8D,0x82,0x8C,0x83,0xE0,0xF5,0x0A,
+
+	0xA3,0xE0,0xF5,0x0B,0x85,0x0D,0x82,0x85,
+
+	0x0C,0x83,0xE5,0x0A,0xF0,0xA3,0xE5,0x0B,
+
+	0xF0,0x25,0x09,0xF5,0x09,0xE5,0x0A,0x35,
+
+	0x08,0xF5,0x08,0x74,0x02,0x2D,0xFD,0xE4,
+
+	0x3C,0xFC,0x74,0x02,0x25,0x0D,0xF5,0x0D,
+
+	0xE4,0x35,0x0C,0xF5,0x0C,0x15,0x0E,0x15,
+
+	0x0E,0x80,0xA5,0xE5,0x09,0xF4,0xFF,0xE5,
+
+	0x08,0xF4,0xFE,0x74,0x03,0x29,0xF5,0x82,
+
+	0xE4,0x34,0xF7,0xF5,0x83,0xEE,0xF0,0xA3,
+
+	0xEF,0xF0,0x22,0x90,0x41,0x82,0xEE,0xF0,
+
+	0xA3,0xEF,0xF0,0xE4,0xA3,0xF0,0xA3,0xF0,
+
+	0xFC,0xEC,0xC3,0x9D,0x50,0x43,0xEC,0x30,
+
+	0xE0,0x1F,0x90,0x41,0x82,0xE0,0xFE,0xA3,
+
+	0xE0,0x2C,0xF5,0x82,0xE4,0x3E,0xF5,0x83,
+
+	0xE0,0xFF,0x90,0x41,0x85,0xE0,0x2F,0xF0,
+
+	0x90,0x41,0x84,0xE0,0x34,0x00,0xF0,0x80,
+
+	0x1D,0x90,0x41,0x82,0xE0,0xFE,0xA3,0xE0,
+
+	0x2C,0xF5,0x82,0xE4,0x3E,0xF5,0x83,0xE0,
+
+	0xFE,0x90,0x41,0x85,0xE0,0x24,0x00,0xF0,
+
+	0x90,0x41,0x84,0xE0,0x3E,0xF0,0x0C,0x80,
+
+	0xB8,0x90,0x41,0x84,0xE0,0xFE,0xA3,0xE0,
+
+	0xF4,0xFF,0xEE,0xF4,0xFE,0x22,0xC0,0xE0,
+
+	0xC0,0xF0,0xC0,0x83,0xC0,0x82,0xC0,0x85,
+
+	0xC0,0x84,0xC0,0x86,0x75,0x86,0x00,0xC0,
+
+	0xD0,0x75,0xD0,0x00,0xC0,0x00,0xC0,0x01,
+
+	0xC0,0x02,0xC0,0x03,0xC0,0x04,0xC0,0x05,
+
+	0xC0,0x06,0xC0,0x07,0x90,0x41,0xAD,0x74,
+
+	0xFE,0xF0,0x90,0xF4,0x05,0xE0,0x20,0xE5,
+
+	0x03,0x02,0x52,0xAD,0x75,0x12,0x00,0x90,
+
+	0xF6,0xB4,0xE0,0x30,0xE0,0x1F,0x90,0xF4,
+
+	0x09,0xE0,0xF4,0x60,0x18,0x90,0xF7,0x00,
+
+	0xE0,0x04,0xFF,0x90,0xF4,0x09,0xE0,0xC3,
+
+	0x9F,0x50,0x0A,0x90,0xF4,0x05,0xE0,0x44,
+
+	0x20,0xF0,0x02,0x52,0xAD,0x90,0xF6,0xB4,
+
+	0xE0,0x30,0xE0,0x05,0x90,0xF4,0x09,0xE4,
+
+	0xF0,0x90,0xF6,0xB4,0xE0,0x20,0xE0,0x46,
+
+	0x90,0xF6,0x6F,0xE0,0x20,0xE0,0x3F,0x90,
+
+	0xF6,0x04,0xE0,0x54,0xF0,0x60,0x37,0x90,
+
+	0xF6,0x03,0xE0,0x04,0xF0,0x90,0xF4,0x05,
+
+	0x74,0x20,0xF0,0x90,0x41,0x8C,0xE0,0x04,
+
+	0xF0,0x70,0x06,0x90,0x41,0x8B,0xE0,0x04,
+
+	0xF0,0x90,0xF6,0x04,0xE0,0x30,0xE1,0xF9,
+
+	0x90,0xF6,0x04,0xE4,0xF0,0xE0,0x44,0x01,
+
+	0xF0,0xE0,0x54,0xFE,0xF0,0x90,0xF6,0x03,
+
+	0xE0,0x14,0xF0,0x02,0x52,0xAD,0x90,0xF7,
+
+	0x01,0xE0,0x54,0x70,0x70,0x03,0x02,0x4A,
+
+	0x6A,0xE0,0x54,0x0F,0xFE,0xA3,0xE0,0xC3,
+
+	0x94,0x06,0xEE,0x94,0x00,0x40,0x03,0x02,
+
+	0x4A,0x61,0x90,0xF1,0x03,0xE0,0x90,0x41,
+
+	0x91,0xF0,0x90,0xF6,0xB5,0xE0,0x54,0xF7,
+
+	0x44,0x08,0xF0,0xE0,0x54,0xF7,0xF0,0x90,
+
+	0x41,0x91,0xE0,0x90,0xF1,0x03,0xF0,0x90,
+
+	0x41,0x8E,0xE0,0x90,0xF0,0x00,0xF0,0x90,
+
+	0x44,0xB8,0xE0,0x60,0x09,0x90,0xF1,0x04,
+
+	0xE0,0x54,0xF3,0xF0,0x80,0x09,0x90,0xF1,
+
+	0x04,0xE0,0x54,0xF3,0x44,0x04,0xF0,0x90,
+
+	0xF7,0x00,0xE0,0x04,0xF5,0x11,0x90,0xF1,
+
+	0x01,0xF0,0x90,0xF7,0x01,0xE0,0x54,0x70,
+
+	0xFF,0x74,0xFE,0x25,0x11,0xF5,0x82,0xE4,
+
+	0x34,0xF6,0xF5,0x83,0xE0,0x2F,0xF0,0x90,
+
+	0xF7,0x01,0xE0,0x54,0x8F,0xF0,0xE5,0x11,
+
+	0x60,0x1E,0x15,0x11,0xE4,0x25,0x11,0xF5,
+
+	0x82,0xE4,0x34,0xF7,0xF5,0x83,0xE0,0xFF,
+
+	0xE5,0x11,0x24,0x01,0xFD,0xE4,0x34,0xF0,
+
+	0x8D,0x82,0xF5,0x83,0xEF,0xF0,0x80,0xDE,
+
+	0x90,0xF1,0x00,0xE0,0x54,0xFE,0xF0,0x90,
+
+	0xF1,0x02,0x74,0x01,0xF0,0x90,0xF7,0x02,
+
+	0xE0,0x30,0xE0,0x05,0x75,0x11,0x05,0x80,
+
+	0x08,0x90,0xF7,0x04,0xE0,0x24,0x05,0xF5,
+
+	0x11,0x90,0xF1,0x02,0xE0,0x30,0xE2,0x0F,
+
+	0x90,0xF4,0x05,0x74,0x20,0xF0,0x90,0xF1,
+
+	0x02,0x74,0x02,0xF0,0x02,0x52,0xAD,0x90,
+
+	0xF1,0x02,0xE0,0x30,0xE1,0xE3,0x74,0x02,
+
+	0xF0,0x90,0xF4,0x12,0xE5,0x11,0xF0,0xA3,
+
+	0xE4,0xF0,0xA3,0xE0,0x54,0xFC,0xF0,0x90,
+
+	0xF0,0x00,0xE0,0x04,0xF0,0x90,0xF1,0x01,
+
+	0xE5,0x11,0xF0,0x90,0xF1,0x00,0xE0,0x44,
+
+	0x01,0xF0,0x90,0xF1,0x02,0x74,0x01,0xF0,
+
+	0x75,0x0F,0x00,0x75,0x10,0x00,0x90,0xF1,
+
+	0x02,0xE0,0x20,0xE3,0x2A,0xE0,0x30,0xE2,
+
+	0xF5,0x74,0x02,0xF0,0xAE,0x0F,0xAF,0x10,
+
+	0xBE,0xFF,0x0C,0xBF,0xFF,0x09,0x90,0xF4,
+
+	0x05,0x74,0x20,0xF0,0x02,0x52,0xAD,0x90,
+
+	0xF1,0x02,0x74,0x01,0xF0,0x05,0x10,0xE5,
+
+	0x10,0x70,0x02,0x05,0x0F,0x80,0xCF,0xE5,
+
+	0x11,0x60,0x1D,0x15,0x11,0xE4,0x25,0x11,
+
+	0xFF,0xE4,0x34,0xF0,0x8F,0x82,0xF5,0x83,
+
+	0xE0,0xFF,0xE4,0x25,0x11,0xF5,0x82,0xE4,
+
+	0x34,0xF7,0xF5,0x83,0xEF,0xF0,0x80,0xDF,
+
+	0x90,0xF4,0x05,0x74,0x20,0xF0,0x90,0x44,
+
+	0xB8,0xE0,0x60,0x1C,0x7E,0xDE,0x7F,0x40,
+
+	0x90,0xF7,0x00,0xE0,0x04,0xFB,0x7D,0x00,
+
+	0x7C,0xF7,0x12,0x56,0x9C,0x90,0xF7,0x00,
+
+	0xE0,0x04,0x90,0xDD,0x86,0xF0,0x80,0x07,
+
+	0x90,0xF4,0x11,0xE0,0x54,0xFC,0xF0,0x90,
+
+	0xF1,0x02,0x74,0x08,0xF0,0x02,0x52,0xAD,
+
+	0x90,0xF4,0x05,0x74,0x20,0xF0,0x02,0x52,
+
+	0xAD,0x90,0xF7,0x03,0xE0,0x90,0x41,0xB2,
+
+	0xF0,0x90,0xF7,0x00,0xE0,0x64,0x03,0x70,
+
+	0x2C,0xA3,0xE0,0x64,0x02,0x70,0x26,0x90,
+
+	0xF7,0x00,0x04,0xF0,0x90,0xF7,0x02,0xE0,
+
+	0xFE,0xA3,0xE0,0xF5,0x82,0x8E,0x83,0xE0,
+
+	0x90,0xF7,0x01,0xF0,0x90,0xF4,0x12,0x74,
+
+	0x02,0xF0,0xA3,0xE4,0xF0,0xA3,0xE0,0x54,
+
+	0xFC,0xF0,0x02,0x51,0xE1,0x90,0xF7,0x00,
+
+	0xE0,0xB4,0x04,0x20,0xA3,0xE0,0xB4,0x03,
+
+	0x1B,0x90,0xF7,0x04,0xE0,0xFF,0x90,0xF7,
+
+	0x02,0xE0,0xFC,0xA3,0xE0,0xF5,0x82,0x8C,
+
+	0x83,0xEF,0xF0,0x90,0xF4,0x05,0x74,0x20,
+
+	0xF0,0x02,0x52,0xAD,0x90,0xF7,0x00,0xE0,
+
+	0xB4,0x04,0x0D,0xA3,0xE0,0xB4,0x04,0x08,
+
+	0x90,0x41,0xAE,0x74,0x01,0xF0,0x80,0x12,
+
+	0x90,0xF7,0x00,0xE0,0x64,0x05,0x70,0x77,
+
+	0xA3,0xE0,0x64,0x05,0x70,0x71,0x90,0x41,
+
+	0xAE,0xF0,0x90,0xF7,0x02,0xE0,0xFD,0x90,
+
+	0x41,0xAE,0xE0,0xFB,0x90,0xF7,0x03,0xE0,
+
+	0x90,0x41,0xC4,0xF0,0x90,0xF7,0x04,0xE0,
+
+	0xFF,0xA3,0xE0,0x90,0x41,0xC5,0xCF,0xF0,
+
+	0xA3,0xEF,0xF0,0xEB,0x60,0x06,0x7E,0xF7,
+
+	0x7F,0x01,0x80,0x04,0x7E,0xF7,0x7F,0x06,
+
+	0x90,0x41,0xC7,0xEE,0xF0,0xA3,0xEF,0xF0,
+
+	0xA3,0xE4,0xF0,0xA3,0x04,0xF0,0x7F,0x02,
+
+	0x12,0x57,0x94,0x90,0x41,0xB0,0xEF,0xF0,
+
+	0x90,0x41,0xAE,0xE0,0x70,0x09,0x90,0xF4,
+
+	0x05,0x74,0x20,0xF0,0x02,0x52,0xAD,0x90,
+
+	0xF7,0x00,0x74,0x01,0xF0,0x90,0x41,0xB0,
+
+	0xE0,0x70,0x03,0x02,0x4A,0x95,0x90,0xF7,
+
+	0x01,0x74,0xFF,0xF0,0x02,0x4A,0x95,0x90,
+
+	0x41,0xAD,0x74,0xFF,0xF0,0x90,0x41,0xB8,
+
+	0x74,0x01,0xF0,0x90,0xF7,0x01,0xE0,0xFE,
+
+	0xA3,0xE0,0xFF,0xEE,0x60,0x03,0x02,0x51,
+
+	0xDE,0xEF,0x12,0x7E,0xB5,0x4E,0x42,0x00,
+
+	0x4B,0xB2,0x01,0x4C,0xE8,0x02,0x4C,0xE1,
+
+	0x03,0x4D,0x9B,0x04,0x4D,0x94,0x05,0x4E,
+
+	0x5A,0x06,0x4C,0x6A,0x18,0x4C,0x0C,0x22,
+
+	0x4F,0xE3,0x23,0x51,0xD3,0x25,0x50,0xA2,
+
+	0x29,0x50,0x18,0x2A,0x50,0x2F,0x2B,0x4E,
+
+	0x5A,0x30,0x4E,0xE2,0x32,0x00,0x00,0x51,
+
+	0xDE,0x90,0xF6,0xB4,0xE0,0x54,0x08,0xF5,
+
+	0x12,0x60,0x04,0xE0,0x54,0xF7,0xF0,0x90,
+
+	0xF7,0x04,0xE0,0xF5,0x11,0x90,0xF7,0x08,
+
+	0xE0,0xFE,0xA3,0xE0,0xFF,0x80,0x00,0xE5,
+
+	0x11,0x60,0x27,0x15,0x11,0x74,0x0A,0x25,
+
+	0x11,0xF5,0x82,0xE4,0x34,0xF7,0xF5,0x83,
+
+	0xE0,0xFF,0xE5,0x11,0xFD,0x7C,0x00,0x90,
+
+	0xF7,0x08,0xE0,0xFA,0xA3,0xE0,0x2D,0xFD,
+
+	0xEC,0x3A,0x8D,0x82,0xF5,0x83,0xEF,0xF0,
+
+	0x80,0xD5,0xE5,0x12,0x60,0x07,0x90,0xF6,
+
+	0xB4,0xE0,0x44,0x08,0xF0,0x75,0x12,0x00,
+
+	0x02,0x51,0xE1,0x90,0xF4,0x12,0x74,0x09,
+
+	0xF0,0xA3,0xE4,0xF0,0xA3,0xE0,0x54,0xFC,
+
+	0xF0,0x90,0xF7,0x00,0x74,0x08,0xF0,0x90,
+
+	0xF7,0x03,0xE0,0x90,0xF7,0x01,0xF0,0xA3,
+
+	0xE4,0xF0,0xA3,0x74,0x0A,0xF0,0xA3,0xF0,
+
+	0xA3,0x74,0x03,0xF0,0xA3,0xE4,0xF0,0x90,
+
+	0xF7,0x03,0xE0,0xFE,0xA3,0xE0,0xFF,0x90,
+
+	0xF7,0x01,0xE0,0xFC,0xA3,0xE0,0x2F,0xFF,
+
+	0xEC,0x3E,0xFE,0x90,0xF7,0x05,0xE0,0xFC,
+
+	0xA3,0xE0,0x2F,0xFF,0xEC,0x3E,0xFE,0xEF,
+
+	0xF4,0xFF,0xEE,0xF4,0xA3,0xF0,0xA3,0xEF,
+
+	0xF0,0x90,0x41,0xAD,0xE4,0xF0,0x02,0x51,
+
+	0xE1,0x90,0xF7,0x00,0x74,0x08,0xF0,0x90,
+
+	0xF7,0x03,0xE0,0x90,0xF7,0x01,0xF0,0x90,
+
+	0x44,0xDE,0xE0,0x60,0x40,0x90,0x44,0xDE,
+
+	0xE4,0xF0,0x90,0xF7,0x02,0xF0,0x90,0x44,
+
+	0xDD,0x04,0xF0,0x90,0x44,0xDF,0xE0,0xFF,
+
+	0x90,0x41,0x86,0xF0,0x90,0xDE,0x80,0xE0,
+
+	0x90,0xF7,0x03,0xF0,0x90,0xDE,0x81,0xE0,
+
+	0x90,0xF7,0x04,0xF0,0x90,0xDE,0x82,0xE0,
+
+	0x90,0xF7,0x05,0xF0,0x90,0xDE,0x83,0xE0,
+
+	0x90,0xF7,0x06,0xF0,0x90,0x41,0x86,0xE0,
+
+	0xB5,0x07,0xC2,0x80,0x06,0x90,0xF7,0x02,
+
+	0x74,0x01,0xF0,0x90,0xF7,0x00,0xE0,0x04,
+
+	0x90,0xF4,0x12,0xF0,0xA3,0xE4,0xF0,0xA3,
+
+	0xE0,0x54,0xFC,0xF0,0x90,0x44,0xDD,0xE4,
+
+	0xF0,0x90,0x41,0xAD,0xF0,0x02,0x51,0xE1,
+
+	0x90,0x41,0xAE,0xE4,0xF0,0x80,0x06,0x90,
+
+	0x41,0xAE,0x74,0x01,0xF0,0x90,0x41,0xAF,
+
+	0x74,0x02,0xF0,0x90,0x41,0xAE,0xE0,0x60,
+
+	0x07,0x90,0xF7,0x04,0xE0,0xFF,0x80,0x02,
+
+	0x7F,0x00,0xEF,0x24,0x04,0x90,0x41,0xB1,
+
+	0xF0,0x90,0xF7,0x05,0xE0,0xB4,0x01,0x08,
+
+	0x90,0x41,0xDE,0xE0,0xFF,0xFD,0x80,0x06,
+
+	0x90,0xF7,0x05,0xE0,0xFF,0xFD,0x90,0x41,
+
+	0xAE,0xE0,0xFB,0x90,0xF7,0x06,0xE0,0x90,
+
+	0x41,0xC4,0xF0,0x90,0xF7,0x07,0xE0,0xFF,
+
+	0xA3,0xE0,0x90,0x41,0xC5,0xCF,0xF0,0xA3,
+
+	0xEF,0xF0,0xEB,0x60,0x06,0x7E,0xF7,0x7F,
+
+	0x03,0x80,0x04,0x7E,0xF7,0x7F,0x09,0x90,
+
+	0x41,0xC7,0xEE,0xF0,0xA3,0xEF,0xF0,0x90,
+
+	0xF7,0x04,0xE0,0xFF,0x90,0x41,0xC9,0xE4,
+
+	0xF0,0xA3,0xEF,0xF0,0x7F,0x02,0x12,0x57,
+
+	0x94,0x90,0x41,0xB0,0xEF,0xF0,0xA3,0xE0,
+
+	0xFF,0x90,0xF7,0x00,0xF0,0x90,0x41,0xB2,
+
+	0xE0,0x90,0xF7,0x01,0xF0,0x90,0x41,0xB0,
+
+	0xE0,0x90,0xF7,0x02,0xF0,0xEF,0x04,0x90,
+
+	0xF4,0x12,0xF0,0xA3,0xE4,0xF0,0xA3,0xE0,
+
+	0x54,0xFC,0xF0,0x90,0x41,0xAD,0xE4,0xF0,
+
+	0x02,0x51,0xE1,0x90,0x41,0xAE,0xE4,0xF0,
+
+	0x80,0x06,0x90,0x41,0xAE,0x74,0x01,0xF0,
+
+	0x90,0x44,0xB8,0xE0,0x60,0x04,0x7F,0x01,
+
+	0x80,0x02,0x7F,0x03,0x90,0x41,0xAF,0xEF,
+
+	0xF0,0x90,0x41,0xAE,0xE0,0xFB,0x60,0x07,
+
+	0x90,0xF7,0x04,0xE0,0xFF,0x80,0x02,0x7F,
+
+	0x00,0xEF,0x24,0x04,0x90,0x41,0xB1,0xF0,
+
+	0x90,0xF7,0x05,0xE0,0xB4,0x01,0x08,0x90,
+
+	0x41,0xDE,0xE0,0xFF,0xFD,0x80,0x06,0x90,
+
+	0xF7,0x05,0xE0,0xFF,0xFD,0x90,0xF7,0x08,
+
+	0xE0,0x90,0x44,0xC9,0xF0,0xEB,0x60,0x06,
+
+	0x7E,0xF7,0x7F,0x03,0x80,0x04,0x7E,0xF7,
+
+	0x7F,0x09,0x90,0x44,0xCA,0xEE,0xF0,0xA3,
+
+	0xEF,0xF0,0x90,0xF7,0x04,0xE0,0xFF,0x90,
+
+	0x44,0xCC,0xE4,0xF0,0xA3,0xEF,0xF0,0x90,
+
+	0x41,0xAF,0xE0,0xFF,0x12,0x6A,0xEA,0x90,
+
+	0x41,0xB0,0xEF,0xF0,0xA3,0xE0,0xFF,0x90,
+
+	0xF7,0x00,0xF0,0x90,0x41,0xB2,0xE0,0x90,
+
+	0xF7,0x01,0xF0,0x90,0x41,0xB0,0xE0,0x90,
+
+	0xF7,0x02,0xF0,0xEF,0x04,0x90,0xF4,0x12,
+
+	0xF0,0xA3,0xE4,0xF0,0xA3,0xE0,0x54,0xFC,
+
+	0xF0,0x90,0x41,0xAD,0xE4,0xF0,0x02,0x51,
+
+	0xE1,0x90,0xF7,0x04,0xE0,0xFF,0x90,0xF7,
+
+	0x08,0xE0,0xFC,0xA3,0xE0,0xFD,0x12,0x47,
+
+	0x02,0x90,0x41,0xAD,0xE4,0xF0,0x02,0x51,
+
+	0xE1,0xC2,0x8C,0xC2,0x8D,0x75,0x8A,0x00,
+
+	0x75,0x8C,0x00,0xE5,0x89,0x54,0xF0,0x44,
+
+	0x01,0xF5,0x89,0xD2,0x8C,0x90,0x41,0x87,
+
+	0xE4,0xF0,0x90,0xF4,0x04,0xE0,0x54,0x04,
+
+	0xFF,0x13,0x13,0x54,0x3F,0x60,0x21,0xE0,
+
+	0x54,0xFB,0x44,0x04,0xF0,0xA3,0x74,0x20,
+
+	0xF0,0x90,0xF4,0x14,0xE0,0x54,0x7F,0xF0,
+
+	0x90,0xF4,0x11,0xE0,0x54,0xFC,0x44,0x02,
+
+	0xF0,0xC2,0x8C,0xC2,0x8D,0x02,0x52,0xAD,
+
+	0x30,0x8D,0xCF,0xC2,0x8C,0xC2,0x8D,0x90,
+
+	0x41,0x87,0xE0,0x04,0xF0,0xE0,0xD3,0x94,
+
+	0x01,0x40,0x2A,0x90,0xF4,0x14,0xE0,0x54,
+
+	0x7F,0x44,0x80,0xF0,0xE0,0x54,0xFC,0xF0,
+
+	0x90,0xF4,0x13,0x74,0x08,0xF0,0x90,0xF4,
+
+	0x12,0xE4,0xF0,0x90,0xF4,0x05,0x74,0x20,
+
+	0xF0,0x90,0xF4,0x11,0xE0,0x54,0xFC,0x44,
+
+	0x01,0xF0,0x02,0x52,0xAD,0xD2,0x8C,0x80,
+
+	0x91,0x90,0xF7,0x0A,0xE0,0xFF,0x90,0x41,
+
+	0xB8,0xF0,0x90,0x41,0x88,0xF0,0x90,0xF4,
+
+	0x14,0xE0,0x30,0xE7,0x1F,0x90,0xF7,0x04,
+
+	0xE0,0x54,0x03,0xFF,0x90,0xF4,0x14,0xE0,
+
+	0x54,0xFC,0x4F,0xF0,0x90,0xF7,0x05,0xE0,
+
+	0x90,0xF4,0x13,0xF0,0x90,0xF7,0x06,0xE0,
+
+	0x90,0xF4,0x12,0xF0,0x90,0xF4,0x05,0x74,
+
+	0x20,0xF0,0x90,0xF4,0x11,0xE0,0x54,0x03,
+
+	0x60,0x08,0x90,0x41,0x89,0xE0,0x64,0x01,
+
+	0x60,0x1B,0x90,0xF7,0x07,0xE0,0xB4,0xF0,
+
+	0x0B,0x90,0xF4,0x11,0xE0,0x54,0xFC,0x44,
+
+	0x02,0xF0,0x80,0x09,0x90,0xF4,0x11,0xE0,
+
+	0x54,0xFC,0x44,0x01,0xF0,0x90,0x41,0x89,
+
+	0xE4,0xF0,0x90,0x41,0x88,0xE0,0xB4,0x01,
+
+	0x0C,0x90,0xF4,0x04,0xE0,0x54,0xFB,0x44,
+
+	0x04,0xF0,0x02,0x52,0xAD,0x90,0xF4,0x05,
+
+	0xE0,0x20,0xE5,0x09,0x90,0xF4,0x15,0xE0,
+
+	0xC3,0x94,0x05,0x40,0xF0,0x90,0xF4,0x04,
+
+	0xE0,0x54,0xFB,0x44,0x04,0xF0,0xA3,0xE0,
+
+	0x30,0xE5,0x09,0x90,0x41,0x89,0x74,0x01,
+
+	0xF0,0x02,0x52,0xAD,0x90,0x41,0xB8,0xE0,
+
+	0x14,0xF0,0x70,0x03,0x02,0x52,0xAD,0x90,
+
+	0xF4,0x15,0xE0,0x70,0xFA,0xA3,0xE0,0x70,
+
+	0xF6,0xA3,0xE0,0x54,0x03,0x70,0xF0,0x90,
+
+	0xF4,0x04,0xE0,0x54,0x04,0xFF,0x13,0x13,
+
+	0x54,0x3F,0x60,0x0C,0x90,0x41,0x8A,0xE0,
+
+	0xC3,0x94,0xFF,0x50,0x03,0xE0,0x04,0xF0,
+
+	0x90,0xF4,0x05,0xE0,0x20,0xE5,0x0D,0x90,
+
+	0xF4,0x04,0xE0,0x54,0x04,0xFF,0x13,0x13,
+
+	0x54,0x3F,0x60,0xEC,0x90,0xF4,0x05,0xE0,
+
+	0x20,0xE5,0x03,0x02,0x4F,0x1B,0x90,0xF4,
+
+	0x04,0xE0,0x54,0xFB,0x44,0x04,0xF0,0x02,
+
+	0x52,0xAD,0xC2,0xAF,0x90,0xF6,0xB3,0xE0,
+
+	0x54,0xFE,0xF0,0x90,0xF6,0xDE,0xE0,0x54,
+
+	0xFE,0x44,0x01,0xF0,0x90,0xF6,0xDE,0xE0,
+
+	0x20,0xE0,0xF9,0x90,0x44,0xB8,0xE0,0x60,
+
+	0x07,0x90,0xDD,0x00,0xE0,0x54,0x7F,0xF0,
+
+	0x90,0xF4,0x05,0x74,0x20,0xF0,0x90,0xF6,
+
+	0x2F,0xE0,0x54,0xFE,0x44,0x01,0xF0,0x90,
+
+	0x41,0xAE,0x74,0x01,0xF0,0x90,0xF7,0x06,
+
+	0xE0,0x44,0x01,0xF0,0x90,0xF7,0x03,0xE0,
+
+	0x90,0xF7,0x01,0xF0,0x80,0x1D,0x90,0x41,
+
+	0xAE,0xE4,0xF0,0x90,0xF7,0x03,0xE0,0x90,
+
+	0xF7,0x01,0xF0,0x7E,0xF0,0x7F,0x01,0x90,
+
+	0xF7,0x04,0xE0,0xFB,0x7D,0x07,0x7C,0xF7,
+
+	0x12,0x56,0x9C,0x90,0xF7,0x04,0xE0,0xF5,
+
+	0x11,0xA3,0xE0,0xFF,0xA3,0xE0,0xFD,0x90,
+
+	0x41,0xBD,0x74,0x01,0xF0,0xAB,0x11,0x12,
+
+	0x54,0xB6,0x8F,0x12,0x90,0xF7,0x02,0xEF,
+
+	0xF0,0x90,0x41,0xAE,0xE0,0x64,0x01,0x60,
+
+	0x03,0x02,0x51,0xE1,0x7C,0xF0,0x7D,0x00,
+
+	0x90,0xF7,0x04,0xE0,0xFB,0x7F,0x03,0x7E,
+
+	0xF7,0x12,0x56,0x9C,0x90,0x41,0xAD,0xE4,
+
+	0xF0,0xE5,0x11,0x24,0x04,0x90,0xF7,0x00,
+
+	0xF0,0xE0,0x90,0xF4,0x12,0xF0,0xA3,0xE4,
+
+	0xF0,0xA3,0xE0,0x54,0xFC,0xF0,0x02,0x51,
+
+	0xE1,0x90,0x41,0xB6,0x74,0xF7,0xF0,0xA3,
+
+	0x74,0x08,0xF0,0x90,0xF7,0x04,0xE0,0x24,
+
+	0xFE,0x60,0x10,0x14,0x60,0x7F,0x24,0x02,
+
+	0x60,0x03,0x02,0x51,0xC8,0x75,0x12,0x01,
+
+	0x02,0x51,0xC8,0x90,0xF7,0x07,0xE0,0x75,
+
+	0xF0,0x02,0xA4,0x24,0x08,0xFE,0xE5,0xF0,
+
+	0x34,0xF7,0x90,0x41,0xB4,0xF0,0xA3,0xCE,
+
+	0xF0,0x90,0x41,0xB3,0xE4,0xF0,0x90,0xF7,
+
+	0x07,0xE0,0xFF,0x90,0x41,0xB3,0xE0,0xC3,
+
+	0x9F,0x50,0x44,0xA3,0xE0,0xFE,0xA3,0xE0,
+
+	0xF5,0x82,0x8E,0x83,0xE0,0xFF,0x90,0x41,
+
+	0xB6,0xE0,0xFC,0xA3,0xE0,0xF5,0x82,0x8C,
+
+	0x83,0xE0,0xFC,0xA3,0xE0,0xF5,0x82,0x8C,
+
+	0x83,0xEF,0xF0,0x90,0x41,0xB3,0xE0,0x04,
+
+	0xF0,0x90,0x41,0xB5,0xE0,0x04,0xF0,0x70,
+
+	0x06,0x90,0x41,0xB4,0xE0,0x04,0xF0,0x90,
+
+	0x41,0xB7,0xE0,0x24,0x02,0xF0,0x90,0x41,
+
+	0xB6,0xE0,0x34,0x00,0xF0,0x80,0xAF,0x75,
+
+	0x12,0x00,0x02,0x51,0xC8,0x90,0xF7,0x07,
+
+	0xE0,0x75,0xF0,0x03,0xA4,0x24,0x08,0xFE,
+
+	0xE5,0xF0,0x34,0xF7,0x90,0x41,0xB4,0xF0,
+
+	0xA3,0xCE,0xF0,0x90,0xF7,0x07,0xE0,0x75,
+
+	0xF0,0x03,0xA4,0x24,0x08,0x90,0xF6,0x20,
+
+	0xF0,0x90,0x41,0xB3,0xE4,0xF0,0x90,0xF7,
+
+	0x07,0xE0,0xFF,0x90,0x41,0xB3,0xE0,0xC3,
+
+	0x9F,0x50,0x59,0x90,0x41,0xB6,0xE0,0xFE,
+
+	0xA3,0xE0,0xFF,0x24,0x02,0xFD,0xE4,0x3E,
+
+	0x8D,0x82,0xF5,0x83,0xE0,0xFD,0x90,0x41,
+
+	0xB9,0xF0,0xFB,0x8F,0x82,0x8E,0x83,0xE0,
+
+	0xFE,0xA3,0xE0,0xFF,0x90,0x41,0xB4,0xE0,
+
+	0xFC,0xA3,0xE0,0xFD,0x12,0x56,0x9C,0x90,
+
+	0x41,0xB9,0xE0,0xFF,0x90,0x41,0xB5,0xE0,
+
+	0x2F,0xF0,0x90,0x41,0xB4,0xE0,0x34,0x00,
+
+	0xF0,0x90,0x41,0xB3,0xE0,0x04,0xF0,0x90,
+
+	0x41,0xB6,0xE0,0xFE,0xA3,0xE0,0x24,0x03,
+
+	0xFF,0xE4,0x3E,0x90,0x41,0xB6,0xF0,0xA3,
+
+	0xEF,0xF0,0x80,0x9A,0x75,0x12,0x00,0x90,
+
+	0x41,0xAD,0x74,0xFF,0xF0,0x75,0x12,0x00,
+
+	0x80,0x0E,0x90,0x41,0xAD,0x74,0xFF,0xF0,
+
+	0x75,0x12,0xFA,0x80,0x03,0x75,0x12,0x02,
+
+	0x90,0x41,0xAD,0xE0,0xFF,0xF4,0x60,0x5E,
+
+	0xEF,0x64,0xFE,0x60,0x59,0x90,0xF7,0x00,
+
+	0xE0,0x24,0xFE,0xFD,0x7F,0x01,0x7E,0xF7,
+
+	0x12,0x47,0xAC,0x90,0xF7,0x00,0xE0,0x24,
+
+	0xFF,0xF5,0x82,0xE4,0x34,0xF6,0xF5,0x83,
+
+	0xEE,0xF0,0xA3,0xEF,0xF0,0x90,0xF4,0x05,
+
+	0x74,0x20,0xF0,0x90,0x44,0xB8,0xE0,0x60,
+
+	0x1C,0x7E,0xDE,0x7F,0x40,0x90,0xF7,0x00,
+
+	0xE0,0x04,0xFB,0x7D,0x00,0x7C,0xF7,0x12,
+
+	0x56,0x9C,0x90,0xF7,0x00,0xE0,0x04,0x90,
+
+	0xDD,0x86,0xF0,0x80,0x77,0x90,0x41,0xAD,
+
+	0xE0,0x54,0x03,0xFF,0x90,0xF4,0x11,0xE0,
+
+	0x54,0xFC,0x4F,0xF0,0x80,0x66,0x90,0x41,
+
+	0xAD,0xE0,0xF4,0x70,0x30,0x90,0xF4,0x12,
+
+	0x74,0x05,0xF0,0xA3,0xE4,0xF0,0xA3,0xE0,
+
+	0x54,0xFC,0xF0,0x90,0xF7,0x00,0x74,0x04,
+
+	0xF0,0x90,0xF7,0x03,0xE0,0x90,0xF7,0x01,
+
+	0xF0,0xA3,0xE5,0x12,0xF0,0x90,0xF7,0x01,
+
+	0xE0,0xFE,0xA3,0xE0,0xF4,0xFF,0xEE,0xF4,
+
+	0xA3,0xF0,0xA3,0xEF,0xF0,0x90,0xF4,0x05,
+
+	0x74,0x20,0xF0,0x90,0x44,0xB8,0xE0,0x60,
+
+	0x1C,0x7E,0xDE,0x7F,0x40,0x90,0xF7,0x00,
+
+	0xE0,0x04,0xFB,0x7D,0x00,0x7C,0xF7,0x12,
+
+	0x56,0x9C,0x90,0xF7,0x00,0xE0,0x04,0x90,
+
+	0xDD,0x86,0xF0,0x80,0x07,0x90,0xF4,0x11,
+
+	0xE0,0x54,0xFC,0xF0,0xD0,0x07,0xD0,0x06,
+
+	0xD0,0x05,0xD0,0x04,0xD0,0x03,0xD0,0x02,
+
+	0xD0,0x01,0xD0,0x00,0xD0,0xD0,0xD0,0x86,
+
+	0xD0,0x84,0xD0,0x85,0xD0,0x82,0xD0,0x83,
+
+	0xD0,0xF0,0xD0,0xE0,0x32,0x32,0x32,0x32,
+
+	0x32,0x32,0x90,0xF6,0x13,0xE0,0x30,0xE0,
+
+	0x03,0x7F,0x03,0x22,0x90,0xF6,0xB4,0xE0,
+
+	0x30,0xE0,0x03,0x7F,0x00,0x22,0x90,0xF6,
+
+	0x6F,0xE0,0x30,0xE0,0x03,0x7F,0x02,0x22,
+
+	0x7F,0x01,0x22,0x90,0x41,0x7F,0xE0,0x90,
+
+	0x41,0x8E,0xF0,0xE0,0x54,0xF9,0xFF,0xBF,
+
+	0x38,0x04,0x7F,0x01,0x80,0x02,0x7F,0x00,
+
+	0xEF,0x54,0x01,0xFF,0x90,0xD8,0x1A,0xE0,
+
+	0x54,0xFE,0x4F,0xF0,0x90,0xF6,0x41,0xE0,
+
+	0xB4,0x22,0x12,0x90,0xD8,0xD1,0xE0,0x54,
+
+	0xFE,0x44,0x01,0xF0,0x90,0xD8,0xD0,0xE0,
+
+	0x54,0xFE,0x44,0x01,0xF0,0x90,0xD8,0x30,
+
+	0xE0,0x54,0xFE,0x44,0x01,0xF0,0xA3,0xE0,
+
+	0x54,0xFE,0xF0,0xA3,0xE0,0x54,0xFE,0xF0,
+
+	0x90,0xD8,0x29,0xE0,0x54,0xFE,0xF0,0x90,
+
+	0xF6,0xB3,0xE0,0x54,0xFE,0x44,0x01,0xF0,
+
+	0x90,0xF6,0x32,0x74,0xFF,0xF0,0xA3,0xF0,
+
+	0x90,0xF6,0x31,0xE0,0x54,0xFE,0x44,0x01,
+
+	0xF0,0x90,0xF6,0x13,0xE0,0x54,0x01,0x90,
+
+	0x44,0xB8,0xF0,0x12,0x7C,0x41,0x12,0x52,
+
+	0xD3,0x90,0x41,0x90,0xEF,0xF0,0x90,0xF6,
+
+	0xA0,0x74,0x04,0xF0,0x90,0x41,0x90,0xE0,
+
+	0x90,0xF6,0xA1,0xF0,0x90,0xF6,0xDE,0xE0,
+
+	0x54,0xFE,0x44,0x01,0xF0,0x90,0xF6,0xDE,
+
+	0xE0,0x20,0xE0,0xF9,0x90,0xDF,0x82,0xE0,
+
+	0x44,0x20,0xF0,0x90,0xDD,0x17,0xE0,0x54,
+
+	0xFE,0xF0,0xC2,0xDC,0xD2,0xBC,0x12,0x56,
+
+	0xD8,0xD2,0xE9,0x12,0x78,0x4B,0x12,0x5A,
+
+	0x72,0x90,0xF4,0x18,0xE4,0xF0,0xA3,0xE0,
+
+	0x54,0xF0,0x44,0x08,0xF0,0x90,0xF4,0x1E,
+
+	0xE0,0x54,0xEF,0x44,0x10,0xF0,0xC2,0xB8,
+
+	0xC2,0xBA,0xD2,0xAF,0xD2,0xA8,0xD2,0xAA,
+
+	0x90,0xDF,0x82,0xE0,0x30,0xE0,0x1A,0xA2,
+
+	0xAF,0xE4,0x33,0x90,0x41,0x8D,0xF0,0xC2,
+
+	0xAF,0x90,0xDF,0x82,0x74,0x20,0xF0,0xE4,
+
+	0xF0,0x90,0x41,0x8D,0xE0,0x24,0xFF,0x92,
+
+	0xAF,0x90,0x41,0x81,0xE0,0xFF,0x90,0x43,
+
+	0x43,0xE0,0x6F,0x60,0x1D,0xA2,0xAF,0xE4,
+
+	0x33,0x90,0x41,0x8D,0xF0,0xC2,0xAF,0x90,
+
+	0x44,0xDE,0xE0,0x70,0x05,0x90,0x43,0x43,
+
+	0xEF,0xF0,0x90,0x41,0x8D,0xE0,0x24,0xFF,
+
+	0x92,0xAF,0x12,0x58,0xDB,0x90,0x41,0x8F,
+
+	0xE0,0xB4,0x07,0x05,0x12,0x5A,0x0B,0x80,
+
+	0xA7,0x12,0x59,0x73,0x80,0xA2,0x22,0x75,
+
+	0x81,0x18,0x02,0x54,0x71,0x02,0x52,0xF4,
+
+	0xE4,0x93,0xA3,0xF8,0xE4,0x93,0xA3,0x40,
+
+	0x03,0xF6,0x80,0x01,0xF2,0x08,0xDF,0xF4,
+
+	0x80,0x29,0xE4,0x93,0xA3,0xF8,0x54,0x07,
+
+	0x24,0x0C,0xC8,0xC3,0x33,0xC4,0x54,0x0F,
+
+	0x44,0x20,0xC8,0x83,0x40,0x04,0xF4,0x56,
+
+	0x80,0x01,0x46,0xF6,0xDF,0xE4,0x80,0x0B,
+
+	0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,
+
+	0x90,0x64,0x98,0xE4,0x7E,0x01,0x93,0x60,
+
+	0xBC,0xA3,0xFF,0x54,0x3F,0x30,0xE5,0x09,
+
+	0x54,0x1F,0xFE,0xE4,0x93,0xA3,0x60,0x01,
+
+	0x0E,0xCF,0x54,0xC0,0x25,0xE0,0x60,0xA8,
+
+	0x40,0xB8,0xE4,0x93,0xA3,0xFA,0xE4,0x93,
+
+	0xA3,0xF8,0xE4,0x93,0xA3,0xC8,0xC5,0x82,
+
+	0xC8,0xCA,0xC5,0x83,0xCA,0xF0,0xA3,0xC8,
+
+	0xC5,0x82,0xC8,0xCA,0xC5,0x83,0xCA,0xDF,
+
+	0xE9,0xDE,0xE7,0x80,0xBE,0x90,0x41,0xBA,
+
+	0xEF,0xF0,0xA3,0xED,0xF0,0xA3,0xEB,0xF0,
+
+	0x90,0x41,0x92,0xE0,0xB4,0x01,0x2E,0x90,
+
+	0x41,0xBC,0xE0,0x24,0x01,0xFF,0xE4,0x33,
+
+	0xFE,0xE4,0xFC,0xFD,0x7B,0xFB,0x7A,0x04,
+
+	0xF9,0xF8,0x12,0x7D,0x98,0xE4,0x7B,0x04,
+
+	0xFA,0xF9,0xF8,0x12,0x7E,0x23,0xEF,0x24,
+
+	0x03,0xFF,0xE4,0x3E,0xFE,0xE4,0x3D,0xFD,
+
+	0xE4,0x3C,0xFC,0x80,0x3F,0x90,0x41,0xBC,
+
+	0xE0,0x24,0x01,0xFF,0xE4,0x33,0xFE,0xE4,
+
+	0xFC,0xFD,0x7B,0x05,0xFA,0xF9,0xF8,0x12,
+
+	0x7D,0x98,0xA8,0x04,0xA9,0x05,0xAA,0x06,
+
+	0xAB,0x07,0x90,0xF1,0x03,0xE0,0xFF,0xE4,
+
+	0xFC,0xFD,0xFE,0x12,0x7D,0x98,0xE4,0x7B,
+
+	0x04,0xFA,0xF9,0xF8,0x12,0x7E,0x23,0xEF,
+
+	0x24,0x03,0xFF,0xE4,0x3E,0xFE,0xE4,0x3D,
+
+	0xFD,0xE4,0x3C,0xFC,0x90,0x41,0xBF,0xEE,
+
+	0xF0,0xA3,0xEF,0xF0,0x90,0x41,0xBB,0xE0,
+
+	0x90,0xF0,0x00,0xF0,0x90,0x41,0x92,0xE0,
+
+	0xB4,0x01,0x27,0x90,0x41,0x98,0xE0,0xFF,
+
+	0x90,0x41,0x97,0xE0,0x2F,0xFF,0xE4,0x33,
+
+	0xFE,0xC3,0xEF,0x94,0x0A,0xEE,0x64,0x80,
+
+	0x94,0x80,0x50,0x05,0x12,0x7C,0x0E,0x80,
+
+	0x09,0x90,0x41,0xBE,0x74,0x05,0xF0,0x02,
+
+	0x56,0x8E,0x90,0xF1,0x03,0xE0,0x90,0x41,
+
+	0x91,0xF0,0x90,0xF6,0xB5,0xE0,0x54,0xF7,
+
+	0x44,0x08,0xF0,0xE0,0x54,0xF7,0xF0,0x90,
+
+	0x41,0x91,0xE0,0x90,0xF1,0x03,0xF0,0x90,
+
+	0x41,0xBA,0xE0,0xFF,0xB4,0x01,0x09,0x90,
+
+	0xF1,0x04,0xE0,0x54,0xF3,0xF0,0x80,0x18,
+
+	0xEF,0xB4,0x02,0x0B,0x90,0xF1,0x04,0xE0,
+
+	0x54,0xF3,0x44,0x08,0xF0,0x80,0x09,0x90,
+
+	0xF1,0x04,0xE0,0x54,0xF3,0x44,0x04,0xF0,
+
+	0x90,0x41,0xBB,0xE0,0x54,0x01,0xFF,0x90,
+
+	0xF1,0x00,0xE0,0x54,0xFE,0x4F,0xF0,0x90,
+
+	0x41,0xBC,0xE0,0x90,0xF1,0x01,0xF0,0x12,
+
+	0x7B,0x3E,0x90,0x41,0xBD,0xE0,0x64,0x01,
+
+	0x60,0x03,0x02,0x56,0x6C,0x90,0xF1,0x02,
+
+	0xE0,0x20,0xE2,0x16,0xE0,0x20,0xE1,0x12,
+
+	0xE0,0x20,0xE3,0x0E,0x90,0x41,0xBF,0x74,
+
+	0xFF,0xF5,0xF0,0x12,0x7D,0x6C,0x45,0xF0,
+
+	0x70,0xE3,0x90,0x41,0xBF,0xE0,0x70,0x02,
+
+	0xA3,0xE0,0x70,0x25,0x90,0xF1,0x03,0xE0,
+
+	0x90,0x41,0x91,0xF0,0x90,0xF6,0xB5,0xE0,
+
+	0x54,0xF7,0x44,0x08,0xF0,0xE0,0x54,0xF7,
+
+	0xF0,0x90,0x41,0x91,0xE0,0x90,0xF1,0x03,
+
+	0xF0,0x90,0x41,0xBE,0x74,0x04,0xF0,0x80,
+
+	0x49,0x90,0xF1,0x02,0xE0,0x30,0xE2,0x08,
+
+	0x90,0x41,0xBE,0x74,0x02,0xF0,0x80,0x3A,
+
+	0x90,0x41,0xBB,0xE0,0x30,0xE0,0x16,0x90,
+
+	0xF1,0x02,0xE0,0x30,0xE1,0x08,0x90,0x41,
+
+	0xBE,0x74,0x01,0xF0,0x80,0x24,0xE4,0x90,
+
+	0x41,0xBE,0xF0,0x80,0x1D,0x90,0xF1,0x02,
+
+	0xE0,0x30,0xE3,0x08,0x90,0x41,0xBE,0x74,
+
+	0x01,0xF0,0x80,0x0E,0xE4,0x90,0x41,0xBE,
+
+	0xF0,0x80,0x07,0xE4,0x90,0x41,0xBE,0xF0,
+
+	0x80,0x1B,0x90,0x41,0xBB,0xE0,0x30,0xE0,
+
+	0x0B,0x90,0xF1,0x02,0xE0,0x54,0xF7,0x44,
+
+	0x08,0xF0,0x80,0x09,0x90,0xF1,0x02,0xE0,
+
+	0x54,0xFD,0x44,0x02,0xF0,0x90,0x41,0x91,
+
+	0xE0,0x90,0xF1,0x03,0xF0,0x90,0x41,0xBE,
+
+	0xE0,0xFF,0x22,0xAA,0x86,0x53,0x86,0xFE,
+
+	0x8E,0x85,0x8F,0x84,0x8C,0x83,0x8D,0x82,
+
+	0x0B,0x80,0x0A,0xE0,0xA3,0x63,0x86,0x01,
+
+	0xF0,0xA3,0x63,0x86,0x01,0xDB,0xF4,0x8A,
+
+	0x86,0x22,0x43,0x8E,0x08,0x53,0x89,0xF0,
+
+	0x43,0x89,0x01,0x22,0xAD,0x07,0xAC,0x06,
+
+	0xC2,0x8C,0xC2,0x8D,0xEC,0xF4,0xF5,0x8C,
+
+	0xED,0xF4,0xF5,0x8A,0xD2,0x8C,0x22,0xC2,
+
+	0xAF,0x90,0x41,0x03,0x74,0x02,0xF0,0xA3,
+
+	0x74,0x47,0xF0,0xA3,0x74,0x00,0xF0,0x90,
+
+	0x41,0x0B,0x74,0x02,0xF0,0xA3,0x74,0x47,
+
+	0xF0,0xA3,0x74,0x01,0xF0,0x90,0x41,0x13,
+
+	0x74,0x02,0xF0,0xA3,0x74,0x48,0xF0,0xA3,
+
+	0x74,0x0F,0xF0,0x90,0x41,0x1B,0x74,0x02,
+
+	0xF0,0xA3,0x74,0x52,0xF0,0xA3,0x74,0xCE,
+
+	0xF0,0x90,0x41,0x23,0x74,0x02,0xF0,0xA3,
+
+	0x74,0x57,0xF0,0xA3,0x74,0x93,0xF0,0x90,
+
+	0x41,0x2B,0x74,0x02,0xF0,0xA3,0x74,0x6D,
+
+	0xF0,0xA3,0x74,0xA9,0xF0,0x90,0x41,0x33,
+
+	0x74,0x02,0xF0,0xA3,0x74,0x67,0xF0,0xA3,
+
+	0x74,0x3B,0xF0,0x90,0x41,0x3B,0x74,0x02,
+
+	0xF0,0xA3,0x74,0x52,0xF0,0xA3,0x74,0xCF,
+
+	0xF0,0x90,0x41,0x43,0x74,0x02,0xF0,0xA3,
+
+	0x74,0x52,0xF0,0xA3,0x74,0xD0,0xF0,0x90,
+
+	0x41,0x4B,0x74,0x02,0xF0,0xA3,0x74,0x60,
+
+	0xF0,0xA3,0x74,0x6A,0xF0,0x90,0x41,0x53,
+
+	0x74,0x02,0xF0,0xA3,0x74,0x52,0xF0,0xA3,
+
+	0x74,0xD1,0xF0,0x90,0x41,0x5B,0x74,0x02,
+
+	0xF0,0xA3,0x74,0x52,0xF0,0xA3,0x74,0xD2,
+
+	0xF0,0x90,0x41,0x63,0x74,0x02,0xF0,0xA3,
+
+	0x74,0x67,0xF0,0xA3,0x74,0x85,0xF0,0xD2,
+
+	0xAF,0x22,0x32,0x90,0x41,0xC1,0xEF,0xF0,
+
+	0xA3,0xED,0xF0,0xEB,0x70,0x61,0x90,0x41,
+
+	0xC4,0xE0,0xFF,0xB4,0x01,0x0A,0x90,0x41,
+
+	0xC6,0xE0,0x90,0xF0,0x01,0xF0,0x80,0x14,
+
+	0xEF,0xB4,0x02,0x10,0x90,0x41,0xC5,0xE0,
+
+	0x90,0xF0,0x01,0xF0,0x90,0x41,0xC6,0xE0,
+
+	0x90,0xF0,0x02,0xF0,0x90,0x41,0xC4,0xE0,
+
+	0x24,0x01,0xF5,0x82,0xE4,0x34,0xF0,0xAF,
+
+	0x82,0xFE,0x90,0x41,0xC7,0xE0,0xFC,0xA3,
+
+	0xE0,0xFD,0x90,0x41,0xCA,0xE0,0xFB,0x12,
+
+	0x56,0x9C,0x90,0x41,0xC1,0xE0,0xFF,0xA3,
+
+	0xE0,0xFD,0x90,0x41,0xCA,0xE0,0xFE,0x90,
+
+	0x41,0xC4,0xE0,0x2E,0xFB,0x90,0x41,0xBD,
+
+	0x74,0x01,0xF0,0x12,0x54,0xB6,0x22,0x90,
+
+	0x41,0xC4,0xE0,0x70,0x22,0x90,0x41,0xC1,
+
+	0xE0,0xFF,0xA3,0xE0,0x44,0x01,0xFD,0x90,
+
+	0x41,0xCA,0xE0,0xFB,0x90,0x41,0xBD,0x74,
+
+	0x01,0xF0,0x12,0x54,0xB6,0x90,0x41,0xCB,
+
+	0xEF,0xF0,0x60,0x5F,0xE0,0xFF,0x22,0x7E,
+
+	0xF0,0x7F,0x01,0x90,0x41,0xC4,0xE0,0xFD,
+
+	0xC3,0x74,0xC7,0x9D,0xF9,0x74,0x41,0x94,
+
+	0x00,0xFC,0xAD,0x01,0xE0,0xFB,0x12,0x56,
+
+	0x9C,0x90,0x41,0xC1,0xE0,0xFF,0xA3,0xE0,
+
+	0xFD,0x90,0x41,0xC4,0xE0,0xFB,0x90,0x41,
+
+	0xBD,0x74,0x01,0xF0,0x12,0x54,0xB6,0x90,
+
+	0x41,0xCB,0xEF,0xF0,0x60,0x03,0xE0,0xFF,
+
+	0x22,0x90,0x41,0xC1,0xE0,0xFF,0xA3,0xE0,
+
+	0x44,0x01,0xFD,0x90,0x41,0xCA,0xE0,0xFB,
+
+	0x90,0x41,0xBD,0x74,0x01,0xF0,0x12,0x54,
+
+	0xB6,0x90,0x41,0xCB,0xEF,0xF0,0x60,0x03,
+
+	0xE0,0xFF,0x22,0x90,0x41,0xC7,0xE0,0xFE,
+
+	0xA3,0xE0,0xFF,0x7C,0xF0,0x7D,0x00,0x90,
+
+	0x41,0xCA,0xE0,0xFB,0x12,0x56,0x9C,0x7F,
+
+	0x00,0x22,0x90,0x41,0xCC,0xEE,0xF0,0xA3,
+
+	0xEF,0xF0,0xA3,0xEC,0xF0,0xA3,0xED,0xF0,
+
+	0x90,0x41,0xC4,0x74,0x01,0xF0,0x90,0x41,
+
+	0xCC,0xE0,0xFF,0xA3,0xE0,0x90,0x41,0xC5,
+
+	0xCF,0xF0,0xA3,0xEF,0xF0,0x90,0x41,0xCE,
+
+	0xE0,0xFF,0xA3,0xE0,0x90,0x41,0xC7,0xCF,
+
+	0xF0,0xA3,0xEF,0xF0,0xA3,0xE4,0xF0,0xA3,
+
+	0x04,0xF0,0x7D,0xC0,0x7F,0x02,0x12,0x57,
+
+	0x94,0x22,0xC2,0xE9,0x90,0x41,0xD3,0xE0,
+
+	0xFF,0xA3,0xE0,0xFE,0xA3,0xE0,0xFD,0xA3,
+
+	0xE0,0xFC,0xD2,0xE9,0x60,0x06,0xED,0xD3,
+
+	0x94,0x02,0x40,0x06,0x90,0xF6,0xA5,0xE4,
+
+	0xF0,0x22,0xED,0xD3,0x94,0x00,0x40,0x16,
+
+	0xED,0xC4,0x54,0xF0,0xFC,0x74,0x37,0x9C,
+
+	0xFC,0xEE,0xC4,0x54,0x0F,0xFB,0xC3,0xEC,
+
+	0x9B,0x90,0xF6,0xA5,0xF0,0x22,0xEE,0xD3,
+
+	0x94,0x0C,0x40,0x10,0xEE,0x13,0x13,0x13,
+
+	0x54,0x1F,0xFC,0xC3,0x74,0x49,0x9C,0x90,
+
+	0xF6,0xA5,0xF0,0x22,0xEE,0xD3,0x94,0x02,
+
+	0x40,0x19,0xEE,0x25,0xE0,0xFC,0xC3,0x74,
+
+	0x5F,0x9C,0xFC,0xEF,0xC4,0x13,0x13,0x13,
+
+	0x54,0x01,0xFB,0xC3,0xEC,0x9B,0x90,0xF6,
+
+	0xA5,0xF0,0x22,0xED,0xD3,0x94,0x10,0x40,
+
+	0x1A,0xEE,0x25,0xE0,0x25,0xE0,0xFE,0xC3,
+
+	0x74,0x64,0x9E,0xFE,0xEF,0xC4,0x13,0x13,
+
+	0x54,0x03,0xFF,0xC3,0xEE,0x9F,0x90,0xF6,
+
+	0xA5,0xF0,0x22,0x90,0xF6,0xA5,0x74,0x64,
+
+	0xF0,0x22,0xC2,0xE9,0x90,0x41,0xD7,0xE0,
+
+	0xFF,0x90,0x41,0xD9,0xE0,0xFD,0x90,0x41,
+
+	0xDB,0xE0,0x90,0x41,0xD2,0xF0,0x90,0x41,
+
+	0xDC,0xE0,0xF9,0xD2,0xE9,0xEF,0xFE,0x7C,
+
+	0x00,0xE4,0x2D,0xFF,0xEC,0x3E,0xFE,0x90,
+
+	0x41,0xD0,0xF0,0xA3,0xEF,0xF0,0xD3,0x94,
+
+	0x64,0xEE,0x94,0x00,0x40,0x45,0x90,0x43,
+
+	0x4F,0xE0,0xB4,0x01,0x1C,0xE9,0xFF,0x90,
+
+	0x41,0xD2,0xE0,0x2F,0xFF,0xEC,0x33,0xCF,
+
+	0x24,0x71,0xCF,0x34,0xFF,0xFE,0x7D,0x28,
+
+	0x12,0x7D,0x05,0xAA,0x06,0xAB,0x07,0x80,
+
+	0x13,0xAF,0x01,0x7E,0x00,0x7C,0x00,0x7D,
+
+	0x28,0x12,0x7D,0x05,0xEF,0x24,0xA0,0xFB,
+
+	0xEE,0x34,0x14,0xFA,0xEA,0xFF,0x90,0x43,
+
+	0x4E,0xE0,0x2F,0xFF,0x24,0x05,0x90,0xF6,
+
+	0xA6,0xF0,0x22,0x90,0x41,0xD0,0xE0,0xFE,
+
+	0xA3,0xE0,0xFF,0xC3,0x74,0x64,0x9F,0xFF,
+
+	0xE4,0x9E,0xFE,0x7C,0x00,0x7D,0x06,0x12,
+
+	0x7D,0x17,0xEF,0x24,0x50,0x90,0xF6,0xA6,
+
+	0xF0,0x22,0xC2,0xE9,0x90,0x41,0xDD,0xE0,
+
+	0xFF,0xD2,0xE9,0xC3,0x13,0x24,0x1A,0x90,
+
+	0xF6,0xA6,0xF0,0xE0,0xC3,0x94,0x5A,0x40,
+
+	0x0A,0xE0,0xD3,0x94,0x64,0x50,0x04,0xA3,
+
+	0xE4,0xF0,0x22,0x90,0xF6,0xA6,0xE0,0xFF,
+
+	0x74,0x5A,0xD3,0x9F,0x40,0x0F,0xE0,0x94,
+
+	0x28,0x40,0x0A,0xE0,0xFF,0x74,0x5A,0x9F,
+
+	0x25,0xE0,0xA3,0xF0,0x22,0x90,0xF6,0xA6,
+
+	0xE0,0xC3,0x94,0x28,0x50,0x0A,0xE0,0xC3,
+
+	0x94,0x00,0x40,0x04,0xA3,0x74,0x64,0xF0,
+
+	0x22,0xE4,0x90,0x44,0xB5,0xF0,0x90,0x44,
+
+	0xB6,0xF0,0x90,0x44,0xB7,0xF0,0x90,0x44,
+
+	0xC5,0xF0,0x12,0x6A,0xDF,0x12,0x64,0xA0,
+
+	0x22,0x90,0x45,0x18,0xE0,0x60,0x38,0x74,
+
+	0x41,0x90,0x41,0x7F,0xF0,0x74,0xE4,0xA3,
+
+	0xF0,0x90,0x45,0x34,0xE0,0x70,0x05,0x12,
+
+	0x6D,0x4C,0x80,0x1B,0x90,0x45,0x34,0xE0,
+
+	0xB4,0x01,0x05,0x12,0x6D,0x56,0x80,0x0F,
+
+	0x90,0x45,0x34,0xE0,0x64,0x02,0x60,0x04,
+
+	0xE0,0xB4,0xFF,0x03,0x12,0x78,0xFE,0x90,
+
+	0x44,0xB8,0xE0,0x70,0x02,0xD2,0xDD,0x90,
+
+	0x44,0xB8,0xE0,0x60,0x06,0x12,0x68,0x68,
+
+	0x12,0x68,0x49,0x22,0x90,0x43,0x54,0xE0,
+
+	0xFF,0x20,0xE7,0x03,0x02,0x5B,0x98,0xB4,
+
+	0xA1,0x19,0xA3,0xE0,0x24,0xFE,0x60,0x0D,
+
+	0x14,0x60,0x0D,0x24,0x02,0x60,0x03,0x02,
+
+	0x5C,0x52,0x7F,0x21,0x22,0x7F,0x22,0x22,
+
+	0x7F,0x23,0x22,0x90,0x43,0x54,0xE0,0xFF,
+
+	0x54,0x60,0x60,0x03,0x02,0x5C,0x52,0x90,
+
+	0x43,0x55,0xE0,0x24,0xFA,0x60,0x2D,0x24,
+
+	0xFE,0x70,0x03,0x02,0x5B,0x92,0x24,0xFE,
+
+	0x70,0x03,0x02,0x5B,0x95,0x24,0x0A,0x60,
+
+	0x03,0x02,0x5C,0x52,0xEF,0x24,0x7F,0x60,
+
+	0x0D,0x14,0x60,0x0D,0x24,0x02,0x60,0x03,
+
+	0x02,0x5C,0x52,0x7F,0x01,0x22,0x7F,0x02,
+
+	0x22,0x7F,0x03,0x22,0x90,0x43,0x54,0xE0,
+
+	0xB4,0x81,0x1B,0x90,0x43,0x57,0xE0,0x24,
+
+	0xDE,0x60,0x0D,0x14,0x60,0x0D,0x24,0x02,
+
+	0x60,0x03,0x02,0x5C,0x52,0x7F,0x6B,0x22,
+
+	0x7F,0x6C,0x22,0x7F,0x6D,0x22,0x90,0x43,
+
+	0x57,0xE0,0x14,0xB4,0x08,0x00,0x40,0x03,
+
+	0x02,0x5C,0x52,0x90,0x5B,0x62,0x75,0xF0,
+
+	0x03,0xA4,0xC5,0x83,0x25,0xF0,0xC5,0x83,
+
+	0x73,0x02,0x5B,0x7A,0x02,0x5B,0x7D,0x02,
+
+	0x5B,0x80,0x02,0x5B,0x83,0x02,0x5B,0x86,
+
+	0x02,0x5B,0x89,0x02,0x5B,0x8C,0x02,0x5B,
+
+	0x8F,0x7F,0x60,0x22,0x7F,0x61,0x22,0x7F,
+
+	0x62,0x22,0x7F,0x63,0x22,0x7F,0x64,0x22,
+
+	0x7F,0x65,0x22,0x7F,0x66,0x22,0x7F,0x67,
+
+	0x22,0x7F,0x80,0x22,0x7F,0xA0,0x22,0x90,
+
+	0x43,0x54,0xE0,0xB4,0x21,0x19,0xA3,0xE0,
+
+	0x24,0xF6,0x60,0x0D,0x14,0x60,0x0D,0x24,
+
+	0x02,0x60,0x03,0x02,0x5C,0x52,0x7F,0x29,
+
+	0x22,0x7F,0x2B,0x22,0x7F,0x2B,0x22,0x90,
+
+	0x43,0x54,0xE0,0xFF,0x54,0x60,0x60,0x03,
+
+	0x02,0x5C,0x52,0x90,0x43,0x55,0xE0,0x24,
+
+	0xFD,0x60,0x39,0x24,0xFE,0x60,0x63,0x24,
+
+	0xFE,0x60,0x6B,0x24,0xFE,0x60,0x74,0x24,
+
+	0xFE,0x60,0x73,0x24,0x0A,0x70,0x72,0xEF,
+
+	0x24,0xFE,0x60,0x17,0x24,0x02,0x70,0x69,
+
+	0x90,0x43,0x56,0xE0,0xFE,0xB4,0x01,0x03,
+
+	0x7F,0x10,0x22,0xEE,0x64,0x02,0x70,0x59,
+
+	0x7F,0x12,0x22,0x90,0x43,0x56,0xE0,0x70,
+
+	0x50,0x7F,0x13,0x22,0x90,0x43,0x54,0xE0,
+
+	0x24,0xFE,0x60,0x1D,0x24,0x02,0x70,0x41,
+
+	0x90,0x43,0x56,0xE0,0xFE,0xB4,0x01,0x03,
+
+	0x7F,0x30,0x22,0xEE,0x64,0x02,0x70,0x31,
+
+	0x90,0x43,0x58,0xE0,0x70,0x2B,0x7F,0x31,
+
+	0x22,0x90,0x43,0x56,0xE0,0x70,0x22,0x7F,
+
+	0x32,0x22,0x90,0x43,0x56,0xE0,0xC3,0x94,
+
+	0x80,0x50,0x16,0x7F,0x50,0x22,0x90,0x43,
+
+	0x54,0xE0,0xB4,0x01,0x03,0x7F,0x71,0x22,
+
+	0x7F,0x70,0x22,0x7F,0x90,0x22,0x7F,0xB0,
+
+	0x22,0x7F,0x00,0x22,0xE4,0xFF,0x7F,0x06,
+
+	0x90,0x43,0x5C,0xE4,0xF0,0xA3,0xDF,0xFC,
+
+	0x22,0x90,0x44,0x67,0xE0,0x24,0xA0,0x60,
+
+	0x2D,0x14,0x60,0x35,0x14,0x70,0x03,0x02,
+
+	0x5C,0xFD,0x24,0xFD,0x70,0x03,0x02,0x5D,
+
+	0x5D,0x14,0x70,0x03,0x02,0x5D,0x67,0x24,
+
+	0x16,0x60,0x03,0x02,0x5D,0xC9,0x90,0x43,
+
+	0x56,0xE0,0x90,0xDD,0x10,0xF0,0xE4,0x90,
+
+	0x44,0x68,0xF0,0x02,0x5D,0xCC,0x90,0x43,
+
+	0x64,0xE0,0xFF,0x12,0x68,0xD9,0x02,0x5D,
+
+	0xCC,0x90,0x44,0xC5,0xE0,0x60,0x29,0x78,
+
+	0x89,0x7C,0x43,0x7D,0x01,0x7B,0x01,0x7A,
+
+	0x43,0x79,0x80,0x7E,0x00,0x7F,0x09,0x12,
+
+	0x7F,0x9D,0x90,0x43,0x8A,0x74,0x02,0xF0,
+
+	0x7F,0x00,0x7E,0x40,0x12,0x6A,0x7A,0x7F,
+
+	0x02,0x7E,0x00,0x12,0x6A,0xBB,0x80,0x21,
+
+	0x78,0x89,0x7C,0x43,0x7D,0x01,0x7B,0x01,
+
+	0x7A,0x44,0x79,0x6A,0x7E,0x00,0x7F,0x09,
+
+	0x12,0x7F,0x9D,0x7F,0x02,0x7E,0x00,0x12,
+
+	0x6A,0x7A,0x7F,0x14,0x7E,0x00,0x12,0x6A,
+
+	0xBB,0x90,0x43,0x8B,0xE0,0xFF,0x12,0x68,
+
+	0xD9,0x02,0x5D,0xCC,0xE4,0xFF,0x90,0x43,
+
+	0x56,0xE0,0xFE,0xEF,0xC3,0x9E,0x50,0x2C,
+
+	0x90,0x44,0x69,0xE0,0xFE,0x90,0x45,0x03,
+
+	0xE0,0x75,0xF0,0x08,0xA4,0x2E,0xF5,0x82,
+
+	0xE4,0x35,0xF0,0xF5,0x83,0xE5,0x82,0x24,
+
+	0x00,0xF5,0x82,0xE5,0x83,0x34,0x45,0xF5,
+
+	0x83,0xE0,0xFE,0x90,0x44,0x69,0xE0,0x2E,
+
+	0xF0,0x0F,0x80,0xCA,0x90,0x44,0x69,0xE0,
+
+	0xFF,0x90,0x45,0x03,0xE0,0x75,0xF0,0x08,
+
+	0xA4,0x2F,0xF5,0x82,0xE4,0x35,0xF0,0xF5,
+
+	0x83,0xE5,0x82,0x24,0x00,0xF5,0x82,0xE5,
+
+	0x83,0x34,0x45,0xF5,0x83,0xE0,0xFF,0x12,
+
+	0x68,0xD9,0x80,0x6F,0x90,0x43,0x76,0xE0,
+
+	0xFF,0x12,0x68,0xD9,0x80,0x65,0x90,0x44,
+
+	0xC5,0xE0,0x60,0x31,0x78,0x89,0x7C,0x43,
+
+	0x7D,0x01,0x7B,0x01,0x7A,0x44,0x79,0x6A,
+
+	0x7E,0x00,0x7F,0x09,0x12,0x7F,0x9D,0x90,
+
+	0x43,0x8A,0x74,0x07,0xF0,0x7F,0x02,0x7E,
+
+	0x00,0x12,0x6A,0x7A,0x7F,0x14,0x7E,0x00,
+
+	0x12,0x6A,0xBB,0x90,0x43,0x8B,0xE0,0xFF,
+
+	0x12,0x68,0xD9,0x80,0x2E,0x78,0x89,0x7C,
+
+	0x43,0x7D,0x01,0x7B,0x01,0x7A,0x43,0x79,
+
+	0x80,0x7E,0x00,0x7F,0x09,0x12,0x7F,0x9D,
+
+	0x90,0x43,0x8B,0xE0,0xFF,0x12,0x68,0xD9,
+
+	0x7F,0x00,0x7E,0x40,0x12,0x6A,0x7A,0x7F,
+
+	0x02,0x7E,0x00,0x12,0x6A,0xBB,0x80,0x03,
+
+	0x7F,0x07,0x22,0x7F,0x00,0x22,0x90,0x44,
+
+	0x67,0xE0,0xFF,0x14,0x24,0xFD,0x50,0x3A,
+
+	0x24,0xF4,0x70,0x03,0x02,0x5E,0x6D,0x24,
+
+	0xFD,0x70,0x03,0x02,0x5E,0x75,0x24,0xE2,
+
+	0x70,0x03,0x02,0x5E,0xA6,0x14,0x70,0x03,
+
+	0x02,0x5E,0x8D,0x24,0xB2,0x70,0x03,0x02,
+
+	0x5E,0xD6,0x24,0xF0,0x70,0x03,0x02,0x5E,
+
+	0xE6,0x24,0xF0,0x70,0x03,0x02,0x5E,0xF8,
+
+	0x24,0xF0,0x70,0x03,0x02,0x5F,0x08,0x02,
+
+	0x5F,0x1A,0xEF,0xB4,0x01,0x26,0x90,0x44,
+
+	0xC5,0xE0,0x60,0x10,0x90,0x43,0x87,0xE0,
+
+	0xFF,0xC4,0x13,0x13,0x54,0x01,0x90,0xDE,
+
+	0x00,0xF0,0x80,0x32,0x90,0x44,0x71,0xE0,
+
+	0xFF,0xC4,0x13,0x13,0x54,0x01,0x90,0xDE,
+
+	0x00,0xF0,0x80,0x22,0x90,0x44,0x67,0xE0,
+
+	0xB4,0x02,0x07,0xE4,0x90,0xDE,0x00,0xF0,
+
+	0x80,0x14,0x90,0x43,0x58,0xE0,0x54,0x0F,
+
+	0x24,0x5C,0xF5,0x82,0xE4,0x34,0x43,0xF5,
+
+	0x83,0xE0,0x90,0xDE,0x00,0xF0,0xE4,0x90,
+
+	0xDE,0x01,0xF0,0x90,0x44,0x68,0x74,0x02,
+
+	0xF0,0x02,0x5F,0x1D,0xE4,0x90,0x44,0x68,
+
+	0xF0,0x02,0x5F,0x1D,0x90,0x43,0x58,0xE0,
+
+	0x54,0x0F,0x24,0x5C,0xF5,0x82,0xE4,0x34,
+
+	0x43,0xF5,0x83,0xE4,0xF0,0x90,0x44,0x68,
+
+	0xF0,0x02,0x5F,0x1D,0x90,0x43,0x58,0xE0,
+
+	0x54,0x0F,0x24,0x5C,0xF5,0x82,0xE4,0x34,
+
+	0x43,0xF5,0x83,0x74,0x01,0xF0,0xE4,0x90,
+
+	0x44,0x68,0xF0,0x80,0x77,0x90,0x44,0xC5,
+
+	0xE0,0x60,0x08,0xE4,0x90,0x44,0xB6,0xF0,
+
+	0x7F,0x07,0x22,0x90,0x43,0x59,0xE0,0x14,
+
+	0x24,0xFC,0x50,0x02,0x80,0x08,0x90,0x44,
+
+	0xB6,0x74,0x01,0xF0,0x80,0x08,0xE4,0x90,
+
+	0x44,0xB6,0xF0,0x7F,0x07,0x22,0xE4,0x90,
+
+	0x44,0x68,0xF0,0x80,0x47,0x90,0x43,0x62,
+
+	0xE0,0x90,0xDE,0x00,0xF0,0x90,0x44,0x68,
+
+	0x74,0x01,0xF0,0x80,0x37,0x12,0x5C,0x55,
+
+	0x90,0x43,0x56,0xE0,0x90,0x43,0x62,0xF0,
+
+	0xE4,0x90,0x44,0x68,0xF0,0x80,0x25,0x90,
+
+	0x43,0x63,0xE0,0x90,0xDE,0x00,0xF0,0x90,
+
+	0x44,0x68,0x74,0x01,0xF0,0x80,0x15,0x12,
+
+	0x5C,0x55,0x90,0x43,0x56,0xE0,0x90,0x43,
+
+	0x63,0xF0,0xE4,0x90,0x44,0x68,0xF0,0x80,
+
+	0x03,0x7F,0x07,0x22,0x7F,0x00,0x22,0x90,
+
+	0x44,0x67,0xE0,0x24,0xDE,0x60,0x1F,0x24,
+
+	0xF7,0x60,0x2B,0x24,0xBF,0x60,0x0D,0x04,
+
+	0x70,0x33,0x90,0x43,0xF3,0xE0,0xFF,0x12,
+
+	0x68,0xD9,0x80,0x2C,0x90,0x43,0xFA,0xE0,
+
+	0xFF,0x12,0x68,0xD9,0x80,0x22,0x90,0x44,
+
+	0xB4,0xE0,0x90,0xDE,0x00,0xF0,0x90,0x44,
+
+	0x68,0x74,0x01,0xF0,0x80,0x12,0x90,0x43,
+
+	0x57,0xE0,0x90,0x44,0xB4,0xF0,0xE4,0x90,
+
+	0x44,0x68,0xF0,0x80,0x03,0x7F,0x07,0x22,
+
+	0x7F,0x00,0x22,0x90,0x44,0x67,0xE0,0x12,
+
+	0x7E,0xB5,0x5F,0xB6,0x01,0x5F,0xB6,0x02,
+
+	0x5F,0xB6,0x03,0x5F,0xB6,0x10,0x5F,0xB6,
+
+	0x13,0x5F,0xB6,0x22,0x5F,0xB6,0x2B,0x5F,
+
+	0xB6,0x31,0x5F,0xB6,0x32,0x5F,0xB6,0x50,
+
+	0x5F,0xC0,0x60,0x5F,0xD6,0x61,0x5F,0xEC,
+
+	0x62,0x5F,0xCB,0x65,0x5F,0xE1,0x66,0x60,
+
+	0x03,0x6B,0x60,0x0E,0x6C,0x5F,0xB6,0x80,
+
+	0x5F,0xB6,0x90,0x5F,0xB6,0xA0,0x5F,0xB6,
+
+	0xB0,0x00,0x00,0x60,0x19,0x90,0x44,0x68,
+
+	0xE0,0x90,0xDD,0x85,0xF0,0x80,0x5C,0x7A,
+
+	0x43,0x79,0x64,0x7B,0x01,0x12,0x68,0xFE,
+
+	0x80,0x51,0x7A,0x43,0x79,0x76,0x7B,0x01,
+
+	0x12,0x68,0xFE,0x80,0x46,0x7A,0x43,0x79,
+
+	0x89,0x7B,0x01,0x12,0x68,0xFE,0x80,0x3B,
+
+	0x7A,0x43,0x79,0x89,0x7B,0x01,0x12,0x68,
+
+	0xFE,0x80,0x30,0x90,0x45,0x03,0xE0,0x75,
+
+	0xF0,0x08,0xA4,0x24,0x00,0xF9,0x74,0x45,
+
+	0x35,0xF0,0xFA,0x7B,0x01,0x12,0x68,0xFE,
+
+	0x80,0x19,0x7A,0x43,0x79,0xF3,0x7B,0x01,
+
+	0x12,0x68,0xFE,0x80,0x0E,0x7B,0x01,0x7A,
+
+	0x44,0x79,0x73,0x12,0x68,0xFE,0x80,0x03,
+
+	0x7F,0x03,0x22,0x7F,0x00,0x22,0x12,0x5A,
+
+	0xBD,0x90,0x44,0x67,0xEF,0xF0,0x90,0x44,
+
+	0x67,0xE0,0x70,0x03,0x7F,0x06,0x22,0x12,
+
+	0x68,0xA2,0xEF,0x60,0x01,0x22,0x7F,0x00,
+
+	0x22,0x12,0x5F,0x6C,0xEF,0x60,0x01,0x22,
+
+	0x7F,0x00,0x22,0x90,0xDE,0xC3,0xE0,0x90,
+
+	0xDE,0x41,0xF0,0xE4,0xA3,0xF0,0x7C,0xDE,
+
+	0x7D,0xC0,0x90,0xDE,0xC0,0xE0,0x04,0xFB,
+
+	0x7F,0x00,0x7E,0xF7,0x12,0x56,0x9C,0x90,
+
+	0xF4,0x10,0xE0,0x54,0xFE,0x44,0x01,0xF0,
+
+	0x22,0xC0,0xE0,0xC0,0xF0,0xC0,0x83,0xC0,
+
+	0x82,0xC0,0x85,0xC0,0x84,0xC0,0x86,0x75,
+
+	0x86,0x00,0xC0,0xD0,0x75,0xD0,0x00,0xC0,
+
+	0x00,0xC0,0x01,0xC0,0x02,0xC0,0x03,0xC0,
+
+	0x04,0xC0,0x05,0xC0,0x06,0xC0,0x07,0x90,
+
+	0xF6,0xA8,0xE0,0x12,0x7E,0xB5,0x60,0xCE,
+
+	0x00,0x63,0x39,0x01,0x63,0x39,0x02,0x60,
+
+	0xEB,0x04,0x61,0x0E,0x05,0x61,0x47,0x07,
+
+	0x62,0x73,0x0D,0x62,0x73,0x0E,0x62,0x73,
+
+	0x0F,0x62,0xC6,0x10,0x62,0x3D,0x11,0x61,
+
+	0x58,0x12,0x61,0xA4,0x13,0x62,0x04,0x14,
+
+	0x62,0x04,0x15,0x64,0x0D,0x16,0x64,0x3E,
+
+	0x17,0x00,0x00,0x64,0x6D,0x7E,0xDE,0x7F,
+
+	0x40,0x90,0xF7,0x00,0xE0,0x04,0xFB,0x7D,
+
+	0x00,0x7C,0xF7,0x12,0x56,0x9C,0x90,0xF7,
+
+	0x00,0xE0,0x04,0x90,0xDD,0x86,0xF0,0x02,
+
+	0x64,0x6D,0x90,0xF6,0xA9,0xE0,0x90,0x41,
+
+	0xD3,0xF0,0x90,0xF6,0xAA,0xE0,0x90,0x41,
+
+	0xD4,0xF0,0x90,0xF6,0xAB,0xE0,0x90,0x41,
+
+	0xD5,0xF0,0x90,0xF6,0xAC,0xE0,0x90,0x41,
+
+	0xD6,0xF0,0x02,0x64,0x6D,0x90,0x41,0x8F,
+
+	0x74,0x05,0xF0,0x90,0xF6,0xA9,0xE0,0x90,
+
+	0x41,0xD7,0xF0,0x90,0xF6,0xAA,0xE0,0x90,
+
+	0x41,0xD9,0xF0,0x90,0xF6,0xAB,0xE0,0x90,
+
+	0x41,0xD8,0xF0,0x90,0xF6,0xAC,0xE0,0x90,
+
+	0x41,0xDA,0xF0,0x90,0xF6,0xAD,0xE0,0x90,
+
+	0x41,0xDB,0xF0,0x90,0xF6,0xAE,0xE0,0x90,
+
+	0x41,0xDC,0xF0,0x02,0x64,0x6D,0x90,0x41,
+
+	0x8F,0x74,0x07,0xF0,0x90,0xF6,0xA9,0xE0,
+
+	0x90,0x41,0xDD,0xF0,0x02,0x64,0x6D,0x90,
+
+	0x41,0xC4,0x74,0x01,0xF0,0xA3,0xE4,0xF0,
+
+	0xA3,0xF0,0xA3,0x74,0xF0,0xF0,0xA3,0x74,
+
+	0x00,0xF0,0xA3,0xE4,0xF0,0xA3,0x74,0x10,
+
+	0xF0,0x7B,0x01,0x7D,0xC0,0x7F,0x02,0x12,
+
+	0x57,0x94,0x90,0xF0,0x01,0xE0,0xFF,0x13,
+
+	0x13,0x54,0x01,0xFE,0xEF,0x13,0x13,0x13,
+
+	0x54,0x03,0x2E,0xFF,0xE0,0x54,0x03,0x2F,
+
+	0xFF,0xC4,0x54,0xF0,0xFF,0xA3,0xE0,0xFE,
+
+	0xC4,0x54,0x0F,0x2F,0x90,0xF6,0xA4,0xF0,
+
+	0x02,0x64,0x6D,0x90,0xF6,0xA9,0xE0,0xC3,
+
+	0x94,0x40,0x50,0x1F,0xE0,0x54,0x0F,0x90,
+
+	0x43,0x4B,0xF0,0x90,0xF6,0xA9,0xE0,0xFF,
+
+	0xC4,0x54,0x0F,0x24,0x50,0xF5,0x82,0xE4,
+
+	0x34,0x43,0xF5,0x83,0xE0,0x90,0x43,0x4A,
+
+	0xF0,0x80,0x10,0x90,0xF6,0xA9,0xE0,0x54,
+
+	0x3F,0x90,0x43,0x4B,0xF0,0x90,0x43,0x4A,
+
+	0x74,0xFE,0xF0,0x90,0x41,0xC4,0x74,0x01,
+
+	0xF0,0xA3,0xE4,0xF0,0xA3,0x74,0x0A,0xF0,
+
+	0xA3,0x74,0x43,0xF0,0xA3,0x74,0x4A,0xF0,
+
+	0xA3,0xE4,0xF0,0xA3,0x74,0x02,0xF0,0xE4,
+
+	0xFB,0x7D,0xC0,0x7F,0x02,0x12,0x57,0x94,
+
+	0x02,0x64,0x6D,0x90,0xF6,0xA8,0xE0,0xB4,
+
+	0x15,0x04,0x7F,0xAC,0x80,0x02,0x7F,0x9C,
+
+	0x90,0x43,0x49,0xEF,0xF0,0x90,0x41,0xC4,
+
+	0x74,0x01,0xF0,0xA3,0xE4,0xF0,0xA3,0x74,
+
+	0x04,0xF0,0xA3,0x74,0x43,0xF0,0xA3,0x74,
+
+	0x49,0xF0,0xA3,0xE4,0xF0,0xA3,0x04,0xF0,
+
+	0xE4,0xFB,0x7D,0xC0,0x7F,0x02,0x12,0x57,
+
+	0x94,0x02,0x64,0x6D,0x7C,0x43,0x7D,0x48,
+
+	0x7B,0x01,0x7F,0x1C,0x7E,0x00,0x12,0x58,
+
+	0x9B,0x90,0x43,0x48,0xE0,0x54,0xF7,0xF0,
+
+	0xE0,0xFF,0x90,0xF6,0xA9,0xE0,0xFE,0x33,
+
+	0x33,0x33,0x54,0xF8,0xFE,0xEF,0x4E,0x90,
+
+	0x43,0x48,0xF0,0x7C,0x43,0x7D,0x48,0xE4,
+
+	0xFB,0x7F,0x1C,0xFE,0x12,0x58,0x9B,0x02,
+
+	0x64,0x6D,0x90,0x44,0xB8,0xE0,0x60,0x08,
+
+	0x90,0x43,0x46,0x74,0x01,0xF0,0x80,0x06,
+
+	0x90,0x43,0x46,0x74,0x03,0xF0,0x90,0xF0,
+
+	0x01,0x74,0x05,0xF0,0xA3,0x74,0x80,0xF0,
+
+	0x90,0xF6,0xA8,0xE0,0x90,0xF0,0x03,0xF0,
+
+	0xA3,0xE4,0xF0,0xA3,0x74,0x7F,0xF0,0x90,
+
+	0xF6,0xA8,0xE0,0xF4,0x90,0xF0,0x06,0xF0,
+
+	0x90,0x43,0x46,0xE0,0xFF,0x90,0x41,0x8E,
+
+	0xE0,0xFD,0x90,0x41,0xBD,0x74,0x01,0xF0,
+
+	0x7B,0x07,0x12,0x54,0xB6,0x90,0x43,0x45,
+
+	0xEF,0xF0,0x02,0x64,0x6D,0x90,0x41,0xC4,
+
+	0x74,0x01,0xF0,0xA3,0xE4,0xF0,0xA3,0x74,
+
+	0x07,0xF0,0xA3,0x74,0x43,0xF0,0xA3,0x74,
+
+	0x44,0xF0,0xA3,0xE4,0xF0,0xA3,0x04,0xF0,
+
+	0xFB,0x7D,0xC0,0x7F,0x02,0x12,0x57,0x94,
+
+	0x90,0xF6,0xA9,0xE0,0x90,0x43,0x4E,0xF0,
+
+	0x90,0x43,0x44,0xE0,0x54,0xC3,0xF0,0xE0,
+
+	0xFF,0x90,0x43,0x4E,0xE0,0xFE,0x25,0xE0,
+
+	0x25,0xE0,0xFE,0xEF,0x4E,0x90,0x43,0x44,
+
+	0xF0,0x90,0x41,0xC4,0x74,0x01,0xF0,0xA3,
+
+	0xE4,0xF0,0xA3,0x74,0x07,0xF0,0xA3,0x74,
+
+	0x43,0xF0,0xA3,0x74,0x44,0xF0,0xA3,0xE4,
+
+	0xF0,0xA3,0x04,0xF0,0xE4,0xFB,0x7D,0xC0,
+
+	0x7F,0x02,0x12,0x57,0x94,0x90,0x43,0x4E,
+
+	0xE0,0x90,0xF6,0xA9,0xF0,0x02,0x64,0x6D,
+
+	0x90,0xF6,0x41,0xE0,0x24,0xDE,0x70,0x03,
+
+	0x02,0x63,0xEA,0x14,0x60,0x0E,0x24,0xFB,
+
+	0x70,0x03,0x02,0x63,0xEA,0x24,0x07,0x60,
+
+	0x03,0x02,0x64,0x6D,0x90,0xF0,0x02,0x74,
+
+	0x52,0xF0,0x90,0x41,0xC4,0x74,0x01,0xF0,
+
+	0xA3,0xE4,0xF0,0xA3,0x74,0x05,0xF0,0xA3,
+
+	0x74,0x43,0xF0,0xA3,0x74,0x44,0xF0,0xA3,
+
+	0xE4,0xF0,0xA3,0x04,0xF0,0xFB,0x7D,0xC0,
+
+	0x7F,0x02,0x12,0x57,0x94,0x90,0xF6,0xA8,
+
+	0xE0,0xB4,0x01,0x0C,0x90,0x43,0x47,0x74,
+
+	0x01,0xF0,0x90,0x43,0x4F,0xF0,0x80,0x12,
+
+	0x90,0xF6,0xA8,0xE0,0xB4,0x02,0x0B,0x90,
+
+	0x43,0x47,0x74,0x02,0xF0,0x90,0x43,0x4F,
+
+	0xE4,0xF0,0x90,0x43,0x44,0xE0,0x54,0xCF,
+
+	0xF0,0xE0,0xFF,0x90,0x43,0x47,0xE0,0xFE,
+
+	0xC4,0x54,0xF0,0xFE,0xEF,0x4E,0x90,0x43,
+
+	0x44,0xF0,0x90,0x41,0xC4,0x74,0x01,0xF0,
+
+	0xA3,0xE4,0xF0,0xA3,0x74,0x05,0xF0,0xA3,
+
+	0x74,0x43,0xF0,0xA3,0x74,0x44,0xF0,0xA3,
+
+	0xE4,0xF0,0xA3,0x04,0xF0,0xE4,0xFB,0x7D,
+
+	0xC0,0x7F,0x02,0x12,0x57,0x94,0x90,0x43,
+
+	0x47,0xE0,0x90,0xF6,0xA9,0xF0,0x02,0x64,
+
+	0x6D,0x90,0xF6,0xA8,0xE0,0xB4,0x01,0x0B,
+
+	0x90,0xD8,0xCF,0xE0,0x54,0xFE,0x44,0x01,
+
+	0xF0,0x80,0x71,0x90,0xF6,0xA8,0xE0,0x64,
+
+	0x02,0x70,0x69,0x90,0xD8,0xCF,0xE0,0x54,
+
+	0xFE,0xF0,0x80,0x60,0x90,0x43,0x4C,0x74,
+
+	0xC0,0xF0,0xA3,0x74,0x16,0xF0,0x90,0x41,
+
+	0xC4,0x74,0x01,0xF0,0xA3,0xE4,0xF0,0xA3,
+
+	0x74,0x36,0xF0,0xA3,0x74,0x43,0xF0,0xA3,
+
+	0x74,0x4C,0xF0,0xA3,0xE4,0xF0,0xA3,0x74,
+
+	0x02,0xF0,0xE4,0xFB,0x7D,0xC0,0x7F,0x02,
+
+	0x12,0x57,0x94,0x80,0x2F,0x90,0x43,0x4C,
+
+	0x74,0xC0,0xF0,0xA3,0x74,0x13,0xF0,0x90,
+
+	0x41,0xC4,0x74,0x01,0xF0,0xA3,0xE4,0xF0,
+
+	0xA3,0x74,0x36,0xF0,0xA3,0x74,0x43,0xF0,
+
+	0xA3,0x74,0x4C,0xF0,0xA3,0xE4,0xF0,0xA3,
+
+	0x74,0x02,0xF0,0xE4,0xFB,0x7D,0xC0,0x7F,
+
+	0x02,0x12,0x57,0x94,0x53,0x91,0xDF,0x90,
+
+	0xF6,0xDF,0xE0,0x54,0xFE,0xF0,0xD0,0x07,
+
+	0xD0,0x06,0xD0,0x05,0xD0,0x04,0xD0,0x03,
+
+	0xD0,0x02,0xD0,0x01,0xD0,0x00,0xD0,0xD0,
+
+	0xD0,0x86,0xD0,0x84,0xD0,0x85,0xD0,0x82,
+
+	0xD0,0x83,0xD0,0xF0,0xD0,0xE0,0x32,0x44,
+
+	0x43,0x50,0x9E,0xBE,0xDE,0xFE,0x00,0x78,
+
+	0x64,0x7C,0x43,0x7D,0x01,0x7B,0xFF,0x7A,
+
+	0x7F,0x79,0xC3,0x7E,0x01,0x7F,0x03,0x12,
+
+	0x7F,0x9D,0x78,0x6A,0x7C,0x44,0x7D,0x01,
+
+	0x7B,0x01,0x7A,0x43,0x79,0x89,0x7E,0x00,
+
+	0x7F,0x09,0x12,0x7F,0x9D,0x78,0x73,0x7C,
+
+	0x44,0x7D,0x01,0x7B,0xFF,0x7A,0x80,0x79,
+
+	0xC6,0x7E,0x00,0x7F,0x41,0x12,0x7F,0x9D,
+
+	0x22,0x90,0x44,0xB9,0x74,0xAF,0xF0,0xA3,
+
+	0xEF,0xF0,0xA3,0x74,0x22,0xF0,0x7A,0x44,
+
+	0x79,0xB9,0x12,0x7E,0xDB,0x22,0x90,0x44,
+
+	0xB9,0x74,0x8F,0xF0,0xA3,0xEF,0xF0,0xA3,
+
+	0x74,0x22,0xF0,0xAF,0x05,0x7C,0x44,0x7D,
+
+	0xB9,0x90,0x44,0xB9,0x12,0x7E,0xDF,0x22,
+
+	0xE4,0x90,0x44,0xBE,0xF0,0x90,0x44,0xB8,
+
+	0xE0,0x60,0x0D,0x90,0xDD,0xA8,0xE0,0x30,
+
+	0xE0,0x06,0x12,0x68,0x77,0x02,0x67,0x38,
+
+	0x90,0xDF,0x82,0xE0,0x20,0xE1,0x06,0x12,
+
+	0x67,0xD1,0x02,0x67,0x38,0x90,0x44,0xB8,
+
+	0xE0,0x70,0x09,0x90,0x44,0xBF,0xE0,0x04,
+
+	0xF0,0x02,0x67,0x38,0x90,0xDD,0xA8,0xE0,
+
+	0x30,0xE0,0x06,0x12,0x68,0x77,0x02,0x67,
+
+	0x38,0x90,0xDD,0x1B,0xE0,0x30,0xE1,0x12,
+
+	0x90,0xDD,0x1D,0x74,0xFF,0xF0,0x90,0xDD,
+
+	0x1B,0x74,0x02,0xF0,0x12,0x68,0x20,0x02,
+
+	0x67,0x38,0x90,0x45,0x33,0xE0,0x64,0x01,
+
+	0x70,0x29,0x90,0xDD,0x1B,0xE0,0x30,0xE0,
+
+	0x22,0x74,0x01,0xF0,0xE4,0x90,0x44,0xBD,
+
+	0xF0,0x90,0xDD,0x1B,0xE0,0x30,0xE0,0x0D,
+
+	0x74,0x01,0xF0,0x90,0x44,0xBD,0xE0,0x04,
+
+	0xF0,0xE0,0xB4,0x02,0xEC,0x12,0x68,0x3F,
+
+	0x02,0x67,0x38,0x90,0xDD,0x1B,0xE0,0x30,
+
+	0xE2,0x28,0x90,0xDD,0x14,0xE0,0x44,0x01,
+
+	0xF0,0x12,0x69,0x63,0x12,0x60,0x1F,0x90,
+
+	0x44,0xBC,0xEF,0xF0,0x70,0x03,0x02,0x67,
+
+	0x38,0x90,0xDD,0x14,0xE0,0x54,0xFE,0xF0,
+
+	0x90,0xDD,0x12,0xE0,0x44,0x01,0xF0,0x02,
+
+	0x67,0x38,0x90,0xDD,0x19,0xE0,0x30,0xE0,
+
+	0x42,0x90,0xDD,0x14,0xE0,0x44,0x01,0xF0,
+
+	0x90,0xDD,0x19,0x74,0x01,0xF0,0x90,0xDD,
+
+	0x13,0xE0,0x44,0x01,0xF0,0x90,0x44,0xB6,
+
+	0xE0,0x64,0x01,0x60,0x03,0x02,0x67,0x38,
+
+	0x90,0xDD,0x00,0xC0,0x83,0xC0,0x82,0xE0,
+
+	0xFF,0x90,0x43,0x59,0xE0,0xFE,0x33,0x33,
+
+	0x33,0x54,0xF8,0xFE,0xEF,0x4E,0xD0,0x82,
+
+	0xD0,0x83,0xF0,0xE4,0x90,0x44,0xB6,0xF0,
+
+	0x02,0x67,0x38,0x90,0xDD,0x18,0xE0,0x30,
+
+	0xE0,0x31,0x90,0xDD,0x14,0xE0,0x30,0xE0,
+
+	0x2A,0x90,0xDD,0x14,0xE0,0x54,0xFE,0xF0,
+
+	0x12,0x60,0x3A,0x90,0x44,0xBC,0xEF,0xF0,
+
+	0x60,0x09,0x90,0xDD,0x12,0xE0,0x44,0x01,
+
+	0xF0,0x80,0x07,0x90,0xDD,0x13,0xE0,0x54,
+
+	0xFE,0xF0,0x90,0xDD,0x18,0x74,0x01,0xF0,
+
+	0x02,0x67,0x38,0x90,0xDD,0x19,0xE0,0x30,
+
+	0xE1,0x10,0x90,0xDD,0x19,0x74,0x02,0xF0,
+
+	0x90,0xDD,0x13,0xE0,0x44,0x02,0xF0,0x02,
+
+	0x67,0x38,0x90,0xDD,0x18,0xE0,0x30,0xE1,
+
+	0x16,0x90,0xDD,0x84,0x74,0x40,0xF0,0x90,
+
+	0xDD,0x13,0xE0,0x54,0xFD,0xF0,0x90,0xDD,
+
+	0x18,0x74,0x02,0xF0,0x02,0x67,0x38,0x90,
+
+	0xDD,0x19,0xE0,0x30,0xE4,0x6A,0x90,0xDD,
+
+	0x19,0x74,0x10,0xF0,0x90,0x43,0x43,0xE0,
+
+	0x64,0x01,0x60,0x03,0x02,0x67,0x38,0x90,
+
+	0x44,0xDE,0xE0,0xFF,0xB4,0x01,0x31,0xE4,
+
+	0x90,0x44,0xBD,0xF0,0x90,0x44,0xBD,0xE0,
+
+	0xFE,0xC3,0x94,0x08,0x50,0x14,0x74,0x80,
+
+	0x2E,0xF5,0x82,0xE4,0x34,0xDE,0xF5,0x83,
+
+	0xE4,0xF0,0x90,0x44,0xBD,0xE0,0x04,0xF0,
+
+	0x80,0xE2,0x90,0xDD,0x87,0x74,0x08,0xF0,
+
+	0x90,0x44,0xDE,0x74,0x02,0xF0,0x80,0x6F,
+
+	0xEF,0x64,0x02,0x70,0x6A,0x90,0x44,0xDE,
+
+	0xF0,0x90,0xDD,0x13,0xE0,0x44,0x10,0xF0,
+
+	0x90,0x41,0x81,0xE0,0xFF,0x64,0x01,0x60,
+
+	0x56,0x90,0x43,0x43,0xEF,0xF0,0x80,0x4F,
+
+	0x90,0xDD,0x19,0xE0,0x30,0xE3,0x18,0x90,
+
+	0xDD,0x13,0xE0,0x44,0x08,0xF0,0x90,0xDD,
+
+	0x19,0x74,0x08,0xF0,0x12,0x60,0x44,0x90,
+
+	0x44,0xB7,0x74,0x01,0xF0,0x80,0x30,0x90,
+
+	0xDD,0x14,0xE0,0x54,0x08,0xFF,0x13,0x13,
+
+	0x13,0x54,0x1F,0x60,0x1C,0x90,0xDD,0x18,
+
+	0xE0,0x30,0xE3,0x15,0x90,0xDD,0x84,0x74,
+
+	0x40,0xF0,0x90,0xDD,0x13,0xE0,0x54,0xF7,
+
+	0xF0,0x90,0xDD,0x18,0x74,0x08,0xF0,0x80,
+
+	0x06,0x90,0x44,0xC0,0xE0,0x04,0xF0,0xC2,
+
+	0xDC,0x22,0xC0,0xE0,0xC0,0xF0,0xC0,0x83,
+
+	0xC0,0x82,0xC0,0x85,0xC0,0x84,0xC0,0x86,
+
+	0x75,0x86,0x00,0xC0,0xD0,0x75,0xD0,0x00,
+
+	0xC0,0x00,0xC0,0x01,0xC0,0x02,0xC0,0x03,
+
+	0xC0,0x04,0xC0,0x05,0xC0,0x06,0xC0,0x07,
+
+	0x12,0x65,0x09,0xD0,0x07,0xD0,0x06,0xD0,
+
+	0x05,0xD0,0x04,0xD0,0x03,0xD0,0x02,0xD0,
+
+	0x01,0xD0,0x00,0xD0,0xD0,0xD0,0x86,0xD0,
+
+	0x84,0xD0,0x85,0xD0,0x82,0xD0,0x83,0xD0,
+
+	0xF0,0xD0,0xE0,0x32,0xC0,0xE0,0xC0,0xF0,
+
+	0xC0,0x83,0xC0,0x82,0xC0,0x85,0xC0,0x84,
+
+	0xC0,0x86,0x75,0x86,0x00,0xC0,0xD0,0x75,
+
+	0xD0,0x00,0xC0,0x00,0xC0,0x01,0xC0,0x02,
+
+	0xC0,0x03,0xC0,0x04,0xC0,0x05,0xC0,0x06,
+
+	0xC0,0x07,0xC2,0xDB,0x12,0x65,0x09,0xD0,
+
+	0x07,0xD0,0x06,0xD0,0x05,0xD0,0x04,0xD0,
+
+	0x03,0xD0,0x02,0xD0,0x01,0xD0,0x00,0xD0,
+
+	0xD0,0xD0,0x86,0xD0,0x84,0xD0,0x85,0xD0,
+
+	0x82,0xD0,0x83,0xD0,0xF0,0xD0,0xE0,0x32,
+
+	0x90,0x45,0x18,0xE0,0x64,0x01,0x60,0x05,
+
+	0xE0,0x64,0x05,0x70,0x41,0x90,0x45,0x34,
+
+	0xE0,0x70,0x05,0x12,0x6E,0x3F,0x80,0x1B,
+
+	0x90,0x45,0x34,0xE0,0xB4,0x01,0x05,0x12,
+
+	0x6F,0xCD,0x80,0x0F,0x90,0x45,0x34,0xE0,
+
+	0x64,0x02,0x60,0x04,0xE0,0xB4,0xFF,0x03,
+
+	0x12,0x79,0x40,0x90,0x43,0x43,0xE0,0xB4,
+
+	0x01,0x14,0x90,0x44,0xDE,0xE0,0xB4,0x01,
+
+	0x0D,0x90,0xDD,0x13,0xE0,0x54,0xEF,0xF0,
+
+	0x90,0xDD,0x87,0x74,0x08,0xF0,0x22,0x12,
+
+	0x69,0x97,0x90,0xDD,0x01,0xE0,0x54,0x04,
+
+	0x90,0x44,0xC5,0xF0,0x90,0x46,0x00,0xE0,
+
+	0x60,0x03,0x12,0x75,0xD6,0x12,0x75,0xD5,
+
+	0xE4,0x90,0x44,0xDE,0xF0,0x22,0x90,0xD8,
+
+	0x06,0xE0,0x54,0xFE,0x44,0x01,0xF0,0x22,
+
+	0x12,0x69,0x97,0x90,0x45,0x11,0xE0,0x30,
+
+	0xE6,0x09,0x90,0xDD,0xA7,0xE0,0x44,0x01,
+
+	0xF0,0x80,0x07,0x90,0xDD,0x00,0xE0,0x44,
+
+	0x80,0xF0,0xD2,0xAF,0xD2,0xDD,0x22,0x90,
+
+	0x45,0x12,0xE0,0x30,0xE0,0x07,0x90,0xDD,
+
+	0xA8,0xE0,0x30,0xE2,0xF9,0x22,0x90,0xDD,
+
+	0xA7,0xE0,0x30,0xE1,0x06,0xE0,0x54,0xFD,
+
+	0xF0,0x80,0x07,0x90,0xDD,0xA7,0xE0,0x44,
+
+	0x02,0xF0,0x90,0xDD,0xA8,0xE0,0x30,0xE1,
+
+	0x08,0x90,0xDD,0x00,0xE0,0x44,0x80,0xF0,
+
+	0x22,0x90,0xDD,0x00,0xE0,0x54,0x7F,0xF0,
+
+	0x22,0xE4,0x90,0x44,0x69,0xF0,0x12,0x5C,
+
+	0x62,0x90,0x44,0xC1,0xEF,0xF0,0x60,0x25,
+
+	0xE0,0xB4,0x05,0x03,0x7F,0x05,0x22,0x12,
+
+	0x5D,0xCF,0x90,0x44,0xC1,0xEF,0xF0,0x60,
+
+	0x14,0xE0,0xB4,0x05,0x03,0x7F,0x05,0x22,
+
+	0x12,0x5F,0x20,0x90,0x44,0xC1,0xEF,0xF0,
+
+	0x60,0x03,0xE0,0xFF,0x22,0x7F,0x00,0x22,
+
+	0x90,0x43,0x5B,0xE0,0xD3,0x94,0x00,0x40,
+
+	0x06,0x90,0x44,0x68,0xEF,0xF0,0x22,0x90,
+
+	0x43,0x5A,0xE0,0xFE,0xEF,0xC3,0x9E,0x50,
+
+	0x06,0x90,0x44,0x68,0xEF,0xF0,0x22,0x90,
+
+	0x44,0x68,0xEE,0xF0,0x22,0x90,0x44,0xC2,
+
+	0xEB,0xF0,0xA3,0xEA,0xF0,0xA3,0xE9,0xF0,
+
+	0xE4,0xFF,0x90,0x44,0x68,0xE0,0xD3,0x94,
+
+	0x00,0x40,0x04,0x7E,0x01,0x80,0x02,0x7E,
+
+	0x00,0xEF,0xC3,0x94,0x40,0x50,0x04,0x7D,
+
+	0x01,0x80,0x02,0x7D,0x00,0xED,0x5E,0x60,
+
+	0x33,0x90,0x44,0xC2,0xE0,0xFB,0xA3,0xE0,
+
+	0xFA,0xA3,0xE0,0xF9,0x90,0x44,0x69,0xE0,
+
+	0xF5,0x82,0x75,0x83,0x00,0x12,0x7C,0xD8,
+
+	0xFE,0x74,0x00,0x2F,0xF5,0x82,0xE4,0x34,
+
+	0xDE,0xF5,0x83,0xEE,0xF0,0x0F,0x90,0x44,
+
+	0x68,0xE0,0x14,0xF0,0x90,0x44,0x69,0xE0,
+
+	0x04,0xF0,0x80,0xAE,0x90,0xDD,0x85,0xEF,
+
+	0xF0,0x22,0x90,0xDD,0x13,0xE0,0x44,0x01,
+
+	0xF0,0x90,0xDD,0x1B,0x74,0x04,0xF0,0xE4,
+
+	0xFF,0x74,0x00,0x2F,0xF5,0x82,0xE4,0x34,
+
+	0xDF,0xF5,0x83,0xE0,0xFE,0x74,0x54,0x2F,
+
+	0xF5,0x82,0xE4,0x34,0x43,0xF5,0x83,0xEE,
+
+	0xF0,0x0F,0xEF,0xB4,0x08,0xE3,0x90,0xDD,
+
+	0x1B,0xE0,0x20,0xE2,0xD4,0x22,0x90,0xDD,
+
+	0x13,0x74,0x7B,0xF0,0x90,0xDD,0x80,0x74,
+
+	0xC0,0xF0,0xA3,0x74,0x00,0xF0,0xA3,0x74,
+
+	0x40,0xF0,0xA3,0x74,0x80,0xF0,0x12,0x5C,
+
+	0x55,0xE4,0x90,0x43,0x62,0xF0,0x90,0x43,
+
+	0x63,0xF0,0x90,0xDD,0x14,0x74,0x0B,0xF0,
+
+	0x90,0xDD,0x17,0x74,0x06,0xF0,0x90,0x45,
+
+	0x33,0xE0,0xB4,0x01,0x07,0x90,0xDD,0x17,
+
+	0xE0,0x44,0x01,0xF0,0x90,0xDD,0x15,0x74,
+
+	0x0B,0xF0,0x90,0xDD,0x0C,0x74,0x80,0xF0,
+
+	0x90,0xDD,0x8E,0xE4,0xF0,0xA3,0x74,0x03,
+
+	0xF0,0x90,0xDD,0x0E,0xE4,0xF0,0xA3,0x04,
+
+	0xF0,0x90,0xDD,0x13,0xE0,0x54,0x7F,0xF0,
+
+	0x90,0xDD,0x20,0xE0,0x54,0xFC,0x44,0x03,
+
+	0xF0,0x90,0xDD,0x11,0x74,0x8F,0xF0,0x90,
+
+	0x45,0x18,0xE0,0x64,0x01,0x70,0x27,0xC3,
+
+	0x74,0x03,0x94,0x89,0x90,0x43,0x82,0xF0,
+
+	0x90,0x44,0x6C,0xF0,0x90,0x43,0x84,0x74,
+
+	0x02,0xF0,0x90,0x44,0x6E,0xF0,0x90,0xDD,
+
+	0x15,0xE0,0x44,0x10,0xF0,0x90,0xDD,0x11,
+
+	0xE0,0x44,0x10,0xF0,0x80,0x17,0xC3,0x74,
+
+	0xEA,0x94,0x89,0x90,0x43,0x82,0xF0,0x90,
+
+	0x44,0x6C,0xF0,0x90,0x43,0x84,0x74,0x01,
+
+	0xF0,0x90,0x44,0x6E,0xF0,0x90,0x46,0x00,
+
+	0xE0,0x60,0x03,0x12,0x75,0xD6,0x90,0xDD,
+
+	0x0C,0x74,0x80,0xF0,0x90,0xDD,0x89,0x74,
+
+	0x03,0xF0,0x90,0xDD,0x88,0x74,0xDB,0xF0,
+
+	0x90,0xDD,0x13,0xE0,0x54,0xDF,0xF0,0x90,
+
+	0xF4,0x1A,0xE0,0x54,0xFE,0x44,0x01,0xF0,
+
+	0x22,0x90,0x43,0xE0,0xEE,0xF0,0xA3,0xEF,
+
+	0xF0,0x90,0x43,0xD9,0xEE,0xF0,0xA3,0xEF,
+
+	0xF0,0x90,0x43,0xD2,0xEE,0xF0,0xA3,0xEF,
+
+	0xF0,0x90,0x43,0xCB,0xEE,0xF0,0xA3,0xEF,
+
+	0xF0,0x90,0x43,0xB4,0xEE,0xF0,0xA3,0xEF,
+
+	0xF0,0x90,0x43,0xAD,0xEE,0xF0,0xA3,0xEF,
+
+	0xF0,0x90,0x43,0xA6,0xEE,0xF0,0xA3,0xEF,
+
+	0xF0,0x90,0x43,0x9F,0xEE,0xF0,0xA3,0xEF,
+
+	0xF0,0x22,0x90,0x43,0xE7,0xEE,0xF0,0xA3,
+
+	0xEF,0xF0,0x22,0x8F,0x82,0x8E,0x83,0xE4,
+
+	0xFF,0xFE,0xED,0x4C,0x60,0x0F,0xED,0x60,
+
+	0x01,0x0C,0xE0,0xA3,0x2F,0xFF,0xE4,0x3E,
+
+	0xFE,0xDD,0xF7,0xDC,0xF5,0x22,0x80,0x02,
+
+	0x80,0xFE,0x90,0xF1,0x03,0x74,0x25,0xF0,
+
+	0x22,0x90,0x44,0xC6,0xEF,0xF0,0xA3,0xED,
+
+	0xF0,0xA3,0xEB,0xF0,0xA3,0xE0,0xFE,0xFD,
+
+	0x7C,0x00,0x90,0x44,0xCC,0xE0,0xFA,0xA3,
+
+	0xE0,0xFB,0x2D,0xFD,0xEC,0x3A,0xFC,0xD3,
+
+	0xED,0x94,0x00,0xEC,0x94,0x01,0x40,0x03,
+
+	0x7F,0x01,0x22,0xE4,0xB5,0x03,0x08,0xEA,
+
+	0xB4,0x01,0x04,0x7F,0x08,0x80,0x0B,0xEE,
+
+	0x54,0x07,0xFF,0xC3,0x74,0x08,0x9F,0x54,
+
+	0x07,0xFF,0x90,0x44,0xCE,0xEF,0xF0,0xC3,
+
+	0xEB,0x9F,0xEA,0x94,0x00,0x50,0x06,0x90,
+
+	0x44,0xCD,0xE0,0xA3,0xF0,0x90,0x44,0xCD,
+
+	0xE0,0xFF,0xA3,0xE0,0xFE,0xC3,0xEF,0x9E,
+
+	0x54,0x07,0xFE,0x90,0x44,0xD0,0xF0,0x90,
+
+	0x44,0xCE,0xE0,0xFD,0xC3,0xEF,0x9D,0xC3,
+
+	0x9E,0xA3,0xF0,0x90,0x44,0xCE,0xE0,0x90,
+
+	0x44,0xD1,0xF0,0xA3,0x74,0x08,0xF0,0x90,
+
+	0x44,0xD0,0xE0,0x90,0x44,0xD3,0xF0,0xE4,
+
+	0xA3,0xF0,0x90,0x44,0xD4,0xE0,0xFB,0x24,
+
+	0xCE,0xF5,0x82,0xE4,0x34,0x44,0xF5,0x83,
+
+	0xE0,0x70,0x03,0x02,0x6C,0x90,0x90,0x44,
+
+	0xC9,0xE0,0x90,0xF0,0x01,0xF0,0x90,0x44,
+
+	0xC8,0xE0,0x70,0x4E,0x7E,0xF0,0x7F,0x02,
+
+	0x90,0x44,0xCA,0xE0,0xFC,0xA3,0xE0,0xFD,
+
+	0x74,0xD1,0x2B,0xF5,0x82,0xE4,0x34,0x44,
+
+	0xF5,0x83,0xE0,0xFB,0x12,0x56,0x9C,0x90,
+
+	0x44,0xC6,0xE0,0xFF,0xA3,0xE0,0xFD,0x90,
+
+	0x44,0xD4,0xE0,0x24,0xD1,0xF5,0x82,0xE4,
+
+	0x34,0x44,0xF5,0x83,0xE0,0x04,0xFB,0x90,
+
+	0x41,0xBD,0x74,0x01,0xF0,0x12,0x54,0xB6,
+
+	0xEF,0x60,0x03,0x7F,0x02,0x22,0x7F,0x35,
+
+	0x7E,0x82,0x12,0x56,0xC5,0x20,0x8D,0x60,
+
+	0x80,0xFB,0x90,0x44,0xC6,0xE0,0xFF,0xA3,
+
+	0xE0,0xFD,0x90,0x41,0xBD,0x74,0x01,0xF0,
+
+	0xFB,0x12,0x54,0xB6,0xEF,0x60,0x03,0x7F,
+
+	0x02,0x22,0x90,0x44,0xC6,0xE0,0xFF,0xA3,
+
+	0xE0,0x44,0x01,0xFD,0x90,0x44,0xD4,0xE0,
+
+	0x24,0xD1,0xF5,0x82,0xE4,0x34,0x44,0xF5,
+
+	0x83,0xE0,0xFB,0x90,0x41,0xBD,0x74,0x01,
+
+	0xF0,0x12,0x54,0xB6,0xEF,0x60,0x03,0x7F,
+
+	0x02,0x22,0x90,0x44,0xCA,0xE0,0xFE,0xA3,
+
+	0xE0,0xFF,0x7C,0xF0,0x7D,0x00,0x90,0x44,
+
+	0xD4,0xE0,0x24,0xD1,0xF5,0x82,0xE4,0x34,
+
+	0x44,0xF5,0x83,0xE0,0xFB,0x12,0x56,0x9C,
+
+	0x90,0x44,0xD4,0xE0,0xFF,0x24,0xD1,0xF5,
+
+	0x82,0xE4,0x34,0x44,0xF5,0x83,0xE0,0xFE,
+
+	0x90,0x44,0xC9,0xE0,0x2E,0xF0,0xEE,0xFD,
+
+	0x90,0x44,0xCB,0xE0,0x2D,0xF0,0x90,0x44,
+
+	0xCA,0xE0,0x34,0x00,0xF0,0x74,0xCE,0x2F,
+
+	0xF5,0x82,0xE4,0x34,0x44,0xF5,0x83,0xC0,
+
+	0x83,0xC0,0x82,0xE0,0xFF,0x90,0x44,0xD4,
+
+	0xE0,0x24,0xD1,0xF5,0x82,0xE4,0x34,0x44,
+
+	0xF5,0x83,0xE0,0xFE,0xC3,0xEF,0x9E,0xD0,
+
+	0x82,0xD0,0x83,0xF0,0x02,0x6B,0x73,0x90,
+
+	0x44,0xD4,0xE0,0x04,0xF0,0xE0,0xC3,0x94,
+
+	0x03,0x50,0x03,0x02,0x6B,0x73,0x7F,0x00,
+
+	0x22,0x90,0x44,0xD5,0xEF,0xF0,0xE4,0x90,
+
+	0x44,0xD6,0xF0,0x90,0x44,0xD6,0xE0,0xFE,
+
+	0xC3,0x94,0x10,0x50,0x1F,0x90,0x44,0xD5,
+
+	0xE0,0xFF,0xEE,0x44,0xA0,0xFD,0x90,0x41,
+
+	0xBD,0x74,0x01,0xF0,0xFB,0x12,0x54,0xB6,
+
+	0xEF,0x60,0x09,0x90,0x44,0xD6,0xE0,0x24,
+
+	0x02,0xF0,0x80,0xD7,0x90,0x44,0xD6,0xE0,
+
+	0xFF,0xC3,0x94,0x10,0x50,0x05,0xEF,0x44,
+
+	0xA0,0xFF,0x22,0x7F,0x01,0x22,0x90,0xDF,
+
+	0x82,0xE0,0x54,0xDF,0xF0,0xE4,0x90,0x44,
+
+	0xDE,0xF0,0x90,0x44,0xDD,0xF0,0x90,0x43,
+
+	0x43,0x04,0xF0,0x90,0x41,0x81,0xF0,0x90,
+
+	0x41,0xE1,0x74,0x32,0xF0,0x90,0x41,0xE3,
+
+	0x74,0x14,0xF0,0x90,0x41,0xE2,0x74,0x3E,
+
+	0xF0,0xE4,0x90,0x44,0xE0,0xF0,0x90,0x44,
+
+	0xEB,0xF0,0x90,0x44,0xEF,0xF0,0x90,0x44,
+
+	0xF1,0xF0,0xA3,0xF0,0x90,0x44,0xE1,0xF0,
+
+	0xA3,0xF0,0x90,0x44,0xEC,0xF0,0xA3,0xF0,
+
+	0x90,0x44,0xF7,0xF0,0x90,0xDF,0x80,0x74,
+
+	0x28,0xF0,0xA3,0x74,0x04,0xF0,0x75,0xCA,
+
+	0x01,0xE4,0xF5,0xCB,0xF5,0xC8,0xD2,0xAD,
+
+	0xD2,0xCA,0x22,0x90,0xDF,0x92,0x74,0x50,
+
+	0xF0,0x12,0x6C,0xE7,0x22,0x90,0x41,0xDF,
+
+	0x74,0x7F,0xF0,0xA3,0x74,0xFF,0xF0,0x90,
+
+	0xDF,0x90,0x74,0x50,0xF0,0xE4,0xA3,0xF0,
+
+	0xA3,0x74,0x96,0xF0,0xE4,0xA3,0xF0,0xA3,
+
+	0x74,0x2C,0xF0,0xA3,0x74,0x01,0xF0,0xA3,
+
+	0x74,0x90,0xF0,0xA3,0x74,0x01,0xF0,0xA3,
+
+	0x74,0xC2,0xF0,0xA3,0x74,0x01,0xF0,0xA3,
+
+	0x74,0x26,0xF0,0xA3,0x74,0x02,0xF0,0xE4,
+
+	0xA3,0xF0,0xA3,0x74,0x10,0xF0,0xE4,0xA3,
+
+	0xF0,0xA3,0x74,0x20,0xF0,0xE4,0xA3,0xF0,
+
+	0xA3,0x74,0x40,0xF0,0x12,0x6C,0xE7,0x22,
+
+	0xC0,0xE0,0xC0,0x83,0xC0,0x82,0xC0,0x85,
+
+	0xC0,0x84,0xC0,0x86,0x75,0x86,0x00,0xC0,
+
+	0xD0,0x75,0xD0,0x00,0xC0,0x07,0xC2,0xCF,
+
+	0x90,0x44,0xE1,0xE0,0x60,0x1A,0xA3,0xE0,
+
+	0x04,0xF0,0x90,0x41,0xE3,0xE0,0xFF,0x90,
+
+	0x44,0xE2,0xE0,0xD3,0x9F,0x40,0x10,0x90,
+
+	0x44,0xE1,0xE4,0xF0,0xA3,0xF0,0x80,0x07,
+
+	0x90,0x44,0xE1,0xE4,0xF0,0xA3,0xF0,0x90,
+
+	0x44,0xF1,0xE0,0x60,0x19,0xA3,0xE0,0x04,
+
+	0xF0,0x90,0x41,0xE2,0xE0,0xFF,0x90,0x44,
+
+	0xF2,0xE0,0xD3,0x9F,0x40,0x11,0xE4,0xF0,
+
+	0x90,0x44,0xF1,0xF0,0x80,0x09,0x90,0x44,
+
+	0xF2,0xE4,0xF0,0x90,0x44,0xF1,0xF0,0xD0,
+
+	0x07,0xD0,0xD0,0xD0,0x86,0xD0,0x84,0xD0,
+
+	0x85,0xD0,0x82,0xD0,0x83,0xD0,0xE0,0x32,
+
+	0x90,0xDF,0x82,0xE0,0x30,0xE0,0x14,0x74,
+
+	0x20,0xF0,0xE0,0x90,0x44,0xD7,0xF0,0xE4,
+
+	0x90,0xDF,0x82,0xF0,0x90,0x44,0xE0,0xF0,
+
+	0x7F,0x01,0x22,0x7F,0x00,0x22,0x12,0x6E,
+
+	0x21,0xEF,0x60,0x03,0x02,0x6F,0xCC,0x90,
+
+	0xDF,0x82,0xE0,0x30,0xE1,0x03,0x02,0x6F,
+
+	0xCC,0x90,0x44,0xD9,0xE5,0xE4,0xF0,0x90,
+
+	0x44,0xE0,0xE0,0x14,0x60,0x68,0x14,0x70,
+
+	0x03,0x02,0x6F,0x51,0x24,0x02,0x60,0x03,
+
+	0x02,0x6F,0xC2,0x90,0x44,0xD9,0xE0,0x64,
+
+	0xBC,0x70,0x3B,0x90,0x44,0xEB,0xF0,0x90,
+
+	0x44,0xED,0xF0,0x90,0x44,0xEC,0xF0,0x90,
+
+	0x44,0xEF,0xF0,0x90,0x44,0xD8,0xF0,0x90,
+
+	0x44,0xD8,0xE0,0xFF,0xC3,0x94,0x08,0x50,
+
+	0x14,0x74,0xE3,0x2F,0xF5,0x82,0xE4,0x34,
+
+	0x44,0xF5,0x83,0xE4,0xF0,0x90,0x44,0xD8,
+
+	0xE0,0x04,0xF0,0x80,0xE2,0x90,0x44,0xE0,
+
+	0x74,0x01,0xF0,0x02,0x6F,0xC2,0x90,0x44,
+
+	0xD9,0xE0,0xB4,0xAC,0x09,0x90,0x44,0xE0,
+
+	0x74,0x02,0xF0,0x02,0x6F,0xC2,0xE4,0x90,
+
+	0x44,0xE0,0xF0,0x02,0x6F,0xC2,0x90,0x44,
+
+	0xD9,0xE0,0xC3,0x94,0xE8,0x40,0x17,0x12,
+
+	0x72,0x67,0xE4,0x90,0x44,0xE0,0xF0,0x90,
+
+	0x44,0xED,0xF0,0x90,0x44,0xEC,0xF0,0x90,
+
+	0x44,0xEB,0xF0,0x02,0x6F,0xC2,0x90,0x44,
+
+	0xD9,0xE0,0xB4,0x98,0x1F,0x90,0x44,0xEC,
+
+	0xE0,0xFF,0x74,0x01,0xA8,0x07,0x08,0x80,
+
+	0x02,0xC3,0x33,0xD8,0xFC,0xFF,0x90,0x44,
+
+	0xED,0xE0,0x2F,0xF0,0x90,0x44,0xEC,0xE0,
+
+	0x04,0xF0,0x80,0x1A,0x90,0x44,0xD9,0xE0,
+
+	0xB4,0x88,0x08,0x90,0x44,0xEC,0xE0,0x04,
+
+	0xF0,0x80,0x0B,0xE4,0x90,0x44,0xE0,0xF0,
+
+	0x90,0x44,0xEC,0xE0,0x04,0xF0,0x90,0x44,
+
+	0xEC,0xE0,0x64,0x08,0x60,0x03,0x02,0x6F,
+
+	0xC2,0xA3,0xE0,0xFF,0x90,0x44,0xEB,0xE0,
+
+	0xFE,0x04,0xF0,0x74,0xE3,0x2E,0xF5,0x82,
+
+	0xE4,0x34,0x44,0xF5,0x83,0xEF,0xF0,0xE4,
+
+	0x90,0x44,0xEC,0xF0,0xA3,0xF0,0x80,0x71,
+
+	0x90,0x44,0xD9,0xE0,0xC3,0x94,0xF8,0x40,
+
+	0x68,0x90,0x44,0xEF,0xE0,0x04,0xF0,0x90,
+
+	0x44,0xDE,0xE0,0x70,0x41,0x90,0x41,0xE3,
+
+	0xE0,0x75,0xF0,0x05,0x84,0xFF,0x90,0x44,
+
+	0xEF,0xE0,0xB5,0x07,0x31,0xE4,0x90,0x44,
+
+	0xD8,0xF0,0x90,0x44,0xD8,0xE0,0xFF,0x24,
+
+	0xE3,0xF5,0x82,0xE4,0x34,0x44,0xF5,0x83,
+
+	0xE0,0xFE,0x74,0x80,0x2F,0xF5,0x82,0xE4,
+
+	0x34,0xDE,0xF5,0x83,0xEE,0xF0,0x90,0x44,
+
+	0xD8,0xE0,0x04,0xF0,0xE0,0xB4,0x08,0xDA,
+
+	0x90,0x44,0xDE,0x74,0x01,0xF0,0x90,0x41,
+
+	0xE3,0xE0,0x75,0xF0,0x05,0x84,0xFF,0x90,
+
+	0x44,0xEF,0xE0,0xB5,0x07,0x02,0xE4,0xF0,
+
+	0xE4,0x90,0x44,0xE0,0xF0,0x90,0x44,0xEB,
+
+	0xF0,0x90,0xDF,0x82,0xE0,0x20,0xE1,0x03,
+
+	0x02,0x6E,0x52,0x22,0x12,0x6E,0x21,0xEF,
+
+	0x60,0x03,0x02,0x72,0x66,0x90,0xDF,0x82,
+
+	0xE0,0x30,0xE1,0x03,0x02,0x72,0x66,0x90,
+
+	0x44,0xDA,0xE5,0xE4,0xF0,0x90,0x44,0xE0,
+
+	0xE0,0x14,0x60,0x3F,0x14,0x70,0x03,0x02,
+
+	0x71,0x33,0x24,0x02,0x60,0x03,0x02,0x72,
+
+	0x5C,0x90,0x44,0xDA,0xE0,0xB4,0x8C,0x23,
+
+	0xE4,0x90,0x44,0xEB,0xF0,0xA3,0xF0,0xA3,
+
+	0xF0,0xFF,0x7F,0x03,0x90,0x44,0xF3,0xE4,
+
+	0xF0,0xA3,0xDF,0xFC,0x7F,0x03,0x90,0x44,
+
+	0xE0,0x74,0x01,0xF0,0x90,0x44,0xF8,0xF0,
+
+	0x02,0x72,0x5C,0xE4,0x90,0x44,0xE0,0xF0,
+
+	0x02,0x72,0x5C,0x90,0x44,0xDA,0xE0,0x54,
+
+	0x0F,0xA3,0xF0,0x90,0x44,0xDA,0xE0,0xFF,
+
+	0xC4,0x54,0x0F,0x90,0x44,0xDC,0xF0,0x90,
+
+	0x44,0xF8,0xE0,0x24,0xFE,0x60,0x34,0x14,
+
+	0x60,0x52,0x14,0x60,0x70,0x14,0x70,0x03,
+
+	0x02,0x70,0xDF,0x24,0x04,0x60,0x03,0x02,
+
+	0x72,0x5C,0x90,0x44,0xDB,0xE0,0xB4,0x07,
+
+	0x0E,0xA3,0xE0,0xB4,0x07,0x09,0x90,0x44,
+
+	0xF8,0x74,0x02,0xF0,0x02,0x72,0x5C,0xE4,
+
+	0x90,0x44,0xE0,0xF0,0x90,0x44,0xF8,0xF0,
+
+	0x02,0x72,0x5C,0x90,0x44,0xDB,0xE0,0xB4,
+
+	0x07,0x0E,0xA3,0xE0,0xB4,0x07,0x09,0x90,
+
+	0x44,0xF8,0x74,0x03,0xF0,0x02,0x72,0x5C,
+
+	0xE4,0x90,0x44,0xE0,0xF0,0x90,0x44,0xF8,
+
+	0xF0,0x02,0x72,0x5C,0x90,0x44,0xDB,0xE0,
+
+	0xB4,0x07,0x0E,0xA3,0xE0,0xB4,0x08,0x09,
+
+	0x90,0x44,0xF8,0x74,0x04,0xF0,0x02,0x72,
+
+	0x5C,0xE4,0x90,0x44,0xE0,0xF0,0x90,0x44,
+
+	0xF8,0xF0,0x02,0x72,0x5C,0x90,0x44,0xDB,
+
+	0xE0,0xB4,0x07,0x0E,0xA3,0xE0,0xB4,0x08,
+
+	0x09,0x90,0x44,0xF8,0x74,0x05,0xF0,0x02,
+
+	0x72,0x5C,0xE4,0x90,0x44,0xE0,0xF0,0x90,
+
+	0x44,0xF8,0xF0,0x02,0x72,0x5C,0x90,0x44,
+
+	0xDB,0xE0,0x64,0x09,0x70,0x40,0x90,0x44,
+
+	0xF3,0x74,0x08,0xF0,0x90,0x44,0xDC,0xE0,
+
+	0xB4,0x08,0x0F,0x90,0x44,0xF4,0x74,0x88,
+
+	0xF0,0xA3,0xF0,0xE4,0xA3,0xF0,0xA3,0x74,
+
+	0x03,0xF0,0x90,0x44,0xDC,0xE0,0xB4,0x07,
+
+	0x0F,0x90,0x44,0xF4,0x74,0x88,0xF0,0xE4,
+
+	0xA3,0xF0,0xA3,0xF0,0xA3,0x74,0x02,0xF0,
+
+	0x90,0x44,0xE0,0x74,0x02,0xF0,0xE4,0x90,
+
+	0x44,0xF8,0xF0,0x02,0x72,0x5C,0xE4,0x90,
+
+	0x44,0xE0,0xF0,0x90,0x44,0xF8,0xF0,0x02,
+
+	0x72,0x5C,0x90,0x44,0xDA,0xE0,0x54,0x0F,
+
+	0xA3,0xF0,0x90,0x44,0xDA,0xE0,0xFF,0xC4,
+
+	0x54,0x0F,0x90,0x44,0xDC,0xF0,0x90,0x44,
+
+	0xDB,0xE0,0xB4,0x07,0x21,0x90,0x44,0xF7,
+
+	0xE0,0xFF,0x04,0xF0,0x74,0xF3,0x2F,0xF5,
+
+	0x82,0xE4,0x34,0x44,0xF5,0x83,0x74,0x08,
+
+	0xF0,0x90,0x44,0xF7,0xE0,0x64,0x04,0x70,
+
+	0x50,0x12,0x72,0xAA,0x80,0x4B,0x90,0x44,
+
+	0xDB,0xE0,0x64,0x08,0x70,0x3E,0x90,0x44,
+
+	0xF7,0xE0,0xFF,0x04,0xF0,0x74,0xF3,0x2F,
+
+	0xF5,0x82,0xE4,0x34,0x44,0xF5,0x83,0x74,
+
+	0x08,0xF0,0x90,0x44,0xF7,0xE0,0xB4,0x04,
+
+	0x03,0x12,0x72,0xAA,0x90,0x44,0xF7,0xE0,
+
+	0xFF,0x04,0xF0,0x74,0xF3,0x2F,0xF5,0x82,
+
+	0xE4,0x34,0x44,0xF5,0x83,0x74,0x08,0xF0,
+
+	0x90,0x44,0xF7,0xE0,0xB4,0x04,0x0A,0x12,
+
+	0x72,0xAA,0x80,0x05,0xE4,0x90,0x44,0xE0,
+
+	0xF0,0x90,0x44,0xDC,0xE0,0xC3,0x94,0x0C,
+
+	0x40,0x26,0x90,0x44,0xF7,0xE0,0x94,0x04,
+
+	0x50,0x14,0xE0,0xFF,0x04,0xF0,0x74,0xF3,
+
+	0x2F,0xF5,0x82,0xE4,0x34,0x44,0xF5,0x83,
+
+	0x74,0x88,0xF0,0x12,0x72,0xAA,0x12,0x72,
+
+	0x67,0xE4,0x90,0x44,0xE0,0xF0,0x80,0x73,
+
+	0x90,0x44,0xDC,0xE0,0xB4,0x07,0x21,0x90,
+
+	0x44,0xF7,0xE0,0xFF,0x04,0xF0,0x74,0xF3,
+
+	0x2F,0xF5,0x82,0xE4,0x34,0x44,0xF5,0x83,
+
+	0x74,0x88,0xF0,0x90,0x44,0xF7,0xE0,0x64,
+
+	0x04,0x70,0x50,0x12,0x72,0xAA,0x80,0x4B,
+
+	0x90,0x44,0xDC,0xE0,0x64,0x08,0x70,0x3E,
+
+	0x90,0x44,0xF7,0xE0,0xFF,0x04,0xF0,0x74,
+
+	0xF3,0x2F,0xF5,0x82,0xE4,0x34,0x44,0xF5,
+
+	0x83,0x74,0x88,0xF0,0x90,0x44,0xF7,0xE0,
+
+	0xB4,0x04,0x03,0x12,0x72,0xAA,0x90,0x44,
+
+	0xF7,0xE0,0xFF,0x04,0xF0,0x74,0xF3,0x2F,
+
+	0xF5,0x82,0xE4,0x34,0x44,0xF5,0x83,0x74,
+
+	0x88,0xF0,0x90,0x44,0xF7,0xE0,0xB4,0x04,
+
+	0x0A,0x12,0x72,0xAA,0x80,0x05,0xE4,0x90,
+
+	0x44,0xE0,0xF0,0x90,0xDF,0x82,0xE0,0x20,
+
+	0xE1,0x03,0x02,0x6F,0xE0,0x22,0x90,0x45,
+
+	0x18,0xE0,0xB4,0x01,0x0D,0x90,0x43,0x43,
+
+	0xE0,0xB4,0x01,0x06,0x12,0x73,0x64,0xEF,
+
+	0x60,0x2E,0x90,0x44,0xE1,0xE0,0x70,0x28,
+
+	0x7E,0xDE,0x7F,0x80,0x7C,0x44,0x7D,0xE3,
+
+	0x7B,0x08,0x12,0x56,0x9C,0x90,0x44,0xE1,
+
+	0x74,0x01,0xF0,0xE4,0xA3,0xF0,0x90,0x44,
+
+	0xDD,0xE0,0x60,0x06,0x90,0x44,0xDF,0xE0,
+
+	0x04,0xF0,0x90,0x44,0xDE,0x74,0x01,0xF0,
+
+	0x22,0xE4,0xFF,0xEF,0xC3,0x94,0x04,0x50,
+
+	0x65,0x74,0xF3,0x2F,0xF5,0x82,0xE4,0x34,
+
+	0x44,0xF5,0x83,0xE0,0xFE,0xB4,0x08,0x32,
+
+	0x74,0xF4,0x2F,0xF5,0x82,0xE4,0x34,0x44,
+
+	0xF5,0x83,0xE0,0xB4,0x88,0x24,0x90,0x44,
+
+	0xEC,0xE0,0xFD,0xC3,0x74,0x07,0x9D,0xFD,
+
+	0x74,0x01,0xA8,0x05,0x08,0x80,0x02,0xC3,
+
+	0x33,0xD8,0xFC,0xFD,0x90,0x44,0xED,0xE0,
+
+	0x2D,0xF0,0x90,0x44,0xEC,0xE0,0x04,0xF0,
+
+	0x80,0x20,0xEE,0xB4,0x88,0x16,0x74,0xF4,
+
+	0x2F,0xF5,0x82,0xE4,0x34,0x44,0xF5,0x83,
+
+	0xE0,0xB4,0x08,0x08,0x90,0x44,0xEC,0xE0,
+
+	0x04,0xF0,0x80,0x06,0x90,0x44,0xEC,0xE0,
+
+	0x04,0xF0,0x0F,0x0F,0x80,0x95,0xE4,0x90,
+
+	0x44,0xF7,0xF0,0x90,0x44,0xEC,0xE0,0x64,
+
+	0x08,0x70,0x3F,0xA3,0xE0,0xFF,0x90,0x44,
+
+	0xEB,0xE0,0xFE,0x04,0xF0,0x74,0xE3,0x2E,
+
+	0xF5,0x82,0xE4,0x34,0x44,0xF5,0x83,0xEF,
+
+	0xF0,0xE4,0x90,0x44,0xEC,0xF0,0xA3,0xF0,
+
+	0x90,0x44,0xEB,0xE0,0xB4,0x04,0x1B,0x90,
+
+	0x41,0xDF,0xE0,0xFF,0x90,0x44,0xE5,0xE0,
+
+	0x5F,0xF0,0x90,0x41,0xE0,0xE0,0xFF,0x90,
+
+	0x44,0xE6,0xE0,0x5F,0xF0,0xE4,0x90,0x44,
+
+	0xEB,0xF0,0x22,0xE4,0xFD,0xFC,0x90,0x41,
+
+	0xE1,0xE0,0x75,0xF0,0x07,0xA4,0xFF,0xC3,
+
+	0xED,0x9F,0xEC,0x95,0xF0,0x40,0x03,0x02,
+
+	0x75,0x01,0x74,0xE4,0x2D,0xF5,0x82,0x74,
+
+	0x41,0x3C,0xF5,0x83,0xE0,0xFF,0x90,0x44,
+
+	0xE3,0xE0,0xFE,0xEF,0x6E,0x60,0x03,0x02,
+
+	0x74,0xF7,0x74,0xE5,0x2D,0xF5,0x82,0x74,
+
+	0x41,0x3C,0xF5,0x83,0xE0,0xFF,0x90,0x44,
+
+	0xE4,0xE0,0xFE,0xEF,0x6E,0x60,0x03,0x02,
+
+	0x74,0xF7,0x74,0xE6,0x2D,0xF5,0x82,0x74,
+
+	0x41,0x3C,0xF5,0x83,0xE0,0xFF,0x90,0x44,
+
+	0xE5,0xE0,0xFE,0xEF,0x6E,0x60,0x03,0x02,
+
+	0x74,0xF7,0x74,0xE7,0x2D,0xF5,0x82,0x74,
+
+	0x41,0x3C,0xF5,0x83,0xE0,0xFF,0x90,0x44,
+
+	0xE6,0xE0,0xFE,0xEF,0x6E,0x60,0x03,0x02,
+
+	0x74,0xF7,0x74,0xEA,0x2D,0xF5,0x82,0x74,
+
+	0x41,0x3C,0xF5,0x83,0xE0,0xFE,0x30,0xE7,
+
+	0x0B,0x90,0x44,0xF1,0x74,0x01,0xF0,0xE4,
+
+	0xA3,0xF0,0xFF,0x22,0x90,0x44,0xF1,0xE0,
+
+	0x60,0x3D,0xE4,0xF0,0xA3,0xF0,0xEE,0x64,
+
+	0x40,0x70,0x2B,0x90,0x44,0xE3,0xF0,0xA3,
+
+	0xF0,0x74,0xEF,0x2D,0xF5,0x82,0x74,0x41,
+
+	0x3C,0xF5,0x83,0xE0,0x90,0x44,0xE5,0xF0,
+
+	0xE4,0xA3,0xF0,0xA3,0xF0,0xA3,0xF0,0xA3,
+
+	0xF0,0xA3,0xF0,0x90,0x44,0xF1,0x04,0xF0,
+
+	0xE4,0xA3,0xF0,0x7F,0x01,0x22,0xE4,0x90,
+
+	0x44,0xF1,0xF0,0xA3,0xF0,0xFF,0x22,0xE4,
+
+	0x90,0x44,0xE3,0xF0,0xA3,0xF0,0xA3,0xF0,
+
+	0xA3,0xF0,0xA3,0xF0,0xA3,0xF0,0xA3,0xF0,
+
+	0xA3,0xF0,0x74,0xE9,0x2D,0xF5,0x82,0x74,
+
+	0x41,0x3C,0xF5,0x83,0xE0,0xFE,0x70,0x1F,
+
+	0x74,0xEA,0x2D,0xF5,0x82,0x74,0x41,0x3C,
+
+	0xF5,0x83,0xE0,0x70,0x12,0x74,0xE8,0x2D,
+
+	0xF5,0x82,0x74,0x41,0x3C,0xF5,0x83,0xE0,
+
+	0x90,0x44,0xE5,0xF0,0x7F,0x01,0x22,0xEE,
+
+	0x70,0x20,0x74,0xEA,0x2D,0xF5,0x82,0x74,
+
+	0x41,0x3C,0xF5,0x83,0xE0,0xB4,0x40,0x12,
+
+	0x74,0xE8,0x2D,0xF5,0x82,0x74,0x41,0x3C,
+
+	0xF5,0x83,0xE0,0x90,0x44,0xE5,0xF0,0x7F,
+
+	0x01,0x22,0x74,0xE9,0x2D,0xF5,0x82,0x74,
+
+	0x41,0x3C,0xF5,0x83,0xE0,0xFF,0x60,0x16,
+
+	0x90,0x44,0xE3,0xF0,0x74,0xE8,0x2D,0xF5,
+
+	0x82,0x74,0x41,0x3C,0xF5,0x83,0xE0,0x90,
+
+	0x44,0xE5,0xF0,0x7F,0x01,0x22,0x74,0xEA,
+
+	0x2D,0xF5,0x82,0x74,0x41,0x3C,0xF5,0x83,
+
+	0xE0,0x30,0xE0,0x18,0x90,0x44,0xE5,0x74,
+
+	0x9A,0xF0,0x74,0xE8,0x2D,0xF5,0x82,0x74,
+
+	0x41,0x3C,0xF5,0x83,0xE0,0x90,0x44,0xE6,
+
+	0xF0,0x7F,0x01,0x22,0x74,0xE8,0x2D,0xF5,
+
+	0x82,0x74,0x41,0x3C,0xF5,0x83,0xE0,0x90,
+
+	0x44,0xE5,0xF0,0x7F,0x01,0x22,0x74,0x07,
+
+	0x2D,0xFD,0xE4,0x3C,0xFC,0x02,0x73,0x67,
+
+	0x7F,0x00,0x22,0xAE,0x07,0x90,0x41,0xDE,
+
+	0xE0,0xFD,0xB4,0x01,0x03,0x7F,0x03,0x22,
+
+	0xAF,0x06,0xE4,0x90,0x44,0xC9,0xF0,0x7A,
+
+	0x45,0x7B,0x00,0xA3,0x74,0x45,0xF0,0xA3,
+
+	0x74,0x00,0xF0,0xA3,0x74,0x01,0xF0,0xA3,
+
+	0xE4,0xF0,0x7B,0x01,0x12,0x6A,0xEA,0xEF,
+
+	0x60,0x03,0x7F,0x04,0x22,0x7E,0x45,0x7F,
+
+	0x02,0x90,0x45,0x02,0xE0,0xFD,0x7C,0x00,
+
+	0x12,0x6A,0xC4,0x90,0x45,0x00,0xE0,0x6E,
+
+	0x70,0x03,0xA3,0xE0,0x6F,0x60,0x03,0x7F,
+
+	0x05,0x22,0x7F,0x00,0x22,0x90,0x45,0x08,
+
+	0xE0,0xFF,0xA3,0xE0,0x90,0x43,0x6C,0xCF,
+
+	0xF0,0xA3,0xEF,0xF0,0x90,0x45,0x0A,0xE0,
+
+	0xFF,0xA3,0xE0,0x90,0x43,0x6E,0xCF,0xF0,
+
+	0xA3,0xEF,0xF0,0x90,0x45,0x0C,0xE0,0xFF,
+
+	0xA3,0xE0,0x90,0x43,0x70,0xCF,0xF0,0xA3,
+
+	0xEF,0xF0,0x90,0x45,0x0E,0xE0,0x90,0x43,
+
+	0x72,0xF0,0x90,0x45,0x0F,0xE0,0x90,0x43,
+
+	0x73,0xF0,0x90,0x45,0x10,0xE0,0x90,0x43,
+
+	0x74,0xF0,0x90,0x45,0x15,0xE0,0x90,0x44,
+
+	0x02,0xF0,0x90,0x45,0x13,0xE0,0x90,0x43,
+
+	0x88,0xF0,0x90,0x45,0x11,0xE0,0xFF,0x90,
+
+	0x44,0x71,0xF0,0x90,0x43,0x87,0xF0,0x90,
+
+	0x45,0x14,0xE0,0x90,0x44,0x72,0xF0,0x90,
+
+	0x45,0x16,0xE0,0x90,0xF1,0x03,0xF0,0x90,
+
+	0x45,0x56,0xE0,0xF4,0x60,0x05,0xE0,0x90,
+
+	0xDD,0x93,0xF0,0x22,0x22,0x90,0x45,0x04,
+
+	0xE0,0x70,0x03,0x02,0x78,0x4A,0x90,0x45,
+
+	0x04,0xE0,0x75,0xF0,0x08,0xA4,0x90,0x44,
+
+	0xF9,0xF0,0xE0,0x24,0x01,0xF5,0x82,0xE4,
+
+	0x34,0x45,0xF5,0x83,0xE0,0x90,0x44,0xFC,
+
+	0xF0,0x90,0x44,0xFC,0xE0,0x70,0x03,0x02,
+
+	0x78,0x4A,0x90,0x44,0xF9,0xE0,0xFE,0x24,
+
+	0x02,0xA3,0xF0,0x74,0x00,0x2E,0xF5,0x82,
+
+	0xE4,0x34,0x45,0xF5,0x83,0xE0,0x90,0x44,
+
+	0xFB,0xF0,0xE0,0x54,0xC0,0xFF,0x70,0x06,
+
+	0x90,0x44,0xC5,0xE0,0x70,0x16,0xBF,0x40,
+
+	0x06,0x90,0x44,0xC5,0xE0,0x60,0x0D,0x90,
+
+	0x44,0xFB,0xE0,0x54,0xC0,0x64,0xC0,0x60,
+
+	0x03,0x02,0x77,0xD7,0x90,0x44,0xFB,0xE0,
+
+	0x54,0x03,0x14,0x60,0x54,0x14,0x70,0x03,
+
+	0x02,0x76,0xEF,0x14,0x70,0x03,0x02,0x77,
+
+	0x6D,0x24,0x03,0x60,0x03,0x02,0x77,0xD7,
+
+	0xE4,0x90,0x44,0xFD,0xF0,0x90,0x44,0xFC,
+
+	0xE0,0xFF,0xA3,0xE0,0xC3,0x9F,0x40,0x03,
+
+	0x02,0x77,0xD7,0x90,0x44,0xFA,0xE0,0xFE,
+
+	0x24,0x00,0xF5,0x82,0xE4,0x34,0x45,0xF5,
+
+	0x83,0xE0,0xFF,0x74,0x01,0x2E,0xF5,0x82,
+
+	0xE4,0x34,0x45,0xF5,0x83,0xE0,0xFD,0x12,
+
+	0x64,0xEF,0x90,0x44,0xFA,0xE0,0x24,0x02,
+
+	0xF0,0x90,0x44,0xFD,0xE0,0x04,0xF0,0x80,
+
+	0xC4,0xE4,0x90,0x44,0xFD,0xF0,0x90,0x44,
+
+	0xFC,0xE0,0xFF,0xA3,0xE0,0xC3,0x9F,0x40,
+
+	0x03,0x02,0x77,0xD7,0x90,0x44,0xFA,0xE0,
+
+	0xFF,0x24,0x02,0xF5,0x82,0xE4,0x34,0x45,
+
+	0xF5,0x83,0xE0,0xFD,0x74,0x00,0x2F,0xF5,
+
+	0x82,0xE4,0x34,0x45,0xF5,0x83,0xE0,0xFE,
+
+	0x90,0x44,0xFA,0xE0,0x24,0x01,0xF5,0x82,
+
+	0xE4,0x34,0x45,0xF5,0x83,0xE0,0xFB,0xEE,
+
+	0xEB,0xF5,0x82,0x8E,0x83,0xED,0xF0,0x90,
+
+	0x44,0xFA,0xE0,0x24,0x03,0xF0,0x90,0x44,
+
+	0xFD,0xE0,0x04,0xF0,0x80,0xB0,0x90,0x44,
+
+	0xFA,0xE0,0xFD,0x24,0x00,0xF5,0x82,0xE4,
+
+	0x34,0x45,0xF5,0x83,0xE0,0xFE,0x74,0x01,
+
+	0x2D,0xF5,0x82,0xE4,0x34,0x45,0xF5,0x83,
+
+	0xE0,0xFD,0xEE,0xED,0xFF,0x90,0x44,0xFE,
+
+	0xEE,0xF0,0xA3,0xEF,0xF0,0x90,0x44,0xFA,
+
+	0xE0,0x24,0x02,0xF0,0xE4,0x90,0x44,0xFD,
+
+	0xF0,0x90,0x44,0xFC,0xE0,0xFF,0xA3,0xE0,
+
+	0xC3,0x9F,0x40,0x03,0x02,0x77,0xD7,0x90,
+
+	0x44,0xFA,0xE0,0xFF,0x24,0x01,0xF5,0x82,
+
+	0xE4,0x34,0x45,0xF5,0x83,0xE0,0xFE,0x74,
+
+	0x00,0x2F,0xF5,0x82,0xE4,0x34,0x45,0xF5,
+
+	0x83,0xE0,0xFD,0x90,0x44,0xFF,0xE0,0x2D,
+
+	0xFD,0x90,0x44,0xFE,0xE0,0x34,0x00,0x8D,
+
+	0x82,0xF5,0x83,0xEE,0xF0,0x90,0x44,0xFA,
+
+	0xE0,0x24,0x02,0xF0,0x90,0x44,0xFD,0xE0,
+
+	0x04,0xF0,0x80,0xB5,0x90,0x44,0xFA,0xE0,
+
+	0xFD,0x24,0x00,0xF5,0x82,0xE4,0x34,0x45,
+
+	0xF5,0x83,0xE0,0xFE,0x74,0x01,0x2D,0xF5,
+
+	0x82,0xE4,0x34,0x45,0xF5,0x83,0xE0,0xFD,
+
+	0xEE,0xED,0xFF,0x90,0x44,0xFE,0xEE,0xF0,
+
+	0xA3,0xEF,0xF0,0x90,0x44,0xFA,0xE0,0x24,
+
+	0x02,0xF0,0xE4,0x90,0x44,0xFD,0xF0,0x90,
+
+	0x44,0xFC,0xE0,0xFF,0xA3,0xE0,0xC3,0x9F,
+
+	0x50,0x2C,0x90,0x44,0xFA,0xE0,0xFF,0x04,
+
+	0xF0,0x74,0x00,0x2F,0xF5,0x82,0xE4,0x34,
+
+	0x45,0xF5,0x83,0xE0,0xFF,0x90,0x44,0xFE,
+
+	0xE4,0x75,0xF0,0x01,0x12,0x7D,0x82,0x85,
+
+	0xF0,0x82,0xF5,0x83,0xEF,0xF0,0x90,0x44,
+
+	0xFD,0xE0,0x04,0xF0,0x80,0xC9,0x90,0x44,
+
+	0xF9,0xE0,0x24,0x02,0xF0,0x90,0x44,0xFB,
+
+	0xE0,0x54,0x03,0x14,0x60,0x19,0x14,0x60,
+
+	0x27,0x14,0x60,0x38,0x24,0x03,0x70,0x44,
+
+	0x90,0x44,0xFC,0xE0,0x25,0xE0,0xFF,0x90,
+
+	0x44,0xF9,0xE0,0x2F,0xF0,0x80,0x35,0x90,
+
+	0x44,0xFC,0xE0,0x75,0xF0,0x03,0xA4,0xFF,
+
+	0x90,0x44,0xF9,0xE0,0x2F,0xF0,0x80,0x24,
+
+	0x90,0x44,0xF9,0xE0,0x24,0x02,0xFF,0x90,
+
+	0x44,0xFC,0xE0,0x25,0xE0,0x2F,0x90,0x44,
+
+	0xF9,0xF0,0x80,0x10,0x90,0x44,0xF9,0xE0,
+
+	0x24,0x02,0xFF,0x90,0x44,0xFC,0xE0,0x2F,
+
+	0x90,0x44,0xF9,0xF0,0x90,0x44,0xF9,0xE0,
+
+	0x24,0x01,0xF5,0x82,0xE4,0x34,0x45,0xF5,
+
+	0x83,0xE0,0x90,0x44,0xFC,0xF0,0x02,0x75,
+
+	0xFA,0x22,0x90,0x44,0xB8,0xE0,0x60,0x08,
+
+	0x90,0x46,0x01,0x74,0x01,0xF0,0x80,0x06,
+
+	0x90,0x46,0x01,0x74,0x03,0xF0,0x12,0x56,
+
+	0xBB,0x12,0x6A,0xDF,0x90,0xF1,0x03,0xE0,
+
+	0x90,0x41,0x91,0xF0,0x90,0xF6,0xB5,0xE0,
+
+	0x54,0xF7,0x44,0x08,0xF0,0xE0,0x54,0xF7,
+
+	0xF0,0x90,0x41,0x91,0xE0,0x90,0xF1,0x03,
+
+	0xF0,0x90,0x46,0x01,0xE0,0xFF,0x12,0x6C,
+
+	0xA2,0x90,0x41,0xDE,0xEF,0xF0,0x90,0x44,
+
+	0xB8,0xE0,0x60,0x03,0x12,0x5A,0x5A,0x90,
+
+	0x46,0x01,0xE0,0xFF,0x12,0x75,0x04,0xEF,
+
+	0x70,0x04,0x7F,0x01,0x80,0x02,0x7F,0x00,
+
+	0x90,0x46,0x00,0xEF,0xF0,0x60,0x1C,0x90,
+
+	0x45,0x57,0xE0,0x60,0x16,0xE0,0x90,0xF6,
+
+	0x32,0xF0,0x90,0x45,0x57,0xE0,0x90,0xF6,
+
+	0x33,0xF0,0x90,0xF6,0x31,0xE0,0x54,0xFE,
+
+	0x44,0x01,0xF0,0x90,0x46,0x00,0xE0,0x60,
+
+	0x07,0x12,0x75,0x56,0x12,0x75,0xD6,0x22,
+
+	0x90,0x44,0xB8,0xE0,0x60,0x1E,0xE4,0x90,
+
+	0x45,0x31,0xF0,0x90,0x45,0x33,0xF0,0x90,
+
+	0x45,0x12,0xF0,0x90,0x45,0x18,0x74,0x05,
+
+	0xF0,0xE4,0x90,0x45,0x34,0xF0,0x90,0x45,
+
+	0x11,0x74,0x80,0xF0,0x22,0xE4,0x90,0x46,
+
+	0x06,0xF0,0xA3,0xF0,0xA3,0xF0,0xA3,0xF0,
+
+	0xA3,0xF0,0x90,0xDF,0x84,0x74,0x64,0xF0,
+
+	0xE4,0x90,0xDF,0x85,0xF0,0x90,0xDF,0x86,
+
+	0x74,0x2C,0xF0,0x90,0xDF,0x87,0x74,0x01,
+
+	0xF0,0xE4,0x90,0xDF,0x88,0xF0,0x90,0xDF,
+
+	0x89,0x74,0x02,0xF0,0x12,0x6C,0xE7,0x90,
+
+	0xDF,0x82,0xE0,0x20,0xE1,0x08,0x90,0x46,
+
+	0x05,0xE5,0xE4,0xF0,0x80,0xF1,0x22,0x90,
+
+	0xDF,0x82,0xE0,0x30,0xE0,0x0E,0x74,0x20,
+
+	0xF0,0xE0,0x90,0x46,0x02,0xF0,0xE4,0x90,
+
+	0xDF,0x82,0xF0,0x22,0x90,0xDF,0x82,0xE0,
+
+	0x30,0xE1,0x03,0x02,0x7B,0x3D,0x90,0x46,
+
+	0x02,0xE5,0xE4,0xF0,0xE0,0x54,0x0F,0xA3,
+
+	0xF0,0x90,0x46,0x02,0xE0,0xFF,0xC4,0x54,
+
+	0x0F,0x90,0x46,0x04,0xF0,0x90,0x44,0xE0,
+
+	0xE0,0x14,0x70,0x03,0x02,0x7A,0x25,0x04,
+
+	0x60,0x03,0x02,0x7A,0x92,0x90,0x46,0x07,
+
+	0xE0,0x25,0xE0,0xF0,0x90,0x46,0x06,0xE0,
+
+	0x33,0xF0,0xA3,0xE0,0x44,0x01,0xF0,0xA3,
+
+	0xE0,0x04,0xF0,0x90,0x46,0x02,0xE0,0x24,
+
+	0xEF,0x70,0x03,0x02,0x7A,0x92,0x24,0xEF,
+
+	0x60,0x20,0x24,0x10,0x70,0x37,0x90,0x46,
+
+	0x07,0xE0,0x25,0xE0,0xF0,0x90,0x46,0x06,
+
+	0xE0,0x33,0xF0,0x90,0x46,0x08,0xE0,0x04,
+
+	0xF0,0x90,0x44,0xE0,0x74,0x01,0xF0,0x02,
+
+	0x7A,0x92,0x90,0x46,0x07,0xE0,0x25,0xE0,
+
+	0xF0,0x90,0x46,0x06,0xE0,0x33,0xF0,0x90,
+
+	0x46,0x08,0xE0,0x04,0xF0,0xE4,0x90,0x44,
+
+	0xE0,0xF0,0x02,0x7A,0x92,0x90,0x46,0x03,
+
+	0xE0,0xB4,0x02,0x13,0x90,0x46,0x07,0xE0,
+
+	0x25,0xE0,0xF0,0x90,0x46,0x06,0xE0,0x33,
+
+	0xF0,0x90,0x46,0x08,0xE0,0x04,0xF0,0x90,
+
+	0x46,0x04,0xE0,0xD3,0x94,0x02,0x40,0x14,
+
+	0x90,0x46,0x03,0xE0,0x64,0x01,0x60,0x04,
+
+	0xE0,0xB4,0x02,0x08,0x90,0x46,0x04,0x74,
+
+	0xFF,0xF0,0x80,0x75,0x90,0x46,0x04,0x74,
+
+	0xFE,0xF0,0x80,0x6D,0x90,0x46,0x02,0xE0,
+
+	0x24,0xDF,0x60,0x1F,0x24,0x10,0x70,0x35,
+
+	0x90,0x46,0x07,0xE0,0x25,0xE0,0xF0,0x90,
+
+	0x46,0x06,0xE0,0x33,0xF0,0x90,0x46,0x08,
+
+	0xE0,0x04,0xF0,0x90,0x44,0xE0,0x74,0x01,
+
+	0xF0,0x80,0x46,0x90,0x46,0x07,0xE0,0x25,
+
+	0xE0,0xF0,0x90,0x46,0x06,0xE0,0x33,0xF0,
+
+	0x90,0x46,0x08,0xE0,0x04,0xF0,0xE4,0x90,
+
+	0x44,0xE0,0xF0,0x80,0x2C,0x90,0x46,0x07,
+
+	0xE0,0x25,0xE0,0xF0,0x90,0x46,0x06,0xE0,
+
+	0x33,0xF0,0x90,0x46,0x08,0xE0,0x04,0xF0,
+
+	0x90,0x46,0x03,0xE0,0xB4,0x01,0x0C,0xA3,
+
+	0xE0,0xD3,0x94,0x02,0x40,0x05,0x74,0xFF,
+
+	0xF0,0x80,0x06,0x90,0x46,0x04,0x74,0xFE,
+
+	0xF0,0x90,0x46,0x04,0xE0,0xD3,0x94,0x0F,
+
+	0x50,0x03,0x02,0x79,0x55,0x90,0x46,0x08,
+
+	0xE0,0xFF,0xD3,0x94,0x10,0x50,0x7E,0xEF,
+
+	0x94,0x0A,0x40,0x79,0x90,0x46,0x04,0xE0,
+
+	0xF4,0x70,0x72,0xFF,0x7F,0x08,0x90,0x44,
+
+	0xE3,0xE4,0xF0,0xA3,0xDF,0xFC,0x7F,0x08,
+
+	0x90,0x45,0x34,0xE0,0xB4,0xFF,0x1A,0x90,
+
+	0x46,0x06,0xE0,0xFE,0xA3,0xE0,0xFF,0x90,
+
+	0x46,0x09,0xE0,0x6E,0x70,0x03,0xA3,0xE0,
+
+	0x6F,0x60,0x06,0x90,0x44,0xE3,0x74,0x01,
+
+	0xF0,0x90,0x46,0x06,0xE0,0xFF,0xA3,0xE0,
+
+	0x90,0x46,0x09,0xCF,0xF0,0xA3,0xEF,0xF0,
+
+	0x90,0x46,0x06,0xE0,0x54,0xF7,0xF0,0x90,
+
+	0x45,0x34,0xE0,0xB4,0xFF,0x12,0x90,0x46,
+
+	0x09,0xE0,0x90,0x44,0xE5,0xF0,0x90,0x46,
+
+	0x0A,0xE0,0x90,0x44,0xE6,0xF0,0x80,0x10,
+
+	0x90,0x46,0x06,0xE0,0x90,0x44,0xE5,0xF0,
+
+	0x90,0x46,0x07,0xE0,0x90,0x44,0xE6,0xF0,
+
+	0x12,0x72,0x67,0x80,0x07,0xE4,0x90,0x46,
+
+	0x09,0xF0,0xA3,0xF0,0xE4,0x90,0x46,0x06,
+
+	0xF0,0xA3,0xF0,0xA3,0xF0,0x90,0x44,0xE0,
+
+	0xF0,0x02,0x79,0x55,0x22,0x90,0x41,0x92,
+
+	0xE0,0x70,0x0A,0x90,0xF1,0x02,0xE0,0x54,
+
+	0xFE,0x44,0x01,0xF0,0x22,0x90,0x41,0x96,
+
+	0xE0,0x90,0xF1,0x03,0xF0,0x90,0x83,0xFE,
+
+	0xE0,0x54,0xFE,0x44,0x01,0xF0,0xE0,0x54,
+
+	0xFE,0xF0,0xE0,0x54,0xFE,0x44,0x01,0xF0,
+
+	0xE0,0x54,0xFE,0xF0,0x12,0x56,0xBB,0xC2,
+
+	0xAF,0x90,0x41,0x93,0xE0,0xFF,0x90,0xF1,
+
+	0x01,0xE0,0x8F,0xF0,0xA4,0xFF,0xAE,0xF0,
+
+	0x90,0x41,0x94,0xE0,0x7C,0x00,0x2F,0xF5,
+
+	0x17,0xEC,0x3E,0xF5,0x16,0xE4,0xF5,0x18,
+
+	0xF5,0x14,0xF5,0x15,0xC3,0xE5,0x15,0x95,
+
+	0x17,0xE5,0x14,0x95,0x16,0x50,0x6A,0xE5,
+
+	0x15,0x45,0x14,0x70,0x16,0x90,0xF1,0x02,
+
+	0xE0,0x54,0xFE,0x44,0x01,0xF0,0x90,0x83,
+
+	0xFE,0xE0,0x54,0xFE,0x44,0x01,0xF0,0xE0,
+
+	0x54,0xFE,0xF0,0xE5,0x18,0x25,0xE0,0x24,
+
+	0x99,0xF5,0x82,0xE4,0x34,0x41,0xF5,0x83,
+
+	0xE0,0xFE,0xA3,0xE0,0xFF,0x12,0x7C,0x73,
+
+	0x7E,0x00,0xE5,0x15,0x54,0x01,0x24,0x95,
+
+	0xF5,0x82,0xEE,0x34,0x41,0xF5,0x83,0xE0,
+
+	0x90,0xF1,0x03,0xF0,0x90,0x83,0xFE,0xE0,
+
+	0x54,0xFE,0x44,0x01,0xF0,0xE0,0x54,0xFE,
+
+	0xF0,0x05,0x15,0xE5,0x15,0x70,0x02,0x05,
+
+	0x14,0x74,0x0B,0x25,0x18,0xF5,0x82,0xE4,
+
+	0x34,0x46,0xF5,0x83,0xE0,0xF5,0x18,0x80,
+
+	0x8B,0xD2,0xAF,0xE4,0x22,0xE4,0xFF,0x90,
+
+	0x41,0x98,0xE0,0xFE,0x90,0x41,0x97,0xE0,
+
+	0xFD,0x2E,0x14,0xFE,0xEF,0xC3,0x9E,0x50,
+
+	0x12,0xEF,0x04,0xFE,0x74,0x0B,0x2F,0xF5,
+
+	0x82,0xE4,0x34,0x46,0xF5,0x83,0xEE,0xF0,
+
+	0x0F,0x80,0xDC,0x74,0x0B,0x2F,0xF5,0x82,
+
+	0xE4,0x34,0x46,0xF5,0x83,0xED,0xF0,0x22,
+
+	0xE4,0x90,0x41,0x92,0xF0,0xA3,0x74,0x02,
+
+	0xF0,0xA3,0x14,0xF0,0xA3,0x74,0xFF,0xF0,
+
+	0xA3,0x74,0x07,0xF0,0xA3,0x74,0x01,0xF0,
+
+	0xA3,0x04,0xF0,0xA3,0xE4,0xF0,0xA3,0x74,
+
+	0x77,0xF0,0xA3,0x74,0x03,0xF0,0xA3,0x74,
+
+	0x40,0xF0,0xA3,0xE4,0xF0,0xA3,0x74,0x24,
+
+	0xF0,0x22,0xC0,0x07,0x85,0x06,0x07,0x12,
+
+	0x7C,0x8F,0xD0,0xE0,0xC0,0xE0,0xC4,0x54,
+
+	0x0F,0xFF,0x12,0x7C,0xAF,0xD0,0xE0,0x54,
+
+	0x0F,0xFF,0x12,0x7C,0xC0,0x22,0xEF,0x70,
+
+	0x02,0x80,0x0B,0x80,0x00,0xC0,0x07,0x12,
+
+	0x7C,0xA0,0xD0,0x07,0xDF,0xF7,0x22,0x7F,
+
+	0x0C,0x12,0x7C,0xAF,0x7F,0x04,0x90,0x7C,
+
+	0xA0,0xE0,0xDF,0xFD,0xE0,0x22,0xEF,0x70,
+
+	0x02,0x80,0x0B,0x80,0x00,0x90,0x7C,0xB6,
+
+	0xE0,0xE0,0xE0,0x04,0xDF,0xF7,0x22,0x90,
+
+	0x7C,0xC8,0xEF,0xF4,0x54,0x0F,0x73,0x04,
+
+	0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
+
+	0x04,0x04,0x04,0x04,0x04,0x04,0x22,0xBB,
+
+	0x01,0x0C,0xE5,0x82,0x29,0xF5,0x82,0xE5,
+
+	0x83,0x3A,0xF5,0x83,0xE0,0x22,0x50,0x06,
+
+	0xE9,0x25,0x82,0xF8,0xE6,0x22,0xBB,0xFE,
+
+	0x06,0xE9,0x25,0x82,0xF8,0xE2,0x22,0xE5,
+
+	0x82,0x29,0xF5,0x82,0xE5,0x83,0x3A,0xF5,
+
+	0x83,0xE4,0x93,0x22,0xEF,0x8D,0xF0,0xA4,
+
+	0xA8,0xF0,0xCF,0x8C,0xF0,0xA4,0x28,0xCE,
+
+	0x8D,0xF0,0xA4,0x2E,0xFE,0x22,0xBC,0x00,
+
+	0x0B,0xBE,0x00,0x29,0xEF,0x8D,0xF0,0x84,
+
+	0xFF,0xAD,0xF0,0x22,0xE4,0xCC,0xF8,0x75,
+
+	0xF0,0x08,0xEF,0x2F,0xFF,0xEE,0x33,0xFE,
+
+	0xEC,0x33,0xFC,0xEE,0x9D,0xEC,0x98,0x40,
+
+	0x05,0xFC,0xEE,0x9D,0xFE,0x0F,0xD5,0xF0,
+
+	0xE9,0xE4,0xCE,0xFD,0x22,0xED,0xF8,0xF5,
+
+	0xF0,0xEE,0x84,0x20,0xD2,0x1C,0xFE,0xAD,
+
+	0xF0,0x75,0xF0,0x08,0xEF,0x2F,0xFF,0xED,
+
+	0x33,0xFD,0x40,0x07,0x98,0x50,0x06,0xD5,
+
+	0xF0,0xF2,0x22,0xC3,0x98,0xFD,0x0F,0xD5,
+
+	0xF0,0xEA,0x22,0xC5,0xF0,0xF8,0xA3,0xE0,
+
+	0x28,0xF0,0xC5,0xF0,0xF8,0xE5,0x82,0x15,
+
+	0x82,0x70,0x02,0x15,0x83,0xE0,0x38,0xF0,
+
+	0x22,0xA3,0xF8,0xE0,0xC5,0xF0,0x25,0xF0,
+
+	0xF0,0xE5,0x82,0x15,0x82,0x70,0x02,0x15,
+
+	0x83,0xE0,0xC8,0x38,0xF0,0xE8,0x22,0xE8,
+
+	0x8F,0xF0,0xA4,0xCC,0x8B,0xF0,0xA4,0x2C,
+
+	0xFC,0xE9,0x8E,0xF0,0xA4,0x2C,0xFC,0x8A,
+
+	0xF0,0xED,0xA4,0x2C,0xFC,0xEA,0x8E,0xF0,
+
+	0xA4,0xCD,0xA8,0xF0,0x8B,0xF0,0xA4,0x2D,
+
+	0xCC,0x38,0x25,0xF0,0xFD,0xE9,0x8F,0xF0,
+
+	0xA4,0x2C,0xCD,0x35,0xF0,0xFC,0xEB,0x8E,
+
+	0xF0,0xA4,0xFE,0xA9,0xF0,0xEB,0x8F,0xF0,
+
+	0xA4,0xCF,0xC5,0xF0,0x2E,0xCD,0x39,0xFE,
+
+	0xE4,0x3C,0xFC,0xEA,0xA4,0x2D,0xCE,0x35,
+
+	0xF0,0xFD,0xE4,0x3C,0xFC,0x22,0x75,0xF0,
+
+	0x08,0x75,0x82,0x00,0xEF,0x2F,0xFF,0xEE,
+
+	0x33,0xFE,0xCD,0x33,0xCD,0xCC,0x33,0xCC,
+
+	0xC5,0x82,0x33,0xC5,0x82,0x9B,0xED,0x9A,
+
+	0xEC,0x99,0xE5,0x82,0x98,0x40,0x0C,0xF5,
+
+	0x82,0xEE,0x9B,0xFE,0xED,0x9A,0xFD,0xEC,
+
+	0x99,0xFC,0x0F,0xD5,0xF0,0xD6,0xE4,0xCE,
+
+	0xFB,0xE4,0xCD,0xFA,0xE4,0xCC,0xF9,0xA8,
+
+	0x82,0x22,0xB8,0x00,0xC1,0xB9,0x00,0x59,
+
+	0xBA,0x00,0x2D,0xEC,0x8B,0xF0,0x84,0xCF,
+
+	0xCE,0xCD,0xFC,0xE5,0xF0,0xCB,0xF9,0x78,
+
+	0x18,0xEF,0x2F,0xFF,0xEE,0x33,0xFE,0xED,
+
+	0x33,0xFD,0xEC,0x33,0xFC,0xEB,0x33,0xFB,
+
+	0x10,0xD7,0x03,0x99,0x40,0x04,0xEB,0x99,
+
+	0xFB,0x0F,0xD8,0xE5,0xE4,0xF9,0xFA,0x22,
+
+	0x78,0x18,0xEF,0x2F,0xFF,0xEE,0x33,0xFE,
+
+	0xED,0x33,0xFD,0xEC,0x33,0xFC,0xC9,0x33,
+
+	0xC9,0x10,0xD7,0x05,0x9B,0xE9,0x9A,0x40,
+
+	0x07,0xEC,0x9B,0xFC,0xE9,0x9A,0xF9,0x0F,
+
+	0xD8,0xE0,0xE4,0xC9,0xFA,0xE4,0xCC,0xFB,
+
+	0x22,0x75,0xF0,0x10,0xEF,0x2F,0xFF,0xEE,
+
+	0x33,0xFE,0xED,0x33,0xFD,0xCC,0x33,0xCC,
+
+	0xC8,0x33,0xC8,0x10,0xD7,0x07,0x9B,0xEC,
+
+	0x9A,0xE8,0x99,0x40,0x0A,0xED,0x9B,0xFD,
+
+	0xEC,0x9A,0xFC,0xE8,0x99,0xF8,0x0F,0xD5,
+
+	0xF0,0xDA,0xE4,0xCD,0xFB,0xE4,0xCC,0xFA,
+
+	0xE4,0xC8,0xF9,0x22,0xD0,0x83,0xD0,0x82,
+
+	0xF8,0xE4,0x93,0x70,0x12,0x74,0x01,0x93,
+
+	0x70,0x0D,0xA3,0xA3,0x93,0xF8,0x74,0x01,
+
+	0x93,0xF5,0x82,0x88,0x83,0xE4,0x73,0x74,
+
+	0x02,0x93,0x68,0x60,0xEF,0xA3,0xA3,0xA3,
+
+	0x80,0xDF,0x8A,0x83,0x89,0x82,0xE4,0x73,
+
+	0xE7,0x09,0xF6,0x08,0xDF,0xFA,0x80,0x46,
+
+	0xE7,0x09,0xF2,0x08,0xDF,0xFA,0x80,0x3E,
+
+	0x88,0x82,0x8C,0x83,0xE7,0x09,0xF0,0xA3,
+
+	0xDF,0xFA,0x80,0x32,0xE3,0x09,0xF6,0x08,
+
+	0xDF,0xFA,0x80,0x6E,0xE3,0x09,0xF2,0x08,
+
+	0xDF,0xFA,0x80,0x66,0x88,0x82,0x8C,0x83,
+
+	0xE3,0x09,0xF0,0xA3,0xDF,0xFA,0x80,0x5A,
+
+	0x89,0x82,0x8A,0x83,0xE0,0xA3,0xF6,0x08,
+
+	0xDF,0xFA,0x80,0x4E,0x89,0x82,0x8A,0x83,
+
+	0xE0,0xA3,0xF2,0x08,0xDF,0xFA,0x80,0x42,
+
+	0x80,0xD2,0x80,0xFA,0x80,0xC6,0x80,0xD4,
+
+	0x80,0x55,0x80,0xF2,0x80,0x29,0x80,0x10,
+
+	0x80,0xA6,0x80,0xEA,0x80,0x9A,0x80,0xA8,
+
+	0x80,0xDA,0x80,0xE2,0x80,0xCA,0x80,0x29,
+
+	0x88,0x84,0x8C,0x85,0x89,0x82,0x8A,0x83,
+
+	0xE4,0x93,0xA3,0x05,0x86,0xF0,0xA3,0x05,
+
+	0x86,0xDF,0xF5,0xDE,0xF3,0x80,0x0B,0x89,
+
+	0x82,0x8A,0x83,0xE4,0x93,0xA3,0xF6,0x08,
+
+	0xDF,0xF9,0xEC,0xFA,0xA9,0xF0,0xED,0xFB,
+
+	0x22,0x88,0x84,0x8C,0x85,0x89,0x82,0x8A,
+
+	0x83,0xE0,0xA3,0x05,0x86,0xF0,0xA3,0x05,
+
+	0x86,0xDF,0xF6,0xDE,0xF4,0x80,0xE3,0x89,
+
+	0x82,0x8A,0x83,0xE4,0x93,0xA3,0xF2,0x08,
+
+	0xDF,0xF9,0x80,0xD6,0x88,0xF0,0xEF,0x60,
+
+	0x01,0x0E,0x4E,0x60,0xCD,0x88,0xF0,0xED,
+
+	0x24,0x02,0xB4,0x04,0x00,0x50,0xC3,0xF5,
+
+	0x82,0xEB,0x24,0x02,0xB4,0x04,0x00,0x50,
+
+	0xB9,0x23,0x23,0x45,0x82,0x23,0x90,0x7F,
+
+	0x31,0x73,0x12,0x01,0x00,0x02,0x00,0x00,
+
+	0x00,0x40,0xA4,0x15,0x50,0x03,0x00,0x02,
+
+	0x00,0x00,0x00,0x01,0x0A,0x06,0x00,0x02,
+
+	0x00,0x00,0x00,0x40,0x01,0x00,0x09,0x07,
+
+	0x35,0x00,0x01,0x01,0x00,0x80,0xFA,0x09,
+
+	0x02,0x35,0x00,0x01,0x01,0x00,0x80,0xFA,
+
+	0x09,0x04,0x00,0x00,0x05,0xFF,0x00,0x00,
+
+	0x00,0x07,0x05,0x81,0x02,0x40,0x00,0x00,
+
+	0x07,0x05,0x02,0x02,0x40,0x00,0x00,0x07,
+
+	0x05,0x84,0x02,0x40,0x00,0x00,0x07,0x05,
+
+	0x85,0x02,0x40,0x00,0x00,0x07,0x05,0x86,
+
+	0x01,0x00,0x00,0x01,0x09,0x04,0x00,0x01,
+
+	0x05,0xFF,0x00,0x00,0x00,0x07,0x05,0x81,
+
+	0x02,0x40,0x00,0x00,0x07,0x05,0x02,0x02,
+
+	0x40,0x00,0x00,0x07,0x05,0x84,0x02,0x40,
+
+	0x00,0x00,0x07,0x05,0x85,0x02,0x40,0x00,
+
+	0x00,0x07,0x05,0x86,0x01,0x00,0x14,0x01,
+
+	0x09,0x04,0x01,0x00,0x01,0x03,0x00,0x01,
+
+	0x00,0x09,0x21,0x01,0x01,0x00,0x01,0x22,
+
+	0x41,0x00,0x07,0x05,0x83,0x03,0x40,0x00,
+
+	0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+
+	0x00,0x00,0x00,0x00,0x00,0x05,0x01,0x09,
+
+	0x06,0xA1,0x01,0x05,0x07,0x19,0xE0,0x29,
+
+	0xE7,0x15,0x00,0x25,0x01,0x95,0x08,0x75,
+
+	0x01,0x81,0x02,0x95,0x08,0x75,0x01,0x81,
+
+	0x01,0x05,0x08,0x19,0x01,0x29,0x03,0x95,
+
+	0x03,0x75,0x01,0x91,0x02,0x95,0x01,0x75,
+
+	0x05,0x91,0x01,0x05,0x07,0x19,0x00,0x2A,
+
+	0xFF,0x00,0x15,0x00,0x26,0xFF,0x00,0x95,
+
+	0x06,0x75,0x08,0x81,0x00,0xC0,
+
+	0x02,0x41,0x00,0x00,0x03,0xFA,0xBE,0x02,
+
+	0x99,0x14,
+
+	0x02,0x45,0x50,0x6A,0xAD,0x00,0x50,0x90,
+
+	0x43,0x66,0xE0,0xFE,0x90,0x44,0x02,0xF0,
+
+	0xE4,0xA3,0xF0,0xA3,0xF0,0xA3,0xF0,0xA3,
+
+	0xF0,0xA3,0xF0,0xA3,0xCE,0xF0,0xE4,0xA3,
+
+	0xF0,0xA3,0xF0,0xA3,0xF0,0xA3,0xF0,0x90,
+
+	0x44,0x02,0xE0,0x04,0xFF,0x90,0x41,0xEF,
+
+	0xE0,0xFE,0x2F,0x8E,0xF0,0x84,0xAF,0xF0,
+
+	0x90,0x44,0x02,0xEF,0xF0,0xA3,0xE0,0xFD,
+
+	0xA3,0xE0,0xA3,0xCD,0xF0,0xA3,0xED,0xF0,
+
+	0xEF,0x25,0xE0,0x24,0x58,0xF5,0x82,0xE4,
+
+	0x34,0x43,0xF5,0x83,0xE0,0xFE,0xA3,0xE0,
+
+	0xFF,0x90,0x43,0x61,0xE0,0xFC,0xA3,0xE0,
+
+	0xFD,0xEF,0x2D,0xFF,0xEE,0x3C,0xFE,0x90,
+
+	0x43,0x66,0xE0,0x25,0xE0,0x24,0x58,0xF5,
+
+	0x82,0xE4,0x34,0x43,0xF5,0x83,0xE0,0xFA,
+
+	0xA3,0xE0,0xFB,0xC3,0xEF,0x9B,0xFF,0xEE,
+
+	0x9A,0xFE,0xED,0x24,0x01,0xFD,0xE4,0x3C,
+
+	0xFC,0x12,0x4A,0x78,0x90,0x44,0x03,0xEC,
+
+	0xF0,0xA3,0xED,0xF0,0xD3,0x90,0x43,0x72,
+
+	0xE0,0x9D,0xEC,0x64,0x80,0xF8,0x90,0x43,
+
+	0x71,0xE0,0x64,0x80,0x98,0x50,0x80,0x90,
+
+	0x41,0xEF,0xE0,0xFD,0x7C,0x00,0x90,0x44,
+
+	0x08,0xE0,0x2D,0xFF,0x90,0x44,0x07,0xE0,
+
+	0x3C,0xCF,0x24,0xFF,0xCF,0x34,0xFF,0xFE,
+
+	0x12,0x4A,0x78,0xEC,0xF0,0xA3,0xED,0xF0,
+
+	0xA3,0xE0,0xFF,0xA3,0xE0,0xA3,0xCF,0xF0,
+
+	0xA3,0xEF,0xF0,0x90,0x44,0x08,0xE0,0x25,
+
+	0xE0,0xFF,0x90,0x44,0x07,0xE0,0x33,0xFE,
+
+	0x74,0x58,0x2F,0xF5,0x82,0x74,0x43,0x3E,
+
+	0xF5,0x83,0xE0,0xFE,0xA3,0xE0,0xFF,0x90,
+
+	0x43,0x66,0xE0,0x25,0xE0,0x24,0x58,0xF5,
+
+	0x82,0xE4,0x34,0x43,0xF5,0x83,0xE0,0xFC,
+
+	0xA3,0xE0,0xFD,0x90,0x43,0x61,0xE0,0xFA,
+
+	0xA3,0xE0,0xFB,0xED,0x2B,0xFD,0xEC,0x3A,
+
+	0xCD,0xC3,0x9F,0xFF,0xED,0x9E,0xFE,0xEB,
+
+	0x24,0x01,0xFD,0xE4,0x3A,0xFC,0x12,0x4A,
+
+	0x78,0x90,0x44,0x09,0xEC,0xF0,0xA3,0xED,
+
+	0xF0,0xD3,0x90,0x43,0x72,0xE0,0x9D,0xEC,
+
+	0x64,0x80,0xF8,0x90,0x43,0x71,0xE0,0x64,
+
+	0x80,0x98,0x40,0x03,0x02,0x45,0xF0,0x90,
+
+	0x44,0x05,0xE0,0xFE,0xA3,0xE0,0xFF,0x90,
+
+	0x44,0x0B,0xE0,0xFC,0xA3,0xE0,0xFD,0x9F,
+
+	0xEE,0x64,0x80,0xF8,0xEC,0x64,0x80,0x98,
+
+	0x40,0x08,0xA3,0xEC,0xF0,0xA3,0xED,0xF0,
+
+	0x80,0x08,0x90,0x44,0x0D,0xEE,0xF0,0xA3,
+
+	0xEF,0xF0,0x90,0x44,0x03,0xE0,0xFE,0xA3,
+
+	0xE0,0xFF,0x90,0x44,0x09,0xE0,0xFC,0xA3,
+
+	0xE0,0xFD,0xC3,0x9F,0xEE,0x64,0x80,0xF8,
+
+	0xEC,0x64,0x80,0x98,0x50,0x2B,0x90,0x44,
+
+	0x0F,0xEC,0xF0,0xA3,0xED,0xF0,0x90,0x41,
+
+	0xEF,0xE0,0xFD,0x7C,0x00,0x90,0x44,0x08,
+
+	0xE0,0x2D,0xFF,0x90,0x44,0x07,0xE0,0x3C,
+
+	0xCF,0x24,0xFF,0xCF,0x34,0xFF,0xFE,0x12,
+
+	0x4A,0x78,0xEC,0xF0,0xA3,0xED,0xF0,0x80,
+
+	0x24,0x90,0x44,0x03,0xE0,0xFF,0xA3,0xE0,
+
+	0x90,0x44,0x0F,0xCF,0xF0,0xA3,0xEF,0xF0,
+
+	0x90,0x44,0x02,0xE0,0x04,0xFF,0x90,0x41,
+
+	0xEF,0xE0,0xFE,0x2F,0x8E,0xF0,0x84,0x90,
+
+	0x44,0x02,0xE5,0xF0,0xF0,0x90,0x44,0x0D,
+
+	0xE0,0xFE,0xA3,0xE0,0xFF,0xC3,0x90,0x44,
+
+	0x10,0xE0,0x9F,0xFF,0x90,0x44,0x0F,0xE0,
+
+	0x9E,0x90,0x44,0x11,0xF0,0xA3,0xEF,0xF0,
+
+	0xE4,0xA3,0xF0,0xA3,0xF0,0xA3,0xF0,0x90,
+
+	0x44,0x01,0xF0,0x90,0x43,0x69,0xE0,0x75,
+
+	0xF0,0x04,0xA4,0xFF,0xC3,0x90,0x44,0x12,
+
+	0xE0,0x9F,0xE5,0xF0,0x64,0x80,0xF8,0x90,
+
+	0x44,0x11,0xE0,0x64,0x80,0x98,0x40,0x03,
+
+	0x02,0x49,0x21,0x90,0x44,0x13,0xE0,0x60,
+
+	0x03,0x02,0x49,0x21,0x90,0x44,0x01,0xE0,
+
+	0x94,0x14,0x40,0x17,0x90,0xF5,0xE7,0xE4,
+
+	0xF0,0x90,0xF5,0xE1,0xF0,0xF5,0x13,0x7B,
+
+	0x01,0x7A,0x44,0x79,0x6A,0x7D,0x01,0xFC,
+
+	0x12,0xA1,0x83,0x90,0x44,0x01,0xE0,0x04,
+
+	0xF0,0x90,0x44,0x0F,0xE0,0xFF,0xA3,0xE0,
+
+	0x90,0x44,0x0D,0xCF,0xF0,0xA3,0xEF,0xF0,
+
+	0x90,0x44,0x02,0xE0,0x25,0xE0,0x24,0x58,
+
+	0xF5,0x82,0xE4,0x34,0x43,0xF5,0x83,0xE0,
+
+	0xFE,0xA3,0xE0,0xFF,0x90,0x43,0x61,0xE0,
+
+	0xFC,0xA3,0xE0,0xFD,0xEF,0x2D,0xFF,0xEE,
+
+	0x3C,0xFE,0x90,0x43,0x66,0xE0,0x25,0xE0,
+
+	0x24,0x58,0xF5,0x82,0xE4,0x34,0x43,0xF5,
+
+	0x83,0xE0,0xFA,0xA3,0xE0,0xFB,0xC3,0xEF,
+
+	0x9B,0xFF,0xEE,0x9A,0xFE,0xED,0x24,0x01,
+
+	0xFD,0xE4,0x3C,0xFC,0x12,0x4A,0x78,0x90,
+
+	0x44,0x03,0xEC,0xF0,0xA3,0xED,0xF0,0x90,
+
+	0x44,0x08,0xE0,0x25,0xE0,0xFF,0x90,0x44,
+
+	0x07,0xE0,0x33,0xFE,0x74,0x58,0x2F,0xF5,
+
+	0x82,0x74,0x43,0x3E,0xF5,0x83,0xE0,0xFE,
+
+	0xA3,0xE0,0xFF,0x90,0x43,0x66,0xE0,0x25,
+
+	0xE0,0x24,0x58,0xF5,0x82,0xE4,0x34,0x43,
+
+	0xF5,0x83,0xE0,0xFC,0xA3,0xE0,0xFD,0x90,
+
+	0x43,0x61,0xE0,0xFA,0xA3,0xE0,0xFB,0xED,
+
+	0x2B,0xFD,0xEC,0x3A,0xCD,0xC3,0x9F,0xFF,
+
+	0xED,0x9E,0xFE,0xEB,0x24,0x01,0xFD,0xE4,
+
+	0x3A,0xFC,0x12,0x4A,0x78,0x90,0x44,0x09,
+
+	0xEC,0xF0,0xA3,0xED,0xF0,0x90,0x44,0x03,
+
+	0xE0,0xFE,0xA3,0xE0,0xFF,0xC3,0x9D,0xEC,
+
+	0x64,0x80,0xF8,0xEE,0x64,0x80,0x98,0x50,
+
+	0x3F,0x90,0x44,0x0F,0xEE,0xF0,0xA3,0xEF,
+
+	0xF0,0x90,0x44,0x15,0xE0,0x60,0x03,0x02,
+
+	0x48,0xEE,0x90,0x43,0x66,0xE0,0xFF,0x90,
+
+	0x44,0x02,0xE0,0xFE,0xB5,0x07,0x04,0x7F,
+
+	0x01,0x80,0x02,0x7F,0x00,0x90,0x44,0x15,
+
+	0xEF,0xF0,0x70,0x69,0xEE,0x04,0xFF,0x90,
+
+	0x41,0xEF,0xE0,0xFE,0x2F,0x8E,0xF0,0x84,
+
+	0x90,0x44,0x02,0xE5,0xF0,0xF0,0x80,0x55,
+
+	0x90,0x44,0x09,0xE0,0xFF,0xA3,0xE0,0x90,
+
+	0x44,0x0F,0xCF,0xF0,0xA3,0xEF,0xF0,0x90,
+
+	0x44,0x14,0xE0,0x70,0x40,0x90,0x43,0x66,
+
+	0xE0,0xFF,0x7E,0x00,0x90,0x44,0x07,0xE0,
+
+	0xFA,0xA3,0xE0,0xFB,0xB5,0x07,0x08,0xEE,
+
+	0xB5,0x02,0x04,0x7F,0x01,0x80,0x02,0x7F,
+
+	0x00,0x90,0x44,0x14,0xEF,0xF0,0x70,0x1D,
+
+	0x90,0x41,0xEF,0xE0,0xFD,0x7C,0x00,0x2B,
+
+	0xFF,0xEC,0x3A,0xCF,0x24,0xFF,0xCF,0x34,
+
+	0xFF,0xFE,0x12,0x4A,0x78,0x90,0x44,0x07,
+
+	0xEC,0xF0,0xA3,0xED,0xF0,0x90,0x44,0x0D,
+
+	0xE0,0xFE,0xA3,0xE0,0xFF,0xC3,0x90,0x44,
+
+	0x10,0xE0,0x9F,0xFF,0x90,0x44,0x0F,0xE0,
+
+	0x9E,0x90,0x44,0x11,0xF0,0xA3,0xEF,0xF0,
+
+	0x90,0x44,0x14,0xE0,0x60,0x08,0xA3,0xE0,
+
+	0x60,0x04,0x7F,0x01,0x80,0x02,0x7F,0x00,
+
+	0x90,0x44,0x13,0xEF,0xF0,0x02,0x47,0x44,
+
+	0x90,0x44,0x13,0xE0,0x60,0x0F,0x90,0x43,
+
+	0x4D,0x74,0x07,0xF0,0x90,0x43,0x6E,0x74,
+
+	0x01,0xF0,0x02,0x49,0xDB,0x90,0x43,0x69,
+
+	0xE0,0xF9,0x25,0xE0,0xFF,0xE4,0x33,0xFE,
+
+	0x90,0x43,0x71,0xE0,0xFC,0xA3,0xE0,0xFD,
+
+	0x90,0x44,0x0F,0xE0,0xFA,0xA3,0xE0,0xFB,
+
+	0xC3,0x9D,0xFD,0xEA,0x9C,0xFC,0xC3,0xED,
+
+	0x9F,0xEE,0x64,0x80,0xF8,0xEC,0x64,0x80,
+
+	0x98,0x50,0x22,0xE9,0x75,0xF0,0x02,0xA4,
+
+	0xFF,0x90,0x43,0x72,0xE0,0x2F,0xFF,0x90,
+
+	0x43,0x71,0xE0,0x35,0xF0,0xFE,0xC3,0xEB,
+
+	0x9F,0xFF,0xEA,0x9E,0x90,0x43,0x67,0xF0,
+
+	0xA3,0xEF,0xF0,0x80,0x55,0xE9,0x25,0xE0,
+
+	0xFF,0xE4,0x33,0xFE,0x90,0x44,0x0D,0xE0,
+
+	0xFC,0xA3,0xE0,0xFD,0x90,0x43,0x71,0xE0,
+
+	0xFA,0xA3,0xE0,0xFB,0xC3,0x9D,0xFD,0xEA,
+
+	0x9C,0xFC,0xC3,0xED,0x9F,0xEE,0x64,0x80,
+
+	0xF8,0xEC,0x64,0x80,0x98,0x50,0x24,0xE9,
+
+	0x25,0xE0,0xFF,0xE4,0x33,0xFE,0xEB,0x2F,
+
+	0xFF,0xEA,0x3E,0xFE,0x90,0x44,0x0D,0xE0,
+
+	0xFC,0xA3,0xE0,0xFD,0xC3,0xEF,0x9D,0xFF,
+
+	0xEE,0x9C,0x90,0x43,0x67,0xF0,0xA3,0xEF,
+
+	0xF0,0x80,0x07,0xE4,0x90,0x43,0x67,0xF0,
+
+	0xA3,0xF0,0x90,0x43,0x6E,0x74,0x03,0xF0,
+
+	0x90,0xF5,0xE6,0xF0,0x90,0x43,0x67,0xE0,
+
+	0xA2,0xE7,0x13,0xF0,0xA3,0xE0,0x13,0xF0,
+
+	0x90,0x43,0x4D,0x74,0x07,0xF0,0x22,0xBB,
+
+	0x01,0x06,0x89,0x82,0x8A,0x83,0xE0,0x22,
+
+	0x50,0x02,0xE7,0x22,0xBB,0xFE,0x02,0xE3,
+
+	0x22,0x89,0x82,0x8A,0x83,0xE4,0x93,0x22,
+
+	0xEF,0x8D,0xF0,0xA4,0xA8,0xF0,0xCF,0x8C,
+
+	0xF0,0xA4,0x28,0xCE,0x8D,0xF0,0xA4,0x2E,
+
+	0xFE,0x22,0xBC,0x00,0x0B,0xBE,0x00,0x29,
+
+	0xEF,0x8D,0xF0,0x84,0xFF,0xAD,0xF0,0x22,
+
+	0xE4,0xCC,0xF8,0x75,0xF0,0x08,0xEF,0x2F,
+
+	0xFF,0xEE,0x33,0xFE,0xEC,0x33,0xFC,0xEE,
+
+	0x9D,0xEC,0x98,0x40,0x05,0xFC,0xEE,0x9D,
+
+	0xFE,0x0F,0xD5,0xF0,0xE9,0xE4,0xCE,0xFD,
+
+	0x22,0xED,0xF8,0xF5,0xF0,0xEE,0x84,0x20,
+
+	0xD2,0x1C,0xFE,0xAD,0xF0,0x75,0xF0,0x08,
+
+	0xEF,0x2F,0xFF,0xED,0x33,0xFD,0x40,0x07,
+
+	0x98,0x50,0x06,0xD5,0xF0,0xF2,0x22,0xC3,
+
+	0x98,0xFD,0x0F,0xD5,0xF0,0xEA,0x22,0xC2,
+
+	0xD5,0xEC,0x30,0xE7,0x09,0xB2,0xD5,0xE4,
+
+	0xC3,0x9D,0xFD,0xE4,0x9C,0xFC,0xEE,0x30,
+
+	0xE7,0x15,0xB2,0xD5,0xE4,0xC3,0x9F,0xFF,
+
+	0xE4,0x9E,0xFE,0x12,0x4A,0x23,0xC3,0xE4,
+
+	0x9D,0xFD,0xE4,0x9C,0xFC,0x80,0x03,0x12,
+
+	0x4A,0x23,0x30,0xD5,0x07,0xC3,0xE4,0x9F,
+
+	0xFF,0xE4,0x9E,0xFE,0x22,0xE8,0x8F,0xF0,
+
+	0xA4,0xCC,0x8B,0xF0,0xA4,0x2C,0xFC,0xE9,
+
+	0x8E,0xF0,0xA4,0x2C,0xFC,0x8A,0xF0,0xED,
+
+	0xA4,0x2C,0xFC,0xEA,0x8E,0xF0,0xA4,0xCD,
+
+	0xA8,0xF0,0x8B,0xF0,0xA4,0x2D,0xCC,0x38,
+
+	0x25,0xF0,0xFD,0xE9,0x8F,0xF0,0xA4,0x2C,
+
+	0xCD,0x35,0xF0,0xFC,0xEB,0x8E,0xF0,0xA4,
+
+	0xFE,0xA9,0xF0,0xEB,0x8F,0xF0,0xA4,0xCF,
+
+	0xC5,0xF0,0x2E,0xCD,0x39,0xFE,0xE4,0x3C,
+
+	0xFC,0xEA,0xA4,0x2D,0xCE,0x35,0xF0,0xFD,
+
+	0xE4,0x3C,0xFC,0x22,0xC3,0xE4,0x9F,0xFF,
+
+	0xE4,0x9E,0xFE,0xE4,0x9D,0xFD,0xE4,0x9C,
+
+	0xFC,0x22,0xEB,0x9F,0xF5,0xF0,0xEA,0x9E,
+
+	0x42,0xF0,0xE9,0x9D,0x42,0xF0,0xEC,0x64,
+
+	0x80,0xC8,0x64,0x80,0x98,0x45,0xF0,0x22,
+
+	0xEB,0x9F,0xF5,0xF0,0xEA,0x9E,0x42,0xF0,
+
+	0xE9,0x9D,0x42,0xF0,0xE8,0x9C,0x45,0xF0,
+
+	0x22,0xE8,0x60,0x0F,0xEC,0xC3,0x13,0xFC,
+
+	0xED,0x13,0xFD,0xEE,0x13,0xFE,0xEF,0x13,
+
+	0xFF,0xD8,0xF1,0x22,0xE8,0x60,0x10,0xEC,
+
+	0xA2,0xE7,0x13,0xFC,0xED,0x13,0xFD,0xEE,
+
+	0x13,0xFE,0xEF,0x13,0xFF,0xD8,0xF0,0x22,
+
+	0xE8,0x60,0x0F,0xEF,0xC3,0x33,0xFF,0xEE,
+
+	0x33,0xFE,0xED,0x33,0xFD,0xEC,0x33,0xFC,
+
+	0xD8,0xF1,0x22,0xEC,0xF0,0xA3,0xED,0xF0,
+
+	0xA3,0xEE,0xF0,0xA3,0xEF,0xF0,0x22,0xA8,
+
+	0x82,0x85,0x83,0xF0,0xD0,0x83,0xD0,0x82,
+
+	0x12,0x4B,0x8F,0x12,0x4B,0x8F,0x12,0x4B,
+
+	0x8F,0x12,0x4B,0x8F,0xE4,0x73,0xE4,0x93,
+
+	0xA3,0xC5,0x83,0xC5,0xF0,0xC5,0x83,0xC8,
+
+	0xC5,0x82,0xC8,0xF0,0xA3,0xC5,0x83,0xC5,
+
+	0xF0,0xC5,0x83,0xC8,0xC5,0x82,0xC8,0x22,
+
+	0x8A,0x83,0x89,0x82,0xE4,0x73,0xBB,0x01,
+
+	0x0C,0xE5,0x82,0x29,0xF5,0x82,0xE5,0x83,
+
+	0x3A,0xF5,0x83,0xE0,0x22,0x50,0x06,0xE9,
+
+	0x25,0x82,0xF8,0xE6,0x22,0xBB,0xFE,0x06,
+
+	0xE9,0x25,0x82,0xF8,0xE2,0x22,0xE5,0x82,
+
+	0x29,0xF5,0x82,0xE5,0x83,0x3A,0xF5,0x83,
+
+	0xE4,0x93,0x22,0xF8,0xBB,0x01,0x0D,0xE5,
+
+	0x82,0x29,0xF5,0x82,0xE5,0x83,0x3A,0xF5,
+
+	0x83,0xE8,0xF0,0x22,0x50,0x06,0xE9,0x25,
+
+	0x82,0xC8,0xF6,0x22,0xBB,0xFE,0x05,0xE9,
+
+	0x25,0x82,0xC8,0xF2,0x22,0xBB,0x01,0x0A,
+
+	0x89,0x82,0x8A,0x83,0xE0,0xF5,0xF0,0xA3,
+
+	0xE0,0x22,0x50,0x06,0x87,0xF0,0x09,0xE7,
+
+	0x19,0x22,0xBB,0xFE,0x07,0xE3,0xF5,0xF0,
+
+	0x09,0xE3,0x19,0x22,0x89,0x82,0x8A,0x83,
+
+	0xE4,0x93,0xF5,0xF0,0x74,0x01,0x93,0x22,
+
+	0xBB,0x01,0x10,0xE5,0x82,0x29,0xF5,0x82,
+
+	0xE5,0x83,0x3A,0xF5,0x83,0xE0,0xF5,0xF0,
+
+	0xA3,0xE0,0x22,0x50,0x09,0xE9,0x25,0x82,
+
+	0xF8,0x86,0xF0,0x08,0xE6,0x22,0xBB,0xFE,
+
+	0x0A,0xE9,0x25,0x82,0xF8,0xE2,0xF5,0xF0,
+
+	0x08,0xE2,0x22,0xE5,0x83,0x2A,0xF5,0x83,
+
+	0xE9,0x93,0xF5,0xF0,0xA3,0xE9,0x93,0x22,
+
+	0xBB,0x01,0x0A,0x89,0x82,0x8A,0x83,0xF0,
+
+	0xE5,0xF0,0xA3,0xF0,0x22,0x50,0x06,0xF7,
+
+	0x09,0xA7,0xF0,0x19,0x22,0xBB,0xFE,0x06,
+
+	0xF3,0xE5,0xF0,0x09,0xF3,0x19,0x22,0xF8,
+
+	0xBB,0x01,0x11,0xE5,0x82,0x29,0xF5,0x82,
+
+	0xE5,0x83,0x3A,0xF5,0x83,0xE8,0xF0,0xE5,
+
+	0xF0,0xA3,0xF0,0x22,0x50,0x09,0xE9,0x25,
+
+	0x82,0xC8,0xF6,0x08,0xA6,0xF0,0x22,0xBB,
+
+	0xFE,0x09,0xE9,0x25,0x82,0xC8,0xF2,0xE5,
+
+	0xF0,0x08,0xF2,0x22,0x75,0xF0,0x08,0x75,
+
+	0x82,0x00,0xEF,0x2F,0xFF,0xEE,0x33,0xFE,
+
+	0xCD,0x33,0xCD,0xCC,0x33,0xCC,0xC5,0x82,
+
+	0x33,0xC5,0x82,0x9B,0xED,0x9A,0xEC,0x99,
+
+	0xE5,0x82,0x98,0x40,0x0C,0xF5,0x82,0xEE,
+
+	0x9B,0xFE,0xED,0x9A,0xFD,0xEC,0x99,0xFC,
+
+	0x0F,0xD5,0xF0,0xD6,0xE4,0xCE,0xFB,0xE4,
+
+	0xCD,0xFA,0xE4,0xCC,0xF9,0xA8,0x82,0x22,
+
+	0xB8,0x00,0xC1,0xB9,0x00,0x59,0xBA,0x00,
+
+	0x2D,0xEC,0x8B,0xF0,0x84,0xCF,0xCE,0xCD,
+
+	0xFC,0xE5,0xF0,0xCB,0xF9,0x78,0x18,0xEF,
+
+	0x2F,0xFF,0xEE,0x33,0xFE,0xED,0x33,0xFD,
+
+	0xEC,0x33,0xFC,0xEB,0x33,0xFB,0x10,0xD7,
+
+	0x03,0x99,0x40,0x04,0xEB,0x99,0xFB,0x0F,
+
+	0xD8,0xE5,0xE4,0xF9,0xFA,0x22,0x78,0x18,
+
+	0xEF,0x2F,0xFF,0xEE,0x33,0xFE,0xED,0x33,
+
+	0xFD,0xEC,0x33,0xFC,0xC9,0x33,0xC9,0x10,
+
+	0xD7,0x05,0x9B,0xE9,0x9A,0x40,0x07,0xEC,
+
+	0x9B,0xFC,0xE9,0x9A,0xF9,0x0F,0xD8,0xE0,
+
+	0xE4,0xC9,0xFA,0xE4,0xCC,0xFB,0x22,0x75,
+
+	0xF0,0x10,0xEF,0x2F,0xFF,0xEE,0x33,0xFE,
+
+	0xED,0x33,0xFD,0xCC,0x33,0xCC,0xC8,0x33,
+
+	0xC8,0x10,0xD7,0x07,0x9B,0xEC,0x9A,0xE8,
+
+	0x99,0x40,0x0A,0xED,0x9B,0xFD,0xEC,0x9A,
+
+	0xFC,0xE8,0x99,0xF8,0x0F,0xD5,0xF0,0xDA,
+
+	0xE4,0xCD,0xFB,0xE4,0xCC,0xFA,0xE4,0xC8,
+
+	0xF9,0x22,0x90,0x44,0x7E,0xEF,0xF0,0xA9,
+
+	0x05,0xE4,0x90,0x44,0x84,0xF0,0xFB,0x90,
+
+	0x43,0x60,0xE0,0xFD,0xEB,0xC3,0x9D,0x50,
+
+	0x4F,0x90,0xF5,0xF1,0xE0,0xFF,0xEB,0x25,
+
+	0xE0,0x24,0x50,0xF5,0x82,0xE4,0x34,0x43,
+
+	0xF5,0x83,0xEF,0xF0,0x90,0xF5,0xF0,0xE0,
+
+	0xFF,0xEB,0x25,0xE0,0x24,0x51,0xF5,0x82,
+
+	0xE4,0x34,0x43,0xF5,0x83,0xEF,0xF0,0x90,
+
+	0xF5,0xF1,0xE0,0xFF,0xEB,0x25,0xE0,0x24,
+
+	0x58,0xF5,0x82,0xE4,0x34,0x43,0xF5,0x83,
+
+	0xEF,0xF0,0x90,0xF5,0xF0,0xE0,0xFF,0xEB,
+
+	0x25,0xE0,0x24,0x59,0xF5,0x82,0xE4,0x34,
+
+	0x43,0xF5,0x83,0xEF,0xF0,0x0B,0x80,0xA7,
+
+	0x90,0x41,0xEF,0xED,0xF0,0x90,0x43,0x50,
+
+	0xE0,0xFE,0xA3,0xE0,0xFF,0xEE,0xC3,0x13,
+
+	0xFE,0xEF,0x13,0xFF,0x90,0x44,0x7F,0xEE,
+
+	0xF0,0xA3,0xEF,0xF0,0x7A,0x01,0x90,0x41,
+
+	0xEF,0xE0,0xFF,0xEA,0xC3,0x9F,0x50,0x4E,
+
+	0xEA,0x25,0xE0,0x24,0x50,0xF5,0x82,0xE4,
+
+	0x34,0x43,0xF5,0x83,0xE0,0xFE,0xA3,0xE0,
+
+	0x78,0x02,0xCE,0xC3,0x13,0xCE,0x13,0xD8,
+
+	0xF9,0xFD,0xAC,0x06,0xEA,0x25,0xE0,0x24,
+
+	0x50,0xF5,0x82,0xE4,0x34,0x43,0xF5,0x83,
+
+	0xE0,0xFE,0xA3,0xE0,0xFF,0xEE,0xC3,0x13,
+
+	0xFE,0xEF,0x13,0x2D,0xFF,0xEE,0x3C,0xFE,
+
+	0x90,0x44,0x7F,0xE0,0xFC,0xA3,0xE0,0xC3,
+
+	0x9F,0xEC,0x9E,0x50,0x06,0x90,0x43,0x4C,
+
+	0x74,0x01,0xF0,0x0A,0x80,0xA8,0x90,0x43,
+
+	0x78,0xE0,0xFE,0x70,0x14,0x90,0x41,0xEF,
+
+	0xE0,0x64,0x01,0x70,0x31,0x90,0x43,0x78,
+
+	0x04,0xF0,0x90,0xF5,0xE2,0xE9,0xF0,0x80,
+
+	0x25,0xEE,0xB4,0x01,0x17,0x90,0x41,0xEF,
+
+	0xE0,0xB4,0x01,0x08,0x90,0x43,0x78,0x74,
+
+	0x03,0xF0,0x80,0x12,0x90,0x43,0x78,0x74,
+
+	0x02,0xF0,0x80,0x0A,0x90,0x43,0x78,0xE0,
+
+	0xB4,0x02,0x03,0x74,0x03,0xF0,0x90,0x43,
+
+	0x78,0xE0,0xB4,0x03,0x0F,0x90,0x42,0x0F,
+
+	0xE0,0x14,0x90,0x43,0x77,0xF0,0x90,0x41,
+
+	0xEF,0x74,0x01,0xF0,0x90,0x44,0x7E,0xE0,
+
+	0x60,0x03,0x02,0x50,0xDD,0x7A,0x01,0x90,
+
+	0x43,0x60,0xE0,0xFF,0xEA,0xC3,0x9F,0x50,
+
+	0x34,0xEA,0x25,0xE0,0x24,0x58,0xF5,0x82,
+
+	0xE4,0x34,0x43,0xF5,0x83,0xE0,0xFE,0xA3,
+
+	0xE0,0xFF,0x90,0x43,0x58,0xE0,0xFC,0xA3,
+
+	0xE0,0xFD,0xC3,0xEF,0x9D,0xFF,0xEE,0x9C,
+
+	0xFE,0xEA,0x25,0xE0,0x24,0x77,0xF5,0x82,
+
+	0xE4,0x34,0x43,0xF5,0x83,0xEE,0xF0,0xA3,
+
+	0xEF,0xF0,0x0A,0x80,0xC2,0x90,0x43,0x8A,
+
+	0xE0,0xFC,0x70,0x39,0xFA,0x90,0x43,0x60,
+
+	0xE0,0xFF,0xEA,0xC3,0x9F,0x50,0x25,0xEA,
+
+	0x25,0xE0,0x24,0x79,0xF5,0x82,0xE4,0x34,
+
+	0x43,0xF5,0x83,0xE0,0xFE,0xA3,0xE0,0xFF,
+
+	0xEA,0x25,0xE0,0x24,0x81,0xF5,0x82,0xE4,
+
+	0x34,0x43,0xF5,0x83,0xEE,0xF0,0xA3,0xEF,
+
+	0xF0,0x0A,0x80,0xD1,0x90,0x41,0xEF,0xE0,
+
+	0x90,0x43,0x8A,0xF0,0x22,0xEC,0x64,0x01,
+
+	0x70,0x03,0x02,0x50,0x96,0x90,0x44,0x83,
+
+	0x74,0x01,0xF0,0x90,0x44,0x82,0xF0,0xE4,
+
+	0xFA,0xF9,0xE9,0x25,0xE0,0x24,0x81,0xF5,
+
+	0x82,0xE4,0x34,0x43,0xF5,0x83,0xE0,0xFE,
+
+	0xA3,0xE0,0xFF,0xEA,0x25,0xE0,0x24,0x79,
+
+	0xF5,0x82,0xE4,0x34,0x43,0xF5,0x83,0xE0,
+
+	0xFC,0xA3,0xE0,0xC3,0x9F,0xFF,0xEC,0x9E,
+
+	0xFE,0xC3,0x64,0x80,0x94,0x80,0x50,0x24,
+
+	0xC3,0xE4,0x9F,0xFF,0xE4,0x9E,0xFE,0x90,
+
+	0x43,0x60,0xE0,0x24,0xFE,0xFD,0xEA,0xC3,
+
+	0x9D,0x50,0x03,0x0A,0x80,0x06,0x90,0x44,
+
+	0x84,0x74,0x01,0xF0,0x90,0x44,0x81,0x74,
+
+	0x01,0xF0,0x80,0x1A,0xE4,0x90,0x44,0x81,
+
+	0xF0,0x90,0x43,0x8A,0xE0,0x24,0xFE,0xFD,
+
+	0xE9,0xC3,0x9D,0x50,0x03,0x09,0x80,0x06,
+
+	0x90,0x44,0x84,0x74,0x01,0xF0,0x90,0x42,
+
+	0x12,0xE0,0xFD,0xC3,0xEF,0x9D,0x74,0x80,
+
+	0xF8,0x6E,0x98,0x40,0x2A,0x90,0x43,0x50,
+
+	0xE0,0xFE,0xA3,0xE0,0xFF,0xEE,0x13,0xFE,
+
+	0xEF,0x13,0xFF,0x90,0x44,0x83,0xE0,0x25,
+
+	0xE0,0x24,0x50,0xF5,0x82,0xE4,0x34,0x43,
+
+	0xF5,0x83,0xE0,0xFC,0xA3,0xE0,0xD3,0x9F,
+
+	0xEC,0x9E,0x50,0x03,0x02,0x50,0x75,0x90,
+
+	0x44,0x83,0xE0,0xFC,0x25,0xE0,0x24,0x58,
+
+	0xF5,0x82,0xE4,0x34,0x43,0xF5,0x83,0xE0,
+
+	0xFE,0xA3,0xE0,0xFF,0x90,0x44,0x82,0xE0,
+
+	0xFD,0x25,0xE0,0x24,0x58,0xF5,0x82,0xE4,
+
+	0x34,0x43,0xF5,0x83,0xEE,0xF0,0xA3,0xEF,
+
+	0xF0,0xEC,0x25,0xE0,0x24,0x50,0xF5,0x82,
+
+	0xE4,0x34,0x43,0xF5,0x83,0xE0,0xFE,0xA3,
+
+	0xE0,0xFF,0xED,0x25,0xE0,0x24,0x50,0xF5,
+
+	0x82,0xE4,0x34,0x43,0xF5,0x83,0xEE,0xF0,
+
+	0xA3,0xEF,0xF0,0x90,0x44,0x82,0xE0,0x04,
+
+	0xF0,0x90,0x44,0x81,0xE0,0xB4,0x01,0x17,
+
+	0x90,0x43,0x8A,0xE0,0x24,0xFE,0xFF,0xE9,
+
+	0xC3,0x9F,0x50,0x03,0x09,0x80,0x1D,0x90,
+
+	0x44,0x84,0x74,0x01,0xF0,0x80,0x15,0x90,
+
+	0x43,0x60,0xE0,0x24,0xFE,0xFF,0xEA,0xC3,
+
+	0x9F,0x50,0x03,0x0A,0x80,0x06,0x90,0x44,
+
+	0x84,0x74,0x01,0xF0,0x90,0x44,0x82,0xE0,
+
+	0x90,0x41,0xEF,0xF0,0xEA,0x04,0x90,0x44,
+
+	0x83,0xF0,0xA3,0xE0,0x64,0x01,0x60,0x03,
+
+	0x02,0x4F,0x4B,0x90,0x41,0xEF,0xE0,0x90,
+
+	0x43,0x8A,0xF0,0x80,0x06,0x90,0x41,0xEF,
+
+	0x74,0x01,0xF0,0x7B,0x01,0x90,0x43,0x8A,
+
+	0xE0,0x14,0xFF,0xEB,0xC3,0x9F,0x50,0x34,
+
+	0xEB,0x25,0xE0,0x24,0x58,0xF5,0x82,0xE4,
+
+	0x34,0x43,0xF5,0x83,0xE0,0xFE,0xA3,0xE0,
+
+	0xFF,0x90,0x43,0x58,0xE0,0xFC,0xA3,0xE0,
+
+	0xFD,0xC3,0xEF,0x9D,0xFF,0xEE,0x9C,0xFE,
+
+	0xEB,0x25,0xE0,0x24,0x7F,0xF5,0x82,0xE4,
+
+	0x34,0x43,0xF5,0x83,0xEE,0xF0,0xA3,0xEF,
+
+	0xF0,0x0B,0x80,0xC1,0x22,0x90,0xF9,0x00,
+
+	0xE0,0x70,0x0A,0x90,0x42,0x72,0xF0,0xA3,
+
+	0x74,0x32,0xF0,0x80,0x1B,0x90,0xF9,0x00,
+
+	0xE0,0xB4,0x01,0x0B,0x90,0x42,0x72,0xE4,
+
+	0xF0,0xA3,0x74,0xC8,0xF0,0x80,0x09,0x90,
+
+	0x42,0x72,0xE4,0xF0,0xA3,0x74,0x64,0xF0,
+
+	0x90,0x41,0xE2,0x74,0x40,0xF0,0x12,0x5A,
+
+	0x62,0x7F,0x01,0x12,0xAE,0x43,0x90,0x42,
+
+	0x72,0xE4,0xF0,0xA3,0x74,0x1E,0xF0,0x90,
+
+	0x41,0xE2,0x74,0x50,0xF0,0x12,0x5A,0x62,
+
+	0x90,0xF4,0x0C,0xE0,0x60,0x5A,0x90,0xF1,
+
+	0xEB,0x74,0x01,0xF0,0xE4,0xF0,0x90,0xF9,
+
+	0x00,0xE0,0x70,0x0A,0x90,0x42,0x72,0xF0,
+
+	0xA3,0x74,0x96,0xF0,0x80,0x1D,0x90,0xF9,
+
+	0x00,0xE0,0xB4,0x01,0x0C,0x90,0x42,0x72,
+
+	0x74,0x02,0xF0,0xA3,0x74,0x58,0xF0,0x80,
+
+	0x0A,0x90,0x42,0x72,0x74,0x01,0xF0,0xA3,
+
+	0x74,0x2C,0xF0,0x7F,0x01,0x12,0xAE,0x43,
+
+	0x90,0x41,0xE2,0x74,0x60,0xF0,0x12,0x5A,
+
+	0x62,0x90,0x42,0x72,0xE4,0xF0,0xA3,0x74,
+
+	0x1E,0xF0,0x7F,0x01,0x12,0xAE,0x43,0x90,
+
+	0x41,0xE2,0x74,0x70,0xF0,0x12,0x5A,0x62,
+
+	0x90,0xF4,0x0C,0xE0,0x60,0x10,0x90,0x41,
+
+	0xD8,0x74,0x02,0xF0,0x90,0xF2,0x1C,0xF0,
+
+	0xE4,0x90,0x43,0xBB,0xF0,0x22,0x90,0x41,
+
+	0xD8,0x74,0x01,0xF0,0x90,0xF2,0x1C,0xF0,
+
+	0x90,0x43,0xBB,0xF0,0xE4,0x90,0x42,0x6E,
+
+	0xF0,0x90,0xF1,0xB5,0xE0,0x90,0x42,0x6F,
+
+	0xF0,0x90,0xF1,0xB4,0xE0,0x90,0x42,0x70,
+
+	0xF0,0x90,0xF1,0xB3,0xE0,0x90,0x42,0x71,
+
+	0xF0,0x90,0x42,0x6E,0xE0,0xFC,0xA3,0xE0,
+
+	0xFD,0xA3,0xE0,0xFE,0xA3,0xE0,0xFF,0x90,
+
+	0x42,0x60,0xE0,0xF8,0xA3,0xE0,0xF9,0xA3,
+
+	0xE0,0xFA,0xA3,0xE0,0xFB,0xC3,0xEF,0x9B,
+
+	0xFF,0xEE,0x9A,0xFE,0xED,0x99,0xFD,0xEC,
+
+	0x98,0xFC,0x90,0x42,0x6E,0x12,0x4B,0x6C,
+
+	0x7F,0xFF,0x7E,0xFF,0x7D,0x3F,0x7C,0x00,
+
+	0x90,0x42,0x6E,0xE0,0xF8,0xA3,0xE0,0xF9,
+
+	0xA3,0xE0,0xFA,0xA3,0xE0,0xFB,0xD3,0x12,
+
+	0x4B,0x0B,0x40,0x21,0x90,0x42,0x6E,0xE0,
+
+	0xFC,0xA3,0xE0,0xFD,0xA3,0xE0,0xFE,0xA3,
+
+	0xE0,0x24,0x00,0xFF,0xE4,0x3E,0xFE,0xED,
+
+	0x34,0x80,0xFD,0xEC,0x34,0xFF,0xFC,0x90,
+
+	0x42,0x6E,0x12,0x4B,0x6C,0x90,0x42,0x6E,
+
+	0xE0,0xFC,0xA3,0xE0,0xFD,0xA3,0xE0,0xFE,
+
+	0xA3,0xE0,0xFF,0x78,0x09,0x12,0x4B,0x45,
+
+	0x90,0x42,0x6E,0x12,0x4B,0x6C,0x90,0x43,
+
+	0xE1,0xE0,0x60,0x04,0x7F,0x01,0x80,0x02,
+
+	0x7F,0x00,0x90,0x42,0x1F,0xE0,0x5F,0x70,
+
+	0x0F,0x90,0xF1,0x33,0xE0,0x70,0x09,0x90,
+
+	0xF1,0x35,0xE0,0x70,0x03,0x02,0x54,0x10,
+
+	0xE4,0x90,0x42,0x60,0xF0,0xA3,0xF0,0x90,
+
+	0xF1,0x0F,0xE0,0x90,0x42,0x62,0xF0,0x90,
+
+	0xF1,0x0E,0xE0,0x90,0x42,0x63,0xF0,0x90,
+
+	0x42,0x60,0xE0,0xFC,0xA3,0xE0,0xFD,0xA3,
+
+	0xE0,0xFE,0xA3,0xE0,0xFF,0x90,0x42,0x6E,
+
+	0xE0,0xF8,0xA3,0xE0,0xF9,0xA3,0xE0,0xFA,
+
+	0xA3,0xE0,0x2F,0xFF,0xEA,0x3E,0xFE,0xE9,
+
+	0x3D,0xFD,0xE8,0x3C,0xFC,0x90,0x42,0x60,
+
+	0x12,0x4B,0x6C,0xE4,0xFF,0x7E,0x40,0xFD,
+
+	0xFC,0x90,0x42,0x60,0xE0,0xF8,0xA3,0xE0,
+
+	0xF9,0xA3,0xE0,0xFA,0xA3,0xE0,0xFB,0xC3,
+
+	0x12,0x4B,0x0B,0x40,0x24,0x90,0x42,0x60,
+
+	0xE0,0xFC,0xA3,0xE0,0xFD,0xA3,0xE0,0xFE,
+
+	0xA3,0xE0,0x24,0x00,0xFF,0xEE,0x34,0xC0,
+
+	0xFE,0xED,0x34,0xFF,0xFD,0xEC,0x34,0xFF,
+
+	0xFC,0x90,0x42,0x60,0x12,0x4B,0x6C,0x80,
+
+	0x39,0xE4,0xFF,0xFE,0xFD,0xFC,0x90,0x42,
+
+	0x60,0xE0,0xF8,0xA3,0xE0,0xF9,0xA3,0xE0,
+
+	0xFA,0xA3,0xE0,0xFB,0xC3,0x12,0x4B,0x0B,
+
+	0x50,0x20,0x90,0x42,0x60,0xE0,0xFC,0xA3,
+
+	0xE0,0xFD,0xA3,0xE0,0xFE,0xA3,0xE0,0x24,
+
+	0x00,0xFF,0xEE,0x34,0x40,0xFE,0xE4,0x3D,
+
+	0xFD,0xE4,0x3C,0xFC,0x90,0x42,0x60,0x12,
+
+	0x4B,0x6C,0x90,0x42,0x63,0xE0,0x90,0xF1,
+
+	0x0E,0xF0,0x90,0x42,0x62,0xE0,0x90,0xF1,
+
+	0x0F,0xF0,0xE4,0x90,0x42,0x60,0xF0,0xA3,
+
+	0xF0,0x90,0xF1,0x13,0xE0,0x90,0x42,0x62,
+
+	0xF0,0x90,0xF1,0x12,0xE0,0x90,0x42,0x63,
+
+	0xF0,0x90,0x42,0x60,0xE0,0xFC,0xA3,0xE0,
+
+	0xFD,0xA3,0xE0,0xFE,0xA3,0xE0,0xFF,0x90,
+
+	0x42,0x6E,0xE0,0xF8,0xA3,0xE0,0xF9,0xA3,
+
+	0xE0,0xFA,0xA3,0xE0,0x2F,0xFF,0xEA,0x3E,
+
+	0xFE,0xE9,0x3D,0xFD,0xE8,0x3C,0xFC,0x90,
+
+	0x42,0x60,0x12,0x4B,0x6C,0xE4,0xFF,0x7E,
+
+	0x40,0xFD,0xFC,0x90,0x42,0x60,0xE0,0xF8,
+
+	0xA3,0xE0,0xF9,0xA3,0xE0,0xFA,0xA3,0xE0,
+
+	0xFB,0xC3,0x12,0x4B,0x0B,0x40,0x24,0x90,
+
+	0x42,0x60,0xE0,0xFC,0xA3,0xE0,0xFD,0xA3,
+
+	0xE0,0xFE,0xA3,0xE0,0x24,0x00,0xFF,0xEE,
+
+	0x34,0xC0,0xFE,0xED,0x34,0xFF,0xFD,0xEC,
+
+	0x34,0xFF,0xFC,0x90,0x42,0x60,0x12,0x4B,
+
+	0x6C,0x80,0x39,0xE4,0xFF,0xFE,0xFD,0xFC,
+
+	0x90,0x42,0x60,0xE0,0xF8,0xA3,0xE0,0xF9,
+
+	0xA3,0xE0,0xFA,0xA3,0xE0,0xFB,0xC3,0x12,
+
+	0x4B,0x0B,0x50,0x20,0x90,0x42,0x60,0xE0,
+
+	0xFC,0xA3,0xE0,0xFD,0xA3,0xE0,0xFE,0xA3,
+
+	0xE0,0x24,0x00,0xFF,0xEE,0x34,0x40,0xFE,
+
+	0xE4,0x3D,0xFD,0xE4,0x3C,0xFC,0x90,0x42,
+
+	0x60,0x12,0x4B,0x6C,0x90,0x42,0x63,0xE0,
+
+	0x90,0xF1,0x12,0xF0,0x90,0x42,0x62,0xE0,
+
+	0x90,0xF1,0x13,0xF0,0x90,0x43,0xDF,0xE0,
+
+	0x70,0x05,0x90,0xF1,0x0A,0x04,0xF0,0xE4,
+
+	0x90,0x42,0x60,0xF0,0x90,0xF1,0xB5,0xE0,
+
+	0x90,0x42,0x61,0xF0,0x90,0xF1,0xB4,0xE0,
+
+	0x90,0x42,0x62,0xF0,0x90,0xF1,0xB3,0xE0,
+
+	0x90,0x42,0x63,0xF0,0x22,0xE4,0x90,0x43,
+
+	0xEE,0xF0,0x90,0x43,0xE1,0xF0,0x90,0x42,
+
+	0x21,0xE0,0x90,0x44,0x8D,0xF0,0x90,0x42,
+
+	0x22,0xE0,0x90,0x44,0x8C,0xF0,0x90,0xF6,
+
+	0x25,0xE4,0xF0,0x90,0x42,0x20,0xE0,0x90,
+
+	0xF6,0x26,0xF0,0x90,0xF6,0x2B,0x74,0x02,
+
+	0xF0,0xA3,0xF0,0xA3,0xE4,0xF0,0x90,0xF6,
+
+	0x25,0x04,0xF0,0x90,0xF6,0x2F,0xF0,0x90,
+
+	0xF6,0x2F,0xE0,0xB4,0x01,0xF9,0x90,0xF6,
+
+	0x32,0xE0,0x90,0x43,0xF0,0xF0,0x90,0xF6,
+
+	0x33,0xE0,0x90,0x43,0xEF,0xF0,0x90,0x44,
+
+	0x8C,0xE0,0xFE,0xA3,0xE0,0xFF,0xC3,0x90,
+
+	0x43,0xF0,0xE0,0x9F,0x90,0x43,0xEF,0xE0,
+
+	0x9E,0x40,0x03,0x02,0x57,0x34,0x90,0x44,
+
+	0x8C,0xE0,0xFE,0xA3,0xE0,0xFF,0xC3,0x90,
+
+	0x43,0xF0,0xE0,0x9F,0x90,0x43,0xEF,0xE0,
+
+	0x9E,0x50,0x3A,0x90,0xF6,0x2C,0xE0,0xB4,
+
+	0x02,0x05,0x74,0x01,0xF0,0x80,0x0A,0x90,
+
+	0xF6,0x2B,0xE0,0x04,0xF0,0xA3,0x74,0x02,
+
+	0xF0,0x90,0xF6,0x2F,0x74,0x01,0xF0,0x90,
+
+	0xF6,0x2F,0xE0,0xB4,0x01,0xF9,0x90,0xF6,
+
+	0x32,0xE0,0x90,0x43,0xF0,0xF0,0x90,0xF6,
+
+	0x33,0xE0,0x90,0x43,0xEF,0xF0,0x90,0xF6,
+
+	0x2B,0xE0,0xB4,0x0F,0xB1,0x90,0x42,0x23,
+
+	0xE0,0xFF,0x90,0xF6,0x2B,0xE0,0xC3,0x9F,
+
+	0x40,0x04,0x7F,0x01,0x80,0x02,0x7F,0x00,
+
+	0x90,0x43,0xDF,0xEF,0xF0,0x60,0x5C,0x90,
+
+	0xF1,0x2F,0xE4,0xF0,0x90,0xF1,0x34,0x04,
+
+	0xF0,0x90,0xF1,0x37,0x74,0x10,0xF0,0xA3,
+
+	0x74,0x06,0xF0,0x90,0xF1,0x3B,0x74,0x60,
+
+	0xF0,0xA3,0x74,0x1A,0xF0,0x90,0xF1,0x3F,
+
+	0x74,0xC0,0xF0,0xA3,0x74,0x2D,0xF0,0x90,
+
+	0xF1,0x33,0x74,0x01,0xF0,0x90,0xF1,0x36,
+
+	0x74,0x0D,0xF0,0x90,0xF1,0x39,0x74,0x10,
+
+	0xF0,0xA3,0x74,0x18,0xF0,0x90,0xF1,0x3D,
+
+	0x74,0x60,0xF0,0xA3,0x74,0x1B,0xF0,0x90,
+
+	0xF1,0x41,0x74,0x40,0xF0,0xA3,0x74,0x3A,
+
+	0xF0,0x90,0xF1,0x35,0x74,0x01,0xF0,0x90,
+
+	0xF1,0x11,0xF0,0x90,0xF6,0x2B,0xE0,0x14,
+
+	0xF0,0xC2,0xAF,0x90,0xF6,0x2D,0x74,0x01,
+
+	0xF0,0x90,0xF6,0x2F,0xF0,0x90,0xF6,0x2F,
+
+	0xE0,0xB4,0x01,0xF9,0xD2,0xAF,0x90,0xF6,
+
+	0x4C,0xE0,0x90,0x44,0x8F,0xF0,0x90,0xF6,
+
+	0x4D,0xE0,0x90,0x44,0x90,0xF0,0x90,0xF6,
+
+	0x4E,0xE0,0x90,0x44,0x91,0xF0,0x90,0xF6,
+
+	0x4F,0xE0,0x90,0x44,0x92,0xF0,0x90,0x44,
+
+	0x90,0xE0,0xFF,0x90,0x44,0x8F,0xE0,0xFE,
+
+	0x6F,0x60,0x20,0x90,0x44,0x91,0xE0,0xFD,
+
+	0xEE,0x6D,0x60,0x17,0xA3,0xE0,0xFC,0xEE,
+
+	0x6C,0x60,0x10,0xEF,0x6D,0x60,0x0C,0x90,
+
+	0x44,0x90,0xE0,0x6C,0x60,0x05,0xA3,0xE0,
+
+	0xB5,0x04,0x06,0x90,0x43,0xEE,0x74,0x01,
+
+	0xF0,0x90,0x44,0x8E,0x74,0x04,0xF0,0x90,
+
+	0x44,0x8E,0xE0,0xFF,0xC3,0x94,0x06,0x40,
+
+	0x03,0x02,0x57,0x34,0x90,0xF6,0x4C,0xE0,
+
+	0x6F,0x70,0x4B,0x90,0x43,0xEE,0xE0,0xB4,
+
+	0x01,0x21,0x90,0x44,0x8E,0xE0,0xB4,0x05,
+
+	0x1A,0x90,0x43,0xE3,0x74,0xAC,0xF0,0x90,
+
+	0x43,0xE2,0x74,0x0D,0xF0,0x90,0x43,0xE5,
+
+	0x74,0x9F,0xF0,0x90,0x43,0xE4,0x74,0x1A,
+
+	0xF0,0x80,0x20,0x90,0xF6,0x34,0xE0,0x90,
+
+	0x43,0xE3,0xF0,0x90,0xF6,0x35,0xE0,0x90,
+
+	0x43,0xE2,0xF0,0x90,0xF6,0x36,0xE0,0x90,
+
+	0x43,0xE5,0xF0,0x90,0xF6,0x37,0xE0,0x90,
+
+	0x43,0xE4,0xF0,0x12,0x75,0xDF,0x90,0x44,
+
+	0x8E,0xE0,0xFF,0x90,0xF6,0x4D,0xE0,0x6F,
+
+	0x70,0x48,0x90,0x43,0xEE,0xE0,0xB4,0x01,
+
+	0x1E,0xEF,0xB4,0x05,0x1A,0x90,0x43,0xE3,
+
+	0x74,0xAC,0xF0,0x90,0x43,0xE2,0x74,0x0D,
+
+	0xF0,0x90,0x43,0xE5,0x74,0x9F,0xF0,0x90,
+
+	0x43,0xE4,0x74,0x1A,0xF0,0x80,0x20,0x90,
+
+	0xF6,0x3A,0xE0,0x90,0x43,0xE3,0xF0,0x90,
+
+	0xF6,0x3B,0xE0,0x90,0x43,0xE2,0xF0,0x90,
+
+	0xF6,0x3C,0xE0,0x90,0x43,0xE5,0xF0,0x90,
+
+	0xF6,0x3D,0xE0,0x90,0x43,0xE4,0xF0,0x12,
+
+	0x75,0xDF,0x90,0x44,0x8E,0xE0,0xFF,0x90,
+
+	0xF6,0x4E,0xE0,0x6F,0x70,0x48,0x90,0x43,
+
+	0xEE,0xE0,0xB4,0x01,0x1E,0xEF,0xB4,0x05,
+
+	0x1A,0x90,0x43,0xE3,0x74,0xAC,0xF0,0x90,
+
+	0x43,0xE2,0x74,0x0D,0xF0,0x90,0x43,0xE5,
+
+	0x74,0x9F,0xF0,0x90,0x43,0xE4,0x74,0x1A,
+
+	0xF0,0x80,0x20,0x90,0xF6,0x40,0xE0,0x90,
+
+	0x43,0xE3,0xF0,0x90,0xF6,0x41,0xE0,0x90,
+
+	0x43,0xE2,0xF0,0x90,0xF6,0x42,0xE0,0x90,
+
+	0x43,0xE5,0xF0,0x90,0xF6,0x43,0xE0,0x90,
+
+	0x43,0xE4,0xF0,0x12,0x75,0xDF,0x90,0x44,
+
+	0x8E,0xE0,0xFF,0x90,0xF6,0x4F,0xE0,0x6F,
+
+	0x70,0x48,0x90,0x43,0xEE,0xE0,0xB4,0x01,
+
+	0x1E,0xEF,0xB4,0x05,0x1A,0x90,0x43,0xE3,
+
+	0x74,0xAC,0xF0,0x90,0x43,0xE2,0x74,0x0D,
+
+	0xF0,0x90,0x43,0xE5,0x74,0x9F,0xF0,0x90,
+
+	0x43,0xE4,0x74,0x1A,0xF0,0x80,0x20,0x90,
+
+	0xF6,0x46,0xE0,0x90,0x43,0xE3,0xF0,0x90,
+
+	0xF6,0x47,0xE0,0x90,0x43,0xE2,0xF0,0x90,
+
+	0xF6,0x48,0xE0,0x90,0x43,0xE5,0xF0,0x90,
+
+	0xF6,0x49,0xE0,0x90,0x43,0xE4,0xF0,0x12,
+
+	0x75,0xDF,0x90,0x44,0x8E,0xE0,0x04,0xF0,
+
+	0x02,0x55,0xD0,0x90,0xF6,0x25,0xE4,0xF0,
+
+	0x90,0x43,0xDF,0xE0,0x70,0x0D,0x90,0x43,
+
+	0xE1,0xE0,0xB4,0x01,0x06,0x90,0xF1,0x0A,
+
+	0x74,0x01,0xF0,0x7F,0x01,0x12,0xAE,0x43,
+
+	0x22,0x90,0xF4,0xC1,0xE0,0xC3,0x94,0x01,
+
+	0x50,0x03,0x02,0x5A,0x4D,0x90,0x43,0x26,
+
+	0xE0,0x70,0x1E,0x90,0x43,0x12,0x12,0x4B,
+
+	0x78,0x00,0x00,0x00,0x00,0x90,0x43,0x16,
+
+	0x12,0x4B,0x78,0x00,0x00,0x00,0x00,0x90,
+
+	0x43,0x0E,0x12,0x4B,0x78,0x00,0x00,0x00,
+
+	0x00,0x90,0x43,0x25,0xE0,0x25,0xE0,0x24,
+
+	0x36,0xF5,0x82,0xE4,0x34,0x43,0xF5,0x83,
+
+	0xE0,0xFF,0xA3,0xE0,0x90,0x43,0x23,0xCF,
+
+	0xF0,0xA3,0xEF,0xF0,0x90,0xF9,0x00,0xE0,
+
+	0x70,0x19,0x90,0x43,0x23,0xE0,0xFE,0xA3,
+
+	0xE0,0xFF,0x7C,0x06,0x7D,0xA8,0x12,0x4A,
+
+	0x23,0x90,0x43,0x23,0xEC,0xF0,0xA3,0xED,
+
+	0xF0,0x80,0x1E,0x90,0xF9,0x00,0xE0,0xB4,
+
+	0x02,0x17,0x90,0x43,0x23,0xE0,0xFE,0xA3,
+
+	0xE0,0xFF,0x7C,0x0D,0x7D,0x50,0x12,0x4A,
+
+	0x23,0x90,0x43,0x23,0xEC,0xF0,0xA3,0xED,
+
+	0xF0,0x12,0xAC,0x5B,0x12,0x8E,0xE5,0x12,
+
+	0xAD,0x5A,0x90,0x42,0xFE,0xE0,0xFF,0xC4,
+
+	0x13,0x13,0x13,0x54,0x01,0x90,0x44,0xD5,
+
+	0xF0,0xE0,0xB4,0x01,0x31,0x90,0x43,0x12,
+
+	0xE0,0xFC,0xA3,0xE0,0xFD,0xA3,0xE0,0xFE,
+
+	0xA3,0xE0,0xFF,0x90,0x42,0xFE,0xE0,0xF8,
+
+	0xA3,0xE0,0xF9,0xA3,0xE0,0xFA,0xA3,0xE0,
+
+	0xFB,0xC3,0xEF,0x9B,0xFF,0xEE,0x9A,0xFE,
+
+	0xED,0x99,0xFD,0xEC,0x98,0xFC,0x90,0x43,
+
+	0x12,0x12,0x4B,0x6C,0x80,0x2E,0x90,0x43,
+
+	0x12,0xE0,0xFC,0xA3,0xE0,0xFD,0xA3,0xE0,
+
+	0xFE,0xA3,0xE0,0xFF,0x90,0x42,0xFE,0xE0,
+
+	0xF8,0xA3,0xE0,0xF9,0xA3,0xE0,0xFA,0xA3,
+
+	0xE0,0xFB,0xEF,0x2B,0xFF,0xEE,0x3A,0xFE,
+
+	0xED,0x39,0xFD,0xEC,0x38,0xFC,0x90,0x43,
+
+	0x12,0x12,0x4B,0x6C,0x90,0x44,0xD5,0xE0,
+
+	0xB4,0x01,0x31,0x90,0x43,0x16,0xE0,0xFC,
+
+	0xA3,0xE0,0xFD,0xA3,0xE0,0xFE,0xA3,0xE0,
+
+	0xFF,0x90,0x43,0x02,0xE0,0xF8,0xA3,0xE0,
+
+	0xF9,0xA3,0xE0,0xFA,0xA3,0xE0,0xFB,0xC3,
+
+	0xEF,0x9B,0xFF,0xEE,0x9A,0xFE,0xED,0x99,
+
+	0xFD,0xEC,0x98,0xFC,0x90,0x43,0x16,0x12,
+
+	0x4B,0x6C,0x80,0x2E,0x90,0x43,0x16,0xE0,
+
+	0xFC,0xA3,0xE0,0xFD,0xA3,0xE0,0xFE,0xA3,
+
+	0xE0,0xFF,0x90,0x43,0x02,0xE0,0xF8,0xA3,
+
+	0xE0,0xF9,0xA3,0xE0,0xFA,0xA3,0xE0,0xFB,
+
+	0xEF,0x2B,0xFF,0xEE,0x3A,0xFE,0xED,0x39,
+
+	0xFD,0xEC,0x38,0xFC,0x90,0x43,0x16,0x12,
+
+	0x4B,0x6C,0x90,0x43,0x0E,0xE0,0xFC,0xA3,
+
+	0xE0,0xFD,0xA3,0xE0,0xFE,0xA3,0xE0,0xFF,
+
+	0x90,0x43,0x06,0xE0,0xF8,0xA3,0xE0,0xF9,
+
+	0xA3,0xE0,0xFA,0xA3,0xE0,0xFB,0xEF,0x2B,
+
+	0xFF,0xEE,0x3A,0xFE,0xED,0x39,0xFD,0xEC,
+
+	0x38,0xFC,0x90,0x43,0x0E,0x12,0x4B,0x6C,
+
+	0x90,0x43,0x26,0xE0,0x04,0xF0,0xE0,0xC3,
+
+	0x94,0x64,0x50,0x03,0x02,0x5A,0x61,0x90,
+
+	0x43,0x0E,0xE0,0xFC,0xA3,0xE0,0xFD,0xA3,
+
+	0xE0,0xFE,0xA3,0xE0,0xFF,0x90,0x43,0x12,
+
+	0xE0,0xF8,0xA3,0xE0,0xF9,0xA3,0xE0,0xFA,
+
+	0xA3,0xE0,0xFB,0xEF,0x9B,0xFF,0xEE,0x9A,
+
+	0xFE,0xED,0x99,0xFD,0xEC,0x98,0xFC,0x90,
+
+	0x43,0x1A,0x12,0x4B,0x6C,0x90,0x43,0x1A,
+
+	0xE0,0xFF,0xC4,0x13,0x13,0x13,0x54,0x01,
+
+	0xFF,0xBF,0x01,0x14,0xE0,0xFC,0xA3,0xE0,
+
+	0xFD,0xA3,0xE0,0xFE,0xA3,0xE0,0xFF,0x12,
+
+	0x4A,0xFD,0x90,0x43,0x1A,0x12,0x4B,0x6C,
+
+	0x90,0x43,0x16,0xE0,0xFF,0xC4,0x13,0x13,
+
+	0x13,0x54,0x01,0xFF,0xBF,0x01,0x31,0x90,
+
+	0x43,0x1A,0xE0,0xFC,0xA3,0xE0,0xFD,0xA3,
+
+	0xE0,0xFE,0xA3,0xE0,0xFF,0x90,0x43,0x16,
+
+	0xE0,0xF8,0xA3,0xE0,0xF9,0xA3,0xE0,0xFA,
+
+	0xA3,0xE0,0xFB,0xC3,0xEF,0x9B,0xFF,0xEE,
+
+	0x9A,0xFE,0xED,0x99,0xFD,0xEC,0x98,0xFC,
+
+	0x90,0x43,0x1A,0x12,0x4B,0x6C,0x80,0x2E,
+
+	0x90,0x43,0x1A,0xE0,0xFC,0xA3,0xE0,0xFD,
+
+	0xA3,0xE0,0xFE,0xA3,0xE0,0xFF,0x90,0x43,
+
+	0x16,0xE0,0xF8,0xA3,0xE0,0xF9,0xA3,0xE0,
+
+	0xFA,0xA3,0xE0,0xFB,0xEF,0x2B,0xFF,0xEE,
+
+	0x3A,0xFE,0xED,0x39,0xFD,0xEC,0x38,0xFC,
+
+	0x90,0x43,0x1A,0x12,0x4B,0x6C,0x90,0x43,
+
+	0x1A,0xE0,0xFC,0xA3,0xE0,0xFD,0xA3,0xE0,
+
+	0xFE,0xA3,0xE0,0xFF,0x78,0x04,0x12,0x4B,
+
+	0x59,0x90,0x43,0x0E,0xE0,0xF8,0xA3,0xE0,
+
+	0xF9,0xA3,0xE0,0xFA,0xA3,0xE0,0xFB,0xC3,
+
+	0x12,0x4B,0x21,0x50,0x06,0x90,0x43,0x27,
+
+	0xE0,0x04,0xF0,0x90,0x43,0x25,0xE0,0x04,
+
+	0xF0,0xE4,0xA3,0xF0,0x90,0x43,0x25,0xE0,
+
+	0xC3,0x94,0x08,0x40,0x6B,0x90,0x43,0x27,
+
+	0xE0,0xFF,0x70,0x1A,0x90,0x42,0x38,0xF0,
+
+	0x90,0xF7,0x07,0x74,0xFC,0xF0,0xA3,0xE4,
+
+	0xF0,0xA3,0x74,0xC9,0xF0,0xA3,0xE4,0xF0,
+
+	0xA3,0x74,0x5E,0xF0,0x80,0x26,0xEF,0xD3,
+
+	0x94,0x07,0x40,0x20,0x90,0x42,0x38,0x74,
+
+	0x01,0xF0,0x90,0xF7,0x07,0x74,0xFC,0xF0,
+
+	0xA3,0xE4,0xF0,0xA3,0x74,0x7E,0xF0,0xA3,
+
+	0xE4,0xF0,0xA3,0x74,0x2F,0xF0,0x90,0x42,
+
+	0x39,0x74,0x01,0xF0,0x90,0x42,0xF7,0xE0,
+
+	0x04,0xF0,0xE4,0x90,0x43,0x25,0xF0,0x90,
+
+	0x43,0x27,0xF0,0x22,0x90,0xF7,0x07,0x74,
+
+	0xFC,0xF0,0xA3,0xE4,0xF0,0xA3,0x74,0x7E,
+
+	0xF0,0xA3,0xE4,0xF0,0xA3,0x74,0x2F,0xF0,
+
+	0x22,0xE4,0x90,0x42,0x68,0xF0,0xA3,0xF0,
+
+	0xA3,0xF0,0xA3,0xF0,0xA3,0xF0,0xA3,0xF0,
+
+	0x90,0xF5,0xB3,0x04,0xF0,0x90,0xF5,0xB1,
+
+	0xE4,0xF0,0x90,0xF5,0xB0,0xF0,0x90,0xF5,
+
+	0xC2,0x04,0xF0,0x90,0xF5,0xB0,0xF0,0x90,
+
+	0xF5,0xC2,0xE4,0xF0,0x90,0x42,0x74,0xF0,
+
+	0x90,0x42,0x5F,0xE0,0x70,0x05,0x90,0x42,
+
+	0x74,0x04,0xF0,0x90,0x42,0x64,0x12,0x4B,
+
+	0x78,0x00,0x00,0x00,0x00,0x90,0xF2,0x1B,
+
+	0x74,0x40,0xF0,0xE4,0x90,0x42,0x78,0xF0,
+
+	0x90,0x42,0x74,0xE0,0xFF,0x90,0x42,0x78,
+
+	0xE0,0xFE,0xD3,0x9F,0x40,0x03,0x02,0x5B,
+
+	0x8B,0x90,0xF5,0xB8,0xEE,0xF0,0x90,0x42,
+
+	0x72,0xE0,0xFE,0xA3,0xE0,0xFF,0xC3,0xE4,
+
+	0x9F,0xFF,0xE4,0x9E,0x90,0x42,0x75,0xF0,
+
+	0xA3,0xEF,0xF0,0x90,0x42,0x72,0xE0,0xFE,
+
+	0xA3,0xE0,0xFF,0x90,0x42,0x75,0xE0,0xFC,
+
+	0xA3,0xE0,0xFD,0xD3,0x9F,0xEE,0x64,0x80,
+
+	0xF8,0xEC,0x64,0x80,0x98,0x40,0x03,0x02,
+
+	0x5B,0x82,0xE0,0x90,0xF4,0x11,0xF0,0xEC,
+
+	0xFF,0x33,0x95,0xE0,0xA3,0xEF,0xF0,0x90,
+
+	0xF5,0xB5,0x74,0x01,0xF0,0x90,0x42,0x78,
+
+	0xE0,0xFF,0x25,0xE0,0x24,0x41,0x90,0xF2,
+
+	0x1B,0xF0,0x7D,0x80,0x7C,0x3E,0xE4,0xFF,
+
+	0x12,0xAB,0xED,0x90,0x44,0xAA,0xE0,0xB4,
+
+	0x01,0x04,0x7F,0x01,0x80,0x02,0x7F,0x00,
+
+	0x90,0xF5,0xB5,0xE0,0x64,0x01,0x60,0x04,
+
+	0x7E,0x01,0x80,0x02,0x7E,0x00,0xEE,0x5F,
+
+	0x70,0xE1,0x90,0xF5,0xB5,0xE0,0xB4,0x01,
+
+	0x04,0x7F,0x01,0x80,0x02,0x7F,0x00,0x90,
+
+	0x42,0x77,0xEF,0xF0,0x90,0x41,0xF8,0xF0,
+
+	0x90,0x42,0x78,0xE0,0xFD,0x25,0xE0,0x24,
+
+	0x42,0x90,0xF2,0x1B,0xF0,0x90,0x42,0x75,
+
+	0xE0,0xFE,0xA3,0xE0,0xFF,0x12,0x9A,0x29,
+
+	0x90,0x42,0x76,0xE0,0x04,0xF0,0x70,0x06,
+
+	0x90,0x42,0x75,0xE0,0x04,0xF0,0x02,0x5A,
+
+	0xDC,0x90,0x42,0x78,0xE0,0x04,0xF0,0x02,
+
+	0x5A,0xB1,0x90,0x42,0x68,0xE0,0xFE,0xA3,
+
+	0xE0,0xFF,0xD3,0x90,0x42,0x6B,0xE0,0x9F,
+
+	0x90,0x42,0x6A,0xE0,0x9E,0x50,0x03,0x02,
+
+	0x5C,0x86,0x90,0x41,0xE7,0xE0,0x64,0x01,
+
+	0xF0,0x90,0xF0,0x76,0xF0,0xE4,0x90,0x42,
+
+	0x6E,0xF0,0x90,0xF1,0xB5,0xE0,0x90,0x42,
+
+	0x6F,0xF0,0x90,0xF1,0xB4,0xE0,0x90,0x42,
+
+	0x70,0xF0,0x90,0xF1,0xB3,0xE0,0x90,0x42,
+
+	0x71,0xF0,0xE4,0xFF,0xFE,0x7D,0x40,0xFC,
+
+	0x90,0x42,0x6E,0xE0,0xF8,0xA3,0xE0,0xF9,
+
+	0xA3,0xE0,0xFA,0xA3,0xE0,0xFB,0x12,0x4B,
+
+	0x0B,0x40,0x23,0x90,0x42,0x6E,0xE0,0xF8,
+
+	0xA3,0xE0,0xF9,0xA3,0xE0,0xFA,0xA3,0xE0,
+
+	0xFB,0xE4,0x9B,0xFF,0xE4,0x9A,0xFE,0x74,
+
+	0x80,0x99,0xFD,0xE4,0x98,0xFC,0x90,0x42,
+
+	0x6E,0x12,0x4B,0x6C,0x80,0x17,0x90,0x42,
+
+	0x6E,0xE0,0xFC,0xA3,0xE0,0xFD,0xA3,0xE0,
+
+	0xFE,0xA3,0xE0,0xFF,0x12,0x4A,0xFD,0x90,
+
+	0x42,0x6E,0x12,0x4B,0x6C,0x90,0x42,0x60,
+
+	0xE0,0xF8,0xA3,0xE0,0xF9,0xA3,0xE0,0xFA,
+
+	0xA3,0xE0,0xFB,0xC3,0xE4,0x9B,0xFF,0xE4,
+
+	0x9A,0xFE,0x74,0x80,0x99,0xFD,0xE4,0x98,
+
+	0xFC,0x90,0x42,0x60,0x12,0x4B,0x6C,0x90,
+
+	0xF1,0xEB,0x74,0x01,0xF0,0xE4,0xF0,0x90,
+
+	0x42,0x6F,0xE0,0x90,0xF1,0xA5,0xF0,0x90,
+
+	0x42,0x70,0xE0,0x90,0xF1,0xA4,0xF0,0x90,
+
+	0x42,0x71,0xE0,0x90,0xF1,0xA3,0xF0,0x90,
+
+	0xF1,0x14,0xE0,0x70,0x06,0x90,0xF1,0x10,
+
+	0xE0,0x60,0x1A,0x90,0xF1,0x0E,0xE0,0xF4,
+
+	0xF0,0xA3,0xE0,0xF4,0xF0,0x90,0xF1,0x12,
+
+	0xE0,0xF4,0xF0,0xA3,0xE0,0xF4,0xF0,0x90,
+
+	0xF1,0x0A,0x74,0x01,0xF0,0x90,0x42,0x6C,
+
+	0xE0,0xFF,0x33,0x95,0xE0,0x90,0xF4,0x0D,
+
+	0xEF,0xF0,0x90,0x42,0x6D,0xE0,0x90,0xF4,
+
+	0x0C,0xF0,0x90,0xF5,0xB6,0x74,0x01,0xF0,
+
+	0x90,0xF2,0x1B,0x74,0x45,0xF0,0x7D,0x80,
+
+	0x7C,0x3E,0xE4,0xFF,0x12,0xAB,0xED,0x90,
+
+	0x44,0xAA,0xE0,0xB4,0x01,0x04,0x7F,0x01,
+
+	0x80,0x02,0x7F,0x00,0x90,0xF5,0xB7,0xE0,
+
+	0x64,0x01,0x60,0x04,0x7E,0x01,0x80,0x02,
+
+	0x7E,0x00,0xEE,0x5F,0x70,0xE1,0x90,0xF5,
+
+	0xB7,0xE0,0xB4,0x01,0x04,0x7F,0x01,0x80,
+
+	0x02,0x7F,0x00,0x90,0x42,0x77,0xEF,0xF0,
+
+	0x90,0x41,0xFF,0xF0,0x90,0xF2,0x1B,0x74,
+
+	0x46,0xF0,0x04,0xF0,0x90,0xF5,0xB6,0xE4,
+
+	0xF0,0x90,0xF5,0xC2,0x04,0xF0,0x90,0xF5,
+
+	0xB0,0xE4,0xF0,0x90,0xF5,0xC2,0xF0,0x22,
+
+	0xE4,0x90,0x44,0x2F,0xF0,0xA3,0xF0,0x90,
+
+	0x44,0x33,0xF0,0xA3,0x04,0xF0,0xE4,0x90,
+
+	0x44,0xB1,0xF0,0x90,0xF5,0xAD,0xF0,0x90,
+
+	0x44,0x2D,0xF0,0xA3,0xF0,0x90,0x44,0x2D,
+
+	0xE0,0xFE,0xA3,0xE0,0xFF,0xC3,0x94,0x03,
+
+	0xEE,0x94,0x00,0x40,0x03,0x02,0x5E,0xA1,
+
+	0xEF,0x4E,0x70,0x22,0x90,0xF4,0x61,0xF0,
+
+	0x90,0xF4,0x60,0xF0,0x90,0xF4,0x64,0x74,
+
+	0x02,0xF0,0x90,0xF4,0x63,0x74,0x06,0xF0,
+
+	0x90,0x43,0xDF,0xE0,0x60,0x5A,0x90,0xF4,
+
+	0x63,0x74,0x07,0xF0,0x80,0x52,0x90,0x44,
+
+	0x2D,0xE0,0x70,0x04,0xA3,0xE0,0x64,0x01,
+
+	0x70,0x22,0x90,0xF4,0x61,0x74,0x02,0xF0,
+
+	0x90,0xF4,0x60,0xF0,0x90,0xF4,0x6C,0xF0,
+
+	0x90,0xF4,0x6B,0x74,0x04,0xF0,0x90,0x43,
+
+	0xDF,0xE0,0x60,0x2C,0x90,0xF4,0x6B,0x74,
+
+	0x07,0xF0,0x80,0x24,0x90,0xF4,0x61,0x74,
+
+	0x01,0xF0,0x90,0xF4,0x60,0x74,0x04,0xF0,
+
+	0x90,0xF4,0x68,0x74,0x02,0xF0,0x90,0xF4,
+
+	0x65,0x74,0x05,0xF0,0x90,0x43,0xDF,0xE0,
+
+	0x60,0x06,0x90,0xF4,0x65,0x74,0x07,0xF0,
+
+	0x90,0xF5,0xAC,0x74,0x01,0xF0,0x90,0xF5,
+
+	0xAE,0xE0,0xB4,0x01,0xF9,0x90,0xF5,0xAE,
+
+	0x74,0x01,0xF0,0x90,0xF4,0x6F,0xE0,0xFE,
+
+	0x90,0xF4,0x6E,0xE0,0xFD,0xEE,0xED,0xFF,
+
+	0x90,0x44,0x31,0xEE,0xF0,0xA3,0xEF,0xF0,
+
+	0x90,0xF4,0x73,0xE0,0xFE,0x90,0xF4,0x72,
+
+	0xE0,0xFD,0xEE,0xED,0xFF,0x90,0x44,0x35,
+
+	0xEE,0xF0,0xA3,0xEF,0xF0,0x90,0x44,0x33,
+
+	0xE0,0xFE,0xA3,0xE0,0xFF,0xFB,0xAA,0x06,
+
+	0xE4,0xF9,0xF8,0x90,0x44,0x31,0xE0,0xFE,
+
+	0xA3,0xE0,0xFF,0xE4,0xFC,0xFD,0x12,0x4A,
+
+	0xAE,0xC0,0x04,0xC0,0x05,0xC0,0x06,0xC0,
+
+	0x07,0x90,0x44,0x35,0xE0,0xFE,0xA3,0xE0,
+
+	0xFF,0xFB,0xAA,0x06,0xE4,0xF9,0xF8,0x90,
+
+	0x44,0x2F,0xE0,0xFE,0xA3,0xE0,0xFF,0xE4,
+
+	0xFC,0xFD,0x12,0x4A,0xAE,0xA8,0x04,0xA9,
+
+	0x05,0xAA,0x06,0xAB,0x07,0xD0,0x07,0xD0,
+
+	0x06,0xD0,0x05,0xD0,0x04,0xC3,0x12,0x4B,
+
+	0x21,0x50,0x4F,0x90,0x44,0x31,0xE0,0xFF,
+
+	0xA3,0xE0,0x90,0x44,0x2F,0xCF,0xF0,0xA3,
+
+	0xEF,0xF0,0x90,0x44,0x35,0xE0,0xFF,0xA3,
+
+	0xE0,0x90,0x44,0x33,0xCF,0xF0,0xA3,0xEF,
+
+	0xF0,0x90,0xF4,0x74,0xE0,0x90,0x44,0x29,
+
+	0xF0,0x90,0xF4,0x75,0xE0,0x90,0x44,0x2A,
+
+	0xF0,0x90,0xF4,0x76,0xE0,0x90,0x44,0x2B,
+
+	0xF0,0x90,0xF4,0x77,0xE0,0x90,0x44,0x2C,
+
+	0xF0,0x90,0x44,0x2E,0xE0,0x25,0xE0,0xFF,
+
+	0x90,0x44,0x2D,0xE0,0x33,0x90,0x44,0xB1,
+
+	0xEF,0xF0,0x90,0xF5,0xAC,0xE4,0xF0,0x90,
+
+	0x44,0x2E,0xE0,0x04,0xF0,0x70,0x06,0x90,
+
+	0x44,0x2D,0xE0,0x04,0xF0,0x02,0x5D,0x1E,
+
+	0x90,0x44,0x2C,0xE0,0xFF,0x90,0x44,0x2B,
+
+	0xE0,0xC3,0x9F,0x50,0x0D,0x90,0x44,0x28,
+
+	0x74,0x03,0xF0,0x90,0x44,0x2B,0xEF,0xF0,
+
+	0x80,0x06,0x90,0x44,0x28,0x74,0x02,0xF0,
+
+	0x90,0x44,0x2A,0xE0,0xFF,0x90,0x44,0x29,
+
+	0xE0,0xC3,0x9F,0x50,0x0D,0x90,0x44,0xB2,
+
+	0x74,0x01,0xF0,0x90,0x44,0x29,0xEF,0xF0,
+
+	0x80,0x05,0xE4,0x90,0x44,0xB2,0xF0,0x90,
+
+	0x44,0x2B,0xE0,0xFF,0x90,0x44,0x29,0xE0,
+
+	0xC3,0x9F,0x50,0x08,0x90,0x44,0x28,0xE0,
+
+	0x90,0x44,0xB2,0xF0,0x90,0x44,0x9A,0xE0,
+
+	0xB4,0x01,0x1F,0x90,0x44,0x9C,0xE0,0xFF,
+
+	0x70,0x06,0x90,0x44,0xB1,0xF0,0x80,0x12,
+
+	0xEF,0xB4,0x01,0x08,0x90,0x44,0xB1,0x74,
+
+	0x02,0xF0,0x80,0x06,0x90,0x44,0xB1,0x74,
+
+	0x04,0xF0,0x90,0x44,0xB2,0xE0,0x90,0xF9,
+
+	0x01,0xF0,0x90,0x44,0xB1,0xE0,0xFF,0x70,
+
+	0x06,0x90,0xF9,0x00,0xF0,0x80,0x21,0xEF,
+
+	0xC3,0x94,0x04,0x40,0x0E,0x90,0xF9,0x00,
+
+	0x74,0x02,0xF0,0x90,0x44,0xB2,0xE0,0x04,
+
+	0xF0,0x80,0x0D,0x90,0xF9,0x00,0x74,0x01,
+
+	0xF0,0x90,0x44,0xB2,0xE0,0x24,0x02,0xF0,
+
+	0x90,0x44,0xB2,0xE0,0xFD,0x12,0xAF,0x75,
+
+	0x90,0x44,0xB2,0xE0,0x24,0x06,0xFF,0x74,
+
+	0x01,0x7E,0x00,0xA8,0x07,0x08,0x80,0x05,
+
+	0xC3,0x33,0xCE,0x33,0xCE,0xD8,0xF9,0x24,
+
+	0xF6,0xFF,0xEE,0x34,0xFF,0x90,0x44,0x2D,
+
+	0xF0,0xA3,0xEF,0xF0,0xE0,0x90,0xF4,0x69,
+
+	0xF0,0x90,0x44,0x2D,0xE0,0x90,0xF4,0x6A,
+
+	0xF0,0x90,0xF4,0x6D,0x74,0x14,0xF0,0x90,
+
+	0xF5,0xAC,0xE4,0xF0,0x22,0xE4,0x90,0x44,
+
+	0x99,0xF0,0x90,0xFE,0x01,0xE0,0x54,0x7F,
+
+	0xFB,0x90,0xFE,0x08,0xE0,0xFD,0xA3,0xE0,
+
+	0x90,0x44,0x97,0xCD,0xF0,0xA3,0xED,0xF0,
+
+	0xAF,0x03,0xEF,0x60,0x0F,0x90,0xFE,0x02,
+
+	0xE0,0xFD,0xA3,0xE0,0x90,0x44,0x97,0xCD,
+
+	0xF0,0xA3,0xED,0xF0,0x90,0x44,0x97,0xE0,
+
+	0xFC,0xA3,0xE0,0xFD,0xC3,0xEC,0x94,0x40,
+
+	0x50,0x12,0x90,0x41,0x8C,0xE0,0x2D,0xFE,
+
+	0x90,0x41,0x8B,0xE0,0x3C,0x90,0x44,0x97,
+
+	0xF0,0xA3,0xCE,0xF0,0x90,0xFE,0x00,0xE0,
+
+	0x64,0x03,0x70,0x29,0xEB,0x64,0x02,0x70,
+
+	0x24,0x04,0xF0,0x90,0x44,0x97,0xE0,0xFE,
+
+	0xA3,0xE0,0xF5,0x82,0x8E,0x83,0xE0,0x90,
+
+	0xFE,0x01,0xF0,0x90,0xFB,0x90,0x74,0x02,
+
+	0xF0,0xA3,0xE4,0xF0,0xA3,0xF0,0x90,0x44,
+
+	0x99,0xF0,0x02,0x61,0xC7,0x90,0xFE,0x00,
+
+	0xE0,0x64,0x04,0x70,0x42,0xAF,0x03,0xEB,
+
+	0x64,0x03,0x70,0x3B,0x90,0x41,0x8B,0xE0,
+
+	0xFE,0xA3,0xE0,0xFF,0x90,0x44,0x97,0xE0,
+
+	0xB5,0x06,0x11,0xA3,0xE0,0xB5,0x07,0x0C,
+
+	0x12,0xA1,0xB1,0x90,0x44,0x99,0x74,0x03,
+
+	0xF0,0x02,0x61,0xC7,0x90,0xFE,0x04,0xE0,
+
+	0xFF,0x90,0x44,0x97,0xE0,0xFC,0xA3,0xE0,
+
+	0xF5,0x82,0x8C,0x83,0xEF,0xF0,0x90,0x44,
+
+	0x99,0x74,0x02,0xF0,0x02,0x61,0xC7,0x90,
+
+	0x44,0x95,0x74,0xFE,0xF0,0xA3,0x74,0x0A,
+
+	0xF0,0x90,0xFE,0x00,0xE0,0xFF,0x24,0xFF,
+
+	0xF5,0x82,0xE4,0x34,0xFD,0xF5,0x83,0xE0,
+
+	0xFC,0xA3,0xE0,0xF4,0xFD,0xEC,0xF4,0x90,
+
+	0x44,0x93,0xF0,0xA3,0xED,0xF0,0xEF,0x24,
+
+	0xFE,0xFF,0x12,0xA2,0xC2,0x90,0x44,0x93,
+
+	0xE0,0x6E,0x70,0x03,0xA3,0xE0,0x6F,0x60,
+
+	0x09,0x90,0x44,0x99,0x74,0x02,0xF0,0x02,
+
+	0x61,0xC7,0x90,0x41,0x8B,0xE0,0xFE,0xA3,
+
+	0xE0,0xFF,0x90,0x44,0x97,0xE0,0xB5,0x06,
+
+	0x27,0xA3,0xE0,0xB5,0x07,0x22,0x12,0xA1,
+
+	0xB1,0x90,0x44,0x99,0x74,0x01,0xF0,0xE4,
+
+	0xFD,0xFF,0x12,0xAC,0xC0,0x90,0xFE,0x01,
+
+	0xE0,0xFE,0xA3,0xE0,0xF4,0xFF,0xEE,0xF4,
+
+	0xA3,0xF0,0xA3,0xEF,0xF0,0x02,0x61,0xC7,
+
+	0x90,0xFE,0x04,0xE0,0xFF,0xFC,0x90,0xFE,
+
+	0x01,0xE0,0x54,0x3F,0xFA,0xA3,0xE0,0xFB,
+
+	0xEA,0x60,0x03,0x02,0x62,0x27,0xEB,0x60,
+
+	0x57,0x24,0xF8,0x60,0x53,0x14,0x60,0x12,
+
+	0x24,0xFC,0x70,0x03,0x02,0x61,0xBE,0x24,
+
+	0xEB,0x60,0x7D,0x24,0x21,0x60,0x03,0x02,
+
+	0x62,0x27,0xEF,0x60,0x23,0x1F,0x90,0x44,
+
+	0x95,0xE0,0xFA,0xA3,0xE0,0x2F,0xF5,0x82,
+
+	0xE4,0x3A,0xF5,0x83,0xE0,0xFE,0x90,0x44,
+
+	0x97,0xE0,0xFA,0xA3,0xE0,0x2F,0xF5,0x82,
+
+	0xE4,0x3A,0xF5,0x83,0xEE,0xF0,0x80,0xDA,
+
+	0xE4,0xFD,0xFF,0x12,0xAC,0xC0,0x90,0xFE,
+
+	0x01,0xE0,0xFE,0xA3,0xE0,0xF4,0xFF,0xEE,
+
+	0xF4,0xA3,0xF0,0xA3,0xEF,0xF0,0x80,0x7E,
+
+	0xAF,0x04,0xE4,0xFD,0x12,0xAC,0xC0,0x90,
+
+	0x44,0x97,0xE0,0xFE,0xA3,0xE0,0xFF,0xAD,
+
+	0x04,0x12,0xA6,0x5B,0x90,0xFE,0x00,0xE0,
+
+	0x24,0xFE,0xFF,0x12,0xA2,0xC2,0xEF,0xF4,
+
+	0xFF,0xEE,0xF4,0xFE,0x90,0xFE,0x00,0xE0,
+
+	0x24,0xFF,0xF5,0x82,0xE4,0x34,0xFD,0xF5,
+
+	0x83,0xEE,0xF0,0xA3,0xEF,0xF0,0x80,0x46,
+
+	0xE4,0xFD,0x7F,0x04,0x12,0xAC,0xC0,0x90,
+
+	0xFE,0x03,0x74,0x04,0xF0,0xA3,0x74,0x15,
+
+	0xF0,0xA3,0x74,0x06,0xF0,0xA3,0x74,0xFB,
+
+	0xF0,0x90,0xFE,0x00,0xE0,0x24,0xFE,0xFF,
+
+	0x12,0xA2,0xC2,0xEF,0xF4,0xFF,0xEE,0xF4,
+
+	0xFE,0x90,0xFE,0x00,0xE0,0x24,0xFF,0xF5,
+
+	0x82,0xE4,0x34,0xFD,0xF5,0x83,0xEE,0xF0,
+
+	0xA3,0xEF,0xF0,0x80,0x09,0x90,0xFB,0x86,
+
+	0x74,0x01,0xF0,0x12,0xA6,0xD7,0x90,0xFB,
+
+	0x86,0x74,0x01,0xF0,0x90,0x44,0x99,0xE0,
+
+	0xFF,0x64,0x02,0x60,0x24,0xEF,0x64,0x03,
+
+	0x60,0x1F,0x90,0xF9,0x9F,0xE0,0x60,0x14,
+
+	0x90,0xFB,0x88,0xE0,0x64,0x01,0x60,0xF8,
+
+	0x90,0xFB,0x96,0xE4,0xF0,0x90,0xFB,0x88,
+
+	0x04,0xF0,0x80,0x05,0x90,0xFB,0x93,0xE4,
+
+	0xF0,0x90,0x44,0x99,0xE0,0xFF,0x64,0x01,
+
+	0x60,0x04,0xEF,0xB4,0x03,0x20,0xE4,0xF5,
+
+	0x13,0xC2,0xAF,0x7A,0xAF,0x79,0xA0,0x12,
+
+	0x4B,0xA9,0x7A,0xAF,0x79,0xA0,0x12,0x4B,
+
+	0xA9,0x7B,0x01,0x7A,0x44,0x79,0x6A,0x7D,
+
+	0x01,0x7C,0x00,0x12,0xA1,0x83,0x22,0x90,
+
+	0x44,0xBB,0xEF,0xF0,0xC2,0xEB,0xE4,0x90,
+
+	0x43,0x6A,0xF0,0xA3,0xF0,0x90,0xF9,0x01,
+
+	0xE0,0xD3,0x94,0x01,0x50,0x0A,0x90,0x43,
+
+	0x6A,0x74,0x05,0xF0,0xA3,0x74,0x55,0xF0,
+
+	0x90,0xF9,0x01,0xE0,0x24,0x06,0xFF,0x74,
+
+	0x01,0x7E,0x00,0xA8,0x07,0x08,0x80,0x05,
+
+	0xC3,0x33,0xCE,0x33,0xCE,0xD8,0xF9,0x90,
+
+	0x43,0x72,0xF0,0xEE,0x90,0x43,0x71,0xF0,
+
+	0x90,0xF9,0x00,0xE0,0x70,0x34,0x90,0x43,
+
+	0x61,0x74,0x02,0xF0,0xA3,0x74,0xAB,0xF0,
+
+	0x90,0x43,0x69,0x74,0x28,0xF0,0x90,0x44,
+
+	0xBD,0x74,0x05,0xF0,0x90,0xF5,0xEF,0x74,
+
+	0x28,0xF0,0x90,0x43,0x6A,0xE0,0xFE,0xA3,
+
+	0xE0,0x78,0x02,0xCE,0xC3,0x13,0xCE,0x13,
+
+	0xD8,0xF9,0xF0,0xEE,0x90,0x43,0x6A,0xF0,
+
+	0x80,0x6F,0x90,0xF9,0x00,0xE0,0xB4,0x01,
+
+	0x34,0x90,0x43,0x61,0x74,0x0A,0xF0,0xA3,
+
+	0x74,0xAB,0xF0,0x90,0x43,0x69,0x74,0x50,
+
+	0xF0,0x90,0x44,0xBD,0x74,0x12,0xF0,0x90,
+
+	0xF5,0xEF,0x74,0x50,0xF0,0x90,0x43,0x71,
+
+	0xE0,0xFE,0xA3,0xE0,0x78,0x02,0xC3,0x33,
+
+	0xCE,0x33,0xCE,0xD8,0xF9,0xF0,0xEE,0x90,
+
+	0x43,0x71,0xF0,0x80,0x34,0x90,0x43,0x61,
+
+	0x74,0x05,0xF0,0xA3,0x74,0x55,0xF0,0x90,
+
+	0x43,0x69,0x74,0x3C,0xF0,0x90,0x44,0xBD,
+
+	0x74,0x09,0xF0,0x90,0xF5,0xEF,0x74,0x3C,
+
+	0xF0,0x90,0x43,0x72,0xE0,0x25,0xE0,0xF0,
+
+	0x90,0x43,0x71,0xE0,0x33,0xF0,0x90,0x43,
+
+	0x6A,0xE0,0xC3,0x13,0xF0,0xA3,0xE0,0x13,
+
+	0xF0,0x90,0x43,0x6A,0xE0,0xFF,0xA3,0xE0,
+
+	0xA3,0xCF,0xF0,0xA3,0xEF,0xF0,0x90,0x43,
+
+	0x69,0xE0,0x90,0xF5,0xE2,0xF0,0x90,0x43,
+
+	0x71,0xE0,0xFE,0xA3,0xE0,0xFF,0x90,0x43,
+
+	0x62,0xE0,0x2F,0xFF,0x90,0x43,0x61,0xE0,
+
+	0x3E,0xA2,0xE7,0x13,0xFE,0xEF,0x13,0xFF,
+
+	0x90,0xF5,0xFE,0xF0,0xEE,0xA3,0xF0,0xE4,
+
+	0x90,0x43,0x6F,0xF0,0xA3,0xF0,0x90,0xF5,
+
+	0x3B,0xF0,0x90,0xF5,0xBB,0xF0,0x90,0xF5,
+
+	0xB1,0xF0,0x90,0xF5,0xC8,0xF0,0x90,0xF5,
+
+	0xF8,0x04,0xF0,0x90,0xF5,0xDF,0x74,0xFB,
+
+	0xF0,0xA3,0xE4,0xF0,0x90,0xF5,0xE3,0x74,
+
+	0x09,0xF0,0xA3,0x74,0x01,0xF0,0xA3,0xF0,
+
+	0x90,0xF5,0xFD,0xF0,0x90,0xF6,0x6D,0xE4,
+
+	0xF0,0x90,0xF5,0xF9,0x74,0x04,0xF0,0x90,
+
+	0x42,0x0E,0xE0,0xB4,0x01,0x1B,0x90,0x44,
+
+	0xBB,0xE0,0xB4,0x01,0x14,0x90,0xF5,0xE3,
+
+	0x74,0x01,0xF0,0x90,0xF5,0xF9,0xF0,0x90,
+
+	0xF5,0xFE,0x74,0xFF,0xF0,0xA3,0x74,0x0F,
+
+	0xF0,0xE4,0x90,0x44,0xBC,0xF0,0x90,0x43,
+
+	0x4B,0xE0,0xB4,0x01,0x22,0xE4,0x90,0x41,
+
+	0xEF,0xF0,0x90,0x43,0x8A,0xF0,0x90,0x43,
+
+	0x4C,0xF0,0x90,0x43,0x77,0xF0,0xA3,0xF0,
+
+	0x90,0xF0,0x2B,0xE0,0xB4,0x01,0x11,0x90,
+
+	0x42,0x12,0x74,0x25,0xF0,0x80,0x09,0x90,
+
+	0x42,0x0F,0xE0,0x14,0x90,0x43,0x77,0xF0,
+
+	0x90,0x42,0x0F,0xE0,0xFF,0x90,0x43,0x77,
+
+	0xE0,0xC3,0x9F,0x50,0x53,0x90,0x44,0xBC,
+
+	0xE0,0x04,0xF0,0x90,0xF5,0xE7,0xE4,0xF0,
+
+	0xA3,0x04,0xF0,0x90,0xF5,0xE1,0xE4,0xF0,
+
+	0x90,0xF5,0xE7,0x04,0xF0,0x90,0xF5,0xE8,
+
+	0xE0,0xB4,0x01,0xF9,0x90,0xF5,0xE1,0xE0,
+
+	0x90,0x43,0x4D,0xF0,0xE0,0xB4,0x05,0x20,
+
+	0x74,0x06,0xF0,0x90,0xF5,0xEA,0xE0,0x90,
+
+	0x43,0x60,0xF0,0x90,0x43,0x4D,0xE0,0x90,
+
+	0xF5,0xE1,0xF0,0x90,0x44,0xBB,0xE0,0xFF,
+
+	0x90,0x44,0xBD,0xE0,0xFD,0x12,0x4D,0x7B,
+
+	0x90,0x43,0x77,0xE0,0x04,0xF0,0x80,0xA0,
+
+	0x12,0x6C,0xF4,0xE4,0x90,0x43,0x4B,0xF0,
+
+	0x90,0x43,0x4D,0xE0,0xFF,0x64,0x0E,0x60,
+
+	0x47,0xEF,0xB4,0x06,0x05,0x12,0x45,0x50,
+
+	0x80,0xEE,0x90,0x43,0x4D,0xE0,0x64,0x07,
+
+	0x70,0x22,0x12,0x84,0x03,0x90,0xF5,0xE8,
+
+	0x74,0x01,0xF0,0x90,0x43,0x4D,0xE0,0x90,
+
+	0xF5,0xE1,0xF0,0x90,0xF5,0xE8,0xE0,0xB4,
+
+	0x01,0xF9,0x90,0xF5,0xE6,0xE4,0xF0,0x12,
+
+	0x8A,0xED,0x80,0xC4,0x90,0x43,0x4D,0xE0,
+
+	0xB4,0x0C,0xBD,0x90,0x44,0xBB,0xE0,0xFF,
+
+	0x12,0x81,0x24,0x12,0x9B,0x32,0x80,0xB0,
+
+	0x90,0xF5,0xE7,0xE4,0xF0,0x90,0xF5,0xE1,
+
+	0xF0,0xD2,0xEB,0x22,0xC2,0xE9,0xC2,0xEA,
+
+	0xD2,0xA8,0xD2,0xAF,0x90,0x43,0xB8,0xE0,
+
+	0x60,0x12,0x90,0xF9,0x57,0xE0,0x54,0xFD,
+
+	0x44,0x02,0xF0,0xE0,0x54,0xFD,0xF0,0xE4,
+
+	0x90,0x43,0xB8,0xF0,0x90,0xF5,0xA9,0x74,
+
+	0x01,0xF0,0x90,0xF0,0x71,0xE4,0xF0,0x90,
+
+	0xF1,0xE9,0xF0,0x90,0xF0,0xD5,0xF0,0x90,
+
+	0xF0,0xE3,0xF0,0x90,0xF0,0xE2,0xF0,0x90,
+
+	0xF1,0xEA,0xF0,0x90,0xF1,0xEF,0xF0,0x90,
+
+	0xF1,0xF2,0xF0,0x90,0xF1,0xF7,0xF0,0x90,
+
+	0xF1,0xFB,0xF0,0x90,0xF5,0xAF,0xF0,0xA3,
+
+	0xF0,0xA3,0xF0,0x90,0xF5,0xBB,0xF0,0x90,
+
+	0xF5,0xA8,0xF0,0x90,0xF5,0xAC,0xF0,0x90,
+
+	0xF5,0xC8,0xF0,0x90,0xF4,0x71,0xF0,0x90,
+
+	0xF9,0x0B,0xF0,0x90,0xF5,0xE7,0xF0,0x90,
+
+	0xF5,0xE1,0xF0,0x90,0xF4,0x71,0xF0,0x90,
+
+	0xF5,0xD7,0xF0,0x90,0xF6,0x25,0xF0,0x90,
+
+	0xFD,0xA2,0xF0,0x90,0xF1,0xE8,0x04,0xF0,
+
+	0x90,0xF0,0x6C,0xF0,0x90,0xF1,0x75,0xF0,
+
+	0x90,0xF1,0x31,0xF0,0xE4,0x90,0x43,0xDF,
+
+	0xF0,0x90,0xF1,0xF6,0x04,0xF0,0x90,0xF1,
+
+	0xFA,0xF0,0x90,0xF1,0xF3,0xF0,0x90,0xF1,
+
+	0xF0,0xF0,0x90,0xF0,0x7D,0xF0,0x90,0xF1,
+
+	0xEB,0xF0,0x90,0xF5,0xC2,0xF0,0x90,0xF5,
+
+	0xB3,0xF0,0x90,0xF5,0xBD,0xF0,0x90,0xF1,
+
+	0xE8,0xF0,0xE4,0xF0,0x90,0xF0,0x6C,0xF0,
+
+	0x90,0xF1,0x75,0xF0,0x90,0xF1,0x31,0xF0,
+
+	0x90,0xF1,0xFA,0xF0,0x90,0x41,0xBA,0xE0,
+
+	0x90,0xF1,0xA3,0xF0,0x90,0x41,0xBB,0xE0,
+
+	0x90,0xF1,0xA4,0xF0,0x90,0x41,0xBC,0xE0,
+
+	0x90,0xF1,0xA5,0xF0,0x90,0xF6,0x21,0x74,
+
+	0x02,0xF0,0x90,0xF6,0x23,0xF0,0x90,0xF5,
+
+	0xC6,0xE4,0xF0,0xA3,0xF0,0x90,0xF5,0xC3,
+
+	0xF0,0xA3,0xF0,0x90,0x41,0xB2,0xE0,0x90,
+
+	0xF1,0x54,0xF0,0x90,0x41,0xB3,0xE0,0x90,
+
+	0xF1,0x55,0xF0,0x90,0x41,0xB4,0xE0,0x90,
+
+	0xF1,0x52,0xF0,0x90,0x41,0xB5,0xE0,0x90,
+
+	0xF1,0x53,0xF0,0x90,0xF1,0x93,0xE4,0xF0,
+
+	0x90,0xF1,0x69,0x74,0x08,0xF0,0x90,0xF1,
+
+	0x5F,0x74,0x02,0xF0,0x90,0xF1,0x4E,0x74,
+
+	0x40,0xF0,0x74,0xFF,0xF0,0x90,0xF1,0x85,
+
+	0xE4,0xF0,0x90,0xF1,0x2F,0x04,0xF0,0x90,
+
+	0xFD,0x02,0xF0,0x90,0xF7,0x0F,0xE4,0xF0,
+
+	0x90,0xF7,0x8A,0x74,0x0F,0xF0,0x90,0xF7,
+
+	0x98,0x74,0x0D,0xF0,0x90,0xF7,0x8B,0x74,
+
+	0x01,0xF0,0x90,0xFD,0xA5,0xE4,0xF0,0x90,
+
+	0xF5,0x52,0x74,0x3F,0xF0,0xA3,0x74,0x05,
+
+	0xF0,0x90,0x44,0x9D,0x74,0x0A,0xF0,0x90,
+
+	0xF0,0x71,0x74,0x01,0xF0,0x90,0xF7,0x15,
+
+	0xF0,0x90,0xF9,0x0E,0xF0,0x90,0xF5,0x06,
+
+	0x74,0x04,0xF0,0x90,0xF7,0x3C,0xE0,0x70,
+
+	0x04,0x90,0xF7,0x2F,0xF0,0x12,0xAE,0x16,
+
+	0x90,0xF7,0x34,0xE4,0xF0,0x90,0xF7,0x33,
+
+	0xF0,0x90,0xF7,0x35,0x74,0x05,0xF0,0xA3,
+
+	0xF0,0x90,0xF7,0x39,0x74,0xFF,0xF0,0xA3,
+
+	0x74,0x9C,0xF0,0x90,0xF7,0x7E,0x74,0x01,
+
+	0xF0,0x90,0xFD,0x00,0xF0,0x90,0xFD,0x90,
+
+	0x74,0x03,0xF0,0x90,0xF2,0x17,0x74,0xFE,
+
+	0xF0,0x90,0xF0,0x42,0x04,0xF0,0xA3,0xF0,
+
+	0xA3,0x74,0x07,0xF0,0xA3,0xF0,0x90,0xF7,
+
+	0x74,0x74,0x01,0xF0,0x90,0xF7,0x6A,0xF0,
+
+	0x12,0xAB,0x75,0x90,0xF7,0x3E,0x74,0x01,
+
+	0xF0,0x90,0xF7,0x3C,0xE0,0x70,0x0B,0x90,
+
+	0x44,0x9B,0xF0,0xD2,0xEA,0x90,0xF7,0x76,
+
+	0x04,0xF0,0x90,0xF7,0x37,0x74,0xDC,0xF0,
+
+	0xA3,0x74,0x05,0xF0,0x90,0xFD,0xA2,0xE4,
+
+	0xF0,0xA3,0xF0,0xA3,0x74,0x05,0xF0,0x90,
+
+	0xF5,0x4D,0x74,0x01,0xF0,0x90,0xF5,0x41,
+
+	0xE4,0xF0,0xA3,0x74,0x02,0xF0,0x90,0xF6,
+
+	0x5C,0xE4,0xF0,0xA3,0xF0,0x90,0xF0,0x5F,
+
+	0x04,0xF0,0x90,0x42,0x0A,0xE0,0x90,0xF0,
+
+	0x06,0xF0,0x90,0xF0,0x58,0xE4,0xF0,0xF0,
+
+	0x90,0x42,0x2B,0xF0,0x90,0x42,0x38,0x74,
+
+	0xFF,0xF0,0x90,0x42,0xFC,0xF0,0x90,0x42,
+
+	0xF7,0xF0,0x90,0xF9,0xE5,0x74,0x1E,0xF0,
+
+	0xA3,0x74,0x05,0xF0,0xA3,0xE4,0xF0,0x90,
+
+	0x42,0x3D,0x74,0xFF,0xF0,0x22,0x90,0xF4,
+
+	0x60,0xE0,0x60,0x03,0x02,0x67,0xA0,0x90,
+
+	0x41,0x92,0xE0,0x90,0xF4,0x03,0xF0,0x90,
+
+	0x41,0x93,0xE0,0x90,0xF4,0x02,0xF0,0x90,
+
+	0x41,0x94,0xE0,0x90,0xF4,0x01,0xF0,0x90,
+
+	0x41,0x95,0xE0,0x90,0xF4,0x00,0xF0,0x90,
+
+	0x41,0x96,0xE0,0x90,0xF4,0x07,0xF0,0x90,
+
+	0x41,0x97,0xE0,0x90,0xF4,0x06,0xF0,0x90,
+
+	0x41,0x98,0xE0,0x90,0xF4,0x05,0xF0,0x90,
+
+	0x41,0x99,0xE0,0x90,0xF4,0x04,0xF0,0x12,
+
+	0xAE,0xA0,0x90,0xF9,0x01,0xE0,0x14,0x60,
+
+	0x16,0x14,0x60,0x1F,0x14,0x60,0x28,0x24,
+
+	0x03,0x70,0x2E,0x90,0xF5,0x59,0x74,0xFA,
+
+	0xF0,0xA3,0x74,0x54,0xF0,0x80,0x22,0x90,
+
+	0xF5,0x59,0x74,0x7A,0xF0,0xA3,0x74,0x52,
+
+	0xF0,0x80,0x16,0x90,0xF5,0x59,0x74,0xE5,
+
+	0xF0,0xA3,0x74,0x4D,0xF0,0x80,0x0A,0x90,
+
+	0xF5,0x59,0x74,0x1B,0xF0,0xA3,0x74,0x46,
+
+	0xF0,0x12,0xAF,0x0C,0x90,0xF7,0x37,0x74,
+
+	0xDC,0xF0,0xA3,0x74,0x05,0xF0,0x22,0x90,
+
+	0xF4,0x60,0xE0,0x64,0x04,0x60,0x03,0x02,
+
+	0x68,0x3B,0x90,0x41,0xAA,0xE0,0x90,0xF4,
+
+	0x03,0xF0,0x90,0x41,0xAB,0xE0,0x90,0xF4,
+
+	0x02,0xF0,0x90,0x41,0xAC,0xE0,0x90,0xF4,
+
+	0x01,0xF0,0x90,0x41,0xAD,0xE0,0x90,0xF4,
+
+	0x00,0xF0,0x90,0x41,0xAE,0xE0,0x90,0xF4,
+
+	0x07,0xF0,0x90,0x41,0xAF,0xE0,0x90,0xF4,
+
+	0x06,0xF0,0x90,0x41,0xB0,0xE0,0x90,0xF4,
+
+	0x05,0xF0,0x90,0x41,0xB1,0xE0,0x90,0xF4,
+
+	0x04,0xF0,0x12,0xAE,0xC0,0x90,0xF9,0x01,
+
+	0xE0,0x14,0x60,0x16,0x14,0x60,0x1F,0x14,
+
+	0x60,0x28,0x24,0x03,0x70,0x2E,0x90,0xF5,
+
+	0x59,0x74,0xA4,0xF0,0xA3,0x74,0x28,0xF0,
+
+	0x80,0x22,0x90,0xF5,0x59,0x74,0x72,0xF0,
+
+	0xA3,0x74,0x27,0xF0,0x80,0x16,0x90,0xF5,
+
+	0x59,0x74,0x41,0xF0,0xA3,0x74,0x25,0xF0,
+
+	0x80,0x0A,0x90,0xF5,0x59,0x74,0x87,0xF0,
+
+	0xA3,0x74,0x21,0xF0,0x12,0xAE,0xD0,0x90,
+
+	0xF7,0x37,0x74,0xB8,0xF0,0xA3,0x74,0x0B,
+
+	0xF0,0x22,0x90,0xF4,0x60,0xE0,0x24,0xFE,
+
+	0x60,0x29,0x14,0x60,0x48,0x24,0x02,0x70,
+
+	0x64,0x90,0x41,0x9A,0xE0,0x90,0xF4,0x03,
+
+	0xF0,0x90,0x41,0x9B,0xE0,0x90,0xF4,0x02,
+
+	0xF0,0x90,0x41,0x9C,0xE0,0x90,0xF4,0x01,
+
+	0xF0,0x90,0x41,0x9D,0xE0,0x90,0xF4,0x00,
+
+	0xF0,0x80,0x42,0x90,0x41,0x9E,0xE0,0x90,
+
+	0xF4,0x03,0xF0,0x90,0x41,0x9F,0xE0,0x90,
+
+	0xF4,0x02,0xF0,0x90,0x41,0xA0,0xE0,0x90,
+
+	0xF4,0x01,0xF0,0x90,0x41,0xA1,0xE0,0x90,
+
+	0xF4,0x00,0xF0,0x80,0x20,0x90,0x41,0xA2,
+
+	0xE0,0x90,0xF4,0x03,0xF0,0x90,0x41,0xA3,
+
+	0xE0,0x90,0xF4,0x02,0xF0,0x90,0x41,0xA4,
+
+	0xE0,0x90,0xF4,0x01,0xF0,0x90,0x41,0xA5,
+
+	0xE0,0x90,0xF4,0x00,0xF0,0x90,0x41,0xA6,
+
+	0xE0,0x90,0xF4,0x07,0xF0,0x90,0x41,0xA7,
+
+	0xE0,0x90,0xF4,0x06,0xF0,0x90,0x41,0xA8,
+
+	0xE0,0x90,0xF4,0x05,0xF0,0x90,0x41,0xA9,
+
+	0xE0,0x90,0xF4,0x04,0xF0,0x12,0xAE,0xB0,
+
+	0x90,0xF9,0x01,0xE0,0x14,0x60,0x16,0x14,
+
+	0x60,0x1F,0x14,0x60,0x28,0x24,0x03,0x70,
+
+	0x2E,0x90,0xF5,0x59,0x74,0x52,0xF0,0xA3,
+
+	0x74,0x14,0xF0,0x80,0x22,0x90,0xF5,0x59,
+
+	0x74,0xB9,0xF0,0xA3,0x74,0x13,0xF0,0x80,
+
+	0x16,0x90,0xF5,0x59,0x74,0xA1,0xF0,0xA3,
+
+	0x74,0x12,0xF0,0x80,0x0A,0x90,0xF5,0x59,
+
+	0x74,0xC4,0xF0,0xA3,0x74,0x10,0xF0,0x12,
+
+	0xAE,0x7E,0x90,0xF7,0x37,0x74,0xB8,0xF0,
+
+	0xA3,0x74,0x0B,0xF0,0x22,0x90,0x41,0xE8,
+
+	0xE0,0x60,0x03,0x02,0x69,0xEB,0x90,0xF0,
+
+	0x60,0xE0,0xC3,0x94,0xD5,0x50,0x27,0x90,
+
+	0x42,0x54,0xE0,0x90,0x44,0x45,0xF0,0x94,
+
+	0x00,0x40,0x06,0xE0,0x14,0x90,0x42,0x54,
+
+	0xF0,0x90,0xF0,0x60,0xE0,0xD3,0x94,0x60,
+
+	0x50,0x24,0x90,0x44,0x47,0x74,0x86,0xF0,
+
+	0x90,0xFB,0x28,0xF0,0x80,0x18,0x90,0xF0,
+
+	0x60,0xE0,0xD3,0x94,0xF7,0x40,0x0F,0xE0,
+
+	0x94,0xFF,0x40,0x0A,0x90,0x44,0x47,0x74,
+
+	0x82,0xF0,0x90,0xFB,0x28,0xF0,0x90,0x41,
+
+	0xE3,0xE0,0x60,0x47,0x90,0xF0,0x61,0xE0,
+
+	0xD3,0x94,0xBA,0x50,0x26,0x90,0x41,0xD5,
+
+	0xE0,0x60,0x38,0x90,0x44,0x46,0xE0,0x25,
+
+	0xE0,0xFF,0xE4,0x33,0xFE,0xEF,0x24,0xA0,
+
+	0xFF,0xE4,0x3E,0xFE,0x90,0xF0,0x61,0xE0,
+
+	0xD3,0x9F,0xEE,0x64,0x80,0xF8,0x74,0x80,
+
+	0x98,0x40,0x18,0x90,0x41,0xDC,0xE0,0xB4,
+
+	0x01,0x07,0x7F,0x02,0x12,0xAD,0x3C,0x80,
+
+	0x05,0x7F,0x0C,0x12,0xAD,0x3C,0xE4,0x90,
+
+	0x41,0xE3,0xF0,0x90,0x41,0xE3,0xE0,0x70,
+
+	0x24,0x90,0xF0,0x61,0xE0,0xC3,0x94,0x5A,
+
+	0x50,0x1B,0x90,0x41,0xDC,0xE0,0xB4,0x01,
+
+	0x07,0x7F,0x01,0x12,0xAD,0x3C,0x80,0x05,
+
+	0x7F,0x0B,0x12,0xAD,0x3C,0x90,0x41,0xE3,
+
+	0x74,0x01,0xF0,0x80,0x05,0x90,0xF0,0x60,
+
+	0xE0,0xFF,0x90,0x41,0xE9,0xE0,0x60,0x03,
+
+	0x02,0x6B,0x1A,0x12,0xA3,0x15,0x90,0x42,
+
+	0x13,0xE0,0xFE,0xEF,0xD3,0x9E,0x50,0x13,
+
+	0x12,0xA3,0x15,0x90,0x42,0x14,0xE0,0xFE,
+
+	0xEF,0xD3,0x9E,0x40,0x68,0x90,0x41,0xD5,
+
+	0xE0,0x60,0x62,0x90,0x42,0x54,0xE0,0xD3,
+
+	0x94,0x00,0x40,0x59,0xE0,0x14,0xF0,0xE0,
+
+	0x90,0x44,0x45,0xF0,0x90,0x41,0xE3,0xE0,
+
+	0x60,0x4B,0x90,0xF0,0x1C,0xE0,0xFE,0x90,
+
+	0xF0,0x1B,0xE0,0x7C,0x00,0x24,0x00,0xFF,
+
+	0xEC,0x3E,0x90,0x44,0x4E,0xF0,0xA3,0xEF,
+
+	0xF0,0xE0,0x24,0xF9,0xF0,0x90,0x44,0x4E,
+
+	0xE0,0x34,0xFF,0xF0,0x90,0xF0,0x0F,0xE0,
+
+	0xFE,0x90,0xF0,0x0E,0xE0,0x24,0x00,0xFF,
+
+	0xEC,0x3E,0x90,0x44,0x4A,0xF0,0xA3,0xEF,
+
+	0xF0,0xE0,0x24,0xF9,0xF0,0x90,0x44,0x4A,
+
+	0xE0,0x34,0xFF,0xF0,0x12,0xA9,0xA8,0x90,
+
+	0x44,0x46,0xE0,0x04,0xF0,0x12,0xA3,0x15,
+
+	0x90,0x42,0x15,0xE0,0xFE,0xEF,0xC3,0x9E,
+
+	0x50,0x06,0x90,0x41,0xD5,0xE0,0x60,0x10,
+
+	0x12,0xA3,0x15,0x90,0x42,0x16,0xE0,0xFE,
+
+	0xEF,0xC3,0x9E,0x40,0x03,0x02,0x6B,0x1A,
+
+	0x90,0x41,0xDC,0xE0,0xB4,0x01,0x04,0x7F,
+
+	0x0F,0x80,0x02,0x7F,0x0B,0x90,0x42,0x54,
+
+	0xE0,0xC3,0x9F,0x50,0x58,0xE0,0x04,0xF0,
+
+	0x90,0x44,0x46,0xE0,0x94,0x00,0x40,0x59,
+
+	0x90,0xF0,0x1C,0xE0,0xFE,0x90,0xF0,0x1B,
+
+	0xE0,0x7C,0x00,0x24,0x00,0xFF,0xEC,0x3E,
+
+	0x90,0x44,0x4E,0xF0,0xA3,0xEF,0xF0,0xE0,
+
+	0x24,0x07,0xF0,0x90,0x44,0x4E,0xE0,0x34,
+
+	0x00,0xF0,0x90,0xF0,0x0F,0xE0,0xFE,0x90,
+
+	0xF0,0x0E,0xE0,0x24,0x00,0xFF,0xEC,0x3E,
+
+	0x90,0x44,0x4A,0xF0,0xA3,0xEF,0xF0,0xE0,
+
+	0x24,0x07,0xF0,0x90,0x44,0x4A,0xE0,0x34,
+
+	0x00,0xF0,0x12,0xA9,0xA8,0x90,0x44,0x46,
+
+	0xE0,0x14,0xF0,0x80,0x0C,0x90,0x44,0x46,
+
+	0xE0,0xD3,0x94,0x00,0x40,0x03,0x12,0xAA,
+
+	0x3A,0x90,0x42,0x54,0xE0,0x90,0x44,0x45,
+
+	0xF0,0x22,0x90,0x41,0xD1,0xE0,0x60,0x6E,
+
+	0x90,0xF9,0x00,0xE0,0x90,0x44,0xB1,0xF0,
+
+	0x90,0xF9,0x01,0xE0,0x90,0x44,0xB2,0xF0,
+
+	0x90,0x44,0xB1,0xE0,0x70,0x0A,0xA3,0xE0,
+
+	0xFD,0xE4,0xFF,0x12,0xAF,0x75,0x80,0x22,
+
+	0x90,0x44,0xB1,0xE0,0xB4,0x02,0x0D,0xA3,
+
+	0xE0,0x04,0xF0,0xE0,0xFD,0x7F,0x04,0x12,
+
+	0xAF,0x75,0x80,0x0E,0x90,0x44,0xB2,0xE0,
+
+	0x24,0x02,0xF0,0xE0,0xFD,0x7F,0x02,0x12,
+
+	0xAF,0x75,0x90,0x44,0xB2,0xE0,0x24,0x06,
+
+	0xFF,0x74,0x01,0x7E,0x00,0xA8,0x07,0x08,
+
+	0x80,0x05,0xC3,0x33,0xCE,0x33,0xCE,0xD8,
+
+	0xF9,0x24,0xF6,0xFF,0xEE,0x34,0xFF,0xFE,
+
+	0xEF,0x90,0xF4,0x69,0xF0,0xEE,0xA3,0xF0,
+
+	0x90,0xF4,0x6D,0x74,0x14,0xF0,0x90,0xF4,
+
+	0x63,0x74,0x05,0xF0,0x90,0x43,0xDF,0xE0,
+
+	0x60,0x06,0x90,0xF4,0x63,0x74,0x07,0xF0,
+
+	0x90,0xF5,0xAD,0x74,0x01,0xF0,0x90,0xF5,
+
+	0xAC,0xE4,0xF0,0x04,0xF0,0x90,0xF5,0xAE,
+
+	0xE0,0xB4,0x01,0xF9,0x90,0xF5,0xAE,0x74,
+
+	0x01,0xF0,0x90,0xF4,0x83,0xE0,0x90,0x44,
+
+	0x52,0xF0,0x90,0xF4,0x82,0xE0,0x90,0x44,
+
+	0x53,0xF0,0x90,0xF4,0x81,0xE0,0x90,0x44,
+
+	0x54,0xF0,0x90,0xF4,0x80,0xE0,0x90,0x44,
+
+	0x55,0xF0,0x90,0xF4,0x86,0xE0,0x30,0xE2,
+
+	0x04,0x7F,0xFF,0x80,0x02,0x7F,0x00,0x90,
+
+	0x44,0x56,0xEF,0xF0,0xE0,0xB4,0xFF,0x09,
+
+	0x90,0xF4,0x86,0xE0,0x44,0xF8,0xFF,0x80,
+
+	0x07,0x90,0xF4,0x86,0xE0,0x54,0x07,0xFF,
+
+	0x90,0x44,0x57,0xEF,0xF0,0x90,0xF4,0x85,
+
+	0xE0,0x90,0x44,0x58,0xF0,0x90,0xF4,0x84,
+
+	0xE0,0x90,0x44,0x59,0xF0,0x90,0x44,0xB2,
+
+	0xE0,0x24,0x05,0xFF,0x74,0x01,0x7E,0x00,
+
+	0xA8,0x07,0x08,0x80,0x05,0xC3,0x33,0xCE,
+
+	0x33,0xCE,0xD8,0xF9,0x90,0x44,0xB0,0xF0,
+
+	0xEE,0x90,0x44,0xAF,0xF0,0x90,0x44,0x56,
+
+	0xE0,0xF8,0xA3,0xE0,0xF9,0xA3,0xE0,0xFA,
+
+	0xA3,0xE0,0xFB,0x90,0x44,0x52,0xE0,0xFC,
+
+	0xA3,0xE0,0xFD,0xA3,0xE0,0xFE,0xA3,0xE0,
+
+	0xFF,0x12,0xA4,0xD1,0xA8,0x04,0xA9,0x05,
+
+	0xAA,0x06,0xAB,0x07,0x90,0x44,0xAF,0xE0,
+
+	0xFE,0xA3,0xE0,0xFF,0xE4,0xFC,0xFD,0xEB,
+
+	0x2F,0xFF,0xEA,0x3E,0xFE,0xED,0x39,0xFD,
+
+	0xEC,0x38,0xFC,0x90,0x44,0x5A,0x12,0x4B,
+
+	0x6C,0x90,0x44,0xB0,0xE0,0x90,0xF5,0x3C,
+
+	0xF0,0x90,0x44,0xAF,0xE0,0x90,0xF5,0x3D,
+
+	0xF0,0xE4,0x7F,0xFF,0x7E,0x07,0xFD,0xFC,
+
+	0x90,0x44,0x5A,0xE0,0xF8,0xA3,0xE0,0xF9,
+
+	0xA3,0xE0,0xFA,0xA3,0xE0,0xFB,0xD3,0x12,
+
+	0x4B,0x0B,0x40,0x0C,0x90,0x44,0x5A,0x12,
+
+	0x4B,0x78,0x00,0x00,0x07,0xFF,0x80,0x26,
+
+	0x7F,0x00,0x7E,0xF8,0x7D,0xFF,0x7C,0xFF,
+
+	0x90,0x44,0x5A,0xE0,0xF8,0xA3,0xE0,0xF9,
+
+	0xA3,0xE0,0xFA,0xA3,0xE0,0xFB,0xC3,0x12,
+
+	0x4B,0x0B,0x50,0x0A,0x90,0x44,0x5A,0x12,
+
+	0x4B,0x78,0xFF,0xFF,0xF8,0x00,0x90,0x44,
+
+	0x5D,0xE0,0x90,0xF4,0x66,0xF0,0x90,0x44,
+
+	0x5C,0xE0,0x90,0xF4,0x67,0xF0,0x90,0xF4,
+
+	0x67,0xE0,0x70,0xFA,0x90,0xF4,0x66,0xE0,
+
+	0x70,0xF4,0x22,0x90,0x43,0x63,0x74,0x01,
+
+	0xF0,0x90,0x41,0xEF,0xE0,0xFF,0xD3,0x94,
+
+	0x01,0x40,0x05,0xEF,0x14,0xFF,0x80,0x02,
+
+	0x7F,0x01,0x90,0x43,0x64,0xEF,0xF0,0x90,
+
+	0xF6,0x6D,0x74,0x01,0xF0,0x90,0x41,0xEF,
+
+	0xE0,0x90,0xF6,0x6C,0xF0,0x90,0xF6,0x69,
+
+	0x74,0x01,0xF0,0xE4,0xF9,0x90,0x41,0xEF,
+
+	0xE0,0xFE,0xE9,0xC3,0x9E,0x50,0x47,0xE9,
+
+	0x25,0xE0,0x24,0x50,0xF5,0x82,0xE4,0x34,
+
+	0x43,0xF5,0x83,0xE0,0x90,0xF6,0x6B,0xF0,
+
+	0xE9,0x25,0xE0,0x24,0x51,0xF5,0x82,0xE4,
+
+	0x34,0x43,0xF5,0x83,0xE0,0x90,0xF6,0x6A,
+
+	0xF0,0xE9,0x25,0xE0,0x24,0x58,0xF5,0x82,
+
+	0xE4,0x34,0x43,0xF5,0x83,0xE0,0x90,0xF6,
+
+	0x6B,0xF0,0xE9,0x25,0xE0,0x24,0x59,0xF5,
+
+	0x82,0xE4,0x34,0x43,0xF5,0x83,0xE0,0x90,
+
+	0xF6,0x6A,0xF0,0x09,0x80,0xAF,0x90,0x42,
+
+	0x0E,0xE0,0xB4,0x01,0x46,0x90,0x43,0x47,
+
+	0xE0,0xFC,0xA3,0xE0,0xFD,0xC3,0x90,0x43,
+
+	0x6B,0xE0,0x9D,0x90,0x43,0x6A,0xE0,0x9C,
+
+	0x50,0x0E,0x90,0x43,0x47,0xE0,0xA3,0xE0,
+
+	0x90,0x43,0x6A,0xEC,0xF0,0xA3,0xED,0xF0,
+
+	0x90,0x43,0x49,0xE0,0xFC,0xA3,0xE0,0xFD,
+
+	0xC3,0x90,0x43,0x6D,0xE0,0x9D,0x90,0x43,
+
+	0x6C,0xE0,0x9C,0x50,0x0E,0x90,0x43,0x49,
+
+	0xE0,0xA3,0xE0,0x90,0x43,0x6C,0xEC,0xF0,
+
+	0xA3,0xED,0xF0,0x79,0x01,0x90,0x41,0xEF,
+
+	0xE0,0xFE,0xE9,0xC3,0x9E,0x50,0x79,0xE9,
+
+	0x25,0xE0,0x24,0x58,0xF5,0x82,0xE4,0x34,
+
+	0x43,0xF5,0x83,0xE0,0xFC,0xA3,0xE0,0xFD,
+
+	0x90,0x43,0x58,0xE0,0xFA,0xA3,0xE0,0xFB,
+
+	0xC3,0xED,0x9B,0xFD,0xEC,0x9A,0xFC,0xD3,
+
+	0x90,0x43,0x6B,0xE0,0x9D,0x90,0x43,0x6A,
+
+	0xE0,0x9C,0x40,0x06,0xE9,0x04,0x90,0x43,
+
+	0x63,0xF0,0x90,0x43,0x61,0xE0,0xFC,0xA3,
+
+	0xE0,0xFD,0x90,0x43,0x59,0xE0,0x2D,0xFD,
+
+	0x90,0x43,0x58,0xE0,0x3C,0xFC,0xC3,0xEE,
+
+	0x99,0xFF,0x25,0xE0,0x24,0x58,0xF5,0x82,
+
+	0xE4,0x34,0x43,0xF5,0x83,0xE0,0xFA,0xA3,
+
+	0xE0,0xFB,0xC3,0xED,0x9B,0xFD,0xEC,0x9A,
+
+	0xFC,0xD3,0x90,0x43,0x6D,0xE0,0x9D,0x90,
+
+	0x43,0x6C,0xE0,0x9C,0x40,0x06,0xEF,0x14,
+
+	0x90,0x43,0x64,0xF0,0x09,0x02,0x6D,0xC6,
+
+	0x90,0x43,0x64,0xE0,0xFF,0x90,0x43,0x63,
+
+	0xE0,0xFE,0xD3,0x9F,0x40,0x0F,0xEF,0x24,
+
+	0x01,0xFD,0xE4,0x33,0xFC,0xEE,0xB5,0x05,
+
+	0xE7,0xE4,0xB5,0x04,0xE3,0x90,0x41,0xEF,
+
+	0xE0,0xFF,0xB4,0x01,0x0C,0xE4,0x90,0x43,
+
+	0x65,0xF0,0x90,0x43,0x4D,0x74,0x0C,0xF0,
+
+	0x22,0x90,0x43,0x64,0xE0,0xF9,0x24,0x01,
+
+	0xFD,0xE4,0x33,0xFC,0x90,0x43,0x63,0xE0,
+
+	0xFE,0xB5,0x05,0x1E,0xE4,0xB5,0x04,0x1A,
+
+	0xEE,0xB5,0x07,0x07,0xE4,0x90,0x43,0x65,
+
+	0xF0,0x80,0x08,0x90,0x43,0x63,0xE0,0x90,
+
+	0x43,0x65,0xF0,0x90,0x43,0x4D,0x74,0x0C,
+
+	0xF0,0x22,0xE9,0xFF,0x90,0x43,0x63,0xE0,
+
+	0x2F,0xFF,0xE4,0x33,0xA2,0xE7,0x13,0xEF,
+
+	0x13,0x90,0x43,0x66,0xF0,0x90,0x43,0x4D,
+
+	0x74,0x06,0xF0,0x22,0x90,0x44,0x20,0x12,
+
+	0x4B,0x78,0x00,0x00,0x00,0x00,0x90,0x44,
+
+	0x24,0x12,0x4B,0x78,0x00,0x00,0x00,0x00,
+
+	0xE4,0x90,0x43,0xF5,0xF0,0xA3,0xF0,0x90,
+
+	0x43,0xF7,0xF0,0xA3,0xF0,0x90,0x43,0xE2,
+
+	0xE0,0xFF,0xA3,0xE0,0x90,0x44,0x16,0xCF,
+
+	0xF0,0xA3,0xEF,0xF0,0x90,0x43,0xE4,0xE0,
+
+	0xFE,0xA3,0xE0,0xFF,0xD3,0x90,0x44,0x17,
+
+	0xE0,0x9F,0x90,0x44,0x16,0xE0,0x9E,0x40,
+
+	0x03,0x02,0x70,0x4D,0xA3,0xE0,0x90,0xF6,
+
+	0x67,0xF0,0x90,0x44,0x16,0xE0,0x90,0xF6,
+
+	0x68,0xF0,0x90,0xF6,0x66,0x74,0x01,0xF0,
+
+	0x90,0xF6,0x66,0xE0,0xB4,0x01,0xF9,0x90,
+
+	0xF6,0x30,0xE0,0x54,0x0F,0xFB,0xA3,0xE0,
+
+	0x75,0xF0,0x10,0xA4,0xFF,0x90,0xF6,0x30,
+
+	0xE0,0xFD,0xC4,0x54,0x0F,0x7C,0x00,0x2F,
+
+	0xFF,0xEC,0x35,0xF0,0xFE,0xE4,0xFD,0x90,
+
+	0x44,0x18,0x12,0x4B,0x6C,0xEB,0xB4,0x0F,
+
+	0x16,0x90,0x44,0x18,0xE0,0xFC,0xA3,0xE0,
+
+	0xFD,0xA3,0xE0,0xFE,0xA3,0xE0,0xFF,0x90,
+
+	0x44,0x1C,0x12,0x4B,0x6C,0x80,0x25,0x90,
+
+	0x44,0x18,0xE0,0xFC,0xA3,0xE0,0xFD,0xA3,
+
+	0xE0,0xFE,0xA3,0xE0,0x24,0x00,0xFF,0xEE,
+
+	0x34,0x10,0xFE,0xE4,0x3D,0xFD,0xE4,0x3C,
+
+	0xFC,0xA8,0x03,0x12,0x4B,0x59,0x90,0x44,
+
+	0x1C,0x12,0x4B,0x6C,0x90,0x44,0x20,0xE0,
+
+	0xFC,0xA3,0xE0,0xFD,0xA3,0xE0,0xFE,0xA3,
+
+	0xE0,0xFF,0x90,0x44,0x1C,0xE0,0xF8,0xA3,
+
+	0xE0,0xF9,0xA3,0xE0,0xFA,0xA3,0xE0,0xFB,
+
+	0xD3,0x12,0x4B,0x21,0x40,0x48,0x90,0x44,
+
+	0x20,0xE0,0xFC,0xA3,0xE0,0xFD,0xA3,0xE0,
+
+	0xFE,0xA3,0xE0,0xFF,0x90,0x44,0x24,0x12,
+
+	0x4B,0x6C,0x90,0x43,0xF5,0xE0,0xFF,0xA3,
+
+	0xE0,0x90,0x43,0xF7,0xCF,0xF0,0xA3,0xEF,
+
+	0xF0,0x90,0x44,0x1C,0xE0,0xFC,0xA3,0xE0,
+
+	0xFD,0xA3,0xE0,0xFE,0xA3,0xE0,0xFF,0x90,
+
+	0x44,0x20,0x12,0x4B,0x6C,0x90,0x44,0x16,
+
+	0xE0,0xFF,0xA3,0xE0,0x90,0x43,0xF5,0xCF,
+
+	0xF0,0xA3,0xEF,0xF0,0x80,0x45,0x90,0x44,
+
+	0x24,0xE0,0xFC,0xA3,0xE0,0xFD,0xA3,0xE0,
+
+	0xFE,0xA3,0xE0,0xFF,0x90,0x44,0x1C,0xE0,
+
+	0xF8,0xA3,0xE0,0xF9,0xA3,0xE0,0xFA,0xA3,
+
+	0xE0,0xFB,0xD3,0x12,0x4B,0x21,0x40,0x23,
+
+	0x90,0x44,0x1C,0xE0,0xFC,0xA3,0xE0,0xFD,
+
+	0xA3,0xE0,0xFE,0xA3,0xE0,0xFF,0x90,0x44,
+
+	0x24,0x12,0x4B,0x6C,0x90,0x44,0x16,0xE0,
+
+	0xFF,0xA3,0xE0,0x90,0x43,0xF7,0xCF,0xF0,
+
+	0xA3,0xEF,0xF0,0x90,0x44,0x17,0xE0,0x04,
+
+	0xF0,0x70,0x06,0x90,0x44,0x16,0xE0,0x04,
+
+	0xF0,0x02,0x6E,0xF5,0x22,0x12,0xA5,0x58,
+
+	0x12,0x99,0xA0,0x12,0x88,0x66,0x12,0x79,
+
+	0x8A,0x90,0xF7,0x8E,0x74,0x01,0xF0,0x90,
+
+	0xF7,0x91,0xF0,0x90,0xF7,0x31,0xE0,0x60,
+
+	0x08,0x90,0xF5,0xA9,0xE0,0xFF,0x12,0xA3,
+
+	0xFB,0xE4,0x90,0x44,0xCF,0xF0,0x12,0x87,
+
+	0x8B,0x12,0x95,0x68,0x12,0xA8,0x4D,0x12,
+
+	0x78,0x57,0x90,0x42,0x1B,0xE0,0x64,0x01,
+
+	0x70,0x34,0x90,0xF1,0x33,0xE0,0x70,0x2E,
+
+	0x90,0xF1,0x35,0xE0,0x70,0x28,0x90,0xF4,
+
+	0xC1,0xE0,0x64,0x02,0x70,0x20,0x90,0xF9,
+
+	0x00,0xE0,0x60,0x1A,0x90,0xF0,0x2B,0xE0,
+
+	0x70,0x14,0x90,0x42,0xFD,0xE0,0x70,0x0E,
+
+	0x90,0x43,0x4C,0xE0,0x60,0x08,0x90,0xFD,
+
+	0xA2,0x74,0x01,0xF0,0x80,0x05,0x90,0xFD,
+
+	0xA2,0xE4,0xF0,0x90,0xF5,0x4E,0xE0,0x60,
+
+	0x36,0xA3,0xE0,0x60,0x32,0x90,0xF9,0x03,
+
+	0xE0,0xFF,0x90,0xF4,0xC1,0xE0,0x6F,0x70,
+
+	0x23,0x90,0xF9,0x05,0xE0,0xB4,0x01,0x0A,
+
+	0xA3,0xE0,0xFF,0x90,0xF4,0xC4,0xE0,0xB5,
+
+	0x07,0x12,0x90,0xF9,0x05,0xE0,0x70,0x0F,
+
+	0x90,0xF9,0x07,0xE0,0xFF,0x90,0xF4,0xC5,
+
+	0xE0,0x6F,0x60,0x03,0x12,0xAF,0x97,0x7D,
+
+	0x00,0x7C,0x07,0xE4,0xFF,0x12,0xAB,0xED,
+
+	0x90,0xF9,0x99,0xE0,0x60,0x0E,0x90,0xF2,
+
+	0x1B,0x74,0x0C,0xF0,0x90,0x42,0x5F,0x74,
+
+	0x01,0xF0,0x80,0x06,0x90,0xF2,0x1B,0x74,
+
+	0x0D,0xF0,0x90,0xFD,0x33,0xE4,0xF0,0x04,
+
+	0xF0,0x90,0xFD,0x36,0xE0,0xB4,0x01,0xF9,
+
+	0x12,0xA3,0xB2,0x12,0xA5,0x15,0x90,0x43,
+
+	0xBC,0xE0,0x64,0x01,0x60,0x1E,0x90,0x43,
+
+	0xDD,0xE0,0xFF,0x90,0xFD,0x54,0xE0,0xC3,
+
+	0x9F,0x50,0x08,0x90,0x44,0xCA,0x74,0x01,
+
+	0xF0,0x80,0x09,0x90,0x44,0xCA,0xE0,0xB4,
+
+	0x01,0x02,0xE4,0xF0,0x12,0x82,0x1E,0x90,
+
+	0x44,0xAA,0xE0,0xB4,0x01,0x08,0x12,0x9E,
+
+	0xF5,0x12,0x78,0x57,0x80,0xF1,0x90,0x43,
+
+	0xDE,0xE0,0xB4,0x01,0x11,0x90,0xF5,0x4E,
+
+	0xE0,0x64,0x01,0x60,0x09,0xA3,0xE0,0x64,
+
+	0x01,0x60,0x03,0x12,0xAF,0x97,0x90,0x44,
+
+	0xCF,0xE0,0x75,0xF0,0x50,0x84,0xE5,0xF0,
+
+	0x70,0x03,0x12,0x79,0x8A,0x12,0x99,0xA0,
+
+	0x12,0x88,0x66,0x90,0x44,0xCF,0xE0,0x04,
+
+	0xF0,0xE0,0xC3,0x94,0xFA,0x50,0x03,0x02,
+
+	0x70,0x77,0x90,0x43,0xDE,0x74,0x01,0xF0,
+
+	0x90,0x42,0x0D,0xE0,0x64,0x01,0x60,0x09,
+
+	0x90,0x43,0x8D,0xE0,0x70,0x03,0x12,0x7E,
+
+	0x10,0x90,0x43,0xBB,0x74,0x01,0xF0,0x22,
+
+	0x90,0x41,0xEF,0xE0,0xD3,0x94,0x01,0x40,
+
+	0x0E,0x90,0xFD,0x0F,0x74,0x07,0xF0,0x90,
+
+	0xFD,0x29,0x74,0x01,0xF0,0x80,0x0A,0x90,
+
+	0xFD,0x0F,0xE4,0xF0,0x90,0xFD,0x29,0x04,
+
+	0xF0,0x90,0x42,0x46,0xE0,0x60,0x03,0x02,
+
+	0x72,0xA0,0x90,0x44,0xA6,0xE0,0xFE,0xA3,
+
+	0xE0,0xFF,0x7C,0x00,0x7D,0x64,0x12,0x4A,
+
+	0x23,0xED,0x4C,0x60,0x03,0x02,0x72,0xA0,
+
+	0x90,0xF9,0x80,0xE0,0xB4,0x01,0x15,0x90,
+
+	0x42,0x4C,0xE0,0x70,0x0F,0x04,0xF0,0x90,
+
+	0xF9,0x80,0xE4,0xF0,0xFF,0x7E,0x05,0x12,
+
+	0xAF,0x5E,0x80,0x7B,0x90,0xF9,0x80,0xE0,
+
+	0xB4,0x01,0x17,0x90,0x42,0x4C,0xE0,0xB4,
+
+	0x01,0x10,0x74,0x01,0xF0,0x90,0xF9,0x80,
+
+	0xE4,0xF0,0xFF,0x7E,0x05,0x12,0xAF,0x5E,
+
+	0x80,0x5D,0x90,0xF9,0x80,0xE0,0x70,0x57,
+
+	0x90,0x42,0x4C,0xE0,0x64,0x01,0x70,0x4F,
+
+	0xA2,0xAF,0x33,0x90,0x44,0xCC,0xF0,0xE4,
+
+	0x90,0x42,0x4C,0xF0,0xC2,0xAF,0x90,0xF7,
+
+	0x14,0xF0,0x7F,0xD4,0x7E,0x27,0x12,0xAF,
+
+	0x5E,0x90,0xF9,0x9D,0x74,0x01,0xF0,0x90,
+
+	0xF7,0x16,0xF0,0x90,0xF7,0x11,0xE4,0xF0,
+
+	0x74,0xFF,0xFF,0xFE,0x12,0xAF,0x5E,0x90,
+
+	0xF9,0x9D,0xE4,0xF0,0x90,0xF7,0x14,0x04,
+
+	0xF0,0x90,0xF7,0x0D,0xF0,0x90,0xF7,0x86,
+
+	0xF0,0xA3,0xF0,0x90,0xF7,0x11,0xF0,0x90,
+
+	0x44,0xCC,0xE0,0x24,0xFF,0x92,0xAF,0x90,
+
+	0x44,0xA7,0xE0,0x04,0xF0,0x70,0x06,0x90,
+
+	0x44,0xA6,0xE0,0x04,0xF0,0x90,0x42,0x44,
+
+	0xE0,0x70,0x0B,0x90,0x42,0x56,0xE0,0x70,
+
+	0x05,0x12,0xAD,0xFF,0x80,0x09,0x90,0xF0,
+
+	0x01,0xE0,0x60,0x03,0x12,0x83,0x14,0x90,
+
+	0x44,0xA6,0xE0,0xFE,0xA3,0xE0,0xFF,0x7C,
+
+	0x00,0x7D,0x0A,0x12,0x4A,0x23,0xED,0x4C,
+
+	0x70,0x13,0x90,0x43,0xBE,0xE0,0x60,0x0D,
+
+	0x90,0x41,0xD7,0xE0,0xB4,0x23,0x03,0x12,
+
+	0x69,0x1E,0x12,0xA5,0x99,0x90,0xF9,0x99,
+
+	0xE0,0x90,0x41,0xCE,0xF0,0x90,0x42,0x42,
+
+	0xE0,0x70,0x06,0x90,0x42,0x43,0xE0,0x60,
+
+	0x04,0x7F,0x01,0x80,0x02,0x7F,0x00,0x90,
+
+	0x41,0xCD,0xEF,0xF0,0x90,0x44,0xA6,0xE0,
+
+	0xFE,0xA3,0xE0,0xFF,0x7C,0x00,0x7D,0x32,
+
+	0x12,0x4A,0x23,0xED,0x4C,0x70,0x0E,0x12,
+
+	0x8A,0x18,0x12,0x89,0x40,0x90,0x43,0x8D,
+
+	0xE0,0x60,0x02,0x14,0xF0,0xC2,0xCF,0x22,
+
+	0xE4,0x90,0x43,0xDE,0xF0,0x12,0xAE,0xFD,
+
+	0xE4,0x90,0x42,0xFB,0xF0,0x90,0x42,0xF9,
+
+	0xF0,0xA3,0xF0,0x12,0x8E,0x1F,0x90,0x42,
+
+	0xF8,0x74,0x01,0xF0,0x90,0x43,0xDF,0xE0,
+
+	0x60,0x0A,0x90,0xF1,0x2F,0x74,0x01,0xF0,
+
+	0x90,0xF1,0x0A,0xF0,0x90,0xF7,0x3C,0xE0,
+
+	0x70,0x03,0xA3,0x04,0xF0,0x12,0x9A,0xAE,
+
+	0x12,0xAF,0x90,0x12,0x7B,0xDB,0xE4,0xFF,
+
+	0x12,0xA7,0xB4,0x90,0xFD,0x32,0xE0,0x90,
+
+	0xFD,0x92,0xF0,0x90,0xFD,0x31,0xE0,0x90,
+
+	0xFD,0x91,0xF0,0x90,0xF2,0x1B,0x74,0x09,
+
+	0xF0,0xE4,0xFF,0x12,0x62,0x28,0x90,0xF2,
+
+	0x1B,0x74,0x0A,0xF0,0x90,0xFD,0xA1,0xE0,
+
+	0x60,0x06,0x90,0xF7,0x81,0x74,0x40,0xF0,
+
+	0x7F,0x04,0x12,0xAE,0x43,0x90,0xF5,0x3B,
+
+	0x74,0x01,0xF0,0xE4,0xFF,0x12,0xA7,0xB4,
+
+	0x12,0x7F,0x1C,0x90,0x43,0xBD,0xE0,0x60,
+
+	0x21,0x90,0xF7,0x3C,0xE0,0x70,0x16,0x90,
+
+	0xF7,0x40,0xF0,0x90,0xF5,0x54,0x04,0xF0,
+
+	0xE4,0x90,0x44,0x9E,0xF0,0x90,0x44,0x9D,
+
+	0xE0,0x90,0xF5,0x52,0xF0,0xE4,0x90,0x43,
+
+	0xB9,0xF0,0x90,0x41,0xCD,0x74,0x01,0xF0,
+
+	0x90,0x42,0x42,0xF0,0x12,0x7E,0x10,0x12,
+
+	0xAD,0xCE,0x7F,0x0A,0x12,0xAE,0x43,0x90,
+
+	0xF5,0xC8,0x74,0x01,0xF0,0x90,0xF7,0x8E,
+
+	0xF0,0x90,0x44,0x3B,0xF0,0x90,0x42,0x41,
+
+	0xE0,0x64,0x01,0x70,0x6D,0x90,0x43,0xD0,
+
+	0xE0,0x64,0x01,0x70,0x65,0x90,0xF0,0x2B,
+
+	0xE0,0x64,0x01,0x70,0x5D,0x90,0xF6,0x08,
+
+	0xE0,0x70,0x57,0xC2,0xEB,0x90,0xF7,0x8B,
+
+	0x74,0x02,0xF0,0x7F,0x01,0x12,0x80,0x20,
+
+	0x90,0x42,0x33,0xE0,0x90,0x44,0xCE,0xF0,
+
+	0x90,0xFD,0xA5,0x74,0x01,0xF0,0x90,0x43,
+
+	0xBC,0xF0,0x7F,0x08,0x12,0xAE,0x43,0x7F,
+
+	0x01,0x12,0x80,0x20,0x90,0x42,0x33,0xE0,
+
+	0xFF,0x90,0x44,0xCE,0xE0,0xC3,0x9F,0x40,
+
+	0x0B,0x90,0xFD,0xA5,0xE4,0xF0,0x90,0x43,
+
+	0xBC,0xF0,0x80,0x0A,0x90,0xFD,0xA5,0x74,
+
+	0x01,0xF0,0x90,0x43,0xBC,0xF0,0xE4,0x90,
+
+	0x43,0xD0,0xF0,0x90,0xF7,0x8B,0x04,0xF0,
+
+	0xD2,0xEB,0x12,0xA5,0x15,0x90,0xF7,0x31,
+
+	0xE0,0x60,0x05,0x7F,0x01,0x12,0xA3,0xFB,
+
+	0xE4,0x90,0x43,0xC7,0xF0,0x90,0x42,0xFD,
+
+	0x04,0xF0,0x12,0xAF,0x36,0x90,0xF2,0x1B,
+
+	0x74,0x0B,0xF0,0x22,0x90,0x42,0x5C,0xE0,
+
+	0x70,0x1A,0xA3,0xE0,0x64,0x0C,0x60,0x05,
+
+	0xE0,0x64,0x0D,0x70,0x22,0x90,0xF5,0x68,
+
+	0xE0,0xB4,0x0A,0x1B,0x90,0x42,0x5C,0x74,
+
+	0x01,0xF0,0x80,0x13,0x90,0x42,0x5D,0xE0,
+
+	0xB4,0x0C,0x0C,0x90,0xF5,0x69,0xE0,0xB4,
+
+	0x05,0x05,0xE4,0x90,0x42,0x5C,0xF0,0x90,
+
+	0x42,0x5C,0xE0,0xB4,0x01,0x19,0xA3,0xE0,
+
+	0xB4,0x0C,0x14,0x90,0xF5,0xC1,0xE0,0xB4,
+
+	0x01,0x0D,0x90,0x42,0x5D,0x74,0x03,0xF0,
+
+	0x90,0xF5,0x66,0xF0,0x02,0x75,0x99,0x90,
+
+	0x42,0x5C,0xE0,0xB4,0x01,0x0F,0xA3,0xE0,
+
+	0xB4,0x0D,0x0A,0x74,0x03,0xF0,0x90,0xF5,
+
+	0x66,0xF0,0x02,0x75,0x99,0x90,0x42,0x5C,
+
+	0xE0,0x70,0x15,0xA3,0xE0,0xB4,0x0C,0x10,
+
+	0x90,0xF5,0xC1,0xE0,0xB4,0x01,0x09,0x90,
+
+	0xF5,0x66,0x74,0x0C,0xF0,0x02,0x75,0x99,
+
+	0x90,0x42,0x5C,0xE0,0x70,0x16,0xA3,0xE0,
+
+	0xB4,0x0C,0x11,0x90,0xF5,0x69,0xE0,0xC3,
+
+	0x94,0x05,0x50,0x08,0x90,0xF5,0x66,0x74,
+
+	0x0C,0xF0,0x80,0x64,0x90,0x42,0x5C,0xE0,
+
+	0x64,0x01,0x70,0x1C,0xA3,0xE0,0xB4,0x0C,
+
+	0x17,0x90,0xF5,0xC1,0xE0,0x70,0x11,0x90,
+
+	0xF5,0x68,0xE0,0xC3,0x94,0x0A,0x50,0x08,
+
+	0x90,0xF5,0x66,0x74,0x0C,0xF0,0x80,0x40,
+
+	0x90,0x42,0x5C,0xE0,0x64,0x01,0x70,0x1E,
+
+	0xA3,0xE0,0xB4,0x0C,0x19,0x90,0xF5,0xC1,
+
+	0xE0,0x70,0x13,0x90,0xF5,0x68,0xE0,0xB4,
+
+	0x0A,0x0C,0x90,0x42,0x5D,0x74,0x03,0xF0,
+
+	0x90,0xF5,0x66,0xF0,0x80,0x1A,0x90,0x42,
+
+	0x5D,0xE0,0xB4,0x0D,0x08,0x90,0xF5,0x66,
+
+	0x74,0x0D,0xF0,0x80,0x0B,0x90,0x42,0x5D,
+
+	0xE0,0x04,0xF0,0xE0,0x90,0xF5,0x66,0xF0,
+
+	0x90,0x42,0x5D,0xE0,0x25,0xE0,0x24,0xA3,
+
+	0xF5,0x82,0xE4,0x34,0x42,0xF5,0x83,0xE0,
+
+	0xA3,0xE0,0x90,0xF5,0x5B,0xF0,0x90,0x42,
+
+	0x5D,0xE0,0x25,0xE0,0x24,0xBF,0xF5,0x82,
+
+	0xE4,0x34,0x42,0xF5,0x83,0xE0,0xA3,0xE0,
+
+	0x90,0xF5,0x5C,0xF0,0x90,0x42,0x5D,0xE0,
+
+	0x25,0xE0,0x24,0xDB,0xF5,0x82,0xE4,0x34,
+
+	0x42,0xF5,0x83,0xE0,0xA3,0xE0,0x90,0xF5,
+
+	0x5D,0xF0,0xA3,0xE4,0xF0,0x22,0x74,0xFF,
+
+	0x90,0x44,0xB9,0xF0,0xA3,0xF0,0x90,0x43,
+
+	0xE2,0xE0,0xFE,0xA3,0xE0,0xFF,0xC3,0x90,
+
+	0x43,0xE5,0xE0,0x9F,0xFF,0x90,0x43,0xE4,
+
+	0xE0,0x9E,0xFE,0x90,0x42,0x1D,0xE0,0xFD,
+
+	0x7C,0x00,0x12,0x4A,0x11,0x90,0x42,0x1C,
+
+	0xE0,0xFD,0xEF,0xA8,0x05,0x08,0x80,0x05,
+
+	0xCE,0xC3,0x13,0xCE,0x13,0xD8,0xF9,0xFF,
+
+	0x90,0x42,0x1E,0xE0,0x2F,0x90,0x44,0xB7,
+
+	0xF0,0x90,0x43,0xE1,0xE0,0x70,0x34,0x90,
+
+	0x43,0xE4,0xE0,0xFF,0xA3,0xE0,0x90,0x43,
+
+	0xF3,0xCF,0xF0,0xA3,0xEF,0xF0,0x90,0x43,
+
+	0xE2,0xE0,0xFF,0xA3,0xE0,0x90,0x43,0xF1,
+
+	0xCF,0xF0,0xA3,0xEF,0xF0,0x12,0x6E,0xC5,
+
+	0x90,0x43,0xF5,0xE0,0xFE,0xA3,0xE0,0xFF,
+
+	0xE4,0xFC,0xFD,0x90,0x43,0xEA,0x12,0x4B,
+
+	0x6C,0x80,0x3F,0x90,0x43,0xE1,0xE0,0xB4,
+
+	0x01,0x16,0x12,0x6E,0xC5,0x90,0x43,0xF5,
+
+	0xE0,0xFE,0xA3,0xE0,0xFF,0xE4,0xFC,0xFD,
+
+	0x90,0x43,0xEA,0x12,0x4B,0x6C,0x80,0x22,
+
+	0x90,0x43,0xE4,0xE0,0xFE,0xA3,0xE0,0xFF,
+
+	0x90,0x43,0xE3,0xE0,0x2F,0xFF,0x90,0x43,
+
+	0xE2,0xE0,0x3E,0xC3,0x13,0xFE,0xEF,0x13,
+
+	0xFF,0xE4,0xFC,0xFD,0x90,0x43,0xEA,0x12,
+
+	0x4B,0x6C,0x12,0x86,0xAE,0x90,0x43,0xE3,
+
+	0xE0,0x24,0xB0,0xF0,0x90,0x43,0xE2,0xE0,
+
+	0x34,0x02,0xF0,0x90,0x43,0xE5,0xE0,0x24,
+
+	0xB0,0xF0,0x90,0x43,0xE4,0xE0,0x34,0x02,
+
+	0xF0,0x90,0x43,0xE1,0xE0,0xFF,0x70,0x20,
+
+	0x90,0x44,0xB7,0xE0,0xA3,0xF0,0x90,0xF1,
+
+	0x09,0xF0,0x90,0x43,0xE9,0xE0,0x90,0xF1,
+
+	0x0E,0xF0,0x90,0x43,0xE8,0xE0,0x90,0xF1,
+
+	0x0F,0xF0,0xA3,0x74,0x01,0xF0,0x80,0x34,
+
+	0xEF,0x64,0x01,0x70,0x2F,0x90,0x43,0xEE,
+
+	0xE0,0x70,0x0A,0x90,0x44,0xB7,0xE0,0x90,
+
+	0xF1,0x0B,0xF0,0x80,0x0B,0x90,0x44,0xB8,
+
+	0xE0,0xFF,0xC3,0x13,0x90,0xF1,0x0B,0xF0,
+
+	0x90,0x43,0xE9,0xE0,0x90,0xF1,0x12,0xF0,
+
+	0x90,0x43,0xE8,0xE0,0x90,0xF1,0x13,0xF0,
+
+	0xA3,0x74,0x01,0xF0,0x90,0x43,0xE1,0xE0,
+
+	0x04,0xF0,0x22,0x90,0x42,0x59,0xE0,0x70,
+
+	0x1A,0xA3,0xE0,0x64,0x0C,0x60,0x05,0xE0,
+
+	0x64,0x0D,0x70,0x22,0x90,0xF4,0x1B,0xE0,
+
+	0xB4,0x0A,0x1B,0x90,0x42,0x59,0x74,0x01,
+
+	0xF0,0x80,0x13,0x90,0x42,0x5A,0xE0,0xB4,
+
+	0x0C,0x0C,0x90,0xF4,0x1C,0xE0,0xB4,0x0A,
+
+	0x05,0xE4,0x90,0x42,0x59,0xF0,0x90,0x42,
+
+	0x59,0xE0,0xB4,0x01,0x19,0xA3,0xE0,0xB4,
+
+	0x0C,0x14,0x90,0xF5,0xBA,0xE0,0xB4,0x01,
+
+	0x0D,0x90,0x42,0x5A,0x74,0x03,0xF0,0x90,
+
+	0xF4,0x19,0xF0,0x02,0x78,0x20,0x90,0x42,
+
+	0x59,0xE0,0xB4,0x01,0x0F,0xA3,0xE0,0xB4,
+
+	0x0D,0x0A,0x74,0x03,0xF0,0x90,0xF4,0x19,
+
+	0xF0,0x02,0x78,0x20,0x90,0x42,0x59,0xE0,
+
+	0x70,0x15,0xA3,0xE0,0xB4,0x0C,0x10,0x90,
+
+	0xF5,0xBA,0xE0,0xB4,0x01,0x09,0x90,0xF4,
+
+	0x19,0x74,0x0C,0xF0,0x02,0x78,0x20,0x90,
+
+	0x42,0x59,0xE0,0x70,0x16,0xA3,0xE0,0xB4,
+
+	0x0C,0x11,0x90,0xF4,0x1C,0xE0,0xC3,0x94,
+
+	0x0A,0x50,0x08,0x90,0xF4,0x19,0x74,0x0C,
+
+	0xF0,0x80,0x64,0x90,0x42,0x59,0xE0,0x64,
+
+	0x01,0x70,0x1C,0xA3,0xE0,0xB4,0x0C,0x17,
+
+	0x90,0xF5,0xBA,0xE0,0x70,0x11,0x90,0xF4,
+
+	0x1B,0xE0,0xC3,0x94,0x0A,0x50,0x08,0x90,
+
+	0xF4,0x19,0x74,0x0C,0xF0,0x80,0x40,0x90,
+
+	0x42,0x59,0xE0,0x64,0x01,0x70,0x1E,0xA3,
+
+	0xE0,0xB4,0x0C,0x19,0x90,0xF5,0xBA,0xE0,
+
+	0x70,0x13,0x90,0xF4,0x1B,0xE0,0xB4,0x0A,
+
+	0x0C,0x90,0x42,0x5A,0x74,0x03,0xF0,0x90,
+
+	0xF4,0x19,0xF0,0x80,0x1A,0x90,0x42,0x5A,
+
+	0xE0,0xB4,0x0D,0x08,0x90,0xF4,0x19,0x74,
+
+	0x0D,0xF0,0x80,0x0B,0x90,0x42,0x5A,0xE0,
+
+	0x04,0xF0,0xE0,0x90,0xF4,0x19,0xF0,0x90,
+
+	0x42,0x5A,0xE0,0x24,0x79,0xF5,0x82,0xE4,
+
+	0x34,0x42,0xF5,0x83,0xE0,0x90,0xF4,0x08,
+
+	0xF0,0x90,0x42,0x5A,0xE0,0x24,0x87,0xF5,
+
+	0x82,0xE4,0x34,0x42,0xF5,0x83,0xE0,0x90,
+
+	0xF4,0x09,0xF0,0x90,0x42,0x5A,0xE0,0x24,
+
+	0x95,0xF5,0x82,0xE4,0x34,0x42,0xF5,0x83,
+
+	0xE0,0x90,0xF4,0x0A,0xF0,0x22,0x90,0x42,
+
+	0x34,0xE0,0x70,0x03,0x02,0x79,0x89,0x90,
+
+	0xF0,0x2B,0xE0,0x70,0x16,0x90,0xF5,0x3E,
+
+	0xE0,0xD3,0x94,0x20,0x40,0x0D,0x90,0xF2,
+
+	0x17,0x74,0xFE,0xF0,0x90,0xF7,0x87,0x74,
+
+	0x01,0xF0,0x22,0x90,0xF7,0x32,0xE0,0x64,
+
+	0x01,0x70,0x2D,0x90,0x42,0x33,0xE0,0xFE,
+
+	0x90,0x44,0x9F,0xE0,0xFD,0xD3,0x9E,0x40,
+
+	0x05,0xED,0x9E,0xFF,0x80,0x0C,0x90,0x44,
+
+	0x9F,0xE0,0xFE,0x90,0x42,0x33,0xE0,0xC3,
+
+	0x9E,0xFF,0xEF,0xC3,0x94,0x0A,0x50,0x08,
+
+	0x90,0x44,0x9F,0xE0,0x90,0x42,0x33,0xF0,
+
+	0x90,0x42,0x33,0xE0,0xFE,0xC3,0x94,0x23,
+
+	0x50,0x07,0x90,0xF2,0x17,0x74,0xFE,0xF0,
+
+	0x22,0xEE,0xC3,0x94,0x28,0x50,0x13,0x90,
+
+	0xF2,0x17,0xE0,0xB4,0xFE,0x05,0xE0,0x64,
+
+	0xA6,0x60,0x07,0x90,0xF2,0x17,0x74,0xFE,
+
+	0xF0,0x22,0x90,0x42,0x33,0xE0,0xC3,0x94,
+
+	0x2D,0x50,0x13,0x90,0xF2,0x17,0xE0,0xB4,
+
+	0xFE,0x05,0xE0,0x64,0xA6,0x60,0x07,0x90,
+
+	0xF2,0x17,0x74,0xA6,0xF0,0x22,0x90,0x42,
+
+	0x33,0xE0,0xFE,0xC3,0x94,0x37,0x50,0x07,
+
+	0x90,0xF2,0x17,0x74,0xA6,0xF0,0x22,0xEE,
+
+	0xC3,0x94,0x3C,0x50,0x13,0x90,0xF2,0x17,
+
+	0xE0,0xB4,0xA6,0x05,0xE0,0x64,0x26,0x60,
+
+	0x07,0x90,0xF2,0x17,0x74,0xA6,0xF0,0x22,
+
+	0x90,0x42,0x33,0xE0,0xC3,0x94,0x41,0x50,
+
+	0x13,0x90,0xF2,0x17,0xE0,0xB4,0xA6,0x05,
+
+	0xE0,0x64,0x26,0x60,0x07,0x90,0xF2,0x17,
+
+	0x74,0x26,0xF0,0x22,0x90,0x42,0x33,0xE0,
+
+	0xFE,0xC3,0x94,0x4B,0x50,0x07,0x90,0xF2,
+
+	0x17,0x74,0x26,0xF0,0x22,0xEE,0xC3,0x94,
+
+	0x50,0x50,0x13,0x90,0xF2,0x17,0xE0,0xB4,
+
+	0x26,0x05,0xE0,0x64,0x25,0x60,0x07,0x90,
+
+	0xF2,0x17,0x74,0x26,0xF0,0x22,0x90,0x42,
+
+	0x33,0xE0,0xC3,0x94,0x55,0x50,0x13,0x90,
+
+	0xF2,0x17,0xE0,0xB4,0x26,0x05,0xE0,0x64,
+
+	0x25,0x60,0x07,0x90,0xF2,0x17,0x74,0x25,
+
+	0xF0,0x22,0x90,0xF2,0x17,0x74,0x25,0xF0,
+
+	0x22,0x90,0xF6,0x08,0xE0,0x90,0x44,0xA3,
+
+	0xF0,0x90,0xFD,0x29,0xE0,0x90,0x44,0xA4,
+
+	0xF0,0xE4,0xA3,0xF0,0x90,0x41,0xD5,0xE0,
+
+	0x70,0x05,0x90,0x43,0xC7,0xF0,0x22,0x90,
+
+	0xF5,0x4C,0xE0,0xFF,0x90,0xF5,0x41,0xE0,
+
+	0x4F,0x70,0x03,0x02,0x7A,0xB2,0x90,0x44,
+
+	0x62,0x74,0x02,0xF0,0xA3,0x74,0x39,0xF0,
+
+	0xE4,0xFB,0xFA,0xFD,0xFF,0x12,0x7C,0xF8,
+
+	0x90,0x44,0xA2,0xEF,0xF0,0xD3,0x94,0x32,
+
+	0x40,0x04,0xE0,0xFF,0x80,0x02,0x7F,0xFF,
+
+	0x90,0x44,0xA2,0xEF,0xF0,0xFD,0x90,0x44,
+
+	0x62,0xE4,0xF0,0xA3,0x74,0x32,0xF0,0xE4,
+
+	0xFB,0xFA,0x7F,0x01,0x12,0x7C,0xF8,0x90,
+
+	0x44,0xA1,0xEF,0xF0,0xD3,0x94,0x0A,0x40,
+
+	0x58,0x90,0xF1,0x14,0xE0,0x70,0x1E,0x04,
+
+	0xF0,0x90,0x43,0xDC,0xE0,0x90,0xF1,0x12,
+
+	0xF0,0x90,0x43,0xDB,0xE0,0x90,0xF1,0x13,
+
+	0xF0,0x90,0xF1,0x0B,0xE4,0xF0,0x90,0xF1,
+
+	0x0A,0x04,0xF0,0x80,0x34,0x90,0xF1,0x10,
+
+	0xE0,0x70,0x2E,0x90,0x43,0xDC,0xE0,0xFF,
+
+	0x90,0xF1,0x12,0xE0,0x6F,0x60,0x22,0x90,
+
+	0x43,0xDB,0xE0,0xFE,0x90,0xF1,0x13,0xE0,
+
+	0x6E,0x60,0x16,0x90,0xF1,0x10,0x74,0x01,
+
+	0xF0,0x90,0xF1,0x0E,0xEF,0xF0,0xA3,0xEE,
+
+	0xF0,0x90,0xF1,0x09,0xE4,0xF0,0xA3,0x04,
+
+	0xF0,0x90,0x44,0xA2,0xE0,0xFD,0x90,0x44,
+
+	0x62,0x74,0x02,0xF0,0xA3,0x74,0x39,0xF0,
+
+	0x7B,0xF4,0x7A,0x01,0x7F,0x01,0x12,0x7C,
+
+	0xF8,0x90,0x44,0xA1,0xEF,0xF0,0xD3,0x94,
+
+	0x19,0x40,0x3E,0x90,0xF1,0x14,0xE0,0x70,
+
+	0x38,0x04,0xF0,0x90,0x43,0xDA,0xE0,0x90,
+
+	0xF1,0x12,0xF0,0x90,0x43,0xD9,0xE0,0x90,
+
+	0xF1,0x13,0xF0,0x90,0xF1,0x0B,0x74,0x15,
+
+	0xF0,0x90,0xF1,0x10,0x74,0x01,0xF0,0x90,
+
+	0x43,0xD8,0xE0,0x90,0xF1,0x0E,0xF0,0x90,
+
+	0x43,0xD7,0xE0,0x90,0xF1,0x0F,0xF0,0x90,
+
+	0xF1,0x09,0x74,0x10,0xF0,0xA3,0x74,0x01,
+
+	0xF0,0x22,0x7E,0x41,0x7F,0x91,0xD3,0xEF,
+
+	0x94,0x56,0xEE,0x94,0x42,0x50,0x0D,0x8F,
+
+	0x82,0x8E,0x83,0xE4,0xF0,0x0F,0xBF,0x00,
+
+	0x01,0x0E,0x80,0xEA,0x12,0xAA,0xC8,0x12,
+
+	0xAA,0xF5,0x90,0x41,0x8B,0x74,0x41,0xF0,
+
+	0xA3,0x74,0x91,0xF0,0xE4,0x90,0x43,0xBE,
+
+	0xF0,0xD2,0xAF,0xD2,0xA8,0xC2,0xDB,0xD2,
+
+	0xEC,0xF5,0x13,0xF5,0x14,0x90,0x43,0xCE,
+
+	0xF0,0xA3,0xF0,0x90,0x43,0xB8,0xF0,0x90,
+
+	0x41,0xD2,0x04,0xF0,0x90,0x42,0x0F,0x74,
+
+	0x04,0xF0,0x90,0x42,0x12,0x74,0x0A,0xF0,
+
+	0x90,0x41,0xE0,0x74,0x03,0xF0,0xE4,0x90,
+
+	0x41,0xE1,0xF0,0xF5,0xF8,0x75,0xB8,0x12,
+
+	0xD2,0x88,0xD2,0xEB,0x90,0x43,0xB6,0xF0,
+
+	0x90,0x41,0xD1,0xF0,0x90,0x43,0xBD,0x04,
+
+	0xF0,0xE4,0x90,0x41,0xE7,0xF0,0x90,0x41,
+
+	0xE6,0x04,0xF0,0x90,0x41,0xEB,0xF0,0x90,
+
+	0x41,0xEC,0x04,0xF0,0xE4,0x90,0x41,0xED,
+
+	0xF0,0x90,0x41,0xEE,0xF0,0x90,0x42,0x0E,
+
+	0x04,0xF0,0x90,0x41,0xCB,0x74,0x10,0xF0,
+
+	0x90,0x41,0xCC,0x74,0x27,0xF0,0x90,0x41,
+
+	0xF6,0x74,0x50,0xF0,0x90,0x41,0xCA,0x74,
+
+	0x01,0xF0,0x90,0x42,0x20,0x74,0x20,0xF0,
+
+	0x90,0x42,0x21,0x74,0x2C,0xF0,0x90,0x42,
+
+	0x22,0x74,0x01,0xF0,0x90,0x42,0x1C,0x74,
+
+	0x07,0xF0,0x90,0x42,0x1D,0xF0,0x90,0x42,
+
+	0x1E,0x14,0xF0,0xE4,0x90,0x43,0xE1,0xF0,
+
+	0x90,0xF6,0x2E,0x74,0x64,0xF0,0xE4,0x90,
+
+	0x42,0x3F,0xF0,0x90,0x41,0xDC,0x04,0xF0,
+
+	0x90,0x44,0x37,0x12,0x4B,0x78,0x00,0x00,
+
+	0x00,0x00,0xE4,0x90,0x41,0xF3,0xF0,0x90,
+
+	0x41,0xF4,0xF0,0x90,0x41,0xF5,0xF0,0x90,
+
+	0x41,0xC0,0x04,0xF0,0x90,0x41,0xC8,0x74,
+
+	0x10,0xF0,0x90,0x41,0xC9,0x74,0x27,0xF0,
+
+	0xE4,0x90,0x41,0xD9,0xF0,0x90,0x41,0xDA,
+
+	0xF0,0x90,0x41,0xDB,0xF0,0x90,0x43,0xC8,
+
+	0xF0,0x90,0x43,0x90,0xF0,0x90,0x41,0xE3,
+
+	0xF0,0x22,0x90,0xF4,0xC1,0xE0,0x14,0x60,
+
+	0x46,0x14,0x60,0x7C,0x24,0x02,0x60,0x03,
+
+	0x02,0x7C,0x97,0x90,0xFD,0x19,0x74,0xCA,
+
+	0xF0,0xA3,0x74,0x08,0xF0,0xA3,0x74,0x4A,
+
+	0xF0,0xA3,0x74,0x0A,0xF0,0xA3,0x74,0xCA,
+
+	0xF0,0xA3,0x74,0x0C,0xF0,0xA3,0x74,0x4A,
+
+	0xF0,0xA3,0x74,0x10,0xF0,0xA3,0x74,0xCA,
+
+	0xF0,0xA3,0x74,0x14,0xF0,0xA3,0x74,0x4A,
+
+	0xF0,0xA3,0x74,0x1A,0xF0,0xA3,0x74,0xCA,
+
+	0xF0,0xA3,0x74,0x20,0xF0,0x80,0x6F,0x90,
+
+	0xFD,0x19,0x74,0x80,0xF0,0xA3,0xE4,0xF0,
+
+	0xA3,0xF0,0xA3,0x74,0x02,0xF0,0xA3,0x74,
+
+	0x20,0xF0,0xA3,0x74,0x03,0xF0,0xA3,0x74,
+
+	0xE8,0xF0,0xA3,0x74,0x03,0xF0,0xA3,0x74,
+
+	0xB0,0xF0,0xA3,0x74,0x04,0xF0,0xA3,0x74,
+
+	0xDC,0xF0,0xA3,0x74,0x05,0xF0,0xA3,0x74,
+
+	0x34,0xF0,0xA3,0x74,0x08,0xF0,0x80,0x36,
+
+	0x90,0xFD,0x19,0x74,0x7D,0xF0,0xA3,0xE4,
+
+	0xF0,0xA3,0x74,0xB4,0xF0,0xA3,0xE4,0xF0,
+
+	0xA3,0x74,0xC8,0xF0,0xA3,0xE4,0xF0,0xA3,
+
+	0x74,0xFA,0xF0,0xA3,0xE4,0xF0,0xA3,0x74,
+
+	0x2C,0xF0,0xA3,0x74,0x01,0xF0,0xA3,0x74,
+
+	0x52,0xF0,0xA3,0x74,0x03,0xF0,0xA3,0x74,
+
+	0x34,0xF0,0xA3,0x74,0x08,0xF0,0xE4,0xFD,
+
+	0xED,0x75,0xF0,0x02,0xA4,0x24,0x19,0xFF,
+
+	0xE5,0xF0,0x34,0xFD,0xFE,0x8F,0x82,0xF5,
+
+	0x83,0xE0,0xF9,0xA3,0xE0,0xFC,0x90,0xF9,
+
+	0x00,0xE0,0x70,0x18,0xEC,0x54,0x0F,0xFB,
+
+	0xC4,0x54,0xF0,0xFB,0xE9,0xC4,0x54,0x0F,
+
+	0x4B,0x8F,0x82,0x8E,0x83,0xF0,0xEC,0xC4,
+
+	0x54,0x0F,0xA3,0xF0,0x90,0xF9,0x00,0xE0,
+
+	0x64,0x02,0x70,0x1D,0xEC,0x54,0x0F,0xFB,
+
+	0x25,0xE0,0x25,0xE0,0xFB,0xAA,0x01,0xEA,
+
+	0x13,0x13,0x54,0x3F,0x4B,0x8F,0x82,0x8E,
+
+	0x83,0xF0,0xEC,0x13,0x13,0x54,0x3F,0xA3,
+
+	0xF0,0x0D,0xED,0xB4,0x07,0xA2,0x22,0x90,
+
+	0x44,0x5E,0xEF,0xF0,0xA3,0xED,0xF0,0xE4,
+
+	0x90,0x44,0x66,0xF0,0xA3,0xF0,0xA3,0xF0,
+
+	0xA3,0xF0,0xAF,0x03,0x90,0x44,0x64,0xEA,
+
+	0xF0,0xA3,0xEF,0xF0,0x90,0x44,0x62,0xE0,
+
+	0xFE,0xA3,0xE0,0xFF,0xA3,0xE0,0xFC,0xA3,
+
+	0xE0,0xFD,0xC3,0x9F,0xEC,0x9E,0x40,0x03,
+
+	0x02,0x7D,0xC4,0x90,0xF9,0x00,0xE0,0xB4,
+
+	0x02,0x0F,0x90,0x44,0x65,0xE0,0x25,0xE0,
+
+	0xFD,0x90,0x44,0x64,0xE0,0x33,0xFC,0x80,
+
+	0x1A,0x90,0xF9,0x00,0xE0,0xB4,0x01,0x13,
+
+	0x90,0x44,0x64,0xE0,0xFE,0xA3,0xE0,0x78,
+
+	0x02,0xC3,0x33,0xCE,0x33,0xCE,0xD8,0xF9,
+
+	0xFD,0xAC,0x06,0xED,0x90,0xF5,0x50,0xF0,
+
+	0xEC,0xA3,0xF0,0x90,0xF6,0x5B,0x74,0x01,
+
+	0xF0,0x7F,0x55,0x7E,0x0D,0x12,0xAF,0x5E,
+
+	0x20,0x8C,0xFD,0x90,0xF6,0x5F,0xE0,0xFF,
+
+	0x13,0x13,0x54,0x3F,0xFF,0x90,0x44,0x67,
+
+	0xE0,0x2F,0xF0,0x90,0x44,0x66,0xE0,0x34,
+
+	0x00,0xF0,0x90,0xF6,0x5F,0xE0,0xFF,0x90,
+
+	0x44,0x69,0xE0,0xC3,0x9F,0x50,0x08,0x90,
+
+	0xF6,0x5F,0xE0,0x90,0x44,0x69,0xF0,0x90,
+
+	0x44,0x5F,0xE0,0xFF,0x90,0xF6,0x5F,0xE0,
+
+	0xD3,0x9F,0x40,0x06,0x90,0x44,0x68,0xE0,
+
+	0x04,0xF0,0x90,0x44,0x65,0xE0,0x04,0xF0,
+
+	0x70,0x06,0x90,0x44,0x64,0xE0,0x04,0xF0,
+
+	0x02,0x7D,0x15,0x90,0x44,0x66,0xE0,0xFE,
+
+	0xA3,0xE0,0x78,0x07,0xCE,0xC3,0x13,0xCE,
+
+	0x13,0xD8,0xF9,0xFF,0x90,0x44,0x69,0xE0,
+
+	0xFE,0x13,0x13,0x54,0x3F,0xFD,0xEF,0xD3,
+
+	0x9D,0x40,0x13,0xEF,0x94,0x80,0x40,0x05,
+
+	0x74,0xFF,0xF0,0x80,0x10,0xEF,0x25,0xE0,
+
+	0x90,0x44,0x69,0xF0,0x80,0x07,0xEE,0xC3,
+
+	0x13,0x90,0x44,0x69,0xF0,0x90,0x44,0x5E,
+
+	0xE0,0x70,0x06,0x90,0x44,0x69,0xE0,0xFF,
+
+	0x22,0x90,0x44,0x68,0xE0,0xFF,0x22,0x90,
+
+	0x44,0xB3,0x74,0x01,0xF0,0xA3,0x04,0xF0,
+
+	0xA3,0xF0,0x90,0x43,0x91,0xE0,0x60,0x0A,
+
+	0x90,0x42,0x53,0xE0,0x60,0x04,0x7F,0x00,
+
+	0x80,0x05,0x90,0x42,0x1F,0xE0,0xFF,0x90,
+
+	0x44,0xB6,0xEF,0xF0,0x90,0x43,0xE0,0xE0,
+
+	0x14,0x70,0x03,0x02,0x7E,0xCC,0x04,0x60,
+
+	0x03,0x02,0x7E,0xFE,0x90,0x44,0xB6,0xE0,
+
+	0x60,0x09,0xE4,0xFD,0x7F,0x02,0x12,0xAF,
+
+	0x75,0x80,0x35,0x90,0x41,0xD1,0xE0,0xB4,
+
+	0x01,0x23,0x90,0xF9,0x01,0xE0,0x90,0x44,
+
+	0xB5,0xF0,0x90,0xF9,0x00,0xE0,0xFF,0x90,
+
+	0x44,0xB3,0xF0,0x60,0x0B,0xA3,0x74,0x02,
+
+	0xF0,0xA3,0xE0,0x24,0x02,0xF0,0x80,0x05,
+
+	0xE4,0x90,0x44,0xB4,0xF0,0x90,0x44,0xB4,
+
+	0xE0,0xFF,0xA3,0xE0,0xFD,0x12,0xAF,0x75,
+
+	0x90,0xF4,0x63,0xE4,0xF0,0x90,0xF4,0x69,
+
+	0x74,0xFB,0xF0,0xA3,0xE4,0xF0,0x90,0xF4,
+
+	0x6D,0x74,0x05,0xF0,0x7F,0x01,0x12,0xAD,
+
+	0x78,0x12,0x9C,0x33,0x90,0x44,0xB6,0xE0,
+
+	0xFF,0x60,0x08,0x90,0xF9,0x00,0x74,0x01,
+
+	0xF0,0x80,0x08,0x90,0x44,0xB3,0xE0,0x90,
+
+	0xF9,0x00,0xF0,0x90,0xF5,0xC2,0x74,0x01,
+
+	0xF0,0xE4,0xF0,0xEF,0x60,0x05,0x12,0x54,
+
+	0x2E,0x80,0x32,0x90,0xF1,0x57,0xE0,0x60,
+
+	0x08,0x90,0xF1,0x49,0x74,0x01,0xF0,0xE4,
+
+	0xF0,0x7D,0xFF,0x7C,0x7F,0xE4,0xFF,0x12,
+
+	0xAB,0xED,0x90,0xF1,0x82,0xE0,0x70,0x15,
+
+	0x90,0xF1,0x57,0xE0,0x60,0x0F,0x90,0x44,
+
+	0xAA,0xE0,0xB4,0x01,0x08,0x90,0xF1,0x7C,
+
+	0xE0,0x60,0xE7,0x80,0xE5,0xE4,0x90,0x42,
+
+	0x60,0xF0,0x90,0xF1,0xB5,0xE0,0x90,0x42,
+
+	0x61,0xF0,0x90,0xF1,0xB4,0xE0,0x90,0x42,
+
+	0x62,0xF0,0x90,0xF1,0xB3,0xE0,0x90,0x42,
+
+	0x63,0xF0,0x22,0x90,0xF5,0xC8,0xE4,0xF0,
+
+	0x90,0xF5,0x75,0xF0,0x90,0xF5,0x74,0xF0,
+
+	0x90,0xF1,0xD0,0xF0,0xA3,0xF0,0xA3,0xF0,
+
+	0x90,0xF5,0x6E,0x74,0x0A,0xF0,0x90,0xF5,
+
+	0x71,0x74,0x02,0xF0,0xA3,0x74,0x27,0xF0,
+
+	0xA3,0xE4,0xF0,0x90,0x42,0x3F,0xE0,0x64,
+
+	0x01,0x60,0x03,0x02,0x7F,0xD4,0x90,0xF5,
+
+	0xF7,0xE0,0xFE,0x90,0xF5,0xF6,0xE0,0x7C,
+
+	0x00,0x24,0x00,0xFF,0xEC,0x3E,0xFE,0xEF,
+
+	0x78,0x06,0xCE,0xC3,0x13,0xCE,0x13,0xD8,
+
+	0xF9,0x90,0x44,0xCB,0xF0,0x90,0xF9,0x00,
+
+	0xE0,0xB4,0x01,0x0C,0x90,0x44,0xCB,0xE0,
+
+	0xFF,0x13,0x13,0x54,0x3F,0xF0,0x80,0x0F,
+
+	0x90,0xF9,0x00,0xE0,0xB4,0x02,0x08,0x90,
+
+	0x44,0xCB,0xE0,0xFF,0xC3,0x13,0xF0,0x90,
+
+	0x44,0xCB,0xE0,0xFF,0xC3,0x94,0x04,0x40,
+
+	0x05,0x74,0x03,0xF0,0x80,0x21,0xEF,0xC3,
+
+	0x94,0x02,0x40,0x08,0x90,0x44,0xCB,0x74,
+
+	0x02,0xF0,0x80,0x13,0xEF,0xC3,0x94,0x01,
+
+	0x40,0x08,0x90,0x44,0xCB,0x74,0x01,0xF0,
+
+	0x80,0x05,0xE4,0x90,0x44,0xCB,0xF0,0x90,
+
+	0x44,0xCB,0xE0,0xFF,0x90,0xF9,0x01,0xE0,
+
+	0xC3,0x9F,0x50,0x0F,0xE0,0x90,0x44,0xCB,
+
+	0xF0,0x80,0x08,0x90,0xF9,0x01,0xE0,0x90,
+
+	0x44,0xCB,0xF0,0x90,0x44,0xCB,0xE0,0x14,
+
+	0x60,0x0F,0x14,0x60,0x11,0x14,0x60,0x13,
+
+	0x24,0x03,0x70,0x12,0x12,0x92,0x9B,0x80,
+
+	0x0D,0x12,0x94,0xB7,0x80,0x08,0x12,0x90,
+
+	0x6C,0x80,0x03,0x12,0x94,0x05,0x90,0xF9,
+
+	0x01,0xE0,0x14,0x60,0x0E,0x14,0x60,0x0F,
+
+	0x14,0x60,0x10,0x24,0x03,0x70,0x0F,0x12,
+
+	0x9E,0x25,0x22,0x12,0x9E,0x8D,0x22,0x12,
+
+	0xA0,0x27,0x22,0x12,0xA0,0x8B,0x22,0xAA,
+
+	0x07,0xEA,0x70,0x10,0x90,0xF7,0x86,0x04,
+
+	0xF0,0xA3,0xF0,0xE4,0x90,0x44,0x41,0xF0,
+
+	0x90,0x44,0x3F,0xF0,0xEA,0x64,0x01,0x70,
+
+	0x1D,0x90,0x44,0x3F,0x04,0xF0,0x90,0xF7,
+
+	0x86,0xF0,0xA3,0xF0,0x90,0xF7,0x86,0xE0,
+
+	0x70,0x06,0x90,0xF7,0x32,0xE0,0x70,0xF4,
+
+	0x90,0xF7,0x87,0xE0,0x60,0xEE,0x90,0xF7,
+
+	0x86,0xE0,0x70,0x09,0x90,0xF7,0x31,0xE0,
+
+	0x70,0x03,0x02,0x81,0x1A,0x90,0x44,0x3B,
+
+	0xE0,0xC3,0x94,0x01,0x50,0x03,0x02,0x81,
+
+	0x1A,0x90,0xF7,0x87,0xE0,0x70,0x03,0x02,
+
+	0x81,0x1A,0x90,0xF9,0x00,0xE0,0x70,0x04,
+
+	0x7B,0x04,0x80,0x0D,0x90,0xF9,0x00,0xE0,
+
+	0xB4,0x01,0x04,0x7B,0x06,0x80,0x02,0x7B,
+
+	0x05,0x90,0xF9,0x03,0xE0,0xFF,0xC3,0xEB,
+
+	0x9F,0xFB,0x90,0xF7,0x92,0xE0,0x90,0x41,
+
+	0xBD,0xF0,0x90,0xF7,0x93,0xE0,0x90,0x41,
+
+	0xBE,0xF0,0x90,0xF7,0x94,0xE0,0x90,0x41,
+
+	0xBF,0xF0,0x90,0xF7,0x8B,0xE0,0x90,0x41,
+
+	0xC0,0xF0,0x90,0xF7,0x97,0xE0,0x90,0x44,
+
+	0x3C,0xF0,0x90,0xF7,0x96,0xE0,0x90,0x44,
+
+	0x3D,0xF0,0x90,0xF7,0x95,0xE0,0x90,0x44,
+
+	0x3E,0xF0,0x90,0x44,0x3C,0xE0,0x90,0x44,
+
+	0x42,0xF0,0x90,0x44,0x3D,0xE0,0x90,0x44,
+
+	0x43,0xF0,0xAF,0x03,0x12,0xA9,0xD9,0x90,
+
+	0x44,0x43,0xE0,0x90,0x42,0x33,0xF0,0x90,
+
+	0x41,0xBF,0xE0,0x90,0x44,0x42,0xF0,0x90,
+
+	0x41,0xBE,0xE0,0x90,0x44,0x43,0xF0,0xAF,
+
+	0x03,0x12,0xA9,0xD9,0x90,0x44,0x43,0xE0,
+
+	0x90,0x42,0x32,0xF0,0x90,0xF7,0x86,0x74,
+
+	0x01,0xF0,0xA3,0xF0,0xE4,0x90,0x44,0x41,
+
+	0xF0,0xEA,0xB4,0x01,0x05,0xE4,0x90,0x44,
+
+	0x3F,0xF0,0x22,0xAD,0x07,0x90,0x43,0x70,
+
+	0xE0,0x90,0xF5,0xDB,0xF0,0x90,0x43,0x6F,
+
+	0xE0,0xFF,0x33,0x95,0xE0,0x90,0xF5,0xDC,
+
+	0xEF,0xF0,0x90,0x43,0x65,0xE0,0x90,0xF5,
+
+	0xFA,0xF0,0x90,0xF5,0xE8,0xE4,0xF0,0x90,
+
+	0x43,0x4D,0xE0,0x90,0xF5,0xE1,0xF0,0x90,
+
+	0xF5,0xE8,0xE0,0xB4,0x01,0xF9,0x90,0xF5,
+
+	0xE8,0xE4,0xF0,0x90,0xF5,0xE1,0x74,0x0D,
+
+	0xF0,0x90,0xF5,0xE8,0xE0,0xB4,0x01,0xF9,
+
+	0x90,0x43,0x4D,0x74,0x0E,0xF0,0x90,0xF5,
+
+	0xDD,0xE0,0x90,0x44,0xBF,0xF0,0x90,0xF5,
+
+	0xDE,0xE0,0x90,0x44,0xBE,0xF0,0xE0,0xC3,
+
+	0x94,0x20,0x40,0x04,0xE0,0x24,0xC0,0xF0,
+
+	0xED,0xB4,0x01,0x1C,0x90,0x43,0x73,0xE0,
+
+	0xFE,0xA3,0xE0,0xFF,0x90,0x44,0xBF,0xE0,
+
+	0x2F,0xFF,0x90,0x44,0xBE,0xE0,0x3E,0x90,
+
+	0x43,0x75,0xF0,0xA3,0xEF,0xF0,0x80,0x1F,
+
+	0x90,0x44,0xBE,0xE0,0xFF,0xA3,0xE0,0x90,
+
+	0x43,0x75,0xCF,0xF0,0xA3,0xEF,0xF0,0x90,
+
+	0xF5,0xFB,0xE0,0x90,0x43,0x74,0xF0,0x90,
+
+	0xF5,0xFC,0xE0,0x90,0x43,0x73,0xF0,0x90,
+
+	0x43,0x76,0xE0,0x90,0xF4,0x66,0xF0,0x90,
+
+	0x43,0x75,0xE0,0x90,0xF4,0x67,0xF0,0x90,
+
+	0xF6,0x08,0xE0,0xFF,0x13,0x13,0x13,0x54,
+
+	0x1F,0x90,0xFD,0xA1,0xF0,0x90,0xF5,0xFC,
+
+	0xE0,0xFE,0x90,0xF5,0xFB,0xE0,0x7C,0x00,
+
+	0x24,0x00,0xFF,0xEC,0x3E,0xAD,0x07,0xFC,
+
+	0x90,0xF5,0x3D,0xE0,0xFE,0x90,0xF5,0x3C,
+
+	0xE0,0x7A,0x00,0x24,0x00,0xFF,0xEA,0x3E,
+
+	0xFE,0xEF,0x2D,0xFD,0xEE,0x3C,0xFF,0x33,
+
+	0x95,0xE0,0xA3,0xEF,0xF0,0xAF,0x05,0xEF,
+
+	0x90,0xF5,0x3C,0xF0,0x22,0x90,0x42,0x37,
+
+	0xE0,0x70,0x03,0x02,0x83,0x10,0xE4,0x90,
+
+	0x44,0xD4,0xF0,0x90,0x44,0xD4,0xE0,0xF9,
+
+	0xC3,0x94,0x08,0x50,0x7E,0x90,0x42,0xFB,
+
+	0xE0,0x75,0xF0,0x05,0xA4,0x24,0x64,0xFB,
+
+	0xE4,0x35,0xF0,0xFA,0xE9,0xFF,0x7E,0x00,
+
+	0x7C,0x02,0x7D,0x58,0x12,0x4A,0x11,0xEF,
+
+	0x2B,0xFF,0xEE,0x3A,0xFE,0x90,0x43,0x21,
+
+	0xE0,0xFC,0xA3,0xE0,0xFD,0x12,0x4A,0x23,
+
+	0xA3,0xEC,0xF0,0xA3,0xED,0xF0,0x12,0xAC,
+
+	0x5B,0x12,0xAD,0x5A,0x90,0x44,0xD4,0xE0,
+
+	0x70,0x03,0x12,0xA6,0x99,0x90,0x43,0x0A,
+
+	0xE0,0xFC,0xA3,0xE0,0xFD,0xA3,0xE0,0xFE,
+
+	0xA3,0xE0,0xFF,0x78,0x04,0x12,0x4B,0x32,
+
+	0x90,0x43,0x06,0xE0,0xF8,0xA3,0xE0,0xF9,
+
+	0xA3,0xE0,0xFA,0xA3,0xE0,0xFB,0xC3,0x12,
+
+	0x4B,0x21,0x50,0x0E,0x90,0x42,0xFA,0xE0,
+
+	0x04,0xF0,0x70,0x06,0x90,0x42,0xF9,0xE0,
+
+	0x04,0xF0,0x90,0x44,0xD4,0xE0,0x04,0xF0,
+
+	0x02,0x82,0x2C,0x90,0x42,0xFB,0xE0,0x04,
+
+	0xF0,0xE0,0x64,0x64,0x70,0x51,0x90,0xF9,
+
+	0x00,0xE0,0x60,0x08,0x90,0x43,0x35,0x74,
+
+	0x28,0xF0,0x80,0x06,0x90,0x43,0x35,0x74,
+
+	0x3E,0xF0,0x90,0x42,0x2B,0x74,0x01,0xF0,
+
+	0x90,0x43,0x35,0xE0,0xFF,0xD3,0x90,0x42,
+
+	0xFA,0xE0,0x9F,0x90,0x42,0xF9,0xE0,0x94,
+
+	0x00,0x40,0x0B,0xE4,0x90,0x41,0xE4,0xF0,
+
+	0x90,0x41,0xE5,0xF0,0x80,0x0A,0x90,0x41,
+
+	0xE4,0x74,0x01,0xF0,0x90,0x41,0xE5,0xF0,
+
+	0x90,0x42,0xFC,0xE0,0x04,0xF0,0xE4,0x90,
+
+	0x42,0xF9,0xF0,0xA3,0xF0,0xA3,0xF0,0x12,
+
+	0xA7,0x80,0x22,0x90,0xF0,0x02,0xE0,0x90,
+
+	0x43,0x8C,0xF0,0x90,0xF0,0x03,0xE0,0x90,
+
+	0x43,0x8B,0xF0,0x90,0xF0,0x03,0xE0,0x60,
+
+	0x04,0x7F,0xFF,0x80,0x05,0x90,0xF0,0x02,
+
+	0xE0,0xFF,0x90,0x42,0x40,0xEF,0xF0,0x90,
+
+	0xF0,0x63,0xE0,0xFE,0x90,0xF0,0x62,0xE0,
+
+	0x7C,0x00,0x24,0x00,0xFF,0xEC,0x3E,0x90,
+
+	0x43,0x9A,0xF0,0xA3,0xEF,0xF0,0x90,0x43,
+
+	0xAA,0xE0,0xFB,0x7A,0x00,0x90,0x43,0x9B,
+
+	0xE0,0x2B,0xFE,0x90,0x43,0x9A,0xE0,0x3A,
+
+	0x90,0x43,0x96,0xF0,0xA3,0xCE,0xF0,0xC3,
+
+	0x90,0x43,0x9B,0xE0,0x9B,0xFE,0x90,0x43,
+
+	0x9A,0xE0,0x9A,0x90,0x43,0x98,0xF0,0xA3,
+
+	0xCE,0xF0,0x90,0x43,0x97,0xE0,0x25,0xE0,
+
+	0xFF,0x90,0x43,0x96,0xE0,0x33,0xFE,0xD3,
+
+	0x90,0x43,0x8C,0xE0,0x9F,0x90,0x43,0x8B,
+
+	0xE0,0x9E,0x40,0x08,0x90,0x43,0x9C,0x74,
+
+	0xFC,0xF0,0x80,0x5F,0x90,0x43,0x96,0xE0,
+
+	0xFE,0xA3,0xE0,0xFF,0xD3,0x90,0x43,0x8C,
+
+	0xE0,0x9F,0x90,0x43,0x8B,0xE0,0x9E,0x40,
+
+	0x08,0x90,0x43,0x9C,0x74,0xFF,0xF0,0x80,
+
+	0x42,0x90,0x43,0x98,0xE0,0xC3,0x13,0xFE,
+
+	0xA3,0xE0,0x13,0xFF,0xC3,0x90,0x43,0x8C,
+
+	0xE0,0x9F,0x90,0x43,0x8B,0xE0,0x9E,0x50,
+
+	0x08,0x90,0x43,0x9C,0x74,0x04,0xF0,0x80,
+
+	0x22,0x90,0x43,0x98,0xE0,0xFE,0xA3,0xE0,
+
+	0xFF,0xC3,0x90,0x43,0x8C,0xE0,0x9F,0x90,
+
+	0x43,0x8B,0xE0,0x9E,0x50,0x08,0x90,0x43,
+
+	0x9C,0x74,0x01,0xF0,0x80,0x05,0xE4,0x90,
+
+	0x43,0x9C,0xF0,0x90,0xF0,0x01,0x74,0x01,
+
+	0xF0,0x22,0x90,0x43,0x6E,0xE0,0xF9,0xB4,
+
+	0x01,0x37,0x90,0x43,0x66,0xE0,0x25,0xE0,
+
+	0x24,0x58,0xF5,0x82,0xE4,0x34,0x43,0xF5,
+
+	0x83,0xE0,0xFC,0xA3,0xE0,0xFD,0x90,0x43,
+
+	0x6F,0xE0,0xFA,0xA3,0xE0,0xFB,0xC3,0xED,
+
+	0x9B,0xFD,0xEC,0x9A,0xFC,0x90,0x43,0x68,
+
+	0xE0,0x2D,0xFE,0x90,0x43,0x67,0xE0,0x3C,
+
+	0x90,0x44,0xC0,0xF0,0xA3,0xCE,0xF0,0x80,
+
+	0x72,0xE9,0xB4,0x02,0x32,0x90,0x43,0x71,
+
+	0xE0,0xFE,0xA3,0xE0,0xFF,0x90,0x43,0x62,
+
+	0xE0,0x2F,0xFF,0x90,0x43,0x61,0xE0,0x3E,
+
+	0xFE,0x90,0x43,0x67,0xE0,0xFC,0xA3,0xE0,
+
+	0xFD,0xC3,0xEF,0x9D,0xFF,0xEE,0x9C,0xFE,
+
+	0xC3,0xE4,0x9F,0xFF,0xE4,0x9E,0x90,0x44,
+
+	0xC0,0xF0,0xA3,0xEF,0xF0,0x80,0x3C,0x90,
+
+	0x43,0x6E,0xE0,0xB4,0x03,0x35,0x90,0x43,
+
+	0x66,0xE0,0x25,0xE0,0x24,0x58,0xF5,0x82,
+
+	0xE4,0x34,0x43,0xF5,0x83,0xE0,0xFE,0xA3,
+
+	0xE0,0xFF,0x90,0x43,0x6F,0xE0,0xFC,0xA3,
+
+	0xE0,0xFD,0xC3,0xEF,0x9D,0xFF,0xEE,0x9C,
+
+	0xFE,0x90,0x43,0x68,0xE0,0x2F,0xFF,0x90,
+
+	0x43,0x67,0xE0,0x3E,0x90,0x44,0xC0,0xF0,
+
+	0xA3,0xEF,0xF0,0x90,0x44,0xC0,0xE0,0xFE,
+
+	0xA3,0xE0,0xFF,0x90,0x43,0x70,0xE0,0x2F,
+
+	0xF0,0x90,0x43,0x6F,0xE0,0x3E,0xF0,0x90,
+
+	0x44,0xC1,0xE0,0x90,0xF4,0x66,0xF0,0x90,
+
+	0x44,0xC0,0xE0,0x90,0xF4,0x67,0xF0,0x90,
+
+	0x43,0x68,0xE0,0x90,0xF5,0xF4,0xF0,0x90,
+
+	0x43,0x67,0xE0,0x90,0xF5,0xF5,0xF0,0x90,
+
+	0x43,0x4D,0x74,0x08,0xF0,0x22,0xC2,0xAF,
+
+	0x90,0xF7,0x7D,0xE0,0x64,0x01,0x70,0x57,
+
+	0x90,0xF7,0x32,0xE0,0x60,0x03,0x12,0x96,
+
+	0xBA,0x90,0xF7,0x3C,0xE0,0x60,0x03,0x02,
+
+	0x85,0xBF,0x90,0xF5,0xA9,0xE0,0x60,0x03,
+
+	0x02,0x85,0xBF,0x90,0xF7,0x32,0xE0,0xB4,
+
+	0x01,0x10,0x90,0xF7,0x7B,0xE0,0xB4,0x01,
+
+	0x09,0x90,0x43,0xBA,0x74,0x02,0xF0,0x12,
+
+	0xA4,0x44,0x90,0xF7,0x31,0xE0,0x64,0x01,
+
+	0x60,0x03,0x02,0x85,0xBF,0x90,0xF7,0x7C,
+
+	0xE0,0x64,0x01,0x60,0x03,0x02,0x85,0xBF,
+
+	0x90,0x44,0x9A,0x04,0xF0,0x90,0xF7,0x49,
+
+	0xE0,0x90,0x44,0x9C,0xF0,0x80,0x6F,0x90,
+
+	0x44,0x9B,0xE0,0x64,0x01,0x70,0x67,0x90,
+
+	0xF5,0xB9,0xE0,0x64,0x01,0x70,0x29,0x90,
+
+	0xF5,0xB3,0x04,0xF0,0x90,0xF4,0x60,0xE0,
+
+	0x70,0x05,0x12,0xAE,0xA0,0x80,0x0F,0x90,
+
+	0xF4,0x60,0xE0,0xB4,0x01,0x05,0x12,0xAE,
+
+	0xB0,0x80,0x03,0x12,0xAE,0xC0,0x90,0xF5,
+
+	0xB3,0xE4,0xF0,0x90,0x42,0x58,0x04,0xF0,
+
+	0x90,0xF5,0xC0,0xE0,0x64,0x01,0x70,0x29,
+
+	0x90,0xF5,0xBD,0x04,0xF0,0x90,0xF4,0x60,
+
+	0xE0,0x70,0x05,0x12,0xAF,0x0C,0x80,0x0F,
+
+	0x90,0xF4,0x60,0xE0,0xB4,0x01,0x05,0x12,
+
+	0xAE,0x7E,0x80,0x03,0x12,0xAE,0xD0,0x90,
+
+	0xF5,0xBD,0xE4,0xF0,0x90,0x42,0x57,0x04,
+
+	0xF0,0xE4,0x90,0x44,0xCD,0xF0,0x12,0xAB,
+
+	0x75,0x53,0x91,0xBF,0xE4,0x90,0x44,0x9B,
+
+	0xF0,0xD2,0xEA,0xD2,0xE9,0xD2,0xAF,0x22,
+
+	0x12,0xAC,0x9F,0x12,0x8F,0xAB,0x12,0x7A,
+
+	0xB3,0x90,0x44,0x71,0x74,0x01,0xF0,0xFB,
+
+	0x7A,0x44,0x79,0x6A,0x12,0xA1,0x52,0xD2,
+
+	0xAF,0x90,0xF2,0x1B,0xE4,0xF0,0x90,0x44,
+
+	0x71,0xE0,0x70,0xFA,0x12,0xAD,0xCE,0xE5,
+
+	0x13,0xB4,0x0A,0x00,0x40,0x03,0x02,0x86,
+
+	0x9E,0x90,0x86,0x09,0xF8,0x28,0x28,0x73,
+
+	0x02,0x86,0x27,0x02,0x86,0x2C,0x02,0x86,
+
+	0x31,0x02,0x86,0x36,0x02,0x86,0x3B,0x02,
+
+	0x86,0x40,0x02,0x86,0x45,0x02,0x86,0x4A,
+
+	0x02,0x86,0x6A,0x02,0x86,0x99,0x12,0xAE,
+
+	0x6C,0x80,0x75,0x12,0x9B,0xB3,0x80,0x70,
+
+	0x12,0x8B,0xBB,0x80,0x6B,0x12,0xAA,0x6A,
+
+	0x80,0x66,0x12,0x9C,0x33,0x80,0x61,0x12,
+
+	0xA8,0xE4,0x80,0x5C,0x12,0xA4,0x8D,0x80,
+
+	0x57,0x90,0xF5,0x05,0x74,0x01,0xF0,0x90,
+
+	0x43,0x8E,0xF0,0x12,0xAF,0x7E,0x90,0x43,
+
+	0xBB,0xE0,0xB4,0x01,0x05,0x7F,0x01,0x12,
+
+	0xAD,0x78,0x7F,0x01,0x12,0xAE,0x43,0x80,
+
+	0x37,0x12,0xA0,0xEF,0x12,0x8D,0x56,0x90,
+
+	0xF5,0x05,0xE4,0xF0,0x90,0x43,0xBB,0xE0,
+
+	0xB4,0x01,0x06,0x12,0x73,0x31,0x12,0xA0,
+
+	0xEF,0x90,0x43,0xBB,0xE0,0xB4,0x01,0x06,
+
+	0xE5,0x13,0x64,0x08,0x60,0x12,0xE4,0x90,
+
+	0x42,0x42,0xF0,0x12,0xAD,0xCE,0x80,0x08,
+
+	0x12,0x70,0x4E,0x80,0x03,0x12,0xAF,0x87,
+
+	0x12,0x9F,0xC1,0x12,0x97,0xF3,0x12,0xAD,
+
+	0xCE,0x02,0x85,0xF8,0x22,0x90,0x41,0xB5,
+
+	0xE0,0xFE,0x90,0x41,0xB4,0xE0,0x7C,0x00,
+
+	0x24,0x00,0xFF,0xEC,0x3E,0x90,0x44,0xC2,
+
+	0xF0,0xA3,0xEF,0xF0,0xE4,0x7F,0x50,0x7E,
+
+	0x0D,0xFD,0x90,0x43,0xEA,0xE0,0xF8,0xA3,
+
+	0xE0,0xF9,0xA3,0xE0,0xFA,0xA3,0xE0,0xFB,
+
+	0xC3,0x12,0x4B,0x21,0x40,0x24,0x90,0x43,
+
+	0xEA,0xE0,0xFC,0xA3,0xE0,0xFD,0xA3,0xE0,
+
+	0xFE,0xA3,0xE0,0x24,0xB0,0xFF,0xEE,0x34,
+
+	0xF2,0xFE,0xED,0x34,0xFF,0xFD,0xEC,0x34,
+
+	0xFF,0xFC,0x90,0x43,0xE6,0x12,0x4B,0x6C,
+
+	0x80,0x23,0x90,0x43,0xEA,0xE0,0xF8,0xA3,
+
+	0xE0,0xF9,0xA3,0xE0,0xFA,0xA3,0xE0,0xFB,
+
+	0xC3,0x74,0x50,0x9B,0xFF,0x74,0x0D,0x9A,
+
+	0xFE,0xE4,0x99,0xFD,0xE4,0x98,0xFC,0x90,
+
+	0x43,0xE6,0x12,0x4B,0x6C,0x90,0x44,0xC2,
+
+	0xE0,0xFE,0xA3,0xE0,0xFF,0xE4,0xFC,0xFD,
+
+	0x90,0x43,0xE6,0xE0,0xF8,0xA3,0xE0,0xF9,
+
+	0xA3,0xE0,0xFA,0xA3,0xE0,0xFB,0x12,0x4A,
+
+	0xAE,0x78,0x09,0x12,0x4B,0x32,0x90,0x43,
+
+	0xE6,0x12,0x4B,0x6C,0xE4,0x7F,0x50,0x7E,
+
+	0x0D,0xFD,0xFC,0x90,0x43,0xEA,0xE0,0xF8,
+
+	0xA3,0xE0,0xF9,0xA3,0xE0,0xFA,0xA3,0xE0,
+
+	0xFB,0xC3,0x12,0x4B,0x21,0x50,0x22,0x90,
+
+	0x43,0xE6,0xE0,0xF8,0xA3,0xE0,0xF9,0xA3,
+
+	0xE0,0xFA,0xA3,0xE0,0xFB,0xC3,0xE4,0x9B,
+
+	0xFF,0x74,0x40,0x9A,0xFE,0xE4,0x99,0xFD,
+
+	0xE4,0x98,0xFC,0x90,0x43,0xE6,0x12,0x4B,
+
+	0x6C,0x22,0xE4,0xFF,0xFE,0x90,0x44,0xD3,
+
+	0xF0,0x90,0x41,0xD7,0xE0,0xFD,0xB4,0x22,
+
+	0x07,0x90,0x42,0x04,0xE0,0x70,0x01,0x0F,
+
+	0xED,0xB4,0x28,0x08,0x90,0xF0,0x61,0xE0,
+
+	0x70,0x02,0x7F,0x01,0x90,0x41,0xD7,0xE0,
+
+	0xB4,0x22,0x19,0x90,0x43,0xAE,0xE0,0x24,
+
+	0xAB,0xF5,0x82,0xE4,0x34,0x43,0xF5,0x83,
+
+	0xE0,0xFD,0x90,0x42,0x04,0xE0,0xC3,0x9D,
+
+	0x50,0x02,0x7E,0x01,0x90,0x41,0xD7,0xE0,
+
+	0xB4,0x28,0x0B,0x90,0xF0,0x61,0xE0,0xC3,
+
+	0x94,0x70,0x50,0x02,0x7E,0x01,0x90,0x43,
+
+	0x8E,0xE0,0x64,0x03,0x60,0x08,0x90,0x42,
+
+	0x52,0xE0,0x64,0x01,0x60,0xF0,0x90,0x41,
+
+	0xE8,0xE0,0x70,0x70,0x90,0x41,0xE3,0xE0,
+
+	0x70,0x2C,0xEF,0x70,0x09,0x90,0x41,0xD5,
+
+	0xE0,0x60,0x61,0xEE,0x60,0x5E,0x90,0x41,
+
+	0xD7,0xE0,0xB4,0x22,0x06,0x90,0x43,0x8F,
+
+	0x74,0x14,0xF0,0x12,0xAB,0x20,0x90,0x43,
+
+	0x8D,0x74,0x32,0xF0,0x90,0x41,0xD5,0xE0,
+
+	0x60,0x42,0x12,0xAF,0x6A,0x22,0x90,0x41,
+
+	0xD7,0xE0,0xFF,0xB4,0x22,0x14,0x90,0x42,
+
+	0x04,0xE0,0xD3,0x94,0x40,0x40,0x0B,0x90,
+
+	0x41,0xD5,0xE0,0x70,0x05,0x90,0x44,0xD3,
+
+	0x04,0xF0,0xEF,0xB4,0x28,0x0F,0x90,0xF0,
+
+	0x61,0xE0,0xD3,0x94,0x90,0x40,0x06,0x90,
+
+	0x44,0xD3,0x74,0x01,0xF0,0x90,0x44,0xD3,
+
+	0xE0,0x60,0x09,0x90,0x43,0x8F,0x74,0x14,
+
+	0xF0,0x12,0xAB,0x4B,0x22,0xE4,0xFF,0x90,
+
+	0x43,0xCA,0xF0,0xA3,0xF0,0xA3,0xF0,0x90,
+
+	0xF9,0x00,0xE0,0x70,0x08,0x90,0x43,0xCD,
+
+	0x74,0x2D,0xF0,0x80,0x15,0x90,0xF9,0x00,
+
+	0xE0,0xB4,0x02,0x08,0x90,0x43,0xCD,0x74,
+
+	0x59,0xF0,0x80,0x06,0x90,0x43,0xCD,0x74,
+
+	0xB1,0xF0,0x90,0xF5,0x56,0xE4,0xF0,0xFF,
+
+	0x90,0x43,0xCD,0xE0,0xFE,0xEF,0xC3,0x9E,
+
+	0x40,0x03,0x02,0x89,0x39,0x90,0xF6,0x56,
+
+	0xEF,0xF0,0x90,0xF6,0x5A,0x74,0x01,0xF0,
+
+	0x90,0xF6,0x5A,0xE0,0x70,0xFA,0x90,0xF6,
+
+	0x5E,0xE0,0x90,0x43,0xC9,0xF0,0x90,0x43,
+
+	0xC7,0xE0,0xC3,0x94,0xC8,0x50,0x25,0x90,
+
+	0x41,0xD5,0xE0,0xB4,0x01,0x1E,0xEF,0xC3,
+
+	0x94,0x0E,0x40,0x0C,0x90,0x43,0xCD,0xE0,
+
+	0x24,0xF2,0xFE,0xEF,0xD3,0x9E,0x40,0x06,
+
+	0x90,0x43,0xC9,0x74,0x01,0xF0,0x90,0x43,
+
+	0xC7,0xE0,0x04,0xF0,0x90,0x43,0xC9,0xE0,
+
+	0x60,0x17,0x90,0x43,0xCB,0xE0,0xFE,0x74,
+
+	0x01,0xA8,0x06,0x08,0x80,0x02,0xC3,0x33,
+
+	0xD8,0xFC,0xFE,0x90,0x43,0xCA,0xE0,0x2E,
+
+	0xF0,0x90,0x43,0xCB,0xE0,0x04,0xF0,0xE0,
+
+	0x64,0x08,0x60,0x05,0xA3,0xE0,0xB4,0x16,
+
+	0x1B,0x90,0x43,0xCC,0xE0,0x90,0xF5,0x57,
+
+	0xF0,0x90,0x43,0xCA,0xE0,0x90,0xF5,0x55,
+
+	0xF0,0xE4,0x90,0x43,0xCA,0xF0,0xA3,0xF0,
+
+	0xA3,0xE0,0x04,0xF0,0x0F,0x02,0x88,0x99,
+
+	0x90,0xF5,0x56,0x74,0x01,0xF0,0x22,0x90,
+
+	0x44,0x44,0xE0,0x54,0x01,0xF0,0xC2,0xAF,
+
+	0x70,0x27,0x90,0xF7,0x02,0xE0,0x90,0xFB,
+
+	0x97,0xF0,0x90,0xF7,0x03,0xE0,0x90,0xFB,
+
+	0x98,0xF0,0x90,0xF7,0x04,0xE0,0x90,0xFB,
+
+	0x99,0xF0,0x90,0xF9,0x99,0xE0,0x90,0xFB,
+
+	0x9A,0xF0,0x7F,0x04,0x12,0xAD,0x3C,0x80,
+
+	0x53,0x90,0x44,0x44,0xE0,0x64,0x01,0x70,
+
+	0x4B,0x90,0x41,0xD7,0xE0,0xB4,0x22,0x0F,
+
+	0x90,0x42,0x04,0xE0,0x90,0xFB,0x97,0xF0,
+
+	0x7F,0x07,0x12,0xAD,0x3C,0x80,0x35,0x90,
+
+	0x43,0x8C,0xE0,0x90,0xFB,0x97,0xF0,0x90,
+
+	0x43,0x8B,0xE0,0x90,0xFB,0x98,0xF0,0x90,
+
+	0x42,0x2E,0xE0,0x90,0xFB,0x99,0xF0,0x90,
+
+	0x42,0x2F,0xE0,0x90,0xFB,0x9A,0xF0,0x90,
+
+	0xF0,0x60,0xE0,0x90,0xFB,0x9B,0xF0,0x90,
+
+	0xF0,0x61,0xE0,0x90,0xFB,0x9C,0xF0,0x7F,
+
+	0x05,0x12,0xAD,0x3C,0xD2,0xAF,0x90,0x44,
+
+	0x44,0xE0,0x04,0xF0,0x90,0xFB,0xA3,0xE0,
+
+	0x90,0x41,0xDA,0xF0,0x90,0xFB,0xA4,0xE0,
+
+	0x25,0xE0,0x25,0xE0,0x24,0x82,0x90,0x41,
+
+	0xDB,0xF0,0xE0,0xFF,0xC3,0x94,0x54,0x40,
+
+	0x06,0xE4,0x90,0x41,0xD9,0xF0,0x22,0xEF,
+
+	0xC3,0x94,0x32,0x40,0x12,0xEF,0x94,0x54,
+
+	0x50,0x0D,0xC3,0x74,0x53,0x9F,0x75,0xF0,
+
+	0x03,0xA4,0x90,0x41,0xD9,0xF0,0x22,0x90,
+
+	0x41,0xDB,0xE0,0xC3,0x94,0x32,0x50,0x06,
+
+	0x90,0x41,0xD9,0x74,0x64,0xF0,0x22,0x90,
+
+	0xF9,0x03,0xE0,0x90,0x41,0xC1,0xF0,0x90,
+
+	0xF9,0x00,0xE0,0x90,0x41,0xC2,0xF0,0x90,
+
+	0x44,0x41,0xE0,0x04,0xF0,0xE0,0xC3,0x94,
+
+	0x32,0x40,0x05,0xE4,0xFF,0x12,0x80,0x20,
+
+	0x90,0x44,0x3F,0xE0,0x70,0x05,0x7F,0x02,
+
+	0x12,0x80,0x20,0x90,0x44,0x40,0xE0,0x04,
+
+	0xF0,0xE0,0xC3,0x94,0x32,0x40,0x0B,0x90,
+
+	0xF7,0x0D,0x74,0x01,0xF0,0xE4,0x90,0x44,
+
+	0x40,0xF0,0x90,0xF7,0x0D,0xE0,0x60,0x5A,
+
+	0x90,0xF7,0x05,0xE0,0x90,0x41,0xC3,0xF0,
+
+	0x90,0xF7,0x06,0xE0,0x90,0x41,0xC4,0xF0,
+
+	0x90,0xF7,0x02,0xE0,0x90,0x41,0xC5,0xF0,
+
+	0x90,0xF7,0x03,0xE0,0x90,0x41,0xC6,0xF0,
+
+	0x90,0xF7,0x04,0xE0,0x90,0x41,0xC7,0xF0,
+
+	0x90,0xF7,0x00,0xE0,0x90,0x41,0xC8,0xF0,
+
+	0x90,0xF7,0x01,0xE0,0x90,0x41,0xC9,0xF0,
+
+	0x90,0xF7,0x0D,0x74,0x01,0xF0,0xE4,0x90,
+
+	0x44,0x40,0xF0,0x90,0x41,0xCF,0xE0,0x04,
+
+	0xF0,0xE0,0xFF,0x90,0x41,0xF6,0xE0,0xFE,
+
+	0xEF,0x8E,0xF0,0x84,0x90,0x41,0xCF,0xE5,
+
+	0xF0,0xF0,0x90,0xF7,0x00,0xE0,0xFF,0x90,
+
+	0x41,0xCB,0xE0,0xFE,0xB5,0x07,0x0C,0x90,
+
+	0xF7,0x01,0xE0,0xFF,0x90,0x41,0xCC,0xE0,
+
+	0x6F,0x60,0x18,0x90,0xF7,0x00,0xEE,0xF0,
+
+	0x90,0x41,0xCC,0xE0,0x90,0xF7,0x01,0xF0,
+
+	0x90,0xF7,0x0C,0x74,0x01,0xF0,0xE4,0xF0,
+
+	0xA3,0x04,0xF0,0x22,0x90,0xF5,0xEB,0xE0,
+
+	0x90,0x44,0xAC,0xF0,0x90,0xF5,0xEC,0xE0,
+
+	0x90,0x44,0xAB,0xF0,0x90,0xF5,0xED,0xE0,
+
+	0x90,0x44,0xAE,0xF0,0x90,0xF5,0xEE,0xE0,
+
+	0x90,0x44,0xAD,0xF0,0x90,0x43,0x6E,0xE0,
+
+	0xFF,0xB4,0x01,0x0A,0x74,0x02,0xF0,0x90,
+
+	0x43,0x4D,0x74,0x07,0xF0,0x22,0xEF,0x64,
+
+	0x02,0x60,0x08,0xEF,0x64,0x03,0x60,0x03,
+
+	0x02,0x8B,0xBA,0x90,0x43,0x64,0xE0,0xFF,
+
+	0x90,0x43,0x63,0xE0,0xFE,0x6F,0x70,0x2C,
+
+	0x90,0xF5,0xE9,0xE0,0x70,0x07,0x90,0x43,
+
+	0x65,0xEE,0xF0,0x80,0x18,0x90,0x41,0xEF,
+
+	0xE0,0x14,0xB5,0x06,0x07,0xE4,0x90,0x43,
+
+	0x65,0xF0,0x80,0x09,0x90,0x43,0x63,0xE0,
+
+	0x04,0x90,0x43,0x65,0xF0,0x90,0x43,0x4D,
+
+	0x74,0x0C,0xF0,0x22,0x90,0xF5,0xE9,0xE0,
+
+	0x70,0x18,0x90,0x43,0x63,0xE0,0xFF,0x90,
+
+	0x43,0x66,0xE0,0xB5,0x07,0x0C,0x90,0x43,
+
+	0x65,0xEF,0xF0,0x90,0x43,0x4D,0x74,0x0C,
+
+	0xF0,0x22,0x90,0xF5,0xE9,0xE0,0x70,0x0B,
+
+	0x90,0x43,0x66,0xE0,0x14,0x90,0x43,0x64,
+
+	0xF0,0x80,0x09,0x90,0x43,0x66,0xE0,0x04,
+
+	0x90,0x43,0x63,0xF0,0x90,0x43,0x64,0xE0,
+
+	0xFF,0x90,0x43,0x63,0xE0,0x2F,0xFF,0xC3,
+
+	0x13,0x90,0x43,0x66,0xF0,0x90,0x43,0x6E,
+
+	0x74,0x03,0xF0,0x90,0x43,0x4D,0x74,0x06,
+
+	0xF0,0x22,0x90,0xF0,0x2B,0xE4,0xF0,0x90,
+
+	0x42,0x44,0xE0,0x70,0x17,0x90,0xF1,0xE5,
+
+	0x04,0xF0,0x12,0xAE,0x59,0x12,0xAB,0x4B,
+
+	0x12,0x96,0x16,0x90,0x43,0xBB,0x74,0x01,
+
+	0xF0,0x02,0x8C,0x5E,0x90,0x44,0x47,0x74,
+
+	0x82,0xF0,0x90,0xFB,0x28,0xF0,0x12,0xAF,
+
+	0xA6,0x90,0x42,0x05,0xE0,0x90,0xF0,0x41,
+
+	0xF0,0x90,0xF0,0x2C,0x74,0x01,0xF0,0x90,
+
+	0xF1,0xE5,0xF0,0x75,0xF0,0x02,0xE5,0x13,
+
+	0xA4,0x24,0xC5,0xF5,0x82,0xE5,0xF0,0x34,
+
+	0xAF,0xF5,0x83,0xE4,0x93,0xFC,0x74,0x01,
+
+	0x93,0xFD,0xE4,0xFF,0x12,0xAB,0xED,0x90,
+
+	0x44,0xAA,0xE0,0xB4,0x01,0x04,0x7F,0x01,
+
+	0x80,0x02,0x7F,0x00,0x90,0xF1,0xE7,0xE0,
+
+	0x64,0x01,0x60,0x04,0x7E,0x01,0x80,0x02,
+
+	0x7E,0x00,0xEE,0x5F,0x70,0xE1,0x90,0xF1,
+
+	0xE7,0xE0,0xB4,0x01,0x04,0x7F,0x01,0x80,
+
+	0x02,0x7F,0x00,0x90,0x43,0xBB,0xEF,0xF0,
+
+	0xE0,0xB4,0x01,0x11,0x7D,0xFE,0x7C,0x27,
+
+	0xE4,0xFF,0x12,0xAB,0xED,0x90,0x44,0xAA,
+
+	0xE0,0x64,0x01,0x60,0xF8,0x90,0xF1,0x75,
+
+	0x74,0x01,0xF0,0x90,0x41,0xD7,0xE0,0xB4,
+
+	0x23,0x08,0x90,0x42,0x54,0xE0,0x90,0x44,
+
+	0x45,0xF0,0x12,0xAC,0x37,0x90,0xF0,0xD5,
+
+	0x74,0x01,0xF0,0x90,0xF0,0xE3,0xF0,0x90,
+
+	0xF0,0xE2,0xF0,0x90,0x43,0xBE,0xF0,0x22,
+
+	0x90,0x43,0xBD,0xE0,0x70,0x03,0x02,0x8D,
+
+	0x4F,0xC2,0xE9,0xE4,0x90,0x44,0x9B,0xF0,
+
+	0x90,0xF7,0x3C,0xE0,0xB4,0x01,0x04,0xC2,
+
+	0xEA,0x80,0x02,0xD2,0xEA,0x90,0xF7,0x0E,
+
+	0xE0,0xB4,0x01,0x20,0x90,0x43,0xB9,0xE0,
+
+	0xC3,0x94,0x02,0x50,0x11,0xE5,0x13,0xB4,
+
+	0x09,0x0C,0x12,0xAD,0xB2,0x90,0x43,0xB9,
+
+	0xE0,0x04,0xF0,0x02,0x8D,0x4F,0x12,0xA6,
+
+	0xD7,0x02,0x8D,0x4F,0x90,0xF5,0x54,0xE0,
+
+	0x64,0x01,0x70,0x7A,0x90,0xF0,0x2B,0xE0,
+
+	0x70,0x12,0x90,0x42,0x34,0xE0,0xB4,0x01,
+
+	0x0B,0x90,0xF2,0x17,0x74,0xFE,0xF0,0x90,
+
+	0x42,0x33,0x04,0xF0,0x90,0x44,0x9E,0xE0,
+
+	0xC3,0x94,0x02,0x50,0x18,0xE5,0x13,0xB4,
+
+	0x09,0x13,0x12,0xAD,0xB2,0x90,0x44,0x9D,
+
+	0xE0,0x90,0xF5,0x52,0xF0,0x90,0x44,0x9E,
+
+	0xE0,0x04,0xF0,0x80,0x41,0x90,0x43,0xBA,
+
+	0x74,0x02,0xF0,0x90,0xF7,0x0E,0xE0,0x64,
+
+	0x01,0x60,0x07,0x90,0xF7,0x40,0xE0,0xB4,
+
+	0x01,0x05,0x12,0xA6,0xD7,0x80,0x27,0x90,
+
+	0xF7,0x31,0xE0,0x60,0x0A,0xE4,0xFF,0x12,
+
+	0xA3,0xFB,0x12,0xAB,0xC7,0x80,0x11,0x90,
+
+	0xF7,0x3C,0xE0,0x70,0x03,0x12,0xAE,0x16,
+
+	0xE4,0x90,0x42,0x42,0xF0,0x12,0xAE,0xDF,
+
+	0x12,0xAE,0x8F,0x12,0xAD,0x95,0x12,0xAE,
+
+	0x8F,0x53,0x91,0x7F,0x22,0x90,0xF5,0xA8,
+
+	0xE4,0xF0,0x04,0xF0,0x75,0xF0,0x02,0xE5,
+
+	0x13,0xA4,0x24,0xC5,0xF5,0x82,0xE5,0xF0,
+
+	0x34,0xAF,0xF5,0x83,0xE4,0x93,0xFC,0x74,
+
+	0x01,0x93,0xFD,0xE4,0xFF,0x12,0xAB,0xED,
+
+	0x90,0x44,0xAA,0xE0,0xB4,0x01,0x04,0x7F,
+
+	0x01,0x80,0x02,0x7F,0x00,0x90,0xF5,0xA9,
+
+	0xE0,0x64,0x01,0x60,0x04,0x7E,0x01,0x80,
+
+	0x02,0x7E,0x00,0xEE,0x5F,0x70,0xE1,0x90,
+
+	0xF5,0xA9,0xE0,0xB4,0x01,0x04,0x7F,0x01,
+
+	0x80,0x02,0x7F,0x00,0x90,0x43,0xBB,0xEF,
+
+	0xF0,0xE0,0x64,0x01,0x70,0x40,0x90,0xF4,
+
+	0xCC,0xE0,0xFF,0x90,0xF9,0x08,0xF0,0x90,
+
+	0xF4,0xC1,0xE0,0xFF,0x90,0xF9,0x03,0xF0,
+
+	0x90,0xF4,0xC4,0xE0,0xFF,0x90,0xF9,0x06,
+
+	0xF0,0x90,0xF4,0xC5,0xE0,0xFF,0x90,0xF9,
+
+	0x07,0xF0,0x90,0xF4,0xC6,0xE0,0x54,0x03,
+
+	0xFF,0x90,0xF9,0x02,0xF0,0x70,0x05,0x90,
+
+	0xF9,0x05,0x04,0xF0,0x90,0x41,0xD1,0x74,
+
+	0x01,0xF0,0x90,0xF7,0x2F,0xF0,0x90,0xF1,
+
+	0x0F,0xE0,0xFE,0x90,0xF1,0x0E,0xE0,0x7C,
+
+	0x00,0x24,0x00,0xFF,0xEC,0x3E,0x90,0x43,
+
+	0xD1,0xF0,0xA3,0xEF,0xF0,0x90,0xF1,0x13,
+
+	0xE0,0xFE,0x90,0xF1,0x12,0xE0,0x24,0x00,
+
+	0xFF,0xEC,0x3E,0x90,0x43,0xD3,0xF0,0xA3,
+
+	0xEF,0xF0,0x12,0x95,0x68,0x22,0x90,0xF9,
+
+	0x00,0xE0,0xB4,0x01,0x10,0x90,0x43,0x20,
+
+	0x74,0x0C,0xF0,0xA3,0x74,0x1A,0xF0,0xA3,
+
+	0x74,0xA1,0xF0,0x80,0x24,0x90,0xF9,0x00,
+
+	0xE0,0x70,0x10,0x90,0x43,0x20,0x74,0x0A,
+
+	0xF0,0xA3,0x74,0x06,0xF0,0xA3,0x74,0xA9,
+
+	0xF0,0x80,0x0E,0x90,0x43,0x20,0x74,0x0B,
+
+	0xF0,0xA3,0x74,0x0D,0xF0,0xA3,0x74,0x51,
+
+	0xF0,0xE4,0xFF,0x7F,0x08,0x90,0x43,0x28,
+
+	0xE4,0xF0,0xA3,0xDF,0xFC,0x7F,0x08,0x90,
+
+	0xF4,0xC1,0xE0,0x14,0x60,0x12,0x14,0x60,
+
+	0x41,0x24,0x02,0x70,0x6E,0x90,0x43,0x1E,
+
+	0x74,0xB5,0xF0,0xA3,0x74,0x08,0xF0,0x22,
+
+	0x90,0xF4,0xC6,0xE0,0x14,0x60,0x0A,0x14,
+
+	0x60,0x12,0x14,0x60,0x1A,0x24,0x03,0x70,
+
+	0x52,0x90,0x43,0x1E,0x74,0xA2,0xF0,0xA3,
+
+	0x74,0x09,0xF0,0x22,0x90,0x43,0x1E,0x74,
+
+	0xE5,0xF0,0xA3,0x74,0x0A,0xF0,0x22,0x90,
+
+	0x43,0x1E,0x74,0x8E,0xF0,0xA3,0x74,0x0A,
+
+	0xF0,0x22,0x90,0xF4,0xC6,0xE0,0x14,0x60,
+
+	0x0A,0x14,0x60,0x12,0x14,0x60,0x1A,0x24,
+
+	0x03,0x70,0x20,0x90,0x43,0x1E,0x74,0x9E,
+
+	0xF0,0xA3,0x74,0x0A,0xF0,0x22,0x90,0x43,
+
+	0x1E,0x74,0x84,0xF0,0xA3,0x74,0x0A,0xF0,
+
+	0x22,0x90,0x43,0x1E,0x74,0xC5,0xF0,0xA3,
+
+	0x74,0x0B,0xF0,0x22,0x90,0xF5,0xCB,0xE0,
+
+	0xB4,0x01,0xF9,0x90,0xF5,0xD0,0xE0,0x90,
+
+	0x42,0xFF,0xF0,0x90,0xF5,0xCF,0xE0,0x90,
+
+	0x43,0x00,0xF0,0x90,0xF5,0xCE,0xE0,0x90,
+
+	0x43,0x01,0xF0,0x90,0x42,0xFE,0xE0,0xFC,
+
+	0xA3,0xE0,0xFD,0xA3,0xE0,0xFE,0xA3,0xE0,
+
+	0xFF,0x78,0x0A,0x12,0x4B,0x59,0x78,0x0A,
+
+	0x12,0x4B,0x45,0x90,0x42,0xFE,0x12,0x4B,
+
+	0x6C,0x90,0x43,0x1E,0xE0,0xFF,0xE4,0xFC,
+
+	0xFD,0xFE,0x90,0x42,0xFE,0xE0,0xF8,0xA3,
+
+	0xE0,0xF9,0xA3,0xE0,0xFA,0xA3,0xE0,0xFB,
+
+	0x12,0x4A,0xAE,0x90,0x43,0x1F,0xE0,0xF9,
+
+	0xF8,0x12,0x4B,0x45,0x90,0x42,0xFE,0x12,
+
+	0x4B,0x6C,0x90,0xF5,0xD3,0xE0,0x90,0x43,
+
+	0x03,0xF0,0x90,0xF5,0xD2,0xE0,0x90,0x43,
+
+	0x04,0xF0,0x90,0xF5,0xD1,0xE0,0x90,0x43,
+
+	0x05,0xF0,0x90,0x43,0x02,0xE0,0xFC,0xA3,
+
+	0xE0,0xFD,0xA3,0xE0,0xFE,0xA3,0xE0,0xFF,
+
+	0x78,0x0A,0x12,0x4B,0x59,0x78,0x0A,0x12,
+
+	0x4B,0x45,0x90,0x43,0x02,0x12,0x4B,0x6C,
+
+	0x90,0x43,0x1E,0xE0,0xFF,0xE4,0xFC,0xFD,
+
+	0xFE,0x90,0x43,0x02,0xE0,0xF8,0xA3,0xE0,
+
+	0xF9,0xA3,0xE0,0xFA,0xA3,0xE0,0xFB,0x12,
+
+	0x4A,0xAE,0x90,0x43,0x1F,0xE0,0xF9,0xF8,
+
+	0x12,0x4B,0x45,0x90,0x43,0x02,0x12,0x4B,
+
+	0x6C,0x22,0xC2,0xAF,0x90,0x41,0x03,0x74,
+
+	0x02,0xF0,0xA3,0x74,0x91,0xF0,0xA3,0x74,
+
+	0x2C,0xF0,0x90,0x41,0x0B,0x74,0x02,0xF0,
+
+	0xA3,0x74,0x91,0xF0,0xA3,0x74,0x34,0xF0,
+
+	0x90,0x41,0x13,0x74,0x02,0xF0,0xA3,0x74,
+
+	0x91,0xF0,0xA3,0x74,0x3C,0xF0,0x90,0x41,
+
+	0x1B,0x74,0x02,0xF0,0xA3,0x74,0x91,0xF0,
+
+	0xA3,0x74,0x44,0xF0,0x90,0x41,0x23,0x74,
+
+	0x02,0xF0,0xA3,0x74,0x91,0xF0,0xA3,0x74,
+
+	0x4C,0xF0,0x90,0x41,0x2B,0x74,0x02,0xF0,
+
+	0xA3,0x74,0x91,0xF0,0xA3,0x74,0x54,0xF0,
+
+	0x90,0x41,0x33,0x74,0x02,0xF0,0xA3,0x74,
+
+	0x91,0xF0,0xA3,0x74,0x5C,0xF0,0x90,0x41,
+
+	0x3B,0x74,0x02,0xF0,0xA3,0x74,0x91,0xF0,
+
+	0xA3,0x74,0x64,0xF0,0x90,0x41,0x43,0x74,
+
+	0x02,0xF0,0xA3,0x74,0x91,0xF0,0xA3,0x74,
+
+	0x6C,0xF0,0x90,0x41,0x4B,0x74,0x02,0xF0,
+
+	0xA3,0x74,0x91,0xF0,0xA3,0x74,0x74,0xF0,
+
+	0x90,0x41,0x53,0x74,0x02,0xF0,0xA3,0x74,
+
+	0x91,0xF0,0xA3,0x74,0x7C,0xF0,0x90,0x41,
+
+	0x5B,0x74,0x02,0xF0,0xA3,0x74,0x91,0xF0,
+
+	0xA3,0x74,0x84,0xF0,0x90,0x41,0x63,0x74,
+
+	0x02,0xF0,0xA3,0x74,0x91,0xF0,0xA3,0x74,
+
+	0x8C,0xF0,0x90,0xAF,0xA0,0x74,0x32,0xF0,
+
+	0xD2,0xAF,0x22,0x90,0xF5,0x76,0x74,0xFF,
+
+	0xF0,0xA3,0x74,0x01,0xF0,0xA3,0x74,0x9E,
+
+	0xF0,0xA3,0x74,0x03,0xF0,0xA3,0x74,0x31,
+
+	0xF0,0xA3,0x74,0x02,0xF0,0xA3,0x74,0xB0,
+
+	0xF0,0xA3,0xE4,0xF0,0xA3,0x74,0x7B,0xF0,
+
+	0xA3,0x74,0x01,0xF0,0xA3,0x74,0x25,0xF0,
+
+	0xA3,0x74,0x03,0xF0,0xA3,0x74,0xEC,0xF0,
+
+	0xA3,0x74,0x02,0xF0,0xA3,0x74,0xE1,0xF0,
+
+	0xA3,0xE4,0xF0,0xA3,0x74,0xB0,0xF0,0xA3,
+
+	0xE4,0xF0,0xA3,0x74,0x3A,0xF0,0xA3,0x74,
+
+	0x03,0xF0,0xA3,0x74,0xA2,0xF0,0xA3,0x74,
+
+	0x03,0xF0,0xA3,0x74,0x97,0xF0,0xA3,0xE4,
+
+	0xF0,0xA3,0x74,0x26,0xF0,0xA3,0xE4,0xF0,
+
+	0xA3,0x74,0x9C,0xF0,0xA3,0x74,0x03,0xF0,
+
+	0xA3,0x74,0xF9,0xF0,0xA3,0x74,0x03,0xF0,
+
+	0xA3,0x74,0x37,0xF0,0xA3,0xE4,0xF0,0xA3,
+
+	0x74,0xFC,0xF0,0xA3,0x74,0x03,0xF0,0xA3,
+
+	0x74,0xE8,0xF0,0xA3,0x74,0x03,0xF0,0x90,
+
+	0xF5,0x6C,0xE4,0xF0,0xA3,0x74,0x05,0xF0,
+
+	0x90,0xF9,0x00,0xE0,0x70,0x0A,0x90,0xF5,
+
+	0x9E,0x74,0x19,0xF0,0xA3,0xE4,0xF0,0x22,
+
+	0x90,0xF9,0x00,0xE0,0xB4,0x01,0x0A,0x90,
+
+	0xF5,0x9E,0x74,0x65,0xF0,0xA3,0xE4,0xF0,
+
+	0x22,0x90,0xF5,0x9E,0x74,0x65,0xF0,0xA3,
+
+	0xE4,0xF0,0x22,0xC0,0xE0,0x75,0xE0,0x00,
+
+	0x02,0x91,0x94,0xC0,0xE0,0x75,0xE0,0x02,
+
+	0x02,0x91,0x94,0xC0,0xE0,0x75,0xE0,0x04,
+
+	0x02,0x91,0x94,0xC0,0xE0,0x75,0xE0,0x06,
+
+	0x02,0x91,0x94,0xC0,0xE0,0x75,0xE0,0x08,
+
+	0x02,0x91,0x94,0xC0,0xE0,0x75,0xE0,0x0A,
+
+	0x02,0x91,0x94,0xC0,0xE0,0x75,0xE0,0x0C,
+
+	0x02,0x91,0x94,0xC0,0xE0,0x75,0xE0,0x0E,
+
+	0x02,0x91,0x94,0xC0,0xE0,0x75,0xE0,0x10,
+
+	0x02,0x91,0x94,0xC0,0xE0,0x75,0xE0,0x12,
+
+	0x02,0x91,0x94,0xC0,0xE0,0x75,0xE0,0x14,
+
+	0x02,0x91,0x94,0xC0,0xE0,0x75,0xE0,0x16,
+
+	0x02,0x91,0x94,0xC0,0xE0,0x75,0xE0,0x18,
+
+	0x02,0x91,0x94,0xC0,0xD0,0x75,0xD0,0x00,
+
+	0xC0,0x86,0x75,0x86,0x00,0xC0,0x83,0xC0,
+
+	0x82,0xC0,0x85,0xC0,0x84,0xC0,0xF0,0xC0,
+
+	0x00,0xC0,0x01,0xC0,0x02,0xC0,0x03,0xC0,
+
+	0x04,0xC0,0x05,0xC0,0x06,0xC0,0x07,0x90,
+
+	0xAF,0xE3,0xF9,0x93,0xFA,0xE9,0x04,0x93,
+
+	0xF9,0x12,0x4B,0xA9,0xD0,0x07,0xD0,0x06,
+
+	0xD0,0x05,0xD0,0x04,0xD0,0x03,0xD0,0x02,
+
+	0xD0,0x01,0xD0,0x00,0xD0,0xF0,0xD0,0x84,
+
+	0xD0,0x85,0xD0,0x82,0xD0,0x83,0xD0,0x86,
+
+	0xD0,0xD0,0xD0,0xE0,0x32,0x4E,0x42,0x79,
+
+	0x99,0x46,0x01,0xE9,0x50,0x06,0xC6,0xB3,
+
+	0xB0,0xB0,0xAE,0xA8,0x9E,0x74,0x4E,0x42,
+
+	0x87,0x02,0x02,0x02,0x01,0x01,0x01,0x00,
+
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x4E,
+
+	0x42,0x95,0x00,0x00,0x00,0x03,0x05,0x08,
+
+	0x0C,0x0F,0x10,0x10,0x10,0x0D,0x0B,0x05,
+
+	0x5C,0x42,0xA3,0x00,0x00,0x00,0x99,0x00,
+
+	0x00,0x00,0xE8,0x00,0x4B,0x00,0xFC,0x00,
+
+	0xAE,0x00,0x8B,0x00,0x79,0x00,0x70,0x00,
+
+	0x6C,0x00,0x6B,0x00,0x6B,0x00,0x14,0x5C,
+
+	0x42,0xBF,0x00,0x03,0x00,0x02,0x00,0x02,
+
+	0x00,0x01,0x00,0x01,0x00,0x00,0x00,0x00,
+
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+
+	0x00,0x00,0x00,0x00,0x00,0x00,0x5C,0x42,
+
+	0xDB,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+
+	0x01,0x00,0x01,0x00,0x02,0x00,0x03,0x00,
+
+	0x03,0x00,0x04,0x00,0x05,0x00,0x05,0x00,
+
+	0x06,0x00,0x06,0x00,0x03,0x43,0x43,0xAB,
+
+	0x3A,0x44,0x40,0x48,0x43,0x28,0x00,0x00,
+
+	0x00,0x00,0x00,0x00,0x00,0x00,0x50,0x43,
+
+	0x36,0x02,0x39,0x04,0xEE,0x08,0xFB,0x0E,
+
+	0xAA,0x10,0xD5,0x13,0x0D,0x14,0xC9,0x18,
+
+	0xFE,0x00,0x90,0xF5,0x76,0x74,0x20,0xF0,
+
+	0xA3,0x74,0x01,0xF0,0xA3,0x74,0x22,0xF0,
+
+	0xA3,0x74,0x02,0xF0,0xA3,0x74,0xFF,0xF0,
+
+	0xA3,0x74,0x01,0xF0,0xA3,0x74,0x7E,0xF0,
+
+	0xA3,0x74,0x02,0xF0,0xA3,0x74,0xA0,0xF0,
+
+	0xA3,0xE4,0xF0,0xA3,0x74,0x51,0xF0,0xA3,
+
+	0xE4,0xF0,0xA3,0xF0,0xA3,0x74,0x03,0xF0,
+
+	0xA3,0x74,0x40,0xF0,0xA3,0x74,0x01,0xF0,
+
+	0xA3,0x74,0xED,0xF0,0xA3,0x74,0x02,0xF0,
+
+	0xA3,0x74,0xA1,0xF0,0xA3,0xE4,0xF0,0xA3,
+
+	0x74,0xDF,0xF0,0xA3,0x74,0x03,0xF0,0xA3,
+
+	0x74,0xC1,0xF0,0xA3,0x74,0x03,0xF0,0xA3,
+
+	0x74,0x68,0xF0,0xA3,0xE4,0xF0,0xA3,0x74,
+
+	0x9F,0xF0,0xA3,0x74,0x03,0xF0,0xA3,0x74,
+
+	0x3E,0xF0,0xA3,0xE4,0xF0,0xA3,0x74,0xE8,
+
+	0xF0,0xA3,0x74,0x03,0xF0,0xA3,0x74,0xFF,
+
+	0xF0,0xA3,0x74,0x03,0xF0,0xA3,0x74,0x0A,
+
+	0xF0,0xA3,0xE4,0xF0,0x90,0xF9,0x00,0xE0,
+
+	0x70,0x0A,0x90,0xF5,0x9E,0x74,0x3F,0xF0,
+
+	0xA3,0xE4,0xF0,0x22,0x90,0xF9,0x00,0xE0,
+
+	0xB4,0x01,0x0A,0x90,0xF5,0x9E,0x74,0xFB,
+
+	0xF0,0xA3,0xE4,0xF0,0x22,0x90,0xF5,0x9E,
+
+	0x74,0x7D,0xF0,0xA3,0xE4,0xF0,0x22,0x90,
+
+	0x41,0xD7,0xE0,0x64,0x22,0x70,0x34,0x90,
+
+	0x41,0xD4,0xE0,0x70,0x06,0x90,0x41,0xD5,
+
+	0xE0,0x60,0x28,0x90,0x43,0x9C,0xE0,0x60,
+
+	0x22,0x90,0x42,0x0B,0xE0,0xFF,0x90,0x42,
+
+	0x04,0xE0,0xB5,0x07,0x16,0x7F,0x12,0x12,
+
+	0xAD,0x3C,0x90,0xFB,0xA2,0xE0,0x90,0x42,
+
+	0x04,0xF0,0x90,0x43,0x8F,0x74,0x14,0xF0,
+
+	0x12,0xA8,0x1A,0x90,0x42,0x04,0xE0,0x90,
+
+	0x43,0xA6,0xF0,0x90,0x43,0x9C,0xE0,0xFF,
+
+	0x60,0x42,0x90,0x43,0xA9,0xE0,0x60,0x02,
+
+	0x14,0xF0,0xEF,0x30,0xE7,0x0B,0x12,0xAD,
+
+	0xE8,0x90,0x43,0x9C,0xE0,0x04,0xF0,0x80,
+
+	0x09,0x12,0xAC,0xFE,0x90,0x43,0x9C,0xE0,
+
+	0x14,0xF0,0x90,0x41,0xD5,0xE0,0x60,0x17,
+
+	0x90,0x43,0xA7,0xE0,0xB4,0x03,0x15,0x12,
+
+	0xA8,0x1A,0xE4,0x90,0x43,0xA7,0xF0,0x90,
+
+	0x43,0xA9,0x74,0x20,0xF0,0x80,0x05,0x12,
+
+	0xAF,0x28,0x80,0xB7,0x90,0x42,0x04,0xE0,
+
+	0xFF,0x90,0x42,0x3D,0xF0,0x90,0x42,0x53,
+
+	0xE0,0x60,0x18,0x90,0x42,0x0B,0xE0,0xFE,
+
+	0xEF,0xB5,0x06,0x0F,0x90,0x43,0x9D,0xE0,
+
+	0xD3,0x94,0x40,0x50,0x06,0x90,0x43,0x90,
+
+	0x74,0x01,0xF0,0x22,0x90,0xF5,0x76,0x74,
+
+	0x06,0xF0,0xA3,0x74,0x01,0xF0,0xA3,0x74,
+
+	0xC1,0xF0,0xA3,0x74,0x01,0xF0,0xA3,0x74,
+
+	0xFF,0xF0,0xA3,0x74,0x01,0xF0,0xA3,0x74,
+
+	0xB8,0xF0,0xA3,0x74,0x01,0xF0,0xA3,0x74,
+
+	0x0C,0xF0,0xA3,0x74,0x01,0xF0,0xA3,0x74,
+
+	0x36,0xF0,0xA3,0xE4,0xF0,0xA3,0x74,0x79,
+
+	0xF0,0xA3,0x74,0x03,0xF0,0xA3,0xF0,0xA3,
+
+	0xF0,0xA3,0x74,0xE7,0xF0,0xA3,0x74,0x02,
+
+	0xF0,0xA3,0x74,0x18,0xF0,0xA3,0x74,0x03,
+
+	0xF0,0xA3,0x74,0x74,0xF0,0xA3,0x74,0x03,
+
+	0xF0,0xA3,0x74,0xD6,0xF0,0xA3,0x74,0x03,
+
+	0xF0,0xA3,0x74,0x1E,0xF0,0xA3,0xE4,0xF0,
+
+	0xA3,0x74,0x41,0xF0,0xA3,0xE4,0xF0,0xA3,
+
+	0x74,0x43,0xF0,0xA3,0xE4,0xF0,0xA3,0x74,
+
+	0x30,0xF0,0xA3,0xE4,0xF0,0xA3,0x74,0x18,
+
+	0xF0,0xA3,0xE4,0xF0,0xA3,0x74,0x07,0xF0,
+
+	0xA3,0xE4,0xF0,0x90,0xF9,0x00,0xE0,0x70,
+
+	0x0A,0x90,0xF5,0x9E,0x74,0x19,0xF0,0xA3,
+
+	0xE4,0xF0,0x22,0x90,0xF9,0x00,0xE0,0xB4,
+
+	0x01,0x0A,0x90,0xF5,0x9E,0x74,0x65,0xF0,
+
+	0xA3,0xE4,0xF0,0x22,0x90,0xF5,0x9E,0x74,
+
+	0x32,0xF0,0xA3,0xE4,0xF0,0x22,0x90,0xF5,
+
+	0x76,0x74,0x72,0xF0,0xA3,0x74,0x01,0xF0,
+
+	0xA3,0xF0,0xA3,0x04,0xF0,0xA3,0x74,0x5C,
+
+	0xF0,0xA3,0x74,0x01,0xF0,0xA3,0xE4,0xF0,
+
+	0xA3,0xF0,0xA3,0x74,0xCD,0xF0,0xA3,0x74,
+
+	0x02,0xF0,0xA3,0x74,0x8E,0xF0,0xA3,0x74,
+
+	0x01,0xF0,0xA3,0x04,0xF0,0xA3,0x04,0xF0,
+
+	0xA3,0xE4,0xF0,0xA3,0xF0,0xA3,0x74,0xC3,
+
+	0xF0,0xA3,0xE4,0xF0,0xA3,0x74,0x16,0xF0,
+
+	0xA3,0x74,0x03,0xF0,0xA3,0x74,0x89,0xF0,
+
+	0xA3,0xE4,0xF0,0xA3,0xF0,0xA3,0xF0,0xA3,
+
+	0x74,0xA9,0xF0,0xA3,0x74,0x03,0xF0,0xA3,
+
+	0x74,0x5D,0xF0,0xA3,0xE4,0xF0,0xA3,0x74,
+
+	0xD0,0xF0,0xA3,0x74,0x03,0xF0,0xA3,0xE4,
+
+	0xF0,0xA3,0xF0,0xA3,0x74,0x15,0xF0,0xA3,
+
+	0xE4,0xF0,0xA3,0x74,0xEF,0xF0,0xA3,0x74,
+
+	0x03,0xF0,0x90,0xF5,0x6C,0x74,0x80,0xF0,
+
+	0xA3,0x74,0x06,0xF0,0x90,0xF9,0x00,0xE0,
+
+	0x70,0x0A,0x90,0xF5,0x9E,0x74,0x3F,0xF0,
+
+	0xA3,0xE4,0xF0,0x22,0x90,0xF9,0x00,0xE0,
+
+	0xB4,0x01,0x0A,0x90,0xF5,0x9E,0x74,0xFB,
+
+	0xF0,0xA3,0xE4,0xF0,0x22,0x90,0xF5,0x9E,
+
+	0x74,0x7D,0xF0,0xA3,0xE4,0xF0,0x22,0x90,
+
+	0xF1,0x10,0xE0,0x64,0x01,0x60,0x03,0x02,
+
+	0x96,0x09,0x90,0xF1,0x14,0xE0,0x64,0x01,
+
+	0x60,0x03,0x02,0x96,0x09,0xD3,0x90,0x43,
+
+	0xD2,0xE0,0x94,0x10,0x90,0x43,0xD1,0xE0,
+
+	0x94,0x35,0x40,0x0C,0xA3,0xE0,0x94,0x30,
+
+	0x90,0x43,0xD1,0xE0,0x94,0x38,0x40,0x1B,
+
+	0xD3,0x90,0x43,0xD4,0xE0,0x94,0x10,0x90,
+
+	0x43,0xD3,0xE0,0x94,0x35,0x40,0x61,0xA3,
+
+	0xE0,0x94,0x30,0x90,0x43,0xD3,0xE0,0x94,
+
+	0x38,0x50,0x55,0x90,0xF4,0xC1,0xE0,0x64,
+
+	0x01,0x70,0x25,0x90,0xF9,0x00,0xE0,0x70,
+
+	0x0C,0x90,0xF5,0x4B,0x74,0x05,0xF0,0x90,
+
+	0xF6,0x55,0x74,0x20,0xF0,0x90,0xF9,0x00,
+
+	0xE0,0xB4,0x01,0x0C,0x90,0xF5,0x4B,0x74,
+
+	0x04,0xF0,0x90,0xF6,0x55,0x74,0x10,0xF0,
+
+	0x90,0xF4,0xC1,0xE0,0x64,0x02,0x70,0x2C,
+
+	0x90,0xF9,0x00,0xE0,0x70,0x06,0x90,0xF5,
+
+	0x4B,0x74,0x09,0xF0,0x90,0xF9,0x00,0xE0,
+
+	0xB4,0x01,0x06,0x90,0xF5,0x4B,0x74,0x08,
+
+	0xF0,0x90,0xF6,0x55,0x74,0x20,0xF0,0x22,
+
+	0x90,0xF5,0x4B,0x74,0x14,0xF0,0x90,0xF6,
+
+	0x55,0x74,0x20,0xF0,0x22,0xC2,0xAD,0x90,
+
+	0x41,0xD7,0xE0,0xB4,0x22,0x0B,0x7F,0x14,
+
+	0x12,0xAD,0x3C,0x90,0x43,0xAF,0x74,0x01,
+
+	0xF0,0x12,0xA7,0xE7,0x90,0x42,0x53,0xE0,
+
+	0x60,0x05,0xE4,0x90,0x43,0x8D,0xF0,0x90,
+
+	0xF0,0x01,0x74,0x01,0xF0,0xE4,0x90,0x44,
+
+	0xD2,0xF0,0x90,0xF0,0x01,0xE0,0xB4,0x01,
+
+	0xF9,0x12,0x83,0x14,0x90,0x43,0x9C,0xE0,
+
+	0x60,0x20,0x12,0x93,0x50,0x7D,0x33,0x7C,
+
+	0x01,0xE4,0xFF,0x12,0xAB,0xED,0x90,0x44,
+
+	0xAA,0xE0,0x64,0x01,0x60,0xF8,0x90,0x44,
+
+	0xD2,0xE0,0x04,0xF0,0xE0,0xC3,0x94,0x30,
+
+	0x40,0xD0,0xE4,0x90,0x43,0x94,0xF0,0xA3,
+
+	0xF0,0x90,0x43,0x92,0xF0,0xA3,0xF0,0x90,
+
+	0x42,0x04,0xE0,0x90,0x43,0x9D,0xF0,0xD2,
+
+	0xAD,0x90,0x41,0xD7,0xE0,0xB4,0x22,0x10,
+
+	0x90,0x42,0x4B,0xE0,0x60,0x0A,0x7F,0x15,
+
+	0x12,0xAD,0x3C,0xE4,0x90,0x43,0xAF,0xF0,
+
+	0x90,0x42,0x53,0xE0,0x60,0x12,0x90,0x42,
+
+	0x04,0xE0,0x70,0x0C,0x90,0x42,0x40,0xE0,
+
+	0xD3,0x94,0xD0,0x40,0x03,0x12,0xAB,0x20,
+
+	0x22,0x90,0xF7,0x66,0xE0,0x90,0x44,0xC8,
+
+	0xF0,0xE0,0xFF,0x90,0x42,0x43,0xF0,0x90,
+
+	0xF7,0x68,0xE0,0x90,0x44,0xA0,0xF0,0x90,
+
+	0xF5,0xA9,0xE0,0x70,0x09,0xEF,0x60,0x06,
+
+	0x90,0x44,0x9A,0xE0,0x60,0x04,0x7F,0x01,
+
+	0x80,0x02,0x7F,0x00,0x90,0x44,0x9A,0xEF,
+
+	0xF0,0x70,0x03,0x12,0xA4,0x44,0x90,0xF5,
+
+	0xA9,0xE0,0x70,0x2A,0x90,0xF7,0x63,0xE0,
+
+	0x90,0x42,0x2B,0xF0,0x90,0xF7,0x64,0xE0,
+
+	0x90,0x41,0xE4,0xF0,0x90,0xF7,0x65,0xE0,
+
+	0x90,0x44,0x9F,0xF0,0x12,0x9A,0xAE,0x90,
+
+	0x44,0xC8,0xE0,0x90,0x41,0xCD,0xF0,0xE4,
+
+	0x90,0x42,0x42,0xF0,0x80,0x0A,0x90,0x41,
+
+	0xCD,0x74,0x01,0xF0,0x90,0x42,0x42,0xF0,
+
+	0x12,0xA7,0x80,0xE4,0x90,0x44,0xC9,0xF0,
+
+	0x7F,0x00,0x7E,0x28,0x12,0xAF,0x5E,0x20,
+
+	0x8C,0xFD,0x90,0x44,0xC9,0xE0,0x04,0xF0,
+
+	0xE0,0xC3,0x94,0x05,0x40,0xEA,0x12,0xAD,
+
+	0xCE,0x90,0xF7,0x69,0xE0,0x70,0xFA,0x90,
+
+	0xF7,0x6B,0x74,0x01,0xF0,0xE4,0xF0,0x22,
+
+	0x90,0xF5,0xCC,0xE4,0xF0,0xA3,0x74,0x02,
+
+	0xF0,0x90,0xF5,0xD4,0xE0,0x90,0x43,0x09,
+
+	0xF0,0x90,0xF5,0xCB,0xE0,0xB4,0x01,0xF9,
+
+	0x12,0xAD,0x5A,0x90,0xFD,0x33,0xE4,0xF0,
+
+	0x04,0xF0,0x90,0xFD,0x36,0xE0,0xB4,0x01,
+
+	0xF9,0x12,0xA6,0x99,0x90,0x43,0x06,0xE0,
+
+	0xFC,0xA3,0xE0,0xFD,0xA3,0xE0,0xFE,0xA3,
+
+	0xE0,0xFF,0x90,0x43,0x0A,0xE0,0xF8,0xA3,
+
+	0xE0,0xF9,0xA3,0xE0,0xFA,0xA3,0xE0,0xFB,
+
+	0xC3,0x12,0x4B,0x21,0x50,0x06,0x90,0x43,
+
+	0x33,0xE0,0x04,0xF0,0x90,0x43,0x06,0xE0,
+
+	0xFC,0xA3,0xE0,0xFD,0xA3,0xE0,0xFE,0xA3,
+
+	0xE0,0xFF,0x78,0x02,0x12,0x4B,0x45,0x90,
+
+	0x43,0x06,0xE0,0xF8,0xA3,0xE0,0xF9,0xA3,
+
+	0xE0,0xFA,0xA3,0xE0,0x2F,0xFF,0xEA,0x3E,
+
+	0xFE,0xE9,0x3D,0xFD,0xE8,0x3C,0xFC,0x90,
+
+	0x43,0x0A,0xE0,0xF8,0xA3,0xE0,0xF9,0xA3,
+
+	0xE0,0xFA,0xA3,0xE0,0xFB,0xD3,0x12,0x4B,
+
+	0x21,0x40,0x06,0x90,0x43,0x32,0xE0,0x04,
+
+	0xF0,0x22,0x90,0x41,0xD2,0xE0,0x70,0x1D,
+
+	0x90,0xF9,0x57,0xE0,0x54,0xFD,0x44,0x02,
+
+	0xF0,0x90,0x41,0xD2,0x74,0x01,0xF0,0xE4,
+
+	0x90,0x43,0xB8,0xF0,0x90,0x43,0xB6,0xF0,
+
+	0xA3,0xF0,0xF5,0x13,0x22,0x90,0x43,0xB7,
+
+	0xE0,0x60,0x68,0x90,0x43,0xBB,0xE0,0xB4,
+
+	0x01,0x0C,0xE5,0x13,0x90,0xAF,0xA7,0x93,
+
+	0xF5,0x13,0xE4,0xF5,0x14,0x22,0xE5,0x13,
+
+	0x70,0x05,0xF5,0x13,0xF5,0x14,0x22,0xE5,
+
+	0x13,0x90,0xAF,0xD9,0x93,0xB5,0x14,0x1C,
+
+	0x90,0x43,0xCE,0xE0,0xB5,0x13,0x05,0x75,
+
+	0x13,0x01,0x80,0x0C,0x90,0x43,0xCE,0xE5,
+
+	0x13,0xF0,0x90,0xAF,0xBB,0x93,0xF5,0x13,
+
+	0xE4,0xF5,0x14,0x22,0xE5,0x13,0x90,0xAF,
+
+	0xB1,0x93,0xFF,0xB5,0x13,0x03,0x05,0x14,
+
+	0x22,0x90,0x43,0xCF,0xE0,0xB5,0x13,0x08,
+
+	0x90,0xAF,0xBB,0x93,0xF5,0x13,0x80,0x08,
+
+	0x90,0x43,0xCF,0xE5,0x13,0xF0,0x8F,0x13,
+
+	0xE4,0xF5,0x14,0x22,0xE4,0xFB,0xEB,0x25,
+
+	0xE0,0x24,0x36,0xF5,0x82,0xE4,0x34,0x43,
+
+	0xF5,0x83,0xE0,0xFF,0xA3,0xE0,0x90,0x43,
+
+	0x23,0xCF,0xF0,0xA3,0xEF,0xF0,0x12,0xA5,
+
+	0xDA,0x90,0xF5,0xD0,0xE0,0xFF,0xC4,0x13,
+
+	0x54,0x07,0xFF,0x90,0xF5,0xD3,0xE0,0xFE,
+
+	0xC4,0x13,0x54,0x07,0x6F,0x60,0x0D,0x74,
+
+	0x28,0x2B,0xF5,0x82,0xE4,0x34,0x43,0xF5,
+
+	0x83,0xE0,0x04,0xF0,0x0B,0xEB,0xB4,0x08,
+
+	0xBD,0x90,0x43,0x26,0xE0,0x04,0xF0,0xE0,
+
+	0xC3,0x94,0x13,0x40,0x3D,0xE4,0xFF,0xFB,
+
+	0x74,0x28,0x2B,0xF5,0x82,0xE4,0x34,0x43,
+
+	0xF5,0x83,0xE0,0xFE,0xD3,0x94,0x0E,0x50,
+
+	0x06,0xEE,0xC3,0x94,0x05,0x50,0x01,0x0F,
+
+	0x74,0x28,0x2B,0xF5,0x82,0xE4,0x34,0x43,
+
+	0xF5,0x83,0xE4,0xF0,0x0B,0xEB,0xB4,0x08,
+
+	0xD7,0xEF,0xD3,0x94,0x06,0x40,0x06,0x90,
+
+	0x42,0x38,0x74,0x01,0xF0,0xE4,0x90,0x43,
+
+	0x26,0xF0,0x22,0x78,0x7F,0xE4,0xF6,0xD8,
+
+	0xFD,0x75,0x81,0x14,0x02,0x99,0x5B,0x02,
+
+	0x85,0xD1,0xE4,0x93,0xA3,0xF8,0xE4,0x93,
+
+	0xA3,0x40,0x03,0xF6,0x80,0x01,0xF2,0x08,
+
+	0xDF,0xF4,0x80,0x29,0xE4,0x93,0xA3,0xF8,
+
+	0x54,0x07,0x24,0x0C,0xC8,0xC3,0x33,0xC4,
+
+	0x54,0x0F,0x44,0x20,0xC8,0x83,0x40,0x04,
+
+	0xF4,0x56,0x80,0x01,0x46,0xF6,0xDF,0xE4,
+
+	0x80,0x0B,0x01,0x02,0x04,0x08,0x10,0x20,
+
+	0x40,0x80,0x90,0x91,0xE6,0xE4,0x7E,0x01,
+
+	0x93,0x60,0xBC,0xA3,0xFF,0x54,0x3F,0x30,
+
+	0xE5,0x09,0x54,0x1F,0xFE,0xE4,0x93,0xA3,
+
+	0x60,0x01,0x0E,0xCF,0x54,0xC0,0x25,0xE0,
+
+	0x60,0xA8,0x40,0xB8,0xE4,0x93,0xA3,0xFA,
+
+	0xE4,0x93,0xA3,0xF8,0xE4,0x93,0xA3,0xC8,
+
+	0xC5,0x82,0xC8,0xCA,0xC5,0x83,0xCA,0xF0,
+
+	0xA3,0xC8,0xC5,0x82,0xC8,0xCA,0xC5,0x83,
+
+	0xCA,0xDF,0xE9,0xDE,0xE7,0x80,0xBE,0x90,
+
+	0xF1,0x14,0xE0,0xFF,0x90,0x43,0xD6,0xE0,
+
+	0x6F,0x60,0x04,0x7F,0x01,0x80,0x02,0x7F,
+
+	0x00,0x90,0xF1,0x10,0xE0,0xFE,0x90,0x43,
+
+	0xD5,0xE0,0x6E,0x60,0x04,0x7E,0x01,0x80,
+
+	0x02,0x7E,0x00,0xEE,0x4F,0xFF,0x90,0x42,
+
+	0x2A,0xE0,0x64,0x01,0x70,0x3C,0x90,0xF5,
+
+	0x41,0xE0,0x60,0x03,0xEF,0x60,0x40,0x90,
+
+	0xF5,0x41,0xE4,0xF0,0x04,0xF0,0x90,0xF5,
+
+	0x4C,0xE0,0xB4,0x01,0xF9,0x90,0xF6,0x5D,
+
+	0x74,0x01,0xF0,0x90,0xF1,0x10,0xE0,0x70,
+
+	0x06,0x90,0xF1,0x14,0xE0,0x60,0x20,0x90,
+
+	0xF4,0xC1,0xE0,0x70,0x1A,0x90,0xF4,0xC4,
+
+	0xE0,0x70,0x14,0x90,0xF6,0x5C,0x04,0xF0,
+
+	0x80,0x0D,0x90,0xF5,0x41,0xE4,0xF0,0x90,
+
+	0xF6,0x5D,0xF0,0x90,0xF6,0x5C,0xF0,0x90,
+
+	0xF1,0x10,0xE0,0x90,0x43,0xD5,0xF0,0x90,
+
+	0xF1,0x14,0xE0,0x90,0x43,0xD6,0xF0,0x22,
+
+	0x90,0x44,0x85,0xEE,0xF0,0xA3,0xEF,0xF0,
+
+	0xA3,0xED,0xF0,0xE4,0xA3,0xF0,0xA3,0xF0,
+
+	0xA3,0xF0,0x90,0xF4,0x1D,0xE0,0x90,0x44,
+
+	0x8B,0xF0,0x90,0x42,0x64,0xE0,0xFC,0xA3,
+
+	0xE0,0xFD,0xA3,0xE0,0xFE,0xA3,0xE0,0xFF,
+
+	0x90,0x44,0x88,0xE0,0xF8,0xA3,0xE0,0xF9,
+
+	0xA3,0xE0,0xFA,0xA3,0xE0,0xFB,0xC3,0x12,
+
+	0x4B,0x0B,0x40,0x48,0x90,0x44,0x88,0xE0,
+
+	0xFC,0xA3,0xE0,0xFD,0xA3,0xE0,0xFE,0xA3,
+
+	0xE0,0xFF,0x90,0x42,0x64,0x12,0x4B,0x6C,
+
+	0x90,0x44,0x85,0xE0,0xFF,0xA3,0xE0,0x90,
+
+	0x42,0x6C,0xCF,0xF0,0xA3,0xEF,0xF0,0x90,
+
+	0x44,0x87,0xE0,0x70,0x10,0x90,0x42,0x66,
+
+	0xE0,0xFF,0xA3,0xE0,0x90,0x42,0x68,0xCF,
+
+	0xF0,0xA3,0xEF,0xF0,0x22,0x90,0x42,0x66,
+
+	0xE0,0xFF,0xA3,0xE0,0x90,0x42,0x6A,0xCF,
+
+	0xF0,0xA3,0xEF,0xF0,0x22,0x90,0xF9,0x05,
+
+	0xE0,0x60,0x0A,0x90,0xF4,0xC4,0xE0,0x90,
+
+	0x44,0x74,0xF0,0x80,0x08,0x90,0xF4,0xC5,
+
+	0xE0,0x90,0x44,0x74,0xF0,0x90,0x44,0x74,
+
+	0xE0,0x14,0x60,0x20,0x14,0x60,0x2F,0x14,
+
+	0x60,0x3D,0x14,0x60,0x4B,0x24,0x04,0x70,
+
+	0x57,0x90,0xF7,0x7F,0x74,0xE0,0xF0,0xA3,
+
+	0x74,0x01,0xF0,0xA3,0x74,0xBB,0xF0,0xA3,
+
+	0x74,0x01,0xF0,0x22,0x90,0xF7,0x7F,0x74,
+
+	0x40,0xF0,0xA3,0x74,0x01,0xF0,0xA3,0x74,
+
+	0x55,0xF0,0xA3,0xE4,0xF0,0x22,0x90,0xF7,
+
+	0x7F,0x74,0xFA,0xF0,0xA3,0xE4,0xF0,0xA3,
+
+	0x74,0x30,0xF0,0xA3,0xE4,0xF0,0x22,0x90,
+
+	0xF7,0x7F,0x74,0xF5,0xF0,0xA3,0xE4,0xF0,
+
+	0xA3,0x74,0x15,0xF0,0xA3,0xE4,0xF0,0x22,
+
+	0x90,0xF7,0x7F,0x74,0xA0,0xF0,0xA3,0xE4,
+
+	0xF0,0xA3,0x74,0x15,0xF0,0xA3,0xE4,0xF0,
+
+	0x22,0xE4,0xFD,0x90,0xF5,0xF7,0xE0,0xFE,
+
+	0x90,0xF5,0xF6,0xE0,0x7A,0x00,0x24,0x00,
+
+	0xFF,0xEA,0x3E,0x90,0x43,0x4E,0xF0,0xA3,
+
+	0xEF,0xF0,0x90,0x43,0x4E,0xE0,0xFE,0xA3,
+
+	0xE0,0xFF,0xC3,0x94,0x40,0xEE,0x94,0x08,
+
+	0x40,0x0A,0xD3,0xEF,0x94,0x60,0xEE,0x94,
+
+	0x08,0x50,0x01,0x0D,0x90,0x41,0xEF,0xE0,
+
+	0x64,0x02,0x70,0x45,0xED,0x64,0x01,0x70,
+
+	0x40,0x90,0xF9,0x04,0xE0,0x64,0x01,0x70,
+
+	0x38,0x90,0xF9,0x01,0xE0,0x64,0x03,0x70,
+
+	0x30,0x90,0xF9,0x00,0xE0,0x64,0x01,0x70,
+
+	0x28,0x90,0xF9,0x03,0xE0,0x64,0x02,0x70,
+
+	0x20,0x90,0x43,0x65,0xE0,0xFF,0x70,0x0B,
+
+	0x90,0xF5,0x6C,0x74,0xE5,0xF0,0xA3,0x74,
+
+	0x01,0xF0,0x22,0xEF,0xB4,0x01,0x0A,0x90,
+
+	0xF5,0x6C,0x74,0x1B,0xF0,0xA3,0x74,0x02,
+
+	0xF0,0x22,0x90,0x41,0xD6,0xE0,0xB4,0x01,
+
+	0x0B,0x90,0xF0,0x7F,0x74,0x01,0xF0,0xA3,
+
+	0xE4,0xF0,0x80,0x08,0x90,0xF0,0x7F,0xE4,
+
+	0xF0,0xA3,0x04,0xF0,0x90,0x43,0x4B,0x74,
+
+	0x01,0xF0,0xE4,0x90,0x41,0xD1,0xF0,0x90,
+
+	0xF7,0x3C,0xE0,0x60,0x09,0xE4,0x90,0x41,
+
+	0xCE,0xF0,0x90,0x41,0xCD,0xF0,0xE4,0x90,
+
+	0x43,0x47,0xF0,0xA3,0xF0,0x90,0x43,0x49,
+
+	0xF0,0xA3,0xF0,0x90,0x44,0x3B,0x04,0xF0,
+
+	0x12,0x64,0xA5,0x90,0x41,0xE6,0xE0,0x70,
+
+	0x04,0x7F,0x01,0x80,0x02,0x7F,0x00,0x90,
+
+	0x42,0x5F,0xEF,0xF0,0x12,0xAA,0x3A,0x12,
+
+	0xAF,0x90,0x90,0x43,0xD0,0x74,0x01,0xF0,
+
+	0xE4,0x90,0x43,0xBE,0xF0,0x90,0xF7,0x31,
+
+	0xE0,0xB4,0x01,0x03,0x12,0xAC,0x7D,0xE4,
+
+	0x90,0x43,0xBC,0xF0,0x90,0x43,0xBB,0x04,
+
+	0xF0,0x22,0x7F,0xD4,0x7E,0x27,0x12,0xAF,
+
+	0x5E,0x20,0x8C,0xFD,0x90,0xF1,0x48,0x74,
+
+	0x01,0xF0,0x90,0xF0,0x92,0xE4,0xF0,0x90,
+
+	0xF0,0x91,0x04,0xF0,0x90,0xF0,0x94,0xF0,
+
+	0x90,0xF0,0x81,0xF0,0x90,0xF0,0x91,0xE4,
+
+	0xF0,0xA3,0x04,0xF0,0x90,0xF0,0x94,0xE0,
+
+	0xB4,0x01,0xF9,0x90,0xF1,0xFB,0xE4,0xF0,
+
+	0x90,0xF1,0xFA,0x04,0xF0,0x90,0xF1,0xFD,
+
+	0xF0,0x90,0xF1,0xFC,0xF0,0x90,0xF1,0xFA,
+
+	0xE4,0xF0,0xA3,0x04,0xF0,0x90,0xF1,0xFD,
+
+	0xE0,0xB4,0x01,0xF9,0x90,0xF1,0xF7,0xE4,
+
+	0xF0,0x90,0xF1,0xF6,0x04,0xF0,0x90,0xF1,
+
+	0xF9,0xF0,0x90,0xF1,0xF8,0x04,0xF0,0x90,
+
+	0xF2,0x14,0x14,0xF0,0x90,0xF1,0xF6,0xE4,
+
+	0xF0,0xA3,0x04,0xF0,0x90,0xF1,0xF9,0xE0,
+
+	0xB4,0x01,0xF9,0x90,0x43,0xBB,0x74,0x01,
+
+	0xF0,0x22,0x90,0xF1,0xEA,0xE4,0xF0,0x90,
+
+	0xF1,0xEF,0xF0,0x90,0xF1,0xF2,0xF0,0x90,
+
+	0xF0,0x7C,0xF0,0x90,0xF1,0xFB,0xF0,0x90,
+
+	0xF1,0xF7,0xF0,0x90,0xF1,0xE8,0x04,0xF0,
+
+	0x90,0xF1,0xEB,0xF0,0x90,0xF1,0xF0,0xF0,
+
+	0x90,0xF1,0xF3,0xF0,0x90,0xF0,0x7D,0xF0,
+
+	0x90,0xF1,0xFA,0xF0,0x90,0xF1,0xF6,0xF0,
+
+	0x90,0xF1,0xF8,0xE4,0xF0,0x90,0xF1,0xFC,
+
+	0x74,0x03,0xF0,0x90,0xF1,0xE8,0xE4,0xF0,
+
+	0x90,0xF1,0xEB,0xF0,0x90,0xF1,0xF0,0xF0,
+
+	0x90,0xF1,0xF3,0xF0,0x90,0xF0,0x7D,0xF0,
+
+	0x90,0xF1,0xFA,0xF0,0x90,0xF1,0xF6,0xF0,
+
+	0x90,0xF1,0xEA,0x04,0xF0,0x90,0xF1,0xEF,
+
+	0xF0,0x90,0xF1,0xF2,0xF0,0x90,0xF0,0x7C,
+
+	0xF0,0x90,0xF1,0xF7,0xF0,0x90,0xF1,0xFB,
+
+	0xF0,0x90,0xF5,0xC2,0xF0,0xE4,0xF0,0x22,
+
+	0xEF,0xB4,0x02,0x1B,0x90,0x43,0xD7,0x74,
+
+	0x0B,0xF0,0xA3,0x74,0xB3,0xF0,0xA3,0x74,
+
+	0x0A,0xF0,0xA3,0x74,0x73,0xF0,0xA3,0x74,
+
+	0x33,0xF0,0xA3,0x74,0xE5,0xF0,0x22,0xEF,
+
+	0xB4,0x04,0x1B,0x90,0x43,0xD7,0x74,0x0B,
+
+	0xF0,0xA3,0x74,0xE3,0xF0,0xA3,0x74,0x0A,
+
+	0xF0,0xA3,0x74,0x9D,0xF0,0xA3,0x74,0x33,
+
+	0xF0,0xA3,0x74,0xB3,0xF0,0x22,0xEF,0xB4,
+
+	0x05,0x1B,0x90,0x43,0xD7,0x74,0x0B,0xF0,
+
+	0xA3,0x74,0xA3,0xF0,0xA3,0x74,0x0A,0xF0,
+
+	0xA3,0x74,0x65,0xF0,0xA3,0x74,0x33,0xF0,
+
+	0xA3,0x74,0xF4,0xF0,0x22,0xEF,0xB4,0x0B,
+
+	0x1A,0x90,0x43,0xD7,0x74,0x0B,0xF0,0xA3,
+
+	0x74,0xD5,0xF0,0xA3,0x74,0x0A,0xF0,0xA3,
+
+	0x74,0x91,0xF0,0xA3,0x74,0x33,0xF0,0xA3,
+
+	0x74,0xC1,0xF0,0x22,0x90,0xF1,0x61,0xE0,
+
+	0xFE,0x90,0xF1,0x60,0xE0,0x7C,0x00,0x24,
+
+	0x00,0xFF,0xEC,0x3E,0x90,0x44,0xC6,0xF0,
+
+	0xA3,0xEF,0xF0,0x90,0x42,0x52,0xE0,0x60,
+
+	0x5A,0xE4,0x90,0x43,0x9E,0xF0,0xA3,0xF0,
+
+	0x90,0xF2,0x10,0xE0,0x90,0x43,0xA0,0xF0,
+
+	0x90,0xF2,0x0F,0xE0,0x90,0x43,0xA1,0xF0,
+
+	0x90,0x42,0x40,0xE0,0xFF,0xE4,0xFC,0xFD,
+
+	0xFE,0x90,0x43,0x9E,0xE0,0xF8,0xA3,0xE0,
+
+	0xF9,0xA3,0xE0,0xFA,0xA3,0xE0,0xFB,0x12,
+
+	0x4A,0xAE,0x90,0x43,0x9E,0x12,0x4B,0x6C,
+
+	0x90,0x43,0x9E,0xE0,0xFC,0xA3,0xE0,0xFD,
+
+	0xA3,0xE0,0xFE,0xA3,0xE0,0xFF,0x90,0xF2,
+
+	0x11,0xE0,0xF9,0xF8,0x12,0x4B,0x32,0x90,
+
+	0x43,0xA3,0xE0,0x2F,0xF0,0x90,0x43,0xA2,
+
+	0xE0,0x3E,0xF0,0x22,0x90,0xF5,0x6C,0x74,
+
+	0x40,0xF0,0xA3,0x74,0x07,0xF0,0x90,0xF9,
+
+	0x00,0xE0,0x70,0x16,0x90,0xF5,0x6A,0xF0,
+
+	0xA3,0x74,0x05,0xF0,0x90,0xF5,0x70,0x74,
+
+	0x03,0xF0,0x90,0xF5,0x6F,0x74,0x01,0xF0,
+
+	0x80,0x32,0x90,0xF9,0x00,0xE0,0xB4,0x01,
+
+	0x16,0x90,0xF5,0x6A,0xE4,0xF0,0xA3,0x74,
+
+	0x04,0xF0,0x90,0xF5,0x70,0x04,0xF0,0x90,
+
+	0xF5,0x6F,0x74,0x03,0xF0,0x80,0x15,0x90,
+
+	0xF5,0x6A,0xE4,0xF0,0xA3,0x74,0x0A,0xF0,
+
+	0x90,0xF5,0x70,0x74,0x04,0xF0,0x90,0xF5,
+
+	0x6F,0x74,0x02,0xF0,0x90,0xFD,0x27,0x74,
+
+	0x03,0xF0,0x90,0xFD,0x31,0x74,0x40,0xF0,
+
+	0xA3,0xE4,0xF0,0x22,0x90,0xF5,0x6C,0x74,
+
+	0x80,0xF0,0xA3,0x74,0x06,0xF0,0x90,0xF9,
+
+	0x00,0xE0,0x70,0x16,0x90,0xF5,0x6A,0xF0,
+
+	0xA3,0x74,0x0A,0xF0,0x90,0xF5,0x70,0x74,
+
+	0x04,0xF0,0x90,0xF5,0x6F,0x74,0x02,0xF0,
+
+	0x80,0x32,0x90,0xF9,0x00,0xE0,0xB4,0x01,
+
+	0x17,0x90,0xF5,0x6A,0xE4,0xF0,0xA3,0x74,
+
+	0x08,0xF0,0x90,0xF5,0x70,0x74,0x06,0xF0,
+
+	0x90,0xF5,0x6F,0x74,0x04,0xF0,0x80,0x14,
+
+	0x90,0xF5,0x6A,0xE4,0xF0,0xA3,0x74,0x04,
+
+	0xF0,0x90,0xF5,0x70,0x04,0xF0,0x90,0xF5,
+
+	0x6F,0x74,0x03,0xF0,0x90,0xFD,0x27,0x74,
+
+	0x04,0xF0,0x90,0xFD,0x31,0x74,0x80,0xF0,
+
+	0xA3,0xE4,0xF0,0x22,0x90,0x42,0x36,0xE0,
+
+	0x64,0x01,0x70,0x5D,0x90,0x42,0x3C,0xE0,
+
+	0x70,0x04,0x90,0x42,0xF8,0xF0,0x90,0x42,
+
+	0x3D,0xE0,0x64,0x01,0x70,0x30,0x90,0x42,
+
+	0xF8,0xE0,0x64,0x01,0x70,0x28,0x90,0xFD,
+
+	0xA5,0x04,0xF0,0x90,0xF9,0x00,0xE0,0x60,
+
+	0x05,0x90,0xF9,0x00,0xE0,0xFF,0x12,0x98,
+
+	0x85,0x90,0x42,0x38,0xE0,0xB4,0x01,0x29,
+
+	0xE4,0x90,0x42,0xF8,0xF0,0x12,0xAE,0xFD,
+
+	0xE4,0x90,0x42,0x38,0xF0,0x22,0x90,0xFD,
+
+	0xA5,0xE4,0xF0,0x90,0x42,0xF8,0xE0,0xB4,
+
+	0x01,0x0C,0x12,0xAE,0xFD,0xE4,0x90,0x42,
+
+	0x38,0xF0,0x90,0x42,0xF8,0xF0,0x12,0x57,
+
+	0x52,0x22,0x90,0x42,0x4A,0xE0,0x60,0x06,
+
+	0x90,0xFB,0x2A,0x74,0x71,0xF0,0x90,0xFB,
+
+	0x97,0xE4,0xF0,0x7F,0x11,0x12,0xAD,0x3C,
+
+	0xE4,0x90,0x44,0xD6,0xF0,0x74,0xFF,0xFB,
+
+	0xFA,0xE4,0xFD,0x7F,0x01,0x12,0xAC,0x13,
+
+	0x90,0x44,0xD6,0xE0,0x04,0xF0,0xE0,0xC3,
+
+	0x94,0x02,0x40,0xE9,0x90,0xFB,0x08,0xE0,
+
+	0xFE,0x90,0xFB,0x07,0xE0,0x7C,0x00,0x24,
+
+	0x00,0xFF,0xEC,0x3E,0x90,0x44,0x50,0xF0,
+
+	0xA3,0xEF,0xF0,0xE0,0x90,0x41,0xFC,0xF0,
+
+	0x90,0xFB,0x97,0x74,0x01,0xF0,0x7F,0x11,
+
+	0x12,0xAD,0x3C,0x90,0x42,0x4A,0xE0,0x60,
+
+	0x06,0x90,0xFB,0x2A,0x74,0x75,0xF0,0x22,
+
+	0xE5,0x13,0x14,0xB4,0x08,0x00,0x50,0x5D,
+
+	0x90,0x9F,0xD7,0x75,0xF0,0x03,0xA4,0xC5,
+
+	0x83,0x25,0xF0,0xC5,0x83,0x73,0x02,0x9F,
+
+	0xEF,0x02,0x9F,0xF6,0x02,0x9F,0xFD,0x02,
+
+	0xA0,0x04,0x02,0xA0,0x0B,0x02,0xA0,0x12,
+
+	0x02,0xA0,0x19,0x02,0xA0,0x20,0x90,0xF2,
+
+	0x1B,0x74,0x01,0xF0,0x22,0x90,0xF2,0x1B,
+
+	0x74,0x02,0xF0,0x22,0x90,0xF2,0x1B,0x74,
+
+	0x03,0xF0,0x22,0x90,0xF2,0x1B,0x74,0x04,
+
+	0xF0,0x22,0x90,0xF2,0x1B,0x74,0x05,0xF0,
+
+	0x22,0x90,0xF2,0x1B,0x74,0x06,0xF0,0x22,
+
+	0x90,0xF2,0x1B,0x74,0x07,0xF0,0x22,0x90,
+
+	0xF2,0x1B,0x74,0x08,0xF0,0x22,0x90,0xF5,
+
+	0x6C,0xE4,0xF0,0xA3,0x74,0x05,0xF0,0x90,
+
+	0xF9,0x00,0xE0,0x70,0x15,0x90,0xF5,0x6A,
+
+	0xF0,0xA3,0x74,0x04,0xF0,0x90,0xF5,0x70,
+
+	0x04,0xF0,0x90,0xF5,0x6F,0x74,0x03,0xF0,
+
+	0x80,0x31,0x90,0xF9,0x00,0xE0,0xB4,0x01,
+
+	0x15,0x90,0xF5,0x6A,0xE4,0xF0,0xA3,0xF0,
+
+	0x90,0xF5,0x70,0x74,0x07,0xF0,0x90,0xF5,
+
+	0x6F,0x74,0x05,0xF0,0x80,0x15,0x90,0xF5,
+
+	0x6A,0xE4,0xF0,0xA3,0x74,0x08,0xF0,0x90,
+
+	0xF5,0x70,0x74,0x06,0xF0,0x90,0xF5,0x6F,
+
+	0x74,0x04,0xF0,0x90,0xFD,0x27,0x74,0x07,
+
+	0xF0,0x90,0xFD,0x31,0xE4,0xF0,0xA3,0x04,
+
+	0xF0,0x22,0x90,0xF5,0x6C,0xE4,0xF0,0xA3,
+
+	0x74,0x02,0xF0,0x90,0xF9,0x00,0xE0,0x70,
+
+	0x16,0x90,0xF5,0x6A,0xF0,0xA3,0x74,0x08,
+
+	0xF0,0x90,0xF5,0x70,0x74,0x04,0xF0,0x90,
+
+	0xF5,0x6F,0x74,0x02,0xF0,0x80,0x2F,0x90,
+
+	0xF9,0x00,0xE0,0xB4,0x01,0x15,0x90,0xF5,
+
+	0x6A,0xE4,0xF0,0xA3,0xF0,0x90,0xF5,0x70,
+
+	0x74,0x06,0xF0,0x90,0xF5,0x6F,0x74,0x04,
+
+	0xF0,0x80,0x13,0x90,0xF5,0x6A,0xE4,0xF0,
+
+	0xA3,0xF0,0x90,0xF5,0x70,0x74,0x05,0xF0,
+
+	0x90,0xF5,0x6F,0x74,0x03,0xF0,0x90,0xFD,
+
+	0x27,0x74,0x07,0xF0,0x90,0xFD,0x31,0xE4,
+
+	0xF0,0xA3,0x74,0x02,0xF0,0x22,0x90,0xF4,
+
+	0x1A,0x74,0x0D,0xF0,0x90,0xF4,0x10,0x74,
+
+	0x08,0xF0,0x90,0xF4,0x18,0xF0,0x90,0xF5,
+
+	0x61,0x74,0x06,0xF0,0xE4,0x90,0x44,0xCD,
+
+	0xF0,0x90,0x42,0x59,0xF0,0x90,0x42,0x5B,
+
+	0xF0,0x90,0x42,0x5C,0xF0,0x90,0x42,0x5E,
+
+	0xF0,0x90,0x42,0x5A,0xF0,0x90,0x42,0x5D,
+
+	0xF0,0x90,0x42,0x57,0x04,0xF0,0x90,0xF5,
+
+	0xBD,0xF0,0x90,0xF5,0xBB,0xF0,0x90,0xF5,
+
+	0xBD,0xE4,0xF0,0x90,0xF5,0xBF,0x04,0xF0,
+
+	0x90,0x42,0x58,0xF0,0x90,0xF5,0xB3,0xF0,
+
+	0x90,0xF5,0xB1,0xF0,0x90,0xF5,0xB3,0xE4,
+
+	0xF0,0x90,0xF5,0xB2,0x04,0xF0,0xD2,0xE9,
+
+	0x22,0xD0,0xE0,0xF5,0xF0,0xFC,0xD0,0xE0,
+
+	0xFD,0x12,0x4C,0x61,0x85,0x0F,0xF0,0xE5,
+
+	0x81,0x90,0x00,0x02,0x12,0x4C,0x80,0x85,
+
+	0x0E,0xF0,0xE5,0x0D,0x90,0x00,0x04,0x12,
+
+	0x4C,0x80,0xE5,0x10,0x90,0x00,0x06,0x12,
+
+	0x4B,0xDC,0x8D,0x82,0x8C,0x83,0xE4,0xFE,
+
+	0xFF,0x73,0xED,0xFF,0xEC,0xFE,0x12,0x4B,
+
+	0xFE,0xFC,0xAD,0xF0,0x90,0x00,0x02,0x12,
+
+	0x4C,0x29,0x85,0xF0,0x81,0xF5,0x0F,0x90,
+
+	0x00,0x04,0x12,0x4C,0x29,0xF5,0x0E,0x85,
+
+	0xF0,0x0D,0x90,0x00,0x06,0x12,0x4B,0xAF,
+
+	0xF5,0x10,0x8D,0x82,0x8C,0x83,0xE4,0x73,
+
+	0x12,0xAB,0xC7,0xE4,0x90,0x41,0xD8,0xF0,
+
+	0x90,0x41,0xE7,0xE0,0x90,0xF0,0x76,0xF0,
+
+	0x90,0x43,0xB6,0x74,0x01,0xF0,0x90,0x43,
+
+	0xBB,0xF0,0x90,0x43,0xB7,0xF0,0xE4,0x90,
+
+	0x43,0xBA,0xF0,0xF5,0x13,0x90,0x41,0xDD,
+
+	0xE0,0xB4,0x01,0x14,0x90,0x44,0x71,0x74,
+
+	0x01,0xF0,0x12,0x9B,0xB3,0x12,0xAF,0x51,
+
+	0x90,0xFB,0xA8,0x74,0x01,0xF0,0x80,0x16,
+
+	0x90,0xFB,0xA8,0xE4,0xF0,0x12,0xAF,0x1A,
+
+	0xE4,0x90,0x44,0x71,0xF0,0x90,0x42,0x47,
+
+	0xE0,0x60,0x03,0x12,0x9F,0x5B,0xE4,0x90,
+
+	0x41,0xDD,0xF0,0x22,0x90,0x41,0xD5,0xE0,
+
+	0x60,0x07,0x90,0xF0,0x2B,0xE4,0xF0,0x80,
+
+	0x39,0x90,0x42,0x01,0xE0,0xF9,0x90,0x42,
+
+	0x02,0xE0,0x89,0xF0,0xA4,0xFF,0x90,0x43,
+
+	0xB4,0xE0,0xFC,0xA3,0xE0,0xFD,0xD3,0x9F,
+
+	0xEC,0x95,0xF0,0x40,0x08,0x90,0xF0,0x2B,
+
+	0x74,0x01,0xF0,0x80,0x15,0x90,0x42,0x03,
+
+	0xE0,0x89,0xF0,0xA4,0xFF,0xC3,0xED,0x9F,
+
+	0xEC,0x95,0xF0,0x50,0x05,0x90,0xF0,0x2B,
+
+	0xE4,0xF0,0x90,0xF0,0x2B,0xE0,0x60,0x07,
+
+	0x90,0x43,0xAA,0x74,0x15,0xF0,0x22,0x90,
+
+	0x42,0x29,0xE0,0x90,0x43,0xAA,0xF0,0x22,
+
+	0xC2,0xAF,0x90,0x44,0xCD,0xE0,0x04,0xF0,
+
+	0x12,0x74,0x95,0x90,0xF5,0xBE,0x74,0x01,
+
+	0xF0,0x12,0x77,0x1C,0x90,0x44,0x9B,0x74,
+
+	0x01,0xF0,0x90,0x44,0xCD,0xE0,0x64,0xAF,
+
+	0x70,0x31,0x90,0xF5,0xC1,0xE0,0x70,0x04,
+
+	0x90,0x42,0x57,0xF0,0x90,0xF5,0xBA,0xE0,
+
+	0x70,0x04,0x90,0x42,0x58,0xF0,0x90,0x42,
+
+	0x58,0xE0,0x70,0x17,0x90,0x42,0x57,0xE0,
+
+	0x70,0x11,0x90,0xF5,0xB9,0x04,0xF0,0x90,
+
+	0xF5,0xC0,0xF0,0xD2,0xE9,0x90,0x44,0x9B,
+
+	0xF0,0xD2,0xEA,0x53,0x91,0xDF,0xD2,0xAF,
+
+	0x22,0xAD,0x07,0x75,0x0A,0x01,0x75,0x0B,
+
+	0xFE,0x75,0x0C,0x01,0xE4,0xF5,0x08,0xF5,
+
+	0x09,0xED,0x60,0x3B,0xB4,0x01,0x16,0xAB,
+
+	0x0A,0xAA,0x0B,0xA9,0x0C,0x12,0x49,0xF8,
+
+	0xFE,0xE4,0x25,0x09,0xF5,0x09,0xEE,0x35,
+
+	0x08,0xF5,0x08,0x80,0x22,0x85,0x0C,0x82,
+
+	0x85,0x0B,0x83,0xE0,0xFE,0xA3,0xE0,0x25,
+
+	0x09,0xF5,0x09,0xEE,0x35,0x08,0xF5,0x08,
+
+	0x74,0x02,0x25,0x0C,0xF5,0x0C,0xE4,0x35,
+
+	0x0B,0xF5,0x0B,0x1D,0x1D,0x80,0xC2,0xAE,
+
+	0x08,0xAF,0x09,0x22,0x90,0xFB,0x08,0xE0,
+
+	0xFE,0x90,0xFB,0x07,0xE0,0x7C,0x00,0x24,
+
+	0x00,0xFF,0xEC,0x3E,0xFE,0x90,0x44,0x50,
+
+	0xE0,0xFC,0xA3,0xE0,0xFD,0xC3,0xEF,0x9D,
+
+	0xFF,0xEE,0x9C,0xFE,0x90,0x42,0x45,0xE0,
+
+	0xFD,0xEF,0xA8,0x05,0x08,0x80,0x05,0xCE,
+
+	0xC3,0x13,0xCE,0x13,0xD8,0xF9,0xFF,0x90,
+
+	0xFB,0x28,0xE0,0xB4,0x86,0x13,0x90,0x42,
+
+	0x00,0xE0,0xFE,0xA8,0x05,0x08,0x80,0x02,
+
+	0xC3,0x13,0xD8,0xFC,0xFE,0xC3,0xEF,0x9E,
+
+	0xFF,0x90,0x41,0xFD,0xEF,0xF0,0x22,0x90,
+
+	0x42,0x52,0xE0,0x60,0x43,0x90,0x43,0x8E,
+
+	0xE0,0xFF,0xD3,0x94,0x01,0x50,0x07,0xEF,
+
+	0x60,0x36,0x74,0x02,0xF0,0x22,0x90,0x43,
+
+	0xA2,0xE0,0xFE,0xA3,0xE0,0xFF,0xA3,0xEE,
+
+	0xF0,0xA3,0xEF,0xF0,0xD3,0x94,0x50,0xEE,
+
+	0x94,0x07,0x40,0x08,0x90,0x41,0xD5,0x74,
+
+	0x01,0xF0,0x80,0x0E,0xC3,0xEF,0x94,0x50,
+
+	0xEE,0x94,0x05,0x50,0x05,0xE4,0x90,0x41,
+
+	0xD5,0xF0,0x90,0x43,0x8E,0x74,0x03,0xF0,
+
+	0x22,0x90,0x42,0x3B,0xE0,0x64,0x01,0x70,
+
+	0x40,0x90,0xFD,0x9D,0xE0,0xFE,0x90,0xFD,
+
+	0x9C,0xE0,0x7C,0x00,0x24,0x00,0xFF,0xEC,
+
+	0x3E,0xFE,0xC3,0xEF,0x94,0x46,0xEE,0x94,
+
+	0x00,0x50,0x26,0x90,0xFD,0x37,0xE0,0xB4,
+
+	0x07,0x1F,0xE4,0x90,0x42,0x39,0xF0,0x90,
+
+	0xFD,0x2B,0xF0,0x7D,0xFF,0x7C,0x7F,0xFF,
+
+	0x12,0xAB,0xED,0x90,0x44,0xAA,0xE0,0x64,
+
+	0x01,0x60,0xF8,0x90,0xFD,0x2B,0x74,0x01,
+
+	0xF0,0x22,0x90,0x42,0x2B,0xE0,0x90,0xF7,
+
+	0x5A,0xF0,0x90,0x41,0xE5,0xE0,0x90,0xF7,
+
+	0x5B,0xF0,0x90,0x42,0x33,0xE0,0x90,0xF7,
+
+	0x5C,0xF0,0xA3,0xEF,0xF0,0x90,0xF9,0x00,
+
+	0xE0,0x90,0xF7,0x5E,0xF0,0x90,0x41,0xDB,
+
+	0xE0,0x90,0xF7,0x5F,0xF0,0x90,0xF7,0x61,
+
+	0x74,0x01,0xF0,0x90,0xF7,0x60,0xF0,0x7F,
+
+	0x00,0x7E,0x28,0x12,0xAF,0x5E,0x20,0x8C,
+
+	0xFD,0x90,0xF7,0x61,0xE4,0xF0,0x90,0xF7,
+
+	0x60,0xF0,0x22,0x90,0x44,0x9A,0x74,0x01,
+
+	0xF0,0x90,0xF7,0x42,0xE0,0x90,0x44,0x9C,
+
+	0xF0,0xE0,0x90,0xF9,0x00,0xF0,0x90,0xF7,
+
+	0x44,0xE0,0xFF,0x90,0xF9,0x08,0xF0,0x90,
+
+	0xF7,0x43,0xE0,0xFF,0x90,0xF9,0x03,0xF0,
+
+	0x90,0xF7,0x46,0xE0,0xFF,0x90,0xF9,0x06,
+
+	0xF0,0x90,0xF7,0x47,0xE0,0xFF,0x90,0xF9,
+
+	0x07,0xF0,0x90,0xF7,0x45,0xE0,0x54,0x03,
+
+	0xFF,0x90,0xF9,0x02,0xF0,0x90,0xF9,0x05,
+
+	0x74,0x01,0xF0,0x22,0x75,0xF0,0x02,0xE5,
+
+	0x13,0xA4,0x24,0xC5,0xF5,0x82,0xE5,0xF0,
+
+	0x34,0xAF,0xF5,0x83,0xE4,0x93,0xFC,0x74,
+
+	0x01,0x93,0xFD,0xE4,0xFF,0x12,0xAB,0xED,
+
+	0x90,0xF1,0x48,0xE4,0xF0,0x90,0xF0,0x81,
+
+	0x74,0x03,0xF0,0x90,0xF1,0xFC,0xF0,0x90,
+
+	0xF5,0xAF,0xE4,0xF0,0x04,0xF0,0x90,0xF5,
+
+	0xB4,0xE0,0xB4,0x01,0xF9,0x90,0xF5,0xAF,
+
+	0xE4,0xF0,0x90,0x43,0xBB,0x04,0xF0,0x22,
+
+	0xC2,0xD5,0xE8,0x30,0xE7,0x0F,0xB2,0xD5,
+
+	0xE4,0xC3,0x9B,0xFB,0xE4,0x9A,0xFA,0xE4,
+
+	0x99,0xF9,0xE4,0x98,0xF8,0xEC,0x30,0xE7,
+
+	0x17,0xB2,0xD5,0x12,0xA5,0x07,0x12,0x4C,
+
+	0xE9,0xE4,0xC3,0x9B,0xFB,0xE4,0x9A,0xFA,
+
+	0xE4,0x99,0xF9,0xE4,0x98,0xF8,0x80,0x03,
+
+	0x12,0x4C,0xE9,0x30,0xD5,0x0D,0xE4,0xC3,
+
+	0x9F,0xFF,0xE4,0x9E,0xFE,0xE4,0x9D,0xFD,
+
+	0xE4,0x9C,0xFC,0x22,0xE4,0x90,0x43,0xDD,
+
+	0xF0,0x90,0xF9,0x00,0xE0,0x70,0x09,0x90,
+
+	0x42,0x26,0xE0,0x90,0x43,0xDD,0xF0,0x22,
+
+	0x90,0xF9,0x00,0xE0,0xB4,0x01,0x1F,0x90,
+
+	0x41,0xE5,0xE0,0xB4,0x01,0x09,0x90,0x42,
+
+	0x24,0xE0,0x90,0x43,0xDD,0xF0,0x22,0x90,
+
+	0xF0,0x2B,0xE0,0x70,0x11,0x90,0x42,0x27,
+
+	0xE0,0x90,0x43,0xDD,0xF0,0x22,0x90,0x42,
+
+	0x25,0xE0,0x90,0x43,0xDD,0xF0,0x22,0x90,
+
+	0x41,0xD7,0xE0,0x64,0x27,0x70,0x38,0x90,
+
+	0x43,0xB0,0xE0,0xB4,0x01,0x1B,0x90,0x41,
+
+	0xD5,0xE0,0x64,0x01,0x60,0x08,0x90,0x41,
+
+	0xDC,0xE0,0x64,0x01,0x60,0x0B,0xE4,0x90,
+
+	0x43,0xB0,0xF0,0x7F,0x17,0x12,0xAD,0x3C,
+
+	0x22,0x90,0x43,0xB0,0xE0,0x70,0x10,0x90,
+
+	0x41,0xD5,0xE0,0x70,0x0A,0x90,0x43,0xB0,
+
+	0x04,0xF0,0x7F,0x16,0x12,0xAD,0x3C,0x22,
+
+	0xE5,0x13,0xD3,0x94,0x02,0x40,0x39,0x90,
+
+	0x43,0xB1,0xE0,0xB4,0x01,0x03,0x12,0xAC,
+
+	0x37,0x90,0x43,0xB1,0xE0,0x70,0x29,0x90,
+
+	0x42,0x01,0xE0,0xFF,0x90,0x43,0xB2,0xE0,
+
+	0xC3,0x9F,0x50,0x0D,0x12,0xA6,0x1B,0x12,
+
+	0x9D,0xAD,0x90,0x43,0xB2,0xE0,0x04,0xF0,
+
+	0x22,0x90,0x43,0xB1,0x74,0x01,0xF0,0x12,
+
+	0xA3,0x68,0x12,0xA2,0x0D,0x12,0xAD,0x1D,
+
+	0x22,0x90,0xF9,0x00,0xE0,0x70,0x19,0x90,
+
+	0x43,0x23,0xE0,0xFE,0xA3,0xE0,0xFF,0x7C,
+
+	0x06,0x7D,0xA8,0x12,0x4A,0x23,0x90,0x43,
+
+	0x23,0xEC,0xF0,0xA3,0xED,0xF0,0x80,0x1E,
+
+	0x90,0xF9,0x00,0xE0,0xB4,0x02,0x17,0x90,
+
+	0x43,0x23,0xE0,0xFE,0xA3,0xE0,0xFF,0x7C,
+
+	0x0D,0x7D,0x50,0x12,0x4A,0x23,0x90,0x43,
+
+	0x23,0xEC,0xF0,0xA3,0xED,0xF0,0x12,0xAC,
+
+	0x5B,0x22,0x90,0x43,0xB2,0xE0,0xD3,0x94,
+
+	0x00,0x40,0x2E,0x90,0x42,0x40,0xE0,0xFE,
+
+	0x90,0x43,0xB3,0xE0,0xFD,0xD3,0x9E,0x40,
+
+	0x05,0xED,0x9E,0xFF,0x80,0x0C,0x90,0x43,
+
+	0xB3,0xE0,0xFE,0x90,0x42,0x40,0xE0,0xC3,
+
+	0x9E,0xFF,0xEF,0xFD,0x90,0x43,0xB5,0xE0,
+
+	0x2D,0xF0,0x90,0x43,0xB4,0xE0,0x34,0x00,
+
+	0xF0,0x90,0x42,0x40,0xE0,0x90,0x43,0xB3,
+
+	0xF0,0x22,0x90,0x44,0xC4,0xEE,0xF0,0xA3,
+
+	0xEF,0xF0,0x75,0x11,0xFE,0x75,0x12,0x03,
+
+	0xED,0x60,0x2C,0x90,0x44,0xC4,0xE0,0xFE,
+
+	0xA3,0xE0,0xF5,0x82,0x8E,0x83,0xE0,0x85,
+
+	0x12,0x82,0x85,0x11,0x83,0xF0,0x90,0x44,
+
+	0xC5,0xE0,0x04,0xF0,0x70,0x06,0x90,0x44,
+
+	0xC4,0xE0,0x04,0xF0,0x05,0x12,0xE5,0x12,
+
+	0x70,0x02,0x05,0x11,0x1D,0x80,0xD1,0x22,
+
+	0x90,0xFD,0x47,0xE0,0x90,0x43,0x0A,0xF0,
+
+	0x90,0xFD,0x46,0xE0,0x90,0x43,0x0B,0xF0,
+
+	0x90,0xFD,0x45,0xE0,0x90,0x43,0x0C,0xF0,
+
+	0x90,0xFD,0x44,0xE0,0x90,0x43,0x0D,0xF0,
+
+	0x90,0x43,0x0A,0xE0,0xFC,0xA3,0xE0,0xFD,
+
+	0xA3,0xE0,0xFE,0xA3,0xE0,0xFF,0x90,0x43,
+
+	0x20,0xE0,0xF9,0xF8,0x12,0x4B,0x32,0x90,
+
+	0x43,0x0A,0x12,0x4B,0x6C,0x22,0x90,0xF7,
+
+	0x3C,0xE0,0x70,0x21,0x90,0xF7,0x31,0xE0,
+
+	0x60,0x07,0xE4,0xFF,0x12,0xA3,0xFB,0x80,
+
+	0x14,0x90,0xFB,0x88,0xE0,0x64,0x01,0x60,
+
+	0xF8,0x90,0xFB,0x96,0x74,0x0D,0xF0,0x90,
+
+	0xFB,0x88,0x74,0x01,0xF0,0x12,0xAB,0xC7,
+
+	0x12,0xAE,0x8F,0x90,0xF7,0x2F,0xE4,0xF0,
+
+	0x90,0x43,0xBA,0x04,0xF0,0x12,0xAD,0x95,
+
+	0x22,0x90,0xFB,0x86,0xE0,0x60,0x32,0x90,
+
+	0x44,0x72,0xE0,0x70,0x24,0x90,0xFE,0x00,
+
+	0xE0,0x24,0x01,0xFF,0xE4,0x33,0xFE,0x90,
+
+	0xFB,0x82,0xE0,0xC3,0x9F,0xEE,0x64,0x80,
+
+	0xF8,0x74,0x80,0x98,0x50,0x0B,0xE0,0xF4,
+
+	0x60,0x07,0x90,0xFB,0x86,0x74,0x01,0xF0,
+
+	0x22,0x90,0xFB,0x82,0xE4,0xF0,0x12,0x5F,
+
+	0x96,0x22,0x90,0xF7,0x14,0xE0,0x60,0x2E,
+
+	0x90,0xF7,0x32,0xE0,0x70,0x06,0x90,0xF7,
+
+	0x3C,0xE0,0x60,0x22,0xC2,0xAF,0x90,0xF7,
+
+	0x14,0xE4,0xF0,0x7B,0xD4,0x7A,0x27,0xFD,
+
+	0x7F,0x01,0x12,0xAC,0x13,0x90,0xF9,0x9D,
+
+	0x74,0x01,0xF0,0x90,0xF7,0x16,0xF0,0x90,
+
+	0xF7,0x11,0xE4,0xF0,0xD2,0xAF,0x22,0x90,
+
+	0x42,0x2B,0xE0,0x60,0x2D,0x90,0xF0,0x2B,
+
+	0xE0,0x70,0x1B,0x90,0x43,0x4C,0xE0,0x70,
+
+	0x06,0x90,0xF9,0x00,0xE0,0x70,0x0F,0x90,
+
+	0x41,0xE4,0xE0,0x70,0x09,0x90,0xF7,0x84,
+
+	0xF0,0x90,0xF7,0x83,0xF0,0x22,0x90,0xF7,
+
+	0x84,0x74,0x01,0xF0,0x90,0xF7,0x83,0x74,
+
+	0xFF,0xF0,0x22,0x90,0xFD,0x15,0x74,0x08,
+
+	0xF0,0xA3,0x74,0x10,0xF0,0xA3,0xE4,0xF0,
+
+	0x90,0xFD,0x05,0x04,0xF0,0x90,0xFD,0x2B,
+
+	0xF0,0x90,0xFD,0x2A,0xF0,0x90,0x44,0xCA,
+
+	0xEF,0xF0,0xE4,0x90,0x42,0x39,0xF0,0x90,
+
+	0xFD,0x2C,0x04,0xF0,0xFF,0x12,0xAE,0x43,
+
+	0x90,0xFD,0x2C,0xE4,0xF0,0x22,0x90,0x42,
+
+	0x06,0xE0,0xFF,0x90,0xF0,0x58,0xF0,0xEF,
+
+	0xF0,0x90,0x42,0x09,0xE0,0x90,0xF0,0x58,
+
+	0xF0,0x90,0x42,0x0C,0xE0,0x90,0x42,0x04,
+
+	0xF0,0xE4,0x90,0x43,0x8F,0xF0,0x90,0x43,
+
+	0x8E,0xF0,0x90,0x43,0xAE,0x74,0x02,0xF0,
+
+	0xE4,0x90,0x41,0xD5,0xF0,0x12,0xAF,0x28,
+
+	0x22,0x90,0x43,0xA8,0xE0,0x04,0xF0,0xE0,
+
+	0x54,0x01,0xF0,0x70,0x10,0x90,0x42,0x49,
+
+	0xE0,0xFF,0x90,0xF0,0x1F,0xF0,0x90,0xF0,
+
+	0x29,0xEF,0xF0,0x80,0x0E,0x90,0x42,0x48,
+
+	0xE0,0xFF,0x90,0xF0,0x1F,0xF0,0x90,0xF0,
+
+	0x29,0xEF,0xF0,0x90,0x43,0xA8,0xE0,0x90,
+
+	0x43,0xAE,0xF0,0x22,0x90,0x43,0x34,0xE0,
+
+	0xB4,0x64,0x22,0x90,0x43,0x33,0xE0,0xD3,
+
+	0x94,0x05,0x40,0x11,0x90,0x43,0x32,0xE0,
+
+	0xD3,0x94,0x05,0x40,0x08,0x90,0x42,0xFD,
+
+	0x74,0x01,0xF0,0x80,0x05,0xE4,0x90,0x42,
+
+	0xFD,0xF0,0x12,0xAF,0x36,0x90,0x43,0x34,
+
+	0xE0,0x04,0xF0,0x12,0x97,0x59,0x22,0x90,
+
+	0x43,0xAF,0xE0,0x60,0x23,0x12,0xA9,0x15,
+
+	0x90,0x43,0xA6,0xE0,0x54,0x0F,0x64,0x0F,
+
+	0x70,0x1E,0x90,0x42,0x04,0xE0,0x54,0x0F,
+
+	0x70,0x16,0x90,0x43,0xA9,0xE0,0x70,0x10,
+
+	0x90,0x43,0xA7,0xE0,0x44,0x01,0xF0,0x22,
+
+	0x90,0x42,0x04,0xE0,0xFF,0x12,0xAE,0xEE,
+
+	0x22,0x90,0x43,0xAF,0xE0,0x60,0x23,0x12,
+
+	0xA9,0x46,0x90,0x43,0xA6,0xE0,0x54,0x0F,
+
+	0x70,0x20,0x90,0x42,0x04,0xE0,0x54,0x0F,
+
+	0xFF,0xBF,0x0F,0x16,0x90,0x43,0xA9,0xE0,
+
+	0x70,0x10,0x90,0x43,0xA7,0xE0,0x44,0x02,
+
+	0xF0,0x22,0x90,0x42,0x04,0xE0,0xFF,0x12,
+
+	0xAE,0xEE,0x22,0x90,0x41,0xD1,0xE0,0x70,
+
+	0x04,0xFF,0x12,0xAD,0x78,0x12,0x67,0x07,
+
+	0x7F,0x01,0x12,0xAD,0x78,0x90,0xF6,0x24,
+
+	0xE0,0xD3,0x94,0x04,0x40,0x0F,0xE4,0x90,
+
+	0x41,0xD8,0xF0,0x90,0xF2,0x1C,0xF0,0x90,
+
+	0x43,0xBB,0x04,0xF0,0x22,0x90,0x43,0xBB,
+
+	0x74,0x01,0xF0,0x22,0x90,0x42,0x4A,0xE0,
+
+	0xFF,0x90,0xF5,0xA9,0xE0,0x5F,0x60,0x0E,
+
+	0x90,0xF0,0x68,0xE0,0x20,0xE0,0xF9,0x90,
+
+	0xF0,0x68,0xE0,0x30,0xE0,0xF9,0x90,0x42,
+
+	0x07,0xE0,0xFF,0x90,0xF0,0x58,0xF0,0xEF,
+
+	0xF0,0x90,0x42,0x09,0xE0,0xFF,0x90,0xF0,
+
+	0x58,0xF0,0xEF,0xF0,0x22,0x90,0x42,0x4A,
+
+	0xE0,0xFF,0x90,0xF5,0xA9,0xE0,0x5F,0x60,
+
+	0x0E,0x90,0xF0,0x68,0xE0,0x20,0xE0,0xF9,
+
+	0x90,0xF0,0x68,0xE0,0x30,0xE0,0xF9,0x90,
+
+	0x42,0x08,0xE0,0xFF,0x90,0xF0,0x58,0xF0,
+
+	0xEF,0xF0,0x90,0x42,0x09,0xE0,0xFF,0x90,
+
+	0xF0,0x58,0xF0,0xEF,0xF0,0x22,0x90,0x42,
+
+	0x53,0xE0,0x60,0x2A,0x7F,0x02,0x12,0xAD,
+
+	0x3C,0xE4,0x90,0x41,0xE3,0xF0,0x90,0x41,
+
+	0xD4,0xF0,0x90,0x42,0x04,0xE0,0xC3,0x94,
+
+	0x1A,0x50,0x04,0xE4,0xF0,0x80,0x07,0x90,
+
+	0x42,0x04,0xE0,0x24,0xE6,0xF0,0x90,0x42,
+
+	0x04,0xE0,0xFF,0x12,0xAB,0x9E,0x22,0x90,
+
+	0x44,0x4F,0xE0,0x90,0xF0,0x1B,0xF0,0x90,
+
+	0x44,0x4E,0xE0,0xFF,0x33,0x95,0xE0,0x90,
+
+	0xF0,0x1C,0xEF,0xF0,0x90,0x44,0x4B,0xE0,
+
+	0x90,0xF0,0x0E,0xF0,0x90,0x44,0x4A,0xE0,
+
+	0xFF,0x33,0x95,0xE0,0x90,0xF0,0x0F,0xEF,
+
+	0xF0,0x90,0xF0,0x2C,0x74,0x01,0xF0,0x22,
+
+	0x90,0x44,0x42,0xE0,0xFE,0xA3,0xE0,0xA8,
+
+	0x07,0x08,0x80,0x05,0xCE,0xC3,0x13,0xCE,
+
+	0x13,0xD8,0xF9,0xF0,0xEE,0x90,0x44,0x42,
+
+	0xF0,0xE0,0xFE,0xA3,0xE0,0xFF,0x90,0x41,
+
+	0xC0,0xE0,0xFD,0x7C,0x00,0x12,0x4A,0x23,
+
+	0x90,0x44,0x42,0xEE,0xF0,0xA3,0xEF,0xF0,
+
+	0x22,0x90,0x41,0xB3,0xE0,0xFE,0x90,0x41,
+
+	0xB2,0xE0,0x7C,0x00,0x24,0x00,0xFF,0xEC,
+
+	0x3E,0xFE,0xE4,0xFD,0x90,0x43,0xE6,0xE0,
+
+	0xF8,0xA3,0xE0,0xF9,0xA3,0xE0,0xFA,0xA3,
+
+	0xE0,0xFB,0x12,0x4A,0xAE,0x78,0x09,0x12,
+
+	0x4B,0x32,0x90,0x43,0xEA,0x12,0x4B,0x6C,
+
+	0x22,0x90,0x42,0x17,0xE0,0x90,0xF0,0x0E,
+
+	0xF0,0x90,0x42,0x18,0xE0,0x90,0xF0,0x0F,
+
+	0xF0,0x90,0x42,0x19,0xE0,0x90,0xF0,0x1B,
+
+	0xF0,0x90,0x42,0x1A,0xE0,0x90,0xF0,0x1C,
+
+	0xF0,0x90,0xF0,0x2C,0x74,0x01,0xF0,0x90,
+
+	0xF1,0xE5,0xF0,0xE4,0x90,0x44,0x46,0xF0,
+
+	0x22,0x12,0x9C,0xB3,0x90,0xF1,0x4E,0x74,
+
+	0x3F,0xF0,0x90,0xF1,0x85,0xE4,0xF0,0x90,
+
+	0xF1,0x47,0xF0,0xA3,0xF0,0x90,0x42,0x0D,
+
+	0xE0,0x64,0x01,0x60,0x08,0xE4,0x90,0x43,
+
+	0xE0,0xF0,0x12,0x7E,0x10,0x90,0x43,0xE0,
+
+	0x74,0x01,0xF0,0x90,0x43,0xBB,0xF0,0x22,
+
+	0xC2,0xAF,0x90,0xF7,0x14,0xE0,0x70,0x24,
+
+	0x90,0xF7,0x32,0xE0,0x70,0x06,0x90,0xF7,
+
+	0x3C,0xE0,0x60,0x18,0x90,0xF9,0x9D,0xE4,
+
+	0xF0,0x90,0xF7,0x14,0x04,0xF0,0x90,0xF7,
+
+	0x0D,0xF0,0x90,0xF7,0x86,0xF0,0xA3,0xF0,
+
+	0x90,0xF7,0x11,0xF0,0xD2,0xAF,0x22,0x90,
+
+	0xFB,0x27,0xE0,0x54,0x1F,0xFF,0xC3,0x13,
+
+	0xFF,0x90,0x41,0xD6,0x74,0x01,0xF0,0x90,
+
+	0x44,0x47,0x74,0x82,0xF0,0x12,0xAF,0x1A,
+
+	0x90,0xFB,0x25,0x74,0x1F,0xF0,0xA3,0x74,
+
+	0x22,0xF0,0x90,0xFB,0x29,0x74,0x42,0xF0,
+
+	0x12,0x9D,0x31,0x22,0xC2,0x8C,0x43,0x8E,
+
+	0x08,0xE4,0x90,0x44,0xA6,0xF0,0xA3,0xF0,
+
+	0x90,0x44,0xA8,0xF0,0xA3,0xF0,0xD2,0xAD,
+
+	0xF5,0xC9,0xC2,0xC9,0xC2,0xCD,0xC2,0xCC,
+
+	0xC2,0xC8,0xC2,0xCE,0xC2,0xCB,0x75,0xCA,
+
+	0xAA,0x75,0xCB,0xF2,0xD2,0xCA,0x22,0x90,
+
+	0x43,0xAF,0xE0,0x90,0x44,0xD1,0xF0,0x90,
+
+	0x42,0x53,0xE0,0x60,0x1C,0x90,0x41,0xE3,
+
+	0x74,0x01,0xF0,0xFF,0x12,0xAD,0x3C,0x90,
+
+	0x41,0xD4,0x74,0x01,0xF0,0x90,0x42,0x04,
+
+	0xE0,0x24,0x1A,0xF0,0xE0,0xFF,0x12,0xAB,
+
+	0x9E,0x22,0x90,0x41,0xE8,0xE0,0x70,0x23,
+
+	0x90,0x43,0x90,0xE0,0xA3,0xF0,0x60,0x05,
+
+	0x12,0xAB,0x20,0x80,0x03,0x12,0xA9,0x77,
+
+	0x90,0x41,0xF9,0xE0,0xFF,0x90,0xF0,0x1F,
+
+	0xF0,0x90,0xF0,0x29,0xEF,0xF0,0xE4,0x90,
+
+	0x43,0x90,0xF0,0x22,0x90,0xF7,0x79,0x74,
+
+	0x01,0xF0,0xA3,0xF0,0xA3,0xF0,0xA3,0xF0,
+
+	0x90,0xF7,0x6A,0xF0,0x90,0xF7,0x74,0xF0,
+
+	0x90,0xF0,0x09,0xF0,0x90,0xF7,0x7D,0xF0,
+
+	0x90,0xF5,0xB9,0xF0,0x90,0xF5,0xBE,0xF0,
+
+	0x90,0xF5,0xC0,0xF0,0x22,0x90,0x44,0xD0,
+
+	0xEF,0xF0,0x90,0x41,0xD7,0xE0,0xB4,0x22,
+
+	0x1C,0xC2,0xAF,0x7F,0x15,0x12,0xAD,0x3C,
+
+	0x90,0x44,0xD0,0xE0,0xFF,0x12,0xAE,0xEE,
+
+	0x90,0x43,0xAF,0xE0,0x60,0x05,0x7F,0x14,
+
+	0x12,0xAD,0x3C,0xD2,0xAF,0x22,0x90,0xF7,
+
+	0x3C,0xE0,0x70,0x03,0x12,0xAE,0x16,0xE4,
+
+	0x90,0x44,0x9A,0xF0,0x90,0x42,0x42,0xF0,
+
+	0x90,0x42,0x43,0xF0,0x12,0xAD,0xCE,0xE4,
+
+	0x90,0x41,0xCE,0xF0,0x90,0x41,0xCD,0xF0,
+
+	0x12,0xAE,0xDF,0x22,0xAB,0x07,0x90,0xF1,
+
+	0x1D,0x74,0x01,0xF0,0xE4,0xF0,0xED,0x90,
+
+	0xF1,0x18,0xF0,0xEC,0xA3,0xF0,0x90,0xF1,
+
+	0x1B,0xEB,0xF0,0xD2,0xAF,0xD2,0xE8,0x90,
+
+	0x44,0xAA,0x74,0x01,0xF0,0x90,0xF1,0x1A,
+
+	0xF0,0x22,0xC2,0xA9,0xEF,0x42,0x89,0xEA,
+
+	0xF4,0xF5,0x8C,0xEB,0xF4,0xF5,0x8A,0x53,
+
+	0x8E,0xF7,0xAF,0x05,0xEF,0x33,0x33,0x33,
+
+	0x54,0xF8,0x42,0x8E,0xD2,0x8C,0x30,0x8D,
+
+	0xFD,0xC2,0x8D,0xD2,0xA9,0x22,0x90,0x41,
+
+	0xF1,0xE0,0x70,0x10,0x90,0x43,0xB1,0xF0,
+
+	0xA3,0xF0,0x90,0x43,0xB4,0xF0,0xA3,0xF0,
+
+	0x90,0x43,0xB3,0xF0,0x90,0x42,0x52,0xE0,
+
+	0x60,0x07,0xE4,0x90,0x43,0xA2,0xF0,0xA3,
+
+	0xF0,0x22,0x90,0x43,0x24,0xE0,0x90,0xF5,
+
+	0xCC,0xF0,0x90,0x43,0x23,0xE0,0x54,0x1F,
+
+	0x90,0xF5,0xCD,0xF0,0x90,0xF5,0xD4,0xE0,
+
+	0x90,0x43,0x09,0xF0,0x90,0xF5,0xCB,0xE0,
+
+	0xB4,0x01,0xF9,0x22,0xE4,0xFF,0xFE,0xC3,
+
+	0xEF,0x94,0xFF,0xEE,0x64,0x80,0x94,0x7F,
+
+	0x50,0x13,0x74,0x58,0x2F,0xF5,0x82,0x74,
+
+	0xF7,0x3E,0xF5,0x83,0xE4,0xF0,0x0F,0xBF,
+
+	0x00,0x01,0x0E,0x80,0xE2,0x22,0x90,0xFB,
+
+	0x87,0xE0,0x60,0xFA,0x90,0xFB,0x9E,0xE0,
+
+	0xB4,0x04,0x05,0xA3,0xE0,0xFF,0x80,0x02,
+
+	0x7F,0x00,0x90,0x44,0x72,0xEF,0xF0,0x90,
+
+	0xFB,0x87,0xE4,0xF0,0xC2,0xDB,0x22,0xEF,
+
+	0x24,0x04,0x90,0xFE,0x00,0xF0,0x90,0xFE,
+
+	0x03,0xE0,0x90,0xFE,0x01,0xF0,0xA3,0xED,
+
+	0xF0,0xEF,0x24,0x05,0x90,0xFB,0x90,0xF0,
+
+	0xA3,0xE4,0xF0,0xA3,0xF0,0x22,0xD2,0xAF,
+
+	0xD2,0xA9,0xEF,0x42,0x89,0xEA,0xF4,0xF5,
+
+	0x8C,0xEB,0xF4,0xF5,0x8A,0x53,0x8E,0xF7,
+
+	0xAF,0x05,0xEF,0x33,0x33,0x33,0x54,0xF8,
+
+	0x42,0x8E,0xD2,0x8C,0x22,0x90,0x42,0x0B,
+
+	0xE0,0xFF,0x90,0x42,0x04,0xE0,0xC3,0x9F,
+
+	0x50,0x11,0xE0,0x04,0xF0,0x90,0x41,0xD7,
+
+	0xE0,0xB4,0x22,0x04,0x12,0xA8,0x80,0x22,
+
+	0x12,0xA9,0x15,0x22,0x90,0xF0,0x2B,0xE0,
+
+	0x70,0x0E,0x90,0x43,0xBC,0xF0,0x90,0xFD,
+
+	0x74,0xF0,0x90,0xF1,0xE9,0x04,0xF0,0x22,
+
+	0x90,0xF1,0xE9,0xE4,0xF0,0x90,0xFD,0x74,
+
+	0x04,0xF0,0x22,0x90,0xFB,0x88,0xE0,0x64,
+
+	0x01,0x60,0xF8,0x90,0xFB,0x96,0xEF,0xF0,
+
+	0x90,0xFB,0x88,0x74,0x01,0xF0,0x90,0xFB,
+
+	0x88,0xE0,0x64,0x01,0x60,0xF8,0x7F,0x01,
+
+	0x22,0xE4,0x90,0x43,0x06,0xF0,0x90,0xF5,
+
+	0xD6,0xE0,0x90,0x43,0x07,0xF0,0x90,0xF5,
+
+	0xD5,0xE0,0x90,0x43,0x08,0xF0,0x90,0xF5,
+
+	0xD4,0xE0,0x90,0x43,0x09,0xF0,0x22,0x90,
+
+	0xF4,0x71,0xE4,0xF0,0x04,0xF0,0x90,0xF5,
+
+	0xAC,0xE4,0xF0,0xEF,0x70,0x05,0x12,0x5D,
+
+	0x01,0x80,0x03,0x12,0x6B,0x1B,0x90,0xF4,
+
+	0x71,0xE4,0xF0,0x22,0xE4,0xF5,0x13,0xC2,
+
+	0xAF,0x53,0x91,0x7F,0x7A,0xAF,0x79,0xA0,
+
+	0x12,0x4B,0xA9,0x7B,0x01,0x7A,0x44,0x79,
+
+	0x6A,0x7D,0x01,0x7C,0x00,0x12,0xA1,0x83,
+
+	0x22,0x90,0xF7,0x11,0xE4,0xF0,0x7F,0xFF,
+
+	0x7E,0x66,0x12,0xAF,0x5E,0x20,0x8C,0xFD,
+
+	0x90,0x44,0x9B,0x74,0x01,0xF0,0xD2,0xEA,
+
+	0x90,0xF7,0x11,0xF0,0x22,0x90,0x42,0x42,
+
+	0xE0,0x70,0x0C,0x90,0x42,0x43,0xE0,0x60,
+
+	0x0A,0x90,0x44,0x9A,0xE0,0x60,0x04,0x12,
+
+	0xAA,0x99,0x22,0x12,0xA7,0x4B,0x22,0x90,
+
+	0x42,0x04,0xE0,0x60,0x10,0x14,0xF0,0x90,
+
+	0x41,0xD7,0xE0,0xB4,0x22,0x04,0x12,0xA8,
+
+	0xB2,0x22,0x12,0xA9,0x46,0x22,0x90,0x43,
+
+	0x8F,0xE0,0x60,0x03,0x14,0xF0,0x22,0x90,
+
+	0xF0,0x01,0xE0,0xB4,0x01,0x06,0x12,0x83,
+
+	0x14,0x12,0x93,0x50,0x22,0xC2,0xAF,0x90,
+
+	0xF5,0xA8,0xE4,0xF0,0x90,0xF7,0x3D,0xF0,
+
+	0xFF,0x7E,0x28,0x12,0xAF,0x5E,0x20,0x8C,
+
+	0xFD,0xD2,0xAF,0x22,0xC2,0xAF,0xC2,0xDB,
+
+	0x90,0xFB,0x7F,0xE0,0x70,0x09,0x90,0xFB,
+
+	0x87,0xF0,0x90,0xFB,0xAF,0x04,0xF0,0xD2,
+
+	0xAF,0x22,0x90,0xF5,0x38,0xE0,0xFD,0xEF,
+
+	0x60,0x0D,0x90,0xF5,0x38,0xE0,0xFE,0x6D,
+
+	0x60,0xF5,0xAD,0x06,0x1F,0x80,0xF0,0x22,
+
+	0x90,0x41,0xD7,0xE0,0xB4,0x27,0x0B,0x7F,
+
+	0x16,0x12,0xAD,0x3C,0x90,0x43,0xB0,0x74,
+
+	0x01,0xF0,0x22,0x90,0x43,0xB6,0xE0,0x70,
+
+	0x05,0x90,0x43,0xBB,0xF0,0x22,0x90,0x43,
+
+	0xBB,0x74,0x01,0xF0,0x22,0x90,0xF5,0x5B,
+
+	0x74,0xFC,0xF0,0xA3,0xE4,0xF0,0xA3,0x74,
+
+	0x02,0xF0,0xA3,0xE4,0xF0,0x22,0x90,0xF5,
+
+	0x52,0x74,0x3F,0xF0,0x90,0xF5,0x54,0x74,
+
+	0x01,0xF0,0x90,0xF7,0x0E,0xF0,0x22,0x90,
+
+	0xF4,0x08,0x74,0x99,0xF0,0xA3,0x74,0x02,
+
+	0xF0,0xA3,0xE4,0xF0,0xA3,0xF0,0x22,0x90,
+
+	0xF4,0x08,0x74,0x99,0xF0,0xA3,0x74,0x02,
+
+	0xF0,0xA3,0xE4,0xF0,0xA3,0xF0,0x22,0x90,
+
+	0xF4,0x08,0x74,0x99,0xF0,0xA3,0x74,0x02,
+
+	0xF0,0xA3,0xE4,0xF0,0xA3,0xF0,0x22,0x90,
+
+	0xF5,0x5B,0xE4,0xF0,0xA3,0x74,0x03,0xF0,
+
+	0xA3,0xE4,0xF0,0xA3,0xF0,0x22,0xE4,0x90,
+
+	0x42,0x2B,0xF0,0x90,0xF7,0x83,0x74,0xAA,
+
+	0xF0,0xA3,0xE4,0xF0,0x22,0xC2,0xAF,0x90,
+
+	0xFB,0x97,0xEF,0xF0,0x7F,0x13,0x12,0xAD,
+
+	0x3C,0xD2,0xAF,0x22,0xE4,0x90,0x43,0x27,
+
+	0xF0,0x90,0x43,0x25,0xF0,0xA3,0xF0,0x12,
+
+	0x8E,0x1F,0x22,0x90,0xF5,0x5B,0x74,0x60,
+
+	0xF0,0xA3,0xE4,0xF0,0xA3,0xF0,0xA3,0xF0,
+
+	0x22,0x90,0xFB,0x24,0xE4,0xF0,0x90,0x44,
+
+	0x47,0xE0,0x90,0xFB,0x28,0xF0,0x22,0xE4,
+
+	0x90,0x43,0xA7,0xF0,0x90,0x43,0xA9,0xF0,
+
+	0x90,0x43,0xA8,0xF0,0x22,0xE4,0x90,0x43,
+
+	0x34,0xF0,0x90,0x43,0x33,0xF0,0x90,0x43,
+
+	0x32,0xF0,0x22,0xE4,0x90,0x44,0xAA,0xF0,
+
+	0x90,0xF1,0x1C,0xF0,0x53,0x91,0xEF,0x22,
+
+	0x90,0xFB,0x24,0x74,0x08,0xF0,0x90,0xFB,
+
+	0x28,0x74,0x74,0xF0,0x22,0xAB,0x07,0xAA,
+
+	0x06,0xE4,0xFD,0x7F,0x01,0x12,0xAC,0xDF,
+
+	0x22,0x90,0xF1,0x75,0x74,0x01,0xF0,0x90,
+
+	0xF1,0x0A,0xF0,0x22,0x90,0xF4,0x60,0xEF,
+
+	0xF0,0xA3,0xED,0xF0,0x22,0x90,0xF4,0x13,
+
+	0xE4,0xF0,0x12,0x50,0xDE,0x22,0x90,0x43,
+
+	0xBB,0x74,0x01,0xF0,0xF5,0x13,0x22,0x90,
+
+	0xF2,0x17,0x74,0xFE,0xF0,0x22,0xC2,0xAF,
+
+	0x12,0xA6,0xD7,0x22,0xC2,0x8C,0x22,0x22,
+
+	0x22,0x22,0x22,0x22,0x22,0x22,0x01,0x02,
+
+	0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x09,
+
+	0x00,0x01,0x02,0x03,0x04,0x05,0x05,0x03,
+
+	0x08,0x01,0x00,0x01,0x01,0x02,0x03,0x03,
+
+	0x01,0x01,0x01,0x01,0x3E,0x80,0x06,0x40,
+
+	0x7D,0x00,0x12,0xC0,0x12,0xC0,0xFA,0x00,
+
+	0x12,0xC0,0xBB,0x80,0x9C,0x40,0x00,0xA0,
+
+	0x00,0x00,0x01,0x02,0x02,0x02,0x02,0x02,
+
+	0x01,0x01,0xA7,0x12,0xAF,0x9D,0xAF,0xA1,
+
+	0xAF,0xA2,0xAF,0xA3,0x71,0xC9,0xAF,0xA4,
+
+	0xAF,0xA5,0xAF,0x44,0xA2,0x69,0x84,0xEF,
+
+	0x8C,0x89,0xAE,0x2D
+
+};
+
+
+
+static Segment Firmware_segments[] = {
+
+	{	0x00,		0x0000000A		},
+
+	{	0x00,		0x00003A0E		},
+
+	{	0x00,		0x0000000A		},
+
+	{	0x00,		0x00006AB4		}
+
+};
+
+
+
+static Byte Firmware_partitions[] = {
+
+	0x04
+
+};
+
+
+
+
+
+#define Firmware_SCRIPTSETLENGTH	0x00000001
+
+
+
+
+
+static Word Firmware_scriptSets[] = {
+
+	0x6B
+
+};
+
+
+
+
+
+static ValueSet Firmware_scripts[] = {
+
+ {0xF905, 0x01},
+
+ {0xF40E, 0x0A},
+
+ {0xF40F, 0x40},
+
+ {0xF410, 0x08},
+
+ {0xF55F, 0x0A},
+
+ {0xF562, 0x20},
+
+ {0xF561, 0x15},
+
+ {0xF610, 0x32},
+
+ {0xF611, 0x10},
+
+ {0xF60F, 0x04},
+
+ {0xF60E, 0x00},
+
+ {0xF600, 0x05},
+
+ {0xF601, 0x08},
+
+ {0xF602, 0x0B},
+
+ {0xF603, 0x0E},
+
+ {0xF604, 0x11},
+
+ {0xF605, 0x14},
+
+ {0xF606, 0x17},
+
+ {0xF607, 0x1F},
+
+ {0xF5F8, 0x01},
+
+ {0xF5DF, 0xFB},
+
+ {0xF5E0, 0x00},
+
+ {0xF5E3, 0x09},
+
+ {0xF5E4, 0x01},
+
+ {0xF5E5, 0x01},
+
+ {0xF5FD, 0x01},
+
+ {0xF80F, 0x40},
+
+ {0xF810, 0x54},
+
+ {0xF811, 0x5a},
+
+ {0xF78B, 0x01},
+
+ {0xFB06, 0x3},
+
+ {0x00a0, 0xCF},
+
+ {0x009f, 0xE1},
+
+ {0x00a6, 0x01},
+
+ {0xFD8B, 0x00},
+
+ {0x00ad, 0x01},
+
+ {0x00a3, 0x01},
+
+ {0x00a4, 0x3C},
+
+ {0x00ab, 0x01},
+
+ {0x008e, 0x01},
+
+ {0x008a, 0x01},
+
+ {0x0099, 0x01},
+
+ {0x00a9, 0x00},
+
+ {0x00a5, 0x01},
+
+ {0x00aa, 0x01},
+
+ {0x0092, 0x06},
+
+ {0xF078, 0x00},
+
+ {0xF016, 0x10},
+
+ {0xF017, 0x04},
+
+ {0xF018, 0x05},
+
+ {0xF019, 0x04},
+
+ {0xF01A, 0x05},
+
+ {0xF021, 0x03},
+
+ {0xF022, 0x0A},
+
+ {0xF023, 0x0A},
+
+ {0xF02B, 0x00},
+
+ {0x0070, 0x0A},
+
+ {0xF1CB, 0xA0},
+
+ {0xF1CC, 0x01},
+
+ {0xF02C, 0x01},
+
+ {0x00b0, 0x01},
+
+ {0xF000, 0xF},
+
+ {0xF707, 0xFC},
+
+ {0xF708, 0x00},
+
+ {0xF709, 0x7E},
+
+ {0xF70A, 0x00},
+
+ {0xF70B, 0x2F},
+
+ {0xF1BC, 0x36},
+
+ {0xF1BD, 0x00},
+
+ {0xF214, 0x0},
+
+ {0xF204, 0x10},
+
+ {0xF087, 0x0},
+
+ {0xF064, 0x03},
+
+ {0xF067, 0x1},
+
+ {0xF065, 0xF9},
+
+ {0xF066, 0x03},
+
+ {0xF06F, 0xe0},
+
+ {0xF070, 0x3},
+
+ {0xF072, 0x0f},
+
+ {0xF073, 0x03},
+
+ {0xF144, 0x1a},
+
+ {0xF146, 0x00},
+
+ {0xF14A, 0x01},
+
+ {0xF14C, 0x00},
+
+ {0xF14D, 0x00},
+
+ {0xF14F, 0x04},
+
+ {0xF09F, 0x0c},
+
+ {0xF0A0, 0x00},
+
+ {0xF15A, 0x00},
+
+ {0xF15B, 0x08},
+
+ {0xF163, 0x05},
+
+ {0xF09B, 0x3f},
+
+ {0xF09C, 0x00},
+
+ {0xF168, 0x0f},
+
+ {0xF09D, 0x20},
+
+ {0xF09E, 0x00},
+
+ {0xF167, 0x40},
+
+ {0xF158, 0x7f},
+
+ {0xF166, 0x01},
+
+ {0xF15D, 0x03},
+
+ {0xF130, 0x04},
+
+ {0xF132, 0x04},
+
+ {0xF183, 0x01},
+
+ {0xF19D, 0x40},
+
+ {0xF15E, 0x05},
+
+ {0xF17A, 0x00},
+
+ {0xF17B, 0x00},
+
+};
+
+#endif
+
+// Warning: version numbers are manually altered.
+
diff --git a/drivers/media/dvb/dvb-usb/a867_inttype.h b/drivers/media/dvb/dvb-usb/a867_inttype.h
new file mode 100644
index 0000000..303ae70
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_inttype.h
@@ -0,0 +1,41 @@
+#ifndef __INTTYPE_H__
+#define __INTTYPE_H__
+
+
+/**
+ * The type defination of SnrTable.
+ */
+typedef struct {
+    Dword errorCount;
+    Dword snr;
+    double errorRate;
+} SnrTable;
+
+
+/**
+ * The type defination of Statistic.
+ */
+typedef struct {
+    Word abortCount;
+    Dword postVitBitCount;
+    Dword postVitErrorCount;
+    /** float point */
+    Dword softBitCount;
+    Dword softErrorCount;
+    Dword preVitBitCount;
+    Dword preVitErrorCount;
+    double snr;
+} ChannelStatistic;
+
+
+/**
+ * The type defination of AgcVoltage.
+ */
+typedef struct {
+    double doSetVolt;
+    double doPuUpVolt;
+} AgcVoltage;
+
+
+#endif
+
diff --git a/drivers/media/dvb/dvb-usb/a867_iocontrol.h b/drivers/media/dvb/dvb-usb/a867_iocontrol.h
new file mode 100644
index 0000000..a38a1e5
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_iocontrol.h
@@ -0,0 +1,738 @@
+/**
+ *
+ * Copyright (c) 2006 Afa Corporation. All rights reserved.
+ *
+ * Module Name:
+ *   iocontrol.h
+ *
+ * Abstract:
+ *   The structure and IO code for IO control call.
+ *
+ */
+
+#ifndef __IOCONTROL_H__
+#define __IOCONTROL_H__
+
+#ifdef UNDER_CE
+#include <winioctl.h>
+#else
+#endif
+
+#include "a867_type.h"
+
+#define MEDIA_DEVICE_AFADEMOD       0x00000AFA
+
+typedef struct {
+    Byte                chipNumber;
+    Word                sawBandwidth;
+    StreamType          streamType;
+    Architecture        architecture;
+    Dword               error;
+    Byte                reserved[16];
+} InitializeRequest, *PInitializeRequest;
+
+typedef struct {
+    Dword               error;
+    Byte                reserved[16];
+} FinalizeRequest, *PFinalizeRequest;
+
+typedef struct {
+    StreamType          streamType;
+    Dword               error;
+    Byte                reserved[16];
+} SetStreamTypeRequest, *PSetStreamTypeRequest;
+
+typedef struct {
+    Architecture        architecture;
+    Dword               error;
+    Byte                reserved[16];
+} SetArchitectureRequest, *PSetArchitectureRequest;
+
+typedef struct {
+    Byte                chip;
+    ChannelModulation*  channelModulation;
+    Dword               error;
+    Byte                reserved[16];
+} GetChannelModulationRequest, *PGetChannelModulationRequest;
+
+typedef struct {
+    Processor           processor;
+    Dword*              version;
+    Dword               error;
+    Byte                reserved[16];
+} GetFirmwareVersionRequest, *PGetFirmwareVersionRequest;
+
+typedef struct {
+    Byte                chip;
+    Word                bandwidth;
+    Dword               frequency;
+    Dword               error;
+    Byte                reserved[16];
+} AcquireChannelRequest, *PAcquireChannelRequest;
+
+typedef struct {
+    Byte                chip;
+    Bool*               locked;
+    Dword               error;
+    Byte                reserved[16];
+} IsLockedRequest, *PIsLockedRequest;
+
+typedef struct {
+    Byte                chip;
+    Pid                 pid;
+    Dword               error;
+    Byte                reserved[16];
+} AddPidRequest, *PAddPidRequest;
+
+typedef struct {
+    Byte                chip;
+    Pid                 pid;
+    Dword               error;
+    Byte                reserved[16];
+} RemovePidRequest, *PRemovePidRequest;
+
+typedef struct {
+    Byte            chip;
+    Dword           error;
+    Byte            reserved[16];
+} ResetPidRequest, *PResetPidRequest;
+
+typedef struct {
+    Byte                chip;
+    Byte                superFrameCount;
+    Word                packetUnit;
+    Dword               error;
+    Byte                reserved[16];
+} SetStatisticRangeRequest, *PSetStatisticRangeRequest;
+
+typedef struct {
+    Byte                chip;
+    Byte*               superFrameCount;
+    Word*               packetUnit;
+    Dword               error;
+    Byte                reserved[16];
+} GetStatisticRangeRequest, *PGetStatisticRangeRequest;
+
+typedef struct {
+    Byte                chip;
+    ChannelStatistic*   channelStatistic;
+    Dword               error;
+    Byte                reserved[16];
+} GetChannelStatisticRequest, *PGetChannelStatisticRequest;
+
+typedef struct {
+    Byte                chip;
+    Statistic*          statistic;
+    Dword               error;
+    Byte                reserved[16];
+} GetStatisticRequest, *PGetStatisticRequest;
+
+typedef struct {
+    Dword*              bufferLength;
+    Byte*               buffer;
+    Dword               error;
+    Byte                reserved[16];
+} GetDatagramRequest, *PGetDatagramRequest;
+
+typedef struct {
+    Byte            chip;
+    Byte            control;
+    Dword           error;
+    Byte            reserved[16];
+} ControlPidFilterRequest, *PControlPidFilterRequest;
+
+typedef struct {
+    Byte                chip;
+    Byte                control;
+    Dword               error;
+    Byte                reserved[16];
+} ControlPowerSavingRequest, *PControlPowerSavingRequest;
+
+typedef struct {
+    Byte                DriverVerion[16];   /** XX.XX.XX.XX Ex., 1.2.3.4            */
+    Byte                APIVerion[32];      /** XX.XX.XXXXXXXX.XX Ex., 1.2.3.4  */
+    Byte                FWVerionLink[16];   /** XX.XX.XX.XX Ex., 1.2.3.4            */
+    Byte                FWVerionOFDM[16];   /** XX.XX.XX.XX Ex., 1.2.3.4            */
+    Byte                DateTime[24];       /** Ex.,"2004-12-20 18:30:00" or "DEC 20 2004 10:22:10" with compiler __DATE__ and __TIME__  definitions */
+    Byte                Company[8];         /** Ex.,"Afatech"                   */
+    Byte                SupportHWInfo[32];  /** Ex.,"Jupiter DVBT/DVBH"         */
+    Dword               error;
+    Byte                reserved[128];
+} DemodDriverInfo, *PDemodDriverInfo;
+
+typedef struct {
+    Ensemble*           ensemble;
+    Dword               error;
+    Byte                reserved[16];
+} AcquireEnsembleRequest, *PAcquireEnsembleRequest;
+
+typedef struct {
+    Byte*               serviceLength;
+    Service*            services;
+    Dword               error;
+    Byte                reserved[16];
+} AcquireServiceRequest, *PAcquireServiceRequest;
+
+typedef struct {
+    Service             service;
+    Byte*               componentLength;
+    Component*          components;
+    Dword               error;
+    Byte                reserved[16];
+} AcquireComponentRequest, *PAcquireComponentRequest;
+
+typedef struct {
+    Component           component;
+    Dword               error;
+    Byte                reserved[16];
+} AddComponentRequest, *PAddComponentRequest;
+
+typedef struct {
+    Component           component;
+    Dword               error;
+    Byte                reserved[16];
+} RemoveComponentRequest, *PRemoveComponentRequest;
+
+typedef struct {
+    Byte                figType;
+    Byte                figExtension;
+    Dword               error;
+    Byte                reserved[16];
+} AddFigRequest, *PAddFigRequest;
+
+typedef struct {
+    Byte                figType;
+    Byte                figExtension;
+    Dword               error;
+    Byte                reserved[16];
+} RemoveFigRequest, *PRemoveFigRequest;
+
+
+/**
+ * Demodulator API commands
+ */
+
+/**
+ * First, download firmware from host to demodulator. Actually, firmware is
+ * put in firmware.h as a part of source code. Therefore, in order to
+ * update firmware the host have to re-compile the source code.
+ * Second, setting all parameters which will be need at the beginning.
+ * Paramters: None
+ */
+#define IOCTL_AFA_DEMOD_INITIALIZE \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x003, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Set the output stream type of chip. Because the device could output in
+ * many stream type, therefore host have to choose one type before receive
+ * data.
+ * Paramters:   DemodStreamType struct
+ */
+#define IOCTL_AFA_DEMOD_SETSTREAMTYPE \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x004, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Set the output stream type of chip. Because the device could output in
+ * many stream type, therefore host have to choose one type before receive
+ * data.
+ * Paramters:   DemodStreamType struct
+ */
+#define IOCTL_AFA_DEMOD_SETARCHITECTURE \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x006, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Set the output stream type of chip. Because the device could output in
+ * many stream type, therefore host have to choose one type before receive
+ * data.
+ * Paramters:   DemodStreamType struct
+ */
+#define IOCTL_AFA_DEMOD_GETCHANNELMODULATION \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x008, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Set the output stream type of chip. Because the device could output in
+ * many stream type, therefore host have to choose one type before receive
+ * data.
+ * Paramters:   DemodStreamType struct
+ */
+#define IOCTL_AFA_DEMOD_GETFIRMWAREVERSION \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x009, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Specify the bandwidth of channel and tune the channel to the specific
+ * frequency. Afterwards, host could use output parameter dvbH to determine
+ * if there is a DVB-H signal.
+ * In DVB-T mode, after calling this function output parameter dvbH should
+ * be False and host could use output parameter "locked" to indicate if the
+ * TS is correct.
+ * In DVB-H mode, after calling this function output parameter dvbH should
+ * be True and host could use Jupiter_acquirePlatorm to get platform.
+ * Paramters:   DemodAcqCh struct
+ */
+#define IOCTL_AFA_DEMOD_ACQUIRECHANNEL \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x00A, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Get all the platforms found in current frequency.
+ * Paramters:   DemodAcqPlatform struct
+ */
+#define IOCTL_AFA_DEMOD_ISLOCKED \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x00B, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Get all the platforms found in current frequency.
+ * Paramters:   DemodAcqPlatform struct
+ */
+#define IOCTL_AFA_DEMOD_ACQUIREPLATFORM \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x00C, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Change the current platform as the specified platform. If the target
+ * platform is locate in different frequency, this function will tune to
+ * that frequency before setting platform.
+ * Paramters:   DemodSetPlatform struct
+ */
+#define IOCTL_AFA_DEMOD_SETPLATFORM \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x00D, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Add IP to IP filter.
+ * Paramters:   DemodIp struct
+ */
+#define IOCTL_AFA_DEMOD_ADDIP \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x00E, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Remove IP from IP filter.
+ * Paramters:   DemodIp struct
+ */
+#define IOCTL_AFA_DEMOD_REMOVEIP \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x00F, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Add PID to PID filter.
+ * Paramters:   DemodPid struct
+ */
+#define IOCTL_AFA_DEMOD_ADDPID \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x010, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Remove PID from PID filter.
+ * Paramters:   DemodPid struct
+ */
+#define IOCTL_AFA_DEMOD_REMOVEPID \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x011, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Reset PID from PID filter.
+ * Paramters:   ResetPidRequest struct
+ */
+#define IOCTL_AFA_DEMOD_RESETPID \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x012, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Get data of one single section
+ * Paramters:   DemodGetStat struct
+ */
+#define IOCTL_AFA_DEMOD_GETSECTION \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x013, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Get the statistic values of demodulator, it includes Pre-Viterbi BER,
+ * Post-Viterbi BER, Abort Count, Signal Presented Flag, Signal Locked Flag,
+ * Signal Quality, Signal Strength, Delta-T for DVB-H time slicing.
+ * Paramters:   DemodGetStat struct
+ */
+#define IOCTL_AFA_DEMOD_SETSTATISTICRANGE \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x014, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Get the statistic values of demodulator, it includes Pre-Viterbi BER,
+ * Post-Viterbi BER, Abort Count, Signal Presented Flag, Signal Locked Flag,
+ * Signal Quality, Signal Strength, Delta-T for DVB-H time slicing.
+ * Paramters:   DemodGetStat struct
+ */
+#define IOCTL_AFA_DEMOD_GETSTATISTICRANGE \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x015, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Get the statistic values of demodulator, it includes Pre-Viterbi BER,
+ * Post-Viterbi BER, Abort Count, Signal Presented Flag, Signal Locked Flag,
+ * Signal Quality, Signal Strength, Delta-T for DVB-H time slicing.
+ * Paramters:   DemodGetStat struct
+ */
+#define IOCTL_AFA_DEMOD_GETCHANNELSTATISTIC \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x016, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Get the statistic values of demodulator, it includes Pre-Viterbi BER,
+ * Post-Viterbi BER, Abort Count, Signal Presented Flag, Signal Locked Flag,
+ * Signal Quality, Signal Strength, Delta-T for DVB-H time slicing.
+ * Paramters:   DemodGetStat struct
+ */
+#define IOCTL_AFA_DEMOD_GETSTATISTIC \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x017, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Get the statistic values of demodulator, it includes Pre-Viterbi BER,
+ * Post-Viterbi BER, Abort Count, Signal Presented Flag, Signal Locked Flag,
+ * Signal Quality, Signal Strength, Delta-T for DVB-H time slicing.
+ * Paramters:   DemodGetStat struct
+ */
+#define IOCTL_AFA_DEMOD_GETINTERRUPTS \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x018, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Get the statistic values of demodulator, it includes Pre-Viterbi BER,
+ * Post-Viterbi BER, Abort Count, Signal Presented Flag, Signal Locked Flag,
+ * Signal Quality, Signal Strength, Delta-T for DVB-H time slicing.
+ * Paramters:   DemodGetStat struct
+ */
+#define IOCTL_AFA_DEMOD_CLEARINTERRUPT \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x019, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Get the statistic values of demodulator, it includes Pre-Viterbi BER,
+ * Post-Viterbi BER, Abort Count, Signal Presented Flag, Signal Locked Flag,
+ * Signal Quality, Signal Strength, Delta-T for DVB-H time slicing.
+ * Paramters:   DemodGetStat struct
+ */
+#define IOCTL_AFA_DEMOD_GETDATAGRAM \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x01A, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ *
+ * Paramters:   DemodControl struct
+ */
+#define IOCTL_AFA_DEMOD_GETDELTAT \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x01B, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Enable PID filter.
+ * Paramters:   EnablePidRequest struct
+ */
+#define IOCTL_AFA_DEMOD_CONTROLPIDFILTER \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x01C, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ *
+ * Paramters:   DemodControl struct
+ */
+#define IOCTL_AFA_DEMOD_CONTROLTIMESLICING \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x01D, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ *
+ * Paramters:   DemodControl struct
+ */
+#define IOCTL_AFA_DEMOD_CONTROLPOWERSAVING \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x01E, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Power off the demodulators.
+ * Paramters:   None
+ */
+#define IOCTL_AFA_DEMOD_FINALIZE \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x01F, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Get driver information.
+ * Paramters:   DemodDriverInfo struct
+ */
+#define IOCTL_AFA_DEMOD_GETDRIVERINFO \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x020, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Get ensemble.
+ * Paramters:   DemodDriverInfo struct
+ */
+#define IOCTL_AFA_DEMOD_ACQUIREENSEMBLE \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x021, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Get service.
+ * Paramters:   DemodDriverInfo struct
+ */
+#define IOCTL_AFA_DEMOD_ACQUIRESERVICE \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x022, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Get component.
+ * Paramters:   DemodDriverInfo struct
+ */
+#define IOCTL_AFA_DEMOD_ACQUIRECOMPONENT \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x023, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Add component.
+ * Paramters:   DemodDriverInfo struct
+ */
+#define IOCTL_AFA_DEMOD_ADDCOMPONENT \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x024, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Remove component.
+ * Paramters:   DemodDriverInfo struct
+ */
+#define IOCTL_AFA_DEMOD_REMOVECOMPONENT \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x025, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Add FIG.
+ * Paramters:   DemodDriverInfo struct
+ */
+#define IOCTL_AFA_DEMOD_ADDFIG \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x026, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Remove FIG.
+ * Paramters:   DemodDriverInfo struct
+ */
+#define IOCTL_AFA_DEMOD_REMOVEFIG \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x027, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+
+/**
+ * Demodulator Misc API commands
+ */
+
+typedef struct {
+    Byte            chip;
+    Processor       processor;
+    Dword           registerAddress;
+    Byte            bufferLength;
+    Byte            buffer[256];
+    Dword           error;
+    Byte            reserved[16];
+} WriteRegistersRequest, *PWriteRegistersRequest;
+
+typedef struct {
+    Byte            chip;
+    Word            registerAddress;
+    Byte            bufferLength;
+    Byte            buffer[256];
+    Dword           error;
+    Byte            reserved[16];
+} WriteTunerRegistersRequest, *PWriteTunerRegistersRequest;
+
+typedef struct {
+    Byte            chip;
+    Word            registerAddress;
+    Byte            bufferLength;
+    Byte            buffer[256];
+    Dword           error;
+    Byte            reserved[16];
+} WriteEepromValuesRequest, *PWriteEepromValuesRequest;
+
+typedef struct {
+    Byte            chip;
+    Processor       processor;
+    Dword           registerAddress;
+    Byte            position;
+    Byte            length;
+    Byte            value;
+    Dword           error;
+    Byte            reserved[16];
+} WriteRegisterBitsRequest, *PWriteRegisterBitsRequest;
+
+typedef struct {
+    Byte            chip;
+    Processor       processor;
+    Word            variableIndex;
+    Byte            bufferLength;
+    Byte            buffer[256];
+    Dword           error;
+    Byte            reserved[16];
+} SetVariablesRequest, *PSetVariablesRequest;
+
+typedef struct {
+    Byte            chip;
+    Processor       processor;
+    Word            variableIndex;
+    Byte            position;
+    Byte            length;
+    Byte            value;
+    Dword           error;
+    Byte            reserved[16];
+} SetVariableBitsRequest, *PSetVariableBitsRequest;
+
+typedef struct {
+    Byte            chip;
+    Processor       processor;
+    Dword           registerAddress;
+    Byte            bufferLength;
+    Byte*           buffer;
+    Dword           error;
+    Byte            reserved[16];
+} ReadRegistersRequest, *PReadRegistersRequest;
+
+typedef struct {
+    Byte            chip;
+    Word            registerAddress;
+    Byte            bufferLength;
+    Byte*           buffer;
+    Dword           error;
+    Byte            reserved[16];
+} ReadTunerRegistersRequest, *PReadTunerRegistersRequest;
+
+typedef struct {
+    Byte            chip;
+    Word            registerAddress;
+    Byte            bufferLength;
+    Byte*           buffer;
+    Dword           error;
+    Byte            reserved[16];
+} ReadEepromValuesRequest, *PReadEepromValuesRequest;
+
+typedef struct {
+    Byte            chip;
+    Processor       processor;
+    Dword           registerAddress;
+    Byte            position;
+    Byte            length;
+    Byte*           value;
+    Dword           error;
+    Byte            reserved[16];
+} ReadRegisterBitsRequest, *PReadRegisterBitsRequest;
+
+typedef struct {
+    Byte            chip;
+    Processor       processor;
+    Word            variableIndex;
+    Byte            bufferLength;
+    Byte*           buffer;
+    Dword           error;
+    Byte            reserved[16];
+} GetVariablesRequest, *PGetVariablesRequest;
+
+typedef struct {
+    Byte            chip;
+    Processor       processor;
+    Word            variableIndex;
+    Byte            position;
+    Byte            length;
+    Byte*           value;
+    Dword           error;
+    Byte            reserved[16];
+} GetVariableBitsRequest, *PGetVariableBitsRequest;
+
+
+/**
+ * Write a sequence of bytes to the contiguous registers in demodulator.
+ * Paramters:   DemodRegs struct
+ */
+#define IOCTL_AFA_DEMOD_WRITEREGISTERS \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x101, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Write a sequence of bytes to the contiguous registers in tuner.
+ * Paramters:   DemodTunerRegs struct
+ */
+#define IOCTL_AFA_DEMOD_WRITETUNERREGISTERS \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x102, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Write a sequence of bytes to the contiguous cells in the EEPROM.
+ * Paramters:   DemodEEPROMVaules struct
+ */
+#define IOCTL_AFA_DEMOD_WRITEEEPROMVALUES \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x103, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Write one byte to the contiguous registers in demodulator.
+ * Paramters:   DemodRegs struct
+ */
+#define IOCTL_AFA_DEMOD_WRITEREGISTERBITS \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x104, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Write a sequence of bytes to the contiguous variables in demodulator.
+ * Paramters:   DemodVariables struct
+ */
+#define IOCTL_AFA_DEMOD_SETVARIABLES \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x105, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Write a sequence of bytes to the contiguous variables in demodulator.
+ * Paramters:   DemodVariables struct
+ */
+#define IOCTL_AFA_DEMOD_SETVARIABLEBITS \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x106, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Read a sequence of bytes from the contiguous registers in demodulator.
+ * Paramters:   DemodRegs struct
+ */
+#define IOCTL_AFA_DEMOD_READREGISTERS \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x108, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Read a sequence of bytes from the contiguous registers in tuner.
+ * Paramters:   DemodTunerRegs
+ */
+#define IOCTL_AFA_DEMOD_READTUNERREGISTERS \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x109, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Read a sequence of bytes from the contiguous cells in the EEPROM.
+ * Paramters:   DemodEEPROMVaules struct
+ */
+#define IOCTL_AFA_DEMOD_READEEPROMVALUES \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x10A, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Read a sequence of bytes from the contiguous registers in demodulator.
+ * Paramters:   DemodRegs struct
+ */
+#define IOCTL_AFA_DEMOD_READREGISTERBITS \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x10B, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Read a sequence of bytes from the contiguous variables in demodulator.
+ * Paramters:   DemodVariables struct
+ */
+#define IOCTL_AFA_DEMOD_GETVARIABLES \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x10C, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+/**
+ * Read a sequence of bytes from the contiguous variables in demodulator.
+ * Paramters:   DemodVariables struct
+ */
+#define IOCTL_AFA_DEMOD_GETVARIABLEBITS \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x10D, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+
+
+/**
+ * Demodulator Stream control API commands
+ */
+
+typedef struct {
+    Byte            chip;
+    Dword           error;
+    Byte            reserved[16];
+} StartCaptureRequest, *PStartCaptureRequest;
+
+typedef struct {
+    Byte            chip;
+    Dword           error;
+    Byte            reserved[16];
+} StopCaptureRequest, *PStopCaptureRequest;
+
+/**
+ * Start capture data stream
+ * Paramters: DemodDriverInfo struct
+ */
+#define IOCTL_AFA_DEMOD_STARTCAPTURE \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x200, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+
+/**
+ * Stop capture data stream
+ * Paramters:   DemodDriverInfo struct
+ */
+#define IOCTL_AFA_DEMOD_STOPCAPTURE \
+    CTL_CODE( MEDIA_DEVICE_AFADEMOD, 0x201, METHOD_BUFFERED, FILE_ANY_ACCESS )
+
+
+#endif
diff --git a/drivers/media/dvb/dvb-usb/a867_mxl5007t.c b/drivers/media/dvb/dvb-usb/a867_mxl5007t.c
new file mode 100644
index 0000000..29b397a
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_mxl5007t.c
@@ -0,0 +1,698 @@
+/*
+ *  mxl5007t.c - driver for the MaxLinear MxL5007T silicon tuner
+ *
+ *  Copyright (C) 2008, 2009 Michael Krufky <mkrufky@linuxtv.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * The code is modified to accommodate the AF903x source code on 2010/6/7
+ */
+
+#include <linux/i2c.h>
+#include <linux/types.h>
+#include <linux/videodev2.h>
+#include <linux/slab.h>
+#include "a867_mxl5007t.h"
+
+/* ------------------------------------------------------------------------- */
+
+#define mxl_printk(kern, fmt, arg...) \
+	printk(kern "%s: " fmt "\n", __func__, ##arg)
+
+#define mxl_err(fmt, arg...) \
+	mxl_printk(KERN_ERR, "%d: " fmt, __LINE__, ##arg)
+
+#define mxl_warn(fmt, arg...) \
+	mxl_printk(KERN_WARNING, fmt, ##arg)
+
+#define mxl_info(fmt, arg...) \
+	mxl_printk(KERN_INFO, fmt, ##arg)
+
+#define mxl_debug(fmt, arg...)				\
+({							\
+	if (1)				\
+		mxl_printk(KERN_DEBUG, fmt, ##arg);	\
+})
+
+#define mxl_fail(ret)							\
+({									\
+	int __ret;							\
+	__ret = (ret < 0);						\
+	if (__ret)							\
+		mxl_printk(KERN_ERR, "error %d on line %d",		\
+			   ret, __LINE__);				\
+	__ret;								\
+})
+
+/* ------------------------------------------------------------------------- */
+
+#define MHz 1000000
+
+
+#include "a867_Maxlinear_MXL5007.h"
+
+
+struct reg_pair_t {
+	u8 reg;
+	u8 val;
+};
+
+/* ------------------------------------------------------------------------- */
+
+static struct reg_pair_t init_tab[] = {
+	{ 0x02, 0x06 },
+	{ 0x03, 0x48 },
+	{ 0x05, 0x04 },
+	{ 0x06, 0x10 },
+	{ 0x2e, 0x15 }, /* OVERRIDE */
+	{ 0x30, 0x10 }, /* OVERRIDE */
+	{ 0x45, 0x58 }, /* OVERRIDE */
+	{ 0x48, 0x19 }, /* OVERRIDE */
+	{ 0x52, 0x03 }, /* OVERRIDE */
+	{ 0x53, 0x44 }, /* OVERRIDE */
+	{ 0x6a, 0x4b }, /* OVERRIDE */
+	{ 0x76, 0x00 }, /* OVERRIDE */
+	{ 0x78, 0x18 }, /* OVERRIDE */
+	{ 0x7a, 0x17 }, /* OVERRIDE */
+	{ 0x85, 0x06 }, /* OVERRIDE */
+	{ 0x01, 0x01 }, /* TOP_MASTER_ENABLE */
+	{ 0, 0 }
+};
+
+static struct reg_pair_t init_tab_cable[] = {
+	{ 0x02, 0x06 },
+	{ 0x03, 0x48 },
+	{ 0x05, 0x04 },
+	{ 0x06, 0x10 },
+	{ 0x09, 0x3f },
+	{ 0x0a, 0x3f },
+	{ 0x0b, 0x3f },
+	{ 0x2e, 0x15 }, /* OVERRIDE */
+	{ 0x30, 0x10 }, /* OVERRIDE */
+	{ 0x45, 0x58 }, /* OVERRIDE */
+	{ 0x48, 0x19 }, /* OVERRIDE */
+	{ 0x52, 0x03 }, /* OVERRIDE */
+	{ 0x53, 0x44 }, /* OVERRIDE */
+	{ 0x6a, 0x4b }, /* OVERRIDE */
+	{ 0x76, 0x00 }, /* OVERRIDE */
+	{ 0x78, 0x18 }, /* OVERRIDE */
+	{ 0x7a, 0x17 }, /* OVERRIDE */
+	{ 0x85, 0x06 }, /* OVERRIDE */
+	{ 0x01, 0x01 }, /* TOP_MASTER_ENABLE */
+	{ 0, 0 }
+};
+
+/* ------------------------------------------------------------------------- */
+
+static struct reg_pair_t reg_pair_rftune[] = {
+	{ 0x0f, 0x00 }, /* abort tune */
+	{ 0x0c, 0x15 },
+	{ 0x0d, 0x40 },
+	{ 0x0e, 0x0e },
+	{ 0x1f, 0x87 }, /* OVERRIDE */
+	{ 0x20, 0x1f }, /* OVERRIDE */
+	{ 0x21, 0x87 }, /* OVERRIDE */
+	{ 0x22, 0x1f }, /* OVERRIDE */
+	{ 0x80, 0x01 }, /* freq dependent */
+	{ 0x0f, 0x01 }, /* start tune */
+	{ 0, 0 }
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+
+/* ------------------------------------------------------------------------- */
+
+/* called by _init and _rftun to manipulate the register arrays */
+
+static void set_reg_bits(struct reg_pair_t *reg_pair, u8 reg, u8 mask, u8 val)
+{
+	unsigned int i = 0;
+
+	while (reg_pair[i].reg || reg_pair[i].val) {
+		if (reg_pair[i].reg == reg) {
+			reg_pair[i].val &= ~mask;
+			reg_pair[i].val |= val;
+		}
+		i++;
+
+	}
+	return;
+}
+
+static void copy_reg_bits(struct reg_pair_t *reg_pair1,
+			  struct reg_pair_t *reg_pair2)
+{
+	unsigned int i, j;
+
+	i = j = 0;
+
+	while (reg_pair1[i].reg || reg_pair1[i].val) {
+		while (reg_pair2[j].reg || reg_pair2[j].val) {
+			if (reg_pair1[i].reg != reg_pair2[j].reg) {
+				j++;
+				continue;
+			}
+			reg_pair2[j].val = reg_pair1[i].val;
+			break;
+		}
+		i++;
+	}
+	return;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static void mxl5007t_set_mode_bits(struct mxl5007t_state *state,
+				   enum mxl5007t_mode mode,
+				   s32 if_diff_out_level)
+{
+	switch (mode) {
+	case MxL_MODE_ATSC:
+		set_reg_bits(state->tab_init, 0x06, 0x1f, 0x12);
+		break;
+	case MxL_MODE_DVBT:
+		set_reg_bits(state->tab_init, 0x06, 0x1f, 0x11);
+		break;
+	case MxL_MODE_ISDBT:
+		set_reg_bits(state->tab_init, 0x06, 0x1f, 0x10);
+		break;
+	case MxL_MODE_CABLE:
+		set_reg_bits(state->tab_init_cable, 0x09, 0xff, 0xc1);
+		set_reg_bits(state->tab_init_cable, 0x0a, 0xff,
+			     8 - if_diff_out_level);
+		set_reg_bits(state->tab_init_cable, 0x0b, 0xff, 0x17);
+		break;
+	default:
+		mxl_fail(-EINVAL);
+	}
+	return;
+}
+
+static void mxl5007t_set_if_freq_bits(struct mxl5007t_state *state,
+				      enum mxl5007t_if_freq if_freq,
+				      int invert_if)
+{
+	u8 val;
+
+	switch (if_freq) {
+	case MxL_IF_4_MHZ:
+		val = 0x00;
+		break;
+	case MxL_IF_4_5_MHZ:
+		val = 0x02;
+		break;
+	case MxL_IF_4_57_MHZ:
+		val = 0x03;
+		break;
+	case MxL_IF_5_MHZ:
+		val = 0x04;
+		break;
+	case MxL_IF_5_38_MHZ:
+		val = 0x05;
+		break;
+	case MxL_IF_6_MHZ:
+		val = 0x06;
+		break;
+	case MxL_IF_6_28_MHZ:
+		val = 0x07;
+		break;
+	case MxL_IF_9_1915_MHZ:
+		val = 0x08;
+		break;
+	case MxL_IF_35_25_MHZ:
+		val = 0x09;
+		break;
+	case MxL_IF_36_15_MHZ:
+		val = 0x0a;
+		break;
+	case MxL_IF_44_MHZ:
+		val = 0x0b;
+		break;
+	default:
+		mxl_fail(-EINVAL);
+		return;
+	}
+	set_reg_bits(state->tab_init, 0x02, 0x0f, val);
+
+	/* set inverted IF or normal IF */
+	set_reg_bits(state->tab_init, 0x02, 0x10, invert_if ? 0x10 : 0x00);
+
+	return;
+}
+
+static void mxl5007t_set_xtal_freq_bits(struct mxl5007t_state *state,
+					enum mxl5007t_xtal_freq xtal_freq)
+{
+	switch (xtal_freq) {
+	case MxL_XTAL_16_MHZ:
+		/* select xtal freq & ref freq */
+		set_reg_bits(state->tab_init, 0x03, 0xf0, 0x00);
+		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x00);
+		break;
+	case MxL_XTAL_20_MHZ:
+		set_reg_bits(state->tab_init, 0x03, 0xf0, 0x10);
+		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x01);
+		break;
+	case MxL_XTAL_20_25_MHZ:
+		set_reg_bits(state->tab_init, 0x03, 0xf0, 0x20);
+		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x02);
+		break;
+	case MxL_XTAL_20_48_MHZ:
+		set_reg_bits(state->tab_init, 0x03, 0xf0, 0x30);
+		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x03);
+		break;
+	case MxL_XTAL_24_MHZ:
+		set_reg_bits(state->tab_init, 0x03, 0xf0, 0x40);
+		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x04);
+		break;
+	case MxL_XTAL_25_MHZ:
+		set_reg_bits(state->tab_init, 0x03, 0xf0, 0x50);
+		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x05);
+		break;
+	case MxL_XTAL_25_14_MHZ:
+		set_reg_bits(state->tab_init, 0x03, 0xf0, 0x60);
+		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x06);
+		break;
+	case MxL_XTAL_27_MHZ:
+		set_reg_bits(state->tab_init, 0x03, 0xf0, 0x70);
+		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x07);
+		break;
+	case MxL_XTAL_28_8_MHZ:
+		set_reg_bits(state->tab_init, 0x03, 0xf0, 0x80);
+		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x08);
+		break;
+	case MxL_XTAL_32_MHZ:
+		set_reg_bits(state->tab_init, 0x03, 0xf0, 0x90);
+		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x09);
+		break;
+	case MxL_XTAL_40_MHZ:
+		set_reg_bits(state->tab_init, 0x03, 0xf0, 0xa0);
+		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0a);
+		break;
+	case MxL_XTAL_44_MHZ:
+		set_reg_bits(state->tab_init, 0x03, 0xf0, 0xb0);
+		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0b);
+		break;
+	case MxL_XTAL_48_MHZ:
+		set_reg_bits(state->tab_init, 0x03, 0xf0, 0xc0);
+		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0c);
+		break;
+	case MxL_XTAL_49_3811_MHZ:
+		set_reg_bits(state->tab_init, 0x03, 0xf0, 0xd0);
+		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0d);
+		break;
+	default:
+		mxl_fail(-EINVAL);
+		return;
+	}
+
+	return;
+}
+
+static struct reg_pair_t *mxl5007t_calc_init_regs(struct mxl5007t_state *state,
+						  enum mxl5007t_mode mode)
+{
+	struct mxl5007t_config *cfg = state->config;
+
+	memcpy(state->tab_init, init_tab, sizeof(init_tab));
+	memcpy(state->tab_init_cable, init_tab_cable, sizeof(init_tab_cable));
+
+	mxl5007t_set_mode_bits(state, mode, cfg->if_diff_out_level);
+	mxl5007t_set_if_freq_bits(state, cfg->if_freq_hz, cfg->invert_if);
+	mxl5007t_set_xtal_freq_bits(state, cfg->xtal_freq_hz);
+
+	set_reg_bits(state->tab_init, 0x04, 0x01, cfg->loop_thru_enable);
+	set_reg_bits(state->tab_init, 0x03, 0x08, cfg->clk_out_enable << 3);
+	set_reg_bits(state->tab_init, 0x03, 0x07, cfg->clk_out_amp);
+
+	if (mode >= MxL_MODE_CABLE) {
+		copy_reg_bits(state->tab_init, state->tab_init_cable);
+		return state->tab_init_cable;
+	} else
+		return state->tab_init;
+}
+
+static void mxl5007t_set_bw_bits(struct mxl5007t_state *state,
+				 enum mxl5007t_bw_mhz bw)
+{
+	u8 val;
+
+	switch (bw) {
+	case MxL_BW_6MHz:
+		val = 0x15; /* set DIG_MODEINDEX, DIG_MODEINDEX_A,
+			     * and DIG_MODEINDEX_CSF */
+		break;
+	case MxL_BW_7MHz:
+		val = 0x2a;
+		break;
+	case MxL_BW_8MHz:
+		val = 0x3f;
+		break;
+	default:
+		mxl_fail(-EINVAL);
+		return;
+	}
+	set_reg_bits(state->tab_rftune, 0x0c, 0x3f, val);
+
+	return;
+}
+
+static struct
+reg_pair_t *mxl5007t_calc_rf_tune_regs(struct mxl5007t_state *state,
+				       u32 rf_freq, enum mxl5007t_bw_mhz bw)
+{
+	u32 dig_rf_freq = 0;
+	u32 temp;
+	u32 frac_divider = 1000000;
+	unsigned int i;
+
+	memcpy(state->tab_rftune, reg_pair_rftune, sizeof(reg_pair_rftune));
+
+	mxl5007t_set_bw_bits(state, bw);
+
+	/* Convert RF frequency into 16 bits =>
+	 * 10 bit integer (MHz) + 6 bit fraction */
+	dig_rf_freq = rf_freq / MHz;
+
+	temp = rf_freq % MHz;
+
+	for (i = 0; i < 6; i++) {
+		dig_rf_freq <<= 1;
+		frac_divider /= 2;
+		if (temp > frac_divider) {
+			temp -= frac_divider;
+			dig_rf_freq++;
+		}
+	}
+
+	/* add to have shift center point by 7.8124 kHz */
+	if (temp > 7812)
+		dig_rf_freq++;
+
+	set_reg_bits(state->tab_rftune, 0x0d, 0xff, (u8) dig_rf_freq);
+	set_reg_bits(state->tab_rftune, 0x0e, 0xff, (u8) (dig_rf_freq >> 8));
+
+	if (rf_freq >= 333000000)
+		set_reg_bits(state->tab_rftune, 0x80, 0x40, 0x40);
+
+	return state->tab_rftune;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static int mxl5007t_write_reg(struct mxl5007t_state *state, u8 reg, u8 val)
+{
+	u8 buf[] = { reg, val };
+	int ret = MxL_I2C_Write(state->config->I2C_Addr, buf, 2, state->config);
+	if (ret) {
+		mxl_err("failed!");
+		return -EREMOTEIO;
+	}
+	
+	return ret;
+}
+
+static int mxl5007t_write_regs(struct mxl5007t_state *state,
+			       struct reg_pair_t *reg_pair)
+{
+	unsigned int i = 0;
+	int ret = 0;
+
+	while ((ret == 0) && (reg_pair[i].reg || reg_pair[i].val)) {
+		ret = mxl5007t_write_reg(state,
+		reg_pair[i].reg, reg_pair[i].val);
+		i++;
+	}
+
+	return ret;
+}
+
+/* unused
+static int mxl5007t_read_reg(struct mxl5007t_state *state, u8 reg, u8 *val)
+{
+	int ret = MxL_I2C_Read(state->config->I2C_Addr, reg, val, state->config);
+
+	if (ret) {
+		mxl_err("failed!");
+		return -EREMOTEIO;
+	}
+	return ret;
+}
+
+*/
+
+static int mxl5007t_soft_reset(struct mxl5007t_state *state)
+{
+	u8 d = 0xff;
+	
+	int ret = MxL_I2C_Write(state->config->I2C_Addr, &d, 1, state->config);
+	if (ret) {
+		mxl_err("failed!");
+		return -EREMOTEIO;
+	}
+	return ret;
+}
+
+static int mxl5007t_tuner_init(struct mxl5007t_state *state,
+			       enum mxl5007t_mode mode)
+{
+	struct reg_pair_t *init_regs;
+	int ret;
+
+	ret = mxl5007t_soft_reset(state);
+	if (mxl_fail(ret))
+		goto fail;
+
+	/* calculate initialization reg array */
+	init_regs = mxl5007t_calc_init_regs(state, mode);
+
+	ret = mxl5007t_write_regs(state, init_regs);
+	if (mxl_fail(ret))
+		goto fail;
+	mdelay(1);
+fail:
+	return ret;
+}
+
+static int mxl5007t_tuner_rf_tune(struct mxl5007t_state *state, u32 rf_freq_hz,
+				  enum mxl5007t_bw_mhz bw)
+{
+	struct reg_pair_t *rf_tune_regs;
+	int ret;
+
+	/* calculate channel change reg array */
+	rf_tune_regs = mxl5007t_calc_rf_tune_regs(state, rf_freq_hz, bw);
+
+	ret = mxl5007t_write_regs(state, rf_tune_regs);
+	if (mxl_fail(ret))
+		goto fail;
+	msleep(3);
+fail:
+	return ret;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* unused
+static int mxl5007t_synth_lock_status(struct mxl5007t_state *state,
+				      int *rf_locked, int *ref_locked)
+{
+	u8 d;
+	int ret;
+
+	*rf_locked = 0;
+	*ref_locked = 0;
+
+	ret = mxl5007t_read_reg(state, 0xd8, &d);
+	if (mxl_fail(ret))
+		goto fail;
+
+	if ((d & 0x0c) == 0x0c)
+		*rf_locked = 1;
+
+	if ((d & 0x03) == 0x03)
+		*ref_locked = 1;
+fail:
+	return ret;
+}
+*/
+
+/* ------------------------------------------------------------------------- */
+
+int a867_mxl5007t_set_params(struct mxl5007t_state *state, enum mxl5007t_bw_mhz bw, u32 freq)
+{
+	int ret;
+
+	mutex_lock(&state->lock);
+
+	ret = mxl5007t_tuner_init(state, state->config->Mode);
+	if (mxl_fail(ret))
+		goto fail;
+
+	ret = mxl5007t_tuner_rf_tune(state, freq, bw);
+	if (mxl_fail(ret))
+		goto fail;
+
+	state->frequency = freq;	//hz
+	state->bandwidth = bw;		//6, 7 ,8
+fail:
+	mutex_unlock(&state->lock);
+
+	return ret;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* unused
+static int mxl5007t_init(struct mxl5007t_state *state)
+{
+	int ret;
+
+	// wake from standby 
+	ret = mxl5007t_write_reg(state, 0x01, 0x01);
+	mxl_fail(ret);
+
+	return ret;
+}
+
+*/
+
+/* unused
+static int mxl5007t_sleep(struct mxl5007t_state *state)
+{
+	int ret;
+
+	// enter standby mode 
+	ret = mxl5007t_write_reg(state, 0x01, 0x00);
+	mxl_fail(ret);
+	ret = mxl5007t_write_reg(state, 0x0f, 0x00);
+	mxl_fail(ret);
+
+	return ret;
+}
+*/
+
+/* ------------------------------------------------------------------------- */
+
+/* unused
+static int mxl5007t_get_frequency(struct mxl5007t_state *state, u32 *frequency)
+{
+	*frequency = state->frequency;
+	return 0;
+}
+
+*/
+
+/* unused
+static int mxl5007t_get_bandwidth(struct mxl5007t_state *state, u32 *bandwidth)
+{
+	*bandwidth = state->bandwidth;
+	return 0;
+}
+*/
+
+void a867_mxl5007t_release(struct mxl5007t_state *state)
+{
+	if( state ) {
+		if( state->tab_init ) kfree(state->tab_init);
+		if( state->tab_init_cable ) kfree(state->tab_init_cable);
+		if( state->tab_rftune ) kfree(state->tab_rftune);
+		state->config->state = NULL;
+		kfree(state);
+	}
+}
+
+/* unused
+static int mxl5007t_get_chip_id(struct mxl5007t_state *state)
+{
+	char *name;
+	int ret;
+	u8 id;
+
+	ret = mxl5007t_read_reg(state, 0xd9, &id);
+	if (mxl_fail(ret))
+		goto fail;
+
+	switch (id) {
+	case MxL_5007_V1_F1:
+		name = "MxL5007.v1.f1";
+		break;
+	case MxL_5007_V1_F2:
+		name = "MxL5007.v1.f2";
+		break;
+	case MxL_5007_V2_100_F1:
+		name = "MxL5007.v2.100.f1";
+		break;
+	case MxL_5007_V2_100_F2:
+		name = "MxL5007.v2.100.f2";
+		break;
+	case MxL_5007_V2_200_F1:
+		name = "MxL5007.v2.200.f1";
+		break;
+	case MxL_5007_V2_200_F2:
+		name = "MxL5007.v2.200.f2";
+		break;
+	case MxL_5007_V4:
+		name = "MxL5007T.v4";
+		break;
+	default:
+		name = "MxL5007T";
+		printk(KERN_WARNING "%s: unknown rev (%02x)\n", __func__, id);
+		id = MxL_UNKNOWN_ID;
+	}
+	state->chip_id = id;
+	return 0;
+
+fail:
+	state->chip_id = MxL_UNKNOWN_ID;
+	return ret;
+}
+*/
+
+void a867_mxl5007t_attach(struct mxl5007t_config *cfg)
+{
+	struct mxl5007t_state *state;
+
+	state = kzalloc(sizeof(struct mxl5007t_state), GFP_KERNEL);
+	if( state == NULL ) return;
+
+	mutex_init(&state->lock);
+
+	state->config = cfg;
+	cfg->state = state;
+	state->tab_init = kzalloc(sizeof(init_tab), GFP_KERNEL);
+	if( !state->tab_init ) goto error;
+
+	state->tab_init_cable = kzalloc(sizeof(init_tab_cable), GFP_KERNEL);
+	if( !state->tab_init_cable ) goto error;
+
+	state->tab_rftune = kzalloc(sizeof(reg_pair_rftune), GFP_KERNEL);
+	if( !state->tab_rftune ) goto error;
+	return;
+error:
+	printk("fail to allocate memory\n");
+	return;
+}
+
+
+/*
+ * Overrides for Emacs so that we follow Linus's tabbing style.
+ * ---------------------------------------------------------------------------
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */
diff --git a/drivers/media/dvb/dvb-usb/a867_mxl5007t.h b/drivers/media/dvb/dvb-usb/a867_mxl5007t.h
new file mode 100644
index 0000000..fae1059
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_mxl5007t.h
@@ -0,0 +1,135 @@
+/*
+ *  mxl5007t.h - driver for the MaxLinear MxL5007T silicon tuner
+ *
+ *  Copyright (C) 2008 Michael Krufky <mkrufky@linuxtv.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * =============> modified from that in linux-2.6.34
+ */
+
+#ifndef __MXL5007T_H__
+#define __MXL5007T_H__
+
+#include "a867_type.h"
+/* ------------------------------------------------------------------------- */
+
+enum mxl5007t_if_freq {
+	MxL_IF_4_MHZ,      /*  4000000 */
+	MxL_IF_4_5_MHZ,    /*  4500000 */
+	MxL_IF_4_57_MHZ,   /*  4570000 */
+	MxL_IF_5_MHZ,      /*  5000000 */
+	MxL_IF_5_38_MHZ,   /*  5380000 */
+	MxL_IF_6_MHZ,      /*  6000000 */
+	MxL_IF_6_28_MHZ,   /*  6280000 */
+	MxL_IF_9_1915_MHZ, /*  9191500 */
+	MxL_IF_35_25_MHZ,  /* 35250000 */
+	MxL_IF_36_15_MHZ,  /* 36150000 */
+	MxL_IF_44_MHZ,     /* 44000000 */
+};
+
+enum mxl5007t_xtal_freq {
+	MxL_XTAL_16_MHZ,      /* 16000000 */
+	MxL_XTAL_20_MHZ,      /* 20000000 */
+	MxL_XTAL_20_25_MHZ,   /* 20250000 */
+	MxL_XTAL_20_48_MHZ,   /* 20480000 */
+	MxL_XTAL_24_MHZ,      /* 24000000 */
+	MxL_XTAL_25_MHZ,      /* 25000000 */
+	MxL_XTAL_25_14_MHZ,   /* 25140000 */
+	MxL_XTAL_27_MHZ,      /* 27000000 */
+	MxL_XTAL_28_8_MHZ,    /* 28800000 */
+	MxL_XTAL_32_MHZ,      /* 32000000 */
+	MxL_XTAL_40_MHZ,      /* 40000000 */
+	MxL_XTAL_44_MHZ,      /* 44000000 */
+	MxL_XTAL_48_MHZ,      /* 48000000 */
+	MxL_XTAL_49_3811_MHZ, /* 49381100 */
+};
+
+enum mxl5007t_clkout_amp {
+	MxL_CLKOUT_AMP_0_94V = 0,
+	MxL_CLKOUT_AMP_0_53V = 1,
+	MxL_CLKOUT_AMP_0_37V = 2,
+	MxL_CLKOUT_AMP_0_28V = 3,
+	MxL_CLKOUT_AMP_0_23V = 4,
+	MxL_CLKOUT_AMP_0_20V = 5,
+	MxL_CLKOUT_AMP_0_17V = 6,
+	MxL_CLKOUT_AMP_0_15V = 7,
+};
+
+enum mxl5007t_mode {
+	MxL_MODE_ISDBT     =    0,
+	MxL_MODE_DVBT      =    1,
+	MxL_MODE_ATSC      =    2,
+	MxL_MODE_CABLE     = 0x10,
+};
+
+enum mxl5007t_bw_mhz {
+	MxL_BW_6MHz = 6,
+	MxL_BW_7MHz = 7,
+	MxL_BW_8MHz = 8,
+};
+
+struct mxl5007t_config;
+enum mxl5007t_chip_version {
+	MxL_UNKNOWN_ID     = 0x00,
+	MxL_5007_V1_F1     = 0x11,
+	MxL_5007_V1_F2     = 0x12,
+	MxL_5007_V4        = 0x14,
+	MxL_5007_V2_100_F1 = 0x21,
+	MxL_5007_V2_100_F2 = 0x22,
+	MxL_5007_V2_200_F1 = 0x23,
+	MxL_5007_V2_200_F2 = 0x24,
+};
+
+struct mxl5007t_state {
+	struct mutex lock;
+	struct mxl5007t_config *config;
+	enum mxl5007t_chip_version chip_id;
+	struct reg_pair_t *tab_init;
+	struct reg_pair_t *tab_init_cable;
+	struct reg_pair_t *tab_rftune;
+	u32 frequency;
+	u32 bandwidth;
+};
+
+struct mxl5007t_config {
+	Demodulator*	demodulator;	//AF9035 instance //todo include
+	unsigned char			chip;			//AF9035 instance
+	unsigned char			I2C_Addr;
+	enum mxl5007t_mode	Mode;
+	struct mxl5007t_state *state;
+	s32 if_diff_out_level;
+	enum mxl5007t_clkout_amp clk_out_amp;
+	enum mxl5007t_xtal_freq xtal_freq_hz;
+	enum mxl5007t_if_freq if_freq_hz;
+	unsigned int invert_if:1;
+	unsigned int loop_thru_enable:1;
+	unsigned int clk_out_enable:1;
+};
+
+extern void a867_mxl5007t_attach(struct mxl5007t_config *cfg);
+extern void a867_mxl5007t_release(struct mxl5007t_state *state);
+extern int a867_mxl5007t_set_params(struct mxl5007t_state *state, enum mxl5007t_bw_mhz bw, u32 freq);
+
+#endif /* __MXL5007T_H__ */
+
+/*
+ * Overrides for Emacs so that we follow Linus's tabbing style.
+ * ---------------------------------------------------------------------------
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */
+
diff --git a/drivers/media/dvb/dvb-usb/a867_ofdm.h b/drivers/media/dvb/dvb-usb/a867_ofdm.h
new file mode 100644
index 0000000..30df3f2
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_ofdm.h
@@ -0,0 +1,18 @@
+
+#define DVB_LL_VERSION1 10
+
+#define DVB_LL_VERSION2 10
+
+#define DVB_LL_VERSION3 3
+
+#define DVB_LL_VERSION4 0
+
+
+#define DVB_OFDM_VERSION1 4
+
+#define DVB_OFDM_VERSION2 21
+
+#define DVB_OFDM_VERSION3 6
+
+#define DVB_OFDM_VERSION4 251
+
diff --git a/drivers/media/dvb/dvb-usb/a867_register.h b/drivers/media/dvb/dvb-usb/a867_register.h
new file mode 100644
index 0000000..76e4795
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_register.h
@@ -0,0 +1,13519 @@
+#ifndef _TD_BIU_REG_H_
+#define _TD_BIU_REG_H_
+// biu_reg.h 6-27-2007
+// gen_biu Ver 1.0 generated by
+#define xd_p_reg_p_aagc_log_2_acc   (*(volatile byte xdata *) 0xF000)
+#define    p_reg_p_aagc_log_2_acc   0xF000
+#define reg_p_aagc_log_2_acc_pos 0
+#define reg_p_aagc_log_2_acc_len 4
+#define reg_p_aagc_log_2_acc_lsb 0
+#define xd_p_reg_p_aagc_signal_level_rdy    (*(volatile byte xdata *) 0xF001)
+#define    p_reg_p_aagc_signal_level_rdy    0xF001
+#define reg_p_aagc_signal_level_rdy_pos 0
+#define reg_p_aagc_signal_level_rdy_len 1
+#define reg_p_aagc_signal_level_rdy_lsb 0
+#define xd_r_reg_r_aagc_signal_level_7_0    (*(volatile byte xdata *) 0xF002)
+#define    r_reg_r_aagc_signal_level_7_0    0xF002
+#define reg_r_aagc_signal_level_7_0_pos 0
+#define reg_r_aagc_signal_level_7_0_len 8
+#define reg_r_aagc_signal_level_7_0_lsb 0
+#define xd_r_reg_r_aagc_signal_level_9_8    (*(volatile byte xdata *) 0xF003)
+#define    r_reg_r_aagc_signal_level_9_8    0xF003
+#define reg_r_aagc_signal_level_9_8_pos 0
+#define reg_r_aagc_signal_level_9_8_len 2
+#define reg_r_aagc_signal_level_9_8_lsb 8
+#define xd_p_reg_p_aagc_rf_if_swap  (*(volatile byte xdata *) 0xF004)
+#define    p_reg_p_aagc_rf_if_swap  0xF004
+#define reg_p_aagc_rf_if_swap_pos 0
+#define reg_p_aagc_rf_if_swap_len 1
+#define reg_p_aagc_rf_if_swap_lsb 0
+#define xd_p_reg_p_pwm_rf_if_from_hw    (*(volatile byte xdata *) 0xF006)
+#define    p_reg_p_pwm_rf_if_from_hw    0xF006
+#define reg_p_pwm_rf_if_from_hw_pos 0
+#define reg_p_pwm_rf_if_from_hw_len 1
+#define reg_p_pwm_rf_if_from_hw_lsb 0
+#define xd_p_reg_aagc_out_if_inv    (*(volatile byte xdata *) 0xF007)
+#define    p_reg_aagc_out_if_inv    0xF007
+#define reg_aagc_out_if_inv_pos 0
+#define reg_aagc_out_if_inv_len 1
+#define reg_aagc_out_if_inv_lsb 0
+#define xd_p_reg_aagc_int_en    (*(volatile byte xdata *) 0xF008)
+#define    p_reg_aagc_int_en    0xF008
+#define reg_aagc_int_en_pos 0
+#define reg_aagc_int_en_len 1
+#define reg_aagc_int_en_lsb 0
+#define xd_p_reg_aagc_lock_change_flag  (*(volatile byte xdata *) 0xF009)
+#define    p_reg_aagc_lock_change_flag  0xF009
+#define reg_aagc_lock_change_flag_pos 0
+#define reg_aagc_lock_change_flag_len 1
+#define reg_aagc_lock_change_flag_lsb 0
+#define xd_p_reg_aagc_rf_loop_bw_scale_acquire  (*(volatile byte xdata *) 0xF00A)
+#define    p_reg_aagc_rf_loop_bw_scale_acquire  0xF00A
+#define reg_aagc_rf_loop_bw_scale_acquire_pos 0
+#define reg_aagc_rf_loop_bw_scale_acquire_len 5
+#define reg_aagc_rf_loop_bw_scale_acquire_lsb 0
+#define xd_p_reg_aagc_rf_loop_bw_scale_track    (*(volatile byte xdata *) 0xF00B)
+#define    p_reg_aagc_rf_loop_bw_scale_track    0xF00B
+#define reg_aagc_rf_loop_bw_scale_track_pos 0
+#define reg_aagc_rf_loop_bw_scale_track_len 5
+#define reg_aagc_rf_loop_bw_scale_track_lsb 0
+#define xd_p_reg_aagc_if_loop_bw_scale_acquire  (*(volatile byte xdata *) 0xF00C)
+#define    p_reg_aagc_if_loop_bw_scale_acquire  0xF00C
+#define reg_aagc_if_loop_bw_scale_acquire_pos 0
+#define reg_aagc_if_loop_bw_scale_acquire_len 5
+#define reg_aagc_if_loop_bw_scale_acquire_lsb 0
+#define xd_p_reg_aagc_if_loop_bw_scale_track    (*(volatile byte xdata *) 0xF00D)
+#define    p_reg_aagc_if_loop_bw_scale_track    0xF00D
+#define reg_aagc_if_loop_bw_scale_track_pos 0
+#define reg_aagc_if_loop_bw_scale_track_len 5
+#define reg_aagc_if_loop_bw_scale_track_lsb 0
+#define xd_p_reg_aagc_max_rf_agc_7_0    (*(volatile byte xdata *) 0xF00E)
+#define    p_reg_aagc_max_rf_agc_7_0    0xF00E
+#define reg_aagc_max_rf_agc_7_0_pos 0
+#define reg_aagc_max_rf_agc_7_0_len 8
+#define reg_aagc_max_rf_agc_7_0_lsb 0
+#define xd_p_reg_aagc_max_rf_agc_9_8    (*(volatile byte xdata *) 0xF00F)
+#define    p_reg_aagc_max_rf_agc_9_8    0xF00F
+#define reg_aagc_max_rf_agc_9_8_pos 0
+#define reg_aagc_max_rf_agc_9_8_len 2
+#define reg_aagc_max_rf_agc_9_8_lsb 8
+#define xd_p_reg_aagc_min_rf_agc_7_0    (*(volatile byte xdata *) 0xF010)
+#define    p_reg_aagc_min_rf_agc_7_0    0xF010
+#define reg_aagc_min_rf_agc_7_0_pos 0
+#define reg_aagc_min_rf_agc_7_0_len 8
+#define reg_aagc_min_rf_agc_7_0_lsb 0
+#define xd_p_reg_aagc_min_rf_agc_9_8    (*(volatile byte xdata *) 0xF011)
+#define    p_reg_aagc_min_rf_agc_9_8    0xF011
+#define reg_aagc_min_rf_agc_9_8_pos 0
+#define reg_aagc_min_rf_agc_9_8_len 2
+#define reg_aagc_min_rf_agc_9_8_lsb 8
+#define xd_p_reg_aagc_max_if_agc_7_0    (*(volatile byte xdata *) 0xF012)
+#define    p_reg_aagc_max_if_agc_7_0    0xF012
+#define reg_aagc_max_if_agc_7_0_pos 0
+#define reg_aagc_max_if_agc_7_0_len 8
+#define reg_aagc_max_if_agc_7_0_lsb 0
+#define xd_p_reg_aagc_max_if_agc_9_8    (*(volatile byte xdata *) 0xF013)
+#define    p_reg_aagc_max_if_agc_9_8    0xF013
+#define reg_aagc_max_if_agc_9_8_pos 0
+#define reg_aagc_max_if_agc_9_8_len 2
+#define reg_aagc_max_if_agc_9_8_lsb 8
+#define xd_p_reg_aagc_min_if_agc_7_0    (*(volatile byte xdata *) 0xF014)
+#define    p_reg_aagc_min_if_agc_7_0    0xF014
+#define reg_aagc_min_if_agc_7_0_pos 0
+#define reg_aagc_min_if_agc_7_0_len 8
+#define reg_aagc_min_if_agc_7_0_lsb 0
+#define xd_p_reg_aagc_min_if_agc_9_8    (*(volatile byte xdata *) 0xF015)
+#define    p_reg_aagc_min_if_agc_9_8    0xF015
+#define reg_aagc_min_if_agc_9_8_pos 0
+#define reg_aagc_min_if_agc_9_8_len 2
+#define reg_aagc_min_if_agc_9_8_lsb 8
+#define xd_p_reg_aagc_lock_sample_scale (*(volatile byte xdata *) 0xF016)
+#define    p_reg_aagc_lock_sample_scale 0xF016
+#define reg_aagc_lock_sample_scale_pos 0
+#define reg_aagc_lock_sample_scale_len 5
+#define reg_aagc_lock_sample_scale_lsb 0
+#define xd_p_reg_aagc_rf_agc_lock_scale_acquire (*(volatile byte xdata *) 0xF017)
+#define    p_reg_aagc_rf_agc_lock_scale_acquire 0xF017
+#define reg_aagc_rf_agc_lock_scale_acquire_pos 0
+#define reg_aagc_rf_agc_lock_scale_acquire_len 3
+#define reg_aagc_rf_agc_lock_scale_acquire_lsb 0
+#define xd_p_reg_aagc_rf_agc_lock_scale_track   (*(volatile byte xdata *) 0xF018)
+#define    p_reg_aagc_rf_agc_lock_scale_track   0xF018
+#define reg_aagc_rf_agc_lock_scale_track_pos 0
+#define reg_aagc_rf_agc_lock_scale_track_len 3
+#define reg_aagc_rf_agc_lock_scale_track_lsb 0
+#define xd_p_reg_aagc_if_agc_lock_scale_acquire (*(volatile byte xdata *) 0xF019)
+#define    p_reg_aagc_if_agc_lock_scale_acquire 0xF019
+#define reg_aagc_if_agc_lock_scale_acquire_pos 0
+#define reg_aagc_if_agc_lock_scale_acquire_len 3
+#define reg_aagc_if_agc_lock_scale_acquire_lsb 0
+#define xd_p_reg_aagc_if_agc_lock_scale_track   (*(volatile byte xdata *) 0xF01A)
+#define    p_reg_aagc_if_agc_lock_scale_track   0xF01A
+#define reg_aagc_if_agc_lock_scale_track_pos 0
+#define reg_aagc_if_agc_lock_scale_track_len 3
+#define reg_aagc_if_agc_lock_scale_track_lsb 0
+#define xd_p_reg_aagc_rf_top_numerator_s_7_0    (*(volatile byte xdata *) 0xF01B)
+#define    p_reg_aagc_rf_top_numerator_s_7_0    0xF01B
+#define reg_aagc_rf_top_numerator_s_7_0_pos 0
+#define reg_aagc_rf_top_numerator_s_7_0_len 8
+#define reg_aagc_rf_top_numerator_s_7_0_lsb 0
+#define xd_p_reg_aagc_rf_top_numerator_s_9_8    (*(volatile byte xdata *) 0xF01C)
+#define    p_reg_aagc_rf_top_numerator_s_9_8    0xF01C
+#define reg_aagc_rf_top_numerator_s_9_8_pos 0
+#define reg_aagc_rf_top_numerator_s_9_8_len 2
+#define reg_aagc_rf_top_numerator_s_9_8_lsb 8
+#define xd_p_reg_aagc_if_top_numerator_s_7_0    (*(volatile byte xdata *) 0xF01D)
+#define    p_reg_aagc_if_top_numerator_s_7_0    0xF01D
+#define reg_aagc_if_top_numerator_s_7_0_pos 0
+#define reg_aagc_if_top_numerator_s_7_0_len 8
+#define reg_aagc_if_top_numerator_s_7_0_lsb 0
+#define xd_p_reg_aagc_if_top_numerator_s_9_8    (*(volatile byte xdata *) 0xF01E)
+#define    p_reg_aagc_if_top_numerator_s_9_8    0xF01E
+#define reg_aagc_if_top_numerator_s_9_8_pos 0
+#define reg_aagc_if_top_numerator_s_9_8_len 2
+#define reg_aagc_if_top_numerator_s_9_8_lsb 8
+#define xd_p_reg_aagc_adc_out_desired_s_7_0 (*(volatile byte xdata *) 0xF01F)
+#define    p_reg_aagc_adc_out_desired_s_7_0 0xF01F
+#define reg_aagc_adc_out_desired_s_7_0_pos 0
+#define reg_aagc_adc_out_desired_s_7_0_len 8
+#define reg_aagc_adc_out_desired_s_7_0_lsb 0
+#define xd_p_reg_aagc_adc_out_desired_s_8   (*(volatile byte xdata *) 0xF020)
+#define    p_reg_aagc_adc_out_desired_s_8   0xF020
+#define reg_aagc_adc_out_desired_s_8_pos 0
+#define reg_aagc_adc_out_desired_s_8_len 1
+#define reg_aagc_adc_out_desired_s_8_lsb 8
+#define xd_p_reg_aagc_lock_count_th (*(volatile byte xdata *) 0xF021)
+#define    p_reg_aagc_lock_count_th 0xF021
+#define reg_aagc_lock_count_th_pos 0
+#define reg_aagc_lock_count_th_len 4
+#define reg_aagc_lock_count_th_lsb 0
+#define xd_p_reg_aagc_rf_agc_unlock_numerator   (*(volatile byte xdata *) 0xF022)
+#define    p_reg_aagc_rf_agc_unlock_numerator   0xF022
+#define reg_aagc_rf_agc_unlock_numerator_pos 0
+#define reg_aagc_rf_agc_unlock_numerator_len 6
+#define reg_aagc_rf_agc_unlock_numerator_lsb 0
+#define xd_p_reg_aagc_if_agc_unlock_numerator   (*(volatile byte xdata *) 0xF023)
+#define    p_reg_aagc_if_agc_unlock_numerator   0xF023
+#define reg_aagc_if_agc_unlock_numerator_pos 0
+#define reg_aagc_if_agc_unlock_numerator_len 6
+#define reg_aagc_if_agc_unlock_numerator_lsb 0
+#define xd_p_reg_aagc_rf_top_numerator_m_7_0    (*(volatile byte xdata *) 0xF025)
+#define    p_reg_aagc_rf_top_numerator_m_7_0    0xF025
+#define reg_aagc_rf_top_numerator_m_7_0_pos 0
+#define reg_aagc_rf_top_numerator_m_7_0_len 8
+#define reg_aagc_rf_top_numerator_m_7_0_lsb 0
+#define xd_p_reg_aagc_rf_top_numerator_m_9_8    (*(volatile byte xdata *) 0xF026)
+#define    p_reg_aagc_rf_top_numerator_m_9_8    0xF026
+#define reg_aagc_rf_top_numerator_m_9_8_pos 0
+#define reg_aagc_rf_top_numerator_m_9_8_len 2
+#define reg_aagc_rf_top_numerator_m_9_8_lsb 8
+#define xd_p_reg_aagc_if_top_numerator_m_7_0    (*(volatile byte xdata *) 0xF027)
+#define    p_reg_aagc_if_top_numerator_m_7_0    0xF027
+#define reg_aagc_if_top_numerator_m_7_0_pos 0
+#define reg_aagc_if_top_numerator_m_7_0_len 8
+#define reg_aagc_if_top_numerator_m_7_0_lsb 0
+#define xd_p_reg_aagc_if_top_numerator_m_9_8    (*(volatile byte xdata *) 0xF028)
+#define    p_reg_aagc_if_top_numerator_m_9_8    0xF028
+#define reg_aagc_if_top_numerator_m_9_8_pos 0
+#define reg_aagc_if_top_numerator_m_9_8_len 2
+#define reg_aagc_if_top_numerator_m_9_8_lsb 8
+#define xd_p_reg_aagc_adc_out_desired_m_7_0 (*(volatile byte xdata *) 0xF029)
+#define    p_reg_aagc_adc_out_desired_m_7_0 0xF029
+#define reg_aagc_adc_out_desired_m_7_0_pos 0
+#define reg_aagc_adc_out_desired_m_7_0_len 8
+#define reg_aagc_adc_out_desired_m_7_0_lsb 0
+#define xd_p_reg_aagc_adc_out_desired_m_8   (*(volatile byte xdata *) 0xF02A)
+#define    p_reg_aagc_adc_out_desired_m_8   0xF02A
+#define reg_aagc_adc_out_desired_m_8_pos 0
+#define reg_aagc_adc_out_desired_m_8_len 1
+#define reg_aagc_adc_out_desired_m_8_lsb 8
+#define xd_p_reg_aagc_mobile_sel    (*(volatile byte xdata *) 0xF02B)
+#define    p_reg_aagc_mobile_sel    0xF02B
+#define reg_aagc_mobile_sel_pos 0
+#define reg_aagc_mobile_sel_len 1
+#define reg_aagc_mobile_sel_lsb 0
+#define xd_p_reg_aagc_top_reload    (*(volatile byte xdata *) 0xF02C)
+#define    p_reg_aagc_top_reload    0xF02C
+#define reg_aagc_top_reload_pos 0
+#define reg_aagc_top_reload_len 1
+#define reg_aagc_top_reload_lsb 0
+#define xd_p_reg_aagc_rf_delta_voltage_en   (*(volatile byte xdata *) 0xF02D)
+#define    p_reg_aagc_rf_delta_voltage_en   0xF02D
+#define reg_aagc_rf_delta_voltage_en_pos 0
+#define reg_aagc_rf_delta_voltage_en_len 1
+#define reg_aagc_rf_delta_voltage_en_lsb 0
+#define xd_p_reg_aagc_rf_voltage_inc    (*(volatile byte xdata *) 0xF02E)
+#define    p_reg_aagc_rf_voltage_inc    0xF02E
+#define reg_aagc_rf_voltage_inc_pos 0
+#define reg_aagc_rf_voltage_inc_len 1
+#define reg_aagc_rf_voltage_inc_lsb 0
+#define xd_p_reg_aagc_if_delta_voltage_en   (*(volatile byte xdata *) 0xF02F)
+#define    p_reg_aagc_if_delta_voltage_en   0xF02F
+#define reg_aagc_if_delta_voltage_en_pos 0
+#define reg_aagc_if_delta_voltage_en_len 1
+#define reg_aagc_if_delta_voltage_en_lsb 0
+#define xd_p_reg_aagc_if_voltage_inc    (*(volatile byte xdata *) 0xF030)
+#define    p_reg_aagc_if_voltage_inc    0xF030
+#define reg_aagc_if_voltage_inc_pos 0
+#define reg_aagc_if_voltage_inc_len 1
+#define reg_aagc_if_voltage_inc_lsb 0
+#define xd_p_reg_aagc_rf_delta_voltage_7_0  (*(volatile byte xdata *) 0xF032)
+#define    p_reg_aagc_rf_delta_voltage_7_0  0xF032
+#define reg_aagc_rf_delta_voltage_7_0_pos 0
+#define reg_aagc_rf_delta_voltage_7_0_len 8
+#define reg_aagc_rf_delta_voltage_7_0_lsb 0
+#define xd_p_reg_aagc_rf_delta_voltage_15_8 (*(volatile byte xdata *) 0xF033)
+#define    p_reg_aagc_rf_delta_voltage_15_8 0xF033
+#define reg_aagc_rf_delta_voltage_15_8_pos 0
+#define reg_aagc_rf_delta_voltage_15_8_len 8
+#define reg_aagc_rf_delta_voltage_15_8_lsb 8
+#define xd_p_reg_aagc_rf_delta_voltage_23_16    (*(volatile byte xdata *) 0xF034)
+#define    p_reg_aagc_rf_delta_voltage_23_16    0xF034
+#define reg_aagc_rf_delta_voltage_23_16_pos 0
+#define reg_aagc_rf_delta_voltage_23_16_len 8
+#define reg_aagc_rf_delta_voltage_23_16_lsb 16
+#define xd_p_reg_aagc_rf_delta_voltage_29_24    (*(volatile byte xdata *) 0xF035)
+#define    p_reg_aagc_rf_delta_voltage_29_24    0xF035
+#define reg_aagc_rf_delta_voltage_29_24_pos 0
+#define reg_aagc_rf_delta_voltage_29_24_len 6
+#define reg_aagc_rf_delta_voltage_29_24_lsb 24
+#define xd_p_reg_aagc_if_delta_voltage_7_0  (*(volatile byte xdata *) 0xF036)
+#define    p_reg_aagc_if_delta_voltage_7_0  0xF036
+#define reg_aagc_if_delta_voltage_7_0_pos 0
+#define reg_aagc_if_delta_voltage_7_0_len 8
+#define reg_aagc_if_delta_voltage_7_0_lsb 0
+#define xd_p_reg_aagc_if_delta_voltage_15_8 (*(volatile byte xdata *) 0xF037)
+#define    p_reg_aagc_if_delta_voltage_15_8 0xF037
+#define reg_aagc_if_delta_voltage_15_8_pos 0
+#define reg_aagc_if_delta_voltage_15_8_len 8
+#define reg_aagc_if_delta_voltage_15_8_lsb 8
+#define xd_p_reg_aagc_if_delta_voltage_23_16    (*(volatile byte xdata *) 0xF038)
+#define    p_reg_aagc_if_delta_voltage_23_16    0xF038
+#define reg_aagc_if_delta_voltage_23_16_pos 0
+#define reg_aagc_if_delta_voltage_23_16_len 8
+#define reg_aagc_if_delta_voltage_23_16_lsb 16
+#define xd_p_reg_aagc_if_delta_voltage_29_24    (*(volatile byte xdata *) 0xF039)
+#define    p_reg_aagc_if_delta_voltage_29_24    0xF039
+#define reg_aagc_if_delta_voltage_29_24_pos 0
+#define reg_aagc_if_delta_voltage_29_24_len 6
+#define reg_aagc_if_delta_voltage_29_24_lsb 24
+#define xd_p_reg_aagc_delta_voltage_hold_time   (*(volatile byte xdata *) 0xF03A)
+#define    p_reg_aagc_delta_voltage_hold_time   0xF03A
+#define reg_aagc_delta_voltage_hold_time_pos 0
+#define reg_aagc_delta_voltage_hold_time_len 8
+#define reg_aagc_delta_voltage_hold_time_lsb 0
+#define xd_p_reg_aagc_top_th_dis    (*(volatile byte xdata *) 0xF041)
+#define    p_reg_aagc_top_th_dis    0xF041
+#define reg_aagc_top_th_dis_pos 0
+#define reg_aagc_top_th_dis_len 1
+#define reg_aagc_top_th_dis_lsb 0
+#define xd_p_reg_p_aagc_rf_floor_dca    (*(volatile byte xdata *) 0xF042)
+#define    p_reg_p_aagc_rf_floor_dca    0xF042
+#define reg_p_aagc_rf_floor_dca_pos 0
+#define reg_p_aagc_rf_floor_dca_len 8
+#define reg_p_aagc_rf_floor_dca_lsb 0
+#define xd_p_reg_p_aagc_if_floor_dca    (*(volatile byte xdata *) 0xF043)
+#define    p_reg_p_aagc_if_floor_dca    0xF043
+#define reg_p_aagc_if_floor_dca_pos 0
+#define reg_p_aagc_if_floor_dca_len 8
+#define reg_p_aagc_if_floor_dca_lsb 0
+#define xd_p_reg_p_aagc_rf_gain_scale_dca   (*(volatile byte xdata *) 0xF044)
+#define    p_reg_p_aagc_rf_gain_scale_dca   0xF044
+#define reg_p_aagc_rf_gain_scale_dca_pos 0
+#define reg_p_aagc_rf_gain_scale_dca_len 3
+#define reg_p_aagc_rf_gain_scale_dca_lsb 0
+#define xd_p_reg_p_aagc_if_gain_scale_dca   (*(volatile byte xdata *) 0xF045)
+#define    p_reg_p_aagc_if_gain_scale_dca   0xF045
+#define reg_p_aagc_if_gain_scale_dca_pos 0
+#define reg_p_aagc_if_gain_scale_dca_len 3
+#define reg_p_aagc_if_gain_scale_dca_lsb 0
+#define xd_r_reg_r_aagc_ufl_gain    (*(volatile byte xdata *) 0xF046)
+#define    r_reg_r_aagc_ufl_gain    0xF046
+#define reg_r_aagc_ufl_gain_pos 0
+#define reg_r_aagc_ufl_gain_len 8
+#define reg_r_aagc_ufl_gain_lsb 0
+#define xd_p_reg_aagc_out_rf_inv    (*(volatile byte xdata *) 0xF047)
+#define    p_reg_aagc_out_rf_inv    0xF047
+#define reg_aagc_out_rf_inv_pos 0
+#define reg_aagc_out_rf_inv_len 1
+#define reg_aagc_out_rf_inv_lsb 0
+#define xd_p_reg_p_aagc_save_agc_control    (*(volatile byte xdata *) 0xF048)
+#define    p_reg_p_aagc_save_agc_control    0xF048
+#define reg_p_aagc_save_agc_control_pos 0
+#define reg_p_aagc_save_agc_control_len 1
+#define reg_p_aagc_save_agc_control_lsb 0
+#define xd_p_reg_aagc_fw_sel    (*(volatile byte xdata *) 0xF049)
+#define    p_reg_aagc_fw_sel    0xF049
+#define reg_aagc_fw_sel_pos 0
+#define reg_aagc_fw_sel_len 1
+#define reg_aagc_fw_sel_lsb 0
+#define xd_r_reg_r_aagc_rf_control_7_0  (*(volatile byte xdata *) 0xF04A)
+#define    r_reg_r_aagc_rf_control_7_0  0xF04A
+#define reg_r_aagc_rf_control_7_0_pos 0
+#define reg_r_aagc_rf_control_7_0_len 8
+#define reg_r_aagc_rf_control_7_0_lsb 0
+#define xd_r_reg_r_aagc_rf_control_9_8  (*(volatile byte xdata *) 0xF04B)
+#define    r_reg_r_aagc_rf_control_9_8  0xF04B
+#define reg_r_aagc_rf_control_9_8_pos 0
+#define reg_r_aagc_rf_control_9_8_len 2
+#define reg_r_aagc_rf_control_9_8_lsb 8
+#define xd_r_reg_r_aagc_if_control_7_0  (*(volatile byte xdata *) 0xF04C)
+#define    r_reg_r_aagc_if_control_7_0  0xF04C
+#define reg_r_aagc_if_control_7_0_pos 0
+#define reg_r_aagc_if_control_7_0_len 8
+#define reg_r_aagc_if_control_7_0_lsb 0
+#define xd_r_reg_r_aagc_if_control_9_8  (*(volatile byte xdata *) 0xF04D)
+#define    r_reg_r_aagc_if_control_9_8  0xF04D
+#define reg_r_aagc_if_control_9_8_pos 0
+#define reg_r_aagc_if_control_9_8_len 2
+#define reg_r_aagc_if_control_9_8_lsb 8
+#define xd_p_reg_aagc_adc_out_desired_from_fw_7_0   (*(volatile byte xdata *) 0xF04E)
+#define    p_reg_aagc_adc_out_desired_from_fw_7_0   0xF04E
+#define reg_aagc_adc_out_desired_from_fw_7_0_pos 0
+#define reg_aagc_adc_out_desired_from_fw_7_0_len 8
+#define reg_aagc_adc_out_desired_from_fw_7_0_lsb 0
+#define xd_p_reg_aagc_adc_out_desired_from_fw_8 (*(volatile byte xdata *) 0xF04F)
+#define    p_reg_aagc_adc_out_desired_from_fw_8 0xF04F
+#define reg_aagc_adc_out_desired_from_fw_8_pos 0
+#define reg_aagc_adc_out_desired_from_fw_8_len 1
+#define reg_aagc_adc_out_desired_from_fw_8_lsb 8
+#define xd_p_reg_aagc_init_rf_agc_7_0   (*(volatile byte xdata *) 0xF050)
+#define    p_reg_aagc_init_rf_agc_7_0   0xF050
+#define reg_aagc_init_rf_agc_7_0_pos 0
+#define reg_aagc_init_rf_agc_7_0_len 8
+#define reg_aagc_init_rf_agc_7_0_lsb 0
+#define xd_p_reg_aagc_init_rf_agc_9_8   (*(volatile byte xdata *) 0xF051)
+#define    p_reg_aagc_init_rf_agc_9_8   0xF051
+#define reg_aagc_init_rf_agc_9_8_pos 0
+#define reg_aagc_init_rf_agc_9_8_len 2
+#define reg_aagc_init_rf_agc_9_8_lsb 8
+#define xd_p_reg_aagc_init_if_agc_7_0   (*(volatile byte xdata *) 0xF052)
+#define    p_reg_aagc_init_if_agc_7_0   0xF052
+#define reg_aagc_init_if_agc_7_0_pos 0
+#define reg_aagc_init_if_agc_7_0_len 8
+#define reg_aagc_init_if_agc_7_0_lsb 0
+#define xd_p_reg_aagc_init_if_agc_9_8   (*(volatile byte xdata *) 0xF053)
+#define    p_reg_aagc_init_if_agc_9_8   0xF053
+#define reg_aagc_init_if_agc_9_8_pos 0
+#define reg_aagc_init_if_agc_9_8_len 2
+#define reg_aagc_init_if_agc_9_8_lsb 8
+#define xd_p_reg_p_pwm_if_high_unit_num (*(volatile byte xdata *) 0xF054)
+#define    p_reg_p_pwm_if_high_unit_num 0xF054
+#define reg_p_pwm_if_high_unit_num_pos 0
+#define reg_p_pwm_if_high_unit_num_len 8
+#define reg_p_pwm_if_high_unit_num_lsb 0
+#define xd_p_reg_p_pwm_rf_high_unit_num (*(volatile byte xdata *) 0xF055)
+#define    p_reg_p_pwm_rf_high_unit_num 0xF055
+#define reg_p_pwm_rf_high_unit_num_pos 0
+#define reg_p_pwm_rf_high_unit_num_len 8
+#define reg_p_pwm_rf_high_unit_num_lsb 0
+#define xd_p_reg_p_pwm_rf_gpio  (*(volatile byte xdata *) 0xF058)
+#define    p_reg_p_pwm_rf_gpio  0xF058
+#define reg_p_pwm_rf_gpio_pos 0
+#define reg_p_pwm_rf_gpio_len 1
+#define reg_p_pwm_rf_gpio_lsb 0
+#define xd_p_reg_p_pwm_if_gpio  (*(volatile byte xdata *) 0xF058)
+#define    p_reg_p_pwm_if_gpio  0xF058
+#define reg_p_pwm_if_gpio_pos 1
+#define reg_p_pwm_if_gpio_len 1
+#define reg_p_pwm_if_gpio_lsb 0
+#define xd_p_reg_aagc_in_sat_cnt_7_0    (*(volatile byte xdata *) 0xF05A)
+#define    p_reg_aagc_in_sat_cnt_7_0    0xF05A
+#define reg_aagc_in_sat_cnt_7_0_pos 0
+#define reg_aagc_in_sat_cnt_7_0_len 8
+#define reg_aagc_in_sat_cnt_7_0_lsb 0
+#define xd_p_reg_aagc_in_sat_cnt_15_8   (*(volatile byte xdata *) 0xF05B)
+#define    p_reg_aagc_in_sat_cnt_15_8   0xF05B
+#define reg_aagc_in_sat_cnt_15_8_pos 0
+#define reg_aagc_in_sat_cnt_15_8_len 8
+#define reg_aagc_in_sat_cnt_15_8_lsb 8
+#define xd_p_reg_aagc_in_sat_cnt_23_16  (*(volatile byte xdata *) 0xF05C)
+#define    p_reg_aagc_in_sat_cnt_23_16  0xF05C
+#define reg_aagc_in_sat_cnt_23_16_pos 0
+#define reg_aagc_in_sat_cnt_23_16_len 8
+#define reg_aagc_in_sat_cnt_23_16_lsb 16
+#define xd_p_reg_aagc_in_sat_cnt_31_24  (*(volatile byte xdata *) 0xF05D)
+#define    p_reg_aagc_in_sat_cnt_31_24  0xF05D
+#define reg_aagc_in_sat_cnt_31_24_pos 0
+#define reg_aagc_in_sat_cnt_31_24_len 8
+#define reg_aagc_in_sat_cnt_31_24_lsb 24
+#define xd_p_reg_p_pwm_cycle_unit   (*(volatile byte xdata *) 0xF05E)
+#define    p_reg_p_pwm_cycle_unit   0xF05E
+#define reg_p_pwm_cycle_unit_pos 0
+#define reg_p_pwm_cycle_unit_len 4
+#define reg_p_pwm_cycle_unit_lsb 0
+#define xd_p_reg_p_pwm_en   (*(volatile byte xdata *) 0xF05F)
+#define    p_reg_p_pwm_en   0xF05F
+#define reg_p_pwm_en_pos 0
+#define reg_p_pwm_en_len 1
+#define reg_p_pwm_en_lsb 0
+#define xd_r_reg_aagc_rf_gain   (*(volatile byte xdata *) 0xF060)
+#define    r_reg_aagc_rf_gain   0xF060
+#define reg_aagc_rf_gain_pos 0
+#define reg_aagc_rf_gain_len 8
+#define reg_aagc_rf_gain_lsb 0
+#define xd_r_reg_aagc_if_gain   (*(volatile byte xdata *) 0xF061)
+#define    r_reg_aagc_if_gain   0xF061
+#define reg_aagc_if_gain_pos 0
+#define reg_aagc_if_gain_len 8
+#define reg_aagc_if_gain_lsb 0
+#define xd_r_reg_aagc_current_desired_level_7_0 (*(volatile byte xdata *) 0xF062)
+#define    r_reg_aagc_current_desired_level_7_0 0xF062
+#define reg_aagc_current_desired_level_7_0_pos 0
+#define reg_aagc_current_desired_level_7_0_len 8
+#define reg_aagc_current_desired_level_7_0_lsb 0
+#define xd_r_reg_aagc_current_desired_level_8   (*(volatile byte xdata *) 0xF063)
+#define    r_reg_aagc_current_desired_level_8   0xF063
+#define reg_aagc_current_desired_level_8_pos 0
+#define reg_aagc_current_desired_level_8_len 1
+#define reg_aagc_current_desired_level_8_lsb 8
+#define xd_p_reg_tinr_fifo_size (*(volatile byte xdata *) 0xF064)
+#define    p_reg_tinr_fifo_size 0xF064
+#define reg_tinr_fifo_size_pos 0
+#define reg_tinr_fifo_size_len 5
+#define reg_tinr_fifo_size_lsb 0
+#define xd_p_reg_tinr_saturation_th_7_0 (*(volatile byte xdata *) 0xF065)
+#define    p_reg_tinr_saturation_th_7_0 0xF065
+#define reg_tinr_saturation_th_7_0_pos 0
+#define reg_tinr_saturation_th_7_0_len 8
+#define reg_tinr_saturation_th_7_0_lsb 0
+#define xd_p_reg_tinr_saturation_th_9_8 (*(volatile byte xdata *) 0xF066)
+#define    p_reg_tinr_saturation_th_9_8 0xF066
+#define reg_tinr_saturation_th_9_8_pos 0
+#define reg_tinr_saturation_th_9_8_len 2
+#define reg_tinr_saturation_th_9_8_lsb 8
+#define xd_p_reg_tinr_saturation_cnt_th (*(volatile byte xdata *) 0xF067)
+#define    p_reg_tinr_saturation_cnt_th 0xF067
+#define reg_tinr_saturation_cnt_th_pos 0
+#define reg_tinr_saturation_cnt_th_len 4
+#define reg_tinr_saturation_cnt_th_lsb 0
+#define xd_r_reg_tinr_counter_7_0   (*(volatile byte xdata *) 0xF068)
+#define    r_reg_tinr_counter_7_0   0xF068
+#define reg_tinr_counter_7_0_pos 0
+#define reg_tinr_counter_7_0_len 8
+#define reg_tinr_counter_7_0_lsb 0
+#define xd_r_reg_tinr_counter_15_8  (*(volatile byte xdata *) 0xF069)
+#define    r_reg_tinr_counter_15_8  0xF069
+#define reg_tinr_counter_15_8_pos 0
+#define reg_tinr_counter_15_8_len 8
+#define reg_tinr_counter_15_8_lsb 8
+#define xd_p_reg_tinr_counter_rst   (*(volatile byte xdata *) 0xF06C)
+#define    p_reg_tinr_counter_rst   0xF06C
+#define reg_tinr_counter_rst_pos 0
+#define reg_tinr_counter_rst_len 1
+#define reg_tinr_counter_rst_lsb 0
+#define xd_p_reg_tinr_ins_th_7_0    (*(volatile byte xdata *) 0xF06F)
+#define    p_reg_tinr_ins_th_7_0    0xF06F
+#define reg_tinr_ins_th_7_0_pos 0
+#define reg_tinr_ins_th_7_0_len 8
+#define reg_tinr_ins_th_7_0_lsb 0
+#define xd_p_reg_tinr_ins_th_9_8    (*(volatile byte xdata *) 0xF070)
+#define    p_reg_tinr_ins_th_9_8    0xF070
+#define reg_tinr_ins_th_9_8_pos 0
+#define reg_tinr_ins_th_9_8_len 2
+#define reg_tinr_ins_th_9_8_lsb 8
+#define xd_p_reg_tinr_ins_en    (*(volatile byte xdata *) 0xF071)
+#define    p_reg_tinr_ins_en    0xF071
+#define reg_tinr_ins_en_pos 0
+#define reg_tinr_ins_en_len 1
+#define reg_tinr_ins_en_lsb 0
+#define xd_p_reg_tinr_ins_size  (*(volatile byte xdata *) 0xF072)
+#define    p_reg_tinr_ins_size  0xF072
+#define reg_tinr_ins_size_pos 0
+#define reg_tinr_ins_size_len 4
+#define reg_tinr_ins_size_lsb 0
+#define xd_p_reg_tinr_ins_hnum  (*(volatile byte xdata *) 0xF073)
+#define    p_reg_tinr_ins_hnum  0xF073
+#define reg_tinr_ins_hnum_pos 0
+#define reg_tinr_ins_hnum_len 4
+#define reg_tinr_ins_hnum_lsb 0
+#define xd_r_reg_tinr_ins_hcnt_7_0  (*(volatile byte xdata *) 0xF074)
+#define    r_reg_tinr_ins_hcnt_7_0  0xF074
+#define reg_tinr_ins_hcnt_7_0_pos 0
+#define reg_tinr_ins_hcnt_7_0_len 8
+#define reg_tinr_ins_hcnt_7_0_lsb 0
+#define xd_r_reg_tinr_ins_hcnt_15_8 (*(volatile byte xdata *) 0xF075)
+#define    r_reg_tinr_ins_hcnt_15_8 0xF075
+#define reg_tinr_ins_hcnt_15_8_pos 0
+#define reg_tinr_ins_hcnt_15_8_len 8
+#define reg_tinr_ins_hcnt_15_8_lsb 8
+#define xd_p_reg_tinr_in_conj   (*(volatile byte xdata *) 0xF076)
+#define    p_reg_tinr_in_conj   0xF076
+#define reg_tinr_in_conj_pos 0
+#define reg_tinr_in_conj_len 1
+#define reg_tinr_in_conj_lsb 0
+#define xd_p_reg_tinr_in_zero_if    (*(volatile byte xdata *) 0xF077)
+#define    p_reg_tinr_in_zero_if    0xF077
+#define reg_tinr_in_zero_if_pos 0
+#define reg_tinr_in_zero_if_len 2
+#define reg_tinr_in_zero_if_lsb 0
+#define xd_p_reg_tinr_in_shift  (*(volatile byte xdata *) 0xF078)
+#define    p_reg_tinr_in_shift  0xF078
+#define reg_tinr_in_shift_pos 0
+#define reg_tinr_in_shift_len 1
+#define reg_tinr_in_shift_lsb 0
+#define xd_p_reg_tinr_in_conj_sat_counter_rst   (*(volatile byte xdata *) 0xF079)
+#define    p_reg_tinr_in_conj_sat_counter_rst   0xF079
+#define reg_tinr_in_conj_sat_counter_rst_pos 0
+#define reg_tinr_in_conj_sat_counter_rst_len 1
+#define reg_tinr_in_conj_sat_counter_rst_lsb 0
+#define xd_r_reg_tinr_in_conj_sat_counter_7_0   (*(volatile byte xdata *) 0xF07A)
+#define    r_reg_tinr_in_conj_sat_counter_7_0   0xF07A
+#define reg_tinr_in_conj_sat_counter_7_0_pos 0
+#define reg_tinr_in_conj_sat_counter_7_0_len 8
+#define reg_tinr_in_conj_sat_counter_7_0_lsb 0
+#define xd_r_reg_tinr_in_conj_sat_counter_14_8  (*(volatile byte xdata *) 0xF07B)
+#define    r_reg_tinr_in_conj_sat_counter_14_8  0xF07B
+#define reg_tinr_in_conj_sat_counter_14_8_pos 0
+#define reg_tinr_in_conj_sat_counter_14_8_len 7
+#define reg_tinr_in_conj_sat_counter_14_8_lsb 8
+#define xd_p_reg_p_antif_en (*(volatile byte xdata *) 0xF07C)
+#define    p_reg_p_antif_en 0xF07C
+#define reg_p_antif_en_pos 0
+#define reg_p_antif_en_len 1
+#define reg_p_antif_en_lsb 0
+#define xd_p_reg_p_antif_rst    (*(volatile byte xdata *) 0xF07D)
+#define    p_reg_p_antif_rst    0xF07D
+#define reg_p_antif_rst_pos 0
+#define reg_p_antif_rst_len 1
+#define reg_p_antif_rst_lsb 0
+#define xd_p_reg_p_antif_byp    (*(volatile byte xdata *) 0xF07E)
+#define    p_reg_p_antif_byp    0xF07E
+#define reg_p_antif_byp_pos 0
+#define reg_p_antif_byp_len 1
+#define reg_p_antif_byp_lsb 0
+#define xd_p_reg_p_antif_mode   (*(volatile byte xdata *) 0xF07F)
+#define    p_reg_p_antif_mode   0xF07F
+#define reg_p_antif_mode_pos 0
+#define reg_p_antif_mode_len 1
+#define reg_p_antif_mode_lsb 0
+#define xd_p_reg_p_ds_byp   (*(volatile byte xdata *) 0xF080)
+#define    p_reg_p_ds_byp   0xF080
+#define reg_p_ds_byp_pos 0
+#define reg_p_ds_byp_len 1
+#define reg_p_ds_byp_lsb 0
+#define xd_p_reg_p_antif_dagc5_mode (*(volatile byte xdata *) 0xF081)
+#define    p_reg_p_antif_dagc5_mode 0xF081
+#define reg_p_antif_dagc5_mode_pos 0
+#define reg_p_antif_dagc5_mode_len 2
+#define reg_p_antif_dagc5_mode_lsb 0
+#define xd_p_reg_p_antif_dagc5_desired_level_7_0    (*(volatile byte xdata *) 0xF082)
+#define    p_reg_p_antif_dagc5_desired_level_7_0    0xF082
+#define reg_p_antif_dagc5_desired_level_7_0_pos 0
+#define reg_p_antif_dagc5_desired_level_7_0_len 8
+#define reg_p_antif_dagc5_desired_level_7_0_lsb 0
+#define xd_p_reg_p_antif_dagc5_desired_level_8  (*(volatile byte xdata *) 0xF083)
+#define    p_reg_p_antif_dagc5_desired_level_8  0xF083
+#define reg_p_antif_dagc5_desired_level_8_pos 0
+#define reg_p_antif_dagc5_desired_level_8_len 1
+#define reg_p_antif_dagc5_desired_level_8_lsb 8
+#define xd_p_reg_p_antif_dagc5_apply_delay  (*(volatile byte xdata *) 0xF084)
+#define    p_reg_p_antif_dagc5_apply_delay  0xF084
+#define reg_p_antif_dagc5_apply_delay_pos 0
+#define reg_p_antif_dagc5_apply_delay_len 7
+#define reg_p_antif_dagc5_apply_delay_lsb 0
+#define xd_p_reg_p_antif_dagc5_fixed_gain_7_0   (*(volatile byte xdata *) 0xF085)
+#define    p_reg_p_antif_dagc5_fixed_gain_7_0   0xF085
+#define reg_p_antif_dagc5_fixed_gain_7_0_pos 0
+#define reg_p_antif_dagc5_fixed_gain_7_0_len 8
+#define reg_p_antif_dagc5_fixed_gain_7_0_lsb 0
+#define xd_p_reg_p_antif_dagc5_fixed_gain_11_8  (*(volatile byte xdata *) 0xF086)
+#define    p_reg_p_antif_dagc5_fixed_gain_11_8  0xF086
+#define reg_p_antif_dagc5_fixed_gain_11_8_pos 0
+#define reg_p_antif_dagc5_fixed_gain_11_8_len 4
+#define reg_p_antif_dagc5_fixed_gain_11_8_lsb 8
+#define xd_p_reg_p_antif_dagc5_use_despow   (*(volatile byte xdata *) 0xF087)
+#define    p_reg_p_antif_dagc5_use_despow   0xF087
+#define reg_p_antif_dagc5_use_despow_pos 0
+#define reg_p_antif_dagc5_use_despow_len 1
+#define reg_p_antif_dagc5_use_despow_lsb 0
+#define xd_p_reg_p_antif_dagc5_log_2_accumulate_num (*(volatile byte xdata *) 0xF088)
+#define    p_reg_p_antif_dagc5_log_2_accumulate_num 0xF088
+#define reg_p_antif_dagc5_log_2_accumulate_num_pos 0
+#define reg_p_antif_dagc5_log_2_accumulate_num_len 5
+#define reg_p_antif_dagc5_log_2_accumulate_num_lsb 0
+#define xd_p_reg_p_antif_dagc5_in_sat_cnt_7_0   (*(volatile byte xdata *) 0xF089)
+#define    p_reg_p_antif_dagc5_in_sat_cnt_7_0   0xF089
+#define reg_p_antif_dagc5_in_sat_cnt_7_0_pos 0
+#define reg_p_antif_dagc5_in_sat_cnt_7_0_len 8
+#define reg_p_antif_dagc5_in_sat_cnt_7_0_lsb 0
+#define xd_p_reg_p_antif_dagc5_in_sat_cnt_15_8  (*(volatile byte xdata *) 0xF08A)
+#define    p_reg_p_antif_dagc5_in_sat_cnt_15_8  0xF08A
+#define reg_p_antif_dagc5_in_sat_cnt_15_8_pos 0
+#define reg_p_antif_dagc5_in_sat_cnt_15_8_len 8
+#define reg_p_antif_dagc5_in_sat_cnt_15_8_lsb 8
+#define xd_p_reg_p_antif_dagc5_in_sat_cnt_23_16 (*(volatile byte xdata *) 0xF08B)
+#define    p_reg_p_antif_dagc5_in_sat_cnt_23_16 0xF08B
+#define reg_p_antif_dagc5_in_sat_cnt_23_16_pos 0
+#define reg_p_antif_dagc5_in_sat_cnt_23_16_len 8
+#define reg_p_antif_dagc5_in_sat_cnt_23_16_lsb 16
+#define xd_p_reg_p_antif_dagc5_in_sat_cnt_31_24 (*(volatile byte xdata *) 0xF08C)
+#define    p_reg_p_antif_dagc5_in_sat_cnt_31_24 0xF08C
+#define reg_p_antif_dagc5_in_sat_cnt_31_24_pos 0
+#define reg_p_antif_dagc5_in_sat_cnt_31_24_len 8
+#define reg_p_antif_dagc5_in_sat_cnt_31_24_lsb 24
+#define xd_p_reg_p_antif_dagc5_out_sat_cnt_7_0  (*(volatile byte xdata *) 0xF08D)
+#define    p_reg_p_antif_dagc5_out_sat_cnt_7_0  0xF08D
+#define reg_p_antif_dagc5_out_sat_cnt_7_0_pos 0
+#define reg_p_antif_dagc5_out_sat_cnt_7_0_len 8
+#define reg_p_antif_dagc5_out_sat_cnt_7_0_lsb 0
+#define xd_p_reg_p_antif_dagc5_out_sat_cnt_15_8 (*(volatile byte xdata *) 0xF08E)
+#define    p_reg_p_antif_dagc5_out_sat_cnt_15_8 0xF08E
+#define reg_p_antif_dagc5_out_sat_cnt_15_8_pos 0
+#define reg_p_antif_dagc5_out_sat_cnt_15_8_len 8
+#define reg_p_antif_dagc5_out_sat_cnt_15_8_lsb 8
+#define xd_p_reg_p_antif_dagc5_out_sat_cnt_23_16    (*(volatile byte xdata *) 0xF08F)
+#define    p_reg_p_antif_dagc5_out_sat_cnt_23_16    0xF08F
+#define reg_p_antif_dagc5_out_sat_cnt_23_16_pos 0
+#define reg_p_antif_dagc5_out_sat_cnt_23_16_len 8
+#define reg_p_antif_dagc5_out_sat_cnt_23_16_lsb 16
+#define xd_p_reg_p_antif_dagc5_out_sat_cnt_31_24    (*(volatile byte xdata *) 0xF090)
+#define    p_reg_p_antif_dagc5_out_sat_cnt_31_24    0xF090
+#define reg_p_antif_dagc5_out_sat_cnt_31_24_pos 0
+#define reg_p_antif_dagc5_out_sat_cnt_31_24_len 8
+#define reg_p_antif_dagc5_out_sat_cnt_31_24_lsb 24
+#define xd_p_reg_p_antif_dagc5_rst  (*(volatile byte xdata *) 0xF091)
+#define    p_reg_p_antif_dagc5_rst  0xF091
+#define reg_p_antif_dagc5_rst_pos 0
+#define reg_p_antif_dagc5_rst_len 1
+#define reg_p_antif_dagc5_rst_lsb 0
+#define xd_p_reg_p_antif_dagc5_en   (*(volatile byte xdata *) 0xF092)
+#define    p_reg_p_antif_dagc5_en   0xF092
+#define reg_p_antif_dagc5_en_pos 0
+#define reg_p_antif_dagc5_en_len 1
+#define reg_p_antif_dagc5_en_lsb 0
+#define xd_p_reg_p_antif_sc_mode    (*(volatile byte xdata *) 0xF093)
+#define    p_reg_p_antif_sc_mode    0xF093
+#define reg_p_antif_sc_mode_pos 0
+#define reg_p_antif_sc_mode_len 4
+#define reg_p_antif_sc_mode_lsb 0
+#define xd_p_reg_p_antif_dagc5_done (*(volatile byte xdata *) 0xF094)
+#define    p_reg_p_antif_dagc5_done 0xF094
+#define reg_p_antif_dagc5_done_pos 0
+#define reg_p_antif_dagc5_done_len 1
+#define reg_p_antif_dagc5_done_lsb 0
+#define xd_r_reg_r_antif_sc_7_0 (*(volatile byte xdata *) 0xF095)
+#define    r_reg_r_antif_sc_7_0 0xF095
+#define reg_r_antif_sc_7_0_pos 0
+#define reg_r_antif_sc_7_0_len 8
+#define reg_r_antif_sc_7_0_lsb 0
+#define xd_r_reg_r_antif_sc_15_8    (*(volatile byte xdata *) 0xF096)
+#define    r_reg_r_antif_sc_15_8    0xF096
+#define reg_r_antif_sc_15_8_pos 0
+#define reg_r_antif_sc_15_8_len 8
+#define reg_r_antif_sc_15_8_lsb 8
+#define xd_r_reg_r_antif_dagc5_multiplier_7_0   (*(volatile byte xdata *) 0xF097)
+#define    r_reg_r_antif_dagc5_multiplier_7_0   0xF097
+#define reg_r_antif_dagc5_multiplier_7_0_pos 0
+#define reg_r_antif_dagc5_multiplier_7_0_len 8
+#define reg_r_antif_dagc5_multiplier_7_0_lsb 0
+#define xd_r_reg_r_antif_dagc5_multiplier_15_8  (*(volatile byte xdata *) 0xF098)
+#define    r_reg_r_antif_dagc5_multiplier_15_8  0xF098
+#define reg_r_antif_dagc5_multiplier_15_8_pos 0
+#define reg_r_antif_dagc5_multiplier_15_8_len 8
+#define reg_r_antif_dagc5_multiplier_15_8_lsb 8
+#define xd_r_reg_r_antif_dagc5_right_shift_bits (*(volatile byte xdata *) 0xF099)
+#define    r_reg_r_antif_dagc5_right_shift_bits 0xF099
+#define reg_r_antif_dagc5_right_shift_bits_pos 0
+#define reg_r_antif_dagc5_right_shift_bits_len 4
+#define reg_r_antif_dagc5_right_shift_bits_lsb 0
+#define xd_p_reg_p_antif_dagc5_bypass_scale_ctl (*(volatile byte xdata *) 0xF09A)
+#define    p_reg_p_antif_dagc5_bypass_scale_ctl 0xF09A
+#define reg_p_antif_dagc5_bypass_scale_ctl_pos 0
+#define reg_p_antif_dagc5_bypass_scale_ctl_len 3
+#define reg_p_antif_dagc5_bypass_scale_ctl_lsb 0
+#define xd_p_reg_mccid_ccirunno_7_0 (*(volatile byte xdata *) 0xF09B)
+#define    p_reg_mccid_ccirunno_7_0 0xF09B
+#define reg_mccid_ccirunno_7_0_pos 0
+#define reg_mccid_ccirunno_7_0_len 8
+#define reg_mccid_ccirunno_7_0_lsb 0
+#define xd_p_reg_mccid_ccirunno_8   (*(volatile byte xdata *) 0xF09C)
+#define    p_reg_mccid_ccirunno_8   0xF09C
+#define reg_mccid_ccirunno_8_pos 0
+#define reg_mccid_ccirunno_8_len 1
+#define reg_mccid_ccirunno_8_lsb 8
+#define xd_p_reg_mccid_acirunno_7_0 (*(volatile byte xdata *) 0xF09D)
+#define    p_reg_mccid_acirunno_7_0 0xF09D
+#define reg_mccid_acirunno_7_0_pos 0
+#define reg_mccid_acirunno_7_0_len 8
+#define reg_mccid_acirunno_7_0_lsb 0
+#define xd_p_reg_mccid_acirunno_8   (*(volatile byte xdata *) 0xF09E)
+#define    p_reg_mccid_acirunno_8   0xF09E
+#define reg_mccid_acirunno_8_pos 0
+#define reg_mccid_acirunno_8_len 1
+#define reg_mccid_acirunno_8_lsb 8
+#define xd_p_reg_mccid_maxtonenearrange_7_0 (*(volatile byte xdata *) 0xF09F)
+#define    p_reg_mccid_maxtonenearrange_7_0 0xF09F
+#define reg_mccid_maxtonenearrange_7_0_pos 0
+#define reg_mccid_maxtonenearrange_7_0_len 8
+#define reg_mccid_maxtonenearrange_7_0_lsb 0
+#define xd_p_reg_mccid_maxtonenearrange_8   (*(volatile byte xdata *) 0xF0A0)
+#define    p_reg_mccid_maxtonenearrange_8   0xF0A0
+#define reg_mccid_maxtonenearrange_8_pos 0
+#define reg_mccid_maxtonenearrange_8_len 1
+#define reg_mccid_maxtonenearrange_8_lsb 8
+#define xd_r_reg_mccid_maxacipower_7_0  (*(volatile byte xdata *) 0xF0A1)
+#define    r_reg_mccid_maxacipower_7_0  0xF0A1
+#define reg_mccid_maxacipower_7_0_pos 0
+#define reg_mccid_maxacipower_7_0_len 8
+#define reg_mccid_maxacipower_7_0_lsb 0
+#define xd_r_reg_mccid_maxacipower_15_8 (*(volatile byte xdata *) 0xF0A2)
+#define    r_reg_mccid_maxacipower_15_8 0xF0A2
+#define reg_mccid_maxacipower_15_8_pos 0
+#define reg_mccid_maxacipower_15_8_len 8
+#define reg_mccid_maxacipower_15_8_lsb 8
+#define xd_r_reg_mccid_maxacipower_19_16    (*(volatile byte xdata *) 0xF0A3)
+#define    r_reg_mccid_maxacipower_19_16    0xF0A3
+#define reg_mccid_maxacipower_19_16_pos 0
+#define reg_mccid_maxacipower_19_16_len 4
+#define reg_mccid_maxacipower_19_16_lsb 16
+#define xd_p_reg_p_dcoe_en  (*(volatile byte xdata *) 0xF0D5)
+#define    p_reg_p_dcoe_en  0xF0D5
+#define reg_p_dcoe_en_pos 0
+#define reg_p_dcoe_en_len 1
+#define reg_p_dcoe_en_lsb 0
+#define xd_p_reg_p_dcoe_rst (*(volatile byte xdata *) 0xF0D6)
+#define    p_reg_p_dcoe_rst 0xF0D6
+#define reg_p_dcoe_rst_pos 0
+#define reg_p_dcoe_rst_len 1
+#define reg_p_dcoe_rst_lsb 0
+#define xd_p_reg_p_dcoe_clear   (*(volatile byte xdata *) 0xF0D7)
+#define    p_reg_p_dcoe_clear   0xF0D7
+#define reg_p_dcoe_clear_pos 0
+#define reg_p_dcoe_clear_len 1
+#define reg_p_dcoe_clear_lsb 0
+#define xd_p_reg_p_dcoe_applyloc_7_0    (*(volatile byte xdata *) 0xF0D8)
+#define    p_reg_p_dcoe_applyloc_7_0    0xF0D8
+#define reg_p_dcoe_applyloc_7_0_pos 0
+#define reg_p_dcoe_applyloc_7_0_len 8
+#define reg_p_dcoe_applyloc_7_0_lsb 0
+#define xd_p_reg_p_dcoe_applyloc_12_8   (*(volatile byte xdata *) 0xF0D9)
+#define    p_reg_p_dcoe_applyloc_12_8   0xF0D9
+#define reg_p_dcoe_applyloc_12_8_pos 0
+#define reg_p_dcoe_applyloc_12_8_len 5
+#define reg_p_dcoe_applyloc_12_8_lsb 8
+#define xd_p_reg_p_dcoe_accnums (*(volatile byte xdata *) 0xF0DA)
+#define    p_reg_p_dcoe_accnums 0xF0DA
+#define reg_p_dcoe_accnums_pos 0
+#define reg_p_dcoe_accnums_len 3
+#define reg_p_dcoe_accnums_lsb 0
+#define xd_p_reg_p_dcoe_accweightsum_sh (*(volatile byte xdata *) 0xF0DB)
+#define    p_reg_p_dcoe_accweightsum_sh 0xF0DB
+#define reg_p_dcoe_accweightsum_sh_pos 0
+#define reg_p_dcoe_accweightsum_sh_len 3
+#define reg_p_dcoe_accweightsum_sh_lsb 0
+#define xd_p_reg_p_dcoe_accweightcurr   (*(volatile byte xdata *) 0xF0DC)
+#define    p_reg_p_dcoe_accweightcurr   0xF0DC
+#define reg_p_dcoe_accweightcurr_pos 0
+#define reg_p_dcoe_accweightcurr_len 8
+#define reg_p_dcoe_accweightcurr_lsb 0
+#define xd_p_reg_dcoe_apply_rd  (*(volatile byte xdata *) 0xF0DF)
+#define    p_reg_dcoe_apply_rd  0xF0DF
+#define reg_dcoe_apply_rd_pos 0
+#define reg_dcoe_apply_rd_len 1
+#define reg_dcoe_apply_rd_lsb 0
+#define xd_r_reg_dcoe_apply_i   (*(volatile byte xdata *) 0xF0E0)
+#define    r_reg_dcoe_apply_i   0xF0E0
+#define reg_dcoe_apply_i_pos 0
+#define reg_dcoe_apply_i_len 8
+#define reg_dcoe_apply_i_lsb 0
+#define xd_r_reg_dcoe_apply_q   (*(volatile byte xdata *) 0xF0E1)
+#define    r_reg_dcoe_apply_q   0xF0E1
+#define reg_dcoe_apply_q_pos 0
+#define reg_dcoe_apply_q_len 8
+#define reg_dcoe_apply_q_lsb 0
+#define xd_p_reg_p_dcrm_en  (*(volatile byte xdata *) 0xF0E2)
+#define    p_reg_p_dcrm_en  0xF0E2
+#define reg_p_dcrm_en_pos 0
+#define reg_p_dcrm_en_len 1
+#define reg_p_dcrm_en_lsb 0
+#define xd_p_reg_p_dcrm_fir (*(volatile byte xdata *) 0xF0E3)
+#define    p_reg_p_dcrm_fir 0xF0E3
+#define reg_p_dcrm_fir_pos 0
+#define reg_p_dcrm_fir_len 1
+#define reg_p_dcrm_fir_lsb 0
+#define xd_p_reg_p_dcrm_log2_firlen (*(volatile byte xdata *) 0xF0E4)
+#define    p_reg_p_dcrm_log2_firlen 0xF0E4
+#define reg_p_dcrm_log2_firlen_pos 0
+#define reg_p_dcrm_log2_firlen_len 3
+#define reg_p_dcrm_log2_firlen_lsb 0
+#define xd_r_reg_dcoe_apply_fir_i   (*(volatile byte xdata *) 0xF0E5)
+#define    r_reg_dcoe_apply_fir_i   0xF0E5
+#define reg_dcoe_apply_fir_i_pos 0
+#define reg_dcoe_apply_fir_i_len 8
+#define reg_dcoe_apply_fir_i_lsb 0
+#define xd_r_reg_dcoe_apply_fir_q   (*(volatile byte xdata *) 0xF0E6)
+#define    r_reg_dcoe_apply_fir_q   0xF0E6
+#define reg_dcoe_apply_fir_q_pos 0
+#define reg_dcoe_apply_fir_q_len 8
+#define reg_dcoe_apply_fir_q_lsb 0
+#define xd_p_reg_p_dcrm_force_en    (*(volatile byte xdata *) 0xF0E7)
+#define    p_reg_p_dcrm_force_en    0xF0E7
+#define reg_p_dcrm_force_en_pos 0
+#define reg_p_dcrm_force_en_len 1
+#define reg_p_dcrm_force_en_lsb 0
+#define xd_p_reg_p_dcrm_force_value_i   (*(volatile byte xdata *) 0xF0E8)
+#define    p_reg_p_dcrm_force_value_i   0xF0E8
+#define reg_p_dcrm_force_value_i_pos 0
+#define reg_p_dcrm_force_value_i_len 8
+#define reg_p_dcrm_force_value_i_lsb 0
+#define xd_p_reg_p_dcrm_force_value_q   (*(volatile byte xdata *) 0xF0E9)
+#define    p_reg_p_dcrm_force_value_q   0xF0E9
+#define reg_p_dcrm_force_value_q_pos 0
+#define reg_p_dcrm_force_value_q_len 8
+#define reg_p_dcrm_force_value_q_lsb 0
+#define xd_p_reg_p_iqip_en  (*(volatile byte xdata *) 0xF0EA)
+#define    p_reg_p_iqip_en  0xF0EA
+#define reg_p_iqip_en_pos 0
+#define reg_p_iqip_en_len 1
+#define reg_p_iqip_en_lsb 0
+#define xd_p_reg_p_iqip_rst (*(volatile byte xdata *) 0xF0EB)
+#define    p_reg_p_iqip_rst 0xF0EB
+#define reg_p_iqip_rst_pos 0
+#define reg_p_iqip_rst_len 1
+#define reg_p_iqip_rst_lsb 0
+#define xd_p_reg_iqip_mu_ld (*(volatile byte xdata *) 0xF0EC)
+#define    p_reg_iqip_mu_ld 0xF0EC
+#define reg_iqip_mu_ld_pos 0
+#define reg_iqip_mu_ld_len 1
+#define reg_iqip_mu_ld_lsb 0
+#define xd_p_reg_p_iqip_mu_7_0  (*(volatile byte xdata *) 0xF0ED)
+#define    p_reg_p_iqip_mu_7_0  0xF0ED
+#define reg_p_iqip_mu_7_0_pos 0
+#define reg_p_iqip_mu_7_0_len 8
+#define reg_p_iqip_mu_7_0_lsb 0
+#define xd_p_reg_p_iqip_mu_11_8 (*(volatile byte xdata *) 0xF0EE)
+#define    p_reg_p_iqip_mu_11_8 0xF0EE
+#define reg_p_iqip_mu_11_8_pos 0
+#define reg_p_iqip_mu_11_8_len 4
+#define reg_p_iqip_mu_11_8_lsb 8
+#define xd_p_reg_iqip_gs_ld (*(volatile byte xdata *) 0xF0EF)
+#define    p_reg_iqip_gs_ld 0xF0EF
+#define reg_iqip_gs_ld_pos 0
+#define reg_iqip_gs_ld_len 1
+#define reg_iqip_gs_ld_lsb 0
+#define xd_p_reg_p_iqip_gsnums  (*(volatile byte xdata *) 0xF0F0)
+#define    p_reg_p_iqip_gsnums  0xF0F0
+#define reg_p_iqip_gsnums_pos 0
+#define reg_p_iqip_gsnums_len 4
+#define reg_p_iqip_gsnums_lsb 0
+#define xd_p_reg_p_iqip_gsites_7_0  (*(volatile byte xdata *) 0xF0F1)
+#define    p_reg_p_iqip_gsites_7_0  0xF0F1
+#define reg_p_iqip_gsites_7_0_pos 0
+#define reg_p_iqip_gsites_7_0_len 8
+#define reg_p_iqip_gsites_7_0_lsb 0
+#define xd_p_reg_p_iqip_gsites_15_8 (*(volatile byte xdata *) 0xF0F2)
+#define    p_reg_p_iqip_gsites_15_8 0xF0F2
+#define reg_p_iqip_gsites_15_8_pos 0
+#define reg_p_iqip_gsites_15_8_len 8
+#define reg_p_iqip_gsites_15_8_lsb 8
+#define xd_p_reg_iqip_w_ld  (*(volatile byte xdata *) 0xF0F3)
+#define    p_reg_iqip_w_ld  0xF0F3
+#define reg_iqip_w_ld_pos 0
+#define reg_iqip_w_ld_len 1
+#define reg_iqip_w_ld_lsb 0
+#define xd_p_reg_p_iqip_w_re_7_0    (*(volatile byte xdata *) 0xF0F4)
+#define    p_reg_p_iqip_w_re_7_0    0xF0F4
+#define reg_p_iqip_w_re_7_0_pos 0
+#define reg_p_iqip_w_re_7_0_len 8
+#define reg_p_iqip_w_re_7_0_lsb 0
+#define xd_p_reg_p_iqip_w_re_15_8   (*(volatile byte xdata *) 0xF0F5)
+#define    p_reg_p_iqip_w_re_15_8   0xF0F5
+#define reg_p_iqip_w_re_15_8_pos 0
+#define reg_p_iqip_w_re_15_8_len 8
+#define reg_p_iqip_w_re_15_8_lsb 8
+#define xd_p_reg_p_iqip_w_re_16 (*(volatile byte xdata *) 0xF0F6)
+#define    p_reg_p_iqip_w_re_16 0xF0F6
+#define reg_p_iqip_w_re_16_pos 0
+#define reg_p_iqip_w_re_16_len 1
+#define reg_p_iqip_w_re_16_lsb 16
+#define xd_p_reg_p_iqip_w_im_7_0    (*(volatile byte xdata *) 0xF0F7)
+#define    p_reg_p_iqip_w_im_7_0    0xF0F7
+#define reg_p_iqip_w_im_7_0_pos 0
+#define reg_p_iqip_w_im_7_0_len 8
+#define reg_p_iqip_w_im_7_0_lsb 0
+#define xd_p_reg_p_iqip_w_im_15_8   (*(volatile byte xdata *) 0xF0F8)
+#define    p_reg_p_iqip_w_im_15_8   0xF0F8
+#define reg_p_iqip_w_im_15_8_pos 0
+#define reg_p_iqip_w_im_15_8_len 8
+#define reg_p_iqip_w_im_15_8_lsb 8
+#define xd_p_reg_p_iqip_w_im_16 (*(volatile byte xdata *) 0xF0F9)
+#define    p_reg_p_iqip_w_im_16 0xF0F9
+#define reg_p_iqip_w_im_16_pos 0
+#define reg_p_iqip_w_im_16_len 1
+#define reg_p_iqip_w_im_16_lsb 16
+#define xd_p_reg_iqip_accnums_rd    (*(volatile byte xdata *) 0xF0FA)
+#define    p_reg_iqip_accnums_rd    0xF0FA
+#define reg_iqip_accnums_rd_pos 0
+#define reg_iqip_accnums_rd_len 1
+#define reg_iqip_accnums_rd_lsb 0
+#define xd_p_reg_p_iqip_accnums (*(volatile byte xdata *) 0xF0FB)
+#define    p_reg_p_iqip_accnums 0xF0FB
+#define reg_p_iqip_accnums_pos 0
+#define reg_p_iqip_accnums_len 2
+#define reg_p_iqip_accnums_lsb 0
+#define xd_p_reg_iqip_accnums_rdy   (*(volatile byte xdata *) 0xF0FC)
+#define    p_reg_iqip_accnums_rdy   0xF0FC
+#define reg_iqip_accnums_rdy_pos 0
+#define reg_iqip_accnums_rdy_len 1
+#define reg_iqip_accnums_rdy_lsb 0
+#define xd_r_reg_r_iqip_wacc_re_7_0 (*(volatile byte xdata *) 0xF0FD)
+#define    r_reg_r_iqip_wacc_re_7_0 0xF0FD
+#define reg_r_iqip_wacc_re_7_0_pos 0
+#define reg_r_iqip_wacc_re_7_0_len 8
+#define reg_r_iqip_wacc_re_7_0_lsb 0
+#define xd_r_reg_r_iqip_wacc_re_15_8    (*(volatile byte xdata *) 0xF0FE)
+#define    r_reg_r_iqip_wacc_re_15_8    0xF0FE
+#define reg_r_iqip_wacc_re_15_8_pos 0
+#define reg_r_iqip_wacc_re_15_8_len 8
+#define reg_r_iqip_wacc_re_15_8_lsb 8
+#define xd_r_reg_r_iqip_wacc_re_16  (*(volatile byte xdata *) 0xF0FF)
+#define    r_reg_r_iqip_wacc_re_16  0xF0FF
+#define reg_r_iqip_wacc_re_16_pos 0
+#define reg_r_iqip_wacc_re_16_len 1
+#define reg_r_iqip_wacc_re_16_lsb 16
+#define xd_r_reg_r_iqip_wacc_im_7_0 (*(volatile byte xdata *) 0xF100)
+#define    r_reg_r_iqip_wacc_im_7_0 0xF100
+#define reg_r_iqip_wacc_im_7_0_pos 0
+#define reg_r_iqip_wacc_im_7_0_len 8
+#define reg_r_iqip_wacc_im_7_0_lsb 0
+#define xd_r_reg_r_iqip_wacc_im_15_8    (*(volatile byte xdata *) 0xF101)
+#define    r_reg_r_iqip_wacc_im_15_8    0xF101
+#define reg_r_iqip_wacc_im_15_8_pos 0
+#define reg_r_iqip_wacc_im_15_8_len 8
+#define reg_r_iqip_wacc_im_15_8_lsb 8
+#define xd_r_reg_r_iqip_wacc_im_16  (*(volatile byte xdata *) 0xF102)
+#define    r_reg_r_iqip_wacc_im_16  0xF102
+#define reg_r_iqip_wacc_im_16_pos 0
+#define reg_r_iqip_wacc_im_16_len 1
+#define reg_r_iqip_wacc_im_16_lsb 16
+#define xd_r_reg_r_iqip_out2cacc_re_7_0 (*(volatile byte xdata *) 0xF103)
+#define    r_reg_r_iqip_out2cacc_re_7_0 0xF103
+#define reg_r_iqip_out2cacc_re_7_0_pos 0
+#define reg_r_iqip_out2cacc_re_7_0_len 8
+#define reg_r_iqip_out2cacc_re_7_0_lsb 0
+#define xd_r_reg_r_iqip_out2cacc_re_15_8    (*(volatile byte xdata *) 0xF104)
+#define    r_reg_r_iqip_out2cacc_re_15_8    0xF104
+#define reg_r_iqip_out2cacc_re_15_8_pos 0
+#define reg_r_iqip_out2cacc_re_15_8_len 8
+#define reg_r_iqip_out2cacc_re_15_8_lsb 8
+#define xd_r_reg_r_iqip_out2cacc_re_21_16   (*(volatile byte xdata *) 0xF105)
+#define    r_reg_r_iqip_out2cacc_re_21_16   0xF105
+#define reg_r_iqip_out2cacc_re_21_16_pos 0
+#define reg_r_iqip_out2cacc_re_21_16_len 6
+#define reg_r_iqip_out2cacc_re_21_16_lsb 16
+#define xd_r_reg_r_iqip_out2cacc_im_7_0 (*(volatile byte xdata *) 0xF106)
+#define    r_reg_r_iqip_out2cacc_im_7_0 0xF106
+#define reg_r_iqip_out2cacc_im_7_0_pos 0
+#define reg_r_iqip_out2cacc_im_7_0_len 8
+#define reg_r_iqip_out2cacc_im_7_0_lsb 0
+#define xd_r_reg_r_iqip_out2cacc_im_15_8    (*(volatile byte xdata *) 0xF107)
+#define    r_reg_r_iqip_out2cacc_im_15_8    0xF107
+#define reg_r_iqip_out2cacc_im_15_8_pos 0
+#define reg_r_iqip_out2cacc_im_15_8_len 8
+#define reg_r_iqip_out2cacc_im_15_8_lsb 8
+#define xd_r_reg_r_iqip_out2cacc_im_21_16   (*(volatile byte xdata *) 0xF108)
+#define    r_reg_r_iqip_out2cacc_im_21_16   0xF108
+#define reg_r_iqip_out2cacc_im_21_16_pos 0
+#define reg_r_iqip_out2cacc_im_21_16_len 6
+#define reg_r_iqip_out2cacc_im_21_16_lsb 16
+#define xd_p_reg_mccid_ccif0_scstrobe   (*(volatile byte xdata *) 0xF109)
+#define    p_reg_mccid_ccif0_scstrobe   0xF109
+#define reg_mccid_ccif0_scstrobe_pos 0
+#define reg_mccid_ccif0_scstrobe_len 7
+#define reg_mccid_ccif0_scstrobe_lsb 0
+#define xd_p_reg_mccid_cciftrigger  (*(volatile byte xdata *) 0xF10A)
+#define    p_reg_mccid_cciftrigger  0xF10A
+#define reg_mccid_cciftrigger_pos 0
+#define reg_mccid_cciftrigger_len 1
+#define reg_mccid_cciftrigger_lsb 0
+#define xd_p_reg_mccid_ccif1_scstrobe   (*(volatile byte xdata *) 0xF10B)
+#define    p_reg_mccid_ccif1_scstrobe   0xF10B
+#define reg_mccid_ccif1_scstrobe_pos 0
+#define reg_mccid_ccif1_scstrobe_len 7
+#define reg_mccid_ccif1_scstrobe_lsb 0
+#define xd_p_reg_mccid_ccif0_fcwccif_7_0    (*(volatile byte xdata *) 0xF10E)
+#define    p_reg_mccid_ccif0_fcwccif_7_0    0xF10E
+#define reg_mccid_ccif0_fcwccif_7_0_pos 0
+#define reg_mccid_ccif0_fcwccif_7_0_len 8
+#define reg_mccid_ccif0_fcwccif_7_0_lsb 0
+#define xd_p_reg_mccid_ccif0_fcwccif_13_8   (*(volatile byte xdata *) 0xF10F)
+#define    p_reg_mccid_ccif0_fcwccif_13_8   0xF10F
+#define reg_mccid_ccif0_fcwccif_13_8_pos 0
+#define reg_mccid_ccif0_fcwccif_13_8_len 6
+#define reg_mccid_ccif0_fcwccif_13_8_lsb 8
+#define xd_p_reg_mccid_ccif0_state  (*(volatile byte xdata *) 0xF110)
+#define    p_reg_mccid_ccif0_state  0xF110
+#define reg_mccid_ccif0_state_pos 0
+#define reg_mccid_ccif0_state_len 1
+#define reg_mccid_ccif0_state_lsb 0
+#define xd_p_reg_mccid_ccif0_acistate   (*(volatile byte xdata *) 0xF111)
+#define    p_reg_mccid_ccif0_acistate   0xF111
+#define reg_mccid_ccif0_acistate_pos 0
+#define reg_mccid_ccif0_acistate_len 1
+#define reg_mccid_ccif0_acistate_lsb 0
+#define xd_p_reg_mccid_ccif1_fcwccif_7_0    (*(volatile byte xdata *) 0xF112)
+#define    p_reg_mccid_ccif1_fcwccif_7_0    0xF112
+#define reg_mccid_ccif1_fcwccif_7_0_pos 0
+#define reg_mccid_ccif1_fcwccif_7_0_len 8
+#define reg_mccid_ccif1_fcwccif_7_0_lsb 0
+#define xd_p_reg_mccid_ccif1_fcwccif_13_8   (*(volatile byte xdata *) 0xF113)
+#define    p_reg_mccid_ccif1_fcwccif_13_8   0xF113
+#define reg_mccid_ccif1_fcwccif_13_8_pos 0
+#define reg_mccid_ccif1_fcwccif_13_8_len 6
+#define reg_mccid_ccif1_fcwccif_13_8_lsb 8
+#define xd_p_reg_mccid_ccif1_state  (*(volatile byte xdata *) 0xF114)
+#define    p_reg_mccid_ccif1_state  0xF114
+#define reg_mccid_ccif1_state_pos 0
+#define reg_mccid_ccif1_state_len 1
+#define reg_mccid_ccif1_state_lsb 0
+#define xd_p_reg_mccid_ccif1_acistate   (*(volatile byte xdata *) 0xF115)
+#define    p_reg_mccid_ccif1_acistate   0xF115
+#define reg_mccid_ccif1_acistate_pos 0
+#define reg_mccid_ccif1_acistate_len 1
+#define reg_mccid_ccif1_acistate_lsb 0
+#define xd_r_reg_r_acif_saturate    (*(volatile byte xdata *) 0xF117)
+#define    r_reg_r_acif_saturate    0xF117
+#define reg_r_acif_saturate_pos 0
+#define reg_r_acif_saturate_len 8
+#define reg_r_acif_saturate_lsb 0
+#define xd_p_reg_tmr_timer0_threshold_7_0   (*(volatile byte xdata *) 0xF118)
+#define    p_reg_tmr_timer0_threshold_7_0   0xF118
+#define reg_tmr_timer0_threshold_7_0_pos 0
+#define reg_tmr_timer0_threshold_7_0_len 8
+#define reg_tmr_timer0_threshold_7_0_lsb 0
+#define xd_p_reg_tmr_timer0_threshold_15_8  (*(volatile byte xdata *) 0xF119)
+#define    p_reg_tmr_timer0_threshold_15_8  0xF119
+#define reg_tmr_timer0_threshold_15_8_pos 0
+#define reg_tmr_timer0_threshold_15_8_len 8
+#define reg_tmr_timer0_threshold_15_8_lsb 8
+#define xd_p_reg_tmr_timer0_enable  (*(volatile byte xdata *) 0xF11A)
+#define    p_reg_tmr_timer0_enable  0xF11A
+#define reg_tmr_timer0_enable_pos 0
+#define reg_tmr_timer0_enable_len 1
+#define reg_tmr_timer0_enable_lsb 0
+#define xd_p_reg_tmr_timer0_clk_sel (*(volatile byte xdata *) 0xF11B)
+#define    p_reg_tmr_timer0_clk_sel 0xF11B
+#define reg_tmr_timer0_clk_sel_pos 0
+#define reg_tmr_timer0_clk_sel_len 1
+#define reg_tmr_timer0_clk_sel_lsb 0
+#define xd_p_reg_tmr_timer0_int (*(volatile byte xdata *) 0xF11C)
+#define    p_reg_tmr_timer0_int 0xF11C
+#define reg_tmr_timer0_int_pos 0
+#define reg_tmr_timer0_int_len 1
+#define reg_tmr_timer0_int_lsb 0
+#define xd_p_reg_tmr_timer0_rst (*(volatile byte xdata *) 0xF11D)
+#define    p_reg_tmr_timer0_rst 0xF11D
+#define reg_tmr_timer0_rst_pos 0
+#define reg_tmr_timer0_rst_len 1
+#define reg_tmr_timer0_rst_lsb 0
+#define xd_r_reg_tmr_timer0_count_7_0   (*(volatile byte xdata *) 0xF11E)
+#define    r_reg_tmr_timer0_count_7_0   0xF11E
+#define reg_tmr_timer0_count_7_0_pos 0
+#define reg_tmr_timer0_count_7_0_len 8
+#define reg_tmr_timer0_count_7_0_lsb 0
+#define xd_r_reg_tmr_timer0_count_15_8  (*(volatile byte xdata *) 0xF11F)
+#define    r_reg_tmr_timer0_count_15_8  0xF11F
+#define reg_tmr_timer0_count_15_8_pos 0
+#define reg_tmr_timer0_count_15_8_len 8
+#define reg_tmr_timer0_count_15_8_lsb 8
+#define xd_p_reg_suspend    (*(volatile byte xdata *) 0xF120)
+#define    p_reg_suspend    0xF120
+#define reg_suspend_pos 0
+#define reg_suspend_len 1
+#define reg_suspend_lsb 0
+#define xd_p_reg_suspend_rdy    (*(volatile byte xdata *) 0xF121)
+#define    p_reg_suspend_rdy    0xF121
+#define reg_suspend_rdy_pos 0
+#define reg_suspend_rdy_len 1
+#define reg_suspend_rdy_lsb 0
+#define xd_p_reg_resume (*(volatile byte xdata *) 0xF122)
+#define    p_reg_resume 0xF122
+#define reg_resume_pos 0
+#define reg_resume_len 1
+#define reg_resume_lsb 0
+#define xd_p_reg_resume_rdy (*(volatile byte xdata *) 0xF123)
+#define    p_reg_resume_rdy 0xF123
+#define reg_resume_rdy_pos 0
+#define reg_resume_rdy_len 1
+#define reg_resume_rdy_lsb 0
+#define xd_p_reg_gp_trigger (*(volatile byte xdata *) 0xF124)
+#define    p_reg_gp_trigger 0xF124
+#define reg_gp_trigger_pos 0
+#define reg_gp_trigger_len 1
+#define reg_gp_trigger_lsb 0
+#define xd_p_reg_trigger_sel    (*(volatile byte xdata *) 0xF125)
+#define    p_reg_trigger_sel    0xF125
+#define reg_trigger_sel_pos 0
+#define reg_trigger_sel_len 2
+#define reg_trigger_sel_lsb 0
+#define xd_p_reg_debug_ofdm (*(volatile byte xdata *) 0xF126)
+#define    p_reg_debug_ofdm 0xF126
+#define reg_debug_ofdm_pos 0
+#define reg_debug_ofdm_len 2
+#define reg_debug_ofdm_lsb 0
+#define xd_p_reg_trigger_module_sel (*(volatile byte xdata *) 0xF127)
+#define    p_reg_trigger_module_sel 0xF127
+#define reg_trigger_module_sel_pos 0
+#define reg_trigger_module_sel_len 6
+#define reg_trigger_module_sel_lsb 0
+#define xd_p_reg_trigger_set_sel    (*(volatile byte xdata *) 0xF128)
+#define    p_reg_trigger_set_sel    0xF128
+#define reg_trigger_set_sel_pos 0
+#define reg_trigger_set_sel_len 6
+#define reg_trigger_set_sel_lsb 0
+#define xd_p_reg_fw_int_mask_n  (*(volatile byte xdata *) 0xF129)
+#define    p_reg_fw_int_mask_n  0xF129
+#define reg_fw_int_mask_n_pos 0
+#define reg_fw_int_mask_n_len 1
+#define reg_fw_int_mask_n_lsb 0
+#define xd_p_reg_dioif_rst  (*(volatile byte xdata *) 0xF12A)
+#define    p_reg_dioif_rst  0xF12A
+#define reg_dioif_rst_pos 0
+#define reg_dioif_rst_len 1
+#define reg_dioif_rst_lsb 0
+#define xd_p_reg_debug_group    (*(volatile byte xdata *) 0xF12B)
+#define    p_reg_debug_group    0xF12B
+#define reg_debug_group_pos 0
+#define reg_debug_group_len 4
+#define reg_debug_group_lsb 0
+#define xd_p_reg_odbg_clk_sel   (*(volatile byte xdata *) 0xF12C)
+#define    p_reg_odbg_clk_sel   0xF12C
+#define reg_odbg_clk_sel_pos 0
+#define reg_odbg_clk_sel_len 3
+#define reg_odbg_clk_sel_lsb 0
+#define xd_p_reg_p_ccif_shift_fre   (*(volatile byte xdata *) 0xF12F)
+#define    p_reg_p_ccif_shift_fre   0xF12F
+#define reg_p_ccif_shift_fre_pos 0
+#define reg_p_ccif_shift_fre_len 1
+#define reg_p_ccif_shift_fre_lsb 0
+#define xd_p_reg_p_ccif_bandwidth_factor    (*(volatile byte xdata *) 0xF130)
+#define    p_reg_p_ccif_bandwidth_factor    0xF130
+#define reg_p_ccif_bandwidth_factor_pos 0
+#define reg_p_ccif_bandwidth_factor_len 3
+#define reg_p_ccif_bandwidth_factor_lsb 0
+#define xd_p_reg_ccif_rst   (*(volatile byte xdata *) 0xF131)
+#define    p_reg_ccif_rst   0xF131
+#define reg_ccif_rst_pos 0
+#define reg_ccif_rst_len 1
+#define reg_ccif_rst_lsb 0
+#define xd_p_reg_p_ccif_min_bandwidth   (*(volatile byte xdata *) 0xF132)
+#define    p_reg_p_ccif_min_bandwidth   0xF132
+#define reg_p_ccif_min_bandwidth_pos 0
+#define reg_p_ccif_min_bandwidth_len 7
+#define reg_p_ccif_min_bandwidth_lsb 0
+#define xd_p_reg_ccif_bq0_state (*(volatile byte xdata *) 0xF133)
+#define    p_reg_ccif_bq0_state 0xF133
+#define reg_ccif_bq0_state_pos 0
+#define reg_ccif_bq0_state_len 1
+#define reg_ccif_bq0_state_lsb 0
+#define xd_p_reg_ccif_bq0_outputscaling (*(volatile byte xdata *) 0xF134)
+#define    p_reg_ccif_bq0_outputscaling 0xF134
+#define reg_ccif_bq0_outputscaling_pos 0
+#define reg_ccif_bq0_outputscaling_len 5
+#define reg_ccif_bq0_outputscaling_lsb 0
+#define xd_p_reg_ccif_bq1_state (*(volatile byte xdata *) 0xF135)
+#define    p_reg_ccif_bq1_state 0xF135
+#define reg_ccif_bq1_state_pos 0
+#define reg_ccif_bq1_state_len 1
+#define reg_ccif_bq1_state_lsb 0
+#define xd_p_reg_ccif_bq1_outputscaling (*(volatile byte xdata *) 0xF136)
+#define    p_reg_ccif_bq1_outputscaling 0xF136
+#define reg_ccif_bq1_outputscaling_pos 0
+#define reg_ccif_bq1_outputscaling_len 5
+#define reg_ccif_bq1_outputscaling_lsb 0
+#define xd_p_reg_ccif_bq0_a1_7_0    (*(volatile byte xdata *) 0xF137)
+#define    p_reg_ccif_bq0_a1_7_0    0xF137
+#define reg_ccif_bq0_a1_7_0_pos 0
+#define reg_ccif_bq0_a1_7_0_len 8
+#define reg_ccif_bq0_a1_7_0_lsb 0
+#define xd_p_reg_ccif_bq0_a1_13_8   (*(volatile byte xdata *) 0xF138)
+#define    p_reg_ccif_bq0_a1_13_8   0xF138
+#define reg_ccif_bq0_a1_13_8_pos 0
+#define reg_ccif_bq0_a1_13_8_len 6
+#define reg_ccif_bq0_a1_13_8_lsb 8
+#define xd_p_reg_ccif_bq1_a1_7_0    (*(volatile byte xdata *) 0xF139)
+#define    p_reg_ccif_bq1_a1_7_0    0xF139
+#define reg_ccif_bq1_a1_7_0_pos 0
+#define reg_ccif_bq1_a1_7_0_len 8
+#define reg_ccif_bq1_a1_7_0_lsb 0
+#define xd_p_reg_ccif_bq1_a1_13_8   (*(volatile byte xdata *) 0xF13A)
+#define    p_reg_ccif_bq1_a1_13_8   0xF13A
+#define reg_ccif_bq1_a1_13_8_pos 0
+#define reg_ccif_bq1_a1_13_8_len 6
+#define reg_ccif_bq1_a1_13_8_lsb 8
+#define xd_p_reg_ccif_bq0_b1_7_0    (*(volatile byte xdata *) 0xF13B)
+#define    p_reg_ccif_bq0_b1_7_0    0xF13B
+#define reg_ccif_bq0_b1_7_0_pos 0
+#define reg_ccif_bq0_b1_7_0_len 8
+#define reg_ccif_bq0_b1_7_0_lsb 0
+#define xd_p_reg_ccif_bq0_b1_13_8   (*(volatile byte xdata *) 0xF13C)
+#define    p_reg_ccif_bq0_b1_13_8   0xF13C
+#define reg_ccif_bq0_b1_13_8_pos 0
+#define reg_ccif_bq0_b1_13_8_len 6
+#define reg_ccif_bq0_b1_13_8_lsb 8
+#define xd_p_reg_ccif_bq1_b1_7_0    (*(volatile byte xdata *) 0xF13D)
+#define    p_reg_ccif_bq1_b1_7_0    0xF13D
+#define reg_ccif_bq1_b1_7_0_pos 0
+#define reg_ccif_bq1_b1_7_0_len 8
+#define reg_ccif_bq1_b1_7_0_lsb 0
+#define xd_p_reg_ccif_bq1_b1_13_8   (*(volatile byte xdata *) 0xF13E)
+#define    p_reg_ccif_bq1_b1_13_8   0xF13E
+#define reg_ccif_bq1_b1_13_8_pos 0
+#define reg_ccif_bq1_b1_13_8_len 6
+#define reg_ccif_bq1_b1_13_8_lsb 8
+#define xd_p_reg_ccif_bq0_b2_7_0    (*(volatile byte xdata *) 0xF13F)
+#define    p_reg_ccif_bq0_b2_7_0    0xF13F
+#define reg_ccif_bq0_b2_7_0_pos 0
+#define reg_ccif_bq0_b2_7_0_len 8
+#define reg_ccif_bq0_b2_7_0_lsb 0
+#define xd_p_reg_ccif_bq0_b2_13_8   (*(volatile byte xdata *) 0xF140)
+#define    p_reg_ccif_bq0_b2_13_8   0xF140
+#define reg_ccif_bq0_b2_13_8_pos 0
+#define reg_ccif_bq0_b2_13_8_len 6
+#define reg_ccif_bq0_b2_13_8_lsb 8
+#define xd_p_reg_ccif_bq1_b2_7_0    (*(volatile byte xdata *) 0xF141)
+#define    p_reg_ccif_bq1_b2_7_0    0xF141
+#define reg_ccif_bq1_b2_7_0_pos 0
+#define reg_ccif_bq1_b2_7_0_len 8
+#define reg_ccif_bq1_b2_7_0_lsb 0
+#define xd_p_reg_ccif_bq1_b2_13_8   (*(volatile byte xdata *) 0xF142)
+#define    p_reg_ccif_bq1_b2_13_8   0xF142
+#define reg_ccif_bq1_b2_13_8_pos 0
+#define reg_ccif_bq1_b2_13_8_len 6
+#define reg_ccif_bq1_b2_13_8_lsb 8
+#define xd_p_reg_ccif_debug_rst (*(volatile byte xdata *) 0xF143)
+#define    p_reg_ccif_debug_rst 0xF143
+#define reg_ccif_debug_rst_pos 0
+#define reg_ccif_debug_rst_len 1
+#define reg_ccif_debug_rst_lsb 0
+#define xd_p_reg_mccid_defaultccifscstrobe  (*(volatile byte xdata *) 0xF144)
+#define    p_reg_mccid_defaultccifscstrobe  0xF144
+#define reg_mccid_defaultccifscstrobe_pos 0
+#define reg_mccid_defaultccifscstrobe_len 7
+#define reg_mccid_defaultccifscstrobe_lsb 0
+#define xd_p_reg_mccid_monitoringaci    (*(volatile byte xdata *) 0xF145)
+#define    p_reg_mccid_monitoringaci    0xF145
+#define reg_mccid_monitoringaci_pos 0
+#define reg_mccid_monitoringaci_len 1
+#define reg_mccid_monitoringaci_lsb 0
+#define xd_p_reg_mccid_ispassmode   (*(volatile byte xdata *) 0xF146)
+#define    p_reg_mccid_ispassmode   0xF146
+#define reg_mccid_ispassmode_pos 0
+#define reg_mccid_ispassmode_len 1
+#define reg_mccid_ispassmode_lsb 0
+#define xd_p_reg_mccid_issteadystatemode    (*(volatile byte xdata *) 0xF147)
+#define    p_reg_mccid_issteadystatemode    0xF147
+#define reg_mccid_issteadystatemode_pos 0
+#define reg_mccid_issteadystatemode_len 1
+#define reg_mccid_issteadystatemode_lsb 0
+#define xd_p_reg_mccid_fixedgaincmp (*(volatile byte xdata *) 0xF148)
+#define    p_reg_mccid_fixedgaincmp 0xF148
+#define reg_mccid_fixedgaincmp_pos 0
+#define reg_mccid_fixedgaincmp_len 1
+#define reg_mccid_fixedgaincmp_lsb 0
+#define xd_p_reg_mccid_misscounter_reset    (*(volatile byte xdata *) 0xF149)
+#define    p_reg_mccid_misscounter_reset    0xF149
+#define reg_mccid_misscounter_reset_pos 0
+#define reg_mccid_misscounter_reset_len 1
+#define reg_mccid_misscounter_reset_lsb 0
+#define xd_p_reg_mccid_acwgcheckcciexist    (*(volatile byte xdata *) 0xF14A)
+#define    p_reg_mccid_acwgcheckcciexist    0xF14A
+#define reg_mccid_acwgcheckcciexist_pos 0
+#define reg_mccid_acwgcheckcciexist_len 1
+#define reg_mccid_acwgcheckcciexist_lsb 0
+#define xd_p_reg_mccid_acidone  (*(volatile byte xdata *) 0xF14B)
+#define    p_reg_mccid_acidone  0xF14B
+#define reg_mccid_acidone_pos 0
+#define reg_mccid_acidone_len 1
+#define reg_mccid_acidone_lsb 0
+#define xd_p_reg_mccid_sxdesiredpower_7_0   (*(volatile byte xdata *) 0xF14C)
+#define    p_reg_mccid_sxdesiredpower_7_0   0xF14C
+#define reg_mccid_sxdesiredpower_7_0_pos 0
+#define reg_mccid_sxdesiredpower_7_0_len 8
+#define reg_mccid_sxdesiredpower_7_0_lsb 0
+#define xd_p_reg_mccid_sxdesiredpower_9_8   (*(volatile byte xdata *) 0xF14D)
+#define    p_reg_mccid_sxdesiredpower_9_8   0xF14D
+#define reg_mccid_sxdesiredpower_9_8_pos 0
+#define reg_mccid_sxdesiredpower_9_8_len 2
+#define reg_mccid_sxdesiredpower_9_8_lsb 8
+#define xd_p_reg_mccid_defaultccitimertriggerno (*(volatile byte xdata *) 0xF14E)
+#define    p_reg_mccid_defaultccitimertriggerno 0xF14E
+#define reg_mccid_defaultccitimertriggerno_pos 0
+#define reg_mccid_defaultccitimertriggerno_len 8
+#define reg_mccid_defaultccitimertriggerno_lsb 0
+#define xd_p_reg_mccid_detectedmaxtonecountshift    (*(volatile byte xdata *) 0xF14F)
+#define    p_reg_mccid_detectedmaxtonecountshift    0xF14F
+#define reg_mccid_detectedmaxtonecountshift_pos 0
+#define reg_mccid_detectedmaxtonecountshift_len 3
+#define reg_mccid_detectedmaxtonecountshift_lsb 0
+#define xd_p_reg_mccid_moveffttoccif_en (*(volatile byte xdata *) 0xF151)
+#define    p_reg_mccid_moveffttoccif_en 0xF151
+#define reg_mccid_moveffttoccif_en_pos 0
+#define reg_mccid_moveffttoccif_en_len 1
+#define reg_mccid_moveffttoccif_en_lsb 0
+#define xd_p_reg_mccid_fftindextobfsfcwfactor_7_0   (*(volatile byte xdata *) 0xF152)
+#define    p_reg_mccid_fftindextobfsfcwfactor_7_0   0xF152
+#define reg_mccid_fftindextobfsfcwfactor_7_0_pos 0
+#define reg_mccid_fftindextobfsfcwfactor_7_0_len 8
+#define reg_mccid_fftindextobfsfcwfactor_7_0_lsb 0
+#define xd_p_reg_mccid_fftindextobfsfcwfactor_9_8   (*(volatile byte xdata *) 0xF153)
+#define    p_reg_mccid_fftindextobfsfcwfactor_9_8   0xF153
+#define reg_mccid_fftindextobfsfcwfactor_9_8_pos 0
+#define reg_mccid_fftindextobfsfcwfactor_9_8_len 2
+#define reg_mccid_fftindextobfsfcwfactor_9_8_lsb 8
+#define xd_p_reg_mccid_bfsfcwffttoindexfactor_7_0   (*(volatile byte xdata *) 0xF154)
+#define    p_reg_mccid_bfsfcwffttoindexfactor_7_0   0xF154
+#define reg_mccid_bfsfcwffttoindexfactor_7_0_pos 0
+#define reg_mccid_bfsfcwffttoindexfactor_7_0_len 8
+#define reg_mccid_bfsfcwffttoindexfactor_7_0_lsb 0
+#define xd_p_reg_mccid_bfsfcwffttoindexfactor_10_8  (*(volatile byte xdata *) 0xF155)
+#define    p_reg_mccid_bfsfcwffttoindexfactor_10_8  0xF155
+#define reg_mccid_bfsfcwffttoindexfactor_10_8_pos 0
+#define reg_mccid_bfsfcwffttoindexfactor_10_8_len 3
+#define reg_mccid_bfsfcwffttoindexfactor_10_8_lsb 8
+#define xd_p_reg_mccid_detectedaci  (*(volatile byte xdata *) 0xF156)
+#define    p_reg_mccid_detectedaci  0xF156
+#define reg_mccid_detectedaci_pos 0
+#define reg_mccid_detectedaci_len 1
+#define reg_mccid_detectedaci_lsb 0
+#define xd_r_reg_mccid_filter_enable    (*(volatile byte xdata *) 0xF157)
+#define    r_reg_mccid_filter_enable    0xF157
+#define reg_mccid_filter_enable_pos 0
+#define reg_mccid_filter_enable_len 1
+#define reg_mccid_filter_enable_lsb 0
+#define xd_p_reg_mccid_aciscstrobe  (*(volatile byte xdata *) 0xF158)
+#define    p_reg_mccid_aciscstrobe  0xF158
+#define reg_mccid_aciscstrobe_pos 0
+#define reg_mccid_aciscstrobe_len 7
+#define reg_mccid_aciscstrobe_lsb 0
+#define xd_p_reg_mccid_scanningaci  (*(volatile byte xdata *) 0xF159)
+#define    p_reg_mccid_scanningaci  0xF159
+#define reg_mccid_scanningaci_pos 0
+#define reg_mccid_scanningaci_len 1
+#define reg_mccid_scanningaci_lsb 0
+#define xd_p_reg_mccid_windowsizeacciwdcount_7_0    (*(volatile byte xdata *) 0xF15A)
+#define    p_reg_mccid_windowsizeacciwdcount_7_0    0xF15A
+#define reg_mccid_windowsizeacciwdcount_7_0_pos 0
+#define reg_mccid_windowsizeacciwdcount_7_0_len 8
+#define reg_mccid_windowsizeacciwdcount_7_0_lsb 0
+#define xd_p_reg_mccid_windowsizeacciwdcount_12_8   (*(volatile byte xdata *) 0xF15B)
+#define    p_reg_mccid_windowsizeacciwdcount_12_8   0xF15B
+#define reg_mccid_windowsizeacciwdcount_12_8_pos 0
+#define reg_mccid_windowsizeacciwdcount_12_8_len 5
+#define reg_mccid_windowsizeacciwdcount_12_8_lsb 8
+#define xd_p_reg_mccid_scannedacionly   (*(volatile byte xdata *) 0xF15C)
+#define    p_reg_mccid_scannedacionly   0xF15C
+#define reg_mccid_scannedacionly_pos 0
+#define reg_mccid_scannedacionly_len 1
+#define reg_mccid_scannedacionly_lsb 0
+#define xd_p_reg_mccid_scfactor (*(volatile byte xdata *) 0xF15D)
+#define    p_reg_mccid_scfactor 0xF15D
+#define reg_mccid_scfactor_pos 0
+#define reg_mccid_scfactor_len 5
+#define reg_mccid_scfactor_lsb 0
+#define xd_p_reg_mccid_defaultevaluatingbandwidthfactor (*(volatile byte xdata *) 0xF15E)
+#define    p_reg_mccid_defaultevaluatingbandwidthfactor 0xF15E
+#define reg_mccid_defaultevaluatingbandwidthfactor_pos 0
+#define reg_mccid_defaultevaluatingbandwidthfactor_len 3
+#define reg_mccid_defaultevaluatingbandwidthfactor_lsb 0
+#define xd_p_reg_mccid_defaultacipowerlevel (*(volatile byte xdata *) 0xF15F)
+#define    p_reg_mccid_defaultacipowerlevel 0xF15F
+#define reg_mccid_defaultacipowerlevel_pos 0
+#define reg_mccid_defaultacipowerlevel_len 3
+#define reg_mccid_defaultacipowerlevel_lsb 0
+#define xd_r_reg_mccid_outputdagc1gain_7_0  (*(volatile byte xdata *) 0xF160)
+#define    r_reg_mccid_outputdagc1gain_7_0  0xF160
+#define reg_mccid_outputdagc1gain_7_0_pos 0
+#define reg_mccid_outputdagc1gain_7_0_len 8
+#define reg_mccid_outputdagc1gain_7_0_lsb 0
+#define xd_r_reg_mccid_outputdagc1gain_9_8  (*(volatile byte xdata *) 0xF161)
+#define    r_reg_mccid_outputdagc1gain_9_8  0xF161
+#define reg_mccid_outputdagc1gain_9_8_pos 0
+#define reg_mccid_outputdagc1gain_9_8_len 2
+#define reg_mccid_outputdagc1gain_9_8_lsb 8
+#define xd_r_reg_mccid_outputdagc1gainshift (*(volatile byte xdata *) 0xF162)
+#define    r_reg_mccid_outputdagc1gainshift 0xF162
+#define reg_mccid_outputdagc1gainshift_pos 0
+#define reg_mccid_outputdagc1gainshift_len 4
+#define reg_mccid_outputdagc1gainshift_lsb 0
+#define xd_p_reg_mccid_defaultacwgcheckccipowerlevel    (*(volatile byte xdata *) 0xF163)
+#define    p_reg_mccid_defaultacwgcheckccipowerlevel    0xF163
+#define reg_mccid_defaultacwgcheckccipowerlevel_pos 0
+#define reg_mccid_defaultacwgcheckccipowerlevel_len 3
+#define reg_mccid_defaultacwgcheckccipowerlevel_lsb 0
+#define xd_p_reg_mccid_ccipowerlevelfactor  (*(volatile byte xdata *) 0xF166)
+#define    p_reg_mccid_ccipowerlevelfactor  0xF166
+#define reg_mccid_ccipowerlevelfactor_pos 0
+#define reg_mccid_ccipowerlevelfactor_len 3
+#define reg_mccid_ccipowerlevelfactor_lsb 0
+#define xd_p_reg_mccid_scstrobesearchingrange   (*(volatile byte xdata *) 0xF167)
+#define    p_reg_mccid_scstrobesearchingrange   0xF167
+#define reg_mccid_scstrobesearchingrange_pos 0
+#define reg_mccid_scstrobesearchingrange_len 8
+#define reg_mccid_scstrobesearchingrange_lsb 0
+#define xd_p_reg_mccid_searchingno  (*(volatile byte xdata *) 0xF168)
+#define    p_reg_mccid_searchingno  0xF168
+#define reg_mccid_searchingno_pos 0
+#define reg_mccid_searchingno_len 6
+#define reg_mccid_searchingno_lsb 0
+#define xd_p_reg_mccid_scannedacifrequencyresolution    (*(volatile byte xdata *) 0xF169)
+#define    p_reg_mccid_scannedacifrequencyresolution    0xF169
+#define reg_mccid_scannedacifrequencyresolution_pos 0
+#define reg_mccid_scannedacifrequencyresolution_len 4
+#define reg_mccid_scannedacifrequencyresolution_lsb 0
+#define xd_p_reg_mccid_fft0_maskmaxtoneindex_7_0    (*(volatile byte xdata *) 0xF16A)
+#define    p_reg_mccid_fft0_maskmaxtoneindex_7_0    0xF16A
+#define reg_mccid_fft0_maskmaxtoneindex_7_0_pos 0
+#define reg_mccid_fft0_maskmaxtoneindex_7_0_len 8
+#define reg_mccid_fft0_maskmaxtoneindex_7_0_lsb 0
+#define xd_p_reg_mccid_fft0_maskmaxtoneindex_12_8   (*(volatile byte xdata *) 0xF16B)
+#define    p_reg_mccid_fft0_maskmaxtoneindex_12_8   0xF16B
+#define reg_mccid_fft0_maskmaxtoneindex_12_8_pos 0
+#define reg_mccid_fft0_maskmaxtoneindex_12_8_len 5
+#define reg_mccid_fft0_maskmaxtoneindex_12_8_lsb 8
+#define xd_p_reg_mccid_fft0_state   (*(volatile byte xdata *) 0xF16C)
+#define    p_reg_mccid_fft0_state   0xF16C
+#define reg_mccid_fft0_state_pos 0
+#define reg_mccid_fft0_state_len 1
+#define reg_mccid_fft0_state_lsb 0
+#define xd_p_reg_mccid_fft1_state   (*(volatile byte xdata *) 0xF16D)
+#define    p_reg_mccid_fft1_state   0xF16D
+#define reg_mccid_fft1_state_pos 0
+#define reg_mccid_fft1_state_len 1
+#define reg_mccid_fft1_state_lsb 0
+#define xd_p_reg_mccid_fft0_maskmintoneindex_7_0    (*(volatile byte xdata *) 0xF16E)
+#define    p_reg_mccid_fft0_maskmintoneindex_7_0    0xF16E
+#define reg_mccid_fft0_maskmintoneindex_7_0_pos 0
+#define reg_mccid_fft0_maskmintoneindex_7_0_len 8
+#define reg_mccid_fft0_maskmintoneindex_7_0_lsb 0
+#define xd_p_reg_mccid_fft0_maskmintoneindex_12_8   (*(volatile byte xdata *) 0xF16F)
+#define    p_reg_mccid_fft0_maskmintoneindex_12_8   0xF16F
+#define reg_mccid_fft0_maskmintoneindex_12_8_pos 0
+#define reg_mccid_fft0_maskmintoneindex_12_8_len 5
+#define reg_mccid_fft0_maskmintoneindex_12_8_lsb 8
+#define xd_p_reg_mccid_acipowerlevelfactor  (*(volatile byte xdata *) 0xF170)
+#define    p_reg_mccid_acipowerlevelfactor  0xF170
+#define reg_mccid_acipowerlevelfactor_pos 0
+#define reg_mccid_acipowerlevelfactor_len 3
+#define reg_mccid_acipowerlevelfactor_lsb 0
+#define xd_p_reg_mccid_fft1_maskmaxtoneindex_7_0    (*(volatile byte xdata *) 0xF171)
+#define    p_reg_mccid_fft1_maskmaxtoneindex_7_0    0xF171
+#define reg_mccid_fft1_maskmaxtoneindex_7_0_pos 0
+#define reg_mccid_fft1_maskmaxtoneindex_7_0_len 8
+#define reg_mccid_fft1_maskmaxtoneindex_7_0_lsb 0
+#define xd_p_reg_mccid_fft1_maskmaxtoneindex_12_8   (*(volatile byte xdata *) 0xF172)
+#define    p_reg_mccid_fft1_maskmaxtoneindex_12_8   0xF172
+#define reg_mccid_fft1_maskmaxtoneindex_12_8_pos 0
+#define reg_mccid_fft1_maskmaxtoneindex_12_8_len 5
+#define reg_mccid_fft1_maskmaxtoneindex_12_8_lsb 8
+#define xd_p_reg_mccid_fft1_maskmintoneindex_7_0    (*(volatile byte xdata *) 0xF173)
+#define    p_reg_mccid_fft1_maskmintoneindex_7_0    0xF173
+#define reg_mccid_fft1_maskmintoneindex_7_0_pos 0
+#define reg_mccid_fft1_maskmintoneindex_7_0_len 8
+#define reg_mccid_fft1_maskmintoneindex_7_0_lsb 0
+#define xd_p_reg_mccid_fft1_maskmintoneindex_12_8   (*(volatile byte xdata *) 0xF174)
+#define    p_reg_mccid_fft1_maskmintoneindex_12_8   0xF174
+#define reg_mccid_fft1_maskmintoneindex_12_8_pos 0
+#define reg_mccid_fft1_maskmintoneindex_12_8_len 5
+#define reg_mccid_fft1_maskmintoneindex_12_8_lsb 8
+#define xd_p_reg_mccid_reset    (*(volatile byte xdata *) 0xF175)
+#define    p_reg_mccid_reset    0xF175
+#define reg_mccid_reset_pos 0
+#define reg_mccid_reset_len 1
+#define reg_mccid_reset_lsb 0
+#define xd_p_reg_mccid_gaincmpreset (*(volatile byte xdata *) 0xF176)
+#define    p_reg_mccid_gaincmpreset 0xF176
+#define reg_mccid_gaincmpreset_pos 0
+#define reg_mccid_gaincmpreset_len 1
+#define reg_mccid_gaincmpreset_lsb 0
+#define xd_p_reg_mccid_acwgreset    (*(volatile byte xdata *) 0xF177)
+#define    p_reg_mccid_acwgreset    0xF177
+#define reg_mccid_acwgreset_pos 0
+#define reg_mccid_acwgreset_len 1
+#define reg_mccid_acwgreset_lsb 0
+#define xd_p_reg_mccid_ccif0_ofsmstateenable    (*(volatile byte xdata *) 0xF178)
+#define    p_reg_mccid_ccif0_ofsmstateenable    0xF178
+#define reg_mccid_ccif0_ofsmstateenable_pos 0
+#define reg_mccid_ccif0_ofsmstateenable_len 1
+#define reg_mccid_ccif0_ofsmstateenable_lsb 0
+#define xd_p_reg_mccid_ccif1_ofsmstateenable    (*(volatile byte xdata *) 0xF179)
+#define    p_reg_mccid_ccif1_ofsmstateenable    0xF179
+#define reg_mccid_ccif1_ofsmstateenable_pos 0
+#define reg_mccid_ccif1_ofsmstateenable_len 1
+#define reg_mccid_ccif1_ofsmstateenable_lsb 0
+#define xd_p_reg_mccid_fft0_ofsmstateenable (*(volatile byte xdata *) 0xF17A)
+#define    p_reg_mccid_fft0_ofsmstateenable 0xF17A
+#define reg_mccid_fft0_ofsmstateenable_pos 0
+#define reg_mccid_fft0_ofsmstateenable_len 1
+#define reg_mccid_fft0_ofsmstateenable_lsb 0
+#define xd_p_reg_mccid_fft1_ofsmstateenable (*(volatile byte xdata *) 0xF17B)
+#define    p_reg_mccid_fft1_ofsmstateenable 0xF17B
+#define reg_mccid_fft1_ofsmstateenable_pos 0
+#define reg_mccid_fft1_ofsmstateenable_len 1
+#define reg_mccid_fft1_ofsmstateenable_lsb 0
+#define xd_p_reg_mccid_fftfiltermaskchange  (*(volatile byte xdata *) 0xF17C)
+#define    p_reg_mccid_fftfiltermaskchange  0xF17C
+#define reg_mccid_fftfiltermaskchange_pos 0
+#define reg_mccid_fftfiltermaskchange_len 1
+#define reg_mccid_fftfiltermaskchange_lsb 0
+#define xd_r_reg_mccid_maxacipowertone_7_0  (*(volatile byte xdata *) 0xF17D)
+#define    r_reg_mccid_maxacipowertone_7_0  0xF17D
+#define reg_mccid_maxacipowertone_7_0_pos 0
+#define reg_mccid_maxacipowertone_7_0_len 8
+#define reg_mccid_maxacipowertone_7_0_lsb 0
+#define xd_r_reg_mccid_maxacipowertone_12_8 (*(volatile byte xdata *) 0xF17E)
+#define    r_reg_mccid_maxacipowertone_12_8 0xF17E
+#define reg_mccid_maxacipowertone_12_8_pos 0
+#define reg_mccid_maxacipowertone_12_8_len 5
+#define reg_mccid_maxacipowertone_12_8_lsb 8
+#define xd_r_reg_mccid_ccidisappear (*(volatile byte xdata *) 0xF17F)
+#define    r_reg_mccid_ccidisappear 0xF17F
+#define reg_mccid_ccidisappear_pos 0
+#define reg_mccid_ccidisappear_len 1
+#define reg_mccid_ccidisappear_lsb 0
+#define xd_r_reg_mccid_ccilocatordone   (*(volatile byte xdata *) 0xF182)
+#define    r_reg_mccid_ccilocatordone   0xF182
+#define reg_mccid_ccilocatordone_pos 0
+#define reg_mccid_ccilocatordone_len 1
+#define reg_mccid_ccilocatordone_lsb 0
+#define xd_p_reg_mccid_enablecciftrigger    (*(volatile byte xdata *) 0xF183)
+#define    p_reg_mccid_enablecciftrigger    0xF183
+#define reg_mccid_enablecciftrigger_pos 0
+#define reg_mccid_enablecciftrigger_len 1
+#define reg_mccid_enablecciftrigger_lsb 0
+#define xd_p_reg_mccid_disableacwglaunchevaluationbandwidthtrigger  (*(volatile byte xdata *) 0xF184)
+#define    p_reg_mccid_disableacwglaunchevaluationbandwidthtrigger  0xF184
+#define reg_mccid_disableacwglaunchevaluationbandwidthtrigger_pos 0
+#define reg_mccid_disableacwglaunchevaluationbandwidthtrigger_len 1
+#define reg_mccid_disableacwglaunchevaluationbandwidthtrigger_lsb 0
+#define xd_p_reg_mccid_control_by_ofsm  (*(volatile byte xdata *) 0xF185)
+#define    p_reg_mccid_control_by_ofsm  0xF185
+#define reg_mccid_control_by_ofsm_pos 0
+#define reg_mccid_control_by_ofsm_len 1
+#define reg_mccid_control_by_ofsm_lsb 0
+#define xd_p_reg_mccid_ofsmcontrolccilocator    (*(volatile byte xdata *) 0xF186)
+#define    p_reg_mccid_ofsmcontrolccilocator    0xF186
+#define reg_mccid_ofsmcontrolccilocator_pos 0
+#define reg_mccid_ofsmcontrolccilocator_len 1
+#define reg_mccid_ofsmcontrolccilocator_lsb 0
+#define xd_p_reg_mccid_disablepotentialccitriggerccilocator (*(volatile byte xdata *) 0xF187)
+#define    p_reg_mccid_disablepotentialccitriggerccilocator 0xF187
+#define reg_mccid_disablepotentialccitriggerccilocator_pos 0
+#define reg_mccid_disablepotentialccitriggerccilocator_len 1
+#define reg_mccid_disablepotentialccitriggerccilocator_lsb 0
+#define xd_p_reg_mccid_ofsmcontrolccitesting    (*(volatile byte xdata *) 0xF188)
+#define    p_reg_mccid_ofsmcontrolccitesting    0xF188
+#define reg_mccid_ofsmcontrolccitesting_pos 0
+#define reg_mccid_ofsmcontrolccitesting_len 1
+#define reg_mccid_ofsmcontrolccitesting_lsb 0
+#define xd_p_reg_mccid_disableccitestingtriggercheckcci (*(volatile byte xdata *) 0xF189)
+#define    p_reg_mccid_disableccitestingtriggercheckcci 0xF189
+#define reg_mccid_disableccitestingtriggercheckcci_pos 0
+#define reg_mccid_disableccitestingtriggercheckcci_len 1
+#define reg_mccid_disableccitestingtriggercheckcci_lsb 0
+#define xd_p_reg_mccid_ofsmcontrolacwgsetccifscstrobe   (*(volatile byte xdata *) 0xF18A)
+#define    p_reg_mccid_ofsmcontrolacwgsetccifscstrobe   0xF18A
+#define reg_mccid_ofsmcontrolacwgsetccifscstrobe_pos 0
+#define reg_mccid_ofsmcontrolacwgsetccifscstrobe_len 1
+#define reg_mccid_ofsmcontrolacwgsetccifscstrobe_lsb 0
+#define xd_p_reg_mccid_disableacwgevaluatingbandwidthtrigger    (*(volatile byte xdata *) 0xF18B)
+#define    p_reg_mccid_disableacwgevaluatingbandwidthtrigger    0xF18B
+#define reg_mccid_disableacwgevaluatingbandwidthtrigger_pos 0
+#define reg_mccid_disableacwgevaluatingbandwidthtrigger_len 1
+#define reg_mccid_disableacwgevaluatingbandwidthtrigger_lsb 0
+#define xd_p_reg_mccid_ofsmcontrolevaluatingbandwidth   (*(volatile byte xdata *) 0xF18C)
+#define    p_reg_mccid_ofsmcontrolevaluatingbandwidth   0xF18C
+#define reg_mccid_ofsmcontrolevaluatingbandwidth_pos 0
+#define reg_mccid_ofsmcontrolevaluatingbandwidth_len 1
+#define reg_mccid_ofsmcontrolevaluatingbandwidth_lsb 0
+#define xd_p_reg_mccid_ofsmcontrolscanningaci   (*(volatile byte xdata *) 0xF18D)
+#define    p_reg_mccid_ofsmcontrolscanningaci   0xF18D
+#define reg_mccid_ofsmcontrolscanningaci_pos 0
+#define reg_mccid_ofsmcontrolscanningaci_len 1
+#define reg_mccid_ofsmcontrolscanningaci_lsb 0
+#define xd_p_reg_mccid_disablescanningaci   (*(volatile byte xdata *) 0xF18E)
+#define    p_reg_mccid_disablescanningaci   0xF18E
+#define reg_mccid_disablescanningaci_pos 0
+#define reg_mccid_disablescanningaci_len 1
+#define reg_mccid_disablescanningaci_lsb 0
+#define xd_p_reg_mccid_disableacwgccidetecting  (*(volatile byte xdata *) 0xF18F)
+#define    p_reg_mccid_disableacwgccidetecting  0xF18F
+#define reg_mccid_disableacwgccidetecting_pos 0
+#define reg_mccid_disableacwgccidetecting_len 1
+#define reg_mccid_disableacwgccidetecting_lsb 0
+#define xd_p_reg_mccid_ofsmcontrolccitimertrigger   (*(volatile byte xdata *) 0xF190)
+#define    p_reg_mccid_ofsmcontrolccitimertrigger   0xF190
+#define reg_mccid_ofsmcontrolccitimertrigger_pos 0
+#define reg_mccid_ofsmcontrolccitimertrigger_len 1
+#define reg_mccid_ofsmcontrolccitimertrigger_lsb 0
+#define xd_p_reg_mccid_disableccitimertrigger   (*(volatile byte xdata *) 0xF191)
+#define    p_reg_mccid_disableccitimertrigger   0xF191
+#define reg_mccid_disableccitimertrigger_pos 0
+#define reg_mccid_disableccitimertrigger_len 1
+#define reg_mccid_disableccitimertrigger_lsb 0
+#define xd_p_reg_mccid_ofsmdisableccitriggercounting    (*(volatile byte xdata *) 0xF192)
+#define    p_reg_mccid_ofsmdisableccitriggercounting    0xF192
+#define reg_mccid_ofsmdisableccitriggercounting_pos 0
+#define reg_mccid_ofsmdisableccitriggercounting_len 1
+#define reg_mccid_ofsmdisableccitriggercounting_lsb 0
+#define xd_p_reg_mccid_enableccifilteraci   (*(volatile byte xdata *) 0xF193)
+#define    p_reg_mccid_enableccifilteraci   0xF193
+#define reg_mccid_enableccifilteraci_pos 0
+#define reg_mccid_enableccifilteraci_len 1
+#define reg_mccid_enableccifilteraci_lsb 0
+#define xd_p_reg_mccid_scannedfcwbfs_7_0    (*(volatile byte xdata *) 0xF194)
+#define    p_reg_mccid_scannedfcwbfs_7_0    0xF194
+#define reg_mccid_scannedfcwbfs_7_0_pos 0
+#define reg_mccid_scannedfcwbfs_7_0_len 8
+#define reg_mccid_scannedfcwbfs_7_0_lsb 0
+#define xd_p_reg_mccid_scannedfcwbfs_13_8   (*(volatile byte xdata *) 0xF195)
+#define    p_reg_mccid_scannedfcwbfs_13_8   0xF195
+#define reg_mccid_scannedfcwbfs_13_8_pos 0
+#define reg_mccid_scannedfcwbfs_13_8_len 6
+#define reg_mccid_scannedfcwbfs_13_8_lsb 8
+#define xd_p_reg_mccid_acwgevaluatingbandwidth  (*(volatile byte xdata *) 0xF196)
+#define    p_reg_mccid_acwgevaluatingbandwidth  0xF196
+#define reg_mccid_acwgevaluatingbandwidth_pos 0
+#define reg_mccid_acwgevaluatingbandwidth_len 1
+#define reg_mccid_acwgevaluatingbandwidth_lsb 0
+#define xd_p_reg_mccid_acwglaunchevaluationbandwidth    (*(volatile byte xdata *) 0xF197)
+#define    p_reg_mccid_acwglaunchevaluationbandwidth    0xF197
+#define reg_mccid_acwglaunchevaluationbandwidth_pos 0
+#define reg_mccid_acwglaunchevaluationbandwidth_len 1
+#define reg_mccid_acwglaunchevaluationbandwidth_lsb 0
+#define xd_p_reg_mccid_scannedcandidate (*(volatile byte xdata *) 0xF198)
+#define    p_reg_mccid_scannedcandidate 0xF198
+#define reg_mccid_scannedcandidate_pos 0
+#define reg_mccid_scannedcandidate_len 3
+#define reg_mccid_scannedcandidate_lsb 0
+#define xd_p_reg_mccid_scstrobesearchingcandidate   (*(volatile byte xdata *) 0xF199)
+#define    p_reg_mccid_scstrobesearchingcandidate   0xF199
+#define reg_mccid_scstrobesearchingcandidate_pos 0
+#define reg_mccid_scstrobesearchingcandidate_len 2
+#define reg_mccid_scstrobesearchingcandidate_lsb 0
+#define xd_p_reg_mccid_potentialcci (*(volatile byte xdata *) 0xF19A)
+#define    p_reg_mccid_potentialcci 0xF19A
+#define reg_mccid_potentialcci_pos 0
+#define reg_mccid_potentialcci_len 1
+#define reg_mccid_potentialcci_lsb 0
+#define xd_p_reg_mccid_cciftimertrigger (*(volatile byte xdata *) 0xF19B)
+#define    p_reg_mccid_cciftimertrigger 0xF19B
+#define reg_mccid_cciftimertrigger_pos 0
+#define reg_mccid_cciftimertrigger_len 1
+#define reg_mccid_cciftimertrigger_lsb 0
+#define xd_p_reg_mccid_ccitesting   (*(volatile byte xdata *) 0xF19C)
+#define    p_reg_mccid_ccitesting   0xF19C
+#define reg_mccid_ccitesting_pos 0
+#define reg_mccid_ccitesting_len 1
+#define reg_mccid_ccitesting_lsb 0
+#define xd_p_reg_mccid_defaultccilocatormissno  (*(volatile byte xdata *) 0xF19D)
+#define    p_reg_mccid_defaultccilocatormissno  0xF19D
+#define reg_mccid_defaultccilocatormissno_pos 0
+#define reg_mccid_defaultccilocatormissno_len 8
+#define reg_mccid_defaultccilocatormissno_lsb 0
+#define xd_p_reg_mccid_dagc1_use_despow (*(volatile byte xdata *) 0xF19E)
+#define    p_reg_mccid_dagc1_use_despow 0xF19E
+#define reg_mccid_dagc1_use_despow_pos 0
+#define reg_mccid_dagc1_use_despow_len 1
+#define reg_mccid_dagc1_use_despow_lsb 0
+#define xd_p_reg_mccid_scannedacifrequencybegin_7_0 (*(volatile byte xdata *) 0xF19F)
+#define    p_reg_mccid_scannedacifrequencybegin_7_0 0xF19F
+#define reg_mccid_scannedacifrequencybegin_7_0_pos 0
+#define reg_mccid_scannedacifrequencybegin_7_0_len 8
+#define reg_mccid_scannedacifrequencybegin_7_0_lsb 0
+#define xd_p_reg_mccid_scannedacifrequencybegin_13_8    (*(volatile byte xdata *) 0xF1A0)
+#define    p_reg_mccid_scannedacifrequencybegin_13_8    0xF1A0
+#define reg_mccid_scannedacifrequencybegin_13_8_pos 0
+#define reg_mccid_scannedacifrequencybegin_13_8_len 6
+#define reg_mccid_scannedacifrequencybegin_13_8_lsb 8
+#define xd_p_reg_mccid_scannedacifrequencyend_7_0   (*(volatile byte xdata *) 0xF1A1)
+#define    p_reg_mccid_scannedacifrequencyend_7_0   0xF1A1
+#define reg_mccid_scannedacifrequencyend_7_0_pos 0
+#define reg_mccid_scannedacifrequencyend_7_0_len 8
+#define reg_mccid_scannedacifrequencyend_7_0_lsb 0
+#define xd_p_reg_mccid_scannedacifrequencyend_13_8  (*(volatile byte xdata *) 0xF1A2)
+#define    p_reg_mccid_scannedacifrequencyend_13_8  0xF1A2
+#define reg_mccid_scannedacifrequencyend_13_8_pos 0
+#define reg_mccid_scannedacifrequencyend_13_8_len 6
+#define reg_mccid_scannedacifrequencyend_13_8_lsb 8
+#define xd_p_reg_bfs_fcw_7_0    (*(volatile byte xdata *) 0xF1A3)
+#define    p_reg_bfs_fcw_7_0    0xF1A3
+#define reg_bfs_fcw_7_0_pos 0
+#define reg_bfs_fcw_7_0_len 8
+#define reg_bfs_fcw_7_0_lsb 0
+#define xd_p_reg_bfs_fcw_15_8   (*(volatile byte xdata *) 0xF1A4)
+#define    p_reg_bfs_fcw_15_8   0xF1A4
+#define reg_bfs_fcw_15_8_pos 0
+#define reg_bfs_fcw_15_8_len 8
+#define reg_bfs_fcw_15_8_lsb 8
+#define xd_p_reg_bfs_fcw_22_16  (*(volatile byte xdata *) 0xF1A5)
+#define    p_reg_bfs_fcw_22_16  0xF1A5
+#define reg_bfs_fcw_22_16_pos 0
+#define reg_bfs_fcw_22_16_len 7
+#define reg_bfs_fcw_22_16_lsb 16
+#define xd_p_reg_cfoe_fcw_inv   (*(volatile byte xdata *) 0xF1A6)
+#define    p_reg_cfoe_fcw_inv   0xF1A6
+#define reg_cfoe_fcw_inv_pos 0
+#define reg_cfoe_fcw_inv_len 1
+#define reg_cfoe_fcw_inv_lsb 0
+#define xd_p_reg_bfs_0if    (*(volatile byte xdata *) 0xF1A7)
+#define    p_reg_bfs_0if    0xF1A7
+#define reg_bfs_0if_pos 0
+#define reg_bfs_0if_len 1
+#define reg_bfs_0if_lsb 0
+#define xd_p_reg_sadc_clk   (*(volatile byte xdata *) 0xF1A9)
+#define    p_reg_sadc_clk   0xF1A9
+#define reg_sadc_clk_pos 0
+#define reg_sadc_clk_len 1
+#define reg_sadc_clk_lsb 0
+#define xd_p_reg_sadc_tx    (*(volatile byte xdata *) 0xF1AA)
+#define    p_reg_sadc_tx    0xF1AA
+#define reg_sadc_tx_pos 0
+#define reg_sadc_tx_len 1
+#define reg_sadc_tx_lsb 0
+#define xd_p_reg_sadc_rx    (*(volatile byte xdata *) 0xF1AB)
+#define    p_reg_sadc_rx    0xF1AB
+#define reg_sadc_rx_pos 0
+#define reg_sadc_rx_len 1
+#define reg_sadc_rx_lsb 0
+#define xd_p_reg_sadc_cs    (*(volatile byte xdata *) 0xF1AC)
+#define    p_reg_sadc_cs    0xF1AC
+#define reg_sadc_cs_pos 0
+#define reg_sadc_cs_len 1
+#define reg_sadc_cs_lsb 0
+#define xd_p_reg_fix_fcw_7_0    (*(volatile byte xdata *) 0xF1AD)
+#define    p_reg_fix_fcw_7_0    0xF1AD
+#define reg_fix_fcw_7_0_pos 0
+#define reg_fix_fcw_7_0_len 8
+#define reg_fix_fcw_7_0_lsb 0
+#define xd_p_reg_fix_fcw_15_8   (*(volatile byte xdata *) 0xF1AE)
+#define    p_reg_fix_fcw_15_8   0xF1AE
+#define reg_fix_fcw_15_8_pos 0
+#define reg_fix_fcw_15_8_len 8
+#define reg_fix_fcw_15_8_lsb 8
+#define xd_p_reg_fix_fcw_22_16  (*(volatile byte xdata *) 0xF1AF)
+#define    p_reg_fix_fcw_22_16  0xF1AF
+#define reg_fix_fcw_22_16_pos 0
+#define reg_fix_fcw_22_16_len 7
+#define reg_fix_fcw_22_16_lsb 16
+#define xd_r_reg_bfs_fcw_offset_7_0 (*(volatile byte xdata *) 0xF1B0)
+#define    r_reg_bfs_fcw_offset_7_0 0xF1B0
+#define reg_bfs_fcw_offset_7_0_pos 0
+#define reg_bfs_fcw_offset_7_0_len 8
+#define reg_bfs_fcw_offset_7_0_lsb 0
+#define xd_r_reg_bfs_fcw_offset_15_8    (*(volatile byte xdata *) 0xF1B1)
+#define    r_reg_bfs_fcw_offset_15_8    0xF1B1
+#define reg_bfs_fcw_offset_15_8_pos 0
+#define reg_bfs_fcw_offset_15_8_len 8
+#define reg_bfs_fcw_offset_15_8_lsb 8
+#define xd_r_reg_bfs_fcw_offset_22_16   (*(volatile byte xdata *) 0xF1B2)
+#define    r_reg_bfs_fcw_offset_22_16   0xF1B2
+#define reg_bfs_fcw_offset_22_16_pos 0
+#define reg_bfs_fcw_offset_22_16_len 7
+#define reg_bfs_fcw_offset_22_16_lsb 16
+#define xd_r_bfs_fcw_q_7_0  (*(volatile byte xdata *) 0xF1B3)
+#define    r_bfs_fcw_q_7_0  0xF1B3
+#define bfs_fcw_q_7_0_pos 0
+#define bfs_fcw_q_7_0_len 8
+#define bfs_fcw_q_7_0_lsb 0
+#define xd_r_bfs_fcw_q_15_8 (*(volatile byte xdata *) 0xF1B4)
+#define    r_bfs_fcw_q_15_8 0xF1B4
+#define bfs_fcw_q_15_8_pos 0
+#define bfs_fcw_q_15_8_len 8
+#define bfs_fcw_q_15_8_lsb 8
+#define xd_r_bfs_fcw_q_22_16    (*(volatile byte xdata *) 0xF1B5)
+#define    r_bfs_fcw_q_22_16    0xF1B5
+#define bfs_fcw_q_22_16_pos 0
+#define bfs_fcw_q_22_16_len 7
+#define bfs_fcw_q_22_16_lsb 16
+#define xd_p_reg_dagc3_use_despow   (*(volatile byte xdata *) 0xF1B6)
+#define    p_reg_dagc3_use_despow   0xF1B6
+#define reg_dagc3_use_despow_pos 0
+#define reg_dagc3_use_despow_len 1
+#define reg_dagc3_use_despow_lsb 0
+#define xd_p_reg_dagc3_log_2_accumulate (*(volatile byte xdata *) 0xF1B7)
+#define    p_reg_dagc3_log_2_accumulate 0xF1B7
+#define reg_dagc3_log_2_accumulate_pos 0
+#define reg_dagc3_log_2_accumulate_len 5
+#define reg_dagc3_log_2_accumulate_lsb 0
+#define xd_p_reg_dagc3_desired_level_7_0    (*(volatile byte xdata *) 0xF1BC)
+#define    p_reg_dagc3_desired_level_7_0    0xF1BC
+#define reg_dagc3_desired_level_7_0_pos 0
+#define reg_dagc3_desired_level_7_0_len 8
+#define reg_dagc3_desired_level_7_0_lsb 0
+#define xd_p_reg_dagc3_desired_level_8  (*(volatile byte xdata *) 0xF1BD)
+#define    p_reg_dagc3_desired_level_8  0xF1BD
+#define reg_dagc3_desired_level_8_pos 0
+#define reg_dagc3_desired_level_8_len 1
+#define reg_dagc3_desired_level_8_lsb 8
+#define xd_p_reg_dagc3_apply_delay  (*(volatile byte xdata *) 0xF1BE)
+#define    p_reg_dagc3_apply_delay  0xF1BE
+#define reg_dagc3_apply_delay_pos 0
+#define reg_dagc3_apply_delay_len 7
+#define reg_dagc3_apply_delay_lsb 0
+#define xd_p_reg_dagc3_bp_scale (*(volatile byte xdata *) 0xF1BF)
+#define    p_reg_dagc3_bp_scale 0xF1BF
+#define reg_dagc3_bp_scale_pos 0
+#define reg_dagc3_bp_scale_len 3
+#define reg_dagc3_bp_scale_lsb 0
+#define xd_p_reg_dagc3_in_sat_cnt_7_0   (*(volatile byte xdata *) 0xF1C0)
+#define    p_reg_dagc3_in_sat_cnt_7_0   0xF1C0
+#define reg_dagc3_in_sat_cnt_7_0_pos 0
+#define reg_dagc3_in_sat_cnt_7_0_len 8
+#define reg_dagc3_in_sat_cnt_7_0_lsb 0
+#define xd_p_reg_dagc3_in_sat_cnt_15_8  (*(volatile byte xdata *) 0xF1C1)
+#define    p_reg_dagc3_in_sat_cnt_15_8  0xF1C1
+#define reg_dagc3_in_sat_cnt_15_8_pos 0
+#define reg_dagc3_in_sat_cnt_15_8_len 8
+#define reg_dagc3_in_sat_cnt_15_8_lsb 8
+#define xd_p_reg_dagc3_in_sat_cnt_23_16 (*(volatile byte xdata *) 0xF1C2)
+#define    p_reg_dagc3_in_sat_cnt_23_16 0xF1C2
+#define reg_dagc3_in_sat_cnt_23_16_pos 0
+#define reg_dagc3_in_sat_cnt_23_16_len 8
+#define reg_dagc3_in_sat_cnt_23_16_lsb 16
+#define xd_p_reg_dagc3_in_sat_cnt_31_24 (*(volatile byte xdata *) 0xF1C3)
+#define    p_reg_dagc3_in_sat_cnt_31_24 0xF1C3
+#define reg_dagc3_in_sat_cnt_31_24_pos 0
+#define reg_dagc3_in_sat_cnt_31_24_len 8
+#define reg_dagc3_in_sat_cnt_31_24_lsb 24
+#define xd_p_reg_dagc3_out_sat_cnt_7_0  (*(volatile byte xdata *) 0xF1C4)
+#define    p_reg_dagc3_out_sat_cnt_7_0  0xF1C4
+#define reg_dagc3_out_sat_cnt_7_0_pos 0
+#define reg_dagc3_out_sat_cnt_7_0_len 8
+#define reg_dagc3_out_sat_cnt_7_0_lsb 0
+#define xd_p_reg_dagc3_out_sat_cnt_15_8 (*(volatile byte xdata *) 0xF1C5)
+#define    p_reg_dagc3_out_sat_cnt_15_8 0xF1C5
+#define reg_dagc3_out_sat_cnt_15_8_pos 0
+#define reg_dagc3_out_sat_cnt_15_8_len 8
+#define reg_dagc3_out_sat_cnt_15_8_lsb 8
+#define xd_p_reg_dagc3_out_sat_cnt_23_16    (*(volatile byte xdata *) 0xF1C6)
+#define    p_reg_dagc3_out_sat_cnt_23_16    0xF1C6
+#define reg_dagc3_out_sat_cnt_23_16_pos 0
+#define reg_dagc3_out_sat_cnt_23_16_len 8
+#define reg_dagc3_out_sat_cnt_23_16_lsb 16
+#define xd_p_reg_dagc3_out_sat_cnt_31_24    (*(volatile byte xdata *) 0xF1C7)
+#define    p_reg_dagc3_out_sat_cnt_31_24    0xF1C7
+#define reg_dagc3_out_sat_cnt_31_24_pos 0
+#define reg_dagc3_out_sat_cnt_31_24_len 8
+#define reg_dagc3_out_sat_cnt_31_24_lsb 24
+#define xd_r_bfs_dagc3_multiplier_7_0   (*(volatile byte xdata *) 0xF1C8)
+#define    r_bfs_dagc3_multiplier_7_0   0xF1C8
+#define bfs_dagc3_multiplier_7_0_pos 0
+#define bfs_dagc3_multiplier_7_0_len 8
+#define bfs_dagc3_multiplier_7_0_lsb 0
+#define xd_r_bfs_dagc3_multiplier_15_8  (*(volatile byte xdata *) 0xF1C9)
+#define    r_bfs_dagc3_multiplier_15_8  0xF1C9
+#define bfs_dagc3_multiplier_15_8_pos 0
+#define bfs_dagc3_multiplier_15_8_len 8
+#define bfs_dagc3_multiplier_15_8_lsb 8
+#define xd_r_bfs_dagc3_right_shift_bits (*(volatile byte xdata *) 0xF1CA)
+#define    r_bfs_dagc3_right_shift_bits 0xF1CA
+#define bfs_dagc3_right_shift_bits_pos 0
+#define bfs_dagc3_right_shift_bits_len 4
+#define bfs_dagc3_right_shift_bits_lsb 0
+#define xd_p_reg_dagc3_fixed_gain_7_0   (*(volatile byte xdata *) 0xF1CB)
+#define    p_reg_dagc3_fixed_gain_7_0   0xF1CB
+#define reg_dagc3_fixed_gain_7_0_pos 0
+#define reg_dagc3_fixed_gain_7_0_len 8
+#define reg_dagc3_fixed_gain_7_0_lsb 0
+#define xd_p_reg_dagc3_fixed_gain_11_8  (*(volatile byte xdata *) 0xF1CC)
+#define    p_reg_dagc3_fixed_gain_11_8  0xF1CC
+#define reg_dagc3_fixed_gain_11_8_pos 0
+#define reg_dagc3_fixed_gain_11_8_len 4
+#define reg_dagc3_fixed_gain_11_8_lsb 8
+#define xd_p_reg_f_adc_7_0  (*(volatile byte xdata *) 0xF1CD)
+#define    p_reg_f_adc_7_0  0xF1CD
+#define reg_f_adc_7_0_pos 0
+#define reg_f_adc_7_0_len 8
+#define reg_f_adc_7_0_lsb 0
+#define xd_p_reg_f_adc_15_8 (*(volatile byte xdata *) 0xF1CE)
+#define    p_reg_f_adc_15_8 0xF1CE
+#define reg_f_adc_15_8_pos 0
+#define reg_f_adc_15_8_len 8
+#define reg_f_adc_15_8_lsb 8
+#define xd_p_reg_f_adc_23_16    (*(volatile byte xdata *) 0xF1CF)
+#define    p_reg_f_adc_23_16    0xF1CF
+#define reg_f_adc_23_16_pos 0
+#define reg_f_adc_23_16_len 8
+#define reg_f_adc_23_16_lsb 16
+#define xd_p_reg_fste_frac_step_size_7_0    (*(volatile byte xdata *) 0xF1D0)
+#define    p_reg_fste_frac_step_size_7_0    0xF1D0
+#define reg_fste_frac_step_size_7_0_pos 0
+#define reg_fste_frac_step_size_7_0_len 8
+#define reg_fste_frac_step_size_7_0_lsb 0
+#define xd_p_reg_fste_frac_step_size_15_8   (*(volatile byte xdata *) 0xF1D1)
+#define    p_reg_fste_frac_step_size_15_8   0xF1D1
+#define reg_fste_frac_step_size_15_8_pos 0
+#define reg_fste_frac_step_size_15_8_len 8
+#define reg_fste_frac_step_size_15_8_lsb 8
+#define xd_p_reg_fste_frac_step_size_19_16  (*(volatile byte xdata *) 0xF1D2)
+#define    p_reg_fste_frac_step_size_19_16  0xF1D2
+#define reg_fste_frac_step_size_19_16_pos 0
+#define reg_fste_frac_step_size_19_16_len 4
+#define reg_fste_frac_step_size_19_16_lsb 16
+#define xd_r_intp_mu_7_0    (*(volatile byte xdata *) 0xF1D3)
+#define    r_intp_mu_7_0    0xF1D3
+#define intp_mu_7_0_pos 0
+#define intp_mu_7_0_len 8
+#define intp_mu_7_0_lsb 0
+#define xd_r_intp_mu_15_8   (*(volatile byte xdata *) 0xF1D4)
+#define    r_intp_mu_15_8   0xF1D4
+#define intp_mu_15_8_pos 0
+#define intp_mu_15_8_len 8
+#define intp_mu_15_8_lsb 8
+#define xd_r_intp_mu_23_16  (*(volatile byte xdata *) 0xF1D5)
+#define    r_intp_mu_23_16  0xF1D5
+#define intp_mu_23_16_pos 0
+#define intp_mu_23_16_len 8
+#define intp_mu_23_16_lsb 16
+#define xd_r_intp_mu_25_24  (*(volatile byte xdata *) 0xF1D6)
+#define    r_intp_mu_25_24  0xF1D6
+#define intp_mu_25_24_pos 0
+#define intp_mu_25_24_len 2
+#define intp_mu_25_24_lsb 24
+#define xd_p_intp_muq_7_0   (*(volatile byte xdata *) 0xF1D7)
+#define    p_intp_muq_7_0   0xF1D7
+#define intp_muq_7_0_pos 0
+#define intp_muq_7_0_len 8
+#define intp_muq_7_0_lsb 0
+#define xd_p_intp_muq_15_8  (*(volatile byte xdata *) 0xF1D8)
+#define    p_intp_muq_15_8  0xF1D8
+#define intp_muq_15_8_pos 0
+#define intp_muq_15_8_len 8
+#define intp_muq_15_8_lsb 8
+#define xd_p_intp_muq_23_16 (*(volatile byte xdata *) 0xF1D9)
+#define    p_intp_muq_23_16 0xF1D9
+#define intp_muq_23_16_pos 0
+#define intp_muq_23_16_len 8
+#define intp_muq_23_16_lsb 16
+#define xd_p_reg_sfoe_inv   (*(volatile byte xdata *) 0xF1DA)
+#define    p_reg_sfoe_inv   0xF1DA
+#define reg_sfoe_inv_pos 0
+#define reg_sfoe_inv_len 1
+#define reg_sfoe_inv_lsb 0
+#define xd_p_intp_ext_en    (*(volatile byte xdata *) 0xF1DB)
+#define    p_intp_ext_en    0xF1DB
+#define intp_ext_en_pos 0
+#define intp_ext_en_len 1
+#define intp_ext_en_lsb 0
+#define xd_r_intp_ext_done  (*(volatile byte xdata *) 0xF1DC)
+#define    r_intp_ext_done  0xF1DC
+#define intp_ext_done_pos 0
+#define intp_ext_done_len 1
+#define intp_ext_done_lsb 0
+#define xd_p_intp_ext_in_7_0    (*(volatile byte xdata *) 0xF1DD)
+#define    p_intp_ext_in_7_0    0xF1DD
+#define intp_ext_in_7_0_pos 0
+#define intp_ext_in_7_0_len 8
+#define intp_ext_in_7_0_lsb 0
+#define xd_p_intp_ext_in_15_8   (*(volatile byte xdata *) 0xF1DE)
+#define    p_intp_ext_in_15_8   0xF1DE
+#define intp_ext_in_15_8_pos 0
+#define intp_ext_in_15_8_len 8
+#define intp_ext_in_15_8_lsb 8
+#define xd_p_intp_ext_in_23_16  (*(volatile byte xdata *) 0xF1DF)
+#define    p_intp_ext_in_23_16  0xF1DF
+#define intp_ext_in_23_16_pos 0
+#define intp_ext_in_23_16_len 8
+#define intp_ext_in_23_16_lsb 16
+#define xd_p_intp_ext_in_25_24  (*(volatile byte xdata *) 0xF1E0)
+#define    p_intp_ext_in_25_24  0xF1E0
+#define intp_ext_in_25_24_pos 0
+#define intp_ext_in_25_24_len 2
+#define intp_ext_in_25_24_lsb 24
+#define xd_r_intp_ext_out_7_0   (*(volatile byte xdata *) 0xF1E1)
+#define    r_intp_ext_out_7_0   0xF1E1
+#define intp_ext_out_7_0_pos 0
+#define intp_ext_out_7_0_len 8
+#define intp_ext_out_7_0_lsb 0
+#define xd_r_intp_ext_out_15_8  (*(volatile byte xdata *) 0xF1E2)
+#define    r_intp_ext_out_15_8  0xF1E2
+#define intp_ext_out_15_8_pos 0
+#define intp_ext_out_15_8_len 8
+#define intp_ext_out_15_8_lsb 8
+#define xd_r_intp_ext_out_23_16 (*(volatile byte xdata *) 0xF1E3)
+#define    r_intp_ext_out_23_16 0xF1E3
+#define intp_ext_out_23_16_pos 0
+#define intp_ext_out_23_16_len 8
+#define intp_ext_out_23_16_lsb 16
+#define xd_r_intp_ext_out_28_24 (*(volatile byte xdata *) 0xF1E4)
+#define    r_intp_ext_out_28_24 0xF1E4
+#define intp_ext_out_28_24_pos 0
+#define intp_ext_out_28_24_len 5
+#define intp_ext_out_28_24_lsb 24
+#define xd_p_reg_agc_rst    (*(volatile byte xdata *) 0xF1E5)
+#define    p_reg_agc_rst    0xF1E5
+#define reg_agc_rst_pos 0
+#define reg_agc_rst_len 1
+#define reg_agc_rst_lsb 0
+#define xd_p_rf_agc_en  (*(volatile byte xdata *) 0xF1E6)
+#define    p_rf_agc_en  0xF1E6
+#define rf_agc_en_pos 0
+#define rf_agc_en_len 1
+#define rf_agc_en_lsb 0
+#define xd_p_agc_lock   (*(volatile byte xdata *) 0xF1E7)
+#define    p_agc_lock   0xF1E7
+#define agc_lock_pos 0
+#define agc_lock_len 1
+#define agc_lock_lsb 0
+#define xd_p_reg_tinr_rst   (*(volatile byte xdata *) 0xF1E8)
+#define    p_reg_tinr_rst   0xF1E8
+#define reg_tinr_rst_pos 0
+#define reg_tinr_rst_len 1
+#define reg_tinr_rst_lsb 0
+#define xd_p_reg_tinr_en    (*(volatile byte xdata *) 0xF1E9)
+#define    p_reg_tinr_en    0xF1E9
+#define reg_tinr_en_pos 0
+#define reg_tinr_en_len 1
+#define reg_tinr_en_lsb 0
+#define xd_p_reg_bfs_en (*(volatile byte xdata *) 0xF1EA)
+#define    p_reg_bfs_en 0xF1EA
+#define reg_bfs_en_pos 0
+#define reg_bfs_en_len 1
+#define reg_bfs_en_lsb 0
+#define xd_p_reg_bfs_rst    (*(volatile byte xdata *) 0xF1EB)
+#define    p_reg_bfs_rst    0xF1EB
+#define reg_bfs_rst_pos 0
+#define reg_bfs_rst_len 1
+#define reg_bfs_rst_lsb 0
+#define xd_p_reg_bfs_byp    (*(volatile byte xdata *) 0xF1EC)
+#define    p_reg_bfs_byp    0xF1EC
+#define reg_bfs_byp_pos 0
+#define reg_bfs_byp_len 1
+#define reg_bfs_byp_lsb 0
+#define xd_p_intp_en    (*(volatile byte xdata *) 0xF1EF)
+#define    p_intp_en    0xF1EF
+#define intp_en_pos 0
+#define intp_en_len 1
+#define intp_en_lsb 0
+#define xd_p_intp_rst   (*(volatile byte xdata *) 0xF1F0)
+#define    p_intp_rst   0xF1F0
+#define intp_rst_pos 0
+#define intp_rst_len 1
+#define intp_rst_lsb 0
+#define xd_p_reg_p_acif_en  (*(volatile byte xdata *) 0xF1F2)
+#define    p_reg_p_acif_en  0xF1F2
+#define reg_p_acif_en_pos 0
+#define reg_p_acif_en_len 1
+#define reg_p_acif_en_lsb 0
+#define xd_p_reg_p_acif_rst (*(volatile byte xdata *) 0xF1F3)
+#define    p_reg_p_acif_rst 0xF1F3
+#define reg_p_acif_rst_pos 0
+#define reg_p_acif_rst_len 1
+#define reg_p_acif_rst_lsb 0
+#define xd_p_reg_p_acif_byp (*(volatile byte xdata *) 0xF1F4)
+#define    p_reg_p_acif_byp 0xF1F4
+#define reg_p_acif_byp_pos 0
+#define reg_p_acif_byp_len 1
+#define reg_p_acif_byp_lsb 0
+#define xd_p_dagc2_rst  (*(volatile byte xdata *) 0xF1F6)
+#define    p_dagc2_rst  0xF1F6
+#define dagc2_rst_pos 0
+#define dagc2_rst_len 1
+#define dagc2_rst_lsb 0
+#define xd_p_dagc2_en   (*(volatile byte xdata *) 0xF1F7)
+#define    p_dagc2_en   0xF1F7
+#define dagc2_en_pos 0
+#define dagc2_en_len 1
+#define dagc2_en_lsb 0
+#define xd_p_dagc2_mode (*(volatile byte xdata *) 0xF1F8)
+#define    p_dagc2_mode 0xF1F8
+#define dagc2_mode_pos 0
+#define dagc2_mode_len 2
+#define dagc2_mode_lsb 0
+#define xd_p_dagc2_done (*(volatile byte xdata *) 0xF1F9)
+#define    p_dagc2_done 0xF1F9
+#define dagc2_done_pos 0
+#define dagc2_done_len 1
+#define dagc2_done_lsb 0
+#define xd_p_dagc3_rst  (*(volatile byte xdata *) 0xF1FA)
+#define    p_dagc3_rst  0xF1FA
+#define dagc3_rst_pos 0
+#define dagc3_rst_len 1
+#define dagc3_rst_lsb 0
+#define xd_p_dagc3_en   (*(volatile byte xdata *) 0xF1FB)
+#define    p_dagc3_en   0xF1FB
+#define dagc3_en_pos 0
+#define dagc3_en_len 1
+#define dagc3_en_lsb 0
+#define xd_p_dagc3_mode (*(volatile byte xdata *) 0xF1FC)
+#define    p_dagc3_mode 0xF1FC
+#define dagc3_mode_pos 0
+#define dagc3_mode_len 2
+#define dagc3_mode_lsb 0
+#define xd_p_dagc3_done (*(volatile byte xdata *) 0xF1FD)
+#define    p_dagc3_done 0xF1FD
+#define dagc3_done_pos 0
+#define dagc3_done_len 1
+#define dagc3_done_lsb 0
+#define xd_p_reg_dagc2_desired_level_7_0    (*(volatile byte xdata *) 0xF202)
+#define    p_reg_dagc2_desired_level_7_0    0xF202
+#define reg_dagc2_desired_level_7_0_pos 0
+#define reg_dagc2_desired_level_7_0_len 8
+#define reg_dagc2_desired_level_7_0_lsb 0
+#define xd_p_reg_dagc2_desired_level_8  (*(volatile byte xdata *) 0xF203)
+#define    p_reg_dagc2_desired_level_8  0xF203
+#define reg_dagc2_desired_level_8_pos 0
+#define reg_dagc2_desired_level_8_len 1
+#define reg_dagc2_desired_level_8_lsb 8
+#define xd_p_reg_dagc2_apply_delay  (*(volatile byte xdata *) 0xF204)
+#define    p_reg_dagc2_apply_delay  0xF204
+#define reg_dagc2_apply_delay_pos 0
+#define reg_dagc2_apply_delay_len 7
+#define reg_dagc2_apply_delay_lsb 0
+#define xd_p_reg_dagc2_bypass_scale_ctl (*(volatile byte xdata *) 0xF205)
+#define    p_reg_dagc2_bypass_scale_ctl 0xF205
+#define reg_dagc2_bypass_scale_ctl_pos 0
+#define reg_dagc2_bypass_scale_ctl_len 3
+#define reg_dagc2_bypass_scale_ctl_lsb 0
+#define xd_p_reg_dagc2_programmable_shift2  (*(volatile byte xdata *) 0xF206)
+#define    p_reg_dagc2_programmable_shift2  0xF206
+#define reg_dagc2_programmable_shift2_pos 0
+#define reg_dagc2_programmable_shift2_len 8
+#define reg_dagc2_programmable_shift2_lsb 0
+#define xd_p_reg_dagc2_in_sat_cnt_7_0   (*(volatile byte xdata *) 0xF207)
+#define    p_reg_dagc2_in_sat_cnt_7_0   0xF207
+#define reg_dagc2_in_sat_cnt_7_0_pos 0
+#define reg_dagc2_in_sat_cnt_7_0_len 8
+#define reg_dagc2_in_sat_cnt_7_0_lsb 0
+#define xd_p_reg_dagc2_in_sat_cnt_15_8  (*(volatile byte xdata *) 0xF208)
+#define    p_reg_dagc2_in_sat_cnt_15_8  0xF208
+#define reg_dagc2_in_sat_cnt_15_8_pos 0
+#define reg_dagc2_in_sat_cnt_15_8_len 8
+#define reg_dagc2_in_sat_cnt_15_8_lsb 8
+#define xd_p_reg_dagc2_in_sat_cnt_23_16 (*(volatile byte xdata *) 0xF209)
+#define    p_reg_dagc2_in_sat_cnt_23_16 0xF209
+#define reg_dagc2_in_sat_cnt_23_16_pos 0
+#define reg_dagc2_in_sat_cnt_23_16_len 8
+#define reg_dagc2_in_sat_cnt_23_16_lsb 16
+#define xd_p_reg_dagc2_in_sat_cnt_31_24 (*(volatile byte xdata *) 0xF20A)
+#define    p_reg_dagc2_in_sat_cnt_31_24 0xF20A
+#define reg_dagc2_in_sat_cnt_31_24_pos 0
+#define reg_dagc2_in_sat_cnt_31_24_len 8
+#define reg_dagc2_in_sat_cnt_31_24_lsb 24
+#define xd_p_reg_dagc2_out_sat_cnt_7_0  (*(volatile byte xdata *) 0xF20B)
+#define    p_reg_dagc2_out_sat_cnt_7_0  0xF20B
+#define reg_dagc2_out_sat_cnt_7_0_pos 0
+#define reg_dagc2_out_sat_cnt_7_0_len 8
+#define reg_dagc2_out_sat_cnt_7_0_lsb 0
+#define xd_p_reg_dagc2_out_sat_cnt_15_8 (*(volatile byte xdata *) 0xF20C)
+#define    p_reg_dagc2_out_sat_cnt_15_8 0xF20C
+#define reg_dagc2_out_sat_cnt_15_8_pos 0
+#define reg_dagc2_out_sat_cnt_15_8_len 8
+#define reg_dagc2_out_sat_cnt_15_8_lsb 8
+#define xd_p_reg_dagc2_out_sat_cnt_23_16    (*(volatile byte xdata *) 0xF20D)
+#define    p_reg_dagc2_out_sat_cnt_23_16    0xF20D
+#define reg_dagc2_out_sat_cnt_23_16_pos 0
+#define reg_dagc2_out_sat_cnt_23_16_len 8
+#define reg_dagc2_out_sat_cnt_23_16_lsb 16
+#define xd_p_reg_dagc2_out_sat_cnt_31_24    (*(volatile byte xdata *) 0xF20E)
+#define    p_reg_dagc2_out_sat_cnt_31_24    0xF20E
+#define reg_dagc2_out_sat_cnt_31_24_pos 0
+#define reg_dagc2_out_sat_cnt_31_24_len 8
+#define reg_dagc2_out_sat_cnt_31_24_lsb 24
+#define xd_r_reg_dagc2_multiplier_7_0   (*(volatile byte xdata *) 0xF20F)
+#define    r_reg_dagc2_multiplier_7_0   0xF20F
+#define reg_dagc2_multiplier_7_0_pos 0
+#define reg_dagc2_multiplier_7_0_len 8
+#define reg_dagc2_multiplier_7_0_lsb 0
+#define xd_r_reg_dagc2_multiplier_15_8  (*(volatile byte xdata *) 0xF210)
+#define    r_reg_dagc2_multiplier_15_8  0xF210
+#define reg_dagc2_multiplier_15_8_pos 0
+#define reg_dagc2_multiplier_15_8_len 8
+#define reg_dagc2_multiplier_15_8_lsb 8
+#define xd_r_reg_dagc2_right_shift_bits (*(volatile byte xdata *) 0xF211)
+#define    r_reg_dagc2_right_shift_bits 0xF211
+#define reg_dagc2_right_shift_bits_pos 0
+#define reg_dagc2_right_shift_bits_len 4
+#define reg_dagc2_right_shift_bits_lsb 0
+#define xd_p_reg_dagc2_smbuf_err    (*(volatile byte xdata *) 0xF212)
+#define    p_reg_dagc2_smbuf_err    0xF212
+#define reg_dagc2_smbuf_err_pos 0
+#define reg_dagc2_smbuf_err_len 1
+#define reg_dagc2_smbuf_err_lsb 0
+#define xd_p_reg_dagc2_cplxconj (*(volatile byte xdata *) 0xF213)
+#define    p_reg_dagc2_cplxconj 0xF213
+#define reg_dagc2_cplxconj_pos 0
+#define reg_dagc2_cplxconj_len 1
+#define reg_dagc2_cplxconj_lsb 0
+#define xd_p_reg_dagc2_use_despow   (*(volatile byte xdata *) 0xF214)
+#define    p_reg_dagc2_use_despow   0xF214
+#define reg_dagc2_use_despow_pos 0
+#define reg_dagc2_use_despow_len 1
+#define reg_dagc2_use_despow_lsb 0
+#define xd_p_reg_dagc2_log_2_accumulate (*(volatile byte xdata *) 0xF215)
+#define    p_reg_dagc2_log_2_accumulate 0xF215
+#define reg_dagc2_log_2_accumulate_pos 0
+#define reg_dagc2_log_2_accumulate_len 5
+#define reg_dagc2_log_2_accumulate_lsb 0
+#define xd_r_dagc2_dca_gain (*(volatile byte xdata *) 0xF216)
+#define    r_dagc2_dca_gain 0xF216
+#define dagc2_dca_gain_pos 0
+#define dagc2_dca_gain_len 8
+#define dagc2_dca_gain_lsb 0
+#define xd_p_reg_dca_gain_offset    (*(volatile byte xdata *) 0xF217)
+#define    p_reg_dca_gain_offset    0xF217
+#define reg_dca_gain_offset_pos 0
+#define reg_dca_gain_offset_len 8
+#define reg_dca_gain_offset_lsb 0
+#define xd_p_reg_dagc2_FG_mode  (*(volatile byte xdata *) 0xF218)
+#define    p_reg_dagc2_FG_mode  0xF218
+#define reg_dagc2_FG_mode_pos 0
+#define reg_dagc2_FG_mode_len 1
+#define reg_dagc2_FG_mode_lsb 0
+#define xd_p_reg_dagc2_fixed_gain_7_0   (*(volatile byte xdata *) 0xF219)
+#define    p_reg_dagc2_fixed_gain_7_0   0xF219
+#define reg_dagc2_fixed_gain_7_0_pos 0
+#define reg_dagc2_fixed_gain_7_0_len 8
+#define reg_dagc2_fixed_gain_7_0_lsb 0
+#define xd_p_reg_dagc2_fixed_gain_11_8  (*(volatile byte xdata *) 0xF21A)
+#define    p_reg_dagc2_fixed_gain_11_8  0xF21A
+#define reg_dagc2_fixed_gain_11_8_pos 0
+#define reg_dagc2_fixed_gain_11_8_len 4
+#define reg_dagc2_fixed_gain_11_8_lsb 8
+#define xd_p_reg_td_debug_7_0   (*(volatile byte xdata *) 0xF21B)
+#define    p_reg_td_debug_7_0   0xF21B
+#define reg_td_debug_7_0_pos 0
+#define reg_td_debug_7_0_len 8
+#define reg_td_debug_7_0_lsb 0
+#define xd_p_reg_td_debug_15_8  (*(volatile byte xdata *) 0xF21C)
+#define    p_reg_td_debug_15_8  0xF21C
+#define reg_td_debug_15_8_pos 0
+#define reg_td_debug_15_8_len 8
+#define reg_td_debug_15_8_lsb 8
+#define xd_p_reg_td_debug_23_16 (*(volatile byte xdata *) 0xF21D)
+#define    p_reg_td_debug_23_16 0xF21D
+#define reg_td_debug_23_16_pos 0
+#define reg_td_debug_23_16_len 8
+#define reg_td_debug_23_16_lsb 16
+#define xd_p_reg_td_debug_30_24 (*(volatile byte xdata *) 0xF21E)
+#define    p_reg_td_debug_30_24 0xF21E
+#define reg_td_debug_30_24_pos 0
+#define reg_td_debug_30_24_len 7
+#define reg_td_debug_30_24_lsb 24
+#define xd_g_reg_tpsd_txmod (*(volatile byte xdata *) 0xF900)
+#define    g_reg_tpsd_txmod 0xF900
+#define reg_tpsd_txmod_pos 0
+#define reg_tpsd_txmod_len 2
+#define reg_tpsd_txmod_lsb 0
+#define xd_g_reg_tpsd_gi    (*(volatile byte xdata *) 0xF901)
+#define    g_reg_tpsd_gi    0xF901
+#define reg_tpsd_gi_pos 0
+#define reg_tpsd_gi_len 2
+#define reg_tpsd_gi_lsb 0
+#define xd_g_reg_tpsd_hier  (*(volatile byte xdata *) 0xF902)
+#define    g_reg_tpsd_hier  0xF902
+#define reg_tpsd_hier_pos 0
+#define reg_tpsd_hier_len 3
+#define reg_tpsd_hier_lsb 0
+#define xd_g_reg_tpsd_const (*(volatile byte xdata *) 0xF903)
+#define    g_reg_tpsd_const 0xF903
+#define reg_tpsd_const_pos 0
+#define reg_tpsd_const_len 2
+#define reg_tpsd_const_lsb 0
+#define xd_g_reg_bw (*(volatile byte xdata *) 0xF904)
+#define    g_reg_bw 0xF904
+#define reg_bw_pos 0
+#define reg_bw_len 2
+#define reg_bw_lsb 0
+#define xd_g_reg_dec_pri    (*(volatile byte xdata *) 0xF905)
+#define    g_reg_dec_pri    0xF905
+#define reg_dec_pri_pos 0
+#define reg_dec_pri_len 1
+#define reg_dec_pri_lsb 0
+#define xd_g_reg_tpsd_hpcr  (*(volatile byte xdata *) 0xF906)
+#define    g_reg_tpsd_hpcr  0xF906
+#define reg_tpsd_hpcr_pos 0
+#define reg_tpsd_hpcr_len 3
+#define reg_tpsd_hpcr_lsb 0
+#define xd_g_reg_tpsd_lpcr  (*(volatile byte xdata *) 0xF907)
+#define    g_reg_tpsd_lpcr  0xF907
+#define reg_tpsd_lpcr_pos 0
+#define reg_tpsd_lpcr_len 3
+#define reg_tpsd_lpcr_lsb 0
+#define xd_g_reg_tpsd_indep (*(volatile byte xdata *) 0xF908)
+#define    g_reg_tpsd_indep 0xF908
+#define reg_tpsd_indep_pos 0
+#define reg_tpsd_indep_len 1
+#define reg_tpsd_indep_lsb 0
+#define xd_g_reg_tpsd_tslice    (*(volatile byte xdata *) 0xF909)
+#define    g_reg_tpsd_tslice    0xF909
+#define reg_tpsd_tslice_pos 0
+#define reg_tpsd_tslice_len 1
+#define reg_tpsd_tslice_lsb 0
+#define xd_g_reg_tpsd_mpefec    (*(volatile byte xdata *) 0xF90A)
+#define    g_reg_tpsd_mpefec    0xF90A
+#define reg_tpsd_mpefec_pos 0
+#define reg_tpsd_mpefec_len 1
+#define reg_tpsd_mpefec_lsb 0
+#define xd_g_reg_sntc_en    (*(volatile byte xdata *) 0xF90B)
+#define    g_reg_sntc_en    0xF90B
+#define reg_sntc_en_pos 0
+#define reg_sntc_en_len 1
+#define reg_sntc_en_lsb 0
+#define xd_g_reg_intp_sys_div   (*(volatile byte xdata *) 0xF90C)
+#define    g_reg_intp_sys_div   0xF90C
+#define reg_intp_sys_div_pos 0
+#define reg_intp_sys_div_len 1
+#define reg_intp_sys_div_lsb 0
+#define xd_g_reg_clk_sntc_sel   (*(volatile byte xdata *) 0xF90D)
+#define    g_reg_clk_sntc_sel   0xF90D
+#define reg_clk_sntc_sel_pos 0
+#define reg_clk_sntc_sel_len 3
+#define reg_clk_sntc_sel_lsb 0
+#define xd_g_reg_clk_sys40  (*(volatile byte xdata *) 0xF90E)
+#define    g_reg_clk_sys40  0xF90E
+#define reg_clk_sys40_pos 0
+#define reg_clk_sys40_len 1
+#define reg_clk_sys40_lsb 0
+#define xd_g_reg_intp_sys_polarity  (*(volatile byte xdata *) 0xF90F)
+#define    g_reg_intp_sys_polarity  0xF90F
+#define reg_intp_sys_polarity_pos 0
+#define reg_intp_sys_polarity_len 1
+#define reg_intp_sys_polarity_lsb 0
+#define xd_g_reg_intp_sys_sc_7_0    (*(volatile byte xdata *) 0xF910)
+#define    g_reg_intp_sys_sc_7_0    0xF910
+#define reg_intp_sys_sc_7_0_pos 0
+#define reg_intp_sys_sc_7_0_len 8
+#define reg_intp_sys_sc_7_0_lsb 0
+#define xd_g_reg_intp_sys_sc_15_8   (*(volatile byte xdata *) 0xF911)
+#define    g_reg_intp_sys_sc_15_8   0xF911
+#define reg_intp_sys_sc_15_8_pos 0
+#define reg_intp_sys_sc_15_8_len 8
+#define reg_intp_sys_sc_15_8_lsb 8
+#define xd_g_reg_intp_sys_sc_23_16  (*(volatile byte xdata *) 0xF912)
+#define    g_reg_intp_sys_sc_23_16  0xF912
+#define reg_intp_sys_sc_23_16_pos 0
+#define reg_intp_sys_sc_23_16_len 8
+#define reg_intp_sys_sc_23_16_lsb 16
+#define xd_g_reg_intp_sys_sc_26_24  (*(volatile byte xdata *) 0xF913)
+#define    g_reg_intp_sys_sc_26_24  0xF913
+#define reg_intp_sys_sc_26_24_pos 0
+#define reg_intp_sys_sc_26_24_len 3
+#define reg_intp_sys_sc_26_24_lsb 24
+#define xd_g_reg_ofsm_clk   (*(volatile byte xdata *) 0xF914)
+#define    g_reg_ofsm_clk   0xF914
+#define reg_ofsm_clk_pos 0
+#define reg_ofsm_clk_len 3
+#define reg_ofsm_clk_lsb 0
+#define xd_g_reg_fclk_cfg   (*(volatile byte xdata *) 0xF915)
+#define    g_reg_fclk_cfg   0xF915
+#define reg_fclk_cfg_pos 0
+#define reg_fclk_cfg_len 1
+#define reg_fclk_cfg_lsb 0
+#define xd_g_reg_fclk_idi   (*(volatile byte xdata *) 0xF916)
+#define    g_reg_fclk_idi   0xF916
+#define reg_fclk_idi_pos 0
+#define reg_fclk_idi_len 1
+#define reg_fclk_idi_lsb 0
+#define xd_g_reg_fclk_odi   (*(volatile byte xdata *) 0xF917)
+#define    g_reg_fclk_odi   0xF917
+#define reg_fclk_odi_pos 0
+#define reg_fclk_odi_len 1
+#define reg_fclk_odi_lsb 0
+#define xd_g_reg_fclk_rsd   (*(volatile byte xdata *) 0xF918)
+#define    g_reg_fclk_rsd   0xF918
+#define reg_fclk_rsd_pos 0
+#define reg_fclk_rsd_len 1
+#define reg_fclk_rsd_lsb 0
+#define xd_g_reg_fclk_vtb   (*(volatile byte xdata *) 0xF919)
+#define    g_reg_fclk_vtb   0xF919
+#define reg_fclk_vtb_pos 0
+#define reg_fclk_vtb_len 1
+#define reg_fclk_vtb_lsb 0
+#define xd_g_reg_fclk_cste  (*(volatile byte xdata *) 0xF91A)
+#define    g_reg_fclk_cste  0xF91A
+#define reg_fclk_cste_pos 0
+#define reg_fclk_cste_len 1
+#define reg_fclk_cste_lsb 0
+#define xd_g_reg_fclk_mp2if (*(volatile byte xdata *) 0xF91B)
+#define    g_reg_fclk_mp2if 0xF91B
+#define reg_fclk_mp2if_pos 0
+#define reg_fclk_mp2if_len 1
+#define reg_fclk_mp2if_lsb 0
+#define xd_p_reg_adcout_sync    (*(volatile byte xdata *) 0xFA00)
+#define    p_reg_adcout_sync    0xFA00
+#define reg_adcout_sync_pos 0
+#define reg_adcout_sync_len 1
+#define reg_adcout_sync_lsb 0
+#define xd_p_reg_dagc2o_edge1   (*(volatile byte xdata *) 0xFA01)
+#define    p_reg_dagc2o_edge1   0xFA01
+#define reg_dagc2o_edge1_pos 0
+#define reg_dagc2o_edge1_len 1
+#define reg_dagc2o_edge1_lsb 0
+#define xd_p_reg_dagc2o_edge0   (*(volatile byte xdata *) 0xFA02)
+#define    p_reg_dagc2o_edge0   0xFA02
+#define reg_dagc2o_edge0_pos 0
+#define reg_dagc2o_edge0_len 1
+#define reg_dagc2o_edge0_lsb 0
+#define xd_p_reg_second_rom_on  (*(volatile byte xdata *) 0xFA03)
+#define    p_reg_second_rom_on  0xFA03
+#define reg_second_rom_on_pos 0
+#define reg_second_rom_on_len 1
+#define reg_second_rom_on_lsb 0
+#define xd_p_reg_bypass_host2tuner  (*(volatile byte xdata *) 0xFA04)
+#define    p_reg_bypass_host2tuner  0xFA04
+#define reg_bypass_host2tuner_pos 0
+#define reg_bypass_host2tuner_len 1
+#define reg_bypass_host2tuner_lsb 0
+#endif
+// biu_reg.h 6-27-2007
+// gen_biu Ver 1.0 generated by tienchi
+#define xd_p_cfoe_NS_coeff1_7_0 (*(volatile byte xdata *) 0xF400)
+#define    p_cfoe_NS_coeff1_7_0 0xF400
+#define cfoe_NS_coeff1_7_0_pos 0
+#define cfoe_NS_coeff1_7_0_len 8
+#define cfoe_NS_coeff1_7_0_lsb 0
+#define xd_p_cfoe_NS_coeff1_15_8    (*(volatile byte xdata *) 0xF401)
+#define    p_cfoe_NS_coeff1_15_8    0xF401
+#define cfoe_NS_coeff1_15_8_pos 0
+#define cfoe_NS_coeff1_15_8_len 8
+#define cfoe_NS_coeff1_15_8_lsb 8
+#define xd_p_cfoe_NS_coeff1_23_16   (*(volatile byte xdata *) 0xF402)
+#define    p_cfoe_NS_coeff1_23_16   0xF402
+#define cfoe_NS_coeff1_23_16_pos 0
+#define cfoe_NS_coeff1_23_16_len 8
+#define cfoe_NS_coeff1_23_16_lsb 16
+#define xd_p_cfoe_NS_coeff1_25_24   (*(volatile byte xdata *) 0xF403)
+#define    p_cfoe_NS_coeff1_25_24   0xF403
+#define cfoe_NS_coeff1_25_24_pos 0
+#define cfoe_NS_coeff1_25_24_len 2
+#define cfoe_NS_coeff1_25_24_lsb 24
+#define xd_p_cfoe_NS_coeff2_7_0 (*(volatile byte xdata *) 0xF404)
+#define    p_cfoe_NS_coeff2_7_0 0xF404
+#define cfoe_NS_coeff2_7_0_pos 0
+#define cfoe_NS_coeff2_7_0_len 8
+#define cfoe_NS_coeff2_7_0_lsb 0
+#define xd_p_cfoe_NS_coeff2_15_8    (*(volatile byte xdata *) 0xF405)
+#define    p_cfoe_NS_coeff2_15_8    0xF405
+#define cfoe_NS_coeff2_15_8_pos 0
+#define cfoe_NS_coeff2_15_8_len 8
+#define cfoe_NS_coeff2_15_8_lsb 8
+#define xd_p_cfoe_NS_coeff2_23_16   (*(volatile byte xdata *) 0xF406)
+#define    p_cfoe_NS_coeff2_23_16   0xF406
+#define cfoe_NS_coeff2_23_16_pos 0
+#define cfoe_NS_coeff2_23_16_len 8
+#define cfoe_NS_coeff2_23_16_lsb 16
+#define xd_p_cfoe_NS_coeff2_24  (*(volatile byte xdata *) 0xF407)
+#define    p_cfoe_NS_coeff2_24  0xF407
+#define cfoe_NS_coeff2_24_pos 0
+#define cfoe_NS_coeff2_24_len 1
+#define cfoe_NS_coeff2_24_lsb 24
+#define xd_p_cfoe_lf_c1_7_0 (*(volatile byte xdata *) 0xF408)
+#define    p_cfoe_lf_c1_7_0 0xF408
+#define cfoe_lf_c1_7_0_pos 0
+#define cfoe_lf_c1_7_0_len 8
+#define cfoe_lf_c1_7_0_lsb 0
+#define xd_p_cfoe_lf_c1_9_8 (*(volatile byte xdata *) 0xF409)
+#define    p_cfoe_lf_c1_9_8 0xF409
+#define cfoe_lf_c1_9_8_pos 0
+#define cfoe_lf_c1_9_8_len 2
+#define cfoe_lf_c1_9_8_lsb 8
+#define xd_p_cfoe_lf_c2_7_0 (*(volatile byte xdata *) 0xF40A)
+#define    p_cfoe_lf_c2_7_0 0xF40A
+#define cfoe_lf_c2_7_0_pos 0
+#define cfoe_lf_c2_7_0_len 8
+#define cfoe_lf_c2_7_0_lsb 0
+#define xd_p_cfoe_lf_c2_9_8 (*(volatile byte xdata *) 0xF40B)
+#define    p_cfoe_lf_c2_9_8 0xF40B
+#define cfoe_lf_c2_9_8_pos 0
+#define cfoe_lf_c2_9_8_len 2
+#define cfoe_lf_c2_9_8_lsb 8
+#define xd_p_cfoe_ifod_7_0  (*(volatile byte xdata *) 0xF40C)
+#define    p_cfoe_ifod_7_0  0xF40C
+#define cfoe_ifod_7_0_pos 0
+#define cfoe_ifod_7_0_len 8
+#define cfoe_ifod_7_0_lsb 0
+#define xd_p_cfoe_ifod_10_8 (*(volatile byte xdata *) 0xF40D)
+#define    p_cfoe_ifod_10_8 0xF40D
+#define cfoe_ifod_10_8_pos 0
+#define cfoe_ifod_10_8_len 3
+#define cfoe_ifod_10_8_lsb 8
+#define xd_p_cfoe_Divg_ctr_th   (*(volatile byte xdata *) 0xF40E)
+#define    p_cfoe_Divg_ctr_th   0xF40E
+#define cfoe_Divg_ctr_th_pos 0
+#define cfoe_Divg_ctr_th_len 4
+#define cfoe_Divg_ctr_th_lsb 0
+#define xd_p_cfoe_FOT_divg_th   (*(volatile byte xdata *) 0xF40F)
+#define    p_cfoe_FOT_divg_th   0xF40F
+#define cfoe_FOT_divg_th_pos 0
+#define cfoe_FOT_divg_th_len 8
+#define cfoe_FOT_divg_th_lsb 0
+#define xd_p_cfoe_FOT_cnvg_th   (*(volatile byte xdata *) 0xF410)
+#define    p_cfoe_FOT_cnvg_th   0xF410
+#define cfoe_FOT_cnvg_th_pos 0
+#define cfoe_FOT_cnvg_th_len 8
+#define cfoe_FOT_cnvg_th_lsb 0
+#define xd_p_reg_cfoe_offset_7_0    (*(volatile byte xdata *) 0xF411)
+#define    p_reg_cfoe_offset_7_0    0xF411
+#define reg_cfoe_offset_7_0_pos 0
+#define reg_cfoe_offset_7_0_len 8
+#define reg_cfoe_offset_7_0_lsb 0
+#define xd_p_reg_cfoe_offset_10_8   (*(volatile byte xdata *) 0xF412)
+#define    p_reg_cfoe_offset_10_8   0xF412
+#define reg_cfoe_offset_10_8_pos 0
+#define reg_cfoe_offset_10_8_len 3
+#define reg_cfoe_offset_10_8_lsb 8
+#define xd_p_reg_cfoe_ifoe_sign_corr    (*(volatile byte xdata *) 0xF413)
+#define    p_reg_cfoe_ifoe_sign_corr    0xF413
+#define reg_cfoe_ifoe_sign_corr_pos 0
+#define reg_cfoe_ifoe_sign_corr_len 1
+#define reg_cfoe_ifoe_sign_corr_lsb 0
+#define xd_p_cfoe_FOT_pullin_cnt_clr    (*(volatile byte xdata *) 0xF414)
+#define    p_cfoe_FOT_pullin_cnt_clr    0xF414
+#define cfoe_FOT_pullin_cnt_clr_pos 0
+#define cfoe_FOT_pullin_cnt_clr_len 1
+#define cfoe_FOT_pullin_cnt_clr_lsb 0
+#define xd_p_cfoe_FOT_spec_inv  (*(volatile byte xdata *) 0xF415)
+#define    p_cfoe_FOT_spec_inv  0xF415
+#define cfoe_FOT_spec_inv_pos 0
+#define cfoe_FOT_spec_inv_len 1
+#define cfoe_FOT_spec_inv_lsb 0
+#define xd_p_cfoe_FOT_pullin_ctr_th (*(volatile byte xdata *) 0xF416)
+#define    p_cfoe_FOT_pullin_ctr_th 0xF416
+#define cfoe_FOT_pullin_ctr_th_pos 0
+#define cfoe_FOT_pullin_ctr_th_len 4
+#define cfoe_FOT_pullin_ctr_th_lsb 0
+#define xd_p_cfoe_FOT_sf_ctr_th (*(volatile byte xdata *) 0xF417)
+#define    p_cfoe_FOT_sf_ctr_th 0xF417
+#define cfoe_FOT_sf_ctr_th_pos 0
+#define cfoe_FOT_sf_ctr_th_len 4
+#define cfoe_FOT_sf_ctr_th_lsb 0
+#define xd_p_cfoe_FOT_pullin_th (*(volatile byte xdata *) 0xF418)
+#define    p_cfoe_FOT_pullin_th 0xF418
+#define cfoe_FOT_pullin_th_pos 0
+#define cfoe_FOT_pullin_th_len 8
+#define cfoe_FOT_pullin_th_lsb 0
+#define xd_p_cfoe_FOT_kalman_cnt    (*(volatile byte xdata *) 0xF419)
+#define    p_cfoe_FOT_kalman_cnt    0xF419
+#define cfoe_FOT_kalman_cnt_pos 0
+#define cfoe_FOT_kalman_cnt_len 4
+#define cfoe_FOT_kalman_cnt_lsb 0
+#define xd_p_cfoe_FOT_fsm_info  (*(volatile byte xdata *) 0xF41A)
+#define    p_cfoe_FOT_fsm_info  0xF41A
+#define cfoe_FOT_fsm_info_pos 0
+#define cfoe_FOT_fsm_info_len 4
+#define cfoe_FOT_fsm_info_lsb 0
+#define xd_r_cfoe_FOT_pullin_cnt    (*(volatile byte xdata *) 0xF41B)
+#define    r_cfoe_FOT_pullin_cnt    0xF41B
+#define cfoe_FOT_pullin_cnt_pos 0
+#define cfoe_FOT_pullin_cnt_len 4
+#define cfoe_FOT_pullin_cnt_lsb 0
+#define xd_r_cfoe_FOT_sf_cnt    (*(volatile byte xdata *) 0xF41C)
+#define    r_cfoe_FOT_sf_cnt    0xF41C
+#define cfoe_FOT_sf_cnt_pos 0
+#define cfoe_FOT_sf_cnt_len 4
+#define cfoe_FOT_sf_cnt_lsb 0
+#define xd_r_reg_r_cfoe_ifoe_ifo_metric (*(volatile byte xdata *) 0xF41D)
+#define    r_reg_r_cfoe_ifoe_ifo_metric 0xF41D
+#define reg_r_cfoe_ifoe_ifo_metric_pos 0
+#define reg_r_cfoe_ifoe_ifo_metric_len 8
+#define reg_r_cfoe_ifoe_ifo_metric_lsb 0
+#define xd_r_reg_r_cfoe_ifoe_cos2num_7_0    (*(volatile byte xdata *) 0xF41E)
+#define    r_reg_r_cfoe_ifoe_cos2num_7_0    0xF41E
+#define reg_r_cfoe_ifoe_cos2num_7_0_pos 0
+#define reg_r_cfoe_ifoe_cos2num_7_0_len 8
+#define reg_r_cfoe_ifoe_cos2num_7_0_lsb 0
+#define xd_r_reg_r_cfoe_ifoe_cos2num_15_8   (*(volatile byte xdata *) 0xF41F)
+#define    r_reg_r_cfoe_ifoe_cos2num_15_8   0xF41F
+#define reg_r_cfoe_ifoe_cos2num_15_8_pos 0
+#define reg_r_cfoe_ifoe_cos2num_15_8_len 8
+#define reg_r_cfoe_ifoe_cos2num_15_8_lsb 8
+#define xd_r_reg_r_cfoe_ifoe_cos2num_19_16  (*(volatile byte xdata *) 0xF420)
+#define    r_reg_r_cfoe_ifoe_cos2num_19_16  0xF420
+#define reg_r_cfoe_ifoe_cos2num_19_16_pos 0
+#define reg_r_cfoe_ifoe_cos2num_19_16_len 4
+#define reg_r_cfoe_ifoe_cos2num_19_16_lsb 16
+#define xd_p_ste_Nu (*(volatile byte xdata *) 0xF460)
+#define    p_ste_Nu 0xF460
+#define ste_Nu_pos 0
+#define ste_Nu_len 3
+#define ste_Nu_lsb 0
+#define xd_p_ste_GI (*(volatile byte xdata *) 0xF461)
+#define    p_ste_GI 0xF461
+#define ste_GI_pos 0
+#define ste_GI_len 3
+#define ste_GI_lsb 0
+#define xd_p_ste_symbol_num (*(volatile byte xdata *) 0xF463)
+#define    p_ste_symbol_num 0xF463
+#define ste_symbol_num_pos 0
+#define ste_symbol_num_len 3
+#define ste_symbol_num_lsb 0
+#define xd_p_ste_sample_num (*(volatile byte xdata *) 0xF464)
+#define    p_ste_sample_num 0xF464
+#define ste_sample_num_pos 0
+#define ste_sample_num_len 2
+#define ste_sample_num_lsb 0
+#define xd_p_ste_symbol_num_4K  (*(volatile byte xdata *) 0xF465)
+#define    p_ste_symbol_num_4K  0xF465
+#define ste_symbol_num_4K_pos 0
+#define ste_symbol_num_4K_len 3
+#define ste_symbol_num_4K_lsb 0
+#define xd_p_ste_FFT_offset_7_0 (*(volatile byte xdata *) 0xF466)
+#define    p_ste_FFT_offset_7_0 0xF466
+#define ste_FFT_offset_7_0_pos 0
+#define ste_FFT_offset_7_0_len 8
+#define ste_FFT_offset_7_0_lsb 0
+#define xd_p_ste_FFT_offset_13_8    (*(volatile byte xdata *) 0xF467)
+#define    p_ste_FFT_offset_13_8    0xF467
+#define ste_FFT_offset_13_8_pos 0
+#define ste_FFT_offset_13_8_len 6
+#define ste_FFT_offset_13_8_lsb 8
+#define xd_p_ste_sample_num_4K  (*(volatile byte xdata *) 0xF468)
+#define    p_ste_sample_num_4K  0xF468
+#define ste_sample_num_4K_pos 0
+#define ste_sample_num_4K_len 2
+#define ste_sample_num_4K_lsb 0
+#define xd_p_ste_adv_start_7_0  (*(volatile byte xdata *) 0xF469)
+#define    p_ste_adv_start_7_0  0xF469
+#define ste_adv_start_7_0_pos 0
+#define ste_adv_start_7_0_len 8
+#define ste_adv_start_7_0_lsb 0
+#define xd_p_ste_adv_start_10_8 (*(volatile byte xdata *) 0xF46A)
+#define    p_ste_adv_start_10_8 0xF46A
+#define ste_adv_start_10_8_pos 0
+#define ste_adv_start_10_8_len 3
+#define ste_adv_start_10_8_lsb 8
+#define xd_p_ste_symbol_num_8K  (*(volatile byte xdata *) 0xF46B)
+#define    p_ste_symbol_num_8K  0xF46B
+#define ste_symbol_num_8K_pos 0
+#define ste_symbol_num_8K_len 3
+#define ste_symbol_num_8K_lsb 0
+#define xd_p_ste_sample_num_8K  (*(volatile byte xdata *) 0xF46C)
+#define    p_ste_sample_num_8K  0xF46C
+#define ste_sample_num_8K_pos 0
+#define ste_sample_num_8K_len 2
+#define ste_sample_num_8K_lsb 0
+#define xd_p_ste_adv_stop   (*(volatile byte xdata *) 0xF46D)
+#define    p_ste_adv_stop   0xF46D
+#define ste_adv_stop_pos 0
+#define ste_adv_stop_len 8
+#define ste_adv_stop_lsb 0
+#define xd_r_ste_P_value_7_0    (*(volatile byte xdata *) 0xF46E)
+#define    r_ste_P_value_7_0    0xF46E
+#define ste_P_value_7_0_pos 0
+#define ste_P_value_7_0_len 8
+#define ste_P_value_7_0_lsb 0
+#define xd_r_ste_P_value_10_8   (*(volatile byte xdata *) 0xF46F)
+#define    r_ste_P_value_10_8   0xF46F
+#define ste_P_value_10_8_pos 0
+#define ste_P_value_10_8_len 3
+#define ste_P_value_10_8_lsb 8
+#define xd_p_reg_ste_tstmod (*(volatile byte xdata *) 0xF470)
+#define    p_reg_ste_tstmod 0xF470
+#define reg_ste_tstmod_pos 0
+#define reg_ste_tstmod_len 1
+#define reg_ste_tstmod_lsb 0
+#define xd_p_reg_ste_buf_en (*(volatile byte xdata *) 0xF471)
+#define    p_reg_ste_buf_en 0xF471
+#define reg_ste_buf_en_pos 0
+#define reg_ste_buf_en_len 1
+#define reg_ste_buf_en_lsb 0
+#define xd_r_ste_M_value_7_0    (*(volatile byte xdata *) 0xF472)
+#define    r_ste_M_value_7_0    0xF472
+#define ste_M_value_7_0_pos 0
+#define ste_M_value_7_0_len 8
+#define ste_M_value_7_0_lsb 0
+#define xd_r_ste_M_value_10_8   (*(volatile byte xdata *) 0xF473)
+#define    r_ste_M_value_10_8   0xF473
+#define ste_M_value_10_8_pos 0
+#define ste_M_value_10_8_len 3
+#define ste_M_value_10_8_lsb 8
+#define xd_r_ste_H1 (*(volatile byte xdata *) 0xF474)
+#define    r_ste_H1 0xF474
+#define ste_H1_pos 0
+#define ste_H1_len 7
+#define ste_H1_lsb 0
+#define xd_r_ste_H2 (*(volatile byte xdata *) 0xF475)
+#define    r_ste_H2 0xF475
+#define ste_H2_pos 0
+#define ste_H2_len 7
+#define ste_H2_lsb 0
+#define xd_r_ste_H3 (*(volatile byte xdata *) 0xF476)
+#define    r_ste_H3 0xF476
+#define ste_H3_pos 0
+#define ste_H3_len 7
+#define ste_H3_lsb 0
+#define xd_r_ste_H4 (*(volatile byte xdata *) 0xF477)
+#define    r_ste_H4 0xF477
+#define ste_H4_pos 0
+#define ste_H4_len 7
+#define ste_H4_lsb 0
+#define xd_r_ste_Corr_value_I_7_0   (*(volatile byte xdata *) 0xF478)
+#define    r_ste_Corr_value_I_7_0   0xF478
+#define ste_Corr_value_I_7_0_pos 0
+#define ste_Corr_value_I_7_0_len 8
+#define ste_Corr_value_I_7_0_lsb 0
+#define xd_r_ste_Corr_value_I_15_8  (*(volatile byte xdata *) 0xF479)
+#define    r_ste_Corr_value_I_15_8  0xF479
+#define ste_Corr_value_I_15_8_pos 0
+#define ste_Corr_value_I_15_8_len 8
+#define ste_Corr_value_I_15_8_lsb 8
+#define xd_r_ste_Corr_value_I_23_16 (*(volatile byte xdata *) 0xF47A)
+#define    r_ste_Corr_value_I_23_16 0xF47A
+#define ste_Corr_value_I_23_16_pos 0
+#define ste_Corr_value_I_23_16_len 8
+#define ste_Corr_value_I_23_16_lsb 16
+#define xd_r_ste_Corr_value_I_27_24 (*(volatile byte xdata *) 0xF47B)
+#define    r_ste_Corr_value_I_27_24 0xF47B
+#define ste_Corr_value_I_27_24_pos 0
+#define ste_Corr_value_I_27_24_len 4
+#define ste_Corr_value_I_27_24_lsb 24
+#define xd_r_ste_Corr_value_Q_7_0   (*(volatile byte xdata *) 0xF47C)
+#define    r_ste_Corr_value_Q_7_0   0xF47C
+#define ste_Corr_value_Q_7_0_pos 0
+#define ste_Corr_value_Q_7_0_len 8
+#define ste_Corr_value_Q_7_0_lsb 0
+#define xd_r_ste_Corr_value_Q_15_8  (*(volatile byte xdata *) 0xF47D)
+#define    r_ste_Corr_value_Q_15_8  0xF47D
+#define ste_Corr_value_Q_15_8_pos 0
+#define ste_Corr_value_Q_15_8_len 8
+#define ste_Corr_value_Q_15_8_lsb 8
+#define xd_r_ste_Corr_value_Q_23_16 (*(volatile byte xdata *) 0xF47E)
+#define    r_ste_Corr_value_Q_23_16 0xF47E
+#define ste_Corr_value_Q_23_16_pos 0
+#define ste_Corr_value_Q_23_16_len 8
+#define ste_Corr_value_Q_23_16_lsb 16
+#define xd_r_ste_Corr_value_Q_27_24 (*(volatile byte xdata *) 0xF47F)
+#define    r_ste_Corr_value_Q_27_24 0xF47F
+#define ste_Corr_value_Q_27_24_pos 0
+#define ste_Corr_value_Q_27_24_len 4
+#define ste_Corr_value_Q_27_24_lsb 24
+#define xd_r_ste_J_num_7_0  (*(volatile byte xdata *) 0xF480)
+#define    r_ste_J_num_7_0  0xF480
+#define ste_J_num_7_0_pos 0
+#define ste_J_num_7_0_len 8
+#define ste_J_num_7_0_lsb 0
+#define xd_r_ste_J_num_15_8 (*(volatile byte xdata *) 0xF481)
+#define    r_ste_J_num_15_8 0xF481
+#define ste_J_num_15_8_pos 0
+#define ste_J_num_15_8_len 8
+#define ste_J_num_15_8_lsb 8
+#define xd_r_ste_J_num_23_16    (*(volatile byte xdata *) 0xF482)
+#define    r_ste_J_num_23_16    0xF482
+#define ste_J_num_23_16_pos 0
+#define ste_J_num_23_16_len 8
+#define ste_J_num_23_16_lsb 16
+#define xd_r_ste_J_num_31_24    (*(volatile byte xdata *) 0xF483)
+#define    r_ste_J_num_31_24    0xF483
+#define ste_J_num_31_24_pos 0
+#define ste_J_num_31_24_len 8
+#define ste_J_num_31_24_lsb 24
+#define xd_r_ste_J_den_7_0  (*(volatile byte xdata *) 0xF484)
+#define    r_ste_J_den_7_0  0xF484
+#define ste_J_den_7_0_pos 0
+#define ste_J_den_7_0_len 8
+#define ste_J_den_7_0_lsb 0
+#define xd_r_ste_J_den_15_8 (*(volatile byte xdata *) 0xF485)
+#define    r_ste_J_den_15_8 0xF485
+#define ste_J_den_15_8_pos 0
+#define ste_J_den_15_8_len 8
+#define ste_J_den_15_8_lsb 8
+#define xd_r_ste_J_den_18_16    (*(volatile byte xdata *) 0xF486)
+#define    r_ste_J_den_18_16    0xF486
+#define ste_J_den_18_16_pos 0
+#define ste_J_den_18_16_len 3
+#define ste_J_den_18_16_lsb 16
+#define xd_r_ste_Beacon_Indicator   (*(volatile byte xdata *) 0xF488)
+#define    r_ste_Beacon_Indicator   0xF488
+#define ste_Beacon_Indicator_pos 0
+#define ste_Beacon_Indicator_len 1
+#define ste_Beacon_Indicator_lsb 0
+#define xd_p_ste_got_sntc_bcn   (*(volatile byte xdata *) 0xF48B)
+#define    p_ste_got_sntc_bcn   0xF48B
+#define ste_got_sntc_bcn_pos 0
+#define ste_got_sntc_bcn_len 1
+#define ste_got_sntc_bcn_lsb 0
+#define xd_r_tpsd_Frame_Num (*(volatile byte xdata *) 0xF4C0)
+#define    r_tpsd_Frame_Num 0xF4C0
+#define tpsd_Frame_Num_pos 0
+#define tpsd_Frame_Num_len 2
+#define tpsd_Frame_Num_lsb 0
+#define xd_r_tpsd_Constel   (*(volatile byte xdata *) 0xF4C1)
+#define    r_tpsd_Constel   0xF4C1
+#define tpsd_Constel_pos 0
+#define tpsd_Constel_len 2
+#define tpsd_Constel_lsb 0
+#define xd_r_tpsd_GI    (*(volatile byte xdata *) 0xF4C2)
+#define    r_tpsd_GI    0xF4C2
+#define tpsd_GI_pos 0
+#define tpsd_GI_len 2
+#define tpsd_GI_lsb 0
+#define xd_r_tpsd_Mode  (*(volatile byte xdata *) 0xF4C3)
+#define    r_tpsd_Mode  0xF4C3
+#define tpsd_Mode_pos 0
+#define tpsd_Mode_len 2
+#define tpsd_Mode_lsb 0
+#define xd_r_tpsd_CR_HP (*(volatile byte xdata *) 0xF4C4)
+#define    r_tpsd_CR_HP 0xF4C4
+#define tpsd_CR_HP_pos 0
+#define tpsd_CR_HP_len 3
+#define tpsd_CR_HP_lsb 0
+#define xd_r_tpsd_CR_LP (*(volatile byte xdata *) 0xF4C5)
+#define    r_tpsd_CR_LP 0xF4C5
+#define tpsd_CR_LP_pos 0
+#define tpsd_CR_LP_len 3
+#define tpsd_CR_LP_lsb 0
+#define xd_r_tpsd_Hie   (*(volatile byte xdata *) 0xF4C6)
+#define    r_tpsd_Hie   0xF4C6
+#define tpsd_Hie_pos 0
+#define tpsd_Hie_len 3
+#define tpsd_Hie_lsb 0
+#define xd_r_tpsd_Res_Bits  (*(volatile byte xdata *) 0xF4C7)
+#define    r_tpsd_Res_Bits  0xF4C7
+#define tpsd_Res_Bits_pos 0
+#define tpsd_Res_Bits_len 5
+#define tpsd_Res_Bits_lsb 0
+#define xd_r_tpsd_Res_Bits_0    (*(volatile byte xdata *) 0xF4C8)
+#define    r_tpsd_Res_Bits_0    0xF4C8
+#define tpsd_Res_Bits_0_pos 0
+#define tpsd_Res_Bits_0_len 1
+#define tpsd_Res_Bits_0_lsb 0
+#define xd_r_tpsd_LengthInd (*(volatile byte xdata *) 0xF4C9)
+#define    r_tpsd_LengthInd 0xF4C9
+#define tpsd_LengthInd_pos 0
+#define tpsd_LengthInd_len 6
+#define tpsd_LengthInd_lsb 0
+#define xd_r_tpsd_Cell_Id_7_0   (*(volatile byte xdata *) 0xF4CA)
+#define    r_tpsd_Cell_Id_7_0   0xF4CA
+#define tpsd_Cell_Id_7_0_pos 0
+#define tpsd_Cell_Id_7_0_len 8
+#define tpsd_Cell_Id_7_0_lsb 0
+#define xd_r_tpsd_Cell_Id_15_8  (*(volatile byte xdata *) 0xF4CB)
+#define    r_tpsd_Cell_Id_15_8  0xF4CB
+#define tpsd_Cell_Id_15_8_pos 0
+#define tpsd_Cell_Id_15_8_len 8
+#define tpsd_Cell_Id_15_8_lsb 0
+#define xd_r_tpsd_use_InDepthInt    (*(volatile byte xdata *) 0xF4CC)
+#define    r_tpsd_use_InDepthInt    0xF4CC
+#define tpsd_use_InDepthInt_pos 0
+#define tpsd_use_InDepthInt_len 1
+#define tpsd_use_InDepthInt_lsb 0
+#define xd_r_tpsd_use_TimeSlicing_HP    (*(volatile byte xdata *) 0xF4CD)
+#define    r_tpsd_use_TimeSlicing_HP    0xF4CD
+#define tpsd_use_TimeSlicing_HP_pos 0
+#define tpsd_use_TimeSlicing_HP_len 1
+#define tpsd_use_TimeSlicing_HP_lsb 0
+#define xd_r_tpsd_use_mpe_fec_HP    (*(volatile byte xdata *) 0xF4CE)
+#define    r_tpsd_use_mpe_fec_HP    0xF4CE
+#define tpsd_use_mpe_fec_HP_pos 0
+#define tpsd_use_mpe_fec_HP_len 1
+#define tpsd_use_mpe_fec_HP_lsb 0
+#define xd_r_tpsd_use_TimeSlicing_LP    (*(volatile byte xdata *) 0xF4CF)
+#define    r_tpsd_use_TimeSlicing_LP    0xF4CF
+#define tpsd_use_TimeSlicing_LP_pos 0
+#define tpsd_use_TimeSlicing_LP_len 1
+#define tpsd_use_TimeSlicing_LP_lsb 0
+#define xd_r_tpsd_use_mpe_fec_LP    (*(volatile byte xdata *) 0xF4D0)
+#define    r_tpsd_use_mpe_fec_LP    0xF4D0
+#define tpsd_use_mpe_fec_LP_pos 0
+#define tpsd_use_mpe_fec_LP_len 1
+#define tpsd_use_mpe_fec_LP_lsb 0
+#define xd_r_tpsd_leng23_ind_return (*(volatile byte xdata *) 0xF4D1)
+#define    r_tpsd_leng23_ind_return 0xF4D1
+#define tpsd_leng23_ind_return_pos 0
+#define tpsd_leng23_ind_return_len 1
+#define tpsd_leng23_ind_return_lsb 0
+#define xd_p_reg_fft_re_exp (*(volatile byte xdata *) 0xF500)
+#define    p_reg_fft_re_exp 0xF500
+#define reg_fft_re_exp_pos 0
+#define reg_fft_re_exp_len 4
+#define reg_fft_re_exp_lsb 0
+#define xd_p_reg_fft_re_mts (*(volatile byte xdata *) 0xF501)
+#define    p_reg_fft_re_mts 0xF501
+#define reg_fft_re_mts_pos 0
+#define reg_fft_re_mts_len 8
+#define reg_fft_re_mts_lsb 0
+#define xd_p_reg_fft_im_exp (*(volatile byte xdata *) 0xF502)
+#define    p_reg_fft_im_exp 0xF502
+#define reg_fft_im_exp_pos 0
+#define reg_fft_im_exp_len 4
+#define reg_fft_im_exp_lsb 0
+#define xd_p_reg_fft_im_mts (*(volatile byte xdata *) 0xF503)
+#define    p_reg_fft_im_mts 0xF503
+#define reg_fft_im_mts_pos 0
+#define reg_fft_im_mts_len 8
+#define reg_fft_im_mts_lsb 0
+#define xd_p_reg_fft_conjugate  (*(volatile byte xdata *) 0xF504)
+#define    p_reg_fft_conjugate  0xF504
+#define reg_fft_conjugate_pos 0
+#define reg_fft_conjugate_len 1
+#define reg_fft_conjugate_lsb 0
+#define xd_p_reg_fft_power_en   (*(volatile byte xdata *) 0xF505)
+#define    p_reg_fft_power_en   0xF505
+#define reg_fft_power_en_pos 0
+#define reg_fft_power_en_len 1
+#define reg_fft_power_en_lsb 0
+#define xd_p_reg_fft_power_factor   (*(volatile byte xdata *) 0xF506)
+#define    p_reg_fft_power_factor   0xF506
+#define reg_fft_power_factor_pos 0
+#define reg_fft_power_factor_len 6
+#define reg_fft_power_factor_lsb 0
+#define xd_p_reg_fft_power_in   (*(volatile byte xdata *) 0xF507)
+#define    p_reg_fft_power_in   0xF507
+#define reg_fft_power_in_pos 0
+#define reg_fft_power_in_len 8
+#define reg_fft_power_in_lsb 0
+#define xd_p_reg_fft_mask_from0_7_0 (*(volatile byte xdata *) 0xF508)
+#define    p_reg_fft_mask_from0_7_0 0xF508
+#define reg_fft_mask_from0_7_0_pos 0
+#define reg_fft_mask_from0_7_0_len 8
+#define reg_fft_mask_from0_7_0_lsb 0
+#define xd_p_reg_fft_mask_from0_12_8    (*(volatile byte xdata *) 0xF509)
+#define    p_reg_fft_mask_from0_12_8    0xF509
+#define reg_fft_mask_from0_12_8_pos 0
+#define reg_fft_mask_from0_12_8_len 5
+#define reg_fft_mask_from0_12_8_lsb 8
+#define xd_p_reg_fft_mask_to0_7_0   (*(volatile byte xdata *) 0xF50A)
+#define    p_reg_fft_mask_to0_7_0   0xF50A
+#define reg_fft_mask_to0_7_0_pos 0
+#define reg_fft_mask_to0_7_0_len 8
+#define reg_fft_mask_to0_7_0_lsb 0
+#define xd_p_reg_fft_mask_to0_12_8  (*(volatile byte xdata *) 0xF50B)
+#define    p_reg_fft_mask_to0_12_8  0xF50B
+#define reg_fft_mask_to0_12_8_pos 0
+#define reg_fft_mask_to0_12_8_len 5
+#define reg_fft_mask_to0_12_8_lsb 8
+#define xd_p_reg_fft_mask_from1_7_0 (*(volatile byte xdata *) 0xF50C)
+#define    p_reg_fft_mask_from1_7_0 0xF50C
+#define reg_fft_mask_from1_7_0_pos 0
+#define reg_fft_mask_from1_7_0_len 8
+#define reg_fft_mask_from1_7_0_lsb 0
+#define xd_p_reg_fft_mask_from1_12_8    (*(volatile byte xdata *) 0xF50D)
+#define    p_reg_fft_mask_from1_12_8    0xF50D
+#define reg_fft_mask_from1_12_8_pos 0
+#define reg_fft_mask_from1_12_8_len 5
+#define reg_fft_mask_from1_12_8_lsb 8
+#define xd_p_reg_fft_mask_to1_7_0   (*(volatile byte xdata *) 0xF50E)
+#define    p_reg_fft_mask_to1_7_0   0xF50E
+#define reg_fft_mask_to1_7_0_pos 0
+#define reg_fft_mask_to1_7_0_len 8
+#define reg_fft_mask_to1_7_0_lsb 0
+#define xd_p_reg_fft_mask_to1_12_8  (*(volatile byte xdata *) 0xF50F)
+#define    p_reg_fft_mask_to1_12_8  0xF50F
+#define reg_fft_mask_to1_12_8_pos 0
+#define reg_fft_mask_to1_12_8_len 5
+#define reg_fft_mask_to1_12_8_lsb 8
+#define xd_p_reg_fft_mask_from2_7_0 (*(volatile byte xdata *) 0xF510)
+#define    p_reg_fft_mask_from2_7_0 0xF510
+#define reg_fft_mask_from2_7_0_pos 0
+#define reg_fft_mask_from2_7_0_len 8
+#define reg_fft_mask_from2_7_0_lsb 0
+#define xd_p_reg_fft_mask_from2_12_8    (*(volatile byte xdata *) 0xF511)
+#define    p_reg_fft_mask_from2_12_8    0xF511
+#define reg_fft_mask_from2_12_8_pos 0
+#define reg_fft_mask_from2_12_8_len 5
+#define reg_fft_mask_from2_12_8_lsb 8
+#define xd_p_reg_fft_mask_to2_7_0   (*(volatile byte xdata *) 0xF512)
+#define    p_reg_fft_mask_to2_7_0   0xF512
+#define reg_fft_mask_to2_7_0_pos 0
+#define reg_fft_mask_to2_7_0_len 8
+#define reg_fft_mask_to2_7_0_lsb 0
+#define xd_p_reg_fft_mask_to2_12_8  (*(volatile byte xdata *) 0xF513)
+#define    p_reg_fft_mask_to2_12_8  0xF513
+#define reg_fft_mask_to2_12_8_pos 0
+#define reg_fft_mask_to2_12_8_len 5
+#define reg_fft_mask_to2_12_8_lsb 8
+#define xd_p_reg_fft_mask_from3_7_0 (*(volatile byte xdata *) 0xF514)
+#define    p_reg_fft_mask_from3_7_0 0xF514
+#define reg_fft_mask_from3_7_0_pos 0
+#define reg_fft_mask_from3_7_0_len 8
+#define reg_fft_mask_from3_7_0_lsb 0
+#define xd_p_reg_fft_mask_from3_12_8    (*(volatile byte xdata *) 0xF515)
+#define    p_reg_fft_mask_from3_12_8    0xF515
+#define reg_fft_mask_from3_12_8_pos 0
+#define reg_fft_mask_from3_12_8_len 5
+#define reg_fft_mask_from3_12_8_lsb 8
+#define xd_p_reg_fft_mask_to3_7_0   (*(volatile byte xdata *) 0xF516)
+#define    p_reg_fft_mask_to3_7_0   0xF516
+#define reg_fft_mask_to3_7_0_pos 0
+#define reg_fft_mask_to3_7_0_len 8
+#define reg_fft_mask_to3_7_0_lsb 0
+#define xd_p_reg_fft_mask_to3_12_8  (*(volatile byte xdata *) 0xF517)
+#define    p_reg_fft_mask_to3_12_8  0xF517
+#define reg_fft_mask_to3_12_8_pos 0
+#define reg_fft_mask_to3_12_8_len 5
+#define reg_fft_mask_to3_12_8_lsb 8
+#define xd_r_fd_sntc_frame_num  (*(volatile byte xdata *) 0xF518)
+#define    r_fd_sntc_frame_num  0xF518
+#define fd_sntc_frame_num_pos 0
+#define fd_sntc_frame_num_len 2
+#define fd_sntc_frame_num_lsb 0
+#define xd_r_fd_sntc_symbol_count   (*(volatile byte xdata *) 0xF519)
+#define    r_fd_sntc_symbol_count   0xF519
+#define fd_sntc_symbol_count_pos 0
+#define fd_sntc_symbol_count_len 7
+#define fd_sntc_symbol_count_lsb 0
+#define xd_p_reg_sntc_cnt_lo    (*(volatile byte xdata *) 0xF51A)
+#define    p_reg_sntc_cnt_lo    0xF51A
+#define reg_sntc_cnt_lo_pos 0
+#define reg_sntc_cnt_lo_len 8
+#define reg_sntc_cnt_lo_lsb 0
+#define xd_p_reg_sntc_cnt_hi    (*(volatile byte xdata *) 0xF51B)
+#define    p_reg_sntc_cnt_hi    0xF51B
+#define reg_sntc_cnt_hi_pos 0
+#define reg_sntc_cnt_hi_len 7
+#define reg_sntc_cnt_hi_lsb 0
+#define xd_p_reg_sntc_fft_in    (*(volatile byte xdata *) 0xF51C)
+#define    p_reg_sntc_fft_in    0xF51C
+#define reg_sntc_fft_in_pos 0
+#define reg_sntc_fft_in_len 1
+#define reg_sntc_fft_in_lsb 0
+#define xd_r_fd_sntc_en (*(volatile byte xdata *) 0xF51D)
+#define    r_fd_sntc_en 0xF51D
+#define fd_sntc_en_pos 0
+#define fd_sntc_en_len 1
+#define fd_sntc_en_lsb 0
+#define xd_p_reg_sntc_x2    (*(volatile byte xdata *) 0xF51E)
+#define    p_reg_sntc_x2    0xF51E
+#define reg_sntc_x2_pos 0
+#define reg_sntc_x2_len 1
+#define reg_sntc_x2_lsb 0
+#define xd_p_reg_cge_en_7_0 (*(volatile byte xdata *) 0xF51F)
+#define    p_reg_cge_en_7_0 0xF51F
+#define reg_cge_en_7_0_pos 0
+#define reg_cge_en_7_0_len 8
+#define reg_cge_en_7_0_lsb 0
+#define xd_p_reg_cge_en_15_8    (*(volatile byte xdata *) 0xF520)
+#define    p_reg_cge_en_15_8    0xF520
+#define reg_cge_en_15_8_pos 0
+#define reg_cge_en_15_8_len 8
+#define reg_cge_en_15_8_lsb 8
+#define xd_p_reg_cge_en_23_16   (*(volatile byte xdata *) 0xF521)
+#define    p_reg_cge_en_23_16   0xF521
+#define reg_cge_en_23_16_pos 0
+#define reg_cge_en_23_16_len 8
+#define reg_cge_en_23_16_lsb 16
+#define xd_p_reg_cge_en_31_24   (*(volatile byte xdata *) 0xF522)
+#define    p_reg_cge_en_31_24   0xF522
+#define reg_cge_en_31_24_pos 0
+#define reg_cge_en_31_24_len 8
+#define reg_cge_en_31_24_lsb 24
+#define xd_p_reg_cge_en_39_32   (*(volatile byte xdata *) 0xF523)
+#define    p_reg_cge_en_39_32   0xF523
+#define reg_cge_en_39_32_pos 0
+#define reg_cge_en_39_32_len 8
+#define reg_cge_en_39_32_lsb 32
+#define xd_p_reg_cge_en_43_40   (*(volatile byte xdata *) 0xF524)
+#define    p_reg_cge_en_43_40   0xF524
+#define reg_cge_en_43_40_pos 0
+#define reg_cge_en_43_40_len 4
+#define reg_cge_en_43_40_lsb 40
+#define xd_p_reg_fft_sat_en (*(volatile byte xdata *) 0xF525)
+#define    p_reg_fft_sat_en 0xF525
+#define reg_fft_sat_en_pos 0
+#define reg_fft_sat_en_len 1
+#define reg_fft_sat_en_lsb 0
+#define xd_p_reg_fft_sat_count_clr  (*(volatile byte xdata *) 0xF526)
+#define    p_reg_fft_sat_count_clr  0xF526
+#define reg_fft_sat_count_clr_pos 0
+#define reg_fft_sat_count_clr_len 1
+#define reg_fft_sat_count_clr_lsb 0
+#define xd_p_reg_fft_rescale_round  (*(volatile byte xdata *) 0xF527)
+#define    p_reg_fft_rescale_round  0xF527
+#define reg_fft_rescale_round_pos 0
+#define reg_fft_rescale_round_len 1
+#define reg_fft_rescale_round_lsb 0
+#define xd_r_reg_fft_sat_count_12_7_0   (*(volatile byte xdata *) 0xF528)
+#define    r_reg_fft_sat_count_12_7_0   0xF528
+#define reg_fft_sat_count_12_7_0_pos 0
+#define reg_fft_sat_count_12_7_0_len 8
+#define reg_fft_sat_count_12_7_0_lsb 0
+#define xd_r_reg_fft_sat_count_12_15_8  (*(volatile byte xdata *) 0xF529)
+#define    r_reg_fft_sat_count_12_15_8  0xF529
+#define reg_fft_sat_count_12_15_8_pos 0
+#define reg_fft_sat_count_12_15_8_len 8
+#define reg_fft_sat_count_12_15_8_lsb 8
+#define xd_r_reg_fft_sat_count_10_7_0   (*(volatile byte xdata *) 0xF52A)
+#define    r_reg_fft_sat_count_10_7_0   0xF52A
+#define reg_fft_sat_count_10_7_0_pos 0
+#define reg_fft_sat_count_10_7_0_len 8
+#define reg_fft_sat_count_10_7_0_lsb 0
+#define xd_r_reg_fft_sat_count_10_15_8  (*(volatile byte xdata *) 0xF52B)
+#define    r_reg_fft_sat_count_10_15_8  0xF52B
+#define reg_fft_sat_count_10_15_8_pos 0
+#define reg_fft_sat_count_10_15_8_len 8
+#define reg_fft_sat_count_10_15_8_lsb 8
+#define xd_p_reg_fft_capture_idx_7_0    (*(volatile byte xdata *) 0xF52C)
+#define    p_reg_fft_capture_idx_7_0    0xF52C
+#define reg_fft_capture_idx_7_0_pos 0
+#define reg_fft_capture_idx_7_0_len 8
+#define reg_fft_capture_idx_7_0_lsb 0
+#define xd_p_reg_fft_capture_idx_12_8   (*(volatile byte xdata *) 0xF52D)
+#define    p_reg_fft_capture_idx_12_8   0xF52D
+#define reg_fft_capture_idx_12_8_pos 0
+#define reg_fft_capture_idx_12_8_len 5
+#define reg_fft_capture_idx_12_8_lsb 8
+#define xd_p_reg_fft_capture    (*(volatile byte xdata *) 0xF52E)
+#define    p_reg_fft_capture    0xF52E
+#define reg_fft_capture_pos 0
+#define reg_fft_capture_len 1
+#define reg_fft_capture_lsb 0
+#define xd_p_reg_gp_trigger_fd  (*(volatile byte xdata *) 0xF52F)
+#define    p_reg_gp_trigger_fd  0xF52F
+#define reg_gp_trigger_fd_pos 0
+#define reg_gp_trigger_fd_len 1
+#define reg_gp_trigger_fd_lsb 0
+#define xd_p_reg_trigger_sel_fd (*(volatile byte xdata *) 0xF530)
+#define    p_reg_trigger_sel_fd 0xF530
+#define reg_trigger_sel_fd_pos 0
+#define reg_trigger_sel_fd_len 2
+#define reg_trigger_sel_fd_lsb 0
+#define xd_p_reg_trigger_module_sel_fd  (*(volatile byte xdata *) 0xF531)
+#define    p_reg_trigger_module_sel_fd  0xF531
+#define reg_trigger_module_sel_fd_pos 0
+#define reg_trigger_module_sel_fd_len 6
+#define reg_trigger_module_sel_fd_lsb 0
+#define xd_p_reg_trigger_set_sel_fd (*(volatile byte xdata *) 0xF532)
+#define    p_reg_trigger_set_sel_fd 0xF532
+#define reg_trigger_set_sel_fd_pos 0
+#define reg_trigger_set_sel_fd_len 6
+#define reg_trigger_set_sel_fd_lsb 0
+#define xd_r_reg_fft_idx_pre_max_7_0    (*(volatile byte xdata *) 0xF533)
+#define    r_reg_fft_idx_pre_max_7_0    0xF533
+#define reg_fft_idx_pre_max_7_0_pos 0
+#define reg_fft_idx_pre_max_7_0_len 8
+#define reg_fft_idx_pre_max_7_0_lsb 0
+#define xd_r_reg_fft_idx_pre_max_12_8   (*(volatile byte xdata *) 0xF534)
+#define    r_reg_fft_idx_pre_max_12_8   0xF534
+#define reg_fft_idx_pre_max_12_8_pos 0
+#define reg_fft_idx_pre_max_12_8_len 5
+#define reg_fft_idx_pre_max_12_8_lsb 8
+#define xd_r_reg_fft_crc    (*(volatile byte xdata *) 0xF535)
+#define    r_reg_fft_crc    0xF535
+#define reg_fft_crc_pos 0
+#define reg_fft_crc_len 8
+#define reg_fft_crc_lsb 0
+#define xd_p_fd_fft_shift_max   (*(volatile byte xdata *) 0xF536)
+#define    p_fd_fft_shift_max   0xF536
+#define fd_fft_shift_max_pos 0
+#define fd_fft_shift_max_len 4
+#define fd_fft_shift_max_lsb 0
+#define xd_p_fd_fft_frame_num   (*(volatile byte xdata *) 0xF537)
+#define    p_fd_fft_frame_num   0xF537
+#define fd_fft_frame_num_pos 0
+#define fd_fft_frame_num_len 2
+#define fd_fft_frame_num_lsb 0
+#define xd_p_fd_fft_symbol_count    (*(volatile byte xdata *) 0xF538)
+#define    p_fd_fft_symbol_count    0xF538
+#define fd_fft_symbol_count_pos 0
+#define fd_fft_symbol_count_len 7
+#define fd_fft_symbol_count_lsb 0
+#define xd_r_reg_fft_idx_max_7_0    (*(volatile byte xdata *) 0xF539)
+#define    r_reg_fft_idx_max_7_0    0xF539
+#define reg_fft_idx_max_7_0_pos 0
+#define reg_fft_idx_max_7_0_len 8
+#define reg_fft_idx_max_7_0_lsb 0
+#define xd_r_reg_fft_idx_max_12_8   (*(volatile byte xdata *) 0xF53A)
+#define    r_reg_fft_idx_max_12_8   0xF53A
+#define reg_fft_idx_max_12_8_pos 0
+#define reg_fft_idx_max_12_8_len 5
+#define reg_fft_idx_max_12_8_lsb 8
+#define xd_p_reg_fft_rotate_en  (*(volatile byte xdata *) 0xF53B)
+#define    p_reg_fft_rotate_en  0xF53B
+#define reg_fft_rotate_en_pos 0
+#define reg_fft_rotate_en_len 1
+#define reg_fft_rotate_en_lsb 0
+#define xd_p_reg_fft_rotate_base_7_0    (*(volatile byte xdata *) 0xF53C)
+#define    p_reg_fft_rotate_base_7_0    0xF53C
+#define reg_fft_rotate_base_7_0_pos 0
+#define reg_fft_rotate_base_7_0_len 8
+#define reg_fft_rotate_base_7_0_lsb 0
+#define xd_p_reg_fft_rotate_base_12_8   (*(volatile byte xdata *) 0xF53D)
+#define    p_reg_fft_rotate_base_12_8   0xF53D
+#define reg_fft_rotate_base_12_8_pos 0
+#define reg_fft_rotate_base_12_8_len 5
+#define reg_fft_rotate_base_12_8_lsb 8
+#define xd_r_fd_fpcc_cp_corr_signn  (*(volatile byte xdata *) 0xF53E)
+#define    r_fd_fpcc_cp_corr_signn  0xF53E
+#define fd_fpcc_cp_corr_signn_pos 0
+#define fd_fpcc_cp_corr_signn_len 8
+#define fd_fpcc_cp_corr_signn_lsb 0
+#define xd_p_reg_feq_s1 (*(volatile byte xdata *) 0xF53F)
+#define    p_reg_feq_s1 0xF53F
+#define reg_feq_s1_pos 0
+#define reg_feq_s1_len 5
+#define reg_feq_s1_lsb 0
+#define xd_p_reg_feq_sat_ind    (*(volatile byte xdata *) 0xF540)
+#define    p_reg_feq_sat_ind    0xF540
+#define reg_feq_sat_ind_pos 0
+#define reg_feq_sat_ind_len 3
+#define reg_feq_sat_ind_lsb 0
+#define xd_p_reg_p_csi_cal_en   (*(volatile byte xdata *) 0xF541)
+#define    p_reg_p_csi_cal_en   0xF541
+#define reg_p_csi_cal_en_pos 0
+#define reg_p_csi_cal_en_len 1
+#define reg_p_csi_cal_en_lsb 0
+#define xd_p_reg_p_csi_ar_mode  (*(volatile byte xdata *) 0xF542)
+#define    p_reg_p_csi_ar_mode  0xF542
+#define reg_p_csi_ar_mode_pos 0
+#define reg_p_csi_ar_mode_len 2
+#define reg_p_csi_ar_mode_lsb 0
+#define xd_p_reg_p_csi_accu_sym_num (*(volatile byte xdata *) 0xF543)
+#define    p_reg_p_csi_accu_sym_num 0xF543
+#define reg_p_csi_accu_sym_num_pos 0
+#define reg_p_csi_accu_sym_num_len 8
+#define reg_p_csi_accu_sym_num_lsb 0
+#define xd_p_reg_p_csi_eh2_shift_thr    (*(volatile byte xdata *) 0xF544)
+#define    p_reg_p_csi_eh2_shift_thr    0xF544
+#define reg_p_csi_eh2_shift_thr_pos 0
+#define reg_p_csi_eh2_shift_thr_len 4
+#define reg_p_csi_eh2_shift_thr_lsb 0
+#define xd_p_reg_p_feq_protect_eh2_shift_thr    (*(volatile byte xdata *) 0xF545)
+#define    p_reg_p_feq_protect_eh2_shift_thr    0xF545
+#define reg_p_feq_protect_eh2_shift_thr_pos 0
+#define reg_p_feq_protect_eh2_shift_thr_len 4
+#define reg_p_feq_protect_eh2_shift_thr_lsb 0
+#define xd_p_reg_p_csi_error_accu_s1    (*(volatile byte xdata *) 0xF546)
+#define    p_reg_p_csi_error_accu_s1    0xF546
+#define reg_p_csi_error_accu_s1_pos 0
+#define reg_p_csi_error_accu_s1_len 6
+#define reg_p_csi_error_accu_s1_lsb 0
+#define xd_p_reg_p_csi_shift2   (*(volatile byte xdata *) 0xF547)
+#define    p_reg_p_csi_shift2   0xF547
+#define reg_p_csi_shift2_pos 0
+#define reg_p_csi_shift2_len 4
+#define reg_p_csi_shift2_lsb 0
+#define xd_p_reg_p_csi_mul2 (*(volatile byte xdata *) 0xF548)
+#define    p_reg_p_csi_mul2 0xF548
+#define reg_p_csi_mul2_pos 0
+#define reg_p_csi_mul2_len 8
+#define reg_p_csi_mul2_lsb 0
+#define xd_p_reg_p_csi_level2_7_0   (*(volatile byte xdata *) 0xF549)
+#define    p_reg_p_csi_level2_7_0   0xF549
+#define reg_p_csi_level2_7_0_pos 0
+#define reg_p_csi_level2_7_0_len 8
+#define reg_p_csi_level2_7_0_lsb 0
+#define xd_p_reg_p_csi_level2_8 (*(volatile byte xdata *) 0xF54A)
+#define    p_reg_p_csi_level2_8 0xF54A
+#define reg_p_csi_level2_8_pos 0
+#define reg_p_csi_level2_8_len 1
+#define reg_p_csi_level2_8_lsb 8
+#define xd_p_reg_p_feq_protect_ratio    (*(volatile byte xdata *) 0xF54B)
+#define    p_reg_p_feq_protect_ratio    0xF54B
+#define reg_p_feq_protect_ratio_pos 0
+#define reg_p_feq_protect_ratio_len 8
+#define reg_p_feq_protect_ratio_lsb 0
+#define xd_r_reg_csi_rdy    (*(volatile byte xdata *) 0xF54C)
+#define    r_reg_csi_rdy    0xF54C
+#define reg_csi_rdy_pos 0
+#define reg_csi_rdy_len 1
+#define reg_csi_rdy_lsb 0
+#define xd_p_reg_p_feq_h2protect_en (*(volatile byte xdata *) 0xF54D)
+#define    p_reg_p_feq_h2protect_en 0xF54D
+#define reg_p_feq_h2protect_en_pos 0
+#define reg_p_feq_h2protect_en_len 1
+#define reg_p_feq_h2protect_en_lsb 0
+#define xd_r_reg_tpsd_lock_f0   (*(volatile byte xdata *) 0xF54E)
+#define    r_reg_tpsd_lock_f0   0xF54E
+#define reg_tpsd_lock_f0_pos 0
+#define reg_tpsd_lock_f0_len 1
+#define reg_tpsd_lock_f0_lsb 0
+#define xd_r_reg_tpsd_lock_f1   (*(volatile byte xdata *) 0xF54F)
+#define    r_reg_tpsd_lock_f1   0xF54F
+#define reg_tpsd_lock_f1_pos 0
+#define reg_tpsd_lock_f1_len 1
+#define reg_tpsd_lock_f1_lsb 0
+#define xd_p_reg_p_csi_sp_idx_7_0   (*(volatile byte xdata *) 0xF550)
+#define    p_reg_p_csi_sp_idx_7_0   0xF550
+#define reg_p_csi_sp_idx_7_0_pos 0
+#define reg_p_csi_sp_idx_7_0_len 8
+#define reg_p_csi_sp_idx_7_0_lsb 0
+#define xd_p_reg_p_csi_sp_idx_11_8  (*(volatile byte xdata *) 0xF551)
+#define    p_reg_p_csi_sp_idx_11_8  0xF551
+#define reg_p_csi_sp_idx_11_8_pos 0
+#define reg_p_csi_sp_idx_11_8_len 4
+#define reg_p_csi_sp_idx_11_8_lsb 8
+#define xd_p_fd_fpcc_cp_corr_tone_th    (*(volatile byte xdata *) 0xF552)
+#define    p_fd_fpcc_cp_corr_tone_th    0xF552
+#define fd_fpcc_cp_corr_tone_th_pos 0
+#define fd_fpcc_cp_corr_tone_th_len 6
+#define fd_fpcc_cp_corr_tone_th_lsb 0
+#define xd_p_fd_fpcc_cp_corr_symbol_log_th  (*(volatile byte xdata *) 0xF553)
+#define    p_fd_fpcc_cp_corr_symbol_log_th  0xF553
+#define fd_fpcc_cp_corr_symbol_log_th_pos 0
+#define fd_fpcc_cp_corr_symbol_log_th_len 4
+#define fd_fpcc_cp_corr_symbol_log_th_lsb 0
+#define xd_p_fd_fpcc_cp_corr_int    (*(volatile byte xdata *) 0xF554)
+#define    p_fd_fpcc_cp_corr_int    0xF554
+#define fd_fpcc_cp_corr_int_pos 0
+#define fd_fpcc_cp_corr_int_len 1
+#define fd_fpcc_cp_corr_int_lsb 0
+#define xd_p_reg_fpcc_cp_memidx (*(volatile byte xdata *) 0xF555)
+#define    p_reg_fpcc_cp_memidx 0xF555
+#define reg_fpcc_cp_memidx_pos 0
+#define reg_fpcc_cp_memidx_len 8
+#define reg_fpcc_cp_memidx_lsb 0
+#define xd_p_reg_fpcc_cpmask_en (*(volatile byte xdata *) 0xF556)
+#define    p_reg_fpcc_cpmask_en 0xF556
+#define reg_fpcc_cpmask_en_pos 0
+#define reg_fpcc_cpmask_en_len 1
+#define reg_fpcc_cpmask_en_lsb 0
+#define xd_p_reg_fpcc_cp_grpidx (*(volatile byte xdata *) 0xF557)
+#define    p_reg_fpcc_cp_grpidx 0xF557
+#define reg_fpcc_cp_grpidx_pos 0
+#define reg_fpcc_cp_grpidx_len 5
+#define reg_fpcc_cp_grpidx_lsb 0
+#define xd_r_reg_fpcc_cp_sts    (*(volatile byte xdata *) 0xF558)
+#define    r_reg_fpcc_cp_sts    0xF558
+#define reg_fpcc_cp_sts_pos 0
+#define reg_fpcc_cp_sts_len 1
+#define reg_fpcc_cp_sts_lsb 0
+#define xd_p_reg_sfoe_ns_7_0    (*(volatile byte xdata *) 0xF559)
+#define    p_reg_sfoe_ns_7_0    0xF559
+#define reg_sfoe_ns_7_0_pos 0
+#define reg_sfoe_ns_7_0_len 8
+#define reg_sfoe_ns_7_0_lsb 0
+#define xd_p_reg_sfoe_ns_14_8   (*(volatile byte xdata *) 0xF55A)
+#define    p_reg_sfoe_ns_14_8   0xF55A
+#define reg_sfoe_ns_14_8_pos 0
+#define reg_sfoe_ns_14_8_len 7
+#define reg_sfoe_ns_14_8_lsb 8
+#define xd_p_reg_sfoe_c1_7_0    (*(volatile byte xdata *) 0xF55B)
+#define    p_reg_sfoe_c1_7_0    0xF55B
+#define reg_sfoe_c1_7_0_pos 0
+#define reg_sfoe_c1_7_0_len 8
+#define reg_sfoe_c1_7_0_lsb 0
+#define xd_p_reg_sfoe_c1_9_8    (*(volatile byte xdata *) 0xF55C)
+#define    p_reg_sfoe_c1_9_8    0xF55C
+#define reg_sfoe_c1_9_8_pos 0
+#define reg_sfoe_c1_9_8_len 2
+#define reg_sfoe_c1_9_8_lsb 8
+#define xd_p_reg_sfoe_c2_7_0    (*(volatile byte xdata *) 0xF55D)
+#define    p_reg_sfoe_c2_7_0    0xF55D
+#define reg_sfoe_c2_7_0_pos 0
+#define reg_sfoe_c2_7_0_len 8
+#define reg_sfoe_c2_7_0_lsb 0
+#define xd_p_reg_sfoe_c2_9_8    (*(volatile byte xdata *) 0xF55E)
+#define    p_reg_sfoe_c2_9_8    0xF55E
+#define reg_sfoe_c2_9_8_pos 0
+#define reg_sfoe_c2_9_8_len 2
+#define reg_sfoe_c2_9_8_lsb 8
+#define xd_p_reg_sfoe_lm_counter_th (*(volatile byte xdata *) 0xF55F)
+#define    p_reg_sfoe_lm_counter_th 0xF55F
+#define reg_sfoe_lm_counter_th_pos 0
+#define reg_sfoe_lm_counter_th_len 4
+#define reg_sfoe_lm_counter_th_lsb 0
+#define xd_p_reg_sfoe_spec_inv  (*(volatile byte xdata *) 0xF560)
+#define    p_reg_sfoe_spec_inv  0xF560
+#define reg_sfoe_spec_inv_pos 0
+#define reg_sfoe_spec_inv_len 1
+#define reg_sfoe_spec_inv_lsb 0
+#define xd_p_reg_sfoe_convg_th  (*(volatile byte xdata *) 0xF561)
+#define    p_reg_sfoe_convg_th  0xF561
+#define reg_sfoe_convg_th_pos 0
+#define reg_sfoe_convg_th_len 8
+#define reg_sfoe_convg_th_lsb 0
+#define xd_p_reg_sfoe_divg_th   (*(volatile byte xdata *) 0xF562)
+#define    p_reg_sfoe_divg_th   0xF562
+#define reg_sfoe_divg_th_pos 0
+#define reg_sfoe_divg_th_len 8
+#define reg_sfoe_divg_th_lsb 0
+#define xd_p_reg_sfoe_pullin_ctr_th (*(volatile byte xdata *) 0xF563)
+#define    p_reg_sfoe_pullin_ctr_th 0xF563
+#define reg_sfoe_pullin_ctr_th_pos 0
+#define reg_sfoe_pullin_ctr_th_len 4
+#define reg_sfoe_pullin_ctr_th_lsb 0
+#define xd_p_reg_sfoe_sf_ctr_th (*(volatile byte xdata *) 0xF564)
+#define    p_reg_sfoe_sf_ctr_th 0xF564
+#define reg_sfoe_sf_ctr_th_pos 0
+#define reg_sfoe_sf_ctr_th_len 4
+#define reg_sfoe_sf_ctr_th_lsb 0
+#define xd_p_reg_sfoe_pullin_th (*(volatile byte xdata *) 0xF565)
+#define    p_reg_sfoe_pullin_th 0xF565
+#define reg_sfoe_pullin_th_pos 0
+#define reg_sfoe_pullin_th_len 8
+#define reg_sfoe_pullin_th_lsb 0
+#define xd_p_reg_sfoe_kalman_cnt    (*(volatile byte xdata *) 0xF566)
+#define    p_reg_sfoe_kalman_cnt    0xF566
+#define reg_sfoe_kalman_cnt_pos 0
+#define reg_sfoe_kalman_cnt_len 4
+#define reg_sfoe_kalman_cnt_lsb 0
+#define xd_p_reg_sfoe_fsm_info  (*(volatile byte xdata *) 0xF567)
+#define    p_reg_sfoe_fsm_info  0xF567
+#define reg_sfoe_fsm_info_pos 0
+#define reg_sfoe_fsm_info_len 4
+#define reg_sfoe_fsm_info_lsb 0
+#define xd_r_reg_sfoe_pullin_cnt    (*(volatile byte xdata *) 0xF568)
+#define    r_reg_sfoe_pullin_cnt    0xF568
+#define reg_sfoe_pullin_cnt_pos 0
+#define reg_sfoe_pullin_cnt_len 4
+#define reg_sfoe_pullin_cnt_lsb 0
+#define xd_r_reg_sfoe_sf_cnt    (*(volatile byte xdata *) 0xF569)
+#define    r_reg_sfoe_sf_cnt    0xF569
+#define reg_sfoe_sf_cnt_pos 0
+#define reg_sfoe_sf_cnt_len 4
+#define reg_sfoe_sf_cnt_lsb 0
+#define xd_p_reg_fste_phase_ini_7_0 (*(volatile byte xdata *) 0xF56A)
+#define    p_reg_fste_phase_ini_7_0 0xF56A
+#define reg_fste_phase_ini_7_0_pos 0
+#define reg_fste_phase_ini_7_0_len 8
+#define reg_fste_phase_ini_7_0_lsb 0
+#define xd_p_reg_fste_phase_ini_11_8    (*(volatile byte xdata *) 0xF56B)
+#define    p_reg_fste_phase_ini_11_8    0xF56B
+#define reg_fste_phase_ini_11_8_pos 0
+#define reg_fste_phase_ini_11_8_len 4
+#define reg_fste_phase_ini_11_8_lsb 8
+#define xd_p_reg_fste_phase_inc_7_0 (*(volatile byte xdata *) 0xF56C)
+#define    p_reg_fste_phase_inc_7_0 0xF56C
+#define reg_fste_phase_inc_7_0_pos 0
+#define reg_fste_phase_inc_7_0_len 8
+#define reg_fste_phase_inc_7_0_lsb 0
+#define xd_p_reg_fste_phase_inc_11_8    (*(volatile byte xdata *) 0xF56D)
+#define    p_reg_fste_phase_inc_11_8    0xF56D
+#define reg_fste_phase_inc_11_8_pos 0
+#define reg_fste_phase_inc_11_8_len 4
+#define reg_fste_phase_inc_11_8_lsb 8
+#define xd_p_reg_fste_acum_cost_cnt_max (*(volatile byte xdata *) 0xF56E)
+#define    p_reg_fste_acum_cost_cnt_max 0xF56E
+#define reg_fste_acum_cost_cnt_max_pos 0
+#define reg_fste_acum_cost_cnt_max_len 4
+#define reg_fste_acum_cost_cnt_max_lsb 0
+#define xd_p_reg_fste_step_size_std (*(volatile byte xdata *) 0xF56F)
+#define    p_reg_fste_step_size_std 0xF56F
+#define reg_fste_step_size_std_pos 0
+#define reg_fste_step_size_std_len 4
+#define reg_fste_step_size_std_lsb 0
+#define xd_p_reg_fste_step_size_max (*(volatile byte xdata *) 0xF570)
+#define    p_reg_fste_step_size_max 0xF570
+#define reg_fste_step_size_max_pos 0
+#define reg_fste_step_size_max_len 4
+#define reg_fste_step_size_max_lsb 0
+#define xd_p_reg_fste_rpd_dir_cnt_max   (*(volatile byte xdata *) 0xF571)
+#define    p_reg_fste_rpd_dir_cnt_max   0xF571
+#define reg_fste_rpd_dir_cnt_max_pos 0
+#define reg_fste_rpd_dir_cnt_max_len 4
+#define reg_fste_rpd_dir_cnt_max_lsb 0
+#define xd_p_reg_fste_frac_cost_cnt_max_7_0 (*(volatile byte xdata *) 0xF572)
+#define    p_reg_fste_frac_cost_cnt_max_7_0 0xF572
+#define reg_fste_frac_cost_cnt_max_7_0_pos 0
+#define reg_fste_frac_cost_cnt_max_7_0_len 8
+#define reg_fste_frac_cost_cnt_max_7_0_lsb 0
+#define xd_p_reg_fste_frac_cost_cnt_max_9_8 (*(volatile byte xdata *) 0xF573)
+#define    p_reg_fste_frac_cost_cnt_max_9_8 0xF573
+#define reg_fste_frac_cost_cnt_max_9_8_pos 0
+#define reg_fste_frac_cost_cnt_max_9_8_len 2
+#define reg_fste_frac_cost_cnt_max_9_8_lsb 8
+#define xd_p_reg_fste_isLongWeakTail    (*(volatile byte xdata *) 0xF574)
+#define    p_reg_fste_isLongWeakTail    0xF574
+#define reg_fste_isLongWeakTail_pos 0
+#define reg_fste_isLongWeakTail_len 1
+#define reg_fste_isLongWeakTail_lsb 0
+#define xd_p_reg_fste_isLongWeakHead    (*(volatile byte xdata *) 0xF575)
+#define    p_reg_fste_isLongWeakHead    0xF575
+#define reg_fste_isLongWeakHead_pos 0
+#define reg_fste_isLongWeakHead_len 1
+#define reg_fste_isLongWeakHead_lsb 0
+#define xd_p_reg_fste_w0_7_0    (*(volatile byte xdata *) 0xF576)
+#define    p_reg_fste_w0_7_0    0xF576
+#define reg_fste_w0_7_0_pos 0
+#define reg_fste_w0_7_0_len 8
+#define reg_fste_w0_7_0_lsb 0
+#define xd_p_reg_fste_w0_9_8    (*(volatile byte xdata *) 0xF577)
+#define    p_reg_fste_w0_9_8    0xF577
+#define reg_fste_w0_9_8_pos 0
+#define reg_fste_w0_9_8_len 2
+#define reg_fste_w0_9_8_lsb 8
+#define xd_p_reg_fste_w1_7_0    (*(volatile byte xdata *) 0xF578)
+#define    p_reg_fste_w1_7_0    0xF578
+#define reg_fste_w1_7_0_pos 0
+#define reg_fste_w1_7_0_len 8
+#define reg_fste_w1_7_0_lsb 0
+#define xd_p_reg_fste_w1_9_8    (*(volatile byte xdata *) 0xF579)
+#define    p_reg_fste_w1_9_8    0xF579
+#define reg_fste_w1_9_8_pos 0
+#define reg_fste_w1_9_8_len 2
+#define reg_fste_w1_9_8_lsb 8
+#define xd_p_reg_fste_w2_7_0    (*(volatile byte xdata *) 0xF57A)
+#define    p_reg_fste_w2_7_0    0xF57A
+#define reg_fste_w2_7_0_pos 0
+#define reg_fste_w2_7_0_len 8
+#define reg_fste_w2_7_0_lsb 0
+#define xd_p_reg_fste_w2_9_8    (*(volatile byte xdata *) 0xF57B)
+#define    p_reg_fste_w2_9_8    0xF57B
+#define reg_fste_w2_9_8_pos 0
+#define reg_fste_w2_9_8_len 2
+#define reg_fste_w2_9_8_lsb 8
+#define xd_p_reg_fste_w3_7_0    (*(volatile byte xdata *) 0xF57C)
+#define    p_reg_fste_w3_7_0    0xF57C
+#define reg_fste_w3_7_0_pos 0
+#define reg_fste_w3_7_0_len 8
+#define reg_fste_w3_7_0_lsb 0
+#define xd_p_reg_fste_w3_9_8    (*(volatile byte xdata *) 0xF57D)
+#define    p_reg_fste_w3_9_8    0xF57D
+#define reg_fste_w3_9_8_pos 0
+#define reg_fste_w3_9_8_len 2
+#define reg_fste_w3_9_8_lsb 8
+#define xd_p_reg_fste_w4_7_0    (*(volatile byte xdata *) 0xF57E)
+#define    p_reg_fste_w4_7_0    0xF57E
+#define reg_fste_w4_7_0_pos 0
+#define reg_fste_w4_7_0_len 8
+#define reg_fste_w4_7_0_lsb 0
+#define xd_p_reg_fste_w4_9_8    (*(volatile byte xdata *) 0xF57F)
+#define    p_reg_fste_w4_9_8    0xF57F
+#define reg_fste_w4_9_8_pos 0
+#define reg_fste_w4_9_8_len 2
+#define reg_fste_w4_9_8_lsb 8
+#define xd_p_reg_fste_w5_7_0    (*(volatile byte xdata *) 0xF580)
+#define    p_reg_fste_w5_7_0    0xF580
+#define reg_fste_w5_7_0_pos 0
+#define reg_fste_w5_7_0_len 8
+#define reg_fste_w5_7_0_lsb 0
+#define xd_p_reg_fste_w5_9_8    (*(volatile byte xdata *) 0xF581)
+#define    p_reg_fste_w5_9_8    0xF581
+#define reg_fste_w5_9_8_pos 0
+#define reg_fste_w5_9_8_len 2
+#define reg_fste_w5_9_8_lsb 8
+#define xd_p_reg_fste_w6_7_0    (*(volatile byte xdata *) 0xF582)
+#define    p_reg_fste_w6_7_0    0xF582
+#define reg_fste_w6_7_0_pos 0
+#define reg_fste_w6_7_0_len 8
+#define reg_fste_w6_7_0_lsb 0
+#define xd_p_reg_fste_w6_9_8    (*(volatile byte xdata *) 0xF583)
+#define    p_reg_fste_w6_9_8    0xF583
+#define reg_fste_w6_9_8_pos 0
+#define reg_fste_w6_9_8_len 2
+#define reg_fste_w6_9_8_lsb 8
+#define xd_p_reg_fste_w7_7_0    (*(volatile byte xdata *) 0xF584)
+#define    p_reg_fste_w7_7_0    0xF584
+#define reg_fste_w7_7_0_pos 0
+#define reg_fste_w7_7_0_len 8
+#define reg_fste_w7_7_0_lsb 0
+#define xd_p_reg_fste_w7_9_8    (*(volatile byte xdata *) 0xF585)
+#define    p_reg_fste_w7_9_8    0xF585
+#define reg_fste_w7_9_8_pos 0
+#define reg_fste_w7_9_8_len 2
+#define reg_fste_w7_9_8_lsb 8
+#define xd_p_reg_fste_w8_7_0    (*(volatile byte xdata *) 0xF586)
+#define    p_reg_fste_w8_7_0    0xF586
+#define reg_fste_w8_7_0_pos 0
+#define reg_fste_w8_7_0_len 8
+#define reg_fste_w8_7_0_lsb 0
+#define xd_p_reg_fste_w8_9_8    (*(volatile byte xdata *) 0xF587)
+#define    p_reg_fste_w8_9_8    0xF587
+#define reg_fste_w8_9_8_pos 0
+#define reg_fste_w8_9_8_len 2
+#define reg_fste_w8_9_8_lsb 8
+#define xd_p_reg_fste_w9_7_0    (*(volatile byte xdata *) 0xF588)
+#define    p_reg_fste_w9_7_0    0xF588
+#define reg_fste_w9_7_0_pos 0
+#define reg_fste_w9_7_0_len 8
+#define reg_fste_w9_7_0_lsb 0
+#define xd_p_reg_fste_w9_9_8    (*(volatile byte xdata *) 0xF589)
+#define    p_reg_fste_w9_9_8    0xF589
+#define reg_fste_w9_9_8_pos 0
+#define reg_fste_w9_9_8_len 2
+#define reg_fste_w9_9_8_lsb 8
+#define xd_p_reg_fste_wa_7_0    (*(volatile byte xdata *) 0xF58A)
+#define    p_reg_fste_wa_7_0    0xF58A
+#define reg_fste_wa_7_0_pos 0
+#define reg_fste_wa_7_0_len 8
+#define reg_fste_wa_7_0_lsb 0
+#define xd_p_reg_fste_wa_9_8    (*(volatile byte xdata *) 0xF58B)
+#define    p_reg_fste_wa_9_8    0xF58B
+#define reg_fste_wa_9_8_pos 0
+#define reg_fste_wa_9_8_len 2
+#define reg_fste_wa_9_8_lsb 8
+#define xd_p_reg_fste_wb_7_0    (*(volatile byte xdata *) 0xF58C)
+#define    p_reg_fste_wb_7_0    0xF58C
+#define reg_fste_wb_7_0_pos 0
+#define reg_fste_wb_7_0_len 8
+#define reg_fste_wb_7_0_lsb 0
+#define xd_p_reg_fste_wb_9_8    (*(volatile byte xdata *) 0xF58D)
+#define    p_reg_fste_wb_9_8    0xF58D
+#define reg_fste_wb_9_8_pos 0
+#define reg_fste_wb_9_8_len 2
+#define reg_fste_wb_9_8_lsb 8
+#define xd_p_reg_fste_wc_7_0    (*(volatile byte xdata *) 0xF58E)
+#define    p_reg_fste_wc_7_0    0xF58E
+#define reg_fste_wc_7_0_pos 0
+#define reg_fste_wc_7_0_len 8
+#define reg_fste_wc_7_0_lsb 0
+#define xd_p_reg_fste_wc_9_8    (*(volatile byte xdata *) 0xF58F)
+#define    p_reg_fste_wc_9_8    0xF58F
+#define reg_fste_wc_9_8_pos 0
+#define reg_fste_wc_9_8_len 2
+#define reg_fste_wc_9_8_lsb 8
+#define xd_p_reg_fste_wd_7_0    (*(volatile byte xdata *) 0xF590)
+#define    p_reg_fste_wd_7_0    0xF590
+#define reg_fste_wd_7_0_pos 0
+#define reg_fste_wd_7_0_len 8
+#define reg_fste_wd_7_0_lsb 0
+#define xd_p_reg_fste_wd_9_8    (*(volatile byte xdata *) 0xF591)
+#define    p_reg_fste_wd_9_8    0xF591
+#define reg_fste_wd_9_8_pos 0
+#define reg_fste_wd_9_8_len 2
+#define reg_fste_wd_9_8_lsb 8
+#define xd_p_reg_fste_we_7_0    (*(volatile byte xdata *) 0xF592)
+#define    p_reg_fste_we_7_0    0xF592
+#define reg_fste_we_7_0_pos 0
+#define reg_fste_we_7_0_len 8
+#define reg_fste_we_7_0_lsb 0
+#define xd_p_reg_fste_we_9_8    (*(volatile byte xdata *) 0xF593)
+#define    p_reg_fste_we_9_8    0xF593
+#define reg_fste_we_9_8_pos 0
+#define reg_fste_we_9_8_len 2
+#define reg_fste_we_9_8_lsb 8
+#define xd_p_reg_fste_wf_7_0    (*(volatile byte xdata *) 0xF594)
+#define    p_reg_fste_wf_7_0    0xF594
+#define reg_fste_wf_7_0_pos 0
+#define reg_fste_wf_7_0_len 8
+#define reg_fste_wf_7_0_lsb 0
+#define xd_p_reg_fste_wf_9_8    (*(volatile byte xdata *) 0xF595)
+#define    p_reg_fste_wf_9_8    0xF595
+#define reg_fste_wf_9_8_pos 0
+#define reg_fste_wf_9_8_len 2
+#define reg_fste_wf_9_8_lsb 8
+#define xd_p_reg_fste_wg_7_0    (*(volatile byte xdata *) 0xF596)
+#define    p_reg_fste_wg_7_0    0xF596
+#define reg_fste_wg_7_0_pos 0
+#define reg_fste_wg_7_0_len 8
+#define reg_fste_wg_7_0_lsb 0
+#define xd_p_reg_fste_wg_9_8    (*(volatile byte xdata *) 0xF597)
+#define    p_reg_fste_wg_9_8    0xF597
+#define reg_fste_wg_9_8_pos 0
+#define reg_fste_wg_9_8_len 2
+#define reg_fste_wg_9_8_lsb 8
+#define xd_p_reg_fste_wh_7_0    (*(volatile byte xdata *) 0xF598)
+#define    p_reg_fste_wh_7_0    0xF598
+#define reg_fste_wh_7_0_pos 0
+#define reg_fste_wh_7_0_len 8
+#define reg_fste_wh_7_0_lsb 0
+#define xd_p_reg_fste_wh_9_8    (*(volatile byte xdata *) 0xF599)
+#define    p_reg_fste_wh_9_8    0xF599
+#define reg_fste_wh_9_8_pos 0
+#define reg_fste_wh_9_8_len 2
+#define reg_fste_wh_9_8_lsb 8
+#define xd_r_fd_fste_i_adj_org  (*(volatile byte xdata *) 0xF59A)
+#define    r_fd_fste_i_adj_org  0xF59A
+#define fd_fste_i_adj_org_pos 0
+#define fd_fste_i_adj_org_len 5
+#define fd_fste_i_adj_org_lsb 0
+#define xd_r_fd_fste_f_adj_7_0  (*(volatile byte xdata *) 0xF59B)
+#define    r_fd_fste_f_adj_7_0  0xF59B
+#define fd_fste_f_adj_7_0_pos 0
+#define fd_fste_f_adj_7_0_len 8
+#define fd_fste_f_adj_7_0_lsb 0
+#define xd_r_fd_fste_f_adj_15_8 (*(volatile byte xdata *) 0xF59C)
+#define    r_fd_fste_f_adj_15_8 0xF59C
+#define fd_fste_f_adj_15_8_pos 0
+#define fd_fste_f_adj_15_8_len 8
+#define fd_fste_f_adj_15_8_lsb 8
+#define xd_r_fd_fste_f_adj_19_16    (*(volatile byte xdata *) 0xF59D)
+#define    r_fd_fste_f_adj_19_16    0xF59D
+#define fd_fste_f_adj_19_16_pos 0
+#define fd_fste_f_adj_19_16_len 4
+#define fd_fste_f_adj_19_16_lsb 16
+#define xd_p_reg_fste_ehw_7_0   (*(volatile byte xdata *) 0xF59E)
+#define    p_reg_fste_ehw_7_0   0xF59E
+#define reg_fste_ehw_7_0_pos 0
+#define reg_fste_ehw_7_0_len 8
+#define reg_fste_ehw_7_0_lsb 0
+#define xd_p_reg_fste_ehw_12_8  (*(volatile byte xdata *) 0xF59F)
+#define    p_reg_fste_ehw_12_8  0xF59F
+#define reg_fste_ehw_12_8_pos 0
+#define reg_fste_ehw_12_8_len 5
+#define reg_fste_ehw_12_8_lsb 8
+#define xd_p_reg_fste_i_adj_vld (*(volatile byte xdata *) 0xF5A0)
+#define    p_reg_fste_i_adj_vld 0xF5A0
+#define reg_fste_i_adj_vld_pos 0
+#define reg_fste_i_adj_vld_len 1
+#define reg_fste_i_adj_vld_lsb 0
+#define xd_p_reg_fste_ceTimesPhasor_real    (*(volatile byte xdata *) 0xF5A1)
+#define    p_reg_fste_ceTimesPhasor_real    0xF5A1
+#define reg_fste_ceTimesPhasor_real_pos 0
+#define reg_fste_ceTimesPhasor_real_len 1
+#define reg_fste_ceTimesPhasor_real_lsb 0
+#define xd_p_reg_fste_ceTimesPhasor_imag    (*(volatile byte xdata *) 0xF5A2)
+#define    p_reg_fste_ceTimesPhasor_imag    0xF5A2
+#define reg_fste_ceTimesPhasor_imag_pos 0
+#define reg_fste_ceTimesPhasor_imag_len 1
+#define reg_fste_ceTimesPhasor_imag_lsb 0
+#define xd_p_reg_fste_cerTimesW_real    (*(volatile byte xdata *) 0xF5A3)
+#define    p_reg_fste_cerTimesW_real    0xF5A3
+#define reg_fste_cerTimesW_real_pos 0
+#define reg_fste_cerTimesW_real_len 1
+#define reg_fste_cerTimesW_real_lsb 0
+#define xd_p_reg_fste_cerTimesW_imag    (*(volatile byte xdata *) 0xF5A4)
+#define    p_reg_fste_cerTimesW_imag    0xF5A4
+#define reg_fste_cerTimesW_imag_pos 0
+#define reg_fste_cerTimesW_imag_len 1
+#define reg_fste_cerTimesW_imag_lsb 0
+#define xd_p_reg_fste_cerTimesWAccum_real   (*(volatile byte xdata *) 0xF5A5)
+#define    p_reg_fste_cerTimesWAccum_real   0xF5A5
+#define reg_fste_cerTimesWAccum_real_pos 0
+#define reg_fste_cerTimesWAccum_real_len 1
+#define reg_fste_cerTimesWAccum_real_lsb 0
+#define xd_p_reg_fste_cerTimesWAccum_imag   (*(volatile byte xdata *) 0xF5A6)
+#define    p_reg_fste_cerTimesWAccum_imag   0xF5A6
+#define reg_fste_cerTimesWAccum_imag_pos 0
+#define reg_fste_cerTimesWAccum_imag_len 1
+#define reg_fste_cerTimesWAccum_imag_lsb 0
+#define xd_p_reg_fste_cost  (*(volatile byte xdata *) 0xF5A7)
+#define    p_reg_fste_cost  0xF5A7
+#define reg_fste_cost_pos 0
+#define reg_fste_cost_len 1
+#define reg_fste_cost_lsb 0
+#define xd_p_fd_tpsd_en (*(volatile byte xdata *) 0xF5A8)
+#define    p_fd_tpsd_en 0xF5A8
+#define fd_tpsd_en_pos 0
+#define fd_tpsd_en_len 1
+#define fd_tpsd_en_lsb 0
+#define xd_p_fd_tpsd_lock   (*(volatile byte xdata *) 0xF5A9)
+#define    p_fd_tpsd_lock   0xF5A9
+#define fd_tpsd_lock_pos 0
+#define fd_tpsd_lock_len 1
+#define fd_tpsd_lock_lsb 0
+#define xd_r_fd_tpsd_s19    (*(volatile byte xdata *) 0xF5AA)
+#define    r_fd_tpsd_s19    0xF5AA
+#define fd_tpsd_s19_pos 0
+#define fd_tpsd_s19_len 1
+#define fd_tpsd_s19_lsb 0
+#define xd_r_fd_tpsd_s17    (*(volatile byte xdata *) 0xF5AB)
+#define    r_fd_tpsd_s17    0xF5AB
+#define fd_tpsd_s17_pos 0
+#define fd_tpsd_s17_len 1
+#define fd_tpsd_s17_lsb 0
+#define xd_p_fd_sfr_ste_en  (*(volatile byte xdata *) 0xF5AC)
+#define    p_fd_sfr_ste_en  0xF5AC
+#define fd_sfr_ste_en_pos 0
+#define fd_sfr_ste_en_len 1
+#define fd_sfr_ste_en_lsb 0
+#define xd_p_fd_sfr_ste_mode    (*(volatile byte xdata *) 0xF5AD)
+#define    p_fd_sfr_ste_mode    0xF5AD
+#define fd_sfr_ste_mode_pos 0
+#define fd_sfr_ste_mode_len 2
+#define fd_sfr_ste_mode_lsb 0
+#define xd_p_fd_sfr_ste_done    (*(volatile byte xdata *) 0xF5AE)
+#define    p_fd_sfr_ste_done    0xF5AE
+#define fd_sfr_ste_done_pos 0
+#define fd_sfr_ste_done_len 1
+#define fd_sfr_ste_done_lsb 0
+#define xd_p_reg_cfoe_ffoe_en   (*(volatile byte xdata *) 0xF5AF)
+#define    p_reg_cfoe_ffoe_en   0xF5AF
+#define reg_cfoe_ffoe_en_pos 0
+#define reg_cfoe_ffoe_en_len 1
+#define reg_cfoe_ffoe_en_lsb 0
+#define xd_p_reg_cfoe_ifoe_en   (*(volatile byte xdata *) 0xF5B0)
+#define    p_reg_cfoe_ifoe_en   0xF5B0
+#define reg_cfoe_ifoe_en_pos 0
+#define reg_cfoe_ifoe_en_len 1
+#define reg_cfoe_ifoe_en_lsb 0
+#define xd_p_reg_cfoe_fot_en    (*(volatile byte xdata *) 0xF5B1)
+#define    p_reg_cfoe_fot_en    0xF5B1
+#define reg_cfoe_fot_en_pos 0
+#define reg_cfoe_fot_en_len 1
+#define reg_cfoe_fot_en_lsb 0
+#define xd_p_reg_cfoe_fot_lm_en (*(volatile byte xdata *) 0xF5B2)
+#define    p_reg_cfoe_fot_lm_en 0xF5B2
+#define reg_cfoe_fot_lm_en_pos 0
+#define reg_cfoe_fot_lm_en_len 1
+#define reg_cfoe_fot_lm_en_lsb 0
+#define xd_p_reg_cfoe_fot_rst   (*(volatile byte xdata *) 0xF5B3)
+#define    p_reg_cfoe_fot_rst   0xF5B3
+#define reg_cfoe_fot_rst_pos 0
+#define reg_cfoe_fot_rst_len 1
+#define reg_cfoe_fot_rst_lsb 0
+#define xd_r_fd_cfoe_ffoe_done  (*(volatile byte xdata *) 0xF5B4)
+#define    r_fd_cfoe_ffoe_done  0xF5B4
+#define fd_cfoe_ffoe_done_pos 0
+#define fd_cfoe_ffoe_done_len 1
+#define fd_cfoe_ffoe_done_lsb 0
+#define xd_p_fd_cfoe_metric_vld (*(volatile byte xdata *) 0xF5B5)
+#define    p_fd_cfoe_metric_vld 0xF5B5
+#define fd_cfoe_metric_vld_pos 0
+#define fd_cfoe_metric_vld_len 1
+#define fd_cfoe_metric_vld_lsb 0
+#define xd_p_reg_cfoe_ifod_vld  (*(volatile byte xdata *) 0xF5B6)
+#define    p_reg_cfoe_ifod_vld  0xF5B6
+#define reg_cfoe_ifod_vld_pos 0
+#define reg_cfoe_ifod_vld_len 1
+#define reg_cfoe_ifod_vld_lsb 0
+#define xd_r_fd_cfoe_ifoe_done  (*(volatile byte xdata *) 0xF5B7)
+#define    r_fd_cfoe_ifoe_done  0xF5B7
+#define fd_cfoe_ifoe_done_pos 0
+#define fd_cfoe_ifoe_done_len 1
+#define fd_cfoe_ifoe_done_lsb 0
+#define xd_p_reg_cfoe_ifoe_spec_inv (*(volatile byte xdata *) 0xF5B8)
+#define    p_reg_cfoe_ifoe_spec_inv 0xF5B8
+#define reg_cfoe_ifoe_spec_inv_pos 0
+#define reg_cfoe_ifoe_spec_inv_len 1
+#define reg_cfoe_ifoe_spec_inv_lsb 0
+#define xd_p_reg_cfoe_divg_int  (*(volatile byte xdata *) 0xF5B9)
+#define    p_reg_cfoe_divg_int  0xF5B9
+#define reg_cfoe_divg_int_pos 0
+#define reg_cfoe_divg_int_len 1
+#define reg_cfoe_divg_int_lsb 0
+#define xd_r_reg_cfoe_divg_flag (*(volatile byte xdata *) 0xF5BA)
+#define    r_reg_cfoe_divg_flag 0xF5BA
+#define reg_cfoe_divg_flag_pos 0
+#define reg_cfoe_divg_flag_len 1
+#define reg_cfoe_divg_flag_lsb 0
+#define xd_p_reg_sfoe_en    (*(volatile byte xdata *) 0xF5BB)
+#define    p_reg_sfoe_en    0xF5BB
+#define reg_sfoe_en_pos 0
+#define reg_sfoe_en_len 1
+#define reg_sfoe_en_lsb 0
+#define xd_p_reg_sfoe_dis   (*(volatile byte xdata *) 0xF5BC)
+#define    p_reg_sfoe_dis   0xF5BC
+#define reg_sfoe_dis_pos 0
+#define reg_sfoe_dis_len 1
+#define reg_sfoe_dis_lsb 0
+#define xd_p_reg_sfoe_rst   (*(volatile byte xdata *) 0xF5BD)
+#define    p_reg_sfoe_rst   0xF5BD
+#define reg_sfoe_rst_pos 0
+#define reg_sfoe_rst_len 1
+#define reg_sfoe_rst_lsb 0
+#define xd_p_reg_sfoe_vld_int   (*(volatile byte xdata *) 0xF5BE)
+#define    p_reg_sfoe_vld_int   0xF5BE
+#define reg_sfoe_vld_int_pos 0
+#define reg_sfoe_vld_int_len 1
+#define reg_sfoe_vld_int_lsb 0
+#define xd_p_reg_sfoe_lm_en (*(volatile byte xdata *) 0xF5BF)
+#define    p_reg_sfoe_lm_en 0xF5BF
+#define reg_sfoe_lm_en_pos 0
+#define reg_sfoe_lm_en_len 1
+#define reg_sfoe_lm_en_lsb 0
+#define xd_p_reg_sfoe_divg_int  (*(volatile byte xdata *) 0xF5C0)
+#define    p_reg_sfoe_divg_int  0xF5C0
+#define reg_sfoe_divg_int_pos 0
+#define reg_sfoe_divg_int_len 1
+#define reg_sfoe_divg_int_lsb 0
+#define xd_r_reg_sfoe_divg_flag (*(volatile byte xdata *) 0xF5C1)
+#define    r_reg_sfoe_divg_flag 0xF5C1
+#define reg_sfoe_divg_flag_pos 0
+#define reg_sfoe_divg_flag_len 1
+#define reg_sfoe_divg_flag_lsb 0
+#define xd_p_reg_fft_rst    (*(volatile byte xdata *) 0xF5C2)
+#define    p_reg_fft_rst    0xF5C2
+#define reg_fft_rst_pos 0
+#define reg_fft_rst_len 1
+#define reg_fft_rst_lsb 0
+#define xd_p_reg_fft_mask2_en   (*(volatile byte xdata *) 0xF5C3)
+#define    p_reg_fft_mask2_en   0xF5C3
+#define reg_fft_mask2_en_pos 0
+#define reg_fft_mask2_en_len 1
+#define reg_fft_mask2_en_lsb 0
+#define xd_p_reg_fft_mask3_en   (*(volatile byte xdata *) 0xF5C4)
+#define    p_reg_fft_mask3_en   0xF5C4
+#define reg_fft_mask3_en_pos 0
+#define reg_fft_mask3_en_len 1
+#define reg_fft_mask3_en_lsb 0
+#define xd_p_reg_fft_crc_en (*(volatile byte xdata *) 0xF5C5)
+#define    p_reg_fft_crc_en 0xF5C5
+#define reg_fft_crc_en_pos 0
+#define reg_fft_crc_en_len 1
+#define reg_fft_crc_en_lsb 0
+#define xd_p_reg_fft_mask0_en   (*(volatile byte xdata *) 0xF5C6)
+#define    p_reg_fft_mask0_en   0xF5C6
+#define reg_fft_mask0_en_pos 0
+#define reg_fft_mask0_en_len 1
+#define reg_fft_mask0_en_lsb 0
+#define xd_p_reg_fft_mask1_en   (*(volatile byte xdata *) 0xF5C7)
+#define    p_reg_fft_mask1_en   0xF5C7
+#define reg_fft_mask1_en_pos 0
+#define reg_fft_mask1_en_len 1
+#define reg_fft_mask1_en_lsb 0
+#define xd_p_fd_fste_en (*(volatile byte xdata *) 0xF5C8)
+#define    p_fd_fste_en 0xF5C8
+#define fd_fste_en_pos 0
+#define fd_fste_en_len 1
+#define fd_fste_en_lsb 0
+#define xd_p_reg_feq_eh2_comp_en    (*(volatile byte xdata *) 0xF5C9)
+#define    p_reg_feq_eh2_comp_en    0xF5C9
+#define reg_feq_eh2_comp_en_pos 0
+#define reg_feq_eh2_comp_en_len 1
+#define reg_feq_eh2_comp_en_lsb 0
+#define xd_p_reg_feq_read_update    (*(volatile byte xdata *) 0xF5CA)
+#define    p_reg_feq_read_update    0xF5CA
+#define reg_feq_read_update_pos 0
+#define reg_feq_read_update_len 1
+#define reg_feq_read_update_lsb 0
+#define xd_p_reg_feq_data_vld   (*(volatile byte xdata *) 0xF5CB)
+#define    p_reg_feq_data_vld   0xF5CB
+#define reg_feq_data_vld_pos 0
+#define reg_feq_data_vld_len 1
+#define reg_feq_data_vld_lsb 0
+#define xd_p_reg_feq_tone_idx_7_0   (*(volatile byte xdata *) 0xF5CC)
+#define    p_reg_feq_tone_idx_7_0   0xF5CC
+#define reg_feq_tone_idx_7_0_pos 0
+#define reg_feq_tone_idx_7_0_len 8
+#define reg_feq_tone_idx_7_0_lsb 0
+#define xd_p_reg_feq_tone_idx_12_8  (*(volatile byte xdata *) 0xF5CD)
+#define    p_reg_feq_tone_idx_12_8  0xF5CD
+#define reg_feq_tone_idx_12_8_pos 0
+#define reg_feq_tone_idx_12_8_len 5
+#define reg_feq_tone_idx_12_8_lsb 8
+#define xd_r_reg_feq_data_re_7_0    (*(volatile byte xdata *) 0xF5CE)
+#define    r_reg_feq_data_re_7_0    0xF5CE
+#define reg_feq_data_re_7_0_pos 0
+#define reg_feq_data_re_7_0_len 8
+#define reg_feq_data_re_7_0_lsb 0
+#define xd_r_reg_feq_data_re_15_8   (*(volatile byte xdata *) 0xF5CF)
+#define    r_reg_feq_data_re_15_8   0xF5CF
+#define reg_feq_data_re_15_8_pos 0
+#define reg_feq_data_re_15_8_len 8
+#define reg_feq_data_re_15_8_lsb 8
+#define xd_r_reg_feq_data_re_21_16  (*(volatile byte xdata *) 0xF5D0)
+#define    r_reg_feq_data_re_21_16  0xF5D0
+#define reg_feq_data_re_21_16_pos 0
+#define reg_feq_data_re_21_16_len 6
+#define reg_feq_data_re_21_16_lsb 16
+#define xd_r_reg_feq_data_im_7_0    (*(volatile byte xdata *) 0xF5D1)
+#define    r_reg_feq_data_im_7_0    0xF5D1
+#define reg_feq_data_im_7_0_pos 0
+#define reg_feq_data_im_7_0_len 8
+#define reg_feq_data_im_7_0_lsb 0
+#define xd_r_reg_feq_data_im_15_8   (*(volatile byte xdata *) 0xF5D2)
+#define    r_reg_feq_data_im_15_8   0xF5D2
+#define reg_feq_data_im_15_8_pos 0
+#define reg_feq_data_im_15_8_len 8
+#define reg_feq_data_im_15_8_lsb 8
+#define xd_r_reg_feq_data_im_21_16  (*(volatile byte xdata *) 0xF5D3)
+#define    r_reg_feq_data_im_21_16  0xF5D3
+#define reg_feq_data_im_21_16_pos 0
+#define reg_feq_data_im_21_16_len 6
+#define reg_feq_data_im_21_16_lsb 16
+#define xd_r_reg_feq_data_h2_7_0    (*(volatile byte xdata *) 0xF5D4)
+#define    r_reg_feq_data_h2_7_0    0xF5D4
+#define reg_feq_data_h2_7_0_pos 0
+#define reg_feq_data_h2_7_0_len 8
+#define reg_feq_data_h2_7_0_lsb 0
+#define xd_r_reg_feq_data_h2_15_8   (*(volatile byte xdata *) 0xF5D5)
+#define    r_reg_feq_data_h2_15_8   0xF5D5
+#define reg_feq_data_h2_15_8_pos 0
+#define reg_feq_data_h2_15_8_len 8
+#define reg_feq_data_h2_15_8_lsb 8
+#define xd_r_reg_feq_data_h2_18_16  (*(volatile byte xdata *) 0xF5D6)
+#define    r_reg_feq_data_h2_18_16  0xF5D6
+#define reg_feq_data_h2_18_16_pos 0
+#define reg_feq_data_h2_18_16_len 3
+#define reg_feq_data_h2_18_16_lsb 16
+#define xd_p_reg_fs_en  (*(volatile byte xdata *) 0xF5D7)
+#define    p_reg_fs_en  0xF5D7
+#define reg_fs_en_pos 0
+#define reg_fs_en_len 1
+#define reg_fs_en_lsb 0
+#define xd_p_reg_fs_offset  (*(volatile byte xdata *) 0xF5D8)
+#define    p_reg_fs_offset  0xF5D8
+#define reg_fs_offset_pos 0
+#define reg_fs_offset_len 3
+#define reg_fs_offset_lsb 0
+#define xd_p_reg_fs_debug   (*(volatile byte xdata *) 0xF5D9)
+#define    p_reg_fs_debug   0xF5D9
+#define reg_fs_debug_pos 0
+#define reg_fs_debug_len 1
+#define reg_fs_debug_lsb 0
+#define xd_p_reg_fs_half_inv    (*(volatile byte xdata *) 0xF5DA)
+#define    p_reg_fs_half_inv    0xF5DA
+#define reg_fs_half_inv_pos 0
+#define reg_fs_half_inv_len 1
+#define reg_fs_half_inv_lsb 0
+#define xd_p_reg_cdpf_currentfftposition_7_0    (*(volatile byte xdata *) 0xF5DB)
+#define    p_reg_cdpf_currentfftposition_7_0    0xF5DB
+#define reg_cdpf_currentfftposition_7_0_pos 0
+#define reg_cdpf_currentfftposition_7_0_len 8
+#define reg_cdpf_currentfftposition_7_0_lsb 0
+#define xd_p_reg_cdpf_currentfftposition_14_8   (*(volatile byte xdata *) 0xF5DC)
+#define    p_reg_cdpf_currentfftposition_14_8   0xF5DC
+#define reg_cdpf_currentfftposition_14_8_pos 0
+#define reg_cdpf_currentfftposition_14_8_len 7
+#define reg_cdpf_currentfftposition_14_8_lsb 8
+#define xd_r_reg_cdpf_fftshift_7_0  (*(volatile byte xdata *) 0xF5DD)
+#define    r_reg_cdpf_fftshift_7_0  0xF5DD
+#define reg_cdpf_fftshift_7_0_pos 0
+#define reg_cdpf_fftshift_7_0_len 8
+#define reg_cdpf_fftshift_7_0_lsb 0
+#define xd_r_reg_cdpf_fftshift_13_8 (*(volatile byte xdata *) 0xF5DE)
+#define    r_reg_cdpf_fftshift_13_8 0xF5DE
+#define reg_cdpf_fftshift_13_8_pos 0
+#define reg_cdpf_fftshift_13_8_len 6
+#define reg_cdpf_fftshift_13_8_lsb 8
+#define xd_p_reg_cdpf_channelpowerdown_7_0  (*(volatile byte xdata *) 0xF5DF)
+#define    p_reg_cdpf_channelpowerdown_7_0  0xF5DF
+#define reg_cdpf_channelpowerdown_7_0_pos 0
+#define reg_cdpf_channelpowerdown_7_0_len 8
+#define reg_cdpf_channelpowerdown_7_0_lsb 0
+#define xd_p_reg_cdpf_channelpowerdown_10_8 (*(volatile byte xdata *) 0xF5E0)
+#define    p_reg_cdpf_channelpowerdown_10_8 0xF5E0
+#define reg_cdpf_channelpowerdown_10_8_pos 0
+#define reg_cdpf_channelpowerdown_10_8_len 3
+#define reg_cdpf_channelpowerdown_10_8_lsb 8
+#define xd_p_reg_cdpf_state (*(volatile byte xdata *) 0xF5E1)
+#define    p_reg_cdpf_state 0xF5E1
+#define reg_cdpf_state_pos 0
+#define reg_cdpf_state_len 4
+#define reg_cdpf_state_lsb 0
+#define xd_p_reg_cdpf_echotestsearchingrange    (*(volatile byte xdata *) 0xF5E2)
+#define    p_reg_cdpf_echotestsearchingrange    0xF5E2
+#define reg_cdpf_echotestsearchingrange_pos 0
+#define reg_cdpf_echotestsearchingrange_len 8
+#define reg_cdpf_echotestsearchingrange_lsb 0
+#define xd_p_reg_cdpf_rxsymboldelay (*(volatile byte xdata *) 0xF5E3)
+#define    p_reg_cdpf_rxsymboldelay 0xF5E3
+#define reg_cdpf_rxsymboldelay_pos 0
+#define reg_cdpf_rxsymboldelay_len 4
+#define reg_cdpf_rxsymboldelay_lsb 0
+#define xd_p_reg_cdpf_ceavesymbolno (*(volatile byte xdata *) 0xF5E4)
+#define    p_reg_cdpf_ceavesymbolno 0xF5E4
+#define reg_cdpf_ceavesymbolno_pos 0
+#define reg_cdpf_ceavesymbolno_len 4
+#define reg_cdpf_ceavesymbolno_lsb 0
+#define xd_p_reg_cdpf_ceshift   (*(volatile byte xdata *) 0xF5E5)
+#define    p_reg_cdpf_ceshift   0xF5E5
+#define reg_cdpf_ceshift_pos 0
+#define reg_cdpf_ceshift_len 3
+#define reg_cdpf_ceshift_lsb 0
+#define xd_p_reg_cdpf_postpreechotry    (*(volatile byte xdata *) 0xF5E6)
+#define    p_reg_cdpf_postpreechotry    0xF5E6
+#define reg_cdpf_postpreechotry_pos 0
+#define reg_cdpf_postpreechotry_len 2
+#define reg_cdpf_postpreechotry_lsb 0
+#define xd_p_reg_cdpf_en    (*(volatile byte xdata *) 0xF5E7)
+#define    p_reg_cdpf_en    0xF5E7
+#define reg_cdpf_en_pos 0
+#define reg_cdpf_en_len 1
+#define reg_cdpf_en_lsb 0
+#define xd_p_reg_cdpf_stateready    (*(volatile byte xdata *) 0xF5E8)
+#define    p_reg_cdpf_stateready    0xF5E8
+#define reg_cdpf_stateready_pos 0
+#define reg_cdpf_stateready_len 1
+#define reg_cdpf_stateready_lsb 0
+#define xd_r_reg_cdpf_prepostpowercompare   (*(volatile byte xdata *) 0xF5E9)
+#define    r_reg_cdpf_prepostpowercompare   0xF5E9
+#define reg_cdpf_prepostpowercompare_pos 0
+#define reg_cdpf_prepostpowercompare_len 1
+#define reg_cdpf_prepostpowercompare_lsb 0
+#define xd_r_reg_cdpf_candidateno   (*(volatile byte xdata *) 0xF5EA)
+#define    r_reg_cdpf_candidateno   0xF5EA
+#define reg_cdpf_candidateno_pos 0
+#define reg_cdpf_candidateno_len 6
+#define reg_cdpf_candidateno_lsb 0
+#define xd_p_reg_cdpf_preechopower_7_0  (*(volatile byte xdata *) 0xF5EB)
+#define    p_reg_cdpf_preechopower_7_0  0xF5EB
+#define reg_cdpf_preechopower_7_0_pos 0
+#define reg_cdpf_preechopower_7_0_len 8
+#define reg_cdpf_preechopower_7_0_lsb 0
+#define xd_p_reg_cdpf_preechopower_15_8 (*(volatile byte xdata *) 0xF5EC)
+#define    p_reg_cdpf_preechopower_15_8 0xF5EC
+#define reg_cdpf_preechopower_15_8_pos 0
+#define reg_cdpf_preechopower_15_8_len 8
+#define reg_cdpf_preechopower_15_8_lsb 8
+#define xd_p_reg_cdpf_postechopower_7_0 (*(volatile byte xdata *) 0xF5ED)
+#define    p_reg_cdpf_postechopower_7_0 0xF5ED
+#define reg_cdpf_postechopower_7_0_pos 0
+#define reg_cdpf_postechopower_7_0_len 8
+#define reg_cdpf_postechopower_7_0_lsb 0
+#define xd_p_reg_cdpf_postechopower_15_8    (*(volatile byte xdata *) 0xF5EE)
+#define    p_reg_cdpf_postechopower_15_8    0xF5EE
+#define reg_cdpf_postechopower_15_8_pos 0
+#define reg_cdpf_postechopower_15_8_len 8
+#define reg_cdpf_postechopower_15_8_lsb 8
+#define xd_p_reg_cdpf_searchingend  (*(volatile byte xdata *) 0xF5EF)
+#define    p_reg_cdpf_searchingend  0xF5EF
+#define reg_cdpf_searchingend_pos 0
+#define reg_cdpf_searchingend_len 8
+#define reg_cdpf_searchingend_lsb 0
+#define xd_r_reg_cdpf_candidate_7_0 (*(volatile byte xdata *) 0xF5F0)
+#define    r_reg_cdpf_candidate_7_0 0xF5F0
+#define reg_cdpf_candidate_7_0_pos 0
+#define reg_cdpf_candidate_7_0_len 8
+#define reg_cdpf_candidate_7_0_lsb 0
+#define xd_r_reg_cdpf_candidate_15_8    (*(volatile byte xdata *) 0xF5F1)
+#define    r_reg_cdpf_candidate_15_8    0xF5F1
+#define reg_cdpf_candidate_15_8_pos 0
+#define reg_cdpf_candidate_15_8_len 8
+#define reg_cdpf_candidate_15_8_lsb 8
+#define xd_p_reg_cdpf_candidate_rptr    (*(volatile byte xdata *) 0xF5F2)
+#define    p_reg_cdpf_candidate_rptr    0xF5F2
+#define reg_cdpf_candidate_rptr_pos 0
+#define reg_cdpf_candidate_rptr_len 7
+#define reg_cdpf_candidate_rptr_lsb 0
+#define xd_p_reg_cdpf_candidate_rptr_force  (*(volatile byte xdata *) 0xF5F3)
+#define    p_reg_cdpf_candidate_rptr_force  0xF5F3
+#define reg_cdpf_candidate_rptr_force_pos 0
+#define reg_cdpf_candidate_rptr_force_len 1
+#define reg_cdpf_candidate_rptr_force_lsb 0
+#define xd_p_reg_cdpf_trialshiftoffset_7_0  (*(volatile byte xdata *) 0xF5F4)
+#define    p_reg_cdpf_trialshiftoffset_7_0  0xF5F4
+#define reg_cdpf_trialshiftoffset_7_0_pos 0
+#define reg_cdpf_trialshiftoffset_7_0_len 8
+#define reg_cdpf_trialshiftoffset_7_0_lsb 0
+#define xd_p_reg_cdpf_trialshiftoffset_13_8 (*(volatile byte xdata *) 0xF5F5)
+#define    p_reg_cdpf_trialshiftoffset_13_8 0xF5F5
+#define reg_cdpf_trialshiftoffset_13_8_pos 0
+#define reg_cdpf_trialshiftoffset_13_8_len 6
+#define reg_cdpf_trialshiftoffset_13_8_lsb 8
+#define xd_p_reg_cdpf_channellength_7_0 (*(volatile byte xdata *) 0xF5F6)
+#define    p_reg_cdpf_channellength_7_0 0xF5F6
+#define reg_cdpf_channellength_7_0_pos 0
+#define reg_cdpf_channellength_7_0_len 8
+#define reg_cdpf_channellength_7_0_lsb 0
+#define xd_p_reg_cdpf_channellength_12_8    (*(volatile byte xdata *) 0xF5F7)
+#define    p_reg_cdpf_channellength_12_8    0xF5F7
+#define reg_cdpf_channellength_12_8_pos 0
+#define reg_cdpf_channellength_12_8_len 5
+#define reg_cdpf_channellength_12_8_lsb 8
+#define xd_p_reg_cdpf_hardwaresort  (*(volatile byte xdata *) 0xF5F8)
+#define    p_reg_cdpf_hardwaresort  0xF5F8
+#define reg_cdpf_hardwaresort_pos 0
+#define reg_cdpf_hardwaresort_len 1
+#define reg_cdpf_hardwaresort_lsb 0
+#define xd_p_reg_cdpf_maxcandidateno    (*(volatile byte xdata *) 0xF5F9)
+#define    p_reg_cdpf_maxcandidateno    0xF5F9
+#define reg_cdpf_maxcandidateno_pos 0
+#define reg_cdpf_maxcandidateno_len 3
+#define reg_cdpf_maxcandidateno_lsb 0
+#define xd_p_reg_cdpf_channelleftindex  (*(volatile byte xdata *) 0xF5FA)
+#define    p_reg_cdpf_channelleftindex  0xF5FA
+#define reg_cdpf_channelleftindex_pos 0
+#define reg_cdpf_channelleftindex_len 4
+#define reg_cdpf_channelleftindex_lsb 0
+#define xd_r_reg_cdpf_fdishift_7_0  (*(volatile byte xdata *) 0xF5FB)
+#define    r_reg_cdpf_fdishift_7_0  0xF5FB
+#define reg_cdpf_fdishift_7_0_pos 0
+#define reg_cdpf_fdishift_7_0_len 8
+#define reg_cdpf_fdishift_7_0_lsb 0
+#define xd_r_reg_cdpf_fdishift_15_8 (*(volatile byte xdata *) 0xF5FC)
+#define    r_reg_cdpf_fdishift_15_8 0xF5FC
+#define reg_cdpf_fdishift_15_8_pos 0
+#define reg_cdpf_fdishift_15_8_len 8
+#define reg_cdpf_fdishift_15_8_lsb 8
+#define xd_p_reg_cdpf_guardband (*(volatile byte xdata *) 0xF5FD)
+#define    p_reg_cdpf_guardband 0xF5FD
+#define reg_cdpf_guardband_pos 0
+#define reg_cdpf_guardband_len 5
+#define reg_cdpf_guardband_lsb 0
+#define xd_p_reg_cdpf_maxtonemaxindex_7_0   (*(volatile byte xdata *) 0xF5FE)
+#define    p_reg_cdpf_maxtonemaxindex_7_0   0xF5FE
+#define reg_cdpf_maxtonemaxindex_7_0_pos 0
+#define reg_cdpf_maxtonemaxindex_7_0_len 8
+#define reg_cdpf_maxtonemaxindex_7_0_lsb 0
+#define xd_p_reg_cdpf_maxtonemaxindex_12_8  (*(volatile byte xdata *) 0xF5FF)
+#define    p_reg_cdpf_maxtonemaxindex_12_8  0xF5FF
+#define reg_cdpf_maxtonemaxindex_12_8_pos 0
+#define reg_cdpf_maxtonemaxindex_12_8_len 5
+#define reg_cdpf_maxtonemaxindex_12_8_lsb 8
+#define xd_p_reg_cdpf_fdiw0 (*(volatile byte xdata *) 0xF600)
+#define    p_reg_cdpf_fdiw0 0xF600
+#define reg_cdpf_fdiw0_pos 0
+#define reg_cdpf_fdiw0_len 7
+#define reg_cdpf_fdiw0_lsb 0
+#define xd_p_reg_cdpf_fdiw1 (*(volatile byte xdata *) 0xF601)
+#define    p_reg_cdpf_fdiw1 0xF601
+#define reg_cdpf_fdiw1_pos 0
+#define reg_cdpf_fdiw1_len 7
+#define reg_cdpf_fdiw1_lsb 0
+#define xd_p_reg_cdpf_fdiw2 (*(volatile byte xdata *) 0xF602)
+#define    p_reg_cdpf_fdiw2 0xF602
+#define reg_cdpf_fdiw2_pos 0
+#define reg_cdpf_fdiw2_len 7
+#define reg_cdpf_fdiw2_lsb 0
+#define xd_p_reg_cdpf_fdiw3 (*(volatile byte xdata *) 0xF603)
+#define    p_reg_cdpf_fdiw3 0xF603
+#define reg_cdpf_fdiw3_pos 0
+#define reg_cdpf_fdiw3_len 7
+#define reg_cdpf_fdiw3_lsb 0
+#define xd_p_reg_cdpf_fdiw4 (*(volatile byte xdata *) 0xF604)
+#define    p_reg_cdpf_fdiw4 0xF604
+#define reg_cdpf_fdiw4_pos 0
+#define reg_cdpf_fdiw4_len 7
+#define reg_cdpf_fdiw4_lsb 0
+#define xd_p_reg_cdpf_fdiw5 (*(volatile byte xdata *) 0xF605)
+#define    p_reg_cdpf_fdiw5 0xF605
+#define reg_cdpf_fdiw5_pos 0
+#define reg_cdpf_fdiw5_len 7
+#define reg_cdpf_fdiw5_lsb 0
+#define xd_p_reg_cdpf_fdiw6 (*(volatile byte xdata *) 0xF606)
+#define    p_reg_cdpf_fdiw6 0xF606
+#define reg_cdpf_fdiw6_pos 0
+#define reg_cdpf_fdiw6_len 7
+#define reg_cdpf_fdiw6_lsb 0
+#define xd_p_reg_cdpf_fdiw7 (*(volatile byte xdata *) 0xF607)
+#define    p_reg_cdpf_fdiw7 0xF607
+#define reg_cdpf_fdiw7_pos 0
+#define reg_cdpf_fdiw7_len 7
+#define reg_cdpf_fdiw7_lsb 0
+#define xd_r_reg_cdpf_fdiwindowsize (*(volatile byte xdata *) 0xF608)
+#define    r_reg_cdpf_fdiwindowsize 0xF608
+#define reg_cdpf_fdiwindowsize_pos 0
+#define reg_cdpf_fdiwindowsize_len 4
+#define reg_cdpf_fdiwindowsize_lsb 0
+#define xd_p_reg_stes_mode  (*(volatile byte xdata *) 0xF609)
+#define    p_reg_stes_mode  0xF609
+#define reg_stes_mode_pos 0
+#define reg_stes_mode_len 1
+#define reg_stes_mode_lsb 0
+#define xd_p_reg_stes_done_st   (*(volatile byte xdata *) 0xF60A)
+#define    p_reg_stes_done_st   0xF60A
+#define reg_stes_done_st_pos 0
+#define reg_stes_done_st_len 2
+#define reg_stes_done_st_lsb 0
+#define xd_p_reg_stes_done  (*(volatile byte xdata *) 0xF60B)
+#define    p_reg_stes_done  0xF60B
+#define reg_stes_done_pos 0
+#define reg_stes_done_len 1
+#define reg_stes_done_lsb 0
+#define xd_p_reg_stes_timing_7_0    (*(volatile byte xdata *) 0xF60C)
+#define    p_reg_stes_timing_7_0    0xF60C
+#define reg_stes_timing_7_0_pos 0
+#define reg_stes_timing_7_0_len 8
+#define reg_stes_timing_7_0_lsb 0
+#define xd_p_reg_stes_timing_15_8   (*(volatile byte xdata *) 0xF60D)
+#define    p_reg_stes_timing_15_8   0xF60D
+#define reg_stes_timing_15_8_pos 0
+#define reg_stes_timing_15_8_len 8
+#define reg_stes_timing_15_8_lsb 8
+#define xd_p_reg_stes_sym_tot_adj_thre_7_0  (*(volatile byte xdata *) 0xF60E)
+#define    p_reg_stes_sym_tot_adj_thre_7_0  0xF60E
+#define reg_stes_sym_tot_adj_thre_7_0_pos 0
+#define reg_stes_sym_tot_adj_thre_7_0_len 8
+#define reg_stes_sym_tot_adj_thre_7_0_lsb 0
+#define xd_p_reg_stes_sym_tot_adj_thre_15_8 (*(volatile byte xdata *) 0xF60F)
+#define    p_reg_stes_sym_tot_adj_thre_15_8 0xF60F
+#define reg_stes_sym_tot_adj_thre_15_8_pos 0
+#define reg_stes_sym_tot_adj_thre_15_8_len 8
+#define reg_stes_sym_tot_adj_thre_15_8_lsb 8
+#define xd_p_reg_stes_sym_thre_9_2  (*(volatile byte xdata *) 0xF610)
+#define    p_reg_stes_sym_thre_9_2  0xF610
+#define reg_stes_sym_thre_9_2_pos 0
+#define reg_stes_sym_thre_9_2_len 8
+#define reg_stes_sym_thre_9_2_lsb 0
+#define xd_p_reg_stes_sym_wo_adj_thre_9_2   (*(volatile byte xdata *) 0xF611)
+#define    p_reg_stes_sym_wo_adj_thre_9_2   0xF611
+#define reg_stes_sym_wo_adj_thre_9_2_pos 0
+#define reg_stes_sym_wo_adj_thre_9_2_len 8
+#define reg_stes_sym_wo_adj_thre_9_2_lsb 0
+#define xd_p_reg_fste_i_adj_7_0 (*(volatile byte xdata *) 0xF612)
+#define    p_reg_fste_i_adj_7_0 0xF612
+#define reg_fste_i_adj_7_0_pos 0
+#define reg_fste_i_adj_7_0_len 8
+#define reg_fste_i_adj_7_0_lsb 0
+#define xd_p_reg_fste_i_adj_15_8    (*(volatile byte xdata *) 0xF613)
+#define    p_reg_fste_i_adj_15_8    0xF613
+#define reg_fste_i_adj_15_8_pos 0
+#define reg_fste_i_adj_15_8_len 8
+#define reg_fste_i_adj_15_8_lsb 8
+#define xd_r_fd_stes_iadj_val_7_0   (*(volatile byte xdata *) 0xF614)
+#define    r_fd_stes_iadj_val_7_0   0xF614
+#define fd_stes_iadj_val_7_0_pos 0
+#define fd_stes_iadj_val_7_0_len 8
+#define fd_stes_iadj_val_7_0_lsb 0
+#define xd_r_fd_stes_iadj_val_15_8  (*(volatile byte xdata *) 0xF615)
+#define    r_fd_stes_iadj_val_15_8  0xF615
+#define fd_stes_iadj_val_15_8_pos 0
+#define fd_stes_iadj_val_15_8_len 8
+#define fd_stes_iadj_val_15_8_lsb 8
+#define xd_r_fd_stes_symb_cnt_9_2   (*(volatile byte xdata *) 0xF616)
+#define    r_fd_stes_symb_cnt_9_2   0xF616
+#define fd_stes_symb_cnt_9_2_pos 0
+#define fd_stes_symb_cnt_9_2_len 8
+#define fd_stes_symb_cnt_9_2_lsb 0
+#define xd_r_fd_stes_snoi_cnt_9_2   (*(volatile byte xdata *) 0xF617)
+#define    r_fd_stes_snoi_cnt_9_2   0xF617
+#define fd_stes_snoi_cnt_9_2_pos 0
+#define fd_stes_snoi_cnt_9_2_len 8
+#define fd_stes_snoi_cnt_9_2_lsb 0
+#define xd_r_fd_last_iadj_val_7_0   (*(volatile byte xdata *) 0xF618)
+#define    r_fd_last_iadj_val_7_0   0xF618
+#define fd_last_iadj_val_7_0_pos 0
+#define fd_last_iadj_val_7_0_len 8
+#define fd_last_iadj_val_7_0_lsb 0
+#define xd_r_fd_last_iadj_val_15_8  (*(volatile byte xdata *) 0xF619)
+#define    r_fd_last_iadj_val_15_8  0xF619
+#define fd_last_iadj_val_15_8_pos 0
+#define fd_last_iadj_val_15_8_len 8
+#define fd_last_iadj_val_15_8_lsb 8
+#define xd_p_reg_stes_bypass    (*(volatile byte xdata *) 0xF61A)
+#define    p_reg_stes_bypass    0xF61A
+#define reg_stes_bypass_pos 0
+#define reg_stes_bypass_len 1
+#define reg_stes_bypass_lsb 0
+#define xd_p_reg_stes_best_timing_idx   (*(volatile byte xdata *) 0xF61B)
+#define    p_reg_stes_best_timing_idx   0xF61B
+#define reg_stes_best_timing_idx_pos 0
+#define reg_stes_best_timing_idx_len 4
+#define reg_stes_best_timing_idx_lsb 0
+#define xd_p_reg_stes_iadj_val_7_0  (*(volatile byte xdata *) 0xF61C)
+#define    p_reg_stes_iadj_val_7_0  0xF61C
+#define reg_stes_iadj_val_7_0_pos 0
+#define reg_stes_iadj_val_7_0_len 8
+#define reg_stes_iadj_val_7_0_lsb 0
+#define xd_p_reg_stes_iadj_val_15_8 (*(volatile byte xdata *) 0xF61D)
+#define    p_reg_stes_iadj_val_15_8 0xF61D
+#define reg_stes_iadj_val_15_8_pos 0
+#define reg_stes_iadj_val_15_8_len 8
+#define reg_stes_iadj_val_15_8_lsb 8
+#define xd_p_reg_p_ste_start_guard_7_0  (*(volatile byte xdata *) 0xF620)
+#define    p_reg_p_ste_start_guard_7_0  0xF620
+#define reg_p_ste_start_guard_7_0_pos 0
+#define reg_p_ste_start_guard_7_0_len 8
+#define reg_p_ste_start_guard_7_0_lsb 0
+#define xd_p_reg_p_ste_start_guard_9_8  (*(volatile byte xdata *) 0xF621)
+#define    p_reg_p_ste_start_guard_9_8  0xF621
+#define reg_p_ste_start_guard_9_8_pos 0
+#define reg_p_ste_start_guard_9_8_len 2
+#define reg_p_ste_start_guard_9_8_lsb 8
+#define xd_p_reg_p_ste_end_guard_7_0    (*(volatile byte xdata *) 0xF622)
+#define    p_reg_p_ste_end_guard_7_0    0xF622
+#define reg_p_ste_end_guard_7_0_pos 0
+#define reg_p_ste_end_guard_7_0_len 8
+#define reg_p_ste_end_guard_7_0_lsb 0
+#define xd_p_reg_p_ste_end_guard_9_8    (*(volatile byte xdata *) 0xF623)
+#define    p_reg_p_ste_end_guard_9_8    0xF623
+#define reg_p_ste_end_guard_9_8_pos 0
+#define reg_p_ste_end_guard_9_8_len 2
+#define reg_p_ste_end_guard_9_8_lsb 8
+#define xd_r_reg_r_ste_wrong_beacon_count   (*(volatile byte xdata *) 0xF624)
+#define    r_reg_r_ste_wrong_beacon_count   0xF624
+#define reg_r_ste_wrong_beacon_count_pos 0
+#define reg_r_ste_wrong_beacon_count_len 7
+#define reg_r_ste_wrong_beacon_count_lsb 0
+#define xd_p_reg_p_fccid_en (*(volatile byte xdata *) 0xF625)
+#define    p_reg_p_fccid_en 0xF625
+#define reg_p_fccid_en_pos 0
+#define reg_p_fccid_en_len 1
+#define reg_p_fccid_en_lsb 0
+#define xd_p_reg_p_fccid_fft_ave_symbol_num (*(volatile byte xdata *) 0xF626)
+#define    p_reg_p_fccid_fft_ave_symbol_num 0xF626
+#define reg_p_fccid_fft_ave_symbol_num_pos 0
+#define reg_p_fccid_fft_ave_symbol_num_len 6
+#define reg_p_fccid_fft_ave_symbol_num_lsb 0
+#define xd_p_reg_p_fccid_fft_work_start_tone_7_0    (*(volatile byte xdata *) 0xF627)
+#define    p_reg_p_fccid_fft_work_start_tone_7_0    0xF627
+#define reg_p_fccid_fft_work_start_tone_7_0_pos 0
+#define reg_p_fccid_fft_work_start_tone_7_0_len 8
+#define reg_p_fccid_fft_work_start_tone_7_0_lsb 0
+#define xd_p_reg_p_fccid_fft_work_start_tone_12_8   (*(volatile byte xdata *) 0xF628)
+#define    p_reg_p_fccid_fft_work_start_tone_12_8   0xF628
+#define reg_p_fccid_fft_work_start_tone_12_8_pos 0
+#define reg_p_fccid_fft_work_start_tone_12_8_len 5
+#define reg_p_fccid_fft_work_start_tone_12_8_lsb 8
+#define xd_p_reg_p_fccid_fft_work_end_tone_7_0  (*(volatile byte xdata *) 0xF629)
+#define    p_reg_p_fccid_fft_work_end_tone_7_0  0xF629
+#define reg_p_fccid_fft_work_end_tone_7_0_pos 0
+#define reg_p_fccid_fft_work_end_tone_7_0_len 8
+#define reg_p_fccid_fft_work_end_tone_7_0_lsb 0
+#define xd_p_reg_p_fccid_fft_work_end_tone_12_8 (*(volatile byte xdata *) 0xF62A)
+#define    p_reg_p_fccid_fft_work_end_tone_12_8 0xF62A
+#define reg_p_fccid_fft_work_end_tone_12_8_pos 0
+#define reg_p_fccid_fft_work_end_tone_12_8_len 5
+#define reg_p_fccid_fft_work_end_tone_12_8_lsb 8
+#define xd_p_reg_p_fccid_peak_to_th_divider (*(volatile byte xdata *) 0xF62B)
+#define    p_reg_p_fccid_peak_to_th_divider 0xF62B
+#define reg_p_fccid_peak_to_th_divider_pos 0
+#define reg_p_fccid_peak_to_th_divider_len 4
+#define reg_p_fccid_peak_to_th_divider_lsb 0
+#define xd_p_reg_p_fccid_peak_to_th_mode    (*(volatile byte xdata *) 0xF62C)
+#define    p_reg_p_fccid_peak_to_th_mode    0xF62C
+#define reg_p_fccid_peak_to_th_mode_pos 0
+#define reg_p_fccid_peak_to_th_mode_len 2
+#define reg_p_fccid_peak_to_th_mode_lsb 0
+#define xd_p_reg_p_fccid_search_mode    (*(volatile byte xdata *) 0xF62D)
+#define    p_reg_p_fccid_search_mode    0xF62D
+#define reg_p_fccid_search_mode_pos 0
+#define reg_p_fccid_search_mode_len 1
+#define reg_p_fccid_search_mode_lsb 0
+#define xd_p_reg_p_fccid_group_th   (*(volatile byte xdata *) 0xF62E)
+#define    p_reg_p_fccid_group_th   0xF62E
+#define reg_p_fccid_group_th_pos 0
+#define reg_p_fccid_group_th_len 7
+#define reg_p_fccid_group_th_lsb 0
+#define xd_p_reg_p_fccid_search_rdy (*(volatile byte xdata *) 0xF62F)
+#define    p_reg_p_fccid_search_rdy 0xF62F
+#define reg_p_fccid_search_rdy_pos 0
+#define reg_p_fccid_search_rdy_len 1
+#define reg_p_fccid_search_rdy_lsb 0
+#define xd_r_reg_r_fccid_fft_ave_read_out_7_0   (*(volatile byte xdata *) 0xF630)
+#define    r_reg_r_fccid_fft_ave_read_out_7_0   0xF630
+#define reg_r_fccid_fft_ave_read_out_7_0_pos 0
+#define reg_r_fccid_fft_ave_read_out_7_0_len 8
+#define reg_r_fccid_fft_ave_read_out_7_0_lsb 0
+#define xd_r_reg_r_fccid_fft_ave_read_out_15_8  (*(volatile byte xdata *) 0xF631)
+#define    r_reg_r_fccid_fft_ave_read_out_15_8  0xF631
+#define reg_r_fccid_fft_ave_read_out_15_8_pos 0
+#define reg_r_fccid_fft_ave_read_out_15_8_len 8
+#define reg_r_fccid_fft_ave_read_out_15_8_lsb 8
+#define xd_r_reg_r_fccid_large_tone_num_7_0 (*(volatile byte xdata *) 0xF632)
+#define    r_reg_r_fccid_large_tone_num_7_0 0xF632
+#define reg_r_fccid_large_tone_num_7_0_pos 0
+#define reg_r_fccid_large_tone_num_7_0_len 8
+#define reg_r_fccid_large_tone_num_7_0_lsb 0
+#define xd_r_reg_r_fccid_large_tone_num_12_8    (*(volatile byte xdata *) 0xF633)
+#define    r_reg_r_fccid_large_tone_num_12_8    0xF633
+#define reg_r_fccid_large_tone_num_12_8_pos 0
+#define reg_r_fccid_large_tone_num_12_8_len 5
+#define reg_r_fccid_large_tone_num_12_8_lsb 8
+#define xd_r_reg_r_fccid_cci1_start_tone_7_0    (*(volatile byte xdata *) 0xF634)
+#define    r_reg_r_fccid_cci1_start_tone_7_0    0xF634
+#define reg_r_fccid_cci1_start_tone_7_0_pos 0
+#define reg_r_fccid_cci1_start_tone_7_0_len 8
+#define reg_r_fccid_cci1_start_tone_7_0_lsb 0
+#define xd_r_reg_r_fccid_cci1_start_tone_12_8   (*(volatile byte xdata *) 0xF635)
+#define    r_reg_r_fccid_cci1_start_tone_12_8   0xF635
+#define reg_r_fccid_cci1_start_tone_12_8_pos 0
+#define reg_r_fccid_cci1_start_tone_12_8_len 5
+#define reg_r_fccid_cci1_start_tone_12_8_lsb 8
+#define xd_r_reg_r_fccid_cci1_end_tone_7_0  (*(volatile byte xdata *) 0xF636)
+#define    r_reg_r_fccid_cci1_end_tone_7_0  0xF636
+#define reg_r_fccid_cci1_end_tone_7_0_pos 0
+#define reg_r_fccid_cci1_end_tone_7_0_len 8
+#define reg_r_fccid_cci1_end_tone_7_0_lsb 0
+#define xd_r_reg_r_fccid_cci1_end_tone_12_8 (*(volatile byte xdata *) 0xF637)
+#define    r_reg_r_fccid_cci1_end_tone_12_8 0xF637
+#define reg_r_fccid_cci1_end_tone_12_8_pos 0
+#define reg_r_fccid_cci1_end_tone_12_8_len 5
+#define reg_r_fccid_cci1_end_tone_12_8_lsb 8
+#define xd_r_reg_r_fccid_cci1_peak_7_0  (*(volatile byte xdata *) 0xF638)
+#define    r_reg_r_fccid_cci1_peak_7_0  0xF638
+#define reg_r_fccid_cci1_peak_7_0_pos 0
+#define reg_r_fccid_cci1_peak_7_0_len 8
+#define reg_r_fccid_cci1_peak_7_0_lsb 0
+#define xd_r_reg_r_fccid_cci1_peak_15_8 (*(volatile byte xdata *) 0xF639)
+#define    r_reg_r_fccid_cci1_peak_15_8 0xF639
+#define reg_r_fccid_cci1_peak_15_8_pos 0
+#define reg_r_fccid_cci1_peak_15_8_len 8
+#define reg_r_fccid_cci1_peak_15_8_lsb 8
+#define xd_r_reg_r_fccid_cci2_start_tone_7_0    (*(volatile byte xdata *) 0xF63A)
+#define    r_reg_r_fccid_cci2_start_tone_7_0    0xF63A
+#define reg_r_fccid_cci2_start_tone_7_0_pos 0
+#define reg_r_fccid_cci2_start_tone_7_0_len 8
+#define reg_r_fccid_cci2_start_tone_7_0_lsb 0
+#define xd_r_reg_r_fccid_cci2_start_tone_12_8   (*(volatile byte xdata *) 0xF63B)
+#define    r_reg_r_fccid_cci2_start_tone_12_8   0xF63B
+#define reg_r_fccid_cci2_start_tone_12_8_pos 0
+#define reg_r_fccid_cci2_start_tone_12_8_len 5
+#define reg_r_fccid_cci2_start_tone_12_8_lsb 8
+#define xd_r_reg_r_fccid_cci2_end_tone_7_0  (*(volatile byte xdata *) 0xF63C)
+#define    r_reg_r_fccid_cci2_end_tone_7_0  0xF63C
+#define reg_r_fccid_cci2_end_tone_7_0_pos 0
+#define reg_r_fccid_cci2_end_tone_7_0_len 8
+#define reg_r_fccid_cci2_end_tone_7_0_lsb 0
+#define xd_r_reg_r_fccid_cci2_end_tone_12_8 (*(volatile byte xdata *) 0xF63D)
+#define    r_reg_r_fccid_cci2_end_tone_12_8 0xF63D
+#define reg_r_fccid_cci2_end_tone_12_8_pos 0
+#define reg_r_fccid_cci2_end_tone_12_8_len 5
+#define reg_r_fccid_cci2_end_tone_12_8_lsb 8
+#define xd_r_reg_r_fccid_cci2_peak_7_0  (*(volatile byte xdata *) 0xF63E)
+#define    r_reg_r_fccid_cci2_peak_7_0  0xF63E
+#define reg_r_fccid_cci2_peak_7_0_pos 0
+#define reg_r_fccid_cci2_peak_7_0_len 8
+#define reg_r_fccid_cci2_peak_7_0_lsb 0
+#define xd_r_reg_r_fccid_cci2_peak_15_8 (*(volatile byte xdata *) 0xF63F)
+#define    r_reg_r_fccid_cci2_peak_15_8 0xF63F
+#define reg_r_fccid_cci2_peak_15_8_pos 0
+#define reg_r_fccid_cci2_peak_15_8_len 8
+#define reg_r_fccid_cci2_peak_15_8_lsb 8
+#define xd_r_reg_r_fccid_cci3_start_tone_7_0    (*(volatile byte xdata *) 0xF640)
+#define    r_reg_r_fccid_cci3_start_tone_7_0    0xF640
+#define reg_r_fccid_cci3_start_tone_7_0_pos 0
+#define reg_r_fccid_cci3_start_tone_7_0_len 8
+#define reg_r_fccid_cci3_start_tone_7_0_lsb 0
+#define xd_r_reg_r_fccid_cci3_start_tone_12_8   (*(volatile byte xdata *) 0xF641)
+#define    r_reg_r_fccid_cci3_start_tone_12_8   0xF641
+#define reg_r_fccid_cci3_start_tone_12_8_pos 0
+#define reg_r_fccid_cci3_start_tone_12_8_len 5
+#define reg_r_fccid_cci3_start_tone_12_8_lsb 8
+#define xd_r_reg_r_fccid_cci3_end_tone_7_0  (*(volatile byte xdata *) 0xF642)
+#define    r_reg_r_fccid_cci3_end_tone_7_0  0xF642
+#define reg_r_fccid_cci3_end_tone_7_0_pos 0
+#define reg_r_fccid_cci3_end_tone_7_0_len 8
+#define reg_r_fccid_cci3_end_tone_7_0_lsb 0
+#define xd_r_reg_r_fccid_cci3_end_tone_12_8 (*(volatile byte xdata *) 0xF643)
+#define    r_reg_r_fccid_cci3_end_tone_12_8 0xF643
+#define reg_r_fccid_cci3_end_tone_12_8_pos 0
+#define reg_r_fccid_cci3_end_tone_12_8_len 5
+#define reg_r_fccid_cci3_end_tone_12_8_lsb 8
+#define xd_r_reg_r_fccid_cci3_peak_7_0  (*(volatile byte xdata *) 0xF644)
+#define    r_reg_r_fccid_cci3_peak_7_0  0xF644
+#define reg_r_fccid_cci3_peak_7_0_pos 0
+#define reg_r_fccid_cci3_peak_7_0_len 8
+#define reg_r_fccid_cci3_peak_7_0_lsb 0
+#define xd_r_reg_r_fccid_cci3_peak_15_8 (*(volatile byte xdata *) 0xF645)
+#define    r_reg_r_fccid_cci3_peak_15_8 0xF645
+#define reg_r_fccid_cci3_peak_15_8_pos 0
+#define reg_r_fccid_cci3_peak_15_8_len 8
+#define reg_r_fccid_cci3_peak_15_8_lsb 8
+#define xd_r_reg_r_fccid_cci4_start_tone_7_0    (*(volatile byte xdata *) 0xF646)
+#define    r_reg_r_fccid_cci4_start_tone_7_0    0xF646
+#define reg_r_fccid_cci4_start_tone_7_0_pos 0
+#define reg_r_fccid_cci4_start_tone_7_0_len 8
+#define reg_r_fccid_cci4_start_tone_7_0_lsb 0
+#define xd_r_reg_r_fccid_cci4_start_tone_12_8   (*(volatile byte xdata *) 0xF647)
+#define    r_reg_r_fccid_cci4_start_tone_12_8   0xF647
+#define reg_r_fccid_cci4_start_tone_12_8_pos 0
+#define reg_r_fccid_cci4_start_tone_12_8_len 5
+#define reg_r_fccid_cci4_start_tone_12_8_lsb 8
+#define xd_r_reg_r_fccid_cci4_end_tone_7_0  (*(volatile byte xdata *) 0xF648)
+#define    r_reg_r_fccid_cci4_end_tone_7_0  0xF648
+#define reg_r_fccid_cci4_end_tone_7_0_pos 0
+#define reg_r_fccid_cci4_end_tone_7_0_len 8
+#define reg_r_fccid_cci4_end_tone_7_0_lsb 0
+#define xd_r_reg_r_fccid_cci4_end_tone_12_8 (*(volatile byte xdata *) 0xF649)
+#define    r_reg_r_fccid_cci4_end_tone_12_8 0xF649
+#define reg_r_fccid_cci4_end_tone_12_8_pos 0
+#define reg_r_fccid_cci4_end_tone_12_8_len 5
+#define reg_r_fccid_cci4_end_tone_12_8_lsb 8
+#define xd_r_reg_r_fccid_cci4_peak_7_0  (*(volatile byte xdata *) 0xF64A)
+#define    r_reg_r_fccid_cci4_peak_7_0  0xF64A
+#define reg_r_fccid_cci4_peak_7_0_pos 0
+#define reg_r_fccid_cci4_peak_7_0_len 8
+#define reg_r_fccid_cci4_peak_7_0_lsb 0
+#define xd_r_reg_r_fccid_cci4_peak_15_8 (*(volatile byte xdata *) 0xF64B)
+#define    r_reg_r_fccid_cci4_peak_15_8 0xF64B
+#define reg_r_fccid_cci4_peak_15_8_pos 0
+#define reg_r_fccid_cci4_peak_15_8_len 8
+#define reg_r_fccid_cci4_peak_15_8_lsb 8
+#define xd_r_reg_r_fccid_cci1_rank  (*(volatile byte xdata *) 0xF64C)
+#define    r_reg_r_fccid_cci1_rank  0xF64C
+#define reg_r_fccid_cci1_rank_pos 0
+#define reg_r_fccid_cci1_rank_len 3
+#define reg_r_fccid_cci1_rank_lsb 0
+#define xd_r_reg_r_fccid_cci2_rank  (*(volatile byte xdata *) 0xF64D)
+#define    r_reg_r_fccid_cci2_rank  0xF64D
+#define reg_r_fccid_cci2_rank_pos 0
+#define reg_r_fccid_cci2_rank_len 3
+#define reg_r_fccid_cci2_rank_lsb 0
+#define xd_r_reg_r_fccid_cci3_rank  (*(volatile byte xdata *) 0xF64E)
+#define    r_reg_r_fccid_cci3_rank  0xF64E
+#define reg_r_fccid_cci3_rank_pos 0
+#define reg_r_fccid_cci3_rank_len 3
+#define reg_r_fccid_cci3_rank_lsb 0
+#define xd_r_reg_r_fccid_cci4_rank  (*(volatile byte xdata *) 0xF64F)
+#define    r_reg_r_fccid_cci4_rank  0xF64F
+#define reg_r_fccid_cci4_rank_pos 0
+#define reg_r_fccid_cci4_rank_len 3
+#define reg_r_fccid_cci4_rank_lsb 0
+#define xd_p_reg_p_csi_shift3   (*(volatile byte xdata *) 0xF650)
+#define    p_reg_p_csi_shift3   0xF650
+#define reg_p_csi_shift3_pos 0
+#define reg_p_csi_shift3_len 4
+#define reg_p_csi_shift3_lsb 0
+#define xd_p_reg_p_csi_mul3 (*(volatile byte xdata *) 0xF651)
+#define    p_reg_p_csi_mul3 0xF651
+#define reg_p_csi_mul3_pos 0
+#define reg_p_csi_mul3_len 8
+#define reg_p_csi_mul3_lsb 0
+#define xd_p_reg_p_csi_level3_7_0   (*(volatile byte xdata *) 0xF652)
+#define    p_reg_p_csi_level3_7_0   0xF652
+#define reg_p_csi_level3_7_0_pos 0
+#define reg_p_csi_level3_7_0_len 8
+#define reg_p_csi_level3_7_0_lsb 0
+#define xd_p_reg_p_csi_level3_8 (*(volatile byte xdata *) 0xF653)
+#define    p_reg_p_csi_level3_8 0xF653
+#define reg_p_csi_level3_8_pos 0
+#define reg_p_csi_level3_8_len 1
+#define reg_p_csi_level3_8_lsb 8
+#define xd_p_reg_p_csi_fftout_shift_fix_value   (*(volatile byte xdata *) 0xF654)
+#define    p_reg_p_csi_fftout_shift_fix_value   0xF654
+#define reg_p_csi_fftout_shift_fix_value_pos 0
+#define reg_p_csi_fftout_shift_fix_value_len 4
+#define reg_p_csi_fftout_shift_fix_value_lsb 0
+#define xd_p_reg_p_feq_scale_pow    (*(volatile byte xdata *) 0xF655)
+#define    p_reg_p_feq_scale_pow    0xF655
+#define reg_p_feq_scale_pow_pos 0
+#define reg_p_feq_scale_pow_len 6
+#define reg_p_feq_scale_pow_lsb 0
+#define xd_p_reg_p_csi_cp_idx   (*(volatile byte xdata *) 0xF656)
+#define    p_reg_p_csi_cp_idx   0xF656
+#define reg_p_csi_cp_idx_pos 0
+#define reg_p_csi_cp_idx_len 8
+#define reg_p_csi_cp_idx_lsb 0
+#define xd_p_reg_p_csi_outsh_zero_th_7_0    (*(volatile byte xdata *) 0xF657)
+#define    p_reg_p_csi_outsh_zero_th_7_0    0xF657
+#define reg_p_csi_outsh_zero_th_7_0_pos 0
+#define reg_p_csi_outsh_zero_th_7_0_len 8
+#define reg_p_csi_outsh_zero_th_7_0_lsb 0
+#define xd_p_reg_p_csi_outsh_zero_th_10_8   (*(volatile byte xdata *) 0xF658)
+#define    p_reg_p_csi_outsh_zero_th_10_8   0xF658
+#define reg_p_csi_outsh_zero_th_10_8_pos 0
+#define reg_p_csi_outsh_zero_th_10_8_len 3
+#define reg_p_csi_outsh_zero_th_10_8_lsb 8
+#define xd_p_reg_p_csi_ar_ratio (*(volatile byte xdata *) 0xF659)
+#define    p_reg_p_csi_ar_ratio 0xF659
+#define reg_p_csi_ar_ratio_pos 0
+#define reg_p_csi_ar_ratio_len 8
+#define reg_p_csi_ar_ratio_lsb 0
+#define xd_p_reg_r_csi_cp_vld   (*(volatile byte xdata *) 0xF65A)
+#define    p_reg_r_csi_cp_vld   0xF65A
+#define reg_r_csi_cp_vld_pos 0
+#define reg_r_csi_cp_vld_len 1
+#define reg_r_csi_cp_vld_lsb 0
+#define xd_p_reg_r_csi_sp_vld   (*(volatile byte xdata *) 0xF65B)
+#define    p_reg_r_csi_sp_vld   0xF65B
+#define reg_r_csi_sp_vld_pos 0
+#define reg_r_csi_sp_vld_len 1
+#define reg_r_csi_sp_vld_lsb 0
+#define xd_p_reg_p_csi_fft_out_shift_en (*(volatile byte xdata *) 0xF65C)
+#define    p_reg_p_csi_fft_out_shift_en 0xF65C
+#define reg_p_csi_fft_out_shift_en_pos 0
+#define reg_p_csi_fft_out_shift_en_len 1
+#define reg_p_csi_fft_out_shift_en_lsb 0
+#define xd_p_reg_p_csi_feq_out_shift_en (*(volatile byte xdata *) 0xF65D)
+#define    p_reg_p_csi_feq_out_shift_en 0xF65D
+#define reg_p_csi_feq_out_shift_en_pos 0
+#define reg_p_csi_feq_out_shift_en_len 1
+#define reg_p_csi_feq_out_shift_en_lsb 0
+#define xd_p_reg_r_csi_cp_fft_out   (*(volatile byte xdata *) 0xF65E)
+#define    p_reg_r_csi_cp_fft_out   0xF65E
+#define reg_r_csi_cp_fft_out_pos 0
+#define reg_r_csi_cp_fft_out_len 1
+#define reg_r_csi_cp_fft_out_lsb 0
+#define xd_p_reg_r_csi_sp_feq_log2_out  (*(volatile byte xdata *) 0xF65F)
+#define    p_reg_r_csi_sp_feq_log2_out  0xF65F
+#define reg_r_csi_sp_feq_log2_out_pos 0
+#define reg_r_csi_sp_feq_log2_out_len 8
+#define reg_r_csi_sp_feq_log2_out_lsb 0
+#define xd_p_reg_r_csi_sp_fft_out   (*(volatile byte xdata *) 0xF660)
+#define    p_reg_r_csi_sp_fft_out   0xF660
+#define reg_r_csi_sp_fft_out_pos 0
+#define reg_r_csi_sp_fft_out_len 1
+#define reg_r_csi_sp_fft_out_lsb 0
+#define xd_p_reg_p_feq_eh2_from_fpcc_en (*(volatile byte xdata *) 0xF661)
+#define    p_reg_p_feq_eh2_from_fpcc_en 0xF661
+#define reg_p_feq_eh2_from_fpcc_en_pos 0
+#define reg_p_feq_eh2_from_fpcc_en_len 1
+#define reg_p_feq_eh2_from_fpcc_en_lsb 0
+#define xd_r_reg_r_fccid_fft_ave_peak_7_0   (*(volatile byte xdata *) 0xF662)
+#define    r_reg_r_fccid_fft_ave_peak_7_0   0xF662
+#define reg_r_fccid_fft_ave_peak_7_0_pos 0
+#define reg_r_fccid_fft_ave_peak_7_0_len 8
+#define reg_r_fccid_fft_ave_peak_7_0_lsb 0
+#define xd_r_reg_r_fccid_fft_ave_peak_15_8  (*(volatile byte xdata *) 0xF663)
+#define    r_reg_r_fccid_fft_ave_peak_15_8  0xF663
+#define reg_r_fccid_fft_ave_peak_15_8_pos 0
+#define reg_r_fccid_fft_ave_peak_15_8_len 8
+#define reg_r_fccid_fft_ave_peak_15_8_lsb 8
+#define xd_r_reg_r_fccid_fft_ave_peak_23_16 (*(volatile byte xdata *) 0xF664)
+#define    r_reg_r_fccid_fft_ave_peak_23_16 0xF664
+#define reg_r_fccid_fft_ave_peak_23_16_pos 0
+#define reg_r_fccid_fft_ave_peak_23_16_len 8
+#define reg_r_fccid_fft_ave_peak_23_16_lsb 16
+#define xd_r_reg_r_fccid_fft_ave_peak_26_24 (*(volatile byte xdata *) 0xF665)
+#define    r_reg_r_fccid_fft_ave_peak_26_24 0xF665
+#define reg_r_fccid_fft_ave_peak_26_24_pos 0
+#define reg_r_fccid_fft_ave_peak_26_24_len 3
+#define reg_r_fccid_fft_ave_peak_26_24_lsb 24
+#define xd_p_reg_p_fccid_fft_ave_read_rdy   (*(volatile byte xdata *) 0xF666)
+#define    p_reg_p_fccid_fft_ave_read_rdy   0xF666
+#define reg_p_fccid_fft_ave_read_rdy_pos 0
+#define reg_p_fccid_fft_ave_read_rdy_len 1
+#define reg_p_fccid_fft_ave_read_rdy_lsb 0
+#define xd_p_reg_p_fccid_fft_ave_read_index_7_0 (*(volatile byte xdata *) 0xF667)
+#define    p_reg_p_fccid_fft_ave_read_index_7_0 0xF667
+#define reg_p_fccid_fft_ave_read_index_7_0_pos 0
+#define reg_p_fccid_fft_ave_read_index_7_0_len 8
+#define reg_p_fccid_fft_ave_read_index_7_0_lsb 0
+#define xd_p_reg_p_fccid_fft_ave_read_index_12_8    (*(volatile byte xdata *) 0xF668)
+#define    p_reg_p_fccid_fft_ave_read_index_12_8    0xF668
+#define reg_p_fccid_fft_ave_read_index_12_8_pos 0
+#define reg_p_fccid_fft_ave_read_index_12_8_len 5
+#define reg_p_fccid_fft_ave_read_index_12_8_lsb 8
+#define xd_p_reg_cdpf_candidate_rw  (*(volatile byte xdata *) 0xF669)
+#define    p_reg_cdpf_candidate_rw  0xF669
+#define reg_cdpf_candidate_rw_pos 0
+#define reg_cdpf_candidate_rw_len 1
+#define reg_cdpf_candidate_rw_lsb 0
+#define xd_p_reg_cdpf_candidate_prog_7_0    (*(volatile byte xdata *) 0xF66A)
+#define    p_reg_cdpf_candidate_prog_7_0    0xF66A
+#define reg_cdpf_candidate_prog_7_0_pos 0
+#define reg_cdpf_candidate_prog_7_0_len 8
+#define reg_cdpf_candidate_prog_7_0_lsb 0
+#define xd_p_reg_cdpf_candidate_prog_15_8   (*(volatile byte xdata *) 0xF66B)
+#define    p_reg_cdpf_candidate_prog_15_8   0xF66B
+#define reg_cdpf_candidate_prog_15_8_pos 0
+#define reg_cdpf_candidate_prog_15_8_len 8
+#define reg_cdpf_candidate_prog_15_8_lsb 8
+#define xd_p_reg_cdpf_candidateno_prog  (*(volatile byte xdata *) 0xF66C)
+#define    p_reg_cdpf_candidateno_prog  0xF66C
+#define reg_cdpf_candidateno_prog_pos 0
+#define reg_cdpf_candidateno_prog_len 6
+#define reg_cdpf_candidateno_prog_lsb 0
+#define xd_p_reg_cdpf_candidateno_switch    (*(volatile byte xdata *) 0xF66D)
+#define    p_reg_cdpf_candidateno_switch    0xF66D
+#define reg_cdpf_candidateno_switch_pos 0
+#define reg_cdpf_candidateno_switch_len 1
+#define reg_cdpf_candidateno_switch_lsb 0
+#define xd_g_reg_tpsd_txmod (*(volatile byte xdata *) 0xF900)
+#define    g_reg_tpsd_txmod 0xF900
+#define reg_tpsd_txmod_pos 0
+#define reg_tpsd_txmod_len 2
+#define reg_tpsd_txmod_lsb 0
+#define xd_g_reg_tpsd_gi    (*(volatile byte xdata *) 0xF901)
+#define    g_reg_tpsd_gi    0xF901
+#define reg_tpsd_gi_pos 0
+#define reg_tpsd_gi_len 2
+#define reg_tpsd_gi_lsb 0
+#define xd_g_reg_tpsd_hier  (*(volatile byte xdata *) 0xF902)
+#define    g_reg_tpsd_hier  0xF902
+#define reg_tpsd_hier_pos 0
+#define reg_tpsd_hier_len 3
+#define reg_tpsd_hier_lsb 0
+#define xd_g_reg_tpsd_const (*(volatile byte xdata *) 0xF903)
+#define    g_reg_tpsd_const 0xF903
+#define reg_tpsd_const_pos 0
+#define reg_tpsd_const_len 2
+#define reg_tpsd_const_lsb 0
+#define xd_g_reg_bw (*(volatile byte xdata *) 0xF904)
+#define    g_reg_bw 0xF904
+#define reg_bw_pos 0
+#define reg_bw_len 2
+#define reg_bw_lsb 0
+#define xd_g_reg_dec_pri    (*(volatile byte xdata *) 0xF905)
+#define    g_reg_dec_pri    0xF905
+#define reg_dec_pri_pos 0
+#define reg_dec_pri_len 1
+#define reg_dec_pri_lsb 0
+#define xd_g_reg_tpsd_hpcr  (*(volatile byte xdata *) 0xF906)
+#define    g_reg_tpsd_hpcr  0xF906
+#define reg_tpsd_hpcr_pos 0
+#define reg_tpsd_hpcr_len 3
+#define reg_tpsd_hpcr_lsb 0
+#define xd_g_reg_tpsd_lpcr  (*(volatile byte xdata *) 0xF907)
+#define    g_reg_tpsd_lpcr  0xF907
+#define reg_tpsd_lpcr_pos 0
+#define reg_tpsd_lpcr_len 3
+#define reg_tpsd_lpcr_lsb 0
+#define xd_g_reg_tpsd_indep (*(volatile byte xdata *) 0xF908)
+#define    g_reg_tpsd_indep 0xF908
+#define reg_tpsd_indep_pos 0
+#define reg_tpsd_indep_len 1
+#define reg_tpsd_indep_lsb 0
+#define xd_g_reg_tpsd_tslice    (*(volatile byte xdata *) 0xF909)
+#define    g_reg_tpsd_tslice    0xF909
+#define reg_tpsd_tslice_pos 0
+#define reg_tpsd_tslice_len 1
+#define reg_tpsd_tslice_lsb 0
+#define xd_g_reg_tpsd_mpefec    (*(volatile byte xdata *) 0xF90A)
+#define    g_reg_tpsd_mpefec    0xF90A
+#define reg_tpsd_mpefec_pos 0
+#define reg_tpsd_mpefec_len 1
+#define reg_tpsd_mpefec_lsb 0
+#define xd_g_reg_sntc_en    (*(volatile byte xdata *) 0xF90B)
+#define    g_reg_sntc_en    0xF90B
+#define reg_sntc_en_pos 0
+#define reg_sntc_en_len 1
+#define reg_sntc_en_lsb 0
+#define xd_g_reg_intp_sys_div   (*(volatile byte xdata *) 0xF90C)
+#define    g_reg_intp_sys_div   0xF90C
+#define reg_intp_sys_div_pos 0
+#define reg_intp_sys_div_len 1
+#define reg_intp_sys_div_lsb 0
+#define xd_g_reg_clk_sntc_sel   (*(volatile byte xdata *) 0xF90D)
+#define    g_reg_clk_sntc_sel   0xF90D
+#define reg_clk_sntc_sel_pos 0
+#define reg_clk_sntc_sel_len 3
+#define reg_clk_sntc_sel_lsb 0
+#define xd_p_reg_ce_gs_force    (*(volatile byte xdata *) 0xFD00)
+#define    p_reg_ce_gs_force    0xFD00
+#define reg_ce_gs_force_pos 0
+#define reg_ce_gs_force_len 1
+#define reg_ce_gs_force_lsb 0
+#define xd_p_reg_ce_dagcgain_delay  (*(volatile byte xdata *) 0xFD01)
+#define    p_reg_ce_dagcgain_delay  0xFD01
+#define reg_ce_dagcgain_delay_pos 0
+#define reg_ce_dagcgain_delay_len 2
+#define reg_ce_dagcgain_delay_lsb 0
+#define xd_p_reg_ce_derot_en    (*(volatile byte xdata *) 0xFD02)
+#define    p_reg_ce_derot_en    0xFD02
+#define reg_ce_derot_en_pos 0
+#define reg_ce_derot_en_len 1
+#define reg_ce_derot_en_lsb 0
+#define xd_p_reg_ce_fctrl_en    (*(volatile byte xdata *) 0xFD05)
+#define    p_reg_ce_fctrl_en    0xFD05
+#define reg_ce_fctrl_en_pos 0
+#define reg_ce_fctrl_en_len 1
+#define reg_ce_fctrl_en_lsb 0
+#define xd_p_reg_ce_en  (*(volatile byte xdata *) 0xFD06)
+#define    p_reg_ce_en  0xFD06
+#define reg_ce_en_pos 0
+#define reg_ce_en_len 1
+#define reg_ce_en_lsb 0
+#define xd_p_reg_ce_sat_wes (*(volatile byte xdata *) 0xFD07)
+#define    p_reg_ce_sat_wes 0xFD07
+#define reg_ce_sat_wes_pos 0
+#define reg_ce_sat_wes_len 1
+#define reg_ce_sat_wes_lsb 0
+#define xd_p_reg_ce_sat_sigma2  (*(volatile byte xdata *) 0xFD08)
+#define    p_reg_ce_sat_sigma2  0xFD08
+#define reg_ce_sat_sigma2_pos 0
+#define reg_ce_sat_sigma2_len 1
+#define reg_ce_sat_sigma2_lsb 0
+#define xd_p_reg_ce_sat_tdi_br_re   (*(volatile byte xdata *) 0xFD09)
+#define    p_reg_ce_sat_tdi_br_re   0xFD09
+#define reg_ce_sat_tdi_br_re_pos 0
+#define reg_ce_sat_tdi_br_re_len 1
+#define reg_ce_sat_tdi_br_re_lsb 0
+#define xd_p_reg_ce_sat_tdi_br_im   (*(volatile byte xdata *) 0xFD0A)
+#define    p_reg_ce_sat_tdi_br_im   0xFD0A
+#define reg_ce_sat_tdi_br_im_pos 0
+#define reg_ce_sat_tdi_br_im_len 1
+#define reg_ce_sat_tdi_br_im_lsb 0
+#define xd_p_reg_ce_sat_tdi_ar_re   (*(volatile byte xdata *) 0xFD0B)
+#define    p_reg_ce_sat_tdi_ar_re   0xFD0B
+#define reg_ce_sat_tdi_ar_re_pos 0
+#define reg_ce_sat_tdi_ar_re_len 1
+#define reg_ce_sat_tdi_ar_re_lsb 0
+#define xd_p_reg_ce_sat_tdi_ar_im   (*(volatile byte xdata *) 0xFD0C)
+#define    p_reg_ce_sat_tdi_ar_im   0xFD0C
+#define reg_ce_sat_tdi_ar_im_pos 0
+#define reg_ce_sat_tdi_ar_im_len 1
+#define reg_ce_sat_tdi_ar_im_lsb 0
+#define xd_p_reg_ce_sat_fdi_br_re   (*(volatile byte xdata *) 0xFD0D)
+#define    p_reg_ce_sat_fdi_br_re   0xFD0D
+#define reg_ce_sat_fdi_br_re_pos 0
+#define reg_ce_sat_fdi_br_re_len 1
+#define reg_ce_sat_fdi_br_re_lsb 0
+#define xd_p_reg_ce_sat_fdi_br_im   (*(volatile byte xdata *) 0xFD0E)
+#define    p_reg_ce_sat_fdi_br_im   0xFD0E
+#define reg_ce_sat_fdi_br_im_pos 0
+#define reg_ce_sat_fdi_br_im_len 1
+#define reg_ce_sat_fdi_br_im_lsb 0
+#define xd_p_reg_ce_var_forced_value    (*(volatile byte xdata *) 0xFD0F)
+#define    p_reg_ce_var_forced_value    0xFD0F
+#define reg_ce_var_forced_value_pos 0
+#define reg_ce_var_forced_value_len 3
+#define reg_ce_var_forced_value_lsb 0
+#define xd_p_reg_ce_s1  (*(volatile byte xdata *) 0xFD10)
+#define    p_reg_ce_s1  0xFD10
+#define reg_ce_s1_pos 0
+#define reg_ce_s1_len 5
+#define reg_ce_s1_lsb 0
+#define xd_r_reg_ce_tdi_flatness_7_0    (*(volatile byte xdata *) 0xFD11)
+#define    r_reg_ce_tdi_flatness_7_0    0xFD11
+#define reg_ce_tdi_flatness_7_0_pos 0
+#define reg_ce_tdi_flatness_7_0_len 8
+#define reg_ce_tdi_flatness_7_0_lsb 0
+#define xd_r_reg_ce_tdi_flatness_8  (*(volatile byte xdata *) 0xFD12)
+#define    r_reg_ce_tdi_flatness_8  0xFD12
+#define reg_ce_tdi_flatness_8_pos 0
+#define reg_ce_tdi_flatness_8_len 1
+#define reg_ce_tdi_flatness_8_lsb 8
+#define xd_r_reg_ce_tone_7_0    (*(volatile byte xdata *) 0xFD13)
+#define    r_reg_ce_tone_7_0    0xFD13
+#define reg_ce_tone_7_0_pos 0
+#define reg_ce_tone_7_0_len 8
+#define reg_ce_tone_7_0_lsb 0
+#define xd_r_reg_ce_tone_12_8   (*(volatile byte xdata *) 0xFD14)
+#define    r_reg_ce_tone_12_8   0xFD14
+#define reg_ce_tone_12_8_pos 0
+#define reg_ce_tone_12_8_len 5
+#define reg_ce_tone_12_8_lsb 8
+#define xd_p_reg_ce_centroid_drift_th   (*(volatile byte xdata *) 0xFD15)
+#define    p_reg_ce_centroid_drift_th   0xFD15
+#define reg_ce_centroid_drift_th_pos 0
+#define reg_ce_centroid_drift_th_len 8
+#define reg_ce_centroid_drift_th_lsb 0
+#define xd_p_reg_ce_centroid_bias_inc_7_0   (*(volatile byte xdata *) 0xFD16)
+#define    p_reg_ce_centroid_bias_inc_7_0   0xFD16
+#define reg_ce_centroid_bias_inc_7_0_pos 0
+#define reg_ce_centroid_bias_inc_7_0_len 8
+#define reg_ce_centroid_bias_inc_7_0_lsb 0
+#define xd_p_reg_ce_centroid_bias_inc_8 (*(volatile byte xdata *) 0xFD17)
+#define    p_reg_ce_centroid_bias_inc_8 0xFD17
+#define reg_ce_centroid_bias_inc_8_pos 0
+#define reg_ce_centroid_bias_inc_8_len 1
+#define reg_ce_centroid_bias_inc_8_lsb 8
+#define xd_p_reg_ce_centroid_count_max  (*(volatile byte xdata *) 0xFD18)
+#define    p_reg_ce_centroid_count_max  0xFD18
+#define reg_ce_centroid_count_max_pos 0
+#define reg_ce_centroid_count_max_len 4
+#define reg_ce_centroid_count_max_lsb 0
+#define xd_p_reg_ce_var_th0_7_0 (*(volatile byte xdata *) 0xFD19)
+#define    p_reg_ce_var_th0_7_0 0xFD19
+#define reg_ce_var_th0_7_0_pos 0
+#define reg_ce_var_th0_7_0_len 8
+#define reg_ce_var_th0_7_0_lsb 0
+#define xd_p_reg_ce_var_th0_15_8    (*(volatile byte xdata *) 0xFD1A)
+#define    p_reg_ce_var_th0_15_8    0xFD1A
+#define reg_ce_var_th0_15_8_pos 0
+#define reg_ce_var_th0_15_8_len 8
+#define reg_ce_var_th0_15_8_lsb 8
+#define xd_p_reg_ce_var_th1_7_0 (*(volatile byte xdata *) 0xFD1B)
+#define    p_reg_ce_var_th1_7_0 0xFD1B
+#define reg_ce_var_th1_7_0_pos 0
+#define reg_ce_var_th1_7_0_len 8
+#define reg_ce_var_th1_7_0_lsb 0
+#define xd_p_reg_ce_var_th1_15_8    (*(volatile byte xdata *) 0xFD1C)
+#define    p_reg_ce_var_th1_15_8    0xFD1C
+#define reg_ce_var_th1_15_8_pos 0
+#define reg_ce_var_th1_15_8_len 8
+#define reg_ce_var_th1_15_8_lsb 8
+#define xd_p_reg_ce_var_th2_7_0 (*(volatile byte xdata *) 0xFD1D)
+#define    p_reg_ce_var_th2_7_0 0xFD1D
+#define reg_ce_var_th2_7_0_pos 0
+#define reg_ce_var_th2_7_0_len 8
+#define reg_ce_var_th2_7_0_lsb 0
+#define xd_p_reg_ce_var_th2_15_8    (*(volatile byte xdata *) 0xFD1E)
+#define    p_reg_ce_var_th2_15_8    0xFD1E
+#define reg_ce_var_th2_15_8_pos 0
+#define reg_ce_var_th2_15_8_len 8
+#define reg_ce_var_th2_15_8_lsb 8
+#define xd_p_reg_ce_var_th3_7_0 (*(volatile byte xdata *) 0xFD1F)
+#define    p_reg_ce_var_th3_7_0 0xFD1F
+#define reg_ce_var_th3_7_0_pos 0
+#define reg_ce_var_th3_7_0_len 8
+#define reg_ce_var_th3_7_0_lsb 0
+#define xd_p_reg_ce_var_th3_15_8    (*(volatile byte xdata *) 0xFD20)
+#define    p_reg_ce_var_th3_15_8    0xFD20
+#define reg_ce_var_th3_15_8_pos 0
+#define reg_ce_var_th3_15_8_len 8
+#define reg_ce_var_th3_15_8_lsb 8
+#define xd_p_reg_ce_var_th4_7_0 (*(volatile byte xdata *) 0xFD21)
+#define    p_reg_ce_var_th4_7_0 0xFD21
+#define reg_ce_var_th4_7_0_pos 0
+#define reg_ce_var_th4_7_0_len 8
+#define reg_ce_var_th4_7_0_lsb 0
+#define xd_p_reg_ce_var_th4_15_8    (*(volatile byte xdata *) 0xFD22)
+#define    p_reg_ce_var_th4_15_8    0xFD22
+#define reg_ce_var_th4_15_8_pos 0
+#define reg_ce_var_th4_15_8_len 8
+#define reg_ce_var_th4_15_8_lsb 8
+#define xd_p_reg_ce_var_th5_7_0 (*(volatile byte xdata *) 0xFD23)
+#define    p_reg_ce_var_th5_7_0 0xFD23
+#define reg_ce_var_th5_7_0_pos 0
+#define reg_ce_var_th5_7_0_len 8
+#define reg_ce_var_th5_7_0_lsb 0
+#define xd_p_reg_ce_var_th5_15_8    (*(volatile byte xdata *) 0xFD24)
+#define    p_reg_ce_var_th5_15_8    0xFD24
+#define reg_ce_var_th5_15_8_pos 0
+#define reg_ce_var_th5_15_8_len 8
+#define reg_ce_var_th5_15_8_lsb 8
+#define xd_p_reg_ce_var_th6_7_0 (*(volatile byte xdata *) 0xFD25)
+#define    p_reg_ce_var_th6_7_0 0xFD25
+#define reg_ce_var_th6_7_0_pos 0
+#define reg_ce_var_th6_7_0_len 8
+#define reg_ce_var_th6_7_0_lsb 0
+#define xd_p_reg_ce_var_th6_15_8    (*(volatile byte xdata *) 0xFD26)
+#define    p_reg_ce_var_th6_15_8    0xFD26
+#define reg_ce_var_th6_15_8_pos 0
+#define reg_ce_var_th6_15_8_len 8
+#define reg_ce_var_th6_15_8_lsb 8
+#define xd_p_reg_ce_var_max (*(volatile byte xdata *) 0xFD27)
+#define    p_reg_ce_var_max 0xFD27
+#define reg_ce_var_max_pos 0
+#define reg_ce_var_max_len 3
+#define reg_ce_var_max_lsb 0
+#define xd_p_reg_ce_cent_forced_en  (*(volatile byte xdata *) 0xFD28)
+#define    p_reg_ce_cent_forced_en  0xFD28
+#define reg_ce_cent_forced_en_pos 0
+#define reg_ce_cent_forced_en_len 1
+#define reg_ce_cent_forced_en_lsb 0
+#define xd_p_reg_ce_var_forced_en   (*(volatile byte xdata *) 0xFD29)
+#define    p_reg_ce_var_forced_en   0xFD29
+#define reg_ce_var_forced_en_pos 0
+#define reg_ce_var_forced_en_len 1
+#define reg_ce_var_forced_en_lsb 0
+#define xd_p_reg_ce_fctrl_auto_reset_en (*(volatile byte xdata *) 0xFD2A)
+#define    p_reg_ce_fctrl_auto_reset_en 0xFD2A
+#define reg_ce_fctrl_auto_reset_en_pos 0
+#define reg_ce_fctrl_auto_reset_en_len 1
+#define reg_ce_fctrl_auto_reset_en_lsb 0
+#define xd_p_reg_ce_cent_auto_clr_en    (*(volatile byte xdata *) 0xFD2B)
+#define    p_reg_ce_cent_auto_clr_en    0xFD2B
+#define reg_ce_cent_auto_clr_en_pos 0
+#define reg_ce_cent_auto_clr_en_len 1
+#define reg_ce_cent_auto_clr_en_lsb 0
+#define xd_p_reg_ce_fctrl_reset (*(volatile byte xdata *) 0xFD2C)
+#define    p_reg_ce_fctrl_reset 0xFD2C
+#define reg_ce_fctrl_reset_pos 0
+#define reg_ce_fctrl_reset_len 1
+#define reg_ce_fctrl_reset_lsb 0
+#define xd_p_reg_ce_cent_forced_value_7_0   (*(volatile byte xdata *) 0xFD2D)
+#define    p_reg_ce_cent_forced_value_7_0   0xFD2D
+#define reg_ce_cent_forced_value_7_0_pos 0
+#define reg_ce_cent_forced_value_7_0_len 8
+#define reg_ce_cent_forced_value_7_0_lsb 0
+#define xd_p_reg_ce_cent_forced_value_11_8  (*(volatile byte xdata *) 0xFD2E)
+#define    p_reg_ce_cent_forced_value_11_8  0xFD2E
+#define reg_ce_cent_forced_value_11_8_pos 0
+#define reg_ce_cent_forced_value_11_8_len 4
+#define reg_ce_cent_forced_value_11_8_lsb 8
+#define xd_p_reg_ce_cent_auto_clr_value_7_0 (*(volatile byte xdata *) 0xFD2F)
+#define    p_reg_ce_cent_auto_clr_value_7_0 0xFD2F
+#define reg_ce_cent_auto_clr_value_7_0_pos 0
+#define reg_ce_cent_auto_clr_value_7_0_len 8
+#define reg_ce_cent_auto_clr_value_7_0_lsb 0
+#define xd_p_reg_ce_cent_auto_clr_value_11_8    (*(volatile byte xdata *) 0xFD30)
+#define    p_reg_ce_cent_auto_clr_value_11_8    0xFD30
+#define reg_ce_cent_auto_clr_value_11_8_pos 0
+#define reg_ce_cent_auto_clr_value_11_8_len 4
+#define reg_ce_cent_auto_clr_value_11_8_lsb 8
+#define xd_p_reg_ce_centroid_max_7_0    (*(volatile byte xdata *) 0xFD31)
+#define    p_reg_ce_centroid_max_7_0    0xFD31
+#define reg_ce_centroid_max_7_0_pos 0
+#define reg_ce_centroid_max_7_0_len 8
+#define reg_ce_centroid_max_7_0_lsb 0
+#define xd_p_reg_ce_centroid_max_11_8   (*(volatile byte xdata *) 0xFD32)
+#define    p_reg_ce_centroid_max_11_8   0xFD32
+#define reg_ce_centroid_max_11_8_pos 0
+#define reg_ce_centroid_max_11_8_len 4
+#define reg_ce_centroid_max_11_8_lsb 8
+#define xd_p_reg_ce_fctrl_rd    (*(volatile byte xdata *) 0xFD33)
+#define    p_reg_ce_fctrl_rd    0xFD33
+#define reg_ce_fctrl_rd_pos 0
+#define reg_ce_fctrl_rd_len 1
+#define reg_ce_fctrl_rd_lsb 0
+#define xd_r_reg_ce_centroid_out_7_0    (*(volatile byte xdata *) 0xFD34)
+#define    r_reg_ce_centroid_out_7_0    0xFD34
+#define reg_ce_centroid_out_7_0_pos 0
+#define reg_ce_centroid_out_7_0_len 8
+#define reg_ce_centroid_out_7_0_lsb 0
+#define xd_r_reg_ce_centroid_out_11_8   (*(volatile byte xdata *) 0xFD35)
+#define    r_reg_ce_centroid_out_11_8   0xFD35
+#define reg_ce_centroid_out_11_8_pos 0
+#define reg_ce_centroid_out_11_8_len 4
+#define reg_ce_centroid_out_11_8_lsb 8
+#define xd_r_reg_ce_fctrl_rdy   (*(volatile byte xdata *) 0xFD36)
+#define    r_reg_ce_fctrl_rdy   0xFD36
+#define reg_ce_fctrl_rdy_pos 0
+#define reg_ce_fctrl_rdy_len 1
+#define reg_ce_fctrl_rdy_lsb 0
+#define xd_r_reg_ce_var (*(volatile byte xdata *) 0xFD37)
+#define    r_reg_ce_var 0xFD37
+#define reg_ce_var_pos 0
+#define reg_ce_var_len 3
+#define reg_ce_var_lsb 0
+#define xd_r_reg_ce_bias_7_0    (*(volatile byte xdata *) 0xFD38)
+#define    r_reg_ce_bias_7_0    0xFD38
+#define reg_ce_bias_7_0_pos 0
+#define reg_ce_bias_7_0_len 8
+#define reg_ce_bias_7_0_lsb 0
+#define xd_r_reg_ce_bias_11_8   (*(volatile byte xdata *) 0xFD39)
+#define    r_reg_ce_bias_11_8   0xFD39
+#define reg_ce_bias_11_8_pos 0
+#define reg_ce_bias_11_8_len 4
+#define reg_ce_bias_11_8_lsb 8
+#define xd_r_reg_ce_m1_7_0  (*(volatile byte xdata *) 0xFD3A)
+#define    r_reg_ce_m1_7_0  0xFD3A
+#define reg_ce_m1_7_0_pos 0
+#define reg_ce_m1_7_0_len 8
+#define reg_ce_m1_7_0_lsb 0
+#define xd_r_reg_ce_m1_11_8 (*(volatile byte xdata *) 0xFD3B)
+#define    r_reg_ce_m1_11_8 0xFD3B
+#define reg_ce_m1_11_8_pos 0
+#define reg_ce_m1_11_8_len 4
+#define reg_ce_m1_11_8_lsb 8
+#define xd_r_reg_ce_rh0_7_0 (*(volatile byte xdata *) 0xFD3C)
+#define    r_reg_ce_rh0_7_0 0xFD3C
+#define reg_ce_rh0_7_0_pos 0
+#define reg_ce_rh0_7_0_len 8
+#define reg_ce_rh0_7_0_lsb 0
+#define xd_r_reg_ce_rh0_15_8    (*(volatile byte xdata *) 0xFD3D)
+#define    r_reg_ce_rh0_15_8    0xFD3D
+#define reg_ce_rh0_15_8_pos 0
+#define reg_ce_rh0_15_8_len 8
+#define reg_ce_rh0_15_8_lsb 8
+#define xd_r_reg_ce_rh0_23_16   (*(volatile byte xdata *) 0xFD3E)
+#define    r_reg_ce_rh0_23_16   0xFD3E
+#define reg_ce_rh0_23_16_pos 0
+#define reg_ce_rh0_23_16_len 8
+#define reg_ce_rh0_23_16_lsb 16
+#define xd_r_reg_ce_rh0_31_24   (*(volatile byte xdata *) 0xFD3F)
+#define    r_reg_ce_rh0_31_24   0xFD3F
+#define reg_ce_rh0_31_24_pos 0
+#define reg_ce_rh0_31_24_len 8
+#define reg_ce_rh0_31_24_lsb 24
+#define xd_p_reg_ce_tdi_delta   (*(volatile byte xdata *) 0xFD40)
+#define    p_reg_ce_tdi_delta   0xFD40
+#define reg_ce_tdi_delta_pos 0
+#define reg_ce_tdi_delta_len 3
+#define reg_ce_tdi_delta_lsb 0
+#define xd_p_reg_ce_fdi_delta   (*(volatile byte xdata *) 0xFD41)
+#define    p_reg_ce_fdi_delta   0xFD41
+#define reg_ce_fdi_delta_pos 0
+#define reg_ce_fdi_delta_len 3
+#define reg_ce_fdi_delta_lsb 0
+#define xd_p_reg_ce_fste_delta  (*(volatile byte xdata *) 0xFD42)
+#define    p_reg_ce_fste_delta  0xFD42
+#define reg_ce_fste_delta_pos 0
+#define reg_ce_fste_delta_len 3
+#define reg_ce_fste_delta_lsb 0
+#define xd_r_reg_ce_fft_s1  (*(volatile byte xdata *) 0xFD43)
+#define    r_reg_ce_fft_s1  0xFD43
+#define reg_ce_fft_s1_pos 0
+#define reg_ce_fft_s1_len 4
+#define reg_ce_fft_s1_lsb 0
+#define xd_r_reg_feq_fix_eh2_7_0    (*(volatile byte xdata *) 0xFD44)
+#define    r_reg_feq_fix_eh2_7_0    0xFD44
+#define reg_feq_fix_eh2_7_0_pos 0
+#define reg_feq_fix_eh2_7_0_len 8
+#define reg_feq_fix_eh2_7_0_lsb 0
+#define xd_r_reg_feq_fix_eh2_15_8   (*(volatile byte xdata *) 0xFD45)
+#define    r_reg_feq_fix_eh2_15_8   0xFD45
+#define reg_feq_fix_eh2_15_8_pos 0
+#define reg_feq_fix_eh2_15_8_len 8
+#define reg_feq_fix_eh2_15_8_lsb 8
+#define xd_r_reg_feq_fix_eh2_23_16  (*(volatile byte xdata *) 0xFD46)
+#define    r_reg_feq_fix_eh2_23_16  0xFD46
+#define reg_feq_fix_eh2_23_16_pos 0
+#define reg_feq_fix_eh2_23_16_len 8
+#define reg_feq_fix_eh2_23_16_lsb 16
+#define xd_r_reg_feq_fix_eh2_31_24  (*(volatile byte xdata *) 0xFD47)
+#define    r_reg_feq_fix_eh2_31_24  0xFD47
+#define reg_feq_fix_eh2_31_24_pos 0
+#define reg_feq_fix_eh2_31_24_len 8
+#define reg_feq_fix_eh2_31_24_lsb 24
+#define xd_r_reg_ce_m2_central_7_0  (*(volatile byte xdata *) 0xFD48)
+#define    r_reg_ce_m2_central_7_0  0xFD48
+#define reg_ce_m2_central_7_0_pos 0
+#define reg_ce_m2_central_7_0_len 8
+#define reg_ce_m2_central_7_0_lsb 0
+#define xd_r_reg_ce_m2_central_15_8 (*(volatile byte xdata *) 0xFD49)
+#define    r_reg_ce_m2_central_15_8 0xFD49
+#define reg_ce_m2_central_15_8_pos 0
+#define reg_ce_m2_central_15_8_len 8
+#define reg_ce_m2_central_15_8_lsb 8
+#define xd_r_reg_ce_sigma2_7_0  (*(volatile byte xdata *) 0xFD4A)
+#define    r_reg_ce_sigma2_7_0  0xFD4A
+#define reg_ce_sigma2_7_0_pos 0
+#define reg_ce_sigma2_7_0_len 8
+#define reg_ce_sigma2_7_0_lsb 0
+#define xd_r_reg_ce_sigma2_15_8 (*(volatile byte xdata *) 0xFD4B)
+#define    r_reg_ce_sigma2_15_8 0xFD4B
+#define reg_ce_sigma2_15_8_pos 0
+#define reg_ce_sigma2_15_8_len 8
+#define reg_ce_sigma2_15_8_lsb 8
+#define xd_r_reg_ce_sigma2_19_16    (*(volatile byte xdata *) 0xFD4C)
+#define    r_reg_ce_sigma2_19_16    0xFD4C
+#define reg_ce_sigma2_19_16_pos 0
+#define reg_ce_sigma2_19_16_len 4
+#define reg_ce_sigma2_19_16_lsb 16
+#define xd_r_reg_ce_data_im_7_0 (*(volatile byte xdata *) 0xFD4D)
+#define    r_reg_ce_data_im_7_0 0xFD4D
+#define reg_ce_data_im_7_0_pos 0
+#define reg_ce_data_im_7_0_len 8
+#define reg_ce_data_im_7_0_lsb 0
+#define xd_r_reg_ce_data_im_14_8    (*(volatile byte xdata *) 0xFD4E)
+#define    r_reg_ce_data_im_14_8    0xFD4E
+#define reg_ce_data_im_14_8_pos 0
+#define reg_ce_data_im_14_8_len 7
+#define reg_ce_data_im_14_8_lsb 8
+#define xd_r_reg_ce_data_re_7_0 (*(volatile byte xdata *) 0xFD4F)
+#define    r_reg_ce_data_re_7_0 0xFD4F
+#define reg_ce_data_re_7_0_pos 0
+#define reg_ce_data_re_7_0_len 8
+#define reg_ce_data_re_7_0_lsb 0
+#define xd_r_reg_ce_data_re_14_8    (*(volatile byte xdata *) 0xFD50)
+#define    r_reg_ce_data_re_14_8    0xFD50
+#define reg_ce_data_re_14_8_pos 0
+#define reg_ce_data_re_14_8_len 7
+#define reg_ce_data_re_14_8_lsb 8
+#define xd_p_reg_ce_var_default_value   (*(volatile byte xdata *) 0xFD51)
+#define    p_reg_ce_var_default_value   0xFD51
+#define reg_ce_var_default_value_pos 0
+#define reg_ce_var_default_value_len 3
+#define reg_ce_var_default_value_lsb 0
+#define xd_p_reg_ce_cent_default_value_7_0  (*(volatile byte xdata *) 0xFD52)
+#define    p_reg_ce_cent_default_value_7_0  0xFD52
+#define reg_ce_cent_default_value_7_0_pos 0
+#define reg_ce_cent_default_value_7_0_len 8
+#define reg_ce_cent_default_value_7_0_lsb 0
+#define xd_p_reg_ce_cent_default_value_11_8 (*(volatile byte xdata *) 0xFD53)
+#define    p_reg_ce_cent_default_value_11_8 0xFD53
+#define reg_ce_cent_default_value_11_8_pos 0
+#define reg_ce_cent_default_value_11_8_len 4
+#define reg_ce_cent_default_value_11_8_lsb 8
+#define xd_r_reg_ce_var_hw  (*(volatile byte xdata *) 0xFD54)
+#define    r_reg_ce_var_hw  0xFD54
+#define reg_ce_var_hw_pos 0
+#define reg_ce_var_hw_len 3
+#define reg_ce_var_hw_lsb 0
+#define xd_r_reg_ce_cent_hw_7_0 (*(volatile byte xdata *) 0xFD55)
+#define    r_reg_ce_cent_hw_7_0 0xFD55
+#define reg_ce_cent_hw_7_0_pos 0
+#define reg_ce_cent_hw_7_0_len 8
+#define reg_ce_cent_hw_7_0_lsb 0
+#define xd_r_reg_ce_cent_hw_11_8    (*(volatile byte xdata *) 0xFD56)
+#define    r_reg_ce_cent_hw_11_8    0xFD56
+#define reg_ce_cent_hw_11_8_pos 0
+#define reg_ce_cent_hw_11_8_len 4
+#define reg_ce_cent_hw_11_8_lsb 8
+#define xd_p_reg_ce_fdi_cp_test_en  (*(volatile byte xdata *) 0xFD57)
+#define    p_reg_ce_fdi_cp_test_en  0xFD57
+#define reg_ce_fdi_cp_test_en_pos 0
+#define reg_ce_fdi_cp_test_en_len 1
+#define reg_ce_fdi_cp_test_en_lsb 0
+#define xd_p_reg_ce_cptestindex0_7_0    (*(volatile byte xdata *) 0xFD58)
+#define    p_reg_ce_cptestindex0_7_0    0xFD58
+#define reg_ce_cptestindex0_7_0_pos 0
+#define reg_ce_cptestindex0_7_0_len 8
+#define reg_ce_cptestindex0_7_0_lsb 0
+#define xd_p_reg_ce_cptestindex0_12_8   (*(volatile byte xdata *) 0xFD59)
+#define    p_reg_ce_cptestindex0_12_8   0xFD59
+#define reg_ce_cptestindex0_12_8_pos 0
+#define reg_ce_cptestindex0_12_8_len 5
+#define reg_ce_cptestindex0_12_8_lsb 8
+#define xd_p_reg_ce_cptestfdi0  (*(volatile byte xdata *) 0xFD5A)
+#define    p_reg_ce_cptestfdi0  0xFD5A
+#define reg_ce_cptestfdi0_pos 0
+#define reg_ce_cptestfdi0_len 3
+#define reg_ce_cptestfdi0_lsb 0
+#define xd_p_reg_ce_cptestindex1_7_0    (*(volatile byte xdata *) 0xFD5B)
+#define    p_reg_ce_cptestindex1_7_0    0xFD5B
+#define reg_ce_cptestindex1_7_0_pos 0
+#define reg_ce_cptestindex1_7_0_len 8
+#define reg_ce_cptestindex1_7_0_lsb 0
+#define xd_p_reg_ce_cptestindex1_12_8   (*(volatile byte xdata *) 0xFD5C)
+#define    p_reg_ce_cptestindex1_12_8   0xFD5C
+#define reg_ce_cptestindex1_12_8_pos 0
+#define reg_ce_cptestindex1_12_8_len 5
+#define reg_ce_cptestindex1_12_8_lsb 8
+#define xd_p_reg_ce_cptestfdi1  (*(volatile byte xdata *) 0xFD5D)
+#define    p_reg_ce_cptestfdi1  0xFD5D
+#define reg_ce_cptestfdi1_pos 0
+#define reg_ce_cptestfdi1_len 3
+#define reg_ce_cptestfdi1_lsb 0
+#define xd_p_reg_ce_cptestindex2_7_0    (*(volatile byte xdata *) 0xFD5E)
+#define    p_reg_ce_cptestindex2_7_0    0xFD5E
+#define reg_ce_cptestindex2_7_0_pos 0
+#define reg_ce_cptestindex2_7_0_len 8
+#define reg_ce_cptestindex2_7_0_lsb 0
+#define xd_p_reg_ce_cptestindex2_12_8   (*(volatile byte xdata *) 0xFD5F)
+#define    p_reg_ce_cptestindex2_12_8   0xFD5F
+#define reg_ce_cptestindex2_12_8_pos 0
+#define reg_ce_cptestindex2_12_8_len 5
+#define reg_ce_cptestindex2_12_8_lsb 8
+#define xd_p_reg_ce_cptestfdi2  (*(volatile byte xdata *) 0xFD60)
+#define    p_reg_ce_cptestfdi2  0xFD60
+#define reg_ce_cptestfdi2_pos 0
+#define reg_ce_cptestfdi2_len 3
+#define reg_ce_cptestfdi2_lsb 0
+#define xd_p_reg_ce_cptestindex3_7_0    (*(volatile byte xdata *) 0xFD61)
+#define    p_reg_ce_cptestindex3_7_0    0xFD61
+#define reg_ce_cptestindex3_7_0_pos 0
+#define reg_ce_cptestindex3_7_0_len 8
+#define reg_ce_cptestindex3_7_0_lsb 0
+#define xd_p_reg_ce_cptestindex3_12_8   (*(volatile byte xdata *) 0xFD62)
+#define    p_reg_ce_cptestindex3_12_8   0xFD62
+#define reg_ce_cptestindex3_12_8_pos 0
+#define reg_ce_cptestindex3_12_8_len 5
+#define reg_ce_cptestindex3_12_8_lsb 8
+#define xd_p_reg_ce_cptestfdi3  (*(volatile byte xdata *) 0xFD63)
+#define    p_reg_ce_cptestfdi3  0xFD63
+#define reg_ce_cptestfdi3_pos 0
+#define reg_ce_cptestfdi3_len 3
+#define reg_ce_cptestfdi3_lsb 0
+#define xd_p_reg_ce_cptestindex4_7_0    (*(volatile byte xdata *) 0xFD64)
+#define    p_reg_ce_cptestindex4_7_0    0xFD64
+#define reg_ce_cptestindex4_7_0_pos 0
+#define reg_ce_cptestindex4_7_0_len 8
+#define reg_ce_cptestindex4_7_0_lsb 0
+#define xd_p_reg_ce_cptestindex4_12_8   (*(volatile byte xdata *) 0xFD65)
+#define    p_reg_ce_cptestindex4_12_8   0xFD65
+#define reg_ce_cptestindex4_12_8_pos 0
+#define reg_ce_cptestindex4_12_8_len 5
+#define reg_ce_cptestindex4_12_8_lsb 8
+#define xd_p_reg_ce_cptestfdi4  (*(volatile byte xdata *) 0xFD66)
+#define    p_reg_ce_cptestfdi4  0xFD66
+#define reg_ce_cptestfdi4_pos 0
+#define reg_ce_cptestfdi4_len 3
+#define reg_ce_cptestfdi4_lsb 0
+#define xd_p_reg_ce_cptestindex5_7_0    (*(volatile byte xdata *) 0xFD67)
+#define    p_reg_ce_cptestindex5_7_0    0xFD67
+#define reg_ce_cptestindex5_7_0_pos 0
+#define reg_ce_cptestindex5_7_0_len 8
+#define reg_ce_cptestindex5_7_0_lsb 0
+#define xd_p_reg_ce_cptestindex5_12_8   (*(volatile byte xdata *) 0xFD68)
+#define    p_reg_ce_cptestindex5_12_8   0xFD68
+#define reg_ce_cptestindex5_12_8_pos 0
+#define reg_ce_cptestindex5_12_8_len 5
+#define reg_ce_cptestindex5_12_8_lsb 8
+#define xd_p_reg_ce_cptestfdi5  (*(volatile byte xdata *) 0xFD69)
+#define    p_reg_ce_cptestfdi5  0xFD69
+#define reg_ce_cptestfdi5_pos 0
+#define reg_ce_cptestfdi5_len 3
+#define reg_ce_cptestfdi5_lsb 0
+#define xd_p_reg_ce_cptestindex6_7_0    (*(volatile byte xdata *) 0xFD6A)
+#define    p_reg_ce_cptestindex6_7_0    0xFD6A
+#define reg_ce_cptestindex6_7_0_pos 0
+#define reg_ce_cptestindex6_7_0_len 8
+#define reg_ce_cptestindex6_7_0_lsb 0
+#define xd_p_reg_ce_cptestindex6_12_8   (*(volatile byte xdata *) 0xFD6B)
+#define    p_reg_ce_cptestindex6_12_8   0xFD6B
+#define reg_ce_cptestindex6_12_8_pos 0
+#define reg_ce_cptestindex6_12_8_len 5
+#define reg_ce_cptestindex6_12_8_lsb 8
+#define xd_p_reg_ce_cptestfdi6  (*(volatile byte xdata *) 0xFD6C)
+#define    p_reg_ce_cptestfdi6  0xFD6C
+#define reg_ce_cptestfdi6_pos 0
+#define reg_ce_cptestfdi6_len 3
+#define reg_ce_cptestfdi6_lsb 0
+#define xd_p_reg_ce_cptestindex7_7_0    (*(volatile byte xdata *) 0xFD6D)
+#define    p_reg_ce_cptestindex7_7_0    0xFD6D
+#define reg_ce_cptestindex7_7_0_pos 0
+#define reg_ce_cptestindex7_7_0_len 8
+#define reg_ce_cptestindex7_7_0_lsb 0
+#define xd_p_reg_ce_cptestindex7_12_8   (*(volatile byte xdata *) 0xFD6E)
+#define    p_reg_ce_cptestindex7_12_8   0xFD6E
+#define reg_ce_cptestindex7_12_8_pos 0
+#define reg_ce_cptestindex7_12_8_len 5
+#define reg_ce_cptestindex7_12_8_lsb 8
+#define xd_p_reg_ce_cptestfdi7  (*(volatile byte xdata *) 0xFD6F)
+#define    p_reg_ce_cptestfdi7  0xFD6F
+#define reg_ce_cptestfdi7_pos 0
+#define reg_ce_cptestfdi7_len 3
+#define reg_ce_cptestfdi7_lsb 0
+#define xd_p_reg_ce_cp_replace_tdiout_en    (*(volatile byte xdata *) 0xFD74)
+#define    p_reg_ce_cp_replace_tdiout_en    0xFD74
+#define reg_ce_cp_replace_tdiout_en_pos 0
+#define reg_ce_cp_replace_tdiout_en_len 1
+#define reg_ce_cp_replace_tdiout_en_lsb 0
+#define xd_p_reg_ce_tdi_mask0_en    (*(volatile byte xdata *) 0xFD7D)
+#define    p_reg_ce_tdi_mask0_en    0xFD7D
+#define reg_ce_tdi_mask0_en_pos 0
+#define reg_ce_tdi_mask0_en_len 1
+#define reg_ce_tdi_mask0_en_lsb 0
+#define xd_p_reg_ce_tdi_mask_from0_7_0  (*(volatile byte xdata *) 0xFD7E)
+#define    p_reg_ce_tdi_mask_from0_7_0  0xFD7E
+#define reg_ce_tdi_mask_from0_7_0_pos 0
+#define reg_ce_tdi_mask_from0_7_0_len 8
+#define reg_ce_tdi_mask_from0_7_0_lsb 0
+#define xd_p_reg_ce_tdi_mask_from0_12_8 (*(volatile byte xdata *) 0xFD7F)
+#define    p_reg_ce_tdi_mask_from0_12_8 0xFD7F
+#define reg_ce_tdi_mask_from0_12_8_pos 0
+#define reg_ce_tdi_mask_from0_12_8_len 5
+#define reg_ce_tdi_mask_from0_12_8_lsb 8
+#define xd_p_reg_ce_tdi_mask_to0_7_0    (*(volatile byte xdata *) 0xFD80)
+#define    p_reg_ce_tdi_mask_to0_7_0    0xFD80
+#define reg_ce_tdi_mask_to0_7_0_pos 0
+#define reg_ce_tdi_mask_to0_7_0_len 8
+#define reg_ce_tdi_mask_to0_7_0_lsb 0
+#define xd_p_reg_ce_tdi_mask_to0_12_8   (*(volatile byte xdata *) 0xFD81)
+#define    p_reg_ce_tdi_mask_to0_12_8   0xFD81
+#define reg_ce_tdi_mask_to0_12_8_pos 0
+#define reg_ce_tdi_mask_to0_12_8_len 5
+#define reg_ce_tdi_mask_to0_12_8_lsb 8
+#define xd_p_reg_ce_tdi_mask1_en    (*(volatile byte xdata *) 0xFD82)
+#define    p_reg_ce_tdi_mask1_en    0xFD82
+#define reg_ce_tdi_mask1_en_pos 0
+#define reg_ce_tdi_mask1_en_len 1
+#define reg_ce_tdi_mask1_en_lsb 0
+#define xd_p_reg_ce_tdi_mask_from1_7_0  (*(volatile byte xdata *) 0xFD83)
+#define    p_reg_ce_tdi_mask_from1_7_0  0xFD83
+#define reg_ce_tdi_mask_from1_7_0_pos 0
+#define reg_ce_tdi_mask_from1_7_0_len 8
+#define reg_ce_tdi_mask_from1_7_0_lsb 0
+#define xd_p_reg_ce_tdi_mask_from1_12_8 (*(volatile byte xdata *) 0xFD84)
+#define    p_reg_ce_tdi_mask_from1_12_8 0xFD84
+#define reg_ce_tdi_mask_from1_12_8_pos 0
+#define reg_ce_tdi_mask_from1_12_8_len 5
+#define reg_ce_tdi_mask_from1_12_8_lsb 8
+#define xd_p_reg_ce_tdi_mask_to1_7_0    (*(volatile byte xdata *) 0xFD85)
+#define    p_reg_ce_tdi_mask_to1_7_0    0xFD85
+#define reg_ce_tdi_mask_to1_7_0_pos 0
+#define reg_ce_tdi_mask_to1_7_0_len 8
+#define reg_ce_tdi_mask_to1_7_0_lsb 0
+#define xd_p_reg_ce_tdi_mask_to1_12_8   (*(volatile byte xdata *) 0xFD86)
+#define    p_reg_ce_tdi_mask_to1_12_8   0xFD86
+#define reg_ce_tdi_mask_to1_12_8_pos 0
+#define reg_ce_tdi_mask_to1_12_8_len 5
+#define reg_ce_tdi_mask_to1_12_8_lsb 8
+#define xd_p_reg_ce_2nd_var_max (*(volatile byte xdata *) 0xFD87)
+#define    p_reg_ce_2nd_var_max 0xFD87
+#define reg_ce_2nd_var_max_pos 0
+#define reg_ce_2nd_var_max_len 3
+#define reg_ce_2nd_var_max_lsb 0
+#define xd_p_reg_ce_2nd_cent_forced_en  (*(volatile byte xdata *) 0xFD88)
+#define    p_reg_ce_2nd_cent_forced_en  0xFD88
+#define reg_ce_2nd_cent_forced_en_pos 0
+#define reg_ce_2nd_cent_forced_en_len 1
+#define reg_ce_2nd_cent_forced_en_lsb 0
+#define xd_p_reg_ce_2nd_var_forced_en   (*(volatile byte xdata *) 0xFD89)
+#define    p_reg_ce_2nd_var_forced_en   0xFD89
+#define reg_ce_2nd_var_forced_en_pos 0
+#define reg_ce_2nd_var_forced_en_len 1
+#define reg_ce_2nd_var_forced_en_lsb 0
+#define xd_p_reg_ce_2nd_fctrl_auto_reset_en (*(volatile byte xdata *) 0xFD8A)
+#define    p_reg_ce_2nd_fctrl_auto_reset_en 0xFD8A
+#define reg_ce_2nd_fctrl_auto_reset_en_pos 0
+#define reg_ce_2nd_fctrl_auto_reset_en_len 1
+#define reg_ce_2nd_fctrl_auto_reset_en_lsb 0
+#define xd_p_reg_ce_2nd_cent_auto_clr_en    (*(volatile byte xdata *) 0xFD8B)
+#define    p_reg_ce_2nd_cent_auto_clr_en    0xFD8B
+#define reg_ce_2nd_cent_auto_clr_en_pos 0
+#define reg_ce_2nd_cent_auto_clr_en_len 1
+#define reg_ce_2nd_cent_auto_clr_en_lsb 0
+#define xd_p_reg_ce_2nd_cent_forced_value_7_0   (*(volatile byte xdata *) 0xFD8C)
+#define    p_reg_ce_2nd_cent_forced_value_7_0   0xFD8C
+#define reg_ce_2nd_cent_forced_value_7_0_pos 0
+#define reg_ce_2nd_cent_forced_value_7_0_len 8
+#define reg_ce_2nd_cent_forced_value_7_0_lsb 0
+#define xd_p_reg_ce_2nd_cent_forced_value_11_8  (*(volatile byte xdata *) 0xFD8D)
+#define    p_reg_ce_2nd_cent_forced_value_11_8  0xFD8D
+#define reg_ce_2nd_cent_forced_value_11_8_pos 0
+#define reg_ce_2nd_cent_forced_value_11_8_len 4
+#define reg_ce_2nd_cent_forced_value_11_8_lsb 8
+#define xd_p_reg_ce_2nd_cent_auto_clr_value_7_0 (*(volatile byte xdata *) 0xFD8E)
+#define    p_reg_ce_2nd_cent_auto_clr_value_7_0 0xFD8E
+#define reg_ce_2nd_cent_auto_clr_value_7_0_pos 0
+#define reg_ce_2nd_cent_auto_clr_value_7_0_len 8
+#define reg_ce_2nd_cent_auto_clr_value_7_0_lsb 0
+#define xd_p_reg_ce_2nd_cent_auto_clr_value_11_8    (*(volatile byte xdata *) 0xFD8F)
+#define    p_reg_ce_2nd_cent_auto_clr_value_11_8    0xFD8F
+#define reg_ce_2nd_cent_auto_clr_value_11_8_pos 0
+#define reg_ce_2nd_cent_auto_clr_value_11_8_len 4
+#define reg_ce_2nd_cent_auto_clr_value_11_8_lsb 8
+#define xd_p_reg_ce_gs_s1_var   (*(volatile byte xdata *) 0xFD90)
+#define    p_reg_ce_gs_s1_var   0xFD90
+#define reg_ce_gs_s1_var_pos 0
+#define reg_ce_gs_s1_var_len 4
+#define reg_ce_gs_s1_var_lsb 0
+#define xd_p_reg_ce_2nd_centroid_max_7_0    (*(volatile byte xdata *) 0xFD91)
+#define    p_reg_ce_2nd_centroid_max_7_0    0xFD91
+#define reg_ce_2nd_centroid_max_7_0_pos 0
+#define reg_ce_2nd_centroid_max_7_0_len 8
+#define reg_ce_2nd_centroid_max_7_0_lsb 0
+#define xd_p_reg_ce_2nd_centroid_max_11_8   (*(volatile byte xdata *) 0xFD92)
+#define    p_reg_ce_2nd_centroid_max_11_8   0xFD92
+#define reg_ce_2nd_centroid_max_11_8_pos 0
+#define reg_ce_2nd_centroid_max_11_8_len 4
+#define reg_ce_2nd_centroid_max_11_8_lsb 8
+#define xd_r_reg_ce_2nd_centroid_out_7_0    (*(volatile byte xdata *) 0xFD93)
+#define    r_reg_ce_2nd_centroid_out_7_0    0xFD93
+#define reg_ce_2nd_centroid_out_7_0_pos 0
+#define reg_ce_2nd_centroid_out_7_0_len 8
+#define reg_ce_2nd_centroid_out_7_0_lsb 0
+#define xd_r_reg_ce_2nd_centroid_out_11_8   (*(volatile byte xdata *) 0xFD94)
+#define    r_reg_ce_2nd_centroid_out_11_8   0xFD94
+#define reg_ce_2nd_centroid_out_11_8_pos 0
+#define reg_ce_2nd_centroid_out_11_8_len 4
+#define reg_ce_2nd_centroid_out_11_8_lsb 8
+#define xd_r_reg_ce_2nd_fctrl_rdy   (*(volatile byte xdata *) 0xFD95)
+#define    r_reg_ce_2nd_fctrl_rdy   0xFD95
+#define reg_ce_2nd_fctrl_rdy_pos 0
+#define reg_ce_2nd_fctrl_rdy_len 1
+#define reg_ce_2nd_fctrl_rdy_lsb 0
+#define xd_r_reg_ce_2nd_var (*(volatile byte xdata *) 0xFD96)
+#define    r_reg_ce_2nd_var 0xFD96
+#define reg_ce_2nd_var_pos 0
+#define reg_ce_2nd_var_len 3
+#define reg_ce_2nd_var_lsb 0
+#define xd_r_reg_ce_2nd_bias_7_0    (*(volatile byte xdata *) 0xFD97)
+#define    r_reg_ce_2nd_bias_7_0    0xFD97
+#define reg_ce_2nd_bias_7_0_pos 0
+#define reg_ce_2nd_bias_7_0_len 8
+#define reg_ce_2nd_bias_7_0_lsb 0
+#define xd_r_reg_ce_2nd_bias_11_8   (*(volatile byte xdata *) 0xFD98)
+#define    r_reg_ce_2nd_bias_11_8   0xFD98
+#define reg_ce_2nd_bias_11_8_pos 0
+#define reg_ce_2nd_bias_11_8_len 4
+#define reg_ce_2nd_bias_11_8_lsb 8
+#define xd_r_reg_ce_2nd_m1_7_0  (*(volatile byte xdata *) 0xFD99)
+#define    r_reg_ce_2nd_m1_7_0  0xFD99
+#define reg_ce_2nd_m1_7_0_pos 0
+#define reg_ce_2nd_m1_7_0_len 8
+#define reg_ce_2nd_m1_7_0_lsb 0
+#define xd_r_reg_ce_2nd_m1_11_8 (*(volatile byte xdata *) 0xFD9A)
+#define    r_reg_ce_2nd_m1_11_8 0xFD9A
+#define reg_ce_2nd_m1_11_8_pos 0
+#define reg_ce_2nd_m1_11_8_len 4
+#define reg_ce_2nd_m1_11_8_lsb 8
+#define xd_p_reg_ce_2nd_var_forced_value    (*(volatile byte xdata *) 0xFD9B)
+#define    p_reg_ce_2nd_var_forced_value    0xFD9B
+#define reg_ce_2nd_var_forced_value_pos 0
+#define reg_ce_2nd_var_forced_value_len 3
+#define reg_ce_2nd_var_forced_value_lsb 0
+#define xd_r_reg_ce_2nd_m2_central_7_0  (*(volatile byte xdata *) 0xFD9C)
+#define    r_reg_ce_2nd_m2_central_7_0  0xFD9C
+#define reg_ce_2nd_m2_central_7_0_pos 0
+#define reg_ce_2nd_m2_central_7_0_len 8
+#define reg_ce_2nd_m2_central_7_0_lsb 0
+#define xd_r_reg_ce_2nd_m2_central_15_8 (*(volatile byte xdata *) 0xFD9D)
+#define    r_reg_ce_2nd_m2_central_15_8 0xFD9D
+#define reg_ce_2nd_m2_central_15_8_pos 0
+#define reg_ce_2nd_m2_central_15_8_len 8
+#define reg_ce_2nd_m2_central_15_8_lsb 8
+#define xd_p_reg_ce_2nd_var_default_value   (*(volatile byte xdata *) 0xFD9E)
+#define    p_reg_ce_2nd_var_default_value   0xFD9E
+#define reg_ce_2nd_var_default_value_pos 0
+#define reg_ce_2nd_var_default_value_len 3
+#define reg_ce_2nd_var_default_value_lsb 0
+#define xd_p_reg_ce_2nd_cent_default_value_7_0  (*(volatile byte xdata *) 0xFD9F)
+#define    p_reg_ce_2nd_cent_default_value_7_0  0xFD9F
+#define reg_ce_2nd_cent_default_value_7_0_pos 0
+#define reg_ce_2nd_cent_default_value_7_0_len 8
+#define reg_ce_2nd_cent_default_value_7_0_lsb 0
+#define xd_p_reg_ce_2nd_cent_default_value_11_8 (*(volatile byte xdata *) 0xFDA0)
+#define    p_reg_ce_2nd_cent_default_value_11_8 0xFDA0
+#define reg_ce_2nd_cent_default_value_11_8_pos 0
+#define reg_ce_2nd_cent_default_value_11_8_len 4
+#define reg_ce_2nd_cent_default_value_11_8_lsb 8
+#define xd_p_reg_ce_use_fdi_long    (*(volatile byte xdata *) 0xFDA1)
+#define    p_reg_ce_use_fdi_long    0xFDA1
+#define reg_ce_use_fdi_long_pos 0
+#define reg_ce_use_fdi_long_len 1
+#define reg_ce_use_fdi_long_lsb 0
+#define xd_p_reg_p_ce_tdi_lms_en    (*(volatile byte xdata *) 0xFDA2)
+#define    p_reg_p_ce_tdi_lms_en    0xFDA2
+#define reg_p_ce_tdi_lms_en_pos 0
+#define reg_p_ce_tdi_lms_en_len 1
+#define reg_p_ce_tdi_lms_en_lsb 0
+#define xd_p_reg_p_ce_tdi_lms_bufshift  (*(volatile byte xdata *) 0xFDA3)
+#define    p_reg_p_ce_tdi_lms_bufshift  0xFDA3
+#define reg_p_ce_tdi_lms_bufshift_pos 0
+#define reg_p_ce_tdi_lms_bufshift_len 2
+#define reg_p_ce_tdi_lms_bufshift_lsb 0
+#define xd_p_reg_p_ce_tdi_lms_ave_ratio (*(volatile byte xdata *) 0xFDA4)
+#define    p_reg_p_ce_tdi_lms_ave_ratio 0xFDA4
+#define reg_p_ce_tdi_lms_ave_ratio_pos 0
+#define reg_p_ce_tdi_lms_ave_ratio_len 5
+#define reg_p_ce_tdi_lms_ave_ratio_lsb 0
+#define xd_p_reg_p_ce_conf2_in_con0_en  (*(volatile byte xdata *) 0xFDA5)
+#define    p_reg_p_ce_conf2_in_con0_en  0xFDA5
+#define reg_p_ce_conf2_in_con0_en_pos 0
+#define reg_p_ce_conf2_in_con0_en_len 1
+#define reg_p_ce_conf2_in_con0_en_lsb 0
+// biu_reg.h 7-6-2007
+// gen_biu Ver 1.0 generated by
+#define xd_p_fec_rsd_packet_unit_7_0    (*(volatile byte xdata *) 0xF700)
+#define    p_fec_rsd_packet_unit_7_0    0xF700
+#define fec_rsd_packet_unit_7_0_pos 0
+#define fec_rsd_packet_unit_7_0_len 8
+#define fec_rsd_packet_unit_7_0_lsb 0
+#define xd_p_fec_rsd_packet_unit_15_8   (*(volatile byte xdata *) 0xF701)
+#define    p_fec_rsd_packet_unit_15_8   0xF701
+#define fec_rsd_packet_unit_15_8_pos 0
+#define fec_rsd_packet_unit_15_8_len 8
+#define fec_rsd_packet_unit_15_8_lsb 8
+#define xd_r_reg_rsd_bit_err_cnt_7_0    (*(volatile byte xdata *) 0xF702)
+#define    r_reg_rsd_bit_err_cnt_7_0    0xF702
+#define reg_rsd_bit_err_cnt_7_0_pos 0
+#define reg_rsd_bit_err_cnt_7_0_len 8
+#define reg_rsd_bit_err_cnt_7_0_lsb 0
+#define xd_r_reg_rsd_bit_err_cnt_15_8   (*(volatile byte xdata *) 0xF703)
+#define    r_reg_rsd_bit_err_cnt_15_8   0xF703
+#define reg_rsd_bit_err_cnt_15_8_pos 0
+#define reg_rsd_bit_err_cnt_15_8_len 8
+#define reg_rsd_bit_err_cnt_15_8_lsb 8
+#define xd_r_reg_rsd_bit_err_cnt_23_16  (*(volatile byte xdata *) 0xF704)
+#define    r_reg_rsd_bit_err_cnt_23_16  0xF704
+#define reg_rsd_bit_err_cnt_23_16_pos 0
+#define reg_rsd_bit_err_cnt_23_16_len 8
+#define reg_rsd_bit_err_cnt_23_16_lsb 16
+#define xd_r_reg_rsd_abort_packet_cnt_7_0   (*(volatile byte xdata *) 0xF705)
+#define    r_reg_rsd_abort_packet_cnt_7_0   0xF705
+#define reg_rsd_abort_packet_cnt_7_0_pos 0
+#define reg_rsd_abort_packet_cnt_7_0_len 8
+#define reg_rsd_abort_packet_cnt_7_0_lsb 0
+#define xd_r_reg_rsd_abort_packet_cnt_15_8  (*(volatile byte xdata *) 0xF706)
+#define    r_reg_rsd_abort_packet_cnt_15_8  0xF706
+#define reg_rsd_abort_packet_cnt_15_8_pos 0
+#define reg_rsd_abort_packet_cnt_15_8_len 8
+#define reg_rsd_abort_packet_cnt_15_8_lsb 8
+#define xd_p_fec_RSD_PKT_NUM_PER_UNIT_7_0   (*(volatile byte xdata *) 0xF707)
+#define    p_fec_RSD_PKT_NUM_PER_UNIT_7_0   0xF707
+#define fec_RSD_PKT_NUM_PER_UNIT_7_0_pos 0
+#define fec_RSD_PKT_NUM_PER_UNIT_7_0_len 8
+#define fec_RSD_PKT_NUM_PER_UNIT_7_0_lsb 0
+#define xd_p_fec_RSD_PKT_NUM_PER_UNIT_15_8  (*(volatile byte xdata *) 0xF708)
+#define    p_fec_RSD_PKT_NUM_PER_UNIT_15_8  0xF708
+#define fec_RSD_PKT_NUM_PER_UNIT_15_8_pos 0
+#define fec_RSD_PKT_NUM_PER_UNIT_15_8_len 8
+#define fec_RSD_PKT_NUM_PER_UNIT_15_8_lsb 8
+#define xd_p_fec_RS_TH_1_7_0    (*(volatile byte xdata *) 0xF709)
+#define    p_fec_RS_TH_1_7_0    0xF709
+#define fec_RS_TH_1_7_0_pos 0
+#define fec_RS_TH_1_7_0_len 8
+#define fec_RS_TH_1_7_0_lsb 0
+#define xd_p_fec_RS_TH_1_15_8   (*(volatile byte xdata *) 0xF70A)
+#define    p_fec_RS_TH_1_15_8   0xF70A
+#define fec_RS_TH_1_15_8_pos 0
+#define fec_RS_TH_1_15_8_len 8
+#define fec_RS_TH_1_15_8_lsb 8
+#define xd_p_fec_RS_TH_2    (*(volatile byte xdata *) 0xF70B)
+#define    p_fec_RS_TH_2    0xF70B
+#define fec_RS_TH_2_pos 0
+#define fec_RS_TH_2_len 8
+#define fec_RS_TH_2_lsb 0
+#define xd_p_fec_rsd_ber_rst    (*(volatile byte xdata *) 0xF70C)
+#define    p_fec_rsd_ber_rst    0xF70C
+#define fec_rsd_ber_rst_pos 0
+#define fec_rsd_ber_rst_len 1
+#define fec_rsd_ber_rst_lsb 0
+#define xd_p_reg_rsd_ber_rdy    (*(volatile byte xdata *) 0xF70D)
+#define    p_reg_rsd_ber_rdy    0xF70D
+#define reg_rsd_ber_rdy_pos 0
+#define reg_rsd_ber_rdy_len 1
+#define reg_rsd_ber_rdy_lsb 0
+#define xd_p_reg_rsd_trigger_retrain    (*(volatile byte xdata *) 0xF70E)
+#define    p_reg_rsd_trigger_retrain    0xF70E
+#define reg_rsd_trigger_retrain_pos 0
+#define reg_rsd_trigger_retrain_len 1
+#define reg_rsd_trigger_retrain_lsb 0
+#define xd_p_reg_sync_recover   (*(volatile byte xdata *) 0xF70F)
+#define    p_reg_sync_recover   0xF70F
+#define reg_sync_recover_pos 0
+#define reg_sync_recover_len 1
+#define reg_sync_recover_lsb 0
+#define xd_p_fec_crc_en (*(volatile byte xdata *) 0xF710)
+#define    p_fec_crc_en 0xF710
+#define fec_crc_en_pos 0
+#define fec_crc_en_len 1
+#define fec_crc_en_lsb 0
+#define xd_p_fec_mon_en (*(volatile byte xdata *) 0xF711)
+#define    p_fec_mon_en 0xF711
+#define fec_mon_en_pos 0
+#define fec_mon_en_len 1
+#define fec_mon_en_lsb 0
+#define xd_p_reg_sync_chk   (*(volatile byte xdata *) 0xF712)
+#define    p_reg_sync_chk   0xF712
+#define reg_sync_chk_pos 0
+#define reg_sync_chk_len 1
+#define reg_sync_chk_lsb 0
+#define xd_p_fec_dummy_reg_2    (*(volatile byte xdata *) 0xF713)
+#define    p_fec_dummy_reg_2    0xF713
+#define fec_dummy_reg_2_pos 0
+#define fec_dummy_reg_2_len 3
+#define fec_dummy_reg_2_lsb 0
+#define xd_p_reg_fec_data_en    (*(volatile byte xdata *) 0xF714)
+#define    p_reg_fec_data_en    0xF714
+#define reg_fec_data_en_pos 0
+#define reg_fec_data_en_len 1
+#define reg_fec_data_en_lsb 0
+#define xd_p_fec_vtb_rsd_mon_en (*(volatile byte xdata *) 0xF715)
+#define    p_fec_vtb_rsd_mon_en 0xF715
+#define fec_vtb_rsd_mon_en_pos 0
+#define fec_vtb_rsd_mon_en_len 1
+#define fec_vtb_rsd_mon_en_lsb 0
+#define xd_p_reg_fec_sw_rst (*(volatile byte xdata *) 0xF716)
+#define    p_reg_fec_sw_rst 0xF716
+#define reg_fec_sw_rst_pos 0
+#define reg_fec_sw_rst_len 1
+#define reg_fec_sw_rst_lsb 0
+#define xd_r_fec_vtb_pm_crc (*(volatile byte xdata *) 0xF717)
+#define    r_fec_vtb_pm_crc 0xF717
+#define fec_vtb_pm_crc_pos 0
+#define fec_vtb_pm_crc_len 8
+#define fec_vtb_pm_crc_lsb 0
+#define xd_r_fec_vtb_tb_7_crc   (*(volatile byte xdata *) 0xF718)
+#define    r_fec_vtb_tb_7_crc   0xF718
+#define fec_vtb_tb_7_crc_pos 0
+#define fec_vtb_tb_7_crc_len 8
+#define fec_vtb_tb_7_crc_lsb 0
+#define xd_r_fec_vtb_tb_6_crc   (*(volatile byte xdata *) 0xF719)
+#define    r_fec_vtb_tb_6_crc   0xF719
+#define fec_vtb_tb_6_crc_pos 0
+#define fec_vtb_tb_6_crc_len 8
+#define fec_vtb_tb_6_crc_lsb 0
+#define xd_r_fec_vtb_tb_5_crc   (*(volatile byte xdata *) 0xF71A)
+#define    r_fec_vtb_tb_5_crc   0xF71A
+#define fec_vtb_tb_5_crc_pos 0
+#define fec_vtb_tb_5_crc_len 8
+#define fec_vtb_tb_5_crc_lsb 0
+#define xd_r_fec_vtb_tb_4_crc   (*(volatile byte xdata *) 0xF71B)
+#define    r_fec_vtb_tb_4_crc   0xF71B
+#define fec_vtb_tb_4_crc_pos 0
+#define fec_vtb_tb_4_crc_len 8
+#define fec_vtb_tb_4_crc_lsb 0
+#define xd_r_fec_vtb_tb_3_crc   (*(volatile byte xdata *) 0xF71C)
+#define    r_fec_vtb_tb_3_crc   0xF71C
+#define fec_vtb_tb_3_crc_pos 0
+#define fec_vtb_tb_3_crc_len 8
+#define fec_vtb_tb_3_crc_lsb 0
+#define xd_r_fec_vtb_tb_2_crc   (*(volatile byte xdata *) 0xF71D)
+#define    r_fec_vtb_tb_2_crc   0xF71D
+#define fec_vtb_tb_2_crc_pos 0
+#define fec_vtb_tb_2_crc_len 8
+#define fec_vtb_tb_2_crc_lsb 0
+#define xd_r_fec_vtb_tb_1_crc   (*(volatile byte xdata *) 0xF71E)
+#define    r_fec_vtb_tb_1_crc   0xF71E
+#define fec_vtb_tb_1_crc_pos 0
+#define fec_vtb_tb_1_crc_len 8
+#define fec_vtb_tb_1_crc_lsb 0
+#define xd_r_fec_vtb_tb_0_crc   (*(volatile byte xdata *) 0xF71F)
+#define    r_fec_vtb_tb_0_crc   0xF71F
+#define fec_vtb_tb_0_crc_pos 0
+#define fec_vtb_tb_0_crc_len 8
+#define fec_vtb_tb_0_crc_lsb 0
+#define xd_r_fec_rsd_bank0_crc  (*(volatile byte xdata *) 0xF720)
+#define    r_fec_rsd_bank0_crc  0xF720
+#define fec_rsd_bank0_crc_pos 0
+#define fec_rsd_bank0_crc_len 8
+#define fec_rsd_bank0_crc_lsb 0
+#define xd_r_fec_rsd_bank1_crc  (*(volatile byte xdata *) 0xF721)
+#define    r_fec_rsd_bank1_crc  0xF721
+#define fec_rsd_bank1_crc_pos 0
+#define fec_rsd_bank1_crc_len 8
+#define fec_rsd_bank1_crc_lsb 0
+#define xd_r_fec_idi_vtb_crc    (*(volatile byte xdata *) 0xF722)
+#define    r_fec_idi_vtb_crc    0xF722
+#define fec_idi_vtb_crc_pos 0
+#define fec_idi_vtb_crc_len 8
+#define fec_idi_vtb_crc_lsb 0
+#define xd_p_reg_fec_rsd_packet_unit_exp    (*(volatile byte xdata *) 0xF723)
+#define    p_reg_fec_rsd_packet_unit_exp    0xF723
+#define reg_fec_rsd_packet_unit_exp_pos 0
+#define reg_fec_rsd_packet_unit_exp_len 4
+#define reg_fec_rsd_packet_unit_exp_lsb 0
+#define xd_p_reg_rsd_bit_err_exp_rdy    (*(volatile byte xdata *) 0xF724)
+#define    p_reg_rsd_bit_err_exp_rdy    0xF724
+#define reg_rsd_bit_err_exp_rdy_pos 0
+#define reg_rsd_bit_err_exp_rdy_len 1
+#define reg_rsd_bit_err_exp_rdy_lsb 0
+#define xd_r_reg_rsd_bit_err_exp    (*(volatile byte xdata *) 0xF725)
+#define    r_reg_rsd_bit_err_exp    0xF725
+#define reg_rsd_bit_err_exp_pos 0
+#define reg_rsd_bit_err_exp_len 5
+#define reg_rsd_bit_err_exp_lsb 0
+#define xd_p_fec_rsd_packet_unit1_7_0   (*(volatile byte xdata *) 0xF726)
+#define    p_fec_rsd_packet_unit1_7_0   0xF726
+#define fec_rsd_packet_unit1_7_0_pos 0
+#define fec_rsd_packet_unit1_7_0_len 8
+#define fec_rsd_packet_unit1_7_0_lsb 0
+#define xd_p_fec_rsd_packet_unit1_15_8  (*(volatile byte xdata *) 0xF727)
+#define    p_fec_rsd_packet_unit1_15_8  0xF727
+#define fec_rsd_packet_unit1_15_8_pos 0
+#define fec_rsd_packet_unit1_15_8_len 8
+#define fec_rsd_packet_unit1_15_8_lsb 8
+#define xd_r_reg_rsd_bit_err_cnt1_7_0   (*(volatile byte xdata *) 0xF728)
+#define    r_reg_rsd_bit_err_cnt1_7_0   0xF728
+#define reg_rsd_bit_err_cnt1_7_0_pos 0
+#define reg_rsd_bit_err_cnt1_7_0_len 8
+#define reg_rsd_bit_err_cnt1_7_0_lsb 0
+#define xd_r_reg_rsd_bit_err_cnt1_15_8  (*(volatile byte xdata *) 0xF729)
+#define    r_reg_rsd_bit_err_cnt1_15_8  0xF729
+#define reg_rsd_bit_err_cnt1_15_8_pos 0
+#define reg_rsd_bit_err_cnt1_15_8_len 8
+#define reg_rsd_bit_err_cnt1_15_8_lsb 8
+#define xd_r_reg_rsd_bit_err_cnt1_23_16 (*(volatile byte xdata *) 0xF72A)
+#define    r_reg_rsd_bit_err_cnt1_23_16 0xF72A
+#define reg_rsd_bit_err_cnt1_23_16_pos 0
+#define reg_rsd_bit_err_cnt1_23_16_len 8
+#define reg_rsd_bit_err_cnt1_23_16_lsb 16
+#define xd_r_reg_rsd_abort_packet_cnt1_7_0  (*(volatile byte xdata *) 0xF72B)
+#define    r_reg_rsd_abort_packet_cnt1_7_0  0xF72B
+#define reg_rsd_abort_packet_cnt1_7_0_pos 0
+#define reg_rsd_abort_packet_cnt1_7_0_len 8
+#define reg_rsd_abort_packet_cnt1_7_0_lsb 0
+#define xd_r_reg_rsd_abort_packet_cnt1_15_8 (*(volatile byte xdata *) 0xF72C)
+#define    r_reg_rsd_abort_packet_cnt1_15_8 0xF72C
+#define reg_rsd_abort_packet_cnt1_15_8_pos 0
+#define reg_rsd_abort_packet_cnt1_15_8_len 8
+#define reg_rsd_abort_packet_cnt1_15_8_lsb 8
+#define xd_p_fec_rsd_ber_rst1   (*(volatile byte xdata *) 0xF72D)
+#define    p_fec_rsd_ber_rst1   0xF72D
+#define fec_rsd_ber_rst1_pos 0
+#define fec_rsd_ber_rst1_len 1
+#define fec_rsd_ber_rst1_lsb 0
+#define xd_p_reg_rsd_ber_rdy1   (*(volatile byte xdata *) 0xF72E)
+#define    p_reg_rsd_ber_rdy1   0xF72E
+#define reg_rsd_ber_rdy1_pos 0
+#define reg_rsd_ber_rdy1_len 1
+#define reg_rsd_ber_rdy1_lsb 0
+#define xd_p_reg_dca_txmod_sel  (*(volatile byte xdata *) 0xF72F)
+#define    p_reg_dca_txmod_sel  0xF72F
+#define reg_dca_txmod_sel_pos 0
+#define reg_dca_txmod_sel_len 1
+#define reg_dca_txmod_sel_lsb 0
+#define xd_p_reg_dca_platch (*(volatile byte xdata *) 0xF730)
+#define    p_reg_dca_platch 0xF730
+#define reg_dca_platch_pos 0
+#define reg_dca_platch_len 1
+#define reg_dca_platch_lsb 0
+#define xd_p_reg_dca_upper_chip (*(volatile byte xdata *) 0xF731)
+#define    p_reg_dca_upper_chip 0xF731
+#define reg_dca_upper_chip_pos 0
+#define reg_dca_upper_chip_len 1
+#define reg_dca_upper_chip_lsb 0
+#define xd_p_reg_dca_lower_chip (*(volatile byte xdata *) 0xF732)
+#define    p_reg_dca_lower_chip 0xF732
+#define reg_dca_lower_chip_pos 0
+#define reg_dca_lower_chip_len 1
+#define reg_dca_lower_chip_lsb 0
+#define xd_p_reg_dca_enl    (*(volatile byte xdata *) 0xF733)
+#define    p_reg_dca_enl    0xF733
+#define reg_dca_enl_pos 0
+#define reg_dca_enl_len 1
+#define reg_dca_enl_lsb 0
+#define xd_p_reg_dca_enu    (*(volatile byte xdata *) 0xF734)
+#define    p_reg_dca_enu    0xF734
+#define reg_dca_enu_pos 0
+#define reg_dca_enu_len 1
+#define reg_dca_enu_lsb 0
+#define xd_p_reg_dca_th (*(volatile byte xdata *) 0xF735)
+#define    p_reg_dca_th 0xF735
+#define reg_dca_th_pos 0
+#define reg_dca_th_len 5
+#define reg_dca_th_lsb 0
+#define xd_p_reg_dca_scale  (*(volatile byte xdata *) 0xF736)
+#define    p_reg_dca_scale  0xF736
+#define reg_dca_scale_pos 0
+#define reg_dca_scale_len 4
+#define reg_dca_scale_lsb 0
+#define xd_p_reg_dca_tone_7_0   (*(volatile byte xdata *) 0xF737)
+#define    p_reg_dca_tone_7_0   0xF737
+#define reg_dca_tone_7_0_pos 0
+#define reg_dca_tone_7_0_len 8
+#define reg_dca_tone_7_0_lsb 0
+#define xd_p_reg_dca_tone_12_8  (*(volatile byte xdata *) 0xF738)
+#define    p_reg_dca_tone_12_8  0xF738
+#define reg_dca_tone_12_8_pos 0
+#define reg_dca_tone_12_8_len 5
+#define reg_dca_tone_12_8_lsb 8
+#define xd_p_reg_dca_time_7_0   (*(volatile byte xdata *) 0xF739)
+#define    p_reg_dca_time_7_0   0xF739
+#define reg_dca_time_7_0_pos 0
+#define reg_dca_time_7_0_len 8
+#define reg_dca_time_7_0_lsb 0
+#define xd_p_reg_dca_time_15_8  (*(volatile byte xdata *) 0xF73A)
+#define    p_reg_dca_time_15_8  0xF73A
+#define reg_dca_time_15_8_pos 0
+#define reg_dca_time_15_8_len 8
+#define reg_dca_time_15_8_lsb 8
+#define xd_r_fec_dcasm  (*(volatile byte xdata *) 0xF73B)
+#define    r_fec_dcasm  0xF73B
+#define fec_dcasm_pos 0
+#define fec_dcasm_len 3
+#define fec_dcasm_lsb 0
+#define xd_p_reg_dca_stand_alone    (*(volatile byte xdata *) 0xF73C)
+#define    p_reg_dca_stand_alone    0xF73C
+#define reg_dca_stand_alone_pos 0
+#define reg_dca_stand_alone_len 1
+#define reg_dca_stand_alone_lsb 0
+#define xd_p_reg_dca_upper_out_en   (*(volatile byte xdata *) 0xF73D)
+#define    p_reg_dca_upper_out_en   0xF73D
+#define reg_dca_upper_out_en_pos 0
+#define reg_dca_upper_out_en_len 1
+#define reg_dca_upper_out_en_lsb 0
+#define xd_p_reg_dca_rc_en  (*(volatile byte xdata *) 0xF73E)
+#define    p_reg_dca_rc_en  0xF73E
+#define reg_dca_rc_en_pos 0
+#define reg_dca_rc_en_len 1
+#define reg_dca_rc_en_lsb 0
+#define xd_p_reg_dca_retrain_send   (*(volatile byte xdata *) 0xF73F)
+#define    p_reg_dca_retrain_send   0xF73F
+#define reg_dca_retrain_send_pos 0
+#define reg_dca_retrain_send_len 1
+#define reg_dca_retrain_send_lsb 0
+#define xd_p_reg_dca_retrain_rec    (*(volatile byte xdata *) 0xF740)
+#define    p_reg_dca_retrain_rec    0xF740
+#define reg_dca_retrain_rec_pos 0
+#define reg_dca_retrain_rec_len 1
+#define reg_dca_retrain_rec_lsb 0
+#define xd_p_reg_dca_gi_gap (*(volatile byte xdata *) 0xF741)
+#define    p_reg_dca_gi_gap 0xF741
+#define reg_dca_gi_gap_pos 0
+#define reg_dca_gi_gap_len 8
+#define reg_dca_gi_gap_lsb 0
+#define xd_r_reg_dca_rec_up_tpsd_txmod  (*(volatile byte xdata *) 0xF742)
+#define    r_reg_dca_rec_up_tpsd_txmod  0xF742
+#define reg_dca_rec_up_tpsd_txmod_pos 0
+#define reg_dca_rec_up_tpsd_txmod_len 2
+#define reg_dca_rec_up_tpsd_txmod_lsb 0
+#define xd_r_reg_dca_rec_up_tpsd_const  (*(volatile byte xdata *) 0xF743)
+#define    r_reg_dca_rec_up_tpsd_const  0xF743
+#define reg_dca_rec_up_tpsd_const_pos 0
+#define reg_dca_rec_up_tpsd_const_len 2
+#define reg_dca_rec_up_tpsd_const_lsb 0
+#define xd_r_reg_dca_rec_up_tpsd_indep  (*(volatile byte xdata *) 0xF744)
+#define    r_reg_dca_rec_up_tpsd_indep  0xF744
+#define reg_dca_rec_up_tpsd_indep_pos 0
+#define reg_dca_rec_up_tpsd_indep_len 1
+#define reg_dca_rec_up_tpsd_indep_lsb 0
+#define xd_r_reg_dca_rec_up_tpsd_hier   (*(volatile byte xdata *) 0xF745)
+#define    r_reg_dca_rec_up_tpsd_hier   0xF745
+#define reg_dca_rec_up_tpsd_hier_pos 0
+#define reg_dca_rec_up_tpsd_hier_len 2
+#define reg_dca_rec_up_tpsd_hier_lsb 0
+#define xd_r_reg_dca_rec_up_tpsd_hpcr   (*(volatile byte xdata *) 0xF746)
+#define    r_reg_dca_rec_up_tpsd_hpcr   0xF746
+#define reg_dca_rec_up_tpsd_hpcr_pos 0
+#define reg_dca_rec_up_tpsd_hpcr_len 3
+#define reg_dca_rec_up_tpsd_hpcr_lsb 0
+#define xd_r_reg_dca_rec_up_tpsd_lpcr   (*(volatile byte xdata *) 0xF747)
+#define    r_reg_dca_rec_up_tpsd_lpcr   0xF747
+#define reg_dca_rec_up_tpsd_lpcr_pos 0
+#define reg_dca_rec_up_tpsd_lpcr_len 3
+#define reg_dca_rec_up_tpsd_lpcr_lsb 0
+#define xd_r_reg_dca_rec_up_tpsd_lock   (*(volatile byte xdata *) 0xF748)
+#define    r_reg_dca_rec_up_tpsd_lock   0xF748
+#define reg_dca_rec_up_tpsd_lock_pos 0
+#define reg_dca_rec_up_tpsd_lock_len 1
+#define reg_dca_rec_up_tpsd_lock_lsb 0
+#define xd_r_reg_dca_rec_lo_tpsd_txmod  (*(volatile byte xdata *) 0xF749)
+#define    r_reg_dca_rec_lo_tpsd_txmod  0xF749
+#define reg_dca_rec_lo_tpsd_txmod_pos 0
+#define reg_dca_rec_lo_tpsd_txmod_len 2
+#define reg_dca_rec_lo_tpsd_txmod_lsb 0
+#define xd_r_reg_dca_rec_lo_tpsd_const  (*(volatile byte xdata *) 0xF74A)
+#define    r_reg_dca_rec_lo_tpsd_const  0xF74A
+#define reg_dca_rec_lo_tpsd_const_pos 0
+#define reg_dca_rec_lo_tpsd_const_len 2
+#define reg_dca_rec_lo_tpsd_const_lsb 0
+#define xd_r_reg_dca_rec_lo_tpsd_indep  (*(volatile byte xdata *) 0xF74B)
+#define    r_reg_dca_rec_lo_tpsd_indep  0xF74B
+#define reg_dca_rec_lo_tpsd_indep_pos 0
+#define reg_dca_rec_lo_tpsd_indep_len 1
+#define reg_dca_rec_lo_tpsd_indep_lsb 0
+#define xd_r_reg_dca_rec_lo_tpsd_hier   (*(volatile byte xdata *) 0xF74C)
+#define    r_reg_dca_rec_lo_tpsd_hier   0xF74C
+#define reg_dca_rec_lo_tpsd_hier_pos 0
+#define reg_dca_rec_lo_tpsd_hier_len 2
+#define reg_dca_rec_lo_tpsd_hier_lsb 0
+#define xd_r_reg_dca_rec_lo_tpsd_hpcr   (*(volatile byte xdata *) 0xF74D)
+#define    r_reg_dca_rec_lo_tpsd_hpcr   0xF74D
+#define reg_dca_rec_lo_tpsd_hpcr_pos 0
+#define reg_dca_rec_lo_tpsd_hpcr_len 3
+#define reg_dca_rec_lo_tpsd_hpcr_lsb 0
+#define xd_r_reg_dca_rec_lo_tpsd_lpcr   (*(volatile byte xdata *) 0xF74E)
+#define    r_reg_dca_rec_lo_tpsd_lpcr   0xF74E
+#define reg_dca_rec_lo_tpsd_lpcr_pos 0
+#define reg_dca_rec_lo_tpsd_lpcr_len 3
+#define reg_dca_rec_lo_tpsd_lpcr_lsb 0
+#define xd_r_reg_dca_rec_lo_tpsd_lock   (*(volatile byte xdata *) 0xF74F)
+#define    r_reg_dca_rec_lo_tpsd_lock   0xF74F
+#define reg_dca_rec_lo_tpsd_lock_pos 0
+#define reg_dca_rec_lo_tpsd_lock_len 1
+#define reg_dca_rec_lo_tpsd_lock_lsb 0
+#define xd_p_reg_dca_gpr_ctr_up_send    (*(volatile byte xdata *) 0xF750)
+#define    p_reg_dca_gpr_ctr_up_send    0xF750
+#define reg_dca_gpr_ctr_up_send_pos 0
+#define reg_dca_gpr_ctr_up_send_len 8
+#define reg_dca_gpr_ctr_up_send_lsb 0
+#define xd_p_reg_dca_gpr_dat_up_send_0  (*(volatile byte xdata *) 0xF751)
+#define    p_reg_dca_gpr_dat_up_send_0  0xF751
+#define reg_dca_gpr_dat_up_send_0_pos 0
+#define reg_dca_gpr_dat_up_send_0_len 8
+#define reg_dca_gpr_dat_up_send_0_lsb 0
+#define xd_p_reg_dca_gpr_dat_up_send_1  (*(volatile byte xdata *) 0xF752)
+#define    p_reg_dca_gpr_dat_up_send_1  0xF752
+#define reg_dca_gpr_dat_up_send_1_pos 0
+#define reg_dca_gpr_dat_up_send_1_len 8
+#define reg_dca_gpr_dat_up_send_1_lsb 0
+#define xd_p_reg_dca_gpr_dat_up_send_2  (*(volatile byte xdata *) 0xF753)
+#define    p_reg_dca_gpr_dat_up_send_2  0xF753
+#define reg_dca_gpr_dat_up_send_2_pos 0
+#define reg_dca_gpr_dat_up_send_2_len 8
+#define reg_dca_gpr_dat_up_send_2_lsb 0
+#define xd_p_reg_dca_gpr_dat_up_send_3  (*(volatile byte xdata *) 0xF754)
+#define    p_reg_dca_gpr_dat_up_send_3  0xF754
+#define reg_dca_gpr_dat_up_send_3_pos 0
+#define reg_dca_gpr_dat_up_send_3_len 8
+#define reg_dca_gpr_dat_up_send_3_lsb 0
+#define xd_p_reg_dca_gpr_dat_up_send_4  (*(volatile byte xdata *) 0xF755)
+#define    p_reg_dca_gpr_dat_up_send_4  0xF755
+#define reg_dca_gpr_dat_up_send_4_pos 0
+#define reg_dca_gpr_dat_up_send_4_len 8
+#define reg_dca_gpr_dat_up_send_4_lsb 0
+#define xd_p_reg_dca_gpr_dat_up_send_5  (*(volatile byte xdata *) 0xF756)
+#define    p_reg_dca_gpr_dat_up_send_5  0xF756
+#define reg_dca_gpr_dat_up_send_5_pos 0
+#define reg_dca_gpr_dat_up_send_5_len 8
+#define reg_dca_gpr_dat_up_send_5_lsb 0
+#define xd_p_reg_dca_over_wr_up_send    (*(volatile byte xdata *) 0xF757)
+#define    p_reg_dca_over_wr_up_send    0xF757
+#define reg_dca_over_wr_up_send_pos 0
+#define reg_dca_over_wr_up_send_len 1
+#define reg_dca_over_wr_up_send_lsb 0
+#define xd_p_reg_dca_int_up_send    (*(volatile byte xdata *) 0xF758)
+#define    p_reg_dca_int_up_send    0xF758
+#define reg_dca_int_up_send_pos 0
+#define reg_dca_int_up_send_len 1
+#define reg_dca_int_up_send_lsb 0
+#define xd_p_reg_dca_gpr_ctr_lo_send    (*(volatile byte xdata *) 0xF759)
+#define    p_reg_dca_gpr_ctr_lo_send    0xF759
+#define reg_dca_gpr_ctr_lo_send_pos 0
+#define reg_dca_gpr_ctr_lo_send_len 8
+#define reg_dca_gpr_ctr_lo_send_lsb 0
+#define xd_p_reg_dca_gpr_dat_lo_send_0  (*(volatile byte xdata *) 0xF75A)
+#define    p_reg_dca_gpr_dat_lo_send_0  0xF75A
+#define reg_dca_gpr_dat_lo_send_0_pos 0
+#define reg_dca_gpr_dat_lo_send_0_len 8
+#define reg_dca_gpr_dat_lo_send_0_lsb 0
+#define xd_p_reg_dca_gpr_dat_lo_send_1  (*(volatile byte xdata *) 0xF75B)
+#define    p_reg_dca_gpr_dat_lo_send_1  0xF75B
+#define reg_dca_gpr_dat_lo_send_1_pos 0
+#define reg_dca_gpr_dat_lo_send_1_len 8
+#define reg_dca_gpr_dat_lo_send_1_lsb 0
+#define xd_p_reg_dca_gpr_dat_lo_send_2  (*(volatile byte xdata *) 0xF75C)
+#define    p_reg_dca_gpr_dat_lo_send_2  0xF75C
+#define reg_dca_gpr_dat_lo_send_2_pos 0
+#define reg_dca_gpr_dat_lo_send_2_len 8
+#define reg_dca_gpr_dat_lo_send_2_lsb 0
+#define xd_p_reg_dca_gpr_dat_lo_send_3  (*(volatile byte xdata *) 0xF75D)
+#define    p_reg_dca_gpr_dat_lo_send_3  0xF75D
+#define reg_dca_gpr_dat_lo_send_3_pos 0
+#define reg_dca_gpr_dat_lo_send_3_len 8
+#define reg_dca_gpr_dat_lo_send_3_lsb 0
+#define xd_p_reg_dca_gpr_dat_lo_send_4  (*(volatile byte xdata *) 0xF75E)
+#define    p_reg_dca_gpr_dat_lo_send_4  0xF75E
+#define reg_dca_gpr_dat_lo_send_4_pos 0
+#define reg_dca_gpr_dat_lo_send_4_len 8
+#define reg_dca_gpr_dat_lo_send_4_lsb 0
+#define xd_p_reg_dca_gpr_dat_lo_send_5  (*(volatile byte xdata *) 0xF75F)
+#define    p_reg_dca_gpr_dat_lo_send_5  0xF75F
+#define reg_dca_gpr_dat_lo_send_5_pos 0
+#define reg_dca_gpr_dat_lo_send_5_len 8
+#define reg_dca_gpr_dat_lo_send_5_lsb 0
+#define xd_p_reg_dca_over_wr_lo_send    (*(volatile byte xdata *) 0xF760)
+#define    p_reg_dca_over_wr_lo_send    0xF760
+#define reg_dca_over_wr_lo_send_pos 0
+#define reg_dca_over_wr_lo_send_len 1
+#define reg_dca_over_wr_lo_send_lsb 0
+#define xd_p_reg_dca_int_lo_send    (*(volatile byte xdata *) 0xF761)
+#define    p_reg_dca_int_lo_send    0xF761
+#define reg_dca_int_lo_send_pos 0
+#define reg_dca_int_lo_send_len 1
+#define reg_dca_int_lo_send_lsb 0
+#define xd_r_reg_dca_gpr_ctr_up_rec (*(volatile byte xdata *) 0xF762)
+#define    r_reg_dca_gpr_ctr_up_rec 0xF762
+#define reg_dca_gpr_ctr_up_rec_pos 0
+#define reg_dca_gpr_ctr_up_rec_len 8
+#define reg_dca_gpr_ctr_up_rec_lsb 0
+#define xd_r_reg_dca_gpr_dat_up_rec_0   (*(volatile byte xdata *) 0xF763)
+#define    r_reg_dca_gpr_dat_up_rec_0   0xF763
+#define reg_dca_gpr_dat_up_rec_0_pos 0
+#define reg_dca_gpr_dat_up_rec_0_len 8
+#define reg_dca_gpr_dat_up_rec_0_lsb 0
+#define xd_r_reg_dca_gpr_dat_up_rec_1   (*(volatile byte xdata *) 0xF764)
+#define    r_reg_dca_gpr_dat_up_rec_1   0xF764
+#define reg_dca_gpr_dat_up_rec_1_pos 0
+#define reg_dca_gpr_dat_up_rec_1_len 8
+#define reg_dca_gpr_dat_up_rec_1_lsb 0
+#define xd_r_reg_dca_gpr_dat_up_rec_2   (*(volatile byte xdata *) 0xF765)
+#define    r_reg_dca_gpr_dat_up_rec_2   0xF765
+#define reg_dca_gpr_dat_up_rec_2_pos 0
+#define reg_dca_gpr_dat_up_rec_2_len 8
+#define reg_dca_gpr_dat_up_rec_2_lsb 0
+#define xd_r_reg_dca_gpr_dat_up_rec_3   (*(volatile byte xdata *) 0xF766)
+#define    r_reg_dca_gpr_dat_up_rec_3   0xF766
+#define reg_dca_gpr_dat_up_rec_3_pos 0
+#define reg_dca_gpr_dat_up_rec_3_len 8
+#define reg_dca_gpr_dat_up_rec_3_lsb 0
+#define xd_r_reg_dca_gpr_dat_up_rec_4   (*(volatile byte xdata *) 0xF767)
+#define    r_reg_dca_gpr_dat_up_rec_4   0xF767
+#define reg_dca_gpr_dat_up_rec_4_pos 0
+#define reg_dca_gpr_dat_up_rec_4_len 8
+#define reg_dca_gpr_dat_up_rec_4_lsb 0
+#define xd_r_reg_dca_gpr_dat_up_rec_5   (*(volatile byte xdata *) 0xF768)
+#define    r_reg_dca_gpr_dat_up_rec_5   0xF768
+#define reg_dca_gpr_dat_up_rec_5_pos 0
+#define reg_dca_gpr_dat_up_rec_5_len 8
+#define reg_dca_gpr_dat_up_rec_5_lsb 0
+#define xd_r_reg_dca_over_wr_up_rec (*(volatile byte xdata *) 0xF769)
+#define    r_reg_dca_over_wr_up_rec 0xF769
+#define reg_dca_over_wr_up_rec_pos 0
+#define reg_dca_over_wr_up_rec_len 1
+#define reg_dca_over_wr_up_rec_lsb 0
+#define xd_p_reg_dca_int_up_rec (*(volatile byte xdata *) 0xF76A)
+#define    p_reg_dca_int_up_rec 0xF76A
+#define reg_dca_int_up_rec_pos 0
+#define reg_dca_int_up_rec_len 1
+#define reg_dca_int_up_rec_lsb 0
+#define xd_p_reg_dca_fw_read_yet_up (*(volatile byte xdata *) 0xF76B)
+#define    p_reg_dca_fw_read_yet_up 0xF76B
+#define reg_dca_fw_read_yet_up_pos 0
+#define reg_dca_fw_read_yet_up_len 1
+#define reg_dca_fw_read_yet_up_lsb 0
+#define xd_r_reg_dca_gpr_ctr_lo_rec (*(volatile byte xdata *) 0xF76C)
+#define    r_reg_dca_gpr_ctr_lo_rec 0xF76C
+#define reg_dca_gpr_ctr_lo_rec_pos 0
+#define reg_dca_gpr_ctr_lo_rec_len 8
+#define reg_dca_gpr_ctr_lo_rec_lsb 0
+#define xd_r_reg_dca_gpr_dat_lo_rec_0   (*(volatile byte xdata *) 0xF76D)
+#define    r_reg_dca_gpr_dat_lo_rec_0   0xF76D
+#define reg_dca_gpr_dat_lo_rec_0_pos 0
+#define reg_dca_gpr_dat_lo_rec_0_len 8
+#define reg_dca_gpr_dat_lo_rec_0_lsb 0
+#define xd_r_reg_dca_gpr_dat_lo_rec_1   (*(volatile byte xdata *) 0xF76E)
+#define    r_reg_dca_gpr_dat_lo_rec_1   0xF76E
+#define reg_dca_gpr_dat_lo_rec_1_pos 0
+#define reg_dca_gpr_dat_lo_rec_1_len 8
+#define reg_dca_gpr_dat_lo_rec_1_lsb 0
+#define xd_r_reg_dca_gpr_dat_lo_rec_2   (*(volatile byte xdata *) 0xF76F)
+#define    r_reg_dca_gpr_dat_lo_rec_2   0xF76F
+#define reg_dca_gpr_dat_lo_rec_2_pos 0
+#define reg_dca_gpr_dat_lo_rec_2_len 8
+#define reg_dca_gpr_dat_lo_rec_2_lsb 0
+#define xd_r_reg_dca_gpr_dat_lo_rec_3   (*(volatile byte xdata *) 0xF770)
+#define    r_reg_dca_gpr_dat_lo_rec_3   0xF770
+#define reg_dca_gpr_dat_lo_rec_3_pos 0
+#define reg_dca_gpr_dat_lo_rec_3_len 8
+#define reg_dca_gpr_dat_lo_rec_3_lsb 0
+#define xd_r_reg_dca_gpr_dat_lo_rec_4   (*(volatile byte xdata *) 0xF771)
+#define    r_reg_dca_gpr_dat_lo_rec_4   0xF771
+#define reg_dca_gpr_dat_lo_rec_4_pos 0
+#define reg_dca_gpr_dat_lo_rec_4_len 8
+#define reg_dca_gpr_dat_lo_rec_4_lsb 0
+#define xd_r_reg_dca_gpr_dat_lo_rec_5   (*(volatile byte xdata *) 0xF772)
+#define    r_reg_dca_gpr_dat_lo_rec_5   0xF772
+#define reg_dca_gpr_dat_lo_rec_5_pos 0
+#define reg_dca_gpr_dat_lo_rec_5_len 8
+#define reg_dca_gpr_dat_lo_rec_5_lsb 0
+#define xd_r_reg_dca_over_wr_lo_rec (*(volatile byte xdata *) 0xF773)
+#define    r_reg_dca_over_wr_lo_rec 0xF773
+#define reg_dca_over_wr_lo_rec_pos 0
+#define reg_dca_over_wr_lo_rec_len 1
+#define reg_dca_over_wr_lo_rec_lsb 0
+#define xd_p_reg_dca_int_lo_rec (*(volatile byte xdata *) 0xF774)
+#define    p_reg_dca_int_lo_rec 0xF774
+#define reg_dca_int_lo_rec_pos 0
+#define reg_dca_int_lo_rec_len 1
+#define reg_dca_int_lo_rec_lsb 0
+#define xd_p_reg_dca_fw_read_yet_lo (*(volatile byte xdata *) 0xF775)
+#define    p_reg_dca_fw_read_yet_lo 0xF775
+#define reg_dca_fw_read_yet_lo_pos 0
+#define reg_dca_fw_read_yet_lo_len 1
+#define reg_dca_fw_read_yet_lo_lsb 0
+#define xd_p_reg_dca_en (*(volatile byte xdata *) 0xF776)
+#define    p_reg_dca_en 0xF776
+#define reg_dca_en_pos 0
+#define reg_dca_en_len 1
+#define reg_dca_en_lsb 0
+#define xd_p_reg_dca_ulrdy_delay    (*(volatile byte xdata *) 0xF777)
+#define    p_reg_dca_ulrdy_delay    0xF777
+#define reg_dca_ulrdy_delay_pos 0
+#define reg_dca_ulrdy_delay_len 8
+#define reg_dca_ulrdy_delay_lsb 0
+#define xd_p_reg_dca_fpga_latch (*(volatile byte xdata *) 0xF778)
+#define    p_reg_dca_fpga_latch 0xF778
+#define reg_dca_fpga_latch_pos 0
+#define reg_dca_fpga_latch_len 8
+#define reg_dca_fpga_latch_lsb 0
+#define xd_p_reg_dca_vldld_err  (*(volatile byte xdata *) 0xF779)
+#define    p_reg_dca_vldld_err  0xF779
+#define reg_dca_vldld_err_pos 0
+#define reg_dca_vldld_err_len 1
+#define reg_dca_vldld_err_lsb 0
+#define xd_p_reg_dca_vldud_err  (*(volatile byte xdata *) 0xF77A)
+#define    p_reg_dca_vldud_err  0xF77A
+#define reg_dca_vldud_err_pos 0
+#define reg_dca_vldud_err_len 1
+#define reg_dca_vldud_err_lsb 0
+#define xd_p_reg_dca_modeu_err  (*(volatile byte xdata *) 0xF77B)
+#define    p_reg_dca_modeu_err  0xF77B
+#define reg_dca_modeu_err_pos 0
+#define reg_dca_modeu_err_len 1
+#define reg_dca_modeu_err_lsb 0
+#define xd_p_reg_dca_model_err  (*(volatile byte xdata *) 0xF77C)
+#define    p_reg_dca_model_err  0xF77C
+#define reg_dca_model_err_pos 0
+#define reg_dca_model_err_len 1
+#define reg_dca_model_err_lsb 0
+#define xd_p_reg_dca_interrupt  (*(volatile byte xdata *) 0xF77D)
+#define    p_reg_dca_interrupt  0xF77D
+#define reg_dca_interrupt_pos 0
+#define reg_dca_interrupt_len 1
+#define reg_dca_interrupt_lsb 0
+#define xd_p_reg_dca_auto_reset_en  (*(volatile byte xdata *) 0xF77E)
+#define    p_reg_dca_auto_reset_en  0xF77E
+#define reg_dca_auto_reset_en_pos 0
+#define reg_dca_auto_reset_en_len 1
+#define reg_dca_auto_reset_en_lsb 0
+#define xd_p_reg_qnt_valuew_7_0 (*(volatile byte xdata *) 0xF77F)
+#define    p_reg_qnt_valuew_7_0 0xF77F
+#define reg_qnt_valuew_7_0_pos 0
+#define reg_qnt_valuew_7_0_len 8
+#define reg_qnt_valuew_7_0_lsb 0
+#define xd_p_reg_qnt_valuew_10_8    (*(volatile byte xdata *) 0xF780)
+#define    p_reg_qnt_valuew_10_8    0xF780
+#define reg_qnt_valuew_10_8_pos 0
+#define reg_qnt_valuew_10_8_len 3
+#define reg_qnt_valuew_10_8_lsb 8
+#define xd_p_reg_qnt_nfvaluew_7_0   (*(volatile byte xdata *) 0xF781)
+#define    p_reg_qnt_nfvaluew_7_0   0xF781
+#define reg_qnt_nfvaluew_7_0_pos 0
+#define reg_qnt_nfvaluew_7_0_len 8
+#define reg_qnt_nfvaluew_7_0_lsb 0
+#define xd_p_reg_qnt_nfvaluew_10_8  (*(volatile byte xdata *) 0xF782)
+#define    p_reg_qnt_nfvaluew_10_8  0xF782
+#define reg_qnt_nfvaluew_10_8_pos 0
+#define reg_qnt_nfvaluew_10_8_len 3
+#define reg_qnt_nfvaluew_10_8_lsb 8
+#define xd_p_reg_qnt_flatness_thr_7_0   (*(volatile byte xdata *) 0xF783)
+#define    p_reg_qnt_flatness_thr_7_0   0xF783
+#define reg_qnt_flatness_thr_7_0_pos 0
+#define reg_qnt_flatness_thr_7_0_len 8
+#define reg_qnt_flatness_thr_7_0_lsb 0
+#define xd_p_reg_qnt_flatness_thr_8 (*(volatile byte xdata *) 0xF784)
+#define    p_reg_qnt_flatness_thr_8 0xF784
+#define reg_qnt_flatness_thr_8_pos 0
+#define reg_qnt_flatness_thr_8_len 1
+#define reg_qnt_flatness_thr_8_lsb 8
+#define xd_p_reg_llr_to_be_monitor  (*(volatile byte xdata *) 0xF785)
+#define    p_reg_llr_to_be_monitor  0xF785
+#define reg_llr_to_be_monitor_pos 0
+#define reg_llr_to_be_monitor_len 1
+#define reg_llr_to_be_monitor_lsb 0
+#define xd_p_reg_qnt_vbc_rdy    (*(volatile byte xdata *) 0xF786)
+#define    p_reg_qnt_vbc_rdy    0xF786
+#define reg_qnt_vbc_rdy_pos 0
+#define reg_qnt_vbc_rdy_len 1
+#define reg_qnt_vbc_rdy_lsb 0
+#define xd_p_reg_qnt_noncmb_vbc_rdy (*(volatile byte xdata *) 0xF787)
+#define    p_reg_qnt_noncmb_vbc_rdy 0xF787
+#define reg_qnt_noncmb_vbc_rdy_pos 0
+#define reg_qnt_noncmb_vbc_rdy_len 1
+#define reg_qnt_noncmb_vbc_rdy_lsb 0
+#define xd_p_reg_use_eh2_mean   (*(volatile byte xdata *) 0xF788)
+#define    p_reg_use_eh2_mean   0xF788
+#define reg_use_eh2_mean_pos 0
+#define reg_use_eh2_mean_len 1
+#define reg_use_eh2_mean_lsb 0
+#define xd_p_reg_qnt_vbc_ccid_mode  (*(volatile byte xdata *) 0xF789)
+#define    p_reg_qnt_vbc_ccid_mode  0xF789
+#define reg_qnt_vbc_ccid_mode_pos 0
+#define reg_qnt_vbc_ccid_mode_len 1
+#define reg_qnt_vbc_ccid_mode_lsb 0
+#define xd_p_reg_qnt_cci_bandsize   (*(volatile byte xdata *) 0xF78A)
+#define    p_reg_qnt_cci_bandsize   0xF78A
+#define reg_qnt_cci_bandsize_pos 0
+#define reg_qnt_cci_bandsize_len 4
+#define reg_qnt_cci_bandsize_lsb 0
+#define xd_p_reg_qnt_vbc_sframe_num (*(volatile byte xdata *) 0xF78B)
+#define    p_reg_qnt_vbc_sframe_num 0xF78B
+#define reg_qnt_vbc_sframe_num_pos 0
+#define reg_qnt_vbc_sframe_num_len 8
+#define reg_qnt_vbc_sframe_num_lsb 0
+#define xd_p_reg_sbx_gain_diff_7_0  (*(volatile byte xdata *) 0xF78C)
+#define    p_reg_sbx_gain_diff_7_0  0xF78C
+#define reg_sbx_gain_diff_7_0_pos 0
+#define reg_sbx_gain_diff_7_0_len 8
+#define reg_sbx_gain_diff_7_0_lsb 0
+#define xd_p_reg_sbx_gain_diff_8    (*(volatile byte xdata *) 0xF78D)
+#define    p_reg_sbx_gain_diff_8    0xF78D
+#define reg_sbx_gain_diff_8_pos 0
+#define reg_sbx_gain_diff_8_len 1
+#define reg_sbx_gain_diff_8_lsb 8
+#define xd_p_reg_sbx_gain_diff_rdy  (*(volatile byte xdata *) 0xF78E)
+#define    p_reg_sbx_gain_diff_rdy  0xF78E
+#define reg_sbx_gain_diff_rdy_pos 0
+#define reg_sbx_gain_diff_rdy_len 1
+#define reg_sbx_gain_diff_rdy_lsb 0
+#define xd_p_reg_sbx_noncmb_gain_diff_7_0   (*(volatile byte xdata *) 0xF78F)
+#define    p_reg_sbx_noncmb_gain_diff_7_0   0xF78F
+#define reg_sbx_noncmb_gain_diff_7_0_pos 0
+#define reg_sbx_noncmb_gain_diff_7_0_len 8
+#define reg_sbx_noncmb_gain_diff_7_0_lsb 0
+#define xd_p_reg_sbx_noncmb_gain_diff_8 (*(volatile byte xdata *) 0xF790)
+#define    p_reg_sbx_noncmb_gain_diff_8 0xF790
+#define reg_sbx_noncmb_gain_diff_8_pos 0
+#define reg_sbx_noncmb_gain_diff_8_len 1
+#define reg_sbx_noncmb_gain_diff_8_lsb 8
+#define xd_p_reg_sbx_noncmb_gain_diff_rdy   (*(volatile byte xdata *) 0xF791)
+#define    p_reg_sbx_noncmb_gain_diff_rdy   0xF791
+#define reg_sbx_noncmb_gain_diff_rdy_pos 0
+#define reg_sbx_noncmb_gain_diff_rdy_len 1
+#define reg_sbx_noncmb_gain_diff_rdy_lsb 0
+#define xd_r_reg_qnt_vbc_err_7_0    (*(volatile byte xdata *) 0xF792)
+#define    r_reg_qnt_vbc_err_7_0    0xF792
+#define reg_qnt_vbc_err_7_0_pos 0
+#define reg_qnt_vbc_err_7_0_len 8
+#define reg_qnt_vbc_err_7_0_lsb 0
+#define xd_r_reg_qnt_vbc_err_15_8   (*(volatile byte xdata *) 0xF793)
+#define    r_reg_qnt_vbc_err_15_8   0xF793
+#define reg_qnt_vbc_err_15_8_pos 0
+#define reg_qnt_vbc_err_15_8_len 8
+#define reg_qnt_vbc_err_15_8_lsb 8
+#define xd_r_reg_qnt_vbc_err_23_16  (*(volatile byte xdata *) 0xF794)
+#define    r_reg_qnt_vbc_err_23_16  0xF794
+#define reg_qnt_vbc_err_23_16_pos 0
+#define reg_qnt_vbc_err_23_16_len 8
+#define reg_qnt_vbc_err_23_16_lsb 16
+#define xd_r_reg_qnt_noncmb_vbc_err_7_0 (*(volatile byte xdata *) 0xF795)
+#define    r_reg_qnt_noncmb_vbc_err_7_0 0xF795
+#define reg_qnt_noncmb_vbc_err_7_0_pos 0
+#define reg_qnt_noncmb_vbc_err_7_0_len 8
+#define reg_qnt_noncmb_vbc_err_7_0_lsb 0
+#define xd_r_reg_qnt_noncmb_vbc_err_15_8    (*(volatile byte xdata *) 0xF796)
+#define    r_reg_qnt_noncmb_vbc_err_15_8    0xF796
+#define reg_qnt_noncmb_vbc_err_15_8_pos 0
+#define reg_qnt_noncmb_vbc_err_15_8_len 8
+#define reg_qnt_noncmb_vbc_err_15_8_lsb 8
+#define xd_r_reg_qnt_noncmb_vbc_err_23_16   (*(volatile byte xdata *) 0xF797)
+#define    r_reg_qnt_noncmb_vbc_err_23_16   0xF797
+#define reg_qnt_noncmb_vbc_err_23_16_pos 0
+#define reg_qnt_noncmb_vbc_err_23_16_len 8
+#define reg_qnt_noncmb_vbc_err_23_16_lsb 16
+#define xd_p_reg_sbx_signalquality_threshold    (*(volatile byte xdata *) 0xF798)
+#define    p_reg_sbx_signalquality_threshold    0xF798
+#define reg_sbx_signalquality_threshold_pos 0
+#define reg_sbx_signalquality_threshold_len 4
+#define reg_sbx_signalquality_threshold_lsb 0
+#define xd_r_reg_sbx_signalquality_ind  (*(volatile byte xdata *) 0xF799)
+#define    r_reg_sbx_signalquality_ind  0xF799
+#define reg_sbx_signalquality_ind_pos 0
+#define reg_sbx_signalquality_ind_len 1
+#define reg_sbx_signalquality_ind_lsb 0
+#define xd_p_reg_p_sbxqnt_th1   (*(volatile byte xdata *) 0xF79A)
+#define    p_reg_p_sbxqnt_th1   0xF79A
+#define reg_p_sbxqnt_th1_pos 0
+#define reg_p_sbxqnt_th1_len 8
+#define reg_p_sbxqnt_th1_lsb 0
+#define xd_p_reg_p_sbxqnt_th2   (*(volatile byte xdata *) 0xF79B)
+#define    p_reg_p_sbxqnt_th2   0xF79B
+#define reg_p_sbxqnt_th2_pos 0
+#define reg_p_sbxqnt_th2_len 8
+#define reg_p_sbxqnt_th2_lsb 0
+#define xd_p_reg_p_sbxqnt_th3   (*(volatile byte xdata *) 0xF79C)
+#define    p_reg_p_sbxqnt_th3   0xF79C
+#define reg_p_sbxqnt_th3_pos 0
+#define reg_p_sbxqnt_th3_len 8
+#define reg_p_sbxqnt_th3_lsb 0
+#define xd_p_reg_p_sbxqnt_th4   (*(volatile byte xdata *) 0xF79D)
+#define    p_reg_p_sbxqnt_th4   0xF79D
+#define reg_p_sbxqnt_th4_pos 0
+#define reg_p_sbxqnt_th4_len 8
+#define reg_p_sbxqnt_th4_lsb 0
+#define xd_p_reg_p_sbxqnt_th5   (*(volatile byte xdata *) 0xF79E)
+#define    p_reg_p_sbxqnt_th5   0xF79E
+#define reg_p_sbxqnt_th5_pos 0
+#define reg_p_sbxqnt_th5_len 8
+#define reg_p_sbxqnt_th5_lsb 0
+#define xd_p_reg_p_sbxqnt_th6   (*(volatile byte xdata *) 0xF79F)
+#define    p_reg_p_sbxqnt_th6   0xF79F
+#define reg_p_sbxqnt_th6_pos 0
+#define reg_p_sbxqnt_th6_len 8
+#define reg_p_sbxqnt_th6_lsb 0
+#define xd_p_reg_p_sbxqnt_th7   (*(volatile byte xdata *) 0xF800)
+#define    p_reg_p_sbxqnt_th7   0xF800
+#define reg_p_sbxqnt_th7_pos 0
+#define reg_p_sbxqnt_th7_len 8
+#define reg_p_sbxqnt_th7_lsb 0
+#define xd_p_reg_p_sbxqnt_th8   (*(volatile byte xdata *) 0xF801)
+#define    p_reg_p_sbxqnt_th8   0xF801
+#define reg_p_sbxqnt_th8_pos 0
+#define reg_p_sbxqnt_th8_len 8
+#define reg_p_sbxqnt_th8_lsb 0
+#define xd_p_reg_p_sbxqnt_th9   (*(volatile byte xdata *) 0xF802)
+#define    p_reg_p_sbxqnt_th9   0xF802
+#define reg_p_sbxqnt_th9_pos 0
+#define reg_p_sbxqnt_th9_len 8
+#define reg_p_sbxqnt_th9_lsb 0
+#define xd_p_reg_p_sbxqnt_th10  (*(volatile byte xdata *) 0xF803)
+#define    p_reg_p_sbxqnt_th10  0xF803
+#define reg_p_sbxqnt_th10_pos 0
+#define reg_p_sbxqnt_th10_len 8
+#define reg_p_sbxqnt_th10_lsb 0
+#define xd_p_reg_p_sbxqnt_th11  (*(volatile byte xdata *) 0xF804)
+#define    p_reg_p_sbxqnt_th11  0xF804
+#define reg_p_sbxqnt_th11_pos 0
+#define reg_p_sbxqnt_th11_len 8
+#define reg_p_sbxqnt_th11_lsb 0
+#define xd_p_reg_p_sbxqnt_th12  (*(volatile byte xdata *) 0xF805)
+#define    p_reg_p_sbxqnt_th12  0xF805
+#define reg_p_sbxqnt_th12_pos 0
+#define reg_p_sbxqnt_th12_len 8
+#define reg_p_sbxqnt_th12_lsb 0
+#define xd_p_reg_p_sbxqnt_th13_7_0  (*(volatile byte xdata *) 0xF806)
+#define    p_reg_p_sbxqnt_th13_7_0  0xF806
+#define reg_p_sbxqnt_th13_7_0_pos 0
+#define reg_p_sbxqnt_th13_7_0_len 8
+#define reg_p_sbxqnt_th13_7_0_lsb 0
+#define xd_p_reg_p_sbxqnt_th13_9_8  (*(volatile byte xdata *) 0xF807)
+#define    p_reg_p_sbxqnt_th13_9_8  0xF807
+#define reg_p_sbxqnt_th13_9_8_pos 0
+#define reg_p_sbxqnt_th13_9_8_len 2
+#define reg_p_sbxqnt_th13_9_8_lsb 8
+#define xd_p_reg_p_sbxqnt_th14_7_0  (*(volatile byte xdata *) 0xF808)
+#define    p_reg_p_sbxqnt_th14_7_0  0xF808
+#define reg_p_sbxqnt_th14_7_0_pos 0
+#define reg_p_sbxqnt_th14_7_0_len 8
+#define reg_p_sbxqnt_th14_7_0_lsb 0
+#define xd_p_reg_p_sbxqnt_th14_9_8  (*(volatile byte xdata *) 0xF809)
+#define    p_reg_p_sbxqnt_th14_9_8  0xF809
+#define reg_p_sbxqnt_th14_9_8_pos 0
+#define reg_p_sbxqnt_th14_9_8_len 2
+#define reg_p_sbxqnt_th14_9_8_lsb 8
+#define xd_p_reg_p_sbxqnt_th15_7_0  (*(volatile byte xdata *) 0xF80A)
+#define    p_reg_p_sbxqnt_th15_7_0  0xF80A
+#define reg_p_sbxqnt_th15_7_0_pos 0
+#define reg_p_sbxqnt_th15_7_0_len 8
+#define reg_p_sbxqnt_th15_7_0_lsb 0
+#define xd_p_reg_p_sbxqnt_th15_9_8  (*(volatile byte xdata *) 0xF80B)
+#define    p_reg_p_sbxqnt_th15_9_8  0xF80B
+#define reg_p_sbxqnt_th15_9_8_pos 0
+#define reg_p_sbxqnt_th15_9_8_len 2
+#define reg_p_sbxqnt_th15_9_8_lsb 8
+#define xd_p_reg_p_sbxqnt_vzh2_th0  (*(volatile byte xdata *) 0xF80C)
+#define    p_reg_p_sbxqnt_vzh2_th0  0xF80C
+#define reg_p_sbxqnt_vzh2_th0_pos 0
+#define reg_p_sbxqnt_vzh2_th0_len 8
+#define reg_p_sbxqnt_vzh2_th0_lsb 0
+#define xd_p_reg_p_sbxqnt_vzh2_th1  (*(volatile byte xdata *) 0xF80D)
+#define    p_reg_p_sbxqnt_vzh2_th1  0xF80D
+#define reg_p_sbxqnt_vzh2_th1_pos 0
+#define reg_p_sbxqnt_vzh2_th1_len 8
+#define reg_p_sbxqnt_vzh2_th1_lsb 0
+#define xd_p_reg_p_sbxqnt_vzh2_th2  (*(volatile byte xdata *) 0xF80E)
+#define    p_reg_p_sbxqnt_vzh2_th2  0xF80E
+#define reg_p_sbxqnt_vzh2_th2_pos 0
+#define reg_p_sbxqnt_vzh2_th2_len 8
+#define reg_p_sbxqnt_vzh2_th2_lsb 0
+#define xd_p_reg_p_qnt_w_comp1  (*(volatile byte xdata *) 0xF80F)
+#define    p_reg_p_qnt_w_comp1  0xF80F
+#define reg_p_qnt_w_comp1_pos 0
+#define reg_p_qnt_w_comp1_len 8
+#define reg_p_qnt_w_comp1_lsb 0
+#define xd_p_reg_p_qnt_w_comp2  (*(volatile byte xdata *) 0xF810)
+#define    p_reg_p_qnt_w_comp2  0xF810
+#define reg_p_qnt_w_comp2_pos 0
+#define reg_p_qnt_w_comp2_len 8
+#define reg_p_qnt_w_comp2_lsb 0
+#define xd_p_reg_p_qnt_w_comp3  (*(volatile byte xdata *) 0xF811)
+#define    p_reg_p_qnt_w_comp3  0xF811
+#define reg_p_qnt_w_comp3_pos 0
+#define reg_p_qnt_w_comp3_len 8
+#define reg_p_qnt_w_comp3_lsb 0
+#define xd_p_reg_p_vtb_in_0 (*(volatile byte xdata *) 0xF821)
+#define    p_reg_p_vtb_in_0 0xF821
+#define reg_p_vtb_in_0_pos 0
+#define reg_p_vtb_in_0_len 6
+#define reg_p_vtb_in_0_lsb 0
+#define xd_p_reg_p_vtb_in_1 (*(volatile byte xdata *) 0xF822)
+#define    p_reg_p_vtb_in_1 0xF822
+#define reg_p_vtb_in_1_pos 0
+#define reg_p_vtb_in_1_len 6
+#define reg_p_vtb_in_1_lsb 0
+#define xd_p_reg_p_vtb_in_2 (*(volatile byte xdata *) 0xF823)
+#define    p_reg_p_vtb_in_2 0xF823
+#define reg_p_vtb_in_2_pos 0
+#define reg_p_vtb_in_2_len 6
+#define reg_p_vtb_in_2_lsb 0
+#define xd_p_reg_p_vtb_in_3 (*(volatile byte xdata *) 0xF824)
+#define    p_reg_p_vtb_in_3 0xF824
+#define reg_p_vtb_in_3_pos 0
+#define reg_p_vtb_in_3_len 6
+#define reg_p_vtb_in_3_lsb 0
+#define xd_p_reg_p_vtb_in_4 (*(volatile byte xdata *) 0xF825)
+#define    p_reg_p_vtb_in_4 0xF825
+#define reg_p_vtb_in_4_pos 0
+#define reg_p_vtb_in_4_len 6
+#define reg_p_vtb_in_4_lsb 0
+#define xd_p_reg_p_vtb_in_5 (*(volatile byte xdata *) 0xF826)
+#define    p_reg_p_vtb_in_5 0xF826
+#define reg_p_vtb_in_5_pos 0
+#define reg_p_vtb_in_5_len 6
+#define reg_p_vtb_in_5_lsb 0
+#define xd_p_reg_p_vtb_in_6 (*(volatile byte xdata *) 0xF827)
+#define    p_reg_p_vtb_in_6 0xF827
+#define reg_p_vtb_in_6_pos 0
+#define reg_p_vtb_in_6_len 6
+#define reg_p_vtb_in_6_lsb 0
+#define xd_p_reg_p_vtb_in_7 (*(volatile byte xdata *) 0xF828)
+#define    p_reg_p_vtb_in_7 0xF828
+#define reg_p_vtb_in_7_pos 0
+#define reg_p_vtb_in_7_len 6
+#define reg_p_vtb_in_7_lsb 0
+#define xd_p_reg_p_vtb_in_8 (*(volatile byte xdata *) 0xF829)
+#define    p_reg_p_vtb_in_8 0xF829
+#define reg_p_vtb_in_8_pos 0
+#define reg_p_vtb_in_8_len 6
+#define reg_p_vtb_in_8_lsb 0
+#define xd_p_reg_p_vtb_in_9 (*(volatile byte xdata *) 0xF82A)
+#define    p_reg_p_vtb_in_9 0xF82A
+#define reg_p_vtb_in_9_pos 0
+#define reg_p_vtb_in_9_len 6
+#define reg_p_vtb_in_9_lsb 0
+#define xd_p_reg_p_vtb_in_10    (*(volatile byte xdata *) 0xF82B)
+#define    p_reg_p_vtb_in_10    0xF82B
+#define reg_p_vtb_in_10_pos 0
+#define reg_p_vtb_in_10_len 6
+#define reg_p_vtb_in_10_lsb 0
+#define xd_p_reg_p_vtb_in_11    (*(volatile byte xdata *) 0xF82C)
+#define    p_reg_p_vtb_in_11    0xF82C
+#define reg_p_vtb_in_11_pos 0
+#define reg_p_vtb_in_11_len 6
+#define reg_p_vtb_in_11_lsb 0
+#define xd_p_reg_p_vtb_in_12    (*(volatile byte xdata *) 0xF82D)
+#define    p_reg_p_vtb_in_12    0xF82D
+#define reg_p_vtb_in_12_pos 0
+#define reg_p_vtb_in_12_len 6
+#define reg_p_vtb_in_12_lsb 0
+#define xd_p_reg_p_vtb_in_13    (*(volatile byte xdata *) 0xF82E)
+#define    p_reg_p_vtb_in_13    0xF82E
+#define reg_p_vtb_in_13_pos 0
+#define reg_p_vtb_in_13_len 6
+#define reg_p_vtb_in_13_lsb 0
+#define xd_p_reg_p_vtb_in_14    (*(volatile byte xdata *) 0xF82F)
+#define    p_reg_p_vtb_in_14    0xF82F
+#define reg_p_vtb_in_14_pos 0
+#define reg_p_vtb_in_14_len 6
+#define reg_p_vtb_in_14_lsb 0
+#define xd_p_reg_p_vtb_in_15    (*(volatile byte xdata *) 0xF830)
+#define    p_reg_p_vtb_in_15    0xF830
+#define reg_p_vtb_in_15_pos 0
+#define reg_p_vtb_in_15_len 6
+#define reg_p_vtb_in_15_lsb 0
+#define xd_I2C_i2c_m_slave_addr (*(volatile byte xdata *) 0xF940)
+#define    I2C_i2c_m_slave_addr 0xF940
+#define i2c_m_slave_addr_pos 0
+#define i2c_m_slave_addr_len 8
+#define i2c_m_slave_addr_lsb 0
+#define xd_I2C_i2c_m_data1  (*(volatile byte xdata *) 0xF941)
+#define    I2C_i2c_m_data1  0xF941
+#define i2c_m_data1_pos 0
+#define i2c_m_data1_len 8
+#define i2c_m_data1_lsb 0
+#define xd_I2C_i2c_m_data2  (*(volatile byte xdata *) 0xF942)
+#define    I2C_i2c_m_data2  0xF942
+#define i2c_m_data2_pos 0
+#define i2c_m_data2_len 8
+#define i2c_m_data2_lsb 0
+#define xd_I2C_i2c_m_data3  (*(volatile byte xdata *) 0xF943)
+#define    I2C_i2c_m_data3  0xF943
+#define i2c_m_data3_pos 0
+#define i2c_m_data3_len 8
+#define i2c_m_data3_lsb 0
+#define xd_I2C_i2c_m_data4  (*(volatile byte xdata *) 0xF944)
+#define    I2C_i2c_m_data4  0xF944
+#define i2c_m_data4_pos 0
+#define i2c_m_data4_len 8
+#define i2c_m_data4_lsb 0
+#define xd_I2C_i2c_m_data5  (*(volatile byte xdata *) 0xF945)
+#define    I2C_i2c_m_data5  0xF945
+#define i2c_m_data5_pos 0
+#define i2c_m_data5_len 8
+#define i2c_m_data5_lsb 0
+#define xd_I2C_i2c_m_data6  (*(volatile byte xdata *) 0xF946)
+#define    I2C_i2c_m_data6  0xF946
+#define i2c_m_data6_pos 0
+#define i2c_m_data6_len 8
+#define i2c_m_data6_lsb 0
+#define xd_I2C_i2c_m_data7  (*(volatile byte xdata *) 0xF947)
+#define    I2C_i2c_m_data7  0xF947
+#define i2c_m_data7_pos 0
+#define i2c_m_data7_len 8
+#define i2c_m_data7_lsb 0
+#define xd_I2C_i2c_m_data8  (*(volatile byte xdata *) 0xF948)
+#define    I2C_i2c_m_data8  0xF948
+#define i2c_m_data8_pos 0
+#define i2c_m_data8_len 8
+#define i2c_m_data8_lsb 0
+#define xd_I2C_i2c_m_data9  (*(volatile byte xdata *) 0xF949)
+#define    I2C_i2c_m_data9  0xF949
+#define i2c_m_data9_pos 0
+#define i2c_m_data9_len 8
+#define i2c_m_data9_lsb 0
+#define xd_I2C_i2c_m_data10 (*(volatile byte xdata *) 0xF94A)
+#define    I2C_i2c_m_data10 0xF94A
+#define i2c_m_data10_pos 0
+#define i2c_m_data10_len 8
+#define i2c_m_data10_lsb 0
+#define xd_I2C_i2c_m_data11 (*(volatile byte xdata *) 0xF94B)
+#define    I2C_i2c_m_data11 0xF94B
+#define i2c_m_data11_pos 0
+#define i2c_m_data11_len 8
+#define i2c_m_data11_lsb 0
+#define xd_I2C_i2c_m_data12 (*(volatile byte xdata *) 0xF94C)
+#define    I2C_i2c_m_data12 0xF94C
+#define i2c_m_data12_pos 0
+#define i2c_m_data12_len 8
+#define i2c_m_data12_lsb 0
+#define xd_I2C_i2c_m_data13 (*(volatile byte xdata *) 0xF94D)
+#define    I2C_i2c_m_data13 0xF94D
+#define i2c_m_data13_pos 0
+#define i2c_m_data13_len 8
+#define i2c_m_data13_lsb 0
+#define xd_I2C_i2c_m_data14 (*(volatile byte xdata *) 0xF94E)
+#define    I2C_i2c_m_data14 0xF94E
+#define i2c_m_data14_pos 0
+#define i2c_m_data14_len 8
+#define i2c_m_data14_lsb 0
+#define xd_I2C_i2c_m_data15 (*(volatile byte xdata *) 0xF94F)
+#define    I2C_i2c_m_data15 0xF94F
+#define i2c_m_data15_pos 0
+#define i2c_m_data15_len 8
+#define i2c_m_data15_lsb 0
+#define xd_I2C_i2c_m_data16 (*(volatile byte xdata *) 0xF950)
+#define    I2C_i2c_m_data16 0xF950
+#define i2c_m_data16_pos 0
+#define i2c_m_data16_len 8
+#define i2c_m_data16_lsb 0
+#define xd_I2C_i2c_m_data17 (*(volatile byte xdata *) 0xF951)
+#define    I2C_i2c_m_data17 0xF951
+#define i2c_m_data17_pos 0
+#define i2c_m_data17_len 8
+#define i2c_m_data17_lsb 0
+#define xd_I2C_i2c_m_data18 (*(volatile byte xdata *) 0xF952)
+#define    I2C_i2c_m_data18 0xF952
+#define i2c_m_data18_pos 0
+#define i2c_m_data18_len 8
+#define i2c_m_data18_lsb 0
+#define xd_I2C_i2c_m_data19 (*(volatile byte xdata *) 0xF953)
+#define    I2C_i2c_m_data19 0xF953
+#define i2c_m_data19_pos 0
+#define i2c_m_data19_len 8
+#define i2c_m_data19_lsb 0
+#define xd_I2C_i2c_m_cmd_rw (*(volatile byte xdata *) 0xF954)
+#define    I2C_i2c_m_cmd_rw 0xF954
+#define i2c_m_cmd_rw_pos 0
+#define i2c_m_cmd_rw_len 1
+#define i2c_m_cmd_rw_lsb 0
+#define xd_I2C_i2c_m_cmd_rwlen  (*(volatile byte xdata *) 0xF954)
+#define    I2C_i2c_m_cmd_rwlen  0xF954
+#define i2c_m_cmd_rwlen_pos 3
+#define i2c_m_cmd_rwlen_len 4
+#define i2c_m_cmd_rwlen_lsb 0
+#define xd_I2C_i2c_m_status_cmd_exe (*(volatile byte xdata *) 0xF955)
+#define    I2C_i2c_m_status_cmd_exe 0xF955
+#define i2c_m_status_cmd_exe_pos 0
+#define i2c_m_status_cmd_exe_len 1
+#define i2c_m_status_cmd_exe_lsb 0
+#define xd_I2C_i2c_m_status_wdat_done   (*(volatile byte xdata *) 0xF955)
+#define    I2C_i2c_m_status_wdat_done   0xF955
+#define i2c_m_status_wdat_done_pos 1
+#define i2c_m_status_wdat_done_len 1
+#define i2c_m_status_wdat_done_lsb 0
+#define xd_I2C_i2c_m_status_wdat_fail   (*(volatile byte xdata *) 0xF955)
+#define    I2C_i2c_m_status_wdat_fail   0xF955
+#define i2c_m_status_wdat_fail_pos 2
+#define i2c_m_status_wdat_fail_len 1
+#define i2c_m_status_wdat_fail_lsb 0
+#define xd_I2C_i2c_m_status_rdat_rdy    (*(volatile byte xdata *) 0xF955)
+#define    I2C_i2c_m_status_rdat_rdy    0xF955
+#define i2c_m_status_rdat_rdy_pos 3
+#define i2c_m_status_rdat_rdy_len 1
+#define i2c_m_status_rdat_rdy_lsb 0
+#define xd_I2C_i2c_m_period (*(volatile byte xdata *) 0xF956)
+#define    I2C_i2c_m_period 0xF956
+#define i2c_m_period_pos 0
+#define i2c_m_period_len 8
+#define i2c_m_period_lsb 0
+#define xd_I2C_i2c_m_reg_msb_lsb    (*(volatile byte xdata *) 0xF957)
+#define    I2C_i2c_m_reg_msb_lsb    0xF957
+#define i2c_m_reg_msb_lsb_pos 0
+#define i2c_m_reg_msb_lsb_len 1
+#define i2c_m_reg_msb_lsb_lsb 0
+#define xd_I2C_reg_ofdm_rst (*(volatile byte xdata *) 0xF957)
+#define    I2C_reg_ofdm_rst 0xF957
+#define reg_ofdm_rst_pos 1
+#define reg_ofdm_rst_len 1
+#define reg_ofdm_rst_lsb 0
+#define xd_I2C_reg_sample_period_on_tuner   (*(volatile byte xdata *) 0xF957)
+#define    I2C_reg_sample_period_on_tuner   0xF957
+#define reg_sample_period_on_tuner_pos 2
+#define reg_sample_period_on_tuner_len 1
+#define reg_sample_period_on_tuner_lsb 0
+#define xd_I2C_reg_sel_tuner    (*(volatile byte xdata *) 0xF957)
+#define    I2C_reg_sel_tuner    0xF957
+#define reg_sel_tuner_pos 3
+#define reg_sel_tuner_len 1
+#define reg_sel_tuner_lsb 0
+#define xd_I2C_reg_ofdm_rst_en  (*(volatile byte xdata *) 0xF957)
+#define    I2C_reg_ofdm_rst_en  0xF957
+#define reg_ofdm_rst_en_pos 4
+#define reg_ofdm_rst_en_len 1
+#define reg_ofdm_rst_en_lsb 0
+#define xd_p_mp2if_psb_overflow (*(volatile byte xdata *) 0xF980)
+#define    p_mp2if_psb_overflow 0xF980
+#define mp2if_psb_overflow_pos 0
+#define mp2if_psb_overflow_len 1
+#define mp2if_psb_overflow_lsb 0
+#define xd_p_mp2if_no_modify_tei_bit    (*(volatile byte xdata *) 0xF981)
+#define    p_mp2if_no_modify_tei_bit    0xF981
+#define mp2if_no_modify_tei_bit_pos 0
+#define mp2if_no_modify_tei_bit_len 1
+#define mp2if_no_modify_tei_bit_lsb 0
+#define xd_p_mp2if_keep_sf_sync_byte    (*(volatile byte xdata *) 0xF982)
+#define    p_mp2if_keep_sf_sync_byte    0xF982
+#define mp2if_keep_sf_sync_byte_pos 0
+#define mp2if_keep_sf_sync_byte_len 1
+#define mp2if_keep_sf_sync_byte_lsb 0
+#define xd_p_mp2if_data_access_disable  (*(volatile byte xdata *) 0xF983)
+#define    p_mp2if_data_access_disable  0xF983
+#define mp2if_data_access_disable_pos 0
+#define mp2if_data_access_disable_len 1
+#define mp2if_data_access_disable_lsb 0
+#define xd_p_mp2if_mpeg_ser_do7 (*(volatile byte xdata *) 0xF984)
+#define    p_mp2if_mpeg_ser_do7 0xF984
+#define mp2if_mpeg_ser_do7_pos 0
+#define mp2if_mpeg_ser_do7_len 1
+#define mp2if_mpeg_ser_do7_lsb 0
+#define xd_p_mp2if_mpeg_ser_mode    (*(volatile byte xdata *) 0xF985)
+#define    p_mp2if_mpeg_ser_mode    0xF985
+#define mp2if_mpeg_ser_mode_pos 0
+#define mp2if_mpeg_ser_mode_len 1
+#define mp2if_mpeg_ser_mode_lsb 0
+#define xd_p_mp2if_mpeg_par_mode    (*(volatile byte xdata *) 0xF986)
+#define    p_mp2if_mpeg_par_mode    0xF986
+#define mp2if_mpeg_par_mode_pos 0
+#define mp2if_mpeg_par_mode_len 1
+#define mp2if_mpeg_par_mode_lsb 0
+#define xd_r_mp2if_psb_empty    (*(volatile byte xdata *) 0xF987)
+#define    r_mp2if_psb_empty    0xF987
+#define mp2if_psb_empty_pos 0
+#define mp2if_psb_empty_len 1
+#define mp2if_psb_empty_lsb 0
+#define xd_r_mp2if_ts_not_188   (*(volatile byte xdata *) 0xF988)
+#define    r_mp2if_ts_not_188   0xF988
+#define mp2if_ts_not_188_pos 0
+#define mp2if_ts_not_188_len 1
+#define mp2if_ts_not_188_lsb 0
+#define xd_p_mp2if_mssync_len   (*(volatile byte xdata *) 0xF989)
+#define    p_mp2if_mssync_len   0xF989
+#define mp2if_mssync_len_pos 0
+#define mp2if_mssync_len_len 1
+#define mp2if_mssync_len_lsb 0
+#define xd_p_mp2if_msdo_msb (*(volatile byte xdata *) 0xF98A)
+#define    p_mp2if_msdo_msb 0xF98A
+#define mp2if_msdo_msb_pos 0
+#define mp2if_msdo_msb_len 1
+#define mp2if_msdo_msb_lsb 0
+#define xd_p_mp2if_mpeg_clk_gated   (*(volatile byte xdata *) 0xF98B)
+#define    p_mp2if_mpeg_clk_gated   0xF98B
+#define mp2if_mpeg_clk_gated_pos 0
+#define mp2if_mpeg_clk_gated_len 1
+#define mp2if_mpeg_clk_gated_lsb 0
+#define xd_p_mp2if_mpeg_err_pol (*(volatile byte xdata *) 0xF98C)
+#define    p_mp2if_mpeg_err_pol 0xF98C
+#define mp2if_mpeg_err_pol_pos 0
+#define mp2if_mpeg_err_pol_len 1
+#define mp2if_mpeg_err_pol_lsb 0
+#define xd_p_mp2if_mpeg_sync_pol    (*(volatile byte xdata *) 0xF98D)
+#define    p_mp2if_mpeg_sync_pol    0xF98D
+#define mp2if_mpeg_sync_pol_pos 0
+#define mp2if_mpeg_sync_pol_len 1
+#define mp2if_mpeg_sync_pol_lsb 0
+#define xd_p_mp2if_mpeg_vld_pol (*(volatile byte xdata *) 0xF98E)
+#define    p_mp2if_mpeg_vld_pol 0xF98E
+#define mp2if_mpeg_vld_pol_pos 0
+#define mp2if_mpeg_vld_pol_len 1
+#define mp2if_mpeg_vld_pol_lsb 0
+#define xd_p_mp2if_mpeg_clk_pol (*(volatile byte xdata *) 0xF98F)
+#define    p_mp2if_mpeg_clk_pol 0xF98F
+#define mp2if_mpeg_clk_pol_pos 0
+#define mp2if_mpeg_clk_pol_len 1
+#define mp2if_mpeg_clk_pol_lsb 0
+#define xd_p_reg_mpeg_full_speed    (*(volatile byte xdata *) 0xF990)
+#define    p_reg_mpeg_full_speed    0xF990
+#define reg_mpeg_full_speed_pos 0
+#define reg_mpeg_full_speed_len 1
+#define reg_mpeg_full_speed_lsb 0
+#define xd_p_mp2if_pid_complement   (*(volatile byte xdata *) 0xF991)
+#define    p_mp2if_pid_complement   0xF991
+#define mp2if_pid_complement_pos 0
+#define mp2if_pid_complement_len 1
+#define mp2if_pid_complement_lsb 0
+#define xd_p_mp2if_pid_rst  (*(volatile byte xdata *) 0xF992)
+#define    p_mp2if_pid_rst  0xF992
+#define mp2if_pid_rst_pos 0
+#define mp2if_pid_rst_len 1
+#define mp2if_pid_rst_lsb 0
+#define xd_p_mp2if_pid_en   (*(volatile byte xdata *) 0xF993)
+#define    p_mp2if_pid_en   0xF993
+#define mp2if_pid_en_pos 0
+#define mp2if_pid_en_len 1
+#define mp2if_pid_en_lsb 0
+#define xd_p_mp2if_pid_index_en (*(volatile byte xdata *) 0xF994)
+#define    p_mp2if_pid_index_en 0xF994
+#define mp2if_pid_index_en_pos 0
+#define mp2if_pid_index_en_len 1
+#define mp2if_pid_index_en_lsb 0
+#define xd_p_mp2if_pid_index    (*(volatile byte xdata *) 0xF995)
+#define    p_mp2if_pid_index    0xF995
+#define mp2if_pid_index_pos 0
+#define mp2if_pid_index_len 5
+#define mp2if_pid_index_lsb 0
+#define xd_p_mp2if_pid_dat_l    (*(volatile byte xdata *) 0xF996)
+#define    p_mp2if_pid_dat_l    0xF996
+#define mp2if_pid_dat_l_pos 0
+#define mp2if_pid_dat_l_len 8
+#define mp2if_pid_dat_l_lsb 0
+#define xd_p_mp2if_pid_dat_h    (*(volatile byte xdata *) 0xF997)
+#define    p_mp2if_pid_dat_h    0xF997
+#define mp2if_pid_dat_h_pos 0
+#define mp2if_pid_dat_h_len 5
+#define mp2if_pid_dat_h_lsb 0
+#define xd_p_reg_latch_clk  (*(volatile byte xdata *) 0xF998)
+#define    p_reg_latch_clk  0xF998
+#define reg_latch_clk_pos 0
+#define reg_latch_clk_len 1
+#define reg_latch_clk_lsb 0
+#define xd_r_mp2if_sync_byte_locked (*(volatile byte xdata *) 0xF999)
+#define    r_mp2if_sync_byte_locked 0xF999
+#define mp2if_sync_byte_locked_pos 0
+#define mp2if_sync_byte_locked_len 1
+#define mp2if_sync_byte_locked_lsb 0
+#define xd_p_mp2if_ignore_sync_byte (*(volatile byte xdata *) 0xF99A)
+#define    p_mp2if_ignore_sync_byte 0xF99A
+#define mp2if_ignore_sync_byte_pos 0
+#define mp2if_ignore_sync_byte_len 1
+#define mp2if_ignore_sync_byte_lsb 0
+#define xd_p_reg_mp2if_clk_en   (*(volatile byte xdata *) 0xF99B)
+#define    p_reg_mp2if_clk_en   0xF99B
+#define reg_mp2if_clk_en_pos 0
+#define reg_mp2if_clk_en_len 1
+#define reg_mp2if_clk_en_lsb 0
+#define xd_p_reg_mpeg_vld_tgl   (*(volatile byte xdata *) 0xF99C)
+#define    p_reg_mpeg_vld_tgl   0xF99C
+#define reg_mpeg_vld_tgl_pos 0
+#define reg_mpeg_vld_tgl_len 1
+#define reg_mpeg_vld_tgl_lsb 0
+#define xd_p_reg_mp2_sw_rst (*(volatile byte xdata *) 0xF99D)
+#define    p_reg_mp2_sw_rst 0xF99D
+#define reg_mp2_sw_rst_pos 0
+#define reg_mp2_sw_rst_len 1
+#define reg_mp2_sw_rst_lsb 0
+#define xd_p_mp2if_psb_en   (*(volatile byte xdata *) 0xF99E)
+#define    p_mp2if_psb_en   0xF99E
+#define mp2if_psb_en_pos 0
+#define mp2if_psb_en_len 1
+#define mp2if_psb_en_lsb 0
+#define xd_r_mp2if_usb20_mode   (*(volatile byte xdata *) 0xF99F)
+#define    r_mp2if_usb20_mode   0xF99F
+#define mp2if_usb20_mode_pos 0
+#define mp2if_usb20_mode_len 1
+#define mp2if_usb20_mode_lsb 0
+#define xd_r_mp2if_strap_usb20_mode (*(volatile byte xdata *) 0xF9A0)
+#define    r_mp2if_strap_usb20_mode 0xF9A0
+#define mp2if_strap_usb20_mode_pos 0
+#define mp2if_strap_usb20_mode_len 1
+#define mp2if_strap_usb20_mode_lsb 0
+#define xd_r_mp2if_lost_pkt_cnt_l   (*(volatile byte xdata *) 0xF9A1)
+#define    r_mp2if_lost_pkt_cnt_l   0xF9A1
+#define mp2if_lost_pkt_cnt_l_pos 0
+#define mp2if_lost_pkt_cnt_l_len 8
+#define mp2if_lost_pkt_cnt_l_lsb 0
+#define xd_r_mp2if_lost_pkt_cnt_h   (*(volatile byte xdata *) 0xF9A2)
+#define    r_mp2if_lost_pkt_cnt_h   0xF9A2
+#define mp2if_lost_pkt_cnt_h_pos 0
+#define mp2if_lost_pkt_cnt_h_len 8
+#define mp2if_lost_pkt_cnt_h_lsb 0
+#define xd_p_reg_mp2if2_en  (*(volatile byte xdata *) 0xF9A3)
+#define    p_reg_mp2if2_en  0xF9A3
+#define reg_mp2if2_en_pos 0
+#define reg_mp2if2_en_len 1
+#define reg_mp2if2_en_lsb 0
+#define xd_p_reg_mp2if2_sw_rst  (*(volatile byte xdata *) 0xF9A4)
+#define    p_reg_mp2if2_sw_rst  0xF9A4
+#define reg_mp2if2_sw_rst_pos 0
+#define reg_mp2if2_sw_rst_len 1
+#define reg_mp2if2_sw_rst_lsb 0
+#define xd_p_reg_mp2if2_half_psb    (*(volatile byte xdata *) 0xF9A5)
+#define    p_reg_mp2if2_half_psb    0xF9A5
+#define reg_mp2if2_half_psb_pos 0
+#define reg_mp2if2_half_psb_len 1
+#define reg_mp2if2_half_psb_lsb 0
+#define xd_p_reg_ts_byte_endian (*(volatile byte xdata *) 0xF9A6)
+#define    p_reg_ts_byte_endian 0xF9A6
+#define reg_ts_byte_endian_pos 0
+#define reg_ts_byte_endian_len 1
+#define reg_ts_byte_endian_lsb 0
+#define xd_p_reg_mp2_dioif  (*(volatile byte xdata *) 0xF9A7)
+#define    p_reg_mp2_dioif  0xF9A7
+#define reg_mp2_dioif_pos 0
+#define reg_mp2_dioif_len 1
+#define reg_mp2_dioif_lsb 0
+#define xd_p_reg_mp2_dioif_fast (*(volatile byte xdata *) 0xF9A8)
+#define    p_reg_mp2_dioif_fast 0xF9A8
+#define reg_mp2_dioif_fast_pos 0
+#define reg_mp2_dioif_fast_len 1
+#define reg_mp2_dioif_fast_lsb 0
+#define xd_p_reg_tpsd_bw_mp2if  (*(volatile byte xdata *) 0xF9A9)
+#define    p_reg_tpsd_bw_mp2if  0xF9A9
+#define reg_tpsd_bw_mp2if_pos 0
+#define reg_tpsd_bw_mp2if_len 2
+#define reg_tpsd_bw_mp2if_lsb 0
+#define xd_p_reg_tpsd_gi_mp2if  (*(volatile byte xdata *) 0xF9AA)
+#define    p_reg_tpsd_gi_mp2if  0xF9AA
+#define reg_tpsd_gi_mp2if_pos 0
+#define reg_tpsd_gi_mp2if_len 2
+#define reg_tpsd_gi_mp2if_lsb 0
+#define xd_p_reg_tpsd_cr_mp2if  (*(volatile byte xdata *) 0xF9AB)
+#define    p_reg_tpsd_cr_mp2if  0xF9AB
+#define reg_tpsd_cr_mp2if_pos 0
+#define reg_tpsd_cr_mp2if_len 3
+#define reg_tpsd_cr_mp2if_lsb 0
+#define xd_p_reg_tpsd_cons_mp2if    (*(volatile byte xdata *) 0xF9AC)
+#define    p_reg_tpsd_cons_mp2if    0xF9AC
+#define reg_tpsd_cons_mp2if_pos 0
+#define reg_tpsd_cons_mp2if_len 2
+#define reg_tpsd_cons_mp2if_lsb 0
+#define xd_p_reg_fw_table_en    (*(volatile byte xdata *) 0xF9AD)
+#define    p_reg_fw_table_en    0xF9AD
+#define reg_fw_table_en_pos 0
+#define reg_fw_table_en_len 1
+#define reg_fw_table_en_lsb 0
+#define xd_p_reg_p_aud_pk_gen_aud_pk_size   (*(volatile byte xdata *) 0xF9AD)
+#define    p_reg_p_aud_pk_gen_aud_pk_size   0xF9AD
+#define reg_p_aud_pk_gen_aud_pk_size_pos 1
+#define reg_p_aud_pk_gen_aud_pk_size_len 6
+#define reg_p_aud_pk_gen_aud_pk_size_lsb 0
+#define xd_p_mp2if_psb_num_blk  (*(volatile byte xdata *) 0xF9AE)
+#define    p_mp2if_psb_num_blk  0xF9AE
+#define mp2if_psb_num_blk_pos 0
+#define mp2if_psb_num_blk_len 6
+#define mp2if_psb_num_blk_lsb 0
+#define xd_p_reg_fec_fake   (*(volatile byte xdata *) 0xF9AF)
+#define    p_reg_fec_fake   0xF9AF
+#define reg_fec_fake_pos 0
+#define reg_fec_fake_len 1
+#define reg_fec_fake_lsb 0
+#define xd_p_reg_p_ccir_atv_en  (*(volatile byte xdata *) 0xF9AF)
+#define    p_reg_p_ccir_atv_en  0xF9AF
+#define reg_p_ccir_atv_en_pos 1
+#define reg_p_ccir_atv_en_len 1
+#define reg_p_ccir_atv_en_lsb 0
+#define xd_p_reg_video_stop_n   (*(volatile byte xdata *) 0xF9AF)
+#define    p_reg_video_stop_n   0xF9AF
+#define reg_video_stop_n_pos 2
+#define reg_video_stop_n_len 1
+#define reg_video_stop_n_lsb 0
+#define xd_p_reg_audio_stop_n   (*(volatile byte xdata *) 0xF9AF)
+#define    p_reg_audio_stop_n   0xF9AF
+#define reg_audio_stop_n_pos 3
+#define reg_audio_stop_n_len 1
+#define reg_audio_stop_n_lsb 0
+#define xd_p_mp2if_i2smode  (*(volatile byte xdata *) 0xF9AF)
+#define    p_mp2if_i2smode  0xF9AF
+#define mp2if_i2smode_pos 4
+#define mp2if_i2smode_len 2
+#define mp2if_i2smode_lsb 0
+#define xd_p_mp2if_word_size    (*(volatile byte xdata *) 0xF9AF)
+#define    p_mp2if_word_size    0xF9AF
+#define mp2if_word_size_pos 6
+#define mp2if_word_size_len 2
+#define mp2if_word_size_lsb 0
+#define xd_p_reg_packet_gap (*(volatile byte xdata *) 0xF9B0)
+#define    p_reg_packet_gap 0xF9B0
+#define reg_packet_gap_pos 0
+#define reg_packet_gap_len 8
+#define reg_packet_gap_lsb 0
+#define xd_p_reg_ts_dat_inv (*(volatile byte xdata *) 0xF9B2)
+#define    p_reg_ts_dat_inv 0xF9B2
+#define reg_ts_dat_inv_pos 0
+#define reg_ts_dat_inv_len 1
+#define reg_ts_dat_inv_lsb 0
+#define xd_p_reg_ts_lsb_1st (*(volatile byte xdata *) 0xF9B3)
+#define    p_reg_ts_lsb_1st 0xF9B3
+#define reg_ts_lsb_1st_pos 0
+#define reg_ts_lsb_1st_len 1
+#define reg_ts_lsb_1st_lsb 0
+#define xd_p_reg_ts_capt_bg_sel (*(volatile byte xdata *) 0xF9B4)
+#define    p_reg_ts_capt_bg_sel 0xF9B4
+#define reg_ts_capt_bg_sel_pos 0
+#define reg_ts_capt_bg_sel_len 1
+#define reg_ts_capt_bg_sel_lsb 0
+#define xd_p_reg_mp2if_stop_en  (*(volatile byte xdata *) 0xF9B5)
+#define    p_reg_mp2if_stop_en  0xF9B5
+#define reg_mp2if_stop_en_pos 0
+#define reg_mp2if_stop_en_len 1
+#define reg_mp2if_stop_en_lsb 0
+#define xd_p_reg_mp2if2_pes_base    (*(volatile byte xdata *) 0xF9B6)
+#define    p_reg_mp2if2_pes_base    0xF9B6
+#define reg_mp2if2_pes_base_pos 0
+#define reg_mp2if2_pes_base_len 1
+#define reg_mp2if2_pes_base_lsb 0
+#define xd_p_reg_ts_sync_inv    (*(volatile byte xdata *) 0xF9B7)
+#define    p_reg_ts_sync_inv    0xF9B7
+#define reg_ts_sync_inv_pos 0
+#define reg_ts_sync_inv_len 1
+#define reg_ts_sync_inv_lsb 0
+#define xd_p_reg_ts_vld_inv (*(volatile byte xdata *) 0xF9B8)
+#define    p_reg_ts_vld_inv 0xF9B8
+#define reg_ts_vld_inv_pos 0
+#define reg_ts_vld_inv_len 1
+#define reg_ts_vld_inv_lsb 0
+#define xd_p_reg_sys_buf_overflow   (*(volatile byte xdata *) 0xF9B9)
+#define    p_reg_sys_buf_overflow   0xF9B9
+#define reg_sys_buf_overflow_pos 0
+#define reg_sys_buf_overflow_len 1
+#define reg_sys_buf_overflow_lsb 0
+#define xd_p_reg_top_dummy0 (*(volatile byte xdata *) 0xF9BB)
+#define    p_reg_top_dummy0 0xF9BB
+#define reg_top_dummy0_pos 0
+#define reg_top_dummy0_len 8
+#define reg_top_dummy0_lsb 0
+#define xd_p_reg_top_dummy1 (*(volatile byte xdata *) 0xF9BC)
+#define    p_reg_top_dummy1 0xF9BC
+#define reg_top_dummy1_pos 0
+#define reg_top_dummy1_len 8
+#define reg_top_dummy1_lsb 0
+#define xd_p_reg_top_dummy2 (*(volatile byte xdata *) 0xF9BD)
+#define    p_reg_top_dummy2 0xF9BD
+#define reg_top_dummy2_pos 0
+#define reg_top_dummy2_len 8
+#define reg_top_dummy2_lsb 0
+#define xd_p_reg_top_dummy3 (*(volatile byte xdata *) 0xF9BE)
+#define    p_reg_top_dummy3 0xF9BE
+#define reg_top_dummy3_pos 0
+#define reg_top_dummy3_len 8
+#define reg_top_dummy3_lsb 0
+#define xd_p_reg_top_dummy4 (*(volatile byte xdata *) 0xF9BF)
+#define    p_reg_top_dummy4 0xF9BF
+#define reg_top_dummy4_pos 0
+#define reg_top_dummy4_len 8
+#define reg_top_dummy4_lsb 0
+#define xd_p_reg_top_dummy5 (*(volatile byte xdata *) 0xF9C0)
+#define    p_reg_top_dummy5 0xF9C0
+#define reg_top_dummy5_pos 0
+#define reg_top_dummy5_len 8
+#define reg_top_dummy5_lsb 0
+#define xd_p_reg_top_dummy6 (*(volatile byte xdata *) 0xF9C1)
+#define    p_reg_top_dummy6 0xF9C1
+#define reg_top_dummy6_pos 0
+#define reg_top_dummy6_len 8
+#define reg_top_dummy6_lsb 0
+#define xd_p_reg_top_dummy7 (*(volatile byte xdata *) 0xF9C2)
+#define    p_reg_top_dummy7 0xF9C2
+#define reg_top_dummy7_pos 0
+#define reg_top_dummy7_len 8
+#define reg_top_dummy7_lsb 0
+#define xd_p_reg_top_dummy8 (*(volatile byte xdata *) 0xF9C3)
+#define    p_reg_top_dummy8 0xF9C3
+#define reg_top_dummy8_pos 0
+#define reg_top_dummy8_len 8
+#define reg_top_dummy8_lsb 0
+#define xd_p_reg_top_dummy9 (*(volatile byte xdata *) 0xF9C4)
+#define    p_reg_top_dummy9 0xF9C4
+#define reg_top_dummy9_pos 0
+#define reg_top_dummy9_len 8
+#define reg_top_dummy9_lsb 0
+#define xd_p_reg_top_dummyA (*(volatile byte xdata *) 0xF9C5)
+#define    p_reg_top_dummyA 0xF9C5
+#define reg_top_dummyA_pos 0
+#define reg_top_dummyA_len 8
+#define reg_top_dummyA_lsb 0
+#define xd_p_reg_top_dummyB (*(volatile byte xdata *) 0xF9C6)
+#define    p_reg_top_dummyB 0xF9C6
+#define reg_top_dummyB_pos 0
+#define reg_top_dummyB_len 8
+#define reg_top_dummyB_lsb 0
+#define xd_p_reg_top_dummyC (*(volatile byte xdata *) 0xF9C7)
+#define    p_reg_top_dummyC 0xF9C7
+#define reg_top_dummyC_pos 0
+#define reg_top_dummyC_len 8
+#define reg_top_dummyC_lsb 0
+#define xd_p_reg_top_dummyD (*(volatile byte xdata *) 0xF9C8)
+#define    p_reg_top_dummyD 0xF9C8
+#define reg_top_dummyD_pos 0
+#define reg_top_dummyD_len 8
+#define reg_top_dummyD_lsb 0
+#define xd_p_reg_top_dummyE (*(volatile byte xdata *) 0xF9C9)
+#define    p_reg_top_dummyE 0xF9C9
+#define reg_top_dummyE_pos 0
+#define reg_top_dummyE_len 8
+#define reg_top_dummyE_lsb 0
+#define xd_p_reg_top_dummyF (*(volatile byte xdata *) 0xF9CA)
+#define    p_reg_top_dummyF 0xF9CA
+#define reg_top_dummyF_pos 0
+#define reg_top_dummyF_len 8
+#define reg_top_dummyF_lsb 0
+#define xd_p_reg_mp2if_clk_coeff    (*(volatile byte xdata *) 0xF9CB)
+#define    p_reg_mp2if_clk_coeff    0xF9CB
+#define reg_mp2if_clk_coeff_pos 0
+#define reg_mp2if_clk_coeff_len 7
+#define reg_mp2if_clk_coeff_lsb 0
+#define xd_p_reg_tsip_en    (*(volatile byte xdata *) 0xF9CC)
+#define    p_reg_tsip_en    0xF9CC
+#define reg_tsip_en_pos 0
+#define reg_tsip_en_len 1
+#define reg_tsip_en_lsb 0
+#define xd_p_reg_tsis_en    (*(volatile byte xdata *) 0xF9CD)
+#define    p_reg_tsis_en    0xF9CD
+#define reg_tsis_en_pos 0
+#define reg_tsis_en_len 1
+#define reg_tsis_en_lsb 0
+#define xd_p_reg_tsip_br    (*(volatile byte xdata *) 0xF9CE)
+#define    p_reg_tsip_br    0xF9CE
+#define reg_tsip_br_pos 0
+#define reg_tsip_br_len 1
+#define reg_tsip_br_lsb 0
+#define xd_p_reg_tsip_frm_inv   (*(volatile byte xdata *) 0xF9D0)
+#define    p_reg_tsip_frm_inv   0xF9D0
+#define reg_tsip_frm_inv_pos 0
+#define reg_tsip_frm_inv_len 1
+#define reg_tsip_frm_inv_lsb 0
+#define xd_p_reg_tsip_str_inv   (*(volatile byte xdata *) 0xF9D1)
+#define    p_reg_tsip_str_inv   0xF9D1
+#define reg_tsip_str_inv_pos 0
+#define reg_tsip_str_inv_len 1
+#define reg_tsip_str_inv_lsb 0
+#define xd_p_reg_tsip_fail_inv  (*(volatile byte xdata *) 0xF9D2)
+#define    p_reg_tsip_fail_inv  0xF9D2
+#define reg_tsip_fail_inv_pos 0
+#define reg_tsip_fail_inv_len 1
+#define reg_tsip_fail_inv_lsb 0
+#define xd_p_reg_tsip_frm_ignore    (*(volatile byte xdata *) 0xF9D3)
+#define    p_reg_tsip_frm_ignore    0xF9D3
+#define reg_tsip_frm_ignore_pos 0
+#define reg_tsip_frm_ignore_len 1
+#define reg_tsip_frm_ignore_lsb 0
+#define xd_p_reg_tsip_str_ignore    (*(volatile byte xdata *) 0xF9D4)
+#define    p_reg_tsip_str_ignore    0xF9D4
+#define reg_tsip_str_ignore_pos 0
+#define reg_tsip_str_ignore_len 1
+#define reg_tsip_str_ignore_lsb 0
+#define xd_p_reg_tsip_fail_ignore   (*(volatile byte xdata *) 0xF9D5)
+#define    p_reg_tsip_fail_ignore   0xF9D5
+#define reg_tsip_fail_ignore_pos 0
+#define reg_tsip_fail_ignore_len 1
+#define reg_tsip_fail_ignore_lsb 0
+#define xd_p_reg_tsip_endian    (*(volatile byte xdata *) 0xF9D6)
+#define    p_reg_tsip_endian    0xF9D6
+#define reg_tsip_endian_pos 0
+#define reg_tsip_endian_len 1
+#define reg_tsip_endian_lsb 0
+#define xd_p_reg_tsip_overflow  (*(volatile byte xdata *) 0xF9D7)
+#define    p_reg_tsip_overflow  0xF9D7
+#define reg_tsip_overflow_pos 0
+#define reg_tsip_overflow_len 1
+#define reg_tsip_overflow_lsb 0
+#define xd_p_reg_ts_in_src  (*(volatile byte xdata *) 0xF9D8)
+#define    p_reg_ts_in_src  0xF9D8
+#define reg_ts_in_src_pos 0
+#define reg_ts_in_src_len 1
+#define reg_ts_in_src_lsb 0
+#define xd_r_reg_clk_sel    (*(volatile byte xdata *) 0xF9D9)
+#define    r_reg_clk_sel    0xF9D9
+#define reg_clk_sel_pos 0
+#define reg_clk_sel_len 2
+#define reg_clk_sel_lsb 0
+#define xd_r_reg_tog_sel    (*(volatile byte xdata *) 0xF9DA)
+#define    r_reg_tog_sel    0xF9DA
+#define reg_tog_sel_pos 0
+#define reg_tog_sel_len 2
+#define reg_tog_sel_lsb 0
+#define xd_p_reg_ts_str_ignore  (*(volatile byte xdata *) 0xF9DB)
+#define    p_reg_ts_str_ignore  0xF9DB
+#define reg_ts_str_ignore_pos 0
+#define reg_ts_str_ignore_len 1
+#define reg_ts_str_ignore_lsb 0
+#define xd_p_reg_ts_frm_ignore  (*(volatile byte xdata *) 0xF9DC)
+#define    p_reg_ts_frm_ignore  0xF9DC
+#define reg_ts_frm_ignore_pos 0
+#define reg_ts_frm_ignore_len 1
+#define reg_ts_frm_ignore_lsb 0
+#define xd_p_reg_clk_sel_fix    (*(volatile byte xdata *) 0xF9DD)
+#define    p_reg_clk_sel_fix    0xF9DD
+#define reg_clk_sel_fix_pos 0
+#define reg_clk_sel_fix_len 2
+#define reg_clk_sel_fix_lsb 0
+#define xd_p_reg_tog_sel_fix    (*(volatile byte xdata *) 0xF9DE)
+#define    p_reg_tog_sel_fix    0xF9DE
+#define reg_tog_sel_fix_pos 0
+#define reg_tog_sel_fix_len 2
+#define reg_tog_sel_fix_lsb 0
+#define xd_p_reg_en_fix (*(volatile byte xdata *) 0xF9DF)
+#define    p_reg_en_fix 0xF9DF
+#define reg_en_fix_pos 0
+#define reg_en_fix_len 1
+#define reg_en_fix_lsb 0
+#define xd_p_reg_check_tpsd_hier    (*(volatile byte xdata *) 0xF9E0)
+#define    p_reg_check_tpsd_hier    0xF9E0
+#define reg_check_tpsd_hier_pos 0
+#define reg_check_tpsd_hier_len 1
+#define reg_check_tpsd_hier_lsb 0
+#define xd_p_reg_p_i2s_master_mode  (*(volatile byte xdata *) 0xF9E1)
+#define    p_reg_p_i2s_master_mode  0xF9E1
+#define reg_p_i2s_master_mode_pos 0
+#define reg_p_i2s_master_mode_len 1
+#define reg_p_i2s_master_mode_lsb 0
+#define xd_p_reg_p_sc_lr_ratio  (*(volatile byte xdata *) 0xF9E2)
+#define    p_reg_p_sc_lr_ratio  0xF9E2
+#define reg_p_sc_lr_ratio_pos 0
+#define reg_p_sc_lr_ratio_len 2
+#define reg_p_sc_lr_ratio_lsb 0
+#define xd_p_reg_p_i2s_fs_type  (*(volatile byte xdata *) 0xF9E2)
+#define    p_reg_p_i2s_fs_type  0xF9E2
+#define reg_p_i2s_fs_type_pos 2
+#define reg_p_i2s_fs_type_len 2
+#define reg_p_i2s_fs_type_lsb 0
+#define xd_r_reg_r_pp_fullq (*(volatile byte xdata *) 0xF9E3)
+#define    r_reg_r_pp_fullq 0xF9E3
+#define reg_r_pp_fullq_pos 0
+#define reg_r_pp_fullq_len 1
+#define reg_r_pp_fullq_lsb 0
+#define xd_p_reg_r_ccir_rst (*(volatile byte xdata *) 0xF9E3)
+#define    p_reg_r_ccir_rst 0xF9E3
+#define reg_r_ccir_rst_pos 1
+#define reg_r_ccir_rst_len 1
+#define reg_r_ccir_rst_lsb 0
+#define xd_p_reg_p_full_en  (*(volatile byte xdata *) 0xF9E3)
+#define    p_reg_p_full_en  0xF9E3
+#define reg_p_full_en_pos 2
+#define reg_p_full_en_len 1
+#define reg_p_full_en_lsb 0
+#define xd_p_reg_p_vbi_dis  (*(volatile byte xdata *) 0xF9E3)
+#define    p_reg_p_vbi_dis  0xF9E3
+#define reg_p_vbi_dis_pos 3
+#define reg_p_vbi_dis_len 1
+#define reg_p_vbi_dis_lsb 0
+#define xd_p_reg_p_ccir_all (*(volatile byte xdata *) 0xF9E3)
+#define    p_reg_p_ccir_all 0xF9E3
+#define reg_p_ccir_all_pos 4
+#define reg_p_ccir_all_len 1
+#define reg_p_ccir_all_lsb 0
+#define xd_p_reg_p_ccir_vbi_raw_en  (*(volatile byte xdata *) 0xF9E3)
+#define    p_reg_p_ccir_vbi_raw_en  0xF9E3
+#define reg_p_ccir_vbi_raw_en_pos 5
+#define reg_p_ccir_vbi_raw_en_len 1
+#define reg_p_ccir_vbi_raw_en_lsb 0
+#define xd_p_reg_err_byte_en    (*(volatile byte xdata *) 0xF9E4)
+#define    p_reg_err_byte_en    0xF9E4
+#define reg_err_byte_en_pos 0
+#define reg_err_byte_en_len 1
+#define reg_err_byte_en_lsb 0
+#define xd_p_reg_mp2_f_adc_7_0  (*(volatile byte xdata *) 0xF9E5)
+#define    p_reg_mp2_f_adc_7_0  0xF9E5
+#define reg_mp2_f_adc_7_0_pos 0
+#define reg_mp2_f_adc_7_0_len 8
+#define reg_mp2_f_adc_7_0_lsb 0
+#define xd_p_reg_mp2_f_adc_15_8 (*(volatile byte xdata *) 0xF9E6)
+#define    p_reg_mp2_f_adc_15_8 0xF9E6
+#define reg_mp2_f_adc_15_8_pos 0
+#define reg_mp2_f_adc_15_8_len 8
+#define reg_mp2_f_adc_15_8_lsb 8
+#define xd_p_reg_mp2_f_adc_23_16    (*(volatile byte xdata *) 0xF9E7)
+#define    p_reg_mp2_f_adc_23_16    0xF9E7
+#define reg_mp2_f_adc_23_16_pos 0
+#define reg_mp2_f_adc_23_16_len 8
+#define reg_mp2_f_adc_23_16_lsb 16
+#define xd_p_reg_set_util   (*(volatile byte xdata *) 0xF9E8)
+#define    p_reg_set_util   0xF9E8
+#define reg_set_util_pos 0
+#define reg_set_util_len 8
+#define reg_set_util_lsb 0
+#define xd_r_reg_err_byte   (*(volatile byte xdata *) 0xF9E9)
+#define    r_reg_err_byte   0xF9E9
+#define reg_err_byte_pos 0
+#define reg_err_byte_len 8
+#define reg_err_byte_lsb 0
+#define xd_p_reg_p_ln_num1  (*(volatile byte xdata *) 0xF9EA)
+#define    p_reg_p_ln_num1  0xF9EA
+#define reg_p_ln_num1_pos 0
+#define reg_p_ln_num1_len 5
+#define reg_p_ln_num1_lsb 0
+#define xd_p_reg_p_ln_num2_2_0  (*(volatile byte xdata *) 0xF9EA)
+#define    p_reg_p_ln_num2_2_0  0xF9EA
+#define reg_p_ln_num2_2_0_pos 5
+#define reg_p_ln_num2_2_0_len 3
+#define reg_p_ln_num2_2_0_lsb 0
+#define xd_p_reg_p_ln_num2_4_3  (*(volatile byte xdata *) 0xF9EB)
+#define    p_reg_p_ln_num2_4_3  0xF9EB
+#define reg_p_ln_num2_4_3_pos 0
+#define reg_p_ln_num2_4_3_len 2
+#define reg_p_ln_num2_4_3_lsb 3
+#define xd_p_reg_p_ln_num3_5_0  (*(volatile byte xdata *) 0xF9EB)
+#define    p_reg_p_ln_num3_5_0  0xF9EB
+#define reg_p_ln_num3_5_0_pos 2
+#define reg_p_ln_num3_5_0_len 6
+#define reg_p_ln_num3_5_0_lsb 0
+#define xd_p_reg_p_ln_num3_8_6  (*(volatile byte xdata *) 0xF9EC)
+#define    p_reg_p_ln_num3_8_6  0xF9EC
+#define reg_p_ln_num3_8_6_pos 0
+#define reg_p_ln_num3_8_6_len 3
+#define reg_p_ln_num3_8_6_lsb 6
+#define xd_p_reg_p_ln_num4_4_0  (*(volatile byte xdata *) 0xF9EC)
+#define    p_reg_p_ln_num4_4_0  0xF9EC
+#define reg_p_ln_num4_4_0_pos 3
+#define reg_p_ln_num4_4_0_len 5
+#define reg_p_ln_num4_4_0_lsb 0
+#define xd_p_reg_p_ln_num4_8_5  (*(volatile byte xdata *) 0xF9ED)
+#define    p_reg_p_ln_num4_8_5  0xF9ED
+#define reg_p_ln_num4_8_5_pos 0
+#define reg_p_ln_num4_8_5_len 4
+#define reg_p_ln_num4_8_5_lsb 5
+#define xd_p_reg_p_ln_num5_3_0  (*(volatile byte xdata *) 0xF9ED)
+#define    p_reg_p_ln_num5_3_0  0xF9ED
+#define reg_p_ln_num5_3_0_pos 4
+#define reg_p_ln_num5_3_0_len 4
+#define reg_p_ln_num5_3_0_lsb 0
+#define xd_p_reg_p_ln_num5_8_4  (*(volatile byte xdata *) 0xF9EE)
+#define    p_reg_p_ln_num5_8_4  0xF9EE
+#define reg_p_ln_num5_8_4_pos 0
+#define reg_p_ln_num5_8_4_len 5
+#define reg_p_ln_num5_8_4_lsb 4
+#define xd_p_reg_p_ln_num6_2_0  (*(volatile byte xdata *) 0xF9EE)
+#define    p_reg_p_ln_num6_2_0  0xF9EE
+#define reg_p_ln_num6_2_0_pos 5
+#define reg_p_ln_num6_2_0_len 3
+#define reg_p_ln_num6_2_0_lsb 0
+#define xd_p_reg_p_ln_num6_8_3  (*(volatile byte xdata *) 0xF9EF)
+#define    p_reg_p_ln_num6_8_3  0xF9EF
+#define reg_p_ln_num6_8_3_pos 0
+#define reg_p_ln_num6_8_3_len 6
+#define reg_p_ln_num6_8_3_lsb 3
+#define xd_p_reg_p_pixel_num_7_0    (*(volatile byte xdata *) 0xF9F0)
+#define    p_reg_p_pixel_num_7_0    0xF9F0
+#define reg_p_pixel_num_7_0_pos 0
+#define reg_p_pixel_num_7_0_len 8
+#define reg_p_pixel_num_7_0_lsb 0
+#define xd_p_reg_p_pixel_num_10_8   (*(volatile byte xdata *) 0xF9F1)
+#define    p_reg_p_pixel_num_10_8   0xF9F1
+#define reg_p_pixel_num_10_8_pos 0
+#define reg_p_pixel_num_10_8_len 3
+#define reg_p_pixel_num_10_8_lsb 8
+#define xd_p_reg_p_ccir_yuv_en  (*(volatile byte xdata *) 0xF9F1)
+#define    p_reg_p_ccir_yuv_en  0xF9F1
+#define reg_p_ccir_yuv_en_pos 3
+#define reg_p_ccir_yuv_en_len 1
+#define reg_p_ccir_yuv_en_lsb 0
+#define xd_p_reg_p_ccir_size_sft    (*(volatile byte xdata *) 0xF9F1)
+#define    p_reg_p_ccir_size_sft    0xF9F1
+#define reg_p_ccir_size_sft_pos 4
+#define reg_p_ccir_size_sft_len 2
+#define reg_p_ccir_size_sft_lsb 0
+#define xd_p_reg_p_psb_cnt_sft  (*(volatile byte xdata *) 0xF9F1)
+#define    p_reg_p_psb_cnt_sft  0xF9F1
+#define reg_p_psb_cnt_sft_pos 6
+#define reg_p_psb_cnt_sft_len 2
+#define reg_p_psb_cnt_sft_lsb 0
+#define xd_p_reg_p_tpsd_lock_trigger    (*(volatile byte xdata *) 0xF9F2)
+#define    p_reg_p_tpsd_lock_trigger    0xF9F2
+#define reg_p_tpsd_lock_trigger_pos 0
+#define reg_p_tpsd_lock_trigger_len 1
+#define reg_p_tpsd_lock_trigger_lsb 0
+#define xd_p_reg_p_ccir_clk_sel (*(volatile byte xdata *) 0xF9F3)
+#define    p_reg_p_ccir_clk_sel 0xF9F3
+#define reg_p_ccir_clk_sel_pos 0
+#define reg_p_ccir_clk_sel_len 1
+#define reg_p_ccir_clk_sel_lsb 0
+#define xd_p_reg_i2c_16_8_data_sel  (*(volatile byte xdata *) 0xFB00)
+#define    p_reg_i2c_16_8_data_sel  0xFB00
+#define reg_i2c_16_8_data_sel_pos 0
+#define reg_i2c_16_8_data_sel_len 1
+#define reg_i2c_16_8_data_sel_lsb 0
+#define xd_p_reg_i2c_slave_trigger_byte (*(volatile byte xdata *) 0xFB01)
+#define    p_reg_i2c_slave_trigger_byte 0xFB01
+#define reg_i2c_slave_trigger_byte_pos 0
+#define reg_i2c_slave_trigger_byte_len 1
+#define reg_i2c_slave_trigger_byte_lsb 0
+#define xd_p_reg_wdti_level (*(volatile byte xdata *) 0xFB05)
+#define    p_reg_wdti_level 0xFB05
+#define reg_wdti_level_pos 0
+#define reg_wdti_level_len 1
+#define reg_wdti_level_lsb 0
+#define xd_p_reg_rssi_avg_sel_lat   (*(volatile byte xdata *) 0xFB06)
+#define    p_reg_rssi_avg_sel_lat   0xFB06
+#define reg_rssi_avg_sel_lat_pos 0
+#define reg_rssi_avg_sel_lat_len 2
+#define reg_rssi_avg_sel_lat_lsb 0
+#define xd_r_ofsm_rssi_avg_7_0  (*(volatile byte xdata *) 0xFB07)
+#define    r_ofsm_rssi_avg_7_0  0xFB07
+#define ofsm_rssi_avg_7_0_pos 0
+#define ofsm_rssi_avg_7_0_len 8
+#define ofsm_rssi_avg_7_0_lsb 0
+#define xd_r_ofsm_rssi_avg_9_8  (*(volatile byte xdata *) 0xFB08)
+#define    r_ofsm_rssi_avg_9_8  0xFB08
+#define ofsm_rssi_avg_9_8_pos 0
+#define ofsm_rssi_avg_9_8_len 2
+#define ofsm_rssi_avg_9_8_lsb 8
+#define xd_r_ofsm_mbist_fail_mon51  (*(volatile byte xdata *) 0xFB09)
+#define    r_ofsm_mbist_fail_mon51  0xFB09
+#define ofsm_mbist_fail_mon51_pos 0
+#define ofsm_mbist_fail_mon51_len 1
+#define ofsm_mbist_fail_mon51_lsb 0
+#define xd_r_ofsm_mbist_fail_com    (*(volatile byte xdata *) 0xFB0A)
+#define    r_ofsm_mbist_fail_com    0xFB0A
+#define ofsm_mbist_fail_com_pos 0
+#define ofsm_mbist_fail_com_len 1
+#define ofsm_mbist_fail_com_lsb 0
+#define xd_r_ofsm_mbist_fail_fft    (*(volatile byte xdata *) 0xFB0B)
+#define    r_ofsm_mbist_fail_fft    0xFB0B
+#define ofsm_mbist_fail_fft_pos 0
+#define ofsm_mbist_fail_fft_len 1
+#define ofsm_mbist_fail_fft_lsb 0
+#define xd_r_ofsm_mbist_fail_fd (*(volatile byte xdata *) 0xFB0C)
+#define    r_ofsm_mbist_fail_fd 0xFB0C
+#define ofsm_mbist_fail_fd_pos 0
+#define ofsm_mbist_fail_fd_len 1
+#define ofsm_mbist_fail_fd_lsb 0
+#define xd_r_ofsm_mbist_fail_link   (*(volatile byte xdata *) 0xFB0D)
+#define    r_ofsm_mbist_fail_link   0xFB0D
+#define ofsm_mbist_fail_link_pos 0
+#define ofsm_mbist_fail_link_len 1
+#define ofsm_mbist_fail_link_lsb 0
+#define xd_r_ofsm_mbist_fail_mpe    (*(volatile byte xdata *) 0xFB0E)
+#define    r_ofsm_mbist_fail_mpe    0xFB0E
+#define ofsm_mbist_fail_mpe_pos 0
+#define ofsm_mbist_fail_mpe_len 1
+#define ofsm_mbist_fail_mpe_lsb 0
+#define xd_r_ofsm_mbist_done_mpe    (*(volatile byte xdata *) 0xFB0F)
+#define    r_ofsm_mbist_done_mpe    0xFB0F
+#define ofsm_mbist_done_mpe_pos 0
+#define ofsm_mbist_done_mpe_len 1
+#define ofsm_mbist_done_mpe_lsb 0
+#define xd_r_ofsm_mbist_mode_mpe    (*(volatile byte xdata *) 0xFB10)
+#define    r_ofsm_mbist_mode_mpe    0xFB10
+#define ofsm_mbist_mode_mpe_pos 0
+#define ofsm_mbist_mode_mpe_len 1
+#define ofsm_mbist_mode_mpe_lsb 0
+#define xd_p_ofsm_cmd_reg   (*(volatile byte xdata *) 0xFB11)
+#define    p_ofsm_cmd_reg   0xFB11
+#define ofsm_cmd_reg_pos 0
+#define ofsm_cmd_reg_len 8
+#define ofsm_cmd_reg_lsb 0
+#define xd_p_ofsm_addr_reg_h    (*(volatile byte xdata *) 0xFB12)
+#define    p_ofsm_addr_reg_h    0xFB12
+#define ofsm_addr_reg_h_pos 0
+#define ofsm_addr_reg_h_len 8
+#define ofsm_addr_reg_h_lsb 0
+#define xd_p_ofsm_addr_reg_l    (*(volatile byte xdata *) 0xFB13)
+#define    p_ofsm_addr_reg_l    0xFB13
+#define ofsm_addr_reg_l_pos 0
+#define ofsm_addr_reg_l_len 8
+#define ofsm_addr_reg_l_lsb 0
+#define xd_p_ofsm_data_reg_0    (*(volatile byte xdata *) 0xFB14)
+#define    p_ofsm_data_reg_0    0xFB14
+#define ofsm_data_reg_0_pos 0
+#define ofsm_data_reg_0_len 8
+#define ofsm_data_reg_0_lsb 0
+#define xd_p_ofsm_data_reg_1    (*(volatile byte xdata *) 0xFB15)
+#define    p_ofsm_data_reg_1    0xFB15
+#define ofsm_data_reg_1_pos 0
+#define ofsm_data_reg_1_len 8
+#define ofsm_data_reg_1_lsb 0
+#define xd_p_ofsm_data_reg_2    (*(volatile byte xdata *) 0xFB16)
+#define    p_ofsm_data_reg_2    0xFB16
+#define ofsm_data_reg_2_pos 0
+#define ofsm_data_reg_2_len 8
+#define ofsm_data_reg_2_lsb 0
+#define xd_p_ofsm_data_reg_3    (*(volatile byte xdata *) 0xFB17)
+#define    p_ofsm_data_reg_3    0xFB17
+#define ofsm_data_reg_3_pos 0
+#define ofsm_data_reg_3_len 8
+#define ofsm_data_reg_3_lsb 0
+#define xd_p_ofsm_data_reg_4    (*(volatile byte xdata *) 0xFB18)
+#define    p_ofsm_data_reg_4    0xFB18
+#define ofsm_data_reg_4_pos 0
+#define ofsm_data_reg_4_len 8
+#define ofsm_data_reg_4_lsb 0
+#define xd_p_ofsm_data_reg_5    (*(volatile byte xdata *) 0xFB19)
+#define    p_ofsm_data_reg_5    0xFB19
+#define ofsm_data_reg_5_pos 0
+#define ofsm_data_reg_5_len 8
+#define ofsm_data_reg_5_lsb 0
+#define xd_p_ofsm_data_reg_6    (*(volatile byte xdata *) 0xFB1A)
+#define    p_ofsm_data_reg_6    0xFB1A
+#define ofsm_data_reg_6_pos 0
+#define ofsm_data_reg_6_len 8
+#define ofsm_data_reg_6_lsb 0
+#define xd_p_ofsm_data_reg_7    (*(volatile byte xdata *) 0xFB1B)
+#define    p_ofsm_data_reg_7    0xFB1B
+#define ofsm_data_reg_7_pos 0
+#define ofsm_data_reg_7_len 8
+#define ofsm_data_reg_7_lsb 0
+#define xd_p_ofsm_data_reg_8    (*(volatile byte xdata *) 0xFB1C)
+#define    p_ofsm_data_reg_8    0xFB1C
+#define ofsm_data_reg_8_pos 0
+#define ofsm_data_reg_8_len 8
+#define ofsm_data_reg_8_lsb 0
+#define xd_p_ofsm_data_reg_9    (*(volatile byte xdata *) 0xFB1D)
+#define    p_ofsm_data_reg_9    0xFB1D
+#define ofsm_data_reg_9_pos 0
+#define ofsm_data_reg_9_len 8
+#define ofsm_data_reg_9_lsb 0
+#define xd_p_ofsm_data_reg_10   (*(volatile byte xdata *) 0xFB1E)
+#define    p_ofsm_data_reg_10   0xFB1E
+#define ofsm_data_reg_10_pos 0
+#define ofsm_data_reg_10_len 8
+#define ofsm_data_reg_10_lsb 0
+#define xd_p_ofsm_data_reg_11   (*(volatile byte xdata *) 0xFB1F)
+#define    p_ofsm_data_reg_11   0xFB1F
+#define ofsm_data_reg_11_pos 0
+#define ofsm_data_reg_11_len 8
+#define ofsm_data_reg_11_lsb 0
+#define xd_p_ofsm_data_reg_12   (*(volatile byte xdata *) 0xFB20)
+#define    p_ofsm_data_reg_12   0xFB20
+#define ofsm_data_reg_12_pos 0
+#define ofsm_data_reg_12_len 8
+#define ofsm_data_reg_12_lsb 0
+#define xd_p_ofsm_data_reg_13   (*(volatile byte xdata *) 0xFB21)
+#define    p_ofsm_data_reg_13   0xFB21
+#define ofsm_data_reg_13_pos 0
+#define ofsm_data_reg_13_len 8
+#define ofsm_data_reg_13_lsb 0
+#define xd_p_ofsm_data_reg_14   (*(volatile byte xdata *) 0xFB22)
+#define    p_ofsm_data_reg_14   0xFB22
+#define ofsm_data_reg_14_pos 0
+#define ofsm_data_reg_14_len 8
+#define ofsm_data_reg_14_lsb 0
+#define xd_p_ofsm_data_reg_15   (*(volatile byte xdata *) 0xFB23)
+#define    p_ofsm_data_reg_15   0xFB23
+#define ofsm_data_reg_15_pos 0
+#define ofsm_data_reg_15_len 8
+#define ofsm_data_reg_15_lsb 0
+#define xd_p_reg_afe_mem0   (*(volatile byte xdata *) 0xFB24)
+#define    p_reg_afe_mem0   0xFB24
+#define reg_afe_mem0_pos 0
+#define reg_afe_mem0_len 8
+#define reg_afe_mem0_lsb 0
+#define xd_p_reg_afe_mem1   (*(volatile byte xdata *) 0xFB25)
+#define    p_reg_afe_mem1   0xFB25
+#define reg_afe_mem1_pos 0
+#define reg_afe_mem1_len 8
+#define reg_afe_mem1_lsb 0
+#define xd_p_reg_afe_mem2   (*(volatile byte xdata *) 0xFB26)
+#define    p_reg_afe_mem2   0xFB26
+#define reg_afe_mem2_pos 0
+#define reg_afe_mem2_len 8
+#define reg_afe_mem2_lsb 0
+#define xd_p_reg_afe_mem3   (*(volatile byte xdata *) 0xFB27)
+#define    p_reg_afe_mem3   0xFB27
+#define reg_afe_mem3_pos 0
+#define reg_afe_mem3_len 8
+#define reg_afe_mem3_lsb 0
+#define xd_p_reg_afe_mem4   (*(volatile byte xdata *) 0xFB28)
+#define    p_reg_afe_mem4   0xFB28
+#define reg_afe_mem4_pos 0
+#define reg_afe_mem4_len 8
+#define reg_afe_mem4_lsb 0
+#define xd_p_reg_afe_mem5   (*(volatile byte xdata *) 0xFB29)
+#define    p_reg_afe_mem5   0xFB29
+#define reg_afe_mem5_pos 0
+#define reg_afe_mem5_len 8
+#define reg_afe_mem5_lsb 0
+#define xd_p_reg_afe_mem6   (*(volatile byte xdata *) 0xFB2A)
+#define    p_reg_afe_mem6   0xFB2A
+#define reg_afe_mem6_pos 0
+#define reg_afe_mem6_len 8
+#define reg_afe_mem6_lsb 0
+#define xd_p_reg_afe_mem7   (*(volatile byte xdata *) 0xFB2B)
+#define    p_reg_afe_mem7   0xFB2B
+#define reg_afe_mem7_pos 0
+#define reg_afe_mem7_len 8
+#define reg_afe_mem7_lsb 0
+#define xd_p_reg_i2cbootreq (*(volatile byte xdata *) 0xFB2C)
+#define    p_reg_i2cbootreq 0xFB2C
+#define reg_i2cbootreq_pos 0
+#define reg_i2cbootreq_len 1
+#define reg_i2cbootreq_lsb 0
+#define xd_p_reg_rst_i2cm   (*(volatile byte xdata *) 0xFB30)
+#define    p_reg_rst_i2cm   0xFB30
+#define reg_rst_i2cm_pos 0
+#define reg_rst_i2cm_len 1
+#define reg_rst_i2cm_lsb 0
+#define xd_p_reg_rst_i2cs   (*(volatile byte xdata *) 0xFB31)
+#define    p_reg_rst_i2cs   0xFB31
+#define reg_rst_i2cs_pos 0
+#define reg_rst_i2cs_len 1
+#define reg_rst_i2cs_lsb 0
+#define xd_r_reg_top_gpioscli   (*(volatile byte xdata *) 0xFB32)
+#define    r_reg_top_gpioscli   0xFB32
+#define reg_top_gpioscli_pos 0
+#define reg_top_gpioscli_len 1
+#define reg_top_gpioscli_lsb 0
+#define xd_p_reg_top_gpiosclo   (*(volatile byte xdata *) 0xFB33)
+#define    p_reg_top_gpiosclo   0xFB33
+#define reg_top_gpiosclo_pos 0
+#define reg_top_gpiosclo_len 1
+#define reg_top_gpiosclo_lsb 0
+#define xd_p_reg_top_gpiosclen  (*(volatile byte xdata *) 0xFB34)
+#define    p_reg_top_gpiosclen  0xFB34
+#define reg_top_gpiosclen_pos 0
+#define reg_top_gpiosclen_len 1
+#define reg_top_gpiosclen_lsb 0
+#define xd_p_reg_top_gpiosclon  (*(volatile byte xdata *) 0xFB35)
+#define    p_reg_top_gpiosclon  0xFB35
+#define reg_top_gpiosclon_pos 0
+#define reg_top_gpiosclon_len 1
+#define reg_top_gpiosclon_lsb 0
+#define xd_r_reg_top_gpiosdai   (*(volatile byte xdata *) 0xFB36)
+#define    r_reg_top_gpiosdai   0xFB36
+#define reg_top_gpiosdai_pos 0
+#define reg_top_gpiosdai_len 1
+#define reg_top_gpiosdai_lsb 0
+#define xd_p_reg_top_gpiosdao   (*(volatile byte xdata *) 0xFB37)
+#define    p_reg_top_gpiosdao   0xFB37
+#define reg_top_gpiosdao_pos 0
+#define reg_top_gpiosdao_len 1
+#define reg_top_gpiosdao_lsb 0
+#define xd_p_reg_top_gpiosdaen  (*(volatile byte xdata *) 0xFB38)
+#define    p_reg_top_gpiosdaen  0xFB38
+#define reg_top_gpiosdaen_pos 0
+#define reg_top_gpiosdaen_len 1
+#define reg_top_gpiosdaen_lsb 0
+#define xd_p_reg_top_gpiosdaon  (*(volatile byte xdata *) 0xFB39)
+#define    p_reg_top_gpiosdaon  0xFB39
+#define reg_top_gpiosdaon_pos 0
+#define reg_top_gpiosdaon_len 1
+#define reg_top_gpiosdaon_lsb 0
+#define xd_p_reg_fix_rom_en (*(volatile byte xdata *) 0xFB3A)
+#define    p_reg_fix_rom_en 0xFB3A
+#define reg_fix_rom_en_pos 0
+#define reg_fix_rom_en_len 1
+#define reg_fix_rom_en_lsb 0
+#define xd_p_reg_ofsm_bug_addh_0    (*(volatile byte xdata *) 0xFB3B)
+#define    p_reg_ofsm_bug_addh_0    0xFB3B
+#define reg_ofsm_bug_addh_0_pos 0
+#define reg_ofsm_bug_addh_0_len 8
+#define reg_ofsm_bug_addh_0_lsb 0
+#define xd_p_reg_ofsm_bug_addl_0    (*(volatile byte xdata *) 0xFB3C)
+#define    p_reg_ofsm_bug_addl_0    0xFB3C
+#define reg_ofsm_bug_addl_0_pos 0
+#define reg_ofsm_bug_addl_0_len 8
+#define reg_ofsm_bug_addl_0_lsb 0
+#define xd_p_reg_ofsm_bug_addh_1    (*(volatile byte xdata *) 0xFB3D)
+#define    p_reg_ofsm_bug_addh_1    0xFB3D
+#define reg_ofsm_bug_addh_1_pos 0
+#define reg_ofsm_bug_addh_1_len 8
+#define reg_ofsm_bug_addh_1_lsb 0
+#define xd_p_reg_ofsm_bug_addl_1    (*(volatile byte xdata *) 0xFB3E)
+#define    p_reg_ofsm_bug_addl_1    0xFB3E
+#define reg_ofsm_bug_addl_1_pos 0
+#define reg_ofsm_bug_addl_1_len 8
+#define reg_ofsm_bug_addl_1_lsb 0
+#define xd_p_reg_ofsm_bug_addh_2    (*(volatile byte xdata *) 0xFB3F)
+#define    p_reg_ofsm_bug_addh_2    0xFB3F
+#define reg_ofsm_bug_addh_2_pos 0
+#define reg_ofsm_bug_addh_2_len 8
+#define reg_ofsm_bug_addh_2_lsb 0
+#define xd_p_reg_ofsm_bug_addl_2    (*(volatile byte xdata *) 0xFB40)
+#define    p_reg_ofsm_bug_addl_2    0xFB40
+#define reg_ofsm_bug_addl_2_pos 0
+#define reg_ofsm_bug_addl_2_len 8
+#define reg_ofsm_bug_addl_2_lsb 0
+#define xd_p_reg_ofsm_bug_addh_3    (*(volatile byte xdata *) 0xFB41)
+#define    p_reg_ofsm_bug_addh_3    0xFB41
+#define reg_ofsm_bug_addh_3_pos 0
+#define reg_ofsm_bug_addh_3_len 8
+#define reg_ofsm_bug_addh_3_lsb 0
+#define xd_p_reg_ofsm_bug_addl_3    (*(volatile byte xdata *) 0xFB42)
+#define    p_reg_ofsm_bug_addl_3    0xFB42
+#define reg_ofsm_bug_addl_3_pos 0
+#define reg_ofsm_bug_addl_3_len 8
+#define reg_ofsm_bug_addl_3_lsb 0
+#define xd_p_reg_ofsm_bug_addh_4    (*(volatile byte xdata *) 0xFB43)
+#define    p_reg_ofsm_bug_addh_4    0xFB43
+#define reg_ofsm_bug_addh_4_pos 0
+#define reg_ofsm_bug_addh_4_len 8
+#define reg_ofsm_bug_addh_4_lsb 0
+#define xd_p_reg_ofsm_bug_addl_4    (*(volatile byte xdata *) 0xFB44)
+#define    p_reg_ofsm_bug_addl_4    0xFB44
+#define reg_ofsm_bug_addl_4_pos 0
+#define reg_ofsm_bug_addl_4_len 8
+#define reg_ofsm_bug_addl_4_lsb 0
+#define xd_p_reg_ofsm_bug_addh_5    (*(volatile byte xdata *) 0xFB45)
+#define    p_reg_ofsm_bug_addh_5    0xFB45
+#define reg_ofsm_bug_addh_5_pos 0
+#define reg_ofsm_bug_addh_5_len 8
+#define reg_ofsm_bug_addh_5_lsb 0
+#define xd_p_reg_ofsm_bug_addl_5    (*(volatile byte xdata *) 0xFB46)
+#define    p_reg_ofsm_bug_addl_5    0xFB46
+#define reg_ofsm_bug_addl_5_pos 0
+#define reg_ofsm_bug_addl_5_len 8
+#define reg_ofsm_bug_addl_5_lsb 0
+#define xd_p_reg_ofsm_bug_addh_6    (*(volatile byte xdata *) 0xFB47)
+#define    p_reg_ofsm_bug_addh_6    0xFB47
+#define reg_ofsm_bug_addh_6_pos 0
+#define reg_ofsm_bug_addh_6_len 8
+#define reg_ofsm_bug_addh_6_lsb 0
+#define xd_p_reg_ofsm_bug_addl_6    (*(volatile byte xdata *) 0xFB48)
+#define    p_reg_ofsm_bug_addl_6    0xFB48
+#define reg_ofsm_bug_addl_6_pos 0
+#define reg_ofsm_bug_addl_6_len 8
+#define reg_ofsm_bug_addl_6_lsb 0
+#define xd_p_reg_ofsm_bug_addh_7    (*(volatile byte xdata *) 0xFB49)
+#define    p_reg_ofsm_bug_addh_7    0xFB49
+#define reg_ofsm_bug_addh_7_pos 0
+#define reg_ofsm_bug_addh_7_len 8
+#define reg_ofsm_bug_addh_7_lsb 0
+#define xd_p_reg_ofsm_bug_addl_7    (*(volatile byte xdata *) 0xFB4A)
+#define    p_reg_ofsm_bug_addl_7    0xFB4A
+#define reg_ofsm_bug_addl_7_pos 0
+#define reg_ofsm_bug_addl_7_len 8
+#define reg_ofsm_bug_addl_7_lsb 0
+#define xd_p_reg_ofsm_bug_addh_8    (*(volatile byte xdata *) 0xFB4B)
+#define    p_reg_ofsm_bug_addh_8    0xFB4B
+#define reg_ofsm_bug_addh_8_pos 0
+#define reg_ofsm_bug_addh_8_len 8
+#define reg_ofsm_bug_addh_8_lsb 0
+#define xd_p_reg_ofsm_bug_addl_8    (*(volatile byte xdata *) 0xFB4C)
+#define    p_reg_ofsm_bug_addl_8    0xFB4C
+#define reg_ofsm_bug_addl_8_pos 0
+#define reg_ofsm_bug_addl_8_len 8
+#define reg_ofsm_bug_addl_8_lsb 0
+#define xd_p_reg_ofsm_bug_addh_9    (*(volatile byte xdata *) 0xFB4D)
+#define    p_reg_ofsm_bug_addh_9    0xFB4D
+#define reg_ofsm_bug_addh_9_pos 0
+#define reg_ofsm_bug_addh_9_len 8
+#define reg_ofsm_bug_addh_9_lsb 0
+#define xd_p_reg_ofsm_bug_addl_9    (*(volatile byte xdata *) 0xFB4E)
+#define    p_reg_ofsm_bug_addl_9    0xFB4E
+#define reg_ofsm_bug_addl_9_pos 0
+#define reg_ofsm_bug_addl_9_len 8
+#define reg_ofsm_bug_addl_9_lsb 0
+#define xd_p_reg_ofsm_bug_addh_10   (*(volatile byte xdata *) 0xFB4F)
+#define    p_reg_ofsm_bug_addh_10   0xFB4F
+#define reg_ofsm_bug_addh_10_pos 0
+#define reg_ofsm_bug_addh_10_len 8
+#define reg_ofsm_bug_addh_10_lsb 0
+#define xd_p_reg_ofsm_bug_addl_10   (*(volatile byte xdata *) 0xFB50)
+#define    p_reg_ofsm_bug_addl_10   0xFB50
+#define reg_ofsm_bug_addl_10_pos 0
+#define reg_ofsm_bug_addl_10_len 8
+#define reg_ofsm_bug_addl_10_lsb 0
+#define xd_p_reg_ofsm_bug_addh_11   (*(volatile byte xdata *) 0xFB51)
+#define    p_reg_ofsm_bug_addh_11   0xFB51
+#define reg_ofsm_bug_addh_11_pos 0
+#define reg_ofsm_bug_addh_11_len 8
+#define reg_ofsm_bug_addh_11_lsb 0
+#define xd_p_reg_ofsm_bug_addl_11   (*(volatile byte xdata *) 0xFB52)
+#define    p_reg_ofsm_bug_addl_11   0xFB52
+#define reg_ofsm_bug_addl_11_pos 0
+#define reg_ofsm_bug_addl_11_len 8
+#define reg_ofsm_bug_addl_11_lsb 0
+#define xd_p_reg_ofsm_bug_addh_12   (*(volatile byte xdata *) 0xFB53)
+#define    p_reg_ofsm_bug_addh_12   0xFB53
+#define reg_ofsm_bug_addh_12_pos 0
+#define reg_ofsm_bug_addh_12_len 8
+#define reg_ofsm_bug_addh_12_lsb 0
+#define xd_p_reg_ofsm_bug_addl_12   (*(volatile byte xdata *) 0xFB54)
+#define    p_reg_ofsm_bug_addl_12   0xFB54
+#define reg_ofsm_bug_addl_12_pos 0
+#define reg_ofsm_bug_addl_12_len 8
+#define reg_ofsm_bug_addl_12_lsb 0
+#define xd_p_reg_ofsm_bug_addh_13   (*(volatile byte xdata *) 0xFB55)
+#define    p_reg_ofsm_bug_addh_13   0xFB55
+#define reg_ofsm_bug_addh_13_pos 0
+#define reg_ofsm_bug_addh_13_len 8
+#define reg_ofsm_bug_addh_13_lsb 0
+#define xd_p_reg_ofsm_bug_addl_13   (*(volatile byte xdata *) 0xFB56)
+#define    p_reg_ofsm_bug_addl_13   0xFB56
+#define reg_ofsm_bug_addl_13_pos 0
+#define reg_ofsm_bug_addl_13_len 8
+#define reg_ofsm_bug_addl_13_lsb 0
+#define xd_p_reg_ofsm_bug_addh_14   (*(volatile byte xdata *) 0xFB57)
+#define    p_reg_ofsm_bug_addh_14   0xFB57
+#define reg_ofsm_bug_addh_14_pos 0
+#define reg_ofsm_bug_addh_14_len 8
+#define reg_ofsm_bug_addh_14_lsb 0
+#define xd_p_reg_ofsm_bug_addl_14   (*(volatile byte xdata *) 0xFB58)
+#define    p_reg_ofsm_bug_addl_14   0xFB58
+#define reg_ofsm_bug_addl_14_pos 0
+#define reg_ofsm_bug_addl_14_len 8
+#define reg_ofsm_bug_addl_14_lsb 0
+#define xd_p_reg_ofsm_bug_addh_15   (*(volatile byte xdata *) 0xFB59)
+#define    p_reg_ofsm_bug_addh_15   0xFB59
+#define reg_ofsm_bug_addh_15_pos 0
+#define reg_ofsm_bug_addh_15_len 8
+#define reg_ofsm_bug_addh_15_lsb 0
+#define xd_p_reg_ofsm_bug_addl_15   (*(volatile byte xdata *) 0xFB5A)
+#define    p_reg_ofsm_bug_addl_15   0xFB5A
+#define reg_ofsm_bug_addl_15_pos 0
+#define reg_ofsm_bug_addl_15_len 8
+#define reg_ofsm_bug_addl_15_lsb 0
+#define xd_p_reg_ofsm_jmp_addh_0    (*(volatile byte xdata *) 0xFB5B)
+#define    p_reg_ofsm_jmp_addh_0    0xFB5B
+#define reg_ofsm_jmp_addh_0_pos 0
+#define reg_ofsm_jmp_addh_0_len 8
+#define reg_ofsm_jmp_addh_0_lsb 0
+#define xd_p_reg_ofsm_jmp_addl_0    (*(volatile byte xdata *) 0xFB5C)
+#define    p_reg_ofsm_jmp_addl_0    0xFB5C
+#define reg_ofsm_jmp_addl_0_pos 0
+#define reg_ofsm_jmp_addl_0_len 8
+#define reg_ofsm_jmp_addl_0_lsb 0
+#define xd_p_reg_ofsm_jmp_addh_1    (*(volatile byte xdata *) 0xFB5D)
+#define    p_reg_ofsm_jmp_addh_1    0xFB5D
+#define reg_ofsm_jmp_addh_1_pos 0
+#define reg_ofsm_jmp_addh_1_len 8
+#define reg_ofsm_jmp_addh_1_lsb 0
+#define xd_p_reg_ofsm_jmp_addl_1    (*(volatile byte xdata *) 0xFB5E)
+#define    p_reg_ofsm_jmp_addl_1    0xFB5E
+#define reg_ofsm_jmp_addl_1_pos 0
+#define reg_ofsm_jmp_addl_1_len 8
+#define reg_ofsm_jmp_addl_1_lsb 0
+#define xd_p_reg_ofsm_jmp_addh_2    (*(volatile byte xdata *) 0xFB5F)
+#define    p_reg_ofsm_jmp_addh_2    0xFB5F
+#define reg_ofsm_jmp_addh_2_pos 0
+#define reg_ofsm_jmp_addh_2_len 8
+#define reg_ofsm_jmp_addh_2_lsb 0
+#define xd_p_reg_ofsm_jmp_addl_2    (*(volatile byte xdata *) 0xFB60)
+#define    p_reg_ofsm_jmp_addl_2    0xFB60
+#define reg_ofsm_jmp_addl_2_pos 0
+#define reg_ofsm_jmp_addl_2_len 8
+#define reg_ofsm_jmp_addl_2_lsb 0
+#define xd_p_reg_ofsm_jmp_addh_3    (*(volatile byte xdata *) 0xFB61)
+#define    p_reg_ofsm_jmp_addh_3    0xFB61
+#define reg_ofsm_jmp_addh_3_pos 0
+#define reg_ofsm_jmp_addh_3_len 8
+#define reg_ofsm_jmp_addh_3_lsb 0
+#define xd_p_reg_ofsm_jmp_addl_3    (*(volatile byte xdata *) 0xFB62)
+#define    p_reg_ofsm_jmp_addl_3    0xFB62
+#define reg_ofsm_jmp_addl_3_pos 0
+#define reg_ofsm_jmp_addl_3_len 8
+#define reg_ofsm_jmp_addl_3_lsb 0
+#define xd_p_reg_ofsm_jmp_addh_4    (*(volatile byte xdata *) 0xFB63)
+#define    p_reg_ofsm_jmp_addh_4    0xFB63
+#define reg_ofsm_jmp_addh_4_pos 0
+#define reg_ofsm_jmp_addh_4_len 8
+#define reg_ofsm_jmp_addh_4_lsb 0
+#define xd_p_reg_ofsm_jmp_addl_4    (*(volatile byte xdata *) 0xFB64)
+#define    p_reg_ofsm_jmp_addl_4    0xFB64
+#define reg_ofsm_jmp_addl_4_pos 0
+#define reg_ofsm_jmp_addl_4_len 8
+#define reg_ofsm_jmp_addl_4_lsb 0
+#define xd_p_reg_ofsm_jmp_addh_5    (*(volatile byte xdata *) 0xFB65)
+#define    p_reg_ofsm_jmp_addh_5    0xFB65
+#define reg_ofsm_jmp_addh_5_pos 0
+#define reg_ofsm_jmp_addh_5_len 8
+#define reg_ofsm_jmp_addh_5_lsb 0
+#define xd_p_reg_ofsm_jmp_addl_5    (*(volatile byte xdata *) 0xFB66)
+#define    p_reg_ofsm_jmp_addl_5    0xFB66
+#define reg_ofsm_jmp_addl_5_pos 0
+#define reg_ofsm_jmp_addl_5_len 8
+#define reg_ofsm_jmp_addl_5_lsb 0
+#define xd_p_reg_ofsm_jmp_addh_6    (*(volatile byte xdata *) 0xFB67)
+#define    p_reg_ofsm_jmp_addh_6    0xFB67
+#define reg_ofsm_jmp_addh_6_pos 0
+#define reg_ofsm_jmp_addh_6_len 8
+#define reg_ofsm_jmp_addh_6_lsb 0
+#define xd_p_reg_ofsm_jmp_addl_6    (*(volatile byte xdata *) 0xFB68)
+#define    p_reg_ofsm_jmp_addl_6    0xFB68
+#define reg_ofsm_jmp_addl_6_pos 0
+#define reg_ofsm_jmp_addl_6_len 8
+#define reg_ofsm_jmp_addl_6_lsb 0
+#define xd_p_reg_ofsm_jmp_addh_7    (*(volatile byte xdata *) 0xFB69)
+#define    p_reg_ofsm_jmp_addh_7    0xFB69
+#define reg_ofsm_jmp_addh_7_pos 0
+#define reg_ofsm_jmp_addh_7_len 8
+#define reg_ofsm_jmp_addh_7_lsb 0
+#define xd_p_reg_ofsm_jmp_addl_7    (*(volatile byte xdata *) 0xFB6A)
+#define    p_reg_ofsm_jmp_addl_7    0xFB6A
+#define reg_ofsm_jmp_addl_7_pos 0
+#define reg_ofsm_jmp_addl_7_len 8
+#define reg_ofsm_jmp_addl_7_lsb 0
+#define xd_p_reg_ofsm_jmp_addh_8    (*(volatile byte xdata *) 0xFB6B)
+#define    p_reg_ofsm_jmp_addh_8    0xFB6B
+#define reg_ofsm_jmp_addh_8_pos 0
+#define reg_ofsm_jmp_addh_8_len 8
+#define reg_ofsm_jmp_addh_8_lsb 0
+#define xd_p_reg_ofsm_jmp_addl_8    (*(volatile byte xdata *) 0xFB6C)
+#define    p_reg_ofsm_jmp_addl_8    0xFB6C
+#define reg_ofsm_jmp_addl_8_pos 0
+#define reg_ofsm_jmp_addl_8_len 8
+#define reg_ofsm_jmp_addl_8_lsb 0
+#define xd_p_reg_ofsm_jmp_addh_9    (*(volatile byte xdata *) 0xFB6D)
+#define    p_reg_ofsm_jmp_addh_9    0xFB6D
+#define reg_ofsm_jmp_addh_9_pos 0
+#define reg_ofsm_jmp_addh_9_len 8
+#define reg_ofsm_jmp_addh_9_lsb 0
+#define xd_p_reg_ofsm_jmp_addl_9    (*(volatile byte xdata *) 0xFB6E)
+#define    p_reg_ofsm_jmp_addl_9    0xFB6E
+#define reg_ofsm_jmp_addl_9_pos 0
+#define reg_ofsm_jmp_addl_9_len 8
+#define reg_ofsm_jmp_addl_9_lsb 0
+#define xd_p_reg_ofsm_jmp_addh_10   (*(volatile byte xdata *) 0xFB6F)
+#define    p_reg_ofsm_jmp_addh_10   0xFB6F
+#define reg_ofsm_jmp_addh_10_pos 0
+#define reg_ofsm_jmp_addh_10_len 8
+#define reg_ofsm_jmp_addh_10_lsb 0
+#define xd_p_reg_ofsm_jmp_addl_10   (*(volatile byte xdata *) 0xFB70)
+#define    p_reg_ofsm_jmp_addl_10   0xFB70
+#define reg_ofsm_jmp_addl_10_pos 0
+#define reg_ofsm_jmp_addl_10_len 8
+#define reg_ofsm_jmp_addl_10_lsb 0
+#define xd_p_reg_ofsm_jmp_addh_11   (*(volatile byte xdata *) 0xFB71)
+#define    p_reg_ofsm_jmp_addh_11   0xFB71
+#define reg_ofsm_jmp_addh_11_pos 0
+#define reg_ofsm_jmp_addh_11_len 8
+#define reg_ofsm_jmp_addh_11_lsb 0
+#define xd_p_reg_ofsm_jmp_addl_11   (*(volatile byte xdata *) 0xFB72)
+#define    p_reg_ofsm_jmp_addl_11   0xFB72
+#define reg_ofsm_jmp_addl_11_pos 0
+#define reg_ofsm_jmp_addl_11_len 8
+#define reg_ofsm_jmp_addl_11_lsb 0
+#define xd_p_reg_ofsm_jmp_addh_12   (*(volatile byte xdata *) 0xFB73)
+#define    p_reg_ofsm_jmp_addh_12   0xFB73
+#define reg_ofsm_jmp_addh_12_pos 0
+#define reg_ofsm_jmp_addh_12_len 8
+#define reg_ofsm_jmp_addh_12_lsb 0
+#define xd_p_reg_ofsm_jmp_addl_12   (*(volatile byte xdata *) 0xFB74)
+#define    p_reg_ofsm_jmp_addl_12   0xFB74
+#define reg_ofsm_jmp_addl_12_pos 0
+#define reg_ofsm_jmp_addl_12_len 8
+#define reg_ofsm_jmp_addl_12_lsb 0
+#define xd_p_reg_ofsm_jmp_addh_13   (*(volatile byte xdata *) 0xFB75)
+#define    p_reg_ofsm_jmp_addh_13   0xFB75
+#define reg_ofsm_jmp_addh_13_pos 0
+#define reg_ofsm_jmp_addh_13_len 8
+#define reg_ofsm_jmp_addh_13_lsb 0
+#define xd_p_reg_ofsm_jmp_addl_13   (*(volatile byte xdata *) 0xFB76)
+#define    p_reg_ofsm_jmp_addl_13   0xFB76
+#define reg_ofsm_jmp_addl_13_pos 0
+#define reg_ofsm_jmp_addl_13_len 8
+#define reg_ofsm_jmp_addl_13_lsb 0
+#define xd_p_reg_ofsm_jmp_addh_14   (*(volatile byte xdata *) 0xFB77)
+#define    p_reg_ofsm_jmp_addh_14   0xFB77
+#define reg_ofsm_jmp_addh_14_pos 0
+#define reg_ofsm_jmp_addh_14_len 8
+#define reg_ofsm_jmp_addh_14_lsb 0
+#define xd_p_reg_ofsm_jmp_addl_14   (*(volatile byte xdata *) 0xFB78)
+#define    p_reg_ofsm_jmp_addl_14   0xFB78
+#define reg_ofsm_jmp_addl_14_pos 0
+#define reg_ofsm_jmp_addl_14_len 8
+#define reg_ofsm_jmp_addl_14_lsb 0
+#define xd_p_reg_ofsm_jmp_addh_15   (*(volatile byte xdata *) 0xFB79)
+#define    p_reg_ofsm_jmp_addh_15   0xFB79
+#define reg_ofsm_jmp_addh_15_pos 0
+#define reg_ofsm_jmp_addh_15_len 8
+#define reg_ofsm_jmp_addh_15_lsb 0
+#define xd_p_reg_ofsm_jmp_addl_15   (*(volatile byte xdata *) 0xFB7A)
+#define    p_reg_ofsm_jmp_addl_15   0xFB7A
+#define reg_ofsm_jmp_addl_15_pos 0
+#define reg_ofsm_jmp_addl_15_len 8
+#define reg_ofsm_jmp_addl_15_lsb 0
+#define xd_p_reg_sw_mon51   (*(volatile byte xdata *) 0xFB7B)
+#define    p_reg_sw_mon51   0xFB7B
+#define reg_sw_mon51_pos 0
+#define reg_sw_mon51_len 7
+#define reg_sw_mon51_lsb 0
+#define xd_p_reg_ofdm_mon51_flag    (*(volatile byte xdata *) 0xFB7C)
+#define    p_reg_ofdm_mon51_flag    0xFB7C
+#define reg_ofdm_mon51_flag_pos 0
+#define reg_ofdm_mon51_flag_len 1
+#define reg_ofdm_mon51_flag_lsb 0
+#define xd_p_reg_ofdm_force_mon51   (*(volatile byte xdata *) 0xFB7D)
+#define    p_reg_ofdm_force_mon51   0xFB7D
+#define reg_ofdm_force_mon51_pos 0
+#define reg_ofdm_force_mon51_len 1
+#define reg_ofdm_force_mon51_lsb 0
+#define xd_p_reg_ofdm_which_cpu (*(volatile byte xdata *) 0xFB7E)
+#define    p_reg_ofdm_which_cpu 0xFB7E
+#define reg_ofdm_which_cpu_pos 0
+#define reg_ofdm_which_cpu_len 1
+#define reg_ofdm_which_cpu_lsb 0
+#define xd_p_reg_ofdm_code_ready    (*(volatile byte xdata *) 0xFB7F)
+#define    p_reg_ofdm_code_ready    0xFB7F
+#define reg_ofdm_code_ready_pos 0
+#define reg_ofdm_code_ready_len 1
+#define reg_ofdm_code_ready_lsb 0
+#define xd_p_reg_ofdm_mailbox_wend  (*(volatile byte xdata *) 0xFB80)
+#define    p_reg_ofdm_mailbox_wend  0xFB80
+#define reg_ofdm_mailbox_wend_pos 0
+#define reg_ofdm_mailbox_wend_len 1
+#define reg_ofdm_mailbox_wend_lsb 0
+#define xd_r_reg_fast_slow_train    (*(volatile byte xdata *) 0xFB81)
+#define    r_reg_fast_slow_train    0xFB81
+#define reg_fast_slow_train_pos 0
+#define reg_fast_slow_train_len 1
+#define reg_fast_slow_train_lsb 0
+#define xd_p_reg_ofdm_mailbox_wptr  (*(volatile byte xdata *) 0xFB82)
+#define    p_reg_ofdm_mailbox_wptr  0xFB82
+#define reg_ofdm_mailbox_wptr_pos 0
+#define reg_ofdm_mailbox_wptr_len 8
+#define reg_ofdm_mailbox_wptr_lsb 0
+#define xd_p_reg_ofdm_mailbox_int   (*(volatile byte xdata *) 0xFB86)
+#define    p_reg_ofdm_mailbox_int   0xFB86
+#define reg_ofdm_mailbox_int_pos 0
+#define reg_ofdm_mailbox_int_len 1
+#define reg_ofdm_mailbox_int_lsb 0
+#define xd_p_reg_ofdm_lnk2ofdm_int  (*(volatile byte xdata *) 0xFB87)
+#define    p_reg_ofdm_lnk2ofdm_int  0xFB87
+#define reg_ofdm_lnk2ofdm_int_pos 0
+#define reg_ofdm_lnk2ofdm_int_len 1
+#define reg_ofdm_lnk2ofdm_int_lsb 0
+#define xd_p_reg_ofdm_ofdm2lnk_int  (*(volatile byte xdata *) 0xFB88)
+#define    p_reg_ofdm_ofdm2lnk_int  0xFB88
+#define reg_ofdm_ofdm2lnk_int_pos 0
+#define reg_ofdm_ofdm2lnk_int_len 1
+#define reg_ofdm_ofdm2lnk_int_lsb 0
+#define xd_r_reg_load_ofdm_reg  (*(volatile byte xdata *) 0xFB8F)
+#define    r_reg_load_ofdm_reg  0xFB8F
+#define reg_load_ofdm_reg_pos 0
+#define reg_load_ofdm_reg_len 1
+#define reg_load_ofdm_reg_lsb 0
+#define xd_p_reg_lnk_mbx_rd_length_7_0  (*(volatile byte xdata *) 0xFB90)
+#define    p_reg_lnk_mbx_rd_length_7_0  0xFB90
+#define reg_lnk_mbx_rd_length_7_0_pos 0
+#define reg_lnk_mbx_rd_length_7_0_len 8
+#define reg_lnk_mbx_rd_length_7_0_lsb 0
+#define xd_p_reg_lnk_mbx_rd_length_15_8 (*(volatile byte xdata *) 0xFB91)
+#define    p_reg_lnk_mbx_rd_length_15_8 0xFB91
+#define reg_lnk_mbx_rd_length_15_8_pos 0
+#define reg_lnk_mbx_rd_length_15_8_len 8
+#define reg_lnk_mbx_rd_length_15_8_lsb 8
+#define xd_p_reg_lnk_mbx_rd_length_17_16    (*(volatile byte xdata *) 0xFB92)
+#define    p_reg_lnk_mbx_rd_length_17_16    0xFB92
+#define reg_lnk_mbx_rd_length_17_16_pos 0
+#define reg_lnk_mbx_rd_length_17_16_len 2
+#define reg_lnk_mbx_rd_length_17_16_lsb 16
+#define xd_p_reg_lnk_rd_data_sel    (*(volatile byte xdata *) 0xFB93)
+#define    p_reg_lnk_rd_data_sel    0xFB93
+#define reg_lnk_rd_data_sel_pos 0
+#define reg_lnk_rd_data_sel_len 2
+#define reg_lnk_rd_data_sel_lsb 0
+#define xd_p_reg_ofdm2lnk_data_7_0  (*(volatile byte xdata *) 0xFB96)
+#define    p_reg_ofdm2lnk_data_7_0  0xFB96
+#define reg_ofdm2lnk_data_7_0_pos 0
+#define reg_ofdm2lnk_data_7_0_len 8
+#define reg_ofdm2lnk_data_7_0_lsb 0
+#define xd_p_reg_ofdm2lnk_data_15_8 (*(volatile byte xdata *) 0xFB97)
+#define    p_reg_ofdm2lnk_data_15_8 0xFB97
+#define reg_ofdm2lnk_data_15_8_pos 0
+#define reg_ofdm2lnk_data_15_8_len 8
+#define reg_ofdm2lnk_data_15_8_lsb 8
+#define xd_p_reg_ofdm2lnk_data_23_16    (*(volatile byte xdata *) 0xFB98)
+#define    p_reg_ofdm2lnk_data_23_16    0xFB98
+#define reg_ofdm2lnk_data_23_16_pos 0
+#define reg_ofdm2lnk_data_23_16_len 8
+#define reg_ofdm2lnk_data_23_16_lsb 16
+#define xd_p_reg_ofdm2lnk_data_31_24    (*(volatile byte xdata *) 0xFB99)
+#define    p_reg_ofdm2lnk_data_31_24    0xFB99
+#define reg_ofdm2lnk_data_31_24_pos 0
+#define reg_ofdm2lnk_data_31_24_len 8
+#define reg_ofdm2lnk_data_31_24_lsb 24
+#define xd_p_reg_ofdm2lnk_data_39_32    (*(volatile byte xdata *) 0xFB9A)
+#define    p_reg_ofdm2lnk_data_39_32    0xFB9A
+#define reg_ofdm2lnk_data_39_32_pos 0
+#define reg_ofdm2lnk_data_39_32_len 8
+#define reg_ofdm2lnk_data_39_32_lsb 32
+#define xd_p_reg_ofdm2lnk_data_47_40    (*(volatile byte xdata *) 0xFB9B)
+#define    p_reg_ofdm2lnk_data_47_40    0xFB9B
+#define reg_ofdm2lnk_data_47_40_pos 0
+#define reg_ofdm2lnk_data_47_40_len 8
+#define reg_ofdm2lnk_data_47_40_lsb 40
+#define xd_p_reg_ofdm2lnk_data_55_48    (*(volatile byte xdata *) 0xFB9C)
+#define    p_reg_ofdm2lnk_data_55_48    0xFB9C
+#define reg_ofdm2lnk_data_55_48_pos 0
+#define reg_ofdm2lnk_data_55_48_len 8
+#define reg_ofdm2lnk_data_55_48_lsb 48
+#define xd_p_reg_ofdm2lnk_data_63_56    (*(volatile byte xdata *) 0xFB9D)
+#define    p_reg_ofdm2lnk_data_63_56    0xFB9D
+#define reg_ofdm2lnk_data_63_56_pos 0
+#define reg_ofdm2lnk_data_63_56_len 8
+#define reg_ofdm2lnk_data_63_56_lsb 56
+#define xd_p_reg_lnktoofdm_data_7_0 (*(volatile byte xdata *) 0xFB9E)
+#define    p_reg_lnktoofdm_data_7_0 0xFB9E
+#define reg_lnktoofdm_data_7_0_pos 0
+#define reg_lnktoofdm_data_7_0_len 8
+#define reg_lnktoofdm_data_7_0_lsb 0
+#define xd_p_reg_lnktoofdm_data_15_8    (*(volatile byte xdata *) 0xFB9F)
+#define    p_reg_lnktoofdm_data_15_8    0xFB9F
+#define reg_lnktoofdm_data_15_8_pos 0
+#define reg_lnktoofdm_data_15_8_len 8
+#define reg_lnktoofdm_data_15_8_lsb 8
+#define xd_p_reg_lnktoofdm_data_23_16   (*(volatile byte xdata *) 0xFBA0)
+#define    p_reg_lnktoofdm_data_23_16   0xFBA0
+#define reg_lnktoofdm_data_23_16_pos 0
+#define reg_lnktoofdm_data_23_16_len 8
+#define reg_lnktoofdm_data_23_16_lsb 16
+#define xd_p_reg_lnktoofdm_data_31_24   (*(volatile byte xdata *) 0xFBA1)
+#define    p_reg_lnktoofdm_data_31_24   0xFBA1
+#define reg_lnktoofdm_data_31_24_pos 0
+#define reg_lnktoofdm_data_31_24_len 8
+#define reg_lnktoofdm_data_31_24_lsb 24
+#define xd_p_reg_lnktoofdm_data_39_32   (*(volatile byte xdata *) 0xFBA2)
+#define    p_reg_lnktoofdm_data_39_32   0xFBA2
+#define reg_lnktoofdm_data_39_32_pos 0
+#define reg_lnktoofdm_data_39_32_len 8
+#define reg_lnktoofdm_data_39_32_lsb 32
+#define xd_p_reg_lnktoofdm_data_47_40   (*(volatile byte xdata *) 0xFBA3)
+#define    p_reg_lnktoofdm_data_47_40   0xFBA3
+#define reg_lnktoofdm_data_47_40_pos 0
+#define reg_lnktoofdm_data_47_40_len 8
+#define reg_lnktoofdm_data_47_40_lsb 40
+#define xd_p_reg_lnktoofdm_data_55_48   (*(volatile byte xdata *) 0xFBA4)
+#define    p_reg_lnktoofdm_data_55_48   0xFBA4
+#define reg_lnktoofdm_data_55_48_pos 0
+#define reg_lnktoofdm_data_55_48_len 8
+#define reg_lnktoofdm_data_55_48_lsb 48
+#define xd_p_reg_lnktoofdm_data_63_56   (*(volatile byte xdata *) 0xFBA5)
+#define    p_reg_lnktoofdm_data_63_56   0xFBA5
+#define reg_lnktoofdm_data_63_56_pos 0
+#define reg_lnktoofdm_data_63_56_len 8
+#define reg_lnktoofdm_data_63_56_lsb 56
+#define xd_p_reg_dbgif32_sel    (*(volatile byte xdata *) 0xFBA6)
+#define    p_reg_dbgif32_sel    0xFBA6
+#define reg_dbgif32_sel_pos 0
+#define reg_dbgif32_sel_len 2
+#define reg_dbgif32_sel_lsb 0
+#define xd_p_reg_dyn1_clk   (*(volatile byte xdata *) 0xFBA7)
+#define    p_reg_dyn1_clk   0xFBA7
+#define reg_dyn1_clk_pos 0
+#define reg_dyn1_clk_len 1
+#define reg_dyn1_clk_lsb 0
+#define xd_p_reg_dyn0_clk   (*(volatile byte xdata *) 0xFBA8)
+#define    p_reg_dyn0_clk   0xFBA8
+#define reg_dyn0_clk_pos 0
+#define reg_dyn0_clk_len 1
+#define reg_dyn0_clk_lsb 0
+#define xd_p_reg_free_clk   (*(volatile byte xdata *) 0xFBA9)
+#define    p_reg_free_clk   0xFBA9
+#define reg_free_clk_pos 0
+#define reg_free_clk_len 1
+#define reg_free_clk_lsb 0
+#define xd_p_reg_ofdm_stick_mem_end_7_0 (*(volatile byte xdata *) 0xFBAD)
+#define    p_reg_ofdm_stick_mem_end_7_0 0xFBAD
+#define reg_ofdm_stick_mem_end_7_0_pos 0
+#define reg_ofdm_stick_mem_end_7_0_len 8
+#define reg_ofdm_stick_mem_end_7_0_lsb 0
+#define xd_p_reg_ofdm_stick_mem_end_15_8    (*(volatile byte xdata *) 0xFBAE)
+#define    p_reg_ofdm_stick_mem_end_15_8    0xFBAE
+#define reg_ofdm_stick_mem_end_15_8_pos 0
+#define reg_ofdm_stick_mem_end_15_8_len 8
+#define reg_ofdm_stick_mem_end_15_8_lsb 8
+#define xd_p_reg_ofdm_cpu_reset (*(volatile byte xdata *) 0xFBAF)
+#define    p_reg_ofdm_cpu_reset 0xFBAF
+#define reg_ofdm_cpu_reset_pos 0
+#define reg_ofdm_cpu_reset_len 1
+#define reg_ofdm_cpu_reset_lsb 0
+#define xd_p_reg_ofdm_bank_float_en (*(volatile byte xdata *) 0xFBB0)
+#define    p_reg_ofdm_bank_float_en 0xFBB0
+#define reg_ofdm_bank_float_en_pos 0
+#define reg_ofdm_bank_float_en_len 1
+#define reg_ofdm_bank_float_en_lsb 0
+#define xd_p_reg_ofdm_bank_float_start  (*(volatile byte xdata *) 0xFBB1)
+#define    p_reg_ofdm_bank_float_start  0xFBB1
+#define reg_ofdm_bank_float_start_pos 0
+#define reg_ofdm_bank_float_start_len 8
+#define reg_ofdm_bank_float_start_lsb 0
+#define xd_p_reg_ofdm_bank_float_stop   (*(volatile byte xdata *) 0xFBB2)
+#define    p_reg_ofdm_bank_float_stop   0xFBB2
+#define reg_ofdm_bank_float_stop_pos 0
+#define reg_ofdm_bank_float_stop_len 8
+#define reg_ofdm_bank_float_stop_lsb 0
+#define xd_r_ofsm_bond0_i   (*(volatile byte xdata *) 0xFBB3)
+#define    r_ofsm_bond0_i   0xFBB3
+#define ofsm_bond0_i_pos 0
+#define ofsm_bond0_i_len 1
+#define ofsm_bond0_i_lsb 0
+#define xd_r_ofsm_bond1_i   (*(volatile byte xdata *) 0xFBB4)
+#define    r_ofsm_bond1_i   0xFBB4
+#define ofsm_bond1_i_pos 0
+#define ofsm_bond1_i_len 1
+#define ofsm_bond1_i_lsb 0
+#define xd_r_io_mux_pwron_clk_strap (*(volatile byte xdata *) 0xD800)
+#define    r_io_mux_pwron_clk_strap 0xD800
+#define io_mux_pwron_clk_strap_pos 0
+#define io_mux_pwron_clk_strap_len 4
+#define io_mux_pwron_clk_strap_lsb 0
+#define xd_r_io_mux_pwron_mode_strap    (*(volatile byte xdata *) 0xD801)
+#define    r_io_mux_pwron_mode_strap    0xD801
+#define io_mux_pwron_mode_strap_pos 0
+#define io_mux_pwron_mode_strap_len 4
+#define io_mux_pwron_mode_strap_lsb 0
+#define xd_r_io_mux_pwron_hosta (*(volatile byte xdata *) 0xD802)
+#define    r_io_mux_pwron_hosta 0xD802
+#define io_mux_pwron_hosta_pos 0
+#define io_mux_pwron_hosta_len 1
+#define io_mux_pwron_hosta_lsb 0
+#define xd_r_reg_top_revid  (*(volatile byte xdata *) 0xD803)
+#define    r_reg_top_revid  0xD803
+#define reg_top_revid_pos 0
+#define reg_top_revid_len 4
+#define reg_top_revid_lsb 0
+#define xd_r_io_mux_bond0_i (*(volatile byte xdata *) 0xD804)
+#define    r_io_mux_bond0_i 0xD804
+#define io_mux_bond0_i_pos 0
+#define io_mux_bond0_i_len 1
+#define io_mux_bond0_i_lsb 0
+#define xd_r_io_mux_bondu0_i    (*(volatile byte xdata *) 0xD805)
+#define    r_io_mux_bondu0_i    0xD805
+#define io_mux_bondu0_i_pos 0
+#define io_mux_bondu0_i_len 1
+#define io_mux_bondu0_i_lsb 0
+#define xd_p_reg_ofsm_suspend   (*(volatile byte xdata *) 0xD806)
+#define    p_reg_ofsm_suspend   0xD806
+#define reg_ofsm_suspend_pos 0
+#define reg_ofsm_suspend_len 1
+#define reg_ofsm_suspend_lsb 0
+#define xd_p_reg_tslice_off (*(volatile byte xdata *) 0xD807)
+#define    p_reg_tslice_off 0xD807
+#define reg_tslice_off_pos 0
+#define reg_tslice_off_len 1
+#define reg_tslice_off_lsb 0
+#define xd_p_io_mux_wake_int    (*(volatile byte xdata *) 0xD808)
+#define    p_io_mux_wake_int    0xD808
+#define io_mux_wake_int_pos 0
+#define io_mux_wake_int_len 1
+#define io_mux_wake_int_lsb 0
+#define xd_p_reg_top_pwrdw_hwen (*(volatile byte xdata *) 0xD809)
+#define    p_reg_top_pwrdw_hwen 0xD809
+#define reg_top_pwrdw_hwen_pos 0
+#define reg_top_pwrdw_hwen_len 1
+#define reg_top_pwrdw_hwen_lsb 0
+#define xd_p_reg_top_pwrdw_inv  (*(volatile byte xdata *) 0xD80A)
+#define    p_reg_top_pwrdw_inv  0xD80A
+#define reg_top_pwrdw_inv_pos 0
+#define reg_top_pwrdw_inv_len 1
+#define reg_top_pwrdw_inv_lsb 0
+#define xd_p_reg_top_pwrdw  (*(volatile byte xdata *) 0xD80B)
+#define    p_reg_top_pwrdw  0xD80B
+#define reg_top_pwrdw_pos 0
+#define reg_top_pwrdw_len 1
+#define reg_top_pwrdw_lsb 0
+#define xd_p_io_mux_wake_int_en (*(volatile byte xdata *) 0xD80C)
+#define    p_io_mux_wake_int_en 0xD80C
+#define io_mux_wake_int_en_pos 0
+#define io_mux_wake_int_en_len 1
+#define io_mux_wake_int_en_lsb 0
+#define xd_p_io_mux_pwrdw_int   (*(volatile byte xdata *) 0xD80D)
+#define    p_io_mux_pwrdw_int   0xD80D
+#define io_mux_pwrdw_int_pos 0
+#define io_mux_pwrdw_int_len 1
+#define io_mux_pwrdw_int_lsb 0
+#define xd_p_reg_top_adcdly (*(volatile byte xdata *) 0xD80E)
+#define    p_reg_top_adcdly 0xD80E
+#define reg_top_adcdly_pos 0
+#define reg_top_adcdly_len 2
+#define reg_top_adcdly_lsb 0
+#define xd_p_reg_top_debug  (*(volatile byte xdata *) 0xD80F)
+#define    p_reg_top_debug  0xD80F
+#define reg_top_debug_pos 0
+#define reg_top_debug_len 1
+#define reg_top_debug_lsb 0
+#define xd_p_reg_top_pcout  (*(volatile byte xdata *) 0xD810)
+#define    p_reg_top_pcout  0xD810
+#define reg_top_pcout_pos 0
+#define reg_top_pcout_len 1
+#define reg_top_pcout_lsb 0
+#define xd_p_reg_top_rs232  (*(volatile byte xdata *) 0xD811)
+#define    p_reg_top_rs232  0xD811
+#define reg_top_rs232_pos 0
+#define reg_top_rs232_len 1
+#define reg_top_rs232_lsb 0
+#define xd_p_reg_iqmode (*(volatile byte xdata *) 0xD812)
+#define    p_reg_iqmode 0xD812
+#define reg_iqmode_pos 0
+#define reg_iqmode_len 1
+#define reg_iqmode_lsb 0
+#define xd_p_reg_top_rstfd  (*(volatile byte xdata *) 0xD813)
+#define    p_reg_top_rstfd  0xD813
+#define reg_top_rstfd_pos 0
+#define reg_top_rstfd_len 1
+#define reg_top_rstfd_lsb 0
+#define xd_p_reg_sdio_clksel    (*(volatile byte xdata *) 0xD814)
+#define    p_reg_sdio_clksel    0xD814
+#define reg_sdio_clksel_pos 0
+#define reg_sdio_clksel_len 1
+#define reg_sdio_clksel_lsb 0
+#define xd_p_reg_utmi_clksel    (*(volatile byte xdata *) 0xD815)
+#define    p_reg_utmi_clksel    0xD815
+#define reg_utmi_clksel_pos 0
+#define reg_utmi_clksel_len 8
+#define reg_utmi_clksel_lsb 0
+#define xd_p_reg_top_suscnt (*(volatile byte xdata *) 0xD816)
+#define    p_reg_top_suscnt 0xD816
+#define reg_top_suscnt_pos 0
+#define reg_top_suscnt_len 2
+#define reg_top_suscnt_lsb 0
+#define xd_p_reg_top_dist2f (*(volatile byte xdata *) 0xD817)
+#define    p_reg_top_dist2f 0xD817
+#define reg_top_dist2f_pos 0
+#define reg_top_dist2f_len 1
+#define reg_top_dist2f_lsb 0
+#define xd_p_reg_top_extusb (*(volatile byte xdata *) 0xD818)
+#define    p_reg_top_extusb 0xD818
+#define reg_top_extusb_pos 0
+#define reg_top_extusb_len 1
+#define reg_top_extusb_lsb 0
+#define xd_p_reg_top_adcfifo    (*(volatile byte xdata *) 0xD819)
+#define    p_reg_top_adcfifo    0xD819
+#define reg_top_adcfifo_pos 0
+#define reg_top_adcfifo_len 1
+#define reg_top_adcfifo_lsb 0
+#define xd_p_reg_top_clkoen (*(volatile byte xdata *) 0xD81A)
+#define    p_reg_top_clkoen 0xD81A
+#define reg_top_clkoen_pos 0
+#define reg_top_clkoen_len 1
+#define reg_top_clkoen_lsb 0
+#define xd_p_reg_top_stpck  (*(volatile byte xdata *) 0xD81B)
+#define    p_reg_top_stpck  0xD81B
+#define reg_top_stpck_pos 0
+#define reg_top_stpck_len 1
+#define reg_top_stpck_lsb 0
+#define xd_p_reg_top_freeck (*(volatile byte xdata *) 0xD81C)
+#define    p_reg_top_freeck 0xD81C
+#define reg_top_freeck_pos 0
+#define reg_top_freeck_len 1
+#define reg_top_freeck_lsb 0
+#define xd_p_reg_top_dio_sel    (*(volatile byte xdata *) 0xD81D)
+#define    p_reg_top_dio_sel    0xD81D
+#define reg_top_dio_sel_pos 0
+#define reg_top_dio_sel_len 1
+#define reg_top_dio_sel_lsb 0
+#define xd_p_reg_top_int_en (*(volatile byte xdata *) 0xD81E)
+#define    p_reg_top_int_en 0xD81E
+#define reg_top_int_en_pos 0
+#define reg_top_int_en_len 1
+#define reg_top_int_en_lsb 0
+#define xd_p_reg_top_int_inv    (*(volatile byte xdata *) 0xD81F)
+#define    p_reg_top_int_inv    0xD81F
+#define reg_top_int_inv_pos 0
+#define reg_top_int_inv_len 1
+#define reg_top_int_inv_lsb 0
+#define xd_p_reg_tsip_clk_inv   (*(volatile byte xdata *) 0xD820)
+#define    p_reg_tsip_clk_inv   0xD820
+#define reg_tsip_clk_inv_pos 0
+#define reg_tsip_clk_inv_len 1
+#define reg_tsip_clk_inv_lsb 0
+#define xd_p_reg_ts_clk_inv (*(volatile byte xdata *) 0xD821)
+#define    p_reg_ts_clk_inv 0xD821
+#define reg_ts_clk_inv_pos 0
+#define reg_ts_clk_inv_len 1
+#define reg_ts_clk_inv_lsb 0
+#define xd_p_reg_ts_hybrid  (*(volatile byte xdata *) 0xD822)
+#define    p_reg_ts_hybrid  0xD822
+#define reg_ts_hybrid_pos 0
+#define reg_ts_hybrid_len 1
+#define reg_ts_hybrid_lsb 0
+#define xd_p_reg_ccir_sel   (*(volatile byte xdata *) 0xD823)
+#define    p_reg_ccir_sel   0xD823
+#define reg_ccir_sel_pos 0
+#define reg_ccir_sel_len 4
+#define reg_ccir_sel_lsb 0
+#define xd_p_reg_top_sys_gate   (*(volatile byte xdata *) 0xD824)
+#define    p_reg_top_sys_gate   0xD824
+#define reg_top_sys_gate_pos 0
+#define reg_top_sys_gate_len 1
+#define reg_top_sys_gate_lsb 0
+#define xd_p_reg_top_padpu  (*(volatile byte xdata *) 0xD825)
+#define    p_reg_top_padpu  0xD825
+#define reg_top_padpu_pos 0
+#define reg_top_padpu_len 1
+#define reg_top_padpu_lsb 0
+#define xd_p_reg_top_padpd  (*(volatile byte xdata *) 0xD826)
+#define    p_reg_top_padpd  0xD826
+#define reg_top_padpd_pos 0
+#define reg_top_padpd_len 1
+#define reg_top_padpd_lsb 0
+#define xd_p_reg_top_padodpu    (*(volatile byte xdata *) 0xD827)
+#define    p_reg_top_padodpu    0xD827
+#define reg_top_padodpu_pos 0
+#define reg_top_padodpu_len 1
+#define reg_top_padodpu_lsb 0
+#define xd_p_reg_top_thirdodpu  (*(volatile byte xdata *) 0xD828)
+#define    p_reg_top_thirdodpu  0xD828
+#define reg_top_thirdodpu_pos 0
+#define reg_top_thirdodpu_len 1
+#define reg_top_thirdodpu_lsb 0
+#define xd_p_reg_top_agc_od (*(volatile byte xdata *) 0xD829)
+#define    p_reg_top_agc_od 0xD829
+#define reg_top_agc_od_pos 0
+#define reg_top_agc_od_len 1
+#define reg_top_agc_od_lsb 0
+#define xd_p_reg_top_padmpdr2   (*(volatile byte xdata *) 0xD82A)
+#define    p_reg_top_padmpdr2   0xD82A
+#define reg_top_padmpdr2_pos 0
+#define reg_top_padmpdr2_len 1
+#define reg_top_padmpdr2_lsb 0
+#define xd_p_reg_top_padmpdr4   (*(volatile byte xdata *) 0xD82B)
+#define    p_reg_top_padmpdr4   0xD82B
+#define reg_top_padmpdr4_pos 0
+#define reg_top_padmpdr4_len 1
+#define reg_top_padmpdr4_lsb 0
+#define xd_p_reg_top_padmpdr8   (*(volatile byte xdata *) 0xD82C)
+#define    p_reg_top_padmpdr8   0xD82C
+#define reg_top_padmpdr8_pos 0
+#define reg_top_padmpdr8_len 1
+#define reg_top_padmpdr8_lsb 0
+#define xd_p_reg_top_padmpdrsr  (*(volatile byte xdata *) 0xD82D)
+#define    p_reg_top_padmpdrsr  0xD82D
+#define reg_top_padmpdrsr_pos 0
+#define reg_top_padmpdrsr_len 1
+#define reg_top_padmpdrsr_lsb 0
+#define xd_p_reg_top_padmppu    (*(volatile byte xdata *) 0xD82E)
+#define    p_reg_top_padmppu    0xD82E
+#define reg_top_padmppu_pos 0
+#define reg_top_padmppu_len 1
+#define reg_top_padmppu_lsb 0
+#define xd_p_reg_top_padmppd    (*(volatile byte xdata *) 0xD82F)
+#define    p_reg_top_padmppd    0xD82F
+#define reg_top_padmppd_pos 0
+#define reg_top_padmppd_len 1
+#define reg_top_padmppd_lsb 0
+#define xd_p_reg_top_padmiscdr2 (*(volatile byte xdata *) 0xD830)
+#define    p_reg_top_padmiscdr2 0xD830
+#define reg_top_padmiscdr2_pos 0
+#define reg_top_padmiscdr2_len 1
+#define reg_top_padmiscdr2_lsb 0
+#define xd_p_reg_top_padmiscdr4 (*(volatile byte xdata *) 0xD831)
+#define    p_reg_top_padmiscdr4 0xD831
+#define reg_top_padmiscdr4_pos 0
+#define reg_top_padmiscdr4_len 1
+#define reg_top_padmiscdr4_lsb 0
+#define xd_p_reg_top_padmiscdr8 (*(volatile byte xdata *) 0xD832)
+#define    p_reg_top_padmiscdr8 0xD832
+#define reg_top_padmiscdr8_pos 0
+#define reg_top_padmiscdr8_len 1
+#define reg_top_padmiscdr8_lsb 0
+#define xd_p_reg_top_padmiscdrsr    (*(volatile byte xdata *) 0xD833)
+#define    p_reg_top_padmiscdrsr    0xD833
+#define reg_top_padmiscdrsr_pos 0
+#define reg_top_padmiscdrsr_len 1
+#define reg_top_padmiscdrsr_lsb 0
+#define xd_p_reg_top_padmiscpu  (*(volatile byte xdata *) 0xD834)
+#define    p_reg_top_padmiscpu  0xD834
+#define reg_top_padmiscpu_pos 0
+#define reg_top_padmiscpu_len 1
+#define reg_top_padmiscpu_lsb 0
+#define xd_p_reg_top_padmiscpd  (*(volatile byte xdata *) 0xD835)
+#define    p_reg_top_padmiscpd  0xD835
+#define reg_top_padmiscpd_pos 0
+#define reg_top_padmiscpd_len 1
+#define reg_top_padmiscpd_lsb 0
+#define xd_p_reg_host_b0_smt    (*(volatile byte xdata *) 0xD836)
+#define    p_reg_host_b0_smt    0xD836
+#define reg_host_b0_smt_pos 0
+#define reg_host_b0_smt_len 1
+#define reg_host_b0_smt_lsb 0
+#define xd_p_reg_host_b1_smt    (*(volatile byte xdata *) 0xD837)
+#define    p_reg_host_b1_smt    0xD837
+#define reg_host_b1_smt_pos 0
+#define reg_host_b1_smt_len 1
+#define reg_host_b1_smt_lsb 0
+#define xd_p_reg_host_b2_smt    (*(volatile byte xdata *) 0xD838)
+#define    p_reg_host_b2_smt    0xD838
+#define reg_host_b2_smt_pos 0
+#define reg_host_b2_smt_len 1
+#define reg_host_b2_smt_lsb 0
+#define xd_p_reg_host_b3_smt    (*(volatile byte xdata *) 0xD839)
+#define    p_reg_host_b3_smt    0xD839
+#define reg_host_b3_smt_pos 0
+#define reg_host_b3_smt_len 1
+#define reg_host_b3_smt_lsb 0
+#define xd_p_reg_host_b4_smt    (*(volatile byte xdata *) 0xD83A)
+#define    p_reg_host_b4_smt    0xD83A
+#define reg_host_b4_smt_pos 0
+#define reg_host_b4_smt_len 1
+#define reg_host_b4_smt_lsb 0
+#define xd_p_reg_host_b5_smt    (*(volatile byte xdata *) 0xD83B)
+#define    p_reg_host_b5_smt    0xD83B
+#define reg_host_b5_smt_pos 0
+#define reg_host_b5_smt_len 1
+#define reg_host_b5_smt_lsb 0
+#define xd_p_reg_host_b6_smt    (*(volatile byte xdata *) 0xD83C)
+#define    p_reg_host_b6_smt    0xD83C
+#define reg_host_b6_smt_pos 0
+#define reg_host_b6_smt_len 1
+#define reg_host_b6_smt_lsb 0
+#define xd_p_reg_host_b7_smt    (*(volatile byte xdata *) 0xD83D)
+#define    p_reg_host_b7_smt    0xD83D
+#define reg_host_b7_smt_pos 0
+#define reg_host_b7_smt_len 1
+#define reg_host_b7_smt_lsb 0
+#define xd_p_reg_host_b8_smt    (*(volatile byte xdata *) 0xD83E)
+#define    p_reg_host_b8_smt    0xD83E
+#define reg_host_b8_smt_pos 0
+#define reg_host_b8_smt_len 1
+#define reg_host_b8_smt_lsb 0
+#define xd_p_reg_host_b9_smt    (*(volatile byte xdata *) 0xD83F)
+#define    p_reg_host_b9_smt    0xD83F
+#define reg_host_b9_smt_pos 0
+#define reg_host_b9_smt_len 1
+#define reg_host_b9_smt_lsb 0
+#define xd_p_reg_host_b10_smt   (*(volatile byte xdata *) 0xD840)
+#define    p_reg_host_b10_smt   0xD840
+#define reg_host_b10_smt_pos 0
+#define reg_host_b10_smt_len 1
+#define reg_host_b10_smt_lsb 0
+#define xd_p_reg_host_b11_smt   (*(volatile byte xdata *) 0xD841)
+#define    p_reg_host_b11_smt   0xD841
+#define reg_host_b11_smt_pos 0
+#define reg_host_b11_smt_len 1
+#define reg_host_b11_smt_lsb 0
+#define xd_p_reg_host_a0_smt    (*(volatile byte xdata *) 0xD842)
+#define    p_reg_host_a0_smt    0xD842
+#define reg_host_a0_smt_pos 0
+#define reg_host_a0_smt_len 1
+#define reg_host_a0_smt_lsb 0
+#define xd_p_reg_host_a1_smt    (*(volatile byte xdata *) 0xD843)
+#define    p_reg_host_a1_smt    0xD843
+#define reg_host_a1_smt_pos 0
+#define reg_host_a1_smt_len 1
+#define reg_host_a1_smt_lsb 0
+#define xd_p_reg_host_a2_smt    (*(volatile byte xdata *) 0xD844)
+#define    p_reg_host_a2_smt    0xD844
+#define reg_host_a2_smt_pos 0
+#define reg_host_a2_smt_len 1
+#define reg_host_a2_smt_lsb 0
+#define xd_p_reg_host_a3_smt    (*(volatile byte xdata *) 0xD845)
+#define    p_reg_host_a3_smt    0xD845
+#define reg_host_a3_smt_pos 0
+#define reg_host_a3_smt_len 1
+#define reg_host_a3_smt_lsb 0
+#define xd_p_reg_host_a4_smt    (*(volatile byte xdata *) 0xD846)
+#define    p_reg_host_a4_smt    0xD846
+#define reg_host_a4_smt_pos 0
+#define reg_host_a4_smt_len 1
+#define reg_host_a4_smt_lsb 0
+#define xd_p_reg_host_a5_smt    (*(volatile byte xdata *) 0xD847)
+#define    p_reg_host_a5_smt    0xD847
+#define reg_host_a5_smt_pos 0
+#define reg_host_a5_smt_len 1
+#define reg_host_a5_smt_lsb 0
+#define xd_p_reg_host_a6_smt    (*(volatile byte xdata *) 0xD848)
+#define    p_reg_host_a6_smt    0xD848
+#define reg_host_a6_smt_pos 0
+#define reg_host_a6_smt_len 1
+#define reg_host_a6_smt_lsb 0
+#define xd_p_reg_host_a7_smt    (*(volatile byte xdata *) 0xD849)
+#define    p_reg_host_a7_smt    0xD849
+#define reg_host_a7_smt_pos 0
+#define reg_host_a7_smt_len 1
+#define reg_host_a7_smt_lsb 0
+#define xd_p_reg_host_a8_smt    (*(volatile byte xdata *) 0xD84A)
+#define    p_reg_host_a8_smt    0xD84A
+#define reg_host_a8_smt_pos 0
+#define reg_host_a8_smt_len 1
+#define reg_host_a8_smt_lsb 0
+#define xd_p_reg_host_a9_smt    (*(volatile byte xdata *) 0xD84B)
+#define    p_reg_host_a9_smt    0xD84B
+#define reg_host_a9_smt_pos 0
+#define reg_host_a9_smt_len 1
+#define reg_host_a9_smt_lsb 0
+#define xd_p_reg_host_a10_smt   (*(volatile byte xdata *) 0xD84C)
+#define    p_reg_host_a10_smt   0xD84C
+#define reg_host_a10_smt_pos 0
+#define reg_host_a10_smt_len 1
+#define reg_host_a10_smt_lsb 0
+#define xd_p_reg_host_a11_smt   (*(volatile byte xdata *) 0xD84D)
+#define    p_reg_host_a11_smt   0xD84D
+#define reg_host_a11_smt_pos 0
+#define reg_host_a11_smt_len 1
+#define reg_host_a11_smt_lsb 0
+#define xd_p_reg_testmode_pds   (*(volatile byte xdata *) 0xD84E)
+#define    p_reg_testmode_pds   0xD84E
+#define reg_testmode_pds_pos 0
+#define reg_testmode_pds_len 3
+#define reg_testmode_pds_lsb 0
+#define xd_p_reg_debug31_pds    (*(volatile byte xdata *) 0xD84F)
+#define    p_reg_debug31_pds    0xD84F
+#define reg_debug31_pds_pos 0
+#define reg_debug31_pds_len 3
+#define reg_debug31_pds_lsb 0
+#define xd_p_reg_debug30_pds    (*(volatile byte xdata *) 0xD850)
+#define    p_reg_debug30_pds    0xD850
+#define reg_debug30_pds_pos 0
+#define reg_debug30_pds_len 3
+#define reg_debug30_pds_lsb 0
+#define xd_p_reg_debug29_pds    (*(volatile byte xdata *) 0xD851)
+#define    p_reg_debug29_pds    0xD851
+#define reg_debug29_pds_pos 0
+#define reg_debug29_pds_len 3
+#define reg_debug29_pds_lsb 0
+#define xd_p_reg_debug28_pds    (*(volatile byte xdata *) 0xD852)
+#define    p_reg_debug28_pds    0xD852
+#define reg_debug28_pds_pos 0
+#define reg_debug28_pds_len 3
+#define reg_debug28_pds_lsb 0
+#define xd_p_reg_debug27_pds    (*(volatile byte xdata *) 0xD853)
+#define    p_reg_debug27_pds    0xD853
+#define reg_debug27_pds_pos 0
+#define reg_debug27_pds_len 3
+#define reg_debug27_pds_lsb 0
+#define xd_p_reg_debug26_pds    (*(volatile byte xdata *) 0xD854)
+#define    p_reg_debug26_pds    0xD854
+#define reg_debug26_pds_pos 0
+#define reg_debug26_pds_len 3
+#define reg_debug26_pds_lsb 0
+#define xd_p_reg_debug25_pds    (*(volatile byte xdata *) 0xD855)
+#define    p_reg_debug25_pds    0xD855
+#define reg_debug25_pds_pos 0
+#define reg_debug25_pds_len 3
+#define reg_debug25_pds_lsb 0
+#define xd_p_reg_debug24_pds    (*(volatile byte xdata *) 0xD856)
+#define    p_reg_debug24_pds    0xD856
+#define reg_debug24_pds_pos 0
+#define reg_debug24_pds_len 3
+#define reg_debug24_pds_lsb 0
+#define xd_p_reg_debug23_pds    (*(volatile byte xdata *) 0xD857)
+#define    p_reg_debug23_pds    0xD857
+#define reg_debug23_pds_pos 0
+#define reg_debug23_pds_len 3
+#define reg_debug23_pds_lsb 0
+#define xd_p_reg_debug22_pds    (*(volatile byte xdata *) 0xD858)
+#define    p_reg_debug22_pds    0xD858
+#define reg_debug22_pds_pos 0
+#define reg_debug22_pds_len 3
+#define reg_debug22_pds_lsb 0
+#define xd_p_reg_gpioh1_pds (*(volatile byte xdata *) 0xD859)
+#define    p_reg_gpioh1_pds 0xD859
+#define reg_gpioh1_pds_pos 0
+#define reg_gpioh1_pds_len 3
+#define reg_gpioh1_pds_lsb 0
+#define xd_p_reg_gpioh2_pds (*(volatile byte xdata *) 0xD85A)
+#define    p_reg_gpioh2_pds 0xD85A
+#define reg_gpioh2_pds_pos 0
+#define reg_gpioh2_pds_len 3
+#define reg_gpioh2_pds_lsb 0
+#define xd_p_reg_gpioh3_pds (*(volatile byte xdata *) 0xD85B)
+#define    p_reg_gpioh3_pds 0xD85B
+#define reg_gpioh3_pds_pos 0
+#define reg_gpioh3_pds_len 3
+#define reg_gpioh3_pds_lsb 0
+#define xd_p_reg_gpioh4_pds (*(volatile byte xdata *) 0xD85C)
+#define    p_reg_gpioh4_pds 0xD85C
+#define reg_gpioh4_pds_pos 0
+#define reg_gpioh4_pds_len 3
+#define reg_gpioh4_pds_lsb 0
+#define xd_p_reg_iosda_pds  (*(volatile byte xdata *) 0xD85D)
+#define    p_reg_iosda_pds  0xD85D
+#define reg_iosda_pds_pos 0
+#define reg_iosda_pds_len 3
+#define reg_iosda_pds_lsb 0
+#define xd_p_reg_ioscl_pds  (*(volatile byte xdata *) 0xD85E)
+#define    p_reg_ioscl_pds  0xD85E
+#define reg_ioscl_pds_pos 0
+#define reg_ioscl_pds_len 3
+#define reg_ioscl_pds_lsb 0
+#define xd_p_reg_gpioh5_pds (*(volatile byte xdata *) 0xD85F)
+#define    p_reg_gpioh5_pds 0xD85F
+#define reg_gpioh5_pds_pos 0
+#define reg_gpioh5_pds_len 3
+#define reg_gpioh5_pds_lsb 0
+#define xd_p_reg_bond0_pds  (*(volatile byte xdata *) 0xD860)
+#define    p_reg_bond0_pds  0xD860
+#define reg_bond0_pds_pos 0
+#define reg_bond0_pds_len 3
+#define reg_bond0_pds_lsb 0
+#define xd_p_reg_i2caddr6_pds   (*(volatile byte xdata *) 0xD861)
+#define    p_reg_i2caddr6_pds   0xD861
+#define reg_i2caddr6_pds_pos 0
+#define reg_i2caddr6_pds_len 3
+#define reg_i2caddr6_pds_lsb 0
+#define xd_p_reg_i2caddr5_pds   (*(volatile byte xdata *) 0xD862)
+#define    p_reg_i2caddr5_pds   0xD862
+#define reg_i2caddr5_pds_pos 0
+#define reg_i2caddr5_pds_len 3
+#define reg_i2caddr5_pds_lsb 0
+#define xd_p_reg_i2caddr4_pds   (*(volatile byte xdata *) 0xD863)
+#define    p_reg_i2caddr4_pds   0xD863
+#define reg_i2caddr4_pds_pos 0
+#define reg_i2caddr4_pds_len 3
+#define reg_i2caddr4_pds_lsb 0
+#define xd_p_reg_host_a0_pds    (*(volatile byte xdata *) 0xD864)
+#define    p_reg_host_a0_pds    0xD864
+#define reg_host_a0_pds_pos 0
+#define reg_host_a0_pds_len 3
+#define reg_host_a0_pds_lsb 0
+#define xd_p_reg_host_a1_pds    (*(volatile byte xdata *) 0xD865)
+#define    p_reg_host_a1_pds    0xD865
+#define reg_host_a1_pds_pos 0
+#define reg_host_a1_pds_len 3
+#define reg_host_a1_pds_lsb 0
+#define xd_p_reg_debug21_pds    (*(volatile byte xdata *) 0xD866)
+#define    p_reg_debug21_pds    0xD866
+#define reg_debug21_pds_pos 0
+#define reg_debug21_pds_len 3
+#define reg_debug21_pds_lsb 0
+#define xd_p_reg_debug20_pds    (*(volatile byte xdata *) 0xD867)
+#define    p_reg_debug20_pds    0xD867
+#define reg_debug20_pds_pos 0
+#define reg_debug20_pds_len 3
+#define reg_debug20_pds_lsb 0
+#define xd_p_reg_debug19_pds    (*(volatile byte xdata *) 0xD868)
+#define    p_reg_debug19_pds    0xD868
+#define reg_debug19_pds_pos 0
+#define reg_debug19_pds_len 3
+#define reg_debug19_pds_lsb 0
+#define xd_p_reg_debug18_pds    (*(volatile byte xdata *) 0xD869)
+#define    p_reg_debug18_pds    0xD869
+#define reg_debug18_pds_pos 0
+#define reg_debug18_pds_len 3
+#define reg_debug18_pds_lsb 0
+#define xd_p_reg_debug17_pds    (*(volatile byte xdata *) 0xD86A)
+#define    p_reg_debug17_pds    0xD86A
+#define reg_debug17_pds_pos 0
+#define reg_debug17_pds_len 3
+#define reg_debug17_pds_lsb 0
+#define xd_p_reg_host_a2_pds    (*(volatile byte xdata *) 0xD86B)
+#define    p_reg_host_a2_pds    0xD86B
+#define reg_host_a2_pds_pos 0
+#define reg_host_a2_pds_len 3
+#define reg_host_a2_pds_lsb 0
+#define xd_p_reg_host_a3_pds    (*(volatile byte xdata *) 0xD86C)
+#define    p_reg_host_a3_pds    0xD86C
+#define reg_host_a3_pds_pos 0
+#define reg_host_a3_pds_len 3
+#define reg_host_a3_pds_lsb 0
+#define xd_p_reg_host_a4_pds    (*(volatile byte xdata *) 0xD86D)
+#define    p_reg_host_a4_pds    0xD86D
+#define reg_host_a4_pds_pos 0
+#define reg_host_a4_pds_len 3
+#define reg_host_a4_pds_lsb 0
+#define xd_p_reg_host_a5_pds    (*(volatile byte xdata *) 0xD86E)
+#define    p_reg_host_a5_pds    0xD86E
+#define reg_host_a5_pds_pos 0
+#define reg_host_a5_pds_len 3
+#define reg_host_a5_pds_lsb 0
+#define xd_p_reg_host_a6_pds    (*(volatile byte xdata *) 0xD86F)
+#define    p_reg_host_a6_pds    0xD86F
+#define reg_host_a6_pds_pos 0
+#define reg_host_a6_pds_len 3
+#define reg_host_a6_pds_lsb 0
+#define xd_p_reg_p160sel_pds    (*(volatile byte xdata *) 0xD870)
+#define    p_reg_p160sel_pds    0xD870
+#define reg_p160sel_pds_pos 0
+#define reg_p160sel_pds_len 3
+#define reg_p160sel_pds_lsb 0
+#define xd_p_reg_gpioh13_pds    (*(volatile byte xdata *) 0xD871)
+#define    p_reg_gpioh13_pds    0xD871
+#define reg_gpioh13_pds_pos 0
+#define reg_gpioh13_pds_len 3
+#define reg_gpioh13_pds_lsb 0
+#define xd_p_reg_gpioh12_pds    (*(volatile byte xdata *) 0xD872)
+#define    p_reg_gpioh12_pds    0xD872
+#define reg_gpioh12_pds_pos 0
+#define reg_gpioh12_pds_len 3
+#define reg_gpioh12_pds_lsb 0
+#define xd_p_reg_gpioh11_pds    (*(volatile byte xdata *) 0xD873)
+#define    p_reg_gpioh11_pds    0xD873
+#define reg_gpioh11_pds_pos 0
+#define reg_gpioh11_pds_len 3
+#define reg_gpioh11_pds_lsb 0
+#define xd_p_reg_host_a7_pds    (*(volatile byte xdata *) 0xD874)
+#define    p_reg_host_a7_pds    0xD874
+#define reg_host_a7_pds_pos 0
+#define reg_host_a7_pds_len 3
+#define reg_host_a7_pds_lsb 0
+#define xd_p_reg_host_a8_pds    (*(volatile byte xdata *) 0xD875)
+#define    p_reg_host_a8_pds    0xD875
+#define reg_host_a8_pds_pos 0
+#define reg_host_a8_pds_len 3
+#define reg_host_a8_pds_lsb 0
+#define xd_p_reg_host_a9_pds    (*(volatile byte xdata *) 0xD876)
+#define    p_reg_host_a9_pds    0xD876
+#define reg_host_a9_pds_pos 0
+#define reg_host_a9_pds_len 3
+#define reg_host_a9_pds_lsb 0
+#define xd_p_reg_host_a10_pds   (*(volatile byte xdata *) 0xD877)
+#define    p_reg_host_a10_pds   0xD877
+#define reg_host_a10_pds_pos 0
+#define reg_host_a10_pds_len 3
+#define reg_host_a10_pds_lsb 0
+#define xd_p_reg_host_a11_pds   (*(volatile byte xdata *) 0xD878)
+#define    p_reg_host_a11_pds   0xD878
+#define reg_host_a11_pds_pos 0
+#define reg_host_a11_pds_len 3
+#define reg_host_a11_pds_lsb 0
+#define xd_p_reg_bondu0_pds (*(volatile byte xdata *) 0xD879)
+#define    p_reg_bondu0_pds 0xD879
+#define reg_bondu0_pds_pos 0
+#define reg_bondu0_pds_len 3
+#define reg_bondu0_pds_lsb 0
+#define xd_p_reg_host_b0_pds    (*(volatile byte xdata *) 0xD87A)
+#define    p_reg_host_b0_pds    0xD87A
+#define reg_host_b0_pds_pos 0
+#define reg_host_b0_pds_len 3
+#define reg_host_b0_pds_lsb 0
+#define xd_p_reg_host_b1_pds    (*(volatile byte xdata *) 0xD87B)
+#define    p_reg_host_b1_pds    0xD87B
+#define reg_host_b1_pds_pos 0
+#define reg_host_b1_pds_len 3
+#define reg_host_b1_pds_lsb 0
+#define xd_p_reg_host_b2_pds    (*(volatile byte xdata *) 0xD87C)
+#define    p_reg_host_b2_pds    0xD87C
+#define reg_host_b2_pds_pos 0
+#define reg_host_b2_pds_len 3
+#define reg_host_b2_pds_lsb 0
+#define xd_p_reg_host_b3_pds    (*(volatile byte xdata *) 0xD87D)
+#define    p_reg_host_b3_pds    0xD87D
+#define reg_host_b3_pds_pos 0
+#define reg_host_b3_pds_len 3
+#define reg_host_b3_pds_lsb 0
+#define xd_p_reg_host_b4_pds    (*(volatile byte xdata *) 0xD87E)
+#define    p_reg_host_b4_pds    0xD87E
+#define reg_host_b4_pds_pos 0
+#define reg_host_b4_pds_len 3
+#define reg_host_b4_pds_lsb 0
+#define xd_p_reg_host_b5_pds    (*(volatile byte xdata *) 0xD87F)
+#define    p_reg_host_b5_pds    0xD87F
+#define reg_host_b5_pds_pos 0
+#define reg_host_b5_pds_len 3
+#define reg_host_b5_pds_lsb 0
+#define xd_p_reg_host_b6_pds    (*(volatile byte xdata *) 0xD880)
+#define    p_reg_host_b6_pds    0xD880
+#define reg_host_b6_pds_pos 0
+#define reg_host_b6_pds_len 3
+#define reg_host_b6_pds_lsb 0
+#define xd_p_reg_host_b7_pds    (*(volatile byte xdata *) 0xD881)
+#define    p_reg_host_b7_pds    0xD881
+#define reg_host_b7_pds_pos 0
+#define reg_host_b7_pds_len 3
+#define reg_host_b7_pds_lsb 0
+#define xd_p_reg_afe_f12_pds    (*(volatile byte xdata *) 0xD882)
+#define    p_reg_afe_f12_pds    0xD882
+#define reg_afe_f12_pds_pos 0
+#define reg_afe_f12_pds_len 3
+#define reg_afe_f12_pds_lsb 0
+#define xd_p_reg_host_b8_pds    (*(volatile byte xdata *) 0xD883)
+#define    p_reg_host_b8_pds    0xD883
+#define reg_host_b8_pds_pos 0
+#define reg_host_b8_pds_len 3
+#define reg_host_b8_pds_lsb 0
+#define xd_p_reg_host_b9_pds    (*(volatile byte xdata *) 0xD884)
+#define    p_reg_host_b9_pds    0xD884
+#define reg_host_b9_pds_pos 0
+#define reg_host_b9_pds_len 3
+#define reg_host_b9_pds_lsb 0
+#define xd_p_reg_host_b10_pds   (*(volatile byte xdata *) 0xD885)
+#define    p_reg_host_b10_pds   0xD885
+#define reg_host_b10_pds_pos 0
+#define reg_host_b10_pds_len 3
+#define reg_host_b10_pds_lsb 0
+#define xd_p_reg_host_b11_pds   (*(volatile byte xdata *) 0xD886)
+#define    p_reg_host_b11_pds   0xD886
+#define reg_host_b11_pds_pos 0
+#define reg_host_b11_pds_len 3
+#define reg_host_b11_pds_lsb 0
+#define xd_p_reg_debug16_pds    (*(volatile byte xdata *) 0xD887)
+#define    p_reg_debug16_pds    0xD887
+#define reg_debug16_pds_pos 0
+#define reg_debug16_pds_len 3
+#define reg_debug16_pds_lsb 0
+#define xd_p_reg_debug15_pds    (*(volatile byte xdata *) 0xD888)
+#define    p_reg_debug15_pds    0xD888
+#define reg_debug15_pds_pos 0
+#define reg_debug15_pds_len 3
+#define reg_debug15_pds_lsb 0
+#define xd_p_reg_debug14_pds    (*(volatile byte xdata *) 0xD889)
+#define    p_reg_debug14_pds    0xD889
+#define reg_debug14_pds_pos 0
+#define reg_debug14_pds_len 3
+#define reg_debug14_pds_lsb 0
+#define xd_p_reg_debug13_pds    (*(volatile byte xdata *) 0xD88A)
+#define    p_reg_debug13_pds    0xD88A
+#define reg_debug13_pds_pos 0
+#define reg_debug13_pds_len 3
+#define reg_debug13_pds_lsb 0
+#define xd_p_reg_debug12_pds    (*(volatile byte xdata *) 0xD88B)
+#define    p_reg_debug12_pds    0xD88B
+#define reg_debug12_pds_pos 0
+#define reg_debug12_pds_len 3
+#define reg_debug12_pds_lsb 0
+#define xd_p_reg_debug11_pds    (*(volatile byte xdata *) 0xD88C)
+#define    p_reg_debug11_pds    0xD88C
+#define reg_debug11_pds_pos 0
+#define reg_debug11_pds_len 3
+#define reg_debug11_pds_lsb 0
+#define xd_p_reg_debug10_pds    (*(volatile byte xdata *) 0xD88D)
+#define    p_reg_debug10_pds    0xD88D
+#define reg_debug10_pds_pos 0
+#define reg_debug10_pds_len 3
+#define reg_debug10_pds_lsb 0
+#define xd_p_reg_debug9_pds (*(volatile byte xdata *) 0xD88E)
+#define    p_reg_debug9_pds 0xD88E
+#define reg_debug9_pds_pos 0
+#define reg_debug9_pds_len 3
+#define reg_debug9_pds_lsb 0
+#define xd_p_reg_debug8_pds (*(volatile byte xdata *) 0xD88F)
+#define    p_reg_debug8_pds 0xD88F
+#define reg_debug8_pds_pos 0
+#define reg_debug8_pds_len 3
+#define reg_debug8_pds_lsb 0
+#define xd_p_reg_debug7_pds (*(volatile byte xdata *) 0xD890)
+#define    p_reg_debug7_pds 0xD890
+#define reg_debug7_pds_pos 0
+#define reg_debug7_pds_len 3
+#define reg_debug7_pds_lsb 0
+#define xd_p_reg_debug6_pds (*(volatile byte xdata *) 0xD891)
+#define    p_reg_debug6_pds 0xD891
+#define reg_debug6_pds_pos 0
+#define reg_debug6_pds_len 3
+#define reg_debug6_pds_lsb 0
+#define xd_p_reg_debug5_pds (*(volatile byte xdata *) 0xD892)
+#define    p_reg_debug5_pds 0xD892
+#define reg_debug5_pds_pos 0
+#define reg_debug5_pds_len 3
+#define reg_debug5_pds_lsb 0
+#define xd_p_reg_debug4_pds (*(volatile byte xdata *) 0xD893)
+#define    p_reg_debug4_pds 0xD893
+#define reg_debug4_pds_pos 0
+#define reg_debug4_pds_len 3
+#define reg_debug4_pds_lsb 0
+#define xd_p_reg_clko_pds   (*(volatile byte xdata *) 0xD894)
+#define    p_reg_clko_pds   0xD894
+#define reg_clko_pds_pos 0
+#define reg_clko_pds_len 3
+#define reg_clko_pds_lsb 0
+#define xd_p_reg_gpioh6_pds (*(volatile byte xdata *) 0xD895)
+#define    p_reg_gpioh6_pds 0xD895
+#define reg_gpioh6_pds_pos 0
+#define reg_gpioh6_pds_len 3
+#define reg_gpioh6_pds_lsb 0
+#define xd_p_reg_gpioh7_pds (*(volatile byte xdata *) 0xD896)
+#define    p_reg_gpioh7_pds 0xD896
+#define reg_gpioh7_pds_pos 0
+#define reg_gpioh7_pds_len 3
+#define reg_gpioh7_pds_lsb 0
+#define xd_p_reg_gpioh8_pds (*(volatile byte xdata *) 0xD897)
+#define    p_reg_gpioh8_pds 0xD897
+#define reg_gpioh8_pds_pos 0
+#define reg_gpioh8_pds_len 3
+#define reg_gpioh8_pds_lsb 0
+#define xd_p_reg_gpioh9_pds (*(volatile byte xdata *) 0xD898)
+#define    p_reg_gpioh9_pds 0xD898
+#define reg_gpioh9_pds_pos 0
+#define reg_gpioh9_pds_len 3
+#define reg_gpioh9_pds_lsb 0
+#define xd_p_reg_gpioh10_pds    (*(volatile byte xdata *) 0xD899)
+#define    p_reg_gpioh10_pds    0xD899
+#define reg_gpioh10_pds_pos 0
+#define reg_gpioh10_pds_len 3
+#define reg_gpioh10_pds_lsb 0
+#define xd_p_reg_debug3_pds (*(volatile byte xdata *) 0xD89A)
+#define    p_reg_debug3_pds 0xD89A
+#define reg_debug3_pds_pos 0
+#define reg_debug3_pds_len 3
+#define reg_debug3_pds_lsb 0
+#define xd_p_reg_debug2_pds (*(volatile byte xdata *) 0xD89B)
+#define    p_reg_debug2_pds 0xD89B
+#define reg_debug2_pds_pos 0
+#define reg_debug2_pds_len 3
+#define reg_debug2_pds_lsb 0
+#define xd_p_reg_debug1_pds (*(volatile byte xdata *) 0xD89C)
+#define    p_reg_debug1_pds 0xD89C
+#define reg_debug1_pds_pos 0
+#define reg_debug1_pds_len 3
+#define reg_debug1_pds_lsb 0
+#define xd_p_reg_debug0_pds (*(volatile byte xdata *) 0xD89D)
+#define    p_reg_debug0_pds 0xD89D
+#define reg_debug0_pds_pos 0
+#define reg_debug0_pds_len 3
+#define reg_debug0_pds_lsb 0
+#define xd_p_reg_gpiot1_pds (*(volatile byte xdata *) 0xD89E)
+#define    p_reg_gpiot1_pds 0xD89E
+#define reg_gpiot1_pds_pos 0
+#define reg_gpiot1_pds_len 3
+#define reg_gpiot1_pds_lsb 0
+#define xd_p_reg_gpiot2_pds (*(volatile byte xdata *) 0xD89F)
+#define    p_reg_gpiot2_pds 0xD89F
+#define reg_gpiot2_pds_pos 0
+#define reg_gpiot2_pds_len 3
+#define reg_gpiot2_pds_lsb 0
+#define xd_p_reg_rfagc_pds  (*(volatile byte xdata *) 0xD8A0)
+#define    p_reg_rfagc_pds  0xD8A0
+#define reg_rfagc_pds_pos 0
+#define reg_rfagc_pds_len 3
+#define reg_rfagc_pds_lsb 0
+#define xd_p_reg_ifagc_pds  (*(volatile byte xdata *) 0xD8A1)
+#define    p_reg_ifagc_pds  0xD8A1
+#define reg_ifagc_pds_pos 0
+#define reg_ifagc_pds_len 3
+#define reg_ifagc_pds_lsb 0
+#define xd_p_reg_gpiot3_pds (*(volatile byte xdata *) 0xD8A2)
+#define    p_reg_gpiot3_pds 0xD8A2
+#define reg_gpiot3_pds_pos 0
+#define reg_gpiot3_pds_len 3
+#define reg_gpiot3_pds_lsb 0
+#define xd_p_reg_i2caddr3_pds   (*(volatile byte xdata *) 0xD8A3)
+#define    p_reg_i2caddr3_pds   0xD8A3
+#define reg_i2caddr3_pds_pos 0
+#define reg_i2caddr3_pds_len 3
+#define reg_i2caddr3_pds_lsb 0
+#define xd_p_reg_i2caddr2_pds   (*(volatile byte xdata *) 0xD8A4)
+#define    p_reg_i2caddr2_pds   0xD8A4
+#define reg_i2caddr2_pds_pos 0
+#define reg_i2caddr2_pds_len 3
+#define reg_i2caddr2_pds_lsb 0
+#define xd_p_reg_i2caddr1_pds   (*(volatile byte xdata *) 0xD8A5)
+#define    p_reg_i2caddr1_pds   0xD8A5
+#define reg_i2caddr1_pds_pos 0
+#define reg_i2caddr1_pds_len 3
+#define reg_i2caddr1_pds_lsb 0
+#define xd_p_reg_afe_sel33_pds  (*(volatile byte xdata *) 0xD8A6)
+#define    p_reg_afe_sel33_pds  0xD8A6
+#define reg_afe_sel33_pds_pos 0
+#define reg_afe_sel33_pds_len 3
+#define reg_afe_sel33_pds_lsb 0
+#define xd_p_reg_iotunscl_pds   (*(volatile byte xdata *) 0xD8A7)
+#define    p_reg_iotunscl_pds   0xD8A7
+#define reg_iotunscl_pds_pos 0
+#define reg_iotunscl_pds_len 3
+#define reg_iotunscl_pds_lsb 0
+#define xd_p_reg_iotunsda_pds   (*(volatile byte xdata *) 0xD8A8)
+#define    p_reg_iotunsda_pds   0xD8A8
+#define reg_iotunsda_pds_pos 0
+#define reg_iotunsda_pds_len 3
+#define reg_iotunsda_pds_lsb 0
+#define xd_p_reg_rxdofsm_pds    (*(volatile byte xdata *) 0xD8A9)
+#define    p_reg_rxdofsm_pds    0xD8A9
+#define reg_rxdofsm_pds_pos 0
+#define reg_rxdofsm_pds_len 3
+#define reg_rxdofsm_pds_lsb 0
+#define xd_p_reg_txdofsm_pds    (*(volatile byte xdata *) 0xD8AA)
+#define    p_reg_txdofsm_pds    0xD8AA
+#define reg_txdofsm_pds_pos 0
+#define reg_txdofsm_pds_len 3
+#define reg_txdofsm_pds_lsb 0
+#define xd_p_reg_rxdlink_pds    (*(volatile byte xdata *) 0xD8AB)
+#define    p_reg_rxdlink_pds    0xD8AB
+#define reg_rxdlink_pds_pos 0
+#define reg_rxdlink_pds_len 3
+#define reg_rxdlink_pds_lsb 0
+#define xd_p_reg_txdlink_pds    (*(volatile byte xdata *) 0xD8AC)
+#define    p_reg_txdlink_pds    0xD8AC
+#define reg_txdlink_pds_pos 0
+#define reg_txdlink_pds_len 3
+#define reg_txdlink_pds_lsb 0
+#define xd_p_reg_ck_test_pds    (*(volatile byte xdata *) 0xD8AD)
+#define    p_reg_ck_test_pds    0xD8AD
+#define reg_ck_test_pds_pos 0
+#define reg_ck_test_pds_len 3
+#define reg_ck_test_pds_lsb 0
+#define xd_r_reg_top_gpioh1_i   (*(volatile byte xdata *) 0xD8AE)
+#define    r_reg_top_gpioh1_i   0xD8AE
+#define reg_top_gpioh1_i_pos 0
+#define reg_top_gpioh1_i_len 1
+#define reg_top_gpioh1_i_lsb 0
+#define xd_p_reg_top_gpioh1_o   (*(volatile byte xdata *) 0xD8AF)
+#define    p_reg_top_gpioh1_o   0xD8AF
+#define reg_top_gpioh1_o_pos 0
+#define reg_top_gpioh1_o_len 1
+#define reg_top_gpioh1_o_lsb 0
+#define xd_p_reg_top_gpioh1_en  (*(volatile byte xdata *) 0xD8B0)
+#define    p_reg_top_gpioh1_en  0xD8B0
+#define reg_top_gpioh1_en_pos 0
+#define reg_top_gpioh1_en_len 1
+#define reg_top_gpioh1_en_lsb 0
+#define xd_p_reg_top_gpioh1_on  (*(volatile byte xdata *) 0xD8B1)
+#define    p_reg_top_gpioh1_on  0xD8B1
+#define reg_top_gpioh1_on_pos 0
+#define reg_top_gpioh1_on_len 1
+#define reg_top_gpioh1_on_lsb 0
+#define xd_r_reg_top_gpioh3_i   (*(volatile byte xdata *) 0xD8B2)
+#define    r_reg_top_gpioh3_i   0xD8B2
+#define reg_top_gpioh3_i_pos 0
+#define reg_top_gpioh3_i_len 1
+#define reg_top_gpioh3_i_lsb 0
+#define xd_p_reg_top_gpioh3_o   (*(volatile byte xdata *) 0xD8B3)
+#define    p_reg_top_gpioh3_o   0xD8B3
+#define reg_top_gpioh3_o_pos 0
+#define reg_top_gpioh3_o_len 1
+#define reg_top_gpioh3_o_lsb 0
+#define xd_p_reg_top_gpioh3_en  (*(volatile byte xdata *) 0xD8B4)
+#define    p_reg_top_gpioh3_en  0xD8B4
+#define reg_top_gpioh3_en_pos 0
+#define reg_top_gpioh3_en_len 1
+#define reg_top_gpioh3_en_lsb 0
+#define xd_p_reg_top_gpioh3_on  (*(volatile byte xdata *) 0xD8B5)
+#define    p_reg_top_gpioh3_on  0xD8B5
+#define reg_top_gpioh3_on_pos 0
+#define reg_top_gpioh3_on_len 1
+#define reg_top_gpioh3_on_lsb 0
+#define xd_r_reg_top_gpioh2_i   (*(volatile byte xdata *) 0xD8B6)
+#define    r_reg_top_gpioh2_i   0xD8B6
+#define reg_top_gpioh2_i_pos 0
+#define reg_top_gpioh2_i_len 1
+#define reg_top_gpioh2_i_lsb 0
+#define xd_p_reg_top_gpioh2_o   (*(volatile byte xdata *) 0xD8B7)
+#define    p_reg_top_gpioh2_o   0xD8B7
+#define reg_top_gpioh2_o_pos 0
+#define reg_top_gpioh2_o_len 1
+#define reg_top_gpioh2_o_lsb 0
+#define xd_p_reg_top_gpioh2_en  (*(volatile byte xdata *) 0xD8B8)
+#define    p_reg_top_gpioh2_en  0xD8B8
+#define reg_top_gpioh2_en_pos 0
+#define reg_top_gpioh2_en_len 1
+#define reg_top_gpioh2_en_lsb 0
+#define xd_p_reg_top_gpioh2_on  (*(volatile byte xdata *) 0xD8B9)
+#define    p_reg_top_gpioh2_on  0xD8B9
+#define reg_top_gpioh2_on_pos 0
+#define reg_top_gpioh2_on_len 1
+#define reg_top_gpioh2_on_lsb 0
+#define xd_r_reg_top_gpioh5_i   (*(volatile byte xdata *) 0xD8BA)
+#define    r_reg_top_gpioh5_i   0xD8BA
+#define reg_top_gpioh5_i_pos 0
+#define reg_top_gpioh5_i_len 1
+#define reg_top_gpioh5_i_lsb 0
+#define xd_p_reg_top_gpioh5_o   (*(volatile byte xdata *) 0xD8BB)
+#define    p_reg_top_gpioh5_o   0xD8BB
+#define reg_top_gpioh5_o_pos 0
+#define reg_top_gpioh5_o_len 1
+#define reg_top_gpioh5_o_lsb 0
+#define xd_p_reg_top_gpioh5_en  (*(volatile byte xdata *) 0xD8BC)
+#define    p_reg_top_gpioh5_en  0xD8BC
+#define reg_top_gpioh5_en_pos 0
+#define reg_top_gpioh5_en_len 1
+#define reg_top_gpioh5_en_lsb 0
+#define xd_p_reg_top_gpioh5_on  (*(volatile byte xdata *) 0xD8BD)
+#define    p_reg_top_gpioh5_on  0xD8BD
+#define reg_top_gpioh5_on_pos 0
+#define reg_top_gpioh5_on_len 1
+#define reg_top_gpioh5_on_lsb 0
+#define xd_r_reg_top_gpioh4_i   (*(volatile byte xdata *) 0xD8BE)
+#define    r_reg_top_gpioh4_i   0xD8BE
+#define reg_top_gpioh4_i_pos 0
+#define reg_top_gpioh4_i_len 1
+#define reg_top_gpioh4_i_lsb 0
+#define xd_p_reg_top_gpioh4_o   (*(volatile byte xdata *) 0xD8BF)
+#define    p_reg_top_gpioh4_o   0xD8BF
+#define reg_top_gpioh4_o_pos 0
+#define reg_top_gpioh4_o_len 1
+#define reg_top_gpioh4_o_lsb 0
+#define xd_p_reg_top_gpioh4_en  (*(volatile byte xdata *) 0xD8C0)
+#define    p_reg_top_gpioh4_en  0xD8C0
+#define reg_top_gpioh4_en_pos 0
+#define reg_top_gpioh4_en_len 1
+#define reg_top_gpioh4_en_lsb 0
+#define xd_p_reg_top_gpioh4_on  (*(volatile byte xdata *) 0xD8C1)
+#define    p_reg_top_gpioh4_on  0xD8C1
+#define reg_top_gpioh4_on_pos 0
+#define reg_top_gpioh4_on_len 1
+#define reg_top_gpioh4_on_lsb 0
+#define xd_r_reg_top_gpioh7_i   (*(volatile byte xdata *) 0xD8C2)
+#define    r_reg_top_gpioh7_i   0xD8C2
+#define reg_top_gpioh7_i_pos 0
+#define reg_top_gpioh7_i_len 1
+#define reg_top_gpioh7_i_lsb 0
+#define xd_p_reg_top_gpioh7_o   (*(volatile byte xdata *) 0xD8C3)
+#define    p_reg_top_gpioh7_o   0xD8C3
+#define reg_top_gpioh7_o_pos 0
+#define reg_top_gpioh7_o_len 1
+#define reg_top_gpioh7_o_lsb 0
+#define xd_p_reg_top_gpioh7_en  (*(volatile byte xdata *) 0xD8C4)
+#define    p_reg_top_gpioh7_en  0xD8C4
+#define reg_top_gpioh7_en_pos 0
+#define reg_top_gpioh7_en_len 1
+#define reg_top_gpioh7_en_lsb 0
+#define xd_p_reg_top_gpioh7_on  (*(volatile byte xdata *) 0xD8C5)
+#define    p_reg_top_gpioh7_on  0xD8C5
+#define reg_top_gpioh7_on_pos 0
+#define reg_top_gpioh7_on_len 1
+#define reg_top_gpioh7_on_lsb 0
+#define xd_r_reg_top_gpioh6_i   (*(volatile byte xdata *) 0xD8C6)
+#define    r_reg_top_gpioh6_i   0xD8C6
+#define reg_top_gpioh6_i_pos 0
+#define reg_top_gpioh6_i_len 1
+#define reg_top_gpioh6_i_lsb 0
+#define xd_p_reg_top_gpioh6_o   (*(volatile byte xdata *) 0xD8C7)
+#define    p_reg_top_gpioh6_o   0xD8C7
+#define reg_top_gpioh6_o_pos 0
+#define reg_top_gpioh6_o_len 1
+#define reg_top_gpioh6_o_lsb 0
+#define xd_p_reg_top_gpioh6_en  (*(volatile byte xdata *) 0xD8C8)
+#define    p_reg_top_gpioh6_en  0xD8C8
+#define reg_top_gpioh6_en_pos 0
+#define reg_top_gpioh6_en_len 1
+#define reg_top_gpioh6_en_lsb 0
+#define xd_p_reg_top_gpioh6_on  (*(volatile byte xdata *) 0xD8C9)
+#define    p_reg_top_gpioh6_on  0xD8C9
+#define reg_top_gpioh6_on_pos 0
+#define reg_top_gpioh6_on_len 1
+#define reg_top_gpioh6_on_lsb 0
+#define xd_r_reg_top_gpioh9_i   (*(volatile byte xdata *) 0xD8CA)
+#define    r_reg_top_gpioh9_i   0xD8CA
+#define reg_top_gpioh9_i_pos 0
+#define reg_top_gpioh9_i_len 1
+#define reg_top_gpioh9_i_lsb 0
+#define xd_p_reg_top_gpioh9_o   (*(volatile byte xdata *) 0xD8CB)
+#define    p_reg_top_gpioh9_o   0xD8CB
+#define reg_top_gpioh9_o_pos 0
+#define reg_top_gpioh9_o_len 1
+#define reg_top_gpioh9_o_lsb 0
+#define xd_p_reg_top_gpioh9_en  (*(volatile byte xdata *) 0xD8CC)
+#define    p_reg_top_gpioh9_en  0xD8CC
+#define reg_top_gpioh9_en_pos 0
+#define reg_top_gpioh9_en_len 1
+#define reg_top_gpioh9_en_lsb 0
+#define xd_p_reg_top_gpioh9_on  (*(volatile byte xdata *) 0xD8CD)
+#define    p_reg_top_gpioh9_on  0xD8CD
+#define reg_top_gpioh9_on_pos 0
+#define reg_top_gpioh9_on_len 1
+#define reg_top_gpioh9_on_lsb 0
+#define xd_r_reg_top_gpioh8_i   (*(volatile byte xdata *) 0xD8CE)
+#define    r_reg_top_gpioh8_i   0xD8CE
+#define reg_top_gpioh8_i_pos 0
+#define reg_top_gpioh8_i_len 1
+#define reg_top_gpioh8_i_lsb 0
+#define xd_p_reg_top_gpioh8_o   (*(volatile byte xdata *) 0xD8CF)
+#define    p_reg_top_gpioh8_o   0xD8CF
+#define reg_top_gpioh8_o_pos 0
+#define reg_top_gpioh8_o_len 1
+#define reg_top_gpioh8_o_lsb 0
+#define xd_p_reg_top_gpioh8_en  (*(volatile byte xdata *) 0xD8D0)
+#define    p_reg_top_gpioh8_en  0xD8D0
+#define reg_top_gpioh8_en_pos 0
+#define reg_top_gpioh8_en_len 1
+#define reg_top_gpioh8_en_lsb 0
+#define xd_p_reg_top_gpioh8_on  (*(volatile byte xdata *) 0xD8D1)
+#define    p_reg_top_gpioh8_on  0xD8D1
+#define reg_top_gpioh8_on_pos 0
+#define reg_top_gpioh8_on_len 1
+#define reg_top_gpioh8_on_lsb 0
+#define xd_r_reg_top_gpioh11_i  (*(volatile byte xdata *) 0xD8D2)
+#define    r_reg_top_gpioh11_i  0xD8D2
+#define reg_top_gpioh11_i_pos 0
+#define reg_top_gpioh11_i_len 1
+#define reg_top_gpioh11_i_lsb 0
+#define xd_p_reg_top_gpioh11_o  (*(volatile byte xdata *) 0xD8D3)
+#define    p_reg_top_gpioh11_o  0xD8D3
+#define reg_top_gpioh11_o_pos 0
+#define reg_top_gpioh11_o_len 1
+#define reg_top_gpioh11_o_lsb 0
+#define xd_p_reg_top_gpioh11_en (*(volatile byte xdata *) 0xD8D4)
+#define    p_reg_top_gpioh11_en 0xD8D4
+#define reg_top_gpioh11_en_pos 0
+#define reg_top_gpioh11_en_len 1
+#define reg_top_gpioh11_en_lsb 0
+#define xd_p_reg_top_gpioh11_on (*(volatile byte xdata *) 0xD8D5)
+#define    p_reg_top_gpioh11_on 0xD8D5
+#define reg_top_gpioh11_on_pos 0
+#define reg_top_gpioh11_on_len 1
+#define reg_top_gpioh11_on_lsb 0
+#define xd_r_reg_top_gpioh10_i  (*(volatile byte xdata *) 0xD8D6)
+#define    r_reg_top_gpioh10_i  0xD8D6
+#define reg_top_gpioh10_i_pos 0
+#define reg_top_gpioh10_i_len 1
+#define reg_top_gpioh10_i_lsb 0
+#define xd_p_reg_top_gpioh10_o  (*(volatile byte xdata *) 0xD8D7)
+#define    p_reg_top_gpioh10_o  0xD8D7
+#define reg_top_gpioh10_o_pos 0
+#define reg_top_gpioh10_o_len 1
+#define reg_top_gpioh10_o_lsb 0
+#define xd_p_reg_top_gpioh10_en (*(volatile byte xdata *) 0xD8D8)
+#define    p_reg_top_gpioh10_en 0xD8D8
+#define reg_top_gpioh10_en_pos 0
+#define reg_top_gpioh10_en_len 1
+#define reg_top_gpioh10_en_lsb 0
+#define xd_p_reg_top_gpioh10_on (*(volatile byte xdata *) 0xD8D9)
+#define    p_reg_top_gpioh10_on 0xD8D9
+#define reg_top_gpioh10_on_pos 0
+#define reg_top_gpioh10_on_len 1
+#define reg_top_gpioh10_on_lsb 0
+#define xd_r_reg_top_gpioh13_i  (*(volatile byte xdata *) 0xD8DA)
+#define    r_reg_top_gpioh13_i  0xD8DA
+#define reg_top_gpioh13_i_pos 0
+#define reg_top_gpioh13_i_len 1
+#define reg_top_gpioh13_i_lsb 0
+#define xd_p_reg_top_gpioh13_o  (*(volatile byte xdata *) 0xD8DB)
+#define    p_reg_top_gpioh13_o  0xD8DB
+#define reg_top_gpioh13_o_pos 0
+#define reg_top_gpioh13_o_len 1
+#define reg_top_gpioh13_o_lsb 0
+#define xd_p_reg_top_gpioh13_en (*(volatile byte xdata *) 0xD8DC)
+#define    p_reg_top_gpioh13_en 0xD8DC
+#define reg_top_gpioh13_en_pos 0
+#define reg_top_gpioh13_en_len 1
+#define reg_top_gpioh13_en_lsb 0
+#define xd_p_reg_top_gpioh13_on (*(volatile byte xdata *) 0xD8DD)
+#define    p_reg_top_gpioh13_on 0xD8DD
+#define reg_top_gpioh13_on_pos 0
+#define reg_top_gpioh13_on_len 1
+#define reg_top_gpioh13_on_lsb 0
+#define xd_r_reg_top_gpioh12_i  (*(volatile byte xdata *) 0xD8DE)
+#define    r_reg_top_gpioh12_i  0xD8DE
+#define reg_top_gpioh12_i_pos 0
+#define reg_top_gpioh12_i_len 1
+#define reg_top_gpioh12_i_lsb 0
+#define xd_p_reg_top_gpioh12_o  (*(volatile byte xdata *) 0xD8DF)
+#define    p_reg_top_gpioh12_o  0xD8DF
+#define reg_top_gpioh12_o_pos 0
+#define reg_top_gpioh12_o_len 1
+#define reg_top_gpioh12_o_lsb 0
+#define xd_p_reg_top_gpioh12_en (*(volatile byte xdata *) 0xD8E0)
+#define    p_reg_top_gpioh12_en 0xD8E0
+#define reg_top_gpioh12_en_pos 0
+#define reg_top_gpioh12_en_len 1
+#define reg_top_gpioh12_en_lsb 0
+#define xd_p_reg_top_gpioh12_on (*(volatile byte xdata *) 0xD8E1)
+#define    p_reg_top_gpioh12_on 0xD8E1
+#define reg_top_gpioh12_on_pos 0
+#define reg_top_gpioh12_on_len 1
+#define reg_top_gpioh12_on_lsb 0
+#define xd_r_reg_top_gpiot1_i   (*(volatile byte xdata *) 0xD8E2)
+#define    r_reg_top_gpiot1_i   0xD8E2
+#define reg_top_gpiot1_i_pos 0
+#define reg_top_gpiot1_i_len 1
+#define reg_top_gpiot1_i_lsb 0
+#define xd_p_reg_top_gpiot1_o   (*(volatile byte xdata *) 0xD8E3)
+#define    p_reg_top_gpiot1_o   0xD8E3
+#define reg_top_gpiot1_o_pos 0
+#define reg_top_gpiot1_o_len 1
+#define reg_top_gpiot1_o_lsb 0
+#define xd_p_reg_top_gpiot1_en  (*(volatile byte xdata *) 0xD8E4)
+#define    p_reg_top_gpiot1_en  0xD8E4
+#define reg_top_gpiot1_en_pos 0
+#define reg_top_gpiot1_en_len 1
+#define reg_top_gpiot1_en_lsb 0
+#define xd_p_reg_top_gpiot1_on  (*(volatile byte xdata *) 0xD8E5)
+#define    p_reg_top_gpiot1_on  0xD8E5
+#define reg_top_gpiot1_on_pos 0
+#define reg_top_gpiot1_on_len 1
+#define reg_top_gpiot1_on_lsb 0
+#define xd_r_reg_top_gpiot3_i   (*(volatile byte xdata *) 0xD8E6)
+#define    r_reg_top_gpiot3_i   0xD8E6
+#define reg_top_gpiot3_i_pos 0
+#define reg_top_gpiot3_i_len 1
+#define reg_top_gpiot3_i_lsb 0
+#define xd_p_reg_top_gpiot3_o   (*(volatile byte xdata *) 0xD8E7)
+#define    p_reg_top_gpiot3_o   0xD8E7
+#define reg_top_gpiot3_o_pos 0
+#define reg_top_gpiot3_o_len 1
+#define reg_top_gpiot3_o_lsb 0
+#define xd_p_reg_top_gpiot3_en  (*(volatile byte xdata *) 0xD8E8)
+#define    p_reg_top_gpiot3_en  0xD8E8
+#define reg_top_gpiot3_en_pos 0
+#define reg_top_gpiot3_en_len 1
+#define reg_top_gpiot3_en_lsb 0
+#define xd_p_reg_top_gpiot3_on  (*(volatile byte xdata *) 0xD8E9)
+#define    p_reg_top_gpiot3_on  0xD8E9
+#define reg_top_gpiot3_on_pos 0
+#define reg_top_gpiot3_on_len 1
+#define reg_top_gpiot3_on_lsb 0
+#define xd_r_reg_top_gpiot2_i   (*(volatile byte xdata *) 0xD8EA)
+#define    r_reg_top_gpiot2_i   0xD8EA
+#define reg_top_gpiot2_i_pos 0
+#define reg_top_gpiot2_i_len 1
+#define reg_top_gpiot2_i_lsb 0
+#define xd_p_reg_top_gpiot2_o   (*(volatile byte xdata *) 0xD8EB)
+#define    p_reg_top_gpiot2_o   0xD8EB
+#define reg_top_gpiot2_o_pos 0
+#define reg_top_gpiot2_o_len 1
+#define reg_top_gpiot2_o_lsb 0
+#define xd_p_reg_top_gpiot2_en  (*(volatile byte xdata *) 0xD8EC)
+#define    p_reg_top_gpiot2_en  0xD8EC
+#define reg_top_gpiot2_en_pos 0
+#define reg_top_gpiot2_en_len 1
+#define reg_top_gpiot2_en_lsb 0
+#define xd_p_reg_top_gpiot2_on  (*(volatile byte xdata *) 0xD8ED)
+#define    p_reg_top_gpiot2_on  0xD8ED
+#define reg_top_gpiot2_on_pos 0
+#define reg_top_gpiot2_on_len 1
+#define reg_top_gpiot2_on_lsb 0
+#define xd_p_reg_top_lock2_out  (*(volatile byte xdata *) 0xD8EE)
+#define    p_reg_top_lock2_out  0xD8EE
+#define reg_top_lock2_out_pos 0
+#define reg_top_lock2_out_len 1
+#define reg_top_lock2_out_lsb 0
+#define xd_p_reg_top_lock2_tpsd (*(volatile byte xdata *) 0xD8EF)
+#define    p_reg_top_lock2_tpsd 0xD8EF
+#define reg_top_lock2_tpsd_pos 0
+#define reg_top_lock2_tpsd_len 1
+#define reg_top_lock2_tpsd_lsb 0
+#define xd_p_reg_top_lock2_o    (*(volatile byte xdata *) 0xD8F0)
+#define    p_reg_top_lock2_o    0xD8F0
+#define reg_top_lock2_o_pos 0
+#define reg_top_lock2_o_len 1
+#define reg_top_lock2_o_lsb 0
+#define xd_p_reg_top_lock2_en   (*(volatile byte xdata *) 0xD8F1)
+#define    p_reg_top_lock2_en   0xD8F1
+#define reg_top_lock2_en_pos 0
+#define reg_top_lock2_en_len 1
+#define reg_top_lock2_en_lsb 0
+#define xd_p_reg_top_lock2_on   (*(volatile byte xdata *) 0xD8F2)
+#define    p_reg_top_lock2_on   0xD8F2
+#define reg_top_lock2_on_pos 0
+#define reg_top_lock2_on_len 1
+#define reg_top_lock2_on_lsb 0
+#define xd_p_reg_top_lock1_out  (*(volatile byte xdata *) 0xD8F3)
+#define    p_reg_top_lock1_out  0xD8F3
+#define reg_top_lock1_out_pos 0
+#define reg_top_lock1_out_len 1
+#define reg_top_lock1_out_lsb 0
+#define xd_p_reg_top_lock1_tpsd (*(volatile byte xdata *) 0xD8F4)
+#define    p_reg_top_lock1_tpsd 0xD8F4
+#define reg_top_lock1_tpsd_pos 0
+#define reg_top_lock1_tpsd_len 1
+#define reg_top_lock1_tpsd_lsb 0
+#define xd_p_reg_top_lock1_o    (*(volatile byte xdata *) 0xD8F5)
+#define    p_reg_top_lock1_o    0xD8F5
+#define reg_top_lock1_o_pos 0
+#define reg_top_lock1_o_len 1
+#define reg_top_lock1_o_lsb 0
+#define xd_p_reg_top_lock1_en   (*(volatile byte xdata *) 0xD8F6)
+#define    p_reg_top_lock1_en   0xD8F6
+#define reg_top_lock1_en_pos 0
+#define reg_top_lock1_en_len 1
+#define reg_top_lock1_en_lsb 0
+#define xd_p_reg_top_lock1_on   (*(volatile byte xdata *) 0xD8F7)
+#define    p_reg_top_lock1_on   0xD8F7
+#define reg_top_lock1_on_pos 0
+#define reg_top_lock1_on_len 1
+#define reg_top_lock1_on_lsb 0
+#define xd_p_reg_top_lock4_out  (*(volatile byte xdata *) 0xD8F8)
+#define    p_reg_top_lock4_out  0xD8F8
+#define reg_top_lock4_out_pos 0
+#define reg_top_lock4_out_len 1
+#define reg_top_lock4_out_lsb 0
+#define xd_p_reg_top_lock4_tpsd (*(volatile byte xdata *) 0xD8F9)
+#define    p_reg_top_lock4_tpsd 0xD8F9
+#define reg_top_lock4_tpsd_pos 0
+#define reg_top_lock4_tpsd_len 1
+#define reg_top_lock4_tpsd_lsb 0
+#define xd_p_reg_top_lock4_o    (*(volatile byte xdata *) 0xD8FA)
+#define    p_reg_top_lock4_o    0xD8FA
+#define reg_top_lock4_o_pos 0
+#define reg_top_lock4_o_len 1
+#define reg_top_lock4_o_lsb 0
+#define xd_p_reg_top_lock4_en   (*(volatile byte xdata *) 0xD8FB)
+#define    p_reg_top_lock4_en   0xD8FB
+#define reg_top_lock4_en_pos 0
+#define reg_top_lock4_en_len 1
+#define reg_top_lock4_en_lsb 0
+#define xd_p_reg_top_lock4_on   (*(volatile byte xdata *) 0xD8FC)
+#define    p_reg_top_lock4_on   0xD8FC
+#define reg_top_lock4_on_pos 0
+#define reg_top_lock4_on_len 1
+#define reg_top_lock4_on_lsb 0
+#define xd_p_reg_top_lock3_out  (*(volatile byte xdata *) 0xD8FD)
+#define    p_reg_top_lock3_out  0xD8FD
+#define reg_top_lock3_out_pos 0
+#define reg_top_lock3_out_len 1
+#define reg_top_lock3_out_lsb 0
+#define xd_p_reg_top_lock3_tpsd (*(volatile byte xdata *) 0xD8FE)
+#define    p_reg_top_lock3_tpsd 0xD8FE
+#define reg_top_lock3_tpsd_pos 0
+#define reg_top_lock3_tpsd_len 1
+#define reg_top_lock3_tpsd_lsb 0
+#define xd_p_reg_top_lock3_o    (*(volatile byte xdata *) 0xD8FF)
+#define    p_reg_top_lock3_o    0xD8FF
+#define reg_top_lock3_o_pos 0
+#define reg_top_lock3_o_len 1
+#define reg_top_lock3_o_lsb 0
+#define xd_p_reg_top_lock3_en   (*(volatile byte xdata *) 0xD900)
+#define    p_reg_top_lock3_en   0xD900
+#define reg_top_lock3_en_pos 0
+#define reg_top_lock3_en_len 1
+#define reg_top_lock3_en_lsb 0
+#define xd_p_reg_top_lock3_on   (*(volatile byte xdata *) 0xD901)
+#define    p_reg_top_lock3_on   0xD901
+#define reg_top_lock3_on_pos 0
+#define reg_top_lock3_on_len 1
+#define reg_top_lock3_on_lsb 0
+#define xd_p_reg_top_pwm0_en    (*(volatile byte xdata *) 0xD902)
+#define    p_reg_top_pwm0_en    0xD902
+#define reg_top_pwm0_en_pos 0
+#define reg_top_pwm0_en_len 1
+#define reg_top_pwm0_en_lsb 0
+#define xd_p_reg_top_pwm1_en    (*(volatile byte xdata *) 0xD903)
+#define    p_reg_top_pwm1_en    0xD903
+#define reg_top_pwm1_en_pos 0
+#define reg_top_pwm1_en_len 1
+#define reg_top_pwm1_en_lsb 0
+#define xd_p_reg_top_pwm2_en    (*(volatile byte xdata *) 0xD904)
+#define    p_reg_top_pwm2_en    0xD904
+#define reg_top_pwm2_en_pos 0
+#define reg_top_pwm2_en_len 1
+#define reg_top_pwm2_en_lsb 0
+#define xd_p_reg_top_pwm3_en    (*(volatile byte xdata *) 0xD905)
+#define    p_reg_top_pwm3_en    0xD905
+#define reg_top_pwm3_en_pos 0
+#define reg_top_pwm3_en_len 1
+#define reg_top_pwm3_en_lsb 0
+#define xd_p_reg_top_pwm0_gpio  (*(volatile byte xdata *) 0xD906)
+#define    p_reg_top_pwm0_gpio  0xD906
+#define reg_top_pwm0_gpio_pos 0
+#define reg_top_pwm0_gpio_len 1
+#define reg_top_pwm0_gpio_lsb 0
+#define xd_p_reg_top_pwm0_pos   (*(volatile byte xdata *) 0xD907)
+#define    p_reg_top_pwm0_pos   0xD907
+#define reg_top_pwm0_pos_pos 0
+#define reg_top_pwm0_pos_len 3
+#define reg_top_pwm0_pos_lsb 0
+#define xd_p_reg_top_pwm0_width (*(volatile byte xdata *) 0xD908)
+#define    p_reg_top_pwm0_width 0xD908
+#define reg_top_pwm0_width_pos 0
+#define reg_top_pwm0_width_len 2
+#define reg_top_pwm0_width_lsb 0
+#define xd_p_reg_top_pwm0_duration  (*(volatile byte xdata *) 0xD909)
+#define    p_reg_top_pwm0_duration  0xD909
+#define reg_top_pwm0_duration_pos 0
+#define reg_top_pwm0_duration_len 8
+#define reg_top_pwm0_duration_lsb 0
+#define xd_p_reg_top_pwm1_gpio  (*(volatile byte xdata *) 0xD90A)
+#define    p_reg_top_pwm1_gpio  0xD90A
+#define reg_top_pwm1_gpio_pos 0
+#define reg_top_pwm1_gpio_len 1
+#define reg_top_pwm1_gpio_lsb 0
+#define xd_p_reg_top_pwm1_pos   (*(volatile byte xdata *) 0xD90B)
+#define    p_reg_top_pwm1_pos   0xD90B
+#define reg_top_pwm1_pos_pos 0
+#define reg_top_pwm1_pos_len 3
+#define reg_top_pwm1_pos_lsb 0
+#define xd_p_reg_top_pwm1_width (*(volatile byte xdata *) 0xD90C)
+#define    p_reg_top_pwm1_width 0xD90C
+#define reg_top_pwm1_width_pos 0
+#define reg_top_pwm1_width_len 2
+#define reg_top_pwm1_width_lsb 0
+#define xd_p_reg_top_pwm1_duration  (*(volatile byte xdata *) 0xD90D)
+#define    p_reg_top_pwm1_duration  0xD90D
+#define reg_top_pwm1_duration_pos 0
+#define reg_top_pwm1_duration_len 8
+#define reg_top_pwm1_duration_lsb 0
+#define xd_p_reg_top_pwm2_gpio  (*(volatile byte xdata *) 0xD90E)
+#define    p_reg_top_pwm2_gpio  0xD90E
+#define reg_top_pwm2_gpio_pos 0
+#define reg_top_pwm2_gpio_len 1
+#define reg_top_pwm2_gpio_lsb 0
+#define xd_p_reg_top_pwm2_pos   (*(volatile byte xdata *) 0xD90F)
+#define    p_reg_top_pwm2_pos   0xD90F
+#define reg_top_pwm2_pos_pos 0
+#define reg_top_pwm2_pos_len 3
+#define reg_top_pwm2_pos_lsb 0
+#define xd_p_reg_top_pwm2_width (*(volatile byte xdata *) 0xD910)
+#define    p_reg_top_pwm2_width 0xD910
+#define reg_top_pwm2_width_pos 0
+#define reg_top_pwm2_width_len 2
+#define reg_top_pwm2_width_lsb 0
+#define xd_p_reg_top_pwm2_duration  (*(volatile byte xdata *) 0xD911)
+#define    p_reg_top_pwm2_duration  0xD911
+#define reg_top_pwm2_duration_pos 0
+#define reg_top_pwm2_duration_len 8
+#define reg_top_pwm2_duration_lsb 0
+#define xd_p_reg_top_pwm3_gpio  (*(volatile byte xdata *) 0xD912)
+#define    p_reg_top_pwm3_gpio  0xD912
+#define reg_top_pwm3_gpio_pos 0
+#define reg_top_pwm3_gpio_len 1
+#define reg_top_pwm3_gpio_lsb 0
+#define xd_p_reg_top_pwm3_pos   (*(volatile byte xdata *) 0xD913)
+#define    p_reg_top_pwm3_pos   0xD913
+#define reg_top_pwm3_pos_pos 0
+#define reg_top_pwm3_pos_len 3
+#define reg_top_pwm3_pos_lsb 0
+#define xd_p_reg_top_pwm3_width (*(volatile byte xdata *) 0xD914)
+#define    p_reg_top_pwm3_width 0xD914
+#define reg_top_pwm3_width_pos 0
+#define reg_top_pwm3_width_len 2
+#define reg_top_pwm3_width_lsb 0
+#define xd_p_reg_top_pwm3_duration  (*(volatile byte xdata *) 0xD915)
+#define    p_reg_top_pwm3_duration  0xD915
+#define reg_top_pwm3_duration_pos 0
+#define reg_top_pwm3_duration_len 8
+#define reg_top_pwm3_duration_lsb 0
+#define xd_p_reg_top_hosta_mpeg_par_mode    (*(volatile byte xdata *) 0xD916)
+#define    p_reg_top_hosta_mpeg_par_mode    0xD916
+#define reg_top_hosta_mpeg_par_mode_pos 0
+#define reg_top_hosta_mpeg_par_mode_len 1
+#define reg_top_hosta_mpeg_par_mode_lsb 0
+#define xd_p_reg_top_hosta_mpeg_ser_mode    (*(volatile byte xdata *) 0xD917)
+#define    p_reg_top_hosta_mpeg_ser_mode    0xD917
+#define reg_top_hosta_mpeg_ser_mode_pos 0
+#define reg_top_hosta_mpeg_ser_mode_len 1
+#define reg_top_hosta_mpeg_ser_mode_lsb 0
+#define xd_p_reg_top_hosta_mpeg_ser_do7 (*(volatile byte xdata *) 0xD918)
+#define    p_reg_top_hosta_mpeg_ser_do7 0xD918
+#define reg_top_hosta_mpeg_ser_do7_pos 0
+#define reg_top_hosta_mpeg_ser_do7_len 1
+#define reg_top_hosta_mpeg_ser_do7_lsb 0
+#define xd_p_reg_top_hosta_dca_upper    (*(volatile byte xdata *) 0xD919)
+#define    p_reg_top_hosta_dca_upper    0xD919
+#define reg_top_hosta_dca_upper_pos 0
+#define reg_top_hosta_dca_upper_len 1
+#define reg_top_hosta_dca_upper_lsb 0
+#define xd_p_reg_top_hosta_dca_lower    (*(volatile byte xdata *) 0xD91A)
+#define    p_reg_top_hosta_dca_lower    0xD91A
+#define reg_top_hosta_dca_lower_pos 0
+#define reg_top_hosta_dca_lower_len 1
+#define reg_top_hosta_dca_lower_lsb 0
+#define xd_p_reg_top_hostb_mpeg_par_mode    (*(volatile byte xdata *) 0xD91B)
+#define    p_reg_top_hostb_mpeg_par_mode    0xD91B
+#define reg_top_hostb_mpeg_par_mode_pos 0
+#define reg_top_hostb_mpeg_par_mode_len 1
+#define reg_top_hostb_mpeg_par_mode_lsb 0
+#define xd_p_reg_top_hostb_mpeg_ser_mode    (*(volatile byte xdata *) 0xD91C)
+#define    p_reg_top_hostb_mpeg_ser_mode    0xD91C
+#define reg_top_hostb_mpeg_ser_mode_pos 0
+#define reg_top_hostb_mpeg_ser_mode_len 1
+#define reg_top_hostb_mpeg_ser_mode_lsb 0
+#define xd_p_reg_top_hostb_mpeg_ser_do7 (*(volatile byte xdata *) 0xD91D)
+#define    p_reg_top_hostb_mpeg_ser_do7 0xD91D
+#define reg_top_hostb_mpeg_ser_do7_pos 0
+#define reg_top_hostb_mpeg_ser_do7_len 1
+#define reg_top_hostb_mpeg_ser_do7_lsb 0
+#define xd_p_reg_top_hostb_dca_upper    (*(volatile byte xdata *) 0xD91E)
+#define    p_reg_top_hostb_dca_upper    0xD91E
+#define reg_top_hostb_dca_upper_pos 0
+#define reg_top_hostb_dca_upper_len 1
+#define reg_top_hostb_dca_upper_lsb 0
+#define xd_p_reg_top_hostb_dca_lower    (*(volatile byte xdata *) 0xD91F)
+#define    p_reg_top_hostb_dca_lower    0xD91F
+#define reg_top_hostb_dca_lower_pos 0
+#define reg_top_hostb_dca_lower_len 1
+#define reg_top_hostb_dca_lower_lsb 0
+#define xd_p_reg_top_host_reverse   (*(volatile byte xdata *) 0xD920)
+#define    p_reg_top_host_reverse   0xD920
+#define reg_top_host_reverse_pos 0
+#define reg_top_host_reverse_len 1
+#define reg_top_host_reverse_lsb 0
+#define xd_p_reg_top_hosta_ccir (*(volatile byte xdata *) 0xD921)
+#define    p_reg_top_hosta_ccir 0xD921
+#define reg_top_hosta_ccir_pos 0
+#define reg_top_hosta_ccir_len 1
+#define reg_top_hosta_ccir_lsb 0
+#define xd_p_reg_top_hostb_ccir (*(volatile byte xdata *) 0xD922)
+#define    p_reg_top_hostb_ccir 0xD922
+#define reg_top_hostb_ccir_pos 0
+#define reg_top_hostb_ccir_len 1
+#define reg_top_hostb_ccir_lsb 0
+#define xd_p_reg_top_i2s_master_mode    (*(volatile byte xdata *) 0xD923)
+#define    p_reg_top_i2s_master_mode    0xD923
+#define reg_top_i2s_master_mode_pos 0
+#define reg_top_i2s_master_mode_len 1
+#define reg_top_i2s_master_mode_lsb 0
+#define xd_p_reg_usb_cfg_speed  (*(volatile byte xdata *) 0xDD00)
+#define    p_reg_usb_cfg_speed  0xDD00
+#define reg_usb_cfg_speed_pos 0
+#define reg_usb_cfg_speed_len 1
+#define reg_usb_cfg_speed_lsb 0
+#define xd_p_reg_usb_cfg_utmi16 (*(volatile byte xdata *) 0xDD00)
+#define    p_reg_usb_cfg_utmi16 0xDD00
+#define reg_usb_cfg_utmi16_pos 1
+#define reg_usb_cfg_utmi16_len 1
+#define reg_usb_cfg_utmi16_lsb 0
+#define xd_p_reg_usb_cfg_test   (*(volatile byte xdata *) 0xDD00)
+#define    p_reg_usb_cfg_test   0xDD00
+#define reg_usb_cfg_test_pos 3
+#define reg_usb_cfg_test_len 3
+#define reg_usb_cfg_test_lsb 0
+#define xd_p_reg_usb_port_sim_reset (*(volatile byte xdata *) 0xDD00)
+#define    p_reg_usb_port_sim_reset 0xDD00
+#define reg_usb_port_sim_reset_pos 6
+#define reg_usb_port_sim_reset_len 1
+#define reg_usb_port_sim_reset_lsb 0
+#define xd_p_reg_usb_port_run   (*(volatile byte xdata *) 0xDD00)
+#define    p_reg_usb_port_run   0xDD00
+#define reg_usb_port_run_pos 7
+#define reg_usb_port_run_len 1
+#define reg_usb_port_run_lsb 0
+#define xd_r_usb_line_state_0   (*(volatile byte xdata *) 0xDD01)
+#define    r_usb_line_state_0   0xDD01
+#define usb_line_state_0_pos 0
+#define usb_line_state_0_len 1
+#define usb_line_state_0_lsb 0
+#define xd_r_usb_line_state_1   (*(volatile byte xdata *) 0xDD01)
+#define    r_usb_line_state_1   0xDD01
+#define usb_line_state_1_pos 1
+#define usb_line_state_1_len 1
+#define usb_line_state_1_lsb 0
+#define xd_r_reg_usb_status_speed   (*(volatile byte xdata *) 0xDD01)
+#define    r_reg_usb_status_speed   0xDD01
+#define reg_usb_status_speed_pos 2
+#define reg_usb_status_speed_len 1
+#define reg_usb_status_speed_lsb 0
+#define xd_r_reg_usb_status_connect (*(volatile byte xdata *) 0xDD01)
+#define    r_reg_usb_status_connect 0xDD01
+#define reg_usb_status_connect_pos 3
+#define reg_usb_status_connect_len 1
+#define reg_usb_status_connect_lsb 0
+#define xd_r_reg_usb_rx_buf (*(volatile byte xdata *) 0xDD01)
+#define    r_reg_usb_rx_buf 0xDD01
+#define reg_usb_rx_buf_pos 4
+#define reg_usb_rx_buf_len 1
+#define reg_usb_rx_buf_lsb 0
+#define xd_r_reg_usb_port_reset (*(volatile byte xdata *) 0xDD01)
+#define    r_reg_usb_port_reset 0xDD01
+#define reg_usb_port_reset_pos 5
+#define reg_usb_port_reset_len 1
+#define reg_usb_port_reset_lsb 0
+#define xd_r_reg_usb_port_suspend   (*(volatile byte xdata *) 0xDD01)
+#define    r_reg_usb_port_suspend   0xDD01
+#define reg_usb_port_suspend_pos 6
+#define reg_usb_port_suspend_len 1
+#define reg_usb_port_suspend_lsb 0
+#define xd_p_reg_ep1_tx_type    (*(volatile byte xdata *) 0xDD07)
+#define    p_reg_ep1_tx_type    0xDD07
+#define reg_ep1_tx_type_pos 2
+#define reg_ep1_tx_type_len 1
+#define reg_ep1_tx_type_lsb 0
+#define xd_p_reg_ep2_rx_type    (*(volatile byte xdata *) 0xDD07)
+#define    p_reg_ep2_rx_type    0xDD07
+#define reg_ep2_rx_type_pos 3
+#define reg_ep2_rx_type_len 1
+#define reg_ep2_rx_type_lsb 0
+#define xd_p_reg_ep3_tx_type    (*(volatile byte xdata *) 0xDD07)
+#define    p_reg_ep3_tx_type    0xDD07
+#define reg_ep3_tx_type_pos 4
+#define reg_ep3_tx_type_len 1
+#define reg_ep3_tx_type_lsb 0
+#define xd_p_reg_ep4_tx_type    (*(volatile byte xdata *) 0xDD07)
+#define    p_reg_ep4_tx_type    0xDD07
+#define reg_ep4_tx_type_pos 5
+#define reg_ep4_tx_type_len 1
+#define reg_ep4_tx_type_lsb 0
+#define xd_p_reg_ep5_tx_type    (*(volatile byte xdata *) 0xDD07)
+#define    p_reg_ep5_tx_type    0xDD07
+#define reg_ep5_tx_type_pos 6
+#define reg_ep5_tx_type_len 1
+#define reg_ep5_tx_type_lsb 0
+#define xd_p_reg_ep6_tx_type    (*(volatile byte xdata *) 0xDD07)
+#define    p_reg_ep6_tx_type    0xDD07
+#define reg_ep6_tx_type_pos 7
+#define reg_ep6_tx_type_len 1
+#define reg_ep6_tx_type_lsb 0
+#define xd_p_reg_ep0_max_pkt    (*(volatile byte xdata *) 0xDD08)
+#define    p_reg_ep0_max_pkt    0xDD08
+#define reg_ep0_max_pkt_pos 0
+#define reg_ep0_max_pkt_len 8
+#define reg_ep0_max_pkt_lsb 0
+#define xd_p_reg_ep2_max_pkt    (*(volatile byte xdata *) 0xDD0A)
+#define    p_reg_ep2_max_pkt    0xDD0A
+#define reg_ep2_max_pkt_pos 0
+#define reg_ep2_max_pkt_len 8
+#define reg_ep2_max_pkt_lsb 0
+#define xd_p_reg_ep4_max_pkt    (*(volatile byte xdata *) 0xDD0C)
+#define    p_reg_ep4_max_pkt    0xDD0C
+#define reg_ep4_max_pkt_pos 0
+#define reg_ep4_max_pkt_len 8
+#define reg_ep4_max_pkt_lsb 0
+#define xd_p_reg_ep5_max_pkt    (*(volatile byte xdata *) 0xDD0D)
+#define    p_reg_ep5_max_pkt    0xDD0D
+#define reg_ep5_max_pkt_pos 0
+#define reg_ep5_max_pkt_len 8
+#define reg_ep5_max_pkt_lsb 0
+#define xd_p_reg_ep6_max_pkt_7_0    (*(volatile byte xdata *) 0xDD0E)
+#define    p_reg_ep6_max_pkt_7_0    0xDD0E
+#define reg_ep6_max_pkt_7_0_pos 0
+#define reg_ep6_max_pkt_7_0_len 8
+#define reg_ep6_max_pkt_7_0_lsb 0
+#define xd_p_reg_ep6_max_pkt_15_8   (*(volatile byte xdata *) 0xDD0F)
+#define    p_reg_ep6_max_pkt_15_8   0xDD0F
+#define reg_ep6_max_pkt_15_8_pos 0
+#define reg_ep6_max_pkt_15_8_len 8
+#define reg_ep6_max_pkt_15_8_lsb 8
+#define xd_p_reg_usb_addr   (*(volatile byte xdata *) 0xDD10)
+#define    p_reg_usb_addr   0xDD10
+#define reg_usb_addr_pos 0
+#define reg_usb_addr_len 7
+#define reg_usb_addr_lsb 0
+#define xd_p_reg_usb_addr_now   (*(volatile byte xdata *) 0xDD10)
+#define    p_reg_usb_addr_now   0xDD10
+#define reg_usb_addr_now_pos 7
+#define reg_usb_addr_now_len 1
+#define reg_usb_addr_now_lsb 0
+#define xd_p_reg_ep0_tx_en  (*(volatile byte xdata *) 0xDD11)
+#define    p_reg_ep0_tx_en  0xDD11
+#define reg_ep0_tx_en_pos 0
+#define reg_ep0_tx_en_len 1
+#define reg_ep0_tx_en_lsb 0
+#define xd_p_reg_ep0_rx_en  (*(volatile byte xdata *) 0xDD11)
+#define    p_reg_ep0_rx_en  0xDD11
+#define reg_ep0_rx_en_pos 1
+#define reg_ep0_rx_en_len 1
+#define reg_ep0_rx_en_lsb 0
+#define xd_p_reg_ep1_tx_en  (*(volatile byte xdata *) 0xDD11)
+#define    p_reg_ep1_tx_en  0xDD11
+#define reg_ep1_tx_en_pos 2
+#define reg_ep1_tx_en_len 1
+#define reg_ep1_tx_en_lsb 0
+#define xd_p_reg_ep2_rx_en  (*(volatile byte xdata *) 0xDD11)
+#define    p_reg_ep2_rx_en  0xDD11
+#define reg_ep2_rx_en_pos 3
+#define reg_ep2_rx_en_len 1
+#define reg_ep2_rx_en_lsb 0
+#define xd_p_reg_ep3_tx_en  (*(volatile byte xdata *) 0xDD11)
+#define    p_reg_ep3_tx_en  0xDD11
+#define reg_ep3_tx_en_pos 4
+#define reg_ep3_tx_en_len 1
+#define reg_ep3_tx_en_lsb 0
+#define xd_p_reg_ep4_tx_en  (*(volatile byte xdata *) 0xDD11)
+#define    p_reg_ep4_tx_en  0xDD11
+#define reg_ep4_tx_en_pos 5
+#define reg_ep4_tx_en_len 1
+#define reg_ep4_tx_en_lsb 0
+#define xd_p_reg_ep5_tx_en  (*(volatile byte xdata *) 0xDD11)
+#define    p_reg_ep5_tx_en  0xDD11
+#define reg_ep5_tx_en_pos 6
+#define reg_ep5_tx_en_len 1
+#define reg_ep5_tx_en_lsb 0
+#define xd_p_reg_ep6_tx_en  (*(volatile byte xdata *) 0xDD11)
+#define    p_reg_ep6_tx_en  0xDD11
+#define reg_ep6_tx_en_pos 7
+#define reg_ep6_tx_en_len 1
+#define reg_ep6_tx_en_lsb 0
+#define xd_p_reg_ep0_tx_stall   (*(volatile byte xdata *) 0xDD12)
+#define    p_reg_ep0_tx_stall   0xDD12
+#define reg_ep0_tx_stall_pos 0
+#define reg_ep0_tx_stall_len 1
+#define reg_ep0_tx_stall_lsb 0
+#define xd_p_reg_ep0_rx_stall   (*(volatile byte xdata *) 0xDD12)
+#define    p_reg_ep0_rx_stall   0xDD12
+#define reg_ep0_rx_stall_pos 1
+#define reg_ep0_rx_stall_len 1
+#define reg_ep0_rx_stall_lsb 0
+#define xd_p_reg_ep1_tx_stall   (*(volatile byte xdata *) 0xDD12)
+#define    p_reg_ep1_tx_stall   0xDD12
+#define reg_ep1_tx_stall_pos 2
+#define reg_ep1_tx_stall_len 1
+#define reg_ep1_tx_stall_lsb 0
+#define xd_p_reg_ep2_rx_stall   (*(volatile byte xdata *) 0xDD12)
+#define    p_reg_ep2_rx_stall   0xDD12
+#define reg_ep2_rx_stall_pos 3
+#define reg_ep2_rx_stall_len 1
+#define reg_ep2_rx_stall_lsb 0
+#define xd_p_reg_ep3_tx_stall   (*(volatile byte xdata *) 0xDD12)
+#define    p_reg_ep3_tx_stall   0xDD12
+#define reg_ep3_tx_stall_pos 4
+#define reg_ep3_tx_stall_len 1
+#define reg_ep3_tx_stall_lsb 0
+#define xd_p_reg_ep4_tx_stall   (*(volatile byte xdata *) 0xDD12)
+#define    p_reg_ep4_tx_stall   0xDD12
+#define reg_ep4_tx_stall_pos 5
+#define reg_ep4_tx_stall_len 1
+#define reg_ep4_tx_stall_lsb 0
+#define xd_p_reg_ep5_tx_stall   (*(volatile byte xdata *) 0xDD12)
+#define    p_reg_ep5_tx_stall   0xDD12
+#define reg_ep5_tx_stall_pos 6
+#define reg_ep5_tx_stall_len 1
+#define reg_ep5_tx_stall_lsb 0
+#define xd_p_reg_ep6_tx_stall   (*(volatile byte xdata *) 0xDD12)
+#define    p_reg_ep6_tx_stall   0xDD12
+#define reg_ep6_tx_stall_pos 7
+#define reg_ep6_tx_stall_len 1
+#define reg_ep6_tx_stall_lsb 0
+#define xd_p_reg_ep0_tx_nak (*(volatile byte xdata *) 0xDD13)
+#define    p_reg_ep0_tx_nak 0xDD13
+#define reg_ep0_tx_nak_pos 0
+#define reg_ep0_tx_nak_len 1
+#define reg_ep0_tx_nak_lsb 0
+#define xd_p_reg_ep0_rx_nak (*(volatile byte xdata *) 0xDD13)
+#define    p_reg_ep0_rx_nak 0xDD13
+#define reg_ep0_rx_nak_pos 1
+#define reg_ep0_rx_nak_len 1
+#define reg_ep0_rx_nak_lsb 0
+#define xd_p_reg_ep1_tx_nak (*(volatile byte xdata *) 0xDD13)
+#define    p_reg_ep1_tx_nak 0xDD13
+#define reg_ep1_tx_nak_pos 2
+#define reg_ep1_tx_nak_len 1
+#define reg_ep1_tx_nak_lsb 0
+#define xd_p_reg_ep2_rx_nak (*(volatile byte xdata *) 0xDD13)
+#define    p_reg_ep2_rx_nak 0xDD13
+#define reg_ep2_rx_nak_pos 3
+#define reg_ep2_rx_nak_len 1
+#define reg_ep2_rx_nak_lsb 0
+#define xd_p_reg_ep3_tx_nak (*(volatile byte xdata *) 0xDD13)
+#define    p_reg_ep3_tx_nak 0xDD13
+#define reg_ep3_tx_nak_pos 4
+#define reg_ep3_tx_nak_len 1
+#define reg_ep3_tx_nak_lsb 0
+#define xd_p_reg_ep4_tx_nak (*(volatile byte xdata *) 0xDD13)
+#define    p_reg_ep4_tx_nak 0xDD13
+#define reg_ep4_tx_nak_pos 5
+#define reg_ep4_tx_nak_len 1
+#define reg_ep4_tx_nak_lsb 0
+#define xd_p_reg_ep5_tx_nak (*(volatile byte xdata *) 0xDD13)
+#define    p_reg_ep5_tx_nak 0xDD13
+#define reg_ep5_tx_nak_pos 6
+#define reg_ep5_tx_nak_len 1
+#define reg_ep5_tx_nak_lsb 0
+#define xd_p_reg_ep6_tx_nak (*(volatile byte xdata *) 0xDD13)
+#define    p_reg_ep6_tx_nak 0xDD13
+#define reg_ep6_tx_nak_pos 7
+#define reg_ep6_tx_nak_len 1
+#define reg_ep6_tx_nak_lsb 0
+#define xd_p_reg_ep0_tx_nak_int_en  (*(volatile byte xdata *) 0xDD14)
+#define    p_reg_ep0_tx_nak_int_en  0xDD14
+#define reg_ep0_tx_nak_int_en_pos 0
+#define reg_ep0_tx_nak_int_en_len 1
+#define reg_ep0_tx_nak_int_en_lsb 0
+#define xd_p_reg_ep0_rx_nak_int_en  (*(volatile byte xdata *) 0xDD14)
+#define    p_reg_ep0_rx_nak_int_en  0xDD14
+#define reg_ep0_rx_nak_int_en_pos 1
+#define reg_ep0_rx_nak_int_en_len 1
+#define reg_ep0_rx_nak_int_en_lsb 0
+#define xd_p_reg_ep1_tx_nak_int_en  (*(volatile byte xdata *) 0xDD14)
+#define    p_reg_ep1_tx_nak_int_en  0xDD14
+#define reg_ep1_tx_nak_int_en_pos 2
+#define reg_ep1_tx_nak_int_en_len 1
+#define reg_ep1_tx_nak_int_en_lsb 0
+#define xd_p_reg_ep2_rx_nak_int_en  (*(volatile byte xdata *) 0xDD14)
+#define    p_reg_ep2_rx_nak_int_en  0xDD14
+#define reg_ep2_rx_nak_int_en_pos 3
+#define reg_ep2_rx_nak_int_en_len 1
+#define reg_ep2_rx_nak_int_en_lsb 0
+#define xd_p_reg_ep3_tx_nak_int_en  (*(volatile byte xdata *) 0xDD14)
+#define    p_reg_ep3_tx_nak_int_en  0xDD14
+#define reg_ep3_tx_nak_int_en_pos 4
+#define reg_ep3_tx_nak_int_en_len 1
+#define reg_ep3_tx_nak_int_en_lsb 0
+#define xd_p_reg_ep4_tx_nak_int_en  (*(volatile byte xdata *) 0xDD14)
+#define    p_reg_ep4_tx_nak_int_en  0xDD14
+#define reg_ep4_tx_nak_int_en_pos 5
+#define reg_ep4_tx_nak_int_en_len 1
+#define reg_ep4_tx_nak_int_en_lsb 0
+#define xd_p_reg_ep5_tx_nak_int_en  (*(volatile byte xdata *) 0xDD14)
+#define    p_reg_ep5_tx_nak_int_en  0xDD14
+#define reg_ep5_tx_nak_int_en_pos 6
+#define reg_ep5_tx_nak_int_en_len 1
+#define reg_ep5_tx_nak_int_en_lsb 0
+#define xd_p_reg_ep6_tx_nak_int_en  (*(volatile byte xdata *) 0xDD14)
+#define    p_reg_ep6_tx_nak_int_en  0xDD14
+#define reg_ep6_tx_nak_int_en_pos 7
+#define reg_ep6_tx_nak_int_en_len 1
+#define reg_ep6_tx_nak_int_en_lsb 0
+#define xd_p_reg_ep0_tx_done_int_en (*(volatile byte xdata *) 0xDD15)
+#define    p_reg_ep0_tx_done_int_en 0xDD15
+#define reg_ep0_tx_done_int_en_pos 0
+#define reg_ep0_tx_done_int_en_len 1
+#define reg_ep0_tx_done_int_en_lsb 0
+#define xd_p_reg_ep0_rx_done_int_en (*(volatile byte xdata *) 0xDD15)
+#define    p_reg_ep0_rx_done_int_en 0xDD15
+#define reg_ep0_rx_done_int_en_pos 1
+#define reg_ep0_rx_done_int_en_len 1
+#define reg_ep0_rx_done_int_en_lsb 0
+#define xd_p_reg_ep1_tx_done_int_en (*(volatile byte xdata *) 0xDD15)
+#define    p_reg_ep1_tx_done_int_en 0xDD15
+#define reg_ep1_tx_done_int_en_pos 2
+#define reg_ep1_tx_done_int_en_len 1
+#define reg_ep1_tx_done_int_en_lsb 0
+#define xd_p_reg_ep2_rx_done_int_en (*(volatile byte xdata *) 0xDD15)
+#define    p_reg_ep2_rx_done_int_en 0xDD15
+#define reg_ep2_rx_done_int_en_pos 3
+#define reg_ep2_rx_done_int_en_len 1
+#define reg_ep2_rx_done_int_en_lsb 0
+#define xd_p_reg_ep3_tx_done_int_en (*(volatile byte xdata *) 0xDD15)
+#define    p_reg_ep3_tx_done_int_en 0xDD15
+#define reg_ep3_tx_done_int_en_pos 4
+#define reg_ep3_tx_done_int_en_len 1
+#define reg_ep3_tx_done_int_en_lsb 0
+#define xd_p_reg_ep4_tx_done_int_en (*(volatile byte xdata *) 0xDD15)
+#define    p_reg_ep4_tx_done_int_en 0xDD15
+#define reg_ep4_tx_done_int_en_pos 5
+#define reg_ep4_tx_done_int_en_len 1
+#define reg_ep4_tx_done_int_en_lsb 0
+#define xd_p_reg_ep5_tx_done_int_en (*(volatile byte xdata *) 0xDD15)
+#define    p_reg_ep5_tx_done_int_en 0xDD15
+#define reg_ep5_tx_done_int_en_pos 6
+#define reg_ep5_tx_done_int_en_len 1
+#define reg_ep5_tx_done_int_en_lsb 0
+#define xd_p_reg_ep6_tx_done_int_en (*(volatile byte xdata *) 0xDD15)
+#define    p_reg_ep6_tx_done_int_en 0xDD15
+#define reg_ep6_tx_done_int_en_pos 7
+#define reg_ep6_tx_done_int_en_len 1
+#define reg_ep6_tx_done_int_en_lsb 0
+#define xd_p_reg_ep0_tx_fail_int_en (*(volatile byte xdata *) 0xDD16)
+#define    p_reg_ep0_tx_fail_int_en 0xDD16
+#define reg_ep0_tx_fail_int_en_pos 0
+#define reg_ep0_tx_fail_int_en_len 1
+#define reg_ep0_tx_fail_int_en_lsb 0
+#define xd_p_reg_ep0_rx_fail_int_en (*(volatile byte xdata *) 0xDD16)
+#define    p_reg_ep0_rx_fail_int_en 0xDD16
+#define reg_ep0_rx_fail_int_en_pos 1
+#define reg_ep0_rx_fail_int_en_len 1
+#define reg_ep0_rx_fail_int_en_lsb 0
+#define xd_p_reg_ep1_tx_fail_int_en (*(volatile byte xdata *) 0xDD16)
+#define    p_reg_ep1_tx_fail_int_en 0xDD16
+#define reg_ep1_tx_fail_int_en_pos 2
+#define reg_ep1_tx_fail_int_en_len 1
+#define reg_ep1_tx_fail_int_en_lsb 0
+#define xd_p_reg_ep2_rx_fail_int_en (*(volatile byte xdata *) 0xDD16)
+#define    p_reg_ep2_rx_fail_int_en 0xDD16
+#define reg_ep2_rx_fail_int_en_pos 3
+#define reg_ep2_rx_fail_int_en_len 1
+#define reg_ep2_rx_fail_int_en_lsb 0
+#define xd_p_reg_ep3_tx_fail_int_en (*(volatile byte xdata *) 0xDD16)
+#define    p_reg_ep3_tx_fail_int_en 0xDD16
+#define reg_ep3_tx_fail_int_en_pos 4
+#define reg_ep3_tx_fail_int_en_len 1
+#define reg_ep3_tx_fail_int_en_lsb 0
+#define xd_p_reg_ep4_tx_fail_int_en (*(volatile byte xdata *) 0xDD16)
+#define    p_reg_ep4_tx_fail_int_en 0xDD16
+#define reg_ep4_tx_fail_int_en_pos 5
+#define reg_ep4_tx_fail_int_en_len 1
+#define reg_ep4_tx_fail_int_en_lsb 0
+#define xd_p_reg_ep5_tx_fail_int_en (*(volatile byte xdata *) 0xDD16)
+#define    p_reg_ep5_tx_fail_int_en 0xDD16
+#define reg_ep5_tx_fail_int_en_pos 6
+#define reg_ep5_tx_fail_int_en_len 1
+#define reg_ep5_tx_fail_int_en_lsb 0
+#define xd_p_reg_ep6_tx_fail_int_en (*(volatile byte xdata *) 0xDD16)
+#define    p_reg_ep6_tx_fail_int_en 0xDD16
+#define reg_ep6_tx_fail_int_en_pos 7
+#define reg_ep6_tx_fail_int_en_len 1
+#define reg_ep6_tx_fail_int_en_lsb 0
+#define xd_p_reg_suspend_int_en (*(volatile byte xdata *) 0xDD17)
+#define    p_reg_suspend_int_en 0xDD17
+#define reg_suspend_int_en_pos 0
+#define reg_suspend_int_en_len 1
+#define reg_suspend_int_en_lsb 0
+#define xd_p_reg_bus_reset_int_en   (*(volatile byte xdata *) 0xDD17)
+#define    p_reg_bus_reset_int_en   0xDD17
+#define reg_bus_reset_int_en_pos 1
+#define reg_bus_reset_int_en_len 1
+#define reg_bus_reset_int_en_lsb 0
+#define xd_p_reg_ep0_setup_int_en   (*(volatile byte xdata *) 0xDD17)
+#define    p_reg_ep0_setup_int_en   0xDD17
+#define reg_ep0_setup_int_en_pos 2
+#define reg_ep0_setup_int_en_len 1
+#define reg_ep0_setup_int_en_lsb 0
+#define xd_p_reg_ep0_tx_nak_int (*(volatile byte xdata *) 0xDD18)
+#define    p_reg_ep0_tx_nak_int 0xDD18
+#define reg_ep0_tx_nak_int_pos 0
+#define reg_ep0_tx_nak_int_len 1
+#define reg_ep0_tx_nak_int_lsb 0
+#define xd_p_reg_ep0_rx_nak_int (*(volatile byte xdata *) 0xDD18)
+#define    p_reg_ep0_rx_nak_int 0xDD18
+#define reg_ep0_rx_nak_int_pos 1
+#define reg_ep0_rx_nak_int_len 1
+#define reg_ep0_rx_nak_int_lsb 0
+#define xd_p_reg_ep1_tx_nak_int (*(volatile byte xdata *) 0xDD18)
+#define    p_reg_ep1_tx_nak_int 0xDD18
+#define reg_ep1_tx_nak_int_pos 2
+#define reg_ep1_tx_nak_int_len 1
+#define reg_ep1_tx_nak_int_lsb 0
+#define xd_p_reg_ep2_rx_nak_int (*(volatile byte xdata *) 0xDD18)
+#define    p_reg_ep2_rx_nak_int 0xDD18
+#define reg_ep2_rx_nak_int_pos 3
+#define reg_ep2_rx_nak_int_len 1
+#define reg_ep2_rx_nak_int_lsb 0
+#define xd_p_reg_ep3_tx_nak_int (*(volatile byte xdata *) 0xDD18)
+#define    p_reg_ep3_tx_nak_int 0xDD18
+#define reg_ep3_tx_nak_int_pos 4
+#define reg_ep3_tx_nak_int_len 1
+#define reg_ep3_tx_nak_int_lsb 0
+#define xd_p_reg_ep4_tx_nak_int (*(volatile byte xdata *) 0xDD18)
+#define    p_reg_ep4_tx_nak_int 0xDD18
+#define reg_ep4_tx_nak_int_pos 5
+#define reg_ep4_tx_nak_int_len 1
+#define reg_ep4_tx_nak_int_lsb 0
+#define xd_p_reg_ep5_tx_nak_int (*(volatile byte xdata *) 0xDD18)
+#define    p_reg_ep5_tx_nak_int 0xDD18
+#define reg_ep5_tx_nak_int_pos 6
+#define reg_ep5_tx_nak_int_len 1
+#define reg_ep5_tx_nak_int_lsb 0
+#define xd_p_reg_ep6_tx_nak_int (*(volatile byte xdata *) 0xDD18)
+#define    p_reg_ep6_tx_nak_int 0xDD18
+#define reg_ep6_tx_nak_int_pos 7
+#define reg_ep6_tx_nak_int_len 1
+#define reg_ep6_tx_nak_int_lsb 0
+#define xd_p_reg_ep0_tx_done_int    (*(volatile byte xdata *) 0xDD19)
+#define    p_reg_ep0_tx_done_int    0xDD19
+#define reg_ep0_tx_done_int_pos 0
+#define reg_ep0_tx_done_int_len 1
+#define reg_ep0_tx_done_int_lsb 0
+#define xd_p_reg_ep0_rx_done_int    (*(volatile byte xdata *) 0xDD19)
+#define    p_reg_ep0_rx_done_int    0xDD19
+#define reg_ep0_rx_done_int_pos 1
+#define reg_ep0_rx_done_int_len 1
+#define reg_ep0_rx_done_int_lsb 0
+#define xd_p_reg_ep1_tx_done_int    (*(volatile byte xdata *) 0xDD19)
+#define    p_reg_ep1_tx_done_int    0xDD19
+#define reg_ep1_tx_done_int_pos 2
+#define reg_ep1_tx_done_int_len 1
+#define reg_ep1_tx_done_int_lsb 0
+#define xd_p_reg_ep2_rx_done_int    (*(volatile byte xdata *) 0xDD19)
+#define    p_reg_ep2_rx_done_int    0xDD19
+#define reg_ep2_rx_done_int_pos 3
+#define reg_ep2_rx_done_int_len 1
+#define reg_ep2_rx_done_int_lsb 0
+#define xd_p_reg_ep3_tx_done_int    (*(volatile byte xdata *) 0xDD19)
+#define    p_reg_ep3_tx_done_int    0xDD19
+#define reg_ep3_tx_done_int_pos 4
+#define reg_ep3_tx_done_int_len 1
+#define reg_ep3_tx_done_int_lsb 0
+#define xd_p_reg_ep4_tx_done_int    (*(volatile byte xdata *) 0xDD19)
+#define    p_reg_ep4_tx_done_int    0xDD19
+#define reg_ep4_tx_done_int_pos 5
+#define reg_ep4_tx_done_int_len 1
+#define reg_ep4_tx_done_int_lsb 0
+#define xd_p_reg_ep5_tx_done_int    (*(volatile byte xdata *) 0xDD19)
+#define    p_reg_ep5_tx_done_int    0xDD19
+#define reg_ep5_tx_done_int_pos 6
+#define reg_ep5_tx_done_int_len 1
+#define reg_ep5_tx_done_int_lsb 0
+#define xd_p_reg_ep6_tx_done_int    (*(volatile byte xdata *) 0xDD19)
+#define    p_reg_ep6_tx_done_int    0xDD19
+#define reg_ep6_tx_done_int_pos 7
+#define reg_ep6_tx_done_int_len 1
+#define reg_ep6_tx_done_int_lsb 0
+#define xd_p_reg_ep0_tx_fail_int    (*(volatile byte xdata *) 0xDD1A)
+#define    p_reg_ep0_tx_fail_int    0xDD1A
+#define reg_ep0_tx_fail_int_pos 0
+#define reg_ep0_tx_fail_int_len 1
+#define reg_ep0_tx_fail_int_lsb 0
+#define xd_p_reg_ep0_rx_fail_int    (*(volatile byte xdata *) 0xDD1A)
+#define    p_reg_ep0_rx_fail_int    0xDD1A
+#define reg_ep0_rx_fail_int_pos 1
+#define reg_ep0_rx_fail_int_len 1
+#define reg_ep0_rx_fail_int_lsb 0
+#define xd_p_reg_ep1_tx_fail_int    (*(volatile byte xdata *) 0xDD1A)
+#define    p_reg_ep1_tx_fail_int    0xDD1A
+#define reg_ep1_tx_fail_int_pos 2
+#define reg_ep1_tx_fail_int_len 1
+#define reg_ep1_tx_fail_int_lsb 0
+#define xd_p_reg_ep2_rx_fail_int    (*(volatile byte xdata *) 0xDD1A)
+#define    p_reg_ep2_rx_fail_int    0xDD1A
+#define reg_ep2_rx_fail_int_pos 3
+#define reg_ep2_rx_fail_int_len 1
+#define reg_ep2_rx_fail_int_lsb 0
+#define xd_p_reg_ep3_tx_fail_int    (*(volatile byte xdata *) 0xDD1A)
+#define    p_reg_ep3_tx_fail_int    0xDD1A
+#define reg_ep3_tx_fail_int_pos 4
+#define reg_ep3_tx_fail_int_len 1
+#define reg_ep3_tx_fail_int_lsb 0
+#define xd_p_reg_ep4_tx_fail_int    (*(volatile byte xdata *) 0xDD1A)
+#define    p_reg_ep4_tx_fail_int    0xDD1A
+#define reg_ep4_tx_fail_int_pos 5
+#define reg_ep4_tx_fail_int_len 1
+#define reg_ep4_tx_fail_int_lsb 0
+#define xd_p_reg_ep5_tx_fail_int    (*(volatile byte xdata *) 0xDD1A)
+#define    p_reg_ep5_tx_fail_int    0xDD1A
+#define reg_ep5_tx_fail_int_pos 6
+#define reg_ep5_tx_fail_int_len 1
+#define reg_ep5_tx_fail_int_lsb 0
+#define xd_p_reg_ep6_tx_fail_int    (*(volatile byte xdata *) 0xDD1A)
+#define    p_reg_ep6_tx_fail_int    0xDD1A
+#define reg_ep6_tx_fail_int_pos 7
+#define reg_ep6_tx_fail_int_len 1
+#define reg_ep6_tx_fail_int_lsb 0
+#define xd_p_reg_suspend_int    (*(volatile byte xdata *) 0xDD1B)
+#define    p_reg_suspend_int    0xDD1B
+#define reg_suspend_int_pos 0
+#define reg_suspend_int_len 1
+#define reg_suspend_int_lsb 0
+#define xd_p_reg_bus_reset_int  (*(volatile byte xdata *) 0xDD1B)
+#define    p_reg_bus_reset_int  0xDD1B
+#define reg_bus_reset_int_pos 1
+#define reg_bus_reset_int_len 1
+#define reg_bus_reset_int_lsb 0
+#define xd_p_reg_ep0_setup_int  (*(volatile byte xdata *) 0xDD1B)
+#define    p_reg_ep0_setup_int  0xDD1B
+#define reg_ep0_setup_int_pos 2
+#define reg_ep0_setup_int_len 1
+#define reg_ep0_setup_int_lsb 0
+#define xd_r_usbc_int   (*(volatile byte xdata *) 0xDD1B)
+#define    r_usbc_int   0xDD1B
+#define usbc_int_pos 3
+#define usbc_int_len 1
+#define usbc_int_lsb 0
+#define xd_r_usb_ir_int (*(volatile byte xdata *) 0xDD1B)
+#define    r_usb_ir_int 0xDD1B
+#define usb_ir_int_pos 4
+#define usb_ir_int_len 1
+#define usb_ir_int_lsb 0
+#define xd_p_reg_ep0_tx_rst (*(volatile byte xdata *) 0xDD1D)
+#define    p_reg_ep0_tx_rst 0xDD1D
+#define reg_ep0_tx_rst_pos 0
+#define reg_ep0_tx_rst_len 1
+#define reg_ep0_tx_rst_lsb 0
+#define xd_p_reg_ep0_rx_rst (*(volatile byte xdata *) 0xDD1D)
+#define    p_reg_ep0_rx_rst 0xDD1D
+#define reg_ep0_rx_rst_pos 1
+#define reg_ep0_rx_rst_len 1
+#define reg_ep0_rx_rst_lsb 0
+#define xd_p_reg_ep1_tx_rst (*(volatile byte xdata *) 0xDD1D)
+#define    p_reg_ep1_tx_rst 0xDD1D
+#define reg_ep1_tx_rst_pos 2
+#define reg_ep1_tx_rst_len 1
+#define reg_ep1_tx_rst_lsb 0
+#define xd_p_reg_ep2_rx_rst (*(volatile byte xdata *) 0xDD1D)
+#define    p_reg_ep2_rx_rst 0xDD1D
+#define reg_ep2_rx_rst_pos 3
+#define reg_ep2_rx_rst_len 1
+#define reg_ep2_rx_rst_lsb 0
+#define xd_p_reg_ep3_tx_rst (*(volatile byte xdata *) 0xDD1D)
+#define    p_reg_ep3_tx_rst 0xDD1D
+#define reg_ep3_tx_rst_pos 4
+#define reg_ep3_tx_rst_len 1
+#define reg_ep3_tx_rst_lsb 0
+#define xd_p_reg_ep4_tx_rst (*(volatile byte xdata *) 0xDD1D)
+#define    p_reg_ep4_tx_rst 0xDD1D
+#define reg_ep4_tx_rst_pos 5
+#define reg_ep4_tx_rst_len 1
+#define reg_ep4_tx_rst_lsb 0
+#define xd_p_reg_ep5_tx_rst (*(volatile byte xdata *) 0xDD1D)
+#define    p_reg_ep5_tx_rst 0xDD1D
+#define reg_ep5_tx_rst_pos 6
+#define reg_ep5_tx_rst_len 1
+#define reg_ep5_tx_rst_lsb 0
+#define xd_p_reg_ep6_tx_rst (*(volatile byte xdata *) 0xDD1D)
+#define    p_reg_ep6_tx_rst 0xDD1D
+#define reg_ep6_tx_rst_pos 7
+#define reg_ep6_tx_rst_len 1
+#define reg_ep6_tx_rst_lsb 0
+#define xd_r_reg_ep0_tx_active  (*(volatile byte xdata *) 0xDD1E)
+#define    r_reg_ep0_tx_active  0xDD1E
+#define reg_ep0_tx_active_pos 0
+#define reg_ep0_tx_active_len 1
+#define reg_ep0_tx_active_lsb 0
+#define xd_r_reg_ep0_rx_active  (*(volatile byte xdata *) 0xDD1E)
+#define    r_reg_ep0_rx_active  0xDD1E
+#define reg_ep0_rx_active_pos 1
+#define reg_ep0_rx_active_len 1
+#define reg_ep0_rx_active_lsb 0
+#define xd_r_reg_ep1_tx_active  (*(volatile byte xdata *) 0xDD1E)
+#define    r_reg_ep1_tx_active  0xDD1E
+#define reg_ep1_tx_active_pos 2
+#define reg_ep1_tx_active_len 1
+#define reg_ep1_tx_active_lsb 0
+#define xd_r_reg_ep2_rx_active  (*(volatile byte xdata *) 0xDD1E)
+#define    r_reg_ep2_rx_active  0xDD1E
+#define reg_ep2_rx_active_pos 3
+#define reg_ep2_rx_active_len 1
+#define reg_ep2_rx_active_lsb 0
+#define xd_r_reg_ep3_tx_active  (*(volatile byte xdata *) 0xDD1E)
+#define    r_reg_ep3_tx_active  0xDD1E
+#define reg_ep3_tx_active_pos 4
+#define reg_ep3_tx_active_len 1
+#define reg_ep3_tx_active_lsb 0
+#define xd_r_reg_ep4_tx_active  (*(volatile byte xdata *) 0xDD1E)
+#define    r_reg_ep4_tx_active  0xDD1E
+#define reg_ep4_tx_active_pos 5
+#define reg_ep4_tx_active_len 1
+#define reg_ep4_tx_active_lsb 0
+#define xd_r_reg_ep5_tx_active  (*(volatile byte xdata *) 0xDD1E)
+#define    r_reg_ep5_tx_active  0xDD1E
+#define reg_ep5_tx_active_pos 6
+#define reg_ep5_tx_active_len 1
+#define reg_ep5_tx_active_lsb 0
+#define xd_r_reg_ep6_tx_active  (*(volatile byte xdata *) 0xDD1E)
+#define    r_reg_ep6_tx_active  0xDD1E
+#define reg_ep6_tx_active_pos 7
+#define reg_ep6_tx_active_len 1
+#define reg_ep6_tx_active_lsb 0
+#define xd_p_reg_usb_setup_reset    (*(volatile byte xdata *) 0xDD1F)
+#define    p_reg_usb_setup_reset    0xDD1F
+#define reg_usb_setup_reset_pos 0
+#define reg_usb_setup_reset_len 1
+#define reg_usb_setup_reset_lsb 0
+#define xd_p_reg_usb_ep4_retry_new  (*(volatile byte xdata *) 0xDD1F)
+#define    p_reg_usb_ep4_retry_new  0xDD1F
+#define reg_usb_ep4_retry_new_pos 1
+#define reg_usb_ep4_retry_new_len 1
+#define reg_usb_ep4_retry_new_lsb 0
+#define xd_p_reg_usb_ep5_retry_new  (*(volatile byte xdata *) 0xDD1F)
+#define    p_reg_usb_ep5_retry_new  0xDD1F
+#define reg_usb_ep5_retry_new_pos 2
+#define reg_usb_ep5_retry_new_len 1
+#define reg_usb_ep5_retry_new_lsb 0
+#define xd_p_reg_usb_ep6_retry_new  (*(volatile byte xdata *) 0xDD1F)
+#define    p_reg_usb_ep6_retry_new  0xDD1F
+#define reg_usb_ep6_retry_new_pos 3
+#define reg_usb_ep6_retry_new_len 1
+#define reg_usb_ep6_retry_new_lsb 0
+#define xd_p_reg_usb_iso_mult_cnt   (*(volatile byte xdata *) 0xDD20)
+#define    p_reg_usb_iso_mult_cnt   0xDD20
+#define reg_usb_iso_mult_cnt_pos 0
+#define reg_usb_iso_mult_cnt_len 2
+#define reg_usb_iso_mult_cnt_lsb 0
+#define xd_p_reg_p_iso_fix_en   (*(volatile byte xdata *) 0xDD21)
+#define    p_reg_p_iso_fix_en   0xDD21
+#define reg_p_iso_fix_en_pos 0
+#define reg_p_iso_fix_en_len 1
+#define reg_p_iso_fix_en_lsb 0
+#define xd_p_reg_p_iso_fix_rst  (*(volatile byte xdata *) 0xDD22)
+#define    p_reg_p_iso_fix_rst  0xDD22
+#define reg_p_iso_fix_rst_pos 0
+#define reg_p_iso_fix_rst_len 1
+#define reg_p_iso_fix_rst_lsb 0
+#define xd_p_reg_p_read_point_7_0   (*(volatile byte xdata *) 0xDD23)
+#define    p_reg_p_read_point_7_0   0xDD23
+#define reg_p_read_point_7_0_pos 0
+#define reg_p_read_point_7_0_len 8
+#define reg_p_read_point_7_0_lsb 0
+#define xd_p_reg_p_read_point_11_8  (*(volatile byte xdata *) 0xDD24)
+#define    p_reg_p_read_point_11_8  0xDD24
+#define reg_p_read_point_11_8_pos 0
+#define reg_p_read_point_11_8_len 4
+#define reg_p_read_point_11_8_lsb 8
+#define xd_p_reg_p_dbg_ctrl (*(volatile byte xdata *) 0xDD25)
+#define    p_reg_p_dbg_ctrl 0xDD25
+#define reg_p_dbg_ctrl_pos 0
+#define reg_p_dbg_ctrl_len 3
+#define reg_p_dbg_ctrl_lsb 0
+#define xd_p_reg_p_data_swap    (*(volatile byte xdata *) 0xDD26)
+#define    p_reg_p_data_swap    0xDD26
+#define reg_p_data_swap_pos 0
+#define reg_p_data_swap_len 2
+#define reg_p_data_swap_lsb 0
+#define xd_p_reg_ep_rx_addr (*(volatile byte xdata *) 0xDD80)
+#define    p_reg_ep_rx_addr 0xDD80
+#define reg_ep_rx_addr_pos 2
+#define reg_ep_rx_addr_len 6
+#define reg_ep_rx_addr_lsb 0
+#define xd_p_reg_ep0_tx_addr    (*(volatile byte xdata *) 0xDD81)
+#define    p_reg_ep0_tx_addr    0xDD81
+#define reg_ep0_tx_addr_pos 2
+#define reg_ep0_tx_addr_len 6
+#define reg_ep0_tx_addr_lsb 0
+#define xd_p_reg_ep1_tx_addr    (*(volatile byte xdata *) 0xDD82)
+#define    p_reg_ep1_tx_addr    0xDD82
+#define reg_ep1_tx_addr_pos 2
+#define reg_ep1_tx_addr_len 6
+#define reg_ep1_tx_addr_lsb 0
+#define xd_p_reg_ep3_tx_addr    (*(volatile byte xdata *) 0xDD83)
+#define    p_reg_ep3_tx_addr    0xDD83
+#define reg_ep3_tx_addr_pos 2
+#define reg_ep3_tx_addr_len 6
+#define reg_ep3_tx_addr_lsb 0
+#define xd_p_reg_ep_rx_len  (*(volatile byte xdata *) 0xDD84)
+#define    p_reg_ep_rx_len  0xDD84
+#define reg_ep_rx_len_pos 0
+#define reg_ep_rx_len_len 8
+#define reg_ep_rx_len_lsb 0
+#define xd_p_reg_ep0_tx_len (*(volatile byte xdata *) 0xDD85)
+#define    p_reg_ep0_tx_len 0xDD85
+#define reg_ep0_tx_len_pos 0
+#define reg_ep0_tx_len_len 8
+#define reg_ep0_tx_len_lsb 0
+#define xd_p_reg_ep1_tx_len (*(volatile byte xdata *) 0xDD86)
+#define    p_reg_ep1_tx_len 0xDD86
+#define reg_ep1_tx_len_pos 0
+#define reg_ep1_tx_len_len 8
+#define reg_ep1_tx_len_lsb 0
+#define xd_p_reg_ep3_tx_len (*(volatile byte xdata *) 0xDD87)
+#define    p_reg_ep3_tx_len 0xDD87
+#define reg_ep3_tx_len_pos 0
+#define reg_ep3_tx_len_len 8
+#define reg_ep3_tx_len_lsb 0
+#define xd_p_reg_ep4_tx_len_7_0 (*(volatile byte xdata *) 0xDD88)
+#define    p_reg_ep4_tx_len_7_0 0xDD88
+#define reg_ep4_tx_len_7_0_pos 0
+#define reg_ep4_tx_len_7_0_len 8
+#define reg_ep4_tx_len_7_0_lsb 0
+#define xd_p_reg_ep4_tx_len_15_8    (*(volatile byte xdata *) 0xDD89)
+#define    p_reg_ep4_tx_len_15_8    0xDD89
+#define reg_ep4_tx_len_15_8_pos 0
+#define reg_ep4_tx_len_15_8_len 8
+#define reg_ep4_tx_len_15_8_lsb 8
+#define xd_p_reg_ep5_tx_len_7_0 (*(volatile byte xdata *) 0xDD8A)
+#define    p_reg_ep5_tx_len_7_0 0xDD8A
+#define reg_ep5_tx_len_7_0_pos 0
+#define reg_ep5_tx_len_7_0_len 8
+#define reg_ep5_tx_len_7_0_lsb 0
+#define xd_p_reg_ep5_tx_len_15_8    (*(volatile byte xdata *) 0xDD8B)
+#define    p_reg_ep5_tx_len_15_8    0xDD8B
+#define reg_ep5_tx_len_15_8_pos 0
+#define reg_ep5_tx_len_15_8_len 8
+#define reg_ep5_tx_len_15_8_lsb 8
+#define xd_p_reg_usb_reset_addr (*(volatile byte xdata *) 0xDD8C)
+#define    p_reg_usb_reset_addr 0xDD8C
+#define reg_usb_reset_addr_pos 0
+#define reg_usb_reset_addr_len 7
+#define reg_usb_reset_addr_lsb 0
+#define xd_p_reg_usb_reset  (*(volatile byte xdata *) 0xDD8C)
+#define    p_reg_usb_reset  0xDD8C
+#define reg_usb_reset_pos 7
+#define reg_usb_reset_len 1
+#define reg_usb_reset_lsb 0
+#define xd_p_reg_usb_sync_in    (*(volatile byte xdata *) 0xDD8D)
+#define    p_reg_usb_sync_in    0xDD8D
+#define reg_usb_sync_in_pos 0
+#define reg_usb_sync_in_len 1
+#define reg_usb_sync_in_lsb 0
+#define xd_p_reg_usb_sync_txready   (*(volatile byte xdata *) 0xDD8D)
+#define    p_reg_usb_sync_txready   0xDD8D
+#define reg_usb_sync_txready_pos 1
+#define reg_usb_sync_txready_len 1
+#define reg_usb_sync_txready_lsb 0
+#define xd_p_reg_utmi_phy_suspend   (*(volatile byte xdata *) 0xDD8D)
+#define    p_reg_utmi_phy_suspend   0xDD8D
+#define reg_utmi_phy_suspend_pos 2
+#define reg_utmi_phy_suspend_len 1
+#define reg_utmi_phy_suspend_lsb 0
+#define xd_p_reg_usb_min_len    (*(volatile byte xdata *) 0xDD8D)
+#define    p_reg_usb_min_len    0xDD8D
+#define reg_usb_min_len_pos 3
+#define reg_usb_min_len_len 1
+#define reg_usb_min_len_lsb 0
+#define xd_p_reg_usb_phy_clksel (*(volatile byte xdata *) 0xDD8D)
+#define    p_reg_usb_phy_clksel 0xDD8D
+#define reg_usb_phy_clksel_pos 4
+#define reg_usb_phy_clksel_len 1
+#define reg_usb_phy_clksel_lsb 0
+#define xd_p_reg_ep6_tx_len_7_0 (*(volatile byte xdata *) 0xDD8E)
+#define    p_reg_ep6_tx_len_7_0 0xDD8E
+#define reg_ep6_tx_len_7_0_pos 0
+#define reg_ep6_tx_len_7_0_len 8
+#define reg_ep6_tx_len_7_0_lsb 0
+#define xd_p_reg_ep6_tx_len_15_8    (*(volatile byte xdata *) 0xDD8F)
+#define    p_reg_ep6_tx_len_15_8    0xDD8F
+#define reg_ep6_tx_len_15_8_pos 0
+#define reg_ep6_tx_len_15_8_len 8
+#define reg_ep6_tx_len_15_8_lsb 8
+#define xd_p_reg_usb_clk_phase  (*(volatile byte xdata *) 0xDD93)
+#define    p_reg_usb_clk_phase  0xDD93
+#define reg_usb_clk_phase_pos 0
+#define reg_usb_clk_phase_len 2
+#define reg_usb_clk_phase_lsb 0
+#define xd_p_reg_usb_clk_sel    (*(volatile byte xdata *) 0xDD93)
+#define    p_reg_usb_clk_sel    0xDD93
+#define reg_usb_clk_sel_pos 4
+#define reg_usb_clk_sel_len 4
+#define reg_usb_clk_sel_lsb 0
+#define xd_p_reg_usb_fifo_ptr   (*(volatile byte xdata *) 0xDD94)
+#define    p_reg_usb_fifo_ptr   0xDD94
+#define reg_usb_fifo_ptr_pos 0
+#define reg_usb_fifo_ptr_len 3
+#define reg_usb_fifo_ptr_lsb 0
+#define xd_p_reg_usb_fifo_byte  (*(volatile byte xdata *) 0xDD94)
+#define    p_reg_usb_fifo_byte  0xDD94
+#define reg_usb_fifo_byte_pos 3
+#define reg_usb_fifo_byte_len 2
+#define reg_usb_fifo_byte_lsb 0
+#define xd_p_reg_usb_fifo_sys   (*(volatile byte xdata *) 0xDD94)
+#define    p_reg_usb_fifo_sys   0xDD94
+#define reg_usb_fifo_sys_pos 5
+#define reg_usb_fifo_sys_len 1
+#define reg_usb_fifo_sys_lsb 0
+#define xd_p_usbdma_utmi_d_ctl_7_0  (*(volatile byte xdata *) 0xDD9E)
+#define    p_usbdma_utmi_d_ctl_7_0  0xDD9E
+#define usbdma_utmi_d_ctl_7_0_pos 0
+#define usbdma_utmi_d_ctl_7_0_len 8
+#define usbdma_utmi_d_ctl_7_0_lsb 0
+#define xd_p_usbdma_utmi_d_ctl_13_8 (*(volatile byte xdata *) 0xDD9F)
+#define    p_usbdma_utmi_d_ctl_13_8 0xDD9F
+#define usbdma_utmi_d_ctl_13_8_pos 0
+#define usbdma_utmi_d_ctl_13_8_len 6
+#define usbdma_utmi_d_ctl_13_8_lsb 8
+#define xd_p_usbdma_utmi_a_ctl_7_0  (*(volatile byte xdata *) 0xDDA0)
+#define    p_usbdma_utmi_a_ctl_7_0  0xDDA0
+#define usbdma_utmi_a_ctl_7_0_pos 0
+#define usbdma_utmi_a_ctl_7_0_len 8
+#define usbdma_utmi_a_ctl_7_0_lsb 0
+#define xd_p_usbdma_utmi_a_ctl_15_8 (*(volatile byte xdata *) 0xDDA1)
+#define    p_usbdma_utmi_a_ctl_15_8 0xDDA1
+#define usbdma_utmi_a_ctl_15_8_pos 0
+#define usbdma_utmi_a_ctl_15_8_len 8
+#define usbdma_utmi_a_ctl_15_8_lsb 8
+#define xd_p_usbdma_utmi_a_ctl_23_16    (*(volatile byte xdata *) 0xDDA2)
+#define    p_usbdma_utmi_a_ctl_23_16    0xDDA2
+#define usbdma_utmi_a_ctl_23_16_pos 0
+#define usbdma_utmi_a_ctl_23_16_len 8
+#define usbdma_utmi_a_ctl_23_16_lsb 16
+#define xd_p_usbdma_utmi_a_ctl_31_24    (*(volatile byte xdata *) 0xDDA3)
+#define    p_usbdma_utmi_a_ctl_31_24    0xDDA3
+#define usbdma_utmi_a_ctl_31_24_pos 0
+#define usbdma_utmi_a_ctl_31_24_len 8
+#define usbdma_utmi_a_ctl_31_24_lsb 24
+#define xd_p_usbdma_utmi_a_ctl_39_32    (*(volatile byte xdata *) 0xDDA4)
+#define    p_usbdma_utmi_a_ctl_39_32    0xDDA4
+#define usbdma_utmi_a_ctl_39_32_pos 0
+#define usbdma_utmi_a_ctl_39_32_len 8
+#define usbdma_utmi_a_ctl_39_32_lsb 32
+#define xd_p_usbdma_utmi_a_ctl_47_40    (*(volatile byte xdata *) 0xDDA5)
+#define    p_usbdma_utmi_a_ctl_47_40    0xDDA5
+#define usbdma_utmi_a_ctl_47_40_pos 0
+#define usbdma_utmi_a_ctl_47_40_len 8
+#define usbdma_utmi_a_ctl_47_40_lsb 40
+#define xd_p_usbdma_utmi_pwrmode    (*(volatile byte xdata *) 0xDDA6)
+#define    p_usbdma_utmi_pwrmode    0xDDA6
+#define usbdma_utmi_pwrmode_pos 3
+#define usbdma_utmi_pwrmode_len 1
+#define usbdma_utmi_pwrmode_lsb 0
+#define xd_p_usbdma_utmi_test_out   (*(volatile byte xdata *) 0xDDA6)
+#define    p_usbdma_utmi_test_out   0xDDA6
+#define usbdma_utmi_test_out_pos 4
+#define usbdma_utmi_test_out_len 1
+#define usbdma_utmi_test_out_lsb 0
+#define xd_p_usbdma_utmi_vbus_int_en    (*(volatile byte xdata *) 0xDDA7)
+#define    p_usbdma_utmi_vbus_int_en    0xDDA7
+#define usbdma_utmi_vbus_int_en_pos 0
+#define usbdma_utmi_vbus_int_en_len 1
+#define usbdma_utmi_vbus_int_en_lsb 0
+#define xd_p_usbdma_utmi_vbus_int_pol   (*(volatile byte xdata *) 0xDDA7)
+#define    p_usbdma_utmi_vbus_int_pol   0xDDA7
+#define usbdma_utmi_vbus_int_pol_pos 1
+#define usbdma_utmi_vbus_int_pol_len 1
+#define usbdma_utmi_vbus_int_pol_lsb 0
+#define xd_r_usbdma_utmi_vbus_int   (*(volatile byte xdata *) 0xDDA8)
+#define    r_usbdma_utmi_vbus_int   0xDDA8
+#define usbdma_utmi_vbus_int_pos 0
+#define usbdma_utmi_vbus_int_len 1
+#define usbdma_utmi_vbus_int_lsb 0
+#define xd_r_usbdma_utmi_vbus_status    (*(volatile byte xdata *) 0xDDA8)
+#define    r_usbdma_utmi_vbus_status    0xDDA8
+#define usbdma_utmi_vbus_status_pos 1
+#define usbdma_utmi_vbus_status_len 1
+#define usbdma_utmi_vbus_status_lsb 0
+#define xd_r_usbdma_utmi_clkrdy (*(volatile byte xdata *) 0xDDA8)
+#define    r_usbdma_utmi_clkrdy 0xDDA8
+#define usbdma_utmi_clkrdy_pos 2
+#define usbdma_utmi_clkrdy_len 1
+#define usbdma_utmi_clkrdy_lsb 0
+#define xd_p_reg_p_usb_iso_ccir_rst (*(volatile byte xdata *) 0xDDA9)
+#define    p_reg_p_usb_iso_ccir_rst 0xDDA9
+#define reg_p_usb_iso_ccir_rst_pos 0
+#define reg_p_usb_iso_ccir_rst_len 1
+#define reg_p_usb_iso_ccir_rst_lsb 0
+#define xd_p_reg_p_usb_iso_ccir (*(volatile byte xdata *) 0xDDA9)
+#define    p_reg_p_usb_iso_ccir 0xDDA9
+#define reg_p_usb_iso_ccir_pos 1
+#define reg_p_usb_iso_ccir_len 1
+#define reg_p_usb_iso_ccir_lsb 0
+#define xd_p_reg_p_ccir_fix_en  (*(volatile byte xdata *) 0xDDAA)
+#define    p_reg_p_ccir_fix_en  0xDDAA
+#define reg_p_ccir_fix_en_pos 0
+#define reg_p_ccir_fix_en_len 1
+#define reg_p_ccir_fix_en_lsb 0
+#define xd_p_ir_sys_clk (*(volatile byte xdata *) 0xDF80)
+#define    p_ir_sys_clk 0xDF80
+#define ir_sys_clk_pos 0
+#define ir_sys_clk_len 8
+#define ir_sys_clk_lsb 0
+#define xd_p_ir_sample_clk  (*(volatile byte xdata *) 0xDF81)
+#define    p_ir_sample_clk  0xDF81
+#define ir_sample_clk_pos 0
+#define ir_sample_clk_len 2
+#define ir_sample_clk_lsb 0
+#define xd_p_ir_idle_polarity   (*(volatile byte xdata *) 0xDF81)
+#define    p_ir_idle_polarity   0xDF81
+#define ir_idle_polarity_pos 2
+#define ir_idle_polarity_len 1
+#define ir_idle_polarity_lsb 0
+#define xd_p_ir_fifo_ovfl   (*(volatile byte xdata *) 0xDF82)
+#define    p_ir_fifo_ovfl   0xDF82
+#define ir_fifo_ovfl_pos 0
+#define ir_fifo_ovfl_len 1
+#define ir_fifo_ovfl_lsb 0
+#define xd_r_ir_fifo_empty  (*(volatile byte xdata *) 0xDF82)
+#define    r_ir_fifo_empty  0xDF82
+#define ir_fifo_empty_pos 1
+#define ir_fifo_empty_len 1
+#define ir_fifo_empty_lsb 0
+#define xd_r_ir_fifo_cnt    (*(volatile byte xdata *) 0xDF82)
+#define    r_ir_fifo_cnt    0xDF82
+#define ir_fifo_cnt_pos 2
+#define ir_fifo_cnt_len 3
+#define ir_fifo_cnt_lsb 0
+#define xd_p_ir_fifo_rst    (*(volatile byte xdata *) 0xDF82)
+#define    p_ir_fifo_rst    0xDF82
+#define ir_fifo_rst_pos 5
+#define ir_fifo_rst_len 1
+#define ir_fifo_rst_lsb 0
+#define xd_p_reg_ir_out_th0_7_0 (*(volatile byte xdata *) 0xDF84)
+#define    p_reg_ir_out_th0_7_0 0xDF84
+#define reg_ir_out_th0_7_0_pos 0
+#define reg_ir_out_th0_7_0_len 8
+#define reg_ir_out_th0_7_0_lsb 0
+#define xd_p_reg_ir_out_th0_14_8    (*(volatile byte xdata *) 0xDF85)
+#define    p_reg_ir_out_th0_14_8    0xDF85
+#define reg_ir_out_th0_14_8_pos 0
+#define reg_ir_out_th0_14_8_len 7
+#define reg_ir_out_th0_14_8_lsb 8
+#define xd_p_reg_ir_out_th1_7_0 (*(volatile byte xdata *) 0xDF86)
+#define    p_reg_ir_out_th1_7_0 0xDF86
+#define reg_ir_out_th1_7_0_pos 0
+#define reg_ir_out_th1_7_0_len 8
+#define reg_ir_out_th1_7_0_lsb 0
+#define xd_p_reg_ir_out_th1_14_8    (*(volatile byte xdata *) 0xDF87)
+#define    p_reg_ir_out_th1_14_8    0xDF87
+#define reg_ir_out_th1_14_8_pos 0
+#define reg_ir_out_th1_14_8_len 7
+#define reg_ir_out_th1_14_8_lsb 8
+#define xd_p_reg_ir_out_th2_7_0 (*(volatile byte xdata *) 0xDF88)
+#define    p_reg_ir_out_th2_7_0 0xDF88
+#define reg_ir_out_th2_7_0_pos 0
+#define reg_ir_out_th2_7_0_len 8
+#define reg_ir_out_th2_7_0_lsb 0
+#define xd_p_reg_ir_out_th2_14_8    (*(volatile byte xdata *) 0xDF89)
+#define    p_reg_ir_out_th2_14_8    0xDF89
+#define reg_ir_out_th2_14_8_pos 0
+#define reg_ir_out_th2_14_8_len 7
+#define reg_ir_out_th2_14_8_lsb 8
+#define xd_p_reg_ir_out_th3_7_0 (*(volatile byte xdata *) 0xDF8A)
+#define    p_reg_ir_out_th3_7_0 0xDF8A
+#define reg_ir_out_th3_7_0_pos 0
+#define reg_ir_out_th3_7_0_len 8
+#define reg_ir_out_th3_7_0_lsb 0
+#define xd_p_reg_ir_out_th3_14_8    (*(volatile byte xdata *) 0xDF8B)
+#define    p_reg_ir_out_th3_14_8    0xDF8B
+#define reg_ir_out_th3_14_8_pos 0
+#define reg_ir_out_th3_14_8_len 7
+#define reg_ir_out_th3_14_8_lsb 8
+#define xd_p_reg_ir_out_th4_7_0 (*(volatile byte xdata *) 0xDF8C)
+#define    p_reg_ir_out_th4_7_0 0xDF8C
+#define reg_ir_out_th4_7_0_pos 0
+#define reg_ir_out_th4_7_0_len 8
+#define reg_ir_out_th4_7_0_lsb 0
+#define xd_p_reg_ir_out_th4_14_8    (*(volatile byte xdata *) 0xDF8D)
+#define    p_reg_ir_out_th4_14_8    0xDF8D
+#define reg_ir_out_th4_14_8_pos 0
+#define reg_ir_out_th4_14_8_len 7
+#define reg_ir_out_th4_14_8_lsb 8
+#define xd_p_reg_ir_out_th5_7_0 (*(volatile byte xdata *) 0xDF8E)
+#define    p_reg_ir_out_th5_7_0 0xDF8E
+#define reg_ir_out_th5_7_0_pos 0
+#define reg_ir_out_th5_7_0_len 8
+#define reg_ir_out_th5_7_0_lsb 0
+#define xd_p_reg_ir_out_th5_14_8    (*(volatile byte xdata *) 0xDF8F)
+#define    p_reg_ir_out_th5_14_8    0xDF8F
+#define reg_ir_out_th5_14_8_pos 0
+#define reg_ir_out_th5_14_8_len 7
+#define reg_ir_out_th5_14_8_lsb 8
+#define xd_p_reg_ir_out_th6_7_0 (*(volatile byte xdata *) 0xDF90)
+#define    p_reg_ir_out_th6_7_0 0xDF90
+#define reg_ir_out_th6_7_0_pos 0
+#define reg_ir_out_th6_7_0_len 8
+#define reg_ir_out_th6_7_0_lsb 0
+#define xd_p_reg_ir_out_th6_14_8    (*(volatile byte xdata *) 0xDF91)
+#define    p_reg_ir_out_th6_14_8    0xDF91
+#define reg_ir_out_th6_14_8_pos 0
+#define reg_ir_out_th6_14_8_len 7
+#define reg_ir_out_th6_14_8_lsb 8
+#define xd_p_reg_ir_out_th7_7_0 (*(volatile byte xdata *) 0xDF92)
+#define    p_reg_ir_out_th7_7_0 0xDF92
+#define reg_ir_out_th7_7_0_pos 0
+#define reg_ir_out_th7_7_0_len 8
+#define reg_ir_out_th7_7_0_lsb 0
+#define xd_p_reg_ir_out_th7_14_8    (*(volatile byte xdata *) 0xDF93)
+#define    p_reg_ir_out_th7_14_8    0xDF93
+#define reg_ir_out_th7_14_8_pos 0
+#define reg_ir_out_th7_14_8_len 7
+#define reg_ir_out_th7_14_8_lsb 8
+#define xd_p_reg_ir_out_th8_7_0 (*(volatile byte xdata *) 0xDF94)
+#define    p_reg_ir_out_th8_7_0 0xDF94
+#define reg_ir_out_th8_7_0_pos 0
+#define reg_ir_out_th8_7_0_len 8
+#define reg_ir_out_th8_7_0_lsb 0
+#define xd_p_reg_ir_out_th8_14_8    (*(volatile byte xdata *) 0xDF95)
+#define    p_reg_ir_out_th8_14_8    0xDF95
+#define reg_ir_out_th8_14_8_pos 0
+#define reg_ir_out_th8_14_8_len 7
+#define reg_ir_out_th8_14_8_lsb 8
+#define xd_p_reg_ir_out_th9_7_0 (*(volatile byte xdata *) 0xDF96)
+#define    p_reg_ir_out_th9_7_0 0xDF96
+#define reg_ir_out_th9_7_0_pos 0
+#define reg_ir_out_th9_7_0_len 8
+#define reg_ir_out_th9_7_0_lsb 0
+#define xd_p_reg_ir_out_th9_14_8    (*(volatile byte xdata *) 0xDF97)
+#define    p_reg_ir_out_th9_14_8    0xDF97
+#define reg_ir_out_th9_14_8_pos 0
+#define reg_ir_out_th9_14_8_len 7
+#define reg_ir_out_th9_14_8_lsb 8
+#define xd_p_reg_ir_out_th10_7_0    (*(volatile byte xdata *) 0xDF98)
+#define    p_reg_ir_out_th10_7_0    0xDF98
+#define reg_ir_out_th10_7_0_pos 0
+#define reg_ir_out_th10_7_0_len 8
+#define reg_ir_out_th10_7_0_lsb 0
+#define xd_p_reg_ir_out_th10_14_8   (*(volatile byte xdata *) 0xDF99)
+#define    p_reg_ir_out_th10_14_8   0xDF99
+#define reg_ir_out_th10_14_8_pos 0
+#define reg_ir_out_th10_14_8_len 7
+#define reg_ir_out_th10_14_8_lsb 8
+#define xd_p_reg_ir_out_th11_7_0    (*(volatile byte xdata *) 0xDF9A)
+#define    p_reg_ir_out_th11_7_0    0xDF9A
+#define reg_ir_out_th11_7_0_pos 0
+#define reg_ir_out_th11_7_0_len 8
+#define reg_ir_out_th11_7_0_lsb 0
+#define xd_p_reg_ir_out_th11_14_8   (*(volatile byte xdata *) 0xDF9B)
+#define    p_reg_ir_out_th11_14_8   0xDF9B
+#define reg_ir_out_th11_14_8_pos 0
+#define reg_ir_out_th11_14_8_len 7
+#define reg_ir_out_th11_14_8_lsb 8
+#define xd_p_reg_ir_out_th12_7_0    (*(volatile byte xdata *) 0xDF9C)
+#define    p_reg_ir_out_th12_7_0    0xDF9C
+#define reg_ir_out_th12_7_0_pos 0
+#define reg_ir_out_th12_7_0_len 8
+#define reg_ir_out_th12_7_0_lsb 0
+#define xd_p_reg_ir_out_th12_14_8   (*(volatile byte xdata *) 0xDF9D)
+#define    p_reg_ir_out_th12_14_8   0xDF9D
+#define reg_ir_out_th12_14_8_pos 0
+#define reg_ir_out_th12_14_8_len 7
+#define reg_ir_out_th12_14_8_lsb 8
+#define xd_p_reg_ir_out_th13_7_0    (*(volatile byte xdata *) 0xDF9E)
+#define    p_reg_ir_out_th13_7_0    0xDF9E
+#define reg_ir_out_th13_7_0_pos 0
+#define reg_ir_out_th13_7_0_len 8
+#define reg_ir_out_th13_7_0_lsb 0
+#define xd_p_reg_ir_out_th13_14_8   (*(volatile byte xdata *) 0xDF9F)
+#define    p_reg_ir_out_th13_14_8   0xDF9F
+#define reg_ir_out_th13_14_8_pos 0
+#define reg_ir_out_th13_14_8_len 7
+#define reg_ir_out_th13_14_8_lsb 8
+#define xd_p_reg_ir_out_th14_7_0    (*(volatile byte xdata *) 0xDFA0)
+#define    p_reg_ir_out_th14_7_0    0xDFA0
+#define reg_ir_out_th14_7_0_pos 0
+#define reg_ir_out_th14_7_0_len 8
+#define reg_ir_out_th14_7_0_lsb 0
+#define xd_p_reg_ir_out_th14_14_8   (*(volatile byte xdata *) 0xDFA1)
+#define    p_reg_ir_out_th14_14_8   0xDFA1
+#define reg_ir_out_th14_14_8_pos 0
+#define reg_ir_out_th14_14_8_len 7
+#define reg_ir_out_th14_14_8_lsb 8
+#define xd_p_reg_tuner_data_7_0 (*(volatile byte xdata *) 0xF000)
+#define    p_reg_tuner_data_7_0 0xF000
+#define reg_tuner_data_7_0_pos 0
+#define reg_tuner_data_7_0_len 8
+#define reg_tuner_data_7_0_lsb 0
+#define xd_p_reg_tuner_data_15_8    (*(volatile byte xdata *) 0xF001)
+#define    p_reg_tuner_data_15_8    0xF001
+#define reg_tuner_data_15_8_pos 0
+#define reg_tuner_data_15_8_len 8
+#define reg_tuner_data_15_8_lsb 8
+#define xd_p_reg_tuner_data_23_16   (*(volatile byte xdata *) 0xF002)
+#define    p_reg_tuner_data_23_16   0xF002
+#define reg_tuner_data_23_16_pos 0
+#define reg_tuner_data_23_16_len 8
+#define reg_tuner_data_23_16_lsb 16
+#define xd_p_reg_tuner_data_31_24   (*(volatile byte xdata *) 0xF003)
+#define    p_reg_tuner_data_31_24   0xF003
+#define reg_tuner_data_31_24_pos 0
+#define reg_tuner_data_31_24_len 8
+#define reg_tuner_data_31_24_lsb 24
+#define xd_p_reg_tuner_data_39_32   (*(volatile byte xdata *) 0xF004)
+#define    p_reg_tuner_data_39_32   0xF004
+#define reg_tuner_data_39_32_pos 0
+#define reg_tuner_data_39_32_len 8
+#define reg_tuner_data_39_32_lsb 32
+#define xd_p_reg_tuner_data_47_40   (*(volatile byte xdata *) 0xF005)
+#define    p_reg_tuner_data_47_40   0xF005
+#define reg_tuner_data_47_40_pos 0
+#define reg_tuner_data_47_40_len 8
+#define reg_tuner_data_47_40_lsb 40
+#define xd_p_reg_tuner_data_55_48   (*(volatile byte xdata *) 0xF006)
+#define    p_reg_tuner_data_55_48   0xF006
+#define reg_tuner_data_55_48_pos 0
+#define reg_tuner_data_55_48_len 8
+#define reg_tuner_data_55_48_lsb 48
+#define xd_p_reg_tuner_data_63_56   (*(volatile byte xdata *) 0xF007)
+#define    p_reg_tuner_data_63_56   0xF007
+#define reg_tuner_data_63_56_pos 0
+#define reg_tuner_data_63_56_len 8
+#define reg_tuner_data_63_56_lsb 56
+#define xd_p_reg_tuner_data_71_64   (*(volatile byte xdata *) 0xF008)
+#define    p_reg_tuner_data_71_64   0xF008
+#define reg_tuner_data_71_64_pos 0
+#define reg_tuner_data_71_64_len 8
+#define reg_tuner_data_71_64_lsb 64
+#define xd_p_reg_tuner_data_79_72   (*(volatile byte xdata *) 0xF009)
+#define    p_reg_tuner_data_79_72   0xF009
+#define reg_tuner_data_79_72_pos 0
+#define reg_tuner_data_79_72_len 8
+#define reg_tuner_data_79_72_lsb 72
+#define xd_p_reg_tuner_data_87_80   (*(volatile byte xdata *) 0xF00A)
+#define    p_reg_tuner_data_87_80   0xF00A
+#define reg_tuner_data_87_80_pos 0
+#define reg_tuner_data_87_80_len 8
+#define reg_tuner_data_87_80_lsb 80
+#define xd_p_reg_tuner_data_95_88   (*(volatile byte xdata *) 0xF00B)
+#define    p_reg_tuner_data_95_88   0xF00B
+#define reg_tuner_data_95_88_pos 0
+#define reg_tuner_data_95_88_len 8
+#define reg_tuner_data_95_88_lsb 88
+#define xd_p_reg_tuner_data_103_96  (*(volatile byte xdata *) 0xF00C)
+#define    p_reg_tuner_data_103_96  0xF00C
+#define reg_tuner_data_103_96_pos 0
+#define reg_tuner_data_103_96_len 8
+#define reg_tuner_data_103_96_lsb 96
+#define xd_p_reg_tuner_data_111_104 (*(volatile byte xdata *) 0xF00D)
+#define    p_reg_tuner_data_111_104 0xF00D
+#define reg_tuner_data_111_104_pos 0
+#define reg_tuner_data_111_104_len 8
+#define reg_tuner_data_111_104_lsb 104
+#define xd_p_reg_tuner_data_119_112 (*(volatile byte xdata *) 0xF00E)
+#define    p_reg_tuner_data_119_112 0xF00E
+#define reg_tuner_data_119_112_pos 0
+#define reg_tuner_data_119_112_len 8
+#define reg_tuner_data_119_112_lsb 112
+#define xd_p_reg_tuner_data_127_120 (*(volatile byte xdata *) 0xF00F)
+#define    p_reg_tuner_data_127_120 0xF00F
+#define reg_tuner_data_127_120_pos 0
+#define reg_tuner_data_127_120_len 8
+#define reg_tuner_data_127_120_lsb 120
+#define xd_p_reg_tuner_data_135_128 (*(volatile byte xdata *) 0xF010)
+#define    p_reg_tuner_data_135_128 0xF010
+#define reg_tuner_data_135_128_pos 0
+#define reg_tuner_data_135_128_len 8
+#define reg_tuner_data_135_128_lsb 128
+#define xd_p_reg_tuner_data_143_136 (*(volatile byte xdata *) 0xF011)
+#define    p_reg_tuner_data_143_136 0xF011
+#define reg_tuner_data_143_136_pos 0
+#define reg_tuner_data_143_136_len 8
+#define reg_tuner_data_143_136_lsb 136
+#define xd_p_reg_tuner_data_151_144 (*(volatile byte xdata *) 0xF012)
+#define    p_reg_tuner_data_151_144 0xF012
+#define reg_tuner_data_151_144_pos 0
+#define reg_tuner_data_151_144_len 8
+#define reg_tuner_data_151_144_lsb 144
+#define xd_p_reg_tuner_data_159_152 (*(volatile byte xdata *) 0xF013)
+#define    p_reg_tuner_data_159_152 0xF013
+#define reg_tuner_data_159_152_pos 0
+#define reg_tuner_data_159_152_len 8
+#define reg_tuner_data_159_152_lsb 152
+#define xd_p_reg_tuner_data_167_160 (*(volatile byte xdata *) 0xF014)
+#define    p_reg_tuner_data_167_160 0xF014
+#define reg_tuner_data_167_160_pos 0
+#define reg_tuner_data_167_160_len 8
+#define reg_tuner_data_167_160_lsb 160
+#define xd_p_reg_tuner_data_175_168 (*(volatile byte xdata *) 0xF015)
+#define    p_reg_tuner_data_175_168 0xF015
+#define reg_tuner_data_175_168_pos 0
+#define reg_tuner_data_175_168_len 8
+#define reg_tuner_data_175_168_lsb 168
+#define xd_p_reg_tuner_data_183_176 (*(volatile byte xdata *) 0xF016)
+#define    p_reg_tuner_data_183_176 0xF016
+#define reg_tuner_data_183_176_pos 0
+#define reg_tuner_data_183_176_len 8
+#define reg_tuner_data_183_176_lsb 176
+#define xd_p_reg_tuner_data_191_184 (*(volatile byte xdata *) 0xF017)
+#define    p_reg_tuner_data_191_184 0xF017
+#define reg_tuner_data_191_184_pos 0
+#define reg_tuner_data_191_184_len 8
+#define reg_tuner_data_191_184_lsb 184
+#define xd_p_reg_tuner_data_199_192 (*(volatile byte xdata *) 0xF018)
+#define    p_reg_tuner_data_199_192 0xF018
+#define reg_tuner_data_199_192_pos 0
+#define reg_tuner_data_199_192_len 8
+#define reg_tuner_data_199_192_lsb 192
+#define xd_p_reg_tuner_data_207_200 (*(volatile byte xdata *) 0xF019)
+#define    p_reg_tuner_data_207_200 0xF019
+#define reg_tuner_data_207_200_pos 0
+#define reg_tuner_data_207_200_len 8
+#define reg_tuner_data_207_200_lsb 200
+#define xd_p_reg_tuner_data_215_208 (*(volatile byte xdata *) 0xF01A)
+#define    p_reg_tuner_data_215_208 0xF01A
+#define reg_tuner_data_215_208_pos 0
+#define reg_tuner_data_215_208_len 8
+#define reg_tuner_data_215_208_lsb 208
+#define xd_p_reg_tuner_data_223_216 (*(volatile byte xdata *) 0xF01B)
+#define    p_reg_tuner_data_223_216 0xF01B
+#define reg_tuner_data_223_216_pos 0
+#define reg_tuner_data_223_216_len 8
+#define reg_tuner_data_223_216_lsb 216
+#define xd_p_reg_tuner_data_231_224 (*(volatile byte xdata *) 0xF01C)
+#define    p_reg_tuner_data_231_224 0xF01C
+#define reg_tuner_data_231_224_pos 0
+#define reg_tuner_data_231_224_len 8
+#define reg_tuner_data_231_224_lsb 224
+#define xd_p_reg_tuner_data_239_232 (*(volatile byte xdata *) 0xF01D)
+#define    p_reg_tuner_data_239_232 0xF01D
+#define reg_tuner_data_239_232_pos 0
+#define reg_tuner_data_239_232_len 8
+#define reg_tuner_data_239_232_lsb 232
+#define xd_p_reg_tuner_data_247_240 (*(volatile byte xdata *) 0xF01E)
+#define    p_reg_tuner_data_247_240 0xF01E
+#define reg_tuner_data_247_240_pos 0
+#define reg_tuner_data_247_240_len 8
+#define reg_tuner_data_247_240_lsb 240
+#define xd_p_reg_tuner_data_255_248 (*(volatile byte xdata *) 0xF01F)
+#define    p_reg_tuner_data_255_248 0xF01F
+#define reg_tuner_data_255_248_pos 0
+#define reg_tuner_data_255_248_len 8
+#define reg_tuner_data_255_248_lsb 248
+#define xd_p_reg_tuner_data_263_256 (*(volatile byte xdata *) 0xF020)
+#define    p_reg_tuner_data_263_256 0xF020
+#define reg_tuner_data_263_256_pos 0
+#define reg_tuner_data_263_256_len 8
+#define reg_tuner_data_263_256_lsb 256
+#define xd_p_reg_tuner_data_271_264 (*(volatile byte xdata *) 0xF021)
+#define    p_reg_tuner_data_271_264 0xF021
+#define reg_tuner_data_271_264_pos 0
+#define reg_tuner_data_271_264_len 8
+#define reg_tuner_data_271_264_lsb 264
+#define xd_p_reg_tuner_data_279_272 (*(volatile byte xdata *) 0xF022)
+#define    p_reg_tuner_data_279_272 0xF022
+#define reg_tuner_data_279_272_pos 0
+#define reg_tuner_data_279_272_len 8
+#define reg_tuner_data_279_272_lsb 272
+#define xd_p_reg_tuner_data_287_280 (*(volatile byte xdata *) 0xF023)
+#define    p_reg_tuner_data_287_280 0xF023
+#define reg_tuner_data_287_280_pos 0
+#define reg_tuner_data_287_280_len 8
+#define reg_tuner_data_287_280_lsb 280
+#define xd_p_reg_tuner_data_295_288 (*(volatile byte xdata *) 0xF024)
+#define    p_reg_tuner_data_295_288 0xF024
+#define reg_tuner_data_295_288_pos 0
+#define reg_tuner_data_295_288_len 8
+#define reg_tuner_data_295_288_lsb 288
+#define xd_p_reg_tuner_data_303_296 (*(volatile byte xdata *) 0xF025)
+#define    p_reg_tuner_data_303_296 0xF025
+#define reg_tuner_data_303_296_pos 0
+#define reg_tuner_data_303_296_len 8
+#define reg_tuner_data_303_296_lsb 296
+#define xd_p_reg_tuner_data_311_304 (*(volatile byte xdata *) 0xF026)
+#define    p_reg_tuner_data_311_304 0xF026
+#define reg_tuner_data_311_304_pos 0
+#define reg_tuner_data_311_304_len 8
+#define reg_tuner_data_311_304_lsb 304
+#define xd_p_reg_tuner_data_319_312 (*(volatile byte xdata *) 0xF027)
+#define    p_reg_tuner_data_319_312 0xF027
+#define reg_tuner_data_319_312_pos 0
+#define reg_tuner_data_319_312_len 8
+#define reg_tuner_data_319_312_lsb 312
+#define xd_p_reg_tuner_data_327_320 (*(volatile byte xdata *) 0xF028)
+#define    p_reg_tuner_data_327_320 0xF028
+#define reg_tuner_data_327_320_pos 0
+#define reg_tuner_data_327_320_len 8
+#define reg_tuner_data_327_320_lsb 320
+#define xd_p_reg_tuner_data_335_328 (*(volatile byte xdata *) 0xF029)
+#define    p_reg_tuner_data_335_328 0xF029
+#define reg_tuner_data_335_328_pos 0
+#define reg_tuner_data_335_328_len 8
+#define reg_tuner_data_335_328_lsb 328
+#define xd_p_reg_tuner_data_343_336 (*(volatile byte xdata *) 0xF02A)
+#define    p_reg_tuner_data_343_336 0xF02A
+#define reg_tuner_data_343_336_pos 0
+#define reg_tuner_data_343_336_len 8
+#define reg_tuner_data_343_336_lsb 336
+#define xd_p_reg_tuner_data_351_344 (*(volatile byte xdata *) 0xF02B)
+#define    p_reg_tuner_data_351_344 0xF02B
+#define reg_tuner_data_351_344_pos 0
+#define reg_tuner_data_351_344_len 8
+#define reg_tuner_data_351_344_lsb 344
+#define xd_p_reg_tuner_data_359_352 (*(volatile byte xdata *) 0xF02C)
+#define    p_reg_tuner_data_359_352 0xF02C
+#define reg_tuner_data_359_352_pos 0
+#define reg_tuner_data_359_352_len 8
+#define reg_tuner_data_359_352_lsb 352
+#define xd_p_reg_tuner_data_367_360 (*(volatile byte xdata *) 0xF02D)
+#define    p_reg_tuner_data_367_360 0xF02D
+#define reg_tuner_data_367_360_pos 0
+#define reg_tuner_data_367_360_len 8
+#define reg_tuner_data_367_360_lsb 360
+#define xd_p_reg_tuner_data_375_368 (*(volatile byte xdata *) 0xF02E)
+#define    p_reg_tuner_data_375_368 0xF02E
+#define reg_tuner_data_375_368_pos 0
+#define reg_tuner_data_375_368_len 8
+#define reg_tuner_data_375_368_lsb 368
+#define xd_p_reg_tuner_data_383_376 (*(volatile byte xdata *) 0xF02F)
+#define    p_reg_tuner_data_383_376 0xF02F
+#define reg_tuner_data_383_376_pos 0
+#define reg_tuner_data_383_376_len 8
+#define reg_tuner_data_383_376_lsb 376
+#define xd_p_reg_tuner_data_391_384 (*(volatile byte xdata *) 0xF030)
+#define    p_reg_tuner_data_391_384 0xF030
+#define reg_tuner_data_391_384_pos 0
+#define reg_tuner_data_391_384_len 8
+#define reg_tuner_data_391_384_lsb 384
+#define xd_p_reg_tuner_data_399_392 (*(volatile byte xdata *) 0xF031)
+#define    p_reg_tuner_data_399_392 0xF031
+#define reg_tuner_data_399_392_pos 0
+#define reg_tuner_data_399_392_len 8
+#define reg_tuner_data_399_392_lsb 392
+#define xd_p_reg_tuner_data_407_400 (*(volatile byte xdata *) 0xF032)
+#define    p_reg_tuner_data_407_400 0xF032
+#define reg_tuner_data_407_400_pos 0
+#define reg_tuner_data_407_400_len 8
+#define reg_tuner_data_407_400_lsb 400
+#define xd_p_reg_tuner_data_415_408 (*(volatile byte xdata *) 0xF033)
+#define    p_reg_tuner_data_415_408 0xF033
+#define reg_tuner_data_415_408_pos 0
+#define reg_tuner_data_415_408_len 8
+#define reg_tuner_data_415_408_lsb 408
+#define xd_p_reg_tuner_data_423_416 (*(volatile byte xdata *) 0xF034)
+#define    p_reg_tuner_data_423_416 0xF034
+#define reg_tuner_data_423_416_pos 0
+#define reg_tuner_data_423_416_len 8
+#define reg_tuner_data_423_416_lsb 416
+#define xd_p_reg_tuner_data_431_424 (*(volatile byte xdata *) 0xF035)
+#define    p_reg_tuner_data_431_424 0xF035
+#define reg_tuner_data_431_424_pos 0
+#define reg_tuner_data_431_424_len 8
+#define reg_tuner_data_431_424_lsb 424
+#define xd_p_reg_tuner_data_439_432 (*(volatile byte xdata *) 0xF036)
+#define    p_reg_tuner_data_439_432 0xF036
+#define reg_tuner_data_439_432_pos 0
+#define reg_tuner_data_439_432_len 8
+#define reg_tuner_data_439_432_lsb 432
+#define xd_p_reg_tuner_data_447_440 (*(volatile byte xdata *) 0xF037)
+#define    p_reg_tuner_data_447_440 0xF037
+#define reg_tuner_data_447_440_pos 0
+#define reg_tuner_data_447_440_len 8
+#define reg_tuner_data_447_440_lsb 440
+#define xd_p_reg_tuner_data_455_448 (*(volatile byte xdata *) 0xF038)
+#define    p_reg_tuner_data_455_448 0xF038
+#define reg_tuner_data_455_448_pos 0
+#define reg_tuner_data_455_448_len 8
+#define reg_tuner_data_455_448_lsb 448
+#define xd_p_reg_tuner_data_463_456 (*(volatile byte xdata *) 0xF039)
+#define    p_reg_tuner_data_463_456 0xF039
+#define reg_tuner_data_463_456_pos 0
+#define reg_tuner_data_463_456_len 8
+#define reg_tuner_data_463_456_lsb 456
+#define xd_p_reg_tuner_data_471_464 (*(volatile byte xdata *) 0xF03A)
+#define    p_reg_tuner_data_471_464 0xF03A
+#define reg_tuner_data_471_464_pos 0
+#define reg_tuner_data_471_464_len 8
+#define reg_tuner_data_471_464_lsb 464
+#define xd_p_reg_tuner_data_479_472 (*(volatile byte xdata *) 0xF03B)
+#define    p_reg_tuner_data_479_472 0xF03B
+#define reg_tuner_data_479_472_pos 0
+#define reg_tuner_data_479_472_len 8
+#define reg_tuner_data_479_472_lsb 472
+#define xd_p_reg_tuner_data_487_480 (*(volatile byte xdata *) 0xF03C)
+#define    p_reg_tuner_data_487_480 0xF03C
+#define reg_tuner_data_487_480_pos 0
+#define reg_tuner_data_487_480_len 8
+#define reg_tuner_data_487_480_lsb 480
+#define xd_p_reg_tuner_data_495_488 (*(volatile byte xdata *) 0xF03D)
+#define    p_reg_tuner_data_495_488 0xF03D
+#define reg_tuner_data_495_488_pos 0
+#define reg_tuner_data_495_488_len 8
+#define reg_tuner_data_495_488_lsb 488
+#define xd_p_reg_tuner_data_503_496 (*(volatile byte xdata *) 0xF03E)
+#define    p_reg_tuner_data_503_496 0xF03E
+#define reg_tuner_data_503_496_pos 0
+#define reg_tuner_data_503_496_len 8
+#define reg_tuner_data_503_496_lsb 496
+#define xd_p_reg_tuner_data_511_504 (*(volatile byte xdata *) 0xF03F)
+#define    p_reg_tuner_data_511_504 0xF03F
+#define reg_tuner_data_511_504_pos 0
+#define reg_tuner_data_511_504_len 8
+#define reg_tuner_data_511_504_lsb 504
+#define xd_p_reg_tuner_data_519_512 (*(volatile byte xdata *) 0xF040)
+#define    p_reg_tuner_data_519_512 0xF040
+#define reg_tuner_data_519_512_pos 0
+#define reg_tuner_data_519_512_len 8
+#define reg_tuner_data_519_512_lsb 512
+#define xd_p_reg_tuner_data_527_520 (*(volatile byte xdata *) 0xF041)
+#define    p_reg_tuner_data_527_520 0xF041
+#define reg_tuner_data_527_520_pos 0
+#define reg_tuner_data_527_520_len 8
+#define reg_tuner_data_527_520_lsb 520
+#define xd_p_reg_tuner_data_535_528 (*(volatile byte xdata *) 0xF042)
+#define    p_reg_tuner_data_535_528 0xF042
+#define reg_tuner_data_535_528_pos 0
+#define reg_tuner_data_535_528_len 8
+#define reg_tuner_data_535_528_lsb 528
+#define xd_p_reg_tuner_data_543_536 (*(volatile byte xdata *) 0xF043)
+#define    p_reg_tuner_data_543_536 0xF043
+#define reg_tuner_data_543_536_pos 0
+#define reg_tuner_data_543_536_len 8
+#define reg_tuner_data_543_536_lsb 536
+#define xd_p_reg_tuner_data_551_544 (*(volatile byte xdata *) 0xF044)
+#define    p_reg_tuner_data_551_544 0xF044
+#define reg_tuner_data_551_544_pos 0
+#define reg_tuner_data_551_544_len 8
+#define reg_tuner_data_551_544_lsb 544
+#define xd_p_reg_tuner_data_559_552 (*(volatile byte xdata *) 0xF045)
+#define    p_reg_tuner_data_559_552 0xF045
+#define reg_tuner_data_559_552_pos 0
+#define reg_tuner_data_559_552_len 8
+#define reg_tuner_data_559_552_lsb 552
+#define xd_p_reg_tuner_data_567_560 (*(volatile byte xdata *) 0xF046)
+#define    p_reg_tuner_data_567_560 0xF046
+#define reg_tuner_data_567_560_pos 0
+#define reg_tuner_data_567_560_len 8
+#define reg_tuner_data_567_560_lsb 560
+#define xd_p_reg_tuner_data_575_568 (*(volatile byte xdata *) 0xF047)
+#define    p_reg_tuner_data_575_568 0xF047
+#define reg_tuner_data_575_568_pos 0
+#define reg_tuner_data_575_568_len 8
+#define reg_tuner_data_575_568_lsb 568
+#define xd_p_reg_tuner_data_583_576 (*(volatile byte xdata *) 0xF048)
+#define    p_reg_tuner_data_583_576 0xF048
+#define reg_tuner_data_583_576_pos 0
+#define reg_tuner_data_583_576_len 8
+#define reg_tuner_data_583_576_lsb 576
+#define xd_p_reg_tuner_data_591_584 (*(volatile byte xdata *) 0xF049)
+#define    p_reg_tuner_data_591_584 0xF049
+#define reg_tuner_data_591_584_pos 0
+#define reg_tuner_data_591_584_len 8
+#define reg_tuner_data_591_584_lsb 584
+#define xd_p_reg_tuner_data_599_592 (*(volatile byte xdata *) 0xF04A)
+#define    p_reg_tuner_data_599_592 0xF04A
+#define reg_tuner_data_599_592_pos 0
+#define reg_tuner_data_599_592_len 8
+#define reg_tuner_data_599_592_lsb 592
+#define xd_p_reg_tuner_data_607_600 (*(volatile byte xdata *) 0xF04B)
+#define    p_reg_tuner_data_607_600 0xF04B
+#define reg_tuner_data_607_600_pos 0
+#define reg_tuner_data_607_600_len 8
+#define reg_tuner_data_607_600_lsb 600
+#define xd_p_reg_tuner_data_615_608 (*(volatile byte xdata *) 0xF04C)
+#define    p_reg_tuner_data_615_608 0xF04C
+#define reg_tuner_data_615_608_pos 0
+#define reg_tuner_data_615_608_len 8
+#define reg_tuner_data_615_608_lsb 608
+#define xd_p_reg_tuner_data_623_616 (*(volatile byte xdata *) 0xF04D)
+#define    p_reg_tuner_data_623_616 0xF04D
+#define reg_tuner_data_623_616_pos 0
+#define reg_tuner_data_623_616_len 8
+#define reg_tuner_data_623_616_lsb 616
+#define xd_p_reg_tuner_data_631_624 (*(volatile byte xdata *) 0xF04E)
+#define    p_reg_tuner_data_631_624 0xF04E
+#define reg_tuner_data_631_624_pos 0
+#define reg_tuner_data_631_624_len 8
+#define reg_tuner_data_631_624_lsb 624
+#define xd_p_reg_tuner_data_639_632 (*(volatile byte xdata *) 0xF04F)
+#define    p_reg_tuner_data_639_632 0xF04F
+#define reg_tuner_data_639_632_pos 0
+#define reg_tuner_data_639_632_len 8
+#define reg_tuner_data_639_632_lsb 632
+#define xd_p_reg_tuner_data_647_640 (*(volatile byte xdata *) 0xF050)
+#define    p_reg_tuner_data_647_640 0xF050
+#define reg_tuner_data_647_640_pos 0
+#define reg_tuner_data_647_640_len 8
+#define reg_tuner_data_647_640_lsb 640
+#define xd_p_reg_tuner_data_655_648 (*(volatile byte xdata *) 0xF051)
+#define    p_reg_tuner_data_655_648 0xF051
+#define reg_tuner_data_655_648_pos 0
+#define reg_tuner_data_655_648_len 8
+#define reg_tuner_data_655_648_lsb 648
+#define xd_p_reg_tuner_data_663_656 (*(volatile byte xdata *) 0xF052)
+#define    p_reg_tuner_data_663_656 0xF052
+#define reg_tuner_data_663_656_pos 0
+#define reg_tuner_data_663_656_len 8
+#define reg_tuner_data_663_656_lsb 656
+#define xd_p_reg_tuner_data_671_664 (*(volatile byte xdata *) 0xF053)
+#define    p_reg_tuner_data_671_664 0xF053
+#define reg_tuner_data_671_664_pos 0
+#define reg_tuner_data_671_664_len 8
+#define reg_tuner_data_671_664_lsb 664
+#define xd_p_reg_tuner_data_679_672 (*(volatile byte xdata *) 0xF054)
+#define    p_reg_tuner_data_679_672 0xF054
+#define reg_tuner_data_679_672_pos 0
+#define reg_tuner_data_679_672_len 8
+#define reg_tuner_data_679_672_lsb 672
+#define xd_p_reg_tuner_data_687_680 (*(volatile byte xdata *) 0xF055)
+#define    p_reg_tuner_data_687_680 0xF055
+#define reg_tuner_data_687_680_pos 0
+#define reg_tuner_data_687_680_len 8
+#define reg_tuner_data_687_680_lsb 680
+#define xd_p_reg_tuner_data_695_688 (*(volatile byte xdata *) 0xF056)
+#define    p_reg_tuner_data_695_688 0xF056
+#define reg_tuner_data_695_688_pos 0
+#define reg_tuner_data_695_688_len 8
+#define reg_tuner_data_695_688_lsb 688
+#define xd_p_reg_tuner_data_703_696 (*(volatile byte xdata *) 0xF057)
+#define    p_reg_tuner_data_703_696 0xF057
+#define reg_tuner_data_703_696_pos 0
+#define reg_tuner_data_703_696_len 8
+#define reg_tuner_data_703_696_lsb 696
+#define xd_p_reg_tuner_data_711_704 (*(volatile byte xdata *) 0xF058)
+#define    p_reg_tuner_data_711_704 0xF058
+#define reg_tuner_data_711_704_pos 0
+#define reg_tuner_data_711_704_len 8
+#define reg_tuner_data_711_704_lsb 704
+#define xd_p_reg_tuner_data_719_712 (*(volatile byte xdata *) 0xF059)
+#define    p_reg_tuner_data_719_712 0xF059
+#define reg_tuner_data_719_712_pos 0
+#define reg_tuner_data_719_712_len 8
+#define reg_tuner_data_719_712_lsb 712
+#define xd_p_reg_tuner_data_727_720 (*(volatile byte xdata *) 0xF05A)
+#define    p_reg_tuner_data_727_720 0xF05A
+#define reg_tuner_data_727_720_pos 0
+#define reg_tuner_data_727_720_len 8
+#define reg_tuner_data_727_720_lsb 720
+#define xd_p_reg_tuner_data_735_728 (*(volatile byte xdata *) 0xF05B)
+#define    p_reg_tuner_data_735_728 0xF05B
+#define reg_tuner_data_735_728_pos 0
+#define reg_tuner_data_735_728_len 8
+#define reg_tuner_data_735_728_lsb 728
+#define xd_p_reg_tuner_data_743_736 (*(volatile byte xdata *) 0xF05C)
+#define    p_reg_tuner_data_743_736 0xF05C
+#define reg_tuner_data_743_736_pos 0
+#define reg_tuner_data_743_736_len 8
+#define reg_tuner_data_743_736_lsb 736
+#define xd_p_reg_tuner_data_751_744 (*(volatile byte xdata *) 0xF05D)
+#define    p_reg_tuner_data_751_744 0xF05D
+#define reg_tuner_data_751_744_pos 0
+#define reg_tuner_data_751_744_len 8
+#define reg_tuner_data_751_744_lsb 744
+#define xd_p_reg_tuner_data_759_752 (*(volatile byte xdata *) 0xF05E)
+#define    p_reg_tuner_data_759_752 0xF05E
+#define reg_tuner_data_759_752_pos 0
+#define reg_tuner_data_759_752_len 8
+#define reg_tuner_data_759_752_lsb 752
+#define xd_p_reg_tuner_data_767_760 (*(volatile byte xdata *) 0xF05F)
+#define    p_reg_tuner_data_767_760 0xF05F
+#define reg_tuner_data_767_760_pos 0
+#define reg_tuner_data_767_760_len 8
+#define reg_tuner_data_767_760_lsb 760
+#define xd_p_reg_tuner_data_775_768 (*(volatile byte xdata *) 0xF060)
+#define    p_reg_tuner_data_775_768 0xF060
+#define reg_tuner_data_775_768_pos 0
+#define reg_tuner_data_775_768_len 8
+#define reg_tuner_data_775_768_lsb 768
+#define xd_p_reg_tuner_data_783_776 (*(volatile byte xdata *) 0xF061)
+#define    p_reg_tuner_data_783_776 0xF061
+#define reg_tuner_data_783_776_pos 0
+#define reg_tuner_data_783_776_len 8
+#define reg_tuner_data_783_776_lsb 776
+#define xd_p_reg_tuner_data_791_784 (*(volatile byte xdata *) 0xF062)
+#define    p_reg_tuner_data_791_784 0xF062
+#define reg_tuner_data_791_784_pos 0
+#define reg_tuner_data_791_784_len 8
+#define reg_tuner_data_791_784_lsb 784
+#define xd_p_reg_tuner_data_799_792 (*(volatile byte xdata *) 0xF063)
+#define    p_reg_tuner_data_799_792 0xF063
+#define reg_tuner_data_799_792_pos 0
+#define reg_tuner_data_799_792_len 8
+#define reg_tuner_data_799_792_lsb 792
+#define xd_p_reg_tuner_data_807_800 (*(volatile byte xdata *) 0xF064)
+#define    p_reg_tuner_data_807_800 0xF064
+#define reg_tuner_data_807_800_pos 0
+#define reg_tuner_data_807_800_len 8
+#define reg_tuner_data_807_800_lsb 800
+#define xd_p_reg_tuner_data_815_808 (*(volatile byte xdata *) 0xF065)
+#define    p_reg_tuner_data_815_808 0xF065
+#define reg_tuner_data_815_808_pos 0
+#define reg_tuner_data_815_808_len 8
+#define reg_tuner_data_815_808_lsb 808
+#define xd_p_reg_tuner_data_823_816 (*(volatile byte xdata *) 0xF066)
+#define    p_reg_tuner_data_823_816 0xF066
+#define reg_tuner_data_823_816_pos 0
+#define reg_tuner_data_823_816_len 8
+#define reg_tuner_data_823_816_lsb 816
+#define xd_p_reg_tuner_data_831_824 (*(volatile byte xdata *) 0xF067)
+#define    p_reg_tuner_data_831_824 0xF067
+#define reg_tuner_data_831_824_pos 0
+#define reg_tuner_data_831_824_len 8
+#define reg_tuner_data_831_824_lsb 824
+#define xd_p_reg_tuner_data_839_832 (*(volatile byte xdata *) 0xF068)
+#define    p_reg_tuner_data_839_832 0xF068
+#define reg_tuner_data_839_832_pos 0
+#define reg_tuner_data_839_832_len 8
+#define reg_tuner_data_839_832_lsb 832
+#define xd_p_reg_tuner_data_847_840 (*(volatile byte xdata *) 0xF069)
+#define    p_reg_tuner_data_847_840 0xF069
+#define reg_tuner_data_847_840_pos 0
+#define reg_tuner_data_847_840_len 8
+#define reg_tuner_data_847_840_lsb 840
+#define xd_p_reg_tuner_data_855_848 (*(volatile byte xdata *) 0xF06A)
+#define    p_reg_tuner_data_855_848 0xF06A
+#define reg_tuner_data_855_848_pos 0
+#define reg_tuner_data_855_848_len 8
+#define reg_tuner_data_855_848_lsb 848
+#define xd_p_reg_tuner_data_863_856 (*(volatile byte xdata *) 0xF06B)
+#define    p_reg_tuner_data_863_856 0xF06B
+#define reg_tuner_data_863_856_pos 0
+#define reg_tuner_data_863_856_len 8
+#define reg_tuner_data_863_856_lsb 856
+#define xd_p_reg_tuner_data_871_864 (*(volatile byte xdata *) 0xF06C)
+#define    p_reg_tuner_data_871_864 0xF06C
+#define reg_tuner_data_871_864_pos 0
+#define reg_tuner_data_871_864_len 8
+#define reg_tuner_data_871_864_lsb 864
+#define xd_p_reg_tuner_data_879_872 (*(volatile byte xdata *) 0xF06D)
+#define    p_reg_tuner_data_879_872 0xF06D
+#define reg_tuner_data_879_872_pos 0
+#define reg_tuner_data_879_872_len 8
+#define reg_tuner_data_879_872_lsb 872
+#define xd_p_reg_tuner_data_887_880 (*(volatile byte xdata *) 0xF06E)
+#define    p_reg_tuner_data_887_880 0xF06E
+#define reg_tuner_data_887_880_pos 0
+#define reg_tuner_data_887_880_len 8
+#define reg_tuner_data_887_880_lsb 880
+#define xd_p_reg_tuner_data_895_888 (*(volatile byte xdata *) 0xF06F)
+#define    p_reg_tuner_data_895_888 0xF06F
+#define reg_tuner_data_895_888_pos 0
+#define reg_tuner_data_895_888_len 8
+#define reg_tuner_data_895_888_lsb 888
+#define xd_p_reg_tuner_data_903_896 (*(volatile byte xdata *) 0xF070)
+#define    p_reg_tuner_data_903_896 0xF070
+#define reg_tuner_data_903_896_pos 0
+#define reg_tuner_data_903_896_len 8
+#define reg_tuner_data_903_896_lsb 896
+#define xd_p_reg_tuner_data_911_904 (*(volatile byte xdata *) 0xF071)
+#define    p_reg_tuner_data_911_904 0xF071
+#define reg_tuner_data_911_904_pos 0
+#define reg_tuner_data_911_904_len 8
+#define reg_tuner_data_911_904_lsb 904
+#define xd_p_reg_tuner_data_919_912 (*(volatile byte xdata *) 0xF072)
+#define    p_reg_tuner_data_919_912 0xF072
+#define reg_tuner_data_919_912_pos 0
+#define reg_tuner_data_919_912_len 8
+#define reg_tuner_data_919_912_lsb 912
+#define xd_p_reg_tuner_data_927_920 (*(volatile byte xdata *) 0xF073)
+#define    p_reg_tuner_data_927_920 0xF073
+#define reg_tuner_data_927_920_pos 0
+#define reg_tuner_data_927_920_len 8
+#define reg_tuner_data_927_920_lsb 920
+#define xd_p_reg_tuner_data_935_928 (*(volatile byte xdata *) 0xF074)
+#define    p_reg_tuner_data_935_928 0xF074
+#define reg_tuner_data_935_928_pos 0
+#define reg_tuner_data_935_928_len 8
+#define reg_tuner_data_935_928_lsb 928
+#define xd_p_reg_tuner_data_943_936 (*(volatile byte xdata *) 0xF075)
+#define    p_reg_tuner_data_943_936 0xF075
+#define reg_tuner_data_943_936_pos 0
+#define reg_tuner_data_943_936_len 8
+#define reg_tuner_data_943_936_lsb 936
+#define xd_p_reg_tuner_data_951_944 (*(volatile byte xdata *) 0xF076)
+#define    p_reg_tuner_data_951_944 0xF076
+#define reg_tuner_data_951_944_pos 0
+#define reg_tuner_data_951_944_len 8
+#define reg_tuner_data_951_944_lsb 944
+#define xd_p_reg_tuner_data_959_952 (*(volatile byte xdata *) 0xF077)
+#define    p_reg_tuner_data_959_952 0xF077
+#define reg_tuner_data_959_952_pos 0
+#define reg_tuner_data_959_952_len 8
+#define reg_tuner_data_959_952_lsb 952
+#define xd_p_reg_tuner_data_967_960 (*(volatile byte xdata *) 0xF078)
+#define    p_reg_tuner_data_967_960 0xF078
+#define reg_tuner_data_967_960_pos 0
+#define reg_tuner_data_967_960_len 8
+#define reg_tuner_data_967_960_lsb 960
+#define xd_p_reg_tuner_data_975_968 (*(volatile byte xdata *) 0xF079)
+#define    p_reg_tuner_data_975_968 0xF079
+#define reg_tuner_data_975_968_pos 0
+#define reg_tuner_data_975_968_len 8
+#define reg_tuner_data_975_968_lsb 968
+#define xd_p_reg_tuner_data_983_976 (*(volatile byte xdata *) 0xF07A)
+#define    p_reg_tuner_data_983_976 0xF07A
+#define reg_tuner_data_983_976_pos 0
+#define reg_tuner_data_983_976_len 8
+#define reg_tuner_data_983_976_lsb 976
+#define xd_p_reg_tuner_data_991_984 (*(volatile byte xdata *) 0xF07B)
+#define    p_reg_tuner_data_991_984 0xF07B
+#define reg_tuner_data_991_984_pos 0
+#define reg_tuner_data_991_984_len 8
+#define reg_tuner_data_991_984_lsb 984
+#define xd_p_reg_tuner_data_999_992 (*(volatile byte xdata *) 0xF07C)
+#define    p_reg_tuner_data_999_992 0xF07C
+#define reg_tuner_data_999_992_pos 0
+#define reg_tuner_data_999_992_len 8
+#define reg_tuner_data_999_992_lsb 992
+#define xd_p_reg_tuner_data_1007_1000   (*(volatile byte xdata *) 0xF07D)
+#define    p_reg_tuner_data_1007_1000   0xF07D
+#define reg_tuner_data_1007_1000_pos 0
+#define reg_tuner_data_1007_1000_len 8
+#define reg_tuner_data_1007_1000_lsb 1000
+#define xd_p_reg_tuner_data_1015_1008   (*(volatile byte xdata *) 0xF07E)
+#define    p_reg_tuner_data_1015_1008   0xF07E
+#define reg_tuner_data_1015_1008_pos 0
+#define reg_tuner_data_1015_1008_len 8
+#define reg_tuner_data_1015_1008_lsb 1008
+#define xd_p_reg_tuner_data_1023_1016   (*(volatile byte xdata *) 0xF07F)
+#define    p_reg_tuner_data_1023_1016   0xF07F
+#define reg_tuner_data_1023_1016_pos 0
+#define reg_tuner_data_1023_1016_len 8
+#define reg_tuner_data_1023_1016_lsb 1016
+#define xd_p_reg_tuner_data_1031_1024   (*(volatile byte xdata *) 0xF080)
+#define    p_reg_tuner_data_1031_1024   0xF080
+#define reg_tuner_data_1031_1024_pos 0
+#define reg_tuner_data_1031_1024_len 8
+#define reg_tuner_data_1031_1024_lsb 1024
+#define xd_p_reg_tuner_data_1039_1032   (*(volatile byte xdata *) 0xF081)
+#define    p_reg_tuner_data_1039_1032   0xF081
+#define reg_tuner_data_1039_1032_pos 0
+#define reg_tuner_data_1039_1032_len 8
+#define reg_tuner_data_1039_1032_lsb 1032
+#define xd_p_reg_tuner_data_1047_1040   (*(volatile byte xdata *) 0xF082)
+#define    p_reg_tuner_data_1047_1040   0xF082
+#define reg_tuner_data_1047_1040_pos 0
+#define reg_tuner_data_1047_1040_len 8
+#define reg_tuner_data_1047_1040_lsb 1040
+#define xd_p_reg_tuner_data_1055_1048   (*(volatile byte xdata *) 0xF083)
+#define    p_reg_tuner_data_1055_1048   0xF083
+#define reg_tuner_data_1055_1048_pos 0
+#define reg_tuner_data_1055_1048_len 8
+#define reg_tuner_data_1055_1048_lsb 1048
+#define xd_p_reg_tuner_data_1063_1056   (*(volatile byte xdata *) 0xF084)
+#define    p_reg_tuner_data_1063_1056   0xF084
+#define reg_tuner_data_1063_1056_pos 0
+#define reg_tuner_data_1063_1056_len 8
+#define reg_tuner_data_1063_1056_lsb 1056
+#define xd_p_reg_tuner_data_1071_1064   (*(volatile byte xdata *) 0xF085)
+#define    p_reg_tuner_data_1071_1064   0xF085
+#define reg_tuner_data_1071_1064_pos 0
+#define reg_tuner_data_1071_1064_len 8
+#define reg_tuner_data_1071_1064_lsb 1064
+#define xd_p_reg_tuner_data_1079_1072   (*(volatile byte xdata *) 0xF086)
+#define    p_reg_tuner_data_1079_1072   0xF086
+#define reg_tuner_data_1079_1072_pos 0
+#define reg_tuner_data_1079_1072_len 8
+#define reg_tuner_data_1079_1072_lsb 1072
+#define xd_p_reg_tuner_data_1087_1080   (*(volatile byte xdata *) 0xF087)
+#define    p_reg_tuner_data_1087_1080   0xF087
+#define reg_tuner_data_1087_1080_pos 0
+#define reg_tuner_data_1087_1080_len 8
+#define reg_tuner_data_1087_1080_lsb 1080
+#define xd_p_reg_tuner_data_1095_1088   (*(volatile byte xdata *) 0xF088)
+#define    p_reg_tuner_data_1095_1088   0xF088
+#define reg_tuner_data_1095_1088_pos 0
+#define reg_tuner_data_1095_1088_len 8
+#define reg_tuner_data_1095_1088_lsb 1088
+#define xd_p_reg_tuner_data_1103_1096   (*(volatile byte xdata *) 0xF089)
+#define    p_reg_tuner_data_1103_1096   0xF089
+#define reg_tuner_data_1103_1096_pos 0
+#define reg_tuner_data_1103_1096_len 8
+#define reg_tuner_data_1103_1096_lsb 1096
+#define xd_p_reg_tuner_data_1111_1104   (*(volatile byte xdata *) 0xF08A)
+#define    p_reg_tuner_data_1111_1104   0xF08A
+#define reg_tuner_data_1111_1104_pos 0
+#define reg_tuner_data_1111_1104_len 8
+#define reg_tuner_data_1111_1104_lsb 1104
+#define xd_p_reg_tuner_data_1119_1112   (*(volatile byte xdata *) 0xF08B)
+#define    p_reg_tuner_data_1119_1112   0xF08B
+#define reg_tuner_data_1119_1112_pos 0
+#define reg_tuner_data_1119_1112_len 8
+#define reg_tuner_data_1119_1112_lsb 1112
+#define xd_p_reg_tuner_data_1127_1120   (*(volatile byte xdata *) 0xF08C)
+#define    p_reg_tuner_data_1127_1120   0xF08C
+#define reg_tuner_data_1127_1120_pos 0
+#define reg_tuner_data_1127_1120_len 8
+#define reg_tuner_data_1127_1120_lsb 1120
+#define xd_p_reg_tuner_data_1135_1128   (*(volatile byte xdata *) 0xF08D)
+#define    p_reg_tuner_data_1135_1128   0xF08D
+#define reg_tuner_data_1135_1128_pos 0
+#define reg_tuner_data_1135_1128_len 8
+#define reg_tuner_data_1135_1128_lsb 1128
+#define xd_p_reg_tuner_data_1143_1136   (*(volatile byte xdata *) 0xF08E)
+#define    p_reg_tuner_data_1143_1136   0xF08E
+#define reg_tuner_data_1143_1136_pos 0
+#define reg_tuner_data_1143_1136_len 8
+#define reg_tuner_data_1143_1136_lsb 1136
+#define xd_p_reg_tuner_data_1151_1144   (*(volatile byte xdata *) 0xF08F)
+#define    p_reg_tuner_data_1151_1144   0xF08F
+#define reg_tuner_data_1151_1144_pos 0
+#define reg_tuner_data_1151_1144_len 8
+#define reg_tuner_data_1151_1144_lsb 1144
+#define xd_p_reg_tuner_data_1159_1152   (*(volatile byte xdata *) 0xF090)
+#define    p_reg_tuner_data_1159_1152   0xF090
+#define reg_tuner_data_1159_1152_pos 0
+#define reg_tuner_data_1159_1152_len 8
+#define reg_tuner_data_1159_1152_lsb 1152
+#define xd_p_reg_tuner_data_1167_1160   (*(volatile byte xdata *) 0xF091)
+#define    p_reg_tuner_data_1167_1160   0xF091
+#define reg_tuner_data_1167_1160_pos 0
+#define reg_tuner_data_1167_1160_len 8
+#define reg_tuner_data_1167_1160_lsb 1160
+#define xd_p_reg_tuner_data_1175_1168   (*(volatile byte xdata *) 0xF092)
+#define    p_reg_tuner_data_1175_1168   0xF092
+#define reg_tuner_data_1175_1168_pos 0
+#define reg_tuner_data_1175_1168_len 8
+#define reg_tuner_data_1175_1168_lsb 1168
+#define xd_p_reg_tuner_data_1183_1176   (*(volatile byte xdata *) 0xF093)
+#define    p_reg_tuner_data_1183_1176   0xF093
+#define reg_tuner_data_1183_1176_pos 0
+#define reg_tuner_data_1183_1176_len 8
+#define reg_tuner_data_1183_1176_lsb 1176
+#define xd_p_reg_tuner_data_1191_1184   (*(volatile byte xdata *) 0xF094)
+#define    p_reg_tuner_data_1191_1184   0xF094
+#define reg_tuner_data_1191_1184_pos 0
+#define reg_tuner_data_1191_1184_len 8
+#define reg_tuner_data_1191_1184_lsb 1184
+#define xd_p_reg_tuner_data_1199_1192   (*(volatile byte xdata *) 0xF095)
+#define    p_reg_tuner_data_1199_1192   0xF095
+#define reg_tuner_data_1199_1192_pos 0
+#define reg_tuner_data_1199_1192_len 8
+#define reg_tuner_data_1199_1192_lsb 1192
+#define xd_p_reg_tuner_data_1207_1200   (*(volatile byte xdata *) 0xF096)
+#define    p_reg_tuner_data_1207_1200   0xF096
+#define reg_tuner_data_1207_1200_pos 0
+#define reg_tuner_data_1207_1200_len 8
+#define reg_tuner_data_1207_1200_lsb 1200
+#define xd_p_reg_tuner_data_1215_1208   (*(volatile byte xdata *) 0xF097)
+#define    p_reg_tuner_data_1215_1208   0xF097
+#define reg_tuner_data_1215_1208_pos 0
+#define reg_tuner_data_1215_1208_len 8
+#define reg_tuner_data_1215_1208_lsb 1208
+#define xd_p_reg_tuner_data_1223_1216   (*(volatile byte xdata *) 0xF098)
+#define    p_reg_tuner_data_1223_1216   0xF098
+#define reg_tuner_data_1223_1216_pos 0
+#define reg_tuner_data_1223_1216_len 8
+#define reg_tuner_data_1223_1216_lsb 1216
+#define xd_p_reg_tuner_data_1231_1224   (*(volatile byte xdata *) 0xF099)
+#define    p_reg_tuner_data_1231_1224   0xF099
+#define reg_tuner_data_1231_1224_pos 0
+#define reg_tuner_data_1231_1224_len 8
+#define reg_tuner_data_1231_1224_lsb 1224
+#define xd_p_reg_tuner_data_1239_1232   (*(volatile byte xdata *) 0xF09A)
+#define    p_reg_tuner_data_1239_1232   0xF09A
+#define reg_tuner_data_1239_1232_pos 0
+#define reg_tuner_data_1239_1232_len 8
+#define reg_tuner_data_1239_1232_lsb 1232
+#define xd_p_reg_tuner_data_1247_1240   (*(volatile byte xdata *) 0xF09B)
+#define    p_reg_tuner_data_1247_1240   0xF09B
+#define reg_tuner_data_1247_1240_pos 0
+#define reg_tuner_data_1247_1240_len 8
+#define reg_tuner_data_1247_1240_lsb 1240
+#define xd_p_reg_tuner_data_1255_1248   (*(volatile byte xdata *) 0xF09C)
+#define    p_reg_tuner_data_1255_1248   0xF09C
+#define reg_tuner_data_1255_1248_pos 0
+#define reg_tuner_data_1255_1248_len 8
+#define reg_tuner_data_1255_1248_lsb 1248
+#define xd_p_reg_tuner_data_1263_1256   (*(volatile byte xdata *) 0xF09D)
+#define    p_reg_tuner_data_1263_1256   0xF09D
+#define reg_tuner_data_1263_1256_pos 0
+#define reg_tuner_data_1263_1256_len 8
+#define reg_tuner_data_1263_1256_lsb 1256
+#define xd_p_reg_tuner_data_1271_1264   (*(volatile byte xdata *) 0xF09E)
+#define    p_reg_tuner_data_1271_1264   0xF09E
+#define reg_tuner_data_1271_1264_pos 0
+#define reg_tuner_data_1271_1264_len 8
+#define reg_tuner_data_1271_1264_lsb 1264
+#define xd_p_reg_tuner_data_1279_1272   (*(volatile byte xdata *) 0xF09F)
+#define    p_reg_tuner_data_1279_1272   0xF09F
+#define reg_tuner_data_1279_1272_pos 0
+#define reg_tuner_data_1279_1272_len 8
+#define reg_tuner_data_1279_1272_lsb 1272
+#define xd_p_reg_tuner_data_1287_1280   (*(volatile byte xdata *) 0xF0A0)
+#define    p_reg_tuner_data_1287_1280   0xF0A0
+#define reg_tuner_data_1287_1280_pos 0
+#define reg_tuner_data_1287_1280_len 8
+#define reg_tuner_data_1287_1280_lsb 1280
+#define xd_p_reg_tuner_data_1295_1288   (*(volatile byte xdata *) 0xF0A1)
+#define    p_reg_tuner_data_1295_1288   0xF0A1
+#define reg_tuner_data_1295_1288_pos 0
+#define reg_tuner_data_1295_1288_len 8
+#define reg_tuner_data_1295_1288_lsb 1288
+#define xd_p_reg_tuner_data_1303_1296   (*(volatile byte xdata *) 0xF0A2)
+#define    p_reg_tuner_data_1303_1296   0xF0A2
+#define reg_tuner_data_1303_1296_pos 0
+#define reg_tuner_data_1303_1296_len 8
+#define reg_tuner_data_1303_1296_lsb 1296
+#define xd_p_reg_tuner_data_1311_1304   (*(volatile byte xdata *) 0xF0A3)
+#define    p_reg_tuner_data_1311_1304   0xF0A3
+#define reg_tuner_data_1311_1304_pos 0
+#define reg_tuner_data_1311_1304_len 8
+#define reg_tuner_data_1311_1304_lsb 1304
+#define xd_p_reg_tuner_data_1319_1312   (*(volatile byte xdata *) 0xF0A4)
+#define    p_reg_tuner_data_1319_1312   0xF0A4
+#define reg_tuner_data_1319_1312_pos 0
+#define reg_tuner_data_1319_1312_len 8
+#define reg_tuner_data_1319_1312_lsb 1312
+#define xd_p_reg_tuner_data_1327_1320   (*(volatile byte xdata *) 0xF0A5)
+#define    p_reg_tuner_data_1327_1320   0xF0A5
+#define reg_tuner_data_1327_1320_pos 0
+#define reg_tuner_data_1327_1320_len 8
+#define reg_tuner_data_1327_1320_lsb 1320
+#define xd_p_reg_tuner_data_1335_1328   (*(volatile byte xdata *) 0xF0A6)
+#define    p_reg_tuner_data_1335_1328   0xF0A6
+#define reg_tuner_data_1335_1328_pos 0
+#define reg_tuner_data_1335_1328_len 8
+#define reg_tuner_data_1335_1328_lsb 1328
+#define xd_p_reg_tuner_data_1343_1336   (*(volatile byte xdata *) 0xF0A7)
+#define    p_reg_tuner_data_1343_1336   0xF0A7
+#define reg_tuner_data_1343_1336_pos 0
+#define reg_tuner_data_1343_1336_len 8
+#define reg_tuner_data_1343_1336_lsb 1336
+#define xd_p_reg_tuner_data_1351_1344   (*(volatile byte xdata *) 0xF0A8)
+#define    p_reg_tuner_data_1351_1344   0xF0A8
+#define reg_tuner_data_1351_1344_pos 0
+#define reg_tuner_data_1351_1344_len 8
+#define reg_tuner_data_1351_1344_lsb 1344
+#define xd_p_reg_tuner_data_1359_1352   (*(volatile byte xdata *) 0xF0A9)
+#define    p_reg_tuner_data_1359_1352   0xF0A9
+#define reg_tuner_data_1359_1352_pos 0
+#define reg_tuner_data_1359_1352_len 8
+#define reg_tuner_data_1359_1352_lsb 1352
+#define xd_p_reg_tuner_data_1367_1360   (*(volatile byte xdata *) 0xF0AA)
+#define    p_reg_tuner_data_1367_1360   0xF0AA
+#define reg_tuner_data_1367_1360_pos 0
+#define reg_tuner_data_1367_1360_len 8
+#define reg_tuner_data_1367_1360_lsb 1360
+#define xd_p_reg_tuner_data_1375_1368   (*(volatile byte xdata *) 0xF0AB)
+#define    p_reg_tuner_data_1375_1368   0xF0AB
+#define reg_tuner_data_1375_1368_pos 0
+#define reg_tuner_data_1375_1368_len 8
+#define reg_tuner_data_1375_1368_lsb 1368
+#define xd_p_reg_tuner_data_1383_1376   (*(volatile byte xdata *) 0xF0AC)
+#define    p_reg_tuner_data_1383_1376   0xF0AC
+#define reg_tuner_data_1383_1376_pos 0
+#define reg_tuner_data_1383_1376_len 8
+#define reg_tuner_data_1383_1376_lsb 1376
+#define xd_p_reg_tuner_data_1391_1384   (*(volatile byte xdata *) 0xF0AD)
+#define    p_reg_tuner_data_1391_1384   0xF0AD
+#define reg_tuner_data_1391_1384_pos 0
+#define reg_tuner_data_1391_1384_len 8
+#define reg_tuner_data_1391_1384_lsb 1384
+#define xd_p_reg_tuner_data_1399_1392   (*(volatile byte xdata *) 0xF0AE)
+#define    p_reg_tuner_data_1399_1392   0xF0AE
+#define reg_tuner_data_1399_1392_pos 0
+#define reg_tuner_data_1399_1392_len 8
+#define reg_tuner_data_1399_1392_lsb 1392
+#define xd_p_reg_tuner_data_1407_1400   (*(volatile byte xdata *) 0xF0AF)
+#define    p_reg_tuner_data_1407_1400   0xF0AF
+#define reg_tuner_data_1407_1400_pos 0
+#define reg_tuner_data_1407_1400_len 8
+#define reg_tuner_data_1407_1400_lsb 1400
+#define xd_p_reg_tuner_data_1415_1408   (*(volatile byte xdata *) 0xF0B0)
+#define    p_reg_tuner_data_1415_1408   0xF0B0
+#define reg_tuner_data_1415_1408_pos 0
+#define reg_tuner_data_1415_1408_len 8
+#define reg_tuner_data_1415_1408_lsb 1408
+#define xd_p_reg_tuner_data_1423_1416   (*(volatile byte xdata *) 0xF0B1)
+#define    p_reg_tuner_data_1423_1416   0xF0B1
+#define reg_tuner_data_1423_1416_pos 0
+#define reg_tuner_data_1423_1416_len 8
+#define reg_tuner_data_1423_1416_lsb 1416
+#define xd_p_reg_tuner_data_1431_1424   (*(volatile byte xdata *) 0xF0B2)
+#define    p_reg_tuner_data_1431_1424   0xF0B2
+#define reg_tuner_data_1431_1424_pos 0
+#define reg_tuner_data_1431_1424_len 8
+#define reg_tuner_data_1431_1424_lsb 1424
+#define xd_p_reg_tuner_data_1439_1432   (*(volatile byte xdata *) 0xF0B3)
+#define    p_reg_tuner_data_1439_1432   0xF0B3
+#define reg_tuner_data_1439_1432_pos 0
+#define reg_tuner_data_1439_1432_len 8
+#define reg_tuner_data_1439_1432_lsb 1432
+#define xd_p_reg_tuner_data_1447_1440   (*(volatile byte xdata *) 0xF0B4)
+#define    p_reg_tuner_data_1447_1440   0xF0B4
+#define reg_tuner_data_1447_1440_pos 0
+#define reg_tuner_data_1447_1440_len 8
+#define reg_tuner_data_1447_1440_lsb 1440
+#define xd_p_reg_tuner_data_1455_1448   (*(volatile byte xdata *) 0xF0B5)
+#define    p_reg_tuner_data_1455_1448   0xF0B5
+#define reg_tuner_data_1455_1448_pos 0
+#define reg_tuner_data_1455_1448_len 8
+#define reg_tuner_data_1455_1448_lsb 1448
+#define xd_p_reg_tuner_data_1463_1456   (*(volatile byte xdata *) 0xF0B6)
+#define    p_reg_tuner_data_1463_1456   0xF0B6
+#define reg_tuner_data_1463_1456_pos 0
+#define reg_tuner_data_1463_1456_len 8
+#define reg_tuner_data_1463_1456_lsb 1456
+#define xd_p_reg_tuner_data_1471_1464   (*(volatile byte xdata *) 0xF0B7)
+#define    p_reg_tuner_data_1471_1464   0xF0B7
+#define reg_tuner_data_1471_1464_pos 0
+#define reg_tuner_data_1471_1464_len 8
+#define reg_tuner_data_1471_1464_lsb 1464
+#define xd_p_reg_tuner_data_1479_1472   (*(volatile byte xdata *) 0xF0B8)
+#define    p_reg_tuner_data_1479_1472   0xF0B8
+#define reg_tuner_data_1479_1472_pos 0
+#define reg_tuner_data_1479_1472_len 8
+#define reg_tuner_data_1479_1472_lsb 1472
+#define xd_p_reg_tuner_data_1487_1480   (*(volatile byte xdata *) 0xF0B9)
+#define    p_reg_tuner_data_1487_1480   0xF0B9
+#define reg_tuner_data_1487_1480_pos 0
+#define reg_tuner_data_1487_1480_len 8
+#define reg_tuner_data_1487_1480_lsb 1480
+#define xd_p_reg_tuner_data_1495_1488   (*(volatile byte xdata *) 0xF0BA)
+#define    p_reg_tuner_data_1495_1488   0xF0BA
+#define reg_tuner_data_1495_1488_pos 0
+#define reg_tuner_data_1495_1488_len 8
+#define reg_tuner_data_1495_1488_lsb 1488
+#define xd_p_reg_tuner_data_1503_1496   (*(volatile byte xdata *) 0xF0BB)
+#define    p_reg_tuner_data_1503_1496   0xF0BB
+#define reg_tuner_data_1503_1496_pos 0
+#define reg_tuner_data_1503_1496_len 8
+#define reg_tuner_data_1503_1496_lsb 1496
+#define xd_p_reg_tuner_data_1511_1504   (*(volatile byte xdata *) 0xF0BC)
+#define    p_reg_tuner_data_1511_1504   0xF0BC
+#define reg_tuner_data_1511_1504_pos 0
+#define reg_tuner_data_1511_1504_len 8
+#define reg_tuner_data_1511_1504_lsb 1504
+#define xd_p_reg_tuner_data_1519_1512   (*(volatile byte xdata *) 0xF0BD)
+#define    p_reg_tuner_data_1519_1512   0xF0BD
+#define reg_tuner_data_1519_1512_pos 0
+#define reg_tuner_data_1519_1512_len 8
+#define reg_tuner_data_1519_1512_lsb 1512
+#define xd_p_reg_tuner_data_1527_1520   (*(volatile byte xdata *) 0xF0BE)
+#define    p_reg_tuner_data_1527_1520   0xF0BE
+#define reg_tuner_data_1527_1520_pos 0
+#define reg_tuner_data_1527_1520_len 8
+#define reg_tuner_data_1527_1520_lsb 1520
+#define xd_p_reg_tuner_data_1535_1528   (*(volatile byte xdata *) 0xF0BF)
+#define    p_reg_tuner_data_1535_1528   0xF0BF
+#define reg_tuner_data_1535_1528_pos 0
+#define reg_tuner_data_1535_1528_len 8
+#define reg_tuner_data_1535_1528_lsb 1528
+#define xd_p_reg_tuner_data_1543_1536   (*(volatile byte xdata *) 0xF0C0)
+#define    p_reg_tuner_data_1543_1536   0xF0C0
+#define reg_tuner_data_1543_1536_pos 0
+#define reg_tuner_data_1543_1536_len 8
+#define reg_tuner_data_1543_1536_lsb 1536
+#define xd_p_reg_tuner_data_1551_1544   (*(volatile byte xdata *) 0xF0C1)
+#define    p_reg_tuner_data_1551_1544   0xF0C1
+#define reg_tuner_data_1551_1544_pos 0
+#define reg_tuner_data_1551_1544_len 8
+#define reg_tuner_data_1551_1544_lsb 1544
+#define xd_p_reg_tuner_data_1559_1552   (*(volatile byte xdata *) 0xF0C2)
+#define    p_reg_tuner_data_1559_1552   0xF0C2
+#define reg_tuner_data_1559_1552_pos 0
+#define reg_tuner_data_1559_1552_len 8
+#define reg_tuner_data_1559_1552_lsb 1552
+#define xd_p_reg_tuner_data_1567_1560   (*(volatile byte xdata *) 0xF0C3)
+#define    p_reg_tuner_data_1567_1560   0xF0C3
+#define reg_tuner_data_1567_1560_pos 0
+#define reg_tuner_data_1567_1560_len 8
+#define reg_tuner_data_1567_1560_lsb 1560
+#define xd_p_reg_tuner_data_1575_1568   (*(volatile byte xdata *) 0xF0C4)
+#define    p_reg_tuner_data_1575_1568   0xF0C4
+#define reg_tuner_data_1575_1568_pos 0
+#define reg_tuner_data_1575_1568_len 8
+#define reg_tuner_data_1575_1568_lsb 1568
+#define xd_p_reg_tuner_data_1583_1576   (*(volatile byte xdata *) 0xF0C5)
+#define    p_reg_tuner_data_1583_1576   0xF0C5
+#define reg_tuner_data_1583_1576_pos 0
+#define reg_tuner_data_1583_1576_len 8
+#define reg_tuner_data_1583_1576_lsb 1576
+#define xd_p_reg_tuner_data_1591_1584   (*(volatile byte xdata *) 0xF0C6)
+#define    p_reg_tuner_data_1591_1584   0xF0C6
+#define reg_tuner_data_1591_1584_pos 0
+#define reg_tuner_data_1591_1584_len 8
+#define reg_tuner_data_1591_1584_lsb 1584
+#define xd_p_reg_tuner_data_1599_1592   (*(volatile byte xdata *) 0xF0C7)
+#define    p_reg_tuner_data_1599_1592   0xF0C7
+#define reg_tuner_data_1599_1592_pos 0
+#define reg_tuner_data_1599_1592_len 8
+#define reg_tuner_data_1599_1592_lsb 1592
+#define xd_p_reg_tuner_data_1607_1600   (*(volatile byte xdata *) 0xF0C8)
+#define    p_reg_tuner_data_1607_1600   0xF0C8
+#define reg_tuner_data_1607_1600_pos 0
+#define reg_tuner_data_1607_1600_len 8
+#define reg_tuner_data_1607_1600_lsb 1600
+#define xd_p_reg_tuner_data_1615_1608   (*(volatile byte xdata *) 0xF0C9)
+#define    p_reg_tuner_data_1615_1608   0xF0C9
+#define reg_tuner_data_1615_1608_pos 0
+#define reg_tuner_data_1615_1608_len 8
+#define reg_tuner_data_1615_1608_lsb 1608
+#define xd_p_reg_tuner_data_1623_1616   (*(volatile byte xdata *) 0xF0CA)
+#define    p_reg_tuner_data_1623_1616   0xF0CA
+#define reg_tuner_data_1623_1616_pos 0
+#define reg_tuner_data_1623_1616_len 8
+#define reg_tuner_data_1623_1616_lsb 1616
+#define xd_p_reg_tuner_data_1631_1624   (*(volatile byte xdata *) 0xF0CB)
+#define    p_reg_tuner_data_1631_1624   0xF0CB
+#define reg_tuner_data_1631_1624_pos 0
+#define reg_tuner_data_1631_1624_len 8
+#define reg_tuner_data_1631_1624_lsb 1624
+#define xd_p_reg_tuner_data_1639_1632   (*(volatile byte xdata *) 0xF0CC)
+#define    p_reg_tuner_data_1639_1632   0xF0CC
+#define reg_tuner_data_1639_1632_pos 0
+#define reg_tuner_data_1639_1632_len 8
+#define reg_tuner_data_1639_1632_lsb 1632
+#define xd_p_reg_tuner_data_1647_1640   (*(volatile byte xdata *) 0xF0CD)
+#define    p_reg_tuner_data_1647_1640   0xF0CD
+#define reg_tuner_data_1647_1640_pos 0
+#define reg_tuner_data_1647_1640_len 8
+#define reg_tuner_data_1647_1640_lsb 1640
+#define xd_p_reg_tuner_data_1655_1648   (*(volatile byte xdata *) 0xF0CE)
+#define    p_reg_tuner_data_1655_1648   0xF0CE
+#define reg_tuner_data_1655_1648_pos 0
+#define reg_tuner_data_1655_1648_len 8
+#define reg_tuner_data_1655_1648_lsb 1648
+#define xd_p_reg_tuner_data_1663_1656   (*(volatile byte xdata *) 0xF0CF)
+#define    p_reg_tuner_data_1663_1656   0xF0CF
+#define reg_tuner_data_1663_1656_pos 0
+#define reg_tuner_data_1663_1656_len 8
+#define reg_tuner_data_1663_1656_lsb 1656
+#define xd_p_reg_tuner_data_1671_1664   (*(volatile byte xdata *) 0xF0D0)
+#define    p_reg_tuner_data_1671_1664   0xF0D0
+#define reg_tuner_data_1671_1664_pos 0
+#define reg_tuner_data_1671_1664_len 8
+#define reg_tuner_data_1671_1664_lsb 1664
+#define xd_p_reg_tuner_data_1679_1672   (*(volatile byte xdata *) 0xF0D1)
+#define    p_reg_tuner_data_1679_1672   0xF0D1
+#define reg_tuner_data_1679_1672_pos 0
+#define reg_tuner_data_1679_1672_len 8
+#define reg_tuner_data_1679_1672_lsb 1672
+#define xd_p_reg_tuner_data_1687_1680   (*(volatile byte xdata *) 0xF0D2)
+#define    p_reg_tuner_data_1687_1680   0xF0D2
+#define reg_tuner_data_1687_1680_pos 0
+#define reg_tuner_data_1687_1680_len 8
+#define reg_tuner_data_1687_1680_lsb 1680
+#define xd_p_reg_tuner_data_1695_1688   (*(volatile byte xdata *) 0xF0D3)
+#define    p_reg_tuner_data_1695_1688   0xF0D3
+#define reg_tuner_data_1695_1688_pos 0
+#define reg_tuner_data_1695_1688_len 8
+#define reg_tuner_data_1695_1688_lsb 1688
+#define xd_p_reg_tuner_data_1703_1696   (*(volatile byte xdata *) 0xF0D4)
+#define    p_reg_tuner_data_1703_1696   0xF0D4
+#define reg_tuner_data_1703_1696_pos 0
+#define reg_tuner_data_1703_1696_len 8
+#define reg_tuner_data_1703_1696_lsb 1696
+#define xd_p_reg_tuner_data_1711_1704   (*(volatile byte xdata *) 0xF0D5)
+#define    p_reg_tuner_data_1711_1704   0xF0D5
+#define reg_tuner_data_1711_1704_pos 0
+#define reg_tuner_data_1711_1704_len 8
+#define reg_tuner_data_1711_1704_lsb 1704
+#define xd_p_reg_tuner_data_1719_1712   (*(volatile byte xdata *) 0xF0D6)
+#define    p_reg_tuner_data_1719_1712   0xF0D6
+#define reg_tuner_data_1719_1712_pos 0
+#define reg_tuner_data_1719_1712_len 8
+#define reg_tuner_data_1719_1712_lsb 1712
+#define xd_p_reg_tuner_data_1727_1720   (*(volatile byte xdata *) 0xF0D7)
+#define    p_reg_tuner_data_1727_1720   0xF0D7
+#define reg_tuner_data_1727_1720_pos 0
+#define reg_tuner_data_1727_1720_len 8
+#define reg_tuner_data_1727_1720_lsb 1720
+#define xd_p_reg_tuner_data_1735_1728   (*(volatile byte xdata *) 0xF0D8)
+#define    p_reg_tuner_data_1735_1728   0xF0D8
+#define reg_tuner_data_1735_1728_pos 0
+#define reg_tuner_data_1735_1728_len 8
+#define reg_tuner_data_1735_1728_lsb 1728
+#define xd_p_reg_tuner_data_1743_1736   (*(volatile byte xdata *) 0xF0D9)
+#define    p_reg_tuner_data_1743_1736   0xF0D9
+#define reg_tuner_data_1743_1736_pos 0
+#define reg_tuner_data_1743_1736_len 8
+#define reg_tuner_data_1743_1736_lsb 1736
+#define xd_p_reg_tuner_data_1751_1744   (*(volatile byte xdata *) 0xF0DA)
+#define    p_reg_tuner_data_1751_1744   0xF0DA
+#define reg_tuner_data_1751_1744_pos 0
+#define reg_tuner_data_1751_1744_len 8
+#define reg_tuner_data_1751_1744_lsb 1744
+#define xd_p_reg_tuner_data_1759_1752   (*(volatile byte xdata *) 0xF0DB)
+#define    p_reg_tuner_data_1759_1752   0xF0DB
+#define reg_tuner_data_1759_1752_pos 0
+#define reg_tuner_data_1759_1752_len 8
+#define reg_tuner_data_1759_1752_lsb 1752
+#define xd_p_reg_tuner_data_1767_1760   (*(volatile byte xdata *) 0xF0DC)
+#define    p_reg_tuner_data_1767_1760   0xF0DC
+#define reg_tuner_data_1767_1760_pos 0
+#define reg_tuner_data_1767_1760_len 8
+#define reg_tuner_data_1767_1760_lsb 1760
+#define xd_p_reg_tuner_data_1775_1768   (*(volatile byte xdata *) 0xF0DD)
+#define    p_reg_tuner_data_1775_1768   0xF0DD
+#define reg_tuner_data_1775_1768_pos 0
+#define reg_tuner_data_1775_1768_len 8
+#define reg_tuner_data_1775_1768_lsb 1768
+#define xd_p_reg_tuner_data_1783_1776   (*(volatile byte xdata *) 0xF0DE)
+#define    p_reg_tuner_data_1783_1776   0xF0DE
+#define reg_tuner_data_1783_1776_pos 0
+#define reg_tuner_data_1783_1776_len 8
+#define reg_tuner_data_1783_1776_lsb 1776
+#define xd_p_reg_tuner_data_1791_1784   (*(volatile byte xdata *) 0xF0DF)
+#define    p_reg_tuner_data_1791_1784   0xF0DF
+#define reg_tuner_data_1791_1784_pos 0
+#define reg_tuner_data_1791_1784_len 8
+#define reg_tuner_data_1791_1784_lsb 1784
+#define xd_p_reg_tuner_data_1799_1792   (*(volatile byte xdata *) 0xF0E0)
+#define    p_reg_tuner_data_1799_1792   0xF0E0
+#define reg_tuner_data_1799_1792_pos 0
+#define reg_tuner_data_1799_1792_len 8
+#define reg_tuner_data_1799_1792_lsb 1792
+#define xd_p_reg_tuner_data_1807_1800   (*(volatile byte xdata *) 0xF0E1)
+#define    p_reg_tuner_data_1807_1800   0xF0E1
+#define reg_tuner_data_1807_1800_pos 0
+#define reg_tuner_data_1807_1800_len 8
+#define reg_tuner_data_1807_1800_lsb 1800
+#define xd_p_reg_tuner_data_1815_1808   (*(volatile byte xdata *) 0xF0E2)
+#define    p_reg_tuner_data_1815_1808   0xF0E2
+#define reg_tuner_data_1815_1808_pos 0
+#define reg_tuner_data_1815_1808_len 8
+#define reg_tuner_data_1815_1808_lsb 1808
+#define xd_p_reg_tuner_data_1823_1816   (*(volatile byte xdata *) 0xF0E3)
+#define    p_reg_tuner_data_1823_1816   0xF0E3
+#define reg_tuner_data_1823_1816_pos 0
+#define reg_tuner_data_1823_1816_len 8
+#define reg_tuner_data_1823_1816_lsb 1816
+#define xd_p_reg_tuner_data_1831_1824   (*(volatile byte xdata *) 0xF0E4)
+#define    p_reg_tuner_data_1831_1824   0xF0E4
+#define reg_tuner_data_1831_1824_pos 0
+#define reg_tuner_data_1831_1824_len 8
+#define reg_tuner_data_1831_1824_lsb 1824
+#define xd_p_reg_tuner_data_1839_1832   (*(volatile byte xdata *) 0xF0E5)
+#define    p_reg_tuner_data_1839_1832   0xF0E5
+#define reg_tuner_data_1839_1832_pos 0
+#define reg_tuner_data_1839_1832_len 8
+#define reg_tuner_data_1839_1832_lsb 1832
+#define xd_p_reg_tuner_data_1847_1840   (*(volatile byte xdata *) 0xF0E6)
+#define    p_reg_tuner_data_1847_1840   0xF0E6
+#define reg_tuner_data_1847_1840_pos 0
+#define reg_tuner_data_1847_1840_len 8
+#define reg_tuner_data_1847_1840_lsb 1840
+#define xd_p_reg_tuner_data_1855_1848   (*(volatile byte xdata *) 0xF0E7)
+#define    p_reg_tuner_data_1855_1848   0xF0E7
+#define reg_tuner_data_1855_1848_pos 0
+#define reg_tuner_data_1855_1848_len 8
+#define reg_tuner_data_1855_1848_lsb 1848
+#define xd_p_reg_tuner_data_1863_1856   (*(volatile byte xdata *) 0xF0E8)
+#define    p_reg_tuner_data_1863_1856   0xF0E8
+#define reg_tuner_data_1863_1856_pos 0
+#define reg_tuner_data_1863_1856_len 8
+#define reg_tuner_data_1863_1856_lsb 1856
+#define xd_p_reg_tuner_data_1871_1864   (*(volatile byte xdata *) 0xF0E9)
+#define    p_reg_tuner_data_1871_1864   0xF0E9
+#define reg_tuner_data_1871_1864_pos 0
+#define reg_tuner_data_1871_1864_len 8
+#define reg_tuner_data_1871_1864_lsb 1864
+#define xd_p_reg_tuner_data_1879_1872   (*(volatile byte xdata *) 0xF0EA)
+#define    p_reg_tuner_data_1879_1872   0xF0EA
+#define reg_tuner_data_1879_1872_pos 0
+#define reg_tuner_data_1879_1872_len 8
+#define reg_tuner_data_1879_1872_lsb 1872
+#define xd_p_reg_tuner_data_1887_1880   (*(volatile byte xdata *) 0xF0EB)
+#define    p_reg_tuner_data_1887_1880   0xF0EB
+#define reg_tuner_data_1887_1880_pos 0
+#define reg_tuner_data_1887_1880_len 8
+#define reg_tuner_data_1887_1880_lsb 1880
+#define xd_p_reg_tuner_data_1895_1888   (*(volatile byte xdata *) 0xF0EC)
+#define    p_reg_tuner_data_1895_1888   0xF0EC
+#define reg_tuner_data_1895_1888_pos 0
+#define reg_tuner_data_1895_1888_len 8
+#define reg_tuner_data_1895_1888_lsb 1888
+#define xd_p_reg_tuner_data_1903_1896   (*(volatile byte xdata *) 0xF0ED)
+#define    p_reg_tuner_data_1903_1896   0xF0ED
+#define reg_tuner_data_1903_1896_pos 0
+#define reg_tuner_data_1903_1896_len 8
+#define reg_tuner_data_1903_1896_lsb 1896
+#define xd_p_reg_tuner_data_1911_1904   (*(volatile byte xdata *) 0xF0EE)
+#define    p_reg_tuner_data_1911_1904   0xF0EE
+#define reg_tuner_data_1911_1904_pos 0
+#define reg_tuner_data_1911_1904_len 8
+#define reg_tuner_data_1911_1904_lsb 1904
+#define xd_p_reg_tuner_data_1919_1912   (*(volatile byte xdata *) 0xF0EF)
+#define    p_reg_tuner_data_1919_1912   0xF0EF
+#define reg_tuner_data_1919_1912_pos 0
+#define reg_tuner_data_1919_1912_len 8
+#define reg_tuner_data_1919_1912_lsb 1912
+#define xd_p_reg_tuner_data_1927_1920   (*(volatile byte xdata *) 0xF0F0)
+#define    p_reg_tuner_data_1927_1920   0xF0F0
+#define reg_tuner_data_1927_1920_pos 0
+#define reg_tuner_data_1927_1920_len 8
+#define reg_tuner_data_1927_1920_lsb 1920
+#define xd_p_reg_tuner_data_1935_1928   (*(volatile byte xdata *) 0xF0F1)
+#define    p_reg_tuner_data_1935_1928   0xF0F1
+#define reg_tuner_data_1935_1928_pos 0
+#define reg_tuner_data_1935_1928_len 8
+#define reg_tuner_data_1935_1928_lsb 1928
+#define xd_p_reg_tuner_data_1943_1936   (*(volatile byte xdata *) 0xF0F2)
+#define    p_reg_tuner_data_1943_1936   0xF0F2
+#define reg_tuner_data_1943_1936_pos 0
+#define reg_tuner_data_1943_1936_len 8
+#define reg_tuner_data_1943_1936_lsb 1936
+#define xd_p_reg_tuner_data_1951_1944   (*(volatile byte xdata *) 0xF0F3)
+#define    p_reg_tuner_data_1951_1944   0xF0F3
+#define reg_tuner_data_1951_1944_pos 0
+#define reg_tuner_data_1951_1944_len 8
+#define reg_tuner_data_1951_1944_lsb 1944
+#define xd_p_reg_tuner_data_1959_1952   (*(volatile byte xdata *) 0xF0F4)
+#define    p_reg_tuner_data_1959_1952   0xF0F4
+#define reg_tuner_data_1959_1952_pos 0
+#define reg_tuner_data_1959_1952_len 8
+#define reg_tuner_data_1959_1952_lsb 1952
+#define xd_p_reg_tuner_data_1967_1960   (*(volatile byte xdata *) 0xF0F5)
+#define    p_reg_tuner_data_1967_1960   0xF0F5
+#define reg_tuner_data_1967_1960_pos 0
+#define reg_tuner_data_1967_1960_len 8
+#define reg_tuner_data_1967_1960_lsb 1960
+#define xd_p_reg_tuner_data_1975_1968   (*(volatile byte xdata *) 0xF0F6)
+#define    p_reg_tuner_data_1975_1968   0xF0F6
+#define reg_tuner_data_1975_1968_pos 0
+#define reg_tuner_data_1975_1968_len 8
+#define reg_tuner_data_1975_1968_lsb 1968
+#define xd_p_reg_tuner_data_1983_1976   (*(volatile byte xdata *) 0xF0F7)
+#define    p_reg_tuner_data_1983_1976   0xF0F7
+#define reg_tuner_data_1983_1976_pos 0
+#define reg_tuner_data_1983_1976_len 8
+#define reg_tuner_data_1983_1976_lsb 1976
+#define xd_p_reg_tuner_data_1991_1984   (*(volatile byte xdata *) 0xF0F8)
+#define    p_reg_tuner_data_1991_1984   0xF0F8
+#define reg_tuner_data_1991_1984_pos 0
+#define reg_tuner_data_1991_1984_len 8
+#define reg_tuner_data_1991_1984_lsb 1984
+#define xd_p_reg_tuner_data_1999_1992   (*(volatile byte xdata *) 0xF0F9)
+#define    p_reg_tuner_data_1999_1992   0xF0F9
+#define reg_tuner_data_1999_1992_pos 0
+#define reg_tuner_data_1999_1992_len 8
+#define reg_tuner_data_1999_1992_lsb 1992
+#define xd_p_reg_tuner_data_2007_2000   (*(volatile byte xdata *) 0xF0FA)
+#define    p_reg_tuner_data_2007_2000   0xF0FA
+#define reg_tuner_data_2007_2000_pos 0
+#define reg_tuner_data_2007_2000_len 8
+#define reg_tuner_data_2007_2000_lsb 2000
+#define xd_p_reg_tuner_data_2015_2008   (*(volatile byte xdata *) 0xF0FB)
+#define    p_reg_tuner_data_2015_2008   0xF0FB
+#define reg_tuner_data_2015_2008_pos 0
+#define reg_tuner_data_2015_2008_len 8
+#define reg_tuner_data_2015_2008_lsb 2008
+#define xd_p_reg_tuner_data_2023_2016   (*(volatile byte xdata *) 0xF0FC)
+#define    p_reg_tuner_data_2023_2016   0xF0FC
+#define reg_tuner_data_2023_2016_pos 0
+#define reg_tuner_data_2023_2016_len 8
+#define reg_tuner_data_2023_2016_lsb 2016
+#define xd_p_reg_tuner_data_2031_2024   (*(volatile byte xdata *) 0xF0FD)
+#define    p_reg_tuner_data_2031_2024   0xF0FD
+#define reg_tuner_data_2031_2024_pos 0
+#define reg_tuner_data_2031_2024_len 8
+#define reg_tuner_data_2031_2024_lsb 2024
+#define xd_p_reg_tuner_data_2039_2032   (*(volatile byte xdata *) 0xF0FE)
+#define    p_reg_tuner_data_2039_2032   0xF0FE
+#define reg_tuner_data_2039_2032_pos 0
+#define reg_tuner_data_2039_2032_len 8
+#define reg_tuner_data_2039_2032_lsb 2032
+#define xd_p_reg_tuner_data_2047_2040   (*(volatile byte xdata *) 0xF0FF)
+#define    p_reg_tuner_data_2047_2040   0xF0FF
+#define reg_tuner_data_2047_2040_pos 0
+#define reg_tuner_data_2047_2040_len 8
+#define reg_tuner_data_2047_2040_lsb 2040
+#define xd_p_reg_tuner_master_rd_wr (*(volatile byte xdata *) 0xF100)
+#define    p_reg_tuner_master_rd_wr 0xF100
+#define reg_tuner_master_rd_wr_pos 0
+#define reg_tuner_master_rd_wr_len 1
+#define reg_tuner_master_rd_wr_lsb 0
+#define xd_p_reg_tuner_master_length    (*(volatile byte xdata *) 0xF101)
+#define    p_reg_tuner_master_length    0xF101
+#define reg_tuner_master_length_pos 0
+#define reg_tuner_master_length_len 8
+#define reg_tuner_master_length_lsb 0
+#define xd_p_reg_tuner_cmd_exe  (*(volatile byte xdata *) 0xF102)
+#define    p_reg_tuner_cmd_exe  0xF102
+#define reg_tuner_cmd_exe_pos 0
+#define reg_tuner_cmd_exe_len 1
+#define reg_tuner_cmd_exe_lsb 0
+#define xd_p_reg_tuner_wdat_done    (*(volatile byte xdata *) 0xF102)
+#define    p_reg_tuner_wdat_done    0xF102
+#define reg_tuner_wdat_done_pos 1
+#define reg_tuner_wdat_done_len 1
+#define reg_tuner_wdat_done_lsb 0
+#define xd_p_reg_tuner_wdat_fail    (*(volatile byte xdata *) 0xF102)
+#define    p_reg_tuner_wdat_fail    0xF102
+#define reg_tuner_wdat_fail_pos 2
+#define reg_tuner_wdat_fail_len 1
+#define reg_tuner_wdat_fail_lsb 0
+#define xd_p_reg_tuner_ofsm_i2cm_rdat_rdy   (*(volatile byte xdata *) 0xF102)
+#define    p_reg_tuner_ofsm_i2cm_rdat_rdy   0xF102
+#define reg_tuner_ofsm_i2cm_rdat_rdy_pos 3
+#define reg_tuner_ofsm_i2cm_rdat_rdy_len 1
+#define reg_tuner_ofsm_i2cm_rdat_rdy_lsb 0
+#define xd_p_reg_tuner_current_state    (*(volatile byte xdata *) 0xF102)
+#define    p_reg_tuner_current_state    0xF102
+#define reg_tuner_current_state_pos 4
+#define reg_tuner_current_state_len 3
+#define reg_tuner_current_state_lsb 0
+#define xd_p_reg_one_cycle_counter_tuner    (*(volatile byte xdata *) 0xF103)
+#define    p_reg_one_cycle_counter_tuner    0xF103
+#define reg_one_cycle_counter_tuner_pos 0
+#define reg_one_cycle_counter_tuner_len 8
+#define reg_one_cycle_counter_tuner_lsb 0
+#define xd_p_reg_msb_lsb    (*(volatile byte xdata *) 0xF104)
+#define    p_reg_msb_lsb    0xF104
+#define reg_msb_lsb_pos 0
+#define reg_msb_lsb_len 1
+#define reg_msb_lsb_lsb 0
+#define xd_p_reg_ofdm_rst   (*(volatile byte xdata *) 0xF104)
+#define    p_reg_ofdm_rst   0xF104
+#define xd_p_reg_sel_thirdi2c   (*(volatile byte xdata *) 0xF104)
+#define    p_reg_sel_thirdi2c   0xF104
+#define reg_sel_thirdi2c_pos 2
+#define reg_sel_thirdi2c_len 1
+#define reg_sel_thirdi2c_lsb 0
+#define xd_p_reg_sel_tuner  (*(volatile byte xdata *) 0xF104)
+#define    p_reg_sel_tuner  0xF104
+#define xd_p_reg_ofdm_rst_en    (*(volatile byte xdata *) 0xF104)
+#define    p_reg_ofdm_rst_en    0xF104
+#define xd_p_reg_sdio_cccr_v    (*(volatile byte xdata *) 0xF140)
+#define    p_reg_sdio_cccr_v    0xF140
+#define reg_sdio_cccr_v_pos 0
+#define reg_sdio_cccr_v_len 4
+#define reg_sdio_cccr_v_lsb 0
+#define xd_p_reg_sdio_sdio_v    (*(volatile byte xdata *) 0xF140)
+#define    p_reg_sdio_sdio_v    0xF140
+#define reg_sdio_sdio_v_pos 4
+#define reg_sdio_sdio_v_len 4
+#define reg_sdio_sdio_v_lsb 0
+#define xd_p_reg_sdioc_sd_v (*(volatile byte xdata *) 0xF141)
+#define    p_reg_sdioc_sd_v 0xF141
+#define reg_sdioc_sd_v_pos 0
+#define reg_sdioc_sd_v_len 4
+#define reg_sdioc_sd_v_lsb 0
+#define xd_p_reg_sdioc_ior1 (*(volatile byte xdata *) 0xF143)
+#define    p_reg_sdioc_ior1 0xF143
+#define reg_sdioc_ior1_pos 1
+#define reg_sdioc_ior1_len 1
+#define reg_sdioc_ior1_lsb 0
+#define xd_p_reg_sdioc_int1 (*(volatile byte xdata *) 0xF145)
+#define    p_reg_sdioc_int1 0xF145
+#define reg_sdioc_int1_pos 1
+#define reg_sdioc_int1_len 1
+#define reg_sdioc_int1_lsb 0
+#define xd_p_reg_sdioc_scsi (*(volatile byte xdata *) 0xF147)
+#define    p_reg_sdioc_scsi 0xF147
+#define reg_sdioc_scsi_pos 6
+#define reg_sdioc_scsi_len 1
+#define reg_sdioc_scsi_lsb 0
+#define xd_p_reg_sdioc_sdc  (*(volatile byte xdata *) 0xF148)
+#define    p_reg_sdioc_sdc  0xF148
+#define reg_sdioc_sdc_pos 0
+#define reg_sdioc_sdc_len 1
+#define reg_sdioc_sdc_lsb 0
+#define xd_p_reg_sdioc_smb  (*(volatile byte xdata *) 0xF148)
+#define    p_reg_sdioc_smb  0xF148
+#define reg_sdioc_smb_pos 1
+#define reg_sdioc_smb_len 1
+#define reg_sdioc_smb_lsb 0
+#define xd_p_reg_sdioc_srw  (*(volatile byte xdata *) 0xF148)
+#define    p_reg_sdioc_srw  0xF148
+#define reg_sdioc_srw_pos 2
+#define reg_sdioc_srw_len 1
+#define reg_sdioc_srw_lsb 0
+#define xd_p_reg_sdioc_sbs  (*(volatile byte xdata *) 0xF148)
+#define    p_reg_sdioc_sbs  0xF148
+#define reg_sdioc_sbs_pos 3
+#define reg_sdioc_sbs_len 1
+#define reg_sdioc_sbs_lsb 0
+#define xd_p_reg_sdioc_s4mi (*(volatile byte xdata *) 0xF148)
+#define    p_reg_sdioc_s4mi 0xF148
+#define reg_sdioc_s4mi_pos 4
+#define reg_sdioc_s4mi_len 1
+#define reg_sdioc_s4mi_lsb 0
+#define xd_p_reg_sdioc_lsc  (*(volatile byte xdata *) 0xF148)
+#define    p_reg_sdioc_lsc  0xF148
+#define reg_sdioc_lsc_pos 6
+#define reg_sdioc_lsc_len 1
+#define reg_sdioc_lsc_lsb 0
+#define xd_p_reg_sdioc_4bls (*(volatile byte xdata *) 0xF148)
+#define    p_reg_sdioc_4bls 0xF148
+#define reg_sdioc_4bls_pos 7
+#define reg_sdioc_4bls_len 1
+#define reg_sdioc_4bls_lsb 0
+#define xd_p_reg_sdioc_cis_7_0  (*(volatile byte xdata *) 0xF149)
+#define    p_reg_sdioc_cis_7_0  0xF149
+#define reg_sdioc_cis_7_0_pos 0
+#define reg_sdioc_cis_7_0_len 8
+#define reg_sdioc_cis_7_0_lsb 0
+#define xd_p_reg_sdioc_cis_15_8 (*(volatile byte xdata *) 0xF14A)
+#define    p_reg_sdioc_cis_15_8 0xF14A
+#define reg_sdioc_cis_15_8_pos 0
+#define reg_sdioc_cis_15_8_len 8
+#define reg_sdioc_cis_15_8_lsb 8
+#define xd_p_reg_sdioc_cis_23_16    (*(volatile byte xdata *) 0xF14B)
+#define    p_reg_sdioc_cis_23_16    0xF14B
+#define reg_sdioc_cis_23_16_pos 0
+#define reg_sdioc_cis_23_16_len 8
+#define reg_sdioc_cis_23_16_lsb 16
+#define xd_p_reg_sdioc_fs   (*(volatile byte xdata *) 0xF14D)
+#define    p_reg_sdioc_fs   0xF14D
+#define reg_sdioc_fs_pos 0
+#define reg_sdioc_fs_len 4
+#define reg_sdioc_fs_lsb 0
+#define xd_p_reg_sdioc_df   (*(volatile byte xdata *) 0xF14D)
+#define    p_reg_sdioc_df   0xF14D
+#define reg_sdioc_df_pos 7
+#define reg_sdioc_df_len 1
+#define reg_sdioc_df_lsb 0
+#define xd_p_reg_sdioc_ex1  (*(volatile byte xdata *) 0xF14E)
+#define    p_reg_sdioc_ex1  0xF14E
+#define reg_sdioc_ex1_pos 1
+#define reg_sdioc_ex1_len 1
+#define reg_sdioc_ex1_lsb 0
+#define xd_p_reg_sdioc_rf1  (*(volatile byte xdata *) 0xF14F)
+#define    p_reg_sdioc_rf1  0xF14F
+#define reg_sdioc_rf1_pos 1
+#define reg_sdioc_rf1_len 1
+#define reg_sdioc_rf1_lsb 0
+#define xd_p_reg_sdioc_smpc (*(volatile byte xdata *) 0xF152)
+#define    p_reg_sdioc_smpc 0xF152
+#define reg_sdioc_smpc_pos 0
+#define reg_sdioc_smpc_len 1
+#define reg_sdioc_smpc_lsb 0
+#define xd_p_reg_sdioc_f1_code  (*(volatile byte xdata *) 0xF160)
+#define    p_reg_sdioc_f1_code  0xF160
+#define reg_sdioc_f1_code_pos 0
+#define reg_sdioc_f1_code_len 4
+#define reg_sdioc_f1_code_lsb 0
+#define xd_p_reg_sdioc_scsa (*(volatile byte xdata *) 0xF160)
+#define    p_reg_sdioc_scsa 0xF160
+#define reg_sdioc_scsa_pos 6
+#define reg_sdioc_scsa_len 1
+#define reg_sdioc_scsa_lsb 0
+#define xd_p_reg_sdioc_csa_en   (*(volatile byte xdata *) 0xF160)
+#define    p_reg_sdioc_csa_en   0xF160
+#define reg_sdioc_csa_en_pos 7
+#define reg_sdioc_csa_en_len 1
+#define reg_sdioc_csa_en_lsb 0
+#define xd_p_reg_sdioc_f1_ext_code  (*(volatile byte xdata *) 0xF161)
+#define    p_reg_sdioc_f1_ext_code  0xF161
+#define reg_sdioc_f1_ext_code_pos 0
+#define reg_sdioc_f1_ext_code_len 8
+#define reg_sdioc_f1_ext_code_lsb 0
+#define xd_p_reg_sdioc_sps  (*(volatile byte xdata *) 0xF162)
+#define    p_reg_sdioc_sps  0xF162
+#define reg_sdioc_sps_pos 0
+#define reg_sdioc_sps_len 1
+#define reg_sdioc_sps_lsb 0
+#define xd_p_reg_sdioc_func1_cis_ptr_7_0    (*(volatile byte xdata *) 0xF169)
+#define    p_reg_sdioc_func1_cis_ptr_7_0    0xF169
+#define reg_sdioc_func1_cis_ptr_7_0_pos 0
+#define reg_sdioc_func1_cis_ptr_7_0_len 8
+#define reg_sdioc_func1_cis_ptr_7_0_lsb 0
+#define xd_p_reg_sdioc_func1_cis_ptr_15_8   (*(volatile byte xdata *) 0xF16A)
+#define    p_reg_sdioc_func1_cis_ptr_15_8   0xF16A
+#define reg_sdioc_func1_cis_ptr_15_8_pos 0
+#define reg_sdioc_func1_cis_ptr_15_8_len 8
+#define reg_sdioc_func1_cis_ptr_15_8_lsb 8
+#define xd_p_reg_sdioc_func1_cis_ptr_23_16  (*(volatile byte xdata *) 0xF16B)
+#define    p_reg_sdioc_func1_cis_ptr_23_16  0xF16B
+#define reg_sdioc_func1_cis_ptr_23_16_pos 0
+#define reg_sdioc_func1_cis_ptr_23_16_len 8
+#define reg_sdioc_func1_cis_ptr_23_16_lsb 16
+#define xd_p_reg_sdio_FUNCID0_0 (*(volatile byte xdata *) 0xF180)
+#define    p_reg_sdio_FUNCID0_0 0xF180
+#define reg_sdio_FUNCID0_0_pos 0
+#define reg_sdio_FUNCID0_0_len 8
+#define reg_sdio_FUNCID0_0_lsb 0
+#define xd_p_reg_sdio_FUNCID0_1 (*(volatile byte xdata *) 0xF181)
+#define    p_reg_sdio_FUNCID0_1 0xF181
+#define reg_sdio_FUNCID0_1_pos 0
+#define reg_sdio_FUNCID0_1_len 8
+#define reg_sdio_FUNCID0_1_lsb 0
+#define xd_p_reg_sdio_FUNCID0_2 (*(volatile byte xdata *) 0xF182)
+#define    p_reg_sdio_FUNCID0_2 0xF182
+#define reg_sdio_FUNCID0_2_pos 0
+#define reg_sdio_FUNCID0_2_len 8
+#define reg_sdio_FUNCID0_2_lsb 0
+#define xd_p_reg_sdio_FUNCID0_3 (*(volatile byte xdata *) 0xF183)
+#define    p_reg_sdio_FUNCID0_3 0xF183
+#define reg_sdio_FUNCID0_3_pos 0
+#define reg_sdio_FUNCID0_3_len 8
+#define reg_sdio_FUNCID0_3_lsb 0
+#define xd_p_reg_sdio_MANFID0_0 (*(volatile byte xdata *) 0xF184)
+#define    p_reg_sdio_MANFID0_0 0xF184
+#define reg_sdio_MANFID0_0_pos 0
+#define reg_sdio_MANFID0_0_len 8
+#define reg_sdio_MANFID0_0_lsb 0
+#define xd_p_reg_sdio_MANFID0_1 (*(volatile byte xdata *) 0xF185)
+#define    p_reg_sdio_MANFID0_1 0xF185
+#define reg_sdio_MANFID0_1_pos 0
+#define reg_sdio_MANFID0_1_len 8
+#define reg_sdio_MANFID0_1_lsb 0
+#define xd_p_reg_sdio_MANFID0_2_7_0 (*(volatile byte xdata *) 0xF186)
+#define    p_reg_sdio_MANFID0_2_7_0 0xF186
+#define reg_sdio_MANFID0_2_7_0_pos 0
+#define reg_sdio_MANFID0_2_7_0_len 8
+#define reg_sdio_MANFID0_2_7_0_lsb 0
+#define xd_p_reg_sdio_MANFID0_2_15_8    (*(volatile byte xdata *) 0xF187)
+#define    p_reg_sdio_MANFID0_2_15_8    0xF187
+#define reg_sdio_MANFID0_2_15_8_pos 0
+#define reg_sdio_MANFID0_2_15_8_len 8
+#define reg_sdio_MANFID0_2_15_8_lsb 8
+#define xd_p_reg_sdio_MANFID0_4_7_0 (*(volatile byte xdata *) 0xF188)
+#define    p_reg_sdio_MANFID0_4_7_0 0xF188
+#define reg_sdio_MANFID0_4_7_0_pos 0
+#define reg_sdio_MANFID0_4_7_0_len 8
+#define reg_sdio_MANFID0_4_7_0_lsb 0
+#define xd_p_reg_sdio_MANFID0_4_15_8    (*(volatile byte xdata *) 0xF189)
+#define    p_reg_sdio_MANFID0_4_15_8    0xF189
+#define reg_sdio_MANFID0_4_15_8_pos 0
+#define reg_sdio_MANFID0_4_15_8_len 8
+#define reg_sdio_MANFID0_4_15_8_lsb 8
+#define xd_p_reg_sdio_FUNCE0_0  (*(volatile byte xdata *) 0xF18A)
+#define    p_reg_sdio_FUNCE0_0  0xF18A
+#define reg_sdio_FUNCE0_0_pos 0
+#define reg_sdio_FUNCE0_0_len 8
+#define reg_sdio_FUNCE0_0_lsb 0
+#define xd_p_reg_sdio_FUNCE0_1  (*(volatile byte xdata *) 0xF18B)
+#define    p_reg_sdio_FUNCE0_1  0xF18B
+#define reg_sdio_FUNCE0_1_pos 0
+#define reg_sdio_FUNCE0_1_len 8
+#define reg_sdio_FUNCE0_1_lsb 0
+#define xd_p_reg_sdio_FUNCE0_2  (*(volatile byte xdata *) 0xF18C)
+#define    p_reg_sdio_FUNCE0_2  0xF18C
+#define reg_sdio_FUNCE0_2_pos 0
+#define reg_sdio_FUNCE0_2_len 8
+#define reg_sdio_FUNCE0_2_lsb 0
+#define xd_p_reg_sdio_FUNCE0_3_7_0  (*(volatile byte xdata *) 0xF18D)
+#define    p_reg_sdio_FUNCE0_3_7_0  0xF18D
+#define reg_sdio_FUNCE0_3_7_0_pos 0
+#define reg_sdio_FUNCE0_3_7_0_len 8
+#define reg_sdio_FUNCE0_3_7_0_lsb 0
+#define xd_p_reg_sdio_FUNCE0_3_15_8 (*(volatile byte xdata *) 0xF18E)
+#define    p_reg_sdio_FUNCE0_3_15_8 0xF18E
+#define reg_sdio_FUNCE0_3_15_8_pos 0
+#define reg_sdio_FUNCE0_3_15_8_len 8
+#define reg_sdio_FUNCE0_3_15_8_lsb 8
+#define xd_p_reg_sdio_FUNCE0_5  (*(volatile byte xdata *) 0xF18F)
+#define    p_reg_sdio_FUNCE0_5  0xF18F
+#define reg_sdio_FUNCE0_5_pos 0
+#define reg_sdio_FUNCE0_5_len 8
+#define reg_sdio_FUNCE0_5_lsb 0
+#define xd_p_reg_sdio_VERS_10_0 (*(volatile byte xdata *) 0xF190)
+#define    p_reg_sdio_VERS_10_0 0xF190
+#define reg_sdio_VERS_10_0_pos 0
+#define reg_sdio_VERS_10_0_len 8
+#define reg_sdio_VERS_10_0_lsb 0
+#define xd_p_reg_sdio_VERS_10_1 (*(volatile byte xdata *) 0xF191)
+#define    p_reg_sdio_VERS_10_1 0xF191
+#define reg_sdio_VERS_10_1_pos 0
+#define reg_sdio_VERS_10_1_len 8
+#define reg_sdio_VERS_10_1_lsb 0
+#define xd_p_reg_sdio_VERS_10_2 (*(volatile byte xdata *) 0xF192)
+#define    p_reg_sdio_VERS_10_2 0xF192
+#define reg_sdio_VERS_10_2_pos 0
+#define reg_sdio_VERS_10_2_len 8
+#define reg_sdio_VERS_10_2_lsb 0
+#define xd_p_reg_sdio_VERS_10_3 (*(volatile byte xdata *) 0xF193)
+#define    p_reg_sdio_VERS_10_3 0xF193
+#define reg_sdio_VERS_10_3_pos 0
+#define reg_sdio_VERS_10_3_len 8
+#define reg_sdio_VERS_10_3_lsb 0
+#define xd_p_reg_sdio_VERS_10_4 (*(volatile byte xdata *) 0xF194)
+#define    p_reg_sdio_VERS_10_4 0xF194
+#define reg_sdio_VERS_10_4_pos 0
+#define reg_sdio_VERS_10_4_len 8
+#define reg_sdio_VERS_10_4_lsb 0
+#define xd_p_reg_sdio_VERS_10_5 (*(volatile byte xdata *) 0xF195)
+#define    p_reg_sdio_VERS_10_5 0xF195
+#define reg_sdio_VERS_10_5_pos 0
+#define reg_sdio_VERS_10_5_len 8
+#define reg_sdio_VERS_10_5_lsb 0
+#define xd_p_reg_sdio_VERS_10_6 (*(volatile byte xdata *) 0xF196)
+#define    p_reg_sdio_VERS_10_6 0xF196
+#define reg_sdio_VERS_10_6_pos 0
+#define reg_sdio_VERS_10_6_len 8
+#define reg_sdio_VERS_10_6_lsb 0
+#define xd_p_reg_sdio_VERS_10_7 (*(volatile byte xdata *) 0xF197)
+#define    p_reg_sdio_VERS_10_7 0xF197
+#define reg_sdio_VERS_10_7_pos 0
+#define reg_sdio_VERS_10_7_len 8
+#define reg_sdio_VERS_10_7_lsb 0
+#define xd_p_reg_sdio_VERS_10_8 (*(volatile byte xdata *) 0xF198)
+#define    p_reg_sdio_VERS_10_8 0xF198
+#define reg_sdio_VERS_10_8_pos 0
+#define reg_sdio_VERS_10_8_len 8
+#define reg_sdio_VERS_10_8_lsb 0
+#define xd_p_reg_sdio_VERS_10_9 (*(volatile byte xdata *) 0xF199)
+#define    p_reg_sdio_VERS_10_9 0xF199
+#define reg_sdio_VERS_10_9_pos 0
+#define reg_sdio_VERS_10_9_len 8
+#define reg_sdio_VERS_10_9_lsb 0
+#define xd_p_reg_sdio_VERS_10_A (*(volatile byte xdata *) 0xF19A)
+#define    p_reg_sdio_VERS_10_A 0xF19A
+#define reg_sdio_VERS_10_A_pos 0
+#define reg_sdio_VERS_10_A_len 8
+#define reg_sdio_VERS_10_A_lsb 0
+#define xd_p_reg_sdio_VERS_10_B (*(volatile byte xdata *) 0xF19B)
+#define    p_reg_sdio_VERS_10_B 0xF19B
+#define reg_sdio_VERS_10_B_pos 0
+#define reg_sdio_VERS_10_B_len 8
+#define reg_sdio_VERS_10_B_lsb 0
+#define xd_p_reg_sdio_VERS_10_C (*(volatile byte xdata *) 0xF19C)
+#define    p_reg_sdio_VERS_10_C 0xF19C
+#define reg_sdio_VERS_10_C_pos 0
+#define reg_sdio_VERS_10_C_len 8
+#define reg_sdio_VERS_10_C_lsb 0
+#define xd_p_reg_sdio_VERS_10_D (*(volatile byte xdata *) 0xF19D)
+#define    p_reg_sdio_VERS_10_D 0xF19D
+#define reg_sdio_VERS_10_D_pos 0
+#define reg_sdio_VERS_10_D_len 8
+#define reg_sdio_VERS_10_D_lsb 0
+#define xd_p_reg_sdio_VERS_10_E (*(volatile byte xdata *) 0xF19E)
+#define    p_reg_sdio_VERS_10_E 0xF19E
+#define reg_sdio_VERS_10_E_pos 0
+#define reg_sdio_VERS_10_E_len 8
+#define reg_sdio_VERS_10_E_lsb 0
+#define xd_p_reg_sdio_VERS_10_F (*(volatile byte xdata *) 0xF19F)
+#define    p_reg_sdio_VERS_10_F 0xF19F
+#define reg_sdio_VERS_10_F_pos 0
+#define reg_sdio_VERS_10_F_len 8
+#define reg_sdio_VERS_10_F_lsb 0
+#define xd_p_reg_sdio_VERS_10_10    (*(volatile byte xdata *) 0xF1A0)
+#define    p_reg_sdio_VERS_10_10    0xF1A0
+#define reg_sdio_VERS_10_10_pos 0
+#define reg_sdio_VERS_10_10_len 8
+#define reg_sdio_VERS_10_10_lsb 0
+#define xd_p_reg_sdio_VERS_10_11    (*(volatile byte xdata *) 0xF1A1)
+#define    p_reg_sdio_VERS_10_11    0xF1A1
+#define reg_sdio_VERS_10_11_pos 0
+#define reg_sdio_VERS_10_11_len 8
+#define reg_sdio_VERS_10_11_lsb 0
+#define xd_p_reg_sdio_VERS_10_12    (*(volatile byte xdata *) 0xF1A2)
+#define    p_reg_sdio_VERS_10_12    0xF1A2
+#define reg_sdio_VERS_10_12_pos 0
+#define reg_sdio_VERS_10_12_len 8
+#define reg_sdio_VERS_10_12_lsb 0
+#define xd_p_reg_sdio_VERS_10_13    (*(volatile byte xdata *) 0xF1A3)
+#define    p_reg_sdio_VERS_10_13    0xF1A3
+#define reg_sdio_VERS_10_13_pos 0
+#define reg_sdio_VERS_10_13_len 8
+#define reg_sdio_VERS_10_13_lsb 0
+#define xd_p_reg_sdio_VERS_10_14    (*(volatile byte xdata *) 0xF1A4)
+#define    p_reg_sdio_VERS_10_14    0xF1A4
+#define reg_sdio_VERS_10_14_pos 0
+#define reg_sdio_VERS_10_14_len 8
+#define reg_sdio_VERS_10_14_lsb 0
+#define xd_p_reg_sdio_VERS_10_15    (*(volatile byte xdata *) 0xF1A5)
+#define    p_reg_sdio_VERS_10_15    0xF1A5
+#define reg_sdio_VERS_10_15_pos 0
+#define reg_sdio_VERS_10_15_len 8
+#define reg_sdio_VERS_10_15_lsb 0
+#define xd_p_reg_sdio_VERS_10_16    (*(volatile byte xdata *) 0xF1A6)
+#define    p_reg_sdio_VERS_10_16    0xF1A6
+#define reg_sdio_VERS_10_16_pos 0
+#define reg_sdio_VERS_10_16_len 8
+#define reg_sdio_VERS_10_16_lsb 0
+#define xd_p_reg_sdio_VERS_10_17    (*(volatile byte xdata *) 0xF1A7)
+#define    p_reg_sdio_VERS_10_17    0xF1A7
+#define reg_sdio_VERS_10_17_pos 0
+#define reg_sdio_VERS_10_17_len 8
+#define reg_sdio_VERS_10_17_lsb 0
+#define xd_p_reg_sdio_VERS_10_18    (*(volatile byte xdata *) 0xF1A8)
+#define    p_reg_sdio_VERS_10_18    0xF1A8
+#define reg_sdio_VERS_10_18_pos 0
+#define reg_sdio_VERS_10_18_len 8
+#define reg_sdio_VERS_10_18_lsb 0
+#define xd_p_reg_sdio_VERS_10_19    (*(volatile byte xdata *) 0xF1A9)
+#define    p_reg_sdio_VERS_10_19    0xF1A9
+#define reg_sdio_VERS_10_19_pos 0
+#define reg_sdio_VERS_10_19_len 8
+#define reg_sdio_VERS_10_19_lsb 0
+#define xd_p_reg_sdio_VERS_10_1A    (*(volatile byte xdata *) 0xF1AA)
+#define    p_reg_sdio_VERS_10_1A    0xF1AA
+#define reg_sdio_VERS_10_1A_pos 0
+#define reg_sdio_VERS_10_1A_len 8
+#define reg_sdio_VERS_10_1A_lsb 0
+#define xd_p_reg_sdio_VERS_10_1B    (*(volatile byte xdata *) 0xF1AB)
+#define    p_reg_sdio_VERS_10_1B    0xF1AB
+#define reg_sdio_VERS_10_1B_pos 0
+#define reg_sdio_VERS_10_1B_len 8
+#define reg_sdio_VERS_10_1B_lsb 0
+#define xd_p_reg_sdio_VERS_10_1C    (*(volatile byte xdata *) 0xF1AC)
+#define    p_reg_sdio_VERS_10_1C    0xF1AC
+#define reg_sdio_VERS_10_1C_pos 0
+#define reg_sdio_VERS_10_1C_len 8
+#define reg_sdio_VERS_10_1C_lsb 0
+#define xd_p_reg_sdio_VERS_10_1D    (*(volatile byte xdata *) 0xF1AD)
+#define    p_reg_sdio_VERS_10_1D    0xF1AD
+#define reg_sdio_VERS_10_1D_pos 0
+#define reg_sdio_VERS_10_1D_len 8
+#define reg_sdio_VERS_10_1D_lsb 0
+#define xd_p_reg_sdio_VERS_10_1E    (*(volatile byte xdata *) 0xF1AE)
+#define    p_reg_sdio_VERS_10_1E    0xF1AE
+#define reg_sdio_VERS_10_1E_pos 0
+#define reg_sdio_VERS_10_1E_len 8
+#define reg_sdio_VERS_10_1E_lsb 0
+#define xd_p_reg_sdio_VERS_10_1F    (*(volatile byte xdata *) 0xF1AF)
+#define    p_reg_sdio_VERS_10_1F    0xF1AF
+#define reg_sdio_VERS_10_1F_pos 0
+#define reg_sdio_VERS_10_1F_len 8
+#define reg_sdio_VERS_10_1F_lsb 0
+#define xd_p_reg_sdio_VERS_10_20    (*(volatile byte xdata *) 0xF1B0)
+#define    p_reg_sdio_VERS_10_20    0xF1B0
+#define reg_sdio_VERS_10_20_pos 0
+#define reg_sdio_VERS_10_20_len 8
+#define reg_sdio_VERS_10_20_lsb 0
+#define xd_p_reg_sdio_VERS_10_21    (*(volatile byte xdata *) 0xF1B1)
+#define    p_reg_sdio_VERS_10_21    0xF1B1
+#define reg_sdio_VERS_10_21_pos 0
+#define reg_sdio_VERS_10_21_len 8
+#define reg_sdio_VERS_10_21_lsb 0
+#define xd_p_reg_sdio_VERS_10_22    (*(volatile byte xdata *) 0xF1B2)
+#define    p_reg_sdio_VERS_10_22    0xF1B2
+#define reg_sdio_VERS_10_22_pos 0
+#define reg_sdio_VERS_10_22_len 8
+#define reg_sdio_VERS_10_22_lsb 0
+#define xd_p_reg_sdio_VERS_10_23    (*(volatile byte xdata *) 0xF1B3)
+#define    p_reg_sdio_VERS_10_23    0xF1B3
+#define reg_sdio_VERS_10_23_pos 0
+#define reg_sdio_VERS_10_23_len 8
+#define reg_sdio_VERS_10_23_lsb 0
+#define xd_p_reg_sdio_VERS_10_24    (*(volatile byte xdata *) 0xF1B4)
+#define    p_reg_sdio_VERS_10_24    0xF1B4
+#define reg_sdio_VERS_10_24_pos 0
+#define reg_sdio_VERS_10_24_len 8
+#define reg_sdio_VERS_10_24_lsb 0
+#define xd_p_reg_sdio_VERS_10_25    (*(volatile byte xdata *) 0xF1B5)
+#define    p_reg_sdio_VERS_10_25    0xF1B5
+#define reg_sdio_VERS_10_25_pos 0
+#define reg_sdio_VERS_10_25_len 8
+#define reg_sdio_VERS_10_25_lsb 0
+#define xd_p_reg_sdio_VERS_10_26    (*(volatile byte xdata *) 0xF1B6)
+#define    p_reg_sdio_VERS_10_26    0xF1B6
+#define reg_sdio_VERS_10_26_pos 0
+#define reg_sdio_VERS_10_26_len 8
+#define reg_sdio_VERS_10_26_lsb 0
+#define xd_p_reg_sdio_VERS_10_27    (*(volatile byte xdata *) 0xF1B7)
+#define    p_reg_sdio_VERS_10_27    0xF1B7
+#define reg_sdio_VERS_10_27_pos 0
+#define reg_sdio_VERS_10_27_len 8
+#define reg_sdio_VERS_10_27_lsb 0
+#define xd_p_reg_sdio_END0  (*(volatile byte xdata *) 0xF1B8)
+#define    p_reg_sdio_END0  0xF1B8
+#define reg_sdio_END0_pos 0
+#define reg_sdio_END0_len 8
+#define reg_sdio_END0_lsb 0
+#define xd_p_reg_sdio_FUNCID1_0 (*(volatile byte xdata *) 0xF1C0)
+#define    p_reg_sdio_FUNCID1_0 0xF1C0
+#define reg_sdio_FUNCID1_0_pos 0
+#define reg_sdio_FUNCID1_0_len 8
+#define reg_sdio_FUNCID1_0_lsb 0
+#define xd_p_reg_sdio_FUNCID1_1 (*(volatile byte xdata *) 0xF1C1)
+#define    p_reg_sdio_FUNCID1_1 0xF1C1
+#define reg_sdio_FUNCID1_1_pos 0
+#define reg_sdio_FUNCID1_1_len 8
+#define reg_sdio_FUNCID1_1_lsb 0
+#define xd_p_reg_sdio_FUNCID1_2 (*(volatile byte xdata *) 0xF1C2)
+#define    p_reg_sdio_FUNCID1_2 0xF1C2
+#define reg_sdio_FUNCID1_2_pos 0
+#define reg_sdio_FUNCID1_2_len 8
+#define reg_sdio_FUNCID1_2_lsb 0
+#define xd_p_reg_sdio_FUNCID1_3 (*(volatile byte xdata *) 0xF1C3)
+#define    p_reg_sdio_FUNCID1_3 0xF1C3
+#define reg_sdio_FUNCID1_3_pos 0
+#define reg_sdio_FUNCID1_3_len 8
+#define reg_sdio_FUNCID1_3_lsb 0
+#define xd_p_reg_sdio_FUNCE1_0  (*(volatile byte xdata *) 0xF1C4)
+#define    p_reg_sdio_FUNCE1_0  0xF1C4
+#define reg_sdio_FUNCE1_0_pos 0
+#define reg_sdio_FUNCE1_0_len 8
+#define reg_sdio_FUNCE1_0_lsb 0
+#define xd_p_reg_sdio_FUNCE1_1  (*(volatile byte xdata *) 0xF1C5)
+#define    p_reg_sdio_FUNCE1_1  0xF1C5
+#define reg_sdio_FUNCE1_1_pos 0
+#define reg_sdio_FUNCE1_1_len 8
+#define reg_sdio_FUNCE1_1_lsb 0
+#define xd_p_reg_sdio_FUNCE1_2  (*(volatile byte xdata *) 0xF1C6)
+#define    p_reg_sdio_FUNCE1_2  0xF1C6
+#define reg_sdio_FUNCE1_2_pos 0
+#define reg_sdio_FUNCE1_2_len 8
+#define reg_sdio_FUNCE1_2_lsb 0
+#define xd_p_reg_sdio_FUNCE1_3  (*(volatile byte xdata *) 0xF1C7)
+#define    p_reg_sdio_FUNCE1_3  0xF1C7
+#define reg_sdio_FUNCE1_3_pos 0
+#define reg_sdio_FUNCE1_3_len 8
+#define reg_sdio_FUNCE1_3_lsb 0
+#define xd_p_reg_sdio_FUNCE1_4  (*(volatile byte xdata *) 0xF1C8)
+#define    p_reg_sdio_FUNCE1_4  0xF1C8
+#define reg_sdio_FUNCE1_4_pos 0
+#define reg_sdio_FUNCE1_4_len 8
+#define reg_sdio_FUNCE1_4_lsb 0
+#define xd_p_reg_sdio_FUNCE1_5_7_0  (*(volatile byte xdata *) 0xF1C9)
+#define    p_reg_sdio_FUNCE1_5_7_0  0xF1C9
+#define reg_sdio_FUNCE1_5_7_0_pos 0
+#define reg_sdio_FUNCE1_5_7_0_len 8
+#define reg_sdio_FUNCE1_5_7_0_lsb 0
+#define xd_p_reg_sdio_FUNCE1_5_15_8 (*(volatile byte xdata *) 0xF1CA)
+#define    p_reg_sdio_FUNCE1_5_15_8 0xF1CA
+#define reg_sdio_FUNCE1_5_15_8_pos 0
+#define reg_sdio_FUNCE1_5_15_8_len 8
+#define reg_sdio_FUNCE1_5_15_8_lsb 8
+#define xd_p_reg_sdio_FUNCE1_5_23_16    (*(volatile byte xdata *) 0xF1CB)
+#define    p_reg_sdio_FUNCE1_5_23_16    0xF1CB
+#define reg_sdio_FUNCE1_5_23_16_pos 0
+#define reg_sdio_FUNCE1_5_23_16_len 8
+#define reg_sdio_FUNCE1_5_23_16_lsb 16
+#define xd_p_reg_sdio_FUNCE1_5_31_24    (*(volatile byte xdata *) 0xF1CC)
+#define    p_reg_sdio_FUNCE1_5_31_24    0xF1CC
+#define reg_sdio_FUNCE1_5_31_24_pos 0
+#define reg_sdio_FUNCE1_5_31_24_len 8
+#define reg_sdio_FUNCE1_5_31_24_lsb 24
+#define xd_p_reg_sdio_FUNCE1_9_7_0  (*(volatile byte xdata *) 0xF1CD)
+#define    p_reg_sdio_FUNCE1_9_7_0  0xF1CD
+#define reg_sdio_FUNCE1_9_7_0_pos 0
+#define reg_sdio_FUNCE1_9_7_0_len 8
+#define reg_sdio_FUNCE1_9_7_0_lsb 0
+#define xd_p_reg_sdio_FUNCE1_9_15_8 (*(volatile byte xdata *) 0xF1CE)
+#define    p_reg_sdio_FUNCE1_9_15_8 0xF1CE
+#define reg_sdio_FUNCE1_9_15_8_pos 0
+#define reg_sdio_FUNCE1_9_15_8_len 8
+#define reg_sdio_FUNCE1_9_15_8_lsb 8
+#define xd_p_reg_sdio_FUNCE1_9_23_16    (*(volatile byte xdata *) 0xF1CF)
+#define    p_reg_sdio_FUNCE1_9_23_16    0xF1CF
+#define reg_sdio_FUNCE1_9_23_16_pos 0
+#define reg_sdio_FUNCE1_9_23_16_len 8
+#define reg_sdio_FUNCE1_9_23_16_lsb 16
+#define xd_p_reg_sdio_FUNCE1_9_31_24    (*(volatile byte xdata *) 0xF1D0)
+#define    p_reg_sdio_FUNCE1_9_31_24    0xF1D0
+#define reg_sdio_FUNCE1_9_31_24_pos 0
+#define reg_sdio_FUNCE1_9_31_24_len 8
+#define reg_sdio_FUNCE1_9_31_24_lsb 24
+#define xd_p_reg_sdio_FUNCE1_D  (*(volatile byte xdata *) 0xF1D1)
+#define    p_reg_sdio_FUNCE1_D  0xF1D1
+#define reg_sdio_FUNCE1_D_pos 0
+#define reg_sdio_FUNCE1_D_len 8
+#define reg_sdio_FUNCE1_D_lsb 0
+#define xd_p_reg_sdio_FUNCE1_E_7_0  (*(volatile byte xdata *) 0xF1D2)
+#define    p_reg_sdio_FUNCE1_E_7_0  0xF1D2
+#define reg_sdio_FUNCE1_E_7_0_pos 0
+#define reg_sdio_FUNCE1_E_7_0_len 8
+#define reg_sdio_FUNCE1_E_7_0_lsb 0
+#define xd_p_reg_sdio_FUNCE1_E_15_8 (*(volatile byte xdata *) 0xF1D3)
+#define    p_reg_sdio_FUNCE1_E_15_8 0xF1D3
+#define reg_sdio_FUNCE1_E_15_8_pos 0
+#define reg_sdio_FUNCE1_E_15_8_len 8
+#define reg_sdio_FUNCE1_E_15_8_lsb 8
+#define xd_p_reg_sdio_FUNCE1_10_7_0 (*(volatile byte xdata *) 0xF1D4)
+#define    p_reg_sdio_FUNCE1_10_7_0 0xF1D4
+#define reg_sdio_FUNCE1_10_7_0_pos 0
+#define reg_sdio_FUNCE1_10_7_0_len 8
+#define reg_sdio_FUNCE1_10_7_0_lsb 0
+#define xd_p_reg_sdio_FUNCE1_10_15_8    (*(volatile byte xdata *) 0xF1D5)
+#define    p_reg_sdio_FUNCE1_10_15_8    0xF1D5
+#define reg_sdio_FUNCE1_10_15_8_pos 0
+#define reg_sdio_FUNCE1_10_15_8_len 8
+#define reg_sdio_FUNCE1_10_15_8_lsb 8
+#define xd_p_reg_sdio_FUNCE1_10_23_16   (*(volatile byte xdata *) 0xF1D6)
+#define    p_reg_sdio_FUNCE1_10_23_16   0xF1D6
+#define reg_sdio_FUNCE1_10_23_16_pos 0
+#define reg_sdio_FUNCE1_10_23_16_len 8
+#define reg_sdio_FUNCE1_10_23_16_lsb 16
+#define xd_p_reg_sdio_FUNCE1_10_31_24   (*(volatile byte xdata *) 0xF1D7)
+#define    p_reg_sdio_FUNCE1_10_31_24   0xF1D7
+#define reg_sdio_FUNCE1_10_31_24_pos 0
+#define reg_sdio_FUNCE1_10_31_24_len 8
+#define reg_sdio_FUNCE1_10_31_24_lsb 24
+#define xd_p_reg_sdio_FUNCE1_14 (*(volatile byte xdata *) 0xF1D8)
+#define    p_reg_sdio_FUNCE1_14 0xF1D8
+#define reg_sdio_FUNCE1_14_pos 0
+#define reg_sdio_FUNCE1_14_len 8
+#define reg_sdio_FUNCE1_14_lsb 0
+#define xd_p_reg_sdio_FUNCE1_15 (*(volatile byte xdata *) 0xF1D9)
+#define    p_reg_sdio_FUNCE1_15 0xF1D9
+#define reg_sdio_FUNCE1_15_pos 0
+#define reg_sdio_FUNCE1_15_len 8
+#define reg_sdio_FUNCE1_15_lsb 0
+#define xd_p_reg_sdio_FUNCE1_16 (*(volatile byte xdata *) 0xF1DA)
+#define    p_reg_sdio_FUNCE1_16 0xF1DA
+#define reg_sdio_FUNCE1_16_pos 0
+#define reg_sdio_FUNCE1_16_len 8
+#define reg_sdio_FUNCE1_16_lsb 0
+#define xd_p_reg_sdio_FUNCE1_17 (*(volatile byte xdata *) 0xF1DB)
+#define    p_reg_sdio_FUNCE1_17 0xF1DB
+#define reg_sdio_FUNCE1_17_pos 0
+#define reg_sdio_FUNCE1_17_len 8
+#define reg_sdio_FUNCE1_17_lsb 0
+#define xd_p_reg_sdio_FUNCE1_18 (*(volatile byte xdata *) 0xF1DC)
+#define    p_reg_sdio_FUNCE1_18 0xF1DC
+#define reg_sdio_FUNCE1_18_pos 0
+#define reg_sdio_FUNCE1_18_len 8
+#define reg_sdio_FUNCE1_18_lsb 0
+#define xd_p_reg_sdio_FUNCE1_19 (*(volatile byte xdata *) 0xF1DD)
+#define    p_reg_sdio_FUNCE1_19 0xF1DD
+#define reg_sdio_FUNCE1_19_pos 0
+#define reg_sdio_FUNCE1_19_len 8
+#define reg_sdio_FUNCE1_19_lsb 0
+#define xd_p_reg_sdio_FUNCE1_1A_7_0 (*(volatile byte xdata *) 0xF1DE)
+#define    p_reg_sdio_FUNCE1_1A_7_0 0xF1DE
+#define reg_sdio_FUNCE1_1A_7_0_pos 0
+#define reg_sdio_FUNCE1_1A_7_0_len 8
+#define reg_sdio_FUNCE1_1A_7_0_lsb 0
+#define xd_p_reg_sdio_FUNCE1_1A_15_8    (*(volatile byte xdata *) 0xF1DF)
+#define    p_reg_sdio_FUNCE1_1A_15_8    0xF1DF
+#define reg_sdio_FUNCE1_1A_15_8_pos 0
+#define reg_sdio_FUNCE1_1A_15_8_len 8
+#define reg_sdio_FUNCE1_1A_15_8_lsb 8
+#define xd_p_reg_sdio_FUNCE1_1C_7_0 (*(volatile byte xdata *) 0xF1E0)
+#define    p_reg_sdio_FUNCE1_1C_7_0 0xF1E0
+#define reg_sdio_FUNCE1_1C_7_0_pos 0
+#define reg_sdio_FUNCE1_1C_7_0_len 8
+#define reg_sdio_FUNCE1_1C_7_0_lsb 0
+#define xd_p_reg_sdio_FUNCE1_1C_15_8    (*(volatile byte xdata *) 0xF1E1)
+#define    p_reg_sdio_FUNCE1_1C_15_8    0xF1E1
+#define reg_sdio_FUNCE1_1C_15_8_pos 0
+#define reg_sdio_FUNCE1_1C_15_8_len 8
+#define reg_sdio_FUNCE1_1C_15_8_lsb 8
+#define xd_p_reg_sdio_FUNCE1_1E_7_0 (*(volatile byte xdata *) 0xF1E2)
+#define    p_reg_sdio_FUNCE1_1E_7_0 0xF1E2
+#define reg_sdio_FUNCE1_1E_7_0_pos 0
+#define reg_sdio_FUNCE1_1E_7_0_len 8
+#define reg_sdio_FUNCE1_1E_7_0_lsb 0
+#define xd_p_reg_sdio_FUNCE1_1E_15_8    (*(volatile byte xdata *) 0xF1E3)
+#define    p_reg_sdio_FUNCE1_1E_15_8    0xF1E3
+#define reg_sdio_FUNCE1_1E_15_8_pos 0
+#define reg_sdio_FUNCE1_1E_15_8_len 8
+#define reg_sdio_FUNCE1_1E_15_8_lsb 8
+#define xd_p_reg_sdio_FUNCE1_20_7_0 (*(volatile byte xdata *) 0xF1E4)
+#define    p_reg_sdio_FUNCE1_20_7_0 0xF1E4
+#define reg_sdio_FUNCE1_20_7_0_pos 0
+#define reg_sdio_FUNCE1_20_7_0_len 8
+#define reg_sdio_FUNCE1_20_7_0_lsb 0
+#define xd_p_reg_sdio_FUNCE1_20_15_8    (*(volatile byte xdata *) 0xF1E5)
+#define    p_reg_sdio_FUNCE1_20_15_8    0xF1E5
+#define reg_sdio_FUNCE1_20_15_8_pos 0
+#define reg_sdio_FUNCE1_20_15_8_len 8
+#define reg_sdio_FUNCE1_20_15_8_lsb 8
+#define xd_p_reg_sdio_FUNCE1_22_7_0 (*(volatile byte xdata *) 0xF1E6)
+#define    p_reg_sdio_FUNCE1_22_7_0 0xF1E6
+#define reg_sdio_FUNCE1_22_7_0_pos 0
+#define reg_sdio_FUNCE1_22_7_0_len 8
+#define reg_sdio_FUNCE1_22_7_0_lsb 0
+#define xd_p_reg_sdio_FUNCE1_22_15_8    (*(volatile byte xdata *) 0xF1E7)
+#define    p_reg_sdio_FUNCE1_22_15_8    0xF1E7
+#define reg_sdio_FUNCE1_22_15_8_pos 0
+#define reg_sdio_FUNCE1_22_15_8_len 8
+#define reg_sdio_FUNCE1_22_15_8_lsb 8
+#define xd_p_reg_sdio_FUNCE1_24_7_0 (*(volatile byte xdata *) 0xF1E8)
+#define    p_reg_sdio_FUNCE1_24_7_0 0xF1E8
+#define reg_sdio_FUNCE1_24_7_0_pos 0
+#define reg_sdio_FUNCE1_24_7_0_len 8
+#define reg_sdio_FUNCE1_24_7_0_lsb 0
+#define xd_p_reg_sdio_FUNCE1_24_15_8    (*(volatile byte xdata *) 0xF1E9)
+#define    p_reg_sdio_FUNCE1_24_15_8    0xF1E9
+#define reg_sdio_FUNCE1_24_15_8_pos 0
+#define reg_sdio_FUNCE1_24_15_8_len 8
+#define reg_sdio_FUNCE1_24_15_8_lsb 8
+#define xd_p_reg_sdio_FUNCE1_26_7_0 (*(volatile byte xdata *) 0xF1EA)
+#define    p_reg_sdio_FUNCE1_26_7_0 0xF1EA
+#define reg_sdio_FUNCE1_26_7_0_pos 0
+#define reg_sdio_FUNCE1_26_7_0_len 8
+#define reg_sdio_FUNCE1_26_7_0_lsb 0
+#define xd_p_reg_sdio_FUNCE1_26_15_8    (*(volatile byte xdata *) 0xF1EB)
+#define    p_reg_sdio_FUNCE1_26_15_8    0xF1EB
+#define reg_sdio_FUNCE1_26_15_8_pos 0
+#define reg_sdio_FUNCE1_26_15_8_len 8
+#define reg_sdio_FUNCE1_26_15_8_lsb 8
+#define xd_p_reg_sdio_FUNCE1_28_7_0 (*(volatile byte xdata *) 0xF1EC)
+#define    p_reg_sdio_FUNCE1_28_7_0 0xF1EC
+#define reg_sdio_FUNCE1_28_7_0_pos 0
+#define reg_sdio_FUNCE1_28_7_0_len 8
+#define reg_sdio_FUNCE1_28_7_0_lsb 0
+#define xd_p_reg_sdio_FUNCE1_28_15_8    (*(volatile byte xdata *) 0xF1ED)
+#define    p_reg_sdio_FUNCE1_28_15_8    0xF1ED
+#define reg_sdio_FUNCE1_28_15_8_pos 0
+#define reg_sdio_FUNCE1_28_15_8_len 8
+#define reg_sdio_FUNCE1_28_15_8_lsb 8
+#define xd_p_reg_sdio_FUNCE1_2A_7_0 (*(volatile byte xdata *) 0xF1EE)
+#define    p_reg_sdio_FUNCE1_2A_7_0 0xF1EE
+#define reg_sdio_FUNCE1_2A_7_0_pos 0
+#define reg_sdio_FUNCE1_2A_7_0_len 8
+#define reg_sdio_FUNCE1_2A_7_0_lsb 0
+#define xd_p_reg_sdio_FUNCE1_2A_15_8    (*(volatile byte xdata *) 0xF1EF)
+#define    p_reg_sdio_FUNCE1_2A_15_8    0xF1EF
+#define reg_sdio_FUNCE1_2A_15_8_pos 0
+#define reg_sdio_FUNCE1_2A_15_8_len 8
+#define reg_sdio_FUNCE1_2A_15_8_lsb 8
+#define xd_p_reg_sdio_END1  (*(volatile byte xdata *) 0xF1F0)
+#define    p_reg_sdio_END1  0xF1F0
+#define reg_sdio_END1_pos 0
+#define reg_sdio_END1_len 8
+#define reg_sdio_END1_lsb 0
+#define xd_r_sdioc_tx_fifo_empty    (*(volatile byte xdata *) 0xF210)
+#define    r_sdioc_tx_fifo_empty    0xF210
+#define sdioc_tx_fifo_empty_pos 0
+#define sdioc_tx_fifo_empty_len 1
+#define sdioc_tx_fifo_empty_lsb 0
+#define xd_p_reg_sdio_53ra  (*(volatile byte xdata *) 0xF210)
+#define    p_reg_sdio_53ra  0xF210
+#define reg_sdio_53ra_pos 1
+#define reg_sdio_53ra_len 1
+#define reg_sdio_53ra_lsb 0
+#define xd_p_reg_sdioc_rd_wait_dly  (*(volatile byte xdata *) 0xF210)
+#define    p_reg_sdioc_rd_wait_dly  0xF210
+#define reg_sdioc_rd_wait_dly_pos 4
+#define reg_sdioc_rd_wait_dly_len 2
+#define reg_sdioc_rd_wait_dly_lsb 0
+#define xd_p_reg_write_mbx_complete (*(volatile byte xdata *) 0xF211)
+#define    p_reg_write_mbx_complete 0xF211
+#define reg_write_mbx_complete_pos 0
+#define reg_write_mbx_complete_len 1
+#define reg_write_mbx_complete_lsb 0
+#define xd_p_reg_sdioc_sw_err   (*(volatile byte xdata *) 0xF211)
+#define    p_reg_sdioc_sw_err   0xF211
+#define reg_sdioc_sw_err_pos 1
+#define reg_sdioc_sw_err_len 1
+#define reg_sdioc_sw_err_lsb 0
+#define xd_p_reg_sdioc_tran_dat_dly (*(volatile byte xdata *) 0xF211)
+#define    p_reg_sdioc_tran_dat_dly 0xF211
+#define reg_sdioc_tran_dat_dly_pos 4
+#define reg_sdioc_tran_dat_dly_len 3
+#define reg_sdioc_tran_dat_dly_lsb 0
+#define xd_p_reg_sdioc_external_int_en  (*(volatile byte xdata *) 0xF212)
+#define    p_reg_sdioc_external_int_en  0xF212
+#define reg_sdioc_external_int_en_pos 1
+#define reg_sdioc_external_int_en_len 1
+#define reg_sdioc_external_int_en_lsb 0
+#define xd_r_reg_sdioc_external_int (*(volatile byte xdata *) 0xF212)
+#define    r_reg_sdioc_external_int 0xF212
+#define reg_sdioc_external_int_pos 2
+#define reg_sdioc_external_int_len 1
+#define reg_sdioc_external_int_lsb 0
+#define xd_p_reg_auto_clrWB_en  (*(volatile byte xdata *) 0xF213)
+#define    p_reg_auto_clrWB_en  0xF213
+#define reg_auto_clrWB_en_pos 0
+#define reg_auto_clrWB_en_len 1
+#define reg_auto_clrWB_en_lsb 0
+#define xd_p_reg_sdioc_crc_s_dly    (*(volatile byte xdata *) 0xF213)
+#define    p_reg_sdioc_crc_s_dly    0xF213
+#define reg_sdioc_crc_s_dly_pos 1
+#define reg_sdioc_crc_s_dly_len 1
+#define reg_sdioc_crc_s_dly_lsb 0
+#define xd_p_reg_sdioc_neg_out_sel  (*(volatile byte xdata *) 0xF213)
+#define    p_reg_sdioc_neg_out_sel  0xF213
+#define reg_sdioc_neg_out_sel_pos 2
+#define reg_sdioc_neg_out_sel_len 1
+#define reg_sdioc_neg_out_sel_lsb 0
+#define xd_p_reg_sdioc_tx_fifo_rst  (*(volatile byte xdata *) 0xF213)
+#define    p_reg_sdioc_tx_fifo_rst  0xF213
+#define reg_sdioc_tx_fifo_rst_pos 4
+#define reg_sdioc_tx_fifo_rst_len 1
+#define reg_sdioc_tx_fifo_rst_lsb 0
+#define xd_p_reg_sdioc_rx_fifo_rst  (*(volatile byte xdata *) 0xF213)
+#define    p_reg_sdioc_rx_fifo_rst  0xF213
+#define reg_sdioc_rx_fifo_rst_pos 5
+#define reg_sdioc_rx_fifo_rst_len 1
+#define reg_sdioc_rx_fifo_rst_lsb 0
+#define xd_p_reg_sdioc_auto_rst_sm_en   (*(volatile byte xdata *) 0xF213)
+#define    p_reg_sdioc_auto_rst_sm_en   0xF213
+#define reg_sdioc_auto_rst_sm_en_pos 6
+#define reg_sdioc_auto_rst_sm_en_len 1
+#define reg_sdioc_auto_rst_sm_en_lsb 0
+#define xd_p_sdio_link_clr_Wbusy_en (*(volatile byte xdata *) 0xF214)
+#define    p_sdio_link_clr_Wbusy_en 0xF214
+#define sdio_link_clr_Wbusy_en_pos 0
+#define sdio_link_clr_Wbusy_en_len 1
+#define sdio_link_clr_Wbusy_en_lsb 0
+#define xd_p_sdio_link_clr_Wbusy    (*(volatile byte xdata *) 0xF214)
+#define    p_sdio_link_clr_Wbusy    0xF214
+#define sdio_link_clr_Wbusy_pos 1
+#define sdio_link_clr_Wbusy_len 1
+#define sdio_link_clr_Wbusy_lsb 0
+#define xd_p_reg_sdioc_dbg_sel  (*(volatile byte xdata *) 0xF214)
+#define    p_reg_sdioc_dbg_sel  0xF214
+#define reg_sdioc_dbg_sel_pos 4
+#define reg_sdioc_dbg_sel_len 4
+#define reg_sdioc_dbg_sel_lsb 0
+#define xd_p_reg_sdioc_skip_ocr (*(volatile byte xdata *) 0xF215)
+#define    p_reg_sdioc_skip_ocr 0xF215
+#define reg_sdioc_skip_ocr_pos 0
+#define reg_sdioc_skip_ocr_len 1
+#define reg_sdioc_skip_ocr_lsb 0
+#define xd_p_reg_sdioc_spi_ns   (*(volatile byte xdata *) 0xF215)
+#define    p_reg_sdioc_spi_ns   0xF215
+#define reg_sdioc_spi_ns_pos 1
+#define reg_sdioc_spi_ns_len 1
+#define reg_sdioc_spi_ns_lsb 0
+#define xd_r_sdio_spi_mode  (*(volatile byte xdata *) 0xF215)
+#define    r_sdio_spi_mode  0xF215
+#define sdio_spi_mode_pos 7
+#define sdio_spi_mode_len 1
+#define sdio_spi_mode_lsb 0
+#define xd_r_link_ofsm_mailbox_int  (*(volatile byte xdata *) 0xF402)
+#define    r_link_ofsm_mailbox_int  0xF402
+#define link_ofsm_mailbox_int_pos 4
+#define link_ofsm_mailbox_int_len 1
+#define link_ofsm_mailbox_int_lsb 0
+#define xd_r_link_ofsm_dvbt_int (*(volatile byte xdata *) 0xF403)
+#define    r_link_ofsm_dvbt_int 0xF403
+#define link_ofsm_dvbt_int_pos 2
+#define link_ofsm_dvbt_int_len 1
+#define link_ofsm_dvbt_int_lsb 0
+#define xd_p_reg_dvbt_intsts    (*(volatile byte xdata *) 0xF404)
+#define    p_reg_dvbt_intsts    0xF404
+#define reg_dvbt_intsts_pos 2
+#define reg_dvbt_intsts_len 1
+#define reg_dvbt_intsts_lsb 0
+#define xd_p_reg_link_mailbox_int   (*(volatile byte xdata *) 0xF405)
+#define    p_reg_link_mailbox_int   0xF405
+#define reg_link_mailbox_int_pos 5
+#define reg_link_mailbox_int_len 1
+#define reg_link_mailbox_int_lsb 0
+#define xd_p_reg_mailbox_wptr_rst   (*(volatile byte xdata *) 0xF408)
+#define    p_reg_mailbox_wptr_rst   0xF408
+#define reg_mailbox_wptr_rst_pos 0
+#define reg_mailbox_wptr_rst_len 1
+#define reg_mailbox_wptr_rst_lsb 0
+#define xd_p_reg_link_mailbox_wptr  (*(volatile byte xdata *) 0xF409)
+#define    p_reg_link_mailbox_wptr  0xF409
+#define reg_link_mailbox_wptr_pos 0
+#define reg_link_mailbox_wptr_len 8
+#define reg_link_mailbox_wptr_lsb 0
+#define xd_p_reg_link_mailbox_wend  (*(volatile byte xdata *) 0xF410)
+#define    p_reg_link_mailbox_wend  0xF410
+#define reg_link_mailbox_wend_pos 0
+#define reg_link_mailbox_wend_len 1
+#define reg_link_mailbox_wend_lsb 0
+#define xd_p_reg_rd_data_sel    (*(volatile byte xdata *) 0xF411)
+#define    p_reg_rd_data_sel    0xF411
+#define reg_rd_data_sel_pos 0
+#define reg_rd_data_sel_len 2
+#define reg_rd_data_sel_lsb 0
+#define xd_p_reg_fifo_rd_length_7_0 (*(volatile byte xdata *) 0xF412)
+#define    p_reg_fifo_rd_length_7_0 0xF412
+#define reg_fifo_rd_length_7_0_pos 0
+#define reg_fifo_rd_length_7_0_len 8
+#define reg_fifo_rd_length_7_0_lsb 0
+#define xd_p_reg_fifo_rd_length_15_8    (*(volatile byte xdata *) 0xF413)
+#define    p_reg_fifo_rd_length_15_8    0xF413
+#define reg_fifo_rd_length_15_8_pos 0
+#define reg_fifo_rd_length_15_8_len 8
+#define reg_fifo_rd_length_15_8_lsb 8
+#define xd_p_reg_fifo_rd_length_17_16   (*(volatile byte xdata *) 0xF414)
+#define    p_reg_fifo_rd_length_17_16   0xF414
+#define reg_fifo_rd_length_17_16_pos 0
+#define reg_fifo_rd_length_17_16_len 2
+#define reg_fifo_rd_length_17_16_lsb 16
+#define xd_p_reg_rst_fifo_rptr  (*(volatile byte xdata *) 0xF414)
+#define    p_reg_rst_fifo_rptr  0xF414
+#define reg_rst_fifo_rptr_pos 6
+#define reg_rst_fifo_rptr_len 1
+#define reg_rst_fifo_rptr_lsb 0
+#define xd_p_reg_force_sel  (*(volatile byte xdata *) 0xF414)
+#define    p_reg_force_sel  0xF414
+#define reg_force_sel_pos 7
+#define reg_force_sel_len 1
+#define reg_force_sel_lsb 0
+#define xd_p_reg_fifo_rptr_7_0  (*(volatile byte xdata *) 0xF415)
+#define    p_reg_fifo_rptr_7_0  0xF415
+#define reg_fifo_rptr_7_0_pos 0
+#define reg_fifo_rptr_7_0_len 8
+#define reg_fifo_rptr_7_0_lsb 0
+#define xd_p_reg_fifo_rptr_15_8 (*(volatile byte xdata *) 0xF416)
+#define    p_reg_fifo_rptr_15_8 0xF416
+#define reg_fifo_rptr_15_8_pos 0
+#define reg_fifo_rptr_15_8_len 8
+#define reg_fifo_rptr_15_8_lsb 8
+#define xd_p_reg_fifo_rptr_17_16    (*(volatile byte xdata *) 0xF417)
+#define    p_reg_fifo_rptr_17_16    0xF417
+#define reg_fifo_rptr_17_16_pos 0
+#define reg_fifo_rptr_17_16_len 2
+#define reg_fifo_rptr_17_16_lsb 16
+#define xd_p_reg_max_package_size_7_0   (*(volatile byte xdata *) 0xF418)
+#define    p_reg_max_package_size_7_0   0xF418
+#define reg_max_package_size_7_0_pos 0
+#define reg_max_package_size_7_0_len 8
+#define reg_max_package_size_7_0_lsb 0
+#define xd_p_reg_max_package_size_11_8  (*(volatile byte xdata *) 0xF419)
+#define    p_reg_max_package_size_11_8  0xF419
+#define reg_max_package_size_11_8_pos 0
+#define reg_max_package_size_11_8_len 4
+#define reg_max_package_size_11_8_lsb 8
+#define xd_p_reg_dvbt_en    (*(volatile byte xdata *) 0xF41A)
+#define    p_reg_dvbt_en    0xF41A
+#define reg_dvbt_en_pos 0
+#define reg_dvbt_en_len 1
+#define reg_dvbt_en_lsb 0
+#define xd_p_reg_dvbt_bufsize   (*(volatile byte xdata *) 0xF41A)
+#define    p_reg_dvbt_bufsize   0xF41A
+#define reg_dvbt_bufsize_pos 1
+#define reg_dvbt_bufsize_len 1
+#define reg_dvbt_bufsize_lsb 0
+#define xd_p_reg_dvbt_path  (*(volatile byte xdata *) 0xF41A)
+#define    p_reg_dvbt_path  0xF41A
+#define reg_dvbt_path_pos 2
+#define reg_dvbt_path_len 1
+#define reg_dvbt_path_lsb 0
+#define xd_p_reg_dvbt_r5    (*(volatile byte xdata *) 0xF41A)
+#define    p_reg_dvbt_r5    0xF41A
+#define reg_dvbt_r5_pos 3
+#define reg_dvbt_r5_len 1
+#define reg_dvbt_r5_lsb 0
+#define xd_p_reg_mailbox_inten  (*(volatile byte xdata *) 0xF41E)
+#define    p_reg_mailbox_inten  0xF41E
+#define reg_mailbox_inten_pos 4
+#define reg_mailbox_inten_len 1
+#define reg_mailbox_inten_lsb 0
+#define xd_p_reg_dvbt_inten (*(volatile byte xdata *) 0xF41F)
+#define    p_reg_dvbt_inten 0xF41F
+#define reg_dvbt_inten_pos 2
+#define reg_dvbt_inten_len 1
+#define reg_dvbt_inten_lsb 0
+#define xd_r_link_ofsm_ip_length_7_0    (*(volatile byte xdata *) 0xF447)
+#define    r_link_ofsm_ip_length_7_0    0xF447
+#define link_ofsm_ip_length_7_0_pos 0
+#define link_ofsm_ip_length_7_0_len 8
+#define link_ofsm_ip_length_7_0_lsb 0
+#define xd_r_link_ofsm_ip_length_11_8   (*(volatile byte xdata *) 0xF448)
+#define    r_link_ofsm_ip_length_11_8   0xF448
+#define link_ofsm_ip_length_11_8_pos 0
+#define link_ofsm_ip_length_11_8_len 4
+#define link_ofsm_ip_length_11_8_lsb 8
+#define xd_r_link_ofsm_ip_valid (*(volatile byte xdata *) 0xF448)
+#define    r_link_ofsm_ip_valid 0xF448
+#define link_ofsm_ip_valid_pos 7
+#define link_ofsm_ip_valid_len 1
+#define link_ofsm_ip_valid_lsb 0
+#define xd_p_reg_spi_master (*(volatile byte xdata *) 0xF600)
+#define    p_reg_spi_master 0xF600
+#define reg_spi_master_pos 0
+#define reg_spi_master_len 1
+#define reg_spi_master_lsb 0
+#define xd_p_reg_spi_bit    (*(volatile byte xdata *) 0xF601)
+#define    p_reg_spi_bit    0xF601
+#define reg_spi_bit_pos 0
+#define reg_spi_bit_len 2
+#define reg_spi_bit_lsb 0
+#define xd_p_reg_spi_cs (*(volatile byte xdata *) 0xF602)
+#define    p_reg_spi_cs 0xF602
+#define reg_spi_cs_pos 0
+#define reg_spi_cs_len 1
+#define reg_spi_cs_lsb 0
+#define xd_p_reg_spi_polarity   (*(volatile byte xdata *) 0xF602)
+#define    p_reg_spi_polarity   0xF602
+#define reg_spi_polarity_pos 1
+#define reg_spi_polarity_len 1
+#define reg_spi_polarity_lsb 0
+#define xd_p_reg_spi_phase  (*(volatile byte xdata *) 0xF602)
+#define    p_reg_spi_phase  0xF602
+#define reg_spi_phase_pos 2
+#define reg_spi_phase_len 1
+#define reg_spi_phase_lsb 0
+#define xd_p_reg_spi_1st_byte   (*(volatile byte xdata *) 0xF603)
+#define    p_reg_spi_1st_byte   0xF603
+#define reg_spi_1st_byte_pos 0
+#define reg_spi_1st_byte_len 4
+#define reg_spi_1st_byte_lsb 0
+#define xd_p_reg_spi_clk_div    (*(volatile byte xdata *) 0xF603)
+#define    p_reg_spi_clk_div    0xF603
+#define reg_spi_clk_div_pos 4
+#define reg_spi_clk_div_len 4
+#define reg_spi_clk_div_lsb 0
+#define xd_p_reg_spi_rst    (*(volatile byte xdata *) 0xF604)
+#define    p_reg_spi_rst    0xF604
+#define reg_spi_rst_pos 0
+#define reg_spi_rst_len 1
+#define reg_spi_rst_lsb 0
+#define xd_r_reg_spi_tx_done    (*(volatile byte xdata *) 0xF604)
+#define    r_reg_spi_tx_done    0xF604
+#define reg_spi_tx_done_pos 1
+#define reg_spi_tx_done_len 1
+#define reg_spi_tx_done_lsb 0
+#define xd_r_reg_spi_rx_done    (*(volatile byte xdata *) 0xF604)
+#define    r_reg_spi_rx_done    0xF604
+#define reg_spi_rx_done_pos 2
+#define reg_spi_rx_done_len 1
+#define reg_spi_rx_done_lsb 0
+#define xd_p_reg_spi_dbg_sel    (*(volatile byte xdata *) 0xF604)
+#define    p_reg_spi_dbg_sel    0xF604
+#define reg_spi_dbg_sel_pos 3
+#define reg_spi_dbg_sel_len 1
+#define reg_spi_dbg_sel_lsb 0
+#define xd_r_reg_spi_crc_err    (*(volatile byte xdata *) 0xF604)
+#define    r_reg_spi_crc_err    0xF604
+#define reg_spi_crc_err_pos 4
+#define reg_spi_crc_err_len 4
+#define reg_spi_crc_err_lsb 0
+#define xd_r_link_ofsm_usb20_mode   (*(volatile byte xdata *) 0xF613)
+#define    r_link_ofsm_usb20_mode   0xF613
+#define link_ofsm_usb20_mode_pos 0
+#define link_ofsm_usb20_mode_len 1
+#define link_ofsm_usb20_mode_lsb 0
+#define xd_r_link_ofsm_strap_usb20_mode (*(volatile byte xdata *) 0xF613)
+#define    r_link_ofsm_strap_usb20_mode 0xF613
+#define link_ofsm_strap_usb20_mode_pos 1
+#define link_ofsm_strap_usb20_mode_len 1
+#define link_ofsm_strap_usb20_mode_lsb 0
+#define xd_p_reg_link_stick_mem_end_7_0 (*(volatile byte xdata *) 0xF618)
+#define    p_reg_link_stick_mem_end_7_0 0xF618
+#define reg_link_stick_mem_end_7_0_pos 0
+#define reg_link_stick_mem_end_7_0_len 8
+#define reg_link_stick_mem_end_7_0_lsb 0
+#define xd_p_reg_link_stick_mem_end_15_8    (*(volatile byte xdata *) 0xF619)
+#define    p_reg_link_stick_mem_end_15_8    0xF619
+#define reg_link_stick_mem_end_15_8_pos 0
+#define reg_link_stick_mem_end_15_8_len 8
+#define reg_link_stick_mem_end_15_8_lsb 8
+#define xd_p_reg_ofdm_auto_write_addr_l (*(volatile byte xdata *) 0xF61A)
+#define    p_reg_ofdm_auto_write_addr_l 0xF61A
+#define reg_ofdm_auto_write_addr_l_pos 0
+#define reg_ofdm_auto_write_addr_l_len 8
+#define reg_ofdm_auto_write_addr_l_lsb 0
+#define xd_p_reg_ofdm_auto_write_addr_h (*(volatile byte xdata *) 0xF61B)
+#define    p_reg_ofdm_auto_write_addr_h 0xF61B
+#define reg_ofdm_auto_write_addr_h_pos 0
+#define reg_ofdm_auto_write_addr_h_len 8
+#define reg_ofdm_auto_write_addr_h_lsb 0
+#define xd_p_reg_link_auto_write_addr_l (*(volatile byte xdata *) 0xF61C)
+#define    p_reg_link_auto_write_addr_l 0xF61C
+#define reg_link_auto_write_addr_l_pos 0
+#define reg_link_auto_write_addr_l_len 8
+#define reg_link_auto_write_addr_l_lsb 0
+#define xd_p_reg_link_auto_write_addr_h (*(volatile byte xdata *) 0xF61D)
+#define    p_reg_link_auto_write_addr_h 0xF61D
+#define reg_link_auto_write_addr_h_pos 0
+#define reg_link_auto_write_addr_h_len 8
+#define reg_link_auto_write_addr_h_lsb 0
+#define xd_p_reg_mailbox_auto_write_addr    (*(volatile byte xdata *) 0xF61E)
+#define    p_reg_mailbox_auto_write_addr    0xF61E
+#define reg_mailbox_auto_write_addr_pos 0
+#define reg_mailbox_auto_write_addr_len 8
+#define reg_mailbox_auto_write_addr_lsb 0
+#define xd_p_reg_usbmem_auto_write_addr (*(volatile byte xdata *) 0xF61F)
+#define    p_reg_usbmem_auto_write_addr 0xF61F
+#define reg_usbmem_auto_write_addr_pos 0
+#define reg_usbmem_auto_write_addr_len 8
+#define reg_usbmem_auto_write_addr_lsb 0
+#define xd_p_reg_mailbox_auto_read_addr (*(volatile byte xdata *) 0xF620)
+#define    p_reg_mailbox_auto_read_addr 0xF620
+#define reg_mailbox_auto_read_addr_pos 0
+#define reg_mailbox_auto_read_addr_len 8
+#define reg_mailbox_auto_read_addr_lsb 0
+#define xd_p_reg_usbmem_auto_read_addr  (*(volatile byte xdata *) 0xF621)
+#define    p_reg_usbmem_auto_read_addr  0xF621
+#define reg_usbmem_auto_read_addr_pos 0
+#define reg_usbmem_auto_read_addr_len 8
+#define reg_usbmem_auto_read_addr_lsb 0
+#define xd_p_reg_auto_write_ofdm    (*(volatile byte xdata *) 0xF622)
+#define    p_reg_auto_write_ofdm    0xF622
+#define reg_auto_write_ofdm_pos 0
+#define reg_auto_write_ofdm_len 1
+#define reg_auto_write_ofdm_lsb 0
+#define xd_p_reg_auto_write_link    (*(volatile byte xdata *) 0xF622)
+#define    p_reg_auto_write_link    0xF622
+#define reg_auto_write_link_pos 1
+#define reg_auto_write_link_len 1
+#define reg_auto_write_link_lsb 0
+#define xd_p_reg_auto_write_mailbox (*(volatile byte xdata *) 0xF622)
+#define    p_reg_auto_write_mailbox 0xF622
+#define reg_auto_write_mailbox_pos 2
+#define reg_auto_write_mailbox_len 1
+#define reg_auto_write_mailbox_lsb 0
+#define xd_p_reg_auto_write_usbmem  (*(volatile byte xdata *) 0xF622)
+#define    p_reg_auto_write_usbmem  0xF622
+#define reg_auto_write_usbmem_pos 3
+#define reg_auto_write_usbmem_len 1
+#define reg_auto_write_usbmem_lsb 0
+#define xd_p_reg_auto_write_i2cm    (*(volatile byte xdata *) 0xF622)
+#define    p_reg_auto_write_i2cm    0xF622
+#define reg_auto_write_i2cm_pos 4
+#define reg_auto_write_i2cm_len 1
+#define reg_auto_write_i2cm_lsb 0
+#define xd_p_reg_auto_read_mailbox  (*(volatile byte xdata *) 0xF623)
+#define    p_reg_auto_read_mailbox  0xF623
+#define reg_auto_read_mailbox_pos 0
+#define reg_auto_read_mailbox_len 1
+#define reg_auto_read_mailbox_lsb 0
+#define xd_p_reg_auto_read_rom  (*(volatile byte xdata *) 0xF623)
+#define    p_reg_auto_read_rom  0xF623
+#define reg_auto_read_rom_pos 1
+#define reg_auto_read_rom_len 1
+#define reg_auto_read_rom_lsb 0
+#define xd_p_reg_auto_sum_l (*(volatile byte xdata *) 0xF624)
+#define    p_reg_auto_sum_l 0xF624
+#define reg_auto_sum_l_pos 0
+#define reg_auto_sum_l_len 8
+#define reg_auto_sum_l_lsb 0
+#define xd_p_reg_auto_sum_h (*(volatile byte xdata *) 0xF625)
+#define    p_reg_auto_sum_h 0xF625
+#define reg_auto_sum_h_pos 0
+#define reg_auto_sum_h_len 8
+#define reg_auto_sum_h_lsb 0
+#define xd_p_reg_auto_sum_to_h  (*(volatile byte xdata *) 0xF626)
+#define    p_reg_auto_sum_to_h  0xF626
+#define reg_auto_sum_to_h_pos 0
+#define reg_auto_sum_to_h_len 1
+#define reg_auto_sum_to_h_lsb 0
+#define xd_p_reg_auto_sum_en    (*(volatile byte xdata *) 0xF627)
+#define    p_reg_auto_sum_en    0xF627
+#define reg_auto_sum_en_pos 0
+#define reg_auto_sum_en_len 1
+#define reg_auto_sum_en_lsb 0
+#define xd_p_reg_rom_remap_begin_7_0    (*(volatile byte xdata *) 0xF628)
+#define    p_reg_rom_remap_begin_7_0    0xF628
+#define reg_rom_remap_begin_7_0_pos 0
+#define reg_rom_remap_begin_7_0_len 8
+#define reg_rom_remap_begin_7_0_lsb 0
+#define xd_p_reg_rom_remap_begin_15_8   (*(volatile byte xdata *) 0xF629)
+#define    p_reg_rom_remap_begin_15_8   0xF629
+#define reg_rom_remap_begin_15_8_pos 0
+#define reg_rom_remap_begin_15_8_len 8
+#define reg_rom_remap_begin_15_8_lsb 8
+#define xd_p_reg_rom_remap_end_7_0  (*(volatile byte xdata *) 0xF62A)
+#define    p_reg_rom_remap_end_7_0  0xF62A
+#define reg_rom_remap_end_7_0_pos 0
+#define reg_rom_remap_end_7_0_len 8
+#define reg_rom_remap_end_7_0_lsb 0
+#define xd_p_reg_rom_remap_end_15_8 (*(volatile byte xdata *) 0xF62B)
+#define    p_reg_rom_remap_end_15_8 0xF62B
+#define reg_rom_remap_end_15_8_pos 0
+#define reg_rom_remap_end_15_8_len 8
+#define reg_rom_remap_end_15_8_lsb 8
+#define xd_p_reg_rom_remap_delta_7_0    (*(volatile byte xdata *) 0xF62C)
+#define    p_reg_rom_remap_delta_7_0    0xF62C
+#define reg_rom_remap_delta_7_0_pos 0
+#define reg_rom_remap_delta_7_0_len 8
+#define reg_rom_remap_delta_7_0_lsb 0
+#define xd_p_reg_rom_remap_delta_15_8   (*(volatile byte xdata *) 0xF62D)
+#define    p_reg_rom_remap_delta_15_8   0xF62D
+#define reg_rom_remap_delta_15_8_pos 0
+#define reg_rom_remap_delta_15_8_len 8
+#define reg_rom_remap_delta_15_8_lsb 8
+#define xd_p_reg_rom_remap_en   (*(volatile byte xdata *) 0xF62E)
+#define    p_reg_rom_remap_en   0xF62E
+#define reg_rom_remap_en_pos 0
+#define reg_rom_remap_en_len 1
+#define reg_rom_remap_en_lsb 0
+#define xd_p_reg_rom_remap_ofdm (*(volatile byte xdata *) 0xF62E)
+#define    p_reg_rom_remap_ofdm 0xF62E
+#define reg_rom_remap_ofdm_pos 1
+#define reg_rom_remap_ofdm_len 1
+#define reg_rom_remap_ofdm_lsb 0
+#define xd_p_reg_link_cpu_reset (*(volatile byte xdata *) 0xF62F)
+#define    p_reg_link_cpu_reset 0xF62F
+#define reg_link_cpu_reset_pos 0
+#define reg_link_cpu_reset_len 1
+#define reg_link_cpu_reset_lsb 0
+#define xd_p_reg_i2cm_auto_write_addr   (*(volatile byte xdata *) 0xF630)
+#define    p_reg_i2cm_auto_write_addr   0xF630
+#define reg_i2cm_auto_write_addr_pos 0
+#define reg_i2cm_auto_write_addr_len 8
+#define reg_i2cm_auto_write_addr_lsb 0
+#define xd_p_reg_link_bank_float_en (*(volatile byte xdata *) 0xF631)
+#define    p_reg_link_bank_float_en 0xF631
+#define reg_link_bank_float_en_pos 0
+#define reg_link_bank_float_en_len 1
+#define reg_link_bank_float_en_lsb 0
+#define xd_p_reg_link_bank_float_start  (*(volatile byte xdata *) 0xF632)
+#define    p_reg_link_bank_float_start  0xF632
+#define reg_link_bank_float_start_pos 0
+#define reg_link_bank_float_start_len 8
+#define reg_link_bank_float_start_lsb 0
+#define xd_p_reg_link_bank_float_stop   (*(volatile byte xdata *) 0xF633)
+#define    p_reg_link_bank_float_stop   0xF633
+#define reg_link_bank_float_stop_pos 0
+#define reg_link_bank_float_stop_len 8
+#define reg_link_bank_float_stop_lsb 0
+#define xd_p_reg_rom_auto_read_addr_7_0 (*(volatile byte xdata *) 0xF638)
+#define    p_reg_rom_auto_read_addr_7_0 0xF638
+#define reg_rom_auto_read_addr_7_0_pos 0
+#define reg_rom_auto_read_addr_7_0_len 8
+#define reg_rom_auto_read_addr_7_0_lsb 0
+#define xd_p_reg_rom_auto_read_addr_15_8    (*(volatile byte xdata *) 0xF639)
+#define    p_reg_rom_auto_read_addr_15_8    0xF639
+#define reg_rom_auto_read_addr_15_8_pos 0
+#define reg_rom_auto_read_addr_15_8_len 8
+#define reg_rom_auto_read_addr_15_8_lsb 8
+#define xd_p_reg_link_ofsm_dummy_7_0    (*(volatile byte xdata *) 0xF640)
+#define    p_reg_link_ofsm_dummy_7_0    0xF640
+#define reg_link_ofsm_dummy_7_0_pos 0
+#define reg_link_ofsm_dummy_7_0_len 8
+#define reg_link_ofsm_dummy_7_0_lsb 0
+#define xd_p_reg_link_ofsm_dummy_15_8   (*(volatile byte xdata *) 0xF641)
+#define    p_reg_link_ofsm_dummy_15_8   0xF641
+#define reg_link_ofsm_dummy_15_8_pos 0
+#define reg_link_ofsm_dummy_15_8_len 8
+#define reg_link_ofsm_dummy_15_8_lsb 8
+#define xd_p_reg_link_ofsm_dummy_23_16  (*(volatile byte xdata *) 0xF642)
+#define    p_reg_link_ofsm_dummy_23_16  0xF642
+#define reg_link_ofsm_dummy_23_16_pos 0
+#define reg_link_ofsm_dummy_23_16_len 8
+#define reg_link_ofsm_dummy_23_16_lsb 16
+#define xd_p_reg_link_ofsm_dummy_31_24  (*(volatile byte xdata *) 0xF643)
+#define    p_reg_link_ofsm_dummy_31_24  0xF643
+#define reg_link_ofsm_dummy_31_24_pos 0
+#define reg_link_ofsm_dummy_31_24_len 8
+#define reg_link_ofsm_dummy_31_24_lsb 24
+#define xd_p_reg_link_ofsm_dummy_39_32  (*(volatile byte xdata *) 0xF644)
+#define    p_reg_link_ofsm_dummy_39_32  0xF644
+#define reg_link_ofsm_dummy_39_32_pos 0
+#define reg_link_ofsm_dummy_39_32_len 8
+#define reg_link_ofsm_dummy_39_32_lsb 32
+#define xd_p_reg_link_ofsm_dummy_47_40  (*(volatile byte xdata *) 0xF645)
+#define    p_reg_link_ofsm_dummy_47_40  0xF645
+#define reg_link_ofsm_dummy_47_40_pos 0
+#define reg_link_ofsm_dummy_47_40_len 8
+#define reg_link_ofsm_dummy_47_40_lsb 40
+#define xd_p_reg_link_ofsm_dummy_55_48  (*(volatile byte xdata *) 0xF646)
+#define    p_reg_link_ofsm_dummy_55_48  0xF646
+#define reg_link_ofsm_dummy_55_48_pos 0
+#define reg_link_ofsm_dummy_55_48_len 8
+#define reg_link_ofsm_dummy_55_48_lsb 48
+#define xd_p_reg_link_ofsm_dummy_63_56  (*(volatile byte xdata *) 0xF647)
+#define    p_reg_link_ofsm_dummy_63_56  0xF647
+#define reg_link_ofsm_dummy_63_56_pos 0
+#define reg_link_ofsm_dummy_63_56_len 8
+#define reg_link_ofsm_dummy_63_56_lsb 56
+#define xd_p_reg_link_ofsm_dummy_71_64  (*(volatile byte xdata *) 0xF648)
+#define    p_reg_link_ofsm_dummy_71_64  0xF648
+#define reg_link_ofsm_dummy_71_64_pos 0
+#define reg_link_ofsm_dummy_71_64_len 8
+#define reg_link_ofsm_dummy_71_64_lsb 64
+#define xd_p_reg_link_ofsm_dummy_79_72  (*(volatile byte xdata *) 0xF649)
+#define    p_reg_link_ofsm_dummy_79_72  0xF649
+#define reg_link_ofsm_dummy_79_72_pos 0
+#define reg_link_ofsm_dummy_79_72_len 8
+#define reg_link_ofsm_dummy_79_72_lsb 72
+#define xd_p_reg_sdio_mode  (*(volatile byte xdata *) 0xF66F)
+#define    p_reg_sdio_mode  0xF66F
+#define reg_sdio_mode_pos 0
+#define reg_sdio_mode_len 1
+#define reg_sdio_mode_lsb 0
+#define xd_p_reg_lnk2ofdm_data_7_0  (*(volatile byte xdata *) 0xF6A0)
+#define    p_reg_lnk2ofdm_data_7_0  0xF6A0
+#define reg_lnk2ofdm_data_7_0_pos 0
+#define reg_lnk2ofdm_data_7_0_len 8
+#define reg_lnk2ofdm_data_7_0_lsb 0
+#define xd_p_reg_lnk2ofdm_data_15_8 (*(volatile byte xdata *) 0xF6A1)
+#define    p_reg_lnk2ofdm_data_15_8 0xF6A1
+#define reg_lnk2ofdm_data_15_8_pos 0
+#define reg_lnk2ofdm_data_15_8_len 8
+#define reg_lnk2ofdm_data_15_8_lsb 8
+#define xd_p_reg_lnk2ofdm_data_23_16    (*(volatile byte xdata *) 0xF6A2)
+#define    p_reg_lnk2ofdm_data_23_16    0xF6A2
+#define reg_lnk2ofdm_data_23_16_pos 0
+#define reg_lnk2ofdm_data_23_16_len 8
+#define reg_lnk2ofdm_data_23_16_lsb 16
+#define xd_p_reg_lnk2ofdm_data_31_24    (*(volatile byte xdata *) 0xF6A3)
+#define    p_reg_lnk2ofdm_data_31_24    0xF6A3
+#define reg_lnk2ofdm_data_31_24_pos 0
+#define reg_lnk2ofdm_data_31_24_len 8
+#define reg_lnk2ofdm_data_31_24_lsb 24
+#define xd_p_reg_lnk2ofdm_data_39_32    (*(volatile byte xdata *) 0xF6A4)
+#define    p_reg_lnk2ofdm_data_39_32    0xF6A4
+#define reg_lnk2ofdm_data_39_32_pos 0
+#define reg_lnk2ofdm_data_39_32_len 8
+#define reg_lnk2ofdm_data_39_32_lsb 32
+#define xd_p_reg_lnk2ofdm_data_47_40    (*(volatile byte xdata *) 0xF6A5)
+#define    p_reg_lnk2ofdm_data_47_40    0xF6A5
+#define reg_lnk2ofdm_data_47_40_pos 0
+#define reg_lnk2ofdm_data_47_40_len 8
+#define reg_lnk2ofdm_data_47_40_lsb 40
+#define xd_p_reg_lnk2ofdm_data_55_48    (*(volatile byte xdata *) 0xF6A6)
+#define    p_reg_lnk2ofdm_data_55_48    0xF6A6
+#define reg_lnk2ofdm_data_55_48_pos 0
+#define reg_lnk2ofdm_data_55_48_len 8
+#define reg_lnk2ofdm_data_55_48_lsb 48
+#define xd_p_reg_lnk2ofdm_data_63_56    (*(volatile byte xdata *) 0xF6A7)
+#define    p_reg_lnk2ofdm_data_63_56    0xF6A7
+#define reg_lnk2ofdm_data_63_56_pos 0
+#define reg_lnk2ofdm_data_63_56_len 8
+#define reg_lnk2ofdm_data_63_56_lsb 56
+#define xd_p_reg_ofdmtolnk_data_7_0 (*(volatile byte xdata *) 0xF6A8)
+#define    p_reg_ofdmtolnk_data_7_0 0xF6A8
+#define reg_ofdmtolnk_data_7_0_pos 0
+#define reg_ofdmtolnk_data_7_0_len 8
+#define reg_ofdmtolnk_data_7_0_lsb 0
+#define xd_p_reg_ofdmtolnk_data_15_8    (*(volatile byte xdata *) 0xF6A9)
+#define    p_reg_ofdmtolnk_data_15_8    0xF6A9
+#define reg_ofdmtolnk_data_15_8_pos 0
+#define reg_ofdmtolnk_data_15_8_len 8
+#define reg_ofdmtolnk_data_15_8_lsb 8
+#define xd_p_reg_ofdmtolnk_data_23_16   (*(volatile byte xdata *) 0xF6AA)
+#define    p_reg_ofdmtolnk_data_23_16   0xF6AA
+#define reg_ofdmtolnk_data_23_16_pos 0
+#define reg_ofdmtolnk_data_23_16_len 8
+#define reg_ofdmtolnk_data_23_16_lsb 16
+#define xd_p_reg_ofdmtolnk_data_31_24   (*(volatile byte xdata *) 0xF6AB)
+#define    p_reg_ofdmtolnk_data_31_24   0xF6AB
+#define reg_ofdmtolnk_data_31_24_pos 0
+#define reg_ofdmtolnk_data_31_24_len 8
+#define reg_ofdmtolnk_data_31_24_lsb 24
+#define xd_p_reg_ofdmtolnk_data_39_32   (*(volatile byte xdata *) 0xF6AC)
+#define    p_reg_ofdmtolnk_data_39_32   0xF6AC
+#define reg_ofdmtolnk_data_39_32_pos 0
+#define reg_ofdmtolnk_data_39_32_len 8
+#define reg_ofdmtolnk_data_39_32_lsb 32
+#define xd_p_reg_ofdmtolnk_data_47_40   (*(volatile byte xdata *) 0xF6AD)
+#define    p_reg_ofdmtolnk_data_47_40   0xF6AD
+#define reg_ofdmtolnk_data_47_40_pos 0
+#define reg_ofdmtolnk_data_47_40_len 8
+#define reg_ofdmtolnk_data_47_40_lsb 40
+#define xd_p_reg_ofdmtolnk_data_55_48   (*(volatile byte xdata *) 0xF6AE)
+#define    p_reg_ofdmtolnk_data_55_48   0xF6AE
+#define reg_ofdmtolnk_data_55_48_pos 0
+#define reg_ofdmtolnk_data_55_48_len 8
+#define reg_ofdmtolnk_data_55_48_lsb 48
+#define xd_p_reg_ofdmtolnk_data_63_56   (*(volatile byte xdata *) 0xF6AF)
+#define    p_reg_ofdmtolnk_data_63_56   0xF6AF
+#define reg_ofdmtolnk_data_63_56_pos 0
+#define reg_ofdmtolnk_data_63_56_len 8
+#define reg_ofdmtolnk_data_63_56_lsb 56
+#define xd_p_reg_mon51_flag (*(volatile byte xdata *) 0xF6B0)
+#define    p_reg_mon51_flag 0xF6B0
+#define reg_mon51_flag_pos 0
+#define reg_mon51_flag_len 1
+#define reg_mon51_flag_lsb 0
+#define xd_p_reg_force_mon51    (*(volatile byte xdata *) 0xF6B1)
+#define    p_reg_force_mon51    0xF6B1
+#define reg_force_mon51_pos 0
+#define reg_force_mon51_len 1
+#define reg_force_mon51_lsb 0
+#define xd_p_reg_which_cpu  (*(volatile byte xdata *) 0xF6B2)
+#define    p_reg_which_cpu  0xF6B2
+#define reg_which_cpu_pos 0
+#define reg_which_cpu_len 1
+#define reg_which_cpu_lsb 0
+#define xd_p_reg_program_ofdm_code_ready    (*(volatile byte xdata *) 0xF6B3)
+#define    p_reg_program_ofdm_code_ready    0xF6B3
+#define reg_program_ofdm_code_ready_pos 0
+#define reg_program_ofdm_code_ready_len 1
+#define reg_program_ofdm_code_ready_lsb 0
+#define xd_p_reg_link_wr_ofdm_en    (*(volatile byte xdata *) 0xF6B3)
+#define    p_reg_link_wr_ofdm_en    0xF6B3
+#define reg_link_wr_ofdm_en_pos 1
+#define reg_link_wr_ofdm_en_len 1
+#define reg_link_wr_ofdm_en_lsb 0
+#define xd_p_reg_i2c_mode   (*(volatile byte xdata *) 0xF6B4)
+#define    p_reg_i2c_mode   0xF6B4
+#define reg_i2c_mode_pos 0
+#define reg_i2c_mode_len 1
+#define reg_i2c_mode_lsb 0
+#define xd_p_reg_sw_reset_sdio  (*(volatile byte xdata *) 0xF6B4)
+#define    p_reg_sw_reset_sdio  0xF6B4
+#define reg_sw_reset_sdio_pos 1
+#define reg_sw_reset_sdio_len 1
+#define reg_sw_reset_sdio_lsb 0
+#define xd_p_reg_debug_mpefec_sel   (*(volatile byte xdata *) 0xF6B4)
+#define    p_reg_debug_mpefec_sel   0xF6B4
+#define reg_debug_mpefec_sel_pos 2
+#define reg_debug_mpefec_sel_len 1
+#define reg_debug_mpefec_sel_lsb 0
+#define xd_p_reg_lnk_dynamic_clk    (*(volatile byte xdata *) 0xF6B4)
+#define    p_reg_lnk_dynamic_clk    0xF6B4
+#define reg_lnk_dynamic_clk_pos 3
+#define reg_lnk_dynamic_clk_len 1
+#define reg_lnk_dynamic_clk_lsb 0
+#define xd_p_reg_lnk_free_clk   (*(volatile byte xdata *) 0xF6B4)
+#define    p_reg_lnk_free_clk   0xF6B4
+#define reg_lnk_free_clk_pos 4
+#define reg_lnk_free_clk_len 1
+#define reg_lnk_free_clk_lsb 0
+#define xd_p_reg_i2c_sample_rate_up_en  (*(volatile byte xdata *) 0xF6B4)
+#define    p_reg_i2c_sample_rate_up_en  0xF6B4
+#define reg_i2c_sample_rate_up_en_pos 5
+#define reg_i2c_sample_rate_up_en_len 1
+#define reg_i2c_sample_rate_up_en_lsb 0
+#define xd_p_reg_i2c_start_patch    (*(volatile byte xdata *) 0xF6B4)
+#define    p_reg_i2c_start_patch    0xF6B4
+#define reg_i2c_start_patch_pos 6
+#define reg_i2c_start_patch_len 1
+#define reg_i2c_start_patch_lsb 0
+#define xd_p_reg_link_i2cs_msb  (*(volatile byte xdata *) 0xF6B5)
+#define    p_reg_link_i2cs_msb  0xF6B5
+#define reg_link_i2cs_msb_pos 1
+#define reg_link_i2cs_msb_len 1
+#define reg_link_i2cs_msb_lsb 0
+#define xd_p_reg_link_ofsm_dbg_en   (*(volatile byte xdata *) 0xF6B5)
+#define    p_reg_link_ofsm_dbg_en   0xF6B5
+#define reg_link_ofsm_dbg_en_pos 4
+#define reg_link_ofsm_dbg_en_len 1
+#define reg_link_ofsm_dbg_en_lsb 0
+#define xd_p_reg_link_i2c_dbg_sel   (*(volatile byte xdata *) 0xF6B5)
+#define    p_reg_link_i2c_dbg_sel   0xF6B5
+#define reg_link_i2c_dbg_sel_pos 5
+#define reg_link_i2c_dbg_sel_len 1
+#define reg_link_i2c_dbg_sel_lsb 0
+#define xd_p_reg_fast_slow_train    (*(volatile byte xdata *) 0xF6DD)
+#define    p_reg_fast_slow_train    0xF6DD
+#define xd_p_reg_lnk2ofdm_int   (*(volatile byte xdata *) 0xF6DE)
+#define    p_reg_lnk2ofdm_int   0xF6DE
+#define reg_lnk2ofdm_int_pos 0
+#define reg_lnk2ofdm_int_len 1
+#define reg_lnk2ofdm_int_lsb 0
+#define xd_p_reg_ofdm2lnk_int   (*(volatile byte xdata *) 0xF6DF)
+#define    p_reg_ofdm2lnk_int   0xF6DF
+#define reg_ofdm2lnk_int_pos 0
+#define reg_ofdm2lnk_int_len 1
+#define reg_ofdm2lnk_int_lsb 0
+#define xd_p_reg_load_ofdm_reg  (*(volatile byte xdata *) 0xF6E4)
+#define    p_reg_load_ofdm_reg  0xF6E4
+#define xd_p_link_ofsm_cmd_reg  (*(volatile byte xdata *) 0xF6EA)
+#define    p_link_ofsm_cmd_reg  0xF6EA
+#define link_ofsm_cmd_reg_pos 0
+#define link_ofsm_cmd_reg_len 8
+#define link_ofsm_cmd_reg_lsb 0
+#define xd_p_link_ofsm_addr_reg_h   (*(volatile byte xdata *) 0xF6EB)
+#define    p_link_ofsm_addr_reg_h   0xF6EB
+#define link_ofsm_addr_reg_h_pos 0
+#define link_ofsm_addr_reg_h_len 8
+#define link_ofsm_addr_reg_h_lsb 0
+#define xd_p_link_ofsm_addr_reg_l   (*(volatile byte xdata *) 0xF6EC)
+#define    p_link_ofsm_addr_reg_l   0xF6EC
+#define link_ofsm_addr_reg_l_pos 0
+#define link_ofsm_addr_reg_l_len 8
+#define link_ofsm_addr_reg_l_lsb 0
+#define xd_p_link_ofsm_data_reg_0   (*(volatile byte xdata *) 0xF6ED)
+#define    p_link_ofsm_data_reg_0   0xF6ED
+#define link_ofsm_data_reg_0_pos 0
+#define link_ofsm_data_reg_0_len 8
+#define link_ofsm_data_reg_0_lsb 0
+#define xd_p_link_ofsm_data_reg_1   (*(volatile byte xdata *) 0xF6EE)
+#define    p_link_ofsm_data_reg_1   0xF6EE
+#define link_ofsm_data_reg_1_pos 0
+#define link_ofsm_data_reg_1_len 8
+#define link_ofsm_data_reg_1_lsb 0
+#define xd_p_link_ofsm_data_reg_2   (*(volatile byte xdata *) 0xF6EF)
+#define    p_link_ofsm_data_reg_2   0xF6EF
+#define link_ofsm_data_reg_2_pos 0
+#define link_ofsm_data_reg_2_len 8
+#define link_ofsm_data_reg_2_lsb 0
+#define xd_p_link_ofsm_data_reg_3   (*(volatile byte xdata *) 0xF6F0)
+#define    p_link_ofsm_data_reg_3   0xF6F0
+#define link_ofsm_data_reg_3_pos 0
+#define link_ofsm_data_reg_3_len 8
+#define link_ofsm_data_reg_3_lsb 0
+#define xd_p_link_ofsm_data_reg_4   (*(volatile byte xdata *) 0xF6F1)
+#define    p_link_ofsm_data_reg_4   0xF6F1
+#define link_ofsm_data_reg_4_pos 0
+#define link_ofsm_data_reg_4_len 8
+#define link_ofsm_data_reg_4_lsb 0
+#define xd_p_link_ofsm_data_reg_5   (*(volatile byte xdata *) 0xF6F2)
+#define    p_link_ofsm_data_reg_5   0xF6F2
+#define link_ofsm_data_reg_5_pos 0
+#define link_ofsm_data_reg_5_len 8
+#define link_ofsm_data_reg_5_lsb 0
+#define xd_p_link_ofsm_data_reg_6   (*(volatile byte xdata *) 0xF6F3)
+#define    p_link_ofsm_data_reg_6   0xF6F3
+#define link_ofsm_data_reg_6_pos 0
+#define link_ofsm_data_reg_6_len 8
+#define link_ofsm_data_reg_6_lsb 0
+#define xd_p_link_ofsm_data_reg_7   (*(volatile byte xdata *) 0xF6F4)
+#define    p_link_ofsm_data_reg_7   0xF6F4
+#define link_ofsm_data_reg_7_pos 0
+#define link_ofsm_data_reg_7_len 8
+#define link_ofsm_data_reg_7_lsb 0
+#define xd_p_link_ofsm_data_reg_8   (*(volatile byte xdata *) 0xF6F5)
+#define    p_link_ofsm_data_reg_8   0xF6F5
+#define link_ofsm_data_reg_8_pos 0
+#define link_ofsm_data_reg_8_len 8
+#define link_ofsm_data_reg_8_lsb 0
+#define xd_p_link_ofsm_data_reg_9   (*(volatile byte xdata *) 0xF6F6)
+#define    p_link_ofsm_data_reg_9   0xF6F6
+#define link_ofsm_data_reg_9_pos 0
+#define link_ofsm_data_reg_9_len 8
+#define link_ofsm_data_reg_9_lsb 0
+#define xd_p_link_ofsm_data_reg_10  (*(volatile byte xdata *) 0xF6F7)
+#define    p_link_ofsm_data_reg_10  0xF6F7
+#define link_ofsm_data_reg_10_pos 0
+#define link_ofsm_data_reg_10_len 8
+#define link_ofsm_data_reg_10_lsb 0
+#define xd_p_link_ofsm_data_reg_11  (*(volatile byte xdata *) 0xF6F8)
+#define    p_link_ofsm_data_reg_11  0xF6F8
+#define link_ofsm_data_reg_11_pos 0
+#define link_ofsm_data_reg_11_len 8
+#define link_ofsm_data_reg_11_lsb 0
+#define xd_p_link_ofsm_data_reg_12  (*(volatile byte xdata *) 0xF6F9)
+#define    p_link_ofsm_data_reg_12  0xF6F9
+#define link_ofsm_data_reg_12_pos 0
+#define link_ofsm_data_reg_12_len 8
+#define link_ofsm_data_reg_12_lsb 0
+#define xd_p_link_ofsm_data_reg_13  (*(volatile byte xdata *) 0xF6FA)
+#define    p_link_ofsm_data_reg_13  0xF6FA
+#define link_ofsm_data_reg_13_pos 0
+#define link_ofsm_data_reg_13_len 8
+#define link_ofsm_data_reg_13_lsb 0
+#define xd_p_link_ofsm_data_reg_14  (*(volatile byte xdata *) 0xF6FB)
+#define    p_link_ofsm_data_reg_14  0xF6FB
+#define link_ofsm_data_reg_14_pos 0
+#define link_ofsm_data_reg_14_len 8
+#define link_ofsm_data_reg_14_lsb 0
+#define xd_p_link_ofsm_data_reg_15  (*(volatile byte xdata *) 0xF6FC)
+#define    p_link_ofsm_data_reg_15  0xF6FC
+#define link_ofsm_data_reg_15_pos 0
+#define link_ofsm_data_reg_15_len 8
+#define link_ofsm_data_reg_15_lsb 0
+#define xd_p_reg_debug_mux  (*(volatile byte xdata *) 0xF6FE)
+#define    p_reg_debug_mux  0xF6FE
+#define reg_debug_mux_pos 3
+#define reg_debug_mux_len 1
+#define reg_debug_mux_lsb 0
+#define xd_p_reg_top_gpioon0    (*(volatile byte xdata *) 0xF6FF)
+#define    p_reg_top_gpioon0    0xF6FF
+#define reg_top_gpioon0_pos 0
+#define reg_top_gpioon0_len 1
+#define reg_top_gpioon0_lsb 0
+#define xd_p_reg_p_dmb_phy_is_dvb   (*(volatile byte xdata *) 0xDC31)
+#define    p_reg_p_dmb_phy_is_dvb   0xDC31
+#define reg_p_dmb_phy_is_dvb_pos 0
+#define reg_p_dmb_phy_is_dvb_len 1
+#define reg_p_dmb_phy_is_dvb_lsb 0
+#define xd_p_reg_p_dmb_xt_reset (*(volatile byte xdata *) 0xDC32)
+#define    p_reg_p_dmb_xt_reset 0xDC32
+#define reg_p_dmb_xt_reset_pos 0
+#define reg_p_dmb_xt_reset_len 1
+#define reg_p_dmb_xt_reset_lsb 0
+#define xd_p_reg_p_dmb_sw_reset (*(volatile byte xdata *) 0xDC33)
+#define    p_reg_p_dmb_sw_reset 0xDC33
+#define reg_p_dmb_sw_reset_pos 0
+#define reg_p_dmb_sw_reset_len 1
+#define reg_p_dmb_sw_reset_lsb 0
diff --git a/drivers/media/dvb/dvb-usb/a867_standard.c b/drivers/media/dvb/dvb-usb/a867_standard.c
new file mode 100644
index 0000000..8b4f4b3
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_standard.c
@@ -0,0 +1,4668 @@
+#include "a867_standard.h"
+//#include <math.h>
+#include "a867_cmd.h"
+#include "a867_user.h"
+#include "a867_af903x.h"
+
+// turn on/off debug in this file
+#define DEBUG_STANDARD	0
+
+#if !DEBUG_STANDARD
+	#undef deb_info
+	#define deb_info(fmt, args...) do {} while(0)
+#endif
+
+#include "a867_firmware.h"
+
+#define Standard_MAX_BIT                8
+#define Standard_MAX_CLOCK              12
+#define Standard_MAX_BAND               3
+
+
+const Byte Standard_bitMask[Standard_MAX_BIT] = {
+    0x01, 0x03, 0x07, 0x0F, 0x1F, 0x3F, 0x7F, 0xFF
+};
+
+const ClockTable Standard_clockTable[Standard_MAX_CLOCK] =
+{
+    {   20480,      20480000    },      /** FPGA     */
+    {   16384,      20480000    },      /** 16.38MHz */
+    {   20480,      20480000    },      /** 20.48MHz */
+    {   36000,      20250000    },      /** 36.00MHz */
+    {   30000,      20156250    },      /** 30.00MHz */
+    {   26000,      20583333    },      /** 26.00MHz */
+    {   28000,      20416667    },      /** 28.00MHz */
+    {   32000,      20500000    },      /** 32.00MHz */
+    {   34000,      20187500    },      /** 34.00MHz */
+    {   24000,      20500000    },      /** 24.00MHz */
+    {   22000,      20625000    },      /** 22.00MHz */
+    {   12000,      20250000    }       /** 12.00MHz */
+};
+
+const BandTable Standard_bandTable[Standard_MAX_BAND] =
+{
+    {    174000,     230000     },      /** VHF    */
+    {    350000,     900000     },      /** UHF    */
+    {   1670000,    1680000     }       /** L-BAND */
+};
+
+#if User_USE_DRIVER
+Dword Standard_getDriver (
+    IN  Demodulator*    demodulator,
+    OUT Handle*         handle
+) {
+    Dword error = Error_NO_ERROR;
+    TCHAR registry1[100] = TEXT("\\Drivers\\SDCARD\\ClientDrivers\\Custom\\MANF-0296-CARDID-5347-FUNC-1");
+    TCHAR registry2[100] = TEXT("\\Drivers\\SDCARD\\ClientDrivers\\Custom\\MANF-03BE-CARDID-0001-FUNC-1");
+    TCHAR name[256];
+    TCHAR shortBuffer[32];
+    DWORD len = 16;
+    DWORD i;
+    HKEY hKey, hSubKey;
+    DWORD size;
+
+    /** Open the HKLM\Drivers\Active key in registry */
+    if (RegOpenKeyEx(HKEY_LOCAL_MACHINE, TEXT("Drivers\\Active"), 0, 0, &hKey) == ERROR_SUCCESS) {
+        /** Get subkeys count */
+        if (RegQueryInfoKey(hKey, NULL, NULL, NULL, &i, NULL, NULL, NULL, NULL, NULL, NULL, NULL) == ERROR_SUCCESS) {
+            /** Browse subkeys in reverse order (pluggable cards are not at the beginning of the list !) */
+            while (i) {
+                i--;
+                /** Select the subkey */
+                size = sizeof(shortBuffer);
+                if (RegEnumKeyEx(hKey, i, shortBuffer, &size, NULL, NULL, NULL, NULL) == ERROR_SUCCESS) {
+                    /** Open the subkey */
+                    shortBuffer[sizeof(shortBuffer)-1] = '\0';
+                    _stprintf(name, TEXT("Drivers\\Active\\%s"), shortBuffer);
+                    if (RegOpenKeyEx(HKEY_LOCAL_MACHINE, name, 0, 0, &hSubKey) == ERROR_SUCCESS) {
+                        size = sizeof(name);
+                        if (RegQueryValueEx(hSubKey, TEXT("Key"), NULL, NULL, (LPBYTE) name, &size) == ERROR_SUCCESS) {
+                            if ((_tcsncmp(name, registry1, _tcsclen(registry1)) == 0) || (_tcsncmp(name, registry2, _tcsclen(registry2)) == 0)) {
+                                /** This is the good PnPID, now get the serial com in the "Name" value */
+                                size = len;
+                                if (RegQueryValueEx(hSubKey, TEXT("Name"), NULL, NULL, (LPBYTE) name, &size) == ERROR_SUCCESS) {
+                                    /** Found ! */
+                                    RegCloseKey(hSubKey);
+                                    RegCloseKey(hKey);
+                                    /** OK */
+                                    goto exit;
+                                }
+                            }
+                        }
+
+                    /** Close the subkey */
+                    RegCloseKey(hSubKey);
+                    }
+                }
+            }
+        }
+    }
+    /** Close the key */
+    RegCloseKey(hKey);
+
+exit :
+    *handle = CreateFile (name, GENERIC_READ | GENERIC_WRITE, 0, NULL, OPEN_EXISTING, 0, NULL);
+
+    return (error);
+}
+#endif
+
+
+Dword Standard_writeRegister (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            value
+) {
+    Dword ret;
+//    deb_info("Enter %s -\n", __FUNCTION__);
+    ret = (Standard_writeRegisters (demodulator, chip, processor, registerAddress, 1, &value));
+    if(ret) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, ret);
+    }
+    return ret;
+		  
+}
+
+
+Dword Standard_writeRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    WriteRegistersRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        request.chip = chip;
+        request.processor = processor;
+        request.registerAddress = registerAddress;
+        request.bufferLength = bufferLength;
+        User_memoryCopy (demodulator, request.buffer, buffer, bufferLength);
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_WRITEREGISTERS,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    Byte registerAddressLength;
+    Ganymede* ganymede;
+
+//    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    if (processor == Processor_LINK) {
+        if (registerAddress > 0x000000FF) {
+            registerAddressLength = 2;
+        } else {
+            registerAddressLength = 1;
+        }
+    } else {
+            registerAddressLength = 2;
+    }
+    if (ganymede->cmdDescription->writeRegisters != NULL) {
+        error = ganymede->cmdDescription->writeRegisters (demodulator, chip, processor, registerAddress, registerAddressLength, bufferLength, buffer);
+    }
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_writeScatterRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Byte            valueSetsLength,
+    IN  ValueSet*       valueSets
+) {
+    Dword error = Error_NO_ERROR;
+    Byte valueSetsAddressLength;
+    Ganymede* ganymede;
+
+//    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    if (processor == Processor_LINK) {
+        valueSetsAddressLength = 2;
+    } else {
+        valueSetsAddressLength = 2;
+    }
+    if (ganymede->cmdDescription->writeScatterRegisters != NULL) {
+        error = ganymede->cmdDescription->writeScatterRegisters (demodulator, chip, processor, valueSetsAddressLength, valueSetsLength, valueSets);
+    }
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_writeTunerRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Word            registerAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+) {
+    Dword error = Error_NO_ERROR;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->cmdDescription->writeTunerRegisters != NULL) {
+        error = ganymede->cmdDescription->writeTunerRegisters (demodulator, chip, ganymede->tunerDescription->tunerAddress, registerAddress, ganymede->tunerDescription->registerAddressLength, bufferLength, buffer);
+    }
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_writeGenericRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            interfaceIndex,
+    IN  Byte            slaveAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+) {
+    Byte writeBuffer[256];
+    Byte i;
+    Ganymede* ganymede;
+    Dword error;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    writeBuffer[0] = bufferLength;
+    writeBuffer[1] = interfaceIndex;
+    writeBuffer[2] = slaveAddress;
+
+    for (i = 0; i < bufferLength; i++) {
+        writeBuffer[3 + i] = buffer[i];
+    }
+    error = (Standard_sendCommand (demodulator, Command_GENERIC_WRITE, chip, Processor_LINK, bufferLength + 3, writeBuffer, 0, NULL));
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return error;
+}
+
+
+Dword Standard_writeEepromValues (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Word            registerAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    WriteEepromValuesRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        request.chip = chip;
+        request.registerAddress = registerAddress;
+        request.bufferLength = bufferLength;
+        User_memoryCopy (demodulator, request.buffer, buffer, bufferLength);
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_WRITEEEPROMVALUES,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    Byte eepromAddress;
+    Byte registerAddressLength;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    /** Read EEPROM address. */
+    /*error = ganymede->cmdDescription.readRegisters (demodulator, chip, Processor_LINK, 0xBFF0, 1, &eepromAddress);
+    if (error) goto exit;
+    */
+    eepromAddress = 0x01;
+
+    /** Read EEPROM valid length of register. */
+    /*error = ganymede->cmdDescription.readRegisters (demodulator, chip, Processor_LINK, 0xBFF1, 1, &registerAddressLength);
+    if (error) goto exit;
+    */
+    registerAddressLength = 0x01;
+
+    if (ganymede->cmdDescription->writeEepromValues != NULL) {
+        error = ganymede->cmdDescription->writeEepromValues (demodulator, chip, eepromAddress, registerAddress, registerAddressLength, bufferLength, buffer);
+    }
+
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_writeRegisterBits (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            position,
+    IN  Byte            length,
+    IN  Byte            value
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    WriteRegisterBitsRequest request;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        request.chip = chip;
+        request.processor = processor;
+        request.registerAddress = registerAddress;
+        request.position = position;
+        request.length = length;
+        request.value = value;
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_WRITEREGISTERBITS,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    Byte registerAddressLength;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (processor == Processor_LINK) {
+        if (registerAddress > 0x000000FF) {
+            registerAddressLength = 2;
+        } else {
+            registerAddressLength = 1;
+        }
+    } else {
+        registerAddressLength = 2;
+    }
+    if (length == 8) {
+        if (ganymede->cmdDescription->writeRegisters != NULL) {
+            error = ganymede->cmdDescription->writeRegisters (demodulator, chip, processor, registerAddress, registerAddressLength, 1, &value);
+        }
+    } else {
+        if (ganymede->cmdDescription->modifyRegister != NULL) {
+            error = ganymede->cmdDescription->modifyRegister (demodulator, chip, processor, registerAddress, registerAddressLength, position, length, value);
+        }
+    }
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_readRegister (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    OUT Byte*           value
+) {
+    Dword error;
+//    deb_info("Enter %s -\n", __FUNCTION__);
+
+    error = (Standard_readRegisters (demodulator, chip, processor, registerAddress, 1, value));
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return error;
+}
+
+
+Dword Standard_readRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            bufferLength,
+    OUT Byte*           buffer
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    ReadRegistersRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        request.chip = chip;
+        request.processor = processor;
+        request.registerAddress = registerAddress;
+        request.bufferLength = bufferLength;
+        request.buffer = buffer;
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_READREGISTERS,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    Byte registerAddressLength;
+    Ganymede* ganymede;
+
+//    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    if (processor == Processor_LINK) {
+        if (registerAddress > 0x000000FF) {
+            registerAddressLength = 2;
+        } else {
+            registerAddressLength = 1;
+        }
+    } else {
+        registerAddressLength = 2;
+    }
+    if (ganymede->cmdDescription->readRegisters != NULL) {
+        error = ganymede->cmdDescription->readRegisters (demodulator, chip, processor, registerAddress, registerAddressLength, bufferLength, buffer);
+    }
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_readScatterRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Byte            valueSetsLength,
+    OUT ValueSet*       valueSets
+) {
+    Dword error = Error_NO_ERROR;
+    Byte valueSetsAddressLength;
+    Ganymede* ganymede;
+
+//    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    if (processor == Processor_LINK) {
+        valueSetsAddressLength = 2;
+    } else {
+        valueSetsAddressLength = 2;
+    }
+
+    if (ganymede->cmdDescription->readScatterRegisters != NULL) {
+        error = ganymede->cmdDescription->readScatterRegisters (demodulator, chip, processor, valueSetsAddressLength, valueSetsLength, valueSets);
+    }
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_readTunerRegisters (
+	IN  Demodulator*    demodulator,
+	IN  Byte            chip,
+	IN  Word            registerAddress,
+	IN  Byte            bufferLength,
+	IN  Byte*           buffer
+) {
+	Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+	DWORD number;
+	BOOL result;
+	ReadTunerRegistersRequest request;
+	Ganymede* ganymede;
+
+	ganymede = (Ganymede*) demodulator;
+
+	if (ganymede->driver != NULL) {
+		request.chip = chip;
+		request.registerAddress = registerAddress;
+		request.bufferLength = bufferLength;
+		request.buffer = buffer;
+		result = DeviceIoControl (
+					ganymede->driver,
+					IOCTL_AFA_DEMOD_READTUNERREGISTERS,
+					&request,
+					sizeof (request),
+					NULL,
+					0,
+					&number,
+					NULL
+		);
+		error = request.error;
+	} else {
+		error = Error_DRIVER_INVALID;
+	}
+#else
+	Ganymede* ganymede;
+
+	deb_info("Enter %s -\n", __FUNCTION__);
+	ganymede = (Ganymede*) demodulator;
+
+	if (ganymede->cmdDescription->readTunerRegisters != NULL) {
+
+	if (registerAddress == 0xffff && ganymede->tunerDescription->registerAddressLength == 1)
+	{
+		error = ganymede->cmdDescription->readTunerRegisters (demodulator, chip, 
+		ganymede->tunerDescription->tunerAddress, registerAddress, 0, bufferLength, buffer);
+	}
+	else
+	{
+		error = ganymede->cmdDescription->readTunerRegisters (demodulator, chip, 
+		ganymede->tunerDescription->tunerAddress, registerAddress, 
+		ganymede->tunerDescription->registerAddressLength, bufferLength, buffer);
+	}
+    }
+#endif
+
+	if(error) 
+	{
+		deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+	}
+	return (error);
+}
+
+
+Dword Standard_readGenericRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            interfaceIndex,
+    IN  Byte            slaveAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+) {
+    Byte writeBuffer[3];
+    Ganymede* ganymede;
+    Dword error;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    writeBuffer[0] = bufferLength;
+    writeBuffer[1] = interfaceIndex;
+    writeBuffer[2] = slaveAddress;
+
+    error = (Standard_sendCommand (demodulator, Command_GENERIC_READ, chip, Processor_LINK, 3, writeBuffer, bufferLength, buffer));
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return error;
+}
+
+
+Dword Standard_readEepromValues (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Word            registerAddress,
+    IN  Byte            bufferLength,
+    OUT Byte*           buffer
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    ReadEepromValuesRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        request.chip = chip;
+        request.registerAddress = registerAddress;
+        request.bufferLength = bufferLength;
+        request.buffer = buffer;
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_READEEPROMVALUES,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    Byte eepromAddress;
+    Byte registerAddressLength;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    /** Read EEPROM address. */
+    /*error = ganymede->cmdDescription.readRegisters (demodulator, chip, Processor_LINK, 0xBFF0, 1, &eepromAddress);
+    if (error) goto exit;
+    */
+    eepromAddress = 0x01;
+
+    /** Read EEPROM valid length of register. */
+    /*error = ganymede->cmdDescription.readRegisters (demodulator, chip, Processor_LINK, 0xBFF1, 1, &registerAddressLength);
+    if (error) goto exit;
+    */
+    registerAddressLength = 0x01;
+
+    if (ganymede->cmdDescription->readEepromValues != NULL) {
+        error = ganymede->cmdDescription->readEepromValues (demodulator, chip, eepromAddress, registerAddress, registerAddressLength, bufferLength, buffer);
+    }
+
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_readRegisterBits (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            position,
+    IN  Byte            length,
+    OUT Byte*           value
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    ReadRegisterBitsRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        request.chip = chip;
+        request.processor = processor;
+        request.registerAddress = registerAddress;
+        request.position = position;
+        request.length = length;
+        request.value = value;
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_READREGISTERBITS,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    Byte temp = 0;
+    Byte registerAddressLength;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    if (processor == Processor_LINK) {
+        if (registerAddress > 0x000000FF) {
+            registerAddressLength = 2;
+        } else {
+            registerAddressLength = 1;
+        }
+    } else {
+        registerAddressLength = 2;
+    }
+    if (ganymede->cmdDescription->readRegisters != NULL) {
+        error = ganymede->cmdDescription->readRegisters (demodulator, chip, processor, registerAddress, registerAddressLength, 1, &temp);
+    }
+    if (error) goto exit;
+
+    if (length == 8) {
+        *value = temp;
+    } else {
+        temp = REG_GET (temp, position, length);
+        *value = temp;
+    }
+
+#endif
+
+exit :
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_sendCommand (
+    IN  Demodulator*    demodulator,
+    OUT Word            command,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           writeBufferLength,
+    IN  Byte*           writeBuffer,
+    IN  Dword           readBufferLength,
+    OUT Byte*           readBuffer
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+#else
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->cmdDescription->sendCommand != NULL) {
+        error = ganymede->cmdDescription->sendCommand (demodulator, command, chip, processor, writeBufferLength, writeBuffer, readBufferLength, readBuffer);
+    }
+#endif
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_getHardwareVersion (
+    IN  Demodulator*    demodulator,
+    OUT Dword*          version
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+#else
+    Byte hwVer0;
+    Byte hwVer1;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    error = Standard_readRegister (demodulator, 0, Processor_OFDM, 0xFFF0, &hwVer0);
+    if (error) goto exit;
+    error = Standard_readRegister (demodulator, 0, Processor_OFDM, 0xFFF1, &hwVer1);
+    if (error) goto exit;
+
+    /** HW Version = HWVer + Top_Ver */
+    *version = (Dword) (hwVer1 << 8) + (Dword) hwVer0;
+
+exit :
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_getFirmwareVersion (
+    IN  Demodulator*    demodulator,
+    IN  Processor       processor,
+    OUT Dword*          version
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    GetFirmwareVersionRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        request.processor = processor;
+        request.version = version;
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_GETFIRMWAREVERSION,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    Byte writeBuffer[1];
+    Byte readBuffer[4];
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    if ((ganymede->busId == Bus_I2M) || (ganymede->busId == Bus_I2U)) {
+        *version = 0xFFFFFFFF;
+        goto exit;
+    }
+
+    writeBuffer[0] = 1;
+    error = Standard_sendCommand (demodulator, Command_QUERYINFO, 0, processor, 1, writeBuffer, 4, readBuffer);
+    if (error) goto exit;
+
+    *version = (Dword) (((Dword) readBuffer[0] << 24) + ((Dword) readBuffer[1] << 16) + ((Dword) readBuffer[2] << 8) + (Dword) readBuffer[3]);
+
+exit :
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_getPostVitBer (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Dword*          postErrorCount,  /** 24 bits */
+    OUT Dword*          postBitCount,    /** 16 bits */
+    OUT Word*           abortCount
+) {
+    Dword error = Error_NO_ERROR;
+    Dword errorCount;
+    Dword bitCount;
+    Byte buffer[7];
+    Word abort;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    *postErrorCount = 0;
+    *postBitCount  = 0;
+
+    error = Standard_readRegisters (demodulator, chip, Processor_OFDM, rsd_abort_packet_cnt_7_0, r_rsd_packet_unit_15_8 - rsd_abort_packet_cnt_7_0 + 1, buffer);
+    if (error) goto exit;
+
+    abort = ((Word) buffer[rsd_abort_packet_cnt_15_8 - rsd_abort_packet_cnt_7_0] << 8) + buffer[rsd_abort_packet_cnt_7_0 - rsd_abort_packet_cnt_7_0];
+    errorCount = ((Dword) buffer[rsd_bit_err_cnt_23_16 - rsd_abort_packet_cnt_7_0] << 16) + ((Dword) buffer[rsd_bit_err_cnt_15_8 - rsd_abort_packet_cnt_7_0] << 8) + buffer[rsd_bit_err_cnt_7_0 - rsd_abort_packet_cnt_7_0];
+    bitCount = ((Dword) buffer[r_rsd_packet_unit_15_8 - rsd_abort_packet_cnt_7_0] << 8) + buffer[r_rsd_packet_unit_7_0 - rsd_abort_packet_cnt_7_0];
+    if (bitCount == 0) {
+        /*error = Error_RSD_PKT_CNT_0;*/
+        *postErrorCount = 1;
+        *postBitCount = 2;
+        *abortCount = 1000;
+        goto exit;
+    }
+
+    *abortCount = abort;
+    bitCount = bitCount - (Dword)abort;
+    if (bitCount == 0) {
+        *postErrorCount = 1;
+        *postBitCount  = 2;
+    } else {
+        *postErrorCount = errorCount - (Dword) abort * 8 * 8;
+        *postBitCount  = bitCount * 204 * 8;
+    }
+
+exit :
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_resetPostVitErrorCount (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip
+) {
+    Dword error = Error_NO_ERROR;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    /** Reset counter for next time we get post Viterbi BER */
+    error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, p_reg_rsd_ber_rdy, reg_rsd_ber_rdy_pos, reg_rsd_ber_rdy_len, 1);
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_wordToInt (
+    IN  Demodulator*    demodulator,
+    short*              value,
+    Word                input
+) {
+    Dword error = Error_NO_ERROR;
+    short volt;
+    //Dword dwUpVoltX100 = 330;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    input = input & 0x03FF;
+
+    if (input >= 512) {
+        volt = (short) input - (short) 0x400ul;
+    } else {
+        volt = (short) input;
+    }
+
+    *value = volt;
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_getRfAgcGain (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Byte*           rfAgc
+) {
+    Dword   error = Error_NO_ERROR;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+#if User_USE_DRIVER
+#else
+    /** get rf_agc_control */
+    error = Standard_readRegisterBits (demodulator, chip, Processor_OFDM, r_reg_aagc_rf_gain, reg_aagc_rf_gain_pos, reg_aagc_rf_gain_len, rfAgc);
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_getIfAgcGain (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Byte*           ifAgc
+) {
+    Dword error = Error_NO_ERROR;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+#if User_USE_DRIVER
+#else
+    /** get if_agc_control */
+    error = Standard_readRegisterBits (demodulator, chip, Processor_OFDM, r_reg_aagc_if_gain, reg_aagc_if_gain_pos, reg_aagc_if_gain_len, ifAgc);
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_getAgcGain (
+    IN  Demodulator*    demodulator,
+    IN  Word            registerHi,
+    IN  Word            registerLo,
+    IN  Byte            position,
+    IN  Byte            length,
+    OUT Word            *value
+) {
+    Dword error = Error_NO_ERROR;
+    Byte temp0;
+    Byte temp1;
+    deb_info("Enter %s -\n", __FUNCTION__);
+
+    error = Standard_readRegister (demodulator, 0, Processor_OFDM, registerLo, &temp0);
+    if (error) goto exit;
+    error = Standard_readRegisterBits (demodulator, 0, Processor_OFDM, registerHi, position, length, &temp1);
+    if (error) goto exit;
+
+    *value = (Word) (temp1 << 8) + (Word) temp0;
+
+exit :
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_setAgcGain (
+    IN  Demodulator*    demodulator,
+    IN  Word            registerHi,
+    IN  Word            registerLo,
+    IN  Byte            position,
+    IN  Byte            length,
+    IN  Word            value
+) {
+    Dword error = Error_NO_ERROR;
+    Byte temp0;
+    Byte temp1;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    temp0 = (Byte) (value & 0x00FF);
+    temp1 = (Byte) ((value & 0x0300) >> 8);
+
+    error = Standard_writeRegister (demodulator, 0, Processor_OFDM, registerLo, temp0);
+    if (error) goto exit;
+    error = Standard_writeRegisterBits (demodulator, 0, Processor_OFDM, registerHi, position, length, temp1);
+
+exit :
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_resetAgc (
+    IN  Demodulator*    demodulator
+) {
+    Dword error = Error_NO_ERROR;
+    //Byte temp = 0;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    error = Standard_writeRegisterBits (demodulator, 0, Processor_OFDM, p_reg_aagc_top_th_dis, reg_aagc_top_th_dis_pos, reg_aagc_top_th_dis_len, 0x00);
+    if (error) goto exit;
+    error = Standard_writeRegisterBits (demodulator, 0, Processor_OFDM, p_reg_aagc_top_reload, reg_aagc_top_reload_pos, reg_aagc_top_reload_len, 0x01);
+    if (error) goto exit;
+    error = Standard_writeRegisterBits (demodulator, 0, Processor_OFDM, p_reg_agc_rst, reg_agc_rst_pos, reg_agc_rst_len, 0x01);
+
+exit :
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_getSignalQuality (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Byte*           quality
+) {
+    Dword error = Error_NO_ERROR;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    error = Standard_readRegister (demodulator, chip, Processor_OFDM, signal_quality, quality);
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_getSignalStrength (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Byte*           strength
+) {
+    Dword error = Error_NO_ERROR;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    error = Standard_readRegister (demodulator, chip, Processor_OFDM, signal_strength, strength);
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_getSignalStrengthDbm (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Long            rfpullUpVolt_X10,     /** RF pull up voltage multiplied by 10 */
+    IN  Long            ifpullUpVolt_X10,     /** IF pull up voltage multiplied by 10 */
+    OUT Long*           strengthDbm           /** DBm                                 */
+)
+{
+    Dword error = Error_NO_ERROR;
+    Byte temp;
+    deb_info("Enter %s -\n", __FUNCTION__);
+
+    if ((rfpullUpVolt_X10 == 0) || (ifpullUpVolt_X10 == 0)) {
+        error = Error_INV_PULLUP_VOLT;
+        goto exit;
+    }
+
+    error = Standard_readRegister (demodulator, chip, Processor_OFDM, est_rf_level_dbm, &temp);
+    if (error) goto exit;
+
+    *strengthDbm = (Long) (temp * -1);
+
+exit :
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_divider (
+    IN  Demodulator*    demodulator,
+    IN  Dword           a,
+    IN  Dword           b,
+    IN  Dword           x
+) {
+    Dword answer = 0;
+    Dword c = 0;
+    Dword i = 0;
+
+    if (a > b) {
+        c = a / b;
+        a = a - c * b;
+    }
+
+    for (i = 0; i < x; i++) {
+        if (a >= b) {
+            answer += 1;
+            a-=b;
+        }
+        a <<= 1;
+        answer <<= 1;
+    }
+
+    answer = (c << (Long) x) + answer;
+
+    return (answer);
+}
+
+
+Dword Standard_computeCrystal (
+    IN  Demodulator*    demodulator,
+    IN  Long            crystalFrequency,   /** Crystal frequency (Hz) */
+    OUT Dword*          crystal
+) {
+    Dword   error = Error_NO_ERROR;
+    deb_info("Enter %s -\n", __FUNCTION__);
+
+    *crystal = (Long) Standard_divider (demodulator, (Dword) crystalFrequency, 1000000ul, 19ul);
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_computeAdc (
+    IN  Demodulator*    demodulator,
+    IN  Long            adcFrequency,       /** ADC frequency (Hz) */
+    OUT Dword*          adc
+)
+{
+    Dword   error = Error_NO_ERROR;
+    deb_info("Enter %s -\n", __FUNCTION__);
+
+    *adc = (Long) Standard_divider (demodulator, (Dword) adcFrequency, 1000000ul, 19ul);
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_computeFcw (
+    IN  Demodulator*    demodulator,
+    IN  Long            adcFrequency,       /** ADC frequency (Hz)    */
+    IN  Long            ifFrequency,        /** IF frequency (Hz)     */
+    IN  Bool            inversion,          /** RF spectrum inversion */
+    OUT Dword*          fcw
+) {
+    Dword error = Error_NO_ERROR;
+    Long ifFreq;
+    Long adcFreq;
+    Long adcFreqHalf;
+    Long adcFreqSample;
+    Long invBfs;
+    Long controlWord;
+    Byte adcMultiplier;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    adcFreq = adcFrequency;
+    ifFreq = ifFrequency;
+    adcFreqHalf = adcFreq / 2;
+
+    if (inversion == True)
+        ifFreq = -1 * ifFreq;
+
+    adcFreqSample = ifFreq;
+
+    if (adcFreqSample >= 0)
+        invBfs = 1;
+    else {
+        invBfs = -1;
+        adcFreqSample = adcFreqSample * -1;
+    }
+
+    while (adcFreqSample > adcFreqHalf)
+        adcFreqSample = adcFreqSample - adcFreq;
+
+    /** Sample, spectrum at positive frequency */
+    if(adcFreqSample >= 0)
+        invBfs = invBfs * -1;
+    else {
+        invBfs = invBfs * 1;
+        adcFreqSample = adcFreqSample * (-1);       /** Absolute value */
+    }
+
+    controlWord = (Long) Standard_divider (demodulator, (Dword) adcFreqSample, (Dword) adcFreq, 23ul);
+
+    if (invBfs == -1) {
+        controlWord *= -1;
+    }
+
+    /** Get ADC multiplier */
+    error = Standard_readRegister (demodulator, 0, Processor_OFDM, adcx2, &adcMultiplier);
+    if (error) goto exit;
+
+    if (adcMultiplier == 1) {
+        controlWord /= 2;
+    }
+
+    *fcw = controlWord & 0x7FFFFF;
+
+exit :
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_selectBandwidth (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Word            bandwidth,          /** KHz              */
+    IN  Dword           adcFrequency        /** Hz, ex: 20480000 */
+) {
+    Dword error = Error_NO_ERROR;
+    Dword coeff1_2048Nu;
+    Dword coeff1_4096Nu;
+    Dword coeff1_8191Nu;
+    Dword coeff1_8192Nu;
+    Dword coeff1_8193Nu;
+    Dword coeff2_2k;
+    Dword coeff2_4k;
+    Dword coeff2_8k;
+    Word bfsfcw_fftindex_ratio;
+    Word fftindex_bfsfcw_ratio;
+
+    Byte temp0;
+    Byte temp1;
+    Byte temp2;
+    Byte temp3;
+    Byte buffer[36];
+    Byte bw;
+    Byte adcMultiplier;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    if (bandwidth == 5000)
+        bw = 3;
+    else if (bandwidth == 6000)
+        bw = 0;
+    else if (bandwidth == 7000)
+        bw = 1;
+    else if (bandwidth == 8000)
+        bw = 2;
+    else {
+        error = Error_INVALID_BW;
+        goto exit;
+    }
+
+    ganymede = (Ganymede*) demodulator;
+
+    error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, g_reg_bw, reg_bw_pos, reg_bw_len, bw);
+    if (error) goto exit;
+
+    /** Program CFOE */
+    if (adcFrequency == 20156250) {
+        if (bandwidth == 5000) {
+            coeff1_2048Nu = 0x02449b5c;
+            coeff1_4096Nu = 0x01224dae;
+            coeff1_8191Nu = 0x00912b60;
+            coeff1_8192Nu = 0x009126d7;
+            coeff1_8193Nu = 0x0091224e;
+            coeff2_2k = 0x01224dae;
+            coeff2_4k = 0x009126d7;
+            coeff2_8k = 0x0048936b;
+            bfsfcw_fftindex_ratio = 0x0387;
+            fftindex_bfsfcw_ratio = 0x0122;
+        } else if (bandwidth == 6000) {
+            coeff1_2048Nu = 0x02b8ba6e;
+            coeff1_4096Nu = 0x015c5d37;
+            coeff1_8191Nu = 0x00ae340d;
+            coeff1_8192Nu = 0x00ae2e9b;
+            coeff1_8193Nu = 0x00ae292a;
+            coeff2_2k = 0x015c5d37;
+            coeff2_4k = 0x00ae2e9b;
+            coeff2_8k = 0x0057174e;
+            bfsfcw_fftindex_ratio = 0x02f1;
+            fftindex_bfsfcw_ratio = 0x015c;
+        } else if (bandwidth == 7000) {
+            coeff1_2048Nu = 0x032cd980;
+            coeff1_4096Nu = 0x01966cc0;
+            coeff1_8191Nu = 0x00cb3cba;
+            coeff1_8192Nu = 0x00cb3660;
+            coeff1_8193Nu = 0x00cb3007;
+            coeff2_2k = 0x01966cc0;
+            coeff2_4k = 0x00cb3660;
+            coeff2_8k = 0x00659b30;
+            bfsfcw_fftindex_ratio = 0x0285;
+            fftindex_bfsfcw_ratio = 0x0196;
+        } else if (bandwidth == 8000) {
+            coeff1_2048Nu = 0x03a0f893;
+            coeff1_4096Nu = 0x01d07c49;
+            coeff1_8191Nu = 0x00e84567;
+            coeff1_8192Nu = 0x00e83e25;
+            coeff1_8193Nu = 0x00e836e3;
+            coeff2_2k = 0x01d07c49;
+            coeff2_4k = 0x00e83e25;
+            coeff2_8k = 0x00741f12;
+            bfsfcw_fftindex_ratio = 0x0234;
+            fftindex_bfsfcw_ratio = 0x01d0;
+        } else {
+            error = Error_INVALID_BW;
+            goto exit;
+        }
+    } else if (adcFrequency == 20187500) {
+        if (bandwidth == 5000) {
+            coeff1_2048Nu = 0x0243b546;
+            coeff1_4096Nu = 0x0121daa3;
+            coeff1_8191Nu = 0x0090f1d9;
+            coeff1_8192Nu = 0x0090ed51;
+            coeff1_8193Nu = 0x0090e8ca;
+            coeff2_2k = 0x0121daa3;
+            coeff2_4k = 0x0090ed51;
+            coeff2_8k = 0x004876a9;
+            bfsfcw_fftindex_ratio = 0x0388;
+            fftindex_bfsfcw_ratio = 0x0122;
+        } else if (bandwidth == 6000) {
+            coeff1_2048Nu = 0x02b7a654;
+            coeff1_4096Nu = 0x015bd32a;
+            coeff1_8191Nu = 0x00adef04;
+            coeff1_8192Nu = 0x00ade995;
+            coeff1_8193Nu = 0x00ade426;
+            coeff2_2k = 0x015bd32a;
+            coeff2_4k = 0x00ade995;
+            coeff2_8k = 0x0056f4ca;
+            bfsfcw_fftindex_ratio = 0x02f2;
+            fftindex_bfsfcw_ratio = 0x015c;
+        } else if (bandwidth == 7000) {
+            coeff1_2048Nu = 0x032b9761;
+            coeff1_4096Nu = 0x0195cbb1;
+            coeff1_8191Nu = 0x00caec30;
+            coeff1_8192Nu = 0x00cae5d8;
+            coeff1_8193Nu = 0x00cadf81;
+            coeff2_2k = 0x0195cbb1;
+            coeff2_4k = 0x00cae5d8;
+            coeff2_8k = 0x006572ec;
+            bfsfcw_fftindex_ratio = 0x0286;
+            fftindex_bfsfcw_ratio = 0x0196;
+        } else if (bandwidth == 8000) {
+            coeff1_2048Nu = 0x039f886f;
+            coeff1_4096Nu = 0x01cfc438;
+            coeff1_8191Nu = 0x00e7e95b;
+            coeff1_8192Nu = 0x00e7e21c;
+            coeff1_8193Nu = 0x00e7dadd;
+            coeff2_2k = 0x01cfc438;
+            coeff2_4k = 0x00e7e21c;
+            coeff2_8k = 0x0073f10e;
+            bfsfcw_fftindex_ratio = 0x0235;
+            fftindex_bfsfcw_ratio = 0x01d0;
+        } else {
+            error = Error_INVALID_BW;
+            goto exit;
+        }
+    } else if (adcFrequency == 20250000) {
+        if (bandwidth == 5000) {
+            coeff1_2048Nu = 0x0241eb3b;
+            coeff1_4096Nu = 0x0120f59e;
+            coeff1_8191Nu = 0x00907f53;
+            coeff1_8192Nu = 0x00907acf;
+            coeff1_8193Nu = 0x0090764b;
+            coeff2_2k = 0x0120f59e;
+            coeff2_4k = 0x00907acf;
+            coeff2_8k = 0x00483d67;
+            bfsfcw_fftindex_ratio = 0x038b;
+            fftindex_bfsfcw_ratio = 0x0121;
+        } else if (bandwidth == 6000) {
+            coeff1_2048Nu = 0x02b580ad;
+            coeff1_4096Nu = 0x015ac057;
+            coeff1_8191Nu = 0x00ad6597;
+            coeff1_8192Nu = 0x00ad602b;
+            coeff1_8193Nu = 0x00ad5ac1;
+            coeff2_2k = 0x015ac057;
+            coeff2_4k = 0x00ad602b;
+            coeff2_8k = 0x0056b016;
+            bfsfcw_fftindex_ratio = 0x02f4;
+            fftindex_bfsfcw_ratio = 0x015b;
+        } else if (bandwidth == 7000) {
+            coeff1_2048Nu = 0x03291620;
+            coeff1_4096Nu = 0x01948b10;
+            coeff1_8191Nu = 0x00ca4bda;
+            coeff1_8192Nu = 0x00ca4588;
+            coeff1_8193Nu = 0x00ca3f36;
+            coeff2_2k = 0x01948b10;
+            coeff2_4k = 0x00ca4588;
+            coeff2_8k = 0x006522c4;
+            bfsfcw_fftindex_ratio = 0x0288;
+            fftindex_bfsfcw_ratio = 0x0195;
+        } else if (bandwidth == 8000) {
+            coeff1_2048Nu = 0x039cab92;
+            coeff1_4096Nu = 0x01ce55c9;
+            coeff1_8191Nu = 0x00e7321e;
+            coeff1_8192Nu = 0x00e72ae4;
+            coeff1_8193Nu = 0x00e723ab;
+            coeff2_2k = 0x01ce55c9;
+            coeff2_4k = 0x00e72ae4;
+            coeff2_8k = 0x00739572;
+            bfsfcw_fftindex_ratio = 0x0237;
+            fftindex_bfsfcw_ratio = 0x01ce;
+        } else {
+            error = Error_INVALID_BW;
+            goto exit;
+        }
+    } else if (adcFrequency == 20583333) {
+        if (bandwidth == 5000) {
+            coeff1_2048Nu = 0x02402402;
+            coeff1_4096Nu = 0x01201201;
+            coeff1_8191Nu = 0x00900d81;
+            coeff1_8192Nu = 0x00900901;
+            coeff1_8193Nu = 0x00900480;
+            coeff2_2k = 0x01201201;
+            coeff2_4k = 0x00900901;
+            coeff2_8k = 0x00480480;
+            bfsfcw_fftindex_ratio = 0x038e;
+            fftindex_bfsfcw_ratio = 0x0120;
+        } else if (bandwidth == 6000) {
+            coeff1_2048Nu = 0x02b35e69;
+            coeff1_4096Nu = 0x0159af35;
+            coeff1_8191Nu = 0x00acdd01;
+            coeff1_8192Nu = 0x00acd79a;
+            coeff1_8193Nu = 0x00acd234;
+            coeff2_2k = 0x0159af35;
+            coeff2_4k = 0x00acd79a;
+            coeff2_8k = 0x00566bcd;
+            bfsfcw_fftindex_ratio = 0x02f6;
+            fftindex_bfsfcw_ratio = 0x015a;
+        } else if (bandwidth == 7000) {
+            coeff1_2048Nu = 0x032698d0;
+            coeff1_4096Nu = 0x01934c68;
+            coeff1_8191Nu = 0x00c9ac81;
+            coeff1_8192Nu = 0x00c9a634;
+            coeff1_8193Nu = 0x00c99fe7;
+            coeff2_2k = 0x01934c68;
+            coeff2_4k = 0x00c9a634;
+            coeff2_8k = 0x0064d31a;
+            bfsfcw_fftindex_ratio = 0x028a;
+            fftindex_bfsfcw_ratio = 0x0193;
+        } else if (bandwidth == 8000) {
+            coeff1_2048Nu = 0x0399d337;
+            coeff1_4096Nu = 0x01cce99b;
+            coeff1_8191Nu = 0x00e67c02;
+            coeff1_8192Nu = 0x00e674ce;
+            coeff1_8193Nu = 0x00e66d9a;
+            coeff2_2k = 0x01cce99b;
+            coeff2_4k = 0x00e674ce;
+            coeff2_8k = 0x00733a67;
+            bfsfcw_fftindex_ratio = 0x0239;
+            fftindex_bfsfcw_ratio = 0x01cd;
+        } else {
+            error = Error_INVALID_BW;
+            goto exit;
+        }
+    } else if (adcFrequency == 20416667) {
+        if (bandwidth == 5000) {
+            coeff1_2048Nu = 0x023d337f;
+            coeff1_4096Nu = 0x011e99c0;
+            coeff1_8191Nu = 0x008f515a;
+            coeff1_8192Nu = 0x008f4ce0;
+            coeff1_8193Nu = 0x008f4865;
+            coeff2_2k = 0x011e99c0;
+            coeff2_4k = 0x008f4ce0;
+            coeff2_8k = 0x0047a670;
+            bfsfcw_fftindex_ratio = 0x0393;
+            fftindex_bfsfcw_ratio = 0x011f;
+        } else if (bandwidth == 6000) {
+            coeff1_2048Nu = 0x02afd765;
+            coeff1_4096Nu = 0x0157ebb3;
+            coeff1_8191Nu = 0x00abfb39;
+            coeff1_8192Nu = 0x00abf5d9;
+            coeff1_8193Nu = 0x00abf07a;
+            coeff2_2k = 0x0157ebb3;
+            coeff2_4k = 0x00abf5d9;
+            coeff2_8k = 0x0055faed;
+            bfsfcw_fftindex_ratio = 0x02fa;
+            fftindex_bfsfcw_ratio = 0x0158;
+        } else if (bandwidth == 7000) {
+            coeff1_2048Nu = 0x03227b4b;
+            coeff1_4096Nu = 0x01913da6;
+            coeff1_8191Nu = 0x00c8a518;
+            coeff1_8192Nu = 0x00c89ed3;
+            coeff1_8193Nu = 0x00c8988e;
+            coeff2_2k = 0x01913da6;
+            coeff2_4k = 0x00c89ed3;
+            coeff2_8k = 0x00644f69;
+            bfsfcw_fftindex_ratio = 0x028d;
+            fftindex_bfsfcw_ratio = 0x0191;
+        } else if (bandwidth == 8000) {
+            coeff1_2048Nu = 0x03951f32;
+            coeff1_4096Nu = 0x01ca8f99;
+            coeff1_8191Nu = 0x00e54ef7;
+            coeff1_8192Nu = 0x00e547cc;
+            coeff1_8193Nu = 0x00e540a2;
+            coeff2_2k = 0x01ca8f99;
+            coeff2_4k = 0x00e547cc;
+            coeff2_8k = 0x0072a3e6;
+            bfsfcw_fftindex_ratio = 0x023c;
+            fftindex_bfsfcw_ratio = 0x01cb;
+        } else {
+            error = Error_INVALID_BW;
+            goto exit;
+        }
+    } else if (adcFrequency == 20480000) {
+        if (bandwidth == 5000) {
+            coeff1_2048Nu = 0x023b6db7;
+            coeff1_4096Nu = 0x011db6db;
+            coeff1_8191Nu = 0x008edfe5;
+            coeff1_8192Nu = 0x008edb6e;
+            coeff1_8193Nu = 0x008ed6f7;
+            coeff2_2k = 0x011db6db;
+            coeff2_4k = 0x008edb6e;
+            coeff2_8k = 0x00476db7;
+            bfsfcw_fftindex_ratio = 0x0396;
+            fftindex_bfsfcw_ratio = 0x011e;
+        } else if (bandwidth == 6000) {
+            coeff1_2048Nu = 0x02adb6db;
+            coeff1_4096Nu = 0x0156db6e;
+            coeff1_8191Nu = 0x00ab7312;
+            coeff1_8192Nu = 0x00ab6db7;
+            coeff1_8193Nu = 0x00ab685c;
+            coeff2_2k = 0x0156db6e;
+            coeff2_4k = 0x00ab6db7;
+            coeff2_8k = 0x0055b6db;
+            bfsfcw_fftindex_ratio = 0x02fd;
+            fftindex_bfsfcw_ratio = 0x0157;
+        } else if (bandwidth == 7000) {
+            coeff1_2048Nu = 0x03200000;
+            coeff1_4096Nu = 0x01900000;
+            coeff1_8191Nu = 0x00c80640;
+            coeff1_8192Nu = 0x00c80000;
+            coeff1_8193Nu = 0x00c7f9c0;
+            coeff2_2k = 0x01900000;
+            coeff2_4k = 0x00c80000;
+            coeff2_8k = 0x00640000;
+            bfsfcw_fftindex_ratio = 0x028f;
+            fftindex_bfsfcw_ratio = 0x0190;
+        } else if (bandwidth == 8000) {
+            coeff1_2048Nu = 0x03924925;
+            coeff1_4096Nu = 0x01c92492;
+            coeff1_8191Nu = 0x00e4996e;
+            coeff1_8192Nu = 0x00e49249;
+            coeff1_8193Nu = 0x00e48b25;
+            coeff2_2k = 0x01c92492;
+            coeff2_4k = 0x00e49249;
+            coeff2_8k = 0x00724925;
+            bfsfcw_fftindex_ratio = 0x023d;
+            fftindex_bfsfcw_ratio = 0x01c9;
+        } else {
+            error = Error_INVALID_BW;
+            goto exit;
+        }
+    } else if (adcFrequency == 20500000) {
+        if (bandwidth == 5000) {
+            coeff1_2048Nu = 0x023adeff;
+            coeff1_4096Nu = 0x011d6f80;
+            coeff1_8191Nu = 0x008ebc36;
+            coeff1_8192Nu = 0x008eb7c0;
+            coeff1_8193Nu = 0x008eb34a;
+            coeff2_2k = 0x011d6f80;
+            coeff2_4k = 0x008eb7c0;
+            coeff2_8k = 0x00475be0;
+            bfsfcw_fftindex_ratio = 0x0396;
+            fftindex_bfsfcw_ratio = 0x011d;
+        } else if (bandwidth == 6000) {
+            coeff1_2048Nu = 0x02ad0b99;
+            coeff1_4096Nu = 0x015685cc;
+            coeff1_8191Nu = 0x00ab4840;
+            coeff1_8192Nu = 0x00ab42e6;
+            coeff1_8193Nu = 0x00ab3d8c;
+            coeff2_2k = 0x015685cc;
+            coeff2_4k = 0x00ab42e6;
+            coeff2_8k = 0x0055a173;
+            bfsfcw_fftindex_ratio = 0x02fd;
+            fftindex_bfsfcw_ratio = 0x0157;
+        } else if (bandwidth == 7000) {
+            coeff1_2048Nu = 0x031f3832;
+            coeff1_4096Nu = 0x018f9c19;
+            coeff1_8191Nu = 0x00c7d44b;
+            coeff1_8192Nu = 0x00c7ce0c;
+            coeff1_8193Nu = 0x00c7c7ce;
+            coeff2_2k = 0x018f9c19;
+            coeff2_4k = 0x00c7ce0c;
+            coeff2_8k = 0x0063e706;
+            bfsfcw_fftindex_ratio = 0x0290;
+            fftindex_bfsfcw_ratio = 0x0190;
+        } else if (bandwidth == 8000) {
+            coeff1_2048Nu = 0x039164cb;
+            coeff1_4096Nu = 0x01c8b266;
+            coeff1_8191Nu = 0x00e46056;
+            coeff1_8192Nu = 0x00e45933;
+            coeff1_8193Nu = 0x00e45210;
+            coeff2_2k = 0x01c8b266;
+            coeff2_4k = 0x00e45933;
+            coeff2_8k = 0x00722c99;
+            bfsfcw_fftindex_ratio = 0x023e;
+            fftindex_bfsfcw_ratio = 0x01c9;
+        } else {
+            error = Error_INVALID_BW;
+            goto exit;
+        }
+    } else if (adcFrequency == 20625000) {
+        if (bandwidth == 5000) {
+            coeff1_2048Nu = 0x02376948;
+            coeff1_4096Nu = 0x011bb4a4;
+            coeff1_8191Nu = 0x008ddec1;
+            coeff1_8192Nu = 0x008dda52;
+            coeff1_8193Nu = 0x008dd5e3;
+            coeff2_2k = 0x011bb4a4;
+            coeff2_4k = 0x008dda52;
+            coeff2_8k = 0x0046ed29;
+            bfsfcw_fftindex_ratio = 0x039c;
+            fftindex_bfsfcw_ratio = 0x011c;
+        } else if (bandwidth == 6000) {
+            coeff1_2048Nu = 0x02a8e4bd;
+            coeff1_4096Nu = 0x0154725e;
+            coeff1_8191Nu = 0x00aa3e81;
+            coeff1_8192Nu = 0x00aa392f;
+            coeff1_8193Nu = 0x00aa33de;
+            coeff2_2k = 0x0154725e;
+            coeff2_4k = 0x00aa392f;
+            coeff2_8k = 0x00551c98;
+            bfsfcw_fftindex_ratio = 0x0302;
+            fftindex_bfsfcw_ratio = 0x0154;
+        } else if (bandwidth == 7000) {
+            coeff1_2048Nu = 0x031a6032;
+            coeff1_4096Nu = 0x018d3019;
+            coeff1_8191Nu = 0x00c69e41;
+            coeff1_8192Nu = 0x00c6980c;
+            coeff1_8193Nu = 0x00c691d8;
+            coeff2_2k = 0x018d3019;
+            coeff2_4k = 0x00c6980c;
+            coeff2_8k = 0x00634c06;
+            bfsfcw_fftindex_ratio = 0x0294;
+            fftindex_bfsfcw_ratio = 0x018d;
+        } else if (bandwidth == 8000) {
+            coeff1_2048Nu = 0x038bdba6;
+            coeff1_4096Nu = 0x01c5edd3;
+            coeff1_8191Nu = 0x00e2fe02;
+            coeff1_8192Nu = 0x00e2f6ea;
+            coeff1_8193Nu = 0x00e2efd2;
+            coeff2_2k = 0x01c5edd3;
+            coeff2_4k = 0x00e2f6ea;
+            coeff2_8k = 0x00717b75;
+            bfsfcw_fftindex_ratio = 0x0242;
+            fftindex_bfsfcw_ratio = 0x01c6;
+        } else {
+            error = Error_INVALID_BW;
+            goto exit;
+        }
+    } else {
+        error = Error_INVALID_XTAL_FREQ;
+        goto exit;
+    }
+
+
+    /** Get ADC multiplier */
+    error = Standard_readRegister (demodulator, 0, Processor_OFDM, adcx2, &adcMultiplier);
+    if (error) goto exit;
+
+    if (adcMultiplier == 1) {
+        coeff1_2048Nu /= 2;
+        coeff1_4096Nu /= 2;
+        coeff1_8191Nu /= 2;
+        coeff1_8192Nu /= 2;
+        coeff1_8193Nu /= 2 ;
+        coeff2_2k /= 2;
+        coeff2_4k /= 2;
+        coeff2_8k /= 2;
+    }
+
+    /** Write coeff1_2048Nu */
+    /** Get Byte0 */
+    temp0 = (Byte) (coeff1_2048Nu & 0x000000FF);
+    /** Get Byte1 */
+    temp1 = (Byte) ((coeff1_2048Nu & 0x0000FF00) >> 8);
+    /** Get Byte2 */
+    temp2 = (Byte) ((coeff1_2048Nu & 0x00FF0000) >> 16);
+    /** Get Byte3 */
+    temp3 = (Byte) ((coeff1_2048Nu & 0x03000000) >> 24);
+
+    /** Gig endian to make 8051 happy */
+    buffer[cfoe_NS_2048_coeff1_25_24 - cfoe_NS_2048_coeff1_25_24] = temp3;
+    buffer[cfoe_NS_2048_coeff1_23_16 - cfoe_NS_2048_coeff1_25_24] = temp2;
+    buffer[cfoe_NS_2048_coeff1_15_8 - cfoe_NS_2048_coeff1_25_24] = temp1;
+    buffer[cfoe_NS_2048_coeff1_7_0 - cfoe_NS_2048_coeff1_25_24] = temp0;
+
+    /** Write coeff2_2k */
+    /** Get Byte0 */
+    temp0 = (Byte) ((coeff2_2k & 0x000000FF));
+    /** Get Byte1 */
+    temp1 = (Byte) ((coeff2_2k & 0x0000FF00) >> 8);
+    /** Get Byte2 */
+    temp2 = (Byte) ((coeff2_2k & 0x00FF0000) >> 16);
+    /** Get Byte3 */
+    temp3 = (Byte) ((coeff2_2k & 0x01000000) >> 24);
+
+    /** Gig endian to make 8051 happy */
+    buffer[cfoe_NS_2k_coeff2_24 - cfoe_NS_2048_coeff1_25_24] = temp3;
+    buffer[cfoe_NS_2k_coeff2_23_16 - cfoe_NS_2048_coeff1_25_24] = temp2;
+    buffer[cfoe_NS_2k_coeff2_15_8 - cfoe_NS_2048_coeff1_25_24] = temp1;
+    buffer[cfoe_NS_2k_coeff2_7_0 - cfoe_NS_2048_coeff1_25_24] = temp0;
+
+    /** Write coeff1_8191Nu */
+    /** Get Byte0 */
+    temp0 = (Byte) ((coeff1_8191Nu & 0x000000FF));
+    /** Get Byte1 */
+    temp1 = (Byte) ((coeff1_8191Nu & 0x0000FF00) >> 8);
+    /** Get Byte2 */
+    temp2 = (Byte) ((coeff1_8191Nu & 0x00FFC000) >> 16);
+    /** Get Byte3 */
+    temp3 = (Byte) ((coeff1_8191Nu & 0x03000000) >> 24);
+
+    /** Big endian to make 8051 happy */
+    buffer[cfoe_NS_8191_coeff1_25_24 - cfoe_NS_2048_coeff1_25_24] = temp3;
+    buffer[cfoe_NS_8191_coeff1_23_16 - cfoe_NS_2048_coeff1_25_24] = temp2;
+    buffer[cfoe_NS_8191_coeff1_15_8 - cfoe_NS_2048_coeff1_25_24] = temp1;
+    buffer[cfoe_NS_8191_coeff1_7_0 - cfoe_NS_2048_coeff1_25_24] = temp0;
+
+    /** Write coeff1_8192Nu */
+    /** Get Byte0 */
+    temp0  = (Byte) (coeff1_8192Nu & 0x000000FF);
+    /** Get Byte1 */
+    temp1 = (Byte) ((coeff1_8192Nu & 0x0000FF00) >> 8);
+    /** Get Byte2 */
+    temp2 = (Byte) ((coeff1_8192Nu & 0x00FFC000) >> 16);
+    /** Get Byte3 */
+    temp3 = (Byte) ((coeff1_8192Nu & 0x03000000) >> 24);
+
+    /** Gig endian to make 8051 happy */
+    buffer[cfoe_NS_8192_coeff1_25_24 - cfoe_NS_2048_coeff1_25_24] = temp3;
+    buffer[cfoe_NS_8192_coeff1_23_16 - cfoe_NS_2048_coeff1_25_24] = temp2;
+    buffer[cfoe_NS_8192_coeff1_15_8 - cfoe_NS_2048_coeff1_25_24] = temp1;
+    buffer[cfoe_NS_8192_coeff1_7_0 - cfoe_NS_2048_coeff1_25_24] = temp0;
+
+    /** Write coeff1_8193Nu */
+    /** Get Byte0 */
+    temp0 = (Byte) ((coeff1_8193Nu & 0x000000FF));
+    /** Get Byte1 */
+    temp1 = (Byte) ((coeff1_8193Nu & 0x0000FF00) >> 8);
+    /** Get Byte2 */
+    temp2 = (Byte) ((coeff1_8193Nu & 0x00FFC000) >> 16);
+    /** Get Byte3 */
+    temp3 = (Byte) ((coeff1_8193Nu & 0x03000000) >> 24);
+
+    /** Big endian to make 8051 happy */
+    buffer[cfoe_NS_8193_coeff1_25_24 - cfoe_NS_2048_coeff1_25_24] = temp3;
+    buffer[cfoe_NS_8193_coeff1_23_16 - cfoe_NS_2048_coeff1_25_24] = temp2;
+    buffer[cfoe_NS_8193_coeff1_15_8 - cfoe_NS_2048_coeff1_25_24] = temp1;
+    buffer[cfoe_NS_8193_coeff1_7_0 - cfoe_NS_2048_coeff1_25_24] = temp0;
+
+    /** Write coeff2_8k */
+    /** Get Byte0 */
+    temp0 = (Byte) ((coeff2_8k & 0x000000FF));
+    /** Get Byte1 */
+    temp1 = (Byte) ((coeff2_8k & 0x0000FF00) >> 8);
+    /** Get Byte2 */
+    temp2 = (Byte) ((coeff2_8k & 0x00FF0000) >> 16);
+    /** Get Byte3 */
+    temp3 = (Byte) ((coeff2_8k & 0x01000000) >> 24);
+
+    /** Big endian to make 8051 happy */
+    buffer[cfoe_NS_8k_coeff2_24 - cfoe_NS_2048_coeff1_25_24] = temp3;
+    buffer[cfoe_NS_8k_coeff2_23_16 - cfoe_NS_2048_coeff1_25_24] = temp2;
+    buffer[cfoe_NS_8k_coeff2_15_8 - cfoe_NS_2048_coeff1_25_24] = temp1;
+    buffer[cfoe_NS_8k_coeff2_7_0 - cfoe_NS_2048_coeff1_25_24] = temp0;
+
+    /** Write coeff1_4096Nu */
+    /** Get Byte0 */
+    temp0 = (Byte) (coeff1_4096Nu & 0x000000FF);
+    /** Get Byte1 */
+    temp1 = (Byte) ((coeff1_4096Nu & 0x0000FF00) >> 8);
+    /** Get Byte2 */
+    temp2 = (Byte) ((coeff1_4096Nu & 0x00FF0000) >> 16);
+    /** Get Byte3[1:0] */
+    /** Bit[7:2] will be written soon and so don't have to care them */
+    temp3 = (Byte) ((coeff1_4096Nu & 0x03000000) >> 24);
+
+    /** Big endian to make 8051 happy */
+    buffer[cfoe_NS_4096_coeff1_25_24 - cfoe_NS_2048_coeff1_25_24] = temp3;
+    buffer[cfoe_NS_4096_coeff1_23_16 - cfoe_NS_2048_coeff1_25_24] = temp2;
+    buffer[cfoe_NS_4096_coeff1_15_8 - cfoe_NS_2048_coeff1_25_24] = temp1;
+    buffer[cfoe_NS_4096_coeff1_7_0 - cfoe_NS_2048_coeff1_25_24] = temp0;
+
+    /** Write coeff2_4k */
+    /** Get Byte0 */
+    temp0 = (Byte) ((coeff2_4k & 0x000000FF));
+    /** Get Byte1 */
+    temp1 = (Byte) ((coeff2_4k & 0x0000FF00) >> 8);
+    /** Get Byte2 */
+    temp2 = (Byte) ((coeff2_4k & 0x00FF0000) >> 16);
+    /** Get Byte3 */
+    temp3 = (Byte) ((coeff2_4k & 0x01000000) >> 24);
+
+    /** Big endian to make 8051 happy */
+    buffer[cfoe_NS_4k_coeff2_24 - cfoe_NS_2048_coeff1_25_24] = temp3;
+    buffer[cfoe_NS_4k_coeff2_23_16 - cfoe_NS_2048_coeff1_25_24] = temp2;
+    buffer[cfoe_NS_4k_coeff2_15_8 - cfoe_NS_2048_coeff1_25_24] = temp1;
+    buffer[cfoe_NS_4k_coeff2_7_0 - cfoe_NS_2048_coeff1_25_24] = temp0;
+
+    /** Get Byte0 */
+    temp0 = (Byte) (bfsfcw_fftindex_ratio & 0x00FF);
+    /** Get Byte1 */
+    temp1 = (Byte) ((bfsfcw_fftindex_ratio & 0xFF00) >> 8);
+
+    /** Big endian to make 8051 happy */
+    buffer[bfsfcw_fftindex_ratio_15_8 - cfoe_NS_2048_coeff1_25_24] = temp1;
+    buffer[bfsfcw_fftindex_ratio_7_0 - cfoe_NS_2048_coeff1_25_24] = temp0;
+
+    /** Get Byte0 */
+    temp0 = (Byte) (fftindex_bfsfcw_ratio & 0x00FF);
+    /** Get Byte1 */
+    temp1 = (Byte) ((fftindex_bfsfcw_ratio & 0xFF00) >> 8);
+
+    /** Big endian to make 8051 happy */
+    buffer[fftindex_bfsfcw_ratio_15_8 - cfoe_NS_2048_coeff1_25_24] = temp1;
+    buffer[fftindex_bfsfcw_ratio_7_0 - cfoe_NS_2048_coeff1_25_24] = temp0;
+
+    error = Standard_writeRegisters (demodulator, chip, Processor_OFDM, cfoe_NS_2048_coeff1_25_24, 36, buffer);
+    if (error) goto exit;
+
+exit :
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_loadFirmware (
+    IN  Demodulator*    demodulator,
+    IN  Byte*           firmwareCodes,
+    IN  Segment*        firmwareSegments,
+    IN  Byte*           firmwarePartitions
+) {
+    Dword error = Error_NO_ERROR;
+    Dword beginPartition;
+    Dword endPartition;
+    Dword version;
+    Dword firmwareLength;
+    Byte* firmwareCodesPointer;
+    Word command;
+    Dword i;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    /** Set I2C master clock speed. */
+    error = Standard_writeRegister (demodulator, 0, Processor_LINK, p_reg_one_cycle_counter_tuner, User_I2C_SPEED);
+    if (error) goto exit;
+
+    firmwareCodesPointer = firmwareCodes;
+    beginPartition = 0;
+    endPartition = firmwarePartitions[0];
+
+    for (i = beginPartition; i < endPartition; i++) {
+        firmwareLength = firmwareSegments[i].segmentLength;
+        if (firmwareSegments[i].segmentType == 0) {
+            /** Dwonload firmware */
+            error = Standard_sendCommand (demodulator, Command_FW_DOWNLOAD_BEGIN, 0, Processor_LINK, 0, NULL, 0, NULL);
+            if (error) goto exit;
+            if (ganymede->cmdDescription->loadFirmware != NULL) {
+                error = ganymede->cmdDescription->loadFirmware (demodulator, firmwareLength, firmwareCodesPointer);
+            }
+            if (error) goto exit;
+            error = Standard_sendCommand (demodulator, Command_FW_DOWNLOAD_END, 0, Processor_LINK, 0, NULL, 0, NULL);
+            if (error) goto exit;
+        } else if (firmwareSegments[i].segmentType == 1) {
+            /** Copy firmware */
+            error = Standard_sendCommand (demodulator, Command_SCATTER_WRITE, 0, Processor_LINK, firmwareLength, firmwareCodesPointer, 0, NULL);
+            if (error) goto exit;
+        } else {
+            /** Direct write firmware */
+            command = (Word) (firmwareCodesPointer[0] << 8) + (Word) firmwareCodesPointer[1];
+            error = Standard_sendCommand (demodulator, command, 0, Processor_LINK, firmwareLength - 2, firmwareCodesPointer + 2, 0, NULL);
+            if (error) goto exit;
+        }
+        firmwareCodesPointer += firmwareLength;
+    }
+
+    /** Boot */
+    error = Standard_sendCommand (demodulator, Command_BOOT, 0, Processor_LINK, 0, NULL, 0, NULL);
+    if (error) goto exit;
+
+    User_delay (demodulator, 10);
+
+    /** Check if firmware is running */
+    version = 0;
+    error = Standard_getFirmwareVersion (demodulator, Processor_LINK, &version);
+    if (error) goto exit;
+    if (version == 0)
+        error = Error_BOOT_FAIL;
+
+exit :
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_loadScript (
+    IN  Demodulator*    demodulator,
+    IN  StreamType      streamType,
+    IN  Word*           scriptSets,
+    IN  ValueSet*       scripts,
+    IN  Word*           tunerScriptSets,
+    IN  ValueSet*       tunerScripts
+) {
+    Dword error = Error_NO_ERROR;
+    Word beginScript;
+    Word endScript;
+    //Byte adcType = 0;
+    Byte i;
+    Word j;
+	Byte value;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+
+    if ((scriptSets[0] != 0) && (scripts != NULL))
+    {
+        beginScript = 0;
+        endScript = scriptSets[0];
+
+        for (i = 0; i < ganymede->chipNumber; i++) {
+            /** Load OFSM init script */
+            for (j = beginScript; j < endScript; j++) {
+                error = Standard_writeRegister (demodulator, i, Processor_OFDM, scripts[j].address, scripts[j].value);
+                if (error) goto exit;
+            }
+        }
+    }
+
+	/** Detect difference between A and B */
+	error = Standard_readRegister (demodulator, 0, Processor_LINK, 0x384F, &value);
+	if (error) goto exit;
+
+    if ((tunerScriptSets[0] != 0) && (tunerScripts != NULL))
+    {
+        if (tunerScriptSets[1] != 0 && value == 0xFF)
+        {
+            beginScript = tunerScriptSets[0];
+            endScript = tunerScriptSets[0] + tunerScriptSets[1];
+		} else {
+            beginScript = 0;
+            endScript = tunerScriptSets[0];
+        }
+
+        for (i = 0; i < ganymede->chipNumber; i++) {
+            /** Load tuner init script */
+            for (j = beginScript; j < endScript; j++) {
+                error = Standard_writeRegister (demodulator, i, Processor_OFDM, tunerScripts[j].address, tunerScripts[j].value);
+                if (error) goto exit;
+            }
+        }
+    }
+
+exit :
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_loadIrTable (
+    IN  Demodulator*    demodulator,
+    IN  Word            tableLength,
+    IN  Byte*           table
+) {
+    Dword error = Error_NO_ERROR;
+    Byte baseHigh;
+    Byte baseLow;
+    Word registerBase;
+    Word i;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    error = Standard_readRegister (demodulator, 0, Processor_LINK, 0x417F, &baseHigh);
+    if (error) goto exit;
+    error = Standard_readRegister (demodulator, 0, Processor_LINK, 0x4180, &baseLow);
+    if (error) goto exit;
+
+    registerBase = (Word) (baseHigh << 8) + (Word) baseLow;
+
+    if (registerBase) {
+        for (i = 0; i < tableLength; i++) {
+            error = Standard_writeRegister (demodulator, 0, Processor_LINK, registerBase + i, table[i]);
+            if (error) goto exit;
+        }
+    }
+
+exit :
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_initialize (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chipNumber,
+    IN  Word            sawBandwidth,
+    IN  StreamType      streamType,
+    IN  Architecture    architecture
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    InitializeRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    ganymede->driver = NULL;
+    error = Standard_getDriver (demodulator, &ganymede->driver);
+
+    if (ganymede->driver != NULL) {
+        request.chipNumber = chipNumber;
+        request.sawBandwidth = sawBandwidth;
+        request.streamType = streamType;
+        request.architecture = architecture;
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_INITIALIZE,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    Dword crystal = 0;
+    Dword adc = 0;
+    Dword fcw = 0;
+    Byte buffer[4];
+	Dword version = 0;
+    Word* tunerScriptSets = NULL;
+    ValueSet* tunerScripts = NULL;
+
+
+    Byte i;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    ganymede->chipNumber = chipNumber;
+    ganymede->options = 0x0000;
+    ganymede->fcw = 0x00000000;
+    ganymede->frequency[0] = 642000;
+	ganymede->frequency[1] = 642000;
+    ganymede->initialized = False;
+
+    if (ganymede->busId == 0xFFFF) {
+        goto exit;
+    }
+
+
+    if (ganymede->tunerDescription->tunerId == 0xFFFF) {
+        goto exit;
+    }
+
+	error = Standard_getFirmwareVersion (demodulator, Processor_LINK, &version);
+	if (error) goto exit;
+	if (version != 0) {
+		ganymede->booted = True;
+	} else {
+		ganymede->booted = False;
+	}
+
+
+
+
+    ganymede->firmwareCodes = Firmware_codes;
+    ganymede->firmwareSegments = Firmware_segments;
+#if 1 //j017,set to 1  //j014+s 
+    ganymede->firmwarePartitions = Firmware_partitions;
+#else
+    ganymede->firmwarePartitions = Firmware_new_partitions;
+#endif //j014+e
+    ganymede->scriptSets = Firmware_scriptSets;
+    ganymede->scripts = Firmware_scripts;
+
+    /** Set up by default tunerDescription */ /** release1remove */
+    tunerScriptSets = ganymede->tunerDescription->tunerScriptSets;
+    tunerScripts = ganymede->tunerDescription->tunerScript;
+
+
+    error = Standard_readRegisterBits (demodulator, 0, Processor_LINK, r_io_mux_pwron_clk_strap, io_mux_pwron_clk_strap_pos, io_mux_pwron_clk_strap_len, &i);
+    if (error) goto exit;
+
+    ganymede->crystalFrequency = Standard_clockTable[i].crystalFrequency;
+    ganymede->adcFrequency = Standard_clockTable[i].adcFrequency;
+
+    ganymede->dataReady = False;
+
+    /** Write secondary I2C address to device */
+    /** it is needed to write i2c address prior to fw-downloading */
+    if (ganymede->chipNumber > 1) {
+		error = Standard_writeRegister (demodulator, 0, Processor_LINK, 0x417F, ((PDEVICE_CONTEXT)demodulator->userData)->Map.I2C_SLAVE_ADDR);
+        if (error) goto exit;
+    } else {
+        error = Standard_writeRegister (demodulator, 0, Processor_LINK, 0x417F, 0x00);
+        if (error) goto exit;
+    }
+
+    if (ganymede->firmwareCodes != NULL) {
+        if (ganymede->booted == False) {
+            error = Standard_loadFirmware (demodulator, ganymede->firmwareCodes, ganymede->firmwareSegments, ganymede->firmwarePartitions);
+            if (error) goto exit;
+            ganymede->booted = True;
+        }
+    }
+
+    /** Detect the HostA or HostB */
+    error = Standard_readRegisterBits (demodulator, 0, Processor_LINK, r_io_mux_pwron_hosta, io_mux_pwron_hosta_pos, io_mux_pwron_hosta_len, &ganymede->hostInterface[0]);
+    if (error) goto exit;
+
+
+    /** Tell firmware the type of tuner. */
+    for (i = 0; i < ganymede->chipNumber; i++) {
+		error = Standard_writeRegister (demodulator, i, Processor_LINK, p_reg_link_ofsm_dummy_15_8, (Byte) ganymede->tunerDescription->tunerId);
+        if (error) goto exit;
+
+        /** Set read-update bit to 1 for constellation */
+        error = Standard_writeRegisterBits (demodulator, i, Processor_OFDM, p_reg_feq_read_update, reg_feq_read_update_pos, reg_feq_read_update_len, 1);
+        if (error) goto exit;
+
+        /** Enable FEC Monitor */
+        error = Standard_writeRegisterBits (demodulator, i, Processor_OFDM, p_fec_vtb_rsd_mon_en, fec_vtb_rsd_mon_en_pos, fec_vtb_rsd_mon_en_len, 1);
+        if (error) goto exit;
+    }
+
+    /** Compute ADC and load them to device */
+    error = Standard_computeCrystal (demodulator, (Long) ganymede->crystalFrequency * 1000, &crystal);
+    if (error) goto exit;
+
+    buffer[0] = (Byte) (crystal & 0x000000FF);
+    buffer[1] = (Byte) ((crystal & 0x0000FF00) >> 8);
+    buffer[2] = (Byte) ((crystal & 0x00FF0000) >> 16);
+    buffer[3] = (Byte) ((crystal & 0xFF000000) >> 24);
+    for (i = 0; i < ganymede->chipNumber; i++) {
+        error = Standard_writeRegisters (demodulator, i, Processor_OFDM, crystal_clk_7_0, 4, buffer);
+        if (error) goto exit;
+    }
+
+    /** Compute ADC and load them to device */
+    error = Standard_computeAdc (demodulator, (Long) ganymede->adcFrequency, &adc);
+    if (error) goto exit;
+
+    buffer[0] = (Byte) (adc & 0x000000FF);
+    buffer[1] = (Byte) ((adc & 0x0000FF00) >> 8);
+    buffer[2] = (Byte) ((adc & 0x00FF0000) >> 16);
+    for (i = 0; i < ganymede->chipNumber; i++) {
+        error = Standard_writeRegisters (demodulator, i, Processor_OFDM, p_reg_f_adc_7_0, 3, buffer);
+        if (error) goto exit;
+    }
+
+    /** Compute FCW and load them to device */
+    error = Standard_computeFcw (demodulator, (Long) ganymede->adcFrequency, (Long) ganymede->tunerDescription->ifFrequency, ganymede->tunerDescription->inversion, &fcw);
+    if (error) goto exit;
+    ganymede->fcw = fcw;
+
+    buffer[0] = (Byte) (fcw & 0x000000FF);
+    buffer[1] = (Byte) ((fcw & 0x0000FF00) >> 8);
+    buffer[2] = (Byte) ((fcw & 0x007F0000) >> 16);
+    for (i = 0; i < ganymede->chipNumber; i++) {
+        error = Standard_writeRegisters (demodulator, i, Processor_OFDM, bfs_fcw_7_0, bfs_fcw_22_16 - bfs_fcw_7_0 + 1, buffer);    
+        if (error) goto exit;
+    }
+
+    /** Set the desired stream type */
+    error = Standard_setStreamType (demodulator, streamType);
+    if (error) goto exit;
+
+    /** Set the desired architecture type */
+    error = Standard_setArchitecture (demodulator, architecture);
+    if (error) goto exit;
+
+    if (ganymede->scripts != NULL) {
+        error = Standard_loadScript (demodulator, streamType, ganymede->scriptSets, ganymede->scripts, tunerScriptSets, tunerScripts);
+        if (error) goto exit;
+    }
+
+    if (ganymede->tunerDescription->openTuner != NULL) {
+        if ((ganymede->busId != Bus_I2M) && (ganymede->busId != Bus_I2U)) {
+            for (i = 0; i < ganymede->chipNumber; i++) {
+                error = ganymede->tunerDescription->openTuner (demodulator, i);
+                if (error) goto exit;
+            }
+        }
+    }
+
+#if User_USE_INTERRUPT
+    if (ganymede->busId == Bus_SDIO) {
+        error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_sdioc_external_int_en, reg_sdioc_external_int_en_pos, reg_sdioc_external_int_en_len, 1);
+        if (error) goto exit;
+    }
+#endif
+
+	for (i = 0; i< ganymede->chipNumber; i++) {
+
+		/** Set H/W MPEG2 locked detection **/
+		error = Standard_writeRegister (demodulator, i, Processor_LINK, p_reg_top_lock3_out, 1);
+		if (error) goto exit;
+
+		/** Set registers for driving power 0xD830 **/
+		error = Standard_writeRegister (demodulator, i, Processor_LINK, p_reg_top_padmiscdr2, 1);
+		if (error) goto exit;
+
+		/** Set registers for driving power 0xD831 **/
+		error = Standard_writeRegister (demodulator, i, Processor_LINK, p_reg_top_padmiscdr4, 0);
+		if (error) goto exit;
+
+		/** Set registers for driving power 0xD832 **/
+		error = Standard_writeRegister (demodulator, i, Processor_LINK, p_reg_top_padmiscdr8, 0);
+		if (error) goto exit;
+	}
+
+    ganymede->initialized = True;
+
+#endif
+exit:
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_finalize (
+    IN  Demodulator*    demodulator
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    FinalizeRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_FINALIZE,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    Byte i;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->tunerDescription->closeTuner != NULL) {
+        for (i = 0; i < ganymede->chipNumber; i++) {
+            error = ganymede->tunerDescription->closeTuner (demodulator, i);
+        }
+    }
+
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_isAgcLocked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+#else
+    Byte temp;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    *locked = False;
+
+    error = Standard_readRegisterBits (demodulator, chip, Processor_OFDM, p_agc_lock, agc_lock_pos, agc_lock_len, &temp);
+    if (error) goto exit;
+    if (temp) *locked = True;
+
+exit :
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_isCfoeLocked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+#else
+    Byte temp;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    *locked = False;
+
+    error = Standard_readRegisterBits (demodulator, chip, Processor_OFDM, r_reg_cfoe_divg_flag, reg_cfoe_divg_flag_pos, reg_cfoe_divg_flag_len, &temp);
+    if (error) goto exit;
+    if (!temp) *locked = True;
+
+exit :
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_isSfoeLocked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+#else
+    Byte temp;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    *locked = False;
+
+    error = Standard_readRegisterBits (demodulator, chip, Processor_OFDM, r_reg_sfoe_divg_flag, reg_sfoe_divg_flag_pos, reg_sfoe_divg_flag_len, &temp);
+    if (error) goto exit;
+    if (!temp) *locked = True;
+
+exit :
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_isTpsLocked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+#else
+    Byte temp;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    *locked = False;
+
+    error = Standard_readRegisterBits (demodulator, chip, Processor_OFDM, p_fd_tpsd_lock, fd_tpsd_lock_pos, fd_tpsd_lock_len, &temp);
+    if (error) goto exit;
+    if (temp) *locked = True;
+
+exit :
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_isMpeg2Locked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+#else
+    Byte temp;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    *locked = False;
+
+    error = Standard_readRegisterBits (demodulator, chip, Processor_OFDM, r_mp2if_sync_byte_locked, mp2if_sync_byte_locked_pos, mp2if_sync_byte_locked_len, &temp);
+    if (error) goto exit;
+    if (temp) *locked = True;
+
+exit :
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_isLocked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+) {
+    Dword error = Error_NO_ERROR;
+
+    Word emptyLoop = 0;
+    Word tpsLoop = 0;
+    Word mpeg2Loop = 0;
+    Byte channels[2];
+    Byte begin;
+    Byte end;
+    Byte i;
+    Byte emptyChannel = 1;
+    Byte tpsLocked = 0;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    IsLockedRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        request.chip = chip;
+        request.locked = locked;
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_ISLOCKED,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    
+    *locked = False;
+
+    if (ganymede->architecture == Architecture_DCA) {
+        begin = 0;
+        end = ganymede->chipNumber;
+    } else {
+        begin = chip;
+        end = begin + 1;
+    }
+
+    for (i = begin; i < end; i++) {
+        ganymede->statistic[i].signalPresented = False;
+        ganymede->statistic[i].signalLocked = False;
+        ganymede->statistic[i].signalQuality = 0;
+        ganymede->statistic[i].signalStrength = 0;
+    }
+
+    channels[0] = 2;
+    channels[1] = 2;
+    while (emptyLoop < 40) {
+        for (i = begin; i < end; i++) {
+            error = Standard_readRegister (demodulator, i, Processor_OFDM, empty_channel_status, &channels[i]);
+            if (error) goto exit;
+        }
+        if ((channels[0] == 1) || (channels[1] == 1)) {
+            emptyChannel = 0;
+            break;
+        }
+        if ((channels[0] == 2) && (channels[1] == 2)) {
+            emptyChannel = 1;
+            goto exit;
+        }
+        User_delay (demodulator, 25);
+        emptyLoop++;
+    }
+
+    if (emptyChannel == 1) goto exit;
+
+    while (tpsLoop < 50) {
+        for (i = begin; i < end; i++) {
+            /** Empty channel */
+            error = Standard_isTpsLocked (demodulator, i, &ganymede->statistic[i].signalPresented);
+            if (error) goto exit;
+            if (ganymede->statistic[i].signalPresented == True) {
+                tpsLocked = 1;
+                break;
+            }
+        }
+
+        if (tpsLocked == 1) break;
+
+        User_delay (demodulator, 25);
+        tpsLoop++;
+    }
+
+    if (tpsLocked == 0) goto exit;
+
+    while (mpeg2Loop < 40) {
+        if (ganymede->architecture == Architecture_DCA) {
+            error = Standard_isMpeg2Locked (demodulator, 0, &ganymede->statistic[0].signalLocked);
+            if (error) goto exit;
+            if (ganymede->statistic[0].signalLocked == True) {
+                for (i = begin; i < end; i++) {
+                    ganymede->statistic[i].signalQuality = 80;
+                    ganymede->statistic[i].signalStrength = 80;
+                }
+                *locked = True;
+                break;
+            }
+        } else {
+            error = Standard_isMpeg2Locked (demodulator, chip, &ganymede->statistic[chip].signalLocked);
+            if (error) goto exit;
+            if (ganymede->statistic[chip].signalLocked == True) {
+                ganymede->statistic[chip].signalQuality = 80;
+                ganymede->statistic[chip].signalStrength = 80;
+                *locked = True;
+                break;
+            }
+        }
+        User_delay (demodulator, 25);
+        mpeg2Loop++;
+    }
+    for (i = begin; i < end; i++) {
+        ganymede->statistic[i].signalQuality = 0;
+        ganymede->statistic[i].signalStrength = 20;
+    }
+
+exit:
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_setPriority (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Priority        priority
+)
+{
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+#else
+    Byte pri;
+    Byte cr;
+    Byte valuew_7_0 = 0;
+    Byte valuew_10_8 = 0;
+    Byte nfvaluew_7_0 = 0;
+    Byte nfvaluew_10_8 = 0;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    if (priority == Priority_HIGH) {
+        pri = 1;
+        /** Get code rate here */
+        error = Standard_readRegisterBits (demodulator, chip, Processor_OFDM, g_reg_tpsd_hpcr, reg_tpsd_hpcr_pos, reg_tpsd_hpcr_len, &cr);
+        if (error) goto exit;
+    } else {
+        pri = 0;
+        /** Get code rate here */
+        error = Standard_readRegisterBits (demodulator, chip, Processor_OFDM, g_reg_tpsd_lpcr, reg_tpsd_lpcr_pos, reg_tpsd_lpcr_len, &cr);
+        if (error) goto exit;
+    }
+
+    error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, g_reg_dec_pri, reg_dec_pri_pos, reg_dec_pri_len, pri);
+    if (error) goto exit;
+
+    /** Set sbx quantizer */
+    switch (cr) {
+        case 0 :
+            valuew_7_0 = 0x20;
+            valuew_10_8 = 0x03;
+            nfvaluew_7_0 = 0x00;
+            nfvaluew_10_8 = 0x01;
+            break;
+        case 1 :
+            valuew_7_0 = 0x5E;
+            valuew_10_8 = 0x01;
+            nfvaluew_7_0 = 0x80;
+            nfvaluew_10_8 = 0x00;
+            break;
+        case 2 :
+            valuew_7_0 = 0x2C;
+            valuew_10_8 = 0x01;
+            nfvaluew_7_0 = 0x55;
+            nfvaluew_10_8 = 0x00;
+            break;
+        case 3 :
+            valuew_7_0 = 0xFA;
+            valuew_10_8 = 0x00;
+            nfvaluew_7_0 = 0x40;
+            nfvaluew_10_8 = 0x00;
+            break;
+        case 4 :
+            valuew_7_0 = 0xC8;
+            valuew_10_8 = 0x00;
+            nfvaluew_7_0 = 0x33;
+            nfvaluew_10_8 = 0x00;
+            break;
+    }
+
+    error = Standard_writeRegister (demodulator, chip, Processor_OFDM, p_reg_qnt_valuew_7_0, valuew_7_0);
+    if (error) goto exit;
+    error = Standard_writeRegister (demodulator, chip, Processor_OFDM, p_reg_qnt_valuew_10_8, valuew_10_8);
+    if (error) goto exit;
+    error = Standard_writeRegister (demodulator, chip, Processor_OFDM, p_reg_qnt_nfvaluew_7_0, nfvaluew_7_0);
+    if (error) goto exit;
+    error = Standard_writeRegister (demodulator, chip, Processor_OFDM, p_reg_qnt_nfvaluew_10_8, nfvaluew_10_8);
+    if (error) goto exit;
+
+exit :
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_reset (
+    IN  Demodulator*    demodulator
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+#else
+    Byte value;
+    Byte i;
+    Byte j;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    for (i = 0; i < ganymede->chipNumber; i++) {
+
+        /** Enable OFDM reset */
+        error = Standard_writeRegisterBits (demodulator, i, Processor_OFDM, I2C_reg_ofdm_rst_en, reg_ofdm_rst_en_pos, reg_ofdm_rst_en_len, 0x01);
+        if (error) goto exit;
+
+        /** Start reset mechanism */
+        value = 0x00;
+        error = Standard_writeRegisters (demodulator, i, Processor_OFDM, RESET_STATE, 1, &value);
+        if (error) goto exit;
+
+        /** Clear ofdm reset */
+        for (j = 0; j < 150; j++) {
+            error = Standard_readRegisterBits (demodulator, i, Processor_OFDM, I2C_reg_ofdm_rst, reg_ofdm_rst_pos, reg_ofdm_rst_len, &value);
+            if (error) goto exit;
+            if (value) break;
+            User_delay (demodulator, 10);
+        }
+
+        if (j == 150) {
+            error = Error_RESET_TIMEOUT;
+            goto exit;
+        }
+
+        error = Standard_writeRegisterBits (demodulator, i, Processor_OFDM, I2C_reg_ofdm_rst, reg_ofdm_rst_pos, reg_ofdm_rst_len, 0);
+        if (error) goto exit;
+
+        /** Disable OFDM reset */
+        error = Standard_writeRegisterBits (demodulator, i, Processor_OFDM, I2C_reg_ofdm_rst_en, reg_ofdm_rst_en_pos, reg_ofdm_rst_en_len, 0x00);
+        if (error) goto exit;
+    }
+
+exit :
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_programFcw (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Long            shift,          /** Hz */
+    IN  Dword           adcFrequency    /** Hz */
+)
+{
+    Dword error = Error_NO_ERROR;
+    Dword fcw;
+    Long fcwShift;
+    Byte temp0;
+    Byte temp1;
+    Byte temp2;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    /** Get shift freq */
+    fcwShift = (shift * 8 * 1024 + (Long) adcFrequency / (2 * 1024)) / (Long) adcFrequency * 1024;
+
+    fcw  = (Dword) ((Long) ganymede->fcw + fcwShift);
+
+    temp0 = (Byte) (fcw  & 0x000000FF);
+    temp1 = (Byte) ((fcw & 0x0000FF00) >> 8);
+    temp2 = (Byte) ((fcw & 0x007F0000) >> 16);
+
+    error = Standard_writeRegister (demodulator, chip, Processor_OFDM, p_reg_bfs_fcw_7_0, temp0);
+    if (error) goto exit;
+    error = Standard_writeRegister (demodulator, chip, Processor_OFDM, p_reg_bfs_fcw_15_8, temp1);
+    if (error) goto exit;
+    error = Standard_writeRegister (demodulator, chip, Processor_OFDM, p_reg_bfs_fcw_22_16, temp2);
+    if (error) goto exit;
+
+exit :
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_getChannelModulation (
+    IN  Demodulator*            demodulator,
+    IN  Byte                    chip,
+    OUT ChannelModulation*      channelModulation
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    GetChannelModulationRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        request.chip = chip;
+        request.channelModulation = channelModulation;
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_GETCHANNELMODULATION,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    Byte temp;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    /** Get constellation type */
+    error = Standard_readRegisterBits (demodulator, chip, Processor_OFDM, g_reg_tpsd_const, reg_tpsd_const_pos, reg_tpsd_const_len, &temp);
+    if (error) goto exit;
+    channelModulation->constellation = (Constellation) temp;
+
+    /** Get TPS hierachy and alpha value */
+    error = Standard_readRegisterBits (demodulator, chip, Processor_OFDM, g_reg_tpsd_hier, reg_tpsd_hier_pos, reg_tpsd_hier_len, &temp);
+    if (error) goto exit;
+    channelModulation->hierarchy = (Hierarchy)temp;
+
+    /** Get high/low priority */
+    error = Standard_readRegisterBits (demodulator, chip, Processor_OFDM, g_reg_dec_pri, reg_dec_pri_pos, reg_dec_pri_len, &temp);
+    if (error) goto exit;
+    if (temp)
+        channelModulation->priority = Priority_HIGH;
+    else
+        channelModulation->priority = Priority_LOW;
+
+    /** Get high code rate */
+    error = Standard_readRegisterBits (demodulator, chip, Processor_OFDM, g_reg_tpsd_hpcr, reg_tpsd_hpcr_pos, reg_tpsd_hpcr_len, &temp);
+    if (error) goto exit;
+    channelModulation->highCodeRate = (CodeRate) temp;
+
+    /** Get low code rate */
+    error = Standard_readRegisterBits (demodulator, chip, Processor_OFDM, g_reg_tpsd_lpcr, reg_tpsd_lpcr_pos, reg_tpsd_lpcr_len, &temp);
+    if (error) goto exit;
+    channelModulation->lowCodeRate  = (CodeRate) temp;
+
+    /** Get guard interval */
+    error = Standard_readRegisterBits (demodulator, chip, Processor_OFDM, g_reg_tpsd_gi, reg_tpsd_gi_pos, reg_tpsd_gi_len, &temp);
+    if (error) goto exit;
+    channelModulation->interval = (Interval) temp;
+
+    /** Get FFT mode */
+    error = Standard_readRegisterBits (demodulator, chip, Processor_OFDM, g_reg_tpsd_txmod, reg_tpsd_txmod_pos, reg_tpsd_txmod_len, &temp);
+    if (error) goto exit;
+    channelModulation->transmissionMode = (TransmissionModes) temp;
+
+    /** Get bandwidth */
+    error = Standard_readRegisterBits (demodulator, chip, Processor_OFDM, g_reg_bw, reg_bw_pos, reg_bw_len, &temp);
+    if (error) goto exit;
+    channelModulation->bandwidth = (Bandwidth) temp;
+
+    /** Get frequency */
+    channelModulation->frequency = ganymede->frequency[chip];
+
+exit :
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_setChannelModulation (
+    IN  Demodulator*            demodulator,
+    IN  Byte                    chip,
+    IN  ChannelModulation*      channelModulation
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+#else
+    Byte temp;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    /** Set constellation type */
+    error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, g_reg_tpsd_const, reg_tpsd_const_pos, reg_tpsd_const_len, (Byte) channelModulation->constellation);
+    if (error) goto exit;
+
+    /** Set TPS hierachy and alpha value */
+    error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, g_reg_tpsd_hier, reg_tpsd_hier_pos, reg_tpsd_hier_len, (Byte) channelModulation->hierarchy);
+    if (error) goto exit;
+
+    /** Set high/low priority */
+    if (channelModulation->priority == Priority_HIGH)
+        temp = 1;
+    else
+        temp = 0;
+    error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, g_reg_dec_pri, reg_dec_pri_pos, reg_dec_pri_len, temp);
+    if (error) goto exit;
+
+    /** Set high code rate */
+    error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, g_reg_tpsd_hpcr, reg_tpsd_hpcr_pos, reg_tpsd_hpcr_len, (Byte) channelModulation->highCodeRate);
+    if (error) goto exit;
+
+    /** Set low code rate */
+    error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, g_reg_tpsd_lpcr, reg_tpsd_lpcr_pos, reg_tpsd_lpcr_len, (Byte) channelModulation->lowCodeRate);
+    if (error) goto exit;
+
+    /** Set guard interval */
+    error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, g_reg_tpsd_gi, reg_tpsd_gi_pos, reg_tpsd_gi_len, (Byte) channelModulation->interval);
+    if (error) goto exit;
+
+    /** Set FFT mode */
+    error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, g_reg_tpsd_txmod, reg_tpsd_txmod_pos, reg_tpsd_txmod_len, (Byte) channelModulation->transmissionMode);
+    if (error) goto exit;
+
+    /** Set bandwidth */
+    error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, g_reg_bw, reg_bw_pos, reg_bw_len, (Byte) channelModulation->bandwidth);
+    if (error) goto exit;
+
+exit :
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+Dword Standard_setFrequency (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Dword           frequency
+) {
+    Dword error = Error_NO_ERROR;
+    Byte band;
+    Byte i;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    /** Clear easy mode flag first */
+    error = Standard_writeRegister (demodulator, chip, Processor_OFDM, Training_Mode, 0x00);
+    if (error) goto exit;
+
+    /** Clear empty_channel_status lock flag */
+    error = Standard_writeRegister (demodulator, chip, Processor_OFDM, empty_channel_status, 0x00);
+    if (error) goto exit;
+
+    /** Clear MPEG2 lock flag */
+    error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, r_mp2if_sync_byte_locked, mp2if_sync_byte_locked_pos, mp2if_sync_byte_locked_len, 0x00);
+    if (error) goto exit;
+
+    /** Determine frequency band */
+    band = 0xFF;
+    for (i = 0; i < Standard_MAX_BAND; i++) {
+        if ((frequency >= Standard_bandTable[i].minimum) && (frequency <= Standard_bandTable[i].maximum)) {
+            band = i;
+            break;
+        }
+    }
+    error = Standard_writeRegister (demodulator, chip, Processor_OFDM, FreBand, band);
+    if (error) goto exit;
+
+    if (ganymede->tunerDescription->setTuner != NULL) {
+        if ((ganymede->busId != Bus_I2M) && (ganymede->busId != Bus_I2U)) {
+            error = ganymede->tunerDescription->setTuner (demodulator, chip, ganymede->bandwidth[chip], frequency);
+            if (error) goto exit;
+        }
+    }
+
+    /** Trigger ofsm */
+    error = Standard_writeRegister (demodulator, chip, Processor_OFDM, trigger_ofsm, 0);
+    if (error) goto exit;
+
+    ganymede->frequency[chip] = frequency;
+
+exit :
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_setFrequencyForRetrain (
+    IN  Demodulator*            demodulator,
+    IN  Byte                    chip,
+    IN  Dword                   frequency,
+    IN  Word                    bandwidth,
+    IN  ChannelModulation*      channelModulation
+)
+{
+    Dword error = Error_NO_ERROR;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    /** Clear MPEG2 lock flag first */
+    error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, r_mp2if_sync_byte_locked, mp2if_sync_byte_locked_pos, mp2if_sync_byte_locked_len, 0);
+    if (error) goto exit;
+
+    /** Set frequency for all chips */
+    if (ganymede->tunerDescription->setTuner != NULL) {
+        error = ganymede->tunerDescription->setTuner (demodulator, chip, bandwidth, frequency);
+        if (error) goto exit;
+    }
+
+    /** Trigger ofsm */
+    error = Standard_writeRegister (demodulator, chip, Processor_OFDM, trigger_ofsm, 0);
+    if (error) goto exit;
+
+exit :
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_maskDcaOutput (
+    IN  Demodulator*    demodulator
+) {
+    Dword error = Error_NO_ERROR;
+    Byte i;
+    Bool dcaValid = False;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    if ((ganymede->chipNumber > 1) && (ganymede->architecture == Architecture_DCA))
+        dcaValid = True;
+
+    if (dcaValid == True) {
+        for (i = 0; i < ganymede->chipNumber; i++) {
+            error = Standard_writeRegisterBits (demodulator, i, Processor_OFDM, p_reg_dca_upper_out_en, reg_dca_upper_out_en_pos, reg_dca_upper_out_en_len, 0);
+            if (error) goto exit;
+        }
+        User_delay (demodulator, 5);
+    }
+
+exit :
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_acquireChannel (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Word            bandwidth,
+    IN  Dword           frequency
+) {
+    Dword error = Error_NO_ERROR;
+
+    Byte begin;
+    Byte end;
+    Byte i;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    AcquireChannelRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        request.chip = chip;
+        request.frequency = frequency;
+        request.bandwidth = bandwidth;
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_ACQUIRECHANNEL,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    Ganymede* ganymede;
+    deb_info("Enter %s , bw=%d, freq=%d\n", __FUNCTION__, bandwidth, frequency);
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->architecture == Architecture_DCA) {
+        begin = 0;
+        end = ganymede->chipNumber;
+    } else {
+        begin = chip;
+        end = begin + 1;
+    }
+
+    for (i = begin; i < end; i++) {
+        error = Standard_selectBandwidth (demodulator, i, bandwidth, ganymede->adcFrequency);
+        if (error) goto exit;
+		ganymede->bandwidth[i] = bandwidth;
+    }
+
+    error = Standard_maskDcaOutput (demodulator);
+    if (error) goto exit;
+
+    /** Set frequency */
+    for (i = begin; i < end; i++) {
+        error = Standard_setFrequency (demodulator, i, frequency);
+        if (error) goto exit;
+    }
+
+exit :
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_setStreamType (
+    IN  Demodulator*    demodulator,
+    IN  StreamType      streamType
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    SetStreamTypeRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        request.streamType = streamType;
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_SETSTREAMTYPE,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    //Dword warning = Error_NO_ERROR;
+    Ganymede* ganymede;
+    Byte i;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    /** Enable DVB-T interrupt if next stream type is StreamType_DVBT_DATAGRAM */
+    if (streamType == StreamType_DVBT_DATAGRAM) {
+        for (i = 0; i < ganymede->chipNumber; i++) {
+            error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_dvbt_inten, reg_dvbt_inten_pos, reg_dvbt_inten_len, 1);
+            if (error) goto exit;
+            if ((ganymede->busId == Bus_USB) || (ganymede->busId == Bus_USB11)) {
+                error = Standard_writeRegisterBits (demodulator, i, Processor_OFDM, p_reg_mpeg_full_speed, reg_mpeg_full_speed_pos, reg_mpeg_full_speed_len, 0);
+                if (error) goto exit;
+            } else {
+                error = Standard_writeRegisterBits (demodulator, i, Processor_OFDM, p_reg_mpeg_full_speed, reg_mpeg_full_speed_pos, reg_mpeg_full_speed_len, 1);
+                if (error) goto exit;
+            }
+        }
+    }
+
+    /** Enable DVB-T mode */
+    for (i = 0; i < ganymede->chipNumber; i++) {
+        error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_dvbt_en, reg_dvbt_en_pos, reg_dvbt_en_len, 1);
+        if (error) goto exit;
+    }
+
+    /** Enter sub mode */
+    switch (streamType) {
+
+	case StreamType_NONE : 
+		goto exit;
+		break;
+
+        case StreamType_DVBT_DATAGRAM :
+            if ((ganymede->busId == Bus_USB) || (ganymede->busId == Bus_USB11)) {
+                error = Standard_writeRegisterBits (demodulator, 0, Processor_OFDM, p_mp2if_mpeg_ser_mode, mp2if_mpeg_ser_mode_pos, mp2if_mpeg_ser_mode_len, 0);
+                if (error) goto exit;
+                error = Standard_writeRegisterBits (demodulator, 0, Processor_OFDM, p_mp2if_mpeg_par_mode, mp2if_mpeg_par_mode_pos, mp2if_mpeg_par_mode_len, 0);
+                if (error) goto exit;
+                /** Fix current leakage */
+                if (ganymede->chipNumber > 1) {
+                    if (ganymede->hostInterface[0]) {
+                        error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_top_hostb_mpeg_ser_mode, reg_top_hostb_mpeg_ser_mode_pos, reg_top_hostb_mpeg_ser_mode_len, 0);
+                        if (error) goto exit;
+                        error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_top_hostb_mpeg_par_mode, reg_top_hostb_mpeg_par_mode_pos, reg_top_hostb_mpeg_par_mode_len, 1);
+                        if (error) goto exit;
+                    } else {
+                        error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_top_hosta_mpeg_ser_mode, reg_top_hosta_mpeg_ser_mode_pos, reg_top_hosta_mpeg_ser_mode_len, 0);
+                        if (error) goto exit;
+                        error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_top_hosta_mpeg_par_mode, reg_top_hosta_mpeg_par_mode_pos, reg_top_hosta_mpeg_par_mode_len, 1);
+                        if (error) goto exit;
+                    }
+                } else {
+                    error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_top_hosta_mpeg_ser_mode, reg_top_hosta_mpeg_ser_mode_pos, reg_top_hosta_mpeg_ser_mode_len, 0);
+                    if (error) goto exit;
+                    error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_top_hosta_mpeg_par_mode, reg_top_hosta_mpeg_par_mode_pos, reg_top_hosta_mpeg_par_mode_len, 1);
+                    if (error) goto exit;
+                    error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_top_hostb_mpeg_ser_mode, reg_top_hostb_mpeg_ser_mode_pos, reg_top_hostb_mpeg_ser_mode_len, 0);
+                    if (error) goto exit;
+                    error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_top_hostb_mpeg_par_mode, reg_top_hostb_mpeg_par_mode_pos, reg_top_hostb_mpeg_par_mode_len, 1);
+                    if (error) goto exit;
+                }
+            } else {
+                error = Standard_writeRegisterBits (demodulator, 0, Processor_OFDM, p_mp2if_mpeg_ser_mode, mp2if_mpeg_ser_mode_pos, mp2if_mpeg_ser_mode_len, 0);
+                if (error) goto exit;
+                error = Standard_writeRegisterBits (demodulator, 0, Processor_OFDM, p_mp2if_mpeg_par_mode, mp2if_mpeg_par_mode_pos, mp2if_mpeg_par_mode_len, 0);
+                if (error) goto exit;
+
+                /** Fix current leakage */
+                if (ganymede->chipNumber > 1) {
+                    error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_top_hosta_mpeg_ser_mode, reg_top_hosta_mpeg_ser_mode_pos, reg_top_hosta_mpeg_ser_mode_len, 0);
+                    if (error) goto exit;
+                    error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_top_hosta_mpeg_par_mode, reg_top_hosta_mpeg_par_mode_pos, reg_top_hosta_mpeg_par_mode_len, 0);
+                    if (error) goto exit;
+                    error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_top_hostb_mpeg_ser_mode, reg_top_hostb_mpeg_ser_mode_pos, reg_top_hostb_mpeg_ser_mode_len, 0);
+                    if (error) goto exit;
+                    error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_top_hostb_mpeg_par_mode, reg_top_hostb_mpeg_par_mode_pos, reg_top_hostb_mpeg_par_mode_len, 0);
+                    if (error) goto exit;
+                } else {
+                    if (ganymede->hostInterface[0]) {
+                        error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_top_hostb_mpeg_ser_mode, reg_top_hostb_mpeg_ser_mode_pos, reg_top_hostb_mpeg_ser_mode_len, 0);
+                        if (error) goto exit;
+                        error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_top_hostb_mpeg_par_mode, reg_top_hostb_mpeg_par_mode_pos, reg_top_hostb_mpeg_par_mode_len, 1);
+                        if (error) goto exit;
+                    } else {
+                        error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_top_hosta_mpeg_ser_mode, reg_top_hosta_mpeg_ser_mode_pos, reg_top_hosta_mpeg_ser_mode_len, 0);
+                        if (error) goto exit;
+                        error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_top_hosta_mpeg_par_mode, reg_top_hosta_mpeg_par_mode_pos, reg_top_hosta_mpeg_par_mode_len, 1);
+                        if (error) goto exit;
+                    }
+                }
+            }
+            break;
+        case StreamType_DVBT_PARALLEL :
+            for (i = 0; i < ganymede->chipNumber; i++) {
+                error = Standard_writeRegisterBits (demodulator, i, Processor_OFDM, p_mp2if_mpeg_ser_mode, mp2if_mpeg_ser_mode_pos, mp2if_mpeg_ser_mode_len, 0);
+                if (error) goto exit;
+                error = Standard_writeRegisterBits (demodulator, i, Processor_OFDM, p_mp2if_mpeg_par_mode, mp2if_mpeg_par_mode_pos, mp2if_mpeg_par_mode_len, 1);
+                if (error) goto exit;
+
+                if (i == 0) {
+                    if (ganymede->hostInterface[0]) {
+                        /** HostA interface is enabled */
+                        error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_top_hosta_mpeg_ser_mode, reg_top_hosta_mpeg_ser_mode_pos, reg_top_hosta_mpeg_ser_mode_len, 0);
+                        if (error) goto exit;
+                        error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_top_hosta_mpeg_par_mode, reg_top_hosta_mpeg_par_mode_pos, reg_top_hosta_mpeg_par_mode_len, 1);
+                        if (error) goto exit;
+                    } else {
+                        /** HostB interface is enabled */
+                        error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_top_hostb_mpeg_ser_mode, reg_top_hostb_mpeg_ser_mode_pos, reg_top_hostb_mpeg_ser_mode_len, 0);
+                        if (error) goto exit;
+                        error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_top_hostb_mpeg_par_mode, reg_top_hostb_mpeg_par_mode_pos, reg_top_hostb_mpeg_par_mode_len, 1);
+                        if (error) goto exit;
+                    }
+                } else {
+                    /** HostA interface is enabled */
+                    error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_top_hosta_mpeg_ser_mode, reg_top_hosta_mpeg_ser_mode_pos, reg_top_hosta_mpeg_ser_mode_len, 0);
+                    if (error) goto exit;
+                    error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_top_hosta_mpeg_par_mode, reg_top_hosta_mpeg_par_mode_pos, reg_top_hosta_mpeg_par_mode_len, 1);
+                    if (error) goto exit;
+                }
+            }
+            break;
+        case StreamType_DVBT_SERIAL :
+            for (i = 0; i < ganymede->chipNumber; i++) {
+                error = Standard_writeRegisterBits (demodulator, i, Processor_OFDM, p_mp2if_mpeg_ser_mode, mp2if_mpeg_ser_mode_pos, mp2if_mpeg_ser_mode_len, 1);
+                if (error) goto exit;
+
+                if (i == 0) {
+                    if (ganymede->hostInterface[0]) {
+                        /** HostA interface is enabled */
+                        error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_top_hosta_mpeg_ser_mode, reg_top_hosta_mpeg_ser_mode_pos, reg_top_hosta_mpeg_ser_mode_len, 1);
+                        if (error) goto exit;
+                    } else {
+                        /** HostB interface is enabled */
+                        error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_top_hostb_mpeg_ser_mode, reg_top_hostb_mpeg_ser_mode_pos, reg_top_hostb_mpeg_ser_mode_len, 1);
+                        if (error) goto exit;
+                    }
+                } else {
+                    /** HostA interface is enabled */
+                    error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_top_hosta_mpeg_ser_mode, reg_top_hosta_mpeg_ser_mode_pos, reg_top_hosta_mpeg_ser_mode_len, 1);
+                    if (error) goto exit;
+                }
+            }
+            break;
+    }
+    error = User_mpegConfig (demodulator);
+
+    ganymede->streamType = streamType;
+
+exit :
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_setArchitecture (
+    IN  Demodulator*    demodulator,
+    IN  Architecture    architecture
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    SetArchitectureRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        request.architecture = architecture;
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_SETARCHITECTURE,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    Word frameSize;
+    Byte packetSize;
+    Byte buffer[2];
+    Byte standAlone[2];
+    Byte upperChip[2];
+    Byte upperHost[2];
+    Byte lowerChip[2];
+    Byte lowerHost[2];
+    Byte dcaEnable[2];
+    Byte phaseLatch[2];
+    Byte fpgaLatch[2];
+    Byte i;
+    Bool pipValid = False;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    if (architecture == Architecture_DCA) {
+        for (i = 0; i < ganymede->chipNumber; i++) {
+            standAlone[i] = 0;
+            upperChip[i] = 0;
+            upperHost[i] = 0;
+            lowerChip[i] = 0;
+            lowerHost[i] = 0;
+            dcaEnable[i] = 1;
+            phaseLatch[i] = 0;
+            fpgaLatch[i] = 0;
+        }
+        if (ganymede->chipNumber == 1) {
+            standAlone[0] = 1;
+            dcaEnable[0] = 0;
+        } else {
+            upperChip[ganymede->chipNumber - 1] = 1;
+            upperHost[0] = 1;
+            lowerChip[0] = 1;
+            lowerHost[ganymede->chipNumber - 1] = 1;
+            phaseLatch[0] = 1;
+            phaseLatch[ganymede->chipNumber - 1] = 1;
+            fpgaLatch[0] = 0x66;
+            fpgaLatch[ganymede->chipNumber - 1] = 0x66;
+        }
+    } else {
+        for (i = 0; i < ganymede->chipNumber; i++) {
+            standAlone[i] = 1;
+            upperChip[i] = 0;
+            upperHost[i] = 0;
+            lowerChip[i] = 0;
+            lowerHost[i] = 0;
+            dcaEnable[i] = 0;
+            phaseLatch[i] = 0;
+            fpgaLatch[i] = 0;
+        }
+    }
+
+    if (ganymede->initialized == True) {
+        error = Standard_maskDcaOutput (demodulator);
+        if (error) goto exit;
+    }
+
+    /** Set upper chip first in order to avoid I/O conflict */
+    for (i = ganymede->chipNumber; i > 0; i--) {
+        /** Set dca_upper_chip */
+        error = Standard_writeRegisterBits (demodulator, i - 1, Processor_OFDM, p_reg_dca_upper_chip, reg_dca_upper_chip_pos, reg_dca_upper_chip_len, upperChip[i - 1]);
+        if (error) goto exit;
+        if (i == 1) {
+            if ((ganymede->busId == Bus_USB) || (ganymede->busId == Bus_USB11)) {
+                if (ganymede->hostInterface[0]) {
+                    error = Standard_writeRegisterBits (demodulator, i - 1, Processor_LINK, p_reg_top_hosta_dca_upper, reg_top_hosta_dca_upper_pos, reg_top_hosta_dca_upper_len, upperHost[i - 1]);
+                    if (error) goto exit;
+                    error = Standard_writeRegisterBits (demodulator, i - 1, Processor_LINK, p_reg_top_hostb_dca_upper, reg_top_hostb_dca_upper_pos, reg_top_hostb_dca_upper_len, 0);
+                    if (error) goto exit;
+                } else {
+                    error = Standard_writeRegisterBits (demodulator, i - 1, Processor_LINK, p_reg_top_hostb_dca_upper, reg_top_hostb_dca_upper_pos, reg_top_hostb_dca_upper_len, upperHost[i - 1]);
+                    if (error) goto exit;
+                    error = Standard_writeRegisterBits (demodulator, i - 1, Processor_LINK, p_reg_top_hosta_dca_upper, reg_top_hosta_dca_upper_pos, reg_top_hosta_dca_upper_len, 0);
+                    if (error) goto exit;
+                }
+            } else {
+                if (ganymede->hostInterface[0]) {
+                    error = Standard_writeRegisterBits (demodulator, i - 1, Processor_LINK, p_reg_top_hostb_dca_upper, reg_top_hostb_dca_upper_pos, reg_top_hostb_dca_upper_len, upperHost[i - 1]);
+                    if (error) goto exit;
+                    error = Standard_writeRegisterBits (demodulator, i - 1, Processor_LINK, p_reg_top_hosta_dca_upper, reg_top_hosta_dca_upper_pos, reg_top_hosta_dca_upper_len, 0);
+                    if (error) goto exit;
+                } else {
+                    error = Standard_writeRegisterBits (demodulator, i - 1, Processor_LINK, p_reg_top_hosta_dca_upper, reg_top_hosta_dca_upper_pos, reg_top_hosta_dca_upper_len, upperHost[i - 1]);
+                    if (error) goto exit;
+                    error = Standard_writeRegisterBits (demodulator, i - 1, Processor_LINK, p_reg_top_hostb_dca_upper, reg_top_hostb_dca_upper_pos, reg_top_hostb_dca_upper_len, 0);
+                    if (error) goto exit;
+                }
+            }
+        } else {
+            error = Standard_writeRegisterBits (demodulator, i - 1, Processor_LINK, p_reg_top_hostb_dca_upper, reg_top_hostb_dca_upper_pos, reg_top_hostb_dca_upper_len, upperHost[i - 1]);
+            if (error) goto exit;
+            error = Standard_writeRegisterBits (demodulator, i - 1, Processor_LINK, p_reg_top_hosta_dca_upper, reg_top_hosta_dca_upper_pos, reg_top_hosta_dca_upper_len, 0);
+            if (error) goto exit;
+        }
+
+        /** Set dca_lower_chip */
+        error = Standard_writeRegisterBits (demodulator, i - 1, Processor_OFDM, p_reg_dca_lower_chip, reg_dca_lower_chip_pos, reg_dca_lower_chip_len, lowerChip[i - 1]);
+        if (error) goto exit;
+        if (i == 1) {
+            if ((ganymede->busId == Bus_USB) || (ganymede->busId == Bus_USB11)) {
+                if (ganymede->hostInterface[0]) {
+                    error = Standard_writeRegisterBits (demodulator, i - 1, Processor_LINK, p_reg_top_hosta_dca_lower, reg_top_hosta_dca_lower_pos, reg_top_hosta_dca_lower_len, lowerHost[i - 1]);
+                    if (error) goto exit;
+                    error = Standard_writeRegisterBits (demodulator, i - 1, Processor_LINK, p_reg_top_hostb_dca_lower, reg_top_hostb_dca_lower_pos, reg_top_hostb_dca_lower_len, 0);
+                    if (error) goto exit;
+                } else {
+                    error = Standard_writeRegisterBits (demodulator, i - 1, Processor_LINK, p_reg_top_hostb_dca_lower, reg_top_hostb_dca_lower_pos, reg_top_hostb_dca_lower_len, lowerHost[i - 1]);
+                    if (error) goto exit;
+                    error = Standard_writeRegisterBits (demodulator, i - 1, Processor_LINK, p_reg_top_hosta_dca_lower, reg_top_hosta_dca_lower_pos, reg_top_hosta_dca_lower_len, 0);
+                    if (error) goto exit;
+                }
+            } else {
+                if (ganymede->hostInterface[0]) {
+                    error = Standard_writeRegisterBits (demodulator, i - 1, Processor_LINK, p_reg_top_hostb_dca_lower, reg_top_hostb_dca_lower_pos, reg_top_hostb_dca_lower_len, lowerHost[i - 1]);
+                    if (error) goto exit;
+                    error = Standard_writeRegisterBits (demodulator, i - 1, Processor_LINK, p_reg_top_hosta_dca_lower, reg_top_hosta_dca_lower_pos, reg_top_hosta_dca_lower_len, 0);
+                    if (error) goto exit;
+                } else {
+                    error = Standard_writeRegisterBits (demodulator, i - 1, Processor_LINK, p_reg_top_hosta_dca_lower, reg_top_hosta_dca_lower_pos, reg_top_hosta_dca_lower_len, lowerHost[i - 1]);
+                    if (error) goto exit;
+                    error = Standard_writeRegisterBits (demodulator, i - 1, Processor_LINK, p_reg_top_hostb_dca_lower, reg_top_hostb_dca_lower_pos, reg_top_hostb_dca_lower_len, 0);
+                    if (error) goto exit;
+                }
+            }
+        } else {
+            error = Standard_writeRegisterBits (demodulator, i - 1, Processor_LINK, p_reg_top_hostb_dca_lower, reg_top_hostb_dca_lower_pos, reg_top_hostb_dca_lower_len, lowerHost[i - 1]);
+            if (error) goto exit;
+            error = Standard_writeRegisterBits (demodulator, i - 1, Processor_LINK, p_reg_top_hosta_dca_lower, reg_top_hosta_dca_lower_pos, reg_top_hosta_dca_lower_len, 0);
+            if (error) goto exit;
+        }
+
+        /** Set phase latch */
+        error = Standard_writeRegisterBits (demodulator, i - 1, Processor_OFDM, p_reg_dca_platch, reg_dca_platch_pos, reg_dca_platch_len, phaseLatch[i - 1]);
+        if (error) goto exit;
+
+        /** Set fpga latch */
+        error = Standard_writeRegisterBits (demodulator, i - 1, Processor_OFDM, p_reg_dca_fpga_latch, reg_dca_fpga_latch_pos, reg_dca_fpga_latch_len, fpgaLatch[i - 1]);
+        if (error) goto exit;
+    }
+
+    for (i = 0; i < ganymede->chipNumber; i++) {
+        /** Set stand alone */
+        error = Standard_writeRegisterBits (demodulator, i, Processor_OFDM, p_reg_dca_stand_alone, reg_dca_stand_alone_pos, reg_dca_stand_alone_len, standAlone[i]);
+        if (error) goto exit;
+
+        /** Set DCA enable */
+        error = Standard_writeRegisterBits (demodulator, i, Processor_OFDM, p_reg_dca_en, reg_dca_en_pos, reg_dca_en_len, dcaEnable[i]);
+        if (error) goto exit;
+    }
+
+    if (ganymede->initialized == True) {
+        for (i = 0; i < ganymede->chipNumber; i++) {
+            error = Standard_writeRegister (demodulator, i, Processor_OFDM, trigger_ofsm, 0);
+            if (error) goto exit;
+        }
+    }
+
+
+    if ((ganymede->busId == Bus_USB) || (ganymede->busId == Bus_USB11)) {
+        frameSize = User_USB20_FRAME_SIZE_DW;
+        packetSize = (Byte) (User_USB20_MAX_PACKET_SIZE / 4);
+
+        if (ganymede->busId == Bus_USB11) {
+            frameSize   = User_USB11_FRAME_SIZE_DW;
+            packetSize = (Byte) (User_USB11_MAX_PACKET_SIZE / 4);
+        }
+
+        if ((ganymede->chipNumber > 1) && (architecture == Architecture_PIP))
+            pipValid = True;
+#if 0 //j011+s
+        /** Reset EP4 */
+        error = Standard_writeRegisterBits (demodulator, 0, Processor_OFDM, p_reg_mp2_sw_rst, reg_mp2_sw_rst_pos, reg_mp2_sw_rst_len, 1);
+        if (error) goto exit;
+#endif //j011+e
+
+        /** Reset EP5 */
+        error = Standard_writeRegisterBits (demodulator, 0, Processor_OFDM, p_reg_mp2if2_sw_rst, reg_mp2if2_sw_rst_pos, reg_mp2if2_sw_rst_len, 1);
+        if (error) goto exit;
+
+        /** Disable EP4 */
+        error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_ep4_tx_en, reg_ep4_tx_en_pos, reg_ep4_tx_en_len, 0);
+        if (error) goto exit;
+
+        /** Disable EP5 */
+        error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_ep5_tx_en, reg_ep5_tx_en_pos, reg_ep5_tx_en_len, 0);
+        if (error) goto exit;
+
+        /** Disable EP4 NAK */
+        error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_ep4_tx_nak, reg_ep4_tx_nak_pos, reg_ep4_tx_nak_len, 0);
+        if (error) goto exit;
+
+        /** Disable EP5 NAK */
+        error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_ep5_tx_nak, reg_ep5_tx_nak_pos, reg_ep5_tx_nak_len, 0);
+        if (error) goto exit;
+
+        /** Enable EP4 */
+        error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_ep4_tx_en, reg_ep4_tx_en_pos, reg_ep4_tx_en_len, 1);
+        if (error) goto exit;
+
+        /** Set EP4 transfer length */
+        buffer[p_reg_ep4_tx_len_7_0 - p_reg_ep4_tx_len_7_0] = (Byte) frameSize;
+        buffer[p_reg_ep4_tx_len_15_8 - p_reg_ep4_tx_len_7_0] = (Byte) (frameSize >> 8);
+        error = Standard_writeRegisters (demodulator, 0, Processor_LINK, p_reg_ep4_tx_len_7_0, 2, buffer);
+
+        /** Set EP4 packet size */
+        error = Standard_writeRegister (demodulator, 0, Processor_LINK, p_reg_ep4_max_pkt, packetSize);
+        if (error) goto exit;
+
+        if (pipValid == True) {
+            /** Enable EP5 */
+            error = Standard_writeRegisterBits (demodulator, 0, Processor_LINK, p_reg_ep5_tx_en, reg_ep5_tx_en_pos, reg_ep5_tx_en_len, 1);
+            if (error) goto exit;
+
+            /** Set EP5 transfer length */
+            buffer[p_reg_ep5_tx_len_7_0 - p_reg_ep5_tx_len_7_0] = (Byte) frameSize;
+            buffer[p_reg_ep5_tx_len_15_8 - p_reg_ep5_tx_len_7_0] = (Byte) (frameSize >> 8);
+            error = Standard_writeRegisters (demodulator, 0, Processor_LINK, p_reg_ep5_tx_len_7_0, 2, buffer);
+
+            /** Set EP5 packet size */
+            error = Standard_writeRegister (demodulator, 0, Processor_LINK, p_reg_ep5_max_pkt, packetSize);
+            if (error) goto exit;
+        }
+
+
+        /** Disable 15 SER/PAR mode */
+        error = Standard_writeRegisterBits (demodulator, 0, Processor_OFDM, p_mp2if_mpeg_ser_mode, mp2if_mpeg_ser_mode_pos, mp2if_mpeg_ser_mode_len, 0);
+        if (error) goto exit;
+        error = Standard_writeRegisterBits (demodulator, 0, Processor_OFDM, p_mp2if_mpeg_par_mode, mp2if_mpeg_par_mode_pos, mp2if_mpeg_par_mode_len, 0);
+        if (error) goto exit;
+
+        if (pipValid == True) {
+            /** Enable mp2if2 */
+            error = Standard_writeRegisterBits (demodulator, 0, Processor_OFDM, p_reg_mp2if2_en, reg_mp2if2_en_pos, reg_mp2if2_en_len, 1);
+            if (error) goto exit;
+
+            for (i = 1; i < ganymede->chipNumber; i++) {
+                /** Enable serial mode */
+                error = Standard_writeRegisterBits (demodulator, i, Processor_OFDM, p_mp2if_mpeg_ser_mode, mp2if_mpeg_ser_mode_pos, mp2if_mpeg_ser_mode_len, 1);
+                if (error) goto exit;
+
+                /** Enable HostB serial */
+                error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_top_hostb_mpeg_ser_mode, reg_top_hostb_mpeg_ser_mode_pos, reg_top_hostb_mpeg_ser_mode_len, 1);
+                if (error) goto exit;
+            }
+
+            /** Enable tsis */
+            error = Standard_writeRegisterBits (demodulator, 0, Processor_OFDM, p_reg_tsis_en, reg_tsis_en_pos, reg_tsis_en_len, 1);
+            if (error) goto exit;
+        } else {
+            /** Disable mp2if2 */
+            error = Standard_writeRegisterBits (demodulator, 0, Processor_OFDM, p_reg_mp2if2_en, reg_mp2if2_en_pos, reg_mp2if2_en_len, 0);
+            if (error) goto exit;
+
+            for (i = 1; i < ganymede->chipNumber; i++) {
+                /** Disable serial mode */
+                error = Standard_writeRegisterBits (demodulator, i, Processor_OFDM, p_mp2if_mpeg_ser_mode, mp2if_mpeg_ser_mode_pos, mp2if_mpeg_ser_mode_len, 0);
+                if (error) goto exit;
+
+                /** Disable HostB serial */
+                error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_top_hostb_mpeg_ser_mode, reg_top_hostb_mpeg_ser_mode_pos, reg_top_hostb_mpeg_ser_mode_len, 0);
+                if (error) goto exit;
+            }
+
+            /** Disable tsis */
+            error = Standard_writeRegisterBits (demodulator, 0, Processor_OFDM, p_reg_tsis_en, reg_tsis_en_pos, reg_tsis_en_len, 0);
+            if (error) goto exit;
+        }
+
+        /** Negate EP4 reset */
+        error = Standard_writeRegisterBits (demodulator, 0, Processor_OFDM, p_reg_mp2_sw_rst, reg_mp2_sw_rst_pos, reg_mp2_sw_rst_len, 0);
+        if (error) goto exit;
+
+        /** Negate EP5 reset */
+        error = Standard_writeRegisterBits (demodulator, 0, Processor_OFDM, p_reg_mp2if2_sw_rst, reg_mp2if2_sw_rst_pos, reg_mp2if2_sw_rst_len, 0);
+        if (error) goto exit;
+
+        if (pipValid == True) {
+            /** Split 15 PSB to 1K + 1K and enable flow control */
+            error = Standard_writeRegisterBits (demodulator, 0, Processor_OFDM, p_reg_mp2if2_half_psb, reg_mp2if2_half_psb_pos, reg_mp2if2_half_psb_len, 0);
+            if (error) goto exit;
+            error = Standard_writeRegisterBits (demodulator, 0, Processor_OFDM, p_reg_mp2if_stop_en, reg_mp2if_stop_en_pos, reg_mp2if_stop_en_len, 1);
+            if (error) goto exit;
+
+            for (i = 1; i < ganymede->chipNumber; i++) {
+                error = Standard_writeRegisterBits (demodulator, i, Processor_OFDM, p_reg_mpeg_full_speed, reg_mpeg_full_speed_pos, reg_mpeg_full_speed_len, 0);
+                if (error) goto exit;
+                error = Standard_writeRegisterBits (demodulator, i, Processor_OFDM, p_reg_mp2if_stop_en, reg_mp2if_stop_en_pos, reg_mp2if_stop_en_len, 0);
+                if (error) goto exit;
+            }
+        }
+    }
+
+    ganymede->architecture = architecture;
+
+exit:
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_setStatisticRange (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            superFrameCount,
+    IN  Word            packetUnit
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    SetStatisticRangeRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        request.chip = chip;
+        request.superFrameCount = superFrameCount;
+        request.packetUnit = packetUnit;
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_SETSTATISTICRANGE,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    Byte temp0;
+    Byte temp1;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    /** Set super frame count */
+    error = Standard_writeRegister (demodulator, chip, Processor_OFDM, qnt_vbc_sframe_num, superFrameCount);
+    if (error) goto exit;
+
+    /** Set packet unit. */
+    temp0 = (Byte) packetUnit;
+    temp1 = (Byte) (packetUnit >> 8);
+    error = Standard_writeRegisters (demodulator, chip, Processor_OFDM, rsd_packet_unit_7_0, 1, &temp0);
+    if (error) goto exit;
+    error = Standard_writeRegisters (demodulator, chip, Processor_OFDM, rsd_packet_unit_15_8, 1, &temp1);
+    if (error) goto exit;
+
+exit:
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_getStatisticRange (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte*           frameCount,
+    IN  Word*           packetUnit
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    GetStatisticRangeRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        request.chip = chip;
+        request.superFrameCount = superFrameCount;
+        request.packetUnit = packetUnit;
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_GETSTATISTICRANGE,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    Byte temp0;
+    Byte temp1;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    /** Get super frame count */
+    error = Standard_readRegister (demodulator, chip, Processor_OFDM, qnt_vbc_sframe_num, frameCount);
+    if (error) goto exit;
+
+    /** Get packet unit. */
+    error = Standard_readRegisters (demodulator, chip, Processor_OFDM, r_rsd_packet_unit_7_0, 1, &temp0);
+    if (error) goto exit;
+    error = Standard_readRegisters (demodulator, chip, Processor_OFDM, r_rsd_packet_unit_15_8, 1, &temp1);
+    if (error) goto exit;
+    *packetUnit = (Word) (temp1 << 8) + (Word) temp0;
+
+exit:
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_getStatistic (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Statistic*      statistic
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    GetStatisticRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        request.chip = chip;
+        request.statistic = statistic;
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_GETSTATISTIC,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    Ganymede* ganymede;
+    Byte quality;
+    Byte strength;
+    Byte buffer[2];
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    /** Get statistic by stream type */
+    error = Standard_readRegisters (demodulator, chip, Processor_OFDM, tpsd_lock, mpeg_lock - tpsd_lock + 1, buffer);
+    if (error) goto exit;
+
+    if (buffer[tpsd_lock - tpsd_lock])
+        ganymede->statistic[chip].signalPresented = True;
+    else
+        ganymede->statistic[chip].signalPresented = False;
+
+    if (buffer[mpeg_lock - tpsd_lock])
+        ganymede->statistic[chip].signalLocked = True;
+    else
+        ganymede->statistic[chip].signalLocked = False;
+
+    error = Standard_getSignalQuality (demodulator, chip, &quality);
+    if (error) goto exit;
+
+    ganymede->statistic[chip].signalQuality = quality;
+
+    error = Standard_getSignalStrength (demodulator, chip, &strength);
+    if (error) goto exit;
+
+    ganymede->statistic[chip].signalStrength = strength;
+
+    *statistic = ganymede->statistic[chip];
+
+exit :
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_getInterrupts (
+    IN  Demodulator*    demodulator,
+    OUT Interrupts*     interrupts
+) {
+    Dword error = Error_NO_ERROR;
+    Ganymede* ganymede;
+    Byte value = 0;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    /** Get interrupts by stream type */
+
+
+    *interrupts = Interrupt_NONE;
+
+    /** Read the interrupts register to determine the type of interrupts. */
+    error = Standard_readRegister (demodulator, 0, Processor_LINK, r_link_ofsm_dvbt_int, &value);
+    if (error) goto exit;
+
+    if (value & 0x04) {
+        ganymede->dataReady = True;
+        *interrupts |= Interrupt_DVBT;
+    }
+
+exit:
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_clearInterrupt (
+    IN  Demodulator*    demodulator,
+    IN  Interrupt       interrupt
+) {
+    Dword error = Error_NO_ERROR;
+    Ganymede* ganymede;
+    Byte value = 0;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    /** Clear interrupt by stream type */
+
+    //error = ganymede->dvbtStandardDescription.clearInterrupt (demodulator, interrupt);
+    value = (Byte) interrupt;
+
+    /** Clear the specific interrupt. */
+    error = Standard_writeRegister (demodulator, 0, Processor_LINK, p_reg_dvbt_intsts, value);
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_getDataLength (
+    IN  Demodulator*    demodulator,
+    OUT Dword*          dataLength,
+    OUT Bool*           valid           /** used in DVBH mode */
+) {
+    Dword error = Error_NO_ERROR;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    /** Get data length by stream type */
+    switch (ganymede->burstSize) {
+        case BurstSize_1024 :
+            *dataLength = 1024;
+            break;
+        case BurstSize_2048 :
+            *dataLength = 2048;
+            break;
+        case BurstSize_4096 :
+            *dataLength = 4096;
+            break;
+    }
+    *valid = True;
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_getData (
+    IN  Demodulator*    demodulator,
+    IN  Dword           bufferLength,
+    OUT Byte*           buffer
+) {
+    Dword error = Error_NO_ERROR;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    /** Get data by stream type */
+
+    //error = ganymede->dvbtStandardDescription.getData (demodulator, bufferLength, buffer);
+
+    if (bufferLength == 0) {
+        error = Error_INVALID_DATA_LENGTH;
+        goto exit;
+    }
+
+
+    /** IP datagram is locate in a special register 0xF00000 */
+    error = ganymede->cmdDescription->receiveData (demodulator, 0xF00000, bufferLength, buffer);
+    if (error) goto exit;
+
+    ganymede->dataReady = False;
+
+exit:
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+/** combine Standard_getLength and Standard_getData */
+Dword Standard_getDatagram (
+    IN  Demodulator*    demodulator,
+    OUT Dword*          bufferLength,
+    OUT Byte*           buffer
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    GetDatagramRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        request.bufferLength = bufferLength;
+        request.buffer = buffer;
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_GETDATAGRAM,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    Ganymede* ganymede;
+    Dword length = 0;
+    Byte value;
+    // Bool ready = False;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    /** Get datagram by stream type */
+
+    //error = ganymede->dvbtStandardDescription.getDatagram (demodulator, bufferLength, buffer);
+
+#if User_USE_INTERRUPT
+#else
+
+    error = Standard_readRegisterBits (demodulator, 0, Processor_LINK, r_link_ofsm_ip_valid, link_ofsm_ip_valid_pos, link_ofsm_ip_valid_len, &value);
+    if (error) goto exit;
+
+    if (value) {
+        ganymede->dataReady = True;
+    }
+    if (ganymede->dataReady == False) {
+        *bufferLength = 0;
+        error = Error_NOT_READY;
+        goto exit;
+    }
+#endif
+    switch (ganymede->burstSize) {
+        case BurstSize_1024 :
+            length = 1024;
+            break;
+        case BurstSize_2048 :
+            length = 2048;
+            break;
+        case BurstSize_4096 :
+            length = 4096;
+            break;
+    }
+    if (*bufferLength >= length) {
+        //error = Dvbt_getData (demodulator, length, (Byte*) buffer);
+        //if (error) goto exit;
+
+        if (bufferLength == 0) {
+            error = Error_INVALID_DATA_LENGTH;
+            goto exit;
+        }
+
+
+        /** IP datagram is locate in a special register 0xF00000 */
+        error = ganymede->cmdDescription->receiveData (demodulator, 0xF00000, length, buffer);
+        if (error) goto exit;
+
+        *bufferLength = length;
+
+        ganymede->dataReady = False;
+
+        *bufferLength = length;
+    } else {
+        error = Error_BUFFER_INSUFFICIENT;
+    }
+
+
+exit:
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+/** get ir raw code (4 bytes) */
+Dword Standard_getIrCode (
+    IN  Demodulator*    demodulator,
+    OUT Dword*          code
+)  {
+    Dword error = Error_NO_ERROR;
+    Byte readBuffer[4];
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    error = Standard_sendCommand (demodulator, Command_IR_GET, 0, Processor_LINK, 0, NULL, 4, readBuffer);
+    if (error) goto exit;
+
+    *code = (Dword) ((readBuffer[0] << 24) + (readBuffer[1] << 16) + (readBuffer[2] << 8) + readBuffer[3]);
+
+exit :
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_reboot (
+    IN  Demodulator*    demodulator
+)  {
+    Dword error = Error_NO_ERROR;
+    Dword version;
+    Byte i;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    error = Standard_getFirmwareVersion (demodulator, Processor_LINK, &version);
+    if (error) goto exit;
+    if (version == 0xFFFFFFFF) goto exit;       /** I2M and I2U */
+    if (version != 0) {
+        for (i = ganymede->chipNumber; i > 0; i--) {
+            error = ganymede->cmdDescription->reboot (demodulator, i - 1);
+            if (error) goto exit;
+            User_delay (demodulator, 1);
+        }
+
+        User_delay (demodulator, 10);
+
+        version = 1;
+        for (i = 0; i < 30; i++) {
+            error = Standard_getFirmwareVersion (demodulator, Processor_LINK, &version);
+            if (error == Error_NO_ERROR) break;
+            User_delay (demodulator, 10);
+        }
+        if (error) goto exit;
+        if (version != 0)
+            error = Error_REBOOT_FAIL;
+    }
+    for (i = ganymede->chipNumber; i > 0; i--) {
+        error = Standard_writeRegisterBits (demodulator, i - 1, Processor_LINK, p_reg_p_dmb_sw_reset, reg_p_dmb_sw_reset_pos, reg_p_dmb_sw_reset_len, 1);
+        if (error) goto exit;
+    }
+
+    ganymede->booted = False;
+
+exit :
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_controlPowerSaving (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            control
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    ControlPowerSavingRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        request.chip = chip;
+        request.control = control;
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_CONTROLPOWERSAVING,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    Byte temp;
+    Byte begin;
+    Byte end;
+    Byte i;
+    Byte j;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s control=%d-\n", __FUNCTION__, control);
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->architecture == Architecture_DCA) {
+        begin = 0;
+        end = ganymede->chipNumber;
+    } else {
+        begin = chip;
+        end = begin + 1;
+    }
+
+    if (control) {
+        /** Power up case */
+        if ((ganymede->busId == Bus_USB) || (ganymede->busId == Bus_USB11)) {
+            for (i = begin; i < end; i++) {
+                error = Standard_writeRegisterBits (demodulator, i, Processor_OFDM, p_reg_afe_mem0, 3, 1, 0);
+                if (error) goto exit;
+                error = Standard_writeRegister (demodulator, i, Processor_OFDM, suspend_flag, 0);
+                if (error) goto exit;
+				error = Standard_writeRegister (demodulator, i, Processor_OFDM, trigger_ofsm, 0);
+				if (error) goto exit;
+
+            }
+        } else {  /** TS, SPI, and SDIO case */
+            /** not implemented yet */
+        }
+
+        /** Fixed current leakage */
+        switch (ganymede->busId) {
+            case Bus_SPI :
+            case Bus_SDIO :
+            case Bus_USB :
+            case Bus_USB11 :
+                if (ganymede->chipNumber > 1) {
+                    for (i = 1; i < ganymede->chipNumber; i++) {
+                        /** Disable HostA parallel */
+                        error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_top_hosta_mpeg_ser_mode, reg_top_hosta_mpeg_ser_mode_pos, reg_top_hosta_mpeg_ser_mode_len, 0);
+                        if (error) goto exit;
+                        error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_top_hosta_mpeg_par_mode, reg_top_hosta_mpeg_par_mode_pos, reg_top_hosta_mpeg_par_mode_len, 0);
+                        if (error) goto exit;
+                    }
+                }
+                break;
+        }
+    } else {
+        /** Power down case */
+        if ((ganymede->busId == Bus_USB) || (ganymede->busId == Bus_USB11)) {
+            for (i = begin; i < end; i++) {
+                error = Standard_writeRegister (demodulator, i, Processor_OFDM, suspend_flag, 1);
+                if (error) goto exit;
+                error = Standard_writeRegister (demodulator, i, Processor_OFDM, trigger_ofsm, 0);
+                if (error) goto exit;
+
+                for (j = 0; j < 150; j++) {
+                    error = Standard_readRegister (demodulator, i, Processor_OFDM, suspend_flag, &temp);
+                    if (error) goto exit;
+                    if (!temp) break;
+                    User_delay (demodulator, 10);
+                }
+                error = Standard_writeRegisterBits (demodulator, i, Processor_OFDM, p_reg_afe_mem0, 3, 1, 1);
+                if (error) goto exit;
+            }
+        } else {  /** TS SPI SDIO */
+            /** not implemented yet */
+        }
+
+        /** Fixed current leakage */
+        switch (ganymede->busId) {
+            case Bus_SPI :
+            case Bus_SDIO :
+            case Bus_USB :
+            case Bus_USB11 :
+                if (ganymede->chipNumber > 1) {
+                    for (i = 1; i < ganymede->chipNumber; i++) {
+                        /** Enable HostA parallel */
+                        error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_top_hosta_mpeg_ser_mode, reg_top_hosta_mpeg_ser_mode_pos, reg_top_hosta_mpeg_ser_mode_len, 0);
+                        if (error) goto exit;
+                        error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_top_hosta_mpeg_par_mode, reg_top_hosta_mpeg_par_mode_pos, reg_top_hosta_mpeg_par_mode_len, 1);
+                        if (error) goto exit;
+                    }
+                }
+                break;
+        }
+    }
+
+exit :
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_controlTunerPowerSaving (
+    IN  Demodulator*    demodulator,
+	IN  Byte            control
+) {
+	Dword error = Error_NO_ERROR;
+
+    deb_info("Enter %s control=%d-\n", __FUNCTION__, control);
+	if (control) {
+		error = Standard_writeRegister (demodulator, 0, Processor_LINK, p_reg_top_gpioh7_en, 1);
+		if (error) goto exit;
+
+		error = Standard_writeRegister (demodulator, 0, Processor_LINK, p_reg_top_gpioh7_on, 1);
+		if (error) goto exit;
+
+		error = Standard_writeRegister (demodulator, 0, Processor_LINK, p_reg_top_gpioh7_o, 1);
+		if (error) goto exit;
+	} else {
+		error = Standard_writeRegister (demodulator, 0, Processor_LINK, p_reg_top_gpioh7_en, 1);
+		if (error) goto exit;
+
+		error = Standard_writeRegister (demodulator, 0, Processor_LINK, p_reg_top_gpioh7_on, 1);
+		if (error) goto exit;
+
+		error = Standard_writeRegister (demodulator, 0, Processor_LINK, p_reg_top_gpioh7_o, 0);
+		if (error) goto exit;
+	}
+
+exit:
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+	return (error);
+}
+
+
+Dword Standard_runCode (
+    IN  Demodulator*    demodulator,
+    IN  Word            code
+) {
+    Dword error = Error_NO_ERROR;
+    Byte writeBuffer[2];
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    writeBuffer[0] = (Byte) (code >> 8);
+    writeBuffer[1] = (Byte) code;
+    error = Standard_sendCommand (demodulator, Command_RUN_CODE, 0, Processor_LINK, 2, writeBuffer, 0, NULL);
+    if (error) goto exit;
+
+exit :
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_controlPidFilter (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            control
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    ControlPidFilterRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        request.chip = chip;
+        request.control = control;
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_CONTROLPIDFILTER,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    deb_info("Enter %s -\n", __FUNCTION__);
+    error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, p_mp2if_pid_en, mp2if_pid_en_pos, mp2if_pid_en_len, control);
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_resetPidFilter (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+#else
+    Ganymede* ganymede;
+    deb_info("Enter %s -\n", __FUNCTION__);
+
+    ganymede = (Ganymede*) demodulator;
+
+    error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, p_mp2if_pid_rst, mp2if_pid_rst_pos, mp2if_pid_rst_len, 1);
+    if (error) goto exit;
+
+exit :
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+Dword Standard_addPidToFilter (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            index,
+    IN  Pid             pid
+) {
+    Dword error = Error_NO_ERROR;
+
+#if User_USE_DRIVER
+    DWORD number;
+    BOOL result;
+    AddPidRequest request;
+    Ganymede* ganymede;
+
+    ganymede = (Ganymede*) demodulator;
+
+    if (ganymede->driver != NULL) {
+        request.chip = chip;
+        request.pid = pid;
+        result = DeviceIoControl (
+                    ganymede->driver,
+                    IOCTL_AFA_DEMOD_ADDPID,
+                    &request,
+                    sizeof (request),
+                    NULL,
+                    0,
+                    &number,
+                    NULL
+        );
+        error = request.error;
+    } else {
+        error = Error_DRIVER_INVALID;
+    }
+#else
+    Byte writeBuffer[2];
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+    /** Enable pid filter */
+    error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, p_mp2if_pid_en, mp2if_pid_en_pos, mp2if_pid_en_len, 1);
+    if (error) goto exit;
+
+    writeBuffer[0] = (Byte) pid.value;
+    writeBuffer[1] = (Byte) (pid.value >> 8);
+
+    error = Standard_writeRegisters (demodulator, chip, Processor_OFDM, p_mp2if_pid_dat_l, 2, writeBuffer);
+    if (error) goto exit;
+
+    error = Standard_writeRegisterBits (demodulator, chip, Processor_OFDM, p_mp2if_pid_index_en, mp2if_pid_index_en_pos, mp2if_pid_index_en_len, 1);
+    if (error) goto exit;
+
+    error = Standard_writeRegister (demodulator, chip, Processor_OFDM, p_mp2if_pid_index, index);
+    if (error) goto exit;
+
+exit :
+#endif
+
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_setBurstSize (
+    IN  Demodulator*    demodulator,
+    IN  BurstSize       burstSize
+) {
+    Dword error = Error_NO_ERROR;
+    Byte i;
+    Ganymede* ganymede;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    ganymede = (Ganymede*) demodulator;
+
+
+    if (burstSize == BurstSize_4096) {
+        error = Error_NOT_SUPPORT;
+        goto exit;
+    }
+
+
+    switch (burstSize) {
+        case BurstSize_1024 :
+            for (i = 0; i < ganymede->chipNumber; i++) {
+                error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_dvbt_path, reg_dvbt_path_pos, reg_dvbt_path_len, 1);
+                if (error) goto exit;
+                error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_dvbt_bufsize, reg_dvbt_bufsize_pos, reg_dvbt_bufsize_len, 1);
+                if (error) goto exit;
+            }
+            ganymede->burstSize = BurstSize_1024;
+            break;
+        case BurstSize_2048 :
+            for (i = 0; i < ganymede->chipNumber; i++) {
+                error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_dvbt_path, reg_dvbt_path_pos, reg_dvbt_path_len, 1);
+                if (error) goto exit;
+                error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_dvbt_bufsize, reg_dvbt_bufsize_pos, reg_dvbt_bufsize_len, 0);
+                if (error) goto exit;
+            }
+            ganymede->burstSize = BurstSize_2048;
+
+            break;
+        case BurstSize_4096 :
+            for (i = 0; i < ganymede->chipNumber; i++) {
+                error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_dvbt_path, reg_dvbt_path_pos, reg_dvbt_path_len, 0);
+                if (error) goto exit;
+                error = Standard_writeRegisterBits (demodulator, i, Processor_LINK, p_reg_dvbt_bufsize, reg_dvbt_bufsize_pos, reg_dvbt_bufsize_len, 1);
+                if (error) goto exit;
+            }
+            ganymede->burstSize = BurstSize_4096;
+            break;
+    }
+
+exit :
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
+
+
+Dword Standard_getBurstSize (
+    IN  Demodulator*    demodulator,
+    IN  BurstSize*      burstSize
+) {
+    Dword error = Error_NO_ERROR;
+    Byte path;
+    Byte size;
+
+    deb_info("Enter %s -\n", __FUNCTION__);
+    error = Standard_readRegisterBits (demodulator, 0, Processor_LINK, p_reg_dvbt_path, reg_dvbt_path_pos, reg_dvbt_path_len, &path);
+    if (error) goto exit;
+    error = Standard_readRegisterBits (demodulator, 0, Processor_LINK, p_reg_dvbt_bufsize, reg_dvbt_bufsize_pos, reg_dvbt_bufsize_len, &size);
+    if (error) goto exit;
+
+    if (path) {
+        if (size) {
+            *burstSize = BurstSize_1024;
+        } else {
+            *burstSize = BurstSize_2048;
+        }
+    } else {
+        if (size) {
+            *burstSize = BurstSize_4096;
+        } else {
+            *burstSize = BurstSize_2048;
+        }
+    }
+
+exit :
+    if(error) {
+	deb_info("%s error, ret=0x%x\n", __FUNCTION__, error);
+    }
+    return (error);
+}
diff --git a/drivers/media/dvb/dvb-usb/a867_standard.h b/drivers/media/dvb/dvb-usb/a867_standard.h
new file mode 100644
index 0000000..6001dbf
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_standard.h
@@ -0,0 +1,1142 @@
+#ifndef __STANDARD_H__
+#define __STANDARD_H__
+
+
+#include "a867_type.h"
+#include "a867_user.h"
+#include "a867_error.h"
+#include "a867_register.h"
+#include "a867_variable.h"
+#include "a867_version.h"
+
+#if User_USE_DRIVER
+#include <tchar.h>
+#include "iocontrol.h"
+#endif
+
+
+/**
+ * Write one byte (8 bits) to a specific register in demodulator.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param processor The processor of specified register. Because each chip
+ *        has two processor so user have to specify the processor. The
+ *        possible values are Processor_LINK and Processor_OFDM.
+ * @param registerAddress the address of the register to be written.
+ * @param value the value to be written.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_writeRegister (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            value
+);
+
+
+/**
+ * Write a sequence of bytes to the contiguous registers in demodulator.
+ * The maximum burst size is restricted by the capacity of bus. If bus
+ * could transfer N bytes in one cycle, then the maximum value of
+ * bufferLength would be N - 5.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param processor The processor of specified register. Because each chip
+ *        has two processor so user have to specify the processor. The
+ *        possible values are Processor_LINK and Processor_OFDM.
+ * @param registerAddress the start address of the registers to be written.
+ * @param bufferLength the number of registers to be written.
+ * @param buffer a byte array which is used to store values to be written.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_writeRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+);
+
+
+/**
+ * Write a collection of values to discontiguous registers in demodulator.
+ * The maximum burst size is restricted by the capacity of bus. If bus
+ * could transfer N bytes in one cycle, then the maximum value of
+ * bufferLength would be N - 6 (one more byte to specify tuner address).
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param processor The processor of specified register. Because each chip
+ *        has two processor so user have to specify the processor. The
+ *        possible values are Processor_LINK and Processor_OFDM.
+ * @param valueSetsLength the number of values to be written.
+ * @param valueSets a ValueSet array which is used to store values to be
+ *        written.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_writeScatterRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Byte            valueSetsLength,
+    IN  ValueSet*       valueSets
+);
+
+
+/**
+ * Write a sequence of bytes to the contiguous registers in slave device.
+ * The maximum burst size is restricted by the capacity of bus. If bus
+ * could transfer N bytes in one cycle, then the maximum value of
+ * bufferLength would be N - 6 (one more byte to specify tuner address).
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param registerAddress the start address of the registers to be read.
+ * @param bufferLength the number of registers to be read.
+ * @param buffer a byte array which is used to store values to be read.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_writeTunerRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Word            registerAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+);
+
+
+/**
+ * Write a sequence of bytes to the contiguous registers in slave device
+ * through specified interface (1, 2, 3).
+ * The maximum burst size is restricted by the capacity of bus. If bus
+ * could transfer N bytes in one cycle, then the maximum value of
+ * bufferLength would be N - 6 (one more byte to specify tuner address).
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param interfaceIndex the index of interface. The possible values are
+ *        1~3.
+ * @param slaveAddress the I2c address of slave device.
+ * @param bufferLength the number of registers to be read.
+ * @param buffer a byte array which is used to store values to be read.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_writeGenericRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            interfaceIndex,
+    IN  Byte            slaveAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+);
+
+
+/**
+ * Write a sequence of bytes to the contiguous cells in the EEPROM.
+ * The maximum burst size is restricted by the capacity of bus. If bus
+ * could transfer N bytes in one cycle, then the maximum value of
+ * bufferLength would be N - 5 (firmware will detect EEPROM address).
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param registerAddress the start address of the cells to be written.
+ * @param bufferLength the number of cells to be written.
+ * @param buffer a byte array which is used to store values to be written.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_writeEepromValues (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Word            registerAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+);
+
+
+/**
+ * Modify bits in the specific register.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param processor The processor of specified register. Because each chip
+ *        has two processor so user have to specify the processor. The
+ *        possible values are Processor_LINK and Processor_OFDM.
+ * @param registerAddress the address of the register to be written.
+ * @param position the start position of bits to be modified (0 means the
+ *        LSB of the specifyed register).
+ * @param length the length of bits.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_writeRegisterBits (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            position,
+    IN  Byte            length,
+    IN  Byte            value
+);
+
+
+/**
+ * Read one byte (8 bits) from a specific register in demodulator.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param processor The processor of specified register. Because each chip
+ *        has two processor so user have to specify the processor. The
+ *        possible values are Processor_LINK and Processor_OFDM.
+ * @param registerAddress the address of the register to be read.
+ * @param value the pointer used to store the value read from demodulator
+ *        register.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_readRegister (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    OUT Byte*           value
+);
+
+
+/**
+ * Read a sequence of bytes from the contiguous registers in demodulator.
+ * The maximum burst size is restricted by the capacity of bus. If bus
+ * could transfer N bytes in one cycle, then the maximum value of
+ * bufferLength would be N - 5.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param processor The processor of specified register. Because each chip
+ *        has two processor so user have to specify the processor. The
+ *        possible values are Processor_LINK and Processor_OFDM.
+ * @param registerAddress the address of the register to be read.
+ * @param bufferLength the number of registers to be read.
+ * @param buffer a byte array which is used to store values to be read.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_readRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            bufferLength,
+    OUT Byte*           buffer
+);
+
+
+/**
+ * Read a collection of values to discontiguous registers from demodulator.
+ * The maximum burst size is restricted by the capacity of bus. If bus
+ * could transfer N bytes in one cycle, then the maximum value of
+ * bufferLength would be N - 6 (one more byte to specify tuner address).
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param processor The processor of specified register. Because each chip
+ *        has two processor so user have to specify the processor. The
+ *        possible values are Processor_LINK and Processor_OFDM.
+ * @param valueSetsLength the number of values to be read.
+ * @param valueSets a ValueSet array which is used to store values to be
+ *        read.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_readScatterRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Byte            valueSetsLength,
+    OUT ValueSet*       valueSets
+);
+
+
+/**
+ * Read a sequence of bytes from the contiguous registers in tuner.
+ * The maximum burst size is restricted by the capacity of bus. If bus
+ * could transfer N bytes in one cycle, then the maximum value of
+ * bufferLength would be N - 6 (one more byte to specify tuner address).
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param registerAddress the start address of the registers to be read.
+ * @param bufferLength the number of registers to be read.
+ * @param buffer a byte array which is used to store values to be read.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_readTunerRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Word            registerAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+);
+
+
+/**
+ * Read a sequence of bytes from the contiguous registers in slave device
+ * through specified interface (1, 2, 3).
+ * The maximum burst size is restricted by the capacity of bus. If bus
+ * could transfer N bytes in one cycle, then the maximum value of
+ * bufferLength would be N - 6 (one more byte to specify tuner address).
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param interfaceIndex the index of interface. The possible values are
+ *        1~3.
+ * @param slaveAddress the I2c address of slave device.
+ * @param bufferLength the number of registers to be read.
+ * @param buffer a byte array which is used to store values to be read.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_readGenericRegisters (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            interfaceIndex,
+    IN  Byte            slaveAddress,
+    IN  Byte            bufferLength,
+    IN  Byte*           buffer
+);
+
+
+/**
+ * Read a sequence of bytes from the contiguous cells in the EEPROM.
+ * The maximum burst size is restricted by the capacity of bus. If bus
+ * could transfer N bytes in one cycle, then the maximum value of
+ * bufferLength would be N - 5 (firmware will detect EEPROM address).
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param registerAddress the start address of the cells to be read.
+ * @param registerAddressLength the valid bytes of registerAddress.
+ * @param bufferLength the number of cells to be read.
+ * @param buffer a byte array which is used to store values to be read.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_readEepromValues (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Word            registerAddress,
+    IN  Byte            bufferLength,
+    OUT Byte*           buffer
+);
+
+
+/**
+ * Read bits of the specified register.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param processor The processor of specified register. Because each chip
+ *        has two processor so user have to specify the processor. The
+ *        possible values are Processor_LINK and Processor_OFDM.
+ * @param registerAddress the address of the register to be read.
+ * @param position the start position of bits to be read (0 means the
+ *        LSB of the specifyed register).
+ * @param length the length of bits.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_readRegisterBits (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            position,
+    IN  Byte            length,
+    OUT Byte*           value
+);
+
+
+/**
+ * Send the command to device.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param command the command to be send.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param processor The processor of specified register. Because each chip
+ *        has two processor so user have to specify the processor. The
+ *        possible values are Processor_LINK and Processor_OFDM.
+ * @param writeBufferLength the number of registers to be write.
+ * @param writeBuffer a byte array which is used to store values to be write.
+ * @param readBufferLength the number of registers to be read.
+ * @param readBuffer a byte array which is used to store values to be read.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_sendCommand (
+    IN  Demodulator*    demodulator,
+    OUT Word            command,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           writeBufferLength,
+    IN  Byte*           writeBuffer,
+    IN  Dword           readBufferLength,
+    OUT Byte*           readBuffer
+);
+
+
+/**
+ * Get the version of hardware.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param version the version of hardware.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_getHardwareVersion (
+    IN  Demodulator*    demodulator,
+    OUT Dword*          version
+);
+
+
+/**
+ * Get the version of firmware.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param version the version of firmware.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_getFirmwareVersion (
+    IN  Demodulator*    demodulator,
+    IN  Processor       processor,
+    OUT Dword*          version
+);
+
+
+/**
+ * Get RF AGC gain.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param rfAgc the value of RF AGC.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_getRfAgcGain (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Byte*           rfAgc
+);
+
+
+/**
+ * Get IF AGC gain.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param ifAgc the value of IF AGC.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_getIfAgcGain (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Byte*           ifAgc
+);
+
+
+/**
+ * Load the IR table for USB device.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param tableLength The length of IR table.
+ * @param table The content of IR table.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_loadIrTable (
+    IN  Demodulator*    demodulator,
+    IN  Word            tableLength,
+    IN  Byte*           table
+);
+
+
+/**
+ * Program the bandwidth related parameters to demodulator.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7. NOTE: When the architecture is set to Architecture_DCA
+ *        this parameter is regard as don't care.
+ * @param bandwidth DVB channel bandwidth in MHz. The possible values
+ *        are 5, 6, 7, and 8 (MHz).
+ * @param adcFrequency The value of desire internal ADC frequency (Hz).
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_selectBandwidth (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Word            bandwidth,          /** KHz                 */
+    IN  Dword           adcFrequency        /** Hz, ex: 20480000    */
+);
+
+
+/**
+ * Mask DCA output.
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_maskDcaOutput (
+    IN  Demodulator*    demodulator
+);
+
+
+/**
+ * Load firmware to device
+ *
+ * @param demodulator the handle of demodulator.
+ * @streamType current stream type (useless for Ganymede).
+ * @firmwareCodes pointer to fw binary.
+ * @firmwareSegments pointer to fw segments.
+ * @firmwarePartitions pointer to fw partition (useless for Ganymede).
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_loadFirmware (
+    IN  Demodulator*    demodulator,
+    IN  Byte*           firmwareCodes,
+    IN  Segment*        firmwareSegments,
+    IN  Byte*           firmwarePartitions
+);
+
+/**
+ * First, download firmware from host to demodulator. Actually, firmware is
+ * put in firmware.h as a part of source code. Therefore, in order to
+ * update firmware the host have to re-compile the source code.
+ * Second, setting all parameters which will be need at the beginning.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chipNumber The total number of demodulators.
+ * @param sawBandwidth SAW filter bandwidth in MHz. The possible values
+ *        are 6000, 7000, and 8000 (KHz).
+ * @param streamType The format of output stream.
+ * @param architecture the architecture of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_initialize (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chipNumber,
+    IN  Word            sawBandwidth,
+    IN  StreamType      streamType,
+    IN  Architecture    architecture
+);
+
+
+/**
+ * Power off the demodulators.
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_finalize (
+    IN  Demodulator*    demodulator
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Standard_isAgcLocked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Standard_isCfoeLocked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Standard_isSfoeLocked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Standard_isTpsLocked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Standard_isMpeg2Locked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7. NOTE: When the architecture is set to Architecture_DCA
+ *        this parameter is regard as don't care.
+ * @param locked the result of frequency tuning. True if there is
+ *        demodulator can lock signal, False otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Standard_isLocked (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Bool*           locked
+);
+
+
+/**
+ * Set priorty of modulation.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param priority modulation priority.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_setPriority (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Priority        priority
+);
+
+
+/**
+ * Reset demodulator.
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_reset (
+    IN  Demodulator*    demodulator
+);
+
+
+/**
+ * Get channel modulation related information.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param channelModulation The modulation of channel.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ */
+Dword Standard_getChannelModulation (
+    IN  Demodulator*            demodulator,
+    IN  Byte                    chip,
+    OUT ChannelModulation*      channelModulation
+);
+
+
+/**
+ * Set channel modulation related information.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param channelModulation The modulation of channel.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ */
+Dword Standard_setChannelModulation (
+    IN  Demodulator*            demodulator,
+    IN  Byte                    chip,
+    IN  ChannelModulation*      channelModulation
+);
+
+
+/**
+ * Set frequency.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param frequency The desired frequency.
+ * @return Error_NO_ERROR: successful, other non-zero error code otherwise.
+ */
+Dword Standard_setFrequency (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Dword           frequency
+);
+
+
+/**
+ * Specify the bandwidth of channel and tune the channel to the specific
+ * frequency. Afterwards, host could use output parameter dvbH to determine
+ * if there is a DVB-H signal.
+ * In DVB-T mode, after calling this function the output parameter dvbH
+ * should return False and host could use output parameter "locked" to check
+ * if the channel has correct TS output.
+ * In DVB-H mode, after calling this function the output parameter dvbH should
+ * return True and host could start get platform thereafter.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7. NOTE: When the architecture is set to Architecture_DCA
+ *        this parameter is regard as don't care.
+ * @param bandwidth The channel bandwidth.
+ *        DVB-T: 5000, 6000, 7000, and 8000 (KHz).
+ *        DVB-H: 5000, 6000, 7000, and 8000 (KHz).
+ *        T-DMB: 5000, 6000, 7000, and 8000 (KHz).
+ *        FM: 100, and 200 (KHz).
+ * @param frequency the channel frequency in KHz.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_acquireChannel (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Word            bandwidth,
+    IN  Dword           frequency
+);
+
+
+
+/**
+ * Set the output stream type of chip. Because the device could output in
+ * many stream type, therefore host have to choose one type before receive
+ * data.
+ *
+ * Note: Please refer to the example of Standard_acquireChannel when host want
+ *       to detect the available channels.
+ * Note: After host know all the available channels, and want to change to
+ *       specific channel, host have to choose output mode before receive
+ *       data. Please refer the example of Standard_setStreamType.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param streamType the possible values are
+ *        DVB-H:    StreamType_DVBH_DATAGRAM
+ *                  StreamType_DVBH_DATABURST
+ *        DVB-T:    StreamType_DVBT_DATAGRAM
+ *                  StreamType_DVBT_PARALLEL
+ *                  StreamType_DVBT_SERIAL
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_setStreamType (
+    IN  Demodulator*    demodulator,
+    IN  StreamType      streamType
+);
+
+
+/**
+ * Set the architecture of chip. When two of our device are using, they could
+ * be operated in Diversity Combine Architecture (DCA) or (PIP). Therefore,
+ * host could decide which mode to be operated.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param architecture the possible values are
+ *        Architecture_DCA
+ *        Architecture_PIP
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_setArchitecture (
+    IN  Demodulator*    demodulator,
+    IN  Architecture    architecture
+);
+
+
+/**
+ * Set the counting range for Post-Viterbi and Post-Viterbi.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7. NOTE: When the architecture is set to Architecture_DCA
+ *        this parameter is regard as don't care.
+ * @param postErrorCount the number of super frame for Pre-Viterbi.
+ * @param postBitCount the number of packet unit for Post-Viterbi.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_getPostVitBer (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Dword*          postErrorCount, /** 24 bits */
+    OUT Dword*          postBitCount,   /** 16 bits */
+    OUT Word*           abortCount
+);
+
+
+/**
+ * Get siganl quality.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7. NOTE: When the architecture is set to Architecture_DCA
+ *        this parameter is regard as don't care.
+ * @param quality The value of signal quality.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_getSignalQuality (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Byte*           quality
+);
+
+
+/**
+ * Get siganl strength.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7. NOTE: When the architecture is set to Architecture_DCA
+ *        this parameter is regard as don't care.
+ * @param strength The value of signal strength.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_getSignalStrength (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Byte*           strength
+);
+
+
+/**
+ * Get signal strength in dbm
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param rfpullUpVolt_X10 the pullup voltag of RF multiply 10.
+ * @param ifpullUpVolt_X10 the pullup voltag of IF multiply 10.
+ * @param strengthDbm The value of signal strength in DBm.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_getSignalStrengthDbm (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Long            rfpullUpVolt_X10,     /** RF pull up voltage multiplied by 10   */
+    IN  Long            ifpullUpVolt_X10,     /** IF pull up voltage multiplied by 10   */
+    OUT Long*           strengthDbm           /** DBm                                   */
+);
+
+
+/**
+ * Set the counting range for Pre-Viterbi and Post-Viterbi.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7. NOTE: When the architecture is set to Architecture_DCA
+ *        this parameter is regard as don't care.
+ * @param frameCount the number of super frame for Pre-Viterbi.
+ * @param packetUnit the number of packet unit for Post-Viterbi.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_setStatisticRange (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            superFrameCount,
+    IN  Word            packetUnit
+);
+
+
+/**
+ * Get the counting range for Pre-Viterbi and Post-Viterbi.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param frameCount the number of super frame for Pre-Viterbi.
+ * @param packetUnit the number of packet unit for Post-Viterbi.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_getStatisticRange (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte*           frameCount,
+    IN  Word*           packetUnit
+);
+
+
+/**
+ * Get the statistic values of demodulator, it includes Pre-Viterbi BER,
+ * Post-Viterbi BER, Abort Count, Signal Presented Flag, Signal Locked Flag,
+ * Signal Quality, Signal Strength, Delta-T for DVB-H time slicing.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param statistic the structure that store all statistic values.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_getStatistic (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    OUT Statistic*      statistic
+);
+
+
+/**
+ * Get interrupt status.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param interrupts the type of interrupts.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_getInterrupts (
+    IN  Demodulator*    demodulator,
+    OUT Interrupts*     interrupts
+);
+
+
+/**
+ * Clear interrupt status.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param interrupt interrupt name.
+ * @param packetUnit the number of packet unit for Post-Viterbi.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_clearInterrupt (
+    IN  Demodulator*    demodulator,
+    IN  Interrupt       interrupt
+);
+
+
+/**
+ * Get data length.
+ * In DVB-T mode, data length should always equals 2K,
+ * In DVB-H mode, data length would be the length of IP datagram.
+ * NOTE: data can't be transfer via I2C bus, in order to transfer data
+ * host must provide SPI bus.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param dataLength the length of data.
+ * @param valid True if the data length is valid.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_getDataLength (
+    IN  Demodulator*    demodulator,
+    OUT Dword*          dataLength,
+    OUT Bool*           valid
+);
+
+
+/**
+ * Get DVB-T data.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param bufferLength the length of buffer.
+ * @param buffer buffer used to get Data.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_getData (
+    IN  Demodulator*    demodulator,
+    IN  Dword           bufferLength,
+    OUT Byte*           buffer
+);
+
+
+/**
+ * Get datagram from device.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param bufferLength the number of registers to be read.
+ * @param buffer a byte array which is used to store values to be read.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @return Error_BUFFER_INSUFFICIENT: if buffer is too small.
+ */
+Dword Standard_getDatagram (
+    IN  Demodulator*    demodulator,
+    OUT Dword*          bufferLength,
+    OUT Byte*           buffer
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @param code the value of IR raw code, the size should be 4 or 6,
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Standard_getIrCode (
+    IN  Demodulator*    demodulator,
+    OUT Dword*          code
+);
+
+
+/**
+ * Return to boot code
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Standard_reboot (
+    IN  Demodulator*    demodulator
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param contorl 1: Power up, 0: Power down;
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Standard_controlPowerSaving (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            control
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @param contorl 1: Power up, 0: Power down;
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Standard_controlTunerPowerSaving (
+    IN  Demodulator*    demodulator,
+    IN  Byte            control
+);
+
+
+/**
+ *
+ * @param demodulator the handle of demodulator.
+ * @param code the address of function pointer in firmware.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Standard_runCode (
+    IN  Demodulator*    demodulator,
+    IN  Word            code
+);
+
+
+/**
+ * Control PID fileter
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param contorl 0: Disable, 1: Enable.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @example <pre>
+ * </pre>
+ */
+Dword Standard_controlPidFilter (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            control
+);
+
+
+/**
+ * Reset PID filter.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_resetPidFilter (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip
+);
+
+
+/**
+ * Add PID to PID filter.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param chip The index of demodulator. The possible values are
+ *        0~7.
+ * @param pid the PID that will be add to PID filter.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+Dword Standard_addPidToFilter (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            index,
+    IN  Pid             pid
+);
+
+
+/**
+ * Set datagram burst size.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param burstSize the burst size.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @return Error_NOT_SUPPORT: if the burst size is not support.
+ */
+Dword Standard_setBurstSize (
+    IN  Demodulator*    demodulator,
+    IN  BurstSize       burstSize
+);
+
+
+/**
+ * Get datagram burst size.
+ *
+ * @param demodulator the handle of demodulator.
+ * @param burstSize the burst size.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ * @return Error_NOT_SUPPORT: if the burst size is not support.
+ */
+Dword Standard_getBurstSize (
+    IN  Demodulator*    demodulator,
+    IN  BurstSize*      burstSize
+);
+#endif
+
diff --git a/drivers/media/dvb/dvb-usb/a867_type.h b/drivers/media/dvb/dvb-usb/a867_type.h
new file mode 100644
index 0000000..d57d36e
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_type.h
@@ -0,0 +1,968 @@
+#ifndef __TYPE_H__
+#define __TYPE_H__
+
+#include <linux/module.h>
+#include "a867_userdef.h"// for Linux
+
+
+//#define IN
+//#define OUT
+//#define INOUT
+
+//j010+s
+#define TS_PACKET_COUNT 44
+//j010+e
+
+
+/**
+ * The type of handle.
+ */
+typedef void* Handle;
+
+
+/**
+ * The type defination of 8-bits unsigned type.
+ */
+typedef unsigned char Byte;
+
+
+/**
+ * The type defination of 16-bits unsigned type.
+ */
+typedef unsigned short Word;
+
+
+/**
+ * The type defination of 32-bits unsigned type.
+ */
+typedef unsigned int Dword;
+
+
+/**
+ * The type defination of 16-bits signed type.
+ */
+typedef short Short;
+
+
+/**
+ * The type defination of 32-bits signed type.
+ */
+typedef int Long;
+
+
+
+#include "a867_inttype.h"        /** release1remove */
+
+/**
+ * The type defination of Bool
+ */
+typedef enum {
+    False = 0,
+    True = 1
+} Bool;
+
+
+/**
+ * The type defination of Segment
+ */
+typedef struct {
+    Byte segmentType;           /** 0:Firmware download 1:Rom copy 2:Direct command */
+    Dword segmentLength;
+} Segment;
+
+
+/**
+ * The type defination of Bandwidth.
+ */
+typedef enum {
+    Bandwidth_6M = 0,           /** Signal bandwidth is 6MHz */
+    Bandwidth_7M,               /** Signal bandwidth is 7MHz */
+    Bandwidth_8M,               /** Signal bandwidth is 8MHz */
+    Bandwidth_5M                /** Signal bandwidth is 5MHz */
+} Bandwidth;
+
+
+/**
+ * The type defination of TransmissionMode.
+ */
+typedef enum {
+    TransmissionMode_2K = 0,    /** OFDM frame consists of 2048 different carriers (2K FFT mode) */
+    TransmissionMode_8K = 1,    /** OFDM frame consists of 8192 different carriers (8K FFT mode) */
+    TransmissionMode_4K = 2     /** OFDM frame consists of 4096 different carriers (4K FFT mode) */
+} TransmissionModes;
+
+
+/**
+ * The type defination of Constellation.
+ */
+typedef enum {
+    Constellation_QPSK = 0,     /** Signal uses QPSK constellation  */
+    Constellation_16QAM,        /** Signal uses 16QAM constellation */
+    Constellation_64QAM         /** Signal uses 64QAM constellation */
+} Constellation;
+
+
+/**
+ * The type defination of Interval.
+ */
+typedef enum {
+    Interval_1_OVER_32 = 0,     /** Guard interval is 1/32 of symbol length */
+    Interval_1_OVER_16,         /** Guard interval is 1/16 of symbol length */
+    Interval_1_OVER_8,          /** Guard interval is 1/8 of symbol length  */
+    Interval_1_OVER_4           /** Guard interval is 1/4 of symbol length  */
+} Interval;
+
+
+/**
+ * The type defination of Priority.
+ */
+typedef enum {
+    Priority_HIGH = 0,          /** DVB-T and DVB-H - identifies high-priority stream */
+    Priority_LOW                /** DVB-T and DVB-H - identifies low-priority stream  */
+} Priority;
+
+
+/**
+ * The type defination of CodeRate.
+ */
+typedef enum {
+    CodeRate_1_OVER_2 = 0,      /** Signal uses FEC coding ratio of 1/2 */
+    CodeRate_2_OVER_3,          /** Signal uses FEC coding ratio of 2/3 */
+    CodeRate_3_OVER_4,          /** Signal uses FEC coding ratio of 3/4 */
+    CodeRate_5_OVER_6,          /** Signal uses FEC coding ratio of 5/6 */
+    CodeRate_7_OVER_8,          /** Signal uses FEC coding ratio of 7/8 */
+    CodeRate_NONE               /** None, NXT doesn't have this one     */
+} CodeRate;
+
+
+/**
+ * TPS Hierarchy and Alpha value.
+ */
+typedef enum {
+    Hierarchy_NONE = 0,         /** Signal is non-hierarchical        */
+    Hierarchy_ALPHA_1,          /** Signalling format uses alpha of 1 */
+    Hierarchy_ALPHA_2,          /** Signalling format uses alpha of 2 */
+    Hierarchy_ALPHA_4           /** Signalling format uses alpha of 4 */
+} Hierarchy;
+
+
+/**
+ * The defination of SubchannelType.
+ */
+typedef enum {
+    SubchannelType_AUDIO = 0,           /** Signal in subchannel is audio format          */
+    SubchannelType_VIDEO = 1,           /** Signal in subchannel is video format          */
+    SubchannelType_PACKET = 3,          /** Signal in subchannel is packet format         */
+    SubchannelType_ENHANCEPACKET = 4    /** Signal in subchannel is enhance packet format */
+} SubchannelType;
+
+
+/**
+ * The defination of ProtectionLevel.
+ */
+typedef enum {
+    ProtectionLevel_NONE = 0x00,    /** The protection level of subchannel is none     */
+    ProtectionLevel_PL1 = 0x01,     /** The protection level of subchannel is level 1  */
+    ProtectionLevel_PL2 = 0x02,     /** The protection level of subchannel is level 2  */
+    ProtectionLevel_PL3 = 0x03,     /** The protection level of subchannel is level 3  */
+    ProtectionLevel_PL4 = 0x04,     /** The protection level of subchannel is level 4  */
+    ProtectionLevel_PL5 = 0x05,     /** The protection level of subchannel is level 5  */
+    ProtectionLevel_PL1A = 0x1A,    /** The protection level of subchannel is level 1A */
+    ProtectionLevel_PL2A = 0x2A,    /** The protection level of subchannel is level 2A */
+    ProtectionLevel_PL3A = 0x3A,    /** The protection level of subchannel is level 3A */
+    ProtectionLevel_PL4A = 0x4A,    /** The protection level of subchannel is level 4A */
+    ProtectionLevel_PL1B = 0x1B,    /** The protection level of subchannel is level 1B */
+    ProtectionLevel_PL2B = 0x2B,    /** The protection level of subchannel is level 2B */
+    ProtectionLevel_PL3B = 0x3B,    /** The protection level of subchannel is level 3B */
+    ProtectionLevel_PL4B = 0x4B     /** The protection level of subchannel is level 4B */
+} ProtectionLevel;
+
+
+/**
+ * The defination of ChannelInformation.
+ */
+typedef struct {
+    Dword frequency;                    /** Channel frequency in KHz.                                */
+    TransmissionModes transmissionMode; /** Number of carriers used for OFDM signal                  */
+    Constellation constellation;        /** Constellation scheme (FFT mode) in use                   */
+    Interval interval;                  /** Fraction of symbol length used as guard (Guard Interval) */
+    Priority priority;                  /** The priority of stream                                   */
+    CodeRate highCodeRate;              /** FEC coding ratio of high-priority stream                 */
+    CodeRate lowCodeRate;               /** FEC coding ratio of low-priority stream                  */
+    Hierarchy hierarchy;                /** Hierarchy levels of OFDM signal                          */
+    Bandwidth bandwidth;
+} ChannelModulation;
+
+
+/**
+ * The defination of SubchannelModulation. This structure is used to
+ * represent subchannel modulation when device is operate in T-DMB/DAB mode.
+ *
+ */
+typedef struct {
+    Byte subchannelId;                  /** The ID of subchannel.                                                 */
+    Word subchannelSize;                /** The size of subchannel.                                               */
+    Word bitRate;                       /** The bit rate of subchannel.                                           */
+    Byte transmissionMode;              /** The transmission mode of subchannel, possible values are: 1, 2, 3, 4. */
+    ProtectionLevel protectionLevel;    /** The protection level of subchannel.                                   */
+    SubchannelType subchannelType;      /** The type of subchannel                                                */
+    Byte conditionalAccess;             /** If a conditional access exist                                         */
+    Byte tiiPrimary;                    /** TII primary                                                           */
+    Byte tiiCombination;                /** TII combination                                                       */
+} SubchannelModulation;
+
+
+/**
+ * The type defination of IpVersion.
+ */
+typedef enum {
+    IpVersion_IPV4 = 0,         /** The IP version if IPv4 */
+    IpVersion_IPV6 = 1          /** The IP version if IPv6 */
+} IpVersion;
+
+
+/**
+ * The type defination of Ip.
+ */
+typedef struct {
+    IpVersion version;          /** The version of IP. See the defination of IpVersion.                                               */
+    Priority priority;          /** The priority of IP. See the defination of Priority.                                               */
+    Bool cache;                 /** True: IP datagram will be cached in device's buffer. Fasle: IP datagram will be transfer to host. */
+    Byte address[16];           /** The byte array to store IP address.                                                               */
+} Ip;
+
+
+/**
+ * The type defination of Platform.
+ * Mostly used is in DVB-H standard
+ */
+typedef struct {
+    Dword platformId;           /** The ID of platform.                                    */
+    char iso639LanguageCode[3]; /** The ISO 639 language code for platform name.           */
+    Byte platformNameLength;    /** The length of platform name.                           */
+    char platformName[32];      /** The char array to store platform name.                 */
+    Word bandwidth;             /** The operating channel bandwith of this platform.       */
+    Dword frequency;            /** The operating channel frequency of this platform.      */
+    Byte* information;          /** The extra information about this platform.             */
+    Word informationLength;     /** The length of information.                             */
+    Bool hasInformation;        /** The flag to indicate if there exist extra information. */
+    IpVersion ipVersion;        /** The IP version of this platform.                       */
+} Platform;
+
+
+/**
+ * The type defination of Label.
+ */
+typedef struct {
+    Byte charSet;
+    Word charFlag;
+    Byte string[16];
+} Label;
+
+
+/**
+ * The type defination of Ensemble.
+ */
+typedef struct {
+    Word ensembleId;
+    Label ensembleLabel;
+    Byte totalServices;
+} Ensemble;
+
+
+/**
+ * The type defination of Service.
+ * Mostly used is in T-DMB standard
+ */
+typedef struct {
+    Byte serviceType;       /** Service Type(P/D): 0x00: Program, 0x80: Data */
+    Dword serviceId;
+    Dword frequency;
+    Label serviceLabel;
+    Byte totalComponents;
+} Service;
+
+
+/**
+ * The type defination of Service Component.
+ */
+typedef struct {
+    Byte serviceType;           /** Service Type(P/D): 0x00: Program, 0x80: Data         */
+    Dword serviceId;            /** Service ID                                           */
+    Word componentId;           /** Stream audio/data is subchid, packet mode is SCId    */
+    Byte componentIdService;    /** Component ID within Service                          */
+    Label componentLabel;       /** The label of component. See the defination of Label. */
+    Byte language;              /** Language code                                        */
+    Byte primary;               /** Primary/Secondary                                    */
+    Byte conditionalAccess;     /** Conditional Access flag                              */
+    Byte componentType;         /** Component Type (A/D)                                 */
+    Byte transmissionId;        /** Transmission Mechanism ID                            */
+} Component;
+
+
+/**
+ * The type defination of Target.
+ */
+typedef enum {
+    SectionType_MPE = 0,        /** Stands for MPE data.                                         */
+    SectionType_SIPSI,          /** Stands for SI/PSI table, but don't have to specify table ID. */
+    SectionType_TABLE           /** Stands for SI/PSI table.                                     */
+} SectionType;
+
+
+/**
+ * The type defination of FrameRow.
+ */
+typedef enum {
+    FrameRow_256 = 0,           /** There should be 256 rows for each column in MPE-FEC frame.  */
+    FrameRow_512,               /** There should be 512 rows for each column in MPE-FEC frame.  */
+    FrameRow_768,               /** There should be 768 rows for each column in MPE-FEC frame.  */
+    FrameRow_1024               /** There should be 1024 rows for each column in MPE-FEC frame. */
+} FrameRow;
+
+
+/**
+ * The type defination of Pid.
+ *
+ * In DVB-T mode, only value is valid. In DVB-H mode,
+ * as sectionType = SectionType_SIPSI: only value is valid.
+ * as sectionType = SectionType_TABLE: both value and table is valid.
+ * as sectionType = SectionType_MPE: except table all other fields is valid.
+ */
+typedef struct {
+    Byte table;                 /** The table ID. Which is used to filter specific SI/PSI table.                                  */
+    Byte duration;              /** The maximum burst duration. It can be specify to 0xFF if user don't know the exact value.     */
+    FrameRow frameRow;          /** The frame row of MPE-FEC. It means the exact number of rows for each column in MPE-FEC frame. */
+    SectionType sectionType;    /** The section type of pid. See the defination of SectionType.                                   */
+    Priority priority;          /** The priority of MPE data. Only valid when sectionType is set to SectionType_MPE.              */
+    IpVersion version;          /** The IP version of MPE data. Only valid when sectionType is set to SectionType_MPE.            */
+    Bool cache;                 /** True: MPE data will be cached in device's buffer. Fasle: MPE will be transfer to host.        */
+    Word value;                 /** The 13 bits Packet ID.                                                                        */
+} Pid;
+
+
+/**
+ * The type defination of ValueSet.
+ */
+typedef struct {
+    Dword address;      /** The address of target register */
+    Byte value;         /** The value of target register   */
+} ValueSet;
+
+
+/**
+ * The type defination of Datetime.
+ */
+typedef struct {
+    Dword mjd;              /** The mjd of datetime           */
+    Byte configuration;     /** The configuration of datetime */
+    Byte hours;             /** The hours of datetime         */
+    Byte minutes;           /** The minutes of datetime       */
+    Byte seconds;           /** The seconds of datetime       */
+    Word milliseconds;      /** The milli seconds of datetime */
+} Datetime;
+
+
+/**
+ * The type defination of Interrupts.
+ */
+typedef Word Interrupts;
+
+
+/**
+ * The type defination of Interrupt.
+ */
+typedef enum {
+    Interrupt_NONE      = 0x0000,   /** No interrupt. */
+    Interrupt_SIPSI     = 0x0001,
+    Interrupt_DVBH      = 0x0002,
+    Interrupt_DVBT      = 0x0004,
+    Interrupt_PLATFORM  = 0x0008,
+    Interrupt_VERSION   = 0x0010,
+    Interrupt_FREQUENCY = 0x0020,
+    Interrupt_SOFTWARE1 = 0x0040,
+    Interrupt_SOFTWARE2 = 0x0080,
+    Interrupt_FIC       = 0x0100,
+    Interrupt_MSC       = 0x0200,
+    Interrupt_MCISI     = 0x0400
+} Interrupt;
+
+
+/**
+ * The type defination of Multiplier.
+ */
+typedef enum {
+    Multiplier_1X = 0,
+    Multiplier_2X
+} Multiplier;
+
+
+/**
+ * The type defination of StreamType.
+ */
+typedef enum {
+    StreamType_NONE = 0,        /** Invalid (Null) StreamType                */
+    StreamType_DVBT_DATAGRAM,   /** DVB-T mode, store data in device buffer  */
+    StreamType_DVBT_PARALLEL,   /** DVB-T mode, output via paralle interface */
+    StreamType_DVBT_SERIAL,     /** DVB-T mode, output via serial interface  */
+} StreamType;
+
+
+/**
+ * The type defination of StreamType.
+ */
+typedef enum {
+    Architecture_NONE = 0,      /** Inavalid (Null) Architecture.                                    */
+    Architecture_DCA,           /** Diversity combine architecture. Only valid when chip number > 1. */
+    Architecture_PIP            /** Picture in picture. Only valid when chip number > 1.             */
+} Architecture;
+
+
+/**
+ * The type defination of ClockTable.
+ */
+typedef struct {
+    Dword crystalFrequency;     /** The frequency of crystal. */
+    Dword adcFrequency;         /** The frequency of ADC.     */
+} ClockTable;
+
+
+/**
+ * The type defination of BandTable.
+ */
+typedef struct {
+    Dword minimum;          /** The minimum frequency of this band */
+    Dword maximum;          /** The maximum frequency of this band */
+} BandTable;
+
+
+/**
+ * The type defination of MeanTable.
+ */
+typedef struct {
+    Dword mean;
+    Dword errorCount;
+} MeanTable;
+
+
+/**
+ * The type defination of Polarity.
+ */
+typedef enum {
+    Polarity_NORMAL = 0,
+    Polarity_INVERSE
+} Polarity;
+
+
+/**
+ * The type defination of Processor.
+ */
+typedef enum {
+    Processor_LINK = 0,
+    Processor_OFDM = 8
+} Processor;
+
+
+/**
+ * The type defination of BurstSize.
+ */
+typedef enum {
+    BurstSize_1024 = 0,
+    BurstSize_2048,
+    BurstSize_4096
+} BurstSize;
+
+
+/**
+ * The type defination of Demodulator.
+ */
+typedef struct {
+    Handle userData;
+    Handle driver;
+} Demodulator;
+
+
+#include "a867_user.h"
+
+
+/**
+ * The type defination of Statistic.
+ */
+typedef struct {
+    Bool signalPresented;       /** Signal is presented.                                                                         */
+    Bool signalLocked;          /** Signal is locked.                                                                            */
+    Byte signalQuality;         /** Signal quality, from 0 (poor) to 100 (good).                                                 */
+    Byte signalStrength;        /** Signal strength from 0 (weak) to 100 (strong).                                               */
+    Byte frameErrorRatio;       /** Frame Error Ratio (error ratio before MPE-FEC), from 0 (no error) to 100 (all error).        */
+    Byte mpefecFrameErrorRatio; /** MPE-FEC Frame Error Ratio (error ratio after MPE-FEC). from 0 (no error) to 100 (all error). */
+} Statistic;
+
+
+/**
+ * General demodulator register-write function
+ *
+ * @param demodulator the handle of demodulator.
+ * @param registerAddress address of register to be written.
+ * @param bufferLength number, 1-8, of registers to be written.
+ * @param buffer buffer used to store values to be written to specified
+ *        registers.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+typedef Dword (*WriteRegisters) (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            registerAddressLength,
+    IN  Dword           writeBufferLength,
+    IN  Byte*           writeBuffer
+);
+
+
+/**
+ * General demodulator register-read function
+ *
+ * @param demodulator the handle of demodulator.
+ * @param registerAddress address of register to be read.
+ * @param bufferLength number, 1-8, of registers to be read.
+ * @param buffer buffer used to store values to be read to specified
+ *        registers.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+typedef Dword (*WriteScatterRegisters) (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Byte            valueSetsAddressLength,
+    IN  Byte            valueSetsLength,
+    IN  ValueSet*       valueSets
+);
+
+
+/**
+ * General tuner register-write function
+ *
+ * @param demodulator the handle of demodulator.
+ * @param registerAddress address of register to be written.
+ * @param bufferLength number, 1-8, of registers to be written.
+ * @param buffer buffer used to store values to be written to specified
+ *        registers.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+typedef Dword (*WriteTunerRegisters) (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            tunerAddress,
+    IN  Word            registerAddress,
+    IN  Byte            registerAddressLength,
+    IN  Byte            writeBufferLength,
+    IN  Byte*           writeBuffer
+);
+
+
+/**
+ * General write EEPROM function
+ *
+ * @param demodulator the handle of demodulator.
+ * @param registerAddress address of register to be read.
+ * @param bufferLength number, 1-8, of registers to be written.
+ * @param buffer buffer used to store values to be written to specified
+ *        registers.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+typedef Dword (*WriteEepromValues) (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            eepromAddress,
+    IN  Word            registerAddress,
+    IN  Byte            registerAddressLength,
+    IN  Byte            writeBufferLength,
+    IN  Byte*           writeBuffer
+);
+
+
+/**
+ * General demodulator register-read function
+ *
+ * @param demodulator the handle of demodulator.
+ * @param registerAddress address of register to be read.
+ * @param bufferLength number, 1-8, of registers to be read.
+ * @param buffer buffer used to store values to be read to specified
+ *        registers.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+typedef Dword (*ReadRegisters) (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            registerAddressLength,
+    IN  Dword           readBufferLength,
+    OUT Byte*           readBuffer
+);
+
+
+/**
+ * General demodulator register-read function
+ *
+ * @param demodulator the handle of demodulator.
+ * @param registerAddress address of register to be read.
+ * @param bufferLength number, 1-8, of registers to be read.
+ * @param buffer buffer used to store values to be read to specified
+ *        registers.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+typedef Dword (*ReadScatterRegisters) (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Byte            valueSetsAddressLength,
+    IN  Byte            valueSetsLength,
+    OUT ValueSet*       valueSets
+);
+
+
+/**
+ * General tuner register-read function
+ *
+ * @param demodulator the handle of demodulator.
+ * @param registerAddress address of register to be read.
+ * @param bufferLength number, 1-8, of registers to be read.
+ * @param buffer buffer used to store values to be read to specified
+ *        registers.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+typedef Dword (*ReadTunerRegisters) (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            tunerAddress,
+    IN  Word            registerAddress,
+    IN  Byte            registerAddressLength,
+    IN  Byte            readBufferLength,
+    IN  Byte*           readBuffer
+);
+
+
+/**
+ * General read EEPROM function
+ *
+ * @param demodulator the handle of demodulator.
+ * @param registerAddress address of register to be read.
+ * @param bufferLength number, 1-8, of registers to be read.
+ * @param buffer buffer used to store values to be read to specified
+ *        registers.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+typedef Dword (*ReadEepromValues) (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Byte            eepromAddress,
+    IN  Word            registerAddress,
+    IN  Byte            registerAddressLength,
+    IN  Byte            readBufferLength,
+    OUT Byte*           readBuffer
+);
+
+
+/**
+ * General demodulator register-read function
+ *
+ * @param demodulator the handle of demodulator.
+ * @param registerAddress address of register to be read.
+ * @param bufferLength number, 1-8, of registers to be read.
+ * @param buffer buffer used to store values to be read to specified
+ *        registers.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+typedef Dword (*ModifyRegister) (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           registerAddress,
+    IN  Byte            registerAddressLength,
+    IN  Byte            position,
+    IN  Byte            length,
+    IN  Byte            value
+);
+
+
+/**
+ * General load firmware function
+ *
+ * @param demodulator the handle of demodulator.
+ * @param length The length of firmware.
+ * @param firmware The byte array of firmware.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+typedef Dword (*LoadFirmware) (
+    IN  Demodulator*    demodulator,
+    IN  Dword           firmwareLength,
+    IN  Byte*           firmware
+);
+
+
+/**
+ * General reboot function
+ *
+ * @param demodulator the handle of demodulator.
+ * @param length The length of firmware.
+ * @param firmware The byte array of firmware.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+typedef Dword (*Reboot) (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip
+);
+
+
+/**
+ * Find and Get bus handle used to control bus
+ *
+ * @param demodulator the handle of demodulator.
+ * @param handle The bus handle.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+typedef Dword (*GetBus) (
+    IN  Demodulator*    demodulator,
+    OUT Handle*         handle
+);
+
+
+/**
+ * Find and Get bus handle used to control bus
+ *
+ * @param demodulator the handle of demodulator.
+ * @param bufferLength The length to transmit.
+ * @param buffer The buffer which we store the data to send.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+typedef Dword (*BusTx) (
+    IN  Demodulator*    demodulator,
+    IN  Dword           bufferLength,
+    IN  Byte*           buffer
+);
+
+
+/**
+ * Find and Get bus handle used to control bus
+ *
+ * @param demodulator the handle of demodulator.
+ * @param bufferLength The length to transmit.
+ * @param buffer The buffer which we store the data to send.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+typedef Dword (*BusRx) (
+    IN  Demodulator*    demodulator,
+    IN  Dword           bufferLength,
+    IN  Byte*           buffer
+);
+
+
+/**
+ * Find and Get bus handle used to control bus
+ *
+ * @param demodulator the handle of demodulator.
+ * @param registerAddress The starting address of memory to get.
+ * @param readBufferLength The length of buffer to receive data.
+ * @param readBuffer The buffer use to store received data
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+typedef Dword (*BusRxData) (
+    IN  Demodulator*    demodulator,
+    IN  Dword           readBufferLength,
+    OUT Byte*           readBuffer
+);
+
+/**
+ * General send command function
+ *
+ * @param demodulator the handle of demodulator.
+ * @param command The command which you wan.
+ * @param valueLength value length.
+ * @param valueBuffer value buffer.
+ * @param referenceLength reference length.
+ * @param referenceBuffer reference buffer.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+typedef Dword (*SendCommand) (
+    IN  Demodulator*    demodulator,
+    IN  Word            command,
+    IN  Byte            chip,
+    IN  Processor       processor,
+    IN  Dword           writeBufferLength,
+    IN  Byte*           writeBuffer,
+    IN  Dword           readBufferLength,
+    OUT Byte*           readBuffer
+);
+
+
+/**
+ * General read EEPROM function
+ *
+ * @param demodulator the handle of demodulator.
+ * @param registerAddress address of register to be read.
+ * @param bufferLength number, 1-8, of registers to be read.
+ * @param buffer buffer used to store values to be read to specified
+ *        registers.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+typedef Dword (*ReceiveData) (
+    IN  Demodulator*    demodulator,
+    IN  Dword           registerAddress,
+    IN  Dword           readBufferLength,
+    OUT Byte*           readBuffer
+);
+
+
+/**
+ * The type defination of BusDescription
+ */
+typedef struct {
+    GetBus              getBus;
+    BusTx               busTx;
+    BusRx               busRx;
+    BusRxData           busRxData;
+} BusDescription;
+
+
+/**
+ * The type defination of BusDescription
+ */
+typedef struct {
+    Dword                   mailBoxSize;
+    BusDescription*         busDescription;
+    WriteRegisters          writeRegisters;
+    WriteScatterRegisters   writeScatterRegisters;
+    WriteTunerRegisters     writeTunerRegisters;
+    WriteEepromValues       writeEepromValues;
+    ReadRegisters           readRegisters;
+    ReadScatterRegisters    readScatterRegisters;
+    ReadTunerRegisters      readTunerRegisters;
+    ReadEepromValues        readEepromValues;
+    ModifyRegister          modifyRegister;
+    LoadFirmware            loadFirmware;
+    Reboot                  reboot;
+    SendCommand             sendCommand;
+    ReceiveData             receiveData;
+} CmdDescription;
+
+
+/**
+ * General tuner opening function
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+typedef Dword (*OpenTuner) (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip
+);
+
+
+/**
+ * General tuner closing function
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+typedef Dword (*CloseTuner) (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip
+);
+
+
+/**
+ * General tuner setting function
+ *
+ * @param demodulator the handle of demodulator.
+ * @return Error_NO_ERROR: successful, non-zero error code otherwise.
+ */
+typedef Dword (*SetTuner) (
+    IN  Demodulator*    demodulator,
+    IN  Byte            chip,
+    IN  Word            bandwidth,
+    IN  Dword           frequency
+);
+
+
+/**
+ * The type defination of TunerDescription
+ */
+typedef struct {
+    OpenTuner       openTuner;
+    CloseTuner      closeTuner;
+    SetTuner        setTuner;
+    ValueSet*       tunerScript;
+    Word*           tunerScriptSets;
+    Byte            tunerAddress;
+    Byte            registerAddressLength;
+    Dword           ifFrequency;
+    Bool            inversion;
+    Word			tunerId;
+} TunerDescription;
+
+
+/**
+ * The data structure of DefaultDemodulator
+ */
+typedef struct {
+    /** Basic structure */
+    Handle userData;
+    Handle driver;
+    Dword options;
+    Word busId;
+    CmdDescription* cmdDescription;
+    Word tunerId;
+    TunerDescription *tunerDescription;
+} DefaultDemodulator;
+
+
+/**
+ * The data structure of Ganymede
+ */
+typedef struct {
+    /** Basic structure */
+    Handle userData;
+    Handle driver;
+    Dword options;
+    Word busId;
+    CmdDescription* cmdDescription;
+    TunerDescription *tunerDescription;
+    Byte* firmwareCodes;
+    Segment* firmwareSegments;
+    Byte* firmwarePartitions;
+    Word* scriptSets;
+    ValueSet* scripts;
+    Word* tunerScriptSets;
+    ValueSet* tunerScripts;
+    Byte chipNumber;
+    Dword crystalFrequency;
+    Dword adcFrequency;
+    StreamType streamType;
+    Architecture architecture;
+    Word bandwidth[2];
+    Dword frequency[2];
+    Dword fcw;
+    Statistic statistic[2];
+    ChannelStatistic channelStatistic[2];   /** release1remove */
+    Byte hostInterface[2];
+    Bool booted;
+    Bool initialized;
+
+    /** DVB-T structure */
+    Bool dataReady;
+    BurstSize burstSize;
+
+    Byte GPIO8Value[2];
+} Ganymede;
+
+
+extern const Byte Standard_bitMask[8];
+#define REG_MASK(pos, len)                (Standard_bitMask[len-1] << pos)
+#define REG_CLEAR(temp, pos, len)         (temp & (~REG_MASK(pos, len)))
+#define REG_CREATE(val, temp, pos, len)   ((val << pos) | (REG_CLEAR(temp, pos, len)))
+#define REG_GET(value, pos, len)          ((value & REG_MASK(pos, len)) >> pos)
+#define LOWBYTE(w)      ((Byte)((w) & 0xff))
+#define HIGHBYTE(w)     ((Byte)((w >> 8) & 0xff))
+
+#endif
diff --git a/drivers/media/dvb/dvb-usb/a867_usb-urb.c b/drivers/media/dvb/dvb-usb/a867_usb-urb.c
new file mode 100644
index 0000000..5caec20
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_usb-urb.c
@@ -0,0 +1,247 @@
+/* usb-urb.c is part of the DVB USB library.
+ *
+ * Copyright (C) 2004-6 Patrick Boettcher (patrick.boettcher@desy.de)
+ * see dvb-usb-init.c for copyright information.
+ *
+ * This file keeps functions for initializing and handling the
+ * BULK and ISOC USB data transfers in a generic way.
+ * Can be used for DVB-only and also, that's the plan, for
+ * Hybrid USB devices (analog and DVB).
+ */
+#include "dvb-usb-common.h"
+
+/* URB stuff for streaming */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
+static void usb_urb_complete(struct urb *urb, struct pt_regs *ptregs)
+#else
+static void usb_urb_complete(struct urb *urb)
+#endif
+{
+	struct usb_data_stream *stream = urb->context;
+	int ptype = usb_pipetype(urb->pipe);
+	int i;
+	u8 *b;
+
+	deb_uxfer("'%s' urb completed. status: %d, length: %d/%d, pack_num: %d, errors: %d\n",
+		ptype == PIPE_ISOCHRONOUS ? "isoc" : "bulk",
+		urb->status,urb->actual_length,urb->transfer_buffer_length,
+		urb->number_of_packets,urb->error_count);
+
+	switch (urb->status) {
+		case 0:         /* success */
+		case -ETIMEDOUT:    /* NAK */
+			break;
+		case -ECONNRESET:   /* kill */
+		case -ENOENT:
+		case -ESHUTDOWN:
+			return;
+		default:        /* error */
+			deb_ts("urb completition error %d.\n", urb->status);
+			break;
+	}
+
+	b = (u8 *) urb->transfer_buffer;
+	switch (ptype) {
+		case PIPE_ISOCHRONOUS:
+			for (i = 0; i < urb->number_of_packets; i++) {
+
+				if (urb->iso_frame_desc[i].status != 0)
+					deb_ts("iso frame descriptor has an error: %d\n",urb->iso_frame_desc[i].status);
+				else if (urb->iso_frame_desc[i].actual_length > 0)
+					stream->complete(stream, b + urb->iso_frame_desc[i].offset, urb->iso_frame_desc[i].actual_length);
+
+				urb->iso_frame_desc[i].status = 0;
+				urb->iso_frame_desc[i].actual_length = 0;
+			}
+			debug_dump(b,20,deb_uxfer);
+			break;
+		case PIPE_BULK:
+			if (urb->actual_length > 0)
+				stream->complete(stream, b, urb->actual_length);
+			break;
+		default:
+			err("unkown endpoint type in completition handler.");
+			return;
+	}
+	usb_submit_urb(urb,GFP_ATOMIC);
+}
+
+int usb_urb_kill(struct usb_data_stream *stream)
+{
+	int i;
+	for (i = 0; i < stream->urbs_submitted; i++) {
+		deb_ts("killing URB no. %d.\n",i);
+
+		/* stop the URB */
+		usb_kill_urb(stream->urb_list[i]);
+	}
+	stream->urbs_submitted = 0;
+	return 0;
+}
+
+int usb_urb_submit(struct usb_data_stream *stream)
+{
+	int i,ret;
+	for (i = 0; i < stream->urbs_initialized; i++) {
+		deb_ts("submitting URB no. %d\n",i);
+		if ((ret = usb_submit_urb(stream->urb_list[i],GFP_ATOMIC))) {
+			err("could not submit URB no. %d - get them all back",i);
+			usb_urb_kill(stream);
+			return ret;
+		}
+		stream->urbs_submitted++;
+	}
+	return 0;
+}
+
+static int usb_free_stream_buffers(struct usb_data_stream *stream)
+{
+	if (stream->state & USB_STATE_URB_BUF) {
+		while (stream->buf_num) {
+			stream->buf_num--;
+			deb_mem("freeing buffer %d\n",stream->buf_num);
+			usb_buffer_free(stream->udev, stream->buf_size,
+					stream->buf_list[stream->buf_num], stream->dma_addr[stream->buf_num]);
+		}
+	}
+
+	stream->state &= ~USB_STATE_URB_BUF;
+
+	return 0;
+}
+
+static int usb_allocate_stream_buffers(struct usb_data_stream *stream, int num, unsigned long size)
+{
+	stream->buf_num = 0;
+	stream->buf_size = size;
+
+	deb_mem("all in all I will use %lu bytes for streaming\n",num*size);
+
+	for (stream->buf_num = 0; stream->buf_num < num; stream->buf_num++) {
+		deb_mem("allocating buffer %d\n",stream->buf_num);
+		if (( stream->buf_list[stream->buf_num] =
+					usb_buffer_alloc(stream->udev, size, GFP_ATOMIC,
+					&stream->dma_addr[stream->buf_num]) ) == NULL) {
+			deb_mem("not enough memory for urb-buffer allocation.\n");
+			usb_free_stream_buffers(stream);
+			return -ENOMEM;
+		}
+		deb_mem("buffer %d: %p (dma: %Lu)\n",
+			stream->buf_num,
+stream->buf_list[stream->buf_num], (long long)stream->dma_addr[stream->buf_num]);
+		memset(stream->buf_list[stream->buf_num],0,size);
+		stream->state |= USB_STATE_URB_BUF;
+	}
+	deb_mem("allocation successful\n");
+
+	return 0;
+}
+
+static int usb_bulk_urb_init(struct usb_data_stream *stream)
+{
+	int i;
+
+	if ((i = usb_allocate_stream_buffers(stream,stream->props.count,
+					stream->props.u.bulk.buffersize)) < 0)
+		return i;
+
+	/* allocate the URBs */
+	for (i = 0; i < stream->props.count; i++) {
+		if ((stream->urb_list[i] = usb_alloc_urb(0,GFP_ATOMIC)) == NULL)
+			return -ENOMEM;
+
+		usb_fill_bulk_urb( stream->urb_list[i], stream->udev,
+				usb_rcvbulkpipe(stream->udev,stream->props.endpoint),
+				stream->buf_list[i],
+				stream->props.u.bulk.buffersize,
+				usb_urb_complete, stream);
+
+		stream->urb_list[i]->transfer_flags = 0;
+		stream->urbs_initialized++;
+	}
+	return 0;
+}
+
+static int usb_isoc_urb_init(struct usb_data_stream *stream)
+{
+	int i,j;
+
+	if ((i = usb_allocate_stream_buffers(stream,stream->props.count,
+					stream->props.u.isoc.framesize*stream->props.u.isoc.framesperurb)) < 0)
+		return i;
+
+	/* allocate the URBs */
+	for (i = 0; i < stream->props.count; i++) {
+		struct urb *urb;
+		int frame_offset = 0;
+		if ((stream->urb_list[i] =
+					usb_alloc_urb(stream->props.u.isoc.framesperurb,GFP_ATOMIC)) == NULL)
+			return -ENOMEM;
+
+		urb = stream->urb_list[i];
+
+		urb->dev = stream->udev;
+		urb->context = stream;
+		urb->complete = usb_urb_complete;
+		urb->pipe = usb_rcvisocpipe(stream->udev,stream->props.endpoint);
+		urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP;
+		urb->interval = stream->props.u.isoc.interval;
+		urb->number_of_packets = stream->props.u.isoc.framesperurb;
+		urb->transfer_buffer_length = stream->buf_size;
+		urb->transfer_buffer = stream->buf_list[i];
+		urb->transfer_dma = stream->dma_addr[i];
+
+		for (j = 0; j < stream->props.u.isoc.framesperurb; j++) {
+			urb->iso_frame_desc[j].offset = frame_offset;
+			urb->iso_frame_desc[j].length = stream->props.u.isoc.framesize;
+			frame_offset += stream->props.u.isoc.framesize;
+		}
+
+		stream->urbs_initialized++;
+	}
+	return 0;
+}
+
+int usb_urb_init(struct usb_data_stream *stream, struct usb_data_stream_properties *props)
+{
+	if (stream == NULL || props == NULL)
+		return -EINVAL;
+
+	memcpy(&stream->props, props, sizeof(*props));
+
+	usb_clear_halt(stream->udev,usb_rcvbulkpipe(stream->udev,stream->props.endpoint));
+
+	if (stream->complete == NULL) {
+		err("there is no data callback - this doesn't make sense.");
+		return -EINVAL;
+	}
+
+	switch (stream->props.type) {
+		case USB_BULK:
+			return usb_bulk_urb_init(stream);
+		case USB_ISOC:
+			return usb_isoc_urb_init(stream);
+		default:
+			err("unkown URB-type for data transfer.");
+			return -EINVAL;
+	}
+}
+
+int usb_urb_exit(struct usb_data_stream *stream)
+{
+	int i;
+
+	usb_urb_kill(stream);
+
+	for (i = 0; i < stream->urbs_initialized; i++) {
+		if (stream->urb_list[i] != NULL) {
+			deb_mem("freeing URB no. %d.\n",i);
+			/* free the URBs */
+			usb_free_urb(stream->urb_list[i]);
+		}
+	}
+	stream->urbs_initialized = 0;
+
+	usb_free_stream_buffers(stream);
+	return 0;
+}
diff --git a/drivers/media/dvb/dvb-usb/a867_usb2impl.c b/drivers/media/dvb/dvb-usb/a867_usb2impl.c
new file mode 100644
index 0000000..23b0629
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_usb2impl.c
@@ -0,0 +1,171 @@
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33)  
+#include <linux/autoconf.h>
+#else
+#include <generated/autoconf.h>
+#endif
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/kref.h>
+#include <linux/usb.h>
+#include <asm/uaccess.h>
+#include <linux/device.h>
+#include <linux/string.h>
+#include <linux/firmware.h>
+#include <linux/delay.h>
+#include <linux/vmalloc.h>
+
+#include "a867_usb2impl.h"
+#include "a867_af903x.h"
+
+#ifdef UNDER_CE
+
+Handle Usb2_handle = NULL;
+
+
+Dword Usb2_getDriver (
+	IN  Demodulator*	demodulator,
+	OUT Handle*			handle
+) {
+	return (Error_NO_ERROR);
+}
+
+
+Dword Usb2_writeControlBus (
+	IN  Demodulator*	demodulator,
+	IN  Dword			bufferLength,
+	IN  Byte*			buffer
+) {
+	return (Error_NO_ERROR);
+}
+
+
+Dword Usb2_readControlBus (
+	IN  Demodulator*	demodulator,
+	IN  Dword			bufferLength,
+	OUT Byte*			buffer
+) {
+	return (Error_NO_ERROR);
+}
+
+
+Dword Usb2_readDataBus (
+	IN  Demodulator*	demodulator,
+	IN  Dword			bufferLength,
+	OUT Byte*			buffer
+) {
+	return (Error_NO_ERROR);
+}
+
+#else
+
+#ifndef _WIN32_WINNT
+#define _WIN32_WINNT 0x0500
+#endif
+
+Handle Usb2_handle = 0;
+/*
+bool (__cdecl *Usb2_initialize) (
+);
+void (__cdecl *Usb2_finalize) (
+);
+bool (__cdecl *Usb2_writeControl) (
+	Byte*		poutBuf,
+	unsigned long		WriteLen,
+	unsigned long*		pnBytesWrite
+); 
+bool (__cdecl *Usb2_readControl) (
+	Byte*		pinBuf,
+	unsigned long		ReadLen,
+	unsigned long*		pnBytesRead
+);
+bool (__cdecl *Usb2_readData) (
+	BYTE*		pinBuf,
+	ULONG		ReadLen
+);
+*/
+
+Dword Usb2_getDriver (
+	IN  Demodulator*	demodulator,
+	OUT Handle*			handle
+) {
+	Dword error = Error_NO_ERROR;
+/*
+	HINSTANCE instance = NULL;
+
+    instance = LoadLibrary ("AF15BDAEX.dll");
+    Usb2_initialize = (bool (__cdecl *) (
+			)) GetProcAddress (instance, "af15_init");
+    Usb2_finalize = (void (__cdecl *) (
+			)) GetProcAddress (instance, "af15_exit");
+	Usb2_writeControl = (bool (__cdecl *) (
+					BYTE*		poutBuf,
+					ULONG		WriteLen,
+					ULONG*		pnBytesWrite
+			)) GetProcAddress (instance, "af15_WriteBulkData");
+    Usb2_readControl = (bool (__cdecl *) (
+					BYTE*		pinBuf,
+					ULONG		ReadLen,
+					ULONG*		pnBytesRead
+			)) GetProcAddress (instance, "af15_ReadBulkData");
+    Usb2_readData = (bool (__cdecl *) (
+					BYTE*		pinBuf,
+					ULONG		ReadLen
+			)) GetProcAddress (instance, "af15_GetTsData");
+
+	if (!Usb2_initialize ())
+		error = Error_DRIVER_INVALID;
+			
+	*handle = (Handle) instance;
+*/
+	return (error);
+}
+
+
+Dword Usb2_writeControlBus (
+	IN  Demodulator*	demodulator,
+	IN  Dword			bufferLength,
+	IN  Byte*			buffer
+) {
+//    Ganymede *pGanymede = (Ganymede *)demodulator;
+    Dword     ret,act_len;
+	    		ret = usb_bulk_msg(usb_get_dev(udevs),
+			usb_sndbulkpipe(usb_get_dev(udevs), 0x02),
+			buffer,
+			bufferLength,
+			&act_len,
+			1000);
+    
+	return (Error_NO_ERROR);
+}
+
+
+Dword Usb2_readControlBus (
+	IN  Demodulator*	demodulator,
+	IN  Dword			bufferLength,
+	OUT Byte*			buffer
+) {
+//    Ganymede *pGanymede = (Ganymede *)demodulator;
+	Dword     ret, nBytesRead;
+   ret = usb_bulk_msg(usb_get_dev(udevs),
+				usb_rcvbulkpipe(usb_get_dev(udevs),129),
+				buffer,
+				255,
+				&nBytesRead,
+				1000);
+    
+	return (Error_NO_ERROR);
+}
+
+
+Dword Usb2_readDataBus (
+	IN  Demodulator*	demodulator,
+	IN  Dword			bufferLength,
+	OUT Byte*			buffer
+) {
+	return (Error_NO_ERROR);
+}
+#endif
diff --git a/drivers/media/dvb/dvb-usb/a867_usb2impl.h b/drivers/media/dvb/dvb-usb/a867_usb2impl.h
new file mode 100644
index 0000000..34b8fe1
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_usb2impl.h
@@ -0,0 +1,38 @@
+#ifndef __USB2IMPL_H__
+#define __USB2IMPL_H__
+
+
+#include "a867_type.h"
+#include "a867_error.h"
+#include "a867_user.h"
+#include "a867_cmd.h"
+
+
+Dword Usb2_getDriver (
+	IN  Demodulator*	demodulator,
+	OUT Handle*			handle
+);
+
+
+Dword Usb2_writeControlBus (
+	IN  Demodulator*	demodulator,
+	IN  Dword			bufferLength,
+	IN  Byte*			buffer
+);
+
+
+Dword Usb2_readControlBus (
+	IN  Demodulator*	demodulator,
+	IN  Dword			bufferLength,
+	OUT Byte*			buffer
+);
+
+
+Dword Usb2_readDataBus (
+	IN  Demodulator*	demodulator,
+	IN  Dword			bufferLength,
+	OUT Byte*			buffer
+);
+
+#endif
+
diff --git a/drivers/media/dvb/dvb-usb/a867_user.c b/drivers/media/dvb/dvb-usb/a867_user.c
new file mode 100644
index 0000000..7e75f05
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_user.c
@@ -0,0 +1,236 @@
+#include "a867_user.h"
+#include "a867_af903x.h"
+
+
+/**
+ * Handle for specific bus driver
+ */
+Handle User_handle = NULL;
+
+
+/**
+ * Totoal number of chip
+ */
+Byte User_chipNumber;
+
+
+/**
+ * Current index of chip
+ */
+Byte User_chipIndex;
+
+
+/**
+ * Variable of critical section
+ */
+
+Dword User_memoryCopy (
+    IN  Demodulator*    demodulator,
+    IN  void*           dest,
+    IN  void*           src,
+    IN  Dword           count
+) {
+    /*
+     *  ToDo:  Add code here
+     *
+     *  //Pseudo code
+     *  memcpy(dest, src, (size_t)count);
+	 *  return (0);
+     */
+	//memcpy (dest, src, (size_t)count);
+    return (Error_NO_ERROR);
+}
+
+
+Dword User_memoryFree (
+	IN  Demodulator*	demodulator,
+	IN  void*			mem
+) {
+    /*
+     *  ToDo:  Add code here
+     *
+     *  //Pseudo code
+     *  free(pMem);
+	 *  return (0);
+     */
+	//free (mem);
+	//ExFreePool(mem);
+    return (Error_NO_ERROR);
+}
+
+
+Dword User_printf (
+	IN  Demodulator*	demodulator,
+	IN  const char*		format, 
+	IN  ...
+) {
+    /*
+     *  ToDo:  Add code here
+     *
+     *  //Pseudo code
+     *  va_list arg;
+     *
+     *  va_start(arg, format);
+     *  vprintf(format, arg);
+     *  va_end(arg);
+     *  return (0);
+     */
+	return (Error_NO_ERROR);
+}
+
+
+Dword User_delay (
+    IN  Demodulator*    demodulator,
+	IN  Dword			dwMs
+) {	
+    /*
+     *  ToDo:  Add code here
+     *
+     *  //Pseudo code
+     *  delay(dwMs);
+     *  return (0);
+     */
+    //Sleep (dwMs);
+	unsigned long j = (HZ*dwMs)/1000;
+	set_current_state(TASK_UNINTERRUPTIBLE);
+	schedule_timeout(j);
+
+	return (Error_NO_ERROR);
+}
+
+
+Dword User_createCriticalSection (
+	IN  Demodulator*	demodulator
+) {
+    /*
+     *  ToDo:  Add code here 
+     *
+     *  //Pseudo code
+     *  return (0);
+     */
+	return (Error_NO_ERROR);
+}
+
+
+Dword User_deleteCriticalSection (
+	IN  Demodulator*	demodulator
+) {
+    /*
+     *  ToDo:  Add code here
+     *
+     *  //Pseudo code
+     *  return (0);
+     */
+    return (Error_NO_ERROR);
+}
+
+
+Dword User_enterCriticalSection (
+    IN  Demodulator*    demodulator
+) {
+    /*
+     *  ToDo:  Add code here
+     *
+     *  //Pseudo code
+     *  return (0);
+     */
+    PDEVICE_CONTEXT PDC = (PDEVICE_CONTEXT)demodulator->userData;
+    if( PDC ) {
+	    down(&PDC->regLock); 
+    }
+    return (Error_NO_ERROR);
+}
+
+
+Dword User_leaveCriticalSection (
+    IN  Demodulator*    demodulator
+) {
+    /*
+     *  ToDo:  Add code here
+     *
+     *  //Pseudo code
+     *  return (0);
+     */
+
+    PDEVICE_CONTEXT PDC = (PDEVICE_CONTEXT)demodulator->userData;
+    if( PDC ) {
+	    up(&PDC->regLock); 
+    }
+    return (Error_NO_ERROR);
+}
+
+
+Dword User_mpegConfig (
+    IN  Demodulator*    demodulator
+) {
+    /*
+     *  ToDo:  Add code here
+     *
+     */
+    return (Error_NO_ERROR);
+}
+
+
+Dword User_busTx (
+    IN  Demodulator*    demodulator,
+    IN  Dword           bufferLength,
+    IN  Byte*           buffer
+) {
+    /*
+     *  ToDo:  Add code here
+     *
+     *  //Pseudo code
+     *  short i;
+     *
+     *  start();
+     *  write_i2c(uc2WireAddr);
+     *  ack();
+     *  for (i = 0; i < bufferLength; i++) {
+     *      write_i2c(*(ucpBuffer + i));
+     *      ack();
+     *  }
+     *  stop();
+     *
+     *  // If no error happened return 0, else return error code.
+     *  return (0);
+     */
+    return (Error_NO_ERROR);
+}
+
+
+Dword User_busRx (
+    IN  Demodulator*    demodulator,
+    IN  Dword           bufferLength,
+    OUT Byte*           buffer
+) {
+    /*
+     *  ToDo:  Add code here
+     *
+     *  //Pseudo code
+     *  short i;
+     *
+     *  start();
+     *  write_i2c(uc2WireAddr | 0x01);
+     *  ack();
+     *  for (i = 0; i < bufferLength - 1; i++) {
+     *      read_i2c(*(ucpBuffer + i));
+     *      ack();
+     *  }
+     *  read_i2c(*(ucpBuffer + bufferLength - 1));
+     *  nack();
+     *  stop();
+     *
+     *  // If no error happened return 0, else return error code.
+     *  return (0);
+     */
+    return (Error_NO_ERROR);
+}
+
+
+Dword User_busRxData (
+    IN  Demodulator*    demodulator,
+    IN  Dword           bufferLength,
+    OUT Byte*           buffer
+) {
+    return (Error_NO_ERROR);
+}
diff --git a/drivers/media/dvb/dvb-usb/a867_user.h b/drivers/media/dvb/dvb-usb/a867_user.h
new file mode 100644
index 0000000..464f521
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_user.h
@@ -0,0 +1,155 @@
+#ifndef __USER_H__
+#define __USER_H__
+
+
+//#include <stdio.h>
+#include "a867_type.h"
+#include "a867_error.h"
+//#include <linux/smp_lock.h> //for Linux mdelay
+#include <linux/delay.h> //for Linux mdelay
+
+
+
+#define User_USE_INTERRUPT              0
+#define User_USE_DRIVER                 0
+
+/** Define timeout count for acquirePlatform and setPlatform, the default value 300 means 30 seconds. */
+#define User_TIMEOUT_COUNT			300
+
+/** Define I2C master speed, the default value 0x0D means 197KHz (1000000000 / (24.4 * 16 * User_I2C_SPEED)). */
+#define User_I2C_SPEED              0x0D
+
+/** Define I2C address of secondary chip when Diversity mode or PIP mode is active. */
+#define User_I2C_ADDRESS			0x3A//0x38
+
+/** Define USB frame size */
+#define User_USB20_MAX_PACKET_SIZE      512
+//j010+s
+//#define User_USB20_FRAME_SIZE           (188 * 348)
+#define User_USB20_FRAME_SIZE           (188 * TS_PACKET_COUNT)
+//j010+e
+#define User_USB20_FRAME_SIZE_DW        (User_USB20_FRAME_SIZE / 4)
+#define User_USB11_MAX_PACKET_SIZE      64
+#define User_USB11_FRAME_SIZE           (188 * 21)
+#define User_USB11_FRAME_SIZE_DW        (User_USB11_FRAME_SIZE / 4)
+
+typedef     unsigned char   tBYTE;      // 1 byte
+typedef     unsigned short  tWORD;      // 2 bytes
+typedef     unsigned int	tDWORD;     // 4 bytes
+typedef     int             tINT;       // 4 bytes
+typedef     void *          tHANDLE;
+
+/**
+ * Memory copy Function
+ */
+Dword User_memoryCopy (
+    IN  Demodulator*    demodulator,
+    IN  void*           dest,
+    IN  void*           src,
+    IN  Dword           count
+);
+
+
+/**
+ * Memory free Function
+ */
+Dword User_memoryFree (
+	IN  Demodulator*	demodulator,
+	IN  void*			mem
+);
+
+
+/**
+ * Print Function
+ */
+Dword User_printf (
+	IN  Demodulator*	demodulator,
+	IN  const char*		format, 
+	IN  ...
+);
+
+
+/**
+ * Delay Function
+ */
+Dword User_delay (
+    IN  Demodulator*    demodulator,
+	IN  Dword			dwMs
+);
+
+
+/**
+ * Creat and initialize critical section
+ */
+Dword User_createCriticalSection (
+	IN  Demodulator*	demodulator
+);
+
+
+/**
+ * Delete critical section
+ */
+Dword User_deleteCriticalSection (
+	IN  Demodulator*	demodulator
+);
+
+
+/**
+ * Enter critical section
+ */
+Dword User_enterCriticalSection (
+    IN  Demodulator*    demodulator
+);
+
+
+/**
+ * Leave critical section
+ */
+Dword User_leaveCriticalSection (
+    IN  Demodulator*    demodulator
+);
+
+
+/**
+ * Config MPEG2 interface
+ */
+Dword User_mpegConfig (
+    IN  Demodulator*    demodulator
+);
+
+
+/**
+ * Write data via "Control Bus"
+ * I2C mode : uc2WireAddr mean demodulator chip address, the default value is 0x38
+ * USB mode : uc2WireAddr is useless, don't have to send this data
+ */
+Dword User_busTx (
+    IN  Demodulator*    demodulator,
+    IN  Dword           bufferLength,
+    IN  Byte*           buffer
+);
+
+
+/**
+ * Read data via "Control Bus"
+ * I2C mode : uc2WireAddr mean demodulator chip address, the default value is 0x38
+ * USB mode : uc2WireAddr is useless, don't have to send this data
+ */
+Dword User_busRx (
+    IN  Demodulator*    demodulator,
+    IN  Dword           bufferLength,
+    OUT Byte*           buffer
+);
+
+
+/**
+ * Read data via "Data Bus"
+ * I2C mode : uc2WireAddr mean demodulator chip address, the default value is 0x38
+ * USB mode : uc2WireAddr is useless, don't have to send this data
+ */
+Dword User_busRxData (
+    IN  Demodulator*    demodulator,
+    IN  Dword           bufferLength,
+    OUT Byte*           buffer
+);
+#endif
diff --git a/drivers/media/dvb/dvb-usb/a867_userdef.h b/drivers/media/dvb/dvb-usb/a867_userdef.h
new file mode 100644
index 0000000..c4be11d
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_userdef.h
@@ -0,0 +1,25 @@
+#ifndef _USERDEF_H_
+#define _USERDEF_H_
+
+
+//typedef     unsigned char   BYTE;      // 1 byte
+//typedef     unsigned short  WORD;      // 2 bytes
+//typedef     unsigned long   DWORD;     // 4 bytes
+typedef     int             INT;       // 4 bytes
+//typedef     void *          HANDLE;
+
+//#define NULL    0
+
+#ifdef IN
+#undef IN
+#endif
+
+#ifdef OUT
+#undef OUT
+#endif
+
+#define IN  
+#define OUT
+#define INOUT
+
+#endif // _USERDEF_H_
diff --git a/drivers/media/dvb/dvb-usb/a867_variable.h b/drivers/media/dvb/dvb-usb/a867_variable.h
new file mode 100644
index 0000000..53d6fbc
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_variable.h
@@ -0,0 +1,260 @@
+#ifndef __VARIABLE_H__
+#define __VARIABLE_H__
+//this file define variable which initialized by AP
+//CFOE------------------------------------------
+
+//These variables are initialized by API.
+//Don't change the order of the definition of these variables.
+
+
+//2k
+//BASE Address 0x418B
+#define var_addr_base                       0x418b
+#define log_addr_base                       0x418d
+#define log_data_base                       0x418f
+// Do NOT touch the following line: used by script
+// --- @xx++ Start variable block
+//Initialization..
+//API relative
+//BASE Address 0x0000
+#define trigger_ofsm                        0x0000
+#define cfoe_NS_2048_coeff1_25_24           0x0001
+#define cfoe_NS_2048_coeff1_23_16           0x0002
+#define cfoe_NS_2048_coeff1_15_8            0x0003
+#define cfoe_NS_2048_coeff1_7_0             0x0004
+#define cfoe_NS_2k_coeff2_24                0x0005
+#define cfoe_NS_2k_coeff2_23_16             0x0006
+#define cfoe_NS_2k_coeff2_15_8              0x0007
+#define cfoe_NS_2k_coeff2_7_0               0x0008
+
+//8k..
+
+#define cfoe_NS_8191_coeff1_25_24           0x0009
+#define cfoe_NS_8191_coeff1_23_16           0x000a
+#define cfoe_NS_8191_coeff1_15_8            0x000b
+#define cfoe_NS_8191_coeff1_7_0             0x000c
+#define cfoe_NS_8192_coeff1_25_24           0x000d
+#define cfoe_NS_8192_coeff1_23_16           0x000e
+#define cfoe_NS_8192_coeff1_15_8            0x000f
+#define cfoe_NS_8192_coeff1_7_0             0x0010
+#define cfoe_NS_8193_coeff1_25_24           0x0011
+#define cfoe_NS_8193_coeff1_23_16           0x0012
+#define cfoe_NS_8193_coeff1_15_8            0x0013
+#define cfoe_NS_8193_coeff1_7_0             0x0014
+
+#define cfoe_NS_8k_coeff2_24                0x0015
+#define cfoe_NS_8k_coeff2_23_16             0x0016
+#define cfoe_NS_8k_coeff2_15_8              0x0017
+#define cfoe_NS_8k_coeff2_7_0               0x0018
+
+//4k
+#define cfoe_NS_4096_coeff1_25_24           0x0019
+#define cfoe_NS_4096_coeff1_23_16           0x001a
+#define cfoe_NS_4096_coeff1_15_8            0x001b
+#define cfoe_NS_4096_coeff1_7_0             0x001c
+#define cfoe_NS_4k_coeff2_24                0x001d
+#define cfoe_NS_4k_coeff2_23_16             0x001e
+#define cfoe_NS_4k_coeff2_15_8              0x001f
+#define cfoe_NS_4k_coeff2_7_0               0x0020
+
+#define bfsfcw_fftindex_ratio_7_0           0x0021
+#define bfsfcw_fftindex_ratio_15_8          0x0022
+#define fftindex_bfsfcw_ratio_7_0           0x0023
+#define fftindex_bfsfcw_ratio_15_8          0x0024
+
+
+
+#define crystal_clk_7_0                     0x0025
+#define crystal_clk_15_8                    0x0026
+#define crystal_clk_23_16                   0x0027
+#define crystal_clk_31_24                   0x0028
+
+
+#define bfs_fcw_7_0                         0x0029
+#define bfs_fcw_15_8                        0x002a
+#define bfs_fcw_22_16                       0x002b
+
+//----------------------------------------------
+//statistic performance..
+
+#define qnt_vbc_err_7_0                     0x002c  //snr
+#define qnt_vbc_err_15_8                    0x002d  //snr
+#define qnt_vbc_err_23_16                   0x002e  //snr
+#define r_qnt_vbc_sframe_num                0x002f
+#define tpsd_const                          0x0030
+#define tpsd_txmod                          0x0031
+ 
+#define rsd_abort_packet_cnt_7_0            0x0032
+#define rsd_abort_packet_cnt_15_8           0x0033
+#define rsd_bit_err_cnt_7_0                 0x0034
+#define rsd_bit_err_cnt_15_8                0x0035
+#define rsd_bit_err_cnt_23_16               0x0036
+#define r_rsd_packet_unit_7_0               0x0037
+#define r_rsd_packet_unit_15_8              0x0038
+
+#define qnt_vbc_sframe_num                  0x0039
+#define rsd_packet_unit_7_0                 0x003a
+#define rsd_packet_unit_15_8                0x003b
+
+#define tpsd_lock                           0x003c
+#define mpeg_lock                           0x003d
+#define RsdSequence                         0x003e
+#define VtbSequence                         0x003f
+
+#define Training_Mode                       0x0040
+#define RESET_STATE                         0x0041
+#define unplug_flg                          0x0042
+#define aci_0                               0x0043
+#define aci_1                               0x0044
+
+#define adcx2                               0x0045
+#define tuner_ID                            0x0046
+#define empty_channel_status                0x0047
+#define signal_strength                     0x0048
+#define signal_quality                      0x0049
+#define est_rf_level_dbm                    0x004a
+#define FreBand                             0x004b
+#define suspend_flag                        0x004c
+//GUI relative
+//Initial OFSM
+#define API_Reserved                        0x004d
+#define var_ofsm_state                      0x004e
+#define OfdmGuiRCN_H                        0x004f
+#define OfdmGuiRCN_L                        0x0050
+#define antenna_unplugged                   0x0051
+#define strong_signal_detected              0x0052
+#define channelFlatnessInd                  0x0053
+#define Flatness_Ind_nonCmb                 0x0054
+#define AutoDetectedSpectrumInv             0x0055
+#define IsSpectrumInv                       0x0056
+#define strong_detect_bypass                0x0057
+#define ss_dtop_bypass                      0x0058
+#define retrain_dtop_bypass                 0x0059
+#define EnableTimeSlice                     0x005a
+#define SynchronizationType                 0x005b
+#define ApplyFastSynchronizationToEchoChannel 0x005c
+#define ApplyPwmToRfIf                      0x005d
+#define ChannelNo                           0x005e
+
+//release to AAGC document..
+#define csi_bypass                          0x005f
+#define mobile_bypass                       0x0060
+#define EnableSpeedLog                      0x0061
+
+//regression used only..
+#define r_rsd_abort_total_packet_7_0        0x0062
+#define r_rsd_abort_total_packet_15_8       0x0063
+#define r_rsd_abort_total_packet_23_16      0x0064
+#define MaxRsdSequence                      0x0065
+#define RsdFrameNo                          0x0066
+#define MPESuperFrameNo                     0x0067
+
+#define AgcDesiredLevel                     0x0068
+#define MinRfGain                           0x0069
+#define MaxIfGain                           0x006a
+#define RssiOffset                          0x006b
+#define RssiResidual                        0x006c
+//Dtop
+
+#define strong_weak_signal_default          0x006d
+#define unplug_th                           0x006e
+#define afe_mem4_rssi_comp                  0x006f
+
+#define aagc_speed_detect_count             0x0070
+#define aagc_mobile_thr                     0x0071
+#define aagc_nonmobile_thr                  0x0072
+#define agc_counter                         0x0073
+#define DisableAagcTop                      0x0074
+#define AgcReset                            0x0075
+#define AgcUp                               0x0076
+#define AgcDown                             0x0077
+#define AgcHold                             0x0078
+#define PwmCtrlHw                           0x0079
+#define MaxAgcGain                          0x007a
+#define IniAgcGain                          0x007b
+#define mccid_bypass                        0x007c
+#define CdpfEnDefaultEchoRange              0x007d
+#define CdpfIniTestNo                       0x007e
+#define timing_err_level                    0x007f
+#define timing_retrain_cnt                  0x0080
+#define ChannelDiffThr                      0x0081
+
+#define adjacent_on                         0x0082
+#define near_adjacent_on                    0x0083
+#define adjacent_off                        0x0084
+#define near_adjacent_off                   0x0085
+#define max_rf_agc_7_0                      0x0086
+#define max_rf_agc_9_8                      0x0087
+#define rf_top_numerator_s_7_0              0x0088
+#define rf_top_numerator_s_9_8              0x0089
+
+#define gui_tdi_lms_en                      0x008a
+#define fccid_strobe_scale                  0x008b
+#define fccid_strobe_numerator              0x008c
+#define fccid_strobe_base                   0x008d
+#define use_fccid                           0x008e
+#define fft_ave_symbol_num                  0x008f
+#define large_tone_num_th_7_0               0x0090
+#define large_tone_num_th_15_8              0x0091
+#define use_3m_lpf_th                       0x0092
+#define ce_var_min_8k                       0x0093
+#define ce_var_min_4k                       0x0094
+#define ce_var_min_2k                       0x0095
+#define ce_var_min_8k_non_flat              0x0096
+#define flatness_thr                        0x0097
+#define non_mobile_signal_level_offset      0x0098
+#define gui_ar_csi_en                       0x0099
+#define h2_echo_detected                    0x009a
+#define signal_strength_rf_high             0x009b
+#define signal_strength_rf_low              0x009c
+#define signal_strength_if_high             0x009d
+#define signal_strength_if_low              0x009e
+//flatness
+#define flatness_thr_high                   0x009f
+#define flatness_thr_low                    0x00a0
+
+//softbit quality
+#define sbq1                                0x00a1
+#define sbq2                                0x00a2
+
+//DCA
+#define dyna_dca_offset_en                  0x00a3
+#define dca_sbq_bad_th                      0x00a4
+#define detect_timing_err_en                0x00a5
+#define flatness_from_h2_echo               0x00a6
+
+#define timging_error_detection             0x00a7
+#define ce_forced_by_rotate                 0x00a8
+#define fccid_fft_mask_en                   0x00a9
+#define second_fctrl_unforce_en             0x00aa
+#define force_fdi0_at_high_mobile_en        0x00ab
+#define high_mobile_detected                0x00ac
+#define flatness_detection_en               0x00ad
+#define ChooseFsteCostFunctionFromCdpf      0x00ae
+#define signal_level                        0x00af
+#define TryConf2En                          0x00b0
+#define Lower_tpsd_lock                     0x00b1
+#define Upper_tpsd_lock                     0x00b2
+
+#define AgcCtrlType                         0x00b3
+#define opt_LNA_Rssi_scale                  0x00b4
+#define StopByTcl                           0x00b5
+#define RssiCalibration                     0x00b6
+#define AciDesiredSignalLevel_h             0x00b7
+#define AciDesiredSignalLevel_l             0x00b8
+#define ECO_ASIC                            0x00b9
+#define NXP_USE_I2C                         0x00ba
+#define rf_freqency_23_16                   0x00bb
+#define rf_freqency_15_8                    0x00bc
+#define rf_freqency_7_0                     0x00bd
+#define iqik_en                             0x00be
+#define dcc_en                              0x00bf
+#define VHFPinEnTh                          0x00c0
+#define ACIdetection                        0x00c1
+#define PinDiode                            0x00c2
+#define LNA_Gain                            0x00c3
+#define RSSI_LNA_ON                         0x00c4
+#define var_end                             0x00c5
+
+//BASE Address 0xFFFF
+#endif
diff --git a/drivers/media/dvb/dvb-usb/a867_version.h b/drivers/media/dvb/dvb-usb/a867_version.h
new file mode 100644
index 0000000..c3d3ddd
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/a867_version.h
@@ -0,0 +1,3 @@
+#define Version_NUMBER		0x0200
+#define Version_DATE		0x20080314
+#define Version_BUILD		0x01
diff --git a/drivers/media/dvb/dvb-usb/af9035.c b/drivers/media/dvb/dvb-usb/af9035.c
new file mode 100644
index 0000000..e1b72e9
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/af9035.c
@@ -0,0 +1,1272 @@
+/*
+ * Afatech AF9035 DVB USB driver
+ *
+ * Copyright (C) 2008 Afatech
+ * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 2 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ * Thanks to TerraTec for a support received.
+ */
+
+#include "af9035.h"
+#include "af9033.h"
+#include "tua9001.h"
+#include "mxl5007t.h"
+#include "tda18218.h"
+#include <linux/version.h>
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0)) || ((defined V4L2_VERSION) && (V4L2_VERSION >= 196608))
+#define V4L2_REFACTORED_MFE_CODE
+#endif
+
+/*
+ * enable devices supported by the Avemedia A867 proprietary driver;
+ * some of this devices may use an unsupported tuner type (AF9007),
+ * so they may not work; probably those devices belong to the A333 family;
+ */
+//#define ENABLE_A867_DEVICES
+
+static int dvb_usb_af9035_debug;
+module_param_named(debug, dvb_usb_af9035_debug, int, 0644);
+MODULE_PARM_DESC(debug, "set debugging level" DVB_USB_DEBUG_STATUS);
+DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
+
+static DEFINE_MUTEX(af9035_usb_mutex);
+
+static struct af9035_config af9035_config;
+static struct dvb_usb_device_properties af9035_properties[1];
+static int af9035_properties_count = ARRAY_SIZE(af9035_properties);
+
+static struct af9033_config af9035_af9033_config[] = {
+	{
+		.demod_address = 0,
+		.tuner_address = 0,
+		.output_mode = AF9033_TS_MODE_USB,
+	}, {
+		.demod_address = 0,
+		.tuner_address = 0,
+		.output_mode = AF9033_TS_MODE_SERIAL,
+	}
+};
+
+static u8 regmask[8] = {0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xff};
+
+static int af9035_rw_udev(struct usb_device *udev, struct af9035_req *req)
+{
+#define BUF_SIZE 63
+	int act_len, ret;
+	u8 buf[BUF_SIZE];
+	u32 msg_len;
+	static u8 seq; /* packet sequence number */
+	u16 checksum = 0;
+	u8 i;
+
+	/* buffer overflow check */
+	if (req->wlen > (BUF_SIZE - 6) || req->rlen > (BUF_SIZE - 5)) {
+		err("too much data wlen:%d rlen:%d", req->wlen, req->rlen);
+		return -EINVAL;
+	}
+
+	if (mutex_lock_interruptible(&af9035_usb_mutex) < 0)
+		return -EAGAIN;
+
+	buf[0] = req->wlen + 3 + 2; /* 3 header + 2 checksum */
+	buf[1] = req->mbox;
+	buf[2] = req->cmd;
+	buf[3] = seq++;
+	if (req->wlen)
+		memcpy(&buf[4], req->wbuf, req->wlen);
+
+	/* calc and add checksum */
+	for (i = 1; i < buf[0]-1; i++) {
+		if (i % 2)
+			checksum += buf[i] << 8;
+		else
+			checksum += buf[i];
+	}
+	checksum = ~checksum;
+
+	buf[buf[0]-1] = (checksum >> 8);
+	buf[buf[0]-0] = (checksum & 0xff);
+
+	msg_len = buf[0]+1;
+
+	deb_xfer(">>> ");
+	debug_dump(buf, msg_len, deb_xfer);
+
+	/* send req */
+	ret = usb_bulk_msg(udev, usb_sndbulkpipe(udev, 0x02), buf, msg_len,
+	&act_len, AF9035_USB_TIMEOUT);
+	if (ret)
+		err("bulk message failed:%d (%d/%d)", ret, msg_len, act_len);
+	else
+		if (act_len != msg_len)
+			ret = -EIO; /* all data is not send */
+	if (ret)
+		goto error_unlock;
+
+	/* no ack for those packets */
+	if (req->cmd == CMD_FW_DOWNLOAD)
+		goto exit_unlock;
+
+	/* receive ack and data if read req */
+	msg_len = 3 + req->rlen + 2;  /* data len + status + seq + checksum */
+	ret = usb_bulk_msg(udev, usb_rcvbulkpipe(udev, 0x81), buf, msg_len,
+			   &act_len, AF9035_USB_TIMEOUT);
+	if (ret) {
+		err("recv bulk message failed:%d", ret);
+		ret = -EIO;
+		goto error_unlock;
+	}
+
+	deb_xfer("<<< ");
+	debug_dump(buf, act_len, deb_xfer);
+
+	/* check status */
+	if (buf[2]) {
+		err("command:%02x failed:%d", req->cmd, buf[2]);
+		ret = -EIO;
+		goto error_unlock;
+	}
+
+	/* read request, copy returned data to return buf */
+	if (req->rlen)
+		memcpy(req->rbuf, &buf[3], req->rlen);
+error_unlock:
+exit_unlock:
+	mutex_unlock(&af9035_usb_mutex);
+
+	return ret;
+}
+
+static int af9035_write_regs_bis(struct usb_device *d, u8 mbox, u16 reg,
+u8 *val, u8 len)
+{
+	u8 wbuf[6+len];
+	struct af9035_req req = {CMD_REG_DEMOD_WRITE, mbox, sizeof(wbuf), wbuf,
+		0, NULL};
+	wbuf[0] = len;
+	wbuf[1] = 2;
+	wbuf[2] = 0;
+	wbuf[3] = 0;
+	wbuf[4] = reg >> 8;
+	wbuf[5] = reg & 0xff;
+	memcpy(&wbuf[6], val, len);
+	return af9035_rw_udev(d, &req);
+}
+
+static int af9035_write_regs(struct dvb_usb_device *d, u8 mbox, u16 reg,
+u8 *val, u8 len)
+{
+	return af9035_write_regs_bis(d->udev, mbox, reg, val, len);
+}
+
+static int af9035_read_regs_bis(struct usb_device *d, u8 mbox, u16 reg, u8 *val,
+	u8 len)
+{
+	u8 wbuf[] = {len, 2, 0, 0, reg >> 8, reg & 0xff};
+	struct af9035_req req = {CMD_REG_DEMOD_READ, mbox, sizeof(wbuf), wbuf,
+		len, val};
+	return af9035_rw_udev(d, &req);
+}
+
+static int af9035_read_regs(struct dvb_usb_device *d, u8 mbox, u16 reg, u8 *val,
+	u8 len)
+{
+	return af9035_read_regs_bis(d->udev, mbox, reg, val, len);
+}
+
+static int af9035_write_reg_bis(struct usb_device *d, u8 mbox, u16 reg, u8 val)
+{
+	return af9035_write_regs_bis(d, mbox, reg, &val, 1);
+}
+
+static int af9035_write_reg(struct dvb_usb_device *d, u8 mbox, u16 reg, u8 val)
+{
+	return af9035_write_regs_bis(d->udev, mbox, reg, &val, 1);
+}
+
+static int af9035_read_reg_bis(struct usb_device *d, u8 mbox, u16 reg, u8 *val)
+{
+	return af9035_read_regs_bis(d, mbox, reg, val, 1);
+}
+
+static int af9035_write_reg_bits_bis(struct usb_device *d, u8 mbox, u16 reg,
+	u8 pos, u8 len, u8 val)
+{
+	int ret;
+	u8 tmp, mask;
+
+	ret = af9035_read_reg_bis(d, mbox, reg, &tmp);
+	if (ret)
+		return ret;
+
+	mask = regmask[len - 1] << pos;
+	tmp = (tmp & ~mask) | ((val << pos) & mask);
+
+	return af9035_write_reg_bis(d, mbox, reg, tmp);
+}
+
+static int af9035_write_reg_bits(struct dvb_usb_device *d, u8 mbox, u16 reg,
+	u8 pos, u8 len, u8 val)
+{
+	return af9035_write_reg_bits_bis(d->udev, mbox, reg, pos, len, val);
+}
+
+static int af9035_read_reg_bits_bis(struct usb_device *d, u8 mbox, u16 reg,
+	u8 pos, u8 len, u8 *val)
+{
+	int ret;
+	u8 tmp;
+
+	ret = af9035_read_reg_bis(d, mbox, reg, &tmp);
+	if (ret)
+		return ret;
+	*val = (tmp >> pos) & regmask[len - 1];
+	return 0;
+}
+
+static int af9035_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[],
+	int num)
+{
+	struct dvb_usb_device *d = i2c_get_adapdata(adap);
+	int ret = 0, i = 0;
+	u16 reg;
+	u8 mbox;
+
+	if (mutex_lock_interruptible(&d->i2c_mutex) < 0)
+		return -EAGAIN;
+
+	while (i < num) {
+		mbox = msg[i].buf[0];
+		reg = msg[i].buf[1] << 8;
+		reg += msg[i].buf[2];
+		if (num > i + 1 && (msg[i+1].flags & I2C_M_RD)) {
+			if (msg[i].addr ==
+				af9035_af9033_config[0].demod_address ||
+			    msg[i].addr ==
+				af9035_af9033_config[1].demod_address) {
+				if (af9035_af9033_config[1].demod_address && (msg[i].addr == af9035_af9033_config[1].demod_address))
+					mbox += 0x10;
+				ret = af9035_read_regs(d, mbox, reg,
+					&msg[i+1].buf[0], msg[i+1].len);
+			} else {
+				/* FIXME */
+				u8 wbuf[5];
+				u8 rbuf[BUF_SIZE];
+				struct af9035_req req = {CMD_REG_TUNER_READ,
+					LINK, sizeof(wbuf), wbuf, msg[i + 1].len,
+					rbuf};
+				if (af9035_af9033_config[1].tuner_address &&
+					(msg[i].addr == af9035_af9033_config[1].tuner_address)) {
+					msg[i].addr = af9035_af9033_config[0].tuner_address;
+					req.mbox += 0x10;
+				}
+				wbuf[0] = msg[i + 1].len; /* read len */
+				wbuf[1] = msg[i].addr; /* tuner i2c addr */
+				wbuf[2] = 0x01; /* reg width */
+				wbuf[3] = 0x00; /* reg MSB */
+				wbuf[4] = msg[i].buf[0]; /* reg LSB */
+				ret = af9035_rw_udev(d->udev, &req);
+				memcpy (msg[i + 1].buf, rbuf, msg[i + 1].len);
+			}
+			i += 2;
+		} else {
+			if (msg[i].addr ==
+				af9035_af9033_config[0].demod_address ||
+			    msg[i].addr ==
+				af9035_af9033_config[1].demod_address) {
+				if (af9035_af9033_config[1].demod_address && (msg[i].addr == af9035_af9033_config[1].demod_address))
+					mbox += 0x10;
+				ret = af9035_write_regs(d, mbox, reg,
+					&msg[i].buf[3], msg[i].len-3);
+			} else {
+				u8 wbuf[BUF_SIZE];
+				struct af9035_req req = {CMD_REG_TUNER_WRITE,
+					LINK, 4 + msg[i].len, wbuf, 0, NULL};
+				if (af9035_af9033_config[1].tuner_address &&
+					(msg[i].addr == af9035_af9033_config[1].tuner_address)) {
+					msg[i].addr = af9035_af9033_config[0].tuner_address;
+					req.mbox += 0x10;
+				}
+				wbuf[0] = msg[i].len - 1; /* write len */
+				wbuf[1] = msg[i].addr; /* tuner i2c addr */
+				wbuf[2] = 0x01; /* reg width */
+				wbuf[3] = 0x00; /* reg MSB */
+				memcpy (&wbuf[4], msg[i].buf, msg[i].len);
+				ret = af9035_rw_udev(d->udev, &req);
+			}
+			i += 1;
+		}
+		if (ret)
+			goto error;
+
+	}
+	ret = i;
+error:
+	mutex_unlock(&d->i2c_mutex);
+
+	return ret;
+}
+
+static u32 af9035_i2c_func(struct i2c_adapter *adapter)
+{
+	return I2C_FUNC_I2C;
+}
+
+static struct i2c_algorithm af9035_i2c_algo = {
+	.master_xfer = af9035_i2c_xfer,
+	.functionality = af9035_i2c_func,
+#ifdef NEED_ALGO_CONTROL
+	.algo_control = dummy_algo_control,
+#endif
+};
+
+static int af9035_init_endpoint(struct dvb_usb_device *d)
+{
+	int ret;
+	u16 frame_size;
+	u8  packet_size;
+
+	if (d->udev->speed == USB_SPEED_FULL) {
+		frame_size = TS_USB11_FRAME_SIZE/4;
+		packet_size = TS_USB11_MAX_PACKET_SIZE/4;
+	} else {
+		frame_size = TS_USB20_FRAME_SIZE/4;
+		packet_size = TS_USB20_MAX_PACKET_SIZE/4;
+	}
+
+	deb_info("%s: USB speed:%d frame_size:%04x packet_size:%02x\n",
+		__func__, d->udev->speed, frame_size, packet_size);
+
+	/* enable EP4 reset */
+	ret = af9035_write_reg_bits(d, OFDM, p_reg_mp2_sw_rst,
+		reg_mp2_sw_rst_pos, reg_mp2_sw_rst_len, 1);
+	if (ret)
+		goto error;
+
+	/* enable EP5 reset */
+	ret = af9035_write_reg_bits(d, OFDM, p_reg_mp2if2_sw_rst,
+		reg_mp2if2_sw_rst_pos, reg_mp2if2_sw_rst_len, 1);
+	if (ret)
+		goto error;
+
+	/* disable EP4 */
+	ret = af9035_write_reg_bits(d, LINK, p_reg_ep4_tx_en,
+		reg_ep4_tx_en_pos, reg_ep4_tx_en_len, 0);
+	if (ret)
+		goto error;
+
+	/* disable EP5 */
+	ret = af9035_write_reg_bits(d, LINK, p_reg_ep5_tx_en,
+		reg_ep5_tx_en_pos, reg_ep5_tx_en_len, 0);
+	if (ret)
+		goto error;
+
+	/* disable EP4 NAK */
+	ret = af9035_write_reg_bits(d, LINK, p_reg_ep4_tx_nak,
+		reg_ep4_tx_nak_pos, reg_ep4_tx_nak_len, 0);
+	if (ret)
+		goto error;
+
+	/* disable EP5 NAK */
+	ret = af9035_write_reg_bits(d, LINK, p_reg_ep5_tx_nak,
+		reg_ep5_tx_nak_pos, reg_ep5_tx_nak_len, 0);
+	if (ret)
+		goto error;
+
+	/* enable EP4 */
+	ret = af9035_write_reg_bits(d, LINK, p_reg_ep4_tx_en,
+		reg_ep4_tx_en_pos, reg_ep4_tx_en_len, 1);
+	if (ret)
+		goto error;
+
+	/* EP4 xfer length */
+	ret = af9035_write_regs(d, LINK, p_reg_ep4_tx_len_7_0,
+		(u8 *) &frame_size, sizeof(frame_size));
+	if (ret)
+		goto error;
+
+	/* EP4 packet size */
+	ret = af9035_write_reg(d, LINK, p_reg_ep4_max_pkt, packet_size);
+	if (ret)
+		goto error;
+
+	/* configure EP5 for dual mode */
+	if (af9035_config.dual_mode) {
+		/* enable EP5 */
+		ret = af9035_write_reg_bits(d, LINK, p_reg_ep5_tx_en,
+			reg_ep5_tx_en_pos, reg_ep5_tx_en_len, 1);
+		if (ret)
+			goto error;
+
+		/* EP5 xfer length */
+		ret = af9035_write_regs(d, LINK, p_reg_ep5_tx_len_7_0,
+			(u8 *) &frame_size, sizeof(frame_size));
+		if (ret)
+			goto error;
+
+		/* EP5 packet size */
+		ret = af9035_write_reg(d, LINK, p_reg_ep5_max_pkt, packet_size);
+		if (ret)
+			goto error;
+	}
+
+	/* enable / disable mp2if2 */
+	ret = af9035_write_reg_bits(d, OFDM, p_reg_mp2if2_en,
+		reg_mp2if2_en_pos, reg_mp2if2_en_len, af9035_config.dual_mode);
+	if (ret)
+		goto error;
+
+	/* enable / disable tsis */
+	ret = af9035_write_reg_bits(d, OFDM, p_reg_tsis_en, reg_tsis_en_pos,
+		reg_tsis_en_len, af9035_config.dual_mode);
+	if (ret)
+		goto error;
+
+	/* negate EP4 reset */
+	ret = af9035_write_reg_bits(d, OFDM, p_reg_mp2_sw_rst,
+		reg_mp2_sw_rst_pos, reg_mp2_sw_rst_len, 0);
+	if (ret)
+		goto error;
+
+	/* negate EP5 reset */
+	ret = af9035_write_reg_bits(d, OFDM, p_reg_mp2if2_sw_rst,
+		reg_mp2if2_sw_rst_pos, reg_mp2if2_sw_rst_len, 0);
+	if (ret)
+		goto error;
+
+error:
+	if (ret)
+		err("endpoint init failed:%d", ret);
+	return ret;
+}
+
+static int af9035_init(struct dvb_usb_device *d)
+{
+	int ret;
+	deb_info("%s:\n", __func__);
+
+	ret = af9035_init_endpoint(d);
+	if (ret)
+		goto error;
+error:
+	return ret;
+}
+
+static int af9035_download_firmware(struct usb_device *udev,
+	const struct firmware *fw)
+{
+	u8 *fw_data_ptr = (u8 *) fw->data;
+	int i, j, len, packets, remainder, ret;
+	u8 wbuf[1];
+	u8 rbuf[4];
+	struct af9035_firmware_header fw_hdr;
+	struct af9035_req req = {0, LINK, 0, NULL, 1, rbuf};
+	struct af9035_req req_fw_dl = {CMD_FW_DOWNLOAD, LINK, 0, NULL, 0, NULL};
+	struct af9035_req req_rom = {CMD_SCATTER_WRITE, LINK, 0, NULL, 1, rbuf};
+	struct af9035_req req_fw_ver = {CMD_QUERYINFO, LINK, 1, wbuf, 4, rbuf};
+
+	/* read firmware segment info from beginning of the firmware file */
+	fw_hdr.segment_count = *fw_data_ptr++;
+	deb_info("%s: fw segment count:%d\n", __func__, fw_hdr.segment_count);
+	if (fw_hdr.segment_count > SEGMENT_MAX_COUNT) {
+		warn("too big firmware segmen count:%d", fw_hdr.segment_count);
+		fw_hdr.segment_count = SEGMENT_MAX_COUNT;
+	}
+	for (i = 0; i < fw_hdr.segment_count; i++) {
+		fw_hdr.segment[i].type = (*fw_data_ptr++);
+		fw_hdr.segment[i].len  = (*fw_data_ptr++) << 24;
+		fw_hdr.segment[i].len += (*fw_data_ptr++) << 16;
+		fw_hdr.segment[i].len += (*fw_data_ptr++) <<  8;
+		fw_hdr.segment[i].len += (*fw_data_ptr++) <<  0;
+		deb_info("%s: fw segment type:%d len:%d\n", __func__,
+			fw_hdr.segment[i].type, fw_hdr.segment[i].len);
+	}
+
+	#define FW_PACKET_MAX_DATA 57 /* 63-4-2, packet_size-header-checksum */
+
+	/* download all segments */
+	for (i = 0; i < fw_hdr.segment_count; i++) {
+		deb_info("%s: segment type:%d\n", __func__,
+			fw_hdr.segment[i].type);
+		if (fw_hdr.segment[i].type == SEGMENT_FW_DOWNLOAD) {
+			/* download begin packet */
+			req.cmd = CMD_FW_DOWNLOAD_BEGIN;
+			ret = af9035_rw_udev(udev, &req);
+			if (ret) {
+				err("firmware download failed:%d", ret);
+				goto error;
+			}
+
+			packets = fw_hdr.segment[i].len / FW_PACKET_MAX_DATA;
+			remainder = fw_hdr.segment[i].len % FW_PACKET_MAX_DATA;
+			len = FW_PACKET_MAX_DATA;
+			for (j = 0; j <= packets; j++) {
+				if (j == packets)  /* size of the last packet */
+					len = remainder;
+
+				req_fw_dl.wlen = len;
+				req_fw_dl.wbuf = fw_data_ptr;
+				ret = af9035_rw_udev(udev, &req_fw_dl);
+				if (ret) {
+					err("firmware download failed at " \
+						"segment:%d packet:%d err:%d", \
+						i, j, ret);
+					goto error;
+				}
+				fw_data_ptr += len;
+			}
+			/* download end packet */
+			req.cmd = CMD_FW_DOWNLOAD_END;
+			ret = af9035_rw_udev(udev, &req);
+			if (ret) {
+				err("firmware download failed:%d", ret);
+				goto error;
+			}
+		} else if (fw_hdr.segment[i].type == SEGMENT_ROM_COPY){
+			packets = fw_hdr.segment[i].len / FW_PACKET_MAX_DATA;
+			remainder = fw_hdr.segment[i].len % FW_PACKET_MAX_DATA;
+			len = FW_PACKET_MAX_DATA;
+			for (j = 0; j <= packets; j++) {
+				if (j == packets)  /* size of the last packet */
+					len = remainder;
+
+				req_rom.wlen = len;
+				req_rom.wbuf = fw_data_ptr;
+				ret = af9035_rw_udev(udev, &req_rom);
+				if (ret) {
+					err("firmware download failed at " \
+						"segment:%d packet:%d err:%d", \
+						i, j, ret);
+					goto error;
+				}
+				fw_data_ptr += len;
+			}
+		} else {
+			deb_info("%s: segment type:%d not implemented\n",
+				__func__, fw_hdr.segment[i].type);
+		}
+	}
+
+	/* firmware loaded, request boot */
+	req.cmd = CMD_BOOT;
+	ret = af9035_rw_udev(udev, &req);
+	if (ret)
+		goto error;
+
+	/* ensure firmware starts */
+	wbuf[0] = 1;
+	ret = af9035_rw_udev(udev, &req_fw_ver);
+	if (ret)
+		goto error;
+
+	deb_info("%s: reply:%02x %02x %02x %02x\n", __func__,
+		rbuf[0], rbuf[1], rbuf[2], rbuf[3]);
+
+	if (!(rbuf[0] || rbuf[1] || rbuf[2] || rbuf[3])) {
+		err("firmware did not run");
+		ret = -EIO;
+	}
+
+error:
+	if (ret)
+		deb_info("%s: failed:%d\n", __func__, ret);
+
+	return ret;
+}
+
+static int af9035_read_eeprom_reg(struct usb_device *udev, u16 reg, u8 *val)
+{
+	u8 wbuf[] = {1, 2, 0, 0, reg >> 8, reg & 0xff};
+	struct af9035_req req = {CMD_REG_DEMOD_READ, LINK, sizeof(wbuf), wbuf,
+		1, val};
+	return af9035_rw_udev(udev, &req);
+}
+
+static int af9035_read_config(struct usb_device *udev)
+{
+	int ret;
+	u8 val, i, offset = 0;
+
+	/* IR remote controller */
+	ret = af9035_read_eeprom_reg(udev, EEPROM_IR_MODE, &val);
+	if (ret)
+		goto error;
+	deb_info("%s: IR mode:%d\n", __func__, val);
+
+	/* TS mode - one or two receivers */
+	ret = af9035_read_eeprom_reg(udev, EEPROM_TS_MODE, &val);
+	if (ret)
+		goto error;
+	af9035_config.dual_mode = val;
+	deb_info("%s: TS mode:%d\n", __func__, af9035_config.dual_mode);
+
+	/* Set adapter0 buffer size according to USB port speed, adapter1 buffer
+	   size can be static because it is enabled only USB2.0 */
+	for (i = 0; i < af9035_properties_count; i++) {
+		/* USB1.1 set smaller buffersize and disable 2nd adapter */
+		if (udev->speed == USB_SPEED_FULL) {
+#ifdef V4L2_REFACTORED_MFE_CODE
+			af9035_properties[i].adapter[0].fe[0].stream.u.bulk.buffersize
+#else
+			af9035_properties[i].adapter[0].stream.u.bulk.buffersize
+#endif
+				= TS_USB11_MAX_PACKET_SIZE;
+			/* disable 2nd adapter because we don't have
+			   PID-filters */
+			af9035_config.dual_mode = 0;
+		} else {
+#ifdef V4L2_REFACTORED_MFE_CODE
+			af9035_properties[i].adapter[0].fe[0].stream.u.bulk.buffersize
+#else
+			af9035_properties[i].adapter[0].stream.u.bulk.buffersize
+#endif
+				= TS_USB20_FRAME_SIZE;
+		}
+	}
+
+	if (af9035_config.dual_mode) {
+		/* read 2nd demodulator I2C address */
+		ret = af9035_read_eeprom_reg(udev, EEPROM_2WIREADDR, &val);
+		if (ret)
+			goto error;
+		deb_info("%s: 2nd demod I2C addr:%02x\n", __func__, val);
+		af9035_af9033_config[1].demod_address = val;
+		/* enable 2nd adapter */
+		for (i = 0; i < af9035_properties_count; i++)
+			af9035_properties[i].num_adapters = 2;
+	} else {
+		 /* disable 2nd adapter */
+		for (i = 0; i < af9035_properties_count; i++)
+			af9035_properties[i].num_adapters = 1;
+	}
+
+	for (i = 0; i < af9035_properties[0].num_adapters; i++) {
+		if (i == 1)
+			offset =  EEPROM_SHIFT;
+
+		/* saw BW */
+		ret = af9035_read_eeprom_reg(udev, EEPROM_SAW_BW1 + offset,
+			&val);
+		if (ret)
+			goto error;
+		deb_info("%s: [%d] saw BW:%d\n", __func__, i, val);
+
+		/* xtal */
+		ret = af9035_read_eeprom_reg(udev, EEPROM_XTAL1 + offset, &val);
+		if (ret)
+			goto error;
+		deb_info("%s: [%d] xtal:%d\n", __func__, i, val);
+
+		/* RF spectrum inversion */
+		ret = af9035_read_eeprom_reg(udev, EEPROM_SPECINV1 + offset,
+			&val);
+		if (ret)
+			goto error;
+		deb_info("%s: [%d] RF spectrum inv:%d\n", __func__, i, val);
+
+		/* IF */
+		ret = af9035_read_eeprom_reg(udev, EEPROM_IFFREQH1 + offset,
+			&val);
+		if (ret)
+			goto error;
+		af9035_af9033_config[i].if_freq = val << 8;
+		ret = af9035_read_eeprom_reg(udev, EEPROM_IFFREQL1 + offset,
+			&val);
+		if (ret)
+			goto error;
+		af9035_af9033_config[i].if_freq += val;
+		deb_info("%s: [%d] IF:%d\n", __func__, i,
+			af9035_af9033_config[0].if_freq);
+
+		/* MT2060 IF1 */
+		ret = af9035_read_eeprom_reg(udev, EEPROM_IF1H1 + offset, &val);
+		if (ret)
+			goto error;
+		af9035_config.mt2060_if1[i] = val << 8;
+		ret = af9035_read_eeprom_reg(udev, EEPROM_IF1L1 + offset, &val);
+		if (ret)
+			goto error;
+		af9035_config.mt2060_if1[i] += val;
+		deb_info("%s: [%d] MT2060 IF1:%d\n", __func__, i,
+			af9035_config.mt2060_if1[i]);
+
+		/* tuner */
+		ret = af9035_read_eeprom_reg(udev, EEPROM_TUNER_ID1 + offset,
+			&val);
+		if (ret)
+			goto error;
+		switch (val) {
+		case AF9033_TUNER_TUA9001:
+			af9035_af9033_config[i].rf_spec_inv = 1;
+			break;
+		case AF9033_TUNER_MXL5007t:
+			af9035_af9033_config[i].rf_spec_inv = 1;
+			break;
+                case AF9033_TUNER_TDA18218:
+			af9035_af9033_config[i].rf_spec_inv = 1;
+			break;
+		default:
+			warn("tuner ID:%d not supported, please report!", val);
+			return -ENODEV;
+		};
+
+		af9035_af9033_config[i].tuner = val;
+		deb_info("%s: [%d] tuner ID:%d\n", __func__, i, val);
+	}
+
+error:
+	if (ret)
+		err("eeprom read failed:%d", ret);
+
+	if (le16_to_cpu(udev->descriptor.idVendor) == USB_VID_AVERMEDIA) {
+		switch (le16_to_cpu(udev->descriptor.idProduct)) {
+		case USB_PID_AVERMEDIA_A825:
+		case USB_PID_AVERMEDIA_A835:
+		case USB_PID_AVERMEDIA_B835:
+		case USB_PID_AVERMEDIA_A333:
+		case USB_PID_AVERMEDIA_B867:
+		case USB_PID_AVERMEDIA_1867:
+		case USB_PID_AVERMEDIA_0337:
+		case USB_PID_AVERMEDIA_A867:
+		case USB_PID_AVERMEDIA_0867:
+		case USB_PID_AVERMEDIA_F337:
+		case USB_PID_AVERMEDIA_3867:
+			deb_info("%s: AverMedia A825/A835/B835/A333/A867: overriding config\n", __func__);
+			/* set correct IF */
+			for (i = 0; i < af9035_properties[0].num_adapters; i++) {
+				af9035_af9033_config[i].if_freq = 4570000;
+			}
+			break;
+		default:
+			break;
+		}
+	}
+
+	return ret;
+}
+
+static int af9035_aux_init(struct usb_device *d)
+{
+	int ret;
+	u8 tmp, i;
+
+	/* get demod crystal and ADC freqs */
+	ret = af9035_read_reg_bits_bis(d, LINK,
+		r_io_mux_pwron_clk_strap, io_mux_pwron_clk_strap_pos,
+		io_mux_pwron_clk_strap_len, &tmp);
+	if (ret)
+		goto error;
+
+	for (i = 0; i < af9035_properties[0].num_adapters; i++) {
+		af9035_af9033_config[i].crystal_clock =
+			clock_table[tmp].crystal;
+		af9035_af9033_config[i].adc_clock =
+			clock_table[tmp].adc;
+	}
+
+	/* write 2nd demod I2C address to device */
+	ret = af9035_write_reg_bis(d, LINK, 0x417f,
+		af9035_af9033_config[1].demod_address);
+	if (ret)
+		goto error;
+
+	/* enable / disable clock out for 2nd demod for power saving */
+	ret = af9035_write_reg_bis(d, LINK, p_reg_top_clkoen,
+		af9035_config.dual_mode);
+
+error:
+	return ret;
+}
+
+static int af9035_identify_state(struct usb_device *udev,
+				 struct dvb_usb_device_properties *props,
+				 struct dvb_usb_device_description **desc,
+				 int *cold)
+{
+	int ret;
+	u8 wbuf[1] = {1};
+	u8 rbuf[4];
+	struct af9035_req req = {CMD_QUERYINFO, 0, sizeof(wbuf), wbuf,
+		sizeof(rbuf), rbuf};
+
+	ret = af9035_rw_udev(udev, &req);
+	if (ret)
+		return ret;
+
+	deb_info("%s: reply:%02x %02x %02x %02x\n", __func__,
+		rbuf[0], rbuf[1], rbuf[2], rbuf[3]);
+	if (rbuf[0] || rbuf[1] || rbuf[2] || rbuf[3])
+		*cold = 0;
+	else
+		*cold = 1;
+
+	return ret;
+}
+
+static int af9035_af9033_frontend_attach(struct dvb_usb_adapter *adap)
+{
+	/* attach demodulator */
+#ifdef V4L2_REFACTORED_MFE_CODE
+	adap->fe_adap[0].fe = dvb_attach(af9033_attach, &af9035_af9033_config[adap->id],
+		&adap->dev->i2c_adap);
+
+	return adap->fe_adap[0].fe == NULL ? -ENODEV : 0;
+#else
+	adap->fe = dvb_attach(af9033_attach, &af9035_af9033_config[adap->id],
+		&adap->dev->i2c_adap);
+
+	return adap->fe == NULL ? -ENODEV : 0;
+#endif
+}
+
+static struct tua9001_config af9035_tua9001_config[] = {
+	{
+		.i2c_address = 0xc0,
+	} , {
+		.i2c_address = 0xc1,
+	}
+};
+
+static struct mxl5007t_config af9035_mxl5007t_config[] = {
+	{
+		.xtal_freq_hz = MxL_XTAL_24_MHZ,
+		.if_freq_hz = MxL_IF_4_57_MHZ,
+		.invert_if = 0,
+		.loop_thru_enable = 0,
+		.clk_out_enable = 0,
+		.clk_out_amp = MxL_CLKOUT_AMP_0_94V,
+		.no_probe = 1,
+		.no_reset = 1,
+	} , {
+		.xtal_freq_hz = MxL_XTAL_24_MHZ,
+		.if_freq_hz = MxL_IF_4_57_MHZ,
+		.invert_if = 0,
+		.loop_thru_enable = 3,
+		.clk_out_enable = 1,
+		.clk_out_amp = MxL_CLKOUT_AMP_0_94V,
+		.no_probe = 1,
+		.no_reset = 1,
+	}
+};
+
+static struct tda18218_config af9035_tda18218_config = {
+        .i2c_address = 0xc0,
+        .i2c_wr_max = 17,
+};
+
+static int af9035_tuner_attach(struct dvb_usb_adapter *adap)
+{
+	int ret;
+	deb_info("%s: \n", __func__);
+
+	switch (af9035_af9033_config[adap->id].tuner) {
+	case AF9033_TUNER_TUA9001:
+		af9035_af9033_config[adap->id].tuner_address = af9035_tua9001_config[adap->id].i2c_address;
+		af9035_af9033_config[adap->id].tuner_address += adap->id;
+		if (adap->id == 0) {
+			/* gpiot3 TUA9001 RESETN
+			   gpiot2 TUA9001 RXEN */
+			ret = af9035_write_reg_bits(adap->dev, LINK,
+				p_reg_top_gpiot2_en, reg_top_gpiot2_en_pos,
+				reg_top_gpiot2_en_len, 1);
+			ret = af9035_write_reg_bits(adap->dev, LINK,
+				p_reg_top_gpiot2_on, reg_top_gpiot2_on_pos,
+				reg_top_gpiot2_on_len, 1);
+			ret = af9035_write_reg_bits(adap->dev, LINK,
+				p_reg_top_gpiot3_en, reg_top_gpiot3_en_pos,
+				reg_top_gpiot3_en_len, 1);
+			ret = af9035_write_reg_bits(adap->dev, LINK,
+				p_reg_top_gpiot3_on, reg_top_gpiot3_on_pos,
+				reg_top_gpiot3_on_len, 1);
+
+			/* reset tuner */
+			ret = af9035_write_reg_bits(adap->dev, LINK, p_reg_top_gpiot3_o,
+				 reg_top_gpiot3_o_pos, reg_top_gpiot3_o_len, 0);
+			msleep(1);
+			ret = af9035_write_reg_bits(adap->dev, LINK, p_reg_top_gpiot3_o,
+				 reg_top_gpiot3_o_pos, reg_top_gpiot3_o_len, 1);
+
+			/* activate tuner - TODO: do that like I2C gate control */
+			ret = af9035_write_reg_bits(adap->dev, LINK, p_reg_top_gpiot2_o,
+				 reg_top_gpiot2_o_pos, reg_top_gpiot2_o_len, 1);
+		}
+
+#ifdef V4L2_REFACTORED_MFE_CODE
+		ret = dvb_attach(tua9001_attach, adap->fe_adap[0].fe, &adap->dev->i2c_adap,
+#else
+		ret = dvb_attach(tua9001_attach, adap->fe, &adap->dev->i2c_adap,
+#endif
+			&af9035_tua9001_config[adap->id]) == NULL ? -ENODEV : 0;
+
+		break;
+	case AF9033_TUNER_MXL5007t:
+		af9035_af9033_config[adap->id].tuner_address = 0xc0;
+		af9035_af9033_config[adap->id].tuner_address += adap->id;
+		if (adap->id == 0) {
+			ret = af9035_write_reg(adap->dev, LINK,
+				p_reg_top_gpioh12_en,
+				1);
+
+			ret = af9035_write_reg(adap->dev, LINK,
+				p_reg_top_gpioh12_on,
+				1);
+
+			ret = af9035_write_reg(adap->dev, LINK,
+				p_reg_top_gpioh12_o,
+				0);
+
+			msleep(30);
+
+			ret = af9035_write_reg(adap->dev, LINK,
+				p_reg_top_gpioh12_o,
+				1);
+
+			msleep(300);
+
+			ret = af9035_write_reg(adap->dev, LINK,
+				p_reg_top_gpioh4_en,
+				1);
+
+			ret = af9035_write_reg(adap->dev, LINK,
+				p_reg_top_gpioh4_on,
+				1);
+
+			ret = af9035_write_reg(adap->dev, LINK,
+				p_reg_top_gpioh4_o,
+				0);
+
+			ret = af9035_write_reg(adap->dev, LINK,
+				p_reg_top_gpioh3_en,
+				1);
+
+			ret = af9035_write_reg(adap->dev, LINK,
+				p_reg_top_gpioh3_on,
+				1);
+
+			ret = af9035_write_reg(adap->dev, LINK,
+				p_reg_top_gpioh3_o,
+				1);
+		}
+
+#ifdef V4L2_REFACTORED_MFE_CODE
+		ret = dvb_attach(mxl5007t_attach, adap->fe_adap[0].fe, &adap->dev->i2c_adap,
+#else
+		ret = dvb_attach(mxl5007t_attach, adap->fe, &adap->dev->i2c_adap,
+#endif
+			af9035_af9033_config[adap->id].tuner_address,
+			&af9035_mxl5007t_config[adap->id]) == NULL ? -ENODEV : 0;
+
+		break;
+          case AF9033_TUNER_TDA18218:
+                  af9035_af9033_config[adap->id].tuner_address = af9035_tua9001_config[adap->id].i2c_address;
+                  af9035_af9033_config[adap->id].tuner_address += adap->id;
+                  if (adap->id == 0) {
+                  /* gpiot3 TUA9001 RESETN
+                  gpiot2 TUA9001 RXEN */
+                  ret = af9035_write_reg_bits(adap->dev, LINK,
+                          p_reg_top_gpiot2_en, reg_top_gpiot2_en_pos,
+                          reg_top_gpiot2_en_len, 1);
+                  ret = af9035_write_reg_bits(adap->dev, LINK,
+                          p_reg_top_gpiot2_on, reg_top_gpiot2_on_pos,
+                          reg_top_gpiot2_on_len, 1);
+                  ret = af9035_write_reg_bits(adap->dev, LINK,
+                          p_reg_top_gpiot3_en, reg_top_gpiot3_en_pos,
+                          reg_top_gpiot3_en_len, 1);
+                  ret = af9035_write_reg_bits(adap->dev, LINK,
+                          p_reg_top_gpiot3_on, reg_top_gpiot3_on_pos,
+                          reg_top_gpiot3_on_len, 1);
+
+                  /* reset tuner */
+                  ret = af9035_write_reg_bits(adap->dev, LINK, p_reg_top_gpiot3_o,
+                          reg_top_gpiot3_o_pos, reg_top_gpiot3_o_len, 0);
+                  msleep(1);
+                  ret = af9035_write_reg_bits(adap->dev, LINK, p_reg_top_gpiot3_o,
+                          reg_top_gpiot3_o_pos, reg_top_gpiot3_o_len, 1);
+
+                   /* activate tuner - TODO: do that like I2C gate control */
+                   ret = af9035_write_reg_bits(adap->dev, LINK, p_reg_top_gpiot2_o,
+                           reg_top_gpiot2_o_pos, reg_top_gpiot2_o_len, 1);
+                   }
+
+#ifdef V4L2_REFACTORED_MFE_CODE
+                   ret = dvb_attach(tda18218_attach, adap->fe_adap[0].fe, &adap->dev->i2c_adap,
+#else
+                   ret = dvb_attach(tda18218_attach, adap->fe, &adap->dev->i2c_adap,
+#endif
+                           &af9035_tda18218_config) == NULL ? -ENODEV : 0;
+                   break;
+	default:
+		ret = -ENODEV;
+		err("unknown tuner ID:%d",
+			af9035_af9033_config[adap->id].tuner);
+	}
+
+	return ret;
+}
+
+enum af9035_usb_table_entry {
+	AFATECH_AF9035_1000,
+	AFATECH_AF9035_1001,
+	AFATECH_AF9035_1002,
+	AFATECH_AF9035_1003,
+	AFATECH_AF9035_9035,
+	TERRATEC_CINERGY_T_STICK,
+	TERRATEC_CINERGY_T_STICK_2,
+	AVERMEDIA_TWINSTAR,
+	AVERMEDIA_VOLAR_HD,
+	AVERMEDIA_VOLAR_HD_PRO,
+#ifdef ENABLE_A867_DEVICES
+	AVERMEDIA_A333,
+	AVERMEDIA_B867,
+	AVERMEDIA_1867,
+	AVERMEDIA_0337,
+	AVERMEDIA_A867,
+	AVERMEDIA_0867,
+	AVERMEDIA_F337,
+	AVERMEDIA_3867,
+#endif
+};
+
+static struct usb_device_id af9035_usb_table[] = {
+	[AFATECH_AF9035_1000] = {USB_DEVICE(USB_VID_AFATECH,
+				USB_PID_AFATECH_AF9035_1000)},
+	[AFATECH_AF9035_1001] = {USB_DEVICE(USB_VID_AFATECH,
+				USB_PID_AFATECH_AF9035_1001)},
+	[AFATECH_AF9035_1002] = {USB_DEVICE(USB_VID_AFATECH,
+				USB_PID_AFATECH_AF9035_1002)},
+	[AFATECH_AF9035_1003] = {USB_DEVICE(USB_VID_AFATECH,
+				USB_PID_AFATECH_AF9035_1003)},
+	[AFATECH_AF9035_9035] = {USB_DEVICE(USB_VID_AFATECH,
+				USB_PID_AFATECH_AF9035_9035)},
+	[TERRATEC_CINERGY_T_STICK] = {USB_DEVICE(USB_VID_TERRATEC,
+				USB_PID_TERRATEC_CINERGY_T_STICK)},
+	[TERRATEC_CINERGY_T_STICK_2] = {USB_DEVICE(USB_VID_TERRATEC,
+				USB_PID_TERRATEC_CINERGY_T_STICK_2)},
+	[AVERMEDIA_TWINSTAR] = {USB_DEVICE(USB_VID_AVERMEDIA,
+				USB_PID_AVERMEDIA_A825)},
+	[AVERMEDIA_VOLAR_HD] = {USB_DEVICE(USB_VID_AVERMEDIA,
+				USB_PID_AVERMEDIA_A835)},
+	[AVERMEDIA_VOLAR_HD_PRO] = {USB_DEVICE(USB_VID_AVERMEDIA,
+				USB_PID_AVERMEDIA_B835)},
+#ifdef ENABLE_A867_DEVICES
+	[AVERMEDIA_A333] = {USB_DEVICE(USB_VID_AVERMEDIA,
+				USB_PID_AVERMEDIA_A333)},
+	[AVERMEDIA_B867] = {USB_DEVICE(USB_VID_AVERMEDIA,
+				USB_PID_AVERMEDIA_B867)},
+	[AVERMEDIA_1867] = {USB_DEVICE(USB_VID_AVERMEDIA,
+				USB_PID_AVERMEDIA_1867)},
+	[AVERMEDIA_0337] = {USB_DEVICE(USB_VID_AVERMEDIA,
+				USB_PID_AVERMEDIA_0337)},
+	[AVERMEDIA_A867] = {USB_DEVICE(USB_VID_AVERMEDIA,
+				USB_PID_AVERMEDIA_A867)},
+	[AVERMEDIA_0867] = {USB_DEVICE(USB_VID_AVERMEDIA,
+				USB_PID_AVERMEDIA_0867)},
+	[AVERMEDIA_F337] = {USB_DEVICE(USB_VID_AVERMEDIA,
+				USB_PID_AVERMEDIA_F337)},
+	[AVERMEDIA_3867] = {USB_DEVICE(USB_VID_AVERMEDIA,
+				USB_PID_AVERMEDIA_3867)},
+#endif
+	{ },
+};
+
+MODULE_DEVICE_TABLE(usb, af9035_usb_table);
+
+static struct dvb_usb_device_properties af9035_properties[] = {
+	{
+		.caps = DVB_USB_IS_AN_I2C_ADAPTER,
+
+		.usb_ctrl = DEVICE_SPECIFIC,
+		.download_firmware = af9035_download_firmware,
+		.firmware = "dvb-usb-af9035-01.fw",
+		.no_reconnect = 1,
+
+		.size_of_priv = 0,
+
+		.adapter = {
+			{
+#ifdef V4L2_REFACTORED_MFE_CODE
+			.num_frontends = 1,
+			.fe = {{
+#endif
+				.frontend_attach =
+					af9035_af9033_frontend_attach,
+				.tuner_attach = af9035_tuner_attach,
+				.stream = {
+					.type = USB_BULK,
+					.count = 4,
+					.endpoint = 0x84,
+				},
+#ifdef V4L2_REFACTORED_MFE_CODE
+			}},
+#endif
+			},
+			{
+#ifdef V4L2_REFACTORED_MFE_CODE
+			.num_frontends = 1,
+			.fe = {{
+#endif
+				.frontend_attach =
+					af9035_af9033_frontend_attach,
+				.tuner_attach = af9035_tuner_attach,
+				.stream = {
+					.type = USB_BULK,
+					.count = 4,
+					.endpoint = 0x85,
+					.u = {
+						.bulk = {
+							.buffersize =
+						TS_USB20_FRAME_SIZE,
+						}
+					}
+				},
+#ifdef V4L2_REFACTORED_MFE_CODE
+			}},
+#endif
+			}
+		},
+
+		.identify_state = af9035_identify_state,
+
+		.i2c_algo = &af9035_i2c_algo,
+
+#ifdef ENABLE_A867_DEVICES
+		.num_device_descs = 6,
+#else
+		.num_device_descs = 4,
+#endif
+		.devices = {
+			{
+				.name = "Afatech AF9035 DVB-T USB2.0 stick - By ItalySat.it",
+				.cold_ids = {&af9035_usb_table[AFATECH_AF9035_1000],
+					     &af9035_usb_table[AFATECH_AF9035_1001],
+					     &af9035_usb_table[AFATECH_AF9035_1002],
+					     &af9035_usb_table[AFATECH_AF9035_1003],
+					     &af9035_usb_table[AFATECH_AF9035_9035], NULL},
+				.warm_ids = {NULL},
+			},
+			{
+				.name = "TerraTec Cinergy T Stick - By ItalySat.it",
+				.cold_ids = {&af9035_usb_table[TERRATEC_CINERGY_T_STICK],
+					     &af9035_usb_table[TERRATEC_CINERGY_T_STICK_2], NULL},
+				.warm_ids = {NULL},
+			},
+			{
+				.name = "Avermedia TwinStar - By ItalySat.it",
+				.cold_ids = {&af9035_usb_table[AVERMEDIA_TWINSTAR], NULL},
+				.warm_ids = {NULL},
+			},
+			{
+				.name = "Avermedia AverTV Volar HD & HD PRO (A835) - By ItalySat.it",
+				.cold_ids = {&af9035_usb_table[AVERMEDIA_VOLAR_HD],
+					     &af9035_usb_table[AVERMEDIA_VOLAR_HD_PRO], NULL},
+				.warm_ids = {NULL},
+			},
+#ifdef ENABLE_A867_DEVICES
+			{
+				.name = "Avermedia A333 - By ItalySat.it",
+				.cold_ids = {&af9035_usb_table[AVERMEDIA_A333],
+					     &af9035_usb_table[AVERMEDIA_B867], NULL},
+				.warm_ids = {NULL},
+			},
+			{
+				.name = "Avermedia A867 - By ItalySat.it",
+				.cold_ids = {&af9035_usb_table[AVERMEDIA_1867],
+					     &af9035_usb_table[AVERMEDIA_0337],
+					     &af9035_usb_table[AVERMEDIA_A867],
+					     &af9035_usb_table[AVERMEDIA_0867],
+					     &af9035_usb_table[AVERMEDIA_F337],
+					     &af9035_usb_table[AVERMEDIA_3867], NULL},
+				.warm_ids = {NULL},
+			},
+#endif
+		}
+	},
+};
+
+static int af9035_usb_probe(struct usb_interface *intf,
+			    const struct usb_device_id *id)
+{
+	int ret = 0;
+	struct dvb_usb_device *d = NULL;
+	struct usb_device *udev = interface_to_usbdev(intf);
+	u8 i;
+
+	deb_info("%s: interface:%d\n", __func__,
+		intf->cur_altsetting->desc.bInterfaceNumber);
+
+	/* interface 0 is used by DVB-T receiver and
+	   interface 1 is for remote controller (HID) */
+	if (intf->cur_altsetting->desc.bInterfaceNumber == 0) {
+		ret = af9035_read_config(udev);
+		if (ret)
+			return ret;
+
+		ret = af9035_aux_init(udev);
+		if (ret)
+			return ret;
+
+		for (i = 0; i < af9035_properties_count; i++) {
+			ret = dvb_usb_device_init(intf, &af9035_properties[i],
+				THIS_MODULE, &d, adapter_nr);
+			if (!ret)
+				break;
+			if (ret != -ENODEV)
+				return ret;
+		}
+		if (ret)
+			return ret;
+
+		if (d)
+			ret = af9035_init(d);
+	}
+
+	return ret;
+}
+
+/* usb specific object needed to register this driver with the usb subsystem */
+static struct usb_driver af9035_usb_driver = {
+	.name = "dvb_usb_af9035",
+	.probe = af9035_usb_probe,
+	.disconnect = dvb_usb_device_exit,
+	.id_table = af9035_usb_table,
+};
+
+/* module stuff */
+static int __init af9035_usb_module_init(void)
+{
+	int ret;
+	ret = usb_register(&af9035_usb_driver);
+	if (ret)
+		err("module init failed:%d", ret);
+
+	return ret;
+}
+
+static void __exit af9035_usb_module_exit(void)
+{
+	/* deregister this driver from the USB subsystem */
+	usb_deregister(&af9035_usb_driver);
+}
+
+module_init(af9035_usb_module_init);
+module_exit(af9035_usb_module_exit);
+
+MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
+MODULE_DESCRIPTION("Afatech AF9035 driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/dvb-usb/af9035.h b/drivers/media/dvb/dvb-usb/af9035.h
new file mode 100644
index 0000000..7c0c971
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/af9035.h
@@ -0,0 +1,187 @@
+/*
+ * Afatech AF9035 DVB USB driver
+ *
+ * Copyright (C) 2008 Afatech
+ * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 2 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ * Thanks to TerraTec for a support received.
+ */
+
+#ifndef AF9035_H
+#define AF9035_H
+#include "af9033_reg.h"
+
+#define DVB_USB_LOG_PREFIX "af9035"
+#include "dvb-usb.h"
+
+#define deb_info(args...) dprintk(dvb_usb_af9035_debug, 0x01, args)
+#define deb_rc(args...)   dprintk(dvb_usb_af9035_debug, 0x02, args)
+#define deb_xfer(args...) dprintk(dvb_usb_af9035_debug, 0x04, args)
+#define deb_reg(args...)  dprintk(dvb_usb_af9035_debug, 0x08, args)
+#define deb_i2c(args...)  dprintk(dvb_usb_af9035_debug, 0x10, args)
+#define deb_fw(args...)   dprintk(dvb_usb_af9035_debug, 0x20, args)
+
+#define AF9035_USB_TIMEOUT 2000
+
+#define LINK 0x00
+#define OFDM 0x80
+
+#define TS_MODE_SINGLE   0
+#define TS_MODE_DCA_PIP  1
+#define TS_MODE_DCA      2 /* any other value than 0, 1, 3 (?) */
+#define TS_MODE_PIP      3
+
+#define TS_PACKET_SIZE            188
+#define TS_USB20_PACKET_COUNT     348
+#define TS_USB20_FRAME_SIZE       (TS_PACKET_SIZE*TS_USB20_PACKET_COUNT)
+#define TS_USB11_PACKET_COUNT      21
+#define TS_USB11_FRAME_SIZE       (TS_PACKET_SIZE*TS_USB11_PACKET_COUNT)
+#define TS_USB20_MAX_PACKET_SIZE  512
+#define TS_USB11_MAX_PACKET_SIZE   64
+
+/* EEPROM locations */
+#define GANY_ONLY 0x42f5
+#define EEPROM_FLB_OFS  8
+#define EEPROM_BASE_ADDR  (GANY_ONLY + EEPROM_FLB_OFS)
+#define EEPROM_SHIFT      (0x10)
+
+#define EEPROM_IR_MODE    (EEPROM_BASE_ADDR+0x10)   /* 00:disabled, 01:HID */
+#define EEPROM_SELSUSPEND (EEPROM_BASE_ADDR+0x28)   /* selective suspend mode */
+#define EEPROM_TS_MODE    (EEPROM_BASE_ADDR+0x28+1) /* 0:one ts, 1:dual ts */
+#define EEPROM_2WIREADDR  (EEPROM_BASE_ADDR+0x28+2) /* 2nd demod I2C addr */
+#define EEPROM_SUSPEND    (EEPROM_BASE_ADDR+0x28+3) /* suspend mode */
+#define EEPROM_IR_TYPE    (EEPROM_BASE_ADDR+0x28+4) /* 0:NEC, 1:RC6 */
+
+#define EEPROM_SAW_BW1    (EEPROM_BASE_ADDR+0x28+5)
+#define EEPROM_XTAL1      (EEPROM_BASE_ADDR+0x28+6)
+#define EEPROM_SPECINV1   (EEPROM_BASE_ADDR+0x28+7)
+#define EEPROM_TUNER_ID1  (EEPROM_BASE_ADDR+0x30+4)
+#define EEPROM_IFFREQL1   (EEPROM_BASE_ADDR+0x30)
+#define EEPROM_IFFREQH1   (EEPROM_BASE_ADDR+0x30+1)
+#define EEPROM_IF1L1      (EEPROM_BASE_ADDR+0x30+2)
+#define EEPROM_IF1H1      (EEPROM_BASE_ADDR+0x30+3)
+
+#define EEPROM_SAW_BW2    (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x28+5)
+#define EEPROM_XTAL2      (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x28+6)
+#define EEPROM_SPECINV2   (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x28+7)
+#define EEPROM_TUNER_ID2  (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x30+4)
+#define EEPROM_IFFREQL2   (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x30)
+#define EEPROM_IFFREQH2   (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x30+1)
+#define EEPROM_IF1L2      (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x30+2)
+#define EEPROM_IF1H2      (EEPROM_BASE_ADDR+EEPROM_SHIFT+0x30+3)
+
+struct af9035_clock {
+	u32 crystal;
+	u32 adc;
+};
+
+static struct af9035_clock clock_table[] = {
+	{20480000, 20480000},  /*     FPGA */
+	{16384000, 20480000},  /* 16.38MHz */
+	{20480000, 20480000},  /* 20.48MHz */
+	{36000000, 20250000},  /* 36.00MHz */
+	{30000000, 20156250},  /* 30.00MHz */
+	{26000000, 20583333},  /* 26.00MHz */
+	{28000000, 20416667},  /* 28.00MHz */
+	{32000000, 20500000},  /* 32.00MHz */
+	{34000000, 20187500},  /* 34.00MHz */
+	{24000000, 20500000},  /* 24.00MHz */
+	{22000000, 20625000},  /* 22.00MHz */
+	{12000000, 20250000},  /* 12.00MHz */
+};
+
+struct af9035_req {
+	u8  cmd;
+	u8  mbox;
+	u8  wlen;
+	u8  *wbuf;
+	u8  rlen;
+	u8  *rbuf;
+};
+
+/* USB commands */
+#define CMD_REG_DEMOD_READ          0x00
+#define CMD_REG_DEMOD_WRITE         0x01
+#define CMD_REG_TUNER_READ          0x02
+#define CMD_REG_TUNER_WRITE         0x03
+#define CMD_REG_EEPROM_READ         0x04
+#define CMD_REG_EEPROM_WRITE        0x05
+#define CMD_VAR_READ                0x08
+#define CMD_VAR_WRITE               0x09
+
+#define CMD_DATA_READ               0x06
+
+#define CMD_PLATFORM_GET            0x0A
+#define CMD_PLATFORM_SET            0x0B
+#define CMD_IP_CACHE                0x0D
+#define CMD_IP_ADD                  0x0E
+#define CMD_IP_REMOVE               0x0F
+#define CMD_PID_ADD                 0x10
+#define CMD_PID_REMOVE              0x11
+/* get SI/PSI table for specific PID "once" */
+#define CMD_SIPSI_GET               0x12
+#define CMD_SIPSI_MPE_RESET         0x13
+#define CMD_H_PID_ADD               0x15
+#define CMD_H_PID_REMOVE            0x16
+#define CMD_ABORT                   0x17
+#define CMD_IR_GET                  0x18
+#define CMD_IR_SET                  0x19
+#define CMD_FW_DOWNLOAD_BEGIN       0x24
+#define CMD_FW_DOWNLOAD             0x21
+#define CMD_FW_DOWNLOAD_END         0x25
+#define CMD_QUERYINFO               0x22
+#define CMD_BOOT                    0x23
+#define CMD_REBOOT                  0x23
+#define CMD_RUN_CODE                0x26
+#define CMD_SCATTER_READ            0x28
+#define CMD_SCATTER_WRITE           0x29
+#define CMD_GENERIC_READ            0x2A
+#define CMD_GENERIC_WRITE           0x2B
+
+#define CMD_SERVICES_GET            0x83
+#define CMD_COMPONENT_ADD           0x86
+#define CMD_COMPONENT_REMOVE        0x87
+#define CMD_FIG_ADD                 0x88
+#define CMD_FIG_REMOVE              0x89
+
+/* this Linux driver does not implement usage of "short command" at all */
+#define CMD_SHORT_REG_DEMOD_READ    0x02
+#define CMD_SHORT_REG_DEMOD_WRITE   0X03
+#define CMD_SHORT_REG_TUNER_READ    0x04
+#define CMD_SHORT_REG_TUNER_WRITE   0X05
+
+struct af9035_config {
+	u8 dual_mode:1;
+	u16 mt2060_if1[2];
+};
+
+struct af9035_segment {
+#define SEGMENT_FW_DOWNLOAD 0
+#define SEGMENT_ROM_COPY    1
+#define SEGMENT_DIRECT_CMD  2
+	u8 type;
+	u32 len;
+};
+
+struct af9035_firmware_header {
+#define SEGMENT_MAX_COUNT 50
+	u8 segment_count;
+	struct af9035_segment segment[SEGMENT_MAX_COUNT];
+};
+
+#endif
diff --git a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
index 397d8f2..8444118 100644
--- a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
+++ b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
@@ -76,6 +76,11 @@
 #define USB_PID_AFATECH_AF9005				0x9020
 #define USB_PID_AFATECH_AF9015_9015			0x9015
 #define USB_PID_AFATECH_AF9015_9016			0x9016
+#define USB_PID_AFATECH_AF9035_1000			0x1000
+#define USB_PID_AFATECH_AF9035_1001			0x1001
+#define USB_PID_AFATECH_AF9035_1002			0x1002
+#define USB_PID_AFATECH_AF9035_1003			0x1003
+#define USB_PID_AFATECH_AF9035_9035			0x9035
 #define USB_PID_TREKSTOR_DVBT				0x901b
 #define USB_VID_ALINK_DTU				0xf170
 #define USB_PID_ANSONIC_DVBT_USB			0x6000
@@ -221,6 +226,17 @@
 #define USB_PID_AVERMEDIA_A850T				0x850b
 #define USB_PID_AVERMEDIA_A805				0xa805
 #define USB_PID_AVERMEDIA_A815M				0x815a
+#define USB_PID_AVERMEDIA_A825				0x0825
+#define USB_PID_AVERMEDIA_A835				0xa835
+#define USB_PID_AVERMEDIA_B835				0xb835
+#define USB_PID_AVERMEDIA_A333				0xa333
+#define USB_PID_AVERMEDIA_B867				0xb867
+#define USB_PID_AVERMEDIA_1867				0x1867
+#define USB_PID_AVERMEDIA_0337				0x0337
+#define USB_PID_AVERMEDIA_A867				0xa867
+#define USB_PID_AVERMEDIA_0867				0x0867
+#define USB_PID_AVERMEDIA_F337				0xf337
+#define USB_PID_AVERMEDIA_3867				0x3867
 #define USB_PID_TECHNOTREND_CONNECT_S2400               0x3006
 #define USB_PID_TECHNOTREND_CONNECT_CT3650		0x300d
 #define USB_PID_TERRATEC_CINERGY_DT_XS_DIVERSITY	0x005a
@@ -230,6 +246,8 @@
 #define USB_PID_TERRATEC_CINERGY_T_EXPRESS		0x0062
 #define USB_PID_TERRATEC_CINERGY_T_XXS			0x0078
 #define USB_PID_TERRATEC_CINERGY_T_XXS_2		0x00ab
+#define USB_PID_TERRATEC_CINERGY_T_STICK		0x0093
+#define USB_PID_TERRATEC_CINERGY_T_STICK_2		0x00aa
 #define USB_PID_TERRATEC_H7				0x10b4
 #define USB_PID_TERRATEC_H7_2				0x10a3
 #define USB_PID_TERRATEC_T3				0x10a0
diff --git a/drivers/media/dvb/dvb-usb/dvb-usb-init.c b/drivers/media/dvb/dvb-usb/dvb-usb-init.c
index 169196e..c741973 100644
--- a/drivers/media/dvb/dvb-usb/dvb-usb-init.c
+++ b/drivers/media/dvb/dvb-usb/dvb-usb-init.c
@@ -18,7 +18,7 @@ int dvb_usb_debug;
 module_param_named(debug, dvb_usb_debug, int, 0644);
 MODULE_PARM_DESC(debug, "set debugging level (1=info,xfer=2,pll=4,ts=8,err=16,rc=32,fw=64,mem=128,uxfer=256  (or-able))." DVB_USB_DEBUG_STATUS);
 
-int dvb_usb_disable_rc_polling;
+int dvb_usb_disable_rc_polling = 1;
 module_param_named(disable_rc_polling, dvb_usb_disable_rc_polling, int, 0644);
 MODULE_PARM_DESC(disable_rc_polling, "disable remote control polling (default: 0).");
 
diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig
index 2124670..903a1da 100644
--- a/drivers/media/dvb/frontends/Kconfig
+++ b/drivers/media/dvb/frontends/Kconfig
@@ -397,6 +397,13 @@ config DVB_AF9013
 	help
 	  Say Y when you want to support this frontend.
 
+config DVB_AF9033
+	tristate "Afatech AF9033 demodulator"
+	depends on DVB_CORE && I2C
+	default m
+	help
+	  Say Y when you want to support this frontend.
+
 config DVB_EC100
 	tristate "E3C EC100"
 	depends on DVB_CORE && I2C
diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile
index 86fa808..ff463a6 100644
--- a/drivers/media/dvb/frontends/Makefile
+++ b/drivers/media/dvb/frontends/Makefile
@@ -73,6 +73,7 @@ obj-$(CONFIG_DVB_LGS8GXX) += lgs8gxx.o
 obj-$(CONFIG_DVB_ATBM8830) += atbm8830.o
 obj-$(CONFIG_DVB_DUMMY_FE) += dvb_dummy_fe.o
 obj-$(CONFIG_DVB_AF9013) += af9013.o
+obj-$(CONFIG_DVB_AF9033) += af9033.o
 obj-$(CONFIG_DVB_CX24116) += cx24116.o
 obj-$(CONFIG_DVB_SI21XX) += si21xx.o
 obj-$(CONFIG_DVB_STV0288) += stv0288.o
diff --git a/drivers/media/dvb/frontends/af9033.c b/drivers/media/dvb/frontends/af9033.c
new file mode 100644
index 0000000..747931f
--- /dev/null
+++ b/drivers/media/dvb/frontends/af9033.c
@@ -0,0 +1,1957 @@
+/*
+ * Afatech AF9033 demodulator driver
+ *
+ * Copyright (C) 2008 Afatech
+ * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 2 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ * Thanks to TerraTec for a support received.
+ */
+
+#include "dvb_frontend.h"
+#include <linux/slab.h>         /* for kzalloc/kfree */
+#include <linux/version.h>
+#include "af9033_priv.h"
+#include "af9033.h"
+#include "af9033_reg.h"
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0)) || ((defined V4L2_VERSION) && (V4L2_VERSION >= 197120))
+/* all DVB frontend drivers now work directly with the DVBv5
+ * structure. This warrants that all drivers will be
+ * getting/setting frontend parameters on a consistent way, in
+ * order to avoid copying data from/to the DVBv3 structs
+ * without need.
+ */
+#define V4L2_ONLY_DVB_V5
+#endif
+
+static int af9033_debug;
+module_param_named(debug, af9033_debug, int, 0644);
+MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
+static int af9033_snrdb;
+module_param_named(snrdb, af9033_snrdb, int, 0644);
+MODULE_PARM_DESC(snrdb, "Turn on/off SNR output as dBx10 (default:off).");
+
+struct af9033_state {
+	struct i2c_adapter *i2c;
+	struct dvb_frontend frontend;
+	struct af9033_config config;
+
+	u16 signal_strength;
+	u32 ber;
+	u32 ucblocks;
+	u16 snr;
+	u32 frequency;
+	unsigned long next_statistics_check;
+};
+
+static u8 regmask[8] = {0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xff};
+
+/* write multiple registers */
+static int af9033_write_regs(struct af9033_state *state, u8 mbox, u16 reg,
+	u8 *val, u8 len)
+{
+	u8 buf[3+len];
+	struct i2c_msg msg = {
+		.addr = state->config.demod_address,
+		.flags = 0,
+		.len = sizeof(buf),
+		.buf = buf };
+
+	buf[0] = mbox;
+	buf[1] = reg >> 8;
+	buf[2] = reg & 0xff;
+	memcpy(&buf[3], val, len);
+
+	if (i2c_transfer(state->i2c, &msg, 1) != 1) {
+		warn("I2C write failed reg:%04x len:%d", reg, len);
+		return -EREMOTEIO;
+	}
+	return 0;
+}
+
+/* read multiple registers */
+static int af9033_read_regs(struct af9033_state *state, u8 mbox, u16 reg,
+	u8 *val, u8 len)
+{
+	u8 obuf[3] = {mbox, reg >> 8, reg & 0xff};
+	struct i2c_msg msg[2] = {
+		{
+			.addr = state->config.demod_address,
+			.flags = 0,
+			.len = sizeof(obuf),
+			.buf = obuf
+		}, {
+			.addr = state->config.demod_address,
+			.flags = I2C_M_RD,
+			.len = len,
+			.buf = val
+		}
+	};
+
+	if (i2c_transfer(state->i2c, msg, 2) != 2) {
+		warn("I2C read failed reg:%04x", reg);
+		return -EREMOTEIO;
+	}
+	return 0;
+}
+
+/* write single register */
+static int af9033_write_reg(struct af9033_state *state, u8 mbox, u16 reg,
+	u8 val)
+{
+	return af9033_write_regs(state, mbox, reg, &val, 1);
+}
+
+/* read single register */
+static int af9033_read_reg(struct af9033_state *state, u8 mbox, u16 reg,
+	u8 *val)
+{
+	return af9033_read_regs(state, mbox, reg, val, 1);
+}
+
+/* write single register bits */
+static int af9033_write_reg_bits(struct af9033_state *state, u8 mbox, u16 reg,
+	u8 pos, u8 len, u8 val)
+{
+	int ret;
+	u8 tmp, mask;
+
+	ret = af9033_read_reg(state, mbox, reg, &tmp);
+	if (ret)
+		return ret;
+
+	mask = regmask[len - 1] << pos;
+	tmp = (tmp & ~mask) | ((val << pos) & mask);
+
+	return af9033_write_reg(state, mbox, reg, tmp);
+}
+
+/* read single register bits */
+static int af9033_read_reg_bits(struct af9033_state *state, u8 mbox, u16 reg,
+	u8 pos, u8 len, u8 *val)
+{
+	int ret;
+	u8 tmp;
+
+	ret = af9033_read_reg(state, mbox, reg, &tmp);
+	if (ret)
+		return ret;
+
+	*val = (tmp >> pos) & regmask[len - 1];
+	return 0;
+}
+
+static u32 af913_div(u32 a, u32 b, u32 x)
+{
+	u32 r = 0, c = 0, i;
+	deb_info("%s: a:%d b:%d x:%d\n", __func__, a, b, x);
+
+	if (a > b) {
+		c = a / b;
+		a = a - c * b;
+	}
+
+	for (i = 0; i < x; i++) {
+		if (a >= b) {
+			r += 1;
+			a -= b;
+		}
+		a <<= 1;
+		r <<= 1;
+	}
+	r = (c << (u32)x) + r;
+
+	deb_info("%s: a:%d b:%d x:%d r:%d r:%x\n", __func__, a, b, x, r, r);
+	return r;
+}
+
+#ifdef V4L2_ONLY_DVB_V5
+static int af9033_set_coeff(struct af9033_state *state, u32 bw)
+#else
+static int af9033_set_coeff(struct af9033_state *state, fe_bandwidth_t bw)
+#endif
+{
+	int ret = 0;
+	u8 tmp, i = 0;
+	u8 buf[36];
+	u32 uninitialized_var(coeff1_2048nu);
+	u32 uninitialized_var(coeff1_4096nu);
+	u32 uninitialized_var(coeff1_8191nu);
+	u32 uninitialized_var(coeff1_8192nu);
+	u32 uninitialized_var(coeff1_8193nu);
+	u32 uninitialized_var(coeff2_2k);
+	u32 uninitialized_var(coeff2_4k);
+	u32 uninitialized_var(coeff2_8k);
+	u16 uninitialized_var(bfsfcw_fftindex_ratio);
+	u16 uninitialized_var(fftindex_bfsfcw_ratio);
+	deb_info("%s: adc_clock:%d bw:%d\n", __func__,
+		state->config.adc_clock, bw);
+
+#ifdef V4L2_ONLY_DVB_V5
+#define BANDWIDTH_5_MHZ 5000000
+#define BANDWIDTH_6_MHZ 6000000
+#define BANDWIDTH_7_MHZ 7000000
+#define BANDWIDTH_8_MHZ 8000000
+#endif
+
+	switch (state->config.adc_clock) {
+	case 20156250:
+		switch (bw) {
+#if 0 /* keep */
+		case BANDWIDTH_5_MHZ:
+			coeff1_2048nu = 0x02449b5c;
+			coeff1_4096nu = 0x01224dae;
+			coeff1_8191nu = 0x00912b60;
+			coeff1_8192nu = 0x009126d7;
+			coeff1_8193nu = 0x0091224e;
+			coeff2_2k = 0x01224dae;
+			coeff2_4k = 0x009126d7;
+			coeff2_8k = 0x0048936b;
+			bfsfcw_fftindex_ratio = 0x0387;
+			fftindex_bfsfcw_ratio = 0x0122;
+			break;
+#endif
+		case BANDWIDTH_6_MHZ:
+			coeff1_2048nu = 0x02b8ba6e;
+			coeff1_4096nu = 0x015c5d37;
+			coeff1_8191nu = 0x00ae340d;
+			coeff1_8192nu = 0x00ae2e9b;
+			coeff1_8193nu = 0x00ae292a;
+			coeff2_2k = 0x015c5d37;
+			coeff2_4k = 0x00ae2e9b;
+			coeff2_8k = 0x0057174e;
+			bfsfcw_fftindex_ratio = 0x02f1;
+			fftindex_bfsfcw_ratio = 0x015c;
+			break;
+		case BANDWIDTH_7_MHZ:
+			coeff1_2048nu = 0x032cd980;
+			coeff1_4096nu = 0x01966cc0;
+			coeff1_8191nu = 0x00cb3cba;
+			coeff1_8192nu = 0x00cb3660;
+			coeff1_8193nu = 0x00cb3007;
+			coeff2_2k = 0x01966cc0;
+			coeff2_4k = 0x00cb3660;
+			coeff2_8k = 0x00659b30;
+			bfsfcw_fftindex_ratio = 0x0285;
+			fftindex_bfsfcw_ratio = 0x0196;
+			break;
+		case BANDWIDTH_8_MHZ:
+			coeff1_2048nu = 0x03a0f893;
+			coeff1_4096nu = 0x01d07c49;
+			coeff1_8191nu = 0x00e84567;
+			coeff1_8192nu = 0x00e83e25;
+			coeff1_8193nu = 0x00e836e3;
+			coeff2_2k = 0x01d07c49;
+			coeff2_4k = 0x00e83e25;
+			coeff2_8k = 0x00741f12;
+			bfsfcw_fftindex_ratio = 0x0234;
+			fftindex_bfsfcw_ratio = 0x01d0;
+			break;
+		default:
+			ret = -EINVAL;
+		}
+		break;
+	case 20187500:
+		switch (bw) {
+#if 0 /* keep */
+		case BANDWIDTH_5_MHZ:
+			coeff1_2048nu = 0x0243b546;
+			coeff1_4096nu = 0x0121daa3;
+			coeff1_8191nu = 0x0090f1d9;
+			coeff1_8192nu = 0x0090ed51;
+			coeff1_8193nu = 0x0090e8ca;
+			coeff2_2k = 0x0121daa3;
+			coeff2_4k = 0x0090ed51;
+			coeff2_8k = 0x004876a9;
+			bfsfcw_fftindex_ratio = 0x0388;
+			fftindex_bfsfcw_ratio = 0x0122;
+			break;
+#endif
+		case BANDWIDTH_6_MHZ:
+			coeff1_2048nu = 0x02b7a654;
+			coeff1_4096nu = 0x015bd32a;
+			coeff1_8191nu = 0x00adef04;
+			coeff1_8192nu = 0x00ade995;
+			coeff1_8193nu = 0x00ade426;
+			coeff2_2k = 0x015bd32a;
+			coeff2_4k = 0x00ade995;
+			coeff2_8k = 0x0056f4ca;
+			bfsfcw_fftindex_ratio = 0x02f2;
+			fftindex_bfsfcw_ratio = 0x015c;
+			break;
+		case BANDWIDTH_7_MHZ:
+			coeff1_2048nu = 0x032b9761;
+			coeff1_4096nu = 0x0195cbb1;
+			coeff1_8191nu = 0x00caec30;
+			coeff1_8192nu = 0x00cae5d8;
+			coeff1_8193nu = 0x00cadf81;
+			coeff2_2k = 0x0195cbb1;
+			coeff2_4k = 0x00cae5d8;
+			coeff2_8k = 0x006572ec;
+			bfsfcw_fftindex_ratio = 0x0286;
+			fftindex_bfsfcw_ratio = 0x0196;
+			break;
+		case BANDWIDTH_8_MHZ:
+			coeff1_2048nu = 0x039f886f;
+			coeff1_4096nu = 0x01cfc438;
+			coeff1_8191nu = 0x00e7e95b;
+			coeff1_8192nu = 0x00e7e21c;
+			coeff1_8193nu = 0x00e7dadd;
+			coeff2_2k = 0x01cfc438;
+			coeff2_4k = 0x00e7e21c;
+			coeff2_8k = 0x0073f10e;
+			bfsfcw_fftindex_ratio = 0x0235;
+			fftindex_bfsfcw_ratio = 0x01d0;
+			break;
+		default:
+			ret = -EINVAL;
+		}
+		break;
+	case 20250000:
+		switch (bw) {
+#if 0 /* keep */
+		case BANDWIDTH_5_MHZ:
+			coeff1_2048nu = 0x0241eb3b;
+			coeff1_4096nu = 0x0120f59e;
+			coeff1_8191nu = 0x00907f53;
+			coeff1_8192nu = 0x00907acf;
+			coeff1_8193nu = 0x0090764b;
+			coeff2_2k = 0x0120f59e;
+			coeff2_4k = 0x00907acf;
+			coeff2_8k = 0x00483d67;
+			bfsfcw_fftindex_ratio = 0x038b;
+			fftindex_bfsfcw_ratio = 0x0121;
+			break;
+#endif
+		case BANDWIDTH_6_MHZ:
+			coeff1_2048nu = 0x02b580ad;
+			coeff1_4096nu = 0x015ac057;
+			coeff1_8191nu = 0x00ad6597;
+			coeff1_8192nu = 0x00ad602b;
+			coeff1_8193nu = 0x00ad5ac1;
+			coeff2_2k = 0x015ac057;
+			coeff2_4k = 0x00ad602b;
+			coeff2_8k = 0x0056b016;
+			bfsfcw_fftindex_ratio = 0x02f4;
+			fftindex_bfsfcw_ratio = 0x015b;
+			break;
+		case BANDWIDTH_7_MHZ:
+			coeff1_2048nu = 0x03291620;
+			coeff1_4096nu = 0x01948b10;
+			coeff1_8191nu = 0x00ca4bda;
+			coeff1_8192nu = 0x00ca4588;
+			coeff1_8193nu = 0x00ca3f36;
+			coeff2_2k = 0x01948b10;
+			coeff2_4k = 0x00ca4588;
+			coeff2_8k = 0x006522c4;
+			bfsfcw_fftindex_ratio = 0x0288;
+			fftindex_bfsfcw_ratio = 0x0195;
+			break;
+		case BANDWIDTH_8_MHZ:
+			coeff1_2048nu = 0x039cab92;
+			coeff1_4096nu = 0x01ce55c9;
+			coeff1_8191nu = 0x00e7321e;
+			coeff1_8192nu = 0x00e72ae4;
+			coeff1_8193nu = 0x00e723ab;
+			coeff2_2k = 0x01ce55c9;
+			coeff2_4k = 0x00e72ae4;
+			coeff2_8k = 0x00739572;
+			bfsfcw_fftindex_ratio = 0x0237;
+			fftindex_bfsfcw_ratio = 0x01ce;
+			break;
+		default:
+			ret = -EINVAL;
+		}
+		break;
+	case 20583333:
+		switch (bw) {
+#if 0 /* keep */
+		case BANDWIDTH_5_MHZ:
+			coeff1_2048nu = 0x02388f54;
+			coeff1_4096nu = 0x011c47aa;
+			coeff1_8191nu = 0x008e2846;
+			coeff1_8192nu = 0x008e23d5;
+			coeff1_8193nu = 0x008e1f64;
+			coeff2_2k = 0x011c47aa;
+			coeff2_4k = 0x008e23d5;
+			coeff2_8k = 0x004711ea;
+			bfsfcw_fftindex_ratio = 0x039a;
+			fftindex_bfsfcw_ratio = 0x011c;
+			break;
+#endif
+		case BANDWIDTH_6_MHZ:
+			coeff1_2048nu = 0x02aa4598;
+			coeff1_4096nu = 0x015522cc;
+			coeff1_8191nu = 0x00aa96bb;
+			coeff1_8192nu = 0x00aa9166;
+			coeff1_8193nu = 0x00aa8c12;
+			coeff2_2k = 0x015522cc;
+			coeff2_4k = 0x00aa9166;
+			coeff2_8k = 0x005548b3;
+			bfsfcw_fftindex_ratio = 0x0300;
+			fftindex_bfsfcw_ratio = 0x0155;
+			break;
+		case BANDWIDTH_7_MHZ:
+			coeff1_2048nu = 0x031bfbdc;
+			coeff1_4096nu = 0x018dfdee;
+			coeff1_8191nu = 0x00c7052f;
+			coeff1_8192nu = 0x00c6fef7;
+			coeff1_8193nu = 0x00c6f8bf;
+			coeff2_2k = 0x018dfdee;
+			coeff2_4k = 0x00c6fef7;
+			coeff2_8k = 0x00637f7b;
+			bfsfcw_fftindex_ratio = 0x0293;
+			fftindex_bfsfcw_ratio = 0x018e;
+			break;
+		case BANDWIDTH_8_MHZ:
+			coeff1_2048nu = 0x038db21f;
+			coeff1_4096nu = 0x01c6d910;
+			coeff1_8191nu = 0x00e373a3;
+			coeff1_8192nu = 0x00e36c88;
+			coeff1_8193nu = 0x00e3656d;
+			coeff2_2k = 0x01c6d910;
+			coeff2_4k = 0x00e36c88;
+			coeff2_8k = 0x0071b644;
+			bfsfcw_fftindex_ratio = 0x0240;
+			fftindex_bfsfcw_ratio = 0x01c7;
+			break;
+		default:
+			ret = -EINVAL;
+		}
+		break;
+	case 20416667:
+		switch (bw) {
+#if 0 /* keep */
+		case BANDWIDTH_5_MHZ:
+			coeff1_2048nu = 0x023d337f;
+			coeff1_4096nu = 0x011e99c0;
+			coeff1_8191nu = 0x008f515a;
+			coeff1_8192nu = 0x008f4ce0;
+			coeff1_8193nu = 0x008f4865;
+			coeff2_2k = 0x011e99c0;
+			coeff2_4k = 0x008f4ce0;
+			coeff2_8k = 0x0047a670;
+			bfsfcw_fftindex_ratio = 0x0393;
+			fftindex_bfsfcw_ratio = 0x011f;
+			break;
+#endif
+		case BANDWIDTH_6_MHZ:
+			coeff1_2048nu = 0x02afd765;
+			coeff1_4096nu = 0x0157ebb3;
+			coeff1_8191nu = 0x00abfb39;
+			coeff1_8192nu = 0x00abf5d9;
+			coeff1_8193nu = 0x00abf07a;
+			coeff2_2k = 0x0157ebb3;
+			coeff2_4k = 0x00abf5d9;
+			coeff2_8k = 0x0055faed;
+			bfsfcw_fftindex_ratio = 0x02fa;
+			fftindex_bfsfcw_ratio = 0x0158;
+			break;
+		case BANDWIDTH_7_MHZ:
+			coeff1_2048nu = 0x03227b4b;
+			coeff1_4096nu = 0x01913da6;
+			coeff1_8191nu = 0x00c8a518;
+			coeff1_8192nu = 0x00c89ed3;
+			coeff1_8193nu = 0x00c8988e;
+			coeff2_2k = 0x01913da6;
+			coeff2_4k = 0x00c89ed3;
+			coeff2_8k = 0x00644f69;
+			bfsfcw_fftindex_ratio = 0x028d;
+			fftindex_bfsfcw_ratio = 0x0191;
+			break;
+		case BANDWIDTH_8_MHZ:
+			coeff1_2048nu = 0x03951f32;
+			coeff1_4096nu = 0x01ca8f99;
+			coeff1_8191nu = 0x00e54ef7;
+			coeff1_8192nu = 0x00e547cc;
+			coeff1_8193nu = 0x00e540a2;
+			coeff2_2k = 0x01ca8f99;
+			coeff2_4k = 0x00e547cc;
+			coeff2_8k = 0x0072a3e6;
+			bfsfcw_fftindex_ratio = 0x023c;
+			fftindex_bfsfcw_ratio = 0x01cb;
+			break;
+		default:
+			ret = -EINVAL;
+		}
+		break;
+	case 20480000:
+		switch (bw) {
+#if 0 /* keep */
+		case BANDWIDTH_5_MHZ:
+			coeff1_2048nu = 0x023b6db7;
+			coeff1_4096nu = 0x011db6db;
+			coeff1_8191nu = 0x008edfe5;
+			coeff1_8192nu = 0x008edb6e;
+			coeff1_8193nu = 0x008ed6f7;
+			coeff2_2k = 0x011db6db;
+			coeff2_4k = 0x008edb6e;
+			coeff2_8k = 0x00476db7;
+			bfsfcw_fftindex_ratio = 0x0396;
+			fftindex_bfsfcw_ratio = 0x011e;
+			break;
+#endif
+		case BANDWIDTH_6_MHZ:
+			coeff1_2048nu = 0x02adb6db;
+			coeff1_4096nu = 0x0156db6e;
+			coeff1_8191nu = 0x00ab7312;
+			coeff1_8192nu = 0x00ab6db7;
+			coeff1_8193nu = 0x00ab685c;
+			coeff2_2k = 0x0156db6e;
+			coeff2_4k = 0x00ab6db7;
+			coeff2_8k = 0x0055b6db;
+			bfsfcw_fftindex_ratio = 0x02fd;
+			fftindex_bfsfcw_ratio = 0x0157;
+			break;
+		case BANDWIDTH_7_MHZ:
+			coeff1_2048nu = 0x03200000;
+			coeff1_4096nu = 0x01900000;
+			coeff1_8191nu = 0x00c80640;
+			coeff1_8192nu = 0x00c80000;
+			coeff1_8193nu = 0x00c7f9c0;
+			coeff2_2k = 0x01900000;
+			coeff2_4k = 0x00c80000;
+			coeff2_8k = 0x00640000;
+			bfsfcw_fftindex_ratio = 0x028f;
+			fftindex_bfsfcw_ratio = 0x0190;
+			break;
+		case BANDWIDTH_8_MHZ:
+			coeff1_2048nu = 0x03924925;
+			coeff1_4096nu = 0x01c92492;
+			coeff1_8191nu = 0x00e4996e;
+			coeff1_8192nu = 0x00e49249;
+			coeff1_8193nu = 0x00e48b25;
+			coeff2_2k = 0x01c92492;
+			coeff2_4k = 0x00e49249;
+			coeff2_8k = 0x00724925;
+			bfsfcw_fftindex_ratio = 0x023d;
+			fftindex_bfsfcw_ratio = 0x01c9;
+			break;
+		default:
+			ret = -EINVAL;
+		}
+		break;
+	case 20500000:
+		switch (bw) {
+#if 0 /* keep */
+		case BANDWIDTH_5_MHZ:
+			coeff1_2048nu = 0x023adeff;
+			coeff1_4096nu = 0x011d6f80;
+			coeff1_8191nu = 0x008ebc36;
+			coeff1_8192nu = 0x008eb7c0;
+			coeff1_8193nu = 0x008eb34a;
+			coeff2_2k = 0x011d6f80;
+			coeff2_4k = 0x008eb7c0;
+			coeff2_8k = 0x00475be0;
+			bfsfcw_fftindex_ratio = 0x0396;
+			fftindex_bfsfcw_ratio = 0x011d;
+			break;
+#endif
+		case BANDWIDTH_6_MHZ:
+			coeff1_2048nu = 0x02ad0b99;
+			coeff1_4096nu = 0x015685cc;
+			coeff1_8191nu = 0x00ab4840;
+			coeff1_8192nu = 0x00ab42e6;
+			coeff1_8193nu = 0x00ab3d8c;
+			coeff2_2k = 0x015685cc;
+			coeff2_4k = 0x00ab42e6;
+			coeff2_8k = 0x0055a173;
+			bfsfcw_fftindex_ratio = 0x02fd;
+			fftindex_bfsfcw_ratio = 0x0157;
+			break;
+		case BANDWIDTH_7_MHZ:
+			coeff1_2048nu = 0x031f3832;
+			coeff1_4096nu = 0x018f9c19;
+			coeff1_8191nu = 0x00c7d44b;
+			coeff1_8192nu = 0x00c7ce0c;
+			coeff1_8193nu = 0x00c7c7ce;
+			coeff2_2k = 0x018f9c19;
+			coeff2_4k = 0x00c7ce0c;
+			coeff2_8k = 0x0063e706;
+			bfsfcw_fftindex_ratio = 0x0290;
+			fftindex_bfsfcw_ratio = 0x0190;
+			break;
+		case BANDWIDTH_8_MHZ:
+			coeff1_2048nu = 0x039164cb;
+			coeff1_4096nu = 0x01c8b266;
+			coeff1_8191nu = 0x00e46056;
+			coeff1_8192nu = 0x00e45933;
+			coeff1_8193nu = 0x00e45210;
+			coeff2_2k = 0x01c8b266;
+			coeff2_4k = 0x00e45933;
+			coeff2_8k = 0x00722c99;
+			bfsfcw_fftindex_ratio = 0x023e;
+			fftindex_bfsfcw_ratio = 0x01c9;
+			break;
+		default:
+			ret = -EINVAL;
+		}
+		break;
+	case 20625000:
+		switch (bw) {
+#if 0 /* keep */
+		case BANDWIDTH_5_MHZ:
+			coeff1_2048nu = 0x02376948;
+			coeff1_4096nu = 0x011bb4a4;
+			coeff1_8191nu = 0x008ddec1;
+			coeff1_8192nu = 0x008dda52;
+			coeff1_8193nu = 0x008dd5e3;
+			coeff2_2k = 0x011bb4a4;
+			coeff2_4k = 0x008dda52;
+			coeff2_8k = 0x0046ed29;
+			bfsfcw_fftindex_ratio = 0x039c;
+			fftindex_bfsfcw_ratio = 0x011c;
+			break;
+#endif
+		case BANDWIDTH_6_MHZ:
+			coeff1_2048nu = 0x02a8e4bd;
+			coeff1_4096nu = 0x0154725e;
+			coeff1_8191nu = 0x00aa3e81;
+			coeff1_8192nu = 0x00aa392f;
+			coeff1_8193nu = 0x00aa33de;
+			coeff2_2k = 0x0154725e;
+			coeff2_4k = 0x00aa392f;
+			coeff2_8k = 0x00551c98;
+			bfsfcw_fftindex_ratio = 0x0302;
+			fftindex_bfsfcw_ratio = 0x0154;
+			break;
+		case BANDWIDTH_7_MHZ:
+			coeff1_2048nu = 0x031a6032;
+			coeff1_4096nu = 0x018d3019;
+			coeff1_8191nu = 0x00c69e41;
+			coeff1_8192nu = 0x00c6980c;
+			coeff1_8193nu = 0x00c691d8;
+			coeff2_2k = 0x018d3019;
+			coeff2_4k = 0x00c6980c;
+			coeff2_8k = 0x00634c06;
+			bfsfcw_fftindex_ratio = 0x0294;
+			fftindex_bfsfcw_ratio = 0x018d;
+			break;
+		case BANDWIDTH_8_MHZ:
+			coeff1_2048nu = 0x038bdba6;
+			coeff1_4096nu = 0x01c5edd3;
+			coeff1_8191nu = 0x00e2fe02;
+			coeff1_8192nu = 0x00e2f6ea;
+			coeff1_8193nu = 0x00e2efd2;
+			coeff2_2k = 0x01c5edd3;
+			coeff2_4k = 0x00e2f6ea;
+			coeff2_8k = 0x00717b75;
+			bfsfcw_fftindex_ratio = 0x0242;
+			fftindex_bfsfcw_ratio = 0x01c6;
+			break;
+		default:
+			ret = -EINVAL;
+		}
+		break;
+	default:
+		err("invalid xtal freq");
+		return -EINVAL;
+	}
+	if (ret) {
+		err("invalid bandwidth");
+		return ret;
+	}
+
+#ifdef V4L2_ONLY_DVB_V5
+#undef BANDWIDTH_5_MHZ
+#undef BANDWIDTH_6_MHZ
+#undef BANDWIDTH_7_MHZ
+#undef BANDWIDTH_8_MHZ
+#endif
+
+	/* adc multiplier */
+	ret = af9033_read_reg(state, OFDM, api_adcx2, &tmp);
+	if (ret)
+		return ret;
+
+	if (tmp == 1) {
+		coeff1_2048nu /= 2;
+		coeff1_4096nu /= 2;
+		coeff1_8191nu /= 2;
+		coeff1_8192nu /= 2;
+		coeff1_8193nu /= 2 ;
+		coeff2_2k /= 2;
+		coeff2_4k /= 2;
+		coeff2_8k /= 2;
+	}
+
+	buf[i++] = (u8) ((coeff1_2048nu         & 0x03000000) >> 24);
+	buf[i++] = (u8) ((coeff1_2048nu         & 0x00ff0000) >> 16);
+	buf[i++] = (u8) ((coeff1_2048nu         & 0x0000ff00) >> 8);
+	buf[i++] = (u8) ((coeff1_2048nu         & 0x000000ff));
+	buf[i++] = (u8) ((coeff1_4096nu         & 0x03000000) >> 24);
+	buf[i++] = (u8) ((coeff1_4096nu         & 0x00ff0000) >> 16);
+	buf[i++] = (u8) ((coeff1_4096nu         & 0x0000ff00) >> 8);
+	buf[i++] = (u8) ((coeff1_4096nu         & 0x000000ff));
+	buf[i++] = (u8) ((coeff1_8191nu         & 0x03000000) >> 24);
+	buf[i++] = (u8) ((coeff1_8191nu         & 0x00ff0000) >> 16);
+	buf[i++] = (u8) ((coeff1_8191nu         & 0x0000ff00) >> 8);
+	buf[i++] = (u8) ((coeff1_8191nu         & 0x000000ff));
+	buf[i++] = (u8) ((coeff1_8192nu         & 0x03000000) >> 24);
+	buf[i++] = (u8) ((coeff1_8192nu         & 0x00ff0000) >> 16);
+	buf[i++] = (u8) ((coeff1_8192nu         & 0x0000ff00) >> 8);
+	buf[i++] = (u8) ((coeff1_8192nu         & 0x000000ff));
+	buf[i++] = (u8) ((coeff1_8193nu         & 0x03000000) >> 24);
+	buf[i++] = (u8) ((coeff1_8193nu         & 0x00ff0000) >> 16);
+	buf[i++] = (u8) ((coeff1_8193nu         & 0x0000ff00) >> 8);
+	buf[i++] = (u8) ((coeff1_8193nu         & 0x000000ff));
+	buf[i++] = (u8) ((coeff2_8k             & 0x01000000) >> 24);
+	buf[i++] = (u8) ((coeff2_8k             & 0x00ff0000) >> 16);
+	buf[i++] = (u8) ((coeff2_8k             & 0x0000ff00) >> 8);
+	buf[i++] = (u8) ((coeff2_8k             & 0x000000ff));
+	buf[i++] = (u8) ((coeff2_2k             & 0x01000000) >> 24);
+	buf[i++] = (u8) ((coeff2_2k             & 0x00ff0000) >> 16);
+	buf[i++] = (u8) ((coeff2_2k             & 0x0000ff00) >> 8);
+	buf[i++] = (u8) ((coeff2_2k             & 0x000000ff));
+	buf[i++] = (u8) ((coeff2_4k             & 0x01000000) >> 24);
+	buf[i++] = (u8) ((coeff2_4k             & 0x00ff0000) >> 16);
+	buf[i++] = (u8) ((coeff2_4k             & 0x0000ff00) >> 8);
+	buf[i++] = (u8) ((coeff2_4k             & 0x000000ff));
+	buf[i++] = (u8) ((bfsfcw_fftindex_ratio &     0x00ff));
+	buf[i++] = (u8) ((bfsfcw_fftindex_ratio &     0xff00) >> 8);
+	buf[i++] = (u8) ((fftindex_bfsfcw_ratio &     0x00ff));
+	buf[i++] = (u8) ((fftindex_bfsfcw_ratio &     0xff00) >> 8);
+
+	deb_info("%s: coeff:", __func__);
+	debug_dump(buf, sizeof(buf), deb_info);
+
+	/* program */
+	return af9033_write_regs(state, OFDM, api_cfoe_NS_2048_coeff1_25_24,
+		buf, sizeof(buf));
+}
+
+static int af9033_set_crystal_ctrl(struct af9033_state *state)
+{
+	u8 buf[4];
+	u32 crystal_cw;
+	deb_info("%s: crystal_clock:%d\n", __func__,
+		state->config.crystal_clock);
+
+	crystal_cw = af913_div(state->config.crystal_clock, 1000000ul, 19ul);
+
+	buf[0] = (u8) ((crystal_cw & 0x000000ff));
+	buf[1] = (u8) ((crystal_cw & 0x0000ff00) >> 8);
+	buf[2] = (u8) ((crystal_cw & 0x00ff0000) >> 16);
+	buf[3] = (u8) ((crystal_cw & 0xff000000) >> 24);
+
+	deb_info("%s: crystal_cw:", __func__);
+	debug_dump(buf, sizeof(buf), deb_info);
+
+	/* program */
+	return af9033_write_regs(state, OFDM, api_crystal_clk_7_0, buf,
+		sizeof(buf));
+}
+
+static int af9033_set_adc_ctrl(struct af9033_state *state)
+{
+	u8 buf[3];
+	u32 adc_cw;
+	deb_info("%s: adc_clock:%d\n", __func__, state->config.adc_clock);
+
+	adc_cw = af913_div(state->config.adc_clock, 1000000ul, 19ul);
+
+	buf[0] = (u8) ((adc_cw & 0x000000ff));
+	buf[1] = (u8) ((adc_cw & 0x0000ff00) >> 8);
+	buf[2] = (u8) ((adc_cw & 0x00ff0000) >> 16);
+
+	deb_info("%s: adc_cw:", __func__);
+	debug_dump(buf, sizeof(buf), deb_info);
+
+	/* program */
+	return af9033_write_regs(state, OFDM, p_reg_f_adc_7_0, buf,
+		sizeof(buf));
+}
+
+static int af9033_set_freq_ctrl(struct af9033_state *state)
+{
+	int ret;
+	u8 buf[3], tmp;
+	u32 adc_freq, freq_cw;
+	s8 bfs_spec_inv;
+	int if_sample_freq;
+
+	bfs_spec_inv = state->config.rf_spec_inv ? -1 : 1;
+
+	adc_freq       = state->config.adc_clock;
+	if_sample_freq = state->config.if_freq;
+
+	while (if_sample_freq > (adc_freq / 2))
+		if_sample_freq = if_sample_freq - adc_freq;
+
+	if (if_sample_freq >= 0)
+		bfs_spec_inv = bfs_spec_inv * (-1);
+	else
+		if_sample_freq = if_sample_freq * (-1);
+
+	freq_cw = af913_div(if_sample_freq, adc_freq, 23ul);
+
+	if (bfs_spec_inv == -1)
+		freq_cw *= -1;
+
+	/* adc multiplier */
+	ret = af9033_read_reg(state, OFDM, api_adcx2, &tmp);
+	if (ret)
+		return ret;
+
+	if (tmp == 1)
+		freq_cw /= 2;
+
+	buf[0] = (u8) ((freq_cw & 0x000000ff));
+	buf[1] = (u8) ((freq_cw & 0x0000ff00) >> 8);
+	buf[2] = (u8) ((freq_cw & 0x007f0000) >> 16);
+
+	deb_info("%s: freq_cw:", __func__);
+	debug_dump(buf, sizeof(buf), deb_info);
+
+	/* program */
+	return af9033_write_regs(state, OFDM, api_bfs_fcw_7_0, buf,
+		sizeof(buf));
+}
+static void af9033_release(struct dvb_frontend *fe)
+{
+	struct af9033_state *state = fe->demodulator_priv;
+	kfree(state);
+}
+
+static int af9033_init(struct dvb_frontend *fe)
+{
+	struct af9033_state *state = fe->demodulator_priv;
+	int ret, i, len;
+	u8 tmp0, tmp1;
+	struct regdesc *init;
+	deb_info("%s\n", __func__);
+
+	/* power on */
+	ret = af9033_write_reg_bits(state, OFDM, p_reg_afe_mem0, 3, 1, 0);
+	if (ret)
+		goto error;
+
+	ret = af9033_write_reg(state, OFDM, api_suspend_flag, 0);
+	if (ret)
+		goto error;
+
+	/* tell to the firmware type of the tuner */
+	ret = af9033_write_reg(state, LINK, p_reg_link_ofsm_dummy_15_8,
+		state->config.tuner);
+	if (ret)
+		goto error;
+
+	/* set read-update bit for constellation */
+	ret = af9033_write_reg_bits(state, OFDM, p_reg_feq_read_update,
+		reg_feq_read_update_pos, reg_feq_read_update_len, 1);
+	if (ret)
+		goto error;
+
+	/* enable FEC monitor */
+	ret = af9033_write_reg_bits(state, OFDM, p_fec_vtb_rsd_mon_en,
+		fec_vtb_rsd_mon_en_pos, fec_vtb_rsd_mon_en_len, 1);
+	if (ret)
+		goto error;
+
+	/* program crystal control */
+	ret = af9033_set_crystal_ctrl(state);
+	if (ret)
+		goto error;
+
+	/* program ADC control */
+	ret = af9033_set_adc_ctrl(state);
+	if (ret)
+		goto error;
+
+	/* enable DVB-T interrupt */
+	ret = af9033_write_reg_bits(state, LINK, p_reg_dvbt_inten,
+		reg_dvbt_inten_pos, reg_dvbt_inten_len, 1);
+	if (ret)
+		goto error;
+
+	/* enable DVB-T mode */
+	ret = af9033_write_reg_bits(state, LINK, p_reg_dvbt_en,
+		reg_dvbt_en_pos, reg_dvbt_en_len, 1);
+	if (ret)
+		goto error;
+
+	/* set dca_upper_chip */
+	ret = af9033_write_reg_bits(state, OFDM, p_reg_dca_upper_chip,
+		reg_dca_upper_chip_pos, reg_dca_upper_chip_len, 0);
+	if (ret)
+		goto error;
+
+	ret = af9033_write_reg_bits(state, LINK, p_reg_top_hostb_dca_upper,
+		reg_top_hostb_dca_upper_pos, reg_top_hostb_dca_upper_len, 0);
+	if (ret)
+		goto error;
+
+	ret = af9033_write_reg_bits(state, LINK, p_reg_top_hosta_dca_upper,
+		reg_top_hosta_dca_upper_pos, reg_top_hosta_dca_upper_len, 0);
+	if (ret)
+		goto error;
+
+	/* set dca_lower_chip */
+	ret = af9033_write_reg_bits(state, OFDM, p_reg_dca_lower_chip,
+		reg_dca_lower_chip_pos, reg_dca_lower_chip_len, 0);
+	if (ret)
+		goto error;
+
+	ret = af9033_write_reg_bits(state, LINK, p_reg_top_hostb_dca_lower,
+		reg_top_hostb_dca_lower_pos, reg_top_hostb_dca_lower_len, 0);
+	if (ret)
+		goto error;
+
+	ret = af9033_write_reg_bits(state, LINK, p_reg_top_hosta_dca_lower,
+		reg_top_hosta_dca_lower_pos, reg_top_hosta_dca_lower_len, 0);
+	if (ret)
+		goto error;
+
+	/* set phase latch */
+	ret = af9033_write_reg_bits(state, OFDM, p_reg_dca_platch,
+		reg_dca_platch_pos, reg_dca_platch_len, 0);
+	if (ret)
+		goto error;
+
+	/* set fpga latch */
+	ret = af9033_write_reg(state, OFDM, p_reg_dca_fpga_latch, 0);
+	if (ret)
+		goto error;
+
+	/* set stand alone */
+	ret = af9033_write_reg_bits(state, OFDM, p_reg_dca_stand_alone,
+		reg_dca_stand_alone_pos, reg_dca_stand_alone_len, 1);
+	if (ret)
+		goto error;
+
+	/* set DCA enable */
+	ret = af9033_write_reg_bits(state, OFDM, p_reg_dca_en, reg_dca_en_pos,
+		reg_dca_en_len, 0);
+	if (ret)
+		goto error;
+
+	/* load OFSM settings */
+	deb_info("%s: load ofsm settings\n", __func__);
+	len = ARRAY_SIZE(ofsm_init);
+	init = ofsm_init;
+	for (i = 0; i < len; i++) {
+		ret = af9033_write_reg(state, OFDM, init[i].addr, init[i].val);
+		if (ret)
+			goto error;
+	}
+
+	/* load tuner specific settings */
+	deb_info("%s: load tuner specific settings\n", __func__);
+	switch (state->config.tuner) {
+	case AF9033_TUNER_TUA9001:
+		len = ARRAY_SIZE(tuner_init_tua9001);
+		init = tuner_init_tua9001;
+		break;
+	case AF9033_TUNER_MXL5007t:
+		len = ARRAY_SIZE(tuner_init_mxl5007t);
+		init = tuner_init_mxl5007t;
+		break;
+        case AF9033_TUNER_TDA18218:
+                len = ARRAY_SIZE(tuner_init_tda18218);
+                init = tuner_init_tda18218;
+                break;
+	default:
+		len = 0;
+		init = NULL;
+		break;
+	}
+	for (i = 0; i < len; i++) {
+		ret = af9033_write_reg(state, OFDM, init[i].addr, init[i].val);
+		if (ret)
+			goto error;
+	}
+
+	/* set H/W MPEG2 locked detection **/
+	ret = af9033_write_reg(state, LINK, p_reg_top_lock3_out, 1);
+	if (ret)
+		goto error;
+
+	/* set registers for driving power */
+	ret = af9033_write_reg(state, LINK, p_reg_top_padmiscdr2, 1);
+	if (ret)
+		goto error;
+
+	/* et registers for driving power */
+	ret = af9033_write_reg(state, LINK, p_reg_top_padmiscdr4, 0);
+	if (ret)
+		goto error;
+
+	/* set registers for driving power */
+	ret = af9033_write_reg(state, LINK, p_reg_top_padmiscdr8, 0);
+	if (ret)
+		goto error;
+
+	/* set TS mode */
+	deb_info("%s: setting ts mode\n", __func__);
+	tmp0 = 0; /* parallel mode */
+	tmp1 = 0; /* serial mode */
+	switch (state->config.output_mode) {
+	case AF9033_TS_MODE_PARALLEL:
+		tmp0 = 1;
+		break;
+	case AF9033_TS_MODE_SERIAL:
+		tmp1 = 1;
+		break;
+	case AF9033_TS_MODE_USB:
+		/* usb mode for AF9035 */
+	default:
+		break;
+	}
+	ret = af9033_write_reg_bits(state, OFDM, p_mp2if_mpeg_par_mode,
+		mp2if_mpeg_par_mode_pos, mp2if_mpeg_par_mode_len, tmp0);
+	if (ret)
+		goto error;
+	ret = af9033_write_reg_bits(state, OFDM, p_mp2if_mpeg_ser_mode,
+		mp2if_mpeg_ser_mode_pos, mp2if_mpeg_ser_mode_len, tmp1);
+	if (ret)
+		goto error;
+
+	if (state->config.output_mode == AF9033_TS_MODE_SERIAL) {
+		ret = af9033_write_reg_bits(state, LINK, p_reg_top_hostb_mpeg_ser_mode,
+			reg_top_hostb_mpeg_ser_mode_pos, reg_top_hostb_mpeg_ser_mode_len, 1);
+		if (ret)
+			goto error;
+	}
+error:
+	if (ret)
+		deb_info("%s: failed:%d\n", __func__, ret);
+
+	return ret;
+}
+
+static int af9033_sleep(struct dvb_frontend *fe)
+{
+	struct af9033_state *state = fe->demodulator_priv;
+	int ret;
+	u8 tmp, i;
+	deb_info("%s\n", __func__);
+
+	ret = af9033_write_reg(state, OFDM, api_suspend_flag, 1);
+	if (ret)
+		goto error;
+
+	ret = af9033_write_reg(state, OFDM, api_trigger_ofsm, 0);
+	if (ret)
+		goto error;
+
+	for (i = 0; i < 150; i++) {
+		ret = af9033_read_reg(state, OFDM, api_suspend_flag, &tmp);
+		if (ret)
+			goto error;
+		if (!tmp)
+			break;
+		msleep(10);
+	}
+	if (tmp) {
+		deb_info("%s: power off time outs\n", __func__);
+		return -ETIMEDOUT;
+	}
+
+	ret = af9033_write_reg_bits(state, OFDM, p_reg_afe_mem0, 3, 1, 1);
+	if (ret)
+		goto error;
+
+	/* fixed current leakage (?) */
+	if (state->config.output_mode != AF9033_TS_MODE_USB) {
+		/* enable parallel TS */
+		ret = af9033_write_reg_bits(state, LINK,
+			p_reg_top_hosta_mpeg_ser_mode,
+			reg_top_hosta_mpeg_ser_mode_pos,
+			reg_top_hosta_mpeg_ser_mode_len, 0);
+		if (ret)
+			goto error;
+
+		ret = af9033_write_reg_bits(state, LINK,
+			p_reg_top_hosta_mpeg_par_mode,
+			reg_top_hosta_mpeg_par_mode_pos,
+			reg_top_hosta_mpeg_par_mode_len, 1);
+	}
+
+error:
+	if (ret)
+		deb_info("%s: failed:%d\n", __func__, ret);
+
+	return ret;
+}
+
+#ifdef V4L2_ONLY_DVB_V5
+static int af9033_set_frontend(struct dvb_frontend *fe)
+{
+	struct dtv_frontend_properties *params = &fe->dtv_property_cache;
+	struct af9033_state *state = fe->demodulator_priv;
+	int ret;
+	u8 tmp;
+	deb_info("%s: freq:%d bw:%d\n", __func__, params->frequency,
+		params->bandwidth_hz);
+
+	state->frequency = params->frequency;
+
+	/* program tuner */
+	if (fe->ops.tuner_ops.set_params)
+		fe->ops.tuner_ops.set_params(fe);
+
+	/* program CFOE coefficients */
+	ret = af9033_set_coeff(state, params->bandwidth_hz);
+	if (ret)
+		goto error;
+
+	/* program frequency control */
+	ret = af9033_set_freq_ctrl(state);
+	if (ret)
+		goto error;
+
+	/* program bandwidth */
+	switch (params->bandwidth_hz) {
+	case 6000000:
+		tmp = 0;
+		break;
+	case 7000000:
+		tmp = 1;
+		break;
+	case 8000000:
+		tmp = 2;
+		break;
+#if 0 /* keep */
+	case 5000000:
+		tmp = 3;
+		break;
+#endif
+	default:
+		deb_info("%s: invalid bandwidth\n", __func__);
+		return -EINVAL;
+	}
+	ret = af9033_write_reg_bits(state, OFDM, g_reg_bw, reg_bw_pos,
+		reg_bw_len, tmp);
+	if (ret)
+		goto error;
+
+	/* clear easy mode flag */
+	ret = af9033_write_reg(state, OFDM, api_Training_Mode, 0x00);
+	if (ret)
+		goto error;
+
+	/* clear empty channel flag */
+	ret = af9033_write_reg(state, OFDM, api_empty_channel_status, 0x00);
+	if (ret)
+		goto error;
+
+	/* clear MPEG2 lock flag */
+	ret = af9033_write_reg_bits(state, OFDM, r_mp2if_sync_byte_locked,
+		mp2if_sync_byte_locked_pos, mp2if_sync_byte_locked_len, 0x00);
+	if (ret)
+		goto error;
+
+	/* set frequency band
+	    174 -  230 MHz VHF     band = 0x00
+	    350 -  900 MHz UHF     band = 0x01
+	   1670 - 1680 MHz L-BAND  band = 0x02
+	   otherwise               band = 0xff */
+	/* TODO: are both min/max ranges really required... */
+	if ((state->frequency >= 174000000) && (state->frequency <= 230000000))
+		tmp = 0x00; /* VHF */
+	else if ((state->frequency >= 350000000) && (state->frequency <= 900000000))
+		tmp = 0x01; /* UHF */
+	else if ((state->frequency >= 1670000000) && (state->frequency <= 1680000000))
+		tmp = 0x02; /* L-BAND */
+	else
+		tmp = 0xff;
+
+	ret = af9033_write_reg(state, OFDM, api_FreBand, tmp);
+	if (ret)
+		goto error;
+
+	/* trigger ofsm */
+	ret = af9033_write_reg(state, OFDM, api_trigger_ofsm, 0);
+	if (ret)
+		goto error;
+error:
+	if (ret)
+		deb_info("%s: failed:%d\n", __func__, ret);
+
+	return ret;
+}
+#else
+static int af9033_set_frontend(struct dvb_frontend *fe,
+	struct dvb_frontend_parameters *params)
+{
+	struct af9033_state *state = fe->demodulator_priv;
+	int ret;
+	u8 tmp;
+	deb_info("%s: freq:%d bw:%d\n", __func__, params->frequency,
+		params->u.ofdm.bandwidth);
+
+	state->frequency = params->frequency;
+
+	/* program tuner */
+	if (fe->ops.tuner_ops.set_params)
+		fe->ops.tuner_ops.set_params(fe, params);
+
+	/* program CFOE coefficients */
+	ret = af9033_set_coeff(state, params->u.ofdm.bandwidth);
+	if (ret)
+		goto error;
+
+	/* program frequency control */
+	ret = af9033_set_freq_ctrl(state);
+	if (ret)
+		goto error;
+
+	/* program bandwidth */
+	switch (params->u.ofdm.bandwidth) {
+	case BANDWIDTH_6_MHZ:
+		tmp = 0;
+		break;
+	case BANDWIDTH_7_MHZ:
+		tmp = 1;
+		break;
+	case BANDWIDTH_8_MHZ:
+		tmp = 2;
+		break;
+#if 0 /* keep */
+	case BANDWIDTH_5_MHZ:
+		tmp = 3;
+		break;
+#endif
+	default:
+		deb_info("%s: invalid bandwidth\n", __func__);
+		return -EINVAL;
+	}
+	ret = af9033_write_reg_bits(state, OFDM, g_reg_bw, reg_bw_pos,
+		reg_bw_len, tmp);
+	if (ret)
+		goto error;
+
+	/* clear easy mode flag */
+	ret = af9033_write_reg(state, OFDM, api_Training_Mode, 0x00);
+	if (ret)
+		goto error;
+
+	/* clear empty channel flag */
+	ret = af9033_write_reg(state, OFDM, api_empty_channel_status, 0x00);
+	if (ret)
+		goto error;
+
+	/* clear MPEG2 lock flag */
+	ret = af9033_write_reg_bits(state, OFDM, r_mp2if_sync_byte_locked,
+		mp2if_sync_byte_locked_pos, mp2if_sync_byte_locked_len, 0x00);
+	if (ret)
+		goto error;
+
+	/* set frequency band
+	    174 -  230 MHz VHF     band = 0x00
+	    350 -  900 MHz UHF     band = 0x01
+	   1670 - 1680 MHz L-BAND  band = 0x02
+	   otherwise               band = 0xff */
+	/* TODO: are both min/max ranges really required... */
+	if ((state->frequency >= 174000000) && (state->frequency <= 230000000))
+		tmp = 0x00; /* VHF */
+	else if ((state->frequency >= 350000000) && (state->frequency <= 900000000))
+		tmp = 0x01; /* UHF */
+	else if ((state->frequency >= 1670000000) && (state->frequency <= 1680000000))
+		tmp = 0x02; /* L-BAND */
+	else
+		tmp = 0xff;
+
+	ret = af9033_write_reg(state, OFDM, api_FreBand, tmp);
+	if (ret)
+		goto error;
+
+	/* trigger ofsm */
+	ret = af9033_write_reg(state, OFDM, api_trigger_ofsm, 0);
+	if (ret)
+		goto error;
+error:
+	if (ret)
+		deb_info("%s: failed:%d\n", __func__, ret);
+
+	return ret;
+}
+#endif
+
+static int af9033_get_tune_settings(struct dvb_frontend *fe,
+	struct dvb_frontend_tune_settings *fesettings)
+{
+	fesettings->min_delay_ms = 800;
+	fesettings->step_size = 0;
+	fesettings->max_drift = 0;
+
+	return 0;
+}
+
+#ifdef V4L2_ONLY_DVB_V5
+static int af9033_get_frontend(struct dvb_frontend *fe)
+{
+	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
+	struct af9033_state *state = fe->demodulator_priv;
+	int ret;
+	u8 buf[8];
+	deb_info("%s\n", __func__);
+#define TRANSMISSION_MODE  (g_reg_tpsd_txmod - g_reg_tpsd_txmod)
+#define GUARD_INTERVAL     (g_reg_tpsd_gi    - g_reg_tpsd_txmod)
+#define HIERARCHY          (g_reg_tpsd_hier  - g_reg_tpsd_txmod)
+#define CONSTELLATION      (g_reg_tpsd_const - g_reg_tpsd_txmod)
+#define BANDWIDTH          (g_reg_bw         - g_reg_tpsd_txmod)
+#define PRIORITY           (g_reg_dec_pri    - g_reg_tpsd_txmod)
+#define CODE_RATE_HP       (g_reg_tpsd_hpcr  - g_reg_tpsd_txmod)
+#define CODE_RATE_LP       (g_reg_tpsd_lpcr  - g_reg_tpsd_txmod)
+
+	/* read all needed registers */
+	ret = af9033_read_regs(state, OFDM, g_reg_tpsd_txmod, buf, sizeof(buf));
+	if (ret)
+		goto error;
+
+	deb_info("%s: ", __func__);
+	debug_dump(buf, sizeof(buf), deb_info);
+
+	switch ((buf[CONSTELLATION] >> 0) & 3) {
+	case 0:
+		p->modulation = QPSK;
+		break;
+	case 1:
+		p->modulation = QAM_16;
+		break;
+	case 2:
+		p->modulation = QAM_64;
+		break;
+	}
+
+	switch ((buf[TRANSMISSION_MODE] >> 0) & 3) {
+	case 0:
+		p->transmission_mode = TRANSMISSION_MODE_2K;
+		break;
+	case 1:
+		p->transmission_mode = TRANSMISSION_MODE_8K;
+		break;
+#if 0 /* keep */
+	case 2:
+		p->transmission_mode = TRANSMISSION_MODE_4K;
+		break;
+#endif
+	}
+
+	switch ((buf[GUARD_INTERVAL] >> 0) & 3) {
+	case 0:
+		p->guard_interval = GUARD_INTERVAL_1_32;
+		break;
+	case 1:
+		p->guard_interval = GUARD_INTERVAL_1_16;
+		break;
+	case 2:
+		p->guard_interval = GUARD_INTERVAL_1_8;
+		break;
+	case 3:
+		p->guard_interval = GUARD_INTERVAL_1_4;
+		break;
+	}
+
+	switch ((buf[HIERARCHY] >> 0) & 7) {
+	case 0:
+		p->hierarchy = HIERARCHY_NONE;
+		break;
+	case 1:
+		p->hierarchy = HIERARCHY_1;
+		break;
+	case 2:
+		p->hierarchy = HIERARCHY_2;
+		break;
+	case 3:
+		p->hierarchy = HIERARCHY_4;
+		break;
+	}
+
+	switch ((buf[CODE_RATE_HP] >> 0) & 7) {
+	case 0:
+		p->code_rate_HP = FEC_1_2;
+		break;
+	case 1:
+		p->code_rate_HP = FEC_2_3;
+		break;
+	case 2:
+		p->code_rate_HP = FEC_3_4;
+		break;
+	case 3:
+		p->code_rate_HP = FEC_5_6;
+		break;
+	case 4:
+		p->code_rate_HP = FEC_7_8;
+		break;
+	case 5:
+		p->code_rate_HP = FEC_NONE;
+		break;
+	}
+
+	switch ((buf[CODE_RATE_LP] >> 0) & 7) {
+	case 0:
+		p->code_rate_LP = FEC_1_2;
+		break;
+	case 1:
+		p->code_rate_LP = FEC_2_3;
+		break;
+	case 2:
+		p->code_rate_LP = FEC_3_4;
+		break;
+	case 3:
+		p->code_rate_LP = FEC_5_6;
+		break;
+	case 4:
+		p->code_rate_LP = FEC_7_8;
+		break;
+	case 5:
+		p->code_rate_LP = FEC_NONE;
+		break;
+	}
+
+	switch ((buf[BANDWIDTH] >> 0) & 3) {
+	case 0:
+		p->bandwidth_hz = 6000000;
+		break;
+	case 1:
+		p->bandwidth_hz = 7000000;
+		break;
+	case 2:
+		p->bandwidth_hz = 8000000;
+		break;
+#if 0 /* keep */
+	case 3:
+		p->bandwidth_hz = 5000000;
+		break;
+#endif
+	}
+
+	p->inversion = INVERSION_AUTO;
+	p->frequency = state->frequency;
+
+error:
+	if (ret)
+		deb_info("%s: failed:%d\n", __func__, ret);
+
+	return ret;
+}
+#else
+static int af9033_get_frontend(struct dvb_frontend *fe,
+	struct dvb_frontend_parameters *p)
+{
+	struct af9033_state *state = fe->demodulator_priv;
+	int ret;
+	u8 buf[8];
+	deb_info("%s\n", __func__);
+#define TRANSMISSION_MODE  (g_reg_tpsd_txmod - g_reg_tpsd_txmod)
+#define GUARD_INTERVAL     (g_reg_tpsd_gi    - g_reg_tpsd_txmod)
+#define HIERARCHY          (g_reg_tpsd_hier  - g_reg_tpsd_txmod)
+#define CONSTELLATION      (g_reg_tpsd_const - g_reg_tpsd_txmod)
+#define BANDWIDTH          (g_reg_bw         - g_reg_tpsd_txmod)
+#define PRIORITY           (g_reg_dec_pri    - g_reg_tpsd_txmod)
+#define CODE_RATE_HP       (g_reg_tpsd_hpcr  - g_reg_tpsd_txmod)
+#define CODE_RATE_LP       (g_reg_tpsd_lpcr  - g_reg_tpsd_txmod)
+
+	/* read all needed registers */
+	ret = af9033_read_regs(state, OFDM, g_reg_tpsd_txmod, buf, sizeof(buf));
+	if (ret)
+		goto error;
+
+	deb_info("%s: ", __func__);
+	debug_dump(buf, sizeof(buf), deb_info);
+
+	switch ((buf[CONSTELLATION] >> 0) & 3) {
+	case 0:
+		p->u.ofdm.constellation = QPSK;
+		break;
+	case 1:
+		p->u.ofdm.constellation = QAM_16;
+		break;
+	case 2:
+		p->u.ofdm.constellation = QAM_64;
+		break;
+	}
+
+	switch ((buf[TRANSMISSION_MODE] >> 0) & 3) {
+	case 0:
+		p->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
+		break;
+	case 1:
+		p->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
+		break;
+#if 0 /* keep */
+	case 2:
+		p->u.ofdm.transmission_mode = TRANSMISSION_MODE_4K;
+		break;
+#endif
+	}
+
+	switch ((buf[GUARD_INTERVAL] >> 0) & 3) {
+	case 0:
+		p->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
+		break;
+	case 1:
+		p->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
+		break;
+	case 2:
+		p->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
+		break;
+	case 3:
+		p->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
+		break;
+	}
+
+	switch ((buf[HIERARCHY] >> 0) & 7) {
+	case 0:
+		p->u.ofdm.hierarchy_information = HIERARCHY_NONE;
+		break;
+	case 1:
+		p->u.ofdm.hierarchy_information = HIERARCHY_1;
+		break;
+	case 2:
+		p->u.ofdm.hierarchy_information = HIERARCHY_2;
+		break;
+	case 3:
+		p->u.ofdm.hierarchy_information = HIERARCHY_4;
+		break;
+	}
+
+	switch ((buf[CODE_RATE_HP] >> 0) & 7) {
+	case 0:
+		p->u.ofdm.code_rate_HP = FEC_1_2;
+		break;
+	case 1:
+		p->u.ofdm.code_rate_HP = FEC_2_3;
+		break;
+	case 2:
+		p->u.ofdm.code_rate_HP = FEC_3_4;
+		break;
+	case 3:
+		p->u.ofdm.code_rate_HP = FEC_5_6;
+		break;
+	case 4:
+		p->u.ofdm.code_rate_HP = FEC_7_8;
+		break;
+	case 5:
+		p->u.ofdm.code_rate_HP = FEC_NONE;
+		break;
+	}
+
+	switch ((buf[CODE_RATE_LP] >> 0) & 7) {
+	case 0:
+		p->u.ofdm.code_rate_LP = FEC_1_2;
+		break;
+	case 1:
+		p->u.ofdm.code_rate_LP = FEC_2_3;
+		break;
+	case 2:
+		p->u.ofdm.code_rate_LP = FEC_3_4;
+		break;
+	case 3:
+		p->u.ofdm.code_rate_LP = FEC_5_6;
+		break;
+	case 4:
+		p->u.ofdm.code_rate_LP = FEC_7_8;
+		break;
+	case 5:
+		p->u.ofdm.code_rate_HP = FEC_NONE;
+		break;
+	}
+
+	switch ((buf[BANDWIDTH] >> 0) & 3) {
+	case 0:
+		p->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
+		break;
+	case 1:
+		p->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
+		break;
+	case 2:
+		p->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
+		break;
+#if 0 /* keep */
+	case 3:
+		p->u.ofdm.bandwidth = BANDWIDTH_5_MHZ;
+		break;
+#endif
+	}
+
+	p->inversion = INVERSION_AUTO;
+	p->frequency = state->frequency;
+
+error:
+	if (ret)
+		deb_info("%s: failed:%d\n", __func__, ret);
+
+	return ret;
+}
+#endif
+
+static int af9033_update_ber_ucblocks(struct dvb_frontend *fe)
+{
+	struct af9033_state *state = fe->demodulator_priv;
+	int ret;
+	u8 buf[3];
+	u32 error_bit_count = 0;
+	u32 total_bit_count = 0;
+	u16 abort_packet_count = 0;
+
+	/* don't update ber / ucblocks unnecessary often */
+	if (time_before(jiffies, state->next_statistics_check))
+		return 0;
+
+	/* set minimum ber / ucblocks update interval */
+	state->next_statistics_check = jiffies + msecs_to_jiffies(500);
+
+	state->ber = 0;
+
+	/* no need to check ber / ucblocks in case of no lock */
+	ret = af9033_read_reg_bits(state, OFDM,
+		r_mp2if_sync_byte_locked, mp2if_sync_byte_locked_pos,
+		mp2if_sync_byte_locked_len, buf);
+	if (ret)
+		goto error;
+	if (!buf[0])
+		goto exit;
+
+	/* get abort packet count */
+	ret = af9033_read_regs(state, OFDM, api_rsd_abort_packet_cnt_7_0, buf,
+		sizeof(buf) - 1);
+	if (ret)
+		goto error;
+
+	abort_packet_count = (buf[1] << 8) + buf[0];
+
+	/* get error bit count */
+	ret = af9033_read_regs(state, OFDM, api_rsd_bit_err_cnt_7_0, buf,
+		sizeof(buf));
+	if (ret)
+		goto error;
+
+	error_bit_count = (buf[2] << 16) + (buf[1] << 8) + buf[0];
+	error_bit_count = error_bit_count - abort_packet_count * 8 * 8;
+
+	/* get used RSD counting period (it is 10000 by defaut) */
+	ret = af9033_read_regs(state, OFDM, api_r_rsd_packet_unit_7_0, buf,
+		sizeof(buf) - 1);
+	if (ret)
+		goto error;
+
+	total_bit_count = (buf[1] << 8) + buf[0];
+	total_bit_count = total_bit_count - abort_packet_count;
+	total_bit_count = total_bit_count * 204 * 8;
+
+	if (total_bit_count)
+		state->ber = error_bit_count * 1000000000 / total_bit_count;
+
+	state->ucblocks += abort_packet_count;
+
+	deb_info("%s: err bits:%d total bits:%d abort count:%d\n", __func__,
+		error_bit_count, total_bit_count, abort_packet_count);
+
+error:
+	if (ret)
+		deb_info("%s: failed:%d\n", __func__, ret);
+exit:
+	return ret;
+}
+
+static int af9033_update_snr(struct dvb_frontend *fe)
+{
+	struct af9033_state *state = fe->demodulator_priv;
+	int ret;
+	u8 buf[3], i, len;
+	u32 snr_val;
+	struct snr_table *uninitialized_var(snr_table);
+
+	/* read snr registers */
+	ret = af9033_read_regs(state, OFDM, api_qnt_vbc_err_7_0, buf,
+		sizeof(buf));
+	if (ret)
+		goto error;
+	snr_val = (buf[2] << 16) + (buf[1] << 8) + buf[0];
+
+	/* read current constellation */
+	ret = af9033_read_reg_bits(state, OFDM, g_reg_tpsd_const,
+		reg_tpsd_const_pos, reg_tpsd_const_len, &buf[0]);
+	if (ret)
+		goto error;
+
+	switch (buf[0]) {
+	case 0:
+		len = ARRAY_SIZE(qpsk_snr_table);
+		snr_table = qpsk_snr_table;
+		break;
+	case 1:
+		len = ARRAY_SIZE(qam16_snr_table);
+		snr_table = qam16_snr_table;
+		break;
+	case 2:
+		len = ARRAY_SIZE(qam64_snr_table);
+		snr_table = qam64_snr_table;
+		break;
+	default:
+		len = 0;
+	}
+
+	/* get snr from lookup table */
+	for (i = 0; i < len; i++) {
+		if (snr_val < snr_table[i].val) {
+			state->snr = snr_table[i].snr * 10;
+			break;
+		}
+	}
+	deb_info("%s: snr_val:%x snr:%x\n", __func__, snr_val, state->snr);
+
+	if (len && !af9033_snrdb)
+		state->snr = (0xffff / (snr_table[len - 1].snr * 10)) * state->snr;
+
+error:
+	return ret;
+}
+
+static int af9033_update_signal_strength(struct dvb_frontend *fe)
+{
+	struct af9033_state *state = fe->demodulator_priv;
+	int ret;
+	u8 strength;
+
+	/* read signal strength from 0-100 scale */
+	ret = af9033_read_reg(state, OFDM, api_signal_strength, &strength);
+	if (ret)
+		goto error;
+
+	/* scale value to 0x0000-0xffff */
+	state->signal_strength = strength * 0xffff / 100;
+
+error:
+	return ret;
+}
+
+static int af9033_read_status(struct dvb_frontend *fe, fe_status_t *status)
+{
+	struct af9033_state *state = fe->demodulator_priv;
+	int ret = 0;
+	u8 tmp;
+	*status = 0;
+
+	/* empty channel; 0:no result, 1:signal, 2:empty */
+	ret = af9033_read_reg(state, OFDM, api_empty_channel_status, &tmp);
+	if (ret)
+		goto error;
+	if (tmp == 0x01) /* have signal */
+		*status |= FE_HAS_SIGNAL;
+
+	if (tmp != 0x02) {
+		/* TPS lock */
+		ret = af9033_read_reg_bits(state, OFDM, p_fd_tpsd_lock,
+			fd_tpsd_lock_pos, fd_tpsd_lock_len, &tmp);
+		if (ret)
+			goto error;
+		if (tmp)
+			*status |= FE_HAS_VITERBI | FE_HAS_CARRIER;
+
+		/* MPEG2 lock */
+		ret = af9033_read_reg_bits(state, OFDM,
+			r_mp2if_sync_byte_locked, mp2if_sync_byte_locked_pos,
+			mp2if_sync_byte_locked_len, &tmp);
+		if (ret)
+			goto error;
+		if (tmp)
+			*status |= FE_HAS_SYNC | FE_HAS_LOCK;
+	}
+
+	/* update ber / ucblocks */
+	ret = af9033_update_ber_ucblocks(fe);
+
+error:
+	if (ret)
+		deb_info("%s: failed:%d\n", __func__, ret);
+
+	return ret;
+}
+
+static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber)
+{
+	struct af9033_state *state = fe->demodulator_priv;
+	int ret;
+	deb_info("%s\n", __func__);
+	ret = af9033_update_ber_ucblocks(fe);
+	*ber = state->ber;
+	return ret;
+}
+
+static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
+{
+	struct af9033_state *state = fe->demodulator_priv;
+	int ret;
+	deb_info("%s\n", __func__);
+	ret = af9033_update_signal_strength(fe);
+	if (ret)
+		goto error;
+	ret = af9033_update_ber_ucblocks(fe);
+	*strength = state->signal_strength;
+error:
+	return ret;
+}
+
+static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr)
+{
+	struct af9033_state *state = fe->demodulator_priv;
+	int ret;
+	deb_info("%s\n", __func__);
+	ret = af9033_update_snr(fe);
+	if (ret)
+		goto error;
+	ret = af9033_update_ber_ucblocks(fe);
+	*snr = state->snr;
+error:
+	return ret;
+}
+
+static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
+{
+	struct af9033_state *state = fe->demodulator_priv;
+	int ret;
+	deb_info("%s\n", __func__);
+	ret = af9033_update_ber_ucblocks(fe);
+	*ucblocks = state->ucblocks;
+	return ret;
+}
+
+static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
+{
+	struct af9033_state *state = fe->demodulator_priv;
+	deb_info("%s: enable:%d\n", __func__, enable);
+
+	return af9033_write_reg_bits(state, LINK, p_reg_bypass_host2tuner,
+		reg_bypass_host2tuner_pos, reg_bypass_host2tuner_len, enable);
+}
+
+static struct dvb_frontend_ops af9033_ops;
+
+struct dvb_frontend *af9033_attach(const struct af9033_config *config,
+	struct i2c_adapter *i2c)
+{
+	int ret;
+	struct af9033_state *state = NULL;
+	u8 buf[8];
+	deb_info("%s:\n", __func__);
+
+	/* allocate memory for the internal state */
+	state = kzalloc(sizeof(struct af9033_state), GFP_KERNEL);
+	if (state == NULL)
+		goto error;
+
+	/* setup the state */
+	state->i2c = i2c;
+	memcpy(&state->config, config, sizeof(struct af9033_config));
+
+	/* firmware version */
+	ret = af9033_read_regs(state, LINK, 0x83e9, &buf[0], sizeof(buf) / 2);
+	if (ret)
+		goto error;
+
+	ret = af9033_read_regs(state, OFDM, 0x4191, &buf[4], sizeof(buf) / 2);
+	if (ret)
+		goto error;
+
+	info("firmware version: LINK:%d.%d.%d.%d OFDM:%d.%d.%d.%d",
+		buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);
+
+	/* settings for mp2if */
+	if (state->config.output_mode == AF9033_TS_MODE_USB) {
+		/* split 15 PSB to 1K + 1K and enable flow control */
+		ret = af9033_write_reg_bits(state, OFDM, p_reg_mp2if2_half_psb,
+			reg_mp2if2_half_psb_pos, reg_mp2if2_half_psb_len, 0);
+		if (ret)
+			goto error;
+		ret = af9033_write_reg_bits(state, OFDM, p_reg_mp2if_stop_en,
+			reg_mp2if_stop_en_pos, reg_mp2if_stop_en_len, 1);
+	} else {
+		/* AF9033 set mpeg to full speed */
+		ret = af9033_write_reg_bits(state, OFDM, p_reg_mpeg_full_speed,
+			reg_mpeg_full_speed_pos, reg_mpeg_full_speed_len, 0);
+		if (ret)
+			goto error;
+		ret = af9033_write_reg_bits(state, OFDM, p_reg_mp2if_stop_en,
+			reg_mp2if_stop_en_pos, reg_mp2if_stop_en_len, 0);
+	}
+	if (ret)
+		goto error;
+
+	/* set to 0 as open drain for tuner i2c */
+	ret = af9033_write_reg(state, LINK, p_reg_top_padodpu, 0);
+	if (ret)
+		goto error;
+
+	/* set to 0 as push pull for tuner AGC */
+	ret = af9033_write_reg(state, LINK, p_reg_top_agc_od, 0);
+	if (ret)
+		goto error;
+
+	/* create dvb_frontend */
+	memcpy(&state->frontend.ops, &af9033_ops,
+		sizeof(struct dvb_frontend_ops));
+	state->frontend.demodulator_priv = state;
+
+	return &state->frontend;
+error:
+	kfree(state);
+	return NULL;
+}
+EXPORT_SYMBOL(af9033_attach);
+
+static struct dvb_frontend_ops af9033_ops = {
+#ifdef V4L2_ONLY_DVB_V5
+	.delsys = { SYS_DVBT },
+#endif
+	.info = {
+		.name = "Afatech AF9033 DVB-T",
+#ifndef V4L2_ONLY_DVB_V5
+		.type = FE_OFDM,
+#endif
+		.frequency_min =  44250000,
+		.frequency_max = 867250000,
+		.frequency_stepsize = 62500,
+		.frequency_tolerance = 0,
+		.caps =
+			FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
+			FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
+			FE_CAN_QPSK | FE_CAN_QAM_16 |
+			FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
+			FE_CAN_TRANSMISSION_MODE_AUTO |
+			FE_CAN_GUARD_INTERVAL_AUTO |
+			FE_CAN_HIERARCHY_AUTO |
+			FE_CAN_RECOVER |
+			FE_CAN_MUTE_TS
+	},
+
+	.release = af9033_release,
+
+	.init = af9033_init,
+	.sleep = af9033_sleep,
+
+	.set_frontend = af9033_set_frontend,
+	.get_tune_settings = af9033_get_tune_settings,
+
+	.get_frontend = af9033_get_frontend,
+
+	.read_status = af9033_read_status,
+	.read_ber = af9033_read_ber,
+	.read_signal_strength = af9033_read_signal_strength,
+	.read_snr = af9033_read_snr,
+	.read_ucblocks = af9033_read_ucblocks,
+
+	.i2c_gate_ctrl = af9033_i2c_gate_ctrl,
+};
+
+MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
+MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/af9033.h b/drivers/media/dvb/frontends/af9033.h
new file mode 100644
index 0000000..53d2e80
--- /dev/null
+++ b/drivers/media/dvb/frontends/af9033.h
@@ -0,0 +1,100 @@
+/*
+ * Afatech AF9033 demodulator driver
+ *
+ * Copyright (C) 2008 Afatech
+ * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 2 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ * Thanks to TerraTec for a support received.
+ */
+
+#ifndef AF9033_H
+#define AF9033_H
+
+#include <linux/dvb/frontend.h>
+
+enum af9033_ts_mode {
+	AF9033_TS_MODE_PARALLEL,
+	AF9033_TS_MODE_SERIAL,
+	AF9033_TS_MODE_USB, /* only for AF9035 */
+};
+
+enum af9033_tuner {
+	AF9033_TUNER_TUA9001    = 0x27, /* Infineon TUA 9001 */
+	AF9033_TUNER_FC0011     = 0x28, /* Fitipower FC0011 */
+	AF9033_TUNER_MXL5007t   = 0xa0, /* Maxlinear MXL5007t */
+        AF9033_TUNER_TDA18218   = 0xa1, /* NXP TDA 18218HN */
+};
+
+/* clock setting table:
+ =================================
+ adc_clock  crystal_clock  Xtal
+ =================================
+ 20480000   20480000      FPGA
+ 16384000   20480000      16.38MHz
+ 20480000   20480000      20.48MHz
+ 36000000   20250000      36.00MHz
+ 30000000   20156250      30.00MHz
+ 26000000   20583333      26.00MHz
+ 28000000   20416667      28.00MHz
+ 32000000   20500000      32.00MHz
+ 34000000   20187500      34.00MHz
+ 24000000   20500000      24.00MHz
+ 22000000   20625000      22.00MHz
+ 12000000   20250000      12.00MHz
+*/
+
+struct af9033_config {
+	/* demodulator's I2C address */
+	u8 demod_address;
+
+	u8 tuner_address;
+
+	/* xtal clock Hz */
+	u32 crystal_clock;
+
+	/* ADC clock Hz */
+	u32 adc_clock;
+
+	/* tuner ID */
+	u8 tuner;
+
+	/* intermediate frequency Hz */
+	u32 if_freq;
+
+	/* TS data output mode */
+	u8 output_mode:2;
+
+	/* RF spectrum inversion */
+	u8 rf_spec_inv:1;
+};
+
+
+#if defined(CONFIG_DVB_AF9033) || \
+	(defined(CONFIG_DVB_AF9033_MODULE) && defined(MODULE))
+extern struct dvb_frontend *af9033_attach(const struct af9033_config *config,
+	struct i2c_adapter *i2c);
+#else
+static inline struct dvb_frontend *af9033_attach(
+const struct af9033_config *config, struct i2c_adapter *i2c)
+{
+	printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+	return NULL;
+}
+#endif /* CONFIG_DVB_AF9033 */
+
+#endif /* AF9033_H */
diff --git a/drivers/media/dvb/frontends/af9033_priv.h b/drivers/media/dvb/frontends/af9033_priv.h
new file mode 100644
index 0000000..6474bfa
--- /dev/null
+++ b/drivers/media/dvb/frontends/af9033_priv.h
@@ -0,0 +1,383 @@
+/*
+ * Afatech AF9033 demodulator driver
+ *
+ * Copyright (C) 2008 Afatech
+ * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 2 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ * Thanks to TerraTec for a support received.
+ */
+
+#ifndef AF9033_PRIV_H
+#define AF9033_PRIV_H
+
+#define LOG_PREFIX "af9033"
+
+#define dprintk(var, level, args...) \
+	    do { if ((var & level)) printk(args); } while (0)
+
+#define debug_dump(b, l, func) {\
+	int loop_; \
+	for (loop_ = 0; loop_ < l; loop_++) \
+		func("%02x ", b[loop_]); \
+	func("\n");\
+}
+
+#define deb_info(args...) dprintk(af9033_debug, 0x01, args)
+
+#undef err
+#define err(f, arg...)  printk(KERN_ERR     LOG_PREFIX": " f "\n" , ## arg)
+#undef info
+#define info(f, arg...) printk(KERN_INFO    LOG_PREFIX": " f "\n" , ## arg)
+#undef warn
+#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg)
+
+#define LINK 0x00
+#define OFDM 0x80
+
+struct regdesc {
+	u16 addr;
+	u8  val;
+};
+
+struct snr_table {
+	u32 val;
+	u8 snr;
+};
+
+/* QPSK SNR lookup table */
+static struct snr_table qpsk_snr_table[] = {
+	{0x000b4771,  0},
+	{0x000c1aed,  1},
+	{0x000d0d27,  2},
+	{0x000e4d19,  3},
+	{0x000e5da8,  4},
+	{0x00107097,  5},
+	{0x00116975,  6},
+	{0x001252d9,  7},
+	{0x00131fa4,  8},
+	{0x0013d5e1,  9},
+	{0x00148e53, 10},
+	{0x0015358b, 11},
+	{0x0015dd29, 12},
+	{0x00168112, 13},
+	{0x00170b61, 14},
+	{0x0017a532, 15},
+	{0x00180f94, 16},
+	{0x00186ed2, 17},
+	{0x0018b271, 18},
+	{0x0018e118, 19},
+	{0x0018ff4b, 20},
+	{0x00190af1, 21},
+	{0x00191451, 22},
+	{0xffffffff, 23},
+};
+
+/* QAM16 SNR lookup table */
+static struct snr_table qam16_snr_table[] = {
+	{0x0004f0d5,  0},
+	{0x0005387a,  1},
+	{0x000573a4,  2},
+	{0x0005a99e,  3},
+	{0x0005cc80,  4},
+	{0x0005eb62,  5},
+	{0x0005fecf,  6},
+	{0x00060b80,  7},
+	{0x00062501,  8},
+	{0x00064865,  9},
+	{0x00069604, 10},
+	{0x0006f356, 11},
+	{0x0007706a, 12},
+	{0x000804d3, 13},
+	{0x00089d1a, 14},
+	{0x00093e3d, 15},
+	{0x0009e35d, 16},
+	{0x000a7c3c, 17},
+	{0x000afaf8, 18},
+	{0x000b719d, 19},
+	{0x000bda6a, 20},
+	{0x000c0c75, 21},
+	{0x000c3f7d, 22},
+	{0x000c5e62, 23},
+	{0x000c6c31, 24},
+	{0x000c7925, 25},
+	{0xffffffff, 26},
+};
+
+/* QAM64 SNR lookup table */
+static struct snr_table qam64_snr_table[] = {
+	{0x000256d0,  0},
+	{0x00027a65,  1},
+	{0x00029873,  2},
+	{0x0002b7fe,  3},
+	{0x0002cf1e,  4},
+	{0x0002e234,  5},
+	{0x0002f409,  6},
+	{0x00030046,  7},
+	{0x00030844,  8},
+	{0x00030a02,  9},
+	{0x00030cde, 10},
+	{0x00031031, 11},
+	{0x0003144c, 12},
+	{0x000315dd, 13},
+	{0x00031920, 14},
+	{0x000322d0, 15},
+	{0x000339fc, 16},
+	{0x000364a1, 17},
+	{0x00038bcc, 18},
+	{0x0003c7d3, 19},
+	{0x000408cc, 20},
+	{0x00043bed, 21},
+	{0x00048061, 22},
+	{0x0004be95, 23},
+	{0x0004fa7d, 24},
+	{0x00052405, 25},
+	{0x0005570d, 26},
+	{0x00059feb, 27},
+	{0x0005bf38, 28},
+	{0xffffffff, 29},
+};
+
+static struct regdesc ofsm_init[] = {
+	{0x0051, 0x01},
+	{0x0070, 0x0A},
+	{0x007E, 0x04},
+	{0x0081, 0x0A},
+	{0x008A, 0x01},
+	{0x008E, 0x01},
+	{0x0092, 0x06},
+	{0x0099, 0x01},
+	{0x009F, 0xE1},
+	{0x00A0, 0xCF},
+	{0x00A3, 0x01},
+	{0x00A5, 0x01},
+	{0x00A6, 0x01},
+	{0x00A9, 0x00},
+	{0x00AA, 0x01},
+	{0x00AB, 0x01},
+	{0x00B0, 0x01},
+	{0x00C0, 0x05},
+	{0x00C4, 0x19},
+	{0xF000, 0x0F},
+	{0xF016, 0x10},
+	{0xF017, 0x04},
+	{0xF018, 0x05},
+	{0xF019, 0x04},
+	{0xF01A, 0x05},
+	{0xF021, 0x03},
+	{0xF022, 0x0A},
+	{0xF023, 0x0A},
+	{0xF02B, 0x00},
+	{0xF02C, 0x01},
+	{0xF064, 0x03},
+	{0xF065, 0xF9},
+	{0xF066, 0x03},
+	{0xF067, 0x01},
+	{0xF06F, 0xE0},
+	{0xF070, 0x03},
+	{0xF072, 0x0F},
+	{0xF073, 0x03},
+	{0xF078, 0x00},
+	{0xF087, 0x00},
+	{0xF09B, 0x3F},
+	{0xF09C, 0x00},
+	{0xF09D, 0x20},
+	{0xF09E, 0x00},
+	{0xF09F, 0x0C},
+	{0xF0A0, 0x00},
+	{0xF130, 0x04},
+	{0xF132, 0x04},
+	{0xF144, 0x1A},
+	{0xF146, 0x00},
+	{0xF14A, 0x01},
+	{0xF14C, 0x00},
+	{0xF14D, 0x00},
+	{0xF14F, 0x04},
+	{0xF158, 0x7F},
+	{0xF15A, 0x00},
+	{0xF15B, 0x08},
+	{0xF15D, 0x03},
+	{0xF15E, 0x05},
+	{0xF163, 0x05},
+	{0xF166, 0x01},
+	{0xF167, 0x40},
+	{0xF168, 0x0F},
+	{0xF17A, 0x00},
+	{0xF17B, 0x00},
+	{0xF183, 0x01},
+	{0xF19D, 0x40},
+	{0xF1BC, 0x36},
+	{0xF1BD, 0x00},
+	{0xF1CB, 0xA0},
+	{0xF1CC, 0x01},
+	{0xF204, 0x10},
+	{0xF214, 0x00},
+	{0xF40E, 0x0A},
+	{0xF40F, 0x40},
+	{0xF410, 0x08},
+	{0xF55F, 0x0A},
+	{0xF561, 0x15},
+	{0xF562, 0x20},
+	{0xF5DF, 0xFB},
+	{0xF5E0, 0x00},
+	{0xF5E3, 0x09},
+	{0xF5E4, 0x01},
+	{0xF5E5, 0x01},
+	{0xF5F8, 0x01},
+	{0xF5FD, 0x01},
+	{0xF600, 0x05},
+	{0xF601, 0x08},
+	{0xF602, 0x0B},
+	{0xF603, 0x0E},
+	{0xF604, 0x11},
+	{0xF605, 0x14},
+	{0xF606, 0x17},
+	{0xF607, 0x1F},
+	{0xF60E, 0x00},
+	{0xF60F, 0x04},
+	{0xF610, 0x32},
+	{0xF611, 0x10},
+	{0xF707, 0xFC},
+	{0xF708, 0x00},
+	{0xF709, 0x37},
+	{0xF70A, 0x00},
+	{0xF78B, 0x01},
+	{0xF80F, 0x40},
+	{0xF810, 0x54},
+	{0xF811, 0x5A},
+	{0xF905, 0x01},
+	{0xFB06, 0x03},
+	{0xFD8B, 0x00}
+};
+
+/* Infineon TUA 9001 tuner init
+   AF9033_TUNER_TUA9001    = 0x27 */
+static struct regdesc tuner_init_tua9001[] = {
+	{0x0046, 0x27},
+	{0x0057, 0x00},
+	{0x0058, 0x01},
+	{0x005f, 0x00},
+	{0x0060, 0x00},
+	{0x006d, 0x00},
+	{0x0071, 0x05},
+	{0x0072, 0x02},
+	{0x0074, 0x01},
+	{0x0075, 0x03},
+	{0x0076, 0x02},
+	{0x0077, 0x00},
+	{0x0078, 0x01},
+	{0x0079, 0x00},
+	{0x007a, 0x7E},
+	{0x007b, 0x3E},
+	{0x0093, 0x00},
+	{0x0094, 0x01},
+	{0x0095, 0x02},
+	{0x0096, 0x01},
+	{0x0098, 0x0A},
+	{0x009b, 0x05},
+	{0x009c, 0x80},
+	{0x00b3, 0x00},
+	{0x00c1, 0x01},
+	{0x00c2, 0x00},
+	{0xF007, 0x00},
+	{0xF01F, 0x82},
+	{0xF020, 0x00},
+	{0xF029, 0x82},
+	{0xF02A, 0x00},
+	{0xF047, 0x00},
+	{0xF054, 0x00},
+	{0xF055, 0x00},
+	{0xF077, 0x01},
+	{0xF1E6, 0x00},
+};
+
+/* NXP TDA18218 tuner init
+   AF9033_TUNER_TDA18218   = 161 */
+static struct regdesc tuner_init_tda18218[] = {
+        {0x0046, 0x27},
+        {0x0071, 0x05},
+        {0x0072, 0x02},
+        {0x0074, 0x01},
+        {0x0075, 0x03},
+        {0x0076, 0x02},
+        {0x0077, 0x00},
+        {0x0078, 0x01},
+        {0x007a, 0x7e},
+        {0x007b, 0x3e},
+        {0x0098, 0x0a},
+        {0x00b3, 0x00},
+        {0xf007, 0x00},
+        {0xf01f, 0x82},
+        {0xf020, 0x00},
+        {0xf047, 0x00},
+        {0xf077, 0x01},
+        {0xf1e6, 0x00},
+        {0x0057, 0x00},
+        {0x0058, 0x01},
+        {0x005f, 0x00},
+        {0x0060, 0x00},
+        {0x006d, 0x00},
+        {0x0079, 0x00},
+        {0x0093, 0x00},
+        {0x0094, 0x01},
+        {0x0095, 0x02},
+        {0x0096, 0x01},
+        {0x009b, 0x05},
+        {0x009c, 0x80},
+        {0x00c1, 0x01},
+        {0x00c2, 0x00},
+        {0xf029, 0x82},
+        {0xf02a, 0x00},
+        {0xf054, 0x00},
+        {0xf055, 0x00},
+};
+
+static struct regdesc tuner_init_mxl5007t[] = {
+	{0x0046, 0x1b},
+	{0x0057, 0x01},
+	{0x0058, 0x01},
+	{0x005f, 0x00},
+	{0x0060, 0x00},
+	{0x0068, 0x96},
+	{0x0071, 0x05},
+	{0x0072, 0x02},
+	{0x0074, 0x01},
+	{0x0079, 0x01},
+	{0x0093, 0x00},
+	{0x0094, 0x00},
+	{0x0095, 0x00},
+	{0x0096, 0x00},
+	{0x00b3, 0x01},
+	{0x00c1, 0x01},
+	{0x00c2, 0x00},
+	{0xF007, 0x00},
+	{0xF00C, 0x19},
+	{0xF00D, 0x1a},
+	{0xF012, 0xda},
+	{0xF013, 0x00},
+	{0xF014, 0x00},
+	{0xF015, 0x02},
+	{0xF01F, 0x82},
+	{0xF020, 0x00},
+	{0xF029, 0x82},
+	{0xF02A, 0x00},
+	{0xF077, 0x02},
+	{0xF1E6, 0x00},
+};
+
+#endif /* AF9033_PRIV_H */
+
diff --git a/drivers/media/dvb/frontends/af9033_reg.h b/drivers/media/dvb/frontends/af9033_reg.h
new file mode 100644
index 0000000..078276c
--- /dev/null
+++ b/drivers/media/dvb/frontends/af9033_reg.h
@@ -0,0 +1,11006 @@
+/*
+ * Afatech AF9033 demodulator driver
+ *
+ * Copyright (C) 2008 Afatech
+ * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 2 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ * Thanks to TerraTec for a support received.
+ */
+
+#ifndef AF9033_REG_H
+#define AF9033_REG_H
+
+/* these variables are initialized by API */
+#define api_var_addr_base                       0x418b
+#define api_log_addr_base                       0x418d
+#define api_log_data_base                       0x418f
+#define api_LowerLocalRetrain                   0x43bb
+
+#define api_trigger_ofsm                        0x0000
+#define api_cfoe_NS_2048_coeff1_25_24           0x0001
+#define api_cfoe_NS_2048_coeff1_23_16           0x0002
+#define api_cfoe_NS_2048_coeff1_15_8            0x0003
+#define api_cfoe_NS_2048_coeff1_7_0             0x0004
+#define api_cfoe_NS_2k_coeff2_24                0x0005
+#define api_cfoe_NS_2k_coeff2_23_16             0x0006
+#define api_cfoe_NS_2k_coeff2_15_8              0x0007
+#define api_cfoe_NS_2k_coeff2_7_0               0x0008
+#define api_cfoe_NS_8191_coeff1_25_24           0x0009
+#define api_cfoe_NS_8191_coeff1_23_16           0x000a
+#define api_cfoe_NS_8191_coeff1_15_8            0x000b
+#define api_cfoe_NS_8191_coeff1_7_0             0x000c
+#define api_cfoe_NS_8192_coeff1_25_24           0x000d
+#define api_cfoe_NS_8192_coeff1_23_16           0x000e
+#define api_cfoe_NS_8192_coeff1_15_8            0x000f
+#define api_cfoe_NS_8192_coeff1_7_0             0x0010
+#define api_cfoe_NS_8193_coeff1_25_24           0x0011
+#define api_cfoe_NS_8193_coeff1_23_16           0x0012
+#define api_cfoe_NS_8193_coeff1_15_8            0x0013
+#define api_cfoe_NS_8193_coeff1_7_0             0x0014
+#define api_cfoe_NS_8k_coeff2_24                0x0015
+#define api_cfoe_NS_8k_coeff2_23_16             0x0016
+#define api_cfoe_NS_8k_coeff2_15_8              0x0017
+#define api_cfoe_NS_8k_coeff2_7_0               0x0018
+#define api_cfoe_NS_4096_coeff1_25_24           0x0019
+#define api_cfoe_NS_4096_coeff1_23_16           0x001a
+#define api_cfoe_NS_4096_coeff1_15_8            0x001b
+#define api_cfoe_NS_4096_coeff1_7_0             0x001c
+#define api_cfoe_NS_4k_coeff2_24                0x001d
+#define api_cfoe_NS_4k_coeff2_23_16             0x001e
+#define api_cfoe_NS_4k_coeff2_15_8              0x001f
+#define api_cfoe_NS_4k_coeff2_7_0               0x0020
+
+#define api_bfsfcw_fftindex_ratio_7_0           0x0021
+#define api_bfsfcw_fftindex_ratio_15_8          0x0022
+#define api_fftindex_bfsfcw_ratio_7_0           0x0023
+#define api_fftindex_bfsfcw_ratio_15_8          0x0024
+
+#define api_crystal_clk_7_0                     0x0025
+#define api_crystal_clk_15_8                    0x0026
+#define api_crystal_clk_23_16                   0x0027
+#define api_crystal_clk_31_24                   0x0028
+
+#define api_bfs_fcw_7_0                         0x0029
+#define api_bfs_fcw_15_8                        0x002a
+#define api_bfs_fcw_22_16                       0x002b
+
+#define api_qnt_vbc_err_7_0                     0x002c
+#define api_qnt_vbc_err_15_8                    0x002d
+#define api_qnt_vbc_err_23_16                   0x002e
+#define api_r_qnt_vbc_sframe_num                0x002f
+#define api_tpsd_const                          0x0030
+#define api_tpsd_txmod                          0x0031
+ 
+#define api_rsd_abort_packet_cnt_7_0            0x0032
+#define api_rsd_abort_packet_cnt_15_8           0x0033
+#define api_rsd_bit_err_cnt_7_0                 0x0034
+#define api_rsd_bit_err_cnt_15_8                0x0035
+#define api_rsd_bit_err_cnt_23_16               0x0036
+#define api_r_rsd_packet_unit_7_0               0x0037
+#define api_r_rsd_packet_unit_15_8              0x0038
+
+#define api_qnt_vbc_sframe_num                  0x0039
+#define api_rsd_packet_unit_7_0                 0x003a
+#define api_rsd_packet_unit_15_8                0x003b
+
+#define api_tpsd_lock                           0x003c
+#define api_mpeg_lock                           0x003d
+#define api_RsdSequence                         0x003e
+#define api_VtbSequence                         0x003f
+
+#define api_Training_Mode                       0x0040
+#define api_RESET_STATE                         0x0041
+#define api_EXT_LNA_OFF                         0x0042
+#define api_aci_0                               0x0043
+#define api_aci_1                               0x0044
+
+#define api_adcx2                               0x0045
+#define api_tuner_ID                            0x0046
+#define api_empty_channel_status                0x0047
+#define api_signal_strength                     0x0048
+#define api_signal_quality                      0x0049
+#define api_est_rf_level_dbm                    0x004a
+#define api_FreBand                             0x004b
+#define api_suspend_flag                        0x004c
+#define api_SupportRelayCommandWrite            0x004d
+#define api_RelayCommandWrite                   0x004e
+
+#define api_OfdmGuiRCN_H                        0x004f
+#define api_OfdmGuiRCN_L                        0x0050
+#define api_antenna_unplugged                   0x0051
+#define api_strong_signal_detected              0x0052
+#define api_channelFlatnessInd                  0x0053
+#define api_Flatness_Ind_nonCmb                 0x0054
+#define api_AutoDetectedSpectrumInv             0x0055
+#define api_IsSpectrumInv                       0x0056
+#define api_strong_detect_bypass                0x0057
+#define api_ss_dtop_bypass                      0x0058
+#define api_retrain_dtop_bypass                 0x0059
+#define api_EnableTimeSlice                     0x005a
+#define api_SynchronizationType                 0x005b
+#define api_ApplyFastSynchronizationToEchoChannel 0x005c
+#define api_ApplyPwmToRfIf                      0x005d
+#define api_ChannelNo                           0x005e
+
+#define api_csi_bypass                          0x005f
+#define api_mobile_bypass                       0x0060
+#define api_EnableSpeedLog                      0x0061
+
+#define api_r_rsd_abort_total_packet_7_0        0x0062
+#define api_r_rsd_abort_total_packet_15_8       0x0063
+#define api_r_rsd_abort_total_packet_23_16      0x0064
+#define api_MaxRsdSequence                      0x0065
+#define api_RsdFrameNo                          0x0066
+#define api_MPESuperFrameNo                     0x0067
+
+#define api_AgcDesiredLevel                     0x0068
+#define api_MinRfGain                           0x0069
+#define api_MaxIfGain                           0x006a
+#define api_RssiOffset                          0x006b
+#define api_RssiResidual                        0x006c
+
+#define api_strong_weak_signal_default          0x006d
+#define api_PionDiodeDefaultResetInVHF          0x006e
+#define api_afe_mem4_rssi_comp                  0x006f
+
+#define api_aagc_speed_detect_count             0x0070
+#define api_aagc_mobile_thr                     0x0071
+#define api_aagc_nonmobile_thr                  0x0072
+#define api_agc_counter                         0x0073
+#define api_DisableAagcTop                      0x0074
+#define api_AgcReset                            0x0075
+#define api_AgcUp                               0x0076
+#define api_AgcDown                             0x0077
+#define api_AgcHold                             0x0078
+#define api_PwmCtrlHw                           0x0079
+#define api_MaxAgcGain                          0x007a
+#define api_IniAgcGain                          0x007b
+#define api_mccid_bypass                        0x007c
+#define api_CdpfEnDefaultEchoRange              0x007d
+#define api_CdpfIniTestNoSteady                 0x007e
+#define api_timing_err_level                    0x007f
+#define api_timing_retrain_cnt                  0x0080
+#define api_ChannelDiffThrSteady                0x0081
+
+#define api_adjacent_on                         0x0082
+#define api_near_adjacent_on                    0x0083
+#define api_adjacent_off                        0x0084
+#define api_near_adjacent_off                   0x0085
+#define api_max_rf_agc_7_0                      0x0086
+#define api_max_rf_agc_9_8                      0x0087
+#define api_rf_top_numerator_s_7_0              0x0088
+#define api_rf_top_numerator_s_9_8              0x0089
+
+#define api_gui_tdi_lms_en                      0x008a
+#define api_fccid_strobe_scale                  0x008b
+#define api_fccid_strobe_numerator              0x008c
+#define api_fccid_strobe_base                   0x008d
+#define api_use_fccid                           0x008e
+#define api_fft_ave_symbol_num                  0x008f
+#define api_large_tone_num_th_7_0               0x0090
+#define api_large_tone_num_th_15_8              0x0091
+#define api_use_3m_lpf_th                       0x0092
+#define api_ce_var_min_8k                       0x0093
+#define api_ce_var_min_4k                       0x0094
+#define api_ce_var_min_2k                       0x0095
+#define api_ce_var_min_8k_non_flat              0x0096
+#define api_flatness_thr                        0x0097
+#define api_non_mobile_signal_level_offset      0x0098
+#define api_gui_ar_csi_en                       0x0099
+#define api_h2_echo_detected                    0x009a
+#define api_gain_offset_O                       0x009b
+#define api_gain_slope_O                        0x009c
+#define api_pin_diode_gain_loss                 0x009d
+#define api_signal_strength_if_low              0x009e
+
+#define api_flatness_thr_high                   0x009f
+#define api_flatness_thr_low                    0x00a0
+
+#define api_sbq1                                0x00a1
+#define api_sbq2                                0x00a2
+
+#define api_dyna_dca_offset_en                  0x00a3
+#define api_dca_sbq_bad_th                      0x00a4
+#define api_detect_timing_err_en                0x00a5
+#define api_flatness_from_h2_echo               0x00a6
+
+#define api_timging_error_detection             0x00a7
+#define api_ce_forced_by_rotate                 0x00a8
+#define api_fccid_fft_mask_en                   0x00a9
+#define api_second_fctrl_unforce_en             0x00aa
+#define api_force_fdi0_at_high_mobile_en        0x00ab
+#define api_high_mobile_detected                0x00ac
+#define api_flatness_detection_en               0x00ad
+#define api_ChooseFsteCostFunctionFromCdpf      0x00ae
+#define api_signal_level                        0x00af
+#define api_TryConf2En                          0x00b0
+#define api_Lower_tpsd_lock                     0x00b1
+#define api_Upper_tpsd_lock                     0x00b2
+
+#define api_AgcCtrlType                         0x00b3
+#define api_opt_LNA_Rssi_scale                  0x00b4
+#define api_StopByTcl                           0x00b5
+#define api_RssiCalibration                     0x00b6
+#define api_AciDesiredSignalLevel_h             0x00b7
+#define api_AciDesiredSignalLevel_l             0x00b8
+#define api_ECO_ASIC                            0x00b9
+#define api_NXP_USE_I2C                         0x00ba
+#define api_rf_freqency_23_16                   0x00bb
+#define api_rf_freqency_15_8                    0x00bc
+#define api_rf_freqency_7_0                     0x00bd
+#define api_iqik_en                             0x00be
+#define api_dcc_en                              0x00bf
+#define api_CdpfIniTestNoMobile                 0x00c0
+#define api_ACIdetection                        0x00c1
+#define api_PinDiode                            0x00c2
+#define api_LNA_Gain                            0x00c3
+#define api_ChannelDiffThrMobile                0x00c4
+#define api_var_end                             0x00c5
+
+/* registers */
+#define    p_reg_p_aagc_log_2_acc   0xF000
+#define reg_p_aagc_log_2_acc_pos 0
+#define reg_p_aagc_log_2_acc_len 4
+#define reg_p_aagc_log_2_acc_lsb 0
+#define    p_reg_p_aagc_signal_level_rdy    0xF001
+#define reg_p_aagc_signal_level_rdy_pos 0
+#define reg_p_aagc_signal_level_rdy_len 1
+#define reg_p_aagc_signal_level_rdy_lsb 0
+#define    r_reg_r_aagc_signal_level_7_0    0xF002
+#define reg_r_aagc_signal_level_7_0_pos 0
+#define reg_r_aagc_signal_level_7_0_len 8
+#define reg_r_aagc_signal_level_7_0_lsb 0
+#define    r_reg_r_aagc_signal_level_9_8    0xF003
+#define reg_r_aagc_signal_level_9_8_pos 0
+#define reg_r_aagc_signal_level_9_8_len 2
+#define reg_r_aagc_signal_level_9_8_lsb 8
+#define    p_reg_p_aagc_rf_if_swap  0xF004
+#define reg_p_aagc_rf_if_swap_pos 0
+#define reg_p_aagc_rf_if_swap_len 1
+#define reg_p_aagc_rf_if_swap_lsb 0
+#define    p_reg_p_pwm_rf_if_from_hw    0xF006
+#define reg_p_pwm_rf_if_from_hw_pos 0
+#define reg_p_pwm_rf_if_from_hw_len 1
+#define reg_p_pwm_rf_if_from_hw_lsb 0
+#define    p_reg_aagc_out_if_inv    0xF007
+#define reg_aagc_out_if_inv_pos 0
+#define reg_aagc_out_if_inv_len 1
+#define reg_aagc_out_if_inv_lsb 0
+#define    p_reg_aagc_int_en    0xF008
+#define reg_aagc_int_en_pos 0
+#define reg_aagc_int_en_len 1
+#define reg_aagc_int_en_lsb 0
+#define    p_reg_aagc_lock_change_flag  0xF009
+#define reg_aagc_lock_change_flag_pos 0
+#define reg_aagc_lock_change_flag_len 1
+#define reg_aagc_lock_change_flag_lsb 0
+#define    p_reg_aagc_rf_loop_bw_scale_acquire  0xF00A
+#define reg_aagc_rf_loop_bw_scale_acquire_pos 0
+#define reg_aagc_rf_loop_bw_scale_acquire_len 5
+#define reg_aagc_rf_loop_bw_scale_acquire_lsb 0
+#define    p_reg_aagc_rf_loop_bw_scale_track    0xF00B
+#define reg_aagc_rf_loop_bw_scale_track_pos 0
+#define reg_aagc_rf_loop_bw_scale_track_len 5
+#define reg_aagc_rf_loop_bw_scale_track_lsb 0
+#define    p_reg_aagc_if_loop_bw_scale_acquire  0xF00C
+#define reg_aagc_if_loop_bw_scale_acquire_pos 0
+#define reg_aagc_if_loop_bw_scale_acquire_len 5
+#define reg_aagc_if_loop_bw_scale_acquire_lsb 0
+#define    p_reg_aagc_if_loop_bw_scale_track    0xF00D
+#define reg_aagc_if_loop_bw_scale_track_pos 0
+#define reg_aagc_if_loop_bw_scale_track_len 5
+#define reg_aagc_if_loop_bw_scale_track_lsb 0
+#define    p_reg_aagc_max_rf_agc_7_0    0xF00E
+#define reg_aagc_max_rf_agc_7_0_pos 0
+#define reg_aagc_max_rf_agc_7_0_len 8
+#define reg_aagc_max_rf_agc_7_0_lsb 0
+#define    p_reg_aagc_max_rf_agc_9_8    0xF00F
+#define reg_aagc_max_rf_agc_9_8_pos 0
+#define reg_aagc_max_rf_agc_9_8_len 2
+#define reg_aagc_max_rf_agc_9_8_lsb 8
+#define    p_reg_aagc_min_rf_agc_7_0    0xF010
+#define reg_aagc_min_rf_agc_7_0_pos 0
+#define reg_aagc_min_rf_agc_7_0_len 8
+#define reg_aagc_min_rf_agc_7_0_lsb 0
+#define    p_reg_aagc_min_rf_agc_9_8    0xF011
+#define reg_aagc_min_rf_agc_9_8_pos 0
+#define reg_aagc_min_rf_agc_9_8_len 2
+#define reg_aagc_min_rf_agc_9_8_lsb 8
+#define    p_reg_aagc_max_if_agc_7_0    0xF012
+#define reg_aagc_max_if_agc_7_0_pos 0
+#define reg_aagc_max_if_agc_7_0_len 8
+#define reg_aagc_max_if_agc_7_0_lsb 0
+#define    p_reg_aagc_max_if_agc_9_8    0xF013
+#define reg_aagc_max_if_agc_9_8_pos 0
+#define reg_aagc_max_if_agc_9_8_len 2
+#define reg_aagc_max_if_agc_9_8_lsb 8
+#define    p_reg_aagc_min_if_agc_7_0    0xF014
+#define reg_aagc_min_if_agc_7_0_pos 0
+#define reg_aagc_min_if_agc_7_0_len 8
+#define reg_aagc_min_if_agc_7_0_lsb 0
+#define    p_reg_aagc_min_if_agc_9_8    0xF015
+#define reg_aagc_min_if_agc_9_8_pos 0
+#define reg_aagc_min_if_agc_9_8_len 2
+#define reg_aagc_min_if_agc_9_8_lsb 8
+#define    p_reg_aagc_lock_sample_scale 0xF016
+#define reg_aagc_lock_sample_scale_pos 0
+#define reg_aagc_lock_sample_scale_len 5
+#define reg_aagc_lock_sample_scale_lsb 0
+#define    p_reg_aagc_rf_agc_lock_scale_acquire 0xF017
+#define reg_aagc_rf_agc_lock_scale_acquire_pos 0
+#define reg_aagc_rf_agc_lock_scale_acquire_len 3
+#define reg_aagc_rf_agc_lock_scale_acquire_lsb 0
+#define    p_reg_aagc_rf_agc_lock_scale_track   0xF018
+#define reg_aagc_rf_agc_lock_scale_track_pos 0
+#define reg_aagc_rf_agc_lock_scale_track_len 3
+#define reg_aagc_rf_agc_lock_scale_track_lsb 0
+#define    p_reg_aagc_if_agc_lock_scale_acquire 0xF019
+#define reg_aagc_if_agc_lock_scale_acquire_pos 0
+#define reg_aagc_if_agc_lock_scale_acquire_len 3
+#define reg_aagc_if_agc_lock_scale_acquire_lsb 0
+#define    p_reg_aagc_if_agc_lock_scale_track   0xF01A
+#define reg_aagc_if_agc_lock_scale_track_pos 0
+#define reg_aagc_if_agc_lock_scale_track_len 3
+#define reg_aagc_if_agc_lock_scale_track_lsb 0
+#define    p_reg_aagc_rf_top_numerator_s_7_0    0xF01B
+#define reg_aagc_rf_top_numerator_s_7_0_pos 0
+#define reg_aagc_rf_top_numerator_s_7_0_len 8
+#define reg_aagc_rf_top_numerator_s_7_0_lsb 0
+#define    p_reg_aagc_rf_top_numerator_s_9_8    0xF01C
+#define reg_aagc_rf_top_numerator_s_9_8_pos 0
+#define reg_aagc_rf_top_numerator_s_9_8_len 2
+#define reg_aagc_rf_top_numerator_s_9_8_lsb 8
+#define    p_reg_aagc_if_top_numerator_s_7_0    0xF01D
+#define reg_aagc_if_top_numerator_s_7_0_pos 0
+#define reg_aagc_if_top_numerator_s_7_0_len 8
+#define reg_aagc_if_top_numerator_s_7_0_lsb 0
+#define    p_reg_aagc_if_top_numerator_s_9_8    0xF01E
+#define reg_aagc_if_top_numerator_s_9_8_pos 0
+#define reg_aagc_if_top_numerator_s_9_8_len 2
+#define reg_aagc_if_top_numerator_s_9_8_lsb 8
+#define    p_reg_aagc_adc_out_desired_s_7_0 0xF01F
+#define reg_aagc_adc_out_desired_s_7_0_pos 0
+#define reg_aagc_adc_out_desired_s_7_0_len 8
+#define reg_aagc_adc_out_desired_s_7_0_lsb 0
+#define    p_reg_aagc_adc_out_desired_s_8   0xF020
+#define reg_aagc_adc_out_desired_s_8_pos 0
+#define reg_aagc_adc_out_desired_s_8_len 1
+#define reg_aagc_adc_out_desired_s_8_lsb 8
+#define    p_reg_aagc_lock_count_th 0xF021
+#define reg_aagc_lock_count_th_pos 0
+#define reg_aagc_lock_count_th_len 4
+#define reg_aagc_lock_count_th_lsb 0
+#define    p_reg_aagc_rf_agc_unlock_numerator   0xF022
+#define reg_aagc_rf_agc_unlock_numerator_pos 0
+#define reg_aagc_rf_agc_unlock_numerator_len 6
+#define reg_aagc_rf_agc_unlock_numerator_lsb 0
+#define    p_reg_aagc_if_agc_unlock_numerator   0xF023
+#define reg_aagc_if_agc_unlock_numerator_pos 0
+#define reg_aagc_if_agc_unlock_numerator_len 6
+#define reg_aagc_if_agc_unlock_numerator_lsb 0
+#define    p_reg_aagc_rf_top_numerator_m_7_0    0xF025
+#define reg_aagc_rf_top_numerator_m_7_0_pos 0
+#define reg_aagc_rf_top_numerator_m_7_0_len 8
+#define reg_aagc_rf_top_numerator_m_7_0_lsb 0
+#define    p_reg_aagc_rf_top_numerator_m_9_8    0xF026
+#define reg_aagc_rf_top_numerator_m_9_8_pos 0
+#define reg_aagc_rf_top_numerator_m_9_8_len 2
+#define reg_aagc_rf_top_numerator_m_9_8_lsb 8
+#define    p_reg_aagc_if_top_numerator_m_7_0    0xF027
+#define reg_aagc_if_top_numerator_m_7_0_pos 0
+#define reg_aagc_if_top_numerator_m_7_0_len 8
+#define reg_aagc_if_top_numerator_m_7_0_lsb 0
+#define    p_reg_aagc_if_top_numerator_m_9_8    0xF028
+#define reg_aagc_if_top_numerator_m_9_8_pos 0
+#define reg_aagc_if_top_numerator_m_9_8_len 2
+#define reg_aagc_if_top_numerator_m_9_8_lsb 8
+#define    p_reg_aagc_adc_out_desired_m_7_0 0xF029
+#define reg_aagc_adc_out_desired_m_7_0_pos 0
+#define reg_aagc_adc_out_desired_m_7_0_len 8
+#define reg_aagc_adc_out_desired_m_7_0_lsb 0
+#define    p_reg_aagc_adc_out_desired_m_8   0xF02A
+#define reg_aagc_adc_out_desired_m_8_pos 0
+#define reg_aagc_adc_out_desired_m_8_len 1
+#define reg_aagc_adc_out_desired_m_8_lsb 8
+#define    p_reg_aagc_mobile_sel    0xF02B
+#define reg_aagc_mobile_sel_pos 0
+#define reg_aagc_mobile_sel_len 1
+#define reg_aagc_mobile_sel_lsb 0
+#define    p_reg_aagc_top_reload    0xF02C
+#define reg_aagc_top_reload_pos 0
+#define reg_aagc_top_reload_len 1
+#define reg_aagc_top_reload_lsb 0
+#define    p_reg_aagc_rf_delta_voltage_en   0xF02D
+#define reg_aagc_rf_delta_voltage_en_pos 0
+#define reg_aagc_rf_delta_voltage_en_len 1
+#define reg_aagc_rf_delta_voltage_en_lsb 0
+#define    p_reg_aagc_rf_voltage_inc    0xF02E
+#define reg_aagc_rf_voltage_inc_pos 0
+#define reg_aagc_rf_voltage_inc_len 1
+#define reg_aagc_rf_voltage_inc_lsb 0
+#define    p_reg_aagc_if_delta_voltage_en   0xF02F
+#define reg_aagc_if_delta_voltage_en_pos 0
+#define reg_aagc_if_delta_voltage_en_len 1
+#define reg_aagc_if_delta_voltage_en_lsb 0
+#define    p_reg_aagc_if_voltage_inc    0xF030
+#define reg_aagc_if_voltage_inc_pos 0
+#define reg_aagc_if_voltage_inc_len 1
+#define reg_aagc_if_voltage_inc_lsb 0
+#define    p_reg_aagc_rf_delta_voltage_7_0  0xF032
+#define reg_aagc_rf_delta_voltage_7_0_pos 0
+#define reg_aagc_rf_delta_voltage_7_0_len 8
+#define reg_aagc_rf_delta_voltage_7_0_lsb 0
+#define    p_reg_aagc_rf_delta_voltage_15_8 0xF033
+#define reg_aagc_rf_delta_voltage_15_8_pos 0
+#define reg_aagc_rf_delta_voltage_15_8_len 8
+#define reg_aagc_rf_delta_voltage_15_8_lsb 8
+#define    p_reg_aagc_rf_delta_voltage_23_16    0xF034
+#define reg_aagc_rf_delta_voltage_23_16_pos 0
+#define reg_aagc_rf_delta_voltage_23_16_len 8
+#define reg_aagc_rf_delta_voltage_23_16_lsb 16
+#define    p_reg_aagc_rf_delta_voltage_29_24    0xF035
+#define reg_aagc_rf_delta_voltage_29_24_pos 0
+#define reg_aagc_rf_delta_voltage_29_24_len 6
+#define reg_aagc_rf_delta_voltage_29_24_lsb 24
+#define    p_reg_aagc_if_delta_voltage_7_0  0xF036
+#define reg_aagc_if_delta_voltage_7_0_pos 0
+#define reg_aagc_if_delta_voltage_7_0_len 8
+#define reg_aagc_if_delta_voltage_7_0_lsb 0
+#define    p_reg_aagc_if_delta_voltage_15_8 0xF037
+#define reg_aagc_if_delta_voltage_15_8_pos 0
+#define reg_aagc_if_delta_voltage_15_8_len 8
+#define reg_aagc_if_delta_voltage_15_8_lsb 8
+#define    p_reg_aagc_if_delta_voltage_23_16    0xF038
+#define reg_aagc_if_delta_voltage_23_16_pos 0
+#define reg_aagc_if_delta_voltage_23_16_len 8
+#define reg_aagc_if_delta_voltage_23_16_lsb 16
+#define    p_reg_aagc_if_delta_voltage_29_24    0xF039
+#define reg_aagc_if_delta_voltage_29_24_pos 0
+#define reg_aagc_if_delta_voltage_29_24_len 6
+#define reg_aagc_if_delta_voltage_29_24_lsb 24
+#define    p_reg_aagc_delta_voltage_hold_time   0xF03A
+#define reg_aagc_delta_voltage_hold_time_pos 0
+#define reg_aagc_delta_voltage_hold_time_len 8
+#define reg_aagc_delta_voltage_hold_time_lsb 0
+#define    p_reg_aagc_top_th_dis    0xF041
+#define reg_aagc_top_th_dis_pos 0
+#define reg_aagc_top_th_dis_len 1
+#define reg_aagc_top_th_dis_lsb 0
+#define    p_reg_p_aagc_rf_floor_dca    0xF042
+#define reg_p_aagc_rf_floor_dca_pos 0
+#define reg_p_aagc_rf_floor_dca_len 8
+#define reg_p_aagc_rf_floor_dca_lsb 0
+#define    p_reg_p_aagc_if_floor_dca    0xF043
+#define reg_p_aagc_if_floor_dca_pos 0
+#define reg_p_aagc_if_floor_dca_len 8
+#define reg_p_aagc_if_floor_dca_lsb 0
+#define    p_reg_p_aagc_rf_gain_scale_dca   0xF044
+#define reg_p_aagc_rf_gain_scale_dca_pos 0
+#define reg_p_aagc_rf_gain_scale_dca_len 3
+#define reg_p_aagc_rf_gain_scale_dca_lsb 0
+#define    p_reg_p_aagc_if_gain_scale_dca   0xF045
+#define reg_p_aagc_if_gain_scale_dca_pos 0
+#define reg_p_aagc_if_gain_scale_dca_len 3
+#define reg_p_aagc_if_gain_scale_dca_lsb 0
+#define    r_reg_r_aagc_ufl_gain    0xF046
+#define reg_r_aagc_ufl_gain_pos 0
+#define reg_r_aagc_ufl_gain_len 8
+#define reg_r_aagc_ufl_gain_lsb 0
+#define    p_reg_aagc_out_rf_inv    0xF047
+#define reg_aagc_out_rf_inv_pos 0
+#define reg_aagc_out_rf_inv_len 1
+#define reg_aagc_out_rf_inv_lsb 0
+#define    p_reg_p_aagc_save_agc_control    0xF048
+#define reg_p_aagc_save_agc_control_pos 0
+#define reg_p_aagc_save_agc_control_len 1
+#define reg_p_aagc_save_agc_control_lsb 0
+#define    p_reg_aagc_fw_sel    0xF049
+#define reg_aagc_fw_sel_pos 0
+#define reg_aagc_fw_sel_len 1
+#define reg_aagc_fw_sel_lsb 0
+#define    r_reg_r_aagc_rf_control_7_0  0xF04A
+#define reg_r_aagc_rf_control_7_0_pos 0
+#define reg_r_aagc_rf_control_7_0_len 8
+#define reg_r_aagc_rf_control_7_0_lsb 0
+#define    r_reg_r_aagc_rf_control_9_8  0xF04B
+#define reg_r_aagc_rf_control_9_8_pos 0
+#define reg_r_aagc_rf_control_9_8_len 2
+#define reg_r_aagc_rf_control_9_8_lsb 8
+#define    r_reg_r_aagc_if_control_7_0  0xF04C
+#define reg_r_aagc_if_control_7_0_pos 0
+#define reg_r_aagc_if_control_7_0_len 8
+#define reg_r_aagc_if_control_7_0_lsb 0
+#define    r_reg_r_aagc_if_control_9_8  0xF04D
+#define reg_r_aagc_if_control_9_8_pos 0
+#define reg_r_aagc_if_control_9_8_len 2
+#define reg_r_aagc_if_control_9_8_lsb 8
+#define    p_reg_aagc_adc_out_desired_from_fw_7_0   0xF04E
+#define reg_aagc_adc_out_desired_from_fw_7_0_pos 0
+#define reg_aagc_adc_out_desired_from_fw_7_0_len 8
+#define reg_aagc_adc_out_desired_from_fw_7_0_lsb 0
+#define    p_reg_aagc_adc_out_desired_from_fw_8 0xF04F
+#define reg_aagc_adc_out_desired_from_fw_8_pos 0
+#define reg_aagc_adc_out_desired_from_fw_8_len 1
+#define reg_aagc_adc_out_desired_from_fw_8_lsb 8
+#define    p_reg_aagc_init_rf_agc_7_0   0xF050
+#define reg_aagc_init_rf_agc_7_0_pos 0
+#define reg_aagc_init_rf_agc_7_0_len 8
+#define reg_aagc_init_rf_agc_7_0_lsb 0
+#define    p_reg_aagc_init_rf_agc_9_8   0xF051
+#define reg_aagc_init_rf_agc_9_8_pos 0
+#define reg_aagc_init_rf_agc_9_8_len 2
+#define reg_aagc_init_rf_agc_9_8_lsb 8
+#define    p_reg_aagc_init_if_agc_7_0   0xF052
+#define reg_aagc_init_if_agc_7_0_pos 0
+#define reg_aagc_init_if_agc_7_0_len 8
+#define reg_aagc_init_if_agc_7_0_lsb 0
+#define    p_reg_aagc_init_if_agc_9_8   0xF053
+#define reg_aagc_init_if_agc_9_8_pos 0
+#define reg_aagc_init_if_agc_9_8_len 2
+#define reg_aagc_init_if_agc_9_8_lsb 8
+#define    p_reg_p_pwm_if_high_unit_num 0xF054
+#define reg_p_pwm_if_high_unit_num_pos 0
+#define reg_p_pwm_if_high_unit_num_len 8
+#define reg_p_pwm_if_high_unit_num_lsb 0
+#define    p_reg_p_pwm_rf_high_unit_num 0xF055
+#define reg_p_pwm_rf_high_unit_num_pos 0
+#define reg_p_pwm_rf_high_unit_num_len 8
+#define reg_p_pwm_rf_high_unit_num_lsb 0
+#define    p_reg_p_pwm_rf_gpio  0xF058
+#define reg_p_pwm_rf_gpio_pos 0
+#define reg_p_pwm_rf_gpio_len 1
+#define reg_p_pwm_rf_gpio_lsb 0
+#define    p_reg_p_pwm_if_gpio  0xF058
+#define reg_p_pwm_if_gpio_pos 1
+#define reg_p_pwm_if_gpio_len 1
+#define reg_p_pwm_if_gpio_lsb 0
+#define    p_reg_aagc_in_sat_cnt_7_0    0xF05A
+#define reg_aagc_in_sat_cnt_7_0_pos 0
+#define reg_aagc_in_sat_cnt_7_0_len 8
+#define reg_aagc_in_sat_cnt_7_0_lsb 0
+#define    p_reg_aagc_in_sat_cnt_15_8   0xF05B
+#define reg_aagc_in_sat_cnt_15_8_pos 0
+#define reg_aagc_in_sat_cnt_15_8_len 8
+#define reg_aagc_in_sat_cnt_15_8_lsb 8
+#define    p_reg_aagc_in_sat_cnt_23_16  0xF05C
+#define reg_aagc_in_sat_cnt_23_16_pos 0
+#define reg_aagc_in_sat_cnt_23_16_len 8
+#define reg_aagc_in_sat_cnt_23_16_lsb 16
+#define    p_reg_aagc_in_sat_cnt_31_24  0xF05D
+#define reg_aagc_in_sat_cnt_31_24_pos 0
+#define reg_aagc_in_sat_cnt_31_24_len 8
+#define reg_aagc_in_sat_cnt_31_24_lsb 24
+#define    p_reg_p_pwm_cycle_unit   0xF05E
+#define reg_p_pwm_cycle_unit_pos 0
+#define reg_p_pwm_cycle_unit_len 4
+#define reg_p_pwm_cycle_unit_lsb 0
+#define    p_reg_p_pwm_en   0xF05F
+#define reg_p_pwm_en_pos 0
+#define reg_p_pwm_en_len 1
+#define reg_p_pwm_en_lsb 0
+#define    r_reg_aagc_rf_gain   0xF060
+#define reg_aagc_rf_gain_pos 0
+#define reg_aagc_rf_gain_len 8
+#define reg_aagc_rf_gain_lsb 0
+#define    r_reg_aagc_if_gain   0xF061
+#define reg_aagc_if_gain_pos 0
+#define reg_aagc_if_gain_len 8
+#define reg_aagc_if_gain_lsb 0
+#define    r_reg_aagc_current_desired_level_7_0 0xF062
+#define reg_aagc_current_desired_level_7_0_pos 0
+#define reg_aagc_current_desired_level_7_0_len 8
+#define reg_aagc_current_desired_level_7_0_lsb 0
+#define    r_reg_aagc_current_desired_level_8   0xF063
+#define reg_aagc_current_desired_level_8_pos 0
+#define reg_aagc_current_desired_level_8_len 1
+#define reg_aagc_current_desired_level_8_lsb 8
+#define    p_reg_tinr_fifo_size 0xF064
+#define reg_tinr_fifo_size_pos 0
+#define reg_tinr_fifo_size_len 5
+#define reg_tinr_fifo_size_lsb 0
+#define    p_reg_tinr_saturation_th_7_0 0xF065
+#define reg_tinr_saturation_th_7_0_pos 0
+#define reg_tinr_saturation_th_7_0_len 8
+#define reg_tinr_saturation_th_7_0_lsb 0
+#define    p_reg_tinr_saturation_th_9_8 0xF066
+#define reg_tinr_saturation_th_9_8_pos 0
+#define reg_tinr_saturation_th_9_8_len 2
+#define reg_tinr_saturation_th_9_8_lsb 8
+#define    p_reg_tinr_saturation_cnt_th 0xF067
+#define reg_tinr_saturation_cnt_th_pos 0
+#define reg_tinr_saturation_cnt_th_len 4
+#define reg_tinr_saturation_cnt_th_lsb 0
+#define    r_reg_tinr_counter_7_0   0xF068
+#define reg_tinr_counter_7_0_pos 0
+#define reg_tinr_counter_7_0_len 8
+#define reg_tinr_counter_7_0_lsb 0
+#define    r_reg_tinr_counter_15_8  0xF069
+#define reg_tinr_counter_15_8_pos 0
+#define reg_tinr_counter_15_8_len 8
+#define reg_tinr_counter_15_8_lsb 8
+#define    p_reg_tinr_counter_rst   0xF06C
+#define reg_tinr_counter_rst_pos 0
+#define reg_tinr_counter_rst_len 1
+#define reg_tinr_counter_rst_lsb 0
+#define    p_reg_tinr_ins_th_7_0    0xF06F
+#define reg_tinr_ins_th_7_0_pos 0
+#define reg_tinr_ins_th_7_0_len 8
+#define reg_tinr_ins_th_7_0_lsb 0
+#define    p_reg_tinr_ins_th_9_8    0xF070
+#define reg_tinr_ins_th_9_8_pos 0
+#define reg_tinr_ins_th_9_8_len 2
+#define reg_tinr_ins_th_9_8_lsb 8
+#define    p_reg_tinr_ins_en    0xF071
+#define reg_tinr_ins_en_pos 0
+#define reg_tinr_ins_en_len 1
+#define reg_tinr_ins_en_lsb 0
+#define    p_reg_tinr_ins_size  0xF072
+#define reg_tinr_ins_size_pos 0
+#define reg_tinr_ins_size_len 4
+#define reg_tinr_ins_size_lsb 0
+#define    p_reg_tinr_ins_hnum  0xF073
+#define reg_tinr_ins_hnum_pos 0
+#define reg_tinr_ins_hnum_len 4
+#define reg_tinr_ins_hnum_lsb 0
+#define    r_reg_tinr_ins_hcnt_7_0  0xF074
+#define reg_tinr_ins_hcnt_7_0_pos 0
+#define reg_tinr_ins_hcnt_7_0_len 8
+#define reg_tinr_ins_hcnt_7_0_lsb 0
+#define    r_reg_tinr_ins_hcnt_15_8 0xF075
+#define reg_tinr_ins_hcnt_15_8_pos 0
+#define reg_tinr_ins_hcnt_15_8_len 8
+#define reg_tinr_ins_hcnt_15_8_lsb 8
+#define    p_reg_tinr_in_conj   0xF076
+#define reg_tinr_in_conj_pos 0
+#define reg_tinr_in_conj_len 1
+#define reg_tinr_in_conj_lsb 0
+#define    p_reg_tinr_in_zero_if    0xF077
+#define reg_tinr_in_zero_if_pos 0
+#define reg_tinr_in_zero_if_len 2
+#define reg_tinr_in_zero_if_lsb 0
+#define    p_reg_tinr_in_shift  0xF078
+#define reg_tinr_in_shift_pos 0
+#define reg_tinr_in_shift_len 1
+#define reg_tinr_in_shift_lsb 0
+#define    p_reg_tinr_in_conj_sat_counter_rst   0xF079
+#define reg_tinr_in_conj_sat_counter_rst_pos 0
+#define reg_tinr_in_conj_sat_counter_rst_len 1
+#define reg_tinr_in_conj_sat_counter_rst_lsb 0
+#define    r_reg_tinr_in_conj_sat_counter_7_0   0xF07A
+#define reg_tinr_in_conj_sat_counter_7_0_pos 0
+#define reg_tinr_in_conj_sat_counter_7_0_len 8
+#define reg_tinr_in_conj_sat_counter_7_0_lsb 0
+#define    r_reg_tinr_in_conj_sat_counter_14_8  0xF07B
+#define reg_tinr_in_conj_sat_counter_14_8_pos 0
+#define reg_tinr_in_conj_sat_counter_14_8_len 7
+#define reg_tinr_in_conj_sat_counter_14_8_lsb 8
+#define    p_reg_p_antif_en 0xF07C
+#define reg_p_antif_en_pos 0
+#define reg_p_antif_en_len 1
+#define reg_p_antif_en_lsb 0
+#define    p_reg_p_antif_rst    0xF07D
+#define reg_p_antif_rst_pos 0
+#define reg_p_antif_rst_len 1
+#define reg_p_antif_rst_lsb 0
+#define    p_reg_p_antif_byp    0xF07E
+#define reg_p_antif_byp_pos 0
+#define reg_p_antif_byp_len 1
+#define reg_p_antif_byp_lsb 0
+#define    p_reg_p_antif_mode   0xF07F
+#define reg_p_antif_mode_pos 0
+#define reg_p_antif_mode_len 1
+#define reg_p_antif_mode_lsb 0
+#define    p_reg_p_ds_byp   0xF080
+#define reg_p_ds_byp_pos 0
+#define reg_p_ds_byp_len 1
+#define reg_p_ds_byp_lsb 0
+#define    p_reg_p_antif_dagc5_mode 0xF081
+#define reg_p_antif_dagc5_mode_pos 0
+#define reg_p_antif_dagc5_mode_len 2
+#define reg_p_antif_dagc5_mode_lsb 0
+#define    p_reg_p_antif_dagc5_desired_level_7_0    0xF082
+#define reg_p_antif_dagc5_desired_level_7_0_pos 0
+#define reg_p_antif_dagc5_desired_level_7_0_len 8
+#define reg_p_antif_dagc5_desired_level_7_0_lsb 0
+#define    p_reg_p_antif_dagc5_desired_level_8  0xF083
+#define reg_p_antif_dagc5_desired_level_8_pos 0
+#define reg_p_antif_dagc5_desired_level_8_len 1
+#define reg_p_antif_dagc5_desired_level_8_lsb 8
+#define    p_reg_p_antif_dagc5_apply_delay  0xF084
+#define reg_p_antif_dagc5_apply_delay_pos 0
+#define reg_p_antif_dagc5_apply_delay_len 7
+#define reg_p_antif_dagc5_apply_delay_lsb 0
+#define    p_reg_p_antif_dagc5_fixed_gain_7_0   0xF085
+#define reg_p_antif_dagc5_fixed_gain_7_0_pos 0
+#define reg_p_antif_dagc5_fixed_gain_7_0_len 8
+#define reg_p_antif_dagc5_fixed_gain_7_0_lsb 0
+#define    p_reg_p_antif_dagc5_fixed_gain_11_8  0xF086
+#define reg_p_antif_dagc5_fixed_gain_11_8_pos 0
+#define reg_p_antif_dagc5_fixed_gain_11_8_len 4
+#define reg_p_antif_dagc5_fixed_gain_11_8_lsb 8
+#define    p_reg_p_antif_dagc5_use_despow   0xF087
+#define reg_p_antif_dagc5_use_despow_pos 0
+#define reg_p_antif_dagc5_use_despow_len 1
+#define reg_p_antif_dagc5_use_despow_lsb 0
+#define    p_reg_p_antif_dagc5_log_2_accumulate_num 0xF088
+#define reg_p_antif_dagc5_log_2_accumulate_num_pos 0
+#define reg_p_antif_dagc5_log_2_accumulate_num_len 5
+#define reg_p_antif_dagc5_log_2_accumulate_num_lsb 0
+#define    p_reg_p_antif_dagc5_in_sat_cnt_7_0   0xF089
+#define reg_p_antif_dagc5_in_sat_cnt_7_0_pos 0
+#define reg_p_antif_dagc5_in_sat_cnt_7_0_len 8
+#define reg_p_antif_dagc5_in_sat_cnt_7_0_lsb 0
+#define    p_reg_p_antif_dagc5_in_sat_cnt_15_8  0xF08A
+#define reg_p_antif_dagc5_in_sat_cnt_15_8_pos 0
+#define reg_p_antif_dagc5_in_sat_cnt_15_8_len 8
+#define reg_p_antif_dagc5_in_sat_cnt_15_8_lsb 8
+#define    p_reg_p_antif_dagc5_in_sat_cnt_23_16 0xF08B
+#define reg_p_antif_dagc5_in_sat_cnt_23_16_pos 0
+#define reg_p_antif_dagc5_in_sat_cnt_23_16_len 8
+#define reg_p_antif_dagc5_in_sat_cnt_23_16_lsb 16
+#define    p_reg_p_antif_dagc5_in_sat_cnt_31_24 0xF08C
+#define reg_p_antif_dagc5_in_sat_cnt_31_24_pos 0
+#define reg_p_antif_dagc5_in_sat_cnt_31_24_len 8
+#define reg_p_antif_dagc5_in_sat_cnt_31_24_lsb 24
+#define    p_reg_p_antif_dagc5_out_sat_cnt_7_0  0xF08D
+#define reg_p_antif_dagc5_out_sat_cnt_7_0_pos 0
+#define reg_p_antif_dagc5_out_sat_cnt_7_0_len 8
+#define reg_p_antif_dagc5_out_sat_cnt_7_0_lsb 0
+#define    p_reg_p_antif_dagc5_out_sat_cnt_15_8 0xF08E
+#define reg_p_antif_dagc5_out_sat_cnt_15_8_pos 0
+#define reg_p_antif_dagc5_out_sat_cnt_15_8_len 8
+#define reg_p_antif_dagc5_out_sat_cnt_15_8_lsb 8
+#define    p_reg_p_antif_dagc5_out_sat_cnt_23_16    0xF08F
+#define reg_p_antif_dagc5_out_sat_cnt_23_16_pos 0
+#define reg_p_antif_dagc5_out_sat_cnt_23_16_len 8
+#define reg_p_antif_dagc5_out_sat_cnt_23_16_lsb 16
+#define    p_reg_p_antif_dagc5_out_sat_cnt_31_24    0xF090
+#define reg_p_antif_dagc5_out_sat_cnt_31_24_pos 0
+#define reg_p_antif_dagc5_out_sat_cnt_31_24_len 8
+#define reg_p_antif_dagc5_out_sat_cnt_31_24_lsb 24
+#define    p_reg_p_antif_dagc5_rst  0xF091
+#define reg_p_antif_dagc5_rst_pos 0
+#define reg_p_antif_dagc5_rst_len 1
+#define reg_p_antif_dagc5_rst_lsb 0
+#define    p_reg_p_antif_dagc5_en   0xF092
+#define reg_p_antif_dagc5_en_pos 0
+#define reg_p_antif_dagc5_en_len 1
+#define reg_p_antif_dagc5_en_lsb 0
+#define    p_reg_p_antif_sc_mode    0xF093
+#define reg_p_antif_sc_mode_pos 0
+#define reg_p_antif_sc_mode_len 4
+#define reg_p_antif_sc_mode_lsb 0
+#define    p_reg_p_antif_dagc5_done 0xF094
+#define reg_p_antif_dagc5_done_pos 0
+#define reg_p_antif_dagc5_done_len 1
+#define reg_p_antif_dagc5_done_lsb 0
+#define    r_reg_r_antif_sc_7_0 0xF095
+#define reg_r_antif_sc_7_0_pos 0
+#define reg_r_antif_sc_7_0_len 8
+#define reg_r_antif_sc_7_0_lsb 0
+#define    r_reg_r_antif_sc_15_8    0xF096
+#define reg_r_antif_sc_15_8_pos 0
+#define reg_r_antif_sc_15_8_len 8
+#define reg_r_antif_sc_15_8_lsb 8
+#define    r_reg_r_antif_dagc5_multiplier_7_0   0xF097
+#define reg_r_antif_dagc5_multiplier_7_0_pos 0
+#define reg_r_antif_dagc5_multiplier_7_0_len 8
+#define reg_r_antif_dagc5_multiplier_7_0_lsb 0
+#define    r_reg_r_antif_dagc5_multiplier_15_8  0xF098
+#define reg_r_antif_dagc5_multiplier_15_8_pos 0
+#define reg_r_antif_dagc5_multiplier_15_8_len 8
+#define reg_r_antif_dagc5_multiplier_15_8_lsb 8
+#define    r_reg_r_antif_dagc5_right_shift_bits 0xF099
+#define reg_r_antif_dagc5_right_shift_bits_pos 0
+#define reg_r_antif_dagc5_right_shift_bits_len 4
+#define reg_r_antif_dagc5_right_shift_bits_lsb 0
+#define    p_reg_p_antif_dagc5_bypass_scale_ctl 0xF09A
+#define reg_p_antif_dagc5_bypass_scale_ctl_pos 0
+#define reg_p_antif_dagc5_bypass_scale_ctl_len 3
+#define reg_p_antif_dagc5_bypass_scale_ctl_lsb 0
+#define    p_reg_mccid_ccirunno_7_0 0xF09B
+#define reg_mccid_ccirunno_7_0_pos 0
+#define reg_mccid_ccirunno_7_0_len 8
+#define reg_mccid_ccirunno_7_0_lsb 0
+#define    p_reg_mccid_ccirunno_8   0xF09C
+#define reg_mccid_ccirunno_8_pos 0
+#define reg_mccid_ccirunno_8_len 1
+#define reg_mccid_ccirunno_8_lsb 8
+#define    p_reg_mccid_acirunno_7_0 0xF09D
+#define reg_mccid_acirunno_7_0_pos 0
+#define reg_mccid_acirunno_7_0_len 8
+#define reg_mccid_acirunno_7_0_lsb 0
+#define    p_reg_mccid_acirunno_8   0xF09E
+#define reg_mccid_acirunno_8_pos 0
+#define reg_mccid_acirunno_8_len 1
+#define reg_mccid_acirunno_8_lsb 8
+#define    p_reg_mccid_maxtonenearrange_7_0 0xF09F
+#define reg_mccid_maxtonenearrange_7_0_pos 0
+#define reg_mccid_maxtonenearrange_7_0_len 8
+#define reg_mccid_maxtonenearrange_7_0_lsb 0
+#define    p_reg_mccid_maxtonenearrange_8   0xF0A0
+#define reg_mccid_maxtonenearrange_8_pos 0
+#define reg_mccid_maxtonenearrange_8_len 1
+#define reg_mccid_maxtonenearrange_8_lsb 8
+#define    r_reg_mccid_maxacipower_7_0  0xF0A1
+#define reg_mccid_maxacipower_7_0_pos 0
+#define reg_mccid_maxacipower_7_0_len 8
+#define reg_mccid_maxacipower_7_0_lsb 0
+#define    r_reg_mccid_maxacipower_15_8 0xF0A2
+#define reg_mccid_maxacipower_15_8_pos 0
+#define reg_mccid_maxacipower_15_8_len 8
+#define reg_mccid_maxacipower_15_8_lsb 8
+#define    r_reg_mccid_maxacipower_19_16    0xF0A3
+#define reg_mccid_maxacipower_19_16_pos 0
+#define reg_mccid_maxacipower_19_16_len 4
+#define reg_mccid_maxacipower_19_16_lsb 16
+#define    p_reg_p_dcoe_en  0xF0D5
+#define reg_p_dcoe_en_pos 0
+#define reg_p_dcoe_en_len 1
+#define reg_p_dcoe_en_lsb 0
+#define    p_reg_p_dcoe_rst 0xF0D6
+#define reg_p_dcoe_rst_pos 0
+#define reg_p_dcoe_rst_len 1
+#define reg_p_dcoe_rst_lsb 0
+#define    p_reg_p_dcoe_clear   0xF0D7
+#define reg_p_dcoe_clear_pos 0
+#define reg_p_dcoe_clear_len 1
+#define reg_p_dcoe_clear_lsb 0
+#define    p_reg_p_dcoe_applyloc_7_0    0xF0D8
+#define reg_p_dcoe_applyloc_7_0_pos 0
+#define reg_p_dcoe_applyloc_7_0_len 8
+#define reg_p_dcoe_applyloc_7_0_lsb 0
+#define    p_reg_p_dcoe_applyloc_12_8   0xF0D9
+#define reg_p_dcoe_applyloc_12_8_pos 0
+#define reg_p_dcoe_applyloc_12_8_len 5
+#define reg_p_dcoe_applyloc_12_8_lsb 8
+#define    p_reg_p_dcoe_accnums 0xF0DA
+#define reg_p_dcoe_accnums_pos 0
+#define reg_p_dcoe_accnums_len 3
+#define reg_p_dcoe_accnums_lsb 0
+#define    p_reg_p_dcoe_accweightsum_sh 0xF0DB
+#define reg_p_dcoe_accweightsum_sh_pos 0
+#define reg_p_dcoe_accweightsum_sh_len 3
+#define reg_p_dcoe_accweightsum_sh_lsb 0
+#define    p_reg_p_dcoe_accweightcurr   0xF0DC
+#define reg_p_dcoe_accweightcurr_pos 0
+#define reg_p_dcoe_accweightcurr_len 8
+#define reg_p_dcoe_accweightcurr_lsb 0
+#define    p_reg_dcoe_apply_rd  0xF0DF
+#define reg_dcoe_apply_rd_pos 0
+#define reg_dcoe_apply_rd_len 1
+#define reg_dcoe_apply_rd_lsb 0
+#define    r_reg_dcoe_apply_i   0xF0E0
+#define reg_dcoe_apply_i_pos 0
+#define reg_dcoe_apply_i_len 8
+#define reg_dcoe_apply_i_lsb 0
+#define    r_reg_dcoe_apply_q   0xF0E1
+#define reg_dcoe_apply_q_pos 0
+#define reg_dcoe_apply_q_len 8
+#define reg_dcoe_apply_q_lsb 0
+#define    p_reg_p_dcrm_en  0xF0E2
+#define reg_p_dcrm_en_pos 0
+#define reg_p_dcrm_en_len 1
+#define reg_p_dcrm_en_lsb 0
+#define    p_reg_p_dcrm_fir 0xF0E3
+#define reg_p_dcrm_fir_pos 0
+#define reg_p_dcrm_fir_len 1
+#define reg_p_dcrm_fir_lsb 0
+#define    p_reg_p_dcrm_log2_firlen 0xF0E4
+#define reg_p_dcrm_log2_firlen_pos 0
+#define reg_p_dcrm_log2_firlen_len 3
+#define reg_p_dcrm_log2_firlen_lsb 0
+#define    r_reg_dcoe_apply_fir_i   0xF0E5
+#define reg_dcoe_apply_fir_i_pos 0
+#define reg_dcoe_apply_fir_i_len 8
+#define reg_dcoe_apply_fir_i_lsb 0
+#define    r_reg_dcoe_apply_fir_q   0xF0E6
+#define reg_dcoe_apply_fir_q_pos 0
+#define reg_dcoe_apply_fir_q_len 8
+#define reg_dcoe_apply_fir_q_lsb 0
+#define    p_reg_p_dcrm_force_en    0xF0E7
+#define reg_p_dcrm_force_en_pos 0
+#define reg_p_dcrm_force_en_len 1
+#define reg_p_dcrm_force_en_lsb 0
+#define    p_reg_p_dcrm_force_value_i   0xF0E8
+#define reg_p_dcrm_force_value_i_pos 0
+#define reg_p_dcrm_force_value_i_len 8
+#define reg_p_dcrm_force_value_i_lsb 0
+#define    p_reg_p_dcrm_force_value_q   0xF0E9
+#define reg_p_dcrm_force_value_q_pos 0
+#define reg_p_dcrm_force_value_q_len 8
+#define reg_p_dcrm_force_value_q_lsb 0
+#define    p_reg_p_iqip_en  0xF0EA
+#define reg_p_iqip_en_pos 0
+#define reg_p_iqip_en_len 1
+#define reg_p_iqip_en_lsb 0
+#define    p_reg_p_iqip_rst 0xF0EB
+#define reg_p_iqip_rst_pos 0
+#define reg_p_iqip_rst_len 1
+#define reg_p_iqip_rst_lsb 0
+#define    p_reg_iqip_mu_ld 0xF0EC
+#define reg_iqip_mu_ld_pos 0
+#define reg_iqip_mu_ld_len 1
+#define reg_iqip_mu_ld_lsb 0
+#define    p_reg_p_iqip_mu_7_0  0xF0ED
+#define reg_p_iqip_mu_7_0_pos 0
+#define reg_p_iqip_mu_7_0_len 8
+#define reg_p_iqip_mu_7_0_lsb 0
+#define    p_reg_p_iqip_mu_11_8 0xF0EE
+#define reg_p_iqip_mu_11_8_pos 0
+#define reg_p_iqip_mu_11_8_len 4
+#define reg_p_iqip_mu_11_8_lsb 8
+#define    p_reg_iqip_gs_ld 0xF0EF
+#define reg_iqip_gs_ld_pos 0
+#define reg_iqip_gs_ld_len 1
+#define reg_iqip_gs_ld_lsb 0
+#define    p_reg_p_iqip_gsnums  0xF0F0
+#define reg_p_iqip_gsnums_pos 0
+#define reg_p_iqip_gsnums_len 4
+#define reg_p_iqip_gsnums_lsb 0
+#define    p_reg_p_iqip_gsites_7_0  0xF0F1
+#define reg_p_iqip_gsites_7_0_pos 0
+#define reg_p_iqip_gsites_7_0_len 8
+#define reg_p_iqip_gsites_7_0_lsb 0
+#define    p_reg_p_iqip_gsites_15_8 0xF0F2
+#define reg_p_iqip_gsites_15_8_pos 0
+#define reg_p_iqip_gsites_15_8_len 8
+#define reg_p_iqip_gsites_15_8_lsb 8
+#define    p_reg_iqip_w_ld  0xF0F3
+#define reg_iqip_w_ld_pos 0
+#define reg_iqip_w_ld_len 1
+#define reg_iqip_w_ld_lsb 0
+#define    p_reg_p_iqip_w_re_7_0    0xF0F4
+#define reg_p_iqip_w_re_7_0_pos 0
+#define reg_p_iqip_w_re_7_0_len 8
+#define reg_p_iqip_w_re_7_0_lsb 0
+#define    p_reg_p_iqip_w_re_15_8   0xF0F5
+#define reg_p_iqip_w_re_15_8_pos 0
+#define reg_p_iqip_w_re_15_8_len 8
+#define reg_p_iqip_w_re_15_8_lsb 8
+#define    p_reg_p_iqip_w_re_16 0xF0F6
+#define reg_p_iqip_w_re_16_pos 0
+#define reg_p_iqip_w_re_16_len 1
+#define reg_p_iqip_w_re_16_lsb 16
+#define    p_reg_p_iqip_w_im_7_0    0xF0F7
+#define reg_p_iqip_w_im_7_0_pos 0
+#define reg_p_iqip_w_im_7_0_len 8
+#define reg_p_iqip_w_im_7_0_lsb 0
+#define    p_reg_p_iqip_w_im_15_8   0xF0F8
+#define reg_p_iqip_w_im_15_8_pos 0
+#define reg_p_iqip_w_im_15_8_len 8
+#define reg_p_iqip_w_im_15_8_lsb 8
+#define    p_reg_p_iqip_w_im_16 0xF0F9
+#define reg_p_iqip_w_im_16_pos 0
+#define reg_p_iqip_w_im_16_len 1
+#define reg_p_iqip_w_im_16_lsb 16
+#define    p_reg_iqip_accnums_rd    0xF0FA
+#define reg_iqip_accnums_rd_pos 0
+#define reg_iqip_accnums_rd_len 1
+#define reg_iqip_accnums_rd_lsb 0
+#define    p_reg_p_iqip_accnums 0xF0FB
+#define reg_p_iqip_accnums_pos 0
+#define reg_p_iqip_accnums_len 2
+#define reg_p_iqip_accnums_lsb 0
+#define    p_reg_iqip_accnums_rdy   0xF0FC
+#define reg_iqip_accnums_rdy_pos 0
+#define reg_iqip_accnums_rdy_len 1
+#define reg_iqip_accnums_rdy_lsb 0
+#define    r_reg_r_iqip_wacc_re_7_0 0xF0FD
+#define reg_r_iqip_wacc_re_7_0_pos 0
+#define reg_r_iqip_wacc_re_7_0_len 8
+#define reg_r_iqip_wacc_re_7_0_lsb 0
+#define    r_reg_r_iqip_wacc_re_15_8    0xF0FE
+#define reg_r_iqip_wacc_re_15_8_pos 0
+#define reg_r_iqip_wacc_re_15_8_len 8
+#define reg_r_iqip_wacc_re_15_8_lsb 8
+#define    r_reg_r_iqip_wacc_re_16  0xF0FF
+#define reg_r_iqip_wacc_re_16_pos 0
+#define reg_r_iqip_wacc_re_16_len 1
+#define reg_r_iqip_wacc_re_16_lsb 16
+#define    r_reg_r_iqip_wacc_im_7_0 0xF100
+#define reg_r_iqip_wacc_im_7_0_pos 0
+#define reg_r_iqip_wacc_im_7_0_len 8
+#define reg_r_iqip_wacc_im_7_0_lsb 0
+#define    r_reg_r_iqip_wacc_im_15_8    0xF101
+#define reg_r_iqip_wacc_im_15_8_pos 0
+#define reg_r_iqip_wacc_im_15_8_len 8
+#define reg_r_iqip_wacc_im_15_8_lsb 8
+#define    r_reg_r_iqip_wacc_im_16  0xF102
+#define reg_r_iqip_wacc_im_16_pos 0
+#define reg_r_iqip_wacc_im_16_len 1
+#define reg_r_iqip_wacc_im_16_lsb 16
+#define    r_reg_r_iqip_out2cacc_re_7_0 0xF103
+#define reg_r_iqip_out2cacc_re_7_0_pos 0
+#define reg_r_iqip_out2cacc_re_7_0_len 8
+#define reg_r_iqip_out2cacc_re_7_0_lsb 0
+#define    r_reg_r_iqip_out2cacc_re_15_8    0xF104
+#define reg_r_iqip_out2cacc_re_15_8_pos 0
+#define reg_r_iqip_out2cacc_re_15_8_len 8
+#define reg_r_iqip_out2cacc_re_15_8_lsb 8
+#define    r_reg_r_iqip_out2cacc_re_21_16   0xF105
+#define reg_r_iqip_out2cacc_re_21_16_pos 0
+#define reg_r_iqip_out2cacc_re_21_16_len 6
+#define reg_r_iqip_out2cacc_re_21_16_lsb 16
+#define    r_reg_r_iqip_out2cacc_im_7_0 0xF106
+#define reg_r_iqip_out2cacc_im_7_0_pos 0
+#define reg_r_iqip_out2cacc_im_7_0_len 8
+#define reg_r_iqip_out2cacc_im_7_0_lsb 0
+#define    r_reg_r_iqip_out2cacc_im_15_8    0xF107
+#define reg_r_iqip_out2cacc_im_15_8_pos 0
+#define reg_r_iqip_out2cacc_im_15_8_len 8
+#define reg_r_iqip_out2cacc_im_15_8_lsb 8
+#define    r_reg_r_iqip_out2cacc_im_21_16   0xF108
+#define reg_r_iqip_out2cacc_im_21_16_pos 0
+#define reg_r_iqip_out2cacc_im_21_16_len 6
+#define reg_r_iqip_out2cacc_im_21_16_lsb 16
+#define    p_reg_mccid_ccif0_scstrobe   0xF109
+#define reg_mccid_ccif0_scstrobe_pos 0
+#define reg_mccid_ccif0_scstrobe_len 7
+#define reg_mccid_ccif0_scstrobe_lsb 0
+#define    p_reg_mccid_cciftrigger  0xF10A
+#define reg_mccid_cciftrigger_pos 0
+#define reg_mccid_cciftrigger_len 1
+#define reg_mccid_cciftrigger_lsb 0
+#define    p_reg_mccid_ccif1_scstrobe   0xF10B
+#define reg_mccid_ccif1_scstrobe_pos 0
+#define reg_mccid_ccif1_scstrobe_len 7
+#define reg_mccid_ccif1_scstrobe_lsb 0
+#define    p_reg_mccid_ccif0_fcwccif_7_0    0xF10E
+#define reg_mccid_ccif0_fcwccif_7_0_pos 0
+#define reg_mccid_ccif0_fcwccif_7_0_len 8
+#define reg_mccid_ccif0_fcwccif_7_0_lsb 0
+#define    p_reg_mccid_ccif0_fcwccif_13_8   0xF10F
+#define reg_mccid_ccif0_fcwccif_13_8_pos 0
+#define reg_mccid_ccif0_fcwccif_13_8_len 6
+#define reg_mccid_ccif0_fcwccif_13_8_lsb 8
+#define    p_reg_mccid_ccif0_state  0xF110
+#define reg_mccid_ccif0_state_pos 0
+#define reg_mccid_ccif0_state_len 1
+#define reg_mccid_ccif0_state_lsb 0
+#define    p_reg_mccid_ccif0_acistate   0xF111
+#define reg_mccid_ccif0_acistate_pos 0
+#define reg_mccid_ccif0_acistate_len 1
+#define reg_mccid_ccif0_acistate_lsb 0
+#define    p_reg_mccid_ccif1_fcwccif_7_0    0xF112
+#define reg_mccid_ccif1_fcwccif_7_0_pos 0
+#define reg_mccid_ccif1_fcwccif_7_0_len 8
+#define reg_mccid_ccif1_fcwccif_7_0_lsb 0
+#define    p_reg_mccid_ccif1_fcwccif_13_8   0xF113
+#define reg_mccid_ccif1_fcwccif_13_8_pos 0
+#define reg_mccid_ccif1_fcwccif_13_8_len 6
+#define reg_mccid_ccif1_fcwccif_13_8_lsb 8
+#define    p_reg_mccid_ccif1_state  0xF114
+#define reg_mccid_ccif1_state_pos 0
+#define reg_mccid_ccif1_state_len 1
+#define reg_mccid_ccif1_state_lsb 0
+#define    p_reg_mccid_ccif1_acistate   0xF115
+#define reg_mccid_ccif1_acistate_pos 0
+#define reg_mccid_ccif1_acistate_len 1
+#define reg_mccid_ccif1_acistate_lsb 0
+#define    r_reg_r_acif_saturate    0xF117
+#define reg_r_acif_saturate_pos 0
+#define reg_r_acif_saturate_len 8
+#define reg_r_acif_saturate_lsb 0
+#define    p_reg_tmr_timer0_threshold_7_0   0xF118
+#define reg_tmr_timer0_threshold_7_0_pos 0
+#define reg_tmr_timer0_threshold_7_0_len 8
+#define reg_tmr_timer0_threshold_7_0_lsb 0
+#define    p_reg_tmr_timer0_threshold_15_8  0xF119
+#define reg_tmr_timer0_threshold_15_8_pos 0
+#define reg_tmr_timer0_threshold_15_8_len 8
+#define reg_tmr_timer0_threshold_15_8_lsb 8
+#define    p_reg_tmr_timer0_enable  0xF11A
+#define reg_tmr_timer0_enable_pos 0
+#define reg_tmr_timer0_enable_len 1
+#define reg_tmr_timer0_enable_lsb 0
+#define    p_reg_tmr_timer0_clk_sel 0xF11B
+#define reg_tmr_timer0_clk_sel_pos 0
+#define reg_tmr_timer0_clk_sel_len 1
+#define reg_tmr_timer0_clk_sel_lsb 0
+#define    p_reg_tmr_timer0_int 0xF11C
+#define reg_tmr_timer0_int_pos 0
+#define reg_tmr_timer0_int_len 1
+#define reg_tmr_timer0_int_lsb 0
+#define    p_reg_tmr_timer0_rst 0xF11D
+#define reg_tmr_timer0_rst_pos 0
+#define reg_tmr_timer0_rst_len 1
+#define reg_tmr_timer0_rst_lsb 0
+#define    r_reg_tmr_timer0_count_7_0   0xF11E
+#define reg_tmr_timer0_count_7_0_pos 0
+#define reg_tmr_timer0_count_7_0_len 8
+#define reg_tmr_timer0_count_7_0_lsb 0
+#define    r_reg_tmr_timer0_count_15_8  0xF11F
+#define reg_tmr_timer0_count_15_8_pos 0
+#define reg_tmr_timer0_count_15_8_len 8
+#define reg_tmr_timer0_count_15_8_lsb 8
+#define    p_reg_suspend    0xF120
+#define reg_suspend_pos 0
+#define reg_suspend_len 1
+#define reg_suspend_lsb 0
+#define    p_reg_suspend_rdy    0xF121
+#define reg_suspend_rdy_pos 0
+#define reg_suspend_rdy_len 1
+#define reg_suspend_rdy_lsb 0
+#define    p_reg_resume 0xF122
+#define reg_resume_pos 0
+#define reg_resume_len 1
+#define reg_resume_lsb 0
+#define    p_reg_resume_rdy 0xF123
+#define reg_resume_rdy_pos 0
+#define reg_resume_rdy_len 1
+#define reg_resume_rdy_lsb 0
+#define    p_reg_gp_trigger 0xF124
+#define reg_gp_trigger_pos 0
+#define reg_gp_trigger_len 1
+#define reg_gp_trigger_lsb 0
+#define    p_reg_trigger_sel    0xF125
+#define reg_trigger_sel_pos 0
+#define reg_trigger_sel_len 2
+#define reg_trigger_sel_lsb 0
+#define    p_reg_debug_ofdm 0xF126
+#define reg_debug_ofdm_pos 0
+#define reg_debug_ofdm_len 2
+#define reg_debug_ofdm_lsb 0
+#define    p_reg_trigger_module_sel 0xF127
+#define reg_trigger_module_sel_pos 0
+#define reg_trigger_module_sel_len 6
+#define reg_trigger_module_sel_lsb 0
+#define    p_reg_trigger_set_sel    0xF128
+#define reg_trigger_set_sel_pos 0
+#define reg_trigger_set_sel_len 6
+#define reg_trigger_set_sel_lsb 0
+#define    p_reg_fw_int_mask_n  0xF129
+#define reg_fw_int_mask_n_pos 0
+#define reg_fw_int_mask_n_len 1
+#define reg_fw_int_mask_n_lsb 0
+#define    p_reg_dioif_rst  0xF12A
+#define reg_dioif_rst_pos 0
+#define reg_dioif_rst_len 1
+#define reg_dioif_rst_lsb 0
+#define    p_reg_debug_group    0xF12B
+#define reg_debug_group_pos 0
+#define reg_debug_group_len 4
+#define reg_debug_group_lsb 0
+#define    p_reg_odbg_clk_sel   0xF12C
+#define reg_odbg_clk_sel_pos 0
+#define reg_odbg_clk_sel_len 3
+#define reg_odbg_clk_sel_lsb 0
+#define    p_reg_p_ccif_shift_fre   0xF12F
+#define reg_p_ccif_shift_fre_pos 0
+#define reg_p_ccif_shift_fre_len 1
+#define reg_p_ccif_shift_fre_lsb 0
+#define    p_reg_p_ccif_bandwidth_factor    0xF130
+#define reg_p_ccif_bandwidth_factor_pos 0
+#define reg_p_ccif_bandwidth_factor_len 3
+#define reg_p_ccif_bandwidth_factor_lsb 0
+#define    p_reg_ccif_rst   0xF131
+#define reg_ccif_rst_pos 0
+#define reg_ccif_rst_len 1
+#define reg_ccif_rst_lsb 0
+#define    p_reg_p_ccif_min_bandwidth   0xF132
+#define reg_p_ccif_min_bandwidth_pos 0
+#define reg_p_ccif_min_bandwidth_len 7
+#define reg_p_ccif_min_bandwidth_lsb 0
+#define    p_reg_ccif_bq0_state 0xF133
+#define reg_ccif_bq0_state_pos 0
+#define reg_ccif_bq0_state_len 1
+#define reg_ccif_bq0_state_lsb 0
+#define    p_reg_ccif_bq0_outputscaling 0xF134
+#define reg_ccif_bq0_outputscaling_pos 0
+#define reg_ccif_bq0_outputscaling_len 5
+#define reg_ccif_bq0_outputscaling_lsb 0
+#define    p_reg_ccif_bq1_state 0xF135
+#define reg_ccif_bq1_state_pos 0
+#define reg_ccif_bq1_state_len 1
+#define reg_ccif_bq1_state_lsb 0
+#define    p_reg_ccif_bq1_outputscaling 0xF136
+#define reg_ccif_bq1_outputscaling_pos 0
+#define reg_ccif_bq1_outputscaling_len 5
+#define reg_ccif_bq1_outputscaling_lsb 0
+#define    p_reg_ccif_bq0_a1_7_0    0xF137
+#define reg_ccif_bq0_a1_7_0_pos 0
+#define reg_ccif_bq0_a1_7_0_len 8
+#define reg_ccif_bq0_a1_7_0_lsb 0
+#define    p_reg_ccif_bq0_a1_13_8   0xF138
+#define reg_ccif_bq0_a1_13_8_pos 0
+#define reg_ccif_bq0_a1_13_8_len 6
+#define reg_ccif_bq0_a1_13_8_lsb 8
+#define    p_reg_ccif_bq1_a1_7_0    0xF139
+#define reg_ccif_bq1_a1_7_0_pos 0
+#define reg_ccif_bq1_a1_7_0_len 8
+#define reg_ccif_bq1_a1_7_0_lsb 0
+#define    p_reg_ccif_bq1_a1_13_8   0xF13A
+#define reg_ccif_bq1_a1_13_8_pos 0
+#define reg_ccif_bq1_a1_13_8_len 6
+#define reg_ccif_bq1_a1_13_8_lsb 8
+#define    p_reg_ccif_bq0_b1_7_0    0xF13B
+#define reg_ccif_bq0_b1_7_0_pos 0
+#define reg_ccif_bq0_b1_7_0_len 8
+#define reg_ccif_bq0_b1_7_0_lsb 0
+#define    p_reg_ccif_bq0_b1_13_8   0xF13C
+#define reg_ccif_bq0_b1_13_8_pos 0
+#define reg_ccif_bq0_b1_13_8_len 6
+#define reg_ccif_bq0_b1_13_8_lsb 8
+#define    p_reg_ccif_bq1_b1_7_0    0xF13D
+#define reg_ccif_bq1_b1_7_0_pos 0
+#define reg_ccif_bq1_b1_7_0_len 8
+#define reg_ccif_bq1_b1_7_0_lsb 0
+#define    p_reg_ccif_bq1_b1_13_8   0xF13E
+#define reg_ccif_bq1_b1_13_8_pos 0
+#define reg_ccif_bq1_b1_13_8_len 6
+#define reg_ccif_bq1_b1_13_8_lsb 8
+#define    p_reg_ccif_bq0_b2_7_0    0xF13F
+#define reg_ccif_bq0_b2_7_0_pos 0
+#define reg_ccif_bq0_b2_7_0_len 8
+#define reg_ccif_bq0_b2_7_0_lsb 0
+#define    p_reg_ccif_bq0_b2_13_8   0xF140
+#define reg_ccif_bq0_b2_13_8_pos 0
+#define reg_ccif_bq0_b2_13_8_len 6
+#define reg_ccif_bq0_b2_13_8_lsb 8
+#define    p_reg_ccif_bq1_b2_7_0    0xF141
+#define reg_ccif_bq1_b2_7_0_pos 0
+#define reg_ccif_bq1_b2_7_0_len 8
+#define reg_ccif_bq1_b2_7_0_lsb 0
+#define    p_reg_ccif_bq1_b2_13_8   0xF142
+#define reg_ccif_bq1_b2_13_8_pos 0
+#define reg_ccif_bq1_b2_13_8_len 6
+#define reg_ccif_bq1_b2_13_8_lsb 8
+#define    p_reg_ccif_debug_rst 0xF143
+#define reg_ccif_debug_rst_pos 0
+#define reg_ccif_debug_rst_len 1
+#define reg_ccif_debug_rst_lsb 0
+#define    p_reg_mccid_defaultccifscstrobe  0xF144
+#define reg_mccid_defaultccifscstrobe_pos 0
+#define reg_mccid_defaultccifscstrobe_len 7
+#define reg_mccid_defaultccifscstrobe_lsb 0
+#define    p_reg_mccid_monitoringaci    0xF145
+#define reg_mccid_monitoringaci_pos 0
+#define reg_mccid_monitoringaci_len 1
+#define reg_mccid_monitoringaci_lsb 0
+#define    p_reg_mccid_ispassmode   0xF146
+#define reg_mccid_ispassmode_pos 0
+#define reg_mccid_ispassmode_len 1
+#define reg_mccid_ispassmode_lsb 0
+#define    p_reg_mccid_issteadystatemode    0xF147
+#define reg_mccid_issteadystatemode_pos 0
+#define reg_mccid_issteadystatemode_len 1
+#define reg_mccid_issteadystatemode_lsb 0
+#define    p_reg_mccid_fixedgaincmp 0xF148
+#define reg_mccid_fixedgaincmp_pos 0
+#define reg_mccid_fixedgaincmp_len 1
+#define reg_mccid_fixedgaincmp_lsb 0
+#define    p_reg_mccid_misscounter_reset    0xF149
+#define reg_mccid_misscounter_reset_pos 0
+#define reg_mccid_misscounter_reset_len 1
+#define reg_mccid_misscounter_reset_lsb 0
+#define    p_reg_mccid_acwgcheckcciexist    0xF14A
+#define reg_mccid_acwgcheckcciexist_pos 0
+#define reg_mccid_acwgcheckcciexist_len 1
+#define reg_mccid_acwgcheckcciexist_lsb 0
+#define    p_reg_mccid_acidone  0xF14B
+#define reg_mccid_acidone_pos 0
+#define reg_mccid_acidone_len 1
+#define reg_mccid_acidone_lsb 0
+#define    p_reg_mccid_sxdesiredpower_7_0   0xF14C
+#define reg_mccid_sxdesiredpower_7_0_pos 0
+#define reg_mccid_sxdesiredpower_7_0_len 8
+#define reg_mccid_sxdesiredpower_7_0_lsb 0
+#define    p_reg_mccid_sxdesiredpower_9_8   0xF14D
+#define reg_mccid_sxdesiredpower_9_8_pos 0
+#define reg_mccid_sxdesiredpower_9_8_len 2
+#define reg_mccid_sxdesiredpower_9_8_lsb 8
+#define    p_reg_mccid_defaultccitimertriggerno 0xF14E
+#define reg_mccid_defaultccitimertriggerno_pos 0
+#define reg_mccid_defaultccitimertriggerno_len 8
+#define reg_mccid_defaultccitimertriggerno_lsb 0
+#define    p_reg_mccid_detectedmaxtonecountshift    0xF14F
+#define reg_mccid_detectedmaxtonecountshift_pos 0
+#define reg_mccid_detectedmaxtonecountshift_len 3
+#define reg_mccid_detectedmaxtonecountshift_lsb 0
+#define    p_reg_mccid_moveffttoccif_en 0xF151
+#define reg_mccid_moveffttoccif_en_pos 0
+#define reg_mccid_moveffttoccif_en_len 1
+#define reg_mccid_moveffttoccif_en_lsb 0
+#define    p_reg_mccid_fftindextobfsfcwfactor_7_0   0xF152
+#define reg_mccid_fftindextobfsfcwfactor_7_0_pos 0
+#define reg_mccid_fftindextobfsfcwfactor_7_0_len 8
+#define reg_mccid_fftindextobfsfcwfactor_7_0_lsb 0
+#define    p_reg_mccid_fftindextobfsfcwfactor_9_8   0xF153
+#define reg_mccid_fftindextobfsfcwfactor_9_8_pos 0
+#define reg_mccid_fftindextobfsfcwfactor_9_8_len 2
+#define reg_mccid_fftindextobfsfcwfactor_9_8_lsb 8
+#define    p_reg_mccid_bfsfcwffttoindexfactor_7_0   0xF154
+#define reg_mccid_bfsfcwffttoindexfactor_7_0_pos 0
+#define reg_mccid_bfsfcwffttoindexfactor_7_0_len 8
+#define reg_mccid_bfsfcwffttoindexfactor_7_0_lsb 0
+#define    p_reg_mccid_bfsfcwffttoindexfactor_10_8  0xF155
+#define reg_mccid_bfsfcwffttoindexfactor_10_8_pos 0
+#define reg_mccid_bfsfcwffttoindexfactor_10_8_len 3
+#define reg_mccid_bfsfcwffttoindexfactor_10_8_lsb 8
+#define    p_reg_mccid_detectedaci  0xF156
+#define reg_mccid_detectedaci_pos 0
+#define reg_mccid_detectedaci_len 1
+#define reg_mccid_detectedaci_lsb 0
+#define    r_reg_mccid_filter_enable    0xF157
+#define reg_mccid_filter_enable_pos 0
+#define reg_mccid_filter_enable_len 1
+#define reg_mccid_filter_enable_lsb 0
+#define    p_reg_mccid_aciscstrobe  0xF158
+#define reg_mccid_aciscstrobe_pos 0
+#define reg_mccid_aciscstrobe_len 7
+#define reg_mccid_aciscstrobe_lsb 0
+#define    p_reg_mccid_scanningaci  0xF159
+#define reg_mccid_scanningaci_pos 0
+#define reg_mccid_scanningaci_len 1
+#define reg_mccid_scanningaci_lsb 0
+#define    p_reg_mccid_windowsizeacciwdcount_7_0    0xF15A
+#define reg_mccid_windowsizeacciwdcount_7_0_pos 0
+#define reg_mccid_windowsizeacciwdcount_7_0_len 8
+#define reg_mccid_windowsizeacciwdcount_7_0_lsb 0
+#define    p_reg_mccid_windowsizeacciwdcount_12_8   0xF15B
+#define reg_mccid_windowsizeacciwdcount_12_8_pos 0
+#define reg_mccid_windowsizeacciwdcount_12_8_len 5
+#define reg_mccid_windowsizeacciwdcount_12_8_lsb 8
+#define    p_reg_mccid_scannedacionly   0xF15C
+#define reg_mccid_scannedacionly_pos 0
+#define reg_mccid_scannedacionly_len 1
+#define reg_mccid_scannedacionly_lsb 0
+#define    p_reg_mccid_scfactor 0xF15D
+#define reg_mccid_scfactor_pos 0
+#define reg_mccid_scfactor_len 5
+#define reg_mccid_scfactor_lsb 0
+#define    p_reg_mccid_defaultevaluatingbandwidthfactor 0xF15E
+#define reg_mccid_defaultevaluatingbandwidthfactor_pos 0
+#define reg_mccid_defaultevaluatingbandwidthfactor_len 3
+#define reg_mccid_defaultevaluatingbandwidthfactor_lsb 0
+#define    p_reg_mccid_defaultacipowerlevel 0xF15F
+#define reg_mccid_defaultacipowerlevel_pos 0
+#define reg_mccid_defaultacipowerlevel_len 3
+#define reg_mccid_defaultacipowerlevel_lsb 0
+#define    r_reg_mccid_outputdagc1gain_7_0  0xF160
+#define reg_mccid_outputdagc1gain_7_0_pos 0
+#define reg_mccid_outputdagc1gain_7_0_len 8
+#define reg_mccid_outputdagc1gain_7_0_lsb 0
+#define    r_reg_mccid_outputdagc1gain_9_8  0xF161
+#define reg_mccid_outputdagc1gain_9_8_pos 0
+#define reg_mccid_outputdagc1gain_9_8_len 2
+#define reg_mccid_outputdagc1gain_9_8_lsb 8
+#define    r_reg_mccid_outputdagc1gainshift 0xF162
+#define reg_mccid_outputdagc1gainshift_pos 0
+#define reg_mccid_outputdagc1gainshift_len 4
+#define reg_mccid_outputdagc1gainshift_lsb 0
+#define    p_reg_mccid_defaultacwgcheckccipowerlevel    0xF163
+#define reg_mccid_defaultacwgcheckccipowerlevel_pos 0
+#define reg_mccid_defaultacwgcheckccipowerlevel_len 3
+#define reg_mccid_defaultacwgcheckccipowerlevel_lsb 0
+#define    p_reg_mccid_ccipowerlevelfactor  0xF166
+#define reg_mccid_ccipowerlevelfactor_pos 0
+#define reg_mccid_ccipowerlevelfactor_len 3
+#define reg_mccid_ccipowerlevelfactor_lsb 0
+#define    p_reg_mccid_scstrobesearchingrange   0xF167
+#define reg_mccid_scstrobesearchingrange_pos 0
+#define reg_mccid_scstrobesearchingrange_len 8
+#define reg_mccid_scstrobesearchingrange_lsb 0
+#define    p_reg_mccid_searchingno  0xF168
+#define reg_mccid_searchingno_pos 0
+#define reg_mccid_searchingno_len 6
+#define reg_mccid_searchingno_lsb 0
+#define    p_reg_mccid_scannedacifrequencyresolution    0xF169
+#define reg_mccid_scannedacifrequencyresolution_pos 0
+#define reg_mccid_scannedacifrequencyresolution_len 4
+#define reg_mccid_scannedacifrequencyresolution_lsb 0
+#define    p_reg_mccid_fft0_maskmaxtoneindex_7_0    0xF16A
+#define reg_mccid_fft0_maskmaxtoneindex_7_0_pos 0
+#define reg_mccid_fft0_maskmaxtoneindex_7_0_len 8
+#define reg_mccid_fft0_maskmaxtoneindex_7_0_lsb 0
+#define    p_reg_mccid_fft0_maskmaxtoneindex_12_8   0xF16B
+#define reg_mccid_fft0_maskmaxtoneindex_12_8_pos 0
+#define reg_mccid_fft0_maskmaxtoneindex_12_8_len 5
+#define reg_mccid_fft0_maskmaxtoneindex_12_8_lsb 8
+#define    p_reg_mccid_fft0_state   0xF16C
+#define reg_mccid_fft0_state_pos 0
+#define reg_mccid_fft0_state_len 1
+#define reg_mccid_fft0_state_lsb 0
+#define    p_reg_mccid_fft1_state   0xF16D
+#define reg_mccid_fft1_state_pos 0
+#define reg_mccid_fft1_state_len 1
+#define reg_mccid_fft1_state_lsb 0
+#define    p_reg_mccid_fft0_maskmintoneindex_7_0    0xF16E
+#define reg_mccid_fft0_maskmintoneindex_7_0_pos 0
+#define reg_mccid_fft0_maskmintoneindex_7_0_len 8
+#define reg_mccid_fft0_maskmintoneindex_7_0_lsb 0
+#define    p_reg_mccid_fft0_maskmintoneindex_12_8   0xF16F
+#define reg_mccid_fft0_maskmintoneindex_12_8_pos 0
+#define reg_mccid_fft0_maskmintoneindex_12_8_len 5
+#define reg_mccid_fft0_maskmintoneindex_12_8_lsb 8
+#define    p_reg_mccid_acipowerlevelfactor  0xF170
+#define reg_mccid_acipowerlevelfactor_pos 0
+#define reg_mccid_acipowerlevelfactor_len 3
+#define reg_mccid_acipowerlevelfactor_lsb 0
+#define    p_reg_mccid_fft1_maskmaxtoneindex_7_0    0xF171
+#define reg_mccid_fft1_maskmaxtoneindex_7_0_pos 0
+#define reg_mccid_fft1_maskmaxtoneindex_7_0_len 8
+#define reg_mccid_fft1_maskmaxtoneindex_7_0_lsb 0
+#define    p_reg_mccid_fft1_maskmaxtoneindex_12_8   0xF172
+#define reg_mccid_fft1_maskmaxtoneindex_12_8_pos 0
+#define reg_mccid_fft1_maskmaxtoneindex_12_8_len 5
+#define reg_mccid_fft1_maskmaxtoneindex_12_8_lsb 8
+#define    p_reg_mccid_fft1_maskmintoneindex_7_0    0xF173
+#define reg_mccid_fft1_maskmintoneindex_7_0_pos 0
+#define reg_mccid_fft1_maskmintoneindex_7_0_len 8
+#define reg_mccid_fft1_maskmintoneindex_7_0_lsb 0
+#define    p_reg_mccid_fft1_maskmintoneindex_12_8   0xF174
+#define reg_mccid_fft1_maskmintoneindex_12_8_pos 0
+#define reg_mccid_fft1_maskmintoneindex_12_8_len 5
+#define reg_mccid_fft1_maskmintoneindex_12_8_lsb 8
+#define    p_reg_mccid_reset    0xF175
+#define reg_mccid_reset_pos 0
+#define reg_mccid_reset_len 1
+#define reg_mccid_reset_lsb 0
+#define    p_reg_mccid_gaincmpreset 0xF176
+#define reg_mccid_gaincmpreset_pos 0
+#define reg_mccid_gaincmpreset_len 1
+#define reg_mccid_gaincmpreset_lsb 0
+#define    p_reg_mccid_acwgreset    0xF177
+#define reg_mccid_acwgreset_pos 0
+#define reg_mccid_acwgreset_len 1
+#define reg_mccid_acwgreset_lsb 0
+#define    p_reg_mccid_ccif0_ofsmstateenable    0xF178
+#define reg_mccid_ccif0_ofsmstateenable_pos 0
+#define reg_mccid_ccif0_ofsmstateenable_len 1
+#define reg_mccid_ccif0_ofsmstateenable_lsb 0
+#define    p_reg_mccid_ccif1_ofsmstateenable    0xF179
+#define reg_mccid_ccif1_ofsmstateenable_pos 0
+#define reg_mccid_ccif1_ofsmstateenable_len 1
+#define reg_mccid_ccif1_ofsmstateenable_lsb 0
+#define    p_reg_mccid_fft0_ofsmstateenable 0xF17A
+#define reg_mccid_fft0_ofsmstateenable_pos 0
+#define reg_mccid_fft0_ofsmstateenable_len 1
+#define reg_mccid_fft0_ofsmstateenable_lsb 0
+#define    p_reg_mccid_fft1_ofsmstateenable 0xF17B
+#define reg_mccid_fft1_ofsmstateenable_pos 0
+#define reg_mccid_fft1_ofsmstateenable_len 1
+#define reg_mccid_fft1_ofsmstateenable_lsb 0
+#define    p_reg_mccid_fftfiltermaskchange  0xF17C
+#define reg_mccid_fftfiltermaskchange_pos 0
+#define reg_mccid_fftfiltermaskchange_len 1
+#define reg_mccid_fftfiltermaskchange_lsb 0
+#define    r_reg_mccid_maxacipowertone_7_0  0xF17D
+#define reg_mccid_maxacipowertone_7_0_pos 0
+#define reg_mccid_maxacipowertone_7_0_len 8
+#define reg_mccid_maxacipowertone_7_0_lsb 0
+#define    r_reg_mccid_maxacipowertone_12_8 0xF17E
+#define reg_mccid_maxacipowertone_12_8_pos 0
+#define reg_mccid_maxacipowertone_12_8_len 5
+#define reg_mccid_maxacipowertone_12_8_lsb 8
+#define    r_reg_mccid_ccidisappear 0xF17F
+#define reg_mccid_ccidisappear_pos 0
+#define reg_mccid_ccidisappear_len 1
+#define reg_mccid_ccidisappear_lsb 0
+#define    r_reg_mccid_ccilocatordone   0xF182
+#define reg_mccid_ccilocatordone_pos 0
+#define reg_mccid_ccilocatordone_len 1
+#define reg_mccid_ccilocatordone_lsb 0
+#define    p_reg_mccid_enablecciftrigger    0xF183
+#define reg_mccid_enablecciftrigger_pos 0
+#define reg_mccid_enablecciftrigger_len 1
+#define reg_mccid_enablecciftrigger_lsb 0
+#define    p_reg_mccid_disableacwglaunchevaluationbandwidthtrigger  0xF184
+#define reg_mccid_disableacwglaunchevaluationbandwidthtrigger_pos 0
+#define reg_mccid_disableacwglaunchevaluationbandwidthtrigger_len 1
+#define reg_mccid_disableacwglaunchevaluationbandwidthtrigger_lsb 0
+#define    p_reg_mccid_control_by_ofsm  0xF185
+#define reg_mccid_control_by_ofsm_pos 0
+#define reg_mccid_control_by_ofsm_len 1
+#define reg_mccid_control_by_ofsm_lsb 0
+#define    p_reg_mccid_ofsmcontrolccilocator    0xF186
+#define reg_mccid_ofsmcontrolccilocator_pos 0
+#define reg_mccid_ofsmcontrolccilocator_len 1
+#define reg_mccid_ofsmcontrolccilocator_lsb 0
+#define    p_reg_mccid_disablepotentialccitriggerccilocator 0xF187
+#define reg_mccid_disablepotentialccitriggerccilocator_pos 0
+#define reg_mccid_disablepotentialccitriggerccilocator_len 1
+#define reg_mccid_disablepotentialccitriggerccilocator_lsb 0
+#define    p_reg_mccid_ofsmcontrolccitesting    0xF188
+#define reg_mccid_ofsmcontrolccitesting_pos 0
+#define reg_mccid_ofsmcontrolccitesting_len 1
+#define reg_mccid_ofsmcontrolccitesting_lsb 0
+#define    p_reg_mccid_disableccitestingtriggercheckcci 0xF189
+#define reg_mccid_disableccitestingtriggercheckcci_pos 0
+#define reg_mccid_disableccitestingtriggercheckcci_len 1
+#define reg_mccid_disableccitestingtriggercheckcci_lsb 0
+#define    p_reg_mccid_ofsmcontrolacwgsetccifscstrobe   0xF18A
+#define reg_mccid_ofsmcontrolacwgsetccifscstrobe_pos 0
+#define reg_mccid_ofsmcontrolacwgsetccifscstrobe_len 1
+#define reg_mccid_ofsmcontrolacwgsetccifscstrobe_lsb 0
+#define    p_reg_mccid_disableacwgevaluatingbandwidthtrigger    0xF18B
+#define reg_mccid_disableacwgevaluatingbandwidthtrigger_pos 0
+#define reg_mccid_disableacwgevaluatingbandwidthtrigger_len 1
+#define reg_mccid_disableacwgevaluatingbandwidthtrigger_lsb 0
+#define    p_reg_mccid_ofsmcontrolevaluatingbandwidth   0xF18C
+#define reg_mccid_ofsmcontrolevaluatingbandwidth_pos 0
+#define reg_mccid_ofsmcontrolevaluatingbandwidth_len 1
+#define reg_mccid_ofsmcontrolevaluatingbandwidth_lsb 0
+#define    p_reg_mccid_ofsmcontrolscanningaci   0xF18D
+#define reg_mccid_ofsmcontrolscanningaci_pos 0
+#define reg_mccid_ofsmcontrolscanningaci_len 1
+#define reg_mccid_ofsmcontrolscanningaci_lsb 0
+#define    p_reg_mccid_disablescanningaci   0xF18E
+#define reg_mccid_disablescanningaci_pos 0
+#define reg_mccid_disablescanningaci_len 1
+#define reg_mccid_disablescanningaci_lsb 0
+#define    p_reg_mccid_disableacwgccidetecting  0xF18F
+#define reg_mccid_disableacwgccidetecting_pos 0
+#define reg_mccid_disableacwgccidetecting_len 1
+#define reg_mccid_disableacwgccidetecting_lsb 0
+#define    p_reg_mccid_ofsmcontrolccitimertrigger   0xF190
+#define reg_mccid_ofsmcontrolccitimertrigger_pos 0
+#define reg_mccid_ofsmcontrolccitimertrigger_len 1
+#define reg_mccid_ofsmcontrolccitimertrigger_lsb 0
+#define    p_reg_mccid_disableccitimertrigger   0xF191
+#define reg_mccid_disableccitimertrigger_pos 0
+#define reg_mccid_disableccitimertrigger_len 1
+#define reg_mccid_disableccitimertrigger_lsb 0
+#define    p_reg_mccid_ofsmdisableccitriggercounting    0xF192
+#define reg_mccid_ofsmdisableccitriggercounting_pos 0
+#define reg_mccid_ofsmdisableccitriggercounting_len 1
+#define reg_mccid_ofsmdisableccitriggercounting_lsb 0
+#define    p_reg_mccid_enableccifilteraci   0xF193
+#define reg_mccid_enableccifilteraci_pos 0
+#define reg_mccid_enableccifilteraci_len 1
+#define reg_mccid_enableccifilteraci_lsb 0
+#define    p_reg_mccid_scannedfcwbfs_7_0    0xF194
+#define reg_mccid_scannedfcwbfs_7_0_pos 0
+#define reg_mccid_scannedfcwbfs_7_0_len 8
+#define reg_mccid_scannedfcwbfs_7_0_lsb 0
+#define    p_reg_mccid_scannedfcwbfs_13_8   0xF195
+#define reg_mccid_scannedfcwbfs_13_8_pos 0
+#define reg_mccid_scannedfcwbfs_13_8_len 6
+#define reg_mccid_scannedfcwbfs_13_8_lsb 8
+#define    p_reg_mccid_acwgevaluatingbandwidth  0xF196
+#define reg_mccid_acwgevaluatingbandwidth_pos 0
+#define reg_mccid_acwgevaluatingbandwidth_len 1
+#define reg_mccid_acwgevaluatingbandwidth_lsb 0
+#define    p_reg_mccid_acwglaunchevaluationbandwidth    0xF197
+#define reg_mccid_acwglaunchevaluationbandwidth_pos 0
+#define reg_mccid_acwglaunchevaluationbandwidth_len 1
+#define reg_mccid_acwglaunchevaluationbandwidth_lsb 0
+#define    p_reg_mccid_scannedcandidate 0xF198
+#define reg_mccid_scannedcandidate_pos 0
+#define reg_mccid_scannedcandidate_len 3
+#define reg_mccid_scannedcandidate_lsb 0
+#define    p_reg_mccid_scstrobesearchingcandidate   0xF199
+#define reg_mccid_scstrobesearchingcandidate_pos 0
+#define reg_mccid_scstrobesearchingcandidate_len 2
+#define reg_mccid_scstrobesearchingcandidate_lsb 0
+#define    p_reg_mccid_potentialcci 0xF19A
+#define reg_mccid_potentialcci_pos 0
+#define reg_mccid_potentialcci_len 1
+#define reg_mccid_potentialcci_lsb 0
+#define    p_reg_mccid_cciftimertrigger 0xF19B
+#define reg_mccid_cciftimertrigger_pos 0
+#define reg_mccid_cciftimertrigger_len 1
+#define reg_mccid_cciftimertrigger_lsb 0
+#define    p_reg_mccid_ccitesting   0xF19C
+#define reg_mccid_ccitesting_pos 0
+#define reg_mccid_ccitesting_len 1
+#define reg_mccid_ccitesting_lsb 0
+#define    p_reg_mccid_defaultccilocatormissno  0xF19D
+#define reg_mccid_defaultccilocatormissno_pos 0
+#define reg_mccid_defaultccilocatormissno_len 8
+#define reg_mccid_defaultccilocatormissno_lsb 0
+#define    p_reg_mccid_dagc1_use_despow 0xF19E
+#define reg_mccid_dagc1_use_despow_pos 0
+#define reg_mccid_dagc1_use_despow_len 1
+#define reg_mccid_dagc1_use_despow_lsb 0
+#define    p_reg_mccid_scannedacifrequencybegin_7_0 0xF19F
+#define reg_mccid_scannedacifrequencybegin_7_0_pos 0
+#define reg_mccid_scannedacifrequencybegin_7_0_len 8
+#define reg_mccid_scannedacifrequencybegin_7_0_lsb 0
+#define    p_reg_mccid_scannedacifrequencybegin_13_8    0xF1A0
+#define reg_mccid_scannedacifrequencybegin_13_8_pos 0
+#define reg_mccid_scannedacifrequencybegin_13_8_len 6
+#define reg_mccid_scannedacifrequencybegin_13_8_lsb 8
+#define    p_reg_mccid_scannedacifrequencyend_7_0   0xF1A1
+#define reg_mccid_scannedacifrequencyend_7_0_pos 0
+#define reg_mccid_scannedacifrequencyend_7_0_len 8
+#define reg_mccid_scannedacifrequencyend_7_0_lsb 0
+#define    p_reg_mccid_scannedacifrequencyend_13_8  0xF1A2
+#define reg_mccid_scannedacifrequencyend_13_8_pos 0
+#define reg_mccid_scannedacifrequencyend_13_8_len 6
+#define reg_mccid_scannedacifrequencyend_13_8_lsb 8
+#define    p_reg_bfs_fcw_7_0    0xF1A3
+#define reg_bfs_fcw_7_0_pos 0
+#define reg_bfs_fcw_7_0_len 8
+#define reg_bfs_fcw_7_0_lsb 0
+#define    p_reg_bfs_fcw_15_8   0xF1A4
+#define reg_bfs_fcw_15_8_pos 0
+#define reg_bfs_fcw_15_8_len 8
+#define reg_bfs_fcw_15_8_lsb 8
+#define    p_reg_bfs_fcw_22_16  0xF1A5
+#define reg_bfs_fcw_22_16_pos 0
+#define reg_bfs_fcw_22_16_len 7
+#define reg_bfs_fcw_22_16_lsb 16
+#define    p_reg_cfoe_fcw_inv   0xF1A6
+#define reg_cfoe_fcw_inv_pos 0
+#define reg_cfoe_fcw_inv_len 1
+#define reg_cfoe_fcw_inv_lsb 0
+#define    p_reg_bfs_0if    0xF1A7
+#define reg_bfs_0if_pos 0
+#define reg_bfs_0if_len 1
+#define reg_bfs_0if_lsb 0
+#define    p_reg_sadc_clk   0xF1A9
+#define reg_sadc_clk_pos 0
+#define reg_sadc_clk_len 1
+#define reg_sadc_clk_lsb 0
+#define    p_reg_sadc_tx    0xF1AA
+#define reg_sadc_tx_pos 0
+#define reg_sadc_tx_len 1
+#define reg_sadc_tx_lsb 0
+#define    p_reg_sadc_rx    0xF1AB
+#define reg_sadc_rx_pos 0
+#define reg_sadc_rx_len 1
+#define reg_sadc_rx_lsb 0
+#define    p_reg_sadc_cs    0xF1AC
+#define reg_sadc_cs_pos 0
+#define reg_sadc_cs_len 1
+#define reg_sadc_cs_lsb 0
+#define    p_reg_fix_fcw_7_0    0xF1AD
+#define reg_fix_fcw_7_0_pos 0
+#define reg_fix_fcw_7_0_len 8
+#define reg_fix_fcw_7_0_lsb 0
+#define    p_reg_fix_fcw_15_8   0xF1AE
+#define reg_fix_fcw_15_8_pos 0
+#define reg_fix_fcw_15_8_len 8
+#define reg_fix_fcw_15_8_lsb 8
+#define    p_reg_fix_fcw_22_16  0xF1AF
+#define reg_fix_fcw_22_16_pos 0
+#define reg_fix_fcw_22_16_len 7
+#define reg_fix_fcw_22_16_lsb 16
+#define    r_reg_bfs_fcw_offset_7_0 0xF1B0
+#define reg_bfs_fcw_offset_7_0_pos 0
+#define reg_bfs_fcw_offset_7_0_len 8
+#define reg_bfs_fcw_offset_7_0_lsb 0
+#define    r_reg_bfs_fcw_offset_15_8    0xF1B1
+#define reg_bfs_fcw_offset_15_8_pos 0
+#define reg_bfs_fcw_offset_15_8_len 8
+#define reg_bfs_fcw_offset_15_8_lsb 8
+#define    r_reg_bfs_fcw_offset_22_16   0xF1B2
+#define reg_bfs_fcw_offset_22_16_pos 0
+#define reg_bfs_fcw_offset_22_16_len 7
+#define reg_bfs_fcw_offset_22_16_lsb 16
+#define    r_bfs_fcw_q_7_0  0xF1B3
+#define bfs_fcw_q_7_0_pos 0
+#define bfs_fcw_q_7_0_len 8
+#define bfs_fcw_q_7_0_lsb 0
+#define    r_bfs_fcw_q_15_8 0xF1B4
+#define bfs_fcw_q_15_8_pos 0
+#define bfs_fcw_q_15_8_len 8
+#define bfs_fcw_q_15_8_lsb 8
+#define    r_bfs_fcw_q_22_16    0xF1B5
+#define bfs_fcw_q_22_16_pos 0
+#define bfs_fcw_q_22_16_len 7
+#define bfs_fcw_q_22_16_lsb 16
+#define    p_reg_dagc3_use_despow   0xF1B6
+#define reg_dagc3_use_despow_pos 0
+#define reg_dagc3_use_despow_len 1
+#define reg_dagc3_use_despow_lsb 0
+#define    p_reg_dagc3_log_2_accumulate 0xF1B7
+#define reg_dagc3_log_2_accumulate_pos 0
+#define reg_dagc3_log_2_accumulate_len 5
+#define reg_dagc3_log_2_accumulate_lsb 0
+#define    p_reg_dagc3_desired_level_7_0    0xF1BC
+#define reg_dagc3_desired_level_7_0_pos 0
+#define reg_dagc3_desired_level_7_0_len 8
+#define reg_dagc3_desired_level_7_0_lsb 0
+#define    p_reg_dagc3_desired_level_8  0xF1BD
+#define reg_dagc3_desired_level_8_pos 0
+#define reg_dagc3_desired_level_8_len 1
+#define reg_dagc3_desired_level_8_lsb 8
+#define    p_reg_dagc3_apply_delay  0xF1BE
+#define reg_dagc3_apply_delay_pos 0
+#define reg_dagc3_apply_delay_len 7
+#define reg_dagc3_apply_delay_lsb 0
+#define    p_reg_dagc3_bp_scale 0xF1BF
+#define reg_dagc3_bp_scale_pos 0
+#define reg_dagc3_bp_scale_len 3
+#define reg_dagc3_bp_scale_lsb 0
+#define    p_reg_dagc3_in_sat_cnt_7_0   0xF1C0
+#define reg_dagc3_in_sat_cnt_7_0_pos 0
+#define reg_dagc3_in_sat_cnt_7_0_len 8
+#define reg_dagc3_in_sat_cnt_7_0_lsb 0
+#define    p_reg_dagc3_in_sat_cnt_15_8  0xF1C1
+#define reg_dagc3_in_sat_cnt_15_8_pos 0
+#define reg_dagc3_in_sat_cnt_15_8_len 8
+#define reg_dagc3_in_sat_cnt_15_8_lsb 8
+#define    p_reg_dagc3_in_sat_cnt_23_16 0xF1C2
+#define reg_dagc3_in_sat_cnt_23_16_pos 0
+#define reg_dagc3_in_sat_cnt_23_16_len 8
+#define reg_dagc3_in_sat_cnt_23_16_lsb 16
+#define    p_reg_dagc3_in_sat_cnt_31_24 0xF1C3
+#define reg_dagc3_in_sat_cnt_31_24_pos 0
+#define reg_dagc3_in_sat_cnt_31_24_len 8
+#define reg_dagc3_in_sat_cnt_31_24_lsb 24
+#define    p_reg_dagc3_out_sat_cnt_7_0  0xF1C4
+#define reg_dagc3_out_sat_cnt_7_0_pos 0
+#define reg_dagc3_out_sat_cnt_7_0_len 8
+#define reg_dagc3_out_sat_cnt_7_0_lsb 0
+#define    p_reg_dagc3_out_sat_cnt_15_8 0xF1C5
+#define reg_dagc3_out_sat_cnt_15_8_pos 0
+#define reg_dagc3_out_sat_cnt_15_8_len 8
+#define reg_dagc3_out_sat_cnt_15_8_lsb 8
+#define    p_reg_dagc3_out_sat_cnt_23_16    0xF1C6
+#define reg_dagc3_out_sat_cnt_23_16_pos 0
+#define reg_dagc3_out_sat_cnt_23_16_len 8
+#define reg_dagc3_out_sat_cnt_23_16_lsb 16
+#define    p_reg_dagc3_out_sat_cnt_31_24    0xF1C7
+#define reg_dagc3_out_sat_cnt_31_24_pos 0
+#define reg_dagc3_out_sat_cnt_31_24_len 8
+#define reg_dagc3_out_sat_cnt_31_24_lsb 24
+#define    r_bfs_dagc3_multiplier_7_0   0xF1C8
+#define bfs_dagc3_multiplier_7_0_pos 0
+#define bfs_dagc3_multiplier_7_0_len 8
+#define bfs_dagc3_multiplier_7_0_lsb 0
+#define    r_bfs_dagc3_multiplier_15_8  0xF1C9
+#define bfs_dagc3_multiplier_15_8_pos 0
+#define bfs_dagc3_multiplier_15_8_len 8
+#define bfs_dagc3_multiplier_15_8_lsb 8
+#define    r_bfs_dagc3_right_shift_bits 0xF1CA
+#define bfs_dagc3_right_shift_bits_pos 0
+#define bfs_dagc3_right_shift_bits_len 4
+#define bfs_dagc3_right_shift_bits_lsb 0
+#define    p_reg_dagc3_fixed_gain_7_0   0xF1CB
+#define reg_dagc3_fixed_gain_7_0_pos 0
+#define reg_dagc3_fixed_gain_7_0_len 8
+#define reg_dagc3_fixed_gain_7_0_lsb 0
+#define    p_reg_dagc3_fixed_gain_11_8  0xF1CC
+#define reg_dagc3_fixed_gain_11_8_pos 0
+#define reg_dagc3_fixed_gain_11_8_len 4
+#define reg_dagc3_fixed_gain_11_8_lsb 8
+#define    p_reg_f_adc_7_0  0xF1CD
+#define reg_f_adc_7_0_pos 0
+#define reg_f_adc_7_0_len 8
+#define reg_f_adc_7_0_lsb 0
+#define    p_reg_f_adc_15_8 0xF1CE
+#define reg_f_adc_15_8_pos 0
+#define reg_f_adc_15_8_len 8
+#define reg_f_adc_15_8_lsb 8
+#define    p_reg_f_adc_23_16    0xF1CF
+#define reg_f_adc_23_16_pos 0
+#define reg_f_adc_23_16_len 8
+#define reg_f_adc_23_16_lsb 16
+#define    p_reg_fste_frac_step_size_7_0    0xF1D0
+#define reg_fste_frac_step_size_7_0_pos 0
+#define reg_fste_frac_step_size_7_0_len 8
+#define reg_fste_frac_step_size_7_0_lsb 0
+#define    p_reg_fste_frac_step_size_15_8   0xF1D1
+#define reg_fste_frac_step_size_15_8_pos 0
+#define reg_fste_frac_step_size_15_8_len 8
+#define reg_fste_frac_step_size_15_8_lsb 8
+#define    p_reg_fste_frac_step_size_19_16  0xF1D2
+#define reg_fste_frac_step_size_19_16_pos 0
+#define reg_fste_frac_step_size_19_16_len 4
+#define reg_fste_frac_step_size_19_16_lsb 16
+#define    r_intp_mu_7_0    0xF1D3
+#define intp_mu_7_0_pos 0
+#define intp_mu_7_0_len 8
+#define intp_mu_7_0_lsb 0
+#define    r_intp_mu_15_8   0xF1D4
+#define intp_mu_15_8_pos 0
+#define intp_mu_15_8_len 8
+#define intp_mu_15_8_lsb 8
+#define    r_intp_mu_23_16  0xF1D5
+#define intp_mu_23_16_pos 0
+#define intp_mu_23_16_len 8
+#define intp_mu_23_16_lsb 16
+#define    r_intp_mu_25_24  0xF1D6
+#define intp_mu_25_24_pos 0
+#define intp_mu_25_24_len 2
+#define intp_mu_25_24_lsb 24
+#define    p_intp_muq_7_0   0xF1D7
+#define intp_muq_7_0_pos 0
+#define intp_muq_7_0_len 8
+#define intp_muq_7_0_lsb 0
+#define    p_intp_muq_15_8  0xF1D8
+#define intp_muq_15_8_pos 0
+#define intp_muq_15_8_len 8
+#define intp_muq_15_8_lsb 8
+#define    p_intp_muq_23_16 0xF1D9
+#define intp_muq_23_16_pos 0
+#define intp_muq_23_16_len 8
+#define intp_muq_23_16_lsb 16
+#define    p_reg_sfoe_inv   0xF1DA
+#define reg_sfoe_inv_pos 0
+#define reg_sfoe_inv_len 1
+#define reg_sfoe_inv_lsb 0
+#define    p_intp_ext_en    0xF1DB
+#define intp_ext_en_pos 0
+#define intp_ext_en_len 1
+#define intp_ext_en_lsb 0
+#define    r_intp_ext_done  0xF1DC
+#define intp_ext_done_pos 0
+#define intp_ext_done_len 1
+#define intp_ext_done_lsb 0
+#define    p_intp_ext_in_7_0    0xF1DD
+#define intp_ext_in_7_0_pos 0
+#define intp_ext_in_7_0_len 8
+#define intp_ext_in_7_0_lsb 0
+#define    p_intp_ext_in_15_8   0xF1DE
+#define intp_ext_in_15_8_pos 0
+#define intp_ext_in_15_8_len 8
+#define intp_ext_in_15_8_lsb 8
+#define    p_intp_ext_in_23_16  0xF1DF
+#define intp_ext_in_23_16_pos 0
+#define intp_ext_in_23_16_len 8
+#define intp_ext_in_23_16_lsb 16
+#define    p_intp_ext_in_25_24  0xF1E0
+#define intp_ext_in_25_24_pos 0
+#define intp_ext_in_25_24_len 2
+#define intp_ext_in_25_24_lsb 24
+#define    r_intp_ext_out_7_0   0xF1E1
+#define intp_ext_out_7_0_pos 0
+#define intp_ext_out_7_0_len 8
+#define intp_ext_out_7_0_lsb 0
+#define    r_intp_ext_out_15_8  0xF1E2
+#define intp_ext_out_15_8_pos 0
+#define intp_ext_out_15_8_len 8
+#define intp_ext_out_15_8_lsb 8
+#define    r_intp_ext_out_23_16 0xF1E3
+#define intp_ext_out_23_16_pos 0
+#define intp_ext_out_23_16_len 8
+#define intp_ext_out_23_16_lsb 16
+#define    r_intp_ext_out_28_24 0xF1E4
+#define intp_ext_out_28_24_pos 0
+#define intp_ext_out_28_24_len 5
+#define intp_ext_out_28_24_lsb 24
+#define    p_reg_agc_rst    0xF1E5
+#define reg_agc_rst_pos 0
+#define reg_agc_rst_len 1
+#define reg_agc_rst_lsb 0
+#define    p_rf_agc_en  0xF1E6
+#define rf_agc_en_pos 0
+#define rf_agc_en_len 1
+#define rf_agc_en_lsb 0
+#define    p_agc_lock   0xF1E7
+#define agc_lock_pos 0
+#define agc_lock_len 1
+#define agc_lock_lsb 0
+#define    p_reg_tinr_rst   0xF1E8
+#define reg_tinr_rst_pos 0
+#define reg_tinr_rst_len 1
+#define reg_tinr_rst_lsb 0
+#define    p_reg_tinr_en    0xF1E9
+#define reg_tinr_en_pos 0
+#define reg_tinr_en_len 1
+#define reg_tinr_en_lsb 0
+#define    p_reg_bfs_en 0xF1EA
+#define reg_bfs_en_pos 0
+#define reg_bfs_en_len 1
+#define reg_bfs_en_lsb 0
+#define    p_reg_bfs_rst    0xF1EB
+#define reg_bfs_rst_pos 0
+#define reg_bfs_rst_len 1
+#define reg_bfs_rst_lsb 0
+#define    p_reg_bfs_byp    0xF1EC
+#define reg_bfs_byp_pos 0
+#define reg_bfs_byp_len 1
+#define reg_bfs_byp_lsb 0
+#define    p_intp_en    0xF1EF
+#define intp_en_pos 0
+#define intp_en_len 1
+#define intp_en_lsb 0
+#define    p_intp_rst   0xF1F0
+#define intp_rst_pos 0
+#define intp_rst_len 1
+#define intp_rst_lsb 0
+#define    p_reg_p_acif_en  0xF1F2
+#define reg_p_acif_en_pos 0
+#define reg_p_acif_en_len 1
+#define reg_p_acif_en_lsb 0
+#define    p_reg_p_acif_rst 0xF1F3
+#define reg_p_acif_rst_pos 0
+#define reg_p_acif_rst_len 1
+#define reg_p_acif_rst_lsb 0
+#define    p_reg_p_acif_byp 0xF1F4
+#define reg_p_acif_byp_pos 0
+#define reg_p_acif_byp_len 1
+#define reg_p_acif_byp_lsb 0
+#define    p_dagc2_rst  0xF1F6
+#define dagc2_rst_pos 0
+#define dagc2_rst_len 1
+#define dagc2_rst_lsb 0
+#define    p_dagc2_en   0xF1F7
+#define dagc2_en_pos 0
+#define dagc2_en_len 1
+#define dagc2_en_lsb 0
+#define    p_dagc2_mode 0xF1F8
+#define dagc2_mode_pos 0
+#define dagc2_mode_len 2
+#define dagc2_mode_lsb 0
+#define    p_dagc2_done 0xF1F9
+#define dagc2_done_pos 0
+#define dagc2_done_len 1
+#define dagc2_done_lsb 0
+#define    p_dagc3_rst  0xF1FA
+#define dagc3_rst_pos 0
+#define dagc3_rst_len 1
+#define dagc3_rst_lsb 0
+#define    p_dagc3_en   0xF1FB
+#define dagc3_en_pos 0
+#define dagc3_en_len 1
+#define dagc3_en_lsb 0
+#define    p_dagc3_mode 0xF1FC
+#define dagc3_mode_pos 0
+#define dagc3_mode_len 2
+#define dagc3_mode_lsb 0
+#define    p_dagc3_done 0xF1FD
+#define dagc3_done_pos 0
+#define dagc3_done_len 1
+#define dagc3_done_lsb 0
+#define    p_reg_dagc2_desired_level_7_0    0xF202
+#define reg_dagc2_desired_level_7_0_pos 0
+#define reg_dagc2_desired_level_7_0_len 8
+#define reg_dagc2_desired_level_7_0_lsb 0
+#define    p_reg_dagc2_desired_level_8  0xF203
+#define reg_dagc2_desired_level_8_pos 0
+#define reg_dagc2_desired_level_8_len 1
+#define reg_dagc2_desired_level_8_lsb 8
+#define    p_reg_dagc2_apply_delay  0xF204
+#define reg_dagc2_apply_delay_pos 0
+#define reg_dagc2_apply_delay_len 7
+#define reg_dagc2_apply_delay_lsb 0
+#define    p_reg_dagc2_bypass_scale_ctl 0xF205
+#define reg_dagc2_bypass_scale_ctl_pos 0
+#define reg_dagc2_bypass_scale_ctl_len 3
+#define reg_dagc2_bypass_scale_ctl_lsb 0
+#define    p_reg_dagc2_programmable_shift2  0xF206
+#define reg_dagc2_programmable_shift2_pos 0
+#define reg_dagc2_programmable_shift2_len 8
+#define reg_dagc2_programmable_shift2_lsb 0
+#define    p_reg_dagc2_in_sat_cnt_7_0   0xF207
+#define reg_dagc2_in_sat_cnt_7_0_pos 0
+#define reg_dagc2_in_sat_cnt_7_0_len 8
+#define reg_dagc2_in_sat_cnt_7_0_lsb 0
+#define    p_reg_dagc2_in_sat_cnt_15_8  0xF208
+#define reg_dagc2_in_sat_cnt_15_8_pos 0
+#define reg_dagc2_in_sat_cnt_15_8_len 8
+#define reg_dagc2_in_sat_cnt_15_8_lsb 8
+#define    p_reg_dagc2_in_sat_cnt_23_16 0xF209
+#define reg_dagc2_in_sat_cnt_23_16_pos 0
+#define reg_dagc2_in_sat_cnt_23_16_len 8
+#define reg_dagc2_in_sat_cnt_23_16_lsb 16
+#define    p_reg_dagc2_in_sat_cnt_31_24 0xF20A
+#define reg_dagc2_in_sat_cnt_31_24_pos 0
+#define reg_dagc2_in_sat_cnt_31_24_len 8
+#define reg_dagc2_in_sat_cnt_31_24_lsb 24
+#define    p_reg_dagc2_out_sat_cnt_7_0  0xF20B
+#define reg_dagc2_out_sat_cnt_7_0_pos 0
+#define reg_dagc2_out_sat_cnt_7_0_len 8
+#define reg_dagc2_out_sat_cnt_7_0_lsb 0
+#define    p_reg_dagc2_out_sat_cnt_15_8 0xF20C
+#define reg_dagc2_out_sat_cnt_15_8_pos 0
+#define reg_dagc2_out_sat_cnt_15_8_len 8
+#define reg_dagc2_out_sat_cnt_15_8_lsb 8
+#define    p_reg_dagc2_out_sat_cnt_23_16    0xF20D
+#define reg_dagc2_out_sat_cnt_23_16_pos 0
+#define reg_dagc2_out_sat_cnt_23_16_len 8
+#define reg_dagc2_out_sat_cnt_23_16_lsb 16
+#define    p_reg_dagc2_out_sat_cnt_31_24    0xF20E
+#define reg_dagc2_out_sat_cnt_31_24_pos 0
+#define reg_dagc2_out_sat_cnt_31_24_len 8
+#define reg_dagc2_out_sat_cnt_31_24_lsb 24
+#define    r_reg_dagc2_multiplier_7_0   0xF20F
+#define reg_dagc2_multiplier_7_0_pos 0
+#define reg_dagc2_multiplier_7_0_len 8
+#define reg_dagc2_multiplier_7_0_lsb 0
+#define    r_reg_dagc2_multiplier_15_8  0xF210
+#define reg_dagc2_multiplier_15_8_pos 0
+#define reg_dagc2_multiplier_15_8_len 8
+#define reg_dagc2_multiplier_15_8_lsb 8
+#define    r_reg_dagc2_right_shift_bits 0xF211
+#define reg_dagc2_right_shift_bits_pos 0
+#define reg_dagc2_right_shift_bits_len 4
+#define reg_dagc2_right_shift_bits_lsb 0
+#define    p_reg_dagc2_smbuf_err    0xF212
+#define reg_dagc2_smbuf_err_pos 0
+#define reg_dagc2_smbuf_err_len 1
+#define reg_dagc2_smbuf_err_lsb 0
+#define    p_reg_dagc2_cplxconj 0xF213
+#define reg_dagc2_cplxconj_pos 0
+#define reg_dagc2_cplxconj_len 1
+#define reg_dagc2_cplxconj_lsb 0
+#define    p_reg_dagc2_use_despow   0xF214
+#define reg_dagc2_use_despow_pos 0
+#define reg_dagc2_use_despow_len 1
+#define reg_dagc2_use_despow_lsb 0
+#define    p_reg_dagc2_log_2_accumulate 0xF215
+#define reg_dagc2_log_2_accumulate_pos 0
+#define reg_dagc2_log_2_accumulate_len 5
+#define reg_dagc2_log_2_accumulate_lsb 0
+#define    r_dagc2_dca_gain 0xF216
+#define dagc2_dca_gain_pos 0
+#define dagc2_dca_gain_len 8
+#define dagc2_dca_gain_lsb 0
+#define    p_reg_dca_gain_offset    0xF217
+#define reg_dca_gain_offset_pos 0
+#define reg_dca_gain_offset_len 8
+#define reg_dca_gain_offset_lsb 0
+#define    p_reg_dagc2_FG_mode  0xF218
+#define reg_dagc2_FG_mode_pos 0
+#define reg_dagc2_FG_mode_len 1
+#define reg_dagc2_FG_mode_lsb 0
+#define    p_reg_dagc2_fixed_gain_7_0   0xF219
+#define reg_dagc2_fixed_gain_7_0_pos 0
+#define reg_dagc2_fixed_gain_7_0_len 8
+#define reg_dagc2_fixed_gain_7_0_lsb 0
+#define    p_reg_dagc2_fixed_gain_11_8  0xF21A
+#define reg_dagc2_fixed_gain_11_8_pos 0
+#define reg_dagc2_fixed_gain_11_8_len 4
+#define reg_dagc2_fixed_gain_11_8_lsb 8
+#define    p_reg_td_debug_7_0   0xF21B
+#define reg_td_debug_7_0_pos 0
+#define reg_td_debug_7_0_len 8
+#define reg_td_debug_7_0_lsb 0
+#define    p_reg_td_debug_15_8  0xF21C
+#define reg_td_debug_15_8_pos 0
+#define reg_td_debug_15_8_len 8
+#define reg_td_debug_15_8_lsb 8
+#define    p_reg_td_debug_23_16 0xF21D
+#define reg_td_debug_23_16_pos 0
+#define reg_td_debug_23_16_len 8
+#define reg_td_debug_23_16_lsb 16
+#define    p_reg_td_debug_30_24 0xF21E
+#define reg_td_debug_30_24_pos 0
+#define reg_td_debug_30_24_len 7
+#define reg_td_debug_30_24_lsb 24
+#define    g_reg_clk_sys40  0xF90E
+#define reg_clk_sys40_pos 0
+#define reg_clk_sys40_len 1
+#define reg_clk_sys40_lsb 0
+#define    g_reg_intp_sys_polarity  0xF90F
+#define reg_intp_sys_polarity_pos 0
+#define reg_intp_sys_polarity_len 1
+#define reg_intp_sys_polarity_lsb 0
+#define    g_reg_intp_sys_sc_7_0    0xF910
+#define reg_intp_sys_sc_7_0_pos 0
+#define reg_intp_sys_sc_7_0_len 8
+#define reg_intp_sys_sc_7_0_lsb 0
+#define    g_reg_intp_sys_sc_15_8   0xF911
+#define reg_intp_sys_sc_15_8_pos 0
+#define reg_intp_sys_sc_15_8_len 8
+#define reg_intp_sys_sc_15_8_lsb 8
+#define    g_reg_intp_sys_sc_23_16  0xF912
+#define reg_intp_sys_sc_23_16_pos 0
+#define reg_intp_sys_sc_23_16_len 8
+#define reg_intp_sys_sc_23_16_lsb 16
+#define    g_reg_intp_sys_sc_26_24  0xF913
+#define reg_intp_sys_sc_26_24_pos 0
+#define reg_intp_sys_sc_26_24_len 3
+#define reg_intp_sys_sc_26_24_lsb 24
+#define    g_reg_ofsm_clk   0xF914
+#define reg_ofsm_clk_pos 0
+#define reg_ofsm_clk_len 3
+#define reg_ofsm_clk_lsb 0
+#define    g_reg_fclk_cfg   0xF915
+#define reg_fclk_cfg_pos 0
+#define reg_fclk_cfg_len 1
+#define reg_fclk_cfg_lsb 0
+#define    g_reg_fclk_idi   0xF916
+#define reg_fclk_idi_pos 0
+#define reg_fclk_idi_len 1
+#define reg_fclk_idi_lsb 0
+#define    g_reg_fclk_odi   0xF917
+#define reg_fclk_odi_pos 0
+#define reg_fclk_odi_len 1
+#define reg_fclk_odi_lsb 0
+#define    g_reg_fclk_rsd   0xF918
+#define reg_fclk_rsd_pos 0
+#define reg_fclk_rsd_len 1
+#define reg_fclk_rsd_lsb 0
+#define    g_reg_fclk_vtb   0xF919
+#define reg_fclk_vtb_pos 0
+#define reg_fclk_vtb_len 1
+#define reg_fclk_vtb_lsb 0
+#define    g_reg_fclk_cste  0xF91A
+#define reg_fclk_cste_pos 0
+#define reg_fclk_cste_len 1
+#define reg_fclk_cste_lsb 0
+#define    g_reg_fclk_mp2if 0xF91B
+#define reg_fclk_mp2if_pos 0
+#define reg_fclk_mp2if_len 1
+#define reg_fclk_mp2if_lsb 0
+#define    p_reg_adcout_sync    0xFA00
+#define reg_adcout_sync_pos 0
+#define reg_adcout_sync_len 1
+#define reg_adcout_sync_lsb 0
+#define    p_reg_dagc2o_edge1   0xFA01
+#define reg_dagc2o_edge1_pos 0
+#define reg_dagc2o_edge1_len 1
+#define reg_dagc2o_edge1_lsb 0
+#define    p_reg_dagc2o_edge0   0xFA02
+#define reg_dagc2o_edge0_pos 0
+#define reg_dagc2o_edge0_len 1
+#define reg_dagc2o_edge0_lsb 0
+#define    p_reg_second_rom_on  0xFA03
+#define reg_second_rom_on_pos 0
+#define reg_second_rom_on_len 1
+#define reg_second_rom_on_lsb 0
+#define    p_reg_bypass_host2tuner  0xFA04
+#define reg_bypass_host2tuner_pos 0
+#define reg_bypass_host2tuner_len 1
+#define reg_bypass_host2tuner_lsb 0
+#define    p_cfoe_NS_coeff1_7_0 0xF400
+#define cfoe_NS_coeff1_7_0_pos 0
+#define cfoe_NS_coeff1_7_0_len 8
+#define cfoe_NS_coeff1_7_0_lsb 0
+#define    p_cfoe_NS_coeff1_15_8    0xF401
+#define cfoe_NS_coeff1_15_8_pos 0
+#define cfoe_NS_coeff1_15_8_len 8
+#define cfoe_NS_coeff1_15_8_lsb 8
+#define    p_cfoe_NS_coeff1_23_16   0xF402
+#define cfoe_NS_coeff1_23_16_pos 0
+#define cfoe_NS_coeff1_23_16_len 8
+#define cfoe_NS_coeff1_23_16_lsb 16
+#define    p_cfoe_NS_coeff1_25_24   0xF403
+#define cfoe_NS_coeff1_25_24_pos 0
+#define cfoe_NS_coeff1_25_24_len 2
+#define cfoe_NS_coeff1_25_24_lsb 24
+#define    p_cfoe_NS_coeff2_7_0 0xF404
+#define cfoe_NS_coeff2_7_0_pos 0
+#define cfoe_NS_coeff2_7_0_len 8
+#define cfoe_NS_coeff2_7_0_lsb 0
+#define    p_cfoe_NS_coeff2_15_8    0xF405
+#define cfoe_NS_coeff2_15_8_pos 0
+#define cfoe_NS_coeff2_15_8_len 8
+#define cfoe_NS_coeff2_15_8_lsb 8
+#define    p_cfoe_NS_coeff2_23_16   0xF406
+#define cfoe_NS_coeff2_23_16_pos 0
+#define cfoe_NS_coeff2_23_16_len 8
+#define cfoe_NS_coeff2_23_16_lsb 16
+#define    p_cfoe_NS_coeff2_24  0xF407
+#define cfoe_NS_coeff2_24_pos 0
+#define cfoe_NS_coeff2_24_len 1
+#define cfoe_NS_coeff2_24_lsb 24
+#define    p_cfoe_lf_c1_7_0 0xF408
+#define cfoe_lf_c1_7_0_pos 0
+#define cfoe_lf_c1_7_0_len 8
+#define cfoe_lf_c1_7_0_lsb 0
+#define    p_cfoe_lf_c1_9_8 0xF409
+#define cfoe_lf_c1_9_8_pos 0
+#define cfoe_lf_c1_9_8_len 2
+#define cfoe_lf_c1_9_8_lsb 8
+#define    p_cfoe_lf_c2_7_0 0xF40A
+#define cfoe_lf_c2_7_0_pos 0
+#define cfoe_lf_c2_7_0_len 8
+#define cfoe_lf_c2_7_0_lsb 0
+#define    p_cfoe_lf_c2_9_8 0xF40B
+#define cfoe_lf_c2_9_8_pos 0
+#define cfoe_lf_c2_9_8_len 2
+#define cfoe_lf_c2_9_8_lsb 8
+#define    p_cfoe_ifod_7_0  0xF40C
+#define cfoe_ifod_7_0_pos 0
+#define cfoe_ifod_7_0_len 8
+#define cfoe_ifod_7_0_lsb 0
+#define    p_cfoe_ifod_10_8 0xF40D
+#define cfoe_ifod_10_8_pos 0
+#define cfoe_ifod_10_8_len 3
+#define cfoe_ifod_10_8_lsb 8
+#define    p_cfoe_Divg_ctr_th   0xF40E
+#define cfoe_Divg_ctr_th_pos 0
+#define cfoe_Divg_ctr_th_len 4
+#define cfoe_Divg_ctr_th_lsb 0
+#define    p_cfoe_FOT_divg_th   0xF40F
+#define cfoe_FOT_divg_th_pos 0
+#define cfoe_FOT_divg_th_len 8
+#define cfoe_FOT_divg_th_lsb 0
+#define    p_cfoe_FOT_cnvg_th   0xF410
+#define cfoe_FOT_cnvg_th_pos 0
+#define cfoe_FOT_cnvg_th_len 8
+#define cfoe_FOT_cnvg_th_lsb 0
+#define    p_reg_cfoe_offset_7_0    0xF411
+#define reg_cfoe_offset_7_0_pos 0
+#define reg_cfoe_offset_7_0_len 8
+#define reg_cfoe_offset_7_0_lsb 0
+#define    p_reg_cfoe_offset_10_8   0xF412
+#define reg_cfoe_offset_10_8_pos 0
+#define reg_cfoe_offset_10_8_len 3
+#define reg_cfoe_offset_10_8_lsb 8
+#define    p_reg_cfoe_ifoe_sign_corr    0xF413
+#define reg_cfoe_ifoe_sign_corr_pos 0
+#define reg_cfoe_ifoe_sign_corr_len 1
+#define reg_cfoe_ifoe_sign_corr_lsb 0
+#define    p_cfoe_FOT_pullin_cnt_clr    0xF414
+#define cfoe_FOT_pullin_cnt_clr_pos 0
+#define cfoe_FOT_pullin_cnt_clr_len 1
+#define cfoe_FOT_pullin_cnt_clr_lsb 0
+#define    p_cfoe_FOT_spec_inv  0xF415
+#define cfoe_FOT_spec_inv_pos 0
+#define cfoe_FOT_spec_inv_len 1
+#define cfoe_FOT_spec_inv_lsb 0
+#define    p_cfoe_FOT_pullin_ctr_th 0xF416
+#define cfoe_FOT_pullin_ctr_th_pos 0
+#define cfoe_FOT_pullin_ctr_th_len 4
+#define cfoe_FOT_pullin_ctr_th_lsb 0
+#define    p_cfoe_FOT_sf_ctr_th 0xF417
+#define cfoe_FOT_sf_ctr_th_pos 0
+#define cfoe_FOT_sf_ctr_th_len 4
+#define cfoe_FOT_sf_ctr_th_lsb 0
+#define    p_cfoe_FOT_pullin_th 0xF418
+#define cfoe_FOT_pullin_th_pos 0
+#define cfoe_FOT_pullin_th_len 8
+#define cfoe_FOT_pullin_th_lsb 0
+#define    p_cfoe_FOT_kalman_cnt    0xF419
+#define cfoe_FOT_kalman_cnt_pos 0
+#define cfoe_FOT_kalman_cnt_len 4
+#define cfoe_FOT_kalman_cnt_lsb 0
+#define    p_cfoe_FOT_fsm_info  0xF41A
+#define cfoe_FOT_fsm_info_pos 0
+#define cfoe_FOT_fsm_info_len 4
+#define cfoe_FOT_fsm_info_lsb 0
+#define    r_cfoe_FOT_pullin_cnt    0xF41B
+#define cfoe_FOT_pullin_cnt_pos 0
+#define cfoe_FOT_pullin_cnt_len 4
+#define cfoe_FOT_pullin_cnt_lsb 0
+#define    r_cfoe_FOT_sf_cnt    0xF41C
+#define cfoe_FOT_sf_cnt_pos 0
+#define cfoe_FOT_sf_cnt_len 4
+#define cfoe_FOT_sf_cnt_lsb 0
+#define    r_reg_r_cfoe_ifoe_ifo_metric 0xF41D
+#define reg_r_cfoe_ifoe_ifo_metric_pos 0
+#define reg_r_cfoe_ifoe_ifo_metric_len 8
+#define reg_r_cfoe_ifoe_ifo_metric_lsb 0
+#define    r_reg_r_cfoe_ifoe_cos2num_7_0    0xF41E
+#define reg_r_cfoe_ifoe_cos2num_7_0_pos 0
+#define reg_r_cfoe_ifoe_cos2num_7_0_len 8
+#define reg_r_cfoe_ifoe_cos2num_7_0_lsb 0
+#define    r_reg_r_cfoe_ifoe_cos2num_15_8   0xF41F
+#define reg_r_cfoe_ifoe_cos2num_15_8_pos 0
+#define reg_r_cfoe_ifoe_cos2num_15_8_len 8
+#define reg_r_cfoe_ifoe_cos2num_15_8_lsb 8
+#define    r_reg_r_cfoe_ifoe_cos2num_19_16  0xF420
+#define reg_r_cfoe_ifoe_cos2num_19_16_pos 0
+#define reg_r_cfoe_ifoe_cos2num_19_16_len 4
+#define reg_r_cfoe_ifoe_cos2num_19_16_lsb 16
+#define    p_ste_Nu 0xF460
+#define ste_Nu_pos 0
+#define ste_Nu_len 3
+#define ste_Nu_lsb 0
+#define    p_ste_GI 0xF461
+#define ste_GI_pos 0
+#define ste_GI_len 3
+#define ste_GI_lsb 0
+#define    p_ste_symbol_num 0xF463
+#define ste_symbol_num_pos 0
+#define ste_symbol_num_len 3
+#define ste_symbol_num_lsb 0
+#define    p_ste_sample_num 0xF464
+#define ste_sample_num_pos 0
+#define ste_sample_num_len 2
+#define ste_sample_num_lsb 0
+#define    p_ste_symbol_num_4K  0xF465
+#define ste_symbol_num_4K_pos 0
+#define ste_symbol_num_4K_len 3
+#define ste_symbol_num_4K_lsb 0
+#define    p_ste_FFT_offset_7_0 0xF466
+#define ste_FFT_offset_7_0_pos 0
+#define ste_FFT_offset_7_0_len 8
+#define ste_FFT_offset_7_0_lsb 0
+#define    p_ste_FFT_offset_13_8    0xF467
+#define ste_FFT_offset_13_8_pos 0
+#define ste_FFT_offset_13_8_len 6
+#define ste_FFT_offset_13_8_lsb 8
+#define    p_ste_sample_num_4K  0xF468
+#define ste_sample_num_4K_pos 0
+#define ste_sample_num_4K_len 2
+#define ste_sample_num_4K_lsb 0
+#define    p_ste_adv_start_7_0  0xF469
+#define ste_adv_start_7_0_pos 0
+#define ste_adv_start_7_0_len 8
+#define ste_adv_start_7_0_lsb 0
+#define    p_ste_adv_start_10_8 0xF46A
+#define ste_adv_start_10_8_pos 0
+#define ste_adv_start_10_8_len 3
+#define ste_adv_start_10_8_lsb 8
+#define    p_ste_symbol_num_8K  0xF46B
+#define ste_symbol_num_8K_pos 0
+#define ste_symbol_num_8K_len 3
+#define ste_symbol_num_8K_lsb 0
+#define    p_ste_sample_num_8K  0xF46C
+#define ste_sample_num_8K_pos 0
+#define ste_sample_num_8K_len 2
+#define ste_sample_num_8K_lsb 0
+#define    p_ste_adv_stop   0xF46D
+#define ste_adv_stop_pos 0
+#define ste_adv_stop_len 8
+#define ste_adv_stop_lsb 0
+#define    r_ste_P_value_7_0    0xF46E
+#define ste_P_value_7_0_pos 0
+#define ste_P_value_7_0_len 8
+#define ste_P_value_7_0_lsb 0
+#define    r_ste_P_value_10_8   0xF46F
+#define ste_P_value_10_8_pos 0
+#define ste_P_value_10_8_len 3
+#define ste_P_value_10_8_lsb 8
+#define    p_reg_ste_tstmod 0xF470
+#define reg_ste_tstmod_pos 0
+#define reg_ste_tstmod_len 1
+#define reg_ste_tstmod_lsb 0
+#define    p_reg_ste_buf_en 0xF471
+#define reg_ste_buf_en_pos 0
+#define reg_ste_buf_en_len 1
+#define reg_ste_buf_en_lsb 0
+#define    r_ste_M_value_7_0    0xF472
+#define ste_M_value_7_0_pos 0
+#define ste_M_value_7_0_len 8
+#define ste_M_value_7_0_lsb 0
+#define    r_ste_M_value_10_8   0xF473
+#define ste_M_value_10_8_pos 0
+#define ste_M_value_10_8_len 3
+#define ste_M_value_10_8_lsb 8
+#define    r_ste_H1 0xF474
+#define ste_H1_pos 0
+#define ste_H1_len 7
+#define ste_H1_lsb 0
+#define    r_ste_H2 0xF475
+#define ste_H2_pos 0
+#define ste_H2_len 7
+#define ste_H2_lsb 0
+#define    r_ste_H3 0xF476
+#define ste_H3_pos 0
+#define ste_H3_len 7
+#define ste_H3_lsb 0
+#define    r_ste_H4 0xF477
+#define ste_H4_pos 0
+#define ste_H4_len 7
+#define ste_H4_lsb 0
+#define    r_ste_Corr_value_I_7_0   0xF478
+#define ste_Corr_value_I_7_0_pos 0
+#define ste_Corr_value_I_7_0_len 8
+#define ste_Corr_value_I_7_0_lsb 0
+#define    r_ste_Corr_value_I_15_8  0xF479
+#define ste_Corr_value_I_15_8_pos 0
+#define ste_Corr_value_I_15_8_len 8
+#define ste_Corr_value_I_15_8_lsb 8
+#define    r_ste_Corr_value_I_23_16 0xF47A
+#define ste_Corr_value_I_23_16_pos 0
+#define ste_Corr_value_I_23_16_len 8
+#define ste_Corr_value_I_23_16_lsb 16
+#define    r_ste_Corr_value_I_27_24 0xF47B
+#define ste_Corr_value_I_27_24_pos 0
+#define ste_Corr_value_I_27_24_len 4
+#define ste_Corr_value_I_27_24_lsb 24
+#define    r_ste_Corr_value_Q_7_0   0xF47C
+#define ste_Corr_value_Q_7_0_pos 0
+#define ste_Corr_value_Q_7_0_len 8
+#define ste_Corr_value_Q_7_0_lsb 0
+#define    r_ste_Corr_value_Q_15_8  0xF47D
+#define ste_Corr_value_Q_15_8_pos 0
+#define ste_Corr_value_Q_15_8_len 8
+#define ste_Corr_value_Q_15_8_lsb 8
+#define    r_ste_Corr_value_Q_23_16 0xF47E
+#define ste_Corr_value_Q_23_16_pos 0
+#define ste_Corr_value_Q_23_16_len 8
+#define ste_Corr_value_Q_23_16_lsb 16
+#define    r_ste_Corr_value_Q_27_24 0xF47F
+#define ste_Corr_value_Q_27_24_pos 0
+#define ste_Corr_value_Q_27_24_len 4
+#define ste_Corr_value_Q_27_24_lsb 24
+#define    r_ste_J_num_7_0  0xF480
+#define ste_J_num_7_0_pos 0
+#define ste_J_num_7_0_len 8
+#define ste_J_num_7_0_lsb 0
+#define    r_ste_J_num_15_8 0xF481
+#define ste_J_num_15_8_pos 0
+#define ste_J_num_15_8_len 8
+#define ste_J_num_15_8_lsb 8
+#define    r_ste_J_num_23_16    0xF482
+#define ste_J_num_23_16_pos 0
+#define ste_J_num_23_16_len 8
+#define ste_J_num_23_16_lsb 16
+#define    r_ste_J_num_31_24    0xF483
+#define ste_J_num_31_24_pos 0
+#define ste_J_num_31_24_len 8
+#define ste_J_num_31_24_lsb 24
+#define    r_ste_J_den_7_0  0xF484
+#define ste_J_den_7_0_pos 0
+#define ste_J_den_7_0_len 8
+#define ste_J_den_7_0_lsb 0
+#define    r_ste_J_den_15_8 0xF485
+#define ste_J_den_15_8_pos 0
+#define ste_J_den_15_8_len 8
+#define ste_J_den_15_8_lsb 8
+#define    r_ste_J_den_18_16    0xF486
+#define ste_J_den_18_16_pos 0
+#define ste_J_den_18_16_len 3
+#define ste_J_den_18_16_lsb 16
+#define    r_ste_Beacon_Indicator   0xF488
+#define ste_Beacon_Indicator_pos 0
+#define ste_Beacon_Indicator_len 1
+#define ste_Beacon_Indicator_lsb 0
+#define    p_ste_got_sntc_bcn   0xF48B
+#define ste_got_sntc_bcn_pos 0
+#define ste_got_sntc_bcn_len 1
+#define ste_got_sntc_bcn_lsb 0
+#define    r_tpsd_Frame_Num 0xF4C0
+#define tpsd_Frame_Num_pos 0
+#define tpsd_Frame_Num_len 2
+#define tpsd_Frame_Num_lsb 0
+#define    r_tpsd_Constel   0xF4C1
+#define tpsd_Constel_pos 0
+#define tpsd_Constel_len 2
+#define tpsd_Constel_lsb 0
+#define    r_tpsd_GI    0xF4C2
+#define tpsd_GI_pos 0
+#define tpsd_GI_len 2
+#define tpsd_GI_lsb 0
+#define    r_tpsd_Mode  0xF4C3
+#define tpsd_Mode_pos 0
+#define tpsd_Mode_len 2
+#define tpsd_Mode_lsb 0
+#define    r_tpsd_CR_HP 0xF4C4
+#define tpsd_CR_HP_pos 0
+#define tpsd_CR_HP_len 3
+#define tpsd_CR_HP_lsb 0
+#define    r_tpsd_CR_LP 0xF4C5
+#define tpsd_CR_LP_pos 0
+#define tpsd_CR_LP_len 3
+#define tpsd_CR_LP_lsb 0
+#define    r_tpsd_Hie   0xF4C6
+#define tpsd_Hie_pos 0
+#define tpsd_Hie_len 3
+#define tpsd_Hie_lsb 0
+#define    r_tpsd_Res_Bits  0xF4C7
+#define tpsd_Res_Bits_pos 0
+#define tpsd_Res_Bits_len 5
+#define tpsd_Res_Bits_lsb 0
+#define    r_tpsd_Res_Bits_0    0xF4C8
+#define tpsd_Res_Bits_0_pos 0
+#define tpsd_Res_Bits_0_len 1
+#define tpsd_Res_Bits_0_lsb 0
+#define    r_tpsd_LengthInd 0xF4C9
+#define tpsd_LengthInd_pos 0
+#define tpsd_LengthInd_len 6
+#define tpsd_LengthInd_lsb 0
+#define    r_tpsd_Cell_Id_7_0   0xF4CA
+#define tpsd_Cell_Id_7_0_pos 0
+#define tpsd_Cell_Id_7_0_len 8
+#define tpsd_Cell_Id_7_0_lsb 0
+#define    r_tpsd_Cell_Id_15_8  0xF4CB
+#define tpsd_Cell_Id_15_8_pos 0
+#define tpsd_Cell_Id_15_8_len 8
+#define tpsd_Cell_Id_15_8_lsb 0
+#define    r_tpsd_use_InDepthInt    0xF4CC
+#define tpsd_use_InDepthInt_pos 0
+#define tpsd_use_InDepthInt_len 1
+#define tpsd_use_InDepthInt_lsb 0
+#define    r_tpsd_use_TimeSlicing_HP    0xF4CD
+#define tpsd_use_TimeSlicing_HP_pos 0
+#define tpsd_use_TimeSlicing_HP_len 1
+#define tpsd_use_TimeSlicing_HP_lsb 0
+#define    r_tpsd_use_mpe_fec_HP    0xF4CE
+#define tpsd_use_mpe_fec_HP_pos 0
+#define tpsd_use_mpe_fec_HP_len 1
+#define tpsd_use_mpe_fec_HP_lsb 0
+#define    r_tpsd_use_TimeSlicing_LP    0xF4CF
+#define tpsd_use_TimeSlicing_LP_pos 0
+#define tpsd_use_TimeSlicing_LP_len 1
+#define tpsd_use_TimeSlicing_LP_lsb 0
+#define    r_tpsd_use_mpe_fec_LP    0xF4D0
+#define tpsd_use_mpe_fec_LP_pos 0
+#define tpsd_use_mpe_fec_LP_len 1
+#define tpsd_use_mpe_fec_LP_lsb 0
+#define    r_tpsd_leng23_ind_return 0xF4D1
+#define tpsd_leng23_ind_return_pos 0
+#define tpsd_leng23_ind_return_len 1
+#define tpsd_leng23_ind_return_lsb 0
+#define    p_reg_fft_re_exp 0xF500
+#define reg_fft_re_exp_pos 0
+#define reg_fft_re_exp_len 4
+#define reg_fft_re_exp_lsb 0
+#define    p_reg_fft_re_mts 0xF501
+#define reg_fft_re_mts_pos 0
+#define reg_fft_re_mts_len 8
+#define reg_fft_re_mts_lsb 0
+#define    p_reg_fft_im_exp 0xF502
+#define reg_fft_im_exp_pos 0
+#define reg_fft_im_exp_len 4
+#define reg_fft_im_exp_lsb 0
+#define    p_reg_fft_im_mts 0xF503
+#define reg_fft_im_mts_pos 0
+#define reg_fft_im_mts_len 8
+#define reg_fft_im_mts_lsb 0
+#define    p_reg_fft_conjugate  0xF504
+#define reg_fft_conjugate_pos 0
+#define reg_fft_conjugate_len 1
+#define reg_fft_conjugate_lsb 0
+#define    p_reg_fft_power_en   0xF505
+#define reg_fft_power_en_pos 0
+#define reg_fft_power_en_len 1
+#define reg_fft_power_en_lsb 0
+#define    p_reg_fft_power_factor   0xF506
+#define reg_fft_power_factor_pos 0
+#define reg_fft_power_factor_len 6
+#define reg_fft_power_factor_lsb 0
+#define    p_reg_fft_power_in   0xF507
+#define reg_fft_power_in_pos 0
+#define reg_fft_power_in_len 8
+#define reg_fft_power_in_lsb 0
+#define    p_reg_fft_mask_from0_7_0 0xF508
+#define reg_fft_mask_from0_7_0_pos 0
+#define reg_fft_mask_from0_7_0_len 8
+#define reg_fft_mask_from0_7_0_lsb 0
+#define    p_reg_fft_mask_from0_12_8    0xF509
+#define reg_fft_mask_from0_12_8_pos 0
+#define reg_fft_mask_from0_12_8_len 5
+#define reg_fft_mask_from0_12_8_lsb 8
+#define    p_reg_fft_mask_to0_7_0   0xF50A
+#define reg_fft_mask_to0_7_0_pos 0
+#define reg_fft_mask_to0_7_0_len 8
+#define reg_fft_mask_to0_7_0_lsb 0
+#define    p_reg_fft_mask_to0_12_8  0xF50B
+#define reg_fft_mask_to0_12_8_pos 0
+#define reg_fft_mask_to0_12_8_len 5
+#define reg_fft_mask_to0_12_8_lsb 8
+#define    p_reg_fft_mask_from1_7_0 0xF50C
+#define reg_fft_mask_from1_7_0_pos 0
+#define reg_fft_mask_from1_7_0_len 8
+#define reg_fft_mask_from1_7_0_lsb 0
+#define    p_reg_fft_mask_from1_12_8    0xF50D
+#define reg_fft_mask_from1_12_8_pos 0
+#define reg_fft_mask_from1_12_8_len 5
+#define reg_fft_mask_from1_12_8_lsb 8
+#define    p_reg_fft_mask_to1_7_0   0xF50E
+#define reg_fft_mask_to1_7_0_pos 0
+#define reg_fft_mask_to1_7_0_len 8
+#define reg_fft_mask_to1_7_0_lsb 0
+#define    p_reg_fft_mask_to1_12_8  0xF50F
+#define reg_fft_mask_to1_12_8_pos 0
+#define reg_fft_mask_to1_12_8_len 5
+#define reg_fft_mask_to1_12_8_lsb 8
+#define    p_reg_fft_mask_from2_7_0 0xF510
+#define reg_fft_mask_from2_7_0_pos 0
+#define reg_fft_mask_from2_7_0_len 8
+#define reg_fft_mask_from2_7_0_lsb 0
+#define    p_reg_fft_mask_from2_12_8    0xF511
+#define reg_fft_mask_from2_12_8_pos 0
+#define reg_fft_mask_from2_12_8_len 5
+#define reg_fft_mask_from2_12_8_lsb 8
+#define    p_reg_fft_mask_to2_7_0   0xF512
+#define reg_fft_mask_to2_7_0_pos 0
+#define reg_fft_mask_to2_7_0_len 8
+#define reg_fft_mask_to2_7_0_lsb 0
+#define    p_reg_fft_mask_to2_12_8  0xF513
+#define reg_fft_mask_to2_12_8_pos 0
+#define reg_fft_mask_to2_12_8_len 5
+#define reg_fft_mask_to2_12_8_lsb 8
+#define    p_reg_fft_mask_from3_7_0 0xF514
+#define reg_fft_mask_from3_7_0_pos 0
+#define reg_fft_mask_from3_7_0_len 8
+#define reg_fft_mask_from3_7_0_lsb 0
+#define    p_reg_fft_mask_from3_12_8    0xF515
+#define reg_fft_mask_from3_12_8_pos 0
+#define reg_fft_mask_from3_12_8_len 5
+#define reg_fft_mask_from3_12_8_lsb 8
+#define    p_reg_fft_mask_to3_7_0   0xF516
+#define reg_fft_mask_to3_7_0_pos 0
+#define reg_fft_mask_to3_7_0_len 8
+#define reg_fft_mask_to3_7_0_lsb 0
+#define    p_reg_fft_mask_to3_12_8  0xF517
+#define reg_fft_mask_to3_12_8_pos 0
+#define reg_fft_mask_to3_12_8_len 5
+#define reg_fft_mask_to3_12_8_lsb 8
+#define    r_fd_sntc_frame_num  0xF518
+#define fd_sntc_frame_num_pos 0
+#define fd_sntc_frame_num_len 2
+#define fd_sntc_frame_num_lsb 0
+#define    r_fd_sntc_symbol_count   0xF519
+#define fd_sntc_symbol_count_pos 0
+#define fd_sntc_symbol_count_len 7
+#define fd_sntc_symbol_count_lsb 0
+#define    p_reg_sntc_cnt_lo    0xF51A
+#define reg_sntc_cnt_lo_pos 0
+#define reg_sntc_cnt_lo_len 8
+#define reg_sntc_cnt_lo_lsb 0
+#define    p_reg_sntc_cnt_hi    0xF51B
+#define reg_sntc_cnt_hi_pos 0
+#define reg_sntc_cnt_hi_len 7
+#define reg_sntc_cnt_hi_lsb 0
+#define    p_reg_sntc_fft_in    0xF51C
+#define reg_sntc_fft_in_pos 0
+#define reg_sntc_fft_in_len 1
+#define reg_sntc_fft_in_lsb 0
+#define    r_fd_sntc_en 0xF51D
+#define fd_sntc_en_pos 0
+#define fd_sntc_en_len 1
+#define fd_sntc_en_lsb 0
+#define    p_reg_sntc_x2    0xF51E
+#define reg_sntc_x2_pos 0
+#define reg_sntc_x2_len 1
+#define reg_sntc_x2_lsb 0
+#define    p_reg_cge_en_7_0 0xF51F
+#define reg_cge_en_7_0_pos 0
+#define reg_cge_en_7_0_len 8
+#define reg_cge_en_7_0_lsb 0
+#define    p_reg_cge_en_15_8    0xF520
+#define reg_cge_en_15_8_pos 0
+#define reg_cge_en_15_8_len 8
+#define reg_cge_en_15_8_lsb 8
+#define    p_reg_cge_en_23_16   0xF521
+#define reg_cge_en_23_16_pos 0
+#define reg_cge_en_23_16_len 8
+#define reg_cge_en_23_16_lsb 16
+#define    p_reg_cge_en_31_24   0xF522
+#define reg_cge_en_31_24_pos 0
+#define reg_cge_en_31_24_len 8
+#define reg_cge_en_31_24_lsb 24
+#define    p_reg_cge_en_39_32   0xF523
+#define reg_cge_en_39_32_pos 0
+#define reg_cge_en_39_32_len 8
+#define reg_cge_en_39_32_lsb 32
+#define    p_reg_cge_en_43_40   0xF524
+#define reg_cge_en_43_40_pos 0
+#define reg_cge_en_43_40_len 4
+#define reg_cge_en_43_40_lsb 40
+#define    p_reg_fft_sat_en 0xF525
+#define reg_fft_sat_en_pos 0
+#define reg_fft_sat_en_len 1
+#define reg_fft_sat_en_lsb 0
+#define    p_reg_fft_sat_count_clr  0xF526
+#define reg_fft_sat_count_clr_pos 0
+#define reg_fft_sat_count_clr_len 1
+#define reg_fft_sat_count_clr_lsb 0
+#define    p_reg_fft_rescale_round  0xF527
+#define reg_fft_rescale_round_pos 0
+#define reg_fft_rescale_round_len 1
+#define reg_fft_rescale_round_lsb 0
+#define    r_reg_fft_sat_count_12_7_0   0xF528
+#define reg_fft_sat_count_12_7_0_pos 0
+#define reg_fft_sat_count_12_7_0_len 8
+#define reg_fft_sat_count_12_7_0_lsb 0
+#define    r_reg_fft_sat_count_12_15_8  0xF529
+#define reg_fft_sat_count_12_15_8_pos 0
+#define reg_fft_sat_count_12_15_8_len 8
+#define reg_fft_sat_count_12_15_8_lsb 8
+#define    r_reg_fft_sat_count_10_7_0   0xF52A
+#define reg_fft_sat_count_10_7_0_pos 0
+#define reg_fft_sat_count_10_7_0_len 8
+#define reg_fft_sat_count_10_7_0_lsb 0
+#define    r_reg_fft_sat_count_10_15_8  0xF52B
+#define reg_fft_sat_count_10_15_8_pos 0
+#define reg_fft_sat_count_10_15_8_len 8
+#define reg_fft_sat_count_10_15_8_lsb 8
+#define    p_reg_fft_capture_idx_7_0    0xF52C
+#define reg_fft_capture_idx_7_0_pos 0
+#define reg_fft_capture_idx_7_0_len 8
+#define reg_fft_capture_idx_7_0_lsb 0
+#define    p_reg_fft_capture_idx_12_8   0xF52D
+#define reg_fft_capture_idx_12_8_pos 0
+#define reg_fft_capture_idx_12_8_len 5
+#define reg_fft_capture_idx_12_8_lsb 8
+#define    p_reg_fft_capture    0xF52E
+#define reg_fft_capture_pos 0
+#define reg_fft_capture_len 1
+#define reg_fft_capture_lsb 0
+#define    p_reg_gp_trigger_fd  0xF52F
+#define reg_gp_trigger_fd_pos 0
+#define reg_gp_trigger_fd_len 1
+#define reg_gp_trigger_fd_lsb 0
+#define    p_reg_trigger_sel_fd 0xF530
+#define reg_trigger_sel_fd_pos 0
+#define reg_trigger_sel_fd_len 2
+#define reg_trigger_sel_fd_lsb 0
+#define    p_reg_trigger_module_sel_fd  0xF531
+#define reg_trigger_module_sel_fd_pos 0
+#define reg_trigger_module_sel_fd_len 6
+#define reg_trigger_module_sel_fd_lsb 0
+#define    p_reg_trigger_set_sel_fd 0xF532
+#define reg_trigger_set_sel_fd_pos 0
+#define reg_trigger_set_sel_fd_len 6
+#define reg_trigger_set_sel_fd_lsb 0
+#define    r_reg_fft_idx_pre_max_7_0    0xF533
+#define reg_fft_idx_pre_max_7_0_pos 0
+#define reg_fft_idx_pre_max_7_0_len 8
+#define reg_fft_idx_pre_max_7_0_lsb 0
+#define    r_reg_fft_idx_pre_max_12_8   0xF534
+#define reg_fft_idx_pre_max_12_8_pos 0
+#define reg_fft_idx_pre_max_12_8_len 5
+#define reg_fft_idx_pre_max_12_8_lsb 8
+#define    r_reg_fft_crc    0xF535
+#define reg_fft_crc_pos 0
+#define reg_fft_crc_len 8
+#define reg_fft_crc_lsb 0
+#define    p_fd_fft_shift_max   0xF536
+#define fd_fft_shift_max_pos 0
+#define fd_fft_shift_max_len 4
+#define fd_fft_shift_max_lsb 0
+#define    p_fd_fft_frame_num   0xF537
+#define fd_fft_frame_num_pos 0
+#define fd_fft_frame_num_len 2
+#define fd_fft_frame_num_lsb 0
+#define    p_fd_fft_symbol_count    0xF538
+#define fd_fft_symbol_count_pos 0
+#define fd_fft_symbol_count_len 7
+#define fd_fft_symbol_count_lsb 0
+#define    r_reg_fft_idx_max_7_0    0xF539
+#define reg_fft_idx_max_7_0_pos 0
+#define reg_fft_idx_max_7_0_len 8
+#define reg_fft_idx_max_7_0_lsb 0
+#define    r_reg_fft_idx_max_12_8   0xF53A
+#define reg_fft_idx_max_12_8_pos 0
+#define reg_fft_idx_max_12_8_len 5
+#define reg_fft_idx_max_12_8_lsb 8
+#define    p_reg_fft_rotate_en  0xF53B
+#define reg_fft_rotate_en_pos 0
+#define reg_fft_rotate_en_len 1
+#define reg_fft_rotate_en_lsb 0
+#define    p_reg_fft_rotate_base_7_0    0xF53C
+#define reg_fft_rotate_base_7_0_pos 0
+#define reg_fft_rotate_base_7_0_len 8
+#define reg_fft_rotate_base_7_0_lsb 0
+#define    p_reg_fft_rotate_base_12_8   0xF53D
+#define reg_fft_rotate_base_12_8_pos 0
+#define reg_fft_rotate_base_12_8_len 5
+#define reg_fft_rotate_base_12_8_lsb 8
+#define    r_fd_fpcc_cp_corr_signn  0xF53E
+#define fd_fpcc_cp_corr_signn_pos 0
+#define fd_fpcc_cp_corr_signn_len 8
+#define fd_fpcc_cp_corr_signn_lsb 0
+#define    p_reg_feq_s1 0xF53F
+#define reg_feq_s1_pos 0
+#define reg_feq_s1_len 5
+#define reg_feq_s1_lsb 0
+#define    p_reg_feq_sat_ind    0xF540
+#define reg_feq_sat_ind_pos 0
+#define reg_feq_sat_ind_len 3
+#define reg_feq_sat_ind_lsb 0
+#define    p_reg_p_csi_cal_en   0xF541
+#define reg_p_csi_cal_en_pos 0
+#define reg_p_csi_cal_en_len 1
+#define reg_p_csi_cal_en_lsb 0
+#define    p_reg_p_csi_ar_mode  0xF542
+#define reg_p_csi_ar_mode_pos 0
+#define reg_p_csi_ar_mode_len 2
+#define reg_p_csi_ar_mode_lsb 0
+#define    p_reg_p_csi_accu_sym_num 0xF543
+#define reg_p_csi_accu_sym_num_pos 0
+#define reg_p_csi_accu_sym_num_len 8
+#define reg_p_csi_accu_sym_num_lsb 0
+#define    p_reg_p_csi_eh2_shift_thr    0xF544
+#define reg_p_csi_eh2_shift_thr_pos 0
+#define reg_p_csi_eh2_shift_thr_len 4
+#define reg_p_csi_eh2_shift_thr_lsb 0
+#define    p_reg_p_feq_protect_eh2_shift_thr    0xF545
+#define reg_p_feq_protect_eh2_shift_thr_pos 0
+#define reg_p_feq_protect_eh2_shift_thr_len 4
+#define reg_p_feq_protect_eh2_shift_thr_lsb 0
+#define    p_reg_p_csi_error_accu_s1    0xF546
+#define reg_p_csi_error_accu_s1_pos 0
+#define reg_p_csi_error_accu_s1_len 6
+#define reg_p_csi_error_accu_s1_lsb 0
+#define    p_reg_p_csi_shift2   0xF547
+#define reg_p_csi_shift2_pos 0
+#define reg_p_csi_shift2_len 4
+#define reg_p_csi_shift2_lsb 0
+#define    p_reg_p_csi_mul2 0xF548
+#define reg_p_csi_mul2_pos 0
+#define reg_p_csi_mul2_len 8
+#define reg_p_csi_mul2_lsb 0
+#define    p_reg_p_csi_level2_7_0   0xF549
+#define reg_p_csi_level2_7_0_pos 0
+#define reg_p_csi_level2_7_0_len 8
+#define reg_p_csi_level2_7_0_lsb 0
+#define    p_reg_p_csi_level2_8 0xF54A
+#define reg_p_csi_level2_8_pos 0
+#define reg_p_csi_level2_8_len 1
+#define reg_p_csi_level2_8_lsb 8
+#define    p_reg_p_feq_protect_ratio    0xF54B
+#define reg_p_feq_protect_ratio_pos 0
+#define reg_p_feq_protect_ratio_len 8
+#define reg_p_feq_protect_ratio_lsb 0
+#define    r_reg_csi_rdy    0xF54C
+#define reg_csi_rdy_pos 0
+#define reg_csi_rdy_len 1
+#define reg_csi_rdy_lsb 0
+#define    p_reg_p_feq_h2protect_en 0xF54D
+#define reg_p_feq_h2protect_en_pos 0
+#define reg_p_feq_h2protect_en_len 1
+#define reg_p_feq_h2protect_en_lsb 0
+#define    r_reg_tpsd_lock_f0   0xF54E
+#define reg_tpsd_lock_f0_pos 0
+#define reg_tpsd_lock_f0_len 1
+#define reg_tpsd_lock_f0_lsb 0
+#define    r_reg_tpsd_lock_f1   0xF54F
+#define reg_tpsd_lock_f1_pos 0
+#define reg_tpsd_lock_f1_len 1
+#define reg_tpsd_lock_f1_lsb 0
+#define    p_reg_p_csi_sp_idx_7_0   0xF550
+#define reg_p_csi_sp_idx_7_0_pos 0
+#define reg_p_csi_sp_idx_7_0_len 8
+#define reg_p_csi_sp_idx_7_0_lsb 0
+#define    p_reg_p_csi_sp_idx_11_8  0xF551
+#define reg_p_csi_sp_idx_11_8_pos 0
+#define reg_p_csi_sp_idx_11_8_len 4
+#define reg_p_csi_sp_idx_11_8_lsb 8
+#define    p_fd_fpcc_cp_corr_tone_th    0xF552
+#define fd_fpcc_cp_corr_tone_th_pos 0
+#define fd_fpcc_cp_corr_tone_th_len 6
+#define fd_fpcc_cp_corr_tone_th_lsb 0
+#define    p_fd_fpcc_cp_corr_symbol_log_th  0xF553
+#define fd_fpcc_cp_corr_symbol_log_th_pos 0
+#define fd_fpcc_cp_corr_symbol_log_th_len 4
+#define fd_fpcc_cp_corr_symbol_log_th_lsb 0
+#define    p_fd_fpcc_cp_corr_int    0xF554
+#define fd_fpcc_cp_corr_int_pos 0
+#define fd_fpcc_cp_corr_int_len 1
+#define fd_fpcc_cp_corr_int_lsb 0
+#define    p_reg_fpcc_cp_memidx 0xF555
+#define reg_fpcc_cp_memidx_pos 0
+#define reg_fpcc_cp_memidx_len 8
+#define reg_fpcc_cp_memidx_lsb 0
+#define    p_reg_fpcc_cpmask_en 0xF556
+#define reg_fpcc_cpmask_en_pos 0
+#define reg_fpcc_cpmask_en_len 1
+#define reg_fpcc_cpmask_en_lsb 0
+#define    p_reg_fpcc_cp_grpidx 0xF557
+#define reg_fpcc_cp_grpidx_pos 0
+#define reg_fpcc_cp_grpidx_len 5
+#define reg_fpcc_cp_grpidx_lsb 0
+#define    r_reg_fpcc_cp_sts    0xF558
+#define reg_fpcc_cp_sts_pos 0
+#define reg_fpcc_cp_sts_len 1
+#define reg_fpcc_cp_sts_lsb 0
+#define    p_reg_sfoe_ns_7_0    0xF559
+#define reg_sfoe_ns_7_0_pos 0
+#define reg_sfoe_ns_7_0_len 8
+#define reg_sfoe_ns_7_0_lsb 0
+#define    p_reg_sfoe_ns_14_8   0xF55A
+#define reg_sfoe_ns_14_8_pos 0
+#define reg_sfoe_ns_14_8_len 7
+#define reg_sfoe_ns_14_8_lsb 8
+#define    p_reg_sfoe_c1_7_0    0xF55B
+#define reg_sfoe_c1_7_0_pos 0
+#define reg_sfoe_c1_7_0_len 8
+#define reg_sfoe_c1_7_0_lsb 0
+#define    p_reg_sfoe_c1_9_8    0xF55C
+#define reg_sfoe_c1_9_8_pos 0
+#define reg_sfoe_c1_9_8_len 2
+#define reg_sfoe_c1_9_8_lsb 8
+#define    p_reg_sfoe_c2_7_0    0xF55D
+#define reg_sfoe_c2_7_0_pos 0
+#define reg_sfoe_c2_7_0_len 8
+#define reg_sfoe_c2_7_0_lsb 0
+#define    p_reg_sfoe_c2_9_8    0xF55E
+#define reg_sfoe_c2_9_8_pos 0
+#define reg_sfoe_c2_9_8_len 2
+#define reg_sfoe_c2_9_8_lsb 8
+#define    p_reg_sfoe_lm_counter_th 0xF55F
+#define reg_sfoe_lm_counter_th_pos 0
+#define reg_sfoe_lm_counter_th_len 4
+#define reg_sfoe_lm_counter_th_lsb 0
+#define    p_reg_sfoe_spec_inv  0xF560
+#define reg_sfoe_spec_inv_pos 0
+#define reg_sfoe_spec_inv_len 1
+#define reg_sfoe_spec_inv_lsb 0
+#define    p_reg_sfoe_convg_th  0xF561
+#define reg_sfoe_convg_th_pos 0
+#define reg_sfoe_convg_th_len 8
+#define reg_sfoe_convg_th_lsb 0
+#define    p_reg_sfoe_divg_th   0xF562
+#define reg_sfoe_divg_th_pos 0
+#define reg_sfoe_divg_th_len 8
+#define reg_sfoe_divg_th_lsb 0
+#define    p_reg_sfoe_pullin_ctr_th 0xF563
+#define reg_sfoe_pullin_ctr_th_pos 0
+#define reg_sfoe_pullin_ctr_th_len 4
+#define reg_sfoe_pullin_ctr_th_lsb 0
+#define    p_reg_sfoe_sf_ctr_th 0xF564
+#define reg_sfoe_sf_ctr_th_pos 0
+#define reg_sfoe_sf_ctr_th_len 4
+#define reg_sfoe_sf_ctr_th_lsb 0
+#define    p_reg_sfoe_pullin_th 0xF565
+#define reg_sfoe_pullin_th_pos 0
+#define reg_sfoe_pullin_th_len 8
+#define reg_sfoe_pullin_th_lsb 0
+#define    p_reg_sfoe_kalman_cnt    0xF566
+#define reg_sfoe_kalman_cnt_pos 0
+#define reg_sfoe_kalman_cnt_len 4
+#define reg_sfoe_kalman_cnt_lsb 0
+#define    p_reg_sfoe_fsm_info  0xF567
+#define reg_sfoe_fsm_info_pos 0
+#define reg_sfoe_fsm_info_len 4
+#define reg_sfoe_fsm_info_lsb 0
+#define    r_reg_sfoe_pullin_cnt    0xF568
+#define reg_sfoe_pullin_cnt_pos 0
+#define reg_sfoe_pullin_cnt_len 4
+#define reg_sfoe_pullin_cnt_lsb 0
+#define    r_reg_sfoe_sf_cnt    0xF569
+#define reg_sfoe_sf_cnt_pos 0
+#define reg_sfoe_sf_cnt_len 4
+#define reg_sfoe_sf_cnt_lsb 0
+#define    p_reg_fste_phase_ini_7_0 0xF56A
+#define reg_fste_phase_ini_7_0_pos 0
+#define reg_fste_phase_ini_7_0_len 8
+#define reg_fste_phase_ini_7_0_lsb 0
+#define    p_reg_fste_phase_ini_11_8    0xF56B
+#define reg_fste_phase_ini_11_8_pos 0
+#define reg_fste_phase_ini_11_8_len 4
+#define reg_fste_phase_ini_11_8_lsb 8
+#define    p_reg_fste_phase_inc_7_0 0xF56C
+#define reg_fste_phase_inc_7_0_pos 0
+#define reg_fste_phase_inc_7_0_len 8
+#define reg_fste_phase_inc_7_0_lsb 0
+#define    p_reg_fste_phase_inc_11_8    0xF56D
+#define reg_fste_phase_inc_11_8_pos 0
+#define reg_fste_phase_inc_11_8_len 4
+#define reg_fste_phase_inc_11_8_lsb 8
+#define    p_reg_fste_acum_cost_cnt_max 0xF56E
+#define reg_fste_acum_cost_cnt_max_pos 0
+#define reg_fste_acum_cost_cnt_max_len 4
+#define reg_fste_acum_cost_cnt_max_lsb 0
+#define    p_reg_fste_step_size_std 0xF56F
+#define reg_fste_step_size_std_pos 0
+#define reg_fste_step_size_std_len 4
+#define reg_fste_step_size_std_lsb 0
+#define    p_reg_fste_step_size_max 0xF570
+#define reg_fste_step_size_max_pos 0
+#define reg_fste_step_size_max_len 4
+#define reg_fste_step_size_max_lsb 0
+#define    p_reg_fste_rpd_dir_cnt_max   0xF571
+#define reg_fste_rpd_dir_cnt_max_pos 0
+#define reg_fste_rpd_dir_cnt_max_len 4
+#define reg_fste_rpd_dir_cnt_max_lsb 0
+#define    p_reg_fste_frac_cost_cnt_max_7_0 0xF572
+#define reg_fste_frac_cost_cnt_max_7_0_pos 0
+#define reg_fste_frac_cost_cnt_max_7_0_len 8
+#define reg_fste_frac_cost_cnt_max_7_0_lsb 0
+#define    p_reg_fste_frac_cost_cnt_max_9_8 0xF573
+#define reg_fste_frac_cost_cnt_max_9_8_pos 0
+#define reg_fste_frac_cost_cnt_max_9_8_len 2
+#define reg_fste_frac_cost_cnt_max_9_8_lsb 8
+#define    p_reg_fste_isLongWeakTail    0xF574
+#define reg_fste_isLongWeakTail_pos 0
+#define reg_fste_isLongWeakTail_len 1
+#define reg_fste_isLongWeakTail_lsb 0
+#define    p_reg_fste_isLongWeakHead    0xF575
+#define reg_fste_isLongWeakHead_pos 0
+#define reg_fste_isLongWeakHead_len 1
+#define reg_fste_isLongWeakHead_lsb 0
+#define    p_reg_fste_w0_7_0    0xF576
+#define reg_fste_w0_7_0_pos 0
+#define reg_fste_w0_7_0_len 8
+#define reg_fste_w0_7_0_lsb 0
+#define    p_reg_fste_w0_9_8    0xF577
+#define reg_fste_w0_9_8_pos 0
+#define reg_fste_w0_9_8_len 2
+#define reg_fste_w0_9_8_lsb 8
+#define    p_reg_fste_w1_7_0    0xF578
+#define reg_fste_w1_7_0_pos 0
+#define reg_fste_w1_7_0_len 8
+#define reg_fste_w1_7_0_lsb 0
+#define    p_reg_fste_w1_9_8    0xF579
+#define reg_fste_w1_9_8_pos 0
+#define reg_fste_w1_9_8_len 2
+#define reg_fste_w1_9_8_lsb 8
+#define    p_reg_fste_w2_7_0    0xF57A
+#define reg_fste_w2_7_0_pos 0
+#define reg_fste_w2_7_0_len 8
+#define reg_fste_w2_7_0_lsb 0
+#define    p_reg_fste_w2_9_8    0xF57B
+#define reg_fste_w2_9_8_pos 0
+#define reg_fste_w2_9_8_len 2
+#define reg_fste_w2_9_8_lsb 8
+#define    p_reg_fste_w3_7_0    0xF57C
+#define reg_fste_w3_7_0_pos 0
+#define reg_fste_w3_7_0_len 8
+#define reg_fste_w3_7_0_lsb 0
+#define    p_reg_fste_w3_9_8    0xF57D
+#define reg_fste_w3_9_8_pos 0
+#define reg_fste_w3_9_8_len 2
+#define reg_fste_w3_9_8_lsb 8
+#define    p_reg_fste_w4_7_0    0xF57E
+#define reg_fste_w4_7_0_pos 0
+#define reg_fste_w4_7_0_len 8
+#define reg_fste_w4_7_0_lsb 0
+#define    p_reg_fste_w4_9_8    0xF57F
+#define reg_fste_w4_9_8_pos 0
+#define reg_fste_w4_9_8_len 2
+#define reg_fste_w4_9_8_lsb 8
+#define    p_reg_fste_w5_7_0    0xF580
+#define reg_fste_w5_7_0_pos 0
+#define reg_fste_w5_7_0_len 8
+#define reg_fste_w5_7_0_lsb 0
+#define    p_reg_fste_w5_9_8    0xF581
+#define reg_fste_w5_9_8_pos 0
+#define reg_fste_w5_9_8_len 2
+#define reg_fste_w5_9_8_lsb 8
+#define    p_reg_fste_w6_7_0    0xF582
+#define reg_fste_w6_7_0_pos 0
+#define reg_fste_w6_7_0_len 8
+#define reg_fste_w6_7_0_lsb 0
+#define    p_reg_fste_w6_9_8    0xF583
+#define reg_fste_w6_9_8_pos 0
+#define reg_fste_w6_9_8_len 2
+#define reg_fste_w6_9_8_lsb 8
+#define    p_reg_fste_w7_7_0    0xF584
+#define reg_fste_w7_7_0_pos 0
+#define reg_fste_w7_7_0_len 8
+#define reg_fste_w7_7_0_lsb 0
+#define    p_reg_fste_w7_9_8    0xF585
+#define reg_fste_w7_9_8_pos 0
+#define reg_fste_w7_9_8_len 2
+#define reg_fste_w7_9_8_lsb 8
+#define    p_reg_fste_w8_7_0    0xF586
+#define reg_fste_w8_7_0_pos 0
+#define reg_fste_w8_7_0_len 8
+#define reg_fste_w8_7_0_lsb 0
+#define    p_reg_fste_w8_9_8    0xF587
+#define reg_fste_w8_9_8_pos 0
+#define reg_fste_w8_9_8_len 2
+#define reg_fste_w8_9_8_lsb 8
+#define    p_reg_fste_w9_7_0    0xF588
+#define reg_fste_w9_7_0_pos 0
+#define reg_fste_w9_7_0_len 8
+#define reg_fste_w9_7_0_lsb 0
+#define    p_reg_fste_w9_9_8    0xF589
+#define reg_fste_w9_9_8_pos 0
+#define reg_fste_w9_9_8_len 2
+#define reg_fste_w9_9_8_lsb 8
+#define    p_reg_fste_wa_7_0    0xF58A
+#define reg_fste_wa_7_0_pos 0
+#define reg_fste_wa_7_0_len 8
+#define reg_fste_wa_7_0_lsb 0
+#define    p_reg_fste_wa_9_8    0xF58B
+#define reg_fste_wa_9_8_pos 0
+#define reg_fste_wa_9_8_len 2
+#define reg_fste_wa_9_8_lsb 8
+#define    p_reg_fste_wb_7_0    0xF58C
+#define reg_fste_wb_7_0_pos 0
+#define reg_fste_wb_7_0_len 8
+#define reg_fste_wb_7_0_lsb 0
+#define    p_reg_fste_wb_9_8    0xF58D
+#define reg_fste_wb_9_8_pos 0
+#define reg_fste_wb_9_8_len 2
+#define reg_fste_wb_9_8_lsb 8
+#define    p_reg_fste_wc_7_0    0xF58E
+#define reg_fste_wc_7_0_pos 0
+#define reg_fste_wc_7_0_len 8
+#define reg_fste_wc_7_0_lsb 0
+#define    p_reg_fste_wc_9_8    0xF58F
+#define reg_fste_wc_9_8_pos 0
+#define reg_fste_wc_9_8_len 2
+#define reg_fste_wc_9_8_lsb 8
+#define    p_reg_fste_wd_7_0    0xF590
+#define reg_fste_wd_7_0_pos 0
+#define reg_fste_wd_7_0_len 8
+#define reg_fste_wd_7_0_lsb 0
+#define    p_reg_fste_wd_9_8    0xF591
+#define reg_fste_wd_9_8_pos 0
+#define reg_fste_wd_9_8_len 2
+#define reg_fste_wd_9_8_lsb 8
+#define    p_reg_fste_we_7_0    0xF592
+#define reg_fste_we_7_0_pos 0
+#define reg_fste_we_7_0_len 8
+#define reg_fste_we_7_0_lsb 0
+#define    p_reg_fste_we_9_8    0xF593
+#define reg_fste_we_9_8_pos 0
+#define reg_fste_we_9_8_len 2
+#define reg_fste_we_9_8_lsb 8
+#define    p_reg_fste_wf_7_0    0xF594
+#define reg_fste_wf_7_0_pos 0
+#define reg_fste_wf_7_0_len 8
+#define reg_fste_wf_7_0_lsb 0
+#define    p_reg_fste_wf_9_8    0xF595
+#define reg_fste_wf_9_8_pos 0
+#define reg_fste_wf_9_8_len 2
+#define reg_fste_wf_9_8_lsb 8
+#define    p_reg_fste_wg_7_0    0xF596
+#define reg_fste_wg_7_0_pos 0
+#define reg_fste_wg_7_0_len 8
+#define reg_fste_wg_7_0_lsb 0
+#define    p_reg_fste_wg_9_8    0xF597
+#define reg_fste_wg_9_8_pos 0
+#define reg_fste_wg_9_8_len 2
+#define reg_fste_wg_9_8_lsb 8
+#define    p_reg_fste_wh_7_0    0xF598
+#define reg_fste_wh_7_0_pos 0
+#define reg_fste_wh_7_0_len 8
+#define reg_fste_wh_7_0_lsb 0
+#define    p_reg_fste_wh_9_8    0xF599
+#define reg_fste_wh_9_8_pos 0
+#define reg_fste_wh_9_8_len 2
+#define reg_fste_wh_9_8_lsb 8
+#define    r_fd_fste_i_adj_org  0xF59A
+#define fd_fste_i_adj_org_pos 0
+#define fd_fste_i_adj_org_len 5
+#define fd_fste_i_adj_org_lsb 0
+#define    r_fd_fste_f_adj_7_0  0xF59B
+#define fd_fste_f_adj_7_0_pos 0
+#define fd_fste_f_adj_7_0_len 8
+#define fd_fste_f_adj_7_0_lsb 0
+#define    r_fd_fste_f_adj_15_8 0xF59C
+#define fd_fste_f_adj_15_8_pos 0
+#define fd_fste_f_adj_15_8_len 8
+#define fd_fste_f_adj_15_8_lsb 8
+#define    r_fd_fste_f_adj_19_16    0xF59D
+#define fd_fste_f_adj_19_16_pos 0
+#define fd_fste_f_adj_19_16_len 4
+#define fd_fste_f_adj_19_16_lsb 16
+#define    p_reg_fste_ehw_7_0   0xF59E
+#define reg_fste_ehw_7_0_pos 0
+#define reg_fste_ehw_7_0_len 8
+#define reg_fste_ehw_7_0_lsb 0
+#define    p_reg_fste_ehw_12_8  0xF59F
+#define reg_fste_ehw_12_8_pos 0
+#define reg_fste_ehw_12_8_len 5
+#define reg_fste_ehw_12_8_lsb 8
+#define    p_reg_fste_i_adj_vld 0xF5A0
+#define reg_fste_i_adj_vld_pos 0
+#define reg_fste_i_adj_vld_len 1
+#define reg_fste_i_adj_vld_lsb 0
+#define    p_reg_fste_ceTimesPhasor_real    0xF5A1
+#define reg_fste_ceTimesPhasor_real_pos 0
+#define reg_fste_ceTimesPhasor_real_len 1
+#define reg_fste_ceTimesPhasor_real_lsb 0
+#define    p_reg_fste_ceTimesPhasor_imag    0xF5A2
+#define reg_fste_ceTimesPhasor_imag_pos 0
+#define reg_fste_ceTimesPhasor_imag_len 1
+#define reg_fste_ceTimesPhasor_imag_lsb 0
+#define    p_reg_fste_cerTimesW_real    0xF5A3
+#define reg_fste_cerTimesW_real_pos 0
+#define reg_fste_cerTimesW_real_len 1
+#define reg_fste_cerTimesW_real_lsb 0
+#define    p_reg_fste_cerTimesW_imag    0xF5A4
+#define reg_fste_cerTimesW_imag_pos 0
+#define reg_fste_cerTimesW_imag_len 1
+#define reg_fste_cerTimesW_imag_lsb 0
+#define    p_reg_fste_cerTimesWAccum_real   0xF5A5
+#define reg_fste_cerTimesWAccum_real_pos 0
+#define reg_fste_cerTimesWAccum_real_len 1
+#define reg_fste_cerTimesWAccum_real_lsb 0
+#define    p_reg_fste_cerTimesWAccum_imag   0xF5A6
+#define reg_fste_cerTimesWAccum_imag_pos 0
+#define reg_fste_cerTimesWAccum_imag_len 1
+#define reg_fste_cerTimesWAccum_imag_lsb 0
+#define    p_reg_fste_cost  0xF5A7
+#define reg_fste_cost_pos 0
+#define reg_fste_cost_len 1
+#define reg_fste_cost_lsb 0
+#define    p_fd_tpsd_en 0xF5A8
+#define fd_tpsd_en_pos 0
+#define fd_tpsd_en_len 1
+#define fd_tpsd_en_lsb 0
+#define    p_fd_tpsd_lock   0xF5A9
+#define fd_tpsd_lock_pos 0
+#define fd_tpsd_lock_len 1
+#define fd_tpsd_lock_lsb 0
+#define    r_fd_tpsd_s19    0xF5AA
+#define fd_tpsd_s19_pos 0
+#define fd_tpsd_s19_len 1
+#define fd_tpsd_s19_lsb 0
+#define    r_fd_tpsd_s17    0xF5AB
+#define fd_tpsd_s17_pos 0
+#define fd_tpsd_s17_len 1
+#define fd_tpsd_s17_lsb 0
+#define    p_fd_sfr_ste_en  0xF5AC
+#define fd_sfr_ste_en_pos 0
+#define fd_sfr_ste_en_len 1
+#define fd_sfr_ste_en_lsb 0
+#define    p_fd_sfr_ste_mode    0xF5AD
+#define fd_sfr_ste_mode_pos 0
+#define fd_sfr_ste_mode_len 2
+#define fd_sfr_ste_mode_lsb 0
+#define    p_fd_sfr_ste_done    0xF5AE
+#define fd_sfr_ste_done_pos 0
+#define fd_sfr_ste_done_len 1
+#define fd_sfr_ste_done_lsb 0
+#define    p_reg_cfoe_ffoe_en   0xF5AF
+#define reg_cfoe_ffoe_en_pos 0
+#define reg_cfoe_ffoe_en_len 1
+#define reg_cfoe_ffoe_en_lsb 0
+#define    p_reg_cfoe_ifoe_en   0xF5B0
+#define reg_cfoe_ifoe_en_pos 0
+#define reg_cfoe_ifoe_en_len 1
+#define reg_cfoe_ifoe_en_lsb 0
+#define    p_reg_cfoe_fot_en    0xF5B1
+#define reg_cfoe_fot_en_pos 0
+#define reg_cfoe_fot_en_len 1
+#define reg_cfoe_fot_en_lsb 0
+#define    p_reg_cfoe_fot_lm_en 0xF5B2
+#define reg_cfoe_fot_lm_en_pos 0
+#define reg_cfoe_fot_lm_en_len 1
+#define reg_cfoe_fot_lm_en_lsb 0
+#define    p_reg_cfoe_fot_rst   0xF5B3
+#define reg_cfoe_fot_rst_pos 0
+#define reg_cfoe_fot_rst_len 1
+#define reg_cfoe_fot_rst_lsb 0
+#define    r_fd_cfoe_ffoe_done  0xF5B4
+#define fd_cfoe_ffoe_done_pos 0
+#define fd_cfoe_ffoe_done_len 1
+#define fd_cfoe_ffoe_done_lsb 0
+#define    p_fd_cfoe_metric_vld 0xF5B5
+#define fd_cfoe_metric_vld_pos 0
+#define fd_cfoe_metric_vld_len 1
+#define fd_cfoe_metric_vld_lsb 0
+#define    p_reg_cfoe_ifod_vld  0xF5B6
+#define reg_cfoe_ifod_vld_pos 0
+#define reg_cfoe_ifod_vld_len 1
+#define reg_cfoe_ifod_vld_lsb 0
+#define    r_fd_cfoe_ifoe_done  0xF5B7
+#define fd_cfoe_ifoe_done_pos 0
+#define fd_cfoe_ifoe_done_len 1
+#define fd_cfoe_ifoe_done_lsb 0
+#define    p_reg_cfoe_ifoe_spec_inv 0xF5B8
+#define reg_cfoe_ifoe_spec_inv_pos 0
+#define reg_cfoe_ifoe_spec_inv_len 1
+#define reg_cfoe_ifoe_spec_inv_lsb 0
+#define    p_reg_cfoe_divg_int  0xF5B9
+#define reg_cfoe_divg_int_pos 0
+#define reg_cfoe_divg_int_len 1
+#define reg_cfoe_divg_int_lsb 0
+#define    r_reg_cfoe_divg_flag 0xF5BA
+#define reg_cfoe_divg_flag_pos 0
+#define reg_cfoe_divg_flag_len 1
+#define reg_cfoe_divg_flag_lsb 0
+#define    p_reg_sfoe_en    0xF5BB
+#define reg_sfoe_en_pos 0
+#define reg_sfoe_en_len 1
+#define reg_sfoe_en_lsb 0
+#define    p_reg_sfoe_dis   0xF5BC
+#define reg_sfoe_dis_pos 0
+#define reg_sfoe_dis_len 1
+#define reg_sfoe_dis_lsb 0
+#define    p_reg_sfoe_rst   0xF5BD
+#define reg_sfoe_rst_pos 0
+#define reg_sfoe_rst_len 1
+#define reg_sfoe_rst_lsb 0
+#define    p_reg_sfoe_vld_int   0xF5BE
+#define reg_sfoe_vld_int_pos 0
+#define reg_sfoe_vld_int_len 1
+#define reg_sfoe_vld_int_lsb 0
+#define    p_reg_sfoe_lm_en 0xF5BF
+#define reg_sfoe_lm_en_pos 0
+#define reg_sfoe_lm_en_len 1
+#define reg_sfoe_lm_en_lsb 0
+#define    p_reg_sfoe_divg_int  0xF5C0
+#define reg_sfoe_divg_int_pos 0
+#define reg_sfoe_divg_int_len 1
+#define reg_sfoe_divg_int_lsb 0
+#define    r_reg_sfoe_divg_flag 0xF5C1
+#define reg_sfoe_divg_flag_pos 0
+#define reg_sfoe_divg_flag_len 1
+#define reg_sfoe_divg_flag_lsb 0
+#define    p_reg_fft_rst    0xF5C2
+#define reg_fft_rst_pos 0
+#define reg_fft_rst_len 1
+#define reg_fft_rst_lsb 0
+#define    p_reg_fft_mask2_en   0xF5C3
+#define reg_fft_mask2_en_pos 0
+#define reg_fft_mask2_en_len 1
+#define reg_fft_mask2_en_lsb 0
+#define    p_reg_fft_mask3_en   0xF5C4
+#define reg_fft_mask3_en_pos 0
+#define reg_fft_mask3_en_len 1
+#define reg_fft_mask3_en_lsb 0
+#define    p_reg_fft_crc_en 0xF5C5
+#define reg_fft_crc_en_pos 0
+#define reg_fft_crc_en_len 1
+#define reg_fft_crc_en_lsb 0
+#define    p_reg_fft_mask0_en   0xF5C6
+#define reg_fft_mask0_en_pos 0
+#define reg_fft_mask0_en_len 1
+#define reg_fft_mask0_en_lsb 0
+#define    p_reg_fft_mask1_en   0xF5C7
+#define reg_fft_mask1_en_pos 0
+#define reg_fft_mask1_en_len 1
+#define reg_fft_mask1_en_lsb 0
+#define    p_fd_fste_en 0xF5C8
+#define fd_fste_en_pos 0
+#define fd_fste_en_len 1
+#define fd_fste_en_lsb 0
+#define    p_reg_feq_eh2_comp_en    0xF5C9
+#define reg_feq_eh2_comp_en_pos 0
+#define reg_feq_eh2_comp_en_len 1
+#define reg_feq_eh2_comp_en_lsb 0
+#define    p_reg_feq_read_update    0xF5CA
+#define reg_feq_read_update_pos 0
+#define reg_feq_read_update_len 1
+#define reg_feq_read_update_lsb 0
+#define    p_reg_feq_data_vld   0xF5CB
+#define reg_feq_data_vld_pos 0
+#define reg_feq_data_vld_len 1
+#define reg_feq_data_vld_lsb 0
+#define    p_reg_feq_tone_idx_7_0   0xF5CC
+#define reg_feq_tone_idx_7_0_pos 0
+#define reg_feq_tone_idx_7_0_len 8
+#define reg_feq_tone_idx_7_0_lsb 0
+#define    p_reg_feq_tone_idx_12_8  0xF5CD
+#define reg_feq_tone_idx_12_8_pos 0
+#define reg_feq_tone_idx_12_8_len 5
+#define reg_feq_tone_idx_12_8_lsb 8
+#define    r_reg_feq_data_re_7_0    0xF5CE
+#define reg_feq_data_re_7_0_pos 0
+#define reg_feq_data_re_7_0_len 8
+#define reg_feq_data_re_7_0_lsb 0
+#define    r_reg_feq_data_re_15_8   0xF5CF
+#define reg_feq_data_re_15_8_pos 0
+#define reg_feq_data_re_15_8_len 8
+#define reg_feq_data_re_15_8_lsb 8
+#define    r_reg_feq_data_re_21_16  0xF5D0
+#define reg_feq_data_re_21_16_pos 0
+#define reg_feq_data_re_21_16_len 6
+#define reg_feq_data_re_21_16_lsb 16
+#define    r_reg_feq_data_im_7_0    0xF5D1
+#define reg_feq_data_im_7_0_pos 0
+#define reg_feq_data_im_7_0_len 8
+#define reg_feq_data_im_7_0_lsb 0
+#define    r_reg_feq_data_im_15_8   0xF5D2
+#define reg_feq_data_im_15_8_pos 0
+#define reg_feq_data_im_15_8_len 8
+#define reg_feq_data_im_15_8_lsb 8
+#define    r_reg_feq_data_im_21_16  0xF5D3
+#define reg_feq_data_im_21_16_pos 0
+#define reg_feq_data_im_21_16_len 6
+#define reg_feq_data_im_21_16_lsb 16
+#define    r_reg_feq_data_h2_7_0    0xF5D4
+#define reg_feq_data_h2_7_0_pos 0
+#define reg_feq_data_h2_7_0_len 8
+#define reg_feq_data_h2_7_0_lsb 0
+#define    r_reg_feq_data_h2_15_8   0xF5D5
+#define reg_feq_data_h2_15_8_pos 0
+#define reg_feq_data_h2_15_8_len 8
+#define reg_feq_data_h2_15_8_lsb 8
+#define    r_reg_feq_data_h2_18_16  0xF5D6
+#define reg_feq_data_h2_18_16_pos 0
+#define reg_feq_data_h2_18_16_len 3
+#define reg_feq_data_h2_18_16_lsb 16
+#define    p_reg_fs_en  0xF5D7
+#define reg_fs_en_pos 0
+#define reg_fs_en_len 1
+#define reg_fs_en_lsb 0
+#define    p_reg_fs_offset  0xF5D8
+#define reg_fs_offset_pos 0
+#define reg_fs_offset_len 3
+#define reg_fs_offset_lsb 0
+#define    p_reg_fs_debug   0xF5D9
+#define reg_fs_debug_pos 0
+#define reg_fs_debug_len 1
+#define reg_fs_debug_lsb 0
+#define    p_reg_fs_half_inv    0xF5DA
+#define reg_fs_half_inv_pos 0
+#define reg_fs_half_inv_len 1
+#define reg_fs_half_inv_lsb 0
+#define    p_reg_cdpf_currentfftposition_7_0    0xF5DB
+#define reg_cdpf_currentfftposition_7_0_pos 0
+#define reg_cdpf_currentfftposition_7_0_len 8
+#define reg_cdpf_currentfftposition_7_0_lsb 0
+#define    p_reg_cdpf_currentfftposition_14_8   0xF5DC
+#define reg_cdpf_currentfftposition_14_8_pos 0
+#define reg_cdpf_currentfftposition_14_8_len 7
+#define reg_cdpf_currentfftposition_14_8_lsb 8
+#define    r_reg_cdpf_fftshift_7_0  0xF5DD
+#define reg_cdpf_fftshift_7_0_pos 0
+#define reg_cdpf_fftshift_7_0_len 8
+#define reg_cdpf_fftshift_7_0_lsb 0
+#define    r_reg_cdpf_fftshift_13_8 0xF5DE
+#define reg_cdpf_fftshift_13_8_pos 0
+#define reg_cdpf_fftshift_13_8_len 6
+#define reg_cdpf_fftshift_13_8_lsb 8
+#define    p_reg_cdpf_channelpowerdown_7_0  0xF5DF
+#define reg_cdpf_channelpowerdown_7_0_pos 0
+#define reg_cdpf_channelpowerdown_7_0_len 8
+#define reg_cdpf_channelpowerdown_7_0_lsb 0
+#define    p_reg_cdpf_channelpowerdown_10_8 0xF5E0
+#define reg_cdpf_channelpowerdown_10_8_pos 0
+#define reg_cdpf_channelpowerdown_10_8_len 3
+#define reg_cdpf_channelpowerdown_10_8_lsb 8
+#define    p_reg_cdpf_state 0xF5E1
+#define reg_cdpf_state_pos 0
+#define reg_cdpf_state_len 4
+#define reg_cdpf_state_lsb 0
+#define    p_reg_cdpf_echotestsearchingrange    0xF5E2
+#define reg_cdpf_echotestsearchingrange_pos 0
+#define reg_cdpf_echotestsearchingrange_len 8
+#define reg_cdpf_echotestsearchingrange_lsb 0
+#define    p_reg_cdpf_rxsymboldelay 0xF5E3
+#define reg_cdpf_rxsymboldelay_pos 0
+#define reg_cdpf_rxsymboldelay_len 4
+#define reg_cdpf_rxsymboldelay_lsb 0
+#define    p_reg_cdpf_ceavesymbolno 0xF5E4
+#define reg_cdpf_ceavesymbolno_pos 0
+#define reg_cdpf_ceavesymbolno_len 4
+#define reg_cdpf_ceavesymbolno_lsb 0
+#define    p_reg_cdpf_ceshift   0xF5E5
+#define reg_cdpf_ceshift_pos 0
+#define reg_cdpf_ceshift_len 3
+#define reg_cdpf_ceshift_lsb 0
+#define    p_reg_cdpf_postpreechotry    0xF5E6
+#define reg_cdpf_postpreechotry_pos 0
+#define reg_cdpf_postpreechotry_len 2
+#define reg_cdpf_postpreechotry_lsb 0
+#define    p_reg_cdpf_en    0xF5E7
+#define reg_cdpf_en_pos 0
+#define reg_cdpf_en_len 1
+#define reg_cdpf_en_lsb 0
+#define    p_reg_cdpf_stateready    0xF5E8
+#define reg_cdpf_stateready_pos 0
+#define reg_cdpf_stateready_len 1
+#define reg_cdpf_stateready_lsb 0
+#define    r_reg_cdpf_prepostpowercompare   0xF5E9
+#define reg_cdpf_prepostpowercompare_pos 0
+#define reg_cdpf_prepostpowercompare_len 1
+#define reg_cdpf_prepostpowercompare_lsb 0
+#define    r_reg_cdpf_candidateno   0xF5EA
+#define reg_cdpf_candidateno_pos 0
+#define reg_cdpf_candidateno_len 6
+#define reg_cdpf_candidateno_lsb 0
+#define    p_reg_cdpf_preechopower_7_0  0xF5EB
+#define reg_cdpf_preechopower_7_0_pos 0
+#define reg_cdpf_preechopower_7_0_len 8
+#define reg_cdpf_preechopower_7_0_lsb 0
+#define    p_reg_cdpf_preechopower_15_8 0xF5EC
+#define reg_cdpf_preechopower_15_8_pos 0
+#define reg_cdpf_preechopower_15_8_len 8
+#define reg_cdpf_preechopower_15_8_lsb 8
+#define    p_reg_cdpf_postechopower_7_0 0xF5ED
+#define reg_cdpf_postechopower_7_0_pos 0
+#define reg_cdpf_postechopower_7_0_len 8
+#define reg_cdpf_postechopower_7_0_lsb 0
+#define    p_reg_cdpf_postechopower_15_8    0xF5EE
+#define reg_cdpf_postechopower_15_8_pos 0
+#define reg_cdpf_postechopower_15_8_len 8
+#define reg_cdpf_postechopower_15_8_lsb 8
+#define    p_reg_cdpf_searchingend  0xF5EF
+#define reg_cdpf_searchingend_pos 0
+#define reg_cdpf_searchingend_len 8
+#define reg_cdpf_searchingend_lsb 0
+#define    r_reg_cdpf_candidate_7_0 0xF5F0
+#define reg_cdpf_candidate_7_0_pos 0
+#define reg_cdpf_candidate_7_0_len 8
+#define reg_cdpf_candidate_7_0_lsb 0
+#define    r_reg_cdpf_candidate_15_8    0xF5F1
+#define reg_cdpf_candidate_15_8_pos 0
+#define reg_cdpf_candidate_15_8_len 8
+#define reg_cdpf_candidate_15_8_lsb 8
+#define    p_reg_cdpf_candidate_rptr    0xF5F2
+#define reg_cdpf_candidate_rptr_pos 0
+#define reg_cdpf_candidate_rptr_len 7
+#define reg_cdpf_candidate_rptr_lsb 0
+#define    p_reg_cdpf_candidate_rptr_force  0xF5F3
+#define reg_cdpf_candidate_rptr_force_pos 0
+#define reg_cdpf_candidate_rptr_force_len 1
+#define reg_cdpf_candidate_rptr_force_lsb 0
+#define    p_reg_cdpf_trialshiftoffset_7_0  0xF5F4
+#define reg_cdpf_trialshiftoffset_7_0_pos 0
+#define reg_cdpf_trialshiftoffset_7_0_len 8
+#define reg_cdpf_trialshiftoffset_7_0_lsb 0
+#define    p_reg_cdpf_trialshiftoffset_13_8 0xF5F5
+#define reg_cdpf_trialshiftoffset_13_8_pos 0
+#define reg_cdpf_trialshiftoffset_13_8_len 6
+#define reg_cdpf_trialshiftoffset_13_8_lsb 8
+#define    p_reg_cdpf_channellength_7_0 0xF5F6
+#define reg_cdpf_channellength_7_0_pos 0
+#define reg_cdpf_channellength_7_0_len 8
+#define reg_cdpf_channellength_7_0_lsb 0
+#define    p_reg_cdpf_channellength_12_8    0xF5F7
+#define reg_cdpf_channellength_12_8_pos 0
+#define reg_cdpf_channellength_12_8_len 5
+#define reg_cdpf_channellength_12_8_lsb 8
+#define    p_reg_cdpf_hardwaresort  0xF5F8
+#define reg_cdpf_hardwaresort_pos 0
+#define reg_cdpf_hardwaresort_len 1
+#define reg_cdpf_hardwaresort_lsb 0
+#define    p_reg_cdpf_maxcandidateno    0xF5F9
+#define reg_cdpf_maxcandidateno_pos 0
+#define reg_cdpf_maxcandidateno_len 3
+#define reg_cdpf_maxcandidateno_lsb 0
+#define    p_reg_cdpf_channelleftindex  0xF5FA
+#define reg_cdpf_channelleftindex_pos 0
+#define reg_cdpf_channelleftindex_len 4
+#define reg_cdpf_channelleftindex_lsb 0
+#define    r_reg_cdpf_fdishift_7_0  0xF5FB
+#define reg_cdpf_fdishift_7_0_pos 0
+#define reg_cdpf_fdishift_7_0_len 8
+#define reg_cdpf_fdishift_7_0_lsb 0
+#define    r_reg_cdpf_fdishift_15_8 0xF5FC
+#define reg_cdpf_fdishift_15_8_pos 0
+#define reg_cdpf_fdishift_15_8_len 8
+#define reg_cdpf_fdishift_15_8_lsb 8
+#define    p_reg_cdpf_guardband 0xF5FD
+#define reg_cdpf_guardband_pos 0
+#define reg_cdpf_guardband_len 5
+#define reg_cdpf_guardband_lsb 0
+#define    p_reg_cdpf_maxtonemaxindex_7_0   0xF5FE
+#define reg_cdpf_maxtonemaxindex_7_0_pos 0
+#define reg_cdpf_maxtonemaxindex_7_0_len 8
+#define reg_cdpf_maxtonemaxindex_7_0_lsb 0
+#define    p_reg_cdpf_maxtonemaxindex_12_8  0xF5FF
+#define reg_cdpf_maxtonemaxindex_12_8_pos 0
+#define reg_cdpf_maxtonemaxindex_12_8_len 5
+#define reg_cdpf_maxtonemaxindex_12_8_lsb 8
+#define    p_reg_cdpf_fdiw0 0xF600
+#define reg_cdpf_fdiw0_pos 0
+#define reg_cdpf_fdiw0_len 7
+#define reg_cdpf_fdiw0_lsb 0
+#define    p_reg_cdpf_fdiw1 0xF601
+#define reg_cdpf_fdiw1_pos 0
+#define reg_cdpf_fdiw1_len 7
+#define reg_cdpf_fdiw1_lsb 0
+#define    p_reg_cdpf_fdiw2 0xF602
+#define reg_cdpf_fdiw2_pos 0
+#define reg_cdpf_fdiw2_len 7
+#define reg_cdpf_fdiw2_lsb 0
+#define    p_reg_cdpf_fdiw3 0xF603
+#define reg_cdpf_fdiw3_pos 0
+#define reg_cdpf_fdiw3_len 7
+#define reg_cdpf_fdiw3_lsb 0
+#define    p_reg_cdpf_fdiw4 0xF604
+#define reg_cdpf_fdiw4_pos 0
+#define reg_cdpf_fdiw4_len 7
+#define reg_cdpf_fdiw4_lsb 0
+#define    p_reg_cdpf_fdiw5 0xF605
+#define reg_cdpf_fdiw5_pos 0
+#define reg_cdpf_fdiw5_len 7
+#define reg_cdpf_fdiw5_lsb 0
+#define    p_reg_cdpf_fdiw6 0xF606
+#define reg_cdpf_fdiw6_pos 0
+#define reg_cdpf_fdiw6_len 7
+#define reg_cdpf_fdiw6_lsb 0
+#define    p_reg_cdpf_fdiw7 0xF607
+#define reg_cdpf_fdiw7_pos 0
+#define reg_cdpf_fdiw7_len 7
+#define reg_cdpf_fdiw7_lsb 0
+#define    r_reg_cdpf_fdiwindowsize 0xF608
+#define reg_cdpf_fdiwindowsize_pos 0
+#define reg_cdpf_fdiwindowsize_len 4
+#define reg_cdpf_fdiwindowsize_lsb 0
+#define    p_reg_stes_mode  0xF609
+#define reg_stes_mode_pos 0
+#define reg_stes_mode_len 1
+#define reg_stes_mode_lsb 0
+#define    p_reg_stes_done_st   0xF60A
+#define reg_stes_done_st_pos 0
+#define reg_stes_done_st_len 2
+#define reg_stes_done_st_lsb 0
+#define    p_reg_stes_done  0xF60B
+#define reg_stes_done_pos 0
+#define reg_stes_done_len 1
+#define reg_stes_done_lsb 0
+#define    p_reg_stes_timing_7_0    0xF60C
+#define reg_stes_timing_7_0_pos 0
+#define reg_stes_timing_7_0_len 8
+#define reg_stes_timing_7_0_lsb 0
+#define    p_reg_stes_timing_15_8   0xF60D
+#define reg_stes_timing_15_8_pos 0
+#define reg_stes_timing_15_8_len 8
+#define reg_stes_timing_15_8_lsb 8
+#define    p_reg_stes_sym_tot_adj_thre_7_0  0xF60E
+#define reg_stes_sym_tot_adj_thre_7_0_pos 0
+#define reg_stes_sym_tot_adj_thre_7_0_len 8
+#define reg_stes_sym_tot_adj_thre_7_0_lsb 0
+#define    p_reg_stes_sym_tot_adj_thre_15_8 0xF60F
+#define reg_stes_sym_tot_adj_thre_15_8_pos 0
+#define reg_stes_sym_tot_adj_thre_15_8_len 8
+#define reg_stes_sym_tot_adj_thre_15_8_lsb 8
+#define    p_reg_stes_sym_thre_9_2  0xF610
+#define reg_stes_sym_thre_9_2_pos 0
+#define reg_stes_sym_thre_9_2_len 8
+#define reg_stes_sym_thre_9_2_lsb 0
+#define    p_reg_stes_sym_wo_adj_thre_9_2   0xF611
+#define reg_stes_sym_wo_adj_thre_9_2_pos 0
+#define reg_stes_sym_wo_adj_thre_9_2_len 8
+#define reg_stes_sym_wo_adj_thre_9_2_lsb 0
+#define    p_reg_fste_i_adj_7_0 0xF612
+#define reg_fste_i_adj_7_0_pos 0
+#define reg_fste_i_adj_7_0_len 8
+#define reg_fste_i_adj_7_0_lsb 0
+#define    p_reg_fste_i_adj_15_8    0xF613
+#define reg_fste_i_adj_15_8_pos 0
+#define reg_fste_i_adj_15_8_len 8
+#define reg_fste_i_adj_15_8_lsb 8
+#define    r_fd_stes_iadj_val_7_0   0xF614
+#define fd_stes_iadj_val_7_0_pos 0
+#define fd_stes_iadj_val_7_0_len 8
+#define fd_stes_iadj_val_7_0_lsb 0
+#define    r_fd_stes_iadj_val_15_8  0xF615
+#define fd_stes_iadj_val_15_8_pos 0
+#define fd_stes_iadj_val_15_8_len 8
+#define fd_stes_iadj_val_15_8_lsb 8
+#define    r_fd_stes_symb_cnt_9_2   0xF616
+#define fd_stes_symb_cnt_9_2_pos 0
+#define fd_stes_symb_cnt_9_2_len 8
+#define fd_stes_symb_cnt_9_2_lsb 0
+#define    r_fd_stes_snoi_cnt_9_2   0xF617
+#define fd_stes_snoi_cnt_9_2_pos 0
+#define fd_stes_snoi_cnt_9_2_len 8
+#define fd_stes_snoi_cnt_9_2_lsb 0
+#define    r_fd_last_iadj_val_7_0   0xF618
+#define fd_last_iadj_val_7_0_pos 0
+#define fd_last_iadj_val_7_0_len 8
+#define fd_last_iadj_val_7_0_lsb 0
+#define    r_fd_last_iadj_val_15_8  0xF619
+#define fd_last_iadj_val_15_8_pos 0
+#define fd_last_iadj_val_15_8_len 8
+#define fd_last_iadj_val_15_8_lsb 8
+#define    p_reg_stes_bypass    0xF61A
+#define reg_stes_bypass_pos 0
+#define reg_stes_bypass_len 1
+#define reg_stes_bypass_lsb 0
+#define    p_reg_stes_best_timing_idx   0xF61B
+#define reg_stes_best_timing_idx_pos 0
+#define reg_stes_best_timing_idx_len 4
+#define reg_stes_best_timing_idx_lsb 0
+#define    p_reg_stes_iadj_val_7_0  0xF61C
+#define reg_stes_iadj_val_7_0_pos 0
+#define reg_stes_iadj_val_7_0_len 8
+#define reg_stes_iadj_val_7_0_lsb 0
+#define    p_reg_stes_iadj_val_15_8 0xF61D
+#define reg_stes_iadj_val_15_8_pos 0
+#define reg_stes_iadj_val_15_8_len 8
+#define reg_stes_iadj_val_15_8_lsb 8
+#define    p_reg_p_ste_start_guard_7_0  0xF620
+#define reg_p_ste_start_guard_7_0_pos 0
+#define reg_p_ste_start_guard_7_0_len 8
+#define reg_p_ste_start_guard_7_0_lsb 0
+#define    p_reg_p_ste_start_guard_9_8  0xF621
+#define reg_p_ste_start_guard_9_8_pos 0
+#define reg_p_ste_start_guard_9_8_len 2
+#define reg_p_ste_start_guard_9_8_lsb 8
+#define    p_reg_p_ste_end_guard_7_0    0xF622
+#define reg_p_ste_end_guard_7_0_pos 0
+#define reg_p_ste_end_guard_7_0_len 8
+#define reg_p_ste_end_guard_7_0_lsb 0
+#define    p_reg_p_ste_end_guard_9_8    0xF623
+#define reg_p_ste_end_guard_9_8_pos 0
+#define reg_p_ste_end_guard_9_8_len 2
+#define reg_p_ste_end_guard_9_8_lsb 8
+#define    r_reg_r_ste_wrong_beacon_count   0xF624
+#define reg_r_ste_wrong_beacon_count_pos 0
+#define reg_r_ste_wrong_beacon_count_len 7
+#define reg_r_ste_wrong_beacon_count_lsb 0
+#define    p_reg_p_fccid_en 0xF625
+#define reg_p_fccid_en_pos 0
+#define reg_p_fccid_en_len 1
+#define reg_p_fccid_en_lsb 0
+#define    p_reg_p_fccid_fft_ave_symbol_num 0xF626
+#define reg_p_fccid_fft_ave_symbol_num_pos 0
+#define reg_p_fccid_fft_ave_symbol_num_len 6
+#define reg_p_fccid_fft_ave_symbol_num_lsb 0
+#define    p_reg_p_fccid_fft_work_start_tone_7_0    0xF627
+#define reg_p_fccid_fft_work_start_tone_7_0_pos 0
+#define reg_p_fccid_fft_work_start_tone_7_0_len 8
+#define reg_p_fccid_fft_work_start_tone_7_0_lsb 0
+#define    p_reg_p_fccid_fft_work_start_tone_12_8   0xF628
+#define reg_p_fccid_fft_work_start_tone_12_8_pos 0
+#define reg_p_fccid_fft_work_start_tone_12_8_len 5
+#define reg_p_fccid_fft_work_start_tone_12_8_lsb 8
+#define    p_reg_p_fccid_fft_work_end_tone_7_0  0xF629
+#define reg_p_fccid_fft_work_end_tone_7_0_pos 0
+#define reg_p_fccid_fft_work_end_tone_7_0_len 8
+#define reg_p_fccid_fft_work_end_tone_7_0_lsb 0
+#define    p_reg_p_fccid_fft_work_end_tone_12_8 0xF62A
+#define reg_p_fccid_fft_work_end_tone_12_8_pos 0
+#define reg_p_fccid_fft_work_end_tone_12_8_len 5
+#define reg_p_fccid_fft_work_end_tone_12_8_lsb 8
+#define    p_reg_p_fccid_peak_to_th_divider 0xF62B
+#define reg_p_fccid_peak_to_th_divider_pos 0
+#define reg_p_fccid_peak_to_th_divider_len 4
+#define reg_p_fccid_peak_to_th_divider_lsb 0
+#define    p_reg_p_fccid_peak_to_th_mode    0xF62C
+#define reg_p_fccid_peak_to_th_mode_pos 0
+#define reg_p_fccid_peak_to_th_mode_len 2
+#define reg_p_fccid_peak_to_th_mode_lsb 0
+#define    p_reg_p_fccid_search_mode    0xF62D
+#define reg_p_fccid_search_mode_pos 0
+#define reg_p_fccid_search_mode_len 1
+#define reg_p_fccid_search_mode_lsb 0
+#define    p_reg_p_fccid_group_th   0xF62E
+#define reg_p_fccid_group_th_pos 0
+#define reg_p_fccid_group_th_len 7
+#define reg_p_fccid_group_th_lsb 0
+#define    p_reg_p_fccid_search_rdy 0xF62F
+#define reg_p_fccid_search_rdy_pos 0
+#define reg_p_fccid_search_rdy_len 1
+#define reg_p_fccid_search_rdy_lsb 0
+#define    r_reg_r_fccid_fft_ave_read_out_7_0   0xF630
+#define reg_r_fccid_fft_ave_read_out_7_0_pos 0
+#define reg_r_fccid_fft_ave_read_out_7_0_len 8
+#define reg_r_fccid_fft_ave_read_out_7_0_lsb 0
+#define    r_reg_r_fccid_fft_ave_read_out_15_8  0xF631
+#define reg_r_fccid_fft_ave_read_out_15_8_pos 0
+#define reg_r_fccid_fft_ave_read_out_15_8_len 8
+#define reg_r_fccid_fft_ave_read_out_15_8_lsb 8
+#define    r_reg_r_fccid_large_tone_num_7_0 0xF632
+#define reg_r_fccid_large_tone_num_7_0_pos 0
+#define reg_r_fccid_large_tone_num_7_0_len 8
+#define reg_r_fccid_large_tone_num_7_0_lsb 0
+#define    r_reg_r_fccid_large_tone_num_12_8    0xF633
+#define reg_r_fccid_large_tone_num_12_8_pos 0
+#define reg_r_fccid_large_tone_num_12_8_len 5
+#define reg_r_fccid_large_tone_num_12_8_lsb 8
+#define    r_reg_r_fccid_cci1_start_tone_7_0    0xF634
+#define reg_r_fccid_cci1_start_tone_7_0_pos 0
+#define reg_r_fccid_cci1_start_tone_7_0_len 8
+#define reg_r_fccid_cci1_start_tone_7_0_lsb 0
+#define    r_reg_r_fccid_cci1_start_tone_12_8   0xF635
+#define reg_r_fccid_cci1_start_tone_12_8_pos 0
+#define reg_r_fccid_cci1_start_tone_12_8_len 5
+#define reg_r_fccid_cci1_start_tone_12_8_lsb 8
+#define    r_reg_r_fccid_cci1_end_tone_7_0  0xF636
+#define reg_r_fccid_cci1_end_tone_7_0_pos 0
+#define reg_r_fccid_cci1_end_tone_7_0_len 8
+#define reg_r_fccid_cci1_end_tone_7_0_lsb 0
+#define    r_reg_r_fccid_cci1_end_tone_12_8 0xF637
+#define reg_r_fccid_cci1_end_tone_12_8_pos 0
+#define reg_r_fccid_cci1_end_tone_12_8_len 5
+#define reg_r_fccid_cci1_end_tone_12_8_lsb 8
+#define    r_reg_r_fccid_cci1_peak_7_0  0xF638
+#define reg_r_fccid_cci1_peak_7_0_pos 0
+#define reg_r_fccid_cci1_peak_7_0_len 8
+#define reg_r_fccid_cci1_peak_7_0_lsb 0
+#define    r_reg_r_fccid_cci1_peak_15_8 0xF639
+#define reg_r_fccid_cci1_peak_15_8_pos 0
+#define reg_r_fccid_cci1_peak_15_8_len 8
+#define reg_r_fccid_cci1_peak_15_8_lsb 8
+#define    r_reg_r_fccid_cci2_start_tone_7_0    0xF63A
+#define reg_r_fccid_cci2_start_tone_7_0_pos 0
+#define reg_r_fccid_cci2_start_tone_7_0_len 8
+#define reg_r_fccid_cci2_start_tone_7_0_lsb 0
+#define    r_reg_r_fccid_cci2_start_tone_12_8   0xF63B
+#define reg_r_fccid_cci2_start_tone_12_8_pos 0
+#define reg_r_fccid_cci2_start_tone_12_8_len 5
+#define reg_r_fccid_cci2_start_tone_12_8_lsb 8
+#define    r_reg_r_fccid_cci2_end_tone_7_0  0xF63C
+#define reg_r_fccid_cci2_end_tone_7_0_pos 0
+#define reg_r_fccid_cci2_end_tone_7_0_len 8
+#define reg_r_fccid_cci2_end_tone_7_0_lsb 0
+#define    r_reg_r_fccid_cci2_end_tone_12_8 0xF63D
+#define reg_r_fccid_cci2_end_tone_12_8_pos 0
+#define reg_r_fccid_cci2_end_tone_12_8_len 5
+#define reg_r_fccid_cci2_end_tone_12_8_lsb 8
+#define    r_reg_r_fccid_cci2_peak_7_0  0xF63E
+#define reg_r_fccid_cci2_peak_7_0_pos 0
+#define reg_r_fccid_cci2_peak_7_0_len 8
+#define reg_r_fccid_cci2_peak_7_0_lsb 0
+#define    r_reg_r_fccid_cci2_peak_15_8 0xF63F
+#define reg_r_fccid_cci2_peak_15_8_pos 0
+#define reg_r_fccid_cci2_peak_15_8_len 8
+#define reg_r_fccid_cci2_peak_15_8_lsb 8
+#define    r_reg_r_fccid_cci3_start_tone_7_0    0xF640
+#define reg_r_fccid_cci3_start_tone_7_0_pos 0
+#define reg_r_fccid_cci3_start_tone_7_0_len 8
+#define reg_r_fccid_cci3_start_tone_7_0_lsb 0
+#define    r_reg_r_fccid_cci3_start_tone_12_8   0xF641
+#define reg_r_fccid_cci3_start_tone_12_8_pos 0
+#define reg_r_fccid_cci3_start_tone_12_8_len 5
+#define reg_r_fccid_cci3_start_tone_12_8_lsb 8
+#define    r_reg_r_fccid_cci3_end_tone_7_0  0xF642
+#define reg_r_fccid_cci3_end_tone_7_0_pos 0
+#define reg_r_fccid_cci3_end_tone_7_0_len 8
+#define reg_r_fccid_cci3_end_tone_7_0_lsb 0
+#define    r_reg_r_fccid_cci3_end_tone_12_8 0xF643
+#define reg_r_fccid_cci3_end_tone_12_8_pos 0
+#define reg_r_fccid_cci3_end_tone_12_8_len 5
+#define reg_r_fccid_cci3_end_tone_12_8_lsb 8
+#define    r_reg_r_fccid_cci3_peak_7_0  0xF644
+#define reg_r_fccid_cci3_peak_7_0_pos 0
+#define reg_r_fccid_cci3_peak_7_0_len 8
+#define reg_r_fccid_cci3_peak_7_0_lsb 0
+#define    r_reg_r_fccid_cci3_peak_15_8 0xF645
+#define reg_r_fccid_cci3_peak_15_8_pos 0
+#define reg_r_fccid_cci3_peak_15_8_len 8
+#define reg_r_fccid_cci3_peak_15_8_lsb 8
+#define    r_reg_r_fccid_cci4_start_tone_7_0    0xF646
+#define reg_r_fccid_cci4_start_tone_7_0_pos 0
+#define reg_r_fccid_cci4_start_tone_7_0_len 8
+#define reg_r_fccid_cci4_start_tone_7_0_lsb 0
+#define    r_reg_r_fccid_cci4_start_tone_12_8   0xF647
+#define reg_r_fccid_cci4_start_tone_12_8_pos 0
+#define reg_r_fccid_cci4_start_tone_12_8_len 5
+#define reg_r_fccid_cci4_start_tone_12_8_lsb 8
+#define    r_reg_r_fccid_cci4_end_tone_7_0  0xF648
+#define reg_r_fccid_cci4_end_tone_7_0_pos 0
+#define reg_r_fccid_cci4_end_tone_7_0_len 8
+#define reg_r_fccid_cci4_end_tone_7_0_lsb 0
+#define    r_reg_r_fccid_cci4_end_tone_12_8 0xF649
+#define reg_r_fccid_cci4_end_tone_12_8_pos 0
+#define reg_r_fccid_cci4_end_tone_12_8_len 5
+#define reg_r_fccid_cci4_end_tone_12_8_lsb 8
+#define    r_reg_r_fccid_cci4_peak_7_0  0xF64A
+#define reg_r_fccid_cci4_peak_7_0_pos 0
+#define reg_r_fccid_cci4_peak_7_0_len 8
+#define reg_r_fccid_cci4_peak_7_0_lsb 0
+#define    r_reg_r_fccid_cci4_peak_15_8 0xF64B
+#define reg_r_fccid_cci4_peak_15_8_pos 0
+#define reg_r_fccid_cci4_peak_15_8_len 8
+#define reg_r_fccid_cci4_peak_15_8_lsb 8
+#define    r_reg_r_fccid_cci1_rank  0xF64C
+#define reg_r_fccid_cci1_rank_pos 0
+#define reg_r_fccid_cci1_rank_len 3
+#define reg_r_fccid_cci1_rank_lsb 0
+#define    r_reg_r_fccid_cci2_rank  0xF64D
+#define reg_r_fccid_cci2_rank_pos 0
+#define reg_r_fccid_cci2_rank_len 3
+#define reg_r_fccid_cci2_rank_lsb 0
+#define    r_reg_r_fccid_cci3_rank  0xF64E
+#define reg_r_fccid_cci3_rank_pos 0
+#define reg_r_fccid_cci3_rank_len 3
+#define reg_r_fccid_cci3_rank_lsb 0
+#define    r_reg_r_fccid_cci4_rank  0xF64F
+#define reg_r_fccid_cci4_rank_pos 0
+#define reg_r_fccid_cci4_rank_len 3
+#define reg_r_fccid_cci4_rank_lsb 0
+#define    p_reg_p_csi_shift3   0xF650
+#define reg_p_csi_shift3_pos 0
+#define reg_p_csi_shift3_len 4
+#define reg_p_csi_shift3_lsb 0
+#define    p_reg_p_csi_mul3 0xF651
+#define reg_p_csi_mul3_pos 0
+#define reg_p_csi_mul3_len 8
+#define reg_p_csi_mul3_lsb 0
+#define    p_reg_p_csi_level3_7_0   0xF652
+#define reg_p_csi_level3_7_0_pos 0
+#define reg_p_csi_level3_7_0_len 8
+#define reg_p_csi_level3_7_0_lsb 0
+#define    p_reg_p_csi_level3_8 0xF653
+#define reg_p_csi_level3_8_pos 0
+#define reg_p_csi_level3_8_len 1
+#define reg_p_csi_level3_8_lsb 8
+#define    p_reg_p_csi_fftout_shift_fix_value   0xF654
+#define reg_p_csi_fftout_shift_fix_value_pos 0
+#define reg_p_csi_fftout_shift_fix_value_len 4
+#define reg_p_csi_fftout_shift_fix_value_lsb 0
+#define    p_reg_p_feq_scale_pow    0xF655
+#define reg_p_feq_scale_pow_pos 0
+#define reg_p_feq_scale_pow_len 6
+#define reg_p_feq_scale_pow_lsb 0
+#define    p_reg_p_csi_cp_idx   0xF656
+#define reg_p_csi_cp_idx_pos 0
+#define reg_p_csi_cp_idx_len 8
+#define reg_p_csi_cp_idx_lsb 0
+#define    p_reg_p_csi_outsh_zero_th_7_0    0xF657
+#define reg_p_csi_outsh_zero_th_7_0_pos 0
+#define reg_p_csi_outsh_zero_th_7_0_len 8
+#define reg_p_csi_outsh_zero_th_7_0_lsb 0
+#define    p_reg_p_csi_outsh_zero_th_10_8   0xF658
+#define reg_p_csi_outsh_zero_th_10_8_pos 0
+#define reg_p_csi_outsh_zero_th_10_8_len 3
+#define reg_p_csi_outsh_zero_th_10_8_lsb 8
+#define    p_reg_p_csi_ar_ratio 0xF659
+#define reg_p_csi_ar_ratio_pos 0
+#define reg_p_csi_ar_ratio_len 8
+#define reg_p_csi_ar_ratio_lsb 0
+#define    p_reg_r_csi_cp_vld   0xF65A
+#define reg_r_csi_cp_vld_pos 0
+#define reg_r_csi_cp_vld_len 1
+#define reg_r_csi_cp_vld_lsb 0
+#define    p_reg_r_csi_sp_vld   0xF65B
+#define reg_r_csi_sp_vld_pos 0
+#define reg_r_csi_sp_vld_len 1
+#define reg_r_csi_sp_vld_lsb 0
+#define    p_reg_p_csi_fft_out_shift_en 0xF65C
+#define reg_p_csi_fft_out_shift_en_pos 0
+#define reg_p_csi_fft_out_shift_en_len 1
+#define reg_p_csi_fft_out_shift_en_lsb 0
+#define    p_reg_p_csi_feq_out_shift_en 0xF65D
+#define reg_p_csi_feq_out_shift_en_pos 0
+#define reg_p_csi_feq_out_shift_en_len 1
+#define reg_p_csi_feq_out_shift_en_lsb 0
+#define    p_reg_r_csi_cp_fft_out   0xF65E
+#define reg_r_csi_cp_fft_out_pos 0
+#define reg_r_csi_cp_fft_out_len 1
+#define reg_r_csi_cp_fft_out_lsb 0
+#define    p_reg_r_csi_sp_feq_log2_out  0xF65F
+#define reg_r_csi_sp_feq_log2_out_pos 0
+#define reg_r_csi_sp_feq_log2_out_len 8
+#define reg_r_csi_sp_feq_log2_out_lsb 0
+#define    p_reg_r_csi_sp_fft_out   0xF660
+#define reg_r_csi_sp_fft_out_pos 0
+#define reg_r_csi_sp_fft_out_len 1
+#define reg_r_csi_sp_fft_out_lsb 0
+#define    p_reg_p_feq_eh2_from_fpcc_en 0xF661
+#define reg_p_feq_eh2_from_fpcc_en_pos 0
+#define reg_p_feq_eh2_from_fpcc_en_len 1
+#define reg_p_feq_eh2_from_fpcc_en_lsb 0
+#define    r_reg_r_fccid_fft_ave_peak_7_0   0xF662
+#define reg_r_fccid_fft_ave_peak_7_0_pos 0
+#define reg_r_fccid_fft_ave_peak_7_0_len 8
+#define reg_r_fccid_fft_ave_peak_7_0_lsb 0
+#define    r_reg_r_fccid_fft_ave_peak_15_8  0xF663
+#define reg_r_fccid_fft_ave_peak_15_8_pos 0
+#define reg_r_fccid_fft_ave_peak_15_8_len 8
+#define reg_r_fccid_fft_ave_peak_15_8_lsb 8
+#define    r_reg_r_fccid_fft_ave_peak_23_16 0xF664
+#define reg_r_fccid_fft_ave_peak_23_16_pos 0
+#define reg_r_fccid_fft_ave_peak_23_16_len 8
+#define reg_r_fccid_fft_ave_peak_23_16_lsb 16
+#define    r_reg_r_fccid_fft_ave_peak_26_24 0xF665
+#define reg_r_fccid_fft_ave_peak_26_24_pos 0
+#define reg_r_fccid_fft_ave_peak_26_24_len 3
+#define reg_r_fccid_fft_ave_peak_26_24_lsb 24
+#define    p_reg_p_fccid_fft_ave_read_rdy   0xF666
+#define reg_p_fccid_fft_ave_read_rdy_pos 0
+#define reg_p_fccid_fft_ave_read_rdy_len 1
+#define reg_p_fccid_fft_ave_read_rdy_lsb 0
+#define    p_reg_p_fccid_fft_ave_read_index_7_0 0xF667
+#define reg_p_fccid_fft_ave_read_index_7_0_pos 0
+#define reg_p_fccid_fft_ave_read_index_7_0_len 8
+#define reg_p_fccid_fft_ave_read_index_7_0_lsb 0
+#define    p_reg_p_fccid_fft_ave_read_index_12_8    0xF668
+#define reg_p_fccid_fft_ave_read_index_12_8_pos 0
+#define reg_p_fccid_fft_ave_read_index_12_8_len 5
+#define reg_p_fccid_fft_ave_read_index_12_8_lsb 8
+#define    p_reg_cdpf_candidate_rw  0xF669
+#define reg_cdpf_candidate_rw_pos 0
+#define reg_cdpf_candidate_rw_len 1
+#define reg_cdpf_candidate_rw_lsb 0
+#define    p_reg_cdpf_candidate_prog_7_0    0xF66A
+#define reg_cdpf_candidate_prog_7_0_pos 0
+#define reg_cdpf_candidate_prog_7_0_len 8
+#define reg_cdpf_candidate_prog_7_0_lsb 0
+#define    p_reg_cdpf_candidate_prog_15_8   0xF66B
+#define reg_cdpf_candidate_prog_15_8_pos 0
+#define reg_cdpf_candidate_prog_15_8_len 8
+#define reg_cdpf_candidate_prog_15_8_lsb 8
+#define    p_reg_cdpf_candidateno_prog  0xF66C
+#define reg_cdpf_candidateno_prog_pos 0
+#define reg_cdpf_candidateno_prog_len 6
+#define reg_cdpf_candidateno_prog_lsb 0
+#define    p_reg_cdpf_candidateno_switch    0xF66D
+#define reg_cdpf_candidateno_switch_pos 0
+#define reg_cdpf_candidateno_switch_len 1
+#define reg_cdpf_candidateno_switch_lsb 0
+#define    g_reg_tpsd_txmod 0xF900
+#define reg_tpsd_txmod_pos 0
+#define reg_tpsd_txmod_len 2
+#define reg_tpsd_txmod_lsb 0
+#define    g_reg_tpsd_gi    0xF901
+#define reg_tpsd_gi_pos 0
+#define reg_tpsd_gi_len 2
+#define reg_tpsd_gi_lsb 0
+#define    g_reg_tpsd_hier  0xF902
+#define reg_tpsd_hier_pos 0
+#define reg_tpsd_hier_len 3
+#define reg_tpsd_hier_lsb 0
+#define    g_reg_tpsd_const 0xF903
+#define reg_tpsd_const_pos 0
+#define reg_tpsd_const_len 2
+#define reg_tpsd_const_lsb 0
+#define    g_reg_bw 0xF904
+#define reg_bw_pos 0
+#define reg_bw_len 2
+#define reg_bw_lsb 0
+#define    g_reg_dec_pri    0xF905
+#define reg_dec_pri_pos 0
+#define reg_dec_pri_len 1
+#define reg_dec_pri_lsb 0
+#define    g_reg_tpsd_hpcr  0xF906
+#define reg_tpsd_hpcr_pos 0
+#define reg_tpsd_hpcr_len 3
+#define reg_tpsd_hpcr_lsb 0
+#define    g_reg_tpsd_lpcr  0xF907
+#define reg_tpsd_lpcr_pos 0
+#define reg_tpsd_lpcr_len 3
+#define reg_tpsd_lpcr_lsb 0
+#define    g_reg_tpsd_indep 0xF908
+#define reg_tpsd_indep_pos 0
+#define reg_tpsd_indep_len 1
+#define reg_tpsd_indep_lsb 0
+#define    g_reg_tpsd_tslice    0xF909
+#define reg_tpsd_tslice_pos 0
+#define reg_tpsd_tslice_len 1
+#define reg_tpsd_tslice_lsb 0
+#define    g_reg_tpsd_mpefec    0xF90A
+#define reg_tpsd_mpefec_pos 0
+#define reg_tpsd_mpefec_len 1
+#define reg_tpsd_mpefec_lsb 0
+#define    g_reg_sntc_en    0xF90B
+#define reg_sntc_en_pos 0
+#define reg_sntc_en_len 1
+#define reg_sntc_en_lsb 0
+#define    g_reg_intp_sys_div   0xF90C
+#define reg_intp_sys_div_pos 0
+#define reg_intp_sys_div_len 1
+#define reg_intp_sys_div_lsb 0
+#define    g_reg_clk_sntc_sel   0xF90D
+#define reg_clk_sntc_sel_pos 0
+#define reg_clk_sntc_sel_len 3
+#define reg_clk_sntc_sel_lsb 0
+#define    p_reg_ce_gs_force    0xFD00
+#define reg_ce_gs_force_pos 0
+#define reg_ce_gs_force_len 1
+#define reg_ce_gs_force_lsb 0
+#define    p_reg_ce_dagcgain_delay  0xFD01
+#define reg_ce_dagcgain_delay_pos 0
+#define reg_ce_dagcgain_delay_len 2
+#define reg_ce_dagcgain_delay_lsb 0
+#define    p_reg_ce_derot_en    0xFD02
+#define reg_ce_derot_en_pos 0
+#define reg_ce_derot_en_len 1
+#define reg_ce_derot_en_lsb 0
+#define    p_reg_ce_fctrl_en    0xFD05
+#define reg_ce_fctrl_en_pos 0
+#define reg_ce_fctrl_en_len 1
+#define reg_ce_fctrl_en_lsb 0
+#define    p_reg_ce_en  0xFD06
+#define reg_ce_en_pos 0
+#define reg_ce_en_len 1
+#define reg_ce_en_lsb 0
+#define    p_reg_ce_sat_wes 0xFD07
+#define reg_ce_sat_wes_pos 0
+#define reg_ce_sat_wes_len 1
+#define reg_ce_sat_wes_lsb 0
+#define    p_reg_ce_sat_sigma2  0xFD08
+#define reg_ce_sat_sigma2_pos 0
+#define reg_ce_sat_sigma2_len 1
+#define reg_ce_sat_sigma2_lsb 0
+#define    p_reg_ce_sat_tdi_br_re   0xFD09
+#define reg_ce_sat_tdi_br_re_pos 0
+#define reg_ce_sat_tdi_br_re_len 1
+#define reg_ce_sat_tdi_br_re_lsb 0
+#define    p_reg_ce_sat_tdi_br_im   0xFD0A
+#define reg_ce_sat_tdi_br_im_pos 0
+#define reg_ce_sat_tdi_br_im_len 1
+#define reg_ce_sat_tdi_br_im_lsb 0
+#define    p_reg_ce_sat_tdi_ar_re   0xFD0B
+#define reg_ce_sat_tdi_ar_re_pos 0
+#define reg_ce_sat_tdi_ar_re_len 1
+#define reg_ce_sat_tdi_ar_re_lsb 0
+#define    p_reg_ce_sat_tdi_ar_im   0xFD0C
+#define reg_ce_sat_tdi_ar_im_pos 0
+#define reg_ce_sat_tdi_ar_im_len 1
+#define reg_ce_sat_tdi_ar_im_lsb 0
+#define    p_reg_ce_sat_fdi_br_re   0xFD0D
+#define reg_ce_sat_fdi_br_re_pos 0
+#define reg_ce_sat_fdi_br_re_len 1
+#define reg_ce_sat_fdi_br_re_lsb 0
+#define    p_reg_ce_sat_fdi_br_im   0xFD0E
+#define reg_ce_sat_fdi_br_im_pos 0
+#define reg_ce_sat_fdi_br_im_len 1
+#define reg_ce_sat_fdi_br_im_lsb 0
+#define    p_reg_ce_var_forced_value    0xFD0F
+#define reg_ce_var_forced_value_pos 0
+#define reg_ce_var_forced_value_len 3
+#define reg_ce_var_forced_value_lsb 0
+#define    p_reg_ce_s1  0xFD10
+#define reg_ce_s1_pos 0
+#define reg_ce_s1_len 5
+#define reg_ce_s1_lsb 0
+#define    r_reg_ce_tdi_flatness_7_0    0xFD11
+#define reg_ce_tdi_flatness_7_0_pos 0
+#define reg_ce_tdi_flatness_7_0_len 8
+#define reg_ce_tdi_flatness_7_0_lsb 0
+#define    r_reg_ce_tdi_flatness_8  0xFD12
+#define reg_ce_tdi_flatness_8_pos 0
+#define reg_ce_tdi_flatness_8_len 1
+#define reg_ce_tdi_flatness_8_lsb 8
+#define    r_reg_ce_tone_7_0    0xFD13
+#define reg_ce_tone_7_0_pos 0
+#define reg_ce_tone_7_0_len 8
+#define reg_ce_tone_7_0_lsb 0
+#define    r_reg_ce_tone_12_8   0xFD14
+#define reg_ce_tone_12_8_pos 0
+#define reg_ce_tone_12_8_len 5
+#define reg_ce_tone_12_8_lsb 8
+#define    p_reg_ce_centroid_drift_th   0xFD15
+#define reg_ce_centroid_drift_th_pos 0
+#define reg_ce_centroid_drift_th_len 8
+#define reg_ce_centroid_drift_th_lsb 0
+#define    p_reg_ce_centroid_bias_inc_7_0   0xFD16
+#define reg_ce_centroid_bias_inc_7_0_pos 0
+#define reg_ce_centroid_bias_inc_7_0_len 8
+#define reg_ce_centroid_bias_inc_7_0_lsb 0
+#define    p_reg_ce_centroid_bias_inc_8 0xFD17
+#define reg_ce_centroid_bias_inc_8_pos 0
+#define reg_ce_centroid_bias_inc_8_len 1
+#define reg_ce_centroid_bias_inc_8_lsb 8
+#define    p_reg_ce_centroid_count_max  0xFD18
+#define reg_ce_centroid_count_max_pos 0
+#define reg_ce_centroid_count_max_len 4
+#define reg_ce_centroid_count_max_lsb 0
+#define    p_reg_ce_var_th0_7_0 0xFD19
+#define reg_ce_var_th0_7_0_pos 0
+#define reg_ce_var_th0_7_0_len 8
+#define reg_ce_var_th0_7_0_lsb 0
+#define    p_reg_ce_var_th0_15_8    0xFD1A
+#define reg_ce_var_th0_15_8_pos 0
+#define reg_ce_var_th0_15_8_len 8
+#define reg_ce_var_th0_15_8_lsb 8
+#define    p_reg_ce_var_th1_7_0 0xFD1B
+#define reg_ce_var_th1_7_0_pos 0
+#define reg_ce_var_th1_7_0_len 8
+#define reg_ce_var_th1_7_0_lsb 0
+#define    p_reg_ce_var_th1_15_8    0xFD1C
+#define reg_ce_var_th1_15_8_pos 0
+#define reg_ce_var_th1_15_8_len 8
+#define reg_ce_var_th1_15_8_lsb 8
+#define    p_reg_ce_var_th2_7_0 0xFD1D
+#define reg_ce_var_th2_7_0_pos 0
+#define reg_ce_var_th2_7_0_len 8
+#define reg_ce_var_th2_7_0_lsb 0
+#define    p_reg_ce_var_th2_15_8    0xFD1E
+#define reg_ce_var_th2_15_8_pos 0
+#define reg_ce_var_th2_15_8_len 8
+#define reg_ce_var_th2_15_8_lsb 8
+#define    p_reg_ce_var_th3_7_0 0xFD1F
+#define reg_ce_var_th3_7_0_pos 0
+#define reg_ce_var_th3_7_0_len 8
+#define reg_ce_var_th3_7_0_lsb 0
+#define    p_reg_ce_var_th3_15_8    0xFD20
+#define reg_ce_var_th3_15_8_pos 0
+#define reg_ce_var_th3_15_8_len 8
+#define reg_ce_var_th3_15_8_lsb 8
+#define    p_reg_ce_var_th4_7_0 0xFD21
+#define reg_ce_var_th4_7_0_pos 0
+#define reg_ce_var_th4_7_0_len 8
+#define reg_ce_var_th4_7_0_lsb 0
+#define    p_reg_ce_var_th4_15_8    0xFD22
+#define reg_ce_var_th4_15_8_pos 0
+#define reg_ce_var_th4_15_8_len 8
+#define reg_ce_var_th4_15_8_lsb 8
+#define    p_reg_ce_var_th5_7_0 0xFD23
+#define reg_ce_var_th5_7_0_pos 0
+#define reg_ce_var_th5_7_0_len 8
+#define reg_ce_var_th5_7_0_lsb 0
+#define    p_reg_ce_var_th5_15_8    0xFD24
+#define reg_ce_var_th5_15_8_pos 0
+#define reg_ce_var_th5_15_8_len 8
+#define reg_ce_var_th5_15_8_lsb 8
+#define    p_reg_ce_var_th6_7_0 0xFD25
+#define reg_ce_var_th6_7_0_pos 0
+#define reg_ce_var_th6_7_0_len 8
+#define reg_ce_var_th6_7_0_lsb 0
+#define    p_reg_ce_var_th6_15_8    0xFD26
+#define reg_ce_var_th6_15_8_pos 0
+#define reg_ce_var_th6_15_8_len 8
+#define reg_ce_var_th6_15_8_lsb 8
+#define    p_reg_ce_var_max 0xFD27
+#define reg_ce_var_max_pos 0
+#define reg_ce_var_max_len 3
+#define reg_ce_var_max_lsb 0
+#define    p_reg_ce_cent_forced_en  0xFD28
+#define reg_ce_cent_forced_en_pos 0
+#define reg_ce_cent_forced_en_len 1
+#define reg_ce_cent_forced_en_lsb 0
+#define    p_reg_ce_var_forced_en   0xFD29
+#define reg_ce_var_forced_en_pos 0
+#define reg_ce_var_forced_en_len 1
+#define reg_ce_var_forced_en_lsb 0
+#define    p_reg_ce_fctrl_auto_reset_en 0xFD2A
+#define reg_ce_fctrl_auto_reset_en_pos 0
+#define reg_ce_fctrl_auto_reset_en_len 1
+#define reg_ce_fctrl_auto_reset_en_lsb 0
+#define    p_reg_ce_cent_auto_clr_en    0xFD2B
+#define reg_ce_cent_auto_clr_en_pos 0
+#define reg_ce_cent_auto_clr_en_len 1
+#define reg_ce_cent_auto_clr_en_lsb 0
+#define    p_reg_ce_fctrl_reset 0xFD2C
+#define reg_ce_fctrl_reset_pos 0
+#define reg_ce_fctrl_reset_len 1
+#define reg_ce_fctrl_reset_lsb 0
+#define    p_reg_ce_cent_forced_value_7_0   0xFD2D
+#define reg_ce_cent_forced_value_7_0_pos 0
+#define reg_ce_cent_forced_value_7_0_len 8
+#define reg_ce_cent_forced_value_7_0_lsb 0
+#define    p_reg_ce_cent_forced_value_11_8  0xFD2E
+#define reg_ce_cent_forced_value_11_8_pos 0
+#define reg_ce_cent_forced_value_11_8_len 4
+#define reg_ce_cent_forced_value_11_8_lsb 8
+#define    p_reg_ce_cent_auto_clr_value_7_0 0xFD2F
+#define reg_ce_cent_auto_clr_value_7_0_pos 0
+#define reg_ce_cent_auto_clr_value_7_0_len 8
+#define reg_ce_cent_auto_clr_value_7_0_lsb 0
+#define    p_reg_ce_cent_auto_clr_value_11_8    0xFD30
+#define reg_ce_cent_auto_clr_value_11_8_pos 0
+#define reg_ce_cent_auto_clr_value_11_8_len 4
+#define reg_ce_cent_auto_clr_value_11_8_lsb 8
+#define    p_reg_ce_centroid_max_7_0    0xFD31
+#define reg_ce_centroid_max_7_0_pos 0
+#define reg_ce_centroid_max_7_0_len 8
+#define reg_ce_centroid_max_7_0_lsb 0
+#define    p_reg_ce_centroid_max_11_8   0xFD32
+#define reg_ce_centroid_max_11_8_pos 0
+#define reg_ce_centroid_max_11_8_len 4
+#define reg_ce_centroid_max_11_8_lsb 8
+#define    p_reg_ce_fctrl_rd    0xFD33
+#define reg_ce_fctrl_rd_pos 0
+#define reg_ce_fctrl_rd_len 1
+#define reg_ce_fctrl_rd_lsb 0
+#define    r_reg_ce_centroid_out_7_0    0xFD34
+#define reg_ce_centroid_out_7_0_pos 0
+#define reg_ce_centroid_out_7_0_len 8
+#define reg_ce_centroid_out_7_0_lsb 0
+#define    r_reg_ce_centroid_out_11_8   0xFD35
+#define reg_ce_centroid_out_11_8_pos 0
+#define reg_ce_centroid_out_11_8_len 4
+#define reg_ce_centroid_out_11_8_lsb 8
+#define    r_reg_ce_fctrl_rdy   0xFD36
+#define reg_ce_fctrl_rdy_pos 0
+#define reg_ce_fctrl_rdy_len 1
+#define reg_ce_fctrl_rdy_lsb 0
+#define    r_reg_ce_var 0xFD37
+#define reg_ce_var_pos 0
+#define reg_ce_var_len 3
+#define reg_ce_var_lsb 0
+#define    r_reg_ce_bias_7_0    0xFD38
+#define reg_ce_bias_7_0_pos 0
+#define reg_ce_bias_7_0_len 8
+#define reg_ce_bias_7_0_lsb 0
+#define    r_reg_ce_bias_11_8   0xFD39
+#define reg_ce_bias_11_8_pos 0
+#define reg_ce_bias_11_8_len 4
+#define reg_ce_bias_11_8_lsb 8
+#define    r_reg_ce_m1_7_0  0xFD3A
+#define reg_ce_m1_7_0_pos 0
+#define reg_ce_m1_7_0_len 8
+#define reg_ce_m1_7_0_lsb 0
+#define    r_reg_ce_m1_11_8 0xFD3B
+#define reg_ce_m1_11_8_pos 0
+#define reg_ce_m1_11_8_len 4
+#define reg_ce_m1_11_8_lsb 8
+#define    r_reg_ce_rh0_7_0 0xFD3C
+#define reg_ce_rh0_7_0_pos 0
+#define reg_ce_rh0_7_0_len 8
+#define reg_ce_rh0_7_0_lsb 0
+#define    r_reg_ce_rh0_15_8    0xFD3D
+#define reg_ce_rh0_15_8_pos 0
+#define reg_ce_rh0_15_8_len 8
+#define reg_ce_rh0_15_8_lsb 8
+#define    r_reg_ce_rh0_23_16   0xFD3E
+#define reg_ce_rh0_23_16_pos 0
+#define reg_ce_rh0_23_16_len 8
+#define reg_ce_rh0_23_16_lsb 16
+#define    r_reg_ce_rh0_31_24   0xFD3F
+#define reg_ce_rh0_31_24_pos 0
+#define reg_ce_rh0_31_24_len 8
+#define reg_ce_rh0_31_24_lsb 24
+#define    p_reg_ce_tdi_delta   0xFD40
+#define reg_ce_tdi_delta_pos 0
+#define reg_ce_tdi_delta_len 3
+#define reg_ce_tdi_delta_lsb 0
+#define    p_reg_ce_fdi_delta   0xFD41
+#define reg_ce_fdi_delta_pos 0
+#define reg_ce_fdi_delta_len 3
+#define reg_ce_fdi_delta_lsb 0
+#define    p_reg_ce_fste_delta  0xFD42
+#define reg_ce_fste_delta_pos 0
+#define reg_ce_fste_delta_len 3
+#define reg_ce_fste_delta_lsb 0
+#define    r_reg_ce_fft_s1  0xFD43
+#define reg_ce_fft_s1_pos 0
+#define reg_ce_fft_s1_len 4
+#define reg_ce_fft_s1_lsb 0
+#define    r_reg_feq_fix_eh2_7_0    0xFD44
+#define reg_feq_fix_eh2_7_0_pos 0
+#define reg_feq_fix_eh2_7_0_len 8
+#define reg_feq_fix_eh2_7_0_lsb 0
+#define    r_reg_feq_fix_eh2_15_8   0xFD45
+#define reg_feq_fix_eh2_15_8_pos 0
+#define reg_feq_fix_eh2_15_8_len 8
+#define reg_feq_fix_eh2_15_8_lsb 8
+#define    r_reg_feq_fix_eh2_23_16  0xFD46
+#define reg_feq_fix_eh2_23_16_pos 0
+#define reg_feq_fix_eh2_23_16_len 8
+#define reg_feq_fix_eh2_23_16_lsb 16
+#define    r_reg_feq_fix_eh2_31_24  0xFD47
+#define reg_feq_fix_eh2_31_24_pos 0
+#define reg_feq_fix_eh2_31_24_len 8
+#define reg_feq_fix_eh2_31_24_lsb 24
+#define    r_reg_ce_m2_central_7_0  0xFD48
+#define reg_ce_m2_central_7_0_pos 0
+#define reg_ce_m2_central_7_0_len 8
+#define reg_ce_m2_central_7_0_lsb 0
+#define    r_reg_ce_m2_central_15_8 0xFD49
+#define reg_ce_m2_central_15_8_pos 0
+#define reg_ce_m2_central_15_8_len 8
+#define reg_ce_m2_central_15_8_lsb 8
+#define    r_reg_ce_sigma2_7_0  0xFD4A
+#define reg_ce_sigma2_7_0_pos 0
+#define reg_ce_sigma2_7_0_len 8
+#define reg_ce_sigma2_7_0_lsb 0
+#define    r_reg_ce_sigma2_15_8 0xFD4B
+#define reg_ce_sigma2_15_8_pos 0
+#define reg_ce_sigma2_15_8_len 8
+#define reg_ce_sigma2_15_8_lsb 8
+#define    r_reg_ce_sigma2_19_16    0xFD4C
+#define reg_ce_sigma2_19_16_pos 0
+#define reg_ce_sigma2_19_16_len 4
+#define reg_ce_sigma2_19_16_lsb 16
+#define    r_reg_ce_data_im_7_0 0xFD4D
+#define reg_ce_data_im_7_0_pos 0
+#define reg_ce_data_im_7_0_len 8
+#define reg_ce_data_im_7_0_lsb 0
+#define    r_reg_ce_data_im_14_8    0xFD4E
+#define reg_ce_data_im_14_8_pos 0
+#define reg_ce_data_im_14_8_len 7
+#define reg_ce_data_im_14_8_lsb 8
+#define    r_reg_ce_data_re_7_0 0xFD4F
+#define reg_ce_data_re_7_0_pos 0
+#define reg_ce_data_re_7_0_len 8
+#define reg_ce_data_re_7_0_lsb 0
+#define    r_reg_ce_data_re_14_8    0xFD50
+#define reg_ce_data_re_14_8_pos 0
+#define reg_ce_data_re_14_8_len 7
+#define reg_ce_data_re_14_8_lsb 8
+#define    p_reg_ce_var_default_value   0xFD51
+#define reg_ce_var_default_value_pos 0
+#define reg_ce_var_default_value_len 3
+#define reg_ce_var_default_value_lsb 0
+#define    p_reg_ce_cent_default_value_7_0  0xFD52
+#define reg_ce_cent_default_value_7_0_pos 0
+#define reg_ce_cent_default_value_7_0_len 8
+#define reg_ce_cent_default_value_7_0_lsb 0
+#define    p_reg_ce_cent_default_value_11_8 0xFD53
+#define reg_ce_cent_default_value_11_8_pos 0
+#define reg_ce_cent_default_value_11_8_len 4
+#define reg_ce_cent_default_value_11_8_lsb 8
+#define    r_reg_ce_var_hw  0xFD54
+#define reg_ce_var_hw_pos 0
+#define reg_ce_var_hw_len 3
+#define reg_ce_var_hw_lsb 0
+#define    r_reg_ce_cent_hw_7_0 0xFD55
+#define reg_ce_cent_hw_7_0_pos 0
+#define reg_ce_cent_hw_7_0_len 8
+#define reg_ce_cent_hw_7_0_lsb 0
+#define    r_reg_ce_cent_hw_11_8    0xFD56
+#define reg_ce_cent_hw_11_8_pos 0
+#define reg_ce_cent_hw_11_8_len 4
+#define reg_ce_cent_hw_11_8_lsb 8
+#define    p_reg_ce_fdi_cp_test_en  0xFD57
+#define reg_ce_fdi_cp_test_en_pos 0
+#define reg_ce_fdi_cp_test_en_len 1
+#define reg_ce_fdi_cp_test_en_lsb 0
+#define    p_reg_ce_cptestindex0_7_0    0xFD58
+#define reg_ce_cptestindex0_7_0_pos 0
+#define reg_ce_cptestindex0_7_0_len 8
+#define reg_ce_cptestindex0_7_0_lsb 0
+#define    p_reg_ce_cptestindex0_12_8   0xFD59
+#define reg_ce_cptestindex0_12_8_pos 0
+#define reg_ce_cptestindex0_12_8_len 5
+#define reg_ce_cptestindex0_12_8_lsb 8
+#define    p_reg_ce_cptestfdi0  0xFD5A
+#define reg_ce_cptestfdi0_pos 0
+#define reg_ce_cptestfdi0_len 3
+#define reg_ce_cptestfdi0_lsb 0
+#define    p_reg_ce_cptestindex1_7_0    0xFD5B
+#define reg_ce_cptestindex1_7_0_pos 0
+#define reg_ce_cptestindex1_7_0_len 8
+#define reg_ce_cptestindex1_7_0_lsb 0
+#define    p_reg_ce_cptestindex1_12_8   0xFD5C
+#define reg_ce_cptestindex1_12_8_pos 0
+#define reg_ce_cptestindex1_12_8_len 5
+#define reg_ce_cptestindex1_12_8_lsb 8
+#define    p_reg_ce_cptestfdi1  0xFD5D
+#define reg_ce_cptestfdi1_pos 0
+#define reg_ce_cptestfdi1_len 3
+#define reg_ce_cptestfdi1_lsb 0
+#define    p_reg_ce_cptestindex2_7_0    0xFD5E
+#define reg_ce_cptestindex2_7_0_pos 0
+#define reg_ce_cptestindex2_7_0_len 8
+#define reg_ce_cptestindex2_7_0_lsb 0
+#define    p_reg_ce_cptestindex2_12_8   0xFD5F
+#define reg_ce_cptestindex2_12_8_pos 0
+#define reg_ce_cptestindex2_12_8_len 5
+#define reg_ce_cptestindex2_12_8_lsb 8
+#define    p_reg_ce_cptestfdi2  0xFD60
+#define reg_ce_cptestfdi2_pos 0
+#define reg_ce_cptestfdi2_len 3
+#define reg_ce_cptestfdi2_lsb 0
+#define    p_reg_ce_cptestindex3_7_0    0xFD61
+#define reg_ce_cptestindex3_7_0_pos 0
+#define reg_ce_cptestindex3_7_0_len 8
+#define reg_ce_cptestindex3_7_0_lsb 0
+#define    p_reg_ce_cptestindex3_12_8   0xFD62
+#define reg_ce_cptestindex3_12_8_pos 0
+#define reg_ce_cptestindex3_12_8_len 5
+#define reg_ce_cptestindex3_12_8_lsb 8
+#define    p_reg_ce_cptestfdi3  0xFD63
+#define reg_ce_cptestfdi3_pos 0
+#define reg_ce_cptestfdi3_len 3
+#define reg_ce_cptestfdi3_lsb 0
+#define    p_reg_ce_cptestindex4_7_0    0xFD64
+#define reg_ce_cptestindex4_7_0_pos 0
+#define reg_ce_cptestindex4_7_0_len 8
+#define reg_ce_cptestindex4_7_0_lsb 0
+#define    p_reg_ce_cptestindex4_12_8   0xFD65
+#define reg_ce_cptestindex4_12_8_pos 0
+#define reg_ce_cptestindex4_12_8_len 5
+#define reg_ce_cptestindex4_12_8_lsb 8
+#define    p_reg_ce_cptestfdi4  0xFD66
+#define reg_ce_cptestfdi4_pos 0
+#define reg_ce_cptestfdi4_len 3
+#define reg_ce_cptestfdi4_lsb 0
+#define    p_reg_ce_cptestindex5_7_0    0xFD67
+#define reg_ce_cptestindex5_7_0_pos 0
+#define reg_ce_cptestindex5_7_0_len 8
+#define reg_ce_cptestindex5_7_0_lsb 0
+#define    p_reg_ce_cptestindex5_12_8   0xFD68
+#define reg_ce_cptestindex5_12_8_pos 0
+#define reg_ce_cptestindex5_12_8_len 5
+#define reg_ce_cptestindex5_12_8_lsb 8
+#define    p_reg_ce_cptestfdi5  0xFD69
+#define reg_ce_cptestfdi5_pos 0
+#define reg_ce_cptestfdi5_len 3
+#define reg_ce_cptestfdi5_lsb 0
+#define    p_reg_ce_cptestindex6_7_0    0xFD6A
+#define reg_ce_cptestindex6_7_0_pos 0
+#define reg_ce_cptestindex6_7_0_len 8
+#define reg_ce_cptestindex6_7_0_lsb 0
+#define    p_reg_ce_cptestindex6_12_8   0xFD6B
+#define reg_ce_cptestindex6_12_8_pos 0
+#define reg_ce_cptestindex6_12_8_len 5
+#define reg_ce_cptestindex6_12_8_lsb 8
+#define    p_reg_ce_cptestfdi6  0xFD6C
+#define reg_ce_cptestfdi6_pos 0
+#define reg_ce_cptestfdi6_len 3
+#define reg_ce_cptestfdi6_lsb 0
+#define    p_reg_ce_cptestindex7_7_0    0xFD6D
+#define reg_ce_cptestindex7_7_0_pos 0
+#define reg_ce_cptestindex7_7_0_len 8
+#define reg_ce_cptestindex7_7_0_lsb 0
+#define    p_reg_ce_cptestindex7_12_8   0xFD6E
+#define reg_ce_cptestindex7_12_8_pos 0
+#define reg_ce_cptestindex7_12_8_len 5
+#define reg_ce_cptestindex7_12_8_lsb 8
+#define    p_reg_ce_cptestfdi7  0xFD6F
+#define reg_ce_cptestfdi7_pos 0
+#define reg_ce_cptestfdi7_len 3
+#define reg_ce_cptestfdi7_lsb 0
+#define    p_reg_ce_cp_replace_tdiout_en    0xFD74
+#define reg_ce_cp_replace_tdiout_en_pos 0
+#define reg_ce_cp_replace_tdiout_en_len 1
+#define reg_ce_cp_replace_tdiout_en_lsb 0
+#define    p_reg_ce_tdi_mask0_en    0xFD7D
+#define reg_ce_tdi_mask0_en_pos 0
+#define reg_ce_tdi_mask0_en_len 1
+#define reg_ce_tdi_mask0_en_lsb 0
+#define    p_reg_ce_tdi_mask_from0_7_0  0xFD7E
+#define reg_ce_tdi_mask_from0_7_0_pos 0
+#define reg_ce_tdi_mask_from0_7_0_len 8
+#define reg_ce_tdi_mask_from0_7_0_lsb 0
+#define    p_reg_ce_tdi_mask_from0_12_8 0xFD7F
+#define reg_ce_tdi_mask_from0_12_8_pos 0
+#define reg_ce_tdi_mask_from0_12_8_len 5
+#define reg_ce_tdi_mask_from0_12_8_lsb 8
+#define    p_reg_ce_tdi_mask_to0_7_0    0xFD80
+#define reg_ce_tdi_mask_to0_7_0_pos 0
+#define reg_ce_tdi_mask_to0_7_0_len 8
+#define reg_ce_tdi_mask_to0_7_0_lsb 0
+#define    p_reg_ce_tdi_mask_to0_12_8   0xFD81
+#define reg_ce_tdi_mask_to0_12_8_pos 0
+#define reg_ce_tdi_mask_to0_12_8_len 5
+#define reg_ce_tdi_mask_to0_12_8_lsb 8
+#define    p_reg_ce_tdi_mask1_en    0xFD82
+#define reg_ce_tdi_mask1_en_pos 0
+#define reg_ce_tdi_mask1_en_len 1
+#define reg_ce_tdi_mask1_en_lsb 0
+#define    p_reg_ce_tdi_mask_from1_7_0  0xFD83
+#define reg_ce_tdi_mask_from1_7_0_pos 0
+#define reg_ce_tdi_mask_from1_7_0_len 8
+#define reg_ce_tdi_mask_from1_7_0_lsb 0
+#define    p_reg_ce_tdi_mask_from1_12_8 0xFD84
+#define reg_ce_tdi_mask_from1_12_8_pos 0
+#define reg_ce_tdi_mask_from1_12_8_len 5
+#define reg_ce_tdi_mask_from1_12_8_lsb 8
+#define    p_reg_ce_tdi_mask_to1_7_0    0xFD85
+#define reg_ce_tdi_mask_to1_7_0_pos 0
+#define reg_ce_tdi_mask_to1_7_0_len 8
+#define reg_ce_tdi_mask_to1_7_0_lsb 0
+#define    p_reg_ce_tdi_mask_to1_12_8   0xFD86
+#define reg_ce_tdi_mask_to1_12_8_pos 0
+#define reg_ce_tdi_mask_to1_12_8_len 5
+#define reg_ce_tdi_mask_to1_12_8_lsb 8
+#define    p_reg_ce_2nd_var_max 0xFD87
+#define reg_ce_2nd_var_max_pos 0
+#define reg_ce_2nd_var_max_len 3
+#define reg_ce_2nd_var_max_lsb 0
+#define    p_reg_ce_2nd_cent_forced_en  0xFD88
+#define reg_ce_2nd_cent_forced_en_pos 0
+#define reg_ce_2nd_cent_forced_en_len 1
+#define reg_ce_2nd_cent_forced_en_lsb 0
+#define    p_reg_ce_2nd_var_forced_en   0xFD89
+#define reg_ce_2nd_var_forced_en_pos 0
+#define reg_ce_2nd_var_forced_en_len 1
+#define reg_ce_2nd_var_forced_en_lsb 0
+#define    p_reg_ce_2nd_fctrl_auto_reset_en 0xFD8A
+#define reg_ce_2nd_fctrl_auto_reset_en_pos 0
+#define reg_ce_2nd_fctrl_auto_reset_en_len 1
+#define reg_ce_2nd_fctrl_auto_reset_en_lsb 0
+#define    p_reg_ce_2nd_cent_auto_clr_en    0xFD8B
+#define reg_ce_2nd_cent_auto_clr_en_pos 0
+#define reg_ce_2nd_cent_auto_clr_en_len 1
+#define reg_ce_2nd_cent_auto_clr_en_lsb 0
+#define    p_reg_ce_2nd_cent_forced_value_7_0   0xFD8C
+#define reg_ce_2nd_cent_forced_value_7_0_pos 0
+#define reg_ce_2nd_cent_forced_value_7_0_len 8
+#define reg_ce_2nd_cent_forced_value_7_0_lsb 0
+#define    p_reg_ce_2nd_cent_forced_value_11_8  0xFD8D
+#define reg_ce_2nd_cent_forced_value_11_8_pos 0
+#define reg_ce_2nd_cent_forced_value_11_8_len 4
+#define reg_ce_2nd_cent_forced_value_11_8_lsb 8
+#define    p_reg_ce_2nd_cent_auto_clr_value_7_0 0xFD8E
+#define reg_ce_2nd_cent_auto_clr_value_7_0_pos 0
+#define reg_ce_2nd_cent_auto_clr_value_7_0_len 8
+#define reg_ce_2nd_cent_auto_clr_value_7_0_lsb 0
+#define    p_reg_ce_2nd_cent_auto_clr_value_11_8    0xFD8F
+#define reg_ce_2nd_cent_auto_clr_value_11_8_pos 0
+#define reg_ce_2nd_cent_auto_clr_value_11_8_len 4
+#define reg_ce_2nd_cent_auto_clr_value_11_8_lsb 8
+#define    p_reg_ce_gs_s1_var   0xFD90
+#define reg_ce_gs_s1_var_pos 0
+#define reg_ce_gs_s1_var_len 4
+#define reg_ce_gs_s1_var_lsb 0
+#define    p_reg_ce_2nd_centroid_max_7_0    0xFD91
+#define reg_ce_2nd_centroid_max_7_0_pos 0
+#define reg_ce_2nd_centroid_max_7_0_len 8
+#define reg_ce_2nd_centroid_max_7_0_lsb 0
+#define    p_reg_ce_2nd_centroid_max_11_8   0xFD92
+#define reg_ce_2nd_centroid_max_11_8_pos 0
+#define reg_ce_2nd_centroid_max_11_8_len 4
+#define reg_ce_2nd_centroid_max_11_8_lsb 8
+#define    r_reg_ce_2nd_centroid_out_7_0    0xFD93
+#define reg_ce_2nd_centroid_out_7_0_pos 0
+#define reg_ce_2nd_centroid_out_7_0_len 8
+#define reg_ce_2nd_centroid_out_7_0_lsb 0
+#define    r_reg_ce_2nd_centroid_out_11_8   0xFD94
+#define reg_ce_2nd_centroid_out_11_8_pos 0
+#define reg_ce_2nd_centroid_out_11_8_len 4
+#define reg_ce_2nd_centroid_out_11_8_lsb 8
+#define    r_reg_ce_2nd_fctrl_rdy   0xFD95
+#define reg_ce_2nd_fctrl_rdy_pos 0
+#define reg_ce_2nd_fctrl_rdy_len 1
+#define reg_ce_2nd_fctrl_rdy_lsb 0
+#define    r_reg_ce_2nd_var 0xFD96
+#define reg_ce_2nd_var_pos 0
+#define reg_ce_2nd_var_len 3
+#define reg_ce_2nd_var_lsb 0
+#define    r_reg_ce_2nd_bias_7_0    0xFD97
+#define reg_ce_2nd_bias_7_0_pos 0
+#define reg_ce_2nd_bias_7_0_len 8
+#define reg_ce_2nd_bias_7_0_lsb 0
+#define    r_reg_ce_2nd_bias_11_8   0xFD98
+#define reg_ce_2nd_bias_11_8_pos 0
+#define reg_ce_2nd_bias_11_8_len 4
+#define reg_ce_2nd_bias_11_8_lsb 8
+#define    r_reg_ce_2nd_m1_7_0  0xFD99
+#define reg_ce_2nd_m1_7_0_pos 0
+#define reg_ce_2nd_m1_7_0_len 8
+#define reg_ce_2nd_m1_7_0_lsb 0
+#define    r_reg_ce_2nd_m1_11_8 0xFD9A
+#define reg_ce_2nd_m1_11_8_pos 0
+#define reg_ce_2nd_m1_11_8_len 4
+#define reg_ce_2nd_m1_11_8_lsb 8
+#define    p_reg_ce_2nd_var_forced_value    0xFD9B
+#define reg_ce_2nd_var_forced_value_pos 0
+#define reg_ce_2nd_var_forced_value_len 3
+#define reg_ce_2nd_var_forced_value_lsb 0
+#define    r_reg_ce_2nd_m2_central_7_0  0xFD9C
+#define reg_ce_2nd_m2_central_7_0_pos 0
+#define reg_ce_2nd_m2_central_7_0_len 8
+#define reg_ce_2nd_m2_central_7_0_lsb 0
+#define    r_reg_ce_2nd_m2_central_15_8 0xFD9D
+#define reg_ce_2nd_m2_central_15_8_pos 0
+#define reg_ce_2nd_m2_central_15_8_len 8
+#define reg_ce_2nd_m2_central_15_8_lsb 8
+#define    p_reg_ce_2nd_var_default_value   0xFD9E
+#define reg_ce_2nd_var_default_value_pos 0
+#define reg_ce_2nd_var_default_value_len 3
+#define reg_ce_2nd_var_default_value_lsb 0
+#define    p_reg_ce_2nd_cent_default_value_7_0  0xFD9F
+#define reg_ce_2nd_cent_default_value_7_0_pos 0
+#define reg_ce_2nd_cent_default_value_7_0_len 8
+#define reg_ce_2nd_cent_default_value_7_0_lsb 0
+#define    p_reg_ce_2nd_cent_default_value_11_8 0xFDA0
+#define reg_ce_2nd_cent_default_value_11_8_pos 0
+#define reg_ce_2nd_cent_default_value_11_8_len 4
+#define reg_ce_2nd_cent_default_value_11_8_lsb 8
+#define    p_reg_ce_use_fdi_long    0xFDA1
+#define reg_ce_use_fdi_long_pos 0
+#define reg_ce_use_fdi_long_len 1
+#define reg_ce_use_fdi_long_lsb 0
+#define    p_reg_p_ce_tdi_lms_en    0xFDA2
+#define reg_p_ce_tdi_lms_en_pos 0
+#define reg_p_ce_tdi_lms_en_len 1
+#define reg_p_ce_tdi_lms_en_lsb 0
+#define    p_reg_p_ce_tdi_lms_bufshift  0xFDA3
+#define reg_p_ce_tdi_lms_bufshift_pos 0
+#define reg_p_ce_tdi_lms_bufshift_len 2
+#define reg_p_ce_tdi_lms_bufshift_lsb 0
+#define    p_reg_p_ce_tdi_lms_ave_ratio 0xFDA4
+#define reg_p_ce_tdi_lms_ave_ratio_pos 0
+#define reg_p_ce_tdi_lms_ave_ratio_len 5
+#define reg_p_ce_tdi_lms_ave_ratio_lsb 0
+#define    p_reg_p_ce_conf2_in_con0_en  0xFDA5
+#define reg_p_ce_conf2_in_con0_en_pos 0
+#define reg_p_ce_conf2_in_con0_en_len 1
+#define reg_p_ce_conf2_in_con0_en_lsb 0
+#define    p_fec_rsd_packet_unit_7_0    0xF700
+#define fec_rsd_packet_unit_7_0_pos 0
+#define fec_rsd_packet_unit_7_0_len 8
+#define fec_rsd_packet_unit_7_0_lsb 0
+#define    p_fec_rsd_packet_unit_15_8   0xF701
+#define fec_rsd_packet_unit_15_8_pos 0
+#define fec_rsd_packet_unit_15_8_len 8
+#define fec_rsd_packet_unit_15_8_lsb 8
+#define    r_reg_rsd_bit_err_cnt_7_0    0xF702
+#define reg_rsd_bit_err_cnt_7_0_pos 0
+#define reg_rsd_bit_err_cnt_7_0_len 8
+#define reg_rsd_bit_err_cnt_7_0_lsb 0
+#define    r_reg_rsd_bit_err_cnt_15_8   0xF703
+#define reg_rsd_bit_err_cnt_15_8_pos 0
+#define reg_rsd_bit_err_cnt_15_8_len 8
+#define reg_rsd_bit_err_cnt_15_8_lsb 8
+#define    r_reg_rsd_bit_err_cnt_23_16  0xF704
+#define reg_rsd_bit_err_cnt_23_16_pos 0
+#define reg_rsd_bit_err_cnt_23_16_len 8
+#define reg_rsd_bit_err_cnt_23_16_lsb 16
+#define    r_reg_rsd_abort_packet_cnt_7_0   0xF705
+#define reg_rsd_abort_packet_cnt_7_0_pos 0
+#define reg_rsd_abort_packet_cnt_7_0_len 8
+#define reg_rsd_abort_packet_cnt_7_0_lsb 0
+#define    r_reg_rsd_abort_packet_cnt_15_8  0xF706
+#define reg_rsd_abort_packet_cnt_15_8_pos 0
+#define reg_rsd_abort_packet_cnt_15_8_len 8
+#define reg_rsd_abort_packet_cnt_15_8_lsb 8
+#define    p_fec_RSD_PKT_NUM_PER_UNIT_7_0   0xF707
+#define fec_RSD_PKT_NUM_PER_UNIT_7_0_pos 0
+#define fec_RSD_PKT_NUM_PER_UNIT_7_0_len 8
+#define fec_RSD_PKT_NUM_PER_UNIT_7_0_lsb 0
+#define    p_fec_RSD_PKT_NUM_PER_UNIT_15_8  0xF708
+#define fec_RSD_PKT_NUM_PER_UNIT_15_8_pos 0
+#define fec_RSD_PKT_NUM_PER_UNIT_15_8_len 8
+#define fec_RSD_PKT_NUM_PER_UNIT_15_8_lsb 8
+#define    p_fec_RS_TH_1_7_0    0xF709
+#define fec_RS_TH_1_7_0_pos 0
+#define fec_RS_TH_1_7_0_len 8
+#define fec_RS_TH_1_7_0_lsb 0
+#define    p_fec_RS_TH_1_15_8   0xF70A
+#define fec_RS_TH_1_15_8_pos 0
+#define fec_RS_TH_1_15_8_len 8
+#define fec_RS_TH_1_15_8_lsb 8
+#define    p_fec_RS_TH_2    0xF70B
+#define fec_RS_TH_2_pos 0
+#define fec_RS_TH_2_len 8
+#define fec_RS_TH_2_lsb 0
+#define    p_fec_rsd_ber_rst    0xF70C
+#define fec_rsd_ber_rst_pos 0
+#define fec_rsd_ber_rst_len 1
+#define fec_rsd_ber_rst_lsb 0
+#define    p_reg_rsd_ber_rdy    0xF70D
+#define reg_rsd_ber_rdy_pos 0
+#define reg_rsd_ber_rdy_len 1
+#define reg_rsd_ber_rdy_lsb 0
+#define    p_reg_rsd_trigger_retrain    0xF70E
+#define reg_rsd_trigger_retrain_pos 0
+#define reg_rsd_trigger_retrain_len 1
+#define reg_rsd_trigger_retrain_lsb 0
+#define    p_reg_sync_recover   0xF70F
+#define reg_sync_recover_pos 0
+#define reg_sync_recover_len 1
+#define reg_sync_recover_lsb 0
+#define    p_fec_crc_en 0xF710
+#define fec_crc_en_pos 0
+#define fec_crc_en_len 1
+#define fec_crc_en_lsb 0
+#define    p_fec_mon_en 0xF711
+#define fec_mon_en_pos 0
+#define fec_mon_en_len 1
+#define fec_mon_en_lsb 0
+#define    p_reg_sync_chk   0xF712
+#define reg_sync_chk_pos 0
+#define reg_sync_chk_len 1
+#define reg_sync_chk_lsb 0
+#define    p_fec_dummy_reg_2    0xF713
+#define fec_dummy_reg_2_pos 0
+#define fec_dummy_reg_2_len 3
+#define fec_dummy_reg_2_lsb 0
+#define    p_reg_fec_data_en    0xF714
+#define reg_fec_data_en_pos 0
+#define reg_fec_data_en_len 1
+#define reg_fec_data_en_lsb 0
+#define    p_fec_vtb_rsd_mon_en 0xF715
+#define fec_vtb_rsd_mon_en_pos 0
+#define fec_vtb_rsd_mon_en_len 1
+#define fec_vtb_rsd_mon_en_lsb 0
+#define    p_reg_fec_sw_rst 0xF716
+#define reg_fec_sw_rst_pos 0
+#define reg_fec_sw_rst_len 1
+#define reg_fec_sw_rst_lsb 0
+#define    r_fec_vtb_pm_crc 0xF717
+#define fec_vtb_pm_crc_pos 0
+#define fec_vtb_pm_crc_len 8
+#define fec_vtb_pm_crc_lsb 0
+#define    r_fec_vtb_tb_7_crc   0xF718
+#define fec_vtb_tb_7_crc_pos 0
+#define fec_vtb_tb_7_crc_len 8
+#define fec_vtb_tb_7_crc_lsb 0
+#define    r_fec_vtb_tb_6_crc   0xF719
+#define fec_vtb_tb_6_crc_pos 0
+#define fec_vtb_tb_6_crc_len 8
+#define fec_vtb_tb_6_crc_lsb 0
+#define    r_fec_vtb_tb_5_crc   0xF71A
+#define fec_vtb_tb_5_crc_pos 0
+#define fec_vtb_tb_5_crc_len 8
+#define fec_vtb_tb_5_crc_lsb 0
+#define    r_fec_vtb_tb_4_crc   0xF71B
+#define fec_vtb_tb_4_crc_pos 0
+#define fec_vtb_tb_4_crc_len 8
+#define fec_vtb_tb_4_crc_lsb 0
+#define    r_fec_vtb_tb_3_crc   0xF71C
+#define fec_vtb_tb_3_crc_pos 0
+#define fec_vtb_tb_3_crc_len 8
+#define fec_vtb_tb_3_crc_lsb 0
+#define    r_fec_vtb_tb_2_crc   0xF71D
+#define fec_vtb_tb_2_crc_pos 0
+#define fec_vtb_tb_2_crc_len 8
+#define fec_vtb_tb_2_crc_lsb 0
+#define    r_fec_vtb_tb_1_crc   0xF71E
+#define fec_vtb_tb_1_crc_pos 0
+#define fec_vtb_tb_1_crc_len 8
+#define fec_vtb_tb_1_crc_lsb 0
+#define    r_fec_vtb_tb_0_crc   0xF71F
+#define fec_vtb_tb_0_crc_pos 0
+#define fec_vtb_tb_0_crc_len 8
+#define fec_vtb_tb_0_crc_lsb 0
+#define    r_fec_rsd_bank0_crc  0xF720
+#define fec_rsd_bank0_crc_pos 0
+#define fec_rsd_bank0_crc_len 8
+#define fec_rsd_bank0_crc_lsb 0
+#define    r_fec_rsd_bank1_crc  0xF721
+#define fec_rsd_bank1_crc_pos 0
+#define fec_rsd_bank1_crc_len 8
+#define fec_rsd_bank1_crc_lsb 0
+#define    r_fec_idi_vtb_crc    0xF722
+#define fec_idi_vtb_crc_pos 0
+#define fec_idi_vtb_crc_len 8
+#define fec_idi_vtb_crc_lsb 0
+#define    p_reg_fec_rsd_packet_unit_exp    0xF723
+#define reg_fec_rsd_packet_unit_exp_pos 0
+#define reg_fec_rsd_packet_unit_exp_len 4
+#define reg_fec_rsd_packet_unit_exp_lsb 0
+#define    p_reg_rsd_bit_err_exp_rdy    0xF724
+#define reg_rsd_bit_err_exp_rdy_pos 0
+#define reg_rsd_bit_err_exp_rdy_len 1
+#define reg_rsd_bit_err_exp_rdy_lsb 0
+#define    r_reg_rsd_bit_err_exp    0xF725
+#define reg_rsd_bit_err_exp_pos 0
+#define reg_rsd_bit_err_exp_len 5
+#define reg_rsd_bit_err_exp_lsb 0
+#define    p_fec_rsd_packet_unit1_7_0   0xF726
+#define fec_rsd_packet_unit1_7_0_pos 0
+#define fec_rsd_packet_unit1_7_0_len 8
+#define fec_rsd_packet_unit1_7_0_lsb 0
+#define    p_fec_rsd_packet_unit1_15_8  0xF727
+#define fec_rsd_packet_unit1_15_8_pos 0
+#define fec_rsd_packet_unit1_15_8_len 8
+#define fec_rsd_packet_unit1_15_8_lsb 8
+#define    r_reg_rsd_bit_err_cnt1_7_0   0xF728
+#define reg_rsd_bit_err_cnt1_7_0_pos 0
+#define reg_rsd_bit_err_cnt1_7_0_len 8
+#define reg_rsd_bit_err_cnt1_7_0_lsb 0
+#define    r_reg_rsd_bit_err_cnt1_15_8  0xF729
+#define reg_rsd_bit_err_cnt1_15_8_pos 0
+#define reg_rsd_bit_err_cnt1_15_8_len 8
+#define reg_rsd_bit_err_cnt1_15_8_lsb 8
+#define    r_reg_rsd_bit_err_cnt1_23_16 0xF72A
+#define reg_rsd_bit_err_cnt1_23_16_pos 0
+#define reg_rsd_bit_err_cnt1_23_16_len 8
+#define reg_rsd_bit_err_cnt1_23_16_lsb 16
+#define    r_reg_rsd_abort_packet_cnt1_7_0  0xF72B
+#define reg_rsd_abort_packet_cnt1_7_0_pos 0
+#define reg_rsd_abort_packet_cnt1_7_0_len 8
+#define reg_rsd_abort_packet_cnt1_7_0_lsb 0
+#define    r_reg_rsd_abort_packet_cnt1_15_8 0xF72C
+#define reg_rsd_abort_packet_cnt1_15_8_pos 0
+#define reg_rsd_abort_packet_cnt1_15_8_len 8
+#define reg_rsd_abort_packet_cnt1_15_8_lsb 8
+#define    p_fec_rsd_ber_rst1   0xF72D
+#define fec_rsd_ber_rst1_pos 0
+#define fec_rsd_ber_rst1_len 1
+#define fec_rsd_ber_rst1_lsb 0
+#define    p_reg_rsd_ber_rdy1   0xF72E
+#define reg_rsd_ber_rdy1_pos 0
+#define reg_rsd_ber_rdy1_len 1
+#define reg_rsd_ber_rdy1_lsb 0
+#define    p_reg_dca_txmod_sel  0xF72F
+#define reg_dca_txmod_sel_pos 0
+#define reg_dca_txmod_sel_len 1
+#define reg_dca_txmod_sel_lsb 0
+#define    p_reg_dca_platch 0xF730
+#define reg_dca_platch_pos 0
+#define reg_dca_platch_len 1
+#define reg_dca_platch_lsb 0
+#define    p_reg_dca_upper_chip 0xF731
+#define reg_dca_upper_chip_pos 0
+#define reg_dca_upper_chip_len 1
+#define reg_dca_upper_chip_lsb 0
+#define    p_reg_dca_lower_chip 0xF732
+#define reg_dca_lower_chip_pos 0
+#define reg_dca_lower_chip_len 1
+#define reg_dca_lower_chip_lsb 0
+#define    p_reg_dca_enl    0xF733
+#define reg_dca_enl_pos 0
+#define reg_dca_enl_len 1
+#define reg_dca_enl_lsb 0
+#define    p_reg_dca_enu    0xF734
+#define reg_dca_enu_pos 0
+#define reg_dca_enu_len 1
+#define reg_dca_enu_lsb 0
+#define    p_reg_dca_th 0xF735
+#define reg_dca_th_pos 0
+#define reg_dca_th_len 5
+#define reg_dca_th_lsb 0
+#define    p_reg_dca_scale  0xF736
+#define reg_dca_scale_pos 0
+#define reg_dca_scale_len 4
+#define reg_dca_scale_lsb 0
+#define    p_reg_dca_tone_7_0   0xF737
+#define reg_dca_tone_7_0_pos 0
+#define reg_dca_tone_7_0_len 8
+#define reg_dca_tone_7_0_lsb 0
+#define    p_reg_dca_tone_12_8  0xF738
+#define reg_dca_tone_12_8_pos 0
+#define reg_dca_tone_12_8_len 5
+#define reg_dca_tone_12_8_lsb 8
+#define    p_reg_dca_time_7_0   0xF739
+#define reg_dca_time_7_0_pos 0
+#define reg_dca_time_7_0_len 8
+#define reg_dca_time_7_0_lsb 0
+#define    p_reg_dca_time_15_8  0xF73A
+#define reg_dca_time_15_8_pos 0
+#define reg_dca_time_15_8_len 8
+#define reg_dca_time_15_8_lsb 8
+#define    r_fec_dcasm  0xF73B
+#define fec_dcasm_pos 0
+#define fec_dcasm_len 3
+#define fec_dcasm_lsb 0
+#define    p_reg_dca_stand_alone    0xF73C
+#define reg_dca_stand_alone_pos 0
+#define reg_dca_stand_alone_len 1
+#define reg_dca_stand_alone_lsb 0
+#define    p_reg_dca_upper_out_en   0xF73D
+#define reg_dca_upper_out_en_pos 0
+#define reg_dca_upper_out_en_len 1
+#define reg_dca_upper_out_en_lsb 0
+#define    p_reg_dca_rc_en  0xF73E
+#define reg_dca_rc_en_pos 0
+#define reg_dca_rc_en_len 1
+#define reg_dca_rc_en_lsb 0
+#define    p_reg_dca_retrain_send   0xF73F
+#define reg_dca_retrain_send_pos 0
+#define reg_dca_retrain_send_len 1
+#define reg_dca_retrain_send_lsb 0
+#define    p_reg_dca_retrain_rec    0xF740
+#define reg_dca_retrain_rec_pos 0
+#define reg_dca_retrain_rec_len 1
+#define reg_dca_retrain_rec_lsb 0
+#define    p_reg_dca_gi_gap 0xF741
+#define reg_dca_gi_gap_pos 0
+#define reg_dca_gi_gap_len 8
+#define reg_dca_gi_gap_lsb 0
+#define    r_reg_dca_rec_up_tpsd_txmod  0xF742
+#define reg_dca_rec_up_tpsd_txmod_pos 0
+#define reg_dca_rec_up_tpsd_txmod_len 2
+#define reg_dca_rec_up_tpsd_txmod_lsb 0
+#define    r_reg_dca_rec_up_tpsd_const  0xF743
+#define reg_dca_rec_up_tpsd_const_pos 0
+#define reg_dca_rec_up_tpsd_const_len 2
+#define reg_dca_rec_up_tpsd_const_lsb 0
+#define    r_reg_dca_rec_up_tpsd_indep  0xF744
+#define reg_dca_rec_up_tpsd_indep_pos 0
+#define reg_dca_rec_up_tpsd_indep_len 1
+#define reg_dca_rec_up_tpsd_indep_lsb 0
+#define    r_reg_dca_rec_up_tpsd_hier   0xF745
+#define reg_dca_rec_up_tpsd_hier_pos 0
+#define reg_dca_rec_up_tpsd_hier_len 2
+#define reg_dca_rec_up_tpsd_hier_lsb 0
+#define    r_reg_dca_rec_up_tpsd_hpcr   0xF746
+#define reg_dca_rec_up_tpsd_hpcr_pos 0
+#define reg_dca_rec_up_tpsd_hpcr_len 3
+#define reg_dca_rec_up_tpsd_hpcr_lsb 0
+#define    r_reg_dca_rec_up_tpsd_lpcr   0xF747
+#define reg_dca_rec_up_tpsd_lpcr_pos 0
+#define reg_dca_rec_up_tpsd_lpcr_len 3
+#define reg_dca_rec_up_tpsd_lpcr_lsb 0
+#define    r_reg_dca_rec_up_tpsd_lock   0xF748
+#define reg_dca_rec_up_tpsd_lock_pos 0
+#define reg_dca_rec_up_tpsd_lock_len 1
+#define reg_dca_rec_up_tpsd_lock_lsb 0
+#define    r_reg_dca_rec_lo_tpsd_txmod  0xF749
+#define reg_dca_rec_lo_tpsd_txmod_pos 0
+#define reg_dca_rec_lo_tpsd_txmod_len 2
+#define reg_dca_rec_lo_tpsd_txmod_lsb 0
+#define    r_reg_dca_rec_lo_tpsd_const  0xF74A
+#define reg_dca_rec_lo_tpsd_const_pos 0
+#define reg_dca_rec_lo_tpsd_const_len 2
+#define reg_dca_rec_lo_tpsd_const_lsb 0
+#define    r_reg_dca_rec_lo_tpsd_indep  0xF74B
+#define reg_dca_rec_lo_tpsd_indep_pos 0
+#define reg_dca_rec_lo_tpsd_indep_len 1
+#define reg_dca_rec_lo_tpsd_indep_lsb 0
+#define    r_reg_dca_rec_lo_tpsd_hier   0xF74C
+#define reg_dca_rec_lo_tpsd_hier_pos 0
+#define reg_dca_rec_lo_tpsd_hier_len 2
+#define reg_dca_rec_lo_tpsd_hier_lsb 0
+#define    r_reg_dca_rec_lo_tpsd_hpcr   0xF74D
+#define reg_dca_rec_lo_tpsd_hpcr_pos 0
+#define reg_dca_rec_lo_tpsd_hpcr_len 3
+#define reg_dca_rec_lo_tpsd_hpcr_lsb 0
+#define    r_reg_dca_rec_lo_tpsd_lpcr   0xF74E
+#define reg_dca_rec_lo_tpsd_lpcr_pos 0
+#define reg_dca_rec_lo_tpsd_lpcr_len 3
+#define reg_dca_rec_lo_tpsd_lpcr_lsb 0
+#define    r_reg_dca_rec_lo_tpsd_lock   0xF74F
+#define reg_dca_rec_lo_tpsd_lock_pos 0
+#define reg_dca_rec_lo_tpsd_lock_len 1
+#define reg_dca_rec_lo_tpsd_lock_lsb 0
+#define    p_reg_dca_gpr_ctr_up_send    0xF750
+#define reg_dca_gpr_ctr_up_send_pos 0
+#define reg_dca_gpr_ctr_up_send_len 8
+#define reg_dca_gpr_ctr_up_send_lsb 0
+#define    p_reg_dca_gpr_dat_up_send_0  0xF751
+#define reg_dca_gpr_dat_up_send_0_pos 0
+#define reg_dca_gpr_dat_up_send_0_len 8
+#define reg_dca_gpr_dat_up_send_0_lsb 0
+#define    p_reg_dca_gpr_dat_up_send_1  0xF752
+#define reg_dca_gpr_dat_up_send_1_pos 0
+#define reg_dca_gpr_dat_up_send_1_len 8
+#define reg_dca_gpr_dat_up_send_1_lsb 0
+#define    p_reg_dca_gpr_dat_up_send_2  0xF753
+#define reg_dca_gpr_dat_up_send_2_pos 0
+#define reg_dca_gpr_dat_up_send_2_len 8
+#define reg_dca_gpr_dat_up_send_2_lsb 0
+#define    p_reg_dca_gpr_dat_up_send_3  0xF754
+#define reg_dca_gpr_dat_up_send_3_pos 0
+#define reg_dca_gpr_dat_up_send_3_len 8
+#define reg_dca_gpr_dat_up_send_3_lsb 0
+#define    p_reg_dca_gpr_dat_up_send_4  0xF755
+#define reg_dca_gpr_dat_up_send_4_pos 0
+#define reg_dca_gpr_dat_up_send_4_len 8
+#define reg_dca_gpr_dat_up_send_4_lsb 0
+#define    p_reg_dca_gpr_dat_up_send_5  0xF756
+#define reg_dca_gpr_dat_up_send_5_pos 0
+#define reg_dca_gpr_dat_up_send_5_len 8
+#define reg_dca_gpr_dat_up_send_5_lsb 0
+#define    p_reg_dca_over_wr_up_send    0xF757
+#define reg_dca_over_wr_up_send_pos 0
+#define reg_dca_over_wr_up_send_len 1
+#define reg_dca_over_wr_up_send_lsb 0
+#define    p_reg_dca_int_up_send    0xF758
+#define reg_dca_int_up_send_pos 0
+#define reg_dca_int_up_send_len 1
+#define reg_dca_int_up_send_lsb 0
+#define    p_reg_dca_gpr_ctr_lo_send    0xF759
+#define reg_dca_gpr_ctr_lo_send_pos 0
+#define reg_dca_gpr_ctr_lo_send_len 8
+#define reg_dca_gpr_ctr_lo_send_lsb 0
+#define    p_reg_dca_gpr_dat_lo_send_0  0xF75A
+#define reg_dca_gpr_dat_lo_send_0_pos 0
+#define reg_dca_gpr_dat_lo_send_0_len 8
+#define reg_dca_gpr_dat_lo_send_0_lsb 0
+#define    p_reg_dca_gpr_dat_lo_send_1  0xF75B
+#define reg_dca_gpr_dat_lo_send_1_pos 0
+#define reg_dca_gpr_dat_lo_send_1_len 8
+#define reg_dca_gpr_dat_lo_send_1_lsb 0
+#define    p_reg_dca_gpr_dat_lo_send_2  0xF75C
+#define reg_dca_gpr_dat_lo_send_2_pos 0
+#define reg_dca_gpr_dat_lo_send_2_len 8
+#define reg_dca_gpr_dat_lo_send_2_lsb 0
+#define    p_reg_dca_gpr_dat_lo_send_3  0xF75D
+#define reg_dca_gpr_dat_lo_send_3_pos 0
+#define reg_dca_gpr_dat_lo_send_3_len 8
+#define reg_dca_gpr_dat_lo_send_3_lsb 0
+#define    p_reg_dca_gpr_dat_lo_send_4  0xF75E
+#define reg_dca_gpr_dat_lo_send_4_pos 0
+#define reg_dca_gpr_dat_lo_send_4_len 8
+#define reg_dca_gpr_dat_lo_send_4_lsb 0
+#define    p_reg_dca_gpr_dat_lo_send_5  0xF75F
+#define reg_dca_gpr_dat_lo_send_5_pos 0
+#define reg_dca_gpr_dat_lo_send_5_len 8
+#define reg_dca_gpr_dat_lo_send_5_lsb 0
+#define    p_reg_dca_over_wr_lo_send    0xF760
+#define reg_dca_over_wr_lo_send_pos 0
+#define reg_dca_over_wr_lo_send_len 1
+#define reg_dca_over_wr_lo_send_lsb 0
+#define    p_reg_dca_int_lo_send    0xF761
+#define reg_dca_int_lo_send_pos 0
+#define reg_dca_int_lo_send_len 1
+#define reg_dca_int_lo_send_lsb 0
+#define    r_reg_dca_gpr_ctr_up_rec 0xF762
+#define reg_dca_gpr_ctr_up_rec_pos 0
+#define reg_dca_gpr_ctr_up_rec_len 8
+#define reg_dca_gpr_ctr_up_rec_lsb 0
+#define    r_reg_dca_gpr_dat_up_rec_0   0xF763
+#define reg_dca_gpr_dat_up_rec_0_pos 0
+#define reg_dca_gpr_dat_up_rec_0_len 8
+#define reg_dca_gpr_dat_up_rec_0_lsb 0
+#define    r_reg_dca_gpr_dat_up_rec_1   0xF764
+#define reg_dca_gpr_dat_up_rec_1_pos 0
+#define reg_dca_gpr_dat_up_rec_1_len 8
+#define reg_dca_gpr_dat_up_rec_1_lsb 0
+#define    r_reg_dca_gpr_dat_up_rec_2   0xF765
+#define reg_dca_gpr_dat_up_rec_2_pos 0
+#define reg_dca_gpr_dat_up_rec_2_len 8
+#define reg_dca_gpr_dat_up_rec_2_lsb 0
+#define    r_reg_dca_gpr_dat_up_rec_3   0xF766
+#define reg_dca_gpr_dat_up_rec_3_pos 0
+#define reg_dca_gpr_dat_up_rec_3_len 8
+#define reg_dca_gpr_dat_up_rec_3_lsb 0
+#define    r_reg_dca_gpr_dat_up_rec_4   0xF767
+#define reg_dca_gpr_dat_up_rec_4_pos 0
+#define reg_dca_gpr_dat_up_rec_4_len 8
+#define reg_dca_gpr_dat_up_rec_4_lsb 0
+#define    r_reg_dca_gpr_dat_up_rec_5   0xF768
+#define reg_dca_gpr_dat_up_rec_5_pos 0
+#define reg_dca_gpr_dat_up_rec_5_len 8
+#define reg_dca_gpr_dat_up_rec_5_lsb 0
+#define    r_reg_dca_over_wr_up_rec 0xF769
+#define reg_dca_over_wr_up_rec_pos 0
+#define reg_dca_over_wr_up_rec_len 1
+#define reg_dca_over_wr_up_rec_lsb 0
+#define    p_reg_dca_int_up_rec 0xF76A
+#define reg_dca_int_up_rec_pos 0
+#define reg_dca_int_up_rec_len 1
+#define reg_dca_int_up_rec_lsb 0
+#define    p_reg_dca_fw_read_yet_up 0xF76B
+#define reg_dca_fw_read_yet_up_pos 0
+#define reg_dca_fw_read_yet_up_len 1
+#define reg_dca_fw_read_yet_up_lsb 0
+#define    r_reg_dca_gpr_ctr_lo_rec 0xF76C
+#define reg_dca_gpr_ctr_lo_rec_pos 0
+#define reg_dca_gpr_ctr_lo_rec_len 8
+#define reg_dca_gpr_ctr_lo_rec_lsb 0
+#define    r_reg_dca_gpr_dat_lo_rec_0   0xF76D
+#define reg_dca_gpr_dat_lo_rec_0_pos 0
+#define reg_dca_gpr_dat_lo_rec_0_len 8
+#define reg_dca_gpr_dat_lo_rec_0_lsb 0
+#define    r_reg_dca_gpr_dat_lo_rec_1   0xF76E
+#define reg_dca_gpr_dat_lo_rec_1_pos 0
+#define reg_dca_gpr_dat_lo_rec_1_len 8
+#define reg_dca_gpr_dat_lo_rec_1_lsb 0
+#define    r_reg_dca_gpr_dat_lo_rec_2   0xF76F
+#define reg_dca_gpr_dat_lo_rec_2_pos 0
+#define reg_dca_gpr_dat_lo_rec_2_len 8
+#define reg_dca_gpr_dat_lo_rec_2_lsb 0
+#define    r_reg_dca_gpr_dat_lo_rec_3   0xF770
+#define reg_dca_gpr_dat_lo_rec_3_pos 0
+#define reg_dca_gpr_dat_lo_rec_3_len 8
+#define reg_dca_gpr_dat_lo_rec_3_lsb 0
+#define    r_reg_dca_gpr_dat_lo_rec_4   0xF771
+#define reg_dca_gpr_dat_lo_rec_4_pos 0
+#define reg_dca_gpr_dat_lo_rec_4_len 8
+#define reg_dca_gpr_dat_lo_rec_4_lsb 0
+#define    r_reg_dca_gpr_dat_lo_rec_5   0xF772
+#define reg_dca_gpr_dat_lo_rec_5_pos 0
+#define reg_dca_gpr_dat_lo_rec_5_len 8
+#define reg_dca_gpr_dat_lo_rec_5_lsb 0
+#define    r_reg_dca_over_wr_lo_rec 0xF773
+#define reg_dca_over_wr_lo_rec_pos 0
+#define reg_dca_over_wr_lo_rec_len 1
+#define reg_dca_over_wr_lo_rec_lsb 0
+#define    p_reg_dca_int_lo_rec 0xF774
+#define reg_dca_int_lo_rec_pos 0
+#define reg_dca_int_lo_rec_len 1
+#define reg_dca_int_lo_rec_lsb 0
+#define    p_reg_dca_fw_read_yet_lo 0xF775
+#define reg_dca_fw_read_yet_lo_pos 0
+#define reg_dca_fw_read_yet_lo_len 1
+#define reg_dca_fw_read_yet_lo_lsb 0
+#define    p_reg_dca_en 0xF776
+#define reg_dca_en_pos 0
+#define reg_dca_en_len 1
+#define reg_dca_en_lsb 0
+#define    p_reg_dca_ulrdy_delay    0xF777
+#define reg_dca_ulrdy_delay_pos 0
+#define reg_dca_ulrdy_delay_len 8
+#define reg_dca_ulrdy_delay_lsb 0
+#define    p_reg_dca_fpga_latch 0xF778
+#define reg_dca_fpga_latch_pos 0
+#define reg_dca_fpga_latch_len 8
+#define reg_dca_fpga_latch_lsb 0
+#define    p_reg_dca_vldld_err  0xF779
+#define reg_dca_vldld_err_pos 0
+#define reg_dca_vldld_err_len 1
+#define reg_dca_vldld_err_lsb 0
+#define    p_reg_dca_vldud_err  0xF77A
+#define reg_dca_vldud_err_pos 0
+#define reg_dca_vldud_err_len 1
+#define reg_dca_vldud_err_lsb 0
+#define    p_reg_dca_modeu_err  0xF77B
+#define reg_dca_modeu_err_pos 0
+#define reg_dca_modeu_err_len 1
+#define reg_dca_modeu_err_lsb 0
+#define    p_reg_dca_model_err  0xF77C
+#define reg_dca_model_err_pos 0
+#define reg_dca_model_err_len 1
+#define reg_dca_model_err_lsb 0
+#define    p_reg_dca_interrupt  0xF77D
+#define reg_dca_interrupt_pos 0
+#define reg_dca_interrupt_len 1
+#define reg_dca_interrupt_lsb 0
+#define    p_reg_dca_auto_reset_en  0xF77E
+#define reg_dca_auto_reset_en_pos 0
+#define reg_dca_auto_reset_en_len 1
+#define reg_dca_auto_reset_en_lsb 0
+#define    p_reg_qnt_valuew_7_0 0xF77F
+#define reg_qnt_valuew_7_0_pos 0
+#define reg_qnt_valuew_7_0_len 8
+#define reg_qnt_valuew_7_0_lsb 0
+#define    p_reg_qnt_valuew_10_8    0xF780
+#define reg_qnt_valuew_10_8_pos 0
+#define reg_qnt_valuew_10_8_len 3
+#define reg_qnt_valuew_10_8_lsb 8
+#define    p_reg_qnt_nfvaluew_7_0   0xF781
+#define reg_qnt_nfvaluew_7_0_pos 0
+#define reg_qnt_nfvaluew_7_0_len 8
+#define reg_qnt_nfvaluew_7_0_lsb 0
+#define    p_reg_qnt_nfvaluew_10_8  0xF782
+#define reg_qnt_nfvaluew_10_8_pos 0
+#define reg_qnt_nfvaluew_10_8_len 3
+#define reg_qnt_nfvaluew_10_8_lsb 8
+#define    p_reg_qnt_flatness_thr_7_0   0xF783
+#define reg_qnt_flatness_thr_7_0_pos 0
+#define reg_qnt_flatness_thr_7_0_len 8
+#define reg_qnt_flatness_thr_7_0_lsb 0
+#define    p_reg_qnt_flatness_thr_8 0xF784
+#define reg_qnt_flatness_thr_8_pos 0
+#define reg_qnt_flatness_thr_8_len 1
+#define reg_qnt_flatness_thr_8_lsb 8
+#define    p_reg_llr_to_be_monitor  0xF785
+#define reg_llr_to_be_monitor_pos 0
+#define reg_llr_to_be_monitor_len 1
+#define reg_llr_to_be_monitor_lsb 0
+#define    p_reg_qnt_vbc_rdy    0xF786
+#define reg_qnt_vbc_rdy_pos 0
+#define reg_qnt_vbc_rdy_len 1
+#define reg_qnt_vbc_rdy_lsb 0
+#define    p_reg_qnt_noncmb_vbc_rdy 0xF787
+#define reg_qnt_noncmb_vbc_rdy_pos 0
+#define reg_qnt_noncmb_vbc_rdy_len 1
+#define reg_qnt_noncmb_vbc_rdy_lsb 0
+#define    p_reg_use_eh2_mean   0xF788
+#define reg_use_eh2_mean_pos 0
+#define reg_use_eh2_mean_len 1
+#define reg_use_eh2_mean_lsb 0
+#define    p_reg_qnt_vbc_ccid_mode  0xF789
+#define reg_qnt_vbc_ccid_mode_pos 0
+#define reg_qnt_vbc_ccid_mode_len 1
+#define reg_qnt_vbc_ccid_mode_lsb 0
+#define    p_reg_qnt_cci_bandsize   0xF78A
+#define reg_qnt_cci_bandsize_pos 0
+#define reg_qnt_cci_bandsize_len 4
+#define reg_qnt_cci_bandsize_lsb 0
+#define    p_reg_qnt_vbc_sframe_num 0xF78B
+#define reg_qnt_vbc_sframe_num_pos 0
+#define reg_qnt_vbc_sframe_num_len 8
+#define reg_qnt_vbc_sframe_num_lsb 0
+#define    p_reg_sbx_gain_diff_7_0  0xF78C
+#define reg_sbx_gain_diff_7_0_pos 0
+#define reg_sbx_gain_diff_7_0_len 8
+#define reg_sbx_gain_diff_7_0_lsb 0
+#define    p_reg_sbx_gain_diff_8    0xF78D
+#define reg_sbx_gain_diff_8_pos 0
+#define reg_sbx_gain_diff_8_len 1
+#define reg_sbx_gain_diff_8_lsb 8
+#define    p_reg_sbx_gain_diff_rdy  0xF78E
+#define reg_sbx_gain_diff_rdy_pos 0
+#define reg_sbx_gain_diff_rdy_len 1
+#define reg_sbx_gain_diff_rdy_lsb 0
+#define    p_reg_sbx_noncmb_gain_diff_7_0   0xF78F
+#define reg_sbx_noncmb_gain_diff_7_0_pos 0
+#define reg_sbx_noncmb_gain_diff_7_0_len 8
+#define reg_sbx_noncmb_gain_diff_7_0_lsb 0
+#define    p_reg_sbx_noncmb_gain_diff_8 0xF790
+#define reg_sbx_noncmb_gain_diff_8_pos 0
+#define reg_sbx_noncmb_gain_diff_8_len 1
+#define reg_sbx_noncmb_gain_diff_8_lsb 8
+#define    p_reg_sbx_noncmb_gain_diff_rdy   0xF791
+#define reg_sbx_noncmb_gain_diff_rdy_pos 0
+#define reg_sbx_noncmb_gain_diff_rdy_len 1
+#define reg_sbx_noncmb_gain_diff_rdy_lsb 0
+#define    r_reg_qnt_vbc_err_7_0    0xF792
+#define reg_qnt_vbc_err_7_0_pos 0
+#define reg_qnt_vbc_err_7_0_len 8
+#define reg_qnt_vbc_err_7_0_lsb 0
+#define    r_reg_qnt_vbc_err_15_8   0xF793
+#define reg_qnt_vbc_err_15_8_pos 0
+#define reg_qnt_vbc_err_15_8_len 8
+#define reg_qnt_vbc_err_15_8_lsb 8
+#define    r_reg_qnt_vbc_err_23_16  0xF794
+#define reg_qnt_vbc_err_23_16_pos 0
+#define reg_qnt_vbc_err_23_16_len 8
+#define reg_qnt_vbc_err_23_16_lsb 16
+#define    r_reg_qnt_noncmb_vbc_err_7_0 0xF795
+#define reg_qnt_noncmb_vbc_err_7_0_pos 0
+#define reg_qnt_noncmb_vbc_err_7_0_len 8
+#define reg_qnt_noncmb_vbc_err_7_0_lsb 0
+#define    r_reg_qnt_noncmb_vbc_err_15_8    0xF796
+#define reg_qnt_noncmb_vbc_err_15_8_pos 0
+#define reg_qnt_noncmb_vbc_err_15_8_len 8
+#define reg_qnt_noncmb_vbc_err_15_8_lsb 8
+#define    r_reg_qnt_noncmb_vbc_err_23_16   0xF797
+#define reg_qnt_noncmb_vbc_err_23_16_pos 0
+#define reg_qnt_noncmb_vbc_err_23_16_len 8
+#define reg_qnt_noncmb_vbc_err_23_16_lsb 16
+#define    p_reg_sbx_signalquality_threshold    0xF798
+#define reg_sbx_signalquality_threshold_pos 0
+#define reg_sbx_signalquality_threshold_len 4
+#define reg_sbx_signalquality_threshold_lsb 0
+#define    r_reg_sbx_signalquality_ind  0xF799
+#define reg_sbx_signalquality_ind_pos 0
+#define reg_sbx_signalquality_ind_len 1
+#define reg_sbx_signalquality_ind_lsb 0
+#define    p_reg_p_sbxqnt_th1   0xF79A
+#define reg_p_sbxqnt_th1_pos 0
+#define reg_p_sbxqnt_th1_len 8
+#define reg_p_sbxqnt_th1_lsb 0
+#define    p_reg_p_sbxqnt_th2   0xF79B
+#define reg_p_sbxqnt_th2_pos 0
+#define reg_p_sbxqnt_th2_len 8
+#define reg_p_sbxqnt_th2_lsb 0
+#define    p_reg_p_sbxqnt_th3   0xF79C
+#define reg_p_sbxqnt_th3_pos 0
+#define reg_p_sbxqnt_th3_len 8
+#define reg_p_sbxqnt_th3_lsb 0
+#define    p_reg_p_sbxqnt_th4   0xF79D
+#define reg_p_sbxqnt_th4_pos 0
+#define reg_p_sbxqnt_th4_len 8
+#define reg_p_sbxqnt_th4_lsb 0
+#define    p_reg_p_sbxqnt_th5   0xF79E
+#define reg_p_sbxqnt_th5_pos 0
+#define reg_p_sbxqnt_th5_len 8
+#define reg_p_sbxqnt_th5_lsb 0
+#define    p_reg_p_sbxqnt_th6   0xF79F
+#define reg_p_sbxqnt_th6_pos 0
+#define reg_p_sbxqnt_th6_len 8
+#define reg_p_sbxqnt_th6_lsb 0
+#define    p_reg_p_sbxqnt_th7   0xF800
+#define reg_p_sbxqnt_th7_pos 0
+#define reg_p_sbxqnt_th7_len 8
+#define reg_p_sbxqnt_th7_lsb 0
+#define    p_reg_p_sbxqnt_th8   0xF801
+#define reg_p_sbxqnt_th8_pos 0
+#define reg_p_sbxqnt_th8_len 8
+#define reg_p_sbxqnt_th8_lsb 0
+#define    p_reg_p_sbxqnt_th9   0xF802
+#define reg_p_sbxqnt_th9_pos 0
+#define reg_p_sbxqnt_th9_len 8
+#define reg_p_sbxqnt_th9_lsb 0
+#define    p_reg_p_sbxqnt_th10  0xF803
+#define reg_p_sbxqnt_th10_pos 0
+#define reg_p_sbxqnt_th10_len 8
+#define reg_p_sbxqnt_th10_lsb 0
+#define    p_reg_p_sbxqnt_th11  0xF804
+#define reg_p_sbxqnt_th11_pos 0
+#define reg_p_sbxqnt_th11_len 8
+#define reg_p_sbxqnt_th11_lsb 0
+#define    p_reg_p_sbxqnt_th12  0xF805
+#define reg_p_sbxqnt_th12_pos 0
+#define reg_p_sbxqnt_th12_len 8
+#define reg_p_sbxqnt_th12_lsb 0
+#define    p_reg_p_sbxqnt_th13_7_0  0xF806
+#define reg_p_sbxqnt_th13_7_0_pos 0
+#define reg_p_sbxqnt_th13_7_0_len 8
+#define reg_p_sbxqnt_th13_7_0_lsb 0
+#define    p_reg_p_sbxqnt_th13_9_8  0xF807
+#define reg_p_sbxqnt_th13_9_8_pos 0
+#define reg_p_sbxqnt_th13_9_8_len 2
+#define reg_p_sbxqnt_th13_9_8_lsb 8
+#define    p_reg_p_sbxqnt_th14_7_0  0xF808
+#define reg_p_sbxqnt_th14_7_0_pos 0
+#define reg_p_sbxqnt_th14_7_0_len 8
+#define reg_p_sbxqnt_th14_7_0_lsb 0
+#define    p_reg_p_sbxqnt_th14_9_8  0xF809
+#define reg_p_sbxqnt_th14_9_8_pos 0
+#define reg_p_sbxqnt_th14_9_8_len 2
+#define reg_p_sbxqnt_th14_9_8_lsb 8
+#define    p_reg_p_sbxqnt_th15_7_0  0xF80A
+#define reg_p_sbxqnt_th15_7_0_pos 0
+#define reg_p_sbxqnt_th15_7_0_len 8
+#define reg_p_sbxqnt_th15_7_0_lsb 0
+#define    p_reg_p_sbxqnt_th15_9_8  0xF80B
+#define reg_p_sbxqnt_th15_9_8_pos 0
+#define reg_p_sbxqnt_th15_9_8_len 2
+#define reg_p_sbxqnt_th15_9_8_lsb 8
+#define    p_reg_p_sbxqnt_vzh2_th0  0xF80C
+#define reg_p_sbxqnt_vzh2_th0_pos 0
+#define reg_p_sbxqnt_vzh2_th0_len 8
+#define reg_p_sbxqnt_vzh2_th0_lsb 0
+#define    p_reg_p_sbxqnt_vzh2_th1  0xF80D
+#define reg_p_sbxqnt_vzh2_th1_pos 0
+#define reg_p_sbxqnt_vzh2_th1_len 8
+#define reg_p_sbxqnt_vzh2_th1_lsb 0
+#define    p_reg_p_sbxqnt_vzh2_th2  0xF80E
+#define reg_p_sbxqnt_vzh2_th2_pos 0
+#define reg_p_sbxqnt_vzh2_th2_len 8
+#define reg_p_sbxqnt_vzh2_th2_lsb 0
+#define    p_reg_p_qnt_w_comp1  0xF80F
+#define reg_p_qnt_w_comp1_pos 0
+#define reg_p_qnt_w_comp1_len 8
+#define reg_p_qnt_w_comp1_lsb 0
+#define    p_reg_p_qnt_w_comp2  0xF810
+#define reg_p_qnt_w_comp2_pos 0
+#define reg_p_qnt_w_comp2_len 8
+#define reg_p_qnt_w_comp2_lsb 0
+#define    p_reg_p_qnt_w_comp3  0xF811
+#define reg_p_qnt_w_comp3_pos 0
+#define reg_p_qnt_w_comp3_len 8
+#define reg_p_qnt_w_comp3_lsb 0
+#define    p_reg_p_vtb_in_0 0xF821
+#define reg_p_vtb_in_0_pos 0
+#define reg_p_vtb_in_0_len 6
+#define reg_p_vtb_in_0_lsb 0
+#define    p_reg_p_vtb_in_1 0xF822
+#define reg_p_vtb_in_1_pos 0
+#define reg_p_vtb_in_1_len 6
+#define reg_p_vtb_in_1_lsb 0
+#define    p_reg_p_vtb_in_2 0xF823
+#define reg_p_vtb_in_2_pos 0
+#define reg_p_vtb_in_2_len 6
+#define reg_p_vtb_in_2_lsb 0
+#define    p_reg_p_vtb_in_3 0xF824
+#define reg_p_vtb_in_3_pos 0
+#define reg_p_vtb_in_3_len 6
+#define reg_p_vtb_in_3_lsb 0
+#define    p_reg_p_vtb_in_4 0xF825
+#define reg_p_vtb_in_4_pos 0
+#define reg_p_vtb_in_4_len 6
+#define reg_p_vtb_in_4_lsb 0
+#define    p_reg_p_vtb_in_5 0xF826
+#define reg_p_vtb_in_5_pos 0
+#define reg_p_vtb_in_5_len 6
+#define reg_p_vtb_in_5_lsb 0
+#define    p_reg_p_vtb_in_6 0xF827
+#define reg_p_vtb_in_6_pos 0
+#define reg_p_vtb_in_6_len 6
+#define reg_p_vtb_in_6_lsb 0
+#define    p_reg_p_vtb_in_7 0xF828
+#define reg_p_vtb_in_7_pos 0
+#define reg_p_vtb_in_7_len 6
+#define reg_p_vtb_in_7_lsb 0
+#define    p_reg_p_vtb_in_8 0xF829
+#define reg_p_vtb_in_8_pos 0
+#define reg_p_vtb_in_8_len 6
+#define reg_p_vtb_in_8_lsb 0
+#define    p_reg_p_vtb_in_9 0xF82A
+#define reg_p_vtb_in_9_pos 0
+#define reg_p_vtb_in_9_len 6
+#define reg_p_vtb_in_9_lsb 0
+#define    p_reg_p_vtb_in_10    0xF82B
+#define reg_p_vtb_in_10_pos 0
+#define reg_p_vtb_in_10_len 6
+#define reg_p_vtb_in_10_lsb 0
+#define    p_reg_p_vtb_in_11    0xF82C
+#define reg_p_vtb_in_11_pos 0
+#define reg_p_vtb_in_11_len 6
+#define reg_p_vtb_in_11_lsb 0
+#define    p_reg_p_vtb_in_12    0xF82D
+#define reg_p_vtb_in_12_pos 0
+#define reg_p_vtb_in_12_len 6
+#define reg_p_vtb_in_12_lsb 0
+#define    p_reg_p_vtb_in_13    0xF82E
+#define reg_p_vtb_in_13_pos 0
+#define reg_p_vtb_in_13_len 6
+#define reg_p_vtb_in_13_lsb 0
+#define    p_reg_p_vtb_in_14    0xF82F
+#define reg_p_vtb_in_14_pos 0
+#define reg_p_vtb_in_14_len 6
+#define reg_p_vtb_in_14_lsb 0
+#define    p_reg_p_vtb_in_15    0xF830
+#define reg_p_vtb_in_15_pos 0
+#define reg_p_vtb_in_15_len 6
+#define reg_p_vtb_in_15_lsb 0
+#define    I2C_i2c_m_slave_addr 0xF940
+#define i2c_m_slave_addr_pos 0
+#define i2c_m_slave_addr_len 8
+#define i2c_m_slave_addr_lsb 0
+#define    I2C_i2c_m_data1  0xF941
+#define i2c_m_data1_pos 0
+#define i2c_m_data1_len 8
+#define i2c_m_data1_lsb 0
+#define    I2C_i2c_m_data2  0xF942
+#define i2c_m_data2_pos 0
+#define i2c_m_data2_len 8
+#define i2c_m_data2_lsb 0
+#define    I2C_i2c_m_data3  0xF943
+#define i2c_m_data3_pos 0
+#define i2c_m_data3_len 8
+#define i2c_m_data3_lsb 0
+#define    I2C_i2c_m_data4  0xF944
+#define i2c_m_data4_pos 0
+#define i2c_m_data4_len 8
+#define i2c_m_data4_lsb 0
+#define    I2C_i2c_m_data5  0xF945
+#define i2c_m_data5_pos 0
+#define i2c_m_data5_len 8
+#define i2c_m_data5_lsb 0
+#define    I2C_i2c_m_data6  0xF946
+#define i2c_m_data6_pos 0
+#define i2c_m_data6_len 8
+#define i2c_m_data6_lsb 0
+#define    I2C_i2c_m_data7  0xF947
+#define i2c_m_data7_pos 0
+#define i2c_m_data7_len 8
+#define i2c_m_data7_lsb 0
+#define    I2C_i2c_m_data8  0xF948
+#define i2c_m_data8_pos 0
+#define i2c_m_data8_len 8
+#define i2c_m_data8_lsb 0
+#define    I2C_i2c_m_data9  0xF949
+#define i2c_m_data9_pos 0
+#define i2c_m_data9_len 8
+#define i2c_m_data9_lsb 0
+#define    I2C_i2c_m_data10 0xF94A
+#define i2c_m_data10_pos 0
+#define i2c_m_data10_len 8
+#define i2c_m_data10_lsb 0
+#define    I2C_i2c_m_data11 0xF94B
+#define i2c_m_data11_pos 0
+#define i2c_m_data11_len 8
+#define i2c_m_data11_lsb 0
+#define    I2C_i2c_m_data12 0xF94C
+#define i2c_m_data12_pos 0
+#define i2c_m_data12_len 8
+#define i2c_m_data12_lsb 0
+#define    I2C_i2c_m_data13 0xF94D
+#define i2c_m_data13_pos 0
+#define i2c_m_data13_len 8
+#define i2c_m_data13_lsb 0
+#define    I2C_i2c_m_data14 0xF94E
+#define i2c_m_data14_pos 0
+#define i2c_m_data14_len 8
+#define i2c_m_data14_lsb 0
+#define    I2C_i2c_m_data15 0xF94F
+#define i2c_m_data15_pos 0
+#define i2c_m_data15_len 8
+#define i2c_m_data15_lsb 0
+#define    I2C_i2c_m_data16 0xF950
+#define i2c_m_data16_pos 0
+#define i2c_m_data16_len 8
+#define i2c_m_data16_lsb 0
+#define    I2C_i2c_m_data17 0xF951
+#define i2c_m_data17_pos 0
+#define i2c_m_data17_len 8
+#define i2c_m_data17_lsb 0
+#define    I2C_i2c_m_data18 0xF952
+#define i2c_m_data18_pos 0
+#define i2c_m_data18_len 8
+#define i2c_m_data18_lsb 0
+#define    I2C_i2c_m_data19 0xF953
+#define i2c_m_data19_pos 0
+#define i2c_m_data19_len 8
+#define i2c_m_data19_lsb 0
+#define    I2C_i2c_m_cmd_rw 0xF954
+#define i2c_m_cmd_rw_pos 0
+#define i2c_m_cmd_rw_len 1
+#define i2c_m_cmd_rw_lsb 0
+#define    I2C_i2c_m_cmd_rwlen  0xF954
+#define i2c_m_cmd_rwlen_pos 3
+#define i2c_m_cmd_rwlen_len 4
+#define i2c_m_cmd_rwlen_lsb 0
+#define    I2C_i2c_m_status_cmd_exe 0xF955
+#define i2c_m_status_cmd_exe_pos 0
+#define i2c_m_status_cmd_exe_len 1
+#define i2c_m_status_cmd_exe_lsb 0
+#define    I2C_i2c_m_status_wdat_done   0xF955
+#define i2c_m_status_wdat_done_pos 1
+#define i2c_m_status_wdat_done_len 1
+#define i2c_m_status_wdat_done_lsb 0
+#define    I2C_i2c_m_status_wdat_fail   0xF955
+#define i2c_m_status_wdat_fail_pos 2
+#define i2c_m_status_wdat_fail_len 1
+#define i2c_m_status_wdat_fail_lsb 0
+#define    I2C_i2c_m_status_rdat_rdy    0xF955
+#define i2c_m_status_rdat_rdy_pos 3
+#define i2c_m_status_rdat_rdy_len 1
+#define i2c_m_status_rdat_rdy_lsb 0
+#define    I2C_i2c_m_period 0xF956
+#define i2c_m_period_pos 0
+#define i2c_m_period_len 8
+#define i2c_m_period_lsb 0
+#define    I2C_i2c_m_reg_msb_lsb    0xF957
+#define i2c_m_reg_msb_lsb_pos 0
+#define i2c_m_reg_msb_lsb_len 1
+#define i2c_m_reg_msb_lsb_lsb 0
+#define    I2C_reg_ofdm_rst 0xF957
+#define reg_ofdm_rst_pos 1
+#define reg_ofdm_rst_len 1
+#define reg_ofdm_rst_lsb 0
+#define    I2C_reg_sample_period_on_tuner   0xF957
+#define reg_sample_period_on_tuner_pos 2
+#define reg_sample_period_on_tuner_len 1
+#define reg_sample_period_on_tuner_lsb 0
+#define    I2C_reg_sel_tuner    0xF957
+#define reg_sel_tuner_pos 3
+#define reg_sel_tuner_len 1
+#define reg_sel_tuner_lsb 0
+#define    I2C_reg_ofdm_rst_en  0xF957
+#define reg_ofdm_rst_en_pos 4
+#define reg_ofdm_rst_en_len 1
+#define reg_ofdm_rst_en_lsb 0
+#define    p_mp2if_psb_overflow 0xF980
+#define mp2if_psb_overflow_pos 0
+#define mp2if_psb_overflow_len 1
+#define mp2if_psb_overflow_lsb 0
+#define    p_mp2if_no_modify_tei_bit    0xF981
+#define mp2if_no_modify_tei_bit_pos 0
+#define mp2if_no_modify_tei_bit_len 1
+#define mp2if_no_modify_tei_bit_lsb 0
+#define    p_mp2if_keep_sf_sync_byte    0xF982
+#define mp2if_keep_sf_sync_byte_pos 0
+#define mp2if_keep_sf_sync_byte_len 1
+#define mp2if_keep_sf_sync_byte_lsb 0
+#define    p_mp2if_data_access_disable  0xF983
+#define mp2if_data_access_disable_pos 0
+#define mp2if_data_access_disable_len 1
+#define mp2if_data_access_disable_lsb 0
+#define    p_mp2if_mpeg_ser_do7 0xF984
+#define mp2if_mpeg_ser_do7_pos 0
+#define mp2if_mpeg_ser_do7_len 1
+#define mp2if_mpeg_ser_do7_lsb 0
+#define    p_mp2if_mpeg_ser_mode    0xF985
+#define mp2if_mpeg_ser_mode_pos 0
+#define mp2if_mpeg_ser_mode_len 1
+#define mp2if_mpeg_ser_mode_lsb 0
+#define    p_mp2if_mpeg_par_mode    0xF986
+#define mp2if_mpeg_par_mode_pos 0
+#define mp2if_mpeg_par_mode_len 1
+#define mp2if_mpeg_par_mode_lsb 0
+#define    r_mp2if_psb_empty    0xF987
+#define mp2if_psb_empty_pos 0
+#define mp2if_psb_empty_len 1
+#define mp2if_psb_empty_lsb 0
+#define    r_mp2if_ts_not_188   0xF988
+#define mp2if_ts_not_188_pos 0
+#define mp2if_ts_not_188_len 1
+#define mp2if_ts_not_188_lsb 0
+#define    p_mp2if_mssync_len   0xF989
+#define mp2if_mssync_len_pos 0
+#define mp2if_mssync_len_len 1
+#define mp2if_mssync_len_lsb 0
+#define    p_mp2if_msdo_msb 0xF98A
+#define mp2if_msdo_msb_pos 0
+#define mp2if_msdo_msb_len 1
+#define mp2if_msdo_msb_lsb 0
+#define    p_mp2if_mpeg_clk_gated   0xF98B
+#define mp2if_mpeg_clk_gated_pos 0
+#define mp2if_mpeg_clk_gated_len 1
+#define mp2if_mpeg_clk_gated_lsb 0
+#define    p_mp2if_mpeg_err_pol 0xF98C
+#define mp2if_mpeg_err_pol_pos 0
+#define mp2if_mpeg_err_pol_len 1
+#define mp2if_mpeg_err_pol_lsb 0
+#define    p_mp2if_mpeg_sync_pol    0xF98D
+#define mp2if_mpeg_sync_pol_pos 0
+#define mp2if_mpeg_sync_pol_len 1
+#define mp2if_mpeg_sync_pol_lsb 0
+#define    p_mp2if_mpeg_vld_pol 0xF98E
+#define mp2if_mpeg_vld_pol_pos 0
+#define mp2if_mpeg_vld_pol_len 1
+#define mp2if_mpeg_vld_pol_lsb 0
+#define    p_mp2if_mpeg_clk_pol 0xF98F
+#define mp2if_mpeg_clk_pol_pos 0
+#define mp2if_mpeg_clk_pol_len 1
+#define mp2if_mpeg_clk_pol_lsb 0
+#define    p_reg_mpeg_full_speed    0xF990
+#define reg_mpeg_full_speed_pos 0
+#define reg_mpeg_full_speed_len 1
+#define reg_mpeg_full_speed_lsb 0
+#define    p_mp2if_pid_complement   0xF991
+#define mp2if_pid_complement_pos 0
+#define mp2if_pid_complement_len 1
+#define mp2if_pid_complement_lsb 0
+#define    p_mp2if_pid_rst  0xF992
+#define mp2if_pid_rst_pos 0
+#define mp2if_pid_rst_len 1
+#define mp2if_pid_rst_lsb 0
+#define    p_mp2if_pid_en   0xF993
+#define mp2if_pid_en_pos 0
+#define mp2if_pid_en_len 1
+#define mp2if_pid_en_lsb 0
+#define    p_mp2if_pid_index_en 0xF994
+#define mp2if_pid_index_en_pos 0
+#define mp2if_pid_index_en_len 1
+#define mp2if_pid_index_en_lsb 0
+#define    p_mp2if_pid_index    0xF995
+#define mp2if_pid_index_pos 0
+#define mp2if_pid_index_len 5
+#define mp2if_pid_index_lsb 0
+#define    p_mp2if_pid_dat_l    0xF996
+#define mp2if_pid_dat_l_pos 0
+#define mp2if_pid_dat_l_len 8
+#define mp2if_pid_dat_l_lsb 0
+#define    p_mp2if_pid_dat_h    0xF997
+#define mp2if_pid_dat_h_pos 0
+#define mp2if_pid_dat_h_len 5
+#define mp2if_pid_dat_h_lsb 0
+#define    p_reg_latch_clk  0xF998
+#define reg_latch_clk_pos 0
+#define reg_latch_clk_len 1
+#define reg_latch_clk_lsb 0
+#define    r_mp2if_sync_byte_locked 0xF999
+#define mp2if_sync_byte_locked_pos 0
+#define mp2if_sync_byte_locked_len 1
+#define mp2if_sync_byte_locked_lsb 0
+#define    p_mp2if_ignore_sync_byte 0xF99A
+#define mp2if_ignore_sync_byte_pos 0
+#define mp2if_ignore_sync_byte_len 1
+#define mp2if_ignore_sync_byte_lsb 0
+#define    p_reg_mp2if_clk_en   0xF99B
+#define reg_mp2if_clk_en_pos 0
+#define reg_mp2if_clk_en_len 1
+#define reg_mp2if_clk_en_lsb 0
+#define    p_reg_mpeg_vld_tgl   0xF99C
+#define reg_mpeg_vld_tgl_pos 0
+#define reg_mpeg_vld_tgl_len 1
+#define reg_mpeg_vld_tgl_lsb 0
+#define    p_reg_mp2_sw_rst 0xF99D
+#define reg_mp2_sw_rst_pos 0
+#define reg_mp2_sw_rst_len 1
+#define reg_mp2_sw_rst_lsb 0
+#define    p_mp2if_psb_en   0xF99E
+#define mp2if_psb_en_pos 0
+#define mp2if_psb_en_len 1
+#define mp2if_psb_en_lsb 0
+#define    r_mp2if_usb20_mode   0xF99F
+#define mp2if_usb20_mode_pos 0
+#define mp2if_usb20_mode_len 1
+#define mp2if_usb20_mode_lsb 0
+#define    r_mp2if_strap_usb20_mode 0xF9A0
+#define mp2if_strap_usb20_mode_pos 0
+#define mp2if_strap_usb20_mode_len 1
+#define mp2if_strap_usb20_mode_lsb 0
+#define    r_mp2if_lost_pkt_cnt_l   0xF9A1
+#define mp2if_lost_pkt_cnt_l_pos 0
+#define mp2if_lost_pkt_cnt_l_len 8
+#define mp2if_lost_pkt_cnt_l_lsb 0
+#define    r_mp2if_lost_pkt_cnt_h   0xF9A2
+#define mp2if_lost_pkt_cnt_h_pos 0
+#define mp2if_lost_pkt_cnt_h_len 8
+#define mp2if_lost_pkt_cnt_h_lsb 0
+#define    p_reg_mp2if2_en  0xF9A3
+#define reg_mp2if2_en_pos 0
+#define reg_mp2if2_en_len 1
+#define reg_mp2if2_en_lsb 0
+#define    p_reg_mp2if2_sw_rst  0xF9A4
+#define reg_mp2if2_sw_rst_pos 0
+#define reg_mp2if2_sw_rst_len 1
+#define reg_mp2if2_sw_rst_lsb 0
+#define    p_reg_mp2if2_half_psb    0xF9A5
+#define reg_mp2if2_half_psb_pos 0
+#define reg_mp2if2_half_psb_len 1
+#define reg_mp2if2_half_psb_lsb 0
+#define    p_reg_ts_byte_endian 0xF9A6
+#define reg_ts_byte_endian_pos 0
+#define reg_ts_byte_endian_len 1
+#define reg_ts_byte_endian_lsb 0
+#define    p_reg_mp2_dioif  0xF9A7
+#define reg_mp2_dioif_pos 0
+#define reg_mp2_dioif_len 1
+#define reg_mp2_dioif_lsb 0
+#define    p_reg_mp2_dioif_fast 0xF9A8
+#define reg_mp2_dioif_fast_pos 0
+#define reg_mp2_dioif_fast_len 1
+#define reg_mp2_dioif_fast_lsb 0
+#define    p_reg_tpsd_bw_mp2if  0xF9A9
+#define reg_tpsd_bw_mp2if_pos 0
+#define reg_tpsd_bw_mp2if_len 2
+#define reg_tpsd_bw_mp2if_lsb 0
+#define    p_reg_tpsd_gi_mp2if  0xF9AA
+#define reg_tpsd_gi_mp2if_pos 0
+#define reg_tpsd_gi_mp2if_len 2
+#define reg_tpsd_gi_mp2if_lsb 0
+#define    p_reg_tpsd_cr_mp2if  0xF9AB
+#define reg_tpsd_cr_mp2if_pos 0
+#define reg_tpsd_cr_mp2if_len 3
+#define reg_tpsd_cr_mp2if_lsb 0
+#define    p_reg_tpsd_cons_mp2if    0xF9AC
+#define reg_tpsd_cons_mp2if_pos 0
+#define reg_tpsd_cons_mp2if_len 2
+#define reg_tpsd_cons_mp2if_lsb 0
+#define    p_reg_fw_table_en    0xF9AD
+#define reg_fw_table_en_pos 0
+#define reg_fw_table_en_len 1
+#define reg_fw_table_en_lsb 0
+#define    p_reg_p_aud_pk_gen_aud_pk_size   0xF9AD
+#define reg_p_aud_pk_gen_aud_pk_size_pos 1
+#define reg_p_aud_pk_gen_aud_pk_size_len 6
+#define reg_p_aud_pk_gen_aud_pk_size_lsb 0
+#define    p_mp2if_psb_num_blk  0xF9AE
+#define mp2if_psb_num_blk_pos 0
+#define mp2if_psb_num_blk_len 6
+#define mp2if_psb_num_blk_lsb 0
+#define    p_reg_fec_fake   0xF9AF
+#define reg_fec_fake_pos 0
+#define reg_fec_fake_len 1
+#define reg_fec_fake_lsb 0
+#define    p_reg_p_ccir_atv_en  0xF9AF
+#define reg_p_ccir_atv_en_pos 1
+#define reg_p_ccir_atv_en_len 1
+#define reg_p_ccir_atv_en_lsb 0
+#define    p_reg_video_stop_n   0xF9AF
+#define reg_video_stop_n_pos 2
+#define reg_video_stop_n_len 1
+#define reg_video_stop_n_lsb 0
+#define    p_reg_audio_stop_n   0xF9AF
+#define reg_audio_stop_n_pos 3
+#define reg_audio_stop_n_len 1
+#define reg_audio_stop_n_lsb 0
+#define    p_mp2if_i2smode  0xF9AF
+#define mp2if_i2smode_pos 4
+#define mp2if_i2smode_len 2
+#define mp2if_i2smode_lsb 0
+#define    p_mp2if_word_size    0xF9AF
+#define mp2if_word_size_pos 6
+#define mp2if_word_size_len 2
+#define mp2if_word_size_lsb 0
+#define    p_reg_packet_gap 0xF9B0
+#define reg_packet_gap_pos 0
+#define reg_packet_gap_len 8
+#define reg_packet_gap_lsb 0
+#define    p_reg_ts_dat_inv 0xF9B2
+#define reg_ts_dat_inv_pos 0
+#define reg_ts_dat_inv_len 1
+#define reg_ts_dat_inv_lsb 0
+#define    p_reg_ts_lsb_1st 0xF9B3
+#define reg_ts_lsb_1st_pos 0
+#define reg_ts_lsb_1st_len 1
+#define reg_ts_lsb_1st_lsb 0
+#define    p_reg_ts_capt_bg_sel 0xF9B4
+#define reg_ts_capt_bg_sel_pos 0
+#define reg_ts_capt_bg_sel_len 1
+#define reg_ts_capt_bg_sel_lsb 0
+#define    p_reg_mp2if_stop_en  0xF9B5
+#define reg_mp2if_stop_en_pos 0
+#define reg_mp2if_stop_en_len 1
+#define reg_mp2if_stop_en_lsb 0
+#define    p_reg_mp2if2_pes_base    0xF9B6
+#define reg_mp2if2_pes_base_pos 0
+#define reg_mp2if2_pes_base_len 1
+#define reg_mp2if2_pes_base_lsb 0
+#define    p_reg_ts_sync_inv    0xF9B7
+#define reg_ts_sync_inv_pos 0
+#define reg_ts_sync_inv_len 1
+#define reg_ts_sync_inv_lsb 0
+#define    p_reg_ts_vld_inv 0xF9B8
+#define reg_ts_vld_inv_pos 0
+#define reg_ts_vld_inv_len 1
+#define reg_ts_vld_inv_lsb 0
+#define    p_reg_sys_buf_overflow   0xF9B9
+#define reg_sys_buf_overflow_pos 0
+#define reg_sys_buf_overflow_len 1
+#define reg_sys_buf_overflow_lsb 0
+#define    p_reg_top_dummy0 0xF9BB
+#define reg_top_dummy0_pos 0
+#define reg_top_dummy0_len 8
+#define reg_top_dummy0_lsb 0
+#define    p_reg_top_dummy1 0xF9BC
+#define reg_top_dummy1_pos 0
+#define reg_top_dummy1_len 8
+#define reg_top_dummy1_lsb 0
+#define    p_reg_top_dummy2 0xF9BD
+#define reg_top_dummy2_pos 0
+#define reg_top_dummy2_len 8
+#define reg_top_dummy2_lsb 0
+#define    p_reg_top_dummy3 0xF9BE
+#define reg_top_dummy3_pos 0
+#define reg_top_dummy3_len 8
+#define reg_top_dummy3_lsb 0
+#define    p_reg_top_dummy4 0xF9BF
+#define reg_top_dummy4_pos 0
+#define reg_top_dummy4_len 8
+#define reg_top_dummy4_lsb 0
+#define    p_reg_top_dummy5 0xF9C0
+#define reg_top_dummy5_pos 0
+#define reg_top_dummy5_len 8
+#define reg_top_dummy5_lsb 0
+#define    p_reg_top_dummy6 0xF9C1
+#define reg_top_dummy6_pos 0
+#define reg_top_dummy6_len 8
+#define reg_top_dummy6_lsb 0
+#define    p_reg_top_dummy7 0xF9C2
+#define reg_top_dummy7_pos 0
+#define reg_top_dummy7_len 8
+#define reg_top_dummy7_lsb 0
+#define    p_reg_top_dummy8 0xF9C3
+#define reg_top_dummy8_pos 0
+#define reg_top_dummy8_len 8
+#define reg_top_dummy8_lsb 0
+#define    p_reg_top_dummy9 0xF9C4
+#define reg_top_dummy9_pos 0
+#define reg_top_dummy9_len 8
+#define reg_top_dummy9_lsb 0
+#define    p_reg_top_dummyA 0xF9C5
+#define reg_top_dummyA_pos 0
+#define reg_top_dummyA_len 8
+#define reg_top_dummyA_lsb 0
+#define    p_reg_top_dummyB 0xF9C6
+#define reg_top_dummyB_pos 0
+#define reg_top_dummyB_len 8
+#define reg_top_dummyB_lsb 0
+#define    p_reg_top_dummyC 0xF9C7
+#define reg_top_dummyC_pos 0
+#define reg_top_dummyC_len 8
+#define reg_top_dummyC_lsb 0
+#define    p_reg_top_dummyD 0xF9C8
+#define reg_top_dummyD_pos 0
+#define reg_top_dummyD_len 8
+#define reg_top_dummyD_lsb 0
+#define    p_reg_top_dummyE 0xF9C9
+#define reg_top_dummyE_pos 0
+#define reg_top_dummyE_len 8
+#define reg_top_dummyE_lsb 0
+#define    p_reg_top_dummyF 0xF9CA
+#define reg_top_dummyF_pos 0
+#define reg_top_dummyF_len 8
+#define reg_top_dummyF_lsb 0
+#define    p_reg_mp2if_clk_coeff    0xF9CB
+#define reg_mp2if_clk_coeff_pos 0
+#define reg_mp2if_clk_coeff_len 7
+#define reg_mp2if_clk_coeff_lsb 0
+#define    p_reg_tsip_en    0xF9CC
+#define reg_tsip_en_pos 0
+#define reg_tsip_en_len 1
+#define reg_tsip_en_lsb 0
+#define    p_reg_tsis_en    0xF9CD
+#define reg_tsis_en_pos 0
+#define reg_tsis_en_len 1
+#define reg_tsis_en_lsb 0
+#define    p_reg_tsip_br    0xF9CE
+#define reg_tsip_br_pos 0
+#define reg_tsip_br_len 1
+#define reg_tsip_br_lsb 0
+#define    p_reg_tsip_frm_inv   0xF9D0
+#define reg_tsip_frm_inv_pos 0
+#define reg_tsip_frm_inv_len 1
+#define reg_tsip_frm_inv_lsb 0
+#define    p_reg_tsip_str_inv   0xF9D1
+#define reg_tsip_str_inv_pos 0
+#define reg_tsip_str_inv_len 1
+#define reg_tsip_str_inv_lsb 0
+#define    p_reg_tsip_fail_inv  0xF9D2
+#define reg_tsip_fail_inv_pos 0
+#define reg_tsip_fail_inv_len 1
+#define reg_tsip_fail_inv_lsb 0
+#define    p_reg_tsip_frm_ignore    0xF9D3
+#define reg_tsip_frm_ignore_pos 0
+#define reg_tsip_frm_ignore_len 1
+#define reg_tsip_frm_ignore_lsb 0
+#define    p_reg_tsip_str_ignore    0xF9D4
+#define reg_tsip_str_ignore_pos 0
+#define reg_tsip_str_ignore_len 1
+#define reg_tsip_str_ignore_lsb 0
+#define    p_reg_tsip_fail_ignore   0xF9D5
+#define reg_tsip_fail_ignore_pos 0
+#define reg_tsip_fail_ignore_len 1
+#define reg_tsip_fail_ignore_lsb 0
+#define    p_reg_tsip_endian    0xF9D6
+#define reg_tsip_endian_pos 0
+#define reg_tsip_endian_len 1
+#define reg_tsip_endian_lsb 0
+#define    p_reg_tsip_overflow  0xF9D7
+#define reg_tsip_overflow_pos 0
+#define reg_tsip_overflow_len 1
+#define reg_tsip_overflow_lsb 0
+#define    p_reg_ts_in_src  0xF9D8
+#define reg_ts_in_src_pos 0
+#define reg_ts_in_src_len 1
+#define reg_ts_in_src_lsb 0
+#define    r_reg_clk_sel    0xF9D9
+#define reg_clk_sel_pos 0
+#define reg_clk_sel_len 2
+#define reg_clk_sel_lsb 0
+#define    r_reg_tog_sel    0xF9DA
+#define reg_tog_sel_pos 0
+#define reg_tog_sel_len 2
+#define reg_tog_sel_lsb 0
+#define    p_reg_ts_str_ignore  0xF9DB
+#define reg_ts_str_ignore_pos 0
+#define reg_ts_str_ignore_len 1
+#define reg_ts_str_ignore_lsb 0
+#define    p_reg_ts_frm_ignore  0xF9DC
+#define reg_ts_frm_ignore_pos 0
+#define reg_ts_frm_ignore_len 1
+#define reg_ts_frm_ignore_lsb 0
+#define    p_reg_clk_sel_fix    0xF9DD
+#define reg_clk_sel_fix_pos 0
+#define reg_clk_sel_fix_len 2
+#define reg_clk_sel_fix_lsb 0
+#define    p_reg_tog_sel_fix    0xF9DE
+#define reg_tog_sel_fix_pos 0
+#define reg_tog_sel_fix_len 2
+#define reg_tog_sel_fix_lsb 0
+#define    p_reg_en_fix 0xF9DF
+#define reg_en_fix_pos 0
+#define reg_en_fix_len 1
+#define reg_en_fix_lsb 0
+#define    p_reg_check_tpsd_hier    0xF9E0
+#define reg_check_tpsd_hier_pos 0
+#define reg_check_tpsd_hier_len 1
+#define reg_check_tpsd_hier_lsb 0
+#define    p_reg_p_i2s_master_mode  0xF9E1
+#define reg_p_i2s_master_mode_pos 0
+#define reg_p_i2s_master_mode_len 1
+#define reg_p_i2s_master_mode_lsb 0
+#define    p_reg_p_sc_lr_ratio  0xF9E2
+#define reg_p_sc_lr_ratio_pos 0
+#define reg_p_sc_lr_ratio_len 2
+#define reg_p_sc_lr_ratio_lsb 0
+#define    p_reg_p_i2s_fs_type  0xF9E2
+#define reg_p_i2s_fs_type_pos 2
+#define reg_p_i2s_fs_type_len 2
+#define reg_p_i2s_fs_type_lsb 0
+#define    r_reg_r_pp_fullq 0xF9E3
+#define reg_r_pp_fullq_pos 0
+#define reg_r_pp_fullq_len 1
+#define reg_r_pp_fullq_lsb 0
+#define    p_reg_r_ccir_rst 0xF9E3
+#define reg_r_ccir_rst_pos 1
+#define reg_r_ccir_rst_len 1
+#define reg_r_ccir_rst_lsb 0
+#define    p_reg_p_full_en  0xF9E3
+#define reg_p_full_en_pos 2
+#define reg_p_full_en_len 1
+#define reg_p_full_en_lsb 0
+#define    p_reg_p_vbi_dis  0xF9E3
+#define reg_p_vbi_dis_pos 3
+#define reg_p_vbi_dis_len 1
+#define reg_p_vbi_dis_lsb 0
+#define    p_reg_p_ccir_all 0xF9E3
+#define reg_p_ccir_all_pos 4
+#define reg_p_ccir_all_len 1
+#define reg_p_ccir_all_lsb 0
+#define    p_reg_p_ccir_vbi_raw_en  0xF9E3
+#define reg_p_ccir_vbi_raw_en_pos 5
+#define reg_p_ccir_vbi_raw_en_len 1
+#define reg_p_ccir_vbi_raw_en_lsb 0
+#define    p_reg_err_byte_en    0xF9E4
+#define reg_err_byte_en_pos 0
+#define reg_err_byte_en_len 1
+#define reg_err_byte_en_lsb 0
+#define    p_reg_mp2_f_adc_7_0  0xF9E5
+#define reg_mp2_f_adc_7_0_pos 0
+#define reg_mp2_f_adc_7_0_len 8
+#define reg_mp2_f_adc_7_0_lsb 0
+#define    p_reg_mp2_f_adc_15_8 0xF9E6
+#define reg_mp2_f_adc_15_8_pos 0
+#define reg_mp2_f_adc_15_8_len 8
+#define reg_mp2_f_adc_15_8_lsb 8
+#define    p_reg_mp2_f_adc_23_16    0xF9E7
+#define reg_mp2_f_adc_23_16_pos 0
+#define reg_mp2_f_adc_23_16_len 8
+#define reg_mp2_f_adc_23_16_lsb 16
+#define    p_reg_set_util   0xF9E8
+#define reg_set_util_pos 0
+#define reg_set_util_len 8
+#define reg_set_util_lsb 0
+#define    r_reg_err_byte   0xF9E9
+#define reg_err_byte_pos 0
+#define reg_err_byte_len 8
+#define reg_err_byte_lsb 0
+#define    p_reg_p_ln_num1  0xF9EA
+#define reg_p_ln_num1_pos 0
+#define reg_p_ln_num1_len 5
+#define reg_p_ln_num1_lsb 0
+#define    p_reg_p_ln_num2_2_0  0xF9EA
+#define reg_p_ln_num2_2_0_pos 5
+#define reg_p_ln_num2_2_0_len 3
+#define reg_p_ln_num2_2_0_lsb 0
+#define    p_reg_p_ln_num2_4_3  0xF9EB
+#define reg_p_ln_num2_4_3_pos 0
+#define reg_p_ln_num2_4_3_len 2
+#define reg_p_ln_num2_4_3_lsb 3
+#define    p_reg_p_ln_num3_5_0  0xF9EB
+#define reg_p_ln_num3_5_0_pos 2
+#define reg_p_ln_num3_5_0_len 6
+#define reg_p_ln_num3_5_0_lsb 0
+#define    p_reg_p_ln_num3_8_6  0xF9EC
+#define reg_p_ln_num3_8_6_pos 0
+#define reg_p_ln_num3_8_6_len 3
+#define reg_p_ln_num3_8_6_lsb 6
+#define    p_reg_p_ln_num4_4_0  0xF9EC
+#define reg_p_ln_num4_4_0_pos 3
+#define reg_p_ln_num4_4_0_len 5
+#define reg_p_ln_num4_4_0_lsb 0
+#define    p_reg_p_ln_num4_8_5  0xF9ED
+#define reg_p_ln_num4_8_5_pos 0
+#define reg_p_ln_num4_8_5_len 4
+#define reg_p_ln_num4_8_5_lsb 5
+#define    p_reg_p_ln_num5_3_0  0xF9ED
+#define reg_p_ln_num5_3_0_pos 4
+#define reg_p_ln_num5_3_0_len 4
+#define reg_p_ln_num5_3_0_lsb 0
+#define    p_reg_p_ln_num5_8_4  0xF9EE
+#define reg_p_ln_num5_8_4_pos 0
+#define reg_p_ln_num5_8_4_len 5
+#define reg_p_ln_num5_8_4_lsb 4
+#define    p_reg_p_ln_num6_2_0  0xF9EE
+#define reg_p_ln_num6_2_0_pos 5
+#define reg_p_ln_num6_2_0_len 3
+#define reg_p_ln_num6_2_0_lsb 0
+#define    p_reg_p_ln_num6_8_3  0xF9EF
+#define reg_p_ln_num6_8_3_pos 0
+#define reg_p_ln_num6_8_3_len 6
+#define reg_p_ln_num6_8_3_lsb 3
+#define    p_reg_p_pixel_num_7_0    0xF9F0
+#define reg_p_pixel_num_7_0_pos 0
+#define reg_p_pixel_num_7_0_len 8
+#define reg_p_pixel_num_7_0_lsb 0
+#define    p_reg_p_pixel_num_10_8   0xF9F1
+#define reg_p_pixel_num_10_8_pos 0
+#define reg_p_pixel_num_10_8_len 3
+#define reg_p_pixel_num_10_8_lsb 8
+#define    p_reg_p_ccir_yuv_en  0xF9F1
+#define reg_p_ccir_yuv_en_pos 3
+#define reg_p_ccir_yuv_en_len 1
+#define reg_p_ccir_yuv_en_lsb 0
+#define    p_reg_p_ccir_size_sft    0xF9F1
+#define reg_p_ccir_size_sft_pos 4
+#define reg_p_ccir_size_sft_len 2
+#define reg_p_ccir_size_sft_lsb 0
+#define    p_reg_p_psb_cnt_sft  0xF9F1
+#define reg_p_psb_cnt_sft_pos 6
+#define reg_p_psb_cnt_sft_len 2
+#define reg_p_psb_cnt_sft_lsb 0
+#define    p_reg_p_tpsd_lock_trigger    0xF9F2
+#define reg_p_tpsd_lock_trigger_pos 0
+#define reg_p_tpsd_lock_trigger_len 1
+#define reg_p_tpsd_lock_trigger_lsb 0
+#define    p_reg_p_ccir_clk_sel 0xF9F3
+#define reg_p_ccir_clk_sel_pos 0
+#define reg_p_ccir_clk_sel_len 1
+#define reg_p_ccir_clk_sel_lsb 0
+#define    p_reg_i2c_16_8_data_sel  0xFB00
+#define reg_i2c_16_8_data_sel_pos 0
+#define reg_i2c_16_8_data_sel_len 1
+#define reg_i2c_16_8_data_sel_lsb 0
+#define    p_reg_i2c_slave_trigger_byte 0xFB01
+#define reg_i2c_slave_trigger_byte_pos 0
+#define reg_i2c_slave_trigger_byte_len 1
+#define reg_i2c_slave_trigger_byte_lsb 0
+#define    p_reg_wdti_level 0xFB05
+#define reg_wdti_level_pos 0
+#define reg_wdti_level_len 1
+#define reg_wdti_level_lsb 0
+#define    p_reg_rssi_avg_sel_lat   0xFB06
+#define reg_rssi_avg_sel_lat_pos 0
+#define reg_rssi_avg_sel_lat_len 2
+#define reg_rssi_avg_sel_lat_lsb 0
+#define    r_ofsm_rssi_avg_7_0  0xFB07
+#define ofsm_rssi_avg_7_0_pos 0
+#define ofsm_rssi_avg_7_0_len 8
+#define ofsm_rssi_avg_7_0_lsb 0
+#define    r_ofsm_rssi_avg_9_8  0xFB08
+#define ofsm_rssi_avg_9_8_pos 0
+#define ofsm_rssi_avg_9_8_len 2
+#define ofsm_rssi_avg_9_8_lsb 8
+#define    r_ofsm_mbist_fail_mon51  0xFB09
+#define ofsm_mbist_fail_mon51_pos 0
+#define ofsm_mbist_fail_mon51_len 1
+#define ofsm_mbist_fail_mon51_lsb 0
+#define    r_ofsm_mbist_fail_com    0xFB0A
+#define ofsm_mbist_fail_com_pos 0
+#define ofsm_mbist_fail_com_len 1
+#define ofsm_mbist_fail_com_lsb 0
+#define    r_ofsm_mbist_fail_fft    0xFB0B
+#define ofsm_mbist_fail_fft_pos 0
+#define ofsm_mbist_fail_fft_len 1
+#define ofsm_mbist_fail_fft_lsb 0
+#define    r_ofsm_mbist_fail_fd 0xFB0C
+#define ofsm_mbist_fail_fd_pos 0
+#define ofsm_mbist_fail_fd_len 1
+#define ofsm_mbist_fail_fd_lsb 0
+#define    r_ofsm_mbist_fail_link   0xFB0D
+#define ofsm_mbist_fail_link_pos 0
+#define ofsm_mbist_fail_link_len 1
+#define ofsm_mbist_fail_link_lsb 0
+#define    r_ofsm_mbist_fail_mpe    0xFB0E
+#define ofsm_mbist_fail_mpe_pos 0
+#define ofsm_mbist_fail_mpe_len 1
+#define ofsm_mbist_fail_mpe_lsb 0
+#define    r_ofsm_mbist_done_mpe    0xFB0F
+#define ofsm_mbist_done_mpe_pos 0
+#define ofsm_mbist_done_mpe_len 1
+#define ofsm_mbist_done_mpe_lsb 0
+#define    r_ofsm_mbist_mode_mpe    0xFB10
+#define ofsm_mbist_mode_mpe_pos 0
+#define ofsm_mbist_mode_mpe_len 1
+#define ofsm_mbist_mode_mpe_lsb 0
+#define    p_ofsm_cmd_reg   0xFB11
+#define ofsm_cmd_reg_pos 0
+#define ofsm_cmd_reg_len 8
+#define ofsm_cmd_reg_lsb 0
+#define    p_ofsm_addr_reg_h    0xFB12
+#define ofsm_addr_reg_h_pos 0
+#define ofsm_addr_reg_h_len 8
+#define ofsm_addr_reg_h_lsb 0
+#define    p_ofsm_addr_reg_l    0xFB13
+#define ofsm_addr_reg_l_pos 0
+#define ofsm_addr_reg_l_len 8
+#define ofsm_addr_reg_l_lsb 0
+#define    p_ofsm_data_reg_0    0xFB14
+#define ofsm_data_reg_0_pos 0
+#define ofsm_data_reg_0_len 8
+#define ofsm_data_reg_0_lsb 0
+#define    p_ofsm_data_reg_1    0xFB15
+#define ofsm_data_reg_1_pos 0
+#define ofsm_data_reg_1_len 8
+#define ofsm_data_reg_1_lsb 0
+#define    p_ofsm_data_reg_2    0xFB16
+#define ofsm_data_reg_2_pos 0
+#define ofsm_data_reg_2_len 8
+#define ofsm_data_reg_2_lsb 0
+#define    p_ofsm_data_reg_3    0xFB17
+#define ofsm_data_reg_3_pos 0
+#define ofsm_data_reg_3_len 8
+#define ofsm_data_reg_3_lsb 0
+#define    p_ofsm_data_reg_4    0xFB18
+#define ofsm_data_reg_4_pos 0
+#define ofsm_data_reg_4_len 8
+#define ofsm_data_reg_4_lsb 0
+#define    p_ofsm_data_reg_5    0xFB19
+#define ofsm_data_reg_5_pos 0
+#define ofsm_data_reg_5_len 8
+#define ofsm_data_reg_5_lsb 0
+#define    p_ofsm_data_reg_6    0xFB1A
+#define ofsm_data_reg_6_pos 0
+#define ofsm_data_reg_6_len 8
+#define ofsm_data_reg_6_lsb 0
+#define    p_ofsm_data_reg_7    0xFB1B
+#define ofsm_data_reg_7_pos 0
+#define ofsm_data_reg_7_len 8
+#define ofsm_data_reg_7_lsb 0
+#define    p_ofsm_data_reg_8    0xFB1C
+#define ofsm_data_reg_8_pos 0
+#define ofsm_data_reg_8_len 8
+#define ofsm_data_reg_8_lsb 0
+#define    p_ofsm_data_reg_9    0xFB1D
+#define ofsm_data_reg_9_pos 0
+#define ofsm_data_reg_9_len 8
+#define ofsm_data_reg_9_lsb 0
+#define    p_ofsm_data_reg_10   0xFB1E
+#define ofsm_data_reg_10_pos 0
+#define ofsm_data_reg_10_len 8
+#define ofsm_data_reg_10_lsb 0
+#define    p_ofsm_data_reg_11   0xFB1F
+#define ofsm_data_reg_11_pos 0
+#define ofsm_data_reg_11_len 8
+#define ofsm_data_reg_11_lsb 0
+#define    p_ofsm_data_reg_12   0xFB20
+#define ofsm_data_reg_12_pos 0
+#define ofsm_data_reg_12_len 8
+#define ofsm_data_reg_12_lsb 0
+#define    p_ofsm_data_reg_13   0xFB21
+#define ofsm_data_reg_13_pos 0
+#define ofsm_data_reg_13_len 8
+#define ofsm_data_reg_13_lsb 0
+#define    p_ofsm_data_reg_14   0xFB22
+#define ofsm_data_reg_14_pos 0
+#define ofsm_data_reg_14_len 8
+#define ofsm_data_reg_14_lsb 0
+#define    p_ofsm_data_reg_15   0xFB23
+#define ofsm_data_reg_15_pos 0
+#define ofsm_data_reg_15_len 8
+#define ofsm_data_reg_15_lsb 0
+#define    p_reg_afe_mem0   0xFB24
+#define reg_afe_mem0_pos 0
+#define reg_afe_mem0_len 8
+#define reg_afe_mem0_lsb 0
+#define    p_reg_afe_mem1   0xFB25
+#define reg_afe_mem1_pos 0
+#define reg_afe_mem1_len 8
+#define reg_afe_mem1_lsb 0
+#define    p_reg_afe_mem2   0xFB26
+#define reg_afe_mem2_pos 0
+#define reg_afe_mem2_len 8
+#define reg_afe_mem2_lsb 0
+#define    p_reg_afe_mem3   0xFB27
+#define reg_afe_mem3_pos 0
+#define reg_afe_mem3_len 8
+#define reg_afe_mem3_lsb 0
+#define    p_reg_afe_mem4   0xFB28
+#define reg_afe_mem4_pos 0
+#define reg_afe_mem4_len 8
+#define reg_afe_mem4_lsb 0
+#define    p_reg_afe_mem5   0xFB29
+#define reg_afe_mem5_pos 0
+#define reg_afe_mem5_len 8
+#define reg_afe_mem5_lsb 0
+#define    p_reg_afe_mem6   0xFB2A
+#define reg_afe_mem6_pos 0
+#define reg_afe_mem6_len 8
+#define reg_afe_mem6_lsb 0
+#define    p_reg_afe_mem7   0xFB2B
+#define reg_afe_mem7_pos 0
+#define reg_afe_mem7_len 8
+#define reg_afe_mem7_lsb 0
+#define    p_reg_i2cbootreq 0xFB2C
+#define reg_i2cbootreq_pos 0
+#define reg_i2cbootreq_len 1
+#define reg_i2cbootreq_lsb 0
+#define    p_reg_rst_i2cm   0xFB30
+#define reg_rst_i2cm_pos 0
+#define reg_rst_i2cm_len 1
+#define reg_rst_i2cm_lsb 0
+#define    p_reg_rst_i2cs   0xFB31
+#define reg_rst_i2cs_pos 0
+#define reg_rst_i2cs_len 1
+#define reg_rst_i2cs_lsb 0
+#define    r_reg_top_gpioscli   0xFB32
+#define reg_top_gpioscli_pos 0
+#define reg_top_gpioscli_len 1
+#define reg_top_gpioscli_lsb 0
+#define    p_reg_top_gpiosclo   0xFB33
+#define reg_top_gpiosclo_pos 0
+#define reg_top_gpiosclo_len 1
+#define reg_top_gpiosclo_lsb 0
+#define    p_reg_top_gpiosclen  0xFB34
+#define reg_top_gpiosclen_pos 0
+#define reg_top_gpiosclen_len 1
+#define reg_top_gpiosclen_lsb 0
+#define    p_reg_top_gpiosclon  0xFB35
+#define reg_top_gpiosclon_pos 0
+#define reg_top_gpiosclon_len 1
+#define reg_top_gpiosclon_lsb 0
+#define    r_reg_top_gpiosdai   0xFB36
+#define reg_top_gpiosdai_pos 0
+#define reg_top_gpiosdai_len 1
+#define reg_top_gpiosdai_lsb 0
+#define    p_reg_top_gpiosdao   0xFB37
+#define reg_top_gpiosdao_pos 0
+#define reg_top_gpiosdao_len 1
+#define reg_top_gpiosdao_lsb 0
+#define    p_reg_top_gpiosdaen  0xFB38
+#define reg_top_gpiosdaen_pos 0
+#define reg_top_gpiosdaen_len 1
+#define reg_top_gpiosdaen_lsb 0
+#define    p_reg_top_gpiosdaon  0xFB39
+#define reg_top_gpiosdaon_pos 0
+#define reg_top_gpiosdaon_len 1
+#define reg_top_gpiosdaon_lsb 0
+#define    p_reg_fix_rom_en 0xFB3A
+#define reg_fix_rom_en_pos 0
+#define reg_fix_rom_en_len 1
+#define reg_fix_rom_en_lsb 0
+#define    p_reg_ofsm_bug_addh_0    0xFB3B
+#define reg_ofsm_bug_addh_0_pos 0
+#define reg_ofsm_bug_addh_0_len 8
+#define reg_ofsm_bug_addh_0_lsb 0
+#define    p_reg_ofsm_bug_addl_0    0xFB3C
+#define reg_ofsm_bug_addl_0_pos 0
+#define reg_ofsm_bug_addl_0_len 8
+#define reg_ofsm_bug_addl_0_lsb 0
+#define    p_reg_ofsm_bug_addh_1    0xFB3D
+#define reg_ofsm_bug_addh_1_pos 0
+#define reg_ofsm_bug_addh_1_len 8
+#define reg_ofsm_bug_addh_1_lsb 0
+#define    p_reg_ofsm_bug_addl_1    0xFB3E
+#define reg_ofsm_bug_addl_1_pos 0
+#define reg_ofsm_bug_addl_1_len 8
+#define reg_ofsm_bug_addl_1_lsb 0
+#define    p_reg_ofsm_bug_addh_2    0xFB3F
+#define reg_ofsm_bug_addh_2_pos 0
+#define reg_ofsm_bug_addh_2_len 8
+#define reg_ofsm_bug_addh_2_lsb 0
+#define    p_reg_ofsm_bug_addl_2    0xFB40
+#define reg_ofsm_bug_addl_2_pos 0
+#define reg_ofsm_bug_addl_2_len 8
+#define reg_ofsm_bug_addl_2_lsb 0
+#define    p_reg_ofsm_bug_addh_3    0xFB41
+#define reg_ofsm_bug_addh_3_pos 0
+#define reg_ofsm_bug_addh_3_len 8
+#define reg_ofsm_bug_addh_3_lsb 0
+#define    p_reg_ofsm_bug_addl_3    0xFB42
+#define reg_ofsm_bug_addl_3_pos 0
+#define reg_ofsm_bug_addl_3_len 8
+#define reg_ofsm_bug_addl_3_lsb 0
+#define    p_reg_ofsm_bug_addh_4    0xFB43
+#define reg_ofsm_bug_addh_4_pos 0
+#define reg_ofsm_bug_addh_4_len 8
+#define reg_ofsm_bug_addh_4_lsb 0
+#define    p_reg_ofsm_bug_addl_4    0xFB44
+#define reg_ofsm_bug_addl_4_pos 0
+#define reg_ofsm_bug_addl_4_len 8
+#define reg_ofsm_bug_addl_4_lsb 0
+#define    p_reg_ofsm_bug_addh_5    0xFB45
+#define reg_ofsm_bug_addh_5_pos 0
+#define reg_ofsm_bug_addh_5_len 8
+#define reg_ofsm_bug_addh_5_lsb 0
+#define    p_reg_ofsm_bug_addl_5    0xFB46
+#define reg_ofsm_bug_addl_5_pos 0
+#define reg_ofsm_bug_addl_5_len 8
+#define reg_ofsm_bug_addl_5_lsb 0
+#define    p_reg_ofsm_bug_addh_6    0xFB47
+#define reg_ofsm_bug_addh_6_pos 0
+#define reg_ofsm_bug_addh_6_len 8
+#define reg_ofsm_bug_addh_6_lsb 0
+#define    p_reg_ofsm_bug_addl_6    0xFB48
+#define reg_ofsm_bug_addl_6_pos 0
+#define reg_ofsm_bug_addl_6_len 8
+#define reg_ofsm_bug_addl_6_lsb 0
+#define    p_reg_ofsm_bug_addh_7    0xFB49
+#define reg_ofsm_bug_addh_7_pos 0
+#define reg_ofsm_bug_addh_7_len 8
+#define reg_ofsm_bug_addh_7_lsb 0
+#define    p_reg_ofsm_bug_addl_7    0xFB4A
+#define reg_ofsm_bug_addl_7_pos 0
+#define reg_ofsm_bug_addl_7_len 8
+#define reg_ofsm_bug_addl_7_lsb 0
+#define    p_reg_ofsm_bug_addh_8    0xFB4B
+#define reg_ofsm_bug_addh_8_pos 0
+#define reg_ofsm_bug_addh_8_len 8
+#define reg_ofsm_bug_addh_8_lsb 0
+#define    p_reg_ofsm_bug_addl_8    0xFB4C
+#define reg_ofsm_bug_addl_8_pos 0
+#define reg_ofsm_bug_addl_8_len 8
+#define reg_ofsm_bug_addl_8_lsb 0
+#define    p_reg_ofsm_bug_addh_9    0xFB4D
+#define reg_ofsm_bug_addh_9_pos 0
+#define reg_ofsm_bug_addh_9_len 8
+#define reg_ofsm_bug_addh_9_lsb 0
+#define    p_reg_ofsm_bug_addl_9    0xFB4E
+#define reg_ofsm_bug_addl_9_pos 0
+#define reg_ofsm_bug_addl_9_len 8
+#define reg_ofsm_bug_addl_9_lsb 0
+#define    p_reg_ofsm_bug_addh_10   0xFB4F
+#define reg_ofsm_bug_addh_10_pos 0
+#define reg_ofsm_bug_addh_10_len 8
+#define reg_ofsm_bug_addh_10_lsb 0
+#define    p_reg_ofsm_bug_addl_10   0xFB50
+#define reg_ofsm_bug_addl_10_pos 0
+#define reg_ofsm_bug_addl_10_len 8
+#define reg_ofsm_bug_addl_10_lsb 0
+#define    p_reg_ofsm_bug_addh_11   0xFB51
+#define reg_ofsm_bug_addh_11_pos 0
+#define reg_ofsm_bug_addh_11_len 8
+#define reg_ofsm_bug_addh_11_lsb 0
+#define    p_reg_ofsm_bug_addl_11   0xFB52
+#define reg_ofsm_bug_addl_11_pos 0
+#define reg_ofsm_bug_addl_11_len 8
+#define reg_ofsm_bug_addl_11_lsb 0
+#define    p_reg_ofsm_bug_addh_12   0xFB53
+#define reg_ofsm_bug_addh_12_pos 0
+#define reg_ofsm_bug_addh_12_len 8
+#define reg_ofsm_bug_addh_12_lsb 0
+#define    p_reg_ofsm_bug_addl_12   0xFB54
+#define reg_ofsm_bug_addl_12_pos 0
+#define reg_ofsm_bug_addl_12_len 8
+#define reg_ofsm_bug_addl_12_lsb 0
+#define    p_reg_ofsm_bug_addh_13   0xFB55
+#define reg_ofsm_bug_addh_13_pos 0
+#define reg_ofsm_bug_addh_13_len 8
+#define reg_ofsm_bug_addh_13_lsb 0
+#define    p_reg_ofsm_bug_addl_13   0xFB56
+#define reg_ofsm_bug_addl_13_pos 0
+#define reg_ofsm_bug_addl_13_len 8
+#define reg_ofsm_bug_addl_13_lsb 0
+#define    p_reg_ofsm_bug_addh_14   0xFB57
+#define reg_ofsm_bug_addh_14_pos 0
+#define reg_ofsm_bug_addh_14_len 8
+#define reg_ofsm_bug_addh_14_lsb 0
+#define    p_reg_ofsm_bug_addl_14   0xFB58
+#define reg_ofsm_bug_addl_14_pos 0
+#define reg_ofsm_bug_addl_14_len 8
+#define reg_ofsm_bug_addl_14_lsb 0
+#define    p_reg_ofsm_bug_addh_15   0xFB59
+#define reg_ofsm_bug_addh_15_pos 0
+#define reg_ofsm_bug_addh_15_len 8
+#define reg_ofsm_bug_addh_15_lsb 0
+#define    p_reg_ofsm_bug_addl_15   0xFB5A
+#define reg_ofsm_bug_addl_15_pos 0
+#define reg_ofsm_bug_addl_15_len 8
+#define reg_ofsm_bug_addl_15_lsb 0
+#define    p_reg_ofsm_jmp_addh_0    0xFB5B
+#define reg_ofsm_jmp_addh_0_pos 0
+#define reg_ofsm_jmp_addh_0_len 8
+#define reg_ofsm_jmp_addh_0_lsb 0
+#define    p_reg_ofsm_jmp_addl_0    0xFB5C
+#define reg_ofsm_jmp_addl_0_pos 0
+#define reg_ofsm_jmp_addl_0_len 8
+#define reg_ofsm_jmp_addl_0_lsb 0
+#define    p_reg_ofsm_jmp_addh_1    0xFB5D
+#define reg_ofsm_jmp_addh_1_pos 0
+#define reg_ofsm_jmp_addh_1_len 8
+#define reg_ofsm_jmp_addh_1_lsb 0
+#define    p_reg_ofsm_jmp_addl_1    0xFB5E
+#define reg_ofsm_jmp_addl_1_pos 0
+#define reg_ofsm_jmp_addl_1_len 8
+#define reg_ofsm_jmp_addl_1_lsb 0
+#define    p_reg_ofsm_jmp_addh_2    0xFB5F
+#define reg_ofsm_jmp_addh_2_pos 0
+#define reg_ofsm_jmp_addh_2_len 8
+#define reg_ofsm_jmp_addh_2_lsb 0
+#define    p_reg_ofsm_jmp_addl_2    0xFB60
+#define reg_ofsm_jmp_addl_2_pos 0
+#define reg_ofsm_jmp_addl_2_len 8
+#define reg_ofsm_jmp_addl_2_lsb 0
+#define    p_reg_ofsm_jmp_addh_3    0xFB61
+#define reg_ofsm_jmp_addh_3_pos 0
+#define reg_ofsm_jmp_addh_3_len 8
+#define reg_ofsm_jmp_addh_3_lsb 0
+#define    p_reg_ofsm_jmp_addl_3    0xFB62
+#define reg_ofsm_jmp_addl_3_pos 0
+#define reg_ofsm_jmp_addl_3_len 8
+#define reg_ofsm_jmp_addl_3_lsb 0
+#define    p_reg_ofsm_jmp_addh_4    0xFB63
+#define reg_ofsm_jmp_addh_4_pos 0
+#define reg_ofsm_jmp_addh_4_len 8
+#define reg_ofsm_jmp_addh_4_lsb 0
+#define    p_reg_ofsm_jmp_addl_4    0xFB64
+#define reg_ofsm_jmp_addl_4_pos 0
+#define reg_ofsm_jmp_addl_4_len 8
+#define reg_ofsm_jmp_addl_4_lsb 0
+#define    p_reg_ofsm_jmp_addh_5    0xFB65
+#define reg_ofsm_jmp_addh_5_pos 0
+#define reg_ofsm_jmp_addh_5_len 8
+#define reg_ofsm_jmp_addh_5_lsb 0
+#define    p_reg_ofsm_jmp_addl_5    0xFB66
+#define reg_ofsm_jmp_addl_5_pos 0
+#define reg_ofsm_jmp_addl_5_len 8
+#define reg_ofsm_jmp_addl_5_lsb 0
+#define    p_reg_ofsm_jmp_addh_6    0xFB67
+#define reg_ofsm_jmp_addh_6_pos 0
+#define reg_ofsm_jmp_addh_6_len 8
+#define reg_ofsm_jmp_addh_6_lsb 0
+#define    p_reg_ofsm_jmp_addl_6    0xFB68
+#define reg_ofsm_jmp_addl_6_pos 0
+#define reg_ofsm_jmp_addl_6_len 8
+#define reg_ofsm_jmp_addl_6_lsb 0
+#define    p_reg_ofsm_jmp_addh_7    0xFB69
+#define reg_ofsm_jmp_addh_7_pos 0
+#define reg_ofsm_jmp_addh_7_len 8
+#define reg_ofsm_jmp_addh_7_lsb 0
+#define    p_reg_ofsm_jmp_addl_7    0xFB6A
+#define reg_ofsm_jmp_addl_7_pos 0
+#define reg_ofsm_jmp_addl_7_len 8
+#define reg_ofsm_jmp_addl_7_lsb 0
+#define    p_reg_ofsm_jmp_addh_8    0xFB6B
+#define reg_ofsm_jmp_addh_8_pos 0
+#define reg_ofsm_jmp_addh_8_len 8
+#define reg_ofsm_jmp_addh_8_lsb 0
+#define    p_reg_ofsm_jmp_addl_8    0xFB6C
+#define reg_ofsm_jmp_addl_8_pos 0
+#define reg_ofsm_jmp_addl_8_len 8
+#define reg_ofsm_jmp_addl_8_lsb 0
+#define    p_reg_ofsm_jmp_addh_9    0xFB6D
+#define reg_ofsm_jmp_addh_9_pos 0
+#define reg_ofsm_jmp_addh_9_len 8
+#define reg_ofsm_jmp_addh_9_lsb 0
+#define    p_reg_ofsm_jmp_addl_9    0xFB6E
+#define reg_ofsm_jmp_addl_9_pos 0
+#define reg_ofsm_jmp_addl_9_len 8
+#define reg_ofsm_jmp_addl_9_lsb 0
+#define    p_reg_ofsm_jmp_addh_10   0xFB6F
+#define reg_ofsm_jmp_addh_10_pos 0
+#define reg_ofsm_jmp_addh_10_len 8
+#define reg_ofsm_jmp_addh_10_lsb 0
+#define    p_reg_ofsm_jmp_addl_10   0xFB70
+#define reg_ofsm_jmp_addl_10_pos 0
+#define reg_ofsm_jmp_addl_10_len 8
+#define reg_ofsm_jmp_addl_10_lsb 0
+#define    p_reg_ofsm_jmp_addh_11   0xFB71
+#define reg_ofsm_jmp_addh_11_pos 0
+#define reg_ofsm_jmp_addh_11_len 8
+#define reg_ofsm_jmp_addh_11_lsb 0
+#define    p_reg_ofsm_jmp_addl_11   0xFB72
+#define reg_ofsm_jmp_addl_11_pos 0
+#define reg_ofsm_jmp_addl_11_len 8
+#define reg_ofsm_jmp_addl_11_lsb 0
+#define    p_reg_ofsm_jmp_addh_12   0xFB73
+#define reg_ofsm_jmp_addh_12_pos 0
+#define reg_ofsm_jmp_addh_12_len 8
+#define reg_ofsm_jmp_addh_12_lsb 0
+#define    p_reg_ofsm_jmp_addl_12   0xFB74
+#define reg_ofsm_jmp_addl_12_pos 0
+#define reg_ofsm_jmp_addl_12_len 8
+#define reg_ofsm_jmp_addl_12_lsb 0
+#define    p_reg_ofsm_jmp_addh_13   0xFB75
+#define reg_ofsm_jmp_addh_13_pos 0
+#define reg_ofsm_jmp_addh_13_len 8
+#define reg_ofsm_jmp_addh_13_lsb 0
+#define    p_reg_ofsm_jmp_addl_13   0xFB76
+#define reg_ofsm_jmp_addl_13_pos 0
+#define reg_ofsm_jmp_addl_13_len 8
+#define reg_ofsm_jmp_addl_13_lsb 0
+#define    p_reg_ofsm_jmp_addh_14   0xFB77
+#define reg_ofsm_jmp_addh_14_pos 0
+#define reg_ofsm_jmp_addh_14_len 8
+#define reg_ofsm_jmp_addh_14_lsb 0
+#define    p_reg_ofsm_jmp_addl_14   0xFB78
+#define reg_ofsm_jmp_addl_14_pos 0
+#define reg_ofsm_jmp_addl_14_len 8
+#define reg_ofsm_jmp_addl_14_lsb 0
+#define    p_reg_ofsm_jmp_addh_15   0xFB79
+#define reg_ofsm_jmp_addh_15_pos 0
+#define reg_ofsm_jmp_addh_15_len 8
+#define reg_ofsm_jmp_addh_15_lsb 0
+#define    p_reg_ofsm_jmp_addl_15   0xFB7A
+#define reg_ofsm_jmp_addl_15_pos 0
+#define reg_ofsm_jmp_addl_15_len 8
+#define reg_ofsm_jmp_addl_15_lsb 0
+#define    p_reg_sw_mon51   0xFB7B
+#define reg_sw_mon51_pos 0
+#define reg_sw_mon51_len 7
+#define reg_sw_mon51_lsb 0
+#define    p_reg_ofdm_mon51_flag    0xFB7C
+#define reg_ofdm_mon51_flag_pos 0
+#define reg_ofdm_mon51_flag_len 1
+#define reg_ofdm_mon51_flag_lsb 0
+#define    p_reg_ofdm_force_mon51   0xFB7D
+#define reg_ofdm_force_mon51_pos 0
+#define reg_ofdm_force_mon51_len 1
+#define reg_ofdm_force_mon51_lsb 0
+#define    p_reg_ofdm_which_cpu 0xFB7E
+#define reg_ofdm_which_cpu_pos 0
+#define reg_ofdm_which_cpu_len 1
+#define reg_ofdm_which_cpu_lsb 0
+#define    p_reg_ofdm_code_ready    0xFB7F
+#define reg_ofdm_code_ready_pos 0
+#define reg_ofdm_code_ready_len 1
+#define reg_ofdm_code_ready_lsb 0
+#define    p_reg_ofdm_mailbox_wend  0xFB80
+#define reg_ofdm_mailbox_wend_pos 0
+#define reg_ofdm_mailbox_wend_len 1
+#define reg_ofdm_mailbox_wend_lsb 0
+#define    r_reg_fast_slow_train    0xFB81
+#define reg_fast_slow_train_pos 0
+#define reg_fast_slow_train_len 1
+#define reg_fast_slow_train_lsb 0
+#define    p_reg_ofdm_mailbox_wptr  0xFB82
+#define reg_ofdm_mailbox_wptr_pos 0
+#define reg_ofdm_mailbox_wptr_len 8
+#define reg_ofdm_mailbox_wptr_lsb 0
+#define    p_reg_ofdm_mailbox_int   0xFB86
+#define reg_ofdm_mailbox_int_pos 0
+#define reg_ofdm_mailbox_int_len 1
+#define reg_ofdm_mailbox_int_lsb 0
+#define    p_reg_ofdm_lnk2ofdm_int  0xFB87
+#define reg_ofdm_lnk2ofdm_int_pos 0
+#define reg_ofdm_lnk2ofdm_int_len 1
+#define reg_ofdm_lnk2ofdm_int_lsb 0
+#define    p_reg_ofdm_ofdm2lnk_int  0xFB88
+#define reg_ofdm_ofdm2lnk_int_pos 0
+#define reg_ofdm_ofdm2lnk_int_len 1
+#define reg_ofdm_ofdm2lnk_int_lsb 0
+#define    r_reg_load_ofdm_reg  0xFB8F
+#define reg_load_ofdm_reg_pos 0
+#define reg_load_ofdm_reg_len 1
+#define reg_load_ofdm_reg_lsb 0
+#define    p_reg_lnk_mbx_rd_length_7_0  0xFB90
+#define reg_lnk_mbx_rd_length_7_0_pos 0
+#define reg_lnk_mbx_rd_length_7_0_len 8
+#define reg_lnk_mbx_rd_length_7_0_lsb 0
+#define    p_reg_lnk_mbx_rd_length_15_8 0xFB91
+#define reg_lnk_mbx_rd_length_15_8_pos 0
+#define reg_lnk_mbx_rd_length_15_8_len 8
+#define reg_lnk_mbx_rd_length_15_8_lsb 8
+#define    p_reg_lnk_mbx_rd_length_17_16    0xFB92
+#define reg_lnk_mbx_rd_length_17_16_pos 0
+#define reg_lnk_mbx_rd_length_17_16_len 2
+#define reg_lnk_mbx_rd_length_17_16_lsb 16
+#define    p_reg_lnk_rd_data_sel    0xFB93
+#define reg_lnk_rd_data_sel_pos 0
+#define reg_lnk_rd_data_sel_len 2
+#define reg_lnk_rd_data_sel_lsb 0
+#define    p_reg_ofdm2lnk_data_7_0  0xFB96
+#define reg_ofdm2lnk_data_7_0_pos 0
+#define reg_ofdm2lnk_data_7_0_len 8
+#define reg_ofdm2lnk_data_7_0_lsb 0
+#define    p_reg_ofdm2lnk_data_15_8 0xFB97
+#define reg_ofdm2lnk_data_15_8_pos 0
+#define reg_ofdm2lnk_data_15_8_len 8
+#define reg_ofdm2lnk_data_15_8_lsb 8
+#define    p_reg_ofdm2lnk_data_23_16    0xFB98
+#define reg_ofdm2lnk_data_23_16_pos 0
+#define reg_ofdm2lnk_data_23_16_len 8
+#define reg_ofdm2lnk_data_23_16_lsb 16
+#define    p_reg_ofdm2lnk_data_31_24    0xFB99
+#define reg_ofdm2lnk_data_31_24_pos 0
+#define reg_ofdm2lnk_data_31_24_len 8
+#define reg_ofdm2lnk_data_31_24_lsb 24
+#define    p_reg_ofdm2lnk_data_39_32    0xFB9A
+#define reg_ofdm2lnk_data_39_32_pos 0
+#define reg_ofdm2lnk_data_39_32_len 8
+#define reg_ofdm2lnk_data_39_32_lsb 32
+#define    p_reg_ofdm2lnk_data_47_40    0xFB9B
+#define reg_ofdm2lnk_data_47_40_pos 0
+#define reg_ofdm2lnk_data_47_40_len 8
+#define reg_ofdm2lnk_data_47_40_lsb 40
+#define    p_reg_ofdm2lnk_data_55_48    0xFB9C
+#define reg_ofdm2lnk_data_55_48_pos 0
+#define reg_ofdm2lnk_data_55_48_len 8
+#define reg_ofdm2lnk_data_55_48_lsb 48
+#define    p_reg_ofdm2lnk_data_63_56    0xFB9D
+#define reg_ofdm2lnk_data_63_56_pos 0
+#define reg_ofdm2lnk_data_63_56_len 8
+#define reg_ofdm2lnk_data_63_56_lsb 56
+#define    p_reg_lnktoofdm_data_7_0 0xFB9E
+#define reg_lnktoofdm_data_7_0_pos 0
+#define reg_lnktoofdm_data_7_0_len 8
+#define reg_lnktoofdm_data_7_0_lsb 0
+#define    p_reg_lnktoofdm_data_15_8    0xFB9F
+#define reg_lnktoofdm_data_15_8_pos 0
+#define reg_lnktoofdm_data_15_8_len 8
+#define reg_lnktoofdm_data_15_8_lsb 8
+#define    p_reg_lnktoofdm_data_23_16   0xFBA0
+#define reg_lnktoofdm_data_23_16_pos 0
+#define reg_lnktoofdm_data_23_16_len 8
+#define reg_lnktoofdm_data_23_16_lsb 16
+#define    p_reg_lnktoofdm_data_31_24   0xFBA1
+#define reg_lnktoofdm_data_31_24_pos 0
+#define reg_lnktoofdm_data_31_24_len 8
+#define reg_lnktoofdm_data_31_24_lsb 24
+#define    p_reg_lnktoofdm_data_39_32   0xFBA2
+#define reg_lnktoofdm_data_39_32_pos 0
+#define reg_lnktoofdm_data_39_32_len 8
+#define reg_lnktoofdm_data_39_32_lsb 32
+#define    p_reg_lnktoofdm_data_47_40   0xFBA3
+#define reg_lnktoofdm_data_47_40_pos 0
+#define reg_lnktoofdm_data_47_40_len 8
+#define reg_lnktoofdm_data_47_40_lsb 40
+#define    p_reg_lnktoofdm_data_55_48   0xFBA4
+#define reg_lnktoofdm_data_55_48_pos 0
+#define reg_lnktoofdm_data_55_48_len 8
+#define reg_lnktoofdm_data_55_48_lsb 48
+#define    p_reg_lnktoofdm_data_63_56   0xFBA5
+#define reg_lnktoofdm_data_63_56_pos 0
+#define reg_lnktoofdm_data_63_56_len 8
+#define reg_lnktoofdm_data_63_56_lsb 56
+#define    p_reg_dbgif32_sel    0xFBA6
+#define reg_dbgif32_sel_pos 0
+#define reg_dbgif32_sel_len 2
+#define reg_dbgif32_sel_lsb 0
+#define    p_reg_dyn1_clk   0xFBA7
+#define reg_dyn1_clk_pos 0
+#define reg_dyn1_clk_len 1
+#define reg_dyn1_clk_lsb 0
+#define    p_reg_dyn0_clk   0xFBA8
+#define reg_dyn0_clk_pos 0
+#define reg_dyn0_clk_len 1
+#define reg_dyn0_clk_lsb 0
+#define    p_reg_free_clk   0xFBA9
+#define reg_free_clk_pos 0
+#define reg_free_clk_len 1
+#define reg_free_clk_lsb 0
+#define    p_reg_ofdm_stick_mem_end_7_0 0xFBAD
+#define reg_ofdm_stick_mem_end_7_0_pos 0
+#define reg_ofdm_stick_mem_end_7_0_len 8
+#define reg_ofdm_stick_mem_end_7_0_lsb 0
+#define    p_reg_ofdm_stick_mem_end_15_8    0xFBAE
+#define reg_ofdm_stick_mem_end_15_8_pos 0
+#define reg_ofdm_stick_mem_end_15_8_len 8
+#define reg_ofdm_stick_mem_end_15_8_lsb 8
+#define    p_reg_ofdm_cpu_reset 0xFBAF
+#define reg_ofdm_cpu_reset_pos 0
+#define reg_ofdm_cpu_reset_len 1
+#define reg_ofdm_cpu_reset_lsb 0
+#define    p_reg_ofdm_bank_float_en 0xFBB0
+#define reg_ofdm_bank_float_en_pos 0
+#define reg_ofdm_bank_float_en_len 1
+#define reg_ofdm_bank_float_en_lsb 0
+#define    p_reg_ofdm_bank_float_start  0xFBB1
+#define reg_ofdm_bank_float_start_pos 0
+#define reg_ofdm_bank_float_start_len 8
+#define reg_ofdm_bank_float_start_lsb 0
+#define    p_reg_ofdm_bank_float_stop   0xFBB2
+#define reg_ofdm_bank_float_stop_pos 0
+#define reg_ofdm_bank_float_stop_len 8
+#define reg_ofdm_bank_float_stop_lsb 0
+#define    r_ofsm_bond0_i   0xFBB3
+#define ofsm_bond0_i_pos 0
+#define ofsm_bond0_i_len 1
+#define ofsm_bond0_i_lsb 0
+#define    r_ofsm_bond1_i   0xFBB4
+#define ofsm_bond1_i_pos 0
+#define ofsm_bond1_i_len 1
+#define ofsm_bond1_i_lsb 0
+#define    r_io_mux_pwron_clk_strap 0xD800
+#define io_mux_pwron_clk_strap_pos 0
+#define io_mux_pwron_clk_strap_len 4
+#define io_mux_pwron_clk_strap_lsb 0
+#define    r_io_mux_pwron_mode_strap    0xD801
+#define io_mux_pwron_mode_strap_pos 0
+#define io_mux_pwron_mode_strap_len 4
+#define io_mux_pwron_mode_strap_lsb 0
+#define    r_io_mux_pwron_hosta 0xD802
+#define io_mux_pwron_hosta_pos 0
+#define io_mux_pwron_hosta_len 1
+#define io_mux_pwron_hosta_lsb 0
+#define    r_reg_top_revid  0xD803
+#define reg_top_revid_pos 0
+#define reg_top_revid_len 4
+#define reg_top_revid_lsb 0
+#define    r_io_mux_bond0_i 0xD804
+#define io_mux_bond0_i_pos 0
+#define io_mux_bond0_i_len 1
+#define io_mux_bond0_i_lsb 0
+#define    r_io_mux_bondu0_i    0xD805
+#define io_mux_bondu0_i_pos 0
+#define io_mux_bondu0_i_len 1
+#define io_mux_bondu0_i_lsb 0
+#define    p_reg_ofsm_suspend   0xD806
+#define reg_ofsm_suspend_pos 0
+#define reg_ofsm_suspend_len 1
+#define reg_ofsm_suspend_lsb 0
+#define    p_reg_tslice_off 0xD807
+#define reg_tslice_off_pos 0
+#define reg_tslice_off_len 1
+#define reg_tslice_off_lsb 0
+#define    p_io_mux_wake_int    0xD808
+#define io_mux_wake_int_pos 0
+#define io_mux_wake_int_len 1
+#define io_mux_wake_int_lsb 0
+#define    p_reg_top_pwrdw_hwen 0xD809
+#define reg_top_pwrdw_hwen_pos 0
+#define reg_top_pwrdw_hwen_len 1
+#define reg_top_pwrdw_hwen_lsb 0
+#define    p_reg_top_pwrdw_inv  0xD80A
+#define reg_top_pwrdw_inv_pos 0
+#define reg_top_pwrdw_inv_len 1
+#define reg_top_pwrdw_inv_lsb 0
+#define    p_reg_top_pwrdw  0xD80B
+#define reg_top_pwrdw_pos 0
+#define reg_top_pwrdw_len 1
+#define reg_top_pwrdw_lsb 0
+#define    p_io_mux_wake_int_en 0xD80C
+#define io_mux_wake_int_en_pos 0
+#define io_mux_wake_int_en_len 1
+#define io_mux_wake_int_en_lsb 0
+#define    p_io_mux_pwrdw_int   0xD80D
+#define io_mux_pwrdw_int_pos 0
+#define io_mux_pwrdw_int_len 1
+#define io_mux_pwrdw_int_lsb 0
+#define    p_reg_top_adcdly 0xD80E
+#define reg_top_adcdly_pos 0
+#define reg_top_adcdly_len 2
+#define reg_top_adcdly_lsb 0
+#define    p_reg_top_debug  0xD80F
+#define reg_top_debug_pos 0
+#define reg_top_debug_len 1
+#define reg_top_debug_lsb 0
+#define    p_reg_top_pcout  0xD810
+#define reg_top_pcout_pos 0
+#define reg_top_pcout_len 1
+#define reg_top_pcout_lsb 0
+#define    p_reg_top_rs232  0xD811
+#define reg_top_rs232_pos 0
+#define reg_top_rs232_len 1
+#define reg_top_rs232_lsb 0
+#define    p_reg_iqmode 0xD812
+#define reg_iqmode_pos 0
+#define reg_iqmode_len 1
+#define reg_iqmode_lsb 0
+#define    p_reg_top_rstfd  0xD813
+#define reg_top_rstfd_pos 0
+#define reg_top_rstfd_len 1
+#define reg_top_rstfd_lsb 0
+#define    p_reg_sdio_clksel    0xD814
+#define reg_sdio_clksel_pos 0
+#define reg_sdio_clksel_len 1
+#define reg_sdio_clksel_lsb 0
+#define    p_reg_utmi_clksel    0xD815
+#define reg_utmi_clksel_pos 0
+#define reg_utmi_clksel_len 8
+#define reg_utmi_clksel_lsb 0
+#define    p_reg_top_suscnt 0xD816
+#define reg_top_suscnt_pos 0
+#define reg_top_suscnt_len 2
+#define reg_top_suscnt_lsb 0
+#define    p_reg_top_dist2f 0xD817
+#define reg_top_dist2f_pos 0
+#define reg_top_dist2f_len 1
+#define reg_top_dist2f_lsb 0
+#define    p_reg_top_extusb 0xD818
+#define reg_top_extusb_pos 0
+#define reg_top_extusb_len 1
+#define reg_top_extusb_lsb 0
+#define    p_reg_top_adcfifo    0xD819
+#define reg_top_adcfifo_pos 0
+#define reg_top_adcfifo_len 1
+#define reg_top_adcfifo_lsb 0
+#define    p_reg_top_clkoen 0xD81A
+#define reg_top_clkoen_pos 0
+#define reg_top_clkoen_len 1
+#define reg_top_clkoen_lsb 0
+#define    p_reg_top_stpck  0xD81B
+#define reg_top_stpck_pos 0
+#define reg_top_stpck_len 1
+#define reg_top_stpck_lsb 0
+#define    p_reg_top_freeck 0xD81C
+#define reg_top_freeck_pos 0
+#define reg_top_freeck_len 1
+#define reg_top_freeck_lsb 0
+#define    p_reg_top_dio_sel    0xD81D
+#define reg_top_dio_sel_pos 0
+#define reg_top_dio_sel_len 1
+#define reg_top_dio_sel_lsb 0
+#define    p_reg_top_int_en 0xD81E
+#define reg_top_int_en_pos 0
+#define reg_top_int_en_len 1
+#define reg_top_int_en_lsb 0
+#define    p_reg_top_int_inv    0xD81F
+#define reg_top_int_inv_pos 0
+#define reg_top_int_inv_len 1
+#define reg_top_int_inv_lsb 0
+#define    p_reg_tsip_clk_inv   0xD820
+#define reg_tsip_clk_inv_pos 0
+#define reg_tsip_clk_inv_len 1
+#define reg_tsip_clk_inv_lsb 0
+#define    p_reg_ts_clk_inv 0xD821
+#define reg_ts_clk_inv_pos 0
+#define reg_ts_clk_inv_len 1
+#define reg_ts_clk_inv_lsb 0
+#define    p_reg_ts_hybrid  0xD822
+#define reg_ts_hybrid_pos 0
+#define reg_ts_hybrid_len 1
+#define reg_ts_hybrid_lsb 0
+#define    p_reg_ccir_sel   0xD823
+#define reg_ccir_sel_pos 0
+#define reg_ccir_sel_len 4
+#define reg_ccir_sel_lsb 0
+#define    p_reg_top_sys_gate   0xD824
+#define reg_top_sys_gate_pos 0
+#define reg_top_sys_gate_len 1
+#define reg_top_sys_gate_lsb 0
+#define    p_reg_top_padpu  0xD825
+#define reg_top_padpu_pos 0
+#define reg_top_padpu_len 1
+#define reg_top_padpu_lsb 0
+#define    p_reg_top_padpd  0xD826
+#define reg_top_padpd_pos 0
+#define reg_top_padpd_len 1
+#define reg_top_padpd_lsb 0
+#define    p_reg_top_padodpu    0xD827
+#define reg_top_padodpu_pos 0
+#define reg_top_padodpu_len 1
+#define reg_top_padodpu_lsb 0
+#define    p_reg_top_thirdodpu  0xD828
+#define reg_top_thirdodpu_pos 0
+#define reg_top_thirdodpu_len 1
+#define reg_top_thirdodpu_lsb 0
+#define    p_reg_top_agc_od 0xD829
+#define reg_top_agc_od_pos 0
+#define reg_top_agc_od_len 1
+#define reg_top_agc_od_lsb 0
+#define    p_reg_top_padmpdr2   0xD82A
+#define reg_top_padmpdr2_pos 0
+#define reg_top_padmpdr2_len 1
+#define reg_top_padmpdr2_lsb 0
+#define    p_reg_top_padmpdr4   0xD82B
+#define reg_top_padmpdr4_pos 0
+#define reg_top_padmpdr4_len 1
+#define reg_top_padmpdr4_lsb 0
+#define    p_reg_top_padmpdr8   0xD82C
+#define reg_top_padmpdr8_pos 0
+#define reg_top_padmpdr8_len 1
+#define reg_top_padmpdr8_lsb 0
+#define    p_reg_top_padmpdrsr  0xD82D
+#define reg_top_padmpdrsr_pos 0
+#define reg_top_padmpdrsr_len 1
+#define reg_top_padmpdrsr_lsb 0
+#define    p_reg_top_padmppu    0xD82E
+#define reg_top_padmppu_pos 0
+#define reg_top_padmppu_len 1
+#define reg_top_padmppu_lsb 0
+#define    p_reg_top_padmppd    0xD82F
+#define reg_top_padmppd_pos 0
+#define reg_top_padmppd_len 1
+#define reg_top_padmppd_lsb 0
+#define    p_reg_top_padmiscdr2 0xD830
+#define reg_top_padmiscdr2_pos 0
+#define reg_top_padmiscdr2_len 1
+#define reg_top_padmiscdr2_lsb 0
+#define    p_reg_top_padmiscdr4 0xD831
+#define reg_top_padmiscdr4_pos 0
+#define reg_top_padmiscdr4_len 1
+#define reg_top_padmiscdr4_lsb 0
+#define    p_reg_top_padmiscdr8 0xD832
+#define reg_top_padmiscdr8_pos 0
+#define reg_top_padmiscdr8_len 1
+#define reg_top_padmiscdr8_lsb 0
+#define    p_reg_top_padmiscdrsr    0xD833
+#define reg_top_padmiscdrsr_pos 0
+#define reg_top_padmiscdrsr_len 1
+#define reg_top_padmiscdrsr_lsb 0
+#define    p_reg_top_padmiscpu  0xD834
+#define reg_top_padmiscpu_pos 0
+#define reg_top_padmiscpu_len 1
+#define reg_top_padmiscpu_lsb 0
+#define    p_reg_top_padmiscpd  0xD835
+#define reg_top_padmiscpd_pos 0
+#define reg_top_padmiscpd_len 1
+#define reg_top_padmiscpd_lsb 0
+#define    p_reg_host_b0_smt    0xD836
+#define reg_host_b0_smt_pos 0
+#define reg_host_b0_smt_len 1
+#define reg_host_b0_smt_lsb 0
+#define    p_reg_host_b1_smt    0xD837
+#define reg_host_b1_smt_pos 0
+#define reg_host_b1_smt_len 1
+#define reg_host_b1_smt_lsb 0
+#define    p_reg_host_b2_smt    0xD838
+#define reg_host_b2_smt_pos 0
+#define reg_host_b2_smt_len 1
+#define reg_host_b2_smt_lsb 0
+#define    p_reg_host_b3_smt    0xD839
+#define reg_host_b3_smt_pos 0
+#define reg_host_b3_smt_len 1
+#define reg_host_b3_smt_lsb 0
+#define    p_reg_host_b4_smt    0xD83A
+#define reg_host_b4_smt_pos 0
+#define reg_host_b4_smt_len 1
+#define reg_host_b4_smt_lsb 0
+#define    p_reg_host_b5_smt    0xD83B
+#define reg_host_b5_smt_pos 0
+#define reg_host_b5_smt_len 1
+#define reg_host_b5_smt_lsb 0
+#define    p_reg_host_b6_smt    0xD83C
+#define reg_host_b6_smt_pos 0
+#define reg_host_b6_smt_len 1
+#define reg_host_b6_smt_lsb 0
+#define    p_reg_host_b7_smt    0xD83D
+#define reg_host_b7_smt_pos 0
+#define reg_host_b7_smt_len 1
+#define reg_host_b7_smt_lsb 0
+#define    p_reg_host_b8_smt    0xD83E
+#define reg_host_b8_smt_pos 0
+#define reg_host_b8_smt_len 1
+#define reg_host_b8_smt_lsb 0
+#define    p_reg_host_b9_smt    0xD83F
+#define reg_host_b9_smt_pos 0
+#define reg_host_b9_smt_len 1
+#define reg_host_b9_smt_lsb 0
+#define    p_reg_host_b10_smt   0xD840
+#define reg_host_b10_smt_pos 0
+#define reg_host_b10_smt_len 1
+#define reg_host_b10_smt_lsb 0
+#define    p_reg_host_b11_smt   0xD841
+#define reg_host_b11_smt_pos 0
+#define reg_host_b11_smt_len 1
+#define reg_host_b11_smt_lsb 0
+#define    p_reg_host_a0_smt    0xD842
+#define reg_host_a0_smt_pos 0
+#define reg_host_a0_smt_len 1
+#define reg_host_a0_smt_lsb 0
+#define    p_reg_host_a1_smt    0xD843
+#define reg_host_a1_smt_pos 0
+#define reg_host_a1_smt_len 1
+#define reg_host_a1_smt_lsb 0
+#define    p_reg_host_a2_smt    0xD844
+#define reg_host_a2_smt_pos 0
+#define reg_host_a2_smt_len 1
+#define reg_host_a2_smt_lsb 0
+#define    p_reg_host_a3_smt    0xD845
+#define reg_host_a3_smt_pos 0
+#define reg_host_a3_smt_len 1
+#define reg_host_a3_smt_lsb 0
+#define    p_reg_host_a4_smt    0xD846
+#define reg_host_a4_smt_pos 0
+#define reg_host_a4_smt_len 1
+#define reg_host_a4_smt_lsb 0
+#define    p_reg_host_a5_smt    0xD847
+#define reg_host_a5_smt_pos 0
+#define reg_host_a5_smt_len 1
+#define reg_host_a5_smt_lsb 0
+#define    p_reg_host_a6_smt    0xD848
+#define reg_host_a6_smt_pos 0
+#define reg_host_a6_smt_len 1
+#define reg_host_a6_smt_lsb 0
+#define    p_reg_host_a7_smt    0xD849
+#define reg_host_a7_smt_pos 0
+#define reg_host_a7_smt_len 1
+#define reg_host_a7_smt_lsb 0
+#define    p_reg_host_a8_smt    0xD84A
+#define reg_host_a8_smt_pos 0
+#define reg_host_a8_smt_len 1
+#define reg_host_a8_smt_lsb 0
+#define    p_reg_host_a9_smt    0xD84B
+#define reg_host_a9_smt_pos 0
+#define reg_host_a9_smt_len 1
+#define reg_host_a9_smt_lsb 0
+#define    p_reg_host_a10_smt   0xD84C
+#define reg_host_a10_smt_pos 0
+#define reg_host_a10_smt_len 1
+#define reg_host_a10_smt_lsb 0
+#define    p_reg_host_a11_smt   0xD84D
+#define reg_host_a11_smt_pos 0
+#define reg_host_a11_smt_len 1
+#define reg_host_a11_smt_lsb 0
+#define    p_reg_testmode_pds   0xD84E
+#define reg_testmode_pds_pos 0
+#define reg_testmode_pds_len 3
+#define reg_testmode_pds_lsb 0
+#define    p_reg_debug31_pds    0xD84F
+#define reg_debug31_pds_pos 0
+#define reg_debug31_pds_len 3
+#define reg_debug31_pds_lsb 0
+#define    p_reg_debug30_pds    0xD850
+#define reg_debug30_pds_pos 0
+#define reg_debug30_pds_len 3
+#define reg_debug30_pds_lsb 0
+#define    p_reg_debug29_pds    0xD851
+#define reg_debug29_pds_pos 0
+#define reg_debug29_pds_len 3
+#define reg_debug29_pds_lsb 0
+#define    p_reg_debug28_pds    0xD852
+#define reg_debug28_pds_pos 0
+#define reg_debug28_pds_len 3
+#define reg_debug28_pds_lsb 0
+#define    p_reg_debug27_pds    0xD853
+#define reg_debug27_pds_pos 0
+#define reg_debug27_pds_len 3
+#define reg_debug27_pds_lsb 0
+#define    p_reg_debug26_pds    0xD854
+#define reg_debug26_pds_pos 0
+#define reg_debug26_pds_len 3
+#define reg_debug26_pds_lsb 0
+#define    p_reg_debug25_pds    0xD855
+#define reg_debug25_pds_pos 0
+#define reg_debug25_pds_len 3
+#define reg_debug25_pds_lsb 0
+#define    p_reg_debug24_pds    0xD856
+#define reg_debug24_pds_pos 0
+#define reg_debug24_pds_len 3
+#define reg_debug24_pds_lsb 0
+#define    p_reg_debug23_pds    0xD857
+#define reg_debug23_pds_pos 0
+#define reg_debug23_pds_len 3
+#define reg_debug23_pds_lsb 0
+#define    p_reg_debug22_pds    0xD858
+#define reg_debug22_pds_pos 0
+#define reg_debug22_pds_len 3
+#define reg_debug22_pds_lsb 0
+#define    p_reg_gpioh1_pds 0xD859
+#define reg_gpioh1_pds_pos 0
+#define reg_gpioh1_pds_len 3
+#define reg_gpioh1_pds_lsb 0
+#define    p_reg_gpioh2_pds 0xD85A
+#define reg_gpioh2_pds_pos 0
+#define reg_gpioh2_pds_len 3
+#define reg_gpioh2_pds_lsb 0
+#define    p_reg_gpioh3_pds 0xD85B
+#define reg_gpioh3_pds_pos 0
+#define reg_gpioh3_pds_len 3
+#define reg_gpioh3_pds_lsb 0
+#define    p_reg_gpioh4_pds 0xD85C
+#define reg_gpioh4_pds_pos 0
+#define reg_gpioh4_pds_len 3
+#define reg_gpioh4_pds_lsb 0
+#define    p_reg_iosda_pds  0xD85D
+#define reg_iosda_pds_pos 0
+#define reg_iosda_pds_len 3
+#define reg_iosda_pds_lsb 0
+#define    p_reg_ioscl_pds  0xD85E
+#define reg_ioscl_pds_pos 0
+#define reg_ioscl_pds_len 3
+#define reg_ioscl_pds_lsb 0
+#define    p_reg_gpioh5_pds 0xD85F
+#define reg_gpioh5_pds_pos 0
+#define reg_gpioh5_pds_len 3
+#define reg_gpioh5_pds_lsb 0
+#define    p_reg_bond0_pds  0xD860
+#define reg_bond0_pds_pos 0
+#define reg_bond0_pds_len 3
+#define reg_bond0_pds_lsb 0
+#define    p_reg_i2caddr6_pds   0xD861
+#define reg_i2caddr6_pds_pos 0
+#define reg_i2caddr6_pds_len 3
+#define reg_i2caddr6_pds_lsb 0
+#define    p_reg_i2caddr5_pds   0xD862
+#define reg_i2caddr5_pds_pos 0
+#define reg_i2caddr5_pds_len 3
+#define reg_i2caddr5_pds_lsb 0
+#define    p_reg_i2caddr4_pds   0xD863
+#define reg_i2caddr4_pds_pos 0
+#define reg_i2caddr4_pds_len 3
+#define reg_i2caddr4_pds_lsb 0
+#define    p_reg_host_a0_pds    0xD864
+#define reg_host_a0_pds_pos 0
+#define reg_host_a0_pds_len 3
+#define reg_host_a0_pds_lsb 0
+#define    p_reg_host_a1_pds    0xD865
+#define reg_host_a1_pds_pos 0
+#define reg_host_a1_pds_len 3
+#define reg_host_a1_pds_lsb 0
+#define    p_reg_debug21_pds    0xD866
+#define reg_debug21_pds_pos 0
+#define reg_debug21_pds_len 3
+#define reg_debug21_pds_lsb 0
+#define    p_reg_debug20_pds    0xD867
+#define reg_debug20_pds_pos 0
+#define reg_debug20_pds_len 3
+#define reg_debug20_pds_lsb 0
+#define    p_reg_debug19_pds    0xD868
+#define reg_debug19_pds_pos 0
+#define reg_debug19_pds_len 3
+#define reg_debug19_pds_lsb 0
+#define    p_reg_debug18_pds    0xD869
+#define reg_debug18_pds_pos 0
+#define reg_debug18_pds_len 3
+#define reg_debug18_pds_lsb 0
+#define    p_reg_debug17_pds    0xD86A
+#define reg_debug17_pds_pos 0
+#define reg_debug17_pds_len 3
+#define reg_debug17_pds_lsb 0
+#define    p_reg_host_a2_pds    0xD86B
+#define reg_host_a2_pds_pos 0
+#define reg_host_a2_pds_len 3
+#define reg_host_a2_pds_lsb 0
+#define    p_reg_host_a3_pds    0xD86C
+#define reg_host_a3_pds_pos 0
+#define reg_host_a3_pds_len 3
+#define reg_host_a3_pds_lsb 0
+#define    p_reg_host_a4_pds    0xD86D
+#define reg_host_a4_pds_pos 0
+#define reg_host_a4_pds_len 3
+#define reg_host_a4_pds_lsb 0
+#define    p_reg_host_a5_pds    0xD86E
+#define reg_host_a5_pds_pos 0
+#define reg_host_a5_pds_len 3
+#define reg_host_a5_pds_lsb 0
+#define    p_reg_host_a6_pds    0xD86F
+#define reg_host_a6_pds_pos 0
+#define reg_host_a6_pds_len 3
+#define reg_host_a6_pds_lsb 0
+#define    p_reg_p160sel_pds    0xD870
+#define reg_p160sel_pds_pos 0
+#define reg_p160sel_pds_len 3
+#define reg_p160sel_pds_lsb 0
+#define    p_reg_gpioh13_pds    0xD871
+#define reg_gpioh13_pds_pos 0
+#define reg_gpioh13_pds_len 3
+#define reg_gpioh13_pds_lsb 0
+#define    p_reg_gpioh12_pds    0xD872
+#define reg_gpioh12_pds_pos 0
+#define reg_gpioh12_pds_len 3
+#define reg_gpioh12_pds_lsb 0
+#define    p_reg_gpioh11_pds    0xD873
+#define reg_gpioh11_pds_pos 0
+#define reg_gpioh11_pds_len 3
+#define reg_gpioh11_pds_lsb 0
+#define    p_reg_host_a7_pds    0xD874
+#define reg_host_a7_pds_pos 0
+#define reg_host_a7_pds_len 3
+#define reg_host_a7_pds_lsb 0
+#define    p_reg_host_a8_pds    0xD875
+#define reg_host_a8_pds_pos 0
+#define reg_host_a8_pds_len 3
+#define reg_host_a8_pds_lsb 0
+#define    p_reg_host_a9_pds    0xD876
+#define reg_host_a9_pds_pos 0
+#define reg_host_a9_pds_len 3
+#define reg_host_a9_pds_lsb 0
+#define    p_reg_host_a10_pds   0xD877
+#define reg_host_a10_pds_pos 0
+#define reg_host_a10_pds_len 3
+#define reg_host_a10_pds_lsb 0
+#define    p_reg_host_a11_pds   0xD878
+#define reg_host_a11_pds_pos 0
+#define reg_host_a11_pds_len 3
+#define reg_host_a11_pds_lsb 0
+#define    p_reg_bondu0_pds 0xD879
+#define reg_bondu0_pds_pos 0
+#define reg_bondu0_pds_len 3
+#define reg_bondu0_pds_lsb 0
+#define    p_reg_host_b0_pds    0xD87A
+#define reg_host_b0_pds_pos 0
+#define reg_host_b0_pds_len 3
+#define reg_host_b0_pds_lsb 0
+#define    p_reg_host_b1_pds    0xD87B
+#define reg_host_b1_pds_pos 0
+#define reg_host_b1_pds_len 3
+#define reg_host_b1_pds_lsb 0
+#define    p_reg_host_b2_pds    0xD87C
+#define reg_host_b2_pds_pos 0
+#define reg_host_b2_pds_len 3
+#define reg_host_b2_pds_lsb 0
+#define    p_reg_host_b3_pds    0xD87D
+#define reg_host_b3_pds_pos 0
+#define reg_host_b3_pds_len 3
+#define reg_host_b3_pds_lsb 0
+#define    p_reg_host_b4_pds    0xD87E
+#define reg_host_b4_pds_pos 0
+#define reg_host_b4_pds_len 3
+#define reg_host_b4_pds_lsb 0
+#define    p_reg_host_b5_pds    0xD87F
+#define reg_host_b5_pds_pos 0
+#define reg_host_b5_pds_len 3
+#define reg_host_b5_pds_lsb 0
+#define    p_reg_host_b6_pds    0xD880
+#define reg_host_b6_pds_pos 0
+#define reg_host_b6_pds_len 3
+#define reg_host_b6_pds_lsb 0
+#define    p_reg_host_b7_pds    0xD881
+#define reg_host_b7_pds_pos 0
+#define reg_host_b7_pds_len 3
+#define reg_host_b7_pds_lsb 0
+#define    p_reg_afe_f12_pds    0xD882
+#define reg_afe_f12_pds_pos 0
+#define reg_afe_f12_pds_len 3
+#define reg_afe_f12_pds_lsb 0
+#define    p_reg_host_b8_pds    0xD883
+#define reg_host_b8_pds_pos 0
+#define reg_host_b8_pds_len 3
+#define reg_host_b8_pds_lsb 0
+#define    p_reg_host_b9_pds    0xD884
+#define reg_host_b9_pds_pos 0
+#define reg_host_b9_pds_len 3
+#define reg_host_b9_pds_lsb 0
+#define    p_reg_host_b10_pds   0xD885
+#define reg_host_b10_pds_pos 0
+#define reg_host_b10_pds_len 3
+#define reg_host_b10_pds_lsb 0
+#define    p_reg_host_b11_pds   0xD886
+#define reg_host_b11_pds_pos 0
+#define reg_host_b11_pds_len 3
+#define reg_host_b11_pds_lsb 0
+#define    p_reg_debug16_pds    0xD887
+#define reg_debug16_pds_pos 0
+#define reg_debug16_pds_len 3
+#define reg_debug16_pds_lsb 0
+#define    p_reg_debug15_pds    0xD888
+#define reg_debug15_pds_pos 0
+#define reg_debug15_pds_len 3
+#define reg_debug15_pds_lsb 0
+#define    p_reg_debug14_pds    0xD889
+#define reg_debug14_pds_pos 0
+#define reg_debug14_pds_len 3
+#define reg_debug14_pds_lsb 0
+#define    p_reg_debug13_pds    0xD88A
+#define reg_debug13_pds_pos 0
+#define reg_debug13_pds_len 3
+#define reg_debug13_pds_lsb 0
+#define    p_reg_debug12_pds    0xD88B
+#define reg_debug12_pds_pos 0
+#define reg_debug12_pds_len 3
+#define reg_debug12_pds_lsb 0
+#define    p_reg_debug11_pds    0xD88C
+#define reg_debug11_pds_pos 0
+#define reg_debug11_pds_len 3
+#define reg_debug11_pds_lsb 0
+#define    p_reg_debug10_pds    0xD88D
+#define reg_debug10_pds_pos 0
+#define reg_debug10_pds_len 3
+#define reg_debug10_pds_lsb 0
+#define    p_reg_debug9_pds 0xD88E
+#define reg_debug9_pds_pos 0
+#define reg_debug9_pds_len 3
+#define reg_debug9_pds_lsb 0
+#define    p_reg_debug8_pds 0xD88F
+#define reg_debug8_pds_pos 0
+#define reg_debug8_pds_len 3
+#define reg_debug8_pds_lsb 0
+#define    p_reg_debug7_pds 0xD890
+#define reg_debug7_pds_pos 0
+#define reg_debug7_pds_len 3
+#define reg_debug7_pds_lsb 0
+#define    p_reg_debug6_pds 0xD891
+#define reg_debug6_pds_pos 0
+#define reg_debug6_pds_len 3
+#define reg_debug6_pds_lsb 0
+#define    p_reg_debug5_pds 0xD892
+#define reg_debug5_pds_pos 0
+#define reg_debug5_pds_len 3
+#define reg_debug5_pds_lsb 0
+#define    p_reg_debug4_pds 0xD893
+#define reg_debug4_pds_pos 0
+#define reg_debug4_pds_len 3
+#define reg_debug4_pds_lsb 0
+#define    p_reg_clko_pds   0xD894
+#define reg_clko_pds_pos 0
+#define reg_clko_pds_len 3
+#define reg_clko_pds_lsb 0
+#define    p_reg_gpioh6_pds 0xD895
+#define reg_gpioh6_pds_pos 0
+#define reg_gpioh6_pds_len 3
+#define reg_gpioh6_pds_lsb 0
+#define    p_reg_gpioh7_pds 0xD896
+#define reg_gpioh7_pds_pos 0
+#define reg_gpioh7_pds_len 3
+#define reg_gpioh7_pds_lsb 0
+#define    p_reg_gpioh8_pds 0xD897
+#define reg_gpioh8_pds_pos 0
+#define reg_gpioh8_pds_len 3
+#define reg_gpioh8_pds_lsb 0
+#define    p_reg_gpioh9_pds 0xD898
+#define reg_gpioh9_pds_pos 0
+#define reg_gpioh9_pds_len 3
+#define reg_gpioh9_pds_lsb 0
+#define    p_reg_gpioh10_pds    0xD899
+#define reg_gpioh10_pds_pos 0
+#define reg_gpioh10_pds_len 3
+#define reg_gpioh10_pds_lsb 0
+#define    p_reg_debug3_pds 0xD89A
+#define reg_debug3_pds_pos 0
+#define reg_debug3_pds_len 3
+#define reg_debug3_pds_lsb 0
+#define    p_reg_debug2_pds 0xD89B
+#define reg_debug2_pds_pos 0
+#define reg_debug2_pds_len 3
+#define reg_debug2_pds_lsb 0
+#define    p_reg_debug1_pds 0xD89C
+#define reg_debug1_pds_pos 0
+#define reg_debug1_pds_len 3
+#define reg_debug1_pds_lsb 0
+#define    p_reg_debug0_pds 0xD89D
+#define reg_debug0_pds_pos 0
+#define reg_debug0_pds_len 3
+#define reg_debug0_pds_lsb 0
+#define    p_reg_gpiot1_pds 0xD89E
+#define reg_gpiot1_pds_pos 0
+#define reg_gpiot1_pds_len 3
+#define reg_gpiot1_pds_lsb 0
+#define    p_reg_gpiot2_pds 0xD89F
+#define reg_gpiot2_pds_pos 0
+#define reg_gpiot2_pds_len 3
+#define reg_gpiot2_pds_lsb 0
+#define    p_reg_rfagc_pds  0xD8A0
+#define reg_rfagc_pds_pos 0
+#define reg_rfagc_pds_len 3
+#define reg_rfagc_pds_lsb 0
+#define    p_reg_ifagc_pds  0xD8A1
+#define reg_ifagc_pds_pos 0
+#define reg_ifagc_pds_len 3
+#define reg_ifagc_pds_lsb 0
+#define    p_reg_gpiot3_pds 0xD8A2
+#define reg_gpiot3_pds_pos 0
+#define reg_gpiot3_pds_len 3
+#define reg_gpiot3_pds_lsb 0
+#define    p_reg_i2caddr3_pds   0xD8A3
+#define reg_i2caddr3_pds_pos 0
+#define reg_i2caddr3_pds_len 3
+#define reg_i2caddr3_pds_lsb 0
+#define    p_reg_i2caddr2_pds   0xD8A4
+#define reg_i2caddr2_pds_pos 0
+#define reg_i2caddr2_pds_len 3
+#define reg_i2caddr2_pds_lsb 0
+#define    p_reg_i2caddr1_pds   0xD8A5
+#define reg_i2caddr1_pds_pos 0
+#define reg_i2caddr1_pds_len 3
+#define reg_i2caddr1_pds_lsb 0
+#define    p_reg_afe_sel33_pds  0xD8A6
+#define reg_afe_sel33_pds_pos 0
+#define reg_afe_sel33_pds_len 3
+#define reg_afe_sel33_pds_lsb 0
+#define    p_reg_iotunscl_pds   0xD8A7
+#define reg_iotunscl_pds_pos 0
+#define reg_iotunscl_pds_len 3
+#define reg_iotunscl_pds_lsb 0
+#define    p_reg_iotunsda_pds   0xD8A8
+#define reg_iotunsda_pds_pos 0
+#define reg_iotunsda_pds_len 3
+#define reg_iotunsda_pds_lsb 0
+#define    p_reg_rxdofsm_pds    0xD8A9
+#define reg_rxdofsm_pds_pos 0
+#define reg_rxdofsm_pds_len 3
+#define reg_rxdofsm_pds_lsb 0
+#define    p_reg_txdofsm_pds    0xD8AA
+#define reg_txdofsm_pds_pos 0
+#define reg_txdofsm_pds_len 3
+#define reg_txdofsm_pds_lsb 0
+#define    p_reg_rxdlink_pds    0xD8AB
+#define reg_rxdlink_pds_pos 0
+#define reg_rxdlink_pds_len 3
+#define reg_rxdlink_pds_lsb 0
+#define    p_reg_txdlink_pds    0xD8AC
+#define reg_txdlink_pds_pos 0
+#define reg_txdlink_pds_len 3
+#define reg_txdlink_pds_lsb 0
+#define    p_reg_ck_test_pds    0xD8AD
+#define reg_ck_test_pds_pos 0
+#define reg_ck_test_pds_len 3
+#define reg_ck_test_pds_lsb 0
+#define    r_reg_top_gpioh1_i   0xD8AE
+#define reg_top_gpioh1_i_pos 0
+#define reg_top_gpioh1_i_len 1
+#define reg_top_gpioh1_i_lsb 0
+#define    p_reg_top_gpioh1_o   0xD8AF
+#define reg_top_gpioh1_o_pos 0
+#define reg_top_gpioh1_o_len 1
+#define reg_top_gpioh1_o_lsb 0
+#define    p_reg_top_gpioh1_en  0xD8B0
+#define reg_top_gpioh1_en_pos 0
+#define reg_top_gpioh1_en_len 1
+#define reg_top_gpioh1_en_lsb 0
+#define    p_reg_top_gpioh1_on  0xD8B1
+#define reg_top_gpioh1_on_pos 0
+#define reg_top_gpioh1_on_len 1
+#define reg_top_gpioh1_on_lsb 0
+#define    r_reg_top_gpioh3_i   0xD8B2
+#define reg_top_gpioh3_i_pos 0
+#define reg_top_gpioh3_i_len 1
+#define reg_top_gpioh3_i_lsb 0
+#define    p_reg_top_gpioh3_o   0xD8B3
+#define reg_top_gpioh3_o_pos 0
+#define reg_top_gpioh3_o_len 1
+#define reg_top_gpioh3_o_lsb 0
+#define    p_reg_top_gpioh3_en  0xD8B4
+#define reg_top_gpioh3_en_pos 0
+#define reg_top_gpioh3_en_len 1
+#define reg_top_gpioh3_en_lsb 0
+#define    p_reg_top_gpioh3_on  0xD8B5
+#define reg_top_gpioh3_on_pos 0
+#define reg_top_gpioh3_on_len 1
+#define reg_top_gpioh3_on_lsb 0
+#define    r_reg_top_gpioh2_i   0xD8B6
+#define reg_top_gpioh2_i_pos 0
+#define reg_top_gpioh2_i_len 1
+#define reg_top_gpioh2_i_lsb 0
+#define    p_reg_top_gpioh2_o   0xD8B7
+#define reg_top_gpioh2_o_pos 0
+#define reg_top_gpioh2_o_len 1
+#define reg_top_gpioh2_o_lsb 0
+#define    p_reg_top_gpioh2_en  0xD8B8
+#define reg_top_gpioh2_en_pos 0
+#define reg_top_gpioh2_en_len 1
+#define reg_top_gpioh2_en_lsb 0
+#define    p_reg_top_gpioh2_on  0xD8B9
+#define reg_top_gpioh2_on_pos 0
+#define reg_top_gpioh2_on_len 1
+#define reg_top_gpioh2_on_lsb 0
+#define    r_reg_top_gpioh5_i   0xD8BA
+#define reg_top_gpioh5_i_pos 0
+#define reg_top_gpioh5_i_len 1
+#define reg_top_gpioh5_i_lsb 0
+#define    p_reg_top_gpioh5_o   0xD8BB
+#define reg_top_gpioh5_o_pos 0
+#define reg_top_gpioh5_o_len 1
+#define reg_top_gpioh5_o_lsb 0
+#define    p_reg_top_gpioh5_en  0xD8BC
+#define reg_top_gpioh5_en_pos 0
+#define reg_top_gpioh5_en_len 1
+#define reg_top_gpioh5_en_lsb 0
+#define    p_reg_top_gpioh5_on  0xD8BD
+#define reg_top_gpioh5_on_pos 0
+#define reg_top_gpioh5_on_len 1
+#define reg_top_gpioh5_on_lsb 0
+#define    r_reg_top_gpioh4_i   0xD8BE
+#define reg_top_gpioh4_i_pos 0
+#define reg_top_gpioh4_i_len 1
+#define reg_top_gpioh4_i_lsb 0
+#define    p_reg_top_gpioh4_o   0xD8BF
+#define reg_top_gpioh4_o_pos 0
+#define reg_top_gpioh4_o_len 1
+#define reg_top_gpioh4_o_lsb 0
+#define    p_reg_top_gpioh4_en  0xD8C0
+#define reg_top_gpioh4_en_pos 0
+#define reg_top_gpioh4_en_len 1
+#define reg_top_gpioh4_en_lsb 0
+#define    p_reg_top_gpioh4_on  0xD8C1
+#define reg_top_gpioh4_on_pos 0
+#define reg_top_gpioh4_on_len 1
+#define reg_top_gpioh4_on_lsb 0
+#define    r_reg_top_gpioh7_i   0xD8C2
+#define reg_top_gpioh7_i_pos 0
+#define reg_top_gpioh7_i_len 1
+#define reg_top_gpioh7_i_lsb 0
+#define    p_reg_top_gpioh7_o   0xD8C3
+#define reg_top_gpioh7_o_pos 0
+#define reg_top_gpioh7_o_len 1
+#define reg_top_gpioh7_o_lsb 0
+#define    p_reg_top_gpioh7_en  0xD8C4
+#define reg_top_gpioh7_en_pos 0
+#define reg_top_gpioh7_en_len 1
+#define reg_top_gpioh7_en_lsb 0
+#define    p_reg_top_gpioh7_on  0xD8C5
+#define reg_top_gpioh7_on_pos 0
+#define reg_top_gpioh7_on_len 1
+#define reg_top_gpioh7_on_lsb 0
+#define    r_reg_top_gpioh6_i   0xD8C6
+#define reg_top_gpioh6_i_pos 0
+#define reg_top_gpioh6_i_len 1
+#define reg_top_gpioh6_i_lsb 0
+#define    p_reg_top_gpioh6_o   0xD8C7
+#define reg_top_gpioh6_o_pos 0
+#define reg_top_gpioh6_o_len 1
+#define reg_top_gpioh6_o_lsb 0
+#define    p_reg_top_gpioh6_en  0xD8C8
+#define reg_top_gpioh6_en_pos 0
+#define reg_top_gpioh6_en_len 1
+#define reg_top_gpioh6_en_lsb 0
+#define    p_reg_top_gpioh6_on  0xD8C9
+#define reg_top_gpioh6_on_pos 0
+#define reg_top_gpioh6_on_len 1
+#define reg_top_gpioh6_on_lsb 0
+#define    r_reg_top_gpioh9_i   0xD8CA
+#define reg_top_gpioh9_i_pos 0
+#define reg_top_gpioh9_i_len 1
+#define reg_top_gpioh9_i_lsb 0
+#define    p_reg_top_gpioh9_o   0xD8CB
+#define reg_top_gpioh9_o_pos 0
+#define reg_top_gpioh9_o_len 1
+#define reg_top_gpioh9_o_lsb 0
+#define    p_reg_top_gpioh9_en  0xD8CC
+#define reg_top_gpioh9_en_pos 0
+#define reg_top_gpioh9_en_len 1
+#define reg_top_gpioh9_en_lsb 0
+#define    p_reg_top_gpioh9_on  0xD8CD
+#define reg_top_gpioh9_on_pos 0
+#define reg_top_gpioh9_on_len 1
+#define reg_top_gpioh9_on_lsb 0
+#define    r_reg_top_gpioh8_i   0xD8CE
+#define reg_top_gpioh8_i_pos 0
+#define reg_top_gpioh8_i_len 1
+#define reg_top_gpioh8_i_lsb 0
+#define    p_reg_top_gpioh8_o   0xD8CF
+#define reg_top_gpioh8_o_pos 0
+#define reg_top_gpioh8_o_len 1
+#define reg_top_gpioh8_o_lsb 0
+#define    p_reg_top_gpioh8_en  0xD8D0
+#define reg_top_gpioh8_en_pos 0
+#define reg_top_gpioh8_en_len 1
+#define reg_top_gpioh8_en_lsb 0
+#define    p_reg_top_gpioh8_on  0xD8D1
+#define reg_top_gpioh8_on_pos 0
+#define reg_top_gpioh8_on_len 1
+#define reg_top_gpioh8_on_lsb 0
+#define    r_reg_top_gpioh11_i  0xD8D2
+#define reg_top_gpioh11_i_pos 0
+#define reg_top_gpioh11_i_len 1
+#define reg_top_gpioh11_i_lsb 0
+#define    p_reg_top_gpioh11_o  0xD8D3
+#define reg_top_gpioh11_o_pos 0
+#define reg_top_gpioh11_o_len 1
+#define reg_top_gpioh11_o_lsb 0
+#define    p_reg_top_gpioh11_en 0xD8D4
+#define reg_top_gpioh11_en_pos 0
+#define reg_top_gpioh11_en_len 1
+#define reg_top_gpioh11_en_lsb 0
+#define    p_reg_top_gpioh11_on 0xD8D5
+#define reg_top_gpioh11_on_pos 0
+#define reg_top_gpioh11_on_len 1
+#define reg_top_gpioh11_on_lsb 0
+#define    r_reg_top_gpioh10_i  0xD8D6
+#define reg_top_gpioh10_i_pos 0
+#define reg_top_gpioh10_i_len 1
+#define reg_top_gpioh10_i_lsb 0
+#define    p_reg_top_gpioh10_o  0xD8D7
+#define reg_top_gpioh10_o_pos 0
+#define reg_top_gpioh10_o_len 1
+#define reg_top_gpioh10_o_lsb 0
+#define    p_reg_top_gpioh10_en 0xD8D8
+#define reg_top_gpioh10_en_pos 0
+#define reg_top_gpioh10_en_len 1
+#define reg_top_gpioh10_en_lsb 0
+#define    p_reg_top_gpioh10_on 0xD8D9
+#define reg_top_gpioh10_on_pos 0
+#define reg_top_gpioh10_on_len 1
+#define reg_top_gpioh10_on_lsb 0
+#define    r_reg_top_gpioh13_i  0xD8DA
+#define reg_top_gpioh13_i_pos 0
+#define reg_top_gpioh13_i_len 1
+#define reg_top_gpioh13_i_lsb 0
+#define    p_reg_top_gpioh13_o  0xD8DB
+#define reg_top_gpioh13_o_pos 0
+#define reg_top_gpioh13_o_len 1
+#define reg_top_gpioh13_o_lsb 0
+#define    p_reg_top_gpioh13_en 0xD8DC
+#define reg_top_gpioh13_en_pos 0
+#define reg_top_gpioh13_en_len 1
+#define reg_top_gpioh13_en_lsb 0
+#define    p_reg_top_gpioh13_on 0xD8DD
+#define reg_top_gpioh13_on_pos 0
+#define reg_top_gpioh13_on_len 1
+#define reg_top_gpioh13_on_lsb 0
+#define    r_reg_top_gpioh12_i  0xD8DE
+#define reg_top_gpioh12_i_pos 0
+#define reg_top_gpioh12_i_len 1
+#define reg_top_gpioh12_i_lsb 0
+#define    p_reg_top_gpioh12_o  0xD8DF
+#define reg_top_gpioh12_o_pos 0
+#define reg_top_gpioh12_o_len 1
+#define reg_top_gpioh12_o_lsb 0
+#define    p_reg_top_gpioh12_en 0xD8E0
+#define reg_top_gpioh12_en_pos 0
+#define reg_top_gpioh12_en_len 1
+#define reg_top_gpioh12_en_lsb 0
+#define    p_reg_top_gpioh12_on 0xD8E1
+#define reg_top_gpioh12_on_pos 0
+#define reg_top_gpioh12_on_len 1
+#define reg_top_gpioh12_on_lsb 0
+#define    r_reg_top_gpiot1_i   0xD8E2
+#define reg_top_gpiot1_i_pos 0
+#define reg_top_gpiot1_i_len 1
+#define reg_top_gpiot1_i_lsb 0
+#define    p_reg_top_gpiot1_o   0xD8E3
+#define reg_top_gpiot1_o_pos 0
+#define reg_top_gpiot1_o_len 1
+#define reg_top_gpiot1_o_lsb 0
+#define    p_reg_top_gpiot1_en  0xD8E4
+#define reg_top_gpiot1_en_pos 0
+#define reg_top_gpiot1_en_len 1
+#define reg_top_gpiot1_en_lsb 0
+#define    p_reg_top_gpiot1_on  0xD8E5
+#define reg_top_gpiot1_on_pos 0
+#define reg_top_gpiot1_on_len 1
+#define reg_top_gpiot1_on_lsb 0
+#define    r_reg_top_gpiot3_i   0xD8E6
+#define reg_top_gpiot3_i_pos 0
+#define reg_top_gpiot3_i_len 1
+#define reg_top_gpiot3_i_lsb 0
+#define    p_reg_top_gpiot3_o   0xD8E7
+#define reg_top_gpiot3_o_pos 0
+#define reg_top_gpiot3_o_len 1
+#define reg_top_gpiot3_o_lsb 0
+#define    p_reg_top_gpiot3_en  0xD8E8
+#define reg_top_gpiot3_en_pos 0
+#define reg_top_gpiot3_en_len 1
+#define reg_top_gpiot3_en_lsb 0
+#define    p_reg_top_gpiot3_on  0xD8E9
+#define reg_top_gpiot3_on_pos 0
+#define reg_top_gpiot3_on_len 1
+#define reg_top_gpiot3_on_lsb 0
+#define    r_reg_top_gpiot2_i   0xD8EA
+#define reg_top_gpiot2_i_pos 0
+#define reg_top_gpiot2_i_len 1
+#define reg_top_gpiot2_i_lsb 0
+#define    p_reg_top_gpiot2_o   0xD8EB
+#define reg_top_gpiot2_o_pos 0
+#define reg_top_gpiot2_o_len 1
+#define reg_top_gpiot2_o_lsb 0
+#define    p_reg_top_gpiot2_en  0xD8EC
+#define reg_top_gpiot2_en_pos 0
+#define reg_top_gpiot2_en_len 1
+#define reg_top_gpiot2_en_lsb 0
+#define    p_reg_top_gpiot2_on  0xD8ED
+#define reg_top_gpiot2_on_pos 0
+#define reg_top_gpiot2_on_len 1
+#define reg_top_gpiot2_on_lsb 0
+#define    p_reg_top_lock2_out  0xD8EE
+#define reg_top_lock2_out_pos 0
+#define reg_top_lock2_out_len 1
+#define reg_top_lock2_out_lsb 0
+#define    p_reg_top_lock2_tpsd 0xD8EF
+#define reg_top_lock2_tpsd_pos 0
+#define reg_top_lock2_tpsd_len 1
+#define reg_top_lock2_tpsd_lsb 0
+#define    p_reg_top_lock2_o    0xD8F0
+#define reg_top_lock2_o_pos 0
+#define reg_top_lock2_o_len 1
+#define reg_top_lock2_o_lsb 0
+#define    p_reg_top_lock2_en   0xD8F1
+#define reg_top_lock2_en_pos 0
+#define reg_top_lock2_en_len 1
+#define reg_top_lock2_en_lsb 0
+#define    p_reg_top_lock2_on   0xD8F2
+#define reg_top_lock2_on_pos 0
+#define reg_top_lock2_on_len 1
+#define reg_top_lock2_on_lsb 0
+#define    p_reg_top_lock1_out  0xD8F3
+#define reg_top_lock1_out_pos 0
+#define reg_top_lock1_out_len 1
+#define reg_top_lock1_out_lsb 0
+#define    p_reg_top_lock1_tpsd 0xD8F4
+#define reg_top_lock1_tpsd_pos 0
+#define reg_top_lock1_tpsd_len 1
+#define reg_top_lock1_tpsd_lsb 0
+#define    p_reg_top_lock1_o    0xD8F5
+#define reg_top_lock1_o_pos 0
+#define reg_top_lock1_o_len 1
+#define reg_top_lock1_o_lsb 0
+#define    p_reg_top_lock1_en   0xD8F6
+#define reg_top_lock1_en_pos 0
+#define reg_top_lock1_en_len 1
+#define reg_top_lock1_en_lsb 0
+#define    p_reg_top_lock1_on   0xD8F7
+#define reg_top_lock1_on_pos 0
+#define reg_top_lock1_on_len 1
+#define reg_top_lock1_on_lsb 0
+#define    p_reg_top_lock4_out  0xD8F8
+#define reg_top_lock4_out_pos 0
+#define reg_top_lock4_out_len 1
+#define reg_top_lock4_out_lsb 0
+#define    p_reg_top_lock4_tpsd 0xD8F9
+#define reg_top_lock4_tpsd_pos 0
+#define reg_top_lock4_tpsd_len 1
+#define reg_top_lock4_tpsd_lsb 0
+#define    p_reg_top_lock4_o    0xD8FA
+#define reg_top_lock4_o_pos 0
+#define reg_top_lock4_o_len 1
+#define reg_top_lock4_o_lsb 0
+#define    p_reg_top_lock4_en   0xD8FB
+#define reg_top_lock4_en_pos 0
+#define reg_top_lock4_en_len 1
+#define reg_top_lock4_en_lsb 0
+#define    p_reg_top_lock4_on   0xD8FC
+#define reg_top_lock4_on_pos 0
+#define reg_top_lock4_on_len 1
+#define reg_top_lock4_on_lsb 0
+#define    p_reg_top_lock3_out  0xD8FD
+#define reg_top_lock3_out_pos 0
+#define reg_top_lock3_out_len 1
+#define reg_top_lock3_out_lsb 0
+#define    p_reg_top_lock3_tpsd 0xD8FE
+#define reg_top_lock3_tpsd_pos 0
+#define reg_top_lock3_tpsd_len 1
+#define reg_top_lock3_tpsd_lsb 0
+#define    p_reg_top_lock3_o    0xD8FF
+#define reg_top_lock3_o_pos 0
+#define reg_top_lock3_o_len 1
+#define reg_top_lock3_o_lsb 0
+#define    p_reg_top_lock3_en   0xD900
+#define reg_top_lock3_en_pos 0
+#define reg_top_lock3_en_len 1
+#define reg_top_lock3_en_lsb 0
+#define    p_reg_top_lock3_on   0xD901
+#define reg_top_lock3_on_pos 0
+#define reg_top_lock3_on_len 1
+#define reg_top_lock3_on_lsb 0
+#define    p_reg_top_pwm0_en    0xD902
+#define reg_top_pwm0_en_pos 0
+#define reg_top_pwm0_en_len 1
+#define reg_top_pwm0_en_lsb 0
+#define    p_reg_top_pwm1_en    0xD903
+#define reg_top_pwm1_en_pos 0
+#define reg_top_pwm1_en_len 1
+#define reg_top_pwm1_en_lsb 0
+#define    p_reg_top_pwm2_en    0xD904
+#define reg_top_pwm2_en_pos 0
+#define reg_top_pwm2_en_len 1
+#define reg_top_pwm2_en_lsb 0
+#define    p_reg_top_pwm3_en    0xD905
+#define reg_top_pwm3_en_pos 0
+#define reg_top_pwm3_en_len 1
+#define reg_top_pwm3_en_lsb 0
+#define    p_reg_top_pwm0_gpio  0xD906
+#define reg_top_pwm0_gpio_pos 0
+#define reg_top_pwm0_gpio_len 1
+#define reg_top_pwm0_gpio_lsb 0
+#define    p_reg_top_pwm0_pos   0xD907
+#define reg_top_pwm0_pos_pos 0
+#define reg_top_pwm0_pos_len 3
+#define reg_top_pwm0_pos_lsb 0
+#define    p_reg_top_pwm0_width 0xD908
+#define reg_top_pwm0_width_pos 0
+#define reg_top_pwm0_width_len 2
+#define reg_top_pwm0_width_lsb 0
+#define    p_reg_top_pwm0_duration  0xD909
+#define reg_top_pwm0_duration_pos 0
+#define reg_top_pwm0_duration_len 8
+#define reg_top_pwm0_duration_lsb 0
+#define    p_reg_top_pwm1_gpio  0xD90A
+#define reg_top_pwm1_gpio_pos 0
+#define reg_top_pwm1_gpio_len 1
+#define reg_top_pwm1_gpio_lsb 0
+#define    p_reg_top_pwm1_pos   0xD90B
+#define reg_top_pwm1_pos_pos 0
+#define reg_top_pwm1_pos_len 3
+#define reg_top_pwm1_pos_lsb 0
+#define    p_reg_top_pwm1_width 0xD90C
+#define reg_top_pwm1_width_pos 0
+#define reg_top_pwm1_width_len 2
+#define reg_top_pwm1_width_lsb 0
+#define    p_reg_top_pwm1_duration  0xD90D
+#define reg_top_pwm1_duration_pos 0
+#define reg_top_pwm1_duration_len 8
+#define reg_top_pwm1_duration_lsb 0
+#define    p_reg_top_pwm2_gpio  0xD90E
+#define reg_top_pwm2_gpio_pos 0
+#define reg_top_pwm2_gpio_len 1
+#define reg_top_pwm2_gpio_lsb 0
+#define    p_reg_top_pwm2_pos   0xD90F
+#define reg_top_pwm2_pos_pos 0
+#define reg_top_pwm2_pos_len 3
+#define reg_top_pwm2_pos_lsb 0
+#define    p_reg_top_pwm2_width 0xD910
+#define reg_top_pwm2_width_pos 0
+#define reg_top_pwm2_width_len 2
+#define reg_top_pwm2_width_lsb 0
+#define    p_reg_top_pwm2_duration  0xD911
+#define reg_top_pwm2_duration_pos 0
+#define reg_top_pwm2_duration_len 8
+#define reg_top_pwm2_duration_lsb 0
+#define    p_reg_top_pwm3_gpio  0xD912
+#define reg_top_pwm3_gpio_pos 0
+#define reg_top_pwm3_gpio_len 1
+#define reg_top_pwm3_gpio_lsb 0
+#define    p_reg_top_pwm3_pos   0xD913
+#define reg_top_pwm3_pos_pos 0
+#define reg_top_pwm3_pos_len 3
+#define reg_top_pwm3_pos_lsb 0
+#define    p_reg_top_pwm3_width 0xD914
+#define reg_top_pwm3_width_pos 0
+#define reg_top_pwm3_width_len 2
+#define reg_top_pwm3_width_lsb 0
+#define    p_reg_top_pwm3_duration  0xD915
+#define reg_top_pwm3_duration_pos 0
+#define reg_top_pwm3_duration_len 8
+#define reg_top_pwm3_duration_lsb 0
+#define    p_reg_top_hosta_mpeg_par_mode    0xD916
+#define reg_top_hosta_mpeg_par_mode_pos 0
+#define reg_top_hosta_mpeg_par_mode_len 1
+#define reg_top_hosta_mpeg_par_mode_lsb 0
+#define    p_reg_top_hosta_mpeg_ser_mode    0xD917
+#define reg_top_hosta_mpeg_ser_mode_pos 0
+#define reg_top_hosta_mpeg_ser_mode_len 1
+#define reg_top_hosta_mpeg_ser_mode_lsb 0
+#define    p_reg_top_hosta_mpeg_ser_do7 0xD918
+#define reg_top_hosta_mpeg_ser_do7_pos 0
+#define reg_top_hosta_mpeg_ser_do7_len 1
+#define reg_top_hosta_mpeg_ser_do7_lsb 0
+#define    p_reg_top_hosta_dca_upper    0xD919
+#define reg_top_hosta_dca_upper_pos 0
+#define reg_top_hosta_dca_upper_len 1
+#define reg_top_hosta_dca_upper_lsb 0
+#define    p_reg_top_hosta_dca_lower    0xD91A
+#define reg_top_hosta_dca_lower_pos 0
+#define reg_top_hosta_dca_lower_len 1
+#define reg_top_hosta_dca_lower_lsb 0
+#define    p_reg_top_hostb_mpeg_par_mode    0xD91B
+#define reg_top_hostb_mpeg_par_mode_pos 0
+#define reg_top_hostb_mpeg_par_mode_len 1
+#define reg_top_hostb_mpeg_par_mode_lsb 0
+#define    p_reg_top_hostb_mpeg_ser_mode    0xD91C
+#define reg_top_hostb_mpeg_ser_mode_pos 0
+#define reg_top_hostb_mpeg_ser_mode_len 1
+#define reg_top_hostb_mpeg_ser_mode_lsb 0
+#define    p_reg_top_hostb_mpeg_ser_do7 0xD91D
+#define reg_top_hostb_mpeg_ser_do7_pos 0
+#define reg_top_hostb_mpeg_ser_do7_len 1
+#define reg_top_hostb_mpeg_ser_do7_lsb 0
+#define    p_reg_top_hostb_dca_upper    0xD91E
+#define reg_top_hostb_dca_upper_pos 0
+#define reg_top_hostb_dca_upper_len 1
+#define reg_top_hostb_dca_upper_lsb 0
+#define    p_reg_top_hostb_dca_lower    0xD91F
+#define reg_top_hostb_dca_lower_pos 0
+#define reg_top_hostb_dca_lower_len 1
+#define reg_top_hostb_dca_lower_lsb 0
+#define    p_reg_top_host_reverse   0xD920
+#define reg_top_host_reverse_pos 0
+#define reg_top_host_reverse_len 1
+#define reg_top_host_reverse_lsb 0
+#define    p_reg_top_hosta_ccir 0xD921
+#define reg_top_hosta_ccir_pos 0
+#define reg_top_hosta_ccir_len 1
+#define reg_top_hosta_ccir_lsb 0
+#define    p_reg_top_hostb_ccir 0xD922
+#define reg_top_hostb_ccir_pos 0
+#define reg_top_hostb_ccir_len 1
+#define reg_top_hostb_ccir_lsb 0
+#define    p_reg_top_i2s_master_mode    0xD923
+#define reg_top_i2s_master_mode_pos 0
+#define reg_top_i2s_master_mode_len 1
+#define reg_top_i2s_master_mode_lsb 0
+#define    p_reg_usb_cfg_speed  0xDD00
+#define reg_usb_cfg_speed_pos 0
+#define reg_usb_cfg_speed_len 1
+#define reg_usb_cfg_speed_lsb 0
+#define    p_reg_usb_cfg_utmi16 0xDD00
+#define reg_usb_cfg_utmi16_pos 1
+#define reg_usb_cfg_utmi16_len 1
+#define reg_usb_cfg_utmi16_lsb 0
+#define    p_reg_usb_cfg_test   0xDD00
+#define reg_usb_cfg_test_pos 3
+#define reg_usb_cfg_test_len 3
+#define reg_usb_cfg_test_lsb 0
+#define    p_reg_usb_port_sim_reset 0xDD00
+#define reg_usb_port_sim_reset_pos 6
+#define reg_usb_port_sim_reset_len 1
+#define reg_usb_port_sim_reset_lsb 0
+#define    p_reg_usb_port_run   0xDD00
+#define reg_usb_port_run_pos 7
+#define reg_usb_port_run_len 1
+#define reg_usb_port_run_lsb 0
+#define    r_usb_line_state_0   0xDD01
+#define usb_line_state_0_pos 0
+#define usb_line_state_0_len 1
+#define usb_line_state_0_lsb 0
+#define    r_usb_line_state_1   0xDD01
+#define usb_line_state_1_pos 1
+#define usb_line_state_1_len 1
+#define usb_line_state_1_lsb 0
+#define    r_reg_usb_status_speed   0xDD01
+#define reg_usb_status_speed_pos 2
+#define reg_usb_status_speed_len 1
+#define reg_usb_status_speed_lsb 0
+#define    r_reg_usb_status_connect 0xDD01
+#define reg_usb_status_connect_pos 3
+#define reg_usb_status_connect_len 1
+#define reg_usb_status_connect_lsb 0
+#define    r_reg_usb_rx_buf 0xDD01
+#define reg_usb_rx_buf_pos 4
+#define reg_usb_rx_buf_len 1
+#define reg_usb_rx_buf_lsb 0
+#define    r_reg_usb_port_reset 0xDD01
+#define reg_usb_port_reset_pos 5
+#define reg_usb_port_reset_len 1
+#define reg_usb_port_reset_lsb 0
+#define    r_reg_usb_port_suspend   0xDD01
+#define reg_usb_port_suspend_pos 6
+#define reg_usb_port_suspend_len 1
+#define reg_usb_port_suspend_lsb 0
+#define    p_reg_ep1_tx_type    0xDD07
+#define reg_ep1_tx_type_pos 2
+#define reg_ep1_tx_type_len 1
+#define reg_ep1_tx_type_lsb 0
+#define    p_reg_ep2_rx_type    0xDD07
+#define reg_ep2_rx_type_pos 3
+#define reg_ep2_rx_type_len 1
+#define reg_ep2_rx_type_lsb 0
+#define    p_reg_ep3_tx_type    0xDD07
+#define reg_ep3_tx_type_pos 4
+#define reg_ep3_tx_type_len 1
+#define reg_ep3_tx_type_lsb 0
+#define    p_reg_ep4_tx_type    0xDD07
+#define reg_ep4_tx_type_pos 5
+#define reg_ep4_tx_type_len 1
+#define reg_ep4_tx_type_lsb 0
+#define    p_reg_ep5_tx_type    0xDD07
+#define reg_ep5_tx_type_pos 6
+#define reg_ep5_tx_type_len 1
+#define reg_ep5_tx_type_lsb 0
+#define    p_reg_ep6_tx_type    0xDD07
+#define reg_ep6_tx_type_pos 7
+#define reg_ep6_tx_type_len 1
+#define reg_ep6_tx_type_lsb 0
+#define    p_reg_ep0_max_pkt    0xDD08
+#define reg_ep0_max_pkt_pos 0
+#define reg_ep0_max_pkt_len 8
+#define reg_ep0_max_pkt_lsb 0
+#define    p_reg_ep2_max_pkt    0xDD0A
+#define reg_ep2_max_pkt_pos 0
+#define reg_ep2_max_pkt_len 8
+#define reg_ep2_max_pkt_lsb 0
+#define    p_reg_ep4_max_pkt    0xDD0C
+#define reg_ep4_max_pkt_pos 0
+#define reg_ep4_max_pkt_len 8
+#define reg_ep4_max_pkt_lsb 0
+#define    p_reg_ep5_max_pkt    0xDD0D
+#define reg_ep5_max_pkt_pos 0
+#define reg_ep5_max_pkt_len 8
+#define reg_ep5_max_pkt_lsb 0
+#define    p_reg_ep6_max_pkt_7_0    0xDD0E
+#define reg_ep6_max_pkt_7_0_pos 0
+#define reg_ep6_max_pkt_7_0_len 8
+#define reg_ep6_max_pkt_7_0_lsb 0
+#define    p_reg_ep6_max_pkt_15_8   0xDD0F
+#define reg_ep6_max_pkt_15_8_pos 0
+#define reg_ep6_max_pkt_15_8_len 8
+#define reg_ep6_max_pkt_15_8_lsb 8
+#define    p_reg_usb_addr   0xDD10
+#define reg_usb_addr_pos 0
+#define reg_usb_addr_len 7
+#define reg_usb_addr_lsb 0
+#define    p_reg_usb_addr_now   0xDD10
+#define reg_usb_addr_now_pos 7
+#define reg_usb_addr_now_len 1
+#define reg_usb_addr_now_lsb 0
+#define    p_reg_ep0_tx_en  0xDD11
+#define reg_ep0_tx_en_pos 0
+#define reg_ep0_tx_en_len 1
+#define reg_ep0_tx_en_lsb 0
+#define    p_reg_ep0_rx_en  0xDD11
+#define reg_ep0_rx_en_pos 1
+#define reg_ep0_rx_en_len 1
+#define reg_ep0_rx_en_lsb 0
+#define    p_reg_ep1_tx_en  0xDD11
+#define reg_ep1_tx_en_pos 2
+#define reg_ep1_tx_en_len 1
+#define reg_ep1_tx_en_lsb 0
+#define    p_reg_ep2_rx_en  0xDD11
+#define reg_ep2_rx_en_pos 3
+#define reg_ep2_rx_en_len 1
+#define reg_ep2_rx_en_lsb 0
+#define    p_reg_ep3_tx_en  0xDD11
+#define reg_ep3_tx_en_pos 4
+#define reg_ep3_tx_en_len 1
+#define reg_ep3_tx_en_lsb 0
+#define    p_reg_ep4_tx_en  0xDD11
+#define reg_ep4_tx_en_pos 5
+#define reg_ep4_tx_en_len 1
+#define reg_ep4_tx_en_lsb 0
+#define    p_reg_ep5_tx_en  0xDD11
+#define reg_ep5_tx_en_pos 6
+#define reg_ep5_tx_en_len 1
+#define reg_ep5_tx_en_lsb 0
+#define    p_reg_ep6_tx_en  0xDD11
+#define reg_ep6_tx_en_pos 7
+#define reg_ep6_tx_en_len 1
+#define reg_ep6_tx_en_lsb 0
+#define    p_reg_ep0_tx_stall   0xDD12
+#define reg_ep0_tx_stall_pos 0
+#define reg_ep0_tx_stall_len 1
+#define reg_ep0_tx_stall_lsb 0
+#define    p_reg_ep0_rx_stall   0xDD12
+#define reg_ep0_rx_stall_pos 1
+#define reg_ep0_rx_stall_len 1
+#define reg_ep0_rx_stall_lsb 0
+#define    p_reg_ep1_tx_stall   0xDD12
+#define reg_ep1_tx_stall_pos 2
+#define reg_ep1_tx_stall_len 1
+#define reg_ep1_tx_stall_lsb 0
+#define    p_reg_ep2_rx_stall   0xDD12
+#define reg_ep2_rx_stall_pos 3
+#define reg_ep2_rx_stall_len 1
+#define reg_ep2_rx_stall_lsb 0
+#define    p_reg_ep3_tx_stall   0xDD12
+#define reg_ep3_tx_stall_pos 4
+#define reg_ep3_tx_stall_len 1
+#define reg_ep3_tx_stall_lsb 0
+#define    p_reg_ep4_tx_stall   0xDD12
+#define reg_ep4_tx_stall_pos 5
+#define reg_ep4_tx_stall_len 1
+#define reg_ep4_tx_stall_lsb 0
+#define    p_reg_ep5_tx_stall   0xDD12
+#define reg_ep5_tx_stall_pos 6
+#define reg_ep5_tx_stall_len 1
+#define reg_ep5_tx_stall_lsb 0
+#define    p_reg_ep6_tx_stall   0xDD12
+#define reg_ep6_tx_stall_pos 7
+#define reg_ep6_tx_stall_len 1
+#define reg_ep6_tx_stall_lsb 0
+#define    p_reg_ep0_tx_nak 0xDD13
+#define reg_ep0_tx_nak_pos 0
+#define reg_ep0_tx_nak_len 1
+#define reg_ep0_tx_nak_lsb 0
+#define    p_reg_ep0_rx_nak 0xDD13
+#define reg_ep0_rx_nak_pos 1
+#define reg_ep0_rx_nak_len 1
+#define reg_ep0_rx_nak_lsb 0
+#define    p_reg_ep1_tx_nak 0xDD13
+#define reg_ep1_tx_nak_pos 2
+#define reg_ep1_tx_nak_len 1
+#define reg_ep1_tx_nak_lsb 0
+#define    p_reg_ep2_rx_nak 0xDD13
+#define reg_ep2_rx_nak_pos 3
+#define reg_ep2_rx_nak_len 1
+#define reg_ep2_rx_nak_lsb 0
+#define    p_reg_ep3_tx_nak 0xDD13
+#define reg_ep3_tx_nak_pos 4
+#define reg_ep3_tx_nak_len 1
+#define reg_ep3_tx_nak_lsb 0
+#define    p_reg_ep4_tx_nak 0xDD13
+#define reg_ep4_tx_nak_pos 5
+#define reg_ep4_tx_nak_len 1
+#define reg_ep4_tx_nak_lsb 0
+#define    p_reg_ep5_tx_nak 0xDD13
+#define reg_ep5_tx_nak_pos 6
+#define reg_ep5_tx_nak_len 1
+#define reg_ep5_tx_nak_lsb 0
+#define    p_reg_ep6_tx_nak 0xDD13
+#define reg_ep6_tx_nak_pos 7
+#define reg_ep6_tx_nak_len 1
+#define reg_ep6_tx_nak_lsb 0
+#define    p_reg_ep0_tx_nak_int_en  0xDD14
+#define reg_ep0_tx_nak_int_en_pos 0
+#define reg_ep0_tx_nak_int_en_len 1
+#define reg_ep0_tx_nak_int_en_lsb 0
+#define    p_reg_ep0_rx_nak_int_en  0xDD14
+#define reg_ep0_rx_nak_int_en_pos 1
+#define reg_ep0_rx_nak_int_en_len 1
+#define reg_ep0_rx_nak_int_en_lsb 0
+#define    p_reg_ep1_tx_nak_int_en  0xDD14
+#define reg_ep1_tx_nak_int_en_pos 2
+#define reg_ep1_tx_nak_int_en_len 1
+#define reg_ep1_tx_nak_int_en_lsb 0
+#define    p_reg_ep2_rx_nak_int_en  0xDD14
+#define reg_ep2_rx_nak_int_en_pos 3
+#define reg_ep2_rx_nak_int_en_len 1
+#define reg_ep2_rx_nak_int_en_lsb 0
+#define    p_reg_ep3_tx_nak_int_en  0xDD14
+#define reg_ep3_tx_nak_int_en_pos 4
+#define reg_ep3_tx_nak_int_en_len 1
+#define reg_ep3_tx_nak_int_en_lsb 0
+#define    p_reg_ep4_tx_nak_int_en  0xDD14
+#define reg_ep4_tx_nak_int_en_pos 5
+#define reg_ep4_tx_nak_int_en_len 1
+#define reg_ep4_tx_nak_int_en_lsb 0
+#define    p_reg_ep5_tx_nak_int_en  0xDD14
+#define reg_ep5_tx_nak_int_en_pos 6
+#define reg_ep5_tx_nak_int_en_len 1
+#define reg_ep5_tx_nak_int_en_lsb 0
+#define    p_reg_ep6_tx_nak_int_en  0xDD14
+#define reg_ep6_tx_nak_int_en_pos 7
+#define reg_ep6_tx_nak_int_en_len 1
+#define reg_ep6_tx_nak_int_en_lsb 0
+#define    p_reg_ep0_tx_done_int_en 0xDD15
+#define reg_ep0_tx_done_int_en_pos 0
+#define reg_ep0_tx_done_int_en_len 1
+#define reg_ep0_tx_done_int_en_lsb 0
+#define    p_reg_ep0_rx_done_int_en 0xDD15
+#define reg_ep0_rx_done_int_en_pos 1
+#define reg_ep0_rx_done_int_en_len 1
+#define reg_ep0_rx_done_int_en_lsb 0
+#define    p_reg_ep1_tx_done_int_en 0xDD15
+#define reg_ep1_tx_done_int_en_pos 2
+#define reg_ep1_tx_done_int_en_len 1
+#define reg_ep1_tx_done_int_en_lsb 0
+#define    p_reg_ep2_rx_done_int_en 0xDD15
+#define reg_ep2_rx_done_int_en_pos 3
+#define reg_ep2_rx_done_int_en_len 1
+#define reg_ep2_rx_done_int_en_lsb 0
+#define    p_reg_ep3_tx_done_int_en 0xDD15
+#define reg_ep3_tx_done_int_en_pos 4
+#define reg_ep3_tx_done_int_en_len 1
+#define reg_ep3_tx_done_int_en_lsb 0
+#define    p_reg_ep4_tx_done_int_en 0xDD15
+#define reg_ep4_tx_done_int_en_pos 5
+#define reg_ep4_tx_done_int_en_len 1
+#define reg_ep4_tx_done_int_en_lsb 0
+#define    p_reg_ep5_tx_done_int_en 0xDD15
+#define reg_ep5_tx_done_int_en_pos 6
+#define reg_ep5_tx_done_int_en_len 1
+#define reg_ep5_tx_done_int_en_lsb 0
+#define    p_reg_ep6_tx_done_int_en 0xDD15
+#define reg_ep6_tx_done_int_en_pos 7
+#define reg_ep6_tx_done_int_en_len 1
+#define reg_ep6_tx_done_int_en_lsb 0
+#define    p_reg_ep0_tx_fail_int_en 0xDD16
+#define reg_ep0_tx_fail_int_en_pos 0
+#define reg_ep0_tx_fail_int_en_len 1
+#define reg_ep0_tx_fail_int_en_lsb 0
+#define    p_reg_ep0_rx_fail_int_en 0xDD16
+#define reg_ep0_rx_fail_int_en_pos 1
+#define reg_ep0_rx_fail_int_en_len 1
+#define reg_ep0_rx_fail_int_en_lsb 0
+#define    p_reg_ep1_tx_fail_int_en 0xDD16
+#define reg_ep1_tx_fail_int_en_pos 2
+#define reg_ep1_tx_fail_int_en_len 1
+#define reg_ep1_tx_fail_int_en_lsb 0
+#define    p_reg_ep2_rx_fail_int_en 0xDD16
+#define reg_ep2_rx_fail_int_en_pos 3
+#define reg_ep2_rx_fail_int_en_len 1
+#define reg_ep2_rx_fail_int_en_lsb 0
+#define    p_reg_ep3_tx_fail_int_en 0xDD16
+#define reg_ep3_tx_fail_int_en_pos 4
+#define reg_ep3_tx_fail_int_en_len 1
+#define reg_ep3_tx_fail_int_en_lsb 0
+#define    p_reg_ep4_tx_fail_int_en 0xDD16
+#define reg_ep4_tx_fail_int_en_pos 5
+#define reg_ep4_tx_fail_int_en_len 1
+#define reg_ep4_tx_fail_int_en_lsb 0
+#define    p_reg_ep5_tx_fail_int_en 0xDD16
+#define reg_ep5_tx_fail_int_en_pos 6
+#define reg_ep5_tx_fail_int_en_len 1
+#define reg_ep5_tx_fail_int_en_lsb 0
+#define    p_reg_ep6_tx_fail_int_en 0xDD16
+#define reg_ep6_tx_fail_int_en_pos 7
+#define reg_ep6_tx_fail_int_en_len 1
+#define reg_ep6_tx_fail_int_en_lsb 0
+#define    p_reg_suspend_int_en 0xDD17
+#define reg_suspend_int_en_pos 0
+#define reg_suspend_int_en_len 1
+#define reg_suspend_int_en_lsb 0
+#define    p_reg_bus_reset_int_en   0xDD17
+#define reg_bus_reset_int_en_pos 1
+#define reg_bus_reset_int_en_len 1
+#define reg_bus_reset_int_en_lsb 0
+#define    p_reg_ep0_setup_int_en   0xDD17
+#define reg_ep0_setup_int_en_pos 2
+#define reg_ep0_setup_int_en_len 1
+#define reg_ep0_setup_int_en_lsb 0
+#define    p_reg_ep0_tx_nak_int 0xDD18
+#define reg_ep0_tx_nak_int_pos 0
+#define reg_ep0_tx_nak_int_len 1
+#define reg_ep0_tx_nak_int_lsb 0
+#define    p_reg_ep0_rx_nak_int 0xDD18
+#define reg_ep0_rx_nak_int_pos 1
+#define reg_ep0_rx_nak_int_len 1
+#define reg_ep0_rx_nak_int_lsb 0
+#define    p_reg_ep1_tx_nak_int 0xDD18
+#define reg_ep1_tx_nak_int_pos 2
+#define reg_ep1_tx_nak_int_len 1
+#define reg_ep1_tx_nak_int_lsb 0
+#define    p_reg_ep2_rx_nak_int 0xDD18
+#define reg_ep2_rx_nak_int_pos 3
+#define reg_ep2_rx_nak_int_len 1
+#define reg_ep2_rx_nak_int_lsb 0
+#define    p_reg_ep3_tx_nak_int 0xDD18
+#define reg_ep3_tx_nak_int_pos 4
+#define reg_ep3_tx_nak_int_len 1
+#define reg_ep3_tx_nak_int_lsb 0
+#define    p_reg_ep4_tx_nak_int 0xDD18
+#define reg_ep4_tx_nak_int_pos 5
+#define reg_ep4_tx_nak_int_len 1
+#define reg_ep4_tx_nak_int_lsb 0
+#define    p_reg_ep5_tx_nak_int 0xDD18
+#define reg_ep5_tx_nak_int_pos 6
+#define reg_ep5_tx_nak_int_len 1
+#define reg_ep5_tx_nak_int_lsb 0
+#define    p_reg_ep6_tx_nak_int 0xDD18
+#define reg_ep6_tx_nak_int_pos 7
+#define reg_ep6_tx_nak_int_len 1
+#define reg_ep6_tx_nak_int_lsb 0
+#define    p_reg_ep0_tx_done_int    0xDD19
+#define reg_ep0_tx_done_int_pos 0
+#define reg_ep0_tx_done_int_len 1
+#define reg_ep0_tx_done_int_lsb 0
+#define    p_reg_ep0_rx_done_int    0xDD19
+#define reg_ep0_rx_done_int_pos 1
+#define reg_ep0_rx_done_int_len 1
+#define reg_ep0_rx_done_int_lsb 0
+#define    p_reg_ep1_tx_done_int    0xDD19
+#define reg_ep1_tx_done_int_pos 2
+#define reg_ep1_tx_done_int_len 1
+#define reg_ep1_tx_done_int_lsb 0
+#define    p_reg_ep2_rx_done_int    0xDD19
+#define reg_ep2_rx_done_int_pos 3
+#define reg_ep2_rx_done_int_len 1
+#define reg_ep2_rx_done_int_lsb 0
+#define    p_reg_ep3_tx_done_int    0xDD19
+#define reg_ep3_tx_done_int_pos 4
+#define reg_ep3_tx_done_int_len 1
+#define reg_ep3_tx_done_int_lsb 0
+#define    p_reg_ep4_tx_done_int    0xDD19
+#define reg_ep4_tx_done_int_pos 5
+#define reg_ep4_tx_done_int_len 1
+#define reg_ep4_tx_done_int_lsb 0
+#define    p_reg_ep5_tx_done_int    0xDD19
+#define reg_ep5_tx_done_int_pos 6
+#define reg_ep5_tx_done_int_len 1
+#define reg_ep5_tx_done_int_lsb 0
+#define    p_reg_ep6_tx_done_int    0xDD19
+#define reg_ep6_tx_done_int_pos 7
+#define reg_ep6_tx_done_int_len 1
+#define reg_ep6_tx_done_int_lsb 0
+#define    p_reg_ep0_tx_fail_int    0xDD1A
+#define reg_ep0_tx_fail_int_pos 0
+#define reg_ep0_tx_fail_int_len 1
+#define reg_ep0_tx_fail_int_lsb 0
+#define    p_reg_ep0_rx_fail_int    0xDD1A
+#define reg_ep0_rx_fail_int_pos 1
+#define reg_ep0_rx_fail_int_len 1
+#define reg_ep0_rx_fail_int_lsb 0
+#define    p_reg_ep1_tx_fail_int    0xDD1A
+#define reg_ep1_tx_fail_int_pos 2
+#define reg_ep1_tx_fail_int_len 1
+#define reg_ep1_tx_fail_int_lsb 0
+#define    p_reg_ep2_rx_fail_int    0xDD1A
+#define reg_ep2_rx_fail_int_pos 3
+#define reg_ep2_rx_fail_int_len 1
+#define reg_ep2_rx_fail_int_lsb 0
+#define    p_reg_ep3_tx_fail_int    0xDD1A
+#define reg_ep3_tx_fail_int_pos 4
+#define reg_ep3_tx_fail_int_len 1
+#define reg_ep3_tx_fail_int_lsb 0
+#define    p_reg_ep4_tx_fail_int    0xDD1A
+#define reg_ep4_tx_fail_int_pos 5
+#define reg_ep4_tx_fail_int_len 1
+#define reg_ep4_tx_fail_int_lsb 0
+#define    p_reg_ep5_tx_fail_int    0xDD1A
+#define reg_ep5_tx_fail_int_pos 6
+#define reg_ep5_tx_fail_int_len 1
+#define reg_ep5_tx_fail_int_lsb 0
+#define    p_reg_ep6_tx_fail_int    0xDD1A
+#define reg_ep6_tx_fail_int_pos 7
+#define reg_ep6_tx_fail_int_len 1
+#define reg_ep6_tx_fail_int_lsb 0
+#define    p_reg_suspend_int    0xDD1B
+#define reg_suspend_int_pos 0
+#define reg_suspend_int_len 1
+#define reg_suspend_int_lsb 0
+#define    p_reg_bus_reset_int  0xDD1B
+#define reg_bus_reset_int_pos 1
+#define reg_bus_reset_int_len 1
+#define reg_bus_reset_int_lsb 0
+#define    p_reg_ep0_setup_int  0xDD1B
+#define reg_ep0_setup_int_pos 2
+#define reg_ep0_setup_int_len 1
+#define reg_ep0_setup_int_lsb 0
+#define    r_usbc_int   0xDD1B
+#define usbc_int_pos 3
+#define usbc_int_len 1
+#define usbc_int_lsb 0
+#define    r_usb_ir_int 0xDD1B
+#define usb_ir_int_pos 4
+#define usb_ir_int_len 1
+#define usb_ir_int_lsb 0
+#define    p_reg_ep0_tx_rst 0xDD1D
+#define reg_ep0_tx_rst_pos 0
+#define reg_ep0_tx_rst_len 1
+#define reg_ep0_tx_rst_lsb 0
+#define    p_reg_ep0_rx_rst 0xDD1D
+#define reg_ep0_rx_rst_pos 1
+#define reg_ep0_rx_rst_len 1
+#define reg_ep0_rx_rst_lsb 0
+#define    p_reg_ep1_tx_rst 0xDD1D
+#define reg_ep1_tx_rst_pos 2
+#define reg_ep1_tx_rst_len 1
+#define reg_ep1_tx_rst_lsb 0
+#define    p_reg_ep2_rx_rst 0xDD1D
+#define reg_ep2_rx_rst_pos 3
+#define reg_ep2_rx_rst_len 1
+#define reg_ep2_rx_rst_lsb 0
+#define    p_reg_ep3_tx_rst 0xDD1D
+#define reg_ep3_tx_rst_pos 4
+#define reg_ep3_tx_rst_len 1
+#define reg_ep3_tx_rst_lsb 0
+#define    p_reg_ep4_tx_rst 0xDD1D
+#define reg_ep4_tx_rst_pos 5
+#define reg_ep4_tx_rst_len 1
+#define reg_ep4_tx_rst_lsb 0
+#define    p_reg_ep5_tx_rst 0xDD1D
+#define reg_ep5_tx_rst_pos 6
+#define reg_ep5_tx_rst_len 1
+#define reg_ep5_tx_rst_lsb 0
+#define    p_reg_ep6_tx_rst 0xDD1D
+#define reg_ep6_tx_rst_pos 7
+#define reg_ep6_tx_rst_len 1
+#define reg_ep6_tx_rst_lsb 0
+#define    r_reg_ep0_tx_active  0xDD1E
+#define reg_ep0_tx_active_pos 0
+#define reg_ep0_tx_active_len 1
+#define reg_ep0_tx_active_lsb 0
+#define    r_reg_ep0_rx_active  0xDD1E
+#define reg_ep0_rx_active_pos 1
+#define reg_ep0_rx_active_len 1
+#define reg_ep0_rx_active_lsb 0
+#define    r_reg_ep1_tx_active  0xDD1E
+#define reg_ep1_tx_active_pos 2
+#define reg_ep1_tx_active_len 1
+#define reg_ep1_tx_active_lsb 0
+#define    r_reg_ep2_rx_active  0xDD1E
+#define reg_ep2_rx_active_pos 3
+#define reg_ep2_rx_active_len 1
+#define reg_ep2_rx_active_lsb 0
+#define    r_reg_ep3_tx_active  0xDD1E
+#define reg_ep3_tx_active_pos 4
+#define reg_ep3_tx_active_len 1
+#define reg_ep3_tx_active_lsb 0
+#define    r_reg_ep4_tx_active  0xDD1E
+#define reg_ep4_tx_active_pos 5
+#define reg_ep4_tx_active_len 1
+#define reg_ep4_tx_active_lsb 0
+#define    r_reg_ep5_tx_active  0xDD1E
+#define reg_ep5_tx_active_pos 6
+#define reg_ep5_tx_active_len 1
+#define reg_ep5_tx_active_lsb 0
+#define    r_reg_ep6_tx_active  0xDD1E
+#define reg_ep6_tx_active_pos 7
+#define reg_ep6_tx_active_len 1
+#define reg_ep6_tx_active_lsb 0
+#define    p_reg_usb_setup_reset    0xDD1F
+#define reg_usb_setup_reset_pos 0
+#define reg_usb_setup_reset_len 1
+#define reg_usb_setup_reset_lsb 0
+#define    p_reg_usb_ep4_retry_new  0xDD1F
+#define reg_usb_ep4_retry_new_pos 1
+#define reg_usb_ep4_retry_new_len 1
+#define reg_usb_ep4_retry_new_lsb 0
+#define    p_reg_usb_ep5_retry_new  0xDD1F
+#define reg_usb_ep5_retry_new_pos 2
+#define reg_usb_ep5_retry_new_len 1
+#define reg_usb_ep5_retry_new_lsb 0
+#define    p_reg_usb_ep6_retry_new  0xDD1F
+#define reg_usb_ep6_retry_new_pos 3
+#define reg_usb_ep6_retry_new_len 1
+#define reg_usb_ep6_retry_new_lsb 0
+#define    p_reg_usb_iso_mult_cnt   0xDD20
+#define reg_usb_iso_mult_cnt_pos 0
+#define reg_usb_iso_mult_cnt_len 2
+#define reg_usb_iso_mult_cnt_lsb 0
+#define    p_reg_p_iso_fix_en   0xDD21
+#define reg_p_iso_fix_en_pos 0
+#define reg_p_iso_fix_en_len 1
+#define reg_p_iso_fix_en_lsb 0
+#define    p_reg_p_iso_fix_rst  0xDD22
+#define reg_p_iso_fix_rst_pos 0
+#define reg_p_iso_fix_rst_len 1
+#define reg_p_iso_fix_rst_lsb 0
+#define    p_reg_p_read_point_7_0   0xDD23
+#define reg_p_read_point_7_0_pos 0
+#define reg_p_read_point_7_0_len 8
+#define reg_p_read_point_7_0_lsb 0
+#define    p_reg_p_read_point_11_8  0xDD24
+#define reg_p_read_point_11_8_pos 0
+#define reg_p_read_point_11_8_len 4
+#define reg_p_read_point_11_8_lsb 8
+#define    p_reg_p_dbg_ctrl 0xDD25
+#define reg_p_dbg_ctrl_pos 0
+#define reg_p_dbg_ctrl_len 3
+#define reg_p_dbg_ctrl_lsb 0
+#define    p_reg_p_data_swap    0xDD26
+#define reg_p_data_swap_pos 0
+#define reg_p_data_swap_len 2
+#define reg_p_data_swap_lsb 0
+#define    p_reg_ep_rx_addr 0xDD80
+#define reg_ep_rx_addr_pos 2
+#define reg_ep_rx_addr_len 6
+#define reg_ep_rx_addr_lsb 0
+#define    p_reg_ep0_tx_addr    0xDD81
+#define reg_ep0_tx_addr_pos 2
+#define reg_ep0_tx_addr_len 6
+#define reg_ep0_tx_addr_lsb 0
+#define    p_reg_ep1_tx_addr    0xDD82
+#define reg_ep1_tx_addr_pos 2
+#define reg_ep1_tx_addr_len 6
+#define reg_ep1_tx_addr_lsb 0
+#define    p_reg_ep3_tx_addr    0xDD83
+#define reg_ep3_tx_addr_pos 2
+#define reg_ep3_tx_addr_len 6
+#define reg_ep3_tx_addr_lsb 0
+#define    p_reg_ep_rx_len  0xDD84
+#define reg_ep_rx_len_pos 0
+#define reg_ep_rx_len_len 8
+#define reg_ep_rx_len_lsb 0
+#define    p_reg_ep0_tx_len 0xDD85
+#define reg_ep0_tx_len_pos 0
+#define reg_ep0_tx_len_len 8
+#define reg_ep0_tx_len_lsb 0
+#define    p_reg_ep1_tx_len 0xDD86
+#define reg_ep1_tx_len_pos 0
+#define reg_ep1_tx_len_len 8
+#define reg_ep1_tx_len_lsb 0
+#define    p_reg_ep3_tx_len 0xDD87
+#define reg_ep3_tx_len_pos 0
+#define reg_ep3_tx_len_len 8
+#define reg_ep3_tx_len_lsb 0
+#define    p_reg_ep4_tx_len_7_0 0xDD88
+#define reg_ep4_tx_len_7_0_pos 0
+#define reg_ep4_tx_len_7_0_len 8
+#define reg_ep4_tx_len_7_0_lsb 0
+#define    p_reg_ep4_tx_len_15_8    0xDD89
+#define reg_ep4_tx_len_15_8_pos 0
+#define reg_ep4_tx_len_15_8_len 8
+#define reg_ep4_tx_len_15_8_lsb 8
+#define    p_reg_ep5_tx_len_7_0 0xDD8A
+#define reg_ep5_tx_len_7_0_pos 0
+#define reg_ep5_tx_len_7_0_len 8
+#define reg_ep5_tx_len_7_0_lsb 0
+#define    p_reg_ep5_tx_len_15_8    0xDD8B
+#define reg_ep5_tx_len_15_8_pos 0
+#define reg_ep5_tx_len_15_8_len 8
+#define reg_ep5_tx_len_15_8_lsb 8
+#define    p_reg_usb_reset_addr 0xDD8C
+#define reg_usb_reset_addr_pos 0
+#define reg_usb_reset_addr_len 7
+#define reg_usb_reset_addr_lsb 0
+#define    p_reg_usb_reset  0xDD8C
+#define reg_usb_reset_pos 7
+#define reg_usb_reset_len 1
+#define reg_usb_reset_lsb 0
+#define    p_reg_usb_sync_in    0xDD8D
+#define reg_usb_sync_in_pos 0
+#define reg_usb_sync_in_len 1
+#define reg_usb_sync_in_lsb 0
+#define    p_reg_usb_sync_txready   0xDD8D
+#define reg_usb_sync_txready_pos 1
+#define reg_usb_sync_txready_len 1
+#define reg_usb_sync_txready_lsb 0
+#define    p_reg_utmi_phy_suspend   0xDD8D
+#define reg_utmi_phy_suspend_pos 2
+#define reg_utmi_phy_suspend_len 1
+#define reg_utmi_phy_suspend_lsb 0
+#define    p_reg_usb_min_len    0xDD8D
+#define reg_usb_min_len_pos 3
+#define reg_usb_min_len_len 1
+#define reg_usb_min_len_lsb 0
+#define    p_reg_usb_phy_clksel 0xDD8D
+#define reg_usb_phy_clksel_pos 4
+#define reg_usb_phy_clksel_len 1
+#define reg_usb_phy_clksel_lsb 0
+#define    p_reg_ep6_tx_len_7_0 0xDD8E
+#define reg_ep6_tx_len_7_0_pos 0
+#define reg_ep6_tx_len_7_0_len 8
+#define reg_ep6_tx_len_7_0_lsb 0
+#define    p_reg_ep6_tx_len_15_8    0xDD8F
+#define reg_ep6_tx_len_15_8_pos 0
+#define reg_ep6_tx_len_15_8_len 8
+#define reg_ep6_tx_len_15_8_lsb 8
+#define    p_reg_usb_clk_phase  0xDD93
+#define reg_usb_clk_phase_pos 0
+#define reg_usb_clk_phase_len 2
+#define reg_usb_clk_phase_lsb 0
+#define    p_reg_usb_clk_sel    0xDD93
+#define reg_usb_clk_sel_pos 4
+#define reg_usb_clk_sel_len 4
+#define reg_usb_clk_sel_lsb 0
+#define    p_reg_usb_fifo_ptr   0xDD94
+#define reg_usb_fifo_ptr_pos 0
+#define reg_usb_fifo_ptr_len 3
+#define reg_usb_fifo_ptr_lsb 0
+#define    p_reg_usb_fifo_byte  0xDD94
+#define reg_usb_fifo_byte_pos 3
+#define reg_usb_fifo_byte_len 2
+#define reg_usb_fifo_byte_lsb 0
+#define    p_reg_usb_fifo_sys   0xDD94
+#define reg_usb_fifo_sys_pos 5
+#define reg_usb_fifo_sys_len 1
+#define reg_usb_fifo_sys_lsb 0
+#define    p_usbdma_utmi_d_ctl_7_0  0xDD9E
+#define usbdma_utmi_d_ctl_7_0_pos 0
+#define usbdma_utmi_d_ctl_7_0_len 8
+#define usbdma_utmi_d_ctl_7_0_lsb 0
+#define    p_usbdma_utmi_d_ctl_13_8 0xDD9F
+#define usbdma_utmi_d_ctl_13_8_pos 0
+#define usbdma_utmi_d_ctl_13_8_len 6
+#define usbdma_utmi_d_ctl_13_8_lsb 8
+#define    p_usbdma_utmi_a_ctl_7_0  0xDDA0
+#define usbdma_utmi_a_ctl_7_0_pos 0
+#define usbdma_utmi_a_ctl_7_0_len 8
+#define usbdma_utmi_a_ctl_7_0_lsb 0
+#define    p_usbdma_utmi_a_ctl_15_8 0xDDA1
+#define usbdma_utmi_a_ctl_15_8_pos 0
+#define usbdma_utmi_a_ctl_15_8_len 8
+#define usbdma_utmi_a_ctl_15_8_lsb 8
+#define    p_usbdma_utmi_a_ctl_23_16    0xDDA2
+#define usbdma_utmi_a_ctl_23_16_pos 0
+#define usbdma_utmi_a_ctl_23_16_len 8
+#define usbdma_utmi_a_ctl_23_16_lsb 16
+#define    p_usbdma_utmi_a_ctl_31_24    0xDDA3
+#define usbdma_utmi_a_ctl_31_24_pos 0
+#define usbdma_utmi_a_ctl_31_24_len 8
+#define usbdma_utmi_a_ctl_31_24_lsb 24
+#define    p_usbdma_utmi_a_ctl_39_32    0xDDA4
+#define usbdma_utmi_a_ctl_39_32_pos 0
+#define usbdma_utmi_a_ctl_39_32_len 8
+#define usbdma_utmi_a_ctl_39_32_lsb 32
+#define    p_usbdma_utmi_a_ctl_47_40    0xDDA5
+#define usbdma_utmi_a_ctl_47_40_pos 0
+#define usbdma_utmi_a_ctl_47_40_len 8
+#define usbdma_utmi_a_ctl_47_40_lsb 40
+#define    p_usbdma_utmi_pwrmode    0xDDA6
+#define usbdma_utmi_pwrmode_pos 3
+#define usbdma_utmi_pwrmode_len 1
+#define usbdma_utmi_pwrmode_lsb 0
+#define    p_usbdma_utmi_test_out   0xDDA6
+#define usbdma_utmi_test_out_pos 4
+#define usbdma_utmi_test_out_len 1
+#define usbdma_utmi_test_out_lsb 0
+#define    p_usbdma_utmi_vbus_int_en    0xDDA7
+#define usbdma_utmi_vbus_int_en_pos 0
+#define usbdma_utmi_vbus_int_en_len 1
+#define usbdma_utmi_vbus_int_en_lsb 0
+#define    p_usbdma_utmi_vbus_int_pol   0xDDA7
+#define usbdma_utmi_vbus_int_pol_pos 1
+#define usbdma_utmi_vbus_int_pol_len 1
+#define usbdma_utmi_vbus_int_pol_lsb 0
+#define    r_usbdma_utmi_vbus_int   0xDDA8
+#define usbdma_utmi_vbus_int_pos 0
+#define usbdma_utmi_vbus_int_len 1
+#define usbdma_utmi_vbus_int_lsb 0
+#define    r_usbdma_utmi_vbus_status    0xDDA8
+#define usbdma_utmi_vbus_status_pos 1
+#define usbdma_utmi_vbus_status_len 1
+#define usbdma_utmi_vbus_status_lsb 0
+#define    r_usbdma_utmi_clkrdy 0xDDA8
+#define usbdma_utmi_clkrdy_pos 2
+#define usbdma_utmi_clkrdy_len 1
+#define usbdma_utmi_clkrdy_lsb 0
+#define    p_reg_p_usb_iso_ccir_rst 0xDDA9
+#define reg_p_usb_iso_ccir_rst_pos 0
+#define reg_p_usb_iso_ccir_rst_len 1
+#define reg_p_usb_iso_ccir_rst_lsb 0
+#define    p_reg_p_usb_iso_ccir 0xDDA9
+#define reg_p_usb_iso_ccir_pos 1
+#define reg_p_usb_iso_ccir_len 1
+#define reg_p_usb_iso_ccir_lsb 0
+#define    p_reg_p_ccir_fix_en  0xDDAA
+#define reg_p_ccir_fix_en_pos 0
+#define reg_p_ccir_fix_en_len 1
+#define reg_p_ccir_fix_en_lsb 0
+#define    p_ir_sys_clk 0xDF80
+#define ir_sys_clk_pos 0
+#define ir_sys_clk_len 8
+#define ir_sys_clk_lsb 0
+#define    p_ir_sample_clk  0xDF81
+#define ir_sample_clk_pos 0
+#define ir_sample_clk_len 2
+#define ir_sample_clk_lsb 0
+#define    p_ir_idle_polarity   0xDF81
+#define ir_idle_polarity_pos 2
+#define ir_idle_polarity_len 1
+#define ir_idle_polarity_lsb 0
+#define    p_ir_fifo_ovfl   0xDF82
+#define ir_fifo_ovfl_pos 0
+#define ir_fifo_ovfl_len 1
+#define ir_fifo_ovfl_lsb 0
+#define    r_ir_fifo_empty  0xDF82
+#define ir_fifo_empty_pos 1
+#define ir_fifo_empty_len 1
+#define ir_fifo_empty_lsb 0
+#define    r_ir_fifo_cnt    0xDF82
+#define ir_fifo_cnt_pos 2
+#define ir_fifo_cnt_len 3
+#define ir_fifo_cnt_lsb 0
+#define    p_ir_fifo_rst    0xDF82
+#define ir_fifo_rst_pos 5
+#define ir_fifo_rst_len 1
+#define ir_fifo_rst_lsb 0
+#define    p_reg_ir_out_th0_7_0 0xDF84
+#define reg_ir_out_th0_7_0_pos 0
+#define reg_ir_out_th0_7_0_len 8
+#define reg_ir_out_th0_7_0_lsb 0
+#define    p_reg_ir_out_th0_14_8    0xDF85
+#define reg_ir_out_th0_14_8_pos 0
+#define reg_ir_out_th0_14_8_len 7
+#define reg_ir_out_th0_14_8_lsb 8
+#define    p_reg_ir_out_th1_7_0 0xDF86
+#define reg_ir_out_th1_7_0_pos 0
+#define reg_ir_out_th1_7_0_len 8
+#define reg_ir_out_th1_7_0_lsb 0
+#define    p_reg_ir_out_th1_14_8    0xDF87
+#define reg_ir_out_th1_14_8_pos 0
+#define reg_ir_out_th1_14_8_len 7
+#define reg_ir_out_th1_14_8_lsb 8
+#define    p_reg_ir_out_th2_7_0 0xDF88
+#define reg_ir_out_th2_7_0_pos 0
+#define reg_ir_out_th2_7_0_len 8
+#define reg_ir_out_th2_7_0_lsb 0
+#define    p_reg_ir_out_th2_14_8    0xDF89
+#define reg_ir_out_th2_14_8_pos 0
+#define reg_ir_out_th2_14_8_len 7
+#define reg_ir_out_th2_14_8_lsb 8
+#define    p_reg_ir_out_th3_7_0 0xDF8A
+#define reg_ir_out_th3_7_0_pos 0
+#define reg_ir_out_th3_7_0_len 8
+#define reg_ir_out_th3_7_0_lsb 0
+#define    p_reg_ir_out_th3_14_8    0xDF8B
+#define reg_ir_out_th3_14_8_pos 0
+#define reg_ir_out_th3_14_8_len 7
+#define reg_ir_out_th3_14_8_lsb 8
+#define    p_reg_ir_out_th4_7_0 0xDF8C
+#define reg_ir_out_th4_7_0_pos 0
+#define reg_ir_out_th4_7_0_len 8
+#define reg_ir_out_th4_7_0_lsb 0
+#define    p_reg_ir_out_th4_14_8    0xDF8D
+#define reg_ir_out_th4_14_8_pos 0
+#define reg_ir_out_th4_14_8_len 7
+#define reg_ir_out_th4_14_8_lsb 8
+#define    p_reg_ir_out_th5_7_0 0xDF8E
+#define reg_ir_out_th5_7_0_pos 0
+#define reg_ir_out_th5_7_0_len 8
+#define reg_ir_out_th5_7_0_lsb 0
+#define    p_reg_ir_out_th5_14_8    0xDF8F
+#define reg_ir_out_th5_14_8_pos 0
+#define reg_ir_out_th5_14_8_len 7
+#define reg_ir_out_th5_14_8_lsb 8
+#define    p_reg_ir_out_th6_7_0 0xDF90
+#define reg_ir_out_th6_7_0_pos 0
+#define reg_ir_out_th6_7_0_len 8
+#define reg_ir_out_th6_7_0_lsb 0
+#define    p_reg_ir_out_th6_14_8    0xDF91
+#define reg_ir_out_th6_14_8_pos 0
+#define reg_ir_out_th6_14_8_len 7
+#define reg_ir_out_th6_14_8_lsb 8
+#define    p_reg_ir_out_th7_7_0 0xDF92
+#define reg_ir_out_th7_7_0_pos 0
+#define reg_ir_out_th7_7_0_len 8
+#define reg_ir_out_th7_7_0_lsb 0
+#define    p_reg_ir_out_th7_14_8    0xDF93
+#define reg_ir_out_th7_14_8_pos 0
+#define reg_ir_out_th7_14_8_len 7
+#define reg_ir_out_th7_14_8_lsb 8
+#define    p_reg_ir_out_th8_7_0 0xDF94
+#define reg_ir_out_th8_7_0_pos 0
+#define reg_ir_out_th8_7_0_len 8
+#define reg_ir_out_th8_7_0_lsb 0
+#define    p_reg_ir_out_th8_14_8    0xDF95
+#define reg_ir_out_th8_14_8_pos 0
+#define reg_ir_out_th8_14_8_len 7
+#define reg_ir_out_th8_14_8_lsb 8
+#define    p_reg_ir_out_th9_7_0 0xDF96
+#define reg_ir_out_th9_7_0_pos 0
+#define reg_ir_out_th9_7_0_len 8
+#define reg_ir_out_th9_7_0_lsb 0
+#define    p_reg_ir_out_th9_14_8    0xDF97
+#define reg_ir_out_th9_14_8_pos 0
+#define reg_ir_out_th9_14_8_len 7
+#define reg_ir_out_th9_14_8_lsb 8
+#define    p_reg_ir_out_th10_7_0    0xDF98
+#define reg_ir_out_th10_7_0_pos 0
+#define reg_ir_out_th10_7_0_len 8
+#define reg_ir_out_th10_7_0_lsb 0
+#define    p_reg_ir_out_th10_14_8   0xDF99
+#define reg_ir_out_th10_14_8_pos 0
+#define reg_ir_out_th10_14_8_len 7
+#define reg_ir_out_th10_14_8_lsb 8
+#define    p_reg_ir_out_th11_7_0    0xDF9A
+#define reg_ir_out_th11_7_0_pos 0
+#define reg_ir_out_th11_7_0_len 8
+#define reg_ir_out_th11_7_0_lsb 0
+#define    p_reg_ir_out_th11_14_8   0xDF9B
+#define reg_ir_out_th11_14_8_pos 0
+#define reg_ir_out_th11_14_8_len 7
+#define reg_ir_out_th11_14_8_lsb 8
+#define    p_reg_ir_out_th12_7_0    0xDF9C
+#define reg_ir_out_th12_7_0_pos 0
+#define reg_ir_out_th12_7_0_len 8
+#define reg_ir_out_th12_7_0_lsb 0
+#define    p_reg_ir_out_th12_14_8   0xDF9D
+#define reg_ir_out_th12_14_8_pos 0
+#define reg_ir_out_th12_14_8_len 7
+#define reg_ir_out_th12_14_8_lsb 8
+#define    p_reg_ir_out_th13_7_0    0xDF9E
+#define reg_ir_out_th13_7_0_pos 0
+#define reg_ir_out_th13_7_0_len 8
+#define reg_ir_out_th13_7_0_lsb 0
+#define    p_reg_ir_out_th13_14_8   0xDF9F
+#define reg_ir_out_th13_14_8_pos 0
+#define reg_ir_out_th13_14_8_len 7
+#define reg_ir_out_th13_14_8_lsb 8
+#define    p_reg_ir_out_th14_7_0    0xDFA0
+#define reg_ir_out_th14_7_0_pos 0
+#define reg_ir_out_th14_7_0_len 8
+#define reg_ir_out_th14_7_0_lsb 0
+#define    p_reg_ir_out_th14_14_8   0xDFA1
+#define reg_ir_out_th14_14_8_pos 0
+#define reg_ir_out_th14_14_8_len 7
+#define reg_ir_out_th14_14_8_lsb 8
+#define    p_reg_tuner_data_7_0 0xF000
+#define reg_tuner_data_7_0_pos 0
+#define reg_tuner_data_7_0_len 8
+#define reg_tuner_data_7_0_lsb 0
+#define    p_reg_tuner_data_15_8    0xF001
+#define reg_tuner_data_15_8_pos 0
+#define reg_tuner_data_15_8_len 8
+#define reg_tuner_data_15_8_lsb 8
+#define    p_reg_tuner_data_23_16   0xF002
+#define reg_tuner_data_23_16_pos 0
+#define reg_tuner_data_23_16_len 8
+#define reg_tuner_data_23_16_lsb 16
+#define    p_reg_tuner_data_31_24   0xF003
+#define reg_tuner_data_31_24_pos 0
+#define reg_tuner_data_31_24_len 8
+#define reg_tuner_data_31_24_lsb 24
+#define    p_reg_tuner_data_39_32   0xF004
+#define reg_tuner_data_39_32_pos 0
+#define reg_tuner_data_39_32_len 8
+#define reg_tuner_data_39_32_lsb 32
+#define    p_reg_tuner_data_47_40   0xF005
+#define reg_tuner_data_47_40_pos 0
+#define reg_tuner_data_47_40_len 8
+#define reg_tuner_data_47_40_lsb 40
+#define    p_reg_tuner_data_55_48   0xF006
+#define reg_tuner_data_55_48_pos 0
+#define reg_tuner_data_55_48_len 8
+#define reg_tuner_data_55_48_lsb 48
+#define    p_reg_tuner_data_63_56   0xF007
+#define reg_tuner_data_63_56_pos 0
+#define reg_tuner_data_63_56_len 8
+#define reg_tuner_data_63_56_lsb 56
+#define    p_reg_tuner_data_71_64   0xF008
+#define reg_tuner_data_71_64_pos 0
+#define reg_tuner_data_71_64_len 8
+#define reg_tuner_data_71_64_lsb 64
+#define    p_reg_tuner_data_79_72   0xF009
+#define reg_tuner_data_79_72_pos 0
+#define reg_tuner_data_79_72_len 8
+#define reg_tuner_data_79_72_lsb 72
+#define    p_reg_tuner_data_87_80   0xF00A
+#define reg_tuner_data_87_80_pos 0
+#define reg_tuner_data_87_80_len 8
+#define reg_tuner_data_87_80_lsb 80
+#define    p_reg_tuner_data_95_88   0xF00B
+#define reg_tuner_data_95_88_pos 0
+#define reg_tuner_data_95_88_len 8
+#define reg_tuner_data_95_88_lsb 88
+#define    p_reg_tuner_data_103_96  0xF00C
+#define reg_tuner_data_103_96_pos 0
+#define reg_tuner_data_103_96_len 8
+#define reg_tuner_data_103_96_lsb 96
+#define    p_reg_tuner_data_111_104 0xF00D
+#define reg_tuner_data_111_104_pos 0
+#define reg_tuner_data_111_104_len 8
+#define reg_tuner_data_111_104_lsb 104
+#define    p_reg_tuner_data_119_112 0xF00E
+#define reg_tuner_data_119_112_pos 0
+#define reg_tuner_data_119_112_len 8
+#define reg_tuner_data_119_112_lsb 112
+#define    p_reg_tuner_data_127_120 0xF00F
+#define reg_tuner_data_127_120_pos 0
+#define reg_tuner_data_127_120_len 8
+#define reg_tuner_data_127_120_lsb 120
+#define    p_reg_tuner_data_135_128 0xF010
+#define reg_tuner_data_135_128_pos 0
+#define reg_tuner_data_135_128_len 8
+#define reg_tuner_data_135_128_lsb 128
+#define    p_reg_tuner_data_143_136 0xF011
+#define reg_tuner_data_143_136_pos 0
+#define reg_tuner_data_143_136_len 8
+#define reg_tuner_data_143_136_lsb 136
+#define    p_reg_tuner_data_151_144 0xF012
+#define reg_tuner_data_151_144_pos 0
+#define reg_tuner_data_151_144_len 8
+#define reg_tuner_data_151_144_lsb 144
+#define    p_reg_tuner_data_159_152 0xF013
+#define reg_tuner_data_159_152_pos 0
+#define reg_tuner_data_159_152_len 8
+#define reg_tuner_data_159_152_lsb 152
+#define    p_reg_tuner_data_167_160 0xF014
+#define reg_tuner_data_167_160_pos 0
+#define reg_tuner_data_167_160_len 8
+#define reg_tuner_data_167_160_lsb 160
+#define    p_reg_tuner_data_175_168 0xF015
+#define reg_tuner_data_175_168_pos 0
+#define reg_tuner_data_175_168_len 8
+#define reg_tuner_data_175_168_lsb 168
+#define    p_reg_tuner_data_183_176 0xF016
+#define reg_tuner_data_183_176_pos 0
+#define reg_tuner_data_183_176_len 8
+#define reg_tuner_data_183_176_lsb 176
+#define    p_reg_tuner_data_191_184 0xF017
+#define reg_tuner_data_191_184_pos 0
+#define reg_tuner_data_191_184_len 8
+#define reg_tuner_data_191_184_lsb 184
+#define    p_reg_tuner_data_199_192 0xF018
+#define reg_tuner_data_199_192_pos 0
+#define reg_tuner_data_199_192_len 8
+#define reg_tuner_data_199_192_lsb 192
+#define    p_reg_tuner_data_207_200 0xF019
+#define reg_tuner_data_207_200_pos 0
+#define reg_tuner_data_207_200_len 8
+#define reg_tuner_data_207_200_lsb 200
+#define    p_reg_tuner_data_215_208 0xF01A
+#define reg_tuner_data_215_208_pos 0
+#define reg_tuner_data_215_208_len 8
+#define reg_tuner_data_215_208_lsb 208
+#define    p_reg_tuner_data_223_216 0xF01B
+#define reg_tuner_data_223_216_pos 0
+#define reg_tuner_data_223_216_len 8
+#define reg_tuner_data_223_216_lsb 216
+#define    p_reg_tuner_data_231_224 0xF01C
+#define reg_tuner_data_231_224_pos 0
+#define reg_tuner_data_231_224_len 8
+#define reg_tuner_data_231_224_lsb 224
+#define    p_reg_tuner_data_239_232 0xF01D
+#define reg_tuner_data_239_232_pos 0
+#define reg_tuner_data_239_232_len 8
+#define reg_tuner_data_239_232_lsb 232
+#define    p_reg_tuner_data_247_240 0xF01E
+#define reg_tuner_data_247_240_pos 0
+#define reg_tuner_data_247_240_len 8
+#define reg_tuner_data_247_240_lsb 240
+#define    p_reg_tuner_data_255_248 0xF01F
+#define reg_tuner_data_255_248_pos 0
+#define reg_tuner_data_255_248_len 8
+#define reg_tuner_data_255_248_lsb 248
+#define    p_reg_tuner_data_263_256 0xF020
+#define reg_tuner_data_263_256_pos 0
+#define reg_tuner_data_263_256_len 8
+#define reg_tuner_data_263_256_lsb 256
+#define    p_reg_tuner_data_271_264 0xF021
+#define reg_tuner_data_271_264_pos 0
+#define reg_tuner_data_271_264_len 8
+#define reg_tuner_data_271_264_lsb 264
+#define    p_reg_tuner_data_279_272 0xF022
+#define reg_tuner_data_279_272_pos 0
+#define reg_tuner_data_279_272_len 8
+#define reg_tuner_data_279_272_lsb 272
+#define    p_reg_tuner_data_287_280 0xF023
+#define reg_tuner_data_287_280_pos 0
+#define reg_tuner_data_287_280_len 8
+#define reg_tuner_data_287_280_lsb 280
+#define    p_reg_tuner_data_295_288 0xF024
+#define reg_tuner_data_295_288_pos 0
+#define reg_tuner_data_295_288_len 8
+#define reg_tuner_data_295_288_lsb 288
+#define    p_reg_tuner_data_303_296 0xF025
+#define reg_tuner_data_303_296_pos 0
+#define reg_tuner_data_303_296_len 8
+#define reg_tuner_data_303_296_lsb 296
+#define    p_reg_tuner_data_311_304 0xF026
+#define reg_tuner_data_311_304_pos 0
+#define reg_tuner_data_311_304_len 8
+#define reg_tuner_data_311_304_lsb 304
+#define    p_reg_tuner_data_319_312 0xF027
+#define reg_tuner_data_319_312_pos 0
+#define reg_tuner_data_319_312_len 8
+#define reg_tuner_data_319_312_lsb 312
+#define    p_reg_tuner_data_327_320 0xF028
+#define reg_tuner_data_327_320_pos 0
+#define reg_tuner_data_327_320_len 8
+#define reg_tuner_data_327_320_lsb 320
+#define    p_reg_tuner_data_335_328 0xF029
+#define reg_tuner_data_335_328_pos 0
+#define reg_tuner_data_335_328_len 8
+#define reg_tuner_data_335_328_lsb 328
+#define    p_reg_tuner_data_343_336 0xF02A
+#define reg_tuner_data_343_336_pos 0
+#define reg_tuner_data_343_336_len 8
+#define reg_tuner_data_343_336_lsb 336
+#define    p_reg_tuner_data_351_344 0xF02B
+#define reg_tuner_data_351_344_pos 0
+#define reg_tuner_data_351_344_len 8
+#define reg_tuner_data_351_344_lsb 344
+#define    p_reg_tuner_data_359_352 0xF02C
+#define reg_tuner_data_359_352_pos 0
+#define reg_tuner_data_359_352_len 8
+#define reg_tuner_data_359_352_lsb 352
+#define    p_reg_tuner_data_367_360 0xF02D
+#define reg_tuner_data_367_360_pos 0
+#define reg_tuner_data_367_360_len 8
+#define reg_tuner_data_367_360_lsb 360
+#define    p_reg_tuner_data_375_368 0xF02E
+#define reg_tuner_data_375_368_pos 0
+#define reg_tuner_data_375_368_len 8
+#define reg_tuner_data_375_368_lsb 368
+#define    p_reg_tuner_data_383_376 0xF02F
+#define reg_tuner_data_383_376_pos 0
+#define reg_tuner_data_383_376_len 8
+#define reg_tuner_data_383_376_lsb 376
+#define    p_reg_tuner_data_391_384 0xF030
+#define reg_tuner_data_391_384_pos 0
+#define reg_tuner_data_391_384_len 8
+#define reg_tuner_data_391_384_lsb 384
+#define    p_reg_tuner_data_399_392 0xF031
+#define reg_tuner_data_399_392_pos 0
+#define reg_tuner_data_399_392_len 8
+#define reg_tuner_data_399_392_lsb 392
+#define    p_reg_tuner_data_407_400 0xF032
+#define reg_tuner_data_407_400_pos 0
+#define reg_tuner_data_407_400_len 8
+#define reg_tuner_data_407_400_lsb 400
+#define    p_reg_tuner_data_415_408 0xF033
+#define reg_tuner_data_415_408_pos 0
+#define reg_tuner_data_415_408_len 8
+#define reg_tuner_data_415_408_lsb 408
+#define    p_reg_tuner_data_423_416 0xF034
+#define reg_tuner_data_423_416_pos 0
+#define reg_tuner_data_423_416_len 8
+#define reg_tuner_data_423_416_lsb 416
+#define    p_reg_tuner_data_431_424 0xF035
+#define reg_tuner_data_431_424_pos 0
+#define reg_tuner_data_431_424_len 8
+#define reg_tuner_data_431_424_lsb 424
+#define    p_reg_tuner_data_439_432 0xF036
+#define reg_tuner_data_439_432_pos 0
+#define reg_tuner_data_439_432_len 8
+#define reg_tuner_data_439_432_lsb 432
+#define    p_reg_tuner_data_447_440 0xF037
+#define reg_tuner_data_447_440_pos 0
+#define reg_tuner_data_447_440_len 8
+#define reg_tuner_data_447_440_lsb 440
+#define    p_reg_tuner_data_455_448 0xF038
+#define reg_tuner_data_455_448_pos 0
+#define reg_tuner_data_455_448_len 8
+#define reg_tuner_data_455_448_lsb 448
+#define    p_reg_tuner_data_463_456 0xF039
+#define reg_tuner_data_463_456_pos 0
+#define reg_tuner_data_463_456_len 8
+#define reg_tuner_data_463_456_lsb 456
+#define    p_reg_tuner_data_471_464 0xF03A
+#define reg_tuner_data_471_464_pos 0
+#define reg_tuner_data_471_464_len 8
+#define reg_tuner_data_471_464_lsb 464
+#define    p_reg_tuner_data_479_472 0xF03B
+#define reg_tuner_data_479_472_pos 0
+#define reg_tuner_data_479_472_len 8
+#define reg_tuner_data_479_472_lsb 472
+#define    p_reg_tuner_data_487_480 0xF03C
+#define reg_tuner_data_487_480_pos 0
+#define reg_tuner_data_487_480_len 8
+#define reg_tuner_data_487_480_lsb 480
+#define    p_reg_tuner_data_495_488 0xF03D
+#define reg_tuner_data_495_488_pos 0
+#define reg_tuner_data_495_488_len 8
+#define reg_tuner_data_495_488_lsb 488
+#define    p_reg_tuner_data_503_496 0xF03E
+#define reg_tuner_data_503_496_pos 0
+#define reg_tuner_data_503_496_len 8
+#define reg_tuner_data_503_496_lsb 496
+#define    p_reg_tuner_data_511_504 0xF03F
+#define reg_tuner_data_511_504_pos 0
+#define reg_tuner_data_511_504_len 8
+#define reg_tuner_data_511_504_lsb 504
+#define    p_reg_tuner_data_519_512 0xF040
+#define reg_tuner_data_519_512_pos 0
+#define reg_tuner_data_519_512_len 8
+#define reg_tuner_data_519_512_lsb 512
+#define    p_reg_tuner_data_527_520 0xF041
+#define reg_tuner_data_527_520_pos 0
+#define reg_tuner_data_527_520_len 8
+#define reg_tuner_data_527_520_lsb 520
+#define    p_reg_tuner_data_535_528 0xF042
+#define reg_tuner_data_535_528_pos 0
+#define reg_tuner_data_535_528_len 8
+#define reg_tuner_data_535_528_lsb 528
+#define    p_reg_tuner_data_543_536 0xF043
+#define reg_tuner_data_543_536_pos 0
+#define reg_tuner_data_543_536_len 8
+#define reg_tuner_data_543_536_lsb 536
+#define    p_reg_tuner_data_551_544 0xF044
+#define reg_tuner_data_551_544_pos 0
+#define reg_tuner_data_551_544_len 8
+#define reg_tuner_data_551_544_lsb 544
+#define    p_reg_tuner_data_559_552 0xF045
+#define reg_tuner_data_559_552_pos 0
+#define reg_tuner_data_559_552_len 8
+#define reg_tuner_data_559_552_lsb 552
+#define    p_reg_tuner_data_567_560 0xF046
+#define reg_tuner_data_567_560_pos 0
+#define reg_tuner_data_567_560_len 8
+#define reg_tuner_data_567_560_lsb 560
+#define    p_reg_tuner_data_575_568 0xF047
+#define reg_tuner_data_575_568_pos 0
+#define reg_tuner_data_575_568_len 8
+#define reg_tuner_data_575_568_lsb 568
+#define    p_reg_tuner_data_583_576 0xF048
+#define reg_tuner_data_583_576_pos 0
+#define reg_tuner_data_583_576_len 8
+#define reg_tuner_data_583_576_lsb 576
+#define    p_reg_tuner_data_591_584 0xF049
+#define reg_tuner_data_591_584_pos 0
+#define reg_tuner_data_591_584_len 8
+#define reg_tuner_data_591_584_lsb 584
+#define    p_reg_tuner_data_599_592 0xF04A
+#define reg_tuner_data_599_592_pos 0
+#define reg_tuner_data_599_592_len 8
+#define reg_tuner_data_599_592_lsb 592
+#define    p_reg_tuner_data_607_600 0xF04B
+#define reg_tuner_data_607_600_pos 0
+#define reg_tuner_data_607_600_len 8
+#define reg_tuner_data_607_600_lsb 600
+#define    p_reg_tuner_data_615_608 0xF04C
+#define reg_tuner_data_615_608_pos 0
+#define reg_tuner_data_615_608_len 8
+#define reg_tuner_data_615_608_lsb 608
+#define    p_reg_tuner_data_623_616 0xF04D
+#define reg_tuner_data_623_616_pos 0
+#define reg_tuner_data_623_616_len 8
+#define reg_tuner_data_623_616_lsb 616
+#define    p_reg_tuner_data_631_624 0xF04E
+#define reg_tuner_data_631_624_pos 0
+#define reg_tuner_data_631_624_len 8
+#define reg_tuner_data_631_624_lsb 624
+#define    p_reg_tuner_data_639_632 0xF04F
+#define reg_tuner_data_639_632_pos 0
+#define reg_tuner_data_639_632_len 8
+#define reg_tuner_data_639_632_lsb 632
+#define    p_reg_tuner_data_647_640 0xF050
+#define reg_tuner_data_647_640_pos 0
+#define reg_tuner_data_647_640_len 8
+#define reg_tuner_data_647_640_lsb 640
+#define    p_reg_tuner_data_655_648 0xF051
+#define reg_tuner_data_655_648_pos 0
+#define reg_tuner_data_655_648_len 8
+#define reg_tuner_data_655_648_lsb 648
+#define    p_reg_tuner_data_663_656 0xF052
+#define reg_tuner_data_663_656_pos 0
+#define reg_tuner_data_663_656_len 8
+#define reg_tuner_data_663_656_lsb 656
+#define    p_reg_tuner_data_671_664 0xF053
+#define reg_tuner_data_671_664_pos 0
+#define reg_tuner_data_671_664_len 8
+#define reg_tuner_data_671_664_lsb 664
+#define    p_reg_tuner_data_679_672 0xF054
+#define reg_tuner_data_679_672_pos 0
+#define reg_tuner_data_679_672_len 8
+#define reg_tuner_data_679_672_lsb 672
+#define    p_reg_tuner_data_687_680 0xF055
+#define reg_tuner_data_687_680_pos 0
+#define reg_tuner_data_687_680_len 8
+#define reg_tuner_data_687_680_lsb 680
+#define    p_reg_tuner_data_695_688 0xF056
+#define reg_tuner_data_695_688_pos 0
+#define reg_tuner_data_695_688_len 8
+#define reg_tuner_data_695_688_lsb 688
+#define    p_reg_tuner_data_703_696 0xF057
+#define reg_tuner_data_703_696_pos 0
+#define reg_tuner_data_703_696_len 8
+#define reg_tuner_data_703_696_lsb 696
+#define    p_reg_tuner_data_711_704 0xF058
+#define reg_tuner_data_711_704_pos 0
+#define reg_tuner_data_711_704_len 8
+#define reg_tuner_data_711_704_lsb 704
+#define    p_reg_tuner_data_719_712 0xF059
+#define reg_tuner_data_719_712_pos 0
+#define reg_tuner_data_719_712_len 8
+#define reg_tuner_data_719_712_lsb 712
+#define    p_reg_tuner_data_727_720 0xF05A
+#define reg_tuner_data_727_720_pos 0
+#define reg_tuner_data_727_720_len 8
+#define reg_tuner_data_727_720_lsb 720
+#define    p_reg_tuner_data_735_728 0xF05B
+#define reg_tuner_data_735_728_pos 0
+#define reg_tuner_data_735_728_len 8
+#define reg_tuner_data_735_728_lsb 728
+#define    p_reg_tuner_data_743_736 0xF05C
+#define reg_tuner_data_743_736_pos 0
+#define reg_tuner_data_743_736_len 8
+#define reg_tuner_data_743_736_lsb 736
+#define    p_reg_tuner_data_751_744 0xF05D
+#define reg_tuner_data_751_744_pos 0
+#define reg_tuner_data_751_744_len 8
+#define reg_tuner_data_751_744_lsb 744
+#define    p_reg_tuner_data_759_752 0xF05E
+#define reg_tuner_data_759_752_pos 0
+#define reg_tuner_data_759_752_len 8
+#define reg_tuner_data_759_752_lsb 752
+#define    p_reg_tuner_data_767_760 0xF05F
+#define reg_tuner_data_767_760_pos 0
+#define reg_tuner_data_767_760_len 8
+#define reg_tuner_data_767_760_lsb 760
+#define    p_reg_tuner_data_775_768 0xF060
+#define reg_tuner_data_775_768_pos 0
+#define reg_tuner_data_775_768_len 8
+#define reg_tuner_data_775_768_lsb 768
+#define    p_reg_tuner_data_783_776 0xF061
+#define reg_tuner_data_783_776_pos 0
+#define reg_tuner_data_783_776_len 8
+#define reg_tuner_data_783_776_lsb 776
+#define    p_reg_tuner_data_791_784 0xF062
+#define reg_tuner_data_791_784_pos 0
+#define reg_tuner_data_791_784_len 8
+#define reg_tuner_data_791_784_lsb 784
+#define    p_reg_tuner_data_799_792 0xF063
+#define reg_tuner_data_799_792_pos 0
+#define reg_tuner_data_799_792_len 8
+#define reg_tuner_data_799_792_lsb 792
+#define    p_reg_tuner_data_807_800 0xF064
+#define reg_tuner_data_807_800_pos 0
+#define reg_tuner_data_807_800_len 8
+#define reg_tuner_data_807_800_lsb 800
+#define    p_reg_tuner_data_815_808 0xF065
+#define reg_tuner_data_815_808_pos 0
+#define reg_tuner_data_815_808_len 8
+#define reg_tuner_data_815_808_lsb 808
+#define    p_reg_tuner_data_823_816 0xF066
+#define reg_tuner_data_823_816_pos 0
+#define reg_tuner_data_823_816_len 8
+#define reg_tuner_data_823_816_lsb 816
+#define    p_reg_tuner_data_831_824 0xF067
+#define reg_tuner_data_831_824_pos 0
+#define reg_tuner_data_831_824_len 8
+#define reg_tuner_data_831_824_lsb 824
+#define    p_reg_tuner_data_839_832 0xF068
+#define reg_tuner_data_839_832_pos 0
+#define reg_tuner_data_839_832_len 8
+#define reg_tuner_data_839_832_lsb 832
+#define    p_reg_tuner_data_847_840 0xF069
+#define reg_tuner_data_847_840_pos 0
+#define reg_tuner_data_847_840_len 8
+#define reg_tuner_data_847_840_lsb 840
+#define    p_reg_tuner_data_855_848 0xF06A
+#define reg_tuner_data_855_848_pos 0
+#define reg_tuner_data_855_848_len 8
+#define reg_tuner_data_855_848_lsb 848
+#define    p_reg_tuner_data_863_856 0xF06B
+#define reg_tuner_data_863_856_pos 0
+#define reg_tuner_data_863_856_len 8
+#define reg_tuner_data_863_856_lsb 856
+#define    p_reg_tuner_data_871_864 0xF06C
+#define reg_tuner_data_871_864_pos 0
+#define reg_tuner_data_871_864_len 8
+#define reg_tuner_data_871_864_lsb 864
+#define    p_reg_tuner_data_879_872 0xF06D
+#define reg_tuner_data_879_872_pos 0
+#define reg_tuner_data_879_872_len 8
+#define reg_tuner_data_879_872_lsb 872
+#define    p_reg_tuner_data_887_880 0xF06E
+#define reg_tuner_data_887_880_pos 0
+#define reg_tuner_data_887_880_len 8
+#define reg_tuner_data_887_880_lsb 880
+#define    p_reg_tuner_data_895_888 0xF06F
+#define reg_tuner_data_895_888_pos 0
+#define reg_tuner_data_895_888_len 8
+#define reg_tuner_data_895_888_lsb 888
+#define    p_reg_tuner_data_903_896 0xF070
+#define reg_tuner_data_903_896_pos 0
+#define reg_tuner_data_903_896_len 8
+#define reg_tuner_data_903_896_lsb 896
+#define    p_reg_tuner_data_911_904 0xF071
+#define reg_tuner_data_911_904_pos 0
+#define reg_tuner_data_911_904_len 8
+#define reg_tuner_data_911_904_lsb 904
+#define    p_reg_tuner_data_919_912 0xF072
+#define reg_tuner_data_919_912_pos 0
+#define reg_tuner_data_919_912_len 8
+#define reg_tuner_data_919_912_lsb 912
+#define    p_reg_tuner_data_927_920 0xF073
+#define reg_tuner_data_927_920_pos 0
+#define reg_tuner_data_927_920_len 8
+#define reg_tuner_data_927_920_lsb 920
+#define    p_reg_tuner_data_935_928 0xF074
+#define reg_tuner_data_935_928_pos 0
+#define reg_tuner_data_935_928_len 8
+#define reg_tuner_data_935_928_lsb 928
+#define    p_reg_tuner_data_943_936 0xF075
+#define reg_tuner_data_943_936_pos 0
+#define reg_tuner_data_943_936_len 8
+#define reg_tuner_data_943_936_lsb 936
+#define    p_reg_tuner_data_951_944 0xF076
+#define reg_tuner_data_951_944_pos 0
+#define reg_tuner_data_951_944_len 8
+#define reg_tuner_data_951_944_lsb 944
+#define    p_reg_tuner_data_959_952 0xF077
+#define reg_tuner_data_959_952_pos 0
+#define reg_tuner_data_959_952_len 8
+#define reg_tuner_data_959_952_lsb 952
+#define    p_reg_tuner_data_967_960 0xF078
+#define reg_tuner_data_967_960_pos 0
+#define reg_tuner_data_967_960_len 8
+#define reg_tuner_data_967_960_lsb 960
+#define    p_reg_tuner_data_975_968 0xF079
+#define reg_tuner_data_975_968_pos 0
+#define reg_tuner_data_975_968_len 8
+#define reg_tuner_data_975_968_lsb 968
+#define    p_reg_tuner_data_983_976 0xF07A
+#define reg_tuner_data_983_976_pos 0
+#define reg_tuner_data_983_976_len 8
+#define reg_tuner_data_983_976_lsb 976
+#define    p_reg_tuner_data_991_984 0xF07B
+#define reg_tuner_data_991_984_pos 0
+#define reg_tuner_data_991_984_len 8
+#define reg_tuner_data_991_984_lsb 984
+#define    p_reg_tuner_data_999_992 0xF07C
+#define reg_tuner_data_999_992_pos 0
+#define reg_tuner_data_999_992_len 8
+#define reg_tuner_data_999_992_lsb 992
+#define    p_reg_tuner_data_1007_1000   0xF07D
+#define reg_tuner_data_1007_1000_pos 0
+#define reg_tuner_data_1007_1000_len 8
+#define reg_tuner_data_1007_1000_lsb 1000
+#define    p_reg_tuner_data_1015_1008   0xF07E
+#define reg_tuner_data_1015_1008_pos 0
+#define reg_tuner_data_1015_1008_len 8
+#define reg_tuner_data_1015_1008_lsb 1008
+#define    p_reg_tuner_data_1023_1016   0xF07F
+#define reg_tuner_data_1023_1016_pos 0
+#define reg_tuner_data_1023_1016_len 8
+#define reg_tuner_data_1023_1016_lsb 1016
+#define    p_reg_tuner_data_1031_1024   0xF080
+#define reg_tuner_data_1031_1024_pos 0
+#define reg_tuner_data_1031_1024_len 8
+#define reg_tuner_data_1031_1024_lsb 1024
+#define    p_reg_tuner_data_1039_1032   0xF081
+#define reg_tuner_data_1039_1032_pos 0
+#define reg_tuner_data_1039_1032_len 8
+#define reg_tuner_data_1039_1032_lsb 1032
+#define    p_reg_tuner_data_1047_1040   0xF082
+#define reg_tuner_data_1047_1040_pos 0
+#define reg_tuner_data_1047_1040_len 8
+#define reg_tuner_data_1047_1040_lsb 1040
+#define    p_reg_tuner_data_1055_1048   0xF083
+#define reg_tuner_data_1055_1048_pos 0
+#define reg_tuner_data_1055_1048_len 8
+#define reg_tuner_data_1055_1048_lsb 1048
+#define    p_reg_tuner_data_1063_1056   0xF084
+#define reg_tuner_data_1063_1056_pos 0
+#define reg_tuner_data_1063_1056_len 8
+#define reg_tuner_data_1063_1056_lsb 1056
+#define    p_reg_tuner_data_1071_1064   0xF085
+#define reg_tuner_data_1071_1064_pos 0
+#define reg_tuner_data_1071_1064_len 8
+#define reg_tuner_data_1071_1064_lsb 1064
+#define    p_reg_tuner_data_1079_1072   0xF086
+#define reg_tuner_data_1079_1072_pos 0
+#define reg_tuner_data_1079_1072_len 8
+#define reg_tuner_data_1079_1072_lsb 1072
+#define    p_reg_tuner_data_1087_1080   0xF087
+#define reg_tuner_data_1087_1080_pos 0
+#define reg_tuner_data_1087_1080_len 8
+#define reg_tuner_data_1087_1080_lsb 1080
+#define    p_reg_tuner_data_1095_1088   0xF088
+#define reg_tuner_data_1095_1088_pos 0
+#define reg_tuner_data_1095_1088_len 8
+#define reg_tuner_data_1095_1088_lsb 1088
+#define    p_reg_tuner_data_1103_1096   0xF089
+#define reg_tuner_data_1103_1096_pos 0
+#define reg_tuner_data_1103_1096_len 8
+#define reg_tuner_data_1103_1096_lsb 1096
+#define    p_reg_tuner_data_1111_1104   0xF08A
+#define reg_tuner_data_1111_1104_pos 0
+#define reg_tuner_data_1111_1104_len 8
+#define reg_tuner_data_1111_1104_lsb 1104
+#define    p_reg_tuner_data_1119_1112   0xF08B
+#define reg_tuner_data_1119_1112_pos 0
+#define reg_tuner_data_1119_1112_len 8
+#define reg_tuner_data_1119_1112_lsb 1112
+#define    p_reg_tuner_data_1127_1120   0xF08C
+#define reg_tuner_data_1127_1120_pos 0
+#define reg_tuner_data_1127_1120_len 8
+#define reg_tuner_data_1127_1120_lsb 1120
+#define    p_reg_tuner_data_1135_1128   0xF08D
+#define reg_tuner_data_1135_1128_pos 0
+#define reg_tuner_data_1135_1128_len 8
+#define reg_tuner_data_1135_1128_lsb 1128
+#define    p_reg_tuner_data_1143_1136   0xF08E
+#define reg_tuner_data_1143_1136_pos 0
+#define reg_tuner_data_1143_1136_len 8
+#define reg_tuner_data_1143_1136_lsb 1136
+#define    p_reg_tuner_data_1151_1144   0xF08F
+#define reg_tuner_data_1151_1144_pos 0
+#define reg_tuner_data_1151_1144_len 8
+#define reg_tuner_data_1151_1144_lsb 1144
+#define    p_reg_tuner_data_1159_1152   0xF090
+#define reg_tuner_data_1159_1152_pos 0
+#define reg_tuner_data_1159_1152_len 8
+#define reg_tuner_data_1159_1152_lsb 1152
+#define    p_reg_tuner_data_1167_1160   0xF091
+#define reg_tuner_data_1167_1160_pos 0
+#define reg_tuner_data_1167_1160_len 8
+#define reg_tuner_data_1167_1160_lsb 1160
+#define    p_reg_tuner_data_1175_1168   0xF092
+#define reg_tuner_data_1175_1168_pos 0
+#define reg_tuner_data_1175_1168_len 8
+#define reg_tuner_data_1175_1168_lsb 1168
+#define    p_reg_tuner_data_1183_1176   0xF093
+#define reg_tuner_data_1183_1176_pos 0
+#define reg_tuner_data_1183_1176_len 8
+#define reg_tuner_data_1183_1176_lsb 1176
+#define    p_reg_tuner_data_1191_1184   0xF094
+#define reg_tuner_data_1191_1184_pos 0
+#define reg_tuner_data_1191_1184_len 8
+#define reg_tuner_data_1191_1184_lsb 1184
+#define    p_reg_tuner_data_1199_1192   0xF095
+#define reg_tuner_data_1199_1192_pos 0
+#define reg_tuner_data_1199_1192_len 8
+#define reg_tuner_data_1199_1192_lsb 1192
+#define    p_reg_tuner_data_1207_1200   0xF096
+#define reg_tuner_data_1207_1200_pos 0
+#define reg_tuner_data_1207_1200_len 8
+#define reg_tuner_data_1207_1200_lsb 1200
+#define    p_reg_tuner_data_1215_1208   0xF097
+#define reg_tuner_data_1215_1208_pos 0
+#define reg_tuner_data_1215_1208_len 8
+#define reg_tuner_data_1215_1208_lsb 1208
+#define    p_reg_tuner_data_1223_1216   0xF098
+#define reg_tuner_data_1223_1216_pos 0
+#define reg_tuner_data_1223_1216_len 8
+#define reg_tuner_data_1223_1216_lsb 1216
+#define    p_reg_tuner_data_1231_1224   0xF099
+#define reg_tuner_data_1231_1224_pos 0
+#define reg_tuner_data_1231_1224_len 8
+#define reg_tuner_data_1231_1224_lsb 1224
+#define    p_reg_tuner_data_1239_1232   0xF09A
+#define reg_tuner_data_1239_1232_pos 0
+#define reg_tuner_data_1239_1232_len 8
+#define reg_tuner_data_1239_1232_lsb 1232
+#define    p_reg_tuner_data_1247_1240   0xF09B
+#define reg_tuner_data_1247_1240_pos 0
+#define reg_tuner_data_1247_1240_len 8
+#define reg_tuner_data_1247_1240_lsb 1240
+#define    p_reg_tuner_data_1255_1248   0xF09C
+#define reg_tuner_data_1255_1248_pos 0
+#define reg_tuner_data_1255_1248_len 8
+#define reg_tuner_data_1255_1248_lsb 1248
+#define    p_reg_tuner_data_1263_1256   0xF09D
+#define reg_tuner_data_1263_1256_pos 0
+#define reg_tuner_data_1263_1256_len 8
+#define reg_tuner_data_1263_1256_lsb 1256
+#define    p_reg_tuner_data_1271_1264   0xF09E
+#define reg_tuner_data_1271_1264_pos 0
+#define reg_tuner_data_1271_1264_len 8
+#define reg_tuner_data_1271_1264_lsb 1264
+#define    p_reg_tuner_data_1279_1272   0xF09F
+#define reg_tuner_data_1279_1272_pos 0
+#define reg_tuner_data_1279_1272_len 8
+#define reg_tuner_data_1279_1272_lsb 1272
+#define    p_reg_tuner_data_1287_1280   0xF0A0
+#define reg_tuner_data_1287_1280_pos 0
+#define reg_tuner_data_1287_1280_len 8
+#define reg_tuner_data_1287_1280_lsb 1280
+#define    p_reg_tuner_data_1295_1288   0xF0A1
+#define reg_tuner_data_1295_1288_pos 0
+#define reg_tuner_data_1295_1288_len 8
+#define reg_tuner_data_1295_1288_lsb 1288
+#define    p_reg_tuner_data_1303_1296   0xF0A2
+#define reg_tuner_data_1303_1296_pos 0
+#define reg_tuner_data_1303_1296_len 8
+#define reg_tuner_data_1303_1296_lsb 1296
+#define    p_reg_tuner_data_1311_1304   0xF0A3
+#define reg_tuner_data_1311_1304_pos 0
+#define reg_tuner_data_1311_1304_len 8
+#define reg_tuner_data_1311_1304_lsb 1304
+#define    p_reg_tuner_data_1319_1312   0xF0A4
+#define reg_tuner_data_1319_1312_pos 0
+#define reg_tuner_data_1319_1312_len 8
+#define reg_tuner_data_1319_1312_lsb 1312
+#define    p_reg_tuner_data_1327_1320   0xF0A5
+#define reg_tuner_data_1327_1320_pos 0
+#define reg_tuner_data_1327_1320_len 8
+#define reg_tuner_data_1327_1320_lsb 1320
+#define    p_reg_tuner_data_1335_1328   0xF0A6
+#define reg_tuner_data_1335_1328_pos 0
+#define reg_tuner_data_1335_1328_len 8
+#define reg_tuner_data_1335_1328_lsb 1328
+#define    p_reg_tuner_data_1343_1336   0xF0A7
+#define reg_tuner_data_1343_1336_pos 0
+#define reg_tuner_data_1343_1336_len 8
+#define reg_tuner_data_1343_1336_lsb 1336
+#define    p_reg_tuner_data_1351_1344   0xF0A8
+#define reg_tuner_data_1351_1344_pos 0
+#define reg_tuner_data_1351_1344_len 8
+#define reg_tuner_data_1351_1344_lsb 1344
+#define    p_reg_tuner_data_1359_1352   0xF0A9
+#define reg_tuner_data_1359_1352_pos 0
+#define reg_tuner_data_1359_1352_len 8
+#define reg_tuner_data_1359_1352_lsb 1352
+#define    p_reg_tuner_data_1367_1360   0xF0AA
+#define reg_tuner_data_1367_1360_pos 0
+#define reg_tuner_data_1367_1360_len 8
+#define reg_tuner_data_1367_1360_lsb 1360
+#define    p_reg_tuner_data_1375_1368   0xF0AB
+#define reg_tuner_data_1375_1368_pos 0
+#define reg_tuner_data_1375_1368_len 8
+#define reg_tuner_data_1375_1368_lsb 1368
+#define    p_reg_tuner_data_1383_1376   0xF0AC
+#define reg_tuner_data_1383_1376_pos 0
+#define reg_tuner_data_1383_1376_len 8
+#define reg_tuner_data_1383_1376_lsb 1376
+#define    p_reg_tuner_data_1391_1384   0xF0AD
+#define reg_tuner_data_1391_1384_pos 0
+#define reg_tuner_data_1391_1384_len 8
+#define reg_tuner_data_1391_1384_lsb 1384
+#define    p_reg_tuner_data_1399_1392   0xF0AE
+#define reg_tuner_data_1399_1392_pos 0
+#define reg_tuner_data_1399_1392_len 8
+#define reg_tuner_data_1399_1392_lsb 1392
+#define    p_reg_tuner_data_1407_1400   0xF0AF
+#define reg_tuner_data_1407_1400_pos 0
+#define reg_tuner_data_1407_1400_len 8
+#define reg_tuner_data_1407_1400_lsb 1400
+#define    p_reg_tuner_data_1415_1408   0xF0B0
+#define reg_tuner_data_1415_1408_pos 0
+#define reg_tuner_data_1415_1408_len 8
+#define reg_tuner_data_1415_1408_lsb 1408
+#define    p_reg_tuner_data_1423_1416   0xF0B1
+#define reg_tuner_data_1423_1416_pos 0
+#define reg_tuner_data_1423_1416_len 8
+#define reg_tuner_data_1423_1416_lsb 1416
+#define    p_reg_tuner_data_1431_1424   0xF0B2
+#define reg_tuner_data_1431_1424_pos 0
+#define reg_tuner_data_1431_1424_len 8
+#define reg_tuner_data_1431_1424_lsb 1424
+#define    p_reg_tuner_data_1439_1432   0xF0B3
+#define reg_tuner_data_1439_1432_pos 0
+#define reg_tuner_data_1439_1432_len 8
+#define reg_tuner_data_1439_1432_lsb 1432
+#define    p_reg_tuner_data_1447_1440   0xF0B4
+#define reg_tuner_data_1447_1440_pos 0
+#define reg_tuner_data_1447_1440_len 8
+#define reg_tuner_data_1447_1440_lsb 1440
+#define    p_reg_tuner_data_1455_1448   0xF0B5
+#define reg_tuner_data_1455_1448_pos 0
+#define reg_tuner_data_1455_1448_len 8
+#define reg_tuner_data_1455_1448_lsb 1448
+#define    p_reg_tuner_data_1463_1456   0xF0B6
+#define reg_tuner_data_1463_1456_pos 0
+#define reg_tuner_data_1463_1456_len 8
+#define reg_tuner_data_1463_1456_lsb 1456
+#define    p_reg_tuner_data_1471_1464   0xF0B7
+#define reg_tuner_data_1471_1464_pos 0
+#define reg_tuner_data_1471_1464_len 8
+#define reg_tuner_data_1471_1464_lsb 1464
+#define    p_reg_tuner_data_1479_1472   0xF0B8
+#define reg_tuner_data_1479_1472_pos 0
+#define reg_tuner_data_1479_1472_len 8
+#define reg_tuner_data_1479_1472_lsb 1472
+#define    p_reg_tuner_data_1487_1480   0xF0B9
+#define reg_tuner_data_1487_1480_pos 0
+#define reg_tuner_data_1487_1480_len 8
+#define reg_tuner_data_1487_1480_lsb 1480
+#define    p_reg_tuner_data_1495_1488   0xF0BA
+#define reg_tuner_data_1495_1488_pos 0
+#define reg_tuner_data_1495_1488_len 8
+#define reg_tuner_data_1495_1488_lsb 1488
+#define    p_reg_tuner_data_1503_1496   0xF0BB
+#define reg_tuner_data_1503_1496_pos 0
+#define reg_tuner_data_1503_1496_len 8
+#define reg_tuner_data_1503_1496_lsb 1496
+#define    p_reg_tuner_data_1511_1504   0xF0BC
+#define reg_tuner_data_1511_1504_pos 0
+#define reg_tuner_data_1511_1504_len 8
+#define reg_tuner_data_1511_1504_lsb 1504
+#define    p_reg_tuner_data_1519_1512   0xF0BD
+#define reg_tuner_data_1519_1512_pos 0
+#define reg_tuner_data_1519_1512_len 8
+#define reg_tuner_data_1519_1512_lsb 1512
+#define    p_reg_tuner_data_1527_1520   0xF0BE
+#define reg_tuner_data_1527_1520_pos 0
+#define reg_tuner_data_1527_1520_len 8
+#define reg_tuner_data_1527_1520_lsb 1520
+#define    p_reg_tuner_data_1535_1528   0xF0BF
+#define reg_tuner_data_1535_1528_pos 0
+#define reg_tuner_data_1535_1528_len 8
+#define reg_tuner_data_1535_1528_lsb 1528
+#define    p_reg_tuner_data_1543_1536   0xF0C0
+#define reg_tuner_data_1543_1536_pos 0
+#define reg_tuner_data_1543_1536_len 8
+#define reg_tuner_data_1543_1536_lsb 1536
+#define    p_reg_tuner_data_1551_1544   0xF0C1
+#define reg_tuner_data_1551_1544_pos 0
+#define reg_tuner_data_1551_1544_len 8
+#define reg_tuner_data_1551_1544_lsb 1544
+#define    p_reg_tuner_data_1559_1552   0xF0C2
+#define reg_tuner_data_1559_1552_pos 0
+#define reg_tuner_data_1559_1552_len 8
+#define reg_tuner_data_1559_1552_lsb 1552
+#define    p_reg_tuner_data_1567_1560   0xF0C3
+#define reg_tuner_data_1567_1560_pos 0
+#define reg_tuner_data_1567_1560_len 8
+#define reg_tuner_data_1567_1560_lsb 1560
+#define    p_reg_tuner_data_1575_1568   0xF0C4
+#define reg_tuner_data_1575_1568_pos 0
+#define reg_tuner_data_1575_1568_len 8
+#define reg_tuner_data_1575_1568_lsb 1568
+#define    p_reg_tuner_data_1583_1576   0xF0C5
+#define reg_tuner_data_1583_1576_pos 0
+#define reg_tuner_data_1583_1576_len 8
+#define reg_tuner_data_1583_1576_lsb 1576
+#define    p_reg_tuner_data_1591_1584   0xF0C6
+#define reg_tuner_data_1591_1584_pos 0
+#define reg_tuner_data_1591_1584_len 8
+#define reg_tuner_data_1591_1584_lsb 1584
+#define    p_reg_tuner_data_1599_1592   0xF0C7
+#define reg_tuner_data_1599_1592_pos 0
+#define reg_tuner_data_1599_1592_len 8
+#define reg_tuner_data_1599_1592_lsb 1592
+#define    p_reg_tuner_data_1607_1600   0xF0C8
+#define reg_tuner_data_1607_1600_pos 0
+#define reg_tuner_data_1607_1600_len 8
+#define reg_tuner_data_1607_1600_lsb 1600
+#define    p_reg_tuner_data_1615_1608   0xF0C9
+#define reg_tuner_data_1615_1608_pos 0
+#define reg_tuner_data_1615_1608_len 8
+#define reg_tuner_data_1615_1608_lsb 1608
+#define    p_reg_tuner_data_1623_1616   0xF0CA
+#define reg_tuner_data_1623_1616_pos 0
+#define reg_tuner_data_1623_1616_len 8
+#define reg_tuner_data_1623_1616_lsb 1616
+#define    p_reg_tuner_data_1631_1624   0xF0CB
+#define reg_tuner_data_1631_1624_pos 0
+#define reg_tuner_data_1631_1624_len 8
+#define reg_tuner_data_1631_1624_lsb 1624
+#define    p_reg_tuner_data_1639_1632   0xF0CC
+#define reg_tuner_data_1639_1632_pos 0
+#define reg_tuner_data_1639_1632_len 8
+#define reg_tuner_data_1639_1632_lsb 1632
+#define    p_reg_tuner_data_1647_1640   0xF0CD
+#define reg_tuner_data_1647_1640_pos 0
+#define reg_tuner_data_1647_1640_len 8
+#define reg_tuner_data_1647_1640_lsb 1640
+#define    p_reg_tuner_data_1655_1648   0xF0CE
+#define reg_tuner_data_1655_1648_pos 0
+#define reg_tuner_data_1655_1648_len 8
+#define reg_tuner_data_1655_1648_lsb 1648
+#define    p_reg_tuner_data_1663_1656   0xF0CF
+#define reg_tuner_data_1663_1656_pos 0
+#define reg_tuner_data_1663_1656_len 8
+#define reg_tuner_data_1663_1656_lsb 1656
+#define    p_reg_tuner_data_1671_1664   0xF0D0
+#define reg_tuner_data_1671_1664_pos 0
+#define reg_tuner_data_1671_1664_len 8
+#define reg_tuner_data_1671_1664_lsb 1664
+#define    p_reg_tuner_data_1679_1672   0xF0D1
+#define reg_tuner_data_1679_1672_pos 0
+#define reg_tuner_data_1679_1672_len 8
+#define reg_tuner_data_1679_1672_lsb 1672
+#define    p_reg_tuner_data_1687_1680   0xF0D2
+#define reg_tuner_data_1687_1680_pos 0
+#define reg_tuner_data_1687_1680_len 8
+#define reg_tuner_data_1687_1680_lsb 1680
+#define    p_reg_tuner_data_1695_1688   0xF0D3
+#define reg_tuner_data_1695_1688_pos 0
+#define reg_tuner_data_1695_1688_len 8
+#define reg_tuner_data_1695_1688_lsb 1688
+#define    p_reg_tuner_data_1703_1696   0xF0D4
+#define reg_tuner_data_1703_1696_pos 0
+#define reg_tuner_data_1703_1696_len 8
+#define reg_tuner_data_1703_1696_lsb 1696
+#define    p_reg_tuner_data_1711_1704   0xF0D5
+#define reg_tuner_data_1711_1704_pos 0
+#define reg_tuner_data_1711_1704_len 8
+#define reg_tuner_data_1711_1704_lsb 1704
+#define    p_reg_tuner_data_1719_1712   0xF0D6
+#define reg_tuner_data_1719_1712_pos 0
+#define reg_tuner_data_1719_1712_len 8
+#define reg_tuner_data_1719_1712_lsb 1712
+#define    p_reg_tuner_data_1727_1720   0xF0D7
+#define reg_tuner_data_1727_1720_pos 0
+#define reg_tuner_data_1727_1720_len 8
+#define reg_tuner_data_1727_1720_lsb 1720
+#define    p_reg_tuner_data_1735_1728   0xF0D8
+#define reg_tuner_data_1735_1728_pos 0
+#define reg_tuner_data_1735_1728_len 8
+#define reg_tuner_data_1735_1728_lsb 1728
+#define    p_reg_tuner_data_1743_1736   0xF0D9
+#define reg_tuner_data_1743_1736_pos 0
+#define reg_tuner_data_1743_1736_len 8
+#define reg_tuner_data_1743_1736_lsb 1736
+#define    p_reg_tuner_data_1751_1744   0xF0DA
+#define reg_tuner_data_1751_1744_pos 0
+#define reg_tuner_data_1751_1744_len 8
+#define reg_tuner_data_1751_1744_lsb 1744
+#define    p_reg_tuner_data_1759_1752   0xF0DB
+#define reg_tuner_data_1759_1752_pos 0
+#define reg_tuner_data_1759_1752_len 8
+#define reg_tuner_data_1759_1752_lsb 1752
+#define    p_reg_tuner_data_1767_1760   0xF0DC
+#define reg_tuner_data_1767_1760_pos 0
+#define reg_tuner_data_1767_1760_len 8
+#define reg_tuner_data_1767_1760_lsb 1760
+#define    p_reg_tuner_data_1775_1768   0xF0DD
+#define reg_tuner_data_1775_1768_pos 0
+#define reg_tuner_data_1775_1768_len 8
+#define reg_tuner_data_1775_1768_lsb 1768
+#define    p_reg_tuner_data_1783_1776   0xF0DE
+#define reg_tuner_data_1783_1776_pos 0
+#define reg_tuner_data_1783_1776_len 8
+#define reg_tuner_data_1783_1776_lsb 1776
+#define    p_reg_tuner_data_1791_1784   0xF0DF
+#define reg_tuner_data_1791_1784_pos 0
+#define reg_tuner_data_1791_1784_len 8
+#define reg_tuner_data_1791_1784_lsb 1784
+#define    p_reg_tuner_data_1799_1792   0xF0E0
+#define reg_tuner_data_1799_1792_pos 0
+#define reg_tuner_data_1799_1792_len 8
+#define reg_tuner_data_1799_1792_lsb 1792
+#define    p_reg_tuner_data_1807_1800   0xF0E1
+#define reg_tuner_data_1807_1800_pos 0
+#define reg_tuner_data_1807_1800_len 8
+#define reg_tuner_data_1807_1800_lsb 1800
+#define    p_reg_tuner_data_1815_1808   0xF0E2
+#define reg_tuner_data_1815_1808_pos 0
+#define reg_tuner_data_1815_1808_len 8
+#define reg_tuner_data_1815_1808_lsb 1808
+#define    p_reg_tuner_data_1823_1816   0xF0E3
+#define reg_tuner_data_1823_1816_pos 0
+#define reg_tuner_data_1823_1816_len 8
+#define reg_tuner_data_1823_1816_lsb 1816
+#define    p_reg_tuner_data_1831_1824   0xF0E4
+#define reg_tuner_data_1831_1824_pos 0
+#define reg_tuner_data_1831_1824_len 8
+#define reg_tuner_data_1831_1824_lsb 1824
+#define    p_reg_tuner_data_1839_1832   0xF0E5
+#define reg_tuner_data_1839_1832_pos 0
+#define reg_tuner_data_1839_1832_len 8
+#define reg_tuner_data_1839_1832_lsb 1832
+#define    p_reg_tuner_data_1847_1840   0xF0E6
+#define reg_tuner_data_1847_1840_pos 0
+#define reg_tuner_data_1847_1840_len 8
+#define reg_tuner_data_1847_1840_lsb 1840
+#define    p_reg_tuner_data_1855_1848   0xF0E7
+#define reg_tuner_data_1855_1848_pos 0
+#define reg_tuner_data_1855_1848_len 8
+#define reg_tuner_data_1855_1848_lsb 1848
+#define    p_reg_tuner_data_1863_1856   0xF0E8
+#define reg_tuner_data_1863_1856_pos 0
+#define reg_tuner_data_1863_1856_len 8
+#define reg_tuner_data_1863_1856_lsb 1856
+#define    p_reg_tuner_data_1871_1864   0xF0E9
+#define reg_tuner_data_1871_1864_pos 0
+#define reg_tuner_data_1871_1864_len 8
+#define reg_tuner_data_1871_1864_lsb 1864
+#define    p_reg_tuner_data_1879_1872   0xF0EA
+#define reg_tuner_data_1879_1872_pos 0
+#define reg_tuner_data_1879_1872_len 8
+#define reg_tuner_data_1879_1872_lsb 1872
+#define    p_reg_tuner_data_1887_1880   0xF0EB
+#define reg_tuner_data_1887_1880_pos 0
+#define reg_tuner_data_1887_1880_len 8
+#define reg_tuner_data_1887_1880_lsb 1880
+#define    p_reg_tuner_data_1895_1888   0xF0EC
+#define reg_tuner_data_1895_1888_pos 0
+#define reg_tuner_data_1895_1888_len 8
+#define reg_tuner_data_1895_1888_lsb 1888
+#define    p_reg_tuner_data_1903_1896   0xF0ED
+#define reg_tuner_data_1903_1896_pos 0
+#define reg_tuner_data_1903_1896_len 8
+#define reg_tuner_data_1903_1896_lsb 1896
+#define    p_reg_tuner_data_1911_1904   0xF0EE
+#define reg_tuner_data_1911_1904_pos 0
+#define reg_tuner_data_1911_1904_len 8
+#define reg_tuner_data_1911_1904_lsb 1904
+#define    p_reg_tuner_data_1919_1912   0xF0EF
+#define reg_tuner_data_1919_1912_pos 0
+#define reg_tuner_data_1919_1912_len 8
+#define reg_tuner_data_1919_1912_lsb 1912
+#define    p_reg_tuner_data_1927_1920   0xF0F0
+#define reg_tuner_data_1927_1920_pos 0
+#define reg_tuner_data_1927_1920_len 8
+#define reg_tuner_data_1927_1920_lsb 1920
+#define    p_reg_tuner_data_1935_1928   0xF0F1
+#define reg_tuner_data_1935_1928_pos 0
+#define reg_tuner_data_1935_1928_len 8
+#define reg_tuner_data_1935_1928_lsb 1928
+#define    p_reg_tuner_data_1943_1936   0xF0F2
+#define reg_tuner_data_1943_1936_pos 0
+#define reg_tuner_data_1943_1936_len 8
+#define reg_tuner_data_1943_1936_lsb 1936
+#define    p_reg_tuner_data_1951_1944   0xF0F3
+#define reg_tuner_data_1951_1944_pos 0
+#define reg_tuner_data_1951_1944_len 8
+#define reg_tuner_data_1951_1944_lsb 1944
+#define    p_reg_tuner_data_1959_1952   0xF0F4
+#define reg_tuner_data_1959_1952_pos 0
+#define reg_tuner_data_1959_1952_len 8
+#define reg_tuner_data_1959_1952_lsb 1952
+#define    p_reg_tuner_data_1967_1960   0xF0F5
+#define reg_tuner_data_1967_1960_pos 0
+#define reg_tuner_data_1967_1960_len 8
+#define reg_tuner_data_1967_1960_lsb 1960
+#define    p_reg_tuner_data_1975_1968   0xF0F6
+#define reg_tuner_data_1975_1968_pos 0
+#define reg_tuner_data_1975_1968_len 8
+#define reg_tuner_data_1975_1968_lsb 1968
+#define    p_reg_tuner_data_1983_1976   0xF0F7
+#define reg_tuner_data_1983_1976_pos 0
+#define reg_tuner_data_1983_1976_len 8
+#define reg_tuner_data_1983_1976_lsb 1976
+#define    p_reg_tuner_data_1991_1984   0xF0F8
+#define reg_tuner_data_1991_1984_pos 0
+#define reg_tuner_data_1991_1984_len 8
+#define reg_tuner_data_1991_1984_lsb 1984
+#define    p_reg_tuner_data_1999_1992   0xF0F9
+#define reg_tuner_data_1999_1992_pos 0
+#define reg_tuner_data_1999_1992_len 8
+#define reg_tuner_data_1999_1992_lsb 1992
+#define    p_reg_tuner_data_2007_2000   0xF0FA
+#define reg_tuner_data_2007_2000_pos 0
+#define reg_tuner_data_2007_2000_len 8
+#define reg_tuner_data_2007_2000_lsb 2000
+#define    p_reg_tuner_data_2015_2008   0xF0FB
+#define reg_tuner_data_2015_2008_pos 0
+#define reg_tuner_data_2015_2008_len 8
+#define reg_tuner_data_2015_2008_lsb 2008
+#define    p_reg_tuner_data_2023_2016   0xF0FC
+#define reg_tuner_data_2023_2016_pos 0
+#define reg_tuner_data_2023_2016_len 8
+#define reg_tuner_data_2023_2016_lsb 2016
+#define    p_reg_tuner_data_2031_2024   0xF0FD
+#define reg_tuner_data_2031_2024_pos 0
+#define reg_tuner_data_2031_2024_len 8
+#define reg_tuner_data_2031_2024_lsb 2024
+#define    p_reg_tuner_data_2039_2032   0xF0FE
+#define reg_tuner_data_2039_2032_pos 0
+#define reg_tuner_data_2039_2032_len 8
+#define reg_tuner_data_2039_2032_lsb 2032
+#define    p_reg_tuner_data_2047_2040   0xF0FF
+#define reg_tuner_data_2047_2040_pos 0
+#define reg_tuner_data_2047_2040_len 8
+#define reg_tuner_data_2047_2040_lsb 2040
+#define    p_reg_tuner_master_rd_wr 0xF100
+#define reg_tuner_master_rd_wr_pos 0
+#define reg_tuner_master_rd_wr_len 1
+#define reg_tuner_master_rd_wr_lsb 0
+#define    p_reg_tuner_master_length    0xF101
+#define reg_tuner_master_length_pos 0
+#define reg_tuner_master_length_len 8
+#define reg_tuner_master_length_lsb 0
+#define    p_reg_tuner_cmd_exe  0xF102
+#define reg_tuner_cmd_exe_pos 0
+#define reg_tuner_cmd_exe_len 1
+#define reg_tuner_cmd_exe_lsb 0
+#define    p_reg_tuner_wdat_done    0xF102
+#define reg_tuner_wdat_done_pos 1
+#define reg_tuner_wdat_done_len 1
+#define reg_tuner_wdat_done_lsb 0
+#define    p_reg_tuner_wdat_fail    0xF102
+#define reg_tuner_wdat_fail_pos 2
+#define reg_tuner_wdat_fail_len 1
+#define reg_tuner_wdat_fail_lsb 0
+#define    p_reg_tuner_ofsm_i2cm_rdat_rdy   0xF102
+#define reg_tuner_ofsm_i2cm_rdat_rdy_pos 3
+#define reg_tuner_ofsm_i2cm_rdat_rdy_len 1
+#define reg_tuner_ofsm_i2cm_rdat_rdy_lsb 0
+#define    p_reg_tuner_current_state    0xF102
+#define reg_tuner_current_state_pos 4
+#define reg_tuner_current_state_len 3
+#define reg_tuner_current_state_lsb 0
+#define    p_reg_one_cycle_counter_tuner    0xF103
+#define reg_one_cycle_counter_tuner_pos 0
+#define reg_one_cycle_counter_tuner_len 8
+#define reg_one_cycle_counter_tuner_lsb 0
+#define    p_reg_msb_lsb    0xF104
+#define reg_msb_lsb_pos 0
+#define reg_msb_lsb_len 1
+#define reg_msb_lsb_lsb 0
+#define    p_reg_ofdm_rst   0xF104
+#define    p_reg_sel_thirdi2c   0xF104
+#define reg_sel_thirdi2c_pos 2
+#define reg_sel_thirdi2c_len 1
+#define reg_sel_thirdi2c_lsb 0
+#define    p_reg_sel_tuner  0xF104
+#define    p_reg_ofdm_rst_en    0xF104
+#define    p_reg_sdio_cccr_v    0xF140
+#define reg_sdio_cccr_v_pos 0
+#define reg_sdio_cccr_v_len 4
+#define reg_sdio_cccr_v_lsb 0
+#define    p_reg_sdio_sdio_v    0xF140
+#define reg_sdio_sdio_v_pos 4
+#define reg_sdio_sdio_v_len 4
+#define reg_sdio_sdio_v_lsb 0
+#define    p_reg_sdioc_sd_v 0xF141
+#define reg_sdioc_sd_v_pos 0
+#define reg_sdioc_sd_v_len 4
+#define reg_sdioc_sd_v_lsb 0
+#define    p_reg_sdioc_ior1 0xF143
+#define reg_sdioc_ior1_pos 1
+#define reg_sdioc_ior1_len 1
+#define reg_sdioc_ior1_lsb 0
+#define    p_reg_sdioc_int1 0xF145
+#define reg_sdioc_int1_pos 1
+#define reg_sdioc_int1_len 1
+#define reg_sdioc_int1_lsb 0
+#define    p_reg_sdioc_scsi 0xF147
+#define reg_sdioc_scsi_pos 6
+#define reg_sdioc_scsi_len 1
+#define reg_sdioc_scsi_lsb 0
+#define    p_reg_sdioc_sdc  0xF148
+#define reg_sdioc_sdc_pos 0
+#define reg_sdioc_sdc_len 1
+#define reg_sdioc_sdc_lsb 0
+#define    p_reg_sdioc_smb  0xF148
+#define reg_sdioc_smb_pos 1
+#define reg_sdioc_smb_len 1
+#define reg_sdioc_smb_lsb 0
+#define    p_reg_sdioc_srw  0xF148
+#define reg_sdioc_srw_pos 2
+#define reg_sdioc_srw_len 1
+#define reg_sdioc_srw_lsb 0
+#define    p_reg_sdioc_sbs  0xF148
+#define reg_sdioc_sbs_pos 3
+#define reg_sdioc_sbs_len 1
+#define reg_sdioc_sbs_lsb 0
+#define    p_reg_sdioc_s4mi 0xF148
+#define reg_sdioc_s4mi_pos 4
+#define reg_sdioc_s4mi_len 1
+#define reg_sdioc_s4mi_lsb 0
+#define    p_reg_sdioc_lsc  0xF148
+#define reg_sdioc_lsc_pos 6
+#define reg_sdioc_lsc_len 1
+#define reg_sdioc_lsc_lsb 0
+#define    p_reg_sdioc_4bls 0xF148
+#define reg_sdioc_4bls_pos 7
+#define reg_sdioc_4bls_len 1
+#define reg_sdioc_4bls_lsb 0
+#define    p_reg_sdioc_cis_7_0  0xF149
+#define reg_sdioc_cis_7_0_pos 0
+#define reg_sdioc_cis_7_0_len 8
+#define reg_sdioc_cis_7_0_lsb 0
+#define    p_reg_sdioc_cis_15_8 0xF14A
+#define reg_sdioc_cis_15_8_pos 0
+#define reg_sdioc_cis_15_8_len 8
+#define reg_sdioc_cis_15_8_lsb 8
+#define    p_reg_sdioc_cis_23_16    0xF14B
+#define reg_sdioc_cis_23_16_pos 0
+#define reg_sdioc_cis_23_16_len 8
+#define reg_sdioc_cis_23_16_lsb 16
+#define    p_reg_sdioc_fs   0xF14D
+#define reg_sdioc_fs_pos 0
+#define reg_sdioc_fs_len 4
+#define reg_sdioc_fs_lsb 0
+#define    p_reg_sdioc_df   0xF14D
+#define reg_sdioc_df_pos 7
+#define reg_sdioc_df_len 1
+#define reg_sdioc_df_lsb 0
+#define    p_reg_sdioc_ex1  0xF14E
+#define reg_sdioc_ex1_pos 1
+#define reg_sdioc_ex1_len 1
+#define reg_sdioc_ex1_lsb 0
+#define    p_reg_sdioc_rf1  0xF14F
+#define reg_sdioc_rf1_pos 1
+#define reg_sdioc_rf1_len 1
+#define reg_sdioc_rf1_lsb 0
+#define    p_reg_sdioc_smpc 0xF152
+#define reg_sdioc_smpc_pos 0
+#define reg_sdioc_smpc_len 1
+#define reg_sdioc_smpc_lsb 0
+#define    p_reg_sdioc_f1_code  0xF160
+#define reg_sdioc_f1_code_pos 0
+#define reg_sdioc_f1_code_len 4
+#define reg_sdioc_f1_code_lsb 0
+#define    p_reg_sdioc_scsa 0xF160
+#define reg_sdioc_scsa_pos 6
+#define reg_sdioc_scsa_len 1
+#define reg_sdioc_scsa_lsb 0
+#define    p_reg_sdioc_csa_en   0xF160
+#define reg_sdioc_csa_en_pos 7
+#define reg_sdioc_csa_en_len 1
+#define reg_sdioc_csa_en_lsb 0
+#define    p_reg_sdioc_f1_ext_code  0xF161
+#define reg_sdioc_f1_ext_code_pos 0
+#define reg_sdioc_f1_ext_code_len 8
+#define reg_sdioc_f1_ext_code_lsb 0
+#define    p_reg_sdioc_sps  0xF162
+#define reg_sdioc_sps_pos 0
+#define reg_sdioc_sps_len 1
+#define reg_sdioc_sps_lsb 0
+#define    p_reg_sdioc_func1_cis_ptr_7_0    0xF169
+#define reg_sdioc_func1_cis_ptr_7_0_pos 0
+#define reg_sdioc_func1_cis_ptr_7_0_len 8
+#define reg_sdioc_func1_cis_ptr_7_0_lsb 0
+#define    p_reg_sdioc_func1_cis_ptr_15_8   0xF16A
+#define reg_sdioc_func1_cis_ptr_15_8_pos 0
+#define reg_sdioc_func1_cis_ptr_15_8_len 8
+#define reg_sdioc_func1_cis_ptr_15_8_lsb 8
+#define    p_reg_sdioc_func1_cis_ptr_23_16  0xF16B
+#define reg_sdioc_func1_cis_ptr_23_16_pos 0
+#define reg_sdioc_func1_cis_ptr_23_16_len 8
+#define reg_sdioc_func1_cis_ptr_23_16_lsb 16
+#define    p_reg_sdio_FUNCID0_0 0xF180
+#define reg_sdio_FUNCID0_0_pos 0
+#define reg_sdio_FUNCID0_0_len 8
+#define reg_sdio_FUNCID0_0_lsb 0
+#define    p_reg_sdio_FUNCID0_1 0xF181
+#define reg_sdio_FUNCID0_1_pos 0
+#define reg_sdio_FUNCID0_1_len 8
+#define reg_sdio_FUNCID0_1_lsb 0
+#define    p_reg_sdio_FUNCID0_2 0xF182
+#define reg_sdio_FUNCID0_2_pos 0
+#define reg_sdio_FUNCID0_2_len 8
+#define reg_sdio_FUNCID0_2_lsb 0
+#define    p_reg_sdio_FUNCID0_3 0xF183
+#define reg_sdio_FUNCID0_3_pos 0
+#define reg_sdio_FUNCID0_3_len 8
+#define reg_sdio_FUNCID0_3_lsb 0
+#define    p_reg_sdio_MANFID0_0 0xF184
+#define reg_sdio_MANFID0_0_pos 0
+#define reg_sdio_MANFID0_0_len 8
+#define reg_sdio_MANFID0_0_lsb 0
+#define    p_reg_sdio_MANFID0_1 0xF185
+#define reg_sdio_MANFID0_1_pos 0
+#define reg_sdio_MANFID0_1_len 8
+#define reg_sdio_MANFID0_1_lsb 0
+#define    p_reg_sdio_MANFID0_2_7_0 0xF186
+#define reg_sdio_MANFID0_2_7_0_pos 0
+#define reg_sdio_MANFID0_2_7_0_len 8
+#define reg_sdio_MANFID0_2_7_0_lsb 0
+#define    p_reg_sdio_MANFID0_2_15_8    0xF187
+#define reg_sdio_MANFID0_2_15_8_pos 0
+#define reg_sdio_MANFID0_2_15_8_len 8
+#define reg_sdio_MANFID0_2_15_8_lsb 8
+#define    p_reg_sdio_MANFID0_4_7_0 0xF188
+#define reg_sdio_MANFID0_4_7_0_pos 0
+#define reg_sdio_MANFID0_4_7_0_len 8
+#define reg_sdio_MANFID0_4_7_0_lsb 0
+#define    p_reg_sdio_MANFID0_4_15_8    0xF189
+#define reg_sdio_MANFID0_4_15_8_pos 0
+#define reg_sdio_MANFID0_4_15_8_len 8
+#define reg_sdio_MANFID0_4_15_8_lsb 8
+#define    p_reg_sdio_FUNCE0_0  0xF18A
+#define reg_sdio_FUNCE0_0_pos 0
+#define reg_sdio_FUNCE0_0_len 8
+#define reg_sdio_FUNCE0_0_lsb 0
+#define    p_reg_sdio_FUNCE0_1  0xF18B
+#define reg_sdio_FUNCE0_1_pos 0
+#define reg_sdio_FUNCE0_1_len 8
+#define reg_sdio_FUNCE0_1_lsb 0
+#define    p_reg_sdio_FUNCE0_2  0xF18C
+#define reg_sdio_FUNCE0_2_pos 0
+#define reg_sdio_FUNCE0_2_len 8
+#define reg_sdio_FUNCE0_2_lsb 0
+#define    p_reg_sdio_FUNCE0_3_7_0  0xF18D
+#define reg_sdio_FUNCE0_3_7_0_pos 0
+#define reg_sdio_FUNCE0_3_7_0_len 8
+#define reg_sdio_FUNCE0_3_7_0_lsb 0
+#define    p_reg_sdio_FUNCE0_3_15_8 0xF18E
+#define reg_sdio_FUNCE0_3_15_8_pos 0
+#define reg_sdio_FUNCE0_3_15_8_len 8
+#define reg_sdio_FUNCE0_3_15_8_lsb 8
+#define    p_reg_sdio_FUNCE0_5  0xF18F
+#define reg_sdio_FUNCE0_5_pos 0
+#define reg_sdio_FUNCE0_5_len 8
+#define reg_sdio_FUNCE0_5_lsb 0
+#define    p_reg_sdio_VERS_10_0 0xF190
+#define reg_sdio_VERS_10_0_pos 0
+#define reg_sdio_VERS_10_0_len 8
+#define reg_sdio_VERS_10_0_lsb 0
+#define    p_reg_sdio_VERS_10_1 0xF191
+#define reg_sdio_VERS_10_1_pos 0
+#define reg_sdio_VERS_10_1_len 8
+#define reg_sdio_VERS_10_1_lsb 0
+#define    p_reg_sdio_VERS_10_2 0xF192
+#define reg_sdio_VERS_10_2_pos 0
+#define reg_sdio_VERS_10_2_len 8
+#define reg_sdio_VERS_10_2_lsb 0
+#define    p_reg_sdio_VERS_10_3 0xF193
+#define reg_sdio_VERS_10_3_pos 0
+#define reg_sdio_VERS_10_3_len 8
+#define reg_sdio_VERS_10_3_lsb 0
+#define    p_reg_sdio_VERS_10_4 0xF194
+#define reg_sdio_VERS_10_4_pos 0
+#define reg_sdio_VERS_10_4_len 8
+#define reg_sdio_VERS_10_4_lsb 0
+#define    p_reg_sdio_VERS_10_5 0xF195
+#define reg_sdio_VERS_10_5_pos 0
+#define reg_sdio_VERS_10_5_len 8
+#define reg_sdio_VERS_10_5_lsb 0
+#define    p_reg_sdio_VERS_10_6 0xF196
+#define reg_sdio_VERS_10_6_pos 0
+#define reg_sdio_VERS_10_6_len 8
+#define reg_sdio_VERS_10_6_lsb 0
+#define    p_reg_sdio_VERS_10_7 0xF197
+#define reg_sdio_VERS_10_7_pos 0
+#define reg_sdio_VERS_10_7_len 8
+#define reg_sdio_VERS_10_7_lsb 0
+#define    p_reg_sdio_VERS_10_8 0xF198
+#define reg_sdio_VERS_10_8_pos 0
+#define reg_sdio_VERS_10_8_len 8
+#define reg_sdio_VERS_10_8_lsb 0
+#define    p_reg_sdio_VERS_10_9 0xF199
+#define reg_sdio_VERS_10_9_pos 0
+#define reg_sdio_VERS_10_9_len 8
+#define reg_sdio_VERS_10_9_lsb 0
+#define    p_reg_sdio_VERS_10_A 0xF19A
+#define reg_sdio_VERS_10_A_pos 0
+#define reg_sdio_VERS_10_A_len 8
+#define reg_sdio_VERS_10_A_lsb 0
+#define    p_reg_sdio_VERS_10_B 0xF19B
+#define reg_sdio_VERS_10_B_pos 0
+#define reg_sdio_VERS_10_B_len 8
+#define reg_sdio_VERS_10_B_lsb 0
+#define    p_reg_sdio_VERS_10_C 0xF19C
+#define reg_sdio_VERS_10_C_pos 0
+#define reg_sdio_VERS_10_C_len 8
+#define reg_sdio_VERS_10_C_lsb 0
+#define    p_reg_sdio_VERS_10_D 0xF19D
+#define reg_sdio_VERS_10_D_pos 0
+#define reg_sdio_VERS_10_D_len 8
+#define reg_sdio_VERS_10_D_lsb 0
+#define    p_reg_sdio_VERS_10_E 0xF19E
+#define reg_sdio_VERS_10_E_pos 0
+#define reg_sdio_VERS_10_E_len 8
+#define reg_sdio_VERS_10_E_lsb 0
+#define    p_reg_sdio_VERS_10_F 0xF19F
+#define reg_sdio_VERS_10_F_pos 0
+#define reg_sdio_VERS_10_F_len 8
+#define reg_sdio_VERS_10_F_lsb 0
+#define    p_reg_sdio_VERS_10_10    0xF1A0
+#define reg_sdio_VERS_10_10_pos 0
+#define reg_sdio_VERS_10_10_len 8
+#define reg_sdio_VERS_10_10_lsb 0
+#define    p_reg_sdio_VERS_10_11    0xF1A1
+#define reg_sdio_VERS_10_11_pos 0
+#define reg_sdio_VERS_10_11_len 8
+#define reg_sdio_VERS_10_11_lsb 0
+#define    p_reg_sdio_VERS_10_12    0xF1A2
+#define reg_sdio_VERS_10_12_pos 0
+#define reg_sdio_VERS_10_12_len 8
+#define reg_sdio_VERS_10_12_lsb 0
+#define    p_reg_sdio_VERS_10_13    0xF1A3
+#define reg_sdio_VERS_10_13_pos 0
+#define reg_sdio_VERS_10_13_len 8
+#define reg_sdio_VERS_10_13_lsb 0
+#define    p_reg_sdio_VERS_10_14    0xF1A4
+#define reg_sdio_VERS_10_14_pos 0
+#define reg_sdio_VERS_10_14_len 8
+#define reg_sdio_VERS_10_14_lsb 0
+#define    p_reg_sdio_VERS_10_15    0xF1A5
+#define reg_sdio_VERS_10_15_pos 0
+#define reg_sdio_VERS_10_15_len 8
+#define reg_sdio_VERS_10_15_lsb 0
+#define    p_reg_sdio_VERS_10_16    0xF1A6
+#define reg_sdio_VERS_10_16_pos 0
+#define reg_sdio_VERS_10_16_len 8
+#define reg_sdio_VERS_10_16_lsb 0
+#define    p_reg_sdio_VERS_10_17    0xF1A7
+#define reg_sdio_VERS_10_17_pos 0
+#define reg_sdio_VERS_10_17_len 8
+#define reg_sdio_VERS_10_17_lsb 0
+#define    p_reg_sdio_VERS_10_18    0xF1A8
+#define reg_sdio_VERS_10_18_pos 0
+#define reg_sdio_VERS_10_18_len 8
+#define reg_sdio_VERS_10_18_lsb 0
+#define    p_reg_sdio_VERS_10_19    0xF1A9
+#define reg_sdio_VERS_10_19_pos 0
+#define reg_sdio_VERS_10_19_len 8
+#define reg_sdio_VERS_10_19_lsb 0
+#define    p_reg_sdio_VERS_10_1A    0xF1AA
+#define reg_sdio_VERS_10_1A_pos 0
+#define reg_sdio_VERS_10_1A_len 8
+#define reg_sdio_VERS_10_1A_lsb 0
+#define    p_reg_sdio_VERS_10_1B    0xF1AB
+#define reg_sdio_VERS_10_1B_pos 0
+#define reg_sdio_VERS_10_1B_len 8
+#define reg_sdio_VERS_10_1B_lsb 0
+#define    p_reg_sdio_VERS_10_1C    0xF1AC
+#define reg_sdio_VERS_10_1C_pos 0
+#define reg_sdio_VERS_10_1C_len 8
+#define reg_sdio_VERS_10_1C_lsb 0
+#define    p_reg_sdio_VERS_10_1D    0xF1AD
+#define reg_sdio_VERS_10_1D_pos 0
+#define reg_sdio_VERS_10_1D_len 8
+#define reg_sdio_VERS_10_1D_lsb 0
+#define    p_reg_sdio_VERS_10_1E    0xF1AE
+#define reg_sdio_VERS_10_1E_pos 0
+#define reg_sdio_VERS_10_1E_len 8
+#define reg_sdio_VERS_10_1E_lsb 0
+#define    p_reg_sdio_VERS_10_1F    0xF1AF
+#define reg_sdio_VERS_10_1F_pos 0
+#define reg_sdio_VERS_10_1F_len 8
+#define reg_sdio_VERS_10_1F_lsb 0
+#define    p_reg_sdio_VERS_10_20    0xF1B0
+#define reg_sdio_VERS_10_20_pos 0
+#define reg_sdio_VERS_10_20_len 8
+#define reg_sdio_VERS_10_20_lsb 0
+#define    p_reg_sdio_VERS_10_21    0xF1B1
+#define reg_sdio_VERS_10_21_pos 0
+#define reg_sdio_VERS_10_21_len 8
+#define reg_sdio_VERS_10_21_lsb 0
+#define    p_reg_sdio_VERS_10_22    0xF1B2
+#define reg_sdio_VERS_10_22_pos 0
+#define reg_sdio_VERS_10_22_len 8
+#define reg_sdio_VERS_10_22_lsb 0
+#define    p_reg_sdio_VERS_10_23    0xF1B3
+#define reg_sdio_VERS_10_23_pos 0
+#define reg_sdio_VERS_10_23_len 8
+#define reg_sdio_VERS_10_23_lsb 0
+#define    p_reg_sdio_VERS_10_24    0xF1B4
+#define reg_sdio_VERS_10_24_pos 0
+#define reg_sdio_VERS_10_24_len 8
+#define reg_sdio_VERS_10_24_lsb 0
+#define    p_reg_sdio_VERS_10_25    0xF1B5
+#define reg_sdio_VERS_10_25_pos 0
+#define reg_sdio_VERS_10_25_len 8
+#define reg_sdio_VERS_10_25_lsb 0
+#define    p_reg_sdio_VERS_10_26    0xF1B6
+#define reg_sdio_VERS_10_26_pos 0
+#define reg_sdio_VERS_10_26_len 8
+#define reg_sdio_VERS_10_26_lsb 0
+#define    p_reg_sdio_VERS_10_27    0xF1B7
+#define reg_sdio_VERS_10_27_pos 0
+#define reg_sdio_VERS_10_27_len 8
+#define reg_sdio_VERS_10_27_lsb 0
+#define    p_reg_sdio_END0  0xF1B8
+#define reg_sdio_END0_pos 0
+#define reg_sdio_END0_len 8
+#define reg_sdio_END0_lsb 0
+#define    p_reg_sdio_FUNCID1_0 0xF1C0
+#define reg_sdio_FUNCID1_0_pos 0
+#define reg_sdio_FUNCID1_0_len 8
+#define reg_sdio_FUNCID1_0_lsb 0
+#define    p_reg_sdio_FUNCID1_1 0xF1C1
+#define reg_sdio_FUNCID1_1_pos 0
+#define reg_sdio_FUNCID1_1_len 8
+#define reg_sdio_FUNCID1_1_lsb 0
+#define    p_reg_sdio_FUNCID1_2 0xF1C2
+#define reg_sdio_FUNCID1_2_pos 0
+#define reg_sdio_FUNCID1_2_len 8
+#define reg_sdio_FUNCID1_2_lsb 0
+#define    p_reg_sdio_FUNCID1_3 0xF1C3
+#define reg_sdio_FUNCID1_3_pos 0
+#define reg_sdio_FUNCID1_3_len 8
+#define reg_sdio_FUNCID1_3_lsb 0
+#define    p_reg_sdio_FUNCE1_0  0xF1C4
+#define reg_sdio_FUNCE1_0_pos 0
+#define reg_sdio_FUNCE1_0_len 8
+#define reg_sdio_FUNCE1_0_lsb 0
+#define    p_reg_sdio_FUNCE1_1  0xF1C5
+#define reg_sdio_FUNCE1_1_pos 0
+#define reg_sdio_FUNCE1_1_len 8
+#define reg_sdio_FUNCE1_1_lsb 0
+#define    p_reg_sdio_FUNCE1_2  0xF1C6
+#define reg_sdio_FUNCE1_2_pos 0
+#define reg_sdio_FUNCE1_2_len 8
+#define reg_sdio_FUNCE1_2_lsb 0
+#define    p_reg_sdio_FUNCE1_3  0xF1C7
+#define reg_sdio_FUNCE1_3_pos 0
+#define reg_sdio_FUNCE1_3_len 8
+#define reg_sdio_FUNCE1_3_lsb 0
+#define    p_reg_sdio_FUNCE1_4  0xF1C8
+#define reg_sdio_FUNCE1_4_pos 0
+#define reg_sdio_FUNCE1_4_len 8
+#define reg_sdio_FUNCE1_4_lsb 0
+#define    p_reg_sdio_FUNCE1_5_7_0  0xF1C9
+#define reg_sdio_FUNCE1_5_7_0_pos 0
+#define reg_sdio_FUNCE1_5_7_0_len 8
+#define reg_sdio_FUNCE1_5_7_0_lsb 0
+#define    p_reg_sdio_FUNCE1_5_15_8 0xF1CA
+#define reg_sdio_FUNCE1_5_15_8_pos 0
+#define reg_sdio_FUNCE1_5_15_8_len 8
+#define reg_sdio_FUNCE1_5_15_8_lsb 8
+#define    p_reg_sdio_FUNCE1_5_23_16    0xF1CB
+#define reg_sdio_FUNCE1_5_23_16_pos 0
+#define reg_sdio_FUNCE1_5_23_16_len 8
+#define reg_sdio_FUNCE1_5_23_16_lsb 16
+#define    p_reg_sdio_FUNCE1_5_31_24    0xF1CC
+#define reg_sdio_FUNCE1_5_31_24_pos 0
+#define reg_sdio_FUNCE1_5_31_24_len 8
+#define reg_sdio_FUNCE1_5_31_24_lsb 24
+#define    p_reg_sdio_FUNCE1_9_7_0  0xF1CD
+#define reg_sdio_FUNCE1_9_7_0_pos 0
+#define reg_sdio_FUNCE1_9_7_0_len 8
+#define reg_sdio_FUNCE1_9_7_0_lsb 0
+#define    p_reg_sdio_FUNCE1_9_15_8 0xF1CE
+#define reg_sdio_FUNCE1_9_15_8_pos 0
+#define reg_sdio_FUNCE1_9_15_8_len 8
+#define reg_sdio_FUNCE1_9_15_8_lsb 8
+#define    p_reg_sdio_FUNCE1_9_23_16    0xF1CF
+#define reg_sdio_FUNCE1_9_23_16_pos 0
+#define reg_sdio_FUNCE1_9_23_16_len 8
+#define reg_sdio_FUNCE1_9_23_16_lsb 16
+#define    p_reg_sdio_FUNCE1_9_31_24    0xF1D0
+#define reg_sdio_FUNCE1_9_31_24_pos 0
+#define reg_sdio_FUNCE1_9_31_24_len 8
+#define reg_sdio_FUNCE1_9_31_24_lsb 24
+#define    p_reg_sdio_FUNCE1_D  0xF1D1
+#define reg_sdio_FUNCE1_D_pos 0
+#define reg_sdio_FUNCE1_D_len 8
+#define reg_sdio_FUNCE1_D_lsb 0
+#define    p_reg_sdio_FUNCE1_E_7_0  0xF1D2
+#define reg_sdio_FUNCE1_E_7_0_pos 0
+#define reg_sdio_FUNCE1_E_7_0_len 8
+#define reg_sdio_FUNCE1_E_7_0_lsb 0
+#define    p_reg_sdio_FUNCE1_E_15_8 0xF1D3
+#define reg_sdio_FUNCE1_E_15_8_pos 0
+#define reg_sdio_FUNCE1_E_15_8_len 8
+#define reg_sdio_FUNCE1_E_15_8_lsb 8
+#define    p_reg_sdio_FUNCE1_10_7_0 0xF1D4
+#define reg_sdio_FUNCE1_10_7_0_pos 0
+#define reg_sdio_FUNCE1_10_7_0_len 8
+#define reg_sdio_FUNCE1_10_7_0_lsb 0
+#define    p_reg_sdio_FUNCE1_10_15_8    0xF1D5
+#define reg_sdio_FUNCE1_10_15_8_pos 0
+#define reg_sdio_FUNCE1_10_15_8_len 8
+#define reg_sdio_FUNCE1_10_15_8_lsb 8
+#define    p_reg_sdio_FUNCE1_10_23_16   0xF1D6
+#define reg_sdio_FUNCE1_10_23_16_pos 0
+#define reg_sdio_FUNCE1_10_23_16_len 8
+#define reg_sdio_FUNCE1_10_23_16_lsb 16
+#define    p_reg_sdio_FUNCE1_10_31_24   0xF1D7
+#define reg_sdio_FUNCE1_10_31_24_pos 0
+#define reg_sdio_FUNCE1_10_31_24_len 8
+#define reg_sdio_FUNCE1_10_31_24_lsb 24
+#define    p_reg_sdio_FUNCE1_14 0xF1D8
+#define reg_sdio_FUNCE1_14_pos 0
+#define reg_sdio_FUNCE1_14_len 8
+#define reg_sdio_FUNCE1_14_lsb 0
+#define    p_reg_sdio_FUNCE1_15 0xF1D9
+#define reg_sdio_FUNCE1_15_pos 0
+#define reg_sdio_FUNCE1_15_len 8
+#define reg_sdio_FUNCE1_15_lsb 0
+#define    p_reg_sdio_FUNCE1_16 0xF1DA
+#define reg_sdio_FUNCE1_16_pos 0
+#define reg_sdio_FUNCE1_16_len 8
+#define reg_sdio_FUNCE1_16_lsb 0
+#define    p_reg_sdio_FUNCE1_17 0xF1DB
+#define reg_sdio_FUNCE1_17_pos 0
+#define reg_sdio_FUNCE1_17_len 8
+#define reg_sdio_FUNCE1_17_lsb 0
+#define    p_reg_sdio_FUNCE1_18 0xF1DC
+#define reg_sdio_FUNCE1_18_pos 0
+#define reg_sdio_FUNCE1_18_len 8
+#define reg_sdio_FUNCE1_18_lsb 0
+#define    p_reg_sdio_FUNCE1_19 0xF1DD
+#define reg_sdio_FUNCE1_19_pos 0
+#define reg_sdio_FUNCE1_19_len 8
+#define reg_sdio_FUNCE1_19_lsb 0
+#define    p_reg_sdio_FUNCE1_1A_7_0 0xF1DE
+#define reg_sdio_FUNCE1_1A_7_0_pos 0
+#define reg_sdio_FUNCE1_1A_7_0_len 8
+#define reg_sdio_FUNCE1_1A_7_0_lsb 0
+#define    p_reg_sdio_FUNCE1_1A_15_8    0xF1DF
+#define reg_sdio_FUNCE1_1A_15_8_pos 0
+#define reg_sdio_FUNCE1_1A_15_8_len 8
+#define reg_sdio_FUNCE1_1A_15_8_lsb 8
+#define    p_reg_sdio_FUNCE1_1C_7_0 0xF1E0
+#define reg_sdio_FUNCE1_1C_7_0_pos 0
+#define reg_sdio_FUNCE1_1C_7_0_len 8
+#define reg_sdio_FUNCE1_1C_7_0_lsb 0
+#define    p_reg_sdio_FUNCE1_1C_15_8    0xF1E1
+#define reg_sdio_FUNCE1_1C_15_8_pos 0
+#define reg_sdio_FUNCE1_1C_15_8_len 8
+#define reg_sdio_FUNCE1_1C_15_8_lsb 8
+#define    p_reg_sdio_FUNCE1_1E_7_0 0xF1E2
+#define reg_sdio_FUNCE1_1E_7_0_pos 0
+#define reg_sdio_FUNCE1_1E_7_0_len 8
+#define reg_sdio_FUNCE1_1E_7_0_lsb 0
+#define    p_reg_sdio_FUNCE1_1E_15_8    0xF1E3
+#define reg_sdio_FUNCE1_1E_15_8_pos 0
+#define reg_sdio_FUNCE1_1E_15_8_len 8
+#define reg_sdio_FUNCE1_1E_15_8_lsb 8
+#define    p_reg_sdio_FUNCE1_20_7_0 0xF1E4
+#define reg_sdio_FUNCE1_20_7_0_pos 0
+#define reg_sdio_FUNCE1_20_7_0_len 8
+#define reg_sdio_FUNCE1_20_7_0_lsb 0
+#define    p_reg_sdio_FUNCE1_20_15_8    0xF1E5
+#define reg_sdio_FUNCE1_20_15_8_pos 0
+#define reg_sdio_FUNCE1_20_15_8_len 8
+#define reg_sdio_FUNCE1_20_15_8_lsb 8
+#define    p_reg_sdio_FUNCE1_22_7_0 0xF1E6
+#define reg_sdio_FUNCE1_22_7_0_pos 0
+#define reg_sdio_FUNCE1_22_7_0_len 8
+#define reg_sdio_FUNCE1_22_7_0_lsb 0
+#define    p_reg_sdio_FUNCE1_22_15_8    0xF1E7
+#define reg_sdio_FUNCE1_22_15_8_pos 0
+#define reg_sdio_FUNCE1_22_15_8_len 8
+#define reg_sdio_FUNCE1_22_15_8_lsb 8
+#define    p_reg_sdio_FUNCE1_24_7_0 0xF1E8
+#define reg_sdio_FUNCE1_24_7_0_pos 0
+#define reg_sdio_FUNCE1_24_7_0_len 8
+#define reg_sdio_FUNCE1_24_7_0_lsb 0
+#define    p_reg_sdio_FUNCE1_24_15_8    0xF1E9
+#define reg_sdio_FUNCE1_24_15_8_pos 0
+#define reg_sdio_FUNCE1_24_15_8_len 8
+#define reg_sdio_FUNCE1_24_15_8_lsb 8
+#define    p_reg_sdio_FUNCE1_26_7_0 0xF1EA
+#define reg_sdio_FUNCE1_26_7_0_pos 0
+#define reg_sdio_FUNCE1_26_7_0_len 8
+#define reg_sdio_FUNCE1_26_7_0_lsb 0
+#define    p_reg_sdio_FUNCE1_26_15_8    0xF1EB
+#define reg_sdio_FUNCE1_26_15_8_pos 0
+#define reg_sdio_FUNCE1_26_15_8_len 8
+#define reg_sdio_FUNCE1_26_15_8_lsb 8
+#define    p_reg_sdio_FUNCE1_28_7_0 0xF1EC
+#define reg_sdio_FUNCE1_28_7_0_pos 0
+#define reg_sdio_FUNCE1_28_7_0_len 8
+#define reg_sdio_FUNCE1_28_7_0_lsb 0
+#define    p_reg_sdio_FUNCE1_28_15_8    0xF1ED
+#define reg_sdio_FUNCE1_28_15_8_pos 0
+#define reg_sdio_FUNCE1_28_15_8_len 8
+#define reg_sdio_FUNCE1_28_15_8_lsb 8
+#define    p_reg_sdio_FUNCE1_2A_7_0 0xF1EE
+#define reg_sdio_FUNCE1_2A_7_0_pos 0
+#define reg_sdio_FUNCE1_2A_7_0_len 8
+#define reg_sdio_FUNCE1_2A_7_0_lsb 0
+#define    p_reg_sdio_FUNCE1_2A_15_8    0xF1EF
+#define reg_sdio_FUNCE1_2A_15_8_pos 0
+#define reg_sdio_FUNCE1_2A_15_8_len 8
+#define reg_sdio_FUNCE1_2A_15_8_lsb 8
+#define    p_reg_sdio_END1  0xF1F0
+#define reg_sdio_END1_pos 0
+#define reg_sdio_END1_len 8
+#define reg_sdio_END1_lsb 0
+#define    r_sdioc_tx_fifo_empty    0xF210
+#define sdioc_tx_fifo_empty_pos 0
+#define sdioc_tx_fifo_empty_len 1
+#define sdioc_tx_fifo_empty_lsb 0
+#define    p_reg_sdio_53ra  0xF210
+#define reg_sdio_53ra_pos 1
+#define reg_sdio_53ra_len 1
+#define reg_sdio_53ra_lsb 0
+#define    p_reg_sdioc_rd_wait_dly  0xF210
+#define reg_sdioc_rd_wait_dly_pos 4
+#define reg_sdioc_rd_wait_dly_len 2
+#define reg_sdioc_rd_wait_dly_lsb 0
+#define    p_reg_write_mbx_complete 0xF211
+#define reg_write_mbx_complete_pos 0
+#define reg_write_mbx_complete_len 1
+#define reg_write_mbx_complete_lsb 0
+#define    p_reg_sdioc_sw_err   0xF211
+#define reg_sdioc_sw_err_pos 1
+#define reg_sdioc_sw_err_len 1
+#define reg_sdioc_sw_err_lsb 0
+#define    p_reg_sdioc_tran_dat_dly 0xF211
+#define reg_sdioc_tran_dat_dly_pos 4
+#define reg_sdioc_tran_dat_dly_len 3
+#define reg_sdioc_tran_dat_dly_lsb 0
+#define    p_reg_sdioc_external_int_en  0xF212
+#define reg_sdioc_external_int_en_pos 1
+#define reg_sdioc_external_int_en_len 1
+#define reg_sdioc_external_int_en_lsb 0
+#define    r_reg_sdioc_external_int 0xF212
+#define reg_sdioc_external_int_pos 2
+#define reg_sdioc_external_int_len 1
+#define reg_sdioc_external_int_lsb 0
+#define    p_reg_auto_clrWB_en  0xF213
+#define reg_auto_clrWB_en_pos 0
+#define reg_auto_clrWB_en_len 1
+#define reg_auto_clrWB_en_lsb 0
+#define    p_reg_sdioc_crc_s_dly    0xF213
+#define reg_sdioc_crc_s_dly_pos 1
+#define reg_sdioc_crc_s_dly_len 1
+#define reg_sdioc_crc_s_dly_lsb 0
+#define    p_reg_sdioc_neg_out_sel  0xF213
+#define reg_sdioc_neg_out_sel_pos 2
+#define reg_sdioc_neg_out_sel_len 1
+#define reg_sdioc_neg_out_sel_lsb 0
+#define    p_reg_sdioc_tx_fifo_rst  0xF213
+#define reg_sdioc_tx_fifo_rst_pos 4
+#define reg_sdioc_tx_fifo_rst_len 1
+#define reg_sdioc_tx_fifo_rst_lsb 0
+#define    p_reg_sdioc_rx_fifo_rst  0xF213
+#define reg_sdioc_rx_fifo_rst_pos 5
+#define reg_sdioc_rx_fifo_rst_len 1
+#define reg_sdioc_rx_fifo_rst_lsb 0
+#define    p_reg_sdioc_auto_rst_sm_en   0xF213
+#define reg_sdioc_auto_rst_sm_en_pos 6
+#define reg_sdioc_auto_rst_sm_en_len 1
+#define reg_sdioc_auto_rst_sm_en_lsb 0
+#define    p_sdio_link_clr_Wbusy_en 0xF214
+#define sdio_link_clr_Wbusy_en_pos 0
+#define sdio_link_clr_Wbusy_en_len 1
+#define sdio_link_clr_Wbusy_en_lsb 0
+#define    p_sdio_link_clr_Wbusy    0xF214
+#define sdio_link_clr_Wbusy_pos 1
+#define sdio_link_clr_Wbusy_len 1
+#define sdio_link_clr_Wbusy_lsb 0
+#define    p_reg_sdioc_dbg_sel  0xF214
+#define reg_sdioc_dbg_sel_pos 4
+#define reg_sdioc_dbg_sel_len 4
+#define reg_sdioc_dbg_sel_lsb 0
+#define    p_reg_sdioc_skip_ocr 0xF215
+#define reg_sdioc_skip_ocr_pos 0
+#define reg_sdioc_skip_ocr_len 1
+#define reg_sdioc_skip_ocr_lsb 0
+#define    p_reg_sdioc_spi_ns   0xF215
+#define reg_sdioc_spi_ns_pos 1
+#define reg_sdioc_spi_ns_len 1
+#define reg_sdioc_spi_ns_lsb 0
+#define    r_sdio_spi_mode  0xF215
+#define sdio_spi_mode_pos 7
+#define sdio_spi_mode_len 1
+#define sdio_spi_mode_lsb 0
+#define    r_link_ofsm_mailbox_int  0xF402
+#define link_ofsm_mailbox_int_pos 4
+#define link_ofsm_mailbox_int_len 1
+#define link_ofsm_mailbox_int_lsb 0
+#define    r_link_ofsm_dvbt_int 0xF403
+#define link_ofsm_dvbt_int_pos 2
+#define link_ofsm_dvbt_int_len 1
+#define link_ofsm_dvbt_int_lsb 0
+#define    p_reg_dvbt_intsts    0xF404
+#define reg_dvbt_intsts_pos 2
+#define reg_dvbt_intsts_len 1
+#define reg_dvbt_intsts_lsb 0
+#define    p_reg_link_mailbox_int   0xF405
+#define reg_link_mailbox_int_pos 5
+#define reg_link_mailbox_int_len 1
+#define reg_link_mailbox_int_lsb 0
+#define    p_reg_mailbox_wptr_rst   0xF408
+#define reg_mailbox_wptr_rst_pos 0
+#define reg_mailbox_wptr_rst_len 1
+#define reg_mailbox_wptr_rst_lsb 0
+#define    p_reg_link_mailbox_wptr  0xF409
+#define reg_link_mailbox_wptr_pos 0
+#define reg_link_mailbox_wptr_len 8
+#define reg_link_mailbox_wptr_lsb 0
+#define    p_reg_link_mailbox_wend  0xF410
+#define reg_link_mailbox_wend_pos 0
+#define reg_link_mailbox_wend_len 1
+#define reg_link_mailbox_wend_lsb 0
+#define    p_reg_rd_data_sel    0xF411
+#define reg_rd_data_sel_pos 0
+#define reg_rd_data_sel_len 2
+#define reg_rd_data_sel_lsb 0
+#define    p_reg_fifo_rd_length_7_0 0xF412
+#define reg_fifo_rd_length_7_0_pos 0
+#define reg_fifo_rd_length_7_0_len 8
+#define reg_fifo_rd_length_7_0_lsb 0
+#define    p_reg_fifo_rd_length_15_8    0xF413
+#define reg_fifo_rd_length_15_8_pos 0
+#define reg_fifo_rd_length_15_8_len 8
+#define reg_fifo_rd_length_15_8_lsb 8
+#define    p_reg_fifo_rd_length_17_16   0xF414
+#define reg_fifo_rd_length_17_16_pos 0
+#define reg_fifo_rd_length_17_16_len 2
+#define reg_fifo_rd_length_17_16_lsb 16
+#define    p_reg_rst_fifo_rptr  0xF414
+#define reg_rst_fifo_rptr_pos 6
+#define reg_rst_fifo_rptr_len 1
+#define reg_rst_fifo_rptr_lsb 0
+#define    p_reg_force_sel  0xF414
+#define reg_force_sel_pos 7
+#define reg_force_sel_len 1
+#define reg_force_sel_lsb 0
+#define    p_reg_fifo_rptr_7_0  0xF415
+#define reg_fifo_rptr_7_0_pos 0
+#define reg_fifo_rptr_7_0_len 8
+#define reg_fifo_rptr_7_0_lsb 0
+#define    p_reg_fifo_rptr_15_8 0xF416
+#define reg_fifo_rptr_15_8_pos 0
+#define reg_fifo_rptr_15_8_len 8
+#define reg_fifo_rptr_15_8_lsb 8
+#define    p_reg_fifo_rptr_17_16    0xF417
+#define reg_fifo_rptr_17_16_pos 0
+#define reg_fifo_rptr_17_16_len 2
+#define reg_fifo_rptr_17_16_lsb 16
+#define    p_reg_max_package_size_7_0   0xF418
+#define reg_max_package_size_7_0_pos 0
+#define reg_max_package_size_7_0_len 8
+#define reg_max_package_size_7_0_lsb 0
+#define    p_reg_max_package_size_11_8  0xF419
+#define reg_max_package_size_11_8_pos 0
+#define reg_max_package_size_11_8_len 4
+#define reg_max_package_size_11_8_lsb 8
+#define    p_reg_dvbt_en    0xF41A
+#define reg_dvbt_en_pos 0
+#define reg_dvbt_en_len 1
+#define reg_dvbt_en_lsb 0
+#define    p_reg_dvbt_bufsize   0xF41A
+#define reg_dvbt_bufsize_pos 1
+#define reg_dvbt_bufsize_len 1
+#define reg_dvbt_bufsize_lsb 0
+#define    p_reg_dvbt_path  0xF41A
+#define reg_dvbt_path_pos 2
+#define reg_dvbt_path_len 1
+#define reg_dvbt_path_lsb 0
+#define    p_reg_dvbt_r5    0xF41A
+#define reg_dvbt_r5_pos 3
+#define reg_dvbt_r5_len 1
+#define reg_dvbt_r5_lsb 0
+#define    p_reg_mailbox_inten  0xF41E
+#define reg_mailbox_inten_pos 4
+#define reg_mailbox_inten_len 1
+#define reg_mailbox_inten_lsb 0
+#define    p_reg_dvbt_inten 0xF41F
+#define reg_dvbt_inten_pos 2
+#define reg_dvbt_inten_len 1
+#define reg_dvbt_inten_lsb 0
+#define    r_link_ofsm_ip_length_7_0    0xF447
+#define link_ofsm_ip_length_7_0_pos 0
+#define link_ofsm_ip_length_7_0_len 8
+#define link_ofsm_ip_length_7_0_lsb 0
+#define    r_link_ofsm_ip_length_11_8   0xF448
+#define link_ofsm_ip_length_11_8_pos 0
+#define link_ofsm_ip_length_11_8_len 4
+#define link_ofsm_ip_length_11_8_lsb 8
+#define    r_link_ofsm_ip_valid 0xF448
+#define link_ofsm_ip_valid_pos 7
+#define link_ofsm_ip_valid_len 1
+#define link_ofsm_ip_valid_lsb 0
+#define    p_reg_spi_master 0xF600
+#define reg_spi_master_pos 0
+#define reg_spi_master_len 1
+#define reg_spi_master_lsb 0
+#define    p_reg_spi_bit    0xF601
+#define reg_spi_bit_pos 0
+#define reg_spi_bit_len 2
+#define reg_spi_bit_lsb 0
+#define    p_reg_spi_cs 0xF602
+#define reg_spi_cs_pos 0
+#define reg_spi_cs_len 1
+#define reg_spi_cs_lsb 0
+#define    p_reg_spi_polarity   0xF602
+#define reg_spi_polarity_pos 1
+#define reg_spi_polarity_len 1
+#define reg_spi_polarity_lsb 0
+#define    p_reg_spi_phase  0xF602
+#define reg_spi_phase_pos 2
+#define reg_spi_phase_len 1
+#define reg_spi_phase_lsb 0
+#define    p_reg_spi_1st_byte   0xF603
+#define reg_spi_1st_byte_pos 0
+#define reg_spi_1st_byte_len 4
+#define reg_spi_1st_byte_lsb 0
+#define    p_reg_spi_clk_div    0xF603
+#define reg_spi_clk_div_pos 4
+#define reg_spi_clk_div_len 4
+#define reg_spi_clk_div_lsb 0
+#define    p_reg_spi_rst    0xF604
+#define reg_spi_rst_pos 0
+#define reg_spi_rst_len 1
+#define reg_spi_rst_lsb 0
+#define    r_reg_spi_tx_done    0xF604
+#define reg_spi_tx_done_pos 1
+#define reg_spi_tx_done_len 1
+#define reg_spi_tx_done_lsb 0
+#define    r_reg_spi_rx_done    0xF604
+#define reg_spi_rx_done_pos 2
+#define reg_spi_rx_done_len 1
+#define reg_spi_rx_done_lsb 0
+#define    p_reg_spi_dbg_sel    0xF604
+#define reg_spi_dbg_sel_pos 3
+#define reg_spi_dbg_sel_len 1
+#define reg_spi_dbg_sel_lsb 0
+#define    r_reg_spi_crc_err    0xF604
+#define reg_spi_crc_err_pos 4
+#define reg_spi_crc_err_len 4
+#define reg_spi_crc_err_lsb 0
+#define    r_link_ofsm_usb20_mode   0xF613
+#define link_ofsm_usb20_mode_pos 0
+#define link_ofsm_usb20_mode_len 1
+#define link_ofsm_usb20_mode_lsb 0
+#define    r_link_ofsm_strap_usb20_mode 0xF613
+#define link_ofsm_strap_usb20_mode_pos 1
+#define link_ofsm_strap_usb20_mode_len 1
+#define link_ofsm_strap_usb20_mode_lsb 0
+#define    p_reg_link_stick_mem_end_7_0 0xF618
+#define reg_link_stick_mem_end_7_0_pos 0
+#define reg_link_stick_mem_end_7_0_len 8
+#define reg_link_stick_mem_end_7_0_lsb 0
+#define    p_reg_link_stick_mem_end_15_8    0xF619
+#define reg_link_stick_mem_end_15_8_pos 0
+#define reg_link_stick_mem_end_15_8_len 8
+#define reg_link_stick_mem_end_15_8_lsb 8
+#define    p_reg_ofdm_auto_write_addr_l 0xF61A
+#define reg_ofdm_auto_write_addr_l_pos 0
+#define reg_ofdm_auto_write_addr_l_len 8
+#define reg_ofdm_auto_write_addr_l_lsb 0
+#define    p_reg_ofdm_auto_write_addr_h 0xF61B
+#define reg_ofdm_auto_write_addr_h_pos 0
+#define reg_ofdm_auto_write_addr_h_len 8
+#define reg_ofdm_auto_write_addr_h_lsb 0
+#define    p_reg_link_auto_write_addr_l 0xF61C
+#define reg_link_auto_write_addr_l_pos 0
+#define reg_link_auto_write_addr_l_len 8
+#define reg_link_auto_write_addr_l_lsb 0
+#define    p_reg_link_auto_write_addr_h 0xF61D
+#define reg_link_auto_write_addr_h_pos 0
+#define reg_link_auto_write_addr_h_len 8
+#define reg_link_auto_write_addr_h_lsb 0
+#define    p_reg_mailbox_auto_write_addr    0xF61E
+#define reg_mailbox_auto_write_addr_pos 0
+#define reg_mailbox_auto_write_addr_len 8
+#define reg_mailbox_auto_write_addr_lsb 0
+#define    p_reg_usbmem_auto_write_addr 0xF61F
+#define reg_usbmem_auto_write_addr_pos 0
+#define reg_usbmem_auto_write_addr_len 8
+#define reg_usbmem_auto_write_addr_lsb 0
+#define    p_reg_mailbox_auto_read_addr 0xF620
+#define reg_mailbox_auto_read_addr_pos 0
+#define reg_mailbox_auto_read_addr_len 8
+#define reg_mailbox_auto_read_addr_lsb 0
+#define    p_reg_usbmem_auto_read_addr  0xF621
+#define reg_usbmem_auto_read_addr_pos 0
+#define reg_usbmem_auto_read_addr_len 8
+#define reg_usbmem_auto_read_addr_lsb 0
+#define    p_reg_auto_write_ofdm    0xF622
+#define reg_auto_write_ofdm_pos 0
+#define reg_auto_write_ofdm_len 1
+#define reg_auto_write_ofdm_lsb 0
+#define    p_reg_auto_write_link    0xF622
+#define reg_auto_write_link_pos 1
+#define reg_auto_write_link_len 1
+#define reg_auto_write_link_lsb 0
+#define    p_reg_auto_write_mailbox 0xF622
+#define reg_auto_write_mailbox_pos 2
+#define reg_auto_write_mailbox_len 1
+#define reg_auto_write_mailbox_lsb 0
+#define    p_reg_auto_write_usbmem  0xF622
+#define reg_auto_write_usbmem_pos 3
+#define reg_auto_write_usbmem_len 1
+#define reg_auto_write_usbmem_lsb 0
+#define    p_reg_auto_write_i2cm    0xF622
+#define reg_auto_write_i2cm_pos 4
+#define reg_auto_write_i2cm_len 1
+#define reg_auto_write_i2cm_lsb 0
+#define    p_reg_auto_read_mailbox  0xF623
+#define reg_auto_read_mailbox_pos 0
+#define reg_auto_read_mailbox_len 1
+#define reg_auto_read_mailbox_lsb 0
+#define    p_reg_auto_read_rom  0xF623
+#define reg_auto_read_rom_pos 1
+#define reg_auto_read_rom_len 1
+#define reg_auto_read_rom_lsb 0
+#define    p_reg_auto_sum_l 0xF624
+#define reg_auto_sum_l_pos 0
+#define reg_auto_sum_l_len 8
+#define reg_auto_sum_l_lsb 0
+#define    p_reg_auto_sum_h 0xF625
+#define reg_auto_sum_h_pos 0
+#define reg_auto_sum_h_len 8
+#define reg_auto_sum_h_lsb 0
+#define    p_reg_auto_sum_to_h  0xF626
+#define reg_auto_sum_to_h_pos 0
+#define reg_auto_sum_to_h_len 1
+#define reg_auto_sum_to_h_lsb 0
+#define    p_reg_auto_sum_en    0xF627
+#define reg_auto_sum_en_pos 0
+#define reg_auto_sum_en_len 1
+#define reg_auto_sum_en_lsb 0
+#define    p_reg_rom_remap_begin_7_0    0xF628
+#define reg_rom_remap_begin_7_0_pos 0
+#define reg_rom_remap_begin_7_0_len 8
+#define reg_rom_remap_begin_7_0_lsb 0
+#define    p_reg_rom_remap_begin_15_8   0xF629
+#define reg_rom_remap_begin_15_8_pos 0
+#define reg_rom_remap_begin_15_8_len 8
+#define reg_rom_remap_begin_15_8_lsb 8
+#define    p_reg_rom_remap_end_7_0  0xF62A
+#define reg_rom_remap_end_7_0_pos 0
+#define reg_rom_remap_end_7_0_len 8
+#define reg_rom_remap_end_7_0_lsb 0
+#define    p_reg_rom_remap_end_15_8 0xF62B
+#define reg_rom_remap_end_15_8_pos 0
+#define reg_rom_remap_end_15_8_len 8
+#define reg_rom_remap_end_15_8_lsb 8
+#define    p_reg_rom_remap_delta_7_0    0xF62C
+#define reg_rom_remap_delta_7_0_pos 0
+#define reg_rom_remap_delta_7_0_len 8
+#define reg_rom_remap_delta_7_0_lsb 0
+#define    p_reg_rom_remap_delta_15_8   0xF62D
+#define reg_rom_remap_delta_15_8_pos 0
+#define reg_rom_remap_delta_15_8_len 8
+#define reg_rom_remap_delta_15_8_lsb 8
+#define    p_reg_rom_remap_en   0xF62E
+#define reg_rom_remap_en_pos 0
+#define reg_rom_remap_en_len 1
+#define reg_rom_remap_en_lsb 0
+#define    p_reg_rom_remap_ofdm 0xF62E
+#define reg_rom_remap_ofdm_pos 1
+#define reg_rom_remap_ofdm_len 1
+#define reg_rom_remap_ofdm_lsb 0
+#define    p_reg_link_cpu_reset 0xF62F
+#define reg_link_cpu_reset_pos 0
+#define reg_link_cpu_reset_len 1
+#define reg_link_cpu_reset_lsb 0
+#define    p_reg_i2cm_auto_write_addr   0xF630
+#define reg_i2cm_auto_write_addr_pos 0
+#define reg_i2cm_auto_write_addr_len 8
+#define reg_i2cm_auto_write_addr_lsb 0
+#define    p_reg_link_bank_float_en 0xF631
+#define reg_link_bank_float_en_pos 0
+#define reg_link_bank_float_en_len 1
+#define reg_link_bank_float_en_lsb 0
+#define    p_reg_link_bank_float_start  0xF632
+#define reg_link_bank_float_start_pos 0
+#define reg_link_bank_float_start_len 8
+#define reg_link_bank_float_start_lsb 0
+#define    p_reg_link_bank_float_stop   0xF633
+#define reg_link_bank_float_stop_pos 0
+#define reg_link_bank_float_stop_len 8
+#define reg_link_bank_float_stop_lsb 0
+#define    p_reg_rom_auto_read_addr_7_0 0xF638
+#define reg_rom_auto_read_addr_7_0_pos 0
+#define reg_rom_auto_read_addr_7_0_len 8
+#define reg_rom_auto_read_addr_7_0_lsb 0
+#define    p_reg_rom_auto_read_addr_15_8    0xF639
+#define reg_rom_auto_read_addr_15_8_pos 0
+#define reg_rom_auto_read_addr_15_8_len 8
+#define reg_rom_auto_read_addr_15_8_lsb 8
+#define    p_reg_link_ofsm_dummy_7_0    0xF640
+#define reg_link_ofsm_dummy_7_0_pos 0
+#define reg_link_ofsm_dummy_7_0_len 8
+#define reg_link_ofsm_dummy_7_0_lsb 0
+#define    p_reg_link_ofsm_dummy_15_8   0xF641
+#define reg_link_ofsm_dummy_15_8_pos 0
+#define reg_link_ofsm_dummy_15_8_len 8
+#define reg_link_ofsm_dummy_15_8_lsb 8
+#define    p_reg_link_ofsm_dummy_23_16  0xF642
+#define reg_link_ofsm_dummy_23_16_pos 0
+#define reg_link_ofsm_dummy_23_16_len 8
+#define reg_link_ofsm_dummy_23_16_lsb 16
+#define    p_reg_link_ofsm_dummy_31_24  0xF643
+#define reg_link_ofsm_dummy_31_24_pos 0
+#define reg_link_ofsm_dummy_31_24_len 8
+#define reg_link_ofsm_dummy_31_24_lsb 24
+#define    p_reg_link_ofsm_dummy_39_32  0xF644
+#define reg_link_ofsm_dummy_39_32_pos 0
+#define reg_link_ofsm_dummy_39_32_len 8
+#define reg_link_ofsm_dummy_39_32_lsb 32
+#define    p_reg_link_ofsm_dummy_47_40  0xF645
+#define reg_link_ofsm_dummy_47_40_pos 0
+#define reg_link_ofsm_dummy_47_40_len 8
+#define reg_link_ofsm_dummy_47_40_lsb 40
+#define    p_reg_link_ofsm_dummy_55_48  0xF646
+#define reg_link_ofsm_dummy_55_48_pos 0
+#define reg_link_ofsm_dummy_55_48_len 8
+#define reg_link_ofsm_dummy_55_48_lsb 48
+#define    p_reg_link_ofsm_dummy_63_56  0xF647
+#define reg_link_ofsm_dummy_63_56_pos 0
+#define reg_link_ofsm_dummy_63_56_len 8
+#define reg_link_ofsm_dummy_63_56_lsb 56
+#define    p_reg_link_ofsm_dummy_71_64  0xF648
+#define reg_link_ofsm_dummy_71_64_pos 0
+#define reg_link_ofsm_dummy_71_64_len 8
+#define reg_link_ofsm_dummy_71_64_lsb 64
+#define    p_reg_link_ofsm_dummy_79_72  0xF649
+#define reg_link_ofsm_dummy_79_72_pos 0
+#define reg_link_ofsm_dummy_79_72_len 8
+#define reg_link_ofsm_dummy_79_72_lsb 72
+#define    p_reg_sdio_mode  0xF66F
+#define reg_sdio_mode_pos 0
+#define reg_sdio_mode_len 1
+#define reg_sdio_mode_lsb 0
+#define    p_reg_lnk2ofdm_data_7_0  0xF6A0
+#define reg_lnk2ofdm_data_7_0_pos 0
+#define reg_lnk2ofdm_data_7_0_len 8
+#define reg_lnk2ofdm_data_7_0_lsb 0
+#define    p_reg_lnk2ofdm_data_15_8 0xF6A1
+#define reg_lnk2ofdm_data_15_8_pos 0
+#define reg_lnk2ofdm_data_15_8_len 8
+#define reg_lnk2ofdm_data_15_8_lsb 8
+#define    p_reg_lnk2ofdm_data_23_16    0xF6A2
+#define reg_lnk2ofdm_data_23_16_pos 0
+#define reg_lnk2ofdm_data_23_16_len 8
+#define reg_lnk2ofdm_data_23_16_lsb 16
+#define    p_reg_lnk2ofdm_data_31_24    0xF6A3
+#define reg_lnk2ofdm_data_31_24_pos 0
+#define reg_lnk2ofdm_data_31_24_len 8
+#define reg_lnk2ofdm_data_31_24_lsb 24
+#define    p_reg_lnk2ofdm_data_39_32    0xF6A4
+#define reg_lnk2ofdm_data_39_32_pos 0
+#define reg_lnk2ofdm_data_39_32_len 8
+#define reg_lnk2ofdm_data_39_32_lsb 32
+#define    p_reg_lnk2ofdm_data_47_40    0xF6A5
+#define reg_lnk2ofdm_data_47_40_pos 0
+#define reg_lnk2ofdm_data_47_40_len 8
+#define reg_lnk2ofdm_data_47_40_lsb 40
+#define    p_reg_lnk2ofdm_data_55_48    0xF6A6
+#define reg_lnk2ofdm_data_55_48_pos 0
+#define reg_lnk2ofdm_data_55_48_len 8
+#define reg_lnk2ofdm_data_55_48_lsb 48
+#define    p_reg_lnk2ofdm_data_63_56    0xF6A7
+#define reg_lnk2ofdm_data_63_56_pos 0
+#define reg_lnk2ofdm_data_63_56_len 8
+#define reg_lnk2ofdm_data_63_56_lsb 56
+#define    p_reg_ofdmtolnk_data_7_0 0xF6A8
+#define reg_ofdmtolnk_data_7_0_pos 0
+#define reg_ofdmtolnk_data_7_0_len 8
+#define reg_ofdmtolnk_data_7_0_lsb 0
+#define    p_reg_ofdmtolnk_data_15_8    0xF6A9
+#define reg_ofdmtolnk_data_15_8_pos 0
+#define reg_ofdmtolnk_data_15_8_len 8
+#define reg_ofdmtolnk_data_15_8_lsb 8
+#define    p_reg_ofdmtolnk_data_23_16   0xF6AA
+#define reg_ofdmtolnk_data_23_16_pos 0
+#define reg_ofdmtolnk_data_23_16_len 8
+#define reg_ofdmtolnk_data_23_16_lsb 16
+#define    p_reg_ofdmtolnk_data_31_24   0xF6AB
+#define reg_ofdmtolnk_data_31_24_pos 0
+#define reg_ofdmtolnk_data_31_24_len 8
+#define reg_ofdmtolnk_data_31_24_lsb 24
+#define    p_reg_ofdmtolnk_data_39_32   0xF6AC
+#define reg_ofdmtolnk_data_39_32_pos 0
+#define reg_ofdmtolnk_data_39_32_len 8
+#define reg_ofdmtolnk_data_39_32_lsb 32
+#define    p_reg_ofdmtolnk_data_47_40   0xF6AD
+#define reg_ofdmtolnk_data_47_40_pos 0
+#define reg_ofdmtolnk_data_47_40_len 8
+#define reg_ofdmtolnk_data_47_40_lsb 40
+#define    p_reg_ofdmtolnk_data_55_48   0xF6AE
+#define reg_ofdmtolnk_data_55_48_pos 0
+#define reg_ofdmtolnk_data_55_48_len 8
+#define reg_ofdmtolnk_data_55_48_lsb 48
+#define    p_reg_ofdmtolnk_data_63_56   0xF6AF
+#define reg_ofdmtolnk_data_63_56_pos 0
+#define reg_ofdmtolnk_data_63_56_len 8
+#define reg_ofdmtolnk_data_63_56_lsb 56
+#define    p_reg_mon51_flag 0xF6B0
+#define reg_mon51_flag_pos 0
+#define reg_mon51_flag_len 1
+#define reg_mon51_flag_lsb 0
+#define    p_reg_force_mon51    0xF6B1
+#define reg_force_mon51_pos 0
+#define reg_force_mon51_len 1
+#define reg_force_mon51_lsb 0
+#define    p_reg_which_cpu  0xF6B2
+#define reg_which_cpu_pos 0
+#define reg_which_cpu_len 1
+#define reg_which_cpu_lsb 0
+#define    p_reg_program_ofdm_code_ready    0xF6B3
+#define reg_program_ofdm_code_ready_pos 0
+#define reg_program_ofdm_code_ready_len 1
+#define reg_program_ofdm_code_ready_lsb 0
+#define    p_reg_link_wr_ofdm_en    0xF6B3
+#define reg_link_wr_ofdm_en_pos 1
+#define reg_link_wr_ofdm_en_len 1
+#define reg_link_wr_ofdm_en_lsb 0
+#define    p_reg_i2c_mode   0xF6B4
+#define reg_i2c_mode_pos 0
+#define reg_i2c_mode_len 1
+#define reg_i2c_mode_lsb 0
+#define    p_reg_sw_reset_sdio  0xF6B4
+#define reg_sw_reset_sdio_pos 1
+#define reg_sw_reset_sdio_len 1
+#define reg_sw_reset_sdio_lsb 0
+#define    p_reg_debug_mpefec_sel   0xF6B4
+#define reg_debug_mpefec_sel_pos 2
+#define reg_debug_mpefec_sel_len 1
+#define reg_debug_mpefec_sel_lsb 0
+#define    p_reg_lnk_dynamic_clk    0xF6B4
+#define reg_lnk_dynamic_clk_pos 3
+#define reg_lnk_dynamic_clk_len 1
+#define reg_lnk_dynamic_clk_lsb 0
+#define    p_reg_lnk_free_clk   0xF6B4
+#define reg_lnk_free_clk_pos 4
+#define reg_lnk_free_clk_len 1
+#define reg_lnk_free_clk_lsb 0
+#define    p_reg_i2c_sample_rate_up_en  0xF6B4
+#define reg_i2c_sample_rate_up_en_pos 5
+#define reg_i2c_sample_rate_up_en_len 1
+#define reg_i2c_sample_rate_up_en_lsb 0
+#define    p_reg_i2c_start_patch    0xF6B4
+#define reg_i2c_start_patch_pos 6
+#define reg_i2c_start_patch_len 1
+#define reg_i2c_start_patch_lsb 0
+#define    p_reg_link_i2cs_msb  0xF6B5
+#define reg_link_i2cs_msb_pos 1
+#define reg_link_i2cs_msb_len 1
+#define reg_link_i2cs_msb_lsb 0
+#define    p_reg_link_ofsm_dbg_en   0xF6B5
+#define reg_link_ofsm_dbg_en_pos 4
+#define reg_link_ofsm_dbg_en_len 1
+#define reg_link_ofsm_dbg_en_lsb 0
+#define    p_reg_link_i2c_dbg_sel   0xF6B5
+#define reg_link_i2c_dbg_sel_pos 5
+#define reg_link_i2c_dbg_sel_len 1
+#define reg_link_i2c_dbg_sel_lsb 0
+#define    p_reg_fast_slow_train    0xF6DD
+#define    p_reg_lnk2ofdm_int   0xF6DE
+#define reg_lnk2ofdm_int_pos 0
+#define reg_lnk2ofdm_int_len 1
+#define reg_lnk2ofdm_int_lsb 0
+#define    p_reg_ofdm2lnk_int   0xF6DF
+#define reg_ofdm2lnk_int_pos 0
+#define reg_ofdm2lnk_int_len 1
+#define reg_ofdm2lnk_int_lsb 0
+#define    p_reg_load_ofdm_reg  0xF6E4
+#define    p_link_ofsm_cmd_reg  0xF6EA
+#define link_ofsm_cmd_reg_pos 0
+#define link_ofsm_cmd_reg_len 8
+#define link_ofsm_cmd_reg_lsb 0
+#define    p_link_ofsm_addr_reg_h   0xF6EB
+#define link_ofsm_addr_reg_h_pos 0
+#define link_ofsm_addr_reg_h_len 8
+#define link_ofsm_addr_reg_h_lsb 0
+#define    p_link_ofsm_addr_reg_l   0xF6EC
+#define link_ofsm_addr_reg_l_pos 0
+#define link_ofsm_addr_reg_l_len 8
+#define link_ofsm_addr_reg_l_lsb 0
+#define    p_link_ofsm_data_reg_0   0xF6ED
+#define link_ofsm_data_reg_0_pos 0
+#define link_ofsm_data_reg_0_len 8
+#define link_ofsm_data_reg_0_lsb 0
+#define    p_link_ofsm_data_reg_1   0xF6EE
+#define link_ofsm_data_reg_1_pos 0
+#define link_ofsm_data_reg_1_len 8
+#define link_ofsm_data_reg_1_lsb 0
+#define    p_link_ofsm_data_reg_2   0xF6EF
+#define link_ofsm_data_reg_2_pos 0
+#define link_ofsm_data_reg_2_len 8
+#define link_ofsm_data_reg_2_lsb 0
+#define    p_link_ofsm_data_reg_3   0xF6F0
+#define link_ofsm_data_reg_3_pos 0
+#define link_ofsm_data_reg_3_len 8
+#define link_ofsm_data_reg_3_lsb 0
+#define    p_link_ofsm_data_reg_4   0xF6F1
+#define link_ofsm_data_reg_4_pos 0
+#define link_ofsm_data_reg_4_len 8
+#define link_ofsm_data_reg_4_lsb 0
+#define    p_link_ofsm_data_reg_5   0xF6F2
+#define link_ofsm_data_reg_5_pos 0
+#define link_ofsm_data_reg_5_len 8
+#define link_ofsm_data_reg_5_lsb 0
+#define    p_link_ofsm_data_reg_6   0xF6F3
+#define link_ofsm_data_reg_6_pos 0
+#define link_ofsm_data_reg_6_len 8
+#define link_ofsm_data_reg_6_lsb 0
+#define    p_link_ofsm_data_reg_7   0xF6F4
+#define link_ofsm_data_reg_7_pos 0
+#define link_ofsm_data_reg_7_len 8
+#define link_ofsm_data_reg_7_lsb 0
+#define    p_link_ofsm_data_reg_8   0xF6F5
+#define link_ofsm_data_reg_8_pos 0
+#define link_ofsm_data_reg_8_len 8
+#define link_ofsm_data_reg_8_lsb 0
+#define    p_link_ofsm_data_reg_9   0xF6F6
+#define link_ofsm_data_reg_9_pos 0
+#define link_ofsm_data_reg_9_len 8
+#define link_ofsm_data_reg_9_lsb 0
+#define    p_link_ofsm_data_reg_10  0xF6F7
+#define link_ofsm_data_reg_10_pos 0
+#define link_ofsm_data_reg_10_len 8
+#define link_ofsm_data_reg_10_lsb 0
+#define    p_link_ofsm_data_reg_11  0xF6F8
+#define link_ofsm_data_reg_11_pos 0
+#define link_ofsm_data_reg_11_len 8
+#define link_ofsm_data_reg_11_lsb 0
+#define    p_link_ofsm_data_reg_12  0xF6F9
+#define link_ofsm_data_reg_12_pos 0
+#define link_ofsm_data_reg_12_len 8
+#define link_ofsm_data_reg_12_lsb 0
+#define    p_link_ofsm_data_reg_13  0xF6FA
+#define link_ofsm_data_reg_13_pos 0
+#define link_ofsm_data_reg_13_len 8
+#define link_ofsm_data_reg_13_lsb 0
+#define    p_link_ofsm_data_reg_14  0xF6FB
+#define link_ofsm_data_reg_14_pos 0
+#define link_ofsm_data_reg_14_len 8
+#define link_ofsm_data_reg_14_lsb 0
+#define    p_link_ofsm_data_reg_15  0xF6FC
+#define link_ofsm_data_reg_15_pos 0
+#define link_ofsm_data_reg_15_len 8
+#define link_ofsm_data_reg_15_lsb 0
+#define    p_reg_debug_mux  0xF6FE
+#define reg_debug_mux_pos 3
+#define reg_debug_mux_len 1
+#define reg_debug_mux_lsb 0
+#define    p_reg_top_gpioon0    0xF6FF
+#define reg_top_gpioon0_pos 0
+#define reg_top_gpioon0_len 1
+#define reg_top_gpioon0_lsb 0
+#define    p_reg_p_dmb_phy_is_dvb   0xDC31
+#define reg_p_dmb_phy_is_dvb_pos 0
+#define reg_p_dmb_phy_is_dvb_len 1
+#define reg_p_dmb_phy_is_dvb_lsb 0
+#define    p_reg_p_dmb_xt_reset 0xDC32
+#define reg_p_dmb_xt_reset_pos 0
+#define reg_p_dmb_xt_reset_len 1
+#define reg_p_dmb_xt_reset_lsb 0
+#define    p_reg_p_dmb_sw_reset 0xDC33
+#define reg_p_dmb_sw_reset_pos 0
+#define reg_p_dmb_sw_reset_len 1
+#define reg_p_dmb_sw_reset_lsb 0
+
+#endif
diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index b4277ac..7102533 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -880,9 +880,7 @@ out:
 		goto retry;
 	if (!err)
 		mmc_blk_reset_success(md, type);
-	spin_lock_irq(&md->lock);
-	__blk_end_request(req, err, blk_rq_bytes(req));
-	spin_unlock_irq(&md->lock);
+	blk_end_request(req, err, blk_rq_bytes(req));
 
 	return err ? 0 : 1;
 }
@@ -964,9 +962,7 @@ out_retry:
 	if (!err)
 		mmc_blk_reset_success(md, type);
 out:
-	spin_lock_irq(&md->lock);
-	__blk_end_request(req, err, blk_rq_bytes(req));
-	spin_unlock_irq(&md->lock);
+	blk_end_request(req, err, blk_rq_bytes(req));
 
 	return err ? 0 : 1;
 }
@@ -981,9 +977,7 @@ static int mmc_blk_issue_flush(struct mmc_queue *mq, struct request *req)
 	if (ret)
 		ret = -EIO;
 
-	spin_lock_irq(&md->lock);
-	__blk_end_request_all(req, ret);
-	spin_unlock_irq(&md->lock);
+	blk_end_request_all(req, ret);
 
 	return ret ? 0 : 1;
 }
@@ -1306,14 +1300,10 @@ static int mmc_blk_cmd_err(struct mmc_blk_data *md, struct mmc_card *card,
 
 		blocks = mmc_sd_num_wr_blocks(card);
 		if (blocks != (u32)-1) {
-			spin_lock_irq(&md->lock);
-			ret = __blk_end_request(req, 0, blocks << 9);
-			spin_unlock_irq(&md->lock);
+			ret = blk_end_request(req, 0, blocks << 9);
 		}
 	} else {
-		spin_lock_irq(&md->lock);
-		ret = __blk_end_request(req, 0, brq->data.bytes_xfered);
-		spin_unlock_irq(&md->lock);
+		ret = blk_end_request(req, 0, brq->data.bytes_xfered);
 	}
 	return ret;
 }
@@ -1355,10 +1345,8 @@ static int mmc_blk_issue_rw_rq(struct mmc_queue *mq, struct request *rqc)
 			 * A block was successfully transferred.
 			 */
 			mmc_blk_reset_success(md, type);
-			spin_lock_irq(&md->lock);
-			ret = __blk_end_request(req, 0,
+			ret = blk_end_request(req, 0,
 						brq->data.bytes_xfered);
-			spin_unlock_irq(&md->lock);
 			/*
 			 * If the blk_end_request function returns non-zero even
 			 * though all data has been transferred and no errors
@@ -1410,10 +1398,8 @@ static int mmc_blk_issue_rw_rq(struct mmc_queue *mq, struct request *rqc)
 			 * time, so we only reach here after trying to
 			 * read a single sector.
 			 */
-			spin_lock_irq(&md->lock);
-			ret = __blk_end_request(req, -EIO,
+			ret = blk_end_request(req, -EIO,
 						brq->data.blksz);
-			spin_unlock_irq(&md->lock);
 			if (!ret)
 				goto start_new_req;
 			break;
@@ -1434,12 +1420,10 @@ static int mmc_blk_issue_rw_rq(struct mmc_queue *mq, struct request *rqc)
 	return 1;
 
  cmd_abort:
-	spin_lock_irq(&md->lock);
 	if (mmc_card_removed(card))
 		req->cmd_flags |= REQ_QUIET;
 	while (ret)
-		ret = __blk_end_request(req, -EIO, blk_rq_cur_bytes(req));
-	spin_unlock_irq(&md->lock);
+		ret = blk_end_request(req, -EIO, blk_rq_cur_bytes(req));
 
  start_new_req:
 	if (rqc) {
@@ -1463,9 +1447,7 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
 	ret = mmc_blk_part_switch(card, md);
 	if (ret) {
 		if (req) {
-			spin_lock_irq(&md->lock);
-			__blk_end_request_all(req, -EIO);
-			spin_unlock_irq(&md->lock);
+			blk_end_request_all(req, -EIO);
 		}
 		ret = 0;
 		goto out;
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index 5352cd7..0dbec53 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -261,13 +261,12 @@ static int mmc_read_ext_csd(struct mmc_card *card, u8 *ext_csd)
 		}
 	}
 
+	/*
+	 * The EXT_CSD format is meant to be forward compatible. As long
+	 * as CSD_STRUCTURE does not change, all values for EXT_CSD_REV
+	 * are authorized, see JEDEC JESD84-B50 section B.8.
+	 */
 	card->ext_csd.rev = ext_csd[EXT_CSD_REV];
-	if (card->ext_csd.rev > 6) {
-		pr_err("%s: unrecognised EXT_CSD revision %d\n",
-			mmc_hostname(card->host), card->ext_csd.rev);
-		err = -EINVAL;
-		goto out;
-	}
 
 	card->ext_csd.raw_sectors[0] = ext_csd[EXT_CSD_SEC_CNT + 0];
 	card->ext_csd.raw_sectors[1] = ext_csd[EXT_CSD_SEC_CNT + 1];
@@ -1060,6 +1059,8 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
 	if (mmc_card_highspeed(card) || mmc_card_hs200(card)) {
 		if (max_dtr > card->ext_csd.hs_max_dtr)
 			max_dtr = card->ext_csd.hs_max_dtr;
+		if (mmc_card_highspeed(card) && (max_dtr > 52000000))
+			max_dtr = 52000000;
 	} else if (max_dtr > card->csd.max_dtr) {
 		max_dtr = card->csd.max_dtr;
 	}
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 3e7e26d..835ec3a 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_MMC_SDHCI_DOVE)		+= sdhci-dove.o
 obj-$(CONFIG_MMC_SDHCI_TEGRA)		+= sdhci-tegra.o
 obj-$(CONFIG_MMC_SDHCI_OF_ESDHC)	+= sdhci-of-esdhc.o
 obj-$(CONFIG_MMC_SDHCI_OF_HLWD)		+= sdhci-of-hlwd.o
+obj-$(CONFIG_BRCM_SDIO)			+= sdhci-brcmstb.o
 
 ifeq ($(CONFIG_CB710_DEBUG),y)
 	CFLAGS-cb710-mmc	+= -DDEBUG
diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c
new file mode 100644
index 0000000..0f15423
--- /dev/null
+++ b/drivers/mmc/host/sdhci-brcmstb.c
@@ -0,0 +1,298 @@
+/*
+ * sdhci-brcmstb.c Support for SDHCI on Broadcom SoC's
+ *
+ * Author: Al Cooper <acooper@broadcom.com>
+ * Based on sdhci-dove.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/io.h>
+#include <linux/mmc/host.h>
+#include <linux/module.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#include "sdhci-pltfm.h"
+#include "sdhci-brcmstb.h"
+
+#define SDIO_CFG_REG(x, y)	(x + BCHP_SDIO_0_CFG_##y - \
+				 BCHP_SDIO_0_CFG_REG_START)
+#define SDIO_CFG_SET(base, reg, mask) do {				\
+		BDEV_SET(SDIO_CFG_REG(base, reg),			\
+			 BCHP_SDIO_0_CFG_##reg##_##mask##_MASK);	\
+	} while (0)
+#define SDIO_CFG_UNSET(base, reg, mask) do {				\
+		BDEV_UNSET(SDIO_CFG_REG(base, reg),			\
+			   BCHP_SDIO_0_CFG_##reg##_##mask##_MASK);	\
+	} while (0)
+#define SDIO_CFG_FIELD(base, reg, field, val) do {			\
+		BDEV_UNSET(SDIO_CFG_REG(base, reg),			\
+			   BCHP_SDIO_0_CFG_##reg##_##field##_MASK);	\
+		BDEV_SET(SDIO_CFG_REG(base, reg),			\
+		 val << BCHP_SDIO_0_CFG_##reg##_##field##_SHIFT);	\
+	} while (0)
+
+#define SDHCI_OVERRIDE_OPTIONS_NONE		0x00000000
+#define SDHCI_OVERRIDE_OPTIONS_UHS_SDR50	0x00000001
+#define SDHCI_OVERRIDE_OPTIONS_TUNING		0x00000002
+
+#define CAP0_SHIFT(field) BCHP_SDIO_0_CFG_CAP_REG0_##field##_SHIFT
+#define CAP1_SHIFT(field) BCHP_SDIO_0_CFG_CAP_REG1_##field##_SHIFT
+
+static inline void sdhci_override_caps(uintptr_t cfg_base, int base_clock,
+				       int timeout_clock, int options)
+{
+	uint32_t val;
+
+	/* Set default for every field with all options off */
+	val = (0 << CAP0_SHIFT(DDR50_SUPPORT) |			\
+	       0 << CAP0_SHIFT(SD104_SUPPORT) |			\
+	       0 << CAP0_SHIFT(SDR50) |				\
+	       0 << CAP0_SHIFT(SLOT_TYPE) |			\
+	       0 << CAP0_SHIFT(ASYNCH_INT_SUPPORT) |		\
+	       0 << CAP0_SHIFT(64B_SYS_BUS_SUPPORT) |		\
+	       0 << CAP0_SHIFT(1_8V_SUPPORT) |			\
+	       0 << CAP0_SHIFT(3_0V_SUPPORT) |			\
+	       1 << CAP0_SHIFT(3_3V_SUPPORT) |			\
+	       1 << CAP0_SHIFT(SUSP_RES_SUPPORT) |		\
+	       1 << CAP0_SHIFT(SDMA_SUPPORT) |			\
+	       1 << CAP0_SHIFT(HIGH_SPEED_SUPPORT) |		\
+	       1 << CAP0_SHIFT(ADMA2_SUPPORT) |			\
+	       1 << CAP0_SHIFT(EXTENDED_MEDIA_SUPPORT) |	\
+	       1 << CAP0_SHIFT(MAX_BL) |			\
+	       0 << CAP0_SHIFT(BASE_FREQ) |			\
+	       1 << CAP0_SHIFT(TIMEOUT_CLK_UNIT) |		\
+	       0 << CAP0_SHIFT(TIMEOUT_FREQ));
+
+	val |= (base_clock << CAP0_SHIFT(BASE_FREQ));
+	val |= (timeout_clock << CAP0_SHIFT(TIMEOUT_FREQ));
+	if (options & SDHCI_OVERRIDE_OPTIONS_UHS_SDR50)
+		val |= (1 << CAP0_SHIFT(SDR50)) |
+			(1 << CAP0_SHIFT(1_8V_SUPPORT));
+	BDEV_WR(SDIO_CFG_REG(cfg_base, CAP_REG0), val);
+
+	val = (1 << CAP1_SHIFT(CAP_REG_OVERRIDE) |	\
+	       0 << CAP1_SHIFT(SPI_BLK_MODE) |		\
+	       0 << CAP1_SHIFT(SPI_MODE) |		\
+	       0 << CAP1_SHIFT(CLK_MULT) |		\
+	       0 << CAP1_SHIFT(RETUNING_MODES) |	\
+	       0 << CAP1_SHIFT(USE_TUNING) |		\
+	       0 << CAP1_SHIFT(RETUNING_TIMER) |	\
+	       0 << CAP1_SHIFT(Driver_D_SUPPORT) |	\
+	       0 << CAP1_SHIFT(Driver_C_SUPPORT) |	\
+	       0 << CAP1_SHIFT(Driver_A_SUPPORT));
+	BDEV_WR(SDIO_CFG_REG(cfg_base, CAP_REG1), val);
+}
+
+static int sdhci_brcmstb_config(struct platform_device *pdev)
+{
+	struct resource *iomem;
+	uintptr_t cfg_base;
+
+	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	if (!iomem)
+		return -ENOMEM;
+	cfg_base = iomem->start;
+	if (BDEV_RD(SDIO_CFG_REG(cfg_base, SCRATCH)) & 0x01) {
+		dev_info(&pdev->dev, "Disabled by bootloader\n");
+		return -ENODEV;
+	}
+	dev_info(&pdev->dev, "Enabling controller\n");
+	BDEV_UNSET(SDIO_CFG_REG(cfg_base, SDIO_EMMC_CTRL1), 0xf000);
+	BDEV_UNSET(SDIO_CFG_REG(cfg_base, SDIO_EMMC_CTRL2), 0x00ff);
+
+	/*
+	 * This is broken on all chips and defaults to enabled on
+	 * some chips so disable it.
+	 */
+	SDIO_CFG_UNSET(cfg_base, SDIO_EMMC_CTRL1, SCB_SEQ_EN);
+
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+	/* FRAME_NHW | BUFFER_ABO */
+	BDEV_SET(SDIO_CFG_REG(cfg_base, SDIO_EMMC_CTRL1), 0x3000);
+#else
+	/* WORD_ABO | FRAME_NBO | FRAME_NHW */
+	BDEV_SET(SDIO_CFG_REG(cfg_base, SDIO_EMMC_CTRL1), 0xe000);
+	/* address swap only */
+	BDEV_SET(SDIO_CFG_REG(cfg_base, SDIO_EMMC_CTRL2), 0x0050);
+#endif
+
+#if defined(CONFIG_BCM7231B0) || defined(CONFIG_BCM7346B0)
+	SDIO_CFG_SET(cfg_base, CAP_REG1, CAP_REG_OVERRIDE);
+#elif defined(CONFIG_BCM7344B0)
+	SDIO_CFG_SET(cfg_base, CAP_REG0, HIGH_SPEED_SUPPORT);
+	SDIO_CFG_SET(cfg_base, CAP_REG1, CAP_REG_OVERRIDE);
+#elif defined(CONFIG_BCM7425)
+	/*
+	 * HW7425-1352: Disable TUNING because it's broken.
+	 * Use manual input and output clock delays to work around
+	 * 7425B2 timing issues.
+	 */
+	if (BRCM_CHIP_REV() == 0x12) {
+		/* disable tuning */
+		sdhci_override_caps(cfg_base, 100, 50,
+				    SDHCI_OVERRIDE_OPTIONS_UHS_SDR50);
+
+		/* enable input delay, resolution = 1, value = 8 */
+		SDIO_CFG_FIELD(cfg_base, IP_DLY, IP_TAP_DELAY, 8);
+		SDIO_CFG_FIELD(cfg_base, IP_DLY, IP_DELAY_CTRL, 1);
+		SDIO_CFG_SET(cfg_base, IP_DLY, IP_TAP_EN);
+
+		/* enable output delay */
+		SDIO_CFG_FIELD(cfg_base, OP_DLY, OP_TAP_DELAY, 4);
+		SDIO_CFG_FIELD(cfg_base, OP_DLY, OP_DELAY_CTRL, 3);
+		SDIO_CFG_SET(cfg_base, OP_DLY, OP_TAP_EN);
+
+		/* Use the manual clock delay */
+		SDIO_CFG_FIELD(cfg_base, SD_CLOCK_DELAY, INPUT_CLOCK_DELAY, 8);
+	}
+#elif defined(CONFIG_BCM7563A0)
+	sdhci_override_caps(cfg_base, 50, 50, SDHCI_OVERRIDE_OPTIONS_NONE);
+#elif defined(CONFIG_BCM7584A0)
+	/* enable output delay */
+	SDIO_CFG_FIELD(cfg_base, OP_DLY, OP_TAP_DELAY, 4);
+	SDIO_CFG_FIELD(cfg_base, OP_DLY, OP_DELAY_CTRL, 3);
+	SDIO_CFG_SET(cfg_base, OP_DLY, OP_TAP_EN);
+#endif
+	return 0;
+}
+
+static int sdhci_brcmstb_supported(void)
+{
+	/* Chips with broken SDIO - 7429A0, 7435A0, 7425B0 and 7425B1 */
+	if ((BRCM_CHIP_ID() == 0x7425) &&
+	    ((BRCM_CHIP_REV() == 0x10) || (BRCM_CHIP_REV() == 0x11)))
+		return 0;
+	if ((BRCM_CHIP_ID() == 0x7429) && (BRCM_CHIP_REV() == 0x00))
+		return 0;
+	if ((BRCM_CHIP_ID() == 0x7435) && (BRCM_CHIP_REV() == 0x00))
+		return 0;
+	return 1;
+}
+
+
+static u32 sdhci_brcmstb_readl(struct sdhci_host *host, int reg)
+{
+	return __raw_readl(host->ioaddr + reg);
+}
+
+static void sdhci_brcmstb_writel(struct sdhci_host *host, u32 val, int reg)
+{
+	__raw_writel(val, host->ioaddr + reg);
+}
+
+static u16 sdhci_brcmstb_readw(struct sdhci_host *host, int reg)
+{
+	return __raw_readw(host->ioaddr + reg);
+}
+
+static void sdhci_brcmstb_writew(struct sdhci_host *host, u16 val, int reg)
+{
+#if defined(CONFIG_BCM7425B0)
+	if (reg == SDHCI_HOST_CONTROL2 && BRCM_CHIP_REV() == 0x12) {
+		/* HW7425-1414: I/O voltage uses Power Control Register (29h) */
+		int pow_reg = __raw_readb(host->ioaddr + SDHCI_POWER_CONTROL);
+
+		pow_reg &= ~SDHCI_POWER_330;
+		if (val & SDHCI_CTRL_VDD_180)
+			pow_reg |= SDHCI_POWER_180;
+		else
+			pow_reg |= SDHCI_POWER_330;
+		__raw_writeb(pow_reg, host->ioaddr + SDHCI_POWER_CONTROL);
+	}
+#endif
+	__raw_writew(val, host->ioaddr + reg);
+}
+
+static struct sdhci_ops sdhci_brcmstb_ops = {
+	.read_w		= sdhci_brcmstb_readw,
+	.write_w	= sdhci_brcmstb_writew,
+	.read_l		= sdhci_brcmstb_readl,
+	.write_l	= sdhci_brcmstb_writel,
+};
+
+static struct sdhci_pltfm_data sdhci_brcmstb_pltfm_data = {
+	.ops	= &sdhci_brcmstb_ops,
+	.quirks2 = SDHCI_QUIRK2_NO_1_8_V
+};
+
+
+static int __devinit sdhci_brcmstb_probe(struct platform_device *pdev)
+{
+	int res;
+	struct sdhci_brcmstb_pdata *pdata = pdev->dev.platform_data;
+
+	if (!sdhci_brcmstb_supported()) {
+		dev_info(&pdev->dev, "Disabled, unsupported chip revision\n");
+		return -ENODEV;
+	}
+	if (sdhci_brcmstb_config(pdev) != 0)
+		return -ENODEV;
+	res = sdhci_pltfm_register(pdev, &sdhci_brcmstb_pltfm_data);
+	if (!res) {
+		struct sdhci_host *host = platform_get_drvdata(pdev);
+		host->mmc->caps |= pdata->caps;
+		host->mmc->caps2 |= pdata->caps2;
+	}
+	return res;
+}
+
+static int __devexit sdhci_brcmstb_remove(struct platform_device *pdev)
+{
+	return sdhci_pltfm_unregister(pdev);
+}
+
+#ifdef CONFIG_PM
+static int sdhci_brcmstb_suspend(struct device *dev)
+{
+	int ret = 0;
+
+	if (sdhci_pltfm_pmops.suspend)
+		ret = sdhci_pltfm_pmops.suspend(dev);
+	return ret;
+}
+
+static int sdhci_brcmstb_resume(struct device *dev)
+{
+	int ret = 0;
+
+	sdhci_brcmstb_config(to_platform_device(dev));
+	if (sdhci_pltfm_pmops.resume)
+		ret = sdhci_pltfm_pmops.resume(dev);
+	return ret;
+}
+
+const struct dev_pm_ops sdhci_brcmstb_pmops = {
+	.suspend	= sdhci_brcmstb_suspend,
+	.resume		= sdhci_brcmstb_resume,
+};
+#endif
+
+static struct platform_driver sdhci_brcmstb_driver = {
+	.driver		= {
+		.name	= "sdhci-brcmstb",
+		.owner	= THIS_MODULE,
+#ifdef CONFIG_PM
+		.pm		= &sdhci_brcmstb_pmops,
+#endif
+	},
+	.probe		= sdhci_brcmstb_probe,
+	.remove		= __devexit_p(sdhci_brcmstb_remove),
+};
+
+module_platform_driver(sdhci_brcmstb_driver);
+
+MODULE_DESCRIPTION("SDHCI driver for Broadcom");
+MODULE_AUTHOR("Al Cooper <acooper@broadcom.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mmc/host/sdhci-brcmstb.h b/drivers/mmc/host/sdhci-brcmstb.h
new file mode 100644
index 0000000..7867e73
--- /dev/null
+++ b/drivers/mmc/host/sdhci-brcmstb.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+struct sdhci_brcmstb_pdata {
+	unsigned long caps;
+	unsigned long caps2;
+};
diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index c5c2a48..bb010da 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -125,8 +125,10 @@ struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev,
 		host->ops = pdata->ops;
 	else
 		host->ops = &sdhci_pltfm_ops;
-	if (pdata)
+	if (pdata) {
 		host->quirks = pdata->quirks;
+		host->quirks2 = pdata->quirks2;
+	}
 	host->irq = platform_get_irq(pdev, 0);
 
 	if (!request_mem_region(iomem->start, resource_size(iomem),
diff --git a/drivers/mmc/host/sdhci-pltfm.h b/drivers/mmc/host/sdhci-pltfm.h
index 37e0e18..283d54a 100644
--- a/drivers/mmc/host/sdhci-pltfm.h
+++ b/drivers/mmc/host/sdhci-pltfm.h
@@ -18,6 +18,7 @@
 struct sdhci_pltfm_data {
 	struct sdhci_ops *ops;
 	unsigned int quirks;
+	unsigned int quirks2;
 };
 
 struct sdhci_pltfm_host {
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 1fe0ca9..39eea6f 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -245,6 +245,18 @@ static void sdhci_init(struct sdhci_host *host, int soft)
 static void sdhci_reinit(struct sdhci_host *host)
 {
 	sdhci_init(host, 0);
+	/*
+	 * Retuning stuffs are affected by different cards inserted and only
+	 * applicable to UHS-I cards. So reset these fields to their initial
+	 * value when card is removed.
+	 */
+	if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
+			host->tuning_mode == SDHCI_TUNING_MODE_1) {
+		del_timer_sync(&host->tuning_timer);
+		host->flags &= ~SDHCI_NEEDS_RETUNING;
+		host->mmc->max_blk_count =
+			(host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
+	}
 	sdhci_enable_card_detection(host);
 }
 
@@ -681,8 +693,8 @@ static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 	}
 
 	if (count >= 0xF) {
-		pr_warning("%s: Too large timeout requested for CMD%d!\n",
-		       mmc_hostname(host->mmc), cmd->opcode);
+		DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
+		    mmc_hostname(host->mmc), count, cmd->opcode);
 		count = 0xE;
 	}
 
@@ -2791,6 +2803,10 @@ int sdhci_add_host(struct sdhci_host *host)
 	    mmc_card_is_removable(mmc))
 		mmc->caps |= MMC_CAP_NEEDS_POLL;
 
+	if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
+		caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
+		       SDHCI_SUPPORT_DDR50);
+
 	/* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
 	if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 		       SDHCI_SUPPORT_DDR50))
diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c
index d02592e..fbd3f55 100644
--- a/drivers/mtd/chips/cfi_cmdset_0002.c
+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
@@ -1691,6 +1691,10 @@ static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
 	int ret = 0;
 	int chipnum;
 
+	*retlen = 0;
+	if (!len)
+		return 0;
+
 	chipnum = to >> cfi->chipshift;
 	ofs = to - (chipnum << cfi->chipshift);
 	chipstart = cfi->chips[chipnum].start;
diff --git a/drivers/mtd/devices/block2mtd.c b/drivers/mtd/devices/block2mtd.c
index 7d7000d..db185e0 100644
--- a/drivers/mtd/devices/block2mtd.c
+++ b/drivers/mtd/devices/block2mtd.c
@@ -21,6 +21,7 @@
 #define ERROR(fmt, args...) printk(KERN_ERR "block2mtd: " fmt "\n" , ## args)
 #define INFO(fmt, args...) printk(KERN_INFO "block2mtd: " fmt "\n" , ## args)
 
+extern int del_mtd_device(struct mtd_info *mtd);
 
 /* Info for the block device */
 struct block2mtd_dev {
@@ -64,6 +65,7 @@ static int _block2mtd_erase(struct block2mtd_dev *dev, loff_t to, size_t len)
 				memset(page_address(page), 0xff, PAGE_SIZE);
 				set_page_dirty(page);
 				unlock_page(page);
+				balance_dirty_pages_ratelimited(mapping);
 				break;
 			}
 
@@ -158,6 +160,7 @@ static int _block2mtd_write(struct block2mtd_dev *dev, const u_char *buf,
 			memcpy(page_address(page) + offset, buf, cpylen);
 			set_page_dirty(page);
 			unlock_page(page);
+			balance_dirty_pages_ratelimited(mapping);
 		}
 		page_cache_release(page);
 
@@ -214,7 +217,7 @@ static void block2mtd_free_device(struct block2mtd_dev *dev)
 
 
 /* FIXME: ensure that mtd->size % erase_size == 0 */
-static struct block2mtd_dev *add_device(char *devname, int erase_size)
+static struct block2mtd_dev *add_device(char *devname, int erase_size, int write_size)
 {
 	const fmode_t mode = FMODE_READ | FMODE_WRITE | FMODE_EXCL;
 	struct block_device *bdev;
@@ -265,7 +268,7 @@ static struct block2mtd_dev *add_device(char *devname, int erase_size)
 
 	dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK;
 	dev->mtd.erasesize = erase_size;
-	dev->mtd.writesize = 1;
+	dev->mtd.writesize = write_size;
 	dev->mtd.writebufsize = PAGE_SIZE;
 	dev->mtd.type = MTD_RAM;
 	dev->mtd.flags = MTD_CAP_RAM;
@@ -281,9 +284,10 @@ static struct block2mtd_dev *add_device(char *devname, int erase_size)
 		goto devinit_err;
 	}
 	list_add(&dev->list, &blkmtd_device_list);
-	INFO("mtd%d: [%s] erase_size = %dKiB [%d]", dev->mtd.index,
+	INFO("mtd%d: [%s] erase_size = %dKiB [%d] write_size = %dKiB [%d]", dev->mtd.index,
 			dev->mtd.name + strlen("block2mtd: "),
-			dev->mtd.erasesize >> 10, dev->mtd.erasesize);
+			dev->mtd.erasesize >> 10, dev->mtd.erasesize,
+			dev->mtd.writesize >> 10, dev->mtd.writesize);
 	return dev;
 
 devinit_err:
@@ -350,17 +354,43 @@ static inline void kill_final_newline(char *str)
 
 #ifndef MODULE
 static int block2mtd_init_called = 0;
-static char block2mtd_paramline[80 + 12]; /* 80 for device, 12 for erase size */
+static char block2mtd_paramline[80 + 12 + 12]; /* 80 for device, 12 for erase size, 12 for writesize */
 #endif
 
+static void remove_device_by_name(const char *name)
+{
+	struct list_head *pos, *next;
+	int name_offset = strlen("block2mtd: ");
+
+	list_for_each_safe(pos, next, &blkmtd_device_list) {
+		struct block2mtd_dev *dev = list_entry(pos, typeof(*dev), list);
+		if (!strcmp(name, dev->mtd.name + name_offset)) {
+			int err;
+			block2mtd_sync(&dev->mtd);
+			err = del_mtd_device(&dev->mtd);
+			if (err == 0) {
+				INFO("mtd%d: [%s] removed",
+						dev->mtd.index, name);
+				list_del(&dev->list);
+				block2mtd_free_device(dev);
+			} else
+				ERROR("mtd%d: [%s] cannot remove: %d",
+						dev->mtd.index, name, err);
+
+			return;
+		}
+	}
+	ERROR("no such device: %s", name);
+}
 
 static int block2mtd_setup2(const char *val)
 {
-	char buf[80 + 12]; /* 80 for device, 12 for erase size */
+	char buf[80 + 12 + 12]; /* 80 for device, 12 for erase size, 12 for writesize */
 	char *str = buf;
-	char *token[2];
+	char *token[3];
 	char *name;
 	size_t erase_size = PAGE_SIZE;
+	size_t write_size = 1;
 	int i, ret;
 
 	if (strnlen(val, sizeof(buf)) >= sizeof(buf))
@@ -369,7 +399,7 @@ static int block2mtd_setup2(const char *val)
 	strcpy(str, val);
 	kill_final_newline(str);
 
-	for (i = 0; i < 2; i++)
+	for (i = 0; i < 3; i++)
 		token[i] = strsep(&str, ",");
 
 	if (str)
@@ -383,13 +413,23 @@ static int block2mtd_setup2(const char *val)
 		parse_err("device name too long");
 
 	if (token[1]) {
+		if (!strcmp("remove", token[1])) {
+			remove_device_by_name(name);
+			return 0;
+		}
 		ret = parse_num(&erase_size, token[1]);
 		if (ret) {
 			parse_err("illegal erase size");
 		}
 	}
+	if (token[2]) {
+		ret = parse_num(&write_size, token[2]);
+		if (ret) {
+			parse_err("illegal write size");
+		}
+	}
 
-	add_device(name, erase_size);
+	add_device(name, erase_size, write_size);
 
 	return 0;
 }
@@ -423,7 +463,7 @@ static int block2mtd_setup(const char *val, struct kernel_param *kp)
 
 
 module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200);
-MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=<dev>[,<erasesize>]\"");
+MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=<dev>[,<erasesize>,<writesize>]\"");
 
 static int __init block2mtd_init(void)
 {
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 797860e..113922f 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -638,6 +638,7 @@ static const struct spi_device_id m25p_ids[] = {
 	{ "en25p32", INFO(0x1c2016, 0, 64 * 1024,  64, 0) },
 	{ "en25q32b", INFO(0x1c3016, 0, 64 * 1024,  64, 0) },
 	{ "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
+	{ "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, SECT_4K) },
 
 	/* Intel/Numonyx -- xxxs33b */
 	{ "160s33b",  INFO(0x898911, 0, 64 * 1024,  32, 0) },
@@ -728,6 +729,7 @@ static const struct spi_device_id m25p_ids[] = {
 	{ "w25q32", INFO(0xef4016, 0, 64 * 1024,  64, SECT_4K) },
 	{ "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
 	{ "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
+	{ "w25q128bv", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
 
 	/* Catalyst / On Semiconductor -- non-JEDEC */
 	{ "cat25c11", CAT25_INFO(  16, 8, 16, 1) },
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index d4b4d87..7a65e03 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_MTD_NAND_ECC)		+= nand_ecc.o
 obj-$(CONFIG_MTD_NAND_BCH)		+= nand_bch.o
 obj-$(CONFIG_MTD_NAND_IDS)		+= nand_ids.o
 obj-$(CONFIG_MTD_SM_COMMON) 		+= sm_common.o
+obj-$(CONFIG_MTD_BRCMNAND)		+= brcmstb_nand.o
 
 obj-$(CONFIG_MTD_NAND_CAFE)		+= cafe_nand.o
 obj-$(CONFIG_MTD_NAND_SPIA)		+= spia.o
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 2165576..ab13400 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -324,9 +324,10 @@ static int atmel_nand_calculate(struct mtd_info *mtd,
  * mtd:        mtd info structure
  * chip:       nand chip info structure
  * buf:        buffer to store read data
+ * oob_required:    caller expects OOB data read to chip->oob_poi
  */
-static int atmel_nand_read_page(struct mtd_info *mtd,
-		struct nand_chip *chip, uint8_t *buf, int page)
+static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
+				uint8_t *buf, int oob_required, int page)
 {
 	int eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c
index 73abbc3..9f609d2 100644
--- a/drivers/mtd/nand/au1550nd.c
+++ b/drivers/mtd/nand/au1550nd.c
@@ -508,8 +508,6 @@ static int __devinit au1550nd_probe(struct platform_device *pdev)
 	this->chip_delay = 30;
 	this->ecc.mode = NAND_ECC_SOFT;
 
-	this->options = NAND_NO_AUTOINCR;
-
 	if (pd->devwidth)
 		this->options |= NAND_BUSWIDTH_16;
 
diff --git a/drivers/mtd/nand/bcm_umi_bch.c b/drivers/mtd/nand/bcm_umi_bch.c
index a930666..ee6669d 100644
--- a/drivers/mtd/nand/bcm_umi_bch.c
+++ b/drivers/mtd/nand/bcm_umi_bch.c
@@ -22,9 +22,9 @@
 
 /* ---- Private Function Prototypes -------------------------------------- */
 static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd,
-	struct nand_chip *chip, uint8_t *buf, int page);
+	struct nand_chip *chip, uint8_t *buf, int oob_required, int page);
 static void bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd,
-	struct nand_chip *chip, const uint8_t *buf);
+	struct nand_chip *chip, const uint8_t *buf, int oob_required);
 
 /* ---- Private Variables ------------------------------------------------ */
 
@@ -103,11 +103,12 @@ static struct nand_ecclayout nand_hw_eccoob_4096 = {
 *  @mtd:	mtd info structure
 *  @chip:	nand chip info structure
 *  @buf:	buffer to store read data
+*  @oob_required:	caller expects OOB data read to chip->oob_poi
 *
 ***************************************************************************/
 static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd,
 				       struct nand_chip *chip, uint8_t * buf,
-						 int page)
+				       int oob_required, int page)
 {
 	int sectorIdx = 0;
 	int eccsize = chip->ecc.size;
@@ -188,10 +189,11 @@ static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd,
 *  @mtd:	mtd info structure
 *  @chip:	nand chip info structure
 *  @buf:	data buffer
+*  @oob_required:	must write chip->oob_poi to OOB
 *
 ***************************************************************************/
 static void bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd,
-	struct nand_chip *chip, const uint8_t *buf)
+	struct nand_chip *chip, const uint8_t *buf, int oob_required)
 {
 	int sectorIdx = 0;
 	int eccsize = chip->ecc.size;
diff --git a/drivers/mtd/nand/bcm_umi_nand.c b/drivers/mtd/nand/bcm_umi_nand.c
index 6908cdd..6d836d2 100644
--- a/drivers/mtd/nand/bcm_umi_nand.c
+++ b/drivers/mtd/nand/bcm_umi_nand.c
@@ -341,7 +341,7 @@ static int bcm_umi_nand_verify_buf(struct mtd_info *mtd, const u_char * buf,
 	 * for MLC parts which may have permanently stuck bits.
 	 */
 	struct nand_chip *chip = mtd->priv;
-	int ret = chip->ecc.read_page(mtd, chip, readbackbuf, 0);
+	int ret = chip->ecc.read_page(mtd, chip, readbackbuf, 0, 0);
 	if (ret < 0)
 		return -EFAULT;
 	else {
diff --git a/drivers/mtd/nand/bf5xx_nand.c b/drivers/mtd/nand/bf5xx_nand.c
index d7b86b9..3f1c185 100644
--- a/drivers/mtd/nand/bf5xx_nand.c
+++ b/drivers/mtd/nand/bf5xx_nand.c
@@ -558,7 +558,7 @@ static void bf5xx_nand_dma_write_buf(struct mtd_info *mtd,
 }
 
 static int bf5xx_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
-		uint8_t *buf, int page)
+		uint8_t *buf, int oob_required, int page)
 {
 	bf5xx_nand_read_buf(mtd, buf, mtd->writesize);
 	bf5xx_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
@@ -567,7 +567,7 @@ static int bf5xx_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip
 }
 
 static void bf5xx_nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
-		const uint8_t *buf)
+		const uint8_t *buf, int oob_required)
 {
 	bf5xx_nand_write_buf(mtd, buf, mtd->writesize);
 	bf5xx_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
diff --git a/drivers/mtd/nand/brcmstb_nand.c b/drivers/mtd/nand/brcmstb_nand.c
new file mode 100644
index 0000000..7e91803
--- /dev/null
+++ b/drivers/mtd/nand/brcmstb_nand.c
@@ -0,0 +1,2000 @@
+/*
+ * Copyright (C) 2010 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/completion.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/dma-mapping.h>
+#include <linux/ioport.h>
+#include <linux/bug.h>
+#include <linux/kernel.h>
+#include <linux/bitops.h>
+#include <linux/mm.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+
+#include <linux/brcmstb/brcmstb.h>
+
+/*
+ * SWLINUX-1818: this flag controls if WP stays on between erase/write
+ * commands to mitigate flash corruption due to power glitches. Values:
+ * 0: NAND_WP is not used or not available
+ * 1: NAND_WP is set by default, cleared for erase/write operations
+ * 2: NAND_WP is always cleared
+ */
+static int wp_on = 1;
+module_param(wp_on, int, 0444);
+
+/***********************************************************************
+ * Definitions
+ ***********************************************************************/
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)
+#define DBG(args...)		pr_debug(args)
+#else
+#define DBG(args...)		DEBUG(MTD_DEBUG_LEVEL3, args)
+#endif
+
+#define DRV_NAME		"brcmstb_nand"
+#define CONTROLLER_VER		(10 * CONFIG_BRCMNAND_MAJOR_VERS + \
+		CONFIG_BRCMNAND_MINOR_VERS)
+
+#define CMD_NULL		0x00
+#define CMD_PAGE_READ		0x01
+#define CMD_SPARE_AREA_READ	0x02
+#define CMD_STATUS_READ		0x03
+#define CMD_PROGRAM_PAGE	0x04
+#define CMD_PROGRAM_SPARE_AREA	0x05
+#define CMD_COPY_BACK		0x06
+#define CMD_DEVICE_ID_READ	0x07
+#define CMD_BLOCK_ERASE		0x08
+#define CMD_FLASH_RESET		0x09
+#define CMD_BLOCKS_LOCK		0x0a
+#define CMD_BLOCKS_LOCK_DOWN	0x0b
+#define CMD_BLOCKS_UNLOCK	0x0c
+#define CMD_READ_BLOCKS_LOCK_STATUS	0x0d
+
+#if CONTROLLER_VER >= 40
+#define CMD_PARAMETER_READ	0x0e
+#define CMD_PARAMETER_CHANGE_COL	0x0f
+#define CMD_LOW_LEVEL_OP	0x10
+#endif
+
+struct brcm_nand_dma_desc {
+	u32 next_desc;
+	u32 next_desc_ext;
+	u32 cmd_irq;
+	u32 dram_addr;
+	u32 dram_addr_ext;
+	u32 tfr_len;
+	u32 total_len;
+	u32 flash_addr;
+	u32 flash_addr_ext;
+	u32 cs;
+	u32 pad2[5];
+	u32 status_valid;
+} __packed;
+
+/* 512B flash cache in the NAND controller HW */
+#define FC_SHIFT		9U
+#define FC_BYTES		512U
+#define FC_WORDS		(FC_BYTES >> 2)
+#define FC(x)			(BCHP_NAND_FLASH_CACHEi_ARRAY_BASE + ((x) << 2))
+
+#if CONTROLLER_VER >= 60
+#define MAX_CONTROLLER_OOB	64
+#define OFS_10_RD		BCHP_NAND_SPARE_AREA_READ_OFS_10
+#define OFS_10_WR		BCHP_NAND_SPARE_AREA_WRITE_OFS_10
+#elif CONTROLLER_VER >= 50
+#define MAX_CONTROLLER_OOB	32
+#define OFS_10_RD		BCHP_NAND_SPARE_AREA_READ_OFS_10
+#define OFS_10_WR		BCHP_NAND_SPARE_AREA_WRITE_OFS_10
+#else
+#define MAX_CONTROLLER_OOB	16
+#define OFS_10_RD		-1
+#define OFS_10_WR		-1
+#endif
+
+#define EDU_CMD_WRITE		0x00
+#define EDU_CMD_READ		0x01
+
+#ifdef CONFIG_BRCM_HAS_EDU
+#define EDU_VA_OK(x)		(!is_vmalloc_addr((const void *)(x)))
+#else
+#define EDU_VA_OK(x)		0
+#endif
+
+#ifdef CONFIG_BRCM_HAS_FLASH_DMA
+#define DMA_VA_OK(x)		(!is_vmalloc_addr((const void *)(x)))
+#else
+#define DMA_VA_OK(x)		0
+#endif
+
+#if CONTROLLER_VER >= 60
+
+#define REG_ACC_CONTROL(cs) (BCHP_NAND_ACC_CONTROL_CS0 + ((cs) << 4))
+
+#define REG_CONFIG(cs) (BCHP_NAND_CONFIG_CS0 + ((cs) << 4))
+
+#define REG_TIMING_1(cs) (BCHP_NAND_TIMING_1_CS0 + ((cs) << 4))
+#define REG_TIMING_2(cs) (BCHP_NAND_TIMING_2_CS0 + ((cs) << 4))
+
+#define CORR_ERROR_COUNT (BDEV_RD(BCHP_NAND_CORR_ERROR_COUNT))
+#define UNCORR_ERROR_COUNT (BDEV_RD(BCHP_NAND_UNCORR_ERROR_COUNT))
+
+#define WR_CORR_THRESH(cs, val) do { \
+	u32 contents = BDEV_RD(BCHP_NAND_CORR_STAT_THRESHOLD); \
+	u32 shift = BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_SHIFT * (cs); \
+	contents &= ~(BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_MASK \
+			<< shift); \
+	contents |= ((val) & BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_MASK) \
+			<< shift; \
+	BDEV_WR(BCHP_NAND_CORR_STAT_THRESHOLD, contents); \
+	} while (0);
+
+#else /* CONTROLLER_VER < 60 */
+
+#define REG_ACC_CONTROL(cs) \
+	((cs) == 0 ? BCHP_NAND_ACC_CONTROL : \
+	 (BCHP_NAND_ACC_CONTROL_CS1 + (((cs) - 1) << 4)))
+
+#define REG_CONFIG(cs) \
+	((cs) == 0 ? BCHP_NAND_CONFIG : \
+	 (BCHP_NAND_CONFIG_CS1 + (((cs) - 1) << 4)))
+
+#define REG_TIMING_1(cs) \
+	((cs) == 0 ? BCHP_NAND_TIMING_1 : \
+	 (BCHP_NAND_TIMING_1_CS1 + (((cs) - 1) << 4)))
+#define REG_TIMING_2(cs) \
+	((cs) == 0 ? BCHP_NAND_TIMING_2 : \
+	 (BCHP_NAND_TIMING_2_CS1 + (((cs) - 1) << 4)))
+
+#define CORR_ERROR_COUNT (1)
+#define UNCORR_ERROR_COUNT (1)
+
+#define WR_CORR_THRESH(cs, val) do { \
+	BDEV_WR(BCHP_NAND_CORR_STAT_THRESHOLD, \
+		((val) & BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_MASK) \
+		    << BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_SHIFT); \
+	} while (0);
+
+#endif /* CONTROLLER_VER < 60 */
+
+#define WR_CONFIG(cs, field, val) do { \
+	u32 reg = REG_CONFIG(cs), contents = BDEV_RD(reg); \
+	contents &= ~(BCHP_NAND_CONFIG_CS1_##field##_MASK); \
+	contents |= (val) << BCHP_NAND_CONFIG_CS1_##field##_SHIFT; \
+	BDEV_WR(reg, contents); \
+	} while (0)
+
+#define RD_CONFIG(cs, field) \
+	((BDEV_RD(REG_CONFIG(cs)) & BCHP_NAND_CONFIG_CS1_##field##_MASK) \
+	 >> BCHP_NAND_CONFIG_CS1_##field##_SHIFT)
+
+#define WR_ACC_CONTROL(cs, field, val) do { \
+	u32 reg = REG_ACC_CONTROL(cs), contents = BDEV_RD(reg); \
+	contents &= ~(BCHP_NAND_ACC_CONTROL_CS1_##field##_MASK); \
+	contents |= (val) << BCHP_NAND_ACC_CONTROL_CS1_##field##_SHIFT; \
+	BDEV_WR(reg, contents); \
+	} while (0)
+
+#define RD_ACC_CONTROL(cs, field) \
+	((BDEV_RD(REG_ACC_CONTROL(cs)) & \
+	BCHP_NAND_ACC_CONTROL_CS1_##field##_MASK) \
+		>> BCHP_NAND_ACC_CONTROL_CS1_##field##_SHIFT)
+
+struct brcmstb_nand_controller {
+	struct nand_hw_control	controller;
+	unsigned int		irq;
+	int			cmd_pending;
+	struct completion	done;
+
+	struct brcm_nand_dma_desc *dma_desc;
+	dma_addr_t dma_pa;
+	int dma_count;
+
+#ifdef CONFIG_BRCM_HAS_EDU
+	/* EDU info, per-transaction */
+	int			edu_count;
+	u64			edu_dram_addr;
+	u32			edu_ext_addr;
+	u32			edu_cmd;
+	u32			edu_config;
+	int			sas; /* spare area size, per flash cache */
+	int			sector_size_1k;
+	u8			*oob;
+#endif
+	u32			nand_cs_nand_select;
+	u32			nand_cs_nand_xor;
+	u32			corr_stat_threshold;
+	u32			hif_intr2;
+	u32			flash_dma_mode;
+};
+
+static struct brcmstb_nand_controller ctrl;
+
+struct brcmstb_nand_cfg {
+	u64			device_size;
+	unsigned int		block_size;
+	unsigned int		page_size;
+	unsigned int		spare_area_size;
+	unsigned int		device_width;
+	unsigned int		col_adr_bytes;
+	unsigned int		blk_adr_bytes;
+	unsigned int		ful_adr_bytes;
+	unsigned int		sector_size_1k;
+	unsigned int		ecc_level;
+	/* use for low-power standby/resume only */
+	u32			acc_control;
+	u32			config;
+	u32			timing_1;
+	u32			timing_2;
+};
+
+struct brcmstb_nand_host {
+	u32			buf[FC_WORDS];
+	struct nand_chip	chip;
+	struct mtd_info		mtd;
+	struct platform_device	*pdev;
+	int			cs;
+
+	unsigned int		last_cmd;
+	unsigned int		last_byte;
+	u64			last_addr;
+	struct brcmstb_nand_cfg	hwcfg;
+};
+
+static struct nand_ecclayout brcmstb_nand_dummy_layout = {
+	.eccbytes		= 16,
+	.eccpos			= { 0, 1, 2, 3, 4, 5, 6, 7,
+				    8, 9, 10, 11, 12, 13, 14, 15 },
+};
+
+struct brcmstb_nand_exception {
+	const char		*name;
+	int			id[7];
+	int			idlen; /* usable */
+	unsigned int		chipsize; /* MB */
+	unsigned int		writesize; /* B */
+	unsigned int		erasesize; /* B */
+	unsigned int		oobsize; /* B per page */
+	int			chipoptions;
+	int			badblockpos;
+};
+
+static struct brcmstb_nand_exception brcmstb_exceptions_list[] = {
+	{"Micron MT29F16G08ABABA",
+		{0x2C, 0x48, 0x00, 0x26, 0x89, 0x00, 0x00},
+		5, 0x00800, 4096, 0x080000, 224},
+	{"Micron MT29F16G08CBABA",
+		{0x2C, 0x48, 0x04, 0x46, 0x85, 0x00, 0x00},
+		5, 0x00800, 4096, 0x100000, 224},
+	{"Micron MT29F16G08MAA",
+		{0x2C, 0xD5, 0x94, 0x3E, 0x74, 0x00, 0x00},
+		5, 0x00800, 4096, 0x080000, 218},
+	{"Micron MT29F32G08CBACA",
+		{0x2C, 0x68, 0x04, 0x4A, 0xA9, 0x00, 0x00},
+		5, 0x01000, 4096, 0x100000, 224},
+	{"Micron MT29F64G08CBAAA",
+		{0x2C, 0x88, 0x04, 0x4B, 0xA9, 0x00, 0x00},
+		5, 0x02000, 8192, 0x200000, 448},
+	{"Micron MT29F256G08CJAAA",
+		{0x2C, 0xA8, 0x05, 0xCB, 0xA9, 0x00, 0x00},
+		5, 0x08000, 8192, 0x200000, 448},
+	{NULL,}
+};
+
+/* Used for running nand_scan_ident without the built-in heuristics */
+static struct nand_flash_dev brcmstb_empty_flash_table[] = {
+	{NULL,}
+};
+
+/***********************************************************************
+ * Internal support functions
+ ***********************************************************************/
+
+static inline bool is_hamming_ecc(struct brcmstb_nand_cfg *cfg)
+{
+	return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
+		cfg->ecc_level == 15;
+}
+
+/*
+ * Returns a nand_ecclayout strucutre for the given layout/configuration.
+ * Returns NULL on failure.
+ */
+static struct nand_ecclayout *brcmstb_nand_create_layout(int ecc_level,
+		struct brcmstb_nand_cfg *cfg)
+{
+	int i, j;
+	struct nand_ecclayout *layout;
+	int req;
+	int sectors;
+	int sas;
+	int idx1, idx2;
+
+	layout = kzalloc(sizeof(*layout), GFP_KERNEL);
+	if (!layout) {
+		pr_err("%s: can't allocate memory\n", __func__);
+		return NULL;
+	}
+
+	sectors = cfg->page_size / (512 << cfg->sector_size_1k);
+	sas = cfg->spare_area_size << cfg->sector_size_1k;
+
+	/* Hamming */
+	if (is_hamming_ecc(cfg)) {
+		for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
+			/* First sector of each page may have BBI */
+			if (i == 0) {
+				layout->oobfree[idx2].offset = i * sas + 1;
+				/* Small-page NAND use byte 6 for BBI */
+				if (cfg->page_size == 512)
+					layout->oobfree[idx2].offset--;
+				layout->oobfree[idx2].length = 5;
+			} else {
+				layout->oobfree[idx2].offset = i * sas;
+				layout->oobfree[idx2].length = 6;
+			}
+			idx2++;
+			layout->eccpos[idx1++] = i * sas + 6;
+			layout->eccpos[idx1++] = i * sas + 7;
+			layout->eccpos[idx1++] = i * sas + 8;
+			layout->oobfree[idx2].offset = i * sas + 9;
+			layout->oobfree[idx2].length = 7;
+			idx2++;
+			/* Leave zero-terminated entry for OOBFREE */
+			if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
+				    idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
+				break;
+		}
+		goto out;
+	}
+
+	/*
+	 * CONTROLLER_VERSION:
+	 *   < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
+	 *  >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)  [see SWLINUX-2038]
+	 * But we will just be conservative.
+	 */
+	req = (ecc_level * 14 + 7) / 8;
+	if (req >= sas) {
+		pr_info("%s: ECC too large for OOB, using dummy layout\n",
+			__func__);
+		memcpy(layout, &brcmstb_nand_dummy_layout, sizeof(*layout));
+		return layout;
+	}
+
+	DBG("OOBLAYOUT: sas=%d  req=%d  sectors=%d\n", sas, req, sectors);
+
+	layout->eccbytes = req * sectors;
+	for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
+		for (j = sas - req; j < sas && idx1 <
+				MTD_MAX_ECCPOS_ENTRIES_LARGE; j++, idx1++)
+			layout->eccpos[idx1] = i * sas + j;
+
+		/* First sector of each page may have BBI */
+		if (i == 0) {
+			if (cfg->page_size == 512 && (sas - req >= 6)) {
+				/* Small-page NAND use byte 6 for BBI */
+				layout->oobfree[idx2].offset = 0;
+				layout->oobfree[idx2].length = 5;
+				idx2++;
+				if (sas - req > 6) {
+					layout->oobfree[idx2].offset = 6;
+					layout->oobfree[idx2].length =
+						sas - req - 6;
+					idx2++;
+				}
+			} else if (sas > req + 1) {
+				layout->oobfree[idx2].offset = i * sas + 1;
+				layout->oobfree[idx2].length = sas - req - 1;
+				idx2++;
+			}
+		} else if (sas > req) {
+			layout->oobfree[idx2].offset = i * sas;
+			layout->oobfree[idx2].length = sas - req;
+			idx2++;
+		}
+		/* Leave zero-terminated entry for OOBFREE */
+		if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
+				idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
+			break;
+	}
+out:
+	/* Sum available OOB */
+	for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE; i++)
+		layout->oobavail += layout->oobfree[i].length;
+	return layout;
+}
+
+static struct nand_ecclayout *brcmstb_choose_ecc_layout(
+		struct brcmstb_nand_host *host)
+{
+	struct nand_ecclayout *layout;
+	struct brcmstb_nand_cfg *p = &host->hwcfg;
+	unsigned int ecc_level = p->ecc_level;
+
+	if (p->sector_size_1k)
+		ecc_level <<= 1;
+
+	layout = brcmstb_nand_create_layout(ecc_level, p);
+	if (!layout) {
+		dev_err(&host->pdev->dev,
+				"no proper ecc_layout for this NAND cfg\n");
+		return NULL;
+	}
+
+	return layout;
+}
+
+static void brcmstb_nand_wp(struct mtd_info *mtd, int wp)
+{
+#ifdef BCHP_NAND_CS_NAND_SELECT_NAND_WP_MASK
+	if (wp_on == 1) {
+		static int old_wp = -1;
+		if (old_wp != wp) {
+			DBG("%s: WP %s\n", __func__, wp ? "on" : "off");
+			old_wp = wp;
+		}
+		BDEV_WR_F_RB(NAND_CS_NAND_SELECT, NAND_WP, wp);
+	}
+#endif
+}
+
+/* Helper functions for reading and writing OOB registers */
+static inline unsigned char oob_reg_read(int offs)
+{
+	if (offs >= MAX_CONTROLLER_OOB)
+		return 0x77;
+
+	if (offs < 16)
+		return BDEV_RD(BCHP_NAND_SPARE_AREA_READ_OFS_0 + (offs & ~0x03))
+			>> (24 - ((offs & 0x03) << 3));
+
+	offs -= 16;
+
+	return BDEV_RD(OFS_10_RD + (offs & ~0x03))
+		>> (24 - ((offs & 0x03) << 3));
+}
+
+static inline void oob_reg_write(int offs, unsigned long data)
+{
+	if (offs >= MAX_CONTROLLER_OOB)
+		return;
+
+	if (offs < 16) {
+		BDEV_WR(BCHP_NAND_SPARE_AREA_WRITE_OFS_0 + (offs & ~0x03),
+				data);
+		return;
+	}
+
+	offs -= 16;
+
+	BDEV_WR(OFS_10_WR + (offs & ~0x03), data);
+}
+
+/*
+ * read_oob_from_regs - read data from OOB registers
+ * @i: sub-page sector index
+ * @oob: buffer to read to
+ * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
+ * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
+ */
+static int read_oob_from_regs(int i, u8 *oob, int sas, int sector_1k)
+{
+	int tbytes = sas << sector_1k;
+	int j;
+
+	/* Adjust OOB values for 1K sector size */
+	if (sector_1k && (i & 0x01))
+		tbytes = max(0, tbytes - MAX_CONTROLLER_OOB);
+	tbytes = min(tbytes, MAX_CONTROLLER_OOB);
+
+	for (j = 0; j < tbytes; j++)
+		oob[j] = oob_reg_read(j);
+	return tbytes;
+}
+
+/*
+ * write_oob_to_regs - write data to OOB registers
+ * @i: sub-page sector index
+ * @oob: buffer to write from
+ * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
+ * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
+ */
+static int write_oob_to_regs(int i, const u8 *oob, int sas, int sector_1k)
+{
+	int tbytes = sas << sector_1k;
+	int j;
+
+	/* Adjust OOB values for 1K sector size */
+	if (sector_1k && (i & 0x01))
+		tbytes = max(0, tbytes - MAX_CONTROLLER_OOB);
+	tbytes = min(tbytes, MAX_CONTROLLER_OOB);
+
+	for (j = 0; j < tbytes; j += 4)
+		oob_reg_write(j,
+				(oob[j + 0] << 24) |
+				(oob[j + 1] << 16) |
+				(oob[j + 2] <<  8) |
+				(oob[j + 3] <<  0));
+	return tbytes;
+}
+
+static irqreturn_t brcmstb_nand_irq(int irq, void *data)
+{
+#ifdef CONFIG_BRCM_HAS_FLASH_DMA
+	if (HIF_TEST_IRQ(FLASH_DMA_DONE)) {
+		HIF_ACK_IRQ(FLASH_DMA_DONE);
+		if (ctrl.dma_count) {
+			ctrl.dma_count = 0;
+			complete(&ctrl.done);
+		}
+		return IRQ_HANDLED;
+	}
+#endif /* CONFIG_BRCM_HAS_FLASH_DMA */
+
+	if (HIF_TEST_IRQ(NAND_CTLRDY)) {
+		HIF_ACK_IRQ(NAND_CTLRDY);
+#ifdef CONFIG_BRCM_HAS_EDU
+		if (ctrl.edu_count) {
+			ctrl.edu_count--;
+			while (!BDEV_RD_F(EDU_DONE, Done))
+				udelay(1);
+			BDEV_WR_F_RB(EDU_DONE, Done, 0);
+		}
+		if (ctrl.edu_count) {
+			ctrl.edu_dram_addr += FC_BYTES;
+			ctrl.edu_ext_addr += FC_BYTES;
+
+			BDEV_WR_RB(BCHP_EDU_DRAM_ADDR, (u32)ctrl.edu_dram_addr);
+			BDEV_WR_RB(BCHP_EDU_EXT_ADDR, ctrl.edu_ext_addr);
+
+			if (ctrl.oob) {
+				if (EDU_CMD_READ == ctrl.edu_cmd) {
+					ctrl.oob += read_oob_from_regs(
+							ctrl.edu_count + 1,
+							ctrl.oob, ctrl.sas,
+							ctrl.sector_size_1k);
+				} else {
+					BDEV_WR_RB(BCHP_NAND_CMD_ADDRESS,
+							ctrl.edu_ext_addr);
+					ctrl.oob += write_oob_to_regs(
+							ctrl.edu_count,
+							ctrl.oob, ctrl.sas,
+							ctrl.sector_size_1k);
+				}
+			}
+
+			mb();
+			BDEV_WR_RB(BCHP_EDU_CMD, ctrl.edu_cmd);
+
+			return IRQ_HANDLED;
+		}
+#endif
+		complete(&ctrl.done);
+		return IRQ_HANDLED;
+	}
+	return IRQ_NONE;
+}
+
+static void brcmstb_nand_send_cmd(int cmd)
+{
+	DBG("%s: native cmd %d addr_lo 0x%lx\n", __func__, cmd,
+		BDEV_RD(BCHP_NAND_CMD_ADDRESS));
+	BUG_ON(ctrl.cmd_pending != 0);
+	ctrl.cmd_pending = cmd;
+	mb();
+	BDEV_WR(BCHP_NAND_CMD_START, cmd << BCHP_NAND_CMD_START_OPCODE_SHIFT);
+}
+
+/***********************************************************************
+ * NAND MTD API: read/program/erase
+ ***********************************************************************/
+
+static void brcmstb_nand_cmd_ctrl(struct mtd_info *mtd, int dat,
+	unsigned int ctrl)
+{
+	/* intentionally left blank */
+}
+
+static int brcmstb_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct brcmstb_nand_host *host = chip->priv;
+
+	DBG("%s: native cmd %d\n", __func__, ctrl.cmd_pending);
+	if (ctrl.cmd_pending &&
+			wait_for_completion_timeout(&ctrl.done, HZ / 10) <= 0) {
+		dev_err(&host->pdev->dev,
+			"timeout waiting for command %u (%ld)\n",
+			host->last_cmd, BDEV_RD(BCHP_NAND_CMD_START) >>
+			BCHP_NAND_CMD_START_OPCODE_SHIFT);
+		dev_err(&host->pdev->dev,
+			"irq status %08lx, intfc status %08lx\n",
+			BDEV_RD(BCHP_HIF_INTR2_CPU_STATUS),
+			BDEV_RD(BCHP_NAND_INTFC_STATUS));
+	}
+	ctrl.cmd_pending = 0;
+	return BDEV_RD_F(NAND_INTFC_STATUS, FLASH_STATUS);
+}
+
+static void brcmstb_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
+	int column, int page_addr)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct brcmstb_nand_host *host = chip->priv;
+	u64 addr = (u64)page_addr << chip->page_shift;
+	int native_cmd = 0;
+
+	if (command == NAND_CMD_READID || command == NAND_CMD_PARAM)
+		addr = (u64)column;
+	/* Avoid propagating a negative, don't-care address */
+	else if (page_addr < 0)
+		addr = 0;
+
+	DBG("%s: cmd 0x%x addr 0x%llx\n", __func__, command,
+		(unsigned long long)addr);
+	host->last_cmd = command;
+	host->last_byte = 0;
+	host->last_addr = addr;
+
+	switch (command) {
+	case NAND_CMD_RESET:
+		native_cmd = CMD_FLASH_RESET;
+		break;
+	case NAND_CMD_STATUS:
+		native_cmd = CMD_STATUS_READ;
+		break;
+	case NAND_CMD_READID:
+		native_cmd = CMD_DEVICE_ID_READ;
+		break;
+	case NAND_CMD_READOOB:
+		native_cmd = CMD_SPARE_AREA_READ;
+		break;
+	case NAND_CMD_ERASE1:
+		native_cmd = CMD_BLOCK_ERASE;
+		brcmstb_nand_wp(mtd, 0);
+		break;
+#if CONTROLLER_VER >= 40
+	case NAND_CMD_PARAM:
+		native_cmd = CMD_PARAMETER_READ;
+		break;
+#endif
+	}
+
+	if (!native_cmd)
+		return;
+
+	BDEV_WR_RB(BCHP_NAND_CMD_EXT_ADDRESS,
+		(host->cs << 16) | ((addr >> 32) & 0xffff));
+	BDEV_WR_RB(BCHP_NAND_CMD_ADDRESS, addr & 0xffffffff);
+
+	brcmstb_nand_send_cmd(native_cmd);
+	brcmstb_nand_waitfunc(mtd, chip);
+
+	/* Re-enable protection is necessary only after erase */
+	if (command == NAND_CMD_ERASE1)
+		brcmstb_nand_wp(mtd, 1);
+}
+
+static uint8_t brcmstb_nand_read_byte(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct brcmstb_nand_host *host = chip->priv;
+	uint8_t ret = 0;
+
+	switch (host->last_cmd) {
+	case NAND_CMD_READID:
+		if (host->last_byte < 4)
+			ret = BDEV_RD(BCHP_NAND_FLASH_DEVICE_ID) >>
+				(24 - (host->last_byte << 3));
+		else if (host->last_byte < 8)
+			ret = BDEV_RD(BCHP_NAND_FLASH_DEVICE_ID_EXT) >>
+				(56 - (host->last_byte << 3));
+		break;
+
+	case NAND_CMD_READOOB:
+		ret = oob_reg_read(host->last_byte);
+		break;
+
+	case NAND_CMD_STATUS:
+		ret = BDEV_RD(BCHP_NAND_INTFC_STATUS) & 0xff;
+		if (wp_on) /* SWLINUX-1818: hide WP status from MTD */
+			ret |= NAND_STATUS_WP;
+		break;
+
+#if CONTROLLER_VER >= 40
+	case NAND_CMD_PARAM:
+		if (host->last_byte < FC_BYTES)
+			ret = BDEV_RD(FC(host->last_byte >> 2)) >>
+				(24 - ((host->last_byte & 0x03) << 3));
+		break;
+#endif
+	}
+
+	DBG("%s: byte = 0x%02x\n", __func__, ret);
+	host->last_byte++;
+
+	return ret;
+}
+
+static void brcmstb_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++, buf++)
+		*buf = brcmstb_nand_read_byte(mtd);
+}
+
+/* Copied from nand_base.c to support custom brcmstb_check_exceptions() */
+static void brcmstb_nand_erase_cmd(struct mtd_info *mtd, int page)
+{
+	struct nand_chip *chip = mtd->priv;
+	chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
+}
+
+static int __maybe_unused brcmstb_nand_fill_dma_desc(
+		struct brcmstb_nand_host *host,
+		struct brcm_nand_dma_desc *desc, u64 addr, u64 buf, u32 len,
+		u8 dma_cmd)
+{
+	memset(desc, 0, sizeof(*desc));
+	/*
+	 * Descriptors are written in native byte order (wordwise)
+	 * Enable IRQ; TYPE=head+tail
+	 */
+	desc->cmd_irq = (dma_cmd << 24) | (0x02 << 8) | 0x03;
+#ifdef CONFIG_CPU_BIG_ENDIAN
+	desc->cmd_irq |= 0x01 << 12;
+#endif
+	desc->dram_addr = buf & 0xffffffff;
+	desc->dram_addr_ext = buf >> 32;
+	desc->tfr_len = len;
+	desc->total_len = len;
+	desc->flash_addr = addr & 0xffffffff;
+	desc->flash_addr_ext = addr >> 32;
+	desc->cs = host->cs;
+	desc->status_valid = 0x01;
+	return 0;
+}
+
+static int brcmstb_nand_dma_trans(struct brcmstb_nand_host *host, u64 addr,
+	u32 *buf, u32 len, u8 dma_cmd)
+{
+	int ret = 0;
+
+#ifdef CONFIG_BRCM_HAS_FLASH_DMA
+	struct mtd_info *mtd = &host->mtd;
+	struct nand_chip *chip = &host->chip;
+	dma_addr_t buf_pa;
+	int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
+
+	ctrl.cmd_pending = dma_cmd;
+	ctrl.dma_count = 1;
+	buf_pa = dma_map_single(&host->pdev->dev, buf, len, dir);
+	brcmstb_nand_fill_dma_desc(host, ctrl.dma_desc, addr, (u64)buf_pa, len,
+			dma_cmd);
+
+	/* Start FLASH_DMA engine */
+	BDEV_WR_RB(BCHP_FLASH_DMA_FIRST_DESC, ctrl.dma_pa);
+	HIF_DISABLE_IRQ(NAND_CTLRDY);
+	mb();
+	BDEV_WR_F(FLASH_DMA_CTRL, RUN, 1);
+	BDEV_WR_F(FLASH_DMA_CTRL, WAKE, 1);
+
+	brcmstb_nand_waitfunc(mtd, chip);
+
+	HIF_ACK_IRQ(NAND_CTLRDY);
+	HIF_ENABLE_IRQ(NAND_CTLRDY);
+	dma_unmap_single(&host->pdev->dev, buf_pa, len, dir);
+#endif
+
+	return ret;
+}
+
+static int brcmstb_nand_edu_trans(struct brcmstb_nand_host *host, u64 addr,
+	u32 *buf, u8 *oob, unsigned int trans, u32 edu_cmd)
+{
+	int ret = 0;
+
+#ifdef CONFIG_BRCM_HAS_EDU
+	int dir = edu_cmd == EDU_CMD_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
+	unsigned int len = trans * FC_BYTES;
+	dma_addr_t pa = dma_map_single(&host->pdev->dev, buf, len, dir);
+	struct mtd_info *mtd = &host->mtd;
+	struct nand_chip *chip = &host->chip;
+
+	ctrl.edu_dram_addr = pa;
+	ctrl.edu_ext_addr = addr;
+	ctrl.edu_cmd = edu_cmd;
+	ctrl.edu_count = trans;
+	ctrl.sas = host->hwcfg.spare_area_size;
+	ctrl.sector_size_1k = host->hwcfg.sector_size_1k;
+	ctrl.oob = oob;
+
+	BDEV_WR_RB(BCHP_EDU_DRAM_ADDR, (u32)ctrl.edu_dram_addr);
+	BDEV_WR_RB(BCHP_EDU_EXT_ADDR, ctrl.edu_ext_addr);
+	BDEV_WR_RB(BCHP_EDU_LENGTH, FC_BYTES);
+
+	/* Write OOB regs for first subpage */
+	if (oob && (edu_cmd == EDU_CMD_WRITE)) {
+		BDEV_WR_RB(BCHP_NAND_CMD_ADDRESS, ctrl.edu_ext_addr);
+		ctrl.oob += write_oob_to_regs(trans, ctrl.oob, ctrl.sas,
+				ctrl.sector_size_1k);
+	}
+
+	ctrl.cmd_pending = (edu_cmd == EDU_CMD_READ) ?
+		CMD_PAGE_READ : CMD_PROGRAM_PAGE;
+	mb();
+	BDEV_WR_RB(BCHP_EDU_CMD, ctrl.edu_cmd);
+
+	/* wait for completion, then (for program page) check NAND status */
+	if ((brcmstb_nand_waitfunc(mtd, chip) & NAND_STATUS_FAIL) &&
+			edu_cmd == EDU_CMD_WRITE) {
+		dev_info(&host->pdev->dev, "program failed at %llx\n",
+			(unsigned long long)addr);
+		ret = -EIO;
+	}
+
+	dma_unmap_single(&host->pdev->dev, pa, len, dir);
+
+	/* Read OOB regs for last subpage */
+	if (oob && edu_cmd == EDU_CMD_READ) {
+		BDEV_WR_RB(BCHP_EDU_DRAM_ADDR, (u32)ctrl.edu_dram_addr);
+		BDEV_WR_RB(BCHP_EDU_EXT_ADDR, ctrl.edu_ext_addr);
+		read_oob_from_regs(1, ctrl.oob, ctrl.sas, ctrl.sector_size_1k);
+	}
+
+	/* Make sure the EDU status is clean */
+	if (BDEV_RD_F(EDU_STATUS, Active))
+		dev_warn(&host->pdev->dev, "EDU still active: %08lx\n",
+			BDEV_RD(BCHP_EDU_STATUS));
+
+	if (unlikely(BDEV_RD_F(EDU_ERR_STATUS, ErrAck))) {
+		dev_warn(&host->pdev->dev, "EDU RBUS error at addr %llx\n",
+			(unsigned long long)addr);
+		ret = -EIO;
+	}
+
+	BDEV_WR(BCHP_EDU_ERR_STATUS, 0);
+#endif /* CONFIG_BRCM_HAS_EDU */
+
+	return ret;
+}
+
+/*
+ * Assumes proper CS is already set
+ */
+static void brcmstb_nand_read_by_pio(struct mtd_info *mtd,
+	struct nand_chip *chip, u64 addr, unsigned int trans,
+	u32 *buf, u8 *oob)
+{
+	struct brcmstb_nand_host *host = chip->priv;
+	int i, j;
+
+	for (i = 0; i < trans; i++, addr += FC_BYTES) {
+		BDEV_WR_RB(BCHP_NAND_CMD_ADDRESS, addr & 0xffffffff);
+		/* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
+		brcmstb_nand_send_cmd(CMD_PAGE_READ);
+		brcmstb_nand_waitfunc(mtd, chip);
+
+		if (likely(buf))
+			for (j = 0; j < FC_WORDS; j++, buf++)
+				*buf = le32_to_cpu(BDEV_RD(FC(j)));
+
+		if (oob)
+			oob += read_oob_from_regs(i, oob, mtd->oobsize / trans, host->hwcfg.sector_size_1k);
+	}
+}
+
+/*
+ * Assumes proper CS is already set
+ * Looks for erased page bitflips during data reads
+ * This tries to detect uncorrectable errors on erased page reads,
+ * however on a real error raw data will be returned to caller
+ * Returns 0 on false uncorrectable error on erased page bitflips
+ * else returns the number of bitflips to the caller.
+ */
+static int brcmstb_nand_verify_uncorr_err(struct mtd_info *mtd,
+		  struct nand_chip *chip, u64 addr)
+{
+	struct brcmstb_nand_host *host = chip->priv;
+	int i, sas, oob_nbits, sector_1k = host->hwcfg.sector_size_1k;
+	int len, data_nbits;
+	int uncorr_err = 1;
+	int oob_bitflips, data_bitflips, total_bitflips;
+	u8 *oob_buf = (u8 *) chip->oob_poi;
+	u8 *data_buf = (u8 *) chip->buffers->databuf;
+	u64 err_addr = addr;
+	int trans = (mtd->writesize >> FC_SHIFT);
+	int threshold = ((host->hwcfg.ecc_level << sector_1k) * 3 + 2) / 4;
+
+	sas = host->hwcfg.spare_area_size << sector_1k;
+	oob_nbits = sas << 3;
+	len = FC_BYTES << sector_1k;
+	data_nbits = len << 3;
+
+	/* read without ecc for verification */
+	WR_ACC_CONTROL(host->cs, RD_ECC_EN, 0);
+	WR_ACC_CONTROL(host->cs, ECC_LEVEL, 0);
+	brcmstb_nand_read_by_pio(mtd, chip, addr, trans,
+				 (u32 *)data_buf, oob_buf);
+	WR_ACC_CONTROL(host->cs, ECC_LEVEL, host->hwcfg.ecc_level);
+	WR_ACC_CONTROL(host->cs, RD_ECC_EN, 1);
+
+	for (i = 0; i < (trans >> sector_1k); i++, oob_buf += sas) {
+		oob_bitflips = oob_nbits -
+			bitmap_weight((unsigned long *)oob_buf, oob_nbits);
+		data_bitflips = data_nbits -
+			bitmap_weight((unsigned long *)data_buf, data_nbits);
+
+		total_bitflips = data_bitflips + oob_bitflips;
+
+		if (total_bitflips)
+			dev_warn(&host->pdev->dev,
+				 "bitflips oob(%d) data(%d) at 0x%llx\n",
+				 oob_bitflips, data_bitflips,
+				 (unsigned long long)err_addr);
+		data_buf += len;
+		err_addr += len;
+
+		/*
+		 * if oob is all ffs or we are within ecc_level
+		 * then we assume erased page sector
+		 */
+		if (!oob_bitflips || total_bitflips < threshold) {
+			uncorr_err = 0;
+			total_bitflips = 0;
+		} else {
+			/* this is not an erased page uncorrectable error */
+			uncorr_err = 1;
+			break;
+		}
+	}
+
+	if (!uncorr_err)
+		dev_warn(&host->pdev->dev,
+			 "bitflips in apparent erased page at 0x%llx\n",
+			 (unsigned long long)addr);
+
+	return uncorr_err;
+}
+
+static int brcmstb_nand_read(struct mtd_info *mtd,
+	struct nand_chip *chip, u64 addr, unsigned int trans,
+	u32 *buf, u8 *oob)
+{
+	struct brcmstb_nand_host *host = chip->priv;
+	struct brcmstb_nand_cfg *cfg = &host->hwcfg;
+	u64 err_addr;
+	bool use_edu, use_dma;
+
+	DBG("%s %llx -> %p\n", __func__, (unsigned long long)addr, buf);
+
+	BDEV_WR_RB(BCHP_NAND_ECC_UNC_ADDR, 0);
+	BDEV_WR_RB(BCHP_NAND_ECC_CORR_ADDR, 0);
+#if CONTROLLER_VER >= 60
+	BDEV_WR_RB(BCHP_NAND_UNCORR_ERROR_COUNT, 0);
+#endif
+
+	/* Don't use FLASH_DMA if buffer is not 32-byte aligned */
+	use_dma = buf && !oob && DMA_VA_OK(buf) && likely(!((u32)buf & 0x1f));
+	/* Don't use EDU if buffer is not 32-bit aligned */
+	use_edu = buf && EDU_VA_OK(buf) && likely(!((u32)buf & 0x03));
+
+	if (use_dma) {
+		if (brcmstb_nand_dma_trans(host, addr, buf, trans * FC_BYTES,
+					CMD_PAGE_READ))
+			return -EIO;
+	} else {
+
+		BDEV_WR_RB(BCHP_NAND_CMD_EXT_ADDRESS,
+				(host->cs << 16) | ((addr >> 32) & 0xffff));
+
+		if (oob)
+			memset(oob, 0x99, mtd->oobsize);
+
+		if (use_edu) {
+			if (brcmstb_nand_edu_trans(host, addr, buf, oob, trans,
+					EDU_CMD_READ))
+				return -EIO;
+		} else {
+			brcmstb_nand_read_by_pio(mtd, chip, addr, trans, buf,
+					oob);
+		}
+	}
+
+	err_addr = BDEV_RD(BCHP_NAND_ECC_UNC_ADDR) |
+		((u64)(BDEV_RD(BCHP_NAND_ECC_UNC_EXT_ADDR) & 0xffff) << 32);
+
+	if (err_addr != 0) {
+		/*
+		 * workaround to detect bit flip within erased page
+		 * applied to data reads for BCH-4 and above
+		 */
+		if (!is_hamming_ecc(cfg)) {
+			if (!brcmstb_nand_verify_uncorr_err(mtd, chip, addr)) {
+				if (buf)
+					memset(buf, 0xff, FC_BYTES * trans);
+				if (oob)
+					memset(oob, 0xff, mtd->oobsize);
+
+				goto no_eccerr;
+			}
+		}
+
+		dev_warn(&host->pdev->dev, "uncorrectable error at 0x%llx\n",
+			(unsigned long long)err_addr);
+		if (use_edu)
+			brcmstb_nand_read_by_pio(mtd, chip, addr, trans, buf,
+					oob);
+		mtd->ecc_stats.failed += UNCORR_ERROR_COUNT;
+		/* NAND layer expects zero on ECC errors */
+		return 0;
+	}
+
+	err_addr = BDEV_RD(BCHP_NAND_ECC_CORR_ADDR) |
+		((u64)(BDEV_RD(BCHP_NAND_ECC_CORR_EXT_ADDR) & 0xffff) << 32);
+	if (err_addr) {
+		dev_info(&host->pdev->dev, "corrected error at 0x%llx\n",
+			(unsigned long long)err_addr);
+		if (use_edu)
+			brcmstb_nand_read_by_pio(mtd, chip, addr, trans, buf,
+					oob);
+		mtd->ecc_stats.corrected += CORR_ERROR_COUNT;
+		/* NAND layer expects zero on ECC errors */
+		return 0;
+	}
+no_eccerr:
+	return 0;
+}
+
+static int brcmstb_nand_read_page(struct mtd_info *mtd,
+	struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
+{
+	struct brcmstb_nand_host *host = chip->priv;
+	u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
+
+	return brcmstb_nand_read(mtd, chip, host->last_addr,
+			mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
+}
+
+static int brcmstb_nand_read_page_raw(struct mtd_info *mtd,
+	struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
+{
+	struct brcmstb_nand_host *host = chip->priv;
+	u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
+	int ret;
+
+	WR_ACC_CONTROL(host->cs, RD_ECC_EN, 0);
+	WR_ACC_CONTROL(host->cs, ECC_LEVEL, 0);
+	ret = brcmstb_nand_read(mtd, chip, host->last_addr,
+			mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
+	WR_ACC_CONTROL(host->cs, ECC_LEVEL, host->hwcfg.ecc_level);
+	WR_ACC_CONTROL(host->cs, RD_ECC_EN, 1);
+	return ret;
+}
+
+static int brcmstb_nand_read_oob(struct mtd_info *mtd,
+	struct nand_chip *chip, int page)
+{
+	return brcmstb_nand_read(mtd, chip, (u64)page << chip->page_shift,
+			mtd->writesize >> FC_SHIFT,
+			NULL, (u8 *)chip->oob_poi);
+}
+
+static int brcmstb_nand_read_oob_raw(struct mtd_info *mtd,
+	struct nand_chip *chip, int page)
+{
+	struct brcmstb_nand_host *host = chip->priv;
+
+	WR_ACC_CONTROL(host->cs, RD_ECC_EN, 0);
+	WR_ACC_CONTROL(host->cs, ECC_LEVEL, 0);
+	brcmstb_nand_read(mtd, chip, (u64)page << chip->page_shift,
+		mtd->writesize >> FC_SHIFT,
+		NULL, (u8 *)chip->oob_poi);
+	WR_ACC_CONTROL(host->cs, ECC_LEVEL, host->hwcfg.ecc_level);
+	WR_ACC_CONTROL(host->cs, RD_ECC_EN, 1);
+	return 0;
+}
+
+static int brcmstb_nand_read_subpage(struct mtd_info *mtd,
+	struct nand_chip *chip, uint32_t data_offs, uint32_t readlen,
+	uint8_t *bufpoi)
+{
+	struct brcmstb_nand_host *host = chip->priv;
+
+	return brcmstb_nand_read(mtd, chip, host->last_addr + data_offs,
+			readlen >> FC_SHIFT, (u32 *)bufpoi, NULL);
+}
+
+static int brcmstb_nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf,
+	int len)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct brcmstb_nand_host *host = chip->priv;
+	unsigned int i, j;
+	int err;
+	u64 addr = host->last_addr;
+	u32 *src = (u32 *)buf, *dst;
+
+	for (i = 0; i < (mtd->writesize >> FC_SHIFT); i++) {
+		err = brcmstb_nand_read(mtd, chip, addr, 1, host->buf, NULL);
+
+		if (err) {
+			dev_info(&host->pdev->dev,
+				"verify failed at 0x%llx (error %d)\n",
+				(unsigned long long)addr, err);
+			return -EFAULT;
+		}
+		dst = host->buf;
+
+		for (j = 0; j < FC_WORDS; j++, src++, dst++)
+			if (*src != le32_to_cpu(*dst)) {
+				dev_info(&host->pdev->dev,
+					"mismatch at 0x%llx (read %08lx, "
+					"expected %08lx)\n",
+					(unsigned long long)addr + (j << 2),
+					(unsigned long)*dst,
+					(unsigned long)*src);
+				return -EFAULT;
+			}
+		addr += FC_BYTES;
+	}
+	return 0;
+}
+
+static int brcmstb_nand_write(struct mtd_info *mtd,
+	struct nand_chip *chip, u64 addr, const u32 *buf, u8 *oob)
+{
+	struct brcmstb_nand_host *host = chip->priv;
+	unsigned int i = 0, j, trans = mtd->writesize >> FC_SHIFT;
+	int status, ret = 0;
+
+	DBG("%s %llx <- %p\n", __func__, (unsigned long long)addr, buf);
+
+	if (unlikely((u32)buf & 0x03)) {
+		dev_warn(&host->pdev->dev, "unaligned buffer: %p\n", buf);
+		buf = (u32 *)((u32)buf & ~0x03);
+	}
+
+	brcmstb_nand_wp(mtd, 0);
+
+	if (buf && !oob && DMA_VA_OK(buf) && !((u32)buf & 0x1f)) {
+		if (brcmstb_nand_dma_trans(host, addr, (u32 *)buf,
+					mtd->writesize, CMD_PROGRAM_PAGE))
+			ret = -EIO;
+		goto out;
+	}
+
+	BDEV_WR_RB(BCHP_NAND_CMD_EXT_ADDRESS,
+		(host->cs << 16) | ((addr >> 32) & 0xffff));
+
+	for (j = 0; j < MAX_CONTROLLER_OOB; j += 4)
+		oob_reg_write(j, 0xffffffff);
+
+	if (buf && EDU_VA_OK(buf)) {
+		if (brcmstb_nand_edu_trans(host, addr, (u32 *)buf, oob, trans,
+				EDU_CMD_WRITE)) {
+			ret = -EIO;
+			goto out;
+		}
+		i = trans;
+	}
+
+	for (; i < trans; i++, addr += FC_BYTES) {
+		/* full address MUST be set before populating FC */
+		BDEV_WR_RB(BCHP_NAND_CMD_ADDRESS, addr & 0xffffffff);
+
+		if (buf)
+			for (j = 0; j < FC_WORDS; j++, buf++)
+				BDEV_WR(FC(j), cpu_to_le32(*buf));
+		else if (oob)
+			for (j = 0; j < FC_WORDS; j++)
+				BDEV_WR(FC(j), 0xffffffff);
+
+		if (oob) {
+			oob += write_oob_to_regs(i, oob, mtd->oobsize / trans,
+					host->hwcfg.sector_size_1k);
+		}
+
+		/* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
+		brcmstb_nand_send_cmd(CMD_PROGRAM_PAGE);
+		status = brcmstb_nand_waitfunc(mtd, chip);
+
+		if (status & NAND_STATUS_FAIL) {
+			dev_info(&host->pdev->dev, "program failed at %llx\n",
+				(unsigned long long)addr);
+			ret = -EIO;
+			goto out;
+		}
+	}
+out:
+	brcmstb_nand_wp(mtd, 1);
+	return ret;
+}
+
+static void brcmstb_nand_write_page(struct mtd_info *mtd,
+	struct nand_chip *chip, const uint8_t *buf, int oob_required)
+{
+	struct brcmstb_nand_host *host = chip->priv;
+	u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
+
+	brcmstb_nand_write(mtd, chip, host->last_addr, (u32 *)buf, oob);
+}
+
+static void brcmstb_nand_write_page_raw(struct mtd_info *mtd,
+	struct nand_chip *chip, const uint8_t *buf, int oob_required)
+{
+	struct brcmstb_nand_host *host = chip->priv;
+	u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
+
+	WR_ACC_CONTROL(host->cs, WR_ECC_EN, 0);
+	brcmstb_nand_write(mtd, chip, host->last_addr, (u32 *)buf, oob);
+	WR_ACC_CONTROL(host->cs, WR_ECC_EN, 1);
+}
+
+static int brcmstb_nand_write_oob(struct mtd_info *mtd,
+	struct nand_chip *chip, int page)
+{
+	return brcmstb_nand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
+		(u8 *)chip->oob_poi);
+}
+
+static int brcmstb_nand_write_oob_raw(struct mtd_info *mtd,
+	struct nand_chip *chip, int page)
+{
+	struct brcmstb_nand_host *host = chip->priv;
+
+	WR_ACC_CONTROL(host->cs, WR_ECC_EN, 0);
+	return brcmstb_nand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
+		(u8 *)chip->oob_poi);
+	WR_ACC_CONTROL(host->cs, WR_ECC_EN, 1);
+}
+
+/***********************************************************************
+ * Per-CS setup (1 NAND device)
+ ***********************************************************************/
+
+#if CONTROLLER_VER >= 60
+static const unsigned int block_sizes[] = { 8, 16, 128, 256, 512, 1024, 2048 };
+static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192 };
+#elif CONTROLLER_VER >= 40
+static const unsigned int block_sizes[] = { 16, 128, 8, 512, 256, 1024, 2048 };
+static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192 };
+#else
+static const unsigned int block_sizes[] = { 16, 128, 8, 512, 256 };
+static const unsigned int page_sizes[] = { 512, 2048, 4096 };
+#endif
+
+static void brcmstb_nand_set_cfg(struct brcmstb_nand_host *host,
+	struct brcmstb_nand_cfg *cfg)
+{
+	int i, found;
+
+	for (i = 0, found = 0; i < ARRAY_SIZE(block_sizes); i++)
+		if ((block_sizes[i] << 10) == cfg->block_size) {
+			WR_CONFIG(host->cs, BLOCK_SIZE, i);
+			found = 1;
+		}
+	if (!found)
+		dev_warn(&host->pdev->dev, "invalid block size %u\n",
+			cfg->block_size);
+
+	for (i = 0, found = 0; i < ARRAY_SIZE(page_sizes); i++)
+		if (page_sizes[i] == cfg->page_size) {
+			WR_CONFIG(host->cs, PAGE_SIZE, i);
+			found = 1;
+		}
+	if (!found)
+		dev_warn(&host->pdev->dev, "invalid page size %u\n",
+			cfg->page_size);
+
+	if (fls64(cfg->device_size) < 23)
+		dev_warn(&host->pdev->dev, "invalid device size 0x%llx\n",
+			(unsigned long long)cfg->device_size);
+
+	WR_CONFIG(host->cs, DEVICE_SIZE, fls64(cfg->device_size) - 23);
+	WR_CONFIG(host->cs, DEVICE_WIDTH, cfg->device_width == 16 ? 1 : 0);
+	WR_CONFIG(host->cs, COL_ADR_BYTES, cfg->col_adr_bytes);
+	WR_CONFIG(host->cs, BLK_ADR_BYTES, cfg->blk_adr_bytes);
+	WR_CONFIG(host->cs, FUL_ADR_BYTES, cfg->ful_adr_bytes);
+
+	WR_ACC_CONTROL(host->cs, SPARE_AREA_SIZE, cfg->spare_area_size);
+#if CONTROLLER_VER >= 50
+	WR_ACC_CONTROL(host->cs, SECTOR_SIZE_1K, cfg->sector_size_1k);
+#endif
+
+	WR_ACC_CONTROL(host->cs, ECC_LEVEL, cfg->ecc_level);
+	/* threshold = ceil(BCH-level * 0.75) */
+	WR_CORR_THRESH(host->cs, ((cfg->ecc_level << cfg->sector_size_1k)
+				* 3 + 2) / 4);
+}
+
+static void brcmstb_nand_get_cfg(struct brcmstb_nand_host *host,
+	struct brcmstb_nand_cfg *cfg)
+{
+	cfg->block_size = RD_CONFIG(host->cs, BLOCK_SIZE);
+	cfg->device_size = (4ULL << 20) << RD_CONFIG(host->cs, DEVICE_SIZE);
+	cfg->page_size = RD_CONFIG(host->cs, PAGE_SIZE);
+	cfg->device_width = RD_CONFIG(host->cs, DEVICE_WIDTH) ? 16 : 8;
+	cfg->col_adr_bytes = RD_CONFIG(host->cs, COL_ADR_BYTES);
+	cfg->blk_adr_bytes = RD_CONFIG(host->cs, BLK_ADR_BYTES);
+	cfg->ful_adr_bytes = RD_CONFIG(host->cs, FUL_ADR_BYTES);
+	cfg->spare_area_size = RD_ACC_CONTROL(host->cs, SPARE_AREA_SIZE);
+#if CONTROLLER_VER >= 50
+	cfg->sector_size_1k = RD_ACC_CONTROL(host->cs, SECTOR_SIZE_1K);
+#else
+	cfg->sector_size_1k = 0;
+#endif
+	cfg->ecc_level = RD_ACC_CONTROL(host->cs, ECC_LEVEL);
+
+	if (cfg->block_size < ARRAY_SIZE(block_sizes))
+		cfg->block_size = block_sizes[cfg->block_size] << 10;
+	else
+		cfg->block_size = 128 << 10;
+
+	if (cfg->page_size < ARRAY_SIZE(page_sizes))
+		cfg->page_size = page_sizes[cfg->page_size];
+	else
+		cfg->page_size = 2048;
+}
+
+static void brcmstb_nand_print_cfg(char *buf, struct brcmstb_nand_cfg *cfg)
+{
+	buf += sprintf(buf,
+		"%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
+		(unsigned long long)cfg->device_size >> 20,
+		cfg->block_size >> 10,
+		cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,
+		cfg->page_size >= 1024 ? "KiB" : "B",
+		cfg->spare_area_size, cfg->device_width);
+
+	/* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
+	if (is_hamming_ecc(cfg))
+		sprintf(buf, ", Hamming ECC");
+	else if (cfg->sector_size_1k)
+		sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
+	else
+		sprintf(buf, ", BCH-%u\n", cfg->ecc_level);
+}
+
+/*
+ * Return true if the two configurations are basically identical. Note that we
+ * allow certain variations in spare area size.
+ */
+static bool brcmstb_nand_config_match(struct brcmstb_nand_cfg *orig,
+		struct brcmstb_nand_cfg *new)
+{
+	/* Negative matches */
+	if (orig->device_size != new->device_size)
+		return false;
+	if (orig->block_size != new->block_size)
+		return false;
+	if (orig->page_size != new->page_size)
+		return false;
+	if (orig->device_width != new->device_width)
+		return false;
+	if (orig->col_adr_bytes != new->col_adr_bytes)
+		return false;
+	if (orig->blk_adr_bytes != new->blk_adr_bytes)
+		return false;
+	if (orig->ful_adr_bytes != new->ful_adr_bytes)
+		return false;
+
+	/* Positive matches */
+	if (orig->spare_area_size == new->spare_area_size)
+		return true;
+	return orig->spare_area_size >= 27 &&
+	       orig->spare_area_size <= new->spare_area_size;
+}
+
+static int __devinit brcmstb_nand_setup_dev(struct brcmstb_nand_host *host)
+{
+	struct mtd_info *mtd = &host->mtd;
+	struct nand_chip *chip = &host->chip;
+	struct brcmstb_nand_cfg orig_cfg, new_cfg;
+	char msg[128];
+
+	brcmstb_nand_get_cfg(host, &orig_cfg);
+	host->hwcfg = orig_cfg;
+
+	memset(&new_cfg, 0, sizeof(new_cfg));
+	new_cfg.device_size = mtd->size;
+	new_cfg.block_size = mtd->erasesize;
+	new_cfg.page_size = mtd->writesize;
+	new_cfg.spare_area_size = mtd->oobsize / (mtd->writesize >> FC_SHIFT);
+	new_cfg.device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
+	new_cfg.col_adr_bytes = 2;
+
+	if (mtd->writesize > 512)
+		if (mtd->size >= (256 << 20))
+			new_cfg.blk_adr_bytes = 3;
+		else
+			new_cfg.blk_adr_bytes = 2;
+	else
+		if (mtd->size >= (64 << 20))
+			new_cfg.blk_adr_bytes = 3;
+		else
+			new_cfg.blk_adr_bytes = 2;
+	new_cfg.ful_adr_bytes = new_cfg.blk_adr_bytes + new_cfg.col_adr_bytes;
+
+	if (new_cfg.spare_area_size > MAX_CONTROLLER_OOB)
+		new_cfg.spare_area_size = MAX_CONTROLLER_OOB;
+
+	if (!brcmstb_nand_config_match(&orig_cfg, &new_cfg)) {
+#if CONTROLLER_VER >= 50
+#ifdef CONFIG_BCM7445A0
+		/* HW7445-750: 7445A0 NAND is broken for SECTOR_SIZE = 1024B */
+		new_cfg.sector_size_1k = 0;
+#else
+		/* default to 1K sector size (if page is large enough) */
+		new_cfg.sector_size_1k = (new_cfg.page_size >= 1024) ? 1 : 0;
+#endif /* CONFIG_BCM7445A0 */
+#endif
+
+		WR_ACC_CONTROL(host->cs, RD_ECC_EN, 1);
+		WR_ACC_CONTROL(host->cs, WR_ECC_EN, 1);
+
+		if (new_cfg.spare_area_size >= 21)
+			new_cfg.ecc_level = 12;
+		else if (chip->badblockpos == NAND_SMALL_BADBLOCK_POS)
+			new_cfg.ecc_level = 5;
+		else
+			new_cfg.ecc_level = 8;
+
+		brcmstb_nand_set_cfg(host, &new_cfg);
+		host->hwcfg = new_cfg;
+
+		if (BDEV_RD(BCHP_NAND_CS_NAND_SELECT) & (0x100 << host->cs)) {
+			/* bootloader activated this CS */
+			dev_warn(&host->pdev->dev, "overriding bootloader "
+				"settings on CS%d\n", host->cs);
+			brcmstb_nand_print_cfg(msg, &orig_cfg);
+			dev_warn(&host->pdev->dev, "was: %s\n", msg);
+			brcmstb_nand_print_cfg(msg, &new_cfg);
+			dev_warn(&host->pdev->dev, "now: %s\n", msg);
+		} else {
+			/*
+			 * nandcs= argument activated this CS; assume that
+			 * nobody even tried to set the device configuration
+			 */
+			brcmstb_nand_print_cfg(msg, &new_cfg);
+			dev_info(&host->pdev->dev, "detected %s\n", msg);
+		}
+	} else {
+#ifdef CONFIG_BCM7445A0
+		/* HW7445-750 */
+		if (orig_cfg.sector_size_1k != 0) {
+			dev_err(&host->pdev->dev, "1KB ECC sectors not "
+					"supported on 7445A0\n");
+			return -ENXIO;
+		}
+#endif
+		/*
+		 * Set oobsize to be consistent with controller's
+		 * spare_area_size. This helps nandwrite testing.
+		 */
+		mtd->oobsize = new_cfg.spare_area_size *
+			       (mtd->writesize >> FC_SHIFT);
+
+		brcmstb_nand_print_cfg(msg, &orig_cfg);
+		dev_info(&host->pdev->dev, "%s\n", msg);
+	}
+
+#if CONTROLLER_VER < 70
+	WR_ACC_CONTROL(host->cs, FAST_PGM_RDIN, 0);
+#endif
+	WR_ACC_CONTROL(host->cs, RD_ERASED_ECC_EN, 0);
+	WR_ACC_CONTROL(host->cs, PARTIAL_PAGE_EN, 0);
+	WR_ACC_CONTROL(host->cs, PAGE_HIT_EN, 1);
+#if CONTROLLER_VER >= 60
+	WR_ACC_CONTROL(host->cs, PREFETCH_EN, 0);
+#endif
+	mb();
+
+	return 0;
+}
+
+static int brcmstb_check_exceptions(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct brcmstb_nand_exception *list = brcmstb_exceptions_list;
+	int i;
+	u8 id_data[8];
+
+	/*
+	 * run default nand_base initialization w/o built-in ID table;
+	 * should return error, so we tell it to be "silent"
+	 */
+	chip->options |= NAND_SCAN_SILENT_NODEV;
+	nand_scan_ident(mtd, 1, brcmstb_empty_flash_table);
+	chip->options &= ~NAND_SCAN_SILENT_NODEV;
+
+	/* Send the command for reading device ID */
+	chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+
+	for (i = 0; i < 8; i++)
+		id_data[i] = chip->read_byte(mtd);
+
+	for (; list->name != NULL; list++) {
+		for (i = 0; i < list->idlen; i++)
+			if (id_data[i] != list->id[i])
+				break;
+		if (i == list->idlen)
+			break;
+	}
+
+	if (!list->name)
+		return -ENODEV;
+
+	chip->chipsize = (uint64_t)list->chipsize << 20;
+	mtd->size = chip->chipsize;
+
+	mtd->erasesize = list->erasesize;
+	mtd->writesize = list->writesize;
+	mtd->oobsize = list->oobsize;
+
+	chip->options |= list->chipoptions;
+	chip->badblockpos = list->badblockpos;
+
+	/* The 3rd id byte holds MLC / multichip data */
+	chip->cellinfo = id_data[2];
+
+	chip->numchips = 1;
+
+	/* Calculate the address shift from the page size */
+	chip->page_shift = ffs(mtd->writesize) - 1;
+	/* Convert chipsize to number of pages per chip -1. */
+	chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
+
+	chip->bbt_erase_shift = chip->phys_erase_shift =
+		ffs(mtd->erasesize) - 1;
+	chip->chip_shift = fls64(chip->chipsize) - 1;
+
+	chip->erase_cmd = brcmstb_nand_erase_cmd;
+
+	pr_info("%s: heuristics exception detected, %s\n",
+		mtd->name, list->name);
+	return 0;
+}
+
+static int __devinit brcmstb_nand_probe(struct platform_device *pdev)
+{
+	struct brcmnand_platform_data *pd = pdev->dev.platform_data;
+	struct device_node *dn = pdev->dev.of_node;
+	struct brcmstb_nand_host *host;
+	struct mtd_info *mtd;
+	struct nand_chip *chip;
+	int ret = 0;
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)
+	const char *part_probe_types[] = { "cmdlinepart", "ofpart", "RedBoot",
+		NULL };
+#elif defined(CONFIG_MTD_PARTITIONS)
+	/* for 2.6.37 compatibility only */
+	int nr_parts;
+	struct mtd_partition *parts;
+	const char *part_probe_types[] = { "cmdlinepart", "RedBoot", NULL };
+#endif
+
+	host = kzalloc(sizeof(*host), GFP_KERNEL);
+	if (!host) {
+		dev_err(&pdev->dev, "can't allocate memory\n");
+		return -ENOMEM;
+	}
+
+	if (dn) {
+		ret = of_property_read_u32(dn, "reg", &host->cs);
+		if (ret) {
+			dev_err(&pdev->dev, "can't get chip-select\n");
+			ret = -ENXIO;
+			goto out;
+		}
+	} else {
+		host->cs = pd->chip_select;
+	}
+
+	DBG("%s: id %d cs %d\n", __func__, pdev->id, host->cs);
+
+	mtd = &host->mtd;
+	chip = &host->chip;
+	host->pdev = pdev;
+	dev_set_drvdata(&pdev->dev, host);
+
+	chip->priv = host;
+	mtd->priv = chip;
+	mtd->name = dev_name(&pdev->dev);
+	mtd->owner = THIS_MODULE;
+	mtd->dev.parent = &pdev->dev;
+
+	chip->IO_ADDR_R = (void *)0xdeadbeef;
+	chip->IO_ADDR_W = (void *)0xdeadbeef;
+
+	chip->cmd_ctrl = brcmstb_nand_cmd_ctrl;
+	chip->cmdfunc = brcmstb_nand_cmdfunc;
+	chip->waitfunc = brcmstb_nand_waitfunc;
+	chip->read_byte = brcmstb_nand_read_byte;
+	chip->read_buf = brcmstb_nand_read_buf;
+	chip->verify_buf = brcmstb_nand_verify_buf;
+
+	chip->ecc.mode = NAND_ECC_HW;
+	chip->ecc.size = 512;
+	chip->ecc.layout = &brcmstb_nand_dummy_layout;
+	chip->ecc.read_page = brcmstb_nand_read_page;
+	chip->ecc.read_subpage = brcmstb_nand_read_subpage;
+	chip->ecc.write_page = brcmstb_nand_write_page;
+	chip->ecc.read_page_raw = brcmstb_nand_read_page_raw;
+	chip->ecc.write_page_raw = brcmstb_nand_write_page_raw;
+	chip->ecc.write_oob_raw = brcmstb_nand_write_oob_raw;
+	chip->ecc.read_oob_raw = brcmstb_nand_read_oob_raw;
+	chip->ecc.read_oob = brcmstb_nand_read_oob;
+	chip->ecc.write_oob = brcmstb_nand_write_oob;
+
+	chip->controller = &ctrl.controller;
+
+	if (brcmstb_check_exceptions(mtd) && nand_scan_ident(mtd, 1, NULL)) {
+		ret = -ENXIO;
+		goto out;
+	}
+	chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_SKIP_BBTSCAN;
+	chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
+	if (nand_scan_tail(mtd) || brcmstb_nand_setup_dev(host) ||
+			chip->scan_bbt(mtd)) {
+		ret = -ENXIO;
+		goto out;
+	}
+
+	chip->ecc.layout = brcmstb_choose_ecc_layout(host);
+	if (!chip->ecc.layout) {
+		ret = -ENXIO;
+		goto out;
+	}
+	/* Update ecclayout info after nand_scan_tail() */
+	mtd->oobavail = chip->ecc.layout->oobavail;
+	mtd->ecclayout = chip->ecc.layout;
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)
+	if (dn) {
+		struct mtd_part_parser_data ppdata = { .of_node = dn };
+		mtd_device_parse_register(mtd, part_probe_types, &ppdata, NULL,
+				0);
+	} else {
+		mtd_device_parse_register(mtd, part_probe_types, NULL,
+				pd->parts, pd->nr_parts);
+	}
+#elif defined(CONFIG_MTD_PARTITIONS)
+	nr_parts = parse_mtd_partitions(mtd, part_probe_types, &parts, 0);
+	if (nr_parts <= 0) {
+		nr_parts = pd->nr_parts;
+		parts = pd->parts;
+	}
+
+	if (nr_parts)
+		add_mtd_partitions(mtd, parts, nr_parts);
+	else
+		add_mtd_device(mtd);
+#else
+	add_mtd_device(mtd);
+#endif
+	return 0;
+
+out:
+	kfree(host);
+	return ret;
+}
+
+static int __devexit brcmstb_nand_remove(struct platform_device *pdev)
+{
+	struct brcmstb_nand_host *host = dev_get_drvdata(&pdev->dev);
+	struct mtd_info *mtd = &host->mtd;
+	struct nand_chip *chip = mtd->priv;
+
+	kfree(chip->ecc.layout);
+	nand_release(mtd);
+	dev_set_drvdata(&pdev->dev, NULL);
+	kfree(host);
+
+	return 0;
+}
+
+#define HIF_ENABLED_IRQ(bit) \
+	(!BDEV_RD_F(HIF_INTR2_CPU_MASK_STATUS, bit##_INTR))
+
+static int brcmstb_nand_suspend(struct device *dev)
+{
+	if (brcm_pm_deep_sleep()) {
+		struct brcmstb_nand_host *host = dev_get_drvdata(dev);
+
+		dev_dbg(dev, "Save state for S3 suspend\n");
+#ifdef CONFIG_BRCM_HAS_EDU
+		ctrl.edu_config = BDEV_RD(BCHP_EDU_CONFIG);
+#endif
+		ctrl.nand_cs_nand_select = BDEV_RD(BCHP_NAND_CS_NAND_SELECT);
+		ctrl.nand_cs_nand_xor = BDEV_RD(BCHP_NAND_CS_NAND_XOR);
+		ctrl.corr_stat_threshold =
+			BDEV_RD(BCHP_NAND_CORR_STAT_THRESHOLD);
+		ctrl.hif_intr2 = HIF_ENABLED_IRQ(NAND_CTLRDY);
+#ifdef CONFIG_BRCM_HAS_FLASH_DMA
+		ctrl.hif_intr2 |= HIF_ENABLED_IRQ(FLASH_DMA_DONE);
+		ctrl.flash_dma_mode = BDEV_RD(BCHP_FLASH_DMA_MODE);
+#endif
+
+		host->hwcfg.acc_control = BDEV_RD(REG_ACC_CONTROL(host->cs));
+		host->hwcfg.config = BDEV_RD(REG_CONFIG(host->cs));
+		host->hwcfg.timing_1 = BDEV_RD(REG_TIMING_1(host->cs));
+		host->hwcfg.timing_2 = BDEV_RD(REG_TIMING_2(host->cs));
+	}
+	return 0;
+}
+
+static int brcmstb_nand_resume(struct device *dev)
+{
+	if (brcm_pm_deep_sleep()) {
+		struct brcmstb_nand_host *host = dev_get_drvdata(dev);
+		struct mtd_info *mtd = &host->mtd;
+		struct nand_chip *chip = mtd->priv;
+
+		dev_dbg(dev, "Restore state after S3 suspend\n");
+#ifdef CONFIG_BRCM_HAS_EDU
+		BDEV_WR_RB(BCHP_EDU_CONFIG, ctrl.edu_config);
+		BDEV_WR(BCHP_EDU_ERR_STATUS, 0);
+		BDEV_WR(BCHP_EDU_DONE, 0);
+		BDEV_WR(BCHP_EDU_DONE, 0);
+		BDEV_WR(BCHP_EDU_DONE, 0);
+		BDEV_WR(BCHP_EDU_DONE, 0);
+#endif
+
+#ifdef CONFIG_BRCM_HAS_FLASH_DMA
+		BDEV_WR_RB(BCHP_FLASH_DMA_MODE, ctrl.flash_dma_mode);
+		BDEV_WR_RB(BCHP_FLASH_DMA_ERROR_STATUS, 0);
+#endif
+
+		BDEV_WR_RB(BCHP_NAND_CS_NAND_SELECT, ctrl.nand_cs_nand_select);
+		BDEV_WR_RB(BCHP_NAND_CS_NAND_XOR, ctrl.nand_cs_nand_xor);
+		BDEV_WR_RB(BCHP_NAND_CORR_STAT_THRESHOLD,
+			ctrl.corr_stat_threshold);
+
+		BDEV_WR_RB(REG_ACC_CONTROL(host->cs), host->hwcfg.acc_control);
+		BDEV_WR_RB(REG_CONFIG(host->cs), host->hwcfg.config);
+		BDEV_WR_RB(REG_TIMING_1(host->cs), host->hwcfg.timing_1);
+		BDEV_WR_RB(REG_TIMING_2(host->cs), host->hwcfg.timing_2);
+
+		HIF_ACK_IRQ(NAND_CTLRDY);
+		if (ctrl.hif_intr2) {
+			HIF_ENABLE_IRQ(NAND_CTLRDY);
+#ifdef CONFIG_BRCM_HAS_FLASH_DMA
+			HIF_ENABLE_IRQ(FLASH_DMA_DONE);
+#endif
+		}
+
+		/* Reset the chip, required by some chips after power-up */
+		chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+	}
+	return 0;
+}
+
+static const struct dev_pm_ops brcmstb_nand_pm_ops = {
+	.suspend		= brcmstb_nand_suspend,
+	.resume			= brcmstb_nand_resume,
+};
+
+static const struct of_device_id brcmstb_nand_of_match[] = {
+	{ .compatible = "brcm,nandcs" },
+	{},
+};
+
+/***********************************************************************
+ * Platform driver setup (per controller)
+ ***********************************************************************/
+static struct platform_driver brcmstb_nand_driver = {
+	.probe			= brcmstb_nand_probe,
+	.remove			= __devexit_p(brcmstb_nand_remove),
+	.driver = {
+		.name		= "brcmnand",
+		.owner		= THIS_MODULE,
+		.pm		= &brcmstb_nand_pm_ops,
+		.of_match_table	= brcmstb_nand_of_match,
+	},
+};
+
+#define BREG_PA(x)		(BPHYSADDR(BCHP_##x##_REG_START))
+#define BREG_LEN(x)		(BCHP_##x##_REG_END + 4 - BCHP_##x##_REG_START)
+
+static int __init brcmstb_nand_init(void)
+{
+	int err = -ENODEV;
+
+	init_completion(&ctrl.done);
+	spin_lock_init(&ctrl.controller.lock);
+	init_waitqueue_head(&ctrl.controller.wq);
+
+	if (!request_mem_region(BREG_PA(NAND), BREG_LEN(NAND), DRV_NAME)) {
+		pr_err("%s: can't request memory region\n", __func__);
+		return err;
+	}
+
+#if defined(CONFIG_BRCM_HAS_FLASH_DMA)
+	if (!request_mem_region(BREG_PA(FLASH_DMA), BREG_LEN(FLASH_DMA),
+				DRV_NAME)) {
+		pr_err("%s: can't request memory region\n", __func__);
+		goto out4;
+	}
+	BDEV_WR_F(FLASH_DMA_MODE, MODE, 1);
+	BDEV_WR_F(FLASH_DMA_MODE, STOP_ON_ERROR, 0);
+	BDEV_WR(BCHP_FLASH_DMA_ERROR_STATUS, 0);
+	ctrl.dma_desc = dma_alloc_coherent(NULL, sizeof(*ctrl.dma_desc),
+			&ctrl.dma_pa, GFP_KERNEL);
+	if (!ctrl.dma_desc) {
+		pr_err("%s: can't allocate memory\n", __func__);
+		goto out3;
+	}
+#elif defined(CONFIG_BRCM_HAS_EDU)
+	if (!request_mem_region(BREG_PA(EDU), BREG_LEN(EDU), DRV_NAME)) {
+		pr_err("%s: can't request memory region\n", __func__);
+		goto out4;
+	}
+
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+	BDEV_WR_RB(BCHP_EDU_CONFIG, 0x01);
+#else
+	BDEV_WR_RB(BCHP_EDU_CONFIG, 0x03);
+#endif
+
+	BDEV_WR(BCHP_EDU_ERR_STATUS, 0);
+	BDEV_WR(BCHP_EDU_DONE, 0);
+	BDEV_WR(BCHP_EDU_DONE, 0);
+	BDEV_WR(BCHP_EDU_DONE, 0);
+	BDEV_WR(BCHP_EDU_DONE, 0);
+#endif /* CONFIG_BRCM_HAS_EDU */
+
+	BDEV_WR_F(NAND_CS_NAND_SELECT, AUTO_DEVICE_ID_CONFIG, 0);
+
+	/* disable direct addressing + XOR for all NAND devices */
+	BDEV_UNSET(BCHP_NAND_CS_NAND_SELECT, 0xff);
+	BDEV_UNSET(BCHP_NAND_CS_NAND_XOR, 0xff);
+
+#ifdef BCHP_NAND_CS_NAND_SELECT_NAND_WP_MASK
+	if (wp_on == 2) /* SWLINUX-1818: Permanently remove write-protection */
+		BDEV_WR_F_RB(NAND_CS_NAND_SELECT, NAND_WP, 0);
+#else
+	wp_on = 0;
+#endif
+
+#ifdef CONFIG_BCM7445A0
+	/* HACK: 7445A0 GIC will map HIF interrupt with an offset of 32 */
+	ctrl.irq = 32 + (BRCM_IRQ_HIF - 1);
+#elif defined(CONFIG_OF)
+#error Legacy driver cannot initialize NAND with OF/DeviceTree
+#else
+	ctrl.irq = BRCM_IRQ_HIF;
+#endif
+
+	HIF_ACK_IRQ(NAND_CTLRDY);
+	HIF_ENABLE_IRQ(NAND_CTLRDY);
+#ifdef CONFIG_BRCM_HAS_FLASH_DMA
+	HIF_ACK_IRQ(FLASH_DMA_DONE);
+	HIF_ENABLE_IRQ(FLASH_DMA_DONE);
+#endif
+
+	err = request_irq(ctrl.irq, brcmstb_nand_irq, IRQF_SHARED,
+		DRV_NAME, &ctrl);
+	if (err < 0) {
+		pr_err("%s: can't allocate IRQ %d: error %d\n",
+			__func__, ctrl.irq, err);
+		goto out2;
+	}
+
+	err = platform_driver_register(&brcmstb_nand_driver);
+	if (err < 0) {
+		pr_err("%s: can't register platform driver (error %d)\n",
+			__func__, err);
+		goto out;
+	}
+
+	pr_info(DRV_NAME ": NAND controller driver is loaded\n");
+	return 0;
+
+out:
+	HIF_DISABLE_IRQ(NAND_CTLRDY);
+#ifdef CONFIG_BRCM_HAS_FLASH_DMA
+	HIF_DISABLE_IRQ(FLASH_DMA_DONE);
+#endif
+	free_irq(ctrl.irq, &ctrl);
+out2:
+#if defined(CONFIG_BRCM_HAS_FLASH_DMA)
+	dma_free_coherent(NULL, sizeof(*ctrl.dma_desc), ctrl.dma_desc,
+			ctrl.dma_pa);
+out3:
+	release_mem_region(BREG_PA(FLASH_DMA), BREG_LEN(FLASH_DMA));
+out4:
+#elif defined(CONFIG_BRCM_HAS_EDU)
+	release_mem_region(BREG_PA(EDU), BREG_LEN(EDU));
+out4:
+#endif
+	release_mem_region(BREG_PA(NAND), BREG_LEN(NAND));
+	return err;
+}
+
+static void __exit brcmstb_nand_exit(void)
+{
+	HIF_DISABLE_IRQ(NAND_CTLRDY);
+#ifdef CONFIG_BRCM_HAS_FLASH_DMA
+	HIF_DISABLE_IRQ(FLASH_DMA_DONE);
+#endif
+	free_irq(ctrl.irq, &ctrl);
+	platform_driver_unregister(&brcmstb_nand_driver);
+
+#ifdef CONFIG_BRCM_HAS_FLASH_DMA
+	dma_free_coherent(NULL, sizeof(*ctrl.dma_desc), ctrl.dma_desc,
+			ctrl.dma_pa);
+	release_mem_region(BREG_PA(FLASH_DMA), BREG_LEN(FLASH_DMA));
+#endif
+#ifdef CONFIG_BRCM_HAS_EDU
+	release_mem_region(BREG_PA(EDU), BREG_LEN(EDU));
+#endif
+	release_mem_region(BREG_PA(NAND), BREG_LEN(NAND));
+}
+
+module_init(brcmstb_nand_init);
+module_exit(brcmstb_nand_exit);
+
+#ifdef CONFIG_OF
+
+static int __devinit brcm_nand_controller_probe(struct platform_device *pdev)
+{
+	struct device_node *dn = pdev->dev.of_node;
+	return of_platform_populate(dn, brcmstb_nand_of_match, NULL, NULL);
+}
+
+static const struct of_device_id brcm_nand_controller_match[] = {
+	{ .compatible = "brcm,brcmnand" },
+	{},
+};
+
+static struct platform_driver brcm_nand_controller_driver = {
+	.driver = {
+		.name = "brcmnand-host",
+		.bus = &platform_bus_type,
+		.of_match_table = of_match_ptr(brcm_nand_controller_match),
+	}
+};
+
+/* Don't unbind/deregister this driver */
+static int __init brcm_nand_controller_init(void)
+{
+	return platform_driver_probe(&brcm_nand_controller_driver,
+			brcm_nand_controller_probe);
+}
+module_init(brcm_nand_controller_init);
+
+#endif /* CONFIG_OF */
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("NAND driver for STB chips");
diff --git a/drivers/mtd/nand/cafe_nand.c b/drivers/mtd/nand/cafe_nand.c
index 6d22755..756ff4b 100644
--- a/drivers/mtd/nand/cafe_nand.c
+++ b/drivers/mtd/nand/cafe_nand.c
@@ -364,23 +364,24 @@ static int cafe_nand_write_oob(struct mtd_info *mtd,
 
 /* Don't use -- use nand_read_oob_std for now */
 static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
-			      int page, int sndcmd)
+			      int page)
 {
 	chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
-	return 1;
+	return 0;
 }
 /**
  * cafe_nand_read_page_syndrome - [REPLACEABLE] hardware ecc syndrome based page read
  * @mtd:	mtd info structure
  * @chip:	nand chip info structure
  * @buf:	buffer to store read data
+ * @oob_required:	caller expects OOB data read to chip->oob_poi
  *
  * The hw generator calculates the error syndrome automatically. Therefor
  * we need a special oob layout and handling.
  */
 static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
-			       uint8_t *buf, int page)
+			       uint8_t *buf, int oob_required, int page)
 {
 	struct cafe_priv *cafe = mtd->priv;
 
@@ -518,7 +519,8 @@ static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
 
 
 static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
-					  struct nand_chip *chip, const uint8_t *buf)
+					  struct nand_chip *chip,
+					  const uint8_t *buf, int oob_required)
 {
 	struct cafe_priv *cafe = mtd->priv;
 
@@ -530,16 +532,17 @@ static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
 }
 
 static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
-				const uint8_t *buf, int page, int cached, int raw)
+				const uint8_t *buf, int oob_required, int page,
+				int cached, int raw)
 {
 	int status;
 
 	chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
 
 	if (unlikely(raw))
-		chip->ecc.write_page_raw(mtd, chip, buf);
+		chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
 	else
-		chip->ecc.write_page(mtd, chip, buf);
+		chip->ecc.write_page(mtd, chip, buf, oob_required);
 
 	/*
 	 * Cached progamming disabled for now, Not sure if its worth the
@@ -685,7 +688,7 @@ static int __devinit cafe_nand_probe(struct pci_dev *pdev,
 
 	/* Enable the following for a flash based bad block table */
 	cafe->nand.bbt_options = NAND_BBT_USE_FLASH;
-	cafe->nand.options = NAND_NO_AUTOINCR | NAND_OWN_BUFFERS;
+	cafe->nand.options = NAND_OWN_BUFFERS;
 
 	if (skipbbt) {
 		cafe->nand.options |= NAND_SKIP_BBTSCAN;
diff --git a/drivers/mtd/nand/cs553x_nand.c b/drivers/mtd/nand/cs553x_nand.c
index 0b9b472..2cdeab8 100644
--- a/drivers/mtd/nand/cs553x_nand.c
+++ b/drivers/mtd/nand/cs553x_nand.c
@@ -241,7 +241,6 @@ static int __init cs553x_init_one(int cs, int mmio, unsigned long adr)
 
 	/* Enable the following for a flash based bad block table */
 	this->bbt_options = NAND_BBT_USE_FLASH;
-	this->options = NAND_NO_AUTOINCR;
 
 	/* Scan to find existence of the device */
 	if (nand_scan(new_mtd, 1)) {
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index a9e57d6..1febaeb 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -1084,7 +1084,7 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
  * by write_page above.
  * */
 static void denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
-				const uint8_t *buf)
+				const uint8_t *buf, int oob_required)
 {
 	/* for regular page writes, we let HW handle all the ECC
 	 * data written to the device. */
@@ -1096,7 +1096,7 @@ static void denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  * write_page() function above.
  */
 static void denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
-					const uint8_t *buf)
+					const uint8_t *buf, int oob_required)
 {
 	/* for raw page writes, we want to disable ECC and simply write
 	   whatever data is in the buffer. */
@@ -1110,16 +1110,15 @@ static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
 }
 
 static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
-			   int page, int sndcmd)
+			   int page)
 {
 	read_oob_data(mtd, chip->oob_poi, page);
 
-	return 0; /* notify NAND core to send command to
-			   NAND device. */
+	return 0;
 }
 
 static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
-			    uint8_t *buf, int page)
+			    uint8_t *buf, int oob_required, int page)
 {
 	struct denali_nand_info *denali = mtd_to_denali(mtd);
 
@@ -1171,7 +1170,7 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 }
 
 static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
-				uint8_t *buf, int page)
+				uint8_t *buf, int oob_required, int page)
 {
 	struct denali_nand_info *denali = mtd_to_denali(mtd);
 
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 80b5264..909ce92 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -738,13 +738,12 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
 	return 0;
 }
 
-static int fsl_elbc_read_page(struct mtd_info *mtd,
-                              struct nand_chip *chip,
-			      uint8_t *buf,
-			      int page)
+static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
+			      uint8_t *buf, int oob_required, int page)
 {
 	fsl_elbc_read_buf(mtd, buf, mtd->writesize);
-	fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
+	if (oob_required)
+		fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 
 	if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
 		mtd->ecc_stats.failed++;
@@ -755,9 +754,8 @@ static int fsl_elbc_read_page(struct mtd_info *mtd,
 /* ECC will be calculated automatically, and errors will be detected in
  * waitfunc.
  */
-static void fsl_elbc_write_page(struct mtd_info *mtd,
-                                struct nand_chip *chip,
-                                const uint8_t *buf)
+static void fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+				const uint8_t *buf, int oob_required)
 {
 	fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 	fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
@@ -795,7 +793,7 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
 	chip->bbt_md = &bbt_mirror_descr;
 
 	/* set up nand options */
-	chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR;
+	chip->options = NAND_NO_READRDY;
 	chip->bbt_options = NAND_BBT_USE_FLASH;
 
 	chip->controller = &elbc_fcm_ctrl->controller;
diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 1b8330e..4ce70b9 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -692,6 +692,7 @@ static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
  * @mtd:	mtd info structure
  * @chip:	nand chip info structure
  * @buf:	buffer to store read data
+ * @oob_required:	caller expects OOB data read to chip->oob_poi
  * @page:	page number to read
  *
  * This routine is needed for fsmc version 8 as reading from NAND chip has to be
@@ -701,7 +702,7 @@ static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
  * max of 8 bits)
  */
 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
-				 uint8_t *buf, int page)
+				 uint8_t *buf, int oob_required, int page)
 {
 	struct fsmc_nand_data *host = container_of(mtd,
 					struct fsmc_nand_data, mtd);
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index 0f000e6..52b7440 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
@@ -842,7 +842,7 @@ static void block_mark_swapping(struct gpmi_nand_data *this,
 }
 
 static int gpmi_ecc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
-				uint8_t *buf, int page)
+				uint8_t *buf, int oob_required, int page)
 {
 	struct gpmi_nand_data *this = chip->priv;
 	struct bch_geometry *nfc_geo = &this->bch_geometry;
@@ -908,28 +908,31 @@ static int gpmi_ecc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 		mtd->ecc_stats.corrected += corrected;
 	}
 
-	/*
-	 * It's time to deliver the OOB bytes. See gpmi_ecc_read_oob() for
-	 * details about our policy for delivering the OOB.
-	 *
-	 * We fill the caller's buffer with set bits, and then copy the block
-	 * mark to th caller's buffer. Note that, if block mark swapping was
-	 * necessary, it has already been done, so we can rely on the first
-	 * byte of the auxiliary buffer to contain the block mark.
-	 */
-	memset(chip->oob_poi, ~0, mtd->oobsize);
-	chip->oob_poi[0] = ((uint8_t *) auxiliary_virt)[0];
+	if (oob_required) {
+		/*
+		 * It's time to deliver the OOB bytes. See gpmi_ecc_read_oob()
+		 * for details about our policy for delivering the OOB.
+		 *
+		 * We fill the caller's buffer with set bits, and then copy the
+		 * block mark to th caller's buffer. Note that, if block mark
+		 * swapping was necessary, it has already been done, so we can
+		 * rely on the first byte of the auxiliary buffer to contain
+		 * the block mark.
+		 */
+		memset(chip->oob_poi, ~0, mtd->oobsize);
+		chip->oob_poi[0] = ((uint8_t *) auxiliary_virt)[0];
 
-	read_page_swap_end(this, buf, mtd->writesize,
-			this->payload_virt, this->payload_phys,
-			nfc_geo->payload_size,
-			payload_virt, payload_phys);
+		read_page_swap_end(this, buf, mtd->writesize,
+				this->payload_virt, this->payload_phys,
+				nfc_geo->payload_size,
+				payload_virt, payload_phys);
+	}
 exit_nfc:
 	return ret;
 }
 
-static void gpmi_ecc_write_page(struct mtd_info *mtd,
-				struct nand_chip *chip, const uint8_t *buf)
+static void gpmi_ecc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+				const uint8_t *buf, int oob_required)
 {
 	struct gpmi_nand_data *this = chip->priv;
 	struct bch_geometry *nfc_geo = &this->bch_geometry;
@@ -1068,7 +1071,7 @@ exit_auxiliary:
  * this driver.
  */
 static int gpmi_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
-				int page, int sndcmd)
+				int page)
 {
 	struct gpmi_nand_data *this = chip->priv;
 
@@ -1091,11 +1094,7 @@ static int gpmi_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 		chip->oob_poi[0] = chip->read_byte(mtd);
 	}
 
-	/*
-	 * Return true, indicating that the next call to this function must send
-	 * a command.
-	 */
-	return true;
+	return 0;
 }
 
 static int
@@ -1309,7 +1308,7 @@ static int mx23_write_transcription_stamp(struct gpmi_nand_data *this)
 		/* Write the first page of the current stride. */
 		dev_dbg(dev, "Writing an NCB fingerprint in page 0x%x\n", page);
 		chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
-		chip->ecc.write_page_raw(mtd, chip, buffer);
+		chip->ecc.write_page_raw(mtd, chip, buffer, 0);
 		chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 
 		/* Wait for the write to finish. */
diff --git a/drivers/mtd/nand/h1910.c b/drivers/mtd/nand/h1910.c
index 11e48781..85e55a5 100644
--- a/drivers/mtd/nand/h1910.c
+++ b/drivers/mtd/nand/h1910.c
@@ -124,7 +124,6 @@ static int __init h1910_init(void)
 	/* 15 us command delay time */
 	this->chip_delay = 50;
 	this->ecc.mode = NAND_ECC_SOFT;
-	this->options = NAND_NO_AUTOINCR;
 
 	/* Scan to find existence of the device */
 	if (nand_scan(h1910_nand_mtd, 1)) {
diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
index c240cf1..c259c24 100644
--- a/drivers/mtd/nand/mpc5121_nfc.c
+++ b/drivers/mtd/nand/mpc5121_nfc.c
@@ -734,7 +734,6 @@ static int __devinit mpc5121_nfc_probe(struct platform_device *op)
 	chip->write_buf = mpc5121_nfc_write_buf;
 	chip->verify_buf = mpc5121_nfc_verify_buf;
 	chip->select_chip = mpc5121_nfc_select_chip;
-	chip->options = NAND_NO_AUTOINCR;
 	chip->bbt_options = NAND_BBT_USE_FLASH;
 	chip->ecc.mode = NAND_ECC_SOFT;
 
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index e50a0b4..9580783 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -1066,15 +1066,17 @@ EXPORT_SYMBOL(nand_lock);
  * @mtd: mtd info structure
  * @chip: nand chip info structure
  * @buf: buffer to store read data
+ * @oob_required: caller requires OOB data read to chip->oob_poi
  * @page: page number to read
  *
  * Not for syndrome calculating ECC controllers, which use a special oob layout.
  */
 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
-			      uint8_t *buf, int page)
+			      uint8_t *buf, int oob_required, int page)
 {
 	chip->read_buf(mtd, buf, mtd->writesize);
-	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+	if (oob_required)
+		chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 	return 0;
 }
 
@@ -1083,13 +1085,14 @@ static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  * @mtd: mtd info structure
  * @chip: nand chip info structure
  * @buf: buffer to store read data
+ * @oob_required: caller requires OOB data read to chip->oob_poi
  * @page: page number to read
  *
  * We need a special oob layout and handling even when OOB isn't used.
  */
 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
-					struct nand_chip *chip,
-					uint8_t *buf, int page)
+				       struct nand_chip *chip, uint8_t *buf,
+				       int oob_required, int page)
 {
 	int eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -1126,10 +1129,11 @@ static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
  * @mtd: mtd info structure
  * @chip: nand chip info structure
  * @buf: buffer to store read data
+ * @oob_required: caller requires OOB data read to chip->oob_poi
  * @page: page number to read
  */
 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
-				uint8_t *buf, int page)
+				uint8_t *buf, int oob_required, int page)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -1139,7 +1143,7 @@ static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 	uint8_t *ecc_code = chip->buffers->ecccode;
 	uint32_t *eccpos = chip->ecc.layout->eccpos;
 
-	chip->ecc.read_page_raw(mtd, chip, buf, page);
+	chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
 
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
@@ -1257,12 +1261,13 @@ static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
  * @mtd: mtd info structure
  * @chip: nand chip info structure
  * @buf: buffer to store read data
+ * @oob_required: caller requires OOB data read to chip->oob_poi
  * @page: page number to read
  *
  * Not for syndrome calculating ECC controllers which need a special oob layout.
  */
 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
-				uint8_t *buf, int page)
+				uint8_t *buf, int oob_required, int page)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -1302,6 +1307,7 @@ static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  * @mtd: mtd info structure
  * @chip: nand chip info structure
  * @buf: buffer to store read data
+ * @oob_required: caller requires OOB data read to chip->oob_poi
  * @page: page number to read
  *
  * Hardware ECC for large page chips, require OOB to be read first. For this
@@ -1311,7 +1317,7 @@ static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  * the data area, by overwriting the NAND manufacturer bad block markings.
  */
 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
-	struct nand_chip *chip, uint8_t *buf, int page)
+	struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -1350,13 +1356,14 @@ static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
  * @mtd: mtd info structure
  * @chip: nand chip info structure
  * @buf: buffer to store read data
+ * @oob_required: caller requires OOB data read to chip->oob_poi
  * @page: page number to read
  *
  * The hw generator calculates the error syndrome automatically. Therefore we
  * need a special oob layout and handling.
  */
 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
-				   uint8_t *buf, int page)
+				   uint8_t *buf, int oob_required, int page)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -1459,11 +1466,9 @@ static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
 			    struct mtd_oob_ops *ops)
 {
-	int chipnr, page, realpage, col, bytes, aligned;
+	int chipnr, page, realpage, col, bytes, aligned, oob_required;
 	struct nand_chip *chip = mtd->priv;
 	struct mtd_ecc_stats stats;
-	int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
-	int sndcmd = 1;
 	int ret = 0;
 	uint32_t readlen = ops->len;
 	uint32_t oobreadlen = ops->ooblen;
@@ -1484,6 +1489,7 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
 
 	buf = ops->datbuf;
 	oob = ops->oobbuf;
+	oob_required = oob ? 1 : 0;
 
 	while (1) {
 		bytes = min(mtd->writesize - col, readlen);
@@ -1493,21 +1499,19 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
 		if (realpage != chip->pagebuf || oob) {
 			bufpoi = aligned ? buf : chip->buffers->databuf;
 
-			if (likely(sndcmd)) {
-				chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
-				sndcmd = 0;
-			}
+			chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
 
 			/* Now read the page into the buffer */
 			if (unlikely(ops->mode == MTD_OPS_RAW))
-				ret = chip->ecc.read_page_raw(mtd, chip,
-							      bufpoi, page);
+				ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
+							      oob_required,
+							      page);
 			else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
 				ret = chip->ecc.read_subpage(mtd, chip,
 							col, bytes, bufpoi);
 			else
 				ret = chip->ecc.read_page(mtd, chip, bufpoi,
-							  page);
+							  oob_required, page);
 			if (ret < 0) {
 				if (!aligned)
 					/* Invalidate page cache */
@@ -1530,7 +1534,6 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
 			buf += bytes;
 
 			if (unlikely(oob)) {
-
 				int toread = min(oobreadlen, max_oobsize);
 
 				if (toread) {
@@ -1541,13 +1544,7 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
 			}
 
 			if (!(chip->options & NAND_NO_READRDY)) {
-				/*
-				 * Apply delay or wait for ready/busy pin. Do
-				 * this before the AUTOINCR check, so no
-				 * problems arise if a chip which does auto
-				 * increment is marked as NOAUTOINCR by the
-				 * board driver.
-				 */
+				/* Apply delay or wait for ready/busy pin */
 				if (!chip->dev_ready)
 					udelay(chip->chip_delay);
 				else
@@ -1575,13 +1572,6 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
 			chip->select_chip(mtd, -1);
 			chip->select_chip(mtd, chipnr);
 		}
-
-		/*
-		 * Check, if the chip supports auto page increment or if we
-		 * have hit a block boundary.
-		 */
-		if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
-			sndcmd = 1;
 	}
 
 	ops->retlen = ops->len - (size_t) readlen;
@@ -1630,17 +1620,13 @@ static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
  * @mtd: mtd info structure
  * @chip: nand chip info structure
  * @page: page number to read
- * @sndcmd: flag whether to issue read command or not
  */
 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
-			     int page, int sndcmd)
+			     int page)
 {
-	if (sndcmd) {
-		chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
-		sndcmd = 0;
-	}
+	chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
-	return sndcmd;
+	return 0;
 }
 
 /**
@@ -1649,10 +1635,9 @@ static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
  * @mtd: mtd info structure
  * @chip: nand chip info structure
  * @page: page number to read
- * @sndcmd: flag whether to issue read command or not
  */
 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
-				  int page, int sndcmd)
+				  int page)
 {
 	uint8_t *buf = chip->oob_poi;
 	int length = mtd->oobsize;
@@ -1679,7 +1664,7 @@ static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
 	if (length > 0)
 		chip->read_buf(mtd, bufpoi, length);
 
-	return 1;
+	return 0;
 }
 
 /**
@@ -1775,13 +1760,13 @@ static int nand_write_oob_syndrome(struct mtd_info *mtd,
 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
 			    struct mtd_oob_ops *ops)
 {
-	int page, realpage, chipnr, sndcmd = 1;
+	int page, realpage, chipnr;
 	struct nand_chip *chip = mtd->priv;
 	struct mtd_ecc_stats stats;
-	int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
 	int readlen = ops->ooblen;
 	int len;
 	uint8_t *buf = ops->oobbuf;
+	int ret = 0;
 
 	pr_debug("%s: from = 0x%08Lx, len = %i\n",
 			__func__, (unsigned long long)from, readlen);
@@ -1817,20 +1802,18 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
 
 	while (1) {
 		if (ops->mode == MTD_OPS_RAW)
-			sndcmd = chip->ecc.read_oob_raw(mtd, chip, page, sndcmd);
+			ret = chip->ecc.read_oob_raw(mtd, chip, page);
 		else
-			sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
+			ret = chip->ecc.read_oob(mtd, chip, page);
+
+		if (ret < 0)
+			break;
 
 		len = min(len, readlen);
 		buf = nand_transfer_oob(chip, buf, ops, len);
 
 		if (!(chip->options & NAND_NO_READRDY)) {
-			/*
-			 * Apply delay or wait for ready/busy pin. Do this
-			 * before the AUTOINCR check, so no problems arise if a
-			 * chip which does auto increment is marked as
-			 * NOAUTOINCR by the board driver.
-			 */
+			/* Apply delay or wait for ready/busy pin */
 			if (!chip->dev_ready)
 				udelay(chip->chip_delay);
 			else
@@ -1851,16 +1834,12 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
 			chip->select_chip(mtd, -1);
 			chip->select_chip(mtd, chipnr);
 		}
-
-		/*
-		 * Check, if the chip supports auto page increment or if we
-		 * have hit a block boundary.
-		 */
-		if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
-			sndcmd = 1;
 	}
 
-	ops->oobretlen = ops->ooblen;
+	ops->oobretlen = ops->ooblen - readlen;
+
+	if (ret < 0)
+		return ret;
 
 	if (mtd->ecc_stats.failed - stats.failed)
 		return -EBADMSG;
@@ -1919,14 +1898,16 @@ out:
  * @mtd: mtd info structure
  * @chip: nand chip info structure
  * @buf: data buffer
+ * @oob_required: must write chip->oob_poi to OOB
  *
  * Not for syndrome calculating ECC controllers, which use a special oob layout.
  */
 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
-				const uint8_t *buf)
+				const uint8_t *buf, int oob_required)
 {
 	chip->write_buf(mtd, buf, mtd->writesize);
-	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+	if (oob_required)
+		chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 }
 
 /**
@@ -1934,12 +1915,13 @@ static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  * @mtd: mtd info structure
  * @chip: nand chip info structure
  * @buf: data buffer
+ * @oob_required: must write chip->oob_poi to OOB
  *
  * We need a special oob layout and handling even when ECC isn't checked.
  */
 static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
 					struct nand_chip *chip,
-					const uint8_t *buf)
+					const uint8_t *buf, int oob_required)
 {
 	int eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -1973,9 +1955,10 @@ static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
  * @mtd: mtd info structure
  * @chip: nand chip info structure
  * @buf: data buffer
+ * @oob_required: must write chip->oob_poi to OOB
  */
 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
-				  const uint8_t *buf)
+				  const uint8_t *buf, int oob_required)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -1991,7 +1974,7 @@ static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 	for (i = 0; i < chip->ecc.total; i++)
 		chip->oob_poi[eccpos[i]] = ecc_calc[i];
 
-	chip->ecc.write_page_raw(mtd, chip, buf);
+	chip->ecc.write_page_raw(mtd, chip, buf, 1);
 }
 
 /**
@@ -1999,9 +1982,10 @@ static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
  * @mtd: mtd info structure
  * @chip: nand chip info structure
  * @buf: data buffer
+ * @oob_required: must write chip->oob_poi to OOB
  */
 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
-				  const uint8_t *buf)
+				  const uint8_t *buf, int oob_required)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -2027,12 +2011,14 @@ static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  * @mtd: mtd info structure
  * @chip: nand chip info structure
  * @buf: data buffer
+ * @oob_required: must write chip->oob_poi to OOB
  *
  * The hw generator calculates the error syndrome automatically. Therefore we
  * need a special oob layout and handling.
  */
 static void nand_write_page_syndrome(struct mtd_info *mtd,
-				    struct nand_chip *chip, const uint8_t *buf)
+				    struct nand_chip *chip,
+				    const uint8_t *buf, int oob_required)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -2071,21 +2057,23 @@ static void nand_write_page_syndrome(struct mtd_info *mtd,
  * @mtd: MTD device structure
  * @chip: NAND chip descriptor
  * @buf: the data to write
+ * @oob_required: must write chip->oob_poi to OOB
  * @page: page number to write
  * @cached: cached programming
  * @raw: use _raw version of write_page
  */
 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
-			   const uint8_t *buf, int page, int cached, int raw)
+			   const uint8_t *buf, int oob_required, int page,
+			   int cached, int raw)
 {
 	int status;
 
 	chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
 
 	if (unlikely(raw))
-		chip->ecc.write_page_raw(mtd, chip, buf);
+		chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
 	else
-		chip->ecc.write_page(mtd, chip, buf);
+		chip->ecc.write_page(mtd, chip, buf, oob_required);
 
 	/*
 	 * Cached progamming disabled for now. Not sure if it's worth the
@@ -2202,6 +2190,7 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
 	uint8_t *oob = ops->oobbuf;
 	uint8_t *buf = ops->datbuf;
 	int ret, subpage;
+	int oob_required = oob ? 1 : 0;
 
 	ops->retlen = 0;
 	if (!writelen)
@@ -2264,8 +2253,8 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
 			memset(chip->oob_poi, 0xff, mtd->oobsize);
 		}
 
-		ret = chip->write_page(mtd, chip, wbuf, page, cached,
-				       (ops->mode == MTD_OPS_RAW));
+		ret = chip->write_page(mtd, chip, wbuf, oob_required, page,
+				       cached, (ops->mode == MTD_OPS_RAW));
 		if (ret)
 			break;
 
@@ -2908,13 +2897,270 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
 	if (le16_to_cpu(p->features) & 1)
 		*busw = NAND_BUSWIDTH_16;
 
-	chip->options |= NAND_NO_READRDY | NAND_NO_AUTOINCR;
+	chip->options |= NAND_NO_READRDY;
 
 	pr_info("ONFI flash detected\n");
 	return 1;
 }
 
 /*
+ * nand_id_has_period - Check if an ID string has a given wraparound period
+ * @id_data: the ID string
+ * @arrlen: the length of the @id_data array
+ * @period: the period of repitition
+ *
+ * Check if an ID string is repeated within a given sequence of bytes at
+ * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
+ * period of 3). This is a helper function for nand_id_len(). Returns non-zero
+ * if the repetition has a period of @period; otherwise, returns zero.
+ */
+static int nand_id_has_period(u8 *id_data, int arrlen, int period)
+{
+	int i, j;
+	for (i = 0; i < period; i++)
+		for (j = i + period; j < arrlen; j += period)
+			if (id_data[i] != id_data[j])
+				return 0;
+	return 1;
+}
+
+/*
+ * nand_id_len - Get the length of an ID string returned by CMD_READID
+ * @id_data: the ID string
+ * @arrlen: the length of the @id_data array
+
+ * Returns the length of the ID string, according to known wraparound/trailing
+ * zero patterns. If no pattern exists, returns the length of the array.
+ */
+static int nand_id_len(u8 *id_data, int arrlen)
+{
+	int last_nonzero, period;
+
+	/* Find last non-zero byte */
+	for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
+		if (id_data[last_nonzero])
+			break;
+
+	/* All zeros */
+	if (last_nonzero < 0)
+		return 0;
+
+	/* Calculate wraparound period */
+	for (period = 1; period < arrlen; period++)
+		if (nand_id_has_period(id_data, arrlen, period))
+			break;
+
+	/* There's a repeated pattern */
+	if (period < arrlen)
+		return period;
+
+	/* There are trailing zeros */
+	if (last_nonzero < arrlen - 1)
+		return last_nonzero + 1;
+
+	/* No pattern detected */
+	return arrlen;
+}
+
+/*
+ * Many new NAND share similar device ID codes, which represent the size of the
+ * chip. The rest of the parameters must be decoded according to generic or
+ * manufacturer-specific "extended ID" decoding patterns.
+ */
+static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
+				u8 id_data[8], int *busw)
+{
+	int extid, id_len;
+	/* The 3rd id byte holds MLC / multichip data */
+	chip->cellinfo = id_data[2];
+	/* The 4th id byte is the important one */
+	extid = id_data[3];
+
+	id_len = nand_id_len(id_data, 8);
+
+	/*
+	 * Field definitions are in the following datasheets:
+	 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
+	 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
+	 * Hynix MLC   (6 byte ID): Hynix H27UBG8T2B (p.22)
+	 *
+	 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
+	 * ID to decide what to do.
+	 */
+	if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
+			(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
+			id_data[5] != 0x00) {
+		/* Calc pagesize */
+		mtd->writesize = 2048 << (extid & 0x03);
+		extid >>= 2;
+		/* Calc oobsize */
+		switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
+		case 1:
+			mtd->oobsize = 128;
+			break;
+		case 2:
+			mtd->oobsize = 218;
+			break;
+		case 3:
+			mtd->oobsize = 400;
+			break;
+		case 4:
+			mtd->oobsize = 436;
+			break;
+		case 5:
+			mtd->oobsize = 512;
+			break;
+		case 6:
+		default: /* Other cases are "reserved" (unknown) */
+			mtd->oobsize = 640;
+			break;
+		}
+		extid >>= 2;
+		/* Calc blocksize */
+		mtd->erasesize = (128 * 1024) <<
+			(((extid >> 1) & 0x04) | (extid & 0x03));
+		*busw = 0;
+	} else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
+			(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
+		unsigned int tmp;
+
+		/* Calc pagesize */
+		mtd->writesize = 2048 << (extid & 0x03);
+		extid >>= 2;
+		/* Calc oobsize */
+		switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
+		case 0:
+			mtd->oobsize = 128;
+			break;
+		case 1:
+			mtd->oobsize = 224;
+			break;
+		case 2:
+			mtd->oobsize = 448;
+			break;
+		case 3:
+			mtd->oobsize = 64;
+			break;
+		case 4:
+			mtd->oobsize = 32;
+			break;
+		case 5:
+			mtd->oobsize = 16;
+			break;
+		default:
+			mtd->oobsize = 640;
+			break;
+		}
+		extid >>= 2;
+		/* Calc blocksize */
+		tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
+		if (tmp < 0x03)
+			mtd->erasesize = (128 * 1024) << tmp;
+		else if (tmp == 0x03)
+			mtd->erasesize = 768 * 1024;
+		else
+			mtd->erasesize = (64 * 1024) << tmp;
+		*busw = 0;
+	} else {
+		/* Calc pagesize */
+		mtd->writesize = 1024 << (extid & 0x03);
+		extid >>= 2;
+		/* Calc oobsize */
+		mtd->oobsize = (8 << (extid & 0x01)) *
+			(mtd->writesize >> 9);
+		extid >>= 2;
+		/* Calc blocksize. Blocksize is multiples of 64KiB */
+		mtd->erasesize = (64 * 1024) << (extid & 0x03);
+		extid >>= 2;
+		/* Get buswidth information */
+		*busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
+
+		/*
+		 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
+		 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
+		 * follows:
+		 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
+		 *                         110b -> 24nm
+		 * - ID byte 5, bit[7]:    1 -> BENAND, 0 -> raw SLC
+		 */
+		if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
+				!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
+				(id_data[5] & 0x7) == 0x6 /* 24nm */ &&
+				!(id_data[4] & 0x80) /* !BENAND */) {
+			mtd->oobsize = 32 * mtd->writesize >> 9;
+		}
+
+	}
+}
+
+/*
+ * Old devices have chip data hardcoded in the device ID table. nand_decode_id
+ * decodes a matching ID table entry and assigns the MTD size parameters for
+ * the chip.
+ */
+static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
+				struct nand_flash_dev *type, u8 id_data[8],
+				int *busw)
+{
+	int maf_id = id_data[0];
+
+	mtd->erasesize = type->erasesize;
+	mtd->writesize = type->pagesize;
+	mtd->oobsize = mtd->writesize / 32;
+	*busw = type->options & NAND_BUSWIDTH_16;
+
+	/*
+	 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
+	 * some Spansion chips have erasesize that conflicts with size
+	 * listed in nand_ids table.
+	 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
+	 */
+	if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
+			&& id_data[6] == 0x00 && id_data[7] == 0x00
+			&& mtd->writesize == 512) {
+		mtd->erasesize = 128 * 1024;
+		mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
+	}
+}
+
+/*
+ * Set the bad block marker/indicator (BBM/BBI) patterns according to some
+ * heuristic patterns using various detected parameters (e.g., manufacturer,
+ * page size, cell-type information).
+ */
+static void nand_decode_bbm_options(struct mtd_info *mtd,
+				    struct nand_chip *chip, u8 id_data[8])
+{
+	int maf_id = id_data[0];
+
+	/* Set the bad block position */
+	if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
+		chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
+	else
+		chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
+
+	/*
+	 * Bad block marker is stored in the last page of each block on Samsung
+	 * and Hynix MLC devices; stored in first two pages of each block on
+	 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
+	 * AMD/Spansion, and Macronix.  All others scan only the first page.
+	 */
+	if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
+			(maf_id == NAND_MFR_SAMSUNG ||
+			 maf_id == NAND_MFR_HYNIX))
+		chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
+	else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
+				(maf_id == NAND_MFR_SAMSUNG ||
+				 maf_id == NAND_MFR_HYNIX ||
+				 maf_id == NAND_MFR_TOSHIBA ||
+				 maf_id == NAND_MFR_AMD ||
+				 maf_id == NAND_MFR_MACRONIX)) ||
+			(mtd->writesize == 2048 &&
+			 maf_id == NAND_MFR_MICRON))
+		chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
+}
+
+/*
  * Get the flash and manufacturer id and lookup if the type is supported.
  */
 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
@@ -2925,7 +3171,6 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 {
 	int i, maf_idx;
 	u8 id_data[8];
-	int ret;
 
 	/* Select the device */
 	chip->select_chip(mtd, 0);
@@ -2952,7 +3197,8 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 
 	chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
 
-	for (i = 0; i < 2; i++)
+	/* Read entire ID string */
+	for (i = 0; i < 8; i++)
 		id_data[i] = chip->read_byte(mtd);
 
 	if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
@@ -2972,18 +3218,10 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 	chip->onfi_version = 0;
 	if (!type->name || !type->pagesize) {
 		/* Check is chip is ONFI compliant */
-		ret = nand_flash_detect_onfi(mtd, chip, &busw);
-		if (ret)
+		if (nand_flash_detect_onfi(mtd, chip, &busw))
 			goto ident_done;
 	}
 
-	chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
-
-	/* Read entire ID string */
-
-	for (i = 0; i < 8; i++)
-		id_data[i] = chip->read_byte(mtd);
-
 	if (!type->name)
 		return ERR_PTR(-ENODEV);
 
@@ -2996,82 +3234,10 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 		/* Set the pagesize, oobsize, erasesize by the driver */
 		busw = chip->init_size(mtd, chip, id_data);
 	} else if (!type->pagesize) {
-		int extid;
-		/* The 3rd id byte holds MLC / multichip data */
-		chip->cellinfo = id_data[2];
-		/* The 4th id byte is the important one */
-		extid = id_data[3];
-
-		/*
-		 * Field definitions are in the following datasheets:
-		 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
-		 * New style   (6 byte ID): Samsung K9GBG08U0M (p.40)
-		 *
-		 * Check for wraparound + Samsung ID + nonzero 6th byte
-		 * to decide what to do.
-		 */
-		if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
-				id_data[0] == NAND_MFR_SAMSUNG &&
-				(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
-				id_data[5] != 0x00) {
-			/* Calc pagesize */
-			mtd->writesize = 2048 << (extid & 0x03);
-			extid >>= 2;
-			/* Calc oobsize */
-			switch (extid & 0x03) {
-			case 1:
-				mtd->oobsize = 128;
-				break;
-			case 2:
-				mtd->oobsize = 218;
-				break;
-			case 3:
-				mtd->oobsize = 400;
-				break;
-			default:
-				mtd->oobsize = 436;
-				break;
-			}
-			extid >>= 2;
-			/* Calc blocksize */
-			mtd->erasesize = (128 * 1024) <<
-				(((extid >> 1) & 0x04) | (extid & 0x03));
-			busw = 0;
-		} else {
-			/* Calc pagesize */
-			mtd->writesize = 1024 << (extid & 0x03);
-			extid >>= 2;
-			/* Calc oobsize */
-			mtd->oobsize = (8 << (extid & 0x01)) *
-				(mtd->writesize >> 9);
-			extid >>= 2;
-			/* Calc blocksize. Blocksize is multiples of 64KiB */
-			mtd->erasesize = (64 * 1024) << (extid & 0x03);
-			extid >>= 2;
-			/* Get buswidth information */
-			busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
-		}
+		/* Decode parameters from extended ID */
+		nand_decode_ext_id(mtd, chip, id_data, &busw);
 	} else {
-		/*
-		 * Old devices have chip data hardcoded in the device id table.
-		 */
-		mtd->erasesize = type->erasesize;
-		mtd->writesize = type->pagesize;
-		mtd->oobsize = mtd->writesize / 32;
-		busw = type->options & NAND_BUSWIDTH_16;
-
-		/*
-		 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
-		 * some Spansion chips have erasesize that conflicts with size
-		 * listed in nand_ids table.
-		 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
-		 */
-		if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
-				id_data[5] == 0x00 && id_data[6] == 0x00 &&
-				id_data[7] == 0x00 && mtd->writesize == 512) {
-			mtd->erasesize = 128 * 1024;
-			mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
-		}
+		nand_decode_id(mtd, chip, type, id_data, &busw);
 	}
 	/* Get chip options */
 	chip->options |= type->options;
@@ -3084,11 +3250,6 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 		chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
 ident_done:
 
-	/*
-	 * Set chip as a default. Board drivers can override it, if necessary.
-	 */
-	chip->options |= NAND_NO_AUTOINCR;
-
 	/* Try to identify manufacturer */
 	for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
 		if (nand_manuf_ids[maf_idx].id == *maf_id)
@@ -3109,6 +3270,8 @@ ident_done:
 		return ERR_PTR(-EINVAL);
 	}
 
+	nand_decode_bbm_options(mtd, chip, id_data);
+
 	/* Calculate the address shift from the page size */
 	chip->page_shift = ffs(mtd->writesize) - 1;
 	/* Convert chipsize to number of pages per chip -1 */
@@ -3125,33 +3288,6 @@ ident_done:
 
 	chip->badblockbits = 8;
 
-	/* Set the bad block position */
-	if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
-		chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
-	else
-		chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
-
-	/*
-	 * Bad block marker is stored in the last page of each block
-	 * on Samsung and Hynix MLC devices; stored in first two pages
-	 * of each block on Micron devices with 2KiB pages and on
-	 * SLC Samsung, Hynix, Toshiba, AMD/Spansion, and Macronix.
-	 * All others scan only the first page.
-	 */
-	if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
-			(*maf_id == NAND_MFR_SAMSUNG ||
-			 *maf_id == NAND_MFR_HYNIX))
-		chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
-	else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
-				(*maf_id == NAND_MFR_SAMSUNG ||
-				 *maf_id == NAND_MFR_HYNIX ||
-				 *maf_id == NAND_MFR_TOSHIBA ||
-				 *maf_id == NAND_MFR_AMD ||
-				 *maf_id == NAND_MFR_MACRONIX)) ||
-			(mtd->writesize == 2048 &&
-			 *maf_id == NAND_MFR_MICRON))
-		chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
-
 	/* Check for AND chips with 4 page planes */
 	if (chip->options & NAND_4PAGE_ARRAY)
 		chip->erase_cmd = multi_erase_cmd;
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index af4fe8c..92baff1 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -70,7 +70,7 @@ struct nand_flash_dev nand_flash_ids[] = {
 	 * These are the new chips with large page size. The pagesize and the
 	 * erasesize is determined from the extended id bytes
 	 */
-#define LP_OPTIONS (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR)
+#define LP_OPTIONS (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY)
 #define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
 
 	/* 512 Megabit */
@@ -157,9 +157,7 @@ struct nand_flash_dev nand_flash_ids[] = {
 	 * writes possible, but not implemented now
 	 */
 	{"AND 128MiB 3,3V 8-bit",	0x01, 2048, 128, 0x4000,
-	 NAND_IS_AND | NAND_NO_AUTOINCR |NAND_NO_READRDY | NAND_4PAGE_ARRAY |
-	 BBT_AUTO_REFRESH
-	},
+	 NAND_IS_AND | NAND_NO_READRDY | NAND_4PAGE_ARRAY | BBT_AUTO_REFRESH},
 
 	{NULL,}
 };
@@ -176,8 +174,9 @@ struct nand_manufacturers nand_manuf_ids[] = {
 	{NAND_MFR_STMICRO, "ST Micro"},
 	{NAND_MFR_HYNIX, "Hynix"},
 	{NAND_MFR_MICRON, "Micron"},
-	{NAND_MFR_AMD, "AMD"},
+	{NAND_MFR_AMD, "AMD/Spansion"},
 	{NAND_MFR_MACRONIX, "Macronix"},
+	{NAND_MFR_EON, "Eon"},
 	{0x0, "Unknown"}
 };
 
diff --git a/drivers/mtd/nand/nandsim.c b/drivers/mtd/nand/nandsim.c
index b9cbd65..5d881180 100644
--- a/drivers/mtd/nand/nandsim.c
+++ b/drivers/mtd/nand/nandsim.c
@@ -268,7 +268,6 @@ MODULE_PARM_DESC(bch,		 "Enable BCH ecc and set how many bits should "
 #define OPT_PAGE512      0x00000002 /* 512-byte  page chips */
 #define OPT_PAGE2048     0x00000008 /* 2048-byte page chips */
 #define OPT_SMARTMEDIA   0x00000010 /* SmartMedia technology chips */
-#define OPT_AUTOINCR     0x00000020 /* page number auto incrementation is possible */
 #define OPT_PAGE512_8BIT 0x00000040 /* 512-byte page chips with 8-bit bus width */
 #define OPT_PAGE4096     0x00000080 /* 4096-byte page chips */
 #define OPT_LARGEPAGE    (OPT_PAGE2048 | OPT_PAGE4096) /* 2048 & 4096-byte page chips */
@@ -588,7 +587,7 @@ static int init_nandsim(struct mtd_info *mtd)
 		ns->options |= OPT_PAGE256;
 	}
 	else if (ns->geom.pgsz == 512) {
-		ns->options |= (OPT_PAGE512 | OPT_AUTOINCR);
+		ns->options |= OPT_PAGE512;
 		if (ns->busw == 8)
 			ns->options |= OPT_PAGE512_8BIT;
 	} else if (ns->geom.pgsz == 2048) {
@@ -657,8 +656,6 @@ static int init_nandsim(struct mtd_info *mtd)
         for (i = 0; nand_flash_ids[i].name != NULL; i++) {
                 if (second_id_byte != nand_flash_ids[i].id)
                         continue;
-		if (!(nand_flash_ids[i].options & NAND_NO_AUTOINCR))
-			ns->options |= OPT_AUTOINCR;
 	}
 
 	if (ns->busw == 16)
@@ -1930,20 +1927,8 @@ static u_char ns_nand_read_byte(struct mtd_info *mtd)
 	if (ns->regs.count == ns->regs.num) {
 		NS_DBG("read_byte: all bytes were read\n");
 
-		/*
-		 * The OPT_AUTOINCR allows to read next consecutive pages without
-		 * new read operation cycle.
-		 */
-		if ((ns->options & OPT_AUTOINCR) && NS_STATE(ns->state) == STATE_DATAOUT) {
-			ns->regs.count = 0;
-			if (ns->regs.row + 1 < ns->geom.pgnum)
-				ns->regs.row += 1;
-			NS_DBG("read_byte: switch to the next page (%#x)\n", ns->regs.row);
-			do_state_action(ns, ACTION_CPY);
-		}
-		else if (NS_STATE(ns->nxstate) == STATE_READY)
+		if (NS_STATE(ns->nxstate) == STATE_READY)
 			switch_state(ns);
-
 	}
 
 	return outb;
@@ -2197,14 +2182,7 @@ static void ns_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 	ns->regs.count += len;
 
 	if (ns->regs.count == ns->regs.num) {
-		if ((ns->options & OPT_AUTOINCR) && NS_STATE(ns->state) == STATE_DATAOUT) {
-			ns->regs.count = 0;
-			if (ns->regs.row + 1 < ns->geom.pgnum)
-				ns->regs.row += 1;
-			NS_DBG("read_buf: switch to the next page (%#x)\n", ns->regs.row);
-			do_state_action(ns, ACTION_CPY);
-		}
-		else if (NS_STATE(ns->nxstate) == STATE_READY)
+		if (NS_STATE(ns->nxstate) == STATE_READY)
 			switch_state(ns);
 	}
 
diff --git a/drivers/mtd/nand/pasemi_nand.c b/drivers/mtd/nand/pasemi_nand.c
index 974dbf8..1440e51 100644
--- a/drivers/mtd/nand/pasemi_nand.c
+++ b/drivers/mtd/nand/pasemi_nand.c
@@ -155,7 +155,6 @@ static int __devinit pasemi_nand_probe(struct platform_device *ofdev)
 	chip->ecc.mode = NAND_ECC_SOFT;
 
 	/* Enable the following for a flash based bad block table */
-	chip->options = NAND_NO_AUTOINCR;
 	chip->bbt_options = NAND_BBT_USE_FLASH;
 
 	/* Scan to find existence of the device */
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index fd11af4..32d3630 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -682,14 +682,15 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
 }
 
 static void pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
-		struct nand_chip *chip, const uint8_t *buf)
+		struct nand_chip *chip, const uint8_t *buf, int oob_required)
 {
 	chip->write_buf(mtd, buf, mtd->writesize);
 	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 }
 
 static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
-		struct nand_chip *chip, uint8_t *buf, int page)
+		struct nand_chip *chip, uint8_t *buf, int oob_required,
+		int page)
 {
 	struct pxa3xx_nand_host *host = mtd->priv;
 	struct pxa3xx_nand_info *info = host->info_data;
@@ -1004,7 +1005,6 @@ KEEP_CONFIG:
 	chip->ecc.size = host->page_size;
 	chip->ecc.strength = 1;
 
-	chip->options = NAND_NO_AUTOINCR;
 	chip->options |= NAND_NO_READRDY;
 	if (host->reg_ndcr & NDCR_DWIDTH_M)
 		chip->options |= NAND_BUSWIDTH_16;
diff --git a/drivers/mtd/nand/r852.c b/drivers/mtd/nand/r852.c
index c204018..b103568 100644
--- a/drivers/mtd/nand/r852.c
+++ b/drivers/mtd/nand/r852.c
@@ -539,14 +539,11 @@ exit:
  * nand_read_oob_syndrome assumes we can send column address - we can't
  */
 static int r852_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
-			     int page, int sndcmd)
+			     int page)
 {
-	if (sndcmd) {
-		chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
-		sndcmd = 0;
-	}
+	chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
-	return sndcmd;
+	return 0;
 }
 
 /*
diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
index e9b2b26..13e50b5 100644
--- a/drivers/mtd/nand/sh_flctl.c
+++ b/drivers/mtd/nand/sh_flctl.c
@@ -344,7 +344,7 @@ static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_va
 }
 
 static int flctl_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
-				uint8_t *buf, int page)
+				uint8_t *buf, int oob_required, int page)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -366,7 +366,7 @@ static int flctl_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 }
 
 static void flctl_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
-				   const uint8_t *buf)
+				   const uint8_t *buf, int oob_required)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -881,8 +881,6 @@ static int __devinit flctl_probe(struct platform_device *pdev)
 	flctl->hwecc = pdata->has_hwecc;
 	flctl->holden = pdata->use_holden;
 
-	nand->options = NAND_NO_AUTOINCR;
-
 	/* Set address of hardware control function */
 	/* 20 us command delay time */
 	nand->chip_delay = 20;
diff --git a/drivers/mtd/nand/sm_common.c b/drivers/mtd/nand/sm_common.c
index 774c3c2..082bcdc 100644
--- a/drivers/mtd/nand/sm_common.c
+++ b/drivers/mtd/nand/sm_common.c
@@ -94,17 +94,16 @@ static struct nand_flash_dev nand_smartmedia_flash_ids[] = {
 	{NULL,}
 };
 
-#define XD_TYPEM       (NAND_NO_AUTOINCR | NAND_BROKEN_XD)
 static struct nand_flash_dev nand_xd_flash_ids[] = {
 
 	{"xD 16MiB 3,3V",    0x73, 512, 16, 0x4000, 0},
 	{"xD 32MiB 3,3V",    0x75, 512, 32, 0x4000, 0},
 	{"xD 64MiB 3,3V",    0x76, 512, 64, 0x4000, 0},
 	{"xD 128MiB 3,3V",   0x79, 512, 128, 0x4000, 0},
-	{"xD 256MiB 3,3V",   0x71, 512, 256, 0x4000, XD_TYPEM},
-	{"xD 512MiB 3,3V",   0xdc, 512, 512, 0x4000, XD_TYPEM},
-	{"xD 1GiB 3,3V",     0xd3, 512, 1024, 0x4000, XD_TYPEM},
-	{"xD 2GiB 3,3V",     0xd5, 512, 2048, 0x4000, XD_TYPEM},
+	{"xD 256MiB 3,3V",   0x71, 512, 256, 0x4000, NAND_BROKEN_XD},
+	{"xD 512MiB 3,3V",   0xdc, 512, 512, 0x4000, NAND_BROKEN_XD},
+	{"xD 1GiB 3,3V",     0xd3, 512, 1024, 0x4000, NAND_BROKEN_XD},
+	{"xD 2GiB 3,3V",     0xd5, 512, 2048, 0x4000, NAND_BROKEN_XD},
 	{NULL,}
 };
 
diff --git a/drivers/mtd/tests/mtd_torturetest.c b/drivers/mtd/tests/mtd_torturetest.c
index b65861b..b3266a6 100644
--- a/drivers/mtd/tests/mtd_torturetest.c
+++ b/drivers/mtd/tests/mtd_torturetest.c
@@ -207,7 +207,7 @@ static inline int write_pattern(int ebnum, void *buf)
 static int __init tort_init(void)
 {
 	int err = 0, i, infinite = !cycles_count;
-	int bad_ebs[ebcnt];
+	int *bad_ebs;
 
 	printk(KERN_INFO "\n");
 	printk(KERN_INFO "=================================================\n");
@@ -249,28 +249,24 @@ static int __init tort_init(void)
 
 	err = -ENOMEM;
 	patt_5A5 = kmalloc(mtd->erasesize, GFP_KERNEL);
-	if (!patt_5A5) {
-		printk(PRINT_PREF "error: cannot allocate memory\n");
+	if (!patt_5A5)
 		goto out_mtd;
-	}
 
 	patt_A5A = kmalloc(mtd->erasesize, GFP_KERNEL);
-	if (!patt_A5A) {
-		printk(PRINT_PREF "error: cannot allocate memory\n");
+	if (!patt_A5A)
 		goto out_patt_5A5;
-	}
 
 	patt_FF = kmalloc(mtd->erasesize, GFP_KERNEL);
-	if (!patt_FF) {
-		printk(PRINT_PREF "error: cannot allocate memory\n");
+	if (!patt_FF)
 		goto out_patt_A5A;
-	}
 
 	check_buf = kmalloc(mtd->erasesize, GFP_KERNEL);
-	if (!check_buf) {
-		printk(PRINT_PREF "error: cannot allocate memory\n");
+	if (!check_buf)
 		goto out_patt_FF;
-	}
+
+	bad_ebs = kcalloc(ebcnt, sizeof(*bad_ebs), GFP_KERNEL);
+	if (!bad_ebs)
+		goto out_check_buf;
 
 	err = 0;
 
@@ -289,7 +285,6 @@ static int __init tort_init(void)
 	/*
 	 * Check if there is a bad eraseblock among those we are going to test.
 	 */
-	memset(&bad_ebs[0], 0, sizeof(int) * ebcnt);
 	if (mtd_can_have_bb(mtd)) {
 		for (i = eb; i < eb + ebcnt; i++) {
 			err = mtd_block_isbad(mtd, (loff_t)i * mtd->erasesize);
@@ -393,6 +388,8 @@ out:
 
 	printk(PRINT_PREF "finished after %u erase cycles\n",
 	       erase_cycles);
+	kfree(bad_ebs);
+out_check_buf:
 	kfree(check_buf);
 out_patt_FF:
 	kfree(patt_FF);
diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index 83bab2c..fca6545 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -1280,7 +1280,11 @@ out:
 	ubi_err("UBI error: cannot initialize UBI, error %d", err);
 	return err;
 }
+#if defined(CONFIG_BRCMSTB) && !defined(MODULE)
+late_initcall(ubi_init);	/* need to wait for the MTD driver */
+#else
 module_init(ubi_init);
+#endif
 
 static void __exit ubi_exit(void)
 {
diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index c63a64c..63a5274 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -143,6 +143,7 @@ config ETHOC
 
 source "drivers/net/ethernet/packetengines/Kconfig"
 source "drivers/net/ethernet/pasemi/Kconfig"
+source "drivers/net/ethernet/pmc-sierra/Kconfig"
 source "drivers/net/ethernet/qlogic/Kconfig"
 source "drivers/net/ethernet/racal/Kconfig"
 source "drivers/net/ethernet/realtek/Kconfig"
diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
index 9676a51..9fa81d3 100644
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_NET_VENDOR_OKI) += oki-semi/
 obj-$(CONFIG_ETHOC) += ethoc.o
 obj-$(CONFIG_NET_PACKET_ENGINE) += packetengines/
 obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
+obj-$(CONFIG_NET_VENDOR_PMC_SIERRA) += pmc-sierra/
 obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
 obj-$(CONFIG_NET_VENDOR_RACAL) += racal/
 obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
diff --git a/drivers/net/ethernet/broadcom/Makefile b/drivers/net/ethernet/broadcom/Makefile
index b789605..2c003253 100644
--- a/drivers/net/ethernet/broadcom/Makefile
+++ b/drivers/net/ethernet/broadcom/Makefile
@@ -2,6 +2,8 @@
 # Makefile for the Broadcom network device drivers.
 #
 
+obj-$(CONFIG_BCMGENET) += genet/
+obj-$(CONFIG_BCMGENET_NG) += genet-ng/
 obj-$(CONFIG_B44) += b44.o
 obj-$(CONFIG_BCM63XX_ENET) += bcm63xx_enet.o
 obj-$(CONFIG_BNX2) += bnx2.o
diff --git a/drivers/net/ethernet/broadcom/genet-ng/Kconfig b/drivers/net/ethernet/broadcom/genet-ng/Kconfig
new file mode 100644
index 0000000..c1ed960
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet-ng/Kconfig
@@ -0,0 +1,47 @@
+menu "BCMGENET options"
+
+config BCMGENET_RX_DESC_THROTTLE 
+	bool "use hardware rx descriptor throttling"
+	depends on BCMGENET
+	default n
+	help
+	  Instead of generating one interrupt for rx packet, the genet can 
+	  generate 1 interrupt for multiple rx packet, thus to reduce the interrupt
+	  number.
+
+config BCMGENET_NAPI
+	bool "use software rx descriptor throttling"
+	depends on BCMGENET
+	default y
+	help
+	  Use software interrupt throttling(the NAPI approach).
+
+config BCMGENET_RX_CSUM
+	bool "Enable L4 checksum offloading for rx"
+	depends on BCMGENET
+	default n
+	help
+	  Enable L4 checksum offloading for rx.
+
+config BCMGENET_TX_CSUM
+	bool "Enable L4 checksum offloading for tx"
+	depends on BCMGENET
+	default n
+	help
+	  Enable L4 checksum offloading for tx.
+
+config BCMGENET_DUMP_DATA
+	bool "Dump out data for debugging"
+	depends on BCMGENET
+	default n
+	help
+	  Dump out data for debugging.
+
+config BCMGENET_DUMP_TRACE
+	bool "Dump out trace message for debugging"
+	depends on BCMGENET
+	default n
+	help
+	  Dump out trace messages for debugging.
+endmenu
+
diff --git a/drivers/net/ethernet/broadcom/genet-ng/Makefile b/drivers/net/ethernet/broadcom/genet-ng/Makefile
new file mode 100644
index 0000000..f74e249
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet-ng/Makefile
@@ -0,0 +1,4 @@
+obj-$(CONFIG_BCMGENET_NG)		+= brcmgenet.o
+brcmgenet-objs := bcmgenet.o bcmmii.o 
+
+EXTRA_CFLAGS += -I.
diff --git a/drivers/net/ethernet/broadcom/genet-ng/bcmgenet.c b/drivers/net/ethernet/broadcom/genet-ng/bcmgenet.c
new file mode 100644
index 0000000..0dd74e4
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet-ng/bcmgenet.c
@@ -0,0 +1,2688 @@
+/*
+ * Copyright (c) 2002-2008 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *
+ * File Name  : bcmgenet.c
+ *
+ * Description: This is Linux driver for the broadcom GENET ethernet MAC core.
+
+*/
+
+#include "bcmgenet.h"
+#include "bcmmii.h"
+#include "if_net.h"
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/fcntl.h>
+#include <linux/interrupt.h>
+#include <linux/string.h>
+#include <linux/if_ether.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/pm.h>
+#include <linux/clk.h>
+#include <linux/version.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_net.h>
+#include <linux/of_platform.h>
+
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/netdevice.h>
+#include <linux/inetdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/in.h>
+
+#include <asm/unaligned.h>
+
+#include <linux/brcmstb/brcmstb.h>
+#include <linux/brcmstb/brcmapi.h>
+
+#ifdef CONFIG_NET_SCH_MULTIQ
+
+#if CONFIG_BRCM_GENET_VERSION == 1
+#error "This version of GENET doesn't support tx multi queue"
+#endif
+/* Default # of tx queues for multi queue support */
+#define GENET_MQ_CNT		4
+/* Default # of bds for each queue for multi queue support */
+#define GENET_MQ_BD_CNT		32
+/* Default highest priority queue for multi queue support */
+#define GENET_Q0_PRIORITY	0
+
+#define GENET_DEFAULT_BD_CNT	\
+	(TOTAL_DESC - GENET_MQ_CNT * GENET_MQ_BD_CNT)
+
+static void bcmgenet_init_multiq(struct net_device *dev);
+
+#endif	/*CONFIG_NET_SCH_MULTIQ */
+
+#define RX_BUF_LENGTH		2048
+#define RX_BUF_BITS			12
+#define SKB_ALIGNMENT		32
+#define DMA_DESC_THRES		4
+#define HFB_TCP_LEN			19
+#define HFB_ARP_LEN			21
+
+/* Tx/Rx DMA register offset, skip 256 descriptors */
+#define GENET_TDMA_REG_OFF	(GENET_TDMA_OFF + \
+		TOTAL_DESC*sizeof(struct DmaDesc))
+#define GENET_RDMA_REG_OFF	(GENET_RDMA_OFF + \
+		TOTAL_DESC*sizeof(struct DmaDesc))
+
+/* --------------------------------------------------------------------------
+External, indirect entry points.
+--------------------------------------------------------------------------*/
+static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
+/* --------------------------------------------------------------------------
+Called for "ifconfig ethX up" & "down"
+--------------------------------------------------------------------------*/
+static int bcmgenet_open(struct net_device *dev);
+static int bcmgenet_close(struct net_device *dev);
+/* --------------------------------------------------------------------------
+Watchdog timeout
+--------------------------------------------------------------------------*/
+static void bcmgenet_timeout(struct net_device *dev);
+/* --------------------------------------------------------------------------
+Packet transmission.
+--------------------------------------------------------------------------*/
+static int bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev);
+/* --------------------------------------------------------------------------
+Set address filtering mode
+--------------------------------------------------------------------------*/
+static void bcmgenet_set_rx_mode(struct net_device *dev);
+/* --------------------------------------------------------------------------
+Set the hardware MAC address.
+--------------------------------------------------------------------------*/
+static int bcmgenet_set_mac_addr(struct net_device *dev, void *p);
+
+/* --------------------------------------------------------------------------
+Interrupt routine, for all interrupts except ring buffer interrupts
+--------------------------------------------------------------------------*/
+static irqreturn_t bcmgenet_isr0(int irq, void *dev_id);
+/*---------------------------------------------------------------------------
+IRQ handler for ring buffer interrupt.
+--------------------------------------------------------------------------*/
+static irqreturn_t bcmgenet_isr1(int irq, void *dev_id);
+/* --------------------------------------------------------------------------
+dev->poll() method
+--------------------------------------------------------------------------*/
+static int bcmgenet_poll(struct napi_struct *napi, int budget);
+/* --------------------------------------------------------------------------
+Process recived packet for descriptor based DMA
+--------------------------------------------------------------------------*/
+static unsigned int bcmgenet_desc_rx(void *ptr, unsigned int budget);
+/* --------------------------------------------------------------------------
+Internal routines
+--------------------------------------------------------------------------*/
+/* Allocate and initialize tx/rx buffer descriptor pools */
+static int bcmgenet_init_dev(struct BcmEnet_devctrl *pDevCtrl);
+static void bcmgenet_uninit_dev(struct BcmEnet_devctrl *pDevCtrl);
+/* Assign the Rx descriptor ring */
+static int assign_rx_buffers(struct BcmEnet_devctrl *pDevCtrl);
+/* Initialize the uniMac control registers */
+static int init_umac(struct BcmEnet_devctrl *pDevCtrl);
+/* Initialize DMA control register */
+static void init_edma(struct BcmEnet_devctrl *pDevCtrl);
+/* Interrupt bottom-half */
+static void bcmgenet_irq_task(struct work_struct *work);
+/* power management */
+static void bcmgenet_power_down(struct BcmEnet_devctrl *pDevCtrl, int mode);
+static void bcmgenet_power_up(struct BcmEnet_devctrl *pDevCtrl, int mode);
+/* clock control */
+static void bcmgenet_clock_enable(struct BcmEnet_devctrl *pDevCtrl);
+static void bcmgenet_clock_disable(struct BcmEnet_devctrl *pDevCtrl);
+/* S3 warm boot */
+static void save_state(struct BcmEnet_devctrl *pDevCtrl);
+static void restore_state(struct BcmEnet_devctrl *pDevCtrl);
+
+static struct net_device *eth_root_dev;
+static int DmaDescThres = DMA_DESC_THRES;
+
+/*
+ * HFB data for ARP request.
+ * In WoL (Magic Packet or ACPI) mode, we need to response
+ * ARP request, so dedicate an HFB to filter the ARP request.
+ * NOTE: the last two words are to be filled by destination.
+ */
+static unsigned int hfb_arp[] = {
+	0x000FFFFF, 0x000FFFFF, 0x000FFFFF,	0x00000000,
+	0x00000000, 0x00000000, 0x000F0806,	0x000F0001,
+	0x000F0800,	0x000F0604, 0x000F0001,	0x00000000,
+	0x00000000,	0x00000000,	0x00000000, 0x00000000,
+	0x000F0000,	0x000F0000,	0x000F0000,	0x000F0000,
+	0x000F0000
+};
+
+static inline void handleAlignment(struct BcmEnet_devctrl *pDevCtrl,
+		struct sk_buff *skb)
+{
+	/*
+	 * We request to allocate 2048 + 32 bytes of buffers, and the
+	 * dev_alloc_skb() added 16B for NET_SKB_PAD, so we totally
+	 * requested 2048+32+16 bytes buffer, the size was aligned to
+	 * SMP_CACHE_BYTES, which is 64B.(is it?), so we finnally ended
+	 * up got 2112 bytes of buffer! Among which, the first 16B is
+	 * reserved for NET_SKB_PAD, to make the skb->data aligned 32B
+	 * boundary, we should have enough space to fullfill the 2KB
+	 * buffer after alignment!
+     */
+
+	unsigned long boundary32, curData, resHeader;
+
+	curData = (unsigned long) skb->data;
+	boundary32 = (curData + (SKB_ALIGNMENT - 1)) & ~(SKB_ALIGNMENT - 1);
+	resHeader = boundary32 - curData ;
+	/* 4 bytes for skb pointer */
+	if (resHeader < 4)
+		boundary32 += 32;
+
+	resHeader = boundary32 - curData - 4;
+	/* We'd have minimum 16B reserved by default. */
+	skb_reserve(skb, resHeader);
+
+	*(unsigned int *)skb->data = (unsigned int)skb;
+	skb_reserve(skb, 4);
+	/*
+	 * Make sure it is on 32B boundary, should never happen if our
+	 * calculation was correct.
+	 */
+	if ((unsigned long) skb->data & (SKB_ALIGNMENT - 1)) {
+		printk(KERN_WARNING "skb buffer is NOT aligned on %d boundary!\n",
+			SKB_ALIGNMENT);
+	}
+
+	/*
+	 *  we don't reserve 2B for IP Header optimization here,
+	 *  use skb_pull when receiving packets
+	 */
+}
+/* --------------------------------------------------------------------------
+Name: bcmgenet_gphy_link_status
+Purpose: GPHY link status monitoring task
+-------------------------------------------------------------------------- */
+static void bcmgenet_gphy_link_status(struct work_struct *work)
+{
+	struct BcmEnet_devctrl *pDevCtrl = container_of(work,
+			struct BcmEnet_devctrl, bcmgenet_link_work);
+
+	bcmgenet_mii_setup(pDevCtrl->dev);
+}
+/* --------------------------------------------------------------------------
+Name: bcmgenet_gphy_link_timer
+Purpose: GPHY link status monitoring timer function
+-------------------------------------------------------------------------- */
+static void bcmgenet_gphy_link_timer(unsigned long data)
+{
+	struct BcmEnet_devctrl *pDevCtrl = (struct BcmEnet_devctrl *)data;
+	schedule_work(&pDevCtrl->bcmgenet_link_work);
+	mod_timer(&pDevCtrl->timer, jiffies + HZ);
+}
+
+static int bcmgenet_wakeup_enable(void *ref)
+{
+	struct BcmEnet_devctrl *pDevCtrl = (struct BcmEnet_devctrl *)ref;
+	u32 mask;
+	if (pDevCtrl->phyType == BRCM_PHY_TYPE_MOCA)
+		mask = WOL_MOCA_MASK;
+	else
+		mask = pDevCtrl->devnum ? WOL_MOCA_MASK : WOL_ENET_MASK;
+	if (device_may_wakeup(&pDevCtrl->dev->dev))
+		brcm_pm_wakeup_source_enable(mask, 1);
+	return 0;
+}
+
+static int bcmgenet_wakeup_disable(void *ref)
+{
+	struct BcmEnet_devctrl *pDevCtrl = (struct BcmEnet_devctrl *)ref;
+	u32 mask;
+	if (pDevCtrl->phyType == BRCM_PHY_TYPE_MOCA)
+		mask = WOL_MOCA_MASK;
+	else
+		mask = pDevCtrl->devnum ? WOL_MOCA_MASK : WOL_ENET_MASK;
+	if (device_may_wakeup(&pDevCtrl->dev->dev))
+		brcm_pm_wakeup_source_enable(mask, 0);
+	return 0;
+}
+
+static int bcmgenet_wakeup_poll(void *ref)
+{
+	struct BcmEnet_devctrl *pDevCtrl = (struct BcmEnet_devctrl *)ref;
+	int retval = 0;
+	u32 mask = 0;
+
+	if (device_may_wakeup(&pDevCtrl->dev->dev)) {
+		if (pDevCtrl->phyType == BRCM_PHY_TYPE_MOCA)
+			mask = WOL_MOCA_MASK;
+		else
+			mask = pDevCtrl->devnum ? WOL_MOCA_MASK : WOL_ENET_MASK;
+		retval = brcm_pm_wakeup_get_status(mask);
+	}
+	printk(KERN_DEBUG "%s %s(%08x): %d\n", __func__,
+	       pDevCtrl->dev->name, mask, retval);
+	return retval;
+}
+
+static struct brcm_wakeup_ops bcmgenet_wakeup_ops = {
+	.enable = bcmgenet_wakeup_enable,
+	.disable = bcmgenet_wakeup_disable,
+	.poll = bcmgenet_wakeup_poll,
+};
+
+/* --------------------------------------------------------------------------
+Name: bcmgenet_open
+Purpose: Open and Initialize the EMAC on the chip
+-------------------------------------------------------------------------- */
+static int bcmgenet_open(struct net_device *dev)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	unsigned long dma_ctrl;
+	volatile struct uniMacRegs *umac = pDevCtrl->umac;
+
+	TRACE(("%s: bcmgenet_open\n", dev->name));
+
+	bcmgenet_clock_enable(pDevCtrl);
+
+	/* take MAC out of reset */
+	GENET_RBUF_FLUSH_CTRL(pDevCtrl) &= ~BIT(1);
+	udelay(10);
+
+	/* disable ethernet MAC while updating its registers */
+	umac->cmd &= ~(CMD_TX_EN | CMD_RX_EN);
+
+	umac->mac_0 = (dev->dev_addr[0] << 24 |
+			dev->dev_addr[1] << 16 |
+			dev->dev_addr[2] << 8  |
+			dev->dev_addr[3]);
+	umac->mac_1 = dev->dev_addr[4] << 8 | dev->dev_addr[5];
+
+	if (pDevCtrl->wol_enabled) {
+		/* From WOL-enabled suspend, switch to regular clock */
+		clk_disable(pDevCtrl->clk_wol);
+		/* init umac registers to synchronize s/w with h/w */
+		init_umac(pDevCtrl);
+		/* Speed settings must be restored */
+		bcmgenet_mii_init(dev);
+		bcmgenet_mii_setup(dev);
+	}
+
+	if (pDevCtrl->phyType == BRCM_PHY_TYPE_INT)
+		pDevCtrl->ext->ext_pwr_mgmt |= EXT_ENERGY_DET_MASK;
+
+	if (test_and_clear_bit(GENET_POWER_WOL_MAGIC, &pDevCtrl->wol_enabled))
+		bcmgenet_power_up(pDevCtrl, GENET_POWER_WOL_MAGIC);
+	if (test_and_clear_bit(GENET_POWER_WOL_ACPI, &pDevCtrl->wol_enabled))
+		bcmgenet_power_up(pDevCtrl, GENET_POWER_WOL_ACPI);
+
+	/* disable DMA */
+	dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
+	pDevCtrl->txDma->tdma_ctrl &= ~dma_ctrl;
+	pDevCtrl->rxDma->rdma_ctrl &= ~dma_ctrl;
+	umac->tx_flush = 1;
+	udelay(10);
+	umac->tx_flush = 0;
+
+	/* reset dma, start from beginning of the ring. */
+	init_edma(pDevCtrl);
+	/* reset internal book keeping variables. */
+	pDevCtrl->txLastCIndex = 0;
+	pDevCtrl->rxBdAssignPtr = pDevCtrl->rxBds;
+
+	if (brcm_pm_deep_sleep())
+		restore_state(pDevCtrl);
+	else
+		assign_rx_buffers(pDevCtrl);
+
+	pDevCtrl->txFreeBds = pDevCtrl->nrTxBds;
+
+	/*Always enable ring 16 - descriptor ring */
+	pDevCtrl->rxDma->rdma_ctrl |= dma_ctrl;
+	pDevCtrl->txDma->tdma_ctrl |= dma_ctrl;
+
+	if (pDevCtrl->extPhy)
+		mod_timer(&pDevCtrl->timer, jiffies);
+
+	if (request_irq(pDevCtrl->irq0, bcmgenet_isr0, IRQF_SHARED,
+				dev->name, pDevCtrl) < 0) {
+		printk(KERN_ERR "can't request IRQ %d\n", pDevCtrl->irq0);
+		goto err2;
+	}
+	if (request_irq(pDevCtrl->irq1, bcmgenet_isr1, IRQF_SHARED,
+				dev->name, pDevCtrl) < 0) {
+		printk(KERN_ERR "can't request IRQ %d\n", pDevCtrl->irq1);
+		free_irq(pDevCtrl->irq0, pDevCtrl);
+		goto err1;
+	}
+	/* Start the network engine */
+	netif_tx_start_all_queues(dev);
+	napi_enable(&pDevCtrl->napi);
+
+	umac->cmd |= (CMD_TX_EN | CMD_RX_EN);
+
+	brcm_pm_wakeup_register(&bcmgenet_wakeup_ops, pDevCtrl, dev->name);
+	device_set_wakeup_capable(&dev->dev, 1);
+
+	if (pDevCtrl->phyType == BRCM_PHY_TYPE_INT)
+		bcmgenet_power_up(pDevCtrl, GENET_POWER_PASSIVE);
+
+	return 0;
+err1:
+	free_irq(pDevCtrl->irq0, dev);
+err2:
+	free_irq(pDevCtrl->irq1, dev);
+	del_timer_sync(&pDevCtrl->timer);
+	netif_tx_stop_all_queues(dev);
+
+	return -ENODEV;
+}
+/* --------------------------------------------------------------------------
+Name: bcmgenet_close
+Purpose: Stop communicating with the outside world
+Note: Caused by 'ifconfig ethX down'
+-------------------------------------------------------------------------- */
+static int bcmgenet_close(struct net_device *dev)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	int timeout = 0;
+
+	TRACE(("%s: bcmgenet_close\n", dev->name));
+
+	/* Disable MAC receive */
+	pDevCtrl->umac->cmd &= ~CMD_RX_EN;
+
+	netif_tx_stop_all_queues(dev);
+
+	/* Disable TDMA to stop add more frames in TX DMA */
+	pDevCtrl->txDma->tdma_ctrl &= ~DMA_EN;
+	/* Check TDMA status register to confirm TDMA is disabled */
+	while (!(pDevCtrl->txDma->tdma_status & DMA_DISABLED)) {
+		if (timeout++ == 5000) {
+			netdev_warn(pDevCtrl->dev,
+				"Timed out while disabling TX DMA\n");
+			break;
+		}
+		udelay(1);
+	}
+
+	/* SWLINUX-2252: Workaround for rx flush issue causes rbuf overflow */
+	/* Wait 10ms for packet drain in both tx and rx dma */
+	usleep_range(10000, 20000);
+
+	/* Disable RDMA */
+	pDevCtrl->rxDma->rdma_ctrl &= ~DMA_EN;
+	/* Check RDMA status register to confirm RDMA is disabled */
+	while (!(pDevCtrl->rxDma->rdma_status & DMA_DISABLED)) {
+		if (timeout++ == 5000) {
+			netdev_warn(pDevCtrl->dev,
+				"Timed out while disabling RX DMA\n");
+			break;
+		}
+		udelay(1);
+	}
+
+	/* Disable MAC transmit. TX DMA disabled have to done before this */
+	pDevCtrl->umac->cmd &= ~CMD_TX_EN;
+
+	napi_disable(&pDevCtrl->napi);
+
+	/* tx reclaim */
+	bcmgenet_xmit(NULL, dev);
+	free_irq(pDevCtrl->irq0, (void *)pDevCtrl);
+	free_irq(pDevCtrl->irq1, (void *)pDevCtrl);
+	if (pDevCtrl->extPhy) {
+		del_timer_sync(&pDevCtrl->timer);
+		cancel_work_sync(&pDevCtrl->bcmgenet_link_work);
+	}
+	/*
+	 * Wait for pending work items to complete - we are stopping
+	 * the clock now. Since interrupts are disabled, no new work
+	 * will be scheduled.
+	 */
+	cancel_work_sync(&pDevCtrl->bcmgenet_irq_work);
+
+	if (brcm_pm_deep_sleep())
+		save_state(pDevCtrl);
+
+	if (device_may_wakeup(&dev->dev) && pDevCtrl->dev_asleep) {
+		if (pDevCtrl->wolopts & (WAKE_MAGIC|WAKE_MAGICSECURE))
+			bcmgenet_power_down(pDevCtrl, GENET_POWER_WOL_MAGIC);
+		if (pDevCtrl->wolopts & WAKE_ARP)
+			bcmgenet_power_down(pDevCtrl, GENET_POWER_WOL_ACPI);
+	} else if (pDevCtrl->phyType == BRCM_PHY_TYPE_INT)
+		bcmgenet_power_down(pDevCtrl, GENET_POWER_PASSIVE);
+
+	if (pDevCtrl->wol_enabled)
+		clk_enable(pDevCtrl->clk_wol);
+
+	bcmgenet_clock_disable(pDevCtrl);
+
+	return 0;
+}
+
+/* --------------------------------------------------------------------------
+Name: bcmgenet_net_timeout
+Purpose:
+-------------------------------------------------------------------------- */
+static void bcmgenet_timeout(struct net_device *dev)
+{
+	BUG_ON(dev == NULL);
+
+	TRACE(("%s: bcmgenet_timeout\n", dev->name));
+
+	dev->trans_start = jiffies;
+
+	dev->stats.tx_errors++;
+
+	netif_tx_wake_all_queues(dev);
+}
+
+/* --------------------------------------------------------------------------
+Name: bcmgenet_set_rx_mode
+Purpose: ndo_set_rx_mode entry point, called when unicast or multicast
+address list, or network interface flags are updated.
+-------------------------------------------------------------------------- */
+static void bcmgenet_set_rx_mode(struct net_device *dev)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	struct netdev_hw_addr *ha;
+	int i, mc;
+#define MAX_MC_COUNT	16
+
+	TRACE(("%s: %s: %08X\n",
+		dev->name, __func__, dev->flags));
+
+	/* Promiscous mode */
+	if (dev->flags & IFF_PROMISC) {
+		pDevCtrl->umac->cmd |= CMD_PROMISC;
+		pDevCtrl->umac->mdf_ctrl = 0;
+		return;
+	} else
+		pDevCtrl->umac->cmd &= ~CMD_PROMISC;
+
+
+	/* UniMac doesn't support ALLMULTI */
+	if (dev->flags & IFF_ALLMULTI)
+		return;
+
+	/* update MDF filter */
+	i = 0;
+	mc = 0;
+	/* Broadcast */
+	pDevCtrl->umac->mdf_addr[i] = 0xFFFF;
+	pDevCtrl->umac->mdf_addr[i+1] = 0xFFFFFFFF;
+	pDevCtrl->umac->mdf_ctrl |= (1 << (MAX_MC_COUNT - mc));
+	i += 2;
+	mc++;
+	/* my own address.*/
+	pDevCtrl->umac->mdf_addr[i] = (dev->dev_addr[0]<<8) | dev->dev_addr[1];
+	pDevCtrl->umac->mdf_addr[i+1] = dev->dev_addr[2] << 24 |
+		dev->dev_addr[3] << 16 |
+		dev->dev_addr[4] << 8 |
+		dev->dev_addr[5];
+	pDevCtrl->umac->mdf_ctrl |= (1 << (MAX_MC_COUNT - mc));
+	i += 2;
+	mc++;
+	/* Unicast list*/
+	if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
+		return;
+
+	if (!netdev_uc_empty(dev)) {
+		netdev_for_each_uc_addr(ha, dev) {
+			pDevCtrl->umac->mdf_addr[i] = (ha->addr[0]<<8) |
+				ha->addr[1];
+			pDevCtrl->umac->mdf_addr[i+1] = ha->addr[2] << 24 |
+				ha->addr[3] << 16 |
+				ha->addr[4] << 8 |
+				ha->addr[5];
+			pDevCtrl->umac->mdf_ctrl |=
+				(1 << (MAX_MC_COUNT - mc));
+			i += 2;
+			mc++;
+		}
+	}
+	/* Multicast */
+	if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
+		return;
+
+	netdev_for_each_mc_addr(ha, dev) {
+		pDevCtrl->umac->mdf_addr[i] = ha->addr[0] << 8 |
+			ha->addr[1];
+		pDevCtrl->umac->mdf_addr[i+1] = ha->addr[2] << 24 |
+			ha->addr[3] << 16 | ha->addr[4] << 8 | ha->addr[5];
+		pDevCtrl->umac->mdf_ctrl |= (1 << (MAX_MC_COUNT - mc));
+		i += 2;
+		mc++;
+	}
+}
+/*
+ * Set the hardware MAC address.
+ */
+static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
+{
+	struct sockaddr *addr = p;
+
+	if (netif_running(dev))
+		return -EBUSY;
+
+	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
+
+	return 0;
+}
+/* --------------------------------------------------------------------------
+Name: bcmgenet_select_queue
+Purpose: select which xmit queue to use based on skb->queue_mapping.
+-------------------------------------------------------------------------- */
+static u16 __maybe_unused bcmgenet_select_queue(struct net_device *dev,
+		struct sk_buff *skb)
+{
+	/*
+	 * If multi-queue support is enabled, and NET_ACT_SKBEDIT is not
+	 * defined, this function simply returns current queue_mapping set
+	 * inside skb, this means other modules, (netaccel, for example),
+	 * must provide a mechanism to set the queue_mapping before trying
+	 * to send a packet.
+	 */
+	return skb->queue_mapping;
+}
+
+/* --------------------------------------------------------------------------
+Name: bcmgenet_get_txcb
+Purpose: return tx control data and increment write pointer.
+-------------------------------------------------------------------------- */
+static struct Enet_CB *bcmgenet_get_txcb(struct net_device *dev,
+		int *pos, int index)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	struct Enet_CB *txCBPtr = NULL;
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+	if (index == DESC_INDEX) {
+		txCBPtr = pDevCtrl->txCbs;
+		txCBPtr += (*pos - GENET_MQ_CNT*GENET_MQ_BD_CNT);
+		txCBPtr->BdAddr = &pDevCtrl->txBds[*pos];
+		if (*pos == (TOTAL_DESC - 1))
+			*pos = (GENET_MQ_CNT*GENET_MQ_BD_CNT);
+		else
+			*pos += 1;
+
+	} else {
+		txCBPtr = pDevCtrl->txRingCBs[index];
+		txCBPtr += (*pos - index*GENET_MQ_BD_CNT);
+		txCBPtr->BdAddr = &pDevCtrl->txBds[*pos];
+		if (*pos == (GENET_MQ_BD_CNT*(index+1) - 1))
+			*pos = GENET_MQ_BD_CNT * index;
+		else
+			*pos += 1;
+	}
+#else
+	txCBPtr = pDevCtrl->txCbs + *pos;
+	txCBPtr->BdAddr = &pDevCtrl->txBds[*pos];
+	/* Advancing local write pointer */
+	if (*pos == (TOTAL_DESC - 1))
+		*pos = 0;
+	else
+		*pos += 1;
+#endif
+
+	return txCBPtr;
+}
+/* --------------------------------------------------------------------------
+Name: bcmgenet_tx_reclaim
+Purpose: reclaim xmited skb
+-------------------------------------------------------------------------- */
+static void bcmgenet_tx_reclaim(struct net_device *dev, int index)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	unsigned int c_index;
+	struct Enet_CB *txCBPtr;
+	int lastTxedCnt = 0, lastCIndex = 0, nrTxBds = 0;
+
+	/* Compute how many buffers are transmited since last xmit call */
+	c_index = pDevCtrl->txDma->tDmaRings[index].tdma_consumer_index;
+
+
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+	if (index == DESC_INDEX) {
+		lastCIndex = pDevCtrl->txLastCIndex;
+		nrTxBds = GENET_DEFAULT_BD_CNT;
+	} else {
+		lastCIndex = pDevCtrl->txRingCIndex[index];
+		nrTxBds = GENET_MQ_BD_CNT;
+	}
+
+#else
+	lastCIndex = pDevCtrl->txLastCIndex;
+	nrTxBds = TOTAL_DESC;
+#endif
+	c_index &= (nrTxBds - 1);
+
+	if (c_index >= lastCIndex)
+		lastTxedCnt = c_index - lastCIndex;
+	else
+		lastTxedCnt = nrTxBds - lastCIndex + c_index;
+
+
+	TRACE(("%s: %s index=%d c_index=%d "
+			"lastTxedCnt=%d txLastCIndex=%d\n",
+			__func__, pDevCtrl->dev->name, index,
+			c_index, lastTxedCnt, lastCIndex));
+
+	/* Reclaim transmitted buffers */
+	while (lastTxedCnt-- > 0) {
+		if (index == DESC_INDEX)
+			txCBPtr = &pDevCtrl->txCbs[lastCIndex];
+		else
+			txCBPtr = pDevCtrl->txRingCBs[index] + lastCIndex;
+		if (txCBPtr->skb != NULL) {
+			dma_unmap_single(&pDevCtrl->dev->dev,
+					dma_unmap_addr(txCBPtr, dma_addr),
+					txCBPtr->skb->len,
+					DMA_TO_DEVICE);
+			dev_kfree_skb_any(txCBPtr->skb);
+			txCBPtr->skb = NULL;
+			dma_unmap_addr_set(txCBPtr, dma_addr, 0);
+		} else if (dma_unmap_addr(txCBPtr, dma_addr)) {
+			dma_unmap_page(&pDevCtrl->dev->dev,
+					dma_unmap_addr(txCBPtr, dma_addr),
+					dma_unmap_len(txCBPtr, dma_len),
+					DMA_TO_DEVICE);
+			dma_unmap_addr_set(txCBPtr, dma_addr, 0);
+		}
+		if (index == DESC_INDEX)
+			pDevCtrl->txFreeBds += 1;
+		else
+			pDevCtrl->txRingFreeBds[index] += 1;
+
+		if (lastCIndex == (nrTxBds - 1))
+			lastCIndex = 0;
+		else
+			lastCIndex++;
+	}
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+	if (index == DESC_INDEX) {
+		if (pDevCtrl->txFreeBds > (MAX_SKB_FRAGS + 1)
+			&& __netif_subqueue_stopped(dev, 0)) {
+			pDevCtrl->intrl2_0->cpu_mask_set |=
+				(UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE);
+			netif_wake_subqueue(dev, 0);
+		}
+		pDevCtrl->txLastCIndex = c_index;
+	} else{
+		if (pDevCtrl->txRingFreeBds[index] > (MAX_SKB_FRAGS + 1)
+			&& __netif_subqueue_stopped(dev, index+1)) {
+			pDevCtrl->intrl2_1->cpu_mask_set = (1 << index);
+			netif_wake_subqueue(dev, index+1);
+		}
+		pDevCtrl->txRingCIndex[index] = c_index;
+	}
+#else
+	if (pDevCtrl->txFreeBds > (MAX_SKB_FRAGS + 1)
+			&& netif_queue_stopped(dev)) {
+		/* Disable txdma bdone/pdone interrupt if we have free tx bds */
+		pDevCtrl->intrl2_0->cpu_mask_set |= (UMAC_IRQ_TXDMA_BDONE |
+				UMAC_IRQ_TXDMA_PDONE);
+		netif_wake_queue(dev);
+	}
+	pDevCtrl->txLastCIndex = c_index;
+#endif
+}
+
+/* --------------------------------------------------------------------------
+Name: bcmgenet_xmit
+Purpose: Send ethernet traffic
+-------------------------------------------------------------------------- */
+static int bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	volatile struct tDmaRingRegs *tDma_ring;
+	dma_addr_t mapping;
+	struct Enet_CB *txCBPtr;
+	unsigned int write_ptr = 0;
+	int i = 0;
+	unsigned long flags;
+	struct status_64 *Status = NULL;
+	int nr_frags = 0, index = DESC_INDEX;
+
+	spin_lock_irqsave(&pDevCtrl->lock, flags);
+
+	if (!pDevCtrl->clock_active) {
+		printk(KERN_WARNING "%s: transmitting with gated clock!\n",
+		       dev_name(&dev->dev));
+		dev_kfree_skb_any(skb);
+		spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+		return NETDEV_TX_OK;
+	}
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+	if (skb) {
+		index = skb_get_queue_mapping(skb);
+		/*
+		* Mapping strategy:
+		* queue_mapping = 0, unclassfieid, packet xmited through ring16
+		* queue_mapping = 1, goes to ring 0. (highest priority queue)
+		* queue_mapping = 2, goes to ring 1.
+		* queue_mapping = 3, goes to ring 2.
+		* queue_mapping = 4, goes to ring 3.
+		*/
+		if (index == 0)
+			index = DESC_INDEX;
+		else
+			index -= 1;
+		if (index != DESC_INDEX && index > 3) {
+			printk(KERN_ERR "%s: skb->queue_mapping %d is invalid\n",
+					__func__, skb_get_queue_mapping(skb));
+			spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+			dev->stats.tx_errors++;
+			dev->stats.tx_dropped++;
+			return 1;
+		}
+		nr_frags = skb_shinfo(skb)->nr_frags;
+		if (index == DESC_INDEX) {
+			if (pDevCtrl->txFreeBds <= nr_frags + 1) {
+				netif_stop_subqueue(dev, 0);
+				spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+				printk(KERN_ERR "%s: tx ring %d full when queue awake\n",
+					__func__, index);
+				return 1;
+			}
+		} else if (pDevCtrl->txRingFreeBds[index] <= nr_frags + 1) {
+			netif_stop_subqueue(dev, index+1);
+			spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+			printk(KERN_ERR "%s: tx ring %d full when queue awake\n",
+					__func__, index);
+			return 1;
+		}
+	}
+	/* Reclaim xmited skb for each subqueue */
+	for (i = 0; i < GENET_MQ_CNT; i++)
+		bcmgenet_tx_reclaim(dev, i);
+#else
+	if (skb) {
+		nr_frags = skb_shinfo(skb)->nr_frags;
+		if (pDevCtrl->txFreeBds <= nr_frags + 1) {
+			netif_stop_queue(dev);
+			spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+			printk(KERN_ERR "%s: tx ring full when queue awake\n",
+				__func__);
+			return 1;
+		}
+	}
+#endif
+
+	if (!skb) {
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+		for (i = 0; i < GENET_MQ_CNT; i++)
+			bcmgenet_tx_reclaim(dev, i);
+#endif
+		bcmgenet_tx_reclaim(dev, DESC_INDEX);
+		spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+		return 0;
+	}
+	/*
+	 * reclaim xmited skb every 8 packets.
+	 */
+	if ((index == DESC_INDEX) &&
+		(pDevCtrl->txFreeBds < pDevCtrl->nrTxBds - 8))
+		bcmgenet_tx_reclaim(dev, index);
+
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+	if ((index != DESC_INDEX) && (pDevCtrl->txRingFreeBds[index]
+			< GENET_MQ_BD_CNT - 8))
+		bcmgenet_tx_reclaim(dev, index);
+#endif
+
+	tDma_ring = &pDevCtrl->txDma->tDmaRings[index];
+	/*
+	 * If 64 byte status block enabled, must make sure skb has
+	 * enough headroom for us to insert 64B status block.
+	 */
+	if (GENET_TBUF_CTRL(pDevCtrl) & RBUF_64B_EN) {
+		if (likely(skb_headroom(skb) < 64)) {
+			struct sk_buff *new_skb;
+			new_skb = skb_realloc_headroom(skb, 64);
+			if (new_skb  == NULL) {
+				dev_kfree_skb(skb);
+				dev->stats.tx_errors++;
+				dev->stats.tx_dropped++;
+				spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+				return 0;
+			} else if (skb->sk) {
+				skb_set_owner_w(new_skb, skb->sk);
+			}
+			dev_kfree_skb(skb);
+			skb = new_skb;
+		}
+		skb_push(skb, 64);
+		Status = (struct status_64 *)skb->data;
+	}
+	write_ptr = tDma_ring->tdma_write_pointer;
+
+	/* Obtain transmit control block */
+	txCBPtr = bcmgenet_get_txcb(dev, &write_ptr, index);
+
+	if (unlikely(!txCBPtr))
+		BUG();
+
+	txCBPtr->skb = skb;
+
+	if ((skb->ip_summed  == CHECKSUM_PARTIAL) &&
+			(GENET_TBUF_CTRL(pDevCtrl) & RBUF_64B_EN)) {
+		u16 offset;
+		offset = skb->csum_start - skb_headroom(skb) - 64;
+		/* Insert 64B TSB and set the flag */
+		Status->tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
+			(offset + skb->csum_offset) |
+			STATUS_TX_CSUM_LV;
+	}
+
+	/*
+	 * Add the buffer to the ring.
+	 * Set addr and length of DMA BD to be transmitted.
+	 */
+	if (!nr_frags) {
+		mapping = dma_map_single(&pDevCtrl->dev->dev,
+				skb->data, skb->len, DMA_TO_DEVICE);
+		if (dma_mapping_error(&pDevCtrl->dev->dev, mapping)) {
+			dev_err(&pDevCtrl->dev->dev, "Tx DMA map failed\n");
+			dev_kfree_skb(skb);
+			spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+			return 0;
+		}
+		dma_unmap_addr_set(txCBPtr, dma_addr, mapping);
+		dma_unmap_len_set(txCBPtr, dma_len, skb->len);
+		dmadesc_set_addr(txCBPtr->BdAddr, mapping);
+		txCBPtr->BdAddr->length_status = (
+			((unsigned long)((skb->len < ETH_ZLEN) ?
+			ETH_ZLEN : skb->len)) << 16) | DMA_SOP | DMA_EOP |
+			(DMA_TX_QTAG_MASK << DMA_TX_QTAG_SHIFT) |
+			DMA_TX_APPEND_CRC;
+
+		if (skb->ip_summed  == CHECKSUM_PARTIAL)
+			txCBPtr->BdAddr->length_status |= DMA_TX_DO_CSUM;
+
+#ifdef CONFIG_BCMGENET_DUMP_DATA
+		printk(KERN_NOTICE "%s: data 0x%p len %d",
+				__func__, skb->data, skb->len);
+		print_hex_dump(KERN_NOTICE, "", DUMP_PREFIX_ADDRESS,
+				16, 1, skb->data, skb->len, 0);
+#endif
+		/* Decrement total BD count and advance our write pointer */
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+		if (index == DESC_INDEX)
+			pDevCtrl->txFreeBds -= 1;
+		else
+			pDevCtrl->txRingFreeBds[index] -= 1;
+#else
+		pDevCtrl->txFreeBds -= 1;
+#endif
+		/* advance producer index and write pointer.*/
+		tDma_ring->tdma_producer_index += 1;
+		tDma_ring->tdma_write_pointer = write_ptr;
+		/* update stats */
+		dev->stats.tx_bytes += ((skb->len < ETH_ZLEN) ?
+				ETH_ZLEN : skb->len);
+		dev->stats.tx_packets++;
+
+	} else {
+		/* xmit head */
+		mapping = dma_map_single(&pDevCtrl->dev->dev,
+				skb->data, skb_headlen(skb), DMA_TO_DEVICE);
+		if (dma_mapping_error(&pDevCtrl->dev->dev, mapping)) {
+			dev_kfree_skb(skb);
+			dev_err(&pDevCtrl->dev->dev, "Tx DMA map failed\n");
+			spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+			return 0;
+		}
+		dma_unmap_addr_set(txCBPtr, dma_addr, mapping);
+		dma_unmap_len_set(txCBPtr, dma_len, skb->len);
+		dmadesc_set_addr(txCBPtr->BdAddr, mapping);
+		txCBPtr->BdAddr->length_status = (skb_headlen(skb) << 16) |
+			(DMA_TX_QTAG_MASK << DMA_TX_QTAG_SHIFT) |
+			DMA_SOP | DMA_TX_APPEND_CRC;
+
+		if (skb->ip_summed  == CHECKSUM_PARTIAL)
+			txCBPtr->BdAddr->length_status |= DMA_TX_DO_CSUM;
+
+#ifdef CONFIG_BCMGENET_DUMP_DATA
+		printk(KERN_NOTICE "%s: frag head len %d",
+				__func__, skb_headlen(skb));
+		print_hex_dump(KERN_NOTICE, "", DUMP_PREFIX_ADDRESS,
+				16, 1, skb->data, skb_headlen(skb), 0);
+#endif
+		/* Decrement total BD count and advance our write pointer */
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+		if (index == DESC_INDEX)
+			pDevCtrl->txFreeBds -= 1;
+		else
+			pDevCtrl->txRingFreeBds[index] -= 1;
+#else
+		pDevCtrl->txFreeBds -= 1;
+#endif
+		/* advance producer index and write pointer.*/
+		tDma_ring->tdma_producer_index += 1;
+		tDma_ring->tdma_write_pointer = write_ptr;
+		dev->stats.tx_bytes += skb_headlen(skb);
+
+		/* xmit fragment */
+		for (i = 0; i < nr_frags; i++) {
+			skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
+
+			txCBPtr = bcmgenet_get_txcb(dev, &write_ptr, index);
+
+			if (unlikely(!txCBPtr))
+				BUG();
+			txCBPtr->skb = NULL;
+
+			mapping = skb_frag_dma_map(&pDevCtrl->dev->dev, frag, 0,
+				skb_frag_size(frag), DMA_TO_DEVICE);
+			if (dma_mapping_error(&pDevCtrl->dev->dev, mapping)) {
+				printk(KERN_ERR "%s: Tx DMA map failed\n",
+						__func__);
+				/*TODO: Handle frag failure.*/
+				spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+				return 0;
+			}
+			dma_unmap_addr_set(txCBPtr, dma_addr, mapping);
+			dma_unmap_len_set(txCBPtr, dma_len, frag->size);
+			dmadesc_set_addr(txCBPtr->BdAddr, mapping);
+#ifdef CONFIG_BCMGENET_DUMP_DATA
+			printk(KERN_NOTICE "%s: frag%d len %d",
+					__func__, i, frag->size);
+			print_hex_dump(KERN_NOTICE, "", DUMP_PREFIX_ADDRESS,
+				16, 1,
+				page_address(frag->page)+frag->page_offset,
+				frag->size, 0);
+#endif
+			txCBPtr->BdAddr->length_status =
+					((unsigned long)frag->size << 16) |
+					(DMA_TX_QTAG_MASK << DMA_TX_QTAG_SHIFT);
+			if (i == nr_frags - 1)
+				txCBPtr->BdAddr->length_status |= DMA_EOP;
+
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+			if (index == DESC_INDEX)
+				pDevCtrl->txFreeBds -= 1;
+			else
+				pDevCtrl->txRingFreeBds[index] -= 1;
+#else
+			pDevCtrl->txFreeBds -= 1;
+#endif
+			/* advance producer index and write pointer.*/
+			tDma_ring->tdma_producer_index += 1;
+			tDma_ring->tdma_write_pointer = write_ptr;
+			/* update stats */
+			dev->stats.tx_bytes += frag->size;
+		}
+		dev->stats.tx_packets++;
+	}
+
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+	if (index == DESC_INDEX) {
+		if (pDevCtrl->txFreeBds <= (MAX_SKB_FRAGS + 1)) {
+			netif_stop_subqueue(dev, 0);
+			pDevCtrl->intrl2_0->cpu_mask_clear =
+				UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE;
+
+		}
+	} else if (pDevCtrl->txRingFreeBds[index] <= (MAX_SKB_FRAGS + 1)) {
+		netif_stop_subqueue(dev, index+1);
+		pDevCtrl->intrl2_1->cpu_mask_clear = (1 << index);
+	}
+#else
+	if (pDevCtrl->txFreeBds <= (MAX_SKB_FRAGS + 1)) {
+		/* Enable Tx bdone/pdone interrupt !*/
+		pDevCtrl->intrl2_0->cpu_mask_clear |= UMAC_IRQ_TXDMA_BDONE |
+			UMAC_IRQ_TXDMA_PDONE;
+		netif_stop_queue(dev);
+	}
+#endif
+	dev->trans_start = jiffies;
+
+	spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+
+	return 0;
+}
+
+/* NAPI polling method*/
+static int bcmgenet_poll(struct napi_struct *napi, int budget)
+{
+	struct BcmEnet_devctrl *pDevCtrl = container_of(napi,
+			struct BcmEnet_devctrl, napi);
+	volatile struct intrl2Regs *intrl2 = pDevCtrl->intrl2_0;
+	volatile struct rDmaRingRegs *rDma_desc;
+	unsigned int work_done;
+	work_done = bcmgenet_desc_rx(pDevCtrl, budget);
+
+	/* tx reclaim */
+	/*bcmgenet_xmit(NULL, pDevCtrl->dev);*/
+	/* Allocate new SKBs for the BD ring */
+	assign_rx_buffers(pDevCtrl);
+	/* Advancing our read pointer and consumer index*/
+	rDma_desc = &pDevCtrl->rxDma->rDmaRings[DESC_INDEX];
+	rDma_desc->rdma_consumer_index += work_done;
+	rDma_desc->rdma_read_pointer =
+		(work_done + rDma_desc->rdma_read_pointer) & (TOTAL_DESC - 1);
+	if (work_done < budget) {
+		napi_complete(napi);
+		intrl2->cpu_mask_clear |= UMAC_IRQ_RXDMA_BDONE;
+	}
+	return work_done;
+}
+
+/*
+ * Interrupt bottom half
+ */
+static void bcmgenet_irq_task(struct work_struct *work)
+{
+	struct BcmEnet_devctrl *pDevCtrl = container_of(
+			work, struct BcmEnet_devctrl, bcmgenet_irq_work);
+	struct net_device *dev;
+
+	dev = pDevCtrl->dev;
+
+	TRACE(("%s\n", __func__));
+	/* Cable plugged/unplugged event */
+	if (pDevCtrl->irq0_stat & UMAC_IRQ_PHY_DET_R) {
+		pDevCtrl->irq0_stat &= ~UMAC_IRQ_PHY_DET_R;
+		printk(KERN_CRIT "%s cable plugged in, powering up\n",
+				pDevCtrl->dev->name);
+		bcmgenet_power_up(pDevCtrl, GENET_POWER_CABLE_SENSE);
+	} else if (pDevCtrl->irq0_stat & UMAC_IRQ_PHY_DET_F) {
+		pDevCtrl->irq0_stat &= ~UMAC_IRQ_PHY_DET_F;
+		printk(KERN_CRIT "%s cable unplugged, powering down\n",
+				pDevCtrl->dev->name);
+		bcmgenet_power_down(pDevCtrl, GENET_POWER_CABLE_SENSE);
+	}
+	if (pDevCtrl->irq0_stat & UMAC_IRQ_MPD_R) {
+		pDevCtrl->irq0_stat &= ~UMAC_IRQ_MPD_R;
+		printk(KERN_CRIT "%s magic packet detected, waking up\n",
+				pDevCtrl->dev->name);
+		/* disable mpd interrupt */
+		pDevCtrl->intrl2_0->cpu_mask_set |= UMAC_IRQ_MPD_R;
+		/* disable CRC forward.*/
+		pDevCtrl->umac->cmd &= ~CMD_CRC_FWD;
+		if (pDevCtrl->dev_asleep)
+			bcmgenet_power_up(pDevCtrl, GENET_POWER_WOL_MAGIC);
+
+	} else if (pDevCtrl->irq0_stat & (UMAC_IRQ_HFB_SM | UMAC_IRQ_HFB_MM)) {
+		pDevCtrl->irq0_stat &= ~(UMAC_IRQ_HFB_SM | UMAC_IRQ_HFB_MM);
+		printk(KERN_CRIT "%s ACPI pattern matched, waking up\n",
+				pDevCtrl->dev->name);
+		/* disable HFB match interrupts */
+		pDevCtrl->intrl2_0->cpu_mask_set |= (UMAC_IRQ_HFB_SM |
+				UMAC_IRQ_HFB_MM);
+		if (pDevCtrl->dev_asleep)
+			bcmgenet_power_up(pDevCtrl, GENET_POWER_WOL_ACPI);
+	}
+
+	/* Link UP/DOWN event */
+	if (pDevCtrl->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN)) {
+		pDevCtrl->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN);
+		bcmgenet_mii_setup(pDevCtrl->dev);
+	}
+}
+
+/*
+ * bcmgenet_isr1: interrupt handler for ring buffer.
+ */
+static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
+{
+	struct BcmEnet_devctrl *pDevCtrl = dev_id;
+	volatile struct intrl2Regs *intrl2 = pDevCtrl->intrl2_1;
+	unsigned int index;
+
+	/* Save irq status for bottom-half processing. */
+	pDevCtrl->irq1_stat = intrl2->cpu_stat & ~intrl2->cpu_mask_status;
+	/* clear inerrupts*/
+	intrl2->cpu_clear |= pDevCtrl->irq1_stat;
+
+	TRACE(("%s: IRQ=0x%x\n", __func__, pDevCtrl->irq1_stat));
+	/*
+	 * Check the MBDONE interrupts.
+	 * packet is done, reclaim descriptors
+	 */
+	if (pDevCtrl->irq1_stat & 0x0000ffff) {
+		index = 0;
+		for (index = 0; index < 16; index++) {
+			if (pDevCtrl->irq1_stat & (1<<index))
+				bcmgenet_tx_reclaim(pDevCtrl->dev, index);
+		}
+	}
+	return IRQ_HANDLED;
+}
+/*
+ * bcmgenet_isr0: Handle various interrupts.
+ */
+static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
+{
+	struct BcmEnet_devctrl *pDevCtrl = dev_id;
+	volatile struct intrl2Regs *intrl2 = pDevCtrl->intrl2_0;
+
+	/* Save irq status for bottom-half processing. */
+	pDevCtrl->irq0_stat = intrl2->cpu_stat & ~intrl2->cpu_mask_status;
+	/* clear inerrupts*/
+	intrl2->cpu_clear |= pDevCtrl->irq0_stat;
+
+	TRACE(("IRQ=0x%x\n", pDevCtrl->irq0_stat));
+#ifndef CONFIG_BCMGENET_RX_DESC_THROTTLE
+	if (pDevCtrl->irq0_stat & (UMAC_IRQ_RXDMA_BDONE|UMAC_IRQ_RXDMA_PDONE)) {
+		/*
+		 * We use NAPI(software interrupt throttling, if
+		 * Rx Descriptor throttling is not used.
+		 * Disable interrupt, will be enabled in the poll method.
+		 */
+		if (likely(napi_schedule_prep(&pDevCtrl->napi))) {
+			intrl2->cpu_mask_set |= UMAC_IRQ_RXDMA_BDONE;
+			__napi_schedule(&pDevCtrl->napi);
+		}
+	}
+#else
+	/* Multiple buffer done event. */
+	if (pDevCtrl->irq0_stat & UMAC_IRQ_RXDMA_MBDONE) {
+		unsigned int work_done;
+		volatile struct rDmaRingRegs *rDma_desc;
+
+		rDma_desc = &pDevCtrl->rxDma->rDmaRings[DESC_INDEX];
+		pDevCtrl->irq0_stat &= ~UMAC_IRQ_RXDMA_MBDONE;
+		TRACE(("%s: %d packets available\n", __func__, DmaDescThres));
+		work_done = bcmgenet_desc_rx(pDevCtrl, DmaDescThres);
+		/* Allocate new SKBs for the BD ring */
+		assign_rx_buffers(pDevCtrl);
+		rDma_desc->rdma_consumer_index += work_done;
+		rDma_desc->rdma_read_pointer =
+			(work_done + rDma_desc->rdma_read_pointer) &
+			(TOTAL_DESC - 1);
+	}
+#endif
+	if (pDevCtrl->irq0_stat &
+			(UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
+		/* Tx reclaim */
+		bcmgenet_xmit(NULL, pDevCtrl->dev);
+	}
+	if (pDevCtrl->irq0_stat & (UMAC_IRQ_PHY_DET_R |
+				UMAC_IRQ_PHY_DET_F |
+				UMAC_IRQ_LINK_UP |
+				UMAC_IRQ_LINK_DOWN |
+				UMAC_IRQ_HFB_SM |
+				UMAC_IRQ_HFB_MM |
+				UMAC_IRQ_MPD_R)) {
+		/* all other interested interrupts handled in bottom half */
+		schedule_work(&pDevCtrl->bcmgenet_irq_work);
+	}
+
+	return IRQ_HANDLED;
+}
+/*
+ *  bcmgenet_desc_rx - descriptor based rx process.
+ *  this could be called from bottom half, or from NAPI polling method.
+ */
+static unsigned int bcmgenet_desc_rx(void *ptr, unsigned int budget)
+{
+	struct BcmEnet_devctrl *pDevCtrl = ptr;
+	struct net_device *dev = pDevCtrl->dev;
+	struct Enet_CB *cb;
+	struct sk_buff *skb;
+	unsigned long dmaFlag;
+	int len;
+	unsigned int rxpktprocessed = 0, rxpkttoprocess = 0;
+	unsigned int p_index = 0, c_index = 0, read_ptr = 0;
+
+	p_index = pDevCtrl->rxDma->rDmaRings[DESC_INDEX].rdma_producer_index;
+	p_index &= DMA_P_INDEX_MASK;
+	c_index = pDevCtrl->rxDma->rDmaRings[DESC_INDEX].rdma_consumer_index;
+	c_index &= DMA_C_INDEX_MASK;
+	read_ptr = pDevCtrl->rxDma->rDmaRings[DESC_INDEX].rdma_read_pointer;
+
+	if (p_index < c_index)
+		rxpkttoprocess = (DMA_C_INDEX_MASK+1) - c_index + p_index;
+	else
+		rxpkttoprocess = p_index - c_index;
+	TRACE(("RDMA: rxpkttoprocess=%d\n", rxpkttoprocess));
+
+	while ((rxpktprocessed < rxpkttoprocess) &&
+			(rxpktprocessed < budget)) {
+
+		dmaFlag = (pDevCtrl->rxBds[read_ptr].length_status & 0xffff);
+		len = ((pDevCtrl->rxBds[read_ptr].length_status)>>16);
+
+		TRACE(("%s:p_index=%d c_index=%d read_ptr=%d "
+			"len_stat=0x%08lx\n",
+			__func__, p_index, c_index, read_ptr,
+			pDevCtrl->rxBds[read_ptr].length_status));
+
+		rxpktprocessed++;
+
+		cb = &pDevCtrl->rxCbs[read_ptr];
+		skb = cb->skb;
+		BUG_ON(skb == NULL);
+		dma_unmap_single(&dev->dev, dma_unmap_addr(cb, dma_addr),
+				pDevCtrl->rxBufLen, DMA_FROM_DEVICE);
+
+		dmadesc_set_addr(&pDevCtrl->rxBds[read_ptr], 0);
+
+		if (read_ptr == pDevCtrl->nrRxBds-1)
+			read_ptr = 0;
+		else
+			read_ptr++;
+
+		if (unlikely(!(dmaFlag & DMA_EOP) || !(dmaFlag & DMA_SOP))) {
+			printk(KERN_WARNING "Droping fragmented packet!\n");
+			dev->stats.rx_dropped++;
+			dev->stats.rx_errors++;
+			dev_kfree_skb_any(cb->skb);
+			continue;
+		}
+		/* report errors */
+		if (unlikely(dmaFlag & (DMA_RX_CRC_ERROR |
+						DMA_RX_OV |
+						DMA_RX_NO |
+						DMA_RX_LG |
+						DMA_RX_RXER))) {
+			TRACE(("ERROR: dmaFlag=0x%x\n", (unsigned int)dmaFlag));
+			if (dmaFlag & DMA_RX_CRC_ERROR)
+				dev->stats.rx_crc_errors++;
+			if (dmaFlag & DMA_RX_OV)
+				dev->stats.rx_over_errors++;
+			if (dmaFlag & DMA_RX_NO)
+				dev->stats.rx_frame_errors++;
+			if (dmaFlag & DMA_RX_LG)
+				dev->stats.rx_length_errors++;
+			dev->stats.rx_dropped++;
+			dev->stats.rx_errors++;
+
+			/* discard the packet and advance consumer index.*/
+			dev_kfree_skb_any(cb->skb);
+			cb->skb = NULL;
+			continue;
+		} /* error packet */
+
+		skb_put(skb, len);
+		if (pDevCtrl->rbuf->rbuf_ctrl & RBUF_64B_EN) {
+			struct status_64 *status;
+			status = (struct status_64 *)skb->data;
+			/* we have 64B rx status block enabled.*/
+			if (pDevCtrl->rbuf->rbuf_chk_ctrl & RBUF_RXCHK_EN) {
+				if (status->rx_csum & STATUS_RX_CSUM_OK)
+					skb->ip_summed = CHECKSUM_UNNECESSARY;
+				else
+					skb->ip_summed = CHECKSUM_NONE;
+			}
+			skb_pull(skb, 64);
+			len -= 64;
+		}
+
+		if (pDevCtrl->bIPHdrOptimize) {
+			skb_pull(skb, 2);
+			len -= 2;
+		}
+
+		if (pDevCtrl->umac->cmd & CMD_CRC_FWD) {
+			skb_trim(skb, len - 4);
+			len -= 4;
+		}
+#ifdef CONFIG_BCMGENET_DUMP_DATA
+		printk(KERN_NOTICE "bcmgenet_desc_rx : len=%d", skb->len);
+		print_hex_dump(KERN_NOTICE, "", DUMP_PREFIX_ADDRESS,
+			16, 1, skb->data, skb->len, 0);
+#endif
+
+		/*Finish setting up the received SKB and send it to the kernel*/
+		skb->dev = pDevCtrl->dev;
+		skb->protocol = eth_type_trans(skb, pDevCtrl->dev);
+		dev->stats.rx_packets++;
+		dev->stats.rx_bytes += len;
+		if (dmaFlag & DMA_RX_MULT)
+			dev->stats.multicast++;
+
+		/* Notify kernel */
+#ifdef CONFIG_BCMGENET_RX_DESC_THROTTLE
+		netif_rx(skb);
+#else
+		netif_receive_skb(skb);
+#endif
+		cb->skb = NULL;
+		TRACE(("pushed up to kernel\n"));
+	}
+
+	return rxpktprocessed;
+}
+
+
+/*
+ * assign_rx_buffers:
+ * Assign skb to RX DMA descriptor.
+ */
+static int assign_rx_buffers(struct BcmEnet_devctrl *pDevCtrl)
+{
+	struct sk_buff *skb;
+	unsigned short bdsfilled = 0;
+	unsigned long flags;
+	struct Enet_CB *cb;
+	dma_addr_t mapping;
+
+	TRACE(("%s\n", __func__));
+
+	/* This function may be called from irq bottom-half. */
+
+#ifndef CONFIG_BCMGENET_RX_DESC_THROTTLE
+	(void)flags;
+	spin_lock_bh(&pDevCtrl->bh_lock);
+#else
+	spin_lock_irqsave(&pDevCtrl->lock, flags);
+#endif
+
+	/* loop here for each buffer needing assign */
+	while (dmadesc_get_addr(pDevCtrl->rxBdAssignPtr) == 0) {
+		cb = &pDevCtrl->rxCbs[pDevCtrl->rxBdAssignPtr-pDevCtrl->rxBds];
+		skb = netdev_alloc_skb(pDevCtrl->dev,
+				pDevCtrl->rxBufLen + SKB_ALIGNMENT);
+		if (!skb) {
+			printk(KERN_ERR " failed to allocate skb for rx\n");
+			break;
+		}
+		handleAlignment(pDevCtrl, skb);
+
+		/* keep count of any BD's we refill */
+		bdsfilled++;
+		cb->skb = skb;
+		mapping = dma_map_single(&pDevCtrl->dev->dev,
+			skb->data, pDevCtrl->rxBufLen, DMA_FROM_DEVICE);
+		if (dma_mapping_error(&pDevCtrl->dev->dev, mapping)) {
+			dev_err(&pDevCtrl->dev->dev, "assign_rx_buff DMA map failed\n");
+			break;
+		}
+		dma_unmap_addr_set(cb, dma_addr, mapping);
+		/* assign packet, prepare descriptor, and advance pointer */
+		dmadesc_set_addr(pDevCtrl->rxBdAssignPtr, mapping);
+		pDevCtrl->rxBdAssignPtr->length_status =
+			(pDevCtrl->rxBufLen << 16);
+
+		/* turn on the newly assigned BD for DMA to use */
+		if (pDevCtrl->rxBdAssignPtr ==
+				pDevCtrl->rxBds+pDevCtrl->nrRxBds-1)
+			pDevCtrl->rxBdAssignPtr = pDevCtrl->rxBds;
+		else
+			pDevCtrl->rxBdAssignPtr++;
+
+	}
+
+	/* Enable rx DMA incase it was disabled due to running out of rx BD */
+	pDevCtrl->rxDma->rdma_ctrl |= DMA_EN;
+
+#ifndef CONFIG_BCMGENET_RX_DESC_THROTTLE
+	spin_unlock_bh(&pDevCtrl->bh_lock);
+#else
+	spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+#endif
+
+	TRACE(("%s return bdsfilled=%d\n", __func__, bdsfilled));
+	return bdsfilled;
+}
+
+static void save_state(struct BcmEnet_devctrl *pDevCtrl)
+{
+	int ii;
+	volatile struct DmaDesc *rxBdAssignPtr = pDevCtrl->rxBds;
+
+	/*
+	 * FIXME: Why is this code saving/restoring descriptors across suspend?
+	 * Most other drivers just shut down and restart the network i/f.
+	 */
+	for (ii = 0; ii < pDevCtrl->nrRxBds; ++ii, ++rxBdAssignPtr) {
+		pDevCtrl->saved_rx_desc[ii].length_status =
+			rxBdAssignPtr->length_status;
+		dmadesc_set_addr(&pDevCtrl->saved_rx_desc[ii],
+				 dmadesc_get_addr(rxBdAssignPtr));
+	}
+
+	pDevCtrl->int_mask = pDevCtrl->intrl2_0->cpu_mask_status;
+	pDevCtrl->rbuf_ctrl = pDevCtrl->rbuf->rbuf_ctrl;
+}
+
+static void restore_state(struct BcmEnet_devctrl *pDevCtrl)
+{
+	int ii;
+	volatile struct DmaDesc *rxBdAssignPtr = pDevCtrl->rxBds;
+
+	pDevCtrl->intrl2_0->cpu_mask_clear = 0xFFFFFFFF ^ pDevCtrl->int_mask;
+	pDevCtrl->rbuf->rbuf_ctrl = pDevCtrl->rbuf_ctrl;
+
+	for (ii = 0; ii < pDevCtrl->nrRxBds; ++ii, ++rxBdAssignPtr) {
+		rxBdAssignPtr->length_status =
+			pDevCtrl->saved_rx_desc[ii].length_status;
+		dmadesc_set_addr(rxBdAssignPtr,
+			dmadesc_get_addr(&pDevCtrl->saved_rx_desc[ii]));
+	}
+
+	pDevCtrl->rxDma->rdma_ctrl |= DMA_EN;
+
+}
+
+/*
+ * init_umac: Initializes the uniMac controller
+ */
+static int init_umac(struct BcmEnet_devctrl *pDevCtrl)
+{
+	volatile struct uniMacRegs *umac;
+	volatile struct intrl2Regs *intrl2;
+
+	umac = pDevCtrl->umac;
+	intrl2 = pDevCtrl->intrl2_0;
+
+	TRACE(("bcmgenet: init_umac "));
+
+	/* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
+	GENET_RBUF_FLUSH_CTRL(pDevCtrl) = 0;
+	udelay(10);
+
+	/* disable MAC while updating its registers */
+	umac->cmd = 0;
+
+	/* issue soft reset, wait for it to complete */
+	umac->cmd = CMD_SW_RESET;
+	udelay(1000);
+	umac->cmd = 0;
+	/* clear tx/rx counter */
+	umac->mib_ctrl = MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT;
+	umac->mib_ctrl = 0;
+
+#ifdef MAC_LOOPBACK
+	/* Enable GMII/MII loopback */
+	umac->cmd |= CMD_LCL_LOOP_EN;
+#endif
+	umac->max_frame_len = ENET_MAX_MTU_SIZE;
+	/*
+	 * init rx registers, enable ip header optimization.
+	 */
+	if (pDevCtrl->bIPHdrOptimize)
+		pDevCtrl->rbuf->rbuf_ctrl |= RBUF_ALIGN_2B ;
+#if CONFIG_BRCM_GENET_VERSION >= 3
+	pDevCtrl->rbuf->rbuf_tbuf_size_ctrl = 1;
+#endif
+
+	/* Mask all interrupts.*/
+	intrl2->cpu_mask_set = 0xFFFFFFFF;
+	intrl2->cpu_clear = 0xFFFFFFFF;
+	intrl2->cpu_mask_clear = 0x0;
+
+#ifdef CONFIG_BCMGENET_RX_DESC_THROTTLE
+	intrl2->cpu_mask_clear |= UMAC_IRQ_RXDMA_MBDONE;
+#else
+	intrl2->cpu_mask_clear |= UMAC_IRQ_RXDMA_BDONE;
+	TRACE(("%s:Enabling RXDMA_BDONE interrupt\n", __func__));
+#endif /* CONFIG_BCMGENET_RX_DESC_THROTTLE */
+
+	/* Monitor cable plug/unpluged event for internal PHY */
+	if (pDevCtrl->phyType == BRCM_PHY_TYPE_INT) {
+		/* HW7445-870: energy detect on A0 silicon is unreliable */
+		intrl2->cpu_mask_clear |= (UMAC_IRQ_PHY_DET_R |
+				UMAC_IRQ_PHY_DET_F);
+		intrl2->cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN |
+				UMAC_IRQ_LINK_UP);
+		/* Turn on ENERGY_DET interrupt in bcmgenet_open()
+		 * TODO: fix me for active standby.
+		 */
+	} else if (pDevCtrl->extPhy) {
+		intrl2->cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN |
+				UMAC_IRQ_LINK_UP);
+	} else if (pDevCtrl->phyType == BRCM_PHY_TYPE_MOCA) {
+		GENET_TBUF_BP_MC(pDevCtrl) |= BIT(GENET_BP_IN_EN_SHIFT);
+
+		/* bp_mask: back pressure mask */
+#if defined(CONFIG_NET_SCH_MULTIQ)
+		GENET_TBUF_BP_MC(pDevCtrl) |= GENET_BP_MASK;
+#else
+		GENET_TBUF_BP_MC(pDevCtrl) &= ~GENET_BP_MASK;
+#endif
+	}
+
+	/* Enable rx/tx engine.*/
+	TRACE(("done init umac\n"));
+	return 0;
+}
+/*
+ * init_edma: Initialize DMA control register
+ */
+static void init_edma(struct BcmEnet_devctrl *pDevCtrl)
+{
+#ifdef CONFIG_BCMGENET_RX_DESC_THROTTLE
+	int speeds[] = {10, 100, 1000, 2500};
+	int sid = 1, timeout, __maybe_unused first_bd;
+#endif
+	volatile struct rDmaRingRegs *rDma_desc;
+	volatile struct tDmaRingRegs *tDma_desc;
+	TRACE(("bcmgenet: init_edma\n"));
+
+	/* init rDma */
+	pDevCtrl->rxDma->rdma_scb_burst_size = DMA_MAX_BURST_LENGTH;
+	/* by default, enable ring 16 (descriptor based) */
+	rDma_desc = &pDevCtrl->rxDma->rDmaRings[DESC_INDEX];
+	rDma_desc->rdma_write_pointer = 0;
+	rDma_desc->rdma_producer_index = 0;
+	rDma_desc->rdma_consumer_index = 0;
+	rDma_desc->rdma_ring_buf_size = ((TOTAL_DESC << DMA_RING_SIZE_SHIFT) |
+		RX_BUF_LENGTH);
+	rDma_desc->rdma_start_addr = 0;
+	rDma_desc->rdma_end_addr = WORDS_PER_BD * TOTAL_DESC - 1;
+	rDma_desc->rdma_xon_xoff_threshold = ((DMA_FC_THRESH_LO
+			<< DMA_XOFF_THRESHOLD_SHIFT) |
+			DMA_FC_THRESH_HI);
+	rDma_desc->rdma_read_pointer = 0;
+
+#ifdef CONFIG_BCMGENET_RX_DESC_THROTTLE
+	/*
+	 * Use descriptor throttle, fire irq when multiple packets are done!
+	 */
+	rDma_desc->rdma_mbuf_done_threshold = DMA_DESC_THRES;
+	/*
+	 * Enable push timer, force the IRQ_DESC_THROT to fire when timeout
+	 * occurs, prevent system slow reponse when handling low throughput.
+	 */
+	sid = (pDevCtrl->umac->cmd >> CMD_SPEED_SHIFT) & CMD_SPEED_MASK;
+	timeout = 2*(DMA_DESC_THRES*ENET_MAX_MTU_SIZE)/speeds[sid];
+	pDevCtrl->rxDma->rdma_timeout[DESC_INDEX] = timeout & DMA_TIMEOUT_MASK;
+#endif	/* CONFIG_BCMGENET_RX_DESC_THROTTLE */
+
+
+	/* Init tDma */
+	pDevCtrl->txDma->tdma_scb_burst_size = DMA_MAX_BURST_LENGTH;
+	/* by default, enable ring DESC_INDEX (descriptor based) */
+	tDma_desc = &pDevCtrl->txDma->tDmaRings[DESC_INDEX];
+	tDma_desc->tdma_producer_index = 0;
+	tDma_desc->tdma_consumer_index = 0;
+	tDma_desc->tdma_mbuf_done_threshold = 1;
+	/* Disable rate control for now */
+	tDma_desc->tdma_flow_period = 0;
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+	/* Unclassified traffic goes to ring 16 */
+	tDma_desc->tdma_ring_buf_size = ((GENET_DEFAULT_BD_CNT <<
+				DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH);
+
+	first_bd = GENET_MQ_CNT * GENET_MQ_BD_CNT;
+	tDma_desc->tdma_start_addr = first_bd * WORDS_PER_BD;
+	tDma_desc->tdma_read_pointer = first_bd * WORDS_PER_BD;
+	tDma_desc->tdma_write_pointer = first_bd;
+	tDma_desc->tdma_end_addr = TOTAL_DESC * WORDS_PER_BD - 1;
+	pDevCtrl->txFreeBds = GENET_DEFAULT_BD_CNT;
+	/* initiaize multi xmit queue */
+	bcmgenet_init_multiq(pDevCtrl->dev);
+
+#else
+	tDma_desc->tdma_ring_buf_size = ((TOTAL_DESC << DMA_RING_SIZE_SHIFT) |
+			RX_BUF_LENGTH);
+	tDma_desc->tdma_start_addr = 0;
+	tDma_desc->tdma_end_addr = WORDS_PER_BD * TOTAL_DESC - 1;
+	tDma_desc->tdma_read_pointer = 0;
+
+	/*
+	 * FIXME: tdma_write_pointer and rdma_read_pointer are essentially
+	 * scratch registers and the GENET block does not use them for
+	 * anything.  We should maintain them in DRAM instead, because
+	 * register accesses are expensive.
+	 */
+	tDma_desc->tdma_write_pointer = 0;
+#endif
+
+}
+
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+/*
+ * init multi xmit queues, only available for GENET2
+ * the queue is partitioned as follows:
+ *
+ * queue 0 - 3 is priority based, each one has 48 descriptors,
+ * with queue 0 being the highest priority queue.
+ *
+ * queue 16 is the default tx queue, with 64 descriptors.
+ */
+static void bcmgenet_init_multiq(struct net_device *dev)
+{
+	int i, dma_enable;
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+
+	dma_enable = pDevCtrl->txDma->tdma_ctrl & DMA_EN;
+	pDevCtrl->txDma->tdma_ctrl &= ~DMA_EN;
+	/* Enable strict priority arbiter mode */
+	pDevCtrl->txDma->tdma_arb_ctrl = 0x2;
+	for (i = 0; i < GENET_MQ_CNT; i++) {
+		int first_bd;
+
+		/* first 64 txCbs are reserved for default tx queue (ring 16) */
+		pDevCtrl->txRingCBs[i] = pDevCtrl->txCbs +
+			GENET_DEFAULT_BD_CNT + i * GENET_MQ_BD_CNT;
+		pDevCtrl->txRingSize[i] = GENET_MQ_BD_CNT;
+		pDevCtrl->txRingCIndex[i] = 0;
+		pDevCtrl->txRingFreeBds[i] = GENET_MQ_BD_CNT;
+
+		pDevCtrl->txDma->tDmaRings[i].tdma_producer_index = 0;
+		pDevCtrl->txDma->tDmaRings[i].tdma_consumer_index = 0;
+		pDevCtrl->txDma->tDmaRings[i].tdma_ring_buf_size =
+			(GENET_MQ_BD_CNT << DMA_RING_SIZE_SHIFT) |
+			RX_BUF_LENGTH;
+
+		first_bd = GENET_MQ_BD_CNT * i;
+		pDevCtrl->txDma->tDmaRings[i].tdma_start_addr =
+			first_bd * WORDS_PER_BD;
+		pDevCtrl->txDma->tDmaRings[i].tdma_read_pointer =
+			first_bd * WORDS_PER_BD;
+		pDevCtrl->txDma->tDmaRings[i].tdma_write_pointer = first_bd;
+
+		pDevCtrl->txDma->tDmaRings[i].tdma_end_addr =
+			WORDS_PER_BD * (i + 1) * GENET_MQ_BD_CNT - 1;
+		pDevCtrl->txDma->tDmaRings[i].tdma_flow_period =
+			ENET_MAX_MTU_SIZE << 16;
+		pDevCtrl->txDma->tDmaRings[i].tdma_mbuf_done_threshold = 1;
+
+		/* Configure ring as decriptor ring and setup priority */
+		pDevCtrl->txDma->tdma_ring_cfg |= (1 << i);
+		pDevCtrl->txDma->tdma_priority[0] |=
+			((GENET_Q0_PRIORITY + i) << 5*i);
+		pDevCtrl->txDma->tdma_ctrl |=
+			(1 << (i + DMA_RING_BUF_EN_SHIFT));
+	}
+	/* Set ring #16 priority */
+	pDevCtrl->txDma->tdma_priority[2] |=
+		((GENET_Q0_PRIORITY + GENET_MQ_CNT) << 20);
+	if (dma_enable)
+		pDevCtrl->txDma->tdma_ctrl |= DMA_EN;
+}
+#endif
+/*
+ * bcmgenet_init_dev: initialize uniMac devie
+ * allocate Tx/Rx buffer descriptors pool, Tx control block pool.
+ */
+static int bcmgenet_init_dev(struct BcmEnet_devctrl *pDevCtrl)
+{
+	int i, ret;
+	unsigned long base;
+	void *ptxCbs, *prxCbs;
+	volatile struct DmaDesc *lastBd;
+
+	pDevCtrl->clk = clk_get(&pDevCtrl->pdev->dev, "enet");
+	pDevCtrl->clk_wol = clk_get(&pDevCtrl->pdev->dev, "enet-wol");
+	bcmgenet_clock_enable(pDevCtrl);
+
+	TRACE(("%s\n", __func__));
+	/* setup buffer/pointer relationships here */
+	pDevCtrl->nrTxBds = pDevCtrl->nrRxBds = TOTAL_DESC;
+	/* Always use 2KB buffer for 7420*/
+	pDevCtrl->rxBufLen = RX_BUF_LENGTH;
+
+	/* register block locations */
+	base = pDevCtrl->dev->base_addr;
+	pDevCtrl->sys = (struct SysRegs *)(base);
+	pDevCtrl->grb = (struct GrBridgeRegs *)(base + GENET_GR_BRIDGE_OFF);
+	pDevCtrl->ext = (struct ExtRegs *)(base + GENET_EXT_OFF);
+#if CONFIG_BRCM_GENET_VERSION == 1
+	/* SWLINUX-1813: EXT block is not available on MOCA_GENET */
+#if !defined(CONFIG_BCM7125)
+	if (pDevCtrl->devnum == 1)
+#endif
+		pDevCtrl->ext = NULL;
+#endif
+	pDevCtrl->intrl2_0 = (struct intrl2Regs *)(base + GENET_INTRL2_0_OFF);
+	pDevCtrl->intrl2_1 = (struct intrl2Regs *)(base + GENET_INTRL2_1_OFF);
+	pDevCtrl->rbuf = (struct rbufRegs *)(base + GENET_RBUF_OFF);
+	pDevCtrl->umac = (struct uniMacRegs *)(base + GENET_UMAC_OFF);
+	pDevCtrl->hfb = (unsigned long *)(base + GENET_HFB_OFF);
+	pDevCtrl->txDma = (struct tDmaRegs *)(base + GENET_TDMA_REG_OFF);
+	pDevCtrl->rxDma = (struct rDmaRegs *)(base + GENET_RDMA_REG_OFF);
+
+#if CONFIG_BRCM_GENET_VERSION > 1
+	pDevCtrl->tbuf = (struct tbufRegs *)(base + GENET_TBUF_OFF);
+	pDevCtrl->hfbReg = (struct hfbRegs *)(base + GENET_HFB_REG_OFF);
+#endif
+
+	pDevCtrl->rxBds = (struct DmaDesc *)(base + GENET_RDMA_OFF);
+	pDevCtrl->txBds = (struct DmaDesc *)(base + GENET_TDMA_OFF);
+
+	TRACE(("%s: rxbds=0x%08x txbds=0x%08x\n", __func__,
+		(unsigned int)pDevCtrl->rxBds, (unsigned int)pDevCtrl->txBds));
+
+	/* alloc space for the tx control block pool */
+	ptxCbs = kmalloc(pDevCtrl->nrTxBds*sizeof(struct Enet_CB), GFP_KERNEL);
+	if (!ptxCbs) {
+		bcmgenet_clock_disable(pDevCtrl);
+		return -ENOMEM;
+	}
+	memset(ptxCbs, 0, pDevCtrl->nrTxBds*sizeof(struct Enet_CB));
+	pDevCtrl->txCbs = (struct Enet_CB *)ptxCbs;
+
+	/* initialize rx ring pointer variables. */
+	pDevCtrl->rxBdAssignPtr = pDevCtrl->rxBds;
+	prxCbs = kmalloc(pDevCtrl->nrRxBds*sizeof(struct Enet_CB), GFP_KERNEL);
+	if (!prxCbs) {
+		ret = -ENOMEM;
+		goto error2;
+	}
+	memset(prxCbs, 0, pDevCtrl->nrRxBds*sizeof(struct Enet_CB));
+	pDevCtrl->rxCbs = (struct Enet_CB *)prxCbs;
+
+	/* init the receive buffer descriptor ring */
+	for (i = 0; i < pDevCtrl->nrRxBds; i++) {
+		pDevCtrl->rxBds[i].length_status = (pDevCtrl->rxBufLen<<16);
+		dmadesc_set_addr(&pDevCtrl->rxBds[i], 0);
+	}
+	lastBd = pDevCtrl->rxBds + pDevCtrl->nrRxBds - 1;
+
+	/* clear the transmit buffer descriptors */
+	for (i = 0; i < pDevCtrl->nrTxBds; i++) {
+		pDevCtrl->txBds[i].length_status = 0<<16;
+		dmadesc_set_addr(&pDevCtrl->txBds[i], 0);
+	}
+	lastBd = pDevCtrl->txBds + pDevCtrl->nrTxBds - 1;
+	pDevCtrl->txFreeBds = pDevCtrl->nrTxBds;
+
+	/* fill receive buffers */
+	if (assign_rx_buffers(pDevCtrl) == 0) {
+		printk(KERN_ERR "Failed to assign rx buffers\n");
+		ret = -ENOMEM;
+		goto error1;
+	}
+
+	TRACE(("%s done!\n", __func__));
+	/* init umac registers */
+	if (init_umac(pDevCtrl)) {
+		ret = -EFAULT;
+		goto error1;
+	}
+
+	/* init dma registers */
+	init_edma(pDevCtrl);
+
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+	pDevCtrl->nrTxBds = GENET_DEFAULT_BD_CNT;
+#endif
+
+	TRACE(("%s done!\n", __func__));
+	/* if we reach this point, we've init'ed successfully */
+	return 0;
+error1:
+	kfree(prxCbs);
+error2:
+	kfree(ptxCbs);
+	bcmgenet_clock_disable(pDevCtrl);
+
+	TRACE(("%s Failed!\n", __func__));
+	return ret;
+}
+
+/* Uninitialize tx/rx buffer descriptor pools */
+static void bcmgenet_uninit_dev(struct BcmEnet_devctrl *pDevCtrl)
+{
+	int i;
+
+	if (pDevCtrl) {
+		/* disable DMA */
+		pDevCtrl->rxDma->rdma_ctrl = 0;
+		pDevCtrl->txDma->tdma_ctrl = 0;
+
+		for (i = 0; i < pDevCtrl->nrTxBds; i++) {
+			if (pDevCtrl->txCbs[i].skb != NULL) {
+				dev_kfree_skb(pDevCtrl->txCbs[i].skb);
+				pDevCtrl->txCbs[i].skb = NULL;
+			}
+		}
+		for (i = 0; i < pDevCtrl->nrRxBds; i++) {
+			if (pDevCtrl->rxCbs[i].skb != NULL) {
+				dev_kfree_skb(pDevCtrl->rxCbs[i].skb);
+				pDevCtrl->rxCbs[i].skb = NULL;
+			}
+		}
+
+		/* free the transmit buffer descriptor */
+		if (pDevCtrl->txBds)
+			pDevCtrl->txBds = NULL;
+		/* free the receive buffer descriptor */
+		if (pDevCtrl->rxBds)
+			pDevCtrl->rxBds = NULL;
+		/* free the transmit control block pool */
+		kfree(pDevCtrl->txCbs);
+		/* free the transmit control block pool */
+		kfree(pDevCtrl->rxCbs);
+
+		clk_put(pDevCtrl->clk);
+	}
+}
+
+#define FILTER_POS(i)	(((HFB_NUM_FLTRS-i-1)>>2))
+#define SET_HFB_FILTER_LEN(dev, i, len) \
+do { \
+	u32 tmp = GENET_HFB_FLTR_LEN(dev, FILTER_POS(i)); \
+	tmp &= ~(RBUF_FLTR_LEN_MASK << (RBUF_FLTR_LEN_SHIFT * (i & 0x03))); \
+	tmp |= (len << (RBUF_FLTR_LEN_SHIFT * (i & 0x03))); \
+	GENET_HFB_FLTR_LEN(dev, FILTER_POS(i)) = tmp; \
+} while (0)
+
+#define GET_HFB_FILTER_LEN(dev, i) \
+	((GENET_HFB_FLTR_LEN(dev, FILTER_POS(i)) >> \
+		(RBUF_FLTR_LEN_SHIFT * (i & 0x03))) & RBUF_FLTR_LEN_MASK)
+
+#if CONFIG_BRCM_GENET_VERSION >= 3
+/* The order of GENET_x_HFB_FLT_ENBLE_0/1 is reversed !!! */
+#define	GET_HFB_FILTER_EN(dev, i) \
+	(dev->hfbReg->hfb_flt_enable[i < 32] & (1 << (i % 32)))
+#define HFB_FILTER_ENABLE(dev, i) \
+	(dev->hfbReg->hfb_flt_enable[i < 32] |= (1 << (i % 32)))
+#define HFB_FILTER_DISABLE(dev, i) \
+	(dev->hfbReg->hfb_flt_enable[i < 32] &= ~(1 << (i % 32)))
+#define	HFB_FILTER_DISABLE_ALL(dev) \
+	do { \
+		dev->hfbReg->hfb_flt_enable[0] = 0; \
+		dev->hfbReg->hfb_flt_enable[1] = 0; \
+	} while (0)
+#else
+#define GET_HFB_FILTER_EN(dev, i) \
+	((GENET_HFB_CTRL(dev) >> (i + RBUF_HFB_FILTER_EN_SHIFT)) & 0x01)
+#define HFB_FILTER_ENABLE(dev, i) \
+	(GENET_HFB_CTRL(dev) |= 1 << (i + RBUF_HFB_FILTER_EN_SHIFT))
+#define HFB_FILTER_DISABLE(dev, i) \
+	(GENET_HFB_CTRL(dev) &= ~(1 << (i + RBUF_HFB_FILTER_EN_SHIFT)))
+#define	HFB_FILTER_DISABLE_ALL(dev) \
+	(GENET_HFB_CTRL(dev) &= ~(0xffff << (RBUF_HFB_FILTER_EN_SHIFT)))
+#endif
+
+/*
+ * Program ACPI pattern into HFB. Return filter index if succesful.
+ * if user == 1, the data will be copied from user space.
+ */
+int bcmgenet_update_hfb(struct net_device *dev, unsigned int *data,
+		int len, int user)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	int filter, offset, count;
+	unsigned int *tmp;
+
+	TRACE(("Updating HFB len=0x%d\n", len));
+
+	count = HFB_NUM_FLTRS;
+	offset = 64;
+	if (GENET_HFB_CTRL(pDevCtrl) & RBUF_HFB_256B) {
+#if CONFIG_BRCM_GENET_VERSION < 3
+		count >>= 1;
+#endif
+		offset = 128;
+	}
+
+	if (len > offset)
+		return -EINVAL;
+
+	/* find next unused filter */
+	for (filter = 0; filter < count; filter++) {
+		if (!GET_HFB_FILTER_EN(pDevCtrl, filter))
+			break;
+	}
+	if (filter == count) {
+		printk(KERN_ERR "no unused filter available!\n");
+		return -EINVAL;	/* all filters have been enabled*/
+	}
+
+	if (user) {
+		tmp = kmalloc(len*sizeof(unsigned int), GFP_KERNEL);
+		if (tmp == NULL) {
+			printk(KERN_ERR "%s: Malloc faild\n", __func__);
+			return -EFAULT;
+		}
+		/* copy pattern data */
+		if (copy_from_user(tmp, data, len*sizeof(unsigned int)) != 0) {
+			printk(KERN_ERR "Failed to copy user data: src=%p, dst=%p\n",
+				data, pDevCtrl->hfb + filter*offset);
+			return -EFAULT;
+		}
+	} else {
+		tmp = data;
+	}
+	/* Copy pattern data into HFB registers.*/
+	for (count = 0; count < offset; count++) {
+		if (count < len)
+			pDevCtrl->hfb[filter * offset + count] = *(tmp + count);
+		else
+			pDevCtrl->hfb[filter * offset + count] = 0;
+	}
+	if (user)
+		kfree(tmp);
+
+	/* set the filter length*/
+	SET_HFB_FILTER_LEN(pDevCtrl, filter, len*2);
+
+	/*enable this filter.*/
+	HFB_FILTER_ENABLE(pDevCtrl, filter);
+
+	return filter;
+
+}
+EXPORT_SYMBOL(bcmgenet_update_hfb);
+/*
+ * read ACPI pattern data for a particular filter.
+ */
+static int bcmgenet_read_hfb(struct net_device *dev, struct acpi_data *u_data)
+{
+	int filter, offset, count, len;
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+
+	if (get_user(filter, &(u_data->fltr_index))) {
+		printk(KERN_ERR "Failed to get user data\n");
+		return -EFAULT;
+	}
+
+	count = HFB_NUM_FLTRS;
+	offset = 128;
+	if (GENET_HFB_CTRL(pDevCtrl) & RBUF_HFB_256B) {
+#if CONFIG_BRCM_GENET_VERSION < 3
+		count >>= 1;
+#endif
+		offset = 256;
+	}
+
+	if (filter > count)
+		return -EINVAL;
+
+	/* see if this filter is enabled, if not, return length 0 */
+	if (!GET_HFB_FILTER_EN(pDevCtrl, filter)) {
+		len = 0;
+		put_user(len , &u_data->count);
+		return 0;
+	}
+	/* check the filter length, in bytes */
+	len = GET_HFB_FILTER_LEN(pDevCtrl, filter);
+	if (u_data->count < len)
+		return -EINVAL;
+	/* copy pattern data */
+	if (copy_to_user((void *)(u_data->p_data),
+			(void *)(pDevCtrl->hfb + filter*offset), len)) {
+		printk(KERN_ERR "Failed to copy data to user space: src=%p, dst=%p\n",
+				pDevCtrl->hfb+filter*offset, u_data->p_data);
+		return -EFAULT;
+	}
+	return len;
+}
+/*
+ * clear the HFB, disable filter indexed by "filter" argument.
+ */
+static inline void bcmgenet_clear_hfb(struct BcmEnet_devctrl *pDevCtrl,
+		int filter)
+{
+	if (filter == CLEAR_ALL_HFB) {
+		HFB_FILTER_DISABLE_ALL(pDevCtrl);
+		GENET_HFB_CTRL(pDevCtrl) &= ~RBUF_HFB_EN;
+	} else {
+		/* disable this filter */
+		HFB_FILTER_DISABLE(pDevCtrl, filter);
+		/* clear filter length register */
+		SET_HFB_FILTER_LEN(pDevCtrl, filter, 0);
+	}
+
+}
+/*
+ * Utility function to get interface ip address in kernel space.
+ */
+static inline unsigned int bcmgenet_getip(struct net_device *dev)
+{
+	struct net_device *pnet_device;
+	unsigned int ip = 0;
+
+	read_lock(&dev_base_lock);
+	/* read all devices */
+	for_each_netdev(&init_net, pnet_device)
+	{
+		if ((netif_running(pnet_device)) &&
+				(pnet_device->ip_ptr != NULL) &&
+				(!strcmp(pnet_device->name, dev->name))) {
+			struct in_device *pin_dev;
+			pin_dev = (struct in_device *)(pnet_device->ip_ptr);
+			if (pin_dev && pin_dev->ifa_list)
+				ip = htonl(pin_dev->ifa_list->ifa_address);
+			break;
+		}
+	}
+	read_unlock(&dev_base_lock);
+	return ip;
+}
+
+static void bcmgenet_clock_enable(struct BcmEnet_devctrl *pDevCtrl)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&pDevCtrl->lock, flags);
+	clk_enable(pDevCtrl->clk);
+	pDevCtrl->clock_active = 1;
+	spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+}
+
+static void bcmgenet_clock_disable(struct BcmEnet_devctrl *pDevCtrl)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&pDevCtrl->lock, flags);
+	pDevCtrl->clock_active = 0;
+	clk_disable(pDevCtrl->clk);
+	spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+}
+
+/*
+ * ethtool function - get WOL (Wake on LAN) settings,
+ * Only Magic Packet Detection is supported through ethtool,
+ * the ACPI (Pattern Matching) WOL option is supported in
+ * bcmumac_do_ioctl function.
+ */
+static void bcmgenet_get_wol(struct net_device *dev,
+		struct ethtool_wolinfo *wol)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	volatile struct uniMacRegs *umac = pDevCtrl->umac;
+	wol->supported = WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_ARP;
+
+	if (!netif_running(dev))
+		return;
+
+	wol->wolopts = pDevCtrl->wolopts;
+	if (wol->wolopts & WAKE_MAGICSECURE) {
+		put_unaligned_be16(umac->mpd_pw_ms, &wol->sopass[0]);
+		put_unaligned_be32(umac->mpd_pw_ls, &wol->sopass[2]);
+	} else {
+		memset(&wol->sopass[0], 0, sizeof(wol->sopass));
+	}
+}
+
+/*
+ * ethtool function - set WOL (Wake on LAN) settings.
+ * Only for magic packet detection mode.
+ */
+static int bcmgenet_set_wol(struct net_device *dev,
+		struct ethtool_wolinfo *wol)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	volatile struct uniMacRegs *umac = pDevCtrl->umac;
+
+	if (wol->wolopts & ~(WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_ARP))
+		return -EINVAL;
+
+	if (wol->wolopts & WAKE_MAGICSECURE) {
+		umac->mpd_pw_ms = get_unaligned_be16(&wol->sopass[0]);
+		umac->mpd_pw_ls = get_unaligned_be32(&wol->sopass[2]);
+		umac->mpd_ctrl |= MPD_PW_EN;
+	}
+
+	device_set_wakeup_enable(&dev->dev, wol->wolopts);
+	pDevCtrl->wolopts = wol->wolopts;
+	return 0;
+}
+/*
+ * ethtool function - get generic settings.
+ */
+static int bcmgenet_get_settings(struct net_device *dev,
+		struct ethtool_cmd *cmd)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	int rc = 0;
+
+	if (pDevCtrl->phyType == BRCM_PHY_TYPE_MOCA) {
+		/* see comments in bcmgenet_set_settings() */
+		cmd->autoneg = netif_carrier_ok(pDevCtrl->dev);
+		cmd->speed = SPEED_1000;
+		cmd->duplex = DUPLEX_HALF;
+		cmd->port = PORT_BNC;
+	} else {
+		if (!netif_running(dev))
+			return -EINVAL;
+		rc = mii_ethtool_gset(&pDevCtrl->mii, cmd);
+	}
+
+	return rc;
+}
+/*
+ * ethtool function - set settings.
+ */
+static int bcmgenet_set_settings(struct net_device *dev,
+		struct ethtool_cmd *cmd)
+{
+	int err = 0;
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+
+	if (pDevCtrl->phyType == BRCM_PHY_TYPE_MOCA) {
+		/* mocad uses cmd->autoneg to control our RUNNING flag */
+		if (cmd->autoneg)
+			netif_carrier_on(pDevCtrl->dev);
+		else
+			netif_carrier_off(pDevCtrl->dev);
+	} else {
+		if (!netif_running(dev))
+			return -EINVAL;
+
+		err = mii_ethtool_sset(&pDevCtrl->mii, cmd);
+		if (err < 0)
+			return err;
+		bcmgenet_mii_setup(dev);
+
+		if (cmd->maxrxpkt != 0)
+			DmaDescThres = cmd->maxrxpkt;
+	}
+
+	return err;
+}
+/*
+ * ethtool function - get driver info.
+ */
+static void bcmgenet_get_drvinfo(struct net_device *dev,
+		struct ethtool_drvinfo *info)
+{
+	strncpy(info->driver, CARDNAME, sizeof(info->driver));
+	strncpy(info->version, VER_STR, sizeof(info->version));
+
+}
+static int bcmgenet_set_rx_csum(struct net_device *dev)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	spin_lock_bh(&pDevCtrl->bh_lock);
+	if (!(dev->flags & NETIF_F_RXCSUM)) {
+		/*pDevCtrl->rbuf->rbuf_endian_ctrl &= ~RBUF_ENDIAN_NOSWAP;*/
+		pDevCtrl->rbuf->rbuf_ctrl &= ~RBUF_64B_EN;
+		pDevCtrl->rbuf->rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
+	} else {
+		/*pDevCtrl->rbuf->rbuf_endian_ctrl &= ~RBUF_ENDIAN_NOSWAP;*/
+		pDevCtrl->rbuf->rbuf_ctrl |= RBUF_64B_EN;
+		pDevCtrl->rbuf->rbuf_chk_ctrl |= RBUF_RXCHK_EN ;
+	}
+	spin_unlock_bh(&pDevCtrl->bh_lock);
+	return 0;
+}
+static int bcmgenet_set_tx_csum(struct net_device *dev)
+{
+	unsigned long flags;
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	spin_lock_irqsave(&pDevCtrl->lock, flags);
+	if (!(dev->features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))) {
+		GENET_TBUF_CTRL(pDevCtrl) &= ~RBUF_64B_EN;
+		if (dev->needed_headroom > 64)
+			dev->needed_headroom -= 64;
+	} else {
+		GENET_TBUF_CTRL(pDevCtrl) |= RBUF_64B_EN;
+		if (dev->needed_headroom < 64)
+			dev->needed_headroom += 64;
+	}
+	spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+	return 0;
+}
+static int bcmgenet_set_sg(struct net_device *dev)
+{
+	if ((dev->features & NETIF_F_SG) &&
+			!(dev->features & NETIF_F_IP_CSUM)) {
+		printk(KERN_WARNING "Tx Checksum offloading disabled, not setting SG\n");
+		return -EINVAL;
+	}
+	/* must have 64B tx status enabled */
+	return 0;
+}
+static int bcmgenet_set_features(struct net_device *dev,
+		netdev_features_t features)
+{
+	int ret;
+	netdev_features_t changed = features ^ dev->features;
+	if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
+		ret = bcmgenet_set_tx_csum(dev);
+	if (changed & (NETIF_F_RXCSUM))
+		ret = bcmgenet_set_rx_csum(dev);
+	if (changed & NETIF_F_SG)
+		ret = bcmgenet_set_sg(dev);
+
+	return ret;
+}
+
+/*
+ * standard ethtool support functions.
+ */
+static struct ethtool_ops bcmgenet_ethtool_ops = {
+	.get_settings		= bcmgenet_get_settings,
+	.set_settings		= bcmgenet_set_settings,
+	.get_drvinfo		= bcmgenet_get_drvinfo,
+	.get_wol			= bcmgenet_get_wol,
+	.set_wol			= bcmgenet_set_wol,
+	.get_link			= ethtool_op_get_link,
+};
+
+static int bcmgenet_enable_arp_filter(struct BcmEnet_devctrl *pDevCtrl)
+{
+	struct net_device *dev = pDevCtrl->dev;
+	unsigned int ip;
+
+	ip = bcmgenet_getip(dev);
+	if (ip) {
+		/* clear the lower halfwords */
+		hfb_arp[HFB_ARP_LEN-2] &= ~0xffff;
+		hfb_arp[HFB_ARP_LEN-1] &= ~0xffff;
+		hfb_arp[HFB_ARP_LEN-2] |= (ip >> 16);
+		hfb_arp[HFB_ARP_LEN-1] |= (ip & 0xFFFF);
+		/* Enable HFB, to response to ARP request.*/
+		if (bcmgenet_update_hfb(dev, hfb_arp, HFB_ARP_LEN, 0) < 0) {
+			printk(KERN_ERR "%s: Unable to update HFB\n",
+			       __func__);
+			return -1;
+		}
+		GENET_HFB_CTRL(pDevCtrl) |= RBUF_HFB_EN;
+		return 0;
+	}
+
+	return -1;
+}
+/*
+ * Power down the unimac, based on mode.
+ */
+static void bcmgenet_power_down(struct BcmEnet_devctrl *pDevCtrl, int mode)
+{
+	struct net_device *dev;
+	int retries = 0;
+
+	dev = pDevCtrl->dev;
+	switch (mode) {
+	case GENET_POWER_CABLE_SENSE:
+#if 0
+		/*
+		 * EPHY bug, setting ext_pwr_down_dll and ext_pwr_down_phy cause
+		 * link IRQ bouncing.
+		 */
+		pDevCtrl->ext->ext_pwr_mgmt |= (EXT_PWR_DOWN_PHY |
+				EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
+#else
+		/* Workaround for putting EPHY in iddq mode. */
+		pDevCtrl->mii.mdio_write(dev, pDevCtrl->phyAddr, 0x1f, 0x008b);
+		pDevCtrl->mii.mdio_write(dev, pDevCtrl->phyAddr, 0x10, 0x01c0);
+		pDevCtrl->mii.mdio_write(dev, pDevCtrl->phyAddr, 0x14, 0x7000);
+		pDevCtrl->mii.mdio_write(dev, pDevCtrl->phyAddr, 0x1f, 0x000f);
+		pDevCtrl->mii.mdio_write(dev, pDevCtrl->phyAddr, 0x10, 0x20d0);
+		pDevCtrl->mii.mdio_write(dev, pDevCtrl->phyAddr, 0x1f, 0x000b);
+
+#endif
+		break;
+	case GENET_POWER_WOL_MAGIC:
+		/* disable RX while turning on MPD_EN */
+		pDevCtrl->umac->cmd &= ~CMD_RX_EN;
+		mdelay(10);
+		pDevCtrl->umac->mpd_ctrl |= MPD_EN;
+		while (!(pDevCtrl->rbuf->rbuf_status & RBUF_STATUS_WOL)) {
+			retries++;
+			if (retries > 5) {
+				printk(KERN_CRIT "%s: polling "
+				       "wol mode timeout\n", dev->name);
+				pDevCtrl->umac->mpd_ctrl &= ~MPD_EN;
+				return;
+			}
+			mdelay(1);
+		}
+		printk(KERN_DEBUG "%s: MP WOL-ready status set after "
+		       "%d msec\n", dev->name, retries);
+
+		/* Enable CRC forward */
+		pDevCtrl->umac->cmd |= CMD_CRC_FWD;
+		/* Receiver must be enabled for WOL MP detection */
+		pDevCtrl->umac->cmd |= CMD_RX_EN;
+
+		if (pDevCtrl->ext && pDevCtrl->dev_asleep)
+			pDevCtrl->ext->ext_pwr_mgmt &= ~EXT_ENERGY_DET_MASK;
+
+		pDevCtrl->intrl2_0->cpu_mask_clear |= UMAC_IRQ_MPD_R;
+
+		set_bit(GENET_POWER_WOL_MAGIC, &pDevCtrl->wol_enabled);
+		break;
+	case GENET_POWER_WOL_ACPI:
+		if (bcmgenet_enable_arp_filter(pDevCtrl)) {
+			printk(KERN_CRIT "%s failed to set HFB filter\n",
+			       dev->name);
+			return;
+		}
+		pDevCtrl->umac->cmd &= ~CMD_RX_EN;
+		mdelay(10);
+		GENET_HFB_CTRL(pDevCtrl) |= RBUF_ACPI_EN;
+		while (!(pDevCtrl->rbuf->rbuf_status & RBUF_STATUS_WOL)) {
+			retries++;
+			if (retries > 5) {
+				printk(KERN_CRIT "%s polling "
+				       "wol mode timeout\n", dev->name);
+				GENET_HFB_CTRL(pDevCtrl) &= ~RBUF_ACPI_EN;
+				return;
+			}
+			mdelay(1);
+		}
+		/* Receiver must be enabled for WOL ACPI detection */
+		pDevCtrl->umac->cmd |= CMD_RX_EN;
+		if (pDevCtrl->ext && pDevCtrl->dev_asleep)
+			pDevCtrl->ext->ext_pwr_mgmt &= ~EXT_ENERGY_DET_MASK;
+		printk(KERN_DEBUG "%s: ACPI WOL-ready status set "
+		       "after %d msec\n", dev->name, retries);
+		/* enable HFB match interrupts */
+		pDevCtrl->intrl2_0->cpu_mask_clear |= (UMAC_IRQ_HFB_MM |
+				UMAC_IRQ_HFB_SM);
+		set_bit(GENET_POWER_WOL_ACPI, &pDevCtrl->wol_enabled);
+		break;
+	case GENET_POWER_PASSIVE:
+		/* Power down LED */
+		bcmgenet_mii_reset(pDevCtrl->dev);
+		if (pDevCtrl->ext)
+			pDevCtrl->ext->ext_pwr_mgmt |= (EXT_PWR_DOWN_PHY |
+				EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
+		break;
+	default:
+		break;
+	}
+
+}
+static void bcmgenet_power_up(struct BcmEnet_devctrl *pDevCtrl, int mode)
+{
+	switch (mode) {
+	case GENET_POWER_CABLE_SENSE:
+#if 0
+		pDevCtrl->ext->ext_pwr_mgmt &= ~EXT_PWR_DOWN_DLL;
+		pDevCtrl->ext->ext_pwr_mgmt &= ~EXT_PWR_DOWN_PHY;
+		pDevCtrl->ext->ext_pwr_mgmt &= ~EXT_PWR_DOWN_BIAS;
+#endif
+		/* enable APD */
+		if (pDevCtrl->ext) {
+			pDevCtrl->ext->ext_pwr_mgmt |= EXT_PWR_DN_EN_LD;
+			bcmgenet_mii_reset(pDevCtrl->dev);
+		}
+		break;
+	case GENET_POWER_WOL_MAGIC:
+		pDevCtrl->umac->mpd_ctrl &= ~MPD_EN;
+		/* Disable CRC Forward */
+		pDevCtrl->umac->cmd &= ~CMD_CRC_FWD;
+		/* Stop monitoring magic packet IRQ */
+		pDevCtrl->intrl2_0->cpu_mask_set |= UMAC_IRQ_MPD_R;
+		clear_bit(GENET_POWER_WOL_MAGIC, &pDevCtrl->wol_enabled);
+		break;
+	case GENET_POWER_WOL_ACPI:
+		GENET_HFB_CTRL(pDevCtrl) &= ~RBUF_ACPI_EN;
+		bcmgenet_clear_hfb(pDevCtrl, CLEAR_ALL_HFB);
+		/* Stop monitoring ACPI interrupts */
+		pDevCtrl->intrl2_0->cpu_mask_set |= (UMAC_IRQ_HFB_SM |
+				UMAC_IRQ_HFB_MM);
+		clear_bit(GENET_POWER_WOL_ACPI, &pDevCtrl->wol_enabled);
+		break;
+	case GENET_POWER_PASSIVE:
+		if (pDevCtrl->ext) {
+			pDevCtrl->ext->ext_pwr_mgmt &= ~EXT_PWR_DOWN_DLL;
+			pDevCtrl->ext->ext_pwr_mgmt &= ~EXT_PWR_DOWN_PHY;
+			pDevCtrl->ext->ext_pwr_mgmt &= ~EXT_PWR_DOWN_BIAS;
+			/* enable APD */
+			pDevCtrl->ext->ext_pwr_mgmt |= EXT_PWR_DN_EN_LD;
+			bcmgenet_mii_reset(pDevCtrl->dev);
+		}
+	default:
+		break;
+	}
+	bcmgenet_ephy_workaround(pDevCtrl->dev);
+}
+/*
+ * ioctl handle special commands that are not present in ethtool.
+ */
+static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	unsigned long flags;
+	struct acpi_data *u_data;
+	int val = 0;
+
+	if (!netif_running(dev))
+		return -EINVAL;
+	/* we can add sub-command in ifr_data if we need to in the future */
+	switch (cmd) {
+	case SIOCSACPISET:
+		spin_lock_irqsave(&pDevCtrl->lock, flags);
+		bcmgenet_power_down(pDevCtrl, GENET_POWER_WOL_ACPI);
+		spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+		break;
+	case SIOCSACPICANCEL:
+		spin_lock_irqsave(&pDevCtrl->lock, flags);
+		bcmgenet_power_up(pDevCtrl, GENET_POWER_WOL_ACPI);
+		spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+		break;
+	case SIOCSPATTERN:
+		u_data = (struct acpi_data *)rq->ifr_data;
+		val =  bcmgenet_update_hfb(dev, (unsigned int *)u_data->p_data,
+				u_data->count, 1);
+		if (val >= 0)
+			put_user(val, &u_data->fltr_index);
+		break;
+	case SIOCGPATTERN:
+		u_data = (struct acpi_data *)rq->ifr_data;
+		val = bcmgenet_read_hfb(dev, u_data);
+		break;
+	case SIOCGMIIPHY:
+	case SIOCGMIIREG:
+	case SIOCSMIIREG:
+		val = generic_mii_ioctl(&pDevCtrl->mii, if_mii(rq), cmd, NULL);
+		break;
+	default:
+		val = -EINVAL;
+		break;
+	}
+
+	return val;
+}
+static const struct net_device_ops bcmgenet_netdev_ops = {
+	.ndo_open = bcmgenet_open,
+	.ndo_stop = bcmgenet_close,
+	.ndo_start_xmit = bcmgenet_xmit,
+#ifdef CONFIG_NET_SCH_MULTIQ
+	.ndo_select_queue = bcmgenet_select_queue,
+#endif
+	.ndo_tx_timeout = bcmgenet_timeout,
+	.ndo_set_rx_mode = bcmgenet_set_rx_mode,
+	.ndo_set_mac_address = bcmgenet_set_mac_addr,
+	.ndo_do_ioctl = bcmgenet_ioctl,
+	.ndo_set_features = bcmgenet_set_features,
+};
+
+static int bcmgenet_drv_probe(struct platform_device *pdev)
+{
+	void __iomem *base;
+	int err = -EIO;
+	struct device_node *dn = pdev->dev.of_node;
+	struct BcmEnet_devctrl *pDevCtrl;
+	struct net_device *dev;
+	const void *macaddr;
+
+#ifdef CONFIG_NET_SCH_MULTIQ
+	dev = alloc_etherdev_mq(sizeof(*(pDevCtrl)), GENET_MQ_CNT+1);
+#else
+	dev = alloc_etherdev(sizeof(*pDevCtrl));
+#endif
+	if (dev == NULL) {
+		dev_err(&pdev->dev, "can't allocate net device\n");
+		err = -ENOMEM;
+		goto err0;
+	}
+	pDevCtrl = (struct BcmEnet_devctrl *)netdev_priv(dev);
+	pDevCtrl->irq0 = irq_of_parse_and_map(dn, 0);
+	pDevCtrl->irq1 = irq_of_parse_and_map(dn, 1);
+
+	if (!pDevCtrl->irq0 || !pDevCtrl->irq1) {
+		dev_err(&pdev->dev, "can't find IRQs\n");
+		return -EINVAL;
+	}
+
+	macaddr = of_get_mac_address(dn);
+	if (!macaddr) {
+		dev_err(&pdev->dev, "can't find MAC address\n");
+		return -EINVAL;
+	}
+
+	base = of_iomap(dn, 0);
+	TRACE(("%s: base=0x%x\n", __func__, (unsigned int)base));
+
+	if (!base) {
+		dev_err(&pdev->dev, "can't ioremap\n");
+		return -EINVAL;
+	}
+
+	dev->base_addr = (unsigned long)base;
+	SET_NETDEV_DEV(dev, &pdev->dev);
+	dev_set_drvdata(&pdev->dev, pDevCtrl);
+	memcpy(dev->dev_addr, macaddr, ETH_ALEN);
+	dev->irq = pDevCtrl->irq0;
+	dev->watchdog_timeo         = 2*HZ;
+	SET_ETHTOOL_OPS(dev, &bcmgenet_ethtool_ops);
+	dev->netdev_ops = &bcmgenet_netdev_ops;
+	netif_napi_add(dev, &pDevCtrl->napi, bcmgenet_poll, 64);
+
+	netdev_boot_setup_check(dev);
+
+	pDevCtrl->dev = dev;
+	/* NOTE: with fast-bridge , must turn this off! */
+	pDevCtrl->bIPHdrOptimize = 1;
+
+	spin_lock_init(&pDevCtrl->lock);
+	spin_lock_init(&pDevCtrl->bh_lock);
+	mutex_init(&pDevCtrl->mdio_mutex);
+	/* Mii wait queue */
+	init_waitqueue_head(&pDevCtrl->wq);
+
+	/* TODO: get these from the OF properties */
+	pDevCtrl->phyType = BRCM_PHY_TYPE_INT;
+	pDevCtrl->phySpeed = SPEED_1000;
+	pDevCtrl->extPhy = 0;
+	pDevCtrl->phyAddr = 10;
+	pDevCtrl->devnum = pdev->id;
+
+	pDevCtrl->pdev = pdev;
+
+	/* Init GENET registers, Tx/Rx buffers */
+	if (bcmgenet_init_dev(pDevCtrl) < 0)
+		goto err1;
+
+	bcmgenet_mii_init(dev);
+
+	INIT_WORK(&pDevCtrl->bcmgenet_irq_work, bcmgenet_irq_task);
+
+	err = register_netdev(dev);
+	if (err != 0)
+		goto err2;
+
+	if (pDevCtrl->extPhy) {
+		/* No Link status IRQ */
+		INIT_WORK(&pDevCtrl->bcmgenet_link_work,
+				bcmgenet_gphy_link_status);
+		init_timer(&pDevCtrl->timer);
+		pDevCtrl->timer.data = (unsigned long)pDevCtrl;
+		pDevCtrl->timer.function = bcmgenet_gphy_link_timer;
+	} else {
+		/* check link status */
+		bcmgenet_mii_setup(dev);
+	}
+
+	netif_carrier_off(pDevCtrl->dev);
+	pDevCtrl->next_dev = eth_root_dev;
+	eth_root_dev = dev;
+	bcmgenet_clock_disable(pDevCtrl);
+
+	return 0;
+
+err2:
+	bcmgenet_clock_disable(pDevCtrl);
+	bcmgenet_uninit_dev(pDevCtrl);
+err1:
+	iounmap(base);
+	free_netdev(dev);
+err0:
+	return err;
+}
+
+static int bcmgenet_drv_remove(struct platform_device *pdev)
+{
+	struct BcmEnet_devctrl *pDevCtrl = dev_get_drvdata(&pdev->dev);
+
+	unregister_netdev(pDevCtrl->dev);
+	free_irq(pDevCtrl->irq0, pDevCtrl);
+	free_irq(pDevCtrl->irq1, pDevCtrl);
+	bcmgenet_uninit_dev(pDevCtrl);
+	iounmap((void __iomem *)pDevCtrl->base_addr);
+	free_netdev(pDevCtrl->dev);
+	return 0;
+}
+
+static int bcmgenet_drv_suspend(struct device *dev)
+{
+	int val = 0;
+	struct BcmEnet_devctrl *pDevCtrl = dev_get_drvdata(dev);
+
+	cancel_work_sync(&pDevCtrl->bcmgenet_irq_work);
+
+	/*
+	 * Save/restore the interface status across PM modes.
+	 * FIXME: Don't use open/close for suspend/resume.
+	 */
+	pDevCtrl->dev_opened = netif_running(pDevCtrl->dev);
+	if (pDevCtrl->dev_opened && !pDevCtrl->dev_asleep) {
+		pDevCtrl->dev_asleep = 1;
+		val = bcmgenet_close(pDevCtrl->dev);
+	}
+
+	return val;
+}
+
+static int bcmgenet_drv_resume(struct device *dev)
+{
+	int val = 0;
+	struct BcmEnet_devctrl *pDevCtrl = dev_get_drvdata(dev);
+
+	if (pDevCtrl->dev_opened)
+		val = bcmgenet_open(pDevCtrl->dev);
+	pDevCtrl->dev_asleep = 0;
+
+	return val;
+}
+
+static struct dev_pm_ops bcmgenet_pm_ops = {
+	.suspend		= bcmgenet_drv_suspend,
+	.resume			= bcmgenet_drv_resume,
+};
+
+static const struct of_device_id bcmgenet_match[] = {
+	{ .compatible = "brcm,genet-v3" },
+	{ .compatible = "brcm,genet-v4" },
+	{ },
+};
+
+static struct platform_driver bcmgenet_plat_drv = {
+	.probe =		bcmgenet_drv_probe,
+	.remove =		bcmgenet_drv_remove,
+	.driver = {
+		.name =		"bcmgenet",
+		.owner =	THIS_MODULE,
+		.pm =		&bcmgenet_pm_ops,
+		.of_match_table = bcmgenet_match,
+	},
+};
+
+static int bcmgenet_module_init(void)
+{
+	platform_driver_register(&bcmgenet_plat_drv);
+	return 0;
+}
+
+static void bcmgenet_module_cleanup(void)
+{
+	platform_driver_unregister(&bcmgenet_plat_drv);
+}
+
+module_init(bcmgenet_module_init);
+module_exit(bcmgenet_module_cleanup);
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/ethernet/broadcom/genet-ng/bcmgenet.h b/drivers/net/ethernet/broadcom/genet-ng/bcmgenet.h
new file mode 100644
index 0000000..6619491
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet-ng/bcmgenet.h
@@ -0,0 +1,206 @@
+/*
+ *
+ * Copyright (c) 2002-2008 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *
+*/
+#ifndef __BCMGENET_H__
+#define __BCMGENET_H__
+
+#define CARDNAME				"bcmgenet"
+#define VERSION     "2.0"
+#define VER_STR     "v" VERSION " " __DATE__ " " __TIME__
+
+#define pr_fmt(fmt)				CARDNAME ": " fmt
+
+#include <linux/skbuff.h>
+#include <linux/netdevice.h>
+#include <linux/spinlock.h>
+#include <linux/clk.h>
+#include <linux/mii.h>
+
+#include "bcmgenet_map.h"
+
+/* total number of Buffer Descriptors, same for Rx/Tx */
+#define TOTAL_DESC				256
+/* which ring is descriptor based */
+#define DESC_INDEX				16
+/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528.
+ * 1536 is multiple of 256 bytes
+ */
+#define ENET_MAX_MTU_SIZE       1536
+#define DMA_MAX_BURST_LENGTH    0x10
+
+#define GENET_TX_RING_COUNT		16
+#define GENET_RX_RING_COUNT		16
+#define GENET_ALLOC_TX_RING		1
+#define GENET_ALLOC_RX_RING		0
+
+#define ETH_CRC_LEN             4
+
+/* misc. configuration */
+#define CLEAR_ALL_HFB			0xFF
+#define DMA_FC_THRESH_HI		(TOTAL_DESC >> 4)
+#define DMA_FC_THRESH_LO		5
+
+
+struct Enet_CB {
+	struct sk_buff      *skb;
+	volatile struct DmaDesc    *BdAddr;
+	DEFINE_DMA_UNMAP_ADDR(dma_addr);
+	DEFINE_DMA_UNMAP_LEN(dma_len);
+};
+
+/* power management mode */
+#define GENET_POWER_CABLE_SENSE	0
+#define GENET_POWER_WOL_MAGIC	1
+#define GENET_POWER_WOL_ACPI	2
+#define GENET_POWER_PASSIVE		3
+
+/*
+ * device context
+ */
+struct BcmEnet_devctrl {
+	struct net_device *dev;	/* ptr to net_device */
+	struct net_device *next_dev;
+	spinlock_t      lock;		/* Serializing lock */
+	spinlock_t		bh_lock;	/* soft IRQ lock */
+	struct mii_if_info mii;		/* mii interface info */
+	struct mutex mdio_mutex;	/* mutex for mii_read/write */
+	wait_queue_head_t	wq;		/* mii wait queue */
+	struct timer_list timer;	/* Link status timer */
+
+	struct napi_struct napi;	/* NAPI for descriptor based rx */
+	unsigned long base_addr;	/* GENET register start address. */
+	volatile struct uniMacRegs *umac;	/* UNIMAC register */
+	volatile struct rbufRegs	*rbuf;	/* rbuf registers */
+	volatile struct intrl2Regs *intrl2_0;	/* INTR2_0 registers */
+	volatile struct intrl2Regs *intrl2_1;	/* INTR2_1 registers */
+	volatile struct SysRegs    *sys;	/* sys register */
+	volatile struct GrBridgeRegs *grb;	/* Grb */
+	volatile struct ExtRegs    *ext;	/* Extention register */
+	volatile unsigned long *hfb;/* HFB registers */
+#if CONFIG_BRCM_GENET_VERSION > 1
+	volatile struct tbufRegs *tbuf;	/* tbuf register for GENET2 */
+	volatile struct hfbRegs  *hfbReg;	/* hfb register for GENET2 */
+#endif
+
+	/* transmit variables */
+	volatile struct tDmaRegs *txDma;/* location of tx Dma register */
+	volatile struct DmaDesc *txBds;	/* location of tx Dma BD ring */
+	struct Enet_CB *txCbs;	/* locaation of tx control block pool */
+	int	nrTxBds;		/* number of transmit bds */
+	int	txFreeBds;		/* # of free transmit bds */
+	int	txLastCIndex;	/* consumer index for the last xmit call */
+
+	struct Enet_CB *txRingCBs[16];	/* tx ring buffer control block*/
+	unsigned int txRingSize[16];	/* size of each tx ring */
+	unsigned int txRingCIndex[16];	/* last consumer index of each ring*/
+	int txRingFreeBds[16];	/* # of free bds for each ring */
+	unsigned char *txRingStart[16];	/* tx ring start addr */
+
+	/* receive variables */
+	volatile struct rDmaRegs *rxDma;	/* location of rx dma  */
+	volatile struct DmaDesc *rxBds;		/* location of rx bd ring */
+	volatile struct DmaDesc *rxBdAssignPtr;	/*next rx bd to assign buffer*/
+	struct Enet_CB *rxCbs;	/* location of rx control block pool */
+	int	nrRxBds;	/* number of receive bds */
+	int	rxBufLen;	/* size of rx buffers for DMA */
+
+	struct Enet_CB *rxRingCbs[16];	/* rx ring buffer control */
+	unsigned int rxRingSize[16];	/* size of each ring */
+	unsigned int rxRingCIndex[16];	/* consumer index for each ring */
+	unsigned int rxRingDiscCnt[16];	/* # of discarded pkt for each ring */
+	unsigned char *rxRingStart[16];	/* ring buffer start addr.*/
+
+	/* other misc variables */
+	int irq0;	/* regular IRQ */
+	int	irq1;	/* ring buf IRQ */
+	int phyAddr;
+	int	phyType;
+	int	phySpeed;
+	int	extPhy;
+	int	bIPHdrOptimize;
+	unsigned int irq0_stat;	/* sw copy of irq0 status, for IRQ BH */
+	unsigned int irq1_stat;	/* sw copy of irq1 status, for NAPI rx */
+
+	struct work_struct bcmgenet_irq_work;	/* bottom half work */
+	struct work_struct bcmgenet_link_work;	/* GPHY link status work */
+	int    devnum;		/* 0=EMAC_0, 1=EMAC_1 */
+	struct clk *clk;
+	int dev_opened;		/* device opened. */
+	int dev_asleep;		/* device is at sleep */
+	struct platform_device *pdev;
+
+	/* WOL */
+	unsigned long	wol_enabled;
+	struct	clk *clk_wol;
+	int	clock_active;
+	u32	wolopts;
+
+	/* S3 warm boot */
+	struct DmaDesc saved_rx_desc[TOTAL_DESC];
+	u32 int_mask;
+	u32 rbuf_ctrl;
+};
+
+#if defined(CONFIG_BCMGENET_DUMP_TRACE)
+#define TRACE(x)        (printk x)
+#else
+#define TRACE(x)
+#endif
+
+/* These macros are defined to deal with register map change
+ * between GENET1.1 and GENET2. Only those currently being used
+ * by driver are defined.
+ */
+#if CONFIG_BRCM_GENET_VERSION > 1
+
+#define GENET_TBUF_CTRL(pdev)			(pdev->tbuf->tbuf_ctrl)
+#define GENET_TBUF_BP_MC(pdev)			(pdev->tbuf->tbuf_bp_mc)
+#define GENET_TBUF_ENDIAN_CTRL(pdev)	(pdev->tbuf->tbuf_endian_ctrl)
+#define GENET_TBUF_FLUSH_CTRL(pdev)		(pdev->sys->tbuf_flush_ctrl)
+#define GENET_RBUF_FLUSH_CTRL(pdev)		(pdev->sys->rbuf_flush_ctrl)
+#define GENET_RGMII_OOB_CTRL(pdev)		(pdev->ext->rgmii_oob_ctrl)
+#define GENET_RGMII_IB_STATUS(pdev)		(pdev->ext->rgmii_ib_status)
+#define GENET_RGMII_LED_STATUS(pdev)	(pdev->ext->rgmii_led_ctrl)
+#define GENET_HFB_CTRL(pdev)			(pdev->hfbReg->hfb_ctrl)
+#define GENET_HFB_FLTR_LEN(pdev, i)		(pdev->hfbReg->hfb_fltr_len[i])
+
+#else
+
+#define GENET_TBUF_CTRL(pdev)			(pdev->rbuf->tbuf_ctrl)
+#define GENET_TBUF_BP_MC(pdev)			(pdev->rbuf->tbuf_bp_mc)
+#define GENET_TBUF_ENDIAN_CTRL(pdev)		(pdev->rbuf->tbuf_endian_ctrl)
+#define GENET_TBUF_FLUSH_CTRL(pdev)		(pdev->rbuf->tbuf_flush_ctrl)
+#define GENET_RBUF_FLUSH_CTRL(pdev)		(pdev->rbuf->rbuf_flush_ctrl)
+#define GENET_RGMII_OOB_CTRL(pdev)		(pdev->rbuf->rgmii_oob_ctrl)
+#define GENET_RGMII_IB_STATUS(pdev)		(pdev->rbuf->rgmii_ib_status)
+#define GENET_RGMII_LED_STATUS(pdev)		(pdev->rbuf->rgmii_led_ctrl)
+#define GENET_HFB_CTRL(pdev)			(pdev->rbuf->rbuf_hfb_ctrl)
+#define GENET_HFB_FLTR_LEN(pdev, i)		(pdev->rbuf->rbuf_fltr_len[i])
+
+#endif /* CONFIG_BRCM_GENET_VERSION > 1 */
+
+#if CONFIG_BRCM_GENET_VERSION < 3
+#define GENET_BP_IN_EN_SHIFT			16
+#define GENET_BP_MASK				0xffff
+#else
+#define GENET_BP_IN_EN_SHIFT			17
+#define GENET_BP_MASK				0x1ffff
+#endif
+
+#endif /* __BCMGENET_H__ */
diff --git a/drivers/net/ethernet/broadcom/genet-ng/bcmgenet_defs.h b/drivers/net/ethernet/broadcom/genet-ng/bcmgenet_defs.h
new file mode 100644
index 0000000..6ca2e0f
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet-ng/bcmgenet_defs.h
@@ -0,0 +1,288 @@
+/*
+ * Copyright (c) 2002-2008 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *
+*/
+/* uniMac common macro definations(chip revision independent, idealy!)
+ *
+ * NOTE: the comments "group start" "group end" "non-proc" are for assisting
+ * perl script parsing, DONT'T delete it.
+ *
+ * Revision: 10/03/2008, L.Sun, created.
+ */
+#ifndef __UNIMAC_DEFS_H__
+#define __UNIMAC_DEFS_H__
+
+#include <linux/bitops.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define UMAC_SPEED_10			0
+#define UMAC_SPEED_100			1
+#define UMAC_SPEED_1000			2
+#define UMAC_SPEED_2500			3
+
+#define PORT_MODE_INT_EPHY		0
+#define PORT_MODE_INT_GPHY		1
+#define PORT_MODE_EXT_EPHY		2
+#define PORT_MODE_EXT_GPHY		3
+#define PORT_MODE_EXT_RVMII_25		(4 | BIT(4))
+#define PORT_MODE_EXT_RVMII_50		4
+
+#define LED_ACT_SOURCE_MAC		(1 << 9)
+
+/* umac register group start */
+/* reg: umac->hdBkpCtrl */
+/* Enable half-duplex flow control.*/
+#define	HD_FC_EN				(1 << 0)
+/* Enable back-off algorithm. */
+#define HD_FC_BKOFF_OK			(1 << 1)
+#define IPG_CONFIG_RX_SHIFT		2
+#define IPG_CONFIG_RX_MASK		0x1F
+/* reg: umac->cmd */
+#define CMD_TX_EN				(1 << 0)
+#define CMD_RX_EN				(1 << 1)
+#define CMD_SPEED_SHIFT			2
+#define CMD_SPEED_MASK			3
+#define CMD_PROMISC				(1 << 4)
+#define CMD_PAD_EN				(1 << 5)
+#define CMD_CRC_FWD				(1 << 6)
+#define CMD_PAUSE_FWD			(1 << 7)
+#define CMD_RX_PAUSE_IGNORE		(1 << 8)
+#define CMD_TX_ADDR_INS			(1 << 9)
+#define CMD_HD_EN				(1 << 10)
+#define CMD_SW_RESET			(1 << 13)
+#define CMD_LCL_LOOP_EN			(1 << 15)
+#define CMD_AUTO_CONFIG			(1 << 22)
+#define CMD_CNTL_FRM_EN			(1 << 23)
+#define CMD_NO_LEN_CHK			(1 << 24)
+#define CMD_RMT_LOOP_EN			(1 << 25)
+#define CMD_PRBL_EN				(1 << 27)
+#define CMD_TX_PAUSE_IGNORE		(1 << 28)
+#define CMD_TX_RX_EN			(1 << 29)
+#define CMD_RUNT_FILTER_DIS		(1 << 30)
+/* reg: umac->mode */
+#define MODE_HD					(1 << 0)
+#define MODE_RX_PAUSE_EN		(1 << 3)
+#define MODE_TX_PAUSE_EN		(1 << 4)
+/* reg: umac->macsec_ctrl */
+#define TX_LANUCH_EN			(1 << 0)
+#define TX_CRC_CORRUPT_EN		(1 << 4)
+#define TX_CRC_PROGRAM			(1 << 5)
+#define PAUSE_CTRL_EN			(1 << 17)
+/* reg: umac->ts_status */
+#define TX_TS_FIFO_FULL			(1 << 0)
+#define TX_TS_FIFO_EMPTY		(1 << 1)
+/* reg: umac->txfifo_status */
+#define TX_FIFO_OVERRUN			(1 << 1)
+#define TX_FIFO_UNDERRUN		(1 << 0)
+/* reg: umac->ppp_ctrl */
+#define PPP_EN_TX				(1 << 0)
+#define PPP_EN_RX				(1 << 1)
+#define PPP_FORCE_XON			(1 << 2)
+/* reg: umac_ppp_refresh_ctrl */
+#define PPP_REFRESH_EN			(1 << 0)
+/* reg: umac->mib_ctrl */
+#define MIB_RESET_RX			(1 << 0)
+#define MIB_RESET_RUNT			(1 << 1)
+#define MIB_RESET_TX			(1 << 2)
+/* reg: umac->mpd_ctrl */
+#define MPD_EN					(1 << 0)
+#define MPD_PW_EN				(1 << 27)
+#define MPD_MSEQ_LEN_SHIFT		16
+#define MPD_MSEQ_LEN_MASK		0xFF
+/* reg: umac->mdio_cmd, non-proc export */
+#define MDIO_START_BUSY			(1 << 29)
+#define MDIO_READ_FAIL			(1 << 28)
+#define MDIO_RD					(2 << 26)
+#define MDIO_WR					(1 << 26)
+#define MDIO_PMD_SHIFT			21
+#define MDIO_PMD_MASK			0x1F
+#define MDIO_REG_SHIFT 			16
+#define MDIO_REG_MASK			0x1F
+/* umac register group end */
+
+/* rbuf register group start */
+/* reg: rbuf->rbuf_ctrl */
+#define RBUF_64B_EN				(1 << 0)
+#define RBUF_ALIGN_2B			(1 << 1)
+#define RBUF_BAD_DIS			(1 << 2)
+/* reg: rbuf->rbuf_status */
+#define RBUF_STATUS_WOL			(1 << 0)
+#define RBUF_STATUS_MPD_INTR_ACTIVE		(1 << 1)
+#define RBUF_STATUS_ACPI_INTR_ACTIVE	(1 << 2)
+/* reg: rbuf->rbuf_endian_ctrl */
+#define RBUF_SWAP_EN			(1 << 2)
+#define RBUF_BIG_ENDIAN_MODE	(1 << 0)
+#define RBUF_REG_MODE			(1 << 1)
+/* reg: rbuf->rbuf_chk_ctrl */
+#define RBUF_RXCHK_EN			(1 << 0)
+#define RBUF_SKIP_FCS			(1 << 4)
+/* reg: rbuf->rbuf_hfb_ctrl */
+#define RBUF_HFB_FILTER_EN_SHIFT	16
+#define RBUF_HFB_FILTER_EN_MASK	0xffff0000
+#define RBUF_HFB_EN				(1 << 0)
+#define RBUF_HFB_256B			(1 << 1)
+#define RBUF_ACPI_EN			(1 << 2)
+/* reg: rbuf->rbuf_fltr_len */
+#define RBUF_FLTR_LEN_MASK		0xFF
+#define RBUF_FLTR_LEN_SHIFT		8
+/* reg: rbuf->tbuf_bp_mc */
+#define TBUF_CPU_BP				(1 << 8)
+/* reg: rbuf->rgmii_oob_ctrl */
+#define RGMII_MODE_EN			(1 << 0)
+#define RGMII_LINK				(1 << 4)
+#define OOB_DISABLE				(1 << 5)
+#define ID_MODE_DIS				(1 << 16)
+/* rbuf register group end */
+
+/* ext register group start */
+/* reg: ext->ephy_pwr_mgmt */
+#define EXT_PWR_DOWN_BIAS		(1 << 0)
+#define EXT_PWR_DOWN_DLL		(1 << 1)
+#define EXT_PWR_DOWN_PHY		(1 << 2)
+#define EXT_PWR_DN_EN_LD		(1 << 3)
+#define EXT_ENERGY_DET			(1 << 4)
+#define EXT_IDDQ_FROM_PHY		(1 << 5)
+#define EXT_PHY_RESET			(1 << 8)
+#define EXT_ENERGY_DET_MASK		(1 << 12)
+
+/* reg: ext->emcg_ctrl */
+#define EXT_Ck25_EN				(1 << 0)
+#define EPHY_CLK_SEL			(1 << 4)
+
+/* intrl2_0 register group start */
+/* reg: intrl2_0->cpu_mask_status, others are same */
+#define UMAC_IRQ_SCB			(1 << 0)
+#define UMAC_IRQ_EPHY			(1 << 1)
+#define UMAC_IRQ_PHY_DET_R		(1 << 2)
+#define UMAC_IRQ_PHY_DET_F		(1 << 3)
+#define UMAC_IRQ_LINK_UP		(1 << 4)
+#define UMAC_IRQ_LINK_DOWN		(1 << 5)
+#define UMAC_IRQ_UMAC			(1 << 6)
+#define UMAC_IRQ_UMAC_TSV		(1 << 7)
+#define UMAC_IRQ_TBUF_UNDERRUN	(1 << 8)
+#define UMAC_IRQ_RBUF_OVERFLOW	(1 << 9)
+#define UMAC_IRQ_HFB_SM			(1 << 10)
+#define UMAC_IRQ_HFB_MM			(1 << 11)
+#define UMAC_IRQ_MPD_R			(1 << 12)
+#define UMAC_IRQ_RXDMA_MBDONE	(1 << 13)
+#define UMAC_IRQ_RXDMA_PDONE	(1 << 14)
+#define UMAC_IRQ_RXDMA_BDONE	(1 << 15)
+#define UMAC_IRQ_TXDMA_MBDONE	(1 << 16)
+#define UMAC_IRQ_TXDMA_PDONE	(1 << 17)
+#define UMAC_IRQ_TXDMA_BDONE	(1 << 18)
+
+#define DMA_RW_POINTER_MASK		0x1FF
+/* reg: rDmaRingRegs->rdma_producer_index */
+#define DMA_P_INDEX_DISCARD_CNT_MASK		0xFFFF
+#define DMA_P_INDEX_DISCARD_CNT_SHIFT		16
+#define DMA_BUFFER_DONE_CNT_MASK			0xFFFF
+#define DMA_BUFFER_DONE_CNT_SHIFT			16
+#define DMA_P_INDEX_MASK					0xFFFF
+#define DMA_C_INDEX_MASK					0xFFFF
+/* reg: rDmaRingRegs->rdma_ring_buf_size */
+#define DMA_RING_SIZE_MASK					0xFFFF
+#define DMA_RING_SIZE_SHIFT					16
+#define DMA_RING_BUFFER_SIZE_MASK			0xFFFF
+/* reg: rDmaRingRegs->rdma_mbuf_done_threshold */
+#define DMA_INTR_THRESHOLD_MASK				0x00FF
+/* reg: rDmaRingRegs->rdma_xon_xoff_threshold */
+#define DMA_XON_THREHOLD_MASK				0xFFFF
+#define DMA_XOFF_THRESHOLD_MASK				0xFFFF
+#define DMA_XOFF_THRESHOLD_SHIFT			16
+/* reg: dDmaRingRegs->tdma_flow_period */
+#define DMA_FLOW_PERIOD_MASK				0xFFFF
+#define DMA_MAX_PKT_SIZE_MASK				0xFFFF
+#define DMA_MAX_PKT_SIZE_SHIFT				16
+
+/* rdma register group start */
+/* reg: rDmaRegs->rdma_ctrl */
+#define DMA_EN								(1 << 0)
+#define DMA_RING_BUF_EN_SHIFT				0x01
+#define DMA_RING_BUF_EN_MASK				0xFFFF
+#define DMA_TSB_SWAP_EN						(1 << 20)
+/* reg : rDmaRegs->rdma_status */
+#define DMA_DISABLED						(1 << 0)
+#define DMA_DESC_RAM_INIT_BUSY				(1 << 1)
+/* reg: rDmaRegs->rdma_scb_burst_size */
+#define DMA_SCB_BURST_SIZE_MASK				0x1F
+/* reg: rDmaRegs->rdma_activity */
+#define DMA_ACTIVITY_VECTOR_MASK			0x1FFFF
+/* reg: rDmaRegs->rdma_mask */
+#define DMA_BACKPRESSURE_MASK				0x1FFFF
+#define DMA_PFC_ENABLE						(1 << 31)
+/* reg: rDmaRegs->rdma_map non-proc export*/
+#define DMA_MAP_MASK						0x0F
+#define DMA_MAP_SHIFT						4
+/* reg: rDmaRegs->rdma_back_status */
+#define DMA_BACKPRESSURE_STATUS_MASK		0x1FFFF
+/* reg: rDmaRegs->rdma_override */
+#define DMA_LITTLE_ENDIAN_MODE				(1 << 0)
+#define DMA_REGISTER_MODE					(1 << 1)
+/* reg: rDmaRegs->rdma_timeout non-proc export */
+#define DMA_TIMEOUT_MASK					0xFFFF
+
+#define DMA_RATE_LIMIT_EN_MASK				0xFFFF
+#define DMA_ARBITER_MODE_MASK				0x03
+#define DMA_RING_BUF_PRIORITY_MASK			0x1F
+#define DMA_RING_BUF_PRIORITY_SHIFT			5
+#define DMA_RATE_ADJ_MASK					0xFF
+
+/*-------------------Dma Descriptor defines ---------------------------------*/
+/* reg : none , non-proc export (not for registers ) */
+/* Tx/Rx Dma Descriptor common bits*/
+#define DMA_BUFLENGTH_MASK		0x0fff
+#define DMA_BUFLENGTH_SHIFT		16
+#define DMA_OWN					0x8000
+#define DMA_EOP					0x4000
+#define DMA_SOP					0x2000
+#define DMA_WRAP				0x1000
+/* Tx specific Dma descriptor bits */
+#define DMA_TX_UNDERRUN			0x0200
+#define DMA_TX_APPEND_CRC		0x0040
+#define DMA_TX_OW_CRC			0x0020
+#define DMA_TX_DO_CSUM			0x0010
+#if CONFIG_BRCM_GENET_VERSION < 3
+#define DMA_TX_QTAG_MASK		0x001F
+#else /* GENET_V3+: 6-bit QTAG */
+#define DMA_TX_QTAG_MASK		0x003F
+#endif
+#define DMA_TX_QTAG_SHIFT		7
+
+/* Rx Specific Dma descriptor bits */
+#define DMA_RX_BRDCAST			0x0040
+#define DMA_RX_MULT				0x0020
+#define DMA_RX_LG				0x0010
+#define DMA_RX_NO				0x0008
+#define DMA_RX_RXER				0x0004
+#define DMA_RX_CRC_ERROR		0x0002
+#define DMA_RX_OV				0x0001
+#define DMA_RX_FI_MASK			0x001F
+#define DMA_RX_FI_SHIFT			0x0007
+#define DMA_DESC_ALLOC_MASK		0x00FF
+
+#define DMA_ARBITER_RR			0x00
+#define DMA_ARBITER_WRR			0x01
+#define DMA_ARBITER_SP			0x02
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __UNIMAC_DEFS_H__ */
diff --git a/drivers/net/ethernet/broadcom/genet-ng/bcmgenet_map.h b/drivers/net/ethernet/broadcom/genet-ng/bcmgenet_map.h
new file mode 100644
index 0000000..720f87f
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet-ng/bcmgenet_map.h
@@ -0,0 +1,531 @@
+/*
+ * Copyright (c) 2002-2008 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *
+*/
+/* uniMAC register definations.*/
+
+#ifndef __BCMGENET_MAP_H__
+#define __BCMGENET_MAP_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/types.h>
+#include "bcmgenet_defs.h"
+
+#ifndef __ASSEMBLY__
+
+/* 64B status Block */
+struct status_64 {
+	u32	length_status;		/* length and peripheral status */
+	u32	ext_status;		/* Extended status*/
+	u32	rx_csum;		/* partial rx checksum */
+#if CONFIG_BRCM_GENET_VERSION < 3
+	u32	filter_index;		/* Filter index */
+	u32	extracted_bytes[4];	/* Extracted byte 0 - 16 */
+	u32	reserved[4];
+#else /* GENET_V3+ */
+	u32	filter_index[2];	/* Filter index */
+	u32	extracted_bytes[4];	/* Extracted byte 0 - 16 */
+	u32	reserved[3];
+#endif
+	u32	tx_csum_info;		/* Tx checksum info. */
+	u32	unused[3];		/* unused */
+} ;
+/* Rx status bits */
+#define STATUS_RX_EXT_MASK		0x1FFFFF
+#define STATUS_RX_CSUM_MASK		0xFFFF
+#define STATUS_RX_CSUM_OK		0x10000
+#define STATUS_RX_CSUM_FR		0x20000
+#define STATUS_RX_PROTO_TCP		0
+#define STATUS_RX_PROTO_UDP		1
+#define STATUS_RX_PROTO_ICMP	2
+#define STATUS_RX_PROTO_OTHER	3
+#define STATUS_RX_PROTO_MASK	3
+#define STATUS_RX_PROTO_SHIFT	18
+#define STATUS_FILTER_INDEX_MASK	0xFFFF
+/* Tx status bits */
+#define STATUS_TX_CSUM_START_MASK	0X7FFF
+#define STATUS_TX_CSUM_START_SHIFT	16
+#define STATUS_TX_CSUM_PROTO_UDP	0x8000
+#define STATUS_TX_CSUM_OFFSET_MASK	0x7FFF
+#define STATUS_TX_CSUM_LV			0x80000000
+
+/*
+** DMA Descriptor
+*/
+struct DmaDesc {
+	u32	length_status;	/* in bytes of data in buffer */
+	u32	address_lo;	/* lower 32 bits of PA */
+#if CONFIG_BRCM_GENET_VERSION >= 4
+	u32	address_hi;	/* upper 32 bits of PA */
+#endif
+};
+
+#define WORDS_PER_BD			(sizeof(struct DmaDesc) / sizeof(u32))
+
+static inline void dmadesc_set_addr(volatile struct DmaDesc *d, dma_addr_t addr)
+{
+	d->address_lo = addr & 0xffffffff;
+#if CONFIG_BRCM_GENET_VERSION >= 4
+	d->address_hi = (u64)addr >> 32;
+#endif
+}
+
+static inline dma_addr_t dmadesc_get_addr(const volatile struct DmaDesc *d)
+{
+	dma_addr_t addr;
+
+	addr = d->address_lo;
+#if CONFIG_BRCM_GENET_VERSION >= 4
+	addr |= (u64)d->address_hi << 32;
+#endif
+	return addr;
+}
+
+/*
+** UniMAC TSV or RSV (Transmit Status Vector or Receive Status Vector
+*/
+/* Rx/Tx common counter group.*/
+struct PktCounterSize {
+	u32	cnt_64;		/* RO Recvied/Transmited 64 bytes packet */
+	u32	cnt_127;	/* RO Rx/Tx 127 bytes packet */
+	u32	cnt_255;	/* RO Rx/Tx 65-255 bytes packet */
+	u32	cnt_511;	/* RO Rx/Tx 256-511 bytes packet */
+	u32	cnt_1023;	/* RO Rx/Tx 512-1023 bytes packet */
+	u32	cnt_1518;	/* RO Rx/Tx 1024-1518 bytes packet */
+	u32	cnt_mgv;	/* RO Rx/Tx 1519-1522 good VLAN packet */
+	u32	cnt_2047;	/* RO Rx/Tx 1522-2047 bytes packet*/
+	u32	cnt_4095;	/* RO Rx/Tx 2048-4095 bytes packet*/
+	u32	cnt_9216;	/* RO Rx/Tx 4096-9216 bytes packet*/
+};
+/* RSV, Receive Status Vector */
+struct UniMacRSV {
+	struct PktCounterSize stat_sz;	/* (0x400 - 0x424), stats of received
+			packets classfied by size */
+	u32	rx_pkt;		/* RO (0x428) Receive pkt count*/
+	u32	rx_bytes;	/* RO Receive byte count */
+	u32	rx_mca;		/* RO # of Received multicast pkt */
+	u32	rx_bca;		/* RO # of Receive broadcast pkt */
+	u32	rx_fcs;		/* RO # of Received FCS error  */
+	u32	rx_cf;		/* RO # of Received control frame pkt*/
+	u32	rx_pf;		/* RO # of Received pause frame pkt */
+	u32	rx_uo;		/* RO # of unknown op code pkt */
+	u32	rx_aln;		/* RO # of alignment error count */
+	u32	rx_flr;		/* RO # of frame length out of range count */
+	u32	rx_cde;		/* RO # of code error pkt */
+	u32	rx_fcr;		/* RO # of carrier sense error pkt */
+	u32	rx_ovr;		/* RO # of oversize pkt*/
+	u32	rx_jbr;		/* RO # of jabber count */
+	u32	rx_mtue;	/* RO # of MTU error pkt*/
+	u32	rx_pok;		/* RO # of Received good pkt */
+	u32	rx_uc;		/* RO # of unicast pkt */
+	u32	rx_ppp;		/* RO # of PPP pkt */
+	u32	rcrc;		/* RO (0x470),# of CRC match pkt */
+};
+
+/* TSV, Transmit Status Vector */
+struct UniMacTSV {
+	struct PktCounterSize stat_sz;	/* (0x480 - 0x0x4a4), statistics of
+			xmited packets classified by size */
+	u32	tx_pkt;		/* RO (0x4a8) Transmited pkt */
+	u32	tx_mca;		/* RO # of xmited multicast pkt */
+	u32	tx_bca;		/* RO # of xmited broadcast pkt */
+	u32	tx_pf;		/* RO # of xmited pause frame count */
+	u32	tx_cf;		/* RO # of xmited control frame count */
+	u32	tx_fcs;		/* RO # of xmited FCS error count */
+	u32	tx_ovr;		/* RO # of xmited oversize pkt */
+	u32	tx_drf;		/* RO # of xmited deferral pkt */
+	u32	tx_edf;		/* RO # of xmited Excessive deferral pkt*/
+	u32	tx_scl;		/* RO # of xmited single collision pkt */
+	u32	tx_mcl;		/* RO # of xmited multiple collision pkt*/
+	u32	tx_lcl;		/* RO # of xmited late collision pkt */
+	u32	tx_ecl;		/* RO # of xmited excessive collision pkt*/
+	u32	tx_frg;		/* RO # of xmited fragments pkt*/
+	u32	tx_ncl;		/* RO # of xmited total collision count */
+	u32	tx_jbr;		/* RO # of xmited jabber count*/
+	u32	tx_bytes;	/* RO # of xmited byte count */
+	u32	tx_pok;		/* RO # of xmited good pkt */
+	u32	tx_uc;		/* RO (0x0x4f0)# of xmited unitcast pkt */
+};
+
+struct uniMacRegs {
+	u32	unused;			/* (00) RO */
+	u32	hdBkpCtrl;		/* (04) RW */
+	u32	cmd;			/* (08) RW */
+	u32	mac_0;			/* (0x0c) RW */
+	u32	mac_1;			/* (0x10) RW */
+	u32	max_frame_len;		/* (0x14) RW */
+	u32	pause_quant;		/* (0x18) RW */
+	u32	unused0[9];		/* (0x1c - 0x3c) */
+	u32	sdf_offset;		/* (0x40) RW */
+	u32	mode;			/* (0x44) RO */
+	u32	frm_tag0;		/* (0x48) RW */
+	u32	frm_tag1;		/* (0x4c) RW */
+	u32	unused1[3];		/* (0x50 - 0x58) */
+	u32	tx_ipg_len;		/* (0x5c) RW */
+	u32	unused2;		/* (0x60) */
+	u32	eee_ctrl;		/* (0x64) RW */
+	u32	eee_lpi_timer;		/* (0x68) RW */
+	u32	eee_wake_timer;		/* (0x6c) RW */
+	u32	eee_ref_count;		/* (0x70) RWS */
+	u32	unused3;		/* (0x74) */
+	u32	rx_pkt_drop_status;	/* (0x78) RW */
+	u32	symmetric_idle_thld;	/* (0x7c) RW */
+	u32	unused4[164];		/* (0x80 - 0x30c) */
+	u32	macsec_tx_crc;		/* (0x310) RW */
+	u32	macsec_ctrl;		/* (0x314) RW */
+	u32	ts_status;		/* (0x318) RO */
+	u32	ts_data;		/* (0x31c) RO */
+	u32	unused5[4];		/* (0x320 - 0x32c) */
+	u32	pause_ctrl;		/* (0x330) RW */
+	u32	tx_flush;		/* (0x334) RW */
+	u32	rxfifo_status;		/* (0x338) RO */
+	u32	txfifo_status;		/* (0x33c) RO */
+	u32	ppp_ctrl;		/* (0x340) RW */
+	u32	ppp_refresh_ctrl;	/* (0x344) RW */
+	u32	unused6[4];		/* (0x348 - 0x354) */
+	u32	unused7[4];		/* (0x358 - 0x364) */
+	u32	unused8[38];		/* (0x368 - 0x3fc) */
+	struct UniMacRSV rsv;		/* (0x400 - 0x470) */
+	u32	unused9[3];		/* (0x474 - 0x47c) */
+	struct UniMacTSV tsv;		/* (0x480 - 0x4f0) */
+	u32	unused10[7];		/* (0x4f4 - 0x50c) */
+	u32	unused11[28];		/* (0x510 - 0x57c) */
+	u32	mib_ctrl;		/* (0x580) RW */
+	u32	unused12[31];		/* (0x584 - 0x5fc) */
+	u32	bkpu_ctrl;		/* (0x600) RW */
+	u32	mac_rxerr_mask;		/* (0x604) RW  */
+	u32	max_pkt_size;		/* (0x608) RW */
+	u32	vlan_tag;		/* (0x60c) RW */
+	u32	unused13;		/* (0x610) */
+	u32	mdio_cmd;		/* (0x614  RO */
+	u32	mdio_cfg;		/* (0x618) RW */
+#if CONFIG_BRCM_GENET_VERSION > 1
+	u32	unused14;		/* (0x61c) */
+#else
+	u32	rbuf_ovfl_pkt_cnt;	/* (0x61c) RO */
+#endif
+	u32	mpd_ctrl;		/* (0x620) RW */
+	u32	mpd_pw_ms;		/* (0x624) RW */
+	u32	mpd_pw_ls;		/* (0x628) RW */
+	u32	unused15[3];		/* (0x62c - 0x634) */
+	u32	mdf_cnt;		/* (0x638) RO */
+	u32	unused16[4];		/* (0x63c - 0x648) */
+	u32	diag_sel;		/* (0x64c) RW */
+	u32	mdf_ctrl;		/* (0x650) RW */
+	u32	mdf_addr[34];		/* (0x654 - 0x6d8) */
+};
+
+#if CONFIG_BRCM_GENET_VERSION < 3
+#define HFB_NUM_FLTRS		16
+#else
+#define HFB_NUM_FLTRS		48
+#endif
+
+#if CONFIG_BRCM_GENET_VERSION > 1
+struct tbufRegs {
+	u32	tbuf_ctrl;		/* (0x00) */
+	u32	unused0;		/* (0x04) */
+	u32	tbuf_endian_ctrl;	/* (0x08) */
+	u32	tbuf_bp_mc;		/* (0x0c) */
+	u32	tbuf_pkt_rdy_thld;	/* (0x10) */
+	u32	tbuf_energy_ctrl;	/* (0x14) */
+	u32	tbuf_ext_bp_stats;	/* (0x18) */
+	u32	tbuf_tsv_mask0;		/* (0x1c) */
+	u32	tbuf_tsv_mask1;		/* (0x20) */
+	u32	tbuf_tsv_status0;	/* (0x24) */
+	u32	tbuf_tsv_status1;	/* (0x28) */
+};
+
+struct rbufRegs {
+	u32	rbuf_ctrl;		/* (0x00) */
+	u32	unused0;		/* (0x04) */
+	u32	rbuf_pkt_rdy_thld;	/* (0x08) */
+	u32	rbuf_status;		/* (0x0c) */
+	u32	rbuf_endian_ctrl;	/* (0x10) */
+	u32	rbuf_chk_ctrl;		/* (0x14) */
+#if CONFIG_BRCM_GENET_VERSION == 2
+	u32	rbuf_rxc_offset[8];	/* (0x18 - 0x34) */
+	u32	unused1[18];
+	u32	rbuf_ovfl_pkt_cnt;	/* (0x80) */
+	u32	rbuf_err_cnt;		/* (0x84) */
+	u32	rbuf_energy_ctrl;	/* (0x88) */
+
+	u32	unused2[7];
+	u32	rbuf_pd_sram_ctrl;	/* (0xa8) */
+	u32	unused3[12];
+	u32	rbuf_test_mux_ctrl;	/* (0xdc) */
+#else /* GENET_V3+ */
+	u32	unused1[7];		/* (0x18 - 0x34) */
+	u32	rbuf_rxc_offset[24];	/* (0x34 - 0x90) */
+	u32	rbuf_ovfl_pkt_cnt;	/* (0x94) */
+	u32	rbuf_err_cnt;		/* (0x98) */
+	u32	rbuf_energy_ctrl;	/* (0x9c) */
+	u32	rbuf_pd_sram_ctrl;	/* (0xa0) */
+	u32	rbuf_test_mux_ctrl;	/* (0xa4) */
+	u32	rbuf_spare_reg0;	/* (0xa8) */
+	u32	rbuf_spare_reg1;	/* (0xac) */
+	u32	rbuf_spare_reg2;	/* (0xb0) */
+	u32	rbuf_tbuf_size_ctrl;	/* (0xb4) */
+#endif
+};
+
+struct hfbRegs {
+	u32	hfb_ctrl;
+#if CONFIG_BRCM_GENET_VERSION > 2
+	u32	hfb_flt_enable[2];
+	u32	unused[4];
+#endif
+	u32	hfb_fltr_len[HFB_NUM_FLTRS / 4];
+};
+
+#else /* CONFIG_BRCM_GENET_VERSION > 1 */
+struct rbufRegs {
+	u32	rbuf_ctrl;		/* (0x00) */
+	u32	rbuf_flush_ctrl;	/* (0x04) */
+	u32	rbuf_pkt_rdy_thld;	/* (0x08) */
+	u32	rbuf_status;		/* (0x0c) */
+	u32	rbuf_endian_ctrl;	/* (0x10) */
+	u32	rbuf_chk_ctrl;		/* (0x14) */
+	u32	rbuf_rxc_offset[8];	/* (0x18 - 0x34) */
+	u32	rbuf_hfb_ctrl;		/* (0x38) */
+	u32	rbuf_fltr_len[HFB_NUM_FLTRS / 4]; /* (0x3c - 0x48) */
+	u32	unused0[13];		/* (0x4c - 0x7c) */
+	u32	tbuf_ctrl;		/* (0x80) */
+	u32	tbuf_flush_ctrl;	/* (0x84) */
+	u32	unused1[5];		/* (0x88 - 0x98) */
+	u32	tbuf_endian_ctrl;	/* (0x9c) */
+	u32	tbuf_bp_mc;		/* (0xa0) */
+	u32	tbuf_pkt_rdy_thld;	/* (0xa4) */
+	u32	unused2[2];		/* (0xa8 - 0xac) */
+	u32	rgmii_oob_ctrl;		/* (0xb0) */
+	u32	rgmii_ib_status;	/* (0xb4) */
+	u32	rgmii_led_ctrl;		/* (0xb8) */
+	u32	unused3;		/* (0xbc) */
+	u32	moca_status;		/* (0xc0) */
+	u32	unused4[6];		/* (0xc4 - 0xd8) */
+	u32	test_mux_ctrl;		/* (0xdc) */
+};
+#endif
+/* uniMac intrl2 registers */
+struct intrl2Regs {
+	u32	cpu_stat;		/* (0x00) */
+	u32	cpu_set;		/* (0x04) */
+	u32	cpu_clear;		/* (0x08) */
+	u32	cpu_mask_status;	/* (0x0c) */
+	u32	cpu_mask_set;		/* (0x10) */
+	u32	cpu_mask_clear;		/* (0x14) */
+	u32	pci_stat;		/* (0x00) */
+	u32	pci_set;		/* (0x04) */
+	u32	pci_clear;		/* (0x08) */
+	u32	pci_mask_status;	/* (0x0c) */
+	u32	pci_mask_set;		/* (0x10) */
+	u32	pci_mask_clear;		/* (0x14) */
+};
+
+/* Register block offset */
+#define GENET_GR_BRIDGE_OFF			0x0040
+#define GENET_EXT_OFF				0x0080
+#define GENET_INTRL2_0_OFF			0x0200
+#define GENET_INTRL2_1_OFF			0x0240
+#define GENET_RBUF_OFF				0X0300
+#define GENET_UMAC_OFF				0x0800
+
+#if CONFIG_BRCM_GENET_VERSION == 1
+#define GENET_HFB_OFF				0x1000
+#define GENET_RDMA_OFF				0x2000
+#define GENET_TDMA_OFF				0x3000
+#elif CONFIG_BRCM_GENET_VERSION == 2
+#define GENET_TBUF_OFF				0x0600
+#define GENET_HFB_OFF				0x1000
+#define GENET_HFB_REG_OFF			0x2000
+#define GENET_RDMA_OFF				0x3000
+#define GENET_TDMA_OFF				0x4000
+#elif CONFIG_BRCM_GENET_VERSION == 3
+#define GENET_TBUF_OFF				0x0600
+#define GENET_HFB_OFF				0x8000
+#define GENET_HFB_REG_OFF			0xfc00
+#define GENET_RDMA_OFF				0x10000
+#define GENET_TDMA_OFF				0x11000
+#elif CONFIG_BRCM_GENET_VERSION == 4
+#define GENET_TBUF_OFF				0x0600
+#define GENET_HFB_OFF				0x8000
+#define GENET_HFB_REG_OFF			0xfc00
+#define GENET_RDMA_OFF				0x2000
+#define GENET_TDMA_OFF				0x4000
+#endif
+
+struct SysRegs {
+	u32	sys_rev_ctrl;
+	u32	sys_port_ctrl;
+#if CONFIG_BRCM_GENET_VERSION > 1
+	u32	rbuf_flush_ctrl;
+	u32	tbuf_flush_ctrl;
+#endif
+};
+
+struct GrBridgeRegs {
+	u32	gr_bridge_rev;
+	u32	gr_bridge_ctrl;
+	u32	gr_bridge_sw_reset_0;
+	u32	gr_bridge_sw_reset_1;
+};
+
+struct ExtRegs {
+	u32	ext_pwr_mgmt;
+	u32	ext_emcg_ctrl;
+	u32	ext_test_ctrl;
+#if CONFIG_BRCM_GENET_VERSION > 1
+	u32	rgmii_oob_ctrl;
+	u32	rgmii_ib_status;
+	u32	rgmii_led_ctrl;
+	u32	ext_genet_pwr_mgmt;
+#if CONFIG_BRCM_GENET_VERSION > 3
+	u32	ext_gphy_ctrl;
+	u32	ext_gphy_status;
+#endif
+#else
+	u32	ext_in_ctrl;
+	u32	ext_fblp_ctrl;
+	u32	ext_stat0;
+	u32	ext_stat1;
+	u32	ext_ch_ctrl[6];
+#endif
+};
+
+struct rDmaRingRegs {
+	u32	rdma_write_pointer;
+#if CONFIG_BRCM_GENET_VERSION > 3
+	u32	rdma_write_pointer_hi;
+#endif
+	u32	rdma_producer_index;
+	u32	rdma_consumer_index;
+	u32	rdma_ring_buf_size;
+	u32	rdma_start_addr;
+#if CONFIG_BRCM_GENET_VERSION > 3
+	u32	rdma_start_addr_hi;
+#endif
+	u32	rdma_end_addr;
+#if CONFIG_BRCM_GENET_VERSION > 3
+	u32	rdma_end_addr_hi;
+#endif
+	u32	rdma_mbuf_done_threshold;
+	u32	rdma_xon_xoff_threshold;
+	u32	rdma_read_pointer;	/* NOTE: not used by hardware */
+#if CONFIG_BRCM_GENET_VERSION > 3
+	u32	rdma_read_pointer_hi;
+	u32	unused[3];
+#else
+	u32	unused[7];
+#endif
+};
+
+struct tDmaRingRegs {
+	u32	tdma_read_pointer;
+#if CONFIG_BRCM_GENET_VERSION > 3
+	u32	tdma_read_pointer_hi;
+#endif
+	u32	tdma_consumer_index;
+	u32	tdma_producer_index;
+	u32	tdma_ring_buf_size;
+	u32	tdma_start_addr;
+#if CONFIG_BRCM_GENET_VERSION > 3
+	u32	tdma_start_addr_hi;
+#endif
+	u32	tdma_end_addr;
+#if CONFIG_BRCM_GENET_VERSION > 3
+	u32	tdma_end_addr_hi;
+#endif
+	u32	tdma_mbuf_done_threshold;
+	u32	tdma_flow_period;
+	u32	tdma_write_pointer;	/* NOTE: not used by hardware */
+#if CONFIG_BRCM_GENET_VERSION > 3
+	u32	tdma_write_pointer_hi;
+	u32	unused[3];
+#else
+	u32	unused[7];
+#endif
+};
+
+struct rDmaRegs {
+	struct rDmaRingRegs rDmaRings[17];
+#if CONFIG_BRCM_GENET_VERSION > 1
+	u32	rdma_ring_cfg;
+#endif
+	u32	rdma_ctrl;
+	u32	rdma_status;
+#if CONFIG_BRCM_GENET_VERSION < 2
+	u32	unused;
+#endif
+	u32	rdma_scb_burst_size;
+	u32	rdma_activity;
+	u32	rdma_mask;
+	u32	rdma_map[3];
+	u32	rdma_back_status;
+	u32	rdma_override;
+	u32	rdma_timeout[17];
+#if CONFIG_BRCM_GENET_VERSION > 2
+	u32	rdma_index2ring[8];
+#endif
+	u32	rdma_test;
+	u32	rdma_debug;
+};
+
+struct tDmaRegs {
+	struct tDmaRingRegs tDmaRings[17];
+#if CONFIG_BRCM_GENET_VERSION > 1
+	u32	tdma_ring_cfg;
+#endif
+	u32	tdma_ctrl;
+	u32	tdma_status;
+#if CONFIG_BRCM_GENET_VERSION == 1
+	u32	unused;
+#endif
+	u32	tdma_scb_burst_size;
+	u32	tdma_activity;
+	u32	tdma_mask;
+#if CONFIG_BRCM_GENET_VERSION > 2
+	u32	tdma_map[2];
+#else
+	u32	tdma_map[3];
+#endif
+	u32	tdma_back_status;
+	u32	tdma_override;
+	u32	tdma_rate_limit_ctrl;
+	u32	tdma_arb_ctrl;
+	u32	tdma_priority[3];
+#if CONFIG_BRCM_GENET_VERSION > 2
+	u32	tdma_rate_adj;
+	u32	tdma_test;
+	u32	tdma_debug;
+#else
+	u32	tdma_test;
+	u32	tdma_debug;
+	u32	tdma_rate_adj;
+#endif
+};
+
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/drivers/net/ethernet/broadcom/genet-ng/bcmmii.c b/drivers/net/ethernet/broadcom/genet-ng/bcmmii.c
new file mode 100644
index 0000000..43eb49a
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet-ng/bcmmii.c
@@ -0,0 +1,350 @@
+/*
+ *
+ * Copyright (c) 2002-2005 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *
+ *File Name  : bcmmii.c
+ *
+ *Description: Broadcom PHY/GPHY/Ethernet Switch Configuration
+ *Revision:	09/25/2008, L.Sun created.
+*/
+
+#include "bcmgenet.h"
+#include "bcmgenet_map.h"
+#include "bcmmii.h"
+
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/wait.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/bitops.h>
+#include <linux/netdevice.h>
+#include <linux/platform_device.h>
+#include <linux/brcmstb/brcmstb.h>
+
+/* read a value from the MII */
+int bcmgenet_mii_read(struct net_device *dev, int phy_id, int location)
+{
+	int ret;
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	volatile struct uniMacRegs *umac = pDevCtrl->umac;
+
+	if (phy_id == BRCM_PHY_ID_NONE) {
+		switch (location) {
+		case MII_BMCR:
+			return (pDevCtrl->phySpeed == SPEED_1000) ?
+				BMCR_FULLDPLX | BMCR_SPEED1000 :
+				BMCR_FULLDPLX | BMCR_SPEED100;
+		case MII_BMSR:
+			return BMSR_LSTATUS;
+		default:
+			return 0;
+		}
+	}
+
+	mutex_lock(&pDevCtrl->mdio_mutex);
+
+	umac->mdio_cmd = (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) |
+			(location << MDIO_REG_SHIFT));
+	/* Start MDIO transaction*/
+	umac->mdio_cmd |= MDIO_START_BUSY;
+	wait_event_timeout(pDevCtrl->wq, !(umac->mdio_cmd & MDIO_START_BUSY),
+			HZ/100);
+	ret = umac->mdio_cmd;
+	mutex_unlock(&pDevCtrl->mdio_mutex);
+	if (ret & MDIO_READ_FAIL) {
+		TRACE(("MDIO read failure\n"));
+		ret = 0;
+	}
+	return ret & 0xffff;
+}
+
+/* write a value to the MII */
+void bcmgenet_mii_write(struct net_device *dev, int phy_id,
+			int location, int val)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	volatile struct uniMacRegs *umac = pDevCtrl->umac;
+
+	if (phy_id == BRCM_PHY_ID_NONE)
+		return;
+	mutex_lock(&pDevCtrl->mdio_mutex);
+	umac->mdio_cmd = (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
+			(location << MDIO_REG_SHIFT) | (0xffff & val));
+	umac->mdio_cmd |= MDIO_START_BUSY;
+	wait_event_timeout(pDevCtrl->wq, !(umac->mdio_cmd & MDIO_START_BUSY),
+			HZ/100);
+	mutex_unlock(&pDevCtrl->mdio_mutex);
+}
+
+/* mii register read/modify/write helper function */
+static int bcmgenet_mii_set_clr_bits(struct net_device *dev, int location,
+		     int set_mask, int clr_mask)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	int phy_id = pDevCtrl->phyAddr;
+	int v;
+
+	v = bcmgenet_mii_read(dev, phy_id, location);
+	v &= ~clr_mask;
+	v |= set_mask;
+	bcmgenet_mii_write(dev, phy_id, location, v);
+	return v;
+}
+
+/* probe for an external PHY via MDIO; return PHY address */
+int bcmgenet_mii_probe(struct net_device *dev, void *p)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	int i;
+	struct bcmemac_platform_data *cfg = p;
+
+	if (cfg->phy_type != BRCM_PHY_TYPE_EXT_MII &&
+	    cfg->phy_type != BRCM_PHY_TYPE_EXT_RVMII) {
+		/*
+		 * Enable RGMII to interface external PHY, disable
+		 * internal 10/100 MII.
+		 */
+		GENET_RGMII_OOB_CTRL(pDevCtrl) |= RGMII_MODE_EN;
+	}
+	/* Power down EPHY */
+	if (pDevCtrl->ext)
+		pDevCtrl->ext->ext_pwr_mgmt |= (EXT_PWR_DOWN_PHY |
+			EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
+
+	for (i = 31; i >= 0; i--) {
+		if (bcmgenet_mii_read(dev, i, MII_BMSR) != 0) {
+			pDevCtrl->phyAddr = i;
+			if (i == 1)
+				continue;
+			return 0;
+		}
+		TRACE(("I=%d\n", i));
+	}
+	return -ENODEV;
+}
+
+/*
+ * setup netdev link state when PHY link status change and
+ * update UMAC and RGMII block when link up
+ */
+void bcmgenet_mii_setup(struct net_device *dev)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	struct ethtool_cmd ecmd;
+	volatile struct uniMacRegs *umac = pDevCtrl->umac;
+	int cur_link, prev_link;
+	unsigned int val, cmd_bits;
+
+	if (pDevCtrl->phyType == BRCM_PHY_TYPE_MOCA)
+		return;
+
+	cur_link = mii_link_ok(&pDevCtrl->mii);
+	prev_link = netif_carrier_ok(pDevCtrl->dev);
+	if (cur_link && !prev_link) {
+		mii_ethtool_gset(&pDevCtrl->mii, &ecmd);
+		/*
+		 * program UMAC and RGMII block based on established link
+		 * speed, pause, and duplex.
+		 * the speed set in umac->cmd tell RGMII block which clock
+		 * 25MHz(100Mbps)/125MHz(1Gbps) to use for transmit.
+		 * receive clock is provided by PHY.
+		 */
+		GENET_RGMII_OOB_CTRL(pDevCtrl) &= ~OOB_DISABLE;
+		GENET_RGMII_OOB_CTRL(pDevCtrl) |= RGMII_LINK;
+
+		/* speed */
+		if (ecmd.speed == SPEED_1000)
+			cmd_bits = UMAC_SPEED_1000;
+		else if (ecmd.speed == SPEED_100)
+			cmd_bits = UMAC_SPEED_100;
+		else
+			cmd_bits = UMAC_SPEED_10;
+		cmd_bits <<= CMD_SPEED_SHIFT;
+
+		/* duplex */
+		if (ecmd.duplex != DUPLEX_FULL)
+			cmd_bits |= CMD_HD_EN;
+
+		/* pause capability */
+		if (pDevCtrl->phyType == BRCM_PHY_TYPE_INT ||
+		    pDevCtrl->phyType == BRCM_PHY_TYPE_EXT_MII ||
+		    pDevCtrl->phyType == BRCM_PHY_TYPE_EXT_RVMII) {
+			val = bcmgenet_mii_read(
+				dev, pDevCtrl->phyAddr, MII_LPA);
+			if (!(val & LPA_PAUSE_CAP)) {
+				cmd_bits |= CMD_RX_PAUSE_IGNORE;
+				cmd_bits |= CMD_TX_PAUSE_IGNORE;
+			}
+		} else if (pDevCtrl->extPhy) { /* RGMII only */
+			val = bcmgenet_mii_read(dev,
+				pDevCtrl->phyAddr, MII_BRCM_AUX_STAT_SUM);
+			if (!(val & MII_BRCM_AUX_GPHY_RX_PAUSE))
+				cmd_bits |= CMD_RX_PAUSE_IGNORE;
+			if (!(val & MII_BRCM_AUX_GPHY_TX_PAUSE))
+				cmd_bits |= CMD_TX_PAUSE_IGNORE;
+		}
+
+		umac->cmd &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
+			       CMD_HD_EN |
+			       CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
+		umac->cmd |= cmd_bits;
+
+		netif_carrier_on(pDevCtrl->dev);
+		netdev_info(dev, "link up, %d Mbps, %s duplex\n", ecmd.speed,
+			ecmd.duplex == DUPLEX_FULL ? "full" : "half");
+	} else if (!cur_link && prev_link) {
+		netif_carrier_off(pDevCtrl->dev);
+		netdev_info(dev, "link down\n");
+	}
+}
+
+void bcmgenet_ephy_workaround(struct net_device *dev)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	int phy_id = pDevCtrl->phyAddr;
+
+	if (pDevCtrl->phyType != BRCM_PHY_TYPE_INT)
+		return;
+
+	/* workarounds are only needed for 100Mbps PHYs */
+	if (pDevCtrl->phySpeed == SPEED_1000)
+		return;
+
+	/* set shadow mode 2 */
+	bcmgenet_mii_set_clr_bits(dev, 0x1f, 0x0004, 0x0004);
+
+	/*
+	 * Workaround for SWLINUX-2281: explicitly reset IDDQ_CLKBIAS
+	 * in the Shadow 2 regset, due to power sequencing issues.
+	 */
+	/* set iddq_clkbias */
+	bcmgenet_mii_write(dev, phy_id, 0x14, 0x0F00);
+	udelay(10);
+	/* reset iddq_clkbias */
+	bcmgenet_mii_write(dev, phy_id, 0x14, 0x0C00);
+
+	/*
+	 * Workaround for SWLINUX-2056: fix timing issue between the ephy
+	 * digital and the ephy analog blocks.  This clock inversion will
+	 * inherently fix any setup and hold issue.
+	 */
+	bcmgenet_mii_write(dev, phy_id, 0x13, 0x7555);
+
+	/* reset shadow mode 2 */
+	bcmgenet_mii_set_clr_bits(dev, 0x1f, 0x0004, 0);
+}
+
+void bcmgenet_mii_reset(struct net_device *dev)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+
+	bcmgenet_mii_write(dev, pDevCtrl->phyAddr, MII_BMCR, BMCR_RESET);
+	udelay(1);
+	/* enable 64 clock MDIO */
+	bcmgenet_mii_write(dev, pDevCtrl->phyAddr, 0x1d, 0x1000);
+	bcmgenet_mii_read(dev, pDevCtrl->phyAddr, 0x1d);
+	bcmgenet_ephy_workaround(dev);
+}
+
+int bcmgenet_mii_init(struct net_device *dev)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	volatile struct uniMacRegs *umac;
+	u32 id_mode_dis = 0;
+	char *phy_name;
+
+	umac = pDevCtrl->umac;
+	pDevCtrl->mii.phy_id = pDevCtrl->phyAddr;
+	pDevCtrl->mii.phy_id_mask = 0x1f;
+	pDevCtrl->mii.reg_num_mask = 0x1f;
+	pDevCtrl->mii.dev = dev;
+	pDevCtrl->mii.mdio_read = bcmgenet_mii_read;
+	pDevCtrl->mii.mdio_write = bcmgenet_mii_write;
+	pDevCtrl->mii.supports_gmii = 0;
+
+	switch (pDevCtrl->phyType) {
+
+	case BRCM_PHY_TYPE_INT:
+		phy_name = "internal PHY";
+		if (pDevCtrl->phySpeed == SPEED_1000) {
+			pDevCtrl->mii.supports_gmii = 1;
+			pDevCtrl->sys->sys_port_ctrl = PORT_MODE_INT_GPHY;
+		} else
+			pDevCtrl->sys->sys_port_ctrl = PORT_MODE_INT_EPHY;
+		/* enable APD */
+		pDevCtrl->ext->ext_pwr_mgmt |= EXT_PWR_DN_EN_LD;
+		bcmgenet_mii_reset(dev);
+		break;
+	case BRCM_PHY_TYPE_EXT_MII:
+		phy_name = "external MII";
+		pDevCtrl->sys->sys_port_ctrl = PORT_MODE_EXT_EPHY;
+		break;
+	case BRCM_PHY_TYPE_EXT_RVMII:
+		phy_name = "external RvMII";
+		if (pDevCtrl->phySpeed == SPEED_100)
+			pDevCtrl->sys->sys_port_ctrl = PORT_MODE_EXT_RVMII_25;
+		else
+			pDevCtrl->sys->sys_port_ctrl = PORT_MODE_EXT_RVMII_50;
+		break;
+	case BRCM_PHY_TYPE_EXT_RGMII_NO_ID:
+		/*
+		 * RGMII_NO_ID: TXC transitions at the same time as TXD
+		 *              (requires PCB or receiver-side delay)
+		 * RGMII:       Add 2ns delay on TXC (90 degree shift)
+		 *
+		 * ID is implicitly disabled for 100Mbps (RG)MII operation.
+		 */
+		id_mode_dis = BIT(16);
+		/* fall through */
+	case BRCM_PHY_TYPE_EXT_RGMII:
+		phy_name = "external RGMII";
+		GENET_RGMII_OOB_CTRL(pDevCtrl) |= RGMII_MODE_EN | id_mode_dis;
+		pDevCtrl->sys->sys_port_ctrl = PORT_MODE_EXT_GPHY;
+		/*
+		 * setup mii based on configure speed and RGMII txclk is set in
+		 * umac->cmd, mii_setup() after link established.
+		 */
+		if (pDevCtrl->phySpeed == SPEED_1000) {
+			pDevCtrl->mii.supports_gmii = 1;
+		} else if (pDevCtrl->phySpeed == SPEED_100) {
+			/* disable 1000BASE-T full, half-duplex capability */
+			bcmgenet_mii_set_clr_bits(dev, MII_CTRL1000, 0,
+				(ADVERTISE_1000FULL|ADVERTISE_1000HALF));
+			/* restart autoneg */
+			bcmgenet_mii_set_clr_bits(dev, MII_BMCR, BMCR_ANRESTART,
+				BMCR_ANRESTART);
+		}
+		break;
+	case BRCM_PHY_TYPE_MOCA:
+		phy_name = "MoCA";
+		/* setup speed in umac->cmd for RGMII txclk set to 125MHz */
+		umac->cmd = umac->cmd | (UMAC_SPEED_1000 << CMD_SPEED_SHIFT);
+		pDevCtrl->mii.force_media = 1;
+		pDevCtrl->sys->sys_port_ctrl = PORT_MODE_INT_GPHY |
+			LED_ACT_SOURCE_MAC;
+		break;
+	default:
+		pr_err("unknown phy_type: %d\n", pDevCtrl->phyType);
+		return -1;
+	}
+
+	pr_info("configuring instance #%d for %s\n", pDevCtrl->pdev->id,
+		phy_name);
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/broadcom/genet-ng/bcmmii.h b/drivers/net/ethernet/broadcom/genet-ng/bcmmii.h
new file mode 100644
index 0000000..1509e26
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet-ng/bcmmii.h
@@ -0,0 +1,54 @@
+/*
+ *
+ * Copyright (c) 2002-2005 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *
+*/
+#ifndef _BCMMII_H_
+#define _BCMMII_H_
+
+/* BRCM EPHY Aux status summery Register */
+#define MII_BRCM_AUX_STAT_SUM				0x19
+#define MII_BRCM_AUX_FD						0x01
+#define MII_BRCM_AUX_AN						0x10
+#define MII_BRCM_AUX_LINK_UP				0x20
+#define MII_BRCM_AUX_SPEED_100				0x40
+#define MII_BRCM_AUX_LP_AN					0x80
+#define MII_BRCM_AUX_LP_PR					0x100
+/* highest common denominator*/
+#define MII_BRCM_AUX_AN_HCD_MASK			0x03
+#define MII_BRCM_AUX_AN_HCD_SHIFT			0x08
+#define MII_BRCM_AUX_AN_HCD_10T				0X01
+#define MII_BRCM_AUX_AN_HCD_10T_FULL		0x02
+#define MII_BRCM_AUX_AN_HCD_100TX			0x03
+#define MII_BRCM_AUX_AN_HCD_100T4			0x04
+#define MII_BRCM_AUX_AN_HCD_100TX_FULL		0x05
+#define MII_BRCM_AUX_AN_PAUSE				0x800
+#define MII_BRCM_AUX_AN_COMPLETE			0x8000
+/* BRCM GPHY Aux status summery register bits ?? */
+#define MII_BRCM_AUX_GPHY_TX_PAUSE			0
+#define MII_BRCM_AUX_GPHY_RX_PAUSE			1
+/****************************************************************************
+Prototypes
+****************************************************************************/
+
+extern void bcmgenet_mii_setup(struct net_device *dev);
+extern int bcmgenet_mii_init(struct net_device *dev);
+extern int bcmgenet_mii_probe(struct net_device *dev, void *p);
+extern void bcmgenet_mii_reset(struct net_device *dev);
+extern void bcmgenet_ephy_workaround(struct net_device *dev);
+
+#endif /* _BCMMII_H_ */
diff --git a/drivers/net/ethernet/broadcom/genet-ng/if_net.h b/drivers/net/ethernet/broadcom/genet-ng/if_net.h
new file mode 100644
index 0000000..e07b9f4
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet-ng/if_net.h
@@ -0,0 +1,72 @@
+/*
+ *
+ * Copyright (c) 2002-2005 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *
+ *if_net.h
+ * Purpose: network ioctl function data definations.
+*/
+#ifndef _IF_NET_H_
+#define _IF_NET_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+ * Ioctl definitions.
+ */
+/* go into ACPI WoL mode*/
+#define SIOCSACPISET		(SIOCDEVPRIVATE + 2)
+/* cancel ACPI WoL Mode */
+#define SIOCSACPICANCEL		(SIOCDEVPRIVATE + 3)
+/* get ACPI pattern */
+#define SIOCGPATTERN		(SIOCDEVPRIVATE + 4)
+/* set ACPI pattern */
+#define SIOCSPATTERN		(SIOCDEVPRIVATE + 5)
+
+/*
+ * ACPI pattern (or generic HFB ) data
+ */
+union acpi_pattern {
+	unsigned long value;
+	struct {
+#ifdef __BIG_ENDIAN
+		unsigned long unused:12;
+		unsigned long mask:4;
+		unsigned long data:16;
+#else
+		unsigned long data:16;
+		unsigned long mask:4;
+		unsigned long unused:12;
+#endif
+	} pattern;
+};
+
+/* used by ioctl call */
+struct acpi_data {
+	/* current filter index */
+	int fltr_index;
+	/* pointer to the pattern data.*/
+	union acpi_pattern *p_data;
+	/* total count of the data */
+	int count;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _IF_NET_H_ */
diff --git a/drivers/net/ethernet/broadcom/genet/Kconfig b/drivers/net/ethernet/broadcom/genet/Kconfig
new file mode 100644
index 0000000..c1ed960
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet/Kconfig
@@ -0,0 +1,47 @@
+menu "BCMGENET options"
+
+config BCMGENET_RX_DESC_THROTTLE 
+	bool "use hardware rx descriptor throttling"
+	depends on BCMGENET
+	default n
+	help
+	  Instead of generating one interrupt for rx packet, the genet can 
+	  generate 1 interrupt for multiple rx packet, thus to reduce the interrupt
+	  number.
+
+config BCMGENET_NAPI
+	bool "use software rx descriptor throttling"
+	depends on BCMGENET
+	default y
+	help
+	  Use software interrupt throttling(the NAPI approach).
+
+config BCMGENET_RX_CSUM
+	bool "Enable L4 checksum offloading for rx"
+	depends on BCMGENET
+	default n
+	help
+	  Enable L4 checksum offloading for rx.
+
+config BCMGENET_TX_CSUM
+	bool "Enable L4 checksum offloading for tx"
+	depends on BCMGENET
+	default n
+	help
+	  Enable L4 checksum offloading for tx.
+
+config BCMGENET_DUMP_DATA
+	bool "Dump out data for debugging"
+	depends on BCMGENET
+	default n
+	help
+	  Dump out data for debugging.
+
+config BCMGENET_DUMP_TRACE
+	bool "Dump out trace message for debugging"
+	depends on BCMGENET
+	default n
+	help
+	  Dump out trace messages for debugging.
+endmenu
+
diff --git a/drivers/net/ethernet/broadcom/genet/Makefile b/drivers/net/ethernet/broadcom/genet/Makefile
new file mode 100644
index 0000000..3d29691
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet/Makefile
@@ -0,0 +1,4 @@
+obj-$(CONFIG_BCMGENET)		+= brcmgenet.o
+brcmgenet-objs := bcmgenet.o bcmmii.o ethsw.o
+
+EXTRA_CFLAGS += -I.
diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet.c b/drivers/net/ethernet/broadcom/genet/bcmgenet.c
new file mode 100644
index 0000000..97fad5a
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c
@@ -0,0 +1,3998 @@
+/*
+ * Copyright (c) 2002-2008 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *
+ * File Name  : bcmgenet.c
+ *
+ * Description: This is Linux driver for the broadcom GENET ethernet MAC core.
+
+*/
+
+#include "bcmgenet.h"
+#include "bcmmii.h"
+#include "if_net.h"
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/fcntl.h>
+#include <linux/interrupt.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/pm.h>
+#include <linux/clk.h>
+#include <linux/version.h>
+#include <asm/unaligned.h>
+
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/netdevice.h>
+#include <linux/inetdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/in.h>
+
+#include <linux/brcmstb/brcmstb.h>
+#include <linux/brcmstb/brcmapi.h>
+
+#ifdef CONFIG_NET_SCH_MULTIQ
+
+#if CONFIG_BRCM_GENET_VERSION == 1
+#error "This version of GENET doesn't support tx multi queue"
+#endif
+/* Default # of tx queues for multi queue support */
+#define GENET_MQ_CNT		4
+/* Default # of bds for each queue for multi queue support */
+#define GENET_MQ_BD_CNT		32
+/* Default highest priority queue for multi queue support */
+#define GENET_Q0_PRIORITY	0
+
+#define GENET_DEFAULT_BD_CNT	\
+	(TOTAL_DESC - GENET_MQ_CNT * GENET_MQ_BD_CNT)
+
+static void bcmgenet_init_multiq(struct net_device *dev);
+
+#endif	/*CONFIG_NET_SCH_MULTIQ */
+
+#define RX_BUF_LENGTH		2048
+#define RX_BUF_BITS			12
+#define SKB_ALIGNMENT		32
+#define DMA_DESC_THRES		4
+#define HFB_TCP_LEN			19
+#define HFB_ARP_LEN			21
+
+/* Tx/Rx DMA register offset, skip 256 descriptors */
+#define GENET_TDMA_REG_OFF	(GENET_TDMA_OFF + \
+		2*TOTAL_DESC*sizeof(unsigned long))
+#define GENET_RDMA_REG_OFF	(GENET_RDMA_OFF + \
+		2*TOTAL_DESC*sizeof(unsigned long))
+
+/* --------------------------------------------------------------------------
+External, indirect entry points.
+--------------------------------------------------------------------------*/
+static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
+/* --------------------------------------------------------------------------
+Called for "ifconfig ethX up" & "down"
+--------------------------------------------------------------------------*/
+static int bcmgenet_open(struct net_device *dev);
+static int bcmgenet_close(struct net_device *dev);
+/* --------------------------------------------------------------------------
+Watchdog timeout
+--------------------------------------------------------------------------*/
+static void bcmgenet_timeout(struct net_device *dev);
+/* --------------------------------------------------------------------------
+Packet transmission.
+--------------------------------------------------------------------------*/
+static int bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev);
+/* --------------------------------------------------------------------------
+Set address filtering mode
+--------------------------------------------------------------------------*/
+static void bcmgenet_set_rx_mode(struct net_device *dev);
+/* --------------------------------------------------------------------------
+Set the hardware MAC address.
+--------------------------------------------------------------------------*/
+static int bcmgenet_set_mac_addr(struct net_device *dev, void *p);
+
+/* --------------------------------------------------------------------------
+Interrupt routine, for all interrupts except ring buffer interrupts
+--------------------------------------------------------------------------*/
+static irqreturn_t bcmgenet_isr0(int irq, void *dev_id);
+/*---------------------------------------------------------------------------
+IRQ handler for ring buffer interrupt.
+--------------------------------------------------------------------------*/
+static irqreturn_t bcmgenet_isr1(int irq, void *dev_id);
+/* --------------------------------------------------------------------------
+dev->poll() method
+--------------------------------------------------------------------------*/
+static int bcmgenet_poll(struct napi_struct *napi, int budget);
+static int bcmgenet_ring_poll(struct napi_struct *napi, int budget);
+/* --------------------------------------------------------------------------
+Process recived packet for descriptor based DMA
+--------------------------------------------------------------------------*/
+static unsigned int bcmgenet_desc_rx(void *ptr, unsigned int budget);
+/* --------------------------------------------------------------------------
+Process recived packet for ring buffer DMA
+--------------------------------------------------------------------------*/
+static unsigned int bcmgenet_ring_rx(void *ptr, unsigned int budget);
+/* --------------------------------------------------------------------------
+Internal routines
+--------------------------------------------------------------------------*/
+/* Allocate and initialize tx/rx buffer descriptor pools */
+static int bcmgenet_init_dev(struct BcmEnet_devctrl *pDevCtrl, bool reset);
+static void bcmgenet_uninit_dev(struct BcmEnet_devctrl *pDevCtrl);
+/* Assign the Rx descriptor ring */
+static int assign_rx_buffers(struct BcmEnet_devctrl *pDevCtrl);
+/* Initialize the uniMac control registers */
+static int init_umac(struct BcmEnet_devctrl *pDevCtrl, bool reset);
+/* Initialize DMA control register */
+static void init_edma(struct BcmEnet_devctrl *pDevCtrl);
+/* Interrupt bottom-half */
+static void bcmgenet_irq_task(struct work_struct *work);
+/* power management */
+static void bcmgenet_power_down(struct BcmEnet_devctrl *pDevCtrl, int mode);
+static void bcmgenet_power_up(struct BcmEnet_devctrl *pDevCtrl, int mode);
+/* allocate an skb, the data comes from ring buffer */
+static struct sk_buff *__bcmgenet_alloc_skb_from_buf(unsigned char *buf,
+		int len, int headroom);
+/* clock control */
+static void bcmgenet_clock_enable(struct BcmEnet_devctrl *pDevCtrl);
+static void bcmgenet_clock_disable(struct BcmEnet_devctrl *pDevCtrl);
+/* S3 warm boot */
+static void save_state(struct BcmEnet_devctrl *pDevCtrl);
+static void restore_state(struct BcmEnet_devctrl *pDevCtrl);
+
+static struct net_device *eth_root_dev;
+static int DmaDescThres = DMA_DESC_THRES;
+
+/*
+ * HFB data for ARP request.
+ * In WoL (Magic Packet or ACPI) mode, we need to response
+ * ARP request, so dedicate an HFB to filter the ARP request.
+ * NOTE: the last two words are to be filled by destination.
+ */
+static unsigned int hfb_arp[] = {
+	0x000FFFFF, 0x000FFFFF, 0x000FFFFF,	0x00000000,
+	0x00000000, 0x00000000, 0x000F0806,	0x000F0001,
+	0x000F0800,	0x000F0604, 0x000F0001,	0x00000000,
+	0x00000000,	0x00000000,	0x00000000, 0x00000000,
+	0x000F0000,	0x000F0000,	0x000F0000,	0x000F0000,
+	0x000F0000
+};
+/* -------------------------------------------------------------------------
+ *  The following bcmemac_xxxx() functions are legacy netaccel hook, will be
+ *  replaced!
+ *  -----------------------------------------------------------------------*/
+struct net_device *bcmemac_get_device(void)
+{
+	return eth_root_dev;
+}
+EXPORT_SYMBOL(bcmemac_get_device);
+/* --------------------------------------------------------------------------
+Name: bcmemac_get_free_txdesc
+Purpose: Get Current Available TX desc count
+-------------------------------------------------------------------------- */
+int bcmemac_get_free_txdesc(struct net_device *dev)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	return pDevCtrl->txFreeBds;
+}
+EXPORT_SYMBOL(bcmemac_get_free_txdesc);
+/* --------------------------------------------------------------------------
+Name: bcmemac_xmit_check
+Purpose: Reclaims TX descriptors
+-------------------------------------------------------------------------- */
+int bcmemac_xmit_check(struct net_device *dev)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	struct Enet_CB *txCBPtr;
+	unsigned long flags, ret;
+	unsigned int c_index;
+	int lastTxedCnt = 0, i = 0;
+	/*
+	* Obtain exclusive access to transmitter.  This is necessary because
+	* we might have more than one stack transmitting at once.
+	*/
+	spin_lock_irqsave(&pDevCtrl->lock, flags);
+	/* Compute how many buffers are transmited since last xmit call */
+	c_index = pDevCtrl->txDma->tDmaRings[16].tdma_consumer_index;
+	c_index &= (TOTAL_DESC - 1);
+
+	if (c_index >= pDevCtrl->txLastCIndex)
+		lastTxedCnt = c_index - pDevCtrl->txLastCIndex;
+	else
+		lastTxedCnt = TOTAL_DESC - pDevCtrl->txLastCIndex + c_index;
+
+	TRACE(("c_index=%d lastTxedCnt=%d txLastCIndex=%d\n",
+				c_index, lastTxedCnt, pDevCtrl->txLastCIndex));
+
+	/* Recalaim transmitted buffers */
+	i = pDevCtrl->txLastCIndex;
+	while (lastTxedCnt-- > 0) {
+		txCBPtr = &pDevCtrl->txCbs[i];
+		if (txCBPtr->skb != NULL) {
+			dma_unmap_single(&pDevCtrl->dev->dev,
+					dma_unmap_addr(txCBPtr, dma_addr),
+					dma_unmap_len(txCBPtr, dma_len),
+					DMA_TO_DEVICE);
+			dev_kfree_skb_any(txCBPtr->skb);
+			txCBPtr->skb = NULL;
+		}
+		pDevCtrl->txFreeBds += 1;
+		if (i == (TOTAL_DESC - 1))
+			i = 0;
+		else
+			i++;
+	}
+	pDevCtrl->txLastCIndex = c_index;
+	if (pDevCtrl->txFreeBds > 0) {
+		/* Disable txdma bdone/pdone interrupt if we have free tx bds */
+		pDevCtrl->intrl2_0->cpu_mask_set |= (UMAC_IRQ_TXDMA_BDONE |
+			UMAC_IRQ_TXDMA_PDONE);
+		netif_wake_queue(dev);
+		ret = 0;
+	} else {
+		ret = 1;
+	}
+	spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+
+	return ret;
+}
+EXPORT_SYMBOL(bcmemac_xmit_check);
+/* --------------------------------------------------------------------------
+Name: bcmemac_xmit_fragment
+Purpose: Send ethernet traffic Buffer DESC and submit to UDMA
+-------------------------------------------------------------------------- */
+int bcmemac_xmit_fragment(int ch, unsigned char *buf, int buf_len,
+		unsigned long tx_flags , struct net_device *dev)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	struct Enet_CB *txCBPtr;
+	unsigned int write_ptr = 0;
+	dma_addr_t mapping;
+
+	if (pDevCtrl->txFreeBds == 0)
+		return 1;
+	/*
+	 * We must don't have 64B status block enabled in this case!
+	 */
+	write_ptr = pDevCtrl->txDma->tDmaRings[16].tdma_write_pointer;
+	write_ptr = ((write_ptr & DMA_RW_POINTER_MASK) >> 1);
+
+	/* Obtain transmit control block */
+	txCBPtr = &pDevCtrl->txCbs[write_ptr];
+	txCBPtr->BdAddr = &pDevCtrl->txBds[write_ptr];
+	mapping = dma_map_single(&pDevCtrl->dev->dev, buf,
+			buf_len, DMA_TO_DEVICE);
+	if (dma_mapping_error(&pDevCtrl->dev->dev, mapping)) {
+		dev_err(&pDevCtrl->dev->dev, "xmit_fragment DMA map error\n");
+		return 1;
+	}
+	dma_unmap_addr_set(txCBPtr, dma_addr, mapping);
+	dma_unmap_len_set(txCBPtr, dma_len, buf_len);
+
+	/*
+	 * Add the buffer to the ring.
+	 * Set addr and length of DMA BD to be transmitted.
+	 */
+	txCBPtr->BdAddr->address = mapping;
+	txCBPtr->BdAddr->length_status = ((unsigned long)(buf_len))<<16;
+	txCBPtr->BdAddr->length_status |= tx_flags | DMA_TX_APPEND_CRC;
+
+	/* Default QTAG for MoCA */
+	txCBPtr->BdAddr->length_status |=
+		(DMA_TX_QTAG_MASK << DMA_TX_QTAG_SHIFT);
+
+#ifdef CONFIG_BCMGENET_DUMP_DATA
+	TRACE(("%s: len %d", __func__, buf_len));
+	print_hex_dump(KERN_NOTICE, "", DUMP_PREFIX_ADDRESS,
+			16, 1, buf, buf_len, 0);
+#endif
+
+	/* Decrement total BD count and advance our write pointer */
+	pDevCtrl->txFreeBds -= 1;
+
+	if (write_ptr == pDevCtrl->nrTxBds - 1)
+		write_ptr = 0;
+	else
+		write_ptr++;
+	/* advance producer index and write pointer.*/
+	pDevCtrl->txDma->tDmaRings[DESC_INDEX].tdma_producer_index += 1;
+	pDevCtrl->txDma->tDmaRings[DESC_INDEX].tdma_write_pointer += 2;
+
+	if (pDevCtrl->txFreeBds == 0) {
+		TRACE(("%s: %s no transmit queue space -- stopping queues\n",
+				dev->name, __func__));
+		/* Enable Tx bdone/pdone interrupt !*/
+		pDevCtrl->intrl2_0->cpu_mask_clear |= (UMAC_IRQ_TXDMA_BDONE |
+				UMAC_IRQ_TXDMA_PDONE);
+		netif_stop_queue(dev);
+	}
+	/* update stats */
+	dev->stats.tx_bytes += buf_len;
+	dev->stats.tx_packets++;
+
+	dev->trans_start = jiffies;
+
+	return 0;
+}
+EXPORT_SYMBOL(bcmemac_xmit_fragment);
+/* --------------------------------------------------------------------------
+Name: bcmemac_xmit_multibuf
+Purpose: Send ethernet traffic in multi buffers (hdr, buf, tail)
+-------------------------------------------------------------------------- */
+int bcmemac_xmit_multibuf(int ch, unsigned char *hdr, int hdr_len,
+		unsigned char *buf, int buf_len, unsigned char *tail,
+		int tail_len, struct net_device *dev)
+{
+	unsigned long flags;
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+
+	while (bcmemac_xmit_check(dev))
+		;
+
+	/*
+	* Obtain exclusive access to transmitter.  This is necessary because
+	* we might have more than one stack transmitting at once.
+	*/
+	spin_lock_irqsave(&pDevCtrl->lock, flags);
+
+	/* Header + Optional payload in two parts */
+	if ((hdr_len > 0) && (buf_len > 0) &&
+			(tail_len > 0) && (hdr) &&
+			(buf) && (tail)) {
+		/* Send Header */
+		while (bcmemac_xmit_fragment(ch, hdr, hdr_len, DMA_SOP, dev))
+			bcmemac_xmit_check(dev);
+		/* Send First Fragment */
+		while (bcmemac_xmit_fragment(ch, buf, buf_len, 0, dev))
+			bcmemac_xmit_check(dev);
+		/* Send 2nd Fragment */
+		while (bcmemac_xmit_fragment(ch, tail, tail_len, DMA_EOP, dev))
+			bcmemac_xmit_check(dev);
+	} else if ((hdr_len > 0) && (buf_len > 0) && (hdr) && (buf)) {
+		/* Header + Optional payload */
+		/* Send Header */
+		while (bcmemac_xmit_fragment(ch, hdr, hdr_len, DMA_SOP, dev))
+			bcmemac_xmit_check(dev);
+		/* Send First Fragment */
+		while (bcmemac_xmit_fragment(ch, buf, buf_len, DMA_EOP, dev))
+			bcmemac_xmit_check(dev);
+	} else if ((hdr_len > 0) && (hdr)) {
+		/* Header Only (includes payload) */
+		/* Send Header */
+		while (bcmemac_xmit_fragment(ch, hdr, hdr_len,
+					DMA_SOP | DMA_EOP, dev))
+			bcmemac_xmit_check(dev);
+	} else {
+		spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+		return 0; /* Drop the packet */
+	}
+	spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+	return 0;
+}
+EXPORT_SYMBOL(bcmemac_xmit_multibuf);
+static inline void handleAlignment(struct BcmEnet_devctrl *pDevCtrl,
+		struct sk_buff *skb)
+{
+	/*
+	 * We request to allocate 2048 + 32 bytes of buffers, and the
+	 * dev_alloc_skb() added 16B for NET_SKB_PAD, so we totally
+	 * requested 2048+32+16 bytes buffer, the size was aligned to
+	 * SMP_CACHE_BYTES, which is 64B.(is it?), so we finnally ended
+	 * up got 2112 bytes of buffer! Among which, the first 16B is
+	 * reserved for NET_SKB_PAD, to make the skb->data aligned 32B
+	 * boundary, we should have enough space to fullfill the 2KB
+	 * buffer after alignment!
+     */
+
+	unsigned long boundary32, curData, resHeader;
+
+	curData = (unsigned long) skb->data;
+	boundary32 = (curData + (SKB_ALIGNMENT - 1)) & ~(SKB_ALIGNMENT - 1);
+	resHeader = boundary32 - curData ;
+	/* 4 bytes for skb pointer */
+	if (resHeader < 4)
+		boundary32 += 32;
+
+	resHeader = boundary32 - curData - 4;
+	/* We'd have minimum 16B reserved by default. */
+	skb_reserve(skb, resHeader);
+
+	*(unsigned int *)skb->data = (unsigned int)skb;
+	skb_reserve(skb, 4);
+	/*
+	 * Make sure it is on 32B boundary, should never happen if our
+	 * calculation was correct.
+	 */
+	if ((unsigned long) skb->data & (SKB_ALIGNMENT - 1)) {
+		printk(KERN_WARNING "skb buffer is NOT aligned on %d boundary!\n",
+			SKB_ALIGNMENT);
+	}
+
+	/*
+	 *  we don't reserve 2B for IP Header optimization here,
+	 *  use skb_pull when receiving packets
+	 */
+}
+/* --------------------------------------------------------------------------
+Name: bcmgenet_gphy_link_status
+Purpose: GPHY link status monitoring task
+-------------------------------------------------------------------------- */
+static void bcmgenet_gphy_link_status(struct work_struct *work)
+{
+	struct BcmEnet_devctrl *pDevCtrl = container_of(work,
+			struct BcmEnet_devctrl, bcmgenet_link_work);
+
+	bcmgenet_mii_setup(pDevCtrl->dev, 0);
+}
+/* --------------------------------------------------------------------------
+Name: bcmgenet_gphy_link_timer
+Purpose: GPHY link status monitoring timer function
+-------------------------------------------------------------------------- */
+static void bcmgenet_gphy_link_timer(unsigned long data)
+{
+	struct BcmEnet_devctrl *pDevCtrl = (struct BcmEnet_devctrl *)data;
+	schedule_work(&pDevCtrl->bcmgenet_link_work);
+	mod_timer(&pDevCtrl->timer, jiffies + HZ);
+}
+
+static int bcmgenet_wakeup_enable(void *ref)
+{
+	struct BcmEnet_devctrl *pDevCtrl = (struct BcmEnet_devctrl *)ref;
+	u32 mask;
+	if (pDevCtrl->phyType == BRCM_PHY_TYPE_MOCA)
+		mask = WOL_MOCA_MASK;
+	else
+		mask = pDevCtrl->devnum ? WOL_MOCA_MASK : WOL_ENET_MASK;
+	if (device_may_wakeup(&pDevCtrl->dev->dev))
+		brcm_pm_wakeup_source_enable(mask, 1);
+	return 0;
+}
+
+static int bcmgenet_wakeup_disable(void *ref)
+{
+	struct BcmEnet_devctrl *pDevCtrl = (struct BcmEnet_devctrl *)ref;
+	u32 mask;
+	if (pDevCtrl->phyType == BRCM_PHY_TYPE_MOCA)
+		mask = WOL_MOCA_MASK;
+	else
+		mask = pDevCtrl->devnum ? WOL_MOCA_MASK : WOL_ENET_MASK;
+	if (device_may_wakeup(&pDevCtrl->dev->dev))
+		brcm_pm_wakeup_source_enable(mask, 0);
+	return 0;
+}
+
+static int bcmgenet_wakeup_poll(void *ref)
+{
+	struct BcmEnet_devctrl *pDevCtrl = (struct BcmEnet_devctrl *)ref;
+	int retval = 0;
+	u32 mask = 0;
+
+	if (device_may_wakeup(&pDevCtrl->dev->dev)) {
+		if (pDevCtrl->phyType == BRCM_PHY_TYPE_MOCA)
+			mask = WOL_MOCA_MASK;
+		else
+			mask = pDevCtrl->devnum ? WOL_MOCA_MASK : WOL_ENET_MASK;
+		retval = brcm_pm_wakeup_get_status(mask);
+	}
+	printk(KERN_DEBUG "%s %s(%08x): %d\n", __func__,
+	       pDevCtrl->dev->name, mask, retval);
+	return retval;
+}
+
+static struct brcm_wakeup_ops bcmgenet_wakeup_ops = {
+	.enable = bcmgenet_wakeup_enable,
+	.disable = bcmgenet_wakeup_disable,
+	.poll = bcmgenet_wakeup_poll,
+};
+
+/* --------------------------------------------------------------------------
+Name: bcmgenet_open
+Purpose: Open and Initialize the EMAC on the chip
+-------------------------------------------------------------------------- */
+static int bcmgenet_open(struct net_device *dev)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	unsigned long dma_ctrl;
+	volatile struct uniMacRegs *umac = pDevCtrl->umac;
+	unsigned int do_reinit = 0;
+
+	TRACE(("%s: bcmgenet_open\n", dev->name));
+
+	bcmgenet_clock_enable(pDevCtrl);
+
+	/* take MAC out of reset */
+	GENET_RBUF_FLUSH_CTRL(pDevCtrl) &= ~BIT(1);
+	udelay(10);
+
+	/* disable ethernet MAC while updating its registers */
+	umac->cmd &= ~(CMD_TX_EN | CMD_RX_EN);
+
+	umac->mac_0 = (dev->dev_addr[0] << 24 |
+			dev->dev_addr[1] << 16 |
+			dev->dev_addr[2] << 8  |
+			dev->dev_addr[3]);
+	umac->mac_1 = dev->dev_addr[4] << 8 | dev->dev_addr[5];
+
+	if (pDevCtrl->wol_enabled) {
+		/* From WOL-enabled suspend, switch to regular clock */
+		clk_disable(pDevCtrl->clk_wol);
+		do_reinit = 1;
+	}
+	/* From deep sleep, re-initialize UMAC and MII configuration */
+	if (brcm_pm_deep_sleep())
+		do_reinit = 1;
+
+	if (do_reinit) {
+		/* init umac registers to synchronize s/w with h/w */
+		init_umac(pDevCtrl, true);
+		/* Speed settings must be restored */
+		bcmgenet_mii_init(dev);
+		bcmgenet_mii_setup(dev, 1);
+	}
+
+	if (pDevCtrl->phyType == BRCM_PHY_TYPE_INT)
+		pDevCtrl->ext->ext_pwr_mgmt |= EXT_ENERGY_DET_MASK;
+
+	if (test_and_clear_bit(GENET_POWER_WOL_MAGIC, &pDevCtrl->wol_enabled))
+		bcmgenet_power_up(pDevCtrl, GENET_POWER_WOL_MAGIC);
+	if (test_and_clear_bit(GENET_POWER_WOL_ACPI, &pDevCtrl->wol_enabled))
+		bcmgenet_power_up(pDevCtrl, GENET_POWER_WOL_ACPI);
+
+	/* disable DMA */
+	dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
+	pDevCtrl->txDma->tdma_ctrl &= ~dma_ctrl;
+	pDevCtrl->rxDma->rdma_ctrl &= ~dma_ctrl;
+	umac->tx_flush = 1;
+	udelay(10);
+	umac->tx_flush = 0;
+
+	/* reset dma, start from beginning of the ring. */
+	init_edma(pDevCtrl);
+	/* reset internal book keeping variables. */
+	pDevCtrl->txLastCIndex = 0;
+	pDevCtrl->rxBdAssignPtr = pDevCtrl->rxBds;
+
+	if (brcm_pm_deep_sleep())
+		restore_state(pDevCtrl);
+	else
+		assign_rx_buffers(pDevCtrl);
+
+	pDevCtrl->txFreeBds = pDevCtrl->nrTxBds;
+
+	/*Always enable ring 16 - descriptor ring */
+	pDevCtrl->rxDma->rdma_ctrl |= dma_ctrl;
+	pDevCtrl->txDma->tdma_ctrl |= dma_ctrl;
+
+	if (pDevCtrl->extPhy)
+		mod_timer(&pDevCtrl->timer, jiffies);
+
+	if (request_irq(pDevCtrl->irq0, bcmgenet_isr0, IRQF_SHARED,
+				dev->name, pDevCtrl) < 0) {
+		printk(KERN_ERR "can't request IRQ %d\n", pDevCtrl->irq0);
+		goto err2;
+	}
+	if (request_irq(pDevCtrl->irq1, bcmgenet_isr1, IRQF_SHARED,
+				dev->name, pDevCtrl) < 0) {
+		printk(KERN_ERR "can't request IRQ %d\n", pDevCtrl->irq1);
+		free_irq(pDevCtrl->irq0, pDevCtrl);
+		goto err1;
+	}
+	/* Start the network engine */
+	napi_enable(&pDevCtrl->napi);
+
+	umac->cmd |= (CMD_TX_EN | CMD_RX_EN);
+
+	brcm_pm_wakeup_register(&bcmgenet_wakeup_ops, pDevCtrl, dev->name);
+	device_set_wakeup_capable(&dev->dev, 1);
+
+	if (pDevCtrl->phyType == BRCM_PHY_TYPE_INT)
+		bcmgenet_power_up(pDevCtrl, GENET_POWER_PASSIVE);
+
+	netif_tx_start_all_queues(dev);
+
+	return 0;
+err1:
+	free_irq(pDevCtrl->irq0, dev);
+err2:
+	free_irq(pDevCtrl->irq1, dev);
+	del_timer_sync(&pDevCtrl->timer);
+	netif_tx_stop_all_queues(dev);
+
+	return -ENODEV;
+}
+
+static void bcmgenet_free_rx_buffers(struct BcmEnet_devctrl *pDevCtrl)
+{
+	struct Enet_CB *cb;
+	unsigned int i;
+	unsigned int freed = 0;
+
+	for (i = 0; i < pDevCtrl->nrRxBds; i++) {
+		cb = &pDevCtrl->rxCbs[i];
+
+		if (dma_unmap_addr(cb, dma_addr)) {
+			dma_unmap_single(&pDevCtrl->dev->dev,
+					 dma_unmap_addr(cb, dma_addr),
+					 pDevCtrl->rxBufLen, DMA_FROM_DEVICE);
+			dma_unmap_addr_set(cb, dma_addr, 0);
+		}
+
+		if (cb->skb) {
+			freed++;
+			dev_kfree_skb(pDevCtrl->rxCbs[i].skb);
+			cb->skb = NULL;
+		}
+
+		/* Reset the address to 0, such that next calls to assign_rx_buffers
+		 * re-allocate buffers
+		 */
+		pDevCtrl->rxBds[i].address = 0;
+	}
+
+	pDevCtrl->rxBdAssignPtr = pDevCtrl->rxBds;
+
+	TRACE(("%s: freed: %d SKBs\n", __func__, freed));
+}
+
+/* --------------------------------------------------------------------------
+Name: bcmgenet_close
+Purpose: Stop communicating with the outside world
+Note: Caused by 'ifconfig ethX down'
+-------------------------------------------------------------------------- */
+static int bcmgenet_close(struct net_device *dev)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	int timeout = 0;
+
+	TRACE(("%s: bcmgenet_close\n", dev->name));
+
+	/* Disable MAC receive */
+	pDevCtrl->umac->cmd &= ~CMD_RX_EN;
+
+	netif_tx_stop_all_queues(dev);
+
+	/* Disable TDMA to stop add more frames in TX DMA */
+	pDevCtrl->txDma->tdma_ctrl &= ~DMA_EN;
+	/* Check TDMA status register to confirm TDMA is disabled */
+	while (!(pDevCtrl->txDma->tdma_status & DMA_DISABLED)) {
+		if (timeout++ == 5000) {
+			netdev_warn(pDevCtrl->dev,
+				"Timed out while disabling TX DMA\n");
+			break;
+		}
+		udelay(1);
+	}
+
+	/* SWLINUX-2252: Workaround for rx flush issue causes rbuf overflow */
+	/* Wait 10ms for packet drain in both tx and rx dma */
+	usleep_range(10000, 20000);
+
+	/* Disable RDMA */
+	pDevCtrl->rxDma->rdma_ctrl &= ~DMA_EN;
+	/* Check RDMA status register to confirm RDMA is disabled */
+	while (!(pDevCtrl->rxDma->rdma_status & DMA_DISABLED)) {
+		if (timeout++ == 5000) {
+			netdev_warn(pDevCtrl->dev,
+				"Timed out while disabling RX DMA\n");
+			break;
+		}
+		udelay(1);
+	}
+
+	/* Disable MAC transmit. TX DMA disabled have to done before this */
+	pDevCtrl->umac->cmd &= ~CMD_TX_EN;
+
+	napi_disable(&pDevCtrl->napi);
+
+	/* tx reclaim */
+	bcmgenet_xmit(NULL, dev);
+	free_irq(pDevCtrl->irq0, (void *)pDevCtrl);
+	free_irq(pDevCtrl->irq1, (void *)pDevCtrl);
+	if (pDevCtrl->extPhy) {
+		del_timer_sync(&pDevCtrl->timer);
+		cancel_work_sync(&pDevCtrl->bcmgenet_link_work);
+	}
+	/*
+	 * Wait for pending work items to complete - we are stopping
+	 * the clock now. Since interrupts are disabled, no new work
+	 * will be scheduled.
+	 */
+	cancel_work_sync(&pDevCtrl->bcmgenet_irq_work);
+
+	/* Set carrier state as down, except for MoCA interfaces */
+	if (pDevCtrl->phyType != BRCM_PHY_TYPE_MOCA)
+		netif_carrier_off(dev);
+
+	if (brcm_pm_deep_sleep())
+		save_state(pDevCtrl);
+	else
+		bcmgenet_free_rx_buffers(pDevCtrl);
+
+	if (device_may_wakeup(&dev->dev) && pDevCtrl->dev_asleep) {
+		if (pDevCtrl->wolopts & (WAKE_MAGIC|WAKE_MAGICSECURE))
+			bcmgenet_power_down(pDevCtrl, GENET_POWER_WOL_MAGIC);
+		if (pDevCtrl->wolopts & WAKE_ARP)
+			bcmgenet_power_down(pDevCtrl, GENET_POWER_WOL_ACPI);
+	} else if (pDevCtrl->phyType == BRCM_PHY_TYPE_INT)
+		bcmgenet_power_down(pDevCtrl, GENET_POWER_PASSIVE);
+
+	if (pDevCtrl->wol_enabled)
+		clk_enable(pDevCtrl->clk_wol);
+
+	bcmgenet_clock_disable(pDevCtrl);
+
+	return 0;
+}
+
+/* --------------------------------------------------------------------------
+Name: bcmgenet_net_timeout
+Purpose:
+-------------------------------------------------------------------------- */
+static void bcmgenet_timeout(struct net_device *dev)
+{
+	BUG_ON(dev == NULL);
+
+	TRACE(("%s: bcmgenet_timeout\n", dev->name));
+
+	dev->trans_start = jiffies;
+
+	dev->stats.tx_errors++;
+
+	netif_tx_wake_all_queues(dev);
+}
+
+/* --------------------------------------------------------------------------
+Name: bcmgenet_set_rx_mode
+Purpose: ndo_set_rx_mode entry point, called when unicast or multicast
+address list, or network interface flags are updated.
+-------------------------------------------------------------------------- */
+static void bcmgenet_set_rx_mode(struct net_device *dev)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	struct netdev_hw_addr *ha;
+	int i, mc;
+#define MAX_MC_COUNT	16
+
+	TRACE(("%s: %s: %08X\n",
+		dev->name, __func__, dev->flags));
+
+	/* Promiscous mode */
+	if (dev->flags & IFF_PROMISC) {
+		pDevCtrl->umac->cmd |= CMD_PROMISC;
+		pDevCtrl->umac->mdf_ctrl = 0;
+		return;
+	} else
+		pDevCtrl->umac->cmd &= ~CMD_PROMISC;
+
+
+	/* UniMac doesn't support ALLMULTI */
+	if (dev->flags & IFF_ALLMULTI)
+		return;
+
+	/* update MDF filter */
+	i = 0;
+	mc = 0;
+	/* Broadcast */
+	pDevCtrl->umac->mdf_addr[i] = 0xFFFF;
+	pDevCtrl->umac->mdf_addr[i+1] = 0xFFFFFFFF;
+	pDevCtrl->umac->mdf_ctrl |= (1 << (MAX_MC_COUNT - mc));
+	i += 2;
+	mc++;
+	/* my own address.*/
+	pDevCtrl->umac->mdf_addr[i] = (dev->dev_addr[0]<<8) | dev->dev_addr[1];
+	pDevCtrl->umac->mdf_addr[i+1] = dev->dev_addr[2] << 24 |
+		dev->dev_addr[3] << 16 |
+		dev->dev_addr[4] << 8 |
+		dev->dev_addr[5];
+	pDevCtrl->umac->mdf_ctrl |= (1 << (MAX_MC_COUNT - mc));
+	i += 2;
+	mc++;
+	/* Unicast list*/
+	if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
+		return;
+
+	if (!netdev_uc_empty(dev)) {
+		netdev_for_each_uc_addr(ha, dev) {
+			pDevCtrl->umac->mdf_addr[i] = (ha->addr[0]<<8) |
+				ha->addr[1];
+			pDevCtrl->umac->mdf_addr[i+1] = ha->addr[2] << 24 |
+				ha->addr[3] << 16 |
+				ha->addr[4] << 8 |
+				ha->addr[5];
+			pDevCtrl->umac->mdf_ctrl |=
+				(1 << (MAX_MC_COUNT - mc));
+			i += 2;
+			mc++;
+		}
+	}
+	/* Multicast */
+	if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
+		return;
+
+	netdev_for_each_mc_addr(ha, dev) {
+		pDevCtrl->umac->mdf_addr[i] = ha->addr[0] << 8 |
+			ha->addr[1];
+		pDevCtrl->umac->mdf_addr[i+1] = ha->addr[2] << 24 |
+			ha->addr[3] << 16 | ha->addr[4] << 8 | ha->addr[5];
+		pDevCtrl->umac->mdf_ctrl |= (1 << (MAX_MC_COUNT - mc));
+		i += 2;
+		mc++;
+	}
+}
+/*
+ * Set the hardware MAC address.
+ */
+static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
+{
+	struct sockaddr *addr = p;
+
+	if (netif_running(dev))
+		return -EBUSY;
+
+	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
+
+	return 0;
+}
+/* --------------------------------------------------------------------------
+Name: bcmgenet_select_queue
+Purpose: select which xmit queue to use based on skb->queue_mapping.
+-------------------------------------------------------------------------- */
+static u16 __maybe_unused bcmgenet_select_queue(struct net_device *dev,
+		struct sk_buff *skb)
+{
+	/*
+	 * If multi-queue support is enabled, and NET_ACT_SKBEDIT is not
+	 * defined, this function simply returns current queue_mapping set
+	 * inside skb, this means other modules, (netaccel, for example),
+	 * must provide a mechanism to set the queue_mapping before trying
+	 * to send a packet.
+	 */
+	return skb->queue_mapping;
+}
+/* --------------------------------------------------------------------------
+Name: __bcmgenet_skb_destructor
+Purpose: For ring buffer, called after skb is consumed.
+-------------------------------------------------------------------------- */
+static void __bcmgenet_skb_destructor(struct sk_buff *skb)
+{
+	struct Enet_CB *cb;
+	int index, cbi;
+	volatile struct rDmaRingRegs *rDma_ring;
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(skb->dev);
+	struct status_64 *status = (struct status_64 *)skb->head;
+	index = status->reserved[0];
+	cbi = status->reserved[1];
+
+	rDma_ring = &pDevCtrl->rxDma->rDmaRings[index];
+	cb = pDevCtrl->rxRingCbs[index] + cbi;
+	dma_sync_single_for_device(&pDevCtrl->dev->dev,
+		cb->dma_addr, cb->dma_len, DMA_FROM_DEVICE);
+	/* Increment consumer index, if previous skb was not consumed.
+	 * this will cause buffer out of sync!! */
+	if ((rDma_ring->rdma_consumer_index & DMA_C_INDEX_MASK) == 0xFFFF)
+		rDma_ring->rdma_consumer_index = 0;
+	else
+		rDma_ring->rdma_consumer_index++;
+	skb->destructor = NULL;
+}
+/* --------------------------------------------------------------------------
+Name: __bcmgenet_alloc_skb_from_buf
+Purpose: Allocated an skb from exsiting buffer.
+-------------------------------------------------------------------------- */
+static struct sk_buff *__bcmgenet_alloc_skb_from_buf(unsigned char *buf,
+		int len, int headroom)
+{
+	struct skb_shared_info *shinfo;
+	struct sk_buff *skb;
+
+	skb = kmem_cache_alloc(skbuff_head_cache, GFP_ATOMIC);
+	if (!skb)
+		return NULL;
+	memset(skb, 0, offsetof(struct sk_buff, tail));
+	skb->truesize = len + sizeof(struct sk_buff);
+	atomic_set(&skb->users, 1);
+	skb->head = buf;
+	skb->data = buf;
+	skb_reset_tail_pointer(skb);
+	skb->end = skb->tail + len - sizeof(struct skb_shared_info);
+	/* FCLONE_ORIG tell kfree_skb() not to release data */
+	skb->cloned = SKB_FCLONE_ORIG;
+	/* FLONE_ORIG tells kfree_skb to free skb from skb head cache*/
+	skb->fclone = SKB_FCLONE_UNAVAILABLE;
+
+	skb_reserve(skb, headroom);
+	shinfo = skb_shinfo(skb);
+
+	/* Set dataref to 2, so upper layer won't free the data buffer */
+	atomic_set(&shinfo->dataref, 2);
+	shinfo->nr_frags = 0;
+	shinfo->gso_size = 0;
+	shinfo->gso_segs = 0;
+	shinfo->gso_type = 0;
+	shinfo->ip6_frag_id = 0;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)
+	shinfo->tx_flags = 0;
+#else
+	shinfo->tx_flags.flags = 0;
+#endif
+	shinfo->frag_list = NULL;
+	memset(&shinfo->hwtstamps, 0, sizeof(shinfo->hwtstamps));
+
+	return skb;
+}
+/* --------------------------------------------------------------------------
+Name: bcmgenet_alloc_txring_skb
+Purpose: Allocated skb for tx ring buffer.
+-------------------------------------------------------------------------- */
+struct sk_buff *bcmgenet_alloc_txring_skb(struct net_device *dev, int index)
+{
+	unsigned long flags, p_index = 0;
+	struct sk_buff *skb = NULL;
+	struct Enet_CB *cb;
+	volatile struct tDmaRingRegs *tDma_ring;
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+
+	if (!(pDevCtrl->txDma->tdma_ctrl &
+			(1 << (index + DMA_RING_BUF_EN_SHIFT)))) {
+		printk(KERN_ERR "Ring %d is not enabled\n", index);
+		BUG();
+	}
+	spin_lock_irqsave(&pDevCtrl->lock, flags);
+	if (pDevCtrl->txRingFreeBds[index] == 0) {
+		/*
+		 * This shouldn't happen, upper level should
+		 * check if the tx queue stopped before calling this.
+		 */
+		printk(KERN_ERR "%s:%d queue stopped!!\n", __func__, index);
+		spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+		return skb;
+	}
+	tDma_ring = &pDevCtrl->txDma->tDmaRings[index];
+	p_index = (DMA_P_INDEX_MASK & tDma_ring->tdma_producer_index);
+	/* P/C index is 16 bits, we do modulo of RING_SIZE */
+	p_index &= (pDevCtrl->txRingSize[index] - 1);
+
+	cb = pDevCtrl->txRingCBs[index] + p_index;
+	skb = __bcmgenet_alloc_skb_from_buf((unsigned char *)cb->BdAddr,
+			RX_BUF_LENGTH, 64);
+
+	cb->skb = skb;
+	spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+
+	return skb;
+}
+EXPORT_SYMBOL(bcmgenet_alloc_txring_skb);
+/* --------------------------------------------------------------------------
+Name: bcmgenet_get_txcb
+Purpose: return tx control data and increment write pointer.
+-------------------------------------------------------------------------- */
+static struct Enet_CB *bcmgenet_get_txcb(struct net_device *dev,
+		int *pos, int index)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	struct Enet_CB *txCBPtr = NULL;
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+	if (index == DESC_INDEX) {
+		txCBPtr = pDevCtrl->txCbs;
+		txCBPtr += (*pos - GENET_MQ_CNT*GENET_MQ_BD_CNT);
+		txCBPtr->BdAddr = &pDevCtrl->txBds[*pos];
+		if (*pos == (TOTAL_DESC - 1))
+			*pos = (GENET_MQ_CNT*GENET_MQ_BD_CNT);
+		else
+			*pos += 1;
+
+	} else {
+		txCBPtr = pDevCtrl->txRingCBs[index];
+		txCBPtr += (*pos - index*GENET_MQ_BD_CNT);
+		txCBPtr->BdAddr = &pDevCtrl->txBds[*pos];
+		if (*pos == (GENET_MQ_BD_CNT*(index+1) - 1))
+			*pos = GENET_MQ_BD_CNT * index;
+		else
+			*pos += 1;
+	}
+#else
+	txCBPtr = pDevCtrl->txCbs + *pos;
+	txCBPtr->BdAddr = &pDevCtrl->txBds[*pos];
+	/* Advancing local write pointer */
+	if (*pos == (TOTAL_DESC - 1))
+		*pos = 0;
+	else
+		*pos += 1;
+#endif
+
+	return txCBPtr;
+}
+/* --------------------------------------------------------------------------
+Name: bcmgenet_tx_reclaim
+Purpose: reclaim xmited skb
+-------------------------------------------------------------------------- */
+static void bcmgenet_tx_reclaim(struct net_device *dev, int index)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	unsigned int c_index;
+	struct Enet_CB *txCBPtr;
+	int lastTxedCnt = 0, lastCIndex = 0, nrTxBds = 0;
+
+	/* Compute how many buffers are transmited since last xmit call */
+	c_index = pDevCtrl->txDma->tDmaRings[index].tdma_consumer_index;
+
+
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+	if (index == DESC_INDEX) {
+		lastCIndex = pDevCtrl->txLastCIndex;
+		nrTxBds = GENET_DEFAULT_BD_CNT;
+	} else {
+		lastCIndex = pDevCtrl->txRingCIndex[index];
+		nrTxBds = GENET_MQ_BD_CNT;
+	}
+
+#else
+	lastCIndex = pDevCtrl->txLastCIndex;
+	nrTxBds = TOTAL_DESC;
+#endif
+	c_index &= (nrTxBds - 1);
+
+	if (c_index >= lastCIndex)
+		lastTxedCnt = c_index - lastCIndex;
+	else
+		lastTxedCnt = nrTxBds - lastCIndex + c_index;
+
+
+	TRACE(("%s: %s index=%d c_index=%d "
+			"lastTxedCnt=%d txLastCIndex=%d\n",
+			__func__, pDevCtrl->dev->name, index,
+			c_index, lastTxedCnt, lastCIndex));
+
+	/* Reclaim transmitted buffers */
+	while (lastTxedCnt-- > 0) {
+		if (index == DESC_INDEX)
+			txCBPtr = &pDevCtrl->txCbs[lastCIndex];
+		else
+			txCBPtr = pDevCtrl->txRingCBs[index] + lastCIndex;
+		if (txCBPtr->skb != NULL) {
+			dma_unmap_single(&pDevCtrl->dev->dev,
+					dma_unmap_addr(txCBPtr, dma_addr),
+					txCBPtr->skb->len,
+					DMA_TO_DEVICE);
+			dev_kfree_skb_any(txCBPtr->skb);
+			txCBPtr->skb = NULL;
+			dma_unmap_addr_set(txCBPtr, dma_addr, 0);
+		} else if (dma_unmap_addr(txCBPtr, dma_addr)) {
+			dma_unmap_page(&pDevCtrl->dev->dev,
+					dma_unmap_addr(txCBPtr, dma_addr),
+					dma_unmap_len(txCBPtr, dma_len),
+					DMA_TO_DEVICE);
+			dma_unmap_addr_set(txCBPtr, dma_addr, 0);
+		}
+		if (index == DESC_INDEX)
+			pDevCtrl->txFreeBds += 1;
+		else
+			pDevCtrl->txRingFreeBds[index] += 1;
+
+		if (lastCIndex == (nrTxBds - 1))
+			lastCIndex = 0;
+		else
+			lastCIndex++;
+	}
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+	if (index == DESC_INDEX) {
+		if (pDevCtrl->txFreeBds > (MAX_SKB_FRAGS + 1)
+			&& __netif_subqueue_stopped(dev, 0)) {
+			pDevCtrl->intrl2_0->cpu_mask_set |=
+				(UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE);
+			netif_wake_subqueue(dev, 0);
+		}
+		pDevCtrl->txLastCIndex = c_index;
+	} else{
+		if (pDevCtrl->txRingFreeBds[index] > (MAX_SKB_FRAGS + 1)
+			&& __netif_subqueue_stopped(dev, index+1)) {
+			pDevCtrl->intrl2_1->cpu_mask_set = (1 << index);
+			netif_wake_subqueue(dev, index+1);
+		}
+		pDevCtrl->txRingCIndex[index] = c_index;
+	}
+#else
+	if (pDevCtrl->txFreeBds > (MAX_SKB_FRAGS + 1)
+			&& netif_queue_stopped(dev)) {
+		/* Disable txdma bdone/pdone interrupt if we have free tx bds */
+		pDevCtrl->intrl2_0->cpu_mask_set |= (UMAC_IRQ_TXDMA_BDONE |
+				UMAC_IRQ_TXDMA_PDONE);
+		netif_wake_queue(dev);
+	}
+	pDevCtrl->txLastCIndex = c_index;
+#endif
+}
+
+/* --------------------------------------------------------------------------
+Name: bcmgenet_xmit
+Purpose: Send ethernet traffic
+-------------------------------------------------------------------------- */
+static int bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	volatile struct tDmaRingRegs *tDma_ring;
+	dma_addr_t mapping;
+	struct Enet_CB *txCBPtr;
+	unsigned int write_ptr = 0;
+	int i = 0;
+	unsigned long flags;
+	struct status_64 *Status = NULL;
+	int nr_frags = 0, index = DESC_INDEX;
+
+	spin_lock_irqsave(&pDevCtrl->lock, flags);
+
+	if (!pDevCtrl->clock_active) {
+		printk(KERN_WARNING "%s: transmitting with gated clock!\n",
+		       dev_name(&dev->dev));
+		dev_kfree_skb_any(skb);
+		spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+		return NETDEV_TX_OK;
+	}
+
+	if (skb && skb_padto(skb, ETH_ZLEN)) {
+		spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+		return NETDEV_TX_OK;
+	}
+
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+	if (skb) {
+		index = skb_get_queue_mapping(skb);
+		/*
+		* Mapping strategy:
+		* queue_mapping = 0, unclassfieid, packet xmited through ring16
+		* queue_mapping = 1, goes to ring 0. (highest priority queue)
+		* queue_mapping = 2, goes to ring 1.
+		* queue_mapping = 3, goes to ring 2.
+		* queue_mapping = 4, goes to ring 3.
+		*/
+		if (index == 0)
+			index = DESC_INDEX;
+		else
+			index -= 1;
+		if (index != DESC_INDEX && index > 3) {
+			printk(KERN_ERR "%s: skb->queue_mapping %d is invalid\n",
+					__func__, skb_get_queue_mapping(skb));
+			spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+			dev->stats.tx_errors++;
+			dev->stats.tx_dropped++;
+			return 1;
+		}
+		nr_frags = skb_shinfo(skb)->nr_frags;
+		if (index == DESC_INDEX) {
+			if (pDevCtrl->txFreeBds <= nr_frags + 1) {
+				netif_stop_subqueue(dev, 0);
+				spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+				printk(KERN_ERR "%s: tx ring %d full when queue awake\n",
+					__func__, index);
+				return 1;
+			}
+		} else if (pDevCtrl->txRingFreeBds[index] <= nr_frags + 1) {
+			netif_stop_subqueue(dev, index+1);
+			spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+			printk(KERN_ERR "%s: tx ring %d full when queue awake\n",
+					__func__, index);
+			return 1;
+		}
+	}
+	/* Reclaim xmited skb for each subqueue */
+	for (i = 0; i < GENET_MQ_CNT; i++)
+		bcmgenet_tx_reclaim(dev, i);
+#else
+	if (skb) {
+		nr_frags = skb_shinfo(skb)->nr_frags;
+		if (pDevCtrl->txFreeBds <= nr_frags + 1) {
+			netif_stop_queue(dev);
+			spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+			printk(KERN_ERR "%s: tx ring full when queue awake\n",
+				__func__);
+			return 1;
+		}
+	}
+#endif
+
+	if (!skb) {
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+		for (i = 0; i < GENET_MQ_CNT; i++)
+			bcmgenet_tx_reclaim(dev, i);
+#endif
+		bcmgenet_tx_reclaim(dev, DESC_INDEX);
+		spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+		return 0;
+	}
+	/*
+	 * reclaim xmited skb every 8 packets.
+	 */
+	if ((index == DESC_INDEX) &&
+		(pDevCtrl->txFreeBds < pDevCtrl->nrTxBds - 8))
+		bcmgenet_tx_reclaim(dev, index);
+
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+	if ((index != DESC_INDEX) && (pDevCtrl->txRingFreeBds[index]
+			< GENET_MQ_BD_CNT - 8))
+		bcmgenet_tx_reclaim(dev, index);
+#endif
+
+	tDma_ring = &pDevCtrl->txDma->tDmaRings[index];
+	/*
+	 * If 64 byte status block enabled, must make sure skb has
+	 * enough headroom for us to insert 64B status block.
+	 */
+	if (GENET_TBUF_CTRL(pDevCtrl) & RBUF_64B_EN) {
+		if (likely(skb_headroom(skb) < 64)) {
+			struct sk_buff *new_skb;
+			new_skb = skb_realloc_headroom(skb, 64);
+			if (new_skb  == NULL) {
+				dev_kfree_skb(skb);
+				dev->stats.tx_errors++;
+				dev->stats.tx_dropped++;
+				spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+				return 0;
+			} else if (skb->sk) {
+				skb_set_owner_w(new_skb, skb->sk);
+			}
+			dev_kfree_skb(skb);
+			skb = new_skb;
+		}
+		skb_push(skb, 64);
+		Status = (struct status_64 *)skb->data;
+	}
+	write_ptr = (DMA_RW_POINTER_MASK & tDma_ring->tdma_write_pointer) >> 1;
+
+	/* Obtain transmit control block */
+	txCBPtr = bcmgenet_get_txcb(dev, &write_ptr, index);
+
+	if (unlikely(!txCBPtr))
+		BUG();
+
+	txCBPtr->skb = skb;
+
+	if ((skb->ip_summed  == CHECKSUM_PARTIAL) &&
+			(GENET_TBUF_CTRL(pDevCtrl) & RBUF_64B_EN)) {
+		u16 offset;
+		offset = skb->csum_start - skb_headroom(skb) - 64;
+		/* Insert 64B TSB and set the flag */
+		Status->tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
+			(offset + skb->csum_offset) |
+			STATUS_TX_CSUM_LV;
+	}
+
+	/*
+	 * Add the buffer to the ring.
+	 * Set addr and length of DMA BD to be transmitted.
+	 */
+	if (!nr_frags) {
+		mapping = dma_map_single(&pDevCtrl->dev->dev,
+				skb->data, skb->len, DMA_TO_DEVICE);
+		if (dma_mapping_error(&pDevCtrl->dev->dev, mapping)) {
+			dev_err(&pDevCtrl->dev->dev, "Tx DMA map failed\n");
+			dev_kfree_skb(skb);
+			spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+			return 0;
+		}
+		dma_unmap_addr_set(txCBPtr, dma_addr, mapping);
+		dma_unmap_len_set(txCBPtr, dma_len, skb->len);
+		txCBPtr->BdAddr->address = mapping;
+		txCBPtr->BdAddr->length_status = (
+			((unsigned long)((skb->len < ETH_ZLEN) ?
+			ETH_ZLEN : skb->len)) << 16) | DMA_SOP | DMA_EOP |
+			(DMA_TX_QTAG_MASK << DMA_TX_QTAG_SHIFT) |
+			DMA_TX_APPEND_CRC;
+
+		if (skb->ip_summed  == CHECKSUM_PARTIAL)
+			txCBPtr->BdAddr->length_status |= DMA_TX_DO_CSUM;
+
+#ifdef CONFIG_BCMGENET_DUMP_DATA
+		printk(KERN_NOTICE "%s: data 0x%p len %d",
+				__func__, skb->data, skb->len);
+		print_hex_dump(KERN_NOTICE, "", DUMP_PREFIX_ADDRESS,
+				16, 1, skb->data, skb->len, 0);
+#endif
+		/* Decrement total BD count and advance our write pointer */
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+		if (index == DESC_INDEX)
+			pDevCtrl->txFreeBds -= 1;
+		else
+			pDevCtrl->txRingFreeBds[index] -= 1;
+#else
+		pDevCtrl->txFreeBds -= 1;
+#endif
+		/* advance producer index and write pointer.*/
+		tDma_ring->tdma_producer_index += 1;
+		tDma_ring->tdma_write_pointer = (write_ptr << 1);
+		/* update stats */
+		dev->stats.tx_bytes += ((skb->len < ETH_ZLEN) ?
+				ETH_ZLEN : skb->len);
+		dev->stats.tx_packets++;
+
+	} else {
+		/* xmit head */
+		mapping = dma_map_single(&pDevCtrl->dev->dev,
+				skb->data, skb_headlen(skb), DMA_TO_DEVICE);
+		if (dma_mapping_error(&pDevCtrl->dev->dev, mapping)) {
+			dev_kfree_skb(skb);
+			dev_err(&pDevCtrl->dev->dev, "Tx DMA map failed\n");
+			spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+			return 0;
+		}
+		dma_unmap_addr_set(txCBPtr, dma_addr, mapping);
+		dma_unmap_len_set(txCBPtr, dma_len, skb->len);
+		txCBPtr->BdAddr->address = mapping;
+		txCBPtr->BdAddr->length_status = (skb_headlen(skb) << 16) |
+			(DMA_TX_QTAG_MASK << DMA_TX_QTAG_SHIFT) |
+			DMA_SOP | DMA_TX_APPEND_CRC;
+
+		if (skb->ip_summed  == CHECKSUM_PARTIAL)
+			txCBPtr->BdAddr->length_status |= DMA_TX_DO_CSUM;
+
+#ifdef CONFIG_BCMGENET_DUMP_DATA
+		printk(KERN_NOTICE "%s: frag head len %d",
+				__func__, skb_headlen(skb));
+		print_hex_dump(KERN_NOTICE, "", DUMP_PREFIX_ADDRESS,
+				16, 1, skb->data, skb_headlen(skb), 0);
+#endif
+		/* Decrement total BD count and advance our write pointer */
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+		if (index == DESC_INDEX)
+			pDevCtrl->txFreeBds -= 1;
+		else
+			pDevCtrl->txRingFreeBds[index] -= 1;
+#else
+		pDevCtrl->txFreeBds -= 1;
+#endif
+		/* advance producer index and write pointer.*/
+		tDma_ring->tdma_producer_index += 1;
+		tDma_ring->tdma_write_pointer = (write_ptr << 1);
+		dev->stats.tx_bytes += skb_headlen(skb);
+
+		/* xmit fragment */
+		for (i = 0; i < nr_frags; i++) {
+			skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
+
+			txCBPtr = bcmgenet_get_txcb(dev, &write_ptr, index);
+
+			if (unlikely(!txCBPtr))
+				BUG();
+			txCBPtr->skb = NULL;
+
+			mapping = skb_frag_dma_map(&pDevCtrl->dev->dev, frag, 0,
+				skb_frag_size(frag), DMA_TO_DEVICE);
+			if (dma_mapping_error(&pDevCtrl->dev->dev, mapping)) {
+				printk(KERN_ERR "%s: Tx DMA map failed\n",
+						__func__);
+				/*TODO: Handle frag failure.*/
+				spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+				return 0;
+			}
+			dma_unmap_addr_set(txCBPtr, dma_addr, mapping);
+			dma_unmap_len_set(txCBPtr, dma_len, frag->size);
+			txCBPtr->BdAddr->address = mapping;
+#ifdef CONFIG_BCMGENET_DUMP_DATA
+			printk(KERN_NOTICE "%s: frag%d len %d",
+					__func__, i, frag->size);
+			print_hex_dump(KERN_NOTICE, "", DUMP_PREFIX_ADDRESS,
+				16, 1,
+				skb_frag_address(frag),
+				skb_frag_size(frag), 0);
+#endif
+			txCBPtr->BdAddr->length_status =
+					((unsigned long)frag->size << 16) |
+					(DMA_TX_QTAG_MASK << DMA_TX_QTAG_SHIFT);
+			if (i == nr_frags - 1)
+				txCBPtr->BdAddr->length_status |= DMA_EOP;
+
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+			if (index == DESC_INDEX)
+				pDevCtrl->txFreeBds -= 1;
+			else
+				pDevCtrl->txRingFreeBds[index] -= 1;
+#else
+			pDevCtrl->txFreeBds -= 1;
+#endif
+			/* advance producer index and write pointer.*/
+			tDma_ring->tdma_producer_index += 1;
+			tDma_ring->tdma_write_pointer = (write_ptr << 1);
+			/* update stats */
+			dev->stats.tx_bytes += frag->size;
+		}
+		dev->stats.tx_packets++;
+	}
+
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+	if (index == DESC_INDEX) {
+		if (pDevCtrl->txFreeBds <= (MAX_SKB_FRAGS + 1)) {
+			netif_stop_subqueue(dev, 0);
+			pDevCtrl->intrl2_0->cpu_mask_clear =
+				UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE;
+
+		}
+	} else if (pDevCtrl->txRingFreeBds[index] <= (MAX_SKB_FRAGS + 1)) {
+		netif_stop_subqueue(dev, index+1);
+		pDevCtrl->intrl2_1->cpu_mask_clear = (1 << index);
+	}
+#else
+	if (pDevCtrl->txFreeBds <= (MAX_SKB_FRAGS + 1)) {
+		/* Enable Tx bdone/pdone interrupt !*/
+		pDevCtrl->intrl2_0->cpu_mask_clear |= UMAC_IRQ_TXDMA_BDONE |
+			UMAC_IRQ_TXDMA_PDONE;
+		netif_stop_queue(dev);
+	}
+#endif
+	dev->trans_start = jiffies;
+
+	spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+
+	return 0;
+}
+/* --------------------------------------------------------------------------
+Name: bcmgenet_tx_ring_reclaim
+Purpose: reclaim xmited skb for a ring buffer
+-------------------------------------------------------------------------- */
+static void bcmgenet_tx_ring_reclaim(struct net_device *dev, int index,
+		unsigned int p_index, unsigned int c_index)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	struct Enet_CB *txCBPtr;
+	int lastTxedCnt = 0, lastCIndex = 0;
+	struct sk_buff *skb;
+
+	/* Compute how many buffers are transmited since last xmit call */
+
+	if (c_index >= pDevCtrl->txRingCIndex[index]) {
+		/* index not wrapped */
+		lastTxedCnt = c_index - pDevCtrl->txRingCIndex[index];
+	} else {
+		/* index wrapped */
+		lastTxedCnt = pDevCtrl->txRingSize[index] -
+			pDevCtrl->txRingCIndex[index] + c_index;
+	}
+	TRACE(("%s: ring %d: p_index=%d c_index=%d"
+			"lastTxedCnt=%d txLastCIndex=%d\n",
+			__func__, index, p_index, c_index,
+			lastTxedCnt, pDevCtrl->txRingCIndex[index]));
+
+	pDevCtrl->txRingFreeBds[index] += lastTxedCnt;
+
+	lastCIndex = pDevCtrl->txRingCIndex[index];
+	pDevCtrl->txRingCIndex[index] = c_index;
+
+	/* free xmited skb */
+	while (lastTxedCnt-- > 0) {
+		txCBPtr = pDevCtrl->txRingCBs[index] + lastCIndex;
+		skb = txCBPtr->skb;
+		if (skb != NULL) {
+			/*
+			 * This will consume skb, we don't want to run
+			 * destructor which is to drop the skb.
+			 */
+			if (skb->destructor != NULL)
+				skb->destructor = NULL;
+			/* make sure dev_kfree_skb_any() don't free mem. */
+			if ((atomic_read(&skb_shinfo(skb)->dataref) &
+						SKB_DATAREF_MASK) < 2)
+				atomic_set(&(skb_shinfo(skb)->dataref), 2);
+			dev_kfree_skb_any(skb);
+			txCBPtr->skb = NULL;
+		}
+		if (lastCIndex == (pDevCtrl->txRingSize[index] - 1))
+			lastCIndex = 0;
+		else
+			lastCIndex++;
+	}
+	if (pDevCtrl->txRingFreeBds[index] > 0 &&
+			netif_queue_stopped(dev)) {
+		/*
+		 * Disable txdma multibuf done interrupt for this ring
+		 * since we have free tx bds.
+		 */
+		pDevCtrl->intrl2_1->cpu_mask_set |= (1 << index);
+		netif_wake_queue(dev);
+	}
+}
+/* --------------------------------------------------------------------------
+Name: bcmgenet_ring_xmit
+Purpose: Send ethernet traffic through ring buffer
+-------------------------------------------------------------------------- */
+int __maybe_unused bcmgenet_ring_xmit(struct sk_buff *skb,
+		struct net_device *dev, int index, int drop)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	volatile struct tDmaRingRegs *tDma_ring;
+	struct Enet_CB *txCBPtr;
+	struct status_64 *Status;
+	unsigned int p_index = 0, c_index = 0;
+
+	/* Compute how many buffers are transmited since last xmit call */
+	tDma_ring = &pDevCtrl->txDma->tDmaRings[index];
+	p_index = (DMA_P_INDEX_MASK & tDma_ring->tdma_producer_index);
+	c_index = (DMA_C_INDEX_MASK & tDma_ring->tdma_consumer_index);
+
+	/* P/C index is 16 bits, we do modulo of RING_SIZE */
+	p_index &= (pDevCtrl->txRingSize[index] - 1);
+	c_index &= (pDevCtrl->txRingSize[index] - 1);
+
+	bcmgenet_tx_ring_reclaim(dev, index, p_index, c_index);
+
+	if (!skb)
+		return 0;
+
+	if (skb_padto(skb, ETH_ZLEN))
+		return 0;
+
+	/* Obtain a tx control block */
+	txCBPtr = pDevCtrl->txRingCBs[index] + p_index;
+	txCBPtr->skb = skb;
+
+	TRACE(("%s: txCBPtr=0x%08lx skb=0x%08lx skb->head=0x%08lx\n",
+		__func__,
+		(unsigned long)txCBPtr,
+		(unsigned long)skb,
+		(unsigned long)skb->head));
+
+	/*
+	 * Make sure we have headroom for us to insert 64B status block.
+	 */
+	if (unlikely(skb_headroom(skb) < 64)) {
+		printk(KERN_ERR "no enough headroom for TSB (head=0x%08x)\n",
+				(unsigned int)skb->head);
+		BUG();
+	}
+
+	Status = (struct status_64 *)skb->head;
+	Status->length_status = ((unsigned long)((skb->len < ETH_ZLEN) ?
+				ETH_ZLEN : skb->len)) << 16;
+	Status->length_status += (sizeof(struct status_64) << 16);
+	Status->length_status |= DMA_SOP | DMA_EOP | DMA_TX_APPEND_CRC;
+	if ((skb->ip_summed  == CHECKSUM_PARTIAL) &&
+			(GENET_TBUF_CTRL(pDevCtrl) & RBUF_64B_EN)) {
+		u16 offset;
+		offset = skb->csum_start - skb_headroom(skb) - 64;
+		/* Insert 64B TSB and set the flag */
+		Status->tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
+			(offset + skb->csum_offset) | STATUS_TX_CSUM_LV;
+		Status->length_status |= DMA_TX_DO_CSUM;
+		TRACE(("Tx Hw Csum: head=0x%08x data=0x%08x "
+				"csum_start=%d csum_offset=%d\n",
+				(unsigned int)skb->head,
+				(unsigned int)skb->data,
+				skb->csum_start,
+				skb->csum_offset));
+	} else {
+		Status->tx_csum_info = 0;
+	}
+	/* Default QTAG for MoCA */
+	Status->length_status |= (DMA_TX_QTAG_MASK << DMA_TX_QTAG_SHIFT);
+
+	txCBPtr->dma_addr = dma_map_single(&pDevCtrl->dev->dev,
+			skb->head, skb->len + 64, DMA_TO_DEVICE);
+
+#ifdef CONFIG_BCMGENET_DUMP_DATA
+	printk(KERN_NOTICE "bcmgenet_xmit: len %d", skb->len);
+	print_hex_dump(KERN_NOTICE, "", DUMP_PREFIX_ADDRESS,
+				16, 1, skb->head, skb->len + 64, 0);
+#endif
+
+	/*
+	 * Decrement total BD count and advance our
+	 * write pointer/producer index
+	 */
+	pDevCtrl->txRingFreeBds[index] -= 1;
+
+	if (likely(txCBPtr->dma_addr == tDma_ring->tdma_write_pointer)) {
+		unsigned long start_addr = tDma_ring->tdma_start_addr;
+		if (unlikely(drop)) {
+			/*
+			 * Don't xmit current packet pointed by read_pointer,
+			 * there is no such mechanism in GENET's TDMA, so we
+			 * disable TDMA and increment consumer index/read
+			 * pointer to skip this packet as a work around.
+			 */
+			pDevCtrl->txDma->tdma_ctrl &= ~DMA_EN;
+			tDma_ring->tdma_consumer_index += 1;
+			if ((tDma_ring->tdma_read_pointer + RX_BUF_LENGTH) >
+				tDma_ring->tdma_end_addr) {
+				tDma_ring->tdma_read_pointer = start_addr;
+			} else {
+				tDma_ring->tdma_read_pointer += RX_BUF_LENGTH;
+			}
+		}
+		/* advance producer index and write pointer.*/
+		tDma_ring->tdma_producer_index += 1;
+		if ((tDma_ring->tdma_write_pointer + RX_BUF_LENGTH) >
+			tDma_ring->tdma_end_addr) {
+			tDma_ring->tdma_write_pointer = start_addr;
+		} else {
+			tDma_ring->tdma_write_pointer += RX_BUF_LENGTH;
+		}
+		if (unlikely(drop))
+			pDevCtrl->txDma->tdma_ctrl |= DMA_EN;
+	} else {
+		/* ooops! how can we get here ?*/
+		BUG();
+	}
+
+	if (pDevCtrl->txRingFreeBds[index] == 0) {
+		TRACE(("%s: no xmit queue space, stopping queue\n", dev->name));
+		/* Enable Tx bdone/pdone interrupt !*/
+		pDevCtrl->intrl2_0->cpu_mask_clear |= (1 << index);
+		netif_stop_subqueue(dev, index);
+	}
+
+	if (!drop) {
+		/* update stats */
+		dev->stats.tx_bytes += ((skb->len < ETH_ZLEN) ?
+			ETH_ZLEN : skb->len);
+		dev->stats.tx_packets++;
+	}
+	dev->trans_start = jiffies;
+	return 0;
+}
+/* NAPI polling method*/
+static int bcmgenet_poll(struct napi_struct *napi, int budget)
+{
+	struct BcmEnet_devctrl *pDevCtrl = container_of(napi,
+			struct BcmEnet_devctrl, napi);
+	volatile struct intrl2Regs *intrl2 = pDevCtrl->intrl2_0;
+	volatile struct rDmaRingRegs *rDma_desc;
+	unsigned int work_done;
+	work_done = bcmgenet_desc_rx(pDevCtrl, budget);
+
+	/* tx reclaim */
+	/*bcmgenet_xmit(NULL, pDevCtrl->dev);*/
+	/* Allocate new SKBs for the BD ring */
+	assign_rx_buffers(pDevCtrl);
+	/* Advancing our read pointer and consumer index*/
+	rDma_desc = &pDevCtrl->rxDma->rDmaRings[DESC_INDEX];
+	rDma_desc->rdma_consumer_index += work_done;
+	rDma_desc->rdma_read_pointer += (work_done << 1);
+	rDma_desc->rdma_read_pointer &= ((TOTAL_DESC << 1)-1);
+	if (work_done < budget) {
+		napi_complete(napi);
+		intrl2->cpu_mask_clear |= UMAC_IRQ_RXDMA_BDONE;
+	}
+	return work_done;
+}
+/*
+ * NAPI polling for ring buffer.
+ */
+static int bcmgenet_ring_poll(struct napi_struct *napi, int budget)
+{
+	struct BcmEnet_devctrl *pDevCtrl = container_of(napi,
+			struct BcmEnet_devctrl, ring_napi);
+	volatile struct intrl2Regs *intrl2 = pDevCtrl->intrl2_1;
+	unsigned int work_done;
+	work_done = bcmgenet_ring_rx(pDevCtrl, budget);
+
+	/* tx reclaim */
+	bcmgenet_ring_xmit(NULL, pDevCtrl->dev, 0, 0);
+	if (work_done < budget) {
+		unsigned long bits;
+		napi_complete(napi);
+		bits = (pDevCtrl->rxDma->rdma_ctrl >> 1) << 16;
+		intrl2->cpu_mask_clear |= bits;
+	}
+	return work_done;
+}
+/*
+ * Interrupt bottom half
+ */
+static void bcmgenet_irq_task(struct work_struct *work)
+{
+	struct BcmEnet_devctrl *pDevCtrl = container_of(
+			work, struct BcmEnet_devctrl, bcmgenet_irq_work);
+	struct net_device *dev;
+
+	dev = pDevCtrl->dev;
+
+	TRACE(("%s\n", __func__));
+	/* Cable plugged/unplugged event */
+	if (pDevCtrl->irq0_stat & UMAC_IRQ_PHY_DET_R) {
+		pDevCtrl->irq0_stat &= ~UMAC_IRQ_PHY_DET_R;
+		printk(KERN_CRIT "%s cable plugged in, powering up\n",
+				pDevCtrl->dev->name);
+		bcmgenet_power_up(pDevCtrl, GENET_POWER_CABLE_SENSE);
+	} else if (pDevCtrl->irq0_stat & UMAC_IRQ_PHY_DET_F) {
+		pDevCtrl->irq0_stat &= ~UMAC_IRQ_PHY_DET_F;
+		printk(KERN_CRIT "%s cable unplugged, powering down\n",
+				pDevCtrl->dev->name);
+		bcmgenet_power_down(pDevCtrl, GENET_POWER_CABLE_SENSE);
+	}
+	if (pDevCtrl->irq0_stat & UMAC_IRQ_MPD_R) {
+		pDevCtrl->irq0_stat &= ~UMAC_IRQ_MPD_R;
+		printk(KERN_CRIT "%s magic packet detected, waking up\n",
+				pDevCtrl->dev->name);
+		/* disable mpd interrupt */
+		pDevCtrl->intrl2_0->cpu_mask_set |= UMAC_IRQ_MPD_R;
+		/* disable CRC forward.*/
+		pDevCtrl->umac->cmd &= ~CMD_CRC_FWD;
+		if (pDevCtrl->dev_asleep)
+			bcmgenet_power_up(pDevCtrl, GENET_POWER_WOL_MAGIC);
+
+	} else if (pDevCtrl->irq0_stat & (UMAC_IRQ_HFB_SM | UMAC_IRQ_HFB_MM)) {
+		pDevCtrl->irq0_stat &= ~(UMAC_IRQ_HFB_SM | UMAC_IRQ_HFB_MM);
+		printk(KERN_CRIT "%s ACPI pattern matched, waking up\n",
+				pDevCtrl->dev->name);
+		/* disable HFB match interrupts */
+		pDevCtrl->intrl2_0->cpu_mask_set |= (UMAC_IRQ_HFB_SM |
+				UMAC_IRQ_HFB_MM);
+		if (pDevCtrl->dev_asleep)
+			bcmgenet_power_up(pDevCtrl, GENET_POWER_WOL_ACPI);
+	}
+
+	/* Link UP/DOWN event */
+	if (pDevCtrl->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN)) {
+		pDevCtrl->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN);
+		bcmgenet_mii_setup(pDevCtrl->dev, 0);
+	}
+
+	/* Re-enable interrupts */
+	pDevCtrl->intrl2_0->cpu_mask_clear = ~pDevCtrl->int_mask;
+}
+/*
+ * bcmgenet_ring_rx: ring buffer rx function.
+ */
+static unsigned int bcmgenet_ring_rx(void *ptr, unsigned int budget)
+{
+	struct BcmEnet_devctrl *pDevCtrl = ptr;
+	volatile struct status_64 *status;
+	volatile struct rDmaRingRegs *rDma_ring;
+	int i, len, rx_discard_flag = 0;
+	struct Enet_CB *cb;
+	struct sk_buff *skb;
+	unsigned long dmaFlag;
+	unsigned int rxpktprocessed = 0, pktcnt = 0, retvalue = 0;
+	unsigned int read_ptr = 0, write_ptr = 0, p_index = 0, c_index = 0;
+
+	TRACE(("%s: ifindex=%d irq_stat=0x%08x\n",
+		__func__, pDevCtrl->dev->ifindex, pDevCtrl->irq1_stat));
+
+	/* loop for each ring */
+	for (i = 0; i < GENET_RX_RING_COUNT; i++) {
+		/* Skip if this ring is not eanbled*/
+		if (!(pDevCtrl->rxDma->rdma_ctrl &
+				(1 << (i + DMA_RING_BUF_EN_SHIFT))))
+			continue;
+		/* Skip if not outstanding packet for this ring*/
+		if (!(pDevCtrl->irq1_stat & (1 << (16 + i))))
+			continue;
+
+		rDma_ring = &pDevCtrl->rxDma->rDmaRings[i];
+		write_ptr = rDma_ring->rdma_write_pointer;
+		read_ptr =  rDma_ring->rdma_read_pointer;
+		p_index = rDma_ring->rdma_producer_index;
+		p_index &= DMA_P_INDEX_MASK;
+		c_index = rDma_ring->rdma_consumer_index;
+		c_index &= DMA_C_INDEX_MASK;
+
+		if (p_index < c_index) {
+			/* index wrapped */
+			if ((DMA_P_INDEX_MASK - c_index + p_index) ==
+					(pDevCtrl->rxRingSize[i] - 1))
+				rx_discard_flag = 1;
+		} else if (p_index > c_index) {
+			/* index not wrapped */
+			if (p_index - c_index == pDevCtrl->rxRingSize[i])
+				rx_discard_flag = 1;
+		}
+
+		if (rx_discard_flag) {
+			int discard_cnt = rDma_ring->rdma_producer_index >> 16;
+			/* Report rx overrun errors */
+			pDevCtrl->dev->stats.rx_over_errors += discard_cnt -
+				pDevCtrl->rxRingDiscCnt[i];
+			pDevCtrl->rxRingDiscCnt[i] = discard_cnt;
+		}
+
+		/*
+		 * We can't use produer/consumer index to compute how
+		 * many outstanding packets are there, because we are not
+		 * advancing consumer index right after packets are moved
+		 * out of DMA. So we use read/write pointer for the math.
+		 */
+		if (write_ptr < read_ptr) {
+			/* pointer wrapped */
+			pktcnt = (rDma_ring->rdma_end_addr + 1 - read_ptr) >>
+				(RX_BUF_BITS - 1);
+			pktcnt += (write_ptr - rDma_ring->rdma_start_addr) >>
+				(RX_BUF_BITS - 1);
+		} else if (write_ptr > read_ptr) {
+			/* pointer not wrapped */
+			pktcnt = (write_ptr - read_ptr) >> (RX_BUF_BITS - 1);
+		} else if (write_ptr == read_ptr && p_index != c_index) {
+			/* overflowed, some packets are discarded by DMA */
+			pktcnt = rDma_ring->rdma_ring_buf_size >> 16;
+		}
+
+		TRACE(("%s: p_index=%d c_index=%d write_ptr=0x%08x "
+				"read_ptr=0x%08x pktcnt=%d\n",
+				__func__, p_index, c_index, write_ptr,
+				read_ptr, pktcnt));
+
+		/*Start processing packets */
+		while ((rxpktprocessed < pktcnt) &&
+				(rxpktprocessed < budget)) {
+
+			unsigned int cbi;
+			/*
+			 * Find out Which buffer in the ring are we pointing to.
+			 */
+			cbi = (read_ptr - rDma_ring->rdma_start_addr) >>
+				(RX_BUF_BITS - 1);
+			cb = pDevCtrl->rxRingCbs[i] + cbi;
+			dma_sync_single_for_cpu(&pDevCtrl->dev->dev,
+					cb->dma_addr, 64, DMA_FROM_DEVICE);
+
+			status = (struct status_64 *)cb->BdAddr;
+			dmaFlag = status->length_status & 0xffff;
+			len = status->length_status >> 16;
+			dma_sync_single_for_cpu(&pDevCtrl->dev->dev,
+					cb->dma_addr + 64, len,
+					DMA_FROM_DEVICE);
+
+			/*
+			 * Advancing our read pointer.
+			 */
+			if (read_ptr + RX_BUF_LENGTH > rDma_ring->rdma_end_addr)
+				read_ptr = rDma_ring->rdma_start_addr;
+			else
+				read_ptr += RX_BUF_LENGTH;
+			rDma_ring->rdma_read_pointer = read_ptr;
+			/*
+			 * per packet processing
+			 */
+			skb = __bcmgenet_alloc_skb_from_buf(
+				(unsigned char *)cb->BdAddr, RX_BUF_LENGTH, 0);
+			skb->destructor = &__bcmgenet_skb_destructor;
+			status->reserved[0] = i;	/* ring index */
+			status->reserved[1] = cbi;	/* cb index */
+
+			rxpktprocessed++;
+			BUG_ON(skb == NULL);
+
+			TRACE(("%s: cbi=%d skb=0x%08x head=0x%08x dataref=%d\n",
+				__func__, cbi,
+				(unsigned int)skb, (unsigned int)skb->head,
+				(atomic_read(&skb_shinfo(skb)->dataref) &
+				 SKB_DATAREF_MASK)));
+			/* report errors */
+			if (unlikely(!(dmaFlag & DMA_EOP) ||
+					!(dmaFlag & DMA_SOP))) {
+				/* probably can't do this for scater gather ?*/
+				printk(KERN_WARNING "Droping fragmented packet!\n");
+				pDevCtrl->dev->stats.rx_dropped++;
+				pDevCtrl->dev->stats.rx_errors++;
+				dev_kfree_skb_any(cb->skb);
+				cb->skb = NULL;
+				continue;
+			}
+			if (unlikely(dmaFlag & (DMA_RX_CRC_ERROR |
+							DMA_RX_OV |
+							DMA_RX_NO |
+							DMA_RX_LG |
+							DMA_RX_RXER))) {
+				TRACE(("ERROR: dmaFlag=0x%lx\n", dmaFlag));
+				if (dmaFlag & DMA_RX_CRC_ERROR)
+					pDevCtrl->dev->stats.rx_crc_errors++;
+				if (dmaFlag & DMA_RX_OV)
+					pDevCtrl->dev->stats.rx_over_errors++;
+				if (dmaFlag & DMA_RX_NO)
+					pDevCtrl->dev->stats.rx_frame_errors++;
+				if (dmaFlag & DMA_RX_LG)
+					pDevCtrl->dev->stats.rx_length_errors++;
+
+				pDevCtrl->dev->stats.rx_dropped++;
+				pDevCtrl->dev->stats.rx_errors++;
+				dev_kfree_skb_any(cb->skb);
+				cb->skb = NULL;
+				continue;
+			} /* error packet */
+
+			skb_put(skb, len);
+			/* we must have 64B rx status block enabled.*/
+			if (pDevCtrl->rbuf->rbuf_chk_ctrl & RBUF_RXCHK_EN) {
+				if (status->rx_csum & STATUS_RX_CSUM_OK) {
+					skb->csum = status->rx_csum ;
+					/*
+					 * Should swap bytes based on
+					 * rbuf->endian_ctrl?
+					 */
+					skb->csum = swab16(skb->csum);
+				}
+				skb->ip_summed = CHECKSUM_COMPLETE;
+			}
+			/*
+			 * TODO: check filter index and compare with ring index
+			 * Report error if not matched
+			 */
+			skb_pull(skb, 64);
+			len -= 64;
+
+			if (pDevCtrl->bIPHdrOptimize) {
+				skb_pull(skb, 2);
+				len -= 2;
+			}
+
+			if (pDevCtrl->umac->cmd & CMD_CRC_FWD) {
+				skb_trim(skb, len - 4);
+				len -= 4;
+			}
+#ifdef CONFIG_BCMGENET_DUMP_DATA
+			printk(KERN_NOTICE "%s:\n", __func__);
+			print_hex_dump(KERN_NOTICE, "", DUMP_PREFIX_ADDRESS,
+				16, 1, skb->data, skb->len, 0);
+#endif
+			/*
+			 * Finish setting up the received SKB and send it
+			 * to the kernel
+			 */
+			skb->dev = pDevCtrl->dev;
+			skb->protocol = eth_type_trans(skb, pDevCtrl->dev);
+			pDevCtrl->dev->stats.rx_packets++;
+			pDevCtrl->dev->stats.rx_bytes += len;
+			if (dmaFlag & DMA_RX_MULT)
+				pDevCtrl->dev->stats.multicast++;
+
+			skb->queue_mapping = i;
+			/* Notify kernel */
+			netif_receive_skb(skb);
+			TRACE(("pushed up to kernel\n"));
+
+		} /* packet process loop */
+
+	} /* ring index loop */
+
+	if (retvalue == 0)
+		retvalue = rxpktprocessed;
+
+	return retvalue;;
+}
+/*
+ * bcmgenet_isr1: interrupt handler for ring buffer.
+ */
+static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
+{
+	struct BcmEnet_devctrl *pDevCtrl = dev_id;
+	volatile struct intrl2Regs *intrl2 = pDevCtrl->intrl2_1;
+	unsigned int index;
+	unsigned long flags;
+
+	/* Save irq status for bottom-half processing. */
+	pDevCtrl->irq1_stat = intrl2->cpu_stat & ~intrl2->cpu_mask_status;
+	/* clear inerrupts*/
+	intrl2->cpu_clear |= pDevCtrl->irq1_stat;
+
+	TRACE(("%s: IRQ=0x%x\n", __func__, pDevCtrl->irq1_stat));
+	/*
+	 * Check the MBDONE interrupts.
+	 * packet is done, reclaim descriptors
+	 */
+	if (pDevCtrl->irq1_stat & 0x0000ffff) {
+		index = 0;
+		for (index = 0; index < 16; index++) {
+			if (pDevCtrl->irq1_stat & (1<<index)) {
+				spin_lock_irqsave(&pDevCtrl->lock, flags);
+				bcmgenet_tx_reclaim(pDevCtrl->dev, index);
+				spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+			}
+		}
+	}
+
+	if (pDevCtrl->irq1_stat & 0xffff0000) {
+		/*
+		 * We use NAPI here, because of the fact that we are NOT
+		 * advancing consumer index right after data moved out of
+		 * DMA, instead we advance it only when we found out upper
+		 * level has consumed it.
+		 */
+		if (likely(napi_schedule_prep(&pDevCtrl->ring_napi))) {
+			/* Disable all rx ring interrupt */
+			intrl2->cpu_mask_set |= 0xffff0000;
+			__napi_schedule(&pDevCtrl->ring_napi);
+		}
+	}
+	return IRQ_HANDLED;
+}
+/*
+ * bcmgenet_isr0: Handle various interrupts.
+ */
+static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
+{
+	struct BcmEnet_devctrl *pDevCtrl = dev_id;
+	volatile struct intrl2Regs *intrl2 = pDevCtrl->intrl2_0;
+
+	/* Save irq status for bottom-half processing. */
+	pDevCtrl->irq0_stat = intrl2->cpu_stat & ~intrl2->cpu_mask_status;
+	/* clear inerrupts*/
+	intrl2->cpu_clear |= pDevCtrl->irq0_stat;
+
+	TRACE(("IRQ=0x%x\n", pDevCtrl->irq0_stat));
+#ifndef CONFIG_BCMGENET_RX_DESC_THROTTLE
+	if (pDevCtrl->irq0_stat & (UMAC_IRQ_RXDMA_BDONE|UMAC_IRQ_RXDMA_PDONE)) {
+		/*
+		 * We use NAPI(software interrupt throttling, if
+		 * Rx Descriptor throttling is not used.
+		 * Disable interrupt, will be enabled in the poll method.
+		 */
+		if (likely(napi_schedule_prep(&pDevCtrl->napi))) {
+			intrl2->cpu_mask_set |= UMAC_IRQ_RXDMA_BDONE;
+			__napi_schedule(&pDevCtrl->napi);
+		}
+	}
+#else
+	/* Multiple buffer done event. */
+	if (pDevCtrl->irq0_stat & UMAC_IRQ_RXDMA_MBDONE) {
+		unsigned int work_done;
+		volatile struct rDmaRingRegs *rDma_desc;
+
+		rDma_desc = &pDevCtrl->rxDma->rDmaRings[DESC_INDEX];
+		pDevCtrl->irq0_stat &= ~UMAC_IRQ_RXDMA_MBDONE;
+		TRACE(("%s: %d packets available\n", __func__, DmaDescThres));
+		work_done = bcmgenet_desc_rx(pDevCtrl, DmaDescThres);
+		/* Allocate new SKBs for the BD ring */
+		assign_rx_buffers(pDevCtrl);
+		rDma_desc->rdma_consumer_index += work_done;
+		rDma_desc->rdma_read_pointer += (work_done << 1);
+		rDma_desc->rdma_read_pointer &= ((TOTAL_DESC << 1)-1);
+	}
+#endif
+	if (pDevCtrl->irq0_stat &
+			(UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
+		/* Tx reclaim */
+		bcmgenet_xmit(NULL, pDevCtrl->dev);
+	}
+	if (pDevCtrl->irq0_stat & (UMAC_IRQ_PHY_DET_R |
+				UMAC_IRQ_PHY_DET_F |
+				UMAC_IRQ_LINK_UP |
+				UMAC_IRQ_LINK_DOWN |
+				UMAC_IRQ_HFB_SM |
+				UMAC_IRQ_HFB_MM |
+				UMAC_IRQ_MPD_R)) {
+
+		/* all other interrupts are handled in the workqueue */
+		pDevCtrl->int_mask = pDevCtrl->intrl2_0->cpu_mask_status;
+		pDevCtrl->intrl2_0->cpu_mask_set = ~0;
+		mb();
+
+		schedule_work(&pDevCtrl->bcmgenet_irq_work);
+	}
+
+	return IRQ_HANDLED;
+}
+/*
+ *  bcmgenet_desc_rx - descriptor based rx process.
+ *  this could be called from bottom half, or from NAPI polling method.
+ */
+static unsigned int bcmgenet_desc_rx(void *ptr, unsigned int budget)
+{
+	struct BcmEnet_devctrl *pDevCtrl = ptr;
+	struct net_device *dev = pDevCtrl->dev;
+	struct Enet_CB *cb;
+	struct sk_buff *skb;
+	unsigned long dmaFlag;
+	int len;
+	unsigned int rxpktprocessed = 0, rxpkttoprocess = 0;
+	unsigned int p_index = 0, c_index = 0, read_ptr = 0;
+
+	p_index = pDevCtrl->rxDma->rDmaRings[DESC_INDEX].rdma_producer_index;
+	p_index &= DMA_P_INDEX_MASK;
+	c_index = pDevCtrl->rxDma->rDmaRings[DESC_INDEX].rdma_consumer_index;
+	c_index &= DMA_C_INDEX_MASK;
+	read_ptr = pDevCtrl->rxDma->rDmaRings[DESC_INDEX].rdma_read_pointer;
+	read_ptr = ((read_ptr & DMA_RW_POINTER_MASK) >> 1);
+
+	if (p_index < c_index)
+		rxpkttoprocess = (DMA_C_INDEX_MASK+1) - c_index + p_index;
+	else
+		rxpkttoprocess = p_index - c_index;
+	TRACE(("RDMA: rxpkttoprocess=%d\n", rxpkttoprocess));
+
+	while ((rxpktprocessed < rxpkttoprocess) &&
+			(rxpktprocessed < budget)) {
+
+		dmaFlag = (pDevCtrl->rxBds[read_ptr].length_status & 0xffff);
+		len = ((pDevCtrl->rxBds[read_ptr].length_status)>>16);
+
+		TRACE(("%s:p_index=%d c_index=%d read_ptr=%d "
+			"len_stat=0x%08lx\n",
+			__func__, p_index, c_index, read_ptr,
+			pDevCtrl->rxBds[read_ptr].length_status));
+
+		rxpktprocessed++;
+
+		cb = &pDevCtrl->rxCbs[read_ptr];
+		skb = cb->skb;
+		dma_unmap_single(&dev->dev, dma_unmap_addr(cb, dma_addr),
+				pDevCtrl->rxBufLen, DMA_FROM_DEVICE);
+
+		pDevCtrl->rxBds[read_ptr].address = 0;
+
+		if (read_ptr == pDevCtrl->nrRxBds-1)
+			read_ptr = 0;
+		else
+			read_ptr++;
+
+		if (unlikely(!skb)) {
+			TRACE(("ERROR: skb is NULL\n"));
+			dev->stats.rx_dropped++;
+			dev->stats.rx_errors++;
+			continue;
+		}
+
+		if (unlikely(!(dmaFlag & DMA_EOP) || !(dmaFlag & DMA_SOP))) {
+			printk(KERN_WARNING "Droping fragmented packet!\n");
+			dev->stats.rx_dropped++;
+			dev->stats.rx_errors++;
+			dev_kfree_skb_any(cb->skb);
+			cb->skb = NULL;
+			continue;
+		}
+		/* report errors */
+		if (unlikely(dmaFlag & (DMA_RX_CRC_ERROR |
+						DMA_RX_OV |
+						DMA_RX_NO |
+						DMA_RX_LG |
+						DMA_RX_RXER))) {
+			TRACE(("ERROR: dmaFlag=0x%x\n", (unsigned int)dmaFlag));
+			if (dmaFlag & DMA_RX_CRC_ERROR)
+				dev->stats.rx_crc_errors++;
+			if (dmaFlag & DMA_RX_OV)
+				dev->stats.rx_over_errors++;
+			if (dmaFlag & DMA_RX_NO)
+				dev->stats.rx_frame_errors++;
+			if (dmaFlag & DMA_RX_LG)
+				dev->stats.rx_length_errors++;
+			dev->stats.rx_dropped++;
+			dev->stats.rx_errors++;
+
+			/* discard the packet and advance consumer index.*/
+			dev_kfree_skb_any(cb->skb);
+			cb->skb = NULL;
+			continue;
+		} /* error packet */
+
+		skb_put(skb, len);
+		if (pDevCtrl->rbuf->rbuf_ctrl & RBUF_64B_EN) {
+			struct status_64 *status;
+			status = (struct status_64 *)skb->data;
+			/* we have 64B rx status block enabled.*/
+			if (pDevCtrl->rbuf->rbuf_chk_ctrl & RBUF_RXCHK_EN) {
+				if (status->rx_csum & STATUS_RX_CSUM_OK)
+					skb->ip_summed = CHECKSUM_UNNECESSARY;
+				else
+					skb->ip_summed = CHECKSUM_NONE;
+			}
+			skb_pull(skb, 64);
+			len -= 64;
+		}
+
+		if (pDevCtrl->bIPHdrOptimize) {
+			skb_pull(skb, 2);
+			len -= 2;
+		}
+
+		if (pDevCtrl->umac->cmd & CMD_CRC_FWD) {
+			skb_trim(skb, len - 4);
+			len -= 4;
+		}
+#ifdef CONFIG_BCMGENET_DUMP_DATA
+		printk(KERN_NOTICE "bcmgenet_desc_rx : len=%d", skb->len);
+		print_hex_dump(KERN_NOTICE, "", DUMP_PREFIX_ADDRESS,
+			16, 1, skb->data, skb->len, 0);
+#endif
+
+		/*Finish setting up the received SKB and send it to the kernel*/
+		skb->dev = pDevCtrl->dev;
+		skb->protocol = eth_type_trans(skb, pDevCtrl->dev);
+		dev->stats.rx_packets++;
+		dev->stats.rx_bytes += len;
+		if (dmaFlag & DMA_RX_MULT)
+			dev->stats.multicast++;
+
+		/* Notify kernel */
+#ifdef CONFIG_BCMGENET_RX_DESC_THROTTLE
+		netif_rx(skb);
+#else
+		netif_receive_skb(skb);
+#endif
+		cb->skb = NULL;
+		TRACE(("pushed up to kernel\n"));
+	}
+
+	return rxpktprocessed;
+}
+
+
+/*
+ * assign_rx_buffers:
+ * Assign skb to RX DMA descriptor.
+ */
+static int assign_rx_buffers(struct BcmEnet_devctrl *pDevCtrl)
+{
+	struct sk_buff *skb;
+	unsigned short bdsfilled = 0;
+	unsigned long flags;
+	struct Enet_CB *cb;
+	dma_addr_t mapping;
+
+	TRACE(("%s\n", __func__));
+
+	/* This function may be called from irq bottom-half. */
+
+#ifndef CONFIG_BCMGENET_RX_DESC_THROTTLE
+	(void)flags;
+	spin_lock_bh(&pDevCtrl->bh_lock);
+#else
+	spin_lock_irqsave(&pDevCtrl->lock, flags);
+#endif
+
+	/* loop here for each buffer needing assign */
+	while (pDevCtrl->rxBdAssignPtr->address == 0) {
+		cb = &pDevCtrl->rxCbs[pDevCtrl->rxBdAssignPtr-pDevCtrl->rxBds];
+		skb = netdev_alloc_skb(pDevCtrl->dev,
+				pDevCtrl->rxBufLen + SKB_ALIGNMENT);
+		if (!skb) {
+			printk(KERN_ERR " failed to allocate skb for rx\n");
+			break;
+		}
+		handleAlignment(pDevCtrl, skb);
+
+		/* keep count of any BD's we refill */
+		cb->skb = skb;
+		mapping = dma_map_single(&pDevCtrl->dev->dev,
+			skb->data, pDevCtrl->rxBufLen, DMA_FROM_DEVICE);
+		if (dma_mapping_error(&pDevCtrl->dev->dev, mapping)) {
+			dev_err(&pDevCtrl->dev->dev, "assign_rx_buff DMA map failed\n");
+			break;
+		}
+		dma_unmap_addr_set(cb, dma_addr, mapping);
+		/* assign packet, prepare descriptor, and advance pointer */
+		pDevCtrl->rxBdAssignPtr->address = mapping;
+		pDevCtrl->rxBdAssignPtr->length_status =
+			(pDevCtrl->rxBufLen << 16);
+
+		/* turn on the newly assigned BD for DMA to use */
+		if (pDevCtrl->rxBdAssignPtr ==
+				pDevCtrl->rxBds+pDevCtrl->nrRxBds-1)
+			pDevCtrl->rxBdAssignPtr = pDevCtrl->rxBds;
+		else
+			pDevCtrl->rxBdAssignPtr++;
+
+		bdsfilled++;
+	}
+
+	/* Enable rx DMA incase it was disabled due to running out of rx BD */
+	pDevCtrl->rxDma->rdma_ctrl |= DMA_EN;
+
+#ifndef CONFIG_BCMGENET_RX_DESC_THROTTLE
+	spin_unlock_bh(&pDevCtrl->bh_lock);
+#else
+	spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+#endif
+
+	TRACE(("%s return bdsfilled=%d\n", __func__, bdsfilled));
+	return bdsfilled;
+}
+
+static void save_state(struct BcmEnet_devctrl *pDevCtrl)
+{
+	int ii;
+	volatile struct DmaDesc *rxBdAssignPtr = pDevCtrl->rxBds;
+
+	for (ii = 0; ii < pDevCtrl->nrRxBds; ++ii, ++rxBdAssignPtr) {
+		pDevCtrl->saved_rx_desc[ii].length_status =
+			rxBdAssignPtr->length_status;
+		pDevCtrl->saved_rx_desc[ii].address = rxBdAssignPtr->address;
+	}
+
+	pDevCtrl->int_mask = pDevCtrl->intrl2_0->cpu_mask_status;
+	pDevCtrl->rbuf_ctrl = pDevCtrl->rbuf->rbuf_ctrl;
+}
+
+static void restore_state(struct BcmEnet_devctrl *pDevCtrl)
+{
+	int ii;
+	volatile struct DmaDesc *rxBdAssignPtr = pDevCtrl->rxBds;
+
+	pDevCtrl->intrl2_0->cpu_mask_clear = 0xFFFFFFFF ^ pDevCtrl->int_mask;
+	pDevCtrl->rbuf->rbuf_ctrl = pDevCtrl->rbuf_ctrl;
+
+	for (ii = 0; ii < pDevCtrl->nrRxBds; ++ii, ++rxBdAssignPtr) {
+		rxBdAssignPtr->length_status =
+			pDevCtrl->saved_rx_desc[ii].length_status;
+		rxBdAssignPtr->address = pDevCtrl->saved_rx_desc[ii].address;
+	}
+
+	pDevCtrl->rxDma->rdma_ctrl |= DMA_EN;
+
+}
+
+/*
+ * init_umac: Initializes the uniMac controller
+ */
+static int init_umac(struct BcmEnet_devctrl *pDevCtrl, bool reset)
+{
+	volatile struct uniMacRegs *umac;
+	volatile struct intrl2Regs *intrl2;
+
+	umac = pDevCtrl->umac;
+	intrl2 = pDevCtrl->intrl2_0;
+
+	TRACE(("bcmgenet: init_umac "));
+
+	if (!reset)
+		goto rbuf_setup;
+
+	/* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
+	GENET_RBUF_FLUSH_CTRL(pDevCtrl) = 0;
+	udelay(10);
+
+	/* disable MAC while updating its registers */
+	umac->cmd = 0;
+
+	/* issue soft reset, wait for it to complete */
+	umac->cmd = CMD_SW_RESET;
+	udelay(1000);
+	umac->cmd = 0;
+	/* clear tx/rx counter */
+	umac->mib_ctrl = MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT;
+	umac->mib_ctrl = 0;
+
+#ifdef MAC_LOOPBACK
+	/* Enable GMII/MII loopback */
+	umac->cmd |= CMD_LCL_LOOP_EN;
+#endif
+	umac->max_frame_len = ENET_MAX_MTU_SIZE;
+	/*
+	 * init rx registers, enable ip header optimization.
+	 */
+rbuf_setup:
+	if (pDevCtrl->bIPHdrOptimize)
+		pDevCtrl->rbuf->rbuf_ctrl |= RBUF_ALIGN_2B ;
+#if CONFIG_BRCM_GENET_VERSION >= 3
+	pDevCtrl->rbuf->rbuf_tbuf_size_ctrl = 1;
+#endif
+
+	/* Mask all interrupts.*/
+	intrl2->cpu_mask_set = 0xFFFFFFFF;
+	intrl2->cpu_clear = 0xFFFFFFFF;
+	intrl2->cpu_mask_clear = 0x0;
+
+#ifdef CONFIG_BCMGENET_RX_DESC_THROTTLE
+	intrl2->cpu_mask_clear |= UMAC_IRQ_RXDMA_MBDONE;
+#else
+	intrl2->cpu_mask_clear |= UMAC_IRQ_RXDMA_BDONE;
+	TRACE(("%s:Enabling RXDMA_BDONE interrupt\n", __func__));
+#endif /* CONFIG_BCMGENET_RX_DESC_THROTTLE */
+
+	/* Monitor cable plug/unpluged event for internal PHY */
+	if (pDevCtrl->phyType == BRCM_PHY_TYPE_INT) {
+		intrl2->cpu_mask_clear |= (UMAC_IRQ_PHY_DET_R |
+				UMAC_IRQ_PHY_DET_F);
+		intrl2->cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN |
+				UMAC_IRQ_LINK_UP);
+		/* Turn on ENERGY_DET interrupt in bcmgenet_open()
+		 * TODO: fix me for active standby.
+		 */
+	} else if (pDevCtrl->extPhy) {
+		intrl2->cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN |
+				UMAC_IRQ_LINK_UP);
+	} else if (pDevCtrl->phyType == BRCM_PHY_TYPE_MOCA) {
+		GENET_TBUF_BP_MC(pDevCtrl) |= BIT(GENET_BP_IN_EN_SHIFT);
+
+		/* bp_mask: back pressure mask */
+#if defined(CONFIG_NET_SCH_MULTIQ)
+		GENET_TBUF_BP_MC(pDevCtrl) |= GENET_BP_MASK;
+#else
+		GENET_TBUF_BP_MC(pDevCtrl) &= ~GENET_BP_MASK;
+#endif
+	}
+
+	/* Enable rx/tx engine.*/
+	TRACE(("done init umac\n"));
+	return 0;
+}
+/*
+ * init_edma: Initialize DMA control register
+ */
+static void init_edma(struct BcmEnet_devctrl *pDevCtrl)
+{
+#ifdef CONFIG_BCMGENET_RX_DESC_THROTTLE
+	int speeds[] = {10, 100, 1000, 2500};
+	int sid = 1, timeout;
+#endif
+	volatile struct rDmaRingRegs *rDma_desc;
+	volatile struct tDmaRingRegs *tDma_desc;
+	TRACE(("bcmgenet: init_edma\n"));
+
+	/* init rDma */
+	pDevCtrl->rxDma->rdma_scb_burst_size = DMA_MAX_BURST_LENGTH;
+	/* by default, enable ring 16 (descriptor based) */
+	rDma_desc = &pDevCtrl->rxDma->rDmaRings[DESC_INDEX];
+	rDma_desc->rdma_write_pointer = 0;
+	rDma_desc->rdma_producer_index = 0;
+	rDma_desc->rdma_consumer_index = 0;
+	rDma_desc->rdma_ring_buf_size = ((TOTAL_DESC << DMA_RING_SIZE_SHIFT) |
+		RX_BUF_LENGTH);
+	rDma_desc->rdma_start_addr = 0;
+	rDma_desc->rdma_end_addr = 2*TOTAL_DESC - 1;
+	rDma_desc->rdma_xon_xoff_threshold = ((DMA_FC_THRESH_LO
+			<< DMA_XOFF_THRESHOLD_SHIFT) |
+			DMA_FC_THRESH_HI);
+	rDma_desc->rdma_read_pointer = 0;
+
+#ifdef CONFIG_BCMGENET_RX_DESC_THROTTLE
+	/*
+	 * Use descriptor throttle, fire irq when multiple packets are done!
+	 */
+	rDma_desc->rdma_mbuf_done_threshold = DMA_DESC_THRES;
+	/*
+	 * Enable push timer, force the IRQ_DESC_THROT to fire when timeout
+	 * occurs, prevent system slow reponse when handling low throughput.
+	 */
+	sid = (pDevCtrl->umac->cmd >> CMD_SPEED_SHIFT) & CMD_SPEED_MASK;
+	timeout = 2*(DMA_DESC_THRES*ENET_MAX_MTU_SIZE)/speeds[sid];
+	pDevCtrl->rxDma->rdma_timeout[DESC_INDEX] = timeout & DMA_TIMEOUT_MASK;
+#endif	/* CONFIG_BCMGENET_RX_DESC_THROTTLE */
+
+
+	/* Init tDma */
+	pDevCtrl->txDma->tdma_scb_burst_size = DMA_MAX_BURST_LENGTH;
+	/* by default, enable ring DESC_INDEX (descriptor based) */
+	tDma_desc = &pDevCtrl->txDma->tDmaRings[DESC_INDEX];
+	tDma_desc->tdma_producer_index = 0;
+	tDma_desc->tdma_consumer_index = 0;
+	tDma_desc->tdma_mbuf_done_threshold = 1;
+	/* Disable rate control for now */
+	tDma_desc->tdma_flow_period = 0;
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+	/* Unclassified traffic goes to ring 16 */
+	tDma_desc->tdma_ring_buf_size = ((GENET_DEFAULT_BD_CNT <<
+				DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH);
+	tDma_desc->tdma_start_addr = 2*(GENET_MQ_CNT*GENET_MQ_BD_CNT);
+	tDma_desc->tdma_end_addr = 2*TOTAL_DESC - 1;
+	tDma_desc->tdma_read_pointer = 2*(GENET_MQ_CNT*GENET_MQ_BD_CNT);
+	tDma_desc->tdma_write_pointer = 2*(GENET_MQ_CNT*GENET_MQ_BD_CNT);
+	pDevCtrl->txFreeBds = GENET_DEFAULT_BD_CNT;
+	/* initiaize multi xmit queue */
+	bcmgenet_init_multiq(pDevCtrl->dev);
+
+#else
+	tDma_desc->tdma_ring_buf_size = ((TOTAL_DESC << DMA_RING_SIZE_SHIFT) |
+			RX_BUF_LENGTH);
+	tDma_desc->tdma_start_addr = 0;
+	tDma_desc->tdma_end_addr = 2*TOTAL_DESC - 1;
+	tDma_desc->tdma_read_pointer = 0;
+	tDma_desc->tdma_write_pointer = 0;
+#endif
+
+}
+/*-----------------------------------------------------------------------------
+ * exported function , Initialize ring buffer
+ * dev: device pointer.
+ * direction: 0 for rx 1 for tx.
+ * id: ring index.
+ * size: ring size, number of buffer in the ring, must be power of 2.
+ * buf_len: buffer length, must be 32 bytes aligned, we assume 2Kb here.
+ * buf: pointer to the buffer, continues memory, if *buf == NULL, buffer will
+ * be allocated by this function.
+ *----------------------------------------------------------------------------*/
+int bcmgenet_init_ringbuf(struct net_device *dev, int direction,
+		unsigned int id, unsigned int size,
+		int buf_len, unsigned char **buf)
+{
+	int speeds[] = {10, 100, 1000, 2500};
+	int sid = 1;
+	int i, dma_enable, timeout;
+	dma_addr_t dma_start;
+	struct Enet_CB *cb;
+	unsigned long flags;
+	volatile struct rDmaRingRegs *rDmaRing;
+	volatile struct tDmaRingRegs *tDmaRing;
+
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+
+	if (id < 0 || id > 15 || size & (size - 1))
+		return -EINVAL;
+
+	spin_lock_irqsave(&pDevCtrl->lock, flags);
+
+	if (direction == GENET_ALLOC_RX_RING) {
+		if (*buf == NULL) {
+			*buf = kmalloc(size * buf_len, GFP_KERNEL);
+			if (*buf == NULL) {
+				spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+				return -ENOMEM;
+			}
+		}
+		cb  = kmalloc(size*sizeof(struct Enet_CB), GFP_KERNEL);
+		if (cb == NULL) {
+			kfree(buf);
+			spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+			return -ENOMEM;
+		}
+		rDmaRing = &pDevCtrl->rxDma->rDmaRings[id];
+		pDevCtrl->rxRingCbs[id] = cb;
+		pDevCtrl->rxRingSize[id] = size;
+		pDevCtrl->rxRingCIndex[id] = 0;
+		pDevCtrl->rxRingDiscCnt[id] = 0;
+
+		dma_enable = pDevCtrl->rxDma->rdma_ctrl & DMA_EN;
+		pDevCtrl->rxDma->rdma_ctrl &= ~DMA_EN;
+		rDmaRing->rdma_producer_index = 0;
+		rDmaRing->rdma_consumer_index = 0;
+		rDmaRing->rdma_ring_buf_size = ((size << DMA_RING_SIZE_SHIFT) |
+				buf_len);
+		dma_start = dma_map_single(&dev->dev, *buf, buf_len * size,
+				DMA_FROM_DEVICE);
+
+		for (i = 0; i < size; i++) {
+			cb->skb = NULL;
+			cb->BdAddr = (struct DmaDesc *)(*buf + i*buf_len);
+			cb->dma_addr = dma_start + i*buf_len;
+			cb->dma_len = buf_len;
+			cb++;
+		}
+
+		rDmaRing->rdma_start_addr = dma_start;
+		rDmaRing->rdma_end_addr = dma_start + size * buf_len - 1;
+		rDmaRing->rdma_xon_xoff_threshold = (DMA_FC_THRESH_LO <<
+				DMA_XOFF_THRESHOLD_SHIFT) | DMA_FC_THRESH_HI;
+		rDmaRing->rdma_read_pointer = dma_start;
+		rDmaRing->rdma_write_pointer = dma_start;
+
+		/*
+		* Use descriptor throttle, fire interrupt only when multiple
+		* packets are done!
+		*/
+		rDmaRing->rdma_mbuf_done_threshold = DMA_DESC_THRES;
+		/*
+		* Enable push timer, that is, force the IRQ_DESC_THROT to fire
+		* when timeout occurs, to prevent system slow reponse when
+		* handling low throughput data.
+		*/
+		sid = (pDevCtrl->umac->cmd >> CMD_SPEED_SHIFT) & CMD_SPEED_MASK;
+		timeout = 16*2*(DMA_DESC_THRES*ENET_MAX_MTU_SIZE)/speeds[sid];
+		/* set large pushtimer value to reduce interrupt rate */
+		pDevCtrl->rxDma->rdma_timeout[id] = timeout & DMA_TIMEOUT_MASK;
+
+		/* Enable interrupt for this ring */
+		pDevCtrl->intrl2_1->cpu_mask_clear |= (1 << (id + 16));
+		pDevCtrl->rxDma->rdma_ctrl |= (1<<(id+DMA_RING_BUF_EN_SHIFT));
+		if (!(pDevCtrl->rbuf->rbuf_ctrl & RBUF_64B_EN))
+			pDevCtrl->rbuf->rbuf_ctrl |= RBUF_64B_EN;
+		if (dma_enable)
+			pDevCtrl->rxDma->rdma_ctrl |= DMA_EN;
+	} else {
+		cb  = kmalloc(size*sizeof(struct Enet_CB), GFP_KERNEL);
+		if (cb == NULL) {
+			spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+			return -ENOMEM;
+		}
+		tDmaRing = &pDevCtrl->txDma->tDmaRings[id];
+		pDevCtrl->txRingCBs[id] = cb;
+		pDevCtrl->txRingSize[id] = size;
+		pDevCtrl->txRingCIndex[id] = 0;
+
+		dma_enable = pDevCtrl->txDma->tdma_ctrl & DMA_EN;
+		pDevCtrl->txDma->tdma_ctrl &= ~DMA_EN;
+		tDmaRing->tdma_producer_index = 0;
+		tDmaRing->tdma_consumer_index = 0;
+		tDmaRing->tdma_ring_buf_size = ((size << DMA_RING_SIZE_SHIFT) |
+				buf_len);
+		dma_start = dma_map_single(&dev->dev, *buf, buf_len * size,
+				DMA_TO_DEVICE);
+		for (i = 0; i < size; i++) {
+			cb->skb = NULL;
+			cb->BdAddr = (struct DmaDesc *)(*buf + i*buf_len);
+			cb->dma_addr = dma_start + i*buf_len;
+			cb++;
+		}
+		tDmaRing->tdma_start_addr = dma_start;
+		tDmaRing->tdma_end_addr = dma_start + size * buf_len - 1;
+		tDmaRing->tdma_mbuf_done_threshold = 1;
+		tDmaRing->tdma_flow_period = ENET_MAX_MTU_SIZE << 16;
+		tDmaRing->tdma_read_pointer = dma_start;
+		tDmaRing->tdma_write_pointer = dma_start;
+
+		if (!(GENET_TBUF_CTRL(pDevCtrl) & RBUF_64B_EN)) {
+			GENET_TBUF_CTRL(pDevCtrl) |= RBUF_64B_EN;
+			if (dev->needed_headroom < 64)
+				dev->needed_headroom += 64;
+		}
+		pDevCtrl->txDma->tdma_ctrl |= DMA_TSB_SWAP_EN;
+		pDevCtrl->txDma->tdma_ctrl |= (1<<(id+DMA_RING_BUF_EN_SHIFT));
+		if (dma_enable)
+			pDevCtrl->txDma->tdma_ctrl |= DMA_EN;
+	}
+
+	spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+	return 0;
+}
+EXPORT_SYMBOL(bcmgenet_init_ringbuf);
+/*
+ * bcmgenet_uninit_ringbuf : cleanup ring buffer
+ * if "free" is non-zero , it will free the buffer.
+ */
+int bcmgenet_uninit_ringbuf(struct net_device *dev, int direction,
+		unsigned int id, int free)
+{
+	int dma_enable, size = 0, buflen, i;
+	struct Enet_CB *cb;
+	unsigned long flags;
+	volatile struct rDmaRingRegs *rDmaRing;
+	volatile struct tDmaRingRegs *tDmaRing;
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+
+	if (id < 0 || id > 15 || size & (size - 1))
+		return -EINVAL;
+
+	spin_lock_irqsave(&pDevCtrl->lock, flags);
+	if (direction == GENET_ALLOC_RX_RING) {
+		rDmaRing = &pDevCtrl->rxDma->rDmaRings[id];
+		size = (rDmaRing->rdma_ring_buf_size >> DMA_RING_SIZE_SHIFT);
+		buflen = (0xFFFF & rDmaRing->rdma_ring_buf_size);
+		/* Disble this ring first */
+		dma_enable = pDevCtrl->rxDma->rdma_ctrl & DMA_EN;
+		pDevCtrl->rxDma->rdma_ctrl &= ~DMA_EN;
+		pDevCtrl->rxDma->rdma_ctrl &=
+			~(1 << (id + DMA_RING_BUF_EN_SHIFT));
+		dma_unmap_single(&pDevCtrl->dev->dev,
+			rDmaRing->rdma_start_addr,
+			size * buflen,
+			DMA_FROM_DEVICE);
+
+		/*release resources */
+		cb = pDevCtrl->rxRingCbs[id];
+
+		for (i = 0; i < size; i++) {
+			if (cb->skb != NULL)
+				dev_kfree_skb_any(cb->skb);
+			cb++;
+		}
+		if (free)
+			kfree((void *)pDevCtrl->rxRingCbs[id]->BdAddr);
+
+		kfree(pDevCtrl->rxRingCbs[id]);
+		if (dma_enable)
+			pDevCtrl->rxDma->rdma_ctrl |= DMA_EN;
+	} else {
+		tDmaRing = &pDevCtrl->txDma->tDmaRings[id];
+		size = (tDmaRing->tdma_ring_buf_size >> DMA_RING_SIZE_SHIFT);
+		buflen = (0xFFFF & tDmaRing->tdma_ring_buf_size);
+		dma_enable = pDevCtrl->txDma->tdma_ctrl & DMA_EN;
+		pDevCtrl->txDma->tdma_ctrl &= ~DMA_EN;
+		/* Disble this ring first */
+		pDevCtrl->txDma->tdma_ctrl &=
+			~(1 << (id + DMA_RING_BUF_EN_SHIFT));
+		dma_unmap_single(&pDevCtrl->dev->dev,
+				tDmaRing->tdma_start_addr,
+				size * buflen,
+				DMA_TO_DEVICE);
+
+		/*release resources */
+		cb = pDevCtrl->txRingCBs[id];
+		kfree(cb);
+		/*
+		 * if all rings are disabled and tx checksum offloading
+		 * is off, disable TSB.
+		 */
+		if (!(pDevCtrl->txDma->tdma_ctrl & (0xFFFF << 1))
+				&& !(dev->features & NETIF_F_IP_CSUM)) {
+			GENET_TBUF_CTRL(pDevCtrl) &= ~RBUF_64B_EN;
+			if (dev->needed_headroom > 64)
+				dev->needed_headroom -= 64;
+		}
+		if (dma_enable)
+			pDevCtrl->rxDma->rdma_ctrl |= DMA_EN;
+	}
+
+	spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+	return 0;
+}
+EXPORT_SYMBOL(bcmgenet_uninit_ringbuf);
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+/*
+ * init multi xmit queues, only available for GENET2
+ * the queue is partitioned as follows:
+ *
+ * queue 0 - 3 is priority based, each one has 48 descriptors,
+ * with queue 0 being the highest priority queue.
+ *
+ * queue 16 is the default tx queue, with 64 descriptors.
+ */
+static void bcmgenet_init_multiq(struct net_device *dev)
+{
+	int i, dma_enable;
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+
+	dma_enable = pDevCtrl->txDma->tdma_ctrl & DMA_EN;
+	pDevCtrl->txDma->tdma_ctrl &= ~DMA_EN;
+	/* Enable strict priority arbiter mode */
+	pDevCtrl->txDma->tdma_arb_ctrl = 0x2;
+	for (i = 0; i < GENET_MQ_CNT; i++) {
+		/* first 64 txCbs are reserved for default tx queue (ring 16) */
+		pDevCtrl->txRingCBs[i] = pDevCtrl->txCbs +
+			GENET_DEFAULT_BD_CNT + i * GENET_MQ_BD_CNT;
+		pDevCtrl->txRingSize[i] = GENET_MQ_BD_CNT;
+		pDevCtrl->txRingCIndex[i] = 0;
+		pDevCtrl->txRingFreeBds[i] = GENET_MQ_BD_CNT;
+
+		pDevCtrl->txDma->tDmaRings[i].tdma_producer_index = 0;
+		pDevCtrl->txDma->tDmaRings[i].tdma_consumer_index = 0;
+		pDevCtrl->txDma->tDmaRings[i].tdma_ring_buf_size =
+			(GENET_MQ_BD_CNT << DMA_RING_SIZE_SHIFT) |
+			RX_BUF_LENGTH;
+		pDevCtrl->txDma->tDmaRings[i].tdma_start_addr =
+			2 * i * GENET_MQ_BD_CNT;
+		pDevCtrl->txDma->tDmaRings[i].tdma_end_addr =
+			2 * (i + 1)*GENET_MQ_BD_CNT - 1;
+		pDevCtrl->txDma->tDmaRings[i].tdma_flow_period =
+			ENET_MAX_MTU_SIZE << 16;
+		pDevCtrl->txDma->tDmaRings[i].tdma_mbuf_done_threshold = 1;
+		pDevCtrl->txDma->tDmaRings[i].tdma_write_pointer =
+			2 * i * GENET_MQ_BD_CNT;
+		pDevCtrl->txDma->tDmaRings[i].tdma_read_pointer =
+			2 * i * GENET_MQ_BD_CNT;
+
+		/* Configure ring as decriptor ring and setup priority */
+		pDevCtrl->txDma->tdma_ring_cfg |= (1 << i);
+		pDevCtrl->txDma->tdma_priority[0] |=
+			((GENET_Q0_PRIORITY + i) << 5*i);
+		pDevCtrl->txDma->tdma_ctrl |=
+			(1 << (i + DMA_RING_BUF_EN_SHIFT));
+	}
+	/* Set ring #16 priority */
+	pDevCtrl->txDma->tdma_priority[2] |=
+		((GENET_Q0_PRIORITY + GENET_MQ_CNT) << 20);
+	if (dma_enable)
+		pDevCtrl->txDma->tdma_ctrl |= DMA_EN;
+}
+#endif
+/*
+ * bcmgenet_init_dev: initialize uniMac devie
+ * allocate Tx/Rx buffer descriptors pool, Tx control block pool.
+ */
+static int bcmgenet_init_dev(struct BcmEnet_devctrl *pDevCtrl, bool reset)
+{
+	int i, ret;
+	unsigned long base;
+	volatile struct DmaDesc *lastBd;
+
+	pDevCtrl->clk = clk_get(&pDevCtrl->pdev->dev, "enet");
+	pDevCtrl->clk_wol = clk_get(&pDevCtrl->pdev->dev, "enet-wol");
+	bcmgenet_clock_enable(pDevCtrl);
+
+	TRACE(("%s\n", __func__));
+	/* setup buffer/pointer relationships here */
+	pDevCtrl->nrTxBds = pDevCtrl->nrRxBds = TOTAL_DESC;
+	/* Always use 2KB buffer for 7420*/
+	pDevCtrl->rxBufLen = RX_BUF_LENGTH;
+
+	/* register block locations */
+	base = pDevCtrl->dev->base_addr;
+	pDevCtrl->sys = (struct SysRegs *)(base);
+	pDevCtrl->grb = (struct GrBridgeRegs *)(base + GENET_GR_BRIDGE_OFF);
+	pDevCtrl->ext = (struct ExtRegs *)(base + GENET_EXT_OFF);
+#if CONFIG_BRCM_GENET_VERSION == 1
+	/* SWLINUX-1813: EXT block is not available on MOCA_GENET */
+#if !defined(CONFIG_BCM7125)
+	if (pDevCtrl->devnum == 1)
+#endif
+		pDevCtrl->ext = NULL;
+#endif
+	pDevCtrl->intrl2_0 = (struct intrl2Regs *)(base + GENET_INTRL2_0_OFF);
+	pDevCtrl->intrl2_1 = (struct intrl2Regs *)(base + GENET_INTRL2_1_OFF);
+	pDevCtrl->rbuf = (struct rbufRegs *)(base + GENET_RBUF_OFF);
+	pDevCtrl->umac = (struct uniMacRegs *)(base + GENET_UMAC_OFF);
+	pDevCtrl->hfb = (unsigned long *)(base + GENET_HFB_OFF);
+	pDevCtrl->txDma = (struct tDmaRegs *)(base + GENET_TDMA_REG_OFF);
+	pDevCtrl->rxDma = (struct rDmaRegs *)(base + GENET_RDMA_REG_OFF);
+
+#if CONFIG_BRCM_GENET_VERSION > 1
+	pDevCtrl->tbuf = (struct tbufRegs *)(base + GENET_TBUF_OFF);
+	pDevCtrl->hfbReg = (struct hfbRegs *)(base + GENET_HFB_REG_OFF);
+#endif
+
+	pDevCtrl->rxBds = (struct DmaDesc *)(base + GENET_RDMA_OFF);
+	pDevCtrl->txBds = (struct DmaDesc *)(base + GENET_TDMA_OFF);
+
+	TRACE(("%s: rxbds=0x%08x txbds=0x%08x\n", __func__,
+		(unsigned int)pDevCtrl->rxBds, (unsigned int)pDevCtrl->txBds));
+
+	/* alloc space for the tx control block pool */
+	if (!pDevCtrl->txCbs)
+		pDevCtrl->txCbs = kmalloc(pDevCtrl->nrTxBds*sizeof(struct Enet_CB), GFP_KERNEL);
+	if (!pDevCtrl->txCbs) {
+		bcmgenet_clock_disable(pDevCtrl);
+		return -ENOMEM;
+	}
+	memset(pDevCtrl->txCbs, 0, pDevCtrl->nrTxBds*sizeof(struct Enet_CB));
+
+	/* initialize rx ring pointer variables. */
+	pDevCtrl->rxBdAssignPtr = pDevCtrl->rxBds;
+	if (!pDevCtrl->rxCbs)
+		pDevCtrl->rxCbs = kmalloc(pDevCtrl->nrRxBds*sizeof(struct Enet_CB), GFP_KERNEL);
+	if (!pDevCtrl->rxCbs) {
+		ret = -ENOMEM;
+		goto error2;
+	}
+	memset(pDevCtrl->rxCbs, 0, pDevCtrl->nrRxBds*sizeof(struct Enet_CB));
+
+	/* init the receive buffer descriptor ring */
+	for (i = 0; i < pDevCtrl->nrRxBds; i++) {
+		(pDevCtrl->rxBds + i)->length_status = (pDevCtrl->rxBufLen<<16);
+		(pDevCtrl->rxBds + i)->address = 0;
+	}
+	lastBd = pDevCtrl->rxBds + pDevCtrl->nrRxBds - 1;
+
+	/* clear the transmit buffer descriptors */
+	for (i = 0; i < pDevCtrl->nrTxBds; i++) {
+		(pDevCtrl->txBds + i)->length_status = 0<<16;
+		(pDevCtrl->txBds + i)->address = 0;
+	}
+	lastBd = pDevCtrl->txBds + pDevCtrl->nrTxBds - 1;
+	pDevCtrl->txFreeBds = pDevCtrl->nrTxBds;
+
+	TRACE(("%s done!\n", __func__));
+	/* init umac registers */
+	if (init_umac(pDevCtrl, reset)) {
+		ret = -EFAULT;
+		goto error1;
+	}
+
+	/* init dma registers */
+	init_edma(pDevCtrl);
+
+#if (CONFIG_BRCM_GENET_VERSION > 1) && defined(CONFIG_NET_SCH_MULTIQ)
+	pDevCtrl->nrTxBds = GENET_DEFAULT_BD_CNT;
+#endif
+
+	TRACE(("%s done!\n", __func__));
+	/* if we reach this point, we've init'ed successfully */
+	return 0;
+error1:
+	kfree(pDevCtrl->rxCbs);
+error2:
+	kfree(pDevCtrl->txCbs);
+	bcmgenet_clock_disable(pDevCtrl);
+
+	TRACE(("%s Failed!\n", __func__));
+	return ret;
+}
+
+/* Uninitialize tx/rx buffer descriptor pools */
+static void bcmgenet_uninit_dev(struct BcmEnet_devctrl *pDevCtrl)
+{
+	int i;
+
+	if (pDevCtrl) {
+		/* disable DMA */
+		pDevCtrl->rxDma->rdma_ctrl = 0;
+		pDevCtrl->txDma->tdma_ctrl = 0;
+
+		for (i = 0; i < pDevCtrl->nrTxBds; i++) {
+			if (pDevCtrl->txCbs[i].skb != NULL) {
+				dev_kfree_skb(pDevCtrl->txCbs[i].skb);
+				pDevCtrl->txCbs[i].skb = NULL;
+			}
+		}
+
+		bcmgenet_free_rx_buffers(pDevCtrl);
+
+		/* free the transmit buffer descriptor */
+		if (pDevCtrl->txBds)
+			pDevCtrl->txBds = NULL;
+		/* free the receive buffer descriptor */
+		if (pDevCtrl->rxBds)
+			pDevCtrl->rxBds = NULL;
+		/* free the transmit control block pool */
+		kfree(pDevCtrl->txCbs);
+		/* free the transmit control block pool */
+		kfree(pDevCtrl->rxCbs);
+
+		clk_put(pDevCtrl->clk);
+	}
+}
+
+#define FILTER_POS(i)	(((HFB_NUM_FLTRS-i-1)>>2))
+#define SET_HFB_FILTER_LEN(dev, i, len) \
+do { \
+	u32 tmp = GENET_HFB_FLTR_LEN(dev, FILTER_POS(i)); \
+	tmp &= ~(RBUF_FLTR_LEN_MASK << (RBUF_FLTR_LEN_SHIFT * (i & 0x03))); \
+	tmp |= (len << (RBUF_FLTR_LEN_SHIFT * (i & 0x03))); \
+	GENET_HFB_FLTR_LEN(dev, FILTER_POS(i)) = tmp; \
+} while (0)
+
+#define GET_HFB_FILTER_LEN(dev, i) \
+	((GENET_HFB_FLTR_LEN(dev, FILTER_POS(i)) >> \
+		(RBUF_FLTR_LEN_SHIFT * (i & 0x03))) & RBUF_FLTR_LEN_MASK)
+
+#if CONFIG_BRCM_GENET_VERSION >= 3
+/* The order of GENET_x_HFB_FLT_ENBLE_0/1 is reversed !!! */
+#define	GET_HFB_FILTER_EN(dev, i) \
+	(dev->hfbReg->hfb_flt_enable[i < 32] & (1 << (i % 32)))
+#define HFB_FILTER_ENABLE(dev, i) \
+	(dev->hfbReg->hfb_flt_enable[i < 32] |= (1 << (i % 32)))
+#define HFB_FILTER_DISABLE(dev, i) \
+	(dev->hfbReg->hfb_flt_enable[i < 32] &= ~(1 << (i % 32)))
+#define	HFB_FILTER_DISABLE_ALL(dev) \
+	do { \
+		dev->hfbReg->hfb_flt_enable[0] = 0; \
+		dev->hfbReg->hfb_flt_enable[1] = 0; \
+	} while (0)
+#else
+#define GET_HFB_FILTER_EN(dev, i) \
+	((GENET_HFB_CTRL(dev) >> (i + RBUF_HFB_FILTER_EN_SHIFT)) & 0x01)
+#define HFB_FILTER_ENABLE(dev, i) \
+	(GENET_HFB_CTRL(dev) |= 1 << (i + RBUF_HFB_FILTER_EN_SHIFT))
+#define HFB_FILTER_DISABLE(dev, i) \
+	(GENET_HFB_CTRL(dev) &= ~(1 << (i + RBUF_HFB_FILTER_EN_SHIFT)))
+#define	HFB_FILTER_DISABLE_ALL(dev) \
+	(GENET_HFB_CTRL(dev) &= ~(0xffff << (RBUF_HFB_FILTER_EN_SHIFT)))
+#endif
+
+/*
+ * Program ACPI pattern into HFB. Return filter index if succesful.
+ * if user == 1, the data will be copied from user space.
+ */
+int bcmgenet_update_hfb(struct net_device *dev, unsigned int *data,
+		int len, int user)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	int filter, offset, count;
+	unsigned int *tmp;
+
+	TRACE(("Updating HFB len=0x%d\n", len));
+
+	count = HFB_NUM_FLTRS;
+	offset = 64;
+	if (GENET_HFB_CTRL(pDevCtrl) & RBUF_HFB_256B) {
+#if CONFIG_BRCM_GENET_VERSION < 3
+		count >>= 1;
+#endif
+		offset = 128;
+	}
+
+	if (len > offset)
+		return -EINVAL;
+
+	/* find next unused filter */
+	for (filter = 0; filter < count; filter++) {
+		if (!GET_HFB_FILTER_EN(pDevCtrl, filter))
+			break;
+	}
+	if (filter == count) {
+		printk(KERN_ERR "no unused filter available!\n");
+		return -EINVAL;	/* all filters have been enabled*/
+	}
+
+	if (user) {
+		tmp = kmalloc(len*sizeof(unsigned int), GFP_KERNEL);
+		if (tmp == NULL) {
+			printk(KERN_ERR "%s: Malloc faild\n", __func__);
+			return -EFAULT;
+		}
+		/* copy pattern data */
+		if (copy_from_user(tmp, data, len*sizeof(unsigned int)) != 0) {
+			printk(KERN_ERR "Failed to copy user data: src=%p, dst=%p\n",
+				data, pDevCtrl->hfb + filter*offset);
+			return -EFAULT;
+		}
+	} else {
+		tmp = data;
+	}
+	/* Copy pattern data into HFB registers.*/
+	for (count = 0; count < offset; count++) {
+		if (count < len)
+			pDevCtrl->hfb[filter * offset + count] = *(tmp + count);
+		else
+			pDevCtrl->hfb[filter * offset + count] = 0;
+	}
+	if (user)
+		kfree(tmp);
+
+	/* set the filter length*/
+	SET_HFB_FILTER_LEN(pDevCtrl, filter, len*2);
+
+	/*enable this filter.*/
+	HFB_FILTER_ENABLE(pDevCtrl, filter);
+
+	return filter;
+
+}
+EXPORT_SYMBOL(bcmgenet_update_hfb);
+/*
+ * read ACPI pattern data for a particular filter.
+ */
+static int bcmgenet_read_hfb(struct net_device *dev, struct acpi_data *u_data)
+{
+	int filter, offset, count, len;
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+
+	if (get_user(filter, &(u_data->fltr_index))) {
+		printk(KERN_ERR "Failed to get user data\n");
+		return -EFAULT;
+	}
+
+	count = HFB_NUM_FLTRS;
+	offset = 128;
+	if (GENET_HFB_CTRL(pDevCtrl) & RBUF_HFB_256B) {
+#if CONFIG_BRCM_GENET_VERSION < 3
+		count >>= 1;
+#endif
+		offset = 256;
+	}
+
+	if (filter > count)
+		return -EINVAL;
+
+	/* see if this filter is enabled, if not, return length 0 */
+	if (!GET_HFB_FILTER_EN(pDevCtrl, filter)) {
+		len = 0;
+		put_user(len , &u_data->count);
+		return 0;
+	}
+	/* check the filter length, in bytes */
+	len = GET_HFB_FILTER_LEN(pDevCtrl, filter);
+	if (u_data->count < len)
+		return -EINVAL;
+	/* copy pattern data */
+	if (copy_to_user((void *)(u_data->p_data),
+			(void *)(pDevCtrl->hfb + filter*offset), len)) {
+		printk(KERN_ERR "Failed to copy data to user space: src=%p, dst=%p\n",
+				pDevCtrl->hfb+filter*offset, u_data->p_data);
+		return -EFAULT;
+	}
+	return len;
+}
+/*
+ * clear the HFB, disable filter indexed by "filter" argument.
+ */
+static inline void bcmgenet_clear_hfb(struct BcmEnet_devctrl *pDevCtrl,
+		int filter)
+{
+	if (filter == CLEAR_ALL_HFB) {
+		HFB_FILTER_DISABLE_ALL(pDevCtrl);
+		GENET_HFB_CTRL(pDevCtrl) &= ~RBUF_HFB_EN;
+	} else {
+		/* disable this filter */
+		HFB_FILTER_DISABLE(pDevCtrl, filter);
+		/* clear filter length register */
+		SET_HFB_FILTER_LEN(pDevCtrl, filter, 0);
+	}
+
+}
+/*
+ * Utility function to get interface ip address in kernel space.
+ */
+static inline unsigned int bcmgenet_getip(struct net_device *dev)
+{
+	struct net_device *pnet_device;
+	unsigned int ip = 0;
+
+	read_lock(&dev_base_lock);
+	/* read all devices */
+	for_each_netdev(&init_net, pnet_device)
+	{
+		if ((netif_running(pnet_device)) &&
+				(pnet_device->ip_ptr != NULL) &&
+				(!strcmp(pnet_device->name, dev->name))) {
+			struct in_device *pin_dev;
+			pin_dev = (struct in_device *)(pnet_device->ip_ptr);
+			if (pin_dev && pin_dev->ifa_list)
+				ip = htonl(pin_dev->ifa_list->ifa_address);
+			break;
+		}
+	}
+	read_unlock(&dev_base_lock);
+	return ip;
+}
+
+static void bcmgenet_clock_enable(struct BcmEnet_devctrl *pDevCtrl)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&pDevCtrl->lock, flags);
+	clk_enable(pDevCtrl->clk);
+	pDevCtrl->clock_active = 1;
+	spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+}
+
+static void bcmgenet_clock_disable(struct BcmEnet_devctrl *pDevCtrl)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&pDevCtrl->lock, flags);
+	pDevCtrl->clock_active = 0;
+	clk_disable(pDevCtrl->clk);
+	spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+}
+
+/*
+ * ethtool function - get WOL (Wake on LAN) settings,
+ * Only Magic Packet Detection is supported through ethtool,
+ * the ACPI (Pattern Matching) WOL option is supported in
+ * bcmumac_do_ioctl function.
+ */
+static void bcmgenet_get_wol(struct net_device *dev,
+		struct ethtool_wolinfo *wol)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	volatile struct uniMacRegs *umac = pDevCtrl->umac;
+	wol->supported = WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_ARP;
+
+	if (!netif_running(dev))
+		return;
+
+	wol->wolopts = pDevCtrl->wolopts;
+	if (wol->wolopts & WAKE_MAGICSECURE) {
+		put_unaligned_be16(umac->mpd_pw_ms, &wol->sopass[0]);
+		put_unaligned_be32(umac->mpd_pw_ls, &wol->sopass[2]);
+	} else {
+		memset(&wol->sopass[0], 0, sizeof(wol->sopass));
+	}
+}
+
+/*
+ * ethtool function - set WOL (Wake on LAN) settings.
+ * Only for magic packet detection mode.
+ */
+static int bcmgenet_set_wol(struct net_device *dev,
+		struct ethtool_wolinfo *wol)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	volatile struct uniMacRegs *umac = pDevCtrl->umac;
+
+	if (wol->wolopts & ~(WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_ARP))
+		return -EINVAL;
+
+	if (wol->wolopts & WAKE_MAGICSECURE) {
+		umac->mpd_pw_ms = get_unaligned_be16(&wol->sopass[0]);
+		umac->mpd_pw_ls = get_unaligned_be32(&wol->sopass[2]);
+		umac->mpd_ctrl |= MPD_PW_EN;
+	}
+
+	device_set_wakeup_enable(&dev->dev, wol->wolopts);
+	pDevCtrl->wolopts = wol->wolopts;
+	return 0;
+}
+/*
+ * ethtool function - get generic settings.
+ */
+static int bcmgenet_get_settings(struct net_device *dev,
+		struct ethtool_cmd *cmd)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	int rc = 0;
+
+	if (pDevCtrl->phyType == BRCM_PHY_TYPE_MOCA) {
+		/* see comments in bcmgenet_set_settings() */
+		cmd->autoneg = netif_carrier_ok(pDevCtrl->dev);
+		cmd->speed = SPEED_1000;
+		cmd->duplex = DUPLEX_HALF;
+		cmd->port = PORT_BNC;
+	} else {
+		if (!netif_running(dev))
+			return -EINVAL;
+
+		if (pDevCtrl->extPhy)
+			cmd->transceiver = XCVR_EXTERNAL;
+
+		rc = mii_ethtool_gset(&pDevCtrl->mii, cmd);
+	}
+
+	return rc;
+}
+/*
+ * ethtool function - set settings.
+ */
+static int bcmgenet_set_settings(struct net_device *dev,
+		struct ethtool_cmd *cmd)
+{
+	int err = 0;
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+
+	if (pDevCtrl->phyType == BRCM_PHY_TYPE_MOCA) {
+		/* mocad uses cmd->autoneg to control our RUNNING flag */
+		if (cmd->autoneg)
+			netif_carrier_on(pDevCtrl->dev);
+		else
+			netif_carrier_off(pDevCtrl->dev);
+	} else {
+		if (!netif_running(dev))
+			return -EINVAL;
+
+		err = mii_ethtool_sset(&pDevCtrl->mii, cmd);
+		if (err < 0)
+			return err;
+		bcmgenet_mii_setup(dev, 0);
+
+		if (cmd->maxrxpkt != 0)
+			DmaDescThres = cmd->maxrxpkt;
+	}
+
+	return err;
+}
+/*
+ * ethtool function - get driver info.
+ */
+static int bcmgenet_set_rx_csum(struct net_device *dev)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	spin_lock_bh(&pDevCtrl->bh_lock);
+	if (!(dev->flags & NETIF_F_RXCSUM)) {
+		/*pDevCtrl->rbuf->rbuf_endian_ctrl &= ~RBUF_ENDIAN_NOSWAP;*/
+		pDevCtrl->rbuf->rbuf_ctrl &= ~RBUF_64B_EN;
+		pDevCtrl->rbuf->rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
+	} else {
+		/*pDevCtrl->rbuf->rbuf_endian_ctrl &= ~RBUF_ENDIAN_NOSWAP;*/
+		pDevCtrl->rbuf->rbuf_ctrl |= RBUF_64B_EN;
+		pDevCtrl->rbuf->rbuf_chk_ctrl |= RBUF_RXCHK_EN ;
+	}
+	spin_unlock_bh(&pDevCtrl->bh_lock);
+	return 0;
+}
+static int bcmgenet_set_tx_csum(struct net_device *dev)
+{
+	unsigned long flags;
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	spin_lock_irqsave(&pDevCtrl->lock, flags);
+	if (!(dev->features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))) {
+		GENET_TBUF_CTRL(pDevCtrl) &= ~RBUF_64B_EN;
+		if (dev->needed_headroom > 64)
+			dev->needed_headroom -= 64;
+	} else {
+		GENET_TBUF_CTRL(pDevCtrl) |= RBUF_64B_EN;
+		if (dev->needed_headroom < 64)
+			dev->needed_headroom += 64;
+	}
+	spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+	return 0;
+}
+static int bcmgenet_set_sg(struct net_device *dev)
+{
+	if ((dev->features & NETIF_F_SG) &&
+			!(dev->features & NETIF_F_IP_CSUM)) {
+		printk(KERN_WARNING "Tx Checksum offloading disabled, not setting SG\n");
+		return -EINVAL;
+	}
+	/* must have 64B tx status enabled */
+	return 0;
+}
+static int bcmgenet_set_features(struct net_device *dev,
+		netdev_features_t features)
+{
+	int ret;
+	netdev_features_t changed = features ^ dev->features;
+	if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
+		ret = bcmgenet_set_tx_csum(dev);
+	if (changed & (NETIF_F_RXCSUM))
+		ret = bcmgenet_set_rx_csum(dev);
+	if (changed & NETIF_F_SG)
+		ret = bcmgenet_set_sg(dev);
+
+	return ret;
+}
+
+/* standard ethtool support functions. */
+enum bcmgenet_stat_type {
+	BCMGENET_STAT_NETDEV = -1,
+	BCMGENET_STAT_MIB_RX,
+	BCMGENET_STAT_MIB_TX,
+	BCMGENET_STAT_RUNT,
+	BCMGENET_STAT_MISC,
+};
+
+struct bcmgenet_stats {
+	char stat_string[ETH_GSTRING_LEN];
+	int stat_sizeof;
+	int stat_offset;
+	enum bcmgenet_stat_type type;
+	/* reg offset from UMAC base for misc counters */
+	u16 reg_offset;
+};
+
+#define STAT_NETDEV(m) { \
+	.stat_string = __stringify(m), \
+	.stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
+	.stat_offset = offsetof(struct net_device_stats, m), \
+	.type = BCMGENET_STAT_NETDEV, \
+}
+
+#define STAT_GENET_MIB(str, m, _type) { \
+	.stat_string = str, \
+	.stat_sizeof = sizeof(((struct BcmEnet_devctrl *)0)->m), \
+	.stat_offset = offsetof(struct BcmEnet_devctrl, m), \
+	.type = _type, \
+}
+
+#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
+#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
+#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
+
+#define STAT_GENET_MISC(str, m, offset) { \
+	.stat_string = str, \
+	.stat_sizeof = sizeof(((struct BcmEnet_devctrl *)0)->m), \
+	.stat_offset = offsetof(struct BcmEnet_devctrl, m), \
+	.type = BCMGENET_STAT_MISC, \
+	.reg_offset = offset, \
+}
+
+
+/* There is a 0xC gap between the end of RX and beginning of TX stats and then
+ * between the end of TX stats and the beginning of the RX RUNT
+ */
+#define BCMGENET_STAT_OFFSET	0xc
+
+/* Hardware counters must be kept in sync because the order/offset
+ * is important here (order in structure declaration = order in hardware)
+ */
+static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
+	/* general stats */
+	STAT_NETDEV(rx_packets),
+	STAT_NETDEV(tx_packets),
+	STAT_NETDEV(rx_bytes),
+	STAT_NETDEV(tx_bytes),
+	STAT_NETDEV(rx_errors),
+	STAT_NETDEV(tx_errors),
+	STAT_NETDEV(rx_dropped),
+	STAT_NETDEV(tx_dropped),
+	STAT_NETDEV(multicast),
+	/* UniMAC RSV counters */
+	STAT_GENET_MIB_RX("rx_64_octets", mib.rx.stat_sz.cnt_64),
+	STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.stat_sz.cnt_127),
+	STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.stat_sz.cnt_255),
+	STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.stat_sz.cnt_511),
+	STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.stat_sz.cnt_1023),
+	STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.stat_sz.cnt_1518),
+	STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.stat_sz.cnt_mgv),
+	STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.stat_sz.cnt_2047),
+	STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.stat_sz.cnt_4095),
+	STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.stat_sz.cnt_9216),
+	STAT_GENET_MIB_RX("rx_pkts", mib.rx.rx_pkt),
+	STAT_GENET_MIB_RX("rx_bytes", mib.rx.rx_bytes),
+	STAT_GENET_MIB_RX("rx_multicast", mib.rx.rx_mca),
+	STAT_GENET_MIB_RX("rx_broadcast", mib.rx.rx_bca),
+	STAT_GENET_MIB_RX("rx_fcs", mib.rx.rx_fcs),
+	STAT_GENET_MIB_RX("rx_control", mib.rx.rx_cf),
+	STAT_GENET_MIB_RX("rx_pause", mib.rx.rx_pf),
+	STAT_GENET_MIB_RX("rx_unknown", mib.rx.rx_uo),
+	STAT_GENET_MIB_RX("rx_align", mib.rx.rx_aln),
+	STAT_GENET_MIB_RX("rx_outrange", mib.rx.rx_flr),
+	STAT_GENET_MIB_RX("rx_code", mib.rx.rx_cde),
+	STAT_GENET_MIB_RX("rx_carrier", mib.rx.rx_fcr),
+	STAT_GENET_MIB_RX("rx_oversize", mib.rx.rx_ovr),
+	STAT_GENET_MIB_RX("rx_jabber", mib.rx.rx_jbr),
+	STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.rx_mtue),
+	STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.rx_pok),
+	STAT_GENET_MIB_RX("rx_unicast", mib.rx.rx_uc),
+	STAT_GENET_MIB_RX("rx_ppp", mib.rx.rx_ppp),
+	STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
+	/* UniMAC TSV counters */
+	STAT_GENET_MIB_TX("tx_64_octets", mib.tx.stat_sz.cnt_64),
+	STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.stat_sz.cnt_127),
+	STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.stat_sz.cnt_255),
+	STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.stat_sz.cnt_511),
+	STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.stat_sz.cnt_1023),
+	STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.stat_sz.cnt_1518),
+	STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.stat_sz.cnt_mgv),
+	STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.stat_sz.cnt_2047),
+	STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.stat_sz.cnt_4095),
+	STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.stat_sz.cnt_9216),
+	STAT_GENET_MIB_TX("tx_pkts", mib.tx.tx_pkt),
+	STAT_GENET_MIB_TX("tx_multicast", mib.tx.tx_mca),
+	STAT_GENET_MIB_TX("tx_broadcast", mib.tx.tx_bca),
+	STAT_GENET_MIB_TX("tx_pause", mib.tx.tx_pf),
+	STAT_GENET_MIB_TX("tx_control", mib.tx.tx_cf),
+	STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.tx_fcs),
+	STAT_GENET_MIB_TX("tx_oversize", mib.tx.tx_ovr),
+	STAT_GENET_MIB_TX("tx_defer", mib.tx.tx_drf),
+	STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.tx_edf),
+	STAT_GENET_MIB_TX("tx_single_col", mib.tx.tx_scl),
+	STAT_GENET_MIB_TX("tx_multi_col", mib.tx.tx_mcl),
+	STAT_GENET_MIB_TX("tx_late_col", mib.tx.tx_lcl),
+	STAT_GENET_MIB_TX("tx_excess_col", mib.tx.tx_ecl),
+	STAT_GENET_MIB_TX("tx_frags", mib.tx.tx_frg),
+	STAT_GENET_MIB_TX("tx_total_col", mib.tx.tx_ncl),
+	STAT_GENET_MIB_TX("tx_jabber", mib.tx.tx_jbr),
+	STAT_GENET_MIB_TX("tx_bytes", mib.tx.tx_bytes),
+	STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.tx_pok),
+	STAT_GENET_MIB_TX("tx_unicast", mib.tx.tx_uc),
+	/* UniMAC RUNT counters */
+	STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
+	STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
+	STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
+	STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
+	/* Misc UniMAC counters */
+	STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
+			UMAC_RBUF_OVFL_CNT),
+	STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
+	STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
+};
+
+#define BCMGENET_STATS_LEN	ARRAY_SIZE(bcmgenet_gstrings_stats)
+
+static void bcmgenet_get_drvinfo(struct net_device *dev,
+		struct ethtool_drvinfo *info)
+{
+	strncpy(info->driver, CARDNAME, sizeof(info->driver));
+	strncpy(info->version, VER_STR, sizeof(info->version));
+	info->n_stats = BCMGENET_STATS_LEN;
+}
+
+static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
+{
+	switch (string_set) {
+	case ETH_SS_STATS:
+		return BCMGENET_STATS_LEN;
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static void bcmgenet_get_strings(struct net_device *dev,
+				u32 stringset, u8 *data)
+{
+	int i;
+
+	switch (stringset) {
+	case ETH_SS_STATS:
+		for (i = 0; i < BCMGENET_STATS_LEN; i++) {
+			memcpy(data + i * ETH_GSTRING_LEN,
+				bcmgenet_gstrings_stats[i].stat_string,
+				ETH_GSTRING_LEN);
+		}
+		break;
+	}
+}
+
+static void bcmgenet_update_mib_counters(struct BcmEnet_devctrl *priv)
+{
+	int i, j = 0;
+
+	for (i = 0; i < BCMGENET_STATS_LEN; i++) {
+		const struct bcmgenet_stats *s;
+		u32 val;
+		char *p;
+		u8 offset = 0;
+
+		s = &bcmgenet_gstrings_stats[i];
+		switch (s->type) {
+		case BCMGENET_STAT_NETDEV:
+			continue;
+		case BCMGENET_STAT_MIB_RX:
+		case BCMGENET_STAT_MIB_TX:
+		case BCMGENET_STAT_RUNT:
+			if (s->type != BCMGENET_STAT_MIB_RX)
+				offset = BCMGENET_STAT_OFFSET;
+			val = DEV_RD(priv->dev->base_addr +
+					GENET_UMAC_OFF + UMAC_MIB_START +
+					j + offset);
+			break;
+		case BCMGENET_STAT_MISC:
+			val = DEV_RD(priv->dev->base_addr + GENET_UMAC_OFF + s->reg_offset);
+			/* clear if overflowed */
+			if (val == ~0)
+				DEV_WR(priv->dev->base_addr + GENET_UMAC_OFF + s->reg_offset, 0);
+			break;
+		}
+
+		j += s->stat_sizeof;
+		p = (char *)priv + s->stat_offset;
+		*(u32 *)p = val;
+	}
+}
+
+static void bcmgenet_get_ethtool_stats(struct net_device *dev,
+					struct ethtool_stats *stats,
+					u64 *data)
+{
+	struct BcmEnet_devctrl *priv = netdev_priv(dev);
+	int i;
+
+	mutex_lock(&priv->mib_mutex);
+	if (netif_running(dev))
+		bcmgenet_update_mib_counters(priv);
+
+	for (i = 0; i < BCMGENET_STATS_LEN; i++) {
+		const struct bcmgenet_stats *s;
+		char *p;
+
+		s = &bcmgenet_gstrings_stats[i];
+		if (s->type == -1)
+			p = (char *)&dev->stats;
+		else
+			p = (char *)priv;
+		p += s->stat_offset;
+		data[i] = *(u32 *)p;
+	}
+	mutex_unlock(&priv->mib_mutex);
+}
+
+/*
+ * standard ethtool support functions.
+ */
+static struct ethtool_ops bcmgenet_ethtool_ops = {
+	.get_settings		= bcmgenet_get_settings,
+	.set_settings		= bcmgenet_set_settings,
+	.get_drvinfo		= bcmgenet_get_drvinfo,
+	.get_wol			= bcmgenet_get_wol,
+	.set_wol			= bcmgenet_set_wol,
+	.get_link			= ethtool_op_get_link,
+	.get_strings		= bcmgenet_get_strings,
+	.get_sset_count		= bcmgenet_get_sset_count,
+	.get_ethtool_stats	= bcmgenet_get_ethtool_stats,
+};
+
+static int bcmgenet_enable_arp_filter(struct BcmEnet_devctrl *pDevCtrl)
+{
+	struct net_device *dev = pDevCtrl->dev;
+	unsigned int ip;
+
+	ip = bcmgenet_getip(dev);
+	if (ip) {
+		/* clear the lower halfwords */
+		hfb_arp[HFB_ARP_LEN-2] &= ~0xffff;
+		hfb_arp[HFB_ARP_LEN-1] &= ~0xffff;
+		hfb_arp[HFB_ARP_LEN-2] |= (ip >> 16);
+		hfb_arp[HFB_ARP_LEN-1] |= (ip & 0xFFFF);
+		/* Enable HFB, to response to ARP request.*/
+		if (bcmgenet_update_hfb(dev, hfb_arp, HFB_ARP_LEN, 0) < 0) {
+			printk(KERN_ERR "%s: Unable to update HFB\n",
+			       __func__);
+			return -1;
+		}
+		GENET_HFB_CTRL(pDevCtrl) |= RBUF_HFB_EN;
+		return 0;
+	}
+
+	return -1;
+}
+/*
+ * Power down the unimac, based on mode.
+ */
+static void bcmgenet_power_down(struct BcmEnet_devctrl *pDevCtrl, int mode)
+{
+	struct net_device *dev;
+	int retries = 0;
+
+	dev = pDevCtrl->dev;
+	switch (mode) {
+	case GENET_POWER_CABLE_SENSE:
+#if 0
+		/*
+		 * EPHY bug, setting ext_pwr_down_dll and ext_pwr_down_phy cause
+		 * link IRQ bouncing.
+		 */
+		pDevCtrl->ext->ext_pwr_mgmt |= (EXT_PWR_DOWN_PHY |
+				EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
+#else
+		/* Workaround for putting EPHY in iddq mode. */
+		pDevCtrl->mii.mdio_write(dev, pDevCtrl->phyAddr, 0x1f, 0x008b);
+		pDevCtrl->mii.mdio_write(dev, pDevCtrl->phyAddr, 0x10, 0x01c0);
+		pDevCtrl->mii.mdio_write(dev, pDevCtrl->phyAddr, 0x14, 0x7000);
+		pDevCtrl->mii.mdio_write(dev, pDevCtrl->phyAddr, 0x1f, 0x000f);
+		pDevCtrl->mii.mdio_write(dev, pDevCtrl->phyAddr, 0x10, 0x20d0);
+		pDevCtrl->mii.mdio_write(dev, pDevCtrl->phyAddr, 0x1f, 0x000b);
+
+#endif
+		break;
+	case GENET_POWER_WOL_MAGIC:
+		/* disable RX while turning on MPD_EN */
+		pDevCtrl->umac->cmd &= ~CMD_RX_EN;
+		mdelay(10);
+		pDevCtrl->umac->mpd_ctrl |= MPD_EN;
+		while (!(pDevCtrl->rbuf->rbuf_status & RBUF_STATUS_WOL)) {
+			retries++;
+			if (retries > 5) {
+				printk(KERN_CRIT "%s: polling "
+				       "wol mode timeout\n", dev->name);
+				pDevCtrl->umac->mpd_ctrl &= ~MPD_EN;
+				return;
+			}
+			mdelay(1);
+		}
+		printk(KERN_DEBUG "%s: MP WOL-ready status set after "
+		       "%d msec\n", dev->name, retries);
+
+		/* Enable CRC forward */
+		pDevCtrl->umac->cmd |= CMD_CRC_FWD;
+		/* Receiver must be enabled for WOL MP detection */
+		pDevCtrl->umac->cmd |= CMD_RX_EN;
+
+		if (pDevCtrl->ext && pDevCtrl->dev_asleep)
+			pDevCtrl->ext->ext_pwr_mgmt &= ~EXT_ENERGY_DET_MASK;
+
+		pDevCtrl->intrl2_0->cpu_mask_clear |= UMAC_IRQ_MPD_R;
+
+		set_bit(GENET_POWER_WOL_MAGIC, &pDevCtrl->wol_enabled);
+		break;
+	case GENET_POWER_WOL_ACPI:
+		if (bcmgenet_enable_arp_filter(pDevCtrl)) {
+			printk(KERN_CRIT "%s failed to set HFB filter\n",
+			       dev->name);
+			return;
+		}
+		pDevCtrl->umac->cmd &= ~CMD_RX_EN;
+		mdelay(10);
+		GENET_HFB_CTRL(pDevCtrl) |= RBUF_ACPI_EN;
+		while (!(pDevCtrl->rbuf->rbuf_status & RBUF_STATUS_WOL)) {
+			retries++;
+			if (retries > 5) {
+				printk(KERN_CRIT "%s polling "
+				       "wol mode timeout\n", dev->name);
+				GENET_HFB_CTRL(pDevCtrl) &= ~RBUF_ACPI_EN;
+				return;
+			}
+			mdelay(1);
+		}
+		/* Receiver must be enabled for WOL ACPI detection */
+		pDevCtrl->umac->cmd |= CMD_RX_EN;
+		if (pDevCtrl->ext && pDevCtrl->dev_asleep)
+			pDevCtrl->ext->ext_pwr_mgmt &= ~EXT_ENERGY_DET_MASK;
+		printk(KERN_DEBUG "%s: ACPI WOL-ready status set "
+		       "after %d msec\n", dev->name, retries);
+		/* enable HFB match interrupts */
+		pDevCtrl->intrl2_0->cpu_mask_clear |= (UMAC_IRQ_HFB_MM |
+				UMAC_IRQ_HFB_SM);
+		set_bit(GENET_POWER_WOL_ACPI, &pDevCtrl->wol_enabled);
+		break;
+	case GENET_POWER_PASSIVE:
+		/* Power down LED */
+		bcmgenet_mii_reset(pDevCtrl->dev);
+		if (pDevCtrl->ext)
+			pDevCtrl->ext->ext_pwr_mgmt |= (EXT_PWR_DOWN_PHY |
+				EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
+		break;
+	default:
+		break;
+	}
+
+}
+static void bcmgenet_power_up(struct BcmEnet_devctrl *pDevCtrl, int mode)
+{
+	switch (mode) {
+	case GENET_POWER_CABLE_SENSE:
+#if 0
+		pDevCtrl->ext->ext_pwr_mgmt &= ~EXT_PWR_DOWN_DLL;
+		pDevCtrl->ext->ext_pwr_mgmt &= ~EXT_PWR_DOWN_PHY;
+		pDevCtrl->ext->ext_pwr_mgmt &= ~EXT_PWR_DOWN_BIAS;
+#endif
+		/* enable APD */
+		if (pDevCtrl->ext) {
+			pDevCtrl->ext->ext_pwr_mgmt |= EXT_PWR_DN_EN_LD;
+			bcmgenet_mii_reset(pDevCtrl->dev);
+		}
+		break;
+	case GENET_POWER_WOL_MAGIC:
+		pDevCtrl->umac->mpd_ctrl &= ~MPD_EN;
+		/* Disable CRC Forward */
+		pDevCtrl->umac->cmd &= ~CMD_CRC_FWD;
+		/* Stop monitoring magic packet IRQ */
+		pDevCtrl->intrl2_0->cpu_mask_set |= UMAC_IRQ_MPD_R;
+		clear_bit(GENET_POWER_WOL_MAGIC, &pDevCtrl->wol_enabled);
+		break;
+	case GENET_POWER_WOL_ACPI:
+		GENET_HFB_CTRL(pDevCtrl) &= ~RBUF_ACPI_EN;
+		bcmgenet_clear_hfb(pDevCtrl, CLEAR_ALL_HFB);
+		/* Stop monitoring ACPI interrupts */
+		pDevCtrl->intrl2_0->cpu_mask_set |= (UMAC_IRQ_HFB_SM |
+				UMAC_IRQ_HFB_MM);
+		clear_bit(GENET_POWER_WOL_ACPI, &pDevCtrl->wol_enabled);
+		break;
+	case GENET_POWER_PASSIVE:
+		if (pDevCtrl->ext) {
+			pDevCtrl->ext->ext_pwr_mgmt &= ~EXT_PWR_DOWN_DLL;
+			pDevCtrl->ext->ext_pwr_mgmt &= ~EXT_PWR_DOWN_PHY;
+			pDevCtrl->ext->ext_pwr_mgmt &= ~EXT_PWR_DOWN_BIAS;
+			/* enable APD */
+			pDevCtrl->ext->ext_pwr_mgmt |= EXT_PWR_DN_EN_LD;
+			bcmgenet_mii_reset(pDevCtrl->dev);
+		}
+	default:
+		break;
+	}
+	if (pDevCtrl->phyType == BRCM_PHY_TYPE_INT)
+		bcmgenet_ephy_workaround(pDevCtrl->dev);
+}
+/*
+ * ioctl handle special commands that are not present in ethtool.
+ */
+static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	unsigned long flags;
+	struct acpi_data *u_data;
+	int val = 0;
+
+	if (!netif_running(dev))
+		return -EINVAL;
+	/* we can add sub-command in ifr_data if we need to in the future */
+	switch (cmd) {
+	case SIOCSACPISET:
+		spin_lock_irqsave(&pDevCtrl->lock, flags);
+		bcmgenet_power_down(pDevCtrl, GENET_POWER_WOL_ACPI);
+		spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+		break;
+	case SIOCSACPICANCEL:
+		spin_lock_irqsave(&pDevCtrl->lock, flags);
+		bcmgenet_power_up(pDevCtrl, GENET_POWER_WOL_ACPI);
+		spin_unlock_irqrestore(&pDevCtrl->lock, flags);
+		break;
+	case SIOCSPATTERN:
+		u_data = (struct acpi_data *)rq->ifr_data;
+		val =  bcmgenet_update_hfb(dev, (unsigned int *)u_data->p_data,
+				u_data->count, 1);
+		if (val >= 0)
+			put_user(val, &u_data->fltr_index);
+		break;
+	case SIOCGPATTERN:
+		u_data = (struct acpi_data *)rq->ifr_data;
+		val = bcmgenet_read_hfb(dev, u_data);
+		break;
+	case SIOCGMIIPHY:
+	case SIOCGMIIREG:
+	case SIOCSMIIREG:
+		val = generic_mii_ioctl(&pDevCtrl->mii, if_mii(rq), cmd, NULL);
+		break;
+	default:
+		val = -EINVAL;
+		break;
+	}
+
+	return val;
+}
+static const struct net_device_ops bcmgenet_netdev_ops = {
+	.ndo_open = bcmgenet_open,
+	.ndo_stop = bcmgenet_close,
+	.ndo_start_xmit = bcmgenet_xmit,
+#ifdef CONFIG_NET_SCH_MULTIQ
+	.ndo_select_queue = bcmgenet_select_queue,
+#endif
+	.ndo_tx_timeout = bcmgenet_timeout,
+	.ndo_set_rx_mode = bcmgenet_set_rx_mode,
+	.ndo_set_mac_address = bcmgenet_set_mac_addr,
+	.ndo_do_ioctl = bcmgenet_ioctl,
+	.ndo_set_features = bcmgenet_set_features,
+};
+static int bcmgenet_drv_probe(struct platform_device *pdev)
+{
+	struct resource *mres, *ires;
+	void __iomem *base;
+	unsigned long res_size;
+	int err = -EIO;
+	/*
+	 * bcmemac and bcmgenet use same platform data structure.
+	 */
+	struct bcmemac_platform_data *cfg = pdev->dev.platform_data;
+	struct BcmEnet_devctrl *pDevCtrl;
+	struct net_device *dev;
+
+	mres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!mres || !ires) {
+		printk(KERN_ERR "%s: can't get resources\n", __func__);
+		return -EIO;
+	}
+	res_size = resource_size(mres);
+	if (!request_mem_region(mres->start, res_size, CARDNAME)) {
+		printk(KERN_ERR "%s: can't request mem region: start: 0x%x size: %lu\n",
+				CARDNAME, mres->start, res_size);
+		return -ENODEV;
+	}
+	base = ioremap(mres->start, res_size);
+	TRACE(("%s: base=0x%x\n", __func__, (unsigned int)base));
+
+	if (!base) {
+		release_mem_region(mres->start, res_size);
+		printk(KERN_ERR "%s: can't ioremap\n", __func__);
+		return -EIO;
+	}
+
+#ifdef CONFIG_NET_SCH_MULTIQ
+	dev = alloc_etherdev_mq(sizeof(*(pDevCtrl)), GENET_MQ_CNT+1);
+#else
+	dev = alloc_etherdev(sizeof(*pDevCtrl));
+#endif
+	if (dev == NULL) {
+		printk(KERN_ERR "bcmgenet: can't allocate net device\n");
+		err = -ENOMEM;
+		goto err0;
+	}
+	dev->base_addr = (unsigned long)base;
+	pDevCtrl = (struct BcmEnet_devctrl *)netdev_priv(dev);
+	SET_NETDEV_DEV(dev, &pdev->dev);
+	dev_set_drvdata(&pdev->dev, pDevCtrl);
+	memcpy(dev->dev_addr, cfg->macaddr, 6);
+	dev->irq = pDevCtrl->irq0;
+	dev->watchdog_timeo         = 2*HZ;
+	SET_ETHTOOL_OPS(dev, &bcmgenet_ethtool_ops);
+	dev->netdev_ops = &bcmgenet_netdev_ops;
+	netif_napi_add(dev, &pDevCtrl->napi, bcmgenet_poll, TOTAL_DESC);
+	netif_napi_add(dev, &pDevCtrl->ring_napi, bcmgenet_ring_poll, 64);
+
+	netdev_boot_setup_check(dev);
+
+	pDevCtrl->dev = dev;
+	pDevCtrl->irq0 = platform_get_irq(pdev, 0);
+	pDevCtrl->irq1 = platform_get_irq(pdev, 1);
+	pDevCtrl->devnum = pdev->id;
+	/* NOTE: with fast-bridge , must turn this off! */
+	pDevCtrl->bIPHdrOptimize = 1;
+
+	spin_lock_init(&pDevCtrl->lock);
+	spin_lock_init(&pDevCtrl->bh_lock);
+	mutex_init(&pDevCtrl->mdio_mutex);
+	mutex_init(&pDevCtrl->mib_mutex);
+	/* Mii wait queue */
+	init_waitqueue_head(&pDevCtrl->wq);
+
+	pDevCtrl->phyType = cfg->phy_type;
+	pDevCtrl->phySpeed = cfg->phy_speed;
+	if (pDevCtrl->phyType == BRCM_PHY_TYPE_EXT_MII ||
+	    pDevCtrl->phyType == BRCM_PHY_TYPE_EXT_RVMII ||
+	    pDevCtrl->phyType == BRCM_PHY_TYPE_EXT_RGMII ||
+	    pDevCtrl->phyType == BRCM_PHY_TYPE_EXT_RGMII_NO_ID)
+		pDevCtrl->extPhy = 1;
+
+	pDevCtrl->pdev = pdev;
+
+	/* Init GENET registers, Tx/Rx buffers */
+	if (bcmgenet_init_dev(pDevCtrl, true) < 0)
+		goto err1;
+
+	if (cfg->phy_id == BRCM_PHY_ID_AUTO) {
+		if (bcmgenet_mii_probe(dev, cfg) < 0) {
+			printk(KERN_ERR "No PHY detected, not registering interface:%d\n",
+					pdev->id);
+			bcmgenet_clock_disable(pDevCtrl);
+			goto err1;
+		} else {
+			printk(KERN_CRIT "Found PHY at Address %d\n",
+					pDevCtrl->phyAddr);
+		}
+
+	} else {
+		pDevCtrl->phyAddr = cfg->phy_id;
+	}
+
+	bcmgenet_mii_init(dev);
+
+	if (cfg->sw_type) {
+		pDevCtrl->sw_type = cfg->sw_type;
+		bcmgenet_ethsw_init(dev);
+	}
+
+	INIT_WORK(&pDevCtrl->bcmgenet_irq_work, bcmgenet_irq_task);
+
+	if (pDevCtrl->extPhy) {
+		/* No Link status IRQ */
+		INIT_WORK(&pDevCtrl->bcmgenet_link_work,
+				bcmgenet_gphy_link_status);
+		init_timer(&pDevCtrl->timer);
+		pDevCtrl->timer.data = (unsigned long)pDevCtrl;
+		pDevCtrl->timer.function = bcmgenet_gphy_link_timer;
+	} else {
+		/* check link status */
+		bcmgenet_mii_setup(dev, 0);
+	}
+
+	netif_carrier_off(pDevCtrl->dev);
+
+	bcmgenet_clock_disable(pDevCtrl);
+
+	err = register_netdev(dev);
+	if (err != 0)
+		goto err2;
+
+	return 0;
+
+err2:
+	bcmgenet_clock_disable(pDevCtrl);
+	bcmgenet_uninit_dev(pDevCtrl);
+err1:
+	iounmap(base);
+	free_netdev(dev);
+err0:
+	release_mem_region(mres->start, res_size);
+	return err;
+}
+
+static int bcmgenet_drv_remove(struct platform_device *pdev)
+{
+	struct BcmEnet_devctrl *pDevCtrl = dev_get_drvdata(&pdev->dev);
+
+	unregister_netdev(pDevCtrl->dev);
+	free_irq(pDevCtrl->irq0, pDevCtrl);
+	free_irq(pDevCtrl->irq1, pDevCtrl);
+	bcmgenet_uninit_dev(pDevCtrl);
+	iounmap((void __iomem *)pDevCtrl->base_addr);
+	free_netdev(pDevCtrl->dev);
+	return 0;
+}
+
+static int bcmgenet_drv_suspend(struct device *dev)
+{
+	int val = 0;
+	struct BcmEnet_devctrl *pDevCtrl = dev_get_drvdata(dev);
+
+	cancel_work_sync(&pDevCtrl->bcmgenet_irq_work);
+
+	/*
+	 * Save/restore the interface status across PM modes.
+	 * FIXME: Don't use open/close for suspend/resume.
+	 */
+	pDevCtrl->dev_opened = netif_running(pDevCtrl->dev);
+	if (pDevCtrl->dev_opened && !pDevCtrl->dev_asleep) {
+		pDevCtrl->dev_asleep = 1;
+		val = bcmgenet_close(pDevCtrl->dev);
+	}
+
+	return val;
+}
+
+static int bcmgenet_drv_resume(struct device *dev)
+{
+	int val = 0;
+	struct BcmEnet_devctrl *pDevCtrl = dev_get_drvdata(dev);
+
+	if (pDevCtrl->dev_opened)
+		val = bcmgenet_open(pDevCtrl->dev);
+	else {
+		bcmgenet_init_dev(pDevCtrl, false);
+		bcmgenet_clock_disable(pDevCtrl);
+	}
+
+	pDevCtrl->dev_asleep = 0;
+
+	return val;
+}
+
+static struct dev_pm_ops bcmgenet_pm_ops = {
+	.suspend		= bcmgenet_drv_suspend,
+	.resume			= bcmgenet_drv_resume,
+};
+
+
+static struct platform_driver bcmgenet_plat_drv = {
+	.probe =		bcmgenet_drv_probe,
+	.remove =		bcmgenet_drv_remove,
+	.driver = {
+		.name =		"bcmgenet",
+		.owner =	THIS_MODULE,
+		.pm =		&bcmgenet_pm_ops,
+	},
+};
+
+static int bcmgenet_module_init(void)
+{
+	platform_driver_register(&bcmgenet_plat_drv);
+	return 0;
+}
+
+static void bcmgenet_module_cleanup(void)
+{
+	platform_driver_unregister(&bcmgenet_plat_drv);
+}
+
+module_init(bcmgenet_module_init);
+module_exit(bcmgenet_module_cleanup);
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet.h b/drivers/net/ethernet/broadcom/genet/bcmgenet.h
new file mode 100644
index 0000000..9fbf842
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.h
@@ -0,0 +1,212 @@
+/*
+ *
+ * Copyright (c) 2002-2008 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *
+*/
+#ifndef __BCMGENET_H__
+#define __BCMGENET_H__
+
+#define CARDNAME				"bcmgenet"
+#define VERSION     "2.0"
+#define VER_STR     "v" VERSION " " __DATE__ " " __TIME__
+
+#define pr_fmt(fmt)				CARDNAME ": " fmt
+
+#include <linux/skbuff.h>
+#include <linux/netdevice.h>
+#include <linux/spinlock.h>
+#include <linux/clk.h>
+#include <linux/mii.h>
+
+#include "bcmgenet_map.h"
+
+/* total number of Buffer Descriptors, same for Rx/Tx */
+#define TOTAL_DESC				256
+/* which ring is descriptor based */
+#define DESC_INDEX				16
+/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528.
+ * 1536 is multiple of 256 bytes
+ */
+#define ENET_MAX_MTU_SIZE       1536
+#define DMA_MAX_BURST_LENGTH    0x10
+
+#define GENET_TX_RING_COUNT		16
+#define GENET_RX_RING_COUNT		16
+#define GENET_ALLOC_TX_RING		1
+#define GENET_ALLOC_RX_RING		0
+
+#define ETH_CRC_LEN             4
+
+/* misc. configuration */
+#define CLEAR_ALL_HFB			0xFF
+#define DMA_FC_THRESH_HI		(TOTAL_DESC >> 4)
+#define DMA_FC_THRESH_LO		5
+
+
+struct Enet_CB {
+	struct sk_buff      *skb;
+	volatile struct DmaDesc    *BdAddr;
+	DEFINE_DMA_UNMAP_ADDR(dma_addr);
+	DEFINE_DMA_UNMAP_LEN(dma_len);
+};
+
+/* power management mode */
+#define GENET_POWER_CABLE_SENSE	0
+#define GENET_POWER_WOL_MAGIC	1
+#define GENET_POWER_WOL_ACPI	2
+#define GENET_POWER_PASSIVE		3
+
+/*
+ * device context
+ */
+struct BcmEnet_devctrl {
+	struct net_device *dev;	/* ptr to net_device */
+	struct net_device *next_dev;
+	spinlock_t      lock;		/* Serializing lock */
+	spinlock_t		bh_lock;	/* soft IRQ lock */
+	struct mii_if_info mii;		/* mii interface info */
+	struct mutex mdio_mutex;	/* mutex for mii_read/write */
+	wait_queue_head_t	wq;		/* mii wait queue */
+	struct timer_list timer;	/* Link status timer */
+
+	struct napi_struct napi;	/* NAPI for descriptor based rx */
+	struct napi_struct ring_napi;	/* NAPI for ring buffer */
+	unsigned long base_addr;	/* GENET register start address. */
+	volatile struct uniMacRegs *umac;	/* UNIMAC register */
+	volatile struct rbufRegs	*rbuf;	/* rbuf registers */
+	volatile struct intrl2Regs *intrl2_0;	/* INTR2_0 registers */
+	volatile struct intrl2Regs *intrl2_1;	/* INTR2_1 registers */
+	volatile struct SysRegs    *sys;	/* sys register */
+	volatile struct GrBridgeRegs *grb;	/* Grb */
+	volatile struct ExtRegs    *ext;	/* Extention register */
+	volatile unsigned long *hfb;/* HFB registers */
+#if CONFIG_BRCM_GENET_VERSION > 1
+	volatile struct tbufRegs *tbuf;	/* tbuf register for GENET2 */
+	volatile struct hfbRegs  *hfbReg;	/* hfb register for GENET2 */
+#endif
+
+	/* transmit variables */
+	volatile struct tDmaRegs *txDma;/* location of tx Dma register */
+	volatile struct DmaDesc *txBds;	/* location of tx Dma BD ring */
+	struct Enet_CB *txCbs;	/* locaation of tx control block pool */
+	int	nrTxBds;		/* number of transmit bds */
+	int	txFreeBds;		/* # of free transmit bds */
+	int	txLastCIndex;	/* consumer index for the last xmit call */
+
+	struct Enet_CB *txRingCBs[16];	/* tx ring buffer control block*/
+	unsigned int txRingSize[16];	/* size of each tx ring */
+	unsigned int txRingCIndex[16];	/* last consumer index of each ring*/
+	int txRingFreeBds[16];	/* # of free bds for each ring */
+	unsigned char *txRingStart[16];	/* tx ring start addr */
+
+	/* receive variables */
+	volatile struct rDmaRegs *rxDma;	/* location of rx dma  */
+	volatile struct DmaDesc *rxBds;		/* location of rx bd ring */
+	volatile struct DmaDesc *rxBdAssignPtr;	/*next rx bd to assign buffer*/
+	struct Enet_CB *rxCbs;	/* location of rx control block pool */
+	int	nrRxBds;	/* number of receive bds */
+	int	rxBufLen;	/* size of rx buffers for DMA */
+
+	struct Enet_CB *rxRingCbs[16];	/* rx ring buffer control */
+	unsigned int rxRingSize[16];	/* size of each ring */
+	unsigned int rxRingCIndex[16];	/* consumer index for each ring */
+	unsigned int rxRingDiscCnt[16];	/* # of discarded pkt for each ring */
+	unsigned char *rxRingStart[16];	/* ring buffer start addr.*/
+
+	/* other misc variables */
+	int irq0;	/* regular IRQ */
+	int	irq1;	/* ring buf IRQ */
+	int phyAddr;
+	int	phyType;
+	int	phySpeed;
+	int	extPhy;
+	int	sw_type;
+	int	sw_addr;
+	int	bIPHdrOptimize;
+	unsigned int irq0_stat;	/* sw copy of irq0 status, for IRQ BH */
+	unsigned int irq1_stat;	/* sw copy of irq1 status, for NAPI rx */
+
+	struct work_struct bcmgenet_irq_work;	/* bottom half work */
+	struct work_struct bcmgenet_link_work;	/* GPHY link status work */
+	int    devnum;		/* 0=EMAC_0, 1=EMAC_1 */
+	struct clk *clk;
+	int dev_opened;		/* device opened. */
+	int dev_asleep;		/* device is at sleep */
+	struct platform_device *pdev;
+
+	/* WOL */
+	unsigned long	wol_enabled;
+	struct	clk *clk_wol;
+	int	clock_active;
+	u32	wolopts;
+
+	/* S3 warm boot */
+	struct DmaDesc saved_rx_desc[TOTAL_DESC];
+	u32 int_mask;
+	u32 rbuf_ctrl;
+
+	struct mutex mib_mutex;
+	struct bcmgenet_mib_counters mib;
+};
+
+#if defined(CONFIG_BCMGENET_DUMP_TRACE)
+#define TRACE(x)        (printk x)
+#else
+#define TRACE(x)
+#endif
+
+/* These macros are defined to deal with register map change
+ * between GENET1.1 and GENET2. Only those currently being used
+ * by driver are defined.
+ */
+#if CONFIG_BRCM_GENET_VERSION > 1
+
+#define GENET_TBUF_CTRL(pdev)			(pdev->tbuf->tbuf_ctrl)
+#define GENET_TBUF_BP_MC(pdev)			(pdev->tbuf->tbuf_bp_mc)
+#define GENET_TBUF_ENDIAN_CTRL(pdev)	(pdev->tbuf->tbuf_endian_ctrl)
+#define GENET_TBUF_FLUSH_CTRL(pdev)		(pdev->sys->tbuf_flush_ctrl)
+#define GENET_RBUF_FLUSH_CTRL(pdev)		(pdev->sys->rbuf_flush_ctrl)
+#define GENET_RGMII_OOB_CTRL(pdev)		(pdev->ext->rgmii_oob_ctrl)
+#define GENET_RGMII_IB_STATUS(pdev)		(pdev->ext->rgmii_ib_status)
+#define GENET_RGMII_LED_STATUS(pdev)	(pdev->ext->rgmii_led_ctrl)
+#define GENET_HFB_CTRL(pdev)			(pdev->hfbReg->hfb_ctrl)
+#define GENET_HFB_FLTR_LEN(pdev, i)		(pdev->hfbReg->hfb_fltr_len[i])
+
+#else
+
+#define GENET_TBUF_CTRL(pdev)			(pdev->rbuf->tbuf_ctrl)
+#define GENET_TBUF_BP_MC(pdev)			(pdev->rbuf->tbuf_bp_mc)
+#define GENET_TBUF_ENDIAN_CTRL(pdev)		(pdev->rbuf->tbuf_endian_ctrl)
+#define GENET_TBUF_FLUSH_CTRL(pdev)		(pdev->rbuf->tbuf_flush_ctrl)
+#define GENET_RBUF_FLUSH_CTRL(pdev)		(pdev->rbuf->rbuf_flush_ctrl)
+#define GENET_RGMII_OOB_CTRL(pdev)		(pdev->rbuf->rgmii_oob_ctrl)
+#define GENET_RGMII_IB_STATUS(pdev)		(pdev->rbuf->rgmii_ib_status)
+#define GENET_RGMII_LED_STATUS(pdev)		(pdev->rbuf->rgmii_led_ctrl)
+#define GENET_HFB_CTRL(pdev)			(pdev->rbuf->rbuf_hfb_ctrl)
+#define GENET_HFB_FLTR_LEN(pdev, i)		(pdev->rbuf->rbuf_fltr_len[i])
+
+#endif /* CONFIG_BRCM_GENET_VERSION > 1 */
+
+#if CONFIG_BRCM_GENET_VERSION < 3
+#define GENET_BP_IN_EN_SHIFT			16
+#define GENET_BP_MASK				0xffff
+#else
+#define GENET_BP_IN_EN_SHIFT			17
+#define GENET_BP_MASK				0x1ffff
+#endif
+
+#endif /* __BCMGENET_H__ */
diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet_defs.h b/drivers/net/ethernet/broadcom/genet/bcmgenet_defs.h
new file mode 100644
index 0000000..6ca2e0f
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet/bcmgenet_defs.h
@@ -0,0 +1,288 @@
+/*
+ * Copyright (c) 2002-2008 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *
+*/
+/* uniMac common macro definations(chip revision independent, idealy!)
+ *
+ * NOTE: the comments "group start" "group end" "non-proc" are for assisting
+ * perl script parsing, DONT'T delete it.
+ *
+ * Revision: 10/03/2008, L.Sun, created.
+ */
+#ifndef __UNIMAC_DEFS_H__
+#define __UNIMAC_DEFS_H__
+
+#include <linux/bitops.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define UMAC_SPEED_10			0
+#define UMAC_SPEED_100			1
+#define UMAC_SPEED_1000			2
+#define UMAC_SPEED_2500			3
+
+#define PORT_MODE_INT_EPHY		0
+#define PORT_MODE_INT_GPHY		1
+#define PORT_MODE_EXT_EPHY		2
+#define PORT_MODE_EXT_GPHY		3
+#define PORT_MODE_EXT_RVMII_25		(4 | BIT(4))
+#define PORT_MODE_EXT_RVMII_50		4
+
+#define LED_ACT_SOURCE_MAC		(1 << 9)
+
+/* umac register group start */
+/* reg: umac->hdBkpCtrl */
+/* Enable half-duplex flow control.*/
+#define	HD_FC_EN				(1 << 0)
+/* Enable back-off algorithm. */
+#define HD_FC_BKOFF_OK			(1 << 1)
+#define IPG_CONFIG_RX_SHIFT		2
+#define IPG_CONFIG_RX_MASK		0x1F
+/* reg: umac->cmd */
+#define CMD_TX_EN				(1 << 0)
+#define CMD_RX_EN				(1 << 1)
+#define CMD_SPEED_SHIFT			2
+#define CMD_SPEED_MASK			3
+#define CMD_PROMISC				(1 << 4)
+#define CMD_PAD_EN				(1 << 5)
+#define CMD_CRC_FWD				(1 << 6)
+#define CMD_PAUSE_FWD			(1 << 7)
+#define CMD_RX_PAUSE_IGNORE		(1 << 8)
+#define CMD_TX_ADDR_INS			(1 << 9)
+#define CMD_HD_EN				(1 << 10)
+#define CMD_SW_RESET			(1 << 13)
+#define CMD_LCL_LOOP_EN			(1 << 15)
+#define CMD_AUTO_CONFIG			(1 << 22)
+#define CMD_CNTL_FRM_EN			(1 << 23)
+#define CMD_NO_LEN_CHK			(1 << 24)
+#define CMD_RMT_LOOP_EN			(1 << 25)
+#define CMD_PRBL_EN				(1 << 27)
+#define CMD_TX_PAUSE_IGNORE		(1 << 28)
+#define CMD_TX_RX_EN			(1 << 29)
+#define CMD_RUNT_FILTER_DIS		(1 << 30)
+/* reg: umac->mode */
+#define MODE_HD					(1 << 0)
+#define MODE_RX_PAUSE_EN		(1 << 3)
+#define MODE_TX_PAUSE_EN		(1 << 4)
+/* reg: umac->macsec_ctrl */
+#define TX_LANUCH_EN			(1 << 0)
+#define TX_CRC_CORRUPT_EN		(1 << 4)
+#define TX_CRC_PROGRAM			(1 << 5)
+#define PAUSE_CTRL_EN			(1 << 17)
+/* reg: umac->ts_status */
+#define TX_TS_FIFO_FULL			(1 << 0)
+#define TX_TS_FIFO_EMPTY		(1 << 1)
+/* reg: umac->txfifo_status */
+#define TX_FIFO_OVERRUN			(1 << 1)
+#define TX_FIFO_UNDERRUN		(1 << 0)
+/* reg: umac->ppp_ctrl */
+#define PPP_EN_TX				(1 << 0)
+#define PPP_EN_RX				(1 << 1)
+#define PPP_FORCE_XON			(1 << 2)
+/* reg: umac_ppp_refresh_ctrl */
+#define PPP_REFRESH_EN			(1 << 0)
+/* reg: umac->mib_ctrl */
+#define MIB_RESET_RX			(1 << 0)
+#define MIB_RESET_RUNT			(1 << 1)
+#define MIB_RESET_TX			(1 << 2)
+/* reg: umac->mpd_ctrl */
+#define MPD_EN					(1 << 0)
+#define MPD_PW_EN				(1 << 27)
+#define MPD_MSEQ_LEN_SHIFT		16
+#define MPD_MSEQ_LEN_MASK		0xFF
+/* reg: umac->mdio_cmd, non-proc export */
+#define MDIO_START_BUSY			(1 << 29)
+#define MDIO_READ_FAIL			(1 << 28)
+#define MDIO_RD					(2 << 26)
+#define MDIO_WR					(1 << 26)
+#define MDIO_PMD_SHIFT			21
+#define MDIO_PMD_MASK			0x1F
+#define MDIO_REG_SHIFT 			16
+#define MDIO_REG_MASK			0x1F
+/* umac register group end */
+
+/* rbuf register group start */
+/* reg: rbuf->rbuf_ctrl */
+#define RBUF_64B_EN				(1 << 0)
+#define RBUF_ALIGN_2B			(1 << 1)
+#define RBUF_BAD_DIS			(1 << 2)
+/* reg: rbuf->rbuf_status */
+#define RBUF_STATUS_WOL			(1 << 0)
+#define RBUF_STATUS_MPD_INTR_ACTIVE		(1 << 1)
+#define RBUF_STATUS_ACPI_INTR_ACTIVE	(1 << 2)
+/* reg: rbuf->rbuf_endian_ctrl */
+#define RBUF_SWAP_EN			(1 << 2)
+#define RBUF_BIG_ENDIAN_MODE	(1 << 0)
+#define RBUF_REG_MODE			(1 << 1)
+/* reg: rbuf->rbuf_chk_ctrl */
+#define RBUF_RXCHK_EN			(1 << 0)
+#define RBUF_SKIP_FCS			(1 << 4)
+/* reg: rbuf->rbuf_hfb_ctrl */
+#define RBUF_HFB_FILTER_EN_SHIFT	16
+#define RBUF_HFB_FILTER_EN_MASK	0xffff0000
+#define RBUF_HFB_EN				(1 << 0)
+#define RBUF_HFB_256B			(1 << 1)
+#define RBUF_ACPI_EN			(1 << 2)
+/* reg: rbuf->rbuf_fltr_len */
+#define RBUF_FLTR_LEN_MASK		0xFF
+#define RBUF_FLTR_LEN_SHIFT		8
+/* reg: rbuf->tbuf_bp_mc */
+#define TBUF_CPU_BP				(1 << 8)
+/* reg: rbuf->rgmii_oob_ctrl */
+#define RGMII_MODE_EN			(1 << 0)
+#define RGMII_LINK				(1 << 4)
+#define OOB_DISABLE				(1 << 5)
+#define ID_MODE_DIS				(1 << 16)
+/* rbuf register group end */
+
+/* ext register group start */
+/* reg: ext->ephy_pwr_mgmt */
+#define EXT_PWR_DOWN_BIAS		(1 << 0)
+#define EXT_PWR_DOWN_DLL		(1 << 1)
+#define EXT_PWR_DOWN_PHY		(1 << 2)
+#define EXT_PWR_DN_EN_LD		(1 << 3)
+#define EXT_ENERGY_DET			(1 << 4)
+#define EXT_IDDQ_FROM_PHY		(1 << 5)
+#define EXT_PHY_RESET			(1 << 8)
+#define EXT_ENERGY_DET_MASK		(1 << 12)
+
+/* reg: ext->emcg_ctrl */
+#define EXT_Ck25_EN				(1 << 0)
+#define EPHY_CLK_SEL			(1 << 4)
+
+/* intrl2_0 register group start */
+/* reg: intrl2_0->cpu_mask_status, others are same */
+#define UMAC_IRQ_SCB			(1 << 0)
+#define UMAC_IRQ_EPHY			(1 << 1)
+#define UMAC_IRQ_PHY_DET_R		(1 << 2)
+#define UMAC_IRQ_PHY_DET_F		(1 << 3)
+#define UMAC_IRQ_LINK_UP		(1 << 4)
+#define UMAC_IRQ_LINK_DOWN		(1 << 5)
+#define UMAC_IRQ_UMAC			(1 << 6)
+#define UMAC_IRQ_UMAC_TSV		(1 << 7)
+#define UMAC_IRQ_TBUF_UNDERRUN	(1 << 8)
+#define UMAC_IRQ_RBUF_OVERFLOW	(1 << 9)
+#define UMAC_IRQ_HFB_SM			(1 << 10)
+#define UMAC_IRQ_HFB_MM			(1 << 11)
+#define UMAC_IRQ_MPD_R			(1 << 12)
+#define UMAC_IRQ_RXDMA_MBDONE	(1 << 13)
+#define UMAC_IRQ_RXDMA_PDONE	(1 << 14)
+#define UMAC_IRQ_RXDMA_BDONE	(1 << 15)
+#define UMAC_IRQ_TXDMA_MBDONE	(1 << 16)
+#define UMAC_IRQ_TXDMA_PDONE	(1 << 17)
+#define UMAC_IRQ_TXDMA_BDONE	(1 << 18)
+
+#define DMA_RW_POINTER_MASK		0x1FF
+/* reg: rDmaRingRegs->rdma_producer_index */
+#define DMA_P_INDEX_DISCARD_CNT_MASK		0xFFFF
+#define DMA_P_INDEX_DISCARD_CNT_SHIFT		16
+#define DMA_BUFFER_DONE_CNT_MASK			0xFFFF
+#define DMA_BUFFER_DONE_CNT_SHIFT			16
+#define DMA_P_INDEX_MASK					0xFFFF
+#define DMA_C_INDEX_MASK					0xFFFF
+/* reg: rDmaRingRegs->rdma_ring_buf_size */
+#define DMA_RING_SIZE_MASK					0xFFFF
+#define DMA_RING_SIZE_SHIFT					16
+#define DMA_RING_BUFFER_SIZE_MASK			0xFFFF
+/* reg: rDmaRingRegs->rdma_mbuf_done_threshold */
+#define DMA_INTR_THRESHOLD_MASK				0x00FF
+/* reg: rDmaRingRegs->rdma_xon_xoff_threshold */
+#define DMA_XON_THREHOLD_MASK				0xFFFF
+#define DMA_XOFF_THRESHOLD_MASK				0xFFFF
+#define DMA_XOFF_THRESHOLD_SHIFT			16
+/* reg: dDmaRingRegs->tdma_flow_period */
+#define DMA_FLOW_PERIOD_MASK				0xFFFF
+#define DMA_MAX_PKT_SIZE_MASK				0xFFFF
+#define DMA_MAX_PKT_SIZE_SHIFT				16
+
+/* rdma register group start */
+/* reg: rDmaRegs->rdma_ctrl */
+#define DMA_EN								(1 << 0)
+#define DMA_RING_BUF_EN_SHIFT				0x01
+#define DMA_RING_BUF_EN_MASK				0xFFFF
+#define DMA_TSB_SWAP_EN						(1 << 20)
+/* reg : rDmaRegs->rdma_status */
+#define DMA_DISABLED						(1 << 0)
+#define DMA_DESC_RAM_INIT_BUSY				(1 << 1)
+/* reg: rDmaRegs->rdma_scb_burst_size */
+#define DMA_SCB_BURST_SIZE_MASK				0x1F
+/* reg: rDmaRegs->rdma_activity */
+#define DMA_ACTIVITY_VECTOR_MASK			0x1FFFF
+/* reg: rDmaRegs->rdma_mask */
+#define DMA_BACKPRESSURE_MASK				0x1FFFF
+#define DMA_PFC_ENABLE						(1 << 31)
+/* reg: rDmaRegs->rdma_map non-proc export*/
+#define DMA_MAP_MASK						0x0F
+#define DMA_MAP_SHIFT						4
+/* reg: rDmaRegs->rdma_back_status */
+#define DMA_BACKPRESSURE_STATUS_MASK		0x1FFFF
+/* reg: rDmaRegs->rdma_override */
+#define DMA_LITTLE_ENDIAN_MODE				(1 << 0)
+#define DMA_REGISTER_MODE					(1 << 1)
+/* reg: rDmaRegs->rdma_timeout non-proc export */
+#define DMA_TIMEOUT_MASK					0xFFFF
+
+#define DMA_RATE_LIMIT_EN_MASK				0xFFFF
+#define DMA_ARBITER_MODE_MASK				0x03
+#define DMA_RING_BUF_PRIORITY_MASK			0x1F
+#define DMA_RING_BUF_PRIORITY_SHIFT			5
+#define DMA_RATE_ADJ_MASK					0xFF
+
+/*-------------------Dma Descriptor defines ---------------------------------*/
+/* reg : none , non-proc export (not for registers ) */
+/* Tx/Rx Dma Descriptor common bits*/
+#define DMA_BUFLENGTH_MASK		0x0fff
+#define DMA_BUFLENGTH_SHIFT		16
+#define DMA_OWN					0x8000
+#define DMA_EOP					0x4000
+#define DMA_SOP					0x2000
+#define DMA_WRAP				0x1000
+/* Tx specific Dma descriptor bits */
+#define DMA_TX_UNDERRUN			0x0200
+#define DMA_TX_APPEND_CRC		0x0040
+#define DMA_TX_OW_CRC			0x0020
+#define DMA_TX_DO_CSUM			0x0010
+#if CONFIG_BRCM_GENET_VERSION < 3
+#define DMA_TX_QTAG_MASK		0x001F
+#else /* GENET_V3+: 6-bit QTAG */
+#define DMA_TX_QTAG_MASK		0x003F
+#endif
+#define DMA_TX_QTAG_SHIFT		7
+
+/* Rx Specific Dma descriptor bits */
+#define DMA_RX_BRDCAST			0x0040
+#define DMA_RX_MULT				0x0020
+#define DMA_RX_LG				0x0010
+#define DMA_RX_NO				0x0008
+#define DMA_RX_RXER				0x0004
+#define DMA_RX_CRC_ERROR		0x0002
+#define DMA_RX_OV				0x0001
+#define DMA_RX_FI_MASK			0x001F
+#define DMA_RX_FI_SHIFT			0x0007
+#define DMA_DESC_ALLOC_MASK		0x00FF
+
+#define DMA_ARBITER_RR			0x00
+#define DMA_ARBITER_WRR			0x01
+#define DMA_ARBITER_SP			0x02
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __UNIMAC_DEFS_H__ */
diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet_map.h b/drivers/net/ethernet/broadcom/genet/bcmgenet_map.h
new file mode 100644
index 0000000..7d700a6
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet/bcmgenet_map.h
@@ -0,0 +1,466 @@
+/*
+ * Copyright (c) 2002-2008 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *
+*/
+/* uniMAC register definations.*/
+
+#ifndef __BCMGENET_MAP_H__
+#define __BCMGENET_MAP_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bcmgenet_defs.h"
+
+#ifndef __ASSEMBLY__
+
+/* 64B status Block */
+struct status_64 {
+	unsigned long length_status;	/* length and peripheral status */
+	unsigned long ext_status;		/* Extended status*/
+	unsigned long rx_csum;			/* partial rx checksum */
+#if CONFIG_BRCM_GENET_VERSION < 3
+	unsigned long filter_index;		/* Filter index */
+	unsigned long extracted_bytes[4];	/* Extracted byte 0 - 16 */
+	unsigned long reserved[4];
+#else /* GENET_V3+ */
+	unsigned long filter_index[2];		/* Filter index */
+	unsigned long extracted_bytes[4];	/* Extracted byte 0 - 16 */
+	unsigned long reserved[3];
+#endif
+	unsigned long tx_csum_info;		/* Tx checksum info. */
+	unsigned long unused[3];		/* unused */
+} ;
+/* Rx status bits */
+#define STATUS_RX_EXT_MASK		0x1FFFFF
+#define STATUS_RX_CSUM_MASK		0xFFFF
+#define STATUS_RX_CSUM_OK		0x10000
+#define STATUS_RX_CSUM_FR		0x20000
+#define STATUS_RX_PROTO_TCP		0
+#define STATUS_RX_PROTO_UDP		1
+#define STATUS_RX_PROTO_ICMP	2
+#define STATUS_RX_PROTO_OTHER	3
+#define STATUS_RX_PROTO_MASK	3
+#define STATUS_RX_PROTO_SHIFT	18
+#define STATUS_FILTER_INDEX_MASK	0xFFFF
+/* Tx status bits */
+#define STATUS_TX_CSUM_START_MASK	0X7FFF
+#define STATUS_TX_CSUM_START_SHIFT	16
+#define STATUS_TX_CSUM_PROTO_UDP	0x8000
+#define STATUS_TX_CSUM_OFFSET_MASK	0x7FFF
+#define STATUS_TX_CSUM_LV			0x80000000
+/*
+** DMA Descriptor
+*/
+struct DmaDesc {
+	unsigned long length_status;	/* in bytes of data in buffer */
+	unsigned long address;	/* address of data */
+};
+/*
+** UniMAC TSV or RSV (Transmit Status Vector or Receive Status Vector
+*/
+/* Rx/Tx common counter group.*/
+struct PktCounterSize {
+	unsigned long cnt_64;	 /* RO Recvied/Transmited 64 bytes packet */
+	unsigned long cnt_127;	 /* RO Rx/Tx 127 bytes packet */
+	unsigned long cnt_255;	 /* RO Rx/Tx 65-255 bytes packet */
+	unsigned long cnt_511;	 /* RO Rx/Tx 256-511 bytes packet */
+	unsigned long cnt_1023;	 /* RO Rx/Tx 512-1023 bytes packet */
+	unsigned long cnt_1518;	 /* RO Rx/Tx 1024-1518 bytes packet */
+	unsigned long cnt_mgv;	 /* RO Rx/Tx 1519-1522 good VLAN packet */
+	unsigned long cnt_2047;	 /* RO Rx/Tx 1522-2047 bytes packet*/
+	unsigned long cnt_4095;	 /* RO Rx/Tx 2048-4095 bytes packet*/
+	unsigned long cnt_9216;	 /* RO Rx/Tx 4096-9216 bytes packet*/
+};
+/* RSV, Receive Status Vector */
+struct UniMacRSV {
+	struct PktCounterSize stat_sz;	/* (0x400 - 0x424), stats of received
+			packets classfied by size */
+	unsigned long rx_pkt;	 /* RO (0x428) Receive pkt count*/
+	unsigned long rx_bytes;	 /* RO Receive byte count */
+	unsigned long rx_mca;	 /* RO # of Received multicast pkt */
+	unsigned long rx_bca;	 /* RO # of Receive broadcast pkt */
+	unsigned long rx_fcs;	 /* RO # of Received FCS error  */
+	unsigned long rx_cf;	 /* RO # of Received control frame pkt*/
+	unsigned long rx_pf;	 /* RO # of Received pause frame pkt */
+	unsigned long rx_uo;	 /* RO # of unknown op code pkt */
+	unsigned long rx_aln;	 /* RO # of alignment error count */
+	unsigned long rx_flr;	 /* RO # of frame length out of range count */
+	unsigned long rx_cde;	 /* RO # of code error pkt */
+	unsigned long rx_fcr;	 /* RO # of carrier sense error pkt */
+	unsigned long rx_ovr;	 /* RO # of oversize pkt*/
+	unsigned long rx_jbr;	 /* RO # of jabber count */
+	unsigned long rx_mtue;	 /* RO # of MTU error pkt*/
+	unsigned long rx_pok;	 /* RO # of Received good pkt */
+	unsigned long rx_uc;	 /* RO # of unicast pkt */
+	unsigned long rx_ppp;	 /* RO # of PPP pkt */
+	unsigned long rcrc;		 /* RO (0x470),# of CRC match pkt */
+};
+
+/* TSV, Transmit Status Vector */
+struct UniMacTSV {
+	struct PktCounterSize stat_sz;	/* (0x480 - 0x0x4a4), statistics of
+			xmited packets classified by size */
+	unsigned long tx_pkt;	/* RO (0x4a8) Transmited pkt */
+	unsigned long tx_mca;	/* RO # of xmited multicast pkt */
+	unsigned long tx_bca;	/* RO # of xmited broadcast pkt */
+	unsigned long tx_pf;	/* RO # of xmited pause frame count */
+	unsigned long tx_cf;	/* RO # of xmited control frame count */
+	unsigned long tx_fcs;	/* RO # of xmited FCS error count */
+	unsigned long tx_ovr;	/* RO # of xmited oversize pkt */
+	unsigned long tx_drf;	/* RO # of xmited deferral pkt */
+	unsigned long tx_edf;	/* RO # of xmited Excessive deferral pkt*/
+	unsigned long tx_scl;	/* RO # of xmited single collision pkt */
+	unsigned long tx_mcl;	/* RO # of xmited multiple collision pkt*/
+	unsigned long tx_lcl;	/* RO # of xmited late collision pkt */
+	unsigned long tx_ecl;	/* RO # of xmited excessive collision pkt*/
+	unsigned long tx_frg;	/* RO # of xmited fragments pkt*/
+	unsigned long tx_ncl;	/* RO # of xmited total collision count */
+	unsigned long tx_jbr;	/* RO # of xmited jabber count*/
+	unsigned long tx_bytes;	/* RO # of xmited byte count */
+	unsigned long tx_pok;	/* RO # of xmited good pkt */
+	unsigned long tx_uc;	/* RO (0x0x4f0)# of xmited unitcast pkt */
+};
+
+struct uniMacRegs {
+	unsigned long unused;	/* (00) UMAC register start from offset 0x04 */
+	unsigned long hdBkpCtrl;	/* (04) RW */
+	unsigned long cmd;		/* (08) RW */
+	unsigned long mac_0;	/* (0x0c) RW */
+	unsigned long mac_1;	/* (0x10) RW */
+	unsigned long max_frame_len;	/* (0x14) RW */
+	unsigned long pause_quant;	/* (0x18) RW */
+	unsigned long unused0[9];
+	unsigned long sdf_offset;	/* (0x40) RW */
+	unsigned long mode;			/* (0x44) RO */
+	unsigned long frm_tag0;		/* (0x48) RW */
+	unsigned long frm_tag1;		/* (0x4c) RW */
+	unsigned long unused10[3];
+	unsigned long tx_ipg_len;	/* (0x5c) RW */
+	unsigned long unused1[172];
+	unsigned long macsec_tx_crc;	/* (0x310) RW */
+	unsigned long macsec_ctrl;	/* (0x314) RW */
+	unsigned long ts_status;	/* (0x318) RO */
+	unsigned long ts_data;		/* (0x31c) RO */
+	unsigned long unused2[4];
+	unsigned long pause_ctrl;	/* (0x330) RW */
+	unsigned long tx_flush;		/* (0x334) RW */
+	unsigned long rxfifo_status;	/* (0x338) RO */
+	unsigned long txfifo_status;	/* (0x33c) RO */
+	unsigned long ppp_ctrl;			/* (0x340) RW */
+	unsigned long ppp_refresh_ctrl;	/* (0x344) RW */
+	unsigned long unused11[4];		/* (0x348 - 0x354)*/
+	unsigned long unused12[4];		/* (0x358 - 0x364) */
+	unsigned long unused13[38];
+	struct UniMacRSV rsv;			/* (0x400 - 0x470) */
+	unsigned long unused3[3];
+	struct UniMacTSV tsv;			/* (0x480 - 0x4f0) */
+	unsigned long unused4[7];		/* Ignore RUNT sutff for now! */
+	unsigned long unused5[28];
+	unsigned long mib_ctrl;			/* (0x580) RW */
+	unsigned long unused6[31];
+	unsigned long bkpu_ctrl;		/* (0x600) RW */
+	unsigned long mac_rxerr_mask;	/* (0x604) RW  */
+	unsigned long max_pkt_size;		/* (0x608) RW */
+	unsigned long unused7[2];
+	unsigned long mdio_cmd;			/* (0x614  RO */
+	unsigned long mdio_cfg;			/* (0x618) RW */
+#if CONFIG_BRCM_GENET_VERSION > 1
+	unsigned long unused9;
+#else
+	unsigned long rbuf_ovfl_pkt_cnt;	/* (0x61c) RO */
+#endif
+	unsigned long mpd_ctrl;		/* (0x620) RW */
+	unsigned long mpd_pw_ms;	/* (0x624) RW */
+	unsigned long mpd_pw_ls;	/* (0x628) RW */
+	unsigned long unused8[9];
+	unsigned long mdf_ctrl;		/* (0x650) RW */
+	unsigned long mdf_addr[34];	/* (0x654 - 0x6d8) */
+
+};
+
+#define UMAC_MIB_START		0x400
+#define UMAC_RBUF_OVFL_CNT	0x61C
+#define UMAC_RBUF_ERR_CNT	0x634
+#define UMAC_MDF_ERR_CNT	0x638
+
+struct bcmgenet_mib_counters {
+	struct UniMacRSV rx;
+	struct UniMacTSV tx;
+	u32	rx_runt_cnt;
+	u32	rx_runt_fcs;
+	u32	rx_runt_fcs_align;
+	u32	rx_runt_bytes;
+	u32	rbuf_ovflow_cnt;
+	u32	rbuf_err_cnt;
+	u32	mdf_err_cnt;
+};
+
+#if CONFIG_BRCM_GENET_VERSION < 3
+#define HFB_NUM_FLTRS		16
+#else
+#define HFB_NUM_FLTRS		48
+#endif
+
+#if CONFIG_BRCM_GENET_VERSION > 1
+struct tbufRegs {
+	unsigned long tbuf_ctrl;	/* (00) tx buffer control */
+	unsigned long unused0;
+	unsigned long tbuf_endian_ctrl;		/* (08) */
+	unsigned long tbuf_bp_mc;			/* (0c) */
+	unsigned long tbuf_pkt_rdy_thld;	/* (10) */
+	unsigned long tbuf_energy_ctrl;		/* (14) */
+	unsigned long tbuf_ext_bp_stats;	/* (18) */
+	unsigned long tbuf_tsv_mask0;
+	unsigned long tbuf_tsv_mask1;
+	unsigned long tbuf_tsv_status0;
+	unsigned long tbuf_tsv_status1;
+};
+
+struct rbufRegs {
+	unsigned long rbuf_ctrl;			/* (00)*/
+	unsigned long unused0;
+	unsigned long rbuf_pkt_rdy_thld;	/* (08)*/
+	unsigned long rbuf_status;			/* (0c)*/
+	unsigned long rbuf_endian_ctrl;		/* (10)*/
+	unsigned long rbuf_chk_ctrl;		/* (14)*/
+#if CONFIG_BRCM_GENET_VERSION == 2
+	unsigned long rbuf_rxc_offset[8];	/* (18 - 34) */
+	unsigned long unused1[18];
+	unsigned long rbuf_ovfl_pkt_cnt;	/* (80) */
+	unsigned long rbuf_err_cnt;		/* (84) */
+	unsigned long rbuf_energy_ctrl;		/* (88) */
+
+	unsigned long unused2[7];
+	unsigned long rbuf_pd_sram_ctrl;	/* (a8) */
+	unsigned long unused3[12];
+	unsigned long rbuf_test_mux_ctrl;	/* (dc) */
+#else /* GENET_V3+ */
+	unsigned long unused1[7];		/* (18 - 34) */
+	unsigned long rbuf_rxc_offset[24];	/* (34 - 90) */
+	unsigned long rbuf_ovfl_pkt_cnt;	/* (94) */
+	unsigned long rbuf_err_cnt;		/* (98) */
+	unsigned long rbuf_energy_ctrl;		/* (9c) */
+	unsigned long rbuf_pd_sram_ctrl;	/* (a0) */
+	unsigned long rbuf_test_mux_ctrl;	/* (a4) */
+	unsigned long rbuf_spare_reg0;		/* (a8) */
+	unsigned long rbuf_spare_reg1;		/* (ac) */
+	unsigned long rbuf_spare_reg2;		/* (b0) */
+	unsigned long rbuf_tbuf_size_ctrl;	/* (b4) */
+#endif
+};
+
+struct hfbRegs {
+	unsigned long hfb_ctrl;
+#if CONFIG_BRCM_GENET_VERSION > 2
+	unsigned long hfb_flt_enable[2];
+	unsigned long unused[4];
+#endif
+	unsigned long hfb_fltr_len[HFB_NUM_FLTRS / 4];
+};
+
+#else /* CONFIG_BRCM_GENET_VERSION > 1 */
+struct rbufRegs {
+	unsigned long rbuf_ctrl;			/* (00) */
+	unsigned long rbuf_flush_ctrl;		/* (04) */
+	unsigned long rbuf_pkt_rdy_thld;	/* (08) */
+	unsigned long rbuf_status;			/* (0c) */
+	unsigned long rbuf_endian_ctrl;		/* (10) */
+	unsigned long rbuf_chk_ctrl;		/* (14) */
+	unsigned long rbuf_rxc_offset[8];	/* (18 - 34) */
+	unsigned long rbuf_hfb_ctrl;		/* (38) */
+	unsigned long rbuf_fltr_len[HFB_NUM_FLTRS / 4];	/* (3c - 48) */
+	unsigned long unused0[13];
+	unsigned long tbuf_ctrl;			/* (80) */
+	unsigned long tbuf_flush_ctrl;		/* (84) */
+	unsigned long unused1[5];
+	unsigned long tbuf_endian_ctrl;		/* (9c) */
+	unsigned long tbuf_bp_mc;			/* (a0) */
+	unsigned long tbuf_pkt_rdy_thld;	/* (a4) */
+	unsigned long unused2[2];
+	unsigned long rgmii_oob_ctrl;		/* (b0) */
+	unsigned long rgmii_ib_status;		/* (b4) */
+	unsigned long rgmii_led_ctrl;		/* (b8) */
+	unsigned long unused3;
+	unsigned long moca_status;			/* (c0) */
+	unsigned long unused4[6];
+	unsigned long test_mux_ctrl;		/* (dc) */
+};
+#endif
+/* uniMac intrl2 registers */
+struct intrl2Regs {
+	unsigned long cpu_stat;	/*(00) CPU interrupt status */
+	unsigned long cpu_set;	/*(04) set the corresponding irq*/
+	unsigned long cpu_clear;	/*(08) clear the corresponding irq*/
+	unsigned long cpu_mask_status;	/*(0c) Show current masking of irq*/
+	unsigned long cpu_mask_set;	/*(10) Disable corresponding irq*/
+	unsigned long cpu_mask_clear;	/*(14) Enable corresponding irq*/
+	unsigned long pci_stat;		/*(00) PCI interrupt status */
+	unsigned long pci_set;		/*(04) set the corresponding irq*/
+	unsigned long pci_clear;	/*(08) clear the corresponding irq*/
+	unsigned long pci_mask_status;	/*(0c) Show current masking of irq*/
+	unsigned long pci_mask_set;	/*(10) Disable corresponding irq*/
+	unsigned long pci_mask_clear;	/*(14) Enable corresponding irq*/
+};
+
+/* Register block offset */
+#define GENET_GR_BRIDGE_OFF			0x0040
+#define GENET_EXT_OFF				0x0080
+#define GENET_INTRL2_0_OFF			0x0200
+#define GENET_INTRL2_1_OFF			0x0240
+#define GENET_RBUF_OFF				0X0300
+#define GENET_UMAC_OFF				0x0800
+
+#if CONFIG_BRCM_GENET_VERSION == 1
+#define GENET_HFB_OFF				0x1000
+#define GENET_RDMA_OFF				0x2000
+#define GENET_TDMA_OFF				0x3000
+#elif CONFIG_BRCM_GENET_VERSION == 2
+#define GENET_TBUF_OFF				0x0600
+#define GENET_HFB_OFF				0x1000
+#define GENET_HFB_REG_OFF			0x2000
+#define GENET_RDMA_OFF				0x3000
+#define GENET_TDMA_OFF				0x4000
+#else /* GENET_V3+ */
+#define GENET_TBUF_OFF				0x0600
+#define GENET_HFB_OFF				0x8000
+#define GENET_HFB_REG_OFF			0xfc00
+#define GENET_RDMA_OFF				0x10000
+#define GENET_TDMA_OFF				0x11000
+#endif
+
+struct SysRegs {
+	unsigned long sys_rev_ctrl;
+	unsigned long sys_port_ctrl;
+#if CONFIG_BRCM_GENET_VERSION > 1
+	unsigned long rbuf_flush_ctrl;
+	unsigned long tbuf_flush_ctrl;
+#endif
+};
+
+struct GrBridgeRegs {
+	unsigned long gr_bridge_rev;
+	unsigned long gr_bridge_ctrl;
+	unsigned long gr_bridge_sw_reset_0;
+	unsigned long gr_bridge_sw_reset_1;
+};
+
+struct ExtRegs {
+	unsigned long ext_pwr_mgmt;
+	unsigned long ext_emcg_ctrl;
+	unsigned long ext_test_ctrl;
+#if CONFIG_BRCM_GENET_VERSION > 1
+	unsigned long rgmii_oob_ctrl;
+	unsigned long rgmii_ib_status;
+	unsigned long rgmii_led_ctrl;
+	unsigned long ext_genet_pwr_mgmt;
+#else
+	unsigned long ext_in_ctrl;
+	unsigned long ext_fblp_ctrl;
+	unsigned long ext_stat0;
+	unsigned long ext_stat1;
+	unsigned long ext_ch_ctrl[6];
+#endif
+};
+
+struct rDmaRingRegs {
+	unsigned long rdma_write_pointer;
+	unsigned long rdma_producer_index;
+	unsigned long rdma_consumer_index;
+	unsigned long rdma_ring_buf_size;
+	unsigned long rdma_start_addr;
+	unsigned long rdma_end_addr;
+	unsigned long rdma_mbuf_done_threshold;
+	unsigned long rdma_xon_xoff_threshold;
+	unsigned long rdma_read_pointer;
+	unsigned long unused[7];
+};
+
+struct tDmaRingRegs {
+	unsigned long tdma_read_pointer;
+	unsigned long tdma_consumer_index;
+	unsigned long tdma_producer_index;
+	unsigned long tdma_ring_buf_size;
+	unsigned long tdma_start_addr;
+	unsigned long tdma_end_addr;
+	unsigned long tdma_mbuf_done_threshold;
+	unsigned long tdma_flow_period;
+	unsigned long tdma_write_pointer;
+	unsigned long unused[7];
+};
+
+struct rDmaRegs {
+	struct rDmaRingRegs rDmaRings[17];
+#if CONFIG_BRCM_GENET_VERSION > 1
+	unsigned long rdma_ring_cfg;
+#endif
+	unsigned long rdma_ctrl;
+	unsigned long rdma_status;
+#if CONFIG_BRCM_GENET_VERSION < 2
+	unsigned long unused;
+#endif
+	unsigned long rdma_scb_burst_size;
+	unsigned long rdma_activity;
+	unsigned long rdma_mask;
+	unsigned long rdma_map[3];
+	unsigned long rdma_back_status;
+	unsigned long rdma_override;
+	unsigned long rdma_timeout[17];
+#if CONFIG_BRCM_GENET_VERSION > 2
+	unsigned long rdma_index2ring[8];
+#endif
+	unsigned long rdma_test;
+	unsigned long rdma_debug;
+};
+
+struct tDmaRegs {
+	struct tDmaRingRegs tDmaRings[17];
+#if CONFIG_BRCM_GENET_VERSION > 1
+	unsigned long tdma_ring_cfg;
+#endif
+	unsigned long tdma_ctrl;
+	unsigned long tdma_status;
+#if CONFIG_BRCM_GENET_VERSION == 1
+	unsigned long unused;
+#endif
+	unsigned long tdma_scb_burst_size;
+	unsigned long tdma_activity;
+	unsigned long tdma_mask;
+#if CONFIG_BRCM_GENET_VERSION > 2
+	unsigned long tdma_map[2];
+#else
+	unsigned long tdma_map[3];
+#endif
+	unsigned long tdma_back_status;
+	unsigned long tdma_override;
+	unsigned long tdma_rate_limit_ctrl;
+	unsigned long tdma_arb_ctrl;
+	unsigned long tdma_priority[3];
+	unsigned long tdma_test;
+	unsigned long tdma_debug;
+	unsigned long tdma_rate_adj;
+};
+
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/drivers/net/ethernet/broadcom/genet/bcmmii.c b/drivers/net/ethernet/broadcom/genet/bcmmii.c
new file mode 100644
index 0000000..c46c7c0
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet/bcmmii.c
@@ -0,0 +1,351 @@
+/*
+ *
+ * Copyright (c) 2002-2005 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *
+ *File Name  : bcmmii.c
+ *
+ *Description: Broadcom PHY/GPHY/Ethernet Switch Configuration
+ *Revision:	09/25/2008, L.Sun created.
+*/
+
+#include "bcmgenet.h"
+#include "bcmgenet_map.h"
+#include "bcmmii.h"
+
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/wait.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/bitops.h>
+#include <linux/netdevice.h>
+#include <linux/platform_device.h>
+#include <linux/brcmstb/brcmstb.h>
+
+/* read a value from the MII */
+int bcmgenet_mii_read(struct net_device *dev, int phy_id, int location)
+{
+	int ret;
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	volatile struct uniMacRegs *umac = pDevCtrl->umac;
+
+	if (phy_id == BRCM_PHY_ID_NONE) {
+		switch (location) {
+		case MII_BMCR:
+			return (pDevCtrl->phySpeed == SPEED_1000) ?
+				BMCR_FULLDPLX | BMCR_SPEED1000 :
+				BMCR_FULLDPLX | BMCR_SPEED100;
+		case MII_BMSR:
+			return BMSR_LSTATUS;
+		default:
+			return 0;
+		}
+	}
+
+	mutex_lock(&pDevCtrl->mdio_mutex);
+
+	umac->mdio_cmd = (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) |
+			(location << MDIO_REG_SHIFT));
+	/* Start MDIO transaction*/
+	umac->mdio_cmd |= MDIO_START_BUSY;
+	wait_event_timeout(pDevCtrl->wq, !(umac->mdio_cmd & MDIO_START_BUSY),
+			HZ/100);
+	ret = umac->mdio_cmd;
+	mutex_unlock(&pDevCtrl->mdio_mutex);
+	if (!pDevCtrl->sw_type && (ret & MDIO_READ_FAIL)) {
+		TRACE(("MDIO read failure\n"));
+		ret = 0;
+	}
+	return ret & 0xffff;
+}
+
+/* write a value to the MII */
+void bcmgenet_mii_write(struct net_device *dev, int phy_id,
+			int location, int val)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	volatile struct uniMacRegs *umac = pDevCtrl->umac;
+
+	if (phy_id == BRCM_PHY_ID_NONE)
+		return;
+	mutex_lock(&pDevCtrl->mdio_mutex);
+	umac->mdio_cmd = (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
+			(location << MDIO_REG_SHIFT) | (0xffff & val));
+	umac->mdio_cmd |= MDIO_START_BUSY;
+	wait_event_timeout(pDevCtrl->wq, !(umac->mdio_cmd & MDIO_START_BUSY),
+			HZ/100);
+	mutex_unlock(&pDevCtrl->mdio_mutex);
+}
+
+/* mii register read/modify/write helper function */
+static int bcmgenet_mii_set_clr_bits(struct net_device *dev, int location,
+		     int set_mask, int clr_mask)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	int phy_id = pDevCtrl->phyAddr;
+	int v;
+
+	v = bcmgenet_mii_read(dev, phy_id, location);
+	v &= ~clr_mask;
+	v |= set_mask;
+	bcmgenet_mii_write(dev, phy_id, location, v);
+	return v;
+}
+
+/* probe for an external PHY via MDIO; return PHY address */
+int bcmgenet_mii_probe(struct net_device *dev, void *p)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	int i;
+	struct bcmemac_platform_data *cfg = p;
+
+	if (cfg->phy_type != BRCM_PHY_TYPE_EXT_MII &&
+	    cfg->phy_type != BRCM_PHY_TYPE_EXT_RVMII) {
+		/*
+		 * Enable RGMII to interface external PHY, disable
+		 * internal 10/100 MII.
+		 */
+		GENET_RGMII_OOB_CTRL(pDevCtrl) |= RGMII_MODE_EN;
+	}
+	/* Power down EPHY */
+	if (pDevCtrl->ext)
+		pDevCtrl->ext->ext_pwr_mgmt |= (EXT_PWR_DOWN_PHY |
+			EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
+
+	for (i = 31; i >= 0; i--) {
+		if (bcmgenet_mii_read(dev, i, MII_BMSR) != 0) {
+			pDevCtrl->phyAddr = i;
+			return 0;
+		}
+		TRACE(("I=%d\n", i));
+	}
+	return -ENODEV;
+}
+
+/*
+ * setup netdev link state when PHY link status change and
+ * update UMAC and RGMII block when link up
+ */
+void bcmgenet_mii_setup(struct net_device *dev, unsigned int force)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	struct ethtool_cmd ecmd;
+	volatile struct uniMacRegs *umac = pDevCtrl->umac;
+	int cur_link, prev_link;
+	unsigned int val, cmd_bits;
+
+	if (pDevCtrl->phyType == BRCM_PHY_TYPE_MOCA)
+		return;
+
+	cur_link = mii_link_ok(&pDevCtrl->mii);
+	prev_link = netif_carrier_ok(pDevCtrl->dev);
+	if ((cur_link && !prev_link) || (cur_link && force)) {
+		mii_ethtool_gset(&pDevCtrl->mii, &ecmd);
+		/*
+		 * program UMAC and RGMII block based on established link
+		 * speed, pause, and duplex.
+		 * the speed set in umac->cmd tell RGMII block which clock
+		 * 25MHz(100Mbps)/125MHz(1Gbps) to use for transmit.
+		 * receive clock is provided by PHY.
+		 */
+		GENET_RGMII_OOB_CTRL(pDevCtrl) &= ~OOB_DISABLE;
+		GENET_RGMII_OOB_CTRL(pDevCtrl) |= RGMII_LINK;
+
+		/* speed */
+		if (ecmd.speed == SPEED_1000)
+			cmd_bits = UMAC_SPEED_1000;
+		else if (ecmd.speed == SPEED_100)
+			cmd_bits = UMAC_SPEED_100;
+		else
+			cmd_bits = UMAC_SPEED_10;
+		cmd_bits <<= CMD_SPEED_SHIFT;
+
+		/* duplex */
+		if (ecmd.duplex != DUPLEX_FULL)
+			cmd_bits |= CMD_HD_EN;
+
+		/* pause capability */
+		if (pDevCtrl->phyType == BRCM_PHY_TYPE_INT ||
+		    pDevCtrl->phyType == BRCM_PHY_TYPE_EXT_MII ||
+		    pDevCtrl->phyType == BRCM_PHY_TYPE_EXT_RVMII) {
+			val = bcmgenet_mii_read(
+				dev, pDevCtrl->phyAddr, MII_LPA);
+			if (!(val & LPA_PAUSE_CAP)) {
+				cmd_bits |= CMD_RX_PAUSE_IGNORE;
+				cmd_bits |= CMD_TX_PAUSE_IGNORE;
+			}
+		} else if (pDevCtrl->extPhy) { /* RGMII only */
+			val = bcmgenet_mii_read(dev,
+				pDevCtrl->phyAddr, MII_BRCM_AUX_STAT_SUM);
+			if (!(val & MII_BRCM_AUX_GPHY_RX_PAUSE))
+				cmd_bits |= CMD_RX_PAUSE_IGNORE;
+			if (!(val & MII_BRCM_AUX_GPHY_TX_PAUSE))
+				cmd_bits |= CMD_TX_PAUSE_IGNORE;
+		}
+
+		umac->cmd &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
+			       CMD_HD_EN |
+			       CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
+		umac->cmd |= cmd_bits;
+
+		if (bcmgenet_mii_read(dev, pDevCtrl->phyAddr, MII_STAT1000) & 0xff) {
+			bcmgenet_mii_set_clr_bits(dev, MII_BMCR, BMCR_ANRESTART, BMCR_ANRESTART);
+			return;
+		}
+
+		netif_carrier_on(pDevCtrl->dev);
+		netdev_info(dev, "link up, %d Mbps, %s duplex\n", ecmd.speed,
+			ecmd.duplex == DUPLEX_FULL ? "full" : "half");
+	} else if (!cur_link && prev_link) {
+		netif_carrier_off(pDevCtrl->dev);
+		netdev_info(dev, "link down\n");
+	}
+}
+
+void bcmgenet_ephy_workaround(struct net_device *dev)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	int phy_id = pDevCtrl->phyAddr;
+
+	/* set shadow mode 2 */
+	bcmgenet_mii_set_clr_bits(dev, 0x1f, 0x0004, 0x0004);
+
+	/*
+	 * Workaround for SWLINUX-2281: explicitly reset IDDQ_CLKBIAS
+	 * in the Shadow 2 regset, due to power sequencing issues.
+	 */
+	/* set iddq_clkbias */
+	bcmgenet_mii_write(dev, phy_id, 0x14, 0x0F00);
+	udelay(10);
+	/* reset iddq_clkbias */
+	bcmgenet_mii_write(dev, phy_id, 0x14, 0x0C00);
+
+	/*
+	 * Workaround for SWLINUX-2056: fix timing issue between the ephy
+	 * digital and the ephy analog blocks.  This clock inversion will
+	 * inherently fix any setup and hold issue.
+	 */
+	bcmgenet_mii_write(dev, phy_id, 0x13, 0x7555);
+
+	/* HW7362-51: A EEE coupling issue has been detected on the 40nm EPHYs
+	 * during a DUT LPI request. The issue occurs when the TX powers
+	 * down/up while receiving packet data on RX. The issue appears as a
+	 * BER rate around 1e-10.
+	 */
+	bcmgenet_mii_write(dev, phy_id, 0xe, 0x0007);
+	bcmgenet_mii_write(dev, phy_id, 0xf, 0x0002);
+
+	/* reset shadow mode 2 */
+	bcmgenet_mii_set_clr_bits(dev, 0x1f, 0, 0x0004);
+
+}
+
+void bcmgenet_mii_reset(struct net_device *dev)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+
+	bcmgenet_mii_write(dev, pDevCtrl->phyAddr, MII_BMCR, BMCR_RESET);
+	udelay(1);
+	/* enable 64 clock MDIO */
+	bcmgenet_mii_write(dev, pDevCtrl->phyAddr, 0x1d, 0x1000);
+	bcmgenet_mii_read(dev, pDevCtrl->phyAddr, 0x1d);
+	bcmgenet_ephy_workaround(dev);
+}
+
+int bcmgenet_mii_init(struct net_device *dev)
+{
+	struct BcmEnet_devctrl *pDevCtrl = netdev_priv(dev);
+	volatile struct uniMacRegs *umac;
+	u32 id_mode_dis = 0;
+	char *phy_name;
+
+	umac = pDevCtrl->umac;
+	pDevCtrl->mii.phy_id = pDevCtrl->phyAddr;
+	pDevCtrl->mii.phy_id_mask = 0x1f;
+	pDevCtrl->mii.reg_num_mask = 0x1f;
+	pDevCtrl->mii.dev = dev;
+	pDevCtrl->mii.mdio_read = bcmgenet_mii_read;
+	pDevCtrl->mii.mdio_write = bcmgenet_mii_write;
+	pDevCtrl->mii.supports_gmii = 0;
+
+	switch (pDevCtrl->phyType) {
+
+	case BRCM_PHY_TYPE_INT:
+		phy_name = "internal PHY";
+		pDevCtrl->sys->sys_port_ctrl = PORT_MODE_INT_EPHY;
+		/* enable APD */
+		pDevCtrl->ext->ext_pwr_mgmt |= EXT_PWR_DN_EN_LD;
+		bcmgenet_mii_reset(dev);
+		break;
+	case BRCM_PHY_TYPE_EXT_MII:
+		phy_name = "external MII";
+		pDevCtrl->sys->sys_port_ctrl = PORT_MODE_EXT_EPHY;
+		break;
+	case BRCM_PHY_TYPE_EXT_RVMII:
+		phy_name = "external RvMII";
+		if (pDevCtrl->phySpeed == SPEED_100)
+			pDevCtrl->sys->sys_port_ctrl = PORT_MODE_EXT_RVMII_25;
+		else
+			pDevCtrl->sys->sys_port_ctrl = PORT_MODE_EXT_RVMII_50;
+		break;
+	case BRCM_PHY_TYPE_EXT_RGMII_NO_ID:
+		/*
+		 * RGMII_NO_ID: TXC transitions at the same time as TXD
+		 *              (requires PCB or receiver-side delay)
+		 * RGMII:       Add 2ns delay on TXC (90 degree shift)
+		 *
+		 * ID is implicitly disabled for 100Mbps (RG)MII operation.
+		 */
+		id_mode_dis = BIT(16);
+		/* fall through */
+	case BRCM_PHY_TYPE_EXT_RGMII:
+		phy_name = "external RGMII";
+		GENET_RGMII_OOB_CTRL(pDevCtrl) |= RGMII_MODE_EN | id_mode_dis;
+		pDevCtrl->sys->sys_port_ctrl = PORT_MODE_EXT_GPHY;
+		/*
+		 * setup mii based on configure speed and RGMII txclk is set in
+		 * umac->cmd, mii_setup() after link established.
+		 */
+		if (pDevCtrl->phySpeed == SPEED_1000) {
+			pDevCtrl->mii.supports_gmii = 1;
+		} else if (pDevCtrl->phySpeed == SPEED_100) {
+			/* disable 1000BASE-T full, half-duplex capability */
+			bcmgenet_mii_set_clr_bits(dev, MII_CTRL1000, 0,
+				(ADVERTISE_1000FULL|ADVERTISE_1000HALF));
+			/* restart autoneg */
+			bcmgenet_mii_set_clr_bits(dev, MII_BMCR, BMCR_ANRESTART,
+				BMCR_ANRESTART);
+		}
+		break;
+	case BRCM_PHY_TYPE_MOCA:
+		phy_name = "MoCA";
+		/* setup speed in umac->cmd for RGMII txclk set to 125MHz */
+		umac->cmd = umac->cmd | (UMAC_SPEED_1000 << CMD_SPEED_SHIFT);
+		pDevCtrl->mii.force_media = 1;
+		pDevCtrl->sys->sys_port_ctrl = PORT_MODE_INT_GPHY |
+			LED_ACT_SOURCE_MAC;
+		break;
+	default:
+		pr_err("unknown phy_type: %d\n", pDevCtrl->phyType);
+		return -1;
+	}
+
+	pr_info("configuring instance #%d for %s\n", pDevCtrl->pdev->id,
+		phy_name);
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/broadcom/genet/bcmmii.h b/drivers/net/ethernet/broadcom/genet/bcmmii.h
new file mode 100644
index 0000000..8eab760
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet/bcmmii.h
@@ -0,0 +1,55 @@
+/*
+ *
+ * Copyright (c) 2002-2005 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *
+*/
+#ifndef _BCMMII_H_
+#define _BCMMII_H_
+
+/* BRCM EPHY Aux status summery Register */
+#define MII_BRCM_AUX_STAT_SUM				0x19
+#define MII_BRCM_AUX_FD						0x01
+#define MII_BRCM_AUX_AN						0x10
+#define MII_BRCM_AUX_LINK_UP				0x20
+#define MII_BRCM_AUX_SPEED_100				0x40
+#define MII_BRCM_AUX_LP_AN					0x80
+#define MII_BRCM_AUX_LP_PR					0x100
+/* highest common denominator*/
+#define MII_BRCM_AUX_AN_HCD_MASK			0x03
+#define MII_BRCM_AUX_AN_HCD_SHIFT			0x08
+#define MII_BRCM_AUX_AN_HCD_10T				0X01
+#define MII_BRCM_AUX_AN_HCD_10T_FULL		0x02
+#define MII_BRCM_AUX_AN_HCD_100TX			0x03
+#define MII_BRCM_AUX_AN_HCD_100T4			0x04
+#define MII_BRCM_AUX_AN_HCD_100TX_FULL		0x05
+#define MII_BRCM_AUX_AN_PAUSE				0x800
+#define MII_BRCM_AUX_AN_COMPLETE			0x8000
+/* BRCM GPHY Aux status summery register bits ?? */
+#define MII_BRCM_AUX_GPHY_TX_PAUSE			0
+#define MII_BRCM_AUX_GPHY_RX_PAUSE			1
+/****************************************************************************
+Prototypes
+****************************************************************************/
+
+extern void bcmgenet_mii_setup(struct net_device *dev, unsigned int force);
+extern int bcmgenet_mii_init(struct net_device *dev);
+extern int bcmgenet_mii_probe(struct net_device *dev, void *p);
+extern void bcmgenet_mii_reset(struct net_device *dev);
+extern void bcmgenet_ephy_workaround(struct net_device *dev);
+extern void bcmgenet_ethsw_init(struct net_device *dev);
+
+#endif /* _BCMMII_H_ */
diff --git a/drivers/net/ethernet/broadcom/genet/ethsw.c b/drivers/net/ethernet/broadcom/genet/ethsw.c
new file mode 100644
index 0000000..d84fa21
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet/ethsw.c
@@ -0,0 +1,640 @@
+/*
+ * Copyright (c) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+/* FIXME: Please just gut this entire file and rewrite it to use phylib */
+
+#include "bcmgenet.h"
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/wait.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/bitops.h>
+#include <linux/netdevice.h>
+#include <linux/proc_fs.h>
+#include <linux/ctype.h>
+#include <linux/stddef.h>
+
+static unsigned char swdata[16];
+
+#define PSEUDO_PHY_ADDR		0x1e
+
+#define REG_PSEUDO_PHY_MII_REG16                          0x10
+    #define REG_PPM_REG16_SWITCH_PAGE_NUMBER_SHIFT        8
+    #define REG_PPM_REG16_MDIO_ENABLE                     0x01
+#define REG_PSEUDO_PHY_MII_REG17                          0x11
+
+    #define REG_PPM_REG17_REG_NUMBER_SHIFT                8
+    #define REG_PPM_REG17_OP_DONE                         0x00
+    #define REG_PPM_REG17_OP_WRITE                        0x01
+    #define REG_PPM_REG17_OP_READ                         0x02
+
+#define REG_PSEUDO_PHY_MII_REG24                          0x18
+#define REG_PSEUDO_PHY_MII_REG25                          0x19
+#define REG_PSEUDO_PHY_MII_REG26                          0x1a
+#define REG_PSEUDO_PHY_MII_REG27                          0x1b
+
+#define PAGE_CONTROL                                      0x00
+    #define REG_PORT_CTRL                                 0x00
+    #define REG_IMP_PORT_CONTROL                          0x08
+
+        #define REG_IMP_PORT_CONTROL_RX_UCST_EN           0x10
+        #define REG_IMP_PORT_CONTROL_RX_MCST_EN           0x08
+        #define REG_IMP_PORT_CONTROL_RX_BCST_EN           0x04  
+    #define REG_SWITCH_MODE                               0x0b
+
+        #define REG_SWITCH_MODE_FRAME_MANAGE_MODE         0x01
+        #define REG_SWITCH_MODE_SW_FWDG_EN                0x02
+    #define REG_CONTROL_IMP_PORT_STATE_OVERRIDE           0x0e
+
+        #define REG_CONTROL_MPSO_MII_SW_OVERRIDE          0x80
+        #define REG_CONTROL_MPSO_TX_FLOW_CONTROL          0x20
+        #define REG_CONTROL_MPSO_RX_FLOW_CONTROL          0x10
+        #define REG_CONTROL_MPSO_SPEED1000                0x08
+        #define REG_CONTROL_MPSO_SPEED100                 0x04
+        #define REG_CONTROL_MPSO_FDX                      0x02
+        #define REG_CONTROL_MPSO_LINKPASS                 0x01
+
+    #define REG_SWITCH_CTRL				  0x20
+	#define REG_MII_DUMB_FWD_EN			  0x01
+
+    #define REG_PORT_FORWARD                              0x21 /* 5397 only */
+
+        #define REG_PORT_FORWARD_MCST                     0x80
+        #define REG_PORT_FORWARD_UCST                     0x40
+        #define REG_PORT_FORWARD_IPMC                     0x01
+
+    #define REG_UCST_LOOKUP_FAIL                          0x32
+
+    #define REG_RGMII_CTRL_IMP                            0x60
+
+    #define REG_RGMII_CTRL_P5                             0x65
+
+        #define REG_RGMII_CTRL_ENABLE_GMII                0x80
+        #define REG_RGMII_CTRL_DLL_IQQD                   0x04
+        #define REG_RGMII_CTRL_DLL_RXC_BYPASS             0x02
+        #define REG_RGMII_CTRL_TIMING_SEL                 0x01
+
+#define SWITCH_PORT_MAP_IMP                               0x0100
+
+#define PAGE_MANAGEMENT                                   0x02
+
+    #define REG_GLOBAL_CONFIG                             0x00
+#define PAGE_PORT_BASED_VLAN                              0x31
+
+    #define REG_VLAN_CTRL_P0                              0x00
+    #define REG_VLAN_CTRL_P1                              0x02
+    #define REG_VLAN_CTRL_P2                              0x04
+    #define REG_VLAN_CTRL_P3                              0x06
+    #define REG_VLAN_CTRL_P4                              0x08
+    #define REG_VLAN_CTRL_P5                              0x0a
+    #define REG_VLAN_CTRL_P6                              0x0c
+    #define REG_VLAN_CTRL_P7                              0x0e
+    #define REG_VLAN_CTRL_P8                              0x10
+
+#define BE64(x) \
+({ \
+	uint64_t __x = (x); \
+	((uint64_t)( \
+		(((uint64_t)(__x) & (uint64_t)0x00000000000000ffUL) << 56) | \
+		(((uint64_t)(__x) & (uint64_t)0x000000000000ff00UL) << 40) | \
+		(((uint64_t)(__x) & (uint64_t)0x0000000000ff0000UL) << 24) | \
+		(((uint64_t)(__x) & (uint64_t)0x00000000ff000000UL) << 8) | \
+		(((uint64_t)(__x) & (uint64_t)0x000000ff00000000UL) >> 8) | \
+		(((uint64_t)(__x) & (uint64_t)0x0000ff0000000000UL) >> 24) | \
+		(((uint64_t)(__x) & (uint64_t)0x00ff000000000000UL) >> 40) | \
+		(((uint64_t)(__x) & (uint64_t)0xff00000000000000UL) >> 56) )); \
+})
+#define BE32(x) \
+({ \
+	uint32_t __x = (x); \
+	((uint32_t)( \
+		(((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
+		(((uint32_t)(__x) & (uint32_t)0x0000ff00UL) <<  8) | \
+		(((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >>  8) | \
+		(((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) )); \
+})
+#define BE16(x) \
+({ \
+	uint16_t __x = (x); \
+	((uint16_t)( \
+		(((uint16_t)(__x) & (uint16_t)0x00ffUL) << 8) | \
+		(((uint16_t)(__x) & (uint16_t)0xff00UL) >>  8) )); \
+})
+
+void ethsw_mdio_rreg(struct net_device *dev, int page, int reg, unsigned char *data, int len)
+{
+	struct BcmEnet_devctrl *priv = netdev_priv(dev);
+	int phy_id;
+	int v, vm[4];
+	int i;
+
+	phy_id = PSEUDO_PHY_ADDR;
+	v = (page << REG_PPM_REG16_SWITCH_PAGE_NUMBER_SHIFT) | REG_PPM_REG16_MDIO_ENABLE;
+	priv->mii.mdio_write(dev, phy_id, REG_PSEUDO_PHY_MII_REG16, v);
+
+	v = (reg << REG_PPM_REG17_REG_NUMBER_SHIFT) | REG_PPM_REG17_OP_READ;
+	priv->mii.mdio_write(dev, phy_id, REG_PSEUDO_PHY_MII_REG17, v);
+
+	for (i = 0; i < 5; i++)
+	{
+		v = priv->mii.mdio_read(dev, phy_id, REG_PSEUDO_PHY_MII_REG17);
+
+		if ((v & (REG_PPM_REG17_OP_WRITE | REG_PPM_REG17_OP_READ)) == REG_PPM_REG17_OP_DONE)
+			break;
+
+		udelay(10);
+	}
+
+	if (i == 5)
+	{
+		printk("ethsw_mdio_rreg: timeout!\n");
+		return;
+	}
+
+	switch (len) 
+	{
+		case 1:
+			v = priv->mii.mdio_read(dev, phy_id, REG_PSEUDO_PHY_MII_REG24);
+			data[0] = (unsigned char)v;
+			break;
+		case 2:
+			v = priv->mii.mdio_read(dev, phy_id, REG_PSEUDO_PHY_MII_REG24);
+			((unsigned short *)data)[0] = (unsigned short)v;
+			break;
+		case 4:
+			vm[0] = priv->mii.mdio_read(dev, phy_id, REG_PSEUDO_PHY_MII_REG24);
+			vm[1] = priv->mii.mdio_read(dev, phy_id, REG_PSEUDO_PHY_MII_REG25);
+			((unsigned short *)data)[0] = (unsigned short)vm[0];
+			((unsigned short *)data)[1] = (unsigned short)vm[1];
+			break;
+		case 6:
+			vm[0] = priv->mii.mdio_read(dev, phy_id, REG_PSEUDO_PHY_MII_REG26);
+			vm[1] = priv->mii.mdio_read(dev, phy_id, REG_PSEUDO_PHY_MII_REG25);
+			vm[2] = priv->mii.mdio_read(dev, phy_id, REG_PSEUDO_PHY_MII_REG24);
+			((unsigned short *)data)[0] = (unsigned short)vm[2];
+			((unsigned short *)data)[1] = (unsigned short)vm[1];
+			((unsigned short *)data)[2] = (unsigned short)vm[0];
+			break;
+		case 8:
+			vm[0] = priv->mii.mdio_read(dev, phy_id, REG_PSEUDO_PHY_MII_REG27);
+			vm[1] = priv->mii.mdio_read(dev, phy_id, REG_PSEUDO_PHY_MII_REG26);
+			vm[2] = priv->mii.mdio_read(dev, phy_id, REG_PSEUDO_PHY_MII_REG25);
+			vm[3] = priv->mii.mdio_read(dev, phy_id, REG_PSEUDO_PHY_MII_REG24);
+			((unsigned short *)data)[0] = (unsigned short)vm[3];
+			((unsigned short *)data)[1] = (unsigned short)vm[2];
+			((unsigned short *)data)[2] = (unsigned short)vm[1];
+			((unsigned short *)data)[3] = (unsigned short)vm[0];
+			break;
+	}
+	v = page << REG_PPM_REG16_SWITCH_PAGE_NUMBER_SHIFT;
+	priv->mii.mdio_write(dev, phy_id, REG_PSEUDO_PHY_MII_REG16, v);
+}
+
+void ethsw_mdio_wreg(struct net_device *dev, int page, int reg, unsigned char *data, int len)
+{
+	struct BcmEnet_devctrl *priv = netdev_priv(dev);
+	int phy_id;
+	int v;
+	int i;
+
+	phy_id = PSEUDO_PHY_ADDR;
+	v = (page << REG_PPM_REG16_SWITCH_PAGE_NUMBER_SHIFT) | REG_PPM_REG16_MDIO_ENABLE;
+	priv->mii.mdio_write(dev, phy_id, REG_PSEUDO_PHY_MII_REG16, v);
+
+	switch (len) 
+	{
+		case 1:
+			v = data[0];
+			priv->mii.mdio_write(dev, phy_id, REG_PSEUDO_PHY_MII_REG24, v);
+			break;
+		case 2:
+			v = ((unsigned short *)data)[0];
+			priv->mii.mdio_write(dev, phy_id, REG_PSEUDO_PHY_MII_REG24, v);
+			break;
+		case 4:
+			v = ((unsigned short *)data)[0];
+			priv->mii.mdio_write(dev, phy_id, REG_PSEUDO_PHY_MII_REG24, v);
+			v = ((unsigned short *)data)[1];
+			priv->mii.mdio_write(dev, phy_id, REG_PSEUDO_PHY_MII_REG25, v);
+			break;
+		case 6:
+			v = ((unsigned short *)data)[0];
+			priv->mii.mdio_write(dev, phy_id, REG_PSEUDO_PHY_MII_REG24, v);
+			v = ((unsigned short *)data)[1];
+			priv->mii.mdio_write(dev, phy_id, REG_PSEUDO_PHY_MII_REG25, v);
+			v = ((unsigned short *)data)[2];
+			priv->mii.mdio_write(dev, phy_id, REG_PSEUDO_PHY_MII_REG26, v);
+			break;
+		case 8:
+			v = ((unsigned short *)data)[0];
+			priv->mii.mdio_write(dev, phy_id, REG_PSEUDO_PHY_MII_REG24, v);
+			v = ((unsigned short *)data)[1];
+			priv->mii.mdio_write(dev, phy_id, REG_PSEUDO_PHY_MII_REG25, v);
+			v = ((unsigned short *)data)[2];
+			priv->mii.mdio_write(dev, phy_id, REG_PSEUDO_PHY_MII_REG26, v);
+			v = ((unsigned short *)data)[3];
+			priv->mii.mdio_write(dev, phy_id, REG_PSEUDO_PHY_MII_REG27, v);
+			break;
+	}
+
+	v = (reg << REG_PPM_REG17_REG_NUMBER_SHIFT) | REG_PPM_REG17_OP_WRITE;
+	priv->mii.mdio_write(dev, phy_id, REG_PSEUDO_PHY_MII_REG17, v);
+
+	for (i = 0; i < 5; i++)
+	{
+		v = priv->mii.mdio_read(dev, phy_id, REG_PSEUDO_PHY_MII_REG17);
+
+		if ((v & (REG_PPM_REG17_OP_WRITE | REG_PPM_REG17_OP_READ)) == REG_PPM_REG17_OP_DONE)
+			break;
+
+		udelay(10);
+	}
+
+	if (i == 5)
+		printk("ethsw_mdio_wreg: timeout!\n");
+
+	v = page << REG_PPM_REG16_SWITCH_PAGE_NUMBER_SHIFT;
+	priv->mii.mdio_write(dev, phy_id, REG_PSEUDO_PHY_MII_REG16, v);
+}
+
+static void ethsw_rreg(struct net_device *dev, int page, int reg, unsigned char *data, int len)
+{
+	if (((len != 1) && (len % 2) != 0) || len > 8)
+		panic("ethsw_rreg: wrong length!\n");
+
+	ethsw_mdio_rreg(dev, page, reg, data, len);
+}
+
+static void ethsw_wreg(struct net_device *dev, int page, int reg, unsigned char *data, int len)
+{
+	if (((len != 1) && (len % 2) != 0) || len > 8)
+		panic("ethsw_wreg: wrong length!\n");
+
+	ethsw_mdio_wreg(dev, page, reg, data, len);
+}
+
+int ethsw_config_learning(struct net_device *dev)
+{
+	unsigned char v8;
+	unsigned short v16;
+
+	// Forward lookup failure to CPU
+	v8 = (REG_PORT_FORWARD_MCST | REG_PORT_FORWARD_UCST | REG_PORT_FORWARD_IPMC);
+	ethsw_wreg(dev, PAGE_CONTROL, REG_PORT_FORWARD, (unsigned char *)&v8, sizeof(v8));
+	// Forward unlearned unicast frames to the MIPS
+	v16 = SWITCH_PORT_MAP_IMP;
+	ethsw_wreg(dev, PAGE_CONTROL, REG_UCST_LOOKUP_FAIL, (unsigned char *)&v16, sizeof(v16));
+
+	return 0;
+}
+
+void ethsw_switch_unmanage_mode(struct net_device *dev)
+{
+	struct BcmEnet_devctrl *priv = netdev_priv(dev);
+	unsigned char v8;
+	unsigned short v16;
+
+	ethsw_rreg(dev, PAGE_CONTROL, REG_SWITCH_MODE, &v8, sizeof(v8));
+	v8 &= ~REG_SWITCH_MODE_FRAME_MANAGE_MODE;
+	v8 |= REG_SWITCH_MODE_SW_FWDG_EN;
+	ethsw_wreg(dev, PAGE_CONTROL, REG_SWITCH_MODE, &v8, sizeof(v8));
+
+	v8 = 0;
+	ethsw_wreg(dev, PAGE_MANAGEMENT, REG_GLOBAL_CONFIG, &v8, sizeof(v8));
+
+	if (priv->sw_type == 0x53101) {
+		v8 = REG_MII_DUMB_FWD_EN;
+		ethsw_wreg(dev, PAGE_CONTROL, REG_SWITCH_CTRL, &v8, sizeof(v8));
+	}
+
+	/* Delete port-based VLAN */
+	v16 = 0x01ff;
+	ethsw_wreg(dev, PAGE_PORT_BASED_VLAN, REG_VLAN_CTRL_P0, (unsigned char *)&v16, sizeof(v16));
+	ethsw_wreg(dev, PAGE_PORT_BASED_VLAN, REG_VLAN_CTRL_P1, (unsigned char *)&v16, sizeof(v16));
+	ethsw_wreg(dev, PAGE_PORT_BASED_VLAN, REG_VLAN_CTRL_P2, (unsigned char *)&v16, sizeof(v16));
+	ethsw_wreg(dev, PAGE_PORT_BASED_VLAN, REG_VLAN_CTRL_P3, (unsigned char *)&v16, sizeof(v16)); 
+	ethsw_wreg(dev, PAGE_PORT_BASED_VLAN, REG_VLAN_CTRL_P4, (unsigned char *)&v16, sizeof(v16)); 
+	ethsw_wreg(dev, PAGE_PORT_BASED_VLAN, REG_VLAN_CTRL_P8, (unsigned char *)&v16, sizeof(v16));
+}
+
+int ethsw_reset_ports(struct net_device *dev)
+{
+	unsigned long flags;
+	int i;
+	unsigned char v8;
+
+	local_irq_save(flags);
+
+	/* MAC level reset */
+	v8 = 0; /* No spanning tree and tx/rx enable */
+	for (i = 0; i < 5; i++)
+	{
+		ethsw_wreg(dev, PAGE_CONTROL, REG_PORT_CTRL + i, &v8, 1);
+	}
+
+	/* Set IMP port RMII mode */
+	v8 = 0;
+	v8 |= REG_IMP_PORT_CONTROL_RX_UCST_EN;
+	v8 |= REG_IMP_PORT_CONTROL_RX_MCST_EN;
+	v8 |= REG_IMP_PORT_CONTROL_RX_BCST_EN;
+	ethsw_wreg(dev, PAGE_CONTROL, REG_IMP_PORT_CONTROL, &v8, 1);
+
+	v8 = 0;
+	v8 |= (REG_CONTROL_MPSO_MII_SW_OVERRIDE|REG_CONTROL_MPSO_LINKPASS);
+	v8 |= (REG_CONTROL_MPSO_RX_FLOW_CONTROL|REG_CONTROL_MPSO_SPEED100|REG_CONTROL_MPSO_FDX);
+	ethsw_wreg(dev, PAGE_CONTROL, REG_CONTROL_IMP_PORT_STATE_OVERRIDE, &v8, sizeof(v8));
+
+	/* checking Switch functional */
+	v8 = 0;
+	ethsw_rreg(dev, PAGE_CONTROL, REG_CONTROL_IMP_PORT_STATE_OVERRIDE, &v8, sizeof(v8));
+	if ((v8 & (REG_CONTROL_MPSO_MII_SW_OVERRIDE|REG_CONTROL_MPSO_LINKPASS)) !=
+		(REG_CONTROL_MPSO_MII_SW_OVERRIDE|REG_CONTROL_MPSO_LINKPASS) ||
+		(v8 == 0xff)) {
+		printk(KERN_ERR "error on Ethernet Switch setup 0x%x\n", v8);
+		local_irq_restore(flags);
+		return -1;
+	}
+	local_irq_restore(flags);
+
+	return 0;
+}
+
+
+void ethsw_print_reg(struct net_device *dev, int reg_page, int reg_addr, int reg_len, char *reg_name) 
+{
+	unsigned char swdata[8];
+	unsigned int val;
+	int i;
+
+	ethsw_rreg(dev, reg_page, reg_addr, swdata, reg_len);
+	printk("%s [%02x:%02x] = ", reg_name, reg_page, reg_addr);
+	switch(reg_len) {
+		case 2:
+			*(uint16_t *)&swdata[0] = BE16(*(uint16_t *)&swdata[0]);
+			break;
+		case 4:
+			*(uint32_t *)&swdata[0] = BE32(*(uint32_t *)&swdata[0]);
+			break;
+		case 8:
+			val = BE32(*(uint32_t *)&swdata[0]);
+			*(uint32_t *)&swdata[0] = BE32(*(uint32_t *)&swdata[4]);
+			*(uint32_t *)&swdata[4] = val;
+			break;
+	}
+	for (i = 0; i < reg_len; i ++)
+		printk("%02x ", swdata[i]);
+	printk("\n");
+}
+
+int ethsw_dump_mib(struct net_device *dev, int port) 
+{
+	int reg_page;
+
+	if (port > 8) {
+		printk("Invalid port number \n"); 
+		return -1; 
+	}
+
+	printk("\n");
+	printk("dump port %d MIB counter\n", port);
+	reg_page = 0x20 + port;
+	/* Display Tx statistics */
+	ethsw_print_reg(dev, reg_page, 0, 8, "TxOctets");
+	ethsw_print_reg(dev, reg_page, 8, 4, "TxDropPkts");
+	ethsw_print_reg(dev, reg_page, 0x10, 4, "TxBroadcastPkts");
+	ethsw_print_reg(dev, reg_page, 0x14, 4, "TxMulticastPkts");
+	ethsw_print_reg(dev, reg_page, 0x18, 4, "TxUnicastPkts");
+	ethsw_print_reg(dev, reg_page, 0x1c, 4, "TxCollisions");
+	ethsw_print_reg(dev, reg_page, 0x58, 4, "RxUndersizePkts");
+	ethsw_print_reg(dev, reg_page, 0x60, 4, "Pkt64Octets");
+	ethsw_print_reg(dev, reg_page, 0x64, 4, "Pkt65to127Octets");
+	ethsw_print_reg(dev, reg_page, 0x68, 4, "Pkt128to255Octets");
+	ethsw_print_reg(dev, reg_page, 0x6C, 4, "Pkt256to511Octets");
+	ethsw_print_reg(dev, reg_page, 0x70, 4, "Pkt512to1023Octets");
+	ethsw_print_reg(dev, reg_page, 0x74, 4, "Pkts1024toMaxPktOctets");
+	ethsw_print_reg(dev, reg_page, 0x78, 4, "RxOversizePkts");
+	ethsw_print_reg(dev, reg_page, 0x80, 4, "RxAlignmentErros");
+	ethsw_print_reg(dev, reg_page, 0x84, 4, "RXFCSErrors");
+	ethsw_print_reg(dev, reg_page, 0x88, 4, "RxGoodOctets");
+	ethsw_print_reg(dev, reg_page, 0x90, 4, "RxDropPkts");
+	ethsw_print_reg(dev, reg_page, 0x94, 4, "RxUnicastPkts");
+	ethsw_print_reg(dev, reg_page, 0x98, 4, "RxMulticastPkts");
+	ethsw_print_reg(dev, reg_page, 0x9C, 4, "RxBroadcastPkts");
+	ethsw_print_reg(dev, reg_page, 0xA8, 4, "JumboPkt");
+	ethsw_print_reg(dev, reg_page, 0xAC, 4, "RXSymbolError");
+	ethsw_print_reg(dev, reg_page, 0xB4, 4, "OutofRangeError");
+
+	return 0;
+}
+
+static void str_to_num(char* in, char* out, int len)
+{
+	int i;
+	memset(out, 0, len);
+
+	for (i = 0; i < len * 2; i ++)
+	{
+		if ((*in >= '0') && (*in <= '9'))
+			*out += (*in - '0');
+		else if ((*in >= 'a') && (*in <= 'f'))
+			*out += (*in - 'a') + 10;
+		else if ((*in >= 'A') && (*in <= 'F'))
+			*out += (*in - 'A') + 10;
+		else
+			*out += 0;
+
+		if ((i % 2) == 0)
+			*out *= 16;
+		else
+			out ++;
+
+		in ++;
+	}
+	return;
+}
+
+static int proc_get_sw_param(char *page, char **start, off_t off, int cnt, int *eof, void *data)
+{
+	int reg_page  = swdata[0];
+	int reg_addr  = swdata[1];
+	int reg_len   = swdata[2];
+	int i = 0;
+	int r = 0;
+	unsigned int val;
+
+	*eof = 1;
+
+	if (reg_len == 0)
+		return 0;
+
+#if 0
+	if (reg_page == 0xfe) {
+		if (reg_len == 6)
+			show_arl((struct net_device *)data, swdata[1], swdata + 3);
+		else
+			show_arl((struct net_device *)data, swdata[1], NULL);
+		return 0;
+	}
+#endif
+	if (reg_page == 0xff) {
+		for (i = 0; i < 8; i++) {
+			if ((0x01 << i) & reg_addr)
+				ethsw_dump_mib((struct net_device *)data, i);
+		}
+		ethsw_dump_mib((struct net_device *)data, 8);
+		return 0;
+	}
+	ethsw_rreg((struct net_device *)data, reg_page, reg_addr, swdata + 3, reg_len);
+
+	r += sprintf(page + r, "[%02x:%02x] = ", swdata[0], swdata[1]);
+	switch(reg_len) {
+		case 2:
+			*(uint16_t *)&swdata[3] = BE16(*(uint16_t *)&swdata[3]);
+			break;
+		case 4:
+			*(uint32_t *)&swdata[3] = BE32(*(uint32_t *)&swdata[3]);
+			break;
+		case 6:
+			val = BE32(*(uint32_t *)&swdata[5]);
+			*(uint16_t *)&swdata[7] = BE16(*(uint32_t *)&swdata[3]);
+			*(uint32_t *)&swdata[3] = val;
+			break;
+		case 8:
+			val = BE32(*(uint32_t *)&swdata[3]);
+			*(uint32_t *)&swdata[3] = BE32(*(uint32_t *)&swdata[7]);
+			*(uint32_t *)&swdata[7] = val;
+			break;
+	}
+
+	for (i = 0; i < reg_len; i ++)
+		r += sprintf(page + r, "%02x ", swdata[3 + i]);
+
+	r += sprintf(page + r, "\n");
+	return (r < cnt)? r: 0;
+}
+
+static int proc_set_sw_param(struct file *f, const char *buf, unsigned long cnt, void *data)
+{
+	char input[32];
+	int i;
+	int r;
+	int num_of_octets;
+
+	int reg_page;
+	int reg_addr;
+	int reg_len;
+	unsigned int val;
+
+	if (cnt > 32)
+		cnt = 32;
+
+	if (copy_from_user(input, buf, cnt) != 0)
+		return -EFAULT;
+
+	r = cnt;
+
+	for (i = 0; i < r; i ++)
+	{
+		if (!isxdigit(input[i]))
+		{
+			memmove(&input[i], &input[i + 1], r - i - 1);
+			r --;
+			i --;
+		}
+	}
+
+	num_of_octets = r / 2;
+
+	if (num_of_octets < 3) // page, addr, len
+		return -EFAULT;
+
+	str_to_num(input, swdata, num_of_octets);
+
+	reg_page  = swdata[0];
+	reg_addr  = swdata[1];
+	reg_len   = swdata[2];
+
+	if (((reg_len != 1) && (reg_len % 2) != 0) || reg_len > 8)
+	{
+		memset(swdata, 0, sizeof(swdata));
+		return -EFAULT;
+	}
+
+	if ((num_of_octets > 3) && (num_of_octets != reg_len + 3))
+	{
+		memset(swdata, 0, sizeof(swdata));
+		return -EFAULT;
+	}
+
+	if ((num_of_octets > 3) && (reg_page < 0xfe)) {
+		switch(reg_len) {
+			case 2:
+				*(uint16_t *)&swdata[3] = BE16(*(uint16_t *)&swdata[3]);
+				break;
+			case 4:
+				*(uint32_t *)&swdata[3] = BE32(*(uint32_t *)&swdata[3]);
+				break;
+			case 6:
+				val = BE32(*(uint32_t *)&swdata[5]);
+				*(uint16_t *)&swdata[7] = BE16(*(uint32_t *)&swdata[3]);
+				*(uint32_t *)&swdata[3] = val;
+				break;
+			case 8:
+				val = BE32(*(uint32_t *)&swdata[3]);
+				*(uint32_t *)&swdata[3] = BE32(*(uint32_t *)&swdata[7]);
+				*(uint32_t *)&swdata[7] = val;
+				break;
+		}
+		ethsw_wreg((struct net_device *)data, reg_page, reg_addr, swdata + 3, reg_len);
+	}
+	return cnt;
+}
+
+
+int ethsw_add_proc_files(struct net_device *dev)
+{
+	struct proc_dir_entry *p;
+
+	p = create_proc_entry("switch", 0644, NULL);
+
+	if (p == NULL)
+		return -1;
+
+	memset(swdata, 0, sizeof(swdata));
+
+	p->data        = dev;
+	p->read_proc   = proc_get_sw_param;
+	p->write_proc  = proc_set_sw_param;
+
+	return 0;
+}
+
+int ethsw_del_proc_files(void)
+{
+	remove_proc_entry("switch", NULL);
+
+	return 0;
+}
+
+void bcmgenet_ethsw_init(struct net_device *dev)
+{
+	ethsw_add_proc_files(dev);
+	ethsw_reset_ports(dev);
+	ethsw_switch_unmanage_mode(dev);
+	ethsw_config_learning(dev);
+}
diff --git a/drivers/net/ethernet/broadcom/genet/if_net.h b/drivers/net/ethernet/broadcom/genet/if_net.h
new file mode 100644
index 0000000..e07b9f4
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet/if_net.h
@@ -0,0 +1,72 @@
+/*
+ *
+ * Copyright (c) 2002-2005 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *
+ *if_net.h
+ * Purpose: network ioctl function data definations.
+*/
+#ifndef _IF_NET_H_
+#define _IF_NET_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+ * Ioctl definitions.
+ */
+/* go into ACPI WoL mode*/
+#define SIOCSACPISET		(SIOCDEVPRIVATE + 2)
+/* cancel ACPI WoL Mode */
+#define SIOCSACPICANCEL		(SIOCDEVPRIVATE + 3)
+/* get ACPI pattern */
+#define SIOCGPATTERN		(SIOCDEVPRIVATE + 4)
+/* set ACPI pattern */
+#define SIOCSPATTERN		(SIOCDEVPRIVATE + 5)
+
+/*
+ * ACPI pattern (or generic HFB ) data
+ */
+union acpi_pattern {
+	unsigned long value;
+	struct {
+#ifdef __BIG_ENDIAN
+		unsigned long unused:12;
+		unsigned long mask:4;
+		unsigned long data:16;
+#else
+		unsigned long data:16;
+		unsigned long mask:4;
+		unsigned long unused:12;
+#endif
+	} pattern;
+};
+
+/* used by ioctl call */
+struct acpi_data {
+	/* current filter index */
+	int fltr_index;
+	/* pointer to the pattern data.*/
+	union acpi_pattern *p_data;
+	/* total count of the data */
+	int count;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _IF_NET_H_ */
diff --git a/drivers/net/ethernet/pmc-sierra/Kconfig b/drivers/net/ethernet/pmc-sierra/Kconfig
new file mode 100644
index 0000000..6ca395c
--- /dev/null
+++ b/drivers/net/ethernet/pmc-sierra/Kconfig
@@ -0,0 +1,16 @@
+config NET_VENDOR_PMC_SIERRA
+        bool "PMC-Sierra devices"
+        default y
+        depends on PMC_YOSEMITE
+
+if NET_VENDOR_PMC_SIERRA
+
+config TITAN_GE
+	bool "PMC-Sierra TITAN Gigabit Ethernet Support"
+	depends on PMC_YOSEMITE
+        default y
+	help
+	  This enables support for the the integrated ethernet of
+	  PMC-Sierra's Titan SoC.
+
+endif # NET_VENDOR_PMC_SIERRA
diff --git a/drivers/net/ethernet/pmc-sierra/Makefile b/drivers/net/ethernet/pmc-sierra/Makefile
new file mode 100644
index 0000000..4a658ac
--- /dev/null
+++ b/drivers/net/ethernet/pmc-sierra/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_TITAN_GE) += titan_mdio.o titan_ge.o
diff --git a/drivers/net/ethernet/pmc-sierra/titan_ge.c b/drivers/net/ethernet/pmc-sierra/titan_ge.c
new file mode 100644
index 0000000..dc137bf8
--- /dev/null
+++ b/drivers/net/ethernet/pmc-sierra/titan_ge.c
@@ -0,0 +1,2069 @@
+/*
+ * drivers/net/titan_ge.c - Driver for Titan ethernet ports
+ *
+ * Copyright (C) 2003 PMC-Sierra Inc.
+ * Author : Manish Lachwani (lachwani@pmc-sierra.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+/*
+ * The MAC unit of the Titan consists of the following:
+ *
+ * -> XDMA Engine to move data to from the memory to the MAC packet FIFO
+ * -> FIFO is where the incoming and outgoing data is placed
+ * -> TRTG is the unit that pulls the data from the FIFO for Tx and pushes
+ *    the data into the FIFO for Rx
+ * -> TMAC is the outgoing MAC interface and RMAC is the incoming.
+ * -> AFX is the address filtering block
+ * -> GMII block to communicate with the PHY
+ *
+ * Rx will look like the following:
+ * GMII --> RMAC --> AFX --> TRTG --> Rx FIFO --> XDMA --> CPU memory
+ *
+ * Tx will look like the following:
+ * CPU memory --> XDMA --> Tx FIFO --> TRTG --> TMAC --> GMII
+ *
+ * The Titan driver has support for the following performance features:
+ * -> Rx side checksumming
+ * -> Jumbo Frames
+ * -> Interrupt Coalscing
+ * -> Rx NAPI
+ * -> SKB Recycling
+ * -> Transmit/Receive descriptors in SRAM
+ * -> Fast routing for IP forwarding
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <linux/ip.h>
+#include <linux/init.h>
+#include <linux/in.h>
+#include <linux/platform_device.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/mii.h>
+#include <linux/delay.h>
+#include <linux/skbuff.h>
+#include <linux/prefetch.h>
+
+/* For MII specifc registers, titan_mdio.h should be included */
+#include <net/ip.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <asm/pgtable.h>
+#include <asm/system.h>
+#include <asm/titan_dep.h>
+
+#include "titan_ge.h"
+#include "titan_mdio.h"
+
+/* Static Function Declarations	 */
+static int titan_ge_eth_open(struct net_device *);
+static void titan_ge_eth_stop(struct net_device *);
+static struct net_device_stats *titan_ge_get_stats(struct net_device *);
+static int titan_ge_init_rx_desc_ring(titan_ge_port_info *, int, int,
+				      unsigned long, unsigned long,
+				      unsigned long);
+static int titan_ge_init_tx_desc_ring(titan_ge_port_info *, int,
+				      unsigned long, unsigned long);
+
+static int titan_ge_open(struct net_device *);
+static int titan_ge_start_xmit(struct sk_buff *, struct net_device *);
+static int titan_ge_stop(struct net_device *);
+
+static unsigned long titan_ge_tx_coal(unsigned long, int);
+
+static void titan_ge_port_reset(unsigned int);
+static int titan_ge_free_tx_queue(titan_ge_port_info *);
+static int titan_ge_rx_task(struct net_device *, titan_ge_port_info *);
+static int titan_ge_port_start(struct net_device *, titan_ge_port_info *);
+
+static int titan_ge_return_tx_desc(titan_ge_port_info *, int);
+
+/*
+ * Some configuration for the FIFO and the XDMA channel needs
+ * to be done only once for all the ports. This flag controls
+ * that
+ */
+static unsigned long config_done;
+
+/*
+ * One time out of memory flag
+ */
+static unsigned int oom_flag;
+
+static int titan_ge_poll(struct net_device *netdev, int *budget);
+
+static int titan_ge_receive_queue(struct net_device *, unsigned int);
+
+static struct platform_device *titan_ge_device[3];
+
+/* MAC Address */
+extern unsigned char titan_ge_mac_addr_base[6];
+
+unsigned long titan_ge_base;
+static unsigned long titan_ge_sram;
+
+static char titan_string[] = "titan";
+
+/*
+ * The Titan GE has two alignment requirements:
+ * -> skb->data to be cacheline aligned (32 byte)
+ * -> IP header alignment to 16 bytes
+ *
+ * The latter is not implemented. So, that results in an extra copy on
+ * the Rx. This is a big performance hog. For the former case, the
+ * dev_alloc_skb() has been replaced with titan_ge_alloc_skb(). The size
+ * requested is calculated:
+ *
+ * Ethernet Frame Size : 1518
+ * Ethernet Header     : 14
+ * Future Titan change for IP header alignment : 2
+ *
+ * Hence, we allocate (1518 + 14 + 2+ 64) = 1580 bytes.  For IP header
+ * alignment, we use skb_reserve().
+ */
+
+#define ALIGNED_RX_SKB_ADDR(addr) \
+	((((unsigned long)(addr) + (64UL - 1UL)) \
+	& ~(64UL - 1UL)) - (unsigned long)(addr))
+
+#define titan_ge_alloc_skb(__length, __gfp_flags) \
+({      struct sk_buff *__skb; \
+	__skb = alloc_skb((__length) + 64, (__gfp_flags)); \
+	if(__skb) { \
+		int __offset = (int) ALIGNED_RX_SKB_ADDR(__skb->data); \
+		if(__offset) \
+			skb_reserve(__skb, __offset); \
+	} \
+	__skb; \
+})
+
+/*
+ * Configure the GMII block of the Titan based on what the PHY tells us
+ */
+static void titan_ge_gmii_config(int port_num)
+{
+	unsigned int reg_data = 0, phy_reg;
+	int err;
+
+	err = titan_ge_mdio_read(port_num, TITAN_GE_MDIO_PHY_STATUS, &phy_reg);
+
+	if (err == TITAN_GE_MDIO_ERROR) {
+		printk(KERN_ERR
+		       "Could not read PHY control register 0x11 \n");
+		printk(KERN_ERR
+			"Setting speed to 1000 Mbps and Duplex to Full \n");
+
+		return;
+	}
+
+	err = titan_ge_mdio_write(port_num, TITAN_GE_MDIO_PHY_IE, 0);
+
+	if (phy_reg & 0x8000) {
+		if (phy_reg & 0x2000) {
+			/* Full Duplex and 1000 Mbps */
+			TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
+					(port_num << 12)), 0x201);
+		}  else {
+			/* Half Duplex and 1000 Mbps */
+			TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
+					(port_num << 12)), 0x2201);
+			}
+	}
+	if (phy_reg & 0x4000) {
+		if (phy_reg & 0x2000) {
+			/* Full Duplex and 100 Mbps */
+			TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
+					(port_num << 12)), 0x100);
+		} else {
+			/* Half Duplex and 100 Mbps */
+			TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
+					(port_num << 12)), 0x2100);
+		}
+	}
+	reg_data = TITAN_GE_READ(TITAN_GE_GMII_CONFIG_GENERAL +
+				(port_num << 12));
+	reg_data |= 0x3;
+	TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_GENERAL +
+			(port_num << 12)), reg_data);
+}
+
+/*
+ * Enable the TMAC if it is not
+ */
+static void titan_ge_enable_tx(unsigned int port_num)
+{
+	unsigned long reg_data;
+
+	reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + (port_num << 12));
+	if (!(reg_data & 0x8000)) {
+		printk("TMAC disabled for port %d!! \n", port_num);
+
+		reg_data |= 0x0001;	/* Enable TMAC */
+		reg_data |= 0x4000;	/* CRC Check Enable */
+		reg_data |= 0x2000;	/* Padding enable */
+		reg_data |= 0x0800;	/* CRC Add enable */
+		reg_data |= 0x0080;	/* PAUSE frame */
+
+		TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
+				(port_num << 12)), reg_data);
+	}
+}
+
+/*
+ * Tx Timeout function
+ */
+static void titan_ge_tx_timeout(struct net_device *netdev)
+{
+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
+
+	printk(KERN_INFO "%s: TX timeout  ", netdev->name);
+	printk(KERN_INFO "Resetting card \n");
+
+	/* Do the reset outside of interrupt context */
+	schedule_work(&titan_ge_eth->tx_timeout_task);
+}
+
+/*
+ * Update the AFX tables for UC and MC for slice 0 only
+ */
+static void titan_ge_update_afx(titan_ge_port_info * titan_ge_eth)
+{
+	int port = titan_ge_eth->port_num;
+	unsigned int i;
+	volatile unsigned long reg_data = 0;
+	u8 p_addr[6];
+
+	memcpy(p_addr, titan_ge_eth->port_mac_addr, 6);
+
+	/* Set the MAC address here for TMAC and RMAC */
+	TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_HI + (port << 12)),
+		       ((p_addr[5] << 8) | p_addr[4]));
+	TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_MID + (port << 12)),
+		       ((p_addr[3] << 8) | p_addr[2]));
+	TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_LOW + (port << 12)),
+		       ((p_addr[1] << 8) | p_addr[0]));
+
+	TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_HI + (port << 12)),
+		       ((p_addr[5] << 8) | p_addr[4]));
+	TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_MID + (port << 12)),
+		       ((p_addr[3] << 8) | p_addr[2]));
+	TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_LOW + (port << 12)),
+		       ((p_addr[1] << 8) | p_addr[0]));
+
+	TITAN_GE_WRITE((0x112c | (port << 12)), 0x1);
+	/* Configure the eight address filters */
+	for (i = 0; i < 8; i++) {
+		/* Select each of the eight filters */
+		TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_2 +
+				(port << 12)), i);
+
+		/* Configure the match */
+		reg_data = 0x9;	/* Forward Enable Bit */
+		TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_0 +
+				(port << 12)), reg_data);
+
+		/* Finally, AFX Exact Match Address Registers */
+		TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_LOW + (port << 12)),
+			       ((p_addr[1] << 8) | p_addr[0]));
+		TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_MID + (port << 12)),
+			       ((p_addr[3] << 8) | p_addr[2]));
+		TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_HIGH + (port << 12)),
+			       ((p_addr[5] << 8) | p_addr[4]));
+
+		/* VLAN id set to 0 */
+		TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_VID +
+				(port << 12)), 0);
+	}
+}
+
+/*
+ * Actual Routine to reset the adapter when the timeout occurred
+ */
+static void titan_ge_tx_timeout_task(struct net_device *netdev)
+{
+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
+	int port = titan_ge_eth->port_num;
+
+	printk("Titan GE: Transmit timed out. Resetting ... \n");
+
+	/* Dump debug info */
+	printk(KERN_ERR "TRTG cause : %x \n",
+			TITAN_GE_READ(0x100c + (port << 12)));
+
+	/* Fix this for the other ports */
+	printk(KERN_ERR "FIFO cause : %x \n", TITAN_GE_READ(0x482c));
+	printk(KERN_ERR "IE cause : %x \n", TITAN_GE_READ(0x0040));
+	printk(KERN_ERR "XDMA GDI ERROR : %x \n",
+			TITAN_GE_READ(0x5008 + (port << 8)));
+	printk(KERN_ERR "CHANNEL ERROR: %x \n",
+			TITAN_GE_READ(TITAN_GE_CHANNEL0_INTERRUPT
+						+ (port << 8)));
+
+	netif_device_detach(netdev);
+	titan_ge_port_reset(titan_ge_eth->port_num);
+	titan_ge_port_start(netdev, titan_ge_eth);
+	netif_device_attach(netdev);
+}
+
+/*
+ * Change the MTU of the Ethernet Device
+ */
+static int titan_ge_change_mtu(struct net_device *netdev, int new_mtu)
+{
+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
+	unsigned long flags;
+
+	if ((new_mtu > 9500) || (new_mtu < 64))
+		return -EINVAL;
+
+	spin_lock_irqsave(&titan_ge_eth->lock, flags);
+
+	netdev->mtu = new_mtu;
+
+	/* Now we have to reopen the interface so that SKBs with the new
+	 * size will be allocated */
+
+	if (netif_running(netdev)) {
+		titan_ge_eth_stop(netdev);
+
+		if (titan_ge_eth_open(netdev) != TITAN_OK) {
+			printk(KERN_ERR
+			       "%s: Fatal error on opening device\n",
+			       netdev->name);
+			spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
+			return -1;
+		}
+	}
+
+	spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
+	return 0;
+}
+
+/*
+ * Titan Gbe Interrupt Handler. All the three ports send interrupt to one line
+ * only. Once an interrupt is triggered, figure out the port and then check
+ * the channel.
+ */
+static irqreturn_t titan_ge_int_handler(int irq, void *dev_id)
+{
+	struct net_device *netdev = (struct net_device *) dev_id;
+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
+	unsigned int port_num = titan_ge_eth->port_num;
+	unsigned int reg_data;
+	unsigned int eth_int_cause_error = 0, is;
+	unsigned long eth_int_cause1;
+	int err = 0;
+#ifdef CONFIG_SMP
+	unsigned long eth_int_cause2;
+#endif
+
+	/* Ack the CPU interrupt */
+	switch (port_num) {
+	case 0:
+		is = OCD_READ(RM9000x2_OCD_INTP0STATUS1);
+		OCD_WRITE(RM9000x2_OCD_INTP0CLEAR1, is);
+
+#ifdef CONFIG_SMP
+		is = OCD_READ(RM9000x2_OCD_INTP1STATUS1);
+		OCD_WRITE(RM9000x2_OCD_INTP1CLEAR1, is);
+#endif
+		break;
+
+	case 1:
+		is = OCD_READ(RM9000x2_OCD_INTP0STATUS0);
+		OCD_WRITE(RM9000x2_OCD_INTP0CLEAR0, is);
+
+#ifdef CONFIG_SMP
+		is = OCD_READ(RM9000x2_OCD_INTP1STATUS0);
+		OCD_WRITE(RM9000x2_OCD_INTP1CLEAR0, is);
+#endif
+		break;
+
+	case 2:
+		is = OCD_READ(RM9000x2_OCD_INTP0STATUS4);
+		OCD_WRITE(RM9000x2_OCD_INTP0CLEAR4, is);
+
+#ifdef CONFIG_SMP
+		is = OCD_READ(RM9000x2_OCD_INTP1STATUS4);
+		OCD_WRITE(RM9000x2_OCD_INTP1CLEAR4, is);
+#endif
+	}
+
+	eth_int_cause1 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_A);
+#ifdef CONFIG_SMP
+	eth_int_cause2 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_B);
+#endif
+
+	/* Spurious interrupt */
+#ifdef CONFIG_SMP
+	if ( (eth_int_cause1 == 0) && (eth_int_cause2 == 0)) {
+#else
+	if (eth_int_cause1 == 0) {
+#endif
+		eth_int_cause_error = TITAN_GE_READ(TITAN_GE_CHANNEL0_INTERRUPT +
+					(port_num << 8));
+
+		if (eth_int_cause_error == 0)
+			return IRQ_NONE;
+	}
+
+	/* Handle Tx first. No need to ack interrupts */
+#ifdef CONFIG_SMP
+	if ( (eth_int_cause1 & 0x20202) ||
+		(eth_int_cause2 & 0x20202) )
+#else
+	if (eth_int_cause1 & 0x20202)
+#endif
+		titan_ge_free_tx_queue(titan_ge_eth);
+
+	/* Handle the Rx next */
+#ifdef CONFIG_SMP
+	if ( (eth_int_cause1 & 0x10101) ||
+		(eth_int_cause2 & 0x10101)) {
+#else
+	if (eth_int_cause1 & 0x10101) {
+#endif
+		if (netif_rx_schedule_prep(netdev)) {
+			unsigned int ack;
+
+			ack = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
+			/* Disable Tx and Rx both */
+			if (port_num == 0)
+				ack &= ~(0x3);
+			if (port_num == 1)
+				ack &= ~(0x300);
+
+			if (port_num == 2)
+				ack &= ~(0x30000);
+
+			/* Interrupts have been disabled */
+			TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, ack);
+
+			__netif_rx_schedule(netdev);
+		}
+	}
+
+	/* Handle error interrupts */
+	if (eth_int_cause_error && (eth_int_cause_error != 0x2)) {
+		printk(KERN_ERR
+			"XDMA Channel Error : %x  on port %d\n",
+			eth_int_cause_error, port_num);
+
+		printk(KERN_ERR
+			"XDMA GDI Hardware error : %x  on port %d\n",
+			TITAN_GE_READ(0x5008 + (port_num << 8)), port_num);
+
+		printk(KERN_ERR
+			"XDMA currently has %d Rx descriptors \n",
+			TITAN_GE_READ(0x5048 + (port_num << 8)));
+
+		printk(KERN_ERR
+			"XDMA currently has prefetcted %d Rx descriptors \n",
+			TITAN_GE_READ(0x505c + (port_num << 8)));
+
+		TITAN_GE_WRITE((TITAN_GE_CHANNEL0_INTERRUPT +
+			       (port_num << 8)), eth_int_cause_error);
+	}
+
+	/*
+	 * PHY interrupt to inform abt the changes. Reading the
+	 * PHY Status register will clear the interrupt
+	 */
+	if ((!(eth_int_cause1 & 0x30303)) &&
+		(eth_int_cause_error == 0)) {
+		err =
+		    titan_ge_mdio_read(port_num,
+			       TITAN_GE_MDIO_PHY_IS, &reg_data);
+
+		if (reg_data & 0x0400) {
+			/* Link status change */
+			titan_ge_mdio_read(port_num,
+				   TITAN_GE_MDIO_PHY_STATUS, &reg_data);
+			if (!(reg_data & 0x0400)) {
+				/* Link is down */
+				netif_carrier_off(netdev);
+				netif_stop_queue(netdev);
+			} else {
+				/* Link is up */
+				netif_carrier_on(netdev);
+				netif_wake_queue(netdev);
+
+				/* Enable the queue */
+				titan_ge_enable_tx(port_num);
+			}
+		}
+	}
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * Multicast and Promiscuous mode set. The
+ * set_multi entry point is called whenever the
+ * multicast address list or the network interface
+ * flags are updated.
+ */
+static void titan_ge_set_multi(struct net_device *netdev)
+{
+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
+	unsigned int port_num = titan_ge_eth->port_num;
+	unsigned long reg_data;
+
+	reg_data = TITAN_GE_READ(TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 +
+				(port_num << 12));
+
+	if (netdev->flags & IFF_PROMISC) {
+		reg_data |= 0x2;
+	}
+	else if (netdev->flags & IFF_ALLMULTI) {
+		reg_data |= 0x01;
+		reg_data |= 0x400; /* Use the 64-bit Multicast Hash bin */
+	}
+	else {
+		reg_data = 0x2;
+	}
+
+	TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 +
+			(port_num << 12)), reg_data);
+	if (reg_data & 0x01) {
+		TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_LOW +
+				(port_num << 12)), 0xffff);
+		TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_MIDLOW +
+				(port_num << 12)), 0xffff);
+		TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_MIDHI +
+				(port_num << 12)), 0xffff);
+		TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_HI +
+				(port_num << 12)), 0xffff);
+	}
+}
+
+/*
+ * Open the network device
+ */
+static int titan_ge_open(struct net_device *netdev)
+{
+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
+	unsigned int port_num = titan_ge_eth->port_num;
+	unsigned int irq = TITAN_ETH_PORT_IRQ - port_num;
+	int retval;
+
+	retval = request_irq(irq, titan_ge_int_handler,
+		     SA_INTERRUPT | SA_SAMPLE_RANDOM , netdev->name, netdev);
+
+	if (retval != 0) {
+		printk(KERN_ERR "Cannot assign IRQ number to TITAN GE \n");
+		return -1;
+	}
+
+	netdev->irq = irq;
+	printk(KERN_INFO "Assigned IRQ %d to port %d\n", irq, port_num);
+
+	spin_lock_irq(&(titan_ge_eth->lock));
+
+	if (titan_ge_eth_open(netdev) != TITAN_OK) {
+		spin_unlock_irq(&(titan_ge_eth->lock));
+		printk("%s: Error opening interface \n", netdev->name);
+		free_irq(netdev->irq, netdev);
+		return -EBUSY;
+	}
+
+	spin_unlock_irq(&(titan_ge_eth->lock));
+
+	return 0;
+}
+
+/*
+ * Allocate the SKBs for the Rx ring. Also used
+ * for refilling the queue
+ */
+static int titan_ge_rx_task(struct net_device *netdev,
+				titan_ge_port_info *titan_ge_port)
+{
+	struct device *device = &titan_ge_device[titan_ge_port->port_num]->dev;
+	volatile titan_ge_rx_desc *rx_desc;
+	struct sk_buff *skb;
+	int rx_used_desc;
+	int count = 0;
+
+	while (titan_ge_port->rx_ring_skbs < titan_ge_port->rx_ring_size) {
+
+	/* First try to get the skb from the recycler */
+#ifdef TITAN_GE_JUMBO_FRAMES
+		skb = titan_ge_alloc_skb(TITAN_GE_JUMBO_BUFSIZE, GFP_ATOMIC);
+#else
+		skb = titan_ge_alloc_skb(TITAN_GE_STD_BUFSIZE, GFP_ATOMIC);
+#endif
+		if (unlikely(!skb)) {
+			/* OOM, set the flag */
+			printk("OOM \n");
+			oom_flag = 1;
+			break;
+		}
+		count++;
+		skb->dev = netdev;
+
+		titan_ge_port->rx_ring_skbs++;
+
+		rx_used_desc = titan_ge_port->rx_used_desc_q;
+		rx_desc = &(titan_ge_port->rx_desc_area[rx_used_desc]);
+
+#ifdef TITAN_GE_JUMBO_FRAMES
+		rx_desc->buffer_addr = dma_map_single(device, skb->data,
+				TITAN_GE_JUMBO_BUFSIZE - 2, DMA_FROM_DEVICE);
+#else
+		rx_desc->buffer_addr = dma_map_single(device, skb->data,
+				TITAN_GE_STD_BUFSIZE - 2, DMA_FROM_DEVICE);
+#endif
+
+		titan_ge_port->rx_skb[rx_used_desc] = skb;
+		rx_desc->cmd_sts = TITAN_GE_RX_BUFFER_OWNED;
+
+		titan_ge_port->rx_used_desc_q =
+			(rx_used_desc + 1) % TITAN_GE_RX_QUEUE;
+	}
+
+	return count;
+}
+
+/*
+ * Actual init of the Tital GE port. There is one register for
+ * the channel configuration
+ */
+static void titan_port_init(struct net_device *netdev,
+			    titan_ge_port_info * titan_ge_eth)
+{
+	unsigned long reg_data;
+
+	titan_ge_port_reset(titan_ge_eth->port_num);
+
+	/* First reset the TMAC */
+	reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
+	reg_data |= 0x80000000;
+	TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
+
+	udelay(30);
+
+	reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
+	reg_data &= ~(0xc0000000);
+	TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
+
+	/* Now reset the RMAC */
+	reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
+	reg_data |= 0x00080000;
+	TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
+
+	udelay(30);
+
+	reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
+	reg_data &= ~(0x000c0000);
+	TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
+}
+
+/*
+ * Start the port. All the hardware specific configuration
+ * for the XDMA, Tx FIFO, Rx FIFO, TMAC, RMAC, TRTG and AFX
+ * go here
+ */
+static int titan_ge_port_start(struct net_device *netdev,
+				titan_ge_port_info * titan_port)
+{
+	volatile unsigned long reg_data, reg_data1;
+	int port_num = titan_port->port_num;
+	int count = 0;
+	unsigned long reg_data_1;
+
+	if (config_done == 0) {
+		reg_data = TITAN_GE_READ(0x0004);
+		reg_data |= 0x100;
+		TITAN_GE_WRITE(0x0004, reg_data);
+
+		reg_data &= ~(0x100);
+		TITAN_GE_WRITE(0x0004, reg_data);
+
+		/* Turn on GMII/MII mode and turn off TBI mode */
+		reg_data = TITAN_GE_READ(TITAN_GE_TSB_CTRL_1);
+		reg_data |= 0x00000700;
+		reg_data &= ~(0x00800000); /* Fencing */
+
+		TITAN_GE_WRITE(0x000c, 0x00001100);
+
+		TITAN_GE_WRITE(TITAN_GE_TSB_CTRL_1, reg_data);
+
+		/* Set the CPU Resource Limit register */
+		TITAN_GE_WRITE(0x00f8, 0x8);
+
+		/* Be conservative when using the BIU buffers */
+		TITAN_GE_WRITE(0x0068, 0x4);
+	}
+
+	titan_port->tx_threshold = 0;
+	titan_port->rx_threshold = 0;
+
+	/* We need to write the descriptors for Tx and Rx */
+	TITAN_GE_WRITE((TITAN_GE_CHANNEL0_TX_DESC + (port_num << 8)),
+		       (unsigned long) titan_port->tx_dma);
+	TITAN_GE_WRITE((TITAN_GE_CHANNEL0_RX_DESC + (port_num << 8)),
+		       (unsigned long) titan_port->rx_dma);
+
+	if (config_done == 0) {
+		/* Step 1:  XDMA config	*/
+		reg_data = TITAN_GE_READ(TITAN_GE_XDMA_CONFIG);
+		reg_data &= ~(0x80000000);      /* clear reset */
+		reg_data |= 0x1 << 29;	/* sparse tx descriptor spacing */
+		reg_data |= 0x1 << 28;	/* sparse rx descriptor spacing */
+		reg_data |= (0x1 << 23) | (0x1 << 24);  /* Descriptor Coherency */
+		reg_data |= (0x1 << 21) | (0x1 << 22);  /* Data Coherency */
+		TITAN_GE_WRITE(TITAN_GE_XDMA_CONFIG, reg_data);
+	}
+
+	/* IR register for the XDMA */
+	reg_data = TITAN_GE_READ(TITAN_GE_GDI_INTERRUPT_ENABLE + (port_num << 8));
+	reg_data |= 0x80068000; /* No Rx_OOD */
+	TITAN_GE_WRITE((TITAN_GE_GDI_INTERRUPT_ENABLE + (port_num << 8)), reg_data);
+
+	/* Start the Tx and Rx XDMA controller */
+	reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG + (port_num << 8));
+	reg_data &= 0x4fffffff;     /* Clear tx reset */
+	reg_data &= 0xfff4ffff;     /* Clear rx reset */
+
+#ifdef TITAN_GE_JUMBO_FRAMES
+	reg_data |= 0xa0 | 0x30030000;
+#else
+	reg_data |= 0x40 | 0x20030000;
+#endif
+
+#ifndef CONFIG_SMP
+	reg_data &= ~(0x10);
+	reg_data |= 0x0f; /* All of the packet */
+#endif
+
+	TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG + (port_num << 8)), reg_data);
+
+	/* Rx desc count */
+	count = titan_ge_rx_task(netdev, titan_port);
+	TITAN_GE_WRITE((0x5048 + (port_num << 8)), count);
+	count = TITAN_GE_READ(0x5048 + (port_num << 8));
+
+	udelay(30);
+
+	/*
+	 * Step 2:  Configure the SDQPF, i.e. FIFO
+	 */
+	if (config_done == 0) {
+		reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_CTL);
+		reg_data = 0x1;
+		TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
+		reg_data &= ~(0x1);
+		TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
+		reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_CTL);
+		TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
+
+		reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_CTL);
+		reg_data = 0x1;
+		TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
+		reg_data &= ~(0x1);
+		TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
+		reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_CTL);
+		TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
+	}
+	/*
+	 * Enable RX FIFO 0, 4 and 8
+	 */
+	if (port_num == 0) {
+		reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_0);
+
+		reg_data |= 0x100000;
+		reg_data |= (0xff << 10);
+
+		TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_0, reg_data);
+		/*
+		 * BAV2,BAV and DAV settings for the Rx FIFO
+		 */
+		reg_data1 = TITAN_GE_READ(0x4844);
+		reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
+		TITAN_GE_WRITE(0x4844, reg_data1);
+
+		reg_data &= ~(0x00100000);
+		reg_data |= 0x200000;
+
+		TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_0, reg_data);
+
+		reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_0);
+		reg_data |= 0x100000;
+
+		TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
+
+		reg_data |= (0xff << 10);
+
+		TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
+
+		/*
+		 * BAV2, BAV and DAV settings for the Tx FIFO
+		 */
+		reg_data1 = TITAN_GE_READ(0x4944);
+		reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
+
+		TITAN_GE_WRITE(0x4944, reg_data1);
+
+		reg_data &= ~(0x00100000);
+		reg_data |= 0x200000;
+
+		TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
+
+	}
+
+	if (port_num == 1) {
+		reg_data = TITAN_GE_READ(0x4870);
+
+		reg_data |= 0x100000;
+		reg_data |= (0xff << 10) | (0xff + 1);
+
+		TITAN_GE_WRITE(0x4870, reg_data);
+		/*
+		 * BAV2,BAV and DAV settings for the Rx FIFO
+		 */
+		reg_data1 = TITAN_GE_READ(0x4874);
+		reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
+		TITAN_GE_WRITE(0x4874, reg_data1);
+
+		reg_data &= ~(0x00100000);
+		reg_data |= 0x200000;
+
+		TITAN_GE_WRITE(0x4870, reg_data);
+
+		reg_data = TITAN_GE_READ(0x494c);
+		reg_data |= 0x100000;
+
+		TITAN_GE_WRITE(0x494c, reg_data);
+		reg_data |= (0xff << 10) | (0xff + 1);
+		TITAN_GE_WRITE(0x494c, reg_data);
+
+		/*
+		 * BAV2, BAV and DAV settings for the Tx FIFO
+		 */
+		reg_data1 = TITAN_GE_READ(0x4950);
+		reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
+
+		TITAN_GE_WRITE(0x4950, reg_data1);
+
+		reg_data &= ~(0x00100000);
+		reg_data |= 0x200000;
+
+		TITAN_GE_WRITE(0x494c, reg_data);
+	}
+
+	/*
+	 * Titan 1.2 revision does support port #2
+	 */
+	if (port_num == 2) {
+		/*
+		 * Put the descriptors in the SRAM
+		 */
+		reg_data = TITAN_GE_READ(0x48a0);
+
+		reg_data |= 0x100000;
+		reg_data |= (0xff << 10) | (2*(0xff + 1));
+
+		TITAN_GE_WRITE(0x48a0, reg_data);
+		/*
+		 * BAV2,BAV and DAV settings for the Rx FIFO
+		 */
+		reg_data1 = TITAN_GE_READ(0x48a4);
+		reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
+		TITAN_GE_WRITE(0x48a4, reg_data1);
+
+		reg_data &= ~(0x00100000);
+		reg_data |= 0x200000;
+
+		TITAN_GE_WRITE(0x48a0, reg_data);
+
+		reg_data = TITAN_GE_READ(0x4958);
+		reg_data |= 0x100000;
+
+		TITAN_GE_WRITE(0x4958, reg_data);
+		reg_data |= (0xff << 10) | (2*(0xff + 1));
+		TITAN_GE_WRITE(0x4958, reg_data);
+
+		/*
+		 * BAV2, BAV and DAV settings for the Tx FIFO
+		 */
+		reg_data1 = TITAN_GE_READ(0x495c);
+		reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
+
+		TITAN_GE_WRITE(0x495c, reg_data1);
+
+		reg_data &= ~(0x00100000);
+		reg_data |= 0x200000;
+
+		TITAN_GE_WRITE(0x4958, reg_data);
+	}
+
+	if (port_num == 2) {
+		reg_data = TITAN_GE_READ(0x48a0);
+
+		reg_data |= 0x100000;
+		reg_data |= (0xff << 10) | (2*(0xff + 1));
+
+		TITAN_GE_WRITE(0x48a0, reg_data);
+		/*
+		 * BAV2,BAV and DAV settings for the Rx FIFO
+		 */
+		reg_data1 = TITAN_GE_READ(0x48a4);
+		reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
+		TITAN_GE_WRITE(0x48a4, reg_data1);
+
+		reg_data &= ~(0x00100000);
+		reg_data |= 0x200000;
+
+		TITAN_GE_WRITE(0x48a0, reg_data);
+
+		reg_data = TITAN_GE_READ(0x4958);
+		reg_data |= 0x100000;
+
+		TITAN_GE_WRITE(0x4958, reg_data);
+		reg_data |= (0xff << 10) | (2*(0xff + 1));
+		TITAN_GE_WRITE(0x4958, reg_data);
+
+		/*
+		 * BAV2, BAV and DAV settings for the Tx FIFO
+		 */
+		reg_data1 = TITAN_GE_READ(0x495c);
+		reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
+
+		TITAN_GE_WRITE(0x495c, reg_data1);
+
+		reg_data &= ~(0x00100000);
+		reg_data |= 0x200000;
+
+		TITAN_GE_WRITE(0x4958, reg_data);
+	}
+
+	/*
+	 * Step 3:  TRTG block enable
+	 */
+	reg_data = TITAN_GE_READ(TITAN_GE_TRTG_CONFIG + (port_num << 12));
+
+	/*
+	 * This is the 1.2 revision of the chip. It has fix for the
+	 * IP header alignment. Now, the IP header begins at an
+	 * aligned address and this wont need an extra copy in the
+	 * driver. This performance drawback existed in the previous
+	 * versions of the silicon
+	 */
+	reg_data_1 = TITAN_GE_READ(0x103c + (port_num << 12));
+	reg_data_1 |= 0x40000000;
+	TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
+
+	reg_data_1 |= 0x04000000;
+	TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
+
+	mdelay(5);
+
+	reg_data_1 &= ~(0x04000000);
+	TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
+
+	mdelay(5);
+
+	reg_data |= 0x0001;
+	TITAN_GE_WRITE((TITAN_GE_TRTG_CONFIG + (port_num << 12)), reg_data);
+
+	/*
+	 * Step 4:  Start the Tx activity
+	 */
+	TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_2 + (port_num << 12)), 0xe197);
+#ifdef TITAN_GE_JUMBO_FRAMES
+	TITAN_GE_WRITE((0x1258 + (port_num << 12)), 0x4000);
+#endif
+	reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + (port_num << 12));
+	reg_data |= 0x0001;	/* Enable TMAC */
+	reg_data |= 0x6c70;	/* PAUSE also set */
+
+	TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 + (port_num << 12)), reg_data);
+
+	udelay(30);
+
+	/* Destination Address drop bit */
+	reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_2 + (port_num << 12));
+	reg_data |= 0x218;        /* DA_DROP bit and pause */
+	TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_2 + (port_num << 12)), reg_data);
+
+	TITAN_GE_WRITE((0x1218 + (port_num << 12)), 0x3);
+
+#ifdef TITAN_GE_JUMBO_FRAMES
+	TITAN_GE_WRITE((0x1208 + (port_num << 12)), 0x4000);
+#endif
+	/* Start the Rx activity */
+	reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + (port_num << 12));
+	reg_data |= 0x0001;	/* RMAC Enable */
+	reg_data |= 0x0010;	/* CRC Check enable */
+	reg_data |= 0x0040;	/* Min Frame check enable */
+	reg_data |= 0x4400;	/* Max Frame check enable */
+
+	TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)), reg_data);
+
+	udelay(30);
+
+	/*
+	 * Enable the Interrupts for Tx and Rx
+	 */
+	reg_data1 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
+
+	if (port_num == 0) {
+		reg_data1 |= 0x3;
+#ifdef CONFIG_SMP
+		TITAN_GE_WRITE(0x0038, 0x003);
+#else
+		TITAN_GE_WRITE(0x0038, 0x303);
+#endif
+	}
+
+	if (port_num == 1) {
+		reg_data1 |= 0x300;
+	}
+
+	if (port_num == 2)
+		reg_data1 |= 0x30000;
+
+	TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data1);
+	TITAN_GE_WRITE(0x003c, 0x300);
+
+	if (config_done == 0) {
+		TITAN_GE_WRITE(0x0024, 0x04000024);	/* IRQ vector */
+		TITAN_GE_WRITE(0x0020, 0x000fb000);	/* INTMSG base */
+	}
+
+	/* Priority */
+	reg_data = TITAN_GE_READ(0x1038 + (port_num << 12));
+	reg_data &= ~(0x00f00000);
+	TITAN_GE_WRITE((0x1038 + (port_num << 12)), reg_data);
+
+	/* Step 5:  GMII config */
+	titan_ge_gmii_config(port_num);
+
+	if (config_done == 0) {
+		TITAN_GE_WRITE(0x1a80, 0);
+		config_done = 1;
+	}
+
+	return TITAN_OK;
+}
+
+/*
+ * Function to queue the packet for the Ethernet device
+ */
+static void titan_ge_tx_queue(titan_ge_port_info * titan_ge_eth,
+				struct sk_buff * skb)
+{
+	struct device *device = &titan_ge_device[titan_ge_eth->port_num]->dev;
+	unsigned int curr_desc = titan_ge_eth->tx_curr_desc_q;
+	volatile titan_ge_tx_desc *tx_curr;
+	int port_num = titan_ge_eth->port_num;
+
+	tx_curr = &(titan_ge_eth->tx_desc_area[curr_desc]);
+	tx_curr->buffer_addr =
+		dma_map_single(device, skb->data, skb_headlen(skb),
+			       DMA_TO_DEVICE);
+
+	titan_ge_eth->tx_skb[curr_desc] = (struct sk_buff *) skb;
+	tx_curr->buffer_len = skb_headlen(skb);
+
+	/* Last descriptor enables interrupt and changes ownership */
+	tx_curr->cmd_sts = 0x1 | (1 << 15) | (1 << 5);
+
+	/* Kick the XDMA to start the transfer from memory to the FIFO */
+	TITAN_GE_WRITE((0x5044 + (port_num << 8)), 0x1);
+
+	/* Current descriptor updated */
+	titan_ge_eth->tx_curr_desc_q = (curr_desc + 1) % TITAN_GE_TX_QUEUE;
+
+	/* Prefetch the next descriptor */
+	prefetch((const void *)
+		 &titan_ge_eth->tx_desc_area[titan_ge_eth->tx_curr_desc_q]);
+}
+
+/*
+ * Actually does the open of the Ethernet device
+ */
+static int titan_ge_eth_open(struct net_device *netdev)
+{
+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
+	unsigned int port_num = titan_ge_eth->port_num;
+	struct device *device = &titan_ge_device[port_num]->dev;
+	unsigned long reg_data;
+	unsigned int phy_reg;
+	int err = 0;
+
+	/* Stop the Rx activity */
+	reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + (port_num << 12));
+	reg_data &= ~(0x00000001);
+	TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)), reg_data);
+
+	/* Clear the port interrupts */
+	TITAN_GE_WRITE((TITAN_GE_CHANNEL0_INTERRUPT + (port_num << 8)), 0x0);
+
+	if (config_done == 0) {
+		TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0);
+		TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_B, 0);
+	}
+
+	/* Set the MAC Address */
+	memcpy(titan_ge_eth->port_mac_addr, netdev->dev_addr, 6);
+
+	if (config_done == 0)
+		titan_port_init(netdev, titan_ge_eth);
+
+	titan_ge_update_afx(titan_ge_eth);
+
+	/* Allocate the Tx ring now */
+	titan_ge_eth->tx_ring_skbs = 0;
+	titan_ge_eth->tx_ring_size = TITAN_GE_TX_QUEUE;
+
+	/* Allocate space in the SRAM for the descriptors */
+	titan_ge_eth->tx_desc_area = (titan_ge_tx_desc *)
+		(titan_ge_sram + TITAN_TX_RING_BYTES * port_num);
+	titan_ge_eth->tx_dma = TITAN_SRAM_BASE + TITAN_TX_RING_BYTES * port_num;
+
+	if (!titan_ge_eth->tx_desc_area) {
+		printk(KERN_ERR
+		       "%s: Cannot allocate Tx Ring (size %d bytes) for port %d\n",
+		       netdev->name, TITAN_TX_RING_BYTES, port_num);
+		return -ENOMEM;
+	}
+
+	memset(titan_ge_eth->tx_desc_area, 0, titan_ge_eth->tx_desc_area_size);
+
+	/* Now initialize the Tx descriptor ring */
+	titan_ge_init_tx_desc_ring(titan_ge_eth,
+				   titan_ge_eth->tx_ring_size,
+				   (unsigned long) titan_ge_eth->tx_desc_area,
+				   (unsigned long) titan_ge_eth->tx_dma);
+
+	/* Allocate the Rx ring now */
+	titan_ge_eth->rx_ring_size = TITAN_GE_RX_QUEUE;
+	titan_ge_eth->rx_ring_skbs = 0;
+
+	titan_ge_eth->rx_desc_area =
+		(titan_ge_rx_desc *)(titan_ge_sram + 0x1000 + TITAN_RX_RING_BYTES * port_num);
+
+	titan_ge_eth->rx_dma = TITAN_SRAM_BASE + 0x1000 + TITAN_RX_RING_BYTES * port_num;
+
+	if (!titan_ge_eth->rx_desc_area) {
+		printk(KERN_ERR "%s: Cannot allocate Rx Ring (size %d bytes)\n",
+		       netdev->name, TITAN_RX_RING_BYTES);
+
+		printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
+		       netdev->name);
+
+		dma_free_coherent(device, titan_ge_eth->tx_desc_area_size,
+				    (void *) titan_ge_eth->tx_desc_area,
+				    titan_ge_eth->tx_dma);
+
+		return -ENOMEM;
+	}
+
+	memset(titan_ge_eth->rx_desc_area, 0, titan_ge_eth->rx_desc_area_size);
+
+	/* Now initialize the Rx ring */
+#ifdef TITAN_GE_JUMBO_FRAMES
+	if ((titan_ge_init_rx_desc_ring
+	    (titan_ge_eth, titan_ge_eth->rx_ring_size, TITAN_GE_JUMBO_BUFSIZE,
+	     (unsigned long) titan_ge_eth->rx_desc_area, 0,
+	      (unsigned long) titan_ge_eth->rx_dma)) == 0)
+#else
+	if ((titan_ge_init_rx_desc_ring
+	     (titan_ge_eth, titan_ge_eth->rx_ring_size, TITAN_GE_STD_BUFSIZE,
+	      (unsigned long) titan_ge_eth->rx_desc_area, 0,
+	      (unsigned long) titan_ge_eth->rx_dma)) == 0)
+#endif
+		panic("%s: Error initializing RX Ring\n", netdev->name);
+
+	/* Fill the Rx ring with the SKBs */
+	titan_ge_port_start(netdev, titan_ge_eth);
+
+	/*
+	 * Check if Interrupt Coalscing needs to be turned on. The
+	 * values specified in the register is multiplied by
+	 * (8 x 64 nanoseconds) to determine when an interrupt should
+	 * be sent to the CPU.
+	 */
+
+	if (TITAN_GE_TX_COAL) {
+		titan_ge_eth->tx_int_coal =
+		    titan_ge_tx_coal(TITAN_GE_TX_COAL, port_num);
+	}
+
+	err = titan_ge_mdio_read(port_num, TITAN_GE_MDIO_PHY_STATUS, &phy_reg);
+	if (err == TITAN_GE_MDIO_ERROR) {
+		printk(KERN_ERR
+		       "Could not read PHY control register 0x11 \n");
+		return TITAN_ERROR;
+	}
+	if (!(phy_reg & 0x0400)) {
+		netif_carrier_off(netdev);
+		netif_stop_queue(netdev);
+		return TITAN_ERROR;
+	} else {
+		netif_carrier_on(netdev);
+		netif_start_queue(netdev);
+	}
+
+	return TITAN_OK;
+}
+
+/*
+ * Queue the packet for Tx. Currently no support for zero copy,
+ * checksum offload and Scatter Gather. The chip does support
+ * Scatter Gather only. But, that wont help here since zero copy
+ * requires support for Tx checksumming also.
+ */
+int titan_ge_start_xmit(struct sk_buff *skb, struct net_device *netdev)
+{
+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
+	unsigned long flags;
+	struct net_device_stats *stats;
+//printk("titan_ge_start_xmit\n");
+
+	stats = &titan_ge_eth->stats;
+	spin_lock_irqsave(&titan_ge_eth->lock, flags);
+
+	if ((TITAN_GE_TX_QUEUE - titan_ge_eth->tx_ring_skbs) <=
+	    (skb_shinfo(skb)->nr_frags + 1)) {
+		netif_stop_queue(netdev);
+		spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
+		printk(KERN_ERR "Tx OOD \n");
+		return 1;
+	}
+
+	titan_ge_tx_queue(titan_ge_eth, skb);
+	titan_ge_eth->tx_ring_skbs++;
+
+	if (TITAN_GE_TX_QUEUE <= (titan_ge_eth->tx_ring_skbs + 4)) {
+		spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
+		titan_ge_free_tx_queue(titan_ge_eth);
+		spin_lock_irqsave(&titan_ge_eth->lock, flags);
+	}
+
+	stats->tx_bytes += skb->len;
+	stats->tx_packets++;
+
+	spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
+
+	netdev->trans_start = jiffies;
+
+	return 0;
+}
+
+/*
+ * Actually does the Rx. Rx side checksumming supported.
+ */
+static int titan_ge_rx(struct net_device *netdev, int port_num,
+			titan_ge_port_info * titan_ge_port,
+		       titan_ge_packet * packet)
+{
+	int rx_curr_desc, rx_used_desc;
+	volatile titan_ge_rx_desc *rx_desc;
+
+	rx_curr_desc = titan_ge_port->rx_curr_desc_q;
+	rx_used_desc = titan_ge_port->rx_used_desc_q;
+
+	if (((rx_curr_desc + 1) % TITAN_GE_RX_QUEUE) == rx_used_desc)
+		return TITAN_ERROR;
+
+	rx_desc = &(titan_ge_port->rx_desc_area[rx_curr_desc]);
+
+	if (rx_desc->cmd_sts & TITAN_GE_RX_BUFFER_OWNED)
+		return TITAN_ERROR;
+
+	packet->skb = titan_ge_port->rx_skb[rx_curr_desc];
+	packet->len = (rx_desc->cmd_sts & 0x7fff);
+
+	/*
+	 * At this point, we dont know if the checksumming
+	 * actually helps relieve CPU. So, keep it for
+	 * port 0 only
+	 */
+	packet->checksum = ntohs((rx_desc->buffer & 0xffff0000) >> 16);
+	packet->cmd_sts = rx_desc->cmd_sts;
+
+	titan_ge_port->rx_curr_desc_q = (rx_curr_desc + 1) % TITAN_GE_RX_QUEUE;
+
+	/* Prefetch the next descriptor */
+	prefetch((const void *)
+	       &titan_ge_port->rx_desc_area[titan_ge_port->rx_curr_desc_q + 1]);
+
+	return TITAN_OK;
+}
+
+/*
+ * Free the Tx queue of the used SKBs
+ */
+static int titan_ge_free_tx_queue(titan_ge_port_info *titan_ge_eth)
+{
+	unsigned long flags;
+
+	/* Take the lock */
+	spin_lock_irqsave(&(titan_ge_eth->lock), flags);
+
+	while (titan_ge_return_tx_desc(titan_ge_eth, titan_ge_eth->port_num) == 0)
+		if (titan_ge_eth->tx_ring_skbs != 1)
+			titan_ge_eth->tx_ring_skbs--;
+
+	spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
+
+	return TITAN_OK;
+}
+
+/*
+ * Threshold beyond which we do the cleaning of
+ * Tx queue and new allocation for the Rx
+ * queue
+ */
+#define	TX_THRESHOLD	4
+#define	RX_THRESHOLD	10
+
+/*
+ * Receive the packets and send it to the kernel.
+ */
+static int titan_ge_receive_queue(struct net_device *netdev, unsigned int max)
+{
+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
+	unsigned int port_num = titan_ge_eth->port_num;
+	titan_ge_packet packet;
+	struct net_device_stats *stats;
+	struct sk_buff *skb;
+	unsigned long received_packets = 0;
+	unsigned int ack;
+
+	stats = &titan_ge_eth->stats;
+
+	while ((--max)
+	       && (titan_ge_rx(netdev, port_num, titan_ge_eth, &packet) == TITAN_OK)) {
+		skb = (struct sk_buff *) packet.skb;
+
+		titan_ge_eth->rx_ring_skbs--;
+
+		if (--titan_ge_eth->rx_work_limit < 0)
+			break;
+		received_packets++;
+
+		stats->rx_packets++;
+		stats->rx_bytes += packet.len;
+
+		if ((packet.cmd_sts & TITAN_GE_RX_PERR) ||
+			(packet.cmd_sts & TITAN_GE_RX_OVERFLOW_ERROR) ||
+			(packet.cmd_sts & TITAN_GE_RX_TRUNC) ||
+			(packet.cmd_sts & TITAN_GE_RX_CRC_ERROR)) {
+				stats->rx_dropped++;
+				dev_kfree_skb_any(skb);
+
+				continue;
+		}
+		/*
+		 * Either support fast path or slow path. Decision
+		 * making can really slow down the performance. The
+		 * idea is to cut down the number of checks and improve
+		 * the fastpath.
+		 */
+
+		skb_put(skb, packet.len - 2);
+
+		/*
+		 * Increment data pointer by two since thats where
+		 * the MAC starts
+		 */
+		skb_reserve(skb, 2);
+		skb->protocol = eth_type_trans(skb, netdev);
+		netif_receive_skb(skb);
+
+		if (titan_ge_eth->rx_threshold > RX_THRESHOLD) {
+			ack = titan_ge_rx_task(netdev, titan_ge_eth);
+			TITAN_GE_WRITE((0x5048 + (port_num << 8)), ack);
+			titan_ge_eth->rx_threshold = 0;
+		} else
+			titan_ge_eth->rx_threshold++;
+
+		if (titan_ge_eth->tx_threshold > TX_THRESHOLD) {
+			titan_ge_eth->tx_threshold = 0;
+			titan_ge_free_tx_queue(titan_ge_eth);
+		}
+		else
+			titan_ge_eth->tx_threshold++;
+
+	}
+	return received_packets;
+}
+
+
+/*
+ * Enable the Rx side interrupts
+ */
+static void titan_ge_enable_int(unsigned int port_num,
+			titan_ge_port_info *titan_ge_eth,
+			struct net_device *netdev)
+{
+	unsigned long reg_data = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
+
+	if (port_num == 0)
+		reg_data |= 0x3;
+	if (port_num == 1)
+		reg_data |= 0x300;
+	if (port_num == 2)
+		reg_data |= 0x30000;
+
+	/* Re-enable interrupts */
+	TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data);
+}
+
+/*
+ * Main function to handle the polling for Rx side NAPI.
+ * Receive interrupts have been disabled at this point.
+ * The poll schedules the transmit followed by receive.
+ */
+static int titan_ge_poll(struct net_device *netdev, int *budget)
+{
+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
+	int port_num = titan_ge_eth->port_num;
+	int work_done = 0;
+	unsigned long flags, status;
+
+	titan_ge_eth->rx_work_limit = *budget;
+	if (titan_ge_eth->rx_work_limit > netdev->quota)
+		titan_ge_eth->rx_work_limit = netdev->quota;
+
+	do {
+		/* Do the transmit cleaning work here */
+		titan_ge_free_tx_queue(titan_ge_eth);
+
+		/* Ack the Rx interrupts */
+		if (port_num == 0)
+			TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x3);
+		if (port_num == 1)
+			TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x300);
+		if (port_num == 2)
+			TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x30000);
+
+		work_done += titan_ge_receive_queue(netdev, 0);
+
+		/* Out of quota and there is work to be done */
+		if (titan_ge_eth->rx_work_limit < 0)
+			goto not_done;
+
+		/* Receive alloc_skb could lead to OOM */
+		if (oom_flag == 1) {
+			oom_flag = 0;
+			goto oom;
+		}
+
+		status = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_A);
+	} while (status & 0x30300);
+
+	/* If we are here, then no more interrupts to process */
+	goto done;
+
+not_done:
+	*budget -= work_done;
+	netdev->quota -= work_done;
+	return 1;
+
+oom:
+	printk(KERN_ERR "OOM \n");
+	netif_rx_complete(netdev);
+	return 0;
+
+done:
+	/*
+	 * No more packets on the poll list. Turn the interrupts
+	 * back on and we should be able to catch the new
+	 * packets in the interrupt handler
+	 */
+	if (!work_done)
+		work_done = 1;
+
+	*budget -= work_done;
+	netdev->quota -= work_done;
+
+	spin_lock_irqsave(&titan_ge_eth->lock, flags);
+
+	/* Remove us from the poll list */
+	netif_rx_complete(netdev);
+
+	/* Re-enable interrupts */
+	titan_ge_enable_int(port_num, titan_ge_eth, netdev);
+
+	spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
+
+	return 0;
+}
+
+/*
+ * Close the network device
+ */
+int titan_ge_stop(struct net_device *netdev)
+{
+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
+
+	spin_lock_irq(&(titan_ge_eth->lock));
+	titan_ge_eth_stop(netdev);
+	free_irq(netdev->irq, netdev);
+	spin_unlock_irq(&titan_ge_eth->lock);
+
+	return TITAN_OK;
+}
+
+/*
+ * Free the Tx ring
+ */
+static void titan_ge_free_tx_rings(struct net_device *netdev)
+{
+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
+	unsigned int port_num = titan_ge_eth->port_num;
+	unsigned int curr;
+	unsigned long reg_data;
+
+	/* Stop the Tx DMA */
+	reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG +
+				(port_num << 8));
+	reg_data |= 0xc0000000;
+	TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG +
+			(port_num << 8)), reg_data);
+
+	/* Disable the TMAC */
+	reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 +
+				(port_num << 12));
+	reg_data &= ~(0x00000001);
+	TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
+			(port_num << 12)), reg_data);
+
+	for (curr = 0;
+	     (titan_ge_eth->tx_ring_skbs) && (curr < TITAN_GE_TX_QUEUE);
+	     curr++) {
+		if (titan_ge_eth->tx_skb[curr]) {
+			dev_kfree_skb(titan_ge_eth->tx_skb[curr]);
+			titan_ge_eth->tx_ring_skbs--;
+		}
+	}
+
+	if (titan_ge_eth->tx_ring_skbs != 0)
+		printk
+		    ("%s: Error on Tx descriptor free - could not free %d"
+		     " descriptors\n", netdev->name,
+		     titan_ge_eth->tx_ring_skbs);
+
+#ifndef TITAN_RX_RING_IN_SRAM
+	dma_free_coherent(&titan_ge_device[port_num]->dev,
+			  titan_ge_eth->tx_desc_area_size,
+			  (void *) titan_ge_eth->tx_desc_area,
+			  titan_ge_eth->tx_dma);
+#endif
+}
+
+/*
+ * Free the Rx ring
+ */
+static void titan_ge_free_rx_rings(struct net_device *netdev)
+{
+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
+	unsigned int port_num = titan_ge_eth->port_num;
+	unsigned int curr;
+	unsigned long reg_data;
+
+	/* Stop the Rx DMA */
+	reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG +
+				(port_num << 8));
+	reg_data |= 0x000c0000;
+	TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG +
+			(port_num << 8)), reg_data);
+
+	/* Disable the RMAC */
+	reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 +
+				(port_num << 12));
+	reg_data &= ~(0x00000001);
+	TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 +
+			(port_num << 12)), reg_data);
+
+	for (curr = 0;
+	     titan_ge_eth->rx_ring_skbs && (curr < TITAN_GE_RX_QUEUE);
+	     curr++) {
+		if (titan_ge_eth->rx_skb[curr]) {
+			dev_kfree_skb(titan_ge_eth->rx_skb[curr]);
+			titan_ge_eth->rx_ring_skbs--;
+		}
+	}
+
+	if (titan_ge_eth->rx_ring_skbs != 0)
+		printk(KERN_ERR
+		       "%s: Error in freeing Rx Ring. %d skb's still"
+		       " stuck in RX Ring - ignoring them\n", netdev->name,
+		       titan_ge_eth->rx_ring_skbs);
+
+#ifndef TITAN_RX_RING_IN_SRAM
+	dma_free_coherent(&titan_ge_device[port_num]->dev,
+			  titan_ge_eth->rx_desc_area_size,
+			  (void *) titan_ge_eth->rx_desc_area,
+			  titan_ge_eth->rx_dma);
+#endif
+}
+
+/*
+ * Actually does the stop of the Ethernet device
+ */
+static void titan_ge_eth_stop(struct net_device *netdev)
+{
+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
+
+	netif_stop_queue(netdev);
+
+	titan_ge_port_reset(titan_ge_eth->port_num);
+
+	titan_ge_free_tx_rings(netdev);
+	titan_ge_free_rx_rings(netdev);
+
+	/* Disable the Tx and Rx Interrupts for all channels */
+	TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, 0x0);
+}
+
+/*
+ * Update the MAC address. Note that we have to write the
+ * address in three station registers, 16 bits each. And this
+ * has to be done for TMAC and RMAC
+ */
+static void titan_ge_update_mac_address(struct net_device *netdev)
+{
+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
+	unsigned int port_num = titan_ge_eth->port_num;
+	u8 p_addr[6];
+
+	memcpy(titan_ge_eth->port_mac_addr, netdev->dev_addr, 6);
+	memcpy(p_addr, netdev->dev_addr, 6);
+
+	/* Update the Address Filtering Match tables */
+	titan_ge_update_afx(titan_ge_eth);
+
+	printk("Station MAC : %d %d %d %d %d %d  \n",
+		p_addr[5], p_addr[4], p_addr[3],
+		p_addr[2], p_addr[1], p_addr[0]);
+
+	/* Set the MAC address here for TMAC and RMAC */
+	TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_HI + (port_num << 12)),
+		       ((p_addr[5] << 8) | p_addr[4]));
+	TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_MID + (port_num << 12)),
+		       ((p_addr[3] << 8) | p_addr[2]));
+	TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_LOW + (port_num << 12)),
+		       ((p_addr[1] << 8) | p_addr[0]));
+
+	TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_HI + (port_num << 12)),
+		       ((p_addr[5] << 8) | p_addr[4]));
+	TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_MID + (port_num << 12)),
+		       ((p_addr[3] << 8) | p_addr[2]));
+	TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_LOW + (port_num << 12)),
+		       ((p_addr[1] << 8) | p_addr[0]));
+}
+
+/*
+ * Set the MAC address of the Ethernet device
+ */
+static int titan_ge_set_mac_address(struct net_device *dev, void *addr)
+{
+	titan_ge_port_info *tp = netdev_priv(dev);
+	struct sockaddr *sa = addr;
+
+	memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
+
+	spin_lock_irq(&tp->lock);
+	titan_ge_update_mac_address(dev);
+	spin_unlock_irq(&tp->lock);
+
+	return 0;
+}
+
+/*
+ * Get the Ethernet device stats
+ */
+static struct net_device_stats *titan_ge_get_stats(struct net_device *netdev)
+{
+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
+
+	return &titan_ge_eth->stats;
+}
+
+/*
+ * Initialize the Rx descriptor ring for the Titan Ge
+ */
+static int titan_ge_init_rx_desc_ring(titan_ge_port_info * titan_eth_port,
+				      int rx_desc_num,
+				      int rx_buff_size,
+				      unsigned long rx_desc_base_addr,
+				      unsigned long rx_buff_base_addr,
+				      unsigned long rx_dma)
+{
+	volatile titan_ge_rx_desc *rx_desc;
+	unsigned long buffer_addr;
+	int index;
+	unsigned long titan_ge_rx_desc_bus = rx_dma;
+
+	buffer_addr = rx_buff_base_addr;
+	rx_desc = (titan_ge_rx_desc *) rx_desc_base_addr;
+
+	/* Check alignment */
+	if (rx_buff_base_addr & 0xF)
+		return 0;
+
+	/* Check Rx buffer size */
+	if ((rx_buff_size < 8) || (rx_buff_size > TITAN_GE_MAX_RX_BUFFER))
+		return 0;
+
+	/* 64-bit alignment
+	if ((rx_buff_base_addr + rx_buff_size) & 0x7)
+		return 0; */
+
+	/* Initialize the Rx desc ring */
+	for (index = 0; index < rx_desc_num; index++) {
+		titan_ge_rx_desc_bus += sizeof(titan_ge_rx_desc);
+		rx_desc[index].cmd_sts = 0;
+		rx_desc[index].buffer_addr = buffer_addr;
+		titan_eth_port->rx_skb[index] = NULL;
+		buffer_addr += rx_buff_size;
+	}
+
+	titan_eth_port->rx_curr_desc_q = 0;
+	titan_eth_port->rx_used_desc_q = 0;
+
+	titan_eth_port->rx_desc_area = (titan_ge_rx_desc *) rx_desc_base_addr;
+	titan_eth_port->rx_desc_area_size =
+	    rx_desc_num * sizeof(titan_ge_rx_desc);
+
+	titan_eth_port->rx_dma = rx_dma;
+
+	return TITAN_OK;
+}
+
+/*
+ * Initialize the Tx descriptor ring. Descriptors in the SRAM
+ */
+static int titan_ge_init_tx_desc_ring(titan_ge_port_info * titan_ge_port,
+				      int tx_desc_num,
+				      unsigned long tx_desc_base_addr,
+				      unsigned long tx_dma)
+{
+	titan_ge_tx_desc *tx_desc;
+	int index;
+	unsigned long titan_ge_tx_desc_bus = tx_dma;
+
+	if (tx_desc_base_addr & 0xF)
+		return 0;
+
+	tx_desc = (titan_ge_tx_desc *) tx_desc_base_addr;
+
+	for (index = 0; index < tx_desc_num; index++) {
+		titan_ge_port->tx_dma_array[index] =
+		    (dma_addr_t) titan_ge_tx_desc_bus;
+		titan_ge_tx_desc_bus += sizeof(titan_ge_tx_desc);
+		tx_desc[index].cmd_sts = 0x0000;
+		tx_desc[index].buffer_len = 0;
+		tx_desc[index].buffer_addr = 0x00000000;
+		titan_ge_port->tx_skb[index] = NULL;
+	}
+
+	titan_ge_port->tx_curr_desc_q = 0;
+	titan_ge_port->tx_used_desc_q = 0;
+
+	titan_ge_port->tx_desc_area = (titan_ge_tx_desc *) tx_desc_base_addr;
+	titan_ge_port->tx_desc_area_size =
+	    tx_desc_num * sizeof(titan_ge_tx_desc);
+
+	titan_ge_port->tx_dma = tx_dma;
+	return TITAN_OK;
+}
+
+/*
+ * Initialize the device as an Ethernet device
+ */
+static int __init titan_ge_probe(struct device *device)
+{
+	titan_ge_port_info *titan_ge_eth;
+	struct net_device *netdev;
+	int port = to_platform_device(device)->id;
+	int err;
+
+	netdev = alloc_etherdev(sizeof(titan_ge_port_info));
+	if (!netdev) {
+		err = -ENODEV;
+		goto out;
+	}
+
+	netdev->open = titan_ge_open;
+	netdev->stop = titan_ge_stop;
+	netdev->hard_start_xmit = titan_ge_start_xmit;
+	netdev->get_stats = titan_ge_get_stats;
+	netdev->set_multicast_list = titan_ge_set_multi;
+	netdev->set_mac_address = titan_ge_set_mac_address;
+
+	/* Tx timeout */
+	netdev->tx_timeout = titan_ge_tx_timeout;
+	netdev->watchdog_timeo = 2 * HZ;
+
+	/* Set these to very high values */
+	netdev->poll = titan_ge_poll;
+	netdev->weight = 64;
+
+	netdev->tx_queue_len = TITAN_GE_TX_QUEUE;
+	netif_carrier_off(netdev);
+	netdev->base_addr = 0;
+
+	netdev->change_mtu = titan_ge_change_mtu;
+
+	titan_ge_eth = netdev_priv(netdev);
+	/* Allocation of memory for the driver structures */
+
+	titan_ge_eth->port_num = port;
+
+	/* Configure the Tx timeout handler */
+	INIT_WORK(&titan_ge_eth->tx_timeout_task,
+		  (void (*)(void *)) titan_ge_tx_timeout_task, netdev);
+
+	spin_lock_init(&titan_ge_eth->lock);
+
+	/* set MAC addresses */
+	memcpy(netdev->dev_addr, titan_ge_mac_addr_base, 6);
+	netdev->dev_addr[5] += port;
+
+	err = register_netdev(netdev);
+
+	if (err)
+		goto out_free_netdev;
+
+	printk(KERN_NOTICE
+	       "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
+	       netdev->name, port, netdev->dev_addr[0],
+	       netdev->dev_addr[1], netdev->dev_addr[2],
+	       netdev->dev_addr[3], netdev->dev_addr[4],
+	       netdev->dev_addr[5]);
+
+	printk(KERN_NOTICE "Rx NAPI supported, Tx Coalescing ON \n");
+
+	return 0;
+
+out_free_netdev:
+	kfree(netdev);
+
+out:
+	return err;
+}
+
+static void __devexit titan_device_remove(struct device *device)
+{
+}
+
+/*
+ * Reset the Ethernet port
+ */
+static void titan_ge_port_reset(unsigned int port_num)
+{
+	unsigned int reg_data;
+
+	/* Stop the Tx port activity */
+	reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 +
+				(port_num << 12));
+	reg_data &= ~(0x0001);
+	TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
+			(port_num << 12)), reg_data);
+
+	/* Stop the Rx port activity */
+	reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 +
+				(port_num << 12));
+	reg_data &= ~(0x0001);
+	TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 +
+			(port_num << 12)), reg_data);
+
+	return;
+}
+
+/*
+ * Return the Tx desc after use by the XDMA
+ */
+static int titan_ge_return_tx_desc(titan_ge_port_info * titan_ge_eth, int port)
+{
+	int tx_desc_used;
+	struct sk_buff *skb;
+
+	tx_desc_used = titan_ge_eth->tx_used_desc_q;
+
+	/* return right away */
+	if (tx_desc_used == titan_ge_eth->tx_curr_desc_q)
+		return TITAN_ERROR;
+
+	/* Now the critical stuff */
+	skb = titan_ge_eth->tx_skb[tx_desc_used];
+
+	dev_kfree_skb_any(skb);
+
+	titan_ge_eth->tx_skb[tx_desc_used] = NULL;
+	titan_ge_eth->tx_used_desc_q =
+	    (tx_desc_used + 1) % TITAN_GE_TX_QUEUE;
+
+	return 0;
+}
+
+/*
+ * Coalescing for the Tx path
+ */
+static unsigned long titan_ge_tx_coal(unsigned long delay, int port)
+{
+	unsigned long rx_delay;
+
+	rx_delay = TITAN_GE_READ(TITAN_GE_INT_COALESCING);
+	delay = (delay << 16) | rx_delay;
+
+	TITAN_GE_WRITE(TITAN_GE_INT_COALESCING, delay);
+	TITAN_GE_WRITE(0x5038, delay);
+
+	return delay;
+}
+
+static struct device_driver titan_soc_driver = {
+	.name   = titan_string,
+	.bus    = &platform_bus_type,
+	.probe  = titan_ge_probe,
+	.remove = __devexit_p(titan_device_remove),
+};
+
+static void titan_platform_release (struct device *device)
+{
+	struct platform_device *pldev;
+
+	/* free device */
+	pldev = to_platform_device (device);
+	kfree (pldev);
+}
+
+/*
+ * Register the Titan GE with the kernel
+ */
+static int __init titan_ge_init_module(void)
+{
+	struct platform_device *pldev;
+	unsigned int version, device;
+	int i;
+
+	printk(KERN_NOTICE
+	       "PMC-Sierra TITAN 10/100/1000 Ethernet Driver \n");
+
+	titan_ge_base = (unsigned long) ioremap(TITAN_GE_BASE, TITAN_GE_SIZE);
+	if (!titan_ge_base) {
+		printk("Mapping Titan GE failed\n");
+		goto out;
+	}
+
+	device = TITAN_GE_READ(TITAN_GE_DEVICE_ID);
+	version = (device & 0x000f0000) >> 16;
+	device &= 0x0000ffff;
+
+	printk(KERN_NOTICE "Device Id : %x,  Version : %x \n", device, version);
+
+#ifdef TITAN_RX_RING_IN_SRAM
+	titan_ge_sram = (unsigned long) ioremap(TITAN_SRAM_BASE,
+						TITAN_SRAM_SIZE);
+	if (!titan_ge_sram) {
+		printk("Mapping Titan SRAM failed\n");
+		goto out_unmap_ge;
+	}
+#endif
+
+	if (driver_register(&titan_soc_driver)) {
+		printk(KERN_ERR "Driver registration failed\n");
+		goto out_unmap_sram;
+	}
+
+	for (i = 0; i < 3; i++) {
+		titan_ge_device[i] = NULL;
+
+		if (!(pldev = kmalloc (sizeof (*pldev), GFP_KERNEL)))
+			continue;
+
+		memset (pldev, 0, sizeof (*pldev));
+		pldev->name		= titan_string;
+		pldev->id		= i;
+		pldev->dev.release	= titan_platform_release;
+		titan_ge_device[i]	= pldev;
+
+		if (platform_device_register (pldev)) {
+			kfree (pldev);
+			titan_ge_device[i] = NULL;
+			continue;
+		}
+
+		if (!pldev->dev.driver) {
+			/*
+			 * The driver was not bound to this device, there was
+			 * no hardware at this address. Unregister it, as the
+			 * release fuction will take care of freeing the
+			 * allocated structure
+			 */
+			titan_ge_device[i] = NULL;
+			platform_device_unregister (pldev);
+		}
+	}
+
+	return 0;
+
+out_unmap_sram:
+	iounmap((void *)titan_ge_sram);
+
+out_unmap_ge:
+	iounmap((void *)titan_ge_base);
+
+out:
+	return -ENOMEM;
+}
+
+/*
+ * Unregister the Titan GE from the kernel
+ */
+static void __exit titan_ge_cleanup_module(void)
+{
+	int i;
+
+	driver_unregister(&titan_soc_driver);
+
+	for (i = 0; i < 3; i++) {
+		if (titan_ge_device[i]) {
+			platform_device_unregister (titan_ge_device[i]);
+			titan_ge_device[i] = NULL;
+		}
+	}
+
+	iounmap((void *)titan_ge_sram);
+	iounmap((void *)titan_ge_base);
+}
+
+MODULE_AUTHOR("Manish Lachwani <lachwani@pmc-sierra.com>");
+MODULE_DESCRIPTION("Titan GE Ethernet driver");
+MODULE_LICENSE("GPL");
+
+module_init(titan_ge_init_module);
+module_exit(titan_ge_cleanup_module);
diff --git a/drivers/net/ethernet/pmc-sierra/titan_ge.h b/drivers/net/ethernet/pmc-sierra/titan_ge.h
new file mode 100644
index 0000000..3719f78
--- /dev/null
+++ b/drivers/net/ethernet/pmc-sierra/titan_ge.h
@@ -0,0 +1,415 @@
+#ifndef _TITAN_GE_H_
+#define _TITAN_GE_H_
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <asm/byteorder.h>
+
+/*
+ * These functions should be later moved to a more generic location since there
+ * will be others accessing it also
+ */
+
+/*
+ * This is the way it works: LKB5 Base is at 0x0128. TITAN_BASE is defined in
+ * include/asm/titan_dep.h. TITAN_GE_BASE is the value in the TITAN_GE_LKB5
+ * register.
+ */
+
+#define	TITAN_GE_BASE	0xfe000000UL
+#define	TITAN_GE_SIZE	0x10000UL
+
+extern unsigned long titan_ge_base;
+
+#define	TITAN_GE_WRITE(offset, data) \
+		*(volatile u32 *)(titan_ge_base + (offset)) = (data)
+
+#define TITAN_GE_READ(offset) *(volatile u32 *)(titan_ge_base + (offset))
+
+#ifndef msec_delay
+#define msec_delay(x)   do { if(in_interrupt()) { \
+				/* Don't mdelay in interrupt context! */ \
+				BUG(); \
+			} else { \
+				set_current_state(TASK_UNINTERRUPTIBLE); \
+				schedule_timeout((x * HZ)/1000); \
+			} } while(0)
+#endif
+
+#define TITAN_GE_PORT_0
+
+#define	TITAN_SRAM_BASE		((OCD_READ(RM9000x2_OCD_LKB13) & ~1) << 4)
+#define	TITAN_SRAM_SIZE		0x2000UL
+
+/*
+ * We may need these constants
+ */
+#define TITAN_BIT0    0x00000001
+#define TITAN_BIT1    0x00000002
+#define TITAN_BIT2    0x00000004
+#define TITAN_BIT3    0x00000008
+#define TITAN_BIT4    0x00000010
+#define TITAN_BIT5    0x00000020
+#define TITAN_BIT6    0x00000040
+#define TITAN_BIT7    0x00000080
+#define TITAN_BIT8    0x00000100
+#define TITAN_BIT9    0x00000200
+#define TITAN_BIT10   0x00000400
+#define TITAN_BIT11   0x00000800
+#define TITAN_BIT12   0x00001000
+#define TITAN_BIT13   0x00002000
+#define TITAN_BIT14   0x00004000
+#define TITAN_BIT15   0x00008000
+#define TITAN_BIT16   0x00010000
+#define TITAN_BIT17   0x00020000
+#define TITAN_BIT18   0x00040000
+#define TITAN_BIT19   0x00080000
+#define TITAN_BIT20   0x00100000
+#define TITAN_BIT21   0x00200000
+#define TITAN_BIT22   0x00400000
+#define TITAN_BIT23   0x00800000
+#define TITAN_BIT24   0x01000000
+#define TITAN_BIT25   0x02000000
+#define TITAN_BIT26   0x04000000
+#define TITAN_BIT27   0x08000000
+#define TITAN_BIT28   0x10000000
+#define TITAN_BIT29   0x20000000
+#define TITAN_BIT30   0x40000000
+#define TITAN_BIT31   0x80000000
+
+/* Flow Control */
+#define	TITAN_GE_FC_NONE	0x0
+#define	TITAN_GE_FC_FULL	0x1
+#define	TITAN_GE_FC_TX_PAUSE	0x2
+#define	TITAN_GE_FC_RX_PAUSE	0x3
+
+/* Duplex Settings */
+#define	TITAN_GE_FULL_DUPLEX	0x1
+#define	TITAN_GE_HALF_DUPLEX	0x2
+
+/* Speed settings */
+#define	TITAN_GE_SPEED_1000	0x1
+#define	TITAN_GE_SPEED_100	0x2
+#define	TITAN_GE_SPEED_10	0x3
+
+/* Debugging info only */
+#undef TITAN_DEBUG
+
+/* Keep the rings in the Titan's SSRAM */
+#define TITAN_RX_RING_IN_SRAM
+
+#ifdef CONFIG_64BIT
+#define	TITAN_GE_IE_MASK	0xfffffffffb001b64
+#define	TITAN_GE_IE_STATUS	0xfffffffffb001b60
+#else
+#define	TITAN_GE_IE_MASK	0xfb001b64
+#define	TITAN_GE_IE_STATUS	0xfb001b60
+#endif
+
+/* Support for Jumbo Frames */
+#undef TITAN_GE_JUMBO_FRAMES
+
+/* Rx buffer size */
+#ifdef TITAN_GE_JUMBO_FRAMES
+#define	TITAN_GE_JUMBO_BUFSIZE	9080
+#else
+#define	TITAN_GE_STD_BUFSIZE	1580
+#endif
+
+/*
+ * Tx and Rx Interrupt Coalescing parameter. These values are
+ * for 1 Ghz processor. Rx coalescing can be taken care of
+ * by NAPI. NAPI is adaptive and hence useful. Tx coalescing
+ * is not adaptive. Hence, these values need to be adjusted
+ * based on load, CPU speed etc.
+ */
+#define	TITAN_GE_RX_COAL	150
+#define	TITAN_GE_TX_COAL	300
+
+#if defined(__BIG_ENDIAN)
+
+/* Define the Rx descriptor */
+typedef struct eth_rx_desc {
+	u32     reserved;	/* Unused 		*/
+	u32     buffer_addr;	/* CPU buffer address 	*/
+	u32	cmd_sts;	/* Command and Status	*/
+	u32	buffer;		/* XDMA buffer address	*/
+} titan_ge_rx_desc;
+
+/* Define the Tx descriptor */
+typedef struct eth_tx_desc {
+	u16     cmd_sts;	/* Command, Status and Buffer count */
+	u16	buffer_len;	/* Length of the buffer	*/
+	u32     buffer_addr;	/* Physical address of the buffer */
+} titan_ge_tx_desc;
+
+#elif defined(__LITTLE_ENDIAN)
+
+/* Define the Rx descriptor */
+typedef struct eth_rx_desc {
+	u32	buffer_addr;	/* CPU buffer address   */
+	u32	reserved;	/* Unused               */
+	u32	buffer;		/* XDMA buffer address  */
+	u32	cmd_sts;	/* Command and Status   */
+} titan_ge_rx_desc;
+
+/* Define the Tx descriptor */
+typedef struct eth_tx_desc {
+	u32     buffer_addr;	/* Physical address of the buffer */
+	u16     buffer_len;     /* Length of the buffer */
+	u16     cmd_sts;        /* Command, Status and Buffer count */
+} titan_ge_tx_desc;
+#endif
+
+/* Default Tx Queue Size */
+#define	TITAN_GE_TX_QUEUE	128
+#define TITAN_TX_RING_BYTES	(TITAN_GE_TX_QUEUE * sizeof(struct eth_tx_desc))
+
+/* Default Rx Queue Size */
+#define	TITAN_GE_RX_QUEUE	64
+#define TITAN_RX_RING_BYTES	(TITAN_GE_RX_QUEUE * sizeof(struct eth_rx_desc))
+
+/* Packet Structure */
+typedef struct _pkt_info {
+	unsigned int           len;
+	unsigned int            cmd_sts;
+	unsigned int            buffer;
+	struct sk_buff          *skb;
+	unsigned int		checksum;
+} titan_ge_packet;
+
+
+#define	PHYS_CNT	3
+
+/* Titan Port specific data structure */
+typedef struct _eth_port_ctrl {
+	unsigned int		port_num;
+	u8			port_mac_addr[6];
+
+	/* Rx descriptor pointers */
+	int 			rx_curr_desc_q, rx_used_desc_q;
+
+	/* Tx descriptor pointers */
+	int 			tx_curr_desc_q, tx_used_desc_q;
+
+	/* Rx descriptor area */
+	volatile titan_ge_rx_desc	*rx_desc_area;
+	unsigned int			rx_desc_area_size;
+	struct sk_buff*			rx_skb[TITAN_GE_RX_QUEUE];
+
+	/* Tx Descriptor area */
+	volatile titan_ge_tx_desc	*tx_desc_area;
+	unsigned int                    tx_desc_area_size;
+	struct sk_buff*                 tx_skb[TITAN_GE_TX_QUEUE];
+
+	/* Timeout task */
+	struct work_struct		tx_timeout_task;
+
+	/* DMA structures and handles */
+	dma_addr_t			tx_dma;
+	dma_addr_t			rx_dma;
+	dma_addr_t			tx_dma_array[TITAN_GE_TX_QUEUE];
+
+	/* Device lock */
+	spinlock_t			lock;
+
+	unsigned int			tx_ring_skbs;
+	unsigned int			rx_ring_size;
+	unsigned int			tx_ring_size;
+	unsigned int			rx_ring_skbs;
+
+	struct net_device_stats		stats;
+
+	/* Tx and Rx coalescing */
+	unsigned long			rx_int_coal;
+	unsigned long			tx_int_coal;
+
+	/* Threshold for replenishing the Rx and Tx rings */
+	unsigned int			tx_threshold;
+	unsigned int			rx_threshold;
+
+	/* NAPI work limit */
+	unsigned int			rx_work_limit;
+} titan_ge_port_info;
+
+/* Titan specific constants */
+#define	TITAN_ETH_PORT_IRQ		3
+
+/* Max Rx buffer */
+#define	TITAN_GE_MAX_RX_BUFFER		65536
+
+/* Tx and Rx Error */
+#define	TITAN_GE_ERROR
+
+/* Rx Descriptor Command and Status */
+
+#define	TITAN_GE_RX_CRC_ERROR		TITAN_BIT27	/* crc error */
+#define	TITAN_GE_RX_OVERFLOW_ERROR	TITAN_BIT15	/* overflow */
+#define TITAN_GE_RX_BUFFER_OWNED	TITAN_BIT21	/* buffer ownership */
+#define	TITAN_GE_RX_STP			TITAN_BIT31	/* start of packet */
+#define	TITAN_GE_RX_BAM			TITAN_BIT30	/* broadcast address match */
+#define TITAN_GE_RX_PAM			TITAN_BIT28	/* physical address match */
+#define TITAN_GE_RX_LAFM		TITAN_BIT29	/* logical address filter match */
+#define TITAN_GE_RX_VLAN		TITAN_BIT26	/* virtual lans */
+#define TITAN_GE_RX_PERR		TITAN_BIT19	/* packet error */
+#define TITAN_GE_RX_TRUNC		TITAN_BIT20	/* packet size greater than 32 buffers */
+
+/* Tx Descriptor Command */
+#define	TITAN_GE_TX_BUFFER_OWNED	TITAN_BIT5	/* buffer ownership */
+#define	TITAN_GE_TX_ENABLE_INTERRUPT	TITAN_BIT15	/* Interrupt Enable */
+
+/* Return Status */
+#define	TITAN_OK	0x1	/* Good Status */
+#define	TITAN_ERROR	0x2	/* Error Status */
+
+/* MIB specific register offset */
+#define TITAN_GE_MSTATX_STATS_BASE_LOW       0x0800  /* MSTATX COUNTL[15:0] */
+#define TITAN_GE_MSTATX_STATS_BASE_MID       0x0804  /* MSTATX COUNTM[15:0] */
+#define TITAN_GE_MSTATX_STATS_BASE_HI        0x0808  /* MSTATX COUNTH[7:0] */
+#define TITAN_GE_MSTATX_CONTROL              0x0828  /* MSTATX Control */
+#define TITAN_GE_MSTATX_VARIABLE_SELECT      0x082C  /* MSTATX Variable Select */
+
+/* MIB counter offsets, add to the TITAN_GE_MSTATX_STATS_BASE_XXX */
+#define TITAN_GE_MSTATX_RXFRAMESOK                   0x0040
+#define TITAN_GE_MSTATX_RXOCTETSOK                   0x0050
+#define TITAN_GE_MSTATX_RXFRAMES                     0x0060
+#define TITAN_GE_MSTATX_RXOCTETS                     0x0070
+#define TITAN_GE_MSTATX_RXUNICASTFRAMESOK            0x0080
+#define TITAN_GE_MSTATX_RXBROADCASTFRAMESOK          0x0090
+#define TITAN_GE_MSTATX_RXMULTICASTFRAMESOK          0x00A0
+#define TITAN_GE_MSTATX_RXTAGGEDFRAMESOK             0x00B0
+#define TITAN_GE_MSTATX_RXMACPAUSECONTROLFRAMESOK    0x00C0
+#define TITAN_GE_MSTATX_RXMACCONTROLFRAMESOK         0x00D0
+#define TITAN_GE_MSTATX_RXFCSERROR                   0x00E0
+#define TITAN_GE_MSTATX_RXALIGNMENTERROR             0x00F0
+#define TITAN_GE_MSTATX_RXSYMBOLERROR                0x0100
+#define TITAN_GE_MSTATX_RXLAYER1ERROR                0x0110
+#define TITAN_GE_MSTATX_RXINRANGELENGTHERROR         0x0120
+#define TITAN_GE_MSTATX_RXLONGLENGTHERROR            0x0130
+#define TITAN_GE_MSTATX_RXLONGLENGTHCRCERROR         0x0140
+#define TITAN_GE_MSTATX_RXSHORTLENGTHERROR           0x0150
+#define TITAN_GE_MSTATX_RXSHORTLLENGTHCRCERROR       0x0160
+#define TITAN_GE_MSTATX_RXFRAMES64OCTETS             0x0170
+#define TITAN_GE_MSTATX_RXFRAMES65TO127OCTETS        0x0180
+#define TITAN_GE_MSTATX_RXFRAMES128TO255OCTETS       0x0190
+#define TITAN_GE_MSTATX_RXFRAMES256TO511OCTETS       0x01A0
+#define TITAN_GE_MSTATX_RXFRAMES512TO1023OCTETS      0x01B0
+#define TITAN_GE_MSTATX_RXFRAMES1024TO1518OCTETS     0x01C0
+#define TITAN_GE_MSTATX_RXFRAMES1519TOMAXSIZE        0x01D0
+#define TITAN_GE_MSTATX_RXSTATIONADDRESSFILTERED     0x01E0
+#define TITAN_GE_MSTATX_RXVARIABLE                   0x01F0
+#define TITAN_GE_MSTATX_GENERICADDRESSFILTERED       0x0200
+#define TITAN_GE_MSTATX_UNICASTFILTERED              0x0210
+#define TITAN_GE_MSTATX_MULTICASTFILTERED            0x0220
+#define TITAN_GE_MSTATX_BROADCASTFILTERED            0x0230
+#define TITAN_GE_MSTATX_HASHFILTERED                 0x0240
+#define TITAN_GE_MSTATX_TXFRAMESOK                   0x0250
+#define TITAN_GE_MSTATX_TXOCTETSOK                   0x0260
+#define TITAN_GE_MSTATX_TXOCTETS                     0x0270
+#define TITAN_GE_MSTATX_TXTAGGEDFRAMESOK             0x0280
+#define TITAN_GE_MSTATX_TXMACPAUSECONTROLFRAMESOK    0x0290
+#define TITAN_GE_MSTATX_TXFCSERROR                   0x02A0
+#define TITAN_GE_MSTATX_TXSHORTLENGTHERROR           0x02B0
+#define TITAN_GE_MSTATX_TXLONGLENGTHERROR            0x02C0
+#define TITAN_GE_MSTATX_TXSYSTEMERROR                0x02D0
+#define TITAN_GE_MSTATX_TXMACERROR                   0x02E0
+#define TITAN_GE_MSTATX_TXCARRIERSENSEERROR          0x02F0
+#define TITAN_GE_MSTATX_TXSQETESTERROR               0x0300
+#define TITAN_GE_MSTATX_TXUNICASTFRAMESOK            0x0310
+#define TITAN_GE_MSTATX_TXBROADCASTFRAMESOK          0x0320
+#define TITAN_GE_MSTATX_TXMULTICASTFRAMESOK          0x0330
+#define TITAN_GE_MSTATX_TXUNICASTFRAMESATTEMPTED     0x0340
+#define TITAN_GE_MSTATX_TXBROADCASTFRAMESATTEMPTED   0x0350
+#define TITAN_GE_MSTATX_TXMULTICASTFRAMESATTEMPTED   0x0360
+#define TITAN_GE_MSTATX_TXFRAMES64OCTETS             0x0370
+#define TITAN_GE_MSTATX_TXFRAMES65TO127OCTETS        0x0380
+#define TITAN_GE_MSTATX_TXFRAMES128TO255OCTETS       0x0390
+#define TITAN_GE_MSTATX_TXFRAMES256TO511OCTETS       0x03A0
+#define TITAN_GE_MSTATX_TXFRAMES512TO1023OCTETS      0x03B0
+#define TITAN_GE_MSTATX_TXFRAMES1024TO1518OCTETS     0x03C0
+#define TITAN_GE_MSTATX_TXFRAMES1519TOMAXSIZE        0x03D0
+#define TITAN_GE_MSTATX_TXVARIABLE                   0x03E0
+#define TITAN_GE_MSTATX_RXSYSTEMERROR                0x03F0
+#define TITAN_GE_MSTATX_SINGLECOLLISION              0x0400
+#define TITAN_GE_MSTATX_MULTIPLECOLLISION            0x0410
+#define TITAN_GE_MSTATX_DEFERREDXMISSIONS            0x0420
+#define TITAN_GE_MSTATX_LATECOLLISIONS               0x0430
+#define TITAN_GE_MSTATX_ABORTEDDUETOXSCOLLS          0x0440
+
+/* Interrupt specific defines */
+#define TITAN_GE_DEVICE_ID         0x0000  /* Device ID */
+#define TITAN_GE_RESET             0x0004  /* Reset reg */
+#define TITAN_GE_TSB_CTRL_0        0x000C  /* TSB Control reg 0 */
+#define TITAN_GE_TSB_CTRL_1        0x0010  /* TSB Control reg 1 */
+#define TITAN_GE_INTR_GRP0_STATUS  0x0040  /* General Interrupt Group 0 Status */
+#define TITAN_GE_INTR_XDMA_CORE_A  0x0048  /* XDMA Channel Interrupt Status, Core A*/
+#define TITAN_GE_INTR_XDMA_CORE_B  0x004C  /* XDMA Channel Interrupt Status, Core B*/
+#define	TITAN_GE_INTR_XDMA_IE	   0x0058  /* XDMA Channel Interrupt Enable */
+#define TITAN_GE_SDQPF_ECC_INTR    0x480C  /* SDQPF ECC Interrupt Status */
+#define TITAN_GE_SDQPF_RXFIFO_CTL  0x4828  /* SDQPF RxFifo Control and Interrupt Enb*/
+#define TITAN_GE_SDQPF_RXFIFO_INTR 0x482C  /* SDQPF RxFifo Interrupt Status */
+#define TITAN_GE_SDQPF_TXFIFO_CTL  0x4928  /* SDQPF TxFifo Control and Interrupt Enb*/
+#define TITAN_GE_SDQPF_TXFIFO_INTR 0x492C  /* SDQPF TxFifo Interrupt Status */
+#define	TITAN_GE_SDQPF_RXFIFO_0	   0x4840  /* SDQPF RxFIFO Enable */
+#define	TITAN_GE_SDQPF_TXFIFO_0	   0x4940  /* SDQPF TxFIFO Enable */
+#define TITAN_GE_XDMA_CONFIG       0x5000  /* XDMA Global Configuration */
+#define TITAN_GE_XDMA_INTR_SUMMARY 0x5010  /* XDMA Interrupt Summary */
+#define TITAN_GE_XDMA_BUFADDRPRE   0x5018  /* XDMA Buffer Address Prefix */
+#define TITAN_GE_XDMA_DESCADDRPRE  0x501C  /* XDMA Descriptor Address Prefix */
+#define TITAN_GE_XDMA_PORTWEIGHT   0x502C  /* XDMA Port Weight Configuration */
+
+/* Rx MAC defines */
+#define TITAN_GE_RMAC_CONFIG_1               0x1200  /* RMAC Configuration 1 */
+#define TITAN_GE_RMAC_CONFIG_2               0x1204  /* RMAC Configuration 2 */
+#define TITAN_GE_RMAC_MAX_FRAME_LEN          0x1208  /* RMAC Max Frame Length */
+#define TITAN_GE_RMAC_STATION_HI             0x120C  /* Rx Station Address High */
+#define TITAN_GE_RMAC_STATION_MID            0x1210  /* Rx Station Address Middle */
+#define TITAN_GE_RMAC_STATION_LOW            0x1214  /* Rx Station Address Low */
+#define TITAN_GE_RMAC_LINK_CONFIG            0x1218  /* RMAC Link Configuration */
+
+/* Tx MAC defines */
+#define TITAN_GE_TMAC_CONFIG_1               0x1240  /* TMAC Configuration 1 */
+#define TITAN_GE_TMAC_CONFIG_2               0x1244  /* TMAC Configuration 2 */
+#define TITAN_GE_TMAC_IPG                    0x1248  /* TMAC Inter-Packet Gap */
+#define TITAN_GE_TMAC_STATION_HI             0x124C  /* Tx Station Address High */
+#define TITAN_GE_TMAC_STATION_MID            0x1250  /* Tx Station Address Middle */
+#define TITAN_GE_TMAC_STATION_LOW            0x1254  /* Tx Station Address Low */
+#define TITAN_GE_TMAC_MAX_FRAME_LEN          0x1258  /* TMAC Max Frame Length */
+#define TITAN_GE_TMAC_MIN_FRAME_LEN          0x125C  /* TMAC Min Frame Length */
+#define TITAN_GE_TMAC_PAUSE_FRAME_TIME       0x1260  /* TMAC Pause Frame Time */
+#define TITAN_GE_TMAC_PAUSE_FRAME_INTERVAL   0x1264  /* TMAC Pause Frame Interval */
+
+/* GMII register */
+#define TITAN_GE_GMII_INTERRUPT_STATUS       0x1348  /* GMII Interrupt Status */
+#define TITAN_GE_GMII_CONFIG_GENERAL         0x134C  /* GMII Configuration General */
+#define TITAN_GE_GMII_CONFIG_MODE            0x1350  /* GMII Configuration Mode */
+
+/* Tx and Rx XDMA defines */
+#define	TITAN_GE_INT_COALESCING		     0x5030 /* Interrupt Coalescing */
+#define	TITAN_GE_CHANNEL0_CONFIG	     0x5040 /* Channel 0 XDMA config */
+#define	TITAN_GE_CHANNEL0_INTERRUPT	     0x504c /* Channel 0 Interrupt Status */
+#define	TITAN_GE_GDI_INTERRUPT_ENABLE        0x5050 /* IE for the GDI Errors */
+#define	TITAN_GE_CHANNEL0_PACKET	     0x5060 /* Channel 0 Packet count */
+#define	TITAN_GE_CHANNEL0_BYTE		     0x5064 /* Channel 0 Byte count */
+#define	TITAN_GE_CHANNEL0_TX_DESC	     0x5054 /* Channel 0 Tx first desc */
+#define	TITAN_GE_CHANNEL0_RX_DESC	     0x5058 /* Channel 0 Rx first desc */
+
+/* AFX (Address Filter Exact) register offsets for Slice 0 */
+#define TITAN_GE_AFX_EXACT_MATCH_LOW         0x1100  /* AFX Exact Match Address Low*/
+#define TITAN_GE_AFX_EXACT_MATCH_MID         0x1104  /* AFX Exact Match Address Mid*/
+#define TITAN_GE_AFX_EXACT_MATCH_HIGH        0x1108  /* AFX Exact Match Address Hi */
+#define TITAN_GE_AFX_EXACT_MATCH_VID         0x110C  /* AFX Exact Match VID */
+#define TITAN_GE_AFX_MULTICAST_HASH_LOW      0x1110  /* AFX Multicast HASH Low */
+#define TITAN_GE_AFX_MULTICAST_HASH_MIDLOW   0x1114  /* AFX Multicast HASH MidLow */
+#define TITAN_GE_AFX_MULTICAST_HASH_MIDHI    0x1118  /* AFX Multicast HASH MidHi */
+#define TITAN_GE_AFX_MULTICAST_HASH_HI       0x111C  /* AFX Multicast HASH Hi */
+#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_0     0x1120  /* AFX Address Filter Ctrl 0 */
+#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_1     0x1124  /* AFX Address Filter Ctrl 1 */
+#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_2     0x1128  /* AFX Address Filter Ctrl 2 */
+
+/* Traffic Groomer block */
+#define        TITAN_GE_TRTG_CONFIG	     0x1000  /* TRTG Config */
+
+#endif 				/* _TITAN_GE_H_ */
+
diff --git a/drivers/net/ethernet/pmc-sierra/titan_mdio.c b/drivers/net/ethernet/pmc-sierra/titan_mdio.c
new file mode 100644
index 0000000..8a8785b
--- /dev/null
+++ b/drivers/net/ethernet/pmc-sierra/titan_mdio.c
@@ -0,0 +1,217 @@
+/*
+ * drivers/net/titan_mdio.c - Driver for Titan ethernet ports
+ *
+ * Copyright (C) 2003 PMC-Sierra Inc.
+ * Author : Manish Lachwani (lachwani@pmc-sierra.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ * Management Data IO (MDIO) driver for the Titan GMII. Interacts with the Marvel PHY
+ * on the Titan. No support for the TBI as yet.
+ *
+ */
+
+#include	"titan_mdio.h"
+
+#define MDIO_DEBUG
+
+/*
+ * Local constants
+ */
+#define MAX_CLKA            1023
+#define MAX_PHY_DEV         31
+#define MAX_PHY_REG         31
+#define WRITEADDRS_OPCODE   0x0
+#define	READ_OPCODE	    0x2
+#define WRITE_OPCODE        0x1
+#define MAX_MDIO_POLL       100
+
+/*
+ * Titan MDIO and SCMB registers
+ */
+#define TITAN_GE_SCMB_CONTROL                0x01c0  /* SCMB Control */
+#define TITAN_GE_SCMB_CLKA	             0x01c4  /* SCMB Clock A */
+#define TITAN_GE_MDIO_COMMAND                0x01d0  /* MDIO Command */
+#define TITAN_GE_MDIO_DEVICE_PORT_ADDRESS    0x01d4  /* MDIO Device and Port addrs */
+#define TITAN_GE_MDIO_DATA                   0x01d8  /* MDIO Data */
+#define TITAN_GE_MDIO_INTERRUPTS             0x01dC  /* MDIO Interrupts */
+
+/*
+ * Function to poll the MDIO
+ */
+static int titan_ge_mdio_poll(void)
+{
+	int	i, val;
+
+	for (i = 0; i < MAX_MDIO_POLL; i++) {
+		val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
+
+		if (!(val & 0x8000))
+			return TITAN_GE_MDIO_GOOD;
+	}
+
+	return TITAN_GE_MDIO_ERROR;
+}
+
+
+/*
+ * Initialize and configure the MDIO
+ */
+int titan_ge_mdio_setup(titan_ge_mdio_config *titan_mdio)
+{
+	unsigned long	val;
+
+	/* Reset the SCMB and program into MDIO mode*/
+	TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CONTROL, 0x9000);
+	TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CONTROL, 0x1000);
+
+	/* CLK A */
+	val = TITAN_GE_MDIO_READ(TITAN_GE_SCMB_CLKA);
+	val = ( (val & ~(0x03ff)) | (titan_mdio->clka & 0x03ff));
+	TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CLKA, val);
+
+	/* Preamble Suppresion */
+	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
+	val = ( (val & ~(0x0001)) | (titan_mdio->mdio_spre & 0x0001));
+	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
+
+	/* MDIO mode */
+	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
+	val = ( (val & ~(0x4000)) | (titan_mdio->mdio_mode & 0x4000));
+	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
+
+	return TITAN_GE_MDIO_GOOD;
+}
+
+/*
+ * Set the PHY address in indirect mode
+ */
+int titan_ge_mdio_inaddrs(int dev_addr, int reg_addr)
+{
+	volatile unsigned long	val;
+
+	/* Setup the PHY device */
+	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
+	val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00));
+	val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f));
+	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
+
+	/* Write the new address */
+	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
+	val = ( (val & ~(0x0300)) | ( (WRITEADDRS_OPCODE << 8) & 0x0300));
+	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
+
+	return TITAN_GE_MDIO_GOOD;
+}
+
+/*
+ * Read the MDIO register. This is what the individual parametes mean:
+ *
+ * dev_addr : PHY ID
+ * reg_addr : register offset
+ *
+ * See the spec for the Titan MAC. We operate in the Direct Mode.
+ */
+
+#define MAX_RETRIES	2
+
+int titan_ge_mdio_read(int dev_addr, int reg_addr, unsigned int *pdata)
+{
+	volatile unsigned long	val;
+	int retries = 0;
+
+	/* Setup the PHY device */
+
+again:
+	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
+	val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00));
+	val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f));
+	val |= 0x4000;
+	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
+
+	udelay(30);
+
+	/* Issue the read command */
+	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
+	val = ( (val & ~(0x0300)) | ( (READ_OPCODE << 8) & 0x0300));
+	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
+
+	udelay(30);
+
+	if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD)
+		return TITAN_GE_MDIO_ERROR;
+
+	*pdata = (unsigned int)TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DATA);
+	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_INTERRUPTS);
+
+	udelay(30);
+
+	if (val & 0x2) {
+		if (retries == MAX_RETRIES)
+			return TITAN_GE_MDIO_ERROR;
+		else {
+			retries++;
+			goto again;
+		}
+	}
+
+	return TITAN_GE_MDIO_GOOD;
+}
+
+/*
+ * Write to the MDIO register
+ *
+ * dev_addr : PHY ID
+ * reg_addr : register that needs to be written to
+ *
+ */
+int titan_ge_mdio_write(int dev_addr, int reg_addr, unsigned int data)
+{
+	volatile unsigned long	val;
+
+	if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD)
+		return TITAN_GE_MDIO_ERROR;
+
+	/* Setup the PHY device */
+	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
+	val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00));
+	val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f));
+	val |= 0x4000;
+	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
+
+	udelay(30);
+
+	/* Setup the data to write */
+	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DATA, data);
+
+	udelay(30);
+
+	/* Issue the write command */
+	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
+	val = ( (val & ~(0x0300)) | ( (WRITE_OPCODE << 8) & 0x0300));
+	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
+
+	udelay(30);
+
+	if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD)
+		return TITAN_GE_MDIO_ERROR;
+
+	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_INTERRUPTS);
+	if (val & 0x2)
+		return TITAN_GE_MDIO_ERROR;
+
+	return TITAN_GE_MDIO_GOOD;
+}
+
diff --git a/drivers/net/ethernet/pmc-sierra/titan_mdio.h b/drivers/net/ethernet/pmc-sierra/titan_mdio.h
new file mode 100644
index 0000000..5d23344
--- /dev/null
+++ b/drivers/net/ethernet/pmc-sierra/titan_mdio.h
@@ -0,0 +1,56 @@
+/*
+ * MDIO used to interact with the PHY when using GMII/MII
+ */
+#ifndef _TITAN_MDIO_H
+#define _TITAN_MDIO_H
+
+#include <linux/netdevice.h>
+#include <linux/workqueue.h>
+#include <linux/delay.h>
+#include "titan_ge.h"
+
+
+#define	TITAN_GE_MDIO_ERROR	(-9000)
+#define	TITAN_GE_MDIO_GOOD	0
+
+#define	TITAN_GE_MDIO_BASE		titan_ge_base
+
+#define	TITAN_GE_MDIO_READ(offset)	\
+	*(volatile u32 *)(titan_ge_base + (offset))
+
+#define	TITAN_GE_MDIO_WRITE(offset, data)	\
+	*(volatile u32 *)(titan_ge_base + (offset)) = (data)
+
+
+/* GMII specific registers */
+#define	TITAN_GE_MARVEL_PHY_ID		0x00
+#define	TITAN_PHY_AUTONEG_ADV		0x04
+#define	TITAN_PHY_LP_ABILITY		0x05
+#define	TITAN_GE_MDIO_MII_CTRL		0x09
+#define	TITAN_GE_MDIO_MII_EXTENDED	0x0f
+#define	TITAN_GE_MDIO_PHY_CTRL		0x10
+#define	TITAN_GE_MDIO_PHY_STATUS	0x11
+#define	TITAN_GE_MDIO_PHY_IE		0x12
+#define	TITAN_GE_MDIO_PHY_IS		0x13
+#define	TITAN_GE_MDIO_PHY_LED		0x18
+#define	TITAN_GE_MDIO_PHY_LED_OVER	0x19
+#define	PHY_ANEG_TIME_WAIT		45	/* 45 seconds wait time */
+
+/*
+ * MDIO Config Structure
+ */
+typedef struct {
+	unsigned int		clka;
+	int			mdio_spre;
+	int			mdio_mode;
+} titan_ge_mdio_config;
+
+/*
+ * Function Prototypes
+ */
+int titan_ge_mdio_setup(titan_ge_mdio_config *);
+int titan_ge_mdio_inaddrs(int, int);
+int titan_ge_mdio_read(int, int, unsigned int *);
+int titan_ge_mdio_write(int, int, unsigned int);
+
+#endif /* _TITAN_MDIO_H */
diff --git a/drivers/net/mii.c b/drivers/net/mii.c
index 4a99c39..20a2bce 100644
--- a/drivers/net/mii.c
+++ b/drivers/net/mii.c
@@ -69,8 +69,13 @@ int mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd)
 	/* only supports twisted-pair */
 	ecmd->port = PORT_MII;
 
-	/* only supports internal transceiver */
+#ifndef CONFIG_BRCMSTB
+	/* only supports internal transceiver, except with CONFIG_BRCMSTB
+	 * where our drivers update the transceiver type accordingly to
+	 * give accurate information to user-space
+	 */
 	ecmd->transceiver = XCVR_INTERNAL;
+#endif
 
 	/* this isn't fully supported at higher layers */
 	ecmd->phy_address = mii->phy_id;
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index c8f160d..ce44388 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -1370,21 +1370,72 @@ struct regulator *regulator_get_exclusive(struct device *dev, const char *id)
 EXPORT_SYMBOL_GPL(regulator_get_exclusive);
 
 /**
- * regulator_put - "free" the regulator source
- * @regulator: regulator source
+ * regulator_get_optional - obtain optional access to a regulator.
+ * @dev: device for regulator "consumer"
+ * @id: Supply name or regulator ID.
  *
- * Note: drivers must ensure that all regulator_enable calls made on this
- * regulator source are balanced by regulator_disable calls prior to calling
- * this function.
+ * Returns a struct regulator corresponding to the regulator producer,
+ * or IS_ERR() condition containing errno.  Other consumers will be
+ * unable to obtain this reference is held and the use count for the
+ * regulator will be initialised to reflect the current state of the
+ * regulator.
+ *
+ * This is intended for use by consumers for devices which can have
+ * some supplies unconnected in normal use, such as some MMC devices.
+ * It can allow the regulator core to provide stub supplies for other
+ * supplies requested using normal regulator_get() calls without
+ * disrupting the operation of drivers that can handle absent
+ * supplies.
+ *
+ * Use of supply names configured via regulator_set_device_supply() is
+ * strongly encouraged.  It is recommended that the supply name used
+ * should match the name used for the supply and/or the relevant
+ * device pins in the datasheet.
  */
-void regulator_put(struct regulator *regulator)
+struct regulator *regulator_get_optional(struct device *dev, const char *id)
+{
+	return _regulator_get(dev, id, 0);
+}
+EXPORT_SYMBOL_GPL(regulator_get_optional);
+
+/**
+ * devm_regulator_get_optional - Resource managed regulator_get_optional()
+ * @dev: device for regulator "consumer"
+ * @id: Supply name or regulator ID.
+ *
+ * Managed regulator_get_optional(). Regulators returned from this
+ * function are automatically regulator_put() on driver detach. See
+ * regulator_get_optional() for more information.
+ */
+struct regulator *devm_regulator_get_optional(struct device *dev,
+					      const char *id)
+{
+	struct regulator **ptr, *regulator;
+
+	ptr = devres_alloc(devm_regulator_release, sizeof(*ptr), GFP_KERNEL);
+	if (!ptr)
+		return ERR_PTR(-ENOMEM);
+
+	regulator = regulator_get_optional(dev, id);
+	if (!IS_ERR(regulator)) {
+		*ptr = regulator;
+		devres_add(dev, ptr);
+	} else {
+		devres_free(ptr);
+	}
+
+	return regulator;
+}
+EXPORT_SYMBOL_GPL(devm_regulator_get_optional);
+
+/* Locks held by regulator_put() */
+static void _regulator_put(struct regulator *regulator)
 {
 	struct regulator_dev *rdev;
 
 	if (regulator == NULL || IS_ERR(regulator))
 		return;
 
-	mutex_lock(&regulator_list_mutex);
 	rdev = regulator->rdev;
 
 	debugfs_remove_recursive(regulator->debugfs);
@@ -1405,6 +1456,20 @@ void regulator_put(struct regulator *regulator)
 	mutex_unlock(&rdev->mutex);
 
 	module_put(rdev->owner);
+}
+
+/**
+ * regulator_put - "free" the regulator source
+ * @regulator: regulator source
+ *
+ * Note: drivers must ensure that all regulator_enable calls made on this
+ * regulator source are balanced by regulator_disable calls prior to calling
+ * this function.
+ */
+void regulator_put(struct regulator *regulator)
+{
+	mutex_lock(&regulator_list_mutex);
+	_regulator_put(regulator);
 	mutex_unlock(&regulator_list_mutex);
 }
 EXPORT_SYMBOL_GPL(regulator_put);
@@ -2526,7 +2591,7 @@ static void regulator_bulk_enable_async(void *data, async_cookie_t cookie)
 int regulator_bulk_enable(int num_consumers,
 			  struct regulator_bulk_data *consumers)
 {
-	LIST_HEAD(async_domain);
+	ASYNC_DOMAIN_EXCLUSIVE(async_domain);
 	int i;
 	int ret = 0;
 
@@ -2974,7 +3039,7 @@ unset_supplies:
 
 scrub:
 	if (rdev->supply)
-		regulator_put(rdev->supply);
+		_regulator_put(rdev->supply);
 	kfree(rdev->constraints);
 	device_unregister(&rdev->dev);
 	/* device core frees rdev */
diff --git a/drivers/scsi/libsas/sas_ata.c b/drivers/scsi/libsas/sas_ata.c
index 51ee663..ec96c5f 100644
--- a/drivers/scsi/libsas/sas_ata.c
+++ b/drivers/scsi/libsas/sas_ata.c
@@ -720,7 +720,7 @@ static void async_sas_ata_eh(void *data, async_cookie_t cookie)
 void sas_ata_strategy_handler(struct Scsi_Host *shost)
 {
 	struct sas_ha_struct *sas_ha = SHOST_TO_SAS_HA(shost);
-	LIST_HEAD(async);
+	ASYNC_DOMAIN_EXCLUSIVE(async);
 	int i;
 
 	/* it's ok to defer revalidation events during ata eh, these
diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c
index 29fabff..5dba497 100644
--- a/drivers/scsi/scsi.c
+++ b/drivers/scsi/scsi.c
@@ -54,6 +54,7 @@
 #include <linux/notifier.h>
 #include <linux/cpu.h>
 #include <linux/mutex.h>
+#include <linux/async.h>
 
 #include <scsi/scsi.h>
 #include <scsi/scsi_cmnd.h>
@@ -90,6 +91,10 @@ unsigned int scsi_logging_level;
 EXPORT_SYMBOL(scsi_logging_level);
 #endif
 
+/* sd, scsi core and power management need to coordinate flushing async actions */
+ASYNC_DOMAIN(scsi_sd_probe_domain);
+EXPORT_SYMBOL(scsi_sd_probe_domain);
+
 /* NB: These are exposed through /proc/scsi/scsi and form part of the ABI.
  * You may not alter any existing entry (although adding new ones is
  * encouraged once assigned by ANSI/INCITS T10
@@ -1353,6 +1358,7 @@ static void __exit exit_scsi(void)
 	scsi_exit_devinfo();
 	scsi_exit_procfs();
 	scsi_exit_queue();
+	async_unregister_domain(&scsi_sd_probe_domain);
 }
 
 subsys_initcall(init_scsi);
diff --git a/drivers/scsi/scsi_error.c b/drivers/scsi/scsi_error.c
index 185971c..142441e 100644
--- a/drivers/scsi/scsi_error.c
+++ b/drivers/scsi/scsi_error.c
@@ -305,12 +305,13 @@ static int scsi_check_sense(struct scsi_cmnd *scmd)
 		 */
 		if (scmd->device->expecting_cc_ua) {
 			/*
-			 * Because some device does not queue unit
+			 * Because some CDROM drives do not queue unit
 			 * attentions correctly, we carefully check
 			 * additional sense code and qualifier so as
 			 * not to squash media change unit attention.
 			 */
-			if (sshdr.asc != 0x28 || sshdr.ascq != 0x00) {
+			if ((sdev->type != TYPE_ROM) ||
+				(sshdr.asc != 0x28 || sshdr.ascq != 0x00)) {
 				scmd->device->expecting_cc_ua = 0;
 				return NEEDS_RETRY;
 			}
@@ -1755,6 +1756,9 @@ void scsi_eh_flush_done_q(struct list_head *done_q)
 	list_for_each_entry_safe(scmd, next, done_q, eh_entry) {
 		list_del_init(&scmd->eh_entry);
 		if (scsi_device_online(scmd->device) &&
+#if defined(CONFIG_BRCM_SCSI_NO_RW10_RETRIES)
+		    (scmd->cmnd[0] != READ_10) && (scmd->cmnd[0] != WRITE_10) &&
+#endif
 		    !scsi_noretry_cmd(scmd) &&
 		    (++scmd->retries <= scmd->allowed)) {
 			SCSI_LOG_ERROR_RECOVERY(3, printk("%s: flush"
diff --git a/drivers/scsi/scsi_lib.c b/drivers/scsi/scsi_lib.c
index a30f7a0..6eae082 100644
--- a/drivers/scsi/scsi_lib.c
+++ b/drivers/scsi/scsi_lib.c
@@ -2351,10 +2351,14 @@ EXPORT_SYMBOL(scsi_device_quiesce);
  *
  *	Must be called with user context, may sleep.
  */
-void
-scsi_device_resume(struct scsi_device *sdev)
+void scsi_device_resume(struct scsi_device *sdev)
 {
-	if(scsi_device_set_state(sdev, SDEV_RUNNING))
+	/* check if the device state was mutated prior to resume, and if
+	 * so assume the state is being managed elsewhere (for example
+	 * device deleted during suspend)
+	 */
+	if (sdev->sdev_state != SDEV_QUIESCE ||
+	    scsi_device_set_state(sdev, SDEV_RUNNING))
 		return;
 	scsi_run_queue(sdev->request_queue);
 }
diff --git a/drivers/scsi/scsi_pm.c b/drivers/scsi/scsi_pm.c
index c467064..f661a41 100644
--- a/drivers/scsi/scsi_pm.c
+++ b/drivers/scsi/scsi_pm.c
@@ -97,7 +97,7 @@ static int scsi_bus_prepare(struct device *dev)
 {
 	if (scsi_is_sdev_device(dev)) {
 		/* sd probing uses async_schedule.  Wait until it finishes. */
-		async_synchronize_full();
+		async_synchronize_full_domain(&scsi_sd_probe_domain);
 
 	} else if (scsi_is_host_device(dev)) {
 		/* Wait until async scanning is finished */
diff --git a/drivers/scsi/scsi_priv.h b/drivers/scsi/scsi_priv.h
index fd9f57f..d49eb9f 100644
--- a/drivers/scsi/scsi_priv.h
+++ b/drivers/scsi/scsi_priv.h
@@ -2,6 +2,7 @@
 #define _SCSI_PRIV_H
 
 #include <linux/device.h>
+#include <linux/async.h>
 
 struct request_queue;
 struct request;
@@ -162,6 +163,8 @@ static inline int scsi_autopm_get_host(struct Scsi_Host *h) { return 0; }
 static inline void scsi_autopm_put_host(struct Scsi_Host *h) {}
 #endif /* CONFIG_PM_RUNTIME */
 
+extern struct async_domain scsi_sd_probe_domain;
+
 /* 
  * internal scsi timeout functions: for use by mid-layer and transport
  * classes.
diff --git a/drivers/scsi/scsi_scan.c b/drivers/scsi/scsi_scan.c
index 37abf4f..b6454b1 100644
--- a/drivers/scsi/scsi_scan.c
+++ b/drivers/scsi/scsi_scan.c
@@ -184,18 +184,6 @@ int scsi_complete_async_scans(void)
 	return 0;
 }
 
-/* Only exported for the benefit of scsi_wait_scan */
-EXPORT_SYMBOL_GPL(scsi_complete_async_scans);
-
-#ifndef MODULE
-/*
- * For async scanning we need to wait for all the scans to complete before
- * trying to mount the root fs.  Otherwise non-modular drivers may not be ready
- * yet.
- */
-late_initcall(scsi_complete_async_scans);
-#endif
-
 /**
  * scsi_unlock_floptical - unlock device via a special MODE SENSE command
  * @sdev:	scsi device to send command to
@@ -1858,14 +1846,13 @@ static void do_scsi_scan_host(struct Scsi_Host *shost)
 	}
 }
 
-static int do_scan_async(void *_data)
+static void do_scan_async(void *_data, async_cookie_t c)
 {
 	struct async_scan_data *data = _data;
 	struct Scsi_Host *shost = data->shost;
 
 	do_scsi_scan_host(shost);
 	scsi_finish_async_scan(data);
-	return 0;
 }
 
 /**
@@ -1874,7 +1861,6 @@ static int do_scan_async(void *_data)
  **/
 void scsi_scan_host(struct Scsi_Host *shost)
 {
-	struct task_struct *p;
 	struct async_scan_data *data;
 
 	if (strncmp(scsi_scan_type, "none", 4) == 0)
@@ -1889,9 +1875,11 @@ void scsi_scan_host(struct Scsi_Host *shost)
 		return;
 	}
 
-	p = kthread_run(do_scan_async, data, "scsi_scan_%d", shost->host_no);
-	if (IS_ERR(p))
-		do_scan_async(data);
+	/* register with the async subsystem so wait_for_device_probe()
+	 * will flush this work
+	 */
+	async_schedule(do_scan_async, data);
+
 	/* scsi_autopm_put_host(shost) is called in scsi_finish_async_scan() */
 }
 EXPORT_SYMBOL(scsi_scan_host);
diff --git a/drivers/scsi/scsi_wait_scan.c b/drivers/scsi/scsi_wait_scan.c
index ae78148..0727345 100644
--- a/drivers/scsi/scsi_wait_scan.c
+++ b/drivers/scsi/scsi_wait_scan.c
@@ -22,11 +22,6 @@ static int __init wait_scan_init(void)
 	 * and might not yet have reached the scsi async scanning
 	 */
 	wait_for_device_probe();
-	/*
-	 * and then we wait for the actual asynchronous scsi scan
-	 * to finish.
-	 */
-	scsi_complete_async_scans();
 	return 0;
 }
 
diff --git a/drivers/scsi/sd.c b/drivers/scsi/sd.c
index 97aa6c6..7ad7671 100644
--- a/drivers/scsi/sd.c
+++ b/drivers/scsi/sd.c
@@ -65,6 +65,7 @@
 #include <scsi/scsicam.h>
 
 #include "sd.h"
+#include "scsi_priv.h"
 #include "scsi_logging.h"
 
 MODULE_AUTHOR("Eric Youngdale");
@@ -2726,7 +2727,7 @@ static int sd_probe(struct device *dev)
 	dev_set_drvdata(dev, sdkp);
 
 	get_device(&sdkp->dev);	/* prevent release before async_schedule */
-	async_schedule(sd_probe_async, sdkp);
+	async_schedule_domain(sd_probe_async, sdkp, &scsi_sd_probe_domain);
 
 	return 0;
 
@@ -2760,7 +2761,7 @@ static int sd_remove(struct device *dev)
 	sdkp = dev_get_drvdata(dev);
 	scsi_autopm_get_device(sdkp->device);
 
-	async_synchronize_full();
+	async_synchronize_full_domain(&scsi_sd_probe_domain);
 	blk_queue_prep_rq(sdkp->device->request_queue, scsi_prep_fn);
 	blk_queue_unprep_rq(sdkp->device->request_queue, NULL);
 	device_del(&sdkp->dev);
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 9d75d21..dd47c511 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_SPI_BCM63XX)		+= spi-bcm63xx.o
 obj-$(CONFIG_SPI_BFIN5XX)		+= spi-bfin5xx.o
 obj-$(CONFIG_SPI_BFIN_SPORT)		+= spi-bfin-sport.o
 obj-$(CONFIG_SPI_BITBANG)		+= spi-bitbang.o
+obj-$(CONFIG_SPI_BRCMSTB)		+= spi-brcmstb.o
 obj-$(CONFIG_SPI_BUTTERFLY)		+= spi-butterfly.o
 obj-$(CONFIG_SPI_COLDFIRE_QSPI)		+= spi-coldfire-qspi.o
 obj-$(CONFIG_SPI_DAVINCI)		+= spi-davinci.o
diff --git a/drivers/spi/spi-brcmstb.c b/drivers/spi/spi-brcmstb.c
new file mode 100644
index 0000000..cbfd983
--- /dev/null
+++ b/drivers/spi/spi-brcmstb.c
@@ -0,0 +1,1712 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/sysfs.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/spi/spi.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+
+#include <linux/brcmstb/brcmstb.h>
+
+#define DBG pr_debug
+
+#if CONFIG_BRCM_BSPI_MAJOR_VERS >= 4
+#define BSPI_HAS_4BYTE_ADDRESS
+#define BSPI_HAS_FLEX_MODE
+#endif
+
+#define BSPI_LR_TIMEOUT			(1000)
+
+#define BSPI_LR_INTERRUPTS_DATA \
+	(BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK	| \
+	 BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK)
+
+#define BSPI_LR_INTERRUPTS_ERROR \
+	(BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK	| \
+	 BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK	| \
+	 BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK)
+
+#define BSPI_LR_INTERRUPTS_ALL \
+	(BSPI_LR_INTERRUPTS_ERROR | \
+	 BSPI_LR_INTERRUPTS_DATA)
+
+#define NUM_CHIPSELECT		4
+#define MSPI_BASE_FREQ		27000000UL
+#define SPBR_MIN		8U
+#define SPBR_MAX		255U
+#define MAX_SPEED_HZ		(MSPI_BASE_FREQ / (SPBR_MIN * 2))
+#define BSPI_BASE_ADDR		KSEG1ADDR(0x1f000000)
+
+#define OPCODE_RDID		0x9f
+#define OPCODE_WREN		0x06
+#define OPCODE_WRR		0x01
+#define OPCODE_RCR		0x35
+#define OPCODE_READ		0x03
+#define OPCODE_RDSR		0x05
+#define OPCODE_WRSR		0x01
+#define OPCODE_FAST_READ	0x0B
+#define OPCODE_DOR		0x3B
+#define OPCODE_QOR		0x6B
+#define OPCODE_FAST_READ_4B	0x0C
+#define OPCODE_DOR_4B		0x3C
+#define OPCODE_QOR_4B		0x6C
+
+#define OPCODE_DIOR		0xBB
+#define OPCODE_QIOR		0xEB
+#define OPCODE_DIOR_4B		0xBC
+#define OPCODE_QIOR_4B		0xEC
+
+#define OPCODE_PP		0x02
+#define OPCODE_PP_4B		0x12
+#define OPCODE_EN4B		0xB7
+#define OPCODE_EX4B		0xE9
+#define OPCODE_BRWR		0x17
+
+#define	BSPI_WIDTH_1BIT		1
+#define BSPI_WIDTH_2BIT		2
+#define BSPI_WIDTH_4BIT		4
+
+#define	BSPI_ADDRLEN_3BYTES	3
+#define	BSPI_ADDRLEN_4BYTES	4
+#define BSPI_BR_EXTADD		BIT(7)
+#define BSPI_FLASH_TYPE_SPANSION	0
+#define BSPI_FLASH_TYPE_MACRONIX	1
+#define BSPI_FLASH_TYPE_NUMONYX		2
+#define BSPI_FLASH_TYPE_SST		3
+#define BSPI_FLASH_TYPE_UNKNOWN		-1
+
+static int nobspi;
+module_param(nobspi, int, 0444);
+
+static int bspi_width  = BSPI_WIDTH_1BIT;
+module_param(bspi_width, int, 0444);
+
+static int bspi_addrlen  = BSPI_ADDRLEN_3BYTES;
+module_param(bspi_addrlen, int, 0444);
+
+static int bspi_hp;
+module_param(bspi_hp, int, 0444);
+
+static int bspi_flash = BSPI_FLASH_TYPE_UNKNOWN;
+module_param(bspi_flash, int, 0444);
+
+struct bcmspi_parms {
+	u32			speed_hz;
+	u8			chip_select;
+	u8			mode;
+	u8			bits_per_word;
+};
+
+const struct bcmspi_parms bcmspi_default_parms_cs0 = {
+	.speed_hz		= MAX_SPEED_HZ,
+	.chip_select		= 0,
+	.mode			= SPI_MODE_3,
+	.bits_per_word		= 8,
+};
+EXPORT_SYMBOL(bcmspi_default_parms_cs0);
+
+const struct bcmspi_parms bcmspi_default_parms_cs1 = {
+	.speed_hz		= MAX_SPEED_HZ,
+	.chip_select		= 1,
+	.mode			= SPI_MODE_3,
+	.bits_per_word		= 8,
+};
+EXPORT_SYMBOL(bcmspi_default_parms_cs1);
+
+struct position {
+	struct spi_message	*msg;
+	struct spi_transfer	*trans;
+	int			byte;
+};
+
+#define NUM_TXRAM		32
+#define NUM_RXRAM		32
+#define NUM_CDRAM		16
+
+struct bcm_mspi_hw {
+	u32			spcr0_lsb;		/* 0x000 */
+	u32			spcr0_msb;		/* 0x004 */
+	u32			spcr1_lsb;		/* 0x008 */
+	u32			spcr1_msb;		/* 0x00c */
+	u32			newqp;			/* 0x010 */
+	u32			endqp;			/* 0x014 */
+	u32			spcr2;			/* 0x018 */
+	u32			reserved0;		/* 0x01c */
+	u32			mspi_status;		/* 0x020 */
+	u32			cptqp;			/* 0x024 */
+	u32			reserved1[6];		/* 0x028 */
+	u32			txram[NUM_TXRAM];	/* 0x040 */
+	u32			rxram[NUM_RXRAM];	/* 0x0c0 */
+	u32			cdram[NUM_CDRAM];	/* 0x140 */
+};
+
+struct bcm_bspi_hw {
+	u32			revision_id;		/* 0x000 */
+	u32			scratch;		/* 0x004 */
+	u32			mast_n_boot_ctrl;	/* 0x008 */
+	u32			busy_status;		/* 0x00c */
+	u32			intr_status;		/* 0x010 */
+	u32			b0_status;		/* 0x014 */
+	u32			b0_ctrl;		/* 0x018 */
+	u32			b1_status;		/* 0x01c */
+	u32			b1_ctrl;		/* 0x020 */
+	u32			strap_override_ctrl;	/* 0x024 */
+#if CONFIG_BRCM_BSPI_MAJOR_VERS >= 4
+	u32			flex_mode_enable;	/* 0x028 */
+	u32			bits_per_cycle;		/* 0x02C */
+	u32			bits_per_phase;		/* 0x030 */
+	u32			cmd_and_mode_byte;	/* 0x034 */
+	u32			flash_upper_addr_byte;	/* 0x038 */
+	u32			xor_value;		/* 0x03C */
+	u32			xor_enable;		/* 0x040 */
+	u32			pio_mode_enable;	/* 0x044 */
+	u32			pio_iodir;		/* 0x048 */
+	u32			pio_data;		/* 0x04C */
+#endif
+};
+
+struct bcm_bspi_raf {
+	u32			start_address;		/* 0x00 */
+	u32			num_words;		/* 0x04 */
+	u32			ctrl;			/* 0x08 */
+	u32			fullness;		/* 0x0C */
+	u32			watermark;		/* 0x10 */
+	u32			status;			/* 0x14 */
+	u32			read_data;		/* 0x18 */
+	u32			word_cnt;		/* 0x1C */
+	u32			curr_addr;		/* 0x20 */
+};
+
+struct bcm_flex_mode {
+	int			width;
+	int			addrlen;
+	int			hp;
+};
+
+#define STATE_IDLE		0
+#define STATE_RUNNING		1
+#define STATE_SHUTDOWN		2
+#define STATE_SUSPEND		3
+
+struct bcmspi_priv {
+	struct platform_device	*pdev;
+	struct spi_master	*master;
+	spinlock_t		lock;
+	struct bcmspi_parms	last_parms;
+	struct position		pos;
+	struct list_head	msg_queue;
+	int			state;
+	int			outstanding_bytes;
+	int			next_udelay;
+	int			cs_change;
+	unsigned int		max_speed_hz;
+	volatile struct bcm_mspi_hw *mspi_hw;
+	int			irq;
+	struct tasklet_struct	tasklet;
+	int			curr_cs;
+
+	/* BSPI */
+	volatile struct bcm_bspi_hw *bspi_hw;
+	int			bspi_enabled;
+	/* all chip selects controlled by BSPI */
+	int			bspi_chip_select;
+
+	/* LR */
+	volatile struct bcm_bspi_raf *bspi_hw_raf;
+	struct spi_transfer	*cur_xfer;
+	u32			cur_xfer_idx;
+	u32			cur_xfer_len;
+	u32			xfer_status;
+	struct spi_message	*cur_msg;
+	u32			actual_length;
+
+	/* current flex mode settings */
+	struct bcm_flex_mode	flex_mode;
+
+	/* S3 warm boot context save */
+	u32			s3_intr2_mask;
+	u32			s3_strap_override_ctrl;
+};
+
+static void bcmspi_enable_interrupt(u32 mask)
+{
+	BDEV_SET_RB(BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR, mask);
+}
+
+static void bcmspi_disable_interrupt(u32 mask)
+{
+	BDEV_SET_RB(BCHP_HIF_SPI_INTR2_CPU_MASK_SET, mask);
+}
+
+static void bcmspi_clear_interrupt(u32 mask)
+{
+	BDEV_SET_RB(BCHP_HIF_SPI_INTR2_CPU_CLEAR, mask);
+}
+
+static u32 bcmspi_read_interrupt(void)
+{
+	return BDEV_RD(BCHP_HIF_SPI_INTR2_CPU_STATUS);
+}
+
+static int bcmspi_busy_poll(struct bcmspi_priv *priv)
+{
+	int i;
+
+	/* this should normally finish within 10us */
+	for (i = 0; i < 1000; i++) {
+		if ((priv->bspi_hw->busy_status & 1) == 0)
+			return 0;
+		udelay(1);
+	}
+	dev_warn(&priv->pdev->dev, "timeout waiting for !busy_status\n");
+	return -EIO;
+}
+
+static void bcmspi_flush_prefetch_buffers(struct bcmspi_priv *priv)
+{
+	/* SWLINUX-2407: avoid flushing if B1 prefetch is still active */
+	bcmspi_busy_poll(priv);
+
+	/* Force rising edge for the b0/b1 'flush' field */
+	priv->bspi_hw->b0_ctrl = 1;
+	priv->bspi_hw->b1_ctrl = 1;
+	priv->bspi_hw->b0_ctrl = 0;
+	priv->bspi_hw->b1_ctrl = 0;
+}
+
+static int bcmspi_lr_is_fifo_empty(struct bcmspi_priv *priv)
+{
+	return priv->bspi_hw_raf->status & BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK;
+}
+
+/* BSPI v3 LR is LE only, convert data to host endianness */
+#if CONFIG_BRCM_BSPI_MAJOR_VERS >= 4
+#define BSPI_DATA(a) (a)
+#else
+#define BSPI_DATA(a) le32_to_cpu(a)
+#endif
+
+static inline u32 bcmspi_lr_read_fifo(struct bcmspi_priv *priv)
+{
+	return BSPI_DATA(priv->bspi_hw_raf->read_data);
+}
+
+static inline void bcmspi_lr_start(struct bcmspi_priv *priv)
+{
+	priv->bspi_hw_raf->ctrl = BCHP_BSPI_RAF_CTRL_START_MASK;
+}
+
+static inline void bcmspi_lr_clear(struct bcmspi_priv *priv)
+{
+	priv->bspi_hw_raf->ctrl = BCHP_BSPI_RAF_CTRL_CLEAR_MASK;
+	bcmspi_flush_prefetch_buffers(priv);
+}
+
+static inline int bcmspi_is_4_byte_mode(struct bcmspi_priv *priv)
+{
+	return priv->flex_mode.addrlen == BSPI_ADDRLEN_4BYTES;
+}
+
+static int bcmspi_set_override_ctrl(struct bcmspi_priv *priv,
+	int width, int addrlen, int hp)
+{
+	u32 strap_override = priv->bspi_hw->strap_override_ctrl;
+
+	switch (width) {
+	case BSPI_WIDTH_4BIT:
+		strap_override &= ~0x2; /* clear dual mode */
+		strap_override |= 0x9; /* set quad mode + override */
+		break;
+	case BSPI_WIDTH_2BIT:
+		strap_override &= ~0x8; /* clear quad mode */
+		strap_override |= 0x3; /* set dual mode + override */
+		break;
+	case BSPI_WIDTH_1BIT:
+		strap_override &= ~0xA; /* clear quad/dual mode */
+		strap_override |= 1; /* set override */
+		break;
+	default:
+		break;
+	}
+
+	if (addrlen == BSPI_ADDRLEN_4BYTES) {
+		strap_override |= 0x5; /* set 4byte + override */
+	} else {
+		strap_override &= ~0x4; /* clear 4 byte */
+		strap_override |= 0x1; /* set override */
+	}
+
+	priv->bspi_hw->strap_override_ctrl = strap_override;
+
+	return 0;
+}
+
+#ifdef BSPI_HAS_FLEX_MODE
+static int bcmbspi_flash_type(struct bcmspi_priv *priv);
+
+static int bcmspi_set_flex_mode(struct bcmspi_priv *priv,
+	int width, int addrlen, int hp)
+{
+	int bpc = 0, bpp = 0, command;
+	int flex_mode = 1, error = 0;
+
+	if (priv->bspi_hw->strap_override_ctrl & 0x1 ||
+		priv->s3_strap_override_ctrl & 0x1) {
+		flex_mode = 0;
+		command = OPCODE_FAST_READ;
+		error = bcmspi_set_override_ctrl(priv, width, addrlen, hp);
+		goto override;
+	}
+
+	switch (width) {
+	case BSPI_WIDTH_1BIT:
+		bpp = 8; /* dummy cycles */
+		if (addrlen == BSPI_ADDRLEN_3BYTES) {
+			/* default mode, does not need flex_cmd */
+			flex_mode = 0;
+			command = OPCODE_FAST_READ;
+		} else {
+			bpp |= BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK;
+			command = OPCODE_FAST_READ_4B;
+		}
+		break;
+	case BSPI_WIDTH_2BIT:
+		bpc = 0x00000001; /* only data is 2-bit */
+		if (hp) {
+			bpc |= 0x00010100; /* address and mode are 2-bit too */
+			bpp |= BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK;
+			command = OPCODE_DIOR;
+			if (addrlen == BSPI_ADDRLEN_4BYTES) {
+				bpp |=
+				 BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK;
+				command = OPCODE_DIOR_4B;
+			}
+		} else {
+			bpp = 8; /* dummy cycles */
+			command = OPCODE_DOR;
+			if (addrlen == BSPI_ADDRLEN_4BYTES) {
+				bpp |=
+				 BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK;
+				command = OPCODE_DOR_4B;
+			}
+		}
+		break;
+	case BSPI_WIDTH_4BIT:
+		bpc = 0x00000002; /* only data is 4-bit */
+		if (hp) {
+			bpc |= 0x00020200; /* address and mode are 4-bit too */
+			bpp = 4; /* dummy cycles */
+			bpp |= BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK;
+			command = OPCODE_QIOR;
+			if (addrlen == BSPI_ADDRLEN_4BYTES) {
+				bpp |=
+				 BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK;
+				command = OPCODE_QIOR_4B;
+			}
+		} else {
+			bpp = 8; /* dummy cycles */
+			command = OPCODE_QOR;
+			if (addrlen == BSPI_ADDRLEN_4BYTES) {
+				bpp |=
+				 BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK;
+				command = OPCODE_QOR_4B;
+			}
+		}
+		break;
+	default:
+		error = 1;
+		break;
+	}
+
+override:
+	if (!error) {
+		priv->bspi_hw->flex_mode_enable = 0;
+		priv->bspi_hw->bits_per_cycle = bpc;
+		priv->bspi_hw->bits_per_phase = bpp;
+		priv->bspi_hw->cmd_and_mode_byte = command;
+		priv->bspi_hw->flex_mode_enable = flex_mode ?
+			BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK
+			: 0;
+		DBG("%s: width=%d addrlen=%d hp=%d\n",
+			__func__, width, addrlen, hp);
+		DBG("%s: fme=%08x bpc=%08x bpp=%08x cmd=%08x\n", __func__,
+			priv->bspi_hw->flex_mode_enable,
+			priv->bspi_hw->bits_per_cycle,
+			priv->bspi_hw->bits_per_phase,
+			priv->bspi_hw->cmd_and_mode_byte);
+	}
+
+	return error;
+}
+#else
+static int bcmspi_set_flex_mode(struct bcmspi_priv *priv,
+	int width, int addrlen, int hp)
+{
+	return bcmspi_set_override_ctrl(priv, width, addrlen, hp);
+}
+#endif
+
+static void bcmspi_set_mode(struct bcmspi_priv *priv,
+	int width, int addrlen, int hp)
+{
+	int error = 0;
+
+	if (width == -1)
+		width = priv->flex_mode.width;
+	if (addrlen == -1)
+		addrlen = priv->flex_mode.addrlen;
+	if (hp == -1)
+		hp = priv->flex_mode.hp;
+
+	error = bcmspi_set_flex_mode(priv, width, addrlen, hp);
+
+	if (!error) {
+		priv->flex_mode.width = width;
+		priv->flex_mode.addrlen = addrlen;
+		priv->flex_mode.hp = hp;
+		dev_info(&priv->pdev->dev,
+			"%d-lane output, %d-byte address%s\n",
+			priv->flex_mode.width,
+			priv->flex_mode.addrlen,
+			priv->flex_mode.hp ? ", high-performance mode" : "");
+	} else
+		dev_warn(&priv->pdev->dev,
+			"INVALID COMBINATION: width=%d addrlen=%d hp=%d\n",
+			width, addrlen, hp);
+}
+
+static void bcmspi_set_chip_select(struct bcmspi_priv *priv, int cs)
+{
+	if (priv->curr_cs != cs) {
+		DBG("Switching CS%1d => CS%1d\n",
+			priv->curr_cs, cs);
+		BDEV_WR_RB(BCHP_EBI_CS_SPI_SELECT,
+			(BDEV_RD(BCHP_EBI_CS_SPI_SELECT) & ~0xff) |
+			(1 << cs));
+		udelay(10);
+	}
+	priv->curr_cs = cs;
+
+}
+
+static inline int is_bspi_chip_select(struct bcmspi_priv *priv, u8 cs)
+{
+	return priv->bspi_chip_select & (1 << cs);
+}
+
+static void bcmspi_disable_bspi(struct bcmspi_priv *priv)
+{
+	if (!priv->bspi_hw || !priv->bspi_enabled)
+		return;
+
+	priv->bspi_enabled = 0;
+	if ((priv->bspi_hw->mast_n_boot_ctrl & 1) == 1)
+		return;
+
+	DBG("disabling bspi\n");
+	bcmspi_busy_poll(priv);
+	priv->bspi_hw->mast_n_boot_ctrl = 1;
+	udelay(1);
+}
+
+static void bcmspi_enable_bspi(struct bcmspi_priv *priv)
+{
+	if (!priv->bspi_hw || priv->bspi_enabled)
+		return;
+	if ((priv->bspi_hw->mast_n_boot_ctrl & 1) == 0) {
+		priv->bspi_enabled = 1;
+		return;
+	}
+
+	DBG("enabling bspi\n");
+	bcmspi_flush_prefetch_buffers(priv);
+	udelay(1);
+	priv->bspi_hw->mast_n_boot_ctrl = 0;
+	priv->bspi_enabled = 1;
+}
+
+static void bcmspi_hw_set_parms(struct bcmspi_priv *priv,
+	const struct bcmspi_parms *xp)
+{
+	if (xp->speed_hz) {
+		unsigned int spbr = MSPI_BASE_FREQ / (2 * xp->speed_hz);
+
+		priv->mspi_hw->spcr0_lsb = max(min(spbr, SPBR_MAX), SPBR_MIN);
+	} else {
+		priv->mspi_hw->spcr0_lsb = SPBR_MIN;
+	}
+	priv->mspi_hw->spcr0_msb = 0x80 |	/* MSTR bit */
+		((xp->bits_per_word ? xp->bits_per_word : 8) << 2) |
+		(xp->mode & 3);
+	priv->last_parms = *xp;
+}
+
+#define PARMS_NO_OVERRIDE		0
+#define PARMS_OVERRIDE			1
+
+static int bcmspi_update_parms(struct bcmspi_priv *priv,
+	struct spi_device *spidev, struct spi_transfer *trans, int override)
+{
+	struct bcmspi_parms xp;
+
+	xp.speed_hz = min(trans->speed_hz ? trans->speed_hz :
+		(spidev->max_speed_hz ? spidev->max_speed_hz : MAX_SPEED_HZ),
+		MAX_SPEED_HZ);
+	xp.chip_select = spidev->chip_select;
+	xp.mode = spidev->mode;
+	xp.bits_per_word = trans->bits_per_word ? trans->bits_per_word :
+		(spidev->bits_per_word ? spidev->bits_per_word : 8);
+
+	if ((override == PARMS_OVERRIDE) ||
+		((xp.speed_hz == priv->last_parms.speed_hz) &&
+		 (xp.chip_select == priv->last_parms.chip_select) &&
+		 (xp.mode == priv->last_parms.mode) &&
+		 (xp.bits_per_word == priv->last_parms.bits_per_word))) {
+		bcmspi_hw_set_parms(priv, &xp);
+		return 0;
+	}
+	/* no override, and parms do not match */
+	return 1;
+}
+
+
+static int bcmspi_setup(struct spi_device *spi)
+{
+	struct bcmspi_parms *xp;
+	struct bcmspi_priv *priv = spi_master_get_devdata(spi->master);
+
+	DBG("%s\n", __func__);
+
+	if (spi->bits_per_word > 16)
+		return -EINVAL;
+
+	xp = spi_get_ctldata(spi);
+	if (!xp) {
+		xp = kzalloc(sizeof(struct bcmspi_parms), GFP_KERNEL);
+		if (!xp)
+			return -ENOMEM;
+		spi_set_ctldata(spi, xp);
+	}
+	if (spi->max_speed_hz < priv->max_speed_hz)
+		xp->speed_hz = spi->max_speed_hz;
+	else
+		xp->speed_hz = 0;
+
+	xp->chip_select = spi->chip_select;
+	xp->mode = spi->mode;
+	xp->bits_per_word = spi->bits_per_word ? spi->bits_per_word : 8;
+
+	return 0;
+}
+
+/* stop at end of transfer, no other reason */
+#define FNB_BREAK_NONE			0
+/* stop at end of spi_message */
+#define FNB_BREAK_EOM			1
+/* stop at end of spi_transfer if delay */
+#define FNB_BREAK_DELAY			2
+/* stop at end of spi_transfer if cs_change */
+#define FNB_BREAK_CS_CHANGE		4
+/* stop if we run out of bytes */
+#define FNB_BREAK_NO_BYTES		8
+
+/* events that make us stop filling TX slots */
+#define FNB_BREAK_TX			(FNB_BREAK_EOM | FNB_BREAK_DELAY | \
+					 FNB_BREAK_CS_CHANGE)
+
+/* events that make us deassert CS */
+#define FNB_BREAK_DESELECT		(FNB_BREAK_EOM | FNB_BREAK_CS_CHANGE)
+
+
+static int find_next_byte(struct bcmspi_priv *priv, struct position *p,
+	struct list_head *completed, int flags)
+{
+	int ret = FNB_BREAK_NONE;
+
+	p->byte++;
+
+	while (p->byte >= p->trans->len) {
+		/* we're at the end of the spi_transfer */
+
+		/* in TX mode, need to pause for a delay or CS change */
+		if (p->trans->delay_usecs && (flags & FNB_BREAK_DELAY))
+			ret |= FNB_BREAK_DELAY;
+		if (p->trans->cs_change && (flags & FNB_BREAK_CS_CHANGE))
+			ret |= FNB_BREAK_CS_CHANGE;
+		if (ret)
+			return ret;
+
+		/* advance to next spi_message? */
+		if (list_is_last(&p->trans->transfer_list,
+				&p->msg->transfers)) {
+			struct spi_message *next_msg = NULL;
+
+			/* TX breaks at the end of each message as well */
+			if (!completed || (flags & FNB_BREAK_EOM)) {
+				DBG("find_next_byte: advance msg exit\n");
+				return FNB_BREAK_EOM;
+			}
+			if (!list_is_last(&p->msg->queue, &priv->msg_queue)) {
+				next_msg = list_entry(p->msg->queue.next,
+					struct spi_message, queue);
+			}
+			/* delete from run queue, add to completion queue */
+			list_del(&p->msg->queue);
+			list_add_tail(&p->msg->queue, completed);
+
+			p->msg = next_msg;
+			p->byte = 0;
+			if (p->msg == NULL) {
+				p->trans = NULL;
+				ret = FNB_BREAK_NO_BYTES;
+				break;
+			}
+
+			/*
+			 * move on to the first spi_transfer of the new
+			 * spi_message
+			 */
+			p->trans = list_entry(p->msg->transfers.next,
+				struct spi_transfer, transfer_list);
+		} else {
+			/* or just advance to the next spi_transfer */
+			p->trans = list_entry(p->trans->transfer_list.next,
+				struct spi_transfer, transfer_list);
+			p->byte = 0;
+		}
+	}
+	DBG("find_next_byte: msg %p trans %p len %d byte %d ret %x\n",
+		p->msg, p->trans, p->trans ? p->trans->len : 0, p->byte, ret);
+	return ret;
+}
+
+static void read_from_hw(struct bcmspi_priv *priv, struct list_head *completed)
+{
+	struct position p;
+	int slot = 0, n = priv->outstanding_bytes;
+
+	DBG("%s\n", __func__);
+
+	p = priv->pos;
+
+	while (n > 0) {
+		BUG_ON(p.msg == NULL);
+
+		if (p.trans->bits_per_word <= 8) {
+			u8 *buf = p.trans->rx_buf;
+
+			if (buf) {
+				buf[p.byte] =
+					priv->mspi_hw->rxram[(slot << 1) + 1]
+						& 0xff;
+			}
+			DBG("RD %02x\n", buf ? buf[p.byte] : 0xff);
+		} else {
+			u16 *buf = p.trans->rx_buf;
+
+			if (buf) {
+				buf[p.byte] =
+					((priv->mspi_hw->rxram[(slot << 1) + 1]
+						& 0xff) << 0) |
+					((priv->mspi_hw->rxram[(slot << 1) + 0]
+						& 0xff) << 8);
+			}
+		}
+		slot++;
+		n--;
+		p.msg->actual_length++;
+
+		find_next_byte(priv, &p, completed, FNB_BREAK_NONE);
+	}
+
+	priv->pos = p;
+	priv->outstanding_bytes = 0;
+}
+
+static void write_to_hw(struct bcmspi_priv *priv)
+{
+	struct position p;
+	int slot = 0, fnb = 0;
+	struct spi_message *msg = NULL;
+
+	DBG("%s\n", __func__);
+
+	bcmspi_disable_bspi(priv);
+
+	p = priv->pos;
+
+	while (1) {
+		if (p.msg == NULL)
+			break;
+		if (!msg) {
+			msg = p.msg;
+			bcmspi_update_parms(priv, msg->spi, p.trans,
+				PARMS_OVERRIDE);
+		} else {
+			/* break if the speed, bits, etc. changed */
+			if (bcmspi_update_parms(priv, msg->spi, p.trans,
+				PARMS_NO_OVERRIDE)) {
+				DBG("parms don't match, breaking\n");
+				break;
+			}
+		}
+		if (p.trans->bits_per_word <= 8) {
+			const u8 *buf = p.trans->tx_buf;
+
+			priv->mspi_hw->txram[slot << 1] = buf ?
+				(buf[p.byte] & 0xff) : 0xff;
+			DBG("WR %02x\n", buf ? buf[p.byte] : 0xff);
+		} else {
+			const u16 *buf = p.trans->tx_buf;
+
+			priv->mspi_hw->txram[(slot << 1) + 0] = buf ?
+				(buf[p.byte] >> 8) : 0xff;
+			priv->mspi_hw->txram[(slot << 1) + 1] = buf ?
+				(buf[p.byte] & 0xff) : 0xff;
+		}
+		priv->mspi_hw->cdram[slot] =
+			((p.trans->bits_per_word <= 8) ? 0x8e : 0xce);
+		slot++;
+
+		fnb = find_next_byte(priv, &p, NULL, FNB_BREAK_TX);
+
+		if (fnb & FNB_BREAK_CS_CHANGE)
+			priv->cs_change = 1;
+		if (fnb & FNB_BREAK_DELAY)
+			priv->next_udelay = p.trans->delay_usecs;
+		if (fnb || (slot == NUM_CDRAM))
+			break;
+	}
+	if (slot) {
+		DBG("submitting %d slots\n", slot);
+		priv->mspi_hw->newqp = 0;
+		priv->mspi_hw->endqp = slot - 1;
+
+		/* deassert CS on the final byte */
+		if (fnb & FNB_BREAK_DESELECT)
+			priv->mspi_hw->cdram[slot - 1] &= ~0x80;
+
+		/* tell HIF_MSPI which CS to use */
+		bcmspi_set_chip_select(priv, msg->spi->chip_select);
+
+		BDEV_WR_F_RB(HIF_MSPI_WRITE_LOCK, WriteLock, 1);
+		priv->mspi_hw->spcr2 = 0xe0;	/* cont | spe | spifie */
+
+		priv->state = STATE_RUNNING;
+		priv->outstanding_bytes = slot;
+	} else {
+		BDEV_WR_F_RB(HIF_MSPI_WRITE_LOCK, WriteLock, 0);
+		priv->state = STATE_IDLE;
+	}
+}
+
+#define DWORD_ALIGNED(a) (!(((unsigned long)(a)) & 3))
+#define ADDR_TO_4MBYTE_SEGMENT(addr)	(((u32)(addr)) >> 22)
+
+static int bcmspi_emulate_flash_read(struct bcmspi_priv *priv,
+	struct spi_message *msg)
+{
+	struct spi_transfer *trans;
+	u32 addr, len, len_in_dwords;
+	u8 *buf, *src;
+	unsigned long flags;
+	int idx;
+
+#ifndef BSPI_HAS_4BYTE_ADDRESS
+	/* 4-byte address mode is not supported through BSPI */
+	if (bcmspi_is_4_byte_mode(priv))
+		return -1;
+#endif
+
+	/* acquire lock when the MSPI is idle */
+	while (1) {
+		spin_lock_irqsave(&priv->lock, flags);
+		if (priv->state == STATE_IDLE)
+			break;
+		spin_unlock_irqrestore(&priv->lock, flags);
+		if (priv->state == STATE_SHUTDOWN)
+			return -EIO;
+		udelay(1);
+	}
+	bcmspi_set_chip_select(priv, msg->spi->chip_select);
+
+	/* first transfer - OPCODE_READ + {3,4}-byte address */
+	trans = list_entry(msg->transfers.next, struct spi_transfer,
+		transfer_list);
+	buf = (void *)trans->tx_buf;
+
+	idx = 1;
+
+#ifdef BSPI_HAS_4BYTE_ADDRESS
+	if (bcmspi_is_4_byte_mode(priv))
+		priv->bspi_hw->flash_upper_addr_byte = buf[idx++] << 24;
+	else
+		priv->bspi_hw->flash_upper_addr_byte = 0;
+#endif
+
+	addr = (buf[idx] << 16) | (buf[idx+1] << 8) | buf[idx+2];
+	addr |= priv->bspi_hw->flash_upper_addr_byte;
+
+	/* second transfer - read result into buffer */
+	trans = list_entry(msg->transfers.next->next, struct spi_transfer,
+		transfer_list);
+
+	buf = (void *)trans->rx_buf;
+	len = trans->len;
+
+#if CONFIG_BRCM_BSPI_MAJOR_VERS < 4
+	/*
+	 * The address coming into this function is a raw flash offset.  But
+	 * for BSPI <= V3, we need to convert it to a remapped BSPI address.
+	 * If it crosses a 4MB boundary, just revert back to using MSPI.
+	 */
+	addr = (addr + 0xc00000) & 0xffffff;
+
+	if (ADDR_TO_4MBYTE_SEGMENT(addr) ^
+	    ADDR_TO_4MBYTE_SEGMENT(addr + len - 1)) {
+		spin_unlock_irqrestore(&priv->lock, flags);
+		return -1;
+	}
+#endif
+
+	/* non-aligned and very short transfers are handled by MSPI */
+	if (unlikely(!DWORD_ALIGNED(addr) ||
+		     !DWORD_ALIGNED(buf) ||
+		     len < sizeof(u32) ||
+		     !priv->bspi_hw_raf)) {
+		spin_unlock_irqrestore(&priv->lock, flags);
+		return -1;
+	}
+
+	src = (u8 *)BSPI_BASE_ADDR + addr;
+
+	bcmspi_enable_bspi(priv);
+
+	DBG("%s: dst %p src %p len %x addr BSPI %06x\n",
+		__func__, buf, src, len, addr);
+
+	len_in_dwords = (len + 3) >> 2;
+
+	/* initialize software parameters */
+	priv->xfer_status = 0;
+	priv->cur_xfer = trans;
+	priv->cur_xfer_idx = 0;
+	priv->cur_xfer_len = len;
+	priv->cur_msg = msg;
+	priv->actual_length = idx + 4 + trans->len;
+
+	/* setup hardware */
+	/* address must be 4-byte aligned */
+	priv->bspi_hw_raf->start_address = addr;
+	priv->bspi_hw_raf->num_words = len_in_dwords;
+	priv->bspi_hw_raf->watermark = 0;
+
+	DBG("READ: %08x %08x (%08x)\n", addr, len_in_dwords, trans->len);
+
+	bcmspi_clear_interrupt(0xffffffff);
+	bcmspi_enable_interrupt(BSPI_LR_INTERRUPTS_ALL);
+	bcmspi_lr_start(priv);
+
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	return 0;
+}
+
+/*
+ * m25p80_read() calls wait_till_ready() before each read to check
+ * the flash status register for pending writes.
+ *
+ * This can be safely skipped if our last transaction was just an
+ * emulated BSPI read.
+ */
+static int bcmspi_emulate_flash_rdsr(struct bcmspi_priv *priv,
+	struct spi_message *msg)
+{
+	u8 *buf;
+	struct spi_transfer *trans;
+
+	if (priv->bspi_enabled == 0)
+		return 1;
+
+	trans = list_entry(msg->transfers.next->next, struct spi_transfer,
+		transfer_list);
+
+	buf = (void *)trans->rx_buf;
+	*buf = 0x00;
+
+	msg->actual_length = 2;
+	msg->complete(msg->context);
+	msg->status = 0;
+
+	return 0;
+}
+
+static int bcmspi_transfer(struct spi_device *spi, struct spi_message *msg)
+{
+	struct bcmspi_priv *priv = spi_master_get_devdata(spi->master);
+	unsigned long flags;
+
+	if (is_bspi_chip_select(priv, msg->spi->chip_select)) {
+		struct spi_transfer *trans;
+
+		trans = list_entry(msg->transfers.next,
+			struct spi_transfer, transfer_list);
+		if (trans && trans->len && trans->tx_buf) {
+			u8 command = ((u8 *)trans->tx_buf)[0];
+			switch (command) {
+			case OPCODE_FAST_READ_4B:
+				if (!bcmspi_is_4_byte_mode(priv))
+					bcmspi_set_mode(priv, -1,
+						BSPI_ADDRLEN_4BYTES, -1);
+				/* fall through */
+			case OPCODE_FAST_READ:
+				if (bcmspi_emulate_flash_read(priv, msg) == 0)
+					return 0;
+				break;
+			case OPCODE_QIOR_4B:
+			case OPCODE_QOR_4B:
+			case OPCODE_QOR:
+				if (bcmspi_emulate_flash_read(priv, msg) == 0)
+					return 0;
+
+			case OPCODE_RDSR:
+				if (bcmspi_emulate_flash_rdsr(priv, msg) == 0)
+					return 0;
+				break;
+			case OPCODE_EN4B:
+				DBG("ENABLE 4-BYTE MODE\n");
+				bcmspi_set_mode(priv, -1,
+					BSPI_ADDRLEN_4BYTES, -1);
+				break;
+			case OPCODE_EX4B:
+				DBG("DISABLE 4-BYTE MODE\n");
+				bcmspi_set_mode(priv, -1,
+					BSPI_ADDRLEN_3BYTES, -1);
+				break;
+			case OPCODE_BRWR:
+				{
+					u8 enable = ((u8 *)trans->tx_buf)[1];
+					DBG("%s 4-BYTE MODE\n",
+					    enable ? "ENABLE" : "DISABLE");
+					bcmspi_set_mode(priv, -1,
+						enable ? BSPI_ADDRLEN_4BYTES :
+						BSPI_ADDRLEN_3BYTES, -1);
+				}
+				break;
+			case OPCODE_PP:
+				DBG("Program page 3B addressing command:\n");
+				break;
+			case OPCODE_PP_4B:
+				DBG("Program page 4B addressing command:\n");
+				break;
+
+			default:
+				break;
+			}
+		}
+	}
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	if (priv->state == STATE_SHUTDOWN) {
+		spin_unlock_irqrestore(&priv->lock, flags);
+		return -EIO;
+	}
+
+	msg->actual_length = 0;
+
+	list_add_tail(&msg->queue, &priv->msg_queue);
+
+	if (priv->state == STATE_IDLE) {
+		BUG_ON(priv->pos.msg != NULL);
+		priv->pos.msg = msg;
+		priv->pos.trans = list_entry(msg->transfers.next,
+			struct spi_transfer, transfer_list);
+		priv->pos.byte = 0;
+
+		write_to_hw(priv);
+	}
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	return 0;
+}
+
+static void bcmspi_cleanup(struct spi_device *spi)
+{
+	struct bcmspi_parms *xp = spi_get_ctldata(spi);
+
+	DBG("%s\n", __func__);
+
+	kfree(xp);
+}
+
+static irqreturn_t bcmspi_interrupt(int irq, void *dev_id)
+{
+	struct bcmspi_priv *priv = dev_id;
+
+	if (priv->bspi_enabled && priv->cur_xfer) {
+		int done = 0;
+		u32 status = bcmspi_read_interrupt();
+		u32 *buf = (u32 *)priv->cur_xfer->rx_buf;
+		if (status & BSPI_LR_INTERRUPTS_DATA) {
+			while (!bcmspi_lr_is_fifo_empty(priv)) {
+				u32 data = bcmspi_lr_read_fifo(priv);
+				if (likely(priv->cur_xfer_len >= 4)) {
+					buf[priv->cur_xfer_idx++] = data;
+					priv->cur_xfer_len -= 4;
+				} else {
+					/*
+					 * Read out remaining bytes, make sure
+					 * we do not cross the buffer boundary
+					 */
+					u8 *cbuf =
+						(u8 *)&buf[priv->cur_xfer_idx];
+					data = cpu_to_le32(data);
+					while (priv->cur_xfer_len) {
+						*cbuf++ = (u8)data;
+						data >>= 8;
+						priv->cur_xfer_len--;
+					}
+				}
+			}
+		}
+		if (status & BSPI_LR_INTERRUPTS_ERROR) {
+			dev_err(&priv->pdev->dev, "ERROR %02x\n", status);
+			priv->xfer_status = -EIO;
+		} else if (!priv->cur_xfer_len)
+			done = 1;
+		if (done) {
+			priv->cur_xfer = NULL;
+			bcmspi_disable_interrupt(BSPI_LR_INTERRUPTS_ALL);
+
+			if (priv->xfer_status) {
+				bcmspi_lr_clear(priv);
+			} else {
+				bcmspi_flush_prefetch_buffers(priv);
+
+				if (priv->cur_msg) {
+					priv->cur_msg->actual_length =
+						priv->actual_length;
+					priv->cur_msg->complete(
+						priv->cur_msg->context);
+					priv->cur_msg->status = 0;
+				}
+			}
+			priv->cur_msg = NULL;
+		}
+		bcmspi_clear_interrupt(status);
+		return IRQ_HANDLED;
+	}
+
+	if (priv->mspi_hw->mspi_status & 1) {
+		/* clear interrupt */
+		priv->mspi_hw->mspi_status &= ~1;
+		bcmspi_clear_interrupt(
+			BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK);
+
+		tasklet_schedule(&priv->tasklet);
+		return IRQ_HANDLED;
+	} else
+		return IRQ_NONE;
+}
+
+static void bcmspi_tasklet(unsigned long param)
+{
+	struct bcmspi_priv *priv = (void *)param;
+	struct list_head completed;
+	struct spi_message *msg;
+	unsigned long flags;
+
+	INIT_LIST_HEAD(&completed);
+	spin_lock_irqsave(&priv->lock, flags);
+
+	if (priv->next_udelay) {
+		udelay(priv->next_udelay);
+		priv->next_udelay = 0;
+	}
+
+	msg = priv->pos.msg;
+
+	read_from_hw(priv, &completed);
+	if (priv->cs_change) {
+		udelay(10);
+		priv->cs_change = 0;
+	}
+
+	write_to_hw(priv);
+
+	while (!list_empty(&completed)) {
+		msg = list_first_entry(&completed, struct spi_message, queue);
+		list_del(&msg->queue);
+		msg->status = 0;
+		if (msg->complete)
+			msg->complete(msg->context);
+	}
+	spin_unlock_irqrestore(&priv->lock, flags);
+}
+
+static void bcmspi_complete(void *arg)
+{
+	complete(arg);
+}
+
+static struct spi_master *default_master;
+
+int bcmspi_simple_transaction(struct bcmspi_parms *xp,
+	const void *tx_buf, int tx_len, void *rx_buf, int rx_len)
+{
+	DECLARE_COMPLETION_ONSTACK(fini);
+	struct spi_message m;
+	struct spi_transfer t_tx, t_rx;
+	struct spi_device spi;
+	int ret;
+
+	memset(&spi, 0, sizeof(spi));
+	spi.max_speed_hz = xp->speed_hz;
+	spi.chip_select = xp->chip_select;
+	spi.mode = xp->mode;
+	spi.bits_per_word = xp->bits_per_word;
+	spi.master = default_master;
+
+	spi_message_init(&m);
+	m.complete = bcmspi_complete;
+	m.context = &fini;
+	m.spi = &spi;
+
+	memset(&t_tx, 0, sizeof(t_tx));
+	memset(&t_rx, 0, sizeof(t_rx));
+	t_tx.tx_buf = tx_buf;
+	t_tx.len = tx_len;
+	t_rx.rx_buf = rx_buf;
+	t_rx.len = rx_len;
+
+	if (tx_len)
+		spi_message_add_tail(&t_tx, &m);
+	if (rx_len)
+		spi_message_add_tail(&t_rx, &m);
+
+	ret = bcmspi_transfer(&spi, &m);
+	if (!ret)
+		wait_for_completion(&fini);
+	return ret;
+}
+EXPORT_SYMBOL(bcmspi_simple_transaction);
+
+static void bcmspi_hw_init(struct bcmspi_priv *priv)
+{
+	priv->mspi_hw->spcr1_lsb = 0;
+	priv->mspi_hw->spcr1_msb = 0;
+	priv->mspi_hw->newqp = 0;
+	priv->mspi_hw->endqp = 0;
+	priv->mspi_hw->spcr2 = 0x20;	/* spifie */
+
+	bcmspi_hw_set_parms(priv, &bcmspi_default_parms_cs0);
+
+	if (!priv->bspi_hw)
+		return;
+
+	priv->bspi_enabled = 1;
+	bcmspi_disable_bspi(priv);
+
+#if CONFIG_BRCM_BSPI_MAJOR_VERS >= 4
+	/* Force a sane 1:1 mapping of BSPI address -> flash offset */
+	priv->bspi_hw->xor_enable = 1;
+	priv->bspi_hw->xor_value = 0;
+#endif
+
+	priv->bspi_hw->b0_ctrl = 0;
+	priv->bspi_hw->b1_ctrl = 0;
+}
+
+static void bcmspi_hw_uninit(struct bcmspi_priv *priv)
+{
+	priv->mspi_hw->spcr2 = 0x0;	/* disable irq and enable bits */
+	bcmspi_enable_bspi(priv);
+}
+
+static int bcmbspi_flash_type(struct bcmspi_priv *priv)
+{
+	char tx_buf[4];
+	unsigned char jedec_id[5] = {0};
+
+	/* command line override */
+	if (bspi_flash != BSPI_FLASH_TYPE_UNKNOWN)
+		return bspi_flash;
+
+	/* Read ID */
+	tx_buf[0] = OPCODE_RDID;
+	bcmspi_simple_transaction(&priv->last_parms, tx_buf, 1, &jedec_id, 5);
+
+	switch (jedec_id[0]) {
+	case 0x01: /* Spansion */
+	case 0xef:
+		bspi_flash = BSPI_FLASH_TYPE_SPANSION;
+		break;
+	case 0xc2: /* Macronix */
+		bspi_flash = BSPI_FLASH_TYPE_MACRONIX;
+		break;
+	case 0xbf: /* SST */
+		bspi_flash = BSPI_FLASH_TYPE_SST;
+		break;
+	case 0x89: /* Numonyx */
+		bspi_flash = BSPI_FLASH_TYPE_NUMONYX;
+		break;
+	default:
+		bspi_flash = BSPI_FLASH_TYPE_UNKNOWN;
+		break;
+	}
+	return bspi_flash;
+}
+
+static int bcmspi_set_quad_mode(struct bcmspi_priv *priv, int _enable)
+{
+	char tx_buf[4];
+	unsigned char cfg_reg, sts_reg;
+
+	switch (bcmbspi_flash_type(priv)) {
+	case BSPI_FLASH_TYPE_SPANSION:
+		/* RCR */
+		tx_buf[0] = OPCODE_RCR;
+		bcmspi_simple_transaction(&priv->last_parms,
+			tx_buf, 1, &cfg_reg, 1);
+		if (_enable)
+			cfg_reg |= 0x2;
+		else
+			cfg_reg &= ~0x2;
+		/* WREN */
+		tx_buf[0] = OPCODE_WREN;
+		bcmspi_simple_transaction(&priv->last_parms,
+			tx_buf, 1, NULL, 0);
+		/* WRR */
+		tx_buf[0] = OPCODE_WRR;
+		tx_buf[1] = 0; /* status register */
+		tx_buf[2] = cfg_reg; /* configuration register */
+		bcmspi_simple_transaction(&priv->last_parms,
+			tx_buf, 3, NULL, 0);
+		/* wait till ready */
+		do {
+			tx_buf[0] = OPCODE_RDSR;
+			bcmspi_simple_transaction(&priv->last_parms,
+				tx_buf, 1, &sts_reg, 1);
+			udelay(1);
+		} while (sts_reg & 1);
+		break;
+	case BSPI_FLASH_TYPE_MACRONIX:
+		/* RDSR */
+		tx_buf[0] = OPCODE_RDSR;
+		bcmspi_simple_transaction(&priv->last_parms,
+			tx_buf, 1, &cfg_reg, 1);
+		if (_enable)
+			cfg_reg |= 0x40;
+		else
+			cfg_reg &= ~0x40;
+		/* WREN */
+		tx_buf[0] = OPCODE_WREN;
+		bcmspi_simple_transaction(&priv->last_parms,
+			tx_buf, 1, NULL, 0);
+		/* WRSR */
+		tx_buf[0] = OPCODE_WRSR;
+		tx_buf[1] = cfg_reg; /* status register */
+		bcmspi_simple_transaction(&priv->last_parms,
+			tx_buf, 2, NULL, 0);
+		/* wait till ready */
+		do {
+			tx_buf[0] = OPCODE_RDSR;
+			bcmspi_simple_transaction(&priv->last_parms,
+				tx_buf, 1, &sts_reg, 1);
+			udelay(1);
+		} while (sts_reg & 1);
+		/* RDSR */
+		tx_buf[0] = OPCODE_RDSR;
+		bcmspi_simple_transaction(&priv->last_parms,
+			tx_buf, 1, &cfg_reg, 1);
+		break;
+	case BSPI_FLASH_TYPE_SST:
+	case BSPI_FLASH_TYPE_NUMONYX:
+		/* TODO - send Quad mode control command */
+		break;
+	default:
+		if (_enable)
+			dev_err(&priv->pdev->dev,
+				"Unrecognized flash type, no QUAD MODE support");
+		return _enable ? -1 : 0;
+	}
+
+	return 0;
+}
+
+static int bcmspi_enable_disable_4byte_addressing(struct bcmspi_priv *priv,
+						 int _enable)
+{
+	char tx_buf[4];
+	int ret = 0;
+
+	switch (bcmbspi_flash_type(priv)) {
+	case BSPI_FLASH_TYPE_SPANSION:
+		tx_buf[0] = OPCODE_BRWR;
+		if (_enable)
+			tx_buf[1] = BSPI_BR_EXTADD;
+		else
+			tx_buf[1] = 0;
+		ret = bcmspi_simple_transaction(&priv->last_parms, tx_buf, 2,
+						NULL, 0);
+		break;
+	case BSPI_FLASH_TYPE_SST:
+	case BSPI_FLASH_TYPE_NUMONYX:
+	case BSPI_FLASH_TYPE_MACRONIX:
+		/* enable write by sending WREN */
+		tx_buf[0] = OPCODE_WREN;
+		ret = bcmspi_simple_transaction(&priv->last_parms, tx_buf, 1,
+						NULL, 0);
+		if (ret != 0)
+			return ret;
+
+		if (_enable)
+			tx_buf[0] = OPCODE_EN4B;
+		else
+			tx_buf[0] = OPCODE_EX4B;
+		ret = bcmspi_simple_transaction(&priv->last_parms, tx_buf, 1,
+						NULL, 0);
+		break;
+	default:
+		if (_enable)
+			dev_err(&priv->pdev->dev,
+				"4-byte addressing not supported\n");
+		return _enable ? -1 : 0;
+	}
+
+	if (ret != 0)
+		dev_err(&priv->pdev->dev,
+			"Unable to enter/exit 4-byte address mode\n");
+
+	return ret;
+}
+
+static int bcmspi_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct brcmspi_platform_data *pdata;
+	struct bcmspi_priv *priv;
+	struct spi_master *master;
+	struct resource *res;
+	int ret;
+
+	DBG("bcmspi_probe\n");
+
+	pdata = (struct brcmspi_platform_data *)pdev->dev.platform_data;
+
+	BDEV_WR_RB(BCHP_BSPI_MAST_N_BOOT_CTRL, 1);
+	bcmspi_disable_interrupt(0xffffffff);
+	bcmspi_clear_interrupt(0xffffffff);
+	bcmspi_enable_interrupt(BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK);
+
+	master = spi_alloc_master(dev, sizeof(struct bcmspi_priv));
+	if (!master) {
+		dev_err(&pdev->dev, "error allocating spi_master\n");
+		return -ENOMEM;
+	}
+
+	priv = spi_master_get_devdata(master);
+
+	priv->pdev = pdev;
+	priv->state = STATE_IDLE;
+	priv->pos.msg = NULL;
+	priv->master = master;
+
+	master->bus_num = pdev->id;
+	master->num_chipselect = NUM_CHIPSELECT;
+	master->mode_bits = SPI_MODE_3;
+
+	master->setup = bcmspi_setup;
+	master->transfer = bcmspi_transfer;
+	master->cleanup = bcmspi_cleanup;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "can't get resource 0\n");
+		ret = -EIO;
+		goto err3;
+	}
+	/* MSPI register range */
+	priv->mspi_hw = (volatile void *)ioremap(res->start,
+		res->end - res->start);
+	if (!priv->mspi_hw) {
+		dev_err(&pdev->dev, "can't ioremap\n");
+		ret = -EIO;
+		goto err3;
+	}
+
+	/* IRQ */
+	priv->irq = platform_get_irq(pdev, 0);
+	if (priv->irq < 0) {
+		dev_err(&pdev->dev, "no IRQ defined\n");
+		ret = -ENODEV;
+		goto err2;
+	}
+
+	ret = request_irq(priv->irq, bcmspi_interrupt, 0, "spi_brcmstb", priv);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "unable to allocate IRQ\n");
+		goto err2;
+	}
+
+	/* BSPI register range (not supported on all platforms) */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	if (res && !nobspi) {
+		priv->bspi_hw = (volatile void *)ioremap(res->start,
+			res->end - res->start);
+		if (!priv->bspi_hw) {
+			dev_err(&pdev->dev, "can't ioremap BSPI range\n");
+			ret = -EIO;
+			goto err2;
+		}
+	} else
+		priv->bspi_hw = NULL;
+
+	/* BSPI_RAF register range */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+	if (res && !nobspi) {
+		priv->bspi_hw_raf = (volatile void *)ioremap(res->start,
+			res->end - res->start);
+		if (!priv->bspi_hw_raf) {
+			dev_err(&pdev->dev, "can't ioremap BSPI_RAF range\n");
+			ret = -EIO;
+			goto err2_1;
+		}
+	} else
+		priv->bspi_hw_raf = NULL;
+
+	bcmspi_hw_init(priv);
+	priv->curr_cs = -1;
+
+	priv->bspi_chip_select = (priv->bspi_hw && pdata) ? pdata->flash_cs : 0;
+#ifdef BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_nand_flash_boot_MASK
+	if (BDEV_RD(BCHP_SUN_TOP_CTRL_STRAP_VALUE_0) &
+		BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_nand_flash_boot_MASK) {
+		/* BSPI is disabled if the board is strapped for NAND */
+		priv->bspi_chip_select = 0;
+	}
+#endif /* BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_nand_flash_boot_MASK */
+
+
+	INIT_LIST_HEAD(&priv->msg_queue);
+	spin_lock_init(&priv->lock);
+
+	platform_set_drvdata(pdev, priv);
+
+	tasklet_init(&priv->tasklet, bcmspi_tasklet, (unsigned long)priv);
+
+	if (!default_master)
+		default_master = master;
+
+	/* default values - undefined */
+	priv->flex_mode.width =
+	priv->flex_mode.addrlen =
+	priv->flex_mode.hp = -1;
+
+	if (priv->bspi_chip_select) {
+		if (bspi_width == BSPI_WIDTH_4BIT ||
+		    ((BDEV_RD(BCHP_BSPI_STRAP_OVERRIDE_CTRL) &
+		      BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK))) {
+			if (bcmspi_set_quad_mode(priv, BSPI_WIDTH_4BIT))
+				bspi_width = BSPI_WIDTH_1BIT;
+			else
+				bspi_width = BSPI_WIDTH_4BIT;
+		}
+		bcmspi_set_mode(priv, bspi_width, bspi_addrlen, bspi_hp);
+	}
+
+	if (bcmspi_is_4_byte_mode(priv))
+		bcmspi_enable_disable_4byte_addressing(priv,
+						       BSPI_ADDRLEN_4BYTES);
+
+	ret = spi_register_master(master);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "can't register master\n");
+		goto err1;
+	}
+
+	return 0;
+
+err1:
+	bcmspi_hw_uninit(priv);
+	free_irq(priv->irq, priv);
+	iounmap(priv->bspi_hw_raf);
+err2_1:
+	iounmap(priv->bspi_hw);
+err2:
+	iounmap(priv->mspi_hw);
+err3:
+	spi_master_put(master);
+	return ret;
+}
+
+static int bcmspi_remove(struct platform_device *pdev)
+{
+	struct bcmspi_priv *priv = platform_get_drvdata(pdev);
+	unsigned long flags;
+
+	/* acquire lock when the MSPI is idle */
+	while (1) {
+		spin_lock_irqsave(&priv->lock, flags);
+		if (priv->state == STATE_IDLE)
+			break;
+		spin_unlock_irqrestore(&priv->lock, flags);
+		udelay(100);
+	}
+	priv->state = STATE_SHUTDOWN;
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	tasklet_kill(&priv->tasklet);
+	platform_set_drvdata(pdev, NULL);
+	bcmspi_hw_uninit(priv);
+	if (priv->bspi_hw_raf)
+		iounmap(priv->bspi_hw_raf);
+	if (priv->bspi_hw)
+		iounmap((const volatile void __iomem *)priv->bspi_hw);
+	free_irq(priv->irq, priv);
+	iounmap((const volatile void __iomem *)priv->mspi_hw);
+	spi_unregister_master(priv->master);
+
+	return 0;
+}
+
+static int bcmspi_suspend(struct device *dev)
+{
+	if (brcm_pm_deep_sleep()) {
+		struct bcmspi_priv *priv = dev_get_drvdata(dev);
+		unsigned long flags;
+		/* acquire lock when the MSPI is idle */
+		while (1) {
+			spin_lock_irqsave(&priv->lock, flags);
+			if (priv->state == STATE_IDLE) {
+				BDEV_WR_F_RB(HIF_MSPI_WRITE_LOCK, WriteLock,
+					     0);
+				priv->state = STATE_SUSPEND;
+				break;
+			}
+			spin_unlock_irqrestore(&priv->lock, flags);
+			if (priv->state == STATE_SHUTDOWN)
+				return -EIO;
+			udelay(1);
+		}
+		spin_unlock_irqrestore(&priv->lock, flags);
+
+		priv->s3_intr2_mask =
+			BDEV_RD(BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS);
+		priv->s3_strap_override_ctrl =
+			BDEV_RD(BCHP_BSPI_STRAP_OVERRIDE_CTRL);
+		bcmspi_hw_uninit(priv);
+	}
+	return 0;
+};
+
+static int bcmspi_resume(struct device *dev)
+{
+	if (brcm_pm_deep_sleep()) {
+		struct bcmspi_priv *priv = dev_get_drvdata(dev);
+		int curr_cs = priv->curr_cs;
+
+		int width = -1, addrlen = -1;
+		int ret = 0;
+		unsigned long flags;
+
+		spin_lock_irqsave(&priv->lock, flags);
+		priv->state = STATE_IDLE;
+		spin_unlock_irqrestore(&priv->lock, flags);
+
+		if (ret != 0)
+			return ret;
+
+		bcmspi_hw_init(priv);
+		priv->curr_cs = -1;
+		bcmspi_set_chip_select(priv, curr_cs);
+		BDEV_WR_RB(BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR,
+			   ~priv->s3_intr2_mask);
+
+		if (bcmspi_is_4_byte_mode(priv) ||
+		    (priv->s3_strap_override_ctrl &
+		     BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK))
+			addrlen = BSPI_ADDRLEN_4BYTES;
+
+		if (bspi_width == BSPI_WIDTH_4BIT ||
+		    (priv->s3_strap_override_ctrl &
+		     BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK)) {
+			width = BSPI_WIDTH_4BIT;
+
+			if (bcmspi_set_quad_mode(priv, width))
+				bspi_width = BSPI_WIDTH_1BIT;
+		}
+
+		bcmspi_set_mode(priv, width, addrlen, -1);
+		if (bcmspi_is_4_byte_mode(priv))
+			bcmspi_enable_disable_4byte_addressing(priv,
+					       BSPI_ADDRLEN_4BYTES);
+
+
+		BDEV_WR_RB(BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR,
+			   ~priv->s3_intr2_mask);
+		bcmspi_hw_init(priv);
+		bcmspi_set_mode(priv, -1, -1, -1);
+		priv->curr_cs = -1;
+		bcmspi_set_chip_select(priv, curr_cs);
+	}
+	return 0;
+}
+
+static const struct dev_pm_ops bcmspi_pm_ops = {
+	.suspend		= bcmspi_suspend,
+	.resume			= bcmspi_resume,
+};
+
+static struct platform_driver driver = {
+	.driver = {
+		.name = "spi_brcmstb",
+		.bus = &platform_bus_type,
+		.owner = THIS_MODULE,
+		.pm		= &bcmspi_pm_ops,
+	},
+	.probe = bcmspi_probe,
+	.remove = __devexit_p(bcmspi_remove),
+};
+
+static int __init bcmspi_spi_init(void)
+{
+	platform_driver_register(&driver);
+
+	return 0;
+}
+module_init(bcmspi_spi_init);
+
+static void __exit bcmspi_spi_exit(void)
+{
+	platform_driver_unregister(&driver);
+}
+module_exit(bcmspi_spi_exit);
+
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("MSPI/HIF SPI driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/staging/android/Kconfig b/drivers/staging/android/Kconfig
index eb1dee2..eddcc64 100644
--- a/drivers/staging/android/Kconfig
+++ b/drivers/staging/android/Kconfig
@@ -81,6 +81,8 @@ config ANDROID_ALARM_OLDDRV_COMPAT
 	  older out-of-tree drivers that use the Android Alarm
 	  in-kernel API. This will be removed eventually.
 
+source "drivers/staging/android/ion/Kconfig"
+
 endif # if ANDROID
 
 endmenu
diff --git a/drivers/staging/android/Makefile b/drivers/staging/android/Makefile
index 9b6c9ed..261f2e2 100644
--- a/drivers/staging/android/Makefile
+++ b/drivers/staging/android/Makefile
@@ -1,3 +1,5 @@
+obj-y					+= ion/
+
 obj-$(CONFIG_ANDROID_BINDER_IPC)	+= binder.o
 obj-$(CONFIG_ASHMEM)			+= ashmem.o
 obj-$(CONFIG_ANDROID_LOGGER)		+= logger.o
diff --git a/drivers/staging/android/ion/Kconfig b/drivers/staging/android/ion/Kconfig
new file mode 100644
index 0000000..0f8fec1
--- /dev/null
+++ b/drivers/staging/android/ion/Kconfig
@@ -0,0 +1,35 @@
+menuconfig ION
+	bool "Ion Memory Manager"
+	depends on HAVE_MEMBLOCK
+	select GENERIC_ALLOCATOR
+	select DMA_SHARED_BUFFER
+	---help---
+	  Chose this option to enable the ION Memory Manager,
+	  used by Android to efficiently allocate buffers
+	  from userspace that can be shared between drivers.
+	  If you're not using Android its probably safe to
+	  say N here.
+
+config ION_TEST
+	tristate "Ion Test Device"
+	depends on ION
+	help
+	  Choose this option to create a device that can be used to test the
+	  kernel and device side ION functions.
+
+config ION_DUMMY
+	bool "Dummy Ion driver"
+	depends on ION
+	help
+	  Provides a dummy ION driver that registers the
+	  /dev/ion device and some basic heaps. This can
+	  be used for testing the ION infrastructure if
+	  one doesn't have access to hardware drivers that
+	  use ION.
+
+config ION_TEGRA
+	tristate "Ion for Tegra"
+	depends on ARCH_TEGRA && ION
+	help
+	  Choose this option if you wish to use ion on an nVidia Tegra.
+
diff --git a/drivers/staging/android/ion/Makefile b/drivers/staging/android/ion/Makefile
new file mode 100644
index 0000000..b56fd2b
--- /dev/null
+++ b/drivers/staging/android/ion/Makefile
@@ -0,0 +1,10 @@
+obj-$(CONFIG_ION) +=	ion.o ion_heap.o ion_page_pool.o ion_system_heap.o \
+			ion_carveout_heap.o ion_chunk_heap.o ion_cma_heap.o
+obj-$(CONFIG_ION_TEST) += ion_test.o
+ifdef CONFIG_COMPAT
+obj-$(CONFIG_ION) += compat_ion.o
+endif
+
+obj-$(CONFIG_ION_DUMMY) += ion_dummy_driver.o
+obj-$(CONFIG_ION_TEGRA) += tegra/
+
diff --git a/drivers/staging/android/ion/compat_ion.c b/drivers/staging/android/ion/compat_ion.c
new file mode 100644
index 0000000..ee3a738
--- /dev/null
+++ b/drivers/staging/android/ion/compat_ion.c
@@ -0,0 +1,195 @@
+/*
+ * drivers/staging/android/ion/compat_ion.c
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/compat.h>
+#include <linux/fs.h>
+#include <linux/uaccess.h>
+
+#include "ion.h"
+#include "compat_ion.h"
+
+/* See drivers/staging/android/uapi/ion.h for the definition of these structs */
+struct compat_ion_allocation_data {
+	compat_size_t len;
+	compat_size_t align;
+	compat_uint_t heap_id_mask;
+	compat_uint_t flags;
+	compat_int_t handle;
+};
+
+struct compat_ion_custom_data {
+	compat_uint_t cmd;
+	compat_ulong_t arg;
+};
+
+struct compat_ion_handle_data {
+	compat_int_t handle;
+};
+
+#define COMPAT_ION_IOC_ALLOC	_IOWR(ION_IOC_MAGIC, 0, \
+				      struct compat_ion_allocation_data)
+#define COMPAT_ION_IOC_FREE	_IOWR(ION_IOC_MAGIC, 1, \
+				      struct compat_ion_handle_data)
+#define COMPAT_ION_IOC_CUSTOM	_IOWR(ION_IOC_MAGIC, 6, \
+				      struct compat_ion_custom_data)
+
+static int compat_get_ion_allocation_data(
+			struct compat_ion_allocation_data __user *data32,
+			struct ion_allocation_data __user *data)
+{
+	compat_size_t s;
+	compat_uint_t u;
+	compat_int_t i;
+	int err;
+
+	err = get_user(s, &data32->len);
+	err |= put_user(s, &data->len);
+	err |= get_user(s, &data32->align);
+	err |= put_user(s, &data->align);
+	err |= get_user(u, &data32->heap_id_mask);
+	err |= put_user(u, &data->heap_id_mask);
+	err |= get_user(u, &data32->flags);
+	err |= put_user(u, &data->flags);
+	err |= get_user(i, &data32->handle);
+	err |= put_user(i, &data->handle);
+
+	return err;
+}
+
+static int compat_get_ion_handle_data(
+			struct compat_ion_handle_data __user *data32,
+			struct ion_handle_data __user *data)
+{
+	compat_int_t i;
+	int err;
+
+	err = get_user(i, &data32->handle);
+	err |= put_user(i, &data->handle);
+
+	return err;
+}
+
+static int compat_put_ion_allocation_data(
+			struct compat_ion_allocation_data __user *data32,
+			struct ion_allocation_data __user *data)
+{
+	compat_size_t s;
+	compat_uint_t u;
+	compat_int_t i;
+	int err;
+
+	err = get_user(s, &data->len);
+	err |= put_user(s, &data32->len);
+	err |= get_user(s, &data->align);
+	err |= put_user(s, &data32->align);
+	err |= get_user(u, &data->heap_id_mask);
+	err |= put_user(u, &data32->heap_id_mask);
+	err |= get_user(u, &data->flags);
+	err |= put_user(u, &data32->flags);
+	err |= get_user(i, &data->handle);
+	err |= put_user(i, &data32->handle);
+
+	return err;
+}
+
+static int compat_get_ion_custom_data(
+			struct compat_ion_custom_data __user *data32,
+			struct ion_custom_data __user *data)
+{
+	compat_uint_t cmd;
+	compat_ulong_t arg;
+	int err;
+
+	err = get_user(cmd, &data32->cmd);
+	err |= put_user(cmd, &data->cmd);
+	err |= get_user(arg, &data32->arg);
+	err |= put_user(arg, &data->arg);
+
+	return err;
+};
+
+long compat_ion_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+	long ret;
+
+	if (!filp->f_op || !filp->f_op->unlocked_ioctl)
+		return -ENOTTY;
+
+	switch (cmd) {
+	case COMPAT_ION_IOC_ALLOC:
+	{
+		struct compat_ion_allocation_data __user *data32;
+		struct ion_allocation_data __user *data;
+		int err;
+
+		data32 = compat_ptr(arg);
+		data = compat_alloc_user_space(sizeof(*data));
+		if (data == NULL)
+			return -EFAULT;
+
+		err = compat_get_ion_allocation_data(data32, data);
+		if (err)
+			return err;
+		ret = filp->f_op->unlocked_ioctl(filp, ION_IOC_ALLOC,
+							(unsigned long)data);
+		err = compat_put_ion_allocation_data(data32, data);
+		return ret ? ret : err;
+	}
+	case COMPAT_ION_IOC_FREE:
+	{
+		struct compat_ion_handle_data __user *data32;
+		struct ion_handle_data __user *data;
+		int err;
+
+		data32 = compat_ptr(arg);
+		data = compat_alloc_user_space(sizeof(*data));
+		if (data == NULL)
+			return -EFAULT;
+
+		err = compat_get_ion_handle_data(data32, data);
+		if (err)
+			return err;
+
+		return filp->f_op->unlocked_ioctl(filp, ION_IOC_FREE,
+							(unsigned long)data);
+	}
+	case COMPAT_ION_IOC_CUSTOM: {
+		struct compat_ion_custom_data __user *data32;
+		struct ion_custom_data __user *data;
+		int err;
+
+		data32 = compat_ptr(arg);
+		data = compat_alloc_user_space(sizeof(*data));
+		if (data == NULL)
+			return -EFAULT;
+
+		err = compat_get_ion_custom_data(data32, data);
+		if (err)
+			return err;
+
+		return filp->f_op->unlocked_ioctl(filp, ION_IOC_CUSTOM,
+							(unsigned long)data);
+	}
+	case ION_IOC_SHARE:
+	case ION_IOC_MAP:
+	case ION_IOC_IMPORT:
+	case ION_IOC_SYNC:
+		return filp->f_op->unlocked_ioctl(filp, cmd,
+						(unsigned long)compat_ptr(arg));
+	default:
+		return -ENOIOCTLCMD;
+	}
+}
diff --git a/drivers/staging/android/ion/compat_ion.h b/drivers/staging/android/ion/compat_ion.h
new file mode 100644
index 0000000..c2ad589
--- /dev/null
+++ b/drivers/staging/android/ion/compat_ion.h
@@ -0,0 +1,30 @@
+/*
+
+ * drivers/staging/android/ion/compat_ion.h
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _LINUX_COMPAT_ION_H
+#define _LINUX_COMPAT_ION_H
+
+#if IS_ENABLED(CONFIG_COMPAT)
+
+long compat_ion_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
+
+#else
+
+#define compat_ion_ioctl  NULL
+
+#endif /* CONFIG_COMPAT */
+#endif /* _LINUX_COMPAT_ION_H */
diff --git a/drivers/staging/android/ion/ion.c b/drivers/staging/android/ion/ion.c
new file mode 100644
index 0000000..71ad9a6
--- /dev/null
+++ b/drivers/staging/android/ion/ion.c
@@ -0,0 +1,1574 @@
+/*
+
+ * drivers/staging/android/ion/ion.c
+ *
+ * Copyright (C) 2011 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/file.h>
+#include <linux/freezer.h>
+#include <linux/fs.h>
+#include <linux/anon_inodes.h>
+#include <linux/kthread.h>
+#include <linux/list.h>
+#include <linux/memblock.h>
+#include <linux/miscdevice.h>
+#include <linux/export.h>
+#include <linux/mm.h>
+#include <linux/mm_types.h>
+#include <linux/rbtree.h>
+#include <linux/slab.h>
+#include <linux/seq_file.h>
+#include <linux/uaccess.h>
+#include <linux/vmalloc.h>
+#include <linux/debugfs.h>
+#include <linux/dma-buf.h>
+#include <linux/idr.h>
+
+#include "ion.h"
+#include "ion_priv.h"
+#include "compat_ion.h"
+
+/**
+ * struct ion_device - the metadata of the ion device node
+ * @dev:		the actual misc device
+ * @buffers:		an rb tree of all the existing buffers
+ * @buffer_lock:	lock protecting the tree of buffers
+ * @lock:		rwsem protecting the tree of heaps and clients
+ * @heaps:		list of all the heaps in the system
+ * @user_clients:	list of all the clients created from userspace
+ */
+struct ion_device {
+	struct miscdevice dev;
+	struct rb_root buffers;
+	struct mutex buffer_lock;
+	struct rw_semaphore lock;
+	struct plist_head heaps;
+	long (*custom_ioctl) (struct ion_client *client, unsigned int cmd,
+			      unsigned long arg);
+	struct rb_root clients;
+	struct dentry *debug_root;
+};
+
+/**
+ * struct ion_client - a process/hw block local address space
+ * @node:		node in the tree of all clients
+ * @dev:		backpointer to ion device
+ * @handles:		an rb tree of all the handles in this client
+ * @idr:		an idr space for allocating handle ids
+ * @lock:		lock protecting the tree of handles
+ * @name:		used for debugging
+ * @task:		used for debugging
+ *
+ * A client represents a list of buffers this client may access.
+ * The mutex stored here is used to protect both handles tree
+ * as well as the handles themselves, and should be held while modifying either.
+ */
+struct ion_client {
+	struct rb_node node;
+	struct ion_device *dev;
+	struct rb_root handles;
+	struct idr idr;
+	struct mutex lock;
+	const char *name;
+	struct task_struct *task;
+	pid_t pid;
+	struct dentry *debug_root;
+};
+
+/**
+ * ion_handle - a client local reference to a buffer
+ * @ref:		reference count
+ * @client:		back pointer to the client the buffer resides in
+ * @buffer:		pointer to the buffer
+ * @node:		node in the client's handle rbtree
+ * @kmap_cnt:		count of times this client has mapped to kernel
+ * @id:			client-unique id allocated by client->idr
+ *
+ * Modifications to node, map_cnt or mapping should be protected by the
+ * lock in the client.  Other fields are never changed after initialization.
+ */
+struct ion_handle {
+	struct kref ref;
+	struct ion_client *client;
+	struct ion_buffer *buffer;
+	struct rb_node node;
+	unsigned int kmap_cnt;
+	int id;
+};
+
+bool ion_buffer_fault_user_mappings(struct ion_buffer *buffer)
+{
+	return (buffer->flags & ION_FLAG_CACHED) &&
+		!(buffer->flags & ION_FLAG_CACHED_NEEDS_SYNC);
+}
+
+bool ion_buffer_cached(struct ion_buffer *buffer)
+{
+	return !!(buffer->flags & ION_FLAG_CACHED);
+}
+
+static inline struct page *ion_buffer_page(struct page *page)
+{
+	return (struct page *)((unsigned long)page & ~(1UL));
+}
+
+static inline bool ion_buffer_page_is_dirty(struct page *page)
+{
+	return !!((unsigned long)page & 1UL);
+}
+
+static inline void ion_buffer_page_dirty(struct page **page)
+{
+	*page = (struct page *)((unsigned long)(*page) | 1UL);
+}
+
+static inline void ion_buffer_page_clean(struct page **page)
+{
+	*page = (struct page *)((unsigned long)(*page) & ~(1UL));
+}
+
+/* this function should only be called while dev->lock is held */
+static void ion_buffer_add(struct ion_device *dev,
+			   struct ion_buffer *buffer)
+{
+	struct rb_node **p = &dev->buffers.rb_node;
+	struct rb_node *parent = NULL;
+	struct ion_buffer *entry;
+
+	while (*p) {
+		parent = *p;
+		entry = rb_entry(parent, struct ion_buffer, node);
+
+		if (buffer < entry) {
+			p = &(*p)->rb_left;
+		} else if (buffer > entry) {
+			p = &(*p)->rb_right;
+		} else {
+			pr_err("%s: buffer already found.", __func__);
+			BUG();
+		}
+	}
+
+	rb_link_node(&buffer->node, parent, p);
+	rb_insert_color(&buffer->node, &dev->buffers);
+}
+
+/* this function should only be called while dev->lock is held */
+static struct ion_buffer *ion_buffer_create(struct ion_heap *heap,
+				     struct ion_device *dev,
+				     unsigned long len,
+				     unsigned long align,
+				     unsigned long flags)
+{
+	struct ion_buffer *buffer;
+	struct sg_table *table;
+	struct scatterlist *sg;
+	int i, ret;
+
+	buffer = kzalloc(sizeof(struct ion_buffer), GFP_KERNEL);
+	if (!buffer)
+		return ERR_PTR(-ENOMEM);
+
+	buffer->heap = heap;
+	buffer->flags = flags;
+	kref_init(&buffer->ref);
+
+	ret = heap->ops->allocate(heap, buffer, len, align, flags);
+
+	if (ret) {
+		if (!(heap->flags & ION_HEAP_FLAG_DEFER_FREE))
+			goto err2;
+
+		ion_heap_freelist_drain(heap, 0);
+		ret = heap->ops->allocate(heap, buffer, len, align,
+					  flags);
+		if (ret)
+			goto err2;
+	}
+
+	buffer->dev = dev;
+	buffer->size = len;
+
+	table = heap->ops->map_dma(heap, buffer);
+	if (WARN_ONCE(table == NULL,
+			"heap->ops->map_dma should return ERR_PTR on error"))
+		table = ERR_PTR(-EINVAL);
+	if (IS_ERR(table)) {
+		heap->ops->free(buffer);
+		kfree(buffer);
+		return ERR_PTR(PTR_ERR(table));
+	}
+	buffer->sg_table = table;
+	if (ion_buffer_fault_user_mappings(buffer)) {
+		int num_pages = PAGE_ALIGN(buffer->size) / PAGE_SIZE;
+		struct scatterlist *sg;
+		int i, j, k = 0;
+
+		buffer->pages = vmalloc(sizeof(struct page *) * num_pages);
+		if (!buffer->pages) {
+			ret = -ENOMEM;
+			goto err1;
+		}
+
+		for_each_sg(table->sgl, sg, table->nents, i) {
+			struct page *page = sg_page(sg);
+
+			for (j = 0; j < sg->length / PAGE_SIZE; j++)
+				buffer->pages[k++] = page++;
+		}
+
+		if (ret)
+			goto err;
+	}
+
+	buffer->dev = dev;
+	buffer->size = len;
+	INIT_LIST_HEAD(&buffer->vmas);
+	mutex_init(&buffer->lock);
+	/* this will set up dma addresses for the sglist -- it is not
+	   technically correct as per the dma api -- a specific
+	   device isn't really taking ownership here.  However, in practice on
+	   our systems the only dma_address space is physical addresses.
+	   Additionally, we can't afford the overhead of invalidating every
+	   allocation via dma_map_sg. The implicit contract here is that
+	   memory comming from the heaps is ready for dma, ie if it has a
+	   cached mapping that mapping has been invalidated */
+	for_each_sg(buffer->sg_table->sgl, sg, buffer->sg_table->nents, i)
+		sg_dma_address(sg) = sg_phys(sg);
+	mutex_lock(&dev->buffer_lock);
+	ion_buffer_add(dev, buffer);
+	mutex_unlock(&dev->buffer_lock);
+	return buffer;
+
+err:
+	heap->ops->unmap_dma(heap, buffer);
+	heap->ops->free(buffer);
+err1:
+	if (buffer->pages)
+		vfree(buffer->pages);
+err2:
+	kfree(buffer);
+	return ERR_PTR(ret);
+}
+
+void ion_buffer_destroy(struct ion_buffer *buffer)
+{
+	if (WARN_ON(buffer->kmap_cnt > 0))
+		buffer->heap->ops->unmap_kernel(buffer->heap, buffer);
+	buffer->heap->ops->unmap_dma(buffer->heap, buffer);
+	buffer->heap->ops->free(buffer);
+	if (buffer->pages)
+		vfree(buffer->pages);
+	kfree(buffer);
+}
+
+static void _ion_buffer_destroy(struct kref *kref)
+{
+	struct ion_buffer *buffer = container_of(kref, struct ion_buffer, ref);
+	struct ion_heap *heap = buffer->heap;
+	struct ion_device *dev = buffer->dev;
+
+	mutex_lock(&dev->buffer_lock);
+	rb_erase(&buffer->node, &dev->buffers);
+	mutex_unlock(&dev->buffer_lock);
+
+	if (heap->flags & ION_HEAP_FLAG_DEFER_FREE)
+		ion_heap_freelist_add(heap, buffer);
+	else
+		ion_buffer_destroy(buffer);
+}
+
+static void ion_buffer_get(struct ion_buffer *buffer)
+{
+	kref_get(&buffer->ref);
+}
+
+static int ion_buffer_put(struct ion_buffer *buffer)
+{
+	return kref_put(&buffer->ref, _ion_buffer_destroy);
+}
+
+static void ion_buffer_add_to_handle(struct ion_buffer *buffer)
+{
+	mutex_lock(&buffer->lock);
+	buffer->handle_count++;
+	mutex_unlock(&buffer->lock);
+}
+
+static void ion_buffer_remove_from_handle(struct ion_buffer *buffer)
+{
+	/*
+	 * when a buffer is removed from a handle, if it is not in
+	 * any other handles, copy the taskcomm and the pid of the
+	 * process it's being removed from into the buffer.  At this
+	 * point there will be no way to track what processes this buffer is
+	 * being used by, it only exists as a dma_buf file descriptor.
+	 * The taskcomm and pid can provide a debug hint as to where this fd
+	 * is in the system
+	 */
+	mutex_lock(&buffer->lock);
+	buffer->handle_count--;
+	BUG_ON(buffer->handle_count < 0);
+	if (!buffer->handle_count) {
+		struct task_struct *task;
+
+		task = current->group_leader;
+		get_task_comm(buffer->task_comm, task);
+		buffer->pid = task_pid_nr(task);
+	}
+	mutex_unlock(&buffer->lock);
+}
+
+static struct ion_handle *ion_handle_create(struct ion_client *client,
+				     struct ion_buffer *buffer)
+{
+	struct ion_handle *handle;
+
+	handle = kzalloc(sizeof(struct ion_handle), GFP_KERNEL);
+	if (!handle)
+		return ERR_PTR(-ENOMEM);
+	kref_init(&handle->ref);
+	RB_CLEAR_NODE(&handle->node);
+	handle->client = client;
+	ion_buffer_get(buffer);
+	ion_buffer_add_to_handle(buffer);
+	handle->buffer = buffer;
+
+	return handle;
+}
+
+static void ion_handle_kmap_put(struct ion_handle *);
+
+static void ion_handle_destroy(struct kref *kref)
+{
+	struct ion_handle *handle = container_of(kref, struct ion_handle, ref);
+	struct ion_client *client = handle->client;
+	struct ion_buffer *buffer = handle->buffer;
+
+	mutex_lock(&buffer->lock);
+	while (handle->kmap_cnt)
+		ion_handle_kmap_put(handle);
+	mutex_unlock(&buffer->lock);
+
+	idr_remove(&client->idr, handle->id);
+	if (!RB_EMPTY_NODE(&handle->node))
+		rb_erase(&handle->node, &client->handles);
+
+	ion_buffer_remove_from_handle(buffer);
+	ion_buffer_put(buffer);
+
+	kfree(handle);
+}
+
+struct ion_buffer *ion_handle_buffer(struct ion_handle *handle)
+{
+	return handle->buffer;
+}
+
+static void ion_handle_get(struct ion_handle *handle)
+{
+	kref_get(&handle->ref);
+}
+
+static int ion_handle_put(struct ion_handle *handle)
+{
+	struct ion_client *client = handle->client;
+	int ret;
+
+	mutex_lock(&client->lock);
+	ret = kref_put(&handle->ref, ion_handle_destroy);
+	mutex_unlock(&client->lock);
+
+	return ret;
+}
+
+static struct ion_handle *ion_handle_lookup(struct ion_client *client,
+					    struct ion_buffer *buffer)
+{
+	struct rb_node *n = client->handles.rb_node;
+
+	while (n) {
+		struct ion_handle *entry = rb_entry(n, struct ion_handle, node);
+		if (buffer < entry->buffer)
+			n = n->rb_left;
+		else if (buffer > entry->buffer)
+			n = n->rb_right;
+		else
+			return entry;
+	}
+	return ERR_PTR(-EINVAL);
+}
+
+static struct ion_handle *ion_handle_get_by_id(struct ion_client *client,
+						int id)
+{
+	struct ion_handle *handle;
+
+	mutex_lock(&client->lock);
+	handle = idr_find(&client->idr, id);
+	if (handle)
+		ion_handle_get(handle);
+	mutex_unlock(&client->lock);
+
+	return handle ? handle : ERR_PTR(-EINVAL);
+}
+
+static bool ion_handle_validate(struct ion_client *client,
+				struct ion_handle *handle)
+{
+	WARN_ON(!mutex_is_locked(&client->lock));
+	return (idr_find(&client->idr, handle->id) == handle);
+}
+
+static int ion_handle_add(struct ion_client *client, struct ion_handle *handle)
+{
+	int rc;
+	struct rb_node **p = &client->handles.rb_node;
+	struct rb_node *parent = NULL;
+	struct ion_handle *entry;
+
+	do {
+		int id;
+		rc = idr_pre_get(&client->idr, GFP_KERNEL);
+		if (!rc)
+			return -ENOMEM;
+		rc = idr_get_new_above(&client->idr, handle, 1, &id);
+		handle->id = id;
+	} while (rc == -EAGAIN);
+
+	if (rc < 0)
+		return rc;
+
+	while (*p) {
+		parent = *p;
+		entry = rb_entry(parent, struct ion_handle, node);
+
+		if (handle->buffer < entry->buffer)
+			p = &(*p)->rb_left;
+		else if (handle->buffer > entry->buffer)
+			p = &(*p)->rb_right;
+		else
+			WARN(1, "%s: buffer already found.", __func__);
+	}
+
+	rb_link_node(&handle->node, parent, p);
+	rb_insert_color(&handle->node, &client->handles);
+
+	return 0;
+}
+
+struct ion_handle *ion_alloc(struct ion_client *client, size_t len,
+			     size_t align, unsigned int heap_id_mask,
+			     unsigned int flags)
+{
+	struct ion_handle *handle;
+	struct ion_device *dev = client->dev;
+	struct ion_buffer *buffer = NULL;
+	struct ion_heap *heap;
+	int ret;
+
+	pr_debug("%s: len %zu align %zu heap_id_mask %u flags %x\n", __func__,
+		 len, align, heap_id_mask, flags);
+	/*
+	 * traverse the list of heaps available in this system in priority
+	 * order.  If the heap type is supported by the client, and matches the
+	 * request of the caller allocate from it.  Repeat until allocate has
+	 * succeeded or all heaps have been tried
+	 */
+	len = PAGE_ALIGN(len);
+
+	if (!len)
+		return ERR_PTR(-EINVAL);
+
+	down_read(&dev->lock);
+	plist_for_each_entry(heap, &dev->heaps, node) {
+		/* if the caller didn't specify this heap id */
+		if (!((1 << heap->id) & heap_id_mask))
+			continue;
+		buffer = ion_buffer_create(heap, dev, len, align, flags);
+		if (!IS_ERR(buffer))
+			break;
+	}
+	up_read(&dev->lock);
+
+	if (buffer == NULL)
+		return ERR_PTR(-ENODEV);
+
+	if (IS_ERR(buffer))
+		return ERR_PTR(PTR_ERR(buffer));
+
+	handle = ion_handle_create(client, buffer);
+
+	/*
+	 * ion_buffer_create will create a buffer with a ref_cnt of 1,
+	 * and ion_handle_create will take a second reference, drop one here
+	 */
+	ion_buffer_put(buffer);
+
+	if (IS_ERR(handle))
+		return handle;
+
+	mutex_lock(&client->lock);
+	ret = ion_handle_add(client, handle);
+	mutex_unlock(&client->lock);
+	if (ret) {
+		ion_handle_put(handle);
+		handle = ERR_PTR(ret);
+	}
+
+	return handle;
+}
+EXPORT_SYMBOL(ion_alloc);
+
+void ion_free(struct ion_client *client, struct ion_handle *handle)
+{
+	bool valid_handle;
+
+	BUG_ON(client != handle->client);
+
+	mutex_lock(&client->lock);
+	valid_handle = ion_handle_validate(client, handle);
+
+	if (!valid_handle) {
+		WARN(1, "%s: invalid handle passed to free.\n", __func__);
+		mutex_unlock(&client->lock);
+		return;
+	}
+	mutex_unlock(&client->lock);
+	ion_handle_put(handle);
+}
+EXPORT_SYMBOL(ion_free);
+
+int ion_phys(struct ion_client *client, struct ion_handle *handle,
+	     ion_phys_addr_t *addr, size_t *len)
+{
+	struct ion_buffer *buffer;
+	int ret;
+
+	mutex_lock(&client->lock);
+	if (!ion_handle_validate(client, handle)) {
+		mutex_unlock(&client->lock);
+		return -EINVAL;
+	}
+
+	buffer = handle->buffer;
+
+	if (!buffer->heap->ops->phys) {
+		pr_err("%s: ion_phys is not implemented by this heap.\n",
+		       __func__);
+		mutex_unlock(&client->lock);
+		return -ENODEV;
+	}
+	mutex_unlock(&client->lock);
+	ret = buffer->heap->ops->phys(buffer->heap, buffer, addr, len);
+	return ret;
+}
+EXPORT_SYMBOL(ion_phys);
+
+static void *ion_buffer_kmap_get(struct ion_buffer *buffer)
+{
+	void *vaddr;
+
+	if (buffer->kmap_cnt) {
+		buffer->kmap_cnt++;
+		return buffer->vaddr;
+	}
+	vaddr = buffer->heap->ops->map_kernel(buffer->heap, buffer);
+	if (WARN_ONCE(vaddr == NULL,
+			"heap->ops->map_kernel should return ERR_PTR on error"))
+		return ERR_PTR(-EINVAL);
+	if (IS_ERR(vaddr))
+		return vaddr;
+	buffer->vaddr = vaddr;
+	buffer->kmap_cnt++;
+	return vaddr;
+}
+
+static void *ion_handle_kmap_get(struct ion_handle *handle)
+{
+	struct ion_buffer *buffer = handle->buffer;
+	void *vaddr;
+
+	if (handle->kmap_cnt) {
+		handle->kmap_cnt++;
+		return buffer->vaddr;
+	}
+	vaddr = ion_buffer_kmap_get(buffer);
+	if (IS_ERR(vaddr))
+		return vaddr;
+	handle->kmap_cnt++;
+	return vaddr;
+}
+
+static void ion_buffer_kmap_put(struct ion_buffer *buffer)
+{
+	buffer->kmap_cnt--;
+	if (!buffer->kmap_cnt) {
+		buffer->heap->ops->unmap_kernel(buffer->heap, buffer);
+		buffer->vaddr = NULL;
+	}
+}
+
+static void ion_handle_kmap_put(struct ion_handle *handle)
+{
+	struct ion_buffer *buffer = handle->buffer;
+
+	handle->kmap_cnt--;
+	if (!handle->kmap_cnt)
+		ion_buffer_kmap_put(buffer);
+}
+
+void *ion_map_kernel(struct ion_client *client, struct ion_handle *handle)
+{
+	struct ion_buffer *buffer;
+	void *vaddr;
+
+	mutex_lock(&client->lock);
+	if (!ion_handle_validate(client, handle)) {
+		pr_err("%s: invalid handle passed to map_kernel.\n",
+		       __func__);
+		mutex_unlock(&client->lock);
+		return ERR_PTR(-EINVAL);
+	}
+
+	buffer = handle->buffer;
+
+	if (!handle->buffer->heap->ops->map_kernel) {
+		pr_err("%s: map_kernel is not implemented by this heap.\n",
+		       __func__);
+		mutex_unlock(&client->lock);
+		return ERR_PTR(-ENODEV);
+	}
+
+	mutex_lock(&buffer->lock);
+	vaddr = ion_handle_kmap_get(handle);
+	mutex_unlock(&buffer->lock);
+	mutex_unlock(&client->lock);
+	return vaddr;
+}
+EXPORT_SYMBOL(ion_map_kernel);
+
+void ion_unmap_kernel(struct ion_client *client, struct ion_handle *handle)
+{
+	struct ion_buffer *buffer;
+
+	mutex_lock(&client->lock);
+	buffer = handle->buffer;
+	mutex_lock(&buffer->lock);
+	ion_handle_kmap_put(handle);
+	mutex_unlock(&buffer->lock);
+	mutex_unlock(&client->lock);
+}
+EXPORT_SYMBOL(ion_unmap_kernel);
+
+static int ion_debug_client_show(struct seq_file *s, void *unused)
+{
+	struct ion_client *client = s->private;
+	struct rb_node *n;
+	size_t sizes[ION_NUM_HEAP_IDS] = {0};
+	const char *names[ION_NUM_HEAP_IDS] = {NULL};
+	int i;
+
+	mutex_lock(&client->lock);
+	for (n = rb_first(&client->handles); n; n = rb_next(n)) {
+		struct ion_handle *handle = rb_entry(n, struct ion_handle,
+						     node);
+		unsigned int id = handle->buffer->heap->id;
+
+		if (!names[id])
+			names[id] = handle->buffer->heap->name;
+		sizes[id] += handle->buffer->size;
+	}
+	mutex_unlock(&client->lock);
+
+	seq_printf(s, "%16.16s: %16.16s\n", "heap_name", "size_in_bytes");
+	for (i = 0; i < ION_NUM_HEAP_IDS; i++) {
+		if (!names[i])
+			continue;
+		seq_printf(s, "%16.16s: %16zu\n", names[i], sizes[i]);
+	}
+	return 0;
+}
+
+static int ion_debug_client_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, ion_debug_client_show, inode->i_private);
+}
+
+static const struct file_operations debug_client_fops = {
+	.open = ion_debug_client_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+};
+
+struct ion_client *ion_client_create(struct ion_device *dev,
+				     const char *name)
+{
+	struct ion_client *client;
+	struct task_struct *task;
+	struct rb_node **p;
+	struct rb_node *parent = NULL;
+	struct ion_client *entry;
+	char debug_name[64];
+	pid_t pid;
+
+	get_task_struct(current->group_leader);
+	task_lock(current->group_leader);
+	pid = task_pid_nr(current->group_leader);
+	/* don't bother to store task struct for kernel threads,
+	   they can't be killed anyway */
+	if (current->group_leader->flags & PF_KTHREAD) {
+		put_task_struct(current->group_leader);
+		task = NULL;
+	} else {
+		task = current->group_leader;
+	}
+	task_unlock(current->group_leader);
+
+	client = kzalloc(sizeof(struct ion_client), GFP_KERNEL);
+	if (!client) {
+		if (task)
+			put_task_struct(current->group_leader);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	client->dev = dev;
+	client->handles = RB_ROOT;
+	idr_init(&client->idr);
+	mutex_init(&client->lock);
+	client->name = name;
+	client->task = task;
+	client->pid = pid;
+
+	down_write(&dev->lock);
+	p = &dev->clients.rb_node;
+	while (*p) {
+		parent = *p;
+		entry = rb_entry(parent, struct ion_client, node);
+
+		if (client < entry)
+			p = &(*p)->rb_left;
+		else if (client > entry)
+			p = &(*p)->rb_right;
+	}
+	rb_link_node(&client->node, parent, p);
+	rb_insert_color(&client->node, &dev->clients);
+
+	snprintf(debug_name, 64, "%u", client->pid);
+	client->debug_root = debugfs_create_file(debug_name, 0664,
+						 dev->debug_root, client,
+						 &debug_client_fops);
+	up_write(&dev->lock);
+
+	return client;
+}
+EXPORT_SYMBOL(ion_client_create);
+
+void ion_client_destroy(struct ion_client *client)
+{
+	struct ion_device *dev = client->dev;
+	struct rb_node *n;
+
+	pr_debug("%s: %d\n", __func__, __LINE__);
+	while ((n = rb_first(&client->handles))) {
+		struct ion_handle *handle = rb_entry(n, struct ion_handle,
+						     node);
+		ion_handle_destroy(&handle->ref);
+	}
+
+	idr_remove_all(&client->idr);
+	idr_destroy(&client->idr);
+
+	down_write(&dev->lock);
+	if (client->task)
+		put_task_struct(client->task);
+	rb_erase(&client->node, &dev->clients);
+	debugfs_remove_recursive(client->debug_root);
+	up_write(&dev->lock);
+
+	kfree(client);
+}
+EXPORT_SYMBOL(ion_client_destroy);
+
+struct sg_table *ion_sg_table(struct ion_client *client,
+			      struct ion_handle *handle)
+{
+	struct ion_buffer *buffer;
+	struct sg_table *table;
+
+	mutex_lock(&client->lock);
+	if (!ion_handle_validate(client, handle)) {
+		pr_err("%s: invalid handle passed to map_dma.\n",
+		       __func__);
+		mutex_unlock(&client->lock);
+		return ERR_PTR(-EINVAL);
+	}
+	buffer = handle->buffer;
+	table = buffer->sg_table;
+	mutex_unlock(&client->lock);
+	return table;
+}
+EXPORT_SYMBOL(ion_sg_table);
+
+static void ion_buffer_sync_for_device(struct ion_buffer *buffer,
+				       struct device *dev,
+				       enum dma_data_direction direction);
+
+static struct sg_table *ion_map_dma_buf(struct dma_buf_attachment *attachment,
+					enum dma_data_direction direction)
+{
+	struct dma_buf *dmabuf = attachment->dmabuf;
+	struct ion_buffer *buffer = dmabuf->priv;
+
+	ion_buffer_sync_for_device(buffer, attachment->dev, direction);
+	return buffer->sg_table;
+}
+
+static void ion_unmap_dma_buf(struct dma_buf_attachment *attachment,
+			      struct sg_table *table,
+			      enum dma_data_direction direction)
+{
+}
+
+void ion_pages_sync_for_device(struct device *dev, struct page *page,
+		size_t size, enum dma_data_direction dir)
+{
+	struct scatterlist sg;
+
+	sg_init_table(&sg, 1);
+	sg_set_page(&sg, page, size, 0);
+	/*
+	 * This is not correct - sg_dma_address needs a dma_addr_t that is valid
+	 * for the the targeted device, but this works on the currently targeted
+	 * hardware.
+	 */
+	sg_dma_address(&sg) = page_to_phys(page);
+	dma_sync_sg_for_device(dev, &sg, 1, dir);
+}
+
+struct ion_vma_list {
+	struct list_head list;
+	struct vm_area_struct *vma;
+};
+
+static void ion_buffer_sync_for_device(struct ion_buffer *buffer,
+				       struct device *dev,
+				       enum dma_data_direction dir)
+{
+	struct ion_vma_list *vma_list;
+	int pages = PAGE_ALIGN(buffer->size) / PAGE_SIZE;
+	int i;
+
+	pr_debug("%s: syncing for device %s\n", __func__,
+		 dev ? dev_name(dev) : "null");
+
+	if (!ion_buffer_fault_user_mappings(buffer))
+		return;
+
+	mutex_lock(&buffer->lock);
+	for (i = 0; i < pages; i++) {
+		struct page *page = buffer->pages[i];
+
+		if (ion_buffer_page_is_dirty(page))
+			ion_pages_sync_for_device(dev, ion_buffer_page(page),
+							PAGE_SIZE, dir);
+
+		ion_buffer_page_clean(buffer->pages + i);
+	}
+	list_for_each_entry(vma_list, &buffer->vmas, list) {
+		struct vm_area_struct *vma = vma_list->vma;
+
+		zap_page_range(vma, vma->vm_start, vma->vm_end - vma->vm_start,
+			       NULL);
+	}
+	mutex_unlock(&buffer->lock);
+}
+
+static int ion_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
+{
+	struct ion_buffer *buffer = vma->vm_private_data;
+	int ret;
+
+	mutex_lock(&buffer->lock);
+	ion_buffer_page_dirty(buffer->pages + vmf->pgoff);
+
+	BUG_ON(!buffer->pages || !buffer->pages[vmf->pgoff]);
+	ret = vm_insert_page(vma, (unsigned long)vmf->virtual_address,
+			     ion_buffer_page(buffer->pages[vmf->pgoff]));
+	mutex_unlock(&buffer->lock);
+	if (ret)
+		return VM_FAULT_ERROR;
+
+	return VM_FAULT_NOPAGE;
+}
+
+static void ion_vm_open(struct vm_area_struct *vma)
+{
+	struct ion_buffer *buffer = vma->vm_private_data;
+	struct ion_vma_list *vma_list;
+
+	vma_list = kmalloc(sizeof(struct ion_vma_list), GFP_KERNEL);
+	if (!vma_list)
+		return;
+	vma_list->vma = vma;
+	mutex_lock(&buffer->lock);
+	list_add(&vma_list->list, &buffer->vmas);
+	mutex_unlock(&buffer->lock);
+	pr_debug("%s: adding %p\n", __func__, vma);
+}
+
+static void ion_vm_close(struct vm_area_struct *vma)
+{
+	struct ion_buffer *buffer = vma->vm_private_data;
+	struct ion_vma_list *vma_list, *tmp;
+
+	pr_debug("%s\n", __func__);
+	mutex_lock(&buffer->lock);
+	list_for_each_entry_safe(vma_list, tmp, &buffer->vmas, list) {
+		if (vma_list->vma != vma)
+			continue;
+		list_del(&vma_list->list);
+		kfree(vma_list);
+		pr_debug("%s: deleting %p\n", __func__, vma);
+		break;
+	}
+	mutex_unlock(&buffer->lock);
+}
+
+static struct vm_operations_struct ion_vma_ops = {
+	.open = ion_vm_open,
+	.close = ion_vm_close,
+	.fault = ion_vm_fault,
+};
+
+static int ion_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma)
+{
+	struct ion_buffer *buffer = dmabuf->priv;
+	int ret = 0;
+
+	if (!buffer->heap->ops->map_user) {
+		pr_err("%s: this heap does not define a method for mapping "
+		       "to userspace\n", __func__);
+		return -EINVAL;
+	}
+
+	if (ion_buffer_fault_user_mappings(buffer)) {
+		vma->vm_private_data = buffer;
+		vma->vm_ops = &ion_vma_ops;
+		ion_vm_open(vma);
+		return 0;
+	}
+
+	if (!(buffer->flags & ION_FLAG_CACHED))
+		vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+
+	mutex_lock(&buffer->lock);
+	/* now map it to userspace */
+	ret = buffer->heap->ops->map_user(buffer->heap, buffer, vma);
+	mutex_unlock(&buffer->lock);
+
+	if (ret)
+		pr_err("%s: failure mapping buffer to userspace\n",
+		       __func__);
+
+	return ret;
+}
+
+static void ion_dma_buf_release(struct dma_buf *dmabuf)
+{
+	struct ion_buffer *buffer = dmabuf->priv;
+	ion_buffer_put(buffer);
+}
+
+static void *ion_dma_buf_kmap(struct dma_buf *dmabuf, unsigned long offset)
+{
+	struct ion_buffer *buffer = dmabuf->priv;
+	return buffer->vaddr + offset * PAGE_SIZE;
+}
+
+static void ion_dma_buf_kunmap(struct dma_buf *dmabuf, unsigned long offset,
+			       void *ptr)
+{
+	return;
+}
+
+static int ion_dma_buf_begin_cpu_access(struct dma_buf *dmabuf, size_t start,
+					size_t len,
+					enum dma_data_direction direction)
+{
+	struct ion_buffer *buffer = dmabuf->priv;
+	void *vaddr;
+
+	if (!buffer->heap->ops->map_kernel) {
+		pr_err("%s: map kernel is not implemented by this heap.\n",
+		       __func__);
+		return -ENODEV;
+	}
+
+	mutex_lock(&buffer->lock);
+	vaddr = ion_buffer_kmap_get(buffer);
+	mutex_unlock(&buffer->lock);
+	if (IS_ERR(vaddr))
+		return PTR_ERR(vaddr);
+	return 0;
+}
+
+static void ion_dma_buf_end_cpu_access(struct dma_buf *dmabuf, size_t start,
+				       size_t len,
+				       enum dma_data_direction direction)
+{
+	struct ion_buffer *buffer = dmabuf->priv;
+
+	mutex_lock(&buffer->lock);
+	ion_buffer_kmap_put(buffer);
+	mutex_unlock(&buffer->lock);
+}
+
+static struct dma_buf_ops dma_buf_ops = {
+	.map_dma_buf = ion_map_dma_buf,
+	.unmap_dma_buf = ion_unmap_dma_buf,
+	.mmap = ion_mmap,
+	.release = ion_dma_buf_release,
+	.begin_cpu_access = ion_dma_buf_begin_cpu_access,
+	.end_cpu_access = ion_dma_buf_end_cpu_access,
+	.kmap_atomic = ion_dma_buf_kmap,
+	.kunmap_atomic = ion_dma_buf_kunmap,
+	.kmap = ion_dma_buf_kmap,
+	.kunmap = ion_dma_buf_kunmap,
+};
+
+struct dma_buf *ion_share_dma_buf(struct ion_client *client,
+						struct ion_handle *handle)
+{
+	struct ion_buffer *buffer;
+	struct dma_buf *dmabuf;
+	bool valid_handle;
+
+	mutex_lock(&client->lock);
+	valid_handle = ion_handle_validate(client, handle);
+	if (!valid_handle) {
+		WARN(1, "%s: invalid handle passed to share.\n", __func__);
+		mutex_unlock(&client->lock);
+		return ERR_PTR(-EINVAL);
+	}
+	buffer = handle->buffer;
+	ion_buffer_get(buffer);
+	mutex_unlock(&client->lock);
+
+	dmabuf = dma_buf_export(buffer, &dma_buf_ops, buffer->size, O_RDWR);
+	if (IS_ERR(dmabuf)) {
+		ion_buffer_put(buffer);
+		return dmabuf;
+	}
+
+	return dmabuf;
+}
+EXPORT_SYMBOL(ion_share_dma_buf);
+
+int ion_share_dma_buf_fd(struct ion_client *client, struct ion_handle *handle)
+{
+	struct dma_buf *dmabuf;
+	int fd;
+
+	dmabuf = ion_share_dma_buf(client, handle);
+	if (IS_ERR(dmabuf))
+		return PTR_ERR(dmabuf);
+
+	fd = dma_buf_fd(dmabuf, O_CLOEXEC);
+	if (fd < 0)
+		dma_buf_put(dmabuf);
+
+	return fd;
+}
+EXPORT_SYMBOL(ion_share_dma_buf_fd);
+
+struct ion_handle *ion_import_dma_buf(struct ion_client *client, int fd)
+{
+	struct dma_buf *dmabuf;
+	struct ion_buffer *buffer;
+	struct ion_handle *handle;
+	int ret;
+
+	dmabuf = dma_buf_get(fd);
+	if (IS_ERR(dmabuf))
+		return ERR_PTR(PTR_ERR(dmabuf));
+	/* if this memory came from ion */
+
+	if (dmabuf->ops != &dma_buf_ops) {
+		pr_err("%s: can not import dmabuf from another exporter\n",
+		       __func__);
+		dma_buf_put(dmabuf);
+		return ERR_PTR(-EINVAL);
+	}
+	buffer = dmabuf->priv;
+
+	mutex_lock(&client->lock);
+	/* if a handle exists for this buffer just take a reference to it */
+	handle = ion_handle_lookup(client, buffer);
+	if (!IS_ERR(handle)) {
+		ion_handle_get(handle);
+		mutex_unlock(&client->lock);
+		goto end;
+	}
+	mutex_unlock(&client->lock);
+
+	handle = ion_handle_create(client, buffer);
+	if (IS_ERR(handle))
+		goto end;
+
+	mutex_lock(&client->lock);
+	ret = ion_handle_add(client, handle);
+	mutex_unlock(&client->lock);
+	if (ret) {
+		ion_handle_put(handle);
+		handle = ERR_PTR(ret);
+	}
+
+end:
+	dma_buf_put(dmabuf);
+	return handle;
+}
+EXPORT_SYMBOL(ion_import_dma_buf);
+
+static int ion_sync_for_device(struct ion_client *client, int fd)
+{
+	struct dma_buf *dmabuf;
+	struct ion_buffer *buffer;
+
+	dmabuf = dma_buf_get(fd);
+	if (IS_ERR(dmabuf))
+		return PTR_ERR(dmabuf);
+
+	/* if this memory came from ion */
+	if (dmabuf->ops != &dma_buf_ops) {
+		pr_err("%s: can not sync dmabuf from another exporter\n",
+		       __func__);
+		dma_buf_put(dmabuf);
+		return -EINVAL;
+	}
+	buffer = dmabuf->priv;
+
+	dma_sync_sg_for_device(NULL, buffer->sg_table->sgl,
+			       buffer->sg_table->nents, DMA_BIDIRECTIONAL);
+	dma_buf_put(dmabuf);
+	return 0;
+}
+
+/* fix up the cases where the ioctl direction bits are incorrect */
+static unsigned int ion_ioctl_dir(unsigned int cmd)
+{
+	switch (cmd) {
+	case ION_IOC_SYNC:
+	case ION_IOC_FREE:
+	case ION_IOC_CUSTOM:
+		return _IOC_WRITE;
+	default:
+		return _IOC_DIR(cmd);
+	}
+}
+
+static long ion_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+	struct ion_client *client = filp->private_data;
+	struct ion_device *dev = client->dev;
+	struct ion_handle *cleanup_handle = NULL;
+	int ret = 0;
+	unsigned int dir;
+
+	union {
+		struct ion_fd_data fd;
+		struct ion_allocation_data allocation;
+		struct ion_handle_data handle;
+		struct ion_custom_data custom;
+		struct ion_phys_data phys;
+	} data;
+
+	dir = ion_ioctl_dir(cmd);
+
+	if (_IOC_SIZE(cmd) > sizeof(data))
+		return -EINVAL;
+
+	if (dir & _IOC_WRITE)
+		if (copy_from_user(&data, (void __user *)arg, _IOC_SIZE(cmd)))
+			return -EFAULT;
+
+	switch (cmd) {
+	case ION_IOC_ALLOC:
+	{
+		struct ion_handle *handle;
+
+		handle = ion_alloc(client, data.allocation.len,
+						data.allocation.align,
+						data.allocation.heap_id_mask,
+						data.allocation.flags);
+		if (IS_ERR(handle))
+			return PTR_ERR(handle);
+
+		data.allocation.handle = handle->id;
+
+		cleanup_handle = handle;
+		break;
+	}
+	case ION_IOC_FREE:
+	{
+		struct ion_handle *handle;
+
+		handle = ion_handle_get_by_id(client, data.handle.handle);
+		if (IS_ERR(handle))
+			return PTR_ERR(handle);
+		ion_free(client, handle);
+		ion_handle_put(handle);
+		break;
+	}
+	case ION_IOC_SHARE:
+	case ION_IOC_MAP:
+	{
+		struct ion_handle *handle;
+
+		handle = ion_handle_get_by_id(client, data.handle.handle);
+		if (IS_ERR(handle))
+			return PTR_ERR(handle);
+		data.fd.fd = ion_share_dma_buf_fd(client, handle);
+		ion_handle_put(handle);
+		if (data.fd.fd < 0)
+			ret = data.fd.fd;
+		break;
+	}
+	case ION_IOC_IMPORT:
+	{
+		struct ion_handle *handle;
+		handle = ion_import_dma_buf(client, data.fd.fd);
+		if (IS_ERR(handle))
+			ret = PTR_ERR(handle);
+		else
+			data.handle.handle = handle->id;
+		break;
+	}
+	case ION_IOC_SYNC:
+	{
+		ret = ion_sync_for_device(client, data.fd.fd);
+		break;
+	}
+	case ION_IOC_CUSTOM:
+	{
+		if (!dev->custom_ioctl)
+			return -ENOTTY;
+		ret = dev->custom_ioctl(client, data.custom.cmd,
+						data.custom.arg);
+		break;
+	}
+	case ION_IOC_PHYS:
+	{
+		struct ion_handle *handle;
+		ion_phys_addr_t addr;
+		size_t len;
+
+		handle = ion_handle_get_by_id(client, data.phys.handle);
+		if (IS_ERR(handle))
+			return PTR_ERR(handle);
+		ret = ion_phys(client, handle, &addr, &len);
+		ion_handle_put(handle);
+		if (ret == 0) {
+			data.phys.addr = addr;
+			data.phys.len = len;
+		}
+		break;
+	}
+	default:
+		return -ENOTTY;
+	}
+
+	if (dir & _IOC_READ) {
+		if (copy_to_user((void __user *)arg, &data, _IOC_SIZE(cmd))) {
+			if (cleanup_handle)
+				ion_free(client, cleanup_handle);
+			return -EFAULT;
+		}
+	}
+	return ret;
+}
+
+static int ion_release(struct inode *inode, struct file *file)
+{
+	struct ion_client *client = file->private_data;
+
+	pr_debug("%s: %d\n", __func__, __LINE__);
+	ion_client_destroy(client);
+	return 0;
+}
+
+static int ion_open(struct inode *inode, struct file *file)
+{
+	struct miscdevice *miscdev = file->private_data;
+	struct ion_device *dev = container_of(miscdev, struct ion_device, dev);
+	struct ion_client *client;
+
+	pr_debug("%s: %d\n", __func__, __LINE__);
+	client = ion_client_create(dev, "user");
+	if (IS_ERR(client))
+		return PTR_ERR(client);
+	file->private_data = client;
+
+	return 0;
+}
+
+static const struct file_operations ion_fops = {
+	.owner          = THIS_MODULE,
+	.open           = ion_open,
+	.release        = ion_release,
+	.unlocked_ioctl = ion_ioctl,
+	.compat_ioctl   = compat_ion_ioctl,
+};
+
+static size_t ion_debug_heap_total(struct ion_client *client,
+				   unsigned int id)
+{
+	size_t size = 0;
+	struct rb_node *n;
+
+	mutex_lock(&client->lock);
+	for (n = rb_first(&client->handles); n; n = rb_next(n)) {
+		struct ion_handle *handle = rb_entry(n,
+						     struct ion_handle,
+						     node);
+		if (handle->buffer->heap->id == id)
+			size += handle->buffer->size;
+	}
+	mutex_unlock(&client->lock);
+	return size;
+}
+
+static int ion_debug_heap_show(struct seq_file *s, void *unused)
+{
+	struct ion_heap *heap = s->private;
+	struct ion_device *dev = heap->dev;
+	struct rb_node *n;
+	size_t total_size = 0;
+	size_t total_orphaned_size = 0;
+
+	seq_printf(s, "%16.s %16.s %16.s\n", "client", "pid", "size");
+	seq_printf(s, "----------------------------------------------------\n");
+
+	for (n = rb_first(&dev->clients); n; n = rb_next(n)) {
+		struct ion_client *client = rb_entry(n, struct ion_client,
+						     node);
+		size_t size = ion_debug_heap_total(client, heap->id);
+		if (!size)
+			continue;
+		if (client->task) {
+			char task_comm[TASK_COMM_LEN];
+
+			get_task_comm(task_comm, client->task);
+			seq_printf(s, "%16.s %16u %16zu\n", task_comm,
+				   client->pid, size);
+		} else {
+			seq_printf(s, "%16.s %16u %16zu\n", client->name,
+				   client->pid, size);
+		}
+	}
+	seq_printf(s, "----------------------------------------------------\n");
+	seq_printf(s, "orphaned allocations (info is from last known client):"
+		   "\n");
+	mutex_lock(&dev->buffer_lock);
+	for (n = rb_first(&dev->buffers); n; n = rb_next(n)) {
+		struct ion_buffer *buffer = rb_entry(n, struct ion_buffer,
+						     node);
+		if (buffer->heap->id != heap->id)
+			continue;
+		total_size += buffer->size;
+		if (!buffer->handle_count) {
+			seq_printf(s, "%16.s %16u %16zu %d %d\n",
+				   buffer->task_comm, buffer->pid,
+				   buffer->size, buffer->kmap_cnt,
+				   atomic_read(&buffer->ref.refcount));
+			total_orphaned_size += buffer->size;
+		}
+	}
+	mutex_unlock(&dev->buffer_lock);
+	seq_printf(s, "----------------------------------------------------\n");
+	seq_printf(s, "%16.s %16zu\n", "total orphaned",
+		   total_orphaned_size);
+	seq_printf(s, "%16.s %16zu\n", "total ", total_size);
+	if (heap->flags & ION_HEAP_FLAG_DEFER_FREE)
+		seq_printf(s, "%16.s %16zu\n", "deferred free",
+				heap->free_list_size);
+	seq_printf(s, "----------------------------------------------------\n");
+
+	if (heap->debug_show)
+		heap->debug_show(heap, s, unused);
+
+	return 0;
+}
+
+static int ion_debug_heap_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, ion_debug_heap_show, inode->i_private);
+}
+
+static const struct file_operations debug_heap_fops = {
+	.open = ion_debug_heap_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+};
+
+#ifdef DEBUG_HEAP_SHRINKER
+static int debug_shrink_set(void *data, u64 val)
+{
+	struct ion_heap *heap = data;
+	struct shrink_control sc;
+	int objs;
+
+	sc.gfp_mask = -1;
+	sc.nr_to_scan = 0;
+
+	if (!val)
+		return 0;
+
+	objs = heap->shrinker.shrink(&heap->shrinker, &sc);
+	sc.nr_to_scan = objs;
+
+	heap->shrinker.shrink(&heap->shrinker, &sc);
+	return 0;
+}
+
+static int debug_shrink_get(void *data, u64 *val)
+{
+	struct ion_heap *heap = data;
+	struct shrink_control sc;
+	int objs;
+
+	sc.gfp_mask = -1;
+	sc.nr_to_scan = 0;
+
+	objs = heap->shrinker.shrink(&heap->shrinker, &sc);
+	*val = objs;
+	return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(debug_shrink_fops, debug_shrink_get,
+			debug_shrink_set, "%llu\n");
+#endif
+
+void ion_device_add_heap(struct ion_device *dev, struct ion_heap *heap)
+{
+	if (!heap->ops->allocate || !heap->ops->free || !heap->ops->map_dma ||
+	    !heap->ops->unmap_dma)
+		pr_err("%s: can not add heap with invalid ops struct.\n",
+		       __func__);
+
+	if (heap->flags & ION_HEAP_FLAG_DEFER_FREE)
+		ion_heap_init_deferred_free(heap);
+
+	heap->dev = dev;
+	down_write(&dev->lock);
+	/* use negative heap->id to reverse the priority -- when traversing
+	   the list later attempt higher id numbers first */
+	plist_node_init(&heap->node, -heap->id);
+	plist_add(&heap->node, &dev->heaps);
+	debugfs_create_file(heap->name, 0664, dev->debug_root, heap,
+			    &debug_heap_fops);
+#ifdef DEBUG_HEAP_SHRINKER
+	if (heap->shrinker.shrink) {
+		char debug_name[64];
+
+		snprintf(debug_name, 64, "%s_shrink", heap->name);
+		debugfs_create_file(debug_name, 0644, dev->debug_root, heap,
+				    &debug_shrink_fops);
+	}
+#endif
+	up_write(&dev->lock);
+}
+EXPORT_SYMBOL(ion_device_add_heap);
+
+struct ion_device *ion_device_create(long (*custom_ioctl)
+				     (struct ion_client *client,
+				      unsigned int cmd,
+				      unsigned long arg))
+{
+	struct ion_device *idev;
+	int ret;
+
+	idev = kzalloc(sizeof(struct ion_device), GFP_KERNEL);
+	if (!idev)
+		return ERR_PTR(-ENOMEM);
+
+	idev->dev.minor = MISC_DYNAMIC_MINOR;
+	idev->dev.name = "ion";
+	idev->dev.fops = &ion_fops;
+	idev->dev.parent = NULL;
+	ret = misc_register(&idev->dev);
+	if (ret) {
+		pr_err("ion: failed to register misc device.\n");
+		return ERR_PTR(ret);
+	}
+
+	idev->debug_root = debugfs_create_dir("ion", NULL);
+	if (!idev->debug_root)
+		pr_err("ion: failed to create debug files.\n");
+
+	idev->custom_ioctl = custom_ioctl;
+	idev->buffers = RB_ROOT;
+	mutex_init(&idev->buffer_lock);
+	init_rwsem(&idev->lock);
+	plist_head_init(&idev->heaps);
+	idev->clients = RB_ROOT;
+	return idev;
+}
+EXPORT_SYMBOL(ion_device_create);
+
+void ion_device_destroy(struct ion_device *dev)
+{
+	misc_deregister(&dev->dev);
+	/* XXX need to free the heaps and clients ? */
+	kfree(dev);
+}
+EXPORT_SYMBOL(ion_device_destroy);
+
+void __init ion_reserve(struct ion_platform_data *data)
+{
+	int i;
+
+	for (i = 0; i < data->nr; i++) {
+		if (data->heaps[i].size == 0)
+			continue;
+
+		if (data->heaps[i].base == 0) {
+			phys_addr_t paddr;
+			paddr = memblock_alloc_base(data->heaps[i].size,
+						    data->heaps[i].align,
+						    MEMBLOCK_ALLOC_ANYWHERE);
+			if (!paddr) {
+				pr_err("%s: error allocating memblock for "
+				       "heap %d\n",
+					__func__, i);
+				continue;
+			}
+			data->heaps[i].base = paddr;
+		} else {
+			int ret = memblock_reserve(data->heaps[i].base,
+					       data->heaps[i].size);
+			if (ret)
+				pr_err("memblock reserve of %zx@%lx failed\n",
+				       data->heaps[i].size,
+				       data->heaps[i].base);
+		}
+		pr_info("%s: %s reserved base %lx size %zu\n", __func__,
+			data->heaps[i].name,
+			data->heaps[i].base,
+			data->heaps[i].size);
+	}
+}
diff --git a/drivers/staging/android/ion/ion.h b/drivers/staging/android/ion/ion.h
new file mode 100644
index 0000000..dcd2a0c
--- /dev/null
+++ b/drivers/staging/android/ion/ion.h
@@ -0,0 +1,204 @@
+/*
+ * drivers/staging/android/ion/ion.h
+ *
+ * Copyright (C) 2011 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _LINUX_ION_H
+#define _LINUX_ION_H
+
+#include <linux/types.h>
+
+#include "../uapi/ion.h"
+
+struct ion_handle;
+struct ion_device;
+struct ion_heap;
+struct ion_mapper;
+struct ion_client;
+struct ion_buffer;
+
+/* This should be removed some day when phys_addr_t's are fully
+   plumbed in the kernel, and all instances of ion_phys_addr_t should
+   be converted to phys_addr_t.  For the time being many kernel interfaces
+   do not accept phys_addr_t's that would have to */
+#define ion_phys_addr_t unsigned long
+
+/**
+ * struct ion_platform_heap - defines a heap in the given platform
+ * @type:	type of the heap from ion_heap_type enum
+ * @id:		unique identifier for heap.  When allocating higher numbers
+ *		will be allocated from first.  At allocation these are passed
+ *		as a bit mask and therefore can not exceed ION_NUM_HEAP_IDS.
+ * @name:	used for debug purposes
+ * @base:	base address of heap in physical memory if applicable
+ * @size:	size of the heap in bytes if applicable
+ * @align:	required alignment in physical memory if applicable
+ * @priv:	private info passed from the board file
+ *
+ * Provided by the board file.
+ */
+struct ion_platform_heap {
+	enum ion_heap_type type;
+	unsigned int id;
+	const char *name;
+	ion_phys_addr_t base;
+	size_t size;
+	ion_phys_addr_t align;
+	void *priv;
+};
+
+/**
+ * struct ion_platform_data - array of platform heaps passed from board file
+ * @nr:		number of structures in the array
+ * @heaps:	array of platform_heap structions
+ *
+ * Provided by the board file in the form of platform data to a platform device.
+ */
+struct ion_platform_data {
+	int nr;
+	struct ion_platform_heap *heaps;
+};
+
+/**
+ * ion_reserve() - reserve memory for ion heaps if applicable
+ * @data:	platform data specifying starting physical address and
+ *		size
+ *
+ * Calls memblock reserve to set aside memory for heaps that are
+ * located at specific memory addresses or of specfic sizes not
+ * managed by the kernel
+ */
+void ion_reserve(struct ion_platform_data *data);
+
+/**
+ * ion_client_create() -  allocate a client and returns it
+ * @dev:		the global ion device
+ * @heap_type_mask:	mask of heaps this client can allocate from
+ * @name:		used for debugging
+ */
+struct ion_client *ion_client_create(struct ion_device *dev,
+				     const char *name);
+
+/**
+ * ion_client_destroy() -  free's a client and all it's handles
+ * @client:	the client
+ *
+ * Free the provided client and all it's resources including
+ * any handles it is holding.
+ */
+void ion_client_destroy(struct ion_client *client);
+
+/**
+ * ion_alloc - allocate ion memory
+ * @client:		the client
+ * @len:		size of the allocation
+ * @align:		requested allocation alignment, lots of hardware blocks
+ *			have alignment requirements of some kind
+ * @heap_id_mask:	mask of heaps to allocate from, if multiple bits are set
+ *			heaps will be tried in order from highest to lowest
+ *			id
+ * @flags:		heap flags, the low 16 bits are consumed by ion, the
+ *			high 16 bits are passed on to the respective heap and
+ *			can be heap custom
+ *
+ * Allocate memory in one of the heaps provided in heap mask and return
+ * an opaque handle to it.
+ */
+struct ion_handle *ion_alloc(struct ion_client *client, size_t len,
+			     size_t align, unsigned int heap_id_mask,
+			     unsigned int flags);
+
+/**
+ * ion_free - free a handle
+ * @client:	the client
+ * @handle:	the handle to free
+ *
+ * Free the provided handle.
+ */
+void ion_free(struct ion_client *client, struct ion_handle *handle);
+
+/**
+ * ion_phys - returns the physical address and len of a handle
+ * @client:	the client
+ * @handle:	the handle
+ * @addr:	a pointer to put the address in
+ * @len:	a pointer to put the length in
+ *
+ * This function queries the heap for a particular handle to get the
+ * handle's physical address.  It't output is only correct if
+ * a heap returns physically contiguous memory -- in other cases
+ * this api should not be implemented -- ion_sg_table should be used
+ * instead.  Returns -EINVAL if the handle is invalid.  This has
+ * no implications on the reference counting of the handle --
+ * the returned value may not be valid if the caller is not
+ * holding a reference.
+ */
+int ion_phys(struct ion_client *client, struct ion_handle *handle,
+	     ion_phys_addr_t *addr, size_t *len);
+
+/**
+ * ion_map_dma - return an sg_table describing a handle
+ * @client:	the client
+ * @handle:	the handle
+ *
+ * This function returns the sg_table describing
+ * a particular ion handle.
+ */
+struct sg_table *ion_sg_table(struct ion_client *client,
+			      struct ion_handle *handle);
+
+/**
+ * ion_map_kernel - create mapping for the given handle
+ * @client:	the client
+ * @handle:	handle to map
+ *
+ * Map the given handle into the kernel and return a kernel address that
+ * can be used to access this address.
+ */
+void *ion_map_kernel(struct ion_client *client, struct ion_handle *handle);
+
+/**
+ * ion_unmap_kernel() - destroy a kernel mapping for a handle
+ * @client:	the client
+ * @handle:	handle to unmap
+ */
+void ion_unmap_kernel(struct ion_client *client, struct ion_handle *handle);
+
+/**
+ * ion_share_dma_buf() - share buffer as dma-buf
+ * @client:	the client
+ * @handle:	the handle
+ */
+struct dma_buf *ion_share_dma_buf(struct ion_client *client,
+						struct ion_handle *handle);
+
+/**
+ * ion_share_dma_buf_fd() - given an ion client, create a dma-buf fd
+ * @client:	the client
+ * @handle:	the handle
+ */
+int ion_share_dma_buf_fd(struct ion_client *client, struct ion_handle *handle);
+
+/**
+ * ion_import_dma_buf() - given an dma-buf fd from the ion exporter get handle
+ * @client:	the client
+ * @fd:		the dma-buf fd
+ *
+ * Given an dma-buf fd that was allocated through ion via ion_share_dma_buf,
+ * import that fd and return a handle representing it.  If a dma-buf from
+ * another exporter is passed in this function will return ERR_PTR(-EINVAL)
+ */
+struct ion_handle *ion_import_dma_buf(struct ion_client *client, int fd);
+
+#endif /* _LINUX_ION_H */
diff --git a/drivers/staging/android/ion/ion_carveout_heap.c b/drivers/staging/android/ion/ion_carveout_heap.c
new file mode 100644
index 0000000..66dec4c
--- /dev/null
+++ b/drivers/staging/android/ion/ion_carveout_heap.c
@@ -0,0 +1,181 @@
+/*
+ * drivers/staging/android/ion/ion_carveout_heap.c
+ *
+ * Copyright (C) 2011 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/spinlock.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/genalloc.h>
+#include <linux/io.h>
+#include <linux/mm.h>
+#include <linux/scatterlist.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include "ion.h"
+#include "ion_priv.h"
+
+struct ion_carveout_heap {
+	struct ion_heap heap;
+	struct gen_pool *pool;
+	ion_phys_addr_t base;
+};
+
+ion_phys_addr_t ion_carveout_allocate(struct ion_heap *heap,
+				      unsigned long size,
+				      unsigned long align)
+{
+	struct ion_carveout_heap *carveout_heap =
+		container_of(heap, struct ion_carveout_heap, heap);
+	unsigned long offset = gen_pool_alloc(carveout_heap->pool, size);
+
+	if (!offset)
+		return ION_CARVEOUT_ALLOCATE_FAIL;
+
+	return offset;
+}
+
+void ion_carveout_free(struct ion_heap *heap, ion_phys_addr_t addr,
+		       unsigned long size)
+{
+	struct ion_carveout_heap *carveout_heap =
+		container_of(heap, struct ion_carveout_heap, heap);
+
+	if (addr == ION_CARVEOUT_ALLOCATE_FAIL)
+		return;
+	gen_pool_free(carveout_heap->pool, addr, size);
+}
+
+static int ion_carveout_heap_phys(struct ion_heap *heap,
+				  struct ion_buffer *buffer,
+				  ion_phys_addr_t *addr, size_t *len)
+{
+	struct sg_table *table = buffer->priv_virt;
+	struct page *page = sg_page(table->sgl);
+	ion_phys_addr_t paddr = PFN_PHYS(page_to_pfn(page));
+
+	*addr = paddr;
+	*len = buffer->size;
+	return 0;
+}
+
+static int ion_carveout_heap_allocate(struct ion_heap *heap,
+				      struct ion_buffer *buffer,
+				      unsigned long size, unsigned long align,
+				      unsigned long flags)
+{
+	struct sg_table *table;
+	ion_phys_addr_t paddr;
+	int ret;
+
+	if (align > PAGE_SIZE)
+		return -EINVAL;
+
+	table = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
+	if (!table)
+		return -ENOMEM;
+	ret = sg_alloc_table(table, 1, GFP_KERNEL);
+	if (ret)
+		goto err_free;
+
+	paddr = ion_carveout_allocate(heap, size, align);
+	if (paddr == ION_CARVEOUT_ALLOCATE_FAIL) {
+		ret = -ENOMEM;
+		goto err_free_table;
+	}
+
+	sg_set_page(table->sgl, pfn_to_page(PFN_DOWN(paddr)), size, 0);
+	buffer->priv_virt = table;
+
+	return 0;
+
+err_free_table:
+	sg_free_table(table);
+err_free:
+	kfree(table);
+	return ret;
+}
+
+static void ion_carveout_heap_free(struct ion_buffer *buffer)
+{
+	struct ion_heap *heap = buffer->heap;
+	struct sg_table *table = buffer->priv_virt;
+	struct page *page = sg_page(table->sgl);
+	ion_phys_addr_t paddr = PFN_PHYS(page_to_pfn(page));
+
+	ion_heap_buffer_zero(buffer);
+
+	if (ion_buffer_cached(buffer))
+		dma_sync_sg_for_device(NULL, table->sgl, table->nents,
+							DMA_BIDIRECTIONAL);
+
+	ion_carveout_free(heap, paddr, buffer->size);
+	sg_free_table(table);
+	kfree(table);
+}
+
+static struct sg_table *ion_carveout_heap_map_dma(struct ion_heap *heap,
+						  struct ion_buffer *buffer)
+{
+	return buffer->priv_virt;
+}
+
+static void ion_carveout_heap_unmap_dma(struct ion_heap *heap,
+					struct ion_buffer *buffer)
+{
+	return;
+}
+
+static struct ion_heap_ops carveout_heap_ops = {
+	.allocate = ion_carveout_heap_allocate,
+	.free = ion_carveout_heap_free,
+	.phys = ion_carveout_heap_phys,
+	.map_dma = ion_carveout_heap_map_dma,
+	.unmap_dma = ion_carveout_heap_unmap_dma,
+	.map_user = ion_heap_map_user,
+	.map_kernel = ion_heap_map_kernel,
+	.unmap_kernel = ion_heap_unmap_kernel,
+};
+
+struct ion_heap *ion_carveout_heap_create(struct ion_platform_heap *heap_data)
+{
+	struct ion_carveout_heap *carveout_heap;
+
+	carveout_heap = kzalloc(sizeof(struct ion_carveout_heap), GFP_KERNEL);
+	if (!carveout_heap)
+		return ERR_PTR(-ENOMEM);
+
+	carveout_heap->pool = gen_pool_create(12, -1);
+	if (!carveout_heap->pool) {
+		kfree(carveout_heap);
+		return ERR_PTR(-ENOMEM);
+	}
+	carveout_heap->base = heap_data->base;
+	gen_pool_add(carveout_heap->pool, carveout_heap->base, heap_data->size,
+		     -1);
+	carveout_heap->heap.ops = &carveout_heap_ops;
+	carveout_heap->heap.type = ION_HEAP_TYPE_CARVEOUT;
+	carveout_heap->heap.flags = ION_HEAP_FLAG_DEFER_FREE;
+
+	return &carveout_heap->heap;
+}
+
+void ion_carveout_heap_destroy(struct ion_heap *heap)
+{
+	struct ion_carveout_heap *carveout_heap =
+	     container_of(heap, struct  ion_carveout_heap, heap);
+
+	gen_pool_destroy(carveout_heap->pool);
+	kfree(carveout_heap);
+	carveout_heap = NULL;
+}
diff --git a/drivers/staging/android/ion/ion_chunk_heap.c b/drivers/staging/android/ion/ion_chunk_heap.c
new file mode 100644
index 0000000..a2f6108
--- /dev/null
+++ b/drivers/staging/android/ion/ion_chunk_heap.c
@@ -0,0 +1,210 @@
+/*
+ * drivers/staging/android/ion/ion_chunk_heap.c
+ *
+ * Copyright (C) 2012 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/genalloc.h>
+#include <linux/io.h>
+#include <linux/mm.h>
+#include <linux/scatterlist.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include "ion.h"
+#include "ion_priv.h"
+
+struct ion_chunk_heap {
+	struct ion_heap heap;
+	struct gen_pool *pool;
+	ion_phys_addr_t base;
+	unsigned long chunk_size;
+	unsigned long size;
+	unsigned long allocated;
+};
+
+static int ion_chunk_heap_allocate(struct ion_heap *heap,
+				      struct ion_buffer *buffer,
+				      unsigned long size, unsigned long align,
+				      unsigned long flags)
+{
+	struct ion_chunk_heap *chunk_heap =
+		container_of(heap, struct ion_chunk_heap, heap);
+	struct sg_table *table;
+	struct scatterlist *sg;
+	int ret, i;
+	unsigned long num_chunks;
+	unsigned long allocated_size;
+
+	if (align > chunk_heap->chunk_size)
+		return -EINVAL;
+
+	allocated_size = ALIGN(size, chunk_heap->chunk_size);
+	num_chunks = allocated_size / chunk_heap->chunk_size;
+
+	if (allocated_size > chunk_heap->size - chunk_heap->allocated)
+		return -ENOMEM;
+
+	table = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
+	if (!table)
+		return -ENOMEM;
+	ret = sg_alloc_table(table, num_chunks, GFP_KERNEL);
+	if (ret) {
+		kfree(table);
+		return ret;
+	}
+
+	sg = table->sgl;
+	for (i = 0; i < num_chunks; i++) {
+		unsigned long paddr = gen_pool_alloc(chunk_heap->pool,
+						     chunk_heap->chunk_size);
+		if (!paddr)
+			goto err;
+		sg_set_page(sg, pfn_to_page(PFN_DOWN(paddr)),
+				chunk_heap->chunk_size, 0);
+		sg = sg_next(sg);
+	}
+
+	buffer->priv_virt = table;
+	chunk_heap->allocated += allocated_size;
+	return 0;
+err:
+	sg = table->sgl;
+	for (i -= 1; i >= 0; i--) {
+		gen_pool_free(chunk_heap->pool, page_to_phys(sg_page(sg)),
+			      sg->length);
+		sg = sg_next(sg);
+	}
+	sg_free_table(table);
+	kfree(table);
+	return -ENOMEM;
+}
+
+static void ion_chunk_heap_free(struct ion_buffer *buffer)
+{
+	struct ion_heap *heap = buffer->heap;
+	struct ion_chunk_heap *chunk_heap =
+		container_of(heap, struct ion_chunk_heap, heap);
+	struct sg_table *table = buffer->priv_virt;
+	struct scatterlist *sg;
+	int i;
+	unsigned long allocated_size;
+
+	allocated_size = ALIGN(buffer->size, chunk_heap->chunk_size);
+
+	ion_heap_buffer_zero(buffer);
+
+	if (ion_buffer_cached(buffer))
+		dma_sync_sg_for_device(NULL, table->sgl, table->nents,
+								DMA_BIDIRECTIONAL);
+
+	for_each_sg(table->sgl, sg, table->nents, i) {
+		gen_pool_free(chunk_heap->pool, page_to_phys(sg_page(sg)),
+			      sg->length);
+	}
+	chunk_heap->allocated -= allocated_size;
+	sg_free_table(table);
+	kfree(table);
+}
+
+static struct sg_table *ion_chunk_heap_map_dma(struct ion_heap *heap,
+					       struct ion_buffer *buffer)
+{
+	return buffer->priv_virt;
+}
+
+static void ion_chunk_heap_unmap_dma(struct ion_heap *heap,
+				     struct ion_buffer *buffer)
+{
+	return;
+}
+
+static struct ion_heap_ops chunk_heap_ops = {
+	.allocate = ion_chunk_heap_allocate,
+	.free = ion_chunk_heap_free,
+	.map_dma = ion_chunk_heap_map_dma,
+	.unmap_dma = ion_chunk_heap_unmap_dma,
+	.map_user = ion_heap_map_user,
+	.map_kernel = ion_heap_map_kernel,
+	.unmap_kernel = ion_heap_unmap_kernel,
+};
+
+struct ion_heap *ion_chunk_heap_create(struct ion_platform_heap *heap_data)
+{
+	struct ion_chunk_heap *chunk_heap;
+	struct vm_struct *vm_struct;
+	pgprot_t pgprot = pgprot_writecombine(PAGE_KERNEL);
+	int i, ret;
+
+	chunk_heap = kzalloc(sizeof(struct ion_chunk_heap), GFP_KERNEL);
+	if (!chunk_heap)
+		return ERR_PTR(-ENOMEM);
+
+	chunk_heap->chunk_size = (unsigned long)heap_data->priv;
+	chunk_heap->pool = gen_pool_create(get_order(chunk_heap->chunk_size) +
+					   PAGE_SHIFT, -1);
+	if (!chunk_heap->pool) {
+		ret = -ENOMEM;
+		goto error_gen_pool_create;
+	}
+	chunk_heap->base = heap_data->base;
+	chunk_heap->size = heap_data->size;
+	chunk_heap->allocated = 0;
+
+	vm_struct = get_vm_area(PAGE_SIZE, VM_ALLOC);
+	if (!vm_struct) {
+		ret = -ENOMEM;
+		goto error;
+	}
+	for (i = 0; i < chunk_heap->size; i += PAGE_SIZE) {
+		struct page *page = pfn_to_page(PFN_DOWN(chunk_heap->base + i));
+		struct page **pages = &page;
+
+		ret = map_vm_area(vm_struct, pgprot, &pages);
+		if (ret)
+			goto error_map_vm_area;
+		memset(vm_struct->addr, 0, PAGE_SIZE);
+		unmap_kernel_range((unsigned long)vm_struct->addr, PAGE_SIZE);
+	}
+	free_vm_area(vm_struct);
+
+	ion_pages_sync_for_device(NULL, pfn_to_page(PFN_DOWN(heap_data->base)),
+			heap_data->size, DMA_BIDIRECTIONAL);
+
+	gen_pool_add(chunk_heap->pool, chunk_heap->base, heap_data->size, -1);
+	chunk_heap->heap.ops = &chunk_heap_ops;
+	chunk_heap->heap.type = ION_HEAP_TYPE_CHUNK;
+	chunk_heap->heap.flags = ION_HEAP_FLAG_DEFER_FREE;
+	pr_info("%s: base %lu size %zu align %ld\n", __func__, chunk_heap->base,
+		heap_data->size, heap_data->align);
+
+	return &chunk_heap->heap;
+
+error_map_vm_area:
+	free_vm_area(vm_struct);
+error:
+	gen_pool_destroy(chunk_heap->pool);
+error_gen_pool_create:
+	kfree(chunk_heap);
+	return ERR_PTR(ret);
+}
+
+void ion_chunk_heap_destroy(struct ion_heap *heap)
+{
+	struct ion_chunk_heap *chunk_heap =
+	     container_of(heap, struct  ion_chunk_heap, heap);
+
+	gen_pool_destroy(chunk_heap->pool);
+	kfree(chunk_heap);
+	chunk_heap = NULL;
+}
diff --git a/drivers/staging/android/ion/ion_cma_heap.c b/drivers/staging/android/ion/ion_cma_heap.c
new file mode 100644
index 0000000..f0f9889
--- /dev/null
+++ b/drivers/staging/android/ion/ion_cma_heap.c
@@ -0,0 +1,218 @@
+/*
+ * drivers/staging/android/ion/ion_cma_heap.c
+ *
+ * Copyright (C) Linaro 2012
+ * Author: <benjamin.gaignard@linaro.org> for ST-Ericsson.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/dma-mapping.h>
+
+#include "ion.h"
+#include "ion_priv.h"
+
+#define ION_CMA_ALLOCATE_FAILED -1
+
+struct ion_cma_heap {
+	struct ion_heap heap;
+	struct device *dev;
+};
+
+#define to_cma_heap(x) container_of(x, struct ion_cma_heap, heap)
+
+struct ion_cma_buffer_info {
+	void *cpu_addr;
+	dma_addr_t handle;
+	struct sg_table *table;
+};
+
+/*
+ * Create scatter-list for the already allocated DMA buffer.
+ * This function could be replaced by dma_common_get_sgtable
+ * as soon as it will avalaible.
+ */
+static int ion_cma_get_sgtable(struct device *dev, struct sg_table *sgt,
+			       void *cpu_addr, dma_addr_t handle, size_t size)
+{
+	struct page *page = virt_to_page(cpu_addr);
+	int ret;
+
+	ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
+	if (unlikely(ret))
+		return ret;
+
+	sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
+	return 0;
+}
+
+/* ION CMA heap operations functions */
+static int ion_cma_allocate(struct ion_heap *heap, struct ion_buffer *buffer,
+			    unsigned long len, unsigned long align,
+			    unsigned long flags)
+{
+	struct ion_cma_heap *cma_heap = to_cma_heap(heap);
+	struct device *dev = cma_heap->dev;
+	struct ion_cma_buffer_info *info;
+
+	dev_dbg(dev, "Request buffer allocation len %ld\n", len);
+
+	if (buffer->flags & ION_FLAG_CACHED)
+		return -EINVAL;
+
+	if (align > PAGE_SIZE)
+		return -EINVAL;
+
+	info = kzalloc(sizeof(struct ion_cma_buffer_info), GFP_KERNEL);
+	if (!info) {
+		dev_err(dev, "Can't allocate buffer info\n");
+		return ION_CMA_ALLOCATE_FAILED;
+	}
+
+	info->cpu_addr = dma_alloc_coherent(dev, len, &(info->handle),
+						GFP_HIGHUSER | __GFP_ZERO);
+
+	if (!info->cpu_addr) {
+		dev_err(dev, "Fail to allocate buffer\n");
+		goto err;
+	}
+
+	info->table = kmalloc(sizeof(struct sg_table), GFP_KERNEL);
+	if (!info->table) {
+		dev_err(dev, "Fail to allocate sg table\n");
+		goto free_mem;
+	}
+
+	if (ion_cma_get_sgtable
+	    (dev, info->table, info->cpu_addr, info->handle, len))
+		goto free_table;
+	/* keep this for memory release */
+	buffer->priv_virt = info;
+	dev_dbg(dev, "Allocate buffer %p\n", buffer);
+	return 0;
+
+free_table:
+	kfree(info->table);
+free_mem:
+	dma_free_coherent(dev, len, info->cpu_addr, info->handle);
+err:
+	kfree(info);
+	return ION_CMA_ALLOCATE_FAILED;
+}
+
+static void ion_cma_free(struct ion_buffer *buffer)
+{
+	struct ion_cma_heap *cma_heap = to_cma_heap(buffer->heap);
+	struct device *dev = cma_heap->dev;
+	struct ion_cma_buffer_info *info = buffer->priv_virt;
+
+	dev_dbg(dev, "Release buffer %p\n", buffer);
+	/* release memory */
+	dma_free_coherent(dev, buffer->size, info->cpu_addr, info->handle);
+	/* release sg table */
+	sg_free_table(info->table);
+	kfree(info->table);
+	kfree(info);
+}
+
+/* return physical address in addr */
+static int ion_cma_phys(struct ion_heap *heap, struct ion_buffer *buffer,
+			ion_phys_addr_t *addr, size_t *len)
+{
+	struct ion_cma_heap *cma_heap = to_cma_heap(buffer->heap);
+	struct device *dev = cma_heap->dev;
+	struct ion_cma_buffer_info *info = buffer->priv_virt;
+
+	dev_dbg(dev, "Return buffer %p physical address 0x%pa\n", buffer,
+		&info->handle);
+
+	*addr = info->handle;
+	*len = buffer->size;
+
+	return 0;
+}
+
+static struct sg_table *ion_cma_heap_map_dma(struct ion_heap *heap,
+					     struct ion_buffer *buffer)
+{
+	struct ion_cma_buffer_info *info = buffer->priv_virt;
+
+	return info->table;
+}
+
+static void ion_cma_heap_unmap_dma(struct ion_heap *heap,
+				   struct ion_buffer *buffer)
+{
+	return;
+}
+
+static int ion_cma_mmap(struct ion_heap *mapper, struct ion_buffer *buffer,
+			struct vm_area_struct *vma)
+{
+	struct ion_cma_heap *cma_heap = to_cma_heap(buffer->heap);
+	struct device *dev = cma_heap->dev;
+	struct ion_cma_buffer_info *info = buffer->priv_virt;
+
+	return dma_mmap_coherent(dev, vma, info->cpu_addr, info->handle,
+				 buffer->size);
+}
+
+static void *ion_cma_map_kernel(struct ion_heap *heap,
+				struct ion_buffer *buffer)
+{
+	struct ion_cma_buffer_info *info = buffer->priv_virt;
+	/* kernel memory mapping has been done at allocation time */
+	return info->cpu_addr;
+}
+
+static void ion_cma_unmap_kernel(struct ion_heap *heap,
+					struct ion_buffer *buffer)
+{
+}
+
+static struct ion_heap_ops ion_cma_ops = {
+	.allocate = ion_cma_allocate,
+	.free = ion_cma_free,
+	.map_dma = ion_cma_heap_map_dma,
+	.unmap_dma = ion_cma_heap_unmap_dma,
+	.phys = ion_cma_phys,
+	.map_user = ion_cma_mmap,
+	.map_kernel = ion_cma_map_kernel,
+	.unmap_kernel = ion_cma_unmap_kernel,
+};
+
+struct ion_heap *ion_cma_heap_create(struct ion_platform_heap *data)
+{
+	struct ion_cma_heap *cma_heap;
+
+	cma_heap = kzalloc(sizeof(struct ion_cma_heap), GFP_KERNEL);
+
+	if (!cma_heap)
+		return ERR_PTR(-ENOMEM);
+
+	cma_heap->heap.ops = &ion_cma_ops;
+	/* get device from private heaps data, later it will be
+	 * used to make the link with reserved CMA memory */
+	cma_heap->dev = data->priv;
+	cma_heap->heap.type = ION_HEAP_TYPE_DMA;
+	return &cma_heap->heap;
+}
+
+void ion_cma_heap_destroy(struct ion_heap *heap)
+{
+	struct ion_cma_heap *cma_heap = to_cma_heap(heap);
+
+	kfree(cma_heap);
+}
diff --git a/drivers/staging/android/ion/ion_dummy_driver.c b/drivers/staging/android/ion/ion_dummy_driver.c
new file mode 100644
index 0000000..01cdc8a
--- /dev/null
+++ b/drivers/staging/android/ion/ion_dummy_driver.c
@@ -0,0 +1,158 @@
+/*
+ * drivers/gpu/ion/ion_dummy_driver.c
+ *
+ * Copyright (C) 2013 Linaro, Inc
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/bootmem.h>
+#include <linux/memblock.h>
+#include <linux/sizes.h>
+#include <linux/io.h>
+#include "ion.h"
+#include "ion_priv.h"
+
+struct ion_device *idev;
+struct ion_heap **heaps;
+
+void *carveout_ptr;
+void *chunk_ptr;
+
+struct ion_platform_heap dummy_heaps[] = {
+		{
+			.id	= ION_HEAP_TYPE_SYSTEM,
+			.type	= ION_HEAP_TYPE_SYSTEM,
+			.name	= "system",
+		},
+		{
+			.id	= ION_HEAP_TYPE_SYSTEM_CONTIG,
+			.type	= ION_HEAP_TYPE_SYSTEM_CONTIG,
+			.name	= "system contig",
+		},
+		{
+			.id	= ION_HEAP_TYPE_CARVEOUT,
+			.type	= ION_HEAP_TYPE_CARVEOUT,
+			.name	= "carveout",
+			.size	= SZ_4M,
+		},
+		{
+			.id	= ION_HEAP_TYPE_CHUNK,
+			.type	= ION_HEAP_TYPE_CHUNK,
+			.name	= "chunk",
+			.size	= SZ_4M,
+			.align	= SZ_16K,
+			.priv	= (void *)(SZ_16K),
+		},
+};
+
+struct ion_platform_data dummy_ion_pdata = {
+	.nr = ARRAY_SIZE(dummy_heaps),
+	.heaps = dummy_heaps,
+};
+
+static int __init ion_dummy_init(void)
+{
+	int i, err;
+
+	idev = ion_device_create(NULL);
+	heaps = kzalloc(sizeof(struct ion_heap *) * dummy_ion_pdata.nr,
+			GFP_KERNEL);
+	if (!heaps)
+		return -ENOMEM;
+
+
+	/* Allocate a dummy carveout heap */
+	carveout_ptr = alloc_pages_exact(
+				dummy_heaps[ION_HEAP_TYPE_CARVEOUT].size,
+				GFP_KERNEL);
+	if (carveout_ptr)
+		dummy_heaps[ION_HEAP_TYPE_CARVEOUT].base =
+						virt_to_phys(carveout_ptr);
+	else
+		pr_err("ion_dummy: Could not allocate carveout\n");
+
+	/* Allocate a dummy chunk heap */
+	chunk_ptr = alloc_pages_exact(
+				dummy_heaps[ION_HEAP_TYPE_CHUNK].size,
+				GFP_KERNEL);
+	if (chunk_ptr)
+		dummy_heaps[ION_HEAP_TYPE_CHUNK].base = virt_to_phys(chunk_ptr);
+	else
+		pr_err("ion_dummy: Could not allocate chunk\n");
+
+	for (i = 0; i < dummy_ion_pdata.nr; i++) {
+		struct ion_platform_heap *heap_data = &dummy_ion_pdata.heaps[i];
+
+		if (heap_data->type == ION_HEAP_TYPE_CARVEOUT &&
+							!heap_data->base)
+			continue;
+
+		if (heap_data->type == ION_HEAP_TYPE_CHUNK && !heap_data->base)
+			continue;
+
+		heaps[i] = ion_heap_create(heap_data);
+		if (IS_ERR_OR_NULL(heaps[i])) {
+			err = PTR_ERR(heaps[i]);
+			goto err;
+		}
+		ion_device_add_heap(idev, heaps[i]);
+	}
+	return 0;
+err:
+	for (i = 0; i < dummy_ion_pdata.nr; i++) {
+		if (heaps[i])
+			ion_heap_destroy(heaps[i]);
+	}
+	kfree(heaps);
+
+	if (carveout_ptr) {
+		free_pages_exact(carveout_ptr,
+				dummy_heaps[ION_HEAP_TYPE_CARVEOUT].size);
+		carveout_ptr = NULL;
+	}
+	if (chunk_ptr) {
+		free_pages_exact(chunk_ptr,
+				dummy_heaps[ION_HEAP_TYPE_CHUNK].size);
+		chunk_ptr = NULL;
+	}
+	return err;
+}
+device_initcall(ion_dummy_init);
+
+static void __exit ion_dummy_exit(void)
+{
+	int i;
+
+	ion_device_destroy(idev);
+
+	for (i = 0; i < dummy_ion_pdata.nr; i++)
+		ion_heap_destroy(heaps[i]);
+	kfree(heaps);
+
+	if (carveout_ptr) {
+		free_pages_exact(carveout_ptr,
+				dummy_heaps[ION_HEAP_TYPE_CARVEOUT].size);
+		carveout_ptr = NULL;
+	}
+	if (chunk_ptr) {
+		free_pages_exact(chunk_ptr,
+				dummy_heaps[ION_HEAP_TYPE_CHUNK].size);
+		chunk_ptr = NULL;
+	}
+
+	return;
+}
+__exitcall(ion_dummy_exit);
diff --git a/drivers/staging/android/ion/ion_heap.c b/drivers/staging/android/ion/ion_heap.c
new file mode 100644
index 0000000..d1ac0b5
--- /dev/null
+++ b/drivers/staging/android/ion/ion_heap.c
@@ -0,0 +1,313 @@
+/*
+ * drivers/staging/android/ion/ion_heap.c
+ *
+ * Copyright (C) 2011 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/err.h>
+#include <linux/freezer.h>
+#include <linux/kthread.h>
+#include <linux/mm.h>
+#include <linux/rtmutex.h>
+#include <linux/sched.h>
+#include <linux/scatterlist.h>
+#include <linux/vmalloc.h>
+#include <linux/export.h>
+#include "ion.h"
+#include "ion_priv.h"
+
+void *ion_heap_map_kernel(struct ion_heap *heap,
+			  struct ion_buffer *buffer)
+{
+	struct scatterlist *sg;
+	int i, j;
+	void *vaddr;
+	pgprot_t pgprot;
+	struct sg_table *table = buffer->sg_table;
+	int npages = PAGE_ALIGN(buffer->size) / PAGE_SIZE;
+	struct page **pages = vmalloc(sizeof(struct page *) * npages);
+	struct page **tmp = pages;
+
+	if (!pages)
+		return NULL;
+
+	if (buffer->flags & ION_FLAG_CACHED)
+		pgprot = PAGE_KERNEL;
+	else
+		pgprot = pgprot_writecombine(PAGE_KERNEL);
+
+	for_each_sg(table->sgl, sg, table->nents, i) {
+		int npages_this_entry = PAGE_ALIGN(sg->length) / PAGE_SIZE;
+		struct page *page = sg_page(sg);
+		BUG_ON(i >= npages);
+		for (j = 0; j < npages_this_entry; j++)
+			*(tmp++) = page++;
+	}
+	vaddr = vmap(pages, npages, VM_MAP, pgprot);
+	vfree(pages);
+
+	if (vaddr == NULL)
+		return ERR_PTR(-ENOMEM);
+
+	return vaddr;
+}
+EXPORT_SYMBOL(ion_heap_map_kernel);
+
+void ion_heap_unmap_kernel(struct ion_heap *heap,
+			   struct ion_buffer *buffer)
+{
+	vunmap(buffer->vaddr);
+}
+EXPORT_SYMBOL(ion_heap_unmap_kernel);
+
+int ion_heap_map_user(struct ion_heap *heap, struct ion_buffer *buffer,
+		      struct vm_area_struct *vma)
+{
+	struct sg_table *table = buffer->sg_table;
+	unsigned long addr = vma->vm_start;
+	unsigned long offset = vma->vm_pgoff * PAGE_SIZE;
+	struct scatterlist *sg;
+	int i;
+	int ret;
+
+	for_each_sg(table->sgl, sg, table->nents, i) {
+		struct page *page = sg_page(sg);
+		unsigned long remainder = vma->vm_end - addr;
+		unsigned long len = sg->length;
+
+		if (offset >= sg->length) {
+			offset -= sg->length;
+			continue;
+		} else if (offset) {
+			page += offset / PAGE_SIZE;
+			len = sg->length - offset;
+			offset = 0;
+		}
+		len = min(len, remainder);
+		ret = remap_pfn_range(vma, addr, page_to_pfn(page), len,
+				vma->vm_page_prot);
+		if (ret)
+			return ret;
+		addr += len;
+		if (addr >= vma->vm_end)
+			return 0;
+	}
+	return 0;
+}
+EXPORT_SYMBOL(ion_heap_map_user);
+
+static int ion_heap_clear_pages(struct page **pages, int num, pgprot_t pgprot)
+{
+	void *addr = vm_map_ram(pages, num, -1, pgprot);
+	if (!addr)
+		return -ENOMEM;
+	memset(addr, 0, PAGE_SIZE * num);
+	vm_unmap_ram(addr, num);
+
+	return 0;
+}
+
+int ion_heap_buffer_zero(struct ion_buffer *buffer)
+{
+	struct sg_table *table = buffer->sg_table;
+	pgprot_t pgprot;
+	struct scatterlist *sg;
+	int i, j, ret = 0;
+	struct page *pages[32];
+	int k = 0;
+
+	if (buffer->flags & ION_FLAG_CACHED)
+		pgprot = PAGE_KERNEL;
+	else
+		pgprot = pgprot_writecombine(PAGE_KERNEL);
+
+	for_each_sg(table->sgl, sg, table->nents, i) {
+		struct page *page = sg_page(sg);
+		unsigned long len = sg->length;
+
+		for (j = 0; j < len / PAGE_SIZE; j++) {
+			pages[k++] = page + j;
+			if (k == ARRAY_SIZE(pages)) {
+				ret = ion_heap_clear_pages(pages, k, pgprot);
+				if (ret)
+					goto end;
+				k = 0;
+			}
+		}
+		if (k)
+			ret = ion_heap_clear_pages(pages, k, pgprot);
+	}
+end:
+	return ret;
+}
+
+void ion_heap_freelist_add(struct ion_heap *heap, struct ion_buffer *buffer)
+{
+	spin_lock(&heap->free_lock);
+	list_add(&buffer->list, &heap->free_list);
+	heap->free_list_size += buffer->size;
+	spin_unlock(&heap->free_lock);
+	wake_up(&heap->waitqueue);
+}
+
+size_t ion_heap_freelist_size(struct ion_heap *heap)
+{
+	size_t size;
+
+	spin_lock(&heap->free_lock);
+	size = heap->free_list_size;
+	spin_unlock(&heap->free_lock);
+
+	return size;
+}
+
+size_t ion_heap_freelist_drain(struct ion_heap *heap, size_t size)
+{
+	struct ion_buffer *buffer;
+	size_t total_drained = 0;
+
+	if (ion_heap_freelist_size(heap) == 0)
+		return 0;
+
+	spin_lock(&heap->free_lock);
+	if (size == 0)
+		size = heap->free_list_size;
+
+	while (!list_empty(&heap->free_list)) {
+		if (total_drained >= size)
+			break;
+		buffer = list_first_entry(&heap->free_list, struct ion_buffer,
+					  list);
+		list_del(&buffer->list);
+		heap->free_list_size -= buffer->size;
+		total_drained += buffer->size;
+		spin_unlock(&heap->free_lock);
+		ion_buffer_destroy(buffer);
+		spin_lock(&heap->free_lock);
+	}
+	spin_unlock(&heap->free_lock);
+
+	return total_drained;
+}
+
+static int ion_heap_deferred_free(void *data)
+{
+	struct ion_heap *heap = data;
+
+	while (true) {
+		struct ion_buffer *buffer;
+
+		wait_event_freezable(heap->waitqueue,
+				     ion_heap_freelist_size(heap) > 0);
+
+		spin_lock(&heap->free_lock);
+		if (list_empty(&heap->free_list)) {
+			spin_unlock(&heap->free_lock);
+			continue;
+		}
+		buffer = list_first_entry(&heap->free_list, struct ion_buffer,
+					  list);
+		list_del(&buffer->list);
+		heap->free_list_size -= buffer->size;
+		spin_unlock(&heap->free_lock);
+		ion_buffer_destroy(buffer);
+	}
+
+	return 0;
+}
+
+int ion_heap_init_deferred_free(struct ion_heap *heap)
+{
+	struct sched_param param = { .sched_priority = 0 };
+
+	INIT_LIST_HEAD(&heap->free_list);
+	heap->free_list_size = 0;
+	spin_lock_init(&heap->free_lock);
+	init_waitqueue_head(&heap->waitqueue);
+	heap->task = kthread_run(ion_heap_deferred_free, heap,
+				 "%s", heap->name);
+	if (IS_ERR(heap->task)) {
+		pr_err("%s: creating thread for deferred free failed\n",
+		       __func__);
+		return PTR_RET(heap->task);
+	}
+	sched_setscheduler(heap->task, SCHED_IDLE, &param);
+	return 0;
+}
+
+struct ion_heap *ion_heap_create(struct ion_platform_heap *heap_data)
+{
+	struct ion_heap *heap = NULL;
+
+	switch (heap_data->type) {
+	case ION_HEAP_TYPE_SYSTEM_CONTIG:
+		heap = ion_system_contig_heap_create(heap_data);
+		break;
+	case ION_HEAP_TYPE_SYSTEM:
+		heap = ion_system_heap_create(heap_data);
+		break;
+	case ION_HEAP_TYPE_CARVEOUT:
+		heap = ion_carveout_heap_create(heap_data);
+		break;
+	case ION_HEAP_TYPE_CHUNK:
+		heap = ion_chunk_heap_create(heap_data);
+		break;
+	case ION_HEAP_TYPE_DMA:
+		heap = ion_cma_heap_create(heap_data);
+		break;
+	default:
+		pr_err("%s: Invalid heap type %d\n", __func__,
+		       heap_data->type);
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (IS_ERR_OR_NULL(heap)) {
+		pr_err("%s: error creating heap %s type %d base %lu size %zu\n",
+		       __func__, heap_data->name, heap_data->type,
+		       heap_data->base, heap_data->size);
+		return ERR_PTR(-EINVAL);
+	}
+
+	heap->name = heap_data->name;
+	heap->id = heap_data->id;
+	return heap;
+}
+EXPORT_SYMBOL(ion_heap_create);
+
+void ion_heap_destroy(struct ion_heap *heap)
+{
+	if (!heap)
+		return;
+
+	switch (heap->type) {
+	case ION_HEAP_TYPE_SYSTEM_CONTIG:
+		ion_system_contig_heap_destroy(heap);
+		break;
+	case ION_HEAP_TYPE_SYSTEM:
+		ion_system_heap_destroy(heap);
+		break;
+	case ION_HEAP_TYPE_CARVEOUT:
+		ion_carveout_heap_destroy(heap);
+		break;
+	case ION_HEAP_TYPE_CHUNK:
+		ion_chunk_heap_destroy(heap);
+		break;
+	case ION_HEAP_TYPE_DMA:
+		ion_cma_heap_destroy(heap);
+		break;
+	default:
+		pr_err("%s: Invalid heap type %d\n", __func__,
+		       heap->type);
+	}
+}
+EXPORT_SYMBOL(ion_heap_destroy);
diff --git a/drivers/staging/android/ion/ion_page_pool.c b/drivers/staging/android/ion/ion_page_pool.c
new file mode 100644
index 0000000..fa693c2
--- /dev/null
+++ b/drivers/staging/android/ion/ion_page_pool.c
@@ -0,0 +1,195 @@
+/*
+ * drivers/staging/android/ion/ion_mem_pool.c
+ *
+ * Copyright (C) 2011 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/debugfs.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/fs.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include "ion_priv.h"
+
+struct ion_page_pool_item {
+	struct page *page;
+	struct list_head list;
+};
+
+static void *ion_page_pool_alloc_pages(struct ion_page_pool *pool)
+{
+	struct page *page = alloc_pages(pool->gfp_mask, pool->order);
+
+	if (!page)
+		return NULL;
+	ion_pages_sync_for_device(NULL, page, PAGE_SIZE << pool->order,
+						DMA_BIDIRECTIONAL);
+	return page;
+}
+
+static void ion_page_pool_free_pages(struct ion_page_pool *pool,
+				     struct page *page)
+{
+	__free_pages(page, pool->order);
+}
+
+static int ion_page_pool_add(struct ion_page_pool *pool, struct page *page)
+{
+	struct ion_page_pool_item *item;
+
+	item = kmalloc(sizeof(struct ion_page_pool_item), GFP_KERNEL);
+	if (!item)
+		return -ENOMEM;
+
+	mutex_lock(&pool->mutex);
+	item->page = page;
+	if (PageHighMem(page)) {
+		list_add_tail(&item->list, &pool->high_items);
+		pool->high_count++;
+	} else {
+		list_add_tail(&item->list, &pool->low_items);
+		pool->low_count++;
+	}
+	mutex_unlock(&pool->mutex);
+	return 0;
+}
+
+static struct page *ion_page_pool_remove(struct ion_page_pool *pool, bool high)
+{
+	struct ion_page_pool_item *item;
+	struct page *page;
+
+	if (high) {
+		BUG_ON(!pool->high_count);
+		item = list_first_entry(&pool->high_items,
+					struct ion_page_pool_item, list);
+		pool->high_count--;
+	} else {
+		BUG_ON(!pool->low_count);
+		item = list_first_entry(&pool->low_items,
+					struct ion_page_pool_item, list);
+		pool->low_count--;
+	}
+
+	list_del(&item->list);
+	page = item->page;
+	kfree(item);
+	return page;
+}
+
+void *ion_page_pool_alloc(struct ion_page_pool *pool)
+{
+	struct page *page = NULL;
+
+	BUG_ON(!pool);
+
+	mutex_lock(&pool->mutex);
+	if (pool->high_count)
+		page = ion_page_pool_remove(pool, true);
+	else if (pool->low_count)
+		page = ion_page_pool_remove(pool, false);
+	mutex_unlock(&pool->mutex);
+
+	if (!page)
+		page = ion_page_pool_alloc_pages(pool);
+
+	return page;
+}
+
+void ion_page_pool_free(struct ion_page_pool *pool, struct page *page)
+{
+	int ret;
+
+	ret = ion_page_pool_add(pool, page);
+	if (ret)
+		ion_page_pool_free_pages(pool, page);
+}
+
+static int ion_page_pool_total(struct ion_page_pool *pool, bool high)
+{
+	int total = 0;
+
+	total += high ? (pool->high_count + pool->low_count) *
+		(1 << pool->order) :
+			pool->low_count * (1 << pool->order);
+	return total;
+}
+
+int ion_page_pool_shrink(struct ion_page_pool *pool, gfp_t gfp_mask,
+				int nr_to_scan)
+{
+	int nr_freed = 0;
+	int i;
+	bool high;
+
+	high = !!(gfp_mask & __GFP_HIGHMEM);
+
+	if (nr_to_scan == 0)
+		return ion_page_pool_total(pool, high);
+
+	for (i = 0; i < nr_to_scan; i++) {
+		struct page *page;
+
+		mutex_lock(&pool->mutex);
+		if (pool->low_count) {
+			page = ion_page_pool_remove(pool, false);
+		} else if (high && pool->high_count) {
+			page = ion_page_pool_remove(pool, true);
+		} else {
+			mutex_unlock(&pool->mutex);
+			break;
+		}
+		mutex_unlock(&pool->mutex);
+		ion_page_pool_free_pages(pool, page);
+		nr_freed += (1 << pool->order);
+	}
+
+	return nr_freed;
+}
+
+struct ion_page_pool *ion_page_pool_create(gfp_t gfp_mask, unsigned int order)
+{
+	struct ion_page_pool *pool = kmalloc(sizeof(struct ion_page_pool),
+					     GFP_KERNEL);
+	if (!pool)
+		return NULL;
+	pool->high_count = 0;
+	pool->low_count = 0;
+	INIT_LIST_HEAD(&pool->low_items);
+	INIT_LIST_HEAD(&pool->high_items);
+	pool->gfp_mask = gfp_mask;
+	pool->order = order;
+	mutex_init(&pool->mutex);
+	plist_node_init(&pool->list, order);
+
+	return pool;
+}
+
+void ion_page_pool_destroy(struct ion_page_pool *pool)
+{
+	kfree(pool);
+}
+
+static int __init ion_page_pool_init(void)
+{
+	return 0;
+}
+
+static void __exit ion_page_pool_exit(void)
+{
+}
+
+module_init(ion_page_pool_init);
+module_exit(ion_page_pool_exit);
diff --git a/drivers/staging/android/ion/ion_priv.h b/drivers/staging/android/ion/ion_priv.h
new file mode 100644
index 0000000..2b55959
--- /dev/null
+++ b/drivers/staging/android/ion/ion_priv.h
@@ -0,0 +1,360 @@
+/*
+ * drivers/staging/android/ion/ion_priv.h
+ *
+ * Copyright (C) 2011 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _ION_PRIV_H
+#define _ION_PRIV_H
+
+#include <linux/device.h>
+#include <linux/dma-direction.h>
+#include <linux/kref.h>
+#include <linux/mm_types.h>
+#include <linux/mutex.h>
+#include <linux/rbtree.h>
+#include <linux/sched.h>
+#include <linux/shrinker.h>
+#include <linux/types.h>
+
+#include "ion.h"
+
+struct ion_buffer *ion_handle_buffer(struct ion_handle *handle);
+
+/**
+ * struct ion_buffer - metadata for a particular buffer
+ * @ref:		refernce count
+ * @node:		node in the ion_device buffers tree
+ * @dev:		back pointer to the ion_device
+ * @heap:		back pointer to the heap the buffer came from
+ * @flags:		buffer specific flags
+ * @size:		size of the buffer
+ * @priv_virt:		private data to the buffer representable as
+ *			a void *
+ * @priv_phys:		private data to the buffer representable as
+ *			an ion_phys_addr_t (and someday a phys_addr_t)
+ * @lock:		protects the buffers cnt fields
+ * @kmap_cnt:		number of times the buffer is mapped to the kernel
+ * @vaddr:		the kenrel mapping if kmap_cnt is not zero
+ * @dmap_cnt:		number of times the buffer is mapped for dma
+ * @sg_table:		the sg table for the buffer if dmap_cnt is not zero
+ * @pages:		flat array of pages in the buffer -- used by fault
+ *			handler and only valid for buffers that are faulted in
+ * @vmas:		list of vma's mapping this buffer
+ * @handle_count:	count of handles referencing this buffer
+ * @task_comm:		taskcomm of last client to reference this buffer in a
+ *			handle, used for debugging
+ * @pid:		pid of last client to reference this buffer in a
+ *			handle, used for debugging
+*/
+struct ion_buffer {
+	struct kref ref;
+	union {
+		struct rb_node node;
+		struct list_head list;
+	};
+	struct ion_device *dev;
+	struct ion_heap *heap;
+	unsigned long flags;
+	size_t size;
+	union {
+		void *priv_virt;
+		ion_phys_addr_t priv_phys;
+	};
+	struct mutex lock;
+	int kmap_cnt;
+	void *vaddr;
+	int dmap_cnt;
+	struct sg_table *sg_table;
+	struct page **pages;
+	struct list_head vmas;
+	/* used to track orphaned buffers */
+	int handle_count;
+	char task_comm[TASK_COMM_LEN];
+	pid_t pid;
+};
+void ion_buffer_destroy(struct ion_buffer *buffer);
+
+/**
+ * struct ion_heap_ops - ops to operate on a given heap
+ * @allocate:		allocate memory
+ * @free:		free memory
+ * @phys		get physical address of a buffer (only define on
+ *			physically contiguous heaps)
+ * @map_dma		map the memory for dma to a scatterlist
+ * @unmap_dma		unmap the memory for dma
+ * @map_kernel		map memory to the kernel
+ * @unmap_kernel	unmap memory to the kernel
+ * @map_user		map memory to userspace
+ *
+ * allocate, phys, and map_user return 0 on success, -errno on error.
+ * map_dma and map_kernel return pointer on success, ERR_PTR on error.
+ */
+struct ion_heap_ops {
+	int (*allocate) (struct ion_heap *heap,
+			 struct ion_buffer *buffer, unsigned long len,
+			 unsigned long align, unsigned long flags);
+	void (*free) (struct ion_buffer *buffer);
+	int (*phys) (struct ion_heap *heap, struct ion_buffer *buffer,
+		     ion_phys_addr_t *addr, size_t *len);
+	struct sg_table *(*map_dma) (struct ion_heap *heap,
+					struct ion_buffer *buffer);
+	void (*unmap_dma) (struct ion_heap *heap, struct ion_buffer *buffer);
+	void * (*map_kernel) (struct ion_heap *heap, struct ion_buffer *buffer);
+	void (*unmap_kernel) (struct ion_heap *heap, struct ion_buffer *buffer);
+	int (*map_user) (struct ion_heap *mapper, struct ion_buffer *buffer,
+			 struct vm_area_struct *vma);
+};
+
+/**
+ * heap flags - flags between the heaps and core ion code
+ */
+#define ION_HEAP_FLAG_DEFER_FREE (1 << 0)
+
+/**
+ * struct ion_heap - represents a heap in the system
+ * @node:		rb node to put the heap on the device's tree of heaps
+ * @dev:		back pointer to the ion_device
+ * @type:		type of heap
+ * @ops:		ops struct as above
+ * @flags:		flags
+ * @id:			id of heap, also indicates priority of this heap when
+ *			allocating.  These are specified by platform data and
+ *			MUST be unique
+ * @name:		used for debugging
+ * @shrinker:		a shrinker for the heap, if the heap caches system
+ *			memory, it must define a shrinker to return it on low
+ *			memory conditions, this includes system memory cached
+ *			in the deferred free lists for heaps that support it
+ * @free_list:		free list head if deferred free is used
+ * @free_list_size	size of the deferred free list in bytes
+ * @lock:		protects the free list
+ * @waitqueue:		queue to wait on from deferred free thread
+ * @task:		task struct of deferred free thread
+ * @debug_show:		called when heap debug file is read to add any
+ *			heap specific debug info to output
+ *
+ * Represents a pool of memory from which buffers can be made.  In some
+ * systems the only heap is regular system memory allocated via vmalloc.
+ * On others, some blocks might require large physically contiguous buffers
+ * that are allocated from a specially reserved heap.
+ */
+struct ion_heap {
+	struct plist_node node;
+	struct ion_device *dev;
+	enum ion_heap_type type;
+	struct ion_heap_ops *ops;
+	unsigned long flags;
+	unsigned int id;
+	const char *name;
+	struct shrinker shrinker;
+	struct list_head free_list;
+	size_t free_list_size;
+	spinlock_t free_lock;
+	wait_queue_head_t waitqueue;
+	struct task_struct *task;
+	int (*debug_show)(struct ion_heap *heap, struct seq_file *, void *);
+};
+
+/**
+ * ion_buffer_cached - this ion buffer is cached
+ * @buffer:		buffer
+ *
+ * indicates whether this ion buffer is cached
+ */
+bool ion_buffer_cached(struct ion_buffer *buffer);
+
+/**
+ * ion_buffer_fault_user_mappings - fault in user mappings of this buffer
+ * @buffer:		buffer
+ *
+ * indicates whether userspace mappings of this buffer will be faulted
+ * in, this can affect how buffers are allocated from the heap.
+ */
+bool ion_buffer_fault_user_mappings(struct ion_buffer *buffer);
+
+/**
+ * ion_device_create - allocates and returns an ion device
+ * @custom_ioctl:	arch specific ioctl function if applicable
+ *
+ * returns a valid device or -PTR_ERR
+ */
+struct ion_device *ion_device_create(long (*custom_ioctl)
+				     (struct ion_client *client,
+				      unsigned int cmd,
+				      unsigned long arg));
+
+/**
+ * ion_device_destroy - free and device and it's resource
+ * @dev:		the device
+ */
+void ion_device_destroy(struct ion_device *dev);
+
+/**
+ * ion_device_add_heap - adds a heap to the ion device
+ * @dev:		the device
+ * @heap:		the heap to add
+ */
+void ion_device_add_heap(struct ion_device *dev, struct ion_heap *heap);
+
+/**
+ * some helpers for common operations on buffers using the sg_table
+ * and vaddr fields
+ */
+void *ion_heap_map_kernel(struct ion_heap *, struct ion_buffer *);
+void ion_heap_unmap_kernel(struct ion_heap *, struct ion_buffer *);
+int ion_heap_map_user(struct ion_heap *, struct ion_buffer *,
+			struct vm_area_struct *);
+int ion_heap_buffer_zero(struct ion_buffer *buffer);
+
+/**
+ * ion_heap_init_deferred_free -- initialize deferred free functionality
+ * @heap:		the heap
+ *
+ * If a heap sets the ION_HEAP_FLAG_DEFER_FREE flag this function will
+ * be called to setup deferred frees. Calls to free the buffer will
+ * return immediately and the actual free will occur some time later
+ */
+int ion_heap_init_deferred_free(struct ion_heap *heap);
+
+/**
+ * ion_heap_freelist_add - add a buffer to the deferred free list
+ * @heap:		the heap
+ * @buffer:		the buffer
+ *
+ * Adds an item to the deferred freelist.
+ */
+void ion_heap_freelist_add(struct ion_heap *heap, struct ion_buffer *buffer);
+
+/**
+ * ion_heap_freelist_drain - drain the deferred free list
+ * @heap:		the heap
+ * @size:		ammount of memory to drain in bytes
+ *
+ * Drains the indicated amount of memory from the deferred freelist immediately.
+ * Returns the total amount freed.  The total freed may be higher depending
+ * on the size of the items in the list, or lower if there is insufficient
+ * total memory on the freelist.
+ */
+size_t ion_heap_freelist_drain(struct ion_heap *heap, size_t size);
+
+/**
+ * ion_heap_freelist_size - returns the size of the freelist in bytes
+ * @heap:		the heap
+ */
+size_t ion_heap_freelist_size(struct ion_heap *heap);
+
+
+/**
+ * functions for creating and destroying the built in ion heaps.
+ * architectures can add their own custom architecture specific
+ * heaps as appropriate.
+ */
+
+struct ion_heap *ion_heap_create(struct ion_platform_heap *);
+void ion_heap_destroy(struct ion_heap *);
+struct ion_heap *ion_system_heap_create(struct ion_platform_heap *);
+void ion_system_heap_destroy(struct ion_heap *);
+
+struct ion_heap *ion_system_contig_heap_create(struct ion_platform_heap *);
+void ion_system_contig_heap_destroy(struct ion_heap *);
+
+struct ion_heap *ion_carveout_heap_create(struct ion_platform_heap *);
+void ion_carveout_heap_destroy(struct ion_heap *);
+
+struct ion_heap *ion_chunk_heap_create(struct ion_platform_heap *);
+void ion_chunk_heap_destroy(struct ion_heap *);
+struct ion_heap *ion_cma_heap_create(struct ion_platform_heap *);
+void ion_cma_heap_destroy(struct ion_heap *);
+
+/**
+ * kernel api to allocate/free from carveout -- used when carveout is
+ * used to back an architecture specific custom heap
+ */
+ion_phys_addr_t ion_carveout_allocate(struct ion_heap *heap, unsigned long size,
+				      unsigned long align);
+void ion_carveout_free(struct ion_heap *heap, ion_phys_addr_t addr,
+		       unsigned long size);
+/**
+ * The carveout heap returns physical addresses, since 0 may be a valid
+ * physical address, this is used to indicate allocation failed
+ */
+#define ION_CARVEOUT_ALLOCATE_FAIL -1
+
+/**
+ * functions for creating and destroying a heap pool -- allows you
+ * to keep a pool of pre allocated memory to use from your heap.  Keeping
+ * a pool of memory that is ready for dma, ie any cached mapping have been
+ * invalidated from the cache, provides a significant peformance benefit on
+ * many systems */
+
+/**
+ * struct ion_page_pool - pagepool struct
+ * @high_count:		number of highmem items in the pool
+ * @low_count:		number of lowmem items in the pool
+ * @high_items:		list of highmem items
+ * @low_items:		list of lowmem items
+ * @shrinker:		a shrinker for the items
+ * @mutex:		lock protecting this struct and especially the count
+ *			item list
+ * @alloc:		function to be used to allocate pageory when the pool
+ *			is empty
+ * @free:		function to be used to free pageory back to the system
+ *			when the shrinker fires
+ * @gfp_mask:		gfp_mask to use from alloc
+ * @order:		order of pages in the pool
+ * @list:		plist node for list of pools
+ *
+ * Allows you to keep a pool of pre allocated pages to use from your heap.
+ * Keeping a pool of pages that is ready for dma, ie any cached mapping have
+ * been invalidated from the cache, provides a significant peformance benefit
+ * on many systems
+ */
+struct ion_page_pool {
+	int high_count;
+	int low_count;
+	struct list_head high_items;
+	struct list_head low_items;
+	struct mutex mutex;
+	gfp_t gfp_mask;
+	unsigned int order;
+	struct plist_node list;
+};
+
+struct ion_page_pool *ion_page_pool_create(gfp_t gfp_mask, unsigned int order);
+void ion_page_pool_destroy(struct ion_page_pool *);
+void *ion_page_pool_alloc(struct ion_page_pool *);
+void ion_page_pool_free(struct ion_page_pool *, struct page *);
+
+/** ion_page_pool_shrink - shrinks the size of the memory cached in the pool
+ * @pool:		the pool
+ * @gfp_mask:		the memory type to reclaim
+ * @nr_to_scan:		number of items to shrink in pages
+ *
+ * returns the number of items freed in pages
+ */
+int ion_page_pool_shrink(struct ion_page_pool *pool, gfp_t gfp_mask,
+			  int nr_to_scan);
+
+/**
+ * ion_pages_sync_for_device - cache flush pages for use with the specified
+ *                             device
+ * @dev:		the device the pages will be used with
+ * @page:		the first page to be flushed
+ * @size:		size in bytes of region to be flushed
+ * @dir:		direction of dma transfer
+ */
+void ion_pages_sync_for_device(struct device *dev, struct page *page,
+		size_t size, enum dma_data_direction dir);
+
+#endif /* _ION_PRIV_H */
diff --git a/drivers/staging/android/ion/ion_system_heap.c b/drivers/staging/android/ion/ion_system_heap.c
new file mode 100644
index 0000000..a78166d
--- /dev/null
+++ b/drivers/staging/android/ion/ion_system_heap.c
@@ -0,0 +1,476 @@
+/*
+ * drivers/staging/android/ion/ion_system_heap.c
+ *
+ * Copyright (C) 2011 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm/page.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/highmem.h>
+#include <linux/mm.h>
+#include <linux/scatterlist.h>
+#include <linux/seq_file.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include "ion.h"
+#include "ion_priv.h"
+
+static gfp_t high_order_gfp_flags = (GFP_HIGHUSER | __GFP_ZERO | __GFP_NOWARN |
+				     __GFP_NORETRY) & ~__GFP_WAIT;
+static gfp_t low_order_gfp_flags  = (GFP_HIGHUSER | __GFP_ZERO | __GFP_NOWARN);
+static const unsigned int orders[] = {8, 4, 0};
+static const int num_orders = ARRAY_SIZE(orders);
+static int order_to_index(unsigned int order)
+{
+	int i;
+	for (i = 0; i < num_orders; i++)
+		if (order == orders[i])
+			return i;
+	BUG();
+	return -1;
+}
+
+static unsigned int order_to_size(int order)
+{
+	return PAGE_SIZE << order;
+}
+
+struct ion_system_heap {
+	struct ion_heap heap;
+	struct ion_page_pool **pools;
+};
+
+struct page_info {
+	struct page *page;
+	unsigned int order;
+	struct list_head list;
+};
+
+static struct page *alloc_buffer_page(struct ion_system_heap *heap,
+				      struct ion_buffer *buffer,
+				      unsigned long order)
+{
+	bool cached = ion_buffer_cached(buffer);
+	struct ion_page_pool *pool = heap->pools[order_to_index(order)];
+	struct page *page;
+
+	if (!cached) {
+		page = ion_page_pool_alloc(pool);
+	} else {
+		gfp_t gfp_flags = low_order_gfp_flags;
+
+		if (order > 4)
+			gfp_flags = high_order_gfp_flags;
+		page = alloc_pages(gfp_flags, order);
+		if (!page)
+			return NULL;
+		ion_pages_sync_for_device(NULL, page, PAGE_SIZE << order,
+						DMA_BIDIRECTIONAL);
+	}
+	if (!page)
+		return NULL;
+
+	return page;
+}
+
+static void free_buffer_page(struct ion_system_heap *heap,
+			     struct ion_buffer *buffer, struct page *page,
+			     unsigned int order)
+{
+	bool cached = ion_buffer_cached(buffer);
+
+	if (!cached) {
+		struct ion_page_pool *pool = heap->pools[order_to_index(order)];
+		ion_page_pool_free(pool, page);
+	} else {
+		__free_pages(page, order);
+	}
+}
+
+
+static struct page_info *alloc_largest_available(struct ion_system_heap *heap,
+						 struct ion_buffer *buffer,
+						 unsigned long size,
+						 unsigned int max_order)
+{
+	struct page *page;
+	struct page_info *info;
+	int i;
+
+	info = kmalloc(sizeof(struct page_info), GFP_KERNEL);
+	if (!info)
+		return NULL;
+
+	for (i = 0; i < num_orders; i++) {
+		if (size < order_to_size(orders[i]))
+			continue;
+		if (max_order < orders[i])
+			continue;
+
+		page = alloc_buffer_page(heap, buffer, orders[i]);
+		if (!page)
+			continue;
+
+		info->page = page;
+		info->order = orders[i];
+		INIT_LIST_HEAD(&info->list);
+		return info;
+	}
+	kfree(info);
+
+	return NULL;
+}
+
+static int ion_system_heap_allocate(struct ion_heap *heap,
+				     struct ion_buffer *buffer,
+				     unsigned long size, unsigned long align,
+				     unsigned long flags)
+{
+	struct ion_system_heap *sys_heap = container_of(heap,
+							struct ion_system_heap,
+							heap);
+	struct sg_table *table;
+	struct scatterlist *sg;
+	int ret;
+	struct list_head pages;
+	struct page_info *info, *tmp_info;
+	int i = 0;
+	unsigned long size_remaining = PAGE_ALIGN(size);
+	unsigned int max_order = orders[0];
+
+	if (align > PAGE_SIZE)
+		return -EINVAL;
+
+	if (size / PAGE_SIZE > totalram_pages / 2)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&pages);
+	while (size_remaining > 0) {
+		info = alloc_largest_available(sys_heap, buffer, size_remaining,
+						max_order);
+		if (!info)
+			goto err;
+		list_add_tail(&info->list, &pages);
+		size_remaining -= (1 << info->order) * PAGE_SIZE;
+		max_order = info->order;
+		i++;
+	}
+	table = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
+	if (!table)
+		goto err;
+
+	ret = sg_alloc_table(table, i, GFP_KERNEL);
+	if (ret)
+		goto err1;
+
+	sg = table->sgl;
+	list_for_each_entry_safe(info, tmp_info, &pages, list) {
+		struct page *page = info->page;
+		sg_set_page(sg, page, (1 << info->order) * PAGE_SIZE, 0);
+		sg = sg_next(sg);
+		list_del(&info->list);
+		kfree(info);
+	}
+
+	buffer->priv_virt = table;
+	return 0;
+err1:
+	kfree(table);
+err:
+	list_for_each_entry_safe(info, tmp_info, &pages, list) {
+		free_buffer_page(sys_heap, buffer, info->page, info->order);
+		kfree(info);
+	}
+	return -ENOMEM;
+}
+
+static void ion_system_heap_free(struct ion_buffer *buffer)
+{
+	struct ion_heap *heap = buffer->heap;
+	struct ion_system_heap *sys_heap = container_of(heap,
+							struct ion_system_heap,
+							heap);
+	struct sg_table *table = buffer->sg_table;
+	bool cached = ion_buffer_cached(buffer);
+	struct scatterlist *sg;
+	LIST_HEAD(pages);
+	int i;
+
+	/* uncached pages come from the page pools, zero them before returning
+	   for security purposes (other allocations are zerod at alloc time */
+	if (!cached)
+		ion_heap_buffer_zero(buffer);
+
+	for_each_sg(table->sgl, sg, table->nents, i)
+		free_buffer_page(sys_heap, buffer, sg_page(sg),
+				get_order(sg->length));
+	sg_free_table(table);
+	kfree(table);
+}
+
+static struct sg_table *ion_system_heap_map_dma(struct ion_heap *heap,
+						struct ion_buffer *buffer)
+{
+	return buffer->priv_virt;
+}
+
+static void ion_system_heap_unmap_dma(struct ion_heap *heap,
+				      struct ion_buffer *buffer)
+{
+	return;
+}
+
+static struct ion_heap_ops system_heap_ops = {
+	.allocate = ion_system_heap_allocate,
+	.free = ion_system_heap_free,
+	.map_dma = ion_system_heap_map_dma,
+	.unmap_dma = ion_system_heap_unmap_dma,
+	.map_kernel = ion_heap_map_kernel,
+	.unmap_kernel = ion_heap_unmap_kernel,
+	.map_user = ion_heap_map_user,
+};
+
+static int ion_system_heap_shrink(struct shrinker *shrinker,
+				  struct shrink_control *sc) {
+
+	struct ion_heap *heap = container_of(shrinker, struct ion_heap,
+					     shrinker);
+	struct ion_system_heap *sys_heap = container_of(heap,
+							struct ion_system_heap,
+							heap);
+	int nr_total = 0;
+	int nr_freed = 0;
+	int i;
+
+	if (sc->nr_to_scan == 0)
+		goto end;
+
+	/* shrink the free list first, no point in zeroing the memory if
+	   we're just going to reclaim it */
+	nr_freed += ion_heap_freelist_drain(heap, sc->nr_to_scan * PAGE_SIZE) /
+		PAGE_SIZE;
+
+	if (nr_freed >= sc->nr_to_scan)
+		goto end;
+
+	for (i = 0; i < num_orders; i++) {
+		struct ion_page_pool *pool = sys_heap->pools[i];
+
+		nr_freed += ion_page_pool_shrink(pool, sc->gfp_mask,
+						 sc->nr_to_scan);
+		if (nr_freed >= sc->nr_to_scan)
+			break;
+	}
+
+end:
+	/* total number of items is whatever the page pools are holding
+	   plus whatever's in the freelist */
+	for (i = 0; i < num_orders; i++) {
+		struct ion_page_pool *pool = sys_heap->pools[i];
+		nr_total += ion_page_pool_shrink(pool, sc->gfp_mask, 0);
+	}
+	nr_total += ion_heap_freelist_size(heap) / PAGE_SIZE;
+	return nr_total;
+
+}
+
+static int ion_system_heap_debug_show(struct ion_heap *heap, struct seq_file *s,
+				      void *unused)
+{
+
+	struct ion_system_heap *sys_heap = container_of(heap,
+							struct ion_system_heap,
+							heap);
+	int i;
+	for (i = 0; i < num_orders; i++) {
+		struct ion_page_pool *pool = sys_heap->pools[i];
+		seq_printf(s, "%d order %u highmem pages in pool = %lu total\n",
+			   pool->high_count, pool->order,
+			   (1 << pool->order) * PAGE_SIZE * pool->high_count);
+		seq_printf(s, "%d order %u lowmem pages in pool = %lu total\n",
+			   pool->low_count, pool->order,
+			   (1 << pool->order) * PAGE_SIZE * pool->low_count);
+	}
+	return 0;
+}
+
+struct ion_heap *ion_system_heap_create(struct ion_platform_heap *unused)
+{
+	struct ion_system_heap *heap;
+	int i;
+
+	heap = kzalloc(sizeof(struct ion_system_heap), GFP_KERNEL);
+	if (!heap)
+		return ERR_PTR(-ENOMEM);
+	heap->heap.ops = &system_heap_ops;
+	heap->heap.type = ION_HEAP_TYPE_SYSTEM;
+	heap->heap.flags = ION_HEAP_FLAG_DEFER_FREE;
+	heap->pools = kzalloc(sizeof(struct ion_page_pool *) * num_orders,
+			      GFP_KERNEL);
+	if (!heap->pools)
+		goto err_alloc_pools;
+	for (i = 0; i < num_orders; i++) {
+		struct ion_page_pool *pool;
+		gfp_t gfp_flags = low_order_gfp_flags;
+
+		if (orders[i] > 4)
+			gfp_flags = high_order_gfp_flags;
+		pool = ion_page_pool_create(gfp_flags, orders[i]);
+		if (!pool)
+			goto err_create_pool;
+		heap->pools[i] = pool;
+	}
+
+	heap->heap.shrinker.shrink = ion_system_heap_shrink;
+	heap->heap.shrinker.seeks = DEFAULT_SEEKS;
+	heap->heap.shrinker.batch = 0;
+	register_shrinker(&heap->heap.shrinker);
+	heap->heap.debug_show = ion_system_heap_debug_show;
+	return &heap->heap;
+err_create_pool:
+	for (i = 0; i < num_orders; i++)
+		if (heap->pools[i])
+			ion_page_pool_destroy(heap->pools[i]);
+	kfree(heap->pools);
+err_alloc_pools:
+	kfree(heap);
+	return ERR_PTR(-ENOMEM);
+}
+
+void ion_system_heap_destroy(struct ion_heap *heap)
+{
+	struct ion_system_heap *sys_heap = container_of(heap,
+							struct ion_system_heap,
+							heap);
+	int i;
+
+	for (i = 0; i < num_orders; i++)
+		ion_page_pool_destroy(sys_heap->pools[i]);
+	kfree(sys_heap->pools);
+	kfree(sys_heap);
+}
+
+static int ion_system_contig_heap_allocate(struct ion_heap *heap,
+					   struct ion_buffer *buffer,
+					   unsigned long len,
+					   unsigned long align,
+					   unsigned long flags)
+{
+	int order = get_order(len);
+	struct page *page;
+	struct sg_table *table;
+	unsigned long i;
+	int ret;
+
+	if (align > (PAGE_SIZE << order))
+		return -EINVAL;
+
+	page = alloc_pages(low_order_gfp_flags, order);
+	if (!page)
+		return -ENOMEM;
+
+	split_page(page, order);
+
+	len = PAGE_ALIGN(len);
+	for (i = len >> PAGE_SHIFT; i < (1 << order); i++)
+		__free_page(page + i);
+
+	table = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
+	if (!table) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	ret = sg_alloc_table(table, 1, GFP_KERNEL);
+	if (ret)
+		goto out;
+
+	sg_set_page(table->sgl, page, len, 0);
+
+	buffer->priv_virt = table;
+
+	ion_pages_sync_for_device(NULL, page, len, DMA_BIDIRECTIONAL);
+
+	return 0;
+
+out:
+	for (i = 0; i < len >> PAGE_SHIFT; i++)
+		__free_page(page + i);
+	kfree(table);
+	return ret;
+}
+
+static void ion_system_contig_heap_free(struct ion_buffer *buffer)
+{
+	struct sg_table *table = buffer->priv_virt;
+	struct page *page = sg_page(table->sgl);
+	unsigned long pages = PAGE_ALIGN(buffer->size) >> PAGE_SHIFT;
+	unsigned long i;
+
+	for (i = 0; i < pages; i++)
+		__free_page(page + i);
+	sg_free_table(table);
+	kfree(table);
+}
+
+static int ion_system_contig_heap_phys(struct ion_heap *heap,
+				       struct ion_buffer *buffer,
+				       ion_phys_addr_t *addr, size_t *len)
+{
+	struct sg_table *table = buffer->priv_virt;
+	struct page *page = sg_page(table->sgl);
+	*addr = page_to_phys(page);
+	*len = buffer->size;
+	return 0;
+}
+
+static struct sg_table *ion_system_contig_heap_map_dma(struct ion_heap *heap,
+						struct ion_buffer *buffer)
+{
+	return buffer->priv_virt;
+}
+
+static void ion_system_contig_heap_unmap_dma(struct ion_heap *heap,
+					     struct ion_buffer *buffer)
+{
+}
+
+static struct ion_heap_ops kmalloc_ops = {
+	.allocate = ion_system_contig_heap_allocate,
+	.free = ion_system_contig_heap_free,
+	.phys = ion_system_contig_heap_phys,
+	.map_dma = ion_system_contig_heap_map_dma,
+	.unmap_dma = ion_system_contig_heap_unmap_dma,
+	.map_kernel = ion_heap_map_kernel,
+	.unmap_kernel = ion_heap_unmap_kernel,
+	.map_user = ion_heap_map_user,
+};
+
+struct ion_heap *ion_system_contig_heap_create(struct ion_platform_heap *unused)
+{
+	struct ion_heap *heap;
+
+	heap = kzalloc(sizeof(struct ion_heap), GFP_KERNEL);
+	if (!heap)
+		return ERR_PTR(-ENOMEM);
+	heap->ops = &kmalloc_ops;
+	heap->type = ION_HEAP_TYPE_SYSTEM_CONTIG;
+	return heap;
+}
+
+void ion_system_contig_heap_destroy(struct ion_heap *heap)
+{
+	kfree(heap);
+}
+
diff --git a/drivers/staging/android/ion/ion_test.c b/drivers/staging/android/ion/ion_test.c
new file mode 100644
index 0000000..654acb5
--- /dev/null
+++ b/drivers/staging/android/ion/ion_test.c
@@ -0,0 +1,282 @@
+/*
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt) "ion-test: " fmt
+
+#include <linux/dma-buf.h>
+#include <linux/dma-direction.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+#include <linux/vmalloc.h>
+
+#include "ion.h"
+#include "../uapi/ion_test.h"
+
+#define u64_to_uptr(x) ((void __user *)(unsigned long)(x))
+
+struct ion_test_device {
+	struct miscdevice misc;
+};
+
+struct ion_test_data {
+	struct dma_buf *dma_buf;
+	struct device *dev;
+};
+
+static int ion_handle_test_dma(struct device *dev, struct dma_buf *dma_buf,
+		void __user *ptr, size_t offset, size_t size, bool write)
+{
+	int ret = 0;
+	struct dma_buf_attachment *attach;
+	struct sg_table *table;
+	pgprot_t pgprot = pgprot_writecombine(PAGE_KERNEL);
+	enum dma_data_direction dir = write ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
+	struct sg_page_iter sg_iter;
+	unsigned long offset_page;
+
+	attach = dma_buf_attach(dma_buf, dev);
+	if (IS_ERR(attach))
+		return PTR_ERR(attach);
+
+	table = dma_buf_map_attachment(attach, dir);
+	if (IS_ERR(table))
+		return PTR_ERR(table);
+
+	offset_page = offset >> PAGE_SHIFT;
+	offset %= PAGE_SIZE;
+
+	for_each_sg_page(table->sgl, &sg_iter, table->nents, offset_page) {
+		struct page *page = sg_page_iter_page(&sg_iter);
+		void *vaddr = vmap(&page, 1, VM_MAP, pgprot);
+		size_t to_copy = PAGE_SIZE - offset;
+
+		to_copy = min(to_copy, size);
+		if (!vaddr) {
+			ret = -ENOMEM;
+			goto err;
+		}
+
+		if (write)
+			ret = copy_from_user(vaddr + offset, ptr, to_copy);
+		else
+			ret = copy_to_user(ptr, vaddr + offset, to_copy);
+
+		vunmap(vaddr);
+		if (ret) {
+			ret = -EFAULT;
+			goto err;
+		}
+		size -= to_copy;
+		if (!size)
+			break;
+		ptr += to_copy;
+		offset = 0;
+	}
+
+err:
+	dma_buf_unmap_attachment(attach, table, dir);
+	dma_buf_detach(dma_buf, attach);
+	return ret;
+}
+
+static int ion_handle_test_kernel(struct dma_buf *dma_buf, void __user *ptr,
+		size_t offset, size_t size, bool write)
+{
+	int ret;
+	unsigned long page_offset = offset >> PAGE_SHIFT;
+	size_t copy_offset = offset % PAGE_SIZE;
+	size_t copy_size = size;
+	enum dma_data_direction dir = write ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
+
+	if (offset > dma_buf->size || size > dma_buf->size - offset)
+		return -EINVAL;
+
+	ret = dma_buf_begin_cpu_access(dma_buf, offset, size, dir);
+	if (ret)
+		return ret;
+
+	while (copy_size > 0) {
+		size_t to_copy;
+		void *vaddr = dma_buf_kmap(dma_buf, page_offset);
+
+		if (!vaddr)
+			goto err;
+
+		to_copy = min_t(size_t, PAGE_SIZE - copy_offset, copy_size);
+
+		if (write)
+			ret = copy_from_user(vaddr + copy_offset, ptr, to_copy);
+		else
+			ret = copy_to_user(ptr, vaddr + copy_offset, to_copy);
+
+		dma_buf_kunmap(dma_buf, page_offset, vaddr);
+		if (ret) {
+			ret = -EFAULT;
+			goto err;
+		}
+
+		copy_size -= to_copy;
+		ptr += to_copy;
+		page_offset++;
+		copy_offset = 0;
+	}
+err:
+	dma_buf_end_cpu_access(dma_buf, offset, size, dir);
+	return ret;
+}
+
+static long ion_test_ioctl(struct file *filp, unsigned int cmd,
+						unsigned long arg)
+{
+	struct ion_test_data *test_data = filp->private_data;
+	int ret = 0;
+
+	union {
+		struct ion_test_rw_data test_rw;
+	} data;
+
+	if (_IOC_SIZE(cmd) > sizeof(data))
+		return -EINVAL;
+
+	if (_IOC_DIR(cmd) & _IOC_WRITE)
+		if (copy_from_user(&data, (void __user *)arg, _IOC_SIZE(cmd)))
+			return -EFAULT;
+
+	switch (cmd) {
+	case ION_IOC_TEST_SET_FD:
+	{
+		struct dma_buf *dma_buf = NULL;
+		int fd = arg;
+
+		if (fd >= 0) {
+			dma_buf = dma_buf_get((int)arg);
+			if (IS_ERR(dma_buf))
+				return PTR_ERR(dma_buf);
+		}
+		if (test_data->dma_buf)
+			dma_buf_put(test_data->dma_buf);
+		test_data->dma_buf = dma_buf;
+		break;
+	}
+	case ION_IOC_TEST_DMA_MAPPING:
+	{
+		ret = ion_handle_test_dma(test_data->dev, test_data->dma_buf,
+					u64_to_uptr(data.test_rw.ptr),
+					data.test_rw.offset, data.test_rw.size,
+					data.test_rw.write);
+		break;
+	}
+	case ION_IOC_TEST_KERNEL_MAPPING:
+	{
+		ret = ion_handle_test_kernel(test_data->dma_buf,
+					u64_to_uptr(data.test_rw.ptr),
+					data.test_rw.offset, data.test_rw.size,
+					data.test_rw.write);
+		break;
+	}
+	default:
+		return -ENOTTY;
+	}
+
+	if (_IOC_DIR(cmd) & _IOC_READ) {
+		if (copy_to_user((void __user *)arg, &data, sizeof(data)))
+			return -EFAULT;
+	}
+	return ret;
+}
+
+static int ion_test_open(struct inode *inode, struct file *file)
+{
+	struct ion_test_data *data;
+	struct miscdevice *miscdev = file->private_data;
+
+	data = kzalloc(sizeof(struct ion_test_data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	data->dev = miscdev->parent;
+
+	file->private_data = data;
+
+	return 0;
+}
+
+static int ion_test_release(struct inode *inode, struct file *file)
+{
+	struct ion_test_data *data = file->private_data;
+
+	kfree(data);
+
+	return 0;
+}
+
+static const struct file_operations ion_test_fops = {
+	.owner = THIS_MODULE,
+	.unlocked_ioctl = ion_test_ioctl,
+	.compat_ioctl = ion_test_ioctl,
+	.open = ion_test_open,
+	.release = ion_test_release,
+};
+
+static int __init ion_test_probe(struct platform_device *pdev)
+{
+	int ret;
+	struct ion_test_device *testdev;
+
+	testdev = devm_kzalloc(&pdev->dev, sizeof(struct ion_test_device),
+				GFP_KERNEL);
+	if (!testdev)
+		return -ENOMEM;
+
+	testdev->misc.minor = MISC_DYNAMIC_MINOR;
+	testdev->misc.name = "ion-test";
+	testdev->misc.fops = &ion_test_fops;
+	testdev->misc.parent = &pdev->dev;
+	ret = misc_register(&testdev->misc);
+	if (ret) {
+		pr_err("failed to register misc device.\n");
+		return ret;
+	}
+
+	platform_set_drvdata(pdev, testdev);
+
+	return 0;
+}
+
+static struct platform_driver ion_test_platform_driver = {
+	.driver = {
+		.name = "ion-test",
+	},
+};
+
+static int __init ion_test_init(void)
+{
+	platform_device_register_simple("ion-test", -1, NULL, 0);
+	return platform_driver_probe(&ion_test_platform_driver, ion_test_probe);
+}
+
+static void __exit ion_test_exit(void)
+{
+	platform_driver_unregister(&ion_test_platform_driver);
+}
+
+module_init(ion_test_init);
+module_exit(ion_test_exit);
diff --git a/drivers/staging/android/ion/tegra/Makefile b/drivers/staging/android/ion/tegra/Makefile
new file mode 100644
index 0000000..11cd003
--- /dev/null
+++ b/drivers/staging/android/ion/tegra/Makefile
@@ -0,0 +1 @@
+obj-y += tegra_ion.o
diff --git a/drivers/staging/android/ion/tegra/tegra_ion.c b/drivers/staging/android/ion/tegra/tegra_ion.c
new file mode 100644
index 0000000..3474c65
--- /dev/null
+++ b/drivers/staging/android/ion/tegra/tegra_ion.c
@@ -0,0 +1,84 @@
+/*
+ * drivers/gpu/tegra/tegra_ion.c
+ *
+ * Copyright (C) 2011 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include "../ion.h"
+#include "../ion_priv.h"
+
+static struct ion_device *idev;
+static int num_heaps;
+static struct ion_heap **heaps;
+
+static int tegra_ion_probe(struct platform_device *pdev)
+{
+	struct ion_platform_data *pdata = pdev->dev.platform_data;
+	int err;
+	int i;
+
+	num_heaps = pdata->nr;
+
+	heaps = kzalloc(sizeof(struct ion_heap *) * pdata->nr, GFP_KERNEL);
+
+	idev = ion_device_create(NULL);
+	if (IS_ERR_OR_NULL(idev)) {
+		kfree(heaps);
+		return PTR_ERR(idev);
+	}
+
+	/* create the heaps as specified in the board file */
+	for (i = 0; i < num_heaps; i++) {
+		struct ion_platform_heap *heap_data = &pdata->heaps[i];
+
+		heaps[i] = ion_heap_create(heap_data);
+		if (IS_ERR_OR_NULL(heaps[i])) {
+			err = PTR_ERR(heaps[i]);
+			goto err;
+		}
+		ion_device_add_heap(idev, heaps[i]);
+	}
+	platform_set_drvdata(pdev, idev);
+	return 0;
+err:
+	for (i = 0; i < num_heaps; i++) {
+		if (heaps[i])
+			ion_heap_destroy(heaps[i]);
+	}
+	kfree(heaps);
+	return err;
+}
+
+static int tegra_ion_remove(struct platform_device *pdev)
+{
+	struct ion_device *idev = platform_get_drvdata(pdev);
+	int i;
+
+	ion_device_destroy(idev);
+	for (i = 0; i < num_heaps; i++)
+		ion_heap_destroy(heaps[i]);
+	kfree(heaps);
+	return 0;
+}
+
+static struct platform_driver ion_driver = {
+	.probe = tegra_ion_probe,
+	.remove = tegra_ion_remove,
+	.driver = { .name = "ion-tegra" }
+};
+
+module_platform_driver(ion_driver);
+
diff --git a/drivers/staging/android/uapi/ion.h b/drivers/staging/android/uapi/ion.h
new file mode 100644
index 0000000..3af51b4
--- /dev/null
+++ b/drivers/staging/android/uapi/ion.h
@@ -0,0 +1,204 @@
+/*
+ * drivers/staging/android/uapi/ion.h
+ *
+ * Copyright (C) 2011 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _UAPI_LINUX_ION_H
+#define _UAPI_LINUX_ION_H
+
+#include <linux/ioctl.h>
+#include <linux/types.h>
+
+typedef int ion_user_handle_t;
+
+/**
+ * enum ion_heap_types - list of all possible types of heaps
+ * @ION_HEAP_TYPE_SYSTEM:	 memory allocated via vmalloc
+ * @ION_HEAP_TYPE_SYSTEM_CONTIG: memory allocated via kmalloc
+ * @ION_HEAP_TYPE_CARVEOUT:	 memory allocated from a prereserved
+ * 				 carveout heap, allocations are physically
+ * 				 contiguous
+ * @ION_HEAP_TYPE_DMA:		 memory allocated via DMA API
+ * @ION_NUM_HEAPS:		 helper for iterating over heaps, a bit mask
+ * 				 is used to identify the heaps, so only 32
+ * 				 total heap types are supported
+ */
+enum ion_heap_type {
+	ION_HEAP_TYPE_SYSTEM,
+	ION_HEAP_TYPE_SYSTEM_CONTIG,
+	ION_HEAP_TYPE_CARVEOUT,
+	ION_HEAP_TYPE_CHUNK,
+	ION_HEAP_TYPE_DMA,
+	ION_HEAP_TYPE_CUSTOM, /* must be last so device specific heaps always
+				 are at the end of this enum */
+	ION_NUM_HEAPS = 16,
+};
+
+#define ION_HEAP_SYSTEM_MASK		(1 << ION_HEAP_TYPE_SYSTEM)
+#define ION_HEAP_SYSTEM_CONTIG_MASK	(1 << ION_HEAP_TYPE_SYSTEM_CONTIG)
+#define ION_HEAP_CARVEOUT_MASK		(1 << ION_HEAP_TYPE_CARVEOUT)
+#define ION_HEAP_TYPE_DMA_MASK		(1 << ION_HEAP_TYPE_DMA)
+
+#define ION_NUM_HEAP_IDS		sizeof(unsigned int) * 8
+
+/**
+ * allocation flags - the lower 16 bits are used by core ion, the upper 16
+ * bits are reserved for use by the heaps themselves.
+ */
+#define ION_FLAG_CACHED 1		/* mappings of this buffer should be
+					   cached, ion will do cache
+					   maintenance when the buffer is
+					   mapped for dma */
+#define ION_FLAG_CACHED_NEEDS_SYNC 2	/* mappings of this buffer will created
+					   at mmap time, if this is set
+					   caches must be managed manually */
+
+/**
+ * DOC: Ion Userspace API
+ *
+ * create a client by opening /dev/ion
+ * most operations handled via following ioctls
+ *
+ */
+
+/**
+ * struct ion_allocation_data - metadata passed from userspace for allocations
+ * @len:		size of the allocation
+ * @align:		required alignment of the allocation
+ * @heap_id_mask:	mask of heap ids to allocate from
+ * @flags:		flags passed to heap
+ * @handle:		pointer that will be populated with a cookie to use to 
+ *			refer to this allocation
+ *
+ * Provided by userspace as an argument to the ioctl
+ */
+struct ion_allocation_data {
+	size_t len;
+	size_t align;
+	unsigned int heap_id_mask;
+	unsigned int flags;
+	ion_user_handle_t handle;
+};
+
+/**
+ * struct ion_fd_data - metadata passed to/from userspace for a handle/fd pair
+ * @handle:	a handle
+ * @fd:		a file descriptor representing that handle
+ *
+ * For ION_IOC_SHARE or ION_IOC_MAP userspace populates the handle field with
+ * the handle returned from ion alloc, and the kernel returns the file
+ * descriptor to share or map in the fd field.  For ION_IOC_IMPORT, userspace
+ * provides the file descriptor and the kernel returns the handle.
+ */
+struct ion_fd_data {
+	ion_user_handle_t handle;
+	int fd;
+};
+
+/**
+ * struct ion_handle_data - a handle passed to/from the kernel
+ * @handle:	a handle
+ */
+struct ion_handle_data {
+	ion_user_handle_t handle;
+};
+
+/**
+ * struct ion_custom_data - metadata passed to/from userspace for a custom ioctl
+ * @cmd:	the custom ioctl function to call
+ * @arg:	additional data to pass to the custom ioctl, typically a user
+ *		pointer to a predefined structure
+ *
+ * This works just like the regular cmd and arg fields of an ioctl.
+ */
+struct ion_custom_data {
+	unsigned int cmd;
+	unsigned long arg;
+};
+
+struct ion_phys_data {
+	ion_user_handle_t handle;
+	unsigned long addr;
+	size_t len;
+};
+
+#define ION_IOC_MAGIC		'I'
+
+/**
+ * DOC: ION_IOC_ALLOC - allocate memory
+ *
+ * Takes an ion_allocation_data struct and returns it with the handle field
+ * populated with the opaque handle for the allocation.
+ */
+#define ION_IOC_ALLOC		_IOWR(ION_IOC_MAGIC, 0, \
+				      struct ion_allocation_data)
+
+/**
+ * DOC: ION_IOC_FREE - free memory
+ *
+ * Takes an ion_handle_data struct and frees the handle.
+ */
+#define ION_IOC_FREE		_IOWR(ION_IOC_MAGIC, 1, struct ion_handle_data)
+
+/**
+ * DOC: ION_IOC_MAP - get a file descriptor to mmap
+ *
+ * Takes an ion_fd_data struct with the handle field populated with a valid
+ * opaque handle.  Returns the struct with the fd field set to a file
+ * descriptor open in the current address space.  This file descriptor
+ * can then be used as an argument to mmap.
+ */
+#define ION_IOC_MAP		_IOWR(ION_IOC_MAGIC, 2, struct ion_fd_data)
+
+/**
+ * DOC: ION_IOC_SHARE - creates a file descriptor to use to share an allocation
+ *
+ * Takes an ion_fd_data struct with the handle field populated with a valid
+ * opaque handle.  Returns the struct with the fd field set to a file
+ * descriptor open in the current address space.  This file descriptor
+ * can then be passed to another process.  The corresponding opaque handle can
+ * be retrieved via ION_IOC_IMPORT.
+ */
+#define ION_IOC_SHARE		_IOWR(ION_IOC_MAGIC, 4, struct ion_fd_data)
+
+/**
+ * DOC: ION_IOC_IMPORT - imports a shared file descriptor
+ *
+ * Takes an ion_fd_data struct with the fd field populated with a valid file
+ * descriptor obtained from ION_IOC_SHARE and returns the struct with the handle
+ * filed set to the corresponding opaque handle.
+ */
+#define ION_IOC_IMPORT		_IOWR(ION_IOC_MAGIC, 5, struct ion_fd_data)
+
+/**
+ * DOC: ION_IOC_SYNC - syncs a shared file descriptors to memory
+ *
+ * Deprecated in favor of using the dma_buf api's correctly (syncing
+ * will happend automatically when the buffer is mapped to a device).
+ * If necessary should be used after touching a cached buffer from the cpu,
+ * this will make the buffer in memory coherent.
+ */
+#define ION_IOC_SYNC		_IOWR(ION_IOC_MAGIC, 7, struct ion_fd_data)
+
+/**
+ * DOC: ION_IOC_CUSTOM - call architecture specific ion ioctl
+ *
+ * Takes the argument of the architecture specific ioctl to call and
+ * passes appropriate userdata for that ioctl
+ */
+#define ION_IOC_CUSTOM		_IOWR(ION_IOC_MAGIC, 6, struct ion_custom_data)
+
+#define ION_IOC_PHYS		_IOWR(ION_IOC_MAGIC, 8, struct ion_phys_data)
+
+#endif /* _UAPI_LINUX_ION_H */
diff --git a/drivers/staging/rtl8192u/ieee80211/ieee80211.h b/drivers/staging/rtl8192u/ieee80211/ieee80211.h
index 1c0a1db..8eb415b 100644
--- a/drivers/staging/rtl8192u/ieee80211/ieee80211.h
+++ b/drivers/staging/rtl8192u/ieee80211/ieee80211.h
@@ -2251,7 +2251,7 @@ static inline void *ieee80211_priv(struct net_device *dev)
 	return ((struct ieee80211_device *)netdev_priv(dev))->priv;
 }
 
-extern inline int ieee80211_is_empty_essid(const char *essid, int essid_len)
+static inline int ieee80211_is_empty_essid(const char *essid, int essid_len)
 {
 	/* Single white space is for Linksys APs */
 	if (essid_len == 1 && essid[0] == ' ')
@@ -2267,7 +2267,7 @@ extern inline int ieee80211_is_empty_essid(const char *essid, int essid_len)
 	return 1;
 }
 
-extern inline int ieee80211_is_valid_mode(struct ieee80211_device *ieee, int mode)
+static inline int ieee80211_is_valid_mode(struct ieee80211_device *ieee, int mode)
 {
 	/*
 	 * It is possible for both access points and our device to support
@@ -2293,7 +2293,7 @@ extern inline int ieee80211_is_valid_mode(struct ieee80211_device *ieee, int mod
 	return 0;
 }
 
-extern inline int ieee80211_get_hdrlen(u16 fc)
+static inline int ieee80211_get_hdrlen(u16 fc)
 {
 	int hdrlen = IEEE80211_3ADDR_LEN;
 
@@ -2579,12 +2579,12 @@ void ieee80211_softmac_scan_syncro(struct ieee80211_device *ieee);
 
 extern const long ieee80211_wlan_frequencies[];
 
-extern inline void ieee80211_increment_scans(struct ieee80211_device *ieee)
+static inline void ieee80211_increment_scans(struct ieee80211_device *ieee)
 {
 	ieee->scans++;
 }
 
-extern inline int ieee80211_get_scans(struct ieee80211_device *ieee)
+static inline int ieee80211_get_scans(struct ieee80211_device *ieee)
 {
 	return ieee->scans;
 }
diff --git a/drivers/staging/rtl8712/ieee80211.h b/drivers/staging/rtl8712/ieee80211.h
index 3c0092b..1e7b55b 100644
--- a/drivers/staging/rtl8712/ieee80211.h
+++ b/drivers/staging/rtl8712/ieee80211.h
@@ -734,7 +734,7 @@ enum ieee80211_state {
 #define IEEE_G            (1<<2)
 #define IEEE_MODE_MASK    (IEEE_A|IEEE_B|IEEE_G)
 
-extern inline int ieee80211_is_empty_essid(const char *essid, int essid_len)
+static inline int ieee80211_is_empty_essid(const char *essid, int essid_len)
 {
 	/* Single white space is for Linksys APs */
 	if (essid_len == 1 && essid[0] == ' ')
@@ -748,7 +748,7 @@ extern inline int ieee80211_is_empty_essid(const char *essid, int essid_len)
 	return 1;
 }
 
-extern inline int ieee80211_get_hdrlen(u16 fc)
+static inline int ieee80211_get_hdrlen(u16 fc)
 {
 	int hdrlen = 24;
 
diff --git a/drivers/tty/serial/8250/8250.c b/drivers/tty/serial/8250/8250.c
index 5fe2191..43552fe 100644
--- a/drivers/tty/serial/8250/8250.c
+++ b/drivers/tty/serial/8250/8250.c
@@ -422,13 +422,25 @@ static void mem_serial_out(struct uart_port *p, int offset, int value)
 static void mem32_serial_out(struct uart_port *p, int offset, int value)
 {
 	offset = map_8250_out_reg(p, offset) << p->regshift;
+#ifdef CONFIG_BRCMSTB
+	/* not on PCI; avoid endian swapping */
+	__raw_writel(value, p->membase + offset);
+
+	/* flush out the write transaction (required on BMIPS5000) */
+	mb();
+#else
 	writel(value, p->membase + offset);
+#endif
 }
 
 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
 {
 	offset = map_8250_in_reg(p, offset) << p->regshift;
+#ifdef CONFIG_BRCMSTB
+	return __raw_readl(p->membase + offset);
+#else
 	return readl(p->membase + offset);
+#endif
 }
 
 static unsigned int au_serial_in(struct uart_port *p, int offset)
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 76316a3..6d727ea 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -26,6 +26,7 @@ config USB_ARCH_HAS_OHCI
 	# MIPS:
 	default y if MIPS_ALCHEMY
 	default y if MACH_JZ4740
+	default y if BRCMSTB
 	# more:
 	default PCI
 
@@ -48,6 +49,7 @@ config USB_ARCH_HAS_EHCI
 	default y if SPARC_LEON
 	default y if ARCH_MMP
 	default y if MACH_LOONGSON1
+	default y if BRCMSTB
 	default PCI
 
 # some non-PCI HCDs implement xHCI
@@ -82,6 +84,7 @@ config USB_ARCH_HAS_HCD
 	default y if ARM				# SL-811
 	default y if BLACKFIN				# SL-811
 	default y if SUPERH				# r8a66597-hcd
+	default y if BRCMSTB
 	default PCI
 
 # ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface.
diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
index 53a7bc0..88ffd89 100644
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_USB_DWC3)		+= dwc3/
 obj-$(CONFIG_USB_MON)		+= mon/
 
 obj-$(CONFIG_PCI)		+= host/
+obj-$(CONFIG_BRCM_USB)		+= host/
 obj-$(CONFIG_USB_EHCI_HCD)	+= host/
 obj-$(CONFIG_USB_ISP116X_HCD)	+= host/
 obj-$(CONFIG_USB_OHCI_HCD)	+= host/
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index 65ff69a..82e36d4 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -2467,6 +2467,47 @@ static int check_port_resume_type(struct usb_device *udev,
 	return status;
 }
 
+/*
+ * There are some SS USB devices which take longer time for link training.
+ * XHCI specs 4.19.4 says that when Link training is successful, port
+ * sets CCS bit to 1. So if SW reads port status before successful link
+ * training, then it will not find device to be present.
+ * USB Analyzer log with such buggy devices show that in some cases
+ * device switch on the RX termination after long delay of host enabling
+ * the VBUS. In few other cases it has been seen that device fails to
+ * negotiate link training in first attempt. It has been
+ * reported till now that few devices take as long as 2000 ms to train
+ * the link after host enabling its VBUS and termination. Following
+ * routine implements a 2000 ms timeout for link training. If in a case
+ * link trains before timeout, loop will exit earlier.
+ *
+ * There are also some 2.0 hard drive based devices and 3.0 thumb
+ * drives that, when plugged into a 2.0 only port, take a long
+ * time to set CCS after VBUS enable.
+ *
+ * FIXME: If a device was connected before suspend, but was removed
+ * while system was asleep, then the loop in the following routine will
+ * only exit at timeout.
+ *
+ * This routine should only be called when persist is enabled.
+ */
+static int wait_for_connected(struct usb_device *udev,
+		struct usb_hub *hub, int *port1,
+		u16 *portchange, u16 *portstatus)
+{
+	int status = 0, delay_ms = 0;
+
+	while (delay_ms < 2000) {
+		if (status || *portstatus & USB_PORT_STAT_CONNECTION)
+			break;
+		msleep(20);
+		delay_ms += 20;
+		status = hub_port_status(hub, *port1, portstatus, portchange);
+	}
+	dev_dbg(&udev->dev, "Waited %dms for CONNECT\n", delay_ms);
+	return status;
+}
+
 #ifdef	CONFIG_USB_SUSPEND
 /*
  * usb_disable_function_remotewakeup - disable usb3.0
@@ -2811,6 +2852,9 @@ int usb_port_resume(struct usb_device *udev, pm_message_t msg)
 
 	clear_bit(port1, hub->busy_bits);
 
+	if (udev->persist_enabled)
+		status = wait_for_connected(udev, hub, &port1, &portchange,
+				&portstatus);
 	status = check_port_resume_type(udev,
 			hub, port1, status, portchange, portstatus);
 	if (status == 0)
@@ -2862,6 +2906,9 @@ int usb_port_resume(struct usb_device *udev, pm_message_t msg)
 	u16		portchange, portstatus;
 
 	status = hub_port_status(hub, port1, &portstatus, &portchange);
+	if (udev->persist_enabled)
+		status = wait_for_connected(udev, hub, &port1, &portchange,
+				&portstatus);
 	status = check_port_resume_type(udev,
 			hub, port1, status, portchange, portstatus);
 
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 0982bcc..2bb6d5c 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -22,6 +22,7 @@ endif
 obj-$(CONFIG_USB_WHCI_HCD)	+= whci/
 
 obj-$(CONFIG_PCI)		+= pci-quirks.o
+obj-$(CONFIG_BRCM_USB)		+= usb-brcm.o ehci-brcm.o ohci-brcm.o
 
 obj-$(CONFIG_USB_EHCI_HCD)	+= ehci-hcd.o
 obj-$(CONFIG_USB_OXU210HP_HCD)	+= oxu210hp-hcd.o
diff --git a/drivers/usb/host/ehci-brcm.c b/drivers/usb/host/ehci-brcm.c
new file mode 100644
index 0000000..49ebc7c
--- /dev/null
+++ b/drivers/usb/host/ehci-brcm.c
@@ -0,0 +1,313 @@
+/*
+ * Copyright (C) 2009 - 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include "usb-brcm.h"
+
+static struct platform_driver	ehci_hcd_brcm_driver;
+#define PLATFORM_DRIVER		ehci_hcd_brcm_driver
+
+#include "ehci-hcd.c"
+
+/* catch unwanted redefinitions */
+#define CONFIG_PCI		0
+
+/* for global USB settings, see arch/mips/brcmstb/bchip.c */
+
+static int ehci_brcm_reset(struct usb_hcd *hcd)
+{
+	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
+	int ret;
+
+	ehci->big_endian_mmio = 1;
+
+	ehci->caps = (struct ehci_caps *) hcd->regs;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)
+	ehci->regs = (struct ehci_regs *) (hcd->regs +
+		HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)));
+#else
+	ehci->regs = (struct ehci_regs *) (hcd->regs +
+		HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)));
+#endif
+	dbg_hcs_params(ehci, "reset");
+	dbg_hcc_params(ehci, "reset");
+
+	/* cache this readonly data; minimize PCI reads */
+	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
+
+	/* This fixes the lockup during reboot due to prior interrupts */
+	ehci_writel(ehci, CMD_RESET, &ehci->regs->command);
+	mdelay(10);
+
+	/*
+	 * SWLINUX-1705: Avoid OUT packet underflows during high memory
+	 *   bus usage
+	 * port_status[0x0f] = Broadcom-proprietary USB_EHCI_INSNREG00 @ 0x90
+	 */
+	ehci_writel(ehci, 0x00800040, &ehci->regs->port_status[0x10]);
+	ehci_writel(ehci, 0x00000001, &ehci->regs->port_status[0x12]);
+
+	/* force HC to halt state */
+	ehci_halt(ehci);
+
+	ret = ehci_init(hcd);
+	if (ret)
+		return ret;
+	ehci_reset(ehci);
+	ehci_port_power(ehci, 1);
+
+	return ret;
+}
+
+static void ehci_brcm_shutdown(struct usb_hcd *hcd)
+{
+	if (test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags))
+		ehci_shutdown(hcd);
+}
+
+/* ehci_brcm_wait_for_sof
+ * Wait for start of next microframe, then wait extra delay microseconds
+ */
+static inline void ehci_brcm_wait_for_sof(struct ehci_hcd *ehci, u32 delay)
+{
+	int frame_idx = ehci_readl(ehci, &ehci->regs->frame_index);
+
+	while (frame_idx == ehci_readl(ehci, &ehci->regs->frame_index))
+		;
+	udelay(delay);
+}
+
+/* ehci_brcm_hub_control
+ * Intercept echi-hcd request to complete RESUME and align it to the start
+ * of the next microframe.
+ * If RESUME is complete too late in the microframe, host controller
+ * detects babble on suspended port and resets the port afterwards.
+ * This s/w workaround allows to avoid this problem.
+ * See http://jira.broadcom.com/browse/SWLINUX-1909 for more details
+ */
+static int ehci_brcm_hub_control(
+	struct usb_hcd	*hcd,
+	u16		typeReq,
+	u16		wValue,
+	u16		wIndex,
+	char		*buf,
+	u16		wLength)
+{
+	struct ehci_hcd	*ehci = hcd_to_ehci(hcd);
+	int		ports = HCS_N_PORTS(ehci->hcs_params);
+	u32 __iomem	*status_reg = &ehci->regs->port_status[
+				(wIndex & 0xff) - 1];
+	unsigned long flags;
+	int retval, irq_disabled = 0;
+
+	/* RESUME is cleared when GetPortStatus() is called 20ms after start
+	  of RESUME */
+	if ((typeReq == GetPortStatus) &&
+	    (wIndex && wIndex <= ports) &&
+	    ehci->reset_done[wIndex-1] &&
+	    time_after_eq(jiffies, ehci->reset_done[wIndex-1]) &&
+	    (ehci_readl(ehci, status_reg) & PORT_RESUME)) {
+		/* to make sure we are not interrupted until RESUME bit
+		  is cleared, disable interrupts on current CPU */
+		ehci_dbg(ehci, "SOF alignment workaround\n");
+		irq_disabled = 1;
+		local_irq_save(flags);
+		ehci_brcm_wait_for_sof(ehci, 5);
+	}
+
+	retval = ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
+	if (irq_disabled)
+		local_irq_restore(flags);
+	return retval;
+}
+
+#ifdef CONFIG_PM
+static int ehci_brcm_suspend(struct device *dev)
+{
+	struct usb_hcd		*hcd = dev_get_drvdata(dev);
+	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
+	unsigned long		flags;
+
+	if (time_before(jiffies, ehci->next_statechange))
+		msleep(10);
+
+	/* Root hub was already suspended. Disable irq emission and
+	 * mark HW unaccessible.  The PM and USB cores make sure that
+	 * the root hub is either suspended or stopped.
+	 */
+	ehci_prepare_ports_for_controller_suspend(ehci, device_may_wakeup(dev));
+	spin_lock_irqsave(&ehci->lock, flags);
+	ehci_writel(ehci, 0, &ehci->regs->intr_enable);
+	(void)ehci_readl(ehci, &ehci->regs->intr_enable);
+	brcm_usb_suspend(hcd);
+	spin_unlock_irqrestore(&ehci->lock, flags);
+
+	return 0;
+}
+
+static int ehci_brcm_resume(struct device *dev)
+{
+	struct usb_hcd *hcd = dev_get_drvdata(dev);
+	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+
+	brcm_usb_resume(hcd);
+	if (time_before(jiffies, ehci->next_statechange))
+		msleep(100);
+
+	/* If CF is still set, we maintained PCI Vaux power.
+	 * Just undo the effect of ehci_pci_suspend().
+	 */
+	if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF) {
+		int mask = INTR_MASK;
+
+		ehci_prepare_ports_for_controller_resume(ehci);
+		if (!hcd->self.root_hub->do_remote_wakeup)
+			mask &= ~STS_PCD;
+		ehci_writel(ehci, mask, &ehci->regs->intr_enable);
+		ehci_readl(ehci, &ehci->regs->intr_enable);
+		return 0;
+	}
+
+	dev_info(dev, "lost power, restarting\n");
+	usb_root_hub_lost_power(hcd->self.root_hub);
+
+	/*
+	 * SWLINUX-1705: Avoid OUT packet underflows during high memory
+	 *   bus usage
+	 * port_status[0x0f] = Broadcom-proprietary USB_EHCI_INSNREG00
+	 * @ 0x90
+	 */
+	ehci_writel(ehci, 0x00800040, &ehci->regs->port_status[0x10]);
+	ehci_writel(ehci, 0x00000001, &ehci->regs->port_status[0x12]);
+
+	/* Else reset, to cope with power loss or flush-to-storage
+	 * style "resume" having let BIOS kick in during reboot.
+	 */
+	(void) ehci_halt(ehci);
+	(void) ehci_reset(ehci);
+
+	/* emptying the schedule aborts any urbs */
+	spin_lock_irq(&ehci->lock);
+	if (ehci->reclaim)
+		end_unlink_async(ehci);
+	ehci_work(ehci);
+	spin_unlock_irq(&ehci->lock);
+
+	ehci_writel(ehci, ehci->command, &ehci->regs->command);
+	ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
+	ehci_readl(ehci, &ehci->regs->command);	/* unblock posted writes */
+
+	/* here we "know" root ports should always stay powered */
+	ehci_port_power(ehci, 1);
+
+	ehci->rh_state = EHCI_RH_SUSPENDED;
+	return 0;
+}
+
+static const struct dev_pm_ops brcm_ehci_pmops = {
+	.suspend	= ehci_brcm_suspend,
+	.resume		= ehci_brcm_resume,
+};
+
+#define BRCM_EHCI_PMOPS (&brcm_ehci_pmops)
+
+#else
+#define BRCM_EHCI_PMOPS NULL
+#endif
+
+
+/*-------------------------------------------------------------------------*/
+
+static const struct hc_driver ehci_brcm_hc_driver = {
+	.description =		hcd_name,
+	.product_desc =		"Broadcom STB EHCI",
+	.hcd_priv_size =	sizeof(struct ehci_hcd),
+
+	/*
+	 * generic hardware linkage
+	 */
+	.irq =			ehci_irq,
+	.flags =		HCD_USB2 | HCD_MEMORY,
+
+	/*
+	 * basic lifecycle operations
+	 */
+	.reset =		ehci_brcm_reset,
+	.start =		ehci_run,
+	.stop =			ehci_stop,
+	.shutdown =		ehci_brcm_shutdown,
+
+	/*
+	 * managing i/o requests and associated device resources
+	 */
+	.urb_enqueue =		ehci_urb_enqueue,
+	.urb_dequeue =		ehci_urb_dequeue,
+	.endpoint_disable =	ehci_endpoint_disable,
+	.endpoint_reset =	ehci_endpoint_reset,
+
+	/*
+	 * scheduling support
+	 */
+	.get_frame_number =	ehci_get_frame,
+
+	/*
+	 * root hub support
+	 */
+	.hub_status_data =	ehci_hub_status_data,
+	.hub_control =		ehci_brcm_hub_control,
+#ifdef	CONFIG_PM
+	.bus_suspend =		ehci_bus_suspend,
+	.bus_resume =		ehci_bus_resume,
+#endif
+	.relinquish_port =	ehci_relinquish_port,
+	.port_handed_over =	ehci_port_handed_over,
+	.clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
+};
+
+/*-------------------------------------------------------------------------*/
+
+static int ehci_hcd_brcm_probe(struct platform_device *pdev)
+{
+	static const u64 usb_dmamask = DMA_BIT_MASK(32);
+	pdev->dev.dma_mask = (u64 *)&usb_dmamask;
+	pdev->dev.coherent_dma_mask = usb_dmamask;
+
+	return brcm_usb_probe(pdev, hcd_name, &ehci_brcm_hc_driver);
+}
+
+static int ehci_hcd_brcm_remove(struct platform_device *pdev)
+{
+	return brcm_usb_remove(pdev);
+}
+
+static const struct of_device_id usb_hcd_brcm_match[] = {
+	{ .compatible = "brcm,ehci-brcm" },
+	{},
+};
+
+static struct platform_driver ehci_hcd_brcm_driver = {
+	.probe = ehci_hcd_brcm_probe,
+	.remove = ehci_hcd_brcm_remove,
+	.shutdown = usb_hcd_platform_shutdown,
+	.driver = {
+		.name = "ehci-brcm",
+		.bus = &platform_bus_type,
+		.of_match_table = of_match_ptr(usb_hcd_brcm_match),
+		.pm = BRCM_EHCI_PMOPS,
+	}
+};
+
+MODULE_ALIAS("ehci-brcm");
diff --git a/drivers/usb/host/ohci-brcm.c b/drivers/usb/host/ohci-brcm.c
new file mode 100644
index 0000000..43d0fe7
--- /dev/null
+++ b/drivers/usb/host/ohci-brcm.c
@@ -0,0 +1,190 @@
+/*
+ * Copyright (C) 2009 - 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include "usb-brcm.h"
+
+static struct platform_driver	ohci_hcd_brcm_driver;
+#define PLATFORM_DRIVER		ohci_hcd_brcm_driver
+
+#include "ohci-hcd.c"
+
+/* catch unwanted redefinitions */
+#define CONFIG_PCI		0
+
+/* for global USB settings, see arch/mips/brcmstb/bchip.c */
+
+static int ohci_brcm_reset(struct usb_hcd *hcd)
+{
+	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
+
+	ohci->flags |= OHCI_QUIRK_BE_MMIO;
+	distrust_firmware = 0;
+	ohci_hcd_init(ohci);
+	return ohci_init(ohci);
+}
+
+static int ohci_brcm_start(struct usb_hcd *hcd)
+{
+	struct ohci_hcd	*ohci = hcd_to_ohci(hcd);
+	struct ohci_regs __iomem *regs;
+
+	regs = hcd->regs;
+
+	ohci_writel(ohci, 1, &regs->cmdstatus);
+	ohci_readl(ohci, &regs->cmdstatus);
+	mdelay(10);
+
+	ohci_hcd_init(ohci);
+	ohci_init(ohci);
+	ohci_run(ohci);
+	hcd->state = HC_STATE_RUNNING;
+	return 0;
+}
+
+static void ohci_brcm_shutdown(struct usb_hcd *hcd)
+{
+	if (test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags))
+		ohci_shutdown(hcd);
+}
+
+#ifdef CONFIG_PM
+static int ohci_brcm_suspend(struct device *dev)
+{
+	struct usb_hcd *hcd = dev_get_drvdata(dev);
+	struct ohci_hcd	*ohci = hcd_to_ohci(hcd);
+	unsigned long	flags;
+	int		rc = 0;
+
+	/* Root hub was already suspended. Disable irq emission and
+	 * mark HW unaccessible, bail out if RH has been resumed. Use
+	 * the spinlock to properly synchronize with possible pending
+	 * RH suspend or resume activity.
+	 */
+	spin_lock_irqsave(&ohci->lock, flags);
+	if (ohci->rh_state != OHCI_RH_SUSPENDED) {
+		rc = -EINVAL;
+		goto bail;
+	}
+	ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
+	(void)ohci_readl(ohci, &ohci->regs->intrdisable);
+
+	brcm_usb_suspend(hcd);
+ bail:
+	spin_unlock_irqrestore(&ohci->lock, flags);
+
+	return rc;
+}
+
+static int ohci_brcm_resume(struct device *dev)
+{
+	struct usb_hcd *hcd = dev_get_drvdata(dev);
+
+	brcm_usb_resume(hcd);
+	ohci_usb_reset(hcd_to_ohci(hcd));
+	ohci_finish_controller_resume(hcd);
+	return 0;
+}
+
+static const struct dev_pm_ops brcm_ohci_pmops = {
+	.suspend	= ohci_brcm_suspend,
+	.resume		= ohci_brcm_resume,
+};
+
+#define BRCM_OHCI_PMOPS (&brcm_ohci_pmops)
+
+#else
+#define BRCM_OHCI_PMOPS NULL
+#endif
+
+static const struct hc_driver ohci_brcm_hc_driver = {
+	.description =		hcd_name,
+	.product_desc =		"Broadcom STB OHCI",
+	.hcd_priv_size =	sizeof(struct ohci_hcd),
+
+	/*
+	 * generic hardware linkage
+	 */
+	.irq =			ohci_irq,
+	.flags =		HCD_USB11 | HCD_MEMORY,
+
+	/*
+	 * basic lifecycle operations
+	 */
+	.reset =		ohci_brcm_reset,
+	.start =		ohci_brcm_start,
+	.stop =			ohci_stop,
+	.shutdown =		ohci_brcm_shutdown,
+
+	/*
+	 * managing i/o requests and associated device resources
+	 */
+	.urb_enqueue =		ohci_urb_enqueue,
+	.urb_dequeue =		ohci_urb_dequeue,
+	.endpoint_disable =	ohci_endpoint_disable,
+
+	/*
+	 * scheduling support
+	 */
+	.get_frame_number =	ohci_get_frame,
+
+	/*
+	 * root hub support
+	 */
+	.hub_status_data =	ohci_hub_status_data,
+	.hub_control =		ohci_hub_control,
+#ifdef	CONFIG_PM
+	.bus_suspend =		ohci_bus_suspend,
+	.bus_resume =		ohci_bus_resume,
+#endif
+	.start_port_reset =	ohci_start_port_reset,
+};
+
+/*-------------------------------------------------------------------------*/
+
+static int ohci_hcd_brcm_probe(struct platform_device *pdev)
+{
+	static const u64 usb_dmamask = DMA_BIT_MASK(32);
+	pdev->dev.dma_mask = (u64 *)&usb_dmamask;
+	pdev->dev.coherent_dma_mask = usb_dmamask;
+
+	return brcm_usb_probe(pdev, hcd_name, &ohci_brcm_hc_driver);
+}
+
+static int ohci_hcd_brcm_remove(struct platform_device *pdev)
+{
+	return brcm_usb_remove(pdev);
+}
+
+static const struct of_device_id usb_hcd_brcm_match[] = {
+	{ .compatible = "brcm,ohci-brcm" },
+	{},
+};
+
+static struct platform_driver ohci_hcd_brcm_driver = {
+	.probe		= ohci_hcd_brcm_probe,
+	.remove		= ohci_hcd_brcm_remove,
+	.shutdown	= usb_hcd_platform_shutdown,
+	.driver		= {
+		.name	= "ohci-brcm",
+		.owner	= THIS_MODULE,
+		.pm = BRCM_OHCI_PMOPS,
+		.bus = &platform_bus_type,
+		.of_match_table = of_match_ptr(usb_hcd_brcm_match),
+	},
+};
+
+MODULE_ALIAS("ohci-brcm");
diff --git a/drivers/usb/host/usb-brcm.c b/drivers/usb/host/usb-brcm.c
new file mode 100644
index 0000000..945c109
--- /dev/null
+++ b/drivers/usb/host/usb-brcm.c
@@ -0,0 +1,262 @@
+/*
+ * Copyright (C) 2010 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/usb.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <linux/pm.h>
+#include <linux/clk.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/bitops.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)
+#include <linux/usb/hcd.h>
+#else
+#include "../core/hcd.h"
+#endif
+
+#define MAX_HCD			8
+
+static struct clk *usb_clk;
+
+/***********************************************************************
+ * Library functions
+ ***********************************************************************/
+
+int brcm_usb_probe(struct platform_device *pdev, char *hcd_name,
+	const struct hc_driver *hc_driver)
+{
+	struct resource *res = NULL;
+	struct usb_hcd *hcd = NULL;
+	int irq, ret, len;
+
+	if (usb_disabled())
+		return -ENODEV;
+
+	if (!usb_clk)
+		usb_clk = clk_get(NULL, "usb");
+	clk_enable(usb_clk);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		err("platform_get_resource error.");
+		return -ENODEV;
+	}
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		err("platform_get_irq error.");
+		return -ENODEV;
+	}
+
+	/* initialize hcd */
+	hcd = usb_create_hcd(hc_driver, &pdev->dev, (char *)hcd_name);
+	if (!hcd) {
+		err("Failed to create hcd");
+		return -ENOMEM;
+	}
+
+	len = res->end - res->start + 1;
+	hcd->regs = ioremap(res->start, len);
+	hcd->rsrc_start = res->start;
+	hcd->rsrc_len = len;
+	ret = usb_add_hcd(hcd, irq, IRQF_DISABLED);
+	if (ret != 0) {
+		err("Failed to add hcd");
+		iounmap(hcd->regs);
+		usb_put_hcd(hcd);
+		clk_disable(usb_clk);
+		return ret;
+	}
+
+#ifdef CONFIG_PM
+	/* disable autosuspend by default to preserve
+	 * original behavior
+	 */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32)
+	usb_disable_autosuspend(hcd->self.root_hub);
+#else
+	hcd->self.root_hub->autosuspend_disabled = 1;
+#endif
+#endif
+
+	return ret;
+}
+EXPORT_SYMBOL(brcm_usb_probe);
+
+int brcm_usb_remove(struct platform_device *pdev)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(pdev);
+	clk_disable(usb_clk);
+	usb_remove_hcd(hcd);
+	iounmap(hcd->regs);
+	usb_put_hcd(hcd);
+
+	return 0;
+}
+EXPORT_SYMBOL(brcm_usb_remove);
+
+void brcm_usb_suspend(struct usb_hcd *hcd)
+{
+	/* Since all HCs share clock source, once we enable USB clock, all
+	   controllers are capable to generate interrupts if enabled. Since some
+	   controllers at this time are still marked as non-accessible, this
+	   leads to spurious interrupts.
+	   To avoid this, disable controller interrupts.
+	*/
+	disable_irq(hcd->irq);
+	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+	clk_disable(usb_clk);
+}
+EXPORT_SYMBOL(brcm_usb_suspend);
+
+void brcm_usb_resume(struct usb_hcd *hcd)
+{
+	clk_enable(usb_clk);
+	set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+	enable_irq(hcd->irq);
+}
+EXPORT_SYMBOL(brcm_usb_resume);
+
+#ifdef CONFIG_OF
+
+/***********************************************************************
+ * DT support for USB instances
+ ***********************************************************************/
+
+struct brcm_usb_instance {
+	void __iomem		*ctrl_regs;
+	int			ioc;
+	int			ipp;
+};
+
+#ifdef __LITTLE_ENDIAN
+#define ENDIAN_SETTING		0x03 /* !WABO !FNBO FNHW BABO */
+#else
+#define ENDIAN_SETTING		0x0e /* WABO FNBO FNHW !BABO */
+#endif
+
+#define ENDIAN_m		0x0f
+#define IOC_m			BIT(4)
+#define IPP_m			BIT(5)
+
+#define SEQ_EN_m		BIT(0)
+#define SCB_SIZE_s		7
+#define SCB_SIZE_m		(0x1f << SCB_SIZE_s)
+
+#define SETUP_REG		0x00
+#define EBRIDGE_REG		0x0c
+#define OBRIDGE_REG		0x10
+
+static void brcm_usb_instance_hw_init(struct brcm_usb_instance *priv)
+{
+	u32 reg;
+
+	/* set up byte order for DRAM accesses */
+	reg = (readl(priv->ctrl_regs + SETUP_REG) & ~ENDIAN_m) |
+	      ENDIAN_SETTING;
+
+	/* set overcurrent and power polarity based on DT properties */
+	reg &= ~(IOC_m | IPP_m);
+	if (priv->ioc)
+		reg |= IOC_m;
+	if (priv->ipp)
+		reg |= IPP_m;
+	writel(reg, priv->ctrl_regs + SETUP_REG);
+
+	/* override lame bridge defaults */
+	reg = readl(priv->ctrl_regs + OBRIDGE_REG);
+	reg &= ~SEQ_EN_m;
+	writel(reg, priv->ctrl_regs + OBRIDGE_REG);
+
+	reg = readl(priv->ctrl_regs + EBRIDGE_REG);
+	reg &= ~SEQ_EN_m;
+	reg &= ~SCB_SIZE_m;
+	reg |= 0x08 << SCB_SIZE_s;
+	writel(reg, priv->ctrl_regs + EBRIDGE_REG);
+}
+
+static int __devinit brcm_usb_instance_probe(struct platform_device *pdev)
+{
+	struct device_node *dn = pdev->dev.of_node;
+	struct resource ctrl_res;
+	const u32 *prop;
+	struct brcm_usb_instance *priv;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+	dev_set_drvdata(&pdev->dev, priv);
+
+	if (of_address_to_resource(dn, 0, &ctrl_res)) {
+		dev_err(&pdev->dev, "can't get USB_CTRL base address\n");
+		return -EINVAL;
+	}
+
+	priv->ctrl_regs = devm_request_and_ioremap(&pdev->dev, &ctrl_res);
+	if (!priv->ctrl_regs) {
+		dev_err(&pdev->dev, "can't map register space\n");
+		return -EINVAL;
+	}
+
+	prop = of_get_property(dn, "ipp", NULL);
+	if (prop)
+		priv->ipp = be32_to_cpup(prop);
+
+	prop = of_get_property(dn, "ioc", NULL);
+	if (prop)
+		priv->ioc = be32_to_cpup(prop);
+
+	brcm_usb_instance_hw_init(priv);
+
+	return of_platform_populate(dn, NULL, NULL, NULL);
+}
+
+static const struct of_device_id brcm_usb_instance_match[] = {
+	{ .compatible = "brcm,usb-instance" },
+	{},
+};
+
+static struct platform_driver brcm_usb_instance_driver = {
+	.driver = {
+		.name = "usb-brcm",
+		.bus = &platform_bus_type,
+		.of_match_table = of_match_ptr(brcm_usb_instance_match),
+	}
+};
+
+/*
+ * We really don't want to try to undo of_platform_populate(), so it
+ * is not possible to unbind/deregister this driver.
+ */
+static int __init brcm_usb_instance_init(void)
+{
+	return platform_driver_probe(&brcm_usb_instance_driver,
+				     brcm_usb_instance_probe);
+}
+module_init(brcm_usb_instance_init);
+
+#endif
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("Broadcom USB common functions");
diff --git a/drivers/usb/host/usb-brcm.h b/drivers/usb/host/usb-brcm.h
new file mode 100644
index 0000000..3650d15
--- /dev/null
+++ b/drivers/usb/host/usb-brcm.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2010 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _USB_BRCM_H
+#define _USB_BRCM_H
+
+#include <linux/usb.h>
+#include <linux/platform_device.h>
+#include <linux/mmdebug.h>
+#include <linux/io.h>
+#include <linux/version.h>
+#include <linux/irq.h>
+#include <linux/dma-mapping.h>
+#include <linux/of.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)
+#include <linux/usb/hcd.h>
+#else
+#include "../core/hcd.h"
+#endif
+
+/* force non-byteswapping reads/writes on LE and BE alike */
+#define CONFIG_USB_EHCI_BIG_ENDIAN_MMIO		1
+#define CONFIG_USB_OHCI_BIG_ENDIAN_MMIO		1
+#undef readl_be
+#undef writel_be
+#define readl_be(x)				__raw_readl(x)
+#define writel_be(x, y)				__raw_writel(x, y)
+
+/* stock Linux drivers assume USB is always PCI-based on platforms with PCI */
+#undef CONFIG_PCI
+
+extern int brcm_usb_probe(struct platform_device *, const char *,
+	const struct hc_driver *);
+extern int brcm_usb_remove(struct platform_device *pdev);
+extern void brcm_usb_suspend(struct usb_hcd *hcd);
+extern void brcm_usb_resume(struct usb_hcd *hcd);
+extern int brcm_usb_is_inactive(void);
+
+#endif /* _USB_BRCM_H */
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index 3053933..93ada51 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -175,6 +175,14 @@ static int xhci_pci_setup(struct usb_hcd *hcd)
 	pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 
+	{
+		unsigned char c;
+		printk("xhci switched power on polarity\n");
+		pci_read_config_byte(pdev, 0xE2, &c);
+		c |= 0x40;
+		pci_write_config_byte(pdev, 0xE2, c);
+	}
+
 	/* Find any debug ports */
 	retval = xhci_pci_reinit(xhci, pdev);
 	if (!retval)
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index f389328..09b8270 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -2049,7 +2049,7 @@ static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
 			td->urb->actual_length =
 				td->urb->transfer_buffer_length -
 				EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
-		else
+		else if (!td->urb_length_set)
 			td->urb->actual_length = 0;
 
 		return finish_td(xhci, td, event_trb, event, ep, status, false);
diff --git a/drivers/usb/serial/ftdi_sio.c b/drivers/usb/serial/ftdi_sio.c
index 4038789..0835b4f 100644
--- a/drivers/usb/serial/ftdi_sio.c
+++ b/drivers/usb/serial/ftdi_sio.c
@@ -2314,10 +2314,20 @@ static void ftdi_set_termios(struct tty_struct *tty,
 	}
 
 	/*
-	 * All FTDI UART chips are limited to CS7/8. We won't pretend to
+	 * All FTDI UART chips are limited to CS7/8. We shouldn't pretend to
 	 * support CS5/6 and revert the CSIZE setting instead.
+	 *
+	 * CS5 however is used to control some smartcard readers which abuse
+	 * this limitation to switch modes. Original FTDI chips fall back to
+	 * eight data bits.
+	 *
+	 * TODO: Implement a quirk to only allow this with mentioned
+	 *       readers. One I know of (Argolis Smartreader V1)
+	 *       returns "USB smartcard server" as iInterface string.
+	 *       The vendor didn't bother with a custom VID/PID of
+	 *       course.
 	 */
-	if ((C_CSIZE(tty) != CS8) && (C_CSIZE(tty) != CS7)) {
+	if (C_CSIZE(tty) == CS6) {
 		dev_warn(&port->dev, "requested CSIZE setting not supported\n");
 
 		termios->c_cflag &= ~CSIZE;
@@ -2364,6 +2374,9 @@ no_skip:
 		urb_value |= FTDI_SIO_SET_DATA_PARITY_NONE;
 	}
 	switch (cflag & CSIZE) {
+	case CS5:
+		dev_dbg(&port->dev, "Setting CS5 quirk\n");
+		break;
 	case CS7:
 		urb_value |= 7;
 		dev_dbg(&port->dev, "Setting CS7\n");
diff --git a/drivers/video/console/newport_con.c b/drivers/video/console/newport_con.c
index 6d15966..b05afd0 100644
--- a/drivers/video/console/newport_con.c
+++ b/drivers/video/console/newport_con.c
@@ -327,9 +327,16 @@ out_unmap:
 
 static void newport_init(struct vc_data *vc, int init)
 {
-	vc->vc_cols = newport_xsize / 8;
-	vc->vc_rows = newport_ysize / 16;
+	int cols, rows;
+
+	cols = newport_xsize / 8;
+	rows = newport_ysize / 16;
 	vc->vc_can_do_color = 1;
+	if (init) {
+		vc->vc_cols = cols;
+		vc->vc_rows = rows;
+	} else
+		vc_resize(vc, cols, rows);
 }
 
 static void newport_deinit(struct vc_data *c)
diff --git a/fs/nfs/super.c b/fs/nfs/super.c
index c252161..56fad25 100644
--- a/fs/nfs/super.c
+++ b/fs/nfs/super.c
@@ -1124,10 +1124,12 @@ static int nfs_parse_version_string(char *string,
 		mnt->version = 4;
 		mnt->minorversion = 0;
 		break;
+#ifdef CONFIG_NFS_V4_1
 	case Opt_vers_4_1:
 		mnt->version = 4;
 		mnt->minorversion = 1;
 		break;
+#endif
 	default:
 		return 0;
 	}
diff --git a/fs/ramfs/inode.c b/fs/ramfs/inode.c
index a1fdabe..92e658f 100644
--- a/fs/ramfs/inode.c
+++ b/fs/ramfs/inode.c
@@ -247,7 +247,12 @@ struct dentry *ramfs_mount(struct file_system_type *fs_type,
 static struct dentry *rootfs_mount(struct file_system_type *fs_type,
 	int flags, const char *dev_name, void *data)
 {
-	return mount_nodev(fs_type, flags|MS_NOUSER, data, ramfs_fill_super);
+	static unsigned long once;
+
+	if (test_and_set_bit(1, &once))
+		return ERR_PTR(-ENODEV);
+
+	return mount_nodev(fs_type, flags, data, ramfs_fill_super);
 }
 
 static void ramfs_kill_sb(struct super_block *sb)
diff --git a/fs/ubifs/lpt.c b/fs/ubifs/lpt.c
index 66d59d0..d7b3709 100644
--- a/fs/ubifs/lpt.c
+++ b/fs/ubifs/lpt.c
@@ -1740,16 +1740,23 @@ int ubifs_lpt_init(struct ubifs_info *c, int rd, int wr)
 	if (rd) {
 		err = lpt_init_rd(c);
 		if (err)
-			return err;
+			goto out_err;
 	}
 
 	if (wr) {
 		err = lpt_init_wr(c);
 		if (err)
-			return err;
+			goto out_err;
 	}
 
 	return 0;
+
+out_err:
+	if (wr)
+		ubifs_lpt_free(c, 1);
+	if (rd)
+		ubifs_lpt_free(c, 0);
+	return err;
 }
 
 /**
diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c
index 129bb48..924153a 100644
--- a/fs/ubifs/super.c
+++ b/fs/ubifs/super.c
@@ -1301,7 +1301,7 @@ static int mount_ubifs(struct ubifs_info *c)
 	if (!c->ro_mount && c->space_fixup) {
 		err = ubifs_fixup_free_space(c);
 		if (err)
-			goto out_master;
+			goto out_lpt;
 	}
 
 	if (!c->ro_mount) {
@@ -1585,7 +1585,7 @@ static int ubifs_remount_rw(struct ubifs_info *c)
 	if (c->space_fixup) {
 		err = ubifs_fixup_free_space(c);
 		if (err)
-			return err;
+			goto out;
 	}
 
 	err = check_free_space(c);
diff --git a/fs/xfs/xfs_aops.c b/fs/xfs/xfs_aops.c
index 7a978c7..8233ebe 100644
--- a/fs/xfs/xfs_aops.c
+++ b/fs/xfs/xfs_aops.c
@@ -469,11 +469,17 @@ static inline int bio_add_buffer(struct bio *bio, struct buffer_head *bh)
  *
  * The fix is two passes across the ioend list - one to start writeback on the
  * buffer_heads, and then submit them for I/O on the second pass.
+ *
+ * If @fail is non-zero, it means that we have a situation where some part of
+ * the submission process has failed after we have marked paged for writeback
+ * and unlocked them. In this situation, we need to fail the ioend chain rather
+ * than submit it to IO. This typically only happens on a filesystem shutdown.
  */
 STATIC void
 xfs_submit_ioend(
 	struct writeback_control *wbc,
-	xfs_ioend_t		*ioend)
+	xfs_ioend_t		*ioend,
+	int			fail)
 {
 	xfs_ioend_t		*head = ioend;
 	xfs_ioend_t		*next;
@@ -494,6 +500,18 @@ xfs_submit_ioend(
 		next = ioend->io_list;
 		bio = NULL;
 
+		/*
+		 * If we are failing the IO now, just mark the ioend with an
+		 * error and finish it. This will run IO completion immediately
+		 * as there is only one reference to the ioend at this point in
+		 * time.
+		 */
+		if (fail) {
+			ioend->io_error = -fail;
+			xfs_finish_ioend(ioend);
+			continue;
+		}
+
 		for (bh = ioend->io_buffer_head; bh; bh = bh->b_private) {
 
 			if (!bio) {
@@ -623,7 +641,7 @@ xfs_map_at_offset(
  * or delayed allocate extent.
  */
 STATIC int
-xfs_is_delayed_page(
+xfs_check_page_type(
 	struct page		*page,
 	unsigned int		type)
 {
@@ -637,11 +655,11 @@ xfs_is_delayed_page(
 		bh = head = page_buffers(page);
 		do {
 			if (buffer_unwritten(bh))
-				acceptable = (type == IO_UNWRITTEN);
+				acceptable += (type == IO_UNWRITTEN);
 			else if (buffer_delay(bh))
-				acceptable = (type == IO_DELALLOC);
+				acceptable += (type == IO_DELALLOC);
 			else if (buffer_dirty(bh) && buffer_mapped(bh))
-				acceptable = (type == IO_OVERWRITE);
+				acceptable += (type == IO_OVERWRITE);
 			else
 				break;
 		} while ((bh = bh->b_this_page) != head);
@@ -684,7 +702,7 @@ xfs_convert_page(
 		goto fail_unlock_page;
 	if (page->mapping != inode->i_mapping)
 		goto fail_unlock_page;
-	if (!xfs_is_delayed_page(page, (*ioendp)->io_type))
+	if (!xfs_check_page_type(page, (*ioendp)->io_type))
 		goto fail_unlock_page;
 
 	/*
@@ -834,7 +852,7 @@ xfs_aops_discard_page(
 	struct buffer_head	*bh, *head;
 	loff_t			offset = page_offset(page);
 
-	if (!xfs_is_delayed_page(page, IO_DELALLOC))
+	if (!xfs_check_page_type(page, IO_DELALLOC))
 		goto out_invalidate;
 
 	if (XFS_FORCED_SHUTDOWN(ip->i_mount))
@@ -925,16 +943,20 @@ xfs_vm_writepage(
 	if (WARN_ON(current->flags & PF_FSTRANS))
 		goto redirty;
 
-	/* Is this page beyond the end of the file? */
+	/*
+	 * Is this page beyond the end of the file? Skip the page if it is
+	 * fully outside i_size, e.g. due to a truncate operation that is in
+	 * progress. We must redirty the page so that reclaim stops reclaiming
+	 * it. Otherwise xfs_vm_releasepage() is called on it and gets
+	 * confused.
+	 */
 	offset = i_size_read(inode);
 	end_index = offset >> PAGE_CACHE_SHIFT;
 	last_index = (offset - 1) >> PAGE_CACHE_SHIFT;
 	if (page->index >= end_index) {
 		if ((page->index >= end_index + 1) ||
-		    !(i_size_read(inode) & (PAGE_CACHE_SIZE - 1))) {
-			unlock_page(page);
-			return 0;
-		}
+		    !(i_size_read(inode) & (PAGE_CACHE_SIZE - 1)))
+			goto redirty;
 	}
 
 	end_offset = min_t(unsigned long long,
@@ -1028,7 +1050,18 @@ xfs_vm_writepage(
 
 	xfs_start_page_writeback(page, 1, count);
 
-	if (ioend && imap_valid) {
+	/* if there is no IO to be submitted for this page, we are done */
+	if (!ioend)
+		return 0;
+
+	ASSERT(iohead);
+
+	/*
+	 * Any errors from this point onwards need tobe reported through the IO
+	 * completion path as we have marked the initial page as under writeback
+	 * and unlocked it.
+	 */
+	if (imap_valid) {
 		xfs_off_t		end_index;
 
 		end_index = imap.br_startoff + imap.br_blockcount;
@@ -1047,21 +1080,14 @@ xfs_vm_writepage(
 				  wbc, end_index);
 	}
 
-	if (iohead) {
-		/*
-		 * Reserve log space if we might write beyond the on-disk
-		 * inode size.
-		 */
-		if (ioend->io_type != IO_UNWRITTEN &&
-		    xfs_ioend_is_append(ioend)) {
-			err = xfs_setfilesize_trans_alloc(ioend);
-			if (err)
-				goto error;
-		}
-
-		xfs_submit_ioend(wbc, iohead);
-	}
+	/*
+	 * Reserve log space if we might write beyond the on-disk inode size.
+	 */
+	err = 0;
+	if (ioend->io_type != IO_UNWRITTEN && xfs_ioend_is_append(ioend))
+		err = xfs_setfilesize_trans_alloc(ioend);
 
+	xfs_submit_ioend(wbc, iohead, err);
 	return 0;
 
 error:
@@ -1146,7 +1172,14 @@ __xfs_get_blocks(
 	if (!create && direct && offset >= i_size_read(inode))
 		return 0;
 
-	if (create) {
+	/*
+	 * Direct I/O is usually done on preallocated files, so try getting
+	 * a block mapping without an exclusive lock first.  For buffered
+	 * writes we already have the exclusive iolock anyway, so avoiding
+	 * a lock roundtrip here by taking the ilock exclusive from the
+	 * beginning is a useful micro optimization.
+	 */
+	if (create && !direct) {
 		lockmode = XFS_ILOCK_EXCL;
 		xfs_ilock(ip, lockmode);
 	} else {
@@ -1168,23 +1201,45 @@ __xfs_get_blocks(
 	    (!nimaps ||
 	     (imap.br_startblock == HOLESTARTBLOCK ||
 	      imap.br_startblock == DELAYSTARTBLOCK))) {
-		if (direct) {
+		if (direct || xfs_get_extsz_hint(ip)) {
+			/*
+			 * Drop the ilock in preparation for starting the block
+			 * allocation transaction.  It will be retaken
+			 * exclusively inside xfs_iomap_write_direct for the
+			 * actual allocation.
+			 */
+			xfs_iunlock(ip, lockmode);
 			error = xfs_iomap_write_direct(ip, offset, size,
 						       &imap, nimaps);
+			if (error)
+				return -error;
+			new = 1;
 		} else {
+			/*
+			 * Delalloc reservations do not require a transaction,
+			 * we can go on without dropping the lock here. If we
+			 * are allocating a new delalloc block, make sure that
+			 * we set the new flag so that we mark the buffer new so
+			 * that we know that it is newly allocated if the write
+			 * fails.
+			 */
+			if (nimaps && imap.br_startblock == HOLESTARTBLOCK)
+				new = 1;
 			error = xfs_iomap_write_delay(ip, offset, size, &imap);
+			if (error)
+				goto out_unlock;
+
+			xfs_iunlock(ip, lockmode);
 		}
-		if (error)
-			goto out_unlock;
 
 		trace_xfs_get_blocks_alloc(ip, offset, size, 0, &imap);
 	} else if (nimaps) {
 		trace_xfs_get_blocks_found(ip, offset, size, 0, &imap);
+		xfs_iunlock(ip, lockmode);
 	} else {
 		trace_xfs_get_blocks_notfound(ip, offset, size);
 		goto out_unlock;
 	}
-	xfs_iunlock(ip, lockmode);
 
 	if (imap.br_startblock != HOLESTARTBLOCK &&
 	    imap.br_startblock != DELAYSTARTBLOCK) {
@@ -1386,52 +1441,91 @@ out_destroy_ioend:
 	return ret;
 }
 
+/*
+ * Punch out the delalloc blocks we have already allocated.
+ *
+ * Don't bother with xfs_setattr given that nothing can have made it to disk yet
+ * as the page is still locked at this point.
+ */
+STATIC void
+xfs_vm_kill_delalloc_range(
+	struct inode		*inode,
+	loff_t			start,
+	loff_t			end)
+{
+	struct xfs_inode	*ip = XFS_I(inode);
+	xfs_fileoff_t		start_fsb;
+	xfs_fileoff_t		end_fsb;
+	int			error;
+
+	start_fsb = XFS_B_TO_FSB(ip->i_mount, start);
+	end_fsb = XFS_B_TO_FSB(ip->i_mount, end);
+	if (end_fsb <= start_fsb)
+		return;
+
+	xfs_ilock(ip, XFS_ILOCK_EXCL);
+	error = xfs_bmap_punch_delalloc_range(ip, start_fsb,
+						end_fsb - start_fsb);
+	if (error) {
+		/* something screwed, just bail */
+		if (!XFS_FORCED_SHUTDOWN(ip->i_mount)) {
+			xfs_alert(ip->i_mount,
+		"xfs_vm_write_failed: unable to clean up ino %lld",
+					ip->i_ino);
+		}
+	}
+	xfs_iunlock(ip, XFS_ILOCK_EXCL);
+}
+
 STATIC void
 xfs_vm_write_failed(
-	struct address_space	*mapping,
-	loff_t			to)
+	struct inode		*inode,
+	struct page		*page,
+	loff_t			pos,
+	unsigned		len)
 {
-	struct inode		*inode = mapping->host;
+	loff_t			block_offset = pos & PAGE_MASK;
+	loff_t			block_start;
+	loff_t			block_end;
+	loff_t			from = pos & (PAGE_CACHE_SIZE - 1);
+	loff_t			to = from + len;
+	struct buffer_head	*bh, *head;
 
-	if (to > inode->i_size) {
-		/*
-		 * Punch out the delalloc blocks we have already allocated.
-		 *
-		 * Don't bother with xfs_setattr given that nothing can have
-		 * made it to disk yet as the page is still locked at this
-		 * point.
-		 */
-		struct xfs_inode	*ip = XFS_I(inode);
-		xfs_fileoff_t		start_fsb;
-		xfs_fileoff_t		end_fsb;
-		int			error;
+	ASSERT(block_offset + from == pos);
 
-		truncate_pagecache(inode, to, inode->i_size);
+	head = page_buffers(page);
+	block_start = 0;
+	for (bh = head; bh != head || !block_start;
+	     bh = bh->b_this_page, block_start = block_end,
+				   block_offset += bh->b_size) {
+		block_end = block_start + bh->b_size;
 
-		/*
-		 * Check if there are any blocks that are outside of i_size
-		 * that need to be trimmed back.
-		 */
-		start_fsb = XFS_B_TO_FSB(ip->i_mount, inode->i_size) + 1;
-		end_fsb = XFS_B_TO_FSB(ip->i_mount, to);
-		if (end_fsb <= start_fsb)
-			return;
-
-		xfs_ilock(ip, XFS_ILOCK_EXCL);
-		error = xfs_bmap_punch_delalloc_range(ip, start_fsb,
-							end_fsb - start_fsb);
-		if (error) {
-			/* something screwed, just bail */
-			if (!XFS_FORCED_SHUTDOWN(ip->i_mount)) {
-				xfs_alert(ip->i_mount,
-			"xfs_vm_write_failed: unable to clean up ino %lld",
-						ip->i_ino);
-			}
-		}
-		xfs_iunlock(ip, XFS_ILOCK_EXCL);
+		/* skip buffers before the write */
+		if (block_end <= from)
+			continue;
+
+		/* if the buffer is after the write, we're done */
+		if (block_start >= to)
+			break;
+
+		if (!buffer_delay(bh))
+			continue;
+
+		if (!buffer_new(bh) && block_offset < i_size_read(inode))
+			continue;
+
+		xfs_vm_kill_delalloc_range(inode, block_offset,
+					   block_offset + bh->b_size);
 	}
+
 }
 
+/*
+ * This used to call block_write_begin(), but it unlocks and releases the page
+ * on error, and we need that page to be able to punch stale delalloc blocks out
+ * on failure. hence we copy-n-waste it here and call xfs_vm_write_failed() at
+ * the appropriate point.
+ */
 STATIC int
 xfs_vm_write_begin(
 	struct file		*file,
@@ -1442,15 +1536,40 @@ xfs_vm_write_begin(
 	struct page		**pagep,
 	void			**fsdata)
 {
-	int			ret;
+	pgoff_t			index = pos >> PAGE_CACHE_SHIFT;
+	struct page		*page;
+	int			status;
 
-	ret = block_write_begin(mapping, pos, len, flags | AOP_FLAG_NOFS,
-				pagep, xfs_get_blocks);
-	if (unlikely(ret))
-		xfs_vm_write_failed(mapping, pos + len);
-	return ret;
+	ASSERT(len <= PAGE_CACHE_SIZE);
+
+	page = grab_cache_page_write_begin(mapping, index,
+					   flags | AOP_FLAG_NOFS);
+	if (!page)
+		return -ENOMEM;
+
+	status = __block_write_begin(page, pos, len, xfs_get_blocks);
+	if (unlikely(status)) {
+		struct inode	*inode = mapping->host;
+
+		xfs_vm_write_failed(inode, page, pos, len);
+		unlock_page(page);
+
+		if (pos + len > i_size_read(inode))
+			truncate_pagecache(inode, pos + len, i_size_read(inode));
+
+		page_cache_release(page);
+		page = NULL;
+	}
+
+	*pagep = page;
+	return status;
 }
 
+/*
+ * On failure, we only need to kill delalloc blocks beyond EOF because they
+ * will never be written. For blocks within EOF, generic_write_end() zeros them
+ * so they are safe to leave alone and be written with all the other valid data.
+ */
 STATIC int
 xfs_vm_write_end(
 	struct file		*file,
@@ -1463,9 +1582,19 @@ xfs_vm_write_end(
 {
 	int			ret;
 
+	ASSERT(len <= PAGE_CACHE_SIZE);
+
 	ret = generic_write_end(file, mapping, pos, len, copied, page, fsdata);
-	if (unlikely(ret < len))
-		xfs_vm_write_failed(mapping, pos + len);
+	if (unlikely(ret < len)) {
+		struct inode	*inode = mapping->host;
+		size_t		isize = i_size_read(inode);
+		loff_t		to = pos + len;
+
+		if (to > isize) {
+			truncate_pagecache(inode, to, isize);
+			xfs_vm_kill_delalloc_range(inode, isize, to);
+		}
+	}
 	return ret;
 }
 
diff --git a/fs/xfs/xfs_iomap.c b/fs/xfs/xfs_iomap.c
index 71a4645..47e714a 100644
--- a/fs/xfs/xfs_iomap.c
+++ b/fs/xfs/xfs_iomap.c
@@ -142,11 +142,7 @@ xfs_iomap_write_direct(
 	int		committed;
 	int		error;
 
-	/*
-	 * Make sure that the dquots are there. This doesn't hold
-	 * the ilock across a disk read.
-	 */
-	error = xfs_qm_dqattach_locked(ip, 0);
+	error = xfs_qm_dqattach(ip, 0);
 	if (error)
 		return XFS_ERROR(error);
 
@@ -158,7 +154,7 @@ xfs_iomap_write_direct(
 	if ((offset + count) > XFS_ISIZE(ip)) {
 		error = xfs_iomap_eof_align_last_fsb(mp, ip, extsz, &last_fsb);
 		if (error)
-			goto error_out;
+			return XFS_ERROR(error);
 	} else {
 		if (nmaps && (imap->br_startblock == HOLESTARTBLOCK))
 			last_fsb = MIN(last_fsb, (xfs_fileoff_t)
@@ -190,7 +186,6 @@ xfs_iomap_write_direct(
 	/*
 	 * Allocate and setup the transaction
 	 */
-	xfs_iunlock(ip, XFS_ILOCK_EXCL);
 	tp = xfs_trans_alloc(mp, XFS_TRANS_DIOSTRAT);
 	error = xfs_trans_reserve(tp, resblks,
 			XFS_WRITE_LOG_RES(mp), resrtextents,
@@ -199,15 +194,16 @@ xfs_iomap_write_direct(
 	/*
 	 * Check for running out of space, note: need lock to return
 	 */
-	if (error)
+	if (error) {
 		xfs_trans_cancel(tp, 0);
+		return XFS_ERROR(error);
+	}
+
 	xfs_ilock(ip, XFS_ILOCK_EXCL);
-	if (error)
-		goto error_out;
 
 	error = xfs_trans_reserve_quota_nblks(tp, ip, qblocks, 0, quota_flag);
 	if (error)
-		goto error1;
+		goto out_trans_cancel;
 
 	xfs_trans_ijoin(tp, ip, 0);
 
@@ -224,42 +220,39 @@ xfs_iomap_write_direct(
 	error = xfs_bmapi_write(tp, ip, offset_fsb, count_fsb, bmapi_flag,
 				&firstfsb, 0, imap, &nimaps, &free_list);
 	if (error)
-		goto error0;
+		goto out_bmap_cancel;
 
 	/*
 	 * Complete the transaction
 	 */
 	error = xfs_bmap_finish(&tp, &free_list, &committed);
 	if (error)
-		goto error0;
+		goto out_bmap_cancel;
 	error = xfs_trans_commit(tp, XFS_TRANS_RELEASE_LOG_RES);
 	if (error)
-		goto error_out;
+		goto out_unlock;
 
 	/*
 	 * Copy any maps to caller's array and return any error.
 	 */
 	if (nimaps == 0) {
-		error = ENOSPC;
-		goto error_out;
+		error = XFS_ERROR(ENOSPC);
+		goto out_unlock;
 	}
 
-	if (!(imap->br_startblock || XFS_IS_REALTIME_INODE(ip))) {
+	if (!(imap->br_startblock || XFS_IS_REALTIME_INODE(ip)))
 		error = xfs_alert_fsblock_zero(ip, imap);
-		goto error_out;
-	}
 
-	return 0;
+out_unlock:
+	xfs_iunlock(ip, XFS_ILOCK_EXCL);
+	return error;
 
-error0:	/* Cancel bmap, unlock inode, unreserve quota blocks, cancel trans */
+out_bmap_cancel:
 	xfs_bmap_cancel(&free_list);
 	xfs_trans_unreserve_quota_nblks(tp, ip, qblocks, 0, quota_flag);
-
-error1:	/* Just cancel transaction */
+out_trans_cancel:
 	xfs_trans_cancel(tp, XFS_TRANS_RELEASE_LOG_RES | XFS_TRANS_ABORT);
-
-error_out:
-	return XFS_ERROR(error);
+	goto out_unlock;
 }
 
 /*
diff --git a/fs/xfs/xfs_rtalloc.c b/fs/xfs/xfs_rtalloc.c
index ca4f315..b550379 100644
--- a/fs/xfs/xfs_rtalloc.c
+++ b/fs/xfs/xfs_rtalloc.c
@@ -859,7 +859,7 @@ xfs_rtbuf_get(
 	xfs_buf_t	*bp;		/* block buffer, result */
 	xfs_inode_t	*ip;		/* bitmap or summary inode */
 	xfs_bmbt_irec_t	map;
-	int		nmap;
+	int		nmap = 1;
 	int		error;		/* error value */
 
 	ip = issum ? mp->m_rsumip : mp->m_rbmip;
diff --git a/include/asm-generic/dma-coherent.h b/include/asm-generic/dma-coherent.h
index 85a3ffa..2be8a2d 100644
--- a/include/asm-generic/dma-coherent.h
+++ b/include/asm-generic/dma-coherent.h
@@ -3,13 +3,15 @@
 
 #ifdef CONFIG_HAVE_GENERIC_DMA_COHERENT
 /*
- * These two functions are only for dma allocator.
+ * These three functions are only for dma allocator.
  * Don't use them in device drivers.
  */
 int dma_alloc_from_coherent(struct device *dev, ssize_t size,
 				       dma_addr_t *dma_handle, void **ret);
 int dma_release_from_coherent(struct device *dev, int order, void *vaddr);
 
+int dma_mmap_from_coherent(struct device *dev, struct vm_area_struct *vma,
+			    void *cpu_addr, size_t size, int *ret);
 /*
  * Standard interface
  */
@@ -27,6 +29,7 @@ dma_mark_declared_memory_occupied(struct device *dev,
 #else
 #define dma_alloc_from_coherent(dev, size, handle, ret) (0)
 #define dma_release_from_coherent(dev, order, vaddr) (0)
+#define dma_mmap_from_coherent(dev, vma, vaddr, order, ret) (0)
 #endif
 
 #endif
diff --git a/include/asm-generic/dma-mapping-common.h b/include/asm-generic/dma-mapping-common.h
index 2e248d8..9073aeb 100644
--- a/include/asm-generic/dma-mapping-common.h
+++ b/include/asm-generic/dma-mapping-common.h
@@ -176,4 +176,41 @@ dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
 #define dma_map_sg(d, s, n, r) dma_map_sg_attrs(d, s, n, r, NULL)
 #define dma_unmap_sg(d, s, n, r) dma_unmap_sg_attrs(d, s, n, r, NULL)
 
+extern int dma_common_mmap(struct device *dev, struct vm_area_struct *vma,
+			   void *cpu_addr, dma_addr_t dma_addr, size_t size);
+
+/**
+ * dma_mmap_attrs - map a coherent DMA allocation into user space
+ * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
+ * @vma: vm_area_struct describing requested user mapping
+ * @cpu_addr: kernel CPU-view address returned from dma_alloc_attrs
+ * @handle: device-view address returned from dma_alloc_attrs
+ * @size: size of memory originally requested in dma_alloc_attrs
+ * @attrs: attributes of mapping properties requested in dma_alloc_attrs
+ *
+ * Map a coherent DMA buffer previously allocated by dma_alloc_attrs
+ * into user space.  The coherent DMA buffer must not be freed by the
+ * driver until the user space mapping has been released.
+ */
+static inline int
+dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma, void *cpu_addr,
+	       dma_addr_t dma_addr, size_t size, struct dma_attrs *attrs)
+{
+	struct dma_map_ops *ops = get_dma_ops(dev);
+	BUG_ON(!ops);
+	if (ops->mmap)
+		return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
+	return dma_common_mmap(dev, vma, cpu_addr, dma_addr, size);
+}
+
+#define dma_mmap_coherent(d, v, c, h, s) dma_mmap_attrs(d, v, c, h, s, NULL)
+
+static inline int dma_mmap_writecombine(struct device *dev, struct vm_area_struct *vma,
+		      void *cpu_addr, dma_addr_t dma_addr, size_t size)
+{
+	DEFINE_DMA_ATTRS(attrs);
+	dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
+	return dma_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, &attrs);
+}
+
 #endif
diff --git a/include/linux/async.h b/include/linux/async.h
index 68a9530..345169c 100644
--- a/include/linux/async.h
+++ b/include/linux/async.h
@@ -9,19 +9,48 @@
  * as published by the Free Software Foundation; version 2
  * of the License.
  */
+#ifndef __ASYNC_H__
+#define __ASYNC_H__
 
 #include <linux/types.h>
 #include <linux/list.h>
 
 typedef u64 async_cookie_t;
 typedef void (async_func_ptr) (void *data, async_cookie_t cookie);
+struct async_domain {
+	struct list_head node;
+	struct list_head domain;
+	int count;
+	unsigned registered:1;
+};
+
+/*
+ * domain participates in global async_synchronize_full
+ */
+#define ASYNC_DOMAIN(_name) \
+	struct async_domain _name = { .node = LIST_HEAD_INIT(_name.node), \
+				      .domain = LIST_HEAD_INIT(_name.domain), \
+				      .count = 0, \
+				      .registered = 1 }
+
+/*
+ * domain is free to go out of scope as soon as all pending work is
+ * complete, this domain does not participate in async_synchronize_full
+ */
+#define ASYNC_DOMAIN_EXCLUSIVE(_name) \
+	struct async_domain _name = { .node = LIST_HEAD_INIT(_name.node), \
+				      .domain = LIST_HEAD_INIT(_name.domain), \
+				      .count = 0, \
+				      .registered = 0 }
 
 extern async_cookie_t async_schedule(async_func_ptr *ptr, void *data);
 extern async_cookie_t async_schedule_domain(async_func_ptr *ptr, void *data,
-					    struct list_head *list);
+					    struct async_domain *domain);
+void async_unregister_domain(struct async_domain *domain);
 extern void async_synchronize_full(void);
-extern void async_synchronize_full_domain(struct list_head *list);
+extern void async_synchronize_full_domain(struct async_domain *domain);
 extern void async_synchronize_cookie(async_cookie_t cookie);
 extern void async_synchronize_cookie_domain(async_cookie_t cookie,
-					    struct list_head *list);
-
+					    struct async_domain *domain);
+extern bool current_is_async(void);
+#endif
diff --git a/include/linux/bmoca.h b/include/linux/bmoca.h
new file mode 100644
index 0000000..047a664
--- /dev/null
+++ b/include/linux/bmoca.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright (C) 2010 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BMOCA_H_
+#define _BMOCA_H_
+
+#include <linux/if.h>
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+/* NOTE: These need to match what is defined in the API template */
+#define MOCA_IE_DRV_PRINTF	0xff00
+#define MOCA_IE_WDT		0xff01
+
+#define MOCA_BAND_HIGHRF	0
+#define MOCA_BAND_MIDRF		1
+#define MOCA_BAND_WANRF		2
+#define MOCA_BAND_EXT_D		3
+#define MOCA_BAND_D_LOW		4
+#define MOCA_BAND_D_HIGH	5
+#define MOCA_BAND_E		6
+#define MOCA_BAND_F		7
+#define MOCA_BAND_G		8
+
+#define MOCA_BOOT_FLAGS_BONDED	(1 << 0)
+
+#define MOCA_IOC_MAGIC		'M'
+
+#define MOCA_IOCTL_GET_DRV_INFO_V2	_IOR(MOCA_IOC_MAGIC, 0, \
+	struct moca_kdrv_info_v2)
+
+#define MOCA_IOCTL_START	_IOW(MOCA_IOC_MAGIC, 1, struct moca_start)
+#define MOCA_IOCTL_STOP		_IO(MOCA_IOC_MAGIC, 2)
+#define MOCA_IOCTL_READMEM	_IOR(MOCA_IOC_MAGIC, 3, struct moca_xfer)
+#define MOCA_IOCTL_WRITEMEM	_IOR(MOCA_IOC_MAGIC, 4, struct moca_xfer)
+
+#define MOCA_IOCTL_CHECK_FOR_DATA	_IOR(MOCA_IOC_MAGIC, 5, int)
+#define MOCA_IOCTL_WOL		_IOW(MOCA_IOC_MAGIC, 6, int)
+#define MOCA_IOCTL_GET_DRV_INFO	_IOR(MOCA_IOC_MAGIC, 0, struct moca_kdrv_info)
+#define MOCA_IOCTL_SET_CPU_RATE	_IOR(MOCA_IOC_MAGIC, 7, unsigned int)
+#define MOCA_IOCTL_SET_PHY_RATE	_IOR(MOCA_IOC_MAGIC, 8, unsigned int)
+#define MOCA_IOCTL_GET_3450_REG	_IOR(MOCA_IOC_MAGIC, 9, unsigned int) /* Reserved */
+#define MOCA_IOCTL_SET_3450_REG	_IOR(MOCA_IOC_MAGIC, 10, unsigned int) /* Reserved */
+#define MOCA_IOCTL_GET_PROC_INFO _IOR(MOCA_IOC_MAGIC, 13, unsigned long)
+
+#define MOCA_DEVICE_ID_UNREGISTERED  (-1)
+
+/* this must match MoCAOS_IFNAMSIZE */
+#define MOCA_IFNAMSIZ		16
+
+/* Legacy version of moca_kdrv_info */
+struct moca_kdrv_info_v2 {
+	__u32			version;
+	__u32			build_number;
+	__u32			builtin_fw;
+
+	__u32			hw_rev;
+	__u32			rf_band;
+
+	__u32			uptime;
+	__s32			refcount;
+	__u32			gp1;
+
+	__s8			enet_name[MOCA_IFNAMSIZ];
+	__u32			enet_id;
+
+	__u32			macaddr_hi;
+	__u32			macaddr_lo;
+
+	__u32			phy_freq;
+	__u32			device_id;
+};
+
+/* this must match MoCAOS_DrvInfo */
+struct moca_kdrv_info {
+	__u32			version;
+	__u32			build_number;
+	__u32			builtin_fw;
+
+	__u32			hw_rev;
+	__u32			rf_band;
+
+	__u32			uptime;
+	__s32			refcount;
+	__u32			gp1;
+
+	__s8			enet_name[MOCA_IFNAMSIZ];
+	__u32			enet_id;
+
+	__u32			macaddr_hi;
+	__u32			macaddr_lo;
+
+	__u32			phy_freq;
+	__u32			cpu_freq;
+
+	__u32			chip_id;
+};
+
+struct moca_xfer {
+	__u64			buf;
+	__u32			len;
+	__u32			moca_addr;
+};
+
+struct moca_start {
+	struct moca_xfer	x;
+	__u32			boot_flags;
+};
+
+#ifdef __KERNEL__
+
+static inline void mac_to_u32(uint32_t *hi, uint32_t *lo, const uint8_t *mac)
+{
+	*hi = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | (mac[3] << 0);
+	*lo = (mac[4] << 24) | (mac[5] << 16);
+}
+
+static inline void u32_to_mac(uint8_t *mac, uint32_t hi, uint32_t lo)
+{
+	mac[0] = (hi >> 24) & 0xff;
+	mac[1] = (hi >> 16) & 0xff;
+	mac[2] = (hi >>  8) & 0xff;
+	mac[3] = (hi >>  0) & 0xff;
+	mac[4] = (lo >> 24) & 0xff;
+	mac[5] = (lo >> 16) & 0xff;
+}
+
+struct moca_platform_data {
+	char			enet_name[IFNAMSIZ];
+	unsigned int		enet_id;
+
+	u32			macaddr_hi;
+	u32			macaddr_lo;
+
+	phys_addr_t		bcm3450_i2c_base;
+	int			bcm3450_i2c_addr;
+
+	u32			hw_rev;  /* this is the chip_id */
+	u32			rf_band;
+
+	int			useDma;
+	int			useSpi;
+
+	u32			chip_id;
+};
+
+enum {
+	HWREV_MOCA_11		= 0x1100,
+	HWREV_MOCA_11_LITE	= 0x1101,
+	HWREV_MOCA_11_PLUS	= 0x1102,
+	HWREV_MOCA_20_GEN21	= 0x2001,
+	HWREV_MOCA_20_GEN22	= 0x2002,
+	HWREV_MOCA_20_GEN23	= 0x2003,
+};
+
+#define MOCA_PROTVER_11		0x1100
+#define MOCA_PROTVER_20		0x2000
+#define MOCA_PROTVER_MASK	0xff00
+
+#endif /* __KERNEL__ */
+
+#endif /* ! _BMOCA_H_ */
diff --git a/include/linux/brcmstb/7231b0/bchp_aon_ctrl.h b/include/linux/brcmstb/7231b0/bchp_aon_ctrl.h
new file mode 100644
index 0000000..646204f
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_aon_ctrl.h
@@ -0,0 +1,1578 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:21:19 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_aon_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:12p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_CTRL_H__
+#define BCHP_AON_CTRL_H__
+
+/***************************************************************************
+ *AON_CTRL - AON Control Registers
+ ***************************************************************************/
+#define BCHP_AON_CTRL_RESET_CTRL                 0x00408000 /* Reset Control register for AON */
+#define BCHP_AON_CTRL_PM_CTRL                    0x00408004 /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_STATUS                  0x00408008 /* Status register for Power Controller */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS        0x0040800c /* Power Management IRQ input status */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT         0x00408010 /* Power Management Wait counter in place of Wait for MIPS IRQ */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER        0x00408014 /* Deep Standby Assertion Timer */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER         0x00408018 /* Deep Standby Wakeup Timer */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE    0x0040801c /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_LED_CTRL                0x00408020 /* LED set control register */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES     0x00408024 /* LED set control register */
+#define BCHP_AON_CTRL_HLCD_CTRL                  0x00408030 /* HW LED Clock Driver Control */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER    0x00408034 /* Second Fraction Counter Initial value */
+#define BCHP_AON_CTRL_TIME_COUNTER               0x00408038 /* Hour/Minute Counter Initial value */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0           0x0040803c /* Digit Code for digit 0, 1, 2, 3 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1           0x00408040 /* Digit Code for digit 4, 5, 6, 7 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2           0x00408044 /* Digit Code for digit 8, 9 */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET      0x00408048 /* Hour MSD/LSD and minute MSD/LSD address offset */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL            0x0040804c /* LED status control */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0             0x00408050 /* General control register 0 */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0           0x00408054 /* General status register 0 */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0     0x00408058 /* General control register without scan 0 */
+#define BCHP_AON_CTRL_SPARE_CTRL_0               0x00408060 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_SPARE_CTRL_1               0x00408064 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH          0x00408068 /* Scratch register */
+#define BCHP_AON_CTRL_RESET_HISTORY              0x0040806c /* Reset History Register For AON */
+#define BCHP_AON_CTRL_NMI_CTRL                   0x00408070 /* Control register for NMI */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL           0x00408074 /* Ana xtal low cur 40g m7fc gisb control */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL         0x00408078 /* Test_mode control register */
+#define BCHP_AON_CTRL_SUB_TEST_MODE              0x0040807c /* Register source for sub_test_mode */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE          0x00408080 /* Final latched testmode value */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE      0x00408084 /* Final latched sub-testmode value */
+#define BCHP_AON_CTRL_PM_INITIATE                0x00408088 /* Power down initiate */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS             0x0040808c /* Power up restore */
+
+/***************************************************************************
+ *RESET_CTRL - Reset Control register for AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_CTRL :: reserved0 [31:04] */
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_MASK                    0xfffffff0
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_SHIFT                   4
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [03:03] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000008
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 3
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_DEFAULT 0
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable [02:02] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_MASK     0x00000004
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT    2
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_DEFAULT  0
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_polarity [01:01] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK   0x00000002
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT  1
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_DEFAULT 0
+
+/* AON_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_MASK          0x00000001
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_SHIFT         0
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_DEFAULT       0
+
+/***************************************************************************
+ *PM_CTRL - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_CTRL :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_MASK                       0xffffff00
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_SHIFT                      8
+
+/* AON_CTRL :: PM_CTRL :: min_s3_width_timer_bypass [07:07] */
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_MASK       0x00000080
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_SHIFT      7
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_DEFAULT    0
+
+/* AON_CTRL :: PM_CTRL :: pm_fast_power_down [06:06] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_MASK              0x00000040
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_SHIFT             6
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_DEFAULT           0
+
+/* AON_CTRL :: PM_CTRL :: pm_warm_boot [05:05] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_MASK                    0x00000020
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_SHIFT                   5
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_DEFAULT                 0
+
+/* AON_CTRL :: PM_CTRL :: pm_deep_standby [04:04] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_MASK                 0x00000010
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_SHIFT                4
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_DEFAULT              0
+
+/* AON_CTRL :: PM_CTRL :: pm_clk_divider_reset_en [03:03] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK         0x00000008
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_SHIFT        3
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_DEFAULT      1
+
+/* AON_CTRL :: PM_CTRL :: pm_use_mips_ready_ctrl [02:02] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_MASK          0x00000004
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_SHIFT         2
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_DEFAULT       0
+
+/* AON_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK             0x00000002
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT            1
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_DEFAULT          0
+
+/* AON_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_MASK                  0x00000001
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT                 0
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_DEFAULT               0
+
+/***************************************************************************
+ *PM_STATUS - Status register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_STATUS :: pm_wait_count_upper_bits [31:26] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_MASK      0xfc000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_SHIFT     26
+
+/* AON_CTRL :: PM_STATUS :: pm_wait_counter_active [25:25] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_MASK        0x02000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_SHIFT       25
+
+/* AON_CTRL :: PM_STATUS :: pm_s3_wakeup_reset_ [24:24] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__MASK           0x01000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__SHIFT          24
+
+/* AON_CTRL :: PM_STATUS :: pm_boundary_scan_request [23:23] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_MASK      0x00800000
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_SHIFT     23
+
+/* AON_CTRL :: PM_STATUS :: pm_fast_pd_precharge_valid [22:22] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_MASK    0x00400000
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_SHIFT   22
+
+/* AON_CTRL :: PM_STATUS :: pm_led_out [21:21] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_MASK                    0x00200000
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_SHIFT                   21
+
+/* AON_CTRL :: PM_STATUS :: pm_standby_b [20:20] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_MASK                  0x00100000
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_SHIFT                 20
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs_ng [19:19] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_MASK           0x00080000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_SHIFT          19
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs [18:18] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_MASK              0x00040000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_SHIFT             18
+
+/* AON_CTRL :: PM_STATUS :: pm_rst_clock_div [17:17] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_MASK              0x00020000
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_SHIFT             17
+
+/* AON_CTRL :: PM_STATUS :: pm_pwrdn_pll_req [16:16] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_MASK              0x00010000
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_SHIFT             16
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_xtal_clocks [15:15] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_MASK            0x00008000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_SHIFT           15
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_all_clocks [14:14] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_MASK             0x00004000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_SHIFT            14
+
+/* AON_CTRL :: PM_STATUS :: pm_dphy_standby [13:13] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_MASK               0x00002000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_SHIFT              13
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_cpu_clock [12:12] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_MASK              0x00001000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_SHIFT             12
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_avd_rptd_clock [11:11] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_MASK         0x00000800
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_SHIFT        11
+
+/* AON_CTRL :: PM_STATUS :: pm_power_ctrl_disable [10:10] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_MASK         0x00000400
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_SHIFT        10
+
+/* AON_CTRL :: PM_STATUS :: pm_pll_lock [09:09] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_MASK                   0x00000200
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_SHIFT                  9
+
+/* AON_CTRL :: PM_STATUS :: pm_dram_ready_for_pwrdn [08:08] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_MASK       0x00000100
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_SHIFT      8
+
+/* AON_CTRL :: PM_STATUS :: pm_bsp_ready_for_pwrdn [07:07] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK        0x00000080
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_SHIFT       7
+
+/* AON_CTRL :: PM_STATUS :: pm_mips_ready_for_pwrdn [06:06] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_MASK       0x00000040
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_SHIFT      6
+
+/* AON_CTRL :: PM_STATUS :: pm_sec_avd_rptd_clk_disable [05:05] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_MASK   0x00000020
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_SHIFT  5
+
+/* AON_CTRL :: PM_STATUS :: pm_state [04:00] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_MASK                      0x0000001f
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_SHIFT                     0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_ACTIVE                 0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_PWRDN_RDY              1
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_AVD_RPTD       2
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_CPU            3
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_STANDBY  4
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY                5
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY_WITH_PLLS_ON   6
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_RESET_216_108_CLKS     7
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_ACTIVE   8
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_FAST_PWRDN             9
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S1  10
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_COLD_ENTRY_S2 11
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_WARM_ENTRY_S2 12
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S3  13
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY           14
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S1   15
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S2   16
+
+/***************************************************************************
+ *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
+ ***************************************************************************/
+/* AON_CTRL :: PM_IRQ_INPUT_STATUS :: pm_irq_input_status [31:00] */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_MASK 0xffffffff
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_SHIFT 0
+
+/***************************************************************************
+ *PM_MIPS_WAIT_COUNT - Power Management Wait counter in place of Wait for MIPS IRQ
+ ***************************************************************************/
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_MASK            0xffff0000
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_SHIFT           16
+
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: counter_start_value [15:00] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_MASK  0x0000ffff
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_DEFAULT 16
+
+/***************************************************************************
+ *PM_S3_STANDBY_TIMER - Deep Standby Assertion Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_MASK           0xf8000000
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_SHIFT          27
+
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_MASK 0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_DEFAULT 540000
+
+/***************************************************************************
+ *PM_S3_WAKEUP_TIMER - Deep Standby Wakeup Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_MASK            0xf8000000
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_SHIFT           27
+
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_MASK  0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_DEFAULT 540000
+
+/***************************************************************************
+ *PM_FAST_PWRDN_PRECHARGE - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: reserved0 [31:24] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_MASK       0xff000000
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_SHIFT      24
+
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: pm_fast_power_down_precharge [23:00] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_MASK 0x00ffffff
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_SHIFT 0
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_DEFAULT 0
+
+/***************************************************************************
+ *PM_LED_CTRL - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_CTRL :: reserved0 [31:03] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_MASK                   0xfffffff8
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_SHIFT                  3
+
+/* AON_CTRL :: PM_LED_CTRL :: led_status [02:02] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_MASK                  0x00000004
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_SHIFT                 2
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_on [01:01] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_MASK                 0x00000002
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_SHIFT                1
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_off [00:00] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_MASK                0x00000001
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_SHIFT               0
+
+/***************************************************************************
+ *PM_LED_AUTO_ON_ENABLES - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_AUTO_ON_ENABLES :: led_status [31:00] */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_MASK       0xffffffff
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_SHIFT      0
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_DEFAULT    0
+
+/***************************************************************************
+ *HLCD_CTRL - HW LED Clock Driver Control
+ ***************************************************************************/
+/* AON_CTRL :: HLCD_CTRL :: reserved0 [31:02] */
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_MASK                     0xfffffffc
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_SHIFT                    2
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable_status [01:01] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_MASK            0x00000002
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_SHIFT           1
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable [00:00] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_MASK                   0x00000001
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_SHIFT                  0
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_DEFAULT                0
+
+/***************************************************************************
+ *SECOND_FRACTION_COUNTER - Second Fraction Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: reserved0 [31:25] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_MASK       0xfe000000
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_SHIFT      25
+
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: second_fraction_counter_init [24:00] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_MASK 0x01ffffff
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_SHIFT 0
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_DEFAULT 0
+
+/***************************************************************************
+ *TIME_COUNTER - Hour/Minute Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: TIME_COUNTER :: reserved0 [31:20] */
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_MASK                  0xfff00000
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_SHIFT                 20
+
+/* AON_CTRL :: TIME_COUNTER :: hour_display_mode [19:19] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_MASK          0x00080000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_SHIFT         19
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: mode_12h_24h_init [18:18] */
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_MASK          0x00040000
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_SHIFT         18
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: am_pm_counter_init [17:17] */
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_MASK         0x00020000
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_SHIFT        17
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_DEFAULT      0
+
+/* AON_CTRL :: TIME_COUNTER :: hour_counter_init [16:12] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_MASK          0x0001f000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_SHIFT         12
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: minute_counter_init [11:06] */
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_MASK        0x00000fc0
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_SHIFT       6
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_DEFAULT     0
+
+/* AON_CTRL :: TIME_COUNTER :: second_counter_init [05:00] */
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_MASK        0x0000003f
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_SHIFT       0
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_DEFAULT     0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_0 - Digit Code for digit 0, 1, 2, 3
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_3 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_2 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_1 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_0 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_1 - Digit Code for digit 4, 5, 6, 7
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_7 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_6 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_5 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_4 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_2 - Digit Code for digit 8, 9
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_MASK              0xffff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_SHIFT             16
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_9 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_8 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_ADDR_OFFSET - Hour MSD/LSD and minute MSD/LSD address offset
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_msd_addr_offset [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_MASK 0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_SHIFT 24
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_DEFAULT 32
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_lsd_addr_offset [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_MASK 0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_SHIFT 16
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_DEFAULT 36
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_msd_addr_offset [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_MASK 0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_SHIFT 8
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_DEFAULT 24
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_lsd_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_MASK 0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_SHIFT 0
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_DEFAULT 28
+
+/***************************************************************************
+ *LED_STATUS_CTRL - LED status control
+ ***************************************************************************/
+/* AON_CTRL :: LED_STATUS_CTRL :: reserved0 [31:28] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_MASK               0xf0000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_SHIFT              28
+
+/* AON_CTRL :: LED_STATUS_CTRL :: hlcd_state [27:25] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_MASK              0x0e000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_SHIFT             25
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_IDLE         0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_COUNT        1
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_LSD 2
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_MSD 3
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_LSD 4
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_MSD 5
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_STATUS 6
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_update_enable [24:24] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_MASK    0x01000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_SHIFT   24
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_DEFAULT 0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_mask [23:12] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_MASK             0x00fff000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_SHIFT            12
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_DEFAULT          0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_bit_offset [11:08] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_MASK       0x00000f00
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_SHIFT      8
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_DEFAULT    0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_MASK      0x000000ff
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_SHIFT     0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK         0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT        31
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK         0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT        30
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK         0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT        29
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK         0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT        28
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK         0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT        27
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK         0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT        26
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK         0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT        25
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK         0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT        24
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK         0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT        23
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK         0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT        22
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK         0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT        21
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK         0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT        20
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK         0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT        19
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK         0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT        18
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK         0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT        17
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK         0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT        16
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK         0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT        15
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK         0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT        14
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK         0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT        13
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK         0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT        12
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK         0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT        11
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK         0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT        10
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK          0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT         9
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK          0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT         8
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK          0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT         7
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK          0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT         6
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK          0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT         5
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK          0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT         4
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK          0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT         3
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK          0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT         2
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK          0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT         1
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK          0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT         0
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT       0
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_MASK              0xffffff00
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_SHIFT             8
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_MASK      0x00000080
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT     7
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_MASK      0x00000040
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT     6
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_MASK      0x00000020
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT     5
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_MASK      0x00000010
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT     4
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_MASK      0x00000008
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT     3
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_MASK      0x00000004
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT     2
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_MASK      0x00000002
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT     1
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: ejtag_ce_wakeup_event [00:00] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_MASK  0x00000001
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_MASK 0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_SHIFT 31
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_MASK 0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_SHIFT 30
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_MASK 0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_SHIFT 29
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_MASK 0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_SHIFT 28
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_MASK 0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_SHIFT 27
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_MASK 0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_SHIFT 26
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_MASK 0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_SHIFT 25
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_MASK 0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_SHIFT 24
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_MASK 0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_SHIFT 23
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_MASK 0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_SHIFT 22
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_MASK 0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_SHIFT 21
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_MASK 0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_SHIFT 20
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_MASK 0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_SHIFT 19
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_MASK 0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_SHIFT 18
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_MASK 0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_SHIFT 17
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_MASK 0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_SHIFT 16
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_MASK 0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_SHIFT 15
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_MASK 0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_SHIFT 14
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_MASK 0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_SHIFT 13
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_MASK 0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_SHIFT 12
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_MASK 0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_SHIFT 11
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_MASK 0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_SHIFT 10
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_MASK 0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_SHIFT 5
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_MASK 0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_SHIFT 4
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_MASK 0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_SHIFT 3
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_MASK 0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_SHIFT 2
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_MASK 0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_SHIFT 0
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_DEFAULT 0
+
+/***************************************************************************
+ *SPARE_CTRL_0 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_DEFAULT           0
+
+/***************************************************************************
+ *SPARE_CTRL_1 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_DEFAULT           0
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* AON_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK     0xffffffff
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT    0
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT  0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset History Register For AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_HISTORY :: reserved0 [31:19] */
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_MASK                 0xfff80000
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_SHIFT                19
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [18:18] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK    0x00040000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT   18
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [17:17] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK    0x00020000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT   17
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [16:16] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK     0x00010000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT    16
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [15:15] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK     0x00008000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT    15
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [14:14] */
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK           0x00004000
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT          14
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_DEFAULT        0
+
+/* AON_CTRL :: RESET_HISTORY :: overtemp_reset [13:13] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_MASK            0x00002000
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_SHIFT           13
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_DEFAULT         0
+
+/* AON_CTRL :: RESET_HISTORY :: overvoltage_reset [12:12] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_MASK         0x00001000
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT        12
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_DEFAULT      0
+
+/* AON_CTRL :: RESET_HISTORY :: undervoltage_reset [11:11] */
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_MASK        0x00000800
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT       11
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_DEFAULT     0
+
+/* AON_CTRL :: RESET_HISTORY :: security_dl_sw_reset [10:10] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK      0x00000400
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT     10
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_DEFAULT   0
+
+/* AON_CTRL :: RESET_HISTORY :: security_master_reset [09:09] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_MASK     0x00000200
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_SHIFT    9
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: software_master_reset [08:08] */
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_MASK     0x00000100
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_SHIFT    8
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [07:07] */
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK       0x00000080
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT      7
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_DEFAULT    0
+
+/* AON_CTRL :: RESET_HISTORY :: watchdog_timer_reset [06:06] */
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK      0x00000040
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT     6
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_DEFAULT   0
+
+/* AON_CTRL :: RESET_HISTORY :: smartcard_insert_reset [05:05] */
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK    0x00000020
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT   5
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: s3_wakeup_reset [04:04] */
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_MASK           0x00000010
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_SHIFT          4
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_DEFAULT        0
+
+/* AON_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [03:03] */
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK    0x00000008
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT   3
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: tap_in_system_reset [02:02] */
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_MASK       0x00000004
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_SHIFT      2
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_DEFAULT    0
+
+/* AON_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_MASK     0x00000002
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT    1
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_MASK            0x00000001
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_SHIFT           0
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_DEFAULT         1
+
+/***************************************************************************
+ *NMI_CTRL - Control register for NMI
+ ***************************************************************************/
+/* AON_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_MASK                0x80000000
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_SHIFT               31
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_DEFAULT             0
+
+/* AON_CTRL :: NMI_CTRL :: reserved0 [30:03] */
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_MASK                      0x7ffffff8
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_SHIFT                     3
+
+/* AON_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_MASK                0x00000004
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT               2
+
+/* AON_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_MASK            0x00000002
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT           1
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_DEFAULT         0
+
+/* AON_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_MASK                0x00000001
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT               0
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_DEFAULT             1
+
+/***************************************************************************
+ *ANA_XTAL_CONTROL - Ana xtal low cur 40g m7fc gisb control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_CONTROL :: reserved0 [31:07] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_MASK              0xffffff80
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_SHIFT             7
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_test_select_gisb_control [06:06] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_MASK 0x00000040
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_SHIFT 6
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_select_current_gisb_control [05:05] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_MASK 0x00000020
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_SHIFT 5
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_cml_sel_pd [04:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_MASK         0x00000018
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_SHIFT        3
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_DEFAULT      2
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_d2cbias_gisb_control [02:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_MASK 0x00000007
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_SHIFT 0
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_DEFAULT 4
+
+/***************************************************************************
+ *SUB_TEST_MODE_CTRL - Test_mode control register
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: reserved0 [31:01] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_MASK            0xfffffffe
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_SHIFT           1
+
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: use_sub_test_mode_reg_src [00:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_MASK 0x00000001
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_SHIFT 0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_DEFAULT 0
+
+/***************************************************************************
+ *SUB_TEST_MODE - Register source for sub_test_mode
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE :: reserved0 [31:09] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_MASK                 0xfffffe00
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_SHIFT                9
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [08:08] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK     0x00000100
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT    8
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_DEFAULT  0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [07:07] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK     0x00000080
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT    7
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_DEFAULT  0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_d2cdiff_ac [06:06] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_MASK  0x00000040
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_SHIFT 6
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [05:05] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK   0x00000020
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT  5
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_mips_in_reset [04:04] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_MASK 0x00000010
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_SHIFT 4
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [03:03] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000008
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 3
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [02:02] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000004
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 2
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK   0x00000003
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT  0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_DEFAULT 0
+
+/***************************************************************************
+ *LATCHED_TEST_MODE - Final latched testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK     0xffffffff
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT    0
+
+/***************************************************************************
+ *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0
+
+/***************************************************************************
+ *PM_INITIATE - Power down initiate
+ ***************************************************************************/
+/* AON_CTRL :: PM_INITIATE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_MASK                   0xffffff00
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_SHIFT                  8
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_7 [07:07] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_MASK               0x00000080
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_SHIFT              7
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_6 [06:06] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_MASK               0x00000040
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_SHIFT              6
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_5 [05:05] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_MASK               0x00000020
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_SHIFT              5
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_4 [04:04] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_MASK               0x00000010
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_SHIFT              4
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_3 [03:03] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_MASK               0x00000008
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_SHIFT              3
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_2 [02:02] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_MASK               0x00000004
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_SHIFT              2
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_1 [01:01] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_MASK               0x00000002
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_SHIFT              1
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_0 [00:00] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_MASK               0x00000001
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_SHIFT              0
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_DEFAULT            0
+
+/***************************************************************************
+ *HOST_MISC_CMDS - Power up restore
+ ***************************************************************************/
+/* AON_CTRL :: HOST_MISC_CMDS :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_MASK                0xffffff00
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_SHIFT               8
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_7 [07:07] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_MASK         0x00000080
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_SHIFT        7
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_6 [06:06] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_MASK         0x00000040
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_SHIFT        6
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_5 [05:05] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_MASK         0x00000020
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_SHIFT        5
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_4 [04:04] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_MASK         0x00000010
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_SHIFT        4
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_3 [03:03] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_MASK         0x00000008
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_SHIFT        3
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_2 [02:02] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_MASK         0x00000004
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_SHIFT        2
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: dram_scram_key_reuse_req [01:01] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_MASK 0x00000002
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_SHIFT 1
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_DEFAULT 0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: pm_restore [00:00] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_MASK               0x00000001
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_SHIFT              0
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_DEFAULT            0
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_BASE                  0x00408200
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_START                 0
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_END                   127
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_ELEMENT_SIZE          32
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_RAMi :: SYSTEM_DATA_RAM [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_MASK        0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_SHIFT       0
+
+
+#endif /* #ifndef BCHP_AON_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_aon_pin_ctrl.h b/include/linux/brcmstb/7231b0/bchp_aon_pin_ctrl.h
new file mode 100644
index 0000000..7c95d2a
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_aon_pin_ctrl.h
@@ -0,0 +1,613 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:04:25 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_aon_pin_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:12p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PIN_CTRL_H__
+#define BCHP_AON_PIN_CTRL_H__
+
+/***************************************************************************
+ *AON_PIN_CTRL - AON Pinmux Control Registers
+ ***************************************************************************/
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0         0x00408500 /* Pinmux control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1         0x00408504 /* Pinmux control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2         0x00408508 /* Pinmux control register 2 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3         0x0040850c /* Pinmux control register 3 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0     0x00408510 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1     0x00408514 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0     0x00408518 /* Bypass clock unselect register 0 */
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_05 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_AON_GPIO_05   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_LD1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PKT5_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_I2S_DATA0_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SC_CLK_OUT    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PWM0          5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SDIO0_WPROT   6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_HD_DVI0_16    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_TP_IN_05      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PM_AON_GPIO_05 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_04 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_AON_GPIO_04   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_LD0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PKT5_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_I2S_CLK0_OUT  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_EXT_IRQ1      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_IR_OUT        5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SDIO0_CMD     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_HD_DVI0_17    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_TP_IN_04      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PM_AON_GPIO_04 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_03 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_GPIO_03   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_OUT       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PWR_BUTTON    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_FP_4SEC_RESETB 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_EXT_IRQ0      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_IR_OUT        5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_IR_INT        6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_TP_IN_03      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PM_AON_GPIO_03 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_01 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AON_GPIO_01   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET0_LINK    1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_PWM0          2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET0_ACTIVITY 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_IR_OUT        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_VEC_VSYNC     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_RMX1_VALID    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AUD_FS_CLK1   7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET1_LINK    8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_TP_OUT_30     9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_00 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AON_GPIO_00   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AUD_SPDIF     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_TP_OUT_21     2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_hdmi_htplg [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_MASK       0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_SHIFT      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_DEFAULT    0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_AON_HDMI_HTPLG 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_TP_IN_02   1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_s3_standbyb [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_MASK      0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_SHIFT     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_DEFAULT   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_AON_S3_STANDBYB 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_TP_IN_01  1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_ir_in0 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_MASK           0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_SHIFT          0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_DEFAULT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_AON_IR_IN0     0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_TP_IN_00       1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_13 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_AON_GPIO_13   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_LED_LS1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PKT2_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_VO0_656_0     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SC1_AUX1      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SDIO0_CLK     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_HD_DVI0_8     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_TP_IN_13      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PM_AON_GPIO_13 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_12 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_AON_GPIO_12   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_LS0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PKT2_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_VO0_656_CLK   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SC1_VPP       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SDIO0_PWR0    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_HD_DVI0_9     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_TP_IN_12      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PM_AON_GPIO_12 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_11 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_GPIO_11   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_LED_LD7       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SC1_CLK       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_CODEC_MCLK    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_CLK_27    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SPI_M_SCK     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_TP_OUT_15     6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_10 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_AON_GPIO_10   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_LED_LD6       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SC1_VCC       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_CODEC_SDO     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_UART_RTS2     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SPI_M_SS0B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_TP_OUT_14     6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_09 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_AON_GPIO_09   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_LED_LD5       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SC1_RST       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_CODEC_SCLK    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_UART_TX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SPI_M_MOSI    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_HD_DVI0_12    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_TP_OUT_20     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_PM_AON_GPIO_09 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_08 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_AON_GPIO_08   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_LED_LD4       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SC1_IO        2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_CODEC_FSYNCB  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_UART_CTS2     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SPI_M_SS1B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_HD_DVI0_13    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_TP_IN_08      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_PM_AON_GPIO_08 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_07 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_AON_GPIO_07   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_LED_LD3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SC1_PRES      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_CODEC_SDI     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_UART_RX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SPI_M_MISO    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_HD_DVI0_14    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_TP_IN_07      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_PM_AON_GPIO_07 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_06 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_AON_GPIO_06   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_LED_LD2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PKT5_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_I2S_LR0_OUT   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SC_EXT_CLK    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_VEC_VSYNC     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_IR_INT        6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_HD_DVI0_15    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_TP_IN_06      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PM_AON_GPIO_06 9
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_00 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_MASK         0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SHIFT        28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_AON_SGPIO_00 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_BSC_M_SCL    1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_TP_IN_21     2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_20 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_GPIO_20   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_LED_KD3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PKT4_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_VO0_656_7     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_CLK_OBSRV     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_CLK_27    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AUD_FS_CLK1   6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_HD_DVI0_1     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_RO_OBSRV      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_TP_IN_20      9
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PM_AON_GPIO_20 10
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_19 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_AON_GPIO_19   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_LED_KD2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_PKT4_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_VO0_656_6     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SC1_PRES      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SPI_M_MISO    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SDIO0_PRES    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_HD_DVI0_2     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_TP_IN_19      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_PM_AON_GPIO_19 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_18 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_AON_GPIO_18   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_LED_KD1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PKT4_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_VO0_656_5     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SC1_IO        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SPI_M_SS1B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SDIO0_DAT3    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_HD_DVI0_3     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_TP_IN_18      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PM_AON_GPIO_18 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_17 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_AON_GPIO_17   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_LED_KD0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PKT3_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_VO0_656_4     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SC1_RST       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SPI_M_MOSI    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SDIO0_DAT2    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_HD_DVI0_4     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_TP_IN_17      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PM_AON_GPIO_17 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_16 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_AON_GPIO_16   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_LED_LS4       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PKT3_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_VO0_656_3     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SC1_CLK       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SPI_M_SCK     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SDIO0_DAT1    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_HD_DVI0_5     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_TP_IN_16      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PM_AON_GPIO_16 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_15 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_AON_GPIO_15   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_LED_LS3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PKT3_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_VO0_656_2     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SC1_VCC       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SPI_M_SS0B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SDIO0_DAT0    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_HD_DVI0_6     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_TP_IN_15      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PM_AON_GPIO_15 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_14 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_AON_GPIO_14   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_LED_LS2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_PKT2_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_VO0_656_1     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SC1_AUX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SDIO0_LED     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_HD_DVI0_7     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_TP_IN_14      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_PM_AON_GPIO_14 8
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: reserved0 [31:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_MASK            0xfffff000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_SHIFT           12
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: sgpio_01 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_MASK             0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_SHIFT            8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_DEFAULT          0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_SGPIO_01         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_BSC_M0_SDA       1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: sgpio_00 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_MASK             0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_SHIFT            4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_DEFAULT          0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_SGPIO_00         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_BSC_M0_SCL       1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_01 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_MASK         0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_SHIFT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_AON_SGPIO_01 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_BSC_M_SDA    1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_TP_IN_22     2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_09_pad_ctrl [29:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_MASK 0x30000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_SHIFT 28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_08_pad_ctrl [27:26] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_MASK 0x0c000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_SHIFT 26
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_07_pad_ctrl [25:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_MASK 0x03000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_SHIFT 24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_06_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_05_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_04_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_03_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_01_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_00_pad_ctrl [13:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_MASK 0x00003000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_SHIFT 12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [11:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x00000fff
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0x3fc00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       22
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_20_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_19_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_18_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_17_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_16_pad_ctrl [13:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_MASK 0x00003000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_SHIFT 12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_15_pad_ctrl [11:10] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_MASK 0x00000c00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_SHIFT 10
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_14_pad_ctrl [09:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_MASK 0x00000300
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_SHIFT 8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_13_pad_ctrl [07:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_MASK 0x000000c0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_SHIFT 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_12_pad_ctrl [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_11_pad_ctrl [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_10_pad_ctrl [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_MASK 0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_SHIFT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:02] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffffc
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       2
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_nmib [01:01] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_MASK 0x00000002
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_SHIFT 1
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_DEFAULT 0
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_reset_outb [00:00] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_MASK 0x00000001
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_SHIFT 0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_DEFAULT 0
+
+#endif /* #ifndef BCHP_AON_PIN_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_aon_pm_l2.h b/include/linux/brcmstb/7231b0/bchp_aon_pm_l2.h
new file mode 100644
index 0000000..b558ac8
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_aon_pm_l2.h
@@ -0,0 +1,918 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Thu Oct 27 10:23:30 2011
+ *                 MD5 Checksum         1dc065bf3d1dc88383610b02195770fc
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PM_L2_H__
+#define BCHP_AON_PM_L2_H__
+
+/***************************************************************************
+ *AON_PM_L2 - AON Power Management L2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_AON_PM_L2_CPU_STATUS                0x00408440 /* CPU interrupt Status Register */
+#define BCHP_AON_PM_L2_CPU_SET                   0x00408444 /* CPU interrupt Set Register */
+#define BCHP_AON_PM_L2_CPU_CLEAR                 0x00408448 /* CPU interrupt Clear Register */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS           0x0040844c /* CPU interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_CPU_MASK_SET              0x00408450 /* CPU interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR            0x00408454 /* CPU interrupt Mask Clear Register */
+#define BCHP_AON_PM_L2_PCI_STATUS                0x00408458 /* PCI interrupt Status Register */
+#define BCHP_AON_PM_L2_PCI_SET                   0x0040845c /* PCI interrupt Set Register */
+#define BCHP_AON_PM_L2_PCI_CLEAR                 0x00408460 /* PCI interrupt Clear Register */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS           0x00408464 /* PCI interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_PCI_MASK_SET              0x00408468 /* PCI interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR            0x0040846c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_STATUS :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_MASK                   0xffffe000
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_SHIFT                  13
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET1_MASK                   0x00001000
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET1_SHIFT                  12
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET1_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_STATUS :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_MASK                    0x00000800
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_SHIFT                   11
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00000400
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_SHIFT          10
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0
+
+/* AON_PM_L2 :: CPU_STATUS :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_MASK                        0x00000200
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_SHIFT                       9
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_MASK                        0x00000100
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_SHIFT                       8
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_MASK                     0x00000080
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_SHIFT                    7
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_MASK                    0x00000040
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_SHIFT                   6
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_DEFAULT                 0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_SET :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_MASK                      0xffffe000
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_SHIFT                     13
+
+/* AON_PM_L2 :: CPU_SET :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET1_MASK                      0x00001000
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET1_SHIFT                     12
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET1_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_SET :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_MASK                       0x00000800
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_SHIFT                      11
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_MASK              0x00000400
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_SHIFT             10
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_DEFAULT           0
+
+/* AON_PM_L2 :: CPU_SET :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_CPU_SET_USB1_MASK                           0x00000200
+#define BCHP_AON_PM_L2_CPU_SET_USB1_SHIFT                          9
+#define BCHP_AON_PM_L2_CPU_SET_USB1_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_CPU_SET_USB0_MASK                           0x00000100
+#define BCHP_AON_PM_L2_CPU_SET_USB0_SHIFT                          8
+#define BCHP_AON_PM_L2_CPU_SET_USB0_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_MASK                        0x00000080
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_SHIFT                       7
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_MASK                       0x00000040
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_SHIFT                      6
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_DEFAULT                    0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_CLEAR :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_MASK                    0xffffe000
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_SHIFT                   13
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET1_MASK                    0x00001000
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET1_SHIFT                   12
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET1_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_CLEAR :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_MASK                     0x00000800
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_SHIFT                    11
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00000400
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           10
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0
+
+/* AON_PM_L2 :: CPU_CLEAR :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_MASK                         0x00000200
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_SHIFT                        9
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_MASK                         0x00000100
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_SHIFT                        8
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_MASK                      0x00000080
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT                     7
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_MASK                     0x00000040
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_SHIFT                    6
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_DEFAULT                  0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_MASK              0xffffe000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT             13
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET1_MASK              0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET1_SHIFT             12
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET1_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_MASK               0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_SHIFT              11
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     10
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_MASK                   0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_SHIFT                  9
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_MASK                   0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_SHIFT                  8
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK                0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT               7
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_MASK               0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_SHIFT              6
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_DEFAULT            1
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_SET :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_MASK                 0xffffe000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_SHIFT                13
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET1_MASK                 0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET1_SHIFT                12
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET1_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_MASK                  0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_SHIFT                 11
+
+/* AON_PM_L2 :: CPU_MASK_SET :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        10
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_MASK                      0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_SHIFT                     9
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_MASK                      0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_SHIFT                     8
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_MASK                   0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT                  7
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_MASK                  0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_SHIFT                 6
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_DEFAULT               1
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_MASK               0xffffe000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT              13
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET1_MASK               0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET1_SHIFT              12
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET1_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_MASK                0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_SHIFT               11
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      10
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_MASK                    0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_SHIFT                   9
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_MASK                    0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_SHIFT                   8
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK                 0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT                7
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_MASK                0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_SHIFT               6
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_DEFAULT             1
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_STATUS :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_MASK                   0xffffe000
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_SHIFT                  13
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET1_MASK                   0x00001000
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET1_SHIFT                  12
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET1_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_STATUS :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_MASK                    0x00000800
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_SHIFT                   11
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00000400
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_SHIFT          10
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0
+
+/* AON_PM_L2 :: PCI_STATUS :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_MASK                        0x00000200
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_SHIFT                       9
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_MASK                        0x00000100
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_SHIFT                       8
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_MASK                     0x00000080
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_SHIFT                    7
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_MASK                    0x00000040
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_SHIFT                   6
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_DEFAULT                 0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_SET :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_MASK                      0xffffe000
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_SHIFT                     13
+
+/* AON_PM_L2 :: PCI_SET :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET1_MASK                      0x00001000
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET1_SHIFT                     12
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET1_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_SET :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_MASK                       0x00000800
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_SHIFT                      11
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_MASK              0x00000400
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_SHIFT             10
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_DEFAULT           0
+
+/* AON_PM_L2 :: PCI_SET :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_PCI_SET_USB1_MASK                           0x00000200
+#define BCHP_AON_PM_L2_PCI_SET_USB1_SHIFT                          9
+#define BCHP_AON_PM_L2_PCI_SET_USB1_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_PCI_SET_USB0_MASK                           0x00000100
+#define BCHP_AON_PM_L2_PCI_SET_USB0_SHIFT                          8
+#define BCHP_AON_PM_L2_PCI_SET_USB0_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_MASK                        0x00000080
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_SHIFT                       7
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_MASK                       0x00000040
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_SHIFT                      6
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_DEFAULT                    0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_CLEAR :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_MASK                    0xffffe000
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_SHIFT                   13
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET1_MASK                    0x00001000
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET1_SHIFT                   12
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET1_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_CLEAR :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_MASK                     0x00000800
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_SHIFT                    11
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00000400
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           10
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0
+
+/* AON_PM_L2 :: PCI_CLEAR :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_MASK                         0x00000200
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_SHIFT                        9
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_MASK                         0x00000100
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_SHIFT                        8
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_MASK                      0x00000080
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT                     7
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_MASK                     0x00000040
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_SHIFT                    6
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_DEFAULT                  0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_MASK              0xffffe000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT             13
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET1_MASK              0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET1_SHIFT             12
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET1_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_MASK               0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_SHIFT              11
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     10
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_MASK                   0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_SHIFT                  9
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_MASK                   0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_SHIFT                  8
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK                0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT               7
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_MASK               0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_SHIFT              6
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_DEFAULT            1
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_SET :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_MASK                 0xffffe000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_SHIFT                13
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET1_MASK                 0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET1_SHIFT                12
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET1_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_MASK                  0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_SHIFT                 11
+
+/* AON_PM_L2 :: PCI_MASK_SET :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        10
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_MASK                      0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_SHIFT                     9
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_MASK                      0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_SHIFT                     8
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_MASK                   0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT                  7
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_MASK                  0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_SHIFT                 6
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_DEFAULT               1
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_MASK               0xffffe000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT              13
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET1_MASK               0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET1_SHIFT              12
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET1_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_MASK                0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_SHIFT               11
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      10
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_MASK                    0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_SHIFT                   9
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_MASK                    0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_SHIFT                   8
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK                 0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT                7
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_MASK                0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_SHIFT               6
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_DEFAULT             1
+
+#endif /* #ifndef BCHP_AON_PM_L2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_bspi.h b/include/linux/brcmstb/7231b0/bchp_bspi.h
new file mode 100644
index 0000000..6c7f78f
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_bspi.h
@@ -0,0 +1,446 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:16:23 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_bspi.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 4:28p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_H__
+#define BCHP_BSPI_H__
+
+/***************************************************************************
+ *BSPI - Public BSPI Control Registers
+ ***************************************************************************/
+#define BCHP_BSPI_REVISION_ID                    0x00413000 /* Revision ID */
+#define BCHP_BSPI_SCRATCH                        0x00413004 /* Revision ID */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL               0x00413008 /* Master/Boot SPI Control Register */
+#define BCHP_BSPI_BUSY_STATUS                    0x0041300c /* BSPI Busy Status Register */
+#define BCHP_BSPI_INTR_STATUS                    0x00413010 /* Interrupt Status Register */
+#define BCHP_BSPI_B0_STATUS                      0x00413014 /* Prefetch Buffer 0 Status Register */
+#define BCHP_BSPI_B0_CTRL                        0x00413018 /* Prefetch Buffer 0 Control Register */
+#define BCHP_BSPI_B1_STATUS                      0x0041301c /* Prefetch Buffer 1 Status Register */
+#define BCHP_BSPI_B1_CTRL                        0x00413020 /* Prefetch Buffer 1 Control Register */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL            0x00413024 /* Dual/Single Receive Mode Control Register */
+#define BCHP_BSPI_FLEX_MODE_ENABLE               0x00413028 /* Flexible Control Mode Enable Register */
+#define BCHP_BSPI_BITS_PER_CYCLE                 0x0041302c /* Bits per cycle "b-p-c" Control Register */
+#define BCHP_BSPI_BITS_PER_PHASE                 0x00413030 /* Bits per Phase "b-p-p" Control Register */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE              0x00413034 /* Command and Mode Data Register */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE     0x00413038 /* Bspi FLash upper address byte register */
+#define BCHP_BSPI_BSPI_XOR_VALUE                 0x0041303c /* BSPI FLASH XOR Value Register */
+#define BCHP_BSPI_BSPI_XOR_ENABLE                0x00413040 /* BSPI FLASH XOR Enable Register */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE           0x00413044 /* BSPI Pin  Programmed IO Mode Enable Register */
+#define BCHP_BSPI_BSPI_PIO_IODIR                 0x00413048 /* BSPI Pin  Programmed IO Mode Direction Register */
+#define BCHP_BSPI_BSPI_PIO_DATA                  0x0041304c /* BSPI Pin  Programmed IO Mode Data Register */
+
+/***************************************************************************
+ *REVISION_ID - Revision ID
+ ***************************************************************************/
+/* BSPI :: REVISION_ID :: reserved0 [31:16] */
+#define BCHP_BSPI_REVISION_ID_reserved0_MASK                       0xffff0000
+#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT                      16
+
+/* BSPI :: REVISION_ID :: MAJOR [15:08] */
+#define BCHP_BSPI_REVISION_ID_MAJOR_MASK                           0x0000ff00
+#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT                          8
+#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT                        4
+
+/* BSPI :: REVISION_ID :: MINOR [07:00] */
+#define BCHP_BSPI_REVISION_ID_MINOR_MASK                           0x000000ff
+#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT                          0
+#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT                        0
+
+/***************************************************************************
+ *SCRATCH - Revision ID
+ ***************************************************************************/
+/* BSPI :: SCRATCH :: SCRATCH [31:00] */
+#define BCHP_BSPI_SCRATCH_SCRATCH_MASK                             0xffffffff
+#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT                            0
+#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT                          0
+
+/***************************************************************************
+ *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
+ ***************************************************************************/
+/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT                 1
+
+/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK                0x00000001
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT               0
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT             0
+
+/***************************************************************************
+ *BUSY_STATUS - BSPI Busy Status Register
+ ***************************************************************************/
+/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
+#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK                       0xfffffffe
+#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT                      1
+
+/* BSPI :: BUSY_STATUS :: busy [00:00] */
+#define BCHP_BSPI_BUSY_STATUS_busy_MASK                            0x00000001
+#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT                           0
+#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT                         0
+
+/***************************************************************************
+ *INTR_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
+#define BCHP_BSPI_INTR_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT                      2
+
+/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
+#define BCHP_BSPI_INTR_STATUS_intr_1_MASK                          0x00000002
+#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT                         1
+#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT                       0
+
+/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
+#define BCHP_BSPI_INTR_STATUS_intr_0_MASK                          0x00000001
+#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT                         0
+#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT                       0
+
+/***************************************************************************
+ *B0_STATUS - Prefetch Buffer 0 Status Register
+ ***************************************************************************/
+/* BSPI :: B0_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B0_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT             0
+
+/* BSPI :: B0_STATUS :: b0_full [29:29] */
+#define BCHP_BSPI_B0_STATUS_b0_full_MASK                           0x20000000
+#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT                          29
+#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT                        0
+
+/* BSPI :: B0_STATUS :: b0_empty [28:28] */
+#define BCHP_BSPI_B0_STATUS_b0_empty_MASK                          0x10000000
+#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT                         28
+#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT                       1
+
+/* BSPI :: B0_STATUS :: b0_miss [27:27] */
+#define BCHP_BSPI_B0_STATUS_b0_miss_MASK                           0x08000000
+#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT                          27
+#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT                        0
+
+/* BSPI :: B0_STATUS :: b0_hit [26:26] */
+#define BCHP_BSPI_B0_STATUS_b0_hit_MASK                            0x04000000
+#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT                           26
+#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT                         0
+
+/* BSPI :: B0_STATUS :: b0_address [25:00] */
+#define BCHP_BSPI_B0_STATUS_b0_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT                       0
+#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT                     0
+
+/***************************************************************************
+ *B0_CTRL - Prefetch Buffer 0 Control Register
+ ***************************************************************************/
+/* BSPI :: B0_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B0_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B0_CTRL :: b0_flush [00:00] */
+#define BCHP_BSPI_B0_CTRL_b0_flush_MASK                            0x00000001
+#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT                           0
+#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT                         0
+
+/***************************************************************************
+ *B1_STATUS - Prefetch Buffer 1 Status Register
+ ***************************************************************************/
+/* BSPI :: B1_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B1_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT             0
+
+/* BSPI :: B1_STATUS :: b1_full [29:29] */
+#define BCHP_BSPI_B1_STATUS_b1_full_MASK                           0x20000000
+#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT                          29
+#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT                        0
+
+/* BSPI :: B1_STATUS :: b1_empty [28:28] */
+#define BCHP_BSPI_B1_STATUS_b1_empty_MASK                          0x10000000
+#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT                         28
+#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT                       1
+
+/* BSPI :: B1_STATUS :: b1_miss [27:27] */
+#define BCHP_BSPI_B1_STATUS_b1_miss_MASK                           0x08000000
+#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT                          27
+#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT                        0
+
+/* BSPI :: B1_STATUS :: b1_hit [26:26] */
+#define BCHP_BSPI_B1_STATUS_b1_hit_MASK                            0x04000000
+#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT                           26
+#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT                         0
+
+/* BSPI :: B1_STATUS :: b1_address [25:00] */
+#define BCHP_BSPI_B1_STATUS_b1_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT                       0
+#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT                     0
+
+/***************************************************************************
+ *B1_CTRL - Prefetch Buffer 1 Control Register
+ ***************************************************************************/
+/* BSPI :: B1_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B1_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B1_CTRL :: b1_flush [00:00] */
+#define BCHP_BSPI_B1_CTRL_b1_flush_MASK                            0x00000001
+#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT                           0
+#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT                         0
+
+/***************************************************************************
+ *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
+ ***************************************************************************/
+/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK               0xffffffe0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT              5
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK             0x00000010
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT            4
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT          0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK               0x00000008
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT              3
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT            0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK      0x00000004
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT     2
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT   0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK         0x00000002
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT        1
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT      0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK                0x00000001
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT               0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT             0
+
+/***************************************************************************
+ *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT                 1
+
+/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK      0x00000001
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT     0
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT   0
+
+/***************************************************************************
+ *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK                    0xfc000000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT                   26
+
+/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK               0x03000000
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT            0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK                    0x00fc0000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT                   18
+
+/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK              0x00030000
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK                    0x0000fc00
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT                   10
+
+/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK              0x00000300
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT             8
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK                    0x000000fc
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT                   2
+
+/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK              0x00000003
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT             0
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT           0
+
+/***************************************************************************
+ *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK                    0xfe000000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT                   25
+
+/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK               0x01000000
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT            0
+
+/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK                    0x00fe0000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT                   17
+
+/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK              0x00010000
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK                    0x0000fe00
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT                   9
+
+/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK                     0x00000100
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT                    8
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT                  0
+
+/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK                 0x000000ff
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT                0
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT              8
+
+/***************************************************************************
+ *CMD_AND_MODE_BYTE - Command and Mode Data Register
+ ***************************************************************************/
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK                 0xff000000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT                24
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK            0x00ff0000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT           16
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT         0
+
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK                 0x0000ff00
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT                8
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK             0x000000ff
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT            0
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT          11
+
+/***************************************************************************
+ *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
+ ***************************************************************************/
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0
+
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK        0x00ffffff
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT       0
+
+/***************************************************************************
+ *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK               0xfff00000
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT              20
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT            0
+
+/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK                    0x000fffff
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT                  1
+
+/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK             0x00000001
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT            0
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT          0
+
+/***************************************************************************
+ *BSPI_PIO_MODE_ENABLE - BSPI Pin  Programmed IO Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK              0xfffffffe
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT             1
+
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK          0x00000001
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT         0
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT       0
+
+/***************************************************************************
+ *BSPI_PIO_IODIR - BSPI Pin  Programmed IO Mode Direction Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK                    0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT                   3
+
+/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT              3
+
+/***************************************************************************
+ *BSPI_PIO_DATA - BSPI Pin  Programmed IO Mode Data Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK                     0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT                    3
+
+/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT              0
+
+#endif /* #ifndef BCHP_BSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_bspi_raf.h b/include/linux/brcmstb/7231b0/bchp_bspi_raf.h
new file mode 100644
index 0000000..1c84a7d
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_bspi_raf.h
@@ -0,0 +1,163 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:26:50 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_bspi_raf.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 4:29p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_RAF_H__
+#define BCHP_BSPI_RAF_H__
+
+/***************************************************************************
+ *BSPI_RAF - Public Linear Read BSPI Pipe Registers
+ ***************************************************************************/
+#define BCHP_BSPI_RAF_START_ADDR                 0x00413100 /* Physical Starting Address Location in Flash device */
+#define BCHP_BSPI_RAF_NUM_WORDS                  0x00413104 /* Number of Words to be fetched */
+#define BCHP_BSPI_RAF_CTRL                       0x00413108 /* RAF Session Control Register */
+#define BCHP_BSPI_RAF_FULLNESS                   0x0041310c /* Fullness indicator for the read ahead buffer */
+#define BCHP_BSPI_RAF_WATERMARK                  0x00413110 /* Watermark level in the read ahead buffer that triggers an interrupt */
+#define BCHP_BSPI_RAF_STATUS                     0x00413114 /* Linear Read Status Register */
+#define BCHP_BSPI_RAF_READ_DATA                  0x00413118 /* Read data from Raf-buffer */
+#define BCHP_BSPI_RAF_WORD_CNT                   0x0041311c /* Current number of words fetched from Flash */
+#define BCHP_BSPI_RAF_CURR_ADDR                  0x00413120 /* Current read address for the linear read session */
+
+/***************************************************************************
+ *START_ADDR - Physical Starting Address Location in Flash device
+ ***************************************************************************/
+/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK                   0xffffffff
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT                  0
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT                0
+
+/***************************************************************************
+ *NUM_WORDS - Number of Words to be fetched
+ ***************************************************************************/
+/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK                      0xffffffff
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT                     0
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT                   0
+
+/***************************************************************************
+ *CTRL - RAF Session Control Register
+ ***************************************************************************/
+/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT                         2
+
+/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
+#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK                              0x00000002
+#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT                             1
+#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT                           0
+
+/* BSPI_RAF :: CTRL :: START [00:00] */
+#define BCHP_BSPI_RAF_CTRL_START_MASK                              0x00000001
+#define BCHP_BSPI_RAF_CTRL_START_SHIFT                             0
+#define BCHP_BSPI_RAF_CTRL_START_DEFAULT                           0
+
+/***************************************************************************
+ *FULLNESS - Fullness indicator for the read ahead buffer
+ ***************************************************************************/
+/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK                      0xffffff80
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT                     7
+
+/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK                       0x0000007f
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT                      0
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT                    0
+
+/***************************************************************************
+ *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
+ ***************************************************************************/
+/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK                     0xfffffffc
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT                    2
+
+/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK            0x00000003
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT           0
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT         0
+
+/***************************************************************************
+ *STATUS - Linear Read Status Register
+ ***************************************************************************/
+/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
+#define BCHP_BSPI_RAF_STATUS_reserved0_MASK                        0xfffffff8
+#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT                       3
+
+/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK                        0x00000004
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT                       2
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT                     0
+
+/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK                       0x00000002
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT                      1
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT                    1
+
+/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK                     0x00000001
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT                    0
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT                  0
+
+/***************************************************************************
+ *READ_DATA - Read data from Raf-buffer
+ ***************************************************************************/
+/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
+#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK                          0xffffffff
+#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT                         0
+#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT                       0
+
+/***************************************************************************
+ *WORD_CNT - Current number of words fetched from Flash
+ ***************************************************************************/
+/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK             0xffffffff
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT            0
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *CURR_ADDR - Current read address for the linear read session
+ ***************************************************************************/
+/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK               0xffffffff
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT              0
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT            0
+
+#endif /* #ifndef BCHP_BSPI_RAF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_clkgen.h b/include/linux/brcmstb/7231b0/bchp_clkgen.h
new file mode 100644
index 0000000..ad17037
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_clkgen.h
@@ -0,0 +1,4512 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:04:59 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_clkgen.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:14p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_CLKGEN_H__
+#define BCHP_CLKGEN_H__
+
+/***************************************************************************
+ *CLKGEN - clkgen registers
+ ***************************************************************************/
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL       0x00420000 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV           0x00420004 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN          0x00420008 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS   0x0042000c /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN         0x00420010 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET         0x00420014 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x00420018 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x0042001c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS        0x00420020 /* Test Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL       0x00420024 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV           0x00420028 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN          0x0042002c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS   0x00420030 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN         0x00420034 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET         0x00420038 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x0042003c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x00420040 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS        0x00420044 /* Test Status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0 0x00420048 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1 0x0042004c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2 0x00420050 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3 0x00420054 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4 0x00420058 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL          0x0042005c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV              0x00420060 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN             0x00420064 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS      0x00420068 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC             0x0042006c /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2            0x00420070 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN            0x00420074 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET            0x00420078 /* Resets */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH 0x0042007c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW 0x00420080 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS           0x00420084 /* Test Status */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 0x00420088 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL         0x0042008c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV             0x00420090 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN            0x00420094 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS     0x00420098 /* Lock Status */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC            0x0042009c /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2           0x004200a0 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN           0x004200a4 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET           0x004200a8 /* Resets */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x004200ac /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x004200b0 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS          0x004200b4 /* Test Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0 0x004200b8 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1 0x004200bc /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL           0x004200c0 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV               0x004200c4 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN              0x004200c8 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS       0x004200cc /* Lock Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC              0x004200d0 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN             0x004200d4 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET             0x004200d8 /* Resets */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH 0x004200dc /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW 0x004200e0 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS            0x004200e4 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x004200e8 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x004200ec /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x004200f0 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x004200f4 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x004200f8 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x004200fc /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL         0x00420100 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV             0x00420104 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN            0x00420108 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS     0x0042010c /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC            0x00420110 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2           0x00420114 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN           0x00420118 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET           0x0042011c /* Resets */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x00420120 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x00420124 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS          0x00420128 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 0x0042012c /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 0x00420130 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 0x00420134 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 0x00420138 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 0x0042013c /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL         0x00420140 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV             0x00420144 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN            0x00420148 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS     0x0042014c /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC            0x00420150 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN           0x00420154 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET           0x00420158 /* Resets */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH 0x0042015c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW 0x00420160 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS          0x00420164 /* Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 0x00420168 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 0x0042016c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 0x00420170 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL         0x00420174 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV             0x00420178 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC            0x0042017c /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN            0x00420180 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS     0x00420184 /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC            0x00420188 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN           0x0042018c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET           0x00420190 /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH 0x00420194 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW 0x00420198 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS          0x0042019c /* Status */
+#define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE 0x004201a0 /* Disable ANA_QDAC40G_M7FC's clocks */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE    0x004201a4 /* Bcm mips top clock enable */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE 0x004201a8 /* Bcm mips top memory standby enable */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK   0x004201ac /* Bcm mips top observe clock */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY 0x004201b0 /* Bcm mips top power switch memory */
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE         0x004201b4 /* Bvn top clock enable */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE 0x004201b8 /* Bvn top memory standby enable */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY  0x004201bc /* Bvn top power switch memory */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE         0x004201c0 /* Disable CLKGEN's clocks */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL        0x004201c4 /* Clock Monitor Control */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT      0x004201c8 /* Clock Monitor Max Reference Count */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER    0x004201cc /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE       0x004201d0 /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER   0x004201d4 /* Clock Monitor View Counter */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE       0x004201d8 /* Disable CORE_XPT's clocks */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE        0x004201dc /* Core xpt clock enable */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE 0x004201e0 /* Core xpt memory standby enable */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK       0x004201e4 /* Core xpt observe clock */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY 0x004201e8 /* Core xpt power switch memory */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE 0x004201ec /* Disable DUAL_GENET_TOP_DUAL_RGMII's clocks */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE 0x004201f0 /* Dual genet top dual rgmii clock enable */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT 0x004201f4 /* Dual genet top dual rgmii clock select */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE 0x004201f8 /* Dual genet top dual rgmii memory standby enable */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK 0x004201fc /* Dual genet top dual rgmii observe clock */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY 0x00420200 /* Dual genet top dual rgmii power switch memory */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE         0x00420204 /* Disable DVP_HT's clocks */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE          0x00420208 /* Dvp ht clock enable */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE 0x0042020c /* Dvp ht memory standby enable */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK         0x00420210 /* Dvp ht observe clock */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY   0x00420214 /* Dvp ht power switch memory */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE        0x00420218 /* Graphics clock enable */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC   0x0042021c /* Graphics clock enable m2mc */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D    0x00420220 /* Graphics clock enable v3d */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC 0x00420224 /* Graphics memory standby enable m2mc */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_V3D 0x00420228 /* Graphics memory standby enable v3d */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK       0x0042022c /* Graphics observe clock */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_M2MC 0x00420230 /* Graphics power switch memory m2mc */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_V3D 0x00420234 /* Graphics power switch memory v3d */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE            0x00420238 /* Disable HIF's clocks */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE             0x0042023c /* Hif clock enable */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO        0x00420240 /* Hif clock enable sdio */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SID         0x00420244 /* Hif clock enable sid */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE    0x00420248 /* Hif memory standby enable */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SDIO 0x0042024c /* Hif memory standby enable sdio */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SID 0x00420250 /* Hif memory standby enable sid */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY      0x00420254 /* Hif power switch memory */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SDIO 0x00420258 /* Hif power switch memory sdio */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SID  0x0042025c /* Hif power switch memory sid */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT          0x00420260 /* Mux selects for Internal clocks */
+#define BCHP_CLKGEN_MEMSYS_32_CLOCK_ENABLE       0x00420264 /* Memsys 32 clock enable */
+#define BCHP_CLKGEN_MEMSYS_32_MEMORY_STANDBY_ENABLE 0x00420268 /* Memsys 32 memory standby enable */
+#define BCHP_CLKGEN_MEMSYS_32_OBSERVE_CLOCK      0x0042026c /* Memsys 32 observe clock */
+#define BCHP_CLKGEN_MEMSYS_32_POWER_SWITCH_MEMORY 0x00420270 /* Memsys 32 power switch memory */
+#define BCHP_CLKGEN_MEMSYS_32_STATUS             0x00420274 /* Memsys 32 status */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION   0x00420278 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION   0x0042027c /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION   0x00420280 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION   0x00420284 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE            0x00420288 /* Disable PAD's clocks */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS  0x0042028c /* PLL_AUDIO0 Reset Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS  0x00420290 /* PLL_AUDIO1 Reset Status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS     0x00420294 /* PLL_AVD Reset Status */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST 0x00420298 /* PLL_MIPS Glitchless Clock Switching */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS 0x0042029c /* PLL_MIPS Glitchless Switching */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS    0x004202a0 /* PLL_MIPS Reset Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS      0x004202a4 /* PLL_SC Reset Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS    0x004202a8 /* PLL_SYS1 Reset Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS    0x004202ac /* PLL_VCXO Reset Status */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL       0x004202b0 /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x004202b4 /* PLL Alive in Standby Mode */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP           0x004202b8 /* Power management LDO PLL */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM        0x004202bc /* Power management LDO PLL state machine */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE   0x004202c0 /* Raaga dsp top clock enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE 0x004202c4 /* Raaga dsp top memory standby enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK  0x004202c8 /* Raaga dsp top observe clock */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY 0x004202cc /* Raaga dsp top power switch memory */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE      0x004202d0 /* Disable SATA3_TOP's clocks */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE       0x004202d4 /* Sata3 top clock enable */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_SELECT       0x004202d8 /* Sata3 top clock select */
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE 0x004202dc /* Sata3 top memory standby enable */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK      0x004202e0 /* Sata3 top observe clock */
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY 0x004202e4 /* Sata3 top power switch memory */
+#define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA   0x004202e8 /* Sectop clock enable m2mdma */
+#define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK         0x004202ec /* Sectop observe clock */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT         0x004202f0 /* Mux selects for Smartcard clocks */
+#define BCHP_CLKGEN_SPARE                        0x004202f4 /* Spares */
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE        0x004202f8 /* Svd0 top clock enable */
+#define BCHP_CLKGEN_SVD0_TOP_MEMORY_STANDBY_ENABLE 0x004202fc /* Svd0 top memory standby enable */
+#define BCHP_CLKGEN_SVD0_TOP_POWER_SWITCH_MEMORY 0x00420300 /* Svd0 top power switch memory */
+#define BCHP_CLKGEN_SYS_AON_MEMORY_STANDBY_ENABLE 0x00420304 /* Sys aon memory standby enable */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK        0x00420308 /* Sys aon observe clock */
+#define BCHP_CLKGEN_SYS_AON_POWER_SWITCH_MEMORY  0x0042030c /* Sys aon power switch memory */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE       0x00420310 /* Disable SYS_CTRL's clocks */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE        0x00420314 /* Sys ctrl clock enable */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE 0x00420318 /* Sys ctrl memory standby enable */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK       0x0042031c /* Sys ctrl observe clock */
+#define BCHP_CLKGEN_TESTPORT                     0x00420320 /* Special Testport Controls */
+#define BCHP_CLKGEN_USB0_CLOCK_DISABLE           0x00420324 /* Disable USB0's clocks */
+#define BCHP_CLKGEN_USB0_CLOCK_ENABLE            0x00420328 /* Usb0 clock enable */
+#define BCHP_CLKGEN_USB0_MEMORY_STANDBY_ENABLE   0x0042032c /* Usb0 memory standby enable */
+#define BCHP_CLKGEN_USB0_OBSERVE_CLOCK           0x00420330 /* Usb0 observe clock */
+#define BCHP_CLKGEN_USB0_POWER_SWITCH_MEMORY     0x00420334 /* Usb0 power switch memory */
+#define BCHP_CLKGEN_USB1_CLOCK_DISABLE           0x00420338 /* Disable USB1's clocks */
+#define BCHP_CLKGEN_USB1_CLOCK_ENABLE            0x0042033c /* Usb1 clock enable */
+#define BCHP_CLKGEN_USB1_MEMORY_STANDBY_ENABLE   0x00420340 /* Usb1 memory standby enable */
+#define BCHP_CLKGEN_USB1_OBSERVE_CLOCK           0x00420344 /* Usb1 observe clock */
+#define BCHP_CLKGEN_USB1_POWER_SWITCH_MEMORY     0x00420348 /* Usb1 power switch memory */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE    0x0042034c /* Disable VEC_AIO_TOP's clocks */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE     0x00420350 /* Vec aio top clock enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO 0x00420354 /* Vec aio top clock enable aio */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC 0x00420358 /* Vec aio top clock enable vec */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO 0x0042035c /* Vec aio top memory standby enable aio */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC 0x00420360 /* Vec aio top memory standby enable vec */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK    0x00420364 /* Vec aio top observe clock */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO 0x00420368 /* Vec aio top power switch memory aio */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC 0x0042036c /* Vec aio top power switch memory vec */
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT                1
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT            0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT                1
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT            0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 6
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT   1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 8
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT   1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 6
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT   1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 8
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT   1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 6
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_AVD_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_SHIFT              0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AVD_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_MASK                 0xffffe000
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_SHIFT                13
+
+/* CLKGEN :: PLL_AVD_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_MASK                      0x00001c00
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_SHIFT                     10
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_DEFAULT                   3
+
+/* CLKGEN :: PLL_AVD_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_MASK                  0x000003ff
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_SHIFT                 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_DEFAULT               135
+
+/***************************************************************************
+ *PLL_AVD_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_MASK                0xff000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_SHIFT               24
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 6
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x000000e0
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       5
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     2
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_MASK         0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_SHIFT        1
+
+/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_SHIFT             0
+
+/***************************************************************************
+ *PLL_AVD_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_reserved0_MASK                0x80000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_reserved0_SHIFT               31
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_MASK                  0x60000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_SHIFT                 29
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_DEFAULT               0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_MASK                  0x10000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_SHIFT                 28
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_DEFAULT               0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_MASK              0x08000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_SHIFT             27
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_MASK              0x07000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_SHIFT             24
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__MASK              0x00800000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__SHIFT             23
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_MASK                0x00600000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_SHIFT               21
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_DEFAULT             0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_MASK                0x00100000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_SHIFT               20
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_DEFAULT             0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_MASK                 0x000c0000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_SHIFT                18
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_DEFAULT              0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_MASK               0x00020000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_SHIFT              17
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_DEFAULT            0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_MASK              0x00010000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_SHIFT             16
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_MASK              0x00008000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_SHIFT             15
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_MASK                0x00004000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_SHIFT               14
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_DEFAULT             0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  13
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00001ffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         1
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_SHIFT                0
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_DEFAULT              0
+
+/***************************************************************************
+ *PLL_AVD_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_AVD_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_DEFAULT                0
+
+/***************************************************************************
+ *PLL_AVD_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_AVD_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_SHIFT              0
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AVD_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_MASK               0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_SHIFT              2
+
+/* CLKGEN :: PLL_AVD_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_MASK                  0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_SHIFT                 1
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_DEFAULT               0
+
+/* CLKGEN :: PLL_AVD_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_SHIFT                 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_DEFAULT               0
+
+/***************************************************************************
+ *PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_MASK              0xfffff000
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_SHIFT             12
+
+/* CLKGEN :: PLL_AVD_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_SHIFT           0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 4
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_MIPS_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_DEFAULT                  2
+
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_DEFAULT              88
+
+/***************************************************************************
+ *PLL_MIPS_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 3
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_DEFAULT              0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_DEFAULT             0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_DEFAULT           0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_DEFAULT               0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MIPS_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT  40
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT  40
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SC_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_MASK                  0xffffe000
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_SHIFT                 13
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_MASK                       0x00001c00
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_SHIFT                      10
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_DEFAULT                    1
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_MASK                   0x000003ff
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_DEFAULT                64
+
+/***************************************************************************
+ *PLL_SC_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_MASK                 0xff000000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_SHIFT                24
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK         0x000000e0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT        5
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT      1
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_SHIFT              0
+
+/***************************************************************************
+ *PLL_SC_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_MASK                 0xc0000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_SHIFT                30
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_MASK                   0x30000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_SHIFT                  28
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_MASK              0x08000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_SHIFT             27
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_DEFAULT           0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_MASK                   0x04000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_SHIFT                  26
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_MASK               0x02000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_SHIFT              25
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_MASK               0x01c00000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_SHIFT              22
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__MASK               0x00200000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__SHIFT              21
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_MASK                 0x00180000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_SHIFT                19
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_MASK                 0x00040000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_SHIFT                18
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_MASK                  0x00030000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_SHIFT                 16
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_DEFAULT               0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_MASK               0x00008000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_SHIFT              15
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_MASK                 0x00004000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_SHIFT                14
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK    0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT   13
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_MASK           0x00001ffe
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_SHIFT          1
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT        0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_DEFAULT               0
+
+/***************************************************************************
+ *PLL_SC_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_SHIFT               1
+
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_SHIFT               2
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_MASK                   0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_SHIFT                  1
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_DEFAULT                0
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK  0x00400000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_MASK               0xfffff000
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_SHIFT              12
+
+/* CLKGEN :: PLL_SC_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_MASK             0x00000fff
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 12
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 26
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 8
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 9
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 96
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 54
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT                  2
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT              96
+
+/***************************************************************************
+ *PLL_SYS0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 3
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT             0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT           0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT               0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_RESET :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_RESET :: RESETD [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_DEFAULT              0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 9
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 18
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 9
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 90
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 90
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_DEFAULT                  3
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_DEFAULT              125
+
+/***************************************************************************
+ *PLL_SYS1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    1
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_MASK                 0x30000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_SHIFT           27
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_DEFAULT         0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_DEFAULT              1
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_MASK             0x02000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_SHIFT            25
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_MASK             0x01c00000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_SHIFT            22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__MASK             0x00200000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__SHIFT            21
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_SHIFT              19
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_MASK                0x00030000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_SHIFT               16
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_DEFAULT             2
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 64
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 250
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 75
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_DEFAULT                  2
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_DEFAULT              64
+
+/***************************************************************************
+ *PLL_VCXO_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_MASK               0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_SHIFT              20
+
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_MASK            0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_SHIFT           0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    1
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_MASK                 0x30000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_SHIFT                28
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_SHIFT           27
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_DEFAULT         0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_MASK             0x02000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_SHIFT            25
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_MASK             0x01c00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_SHIFT            22
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__MASK             0x00200000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__SHIFT            21
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_SHIFT              19
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_MASK                0x00030000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_SHIFT               16
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_DEFAULT             0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_SHIFT            15
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *ANA_QDAC40G_M7FC_CLOCK_DISABLE - Disable ANA_QDAC40G_M7FC's clocks
+ ***************************************************************************/
+/* CLKGEN :: ANA_QDAC40G_M7FC_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: ANA_QDAC40G_M7FC_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
+#define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *BCM_MIPS_TOP_CLOCK_ENABLE - Bcm mips top clock enable
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffff8
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_SHIFT      3
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE - Bcm mips top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: MIPS_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *BCM_MIPS_TOP_OBSERVE_CLOCK - Bcm mips top observe clock
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_SHIFT     1
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *BCM_MIPS_TOP_POWER_SWITCH_MEMORY - Bcm mips top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: MIPS_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *BVN_TOP_CLOCK_ENABLE - Bvn top clock enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_reserved0_MASK            0xfffffff8
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_reserved0_SHIFT           3
+
+/* CLKGEN :: BVN_TOP_CLOCK_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: BVN_TOP_CLOCK_ENABLE :: BVN_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: BVN_TOP_CLOCK_ENABLE :: BVN_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *BVN_TOP_MEMORY_STANDBY_ENABLE - Bvn top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: BVN_TOP_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *BVN_TOP_POWER_SWITCH_MEMORY - Bvn top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: BVN_TOP_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks
+ ***************************************************************************/
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT           1
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_AVS_CLOCK [00:00] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_MASK    0x00000001
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_SHIFT   0
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_CONTROL - Clock Monitor Control
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT          4
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK   0x00000008
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT  3
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK    0x00000004
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT   2
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK      0x00000002
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT     1
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT   1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 1
+
+/***************************************************************************
+ *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK  0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT         1
+
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK     0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT    0
+
+/***************************************************************************
+ *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CORE_XPT_CLOCK_DISABLE - Disable CORE_XPT's clocks
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_SHIFT         5
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_CLOCK_ENABLE - Core xpt clock enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_MASK           0xfffffff8
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_SHIFT          3
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *CORE_XPT_MEMORY_STANDBY_ENABLE - Core xpt memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_OBSERVE_CLOCK - Core xpt observe clock
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_SHIFT         1
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_POWER_SWITCH_MEMORY - Core xpt power switch memory
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE - Disable DUAL_GENET_TOP_DUAL_RGMII's clocks
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: reserved0 [31:08] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_reserved0_MASK 0xffffff00
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_reserved0_SHIFT 8
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET_ALWAYSON_CLOCK [07:07] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_MASK 0x00000080
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_SHIFT 7
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET_25_PHY_LVCLOCK [06:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET_25_PHY_LVCLOCK_MASK 0x00000040
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET_25_PHY_LVCLOCK_SHIFT 6
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET_25_PHY_LVCLOCK_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_PM_CLOCK [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_FAST_CLOCK [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_FAST_CLOCK [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE - Dual genet top dual rgmii clock enable
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: reserved0 [31:16] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_reserved0_SHIFT 16
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [15:15] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00008000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 15
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET_108_CLOCK_ENABLE [14:14] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_MASK 0x00004000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_SHIFT 14
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE [13:13] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE [12:12] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00001000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET1_L2INTR_CLOCK_ENABLE [11:11] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_MASK 0x00000800
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_SHIFT 11
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET1_HFB_CLOCK_ENABLE [10:10] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_MASK 0x00000400
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_SHIFT 10
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET1_GMII_CLOCK_ENABLE [09:09] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_MASK 0x00000200
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_SHIFT 9
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET1_EEE_CLOCK_ENABLE [08:08] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_MASK 0x00000100
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_SHIFT 8
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET1_CLK_250_CLOCK_ENABLE [07:07] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_MASK 0x00000080
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_SHIFT 7
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET0_L2INTR_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET0_HFB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET0_GMII_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET0_EEE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET0_CLK_250_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT - Dual genet top dual rgmii clock select
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT :: reserved0 [31:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_reserved0_SHIFT 4
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT :: GENET1_GMII_CLOCK_SELECT [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT :: GENET1_CLOCK_SELECT [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET1_CLOCK_SELECT_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET1_CLOCK_SELECT_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET1_CLOCK_SELECT_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT :: GENET0_GMII_CLOCK_SELECT [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT :: GENET0_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET0_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET0_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET0_CLOCK_SELECT_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE - Dual genet top dual rgmii memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE :: GENET0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE_GENET0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE_GENET0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE_GENET0_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK - Dual genet top dual rgmii observe clock
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK :: GENET_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK :: GENET_BROADCAST_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_BROADCAST_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_BROADCAST_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_BROADCAST_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK :: GENET_BROADCAST_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_BROADCAST_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_BROADCAST_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_BROADCAST_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY - Dual genet top dual rgmii power switch memory
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY :: GENET0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY_GENET0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY_GENET0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY_GENET0_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_CLOCK_DISABLE - Disable DVP_HT's clocks
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_SHIFT           1
+
+/* CLKGEN :: DVP_HT_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_CLOCK_ENABLE - Dvp ht clock enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_MASK             0xfffffff0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_SHIFT            4
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: VEC_IF_216_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_VEC_IF_216_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_VEC_IF_216_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_VEC_IF_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_MAX_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_MAX_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_MAX_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_MAX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *DVP_HT_MEMORY_STANDBY_ENABLE - Dvp ht memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_MASK    0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT   1
+
+/* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_OBSERVE_CLOCK - Dvp ht observe clock
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_SHIFT           1
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_POWER_SWITCH_MEMORY - Dvp ht power switch memory
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_SHIFT     2
+
+/* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_CLOCK_ENABLE - Graphics clock enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_reserved0_SHIFT          1
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *GRAPHICS_CLOCK_ENABLE_M2MC - Graphics clock enable m2mc
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE_M2MC :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_reserved0_SHIFT     2
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE_M2MC :: M2MC_SCB_CLOCK_ENABLE_M2MC [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_M2MC_SCB_CLOCK_ENABLE_M2MC_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_M2MC_SCB_CLOCK_ENABLE_M2MC_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_M2MC_SCB_CLOCK_ENABLE_M2MC_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE_M2MC :: M2MC_CORE_CLOCK_ENABLE_M2MC [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_M2MC_CORE_CLOCK_ENABLE_M2MC_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_M2MC_CORE_CLOCK_ENABLE_M2MC_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_M2MC_CORE_CLOCK_ENABLE_M2MC_DEFAULT 1
+
+/***************************************************************************
+ *GRAPHICS_CLOCK_ENABLE_V3D - Graphics clock enable v3d
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE_V3D :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_reserved0_SHIFT      2
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE_V3D :: V3D_SCB_CLOCK_ENABLE_V3D [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_V3D_SCB_CLOCK_ENABLE_V3D_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_V3D_SCB_CLOCK_ENABLE_V3D_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_V3D_SCB_CLOCK_ENABLE_V3D_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE_V3D :: V3D_CORE_CLOCK_ENABLE_V3D [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_V3D_CORE_CLOCK_ENABLE_V3D_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_V3D_CORE_CLOCK_ENABLE_V3D_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_V3D_CORE_CLOCK_ENABLE_V3D_DEFAULT 1
+
+/***************************************************************************
+ *GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC - Graphics memory standby enable m2mc
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC :: M2MC_MEMORY_STANDBY_ENABLE_M2MC [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC_M2MC_MEMORY_STANDBY_ENABLE_M2MC_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC_M2MC_MEMORY_STANDBY_ENABLE_M2MC_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC_M2MC_MEMORY_STANDBY_ENABLE_M2MC_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_MEMORY_STANDBY_ENABLE_V3D - Graphics memory standby enable v3d
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE_V3D :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_V3D_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_V3D_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE_V3D :: V3D_MEMORY_STANDBY_ENABLE_V3D [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_V3D_V3D_MEMORY_STANDBY_ENABLE_V3D_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_V3D_V3D_MEMORY_STANDBY_ENABLE_V3D_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_V3D_V3D_MEMORY_STANDBY_ENABLE_V3D_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_OBSERVE_CLOCK - Graphics observe clock
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_reserved0_SHIFT         1
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_POWER_SWITCH_MEMORY_M2MC - Graphics power switch memory m2mc
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY_M2MC :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_M2MC_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_M2MC_reserved0_SHIFT 2
+
+/* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY_M2MC :: GFX_POWER_SWITCH_MEMORY_M2MC [01:00] */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_M2MC_GFX_POWER_SWITCH_MEMORY_M2MC_MASK 0x00000003
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_M2MC_GFX_POWER_SWITCH_MEMORY_M2MC_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_M2MC_GFX_POWER_SWITCH_MEMORY_M2MC_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_POWER_SWITCH_MEMORY_V3D - Graphics power switch memory v3d
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY_V3D :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_V3D_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_V3D_reserved0_SHIFT 2
+
+/* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY_V3D :: GFX_POWER_SWITCH_MEMORY_V3D [01:00] */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_V3D_GFX_POWER_SWITCH_MEMORY_V3D_MASK 0x00000003
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_V3D_GFX_POWER_SWITCH_MEMORY_V3D_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_V3D_GFX_POWER_SWITCH_MEMORY_V3D_DEFAULT 0
+
+/***************************************************************************
+ *HIF_CLOCK_DISABLE - Disable HIF's clocks
+ ***************************************************************************/
+/* CLKGEN :: HIF_CLOCK_DISABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_reserved0_MASK               0xfffffff8
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_reserved0_SHIFT              3
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [02:02] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK   0x00000004
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT  2
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CLOCK [01:01] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_MASK  0x00000002
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_DEFAULT 0
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_EBI_CLOCK [00:00] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_MASK   0x00000001
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_SHIFT  0
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *HIF_CLOCK_ENABLE - Hif clock enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_reserved0_SHIFT               2
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_MASK     0x00000002
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_SHIFT    1
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_DEFAULT  1
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_MASK     0x00000001
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_SHIFT    0
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_DEFAULT  1
+
+/***************************************************************************
+ *HIF_CLOCK_ENABLE_SDIO - Hif clock enable sdio
+ ***************************************************************************/
+/* CLKGEN :: HIF_CLOCK_ENABLE_SDIO :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_reserved0_MASK           0xfffffffc
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_reserved0_SHIFT          2
+
+/* CLKGEN :: HIF_CLOCK_ENABLE_SDIO :: SDIO_SCB_CLOCK_ENABLE_SDIO [01:01] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_SDIO_SCB_CLOCK_ENABLE_SDIO_MASK 0x00000002
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_SDIO_SCB_CLOCK_ENABLE_SDIO_SHIFT 1
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_SDIO_SCB_CLOCK_ENABLE_SDIO_DEFAULT 1
+
+/* CLKGEN :: HIF_CLOCK_ENABLE_SDIO :: SDIO_216_CLOCK_ENABLE_SDIO [00:00] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_SDIO_216_CLOCK_ENABLE_SDIO_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_SDIO_216_CLOCK_ENABLE_SDIO_SHIFT 0
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_SDIO_216_CLOCK_ENABLE_SDIO_DEFAULT 1
+
+/***************************************************************************
+ *HIF_CLOCK_ENABLE_SID - Hif clock enable sid
+ ***************************************************************************/
+/* CLKGEN :: HIF_CLOCK_ENABLE_SID :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SID_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SID_reserved0_SHIFT           2
+
+/* CLKGEN :: HIF_CLOCK_ENABLE_SID :: SID_SCB_CLOCK_ENABLE_SID [01:01] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SID_SID_SCB_CLOCK_ENABLE_SID_MASK 0x00000002
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SID_SID_SCB_CLOCK_ENABLE_SID_SHIFT 1
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SID_SID_SCB_CLOCK_ENABLE_SID_DEFAULT 1
+
+/* CLKGEN :: HIF_CLOCK_ENABLE_SID :: SID_216_CLOCK_ENABLE_SID [00:00] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SID_SID_216_CLOCK_ENABLE_SID_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SID_SID_216_CLOCK_ENABLE_SID_SHIFT 0
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SID_SID_216_CLOCK_ENABLE_SID_DEFAULT 1
+
+/***************************************************************************
+ *HIF_MEMORY_STANDBY_ENABLE - Hif memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE :: HIF_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *HIF_MEMORY_STANDBY_ENABLE_SDIO - Hif memory standby enable sdio
+ ***************************************************************************/
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE_SDIO :: reserved0 [31:01] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SDIO_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SDIO_reserved0_SHIFT 1
+
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE_SDIO :: SDIO_MEMORY_STANDBY_ENABLE_SDIO [00:00] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SDIO_SDIO_MEMORY_STANDBY_ENABLE_SDIO_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SDIO_SDIO_MEMORY_STANDBY_ENABLE_SDIO_SHIFT 0
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SDIO_SDIO_MEMORY_STANDBY_ENABLE_SDIO_DEFAULT 0
+
+/***************************************************************************
+ *HIF_MEMORY_STANDBY_ENABLE_SID - Hif memory standby enable sid
+ ***************************************************************************/
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE_SID :: reserved0 [31:01] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SID_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SID_reserved0_SHIFT  1
+
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE_SID :: SID_MEMORY_STANDBY_ENABLE_SID [00:00] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SID_SID_MEMORY_STANDBY_ENABLE_SID_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SID_SID_MEMORY_STANDBY_ENABLE_SID_SHIFT 0
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SID_SID_MEMORY_STANDBY_ENABLE_SID_DEFAULT 0
+
+/***************************************************************************
+ *HIF_POWER_SWITCH_MEMORY - Hif power switch memory
+ ***************************************************************************/
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_reserved0_SHIFT        2
+
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY :: HIF_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *HIF_POWER_SWITCH_MEMORY_SDIO - Hif power switch memory sdio
+ ***************************************************************************/
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY_SDIO :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SDIO_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SDIO_reserved0_SHIFT   2
+
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY_SDIO :: SDIO_POWER_SWITCH_MEMORY_SDIO [01:00] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SDIO_SDIO_POWER_SWITCH_MEMORY_SDIO_MASK 0x00000003
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SDIO_SDIO_POWER_SWITCH_MEMORY_SDIO_SHIFT 0
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SDIO_SDIO_POWER_SWITCH_MEMORY_SDIO_DEFAULT 0
+
+/***************************************************************************
+ *HIF_POWER_SWITCH_MEMORY_SID - Hif power switch memory sid
+ ***************************************************************************/
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY_SID :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SID_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SID_reserved0_SHIFT    2
+
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY_SID :: SID_POWER_SWITCH_MEMORY_SID [01:00] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SID_SID_POWER_SWITCH_MEMORY_SID_MASK 0x00000003
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SID_SID_POWER_SWITCH_MEMORY_SID_SHIFT 0
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SID_SID_POWER_SWITCH_MEMORY_SID_DEFAULT 0
+
+/***************************************************************************
+ *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
+ ***************************************************************************/
+/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:04] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK             0xfffffff0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT            4
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [03:03] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [02:02] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: GFX_M2MC_CORE_CLOCK [01:00] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_MASK   0x00000003
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_SHIFT  0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_32_CLOCK_ENABLE - Memsys 32 clock enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: MEMSYS_32_CLOCK_ENABLE :: DDR_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MEMSYS_32_CLOCK_ENABLE_DDR_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_32_CLOCK_ENABLE_DDR_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MEMSYS_32_CLOCK_ENABLE_DDR_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: MEMSYS_32_CLOCK_ENABLE :: DDR_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_CLOCK_ENABLE_DDR_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_CLOCK_ENABLE_DDR_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_CLOCK_ENABLE_DDR_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *MEMSYS_32_MEMORY_STANDBY_ENABLE - Memsys 32 memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MEMSYS_32_MEMORY_STANDBY_ENABLE :: DDR_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_MEMORY_STANDBY_ENABLE_DDR_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_MEMORY_STANDBY_ENABLE_DDR_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_MEMORY_STANDBY_ENABLE_DDR_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_32_OBSERVE_CLOCK - Memsys 32 observe clock
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_OBSERVE_CLOCK_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_OBSERVE_CLOCK_reserved0_SHIFT        1
+
+/* CLKGEN :: MEMSYS_32_OBSERVE_CLOCK :: MEMSYS_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_32_POWER_SWITCH_MEMORY - Memsys 32 power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: MEMSYS_32_POWER_SWITCH_MEMORY :: MEMSYS_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MEMSYS_32_POWER_SWITCH_MEMORY_MEMSYS_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MEMSYS_32_POWER_SWITCH_MEMORY_MEMSYS_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_POWER_SWITCH_MEMORY_MEMSYS_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_32_STATUS - Memsys 32 status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_STATUS_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_STATUS_reserved0_SHIFT               1
+
+/* CLKGEN :: MEMSYS_32_STATUS :: MEMSYS_PLL_LOCKED_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_STATUS_MEMSYS_PLL_LOCKED_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_STATUS_MEMSYS_PLL_LOCKED_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PAD_CLK_OBSRV0_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLK_OBSRV1_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLK_OBSRV2_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLK_OBSRV3_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLOCK_DISABLE - Disable PAD's clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT              1
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET_STATUS - PLL_AUDIO0 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET_STATUS - PLL_AUDIO1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_RESET_STATUS - PLL_AVD Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_MIPS_GLITCHLESS_SWITCH_REQUEST - PLL_MIPS Glitchless Clock Switching
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_reserved0_SHIFT 9
+
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: TRANSACTION_WAIT [08:01] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_DEFAULT 31
+
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: PLL_BYPASS_REQUEST [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_GLITCHLESS_SWITCH_STATUS - PLL_MIPS Glitchless Switching
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_STATUS :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_reserved0_SHIFT 4
+
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_STATUS :: PLL_BYPASS_STATUS [03:00] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_MASK 0x0000000f
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_RESET_STATUS - PLL_MIPS Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET_STATUS - PLL_SC Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET_STATUS - PLL_SYS1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET_STATUS - PLL_VCXO Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PM_CLOCK_216_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_SHIFT         1
+
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_MASK   0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT  0
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_DEFAULT 0
+
+/***************************************************************************
+ *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               3
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys_PLL [02:02] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_MASK               0x00000004
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_SHIFT              2
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_DEFAULT            0
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [01:01] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK                 0x00000002
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT                1
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT              0
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_MIPS [00:00] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_MASK                 0x00000001
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_SHIFT                0
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_DEFAULT              0
+
+/***************************************************************************
+ *PM_PLL_LDO_POWERUP - Power management LDO PLL
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_SHIFT             1
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AVD [00:00] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_MASK      0x00000001
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_SHIFT     0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_DEFAULT   1
+
+/***************************************************************************
+ *PM_PLL_LDO_POWERUP_SM - Power management LDO PLL state machine
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: reserved0 [31:27] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_MASK           0xf8000000
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_SHIFT          27
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_POWERUP_WAIT_TIME [26:14] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_MASK 0x07ffc000
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_SHIFT 14
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_DEFAULT 5400
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_CLK_STOP_WAIT_TIME [13:01] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_MASK 0x00003ffe
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_SHIFT 1
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_DEFAULT 200
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: GISB_OVERRIDE_SM [00:00] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_MASK    0x00000001
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_SHIFT   0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_DEFAULT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_CLOCK_ENABLE - Raaga dsp top clock enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_reserved0_MASK      0xfffffff8
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_reserved0_SHIFT     3
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_DSP_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE - Raaga dsp top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE :: RAAGA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGA_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_OBSERVE_CLOCK - Raaga dsp top observe clock
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_reserved0_SHIFT    1
+
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: RAAGA_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_POWER_SWITCH_MEMORY - Raaga dsp top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_POWER_SWITCH_MEMORY :: RAAGA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SATA3_TOP_CLOCK_DISABLE - Disable SATA3_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_reserved0_SHIFT        1
+
+/* CLKGEN :: SATA3_TOP_CLOCK_DISABLE :: DISABLE_SATA_LV_CLK_30 [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_LV_CLK_30_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_LV_CLK_30_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_LV_CLK_30_DEFAULT 1
+
+/***************************************************************************
+ *SATA3_TOP_CLOCK_ENABLE - Sata3 top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: SATA3_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: SATA3_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SATA3_TOP_CLOCK_SELECT - Sata3 top clock select
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_CLOCK_SELECT :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_SELECT_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_SELECT_reserved0_SHIFT         1
+
+/* CLKGEN :: SATA3_TOP_CLOCK_SELECT :: SATA3_REF_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_DEFAULT 1
+
+/***************************************************************************
+ *SATA3_TOP_MEMORY_STANDBY_ENABLE - Sata3 top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SATA3_TOP_MEMORY_STANDBY_ENABLE :: SATA3_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SATA3_TOP_OBSERVE_CLOCK - Sata3 top observe clock
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_reserved0_SHIFT        1
+
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: SATA3_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SATA3_TOP_POWER_SWITCH_MEMORY - Sata3 top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: SATA3_TOP_POWER_SWITCH_MEMORY :: SATA3_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SECTOP_CLOCK_ENABLE_M2MDMA - Sectop clock enable m2mdma
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_CLOCK_ENABLE_M2MDMA :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA_reserved0_SHIFT     1
+
+/* CLKGEN :: SECTOP_CLOCK_ENABLE_M2MDMA :: M2M_DMA_SCB_CLOCK_ENABLE_M2MDMA [00:00] */
+#define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA_M2M_DMA_SCB_CLOCK_ENABLE_M2MDMA_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA_M2M_DMA_SCB_CLOCK_ENABLE_M2MDMA_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA_M2M_DMA_SCB_CLOCK_ENABLE_M2MDMA_DEFAULT 1
+
+/***************************************************************************
+ *SECTOP_OBSERVE_CLOCK - Sectop observe clock
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK_reserved0_SHIFT           1
+
+/* CLKGEN :: SECTOP_OBSERVE_CLOCK :: SEC_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK_SEC_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK_SEC_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK_SEC_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
+ ***************************************************************************/
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:11] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK            0xfffff800
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT           11
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC_OUT_CLOCK [10:08] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_MASK         0x00000700
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_SHIFT        8
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_DEFAULT      0
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [07:05] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK            0x000000e0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT           5
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT         0
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [04:02] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK            0x0000001c
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT           2
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT         0
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: PLLSC_REFERENCE_CLOCK [01:00] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_MASK 0x00000003
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SPARE - Spares
+ ***************************************************************************/
+/* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK                     0xfffff000
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT                    12
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT                  0
+
+/* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK                    0x00000fff
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT                   0
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT                 0
+
+/***************************************************************************
+ *SVD0_TOP_CLOCK_ENABLE - Svd0 top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_reserved0_SHIFT          4
+
+/* CLKGEN :: SVD0_TOP_CLOCK_ENABLE :: SVD_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SVD0_TOP_CLOCK_ENABLE :: SVD_CPU_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SVD0_TOP_CLOCK_ENABLE :: SVD_CORE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_CORE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_CORE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_CORE_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SVD0_TOP_CLOCK_ENABLE :: SVD_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SVD0_TOP_MEMORY_STANDBY_ENABLE - Svd0 top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_SVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SVD0_TOP_MEMORY_STANDBY_ENABLE :: SVD_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SVD0_TOP_POWER_SWITCH_MEMORY - Svd0 top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SVD0_TOP_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_SVD0_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: SVD0_TOP_POWER_SWITCH_MEMORY :: SVD_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SYS_AON_MEMORY_STANDBY_ENABLE - Sys aon memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_AON_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_AON_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_SYS_AON_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: SYS_AON_MEMORY_STANDBY_ENABLE :: AON_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_AON_MEMORY_STANDBY_ENABLE_AON_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_AON_MEMORY_STANDBY_ENABLE_AON_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_AON_MEMORY_STANDBY_ENABLE_AON_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SYS_AON_OBSERVE_CLOCK - Sys aon observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_SHIFT          1
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SYS_AON_POWER_SWITCH_MEMORY - Sys aon power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SYS_AON_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SYS_AON_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_SYS_AON_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: SYS_AON_POWER_SWITCH_MEMORY :: AON_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SYS_AON_POWER_SWITCH_MEMORY_AON_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SYS_AON_POWER_SWITCH_MEMORY_AON_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SYS_AON_POWER_SWITCH_MEMORY_AON_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_CLOCK_DISABLE - Disable SYS_CTRL's clocks
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_MASK          0xfffffff0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_SHIFT         4
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [03:03] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK [02:02] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK  0x00000002
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK  0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_CLOCK_ENABLE - Sys ctrl clock enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_SHIFT          1
+
+/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: SYS_CTRL_SCB_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SYS_CTRL_MEMORY_STANDBY_ENABLE - Sys ctrl memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_OBSERVE_CLOCK - Sys ctrl observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_SHIFT         1
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *TESTPORT - Special Testport Controls
+ ***************************************************************************/
+/* CLKGEN :: TESTPORT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_TESTPORT_reserved0_MASK                        0xfffffff8
+#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT                       3
+
+/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [02:00] */
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK           0x00000007
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT          0
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT        0
+
+/***************************************************************************
+ *USB0_CLOCK_DISABLE - Disable USB0's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB0_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_CLOCK_DISABLE_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_USB0_CLOCK_DISABLE_reserved0_SHIFT             2
+
+/* CLKGEN :: USB0_CLOCK_DISABLE :: DISABLE_USB_54_MDIO_CLOCK [01:01] */
+#define BCHP_CLKGEN_USB0_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_USB0_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB0_CLOCK_DISABLE :: DISABLE_USB0_27_FREERUN_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB0_CLOCK_DISABLE_DISABLE_USB0_27_FREERUN_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_CLOCK_DISABLE_DISABLE_USB0_27_FREERUN_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB0_CLOCK_DISABLE_DISABLE_USB0_27_FREERUN_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB0_CLOCK_ENABLE - Usb0 clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB0_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_CLOCK_ENABLE_reserved0_MASK               0xfffffffc
+#define BCHP_CLKGEN_USB0_CLOCK_ENABLE_reserved0_SHIFT              2
+
+/* CLKGEN :: USB0_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB0_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK   0x00000002
+#define BCHP_CLKGEN_USB0_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT  1
+#define BCHP_CLKGEN_USB0_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: USB0_CLOCK_ENABLE :: USB0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB0_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK   0x00000001
+#define BCHP_CLKGEN_USB0_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT  0
+#define BCHP_CLKGEN_USB0_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *USB0_MEMORY_STANDBY_ENABLE - Usb0 memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB0_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB0_MEMORY_STANDBY_ENABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_USB0_MEMORY_STANDBY_ENABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: USB0_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB0_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB0_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *USB0_OBSERVE_CLOCK - Usb0 observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB0_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB0_OBSERVE_CLOCK_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_USB0_OBSERVE_CLOCK_reserved0_SHIFT             1
+
+/* CLKGEN :: USB0_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB0_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB0_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB0_POWER_SWITCH_MEMORY - Usb0 power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB0_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_POWER_SWITCH_MEMORY_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_USB0_POWER_SWITCH_MEMORY_reserved0_SHIFT       2
+
+/* CLKGEN :: USB0_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB0_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB0_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB0_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *USB1_CLOCK_DISABLE - Disable USB1's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB1_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_CLOCK_DISABLE_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_USB1_CLOCK_DISABLE_reserved0_SHIFT             2
+
+/* CLKGEN :: USB1_CLOCK_DISABLE :: DISABLE_USB_54_MDIO_CLOCK [01:01] */
+#define BCHP_CLKGEN_USB1_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_USB1_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB1_CLOCK_DISABLE :: DISABLE_USB1_27_FREERUN_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB1_CLOCK_DISABLE_DISABLE_USB1_27_FREERUN_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_CLOCK_DISABLE_DISABLE_USB1_27_FREERUN_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB1_CLOCK_DISABLE_DISABLE_USB1_27_FREERUN_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB1_CLOCK_ENABLE - Usb1 clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB1_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_CLOCK_ENABLE_reserved0_MASK               0xfffffffc
+#define BCHP_CLKGEN_USB1_CLOCK_ENABLE_reserved0_SHIFT              2
+
+/* CLKGEN :: USB1_CLOCK_ENABLE :: USB1_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB1_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_MASK   0x00000002
+#define BCHP_CLKGEN_USB1_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_SHIFT  1
+#define BCHP_CLKGEN_USB1_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: USB1_CLOCK_ENABLE :: USB1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB1_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_MASK   0x00000001
+#define BCHP_CLKGEN_USB1_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_SHIFT  0
+#define BCHP_CLKGEN_USB1_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *USB1_MEMORY_STANDBY_ENABLE - Usb1 memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB1_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB1_MEMORY_STANDBY_ENABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_USB1_MEMORY_STANDBY_ENABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: USB1_MEMORY_STANDBY_ENABLE :: USB1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB1_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB1_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *USB1_OBSERVE_CLOCK - Usb1 observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB1_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB1_OBSERVE_CLOCK_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_USB1_OBSERVE_CLOCK_reserved0_SHIFT             1
+
+/* CLKGEN :: USB1_OBSERVE_CLOCK :: USB1_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB1_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB1_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB1_POWER_SWITCH_MEMORY - Usb1 power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB1_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_POWER_SWITCH_MEMORY_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_USB1_POWER_SWITCH_MEMORY_reserved0_SHIFT       2
+
+/* CLKGEN :: USB1_POWER_SWITCH_MEMORY :: USB1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB1_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB1_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB1_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_CLOCK_DISABLE - Disable VEC_AIO_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_SHIFT      2
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: DISABLE_VEC_ITU656_CLOCK [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_DEFAULT 0
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_CLOCK_ENABLE - Vec aio top clock enable
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_reserved0_MASK        0xfffffff8
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_reserved0_SHIFT       3
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_AIO_ALTERNATE_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_AIO_ALTERNATE2_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_AIO_ALTERNATE2_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_AIO_ALTERNATE2_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_AIO_ALTERNATE2_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_AIO_ALTERNATE2_216_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_AIO_ALTERNATE2_216_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_AIO_ALTERNATE2_216_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_AIO_ALTERNATE2_216_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *VEC_AIO_TOP_CLOCK_ENABLE_AIO - Vec aio top clock enable aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_AIO :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_reserved0_SHIFT   2
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_AIO :: AIO_SCB_CLOCK_ENABLE_AIO [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_SCB_CLOCK_ENABLE_AIO_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_SCB_CLOCK_ENABLE_AIO_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_SCB_CLOCK_ENABLE_AIO_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_AIO :: AIO_108_CLOCK_ENABLE_AIO [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_108_CLOCK_ENABLE_AIO_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_108_CLOCK_ENABLE_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_108_CLOCK_ENABLE_AIO_DEFAULT 1
+
+/***************************************************************************
+ *VEC_AIO_TOP_CLOCK_ENABLE_VEC - Vec aio top clock enable vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC :: reserved0 [31:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_reserved0_MASK    0xfffffff0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_reserved0_SHIFT   4
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC :: VEC_SCB_CLOCK_ENABLE_VEC [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_SHIFT 3
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC :: VEC_DAC_216_CLOCK_ENABLE_VEC [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_DAC_216_CLOCK_ENABLE_VEC_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_DAC_216_CLOCK_ENABLE_VEC_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_DAC_216_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC :: VEC_216_CLOCK_ENABLE_VEC [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC :: VEC_108_CLOCK_ENABLE_VEC [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/***************************************************************************
+ *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO - Vec aio top memory standby enable aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO :: AIO_MEMORY_STANDBY_ENABLE_AIO [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC - Vec aio top memory standby enable vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC :: VEC_MEMORY_STANDBY_ENABLE_VEC [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_OBSERVE_CLOCK - Vec aio top observe clock
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_SHIFT      2
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_ENABLE_OBSERVE_CLOCK [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: AIO_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO - Vec aio top power switch memory aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO :: AIO_POWER_SWITCH_MEMORY_AIO [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC - Vec aio top power switch memory vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC :: VEC_POWER_SWITCH_MEMORY_VEC [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_DEFAULT 0
+
+#endif /* #ifndef BCHP_CLKGEN_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_common.h b/include/linux/brcmstb/7231b0/bchp_common.h
new file mode 100644
index 0000000..86ea1f1
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_common.h
@@ -0,0 +1,2192 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:00:52 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_common.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:15p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_COMMON_H__
+#define BCHP_COMMON_H__
+
+/***************************************************************************
+ *BCM7231_B0
+ ***************************************************************************/
+#define BCHP_PHYSICAL_OFFSET                               0x10000000
+#define BCHP_REGISTER_START                                0x00000000 /* DECODE_RBNODE_REGS_0 is first */
+#define BCHP_REGISTER_END                                  0x00a3f004 /* XPT_SECURE_BUS_IF is last */
+#define BCHP_REGISTER_SIZE                                 0x0028fc01 /* Number of registers */
+
+/****************************************************************************
+ * Core instance register start address.
+ ***************************************************************************/
+#define BCHP_DECODE_RBNODE_REGS_0_REG_START                0x00000000
+#define BCHP_DECODE_RBNODE_REGS_0_REG_END                  0x0000007c
+#define BCHP_DECODE_MAIN_0_REG_START                       0x00000100
+#define BCHP_DECODE_MAIN_0_REG_END                         0x000001fc
+#define BCHP_SDRAM_DEBUG_0_REG_START                       0x00000200
+#define BCHP_SDRAM_DEBUG_0_REG_END                         0x0000027c
+#define BCHP_DECODE_MCOM_0_REG_START                       0x00000300
+#define BCHP_DECODE_MCOM_0_REG_END                         0x0000031c
+#define BCHP_DECODE_SPRE_0_REG_START                       0x00000320
+#define BCHP_DECODE_SPRE_0_REG_END                         0x0000033c
+#define BCHP_DECODE_WPRD_0_REG_START                       0x00000340
+#define BCHP_DECODE_WPRD_0_REG_END                         0x0000035c
+#define BCHP_DECODE_DQNT_0_REG_START                       0x00000400
+#define BCHP_DECODE_DQNT_0_REG_END                         0x0000045c
+#define BCHP_DECODE_DQNT_8X8_0_REG_START                   0x00000500
+#define BCHP_DECODE_DQNT_8X8_0_REG_END                     0x0000057c
+#define BCHP_DECODE_VP8_XFRM_0_REG_START                   0x00000600
+#define BCHP_DECODE_VP8_XFRM_0_REG_END                     0x0000060c
+#define BCHP_DECODE_XFRM_0_REG_START                       0x00000700
+#define BCHP_DECODE_XFRM_0_REG_END                         0x0000071c
+#define BCHP_DECODE_DBLK_0_REG_START                       0x00000720
+#define BCHP_DECODE_DBLK_0_REG_END                         0x0000073c
+#define BCHP_DECODE_MB_0_REG_START                         0x00000740
+#define BCHP_DECODE_MB_0_REG_END                           0x0000075c
+#define BCHP_REG_CABAC2BINS_0_REG_START                    0x00000b00
+#define BCHP_REG_CABAC2BINS_0_REG_END                      0x00000bfc
+#define BCHP_DECODE_SINT_0_REG_START                       0x00000c00
+#define BCHP_DECODE_SINT_0_REG_END                         0x00000dfc
+#define BCHP_DECODE_RVC_0_REG_START                        0x00000e00
+#define BCHP_DECODE_RVC_0_REG_END                          0x00000efc
+#define BCHP_DECODE_CPUREGS_0_REG_START                    0x00000f00
+#define BCHP_DECODE_CPUREGS_0_REG_END                      0x00000f7c
+#define BCHP_DECODE_CPUREGS2_0_REG_START                   0x00000f80
+#define BCHP_DECODE_CPUREGS2_0_REG_END                     0x00000ffc
+#define BCHP_DECODE_CPUDMA_0_REG_START                     0x00001800
+#define BCHP_DECODE_CPUDMA_0_REG_END                       0x000018fc
+#define BCHP_DECODE_DMAMEM_0_REG_START                     0x00001a00
+#define BCHP_DECODE_DMAMEM_0_REG_END                       0x000021fc
+#define BCHP_REG_CABAC2BINS2_0_REG_START                   0x00002400
+#define BCHP_REG_CABAC2BINS2_0_REG_END                     0x000027fc
+#define BCHP_DECODE_WPTBL_0_REG_START                      0x00003000
+#define BCHP_DECODE_WPTBL_0_REG_END                        0x000031fc
+#define BCHP_DECODE_SINT_OLOOP_0_REG_START                 0x0000cc00
+#define BCHP_DECODE_SINT_OLOOP_0_REG_END                   0x0000ccfc
+#define BCHP_DECODE_SD_0_REG_START                         0x00040800
+#define BCHP_DECODE_SD_0_REG_END                           0x00040ffc
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_START             0x00041000
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_END               0x0004107c
+#define BCHP_DECODE_CPUCORE_0_REG_START                    0x00044000
+#define BCHP_DECODE_CPUCORE_0_REG_END                      0x00044ffc
+#define BCHP_DECODE_CPUAUX_0_REG_START                     0x00045000
+#define BCHP_DECODE_CPUAUX_0_REG_END                       0x00045ffc
+#define BCHP_DECODE_CPUIMEM_0_REG_START                    0x00046000
+#define BCHP_DECODE_CPUIMEM_0_REG_END                      0x00047ffc
+#define BCHP_DECODE_CPUDMEM_0_REG_START                    0x00048000
+#define BCHP_DECODE_CPUDMEM_0_REG_END                      0x0004fffc
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_START            0x00051000
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_END              0x0005107c
+#define BCHP_DECODE_CPUDMA2_0_REG_START                    0x00051800
+#define BCHP_DECODE_CPUDMA2_0_REG_END                      0x000518fc
+#define BCHP_DECODE_DMAMEM2_0_REG_START                    0x00051a00
+#define BCHP_DECODE_DMAMEM2_0_REG_END                      0x000521fc
+#define BCHP_DECODE_CPUCORE2_0_REG_START                   0x00054000
+#define BCHP_DECODE_CPUCORE2_0_REG_END                     0x00054ffc
+#define BCHP_DECODE_CPUAUX2_0_REG_START                    0x00055000
+#define BCHP_DECODE_CPUAUX2_0_REG_END                      0x00055ffc
+#define BCHP_DECODE_CPUIMEM2_0_REG_START                   0x00056000
+#define BCHP_DECODE_CPUIMEM2_0_REG_END                     0x00057ffc
+#define BCHP_DECODE_CPUDMEM2_0_REG_START                   0x00058000
+#define BCHP_DECODE_CPUDMEM2_0_REG_END                     0x0005fffc
+#define BCHP_DECODE_IP_SHIM_0_REG_START                    0x00060000
+#define BCHP_DECODE_IP_SHIM_0_REG_END                      0x00060084
+#define BCHP_AVD_CACHE_0_REG_START                         0x00062000
+#define BCHP_AVD_CACHE_0_REG_END                           0x0006203c
+#define BCHP_ILS_REGS_0_REG_START                          0x00070000
+#define BCHP_ILS_REGS_0_REG_END                            0x0007007c
+#define BCHP_ILS_SCALE_ADDR_0_REG_START                    0x00070100
+#define BCHP_ILS_SCALE_ADDR_0_REG_END                      0x0007010c
+#define BCHP_ILS_SPSCALE_FILL_0_REG_START                  0x00070180
+#define BCHP_ILS_SPSCALE_FILL_0_REG_END                    0x00070180
+#define BCHP_ILS_MVSCALE_0_REG_START                       0x00070200
+#define BCHP_ILS_MVSCALE_0_REG_END                         0x0007038c
+#define BCHP_SVD_INTR2_0_REG_START                         0x00080000
+#define BCHP_SVD_INTR2_0_REG_END                           0x0008002c
+#define BCHP_SVD_RGR_0_REG_START                           0x00080400
+#define BCHP_SVD_RGR_0_REG_END                             0x00080410
+#define BCHP_BLD_DECODE_RBNODE_REGS_0_REG_START            0x00100000
+#define BCHP_BLD_DECODE_RBNODE_REGS_0_REG_END              0x0010007c
+#define BCHP_BLD_DECODE_MAIN_0_REG_START                   0x00100100
+#define BCHP_BLD_DECODE_MAIN_0_REG_END                     0x001001fc
+#define BCHP_BLD_SDRAM_DEBUG_0_REG_START                   0x00100200
+#define BCHP_BLD_SDRAM_DEBUG_0_REG_END                     0x0010027c
+#define BCHP_BLD_DECODE_MCOM_0_REG_START                   0x00100300
+#define BCHP_BLD_DECODE_MCOM_0_REG_END                     0x0010031c
+#define BCHP_BLD_DECODE_SPRE_0_REG_START                   0x00100320
+#define BCHP_BLD_DECODE_SPRE_0_REG_END                     0x0010033c
+#define BCHP_BLD_DECODE_WPRD_0_REG_START                   0x00100340
+#define BCHP_BLD_DECODE_WPRD_0_REG_END                     0x0010035c
+#define BCHP_BLD_DECODE_DQNT_0_REG_START                   0x00100400
+#define BCHP_BLD_DECODE_DQNT_0_REG_END                     0x0010045c
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_START               0x00100500
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_END                 0x0010057c
+#define BCHP_BLD_DECODE_VP8_XFRM_0_REG_START               0x00100600
+#define BCHP_BLD_DECODE_VP8_XFRM_0_REG_END                 0x0010060c
+#define BCHP_BLD_DECODE_XFRM_0_REG_START                   0x00100700
+#define BCHP_BLD_DECODE_XFRM_0_REG_END                     0x0010071c
+#define BCHP_BLD_DECODE_DBLK_0_REG_START                   0x00100720
+#define BCHP_BLD_DECODE_DBLK_0_REG_END                     0x0010073c
+#define BCHP_BLD_DECODE_MB_0_REG_START                     0x00100740
+#define BCHP_BLD_DECODE_MB_0_REG_END                       0x0010075c
+#define BCHP_BLD_REG_CABAC2BINS_0_REG_START                0x00100b00
+#define BCHP_BLD_REG_CABAC2BINS_0_REG_END                  0x00100bfc
+#define BCHP_BLD_DECODE_SINT_0_REG_START                   0x00100c00
+#define BCHP_BLD_DECODE_SINT_0_REG_END                     0x00100dfc
+#define BCHP_BLD_DECODE_RVC_0_REG_START                    0x00100e00
+#define BCHP_BLD_DECODE_RVC_0_REG_END                      0x00100efc
+#define BCHP_BLD_DECODE_CPUREGS_0_REG_START                0x00100f00
+#define BCHP_BLD_DECODE_CPUREGS_0_REG_END                  0x00100f7c
+#define BCHP_BLD_DECODE_CPUREGS2_0_REG_START               0x00100f80
+#define BCHP_BLD_DECODE_CPUREGS2_0_REG_END                 0x00100ffc
+#define BCHP_BLD_DECODE_CPUDMA_0_REG_START                 0x00101800
+#define BCHP_BLD_DECODE_CPUDMA_0_REG_END                   0x001018fc
+#define BCHP_BLD_DECODE_DMAMEM_0_REG_START                 0x00101a00
+#define BCHP_BLD_DECODE_DMAMEM_0_REG_END                   0x001021fc
+#define BCHP_BLD_REG_CABAC2BINS2_0_REG_START               0x00102400
+#define BCHP_BLD_REG_CABAC2BINS2_0_REG_END                 0x001027fc
+#define BCHP_BLD_DECODE_WPTBL_0_REG_START                  0x00103000
+#define BCHP_BLD_DECODE_WPTBL_0_REG_END                    0x001031fc
+#define BCHP_BLD_DECODE_SINT_OLOOP_0_REG_START             0x0010cc00
+#define BCHP_BLD_DECODE_SINT_OLOOP_0_REG_END               0x0010ccfc
+#define BCHP_BLD_DECODE_SD_0_REG_START                     0x00140800
+#define BCHP_BLD_DECODE_SD_0_REG_END                       0x00140ffc
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS_0_REG_START         0x00141000
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS_0_REG_END           0x0014107c
+#define BCHP_BLD_DECODE_CPUCORE_0_REG_START                0x00144000
+#define BCHP_BLD_DECODE_CPUCORE_0_REG_END                  0x00144ffc
+#define BCHP_BLD_DECODE_CPUAUX_0_REG_START                 0x00145000
+#define BCHP_BLD_DECODE_CPUAUX_0_REG_END                   0x00145ffc
+#define BCHP_BLD_DECODE_CPUIMEM_0_REG_START                0x00146000
+#define BCHP_BLD_DECODE_CPUIMEM_0_REG_END                  0x00147ffc
+#define BCHP_BLD_DECODE_CPUDMEM_0_REG_START                0x00148000
+#define BCHP_BLD_DECODE_CPUDMEM_0_REG_END                  0x0014fffc
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS2_0_REG_START        0x00151000
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS2_0_REG_END          0x0015107c
+#define BCHP_BLD_DECODE_CPUDMA2_0_REG_START                0x00151800
+#define BCHP_BLD_DECODE_CPUDMA2_0_REG_END                  0x001518fc
+#define BCHP_BLD_DECODE_DMAMEM2_0_REG_START                0x00151a00
+#define BCHP_BLD_DECODE_DMAMEM2_0_REG_END                  0x001521fc
+#define BCHP_BLD_DECODE_CPUCORE2_0_REG_START               0x00154000
+#define BCHP_BLD_DECODE_CPUCORE2_0_REG_END                 0x00154ffc
+#define BCHP_BLD_DECODE_CPUAUX2_0_REG_START                0x00155000
+#define BCHP_BLD_DECODE_CPUAUX2_0_REG_END                  0x00155ffc
+#define BCHP_BLD_DECODE_CPUIMEM2_0_REG_START               0x00156000
+#define BCHP_BLD_DECODE_CPUIMEM2_0_REG_END                 0x00157ffc
+#define BCHP_BLD_DECODE_CPUDMEM2_0_REG_START               0x00158000
+#define BCHP_BLD_DECODE_CPUDMEM2_0_REG_END                 0x0015fffc
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_START                0x00160000
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_END                  0x00160084
+#define BCHP_BLD_AVD_CACHE_0_REG_START                     0x00162000
+#define BCHP_BLD_AVD_CACHE_0_REG_END                       0x0016203c
+#define BCHP_VICH_0_REG_START                              0x00170000
+#define BCHP_VICH_0_REG_END                                0x0017008b
+#define BCHP_SATA_GRB_REG_START                            0x00180000
+#define BCHP_SATA_GRB_REG_END                              0x0018000c
+#define BCHP_SATA_TOP_CTRL_REG_START                       0x00180020
+#define BCHP_SATA_TOP_CTRL_REG_END                         0x00180038
+#define BCHP_SATA3_INTR2_REG_START                         0x00180080
+#define BCHP_SATA3_INTR2_REG_END                           0x001800ac
+#define BCHP_SATA_AHCI_GHC_REG_START                       0x00181000
+#define BCHP_SATA_AHCI_GHC_REG_END                         0x00181028
+#define BCHP_SATA_GLOBAL_RESERVED_REG_START                0x0018102c
+#define BCHP_SATA_GLOBAL_RESERVED_REG_END                  0x0018109c
+#define BCHP_SATA_PORT0_AHCI_S1_REG_START                  0x00181100
+#define BCHP_SATA_PORT0_AHCI_S1_REG_END                    0x0018111c
+#define BCHP_SATA_PORT0_AHCI_S2_REG_START                  0x00181120
+#define BCHP_SATA_PORT0_AHCI_S2_REG_END                    0x00181134
+#define BCHP_SATA_PORT0_AHCI_S3_REG_START                  0x00181138
+#define BCHP_SATA_PORT0_AHCI_S3_REG_END                    0x0018117c
+#define BCHP_SATA_PORT1_AHCI_S1_REG_START                  0x00181180
+#define BCHP_SATA_PORT1_AHCI_S1_REG_END                    0x0018119c
+#define BCHP_SATA_PORT1_AHCI_S2_REG_START                  0x001811a0
+#define BCHP_SATA_PORT1_AHCI_S2_REG_END                    0x001811b4
+#define BCHP_SATA_PORT1_AHCI_S3_REG_START                  0x001811b8
+#define BCHP_SATA_PORT1_AHCI_S3_REG_END                    0x001811fc
+#define BCHP_SATA_AHCI_PCICFG_REG_START                    0x00181600
+#define BCHP_SATA_AHCI_PCICFG_REG_END                      0x00181664
+#define BCHP_SATA_PORT0_CTRL_REG_START                     0x00181700
+#define BCHP_SATA_PORT0_CTRL_REG_END                       0x00181730
+#define BCHP_SATA_PORT0_CJPAT_REG_START                    0x00181740
+#define BCHP_SATA_PORT0_CJPAT_REG_END                      0x00181764
+#define BCHP_SATA_PORT1_CTRL_REG_START                     0x00181780
+#define BCHP_SATA_PORT1_CTRL_REG_END                       0x001817b0
+#define BCHP_SATA_PORT1_CJPAT_REG_START                    0x001817c0
+#define BCHP_SATA_PORT1_CJPAT_REG_END                      0x001817e4
+#define BCHP_SATA_LEG_PCICFG_REG_START                     0x00181800
+#define BCHP_SATA_LEG_PCICFG_REG_END                       0x00181880
+#define BCHP_SATA_PORT0_LEG_S1_REG_START                   0x00181900
+#define BCHP_SATA_PORT0_LEG_S1_REG_END                     0x00181934
+#define BCHP_SATA_PORT0_LEG_S2_REG_START                   0x00181940
+#define BCHP_SATA_PORT0_LEG_S2_REG_END                     0x00181954
+#define BCHP_SATA_PORT0_LEG_S3_REG_START                   0x00181958
+#define BCHP_SATA_PORT0_LEG_S3_REG_END                     0x00181998
+#define BCHP_SATA_PORT1_LEG_S1_REG_START                   0x00181a00
+#define BCHP_SATA_PORT1_LEG_S1_REG_END                     0x00181a34
+#define BCHP_SATA_PORT1_LEG_S2_REG_START                   0x00181a40
+#define BCHP_SATA_PORT1_LEG_S2_REG_END                     0x00181a54
+#define BCHP_SATA_PORT1_LEG_S3_REG_START                   0x00181a58
+#define BCHP_SATA_PORT1_LEG_S3_REG_END                     0x00181a98
+#define BCHP_BSP_CMDBUF_REG_START                          0x00329800
+#define BCHP_BSP_CMDBUF_REG_END                            0x00329ffc
+#define BCHP_BSP_GLB_CONTROL_REG_START                     0x0032b000
+#define BCHP_BSP_GLB_CONTROL_REG_END                       0x0032b098
+#define BCHP_BSP_PKL_REG_START                             0x0032b300
+#define BCHP_BSP_PKL_REG_END                               0x0032b37c
+#define BCHP_BSP_INST_PATCH_CTRL_REG_START                 0x0032b400
+#define BCHP_BSP_INST_PATCH_CTRL_REG_END                   0x0032b404
+#define BCHP_BSP_CONTROL_INTR2_REG_START                   0x0032b800
+#define BCHP_BSP_CONTROL_INTR2_REG_END                     0x0032b82c
+#define BCHP_BSP_INST_PATCHRAM_REG_START                   0x0032c000
+#define BCHP_BSP_INST_PATCHRAM_REG_END                     0x0032fffc
+#define BCHP_XPT_SECURITY_REG_START                        0x00360000
+#define BCHP_XPT_SECURITY_REG_END                          0x0036fffc
+#define BCHP_MMSCRAM_REG_START                             0x00370000
+#define BCHP_MMSCRAM_REG_END                               0x00371ffc
+#define BCHP_MEM_DMA_SECURE_REG_START                      0x00372000
+#define BCHP_MEM_DMA_SECURE_REG_END                        0x0037200c
+#define BCHP_SECTOP_GRB_REG_START                          0x00374000
+#define BCHP_SECTOP_GRB_REG_END                            0x0037400c
+#define BCHP_JTAG_OTP_REG_START                            0x00374100
+#define BCHP_JTAG_OTP_REG_END                              0x00374138
+#define BCHP_MEM_DMA_0_REG_START                           0x00374200
+#define BCHP_MEM_DMA_0_REG_END                             0x00374224
+#define BCHP_XPT_SECURITY_NS_REG_START                     0x00374300
+#define BCHP_XPT_SECURITY_NS_REG_END                       0x00374310
+#define BCHP_MEMC_GEN_0_REG_START                          0x003b0000
+#define BCHP_MEMC_GEN_0_REG_END                            0x003b04f4
+#define BCHP_MEMC_ARB_0_REG_START                          0x003b1000
+#define BCHP_MEMC_ARB_0_REG_END                            0x003b1244
+#define BCHP_MEMC_DDR_0_REG_START                          0x003b2000
+#define BCHP_MEMC_DDR_0_REG_END                            0x003b22fc
+#define BCHP_MEMC_L2_0_REG_START                           0x003b3000
+#define BCHP_MEMC_L2_0_REG_END                             0x003b302c
+#define BCHP_MEMC_L2_1_0_REG_START                         0x003b3800
+#define BCHP_MEMC_L2_1_0_REG_END                           0x003b382c
+#define BCHP_MEMC_RGRB_0_REG_START                         0x003b4000
+#define BCHP_MEMC_RGRB_0_REG_END                           0x003b4010
+#define BCHP_MEMC_MISC_0_REG_START                         0x003b5000
+#define BCHP_MEMC_MISC_0_REG_END                           0x003b5010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_START            0x003b6000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_END              0x003b60c4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_START             0x003b6200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_END               0x003b63b0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_REG_START             0x003b6400
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_REG_END               0x003b65b0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_START         0x003b8000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_END           0x003b8138
+#define BCHP_S_MEMC_0_REG_START                            0x003ba000
+#define BCHP_S_MEMC_0_REG_END                              0x003ba220
+#define BCHP_SUN_GISB_ARB_REG_START                        0x00400000
+#define BCHP_SUN_GISB_ARB_REG_END                          0x004000d8
+#define BCHP_SUN_RGR_REG_START                             0x00400400
+#define BCHP_SUN_RGR_REG_END                               0x00400410
+#define BCHP_SUN_RG_REG_START                              0x00400800
+#define BCHP_SUN_RG_REG_END                                0x0040080c
+#define BCHP_SUN_L2_REG_START                              0x00403000
+#define BCHP_SUN_L2_REG_END                                0x0040302c
+#define BCHP_SM_L2_REG_START                               0x00403400
+#define BCHP_SM_L2_REG_END                                 0x0040342c
+#define BCHP_SM_REG_START                                  0x00403800
+#define BCHP_SM_REG_END                                    0x00403824
+#define BCHP_SM_FAST_REG_START                             0x00403c00
+#define BCHP_SM_FAST_REG_END                               0x00403c18
+#define BCHP_SUN_TOP_CTRL_REG_START                        0x00404000
+#define BCHP_SUN_TOP_CTRL_REG_END                          0x00404518
+#define BCHP_IRB_REG_START                                 0x00406000
+#define BCHP_IRB_REG_END                                   0x00406138
+#define BCHP_PM_REG_START                                  0x00406180
+#define BCHP_PM_REG_END                                    0x00406188
+#define BCHP_BSCA_REG_START                                0x00406200
+#define BCHP_BSCA_REG_END                                  0x00406254
+#define BCHP_BSCB_REG_START                                0x00406280
+#define BCHP_BSCB_REG_END                                  0x004062d4
+#define BCHP_BSCC_REG_START                                0x00406300
+#define BCHP_BSCC_REG_END                                  0x00406354
+#define BCHP_PWM_REG_START                                 0x00406580
+#define BCHP_PWM_REG_END                                   0x004065a4
+#define BCHP_PWMB_REG_START                                0x004065c0
+#define BCHP_PWMB_REG_END                                  0x004065e4
+#define BCHP_GIO_REG_START                                 0x00406600
+#define BCHP_GIO_REG_END                                   0x0040669c
+#define BCHP_IRQ0_REG_START                                0x00406780
+#define BCHP_IRQ0_REG_END                                  0x00406784
+#define BCHP_IRQ1_REG_START                                0x00406788
+#define BCHP_IRQ1_REG_END                                  0x0040678c
+#define BCHP_TIMER_REG_START                               0x004067c0
+#define BCHP_TIMER_REG_END                                 0x004067fc
+#define BCHP_UARTA_REG_START                               0x00406900
+#define BCHP_UARTA_REG_END                                 0x0040691c
+#define BCHP_UARTB_REG_START                               0x00406940
+#define BCHP_UARTB_REG_END                                 0x0040695c
+#define BCHP_UARTC_REG_START                               0x00406980
+#define BCHP_UARTC_REG_END                                 0x0040699c
+#define BCHP_SCA_REG_START                                 0x00406a00
+#define BCHP_SCA_REG_END                                   0x00406abc
+#define BCHP_SCB_REG_START                                 0x00406ac0
+#define BCHP_SCB_REG_END                                   0x00406b7c
+#define BCHP_SCIRQ0_REG_START                              0x00406c40
+#define BCHP_SCIRQ0_REG_END                                0x00406c44
+#define BCHP_SCIRQ1_REG_START                              0x00406c48
+#define BCHP_SCIRQ1_REG_END                                0x00406c4c
+#define BCHP_MCIF_REG_START                                0x00406d00
+#define BCHP_MCIF_REG_END                                  0x00406d20
+#define BCHP_MCIF_INTR2_REG_START                          0x00406d40
+#define BCHP_MCIF_INTR2_REG_END                            0x00406d6c
+#define BCHP_TMON_REG_START                                0x00406d80
+#define BCHP_TMON_REG_END                                  0x00406dd0
+#define BCHP_UPG_AUX_INTR2_REG_START                       0x00406e00
+#define BCHP_UPG_AUX_INTR2_REG_END                         0x00406e2c
+#define BCHP_AON_CTRL_REG_START                            0x00408000
+#define BCHP_AON_CTRL_REG_END                              0x004083fc
+#define BCHP_AON_L2_REG_START                              0x00408400
+#define BCHP_AON_L2_REG_END                                0x0040842c
+#define BCHP_AON_PM_L2_REG_START                           0x00408440
+#define BCHP_AON_PM_L2_REG_END                             0x0040846c
+#define BCHP_AON_PIN_CTRL_REG_START                        0x00408500
+#define BCHP_AON_PIN_CTRL_REG_END                          0x00408518
+#define BCHP_AON_HDMI_TX_REG_START                         0x00408600
+#define BCHP_AON_HDMI_TX_REG_END                           0x00408698
+#define BCHP_LDK_REG_START                                 0x00408800
+#define BCHP_LDK_REG_END                                   0x0040883c
+#define BCHP_PM_AON_REG_START                              0x00408840
+#define BCHP_PM_AON_REG_END                                0x00408848
+#define BCHP_ICAP_REG_START                                0x00408880
+#define BCHP_ICAP_REG_END                                  0x004088bc
+#define BCHP_KBD1_REG_START                                0x004088c0
+#define BCHP_KBD1_REG_END                                  0x004088fc
+#define BCHP_KBD2_REG_START                                0x00408900
+#define BCHP_KBD2_REG_END                                  0x0040893c
+#define BCHP_KBD3_REG_START                                0x00408940
+#define BCHP_KBD3_REG_END                                  0x0040897c
+#define BCHP_BSCD_REG_START                                0x00408980
+#define BCHP_BSCD_REG_END                                  0x004089d4
+#define BCHP_MSPI_REG_START                                0x00408a00
+#define BCHP_MSPI_REG_END                                  0x00408b7c
+#define BCHP_IRQ0_AON_REG_START                            0x00408b80
+#define BCHP_IRQ0_AON_REG_END                              0x00408b84
+#define BCHP_IRQ1_AON_REG_START                            0x00408b88
+#define BCHP_IRQ1_AON_REG_END                              0x00408b8c
+#define BCHP_GIO_AON_REG_START                             0x00408c00
+#define BCHP_GIO_AON_REG_END                               0x00408c5c
+#define BCHP_BICAP_REG_START                               0x00408e00
+#define BCHP_BICAP_REG_END                                 0x00408e38
+#define BCHP_UPG_AUX_AON_INTR2_REG_START                   0x00408e40
+#define BCHP_UPG_AUX_AON_INTR2_REG_END                     0x00408e6c
+#define BCHP_WKTMR_REG_START                               0x00408e80
+#define BCHP_WKTMR_REG_END                                 0x00408e90
+#define BCHP_SYS_GISB_ARB_SEC_REG_START                    0x0040e000
+#define BCHP_SYS_GISB_ARB_SEC_REG_END                      0x0040e0b4
+#define BCHP_SYS_TOP_CTRL_SEC_REG_START                    0x0040e700
+#define BCHP_SYS_TOP_CTRL_SEC_REG_END                      0x0040e704
+#define BCHP_AON_CTRL_SECURE_REG_START                     0x0040e800
+#define BCHP_AON_CTRL_SECURE_REG_END                       0x0040e87c
+#define BCHP_SDIO_0_HOST_REG_START                         0x00410000
+#define BCHP_SDIO_0_HOST_REG_END                           0x004100fc
+#define BCHP_SDIO_0_CFG_REG_START                          0x00410100
+#define BCHP_SDIO_0_CFG_REG_END                            0x004101fc
+#define BCHP_MISB_BRIDGE_REG_START                         0x00410400
+#define BCHP_MISB_BRIDGE_REG_END                           0x00410408
+#define BCHP_EBI_REG_START                                 0x00410800
+#define BCHP_EBI_REG_END                                   0x00410bfc
+#define BCHP_HIF_INTR2_REG_START                           0x00411000
+#define BCHP_HIF_INTR2_REG_END                             0x0041102c
+#define BCHP_IPI0_INTR2_REG_START                          0x00411100
+#define BCHP_IPI0_INTR2_REG_END                            0x0041112c
+#define BCHP_IPI1_INTR2_REG_START                          0x00411200
+#define BCHP_IPI1_INTR2_REG_END                            0x0041122c
+#define BCHP_HIF_CPU_INTR1_REG_START                       0x00411400
+#define BCHP_HIF_CPU_INTR1_REG_END                         0x0041142c
+#define BCHP_HIF_CPU_TP1_INTR1_REG_START                   0x00411600
+#define BCHP_HIF_CPU_TP1_INTR1_REG_END                     0x0041162c
+#define BCHP_HIF_RGR_REG_START                             0x00411800
+#define BCHP_HIF_RGR_REG_END                               0x00411810
+#define BCHP_HIF_SPI_INTR2_REG_START                       0x00411d00
+#define BCHP_HIF_SPI_INTR2_REG_END                         0x00411d2c
+#define BCHP_HIF_TOP_CTRL_REG_START                        0x00412400
+#define BCHP_HIF_TOP_CTRL_REG_END                          0x0041241c
+#define BCHP_NAND_REG_START                                0x00412800
+#define BCHP_NAND_REG_END                                  0x00412bfc
+#define BCHP_BSPI_REG_START                                0x00413000
+#define BCHP_BSPI_REG_END                                  0x0041304c
+#define BCHP_BSPI_RAF_REG_START                            0x00413100
+#define BCHP_BSPI_RAF_REG_END                              0x00413120
+#define BCHP_HIF_MSPI_REG_START                            0x00413200
+#define BCHP_HIF_MSPI_REG_END                              0x00413384
+#define BCHP_MICH_REG_START                                0x00414000
+#define BCHP_MICH_REG_END                                  0x00414000
+#define BCHP_HIF_SECURE_CTRL_REG_START                     0x00414100
+#define BCHP_HIF_SECURE_CTRL_REG_END                       0x00414100
+#define BCHP_HIF_SECURE_BSPI_REG_START                     0x00414200
+#define BCHP_HIF_SECURE_BSPI_REG_END                       0x00414200
+#define BCHP_HIF_SECURE_LR_SPI_REG_START                   0x00414300
+#define BCHP_HIF_SECURE_LR_SPI_REG_END                     0x00414300
+#define BCHP_NAND_SECURE_REG_START                         0x00414400
+#define BCHP_NAND_SECURE_REG_END                           0x00414400
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_START        0x00414800
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_END          0x00414800
+#define BCHP_CLKGEN_REG_START                              0x00420000
+#define BCHP_CLKGEN_REG_END                                0x0042036c
+#define BCHP_VCXO_RM_REG_START                             0x00422800
+#define BCHP_VCXO_RM_REG_END                               0x0042282c
+#define BCHP_AVS_HW_MNTR_REG_START                         0x00423000
+#define BCHP_AVS_HW_MNTR_REG_END                           0x00423074
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_START                 0x00423100
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_END                   0x0042311c
+#define BCHP_AVS_ASB_REGISTERS_REG_START                   0x00423200
+#define BCHP_AVS_ASB_REGISTERS_REG_END                     0x00423218
+#define BCHP_AVS_RO_REGISTERS_0_REG_START                  0x00423300
+#define BCHP_AVS_RO_REGISTERS_0_REG_END                    0x004233dc
+#define BCHP_AVS_RO_REGISTERS_1_REG_START                  0x00423400
+#define BCHP_AVS_RO_REGISTERS_1_REG_END                    0x0042347c
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_START                0x00423500
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_END                  0x004235e4
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_START                0x00423600
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_END                  0x004236e4
+#define BCHP_CLKGEN_INTR2_REG_START                        0x00424000
+#define BCHP_CLKGEN_INTR2_REG_END                          0x0042402c
+#define BCHP_CLKGEN_GR_REG_START                           0x00424800
+#define BCHP_CLKGEN_GR_REG_END                             0x0042480c
+#define BCHP_GENET_0_SYS_REG_START                         0x00430000
+#define BCHP_GENET_0_SYS_REG_END                           0x0043000c
+#define BCHP_GENET_0_GR_BRIDGE_REG_START                   0x00430040
+#define BCHP_GENET_0_GR_BRIDGE_REG_END                     0x0043004c
+#define BCHP_GENET_0_EXT_REG_START                         0x00430080
+#define BCHP_GENET_0_EXT_REG_END                           0x00430098
+#define BCHP_GENET_0_INTRL2_0_REG_START                    0x00430200
+#define BCHP_GENET_0_INTRL2_0_REG_END                      0x0043022c
+#define BCHP_GENET_0_INTRL2_1_REG_START                    0x00430240
+#define BCHP_GENET_0_INTRL2_1_REG_END                      0x0043026c
+#define BCHP_GENET_0_RBUF_REG_START                        0x00430300
+#define BCHP_GENET_0_RBUF_REG_END                          0x004303ec
+#define BCHP_GENET_0_TBUF_REG_START                        0x00430600
+#define BCHP_GENET_0_TBUF_REG_END                          0x00430628
+#define BCHP_GENET_0_UMAC_REG_START                        0x00430800
+#define BCHP_GENET_0_UMAC_REG_END                          0x00430ed8
+#define BCHP_GENET_0_HFB_REG_START                         0x00431000
+#define BCHP_GENET_0_HFB_REG_END                           0x00432010
+#define BCHP_GENET_0_RDMA_REG_START                        0x00433000
+#define BCHP_GENET_0_RDMA_REG_END                          0x00433cb4
+#define BCHP_GENET_0_TDMA_REG_START                        0x00434000
+#define BCHP_GENET_0_TDMA_REG_END                          0x00434c88
+#define BCHP_GENET_1_SYS_REG_START                         0x00440000
+#define BCHP_GENET_1_SYS_REG_END                           0x0044000c
+#define BCHP_GENET_1_GR_BRIDGE_REG_START                   0x00440040
+#define BCHP_GENET_1_GR_BRIDGE_REG_END                     0x0044004c
+#define BCHP_GENET_1_EXT_REG_START                         0x00440080
+#define BCHP_GENET_1_EXT_REG_END                           0x00440098
+#define BCHP_GENET_1_INTRL2_0_REG_START                    0x00440200
+#define BCHP_GENET_1_INTRL2_0_REG_END                      0x0044022c
+#define BCHP_GENET_1_INTRL2_1_REG_START                    0x00440240
+#define BCHP_GENET_1_INTRL2_1_REG_END                      0x0044026c
+#define BCHP_GENET_1_RBUF_REG_START                        0x00440300
+#define BCHP_GENET_1_RBUF_REG_END                          0x004403ec
+#define BCHP_GENET_1_TBUF_REG_START                        0x00440600
+#define BCHP_GENET_1_TBUF_REG_END                          0x00440628
+#define BCHP_GENET_1_UMAC_REG_START                        0x00440800
+#define BCHP_GENET_1_UMAC_REG_END                          0x00440ed8
+#define BCHP_GENET_1_HFB_REG_START                         0x00441000
+#define BCHP_GENET_1_HFB_REG_END                           0x00442010
+#define BCHP_GENET_1_RDMA_REG_START                        0x00443000
+#define BCHP_GENET_1_RDMA_REG_END                          0x00443cb4
+#define BCHP_GENET_1_TDMA_REG_START                        0x00444000
+#define BCHP_GENET_1_TDMA_REG_END                          0x00444c88
+#define BCHP_M2MC_REG_START                                0x00450000
+#define BCHP_M2MC_REG_END                                  0x004507fc
+#define BCHP_V3D_CTL_REG_START                             0x00451000
+#define BCHP_V3D_CTL_REG_END                               0x00451040
+#define BCHP_V3D_CLE_REG_START                             0x00451100
+#define BCHP_V3D_CLE_REG_END                               0x00451138
+#define BCHP_V3D_PTB_REG_START                             0x00451300
+#define BCHP_V3D_PTB_REG_END                               0x00451310
+#define BCHP_V3D_QPS_REG_START                             0x00451400
+#define BCHP_V3D_QPS_REG_END                               0x0045143c
+#define BCHP_V3D_VPM_REG_START                             0x00451500
+#define BCHP_V3D_VPM_REG_END                               0x00451504
+#define BCHP_V3D_PCTR_REG_START                            0x00451600
+#define BCHP_V3D_PCTR_REG_END                              0x004516fc
+#define BCHP_V3D_GCA_REG_START                             0x00451a00
+#define BCHP_V3D_GCA_REG_END                               0x00451a54
+#define BCHP_V3D_DBG_REG_START                             0x00451e00
+#define BCHP_V3D_DBG_REG_END                               0x00451f20
+#define BCHP_GFX_L2_REG_START                              0x00453000
+#define BCHP_GFX_L2_REG_END                                0x0045302c
+#define BCHP_GFX_GR_REG_START                              0x00454000
+#define BCHP_GFX_GR_REG_END                                0x0045400c
+#define BCHP_USB_CAPS_REG_START                            0x00480000
+#define BCHP_USB_CAPS_REG_END                              0x0048002c
+#define BCHP_USB_GR_BRIDGE_REG_START                       0x00480100
+#define BCHP_USB_GR_BRIDGE_REG_END                         0x0048010c
+#define BCHP_USB_INTR2_REG_START                           0x00480180
+#define BCHP_USB_INTR2_REG_END                             0x004801ac
+#define BCHP_USB_CTRL_REG_START                            0x00480200
+#define BCHP_USB_CTRL_REG_END                              0x00480238
+#define BCHP_USB_EHCI_REG_START                            0x00480300
+#define BCHP_USB_EHCI_REG_END                              0x004803a4
+#define BCHP_USB_OHCI_REG_START                            0x00480400
+#define BCHP_USB_OHCI_REG_END                              0x00480454
+#define BCHP_USB_EHCI1_REG_START                           0x00480500
+#define BCHP_USB_EHCI1_REG_END                             0x004805a4
+#define BCHP_USB_OHCI1_REG_START                           0x00480600
+#define BCHP_USB_OHCI1_REG_END                             0x00480654
+#define BCHP_USB_OTG_REG_START                             0x00482000
+#define BCHP_USB_OTG_REG_END                               0x00482e00
+#define BCHP_USB1_CAPS_REG_START                           0x00490000
+#define BCHP_USB1_CAPS_REG_END                             0x0049002c
+#define BCHP_USB1_GR_BRIDGE_REG_START                      0x00490100
+#define BCHP_USB1_GR_BRIDGE_REG_END                        0x0049010c
+#define BCHP_USB1_INTR2_REG_START                          0x00490180
+#define BCHP_USB1_INTR2_REG_END                            0x004901ac
+#define BCHP_USB1_CTRL_REG_START                           0x00490200
+#define BCHP_USB1_CTRL_REG_END                             0x00490238
+#define BCHP_USB1_EHCI_REG_START                           0x00490300
+#define BCHP_USB1_EHCI_REG_END                             0x004903a4
+#define BCHP_USB1_OHCI_REG_START                           0x00490400
+#define BCHP_USB1_OHCI_REG_END                             0x00490454
+#define BCHP_USB1_EHCI1_REG_START                          0x00490500
+#define BCHP_USB1_EHCI1_REG_END                            0x004905a4
+#define BCHP_USB1_OHCI1_REG_START                          0x00490600
+#define BCHP_USB1_OHCI1_REG_END                            0x00490654
+#define BCHP_USB1_OTG_REG_START                            0x00492000
+#define BCHP_USB1_OTG_REG_END                              0x00492e00
+#define BCHP_BOOTROM_REG_START                             0x00500000
+#define BCHP_BOOTROM_REG_END                               0x00500ffc
+#define BCHP_SID_REG_START                                 0x00540100
+#define BCHP_SID_REG_END                                   0x0054019c
+#define BCHP_SID_RLE_REG_START                             0x00540300
+#define BCHP_SID_RLE_REG_END                               0x0054039c
+#define BCHP_SID_DQ_REG_START                              0x00540400
+#define BCHP_SID_DQ_REG_END                                0x005404bc
+#define BCHP_SID_STRM_REG_START                            0x00540800
+#define BCHP_SID_STRM_REG_END                              0x0054087c
+#define BCHP_SID_OUTPUT_REG_START                          0x00540c00
+#define BCHP_SID_OUTPUT_REG_END                            0x00540c40
+#define BCHP_SID_ARC_REG_START                             0x00540f00
+#define BCHP_SID_ARC_REG_END                               0x00540f3c
+#define BCHP_SID_ARCDMA_REG_START                          0x00541800
+#define BCHP_SID_ARCDMA_REG_END                            0x00541840
+#define BCHP_SID_DMARAM_REG_START                          0x00541a00
+#define BCHP_SID_DMARAM_REG_END                            0x00541bfc
+#define BCHP_SID_PEEK_BITS_REG_START                       0x00542b00
+#define BCHP_SID_PEEK_BITS_REG_END                         0x00542b3c
+#define BCHP_SID_EXTRACT_BITS_REG_START                    0x00542b40
+#define BCHP_SID_EXTRACT_BITS_REG_END                      0x00542b7c
+#define BCHP_SID_HUFF_SYMB_REG_START                       0x00543000
+#define BCHP_SID_HUFF_SYMB_REG_END                         0x005437fc
+#define BCHP_SID_HUFF_CODE_REG_START                       0x00543900
+#define BCHP_SID_HUFF_CODE_REG_END                         0x005439fc
+#define BCHP_SID_SYMB_REG_START                            0x00543a00
+#define BCHP_SID_SYMB_REG_END                              0x00543a10
+#define BCHP_SID_SYMB_JPEG_REG_START                       0x00543a80
+#define BCHP_SID_SYMB_JPEG_REG_END                         0x00543a8c
+#define BCHP_SID_BIGRAM_REG_START                          0x00548000
+#define BCHP_SID_BIGRAM_REG_END                            0x0054fffc
+#define BCHP_SID_ARC_DBG_REG_START                         0x00551000
+#define BCHP_SID_ARC_DBG_REG_END                           0x00551010
+#define BCHP_SID_ARC_CORE_REG_START                        0x00555000
+#define BCHP_SID_ARC_CORE_REG_END                          0x00555014
+#define BCHP_SID_GR_REG_START                              0x00560000
+#define BCHP_SID_GR_REG_END                                0x0056000c
+#define BCHP_SICH_REG_START                                0x00561000
+#define BCHP_SICH_REG_END                                  0x0056103c
+#define BCHP_MFD_0_REG_START                               0x00600000
+#define BCHP_MFD_0_REG_END                                 0x00600264
+#define BCHP_MFD_1_REG_START                               0x00600400
+#define BCHP_MFD_1_REG_END                                 0x006005fc
+#define BCHP_VFD_0_REG_START                               0x00601000
+#define BCHP_VFD_0_REG_END                                 0x006011fc
+#define BCHP_VFD_1_REG_START                               0x00601200
+#define BCHP_VFD_1_REG_END                                 0x006013fc
+#define BCHP_VFD_2_REG_START                               0x00601400
+#define BCHP_VFD_2_REG_END                                 0x006015fc
+#define BCHP_VFD_3_REG_START                               0x00601600
+#define BCHP_VFD_3_REG_END                                 0x006017fc
+#define BCHP_RDC_REG_START                                 0x00602000
+#define BCHP_RDC_REG_END                                   0x006029fc
+#define BCHP_BVNF_INTR2_0_REG_START                        0x00603000
+#define BCHP_BVNF_INTR2_0_REG_END                          0x0060302c
+#define BCHP_BVNF_INTR2_1_REG_START                        0x00603100
+#define BCHP_BVNF_INTR2_1_REG_END                          0x0060312c
+#define BCHP_BVNF_INTR2_3_REG_START                        0x00603300
+#define BCHP_BVNF_INTR2_3_REG_END                          0x0060332c
+#define BCHP_BVNF_INTR2_4_REG_START                        0x00603400
+#define BCHP_BVNF_INTR2_4_REG_END                          0x0060342c
+#define BCHP_BVNF_INTR2_5_REG_START                        0x00603500
+#define BCHP_BVNF_INTR2_5_REG_END                          0x0060352c
+#define BCHP_BVNF_INTR2_6_REG_START                        0x00603600
+#define BCHP_BVNF_INTR2_6_REG_END                          0x0060362c
+#define BCHP_BVNF_INTR2_7_REG_START                        0x00603700
+#define BCHP_BVNF_INTR2_7_REG_END                          0x0060372c
+#define BCHP_FMISC_REG_START                               0x00604000
+#define BCHP_FMISC_REG_END                                 0x00604020
+#define BCHP_SCL_0_REG_START                               0x00620000
+#define BCHP_SCL_0_REG_END                                 0x006203fc
+#define BCHP_SCL_1_REG_START                               0x00620400
+#define BCHP_SCL_1_REG_END                                 0x006207fc
+#define BCHP_SCL_2_REG_START                               0x00620800
+#define BCHP_SCL_2_REG_END                                 0x00620bfc
+#define BCHP_SCL_3_REG_START                               0x00620c00
+#define BCHP_SCL_3_REG_END                                 0x00620ffc
+#define BCHP_VNET_F_REG_START                              0x00622000
+#define BCHP_VNET_F_REG_END                                0x006220bc
+#define BCHP_VNET_B_REG_START                              0x00622200
+#define BCHP_VNET_B_REG_END                                0x006222bc
+#define BCHP_MMISC_REG_START                               0x00622800
+#define BCHP_MMISC_REG_END                                 0x00622820
+#define BCHP_LBOX_0_REG_START                              0x00625000
+#define BCHP_LBOX_0_REG_END                                0x00625070
+#define BCHP_LBOX_1_REG_START                              0x00625200
+#define BCHP_LBOX_1_REG_END                                0x00625270
+#define BCHP_BVNM_INTR2_0_REG_START                        0x00626000
+#define BCHP_BVNM_INTR2_0_REG_END                          0x0062602c
+#define BCHP_DNR_0_REG_START                               0x00627000
+#define BCHP_DNR_0_REG_END                                 0x006270a4
+#define BCHP_CAP_0_REG_START                               0x00640000
+#define BCHP_CAP_0_REG_END                                 0x0064007c
+#define BCHP_CAP_1_REG_START                               0x00640200
+#define BCHP_CAP_1_REG_END                                 0x0064027c
+#define BCHP_CAP_2_REG_START                               0x00640400
+#define BCHP_CAP_2_REG_END                                 0x0064047c
+#define BCHP_CAP_3_REG_START                               0x00640600
+#define BCHP_CAP_3_REG_END                                 0x0064067c
+#define BCHP_GFD_0_REG_START                               0x00641000
+#define BCHP_GFD_0_REG_END                                 0x00641228
+#define BCHP_GFD_1_REG_START                               0x00641400
+#define BCHP_GFD_1_REG_END                                 0x00641554
+#define BCHP_CMP_0_REG_START                               0x00642000
+#define BCHP_CMP_0_REG_END                                 0x006424b4
+#define BCHP_CMP_1_REG_START                               0x00642800
+#define BCHP_CMP_1_REG_END                                 0x00642cb4
+#define BCHP_TNT_CMP_0_V0_REG_START                        0x00643000
+#define BCHP_TNT_CMP_0_V0_REG_END                          0x006430a4
+#define BCHP_MASK_0_REG_START                              0x00643400
+#define BCHP_MASK_0_REG_END                                0x00643420
+#define BCHP_PEP_CMP_0_V0_REG_START                        0x00644000
+#define BCHP_PEP_CMP_0_V0_REG_END                          0x00645484
+#define BCHP_BVNB_INTR2_REG_START                          0x00646000
+#define BCHP_BVNB_INTR2_REG_END                            0x0064602c
+#define BCHP_BMISC_REG_START                               0x00646400
+#define BCHP_BMISC_REG_END                                 0x0064641c
+#define BCHP_MVP_TOP_0_REG_START                           0x00660000
+#define BCHP_MVP_TOP_0_REG_END                             0x0066002c
+#define BCHP_SIOB_0_REG_START                              0x00660200
+#define BCHP_SIOB_0_REG_END                                0x006602fc
+#define BCHP_HSCL_0_REG_START                              0x00660400
+#define BCHP_HSCL_0_REG_END                                0x006607fc
+#define BCHP_MDI_TOP_0_REG_START                           0x00662000
+#define BCHP_MDI_TOP_0_REG_END                             0x00662044
+#define BCHP_MDI_PPB_0_REG_START                           0x00662800
+#define BCHP_MDI_PPB_0_REG_END                             0x00662bfc
+#define BCHP_MDI_FCN_0_REG_START                           0x00662c00
+#define BCHP_MDI_FCN_0_REG_END                             0x00662ffc
+#define BCHP_MISC_REG_START                                0x00680000
+#define BCHP_MISC_REG_END                                  0x0068009c
+#define BCHP_IT_0_REG_START                                0x00681000
+#define BCHP_IT_0_REG_END                                  0x006817fc
+#define BCHP_IT_1_REG_START                                0x00682000
+#define BCHP_IT_1_REG_END                                  0x006827fc
+#define BCHP_VF_0_REG_START                                0x00683000
+#define BCHP_VF_0_REG_END                                  0x00683134
+#define BCHP_VF_1_REG_START                                0x00683200
+#define BCHP_VF_1_REG_END                                  0x00683334
+#define BCHP_SECAM_0_REG_START                             0x00683400
+#define BCHP_SECAM_0_REG_END                               0x00683414
+#define BCHP_SM_0_REG_START                                0x00683480
+#define BCHP_SM_0_REG_END                                  0x006834ac
+#define BCHP_SDSRC_0_REG_START                             0x00683500
+#define BCHP_SDSRC_0_REG_END                               0x0068350c
+#define BCHP_HDSRC_0_REG_START                             0x00683520
+#define BCHP_HDSRC_0_REG_END                               0x0068353c
+#define BCHP_CSC_0_REG_START                               0x00683580
+#define BCHP_CSC_0_REG_END                                 0x006835b0
+#define BCHP_CSC_1_REG_START                               0x00683600
+#define BCHP_CSC_1_REG_END                                 0x00683630
+#define BCHP_RM_0_REG_START                                0x00683680
+#define BCHP_RM_0_REG_END                                  0x006836a4
+#define BCHP_RM_1_REG_START                                0x006836c0
+#define BCHP_RM_1_REG_END                                  0x006836e4
+#define BCHP_ANA_DEBUG_0_REG_START                         0x00683700
+#define BCHP_ANA_DEBUG_0_REG_END                           0x00683744
+#define BCHP_GRPD_0_REG_START                              0x00683800
+#define BCHP_GRPD_0_REG_END                                0x006838ec
+#define BCHP_DTRAM_0_REG_START                             0x00684000
+#define BCHP_DTRAM_0_REG_END                               0x0068447c
+#define BCHP_DVI_DTG_0_REG_START                           0x00684800
+#define BCHP_DVI_DTG_0_REG_END                             0x00684954
+#define BCHP_DVI_CSC_0_REG_START                           0x00684a00
+#define BCHP_DVI_CSC_0_REG_END                             0x00684a30
+#define BCHP_DVI_DVF_0_REG_START                           0x00684b00
+#define BCHP_DVI_DVF_0_REG_END                             0x00684b14
+#define BCHP_DVI_DEBUG_0_REG_START                         0x00684c00
+#define BCHP_DVI_DEBUG_0_REG_END                           0x00684c44
+#define BCHP_ITU656_DTG_0_REG_START                        0x00685000
+#define BCHP_ITU656_DTG_0_REG_END                          0x00685154
+#define BCHP_ITU656_CSC_0_REG_START                        0x00685200
+#define BCHP_ITU656_CSC_0_REG_END                          0x00685230
+#define BCHP_ITU656_DVF_0_REG_START                        0x00685300
+#define BCHP_ITU656_DVF_0_REG_END                          0x00685314
+#define BCHP_ITU656_0_REG_START                            0x00685400
+#define BCHP_ITU656_0_REG_END                              0x00685420
+#define BCHP_VEC_CFG_REG_START                             0x00685600
+#define BCHP_VEC_CFG_REG_END                               0x00685708
+#define BCHP_VIDEO_ENC_INTR2_REG_START                     0x00685a00
+#define BCHP_VIDEO_ENC_INTR2_REG_END                       0x00685a2c
+#define BCHP_VIDEO_ENC_TPG_0_REG_START                     0x00685b00
+#define BCHP_VIDEO_ENC_TPG_0_REG_END                       0x00685b18
+#define BCHP_VIDEO_ENC_DECIM_0_REG_START                   0x00685c00
+#define BCHP_VIDEO_ENC_DECIM_0_REG_END                     0x00685c08
+#define BCHP_DVP_TVG_0_REG_START                           0x00685d00
+#define BCHP_DVP_TVG_0_REG_END                             0x00685d88
+#define BCHP_VBI_ENC_REG_START                             0x00686000
+#define BCHP_VBI_ENC_REG_END                               0x00686074
+#define BCHP_CCE_0_REG_START                               0x00686400
+#define BCHP_CCE_0_REG_END                                 0x00686458
+#define BCHP_CCE_1_REG_START                               0x00686500
+#define BCHP_CCE_1_REG_END                                 0x00686558
+#define BCHP_WSE_0_REG_START                               0x00686600
+#define BCHP_WSE_0_REG_END                                 0x00686614
+#define BCHP_WSE_1_REG_START                               0x00686700
+#define BCHP_WSE_1_REG_END                                 0x00686714
+#define BCHP_CGMSAE_0_REG_START                            0x00686800
+#define BCHP_CGMSAE_0_REG_END                              0x00686858
+#define BCHP_CGMSAE_1_REG_START                            0x00686900
+#define BCHP_CGMSAE_1_REG_END                              0x00686958
+#define BCHP_TTE_0_REG_START                               0x00686a00
+#define BCHP_TTE_0_REG_END                                 0x00686a28
+#define BCHP_TTE_1_REG_START                               0x00686b00
+#define BCHP_TTE_1_REG_END                                 0x00686b28
+#define BCHP_GSE_0_REG_START                               0x00686c00
+#define BCHP_GSE_0_REG_END                                 0x00686c80
+#define BCHP_GSE_1_REG_START                               0x00686d00
+#define BCHP_GSE_1_REG_END                                 0x00686d80
+#define BCHP_AMOLE_0_REG_START                             0x00686e00
+#define BCHP_AMOLE_0_REG_END                               0x00686e8c
+#define BCHP_AMOLE_1_REG_START                             0x00686f00
+#define BCHP_AMOLE_1_REG_END                               0x00686f8c
+#define BCHP_CCE_ANCIL_0_REG_START                         0x00687000
+#define BCHP_CCE_ANCIL_0_REG_END                           0x00687054
+#define BCHP_WSE_ANCIL_0_REG_START                         0x00687100
+#define BCHP_WSE_ANCIL_0_REG_END                           0x0068710c
+#define BCHP_TTE_ANCIL_0_REG_START                         0x00687200
+#define BCHP_TTE_ANCIL_0_REG_END                           0x00687228
+#define BCHP_GSE_ANCIL_0_REG_START                         0x00687300
+#define BCHP_GSE_ANCIL_0_REG_END                           0x00687380
+#define BCHP_AMOLE_ANCIL_0_REG_START                       0x00687400
+#define BCHP_AMOLE_ANCIL_0_REG_END                         0x0068748c
+#define BCHP_ANCI656_ANCIL_0_REG_START                     0x00687500
+#define BCHP_ANCI656_ANCIL_0_REG_END                       0x00687524
+#define BCHP_DVP_HT_REG_START                              0x006a0000
+#define BCHP_DVP_HT_REG_END                                0x006a00d4
+#define BCHP_HDMI_REG_START                                0x006a0800
+#define BCHP_HDMI_REG_END                                  0x006a0994
+#define BCHP_HDMI_TX_PHY_REG_START                         0x006a0a80
+#define BCHP_HDMI_TX_PHY_REG_END                           0x006a0ad8
+#define BCHP_HDMI_RM_REG_START                             0x006a0b00
+#define BCHP_HDMI_RM_REG_END                               0x006a0b2c
+#define BCHP_HDMI_TX_INTR2_REG_START                       0x006a0b40
+#define BCHP_HDMI_TX_INTR2_REG_END                         0x006a0b6c
+#define BCHP_HDMI_RAM_REG_START                            0x006a0c00
+#define BCHP_HDMI_RAM_REG_END                              0x006a0dfc
+#define BCHP_HD_DVI_0_REG_START                            0x006a8000
+#define BCHP_HD_DVI_0_REG_END                              0x006a81fc
+#define BCHP_BVN_RGR_REG_START                             0x006ac000
+#define BCHP_BVN_RGR_REG_END                               0x006ac010
+#define BCHP_RAAGA_DSP_RGR_REG_START                       0x00800000
+#define BCHP_RAAGA_DSP_RGR_REG_END                         0x00800008
+#define BCHP_RAAGA_DSP_MISC_REG_START                      0x00820000
+#define BCHP_RAAGA_DSP_MISC_REG_END                        0x0082044c
+#define BCHP_RAAGA_DSP_TIMERS_REG_START                    0x00821000
+#define BCHP_RAAGA_DSP_TIMERS_REG_END                      0x00821058
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START             0x00821080
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END               0x0082109c
+#define BCHP_RAAGA_DSP_PERI_SW_REG_START                   0x00821100
+#define BCHP_RAAGA_DSP_PERI_SW_REG_END                     0x00821154
+#define BCHP_RAAGA_DSP_DMA_REG_START                       0x00821400
+#define BCHP_RAAGA_DSP_DMA_REG_END                         0x00821664
+#define BCHP_RAAGA_DSP_ESR_SI_REG_START                    0x00822000
+#define BCHP_RAAGA_DSP_ESR_SI_REG_END                      0x00822014
+#define BCHP_RAAGA_DSP_INTH_REG_START                      0x00822200
+#define BCHP_RAAGA_DSP_INTH_REG_END                        0x0082222c
+#define BCHP_RAAGA_DSP_FW_INTH_REG_START                   0x00822400
+#define BCHP_RAAGA_DSP_FW_INTH_REG_END                     0x0082242c
+#define BCHP_RAAGA_DSP_FW_CFG_REG_START                    0x00823000
+#define BCHP_RAAGA_DSP_FW_CFG_REG_END                      0x0082357c
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START             0x00830000
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END               0x0083bffc
+#define BCHP_AIO_MISC_REG_START                            0x00880000
+#define BCHP_AIO_MISC_REG_END                              0x00880010
+#define BCHP_AIO_INTH_REG_START                            0x00880800
+#define BCHP_AIO_INTH_REG_END                              0x0088082c
+#define BCHP_AIO_INTD0_REG_START                           0x00880a00
+#define BCHP_AIO_INTD0_REG_END                             0x00880a14
+#define BCHP_AUD_FMM_MISC_REG_START                        0x008a0000
+#define BCHP_AUD_FMM_MISC_REG_END                          0x008a010c
+#define BCHP_AUD_FMM_BF_CTRL_REG_START                     0x008a2000
+#define BCHP_AUD_FMM_BF_CTRL_REG_END                       0x008a2b7c
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_START                   0x008a3000
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_END                     0x008a3014
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_START                   0x008a3020
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_END                     0x008a3034
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_START                   0x008a3040
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_END                     0x008a3054
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_START                  0x008a3100
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_END                    0x008a3114
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_START                  0x008a3120
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_END                    0x008a3134
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_START                  0x008a3140
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_END                    0x008a3154
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_START                   0x008a4000
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_END                     0x008a4bfc
+#define BCHP_AUD_FMM_SRC_ESR0_REG_START                    0x008a5000
+#define BCHP_AUD_FMM_SRC_ESR0_REG_END                      0x008a5014
+#define BCHP_AUD_FMM_DP_CTRL0_REG_START                    0x008a8000
+#define BCHP_AUD_FMM_DP_CTRL0_REG_END                      0x008a98ec
+#define BCHP_AUD_FMM_DP_ESR00_REG_START                    0x008abc00
+#define BCHP_AUD_FMM_DP_ESR00_REG_END                      0x008abc14
+#define BCHP_AUD_FMM_DP_ESR20_REG_START                    0x008abc80
+#define BCHP_AUD_FMM_DP_ESR20_REG_END                      0x008abc94
+#define BCHP_AUD_FMM_IOP_CTRL_REG_START                    0x008b8000
+#define BCHP_AUD_FMM_IOP_CTRL_REG_END                      0x008b8144
+#define BCHP_AUD_FMM_IOP_ESR_REG_START                     0x008b8400
+#define BCHP_AUD_FMM_IOP_ESR_REG_END                       0x008b8414
+#define BCHP_AUD_FMM_OP_CTRL_REG_START                     0x008ba000
+#define BCHP_AUD_FMM_OP_CTRL_REG_END                       0x008ba1fc
+#define BCHP_AUD_FMM_OP_ESR_REG_START                      0x008ba400
+#define BCHP_AUD_FMM_OP_ESR_REG_END                        0x008ba414
+#define BCHP_AUD_FMM_PLL0_REG_START                        0x008ba800
+#define BCHP_AUD_FMM_PLL0_REG_END                          0x008ba834
+#define BCHP_AUD_FMM_PLL1_REG_START                        0x008ba900
+#define BCHP_AUD_FMM_PLL1_REG_END                          0x008ba934
+#define BCHP_HIFIDAC_CTRL0_REG_START                       0x008bb000
+#define BCHP_HIFIDAC_CTRL0_REG_END                         0x008bb1fc
+#define BCHP_HIFIDAC_RM0_REG_START                         0x008bb200
+#define BCHP_HIFIDAC_RM0_REG_END                           0x008bb224
+#define BCHP_HIFIDAC_ESR0_REG_START                        0x008bb300
+#define BCHP_HIFIDAC_ESR0_REG_END                          0x008bb314
+#define BCHP_AUD_FMM_MS_CTRL_REG_START                     0x008bc000
+#define BCHP_AUD_FMM_MS_CTRL_REG_END                       0x008bdbfc
+#define BCHP_AUD_FMM_MS_ESR_REG_START                      0x008be000
+#define BCHP_AUD_FMM_MS_ESR_REG_END                        0x008be014
+#define BCHP_RAAGA_DSP_SEC0_REG_START                      0x00900000
+#define BCHP_RAAGA_DSP_SEC0_REG_END                        0x00900000
+#define BCHP_XPT_BUS_IF_REG_START                          0x00a00000
+#define BCHP_XPT_BUS_IF_REG_END                            0x00a00078
+#define BCHP_XPT_XMEMIF_REG_START                          0x00a00100
+#define BCHP_XPT_XMEMIF_REG_END                            0x00a001a0
+#define BCHP_XPT_PMU_REG_START                             0x00a00200
+#define BCHP_XPT_PMU_REG_END                               0x00a00208
+#define BCHP_XPT_GR_REG_START                              0x00a00300
+#define BCHP_XPT_GR_REG_END                                0x00a0030c
+#define BCHP_XPT_RMX0_IO_REG_START                         0x00a00400
+#define BCHP_XPT_RMX0_IO_REG_END                           0x00a00420
+#define BCHP_XPT_RMX1_IO_REG_START                         0x00a00500
+#define BCHP_XPT_RMX1_IO_REG_END                           0x00a00520
+#define BCHP_XPT_WAKEUP_REG_START                          0x00a01000
+#define BCHP_XPT_WAKEUP_REG_END                            0x00a01fbc
+#define BCHP_XPT_FE_REG_START                              0x00a04000
+#define BCHP_XPT_FE_REG_END                                0x00a053fc
+#define BCHP_XPT_DPCR0_REG_START                           0x00a07000
+#define BCHP_XPT_DPCR0_REG_END                             0x00a07074
+#define BCHP_XPT_DPCR1_REG_START                           0x00a07080
+#define BCHP_XPT_DPCR1_REG_END                             0x00a070f4
+#define BCHP_XPT_DPCR2_REG_START                           0x00a07100
+#define BCHP_XPT_DPCR2_REG_END                             0x00a07174
+#define BCHP_XPT_DPCR3_REG_START                           0x00a07180
+#define BCHP_XPT_DPCR3_REG_END                             0x00a071f4
+#define BCHP_XPT_DPCR_PP_REG_START                         0x00a07400
+#define BCHP_XPT_DPCR_PP_REG_END                           0x00a07404
+#define BCHP_XPT_PSUB_REG_START                            0x00a07a00
+#define BCHP_XPT_PSUB_REG_END                              0x00a07ac8
+#define BCHP_XPT_MPOD_REG_START                            0x00a07c00
+#define BCHP_XPT_MPOD_REG_END                              0x00a07c20
+#define BCHP_XPT_RMX0_REG_START                            0x00a07d00
+#define BCHP_XPT_RMX0_REG_END                              0x00a07d08
+#define BCHP_XPT_RMX1_REG_START                            0x00a07e00
+#define BCHP_XPT_RMX1_REG_END                              0x00a07e08
+#define BCHP_XPT_PB_TOP_REG_START                          0x00a08000
+#define BCHP_XPT_PB_TOP_REG_END                            0x00a0805c
+#define BCHP_XPT_PB0_REG_START                             0x00a08100
+#define BCHP_XPT_PB0_REG_END                               0x00a08174
+#define BCHP_XPT_PB1_REG_START                             0x00a08180
+#define BCHP_XPT_PB1_REG_END                               0x00a081f4
+#define BCHP_XPT_PB2_REG_START                             0x00a08200
+#define BCHP_XPT_PB2_REG_END                               0x00a08274
+#define BCHP_XPT_PB3_REG_START                             0x00a08280
+#define BCHP_XPT_PB3_REG_END                               0x00a082f4
+#define BCHP_XPT_PB4_REG_START                             0x00a08300
+#define BCHP_XPT_PB4_REG_END                               0x00a08374
+#define BCHP_XPT_PB5_REG_START                             0x00a08380
+#define BCHP_XPT_PB5_REG_END                               0x00a083f4
+#define BCHP_XPT_PCROFFSET_REG_START                       0x00a0c000
+#define BCHP_XPT_PCROFFSET_REG_END                         0x00a0d8fc
+#define BCHP_XPT_FULL_PID_PARSER_REG_START                 0x00a10000
+#define BCHP_XPT_FULL_PID_PARSER_REG_END                   0x00a12050
+#define BCHP_XPT_RSBUFF_REG_START                          0x00a15000
+#define BCHP_XPT_RSBUFF_REG_END                            0x00a15b44
+#define BCHP_XPT_XCBUFF_REG_START                          0x00a16000
+#define BCHP_XPT_XCBUFF_REG_END                            0x00a17ccc
+#define BCHP_XPT_MSG_REG_START                             0x00a18000
+#define BCHP_XPT_MSG_REG_END                               0x00a1e014
+#define BCHP_XPT_RAVE_REG_START                            0x00a20000
+#define BCHP_XPT_RAVE_REG_END                              0x00a2bcfc
+#define BCHP_XPT_XPU_REG_START                             0x00a30000
+#define BCHP_XPT_XPU_REG_END                               0x00a347fc
+#define BCHP_XPT_SECURE_BUS_IF_REG_START                   0x00a3f000
+#define BCHP_XPT_SECURE_BUS_IF_REG_END                     0x00a3f000
+
+
+/***************************************************************************
+ *AUD_FMM_MS_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK  0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
+
+/***************************************************************************
+ *AUD_FMM_OP_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
+ ***************************************************************************/
+/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD1
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_VFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *GFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK      0xffffffff
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT     0
+
+/***************************************************************************
+ *GFD_1
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD_1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK    0xffffffff
+#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT   0
+
+/***************************************************************************
+ *HIFIDAC_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_MUTE_USAGE - Mute usage
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *M2MC
+ ***************************************************************************/
+/***************************************************************************
+ *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK          0xffffffff
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT         0
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK              0xf0000000
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT             28
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK          0x0fffffe0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT         5
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK              0x0000001e
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT             1
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK           0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT          0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid   0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK              0xffff8000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT             15
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK   0x00004000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT  14
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK   0x00002000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT  13
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK         0x00000800
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT        11
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE   1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE  0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK  0x00000400
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK  0x00000200
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK          0x00000100
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT         8
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE   0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK   0x00000020
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT  5
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK     0x00000002
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK     0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT    0
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/***************************************************************************
+ *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK        0xffffffff
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT       0
+
+/***************************************************************************
+ *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK         0xffffffff
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT        0
+
+/***************************************************************************
+ *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_11_DST_COLOR_MATRIX_N - Linked-List Packet Word N for group DST_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_11_DST_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_12_OUTPUT_COLOR_MATRIX_N - Linked-List Packet Word N for group OUTPUT_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_12_OUTPUT_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_13_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *LIST_PKT_14_DST_CLUT - Linked-List Packet Word for group DST_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_14_DST_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_14_DST_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *TYPE_CLUT_COLOR_DATA - color data for color look up table
+ ***************************************************************************/
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK                  0xff000000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT                 24
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK                    0x00ff0000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT                   16
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK                  0x0000ff00
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT                 8
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK                   0x000000ff
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT                  0
+
+/***************************************************************************
+ *MEM_DMA
+ ***************************************************************************/
+/***************************************************************************
+ *DESC_WORD0 - MEM DMA Descriptor Word 0
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD0 :: READ_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD1 - MEM DMA Descriptor Word 1
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD1 :: WRITE_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_MASK                    0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD2 - MEM DMA Descriptor Word 2
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD2 :: INTR_ENABLE [31:31] */
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK                   0x80000000
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_SHIFT                  31
+
+/* MEM_DMA :: DESC_WORD2 :: LAST [30:30] */
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_MASK                          0x40000000
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_SHIFT                         30
+
+/* MEM_DMA :: DESC_WORD2 :: AUTO_APPEND [29:29] */
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_MASK                   0x20000000
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_SHIFT                  29
+
+/* MEM_DMA :: DESC_WORD2 :: reserved0 [28:25] */
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_MASK                     0x1e000000
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_SHIFT                    25
+
+/* MEM_DMA :: DESC_WORD2 :: TRANSFER_SIZE [24:00] */
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK                 0x01ffffff
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_SHIFT                0
+
+/***************************************************************************
+ *DESC_WORD3 - MEM DMA Descriptor Word 3
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD3 :: NEXT_DESC_ADDR [31:05] */
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK                0xffffffe0
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_SHIFT               5
+
+/* MEM_DMA :: DESC_WORD3 :: reserved0 [04:03] */
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_MASK                     0x00000018
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_SHIFT                    3
+
+/* MEM_DMA :: DESC_WORD3 :: READ_ENDIAN_MODE [02:02] */
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_MASK              0x00000004
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_SHIFT             2
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_BIG_ENDIAN        0
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_LITTLE_ENDIAN     1
+
+/* MEM_DMA :: DESC_WORD3 :: WRITE_ENDIAN_XLATE_MODE [01:00] */
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_MASK       0x00000003
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_SHIFT      0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_WORD_ALIGNED 0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_HALF_WORD_ALIGNED 1
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_BYTE_ALIGNED 2
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_reserved   3
+
+/***************************************************************************
+ *DESC_WORD4 - MEM DMA Descriptor Word 4
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD4 :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_SHIFT                    16
+
+/* MEM_DMA :: DESC_WORD4 :: SCRAM_CTRL_RSV [15:14] */
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_MASK                0x0000c000
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_SHIFT               14
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_END [13:13] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK                  0x00002000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_SHIFT                 13
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_START [12:12] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK                0x00001000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_SHIFT               12
+
+/* MEM_DMA :: DESC_WORD4 :: SG_ENABLE [11:11] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK                     0x00000800
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_SHIFT                    11
+
+/* MEM_DMA :: DESC_WORD4 :: ENC_DEC_INIT [10:10] */
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_MASK                  0x00000400
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_SHIFT                 10
+
+/* MEM_DMA :: DESC_WORD4 :: MODE_SEL [09:08] */
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_MASK                      0x00000300
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT                     8
+
+/* MEM_DMA :: DESC_WORD4 :: KEY_SELECT [07:00] */
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_MASK                    0x000000ff
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD5 - MEM DMA Descriptor Word 5
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD5 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD6 - MEM DMA Descriptor Word 6
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD6 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD7 - MEM DMA Descriptor Word 7
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD7 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *RAAGA_REGSET_DSP_CFG
+ ***************************************************************************/
+/***************************************************************************
+ *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK     0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT    0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo   2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono     1
+
+/***************************************************************************
+ *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
+
+/***************************************************************************
+ *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off     0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On      1
+
+/***************************************************************************
+ *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt  1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo  2
+
+/***************************************************************************
+ *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK       0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT      0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono    1
+
+/***************************************************************************
+ *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK   0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *RDC
+ ***************************************************************************/
+/***************************************************************************
+ *RUL - RUL Command.
+ ***************************************************************************/
+/* RDC :: RUL :: opcode [31:24] */
+#define BCHP_RDC_RUL_opcode_MASK                                   0xff000000
+#define BCHP_RDC_RUL_opcode_SHIFT                                  24
+#define BCHP_RDC_RUL_opcode_NOP                                    0
+#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM                          1
+#define BCHP_RDC_RUL_opcode_REG_WRITE                              2
+#define BCHP_RDC_RUL_opcode_REG_READ                               3
+#define BCHP_RDC_RUL_opcode_LOAD_IMM                               4
+#define BCHP_RDC_RUL_opcode_WINDOW_WRITE                           5
+#define BCHP_RDC_RUL_opcode_BLOCK_WRITE                            6
+#define BCHP_RDC_RUL_opcode_WINDOW_COPY                            7
+#define BCHP_RDC_RUL_opcode_BLOCK_COPY                             8
+#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK                        9
+#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW                        10
+#define BCHP_RDC_RUL_opcode_AND                                    11
+#define BCHP_RDC_RUL_opcode_AND_IMM                                12
+#define BCHP_RDC_RUL_opcode_OR                                     13
+#define BCHP_RDC_RUL_opcode_OR_IMM                                 14
+#define BCHP_RDC_RUL_opcode_XOR                                    15
+#define BCHP_RDC_RUL_opcode_XOR_IMM                                16
+#define BCHP_RDC_RUL_opcode_NOT                                    17
+#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT                           18
+#define BCHP_RDC_RUL_opcode_SUM                                    19
+#define BCHP_RDC_RUL_opcode_SUM_IMM                                20
+#define BCHP_RDC_RUL_opcode_COND_SKIP                              21
+#define BCHP_RDC_RUL_opcode_SKIP                                   22
+#define BCHP_RDC_RUL_opcode_EXIT                                   23
+#define BCHP_RDC_RUL_opcode_PLACEHOLDER                            255
+
+/* RDC :: RUL :: reserved0 [23:23] */
+#define BCHP_RDC_RUL_reserved0_MASK                                0x00800000
+#define BCHP_RDC_RUL_reserved0_SHIFT                               23
+
+/* union - case rdc_args [22:00] */
+/* RDC :: RUL :: rdc_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_rdc_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: rdc_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_rdc_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_rdc_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: rdc_args :: src2 [11:06] */
+#define BCHP_RDC_RUL_rdc_args_src2_MASK                            0x00000fc0
+#define BCHP_RDC_RUL_rdc_args_src2_SHIFT                           6
+
+/* RDC :: RUL :: rdc_args :: dest [05:00] */
+#define BCHP_RDC_RUL_rdc_args_dest_MASK                            0x0000003f
+#define BCHP_RDC_RUL_rdc_args_dest_SHIFT                           0
+
+/* union - case reg_args [22:00] */
+/* RDC :: RUL :: reg_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_reg_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_reg_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: reg_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_reg_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_reg_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: reg_args :: count [11:00] */
+#define BCHP_RDC_RUL_reg_args_count_MASK                           0x00000fff
+#define BCHP_RDC_RUL_reg_args_count_SHIFT                          0
+
+/***************************************************************************
+ *XPT_PB
+ ***************************************************************************/
+/***************************************************************************
+ *DESCRIPTOR_ABSTRACT - Playback Linked-List Descriptor Abstract
+ ***************************************************************************/
+/* XPT_PB :: DESCRIPTOR_ABSTRACT :: DESCRIPTOR_FORMAT [31:00] */
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_MASK     0xffffffff
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_SHIFT    0
+
+/***************************************************************************
+ *DESC_0 - Playback Linked-List Descriptor Word 0
+ ***************************************************************************/
+/* XPT_PB :: DESC_0 :: PB_BUFFER_START_ADDR [31:00] */
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_MASK               0xffffffff
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_SHIFT              0
+
+/***************************************************************************
+ *DESC_1 - Playback Linked-List Descriptor Word 1
+ ***************************************************************************/
+/* XPT_PB :: DESC_1 :: PB_BUFFER_LENGTH [31:00] */
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_MASK                   0xffffffff
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_SHIFT                  0
+
+/***************************************************************************
+ *DESC_2 - Playback Linked-List Descriptor Word 2
+ ***************************************************************************/
+/* XPT_PB :: DESC_2 :: PB_INTERRUPT_ENABLE [31:31] */
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_MASK                0x80000000
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_SHIFT               31
+
+/* XPT_PB :: DESC_2 :: PB_FORCE_RESYNC [30:30] */
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_MASK                    0x40000000
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_SHIFT                   30
+
+/* XPT_PB :: DESC_2 :: PB_HOST_DATA_INS_EN [29:29] */
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_MASK                0x20000000
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_SHIFT               29
+
+/* XPT_PB :: DESC_2 :: PUSH_PARTIAL_PACKET [28:28] */
+#define BCHP_XPT_PB_DESC_2_PUSH_PARTIAL_PACKET_MASK                0x10000000
+#define BCHP_XPT_PB_DESC_2_PUSH_PARTIAL_PACKET_SHIFT               28
+
+/* XPT_PB :: DESC_2 :: PB_DESC_TAG_ID [27:24] */
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_MASK                     0x0f000000
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_SHIFT                    24
+
+/* XPT_PB :: DESC_2 :: reserved0 [23:00] */
+#define BCHP_XPT_PB_DESC_2_reserved0_MASK                          0x00ffffff
+#define BCHP_XPT_PB_DESC_2_reserved0_SHIFT                         0
+
+/***************************************************************************
+ *DESC_3 - Playback Linked-List Descriptor Word 3
+ ***************************************************************************/
+/* XPT_PB :: DESC_3 :: PB_NEXT_DESC_ADDR [31:04] */
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_MASK                  0xfffffff0
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_SHIFT                 4
+
+/* XPT_PB :: DESC_3 :: reserved0 [03:01] */
+#define BCHP_XPT_PB_DESC_3_reserved0_MASK                          0x0000000e
+#define BCHP_XPT_PB_DESC_3_reserved0_SHIFT                         1
+
+/* XPT_PB :: DESC_3 :: PB_LAST_DESC_IND [00:00] */
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_MASK                   0x00000001
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_SHIFT                  0
+
+/***************************************************************************
+ *DESC_4 - Playback Linked-List Descriptor Word 4
+ ***************************************************************************/
+/* XPT_PB :: DESC_4 :: reserved0 [31:00] */
+#define BCHP_XPT_PB_DESC_4_reserved0_MASK                          0xffffffff
+#define BCHP_XPT_PB_DESC_4_reserved0_SHIFT                         0
+
+/***************************************************************************
+ *DESC_5 - Playback Linked-List Descriptor Word 5
+ ***************************************************************************/
+/* XPT_PB :: DESC_5 :: reserved0 [31:03] */
+#define BCHP_XPT_PB_DESC_5_reserved0_MASK                          0xfffffff8
+#define BCHP_XPT_PB_DESC_5_reserved0_SHIFT                         3
+
+/* XPT_PB :: DESC_5 :: RANDOM_ACCESS_INDICATION [02:02] */
+#define BCHP_XPT_PB_DESC_5_RANDOM_ACCESS_INDICATION_MASK           0x00000004
+#define BCHP_XPT_PB_DESC_5_RANDOM_ACCESS_INDICATION_SHIFT          2
+
+/* XPT_PB :: DESC_5 :: NEXT_PACKET_PACING_TIMESTAMP_VALID [01:01] */
+#define BCHP_XPT_PB_DESC_5_NEXT_PACKET_PACING_TIMESTAMP_VALID_MASK 0x00000002
+#define BCHP_XPT_PB_DESC_5_NEXT_PACKET_PACING_TIMESTAMP_VALID_SHIFT 1
+
+/* XPT_PB :: DESC_5 :: PKT2PKT_PACING_TIMESTAMP_DELTA_VALID [00:00] */
+#define BCHP_XPT_PB_DESC_5_PKT2PKT_PACING_TIMESTAMP_DELTA_VALID_MASK 0x00000001
+#define BCHP_XPT_PB_DESC_5_PKT2PKT_PACING_TIMESTAMP_DELTA_VALID_SHIFT 0
+
+/***************************************************************************
+ *DESC_6 - Playback Linked-List Descriptor Word 6
+ ***************************************************************************/
+/* XPT_PB :: DESC_6 :: NEXT_PACKET_PACING_TIMESTAMP [31:00] */
+#define BCHP_XPT_PB_DESC_6_NEXT_PACKET_PACING_TIMESTAMP_MASK       0xffffffff
+#define BCHP_XPT_PB_DESC_6_NEXT_PACKET_PACING_TIMESTAMP_SHIFT      0
+
+/***************************************************************************
+ *DESC_7 - Playback Linked-List Descriptor Word 7
+ ***************************************************************************/
+/* XPT_PB :: DESC_7 :: PKT2PKT_PACING_TIMESTAMP_DELTA [31:00] */
+#define BCHP_XPT_PB_DESC_7_PKT2PKT_PACING_TIMESTAMP_DELTA_MASK     0xffffffff
+#define BCHP_XPT_PB_DESC_7_PKT2PKT_PACING_TIMESTAMP_DELTA_SHIFT    0
+
+/***************************************************************************
+ *XPT_RAVE
+ ***************************************************************************/
+/***************************************************************************
+ *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
+
+/***************************************************************************
+ *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
+
+/***************************************************************************
+ *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
+ ***************************************************************************/
+/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
+
+#endif /* #ifndef BCHP_COMMON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_ddr40_phy_control_regs_0.h b/include/linux/brcmstb/7231b0/bchp_ddr40_phy_control_regs_0.h
new file mode 100644
index 0000000..1d0c0b9
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_ddr40_phy_control_regs_0.h
@@ -0,0 +1,1513 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:05:34 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_ddr40_phy_control_regs_0.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:15p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_CONTROL_REGS_0 - DDR40 DDR40 physical interface control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION   0x003b6000 /* Address & Control revision register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL 0x003b6004 /* PHY clock power management control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS 0x003b6010 /* PHY PLL status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG 0x003b6014 /* PHY PLL configuration register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL 0x003b6018 /* PHY PLL control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS 0x003b601c /* PHY PLL dividers control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL 0x003b6020 /* Aux Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL 0x003b6030 /* Address & Control coarse VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL 0x003b6034 /* Address & Control fine VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL 0x003b6038 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL 0x003b603c /* PVT Compensation control and status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL 0x003b6040 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS 0x003b6044 /* PHY Auto Init rd_data_dly result register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE 0x003b6048 /* PHY VDL calibration control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS 0x003b604c /* PHY VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS 0x003b6050 /* PHY DQ VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS 0x003b6054 /* PHY Write Channel VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS 0x003b6058 /* PHY Read Enable VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL 0x003b605c /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS 0x003b6060 /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS 0x003b6064 /* Virtual VTT Connections register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE 0x003b6068 /* Virtual VTT Override register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL 0x003b606c /* VREF DAC Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL 0x003b6070 /* PhyBist Control Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED 0x003b6074 /* PhyBist Seed Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS 0x003b6078 /* PhyBist General Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS 0x003b607c /* PhyBist Per-Bit Control Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS 0x003b6080 /* PhyBist Per-Bit DQ Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS 0x003b6084 /* PhyBist Per-Bit DM and CK Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG 0x003b6090 /* DRAM Command Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0  0x003b6094 /* Mode Register 0 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1  0x003b6098 /* Mode Register 1 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2  0x003b609c /* Mode Register 2 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3  0x003b60a0 /* Mode Register 3 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL 0x003b60a4 /* Standby Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL 0x003b60b0 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2 0x003b60b4 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS 0x003b60b8 /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2 0x003b60bc /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE 0x003b60c0 /* Freeze-on-error enable register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK 0x003b60c4 /* Datapth Loopback control register */
+
+/***************************************************************************
+ *REVISION - Address & Control revision register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_MASK      0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_SHIFT     16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_MASK          0x0000ff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_SHIFT         8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_DEFAULT       64
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_MASK          0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_DEFAULT       5
+
+/***************************************************************************
+ *CLK_PM_CTRL - PHY clock power management control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_MASK   0xfffffffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_SHIFT  1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_DEFAULT 0
+
+/***************************************************************************
+ *PLL_STATUS - PHY PLL status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_MASK    0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_SHIFT   27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK_LOST [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_MASK    0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_SHIFT   26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: DDR_MHZ [25:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_MASK      0x03ffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_SHIFT     14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_4X [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: STATUS [12:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_MASK       0x00001ffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_SHIFT      1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_MASK         0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_CONFIG - PHY PLL configuration register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved0 [31:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_MASK    0xffffff80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_SHIFT   7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LP40_PLL_POST_RESET [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET_POST_DIV [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LDO_CTRL [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_MASK     0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_SHIFT    3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_DEFAULT  2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved1 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_MASK    0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_SHIFT   2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_MASK        0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_SHIFT       1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_DEFAULT     1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PWRDN [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_MASK        0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_SHIFT       0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_DEFAULT     0
+
+/***************************************************************************
+ *PLL_CONTROL - PHY PLL control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: reserved0 [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_SHIFT  31
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_kp [30:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_MASK        0x78000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_SHIFT       27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_DEFAULT     10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ki [26:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_MASK        0x07000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_SHIFT       24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_DEFAULT     3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ka [23:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_MASK        0x00e00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_SHIFT       21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_DEFAULT     3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: PLL_CONTROL [20:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_MASK 0x001fffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_DEFAULT 0
+
+/***************************************************************************
+ *PLL_DIVIDERS - PHY PLL dividers control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_MASK  0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_SHIFT 16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_HI [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_MASK 0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_LO [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: POST_DIV [13:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_MASK   0x00003800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_SHIFT  11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_DEFAULT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: PDIV [10:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_MASK       0x00000700
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_SHIFT      8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_DEFAULT    4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_MASK       0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_DEFAULT    32
+
+/***************************************************************************
+ *AUX_CONTROL - Aux Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved0 [31:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_MASK   0xfffffc00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_SHIFT  10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_cs [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_MASK       0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_SHIFT      7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_ad [06:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_MASK       0x00000070
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_SHIFT      4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_odt [03:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_MASK      0x0000000e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_SHIFT     1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: override [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_CTL - Address & Control coarse VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BIT_CTL - Address & Control fine VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_SHIFT  31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved0 [30:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ffffe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: rxenb [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_MASK  0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved1 [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_SHIFT 7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_reb [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_DEFAULT 0
+
+/***************************************************************************
+ *ZQ_PVT_COMP_CTL - PVT Compensation control and status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: update_mode [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_done [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_done [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_done [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: auto_sample_en [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_MASK 0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_en [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_ovr_en [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_ovr_en [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_comp [17:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_MASK 0x00038000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_comp [14:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_MASK 0x00007000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [11:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_MASK 0x00000e00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [08:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_MASK 0x000001c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_DEFAULT 0
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: auto_oeb [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a15 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_MASK  0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a14 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_MASK  0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a13 [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_MASK  0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_aux [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_MASK  0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: half_strength [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_MASK     0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_SHIFT    2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_MASK  0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_MASK     0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_SHIFT    0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_DEFAULT  0
+
+/***************************************************************************
+ *VDL_RD_DATA_DLY_STATUS - PHY Auto Init rd_data_dly result register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_SHIFT 12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: auto_init_state [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_MASK 0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_max [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_min [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_DEFAULT 7
+
+/***************************************************************************
+ *VDL_CALIBRATE - PHY VDL calibration control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_SHIFT 29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: use_straps [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: auto_init [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: skip_rst [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_MASK  0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_SHIFT 26
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: exit_in_sr [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_dly_cal [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_refresh [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_wr_dq [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: dq0_only [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_MASK  0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_mr_mpr [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_cal [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_MASK   0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_SHIFT  19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_en_cal [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_clocks [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_pair [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_steps [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_auto [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_ftm [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_phybist [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_byte [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_clocks [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_test [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_always [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_once [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_fast [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_DEFAULT 0
+
+/***************************************************************************
+ *VDL_CALIB_STATUS - PHY VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_MASK 0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_fail [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_MASK 0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_SHIFT 29
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_done [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_rd_data_dly_error [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_read_en_error [26:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_MASK 0x07800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_error [22:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_MASK 0x00780000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_sel [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_total [11:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_MASK 0x00000ffc
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_DEFAULT 1
+
+/***************************************************************************
+ *VDL_DQ_CALIB_STATUS - PHY DQ VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_total [25:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_MASK 0x03ff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_clocks [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_mode [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VDL_WR_CHAN_CALIB_STATUS - PHY Write Channel VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VDL_RD_EN_CALIB_STATUS - PHY Read Enable VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: low_vtt [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: high_vtt [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: error_reset [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_ctl_idle [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cs_idle [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cke_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error [18:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_MASK 0x0007fff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_low [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_high [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ready [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_DEFAULT 16777215
+
+/***************************************************************************
+ *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_DEFAULT 262143
+
+/***************************************************************************
+ *VREF_DAC_CONTROL - VREF DAC Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK1_GT_INT [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK0_GT_INT [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_GT_INT [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: EXT_GT_INT [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_TESTOUT_MUX_CTL [16:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_MASK 0x00018000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TEST [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_MASK   0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_SHIFT  14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_MASK   0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_SHIFT  13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_MASK   0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_SHIFT  12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_MASK   0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_SHIFT  6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_DEFAULT 32
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_MASK   0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_SHIFT  0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_DEFAULT 32
+
+/***************************************************************************
+ *PHYBIST_CNTRL - PhyBist Control Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_error_sel [13:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_MASK 0x00003f00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved1 [07:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_MASK 0x000000e0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_SHIFT 5
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: bench_mode [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_dat_error [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_ctl_error [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: int_loopback [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_DEFAULT 0
+
+/***************************************************************************
+ *PHYBIST_SEED - PhyBist Seed Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_SEED :: seed [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_MASK       0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_DEFAULT    621693686
+
+/***************************************************************************
+ *PHYBIST_STATUS - PhyBist General Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_pass [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_pass [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_SHIFT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_done [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_done [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: ctl_errors [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_DQ_STATUS - PhyBist Per-Bit DQ Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_STATUS :: dat_errors [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_MASK 0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_MISC_STATUS - PhyBist Per-Bit DM and CK Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: ck_errors [07:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_MASK 0x000000f0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: dm_errors [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_SHIFT 0
+
+/***************************************************************************
+ *COMMAND_REG - DRAM Command Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_MASK   0xfe000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_SHIFT  25
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: aux [24:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_MASK         0x01c00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_SHIFT        22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: we [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_MASK          0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_SHIFT         21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_DEFAULT       0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: cas [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_MASK         0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_SHIFT        20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ras [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_MASK         0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_SHIFT        19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ba [18:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_MASK          0x00070000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_SHIFT         16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_DEFAULT       0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_MASK          0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_DEFAULT       0
+
+/***************************************************************************
+ *MODE_REG0 - Mode Register 0
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG1 - Mode Register 1
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG2 - Mode Register 2
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG3 - Mode Register 3
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_DEFAULT         0
+
+/***************************************************************************
+ *STANDBY_CONTROL - Standby Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_ready [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_exit_pin_en [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_active [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: armed [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_MASK   0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_SHIFT  15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: warmstart [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_ldo_volts [13:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_MASK 0x00003000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_skip_mrs [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_rst_n [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_cke [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: ldo_volts [08:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_MASK 0x00000180
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_DEFAULT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: skip_mrs [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: rst_n [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_MASK   0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_SHIFT  5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: cke [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_MASK     0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_SHIFT    4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_CONTROL - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: reserved0 [31:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_MASK 0xf0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_MASK       0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_SHIFT      16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_MASK  0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_MASK 0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_MASK     0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_SHIFT    12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_MASK      0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_SHIFT     11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_MASK      0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_SHIFT     8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_CONTROL2 - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_MASK     0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_SHIFT    20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_MASK       0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_SHIFT      17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_MASK       0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_SHIFT      12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_MASK      0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_SHIFT     7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_MASK       0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_DEFAULT    0
+
+/***************************************************************************
+ *STRAP_STATUS - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_MASK  0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_reg [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_MASK   0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_SHIFT  29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_memc [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_MASK  0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_MASK        0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_SHIFT       16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_MASK   0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_SHIFT  14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_MASK      0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_SHIFT     12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_MASK       0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_SHIFT      11
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_SHIFT 10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_MASK       0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_SHIFT      8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_MASK  0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_SHIFT 0
+
+/***************************************************************************
+ *STRAP_STATUS2 - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_MASK      0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_SHIFT     20
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_MASK        0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_SHIFT       17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_MASK        0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_SHIFT       12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_MASK       0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_SHIFT      7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_MASK        0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_SHIFT       0
+
+/***************************************************************************
+ *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl1 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl0 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl1 [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl0 [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_DEFAULT 0
+
+/***************************************************************************
+ *DATAPATH_LOOPBACK - Datapth Loopback control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: xor_dm_rd_en [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: use_addr_ctl [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_DEFAULT 0
+
+#endif /* #ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_ddr40_phy_word_lane_0_0.h b/include/linux/brcmstb/7231b0/bchp_ddr40_phy_word_lane_0_0.h
new file mode 100644
index 0000000..9a0ea8f
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_ddr40_phy_word_lane_0_0.h
@@ -0,0 +1,3334 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:05:58 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_ddr40_phy_word_lane_0_0.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:15p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_0_0 - DDR40 DDR40 word lane #0 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN 0x003b6200 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W 0x003b6204 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P 0x003b6208 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N 0x003b620c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W 0x003b6210 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W 0x003b6214 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W 0x003b6218 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W 0x003b621c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W 0x003b6220 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W 0x003b6224 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W 0x003b6228 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W 0x003b622c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W 0x003b6230 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003b6234 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003b6238 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003b623c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003b6240 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003b6244 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003b6248 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003b624c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003b6250 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003b6254 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003b6258 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003b625c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003b6260 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003b6264 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003b6268 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003b626c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003b6270 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003b6274 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W 0x003b62a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P 0x003b62a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N 0x003b62ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W 0x003b62b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W 0x003b62b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W 0x003b62b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W 0x003b62bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W 0x003b62c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W 0x003b62c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W 0x003b62c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W 0x003b62cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W 0x003b62d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003b62d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003b62d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003b62dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003b62e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003b62e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003b62e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003b62ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003b62f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003b62f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003b62f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003b62fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003b6300 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003b6304 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003b6308 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003b630c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003b6310 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003b6314 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x003b6328 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x003b632c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003b6330 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003b6334 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W 0x003b6338 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003b633c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x003b6348 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x003b634c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003b6350 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003b6354 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W 0x003b6358 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003b635c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY 0x003b6360 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL 0x003b6364 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0 0x003b6370 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1 0x003b6374 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2 0x003b6378 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3 0x003b637c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0 0x003b6380 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1 0x003b6384 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2 0x003b6388 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3 0x003b638c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS 0x003b6390 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR 0x003b6394 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL 0x003b63a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL 0x003b63a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE 0x003b63a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE 0x003b63ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ 0x003b63b0 /* PHYBIST mode VDL step select adjustment register */
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_RD_EN - Read Enable Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *READ_DATA_DLY - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_MASK  0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: rd_data_dly [02:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_MASK 0x00000007
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_DEFAULT 1
+
+/***************************************************************************
+ *READ_CONTROL - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_MASK   0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_SHIFT  3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_enable [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_te_adj [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_le_adj [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_DEFAULT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status1 [07:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_MASK 0x000000f0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status0 [03:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_MASK 0x0000000f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_DEFAULT 0
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: clear [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_DEFAULT 0
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_MASK    0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_SHIFT   31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_SHIFT 24
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_MASK 0x00c00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_SHIFT 22
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_MASK 0x00300000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_SHIFT 20
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00080000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 19
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00040000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_SHIFT 18
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_MASK  0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_MASK  0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00008000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 15
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00004000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 14
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00002000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 13
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00001000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 12
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_MASK 0x00000008
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_DEFAULT 0
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_MASK  0xfffff000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_SHIFT 12
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: no_dqs_rd [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_MASK  0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_MASK    0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_SHIFT   6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_MASK      0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_SHIFT     2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_DEFAULT   0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_MASK   0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_SHIFT  1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_MASK      0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_SHIFT     0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_DEFAULT   0
+
+/***************************************************************************
+ *CLOCK_PAD_DISABLE - Clock pad disable register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_DEFAULT 0
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffc
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_SHIFT 2
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: long [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_MASK    0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_SHIFT   1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: mode [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_DEFAULT 0
+
+/***************************************************************************
+ *PHYBIST_VDL_ADJ - PHYBIST mode VDL step select adjustment register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_SHIFT 29
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq1_vdl_adj [28:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_MASK 0x1f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved1 [23:21] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_MASK 0x00e00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_SHIFT 21
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq0_vdl_adj [20:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_MASK 0x001f0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved2 [15:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_MASK 0x0000e000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_SHIFT 13
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs1_vdl_adj [12:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_MASK 0x00001f00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved3 [07:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_MASK 0x000000e0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_SHIFT 5
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs0_vdl_adj [04:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_MASK 0x0000001f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_DEFAULT 0
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_ddr40_phy_word_lane_1_0.h b/include/linux/brcmstb/7231b0/bchp_ddr40_phy_word_lane_1_0.h
new file mode 100644
index 0000000..8c0f9b9
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_ddr40_phy_word_lane_1_0.h
@@ -0,0 +1,139 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:08:18 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_ddr40_phy_word_lane_1_0.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:15p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_1_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_1_0 - DDR40 DDR40 word lane #1 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN 0x003b6400 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W 0x003b6404 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P 0x003b6408 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N 0x003b640c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W 0x003b6410 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W 0x003b6414 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W 0x003b6418 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W 0x003b641c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W 0x003b6420 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W 0x003b6424 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W 0x003b6428 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W 0x003b642c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W 0x003b6430 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003b6434 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003b6438 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003b643c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003b6440 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003b6444 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003b6448 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003b644c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003b6450 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003b6454 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003b6458 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003b645c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003b6460 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003b6464 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003b6468 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003b646c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003b6470 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003b6474 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W 0x003b64a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P 0x003b64a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N 0x003b64ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W 0x003b64b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W 0x003b64b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W 0x003b64b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W 0x003b64bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W 0x003b64c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W 0x003b64c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W 0x003b64c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W 0x003b64cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W 0x003b64d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003b64d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003b64d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003b64dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003b64e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003b64e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003b64e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003b64ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003b64f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003b64f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003b64f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003b64fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003b6500 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003b6504 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003b6508 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003b650c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003b6510 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003b6514 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x003b6528 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x003b652c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003b6530 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003b6534 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W 0x003b6538 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003b653c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x003b6548 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x003b654c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003b6550 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003b6554 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W 0x003b6558 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003b655c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_DATA_DLY 0x003b6560 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_CONTROL 0x003b6564 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_0 0x003b6570 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_1 0x003b6574 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_2 0x003b6578 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_3 0x003b657c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_0 0x003b6580 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_1 0x003b6584 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_2 0x003b6588 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_3 0x003b658c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_STATUS 0x003b6590 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_CLEAR 0x003b6594 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL 0x003b65a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL 0x003b65a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_CLOCK_PAD_DISABLE 0x003b65a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_WR_PREAMBLE_MODE 0x003b65ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ 0x003b65b0 /* PHYBIST mode VDL step select adjustment register */
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_1_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_ebi.h b/include/linux/brcmstb/7231b0/bchp_ebi.h
new file mode 100644
index 0000000..ab42d3c
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_ebi.h
@@ -0,0 +1,1711 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:15:44 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_ebi.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 5:04p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EBI_H__
+#define BCHP_EBI_H__
+
+/***************************************************************************
+ *EBI - EBI Registers
+ ***************************************************************************/
+#define BCHP_EBI_CS_BASE_0                       0x00410800 /* EBI CS Base 0 Register */
+#define BCHP_EBI_CS_CONFIG_0                     0x00410804 /* EBI CS Config 0 Register */
+#define BCHP_EBI_CS_BASE_1                       0x00410808 /* EBI CS Base 1 Register */
+#define BCHP_EBI_CS_CONFIG_1                     0x0041080c /* EBI CS Config 1 Register */
+#define BCHP_EBI_CS_BASE_2                       0x00410810 /* EBI CS Base 2 Register */
+#define BCHP_EBI_CS_CONFIG_2                     0x00410814 /* EBI CS Config 2 Register */
+#define BCHP_EBI_CS_BASE_3                       0x00410818 /* EBI CS Base 3 Register */
+#define BCHP_EBI_CS_CONFIG_3                     0x0041081c /* EBI CS Config 3 Register */
+#define BCHP_EBI_CS_BASE_4                       0x00410820 /* EBI CS Base 4 Register */
+#define BCHP_EBI_CS_CONFIG_4                     0x00410824 /* EBI CS Config 4 Register */
+#define BCHP_EBI_CS_BASE_5                       0x00410828 /* EBI CS Base 5 Register */
+#define BCHP_EBI_CS_CONFIG_5                     0x0041082c /* EBI CS Config 5 Register */
+#define BCHP_EBI_BURST_CFG_0                     0x00410840 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_1                     0x00410844 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_2                     0x00410848 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_3                     0x0041084c /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_4                     0x00410850 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_5                     0x00410854 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_ECR                             0x00410900 /* EBI Configuration Register */
+#define BCHP_EBI_CS_TRISTATE_CFG                 0x00410918 /* EBI CS Tristate Configuration Register */
+#define BCHP_EBI_TA_CFG                          0x0041091c /* EBI TA Configuration Register */
+#define BCHP_EBI_CS_SPI_SELECT                   0x00410920 /* SPI CS Select */
+#define BCHP_EBI_ARRAY_ADDRESS                   0x004109f0 /* EBI Data Array Address */
+
+/***************************************************************************
+ *CS_BASE_0 - EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_0 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_0_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT                         13
+
+/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_0_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_0 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_0_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_0_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_0 - EBI CS Config 0 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_0_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT                       1
+
+/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_0_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_0 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_0_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_0_le_SHIFT                              10
+
+/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_0_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_0_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT                       4
+
+/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_0_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT                        1
+
+/***************************************************************************
+ *CS_BASE_1 - EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_1 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_1_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_1_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_1 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_1_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_1_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_1_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_1 - EBI CS Config 1 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_1_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_1_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_1 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_1_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_1_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_1_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_1_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_1_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_2 - EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_2 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_2_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_2_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_2 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_2_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_2_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_2_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_2 - EBI CS Config 2 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_2_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_2_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_2 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_2_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_2_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_2_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_2_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_2_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_3 - EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_3 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_3_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_3_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_3 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_3_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_3_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_3_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_3 - EBI CS Config 3 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_3_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_3_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_3 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_3_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_3_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_3_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_3_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_3_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_4 - EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_4 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_4_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_4_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_4 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_4_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_4_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_4_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_4 - EBI CS Config 4 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_4_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_4_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_4 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_4_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_4_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_4_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_4_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_4_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_5 - EBI CS Base 5 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_5 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_5_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_5_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_5_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_5 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_5_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_5_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_5 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_5_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_5_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_5_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_5_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_5_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_5_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_5_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_5 - EBI CS Config 5 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_5 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_5_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_5_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_5_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_5_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_5_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_5_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_5 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_5_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_5_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_5_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_5 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_5_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_5_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_5_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_5_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_5_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_5_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_5_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_5_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_5_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_5 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_5_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_5_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_5_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_5 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_5_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_5_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_5_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_5 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_5_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_5_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_5_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_5 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_5_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_5_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_5_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_5 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_5_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_5_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_5_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_5 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_5_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_5_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_5_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_5 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_5_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_5_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_5_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_5 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_5_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_5_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_5_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_5 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_5_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_5_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_5_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_5_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_5_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_5_enable_DEFAULT                        0
+
+/***************************************************************************
+ *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_0_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_0_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_0 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_0_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_0_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_0_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_0_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_0_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_1_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_1_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_1 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_1_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_1_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_1_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_1_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_1_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_2_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_2_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_2 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_2_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_2_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_2_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_2_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_2_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_3_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_3_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_3 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_3_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_3_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_3_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_3_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_3_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_4_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_4_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_4 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_4_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_4_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_4_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_4_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_4_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_5 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_5 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_5 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_5_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_5_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_5_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_5 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_5 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_5 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_5 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_5_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_5_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_5 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_5 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_5_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_5_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_5_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_5 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_5 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_5 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_5_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_5_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_5 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_5_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_5_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_5_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_5 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_5_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_5_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_5 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_5_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_5_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_5_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_5 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_5_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_5_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_5_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *ECR - EBI Configuration Register
+ ***************************************************************************/
+/* EBI :: ECR :: reserved0 [31:28] */
+#define BCHP_EBI_ECR_reserved0_MASK                                0xf0000000
+#define BCHP_EBI_ECR_reserved0_SHIFT                               28
+
+/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK                            0x08000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT                           27
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT                         0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only  1
+
+/* EBI :: ECR :: reserved1 [26:26] */
+#define BCHP_EBI_ECR_reserved1_MASK                                0x04000000
+#define BCHP_EBI_ECR_reserved1_SHIFT                               26
+
+/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK                          0x02000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT                         25
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT                       0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10         0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00         1
+
+/* EBI :: ECR :: reserved2 [24:11] */
+#define BCHP_EBI_ECR_reserved2_MASK                                0x01fff800
+#define BCHP_EBI_ECR_reserved2_SHIFT                               11
+
+/* EBI :: ECR :: timeout_count [10:00] */
+#define BCHP_EBI_ECR_timeout_count_MASK                            0x000007ff
+#define BCHP_EBI_ECR_timeout_count_SHIFT                           0
+#define BCHP_EBI_ECR_timeout_count_DEFAULT                         1024
+
+/***************************************************************************
+ *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
+ ***************************************************************************/
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK             0x80000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT            31
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK             0x40000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT            30
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK             0x20000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT            29
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK             0x10000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT            28
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK            0x08000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT           27
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT         0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK            0x04000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT           26
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT         0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK         0x02000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT        25
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT      0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK         0x01000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT        24
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT      0
+
+/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:06] */
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK                    0x00ffffc0
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT                   6
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs5 [05:05] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_MASK             0x00000020
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_SHIFT            5
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK             0x00000010
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT            4
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK             0x00000008
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT            3
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK             0x00000004
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT            2
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK             0x00000002
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT            1
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK             0x00000001
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT            0
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT          0
+
+/***************************************************************************
+ *TA_CFG - EBI TA Configuration Register
+ ***************************************************************************/
+/* EBI :: TA_CFG :: reserved0 [31:04] */
+#define BCHP_EBI_TA_CFG_reserved0_MASK                             0xfffffff0
+#define BCHP_EBI_TA_CFG_reserved0_SHIFT                            4
+
+/* EBI :: TA_CFG :: use_ta3 [03:03] */
+#define BCHP_EBI_TA_CFG_use_ta3_MASK                               0x00000008
+#define BCHP_EBI_TA_CFG_use_ta3_SHIFT                              3
+#define BCHP_EBI_TA_CFG_use_ta3_DEFAULT                            1
+
+/* EBI :: TA_CFG :: use_ta2 [02:02] */
+#define BCHP_EBI_TA_CFG_use_ta2_MASK                               0x00000004
+#define BCHP_EBI_TA_CFG_use_ta2_SHIFT                              2
+#define BCHP_EBI_TA_CFG_use_ta2_DEFAULT                            0
+
+/* EBI :: TA_CFG :: use_ta1 [01:01] */
+#define BCHP_EBI_TA_CFG_use_ta1_MASK                               0x00000002
+#define BCHP_EBI_TA_CFG_use_ta1_SHIFT                              1
+#define BCHP_EBI_TA_CFG_use_ta1_DEFAULT                            1
+
+/* EBI :: TA_CFG :: reserved1 [00:00] */
+#define BCHP_EBI_TA_CFG_reserved1_MASK                             0x00000001
+#define BCHP_EBI_TA_CFG_reserved1_SHIFT                            0
+
+/***************************************************************************
+ *CS_SPI_SELECT - SPI CS Select
+ ***************************************************************************/
+/* EBI :: CS_SPI_SELECT :: reserved0 [31:16] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK                      0xffff0000
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT                     16
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_7_USES_SPI [15:15] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_MASK              0x00008000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_SHIFT             15
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK              0x00004000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT             14
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK              0x00002000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT             13
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK              0x00001000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT             12
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK              0x00000800
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT             11
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK              0x00000400
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT             10
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK              0x00000200
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT             9
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK              0x00000100
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT             8
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_7_SEL [07:07] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_MASK               0x00000080
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_SHIFT              7
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK               0x00000040
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT              6
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK               0x00000020
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT              5
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK               0x00000010
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT              4
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK               0x00000008
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT              3
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK               0x00000004
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT              2
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK               0x00000002
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT              1
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK               0x00000001
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT              0
+
+/***************************************************************************
+ *ARRAY_ADDRESS - EBI Data Array Address
+ ***************************************************************************/
+/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK                        0xfffffe00
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT                       9
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT                     0
+
+/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK                      0x000001f8
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT                     3
+
+/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK                         0x00000007
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT                        0
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT                      0
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE                            0x00410a00
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_START                           0
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_END                             127
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE                    32
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+/* EBI :: DATA_ARRAYi :: WORD [31:00] */
+#define BCHP_EBI_DATA_ARRAYi_WORD_MASK                             0xffffffff
+#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT                            0
+
+
+#endif /* #ifndef BCHP_EBI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_hif_cpu_intr1.h b/include/linux/brcmstb/7231b0/bchp_hif_cpu_intr1.h
new file mode 100644
index 0000000..74610c0
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_hif_cpu_intr1.h
@@ -0,0 +1,1855 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:28:18 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_hif_cpu_intr1.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 5:32p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_INTR1_H__
+#define BCHP_HIF_CPU_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_INTR1 - HIF CPU Thread Processor 0 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS        0x00411400 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS        0x00411404 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS        0x00411408 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS   0x0041140c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS   0x00411410 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS   0x00411414 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET      0x00411418 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET      0x0041141c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET      0x00411420 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR    0x00411424 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR    0x00411428 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR    0x0041142c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK    0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT   31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK        0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT       30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK    0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT   29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_MASK        0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_SHIFT       28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_MASK  0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_MASK  0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK  0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK  0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_MASK        0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_SHIFT       23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK     0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT    7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK     0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT    6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK     0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT    5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK     0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT    4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK     0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT    3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK     0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT    2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK        0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT       1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK        0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT       0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT     0
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK    0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT   31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK     0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT    29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK    0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT   25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_MASK        0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_SHIFT       22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK     0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT    21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK    0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT   20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK        0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT       19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_MASK     0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_SHIFT    18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_MASK  0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_MASK  0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_MASK  0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_MASK  0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_MASK  0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK      0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT     5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT   0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK    0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT   4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_MASK       0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_SHIFT      3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_DEFAULT    0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_MASK      0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_SHIFT     2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_DEFAULT   0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_MASK       0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_SHIFT      1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_DEFAULT    0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_MASK       0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_SHIFT      0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_DEFAULT    0
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved0_MASK           0xff800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved0_SHIFT          23
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_MASK     0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_SHIFT    22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_MASK    0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_SHIFT   21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK    0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT   19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK    0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT   18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK   0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT  17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK    0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT   15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK     0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT    14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK        0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT       13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK   0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT  30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_MASK   0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_SHIFT  28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_MASK   0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_SHIFT  23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_MASK   0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_SHIFT  22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_MASK  0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved0_MASK      0xff800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved0_SHIFT     23
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK   0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT  13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK      0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT     30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_MASK      0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_SHIFT     28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_MASK      0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_SHIFT     23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK      0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT     1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK      0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT     0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT   1
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK   0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT  29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK  0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_MASK  0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_MASK      0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_SHIFT     22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK   0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT  21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK  0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK      0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT     19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_MASK   0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_SHIFT  18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK    0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT   5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK  0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_MASK     0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_SHIFT    3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_DEFAULT  1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_MASK    0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_SHIFT   2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_MASK     0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_SHIFT    1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_DEFAULT  1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_MASK     0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_SHIFT    0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_DEFAULT  1
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved0_MASK         0xff800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved0_SHIFT        23
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_MASK   0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_SHIFT  22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_MASK  0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK  0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK  0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK  0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK   0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT  14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK      0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT     13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_MASK    0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_SHIFT   28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_MASK    0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_SHIFT   22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK    0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT   19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK  0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved0_MASK       0xff800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved0_SHIFT      23
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK    0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT   13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 1
+
+#endif /* #ifndef BCHP_HIF_CPU_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_hif_cpu_tp1_intr1.h b/include/linux/brcmstb/7231b0/bchp_hif_cpu_tp1_intr1.h
new file mode 100644
index 0000000..b5422a1
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_hif_cpu_tp1_intr1.h
@@ -0,0 +1,1855 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:20:13 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_hif_cpu_tp1_intr1.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 5:33p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_TP1_INTR1_H__
+#define BCHP_HIF_CPU_TP1_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_TP1_INTR1 - HIF CPU Thread Processor 1 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS    0x00411600 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS    0x00411604 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS    0x00411608 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS 0x0041160c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS 0x00411610 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS 0x00411614 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET  0x00411618 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET  0x0041161c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET  0x00411620 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR 0x00411624 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR 0x00411628 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR 0x0041162c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_MASK    0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_SHIFT   28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_MASK    0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_SHIFT   22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK    0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT   19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK  0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_reserved0_MASK       0xff800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_reserved0_SHIFT      23
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK    0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT   13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_reserved0_MASK  0xff800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_reserved0_SHIFT 23
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_MASK  0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_MASK  0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK  0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_reserved0_MASK     0xff800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_reserved0_SHIFT    23
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK  0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_reserved0_MASK   0xff800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_reserved0_SHIFT  23
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 1
+
+#endif /* #ifndef BCHP_HIF_CPU_TP1_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_hif_intr2.h b/include/linux/brcmstb/7231b0/bchp_hif_intr2.h
new file mode 100644
index 0000000..d496a46
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_hif_intr2.h
@@ -0,0 +1,975 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:22:43 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_hif_intr2.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 5:34p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_INTR2_H__
+#define BCHP_HIF_INTR2_H__
+
+/***************************************************************************
+ *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_INTR2_CPU_STATUS                0x00411000 /* CPU interrupt Status Register */
+#define BCHP_HIF_INTR2_CPU_SET                   0x00411004 /* CPU interrupt Set Register */
+#define BCHP_HIF_INTR2_CPU_CLEAR                 0x00411008 /* CPU interrupt Clear Register */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS           0x0041100c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_CPU_MASK_SET              0x00411010 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR            0x00411014 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_INTR2_PCI_STATUS                0x00411018 /* PCI interrupt Status Register */
+#define BCHP_HIF_INTR2_PCI_SET                   0x0041101c /* PCI interrupt Set Register */
+#define BCHP_HIF_INTR2_PCI_CLEAR                 0x00411020 /* PCI interrupt Clear Register */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS           0x00411024 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_PCI_MASK_SET              0x00411028 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR            0x0041102c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK                   0x0000fffe
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT               0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_MASK              0x00080000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_SHIFT             19
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: CPU_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK                      0x0000fffe
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: CPU_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_MASK            0x00080000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_SHIFT           19
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK                    0x0000fffe
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK              0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 1
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT          1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_MASK         0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_SHIFT        19
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK                 0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    1
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_MASK       0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_SHIFT      19
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK               0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  1
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK                   0x0000fffe
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT               0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_MASK              0x00080000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_SHIFT             19
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: PCI_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK                      0x0000fffe
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: PCI_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_MASK            0x00080000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_SHIFT           19
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK                    0x0000fffe
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK              0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 1
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT          1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_MASK         0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_SHIFT        19
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK                 0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    1
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_MASK       0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_SHIFT      19
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK               0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  1
+
+#endif /* #ifndef BCHP_HIF_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_hif_mspi.h b/include/linux/brcmstb/7231b0/bchp_hif_mspi.h
new file mode 100644
index 0000000..5a6fd9b
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_hif_mspi.h
@@ -0,0 +1,1214 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:24:34 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_hif_mspi.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 5:35p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_MSPI_H__
+#define BCHP_HIF_MSPI_H__
+
+/***************************************************************************
+ *HIF_MSPI - Public MSPI Registers
+ ***************************************************************************/
+#define BCHP_HIF_MSPI_SPCR0_LSB                  0x00413200 /* SPCR0_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR0_MSB                  0x00413204 /* SPCR0_MSB Register */
+#define BCHP_HIF_MSPI_SPCR1_LSB                  0x00413208 /* SPCR1_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR1_MSB                  0x0041320c /* SPCR1_MSB REGISTER */
+#define BCHP_HIF_MSPI_NEWQP                      0x00413210 /* NEWQP REGISTER */
+#define BCHP_HIF_MSPI_ENDQP                      0x00413214 /* ENDQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR2                      0x00413218 /* SPCR2 REGISTER */
+#define BCHP_HIF_MSPI_MSPI_STATUS                0x00413220 /* MSPI STATUS REGISTER */
+#define BCHP_HIF_MSPI_CPTQP                      0x00413224 /* CPTQP REGISTER */
+#define BCHP_HIF_MSPI_TXRAM00                    0x00413240 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM01                    0x00413244 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM02                    0x00413248 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM03                    0x0041324c /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM04                    0x00413250 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM05                    0x00413254 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM06                    0x00413258 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM07                    0x0041325c /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM08                    0x00413260 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM09                    0x00413264 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM10                    0x00413268 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM11                    0x0041326c /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM12                    0x00413270 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM13                    0x00413274 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM14                    0x00413278 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM15                    0x0041327c /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM16                    0x00413280 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM17                    0x00413284 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM18                    0x00413288 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM19                    0x0041328c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM20                    0x00413290 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM21                    0x00413294 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM22                    0x00413298 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM23                    0x0041329c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM24                    0x004132a0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM25                    0x004132a4 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM26                    0x004132a8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM27                    0x004132ac /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM28                    0x004132b0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM29                    0x004132b4 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM30                    0x004132b8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_TXRAM31                    0x004132bc /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM00                    0x004132c0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM01                    0x004132c4 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM02                    0x004132c8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM03                    0x004132cc /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM04                    0x004132d0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM05                    0x004132d4 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM06                    0x004132d8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM07                    0x004132dc /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM08                    0x004132e0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM09                    0x004132e4 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM10                    0x004132e8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM11                    0x004132ec /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM12                    0x004132f0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM13                    0x004132f4 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM14                    0x004132f8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM15                    0x004132fc /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM16                    0x00413300 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM17                    0x00413304 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM18                    0x00413308 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM19                    0x0041330c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM20                    0x00413310 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM21                    0x00413314 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM22                    0x00413318 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM23                    0x0041331c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM24                    0x00413320 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM25                    0x00413324 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM26                    0x00413328 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM27                    0x0041332c /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM28                    0x00413330 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM29                    0x00413334 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM30                    0x00413338 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM31                    0x0041333c /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_CDRAM00                    0x00413340 /* 8-bit command (queue pointer = 0) */
+#define BCHP_HIF_MSPI_CDRAM01                    0x00413344 /* 8-bit command (queue pointer = 1) */
+#define BCHP_HIF_MSPI_CDRAM02                    0x00413348 /* 8-bit command (queue pointer = 2) */
+#define BCHP_HIF_MSPI_CDRAM03                    0x0041334c /* 8-bit command (queue pointer = 3) */
+#define BCHP_HIF_MSPI_CDRAM04                    0x00413350 /* 8-bit command (queue pointer = 4) */
+#define BCHP_HIF_MSPI_CDRAM05                    0x00413354 /* 8-bit command (queue pointer = 5) */
+#define BCHP_HIF_MSPI_CDRAM06                    0x00413358 /* 8-bit command (queue pointer = 6) */
+#define BCHP_HIF_MSPI_CDRAM07                    0x0041335c /* 8-bit command (queue pointer = 7) */
+#define BCHP_HIF_MSPI_CDRAM08                    0x00413360 /* 8-bit command (queue pointer = 8) */
+#define BCHP_HIF_MSPI_CDRAM09                    0x00413364 /* 8-bit command (queue pointer = 9) */
+#define BCHP_HIF_MSPI_CDRAM10                    0x00413368 /* 8-bit command (queue pointer = a) */
+#define BCHP_HIF_MSPI_CDRAM11                    0x0041336c /* 8-bit command (queue pointer = b) */
+#define BCHP_HIF_MSPI_CDRAM12                    0x00413370 /* 8-bit command (queue pointer = c) */
+#define BCHP_HIF_MSPI_CDRAM13                    0x00413374 /* 8-bit command (queue pointer = d) */
+#define BCHP_HIF_MSPI_CDRAM14                    0x00413378 /* 8-bit command (queue pointer = e) */
+#define BCHP_HIF_MSPI_CDRAM15                    0x0041337c /* 8-bit command (queue pointer = f) */
+#define BCHP_HIF_MSPI_WRITE_LOCK                 0x00413380 /* Control bit to lock group of write commands */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN          0x00413384 /* Debug bit to mask the generation of flush signals from Mspi */
+
+/***************************************************************************
+ *SPCR0_LSB - SPCR0_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK                          0x000000ff
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT                       0
+
+/***************************************************************************
+ *SPCR0_MSB - SPCR0_MSB Register
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_MSB :: MSTR [07:07] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_MASK                          0x00000080
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_SHIFT                         7
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_DEFAULT                       1
+
+/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [06:06] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK               0x00000040
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT              6
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT            0
+
+/* HIF_MSPI :: SPCR0_MSB :: BitS [05:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_MASK                          0x0000003c
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_SHIFT                         2
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_DEFAULT                       0
+
+/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK                          0x00000002
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT                         1
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT                       0
+
+/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK                          0x00000001
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT                       0
+
+/***************************************************************************
+ *SPCR1_LSB - SPCR1_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT                          0
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT                        0
+
+/***************************************************************************
+ *SPCR1_MSB - SPCR1_MSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK                        0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT                       0
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT                     0
+
+/***************************************************************************
+ *NEWQP - NEWQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: NEWQP :: newqp [03:00] */
+#define BCHP_HIF_MSPI_NEWQP_newqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT                            0
+#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT                          0
+
+/***************************************************************************
+ *ENDQP - ENDQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: ENDQP :: endqp [03:00] */
+#define BCHP_HIF_MSPI_ENDQP_endqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT                            0
+#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT                          0
+
+/***************************************************************************
+ *SPCR2 - SPCR2 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK                         0xffffff00
+#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT                        8
+
+/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK                    0x00000080
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT                   7
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT                 0
+
+/* HIF_MSPI :: SPCR2 :: spe [06:06] */
+#define BCHP_HIF_MSPI_SPCR2_spe_MASK                               0x00000040
+#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT                              6
+#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT                            0
+
+/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
+#define BCHP_HIF_MSPI_SPCR2_spifie_MASK                            0x00000020
+#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT                           5
+#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT                         0
+
+/* HIF_MSPI :: SPCR2 :: wren [04:04] */
+#define BCHP_HIF_MSPI_SPCR2_wren_MASK                              0x00000010
+#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT                             4
+#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT                           0
+
+/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
+#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK                              0x00000008
+#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT                             3
+#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT                           0
+
+/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
+#define BCHP_HIF_MSPI_SPCR2_loopq_MASK                             0x00000004
+#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT                            2
+#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT                          0
+
+/* HIF_MSPI :: SPCR2 :: hie [01:01] */
+#define BCHP_HIF_MSPI_SPCR2_hie_MASK                               0x00000002
+#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT                              1
+#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT                            0
+
+/* HIF_MSPI :: SPCR2 :: halt [00:00] */
+#define BCHP_HIF_MSPI_SPCR2_halt_MASK                              0x00000001
+#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT                             0
+#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT                           0
+
+/***************************************************************************
+ *MSPI_STATUS - MSPI STATUS REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK                   0xfffffffc
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT                  2
+
+/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK                       0x00000002
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT                      1
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT                    0
+
+/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK                        0x00000001
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT                       0
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT                     0
+
+/***************************************************************************
+ *CPTQP - CPTQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
+#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT                            0
+#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT                          0
+
+/***************************************************************************
+ *TXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM00_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM01_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM02_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM03_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM04_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM05_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM06_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM07_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM08_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM09_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM10_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM11_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM12_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM13_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM14_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM15_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM16_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM17_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM18_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM19_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM20_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM21_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM22_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM23_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM24_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM25_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM26_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM27_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM28_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM29_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM30_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM31_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM00 - 8-bit command (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM00 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM01 - 8-bit command (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM01 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM02 - 8-bit command (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM02 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM03 - 8-bit command (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM03 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM04 - 8-bit command (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM04 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM05 - 8-bit command (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM05 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM06 - 8-bit command (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM06 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM07 - 8-bit command (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM07 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM08 - 8-bit command (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM08 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM09 - 8-bit command (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM09 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM10 - 8-bit command (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM10 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM11 - 8-bit command (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM11 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM12 - 8-bit command (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM12 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM13 - 8-bit command (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM13 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM14 - 8-bit command (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM14 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM15 - 8-bit command (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM15 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT                          0
+
+/***************************************************************************
+ *WRITE_LOCK - Control bit to lock group of write commands
+ ***************************************************************************/
+/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK                    0xfffffffe
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT                   1
+
+/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK                    0x00000001
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT                   0
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT                 0
+
+/***************************************************************************
+ *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
+ ***************************************************************************/
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK             0xfffffffe
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT            1
+
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK       0x00000001
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT      0
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT    0
+
+#endif /* #ifndef BCHP_HIF_MSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/7231b0/bchp_hif_spi_intr2.h
new file mode 100644
index 0000000..f9e6822
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_hif_spi_intr2.h
@@ -0,0 +1,567 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:11:55 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_hif_spi_intr2.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 5:39p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_SPI_INTR2_H__
+#define BCHP_HIF_SPI_INTR2_H__
+
+/***************************************************************************
+ *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
+ ***************************************************************************/
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS            0x00411d00 /* CPU interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_SET               0x00411d04 /* CPU interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR             0x00411d08 /* CPU interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS       0x00411d0c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET          0x00411d10 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR        0x00411d14 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS            0x00411d18 /* PCI interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_SET               0x00411d1c /* PCI interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR             0x00411d20 /* PCI interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS       0x00411d24 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET          0x00411d28 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR        0x00411d2c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT            0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT               0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT         0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT           0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT            0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT               0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT         0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT           0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_hif_top_ctrl.h b/include/linux/brcmstb/7231b0/bchp_hif_top_ctrl.h
new file mode 100644
index 0000000..ae9c838
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_hif_top_ctrl.h
@@ -0,0 +1,530 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:11:47 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_hif_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:19p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_TOP_CTRL_H__
+#define BCHP_HIF_TOP_CTRL_H__
+
+/***************************************************************************
+ *HIF_TOP_CTRL - HIF Top Control Registers
+ ***************************************************************************/
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL          0x00412400 /* External IRQ Active Level Control Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0               0x00412404 /* HIF Power Management Control0 Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1               0x00412408 /* HIF Power Management Control1 Register */
+#define BCHP_HIF_TOP_CTRL_SCRATCH                0x0041240c /* HIF Scratch Register */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE             0x00412410 /* HIF Decoded Flash Type */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL            0x00412414 /* SPI test port select register */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL               0x0041241c /* HIF HIF_CTRL Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2               0x00412418 /* HIF Power Management Control Register:used to control SDIO_0 (CARD) */
+
+/***************************************************************************
+ *EXT_IRQ_LEVEL - External IRQ Active Level Control Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: reserved0 [31:15] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_MASK             0xffff8000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_SHIFT            15
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_14_level [14:14] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_MASK      0x00004000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_SHIFT     14
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_13_level [13:13] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_MASK      0x00002000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_SHIFT     13
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_12_level [12:12] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_MASK      0x00001000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_SHIFT     12
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_11_level [11:11] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_MASK      0x00000800
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_SHIFT     11
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_10_level [10:10] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_MASK      0x00000400
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_SHIFT     10
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_09_level [09:09] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_MASK      0x00000200
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_SHIFT     9
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_08_level [08:08] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_MASK      0x00000100
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_SHIFT     8
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_07_level [07:07] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_MASK      0x00000080
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_SHIFT     7
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_06_level [06:06] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_MASK      0x00000040
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_SHIFT     6
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_05_level [05:05] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_MASK      0x00000020
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_SHIFT     5
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_04_level [04:04] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_MASK      0x00000010
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_03_level [03:03] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_MASK      0x00000008
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_SHIFT     3
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_02_level [02:02] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_MASK      0x00000004
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_SHIFT     2
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_01_level [01:01] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_MASK      0x00000002
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_SHIFT     1
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_00_level [00:00] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_MASK      0x00000001
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_SHIFT     0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_HIGH      1
+
+/***************************************************************************
+ *PM_CTRL0 - HIF Power Management Control0 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_PM_IN_DRIVE_INACTIVE [31:30] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_MASK   0xc0000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_SHIFT  30
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_IN_DRIVE_INACTIVE [29:28] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x30000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 28
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: reserved0 [27:26] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_reserved0_MASK                  0x0c000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_reserved0_SHIFT                 26
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_DATA_PM_OUT_CTRL [25:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_MASK       0x03000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_SHIFT      24
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_ADDR_PM_OUT_CTRL [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_MASK       0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_SHIFT      22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_CTRL_PM_OUT_CTRL [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_MASK       0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_SHIFT      20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_OUT_CTRL [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_MASK      0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_SHIFT     18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_CTRL_PM_OUT_CTRL [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_MASK      0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_SHIFT     16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS7 [15:14] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_MASK            0x0000c000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_SHIFT           14
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS6 [13:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_MASK            0x00003000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_SHIFT           12
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS5 [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_MASK            0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_SHIFT           10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS4 [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_MASK            0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_SHIFT           8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS3 [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_MASK            0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_SHIFT           6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS2 [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_MASK            0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_SHIFT           4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS1 [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_MASK            0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_SHIFT           2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS0 [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_MASK            0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_SHIFT           0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_Tristate        3
+
+/***************************************************************************
+ *PM_CTRL1 - HIF Power Management Control1 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL1 :: reserved0 [31:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_MASK                  0xfffff000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_PM_IN_DRIVE_INACTIVE [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_WPB_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_MASK        0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_SHIFT       8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_DEFAULT     0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_Tristate    3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_HOLDB_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_MASK      0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_SHIFT     6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MISO_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_MASK       0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_SHIFT      4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MOSI_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_MASK        0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_SHIFT       0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_DEFAULT     0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_Tristate    3
+
+/***************************************************************************
+ *SCRATCH - HIF Scratch Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_MASK                 0xffffffff
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_SHIFT                0
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_DEFAULT              0
+
+/***************************************************************************
+ *FLASH_TYPE - HIF Decoded Flash Type
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: FLASH_TYPE :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_MASK                0xfffffff8
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_SHIFT               3
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: InvalidStrap [02:02] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_MASK             0x00000004
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_SHIFT            2
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_DEFAULT          0
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: FLASH_TYPE [01:00] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_MASK               0x00000003
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SHIFT              0
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_ParallelNOR        0
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_Nand               1
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SerialNOR          2
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_UnSupport          3
+
+/***************************************************************************
+ *SPI_DBG_SEL - SPI test port select register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_MASK               0xfffffff8
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_SHIFT              3
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: DISABLE_MSPI_FLUSH [02:02] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_MASK      0x00000004
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_SHIFT     2
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_DEFAULT   0
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SPI_RBUS_TIMER_EN [01:01] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_MASK       0x00000002
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_SHIFT      1
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_DEFAULT    0
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SDIO_TP_SEL [00:00] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SDIO_TP_SEL_MASK             0x00000001
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SDIO_TP_SEL_SHIFT            0
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SDIO_TP_SEL_DEFAULT          0
+
+/***************************************************************************
+ *HIF_CTRL - HIF HIF_CTRL Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: HIF_CTRL :: reserved0 [31:01] */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_reserved0_SHIFT                 1
+
+/* HIF_TOP_CTRL :: HIF_CTRL :: ENABLE_FULL_USE_OF_EBI [00:00] */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_MASK     0x00000001
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_SHIFT    0
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_DEFAULT  0
+
+/***************************************************************************
+ *PM_CTRL2 - HIF Power Management Control Register:used to control SDIO_0 (CARD)
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved0 [31:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_MASK                  0xff000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_SHIFT                 24
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_MASK 0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_SHIFT 22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_MASK 0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_SHIFT 20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_IN_DRIVE_INACTIVE [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_IN_DRIVE_INACTIVE [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_MASK 0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_SHIFT 16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved1 [15:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_MASK                  0x0000f000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_VOLTAGE_PM_OUT_CTRL [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_LOW    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_HIGH   2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_POWER_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_MASK     0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_SHIFT    8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_DEFAULT  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_LOW      1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_HIGH     2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_LED_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_MASK       0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_SHIFT      6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_MASK      0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_MASK       0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_SHIFT      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_Tristate   3
+
+#endif /* #ifndef BCHP_HIF_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_irq0.h b/include/linux/brcmstb/7231b0/bchp_irq0.h
new file mode 100644
index 0000000..6a133b3
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_irq0.h
@@ -0,0 +1,217 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:14:45 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_irq0.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 6:11p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ0_H__
+#define BCHP_IRQ0_H__
+
+/***************************************************************************
+ *IRQ0 - Level 2 CPU Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ0_IRQEN                          0x00406780 /* Interrupt Enable */
+#define BCHP_IRQ0_IRQSTAT                        0x00406784 /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ0 :: IRQEN :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQEN_reserved0_MASK                             0xf8000000
+#define BCHP_IRQ0_IRQEN_reserved0_SHIFT                            27
+
+/* IRQ0 :: IRQEN :: iicc_irqen [26:26] */
+#define BCHP_IRQ0_IRQEN_iicc_irqen_MASK                            0x04000000
+#define BCHP_IRQ0_IRQEN_iicc_irqen_SHIFT                           26
+#define BCHP_IRQ0_IRQEN_iicc_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: iicb_irqen [25:25] */
+#define BCHP_IRQ0_IRQEN_iicb_irqen_MASK                            0x02000000
+#define BCHP_IRQ0_IRQEN_iicb_irqen_SHIFT                           25
+#define BCHP_IRQ0_IRQEN_iicb_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: iica_irqen [24:24] */
+#define BCHP_IRQ0_IRQEN_iica_irqen_MASK                            0x01000000
+#define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT                           24
+#define BCHP_IRQ0_IRQEN_iica_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQEN_reserved1_MASK                             0x00f80000
+#define BCHP_IRQ0_IRQEN_reserved1_SHIFT                            19
+
+/* IRQ0 :: IRQEN :: uartc_irqen [18:18] */
+#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK                           0x00040000
+#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT                          18
+#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: uartb_irqen [17:17] */
+#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK                           0x00020000
+#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT                          17
+#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: uarta_irqen [16:16] */
+#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK                           0x00010000
+#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT                          16
+#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQEN_reserved2_MASK                             0x0000fc00
+#define BCHP_IRQ0_IRQEN_reserved2_SHIFT                            10
+
+/* IRQ0 :: IRQEN :: uc_irqen [09:09] */
+#define BCHP_IRQ0_IRQEN_uc_irqen_MASK                              0x00000200
+#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT                             9
+#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQEN_reserved3_MASK                             0x00000180
+#define BCHP_IRQ0_IRQEN_reserved3_SHIFT                            7
+
+/* IRQ0 :: IRQEN :: gio_irqen [06:06] */
+#define BCHP_IRQ0_IRQEN_gio_irqen_MASK                             0x00000040
+#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT                            6
+#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT                          0
+
+/* IRQ0 :: IRQEN :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQEN_reserved4_MASK                             0x00000020
+#define BCHP_IRQ0_IRQEN_reserved4_SHIFT                            5
+
+/* IRQ0 :: IRQEN :: ua_irqen [04:04] */
+#define BCHP_IRQ0_IRQEN_ua_irqen_MASK                              0x00000010
+#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT                             4
+#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: ub_irqen [03:03] */
+#define BCHP_IRQ0_IRQEN_ub_irqen_MASK                              0x00000008
+#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT                             3
+#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: irb_irqen [02:02] */
+#define BCHP_IRQ0_IRQEN_irb_irqen_MASK                             0x00000004
+#define BCHP_IRQ0_IRQEN_irb_irqen_SHIFT                            2
+#define BCHP_IRQ0_IRQEN_irb_irqen_DEFAULT                          0
+
+/* IRQ0 :: IRQEN :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQEN_reserved5_MASK                             0x00000003
+#define BCHP_IRQ0_IRQEN_reserved5_SHIFT                            0
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ0 :: IRQSTAT :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQSTAT_reserved0_MASK                           0xf8000000
+#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT                          27
+
+/* IRQ0 :: IRQSTAT :: iiccirq [26:26] */
+#define BCHP_IRQ0_IRQSTAT_iiccirq_MASK                             0x04000000
+#define BCHP_IRQ0_IRQSTAT_iiccirq_SHIFT                            26
+#define BCHP_IRQ0_IRQSTAT_iiccirq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: iicbirq [25:25] */
+#define BCHP_IRQ0_IRQSTAT_iicbirq_MASK                             0x02000000
+#define BCHP_IRQ0_IRQSTAT_iicbirq_SHIFT                            25
+#define BCHP_IRQ0_IRQSTAT_iicbirq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: iicairq [24:24] */
+#define BCHP_IRQ0_IRQSTAT_iicairq_MASK                             0x01000000
+#define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT                            24
+#define BCHP_IRQ0_IRQSTAT_iicairq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQSTAT_reserved1_MASK                           0x00f80000
+#define BCHP_IRQ0_IRQSTAT_reserved1_SHIFT                          19
+
+/* IRQ0 :: IRQSTAT :: uartc_irq [18:18] */
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK                           0x00040000
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT                          18
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: uartb_irq [17:17] */
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK                           0x00020000
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT                          17
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: uarta_irq [16:16] */
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK                           0x00010000
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT                          16
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQSTAT_reserved2_MASK                           0x0000fc00
+#define BCHP_IRQ0_IRQSTAT_reserved2_SHIFT                          10
+
+/* IRQ0 :: IRQSTAT :: ucirq [09:09] */
+#define BCHP_IRQ0_IRQSTAT_ucirq_MASK                               0x00000200
+#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT                              9
+#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQSTAT_reserved3_MASK                           0x00000180
+#define BCHP_IRQ0_IRQSTAT_reserved3_SHIFT                          7
+
+/* IRQ0 :: IRQSTAT :: gioirq [06:06] */
+#define BCHP_IRQ0_IRQSTAT_gioirq_MASK                              0x00000040
+#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT                             6
+#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT                           0
+
+/* IRQ0 :: IRQSTAT :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQSTAT_reserved4_MASK                           0x00000020
+#define BCHP_IRQ0_IRQSTAT_reserved4_SHIFT                          5
+
+/* IRQ0 :: IRQSTAT :: uairq [04:04] */
+#define BCHP_IRQ0_IRQSTAT_uairq_MASK                               0x00000010
+#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT                              4
+#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: ubirq [03:03] */
+#define BCHP_IRQ0_IRQSTAT_ubirq_MASK                               0x00000008
+#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT                              3
+#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: irbirq [02:02] */
+#define BCHP_IRQ0_IRQSTAT_irbirq_MASK                              0x00000004
+#define BCHP_IRQ0_IRQSTAT_irbirq_SHIFT                             2
+#define BCHP_IRQ0_IRQSTAT_irbirq_DEFAULT                           0
+
+/* IRQ0 :: IRQSTAT :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQSTAT_reserved5_MASK                           0x00000003
+#define BCHP_IRQ0_IRQSTAT_reserved5_SHIFT                          0
+
+#endif /* #ifndef BCHP_IRQ0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_irq1.h b/include/linux/brcmstb/7231b0/bchp_irq1.h
new file mode 100644
index 0000000..aa14c59
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_irq1.h
@@ -0,0 +1,50 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon May 17 03:36:55 2010
+ *                 MD5 Checksum         48de0819069cffb1a27afe66f66cd920
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ1_H__
+#define BCHP_IRQ1_H__
+
+/***************************************************************************
+ *IRQ1 - Level 2 PCI Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ1_IRQEN                          0x00406788 /* Interrupt Enable */
+#define BCHP_IRQ1_IRQSTAT                        0x0040678c /* Interrupt Status */
+
+#endif /* #ifndef BCHP_IRQ1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_mem_dma_0.h b/include/linux/brcmstb/7231b0/bchp_mem_dma_0.h
new file mode 100644
index 0000000..e2514da
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_mem_dma_0.h
@@ -0,0 +1,157 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:18:31 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_mem_dma_0.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:22p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEM_DMA_0_H__
+#define BCHP_MEM_DMA_0_H__
+
+/***************************************************************************
+ *MEM_DMA_0 - MEM_DMA_0 Registers
+ ***************************************************************************/
+#define BCHP_MEM_DMA_0_REVISION                  0x00374200 /* MEM_DMA REVISION */
+#define BCHP_MEM_DMA_0_FIRST_DESC                0x00374204 /* MEM_DMA First Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CTRL                      0x00374208 /* MEM_DMA Control Register */
+#define BCHP_MEM_DMA_0_WAKE_CTRL                 0x0037420c /* MEM_DMA Wake Control Register */
+#define BCHP_MEM_DMA_0_STATUS                    0x00374214 /* MEM_DMA Status Register */
+#define BCHP_MEM_DMA_0_CUR_DESC                  0x00374218 /* MEM_DMA Current Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CUR_BYTE                  0x0037421c /* MEM_DMA Current Byte Count Register */
+#define BCHP_MEM_DMA_0_SCRATCH                   0x00374224 /* MEM_DMA Scratch Register */
+
+/***************************************************************************
+ *REVISION - MEM_DMA REVISION
+ ***************************************************************************/
+/* MEM_DMA_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_0_REVISION_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_0_REVISION_reserved0_SHIFT                    16
+
+/* MEM_DMA_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_MASK                         0x0000ff00
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_SHIFT                        8
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_DEFAULT                      2
+
+/* MEM_DMA_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_MEM_DMA_0_REVISION_MINOR_MASK                         0x000000ff
+#define BCHP_MEM_DMA_0_REVISION_MINOR_SHIFT                        0
+#define BCHP_MEM_DMA_0_REVISION_MINOR_DEFAULT                      10
+
+/***************************************************************************
+ *FIRST_DESC - MEM_DMA First Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: FIRST_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_MASK                        0xffffffff
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_SHIFT                       0
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_DEFAULT                     0
+
+/***************************************************************************
+ *CTRL - MEM_DMA Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CTRL :: reserved0 [31:01] */
+#define BCHP_MEM_DMA_0_CTRL_reserved0_MASK                         0xfffffffe
+#define BCHP_MEM_DMA_0_CTRL_reserved0_SHIFT                        1
+
+/* MEM_DMA_0 :: CTRL :: RUN [00:00] */
+#define BCHP_MEM_DMA_0_CTRL_RUN_MASK                               0x00000001
+#define BCHP_MEM_DMA_0_CTRL_RUN_SHIFT                              0
+#define BCHP_MEM_DMA_0_CTRL_RUN_DEFAULT                            0
+
+/***************************************************************************
+ *WAKE_CTRL - MEM_DMA Wake Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: WAKE_CTRL :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_MASK                    0xfffffffc
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_SHIFT                   2
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE_MODE [01:01] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_MASK                    0x00000002
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_SHIFT                   1
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_DEFAULT                 0
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE [00:00] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MASK                         0x00000001
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_SHIFT                        0
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_DEFAULT                      0
+
+/***************************************************************************
+ *STATUS - MEM_DMA Status Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: STATUS :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_MEM_DMA_0_STATUS_reserved0_SHIFT                      2
+
+/* MEM_DMA_0 :: STATUS :: DMA_STATUS [01:00] */
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_MASK                      0x00000003
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_SHIFT                     0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_DEFAULT                   0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Idle                      0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Busy                      1
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Sleep                     2
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Reserved                  3
+
+/***************************************************************************
+ *CUR_DESC - MEM_DMA Current Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_MASK                          0xffffffff
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_SHIFT                         0
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_DEFAULT                       0
+
+/***************************************************************************
+ *CUR_BYTE - MEM_DMA Current Byte Count Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_BYTE :: reserved0 [31:25] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_MASK                     0xfe000000
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_SHIFT                    25
+
+/* MEM_DMA_0 :: CUR_BYTE :: COUNT [24:00] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_MASK                         0x01ffffff
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_SHIFT                        0
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_DEFAULT                      0
+
+/***************************************************************************
+ *SCRATCH - MEM_DMA Scratch Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_MASK                    0xffffffff
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_SHIFT                   0
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_DEFAULT                 0
+
+#endif /* #ifndef BCHP_MEM_DMA_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_memc_ddr_0.h b/include/linux/brcmstb/7231b0/bchp_memc_ddr_0.h
new file mode 100644
index 0000000..194f028
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_memc_ddr_0.h
@@ -0,0 +1,2665 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:36:03 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_memc_ddr_0.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:22p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR_0_H__
+#define BCHP_MEMC_DDR_0_H__
+
+/***************************************************************************
+ *MEMC_DDR_0 - Memory Controller Sequencer (DDR Param/Control) Registers 0
+ ***************************************************************************/
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG            0x003b2000 /* Memory Controller Mode-Configuration Register. */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL          0x003b2004 /* Dram iniitialization control */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS         0x003b2008 /* Dram iniitialization status */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0              0x003b200c /* Dram Mode0 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1              0x003b2010 /* Dram Mode1 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2              0x003b2014 /* Dram Mode2 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3              0x003b2018 /* Dram Mode3 register */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG               0x003b201c /* Precharge power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG              0x003b2020 /* Self-refresh power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SSPD_CMD                 0x003b2024 /* Software standby power down mode */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS        0x003b2028 /* Power down status */
+#define BCHP_MEMC_DDR_0_WARM_BOOT                0x003b202c /* Warm boot control registers */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0            0x003b2030 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1            0x003b2034 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2            0x003b2038 /* Read to Write & write to read timing register */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3            0x003b203c /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4            0x003b2040 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5            0x003b2044 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ         0x003b2048 /* Memory Controller Sequencer Enable */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT        0x003b204c /* Memory Controller , state machine timeout register. */
+#define BCHP_MEMC_DDR_0_BANK_STATUS              0x003b2050 /* Memory Controller, Bank Status Register. */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY           0x003b2054 /* Memory Controller, Tester Latency Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0               0x003b2058 /* Memory Controller, DATA_PINMAP_BYTE0_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1               0x003b205c /* Memory Controller, DATA_PINMAP_BYTE1_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2               0x003b2060 /* Memory Controller, DATA_PINMAP_BYTE2_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3               0x003b2064 /* Memory Controller, DATA_PINMAP_BYTE3_SEL Register. */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD   0x003b2068 /* Memory Controller, DDR3 DRAM reset Register. */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL             0x003b206c /* Statistics Control register */
+#define BCHP_MEMC_DDR_0_STAT_TIMER               0x003b2070 /* Statistics Timer */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP            0x003b2074 /* DRAM Idle_NOP Cycle Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP        0x003b2078 /* Maximum DRAM idle_NOP cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL             0x003b207c /* CAS Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL         0x003b2080 /* Maximum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL         0x003b2084 /* DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL 0x003b2088 /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL      0x003b208c /* Number of overall system memory read transactions. */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL     0x003b2090 /* Number of overall system memory write transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL       0x003b2094 /* Maximum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL       0x003b2098 /* Minimum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS  0x003b209c /* Service CAS Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS 0x003b20a0 /* Maximum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS 0x003b20a4 /* Minimum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY 0x003b20a8 /* Service Intra DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY 0x003b20ac /* Service Post DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES 0x003b20b0 /* Maximum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES 0x003b20b4 /* Minimum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ 0x003b20b8 /* Service Read Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE 0x003b20bc /* Service Write Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS 0x003b20c0 /* Maximum service Transaction count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS 0x003b20c4 /* Minimum service cycle Transaction register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY 0x003b20c8 /* Service Latency Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY 0x003b20cc /* Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY 0x003b20d0 /* Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x003b20d4 /* Absolute Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x003b20d8 /* Absolute Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH             0x003b20dc /* Total number of refreshes issuedr. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0        0x003b20e0 /* CAS cycle count register for client 0. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1        0x003b20e4 /* CAS cycle count register for client 1. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2        0x003b20e8 /* CAS cycle count register for client 2. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3        0x003b20ec /* CAS cycle count register for client 3. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4        0x003b20f0 /* CAS cycle count register for client 4. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5        0x003b20f4 /* CAS cycle count register for client 5. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6        0x003b20f8 /* CAS cycle count register for client 6. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7        0x003b20fc /* CAS cycle count register for client 7. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8        0x003b2100 /* CAS cycle count register for client 8. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9        0x003b2104 /* CAS cycle count register for client 9. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10       0x003b2108 /* CAS cycle count register for client 10. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11       0x003b210c /* CAS cycle count register for client 11. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12       0x003b2110 /* CAS cycle count register for client 12. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13       0x003b2114 /* CAS cycle count register for client 13. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14       0x003b2118 /* CAS cycle count register for client 14. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15       0x003b211c /* CAS cycle count register for client 15. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16       0x003b2120 /* CAS cycle count register for client 16. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17       0x003b2124 /* CAS cycle count register for client 17. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18       0x003b2128 /* CAS cycle count register for client 18. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19       0x003b212c /* CAS cycle count register for client 19. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20       0x003b2130 /* CAS cycle count register for client 20. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21       0x003b2134 /* CAS cycle count register for client 21. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22       0x003b2138 /* CAS cycle count register for client 22. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23       0x003b213c /* CAS cycle count register for client 23. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24       0x003b2140 /* CAS cycle count register for client 24. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25       0x003b2144 /* CAS cycle count register for client 25. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26       0x003b2148 /* CAS cycle count register for client 26. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27       0x003b214c /* CAS cycle count register for client 27. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28       0x003b2150 /* CAS cycle count register for client 28. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29       0x003b2154 /* CAS cycle count register for client 29. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30       0x003b2158 /* CAS cycle count register for client 30. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31       0x003b215c /* CAS cycle count register for client 31. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32       0x003b2160 /* CAS cycle count register for client 32. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33       0x003b2164 /* CAS cycle count register for client 33. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34       0x003b2168 /* CAS cycle count register for client 34. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35       0x003b216c /* CAS cycle count register for client 35. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36       0x003b2170 /* CAS cycle count register for client 36. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37       0x003b2174 /* CAS cycle count register for client 37. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38       0x003b2178 /* CAS cycle count register for client 38. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39       0x003b217c /* CAS cycle count register for client 39. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40       0x003b2180 /* CAS cycle count register for client 40. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41       0x003b2184 /* CAS cycle count register for client 41. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42       0x003b2188 /* CAS cycle count register for client 42. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43       0x003b218c /* CAS cycle count register for client 43. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44       0x003b2190 /* CAS cycle count register for client 44. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45       0x003b2194 /* CAS cycle count register for client 45. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46       0x003b2198 /* CAS cycle count register for client 46. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47       0x003b219c /* CAS cycle count register for client 47. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48       0x003b21a0 /* CAS cycle count register for client 48. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49       0x003b21a4 /* CAS cycle count register for client 49. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50       0x003b21a8 /* CAS cycle count register for client 50. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51       0x003b21ac /* CAS cycle count register for client 51. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52       0x003b21b0 /* CAS cycle count register for client 52. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53       0x003b21b4 /* CAS cycle count register for client 53. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54       0x003b21b8 /* CAS cycle count register for client 54. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55       0x003b21bc /* CAS cycle count register for client 55. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56       0x003b21c0 /* CAS cycle count register for client 56. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57       0x003b21c4 /* CAS cycle count register for client 57. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58       0x003b21c8 /* CAS cycle count register for client 58. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59       0x003b21cc /* CAS cycle count register for client 59. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60       0x003b21d0 /* CAS cycle count register for client 60. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61       0x003b21d4 /* CAS cycle count register for client 61. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62       0x003b21d8 /* CAS cycle count register for client 62. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63       0x003b21dc /* CAS cycle count register for client 63. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64       0x003b21e0 /* CAS cycle count register for client 64. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65       0x003b21e4 /* CAS cycle count register for client 65. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66       0x003b21e8 /* CAS cycle count register for client 66. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67       0x003b21ec /* CAS cycle count register for client 67. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68       0x003b21f0 /* CAS cycle count register for client 68. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69       0x003b21f4 /* CAS cycle count register for client 69. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70       0x003b21f8 /* CAS cycle count register for client 70. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71       0x003b21fc /* CAS cycle count register for client 71. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72       0x003b2200 /* CAS cycle count register for client 72. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73       0x003b2204 /* CAS cycle count register for client 73. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74       0x003b2208 /* CAS cycle count register for client 74. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75       0x003b220c /* CAS cycle count register for client 75. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76       0x003b2210 /* CAS cycle count register for client 76. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77       0x003b2214 /* CAS cycle count register for client 77. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78       0x003b2218 /* CAS cycle count register for client 78. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79       0x003b221c /* CAS cycle count register for client 79. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80       0x003b2220 /* CAS cycle count register for client 80. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81       0x003b2224 /* CAS cycle count register for client 81. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82       0x003b2228 /* CAS cycle count register for client 82. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83       0x003b222c /* CAS cycle count register for client 83. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84       0x003b2230 /* CAS cycle count register for client 84. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85       0x003b2234 /* CAS cycle count register for client 85. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86       0x003b2238 /* CAS cycle count register for client 86. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87       0x003b223c /* CAS cycle count register for client 87. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88       0x003b2240 /* CAS cycle count register for client 88. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89       0x003b2244 /* CAS cycle count register for client 89. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90       0x003b2248 /* CAS cycle count register for client 90. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91       0x003b224c /* CAS cycle count register for client 91. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92       0x003b2250 /* CAS cycle count register for client 92. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93       0x003b2254 /* CAS cycle count register for client 93. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94       0x003b2258 /* CAS cycle count register for client 94. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95       0x003b225c /* CAS cycle count register for client 95. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96       0x003b2260 /* CAS cycle count register for client 96. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97       0x003b2264 /* CAS cycle count register for client 97. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98       0x003b2268 /* CAS cycle count register for client 98. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99       0x003b226c /* CAS cycle count register for client 99. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100      0x003b2270 /* CAS cycle count register for client 100. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101      0x003b2274 /* CAS cycle count register for client 101. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102      0x003b2278 /* CAS cycle count register for client 102. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103      0x003b227c /* CAS cycle count register for client 103. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104      0x003b2280 /* CAS cycle count register for client 104. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105      0x003b2284 /* CAS cycle count register for client 105. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106      0x003b2288 /* CAS cycle count register for client 106. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107      0x003b228c /* CAS cycle count register for client 107. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108      0x003b2290 /* CAS cycle count register for client 108. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109      0x003b2294 /* CAS cycle count register for client 109. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110      0x003b2298 /* CAS cycle count register for client 110. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111      0x003b229c /* CAS cycle count register for client 111. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112      0x003b22a0 /* CAS cycle count register for client 112. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113      0x003b22a4 /* CAS cycle count register for client 113. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114      0x003b22a8 /* CAS cycle count register for client 114. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115      0x003b22ac /* CAS cycle count register for client 115. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116      0x003b22b0 /* CAS cycle count register for client 116. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117      0x003b22b4 /* CAS cycle count register for client 117. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118      0x003b22b8 /* CAS cycle count register for client 118. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119      0x003b22bc /* CAS cycle count register for client 119. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120      0x003b22c0 /* CAS cycle count register for client 120. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121      0x003b22c4 /* CAS cycle count register for client 121. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122      0x003b22c8 /* CAS cycle count register for client 122. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123      0x003b22cc /* CAS cycle count register for client 123. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124      0x003b22d0 /* CAS cycle count register for client 124. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125      0x003b22d4 /* CAS cycle count register for client 125. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126      0x003b22d8 /* CAS cycle count register for client 126. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127      0x003b22dc /* CAS cycle count register for client 127. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL         0x003b22e0 /* Minimum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL 0x003b22e4 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL 0x003b22e8 /* MEMSYS Auto Init Control. */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS  0x003b22ec /* MEMSYS Auto Init Status. */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE 0x003b22f0 /* PHY VDL calibrate override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE 0x003b22f4 /* SHIM PLL pndiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE 0x003b22f8 /* SHIM PLL mdiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY          0x003b22fc /* Dynamic VDL shmoo command delay. */
+
+/***************************************************************************
+ *CNTRLR_CONFIG - Memory Controller Mode-Configuration Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_MASK               0xfffffff8
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_SHIFT              3
+
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DEVICE_TECH [02:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_SHIFT            0
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_DEFAULT          3
+
+/***************************************************************************
+ *DRAM_INIT_CNTRL - Dram iniitialization control
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_MASK             0xfffffff8
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_SHIFT            3
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: BYPASS_PHY_INIT_RDY [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_MASK   0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_SHIFT  2
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR_TECH [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DEFAULT           1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR2              0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR3              1
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR3_INIT_MODE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_MASK        0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_SHIFT       0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_DEFAULT     0
+
+/***************************************************************************
+ *DRAM_INIT_STATUS - Dram iniitialization status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_SHIFT           0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_DEFAULT         0
+
+/***************************************************************************
+ *DRAM_MODE_0 - Dram Mode0 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: PD_EXIT [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_MASK              0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_SHIFT             12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_DEFAULT                7
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_DEFAULT         0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: CL [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_MASK                   0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_DEFAULT                0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BL [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_DEFAULT                2
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK        0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT       12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT     0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_DEFAULT                4
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT         0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_MASK               0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_SHIFT              4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT            4
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_DEFAULT               0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_MASK                 0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_SHIFT                2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_DEFAULT              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_MASK                   0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_MODE_1 - Dram Mode1 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DEFAULT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: RDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DQSB [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_MASK                 0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_SHIFT                10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_ENABLE               0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DISABLE              1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: OCD_CAL [09:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_MASK              0x00000380
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_SHIFT             7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_DEFAULT       1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: AL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_MASK                   0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DRV_IMP [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DISABLE            1
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_MASK             0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_SHIFT            10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK          0x00000200
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT         9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_MASK             0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT            7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT          0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE           1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK   0x00000020
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT  5
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_MASK                   0x00000018
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT       1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK   0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT  1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DISABLE            1
+
+/***************************************************************************
+ *DRAM_MODE_2 - Dram Mode2 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_1 [12:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_MASK             0x00001f00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: HT_SRF [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_ENABLE             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DISABLE            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_2 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_MASK             0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_SHIFT            4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: DCC_ENABLE [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_MASK           0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_SHIFT          3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DEFAULT        0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_ENABLE         1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DISABLE        0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_DEFAULT              0
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_MASK             0x00001800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_SHIFT            11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_MASK               0x00000600
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_SHIFT              9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT            1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT             6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT           1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_MASK                  0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_DEFAULT               1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_MODE_3 - Dram Mode3 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: unused_0 [15:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_MASK                  0x0000fff8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_DEFAULT               0
+
+/* union - case DDR2 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR2 :: unused_1 [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_SHIFT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_DEFAULT          0
+
+/* union - case DDR3 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_MASK                  0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_SHIFT                 2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_DEFAULT               0
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_MASK              0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT           0
+
+/***************************************************************************
+ *PPD_CONFIG - Precharge power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PPD_CONFIG :: reserved0 [31:13] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_MASK                  0xffffe000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_SHIFT                 13
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_EN [12:12] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_MASK                     0x00001000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_SHIFT                    12
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_DEFAULT                  0
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: INACT_COUNT [11:00] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_MASK                0x00000fff
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *SRPD_CONFIG - Self-refresh power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SRPD_CONFIG :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_MASK                 0xfffe0000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_SHIFT                17
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: SRPD_EN [16:16] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_MASK                   0x00010000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_SHIFT                  16
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_DEFAULT                0
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *SSPD_CMD - Software standby power down mode
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SSPD_CMD :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_MASK                    0xfffffffe
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_SHIFT                   1
+
+/* MEMC_DDR_0 :: SSPD_CMD :: SSPD [00:00] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK                         0x00000001
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_SHIFT                        0
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_DEFAULT                      0
+
+/***************************************************************************
+ *POWER_DOWN_STATUS - Power down status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_MASK           0xfffffff8
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_SHIFT          3
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SSPD [02:02] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK                0x00000004
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_SHIFT               2
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_DEFAULT             0
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SRPD [01:01] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_MASK                0x00000002
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_SHIFT               1
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_DEFAULT             0
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: PPD [00:00] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_MASK                 0x00000001
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_SHIFT                0
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_DEFAULT              0
+
+/***************************************************************************
+ *WARM_BOOT - Warm boot control registers
+ ***************************************************************************/
+/* MEMC_DDR_0 :: WARM_BOOT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_MASK                   0xfffffffe
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_SHIFT                  1
+
+/* MEMC_DDR_0 :: WARM_BOOT :: WARM_BOOT [00:00] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_MASK                   0x00000001
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_TIMING_0 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_MASK                0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_SHIFT               24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_DEFAULT             6
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_MASK                0x00ff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_SHIFT               16
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_DEFAULT             8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_MASK                 0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_SHIFT                8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_DEFAULT              8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_DEFAULT             20
+
+/***************************************************************************
+ *DRAM_TIMING_1 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_MASK                0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_SHIFT               8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_DEFAULT             27
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_DEFAULT             4
+
+/***************************************************************************
+ *DRAM_TIMING_2 - Read to Write & write to read timing register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_MASK               0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_SHIFT              8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_DEFAULT            14
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_MASK               0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_DEFAULT            9
+
+/***************************************************************************
+ *DRAM_TIMING_3 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: reserved0 [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_MASK               0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_SHIFT              24
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT      12
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: POWERUP_CKE_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_MASK       0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_SHIFT      10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_DEFAULT    94
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: DLL_LOCK_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_MASK          0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_SHIFT         0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_DEFAULT       512
+
+/***************************************************************************
+ *DRAM_TIMING_4 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: PRECHARGE_ALL_DELAY [28:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_MASK     0x1f000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_SHIFT    24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_DEFAULT  8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: LOAD_MODE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_DEFAULT      12
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: REFRESH_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_MASK           0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_SHIFT          10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT        88
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_MASK           0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT          0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT        512
+
+/***************************************************************************
+ *DRAM_TIMING_5 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_ASSETION_DELAY [28:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_MASK      0x1ff80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_SHIFT     19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_DEFAULT   261
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [18:15] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK           0x00078000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT          15
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT        3
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [14:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK         0x00007c00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT        10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT      13
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK      0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT     0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT   512
+
+/***************************************************************************
+ *CNTRLR_START_SEQ - Memory Controller Sequencer Enable
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: START_SEQ [00:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_SHIFT           0
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_DEFAULT         0
+
+/***************************************************************************
+ *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_MASK           0xfffe0000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_SHIFT          17
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_MASK              0x00010000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT             16
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT           0
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT            65535
+
+/***************************************************************************
+ *BANK_STATUS - Memory Controller, Bank Status Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: BANK_STATUS :: reserved0 [31:08] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_SHIFT                8
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK7_STATUS [07:07] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_SHIFT             7
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK6_STATUS [06:06] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_SHIFT             6
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK5_STATUS [05:05] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_MASK              0x00000020
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_SHIFT             5
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK4_STATUS [04:04] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_MASK              0x00000010
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_SHIFT             4
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK3_STATUS [03:03] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_MASK              0x00000008
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_SHIFT             3
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK2_STATUS [02:02] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_MASK              0x00000004
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_SHIFT             2
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK1_STATUS [01:01] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_SHIFT             1
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK0_STATUS [00:00] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_MASK              0x00000001
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_SHIFT             0
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_DEFAULT           1
+
+/***************************************************************************
+ *TESTER_LATENCY - Memory Controller, Tester Latency Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: TESTER_LATENCY :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_MASK              0xffffff80
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_SHIFT             7
+
+/* MEMC_DDR_0 :: TESTER_LATENCY :: TLATENCY_SEL [06:00] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_MASK           0x0000007f
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_SHIFT          0
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_DEFAULT        0
+
+/***************************************************************************
+ *DTPM_BYTE0 - Memory Controller, DATA_PINMAP_BYTE0_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE1 - Memory Controller, DATA_PINMAP_BYTE1_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE2 - Memory Controller, DATA_PINMAP_BYTE2_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE3 - Memory Controller, DATA_PINMAP_BYTE3_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_DDR3_RESET_PERIOD - Memory Controller, DDR3 DRAM reset Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: reserved0 [31:20] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_MASK      0xfff00000
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_SHIFT     20
+
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: DRAM_RESET_PERIOD [19:00] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_MASK 0x000fffff
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_SHIFT 0
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_DEFAULT 43200
+
+/***************************************************************************
+ *STAT_CONTROL - Statistics Control register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CONTROL :: reserved0 [31:09] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_MASK                0xfffffe00
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_SHIFT               9
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: COUNTER_MODE [08:08] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_SHIFT            8
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_DEFAULT          0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT    1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_NORMAL           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: STAT_ENABLE [07:07] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_SHIFT             7
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DEFAULT           0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_ENABLE            1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DISABLE           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: CLIENT_ID [06:00] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_MASK                0x0000007f
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_DEFAULT             0
+
+/***************************************************************************
+ *STAT_TIMER - Statistics Timer
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TIMER :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_MASK                      0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_SHIFT                     0
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_DEFAULT                   0
+
+/***************************************************************************
+ *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_MASK                   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_DEFAULT                0
+
+/***************************************************************************
+ *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_ALL - CAS Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_DEFAULT                 0
+
+/***************************************************************************
+ *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_PENALTY_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT    0
+
+/***************************************************************************
+ *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_MASK            0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_SHIFT           0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT         0
+
+/***************************************************************************
+ *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_DEFAULT           4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_MASK         0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT        0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT      0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT  4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT  0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_REFRESH - Total number of refreshes issuedr.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_REFRESH :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_DEFAULT                 0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_0 - CAS cycle count register for client 0.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_1 - CAS cycle count register for client 1.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_2 - CAS cycle count register for client 2.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_3 - CAS cycle count register for client 3.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_4 - CAS cycle count register for client 4.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_5 - CAS cycle count register for client 5.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_6 - CAS cycle count register for client 6.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_7 - CAS cycle count register for client 7.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_8 - CAS cycle count register for client 8.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_9 - CAS cycle count register for client 9.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_10 - CAS cycle count register for client 10.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_11 - CAS cycle count register for client 11.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_12 - CAS cycle count register for client 12.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_13 - CAS cycle count register for client 13.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_14 - CAS cycle count register for client 14.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_15 - CAS cycle count register for client 15.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_16 - CAS cycle count register for client 16.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_17 - CAS cycle count register for client 17.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_18 - CAS cycle count register for client 18.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_19 - CAS cycle count register for client 19.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_20 - CAS cycle count register for client 20.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_21 - CAS cycle count register for client 21.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_22 - CAS cycle count register for client 22.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_23 - CAS cycle count register for client 23.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_24 - CAS cycle count register for client 24.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_25 - CAS cycle count register for client 25.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_26 - CAS cycle count register for client 26.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_27 - CAS cycle count register for client 27.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_28 - CAS cycle count register for client 28.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_29 - CAS cycle count register for client 29.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_30 - CAS cycle count register for client 30.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_31 - CAS cycle count register for client 31.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_32 - CAS cycle count register for client 32.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_33 - CAS cycle count register for client 33.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_34 - CAS cycle count register for client 34.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_35 - CAS cycle count register for client 35.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_36 - CAS cycle count register for client 36.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_37 - CAS cycle count register for client 37.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_38 - CAS cycle count register for client 38.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_39 - CAS cycle count register for client 39.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_40 - CAS cycle count register for client 40.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_41 - CAS cycle count register for client 41.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_42 - CAS cycle count register for client 42.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_43 - CAS cycle count register for client 43.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_44 - CAS cycle count register for client 44.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_45 - CAS cycle count register for client 45.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_46 - CAS cycle count register for client 46.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_47 - CAS cycle count register for client 47.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_48 - CAS cycle count register for client 48.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_49 - CAS cycle count register for client 49.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_50 - CAS cycle count register for client 50.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_51 - CAS cycle count register for client 51.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_52 - CAS cycle count register for client 52.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_53 - CAS cycle count register for client 53.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_54 - CAS cycle count register for client 54.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_55 - CAS cycle count register for client 55.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_56 - CAS cycle count register for client 56.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_57 - CAS cycle count register for client 57.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_58 - CAS cycle count register for client 58.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_59 - CAS cycle count register for client 59.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_60 - CAS cycle count register for client 60.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_61 - CAS cycle count register for client 61.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_62 - CAS cycle count register for client 62.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_63 - CAS cycle count register for client 63.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_64 - CAS cycle count register for client 64.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_65 - CAS cycle count register for client 65.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_66 - CAS cycle count register for client 66.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_67 - CAS cycle count register for client 67.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_68 - CAS cycle count register for client 68.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_69 - CAS cycle count register for client 69.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_70 - CAS cycle count register for client 70.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_71 - CAS cycle count register for client 71.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_72 - CAS cycle count register for client 72.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_73 - CAS cycle count register for client 73.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_74 - CAS cycle count register for client 74.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_75 - CAS cycle count register for client 75.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_76 - CAS cycle count register for client 76.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_77 - CAS cycle count register for client 77.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_78 - CAS cycle count register for client 78.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_79 - CAS cycle count register for client 79.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_80 - CAS cycle count register for client 80.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_81 - CAS cycle count register for client 81.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_82 - CAS cycle count register for client 82.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_83 - CAS cycle count register for client 83.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_84 - CAS cycle count register for client 84.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_85 - CAS cycle count register for client 85.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_86 - CAS cycle count register for client 86.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_87 - CAS cycle count register for client 87.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_88 - CAS cycle count register for client 88.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_89 - CAS cycle count register for client 89.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_90 - CAS cycle count register for client 90.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_91 - CAS cycle count register for client 91.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_92 - CAS cycle count register for client 92.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_93 - CAS cycle count register for client 93.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_94 - CAS cycle count register for client 94.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_95 - CAS cycle count register for client 95.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_96 - CAS cycle count register for client 96.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_97 - CAS cycle count register for client 97.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_98 - CAS cycle count register for client 98.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_99 - CAS cycle count register for client 99.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_100 - CAS cycle count register for client 100.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_101 - CAS cycle count register for client 101.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_102 - CAS cycle count register for client 102.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_103 - CAS cycle count register for client 103.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_104 - CAS cycle count register for client 104.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_105 - CAS cycle count register for client 105.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_106 - CAS cycle count register for client 106.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_107 - CAS cycle count register for client 107.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_108 - CAS cycle count register for client 108.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_109 - CAS cycle count register for client 109.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_110 - CAS cycle count register for client 110.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_111 - CAS cycle count register for client 111.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_112 - CAS cycle count register for client 112.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_113 - CAS cycle count register for client 113.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_114 - CAS cycle count register for client 114.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_115 - CAS cycle count register for client 115.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_116 - CAS cycle count register for client 116.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_117 - CAS cycle count register for client 117.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_118 - CAS cycle count register for client 118.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_119 - CAS cycle count register for client 119.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_120 - CAS cycle count register for client 120.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_121 - CAS cycle count register for client 121.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_122 - CAS cycle count register for client 122.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_123 - CAS cycle count register for client 123.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_124 - CAS cycle count register for client 124.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_125 - CAS cycle count register for client 125.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_126 - CAS cycle count register for client 126.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_127 - CAS cycle count register for client 127.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_DEFAULT             4294967295
+
+/***************************************************************************
+ *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT    4294967295
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_CONTROL - MEMSYS Auto Init Control.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: reserved0 [31:10] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_MASK    0xfffffc00
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_SHIFT   10
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_DIVIDER [09:09] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_MASK 0x00000200
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_SHIFT 9
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_VDL_CALIB_AUTO_INIT [08:08] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_MASK 0x00000100
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_SHIFT 8
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_DRAM_INIT_DONE_SET [07:07] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_MASK 0x00000080
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_SHIFT 7
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_RESET [06:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_MASK 0x00000040
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_SET [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_READY_SET [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_AUTO_INIT_ACTIVE_RESET [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_MASK 0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_SHIFT 3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: SKIP_PHY_AUTO_INIT [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: MEMSYS_AUTO_INIT_START [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_STATUS - MEMSYS Auto Init Status.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_MASK     0xfffff000
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_SHIFT    12
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMC_AUTO_INIT_STATES [11:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_MASK 0x00000fc0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: AUTO_INIT_ACTIVE [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_STRAP_VALID [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_READY [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_MASK     0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_SHIFT    3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_DEFAULT  0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: DRAM_INIT_DONE [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_FAIL [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_DEFAULT 0
+
+/***************************************************************************
+ *PHY_VDL_CALIB_AUTO_INIT_OVERRIDE - PHY VDL calibrate override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PHY_VDL_CALIB_AUTO_INIT_OVERRIDE :: PHY_VDL_CALIB_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_DEFAULT 268435456
+
+/***************************************************************************
+ *SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE - SHIM PLL pndiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_PNDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_DEFAULT 598736896
+
+/***************************************************************************
+ *SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE - SHIM PLL mdiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_MDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_DEFAULT 4099
+
+/***************************************************************************
+ *DYN_VDL_CMD_DLY - Dynamic VDL shmoo command delay.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_MASK             0xfffff000
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_SHIFT            12
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: END_CAS_DLY [11:06] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_MASK           0x00000fc0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_SHIFT          6
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_DEFAULT        0
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: START_CAS_DLY [05:00] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_MASK         0x0000003f
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_SHIFT        0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_DEFAULT      0
+
+#endif /* #ifndef BCHP_MEMC_DDR_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_nand.h b/include/linux/brcmstb/7231b0/bchp_nand.h
new file mode 100644
index 0000000..a54345d
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_nand.h
@@ -0,0 +1,2486 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:17:57 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_nand.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 6:33p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_NAND_H__
+#define BCHP_NAND_H__
+
+/***************************************************************************
+ *NAND - Nand Flash Control Registers
+ ***************************************************************************/
+#define BCHP_NAND_REVISION                       0x00412800 /* NAND Revision */
+#define BCHP_NAND_CMD_START                      0x00412804 /* Nand Flash Command Start */
+#define BCHP_NAND_CMD_EXT_ADDRESS                0x00412808 /* Nand Flash Command Extended Address */
+#define BCHP_NAND_CMD_ADDRESS                    0x0041280c /* Nand Flash Command Address */
+#define BCHP_NAND_CMD_END_ADDRESS                0x00412810 /* Nand Flash Command End Address */
+#define BCHP_NAND_CS_NAND_SELECT                 0x00412814 /* Nand Flash EBI CS Select */
+#define BCHP_NAND_CS_NAND_XOR                    0x00412818 /* Nand Flash EBI CS Address XOR with 1FC0 Control */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0          0x00412820 /* Nand Flash Spare Area Read Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4          0x00412824 /* Nand Flash Spare Area Read Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8          0x00412828 /* Nand Flash Spare Area Read Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C          0x0041282c /* Nand Flash Spare Area Read Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0         0x00412830 /* Nand Flash Spare Area Write Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4         0x00412834 /* Nand Flash Spare Area Write Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8         0x00412838 /* Nand Flash Spare Area Write Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C         0x0041283c /* Nand Flash Spare Area Write Bytes 12-15 */
+#define BCHP_NAND_ACC_CONTROL                    0x00412840 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG                         0x00412848 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1                       0x00412850 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2                       0x00412854 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SEMAPHORE                      0x00412858 /* Semaphore */
+#define BCHP_NAND_FLASH_DEVICE_ID                0x00412860 /* Nand Flash Device ID */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT            0x00412864 /* Nand Flash Extended Device ID */
+#define BCHP_NAND_BLOCK_LOCK_STATUS              0x00412868 /* Nand Flash Block Lock Status */
+#define BCHP_NAND_INTFC_STATUS                   0x0041286c /* Nand Flash Interface Status */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR              0x00412870 /* ECC Correctable Error Extended Address */
+#define BCHP_NAND_ECC_CORR_ADDR                  0x00412874 /* ECC Correctable Error Address */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR               0x00412878 /* ECC Uncorrectable Error Extended Address */
+#define BCHP_NAND_ECC_UNC_ADDR                   0x0041287c /* ECC Uncorrectable Error Address */
+#define BCHP_NAND_READ_ERROR_COUNT               0x00412880 /* Read Error Count */
+#define BCHP_NAND_CORR_STAT_THRESHOLD            0x00412884 /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_ONFI_STATUS                    0x00412888 /* ONFI Status */
+#define BCHP_NAND_ONFI_DEBUG_DATA                0x0041288c /* ONFI Debug Data */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR            0x00412890 /* Flash Read Data Extended Address */
+#define BCHP_NAND_FLASH_READ_ADDR                0x00412894 /* Flash Read Data Address */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR          0x00412898 /* Page Program Extended Address */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR              0x0041289c /* Page Program Address */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR             0x004128a0 /* Copy Back Extended Address */
+#define BCHP_NAND_COPY_BACK_ADDR                 0x004128a4 /* Copy Back Address */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR           0x004128a8 /* Block Erase Extended Address */
+#define BCHP_NAND_BLOCK_ERASE_ADDR               0x004128ac /* Block Erase Address */
+#define BCHP_NAND_INV_READ_EXT_ADDR              0x004128b0 /* Flash Invalid Data Extended Address */
+#define BCHP_NAND_INV_READ_ADDR                  0x004128b4 /* Flash Invalid Data Address */
+#define BCHP_NAND_BLK_WR_PROTECT                 0x004128c0 /* Block Write Protect Enable and Size for EBI_CS0b */
+#define BCHP_NAND_ACC_CONTROL_CS1                0x004128d0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS1                     0x004128d4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS1                   0x004128d8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS1                   0x004128dc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS2                0x004128e0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS2                     0x004128e4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS2                   0x004128e8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS2                   0x004128ec /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS3                0x004128f0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS3                     0x004128f4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS3                   0x004128f8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS3                   0x004128fc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS4                0x00412900 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS4                     0x00412904 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS4                   0x00412908 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS4                   0x0041290c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS5                0x00412910 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS5                     0x00412914 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS5                   0x00412918 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS5                   0x0041291c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10         0x00412930 /* Nand Flash Spare Area Read Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14         0x00412934 /* Nand Flash Spare Area Read Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18         0x00412938 /* Nand Flash Spare Area Read Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C         0x0041293c /* Nand Flash Spare Area Read Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10        0x00412940 /* Nand Flash Spare Area Write Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14        0x00412944 /* Nand Flash Spare Area Write Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18        0x00412948 /* Nand Flash Spare Area Write Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C        0x0041294c /* Nand Flash Spare Area Write Bytes 28-31 */
+#define BCHP_NAND_LL_OP                          0x00412978 /* Nand Flash Low Level Operation */
+#define BCHP_NAND_LL_RDDATA                      0x0041297c /* Nand Flash Low Level Read Data */
+
+/***************************************************************************
+ *REVISION - NAND Revision
+ ***************************************************************************/
+/* NAND :: REVISION :: 8KB_PAGE_SUPPORT [31:31] */
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_MASK                   0x80000000
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_SHIFT                  31
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_DEFAULT                1
+
+/* NAND :: REVISION :: reserved0 [30:16] */
+#define BCHP_NAND_REVISION_reserved0_MASK                          0x7fff0000
+#define BCHP_NAND_REVISION_reserved0_SHIFT                         16
+
+/* NAND :: REVISION :: MAJOR [15:08] */
+#define BCHP_NAND_REVISION_MAJOR_MASK                              0x0000ff00
+#define BCHP_NAND_REVISION_MAJOR_SHIFT                             8
+#define BCHP_NAND_REVISION_MAJOR_DEFAULT                           5
+
+/* NAND :: REVISION :: MINOR [07:00] */
+#define BCHP_NAND_REVISION_MINOR_MASK                              0x000000ff
+#define BCHP_NAND_REVISION_MINOR_SHIFT                             0
+#define BCHP_NAND_REVISION_MINOR_DEFAULT                           0
+
+/***************************************************************************
+ *CMD_START - Nand Flash Command Start
+ ***************************************************************************/
+/* NAND :: CMD_START :: reserved0 [31:29] */
+#define BCHP_NAND_CMD_START_reserved0_MASK                         0xe0000000
+#define BCHP_NAND_CMD_START_reserved0_SHIFT                        29
+
+/* NAND :: CMD_START :: OPCODE [28:24] */
+#define BCHP_NAND_CMD_START_OPCODE_MASK                            0x1f000000
+#define BCHP_NAND_CMD_START_OPCODE_SHIFT                           24
+#define BCHP_NAND_CMD_START_OPCODE_DEFAULT                         0
+#define BCHP_NAND_CMD_START_OPCODE_NULL                            0
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ                       1
+#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ                 2
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ                     3
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE                    4
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA              5
+#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK                       6
+#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ                  7
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE                     8
+#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET                     9
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK                     10
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN                11
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK                   12
+#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS         13
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ                  14
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL            15
+#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP                    16
+
+/* NAND :: CMD_START :: reserved1 [23:00] */
+#define BCHP_NAND_CMD_START_reserved1_MASK                         0x00ffffff
+#define BCHP_NAND_CMD_START_reserved1_SHIFT                        0
+
+/***************************************************************************
+ *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
+ ***************************************************************************/
+/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK                   0xfff80000
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT                  19
+
+/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK                      0x00070000
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT                     16
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT                   0
+
+/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK                 0x0000ffff
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT                0
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT              0
+
+/***************************************************************************
+ *CMD_ADDRESS - Nand Flash Command Address
+ ***************************************************************************/
+/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK                         0xffffffff
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT                        0
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT                      0
+
+/***************************************************************************
+ *CMD_END_ADDRESS - Nand Flash Command End Address
+ ***************************************************************************/
+/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT                    0
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT                  0
+
+/***************************************************************************
+ *CS_NAND_SELECT - Nand Flash EBI CS Select
+ ***************************************************************************/
+/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT                     31
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT                   0
+
+/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK        0x40000000
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT       30
+
+/* NAND :: CS_NAND_SELECT :: reserved0 [29:29] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK                    0x20000000
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT                   29
+
+/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK              0x10000000
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT             28
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT           0
+
+/* NAND :: CS_NAND_SELECT :: reserved1 [27:16] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_MASK                    0x0fff0000
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_SHIFT                   16
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK           0x00008000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT          15
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK           0x00004000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT          14
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK           0x00002000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT          13
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK           0x00001000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT          12
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK           0x00000800
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT          11
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK           0x00000400
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT          10
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK           0x00000200
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT          9
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK           0x00000100
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT          8
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK                 0x00000080
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT                7
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK                 0x00000040
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT                6
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK                 0x00000020
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT                5
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK                 0x00000010
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT                4
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK                 0x00000008
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT                3
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK                 0x00000004
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT                2
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK                 0x00000002
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT                1
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK                 0x00000001
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT                0
+
+/***************************************************************************
+ *CS_NAND_XOR - Nand Flash EBI CS Address XOR with 1FC0 Control
+ ***************************************************************************/
+/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_1FC0_XOR [31:31] */
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_MASK           0x80000000
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_SHIFT          31
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_DEFAULT        0
+
+/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
+#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK                       0x7fffff00
+#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT                      8
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_1FC0_XOR [07:07] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_MASK          0x00000080
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_SHIFT         7
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_1FC0_XOR [06:06] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_MASK          0x00000040
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_SHIFT         6
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_1FC0_XOR [05:05] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_MASK          0x00000020
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_SHIFT         5
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_1FC0_XOR [04:04] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_MASK          0x00000010
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_SHIFT         4
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_1FC0_XOR [03:03] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_MASK          0x00000008
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_SHIFT         3
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_1FC0_XOR [02:02] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_MASK          0x00000004
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_SHIFT         2
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_1FC0_XOR [01:01] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_MASK          0x00000002
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_SHIFT         1
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_1FC0_XOR [00:00] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_MASK          0x00000001
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_SHIFT         0
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT         255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT         255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT       255
+
+/***************************************************************************
+ *ACC_CONTROL - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_MASK                       0x80000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_SHIFT                      31
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_DEFAULT                    1
+
+/* NAND :: ACC_CONTROL :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_MASK                       0x40000000
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_SHIFT                      30
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_DEFAULT                    1
+
+/* NAND :: ACC_CONTROL :: RD_ECC_BLK0_EN [29:29] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_MASK                  0x20000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_SHIFT                 29
+
+/* NAND :: ACC_CONTROL :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_SHIFT                  28
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_MASK                0x08000000
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_SHIFT               27
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_DEFAULT             0
+
+/* NAND :: ACC_CONTROL :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_MASK                 0x04000000
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_SHIFT                26
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_MASK                   0x02000000
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_SHIFT                  25
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_MASK                     0x01000000
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_SHIFT                    24
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_DEFAULT                  1
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL_0 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_MASK                     0x00f00000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_SHIFT                    20
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_DEFAULT                  15
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_MASK                       0x000f0000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_SHIFT                      16
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_DEFAULT                    15
+
+/* NAND :: ACC_CONTROL :: reserved0 [15:15] */
+#define BCHP_NAND_ACC_CONTROL_reserved0_MASK                       0x00008000
+#define BCHP_NAND_ACC_CONTROL_reserved0_SHIFT                      15
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K_0 [14:14] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_MASK                0x00004000
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_SHIFT               14
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_DEFAULT             0
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE_0 [13:08] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_MASK               0x00003f00
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_SHIFT              8
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_DEFAULT            16
+
+/* NAND :: ACC_CONTROL :: reserved1 [07:07] */
+#define BCHP_NAND_ACC_CONTROL_reserved1_MASK                       0x00000080
+#define BCHP_NAND_ACC_CONTROL_reserved1_SHIFT                      7
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_MASK                  0x00000040
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_SHIFT                 6
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_DEFAULT               0
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_MASK                 0x0000003f
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_SHIFT                0
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_DEFAULT              16
+
+/***************************************************************************
+ *CONFIG - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_MASK                          0x80000000
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_SHIFT                         31
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_DEFAULT                       0
+
+/* NAND :: CONFIG :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_MASK                           0x70000000
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_SHIFT                          28
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_2048KB                 6
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_1024KB                 5
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_512KB                  3
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_128KB                  1
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_16KB                   0
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_8KB                    2
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_256KB                  4
+
+/* NAND :: CONFIG :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_MASK                          0x0f000000
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_SHIFT                         24
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4MB                  0
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8MB                  1
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16MB                 2
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32MB                 3
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64MB                 4
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128MB                5
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_256MB                6
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_512MB                7
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_1GB                  8
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_2GB                  9
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4GB                  10
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8GB                  11
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16GB                 12
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32GB                 13
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64GB                 14
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128GB                15
+
+/* NAND :: CONFIG :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_MASK                         0x00800000
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_SHIFT                        23
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_8                  0
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_16                 1
+
+/* NAND :: CONFIG :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_reserved0_MASK                            0x00400000
+#define BCHP_NAND_CONFIG_reserved0_SHIFT                           22
+
+/* NAND :: CONFIG :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_PAGE_SIZE_MASK                            0x00300000
+#define BCHP_NAND_CONFIG_PAGE_SIZE_SHIFT                           20
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_512                     0
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_2KB                     1
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_4KB                     2
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_8KB                     3
+
+/* NAND :: CONFIG :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_reserved1_MASK                            0x00080000
+#define BCHP_NAND_CONFIG_reserved1_SHIFT                           19
+
+/* NAND :: CONFIG :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_MASK                        0x00070000
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_SHIFT                       16
+
+/* NAND :: CONFIG :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_reserved2_MASK                            0x00008000
+#define BCHP_NAND_CONFIG_reserved2_SHIFT                           15
+
+/* NAND :: CONFIG :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_MASK                        0x00007000
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_SHIFT                       12
+
+/* NAND :: CONFIG :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_reserved3_MASK                            0x00000800
+#define BCHP_NAND_CONFIG_reserved3_SHIFT                           11
+
+/* NAND :: CONFIG :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_MASK                        0x00000700
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_SHIFT                       8
+
+/* NAND :: CONFIG :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_reserved4_MASK                            0x000000ff
+#define BCHP_NAND_CONFIG_reserved4_SHIFT                           0
+
+/***************************************************************************
+ *TIMING_1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_tWP_MASK                                0xf0000000
+#define BCHP_NAND_TIMING_1_tWP_SHIFT                               28
+#define BCHP_NAND_TIMING_1_tWP_DEFAULT                             6
+
+/* NAND :: TIMING_1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_tWH_MASK                                0x0f000000
+#define BCHP_NAND_TIMING_1_tWH_SHIFT                               24
+#define BCHP_NAND_TIMING_1_tWH_DEFAULT                             5
+
+/* NAND :: TIMING_1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_tRP_MASK                                0x00f00000
+#define BCHP_NAND_TIMING_1_tRP_SHIFT                               20
+#define BCHP_NAND_TIMING_1_tRP_DEFAULT                             7
+
+/* NAND :: TIMING_1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_tREH_MASK                               0x000f0000
+#define BCHP_NAND_TIMING_1_tREH_SHIFT                              16
+#define BCHP_NAND_TIMING_1_tREH_DEFAULT                            4
+
+/* NAND :: TIMING_1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_tCS_MASK                                0x0000f000
+#define BCHP_NAND_TIMING_1_tCS_SHIFT                               12
+#define BCHP_NAND_TIMING_1_tCS_DEFAULT                             8
+
+/* NAND :: TIMING_1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_tCLH_MASK                               0x00000f00
+#define BCHP_NAND_TIMING_1_tCLH_SHIFT                              8
+#define BCHP_NAND_TIMING_1_tCLH_DEFAULT                            4
+
+/* NAND :: TIMING_1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_tALH_MASK                               0x000000f0
+#define BCHP_NAND_TIMING_1_tALH_SHIFT                              4
+#define BCHP_NAND_TIMING_1_tALH_DEFAULT                            5
+
+/* NAND :: TIMING_1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_tADL_MASK                               0x0000000f
+#define BCHP_NAND_TIMING_1_tADL_SHIFT                              0
+#define BCHP_NAND_TIMING_1_tADL_DEFAULT                            11
+
+/***************************************************************************
+ *TIMING_2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CLK_SELECT_MASK                         0x80000000
+#define BCHP_NAND_TIMING_2_CLK_SELECT_SHIFT                        31
+#define BCHP_NAND_TIMING_2_CLK_SELECT_DEFAULT                      0
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_108                      0
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_216                      1
+
+/* NAND :: TIMING_2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_reserved0_MASK                          0x7fffe000
+#define BCHP_NAND_TIMING_2_reserved0_SHIFT                         13
+
+/* NAND :: TIMING_2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_tWB_MASK                                0x00001e00
+#define BCHP_NAND_TIMING_2_tWB_SHIFT                               9
+#define BCHP_NAND_TIMING_2_tWB_DEFAULT                             15
+
+/* NAND :: TIMING_2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_tWHR_MASK                               0x000001f0
+#define BCHP_NAND_TIMING_2_tWHR_SHIFT                              4
+#define BCHP_NAND_TIMING_2_tWHR_DEFAULT                            9
+
+/* NAND :: TIMING_2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_tREAD_MASK                              0x0000000f
+#define BCHP_NAND_TIMING_2_tREAD_SHIFT                             0
+#define BCHP_NAND_TIMING_2_tREAD_DEFAULT                           6
+
+/***************************************************************************
+ *SEMAPHORE - Semaphore
+ ***************************************************************************/
+/* NAND :: SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_NAND_SEMAPHORE_reserved0_MASK                         0xffffff00
+#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT                        8
+
+/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK                    0x000000ff
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT                   0
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT                 0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID - Nand Flash Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK                      0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT                     24
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK                      0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT                     16
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK                      0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT                     8
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK                      0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT                     0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK                  0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT                 24
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK                  0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT                 16
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK                  0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT                 8
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK                  0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT                 0
+
+/***************************************************************************
+ *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
+ ***************************************************************************/
+/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT                8
+
+/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK                    0x000000ff
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT                   0
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT                 0
+
+/***************************************************************************
+ *INTFC_STATUS - Nand Flash Interface Status
+ ***************************************************************************/
+/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK                     0x80000000
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT                    31
+
+/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK                    0x40000000
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT                   30
+
+/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK                    0x20000000
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT                   29
+
+/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK               0x10000000
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT              28
+
+/* NAND :: INTFC_STATUS :: ERASED [27:27] */
+#define BCHP_NAND_INTFC_STATUS_ERASED_MASK                         0x08000000
+#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT                        27
+
+/* NAND :: INTFC_STATUS :: reserved0 [26:08] */
+#define BCHP_NAND_INTFC_STATUS_reserved0_MASK                      0x07ffff00
+#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT                     8
+
+/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK                   0x000000ff
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT                  0
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT                0
+
+/***************************************************************************
+ *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT                 0
+
+/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT            0
+
+/***************************************************************************
+ *ECC_CORR_ADDR - ECC Correctable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT                    0
+
+/***************************************************************************
+ *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK                  0xfff80000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT                 19
+
+/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK                     0x00070000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT                    16
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT                  0
+
+/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK                0x0000ffff
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT               0
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT             0
+
+/***************************************************************************
+ *ECC_UNC_ADDR - ECC Uncorrectable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK                        0xffffffff
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT                       0
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT                     0
+
+/***************************************************************************
+ *READ_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT        0
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:05] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK               0xffffffe0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT              5
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD [04:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_MASK     0x0000001f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_SHIFT    0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_DEFAULT  1
+
+/***************************************************************************
+ *ONFI_STATUS - ONFI Status
+ ***************************************************************************/
+/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK                  0xf0000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT                 28
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT               0
+
+/* NAND :: ONFI_STATUS :: reserved0 [27:06] */
+#define BCHP_NAND_ONFI_STATUS_reserved0_MASK                       0x0fffffc0
+#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT                      6
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK              0x00000020
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT             5
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK              0x00000010
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT             4
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK              0x00000008
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT             3
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK              0x00000004
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT             2
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK              0x00000002
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT             1
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK              0x00000001
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT             0
+
+/***************************************************************************
+ *ONFI_DEBUG_DATA - ONFI Debug Data
+ ***************************************************************************/
+/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK             0xffffffff
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT            0
+
+/***************************************************************************
+ *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK               0xfff80000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT              19
+
+/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK                  0x00070000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT                 16
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT               0
+
+/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK             0x0000ffff
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT            0
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT          0
+
+/***************************************************************************
+ *FLASH_READ_ADDR - Flash Read Data Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT                    0
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT                  0
+
+/***************************************************************************
+ *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK             0xfff80000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT            19
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK                0x00070000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT               16
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT             0
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK           0x0000ffff
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT          0
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT        0
+
+/***************************************************************************
+ *PROGRAM_PAGE_ADDR - Page Program Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK                   0xffffffff
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT                  0
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT                0
+
+/***************************************************************************
+ *COPY_BACK_EXT_ADDR - Copy Back Extended Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK                0xfff80000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT               19
+
+/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK                   0x00070000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT                  16
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT                0
+
+/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK              0x0000ffff
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT             0
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT           0
+
+/***************************************************************************
+ *COPY_BACK_ADDR - Copy Back Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK                      0xffffffff
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT                     0
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT                   0
+
+/***************************************************************************
+ *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK              0xfff80000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT             19
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK                 0x00070000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT                16
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT              0
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK            0x0000ffff
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT           0
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT         0
+
+/***************************************************************************
+ *BLOCK_ERASE_ADDR - Block Erase Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK                    0xffffffff
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT                   0
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT                 0
+
+/***************************************************************************
+ *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
+ ***************************************************************************/
+/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT                 0
+
+/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT            0
+
+/***************************************************************************
+ *INV_READ_ADDR - Flash Invalid Data Address
+ ***************************************************************************/
+/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT                    0
+
+/***************************************************************************
+ *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
+ ***************************************************************************/
+/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK                 0xffffffff
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT                0
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT              0
+
+/***************************************************************************
+ *ACC_CONTROL_CS1 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS1 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS1 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS1 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS1 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS1_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS1 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS1 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS1_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS1_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS1_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS1_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS1_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS1_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS1_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS1_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS1_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS1_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS1_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS1 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS1 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS1_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS2 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS2 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS2 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS2 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS2 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS2_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS2 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS2 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS2_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS2_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS2_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS2_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS2 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS2_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS2_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS2_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS2_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS2_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS2_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS2_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS2_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS3 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS3 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS3 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS3 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS3 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS3_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS3 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS3 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS3_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS3_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS3_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS3_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS3 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS3_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS3_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS3_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS3_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS3_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS3_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS3_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS3 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS3 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS3_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS4 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS4 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS4 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS4 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS4 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS4_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS4 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS4 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS4_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS4_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS4_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS4_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS4 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS4_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS4_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS4_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS4_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS4_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS4_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS4_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS4 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS4 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS4_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS5 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS5 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS5 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS5 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS5 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS5 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS5 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS5 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS5 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS5 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS5 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS5 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS5 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS5 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS5 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS5_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS5_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS5 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS5 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS5_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS5_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS5 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS5 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS5_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS5_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS5 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS5 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS5_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS5_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS5 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS5 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS5_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS5_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS5 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS5 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS5_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS5_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS5_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS5 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS5_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS5_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS5_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS5 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS5_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS5_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS5_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS5 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS5_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS5_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS5_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS5 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS5_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS5_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS5_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS5 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS5_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS5_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS5_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS5 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS5_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS5_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS5_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS5 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS5_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS5_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS5_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS5 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS5 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS5 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS5_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS5_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS5 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS5_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS5_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS5_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS5 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS5_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS5_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS5_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS5 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS5_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS5_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS5_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT      255
+
+/***************************************************************************
+ *LL_OP - Nand Flash Low Level Operation
+ ***************************************************************************/
+/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
+#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK                           0x80000000
+#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT                          31
+#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT                        0
+
+/* NAND :: LL_OP :: reserved0 [30:20] */
+#define BCHP_NAND_LL_OP_reserved0_MASK                             0x7ff00000
+#define BCHP_NAND_LL_OP_reserved0_SHIFT                            20
+
+/* NAND :: LL_OP :: CLE [19:19] */
+#define BCHP_NAND_LL_OP_CLE_MASK                                   0x00080000
+#define BCHP_NAND_LL_OP_CLE_SHIFT                                  19
+#define BCHP_NAND_LL_OP_CLE_DEFAULT                                0
+
+/* NAND :: LL_OP :: ALE [18:18] */
+#define BCHP_NAND_LL_OP_ALE_MASK                                   0x00040000
+#define BCHP_NAND_LL_OP_ALE_SHIFT                                  18
+#define BCHP_NAND_LL_OP_ALE_DEFAULT                                0
+
+/* NAND :: LL_OP :: WE [17:17] */
+#define BCHP_NAND_LL_OP_WE_MASK                                    0x00020000
+#define BCHP_NAND_LL_OP_WE_SHIFT                                   17
+#define BCHP_NAND_LL_OP_WE_DEFAULT                                 0
+
+/* NAND :: LL_OP :: RE [16:16] */
+#define BCHP_NAND_LL_OP_RE_MASK                                    0x00010000
+#define BCHP_NAND_LL_OP_RE_SHIFT                                   16
+#define BCHP_NAND_LL_OP_RE_DEFAULT                                 0
+
+/* NAND :: LL_OP :: DATA [15:00] */
+#define BCHP_NAND_LL_OP_DATA_MASK                                  0x0000ffff
+#define BCHP_NAND_LL_OP_DATA_SHIFT                                 0
+#define BCHP_NAND_LL_OP_DATA_DEFAULT                               0
+
+/***************************************************************************
+ *LL_RDDATA - Nand Flash Low Level Read Data
+ ***************************************************************************/
+/* NAND :: LL_RDDATA :: reserved0 [31:16] */
+#define BCHP_NAND_LL_RDDATA_reserved0_MASK                         0xffff0000
+#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT                        16
+
+/* NAND :: LL_RDDATA :: DATA [15:00] */
+#define BCHP_NAND_LL_RDDATA_DATA_MASK                              0x0000ffff
+#define BCHP_NAND_LL_RDDATA_DATA_SHIFT                             0
+#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT                           0
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE                          0x00412a00
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_START                         0
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_END                           127
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE                  32
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+/* NAND :: FLASH_CACHEi :: WORD [31:00] */
+#define BCHP_NAND_FLASH_CACHEi_WORD_MASK                           0xffffffff
+#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT                          0
+
+
+#endif /* #ifndef BCHP_NAND_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_sata_top_ctrl.h b/include/linux/brcmstb/7231b0/bchp_sata_top_ctrl.h
new file mode 100644
index 0000000..2113ed2
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_sata_top_ctrl.h
@@ -0,0 +1,164 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:14:27 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_sata_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:26p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SATA_TOP_CTRL_H__
+#define BCHP_SATA_TOP_CTRL_H__
+
+/***************************************************************************
+ *SATA_TOP_CTRL - SATA3 MISC Control Registers
+ ***************************************************************************/
+#define BCHP_SATA_TOP_CTRL_Version               0x00180020 /* SATA3 Version Register */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL              0x00180024 /* SATA3 System Bus Access Control Register */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL               0x00180028 /* SATA3 Test Port Control register */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1            0x0018002c /* SATA3 phy interface control 1 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2            0x00180030 /* SATA3 phy interface control 2 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3            0x00180034 /* SATA3 phy interface control 3 */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT           0x00180038 /* SATA3 TP OUT */
+
+/***************************************************************************
+ *Version - SATA3 Version Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: Version :: reserved0 [31:08] */
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_MASK                  0xffffff00
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_SHIFT                 8
+
+/* SATA_TOP_CTRL :: Version :: major_version [07:04] */
+#define BCHP_SATA_TOP_CTRL_Version_major_version_MASK              0x000000f0
+#define BCHP_SATA_TOP_CTRL_Version_major_version_SHIFT             4
+#define BCHP_SATA_TOP_CTRL_Version_major_version_DEFAULT           0
+
+/* SATA_TOP_CTRL :: Version :: minor_version [03:00] */
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_MASK              0x0000000f
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_SHIFT             0
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_DEFAULT           1
+
+/***************************************************************************
+ *BUS_CTRL - SATA3 System Bus Access Control Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_31_17 [31:17] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_MASK            0xfffe0000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_SHIFT           17
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_DEFAULT         0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: overide_hwinit_registers [16:16] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_MASK  0x00010000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_SHIFT 16
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_DEFAULT 0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_15_8 [15:08] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_MASK             0x0000ff00
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_SHIFT            8
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_DEFAULT          0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: piodata_endian_ctrl [07:06] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_MASK       0x000000c0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SHIFT      6
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_DEFAULT    0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadata_endian_ctrl [05:04] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_MASK       0x00000030
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SHIFT      4
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_DEFAULT    0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadesc_endian_ctrl [03:02] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_MASK       0x0000000c
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SHIFT      2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_DEFAULT    0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: reg_endian_ctrl [01:00] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_MASK           0x00000003
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SHIFT          0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_DEFAULT        0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SwapEndianess  2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_HalfWordSwap   1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_NoSwap         0
+
+/***************************************************************************
+ *TP_CTRL - SATA3 Test Port Control register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: TP_CTRL :: tp_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_MASK                    0xffffffff
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_SHIFT                   0
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_DEFAULT                 0
+
+/***************************************************************************
+ *PHY_CTRL_1 - SATA3 phy interface control 1
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_1 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_DEFAULT             0
+
+/***************************************************************************
+ *PHY_CTRL_2 - SATA3 phy interface control 2
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_2 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_DEFAULT             0
+
+/***************************************************************************
+ *PHY_CTRL_3 - SATA3 phy interface control 3
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_3 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_DEFAULT             0
+
+/***************************************************************************
+ *SATA_TP_OUT - SATA3 TP OUT
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: SATA_TP_OUT :: TP_OUT [31:00] */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_MASK                 0xffffffff
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_SHIFT                0
+
+#endif /* #ifndef BCHP_SATA_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_sdio_0_cfg.h b/include/linux/brcmstb/7231b0/bchp_sdio_0_cfg.h
new file mode 100644
index 0000000..73d5931c
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_sdio_0_cfg.h
@@ -0,0 +1,589 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:17:51 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_sdio_0_cfg.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:26p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SDIO_0_CFG_H__
+#define BCHP_SDIO_0_CFG_H__
+
+/***************************************************************************
+ *SDIO_0_CFG - SDIO_0 (CARD) Configuration Registers
+ ***************************************************************************/
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1          0x00410100 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2          0x00410104 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL               0x00410108 /* SDIO TP_OUT Control Register */
+#define BCHP_SDIO_0_CFG_CAP_REG0                 0x0041010c /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_CAP_REG1                 0x00410110 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET1                  0x00410114 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET2                  0x00410118 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY           0x0041011c /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV               0x00410120 /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_IP_DLY                   0x00410130 /* SDIO Host input delay register */
+#define BCHP_SDIO_0_CFG_OP_DLY                   0x00410134 /* SDIO Host output delay register */
+#define BCHP_SDIO_0_CFG_SCRATCH                  0x004101fc /* SDIO Scratch Register */
+#define BCHP_SDIO_0_CFG_VERSION                  0x004101f0 /* SDIO VERSION Register */
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL1 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_SEL_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_MASK    0x80000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_SHIFT   31
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_DEFAULT 0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_LEV [30:30] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_MASK       0x40000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_SHIFT      30
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_DEFAULT    1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: CFG_RESERVED [29:29] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_MASK          0x20000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_SHIFT         29
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_DEFAULT       0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: RETUNING_REQ [28:28] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_MASK          0x10000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_SHIFT         28
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_DEFAULT       0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DDR_TAP_DELAY [27:24] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_MASK         0x0f000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_SHIFT        24
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_DEFAULT      0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DELAY_CTRL [23:21] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_MASK            0x00e00000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_SHIFT           21
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_DEFAULT         0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_ENA [20:20] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_MASK       0x00100000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_SHIFT      20
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_DEFAULT    1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_PULSE [19:19] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_MASK     0x00080000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_SHIFT    19
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_DEFAULT  0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DATA_PENDING [18:18] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_MASK          0x00040000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_SHIFT         18
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_DEFAULT       0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WR_FLUSH [17:17] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_MASK              0x00020000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_SHIFT             17
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_DEFAULT           0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: MF_NUM_WR [16:16] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_MASK             0x00010000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_SHIFT            16
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_DEFAULT          0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WORD_ABO [15:15] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_MASK              0x00008000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_SHIFT             15
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_DEFAULT           0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NBO [14:14] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_MASK             0x00004000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_SHIFT            14
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_DEFAULT          0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NHW [13:13] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_MASK             0x00002000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_SHIFT            13
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_DEFAULT          1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: BUFFER_ABO [12:12] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_MASK            0x00001000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_SHIFT           12
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_DEFAULT         1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_BUF_ACC [11:11] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_MASK           0x00000800
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_SHIFT          11
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_DEFAULT        1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SEQ_EN [10:10] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_MASK            0x00000400
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_SHIFT           10
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_DEFAULT         0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_RD_THRESH [09:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_MASK         0x000003e0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_SHIFT        5
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_DEFAULT      2
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SIZE [04:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_MASK              0x0000001f
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_SHIFT             0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_DEFAULT           4
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL2 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved0 [31:08] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_MASK             0xffffff00
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_SHIFT            8
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_BYTE [07:06] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_MASK     0x000000c0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_SHIFT    6
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_DEFAULT  0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved1 [05:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_MASK             0x00000020
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_SHIFT            5
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_HW [04:04] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_MASK       0x00000010
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_SHIFT      4
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_DEFAULT    0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_WR [03:02] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_MASK      0x0000000c
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_SHIFT     2
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_DEFAULT   0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_RD [01:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_MASK      0x00000003
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_SHIFT     0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_DEFAULT   0
+
+/***************************************************************************
+ *TP_OUT_SEL - SDIO TP_OUT Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TP_OUT_SEL :: reserved0 [31:01] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_MASK                  0xfffffffe
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_SHIFT                 1
+
+/* SDIO_0_CFG :: TP_OUT_SEL :: TP_OUT_SELECT [00:00] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_MASK              0x00000001
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_SHIFT             0
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_DEFAULT           0
+
+/***************************************************************************
+ *CAP_REG0 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG0 :: DDR50_SUPPORT [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_SHIFT               31
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_DEFAULT             0
+
+/* SDIO_0_CFG :: CAP_REG0 :: SD104_SUPPORT [30:30] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_MASK                0x40000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_SHIFT               30
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_DEFAULT             0
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDR50 [29:29] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_MASK                        0x20000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_SHIFT                       29
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_DEFAULT                     0
+
+/* SDIO_0_CFG :: CAP_REG0 :: SLOT_TYPE [28:27] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_MASK                    0x18000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_SHIFT                   27
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_DEFAULT                 0
+
+/* SDIO_0_CFG :: CAP_REG0 :: ASYNCH_INT_SUPPORT [26:26] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_MASK           0x04000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_SHIFT          26
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_DEFAULT        0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 64B_SYS_BUS_SUPPORT [25:25] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_MASK          0x02000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_SHIFT         25
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_DEFAULT       0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 1_8V_SUPPORT [24:24] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_MASK                 0x01000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_SHIFT                24
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_DEFAULT              0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_0V_SUPPORT [23:23] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_MASK                 0x00800000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_SHIFT                23
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_DEFAULT              0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_3V_SUPPORT [22:22] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_MASK                 0x00400000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_SHIFT                22
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_DEFAULT              1
+
+/* SDIO_0_CFG :: CAP_REG0 :: SUSP_RES_SUPPORT [21:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_MASK             0x00200000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_SHIFT            21
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_DEFAULT          1
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDMA_SUPPORT [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_MASK                 0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_SHIFT                20
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_DEFAULT              1
+
+/* SDIO_0_CFG :: CAP_REG0 :: HIGH_SPEED_SUPPORT [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_MASK           0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_SHIFT          19
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_DEFAULT        1
+
+/* SDIO_0_CFG :: CAP_REG0 :: ADMA2_SUPPORT [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_MASK                0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_SHIFT               18
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_DEFAULT             1
+
+/* SDIO_0_CFG :: CAP_REG0 :: EXTENDED_MEDIA_SUPPORT [17:17] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_MASK       0x00020000
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_SHIFT      17
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_DEFAULT    1
+
+/* SDIO_0_CFG :: CAP_REG0 :: MAX_BL [16:15] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_MASK                       0x00018000
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_SHIFT                      15
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_DEFAULT                    1
+
+/* SDIO_0_CFG :: CAP_REG0 :: BASE_FREQ [14:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_MASK                    0x00007f80
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_SHIFT                   7
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_DEFAULT                 100
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_CLK_UNIT [06:06] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_MASK             0x00000040
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_SHIFT            6
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_DEFAULT          1
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_FREQ [05:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_MASK                 0x0000003f
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_SHIFT                0
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_DEFAULT              50
+
+/***************************************************************************
+ *CAP_REG1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_REG_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_MASK             0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_SHIFT            31
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_DEFAULT          0
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved0 [30:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_MASK                    0x7fe00000
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_SHIFT                   21
+
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_1_stuff [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_MASK                  0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_SHIFT                 20
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_DEFAULT               0
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_BLK_MODE [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_MASK                 0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_SHIFT                19
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_DEFAULT              0
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_MODE [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_MASK                     0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_SHIFT                    18
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_DEFAULT                  1
+
+/* SDIO_0_CFG :: CAP_REG1 :: CLK_MULT [17:10] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_MASK                     0x0003fc00
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_SHIFT                    10
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_DEFAULT                  0
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_MODES [09:08] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_MASK               0x00000300
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_SHIFT              8
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_DEFAULT            2
+
+/* SDIO_0_CFG :: CAP_REG1 :: USE_TUNING [07:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_MASK                   0x00000080
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_SHIFT                  7
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_DEFAULT                0
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_TIMER [06:03] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_MASK               0x00000078
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_SHIFT              3
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_DEFAULT            10
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_D_SUPPORT [02:02] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_MASK             0x00000004
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_SHIFT            2
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_DEFAULT          0
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_C_SUPPORT [01:01] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_MASK             0x00000002
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_SHIFT            1
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_DEFAULT          0
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_A_SUPPORT [00:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_MASK             0x00000001
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_SHIFT            0
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_DEFAULT          0
+
+/***************************************************************************
+ *PRESET1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET1 :: PRESET1_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_DEFAULT           0
+
+/* SDIO_0_CFG :: PRESET1 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET100 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_MASK                     0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_SHIFT                    16
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_DEFAULT                  0
+
+/* SDIO_0_CFG :: PRESET1 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET50 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_MASK                      0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_SHIFT                     0
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_DEFAULT                   1
+
+/***************************************************************************
+ *PRESET2 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET2 :: PRESET2_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_DEFAULT           0
+
+/* SDIO_0_CFG :: PRESET2 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET25 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_MASK                      0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_SHIFT                     16
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_DEFAULT                   2
+
+/* SDIO_0_CFG :: PRESET2 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET12P5 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_MASK                    0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_SHIFT                   0
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_DEFAULT                 3
+
+/***************************************************************************
+ *SD_CLOCK_DELAY - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_SEL [31:31] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_MASK        0x80000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_SHIFT       31
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_DEFAULT     1
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY_OVERRIDE [30:30] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_MASK 0x40000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_SHIFT 30
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_DEFAULT 0
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved0 [29:12] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_MASK              0x3ffff000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_SHIFT             12
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: OUTPUT_CLOCK_DELAY [11:08] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_MASK     0x00000f00
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_SHIFT    8
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_DEFAULT  0
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INTERNAL_CLOCK_DELAY [07:04] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_MASK   0x000000f0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_SHIFT  4
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_DEFAULT 0
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_MASK      0x0000000f
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_SHIFT     0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_DEFAULT   0
+
+/***************************************************************************
+ *SD_PAD_DRV - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_PAD_DRV :: OVERRIDE_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_SHIFT               31
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_DEFAULT             0
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved0 [30:23] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_MASK                  0x7f800000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_SHIFT                 23
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CLK_VAL [22:20] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_MASK                    0x00700000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_SHIFT                   20
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_DEFAULT                 5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved1 [19:19] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_MASK                  0x00080000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_SHIFT                 19
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CMD_VAL [18:16] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_MASK                    0x00070000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_SHIFT                   16
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_DEFAULT                 5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved2 [15:15] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_MASK                  0x00008000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_SHIFT                 15
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT3_VAL [14:12] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_MASK                   0x00007000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_SHIFT                  12
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_DEFAULT                5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved3 [11:11] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_MASK                  0x00000800
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_SHIFT                 11
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT2_VAL [10:08] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_MASK                   0x00000700
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_SHIFT                  8
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_DEFAULT                5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved4 [07:07] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_MASK                  0x00000080
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_SHIFT                 7
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT1_VAL [06:04] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_MASK                   0x00000070
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_SHIFT                  4
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_DEFAULT                5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved5 [03:03] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_MASK                  0x00000008
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_SHIFT                 3
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT0_VAL [02:00] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_MASK                   0x00000007
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_SHIFT                  0
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_DEFAULT                5
+
+/***************************************************************************
+ *IP_DLY - SDIO Host input delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_DEFAULT                   0
+
+/* SDIO_0_CFG :: IP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: IP_DLY :: IP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_DEFAULT               3
+
+/* SDIO_0_CFG :: IP_DLY :: reserved1 [15:06] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_MASK                      0x0000ffc0
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_SHIFT                     6
+
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_DELAY [05:00] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_MASK                   0x0000003f
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_DEFAULT                0
+
+/***************************************************************************
+ *OP_DLY - SDIO Host output delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_DEFAULT                   0
+
+/* SDIO_0_CFG :: OP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: OP_DLY :: OP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_DEFAULT               3
+
+/* SDIO_0_CFG :: OP_DLY :: reserved1 [15:04] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_MASK                      0x0000fff0
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_SHIFT                     4
+
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_MASK                   0x0000000f
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_DEFAULT                0
+
+/***************************************************************************
+ *SCRATCH - SDIO Scratch Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SCRATCH :: SCRATCH_BITS [31:00] */
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_MASK                  0xffffffff
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_SHIFT                 0
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_DEFAULT               0
+
+/***************************************************************************
+ *VERSION - SDIO VERSION Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VERSION :: SD_VER [31:24] */
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_MASK                        0xff000000
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_SHIFT                       24
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_DEFAULT                     48
+
+/* SDIO_0_CFG :: VERSION :: MMC_VER [23:16] */
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_MASK                       0x00ff0000
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_SHIFT                      16
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_DEFAULT                    67
+
+/* SDIO_0_CFG :: VERSION :: REV [15:08] */
+#define BCHP_SDIO_0_CFG_VERSION_REV_MASK                           0x0000ff00
+#define BCHP_SDIO_0_CFG_VERSION_REV_SHIFT                          8
+#define BCHP_SDIO_0_CFG_VERSION_REV_DEFAULT                        160
+
+/* SDIO_0_CFG :: VERSION :: A2S_VER [07:00] */
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_MASK                       0x000000ff
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_SHIFT                      0
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_DEFAULT                    1
+
+#endif /* #ifndef BCHP_SDIO_0_CFG_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/7231b0/bchp_sun_top_ctrl.h
new file mode 100644
index 0000000..6d809d2
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_sun_top_ctrl.h
@@ -0,0 +1,6822 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug  8 18:42:10 2011
+ *                 MD5 Checksum         2fa181eb09c8005dabf78dab1495aac5
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_sun_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/3   8/9/11 5:02p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SUN_TOP_CTRL_H__
+#define BCHP_SUN_TOP_CTRL_H__
+
+/***************************************************************************
+ *SUN_TOP_CTRL - Top Control registers
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID         0x00404000 /* Chip family ID */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID             0x00404004 /* Product Revision ID */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x0040401c /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x00404020 /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x00404024 /* Bond option value register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x00404028 /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x0040402c /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x00404030 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x00404034 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x00404038 /* Semaphore channel 0 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x0040403c /* Semaphore channel 1 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x00404040 /* Semaphore channel 2 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x00404044 /* Semaphore channel 3 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x00404048 /* Semaphore channel 4 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x0040404c /* Semaphore channel 5 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x00404050 /* Semaphore channel 6 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x00404054 /* Semaphore channel 7 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x00404058 /* Semaphore channel 8 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x0040405c /* Semaphore channel 9 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x00404060 /* Semaphore channel 10 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x00404064 /* Semaphore channel 11 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x00404068 /* Semaphore channel 12 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x0040406c /* Semaphore channel 13 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x00404070 /* Semaphore channel 14 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x00404074 /* Semaphore channel 15 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x00404078 /* General watchdog timer 0 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x0040407c /* General watchdog timer 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x00404080 /* General control register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x00404084 /* General control register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x00404088 /* General control register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x0040408c /* General control register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x00404090 /* General control register 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x00404094 /* General control register 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x00404098 /* General status register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x0040409c /* General status register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x004040a0 /* General status register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x00404100 /* Pinmux control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x00404104 /* Pinmux control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x00404108 /* Pinmux control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x0040410c /* Pinmux control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x00404110 /* Pinmux control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x00404114 /* Pinmux control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x00404118 /* Pinmux control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x0040411c /* Pinmux control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x00404120 /* Pinmux control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x00404124 /* Pinmux control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10        0x00404128 /* Pinmux control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11        0x0040412c /* Pinmux control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12        0x00404130 /* Pinmux control register 12 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13        0x00404134 /* Pinmux control register 13 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14        0x00404138 /* Pinmux control register 14 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15        0x0040413c /* Pinmux control register 15 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16        0x00404140 /* Pinmux control register 16 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17        0x00404144 /* Pinmux control register 17 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18        0x00404148 /* Pinmux control register 18 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x0040414c /* Pad pull-up/pull-down control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x00404150 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x00404154 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x00404158 /* Pad pull-up/pull-down control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x0040415c /* Pad pull-up/pull-down control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5     0x00404160 /* Pad pull-up/pull-down control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6     0x00404164 /* Pad pull-up/pull-down control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7     0x00404168 /* Pad pull-up/pull-down control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8     0x0040416c /* Pad pull-up/pull-down control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9     0x00404170 /* Pad pull-up/pull-down control register 9 */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x00404174 /* Bypass clock unselect register 0 */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x00404300 /* Reset control */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE    0x00404304 /* Reset source enable */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET        0x00404308 /* Software master reset */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION     0x0040430c /* Hardware reset extension */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR          0x00404310 /* Reset Monitor */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x00404314 /* Reset history */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET          0x00404318 /* Software init 0 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR        0x0040431c /* Software init 0 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS       0x00404320 /* Software init 0 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR  0x00404324 /* Security software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET          0x00404330 /* Software init 1 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR        0x00404334 /* Software init 1 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS       0x00404338 /* Software init 1 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR  0x0040433c /* Security software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x00404364 /* Scratch register */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x00404368 /* Spare control bits reserved for future use */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x00404380 /* Test port control */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x00404384 /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x00404388 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x0040438c /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x00404390 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x00404394 /* EJTAG input bus enables */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x00404398 /* EJTAG output select */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL        0x0040439c /* UART Router select */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL             0x004043a0 /* VTRAP Control */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS           0x004043a4 /* VTRAP Status */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x00404400 /* Serial Slave Port configuration register */
+#define BCHP_SUN_TOP_CTRL_SERS_REV               0x00404420 /* SERS Revision Register */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x00404424 /* SERS Configuration Register */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x00404514 /* Block select for RO testmode */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION     0x00404518 /* Test configuration */
+
+/***************************************************************************
+ *CHIP_FAMILY_ID - Chip family ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT    1915813904
+
+/***************************************************************************
+ *PRODUCT_ID - Product Revision ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK               0xffffffff
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT            1915813904
+
+/***************************************************************************
+ *BSP_FEATURE_TABLE_ADDR - BSP feature table address
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_VALUE_0 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:09] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xfffffe00
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            9
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [08:05] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK      0x000001e0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT   7
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [04:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_DEFAULT 0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_ebi_cs_swap [03:03] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_cs_swap_MASK     0x00000008
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_cs_swap_SHIFT    3
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_cs_swap_DEFAULT  0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_spare0 [02:02] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare0_MASK          0x00000004
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare0_SHIFT         2
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare0_DEFAULT       0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_spare1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare1_MASK          0x00000002
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare1_SHIFT         1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare1_DEFAULT       0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_spare4 [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare4_MASK          0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare4_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare4_DEFAULT       0
+
+/***************************************************************************
+ *STRAP_VALUE_1 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xfffffff0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            4
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias_sel [03:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_MASK  0x0000000e
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_DEFAULT 4
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK     0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT  1
+
+/***************************************************************************
+ *BOND_STATUS - Bond option value register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1
+
+/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_0 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_5 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_5_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_5_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_4 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_4_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_3 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_2 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_1 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_0 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_jtag_0 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_jtag_0_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_jtag_0_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_jtag_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb3_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb3_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb3_disable_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb3_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb2_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb2_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb2_disable_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb2_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb1_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb1_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb1_disable_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb1_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb0_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb0_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb0_disable_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb0_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_genet1_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet1_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet1_disable_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet1_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_svc_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hd_display_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sata_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ephy_disable [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb23_otg_disable [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb23_otg_disable_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb23_otg_disable_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb23_otg_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb01_otg_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb01_otg_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb01_otg_disable_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb01_otg_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_1 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_30 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_29 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_28 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_27 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_26 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_25 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_24 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_23 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_22 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_21 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_20 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_19 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_18 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_17 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_16 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_15 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_14 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_0 [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_DEFAULT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_0 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_5 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_5_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_5_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_4 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_4_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_4_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_3 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_3_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_3_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_2 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_2_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_2_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_1 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_0 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_jtag_0 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_jtag_0_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_jtag_0_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb3_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb3_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb3_disable_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb2_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb2_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb2_disable_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb1_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb1_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb1_disable_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb0_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb0_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb0_disable_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_genet1_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet1_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet1_disable_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_svc_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_svc_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_svc_disable_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hd_display_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sata_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ephy_disable [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb23_otg_disable [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb23_otg_disable_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb23_otg_disable_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb01_otg_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb01_otg_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb01_otg_disable_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_1 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_30 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_30_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_30_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_29 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_28 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_27 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_26 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_25 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_24 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_23 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_22 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_21 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_20 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_19 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_18 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_17 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_16 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_15 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_14 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 6
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 2
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_0 [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_SHIFT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_SHIFT 0
+
+/***************************************************************************
+ *SEMAPHORE_0 - Semaphore channel 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_1 - Semaphore channel 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_2 - Semaphore channel 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_3 - Semaphore channel 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_4 - Semaphore channel 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_5 - Semaphore channel 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_6 - Semaphore channel 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_7 - Semaphore channel 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_8 - Semaphore channel 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_9 - Semaphore channel 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_10 - Semaphore channel 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_11 - Semaphore channel 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_12 - Semaphore channel 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_13 - Semaphore channel 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_14 - Semaphore channel 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_15 - Semaphore channel 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *GEN_WATCHDOG_0 - General watchdog timer 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0
+
+/***************************************************************************
+ *GEN_WATCHDOG_1 - General watchdog timer 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK     0x80000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT    31
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK     0x40000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT    30
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK     0x20000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT    29
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK     0x10000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT    28
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK     0x02000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT    25
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK     0x01000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT    24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK     0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT    23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK     0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT    22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK     0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT    21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK     0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT    20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb1_pwrflt_4_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_pwrflt_4_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_pwrflt_4_disable_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_pwrflt_4_disable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb1_pwrflt_3_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_pwrflt_3_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_pwrflt_3_disable_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_pwrflt_3_disable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb0_pwrflt_2_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_pwrflt_2_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_pwrflt_2_disable_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_pwrflt_2_disable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb0_pwrflt_1_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_pwrflt_1_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_pwrflt_1_disable_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_pwrflt_1_disable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb1_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_mode_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_mode_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_mode_DEFAULT         0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb0_mode [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_DEFAULT         0
+
+/***************************************************************************
+ *GENERAL_CTRL_1 - General control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0xffff0000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           16
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_2 - General control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_3 - General control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_4 - General control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_5 - General control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK          0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT         8
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_1 - General status register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_2 - General status register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   8
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_mode [07:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_MASK 0x000000f0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_mode [03:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: mtsif_hys_en [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_mtsif_hys_en_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_mtsif_hys_en_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_mtsif_hys_en_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK    0xff000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT   24
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: mii_drive_src_0 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: mii_drive_sel_0 [22:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_MASK 0x00700000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_4 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_4_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_4_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_4 [18:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_MASK 0x00070000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_3 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_3_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_3_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_3 [14:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_MASK 0x00007000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_2 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_2_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_2_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_2 [10:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_MASK 0x00000700
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_1 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_1_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_1_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_1 [06:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_MASK 0x00000070
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_0 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_0_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_0_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_0 [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_16MA 7
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xfff00000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   20
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_069 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_069_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_069_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_069_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_068 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_068_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_068_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_068_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_066 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_066_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_066_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_066_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_065 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_065_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_065_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_065_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_064 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_064_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_064_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_064_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_063 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_063_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_063_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_063_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_062 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_062_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_062_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_062_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_061 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_061_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_061_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_061_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_060 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_060_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_060_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_060_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_059 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_059_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_059_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_059_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_058 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_058_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_058_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_058_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_055 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_055_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_055_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_055_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_054 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_054_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_054_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_054_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_053 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_053_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_053_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_053_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_052 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_052_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_052_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_052_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_051 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_051_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_051_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_051_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_050 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_050_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_050_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_050_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_049 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_049_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_049_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_049_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_048 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_048_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_048_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_048_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_047 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_047_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_047_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_047_DEFAULT 1
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xffc00000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   22
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_pwrdn [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_MASK    0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_SHIFT   21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_vregcntl [20:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_MASK 0x001ffffe
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_vregcntl_en [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_DEFAULT 1
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xffffff80
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_hys_en [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_oeb [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_do [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_src [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DEFAULT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_16MA 7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_07 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_GPIO_07           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_EBI_ADDR7         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_PM_GPIO_07        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_06 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_GPIO_06           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_EBI_ADDR6         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_PM_GPIO_06        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_05 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_GPIO_05           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_EBI_ADDR5         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_PM_GPIO_05        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_04 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_GPIO_04           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_EBI_ADDR4         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_PM_GPIO_04        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_03 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_GPIO_03           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_EBI_ADDR3         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_PM_GPIO_03        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_02 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_GPIO_02           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_EBI_ADDR2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_PM_GPIO_02        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_01 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_GPIO_01           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_EBI_ADDR1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_PM_GPIO_01        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_00 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_GPIO_00           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_EBI_ADDR0         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_PM_GPIO_00        2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_15 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_15_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_15_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_15_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_15_GPIO_15           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_15_EBI_WAITB         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_15_PM_GPIO_15        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_14 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_14_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_14_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_14_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_14_GPIO_14           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_14_EBI_ADDR14        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_14_PM_GPIO_14        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_13 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_13_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_13_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_13_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_13_GPIO_13           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_13_EBI_ADDR13        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_13_PM_GPIO_13        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_12 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_12_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_12_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_12_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_12_GPIO_12           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_12_EBI_ADDR12        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_12_PM_GPIO_12        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_11 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_GPIO_11           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_EBI_ADDR11        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_PM_GPIO_11        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_10 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_GPIO_10           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_EBI_ADDR10        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_PM_GPIO_10        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_09 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_GPIO_09           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_EBI_ADDR9         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_PM_GPIO_09        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_08 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_GPIO_08           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_EBI_ADDR8         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_PM_GPIO_08        2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_25 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_25_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_25_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_25_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_25_GPIO_25           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_25_EBI_DATA0         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_25_TP_IN_25          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_25_PM_GPIO_25        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_24 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_24_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_24_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_24_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_24_GPIO_24           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_24_EBI_CS4B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_24_SPI_M_SS0B        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_24_PM_GPIO_24        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_23 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_23_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_23_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_23_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_23_GPIO_23           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_23_EBI_CS3B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_23_PM_GPIO_23        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_22 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_22_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_22_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_22_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_22_GPIO_22           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_22_EBI_CS2B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_22_TP_IN_24          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_22_PM_GPIO_22        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_21 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_21_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_21_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_21_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_21_GPIO_21           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_21_EBI_CS1B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_21_PM_GPIO_21        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_20 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_20_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_20_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_20_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_20_GPIO_20           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_20_EBI_CS0B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_20_PM_GPIO_20        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_19 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_19_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_19_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_19_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_19_GPIO_19           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_19_EBI_RWB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_19_PM_GPIO_19        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_16 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_GPIO_16           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_EBI_WE1B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_PM_GPIO_16        2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_33 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_33_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_33_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_33_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_33_GPIO_33           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_33_EBI_DATA8         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_33_SC1_VCC           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_33_PM_GPIO_33        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_32 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_32_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_32_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_32_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_32_GPIO_32           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_32_EBI_DATA7         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_32_TP_OUT_00         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_32_PM_GPIO_32        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_31 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_31_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_31_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_31_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_31_GPIO_31           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_31_EBI_DATA6         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_31_TP_IN_31          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_31_PM_GPIO_31        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_30 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_30_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_30_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_30_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_30_GPIO_30           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_30_EBI_DATA5         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_30_TP_IN_30          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_30_PM_GPIO_30        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_29 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_29_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_29_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_29_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_29_GPIO_29           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_29_EBI_DATA4         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_29_TP_IN_29          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_29_PM_GPIO_29        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_28 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_GPIO_28           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_EBI_DATA3         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_TP_IN_28          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_PM_GPIO_28        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_27 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_GPIO_27           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_EBI_DATA2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_TP_IN_27          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_PM_GPIO_27        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_26 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_GPIO_26           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_EBI_DATA1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_TP_IN_26          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_PM_GPIO_26        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_4 - Pinmux control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_41 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_41_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_41_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_41_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_41_GPIO_41           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_41_EBI_RDB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_41_TP_OUT_01         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_41_PM_GPIO_41        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_40 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_40_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_40_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_40_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_40_GPIO_40           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_40_EBI_DATA15        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_40_SPI_M_SCK         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_40_PM_GPIO_40        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_39 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_39_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_39_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_39_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_39_GPIO_39           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_39_EBI_DATA14        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_39_SPI_M_MISO        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_39_PM_GPIO_39        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_38 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_38_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_38_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_38_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_38_GPIO_38           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_38_EBI_DATA13        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_38_SPI_M_MOSI        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_38_PM_GPIO_38        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_37 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_37_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_37_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_37_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_37_GPIO_37           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_37_EBI_DATA12        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_37_SC1_PRES          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_37_PM_GPIO_37        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_36 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_GPIO_36           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_EBI_DATA11        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_SC1_IO            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_PM_GPIO_36        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_35 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_GPIO_35           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_EBI_DATA10        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_SC1_RST           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_PM_GPIO_35        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_34 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_GPIO_34           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_EBI_DATA9         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_SC1_CLK           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_PM_GPIO_34        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_5 - Pinmux control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_49 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_49_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_49_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_49_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_49_GPIO_49           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_49_POD2CHIP_MDI2     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_49_PPKT_I_DATA_2     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_49_PM_GPIO_49        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_48 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_48_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_48_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_48_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_48_GPIO_48           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_48_POD2CHIP_MDI1     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_48_PPKT_I_DATA_1     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_48_PM_GPIO_48        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_47 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_47_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_47_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_47_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_47_GPIO_47           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_47_POD2CHIP_MDI0     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_47_PPKT_I_DATA_0     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_47_PM_GPIO_47        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_46 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_46_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_46_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_46_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_46_GPIO_46           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_46_POD2CHIP_MCLKI    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_46_PPKT_I_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_46_EBI_ADDR14        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_46_PM_GPIO_46        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_45 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_45_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_45_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_45_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_45_GPIO_45           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_45_NAND_RBB          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_45_TP_OUT_05         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_45_PM_GPIO_45        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_44 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_GPIO_44           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_EBI_TSB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_OUT_04         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_PM_GPIO_44        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_43 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_GPIO_43           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_EBI_DSB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_OUT_03         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_PM_GPIO_43        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_42 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_GPIO_42           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_EBI_WE0B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_OUT_02         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_PM_GPIO_42        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_6 - Pinmux control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_57 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_57_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_57_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_57_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_57_GPIO_57           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_57_CHIP2POD_MCLKO    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_57_RMXP_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_57_EBI_ADDR15        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_57_PM_GPIO_57        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_56 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_56_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_56_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_56_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_56_GPIO_56           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_56_POD2CHIP_MIVAL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_56_PPKT_I_VALID      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_56_PM_GPIO_56        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_55 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_55_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_55_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_55_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_55_GPIO_55           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_55_POD2CHIP_MISTRT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_55_PPKT_I_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_55_PM_GPIO_55        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_54 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_54_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_54_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_54_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_54_GPIO_54           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_54_POD2CHIP_MDI7     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_54_PPKT_I_DATA_7     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_54_PM_GPIO_54        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_53 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_53_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_53_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_53_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_53_GPIO_53           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_53_POD2CHIP_MDI6     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_53_PPKT_I_DATA_6     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_53_PM_GPIO_53        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_52 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_GPIO_52           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_POD2CHIP_MDI5     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_PPKT_I_DATA_5     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_PM_GPIO_52        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_51 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_GPIO_51           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_POD2CHIP_MDI4     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_PPKT_I_DATA_4     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_PM_GPIO_51        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_50 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_GPIO_50           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_POD2CHIP_MDI3     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_PPKT_I_DATA_3     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_PM_GPIO_50        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_7 - Pinmux control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_65 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_65_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_65_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_65_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_65_GPIO_65           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_65_CHIP2POD_MDO7     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_65_RMXP_DATA7        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_65_EBI_ADDR25        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_65_PM_GPIO_65        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_64 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_64_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_64_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_64_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_64_GPIO_64           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_64_CHIP2POD_MDO6     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_64_RMXP_DATA6        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_64_EBI_ADDR24        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_64_PM_GPIO_64        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_63 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_63_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_63_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_63_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_63_GPIO_63           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_63_CHIP2POD_MDO5     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_63_RMXP_DATA5        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_63_EBI_ADDR23        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_63_PM_GPIO_63        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_62 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_62_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_62_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_62_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_62_GPIO_62           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_62_CHIP2POD_MDO4     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_62_RMXP_DATA4        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_62_EBI_ADDR22        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_62_PM_GPIO_62        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_61 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_61_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_61_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_61_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_61_GPIO_61           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_61_CHIP2POD_MDO3     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_61_RMXP_DATA3        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_61_EBI_ADDR21        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_61_PM_GPIO_61        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_60 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_GPIO_60           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_CHIP2POD_MDO2     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_RMXP_DATA2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_EBI_ADDR20        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_PM_GPIO_60        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_59 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_GPIO_59           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_CHIP2POD_MDO1     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_RMXP_DATA1        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_EBI_ADDR19        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_PM_GPIO_59        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_58 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_GPIO_58           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_CHIP2POD_MDO0     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_RMXP_DATA0        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_EBI_ADDR18        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_PM_GPIO_58        4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_8 - Pinmux control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_73 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_73_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_73_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_73_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_73_GPIO_73           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_73_MPOD_M_SDI        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_73_PM_GPIO_73        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_72 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_72_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_72_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_72_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_72_GPIO_72           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_72_MPOD_M_SDO        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_72_EBI_ADDR0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_72_PM_GPIO_72        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_71 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_71_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_71_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_71_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_71_GPIO_71           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_71_MPOD_SCLK         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_71_EBI_ADDR1         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_71_PM_GPIO_71        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_70 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_70_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_70_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_70_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_70_GPIO_70           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_70_MPOD_SCTL         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_70_EBI_ADDR2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_70_PM_GPIO_70        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_69 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_69_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_69_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_69_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_69_GPIO_69           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_69_CHIP2POD_MOCLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_69_RMXP_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_69_EBI_ADDR12        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_69_PM_GPIO_69        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_68 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_GPIO_68           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_POD2CHIP_MICLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_PPKT_I_ERROR      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_EBI_ADDR13        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_PM_GPIO_68        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_67 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_GPIO_67           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_CHIP2POD_MOVAL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_RMXP_VALID        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_EBI_ADDR16        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_PM_GPIO_67        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_66 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_GPIO_66           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_CHIP2POD_MOSTRT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_RMXP_SYNC         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_EBI_ADDR17        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_PM_GPIO_66        4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_9 - Pinmux control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_81 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_81_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_81_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_81_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_81_GPIO_81           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_81_SC0_RST           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_81_TP_OUT_08         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_81_PM_GPIO_81        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_80 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_80_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_80_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_80_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_80_GPIO_80           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_80_SC0_CLK           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_80_TP_OUT_07         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_80_PM_GPIO_80        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_79 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_79_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_79_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_79_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_79_GPIO_79           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_79_SC0_VCC           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_79_TEST_THP          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_79_TP_OUT_06         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_79_PM_GPIO_79        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_78 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_78_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_78_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_78_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_78_GPIO_78           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_78_RMX0_PAUSE        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_78_I2S_LR0_IN        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_78_P1_INTR_1         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_78_PM_GPIO_78        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_77 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_77_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_77_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_77_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_77_GPIO_77           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_77_RMX0_VALID        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_77_SPI_M_SS1B        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_77_PM_GPIO_77        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_76 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_GPIO_76           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_RMX0_SYNC         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_CLK_OBSRV3        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_PM_GPIO_76        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_75 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_GPIO_75           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_RMX0_DATA         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_CLK_OBSRV2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_PM_GPIO_75        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_74 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_GPIO_74           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_RMX0_CLK          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_RO_OBSRV          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_CLK_OBSRV1        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_PM_GPIO_74        4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_10 - Pinmux control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_89 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_89_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_89_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_89_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_89_GPIO_89          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_89_PKT1_SYNC        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_89_PPKT_I_SYNC      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_89_MTSIF0_SYNC      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_89_TP_OUT_16        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_89_PM_GPIO_89       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_88 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_88_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_88_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_88_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_88_GPIO_88          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_88_PKT1_DATA        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_88_PPKT_I_VALID     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_88_MTSIF0_DATA0     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_88_TP_IN_11         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_88_PM_GPIO_88       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_87 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_87_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_87_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_87_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_87_GPIO_87          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_87_PKT1_CLK         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_87_PPKT_I_CLK       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_87_MTSIF0_CLK       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_87_TP_IN_10         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_87_PM_GPIO_87       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_86 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_86_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_86_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_86_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_86_GPIO_86          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_86_SC0_VPP          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_86_POD_EBI_DSB      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_86_I2S_LR0_OUT      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_86_TP_OUT_13        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_86_PM_GPIO_86       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_85 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_85_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_85_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_85_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_85_GPIO_85          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_85_SC0_AUX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_85_POD_EBI_WE0B     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_85_I2S_DATA0_OUT    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_85_TP_OUT_12        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_85_PM_GPIO_85       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_84 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_GPIO_84          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_SC0_AUX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_POD_EBI_RDB      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_I2S_CLK0_OUT     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_TP_OUT_11        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_PM_GPIO_84       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_83 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_GPIO_83          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_SC0_PRES         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_TP_OUT_10        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_PM_GPIO_83       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_82 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_GPIO_82          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_SC0_IO           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_TP_OUT_09        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_PM_GPIO_82       3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_11 - Pinmux control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_97 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_97_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_97_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_97_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_97_GPIO_97          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_97_UART_RX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_97_IR_OUT           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_97_I2S_LR0_OUT      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_97_POD2CHIP_MCLKI   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_97_ALT_TP_IN_1      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_97_PM_GPIO_97       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_96 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_96_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_96_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_96_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_96_GPIO_96          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_96_UART_TX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_96_PWM0             2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_96_I2S_DATA0_OUT    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_96_POD_EBI_DSB      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_96_ALT_TP_OUT_1     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_96_PM_GPIO_96       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_95 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_95_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_95_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_95_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_95_GPIO_95          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_95_UART_RX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_95_VEC_VSYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_95_I2S_CLK0_OUT     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_95_POD_EBI_WE0B     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_95_ALT_TP_IN_0      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_95_PM_GPIO_95       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_94 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_94_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_94_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_94_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_94_GPIO_94          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_94_UART_TX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_94_VEC_HSYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_94_POD_EBI_RDB      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_94_ALT_TP_OUT_0     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_94_PM_GPIO_94       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_93 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_93_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_93_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_93_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_93_GPIO_93          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_93_SPI_S_SSB        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_93_UART_RX0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_93_ALT_TP_IN_2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_93_PM_GPIO_93       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_92 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_GPIO_92          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_SPI_S_MISO       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_UART_TX0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_ALT_TP_OUT_2     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_PM_GPIO_92       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_91 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_GPIO_91          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_PKT1_ERROR       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_PKT3_DATA        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_MTSIF0_DATA1     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_TP_OUT_18        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_PM_GPIO_91       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_90 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_GPIO_90          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_PKT1_VALID       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_PKT3_CLK         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_PPKT_I_ERROR     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_TP_OUT_17        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_PM_GPIO_90       5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_12 - Pinmux control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_106 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_106_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_106_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_106_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_106_GPIO_106        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_106_USB0_PWRON_1    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_106_TP_OUT_27       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_106_PM_GPIO_106     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_105 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_GPIO_105        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_PKT2_ERROR      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_VEC_HSYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_UART_CTS2       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_CODEC_FSYNCB    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_SPI_M_SS1B      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_MTSIF0_DATA5    6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_TP_OUT_26       7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_PM_GPIO_105     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_104 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_GPIO_104        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_PKT2_VALID      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_PKT3_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_IR_OUT          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_UART_RX2        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_CODEC_SDI       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_SPI_M_MISO      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_MTSIF_ATS_RST   7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_TP_OUT_25       8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_PM_GPIO_104     9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_103 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_GPIO_103        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_PKT2_SYNC       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_CODEC_MCLK      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_SPI_M_SCK       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_MTSIF0_DATA4    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_TP_OUT_24       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_PM_GPIO_103     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_102 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_GPIO_102        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_PKT2_DATA       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_HD_DVI0_0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_SATA_MDCLK      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_UART_RTS2       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_CODEC_SDO       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_SPI_M_SS0B      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_MTSIF0_DATA3    7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_TP_OUT_23       8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_PM_GPIO_102     9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_101 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_GPIO_101        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_PKT2_CLK        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_HD_DVI0_10      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SATA_MDIO       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_UART_TX2        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_CODEC_SCLK      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SPI_M_MOSI      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_MTSIF0_DATA2    7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_TP_OUT_22       8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_PM_GPIO_101     9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_99 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_GPIO_99          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SF_WPB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_EXT_IRQ3         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PWM0             3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_UART_RTS0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_I2S_DATA0_IN     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PM_GPIO_99       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_98 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_GPIO_98          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SF_HOLDB         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_EXT_IRQ2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_VEC_VSYNC        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_UART_CTS0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_I2S_CLK0_IN      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_PM_GPIO_98       6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_13 - Pinmux control register 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_114 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_GPIO_114        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_ENET0_ACTIVITY  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_PWM1            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_CLK_OBSRV       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_CLK_27M         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_AUD_FS_CLK0     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_SC_CLK_OUT      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_ENET1_ACTIVITY  7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_ENET1_LINK      8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_TP_OUT_29       9
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_PM_GPIO_114     10
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_113 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_113_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_113_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_113_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_113_GPIO_113        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_113_USB1_PWRFLT_4   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_113_RMX1_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_113_PM_GPIO_113     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_112 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_GPIO_112        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_USB1_PWRFLT_3   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_RMX1_PAUSE      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_P1_INTR_1       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_PM_GPIO_112     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_111 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_GPIO_111        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_USB0_PWRFLT_2   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_EXT_IRQ5        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_SDIO0_VCTL      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_PM_GPIO_111     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_110 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_GPIO_110        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_USB0_PWRFLT_1   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_EXT_IRQ4        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_TP_OUT_31       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_PM_GPIO_110     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_109 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_GPIO_109        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_USB1_PWRON_4    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_RMX1_DATA       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_PM_GPIO_109     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_108 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_GPIO_108        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_USB1_PWRON_3    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_RMX1_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_PM_GPIO_108     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_107 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_GPIO_107        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_USB0_PWRON_2    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_TP_OUT_28       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_PM_GPIO_107     3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_14 - Pinmux control register 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_126 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_126_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_126_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_126_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_126_GPIO_126        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_126_SDIO0_DAT0      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_126_I2S_DATA0_OUT   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_126_VO0_656_3       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_126_PPKT_I_DATA_3   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_126_PM_GPIO_126     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_125 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_125_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_125_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_125_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_125_GPIO_125        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_125_SDIO0_CLK       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_125_I2S_CLK0_OUT    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_125_VO0_656_2       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_125_PPKT_I_DATA_2   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_125_PM_GPIO_125     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_124 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_GPIO_124        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_SDIO0_PWR0      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_VO0_656_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_PPKT_I_DATA_1   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_PM_GPIO_124     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_123 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_GPIO_123        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_SDIO0_WPROT     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_VO0_656_0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_PPKT_I_DATA_0   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_PM_GPIO_123     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_122 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_122_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_122_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_122_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_122_GPIO_122        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_122_SDIO0_CMD       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_122_VO0_656_CLK     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_122_PM_GPIO_122     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_118 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_GPIO_118        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_PKT4_SYNC       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_I2S_LR0_IN      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_I2S_LR0_OUT     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_EXT_IRQ2        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_HD_DVI0_11      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SC1_AUX2        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_MTSIF0_DATA7    7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_I2S_LR1_OUT     8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_TP_IN_09        9
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_PM_GPIO_118     10
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_117 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_GPIO_117        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_PKT4_DATA       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_I2S_DATA0_IN    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_I2S_DATA0_OUT   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_EXT_IRQ1        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_HD_DVI0_20      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SC1_AUX1        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_MTSIF0_DATA6    7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_I2S_DATA1_OUT   8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_TP_OUT_19       9
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_PM_GPIO_117     10
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_116 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_GPIO_116        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_PKT4_CLK        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_I2S_CLK0_IN     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_I2S_CLK0_OUT    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_EXT_IRQ0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_HD_DVI0_21      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SC1_VPP         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_MTSIF_ATS_INC   7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_I2S_CLK1_OUT    8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_TP_IN_23        9
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_PM_GPIO_116     10
+
+/***************************************************************************
+ *PIN_MUX_CTRL_15 - Pinmux control register 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_134 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_134_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_134_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_134_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_134_GPIO_134        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_134_MII_RX_CLK      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_134_EBI_ADDR17      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_134_HD_DVI0_22      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_134_PM_GPIO_134     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_133 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_133_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_133_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_133_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_133_GPIO_133        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_133_MII_RX_ER       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_133_POD_EBI_WE0B    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_133_PKT4_CLK        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_133_HD_DVI0_23      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_133_PM_GPIO_133     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_132 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_GPIO_132        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_MII_RX_DV       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_EBI_ADDR16      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_HD_DVI0_24      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_PM_GPIO_132     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_131 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_GPIO_131        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_SDIO0_LED       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_VEC_HSYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_PM_GPIO_131     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_130 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_GPIO_130        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_SDIO0_PRES      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_I2S_LR0_IN      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_VO0_656_7       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_PPKT_I_DATA_7   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_PM_GPIO_130     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_129 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_GPIO_129        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_SDIO0_DAT3      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_I2S_DATA0_IN    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_VO0_656_6       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_PPKT_I_DATA_6   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_PM_GPIO_129     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_128 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_GPIO_128        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_SDIO0_DAT2      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_I2S_CLK0_IN     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_VO0_656_5       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_PPKT_I_DATA_5   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_PM_GPIO_128     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_127 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_GPIO_127        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_SDIO0_DAT1      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_I2S_LR0_OUT     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_VO0_656_4       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_PPKT_I_DATA_4   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_PM_GPIO_127     5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_16 - Pinmux control register 16
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_142 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_142_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_142_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_142_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_142_GPIO_142        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_142_MII_RXD_00      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_142_EBI_ADDR22      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_142_SC1_PRES        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_142_HD_DVI0_DE      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_142_PM_GPIO_142     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_141 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_141_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_141_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_141_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_141_GPIO_141        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_141_MII_RXD_01      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_141_EBI_ADDR21      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_141_HD_DVI0_VS      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_141_PM_GPIO_141     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_140 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_GPIO_140        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_MII_RXD_02      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_EBI_ADDR20      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_HD_DVI0_HS      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_PM_GPIO_140     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_139 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_GPIO_139        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_MII_RXD_03      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_EBI_ADDR19      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_SPI_M_SS0B      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_PM_GPIO_139     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_138 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_GPIO_138        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_MII_TX_CLK      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_EBI_ADDR18      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_SPI_M_MISO      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_HD_DVI0_CLK     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_PM_GPIO_138     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_137 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_137_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_137_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_137_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_137_GPIO_137        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_137_MII_MDIO        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_137_PM_GPIO_137     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_136 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_GPIO_136        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_MII_CRS         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_EBI_ADDR15      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_POD_EBI_RDB     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_PKT4_SYNC       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_HD_DVI0_18      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_PM_GPIO_136     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_135 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_GPIO_135        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_MII_COL         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_POD_EBI_DSB     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_PKT4_DATA       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_HD_DVI0_19      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_PM_GPIO_135     5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_17 - Pinmux control register 17
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: sgpio_02 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_02_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_02_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_02_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_02_SGPIO_02        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_02_BSC_M1_SCL      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_149 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_149_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_149_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_149_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_149_GPIO_149        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_149_MII_MDC         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_149_SPI_M_SCK       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_149_PM_GPIO_149     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_148 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_GPIO_148        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_MII_TX_ER       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_POD2CHIP_MCLKI  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_HD_DVI0_25      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_PM_GPIO_148     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_147 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_GPIO_147        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_MII_TX_EN       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_EBI_ADDR27      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_SPI_M_MOSI      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_PM_GPIO_147     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_146 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_GPIO_146        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_MII_TXD_00      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_EBI_ADDR26      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_SC1_IO          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_HD_DVI0_26      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_PM_GPIO_146     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_145 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_GPIO_145        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_MII_TXD_01      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_EBI_ADDR25      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_SC1_RST         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_HD_DVI0_27      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_PM_GPIO_145     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_144 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_GPIO_144        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_MII_TXD_02      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_EBI_ADDR24      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_SC1_CLK         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_HD_DVI0_28      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_PM_GPIO_144     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_143 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_GPIO_143        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_MII_TXD_03      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_EBI_ADDR23      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_SC1_VCC         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_HD_DVI0_29      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_PM_GPIO_143     5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_18 - Pinmux control register 18
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_reserved0_MASK           0xfffff000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_reserved0_SHIFT          12
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: sgpio_05 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_05_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_05_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_05_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_05_SGPIO_05        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_05_BSC_M2_SDA      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_05_EXT_IRQ1        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: sgpio_04 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_04_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_04_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_04_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_04_SGPIO_04        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_04_BSC_M2_SCL      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: sgpio_03 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_03_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_03_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_03_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_03_SGPIO_03        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_03_BSC_M1_SDA      1
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_11_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_11_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_11_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_11_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_11_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_10_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_10_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_10_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_10_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_10_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_09_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_09_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_09_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_09_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_09_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_08_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_08_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_08_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_08_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_08_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_07_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_06_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_05_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_04_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_03_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_02_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_01_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_00_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_sck_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_MASK  0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_mosi_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_miso_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_28_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_28_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_28_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_28_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_28_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_28_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_28_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_27_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_27_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_27_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_27_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_27_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_27_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_27_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_26_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_26_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_26_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_26_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_26_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_26_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_26_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_25_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_25_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_25_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_25_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_25_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_25_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_25_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_24_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_24_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_24_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_24_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_24_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_24_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_24_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_23_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_23_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_23_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_23_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_23_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_23_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_23_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_22_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_21_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_20_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_19_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_16_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_15_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_14_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_13_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_12_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_43_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_43_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_43_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_43_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_43_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_43_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_43_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_42_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_42_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_42_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_42_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_42_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_42_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_42_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_41_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_41_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_41_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_41_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_41_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_41_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_41_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_40_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_40_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_40_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_40_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_40_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_40_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_40_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_39_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_38_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_37_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_36_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_35_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_34_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_33_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_32_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_31_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_30_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_29_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_58_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_58_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_58_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_58_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_58_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_58_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_58_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_57_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_57_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_57_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_57_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_57_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_57_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_57_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_56_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_56_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_56_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_56_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_56_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_56_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_56_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_55_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_55_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_55_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_55_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_55_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_55_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_55_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_54_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_53_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_52_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_51_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_50_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_49_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_48_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_47_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_46_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_45_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_44_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_73_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_73_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_73_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_73_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_73_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_73_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_73_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_72_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_72_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_72_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_72_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_72_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_72_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_72_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_71_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_71_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_71_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_71_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_71_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_71_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_71_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_70_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_70_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_70_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_70_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_70_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_70_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_70_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_69_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_68_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_67_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_66_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_65_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_64_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_63_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_62_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_61_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_60_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_59_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_88_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_88_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_88_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_88_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_88_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_88_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_88_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_87_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_87_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_87_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_87_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_87_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_87_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_87_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_86_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_86_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_86_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_86_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_86_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_86_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_86_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_85_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_85_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_85_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_85_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_85_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_85_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_85_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_84_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_83_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_82_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_81_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_80_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_79_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_78_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_77_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_76_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_75_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_74_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_104_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_104_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_104_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_104_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_104_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_104_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_104_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_103_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_103_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_103_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_103_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_103_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_103_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_103_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_102_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_102_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_102_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_102_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_102_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_102_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_102_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_101_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_101_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_101_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_101_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_101_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_101_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_101_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_99_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_98_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_97_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_96_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_95_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_95_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_95_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_95_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_95_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_95_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_95_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_94_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_93_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_92_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_91_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_90_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_89_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_123_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_123_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_123_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_123_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_123_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_123_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_123_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_122_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_122_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_122_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_122_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_122_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_122_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_122_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_118_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_118_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_118_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_118_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_118_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_118_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_118_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_117_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_117_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_117_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_117_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_117_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_117_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_117_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_116_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_114_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_113_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_112_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_111_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_110_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_109_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_108_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_107_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_106_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_106_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_106_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_106_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_106_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_106_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_106_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_105_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_138_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_138_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_138_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_138_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_138_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_138_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_138_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_137_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_137_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_137_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_137_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_137_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_137_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_137_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_136_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_136_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_136_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_136_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_136_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_136_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_136_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_135_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_135_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_135_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_135_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_135_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_135_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_135_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_134_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_134_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_134_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_134_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_134_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_134_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_134_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_133_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_133_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_133_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_133_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_133_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_133_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_133_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_132_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_132_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_132_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_132_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_132_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_132_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_132_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_131_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_131_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_131_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_131_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_131_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_131_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_131_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_130_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_130_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_130_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_130_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_130_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_130_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_130_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_129_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_129_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_129_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_129_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_129_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_129_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_129_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_128_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_128_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_128_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_128_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_128_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_128_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_128_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_127_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_127_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_127_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_127_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_127_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_127_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_127_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_126_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_126_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_126_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_126_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_126_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_126_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_126_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_125_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_125_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_125_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_125_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_125_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_125_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_125_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_124_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_9 - Pad pull-up/pull-down control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: spare_pad_ctrl_9 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: reserved0 [29:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved0_MASK        0x3fc00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved0_SHIFT       22
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_149_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_149_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_149_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_149_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_149_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_149_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_149_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_148_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_148_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_148_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_148_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_148_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_148_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_148_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_147_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_147_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_147_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_147_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_147_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_147_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_147_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_146_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_146_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_146_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_146_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_146_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_146_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_146_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_145_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_145_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_145_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_145_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_145_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_145_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_145_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_144_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_144_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_144_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_144_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_144_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_144_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_144_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_143_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_143_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_143_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_143_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_143_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_143_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_143_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_142_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_142_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_142_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_142_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_142_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_142_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_142_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_141_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_141_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_141_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_141_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_141_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_141_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_141_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_140_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_140_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_140_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_140_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_140_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_140_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_140_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_139_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_139_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_139_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_139_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_139_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_139_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_139_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_03_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_03_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_03_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_02_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_02_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_02_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_111 [01:01] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_111_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_111_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_111_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_20 [00:00] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_20_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_20_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_20_DEFAULT 1
+
+/***************************************************************************
+ *RESET_CTRL - Reset control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0xfffffffe
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               1
+
+/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT   0
+
+/***************************************************************************
+ *RESET_SOURCE_ENABLE - Reset source enable
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK       0xfffffc00
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT      10
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0
+
+/***************************************************************************
+ *SW_MASTER_RESET - Software master reset
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK           0xfffffffe
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT          1
+
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0
+
+/***************************************************************************
+ *HW_RESET_EXTENSION - Hardware reset extension
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0
+
+/***************************************************************************
+ *RESET_MONITOR - Reset Monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT  7
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT   6
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT   4
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset history
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:17] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xfffe0000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            17
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [16:16] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 16
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [15:15] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 15
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [14:14] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 14
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [13:13] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 13
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_reset [12:12] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_MASK    0x00001000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT   12
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_reset [11:11] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT    11
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [10:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT       10
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK       0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT      9
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_dl_sw_reset [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK  0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT 8
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 7
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 6
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK   0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT  4
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0
+
+/***************************************************************************
+ *SW_INIT_0_SET - Software init 0 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved0_MASK             0xc0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved0_SHIFT            30
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_MASK          0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_MASK   0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_SHIFT  28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_MASK        0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_SHIFT       27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK        0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT       26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_MASK          0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_SHIFT         25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK          0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK   0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT  23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_MASK   0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_SHIFT  22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK          0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT         21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_MASK   0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_SHIFT  20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK         0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT        19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK           0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT          18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK   0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT  17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_MASK         0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_SHIFT        16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK           0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT          15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK           0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT          14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_MASK   0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_SHIFT  13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_MASK          0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_MASK   0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_SHIFT  11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT       10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK           0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT          9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK           0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK           0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT          6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_SHIFT   4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT   0
+
+/***************************************************************************
+ *SW_INIT_0_CLEAR - Software init 0 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved0_MASK           0xc0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved0_SHIFT          30
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_MASK        0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_SHIFT       29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_MASK      0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_SHIFT     27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK      0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT     26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_MASK        0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_SHIFT       25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK        0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT       24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK        0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT       21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK       0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT      19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK         0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT        18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_MASK       0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK         0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT        15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK         0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT        14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_MASK        0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_SHIFT       12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK      0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT     10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK         0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT        9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK         0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK         0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT        6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT  0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *SW_INIT_0_STATUS - Software init 0 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved0_MASK          0xc0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved0_SHIFT         30
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_MASK       0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_SHIFT      29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_DEFAULT    1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_MASK       0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_SHIFT      25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK       0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK       0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT      21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK      0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT     19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK        0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT       18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_MASK      0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_DEFAULT   1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK        0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT       15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK        0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT       14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_MASK       0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_DEFAULT    1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK        0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT   2
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT       1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved0_MASK     0xc0000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved0_SHIFT    30
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_MASK  0x20000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_MASK  0x02000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK  0x01000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK  0x00200000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK   0x00040000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT  18
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK   0x00008000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT  15
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK   0x00004000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT  14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_svd0_sw_init_MASK  0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK   0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT  9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK   0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT  8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT  6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved0_SHIFT 30
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved0_MASK   0xc0000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved0_SHIFT  30
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_1_SET - Software init 1 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK             0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT            2
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT       1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_DEFAULT        0
+
+/***************************************************************************
+ *SW_INIT_1_CLEAR - Software init 1 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK           0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT          2
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_MASK         0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_DEFAULT      0
+
+/***************************************************************************
+ *SW_INIT_1_STATUS - Software init 1 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK     0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT    1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_DEFAULT     1
+
+/***************************************************************************
+ *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK     0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT    2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_SHIFT  0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xfffffffc
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK   0xfffffffc
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT  2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK  0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved0_SHIFT 30
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 1
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xfffffffc
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved0_SHIFT 30
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 1
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xfffffffc
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0
+
+/***************************************************************************
+ *SPARE_CTRL - Spare control bits reserved for future use
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT         0
+
+/***************************************************************************
+ *TEST_PORT_CTRL - Test port control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SOFT_MODEM_TP 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT         0
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 127
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0  0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET1  1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU     2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SATA    3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS     16
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK     17
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON     18
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     20
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     21
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE    22
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM    23
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC     25
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DVP_HT  26
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SVD0    27
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GFX     29
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO     30
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA   31
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     33
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0   35
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0    45
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB1    46
+
+/***************************************************************************
+ *TEST_PORT_OUT_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_OUT_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0
+
+/***************************************************************************
+ *EJTAG_INPUT_EN - EJTAG input bus enables
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           3
+
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 4
+
+/***************************************************************************
+ *EJTAG_OUTPUT_SEL - EJTAG output select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         3
+
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 2
+
+/***************************************************************************
+ *UART_ROUTER_SEL - UART Router select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK      0xf0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT     28
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK      0x0f000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT     24
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK      0x00f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK      0x000f0000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK      0x0000f000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK      0x00000f00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK      0x0000000f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15
+
+/***************************************************************************
+ *VTRAP_CTRL - VTRAP Control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK                0xfffff000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT               12
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_threshold [11:11] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_threshold [10:10] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_threshold [09:09] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_DEFAULT 1
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [08:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x000001f8
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 24
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_status_clear [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_status_clear [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_status_clear [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_DEFAULT 0
+
+/***************************************************************************
+ *VTRAP_STATUS - VTRAP Status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK              0xfffffff8
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT             3
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_status [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_status [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_status [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_DEFAULT 0
+
+/***************************************************************************
+ *SSP_CONFIG - Serial Slave Port configuration register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT        4
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT           0
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT     1
+
+/***************************************************************************
+ *SERS_REV - SERS Revision Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16
+
+/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT     0
+
+/***************************************************************************
+ *SERS_CFG - SERS Configuration Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT                1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT           0
+
+/* union - case mapped_buffer_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0
+
+/* union - case cmd_fifo_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 31
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 16
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT  0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT                 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT            0
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x00404428
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0
+
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x00404448
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0
+
+
+/***************************************************************************
+ *RO_TEST_BLOCK_SEL - Block select for RO testmode
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xffffffe0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        5
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_pwenb [04:04] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DEFAULT  1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_ENABLED  0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DISABLED 1
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [03:02] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MIN_LOAD 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MED_LOAD 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MAX_LOAD 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SVT_MIN_LOAD 3
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
+
+/***************************************************************************
+ *TEST_CONFIGURATION - Test configuration
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0
+
+#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_timer.h b/include/linux/brcmstb/7231b0/bchp_timer.h
new file mode 100644
index 0000000..1987416
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_timer.h
@@ -0,0 +1,340 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:13:07 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_timer.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 7:21p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_TIMER_H__
+#define BCHP_TIMER_H__
+
+/***************************************************************************
+ *TIMER - Watchdog & Programmable Timers
+ ***************************************************************************/
+#define BCHP_TIMER_TIMER_IS                      0x004067c0 /* TIMER INTERRUPT STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE0                     0x004067c4 /* TIMER CPU INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_TIMER0_CTRL                   0x004067c8 /* TIMER0 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER1_CTRL                   0x004067cc /* TIMER1 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER2_CTRL                   0x004067d0 /* TIMER2 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER3_CTRL                   0x004067d4 /* TIMER3 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER0_STAT                   0x004067d8 /* TIMER0 STATUS REGISTER */
+#define BCHP_TIMER_TIMER1_STAT                   0x004067dc /* TIMER1 STATUS REGISTER */
+#define BCHP_TIMER_TIMER2_STAT                   0x004067e0 /* TIMER2 STATUS REGISTER */
+#define BCHP_TIMER_TIMER3_STAT                   0x004067e4 /* TIMER3 STATUS REGISTER */
+#define BCHP_TIMER_WDTIMEOUT                     0x004067e8 /* WATCHDOG TIMEOUT REGISTER */
+#define BCHP_TIMER_WDCMD                         0x004067ec /* WATCHDOG COMMAND REGISTER */
+#define BCHP_TIMER_WDCHIPRST_CNT                 0x004067f0 /* WATCHDOG CHIP RESET COUNT REGISTER */
+#define BCHP_TIMER_WDCRS                         0x004067f4 /* WATCHDOG CHIP RESET STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE1                     0x004067f8 /* TIMER PCI INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_WDCTRL                        0x004067fc /* WATCHDOG CONTROL REGISTER */
+
+/***************************************************************************
+ *TIMER_IS - TIMER INTERRUPT STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IS :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IS_reserved0_MASK                         0xffffffe0
+#define BCHP_TIMER_TIMER_IS_reserved0_SHIFT                        5
+
+/* TIMER :: TIMER_IS :: WDINT [04:04] */
+#define BCHP_TIMER_TIMER_IS_WDINT_MASK                             0x00000010
+#define BCHP_TIMER_TIMER_IS_WDINT_SHIFT                            4
+#define BCHP_TIMER_TIMER_IS_WDINT_DEFAULT                          0
+
+/* TIMER :: TIMER_IS :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IS_TMR3TO_MASK                            0x00000008
+#define BCHP_TIMER_TIMER_IS_TMR3TO_SHIFT                           3
+#define BCHP_TIMER_TIMER_IS_TMR3TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IS_TMR2TO_MASK                            0x00000004
+#define BCHP_TIMER_TIMER_IS_TMR2TO_SHIFT                           2
+#define BCHP_TIMER_TIMER_IS_TMR2TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IS_TMR1TO_MASK                            0x00000002
+#define BCHP_TIMER_TIMER_IS_TMR1TO_SHIFT                           1
+#define BCHP_TIMER_TIMER_IS_TMR1TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IS_TMR0TO_MASK                            0x00000001
+#define BCHP_TIMER_TIMER_IS_TMR0TO_SHIFT                           0
+#define BCHP_TIMER_TIMER_IS_TMR0TO_DEFAULT                         0
+
+/***************************************************************************
+ *TIMER_IE0 - TIMER CPU INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE0 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE0_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE0_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE0 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_DEFAULT                     0
+
+/* TIMER :: TIMER_IE0 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_DEFAULT                        0
+
+/***************************************************************************
+ *TIMER0_CTRL - TIMER0 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER0_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER0_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER0_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER0_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER0_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER0_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER0_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER0_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER1_CTRL - TIMER1 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER1_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER1_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER1_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER1_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER1_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER1_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER1_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER1_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER2_CTRL - TIMER2 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER2_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER2_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER2_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER2_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER2_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER2_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER2_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER2_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER3_CTRL - TIMER3 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER3_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER3_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER3_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER3_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER3_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER3_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER3_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER3_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER0_STAT - TIMER0 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER0_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER0_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER0_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER1_STAT - TIMER1 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER1_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER1_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER1_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER2_STAT - TIMER2 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER2_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER2_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER2_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER3_STAT - TIMER3 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER3_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER3_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER3_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *WDTIMEOUT - WATCHDOG TIMEOUT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDTIMEOUT :: WDTIMEOUT_VAL [31:00] */
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_MASK                    0xffffffff
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *WDCMD - WATCHDOG COMMAND REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCMD :: WDCMD [31:00] */
+#define BCHP_TIMER_WDCMD_WDCMD_MASK                                0xffffffff
+#define BCHP_TIMER_WDCMD_WDCMD_SHIFT                               0
+#define BCHP_TIMER_WDCMD_WDCMD_DEFAULT                             0
+
+/***************************************************************************
+ *WDCHIPRST_CNT - WATCHDOG CHIP RESET COUNT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCHIPRST_CNT :: reserved0 [31:26] */
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_MASK                    0xfc000000
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_SHIFT                   26
+
+/* TIMER :: WDCHIPRST_CNT :: WDCHIPRST_CNT [25:00] */
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_MASK                0x03ffffff
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_SHIFT               0
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_DEFAULT             50331647
+
+/***************************************************************************
+ *WDCRS - WATCHDOG CHIP RESET STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCRS :: reserved0 [31:01] */
+#define BCHP_TIMER_WDCRS_reserved0_MASK                            0xfffffffe
+#define BCHP_TIMER_WDCRS_reserved0_SHIFT                           1
+
+/* TIMER :: WDCRS :: WDCR [00:00] */
+#define BCHP_TIMER_WDCRS_WDCR_MASK                                 0x00000001
+#define BCHP_TIMER_WDCRS_WDCR_SHIFT                                0
+#define BCHP_TIMER_WDCRS_WDCR_DEFAULT                              0
+
+/***************************************************************************
+ *TIMER_IE1 - TIMER PCI INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE1 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE1_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE1_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE1 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_DEFAULT                     0
+
+/* TIMER :: TIMER_IE1 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_DEFAULT                        0
+
+/***************************************************************************
+ *WDCTRL - WATCHDOG CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCTRL :: reserved0 [31:03] */
+#define BCHP_TIMER_WDCTRL_reserved0_MASK                           0xfffffff8
+#define BCHP_TIMER_WDCTRL_reserved0_SHIFT                          3
+
+/* TIMER :: WDCTRL :: WD_COUNT_MODE [02:02] */
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_MASK                       0x00000004
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_SHIFT                      2
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_DEFAULT                    0
+
+/* TIMER :: WDCTRL :: WD_EVENT_MODE [01:00] */
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_MASK                       0x00000003
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_SHIFT                      0
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_DEFAULT                    0
+
+#endif /* #ifndef BCHP_TIMER_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_uarta.h b/include/linux/brcmstb/7231b0/bchp_uarta.h
new file mode 100644
index 0000000..f0e1936
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_uarta.h
@@ -0,0 +1,394 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:25:46 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_uarta.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 7:23p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTA_H__
+#define BCHP_UARTA_H__
+
+/***************************************************************************
+ *UARTA - UART A
+ ***************************************************************************/
+#define BCHP_UARTA_RBR                           0x00406900 /* Receive Buffer Register */
+#define BCHP_UARTA_THR                           0x00406900 /* Transmit Holding Register */
+#define BCHP_UARTA_DLH                           0x00406904 /* Divisor Latch High */
+#define BCHP_UARTA_DLL                           0x00406900 /* Divisor Latch Low */
+#define BCHP_UARTA_IER                           0x00406904 /* Interrupt Enable Register */
+#define BCHP_UARTA_IIR                           0x00406908 /* Interrupt Identity Register */
+#define BCHP_UARTA_FCR                           0x00406908 /* FIFO Control Register */
+#define BCHP_UARTA_LCR                           0x0040690c /* Line Control Register */
+#define BCHP_UARTA_MCR                           0x00406910 /* Modem Control Register */
+#define BCHP_UARTA_LSR                           0x00406914 /* Line Status Register */
+#define BCHP_UARTA_MSR                           0x00406918 /* Modem Status Register */
+#define BCHP_UARTA_SCR                           0x0040691c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTA :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTA_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_RBR_reserved0_SHIFT                             8
+
+/* UARTA :: RBR :: RBR [07:00] */
+#define BCHP_UARTA_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTA_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTA_RBR_RBR_DEFAULT                                 0
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTA :: THR :: reserved0 [31:08] */
+#define BCHP_UARTA_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_THR_reserved0_SHIFT                             8
+
+/* UARTA :: THR :: THR [07:00] */
+#define BCHP_UARTA_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTA_THR_THR_SHIFT                                   0
+#define BCHP_UARTA_THR_THR_DEFAULT                                 0
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTA :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTA_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLH_reserved0_SHIFT                             8
+
+/* UARTA :: DLH :: DLH [07:00] */
+#define BCHP_UARTA_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTA_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTA_DLH_DLH_DEFAULT                                 0
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTA :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTA_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLL_reserved0_SHIFT                             8
+
+/* UARTA :: DLL :: DLL [07:00] */
+#define BCHP_UARTA_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTA_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTA_DLL_DLL_DEFAULT                                 0
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTA :: IER :: reserved0 [31:08] */
+#define BCHP_UARTA_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IER_reserved0_SHIFT                             8
+
+/* UARTA :: IER :: PTIME [07:07] */
+#define BCHP_UARTA_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTA_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTA_IER_PTIME_DEFAULT                               0
+
+/* UARTA :: IER :: reserved1 [06:04] */
+#define BCHP_UARTA_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTA_IER_reserved1_SHIFT                             4
+
+/* UARTA :: IER :: EDSSI [03:03] */
+#define BCHP_UARTA_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTA_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTA_IER_EDSSI_DEFAULT                               0
+
+/* UARTA :: IER :: ELSI [02:02] */
+#define BCHP_UARTA_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTA_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTA_IER_ELSI_DEFAULT                                0
+
+/* UARTA :: IER :: ETBEI [01:01] */
+#define BCHP_UARTA_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTA_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTA_IER_ETBEI_DEFAULT                               0
+
+/* UARTA :: IER :: ERBFI [00:00] */
+#define BCHP_UARTA_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTA_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTA_IER_ERBFI_DEFAULT                               0
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTA :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTA_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IIR_reserved0_SHIFT                             8
+
+/* UARTA :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTA_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTA_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTA_IIR_FIFOSE_DEFAULT                              0
+
+/* UARTA :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTA_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTA_IIR_reserved1_SHIFT                             4
+
+/* UARTA :: IIR :: IID [03:00] */
+#define BCHP_UARTA_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTA_IIR_IID_SHIFT                                   0
+#define BCHP_UARTA_IIR_IID_DEFAULT                                 1
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTA :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTA_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_FCR_reserved0_SHIFT                             8
+
+/* UARTA :: FCR :: RT [07:06] */
+#define BCHP_UARTA_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTA_FCR_RT_SHIFT                                    6
+#define BCHP_UARTA_FCR_RT_DEFAULT                                  0
+
+/* UARTA :: FCR :: TET [05:04] */
+#define BCHP_UARTA_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTA_FCR_TET_SHIFT                                   4
+#define BCHP_UARTA_FCR_TET_DEFAULT                                 0
+
+/* UARTA :: FCR :: DMAM [03:03] */
+#define BCHP_UARTA_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTA_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTA_FCR_DMAM_DEFAULT                                0
+
+/* UARTA :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTA_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTA_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTA_FCR_XFIFOR_DEFAULT                              0
+
+/* UARTA :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTA_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTA_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTA_FCR_RFIFOR_DEFAULT                              0
+
+/* UARTA :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTA_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTA_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTA_FCR_FIFOE_DEFAULT                               0
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTA :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTA_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LCR_reserved0_SHIFT                             8
+
+/* UARTA :: LCR :: DLAB [07:07] */
+#define BCHP_UARTA_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTA_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTA_LCR_DLAB_DEFAULT                                0
+
+/* UARTA :: LCR :: BC [06:06] */
+#define BCHP_UARTA_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTA_LCR_BC_SHIFT                                    6
+#define BCHP_UARTA_LCR_BC_DEFAULT                                  0
+
+/* UARTA :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTA_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTA_LCR_reserved1_SHIFT                             5
+
+/* UARTA :: LCR :: EPS [04:04] */
+#define BCHP_UARTA_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTA_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTA_LCR_EPS_DEFAULT                                 0
+
+/* UARTA :: LCR :: PEN [03:03] */
+#define BCHP_UARTA_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTA_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTA_LCR_PEN_DEFAULT                                 0
+
+/* UARTA :: LCR :: STOP [02:02] */
+#define BCHP_UARTA_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTA_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTA_LCR_STOP_DEFAULT                                0
+
+/* UARTA :: LCR :: DLS [01:00] */
+#define BCHP_UARTA_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTA_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTA_LCR_DLS_DEFAULT                                 0
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTA :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTA_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTA_MCR_reserved0_SHIFT                             7
+
+/* UARTA :: MCR :: SIRE [06:06] */
+#define BCHP_UARTA_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTA_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTA_MCR_SIRE_DEFAULT                                0
+
+/* UARTA :: MCR :: AFCE [05:05] */
+#define BCHP_UARTA_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTA_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTA_MCR_AFCE_DEFAULT                                0
+
+/* UARTA :: MCR :: LB [04:04] */
+#define BCHP_UARTA_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTA_MCR_LB_SHIFT                                    4
+#define BCHP_UARTA_MCR_LB_DEFAULT                                  0
+
+/* UARTA :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTA_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTA_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTA_MCR_OUT2_DEFAULT                                0
+
+/* UARTA :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTA_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTA_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTA_MCR_OUT1_DEFAULT                                0
+
+/* UARTA :: MCR :: RTS [01:01] */
+#define BCHP_UARTA_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTA_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTA_MCR_RTS_DEFAULT                                 0
+
+/* UARTA :: MCR :: DTR [00:00] */
+#define BCHP_UARTA_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTA_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTA_MCR_DTR_DEFAULT                                 0
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTA :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTA_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LSR_reserved0_SHIFT                             8
+
+/* UARTA :: LSR :: RFE [07:07] */
+#define BCHP_UARTA_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTA_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTA_LSR_RFE_DEFAULT                                 0
+
+/* UARTA :: LSR :: TEMT [06:06] */
+#define BCHP_UARTA_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTA_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTA_LSR_TEMT_DEFAULT                                1
+
+/* UARTA :: LSR :: THRE [05:05] */
+#define BCHP_UARTA_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTA_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTA_LSR_THRE_DEFAULT                                1
+
+/* UARTA :: LSR :: BI [04:04] */
+#define BCHP_UARTA_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTA_LSR_BI_SHIFT                                    4
+#define BCHP_UARTA_LSR_BI_DEFAULT                                  0
+
+/* UARTA :: LSR :: FE [03:03] */
+#define BCHP_UARTA_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTA_LSR_FE_SHIFT                                    3
+#define BCHP_UARTA_LSR_FE_DEFAULT                                  0
+
+/* UARTA :: LSR :: PE [02:02] */
+#define BCHP_UARTA_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTA_LSR_PE_SHIFT                                    2
+#define BCHP_UARTA_LSR_PE_DEFAULT                                  0
+
+/* UARTA :: LSR :: OE [01:01] */
+#define BCHP_UARTA_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTA_LSR_OE_SHIFT                                    1
+#define BCHP_UARTA_LSR_OE_DEFAULT                                  0
+
+/* UARTA :: LSR :: DR [00:00] */
+#define BCHP_UARTA_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTA_LSR_DR_SHIFT                                    0
+#define BCHP_UARTA_LSR_DR_DEFAULT                                  0
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTA :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTA_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_MSR_reserved0_SHIFT                             8
+
+/* UARTA :: MSR :: DCD [07:07] */
+#define BCHP_UARTA_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTA_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTA_MSR_DCD_DEFAULT                                 0
+
+/* UARTA :: MSR :: RI [06:06] */
+#define BCHP_UARTA_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTA_MSR_RI_SHIFT                                    6
+#define BCHP_UARTA_MSR_RI_DEFAULT                                  0
+
+/* UARTA :: MSR :: DSR [05:05] */
+#define BCHP_UARTA_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTA_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTA_MSR_DSR_DEFAULT                                 0
+
+/* UARTA :: MSR :: CTS [04:04] */
+#define BCHP_UARTA_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTA_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTA_MSR_CTS_DEFAULT                                 0
+
+/* UARTA :: MSR :: DDCD [03:03] */
+#define BCHP_UARTA_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTA_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTA_MSR_DDCD_DEFAULT                                0
+
+/* UARTA :: MSR :: TERI [02:02] */
+#define BCHP_UARTA_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTA_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTA_MSR_TERI_DEFAULT                                0
+
+/* UARTA :: MSR :: DDSR [01:01] */
+#define BCHP_UARTA_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTA_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTA_MSR_DDSR_DEFAULT                                0
+
+/* UARTA :: MSR :: DCTS [00:00] */
+#define BCHP_UARTA_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTA_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTA_MSR_DCTS_DEFAULT                                0
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTA :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTA_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_SCR_reserved0_SHIFT                             8
+
+/* UARTA :: SCR :: SCR [07:00] */
+#define BCHP_UARTA_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTA_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTA_SCR_SCR_DEFAULT                                 0
+
+#endif /* #ifndef BCHP_UARTA_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_uartb.h b/include/linux/brcmstb/7231b0/bchp_uartb.h
new file mode 100644
index 0000000..537b74f
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_uartb.h
@@ -0,0 +1,60 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon May 17 03:38:55 2010
+ *                 MD5 Checksum         48de0819069cffb1a27afe66f66cd920
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTB_H__
+#define BCHP_UARTB_H__
+
+/***************************************************************************
+ *UARTB - UART B
+ ***************************************************************************/
+#define BCHP_UARTB_RBR                           0x00406940 /* Receive Buffer Register */
+#define BCHP_UARTB_THR                           0x00406940 /* Transmit Holding Register */
+#define BCHP_UARTB_DLH                           0x00406944 /* Divisor Latch High */
+#define BCHP_UARTB_DLL                           0x00406940 /* Divisor Latch Low */
+#define BCHP_UARTB_IER                           0x00406944 /* Interrupt Enable Register */
+#define BCHP_UARTB_IIR                           0x00406948 /* Interrupt Identity Register */
+#define BCHP_UARTB_FCR                           0x00406948 /* FIFO Control Register */
+#define BCHP_UARTB_LCR                           0x0040694c /* Line Control Register */
+#define BCHP_UARTB_MCR                           0x00406950 /* Modem Control Register */
+#define BCHP_UARTB_LSR                           0x00406954 /* Line Status Register */
+#define BCHP_UARTB_MSR                           0x00406958 /* Modem Status Register */
+#define BCHP_UARTB_SCR                           0x0040695c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTB_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_uartc.h b/include/linux/brcmstb/7231b0/bchp_uartc.h
new file mode 100644
index 0000000..63240a7
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_uartc.h
@@ -0,0 +1,60 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon May 17 03:30:38 2010
+ *                 MD5 Checksum         48de0819069cffb1a27afe66f66cd920
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTC_H__
+#define BCHP_UARTC_H__
+
+/***************************************************************************
+ *UARTC - UART C
+ ***************************************************************************/
+#define BCHP_UARTC_RBR                           0x00406980 /* Receive Buffer Register */
+#define BCHP_UARTC_THR                           0x00406980 /* Transmit Holding Register */
+#define BCHP_UARTC_DLH                           0x00406984 /* Divisor Latch High */
+#define BCHP_UARTC_DLL                           0x00406980 /* Divisor Latch Low */
+#define BCHP_UARTC_IER                           0x00406984 /* Interrupt Enable Register */
+#define BCHP_UARTC_IIR                           0x00406988 /* Interrupt Identity Register */
+#define BCHP_UARTC_FCR                           0x00406988 /* FIFO Control Register */
+#define BCHP_UARTC_LCR                           0x0040698c /* Line Control Register */
+#define BCHP_UARTC_MCR                           0x00406990 /* Modem Control Register */
+#define BCHP_UARTC_LSR                           0x00406994 /* Line Status Register */
+#define BCHP_UARTC_MSR                           0x00406998 /* Modem Status Register */
+#define BCHP_UARTC_SCR                           0x0040699c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_usb1_ctrl.h b/include/linux/brcmstb/7231b0/bchp_usb1_ctrl.h
new file mode 100644
index 0000000..1f20317
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_usb1_ctrl.h
@@ -0,0 +1,66 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Aug 24 17:42:44 2010
+ *                 MD5 Checksum         39761c6e4b9d69cf41e7412c1f6df022
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/a0/bchp_usb1_ctrl.h $
+ * 
+ * Hydra_Software_Devel/1   8/25/10 2:00p albertl
+ * HW7231-39: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB1_CTRL_H__
+#define BCHP_USB1_CTRL_H__
+
+/***************************************************************************
+ *USB1_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB1_CTRL_SETUP                     0x00490200 /* Setup Register */
+#define BCHP_USB1_CTRL_PLL_CTL                   0x00490204 /* PLL Control Register */
+#define BCHP_USB1_CTRL_FLADJ_VALUE               0x00490208 /* Frame Adjust Value */
+#define BCHP_USB1_CTRL_EBRIDGE                   0x0049020c /* Control Register for EHCI Bridge */
+#define BCHP_USB1_CTRL_OBRIDGE                   0x00490210 /* Control Register for OHCI Bridge */
+#define BCHP_USB1_CTRL_MDIO                      0x00490214 /* MDIO Interface Programming Register */
+#define BCHP_USB1_CTRL_MDIO2                     0x00490218 /* MDIO Interface Read Register */
+#define BCHP_USB1_CTRL_TEST_PORT_CTL             0x0049021c /* Test Port Control Register */
+#define BCHP_USB1_CTRL_USB_SIMCTL                0x00490220 /* Simulation Register */
+#define BCHP_USB1_CTRL_USB_TESTCTL               0x00490224 /* Throutput Test Control */
+#define BCHP_USB1_CTRL_USB_TESTMON               0x00490228 /* Throughput Test Monitor */
+#define BCHP_USB1_CTRL_UTMI_CTL_1                0x0049022c /* UTMI Control Register */
+#define BCHP_USB1_CTRL_UTMI_CTL_2                0x00490230 /* UTMI Control 2 Register */
+#define BCHP_USB1_CTRL_SPARE1                    0x00490234 /* Spare1 Register for future use */
+#define BCHP_USB1_CTRL_SPARE2                    0x00490238 /* Spare2 Register for future use */
+
+#endif /* #ifndef BCHP_USB1_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_usb_ctrl.h b/include/linux/brcmstb/7231b0/bchp_usb_ctrl.h
new file mode 100644
index 0000000..6db4b579
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_usb_ctrl.h
@@ -0,0 +1,675 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:18:38 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_usb_ctrl.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 7:27p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB_CTRL_H__
+#define BCHP_USB_CTRL_H__
+
+/***************************************************************************
+ *USB_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB_CTRL_SETUP                      0x00480200 /* Setup Register */
+#define BCHP_USB_CTRL_PLL_CTL                    0x00480204 /* PLL Control Register */
+#define BCHP_USB_CTRL_FLADJ_VALUE                0x00480208 /* Frame Adjust Value */
+#define BCHP_USB_CTRL_EBRIDGE                    0x0048020c /* Control Register for EHCI Bridge */
+#define BCHP_USB_CTRL_OBRIDGE                    0x00480210 /* Control Register for OHCI Bridge */
+#define BCHP_USB_CTRL_MDIO                       0x00480214 /* MDIO Interface Programming Register */
+#define BCHP_USB_CTRL_MDIO2                      0x00480218 /* MDIO Interface Read Register */
+#define BCHP_USB_CTRL_TEST_PORT_CTL              0x0048021c /* Test Port Control Register */
+#define BCHP_USB_CTRL_USB_SIMCTL                 0x00480220 /* Simulation Register */
+#define BCHP_USB_CTRL_USB_TESTCTL                0x00480224 /* Throutput Test Control */
+#define BCHP_USB_CTRL_USB_TESTMON                0x00480228 /* Throughput Test Monitor */
+#define BCHP_USB_CTRL_UTMI_CTL_1                 0x0048022c /* UTMI Control Register */
+#define BCHP_USB_CTRL_UTMI_CTL_2                 0x00480230 /* UTMI Control 2 Register */
+#define BCHP_USB_CTRL_SPARE1                     0x00480234 /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE2                     0x00480238 /* Spare2 Register for future use */
+
+/***************************************************************************
+ *SETUP - Setup Register
+ ***************************************************************************/
+/* USB_CTRL :: SETUP :: OC_DISABLE [31:28] */
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK                        0xf0000000
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT                       28
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT                     0
+
+/* USB_CTRL :: SETUP :: SRAM_CS_DIS [27:25] */
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_MASK                       0x0e000000
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_SHIFT                      25
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: SETUP_SPARE [24:15] */
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK                       0x01ff8000
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT                      15
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: scb_client_swap [14:14] */
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_MASK                   0x00004000
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_SHIFT                  14
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_DEFAULT                0
+
+/* USB_CTRL :: SETUP :: scb1_en [13:13] */
+#define BCHP_USB_CTRL_SETUP_scb1_en_MASK                           0x00002000
+#define BCHP_USB_CTRL_SETUP_scb1_en_SHIFT                          13
+#define BCHP_USB_CTRL_SETUP_scb1_en_DEFAULT                        0
+
+/* USB_CTRL :: SETUP :: async_expire_dis [12:12] */
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK                  0x00001000
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT                 12
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT               0
+
+/* USB_CTRL :: SETUP :: discon_intr_en [11:11] */
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_MASK                    0x00000800
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_SHIFT                   11
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_DEFAULT                 0
+
+/* USB_CTRL :: SETUP :: con_intr_en [10:10] */
+#define BCHP_USB_CTRL_SETUP_con_intr_en_MASK                       0x00000400
+#define BCHP_USB_CTRL_SETUP_con_intr_en_SHIFT                      10
+#define BCHP_USB_CTRL_SETUP_con_intr_en_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: soft_shutdown [09:09] */
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_MASK                     0x00000200
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_SHIFT                    9
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_DEFAULT                  0
+
+/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK                    0x00000100
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT                   8
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT                 0
+
+/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK                       0x00000080
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT                      7
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: soft_reset [06:06] */
+#define BCHP_USB_CTRL_SETUP_soft_reset_MASK                        0x00000040
+#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT                       6
+#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT                     0
+
+/* USB_CTRL :: SETUP :: IPP [05:05] */
+#define BCHP_USB_CTRL_SETUP_IPP_MASK                               0x00000020
+#define BCHP_USB_CTRL_SETUP_IPP_SHIFT                              5
+#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT                            0
+
+/* USB_CTRL :: SETUP :: IOC [04:04] */
+#define BCHP_USB_CTRL_SETUP_IOC_MASK                               0x00000010
+#define BCHP_USB_CTRL_SETUP_IOC_SHIFT                              4
+#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT                            0
+
+/* USB_CTRL :: SETUP :: WABO [03:03] */
+#define BCHP_USB_CTRL_SETUP_WABO_MASK                              0x00000008
+#define BCHP_USB_CTRL_SETUP_WABO_SHIFT                             3
+#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: FNBO [02:02] */
+#define BCHP_USB_CTRL_SETUP_FNBO_MASK                              0x00000004
+#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT                             2
+#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: FNHW [01:01] */
+#define BCHP_USB_CTRL_SETUP_FNHW_MASK                              0x00000002
+#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT                             1
+#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: BABO [00:00] */
+#define BCHP_USB_CTRL_SETUP_BABO_MASK                              0x00000001
+#define BCHP_USB_CTRL_SETUP_BABO_SHIFT                             0
+#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT                           0
+
+/***************************************************************************
+ *PLL_CTL - PLL Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK                  0x80000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT                 31
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT               0
+
+/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK                      0x40000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT                     30
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                   1
+
+/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK                      0x20000000
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                     29
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                   0
+
+/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                     0x10000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                    28
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                  1
+
+/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                  0x08000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                 27
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT               0
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK                          0x07000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT                         24
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT                       3
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                   0x00800000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                  23
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK                          0x00700000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT                         20
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT                       3
+
+/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK                          0x000f0000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT                         16
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT                       10
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE2 [15:15] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_MASK                   0x00008000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_SHIFT                  15
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_pdiv [14:12] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK                        0x00007000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT                       12
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                     1
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                   0x00000c00
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                  10
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK                        0x000003ff
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT                       0
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                     40
+
+/***************************************************************************
+ *FLADJ_VALUE - Frame Adjust Value
+ ***************************************************************************/
+/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                   0xffffffff
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                  0
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT                786464
+
+/***************************************************************************
+ *EBRIDGE - Control Register for EHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT               0
+
+/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT                  0
+
+/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT           0
+
+/* USB_CTRL :: EBRIDGE :: ebr_size_sel [28:28] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_DEFAULT                 0
+
+/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT                2
+
+/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                 4
+
+/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT                     0
+
+/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                   0
+
+/***************************************************************************
+ *OBRIDGE - Control Register for OHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT               0
+
+/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT                  0
+
+/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT           0
+
+/* USB_CTRL :: OBRIDGE :: obr_size_sel [28:28] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_DEFAULT                 0
+
+/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT                2
+
+/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                 4
+
+/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT                     0
+
+/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                   0
+
+/***************************************************************************
+ *MDIO - MDIO Interface Programming Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO :: MDIO_CLK_SEL [31:31] */
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_MASK                       0x80000000
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_SHIFT                      31
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_DEFAULT                    0
+
+/* USB_CTRL :: MDIO :: MDIO_XVER_SELECT [30:29] */
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_MASK                   0x60000000
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_SHIFT                  29
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_DEFAULT                0
+
+/* USB_CTRL :: MDIO :: MDIO_TERM_SELECT [28:28] */
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_MASK                   0x10000000
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_SHIFT                  28
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_DEFAULT                0
+
+/* USB_CTRL :: MDIO :: MDIO_FS_XVER_OWN [27:27] */
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_MASK                   0x08000000
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_SHIFT                  27
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_DEFAULT                0
+
+/* USB_CTRL :: MDIO :: MDIO_TESTMODE [26:26] */
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_MASK                      0x04000000
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_SHIFT                     26
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_DEFAULT                   0
+
+/* USB_CTRL :: MDIO :: WR_START [25:25] */
+#define BCHP_USB_CTRL_MDIO_WR_START_MASK                           0x02000000
+#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT                          25
+#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT                        0
+
+/* USB_CTRL :: MDIO :: RD_START [24:24] */
+#define BCHP_USB_CTRL_MDIO_RD_START_MASK                           0x01000000
+#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT                          24
+#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT                        0
+
+/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK                          0x00ff0000
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT                         16
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT                       0
+
+/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK                          0x0000ffff
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT                         0
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT                       0
+
+/***************************************************************************
+ *MDIO2 - MDIO Interface Read Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO2 :: SYNOPSIS_CORE_ID [31:16] */
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_MASK                  0xffff0000
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_SHIFT                 16
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_DEFAULT               9994
+
+/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK                      0x0000ffff
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                     0
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                   0
+
+/***************************************************************************
+ *TEST_PORT_CTL - Test Port Control Register
+ ***************************************************************************/
+/* USB_CTRL :: TEST_PORT_CTL :: TP_EN [31:31] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_MASK                     0x80000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_SHIFT                    31
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_DEFAULT                  0
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [30:26] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK               0x7c000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT              26
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT            0
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb0_wr_data_sel [25:25] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_MASK          0x02000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_SHIFT         25
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_DEFAULT       0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [24:24] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK                0x01000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT               24
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT             0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt2_oe [23:23] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_MASK                0x00800000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_SHIFT               23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_DEFAULT             0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron1_tstsel [22:22] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_MASK             0x00400000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_SHIFT            22
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron2_tstsel [21:21] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_MASK             0x00200000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_SHIFT            21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: test_clksel [20:19] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_MASK               0x00180000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_SHIFT              19
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_DEFAULT            0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_tstsel [18:16] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_MASK             0x00070000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_SHIFT            16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: UTMI_TEST_SEL [15:08] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_MASK             0x0000ff00
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_SHIFT            8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                 0x000000ff
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT                0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT              0
+
+/***************************************************************************
+ *USB_SIMCTL - Simulation Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK                  0x80000000
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                 31
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT               0
+
+/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK                0x40000000
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT               30
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT             0
+
+/* USB_CTRL :: USB_SIMCTL :: otg_scale_down_en [29:28] */
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_MASK            0x30000000
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_SHIFT           28
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_DEFAULT         0
+
+/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK                    0x08000000
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT                   27
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT                 0
+
+/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK        0x04000000
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT       26
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT     0
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:00] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                 0x03ffffff
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT                0
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT              0
+
+/***************************************************************************
+ *USB_TESTCTL - Throutput Test Control
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:23] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK              0xff800000
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT             23
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT           0
+
+/* USB_CTRL :: USB_TESTCTL :: CTRLLER_SEL [22:21] */
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_MASK                 0x00600000
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_SHIFT                21
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_DEFAULT              0
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK                     0x00100000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                    20
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                  0
+
+/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK                   0x00080000
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                  19
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT                0
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK                    0x00070000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                   16
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                 0
+
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK              0x0000fc00
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT             10
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT           0
+
+/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK              0x000003ff
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT             0
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT           0
+
+/***************************************************************************
+ *USB_TESTMON - Throughput Test Monitor
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [31:00] */
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK                0xffffffff
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT               0
+
+/***************************************************************************
+ *UTMI_CTL_1 - UTMI Control Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB_P1 [31:31] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_MASK              0x80000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_SHIFT             31
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK             0x70000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT            28
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT          0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK_P1 [27:27] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_MASK                0x08000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_SHIFT               27
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE3 [26:25] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_MASK              0x06000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_SHIFT             25
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY_P1 [24:24] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_MASK                0x01000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_SHIFT               24
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK                0x00800000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT               23
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK                0x00400000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT               22
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK                0x00200000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT               21
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK                0x00100000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT               20
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                  0x000c0000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                 18
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT               0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT       1
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK           0x00010000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT          16
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT        0
+
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB [15:15] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_MASK                 0x00008000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_SHIFT                15
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_DEFAULT              0
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK                0x00007000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT               12
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK [11:11] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_MASK                   0x00000800
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_SHIFT                  11
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE1 [10:09] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_MASK              0x00000600
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_SHIFT             9
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY [08:08] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_MASK                   0x00000100
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_SHIFT                  8
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                   0x00000080
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                  7
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                   0x00000040
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                  6
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                   0x00000020
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                  5
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                   0x00000010
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                  4
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK                     0x0000000c
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                    2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                  0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT          1
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK              0x00000001
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT             0
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT           0
+
+/***************************************************************************
+ *UTMI_CTL_2 - UTMI Control 2 Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK               0xffffffff
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT              0
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT            0
+
+/***************************************************************************
+ *SPARE1 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE1 :: SPARE1_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_DEFAULT                   0
+
+/***************************************************************************
+ *SPARE2 - Spare2 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE2 :: SPARE2_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_DEFAULT                   0
+
+#endif /* #ifndef BCHP_USB_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_wktmr.h b/include/linux/brcmstb/7231b0/bchp_wktmr.h
new file mode 100644
index 0000000..a05d081
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_wktmr.h
@@ -0,0 +1,108 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:13:12 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_wktmr.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 3:03p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_WKTMR_H__
+#define BCHP_WKTMR_H__
+
+/***************************************************************************
+ *WKTMR - Wakeup timer
+ ***************************************************************************/
+#define BCHP_WKTMR_EVENT                         0x00408e80 /* Wakeup Timer Register */
+#define BCHP_WKTMR_COUNTER                       0x00408e84 /* Wakeup Counter */
+#define BCHP_WKTMR_ALARM                         0x00408e88 /* Wakeup Timer Alarm */
+#define BCHP_WKTMR_PRESCALER                     0x00408e8c /* Wakeup Timer Prescaler */
+#define BCHP_WKTMR_PRESCALER_VAL                 0x00408e90 /* Wakeup Timer Prescaler Value */
+
+/***************************************************************************
+ *EVENT - Wakeup Timer Register
+ ***************************************************************************/
+/* WKTMR :: EVENT :: reserved0 [31:01] */
+#define BCHP_WKTMR_EVENT_reserved0_MASK                            0xfffffffe
+#define BCHP_WKTMR_EVENT_reserved0_SHIFT                           1
+
+/* WKTMR :: EVENT :: wktmr_alarm_event [00:00] */
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_MASK                    0x00000001
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_SHIFT                   0
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_DEFAULT                 0
+
+/***************************************************************************
+ *COUNTER - Wakeup Counter
+ ***************************************************************************/
+/* WKTMR :: COUNTER :: wktmr_counter [31:00] */
+#define BCHP_WKTMR_COUNTER_wktmr_counter_MASK                      0xffffffff
+#define BCHP_WKTMR_COUNTER_wktmr_counter_SHIFT                     0
+#define BCHP_WKTMR_COUNTER_wktmr_counter_DEFAULT                   0
+
+/***************************************************************************
+ *ALARM - Wakeup Timer Alarm
+ ***************************************************************************/
+/* WKTMR :: ALARM :: wktmr_alarm [31:00] */
+#define BCHP_WKTMR_ALARM_wktmr_alarm_MASK                          0xffffffff
+#define BCHP_WKTMR_ALARM_wktmr_alarm_SHIFT                         0
+#define BCHP_WKTMR_ALARM_wktmr_alarm_DEFAULT                       0
+
+/***************************************************************************
+ *PRESCALER - Wakeup Timer Prescaler
+ ***************************************************************************/
+/* WKTMR :: PRESCALER :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_reserved0_MASK                        0xfe000000
+#define BCHP_WKTMR_PRESCALER_reserved0_SHIFT                       25
+
+/* WKTMR :: PRESCALER :: wktmr_prescaler [24:00] */
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_MASK                  0x01ffffff
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_SHIFT                 0
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_DEFAULT               27000000
+
+/***************************************************************************
+ *PRESCALER_VAL - Wakeup Timer Prescaler Value
+ ***************************************************************************/
+/* WKTMR :: PRESCALER_VAL :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_MASK                    0xfe000000
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_SHIFT                   25
+
+/* WKTMR :: PRESCALER_VAL :: wktmr_prescaler_val [24:00] */
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_MASK          0x01ffffff
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_SHIFT         0
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_DEFAULT       0
+
+#endif /* #ifndef BCHP_WKTMR_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/brcmirq.h b/include/linux/brcmstb/7231b0/brcmirq.h
new file mode 100644
index 0000000..b2d71bb
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/brcmirq.h
@@ -0,0 +1,48 @@
+/*
+ * 7231b0 IRQ header file autogenerated by update_bchp.pl
+ * DO NOT EDIT THIS FILE BY HAND.
+ *
+ * Copyright (C) 2011 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BRCMIRQ_H_
+#define _BRCMIRQ_H_
+
+#define BRCM_IRQ_EHCI0_0	69
+#define BRCM_IRQ_EHCI0_1	70
+#define BRCM_IRQ_EHCI1_0	74
+#define BRCM_IRQ_EHCI1_1	75
+#define BRCM_IRQ_GENET_0_A	25
+#define BRCM_IRQ_GENET_0_B	26
+#define BRCM_IRQ_GENET_1_A	27
+#define BRCM_IRQ_GENET_1_B	28
+#define BRCM_IRQ_HIF		31
+#define BRCM_IRQ_HIF_SPI	32
+#define BRCM_IRQ_MOCA		36
+#define BRCM_IRQ_OHCI0_0	71
+#define BRCM_IRQ_OHCI0_1	72
+#define BRCM_IRQ_OHCI1_0	76
+#define BRCM_IRQ_OHCI1_1	77
+#define BRCM_IRQ_SATA		41
+#define BRCM_IRQ_SDIO0		86
+#define BRCM_IRQ_STANDBY	54
+#define BRCM_IRQ_UARTA		65
+#define BRCM_IRQ_UARTB		66
+#define BRCM_IRQ_UARTC		67
+#define BRCM_IRQLIST_EHCI	{ 69, 70, 74, 75 }
+#define BRCM_IRQLIST_OHCI	{ 71, 72, 76, 77 }
+
+#endif /* _BRCMIRQ_H_ */
diff --git a/include/linux/brcmstb/7344b0/bchp_aon_ctrl.h b/include/linux/brcmstb/7344b0/bchp_aon_ctrl.h
new file mode 100644
index 0000000..148a701
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_aon_ctrl.h
@@ -0,0 +1,1606 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 31 14:13:45 2011
+ *                 MD5 Checksum         b0a0062767e487fe78d25d07b5b21b78
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_aon_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   5/31/11 3:29p albertl
+ * SW7344-40: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_CTRL_H__
+#define BCHP_AON_CTRL_H__
+
+/***************************************************************************
+ *AON_CTRL - AON Control Registers
+ ***************************************************************************/
+#define BCHP_AON_CTRL_RESET_CTRL                 0x00408000 /* Reset Control register for AON */
+#define BCHP_AON_CTRL_PM_CTRL                    0x00408004 /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_STATUS                  0x00408008 /* Status register for Power Controller */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS        0x0040800c /* Power Management IRQ input status */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT         0x00408010 /* Power Management Wait counter in place of Wait for MIPS IRQ */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER        0x00408014 /* Deep Standby Assertion Timer */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER         0x00408018 /* Deep Standby Wakeup Timer */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE    0x0040801c /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_LED_CTRL                0x00408020 /* LED set control register */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES     0x00408024 /* LED set control register */
+#define BCHP_AON_CTRL_HLCD_CTRL                  0x00408030 /* HW LED Clock Driver Control */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER    0x00408034 /* Second Fraction Counter Initial value */
+#define BCHP_AON_CTRL_TIME_COUNTER               0x00408038 /* Hour/Minute Counter Initial value */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0           0x0040803c /* Digit Code for digit 0, 1, 2, 3 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1           0x00408040 /* Digit Code for digit 4, 5, 6, 7 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2           0x00408044 /* Digit Code for digit 8, 9 */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET      0x00408048 /* Hour MSD/LSD and minute MSD/LSD address offset */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL            0x0040804c /* LED status control */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0             0x00408050 /* General control register 0 */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0           0x00408054 /* General status register 0 */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0     0x00408058 /* General control register without scan 0 */
+#define BCHP_AON_CTRL_SPARE_CTRL_0               0x00408060 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_SPARE_CTRL_1               0x00408064 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH          0x00408068 /* Scratch register */
+#define BCHP_AON_CTRL_RESET_HISTORY              0x0040806c /* Reset History Register For AON */
+#define BCHP_AON_CTRL_NMI_CTRL                   0x00408070 /* Control register for NMI */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL           0x00408074 /* Ana xtal low cur 40g m7fc gisb control */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL         0x00408078 /* Test_mode control register */
+#define BCHP_AON_CTRL_SUB_TEST_MODE              0x0040807c /* Register source for sub_test_mode */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE          0x00408080 /* Final latched testmode value */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE      0x00408084 /* Final latched sub-testmode value */
+#define BCHP_AON_CTRL_PM_INITIATE                0x00408088 /* Power down initiate */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS             0x0040808c /* Power up restore */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL   0x00408090 /* Ana xtal low cur 40g m7fc external CML control */
+
+/***************************************************************************
+ *RESET_CTRL - Reset Control register for AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_CTRL :: reserved0 [31:04] */
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_MASK                    0xfffffff0
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_SHIFT                   4
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [03:03] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000008
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 3
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_DEFAULT 0
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable [02:02] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_MASK     0x00000004
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT    2
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_DEFAULT  0
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_polarity [01:01] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK   0x00000002
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT  1
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_DEFAULT 0
+
+/* AON_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_MASK          0x00000001
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_SHIFT         0
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_DEFAULT       0
+
+/***************************************************************************
+ *PM_CTRL - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_CTRL :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_MASK                       0xffffff00
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_SHIFT                      8
+
+/* AON_CTRL :: PM_CTRL :: min_s3_width_timer_bypass [07:07] */
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_MASK       0x00000080
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_SHIFT      7
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_DEFAULT    0
+
+/* AON_CTRL :: PM_CTRL :: pm_fast_power_down [06:06] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_MASK              0x00000040
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_SHIFT             6
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_DEFAULT           0
+
+/* AON_CTRL :: PM_CTRL :: pm_warm_boot [05:05] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_MASK                    0x00000020
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_SHIFT                   5
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_DEFAULT                 0
+
+/* AON_CTRL :: PM_CTRL :: pm_deep_standby [04:04] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_MASK                 0x00000010
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_SHIFT                4
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_DEFAULT              0
+
+/* AON_CTRL :: PM_CTRL :: pm_clk_divider_reset_en [03:03] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK         0x00000008
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_SHIFT        3
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_DEFAULT      1
+
+/* AON_CTRL :: PM_CTRL :: pm_use_mips_ready_ctrl [02:02] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_MASK          0x00000004
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_SHIFT         2
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_DEFAULT       0
+
+/* AON_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK             0x00000002
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT            1
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_DEFAULT          0
+
+/* AON_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_MASK                  0x00000001
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT                 0
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_DEFAULT               0
+
+/***************************************************************************
+ *PM_STATUS - Status register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_STATUS :: pm_wait_count_upper_bits [31:26] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_MASK      0xfc000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_SHIFT     26
+
+/* AON_CTRL :: PM_STATUS :: pm_wait_counter_active [25:25] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_MASK        0x02000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_SHIFT       25
+
+/* AON_CTRL :: PM_STATUS :: pm_s3_wakeup_reset_ [24:24] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__MASK           0x01000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__SHIFT          24
+
+/* AON_CTRL :: PM_STATUS :: pm_boundary_scan_request [23:23] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_MASK      0x00800000
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_SHIFT     23
+
+/* AON_CTRL :: PM_STATUS :: pm_fast_pd_precharge_valid [22:22] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_MASK    0x00400000
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_SHIFT   22
+
+/* AON_CTRL :: PM_STATUS :: pm_led_out [21:21] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_MASK                    0x00200000
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_SHIFT                   21
+
+/* AON_CTRL :: PM_STATUS :: pm_standby_b [20:20] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_MASK                  0x00100000
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_SHIFT                 20
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs_ng [19:19] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_MASK           0x00080000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_SHIFT          19
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs [18:18] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_MASK              0x00040000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_SHIFT             18
+
+/* AON_CTRL :: PM_STATUS :: pm_rst_clock_div [17:17] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_MASK              0x00020000
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_SHIFT             17
+
+/* AON_CTRL :: PM_STATUS :: pm_pwrdn_pll_req [16:16] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_MASK              0x00010000
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_SHIFT             16
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_xtal_clocks [15:15] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_MASK            0x00008000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_SHIFT           15
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_all_clocks [14:14] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_MASK             0x00004000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_SHIFT            14
+
+/* AON_CTRL :: PM_STATUS :: pm_dphy_standby [13:13] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_MASK               0x00002000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_SHIFT              13
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_cpu_clock [12:12] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_MASK              0x00001000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_SHIFT             12
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_avd_rptd_clock [11:11] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_MASK         0x00000800
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_SHIFT        11
+
+/* AON_CTRL :: PM_STATUS :: pm_power_ctrl_disable [10:10] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_MASK         0x00000400
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_SHIFT        10
+
+/* AON_CTRL :: PM_STATUS :: pm_pll_lock [09:09] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_MASK                   0x00000200
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_SHIFT                  9
+
+/* AON_CTRL :: PM_STATUS :: pm_dram_ready_for_pwrdn [08:08] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_MASK       0x00000100
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_SHIFT      8
+
+/* AON_CTRL :: PM_STATUS :: pm_bsp_ready_for_pwrdn [07:07] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK        0x00000080
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_SHIFT       7
+
+/* AON_CTRL :: PM_STATUS :: pm_mips_ready_for_pwrdn [06:06] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_MASK       0x00000040
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_SHIFT      6
+
+/* AON_CTRL :: PM_STATUS :: pm_sec_avd_rptd_clk_disable [05:05] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_MASK   0x00000020
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_SHIFT  5
+
+/* AON_CTRL :: PM_STATUS :: pm_state [04:00] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_MASK                      0x0000001f
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_SHIFT                     0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_ACTIVE                 0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_PWRDN_RDY              1
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_AVD_RPTD       2
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_CPU            3
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_STANDBY  4
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY                5
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY_WITH_PLLS_ON   6
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_RESET_216_108_CLKS     7
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_ACTIVE   8
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_FAST_PWRDN             9
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S1  10
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_COLD_ENTRY_S2 11
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_WARM_ENTRY_S2 12
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S3  13
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY           14
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S1   15
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S2   16
+
+/***************************************************************************
+ *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
+ ***************************************************************************/
+/* AON_CTRL :: PM_IRQ_INPUT_STATUS :: pm_irq_input_status [31:00] */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_MASK 0xffffffff
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_SHIFT 0
+
+/***************************************************************************
+ *PM_MIPS_WAIT_COUNT - Power Management Wait counter in place of Wait for MIPS IRQ
+ ***************************************************************************/
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_MASK            0xffff0000
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_SHIFT           16
+
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: counter_start_value [15:00] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_MASK  0x0000ffff
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_DEFAULT 16
+
+/***************************************************************************
+ *PM_S3_STANDBY_TIMER - Deep Standby Assertion Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_MASK           0xf8000000
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_SHIFT          27
+
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_MASK 0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_DEFAULT 540000
+
+/***************************************************************************
+ *PM_S3_WAKEUP_TIMER - Deep Standby Wakeup Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_MASK            0xf8000000
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_SHIFT           27
+
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_MASK  0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_DEFAULT 540000
+
+/***************************************************************************
+ *PM_FAST_PWRDN_PRECHARGE - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: reserved0 [31:24] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_MASK       0xff000000
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_SHIFT      24
+
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: pm_fast_power_down_precharge [23:00] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_MASK 0x00ffffff
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_SHIFT 0
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_DEFAULT 0
+
+/***************************************************************************
+ *PM_LED_CTRL - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_CTRL :: reserved0 [31:03] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_MASK                   0xfffffff8
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_SHIFT                  3
+
+/* AON_CTRL :: PM_LED_CTRL :: led_status [02:02] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_MASK                  0x00000004
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_SHIFT                 2
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_on [01:01] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_MASK                 0x00000002
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_SHIFT                1
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_off [00:00] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_MASK                0x00000001
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_SHIFT               0
+
+/***************************************************************************
+ *PM_LED_AUTO_ON_ENABLES - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_AUTO_ON_ENABLES :: led_status [31:00] */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_MASK       0xffffffff
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_SHIFT      0
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_DEFAULT    0
+
+/***************************************************************************
+ *HLCD_CTRL - HW LED Clock Driver Control
+ ***************************************************************************/
+/* AON_CTRL :: HLCD_CTRL :: reserved0 [31:02] */
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_MASK                     0xfffffffc
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_SHIFT                    2
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable_status [01:01] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_MASK            0x00000002
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_SHIFT           1
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable [00:00] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_MASK                   0x00000001
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_SHIFT                  0
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_DEFAULT                0
+
+/***************************************************************************
+ *SECOND_FRACTION_COUNTER - Second Fraction Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: reserved0 [31:25] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_MASK       0xfe000000
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_SHIFT      25
+
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: second_fraction_counter_init [24:00] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_MASK 0x01ffffff
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_SHIFT 0
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_DEFAULT 0
+
+/***************************************************************************
+ *TIME_COUNTER - Hour/Minute Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: TIME_COUNTER :: reserved0 [31:20] */
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_MASK                  0xfff00000
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_SHIFT                 20
+
+/* AON_CTRL :: TIME_COUNTER :: hour_display_mode [19:19] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_MASK          0x00080000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_SHIFT         19
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: mode_12h_24h_init [18:18] */
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_MASK          0x00040000
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_SHIFT         18
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: am_pm_counter_init [17:17] */
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_MASK         0x00020000
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_SHIFT        17
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_DEFAULT      0
+
+/* AON_CTRL :: TIME_COUNTER :: hour_counter_init [16:12] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_MASK          0x0001f000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_SHIFT         12
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: minute_counter_init [11:06] */
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_MASK        0x00000fc0
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_SHIFT       6
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_DEFAULT     0
+
+/* AON_CTRL :: TIME_COUNTER :: second_counter_init [05:00] */
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_MASK        0x0000003f
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_SHIFT       0
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_DEFAULT     0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_0 - Digit Code for digit 0, 1, 2, 3
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_3 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_2 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_1 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_0 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_1 - Digit Code for digit 4, 5, 6, 7
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_7 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_6 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_5 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_4 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_2 - Digit Code for digit 8, 9
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_MASK              0xffff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_SHIFT             16
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_9 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_8 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_ADDR_OFFSET - Hour MSD/LSD and minute MSD/LSD address offset
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_msd_addr_offset [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_MASK 0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_SHIFT 24
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_DEFAULT 32
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_lsd_addr_offset [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_MASK 0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_SHIFT 16
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_DEFAULT 36
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_msd_addr_offset [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_MASK 0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_SHIFT 8
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_DEFAULT 24
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_lsd_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_MASK 0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_SHIFT 0
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_DEFAULT 28
+
+/***************************************************************************
+ *LED_STATUS_CTRL - LED status control
+ ***************************************************************************/
+/* AON_CTRL :: LED_STATUS_CTRL :: reserved0 [31:28] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_MASK               0xf0000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_SHIFT              28
+
+/* AON_CTRL :: LED_STATUS_CTRL :: hlcd_state [27:25] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_MASK              0x0e000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_SHIFT             25
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_IDLE         0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_COUNT        1
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_LSD 2
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_MSD 3
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_LSD 4
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_MSD 5
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_STATUS 6
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_update_enable [24:24] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_MASK    0x01000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_SHIFT   24
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_DEFAULT 0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_mask [23:12] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_MASK             0x00fff000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_SHIFT            12
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_DEFAULT          0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_bit_offset [11:08] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_MASK       0x00000f00
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_SHIFT      8
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_DEFAULT    0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_MASK      0x000000ff
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_SHIFT     0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK         0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT        31
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK         0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT        30
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK         0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT        29
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK         0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT        28
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK         0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT        27
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK         0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT        26
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK         0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT        25
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK         0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT        24
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK         0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT        23
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK         0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT        22
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK         0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT        21
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK         0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT        20
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK         0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT        19
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK         0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT        18
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK         0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT        17
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK         0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT        16
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK         0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT        15
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK         0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT        14
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK         0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT        13
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK         0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT        12
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK         0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT        11
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK         0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT        10
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK          0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT         9
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK          0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT         8
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK          0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT         7
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK          0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT         6
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK          0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT         5
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK          0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT         4
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK          0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT         3
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK          0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT         2
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK          0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT         1
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK          0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT         0
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT       0
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_MASK              0xffffff00
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_SHIFT             8
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_MASK      0x00000080
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT     7
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_MASK      0x00000040
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT     6
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_MASK      0x00000020
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT     5
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_MASK      0x00000010
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT     4
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_MASK      0x00000008
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT     3
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_MASK      0x00000004
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT     2
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_MASK      0x00000002
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT     1
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: ejtag_ce_wakeup_event [00:00] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_MASK  0x00000001
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_MASK 0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_SHIFT 31
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_MASK 0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_SHIFT 30
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_MASK 0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_SHIFT 29
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_MASK 0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_SHIFT 28
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_MASK 0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_SHIFT 27
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_MASK 0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_SHIFT 26
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_MASK 0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_SHIFT 25
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_MASK 0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_SHIFT 24
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_MASK 0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_SHIFT 23
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_MASK 0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_SHIFT 22
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_MASK 0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_SHIFT 21
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_MASK 0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_SHIFT 20
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_MASK 0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_SHIFT 19
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_MASK 0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_SHIFT 18
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_MASK 0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_SHIFT 17
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_MASK 0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_SHIFT 16
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_MASK 0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_SHIFT 15
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_MASK 0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_SHIFT 14
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_MASK 0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_SHIFT 13
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_MASK 0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_SHIFT 12
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_MASK 0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_SHIFT 11
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_MASK 0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_SHIFT 10
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_MASK 0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_SHIFT 5
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_MASK 0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_SHIFT 4
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_MASK 0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_SHIFT 3
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_MASK 0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_SHIFT 2
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_MASK 0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_SHIFT 0
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_DEFAULT 0
+
+/***************************************************************************
+ *SPARE_CTRL_0 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_DEFAULT           0
+
+/***************************************************************************
+ *SPARE_CTRL_1 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_DEFAULT           0
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* AON_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK     0xffffffff
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT    0
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT  0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset History Register For AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_HISTORY :: reserved0 [31:19] */
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_MASK                 0xfff80000
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_SHIFT                19
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [18:18] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK    0x00040000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT   18
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [17:17] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK    0x00020000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT   17
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [16:16] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK     0x00010000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT    16
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [15:15] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK     0x00008000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT    15
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [14:14] */
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK           0x00004000
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT          14
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_DEFAULT        0
+
+/* AON_CTRL :: RESET_HISTORY :: overtemp_reset [13:13] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_MASK            0x00002000
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_SHIFT           13
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_DEFAULT         0
+
+/* AON_CTRL :: RESET_HISTORY :: overvoltage_reset [12:12] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_MASK         0x00001000
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT        12
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_DEFAULT      0
+
+/* AON_CTRL :: RESET_HISTORY :: undervoltage_reset [11:11] */
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_MASK        0x00000800
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT       11
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_DEFAULT     0
+
+/* AON_CTRL :: RESET_HISTORY :: security_dl_sw_reset [10:10] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK      0x00000400
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT     10
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_DEFAULT   0
+
+/* AON_CTRL :: RESET_HISTORY :: security_master_reset [09:09] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_MASK     0x00000200
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_SHIFT    9
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: software_master_reset [08:08] */
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_MASK     0x00000100
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_SHIFT    8
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [07:07] */
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK       0x00000080
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT      7
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_DEFAULT    0
+
+/* AON_CTRL :: RESET_HISTORY :: watchdog_timer_reset [06:06] */
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK      0x00000040
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT     6
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_DEFAULT   0
+
+/* AON_CTRL :: RESET_HISTORY :: smartcard_insert_reset [05:05] */
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK    0x00000020
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT   5
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: s3_wakeup_reset [04:04] */
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_MASK           0x00000010
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_SHIFT          4
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_DEFAULT        0
+
+/* AON_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [03:03] */
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK    0x00000008
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT   3
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: tap_in_system_reset [02:02] */
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_MASK       0x00000004
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_SHIFT      2
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_DEFAULT    0
+
+/* AON_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_MASK     0x00000002
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT    1
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_MASK            0x00000001
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_SHIFT           0
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_DEFAULT         1
+
+/***************************************************************************
+ *NMI_CTRL - Control register for NMI
+ ***************************************************************************/
+/* AON_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_MASK                0x80000000
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_SHIFT               31
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_DEFAULT             0
+
+/* AON_CTRL :: NMI_CTRL :: reserved0 [30:03] */
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_MASK                      0x7ffffff8
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_SHIFT                     3
+
+/* AON_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_MASK                0x00000004
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT               2
+
+/* AON_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_MASK            0x00000002
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT           1
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_DEFAULT         0
+
+/* AON_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_MASK                0x00000001
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT               0
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_DEFAULT             1
+
+/***************************************************************************
+ *ANA_XTAL_CONTROL - Ana xtal low cur 40g m7fc gisb control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_CONTROL :: reserved0 [31:09] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_MASK              0xfffffe00
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_SHIFT             9
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_test_select_gisb_control [08:08] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_MASK 0x00000100
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_SHIFT 8
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_select_current_gisb_control [07:07] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_MASK 0x00000080
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_SHIFT 7
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_cml_sel_pd [06:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_MASK         0x00000078
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_SHIFT        3
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_DEFAULT      12
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_d2cbias_gisb_control [02:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_MASK 0x00000007
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_SHIFT 0
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_DEFAULT 4
+
+/***************************************************************************
+ *SUB_TEST_MODE_CTRL - Test_mode control register
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: reserved0 [31:01] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_MASK            0xfffffffe
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_SHIFT           1
+
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: use_sub_test_mode_reg_src [00:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_MASK 0x00000001
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_SHIFT 0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_DEFAULT 0
+
+/***************************************************************************
+ *SUB_TEST_MODE - Register source for sub_test_mode
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_MASK                 0xffffff00
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_SHIFT                8
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [07:07] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK     0x00000080
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT    7
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_DEFAULT  0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [06:06] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK     0x00000040
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT    6
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_DEFAULT  0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [05:05] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK   0x00000020
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT  5
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_mips_in_reset [04:04] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_MASK 0x00000010
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_SHIFT 4
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [03:03] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000008
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 3
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [02:02] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000004
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 2
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK   0x00000003
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT  0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_DEFAULT 0
+
+/***************************************************************************
+ *LATCHED_TEST_MODE - Final latched testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK     0xffffffff
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT    0
+
+/***************************************************************************
+ *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0
+
+/***************************************************************************
+ *PM_INITIATE - Power down initiate
+ ***************************************************************************/
+/* AON_CTRL :: PM_INITIATE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_MASK                   0xffffff00
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_SHIFT                  8
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_7 [07:07] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_MASK               0x00000080
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_SHIFT              7
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_6 [06:06] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_MASK               0x00000040
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_SHIFT              6
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_5 [05:05] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_MASK               0x00000020
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_SHIFT              5
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_4 [04:04] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_MASK               0x00000010
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_SHIFT              4
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_3 [03:03] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_MASK               0x00000008
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_SHIFT              3
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_2 [02:02] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_MASK               0x00000004
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_SHIFT              2
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_1 [01:01] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_MASK               0x00000002
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_SHIFT              1
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_0 [00:00] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_MASK               0x00000001
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_SHIFT              0
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_DEFAULT            0
+
+/***************************************************************************
+ *HOST_MISC_CMDS - Power up restore
+ ***************************************************************************/
+/* AON_CTRL :: HOST_MISC_CMDS :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_MASK                0xffffff00
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_SHIFT               8
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_7 [07:07] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_MASK         0x00000080
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_SHIFT        7
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_6 [06:06] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_MASK         0x00000040
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_SHIFT        6
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_5 [05:05] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_MASK         0x00000020
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_SHIFT        5
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_4 [04:04] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_MASK         0x00000010
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_SHIFT        4
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_3 [03:03] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_MASK         0x00000008
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_SHIFT        3
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_2 [02:02] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_MASK         0x00000004
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_SHIFT        2
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: dram_scram_key_reuse_req [01:01] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_MASK 0x00000002
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_SHIFT 1
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_DEFAULT 0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: pm_restore [00:00] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_MASK               0x00000001
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_SHIFT              0
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_DEFAULT            0
+
+/***************************************************************************
+ *ANA_XTAL_EXT_CML_CONTROL - Ana xtal low cur 40g m7fc external CML control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: reserved0 [31:06] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_reserved0_MASK      0xffffffc0
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_reserved0_SHIFT     6
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_PMSM_S3_pd_buffer [05:05] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_MASK 0x00000020
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_SHIFT 5
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_override_strap [04:04] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_MASK 0x00000010
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_SHIFT 4
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_pd_buffer [03:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_MASK  0x00000008
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_SHIFT 3
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_div2_sel [02:02] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_MASK   0x00000004
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_SHIFT  2
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_DEFAULT 1
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_current [01:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_MASK    0x00000003
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_SHIFT   0
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_DEFAULT 1
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_BASE                  0x00408200
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_START                 0
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_END                   127
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_ELEMENT_SIZE          32
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_RAMi :: SYSTEM_DATA_RAM [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_MASK        0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_SHIFT       0
+
+
+#endif /* #ifndef BCHP_AON_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_aon_pin_ctrl.h b/include/linux/brcmstb/7344b0/bchp_aon_pin_ctrl.h
new file mode 100644
index 0000000..08b9385
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_aon_pin_ctrl.h
@@ -0,0 +1,545 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 31 13:55:25 2011
+ *                 MD5 Checksum         b0a0062767e487fe78d25d07b5b21b78
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_aon_pin_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   5/31/11 3:29p albertl
+ * SW7344-40: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PIN_CTRL_H__
+#define BCHP_AON_PIN_CTRL_H__
+
+/***************************************************************************
+ *AON_PIN_CTRL - AON Pinmux Control Registers
+ ***************************************************************************/
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0         0x00408500 /* Pinmux control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1         0x00408504 /* Pinmux control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2         0x00408508 /* Pinmux control register 2 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3         0x0040850c /* Pinmux control register 3 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0     0x00408510 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1     0x00408514 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2     0x00408518 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0     0x0040851c /* Bypass clock unselect register 0 */
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_14 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_14_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_14_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_14_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_14_AON_GPIO_14   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_14_SDS0_DSEC_VCTL 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_14_SDS0_IF_AGC   2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_14_AIO_EXTMCLK0  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_14_PM_AON_GPIO_14 4
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_13 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_13_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_13_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_13_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_13_AON_GPIO_13   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_13_SDS0_DSEC_SELVTOP 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_13_I2S_BIDIR_CLK_IN 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_13_I2S_BIDIR_CLK_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_13_SDS0_RF_AGC   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_13_TP_OUT_26     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_13_PM_AON_GPIO_13 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_12 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_12_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_12_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_12_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_12_AON_GPIO_12   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_12_SDS0_DSEC_TXEN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_12_I2S_BIDIR_SYNC_IN 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_12_I2S_BIDIR_SYNC_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_12_TP_OUT_25     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_12_PM_AON_GPIO_12 5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_11 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_11_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_11_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_11_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_11_AON_GPIO_11   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_11_SDS0_DSEC_TXOUT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_11_I2S_BIDIR_DATA_IN 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_11_I2S_BIDIR_DATA_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_11_TP_OUT_24     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_11_PM_AON_GPIO_11 5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_03 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_DEFAULT       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_GPIO_03   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_KD_3      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_EXT_IRQB_5    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_UART_RTSCB    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_PM_LED_OUT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_TP_OUT_03     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PM_AON_GPIO_03 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_02 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_AON_GPIO_02   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_LED_KD_2      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_EXT_IRQB_4    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_UART_CTSCB    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_SC0_RST_ALT   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_TP_OUT_02     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_PM_AON_GPIO_02 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_01 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AON_GPIO_01   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_LED_KD_1      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_EXT_IRQB_3    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_UART_TXDC     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SC0_CLK_OUT_ALT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_TP_OUT_01     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_PM_AON_GPIO_01 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_00 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AON_GPIO_00   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_LED_KD_0      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_EXT_IRQB_2    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_UART_RXDC     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SC0_IO_ALT    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_ALT_TP_IN_00  5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_TP_OUT_00     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_PM_AON_GPIO_00 7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_09 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_AON_GPIO_09   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_IR_IN0        1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_UHF_LNA_PWRDN 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_ALT_TP_OUT_08 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_PM_AON_GPIO_09 4
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_08 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_AON_GPIO_08   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_EXT_IRQB_10   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_IR_INT        2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_RMX_PAUSE1    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SC0_VPP_ALT   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_TP_OUT_31     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_PM_AON_GPIO_08 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_07 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_AON_GPIO_07   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_EXT_IRQB_9    1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_LED_LS_3      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_RMX_VALID1    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SC0_IO_AUX2_ALT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_TP_OUT_30     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_PM_AON_GPIO_07 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_06 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_AON_GPIO_06   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_EXT_IRQB_8    1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_LED_LS_2      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_RMX_SYNC1     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SC0_IO_AUX1_ALT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_TP_OUT_29     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PM_AON_GPIO_06 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_05 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_05_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_05_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_05_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_05_AON_GPIO_05   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_05_EXT_IRQB_7    1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_05_LED_LS_1      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_05_RMX_DATA1     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_05_SC0_VCC_ALT   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_05_TP_OUT_28     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_05_PM_AON_GPIO_05 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_04 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_04_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_04_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_04_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_04_AON_GPIO_04   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_04_EXT_IRQB_6    1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_04_LED_LS_0      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_04_RMX_CLK1      3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_04_SC0_PRES_ALT  4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_04_TP_OUT_27     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_04_PM_AON_GPIO_04 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_16 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_16_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_16_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_16_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_16_AON_GPIO_16   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_16_AON_PM_LED_OUT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_16_PM_AON_GPIO_16 2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_15 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_AON_GPIO_15   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_EXT_IRQB_16   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_P1_INTR       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_AIO_EXTMCLK1  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_PM_AON_GPIO_15 4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_spi_m_miso [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_miso_MASK       0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_miso_SHIFT      28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_miso_DEFAULT    0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_miso_AON_SPI_M_MISO 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_miso_ALT_TP_OUT_04 1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_spi_m_mosi [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_mosi_MASK       0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_mosi_SHIFT      24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_mosi_DEFAULT    0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_mosi_AON_SPI_M_MOSI 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_mosi_ALT_TP_OUT_03 1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_spi_m_sck [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_sck_MASK        0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_sck_SHIFT       20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_sck_DEFAULT     0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_sck_AON_SPI_M_SCK 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_sck_ALT_TP_OUT_02 1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_01 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_MASK         0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_SHIFT        16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_AON_SGPIO_01 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_BSC_M2_SDA   1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_00 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_MASK         0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SHIFT        12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_AON_SGPIO_00 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_BSC_M2_SCL   1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_03 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_MASK         0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_SHIFT        8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_AON_SGPIO_03 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_AON_BSC_M0_SDA 1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_02 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_MASK         0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_SHIFT        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_AON_SGPIO_02 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_AON_BSC_M0_SCL 1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_10 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_10_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_10_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_10_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_10_AON_GPIO_10   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_10_IR_IN1        1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_10_UHF_LNA_PWRDN 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_10_PM_AON_GPIO_10 3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: reserved0 [31:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_MASK            0xffff0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_SHIFT           16
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_gpio_18 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_18_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_18_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_18_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_18_AON_GPIO_18   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_18_AON_IRQB1     1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_gpio_17 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_17_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_17_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_17_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_17_AON_GPIO_17   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_17_AON_IRQB0     1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_spi_m_ss1b [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_spi_m_ss1b_MASK       0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_spi_m_ss1b_SHIFT      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_spi_m_ss1b_DEFAULT    0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_spi_m_ss1b_AON_SPI_M_SS1B 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_spi_m_ss1b_ALT_TP_OUT_06 1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_spi_m_ss0b [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_spi_m_ss0b_MASK       0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_spi_m_ss0b_SHIFT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_spi_m_ss0b_DEFAULT    0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_spi_m_ss0b_AON_SPI_M_SS0B 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_spi_m_ss0b_ALT_TP_OUT_05 1
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_08_pad_ctrl [29:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_MASK 0x30000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_SHIFT 28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_07_pad_ctrl [27:26] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_MASK 0x0c000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_SHIFT 26
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_06_pad_ctrl [25:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_MASK 0x03000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_SHIFT 24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_05_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_04_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_16_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_16_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_16_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_16_pad_ctrl_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_16_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_15_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_15_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_15_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_15_pad_ctrl_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_15_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_14_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_14_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_14_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_14_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_14_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_13_pad_ctrl [13:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_13_pad_ctrl_MASK 0x00003000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_13_pad_ctrl_SHIFT 12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_13_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_13_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_12_pad_ctrl [11:10] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_MASK 0x00000c00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_SHIFT 10
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_11_pad_ctrl [09:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_MASK 0x00000300
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_SHIFT 8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_03_pad_ctrl [07:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_MASK 0x000000c0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_SHIFT 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_02_pad_ctrl [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_01_pad_ctrl [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_00_pad_ctrl [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_MASK 0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_SHIFT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0x3ffffff0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       4
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_10_pad_ctrl [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_09_pad_ctrl [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_MASK 0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_SHIFT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [31:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK        0xffffffc0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT       6
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved1 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_MASK        0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_SHIFT       0
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:03] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffff8
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       3
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_nmib [02:02] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_MASK 0x00000004
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_SHIFT 2
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_DEFAULT 0
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_10 [01:01] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_10_MASK 0x00000002
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_10_SHIFT 1
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_10_DEFAULT 0
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_14 [00:00] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_14_MASK 0x00000001
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_14_SHIFT 0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_14_DEFAULT 0
+
+#endif /* #ifndef BCHP_AON_PIN_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_aon_pm_l2.h b/include/linux/brcmstb/7344b0/bchp_aon_pm_l2.h
new file mode 100644
index 0000000..1aa1c4f
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_aon_pm_l2.h
@@ -0,0 +1,1407 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:30:15 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_aon_pm_l2.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 12:42p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PM_L2_H__
+#define BCHP_AON_PM_L2_H__
+
+/***************************************************************************
+ *AON_PM_L2 - AON Power Management L2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_AON_PM_L2_CPU_STATUS                0x00408440 /* CPU interrupt Status Register */
+#define BCHP_AON_PM_L2_CPU_SET                   0x00408444 /* CPU interrupt Set Register */
+#define BCHP_AON_PM_L2_CPU_CLEAR                 0x00408448 /* CPU interrupt Clear Register */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS           0x0040844c /* CPU interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_CPU_MASK_SET              0x00408450 /* CPU interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR            0x00408454 /* CPU interrupt Mask Clear Register */
+#define BCHP_AON_PM_L2_PCI_STATUS                0x00408458 /* PCI interrupt Status Register */
+#define BCHP_AON_PM_L2_PCI_SET                   0x0040845c /* PCI interrupt Set Register */
+#define BCHP_AON_PM_L2_PCI_CLEAR                 0x00408460 /* PCI interrupt Clear Register */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS           0x00408464 /* PCI interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_PCI_MASK_SET              0x00408468 /* PCI interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR            0x0040846c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_STATUS :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_MASK                   0xffe00000
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_SHIFT                  21
+
+/* AON_PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x00100000
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       20
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0
+
+/* AON_PM_L2 :: CPU_STATUS :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_MASK                    0x00080000
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_SHIFT                   19
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00040000
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_SHIFT          18
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0
+
+/* AON_PM_L2 :: CPU_STATUS :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_MASK                        0x00020000
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_SHIFT                       17
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_MASK                        0x00010000
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_SHIFT                       16
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_MASK                        0x00008000
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_SHIFT                       15
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_MASK                     0x00004000
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_SHIFT                    14
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_STATUS :: FTM [13:13] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_MASK                         0x00002000
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_SHIFT                        13
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_MASK                   0x00001000
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_SHIFT                  12
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_MASK                   0x00000800
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_SHIFT                  11
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_MASK                 0x00000400
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_SHIFT                10
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_DEFAULT              0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_MASK                 0x00000200
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_SHIFT                9
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_DEFAULT              0
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_MASK                    0x00000100
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_SHIFT                   8
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_MASK                    0x00000080
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_SHIFT                   7
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_STATUS_UHFR_MASK                        0x00000040
+#define BCHP_AON_PM_L2_CPU_STATUS_UHFR_SHIFT                       6
+#define BCHP_AON_PM_L2_CPU_STATUS_UHFR_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_DEFAULT                 0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_SET :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_MASK                      0xffe00000
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_SHIFT                     21
+
+/* AON_PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_MASK           0x00100000
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_SHIFT          20
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0
+
+/* AON_PM_L2 :: CPU_SET :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_MASK                       0x00080000
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_SHIFT                      19
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_MASK              0x00040000
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_SHIFT             18
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_DEFAULT           0
+
+/* AON_PM_L2 :: CPU_SET :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_CPU_SET_USB1_MASK                           0x00020000
+#define BCHP_AON_PM_L2_CPU_SET_USB1_SHIFT                          17
+#define BCHP_AON_PM_L2_CPU_SET_USB1_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_SET_USB0_MASK                           0x00010000
+#define BCHP_AON_PM_L2_CPU_SET_USB0_SHIFT                          16
+#define BCHP_AON_PM_L2_CPU_SET_USB0_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_MASK                           0x00008000
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_SHIFT                          15
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_MASK                        0x00004000
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_SHIFT                       14
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_SET :: FTM [13:13] */
+#define BCHP_AON_PM_L2_CPU_SET_FTM_MASK                            0x00002000
+#define BCHP_AON_PM_L2_CPU_SET_FTM_SHIFT                           13
+#define BCHP_AON_PM_L2_CPU_SET_FTM_DEFAULT                         0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_MASK                      0x00001000
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_SHIFT                     12
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_MASK                      0x00000800
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_SHIFT                     11
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_MASK                    0x00000400
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_SHIFT                   10
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_MASK                    0x00000200
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_SHIFT                   9
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_MASK                       0x00000100
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_SHIFT                      8
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_MOCA_MASK                       0x00000080
+#define BCHP_AON_PM_L2_CPU_SET_WOL_MOCA_SHIFT                      7
+#define BCHP_AON_PM_L2_CPU_SET_WOL_MOCA_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_SET_UHFR_MASK                           0x00000040
+#define BCHP_AON_PM_L2_CPU_SET_UHFR_SHIFT                          6
+#define BCHP_AON_PM_L2_CPU_SET_UHFR_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_DEFAULT                    0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_CLEAR :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_MASK                    0xffe00000
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_SHIFT                   21
+
+/* AON_PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x00100000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        20
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_MASK                     0x00080000
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_SHIFT                    19
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00040000
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           18
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0
+
+/* AON_PM_L2 :: CPU_CLEAR :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_MASK                         0x00020000
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_SHIFT                        17
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_MASK                         0x00010000
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_SHIFT                        16
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_MASK                         0x00008000
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_SHIFT                        15
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_MASK                      0x00004000
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT                     14
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_CLEAR :: FTM [13:13] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_MASK                          0x00002000
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_SHIFT                         13
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_DEFAULT                       0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_MASK                    0x00001000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_SHIFT                   12
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_MASK                    0x00000800
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_SHIFT                   11
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_MASK                  0x00000400
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_SHIFT                 10
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_MASK                  0x00000200
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_SHIFT                 9
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_MASK                     0x00000100
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_SHIFT                    8
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_MOCA_MASK                     0x00000080
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_MOCA_SHIFT                    7
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_MOCA_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_UHFR_MASK                         0x00000040
+#define BCHP_AON_PM_L2_CPU_CLEAR_UHFR_SHIFT                        6
+#define BCHP_AON_PM_L2_CPU_CLEAR_UHFR_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_DEFAULT                  0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_MASK              0xffe00000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT             21
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x00100000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  20
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_MASK               0x00080000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_SHIFT              19
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00040000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     18
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_MASK                   0x00020000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_SHIFT                  17
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_MASK                   0x00010000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_SHIFT                  16
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_MASK                   0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_SHIFT                  15
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK                0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT               14
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FTM [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_MASK                    0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_SHIFT                   13
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_MASK              0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_SHIFT             12
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_MASK              0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_SHIFT             11
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_MASK            0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_SHIFT           10
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_DEFAULT         1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_MASK            0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_SHIFT           9
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_DEFAULT         1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_MASK               0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_SHIFT              8
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_MOCA_MASK               0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_MOCA_SHIFT              7
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_MOCA_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_UHFR_MASK                   0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_UHFR_SHIFT                  6
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_UHFR_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_DEFAULT            1
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_SET :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_MASK                 0xffe00000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_SHIFT                21
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x00100000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     20
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_MASK                  0x00080000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_SHIFT                 19
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00040000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        18
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_MASK                      0x00020000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_SHIFT                     17
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_MASK                      0x00010000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_SHIFT                     16
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_MASK                      0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_SHIFT                     15
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_MASK                   0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT                  14
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FTM [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_MASK                       0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_SHIFT                      13
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_DEFAULT                    1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_MASK                 0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_SHIFT                12
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_MASK                 0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_SHIFT                11
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_MASK               0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_SHIFT              10
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_MASK               0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_SHIFT              9
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_MASK                  0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_SHIFT                 8
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_MOCA_MASK                  0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_MOCA_SHIFT                 7
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_MOCA_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_UHFR_MASK                      0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_SET_UHFR_SHIFT                     6
+#define BCHP_AON_PM_L2_CPU_MASK_SET_UHFR_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_DEFAULT               1
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_MASK               0xffe00000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT              21
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x00100000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   20
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_MASK                0x00080000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_SHIFT               19
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00040000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      18
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_MASK                    0x00020000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_SHIFT                   17
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_MASK                    0x00010000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_SHIFT                   16
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_MASK                    0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_SHIFT                   15
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK                 0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT                14
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FTM [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_MASK                     0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_SHIFT                    13
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_DEFAULT                  1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_MASK               0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_SHIFT              12
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_MASK               0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_SHIFT              11
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_MASK             0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_SHIFT            10
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_MASK             0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_SHIFT            9
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_MASK                0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_SHIFT               8
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_MASK                0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_SHIFT               7
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_UHFR_MASK                    0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_UHFR_SHIFT                   6
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_UHFR_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_DEFAULT             1
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_STATUS :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_MASK                   0xffe00000
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_SHIFT                  21
+
+/* AON_PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x00100000
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       20
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0
+
+/* AON_PM_L2 :: PCI_STATUS :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_MASK                    0x00080000
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_SHIFT                   19
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00040000
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_SHIFT          18
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0
+
+/* AON_PM_L2 :: PCI_STATUS :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_MASK                        0x00020000
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_SHIFT                       17
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_MASK                        0x00010000
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_SHIFT                       16
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_MASK                        0x00008000
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_SHIFT                       15
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_MASK                     0x00004000
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_SHIFT                    14
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_STATUS :: FTM [13:13] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_MASK                         0x00002000
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_SHIFT                        13
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_MASK                   0x00001000
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_SHIFT                  12
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_MASK                   0x00000800
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_SHIFT                  11
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_MASK                 0x00000400
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_SHIFT                10
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_DEFAULT              0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_MASK                 0x00000200
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_SHIFT                9
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_DEFAULT              0
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_MASK                    0x00000100
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_SHIFT                   8
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_MOCA_MASK                    0x00000080
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_MOCA_SHIFT                   7
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_MOCA_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_STATUS_UHFR_MASK                        0x00000040
+#define BCHP_AON_PM_L2_PCI_STATUS_UHFR_SHIFT                       6
+#define BCHP_AON_PM_L2_PCI_STATUS_UHFR_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_DEFAULT                 0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_SET :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_MASK                      0xffe00000
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_SHIFT                     21
+
+/* AON_PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_MASK           0x00100000
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_SHIFT          20
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0
+
+/* AON_PM_L2 :: PCI_SET :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_MASK                       0x00080000
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_SHIFT                      19
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_MASK              0x00040000
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_SHIFT             18
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_DEFAULT           0
+
+/* AON_PM_L2 :: PCI_SET :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_PCI_SET_USB1_MASK                           0x00020000
+#define BCHP_AON_PM_L2_PCI_SET_USB1_SHIFT                          17
+#define BCHP_AON_PM_L2_PCI_SET_USB1_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_SET_USB0_MASK                           0x00010000
+#define BCHP_AON_PM_L2_PCI_SET_USB0_SHIFT                          16
+#define BCHP_AON_PM_L2_PCI_SET_USB0_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_MASK                           0x00008000
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_SHIFT                          15
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_MASK                        0x00004000
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_SHIFT                       14
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_SET :: FTM [13:13] */
+#define BCHP_AON_PM_L2_PCI_SET_FTM_MASK                            0x00002000
+#define BCHP_AON_PM_L2_PCI_SET_FTM_SHIFT                           13
+#define BCHP_AON_PM_L2_PCI_SET_FTM_DEFAULT                         0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_MASK                      0x00001000
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_SHIFT                     12
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_MASK                      0x00000800
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_SHIFT                     11
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_MASK                    0x00000400
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_SHIFT                   10
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_MASK                    0x00000200
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_SHIFT                   9
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_MASK                       0x00000100
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_SHIFT                      8
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_MOCA_MASK                       0x00000080
+#define BCHP_AON_PM_L2_PCI_SET_WOL_MOCA_SHIFT                      7
+#define BCHP_AON_PM_L2_PCI_SET_WOL_MOCA_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_SET_UHFR_MASK                           0x00000040
+#define BCHP_AON_PM_L2_PCI_SET_UHFR_SHIFT                          6
+#define BCHP_AON_PM_L2_PCI_SET_UHFR_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_DEFAULT                    0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_CLEAR :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_MASK                    0xffe00000
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_SHIFT                   21
+
+/* AON_PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x00100000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        20
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_MASK                     0x00080000
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_SHIFT                    19
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00040000
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           18
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0
+
+/* AON_PM_L2 :: PCI_CLEAR :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_MASK                         0x00020000
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_SHIFT                        17
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_MASK                         0x00010000
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_SHIFT                        16
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_MASK                         0x00008000
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_SHIFT                        15
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_MASK                      0x00004000
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT                     14
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_CLEAR :: FTM [13:13] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_MASK                          0x00002000
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_SHIFT                         13
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_DEFAULT                       0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_MASK                    0x00001000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_SHIFT                   12
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_MASK                    0x00000800
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_SHIFT                   11
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_MASK                  0x00000400
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_SHIFT                 10
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_MASK                  0x00000200
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_SHIFT                 9
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_MASK                     0x00000100
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_SHIFT                    8
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_MOCA_MASK                     0x00000080
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_MOCA_SHIFT                    7
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_MOCA_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_UHFR_MASK                         0x00000040
+#define BCHP_AON_PM_L2_PCI_CLEAR_UHFR_SHIFT                        6
+#define BCHP_AON_PM_L2_PCI_CLEAR_UHFR_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_DEFAULT                  0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_MASK              0xffe00000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT             21
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x00100000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  20
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_MASK               0x00080000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_SHIFT              19
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00040000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     18
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_MASK                   0x00020000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_SHIFT                  17
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_MASK                   0x00010000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_SHIFT                  16
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_MASK                   0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_SHIFT                  15
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK                0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT               14
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FTM [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_MASK                    0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_SHIFT                   13
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_MASK              0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_SHIFT             12
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_MASK              0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_SHIFT             11
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_MASK            0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_SHIFT           10
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_DEFAULT         1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_MASK            0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_SHIFT           9
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_DEFAULT         1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_MASK               0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_SHIFT              8
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_MOCA_MASK               0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_MOCA_SHIFT              7
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_MOCA_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_UHFR_MASK                   0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_UHFR_SHIFT                  6
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_UHFR_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_DEFAULT            1
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_SET :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_MASK                 0xffe00000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_SHIFT                21
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x00100000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     20
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_MASK                  0x00080000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_SHIFT                 19
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00040000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        18
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_MASK                      0x00020000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_SHIFT                     17
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_MASK                      0x00010000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_SHIFT                     16
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_MASK                      0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_SHIFT                     15
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_MASK                   0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT                  14
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FTM [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_MASK                       0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_SHIFT                      13
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_DEFAULT                    1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_MASK                 0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_SHIFT                12
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_MASK                 0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_SHIFT                11
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_MASK               0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_SHIFT              10
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_MASK               0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_SHIFT              9
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_MASK                  0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_SHIFT                 8
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_MOCA_MASK                  0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_MOCA_SHIFT                 7
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_MOCA_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_UHFR_MASK                      0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_SET_UHFR_SHIFT                     6
+#define BCHP_AON_PM_L2_PCI_MASK_SET_UHFR_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_DEFAULT               1
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_MASK               0xffe00000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT              21
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x00100000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   20
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_MASK                0x00080000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_SHIFT               19
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00040000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      18
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_MASK                    0x00020000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_SHIFT                   17
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_MASK                    0x00010000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_SHIFT                   16
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_MASK                    0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_SHIFT                   15
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK                 0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT                14
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FTM [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_MASK                     0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_SHIFT                    13
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_DEFAULT                  1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_MASK               0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_SHIFT              12
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_MASK               0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_SHIFT              11
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_MASK             0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_SHIFT            10
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_MASK             0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_SHIFT            9
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_MASK                0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_SHIFT               8
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_MASK                0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_SHIFT               7
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_UHFR_MASK                    0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_UHFR_SHIFT                   6
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_UHFR_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_DEFAULT             1
+
+#endif /* #ifndef BCHP_AON_PM_L2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_bspi.h b/include/linux/brcmstb/7344b0/bchp_bspi.h
new file mode 100644
index 0000000..8ce7918
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_bspi.h
@@ -0,0 +1,446 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:35:16 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_bspi.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 1:01p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_H__
+#define BCHP_BSPI_H__
+
+/***************************************************************************
+ *BSPI - Public BSPI Control Registers
+ ***************************************************************************/
+#define BCHP_BSPI_REVISION_ID                    0x00003000 /* Revision ID */
+#define BCHP_BSPI_SCRATCH                        0x00003004 /* Revision ID */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL               0x00003008 /* Master/Boot SPI Control Register */
+#define BCHP_BSPI_BUSY_STATUS                    0x0000300c /* BSPI Busy Status Register */
+#define BCHP_BSPI_INTR_STATUS                    0x00003010 /* Interrupt Status Register */
+#define BCHP_BSPI_B0_STATUS                      0x00003014 /* Prefetch Buffer 0 Status Register */
+#define BCHP_BSPI_B0_CTRL                        0x00003018 /* Prefetch Buffer 0 Control Register */
+#define BCHP_BSPI_B1_STATUS                      0x0000301c /* Prefetch Buffer 1 Status Register */
+#define BCHP_BSPI_B1_CTRL                        0x00003020 /* Prefetch Buffer 1 Control Register */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL            0x00003024 /* Dual/Single Receive Mode Control Register */
+#define BCHP_BSPI_FLEX_MODE_ENABLE               0x00003028 /* Flexible Control Mode Enable Register */
+#define BCHP_BSPI_BITS_PER_CYCLE                 0x0000302c /* Bits per cycle "b-p-c" Control Register */
+#define BCHP_BSPI_BITS_PER_PHASE                 0x00003030 /* Bits per Phase "b-p-p" Control Register */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE              0x00003034 /* Command and Mode Data Register */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE     0x00003038 /* Bspi FLash upper address byte register */
+#define BCHP_BSPI_BSPI_XOR_VALUE                 0x0000303c /* BSPI FLASH XOR Value Register */
+#define BCHP_BSPI_BSPI_XOR_ENABLE                0x00003040 /* BSPI FLASH XOR Enable Register */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE           0x00003044 /* BSPI Pin  Programmed IO Mode Enable Register */
+#define BCHP_BSPI_BSPI_PIO_IODIR                 0x00003048 /* BSPI Pin  Programmed IO Mode Direction Register */
+#define BCHP_BSPI_BSPI_PIO_DATA                  0x0000304c /* BSPI Pin  Programmed IO Mode Data Register */
+
+/***************************************************************************
+ *REVISION_ID - Revision ID
+ ***************************************************************************/
+/* BSPI :: REVISION_ID :: reserved0 [31:16] */
+#define BCHP_BSPI_REVISION_ID_reserved0_MASK                       0xffff0000
+#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT                      16
+
+/* BSPI :: REVISION_ID :: MAJOR [15:08] */
+#define BCHP_BSPI_REVISION_ID_MAJOR_MASK                           0x0000ff00
+#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT                          8
+#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT                        4
+
+/* BSPI :: REVISION_ID :: MINOR [07:00] */
+#define BCHP_BSPI_REVISION_ID_MINOR_MASK                           0x000000ff
+#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT                          0
+#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT                        0
+
+/***************************************************************************
+ *SCRATCH - Revision ID
+ ***************************************************************************/
+/* BSPI :: SCRATCH :: SCRATCH [31:00] */
+#define BCHP_BSPI_SCRATCH_SCRATCH_MASK                             0xffffffff
+#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT                            0
+#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT                          0
+
+/***************************************************************************
+ *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
+ ***************************************************************************/
+/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT                 1
+
+/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK                0x00000001
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT               0
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT             0
+
+/***************************************************************************
+ *BUSY_STATUS - BSPI Busy Status Register
+ ***************************************************************************/
+/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
+#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK                       0xfffffffe
+#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT                      1
+
+/* BSPI :: BUSY_STATUS :: busy [00:00] */
+#define BCHP_BSPI_BUSY_STATUS_busy_MASK                            0x00000001
+#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT                           0
+#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT                         0
+
+/***************************************************************************
+ *INTR_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
+#define BCHP_BSPI_INTR_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT                      2
+
+/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
+#define BCHP_BSPI_INTR_STATUS_intr_1_MASK                          0x00000002
+#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT                         1
+#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT                       0
+
+/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
+#define BCHP_BSPI_INTR_STATUS_intr_0_MASK                          0x00000001
+#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT                         0
+#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT                       0
+
+/***************************************************************************
+ *B0_STATUS - Prefetch Buffer 0 Status Register
+ ***************************************************************************/
+/* BSPI :: B0_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B0_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT             0
+
+/* BSPI :: B0_STATUS :: b0_full [29:29] */
+#define BCHP_BSPI_B0_STATUS_b0_full_MASK                           0x20000000
+#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT                          29
+#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT                        0
+
+/* BSPI :: B0_STATUS :: b0_empty [28:28] */
+#define BCHP_BSPI_B0_STATUS_b0_empty_MASK                          0x10000000
+#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT                         28
+#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT                       1
+
+/* BSPI :: B0_STATUS :: b0_miss [27:27] */
+#define BCHP_BSPI_B0_STATUS_b0_miss_MASK                           0x08000000
+#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT                          27
+#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT                        0
+
+/* BSPI :: B0_STATUS :: b0_hit [26:26] */
+#define BCHP_BSPI_B0_STATUS_b0_hit_MASK                            0x04000000
+#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT                           26
+#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT                         0
+
+/* BSPI :: B0_STATUS :: b0_address [25:00] */
+#define BCHP_BSPI_B0_STATUS_b0_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT                       0
+#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT                     0
+
+/***************************************************************************
+ *B0_CTRL - Prefetch Buffer 0 Control Register
+ ***************************************************************************/
+/* BSPI :: B0_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B0_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B0_CTRL :: b0_flush [00:00] */
+#define BCHP_BSPI_B0_CTRL_b0_flush_MASK                            0x00000001
+#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT                           0
+#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT                         0
+
+/***************************************************************************
+ *B1_STATUS - Prefetch Buffer 1 Status Register
+ ***************************************************************************/
+/* BSPI :: B1_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B1_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT             0
+
+/* BSPI :: B1_STATUS :: b1_full [29:29] */
+#define BCHP_BSPI_B1_STATUS_b1_full_MASK                           0x20000000
+#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT                          29
+#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT                        0
+
+/* BSPI :: B1_STATUS :: b1_empty [28:28] */
+#define BCHP_BSPI_B1_STATUS_b1_empty_MASK                          0x10000000
+#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT                         28
+#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT                       1
+
+/* BSPI :: B1_STATUS :: b1_miss [27:27] */
+#define BCHP_BSPI_B1_STATUS_b1_miss_MASK                           0x08000000
+#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT                          27
+#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT                        0
+
+/* BSPI :: B1_STATUS :: b1_hit [26:26] */
+#define BCHP_BSPI_B1_STATUS_b1_hit_MASK                            0x04000000
+#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT                           26
+#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT                         0
+
+/* BSPI :: B1_STATUS :: b1_address [25:00] */
+#define BCHP_BSPI_B1_STATUS_b1_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT                       0
+#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT                     0
+
+/***************************************************************************
+ *B1_CTRL - Prefetch Buffer 1 Control Register
+ ***************************************************************************/
+/* BSPI :: B1_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B1_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B1_CTRL :: b1_flush [00:00] */
+#define BCHP_BSPI_B1_CTRL_b1_flush_MASK                            0x00000001
+#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT                           0
+#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT                         0
+
+/***************************************************************************
+ *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
+ ***************************************************************************/
+/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK               0xffffffe0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT              5
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK             0x00000010
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT            4
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT          0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK               0x00000008
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT              3
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT            0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK      0x00000004
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT     2
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT   0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK         0x00000002
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT        1
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT      0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK                0x00000001
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT               0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT             0
+
+/***************************************************************************
+ *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT                 1
+
+/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK      0x00000001
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT     0
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT   0
+
+/***************************************************************************
+ *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK                    0xfc000000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT                   26
+
+/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK               0x03000000
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT            0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK                    0x00fc0000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT                   18
+
+/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK              0x00030000
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK                    0x0000fc00
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT                   10
+
+/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK              0x00000300
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT             8
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK                    0x000000fc
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT                   2
+
+/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK              0x00000003
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT             0
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT           0
+
+/***************************************************************************
+ *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK                    0xfe000000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT                   25
+
+/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK               0x01000000
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT            0
+
+/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK                    0x00fe0000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT                   17
+
+/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK              0x00010000
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK                    0x0000fe00
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT                   9
+
+/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK                     0x00000100
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT                    8
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT                  0
+
+/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK                 0x000000ff
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT                0
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT              8
+
+/***************************************************************************
+ *CMD_AND_MODE_BYTE - Command and Mode Data Register
+ ***************************************************************************/
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK                 0xff000000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT                24
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK            0x00ff0000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT           16
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT         0
+
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK                 0x0000ff00
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT                8
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK             0x000000ff
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT            0
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT          11
+
+/***************************************************************************
+ *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
+ ***************************************************************************/
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0
+
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK        0x00ffffff
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT       0
+
+/***************************************************************************
+ *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK               0xfff00000
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT              20
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT            0
+
+/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK                    0x000fffff
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT                  1
+
+/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK             0x00000001
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT            0
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT          0
+
+/***************************************************************************
+ *BSPI_PIO_MODE_ENABLE - BSPI Pin  Programmed IO Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK              0xfffffffe
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT             1
+
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK          0x00000001
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT         0
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT       0
+
+/***************************************************************************
+ *BSPI_PIO_IODIR - BSPI Pin  Programmed IO Mode Direction Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK                    0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT                   3
+
+/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT              3
+
+/***************************************************************************
+ *BSPI_PIO_DATA - BSPI Pin  Programmed IO Mode Data Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK                     0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT                    3
+
+/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT              0
+
+#endif /* #ifndef BCHP_BSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_bspi_raf.h b/include/linux/brcmstb/7344b0/bchp_bspi_raf.h
new file mode 100644
index 0000000..2071da6
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_bspi_raf.h
@@ -0,0 +1,163 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:47:07 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_bspi_raf.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 1:01p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_RAF_H__
+#define BCHP_BSPI_RAF_H__
+
+/***************************************************************************
+ *BSPI_RAF - Public Linear Read BSPI Pipe Registers
+ ***************************************************************************/
+#define BCHP_BSPI_RAF_START_ADDR                 0x00003100 /* Physical Starting Address Location in Flash device */
+#define BCHP_BSPI_RAF_NUM_WORDS                  0x00003104 /* Number of Words to be fetched */
+#define BCHP_BSPI_RAF_CTRL                       0x00003108 /* RAF Session Control Register */
+#define BCHP_BSPI_RAF_FULLNESS                   0x0000310c /* Fullness indicator for the read ahead buffer */
+#define BCHP_BSPI_RAF_WATERMARK                  0x00003110 /* Watermark level in the read ahead buffer that triggers an interrupt */
+#define BCHP_BSPI_RAF_STATUS                     0x00003114 /* Linear Read Status Register */
+#define BCHP_BSPI_RAF_READ_DATA                  0x00003118 /* Read data from Raf-buffer */
+#define BCHP_BSPI_RAF_WORD_CNT                   0x0000311c /* Current number of words fetched from Flash */
+#define BCHP_BSPI_RAF_CURR_ADDR                  0x00003120 /* Current read address for the linear read session */
+
+/***************************************************************************
+ *START_ADDR - Physical Starting Address Location in Flash device
+ ***************************************************************************/
+/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK                   0xffffffff
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT                  0
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT                0
+
+/***************************************************************************
+ *NUM_WORDS - Number of Words to be fetched
+ ***************************************************************************/
+/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK                      0xffffffff
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT                     0
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT                   0
+
+/***************************************************************************
+ *CTRL - RAF Session Control Register
+ ***************************************************************************/
+/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT                         2
+
+/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
+#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK                              0x00000002
+#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT                             1
+#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT                           0
+
+/* BSPI_RAF :: CTRL :: START [00:00] */
+#define BCHP_BSPI_RAF_CTRL_START_MASK                              0x00000001
+#define BCHP_BSPI_RAF_CTRL_START_SHIFT                             0
+#define BCHP_BSPI_RAF_CTRL_START_DEFAULT                           0
+
+/***************************************************************************
+ *FULLNESS - Fullness indicator for the read ahead buffer
+ ***************************************************************************/
+/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK                      0xffffff80
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT                     7
+
+/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK                       0x0000007f
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT                      0
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT                    0
+
+/***************************************************************************
+ *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
+ ***************************************************************************/
+/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK                     0xfffffffc
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT                    2
+
+/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK            0x00000003
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT           0
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT         0
+
+/***************************************************************************
+ *STATUS - Linear Read Status Register
+ ***************************************************************************/
+/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
+#define BCHP_BSPI_RAF_STATUS_reserved0_MASK                        0xfffffff8
+#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT                       3
+
+/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK                        0x00000004
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT                       2
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT                     0
+
+/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK                       0x00000002
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT                      1
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT                    1
+
+/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK                     0x00000001
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT                    0
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT                  0
+
+/***************************************************************************
+ *READ_DATA - Read data from Raf-buffer
+ ***************************************************************************/
+/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
+#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK                          0xffffffff
+#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT                         0
+#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT                       0
+
+/***************************************************************************
+ *WORD_CNT - Current number of words fetched from Flash
+ ***************************************************************************/
+/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK             0xffffffff
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT            0
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *CURR_ADDR - Current read address for the linear read session
+ ***************************************************************************/
+/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK               0xffffffff
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT              0
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT            0
+
+#endif /* #ifndef BCHP_BSPI_RAF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_clkgen.h b/include/linux/brcmstb/7344b0/bchp_clkgen.h
new file mode 100644
index 0000000..9d9fe32
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_clkgen.h
@@ -0,0 +1,5694 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 31 13:56:02 2011
+ *                 MD5 Checksum         b0a0062767e487fe78d25d07b5b21b78
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_clkgen.h $
+ * 
+ * Hydra_Software_Devel/2   5/31/11 3:28p albertl
+ * SW7344-40: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_CLKGEN_H__
+#define BCHP_CLKGEN_H__
+
+/***************************************************************************
+ *CLKGEN - clkgen registers
+ ***************************************************************************/
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL       0x00040000 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV           0x00040004 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN          0x00040008 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS   0x0004000c /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN         0x00040010 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET         0x00040014 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x00040018 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x0004001c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS        0x00040020 /* Test Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL       0x00040024 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV           0x00040028 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN          0x0004002c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS   0x00040030 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN         0x00040034 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET         0x00040038 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x0004003c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x00040040 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS        0x00040044 /* Test Status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0 0x00040048 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1 0x0004004c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2 0x00040050 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL          0x00040054 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV              0x00040058 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN             0x0004005c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS      0x00040060 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC             0x00040064 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2            0x00040068 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN            0x0004006c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET            0x00040070 /* Resets */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH 0x00040074 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW 0x00040078 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS           0x0004007c /* Test Status */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 0x00040080 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 0x00040084 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL         0x00040088 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV             0x0004008c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN            0x00040090 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS     0x00040094 /* Lock Status */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC            0x00040098 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2           0x0004009c /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN           0x000400a0 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET           0x000400a4 /* Resets */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x000400a8 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x000400ac /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS          0x000400b0 /* Test Status */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 0x000400b4 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 0x000400b8 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 0x000400bc /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 0x000400c0 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 0x000400c4 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 0x000400c8 /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL         0x000400cc /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV             0x000400d0 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN            0x000400d4 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS     0x000400d8 /* Lock Status */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC            0x000400dc /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2           0x000400e0 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN           0x000400e4 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET           0x000400e8 /* Resets */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH 0x000400ec /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW 0x000400f0 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS          0x000400f4 /* Test Status */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 0x000400f8 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 0x000400fc /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL        0x00040100 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV            0x00040104 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN           0x00040108 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS    0x0004010c /* Lock Status */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC           0x00040110 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2          0x00040114 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN          0x00040118 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET          0x0004011c /* Resets */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH 0x00040120 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW 0x00040124 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS         0x00040128 /* Test Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0 0x0004012c /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1 0x00040130 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2 0x00040134 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL           0x00040138 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV               0x0004013c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN              0x00040140 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS       0x00040144 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC              0x00040148 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN             0x0004014c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET             0x00040150 /* Resets */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH 0x00040154 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW 0x00040158 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS            0x0004015c /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x00040160 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x00040164 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x00040168 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x0004016c /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x00040170 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x00040174 /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL         0x00040178 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV             0x0004017c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN            0x00040180 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS     0x00040184 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC            0x00040188 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2           0x0004018c /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN           0x00040190 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET           0x00040194 /* Resets */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x00040198 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x0004019c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS          0x000401a0 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 0x000401a4 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 0x000401a8 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 0x000401ac /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 0x000401b0 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 0x000401b4 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 0x000401b8 /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL         0x000401bc /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV             0x000401c0 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN            0x000401c4 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS     0x000401c8 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC            0x000401cc /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN           0x000401d0 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET           0x000401d4 /* Resets */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH 0x000401d8 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW 0x000401dc /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS          0x000401e0 /* Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 0x000401e4 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 0x000401e8 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 0x000401ec /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL         0x000401f0 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV             0x000401f4 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC            0x000401f8 /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN            0x000401fc /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS     0x00040200 /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC            0x00040204 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN           0x00040208 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET           0x0004020c /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH 0x00040210 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW 0x00040214 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS          0x00040218 /* Test Status */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE    0x0004021c /* Bvn top inst clock enable */
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE 0x00040220 /* Bvn top inst memory standby enable */
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY 0x00040224 /* Bvn top inst power switch memory */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE         0x00040228 /* Disable CLKGEN's clocks */
+#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE     0x0004022c /* Clkgen inst clock enable */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL        0x00040230 /* Clock Monitor Control */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT      0x00040234 /* Clock Monitor Max Reference Count */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER    0x00040238 /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE       0x0004023c /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER   0x00040240 /* Clock Monitor View Counter */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE  0x00040244 /* Disable CORE_XPT_INST's clocks */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE   0x00040248 /* Core xpt inst clock enable */
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE 0x0004024c /* Core xpt inst memory standby enable */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK  0x00040250 /* Core xpt inst observe clock */
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY 0x00040254 /* Core xpt inst power switch memory */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE 0x00040258 /* Disable DUAL_GENET_TOP_RGMII_INST's clocks */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE 0x0004025c /* Dual genet top rgmii inst clock enable */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT 0x00040260 /* Dual genet top rgmii inst clock select */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A 0x00040264 /* Dual genet top rgmii inst memory standby enable a */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK 0x00040268 /* Dual genet top rgmii inst observe clock */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A 0x0004026c /* Dual genet top rgmii inst power switch memory a */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE    0x00040270 /* Disable DVP_HT_INST's clocks */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE     0x00040274 /* Dvp ht inst clock enable */
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE 0x00040278 /* Dvp ht inst memory standby enable */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK    0x0004027c /* Dvp ht inst observe clock */
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY 0x00040280 /* Dvp ht inst power switch memory */
+#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE    0x00040284 /* Fsk top inst clock enable */
+#define BCHP_CLKGEN_FSK_TOP_INST_MEMORY_STANDBY_ENABLE 0x00040288 /* Fsk top inst memory standby enable */
+#define BCHP_CLKGEN_FSK_TOP_INST_POWER_SWITCH_MEMORY 0x0004028c /* Fsk top inst power switch memory */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE  0x00040290 /* Disable GRAPHICS_INST's clocks */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE   0x00040294 /* Graphics inst clock enable */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE 0x00040298 /* Graphics inst memory standby enable */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK  0x0004029c /* Graphics inst observe clock */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY 0x000402a0 /* Graphics inst power switch memory */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE       0x000402a4 /* Disable HIF_INST's clocks */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT          0x000402a8 /* Mux selects for Internal clocks */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE  0x000402ac /* Memsys 32 inst clock enable */
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE 0x000402b0 /* Memsys 32 inst memory standby enable */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK 0x000402b4 /* Memsys 32 inst observe clock */
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY 0x000402b8 /* Memsys 32 inst power switch memory */
+#define BCHP_CLKGEN_MEMSYS_32_INST_STATUS        0x000402bc /* Memsys 32 inst status */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE   0x000402c0 /* Moca top inst clock enable */
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE 0x000402c4 /* Moca top inst memory standby enable */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK  0x000402c8 /* Moca top inst observe clock */
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY 0x000402cc /* Moca top inst power switch memory */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION        0x000402d0 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION      0x000402d4 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE            0x000402d8 /* Disable PAD's clocks */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION   0x000402dc /* Select observation clk */
+#define BCHP_CLKGEN_PAD_MUX_SELECT               0x000402e0 /* Mux selects for Pad clocks */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION       0x000402e4 /* Select observation clk */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS  0x000402e8 /* PLL_AUDIO0 Reset Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS  0x000402ec /* PLL_AUDIO1 Reset Status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS     0x000402f0 /* PLL_AVD Reset Status */
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL       0x000402f4 /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST 0x000402f8 /* PLL_MIPS Glitchless Clock Switching */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS 0x000402fc /* PLL_MIPS Glitchless Switching */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS    0x00040300 /* PLL_MIPS Reset Status */
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL      0x00040304 /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS    0x00040308 /* PLL_MOCA Reset Status */
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL      0x0004030c /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS   0x00040310 /* PLL_RAAGA Reset Status */
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL     0x00040314 /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS      0x00040318 /* PLL_SC Reset Status */
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE           0x0004031c /* Disable */
+#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL      0x00040320 /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS    0x00040324 /* PLL_SYS1 Reset Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS    0x00040328 /* PLL_VCXO Reset Status */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL       0x0004032c /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL       0x00040330 /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x00040334 /* PLL Alive in Standby Mode */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP           0x00040338 /* Power management LDO PLL */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM        0x0004033c /* Power management LDO PLL state machine */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE 0x00040340 /* Raaga dsp top inst clock enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE 0x00040344 /* Raaga dsp top inst memory standby enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK 0x00040348 /* Raaga dsp top inst observe clock */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY 0x0004034c /* Raaga dsp top inst power switch memory */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE 0x00040350 /* Sds0 afec top inst clock enable */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE 0x00040354 /* Sds0 afec top inst memory standby enable */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK 0x00040358 /* Sds0 afec top inst observe clock */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY 0x0004035c /* Sds0 afec top inst power switch memory */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE  0x00040360 /* Disable SDS0_TOP_INST's clocks */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE   0x00040364 /* Sds0 top inst clock enable */
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK  0x00040368 /* Sds0 top inst observe clock */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA 0x0004036c /* Sectop inst clock enable m2mdma */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK    0x00040370 /* Sectop inst observe clock */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT         0x00040374 /* Mux selects for Smartcard clocks */
+#define BCHP_CLKGEN_SPARE                        0x00040378 /* Spares */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE   0x0004037c /* Svd0 top inst clock enable */
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE 0x00040380 /* Svd0 top inst memory standby enable */
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY 0x00040384 /* Svd0 top inst power switch memory */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK   0x00040388 /* Sys aon inst observe clock */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE  0x0004038c /* Disable SYS_CTRL_INST's clocks */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_ENABLE   0x00040390 /* Sys ctrl inst clock enable */
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE 0x00040394 /* Sys ctrl inst memory standby enable */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK  0x00040398 /* Sys ctrl inst observe clock */
+#define BCHP_CLKGEN_TESTPORT                     0x0004039c /* Special Testport Controls */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE  0x000403a0 /* Disable UHFR_TOP_INST's clocks */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE   0x000403a4 /* Uhfr top inst clock enable */
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE 0x000403a8 /* Uhfr top inst memory standby enable */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK  0x000403ac /* Uhfr top inst observe clock */
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY 0x000403b0 /* Uhfr top inst power switch memory */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE      0x000403b4 /* Disable USB0_INST's clocks */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE       0x000403b8 /* Usb0 inst clock enable */
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE 0x000403bc /* Usb0 inst memory standby enable */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK      0x000403c0 /* Usb0 inst observe clock */
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY 0x000403c4 /* Usb0 inst power switch memory */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE      0x000403c8 /* Disable USB1_INST's clocks */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE       0x000403cc /* Usb1 inst clock enable */
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE 0x000403d0 /* Usb1 inst memory standby enable */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK      0x000403d4 /* Usb1 inst observe clock */
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY 0x000403d8 /* Usb1 inst power switch memory */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE 0x000403dc /* Disable VEC_AIO_TOP_INST's clocks */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE 0x000403e0 /* Vec aio top inst clock enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO 0x000403e4 /* Vec aio top inst clock enable aio */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC 0x000403e8 /* Vec aio top inst clock enable vec */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO 0x000403ec /* Vec aio top inst memory standby enable aio */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC 0x000403f0 /* Vec aio top inst memory standby enable vec */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK 0x000403f4 /* Vec aio top inst observe clock */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO 0x000403f8 /* Vec aio top inst power switch memory aio */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC 0x000403fc /* Vec aio top inst power switch memory vec */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE  0x00040400 /* Disable ZCPU_TOP_INST's clocks */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE   0x00040404 /* Zcpu top inst clock enable */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK  0x00040408 /* Zcpu top inst observe clock */
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT                1
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT            0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT                1
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT            0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 6
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT   1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 8
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT   1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 100
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_AVD_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_SHIFT              0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AVD_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_MASK                 0xffffe000
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_SHIFT                13
+
+/* CLKGEN :: PLL_AVD_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_MASK                      0x00001c00
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_SHIFT                     10
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_DEFAULT                   3
+
+/* CLKGEN :: PLL_AVD_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_MASK                  0x000003ff
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_SHIFT                 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_DEFAULT               142
+
+/***************************************************************************
+ *PLL_AVD_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_MASK                0xff000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_SHIFT               24
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 6
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x000000e0
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       5
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     2
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_MASK         0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_SHIFT        1
+
+/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_SHIFT             0
+
+/***************************************************************************
+ *PLL_AVD_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_reserved0_MASK                0x80000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_reserved0_SHIFT               31
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_MASK                  0x60000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_SHIFT                 29
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_DEFAULT               0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_MASK                  0x10000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_SHIFT                 28
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_DEFAULT               0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_MASK              0x08000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_SHIFT             27
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_MASK              0x07000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_SHIFT             24
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__MASK              0x00800000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__SHIFT             23
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_MASK                0x00600000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_SHIFT               21
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_DEFAULT             0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_MASK                0x00100000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_SHIFT               20
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_DEFAULT             0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_MASK                 0x000c0000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_SHIFT                18
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_DEFAULT              0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_MASK               0x00020000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_SHIFT              17
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_DEFAULT            0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_MASK              0x00010000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_SHIFT             16
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_MASK              0x00008000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_SHIFT             15
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_MASK                0x00004000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_SHIFT               14
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_DEFAULT             0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  13
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00001ffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         1
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_SHIFT                0
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_DEFAULT              0
+
+/***************************************************************************
+ *PLL_AVD_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_AVD_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_DEFAULT                0
+
+/***************************************************************************
+ *PLL_AVD_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_AVD_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_SHIFT              0
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AVD_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_MASK               0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_SHIFT              2
+
+/* CLKGEN :: PLL_AVD_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_MASK                  0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_SHIFT                 1
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_DEFAULT               0
+
+/* CLKGEN :: PLL_AVD_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_SHIFT                 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_DEFAULT               0
+
+/***************************************************************************
+ *PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_MASK              0xfffff000
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_SHIFT             12
+
+/* CLKGEN :: PLL_AVD_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_SHIFT           0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 3
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 100
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_MIPS_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_DEFAULT                  3
+
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_DEFAULT              150
+
+/***************************************************************************
+ *PLL_MIPS_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 6
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_DEFAULT              0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_DEFAULT             0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_DEFAULT           0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_DEFAULT               0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MIPS_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 9
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 16
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 36
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 72
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 9
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 75
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_MOCA_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_DEFAULT                  3
+
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_DEFAULT              200
+
+/***************************************************************************
+ *PLL_MOCA_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 3
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_DEFAULT              1
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_DEFAULT             2
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_DEFAULT           0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_DEFAULT          0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_DEFAULT               0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MOCA_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_MOCA_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 7
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 9
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_RAAGA_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_SHIFT            0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_DEFAULT          0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_MASK               0xffffe000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_SHIFT              13
+
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_MASK                    0x00001c00
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_SHIFT                   10
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_DEFAULT                 2
+
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_MASK                0x000003ff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_SHIFT               0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_DEFAULT             143
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_MASK              0xff000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_SHIFT             24
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 9
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x000000e0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     5
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   2
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 4
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_MASK       0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT      1
+
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_SHIFT           0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_reserved0_MASK              0x80000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_reserved0_SHIFT             31
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_MASK                0x60000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_SHIFT               29
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_DEFAULT             0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_MASK                0x10000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_SHIFT               28
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_DEFAULT             1
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_SHIFT           27
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_DEFAULT         0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_MASK            0x07000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_SHIFT           24
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_DEFAULT         0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__MASK            0x00800000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__SHIFT           23
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__DEFAULT         0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_MASK              0x00600000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_SHIFT             21
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_DEFAULT           0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_MASK              0x00100000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_SHIFT             20
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_DEFAULT           0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_MASK               0x000c0000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_SHIFT              18
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_DEFAULT            2
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_MASK             0x00020000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_SHIFT            17
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_DEFAULT          0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_MASK            0x00010000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_SHIFT           16
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_DEFAULT         0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_MASK            0x00008000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_SHIFT           15
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_DEFAULT         0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_MASK              0x00004000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_SHIFT             14
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_DEFAULT           0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00001ffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_SHIFT              0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_DEFAULT            0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_SHIFT                0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_DEFAULT              0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_RAAGA_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_SHIFT            0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_DEFAULT          0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_MASK             0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_SHIFT            2
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_MASK                0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_SHIFT               1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_DEFAULT             0
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_SHIFT               0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_DEFAULT             0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_MASK            0xfffff000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_SHIFT           12
+
+/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_SHIFT         0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT  40
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT  40
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT  96
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SC_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_MASK                  0xffffe000
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_SHIFT                 13
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_MASK                       0x00001c00
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_SHIFT                      10
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_DEFAULT                    1
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_MASK                   0x000003ff
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_DEFAULT                64
+
+/***************************************************************************
+ *PLL_SC_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_MASK                 0xff000000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_SHIFT                24
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK         0x000000e0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT        5
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT      1
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_SHIFT              0
+
+/***************************************************************************
+ *PLL_SC_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_MASK                 0xc0000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_SHIFT                30
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_MASK                   0x30000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_SHIFT                  28
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_MASK              0x08000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_SHIFT             27
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_DEFAULT           0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_MASK                   0x04000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_SHIFT                  26
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_MASK               0x02000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_SHIFT              25
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_MASK               0x01c00000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_SHIFT              22
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__MASK               0x00200000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__SHIFT              21
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_MASK                 0x00180000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_SHIFT                19
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_MASK                 0x00040000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_SHIFT                18
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_MASK                  0x00030000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_SHIFT                 16
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_DEFAULT               0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_MASK               0x00008000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_SHIFT              15
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_MASK                 0x00004000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_SHIFT                14
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK    0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT   13
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_MASK           0x00001ffe
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_SHIFT          1
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT        0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_DEFAULT               0
+
+/***************************************************************************
+ *PLL_SC_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_SHIFT               1
+
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_SHIFT               2
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_MASK                   0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_SHIFT                  1
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_DEFAULT                0
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK  0x00400000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_MASK               0xfffff000
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_SHIFT              12
+
+/* CLKGEN :: PLL_SC_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_MASK             0x00000fff
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 18
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 36
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 81
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 48
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 10
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT                  1
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT              72
+
+/***************************************************************************
+ *PLL_SYS0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 10
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    3
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 4
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT              1
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT             2
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT           0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT               0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_RESET :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_RESET :: RESETD [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_DEFAULT              0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 9
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 18
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 9
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 90
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 90
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 45
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_DEFAULT                  3
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_DEFAULT              125
+
+/***************************************************************************
+ *PLL_SYS1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    1
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_MASK                 0x30000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_SHIFT           27
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_DEFAULT         0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_DEFAULT              1
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_MASK             0x02000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_SHIFT            25
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_MASK             0x01c00000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_SHIFT            22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__MASK             0x00200000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__SHIFT            21
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_SHIFT              19
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_MASK                0x00030000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_SHIFT               16
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_DEFAULT             2
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 64
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 250
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 75
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_DEFAULT                  2
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_DEFAULT              64
+
+/***************************************************************************
+ *PLL_VCXO_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_MASK               0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_SHIFT              20
+
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_MASK            0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_SHIFT           0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    1
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_MASK                 0x30000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_SHIFT                28
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_SHIFT           27
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_DEFAULT         0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_MASK             0x02000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_SHIFT            25
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_MASK             0x01c00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_SHIFT            22
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__MASK             0x00200000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__SHIFT            21
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_SHIFT              19
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_MASK                0x00030000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_SHIFT               16
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_DEFAULT             0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_SHIFT            15
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *BVN_TOP_INST_CLOCK_ENABLE - Bvn top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffff8
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      3
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *BVN_TOP_INST_MEMORY_STANDBY_ENABLE - Bvn top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: BVN_TOP_INST_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *BVN_TOP_INST_POWER_SWITCH_MEMORY - Bvn top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: BVN_TOP_INST_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks
+ ***************************************************************************/
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT           2
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_OSC_DIGITAL_CLOCK [01:01] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_AVS_CLOCK [00:00] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_MASK    0x00000001
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_SHIFT   0
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *CLKGEN_INST_CLOCK_ENABLE - Clkgen inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_reserved0_SHIFT       1
+
+/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: CG_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *CLOCK_MONITOR_CONTROL - Clock Monitor Control
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT          4
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK   0x00000008
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT  3
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK    0x00000004
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT   2
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK      0x00000002
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT     1
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT   1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 1
+
+/***************************************************************************
+ *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK  0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT         1
+
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK     0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT    0
+
+/***************************************************************************
+ *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_CLOCK_DISABLE - Disable CORE_XPT_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_MASK     0xffffffe0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_SHIFT    5
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_CLOCK_ENABLE - Core xpt inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffff8
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_SHIFT     3
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *CORE_XPT_INST_MEMORY_STANDBY_ENABLE - Core xpt inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: CORE_XPT_INST_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_OBSERVE_CLOCK - Core xpt inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_POWER_SWITCH_MEMORY - Core xpt inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: CORE_XPT_INST_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE - Disable DUAL_GENET_TOP_RGMII_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_SHIFT 6
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET_ALWAYSON_CLOCK [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_PM_CLOCK [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_FAST_CLOCK [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE - Dual genet top rgmii inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: reserved0 [31:15] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_MASK 0xffff8000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_SHIFT 15
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [14:14] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00004000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 14
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_108_CLOCK_ENABLE [13:13] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE [12:12] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00001000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE [11:11] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00000800
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 11
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET1_L2INTR_CLOCK_ENABLE [10:10] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_MASK 0x00000400
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_SHIFT 10
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET1_HFB_CLOCK_ENABLE [09:09] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_MASK 0x00000200
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_SHIFT 9
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET1_GMII_CLOCK_ENABLE [08:08] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_MASK 0x00000100
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_SHIFT 8
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET1_EEE_CLOCK_ENABLE [07:07] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_MASK 0x00000080
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_SHIFT 7
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_L2INTR_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_HFB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_GMII_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_EEE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_CLK_250_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT - Dual genet top rgmii inst clock select
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT :: reserved0 [31:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_reserved0_SHIFT 4
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET1_GMII_CLOCK_SELECT [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET1_CLOCK_SELECT [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET0_GMII_CLOCK_SELECT [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET0_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A - Dual genet top rgmii inst memory standby enable a
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: GENET0_MEMORY_STANDBY_ENABLE_A [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK - Dual genet top rgmii inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: GENET_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A - Dual genet top rgmii inst power switch memory a
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A :: GENET0_POWER_SWITCH_MEMORY_A [01:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_MASK 0x00000003
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_INST_CLOCK_DISABLE - Disable DVP_HT_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_INST_CLOCK_ENABLE - Dvp ht inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_MASK        0xffffffc0
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_SHIFT       6
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_VEC_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_VEC_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_VEC_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_VEC_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_MAX_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_MAX_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_MAX_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_MAX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_ALTERNATE_216_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_ALTERNATE_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *DVP_HT_INST_MEMORY_STANDBY_ENABLE - Dvp ht inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: DVP_HT_INST_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_INST_OBSERVE_CLOCK - Dvp ht inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_INST_POWER_SWITCH_MEMORY - Dvp ht inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: DVP_HT_INST_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *FSK_TOP_INST_CLOCK_ENABLE - Fsk top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      2
+
+/* CLKGEN :: FSK_TOP_INST_CLOCK_ENABLE :: FTM_CH0_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_FTM_CH0_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_FTM_CH0_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_FTM_CH0_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: FSK_TOP_INST_CLOCK_ENABLE :: FTM_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_FTM_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_FTM_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_FTM_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *FSK_TOP_INST_MEMORY_STANDBY_ENABLE - Fsk top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_FSK_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_FSK_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: FSK_TOP_INST_MEMORY_STANDBY_ENABLE :: FTM_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_FSK_TOP_INST_MEMORY_STANDBY_ENABLE_FTM_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_FSK_TOP_INST_MEMORY_STANDBY_ENABLE_FTM_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_INST_MEMORY_STANDBY_ENABLE_FTM_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *FSK_TOP_INST_POWER_SWITCH_MEMORY - Fsk top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_FSK_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_FSK_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: FSK_TOP_INST_POWER_SWITCH_MEMORY :: FTM_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_FSK_TOP_INST_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_FSK_TOP_INST_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_INST_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_DISABLE - Disable GRAPHICS_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_reserved0_SHIFT    2
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_DISABLE :: DISABLE_GFX_V3D_CORE_CLOCK [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_V3D_CORE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_V3D_CORE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_V3D_CORE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_DISABLE :: DISABLE_GFX_M2MC_CORE_CLOCK [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE - Graphics inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: reserved0 [31:07] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_MASK      0xffffff80
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_SHIFT     7
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_V3D_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_SCB_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_M2MC_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_ALTERNATE_216_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_ALTERNATE_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *GRAPHICS_INST_MEMORY_STANDBY_ENABLE - Graphics inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE :: GFX_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_OBSERVE_CLOCK - Graphics inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_POWER_SWITCH_MEMORY - Graphics inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY :: GFX_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *HIF_INST_CLOCK_DISABLE - Disable HIF_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_MASK          0xfffffff0
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_SHIFT         4
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [03:03] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CLOCK [02:02] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_DEFAULT 0
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_EBI_CLOCK [01:01] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_DEFAULT 0
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_54_SCANCLOCK [00:00] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_DEFAULT 1
+
+/***************************************************************************
+ *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
+ ***************************************************************************/
+/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:05] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK             0xffffffe0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT            5
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: STRAP_OVERRIDE_HIF_SPI_CLOCK [04:04] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_STRAP_OVERRIDE_HIF_SPI_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_STRAP_OVERRIDE_HIF_SPI_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_STRAP_OVERRIDE_HIF_SPI_CLOCK_DEFAULT 0
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [03:03] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [02:02] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: HIF_SPI_CLOCK [01:00] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_HIF_SPI_CLOCK_MASK         0x00000003
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_HIF_SPI_CLOCK_SHIFT        0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_HIF_SPI_CLOCK_DEFAULT      0
+
+/***************************************************************************
+ *MEMSYS_32_INST_CLOCK_ENABLE - Memsys 32 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_reserved0_SHIFT    2
+
+/* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE :: MEMSYS_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE :: MEMSYS_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *MEMSYS_32_INST_MEMORY_STANDBY_ENABLE - Memsys 32 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MEMSYS_32_INST_MEMORY_STANDBY_ENABLE :: MEMSYS_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_MEMSYS_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_MEMSYS_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_MEMSYS_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_32_INST_OBSERVE_CLOCK - Memsys 32 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_reserved0_MASK    0xffffffc0
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_reserved0_SHIFT   6
+
+/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: MEMSYS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: MEMSYS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_32_INST_POWER_SWITCH_MEMORY - Memsys 32 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: MEMSYS_32_INST_POWER_SWITCH_MEMORY :: MEMSYS_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_MEMSYS_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_MEMSYS_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_MEMSYS_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_32_INST_STATUS - Memsys 32 inst status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_STATUS_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_INST_STATUS_reserved0_SHIFT          1
+
+/* CLKGEN :: MEMSYS_32_INST_STATUS :: MEMSYS_PLL_LOCKED_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_STATUS_MEMSYS_PLL_LOCKED_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_INST_STATUS_MEMSYS_PLL_LOCKED_STATUS_SHIFT 0
+
+/***************************************************************************
+ *MOCA_TOP_INST_CLOCK_ENABLE - Moca top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     2
+
+/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: MOCA_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: MOCA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *MOCA_TOP_INST_MEMORY_STANDBY_ENABLE - Moca top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MOCA_TOP_INST_MEMORY_STANDBY_ENABLE :: MOCA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *MOCA_TOP_INST_OBSERVE_CLOCK - Moca top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *MOCA_TOP_INST_POWER_SWITCH_MEMORY - Moca top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: MOCA_TOP_INST_POWER_SWITCH_MEMORY :: MOCA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLK27_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_MASK           0xfffffe00
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_SHIFT          9
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_MASK  0x00000100
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_MASK  0x000000fe
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK  0x00000001
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLK_ACC_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_ACC_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_reserved0_MASK         0xfffffe00
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_reserved0_SHIFT        9
+
+/* CLKGEN :: PAD_CLK_ACC_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_ACC_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_ACC_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLOCK_DISABLE - Disable PAD's clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK               0xfffffff0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT              4
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_VCXO27_CLOCK [03:03] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [02:02] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLKACC_CLOCK [01:01] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKACC_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKACC_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKACC_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CODEC_MCLK_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_MASK      0xfffffe00
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_SHIFT     9
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_MUX_SELECT - Mux selects for Pad clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:10] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK                  0xfffffc00
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT                 10
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_VCXO27_CLOCK [09:07] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_MASK    0x00000380
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_SHIFT   7
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLKACC_CLOCK [06:04] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLKACC_CLOCK_MASK    0x00000070
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLKACC_CLOCK_SHIFT   4
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLKACC_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK27_CLOCK [03:01] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_MASK     0x0000000e
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_SHIFT    1
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_DEFAULT  0
+
+/* CLKGEN :: PAD_MUX_SELECT :: ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *PAD_VCXO27_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_MASK          0xfffffe00
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_SHIFT         9
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET_STATUS - PLL_AUDIO0 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET_STATUS - PLL_AUDIO1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_RESET_STATUS - PLL_AVD Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AVD_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_RDB_MACRO_CTRL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_reserved0_MASK          0xfffffff0
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_reserved0_SHIFT         4
+
+/* CLKGEN :: PLL_AVD_RDB_MACRO_CTRL :: PLL_AVD_OPTIONS_DISABLE_RDB_MACRO [03:03] */
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_PLL_AVD_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_PLL_AVD_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_PLL_AVD_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_RDB_MACRO_CTRL :: OPTIONS [02:00] */
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_OPTIONS_MASK            0x00000007
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_OPTIONS_SHIFT           0
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_OPTIONS_DEFAULT         0
+
+/***************************************************************************
+ *PLL_MIPS_GLITCHLESS_SWITCH_REQUEST - PLL_MIPS Glitchless Clock Switching
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_reserved0_SHIFT 9
+
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: TRANSACTION_WAIT [08:01] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_DEFAULT 31
+
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: PLL_BYPASS_REQUEST [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_GLITCHLESS_SWITCH_STATUS - PLL_MIPS Glitchless Switching
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_STATUS :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_reserved0_SHIFT 4
+
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_STATUS :: PLL_BYPASS_STATUS [03:00] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_MASK 0x0000000f
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_RESET_STATUS - PLL_MIPS Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_MIPS_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_RDB_MACRO_CTRL :: reserved0 [31:05] */
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_reserved0_MASK         0xffffffe0
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_reserved0_SHIFT        5
+
+/* CLKGEN :: PLL_MIPS_RDB_MACRO_CTRL :: PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO [04:04] */
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO_SHIFT 4
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_RDB_MACRO_CTRL :: OPTIONS [03:00] */
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_OPTIONS_MASK           0x0000000f
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_OPTIONS_SHIFT          0
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_OPTIONS_DEFAULT        0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_RESET_STATUS - PLL_MOCA Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_MOCA_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: OPTIONS [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_SHIFT          0
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_DEFAULT        0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_RESET_STATUS - PLL_RAAGA Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_SHIFT     2
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_RAAGA_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_MASK        0xfffffff0
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_SHIFT       4
+
+/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO [03:03] */
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: OPTIONS [02:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_MASK          0x00000007
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_SHIFT         0
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_DEFAULT       0
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET_STATUS - PLL_SC Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_STRAP_OVERRIDE - Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_STRAP_OVERRIDE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_STRAP_OVERRIDE :: STRAP_FREQ_PLLSYS0_DISABLE [01:01] */
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLSYS0_DISABLE_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLSYS0_DISABLE_SHIFT 1
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLSYS0_DISABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_STRAP_OVERRIDE :: STRAP_FREQ_PLLMIPS_DISABLE [00:00] */
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_RDB_MACRO_CTRL :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_reserved0_MASK         0xfffffff8
+#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_reserved0_SHIFT        3
+
+/* CLKGEN :: PLL_SYS0_RDB_MACRO_CTRL :: PLL_SYS0_OPTIONS_DISABLE_RDB_MACRO [02:02] */
+#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_PLL_SYS0_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000004
+#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_PLL_SYS0_OPTIONS_DISABLE_RDB_MACRO_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_PLL_SYS0_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_RDB_MACRO_CTRL :: OPTIONS [01:00] */
+#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_OPTIONS_MASK           0x00000003
+#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_OPTIONS_SHIFT          0
+#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_OPTIONS_DEFAULT        0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET_STATUS - PLL_SYS1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET_STATUS - PLL_VCXO Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PM_CLOCK_108_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_MASK          0xfffffff8
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_SHIFT         3
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSTOP0 [02:02] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTOP0_MASK 0x00000004
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTOP0_SHIFT 2
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTOP0_DEFAULT 0
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSAFEC0 [01:01] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC0_MASK 0x00000002
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC0_SHIFT 1
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC0_DEFAULT 0
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_FSK [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_FSK_MASK   0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_FSK_SHIFT  0
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_FSK_DEFAULT 0
+
+/***************************************************************************
+ *PM_CLOCK_216_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_SHIFT         1
+
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_MASK   0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT  0
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_DEFAULT 0
+
+/***************************************************************************
+ *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               3
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys_PLL [02:02] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_MASK               0x00000004
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_SHIFT              2
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_DEFAULT            0
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [01:01] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK                 0x00000002
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT                1
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT              0
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_MIPS [00:00] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_MASK                 0x00000001
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_SHIFT                0
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_DEFAULT              0
+
+/***************************************************************************
+ *PM_PLL_LDO_POWERUP - Power management LDO PLL
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_SHIFT             3
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_RAAGA [02:02] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_MASK    0x00000004
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_SHIFT   2
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_DEFAULT 1
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_MOCA [01:01] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_MASK     0x00000002
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_SHIFT    1
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_DEFAULT  1
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AVD [00:00] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_MASK      0x00000001
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_SHIFT     0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_DEFAULT   1
+
+/***************************************************************************
+ *PM_PLL_LDO_POWERUP_SM - Power management LDO PLL state machine
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: reserved0 [31:27] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_MASK           0xf8000000
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_SHIFT          27
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_POWERUP_WAIT_TIME [26:14] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_MASK 0x07ffc000
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_SHIFT 14
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_DEFAULT 5400
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_CLK_STOP_WAIT_TIME [13:01] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_MASK 0x00003ffe
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_SHIFT 1
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_DEFAULT 200
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: GISB_OVERRIDE_SM [00:00] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_MASK    0x00000001
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_SHIFT   0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_DEFAULT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_CLOCK_ENABLE - Raaga dsp top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_DSP_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE - Raaga dsp top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE :: RAAGAA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_OBSERVE_CLOCK - Raaga dsp top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_ENABLE_OBSERVE_CLOCK [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY - Raaga dsp top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY :: RAAGA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SDS0_AFEC_TOP_INST_CLOCK_ENABLE - Sds0 afec top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS0_AFEC_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_CLOCK_ENABLE :: SDSAFEC0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE - Sds0 afec top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE :: SDSAFEC0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SDS0_AFEC_TOP_INST_OBSERVE_CLOCK - Sds0 afec top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY - Sds0 afec top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY :: SDSAFEC0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SDS0_TOP_INST_CLOCK_DISABLE - Disable SDS0_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: SDS0_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1
+
+/* CLKGEN :: SDS0_TOP_INST_CLOCK_DISABLE :: DISABLE_SDSTOP0_108_PRESPMBALANCE_CLOCK [00:00] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_DISABLE_SDSTOP0_108_PRESPMBALANCE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_DISABLE_SDSTOP0_108_PRESPMBALANCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_DISABLE_SDSTOP0_108_PRESPMBALANCE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SDS0_TOP_INST_CLOCK_ENABLE - Sds0 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: SDS0_TOP_INST_CLOCK_ENABLE :: SDS_TOP0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_SDS_TOP0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_SDS_TOP0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_SDS_TOP0_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SDS0_TOP_INST_OBSERVE_CLOCK - Sds0 top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS0_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:12] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xfffff000
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    12
+
+/* CLKGEN :: SDS0_TOP_INST_OBSERVE_CLOCK :: SDS_TOP0_TFEC_ENABLE_OBSERVE_CLOCK [11:11] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_ENABLE_OBSERVE_CLOCK_MASK 0x00000800
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_ENABLE_OBSERVE_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_TOP_INST_OBSERVE_CLOCK :: SDS_TOP0_TFEC_ENABLE_DIVIDER_OBSERVE_CLOCK [10:10] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_TOP_INST_OBSERVE_CLOCK :: SDS_TOP0_TFEC_CONTROL_OBSERVE_CLOCK [09:06] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_CONTROL_OBSERVE_CLOCK_MASK 0x000003c0
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_CONTROL_OBSERVE_CLOCK_SHIFT 6
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_TOP_INST_OBSERVE_CLOCK :: SDS_TOP0_RCVR_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_TOP_INST_OBSERVE_CLOCK :: SDS_TOP0_RCVR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_TOP_INST_OBSERVE_CLOCK :: SDS_TOP0_RCVR_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SECTOP_INST_CLOCK_ENABLE_M2MDMA - Sectop inst clock enable m2mdma
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_reserved0_SHIFT 1
+
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA :: M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_DEFAULT 1
+
+/***************************************************************************
+ *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SEC_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SEC_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SEC_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
+ ***************************************************************************/
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:08] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK            0xffffff00
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT           8
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [07:05] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK            0x000000e0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT           5
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT         0
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [04:02] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK            0x0000001c
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT           2
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT         0
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: PLLSC_REFERENCE_CLOCK [01:00] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_MASK 0x00000003
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SPARE - Spares
+ ***************************************************************************/
+/* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK                     0xfffff000
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT                    12
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT                  0
+
+/* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK                    0x00000fff
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT                   0
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT                 0
+
+/***************************************************************************
+ *SVD0_TOP_INST_CLOCK_ENABLE - Svd0 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xffffffe0
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     5
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD_SCB_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD_CPU_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD_CORE_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CORE_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CORE_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CORE_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD_ALTERNATE_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SVD0_TOP_INST_MEMORY_STANDBY_ENABLE - Svd0 top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SVD0_TOP_INST_MEMORY_STANDBY_ENABLE :: SVD_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SVD0_TOP_INST_POWER_SWITCH_MEMORY - Svd0 top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SVD0_TOP_INST_POWER_SWITCH_MEMORY :: SVD_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SYS_AON_INST_OBSERVE_CLOCK - Sys aon inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_INST_CLOCK_DISABLE - Disable SYS_CTRL_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffff0
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_SHIFT    4
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_UHFR_CLOCK [03:03] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UHFR_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UHFR_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UHFR_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK [02:02] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_INST_CLOCK_ENABLE - Sys ctrl inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_ENABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_ENABLE :: SYS_CTRL_SCB_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SYS_CTRL_INST_MEMORY_STANDBY_ENABLE - Sys ctrl inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SYS_CTRL_INST_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_INST_OBSERVE_CLOCK - Sys ctrl inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *TESTPORT - Special Testport Controls
+ ***************************************************************************/
+/* CLKGEN :: TESTPORT :: reserved0 [31:04] */
+#define BCHP_CLKGEN_TESTPORT_reserved0_MASK                        0xfffffff0
+#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT                       4
+
+/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [03:00] */
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK           0x0000000f
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT          0
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT        0
+
+/***************************************************************************
+ *UHFR_TOP_INST_CLOCK_DISABLE - Disable UHFR_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1
+
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE :: DISABLE_UHFR_ALWAYSON_CLOCK [00:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *UHFR_TOP_INST_CLOCK_ENABLE - Uhfr top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE :: UHFR_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *UHFR_TOP_INST_MEMORY_STANDBY_ENABLE - Uhfr top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: UHFR_TOP_INST_MEMORY_STANDBY_ENABLE :: UHFR_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *UHFR_TOP_INST_OBSERVE_CLOCK - Uhfr top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *UHFR_TOP_INST_POWER_SWITCH_MEMORY - Uhfr top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: UHFR_TOP_INST_POWER_SWITCH_MEMORY :: UHFR_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *USB0_INST_CLOCK_DISABLE - Disable USB0_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_reserved0_SHIFT        2
+
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: DISABLE_USB_54_MDIO_CLOCK [01:01] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: DISABLE_USB0_27_FREERUN_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_27_FREERUN_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_27_FREERUN_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_27_FREERUN_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB0_INST_CLOCK_ENABLE - Usb0 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: USB0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *USB0_INST_MEMORY_STANDBY_ENABLE - Usb0 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: USB0_INST_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *USB0_INST_OBSERVE_CLOCK - Usb0 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB0_INST_POWER_SWITCH_MEMORY - Usb0 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: USB0_INST_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *USB1_INST_CLOCK_DISABLE - Disable USB1_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_reserved0_SHIFT        2
+
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: DISABLE_USB_54_MDIO_CLOCK [01:01] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: DISABLE_USB1_27_FREERUN_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_27_FREERUN_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_27_FREERUN_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_27_FREERUN_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB1_INST_CLOCK_ENABLE - Usb1 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: USB1_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: USB1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *USB1_INST_MEMORY_STANDBY_ENABLE - Usb1 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: USB1_INST_MEMORY_STANDBY_ENABLE :: USB1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *USB1_INST_OBSERVE_CLOCK - Usb1 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB1_INST_POWER_SWITCH_MEMORY - Usb1 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: USB1_INST_POWER_SWITCH_MEMORY :: USB1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_DISABLE - Disable VEC_AIO_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_MASK  0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_ITU656_CLOCK [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_DEFAULT 0
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE - Vec aio top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_AIO_ALTERNATE_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO - Vec aio top inst clock enable aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_DEFAULT 1
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC - Vec aio top inst clock enable vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: reserved0 [31:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_SHIFT 5
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_SCB_CLOCK_ENABLE_VEC [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_QDAC_216_CLOCK_ENABLE_VEC [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_SHIFT 3
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_ALTERNATE_216_CLOCK_ENABLE_VEC [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_216_CLOCK_ENABLE_VEC [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_108_CLOCK_ENABLE_VEC [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO - Vec aio top inst memory standby enable aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO :: AIO_MEMORY_STANDBY_ENABLE_AIO [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC - Vec aio top inst memory standby enable vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC :: VEC_MEMORY_STANDBY_ENABLE_VEC [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_OBSERVE_CLOCK - Vec aio top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_AIO_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_AIO_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO - Vec aio top inst power switch memory aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO :: AIO_POWER_SWITCH_MEMORY_AIO [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC - Vec aio top inst power switch memory vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC :: VEC_POWER_SWITCH_MEMORY_VEC [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_DEFAULT 0
+
+/***************************************************************************
+ *ZCPU_TOP_INST_CLOCK_DISABLE - Disable ZCPU_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1
+
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_DISABLE :: DISABLE_ZMIPS_SLOWMIPS_CLOCK [00:00] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_SLOWMIPS_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_SLOWMIPS_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_SLOWMIPS_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *ZCPU_TOP_INST_CLOCK_ENABLE - Zcpu top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffff8
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     3
+
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE :: ZMIPS_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE :: ZMIPS_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE :: ZMIPS_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *ZCPU_TOP_INST_OBSERVE_CLOCK - Zcpu top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+#endif /* #ifndef BCHP_CLKGEN_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_common.h b/include/linux/brcmstb/7344b0/bchp_common.h
new file mode 100644
index 0000000..f03d4a4
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_common.h
@@ -0,0 +1,2220 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Jul  8 19:13:13 2011
+ *                 MD5 Checksum         6d43009b3dfb16bef651d8873360bc15
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_common.h $
+ * 
+ * Hydra_Software_Devel/3   7/11/11 12:10p albertl
+ * SW7344-40: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_COMMON_H__
+#define BCHP_COMMON_H__
+
+/***************************************************************************
+ *BCM7344_B0
+ ***************************************************************************/
+#define BCHP_PHYSICAL_OFFSET                               0x10000000
+#define BCHP_REGISTER_START                                0x00000800 /* EBI is first */
+#define BCHP_REGISTER_END                                  0x01410348 /* FTM_SW_SPARE is last */
+#define BCHP_REGISTER_SIZE                                 0x00503ed2 /* Number of registers */
+
+/****************************************************************************
+ * Core instance register start address.
+ ***************************************************************************/
+#define BCHP_EBI_REG_START                                 0x00000800
+#define BCHP_EBI_REG_END                                   0x00000bfc
+#define BCHP_HIF_INTR2_REG_START                           0x00001000
+#define BCHP_HIF_INTR2_REG_END                             0x0000102c
+#define BCHP_IPI0_INTR2_REG_START                          0x00001100
+#define BCHP_IPI0_INTR2_REG_END                            0x0000112c
+#define BCHP_IPI1_INTR2_REG_START                          0x00001200
+#define BCHP_IPI1_INTR2_REG_END                            0x0000122c
+#define BCHP_HIF_CPU_INTR1_REG_START                       0x00001400
+#define BCHP_HIF_CPU_INTR1_REG_END                         0x0000142c
+#define BCHP_HIF_CPU_TP1_INTR1_REG_START                   0x00001600
+#define BCHP_HIF_CPU_TP1_INTR1_REG_END                     0x0000162c
+#define BCHP_HIF_RGR_REG_START                             0x00001800
+#define BCHP_HIF_RGR_REG_END                               0x00001810
+#define BCHP_HIF_SPI_INTR2_REG_START                       0x00001d00
+#define BCHP_HIF_SPI_INTR2_REG_END                         0x00001d2c
+#define BCHP_HIF_TOP_CTRL_REG_START                        0x00002400
+#define BCHP_HIF_TOP_CTRL_REG_END                          0x00002418
+#define BCHP_NAND_REG_START                                0x00002800
+#define BCHP_NAND_REG_END                                  0x00002bfc
+#define BCHP_BSPI_REG_START                                0x00003000
+#define BCHP_BSPI_REG_END                                  0x0000304c
+#define BCHP_BSPI_RAF_REG_START                            0x00003100
+#define BCHP_BSPI_RAF_REG_END                              0x00003120
+#define BCHP_HIF_MSPI_REG_START                            0x00003200
+#define BCHP_HIF_MSPI_REG_END                              0x00003384
+#define BCHP_SDIO_0_HOST_REG_START                         0x00003500
+#define BCHP_SDIO_0_HOST_REG_END                           0x000035fc
+#define BCHP_SDIO_0_CFG_REG_START                          0x00003600
+#define BCHP_SDIO_0_CFG_REG_END                            0x000036fc
+#define BCHP_MICH_REG_START                                0x00020000
+#define BCHP_MICH_REG_END                                  0x00020000
+#define BCHP_HIF_SECURE_CTRL_REG_START                     0x00020100
+#define BCHP_HIF_SECURE_CTRL_REG_END                       0x00020100
+#define BCHP_HIF_SECURE_BSPI_REG_START                     0x00020200
+#define BCHP_HIF_SECURE_BSPI_REG_END                       0x00020200
+#define BCHP_HIF_SECURE_LR_SPI_REG_START                   0x00020300
+#define BCHP_HIF_SECURE_LR_SPI_REG_END                     0x00020300
+#define BCHP_NAND_SECURE_REG_START                         0x00020400
+#define BCHP_NAND_SECURE_REG_END                           0x00020400
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_START        0x00020800
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_END          0x00020800
+#define BCHP_CLKGEN_REG_START                              0x00040000
+#define BCHP_CLKGEN_REG_END                                0x00040408
+#define BCHP_VCXO_RM_REG_START                             0x00042800
+#define BCHP_VCXO_RM_REG_END                               0x0004282c
+#define BCHP_AVS_HW_MNTR_REG_START                         0x00043000
+#define BCHP_AVS_HW_MNTR_REG_END                           0x00043074
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_START                 0x00043100
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_END                   0x0004311c
+#define BCHP_AVS_ASB_REGISTERS_REG_START                   0x00043200
+#define BCHP_AVS_ASB_REGISTERS_REG_END                     0x00043218
+#define BCHP_AVS_RO_REGISTERS_0_REG_START                  0x00043300
+#define BCHP_AVS_RO_REGISTERS_0_REG_END                    0x000433dc
+#define BCHP_AVS_RO_REGISTERS_1_REG_START                  0x00043400
+#define BCHP_AVS_RO_REGISTERS_1_REG_END                    0x0004348c
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_START                0x00043500
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_END                  0x000435e4
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_START                0x00043600
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_END                  0x000436e4
+#define BCHP_CLKGEN_INTR2_REG_START                        0x00044000
+#define BCHP_CLKGEN_INTR2_REG_END                          0x0004402c
+#define BCHP_CLKGEN_GR_REG_START                           0x00044800
+#define BCHP_CLKGEN_GR_REG_END                             0x0004480c
+#define BCHP_GENET_0_SYS_REG_START                         0x00080000
+#define BCHP_GENET_0_SYS_REG_END                           0x0008000c
+#define BCHP_GENET_0_GR_BRIDGE_REG_START                   0x00080040
+#define BCHP_GENET_0_GR_BRIDGE_REG_END                     0x0008004c
+#define BCHP_GENET_0_EXT_REG_START                         0x00080080
+#define BCHP_GENET_0_EXT_REG_END                           0x00080098
+#define BCHP_GENET_0_INTRL2_0_REG_START                    0x00080200
+#define BCHP_GENET_0_INTRL2_0_REG_END                      0x0008022c
+#define BCHP_GENET_0_INTRL2_1_REG_START                    0x00080240
+#define BCHP_GENET_0_INTRL2_1_REG_END                      0x0008026c
+#define BCHP_GENET_0_RBUF_REG_START                        0x00080300
+#define BCHP_GENET_0_RBUF_REG_END                          0x000803ec
+#define BCHP_GENET_0_TBUF_REG_START                        0x00080600
+#define BCHP_GENET_0_TBUF_REG_END                          0x00080628
+#define BCHP_GENET_0_UMAC_REG_START                        0x00080800
+#define BCHP_GENET_0_UMAC_REG_END                          0x00080ed8
+#define BCHP_GENET_0_HFB_REG_START                         0x00081000
+#define BCHP_GENET_0_HFB_REG_END                           0x00082010
+#define BCHP_GENET_0_RDMA_REG_START                        0x00083000
+#define BCHP_GENET_0_RDMA_REG_END                          0x00083cb4
+#define BCHP_GENET_0_TDMA_REG_START                        0x00084000
+#define BCHP_GENET_0_TDMA_REG_END                          0x00084c88
+#define BCHP_GENET_1_SYS_REG_START                         0x00090000
+#define BCHP_GENET_1_SYS_REG_END                           0x0009000c
+#define BCHP_GENET_1_GR_BRIDGE_REG_START                   0x00090040
+#define BCHP_GENET_1_GR_BRIDGE_REG_END                     0x0009004c
+#define BCHP_GENET_1_EXT_REG_START                         0x00090080
+#define BCHP_GENET_1_EXT_REG_END                           0x00090098
+#define BCHP_GENET_1_INTRL2_0_REG_START                    0x00090200
+#define BCHP_GENET_1_INTRL2_0_REG_END                      0x0009022c
+#define BCHP_GENET_1_INTRL2_1_REG_START                    0x00090240
+#define BCHP_GENET_1_INTRL2_1_REG_END                      0x0009026c
+#define BCHP_GENET_1_RBUF_REG_START                        0x00090300
+#define BCHP_GENET_1_RBUF_REG_END                          0x000903ec
+#define BCHP_GENET_1_TBUF_REG_START                        0x00090600
+#define BCHP_GENET_1_TBUF_REG_END                          0x00090628
+#define BCHP_GENET_1_UMAC_REG_START                        0x00090800
+#define BCHP_GENET_1_UMAC_REG_END                          0x00090ed8
+#define BCHP_GENET_1_HFB_REG_START                         0x00091000
+#define BCHP_GENET_1_HFB_REG_END                           0x00092010
+#define BCHP_GENET_1_RDMA_REG_START                        0x00093000
+#define BCHP_GENET_1_RDMA_REG_END                          0x00093cb4
+#define BCHP_GENET_1_TDMA_REG_START                        0x00094000
+#define BCHP_GENET_1_TDMA_REG_END                          0x00094c88
+#define BCHP_XPT_SECURITY_REG_START                        0x000a0000
+#define BCHP_XPT_SECURITY_REG_END                          0x000afffc
+#define BCHP_MMSCRAM_REG_START                             0x000b0000
+#define BCHP_MMSCRAM_REG_END                               0x000b1ffc
+#define BCHP_MEM_DMA_SECURE_REG_START                      0x000b2000
+#define BCHP_MEM_DMA_SECURE_REG_END                        0x000b200c
+#define BCHP_SECTOP_GRB_REG_START                          0x000b4000
+#define BCHP_SECTOP_GRB_REG_END                            0x000b400c
+#define BCHP_JTAG_OTP_REG_START                            0x000b4100
+#define BCHP_JTAG_OTP_REG_END                              0x000b4138
+#define BCHP_MEM_DMA_0_REG_START                           0x000b4200
+#define BCHP_MEM_DMA_0_REG_END                             0x000b4224
+#define BCHP_XPT_SECURITY_NS_REG_START                     0x000b4300
+#define BCHP_XPT_SECURITY_NS_REG_END                       0x000b4310
+#define BCHP_SYS_GISB_ARB_SEC_REG_START                    0x000c0000
+#define BCHP_SYS_GISB_ARB_SEC_REG_END                      0x000c00b4
+#define BCHP_SYS_TOP_CTRL_SEC_REG_START                    0x000c0700
+#define BCHP_SYS_TOP_CTRL_SEC_REG_END                      0x000c0704
+#define BCHP_AON_CTRL_SECURE_REG_START                     0x000c0800
+#define BCHP_AON_CTRL_SECURE_REG_END                       0x000c087c
+#define BCHP_S_MEMC_0_REG_START                            0x000e0000
+#define BCHP_S_MEMC_0_REG_END                              0x000e0220
+#define BCHP_MFD_0_REG_START                               0x00100000
+#define BCHP_MFD_0_REG_END                                 0x00100264
+#define BCHP_MFD_1_REG_START                               0x00100400
+#define BCHP_MFD_1_REG_END                                 0x001005fc
+#define BCHP_VFD_0_REG_START                               0x00101000
+#define BCHP_VFD_0_REG_END                                 0x001011fc
+#define BCHP_VFD_1_REG_START                               0x00101200
+#define BCHP_VFD_1_REG_END                                 0x001013fc
+#define BCHP_VFD_2_REG_START                               0x00101400
+#define BCHP_VFD_2_REG_END                                 0x001015fc
+#define BCHP_VFD_3_REG_START                               0x00101600
+#define BCHP_VFD_3_REG_END                                 0x001017fc
+#define BCHP_RDC_REG_START                                 0x00102000
+#define BCHP_RDC_REG_END                                   0x001029fc
+#define BCHP_BVNF_INTR2_0_REG_START                        0x00103000
+#define BCHP_BVNF_INTR2_0_REG_END                          0x0010302c
+#define BCHP_BVNF_INTR2_1_REG_START                        0x00103100
+#define BCHP_BVNF_INTR2_1_REG_END                          0x0010312c
+#define BCHP_BVNF_INTR2_3_REG_START                        0x00103300
+#define BCHP_BVNF_INTR2_3_REG_END                          0x0010332c
+#define BCHP_BVNF_INTR2_4_REG_START                        0x00103400
+#define BCHP_BVNF_INTR2_4_REG_END                          0x0010342c
+#define BCHP_BVNF_INTR2_5_REG_START                        0x00103500
+#define BCHP_BVNF_INTR2_5_REG_END                          0x0010352c
+#define BCHP_FMISC_REG_START                               0x00104000
+#define BCHP_FMISC_REG_END                                 0x00104020
+#define BCHP_SCL_0_REG_START                               0x00120000
+#define BCHP_SCL_0_REG_END                                 0x001203fc
+#define BCHP_SCL_1_REG_START                               0x00120400
+#define BCHP_SCL_1_REG_END                                 0x001207fc
+#define BCHP_SCL_2_REG_START                               0x00120800
+#define BCHP_SCL_2_REG_END                                 0x00120bfc
+#define BCHP_SCL_3_REG_START                               0x00120c00
+#define BCHP_SCL_3_REG_END                                 0x00120ffc
+#define BCHP_VNET_F_REG_START                              0x00122000
+#define BCHP_VNET_F_REG_END                                0x001220ac
+#define BCHP_VNET_B_REG_START                              0x00122200
+#define BCHP_VNET_B_REG_END                                0x001222bc
+#define BCHP_MMISC_REG_START                               0x00122800
+#define BCHP_MMISC_REG_END                                 0x00122820
+#define BCHP_LBOX_0_REG_START                              0x00125000
+#define BCHP_LBOX_0_REG_END                                0x00125070
+#define BCHP_LBOX_1_REG_START                              0x00125200
+#define BCHP_LBOX_1_REG_END                                0x00125270
+#define BCHP_BVNM_INTR2_0_REG_START                        0x00126000
+#define BCHP_BVNM_INTR2_0_REG_END                          0x0012602c
+#define BCHP_DNR_0_REG_START                               0x00127000
+#define BCHP_DNR_0_REG_END                                 0x001270a4
+#define BCHP_CAP_0_REG_START                               0x00140000
+#define BCHP_CAP_0_REG_END                                 0x0014007c
+#define BCHP_CAP_1_REG_START                               0x00140200
+#define BCHP_CAP_1_REG_END                                 0x0014027c
+#define BCHP_CAP_2_REG_START                               0x00140400
+#define BCHP_CAP_2_REG_END                                 0x0014047c
+#define BCHP_CAP_3_REG_START                               0x00140600
+#define BCHP_CAP_3_REG_END                                 0x0014067c
+#define BCHP_GFD_0_REG_START                               0x00141000
+#define BCHP_GFD_0_REG_END                                 0x00141228
+#define BCHP_GFD_1_REG_START                               0x00141400
+#define BCHP_GFD_1_REG_END                                 0x00141554
+#define BCHP_CMP_0_REG_START                               0x00142000
+#define BCHP_CMP_0_REG_END                                 0x001424b4
+#define BCHP_CMP_1_REG_START                               0x00142800
+#define BCHP_CMP_1_REG_END                                 0x00142cb4
+#define BCHP_TNT_CMP_0_V0_REG_START                        0x00143000
+#define BCHP_TNT_CMP_0_V0_REG_END                          0x001430a4
+#define BCHP_MASK_0_REG_START                              0x00143400
+#define BCHP_MASK_0_REG_END                                0x00143420
+#define BCHP_PEP_CMP_0_V0_REG_START                        0x00144000
+#define BCHP_PEP_CMP_0_V0_REG_END                          0x00145484
+#define BCHP_BVNB_INTR2_REG_START                          0x00146000
+#define BCHP_BVNB_INTR2_REG_END                            0x0014602c
+#define BCHP_BMISC_REG_START                               0x00146400
+#define BCHP_BMISC_REG_END                                 0x0014641c
+#define BCHP_MVP_TOP_0_REG_START                           0x00160000
+#define BCHP_MVP_TOP_0_REG_END                             0x0016002c
+#define BCHP_SIOB_0_REG_START                              0x00160200
+#define BCHP_SIOB_0_REG_END                                0x001602fc
+#define BCHP_HSCL_0_REG_START                              0x00160400
+#define BCHP_HSCL_0_REG_END                                0x001607fc
+#define BCHP_MDI_TOP_0_REG_START                           0x00162000
+#define BCHP_MDI_TOP_0_REG_END                             0x00162044
+#define BCHP_MDI_PPB_0_REG_START                           0x00162800
+#define BCHP_MDI_PPB_0_REG_END                             0x00162bfc
+#define BCHP_MDI_FCN_0_REG_START                           0x00162c00
+#define BCHP_MDI_FCN_0_REG_END                             0x00162ffc
+#define BCHP_MISC_REG_START                                0x00180000
+#define BCHP_MISC_REG_END                                  0x0018009c
+#define BCHP_IT_0_REG_START                                0x00181000
+#define BCHP_IT_0_REG_END                                  0x001817fc
+#define BCHP_IT_1_REG_START                                0x00182000
+#define BCHP_IT_1_REG_END                                  0x001827fc
+#define BCHP_VF_0_REG_START                                0x00183000
+#define BCHP_VF_0_REG_END                                  0x00183134
+#define BCHP_VF_1_REG_START                                0x00183200
+#define BCHP_VF_1_REG_END                                  0x00183334
+#define BCHP_SECAM_0_REG_START                             0x00183400
+#define BCHP_SECAM_0_REG_END                               0x00183414
+#define BCHP_SM_0_REG_START                                0x00183480
+#define BCHP_SM_0_REG_END                                  0x001834ac
+#define BCHP_SDSRC_0_REG_START                             0x00183500
+#define BCHP_SDSRC_0_REG_END                               0x0018350c
+#define BCHP_HDSRC_0_REG_START                             0x00183520
+#define BCHP_HDSRC_0_REG_END                               0x0018353c
+#define BCHP_CSC_0_REG_START                               0x00183580
+#define BCHP_CSC_0_REG_END                                 0x001835b0
+#define BCHP_CSC_1_REG_START                               0x00183600
+#define BCHP_CSC_1_REG_END                                 0x00183630
+#define BCHP_RM_0_REG_START                                0x00183680
+#define BCHP_RM_0_REG_END                                  0x001836a4
+#define BCHP_RM_1_REG_START                                0x001836c0
+#define BCHP_RM_1_REG_END                                  0x001836e4
+#define BCHP_ANA_DEBUG_0_REG_START                         0x00183700
+#define BCHP_ANA_DEBUG_0_REG_END                           0x00183744
+#define BCHP_GRPD_0_REG_START                              0x00183800
+#define BCHP_GRPD_0_REG_END                                0x001838ec
+#define BCHP_DTRAM_0_REG_START                             0x00184000
+#define BCHP_DTRAM_0_REG_END                               0x0018447c
+#define BCHP_DVI_DTG_0_REG_START                           0x00184800
+#define BCHP_DVI_DTG_0_REG_END                             0x00184954
+#define BCHP_DVI_CSC_0_REG_START                           0x00184a00
+#define BCHP_DVI_CSC_0_REG_END                             0x00184a30
+#define BCHP_DVI_DVF_0_REG_START                           0x00184b00
+#define BCHP_DVI_DVF_0_REG_END                             0x00184b14
+#define BCHP_DVI_DEBUG_0_REG_START                         0x00184c00
+#define BCHP_DVI_DEBUG_0_REG_END                           0x00184c44
+#define BCHP_ITU656_DTG_0_REG_START                        0x00185000
+#define BCHP_ITU656_DTG_0_REG_END                          0x00185154
+#define BCHP_ITU656_CSC_0_REG_START                        0x00185200
+#define BCHP_ITU656_CSC_0_REG_END                          0x00185230
+#define BCHP_ITU656_DVF_0_REG_START                        0x00185300
+#define BCHP_ITU656_DVF_0_REG_END                          0x00185314
+#define BCHP_ITU656_0_REG_START                            0x00185400
+#define BCHP_ITU656_0_REG_END                              0x00185420
+#define BCHP_VEC_CFG_REG_START                             0x00185600
+#define BCHP_VEC_CFG_REG_END                               0x00185708
+#define BCHP_VIDEO_ENC_INTR2_REG_START                     0x00185a00
+#define BCHP_VIDEO_ENC_INTR2_REG_END                       0x00185a2c
+#define BCHP_VIDEO_ENC_TPG_0_REG_START                     0x00185b00
+#define BCHP_VIDEO_ENC_TPG_0_REG_END                       0x00185b18
+#define BCHP_VIDEO_ENC_DECIM_0_REG_START                   0x00185c00
+#define BCHP_VIDEO_ENC_DECIM_0_REG_END                     0x00185c08
+#define BCHP_DVP_TVG_0_REG_START                           0x00185d00
+#define BCHP_DVP_TVG_0_REG_END                             0x00185d88
+#define BCHP_VBI_ENC_REG_START                             0x00186000
+#define BCHP_VBI_ENC_REG_END                               0x00186074
+#define BCHP_CCE_0_REG_START                               0x00186400
+#define BCHP_CCE_0_REG_END                                 0x00186458
+#define BCHP_CCE_1_REG_START                               0x00186500
+#define BCHP_CCE_1_REG_END                                 0x00186558
+#define BCHP_WSE_0_REG_START                               0x00186600
+#define BCHP_WSE_0_REG_END                                 0x00186614
+#define BCHP_WSE_1_REG_START                               0x00186700
+#define BCHP_WSE_1_REG_END                                 0x00186714
+#define BCHP_CGMSAE_0_REG_START                            0x00186800
+#define BCHP_CGMSAE_0_REG_END                              0x00186858
+#define BCHP_CGMSAE_1_REG_START                            0x00186900
+#define BCHP_CGMSAE_1_REG_END                              0x00186958
+#define BCHP_TTE_0_REG_START                               0x00186a00
+#define BCHP_TTE_0_REG_END                                 0x00186a28
+#define BCHP_TTE_1_REG_START                               0x00186b00
+#define BCHP_TTE_1_REG_END                                 0x00186b28
+#define BCHP_GSE_0_REG_START                               0x00186c00
+#define BCHP_GSE_0_REG_END                                 0x00186c80
+#define BCHP_GSE_1_REG_START                               0x00186d00
+#define BCHP_GSE_1_REG_END                                 0x00186d80
+#define BCHP_AMOLE_0_REG_START                             0x00186e00
+#define BCHP_AMOLE_0_REG_END                               0x00186e8c
+#define BCHP_AMOLE_1_REG_START                             0x00186f00
+#define BCHP_AMOLE_1_REG_END                               0x00186f8c
+#define BCHP_CCE_ANCIL_0_REG_START                         0x00187000
+#define BCHP_CCE_ANCIL_0_REG_END                           0x00187054
+#define BCHP_WSE_ANCIL_0_REG_START                         0x00187100
+#define BCHP_WSE_ANCIL_0_REG_END                           0x0018710c
+#define BCHP_TTE_ANCIL_0_REG_START                         0x00187200
+#define BCHP_TTE_ANCIL_0_REG_END                           0x00187228
+#define BCHP_GSE_ANCIL_0_REG_START                         0x00187300
+#define BCHP_GSE_ANCIL_0_REG_END                           0x00187380
+#define BCHP_AMOLE_ANCIL_0_REG_START                       0x00187400
+#define BCHP_AMOLE_ANCIL_0_REG_END                         0x0018748c
+#define BCHP_ANCI656_ANCIL_0_REG_START                     0x00187500
+#define BCHP_ANCI656_ANCIL_0_REG_END                       0x00187524
+#define BCHP_DVP_HT_REG_START                              0x001a0000
+#define BCHP_DVP_HT_REG_END                                0x001a00d4
+#define BCHP_HDMI_REG_START                                0x001a0800
+#define BCHP_HDMI_REG_END                                  0x001a0994
+#define BCHP_HDMI_TX_PHY_REG_START                         0x001a0a80
+#define BCHP_HDMI_TX_PHY_REG_END                           0x001a0ad8
+#define BCHP_HDMI_RM_REG_START                             0x001a0b00
+#define BCHP_HDMI_RM_REG_END                               0x001a0b2c
+#define BCHP_HDMI_TX_INTR2_REG_START                       0x001a0b40
+#define BCHP_HDMI_TX_INTR2_REG_END                         0x001a0b6c
+#define BCHP_HDMI_RAM_REG_START                            0x001a0c00
+#define BCHP_HDMI_RAM_REG_END                              0x001a0dfc
+#define BCHP_BVN_RGR_REG_START                             0x001a8000
+#define BCHP_BVN_RGR_REG_END                               0x001a8010
+#define BCHP_DATA_MEM_REG_START                            0x00200000
+#define BCHP_DATA_MEM_REG_END                              0x0023fffc
+#define BCHP_CNTL_MEM_REG_START                            0x00240000
+#define BCHP_CNTL_MEM_REG_END                              0x0025fffc
+#define BCHP_MOCA_DMA_Channel0_REG_START                   0x00280000
+#define BCHP_MOCA_DMA_Channel0_REG_END                     0x0028000c
+#define BCHP_MOCA_DMA_Channel1_REG_START                   0x00280010
+#define BCHP_MOCA_DMA_Channel1_REG_END                     0x0028001c
+#define BCHP_MOCA_DMA_Channel2_REG_START                   0x00280020
+#define BCHP_MOCA_DMA_Channel2_REG_END                     0x0028002c
+#define BCHP_MOCA_DMA_Channel3_REG_START                   0x00280030
+#define BCHP_MOCA_DMA_Channel3_REG_END                     0x0028003c
+#define BCHP_MOCA_DMA_Channel4_REG_START                   0x00280040
+#define BCHP_MOCA_DMA_Channel4_REG_END                     0x0028004c
+#define BCHP_MOCA_DMA_Channel5_REG_START                   0x00280050
+#define BCHP_MOCA_DMA_Channel5_REG_END                     0x0028005c
+#define BCHP_MOCA_DMA_Channel6_REG_START                   0x00280060
+#define BCHP_MOCA_DMA_Channel6_REG_END                     0x0028006c
+#define BCHP_MOCA_MAC_REG_START                            0x00280400
+#define BCHP_MOCA_MAC_REG_END                              0x00280480
+#define BCHP_MOCA_PHY_REG_START                            0x00288000
+#define BCHP_MOCA_PHY_REG_END                              0x0028a9fc
+#define BCHP_MOCA_TRX_REG_START                            0x0028c000
+#define BCHP_MOCA_TRX_REG_END                              0x0028c0d0
+#define BCHP_MOCA_GMII_REG_START                           0x00290000
+#define BCHP_MOCA_GMII_REG_END                             0x00290058
+#define BCHP_MOCA_DMA_Channel_rx_REG_START                 0x00290400
+#define BCHP_MOCA_DMA_Channel_rx_REG_END                   0x0029040c
+#define BCHP_MOCA_DMA_Channel_tx_REG_START                 0x00290410
+#define BCHP_MOCA_DMA_Channel_tx_REG_END                   0x0029041c
+#define BCHP_MOCA_ECL_REG_START                            0x00290800
+#define BCHP_MOCA_ECL_REG_END                              0x00290848
+#define BCHP_MOCA_PRI_REG_START                            0x00292000
+#define BCHP_MOCA_PRI_REG_END                              0x0029207c
+#define BCHP_MOCA_NID_REG_START                            0x00294000
+#define BCHP_MOCA_NID_REG_END                              0x002943fc
+#define BCHP_MOCA_TIMER_0_REG_START                        0x002a0000
+#define BCHP_MOCA_TIMER_0_REG_END                          0x002a0010
+#define BCHP_MOCA_TIMER_1_REG_START                        0x002a0020
+#define BCHP_MOCA_TIMER_1_REG_END                          0x002a0030
+#define BCHP_MOCA_TIMER_2_REG_START                        0x002a0040
+#define BCHP_MOCA_TIMER_2_REG_END                          0x002a0050
+#define BCHP_MOCA_GPIO_REG_START                           0x002a1000
+#define BCHP_MOCA_GPIO_REG_END                             0x002a1018
+#define BCHP_MOCA_EXTRAS_REG_START                         0x002a1400
+#define BCHP_MOCA_EXTRAS_REG_END                           0x002a1494
+#define BCHP_MOCA_HOSTM2M_REG_START                        0x002a2000
+#define BCHP_MOCA_HOSTM2M_REG_END                          0x002a200c
+#define BCHP_MOCA_HOSTMISC_REG_START                       0x002a2040
+#define BCHP_MOCA_HOSTMISC_REG_END                         0x002a2064
+#define BCHP_MOCA_L2_REG_START                             0x002a2080
+#define BCHP_MOCA_L2_REG_END                               0x002a20ac
+#define BCHP_MOCA_GR_BRIDGE_REG_START                      0x002a20c0
+#define BCHP_MOCA_GR_BRIDGE_REG_END                        0x002a20cc
+#define BCHP_MOCA_HOSTMISC_MMP_REG_START                   0x002a2100
+#define BCHP_MOCA_HOSTMISC_MMP_REG_END                     0x002a212c
+#define BCHP_BSP_CMDBUF_REG_START                          0x00329800
+#define BCHP_BSP_CMDBUF_REG_END                            0x00329ffc
+#define BCHP_BSP_GLB_CONTROL_REG_START                     0x0032b000
+#define BCHP_BSP_GLB_CONTROL_REG_END                       0x0032b098
+#define BCHP_BSP_PKL_REG_START                             0x0032b300
+#define BCHP_BSP_PKL_REG_END                               0x0032b37c
+#define BCHP_BSP_INST_PATCH_CTRL_REG_START                 0x0032b400
+#define BCHP_BSP_INST_PATCH_CTRL_REG_END                   0x0032b404
+#define BCHP_BSP_CONTROL_INTR2_REG_START                   0x0032b800
+#define BCHP_BSP_CONTROL_INTR2_REG_END                     0x0032b82c
+#define BCHP_BSP_INST_PATCHRAM_REG_START                   0x0032c000
+#define BCHP_BSP_INST_PATCHRAM_REG_END                     0x0032fffc
+#define BCHP_XPT_BUS_IF_REG_START                          0x00380000
+#define BCHP_XPT_BUS_IF_REG_END                            0x00380088
+#define BCHP_XPT_XMEMIF_REG_START                          0x00381000
+#define BCHP_XPT_XMEMIF_REG_END                            0x0038109c
+#define BCHP_XPT_PMU_REG_START                             0x00381800
+#define BCHP_XPT_PMU_REG_END                               0x00381808
+#define BCHP_XPT_WAKEUP_REG_START                          0x00382000
+#define BCHP_XPT_WAKEUP_REG_END                            0x00382fbc
+#define BCHP_XPT_RMX0_IO_REG_START                         0x00383000
+#define BCHP_XPT_RMX0_IO_REG_END                           0x00383020
+#define BCHP_XPT_RMX1_IO_REG_START                         0x00383100
+#define BCHP_XPT_RMX1_IO_REG_END                           0x00383120
+#define BCHP_XPT_FE_REG_START                              0x00384000
+#define BCHP_XPT_FE_REG_END                                0x00384ffc
+#define BCHP_XPT_DPCR0_REG_START                           0x00386000
+#define BCHP_XPT_DPCR0_REG_END                             0x00386074
+#define BCHP_XPT_DPCR1_REG_START                           0x00386080
+#define BCHP_XPT_DPCR1_REG_END                             0x003860f4
+#define BCHP_XPT_DPCR2_REG_START                           0x00386100
+#define BCHP_XPT_DPCR2_REG_END                             0x00386174
+#define BCHP_XPT_DPCR3_REG_START                           0x00386180
+#define BCHP_XPT_DPCR3_REG_END                             0x003861f4
+#define BCHP_XPT_DPCR_PP_REG_START                         0x00386400
+#define BCHP_XPT_DPCR_PP_REG_END                           0x00386404
+#define BCHP_XPT_PSUB_REG_START                            0x00386600
+#define BCHP_XPT_PSUB_REG_END                              0x003866c8
+#define BCHP_XPT_RSBUFF_REG_START                          0x00386800
+#define BCHP_XPT_RSBUFF_REG_END                            0x00386f2c
+#define BCHP_XPT_PB0_REG_START                             0x00387000
+#define BCHP_XPT_PB0_REG_END                               0x00387060
+#define BCHP_XPT_PB1_REG_START                             0x00387080
+#define BCHP_XPT_PB1_REG_END                               0x003870e0
+#define BCHP_XPT_PB2_REG_START                             0x00387100
+#define BCHP_XPT_PB2_REG_END                               0x00387160
+#define BCHP_XPT_PB3_REG_START                             0x00387180
+#define BCHP_XPT_PB3_REG_END                               0x003871e0
+#define BCHP_XPT_MPOD_REG_START                            0x00388000
+#define BCHP_XPT_MPOD_REG_END                              0x00388020
+#define BCHP_XPT_RMX0_REG_START                            0x00388400
+#define BCHP_XPT_RMX0_REG_END                              0x00388408
+#define BCHP_XPT_RMX1_REG_START                            0x00388500
+#define BCHP_XPT_RMX1_REG_END                              0x00388508
+#define BCHP_XPT_XCBUFF_REG_START                          0x0038a000
+#define BCHP_XPT_XCBUFF_REG_END                            0x0038bcc8
+#define BCHP_XPT_RAVE_REG_START                            0x00390000
+#define BCHP_XPT_RAVE_REG_END                              0x0039a69c
+#define BCHP_XPT_PCROFFSET_REG_START                       0x0039b000
+#define BCHP_XPT_PCROFFSET_REG_END                         0x0039bffc
+#define BCHP_XPT_MSG_REG_START                             0x003a0000
+#define BCHP_XPT_MSG_REG_END                               0x003a4814
+#define BCHP_XPT_GR_REG_START                              0x003a5000
+#define BCHP_XPT_GR_REG_END                                0x003a500c
+#define BCHP_XPT_FULL_PID_PARSER_REG_START                 0x003a6000
+#define BCHP_XPT_FULL_PID_PARSER_REG_END                   0x003a7050
+#define BCHP_XPT_XPU_REG_START                             0x003a8000
+#define BCHP_XPT_XPU_REG_END                               0x003ac7fc
+#define BCHP_XPT_SECURE_BUS_IF_REG_START                   0x003b8000
+#define BCHP_XPT_SECURE_BUS_IF_REG_END                     0x003b8000
+#define BCHP_SUN_GISB_ARB_REG_START                        0x00400000
+#define BCHP_SUN_GISB_ARB_REG_END                          0x004000d8
+#define BCHP_SUN_RGR_REG_START                             0x00400400
+#define BCHP_SUN_RGR_REG_END                               0x00400410
+#define BCHP_SUN_RG_REG_START                              0x00400800
+#define BCHP_SUN_RG_REG_END                                0x0040080c
+#define BCHP_TPCAP_REG_START                               0x00400c00
+#define BCHP_TPCAP_REG_END                                 0x00400c84
+#define BCHP_SUN_L2_REG_START                              0x00403000
+#define BCHP_SUN_L2_REG_END                                0x0040302c
+#define BCHP_SM_L2_REG_START                               0x00403400
+#define BCHP_SM_L2_REG_END                                 0x0040342c
+#define BCHP_SM_REG_START                                  0x00403800
+#define BCHP_SM_REG_END                                    0x00403824
+#define BCHP_SM_FAST_REG_START                             0x00403c00
+#define BCHP_SM_FAST_REG_END                               0x00403c18
+#define BCHP_SUN_TOP_CTRL_REG_START                        0x00404000
+#define BCHP_SUN_TOP_CTRL_REG_END                          0x00404518
+#define BCHP_IRB_REG_START                                 0x00406000
+#define BCHP_IRB_REG_END                                   0x00406138
+#define BCHP_PM_REG_START                                  0x00406180
+#define BCHP_PM_REG_END                                    0x00406188
+#define BCHP_BSCA_REG_START                                0x00406200
+#define BCHP_BSCA_REG_END                                  0x00406254
+#define BCHP_BSCB_REG_START                                0x00406280
+#define BCHP_BSCB_REG_END                                  0x004062d4
+#define BCHP_BSCD_REG_START                                0x00406300
+#define BCHP_BSCD_REG_END                                  0x00406354
+#define BCHP_PWM_REG_START                                 0x00406580
+#define BCHP_PWM_REG_END                                   0x004065a4
+#define BCHP_PWMB_REG_START                                0x004066c0
+#define BCHP_PWMB_REG_END                                  0x004066e4
+#define BCHP_GIO_REG_START                                 0x00406700
+#define BCHP_GIO_REG_END                                   0x0040675c
+#define BCHP_IRQ0_REG_START                                0x00406780
+#define BCHP_IRQ0_REG_END                                  0x00406784
+#define BCHP_IRQ1_REG_START                                0x00406788
+#define BCHP_IRQ1_REG_END                                  0x0040678c
+#define BCHP_TIMER_REG_START                               0x004067c0
+#define BCHP_TIMER_REG_END                                 0x004067fc
+#define BCHP_UARTA_REG_START                               0x00406900
+#define BCHP_UARTA_REG_END                                 0x0040691c
+#define BCHP_UARTB_REG_START                               0x00406940
+#define BCHP_UARTB_REG_END                                 0x0040695c
+#define BCHP_UARTC_REG_START                               0x00406980
+#define BCHP_UARTC_REG_END                                 0x0040699c
+#define BCHP_SCA_REG_START                                 0x00406a00
+#define BCHP_SCA_REG_END                                   0x00406abc
+#define BCHP_SCB_REG_START                                 0x00406ac0
+#define BCHP_SCB_REG_END                                   0x00406b7c
+#define BCHP_SCIRQ0_REG_START                              0x00406c40
+#define BCHP_SCIRQ0_REG_END                                0x00406c44
+#define BCHP_SCIRQ1_REG_START                              0x00406c48
+#define BCHP_SCIRQ1_REG_END                                0x00406c4c
+#define BCHP_MCIF_REG_START                                0x00406e00
+#define BCHP_MCIF_REG_END                                  0x00406e20
+#define BCHP_MCIF_INTR2_REG_START                          0x00406e40
+#define BCHP_MCIF_INTR2_REG_END                            0x00406e6c
+#define BCHP_UPG_AUX_INTR2_REG_START                       0x00406e80
+#define BCHP_UPG_AUX_INTR2_REG_END                         0x00406eac
+#define BCHP_TMON_REG_START                                0x00406f00
+#define BCHP_TMON_REG_END                                  0x00406f50
+#define BCHP_AON_CTRL_REG_START                            0x00408000
+#define BCHP_AON_CTRL_REG_END                              0x004083fc
+#define BCHP_AON_L2_REG_START                              0x00408400
+#define BCHP_AON_L2_REG_END                                0x0040842c
+#define BCHP_AON_PM_L2_REG_START                           0x00408440
+#define BCHP_AON_PM_L2_REG_END                             0x0040846c
+#define BCHP_AON_PIN_CTRL_REG_START                        0x00408500
+#define BCHP_AON_PIN_CTRL_REG_END                          0x0040851c
+#define BCHP_AON_HDMI_TX_REG_START                         0x00408600
+#define BCHP_AON_HDMI_TX_REG_END                           0x00408698
+#define BCHP_LDK_REG_START                                 0x00408800
+#define BCHP_LDK_REG_END                                   0x0040883c
+#define BCHP_PM_AON_REG_START                              0x00408840
+#define BCHP_PM_AON_REG_END                                0x00408848
+#define BCHP_ICAP_REG_START                                0x00408880
+#define BCHP_ICAP_REG_END                                  0x004088bc
+#define BCHP_KBD1_REG_START                                0x004088c0
+#define BCHP_KBD1_REG_END                                  0x004088fc
+#define BCHP_KBD2_REG_START                                0x00408900
+#define BCHP_KBD2_REG_END                                  0x0040893c
+#define BCHP_KBD3_REG_START                                0x00408940
+#define BCHP_KBD3_REG_END                                  0x0040897c
+#define BCHP_BSCC_REG_START                                0x00408980
+#define BCHP_BSCC_REG_END                                  0x004089d4
+#define BCHP_MSPI_REG_START                                0x00408a00
+#define BCHP_MSPI_REG_END                                  0x00408b7c
+#define BCHP_IRQ0_AON_REG_START                            0x00408b80
+#define BCHP_IRQ0_AON_REG_END                              0x00408b84
+#define BCHP_IRQ1_AON_REG_START                            0x00408b88
+#define BCHP_IRQ1_AON_REG_END                              0x00408b8c
+#define BCHP_GIO_AON_REG_START                             0x00408c00
+#define BCHP_GIO_AON_REG_END                               0x00408c3c
+#define BCHP_BICAP_REG_START                               0x00408e00
+#define BCHP_BICAP_REG_END                                 0x00408e38
+#define BCHP_UPG_AUX_AON_INTR2_REG_START                   0x00408e40
+#define BCHP_UPG_AUX_AON_INTR2_REG_END                     0x00408e6c
+#define BCHP_WKTMR_REG_START                               0x00408e80
+#define BCHP_WKTMR_REG_END                                 0x00408e90
+#define BCHP_USB_CAPS_REG_START                            0x00480000
+#define BCHP_USB_CAPS_REG_END                              0x0048002c
+#define BCHP_USB_GR_BRIDGE_REG_START                       0x00480100
+#define BCHP_USB_GR_BRIDGE_REG_END                         0x0048010c
+#define BCHP_USB_INTR2_REG_START                           0x00480180
+#define BCHP_USB_INTR2_REG_END                             0x004801ac
+#define BCHP_USB_CTRL_REG_START                            0x00480200
+#define BCHP_USB_CTRL_REG_END                              0x00480238
+#define BCHP_USB_EHCI_REG_START                            0x00480300
+#define BCHP_USB_EHCI_REG_END                              0x004803a4
+#define BCHP_USB_OHCI_REG_START                            0x00480400
+#define BCHP_USB_OHCI_REG_END                              0x00480454
+#define BCHP_USB_EHCI1_REG_START                           0x00480500
+#define BCHP_USB_EHCI1_REG_END                             0x004805a4
+#define BCHP_USB_OHCI1_REG_START                           0x00480600
+#define BCHP_USB_OHCI1_REG_END                             0x00480654
+#define BCHP_USB1_CAPS_REG_START                           0x00490000
+#define BCHP_USB1_CAPS_REG_END                             0x0049002c
+#define BCHP_USB1_GR_BRIDGE_REG_START                      0x00490100
+#define BCHP_USB1_GR_BRIDGE_REG_END                        0x0049010c
+#define BCHP_USB1_INTR2_REG_START                          0x00490180
+#define BCHP_USB1_INTR2_REG_END                            0x004901ac
+#define BCHP_USB1_CTRL_REG_START                           0x00490200
+#define BCHP_USB1_CTRL_REG_END                             0x00490238
+#define BCHP_USB1_EHCI_REG_START                           0x00490300
+#define BCHP_USB1_EHCI_REG_END                             0x004903a4
+#define BCHP_USB1_OHCI_REG_START                           0x00490400
+#define BCHP_USB1_OHCI_REG_END                             0x00490454
+#define BCHP_USB1_EHCI1_REG_START                          0x00490500
+#define BCHP_USB1_EHCI1_REG_END                            0x004905a4
+#define BCHP_USB1_OHCI1_REG_START                          0x00490600
+#define BCHP_USB1_OHCI1_REG_END                            0x00490654
+#define BCHP_BOOTROM_REG_START                             0x00500000
+#define BCHP_BOOTROM_REG_END                               0x00500ffc
+#define BCHP_DECODE_RBNODE_REGS_0_REG_START                0x00800000
+#define BCHP_DECODE_RBNODE_REGS_0_REG_END                  0x0080007c
+#define BCHP_DECODE_MAIN_0_REG_START                       0x00800100
+#define BCHP_DECODE_MAIN_0_REG_END                         0x008001fc
+#define BCHP_SDRAM_DEBUG_0_REG_START                       0x00800200
+#define BCHP_SDRAM_DEBUG_0_REG_END                         0x0080027c
+#define BCHP_DECODE_MCOM_0_REG_START                       0x00800300
+#define BCHP_DECODE_MCOM_0_REG_END                         0x0080031c
+#define BCHP_DECODE_SPRE_0_REG_START                       0x00800320
+#define BCHP_DECODE_SPRE_0_REG_END                         0x0080033c
+#define BCHP_DECODE_WPRD_0_REG_START                       0x00800340
+#define BCHP_DECODE_WPRD_0_REG_END                         0x0080035c
+#define BCHP_DECODE_DQNT_0_REG_START                       0x00800400
+#define BCHP_DECODE_DQNT_0_REG_END                         0x0080045c
+#define BCHP_DECODE_DQNT_8X8_0_REG_START                   0x00800500
+#define BCHP_DECODE_DQNT_8X8_0_REG_END                     0x0080057c
+#define BCHP_DECODE_VP8_XFRM_0_REG_START                   0x00800600
+#define BCHP_DECODE_VP8_XFRM_0_REG_END                     0x0080060c
+#define BCHP_DECODE_XFRM_0_REG_START                       0x00800700
+#define BCHP_DECODE_XFRM_0_REG_END                         0x0080071c
+#define BCHP_DECODE_DBLK_0_REG_START                       0x00800720
+#define BCHP_DECODE_DBLK_0_REG_END                         0x0080073c
+#define BCHP_DECODE_MB_0_REG_START                         0x00800740
+#define BCHP_DECODE_MB_0_REG_END                           0x0080075c
+#define BCHP_REG_CABAC2BINS_0_REG_START                    0x00800b00
+#define BCHP_REG_CABAC2BINS_0_REG_END                      0x00800bfc
+#define BCHP_DECODE_SINT_0_REG_START                       0x00800c00
+#define BCHP_DECODE_SINT_0_REG_END                         0x00800dfc
+#define BCHP_DECODE_RVC_0_REG_START                        0x00800e00
+#define BCHP_DECODE_RVC_0_REG_END                          0x00800efc
+#define BCHP_DECODE_CPUREGS_0_REG_START                    0x00800f00
+#define BCHP_DECODE_CPUREGS_0_REG_END                      0x00800f7c
+#define BCHP_DECODE_CPUREGS2_0_REG_START                   0x00800f80
+#define BCHP_DECODE_CPUREGS2_0_REG_END                     0x00800ffc
+#define BCHP_DECODE_CPUDMA_0_REG_START                     0x00801800
+#define BCHP_DECODE_CPUDMA_0_REG_END                       0x008018fc
+#define BCHP_DECODE_DMAMEM_0_REG_START                     0x00801a00
+#define BCHP_DECODE_DMAMEM_0_REG_END                       0x008021fc
+#define BCHP_REG_CABAC2BINS2_0_REG_START                   0x00802400
+#define BCHP_REG_CABAC2BINS2_0_REG_END                     0x008027fc
+#define BCHP_DECODE_WPTBL_0_REG_START                      0x00803000
+#define BCHP_DECODE_WPTBL_0_REG_END                        0x008031fc
+#define BCHP_DECODE_SINT_OLOOP_0_REG_START                 0x0080cc00
+#define BCHP_DECODE_SINT_OLOOP_0_REG_END                   0x0080ccfc
+#define BCHP_DECODE_SD_0_REG_START                         0x00840800
+#define BCHP_DECODE_SD_0_REG_END                           0x00840ffc
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_START             0x00841000
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_END               0x0084107c
+#define BCHP_DECODE_CPUCORE_0_REG_START                    0x00844000
+#define BCHP_DECODE_CPUCORE_0_REG_END                      0x00844ffc
+#define BCHP_DECODE_CPUAUX_0_REG_START                     0x00845000
+#define BCHP_DECODE_CPUAUX_0_REG_END                       0x00845ffc
+#define BCHP_DECODE_CPUIMEM_0_REG_START                    0x00846000
+#define BCHP_DECODE_CPUIMEM_0_REG_END                      0x00847ffc
+#define BCHP_DECODE_CPUDMEM_0_REG_START                    0x00848000
+#define BCHP_DECODE_CPUDMEM_0_REG_END                      0x0084fffc
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_START            0x00851000
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_END              0x0085107c
+#define BCHP_DECODE_CPUDMA2_0_REG_START                    0x00851800
+#define BCHP_DECODE_CPUDMA2_0_REG_END                      0x008518fc
+#define BCHP_DECODE_DMAMEM2_0_REG_START                    0x00851a00
+#define BCHP_DECODE_DMAMEM2_0_REG_END                      0x008521fc
+#define BCHP_DECODE_CPUCORE2_0_REG_START                   0x00854000
+#define BCHP_DECODE_CPUCORE2_0_REG_END                     0x00854ffc
+#define BCHP_DECODE_CPUAUX2_0_REG_START                    0x00855000
+#define BCHP_DECODE_CPUAUX2_0_REG_END                      0x00855ffc
+#define BCHP_DECODE_CPUIMEM2_0_REG_START                   0x00856000
+#define BCHP_DECODE_CPUIMEM2_0_REG_END                     0x00857ffc
+#define BCHP_DECODE_CPUDMEM2_0_REG_START                   0x00858000
+#define BCHP_DECODE_CPUDMEM2_0_REG_END                     0x0085fffc
+#define BCHP_DECODE_IP_SHIM_0_REG_START                    0x00860000
+#define BCHP_DECODE_IP_SHIM_0_REG_END                      0x00860084
+#define BCHP_AVD_CACHE_0_REG_START                         0x00862000
+#define BCHP_AVD_CACHE_0_REG_END                           0x0086203c
+#define BCHP_ILS_REGS_0_REG_START                          0x00870000
+#define BCHP_ILS_REGS_0_REG_END                            0x0087007c
+#define BCHP_ILS_SCALE_ADDR_0_REG_START                    0x00870100
+#define BCHP_ILS_SCALE_ADDR_0_REG_END                      0x0087010c
+#define BCHP_ILS_SPSCALE_FILL_0_REG_START                  0x00870180
+#define BCHP_ILS_SPSCALE_FILL_0_REG_END                    0x00870180
+#define BCHP_ILS_MVSCALE_0_REG_START                       0x00870200
+#define BCHP_ILS_MVSCALE_0_REG_END                         0x0087038c
+#define BCHP_SVD_INTR2_0_REG_START                         0x00880000
+#define BCHP_SVD_INTR2_0_REG_END                           0x0088002c
+#define BCHP_SVD_RGR_0_REG_START                           0x00880400
+#define BCHP_SVD_RGR_0_REG_END                             0x00880410
+#define BCHP_BLD_DECODE_RBNODE_REGS_0_REG_START            0x00900000
+#define BCHP_BLD_DECODE_RBNODE_REGS_0_REG_END              0x0090007c
+#define BCHP_BLD_DECODE_MAIN_0_REG_START                   0x00900100
+#define BCHP_BLD_DECODE_MAIN_0_REG_END                     0x009001fc
+#define BCHP_BLD_SDRAM_DEBUG_0_REG_START                   0x00900200
+#define BCHP_BLD_SDRAM_DEBUG_0_REG_END                     0x0090027c
+#define BCHP_BLD_DECODE_MCOM_0_REG_START                   0x00900300
+#define BCHP_BLD_DECODE_MCOM_0_REG_END                     0x0090031c
+#define BCHP_BLD_DECODE_SPRE_0_REG_START                   0x00900320
+#define BCHP_BLD_DECODE_SPRE_0_REG_END                     0x0090033c
+#define BCHP_BLD_DECODE_WPRD_0_REG_START                   0x00900340
+#define BCHP_BLD_DECODE_WPRD_0_REG_END                     0x0090035c
+#define BCHP_BLD_DECODE_DQNT_0_REG_START                   0x00900400
+#define BCHP_BLD_DECODE_DQNT_0_REG_END                     0x0090045c
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_START               0x00900500
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_END                 0x0090057c
+#define BCHP_BLD_DECODE_VP8_XFRM_0_REG_START               0x00900600
+#define BCHP_BLD_DECODE_VP8_XFRM_0_REG_END                 0x0090060c
+#define BCHP_BLD_DECODE_XFRM_0_REG_START                   0x00900700
+#define BCHP_BLD_DECODE_XFRM_0_REG_END                     0x0090071c
+#define BCHP_BLD_DECODE_DBLK_0_REG_START                   0x00900720
+#define BCHP_BLD_DECODE_DBLK_0_REG_END                     0x0090073c
+#define BCHP_BLD_DECODE_MB_0_REG_START                     0x00900740
+#define BCHP_BLD_DECODE_MB_0_REG_END                       0x0090075c
+#define BCHP_BLD_REG_CABAC2BINS_0_REG_START                0x00900b00
+#define BCHP_BLD_REG_CABAC2BINS_0_REG_END                  0x00900bfc
+#define BCHP_BLD_DECODE_SINT_0_REG_START                   0x00900c00
+#define BCHP_BLD_DECODE_SINT_0_REG_END                     0x00900dfc
+#define BCHP_BLD_DECODE_RVC_0_REG_START                    0x00900e00
+#define BCHP_BLD_DECODE_RVC_0_REG_END                      0x00900efc
+#define BCHP_BLD_DECODE_CPUREGS_0_REG_START                0x00900f00
+#define BCHP_BLD_DECODE_CPUREGS_0_REG_END                  0x00900f7c
+#define BCHP_BLD_DECODE_CPUREGS2_0_REG_START               0x00900f80
+#define BCHP_BLD_DECODE_CPUREGS2_0_REG_END                 0x00900ffc
+#define BCHP_BLD_DECODE_CPUDMA_0_REG_START                 0x00901800
+#define BCHP_BLD_DECODE_CPUDMA_0_REG_END                   0x009018fc
+#define BCHP_BLD_DECODE_DMAMEM_0_REG_START                 0x00901a00
+#define BCHP_BLD_DECODE_DMAMEM_0_REG_END                   0x009021fc
+#define BCHP_BLD_REG_CABAC2BINS2_0_REG_START               0x00902400
+#define BCHP_BLD_REG_CABAC2BINS2_0_REG_END                 0x009027fc
+#define BCHP_BLD_DECODE_WPTBL_0_REG_START                  0x00903000
+#define BCHP_BLD_DECODE_WPTBL_0_REG_END                    0x009031fc
+#define BCHP_BLD_DECODE_SINT_OLOOP_0_REG_START             0x0090cc00
+#define BCHP_BLD_DECODE_SINT_OLOOP_0_REG_END               0x0090ccfc
+#define BCHP_BLD_DECODE_SD_0_REG_START                     0x00940800
+#define BCHP_BLD_DECODE_SD_0_REG_END                       0x00940ffc
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS_0_REG_START         0x00941000
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS_0_REG_END           0x0094107c
+#define BCHP_BLD_DECODE_CPUCORE_0_REG_START                0x00944000
+#define BCHP_BLD_DECODE_CPUCORE_0_REG_END                  0x00944ffc
+#define BCHP_BLD_DECODE_CPUAUX_0_REG_START                 0x00945000
+#define BCHP_BLD_DECODE_CPUAUX_0_REG_END                   0x00945ffc
+#define BCHP_BLD_DECODE_CPUIMEM_0_REG_START                0x00946000
+#define BCHP_BLD_DECODE_CPUIMEM_0_REG_END                  0x00947ffc
+#define BCHP_BLD_DECODE_CPUDMEM_0_REG_START                0x00948000
+#define BCHP_BLD_DECODE_CPUDMEM_0_REG_END                  0x0094fffc
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS2_0_REG_START        0x00951000
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS2_0_REG_END          0x0095107c
+#define BCHP_BLD_DECODE_CPUDMA2_0_REG_START                0x00951800
+#define BCHP_BLD_DECODE_CPUDMA2_0_REG_END                  0x009518fc
+#define BCHP_BLD_DECODE_DMAMEM2_0_REG_START                0x00951a00
+#define BCHP_BLD_DECODE_DMAMEM2_0_REG_END                  0x009521fc
+#define BCHP_BLD_DECODE_CPUCORE2_0_REG_START               0x00954000
+#define BCHP_BLD_DECODE_CPUCORE2_0_REG_END                 0x00954ffc
+#define BCHP_BLD_DECODE_CPUAUX2_0_REG_START                0x00955000
+#define BCHP_BLD_DECODE_CPUAUX2_0_REG_END                  0x00955ffc
+#define BCHP_BLD_DECODE_CPUIMEM2_0_REG_START               0x00956000
+#define BCHP_BLD_DECODE_CPUIMEM2_0_REG_END                 0x00957ffc
+#define BCHP_BLD_DECODE_CPUDMEM2_0_REG_START               0x00958000
+#define BCHP_BLD_DECODE_CPUDMEM2_0_REG_END                 0x0095fffc
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_START                0x00960000
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_END                  0x00960084
+#define BCHP_BLD_AVD_CACHE_0_REG_START                     0x00962000
+#define BCHP_BLD_AVD_CACHE_0_REG_END                       0x0096203c
+#define BCHP_MEMC_GEN_0_REG_START                          0x00a00000
+#define BCHP_MEMC_GEN_0_REG_END                            0x00a004f4
+#define BCHP_MEMC_ARB_0_REG_START                          0x00a01000
+#define BCHP_MEMC_ARB_0_REG_END                            0x00a01244
+#define BCHP_MEMC_DDR_0_REG_START                          0x00a02000
+#define BCHP_MEMC_DDR_0_REG_END                            0x00a022fc
+#define BCHP_MEMC_L2_0_REG_START                           0x00a03000
+#define BCHP_MEMC_L2_0_REG_END                             0x00a0302c
+#define BCHP_MEMC_L2_1_0_REG_START                         0x00a03800
+#define BCHP_MEMC_L2_1_0_REG_END                           0x00a0382c
+#define BCHP_MEMC_RGRB_0_REG_START                         0x00a04000
+#define BCHP_MEMC_RGRB_0_REG_END                           0x00a04010
+#define BCHP_MEMC_MISC_0_REG_START                         0x00a05000
+#define BCHP_MEMC_MISC_0_REG_END                           0x00a05010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_START            0x00a06000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_END              0x00a060c4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_START             0x00a06200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_END               0x00a063b0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_REG_START             0x00a06400
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_REG_END               0x00a065b0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_START         0x00a08000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_END           0x00a08138
+#define BCHP_VICH_0_REG_START                              0x00b00000
+#define BCHP_VICH_0_REG_END                                0x00b0008b
+#define BCHP_SID_REG_START                                 0x00c00100
+#define BCHP_SID_REG_END                                   0x00c0019c
+#define BCHP_SID_RLE_REG_START                             0x00c00300
+#define BCHP_SID_RLE_REG_END                               0x00c0039c
+#define BCHP_SID_DQ_REG_START                              0x00c00400
+#define BCHP_SID_DQ_REG_END                                0x00c004bc
+#define BCHP_SID_STRM_REG_START                            0x00c00800
+#define BCHP_SID_STRM_REG_END                              0x00c0087c
+#define BCHP_SID_OUTPUT_REG_START                          0x00c00c00
+#define BCHP_SID_OUTPUT_REG_END                            0x00c00c40
+#define BCHP_SID_ARC_REG_START                             0x00c00f00
+#define BCHP_SID_ARC_REG_END                               0x00c00f3c
+#define BCHP_SID_ARCDMA_REG_START                          0x00c01800
+#define BCHP_SID_ARCDMA_REG_END                            0x00c01840
+#define BCHP_SID_DMARAM_REG_START                          0x00c01a00
+#define BCHP_SID_DMARAM_REG_END                            0x00c01bfc
+#define BCHP_SID_PEEK_BITS_REG_START                       0x00c02b00
+#define BCHP_SID_PEEK_BITS_REG_END                         0x00c02b3c
+#define BCHP_SID_EXTRACT_BITS_REG_START                    0x00c02b40
+#define BCHP_SID_EXTRACT_BITS_REG_END                      0x00c02b7c
+#define BCHP_SID_HUFF_SYMB_REG_START                       0x00c03000
+#define BCHP_SID_HUFF_SYMB_REG_END                         0x00c037fc
+#define BCHP_SID_HUFF_CODE_REG_START                       0x00c03900
+#define BCHP_SID_HUFF_CODE_REG_END                         0x00c039fc
+#define BCHP_SID_SYMB_REG_START                            0x00c03a00
+#define BCHP_SID_SYMB_REG_END                              0x00c03a10
+#define BCHP_SID_SYMB_JPEG_REG_START                       0x00c03a80
+#define BCHP_SID_SYMB_JPEG_REG_END                         0x00c03a8c
+#define BCHP_SID_BIGRAM_REG_START                          0x00c08000
+#define BCHP_SID_BIGRAM_REG_END                            0x00c0fffc
+#define BCHP_SID_ARC_DBG_REG_START                         0x00c11000
+#define BCHP_SID_ARC_DBG_REG_END                           0x00c11010
+#define BCHP_SID_ARC_CORE_REG_START                        0x00c15000
+#define BCHP_SID_ARC_CORE_REG_END                          0x00c15014
+#define BCHP_M2MC_REG_START                                0x00c20000
+#define BCHP_M2MC_REG_END                                  0x00c207fc
+#define BCHP_V3D_CTL_REG_START                             0x00c21000
+#define BCHP_V3D_CTL_REG_END                               0x00c21040
+#define BCHP_V3D_CLE_REG_START                             0x00c21100
+#define BCHP_V3D_CLE_REG_END                               0x00c21138
+#define BCHP_V3D_PTB_REG_START                             0x00c21300
+#define BCHP_V3D_PTB_REG_END                               0x00c21310
+#define BCHP_V3D_QPS_REG_START                             0x00c21400
+#define BCHP_V3D_QPS_REG_END                               0x00c2143c
+#define BCHP_V3D_VPM_REG_START                             0x00c21500
+#define BCHP_V3D_VPM_REG_END                               0x00c21504
+#define BCHP_V3D_PCTR_REG_START                            0x00c21600
+#define BCHP_V3D_PCTR_REG_END                              0x00c216fc
+#define BCHP_V3D_GCA_REG_START                             0x00c21a00
+#define BCHP_V3D_GCA_REG_END                               0x00c21a54
+#define BCHP_V3D_DBG_REG_START                             0x00c21e00
+#define BCHP_V3D_DBG_REG_END                               0x00c21f20
+#define BCHP_GFX_L2_REG_START                              0x00c23000
+#define BCHP_GFX_L2_REG_END                                0x00c2302c
+#define BCHP_GFX_GR_REG_START                              0x00c24000
+#define BCHP_GFX_GR_REG_END                                0x00c2400c
+#define BCHP_SICH_REG_START                                0x00c50000
+#define BCHP_SICH_REG_END                                  0x00c5003c
+#define BCHP_UHFR_REG_START                                0x00d00000
+#define BCHP_UHFR_REG_END                                  0x00d000f8
+#define BCHP_UHFR_INTR2_REG_START                          0x00d00200
+#define BCHP_UHFR_INTR2_REG_END                            0x00d0022c
+#define BCHP_UHFR_GR_BRIDGE_REG_START                      0x00d00300
+#define BCHP_UHFR_GR_BRIDGE_REG_END                        0x00d0030c
+#define BCHP_SDS_CG_REG_START                              0x01100000
+#define BCHP_SDS_CG_REG_END                                0x01100038
+#define BCHP_SDS_FE_REG_START                              0x01100080
+#define BCHP_SDS_FE_REG_END                                0x011000bc
+#define BCHP_SDS_AGC_REG_START                             0x01100100
+#define BCHP_SDS_AGC_REG_END                               0x01100124
+#define BCHP_SDS_BL_REG_START                              0x01100140
+#define BCHP_SDS_BL_REG_END                                0x01100160
+#define BCHP_SDS_CL_REG_START                              0x01100180
+#define BCHP_SDS_CL_REG_END                                0x011001fc
+#define BCHP_SDS_EQ_REG_START                              0x01100200
+#define BCHP_SDS_EQ_REG_END                                0x0110028c
+#define BCHP_SDS_HP_REG_START                              0x01100300
+#define BCHP_SDS_HP_REG_END                                0x011003d4
+#define BCHP_SDS_VIT_REG_START                             0x01100400
+#define BCHP_SDS_VIT_REG_END                               0x01100428
+#define BCHP_SDS_FEC_REG_START                             0x01100440
+#define BCHP_SDS_FEC_REG_END                               0x01100454
+#define BCHP_SDS_OI_REG_START                              0x01100480
+#define BCHP_SDS_OI_REG_END                                0x011004c8
+#define BCHP_SDS_SNR_REG_START                             0x01100500
+#define BCHP_SDS_SNR_REG_END                               0x01100518
+#define BCHP_SDS_BERT_REG_START                            0x01100540
+#define BCHP_SDS_BERT_REG_END                              0x0110055c
+#define BCHP_SDS_DFT_REG_START                             0x01100580
+#define BCHP_SDS_DFT_REG_END                               0x011005a8
+#define BCHP_SDS_CWC_REG_START                             0x01100600
+#define BCHP_SDS_CWC_REG_END                               0x01100694
+#define BCHP_SDS_MISC_REG_START                            0x01100700
+#define BCHP_SDS_MISC_REG_END                              0x01100798
+#define BCHP_SDS_DSEC_REG_START                            0x01100800
+#define BCHP_SDS_DSEC_REG_END                              0x011008c8
+#define BCHP_SDS_TUNER_REG_START                           0x01100900
+#define BCHP_SDS_TUNER_REG_END                             0x011009fc
+#define BCHP_SDS_INTR2_0_REG_START                         0x01100a00
+#define BCHP_SDS_INTR2_0_REG_END                           0x01100a2c
+#define BCHP_SDS_INTR2_1_REG_START                         0x01100b00
+#define BCHP_SDS_INTR2_1_REG_END                           0x01100b2c
+#define BCHP_SDS_GR_BRIDGE_REG_START                       0x01100c00
+#define BCHP_SDS_GR_BRIDGE_REG_END                         0x01100c0c
+#define BCHP_TFEC_REG_START                                0x01130000
+#define BCHP_TFEC_REG_END                                  0x01130060
+#define BCHP_TFEC_MISC_REG_START                           0x01130100
+#define BCHP_TFEC_MISC_REG_END                             0x01130108
+#define BCHP_TFEC_INTR2_REG_START                          0x01130200
+#define BCHP_TFEC_INTR2_REG_END                            0x0113022c
+#define BCHP_TFEC_GR_BRIDGE_REG_START                      0x01130300
+#define BCHP_TFEC_GR_BRIDGE_REG_END                        0x0113030c
+#define BCHP_AFEC_REG_START                                0x01200000
+#define BCHP_AFEC_REG_END                                  0x012003fc
+#define BCHP_AFEC_INTR_CTRL2_REG_START                     0x01200800
+#define BCHP_AFEC_INTR_CTRL2_REG_END                       0x0120082c
+#define BCHP_AFEC_GR_BRIDGE_REG_START                      0x01200900
+#define BCHP_AFEC_GR_BRIDGE_REG_END                        0x0120090c
+#define BCHP_AFEC_GLOBAL_REG_START                         0x01200a00
+#define BCHP_AFEC_GLOBAL_REG_END                           0x01200a0c
+#define BCHP_RAAGA_DSP_RGR_REG_START                       0x01300000
+#define BCHP_RAAGA_DSP_RGR_REG_END                         0x01300008
+#define BCHP_RAAGA_DSP_MISC_REG_START                      0x01320000
+#define BCHP_RAAGA_DSP_MISC_REG_END                        0x0132044c
+#define BCHP_RAAGA_DSP_TIMERS_REG_START                    0x01321000
+#define BCHP_RAAGA_DSP_TIMERS_REG_END                      0x01321058
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START             0x01321080
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END               0x0132109c
+#define BCHP_RAAGA_DSP_PERI_SW_REG_START                   0x01321100
+#define BCHP_RAAGA_DSP_PERI_SW_REG_END                     0x01321154
+#define BCHP_RAAGA_DSP_DMA_REG_START                       0x01321400
+#define BCHP_RAAGA_DSP_DMA_REG_END                         0x01321664
+#define BCHP_RAAGA_DSP_ESR_SI_REG_START                    0x01322000
+#define BCHP_RAAGA_DSP_ESR_SI_REG_END                      0x01322014
+#define BCHP_RAAGA_DSP_INTH_REG_START                      0x01322200
+#define BCHP_RAAGA_DSP_INTH_REG_END                        0x0132222c
+#define BCHP_RAAGA_DSP_FW_INTH_REG_START                   0x01322400
+#define BCHP_RAAGA_DSP_FW_INTH_REG_END                     0x0132242c
+#define BCHP_RAAGA_DSP_FW_CFG_REG_START                    0x01323000
+#define BCHP_RAAGA_DSP_FW_CFG_REG_END                      0x0132357c
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START             0x01330000
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END               0x0133bffc
+#define BCHP_AIO_MISC_REG_START                            0x01380000
+#define BCHP_AIO_MISC_REG_END                              0x01380010
+#define BCHP_AIO_INTH_REG_START                            0x01380800
+#define BCHP_AIO_INTH_REG_END                              0x0138082c
+#define BCHP_AIO_INTD0_REG_START                           0x01380a00
+#define BCHP_AIO_INTD0_REG_END                             0x01380a14
+#define BCHP_AUD_FMM_MISC_REG_START                        0x013a0000
+#define BCHP_AUD_FMM_MISC_REG_END                          0x013a010c
+#define BCHP_AUD_FMM_BF_CTRL_REG_START                     0x013a2000
+#define BCHP_AUD_FMM_BF_CTRL_REG_END                       0x013a2b7c
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_START                   0x013a3000
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_END                     0x013a3014
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_START                   0x013a3020
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_END                     0x013a3034
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_START                   0x013a3040
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_END                     0x013a3054
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_START                  0x013a3100
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_END                    0x013a3114
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_START                  0x013a3120
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_END                    0x013a3134
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_START                  0x013a3140
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_END                    0x013a3154
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_START                   0x013a4000
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_END                     0x013a4bfc
+#define BCHP_AUD_FMM_SRC_ESR0_REG_START                    0x013a5000
+#define BCHP_AUD_FMM_SRC_ESR0_REG_END                      0x013a5014
+#define BCHP_AUD_FMM_DP_CTRL0_REG_START                    0x013a8000
+#define BCHP_AUD_FMM_DP_CTRL0_REG_END                      0x013a98ec
+#define BCHP_AUD_FMM_DP_ESR00_REG_START                    0x013abc00
+#define BCHP_AUD_FMM_DP_ESR00_REG_END                      0x013abc14
+#define BCHP_AUD_FMM_DP_ESR20_REG_START                    0x013abc80
+#define BCHP_AUD_FMM_DP_ESR20_REG_END                      0x013abc94
+#define BCHP_AUD_FMM_IOP_CTRL_REG_START                    0x013b8000
+#define BCHP_AUD_FMM_IOP_CTRL_REG_END                      0x013b8144
+#define BCHP_AUD_FMM_IOP_ESR_REG_START                     0x013b8400
+#define BCHP_AUD_FMM_IOP_ESR_REG_END                       0x013b8414
+#define BCHP_AUD_FMM_OP_CTRL_REG_START                     0x013ba000
+#define BCHP_AUD_FMM_OP_CTRL_REG_END                       0x013ba1fc
+#define BCHP_AUD_FMM_OP_ESR_REG_START                      0x013ba400
+#define BCHP_AUD_FMM_OP_ESR_REG_END                        0x013ba414
+#define BCHP_AUD_FMM_PLL0_REG_START                        0x013ba800
+#define BCHP_AUD_FMM_PLL0_REG_END                          0x013ba834
+#define BCHP_AUD_FMM_PLL1_REG_START                        0x013ba900
+#define BCHP_AUD_FMM_PLL1_REG_END                          0x013ba934
+#define BCHP_HIFIDAC_CTRL0_REG_START                       0x013bb000
+#define BCHP_HIFIDAC_CTRL0_REG_END                         0x013bb1fc
+#define BCHP_HIFIDAC_RM0_REG_START                         0x013bb200
+#define BCHP_HIFIDAC_RM0_REG_END                           0x013bb224
+#define BCHP_HIFIDAC_ESR0_REG_START                        0x013bb300
+#define BCHP_HIFIDAC_ESR0_REG_END                          0x013bb314
+#define BCHP_AUD_FMM_MS_CTRL_REG_START                     0x013bc000
+#define BCHP_AUD_FMM_MS_CTRL_REG_END                       0x013bdbfc
+#define BCHP_AUD_FMM_MS_ESR_REG_START                      0x013be000
+#define BCHP_AUD_FMM_MS_ESR_REG_END                        0x013be014
+#define BCHP_RAAGA_DSP_SEC0_REG_START                      0x01400000
+#define BCHP_RAAGA_DSP_SEC0_REG_END                        0x01400000
+#define BCHP_FTM_UART_REG_START                            0x01410000
+#define BCHP_FTM_UART_REG_END                              0x014100fc
+#define BCHP_FTM_PHY_REG_START                             0x01410000
+#define BCHP_FTM_PHY_REG_END                               0x014101fc
+#define BCHP_FTM_PHY_ANA_REG_START                         0x01410000
+#define BCHP_FTM_PHY_ANA_REG_END                           0x01410210
+#define BCHP_FTM_SKIT_REG_START                            0x01410000
+#define BCHP_FTM_SKIT_REG_END                              0x01410248
+#define BCHP_FTM_INTR2_REG_START                           0x01410000
+#define BCHP_FTM_INTR2_REG_END                             0x0141032c
+#define BCHP_FTM_GR_BRIDGE_REG_START                       0x01410000
+#define BCHP_FTM_GR_BRIDGE_REG_END                         0x0141033c
+#define BCHP_FTM_SW_SPARE_REG_START                        0x01410000
+#define BCHP_FTM_SW_SPARE_REG_END                          0x01410344
+
+
+/***************************************************************************
+ *AUD_FMM_MS_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK  0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
+
+/***************************************************************************
+ *AUD_FMM_OP_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
+ ***************************************************************************/
+/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD1
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_VFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *GFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK      0xffffffff
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT     0
+
+/***************************************************************************
+ *GFD_1
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD_1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK    0xffffffff
+#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT   0
+
+/***************************************************************************
+ *HIFIDAC_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_MUTE_USAGE - Mute usage
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *M2MC
+ ***************************************************************************/
+/***************************************************************************
+ *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK          0xffffffff
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT         0
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK              0xf0000000
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT             28
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK          0x0fffffe0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT         5
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK              0x0000001e
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT             1
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK           0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT          0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid   0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK              0xffff8000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT             15
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK   0x00004000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT  14
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK   0x00002000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT  13
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK         0x00000800
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT        11
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE   1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE  0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK  0x00000400
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK  0x00000200
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK          0x00000100
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT         8
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE   0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK   0x00000020
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT  5
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK     0x00000002
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK     0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT    0
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/***************************************************************************
+ *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK        0xffffffff
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT       0
+
+/***************************************************************************
+ *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK         0xffffffff
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT        0
+
+/***************************************************************************
+ *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_11_DST_COLOR_MATRIX_N - Linked-List Packet Word N for group DST_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_11_DST_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_12_OUTPUT_COLOR_MATRIX_N - Linked-List Packet Word N for group OUTPUT_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_12_OUTPUT_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_13_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *LIST_PKT_14_DST_CLUT - Linked-List Packet Word for group DST_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_14_DST_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_14_DST_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *TYPE_CLUT_COLOR_DATA - color data for color look up table
+ ***************************************************************************/
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK                  0xff000000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT                 24
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK                    0x00ff0000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT                   16
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK                  0x0000ff00
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT                 8
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK                   0x000000ff
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT                  0
+
+/***************************************************************************
+ *MEM_DMA
+ ***************************************************************************/
+/***************************************************************************
+ *DESC_WORD0 - MEM DMA Descriptor Word 0
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD0 :: READ_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD1 - MEM DMA Descriptor Word 1
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD1 :: WRITE_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_MASK                    0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD2 - MEM DMA Descriptor Word 2
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD2 :: INTR_ENABLE [31:31] */
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK                   0x80000000
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_SHIFT                  31
+
+/* MEM_DMA :: DESC_WORD2 :: LAST [30:30] */
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_MASK                          0x40000000
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_SHIFT                         30
+
+/* MEM_DMA :: DESC_WORD2 :: AUTO_APPEND [29:29] */
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_MASK                   0x20000000
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_SHIFT                  29
+
+/* MEM_DMA :: DESC_WORD2 :: reserved0 [28:25] */
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_MASK                     0x1e000000
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_SHIFT                    25
+
+/* MEM_DMA :: DESC_WORD2 :: TRANSFER_SIZE [24:00] */
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK                 0x01ffffff
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_SHIFT                0
+
+/***************************************************************************
+ *DESC_WORD3 - MEM DMA Descriptor Word 3
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD3 :: NEXT_DESC_ADDR [31:05] */
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK                0xffffffe0
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_SHIFT               5
+
+/* MEM_DMA :: DESC_WORD3 :: reserved0 [04:03] */
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_MASK                     0x00000018
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_SHIFT                    3
+
+/* MEM_DMA :: DESC_WORD3 :: READ_ENDIAN_MODE [02:02] */
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_MASK              0x00000004
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_SHIFT             2
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_BIG_ENDIAN        0
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_LITTLE_ENDIAN     1
+
+/* MEM_DMA :: DESC_WORD3 :: WRITE_ENDIAN_XLATE_MODE [01:00] */
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_MASK       0x00000003
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_SHIFT      0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_WORD_ALIGNED 0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_HALF_WORD_ALIGNED 1
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_BYTE_ALIGNED 2
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_reserved   3
+
+/***************************************************************************
+ *DESC_WORD4 - MEM DMA Descriptor Word 4
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD4 :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_SHIFT                    16
+
+/* MEM_DMA :: DESC_WORD4 :: SCRAM_CTRL_RSV [15:14] */
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_MASK                0x0000c000
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_SHIFT               14
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_END [13:13] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK                  0x00002000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_SHIFT                 13
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_START [12:12] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK                0x00001000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_SHIFT               12
+
+/* MEM_DMA :: DESC_WORD4 :: SG_ENABLE [11:11] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK                     0x00000800
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_SHIFT                    11
+
+/* MEM_DMA :: DESC_WORD4 :: ENC_DEC_INIT [10:10] */
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_MASK                  0x00000400
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_SHIFT                 10
+
+/* MEM_DMA :: DESC_WORD4 :: MODE_SEL [09:08] */
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_MASK                      0x00000300
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT                     8
+
+/* MEM_DMA :: DESC_WORD4 :: KEY_SELECT [07:00] */
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_MASK                    0x000000ff
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD5 - MEM DMA Descriptor Word 5
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD5 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD6 - MEM DMA Descriptor Word 6
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD6 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD7 - MEM DMA Descriptor Word 7
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD7 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *RAAGA_REGSET_DSP_CFG
+ ***************************************************************************/
+/***************************************************************************
+ *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK     0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT    0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo   2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono     1
+
+/***************************************************************************
+ *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
+
+/***************************************************************************
+ *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off     0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On      1
+
+/***************************************************************************
+ *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt  1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo  2
+
+/***************************************************************************
+ *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK       0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT      0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono    1
+
+/***************************************************************************
+ *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK   0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *RDC
+ ***************************************************************************/
+/***************************************************************************
+ *RUL - RUL Command.
+ ***************************************************************************/
+/* RDC :: RUL :: opcode [31:24] */
+#define BCHP_RDC_RUL_opcode_MASK                                   0xff000000
+#define BCHP_RDC_RUL_opcode_SHIFT                                  24
+#define BCHP_RDC_RUL_opcode_NOP                                    0
+#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM                          1
+#define BCHP_RDC_RUL_opcode_REG_WRITE                              2
+#define BCHP_RDC_RUL_opcode_REG_READ                               3
+#define BCHP_RDC_RUL_opcode_LOAD_IMM                               4
+#define BCHP_RDC_RUL_opcode_WINDOW_WRITE                           5
+#define BCHP_RDC_RUL_opcode_BLOCK_WRITE                            6
+#define BCHP_RDC_RUL_opcode_WINDOW_COPY                            7
+#define BCHP_RDC_RUL_opcode_BLOCK_COPY                             8
+#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK                        9
+#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW                        10
+#define BCHP_RDC_RUL_opcode_AND                                    11
+#define BCHP_RDC_RUL_opcode_AND_IMM                                12
+#define BCHP_RDC_RUL_opcode_OR                                     13
+#define BCHP_RDC_RUL_opcode_OR_IMM                                 14
+#define BCHP_RDC_RUL_opcode_XOR                                    15
+#define BCHP_RDC_RUL_opcode_XOR_IMM                                16
+#define BCHP_RDC_RUL_opcode_NOT                                    17
+#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT                           18
+#define BCHP_RDC_RUL_opcode_SUM                                    19
+#define BCHP_RDC_RUL_opcode_SUM_IMM                                20
+#define BCHP_RDC_RUL_opcode_COND_SKIP                              21
+#define BCHP_RDC_RUL_opcode_SKIP                                   22
+#define BCHP_RDC_RUL_opcode_EXIT                                   23
+#define BCHP_RDC_RUL_opcode_PLACEHOLDER                            255
+
+/* RDC :: RUL :: reserved0 [23:23] */
+#define BCHP_RDC_RUL_reserved0_MASK                                0x00800000
+#define BCHP_RDC_RUL_reserved0_SHIFT                               23
+
+/* union - case rdc_args [22:00] */
+/* RDC :: RUL :: rdc_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_rdc_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: rdc_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_rdc_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_rdc_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: rdc_args :: src2 [11:06] */
+#define BCHP_RDC_RUL_rdc_args_src2_MASK                            0x00000fc0
+#define BCHP_RDC_RUL_rdc_args_src2_SHIFT                           6
+
+/* RDC :: RUL :: rdc_args :: dest [05:00] */
+#define BCHP_RDC_RUL_rdc_args_dest_MASK                            0x0000003f
+#define BCHP_RDC_RUL_rdc_args_dest_SHIFT                           0
+
+/* union - case reg_args [22:00] */
+/* RDC :: RUL :: reg_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_reg_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_reg_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: reg_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_reg_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_reg_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: reg_args :: count [11:00] */
+#define BCHP_RDC_RUL_reg_args_count_MASK                           0x00000fff
+#define BCHP_RDC_RUL_reg_args_count_SHIFT                          0
+
+/***************************************************************************
+ *XPT_PB
+ ***************************************************************************/
+/***************************************************************************
+ *DESCRIPTOR_ABSTRACT - Playback Linked-List Descriptor Abstract
+ ***************************************************************************/
+/* XPT_PB :: DESCRIPTOR_ABSTRACT :: DESCRIPTOR_FORMAT [31:00] */
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_MASK     0xffffffff
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_SHIFT    0
+
+/***************************************************************************
+ *DESC_0 - Playback Linked-List Descriptor Word 0
+ ***************************************************************************/
+/* XPT_PB :: DESC_0 :: PB_BUFFER_START_ADDR [31:00] */
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_MASK               0xffffffff
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_SHIFT              0
+
+/***************************************************************************
+ *DESC_1 - Playback Linked-List Descriptor Word 1
+ ***************************************************************************/
+/* XPT_PB :: DESC_1 :: PB_BUFFER_LENGTH [31:00] */
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_MASK                   0xffffffff
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_SHIFT                  0
+
+/***************************************************************************
+ *DESC_2 - Playback Linked-List Descriptor Word 2
+ ***************************************************************************/
+/* XPT_PB :: DESC_2 :: PB_INTERRUPT_ENABLE [31:31] */
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_MASK                0x80000000
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_SHIFT               31
+
+/* XPT_PB :: DESC_2 :: PB_FORCE_RESYNC [30:30] */
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_MASK                    0x40000000
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_SHIFT                   30
+
+/* XPT_PB :: DESC_2 :: PB_HOST_DATA_INS_EN [29:29] */
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_MASK                0x20000000
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_SHIFT               29
+
+/* XPT_PB :: DESC_2 :: reserved0 [28:28] */
+#define BCHP_XPT_PB_DESC_2_reserved0_MASK                          0x10000000
+#define BCHP_XPT_PB_DESC_2_reserved0_SHIFT                         28
+
+/* XPT_PB :: DESC_2 :: PB_DESC_TAG_ID [27:24] */
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_MASK                     0x0f000000
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_SHIFT                    24
+
+/* XPT_PB :: DESC_2 :: reserved1 [23:00] */
+#define BCHP_XPT_PB_DESC_2_reserved1_MASK                          0x00ffffff
+#define BCHP_XPT_PB_DESC_2_reserved1_SHIFT                         0
+
+/***************************************************************************
+ *DESC_3 - Playback Linked-List Descriptor Word 3
+ ***************************************************************************/
+/* XPT_PB :: DESC_3 :: PB_NEXT_DESC_ADDR [31:04] */
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_MASK                  0xfffffff0
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_SHIFT                 4
+
+/* XPT_PB :: DESC_3 :: reserved0 [03:01] */
+#define BCHP_XPT_PB_DESC_3_reserved0_MASK                          0x0000000e
+#define BCHP_XPT_PB_DESC_3_reserved0_SHIFT                         1
+
+/* XPT_PB :: DESC_3 :: PB_LAST_DESC_IND [00:00] */
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_MASK                   0x00000001
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_SHIFT                  0
+
+/***************************************************************************
+ *XPT_RAVE
+ ***************************************************************************/
+/***************************************************************************
+ *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
+
+/***************************************************************************
+ *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
+
+/***************************************************************************
+ *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
+ ***************************************************************************/
+/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
+
+#endif /* #ifndef BCHP_COMMON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_ddr40_phy_control_regs_0.h b/include/linux/brcmstb/7344b0/bchp_ddr40_phy_control_regs_0.h
new file mode 100644
index 0000000..836adfb
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_ddr40_phy_control_regs_0.h
@@ -0,0 +1,1513 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 31 13:56:38 2011
+ *                 MD5 Checksum         b0a0062767e487fe78d25d07b5b21b78
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_ddr40_phy_control_regs_0.h $
+ * 
+ * Hydra_Software_Devel/2   5/31/11 3:28p albertl
+ * SW7344-40: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_CONTROL_REGS_0 - DDR40 DDR40 physical interface control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION   0x00a06000 /* Address & Control revision register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL 0x00a06004 /* PHY clock power management control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS 0x00a06010 /* PHY PLL status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG 0x00a06014 /* PHY PLL configuration register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL 0x00a06018 /* PHY PLL control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS 0x00a0601c /* PHY PLL dividers control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL 0x00a06020 /* Aux Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL 0x00a06030 /* Address & Control coarse VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL 0x00a06034 /* Address & Control fine VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL 0x00a06038 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL 0x00a0603c /* PVT Compensation control and status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL 0x00a06040 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS 0x00a06044 /* PHY Auto Init rd_data_dly result register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE 0x00a06048 /* PHY VDL calibration control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS 0x00a0604c /* PHY VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS 0x00a06050 /* PHY DQ VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS 0x00a06054 /* PHY Write Channel VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS 0x00a06058 /* PHY Read Enable VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL 0x00a0605c /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS 0x00a06060 /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS 0x00a06064 /* Virtual VTT Connections register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE 0x00a06068 /* Virtual VTT Override register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL 0x00a0606c /* VREF DAC Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL 0x00a06070 /* PhyBist Control Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED 0x00a06074 /* PhyBist Seed Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS 0x00a06078 /* PhyBist General Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS 0x00a0607c /* PhyBist Per-Bit Control Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS 0x00a06080 /* PhyBist Per-Bit DQ Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS 0x00a06084 /* PhyBist Per-Bit DM and CK Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG 0x00a06090 /* DRAM Command Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0  0x00a06094 /* Mode Register 0 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1  0x00a06098 /* Mode Register 1 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2  0x00a0609c /* Mode Register 2 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3  0x00a060a0 /* Mode Register 3 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL 0x00a060a4 /* Standby Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL 0x00a060b0 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2 0x00a060b4 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS 0x00a060b8 /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2 0x00a060bc /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE 0x00a060c0 /* Freeze-on-error enable register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK 0x00a060c4 /* Datapth Loopback control register */
+
+/***************************************************************************
+ *REVISION - Address & Control revision register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_MASK      0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_SHIFT     16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_MASK          0x0000ff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_SHIFT         8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_DEFAULT       64
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_MASK          0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_DEFAULT       5
+
+/***************************************************************************
+ *CLK_PM_CTRL - PHY clock power management control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_MASK   0xfffffffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_SHIFT  1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_DEFAULT 0
+
+/***************************************************************************
+ *PLL_STATUS - PHY PLL status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_MASK    0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_SHIFT   27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK_LOST [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_MASK    0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_SHIFT   26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: DDR_MHZ [25:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_MASK      0x03ffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_SHIFT     14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_4X [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: STATUS [12:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_MASK       0x00001ffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_SHIFT      1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_MASK         0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_CONFIG - PHY PLL configuration register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved0 [31:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_MASK    0xffffff80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_SHIFT   7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LP40_PLL_POST_RESET [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET_POST_DIV [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LDO_CTRL [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_MASK     0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_SHIFT    3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_DEFAULT  2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved1 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_MASK    0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_SHIFT   2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_MASK        0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_SHIFT       1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_DEFAULT     1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PWRDN [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_MASK        0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_SHIFT       0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_DEFAULT     0
+
+/***************************************************************************
+ *PLL_CONTROL - PHY PLL control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: reserved0 [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_SHIFT  31
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_kp [30:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_MASK        0x78000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_SHIFT       27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_DEFAULT     10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ki [26:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_MASK        0x07000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_SHIFT       24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_DEFAULT     3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ka [23:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_MASK        0x00e00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_SHIFT       21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_DEFAULT     3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: PLL_CONTROL [20:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_MASK 0x001fffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_DEFAULT 0
+
+/***************************************************************************
+ *PLL_DIVIDERS - PHY PLL dividers control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_MASK  0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_SHIFT 16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_HI [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_MASK 0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_LO [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: POST_DIV [13:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_MASK   0x00003800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_SHIFT  11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_DEFAULT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: PDIV [10:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_MASK       0x00000700
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_SHIFT      8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_DEFAULT    4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_MASK       0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_DEFAULT    32
+
+/***************************************************************************
+ *AUX_CONTROL - Aux Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved0 [31:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_MASK   0xfffffc00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_SHIFT  10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_cs [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_MASK       0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_SHIFT      7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_ad [06:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_MASK       0x00000070
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_SHIFT      4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_odt [03:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_MASK      0x0000000e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_SHIFT     1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: override [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_CTL - Address & Control coarse VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BIT_CTL - Address & Control fine VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_SHIFT  31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved0 [30:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ffffe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: rxenb [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_MASK  0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved1 [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_SHIFT 7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_reb [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_DEFAULT 0
+
+/***************************************************************************
+ *ZQ_PVT_COMP_CTL - PVT Compensation control and status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: update_mode [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_done [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_done [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_done [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: auto_sample_en [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_MASK 0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_en [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_ovr_en [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_ovr_en [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_comp [17:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_MASK 0x00038000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_comp [14:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_MASK 0x00007000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [11:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_MASK 0x00000e00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [08:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_MASK 0x000001c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_DEFAULT 0
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: auto_oeb [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a15 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_MASK  0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a14 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_MASK  0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a13 [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_MASK  0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_aux [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_MASK  0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: half_strength [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_MASK     0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_SHIFT    2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_MASK  0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_MASK     0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_SHIFT    0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_DEFAULT  0
+
+/***************************************************************************
+ *VDL_RD_DATA_DLY_STATUS - PHY Auto Init rd_data_dly result register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_SHIFT 12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: auto_init_state [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_MASK 0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_max [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_min [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_DEFAULT 7
+
+/***************************************************************************
+ *VDL_CALIBRATE - PHY VDL calibration control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_SHIFT 29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: use_straps [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: auto_init [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: skip_rst [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_MASK  0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_SHIFT 26
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: exit_in_sr [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_dly_cal [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_refresh [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_wr_dq [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: dq0_only [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_MASK  0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_mr_mpr [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_cal [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_MASK   0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_SHIFT  19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_en_cal [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_clocks [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_pair [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_steps [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_auto [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_ftm [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_phybist [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_byte [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_clocks [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_test [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_always [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_once [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_fast [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_DEFAULT 0
+
+/***************************************************************************
+ *VDL_CALIB_STATUS - PHY VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_MASK 0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_fail [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_MASK 0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_SHIFT 29
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_done [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_rd_data_dly_error [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_read_en_error [26:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_MASK 0x07800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_error [22:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_MASK 0x00780000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_sel [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_total [11:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_MASK 0x00000ffc
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_DEFAULT 1
+
+/***************************************************************************
+ *VDL_DQ_CALIB_STATUS - PHY DQ VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_total [25:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_MASK 0x03ff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_clocks [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_mode [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VDL_WR_CHAN_CALIB_STATUS - PHY Write Channel VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VDL_RD_EN_CALIB_STATUS - PHY Read Enable VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: low_vtt [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: high_vtt [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: error_reset [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_ctl_idle [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cs_idle [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cke_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error [18:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_MASK 0x0007fff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_low [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_high [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ready [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_DEFAULT 16777215
+
+/***************************************************************************
+ *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_DEFAULT 262143
+
+/***************************************************************************
+ *VREF_DAC_CONTROL - VREF DAC Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK1_GT_INT [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK0_GT_INT [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_GT_INT [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: EXT_GT_INT [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_TESTOUT_MUX_CTL [16:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_MASK 0x00018000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TEST [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_MASK   0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_SHIFT  14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_MASK   0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_SHIFT  13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_MASK   0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_SHIFT  12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_MASK   0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_SHIFT  6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_DEFAULT 32
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_MASK   0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_SHIFT  0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_DEFAULT 32
+
+/***************************************************************************
+ *PHYBIST_CNTRL - PhyBist Control Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_error_sel [13:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_MASK 0x00003f00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved1 [07:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_MASK 0x000000e0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_SHIFT 5
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: bench_mode [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_dat_error [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_ctl_error [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: int_loopback [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_DEFAULT 0
+
+/***************************************************************************
+ *PHYBIST_SEED - PhyBist Seed Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_SEED :: seed [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_MASK       0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_DEFAULT    621693686
+
+/***************************************************************************
+ *PHYBIST_STATUS - PhyBist General Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_pass [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_pass [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_SHIFT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_done [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_done [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: ctl_errors [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_DQ_STATUS - PhyBist Per-Bit DQ Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_STATUS :: dat_errors [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_MASK 0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_MISC_STATUS - PhyBist Per-Bit DM and CK Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: ck_errors [07:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_MASK 0x000000f0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: dm_errors [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_SHIFT 0
+
+/***************************************************************************
+ *COMMAND_REG - DRAM Command Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_MASK   0xfe000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_SHIFT  25
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: aux [24:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_MASK         0x01c00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_SHIFT        22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: we [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_MASK          0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_SHIFT         21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_DEFAULT       0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: cas [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_MASK         0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_SHIFT        20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ras [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_MASK         0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_SHIFT        19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ba [18:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_MASK          0x00070000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_SHIFT         16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_DEFAULT       0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_MASK          0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_DEFAULT       0
+
+/***************************************************************************
+ *MODE_REG0 - Mode Register 0
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG1 - Mode Register 1
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG2 - Mode Register 2
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG3 - Mode Register 3
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_DEFAULT         0
+
+/***************************************************************************
+ *STANDBY_CONTROL - Standby Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_ready [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_exit_pin_en [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_active [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: armed [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_MASK   0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_SHIFT  15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: warmstart [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_ldo_volts [13:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_MASK 0x00003000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_skip_mrs [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_rst_n [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_cke [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: ldo_volts [08:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_MASK 0x00000180
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_DEFAULT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: skip_mrs [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: rst_n [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_MASK   0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_SHIFT  5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: cke [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_MASK     0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_SHIFT    4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_CONTROL - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: reserved0 [31:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_MASK 0xf0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_MASK       0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_SHIFT      16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_MASK  0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_MASK 0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_MASK     0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_SHIFT    12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_MASK      0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_SHIFT     11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_MASK      0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_SHIFT     8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_CONTROL2 - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_MASK     0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_SHIFT    20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_MASK       0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_SHIFT      17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_MASK       0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_SHIFT      12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_MASK      0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_SHIFT     7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_MASK       0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_DEFAULT    0
+
+/***************************************************************************
+ *STRAP_STATUS - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_MASK  0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_reg [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_MASK   0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_SHIFT  29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_memc [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_MASK  0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_MASK        0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_SHIFT       16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_MASK   0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_SHIFT  14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_MASK      0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_SHIFT     12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_MASK       0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_SHIFT      11
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_SHIFT 10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_MASK       0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_SHIFT      8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_MASK  0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_SHIFT 0
+
+/***************************************************************************
+ *STRAP_STATUS2 - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_MASK      0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_SHIFT     20
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_MASK        0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_SHIFT       17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_MASK        0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_SHIFT       12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_MASK       0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_SHIFT      7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_MASK        0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_SHIFT       0
+
+/***************************************************************************
+ *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl1 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl0 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl1 [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl0 [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_DEFAULT 0
+
+/***************************************************************************
+ *DATAPATH_LOOPBACK - Datapth Loopback control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: xor_dm_rd_en [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: use_addr_ctl [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_DEFAULT 0
+
+#endif /* #ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_ddr40_phy_word_lane_0_0.h b/include/linux/brcmstb/7344b0/bchp_ddr40_phy_word_lane_0_0.h
new file mode 100644
index 0000000..8d52161
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_ddr40_phy_word_lane_0_0.h
@@ -0,0 +1,3334 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 31 13:56:57 2011
+ *                 MD5 Checksum         b0a0062767e487fe78d25d07b5b21b78
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_ddr40_phy_word_lane_0_0.h $
+ * 
+ * Hydra_Software_Devel/2   5/31/11 3:28p albertl
+ * SW7344-40: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_0_0 - DDR40 DDR40 word lane #0 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN 0x00a06200 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W 0x00a06204 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P 0x00a06208 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N 0x00a0620c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W 0x00a06210 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W 0x00a06214 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W 0x00a06218 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W 0x00a0621c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W 0x00a06220 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W 0x00a06224 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W 0x00a06228 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W 0x00a0622c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W 0x00a06230 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x00a06234 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x00a06238 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x00a0623c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x00a06240 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x00a06244 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x00a06248 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x00a0624c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x00a06250 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x00a06254 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x00a06258 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x00a0625c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x00a06260 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x00a06264 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x00a06268 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x00a0626c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x00a06270 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x00a06274 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W 0x00a062a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P 0x00a062a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N 0x00a062ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W 0x00a062b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W 0x00a062b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W 0x00a062b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W 0x00a062bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W 0x00a062c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W 0x00a062c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W 0x00a062c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W 0x00a062cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W 0x00a062d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x00a062d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x00a062d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x00a062dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x00a062e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x00a062e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x00a062e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x00a062ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x00a062f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x00a062f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x00a062f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x00a062fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x00a06300 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x00a06304 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x00a06308 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x00a0630c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x00a06310 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x00a06314 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x00a06328 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x00a0632c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x00a06330 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x00a06334 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W 0x00a06338 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x00a0633c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x00a06348 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x00a0634c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x00a06350 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x00a06354 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W 0x00a06358 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x00a0635c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY 0x00a06360 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL 0x00a06364 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0 0x00a06370 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1 0x00a06374 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2 0x00a06378 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3 0x00a0637c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0 0x00a06380 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1 0x00a06384 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2 0x00a06388 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3 0x00a0638c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS 0x00a06390 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR 0x00a06394 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL 0x00a063a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL 0x00a063a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE 0x00a063a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE 0x00a063ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ 0x00a063b0 /* PHYBIST mode VDL step select adjustment register */
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_RD_EN - Read Enable Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *READ_DATA_DLY - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_MASK  0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: rd_data_dly [02:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_MASK 0x00000007
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_DEFAULT 1
+
+/***************************************************************************
+ *READ_CONTROL - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_MASK   0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_SHIFT  3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_enable [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_te_adj [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_le_adj [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_DEFAULT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status1 [07:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_MASK 0x000000f0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status0 [03:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_MASK 0x0000000f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_DEFAULT 0
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: clear [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_DEFAULT 0
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_MASK    0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_SHIFT   31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_SHIFT 24
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_MASK 0x00c00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_SHIFT 22
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_MASK 0x00300000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_SHIFT 20
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00080000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 19
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00040000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_SHIFT 18
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_MASK  0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_MASK  0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00008000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 15
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00004000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 14
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00002000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 13
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00001000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 12
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_MASK 0x00000008
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_DEFAULT 0
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_MASK  0xfffff000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_SHIFT 12
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: no_dqs_rd [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_MASK  0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_MASK    0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_SHIFT   6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_MASK      0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_SHIFT     2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_DEFAULT   0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_MASK   0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_SHIFT  1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_MASK      0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_SHIFT     0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_DEFAULT   0
+
+/***************************************************************************
+ *CLOCK_PAD_DISABLE - Clock pad disable register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_DEFAULT 0
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffc
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_SHIFT 2
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: long [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_MASK    0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_SHIFT   1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: mode [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_DEFAULT 0
+
+/***************************************************************************
+ *PHYBIST_VDL_ADJ - PHYBIST mode VDL step select adjustment register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_SHIFT 29
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq1_vdl_adj [28:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_MASK 0x1f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved1 [23:21] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_MASK 0x00e00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_SHIFT 21
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq0_vdl_adj [20:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_MASK 0x001f0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved2 [15:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_MASK 0x0000e000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_SHIFT 13
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs1_vdl_adj [12:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_MASK 0x00001f00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved3 [07:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_MASK 0x000000e0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_SHIFT 5
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs0_vdl_adj [04:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_MASK 0x0000001f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_DEFAULT 0
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_ddr40_phy_word_lane_1_0.h b/include/linux/brcmstb/7344b0/bchp_ddr40_phy_word_lane_1_0.h
new file mode 100644
index 0000000..72871d7
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_ddr40_phy_word_lane_1_0.h
@@ -0,0 +1,139 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:38:02 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_ddr40_phy_word_lane_1_0.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 1:09p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_1_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_1_0 - DDR40 DDR40 word lane #1 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN 0x00a06400 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W 0x00a06404 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P 0x00a06408 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N 0x00a0640c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W 0x00a06410 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W 0x00a06414 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W 0x00a06418 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W 0x00a0641c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W 0x00a06420 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W 0x00a06424 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W 0x00a06428 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W 0x00a0642c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W 0x00a06430 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x00a06434 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x00a06438 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x00a0643c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x00a06440 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x00a06444 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x00a06448 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x00a0644c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x00a06450 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x00a06454 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x00a06458 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x00a0645c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x00a06460 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x00a06464 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x00a06468 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x00a0646c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x00a06470 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x00a06474 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W 0x00a064a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P 0x00a064a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N 0x00a064ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W 0x00a064b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W 0x00a064b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W 0x00a064b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W 0x00a064bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W 0x00a064c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W 0x00a064c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W 0x00a064c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W 0x00a064cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W 0x00a064d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x00a064d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x00a064d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x00a064dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x00a064e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x00a064e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x00a064e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x00a064ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x00a064f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x00a064f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x00a064f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x00a064fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x00a06500 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x00a06504 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x00a06508 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x00a0650c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x00a06510 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x00a06514 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x00a06528 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x00a0652c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x00a06530 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x00a06534 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W 0x00a06538 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x00a0653c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x00a06548 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x00a0654c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x00a06550 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x00a06554 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W 0x00a06558 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x00a0655c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_DATA_DLY 0x00a06560 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_CONTROL 0x00a06564 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_0 0x00a06570 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_1 0x00a06574 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_2 0x00a06578 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_3 0x00a0657c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_0 0x00a06580 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_1 0x00a06584 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_2 0x00a06588 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_3 0x00a0658c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_STATUS 0x00a06590 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_CLEAR 0x00a06594 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL 0x00a065a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL 0x00a065a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_CLOCK_PAD_DISABLE 0x00a065a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_WR_PREAMBLE_MODE 0x00a065ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ 0x00a065b0 /* PHYBIST mode VDL step select adjustment register */
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_1_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_ebi.h b/include/linux/brcmstb/7344b0/bchp_ebi.h
new file mode 100644
index 0000000..9f1aad8
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_ebi.h
@@ -0,0 +1,1711 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:34:35 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_ebi.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 1:18p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EBI_H__
+#define BCHP_EBI_H__
+
+/***************************************************************************
+ *EBI - EBI Registers
+ ***************************************************************************/
+#define BCHP_EBI_CS_BASE_0                       0x00000800 /* EBI CS Base 0 Register */
+#define BCHP_EBI_CS_CONFIG_0                     0x00000804 /* EBI CS Config 0 Register */
+#define BCHP_EBI_CS_BASE_1                       0x00000808 /* EBI CS Base 1 Register */
+#define BCHP_EBI_CS_CONFIG_1                     0x0000080c /* EBI CS Config 1 Register */
+#define BCHP_EBI_CS_BASE_2                       0x00000810 /* EBI CS Base 2 Register */
+#define BCHP_EBI_CS_CONFIG_2                     0x00000814 /* EBI CS Config 2 Register */
+#define BCHP_EBI_CS_BASE_3                       0x00000818 /* EBI CS Base 3 Register */
+#define BCHP_EBI_CS_CONFIG_3                     0x0000081c /* EBI CS Config 3 Register */
+#define BCHP_EBI_CS_BASE_4                       0x00000820 /* EBI CS Base 4 Register */
+#define BCHP_EBI_CS_CONFIG_4                     0x00000824 /* EBI CS Config 4 Register */
+#define BCHP_EBI_CS_BASE_5                       0x00000828 /* EBI CS Base 5 Register */
+#define BCHP_EBI_CS_CONFIG_5                     0x0000082c /* EBI CS Config 5 Register */
+#define BCHP_EBI_BURST_CFG_0                     0x00000840 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_1                     0x00000844 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_2                     0x00000848 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_3                     0x0000084c /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_4                     0x00000850 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_5                     0x00000854 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_ECR                             0x00000900 /* EBI Configuration Register */
+#define BCHP_EBI_CS_TRISTATE_CFG                 0x00000918 /* EBI CS Tristate Configuration Register */
+#define BCHP_EBI_TA_CFG                          0x0000091c /* EBI TA Configuration Register */
+#define BCHP_EBI_CS_SPI_SELECT                   0x00000920 /* SPI CS Select */
+#define BCHP_EBI_ARRAY_ADDRESS                   0x000009f0 /* EBI Data Array Address */
+
+/***************************************************************************
+ *CS_BASE_0 - EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_0 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_0_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT                         13
+
+/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_0_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_0 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_0_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_0_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_0 - EBI CS Config 0 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_0_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT                       1
+
+/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_0_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_0 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_0_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_0_le_SHIFT                              10
+
+/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_0_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_0_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT                       4
+
+/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_0_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT                        1
+
+/***************************************************************************
+ *CS_BASE_1 - EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_1 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_1_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_1_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_1 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_1_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_1_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_1_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_1 - EBI CS Config 1 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_1_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_1_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_1 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_1_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_1_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_1_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_1_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_1_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_2 - EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_2 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_2_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_2_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_2 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_2_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_2_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_2_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_2 - EBI CS Config 2 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_2_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_2_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_2 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_2_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_2_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_2_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_2_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_2_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_3 - EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_3 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_3_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_3_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_3 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_3_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_3_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_3_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_3 - EBI CS Config 3 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_3_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_3_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_3 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_3_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_3_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_3_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_3_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_3_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_4 - EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_4 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_4_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_4_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_4 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_4_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_4_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_4_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_4 - EBI CS Config 4 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_4_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_4_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_4 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_4_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_4_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_4_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_4_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_4_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_5 - EBI CS Base 5 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_5 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_5_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_5_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_5_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_5 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_5_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_5_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_5 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_5_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_5_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_5_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_5_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_5_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_5_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_5_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_5 - EBI CS Config 5 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_5 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_5_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_5_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_5_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_5_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_5_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_5_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_5 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_5_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_5_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_5_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_5 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_5_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_5_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_5_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_5_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_5_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_5_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_5_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_5_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_5_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_5 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_5_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_5_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_5_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_5 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_5_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_5_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_5_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_5 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_5_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_5_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_5_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_5 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_5_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_5_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_5_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_5 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_5_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_5_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_5_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_5 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_5_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_5_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_5_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_5 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_5_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_5_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_5_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_5 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_5_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_5_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_5_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_5 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_5_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_5_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_5_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_5_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_5_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_5_enable_DEFAULT                        0
+
+/***************************************************************************
+ *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_0_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_0_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_0 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_0_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_0_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_0_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_0_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_0_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_1_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_1_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_1 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_1_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_1_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_1_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_1_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_1_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_2_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_2_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_2 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_2_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_2_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_2_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_2_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_2_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_3_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_3_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_3 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_3_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_3_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_3_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_3_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_3_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_4_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_4_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_4 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_4_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_4_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_4_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_4_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_4_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_5 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_5 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_5 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_5_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_5_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_5_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_5 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_5 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_5 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_5 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_5_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_5_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_5 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_5 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_5_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_5_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_5_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_5 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_5 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_5 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_5_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_5_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_5 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_5_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_5_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_5_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_5 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_5_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_5_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_5 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_5_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_5_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_5_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_5 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_5_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_5_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_5_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *ECR - EBI Configuration Register
+ ***************************************************************************/
+/* EBI :: ECR :: reserved0 [31:28] */
+#define BCHP_EBI_ECR_reserved0_MASK                                0xf0000000
+#define BCHP_EBI_ECR_reserved0_SHIFT                               28
+
+/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK                            0x08000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT                           27
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT                         0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only  1
+
+/* EBI :: ECR :: reserved1 [26:26] */
+#define BCHP_EBI_ECR_reserved1_MASK                                0x04000000
+#define BCHP_EBI_ECR_reserved1_SHIFT                               26
+
+/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK                          0x02000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT                         25
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT                       0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10         0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00         1
+
+/* EBI :: ECR :: reserved2 [24:11] */
+#define BCHP_EBI_ECR_reserved2_MASK                                0x01fff800
+#define BCHP_EBI_ECR_reserved2_SHIFT                               11
+
+/* EBI :: ECR :: timeout_count [10:00] */
+#define BCHP_EBI_ECR_timeout_count_MASK                            0x000007ff
+#define BCHP_EBI_ECR_timeout_count_SHIFT                           0
+#define BCHP_EBI_ECR_timeout_count_DEFAULT                         1024
+
+/***************************************************************************
+ *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
+ ***************************************************************************/
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK             0x80000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT            31
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK             0x40000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT            30
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK             0x20000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT            29
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK             0x10000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT            28
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK            0x08000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT           27
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT         0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK            0x04000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT           26
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT         0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK         0x02000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT        25
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT      0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK         0x01000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT        24
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT      0
+
+/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:06] */
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK                    0x00ffffc0
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT                   6
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs5 [05:05] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_MASK             0x00000020
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_SHIFT            5
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK             0x00000010
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT            4
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK             0x00000008
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT            3
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK             0x00000004
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT            2
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK             0x00000002
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT            1
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK             0x00000001
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT            0
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT          0
+
+/***************************************************************************
+ *TA_CFG - EBI TA Configuration Register
+ ***************************************************************************/
+/* EBI :: TA_CFG :: reserved0 [31:04] */
+#define BCHP_EBI_TA_CFG_reserved0_MASK                             0xfffffff0
+#define BCHP_EBI_TA_CFG_reserved0_SHIFT                            4
+
+/* EBI :: TA_CFG :: use_ta3 [03:03] */
+#define BCHP_EBI_TA_CFG_use_ta3_MASK                               0x00000008
+#define BCHP_EBI_TA_CFG_use_ta3_SHIFT                              3
+#define BCHP_EBI_TA_CFG_use_ta3_DEFAULT                            1
+
+/* EBI :: TA_CFG :: use_ta2 [02:02] */
+#define BCHP_EBI_TA_CFG_use_ta2_MASK                               0x00000004
+#define BCHP_EBI_TA_CFG_use_ta2_SHIFT                              2
+#define BCHP_EBI_TA_CFG_use_ta2_DEFAULT                            0
+
+/* EBI :: TA_CFG :: use_ta1 [01:01] */
+#define BCHP_EBI_TA_CFG_use_ta1_MASK                               0x00000002
+#define BCHP_EBI_TA_CFG_use_ta1_SHIFT                              1
+#define BCHP_EBI_TA_CFG_use_ta1_DEFAULT                            1
+
+/* EBI :: TA_CFG :: reserved1 [00:00] */
+#define BCHP_EBI_TA_CFG_reserved1_MASK                             0x00000001
+#define BCHP_EBI_TA_CFG_reserved1_SHIFT                            0
+
+/***************************************************************************
+ *CS_SPI_SELECT - SPI CS Select
+ ***************************************************************************/
+/* EBI :: CS_SPI_SELECT :: reserved0 [31:16] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK                      0xffff0000
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT                     16
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_7_USES_SPI [15:15] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_MASK              0x00008000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_SHIFT             15
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK              0x00004000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT             14
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK              0x00002000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT             13
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK              0x00001000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT             12
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK              0x00000800
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT             11
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK              0x00000400
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT             10
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK              0x00000200
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT             9
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK              0x00000100
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT             8
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_7_SEL [07:07] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_MASK               0x00000080
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_SHIFT              7
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK               0x00000040
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT              6
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK               0x00000020
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT              5
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK               0x00000010
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT              4
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK               0x00000008
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT              3
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK               0x00000004
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT              2
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK               0x00000002
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT              1
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK               0x00000001
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT              0
+
+/***************************************************************************
+ *ARRAY_ADDRESS - EBI Data Array Address
+ ***************************************************************************/
+/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK                        0xfffffe00
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT                       9
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT                     0
+
+/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK                      0x000001f8
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT                     3
+
+/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK                         0x00000007
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT                        0
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT                      0
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE                            0x00000a00
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_START                           0
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_END                             127
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE                    32
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+/* EBI :: DATA_ARRAYi :: WORD [31:00] */
+#define BCHP_EBI_DATA_ARRAYi_WORD_MASK                             0xffffffff
+#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT                            0
+
+
+#endif /* #ifndef BCHP_EBI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_hif_cpu_intr1.h b/include/linux/brcmstb/7344b0/bchp_hif_cpu_intr1.h
new file mode 100644
index 0000000..43318e8
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_hif_cpu_intr1.h
@@ -0,0 +1,1855 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:48:39 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_hif_cpu_intr1.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 1:30p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_INTR1_H__
+#define BCHP_HIF_CPU_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_INTR1 - HIF CPU Thread Processor 0 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS        0x00001400 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS        0x00001404 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS        0x00001408 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS   0x0000140c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS   0x00001410 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS   0x00001414 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET      0x00001418 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET      0x0000141c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET      0x00001420 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR    0x00001424 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR    0x00001428 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR    0x0000142c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: FTM_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_MASK        0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_SHIFT       29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_20_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_20_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_20_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_20_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_19_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_19_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_19_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_19_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_18_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_18_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_18_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_18_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_17_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_17_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_17_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_17_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_16_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_16_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_16_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_16_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_15_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_15_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_15_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_15_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK     0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT    7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK     0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT    6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK     0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT    5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK     0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT    4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK     0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT    3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK     0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT    2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK        0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT       1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK        0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT       0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT     0
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK    0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT   31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK     0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT    29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK    0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT   25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_MASK        0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_SHIFT       22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK     0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT    21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK    0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT   20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK        0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT       19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_MASK     0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_SHIFT    18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_MASK  0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_MASK  0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK   0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT  12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK      0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT     11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT   0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK    0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT   10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: MOCA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_MASK       0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_SHIFT      9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_DEFAULT    0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: MEMC0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_MASK      0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_SHIFT     8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_DEFAULT   0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_MASK       0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_SHIFT      7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_DEFAULT    0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_MASK       0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_SHIFT      6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_DEFAULT    0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: HIF_SPI_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_HIF_SPI_CPU_INTR_MASK    0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_HIF_SPI_CPU_INTR_SHIFT   5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: HIF_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_HIF_CPU_INTR_MASK        0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_HIF_CPU_INTR_SHIFT       4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_HIF_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: HDMI_TX_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_HDMI_TX_CPU_INTR_MASK    0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_HDMI_TX_CPU_INTR_SHIFT   3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: GFX_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_GFX_CPU_INTR_MASK        0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_GFX_CPU_INTR_SHIFT       2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_GFX_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: GENET_1_B_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_GENET_1_B_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_GENET_1_B_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: GENET_1_A_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_GENET_1_A_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_GENET_1_A_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved0_MASK           0xff800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved0_SHIFT          23
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_MASK     0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_SHIFT    22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_MASK    0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_SHIFT   21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK    0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT   19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK    0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT   18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK   0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT  17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK    0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT   15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK     0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT    14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK        0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT       13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: FTM_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_MASK   0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_SHIFT  29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_20_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_20_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_20_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_20_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_19_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_19_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_19_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_19_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_18_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_18_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_18_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_18_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_17_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_17_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_17_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_17_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_16_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_16_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_16_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_16_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_15_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_15_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_15_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_15_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_MASK   0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_SHIFT  22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: MOCA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_MASK  0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: MEMC0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_MASK  0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_MASK  0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: HIF_SPI_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: HIF_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_HIF_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_HIF_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: HDMI_TX_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: GFX_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_GFX_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_GFX_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: GENET_1_B_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_GENET_1_B_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_GENET_1_B_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: GENET_1_A_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_GENET_1_A_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_GENET_1_A_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved0_MASK      0xff800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved0_SHIFT     23
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK   0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT  13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: FTM_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_MASK      0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_SHIFT     29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_20_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_20_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_20_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_20_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_19_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_19_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_19_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_19_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_18_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_18_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_18_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_18_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_17_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_17_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_17_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_17_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_16_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_16_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_16_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_16_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_15_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_15_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_15_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_15_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK      0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT     1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK      0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT     0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT   1
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK   0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT  29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK  0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_MASK  0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_MASK      0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_SHIFT     22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK   0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT  21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK  0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK      0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT     19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_MASK   0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_SHIFT  18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK    0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT   11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK  0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: MOCA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_MASK     0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_SHIFT    9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_DEFAULT  1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: MEMC0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_MASK    0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_SHIFT   8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_MASK     0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_SHIFT    7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_DEFAULT  1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_MASK     0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_SHIFT    6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_DEFAULT  1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: HIF_SPI_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_HIF_SPI_CPU_INTR_MASK  0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: HIF_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_HIF_CPU_INTR_MASK      0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_HIF_CPU_INTR_SHIFT     4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_HIF_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: HDMI_TX_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_HDMI_TX_CPU_INTR_MASK  0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: GFX_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_GFX_CPU_INTR_MASK      0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_GFX_CPU_INTR_SHIFT     2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_GFX_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: GENET_1_B_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_GENET_1_B_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_GENET_1_B_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: GENET_1_A_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_GENET_1_A_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_GENET_1_A_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved0_MASK         0xff800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved0_SHIFT        23
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_MASK   0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_SHIFT  22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_MASK  0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK  0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK  0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK  0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK   0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT  14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK      0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT     13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: FTM_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_MASK    0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_SHIFT   29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_20_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_20_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_20_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_20_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_19_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_19_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_19_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_19_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_18_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_18_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_18_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_18_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_17_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_17_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_17_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_17_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_16_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_16_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_16_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_16_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_15_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_15_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_15_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_15_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_MASK    0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_SHIFT   22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK    0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT   19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK  0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: MOCA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_MASK   0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_SHIFT  9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: MEMC0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_MASK  0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: HIF_SPI_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: HIF_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_HIF_CPU_INTR_MASK    0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_HIF_CPU_INTR_SHIFT   4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: HDMI_TX_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: GFX_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_GFX_CPU_INTR_MASK    0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_GFX_CPU_INTR_SHIFT   2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: GENET_1_B_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_GENET_1_B_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_GENET_1_B_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: GENET_1_A_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_GENET_1_A_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_GENET_1_A_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved0_MASK       0xff800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved0_SHIFT      23
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK    0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT   13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 1
+
+#endif /* #ifndef BCHP_HIF_CPU_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_hif_cpu_tp1_intr1.h b/include/linux/brcmstb/7344b0/bchp_hif_cpu_tp1_intr1.h
new file mode 100644
index 0000000..269f9c4
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_hif_cpu_tp1_intr1.h
@@ -0,0 +1,1855 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:39:29 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_hif_cpu_tp1_intr1.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 1:31p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_TP1_INTR1_H__
+#define BCHP_HIF_CPU_TP1_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_TP1_INTR1 - HIF CPU Thread Processor 1 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS    0x00001600 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS    0x00001604 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS    0x00001608 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS 0x0000160c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS 0x00001610 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS 0x00001614 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET  0x00001618 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET  0x0000161c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET  0x00001620 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR 0x00001624 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR 0x00001628 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR 0x0000162c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: FTM_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_MASK    0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_SHIFT   29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_20_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_20_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_20_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_20_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_19_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_19_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_19_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_19_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_18_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_18_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_18_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_18_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_17_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_17_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_17_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_17_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_16_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_16_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_16_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_16_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_15_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_15_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_15_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_15_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_MASK    0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_SHIFT   22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK    0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT   19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK  0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: MOCA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_MASK   0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_SHIFT  9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: MEMC0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_MASK  0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: IPI1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: IPI0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: HIF_SPI_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_HIF_SPI_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_HIF_SPI_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: HIF_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_HIF_CPU_INTR_MASK    0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_HIF_CPU_INTR_SHIFT   4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_HIF_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: HDMI_TX_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_HDMI_TX_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_HDMI_TX_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: GFX_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_GFX_CPU_INTR_MASK    0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_GFX_CPU_INTR_SHIFT   2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_GFX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: GENET_1_B_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_GENET_1_B_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_GENET_1_B_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: GENET_1_A_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_GENET_1_A_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_GENET_1_A_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_reserved0_MASK       0xff800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_reserved0_SHIFT      23
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK    0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT   13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: FTM_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_20_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_20_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_20_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_20_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_19_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_19_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_19_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_19_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_18_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_18_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_18_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_18_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_17_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_17_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_17_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_17_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_16_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_16_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_16_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_16_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_15_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_15_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_15_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_15_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: MOCA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: MEMC0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: IPI1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: IPI0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: HIF_SPI_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: HIF_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_HIF_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_HIF_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: HDMI_TX_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: GFX_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_GFX_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_GFX_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: GENET_1_B_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_GENET_1_B_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_GENET_1_B_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: GENET_1_A_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_GENET_1_A_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_GENET_1_A_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_reserved0_MASK  0xff800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_reserved0_SHIFT 23
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: FTM_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_20_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_20_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_20_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_20_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_19_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_19_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_19_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_19_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_18_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_18_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_18_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_18_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_17_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_17_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_17_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_17_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_16_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_16_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_16_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_16_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_15_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_15_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_15_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_15_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_MASK  0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK  0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: MOCA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: MEMC0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: IPI1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: IPI0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: HIF_SPI_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_HIF_SPI_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: HIF_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_HIF_CPU_INTR_MASK  0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_HIF_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: HDMI_TX_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_HDMI_TX_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: GFX_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_GFX_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_GFX_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: GENET_1_B_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_GENET_1_B_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_GENET_1_B_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: GENET_1_A_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_GENET_1_A_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_GENET_1_A_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_reserved0_MASK     0xff800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_reserved0_SHIFT    23
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK  0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: FTM_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_20_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_20_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_20_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_20_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_19_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_19_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_19_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_19_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_18_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_18_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_18_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_18_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_17_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_17_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_17_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_17_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_16_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_16_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_16_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_16_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_15_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_15_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_15_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_15_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: MOCA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: MEMC0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: IPI1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: IPI0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: HIF_SPI_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: HIF_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_HIF_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_HIF_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: HDMI_TX_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: GFX_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_GFX_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_GFX_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: GENET_1_B_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_GENET_1_B_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_GENET_1_B_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: GENET_1_A_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_GENET_1_A_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_GENET_1_A_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_reserved0_MASK   0xff800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_reserved0_SHIFT  23
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 1
+
+#endif /* #ifndef BCHP_HIF_CPU_TP1_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_hif_intr2.h b/include/linux/brcmstb/7344b0/bchp_hif_intr2.h
new file mode 100644
index 0000000..6002a99
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_hif_intr2.h
@@ -0,0 +1,1035 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:42:23 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_hif_intr2.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 1:31p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_INTR2_H__
+#define BCHP_HIF_INTR2_H__
+
+/***************************************************************************
+ *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_INTR2_CPU_STATUS                0x00001000 /* CPU interrupt Status Register */
+#define BCHP_HIF_INTR2_CPU_SET                   0x00001004 /* CPU interrupt Set Register */
+#define BCHP_HIF_INTR2_CPU_CLEAR                 0x00001008 /* CPU interrupt Clear Register */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS           0x0000100c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_CPU_MASK_SET              0x00001010 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR            0x00001014 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_INTR2_PCI_STATUS                0x00001018 /* PCI interrupt Status Register */
+#define BCHP_HIF_INTR2_PCI_SET                   0x0000101c /* PCI interrupt Set Register */
+#define BCHP_HIF_INTR2_PCI_CLEAR                 0x00001020 /* PCI interrupt Clear Register */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS           0x00001024 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_PCI_MASK_SET              0x00001028 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR            0x0000102c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_MASK          0x00080000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_SHIFT         19
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_DEFAULT       0
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_MASK          0x00008000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_SHIFT         15
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_DEFAULT       0
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK                   0x00007ffe
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT               0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_MASK             0x00080000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_SHIFT            19
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_MASK             0x00008000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_SHIFT            15
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_SET :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK                      0x00007ffe
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: CPU_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_MASK           0x00008000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_SHIFT          15
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK                    0x00007ffe
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_MASK     0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_SHIFT    19
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_DEFAULT  1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_MASK     0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_SHIFT    15
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_DEFAULT  1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK              0x00007ffe
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 1
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT          1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_MASK        0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_SHIFT       19
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_MASK        0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_SHIFT       15
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK                 0x00007ffe
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    1
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_MASK      0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_SHIFT     15
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK               0x00007ffe
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  1
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_MASK          0x00080000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_SHIFT         19
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_DEFAULT       0
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_MASK          0x00008000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_SHIFT         15
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_DEFAULT       0
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK                   0x00007ffe
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT               0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_MASK             0x00080000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_SHIFT            19
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_MASK             0x00008000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_SHIFT            15
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_SET :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK                      0x00007ffe
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: PCI_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_MASK           0x00008000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_SHIFT          15
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK                    0x00007ffe
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_MASK     0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_SHIFT    19
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_DEFAULT  1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_MASK     0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_SHIFT    15
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_DEFAULT  1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK              0x00007ffe
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 1
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT          1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_MASK        0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_SHIFT       19
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_MASK        0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_SHIFT       15
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK                 0x00007ffe
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    1
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_MASK      0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_SHIFT     15
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK               0x00007ffe
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  1
+
+#endif /* #ifndef BCHP_HIF_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_hif_mspi.h b/include/linux/brcmstb/7344b0/bchp_hif_mspi.h
new file mode 100644
index 0000000..28cf295
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_hif_mspi.h
@@ -0,0 +1,1214 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:44:34 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_hif_mspi.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 1:31p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_MSPI_H__
+#define BCHP_HIF_MSPI_H__
+
+/***************************************************************************
+ *HIF_MSPI - Public MSPI Registers
+ ***************************************************************************/
+#define BCHP_HIF_MSPI_SPCR0_LSB                  0x00003200 /* SPCR0_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR0_MSB                  0x00003204 /* SPCR0_MSB Register */
+#define BCHP_HIF_MSPI_SPCR1_LSB                  0x00003208 /* SPCR1_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR1_MSB                  0x0000320c /* SPCR1_MSB REGISTER */
+#define BCHP_HIF_MSPI_NEWQP                      0x00003210 /* NEWQP REGISTER */
+#define BCHP_HIF_MSPI_ENDQP                      0x00003214 /* ENDQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR2                      0x00003218 /* SPCR2 REGISTER */
+#define BCHP_HIF_MSPI_MSPI_STATUS                0x00003220 /* MSPI STATUS REGISTER */
+#define BCHP_HIF_MSPI_CPTQP                      0x00003224 /* CPTQP REGISTER */
+#define BCHP_HIF_MSPI_TXRAM00                    0x00003240 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM01                    0x00003244 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM02                    0x00003248 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM03                    0x0000324c /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM04                    0x00003250 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM05                    0x00003254 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM06                    0x00003258 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM07                    0x0000325c /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM08                    0x00003260 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM09                    0x00003264 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM10                    0x00003268 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM11                    0x0000326c /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM12                    0x00003270 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM13                    0x00003274 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM14                    0x00003278 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM15                    0x0000327c /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM16                    0x00003280 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM17                    0x00003284 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM18                    0x00003288 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM19                    0x0000328c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM20                    0x00003290 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM21                    0x00003294 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM22                    0x00003298 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM23                    0x0000329c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM24                    0x000032a0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM25                    0x000032a4 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM26                    0x000032a8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM27                    0x000032ac /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM28                    0x000032b0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM29                    0x000032b4 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM30                    0x000032b8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_TXRAM31                    0x000032bc /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM00                    0x000032c0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM01                    0x000032c4 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM02                    0x000032c8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM03                    0x000032cc /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM04                    0x000032d0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM05                    0x000032d4 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM06                    0x000032d8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM07                    0x000032dc /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM08                    0x000032e0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM09                    0x000032e4 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM10                    0x000032e8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM11                    0x000032ec /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM12                    0x000032f0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM13                    0x000032f4 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM14                    0x000032f8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM15                    0x000032fc /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM16                    0x00003300 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM17                    0x00003304 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM18                    0x00003308 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM19                    0x0000330c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM20                    0x00003310 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM21                    0x00003314 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM22                    0x00003318 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM23                    0x0000331c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM24                    0x00003320 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM25                    0x00003324 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM26                    0x00003328 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM27                    0x0000332c /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM28                    0x00003330 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM29                    0x00003334 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM30                    0x00003338 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM31                    0x0000333c /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_CDRAM00                    0x00003340 /* 8-bit command (queue pointer = 0) */
+#define BCHP_HIF_MSPI_CDRAM01                    0x00003344 /* 8-bit command (queue pointer = 1) */
+#define BCHP_HIF_MSPI_CDRAM02                    0x00003348 /* 8-bit command (queue pointer = 2) */
+#define BCHP_HIF_MSPI_CDRAM03                    0x0000334c /* 8-bit command (queue pointer = 3) */
+#define BCHP_HIF_MSPI_CDRAM04                    0x00003350 /* 8-bit command (queue pointer = 4) */
+#define BCHP_HIF_MSPI_CDRAM05                    0x00003354 /* 8-bit command (queue pointer = 5) */
+#define BCHP_HIF_MSPI_CDRAM06                    0x00003358 /* 8-bit command (queue pointer = 6) */
+#define BCHP_HIF_MSPI_CDRAM07                    0x0000335c /* 8-bit command (queue pointer = 7) */
+#define BCHP_HIF_MSPI_CDRAM08                    0x00003360 /* 8-bit command (queue pointer = 8) */
+#define BCHP_HIF_MSPI_CDRAM09                    0x00003364 /* 8-bit command (queue pointer = 9) */
+#define BCHP_HIF_MSPI_CDRAM10                    0x00003368 /* 8-bit command (queue pointer = a) */
+#define BCHP_HIF_MSPI_CDRAM11                    0x0000336c /* 8-bit command (queue pointer = b) */
+#define BCHP_HIF_MSPI_CDRAM12                    0x00003370 /* 8-bit command (queue pointer = c) */
+#define BCHP_HIF_MSPI_CDRAM13                    0x00003374 /* 8-bit command (queue pointer = d) */
+#define BCHP_HIF_MSPI_CDRAM14                    0x00003378 /* 8-bit command (queue pointer = e) */
+#define BCHP_HIF_MSPI_CDRAM15                    0x0000337c /* 8-bit command (queue pointer = f) */
+#define BCHP_HIF_MSPI_WRITE_LOCK                 0x00003380 /* Control bit to lock group of write commands */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN          0x00003384 /* Debug bit to mask the generation of flush signals from Mspi */
+
+/***************************************************************************
+ *SPCR0_LSB - SPCR0_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK                          0x000000ff
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT                       0
+
+/***************************************************************************
+ *SPCR0_MSB - SPCR0_MSB Register
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_MSB :: MSTR [07:07] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_MASK                          0x00000080
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_SHIFT                         7
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_DEFAULT                       1
+
+/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [06:06] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK               0x00000040
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT              6
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT            0
+
+/* HIF_MSPI :: SPCR0_MSB :: BitS [05:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_MASK                          0x0000003c
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_SHIFT                         2
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_DEFAULT                       0
+
+/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK                          0x00000002
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT                         1
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT                       0
+
+/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK                          0x00000001
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT                       0
+
+/***************************************************************************
+ *SPCR1_LSB - SPCR1_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT                          0
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT                        0
+
+/***************************************************************************
+ *SPCR1_MSB - SPCR1_MSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK                        0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT                       0
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT                     0
+
+/***************************************************************************
+ *NEWQP - NEWQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: NEWQP :: newqp [03:00] */
+#define BCHP_HIF_MSPI_NEWQP_newqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT                            0
+#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT                          0
+
+/***************************************************************************
+ *ENDQP - ENDQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: ENDQP :: endqp [03:00] */
+#define BCHP_HIF_MSPI_ENDQP_endqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT                            0
+#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT                          0
+
+/***************************************************************************
+ *SPCR2 - SPCR2 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK                         0xffffff00
+#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT                        8
+
+/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK                    0x00000080
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT                   7
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT                 0
+
+/* HIF_MSPI :: SPCR2 :: spe [06:06] */
+#define BCHP_HIF_MSPI_SPCR2_spe_MASK                               0x00000040
+#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT                              6
+#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT                            0
+
+/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
+#define BCHP_HIF_MSPI_SPCR2_spifie_MASK                            0x00000020
+#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT                           5
+#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT                         0
+
+/* HIF_MSPI :: SPCR2 :: wren [04:04] */
+#define BCHP_HIF_MSPI_SPCR2_wren_MASK                              0x00000010
+#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT                             4
+#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT                           0
+
+/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
+#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK                              0x00000008
+#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT                             3
+#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT                           0
+
+/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
+#define BCHP_HIF_MSPI_SPCR2_loopq_MASK                             0x00000004
+#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT                            2
+#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT                          0
+
+/* HIF_MSPI :: SPCR2 :: hie [01:01] */
+#define BCHP_HIF_MSPI_SPCR2_hie_MASK                               0x00000002
+#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT                              1
+#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT                            0
+
+/* HIF_MSPI :: SPCR2 :: halt [00:00] */
+#define BCHP_HIF_MSPI_SPCR2_halt_MASK                              0x00000001
+#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT                             0
+#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT                           0
+
+/***************************************************************************
+ *MSPI_STATUS - MSPI STATUS REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK                   0xfffffffc
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT                  2
+
+/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK                       0x00000002
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT                      1
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT                    0
+
+/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK                        0x00000001
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT                       0
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT                     0
+
+/***************************************************************************
+ *CPTQP - CPTQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
+#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT                            0
+#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT                          0
+
+/***************************************************************************
+ *TXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM00_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM01_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM02_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM03_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM04_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM05_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM06_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM07_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM08_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM09_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM10_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM11_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM12_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM13_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM14_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM15_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM16_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM17_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM18_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM19_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM20_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM21_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM22_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM23_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM24_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM25_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM26_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM27_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM28_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM29_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM30_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM31_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM00 - 8-bit command (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM00 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM01 - 8-bit command (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM01 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM02 - 8-bit command (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM02 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM03 - 8-bit command (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM03 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM04 - 8-bit command (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM04 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM05 - 8-bit command (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM05 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM06 - 8-bit command (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM06 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM07 - 8-bit command (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM07 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM08 - 8-bit command (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM08 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM09 - 8-bit command (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM09 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM10 - 8-bit command (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM10 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM11 - 8-bit command (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM11 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM12 - 8-bit command (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM12 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM13 - 8-bit command (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM13 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM14 - 8-bit command (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM14 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM15 - 8-bit command (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM15 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT                          0
+
+/***************************************************************************
+ *WRITE_LOCK - Control bit to lock group of write commands
+ ***************************************************************************/
+/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK                    0xfffffffe
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT                   1
+
+/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK                    0x00000001
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT                   0
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT                 0
+
+/***************************************************************************
+ *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
+ ***************************************************************************/
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK             0xfffffffe
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT            1
+
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK       0x00000001
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT      0
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT    0
+
+#endif /* #ifndef BCHP_HIF_MSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/7344b0/bchp_hif_spi_intr2.h
new file mode 100644
index 0000000..23109e8
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_hif_spi_intr2.h
@@ -0,0 +1,567 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:30:07 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_hif_spi_intr2.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 1:32p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_SPI_INTR2_H__
+#define BCHP_HIF_SPI_INTR2_H__
+
+/***************************************************************************
+ *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
+ ***************************************************************************/
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS            0x00001d00 /* CPU interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_SET               0x00001d04 /* CPU interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR             0x00001d08 /* CPU interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS       0x00001d0c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET          0x00001d10 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR        0x00001d14 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS            0x00001d18 /* PCI interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_SET               0x00001d1c /* PCI interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR             0x00001d20 /* PCI interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS       0x00001d24 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET          0x00001d28 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR        0x00001d2c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT            0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT               0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT         0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT           0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT            0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT               0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT         0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT           0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_irq0.h b/include/linux/brcmstb/7344b0/bchp_irq0.h
new file mode 100644
index 0000000..797dc35
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_irq0.h
@@ -0,0 +1,217 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Sep 16 19:16:14 2011
+ *                 MD5 Checksum         823a10b379073d7995e16a4f32a03392
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_irq0.h $
+ * 
+ * Hydra_Software_Devel/2   9/19/11 4:07p pntruong
+ * SW7425-1183: Added new int id and synced with central RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ0_H__
+#define BCHP_IRQ0_H__
+
+/***************************************************************************
+ *IRQ0 - Level 2 CPU Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ0_IRQEN                          0x00406780 /* Interrupt Enable */
+#define BCHP_IRQ0_IRQSTAT                        0x00406784 /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ0 :: IRQEN :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQEN_reserved0_MASK                             0xf8000000
+#define BCHP_IRQ0_IRQEN_reserved0_SHIFT                            27
+
+/* IRQ0 :: IRQEN :: iicd_irqen [26:26] */
+#define BCHP_IRQ0_IRQEN_iicd_irqen_MASK                            0x04000000
+#define BCHP_IRQ0_IRQEN_iicd_irqen_SHIFT                           26
+#define BCHP_IRQ0_IRQEN_iicd_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: iicb_irqen [25:25] */
+#define BCHP_IRQ0_IRQEN_iicb_irqen_MASK                            0x02000000
+#define BCHP_IRQ0_IRQEN_iicb_irqen_SHIFT                           25
+#define BCHP_IRQ0_IRQEN_iicb_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: iica_irqen [24:24] */
+#define BCHP_IRQ0_IRQEN_iica_irqen_MASK                            0x01000000
+#define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT                           24
+#define BCHP_IRQ0_IRQEN_iica_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQEN_reserved1_MASK                             0x00f80000
+#define BCHP_IRQ0_IRQEN_reserved1_SHIFT                            19
+
+/* IRQ0 :: IRQEN :: uartc_irqen [18:18] */
+#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK                           0x00040000
+#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT                          18
+#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: uartb_irqen [17:17] */
+#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK                           0x00020000
+#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT                          17
+#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: uarta_irqen [16:16] */
+#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK                           0x00010000
+#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT                          16
+#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQEN_reserved2_MASK                             0x0000fc00
+#define BCHP_IRQ0_IRQEN_reserved2_SHIFT                            10
+
+/* IRQ0 :: IRQEN :: uc_irqen [09:09] */
+#define BCHP_IRQ0_IRQEN_uc_irqen_MASK                              0x00000200
+#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT                             9
+#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQEN_reserved3_MASK                             0x00000180
+#define BCHP_IRQ0_IRQEN_reserved3_SHIFT                            7
+
+/* IRQ0 :: IRQEN :: gio_irqen [06:06] */
+#define BCHP_IRQ0_IRQEN_gio_irqen_MASK                             0x00000040
+#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT                            6
+#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT                          0
+
+/* IRQ0 :: IRQEN :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQEN_reserved4_MASK                             0x00000020
+#define BCHP_IRQ0_IRQEN_reserved4_SHIFT                            5
+
+/* IRQ0 :: IRQEN :: ua_irqen [04:04] */
+#define BCHP_IRQ0_IRQEN_ua_irqen_MASK                              0x00000010
+#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT                             4
+#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: ub_irqen [03:03] */
+#define BCHP_IRQ0_IRQEN_ub_irqen_MASK                              0x00000008
+#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT                             3
+#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: irb_irqen [02:02] */
+#define BCHP_IRQ0_IRQEN_irb_irqen_MASK                             0x00000004
+#define BCHP_IRQ0_IRQEN_irb_irqen_SHIFT                            2
+#define BCHP_IRQ0_IRQEN_irb_irqen_DEFAULT                          0
+
+/* IRQ0 :: IRQEN :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQEN_reserved5_MASK                             0x00000003
+#define BCHP_IRQ0_IRQEN_reserved5_SHIFT                            0
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ0 :: IRQSTAT :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQSTAT_reserved0_MASK                           0xf8000000
+#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT                          27
+
+/* IRQ0 :: IRQSTAT :: iicdirq [26:26] */
+#define BCHP_IRQ0_IRQSTAT_iicdirq_MASK                             0x04000000
+#define BCHP_IRQ0_IRQSTAT_iicdirq_SHIFT                            26
+#define BCHP_IRQ0_IRQSTAT_iicdirq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: iicbirq [25:25] */
+#define BCHP_IRQ0_IRQSTAT_iicbirq_MASK                             0x02000000
+#define BCHP_IRQ0_IRQSTAT_iicbirq_SHIFT                            25
+#define BCHP_IRQ0_IRQSTAT_iicbirq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: iicairq [24:24] */
+#define BCHP_IRQ0_IRQSTAT_iicairq_MASK                             0x01000000
+#define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT                            24
+#define BCHP_IRQ0_IRQSTAT_iicairq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQSTAT_reserved1_MASK                           0x00f80000
+#define BCHP_IRQ0_IRQSTAT_reserved1_SHIFT                          19
+
+/* IRQ0 :: IRQSTAT :: uartc_irq [18:18] */
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK                           0x00040000
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT                          18
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: uartb_irq [17:17] */
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK                           0x00020000
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT                          17
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: uarta_irq [16:16] */
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK                           0x00010000
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT                          16
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQSTAT_reserved2_MASK                           0x0000fc00
+#define BCHP_IRQ0_IRQSTAT_reserved2_SHIFT                          10
+
+/* IRQ0 :: IRQSTAT :: ucirq [09:09] */
+#define BCHP_IRQ0_IRQSTAT_ucirq_MASK                               0x00000200
+#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT                              9
+#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQSTAT_reserved3_MASK                           0x00000180
+#define BCHP_IRQ0_IRQSTAT_reserved3_SHIFT                          7
+
+/* IRQ0 :: IRQSTAT :: gioirq [06:06] */
+#define BCHP_IRQ0_IRQSTAT_gioirq_MASK                              0x00000040
+#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT                             6
+#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT                           0
+
+/* IRQ0 :: IRQSTAT :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQSTAT_reserved4_MASK                           0x00000020
+#define BCHP_IRQ0_IRQSTAT_reserved4_SHIFT                          5
+
+/* IRQ0 :: IRQSTAT :: uairq [04:04] */
+#define BCHP_IRQ0_IRQSTAT_uairq_MASK                               0x00000010
+#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT                              4
+#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: ubirq [03:03] */
+#define BCHP_IRQ0_IRQSTAT_ubirq_MASK                               0x00000008
+#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT                              3
+#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: irbirq [02:02] */
+#define BCHP_IRQ0_IRQSTAT_irbirq_MASK                              0x00000004
+#define BCHP_IRQ0_IRQSTAT_irbirq_SHIFT                             2
+#define BCHP_IRQ0_IRQSTAT_irbirq_DEFAULT                           0
+
+/* IRQ0 :: IRQSTAT :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQSTAT_reserved5_MASK                           0x00000003
+#define BCHP_IRQ0_IRQSTAT_reserved5_SHIFT                          0
+
+#endif /* #ifndef BCHP_IRQ0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_irq1.h b/include/linux/brcmstb/7344b0/bchp_irq1.h
new file mode 100644
index 0000000..7df0bdc
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_irq1.h
@@ -0,0 +1,50 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri May 21 13:08:30 2010
+ *                 MD5 Checksum         34dd0d3bbf3478606c423cca67439a45
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ1_H__
+#define BCHP_IRQ1_H__
+
+/***************************************************************************
+ *IRQ1 - Level 2 PCI Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ1_IRQEN                          0x00406788 /* Interrupt Enable */
+#define BCHP_IRQ1_IRQSTAT                        0x0040678c /* Interrupt Status */
+
+#endif /* #ifndef BCHP_IRQ1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_mem_dma_0.h b/include/linux/brcmstb/7344b0/bchp_mem_dma_0.h
new file mode 100644
index 0000000..68e7759
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_mem_dma_0.h
@@ -0,0 +1,157 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 31 14:10:42 2011
+ *                 MD5 Checksum         b0a0062767e487fe78d25d07b5b21b78
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_mem_dma_0.h $
+ * 
+ * Hydra_Software_Devel/2   5/31/11 3:25p albertl
+ * SW7344-40: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEM_DMA_0_H__
+#define BCHP_MEM_DMA_0_H__
+
+/***************************************************************************
+ *MEM_DMA_0 - MEM_DMA_0 Registers
+ ***************************************************************************/
+#define BCHP_MEM_DMA_0_REVISION                  0x000b4200 /* MEM_DMA REVISION */
+#define BCHP_MEM_DMA_0_FIRST_DESC                0x000b4204 /* MEM_DMA First Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CTRL                      0x000b4208 /* MEM_DMA Control Register */
+#define BCHP_MEM_DMA_0_WAKE_CTRL                 0x000b420c /* MEM_DMA Wake Control Register */
+#define BCHP_MEM_DMA_0_STATUS                    0x000b4214 /* MEM_DMA Status Register */
+#define BCHP_MEM_DMA_0_CUR_DESC                  0x000b4218 /* MEM_DMA Current Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CUR_BYTE                  0x000b421c /* MEM_DMA Current Byte Count Register */
+#define BCHP_MEM_DMA_0_SCRATCH                   0x000b4224 /* MEM_DMA Scratch Register */
+
+/***************************************************************************
+ *REVISION - MEM_DMA REVISION
+ ***************************************************************************/
+/* MEM_DMA_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_0_REVISION_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_0_REVISION_reserved0_SHIFT                    16
+
+/* MEM_DMA_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_MASK                         0x0000ff00
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_SHIFT                        8
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_DEFAULT                      2
+
+/* MEM_DMA_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_MEM_DMA_0_REVISION_MINOR_MASK                         0x000000ff
+#define BCHP_MEM_DMA_0_REVISION_MINOR_SHIFT                        0
+#define BCHP_MEM_DMA_0_REVISION_MINOR_DEFAULT                      10
+
+/***************************************************************************
+ *FIRST_DESC - MEM_DMA First Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: FIRST_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_MASK                        0xffffffff
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_SHIFT                       0
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_DEFAULT                     0
+
+/***************************************************************************
+ *CTRL - MEM_DMA Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CTRL :: reserved0 [31:01] */
+#define BCHP_MEM_DMA_0_CTRL_reserved0_MASK                         0xfffffffe
+#define BCHP_MEM_DMA_0_CTRL_reserved0_SHIFT                        1
+
+/* MEM_DMA_0 :: CTRL :: RUN [00:00] */
+#define BCHP_MEM_DMA_0_CTRL_RUN_MASK                               0x00000001
+#define BCHP_MEM_DMA_0_CTRL_RUN_SHIFT                              0
+#define BCHP_MEM_DMA_0_CTRL_RUN_DEFAULT                            0
+
+/***************************************************************************
+ *WAKE_CTRL - MEM_DMA Wake Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: WAKE_CTRL :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_MASK                    0xfffffffc
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_SHIFT                   2
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE_MODE [01:01] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_MASK                    0x00000002
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_SHIFT                   1
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_DEFAULT                 0
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE [00:00] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MASK                         0x00000001
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_SHIFT                        0
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_DEFAULT                      0
+
+/***************************************************************************
+ *STATUS - MEM_DMA Status Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: STATUS :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_MEM_DMA_0_STATUS_reserved0_SHIFT                      2
+
+/* MEM_DMA_0 :: STATUS :: DMA_STATUS [01:00] */
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_MASK                      0x00000003
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_SHIFT                     0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_DEFAULT                   0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Idle                      0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Busy                      1
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Sleep                     2
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Reserved                  3
+
+/***************************************************************************
+ *CUR_DESC - MEM_DMA Current Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_MASK                          0xffffffff
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_SHIFT                         0
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_DEFAULT                       0
+
+/***************************************************************************
+ *CUR_BYTE - MEM_DMA Current Byte Count Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_BYTE :: reserved0 [31:25] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_MASK                     0xfe000000
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_SHIFT                    25
+
+/* MEM_DMA_0 :: CUR_BYTE :: COUNT [24:00] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_MASK                         0x01ffffff
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_SHIFT                        0
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_DEFAULT                      0
+
+/***************************************************************************
+ *SCRATCH - MEM_DMA Scratch Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_MASK                    0xffffffff
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_SHIFT                   0
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_DEFAULT                 0
+
+#endif /* #ifndef BCHP_MEM_DMA_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_memc_ddr_0.h b/include/linux/brcmstb/7344b0/bchp_memc_ddr_0.h
new file mode 100644
index 0000000..e25d4b4
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_memc_ddr_0.h
@@ -0,0 +1,2665 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 17:09:42 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_memc_ddr_0.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 1:52p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR_0_H__
+#define BCHP_MEMC_DDR_0_H__
+
+/***************************************************************************
+ *MEMC_DDR_0 - Memory Controller Sequencer (DDR Param/Control) Registers 0
+ ***************************************************************************/
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG            0x00a02000 /* Memory Controller Mode-Configuration Register. */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL          0x00a02004 /* Dram iniitialization control */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS         0x00a02008 /* Dram iniitialization status */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0              0x00a0200c /* Dram Mode0 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1              0x00a02010 /* Dram Mode1 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2              0x00a02014 /* Dram Mode2 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3              0x00a02018 /* Dram Mode3 register */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG               0x00a0201c /* Precharge power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG              0x00a02020 /* Self-refresh power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SSPD_CMD                 0x00a02024 /* Software standby power down mode */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS        0x00a02028 /* Power down status */
+#define BCHP_MEMC_DDR_0_WARM_BOOT                0x00a0202c /* Warm boot control registers */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0            0x00a02030 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1            0x00a02034 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2            0x00a02038 /* Read to Write & write to read timing register */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3            0x00a0203c /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4            0x00a02040 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5            0x00a02044 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ         0x00a02048 /* Memory Controller Sequencer Enable */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT        0x00a0204c /* Memory Controller , state machine timeout register. */
+#define BCHP_MEMC_DDR_0_BANK_STATUS              0x00a02050 /* Memory Controller, Bank Status Register. */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY           0x00a02054 /* Memory Controller, Tester Latency Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0               0x00a02058 /* Memory Controller, DATA_PINMAP_BYTE0_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1               0x00a0205c /* Memory Controller, DATA_PINMAP_BYTE1_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2               0x00a02060 /* Memory Controller, DATA_PINMAP_BYTE2_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3               0x00a02064 /* Memory Controller, DATA_PINMAP_BYTE3_SEL Register. */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD   0x00a02068 /* Memory Controller, DDR3 DRAM reset Register. */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL             0x00a0206c /* Statistics Control register */
+#define BCHP_MEMC_DDR_0_STAT_TIMER               0x00a02070 /* Statistics Timer */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP            0x00a02074 /* DRAM Idle_NOP Cycle Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP        0x00a02078 /* Maximum DRAM idle_NOP cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL             0x00a0207c /* CAS Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL         0x00a02080 /* Maximum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL         0x00a02084 /* DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL 0x00a02088 /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL      0x00a0208c /* Number of overall system memory read transactions. */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL     0x00a02090 /* Number of overall system memory write transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL       0x00a02094 /* Maximum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL       0x00a02098 /* Minimum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS  0x00a0209c /* Service CAS Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS 0x00a020a0 /* Maximum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS 0x00a020a4 /* Minimum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY 0x00a020a8 /* Service Intra DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY 0x00a020ac /* Service Post DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES 0x00a020b0 /* Maximum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES 0x00a020b4 /* Minimum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ 0x00a020b8 /* Service Read Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE 0x00a020bc /* Service Write Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS 0x00a020c0 /* Maximum service Transaction count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS 0x00a020c4 /* Minimum service cycle Transaction register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY 0x00a020c8 /* Service Latency Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY 0x00a020cc /* Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY 0x00a020d0 /* Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x00a020d4 /* Absolute Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x00a020d8 /* Absolute Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH             0x00a020dc /* Total number of refreshes issuedr. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0        0x00a020e0 /* CAS cycle count register for client 0. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1        0x00a020e4 /* CAS cycle count register for client 1. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2        0x00a020e8 /* CAS cycle count register for client 2. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3        0x00a020ec /* CAS cycle count register for client 3. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4        0x00a020f0 /* CAS cycle count register for client 4. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5        0x00a020f4 /* CAS cycle count register for client 5. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6        0x00a020f8 /* CAS cycle count register for client 6. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7        0x00a020fc /* CAS cycle count register for client 7. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8        0x00a02100 /* CAS cycle count register for client 8. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9        0x00a02104 /* CAS cycle count register for client 9. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10       0x00a02108 /* CAS cycle count register for client 10. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11       0x00a0210c /* CAS cycle count register for client 11. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12       0x00a02110 /* CAS cycle count register for client 12. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13       0x00a02114 /* CAS cycle count register for client 13. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14       0x00a02118 /* CAS cycle count register for client 14. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15       0x00a0211c /* CAS cycle count register for client 15. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16       0x00a02120 /* CAS cycle count register for client 16. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17       0x00a02124 /* CAS cycle count register for client 17. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18       0x00a02128 /* CAS cycle count register for client 18. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19       0x00a0212c /* CAS cycle count register for client 19. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20       0x00a02130 /* CAS cycle count register for client 20. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21       0x00a02134 /* CAS cycle count register for client 21. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22       0x00a02138 /* CAS cycle count register for client 22. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23       0x00a0213c /* CAS cycle count register for client 23. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24       0x00a02140 /* CAS cycle count register for client 24. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25       0x00a02144 /* CAS cycle count register for client 25. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26       0x00a02148 /* CAS cycle count register for client 26. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27       0x00a0214c /* CAS cycle count register for client 27. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28       0x00a02150 /* CAS cycle count register for client 28. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29       0x00a02154 /* CAS cycle count register for client 29. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30       0x00a02158 /* CAS cycle count register for client 30. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31       0x00a0215c /* CAS cycle count register for client 31. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32       0x00a02160 /* CAS cycle count register for client 32. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33       0x00a02164 /* CAS cycle count register for client 33. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34       0x00a02168 /* CAS cycle count register for client 34. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35       0x00a0216c /* CAS cycle count register for client 35. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36       0x00a02170 /* CAS cycle count register for client 36. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37       0x00a02174 /* CAS cycle count register for client 37. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38       0x00a02178 /* CAS cycle count register for client 38. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39       0x00a0217c /* CAS cycle count register for client 39. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40       0x00a02180 /* CAS cycle count register for client 40. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41       0x00a02184 /* CAS cycle count register for client 41. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42       0x00a02188 /* CAS cycle count register for client 42. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43       0x00a0218c /* CAS cycle count register for client 43. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44       0x00a02190 /* CAS cycle count register for client 44. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45       0x00a02194 /* CAS cycle count register for client 45. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46       0x00a02198 /* CAS cycle count register for client 46. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47       0x00a0219c /* CAS cycle count register for client 47. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48       0x00a021a0 /* CAS cycle count register for client 48. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49       0x00a021a4 /* CAS cycle count register for client 49. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50       0x00a021a8 /* CAS cycle count register for client 50. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51       0x00a021ac /* CAS cycle count register for client 51. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52       0x00a021b0 /* CAS cycle count register for client 52. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53       0x00a021b4 /* CAS cycle count register for client 53. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54       0x00a021b8 /* CAS cycle count register for client 54. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55       0x00a021bc /* CAS cycle count register for client 55. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56       0x00a021c0 /* CAS cycle count register for client 56. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57       0x00a021c4 /* CAS cycle count register for client 57. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58       0x00a021c8 /* CAS cycle count register for client 58. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59       0x00a021cc /* CAS cycle count register for client 59. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60       0x00a021d0 /* CAS cycle count register for client 60. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61       0x00a021d4 /* CAS cycle count register for client 61. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62       0x00a021d8 /* CAS cycle count register for client 62. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63       0x00a021dc /* CAS cycle count register for client 63. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64       0x00a021e0 /* CAS cycle count register for client 64. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65       0x00a021e4 /* CAS cycle count register for client 65. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66       0x00a021e8 /* CAS cycle count register for client 66. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67       0x00a021ec /* CAS cycle count register for client 67. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68       0x00a021f0 /* CAS cycle count register for client 68. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69       0x00a021f4 /* CAS cycle count register for client 69. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70       0x00a021f8 /* CAS cycle count register for client 70. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71       0x00a021fc /* CAS cycle count register for client 71. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72       0x00a02200 /* CAS cycle count register for client 72. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73       0x00a02204 /* CAS cycle count register for client 73. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74       0x00a02208 /* CAS cycle count register for client 74. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75       0x00a0220c /* CAS cycle count register for client 75. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76       0x00a02210 /* CAS cycle count register for client 76. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77       0x00a02214 /* CAS cycle count register for client 77. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78       0x00a02218 /* CAS cycle count register for client 78. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79       0x00a0221c /* CAS cycle count register for client 79. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80       0x00a02220 /* CAS cycle count register for client 80. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81       0x00a02224 /* CAS cycle count register for client 81. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82       0x00a02228 /* CAS cycle count register for client 82. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83       0x00a0222c /* CAS cycle count register for client 83. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84       0x00a02230 /* CAS cycle count register for client 84. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85       0x00a02234 /* CAS cycle count register for client 85. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86       0x00a02238 /* CAS cycle count register for client 86. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87       0x00a0223c /* CAS cycle count register for client 87. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88       0x00a02240 /* CAS cycle count register for client 88. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89       0x00a02244 /* CAS cycle count register for client 89. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90       0x00a02248 /* CAS cycle count register for client 90. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91       0x00a0224c /* CAS cycle count register for client 91. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92       0x00a02250 /* CAS cycle count register for client 92. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93       0x00a02254 /* CAS cycle count register for client 93. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94       0x00a02258 /* CAS cycle count register for client 94. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95       0x00a0225c /* CAS cycle count register for client 95. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96       0x00a02260 /* CAS cycle count register for client 96. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97       0x00a02264 /* CAS cycle count register for client 97. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98       0x00a02268 /* CAS cycle count register for client 98. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99       0x00a0226c /* CAS cycle count register for client 99. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100      0x00a02270 /* CAS cycle count register for client 100. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101      0x00a02274 /* CAS cycle count register for client 101. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102      0x00a02278 /* CAS cycle count register for client 102. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103      0x00a0227c /* CAS cycle count register for client 103. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104      0x00a02280 /* CAS cycle count register for client 104. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105      0x00a02284 /* CAS cycle count register for client 105. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106      0x00a02288 /* CAS cycle count register for client 106. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107      0x00a0228c /* CAS cycle count register for client 107. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108      0x00a02290 /* CAS cycle count register for client 108. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109      0x00a02294 /* CAS cycle count register for client 109. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110      0x00a02298 /* CAS cycle count register for client 110. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111      0x00a0229c /* CAS cycle count register for client 111. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112      0x00a022a0 /* CAS cycle count register for client 112. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113      0x00a022a4 /* CAS cycle count register for client 113. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114      0x00a022a8 /* CAS cycle count register for client 114. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115      0x00a022ac /* CAS cycle count register for client 115. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116      0x00a022b0 /* CAS cycle count register for client 116. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117      0x00a022b4 /* CAS cycle count register for client 117. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118      0x00a022b8 /* CAS cycle count register for client 118. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119      0x00a022bc /* CAS cycle count register for client 119. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120      0x00a022c0 /* CAS cycle count register for client 120. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121      0x00a022c4 /* CAS cycle count register for client 121. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122      0x00a022c8 /* CAS cycle count register for client 122. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123      0x00a022cc /* CAS cycle count register for client 123. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124      0x00a022d0 /* CAS cycle count register for client 124. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125      0x00a022d4 /* CAS cycle count register for client 125. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126      0x00a022d8 /* CAS cycle count register for client 126. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127      0x00a022dc /* CAS cycle count register for client 127. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL         0x00a022e0 /* Minimum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL 0x00a022e4 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL 0x00a022e8 /* MEMSYS Auto Init Control. */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS  0x00a022ec /* MEMSYS Auto Init Status. */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE 0x00a022f0 /* PHY VDL calibrate override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE 0x00a022f4 /* SHIM PLL pndiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE 0x00a022f8 /* SHIM PLL mdiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY          0x00a022fc /* Dynamic VDL shmoo command delay. */
+
+/***************************************************************************
+ *CNTRLR_CONFIG - Memory Controller Mode-Configuration Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_MASK               0xfffffff8
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_SHIFT              3
+
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DEVICE_TECH [02:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_SHIFT            0
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_DEFAULT          3
+
+/***************************************************************************
+ *DRAM_INIT_CNTRL - Dram iniitialization control
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_MASK             0xfffffff8
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_SHIFT            3
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: BYPASS_PHY_INIT_RDY [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_MASK   0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_SHIFT  2
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR_TECH [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DEFAULT           1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR2              0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR3              1
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR3_INIT_MODE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_MASK        0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_SHIFT       0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_DEFAULT     0
+
+/***************************************************************************
+ *DRAM_INIT_STATUS - Dram iniitialization status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_SHIFT           0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_DEFAULT         0
+
+/***************************************************************************
+ *DRAM_MODE_0 - Dram Mode0 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: PD_EXIT [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_MASK              0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_SHIFT             12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_DEFAULT                7
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_DEFAULT         0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: CL [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_MASK                   0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_DEFAULT                0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BL [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_DEFAULT                2
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK        0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT       12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT     0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_DEFAULT                4
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT         0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_MASK               0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_SHIFT              4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT            4
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_DEFAULT               0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_MASK                 0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_SHIFT                2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_DEFAULT              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_MASK                   0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_MODE_1 - Dram Mode1 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DEFAULT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: RDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DQSB [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_MASK                 0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_SHIFT                10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_ENABLE               0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DISABLE              1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: OCD_CAL [09:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_MASK              0x00000380
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_SHIFT             7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_DEFAULT       1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: AL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_MASK                   0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DRV_IMP [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DISABLE            1
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_MASK             0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_SHIFT            10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK          0x00000200
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT         9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_MASK             0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT            7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT          0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE           1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK   0x00000020
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT  5
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_MASK                   0x00000018
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT       1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK   0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT  1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DISABLE            1
+
+/***************************************************************************
+ *DRAM_MODE_2 - Dram Mode2 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_1 [12:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_MASK             0x00001f00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: HT_SRF [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_ENABLE             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DISABLE            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_2 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_MASK             0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_SHIFT            4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: DCC_ENABLE [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_MASK           0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_SHIFT          3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DEFAULT        0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_ENABLE         1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DISABLE        0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_DEFAULT              0
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_MASK             0x00001800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_SHIFT            11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_MASK               0x00000600
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_SHIFT              9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT            1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT             6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT           1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_MASK                  0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_DEFAULT               1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_MODE_3 - Dram Mode3 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: unused_0 [15:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_MASK                  0x0000fff8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_DEFAULT               0
+
+/* union - case DDR2 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR2 :: unused_1 [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_SHIFT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_DEFAULT          0
+
+/* union - case DDR3 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_MASK                  0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_SHIFT                 2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_DEFAULT               0
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_MASK              0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT           0
+
+/***************************************************************************
+ *PPD_CONFIG - Precharge power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PPD_CONFIG :: reserved0 [31:13] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_MASK                  0xffffe000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_SHIFT                 13
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_EN [12:12] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_MASK                     0x00001000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_SHIFT                    12
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_DEFAULT                  0
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: INACT_COUNT [11:00] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_MASK                0x00000fff
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *SRPD_CONFIG - Self-refresh power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SRPD_CONFIG :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_MASK                 0xfffe0000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_SHIFT                17
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: SRPD_EN [16:16] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_MASK                   0x00010000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_SHIFT                  16
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_DEFAULT                0
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *SSPD_CMD - Software standby power down mode
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SSPD_CMD :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_MASK                    0xfffffffe
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_SHIFT                   1
+
+/* MEMC_DDR_0 :: SSPD_CMD :: SSPD [00:00] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK                         0x00000001
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_SHIFT                        0
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_DEFAULT                      0
+
+/***************************************************************************
+ *POWER_DOWN_STATUS - Power down status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_MASK           0xfffffff8
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_SHIFT          3
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SSPD [02:02] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK                0x00000004
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_SHIFT               2
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_DEFAULT             0
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SRPD [01:01] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_MASK                0x00000002
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_SHIFT               1
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_DEFAULT             0
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: PPD [00:00] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_MASK                 0x00000001
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_SHIFT                0
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_DEFAULT              0
+
+/***************************************************************************
+ *WARM_BOOT - Warm boot control registers
+ ***************************************************************************/
+/* MEMC_DDR_0 :: WARM_BOOT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_MASK                   0xfffffffe
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_SHIFT                  1
+
+/* MEMC_DDR_0 :: WARM_BOOT :: WARM_BOOT [00:00] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_MASK                   0x00000001
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_TIMING_0 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_MASK                0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_SHIFT               24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_DEFAULT             6
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_MASK                0x00ff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_SHIFT               16
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_DEFAULT             8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_MASK                 0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_SHIFT                8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_DEFAULT              8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_DEFAULT             20
+
+/***************************************************************************
+ *DRAM_TIMING_1 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_MASK                0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_SHIFT               8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_DEFAULT             27
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_DEFAULT             4
+
+/***************************************************************************
+ *DRAM_TIMING_2 - Read to Write & write to read timing register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_MASK               0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_SHIFT              8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_DEFAULT            14
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_MASK               0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_DEFAULT            9
+
+/***************************************************************************
+ *DRAM_TIMING_3 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: reserved0 [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_MASK               0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_SHIFT              24
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT      12
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: POWERUP_CKE_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_MASK       0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_SHIFT      10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_DEFAULT    94
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: DLL_LOCK_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_MASK          0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_SHIFT         0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_DEFAULT       512
+
+/***************************************************************************
+ *DRAM_TIMING_4 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: PRECHARGE_ALL_DELAY [28:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_MASK     0x1f000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_SHIFT    24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_DEFAULT  8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: LOAD_MODE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_DEFAULT      12
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: REFRESH_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_MASK           0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_SHIFT          10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT        88
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_MASK           0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT          0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT        512
+
+/***************************************************************************
+ *DRAM_TIMING_5 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_ASSETION_DELAY [28:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_MASK      0x1ff80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_SHIFT     19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_DEFAULT   261
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [18:15] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK           0x00078000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT          15
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT        3
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [14:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK         0x00007c00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT        10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT      13
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK      0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT     0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT   512
+
+/***************************************************************************
+ *CNTRLR_START_SEQ - Memory Controller Sequencer Enable
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: START_SEQ [00:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_SHIFT           0
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_DEFAULT         0
+
+/***************************************************************************
+ *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_MASK           0xfffe0000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_SHIFT          17
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_MASK              0x00010000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT             16
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT           0
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT            65535
+
+/***************************************************************************
+ *BANK_STATUS - Memory Controller, Bank Status Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: BANK_STATUS :: reserved0 [31:08] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_SHIFT                8
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK7_STATUS [07:07] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_SHIFT             7
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK6_STATUS [06:06] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_SHIFT             6
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK5_STATUS [05:05] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_MASK              0x00000020
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_SHIFT             5
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK4_STATUS [04:04] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_MASK              0x00000010
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_SHIFT             4
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK3_STATUS [03:03] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_MASK              0x00000008
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_SHIFT             3
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK2_STATUS [02:02] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_MASK              0x00000004
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_SHIFT             2
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK1_STATUS [01:01] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_SHIFT             1
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK0_STATUS [00:00] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_MASK              0x00000001
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_SHIFT             0
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_DEFAULT           1
+
+/***************************************************************************
+ *TESTER_LATENCY - Memory Controller, Tester Latency Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: TESTER_LATENCY :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_MASK              0xffffff80
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_SHIFT             7
+
+/* MEMC_DDR_0 :: TESTER_LATENCY :: TLATENCY_SEL [06:00] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_MASK           0x0000007f
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_SHIFT          0
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_DEFAULT        0
+
+/***************************************************************************
+ *DTPM_BYTE0 - Memory Controller, DATA_PINMAP_BYTE0_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE1 - Memory Controller, DATA_PINMAP_BYTE1_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE2 - Memory Controller, DATA_PINMAP_BYTE2_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE3 - Memory Controller, DATA_PINMAP_BYTE3_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_DDR3_RESET_PERIOD - Memory Controller, DDR3 DRAM reset Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: reserved0 [31:20] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_MASK      0xfff00000
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_SHIFT     20
+
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: DRAM_RESET_PERIOD [19:00] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_MASK 0x000fffff
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_SHIFT 0
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_DEFAULT 43200
+
+/***************************************************************************
+ *STAT_CONTROL - Statistics Control register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CONTROL :: reserved0 [31:09] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_MASK                0xfffffe00
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_SHIFT               9
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: COUNTER_MODE [08:08] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_SHIFT            8
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_DEFAULT          0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT    1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_NORMAL           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: STAT_ENABLE [07:07] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_SHIFT             7
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DEFAULT           0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_ENABLE            1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DISABLE           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: CLIENT_ID [06:00] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_MASK                0x0000007f
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_DEFAULT             0
+
+/***************************************************************************
+ *STAT_TIMER - Statistics Timer
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TIMER :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_MASK                      0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_SHIFT                     0
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_DEFAULT                   0
+
+/***************************************************************************
+ *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_MASK                   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_DEFAULT                0
+
+/***************************************************************************
+ *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_ALL - CAS Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_DEFAULT                 0
+
+/***************************************************************************
+ *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_PENALTY_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT    0
+
+/***************************************************************************
+ *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_MASK            0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_SHIFT           0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT         0
+
+/***************************************************************************
+ *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_DEFAULT           4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_MASK         0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT        0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT      0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT  4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT  0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_REFRESH - Total number of refreshes issuedr.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_REFRESH :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_DEFAULT                 0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_0 - CAS cycle count register for client 0.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_1 - CAS cycle count register for client 1.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_2 - CAS cycle count register for client 2.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_3 - CAS cycle count register for client 3.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_4 - CAS cycle count register for client 4.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_5 - CAS cycle count register for client 5.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_6 - CAS cycle count register for client 6.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_7 - CAS cycle count register for client 7.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_8 - CAS cycle count register for client 8.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_9 - CAS cycle count register for client 9.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_10 - CAS cycle count register for client 10.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_11 - CAS cycle count register for client 11.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_12 - CAS cycle count register for client 12.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_13 - CAS cycle count register for client 13.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_14 - CAS cycle count register for client 14.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_15 - CAS cycle count register for client 15.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_16 - CAS cycle count register for client 16.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_17 - CAS cycle count register for client 17.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_18 - CAS cycle count register for client 18.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_19 - CAS cycle count register for client 19.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_20 - CAS cycle count register for client 20.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_21 - CAS cycle count register for client 21.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_22 - CAS cycle count register for client 22.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_23 - CAS cycle count register for client 23.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_24 - CAS cycle count register for client 24.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_25 - CAS cycle count register for client 25.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_26 - CAS cycle count register for client 26.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_27 - CAS cycle count register for client 27.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_28 - CAS cycle count register for client 28.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_29 - CAS cycle count register for client 29.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_30 - CAS cycle count register for client 30.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_31 - CAS cycle count register for client 31.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_32 - CAS cycle count register for client 32.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_33 - CAS cycle count register for client 33.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_34 - CAS cycle count register for client 34.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_35 - CAS cycle count register for client 35.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_36 - CAS cycle count register for client 36.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_37 - CAS cycle count register for client 37.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_38 - CAS cycle count register for client 38.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_39 - CAS cycle count register for client 39.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_40 - CAS cycle count register for client 40.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_41 - CAS cycle count register for client 41.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_42 - CAS cycle count register for client 42.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_43 - CAS cycle count register for client 43.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_44 - CAS cycle count register for client 44.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_45 - CAS cycle count register for client 45.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_46 - CAS cycle count register for client 46.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_47 - CAS cycle count register for client 47.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_48 - CAS cycle count register for client 48.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_49 - CAS cycle count register for client 49.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_50 - CAS cycle count register for client 50.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_51 - CAS cycle count register for client 51.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_52 - CAS cycle count register for client 52.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_53 - CAS cycle count register for client 53.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_54 - CAS cycle count register for client 54.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_55 - CAS cycle count register for client 55.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_56 - CAS cycle count register for client 56.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_57 - CAS cycle count register for client 57.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_58 - CAS cycle count register for client 58.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_59 - CAS cycle count register for client 59.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_60 - CAS cycle count register for client 60.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_61 - CAS cycle count register for client 61.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_62 - CAS cycle count register for client 62.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_63 - CAS cycle count register for client 63.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_64 - CAS cycle count register for client 64.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_65 - CAS cycle count register for client 65.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_66 - CAS cycle count register for client 66.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_67 - CAS cycle count register for client 67.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_68 - CAS cycle count register for client 68.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_69 - CAS cycle count register for client 69.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_70 - CAS cycle count register for client 70.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_71 - CAS cycle count register for client 71.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_72 - CAS cycle count register for client 72.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_73 - CAS cycle count register for client 73.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_74 - CAS cycle count register for client 74.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_75 - CAS cycle count register for client 75.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_76 - CAS cycle count register for client 76.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_77 - CAS cycle count register for client 77.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_78 - CAS cycle count register for client 78.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_79 - CAS cycle count register for client 79.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_80 - CAS cycle count register for client 80.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_81 - CAS cycle count register for client 81.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_82 - CAS cycle count register for client 82.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_83 - CAS cycle count register for client 83.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_84 - CAS cycle count register for client 84.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_85 - CAS cycle count register for client 85.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_86 - CAS cycle count register for client 86.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_87 - CAS cycle count register for client 87.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_88 - CAS cycle count register for client 88.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_89 - CAS cycle count register for client 89.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_90 - CAS cycle count register for client 90.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_91 - CAS cycle count register for client 91.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_92 - CAS cycle count register for client 92.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_93 - CAS cycle count register for client 93.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_94 - CAS cycle count register for client 94.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_95 - CAS cycle count register for client 95.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_96 - CAS cycle count register for client 96.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_97 - CAS cycle count register for client 97.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_98 - CAS cycle count register for client 98.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_99 - CAS cycle count register for client 99.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_100 - CAS cycle count register for client 100.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_101 - CAS cycle count register for client 101.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_102 - CAS cycle count register for client 102.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_103 - CAS cycle count register for client 103.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_104 - CAS cycle count register for client 104.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_105 - CAS cycle count register for client 105.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_106 - CAS cycle count register for client 106.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_107 - CAS cycle count register for client 107.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_108 - CAS cycle count register for client 108.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_109 - CAS cycle count register for client 109.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_110 - CAS cycle count register for client 110.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_111 - CAS cycle count register for client 111.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_112 - CAS cycle count register for client 112.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_113 - CAS cycle count register for client 113.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_114 - CAS cycle count register for client 114.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_115 - CAS cycle count register for client 115.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_116 - CAS cycle count register for client 116.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_117 - CAS cycle count register for client 117.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_118 - CAS cycle count register for client 118.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_119 - CAS cycle count register for client 119.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_120 - CAS cycle count register for client 120.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_121 - CAS cycle count register for client 121.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_122 - CAS cycle count register for client 122.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_123 - CAS cycle count register for client 123.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_124 - CAS cycle count register for client 124.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_125 - CAS cycle count register for client 125.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_126 - CAS cycle count register for client 126.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_127 - CAS cycle count register for client 127.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_DEFAULT             4294967295
+
+/***************************************************************************
+ *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT    4294967295
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_CONTROL - MEMSYS Auto Init Control.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: reserved0 [31:10] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_MASK    0xfffffc00
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_SHIFT   10
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_DIVIDER [09:09] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_MASK 0x00000200
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_SHIFT 9
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_VDL_CALIB_AUTO_INIT [08:08] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_MASK 0x00000100
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_SHIFT 8
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_DRAM_INIT_DONE_SET [07:07] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_MASK 0x00000080
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_SHIFT 7
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_RESET [06:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_MASK 0x00000040
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_SET [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_READY_SET [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_AUTO_INIT_ACTIVE_RESET [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_MASK 0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_SHIFT 3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: SKIP_PHY_AUTO_INIT [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: MEMSYS_AUTO_INIT_START [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_STATUS - MEMSYS Auto Init Status.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_MASK     0xfffff000
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_SHIFT    12
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMC_AUTO_INIT_STATES [11:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_MASK 0x00000fc0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: AUTO_INIT_ACTIVE [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_STRAP_VALID [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_READY [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_MASK     0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_SHIFT    3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_DEFAULT  0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: DRAM_INIT_DONE [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_FAIL [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_DEFAULT 0
+
+/***************************************************************************
+ *PHY_VDL_CALIB_AUTO_INIT_OVERRIDE - PHY VDL calibrate override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PHY_VDL_CALIB_AUTO_INIT_OVERRIDE :: PHY_VDL_CALIB_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_DEFAULT 268435456
+
+/***************************************************************************
+ *SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE - SHIM PLL pndiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_PNDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_DEFAULT 598736896
+
+/***************************************************************************
+ *SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE - SHIM PLL mdiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_MDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_DEFAULT 4099
+
+/***************************************************************************
+ *DYN_VDL_CMD_DLY - Dynamic VDL shmoo command delay.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_MASK             0xfffff000
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_SHIFT            12
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: END_CAS_DLY [11:06] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_MASK           0x00000fc0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_SHIFT          6
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_DEFAULT        0
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: START_CAS_DLY [05:00] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_MASK         0x0000003f
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_SHIFT        0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_DEFAULT      0
+
+#endif /* #ifndef BCHP_MEMC_DDR_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_moca_hostmisc.h b/include/linux/brcmstb/7344b0/bchp_moca_hostmisc.h
new file mode 100644
index 0000000..632e9b5
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_moca_hostmisc.h
@@ -0,0 +1,195 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:41:09 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_moca_hostmisc.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 1:59p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MOCA_HOSTMISC_H__
+#define BCHP_MOCA_HOSTMISC_H__
+
+/***************************************************************************
+ *MOCA_HOSTMISC - MOCA_HOSTMISC registers
+ ***************************************************************************/
+#define BCHP_MOCA_HOSTMISC_SW_RESET              0x002a2040 /* Moca Software Reset */
+#define BCHP_MOCA_HOSTMISC_SCRATCH               0x002a2044 /* Moca Scratch Register */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG      0x002a204c /* MoCA version register */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP0             0x002a2050 /* Moca Host Messaging Register 0 */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP1             0x002a2054 /* Moca Host Messaging Register 1 */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP2             0x002a2058 /* Moca Host Messaging Register 2 */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP3             0x002a205c /* Moca Host Messaging Register 3 */
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG          0x002a2060 /* Host-to-MoCA Interrupt Trigger */
+#define BCHP_MOCA_HOSTMISC_WAKEUP                0x002a2064 /* Host-to-MoCA Wakeup Interrupt */
+
+/***************************************************************************
+ *SW_RESET - Moca Software Reset
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: SW_RESET :: spare_control [31:15] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_control_MASK             0xffff8000
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_control_SHIFT            15
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_control_DEFAULT          131071
+
+/* MOCA_HOSTMISC :: SW_RESET :: spare_status [14:08] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_status_MASK              0x00007f00
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_status_SHIFT             8
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_status_DEFAULT           127
+
+/* MOCA_HOSTMISC :: SW_RESET :: moca_disable_clocks [07:07] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_disable_clocks_MASK       0x00000080
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_disable_clocks_SHIFT      7
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_disable_clocks_DEFAULT    0
+
+/* MOCA_HOSTMISC :: SW_RESET :: spare_reset2 [06:04] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset2_MASK              0x00000070
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset2_SHIFT             4
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset2_DEFAULT           7
+
+/* MOCA_HOSTMISC :: SW_RESET :: moca_gmii_sw_init [03:03] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_gmii_sw_init_MASK         0x00000008
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_gmii_sw_init_SHIFT        3
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_gmii_sw_init_DEFAULT      0
+
+/* MOCA_HOSTMISC :: SW_RESET :: spare_reset [02:02] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset_MASK               0x00000004
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset_SHIFT              2
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset_DEFAULT            1
+
+/* MOCA_HOSTMISC :: SW_RESET :: moca_sys_reset [01:01] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_sys_reset_MASK            0x00000002
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_sys_reset_SHIFT           1
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_sys_reset_DEFAULT         1
+
+/* MOCA_HOSTMISC :: SW_RESET :: moca_cpu_reset [00:00] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_cpu_reset_MASK            0x00000001
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_cpu_reset_SHIFT           0
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_cpu_reset_DEFAULT         1
+
+/***************************************************************************
+ *SCRATCH - Moca Scratch Register
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: SCRATCH :: VALUE [31:00] */
+#define BCHP_MOCA_HOSTMISC_SCRATCH_VALUE_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_SCRATCH_VALUE_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_SCRATCH_VALUE_DEFAULT                   0
+
+/***************************************************************************
+ *MOCA_VERSION_REG - MoCA version register
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: MOCA_VERSION_REG :: moca_id [31:16] */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_id_MASK           0xffff0000
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_id_SHIFT          16
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_id_DEFAULT        26146
+
+/* MOCA_HOSTMISC :: MOCA_VERSION_REG :: moca_spec_ver [15:12] */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_spec_ver_MASK     0x0000f000
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_spec_ver_SHIFT    12
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_spec_ver_DEFAULT  1
+
+/* MOCA_HOSTMISC :: MOCA_VERSION_REG :: core_version [11:08] */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_version_MASK      0x00000f00
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_version_SHIFT     8
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_version_DEFAULT   1
+
+/* MOCA_HOSTMISC :: MOCA_VERSION_REG :: core_revision [07:04] */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_revision_MASK     0x000000f0
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_revision_SHIFT    4
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_revision_DEFAULT  1
+
+/* MOCA_HOSTMISC :: MOCA_VERSION_REG :: core_mask [03:00] */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_mask_MASK         0x0000000f
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_mask_SHIFT        0
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_mask_DEFAULT      0
+
+/***************************************************************************
+ *HOST_MMP0 - Moca Host Messaging Register 0
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: HOST_MMP0 :: MMP [31:00] */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP0_MMP_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_HOST_MMP0_MMP_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_HOST_MMP0_MMP_DEFAULT                   0
+
+/***************************************************************************
+ *HOST_MMP1 - Moca Host Messaging Register 1
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: HOST_MMP1 :: MMP [31:00] */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP1_MMP_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_HOST_MMP1_MMP_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_HOST_MMP1_MMP_DEFAULT                   0
+
+/***************************************************************************
+ *HOST_MMP2 - Moca Host Messaging Register 2
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: HOST_MMP2 :: MMP [31:00] */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP2_MMP_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_HOST_MMP2_MMP_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_HOST_MMP2_MMP_DEFAULT                   0
+
+/***************************************************************************
+ *HOST_MMP3 - Moca Host Messaging Register 3
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: HOST_MMP3 :: MMP [31:00] */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP3_MMP_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_HOST_MMP3_MMP_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_HOST_MMP3_MMP_DEFAULT                   0
+
+/***************************************************************************
+ *H2M_INT_TRIG - Host-to-MoCA Interrupt Trigger
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_INT_TRIG :: reserved0 [31:08] */
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_reserved0_MASK             0xffffff00
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_reserved0_SHIFT            8
+
+/* MOCA_HOSTMISC :: H2M_INT_TRIG :: INT_TRIG [07:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_MASK              0x000000ff
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_SHIFT             0
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_DEFAULT           0
+
+/***************************************************************************
+ *WAKEUP - Host-to-MoCA Wakeup Interrupt
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: WAKEUP :: reserved0 [31:01] */
+#define BCHP_MOCA_HOSTMISC_WAKEUP_reserved0_MASK                   0xfffffffe
+#define BCHP_MOCA_HOSTMISC_WAKEUP_reserved0_SHIFT                  1
+
+/* MOCA_HOSTMISC :: WAKEUP :: wakeup_int [00:00] */
+#define BCHP_MOCA_HOSTMISC_WAKEUP_wakeup_int_MASK                  0x00000001
+#define BCHP_MOCA_HOSTMISC_WAKEUP_wakeup_int_SHIFT                 0
+#define BCHP_MOCA_HOSTMISC_WAKEUP_wakeup_int_DEFAULT               0
+
+#endif /* #ifndef BCHP_MOCA_HOSTMISC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_nand.h b/include/linux/brcmstb/7344b0/bchp_nand.h
new file mode 100644
index 0000000..ef922ca
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_nand.h
@@ -0,0 +1,2486 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:36:59 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_nand.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 2:02p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_NAND_H__
+#define BCHP_NAND_H__
+
+/***************************************************************************
+ *NAND - Nand Flash Control Registers
+ ***************************************************************************/
+#define BCHP_NAND_REVISION                       0x00002800 /* NAND Revision */
+#define BCHP_NAND_CMD_START                      0x00002804 /* Nand Flash Command Start */
+#define BCHP_NAND_CMD_EXT_ADDRESS                0x00002808 /* Nand Flash Command Extended Address */
+#define BCHP_NAND_CMD_ADDRESS                    0x0000280c /* Nand Flash Command Address */
+#define BCHP_NAND_CMD_END_ADDRESS                0x00002810 /* Nand Flash Command End Address */
+#define BCHP_NAND_CS_NAND_SELECT                 0x00002814 /* Nand Flash EBI CS Select */
+#define BCHP_NAND_CS_NAND_XOR                    0x00002818 /* Nand Flash EBI CS Address XOR with 1FC0 Control */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0          0x00002820 /* Nand Flash Spare Area Read Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4          0x00002824 /* Nand Flash Spare Area Read Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8          0x00002828 /* Nand Flash Spare Area Read Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C          0x0000282c /* Nand Flash Spare Area Read Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0         0x00002830 /* Nand Flash Spare Area Write Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4         0x00002834 /* Nand Flash Spare Area Write Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8         0x00002838 /* Nand Flash Spare Area Write Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C         0x0000283c /* Nand Flash Spare Area Write Bytes 12-15 */
+#define BCHP_NAND_ACC_CONTROL                    0x00002840 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG                         0x00002848 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1                       0x00002850 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2                       0x00002854 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SEMAPHORE                      0x00002858 /* Semaphore */
+#define BCHP_NAND_FLASH_DEVICE_ID                0x00002860 /* Nand Flash Device ID */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT            0x00002864 /* Nand Flash Extended Device ID */
+#define BCHP_NAND_BLOCK_LOCK_STATUS              0x00002868 /* Nand Flash Block Lock Status */
+#define BCHP_NAND_INTFC_STATUS                   0x0000286c /* Nand Flash Interface Status */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR              0x00002870 /* ECC Correctable Error Extended Address */
+#define BCHP_NAND_ECC_CORR_ADDR                  0x00002874 /* ECC Correctable Error Address */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR               0x00002878 /* ECC Uncorrectable Error Extended Address */
+#define BCHP_NAND_ECC_UNC_ADDR                   0x0000287c /* ECC Uncorrectable Error Address */
+#define BCHP_NAND_READ_ERROR_COUNT               0x00002880 /* Read Error Count */
+#define BCHP_NAND_CORR_STAT_THRESHOLD            0x00002884 /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_ONFI_STATUS                    0x00002888 /* ONFI Status */
+#define BCHP_NAND_ONFI_DEBUG_DATA                0x0000288c /* ONFI Debug Data */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR            0x00002890 /* Flash Read Data Extended Address */
+#define BCHP_NAND_FLASH_READ_ADDR                0x00002894 /* Flash Read Data Address */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR          0x00002898 /* Page Program Extended Address */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR              0x0000289c /* Page Program Address */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR             0x000028a0 /* Copy Back Extended Address */
+#define BCHP_NAND_COPY_BACK_ADDR                 0x000028a4 /* Copy Back Address */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR           0x000028a8 /* Block Erase Extended Address */
+#define BCHP_NAND_BLOCK_ERASE_ADDR               0x000028ac /* Block Erase Address */
+#define BCHP_NAND_INV_READ_EXT_ADDR              0x000028b0 /* Flash Invalid Data Extended Address */
+#define BCHP_NAND_INV_READ_ADDR                  0x000028b4 /* Flash Invalid Data Address */
+#define BCHP_NAND_BLK_WR_PROTECT                 0x000028c0 /* Block Write Protect Enable and Size for EBI_CS0b */
+#define BCHP_NAND_ACC_CONTROL_CS1                0x000028d0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS1                     0x000028d4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS1                   0x000028d8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS1                   0x000028dc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS2                0x000028e0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS2                     0x000028e4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS2                   0x000028e8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS2                   0x000028ec /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS3                0x000028f0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS3                     0x000028f4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS3                   0x000028f8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS3                   0x000028fc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS4                0x00002900 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS4                     0x00002904 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS4                   0x00002908 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS4                   0x0000290c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS5                0x00002910 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS5                     0x00002914 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS5                   0x00002918 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS5                   0x0000291c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10         0x00002930 /* Nand Flash Spare Area Read Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14         0x00002934 /* Nand Flash Spare Area Read Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18         0x00002938 /* Nand Flash Spare Area Read Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C         0x0000293c /* Nand Flash Spare Area Read Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10        0x00002940 /* Nand Flash Spare Area Write Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14        0x00002944 /* Nand Flash Spare Area Write Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18        0x00002948 /* Nand Flash Spare Area Write Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C        0x0000294c /* Nand Flash Spare Area Write Bytes 28-31 */
+#define BCHP_NAND_LL_OP                          0x00002978 /* Nand Flash Low Level Operation */
+#define BCHP_NAND_LL_RDDATA                      0x0000297c /* Nand Flash Low Level Read Data */
+
+/***************************************************************************
+ *REVISION - NAND Revision
+ ***************************************************************************/
+/* NAND :: REVISION :: 8KB_PAGE_SUPPORT [31:31] */
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_MASK                   0x80000000
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_SHIFT                  31
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_DEFAULT                1
+
+/* NAND :: REVISION :: reserved0 [30:16] */
+#define BCHP_NAND_REVISION_reserved0_MASK                          0x7fff0000
+#define BCHP_NAND_REVISION_reserved0_SHIFT                         16
+
+/* NAND :: REVISION :: MAJOR [15:08] */
+#define BCHP_NAND_REVISION_MAJOR_MASK                              0x0000ff00
+#define BCHP_NAND_REVISION_MAJOR_SHIFT                             8
+#define BCHP_NAND_REVISION_MAJOR_DEFAULT                           5
+
+/* NAND :: REVISION :: MINOR [07:00] */
+#define BCHP_NAND_REVISION_MINOR_MASK                              0x000000ff
+#define BCHP_NAND_REVISION_MINOR_SHIFT                             0
+#define BCHP_NAND_REVISION_MINOR_DEFAULT                           0
+
+/***************************************************************************
+ *CMD_START - Nand Flash Command Start
+ ***************************************************************************/
+/* NAND :: CMD_START :: reserved0 [31:29] */
+#define BCHP_NAND_CMD_START_reserved0_MASK                         0xe0000000
+#define BCHP_NAND_CMD_START_reserved0_SHIFT                        29
+
+/* NAND :: CMD_START :: OPCODE [28:24] */
+#define BCHP_NAND_CMD_START_OPCODE_MASK                            0x1f000000
+#define BCHP_NAND_CMD_START_OPCODE_SHIFT                           24
+#define BCHP_NAND_CMD_START_OPCODE_DEFAULT                         0
+#define BCHP_NAND_CMD_START_OPCODE_NULL                            0
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ                       1
+#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ                 2
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ                     3
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE                    4
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA              5
+#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK                       6
+#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ                  7
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE                     8
+#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET                     9
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK                     10
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN                11
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK                   12
+#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS         13
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ                  14
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL            15
+#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP                    16
+
+/* NAND :: CMD_START :: reserved1 [23:00] */
+#define BCHP_NAND_CMD_START_reserved1_MASK                         0x00ffffff
+#define BCHP_NAND_CMD_START_reserved1_SHIFT                        0
+
+/***************************************************************************
+ *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
+ ***************************************************************************/
+/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK                   0xfff80000
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT                  19
+
+/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK                      0x00070000
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT                     16
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT                   0
+
+/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK                 0x0000ffff
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT                0
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT              0
+
+/***************************************************************************
+ *CMD_ADDRESS - Nand Flash Command Address
+ ***************************************************************************/
+/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK                         0xffffffff
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT                        0
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT                      0
+
+/***************************************************************************
+ *CMD_END_ADDRESS - Nand Flash Command End Address
+ ***************************************************************************/
+/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT                    0
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT                  0
+
+/***************************************************************************
+ *CS_NAND_SELECT - Nand Flash EBI CS Select
+ ***************************************************************************/
+/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT                     31
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT                   0
+
+/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK        0x40000000
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT       30
+
+/* NAND :: CS_NAND_SELECT :: reserved0 [29:29] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK                    0x20000000
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT                   29
+
+/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK              0x10000000
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT             28
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT           0
+
+/* NAND :: CS_NAND_SELECT :: reserved1 [27:16] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_MASK                    0x0fff0000
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_SHIFT                   16
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK           0x00008000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT          15
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK           0x00004000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT          14
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK           0x00002000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT          13
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK           0x00001000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT          12
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK           0x00000800
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT          11
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK           0x00000400
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT          10
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK           0x00000200
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT          9
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK           0x00000100
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT          8
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK                 0x00000080
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT                7
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK                 0x00000040
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT                6
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK                 0x00000020
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT                5
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK                 0x00000010
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT                4
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK                 0x00000008
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT                3
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK                 0x00000004
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT                2
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK                 0x00000002
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT                1
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK                 0x00000001
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT                0
+
+/***************************************************************************
+ *CS_NAND_XOR - Nand Flash EBI CS Address XOR with 1FC0 Control
+ ***************************************************************************/
+/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_1FC0_XOR [31:31] */
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_MASK           0x80000000
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_SHIFT          31
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_DEFAULT        0
+
+/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
+#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK                       0x7fffff00
+#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT                      8
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_1FC0_XOR [07:07] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_MASK          0x00000080
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_SHIFT         7
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_1FC0_XOR [06:06] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_MASK          0x00000040
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_SHIFT         6
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_1FC0_XOR [05:05] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_MASK          0x00000020
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_SHIFT         5
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_1FC0_XOR [04:04] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_MASK          0x00000010
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_SHIFT         4
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_1FC0_XOR [03:03] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_MASK          0x00000008
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_SHIFT         3
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_1FC0_XOR [02:02] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_MASK          0x00000004
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_SHIFT         2
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_1FC0_XOR [01:01] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_MASK          0x00000002
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_SHIFT         1
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_1FC0_XOR [00:00] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_MASK          0x00000001
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_SHIFT         0
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT         255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT         255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT       255
+
+/***************************************************************************
+ *ACC_CONTROL - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_MASK                       0x80000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_SHIFT                      31
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_DEFAULT                    1
+
+/* NAND :: ACC_CONTROL :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_MASK                       0x40000000
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_SHIFT                      30
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_DEFAULT                    1
+
+/* NAND :: ACC_CONTROL :: RD_ECC_BLK0_EN [29:29] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_MASK                  0x20000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_SHIFT                 29
+
+/* NAND :: ACC_CONTROL :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_SHIFT                  28
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_MASK                0x08000000
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_SHIFT               27
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_DEFAULT             0
+
+/* NAND :: ACC_CONTROL :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_MASK                 0x04000000
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_SHIFT                26
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_MASK                   0x02000000
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_SHIFT                  25
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_MASK                     0x01000000
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_SHIFT                    24
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_DEFAULT                  1
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL_0 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_MASK                     0x00f00000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_SHIFT                    20
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_DEFAULT                  15
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_MASK                       0x000f0000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_SHIFT                      16
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_DEFAULT                    15
+
+/* NAND :: ACC_CONTROL :: reserved0 [15:15] */
+#define BCHP_NAND_ACC_CONTROL_reserved0_MASK                       0x00008000
+#define BCHP_NAND_ACC_CONTROL_reserved0_SHIFT                      15
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K_0 [14:14] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_MASK                0x00004000
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_SHIFT               14
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_DEFAULT             0
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE_0 [13:08] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_MASK               0x00003f00
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_SHIFT              8
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_DEFAULT            16
+
+/* NAND :: ACC_CONTROL :: reserved1 [07:07] */
+#define BCHP_NAND_ACC_CONTROL_reserved1_MASK                       0x00000080
+#define BCHP_NAND_ACC_CONTROL_reserved1_SHIFT                      7
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_MASK                  0x00000040
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_SHIFT                 6
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_DEFAULT               0
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_MASK                 0x0000003f
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_SHIFT                0
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_DEFAULT              16
+
+/***************************************************************************
+ *CONFIG - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_MASK                          0x80000000
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_SHIFT                         31
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_DEFAULT                       0
+
+/* NAND :: CONFIG :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_MASK                           0x70000000
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_SHIFT                          28
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_2048KB                 6
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_1024KB                 5
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_512KB                  3
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_128KB                  1
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_16KB                   0
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_8KB                    2
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_256KB                  4
+
+/* NAND :: CONFIG :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_MASK                          0x0f000000
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_SHIFT                         24
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4MB                  0
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8MB                  1
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16MB                 2
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32MB                 3
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64MB                 4
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128MB                5
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_256MB                6
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_512MB                7
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_1GB                  8
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_2GB                  9
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4GB                  10
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8GB                  11
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16GB                 12
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32GB                 13
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64GB                 14
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128GB                15
+
+/* NAND :: CONFIG :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_MASK                         0x00800000
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_SHIFT                        23
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_8                  0
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_16                 1
+
+/* NAND :: CONFIG :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_reserved0_MASK                            0x00400000
+#define BCHP_NAND_CONFIG_reserved0_SHIFT                           22
+
+/* NAND :: CONFIG :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_PAGE_SIZE_MASK                            0x00300000
+#define BCHP_NAND_CONFIG_PAGE_SIZE_SHIFT                           20
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_512                     0
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_2KB                     1
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_4KB                     2
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_8KB                     3
+
+/* NAND :: CONFIG :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_reserved1_MASK                            0x00080000
+#define BCHP_NAND_CONFIG_reserved1_SHIFT                           19
+
+/* NAND :: CONFIG :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_MASK                        0x00070000
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_SHIFT                       16
+
+/* NAND :: CONFIG :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_reserved2_MASK                            0x00008000
+#define BCHP_NAND_CONFIG_reserved2_SHIFT                           15
+
+/* NAND :: CONFIG :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_MASK                        0x00007000
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_SHIFT                       12
+
+/* NAND :: CONFIG :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_reserved3_MASK                            0x00000800
+#define BCHP_NAND_CONFIG_reserved3_SHIFT                           11
+
+/* NAND :: CONFIG :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_MASK                        0x00000700
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_SHIFT                       8
+
+/* NAND :: CONFIG :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_reserved4_MASK                            0x000000ff
+#define BCHP_NAND_CONFIG_reserved4_SHIFT                           0
+
+/***************************************************************************
+ *TIMING_1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_tWP_MASK                                0xf0000000
+#define BCHP_NAND_TIMING_1_tWP_SHIFT                               28
+#define BCHP_NAND_TIMING_1_tWP_DEFAULT                             6
+
+/* NAND :: TIMING_1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_tWH_MASK                                0x0f000000
+#define BCHP_NAND_TIMING_1_tWH_SHIFT                               24
+#define BCHP_NAND_TIMING_1_tWH_DEFAULT                             5
+
+/* NAND :: TIMING_1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_tRP_MASK                                0x00f00000
+#define BCHP_NAND_TIMING_1_tRP_SHIFT                               20
+#define BCHP_NAND_TIMING_1_tRP_DEFAULT                             7
+
+/* NAND :: TIMING_1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_tREH_MASK                               0x000f0000
+#define BCHP_NAND_TIMING_1_tREH_SHIFT                              16
+#define BCHP_NAND_TIMING_1_tREH_DEFAULT                            4
+
+/* NAND :: TIMING_1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_tCS_MASK                                0x0000f000
+#define BCHP_NAND_TIMING_1_tCS_SHIFT                               12
+#define BCHP_NAND_TIMING_1_tCS_DEFAULT                             8
+
+/* NAND :: TIMING_1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_tCLH_MASK                               0x00000f00
+#define BCHP_NAND_TIMING_1_tCLH_SHIFT                              8
+#define BCHP_NAND_TIMING_1_tCLH_DEFAULT                            4
+
+/* NAND :: TIMING_1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_tALH_MASK                               0x000000f0
+#define BCHP_NAND_TIMING_1_tALH_SHIFT                              4
+#define BCHP_NAND_TIMING_1_tALH_DEFAULT                            5
+
+/* NAND :: TIMING_1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_tADL_MASK                               0x0000000f
+#define BCHP_NAND_TIMING_1_tADL_SHIFT                              0
+#define BCHP_NAND_TIMING_1_tADL_DEFAULT                            11
+
+/***************************************************************************
+ *TIMING_2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CLK_SELECT_MASK                         0x80000000
+#define BCHP_NAND_TIMING_2_CLK_SELECT_SHIFT                        31
+#define BCHP_NAND_TIMING_2_CLK_SELECT_DEFAULT                      0
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_108                      0
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_216                      1
+
+/* NAND :: TIMING_2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_reserved0_MASK                          0x7fffe000
+#define BCHP_NAND_TIMING_2_reserved0_SHIFT                         13
+
+/* NAND :: TIMING_2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_tWB_MASK                                0x00001e00
+#define BCHP_NAND_TIMING_2_tWB_SHIFT                               9
+#define BCHP_NAND_TIMING_2_tWB_DEFAULT                             15
+
+/* NAND :: TIMING_2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_tWHR_MASK                               0x000001f0
+#define BCHP_NAND_TIMING_2_tWHR_SHIFT                              4
+#define BCHP_NAND_TIMING_2_tWHR_DEFAULT                            9
+
+/* NAND :: TIMING_2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_tREAD_MASK                              0x0000000f
+#define BCHP_NAND_TIMING_2_tREAD_SHIFT                             0
+#define BCHP_NAND_TIMING_2_tREAD_DEFAULT                           6
+
+/***************************************************************************
+ *SEMAPHORE - Semaphore
+ ***************************************************************************/
+/* NAND :: SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_NAND_SEMAPHORE_reserved0_MASK                         0xffffff00
+#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT                        8
+
+/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK                    0x000000ff
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT                   0
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT                 0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID - Nand Flash Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK                      0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT                     24
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK                      0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT                     16
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK                      0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT                     8
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK                      0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT                     0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK                  0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT                 24
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK                  0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT                 16
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK                  0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT                 8
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK                  0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT                 0
+
+/***************************************************************************
+ *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
+ ***************************************************************************/
+/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT                8
+
+/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK                    0x000000ff
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT                   0
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT                 0
+
+/***************************************************************************
+ *INTFC_STATUS - Nand Flash Interface Status
+ ***************************************************************************/
+/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK                     0x80000000
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT                    31
+
+/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK                    0x40000000
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT                   30
+
+/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK                    0x20000000
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT                   29
+
+/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK               0x10000000
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT              28
+
+/* NAND :: INTFC_STATUS :: ERASED [27:27] */
+#define BCHP_NAND_INTFC_STATUS_ERASED_MASK                         0x08000000
+#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT                        27
+
+/* NAND :: INTFC_STATUS :: reserved0 [26:08] */
+#define BCHP_NAND_INTFC_STATUS_reserved0_MASK                      0x07ffff00
+#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT                     8
+
+/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK                   0x000000ff
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT                  0
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT                0
+
+/***************************************************************************
+ *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT                 0
+
+/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT            0
+
+/***************************************************************************
+ *ECC_CORR_ADDR - ECC Correctable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT                    0
+
+/***************************************************************************
+ *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK                  0xfff80000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT                 19
+
+/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK                     0x00070000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT                    16
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT                  0
+
+/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK                0x0000ffff
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT               0
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT             0
+
+/***************************************************************************
+ *ECC_UNC_ADDR - ECC Uncorrectable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK                        0xffffffff
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT                       0
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT                     0
+
+/***************************************************************************
+ *READ_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT        0
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:05] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK               0xffffffe0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT              5
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD [04:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_MASK     0x0000001f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_SHIFT    0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_DEFAULT  1
+
+/***************************************************************************
+ *ONFI_STATUS - ONFI Status
+ ***************************************************************************/
+/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK                  0xf0000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT                 28
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT               0
+
+/* NAND :: ONFI_STATUS :: reserved0 [27:06] */
+#define BCHP_NAND_ONFI_STATUS_reserved0_MASK                       0x0fffffc0
+#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT                      6
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK              0x00000020
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT             5
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK              0x00000010
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT             4
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK              0x00000008
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT             3
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK              0x00000004
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT             2
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK              0x00000002
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT             1
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK              0x00000001
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT             0
+
+/***************************************************************************
+ *ONFI_DEBUG_DATA - ONFI Debug Data
+ ***************************************************************************/
+/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK             0xffffffff
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT            0
+
+/***************************************************************************
+ *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK               0xfff80000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT              19
+
+/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK                  0x00070000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT                 16
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT               0
+
+/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK             0x0000ffff
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT            0
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT          0
+
+/***************************************************************************
+ *FLASH_READ_ADDR - Flash Read Data Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT                    0
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT                  0
+
+/***************************************************************************
+ *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK             0xfff80000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT            19
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK                0x00070000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT               16
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT             0
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK           0x0000ffff
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT          0
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT        0
+
+/***************************************************************************
+ *PROGRAM_PAGE_ADDR - Page Program Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK                   0xffffffff
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT                  0
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT                0
+
+/***************************************************************************
+ *COPY_BACK_EXT_ADDR - Copy Back Extended Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK                0xfff80000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT               19
+
+/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK                   0x00070000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT                  16
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT                0
+
+/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK              0x0000ffff
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT             0
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT           0
+
+/***************************************************************************
+ *COPY_BACK_ADDR - Copy Back Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK                      0xffffffff
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT                     0
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT                   0
+
+/***************************************************************************
+ *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK              0xfff80000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT             19
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK                 0x00070000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT                16
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT              0
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK            0x0000ffff
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT           0
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT         0
+
+/***************************************************************************
+ *BLOCK_ERASE_ADDR - Block Erase Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK                    0xffffffff
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT                   0
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT                 0
+
+/***************************************************************************
+ *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
+ ***************************************************************************/
+/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT                 0
+
+/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT            0
+
+/***************************************************************************
+ *INV_READ_ADDR - Flash Invalid Data Address
+ ***************************************************************************/
+/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT                    0
+
+/***************************************************************************
+ *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
+ ***************************************************************************/
+/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK                 0xffffffff
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT                0
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT              0
+
+/***************************************************************************
+ *ACC_CONTROL_CS1 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS1 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS1 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS1 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS1 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS1_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS1 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS1 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS1_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS1_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS1_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS1_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS1_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS1_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS1_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS1_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS1_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS1_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS1_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS1 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS1 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS1_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS2 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS2 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS2 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS2 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS2 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS2_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS2 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS2 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS2_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS2_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS2_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS2_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS2 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS2_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS2_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS2_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS2_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS2_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS2_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS2_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS2_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS3 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS3 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS3 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS3 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS3 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS3_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS3 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS3 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS3_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS3_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS3_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS3_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS3 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS3_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS3_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS3_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS3_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS3_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS3_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS3_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS3 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS3 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS3_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS4 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS4 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS4 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS4 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS4 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS4_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS4 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS4 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS4_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS4_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS4_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS4_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS4 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS4_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS4_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS4_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS4_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS4_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS4_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS4_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS4 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS4 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS4_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS5 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS5 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS5 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS5 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS5 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS5 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS5 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS5 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS5 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS5 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS5 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS5 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS5 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS5 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS5 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS5_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS5_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS5 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS5 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS5_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS5_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS5 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS5 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS5_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS5_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS5 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS5 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS5_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS5_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS5 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS5 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS5_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS5_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS5 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS5 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS5_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS5_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS5_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS5 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS5_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS5_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS5_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS5 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS5_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS5_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS5_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS5 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS5_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS5_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS5_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS5 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS5_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS5_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS5_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS5 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS5_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS5_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS5_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS5 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS5_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS5_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS5_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS5 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS5_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS5_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS5_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS5 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS5 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS5 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS5_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS5_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS5 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS5_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS5_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS5_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS5 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS5_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS5_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS5_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS5 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS5_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS5_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS5_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT      255
+
+/***************************************************************************
+ *LL_OP - Nand Flash Low Level Operation
+ ***************************************************************************/
+/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
+#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK                           0x80000000
+#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT                          31
+#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT                        0
+
+/* NAND :: LL_OP :: reserved0 [30:20] */
+#define BCHP_NAND_LL_OP_reserved0_MASK                             0x7ff00000
+#define BCHP_NAND_LL_OP_reserved0_SHIFT                            20
+
+/* NAND :: LL_OP :: CLE [19:19] */
+#define BCHP_NAND_LL_OP_CLE_MASK                                   0x00080000
+#define BCHP_NAND_LL_OP_CLE_SHIFT                                  19
+#define BCHP_NAND_LL_OP_CLE_DEFAULT                                0
+
+/* NAND :: LL_OP :: ALE [18:18] */
+#define BCHP_NAND_LL_OP_ALE_MASK                                   0x00040000
+#define BCHP_NAND_LL_OP_ALE_SHIFT                                  18
+#define BCHP_NAND_LL_OP_ALE_DEFAULT                                0
+
+/* NAND :: LL_OP :: WE [17:17] */
+#define BCHP_NAND_LL_OP_WE_MASK                                    0x00020000
+#define BCHP_NAND_LL_OP_WE_SHIFT                                   17
+#define BCHP_NAND_LL_OP_WE_DEFAULT                                 0
+
+/* NAND :: LL_OP :: RE [16:16] */
+#define BCHP_NAND_LL_OP_RE_MASK                                    0x00010000
+#define BCHP_NAND_LL_OP_RE_SHIFT                                   16
+#define BCHP_NAND_LL_OP_RE_DEFAULT                                 0
+
+/* NAND :: LL_OP :: DATA [15:00] */
+#define BCHP_NAND_LL_OP_DATA_MASK                                  0x0000ffff
+#define BCHP_NAND_LL_OP_DATA_SHIFT                                 0
+#define BCHP_NAND_LL_OP_DATA_DEFAULT                               0
+
+/***************************************************************************
+ *LL_RDDATA - Nand Flash Low Level Read Data
+ ***************************************************************************/
+/* NAND :: LL_RDDATA :: reserved0 [31:16] */
+#define BCHP_NAND_LL_RDDATA_reserved0_MASK                         0xffff0000
+#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT                        16
+
+/* NAND :: LL_RDDATA :: DATA [15:00] */
+#define BCHP_NAND_LL_RDDATA_DATA_MASK                              0x0000ffff
+#define BCHP_NAND_LL_RDDATA_DATA_SHIFT                             0
+#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT                           0
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE                          0x00002a00
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_START                         0
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_END                           127
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE                  32
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+/* NAND :: FLASH_CACHEi :: WORD [31:00] */
+#define BCHP_NAND_FLASH_CACHEi_WORD_MASK                           0xffffffff
+#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT                          0
+
+
+#endif /* #ifndef BCHP_NAND_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_sdio_0_cfg.h b/include/linux/brcmstb/7344b0/bchp_sdio_0_cfg.h
new file mode 100644
index 0000000..786f6c6
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_sdio_0_cfg.h
@@ -0,0 +1,589 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 31 14:09:57 2011
+ *                 MD5 Checksum         b0a0062767e487fe78d25d07b5b21b78
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_sdio_0_cfg.h $
+ * 
+ * Hydra_Software_Devel/2   5/31/11 3:23p albertl
+ * SW7344-40: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SDIO_0_CFG_H__
+#define BCHP_SDIO_0_CFG_H__
+
+/***************************************************************************
+ *SDIO_0_CFG - SDIO (CARD) Configuration Registers
+ ***************************************************************************/
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1          0x00003600 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2          0x00003604 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL               0x00003608 /* SDIO TP_OUT Control Register */
+#define BCHP_SDIO_0_CFG_CAP_REG0                 0x0000360c /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_CAP_REG1                 0x00003610 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET1                  0x00003614 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET2                  0x00003618 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY           0x0000361c /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV               0x00003620 /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_IP_DLY                   0x00003630 /* SDIO Host input delay register */
+#define BCHP_SDIO_0_CFG_OP_DLY                   0x00003634 /* SDIO Host output delay register */
+#define BCHP_SDIO_0_CFG_SCRATCH                  0x000036fc /* SDIO Scratch Register */
+#define BCHP_SDIO_0_CFG_VERSION                  0x000036f0 /* SDIO VERSION Register */
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL1 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_SEL_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_MASK    0x80000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_SHIFT   31
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_DEFAULT 0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_LEV [30:30] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_MASK       0x40000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_SHIFT      30
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_DEFAULT    1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: CFG_RESERVED [29:29] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_MASK          0x20000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_SHIFT         29
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_DEFAULT       0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: RETUNING_REQ [28:28] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_MASK          0x10000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_SHIFT         28
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_DEFAULT       0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DDR_TAP_DELAY [27:24] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_MASK         0x0f000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_SHIFT        24
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_DEFAULT      0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DELAY_CTRL [23:21] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_MASK            0x00e00000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_SHIFT           21
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_DEFAULT         0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_ENA [20:20] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_MASK       0x00100000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_SHIFT      20
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_DEFAULT    1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_PULSE [19:19] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_MASK     0x00080000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_SHIFT    19
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_DEFAULT  0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DATA_PENDING [18:18] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_MASK          0x00040000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_SHIFT         18
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_DEFAULT       0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WR_FLUSH [17:17] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_MASK              0x00020000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_SHIFT             17
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_DEFAULT           0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: MF_NUM_WR [16:16] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_MASK             0x00010000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_SHIFT            16
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_DEFAULT          0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WORD_ABO [15:15] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_MASK              0x00008000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_SHIFT             15
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_DEFAULT           0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NBO [14:14] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_MASK             0x00004000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_SHIFT            14
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_DEFAULT          0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NHW [13:13] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_MASK             0x00002000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_SHIFT            13
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_DEFAULT          1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: BUFFER_ABO [12:12] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_MASK            0x00001000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_SHIFT           12
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_DEFAULT         1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_BUF_ACC [11:11] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_MASK           0x00000800
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_SHIFT          11
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_DEFAULT        1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SEQ_EN [10:10] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_MASK            0x00000400
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_SHIFT           10
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_DEFAULT         0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_RD_THRESH [09:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_MASK         0x000003e0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_SHIFT        5
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_DEFAULT      2
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SIZE [04:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_MASK              0x0000001f
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_SHIFT             0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_DEFAULT           4
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL2 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved0 [31:08] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_MASK             0xffffff00
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_SHIFT            8
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_BYTE [07:06] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_MASK     0x000000c0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_SHIFT    6
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_DEFAULT  0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved1 [05:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_MASK             0x00000020
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_SHIFT            5
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_HW [04:04] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_MASK       0x00000010
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_SHIFT      4
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_DEFAULT    0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_WR [03:02] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_MASK      0x0000000c
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_SHIFT     2
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_DEFAULT   0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_RD [01:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_MASK      0x00000003
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_SHIFT     0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_DEFAULT   0
+
+/***************************************************************************
+ *TP_OUT_SEL - SDIO TP_OUT Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TP_OUT_SEL :: reserved0 [31:01] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_MASK                  0xfffffffe
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_SHIFT                 1
+
+/* SDIO_0_CFG :: TP_OUT_SEL :: TP_OUT_SELECT [00:00] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_MASK              0x00000001
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_SHIFT             0
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_DEFAULT           0
+
+/***************************************************************************
+ *CAP_REG0 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG0 :: DDR50_SUPPORT [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_SHIFT               31
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_DEFAULT             0
+
+/* SDIO_0_CFG :: CAP_REG0 :: SD104_SUPPORT [30:30] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_MASK                0x40000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_SHIFT               30
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_DEFAULT             0
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDR50 [29:29] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_MASK                        0x20000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_SHIFT                       29
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_DEFAULT                     0
+
+/* SDIO_0_CFG :: CAP_REG0 :: SLOT_TYPE [28:27] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_MASK                    0x18000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_SHIFT                   27
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_DEFAULT                 0
+
+/* SDIO_0_CFG :: CAP_REG0 :: ASYNCH_INT_SUPPORT [26:26] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_MASK           0x04000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_SHIFT          26
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_DEFAULT        0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 64B_SYS_BUS_SUPPORT [25:25] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_MASK          0x02000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_SHIFT         25
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_DEFAULT       0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 1_8V_SUPPORT [24:24] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_MASK                 0x01000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_SHIFT                24
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_DEFAULT              0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_0V_SUPPORT [23:23] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_MASK                 0x00800000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_SHIFT                23
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_DEFAULT              0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_3V_SUPPORT [22:22] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_MASK                 0x00400000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_SHIFT                22
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_DEFAULT              1
+
+/* SDIO_0_CFG :: CAP_REG0 :: SUSP_RES_SUPPORT [21:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_MASK             0x00200000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_SHIFT            21
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_DEFAULT          1
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDMA_SUPPORT [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_MASK                 0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_SHIFT                20
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_DEFAULT              1
+
+/* SDIO_0_CFG :: CAP_REG0 :: HIGH_SPEED_SUPPORT [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_MASK           0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_SHIFT          19
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_DEFAULT        1
+
+/* SDIO_0_CFG :: CAP_REG0 :: ADMA2_SUPPORT [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_MASK                0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_SHIFT               18
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_DEFAULT             1
+
+/* SDIO_0_CFG :: CAP_REG0 :: EXTENDED_MEDIA_SUPPORT [17:17] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_MASK       0x00020000
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_SHIFT      17
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_DEFAULT    1
+
+/* SDIO_0_CFG :: CAP_REG0 :: MAX_BL [16:15] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_MASK                       0x00018000
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_SHIFT                      15
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_DEFAULT                    1
+
+/* SDIO_0_CFG :: CAP_REG0 :: BASE_FREQ [14:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_MASK                    0x00007f80
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_SHIFT                   7
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_DEFAULT                 100
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_CLK_UNIT [06:06] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_MASK             0x00000040
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_SHIFT            6
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_DEFAULT          1
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_FREQ [05:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_MASK                 0x0000003f
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_SHIFT                0
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_DEFAULT              50
+
+/***************************************************************************
+ *CAP_REG1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_REG_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_MASK             0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_SHIFT            31
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_DEFAULT          0
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved0 [30:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_MASK                    0x7fe00000
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_SHIFT                   21
+
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_1_stuff [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_MASK                  0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_SHIFT                 20
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_DEFAULT               0
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_BLK_MODE [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_MASK                 0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_SHIFT                19
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_DEFAULT              0
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_MODE [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_MASK                     0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_SHIFT                    18
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_DEFAULT                  1
+
+/* SDIO_0_CFG :: CAP_REG1 :: CLK_MULT [17:10] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_MASK                     0x0003fc00
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_SHIFT                    10
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_DEFAULT                  0
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_MODES [09:08] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_MASK               0x00000300
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_SHIFT              8
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_DEFAULT            2
+
+/* SDIO_0_CFG :: CAP_REG1 :: USE_TUNING [07:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_MASK                   0x00000080
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_SHIFT                  7
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_DEFAULT                0
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_TIMER [06:03] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_MASK               0x00000078
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_SHIFT              3
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_DEFAULT            10
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_D_SUPPORT [02:02] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_MASK             0x00000004
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_SHIFT            2
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_DEFAULT          0
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_C_SUPPORT [01:01] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_MASK             0x00000002
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_SHIFT            1
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_DEFAULT          0
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_A_SUPPORT [00:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_MASK             0x00000001
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_SHIFT            0
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_DEFAULT          0
+
+/***************************************************************************
+ *PRESET1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET1 :: PRESET1_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_DEFAULT           0
+
+/* SDIO_0_CFG :: PRESET1 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET100 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_MASK                     0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_SHIFT                    16
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_DEFAULT                  0
+
+/* SDIO_0_CFG :: PRESET1 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET50 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_MASK                      0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_SHIFT                     0
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_DEFAULT                   1
+
+/***************************************************************************
+ *PRESET2 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET2 :: PRESET2_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_DEFAULT           0
+
+/* SDIO_0_CFG :: PRESET2 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET25 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_MASK                      0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_SHIFT                     16
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_DEFAULT                   2
+
+/* SDIO_0_CFG :: PRESET2 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET12P5 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_MASK                    0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_SHIFT                   0
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_DEFAULT                 3
+
+/***************************************************************************
+ *SD_CLOCK_DELAY - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_SEL [31:31] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_MASK        0x80000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_SHIFT       31
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_DEFAULT     1
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY_OVERRIDE [30:30] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_MASK 0x40000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_SHIFT 30
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_DEFAULT 0
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved0 [29:12] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_MASK              0x3ffff000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_SHIFT             12
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: OUTPUT_CLOCK_DELAY [11:08] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_MASK     0x00000f00
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_SHIFT    8
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_DEFAULT  0
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INTERNAL_CLOCK_DELAY [07:04] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_MASK   0x000000f0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_SHIFT  4
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_DEFAULT 0
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_MASK      0x0000000f
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_SHIFT     0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_DEFAULT   0
+
+/***************************************************************************
+ *SD_PAD_DRV - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_PAD_DRV :: OVERRIDE_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_SHIFT               31
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_DEFAULT             0
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved0 [30:23] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_MASK                  0x7f800000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_SHIFT                 23
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CLK_VAL [22:20] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_MASK                    0x00700000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_SHIFT                   20
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_DEFAULT                 5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved1 [19:19] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_MASK                  0x00080000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_SHIFT                 19
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CMD_VAL [18:16] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_MASK                    0x00070000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_SHIFT                   16
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_DEFAULT                 5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved2 [15:15] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_MASK                  0x00008000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_SHIFT                 15
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT3_VAL [14:12] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_MASK                   0x00007000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_SHIFT                  12
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_DEFAULT                5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved3 [11:11] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_MASK                  0x00000800
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_SHIFT                 11
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT2_VAL [10:08] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_MASK                   0x00000700
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_SHIFT                  8
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_DEFAULT                5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved4 [07:07] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_MASK                  0x00000080
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_SHIFT                 7
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT1_VAL [06:04] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_MASK                   0x00000070
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_SHIFT                  4
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_DEFAULT                5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved5 [03:03] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_MASK                  0x00000008
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_SHIFT                 3
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT0_VAL [02:00] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_MASK                   0x00000007
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_SHIFT                  0
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_DEFAULT                5
+
+/***************************************************************************
+ *IP_DLY - SDIO Host input delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_DEFAULT                   0
+
+/* SDIO_0_CFG :: IP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: IP_DLY :: IP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_DEFAULT               3
+
+/* SDIO_0_CFG :: IP_DLY :: reserved1 [15:06] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_MASK                      0x0000ffc0
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_SHIFT                     6
+
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_DELAY [05:00] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_MASK                   0x0000003f
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_DEFAULT                0
+
+/***************************************************************************
+ *OP_DLY - SDIO Host output delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_DEFAULT                   0
+
+/* SDIO_0_CFG :: OP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: OP_DLY :: OP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_DEFAULT               3
+
+/* SDIO_0_CFG :: OP_DLY :: reserved1 [15:04] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_MASK                      0x0000fff0
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_SHIFT                     4
+
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_MASK                   0x0000000f
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_DEFAULT                0
+
+/***************************************************************************
+ *SCRATCH - SDIO Scratch Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SCRATCH :: SCRATCH_BITS [31:00] */
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_MASK                  0xffffffff
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_SHIFT                 0
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_DEFAULT               0
+
+/***************************************************************************
+ *VERSION - SDIO VERSION Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VERSION :: SD_VER [31:24] */
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_MASK                        0xff000000
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_SHIFT                       24
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_DEFAULT                     48
+
+/* SDIO_0_CFG :: VERSION :: MMC_VER [23:16] */
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_MASK                       0x00ff0000
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_SHIFT                      16
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_DEFAULT                    67
+
+/* SDIO_0_CFG :: VERSION :: REV [15:08] */
+#define BCHP_SDIO_0_CFG_VERSION_REV_MASK                           0x0000ff00
+#define BCHP_SDIO_0_CFG_VERSION_REV_SHIFT                          8
+#define BCHP_SDIO_0_CFG_VERSION_REV_DEFAULT                        160
+
+/* SDIO_0_CFG :: VERSION :: A2S_VER [07:00] */
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_MASK                       0x000000ff
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_SHIFT                      0
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_DEFAULT                    1
+
+#endif /* #ifndef BCHP_SDIO_0_CFG_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/7344b0/bchp_sun_top_ctrl.h
new file mode 100644
index 0000000..8542101
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_sun_top_ctrl.h
@@ -0,0 +1,6592 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug  8 20:14:25 2011
+ *                 MD5 Checksum         bdb30c5d18c5d13008bcd4430a6d3384
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_sun_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/3   8/9/11 11:21a pntruong
+ * SW7344-144: Synced with central RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SUN_TOP_CTRL_H__
+#define BCHP_SUN_TOP_CTRL_H__
+
+/***************************************************************************
+ *SUN_TOP_CTRL - Top Control registers
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID         0x00404000 /* Chip family ID */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID             0x00404004 /* Product Revision ID */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x0040401c /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x00404020 /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x00404024 /* Bond option value register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x00404028 /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x0040402c /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x00404030 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x00404034 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x00404038 /* Semaphore channel 0 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x0040403c /* Semaphore channel 1 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x00404040 /* Semaphore channel 2 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x00404044 /* Semaphore channel 3 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x00404048 /* Semaphore channel 4 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x0040404c /* Semaphore channel 5 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x00404050 /* Semaphore channel 6 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x00404054 /* Semaphore channel 7 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x00404058 /* Semaphore channel 8 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x0040405c /* Semaphore channel 9 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x00404060 /* Semaphore channel 10 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x00404064 /* Semaphore channel 11 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x00404068 /* Semaphore channel 12 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x0040406c /* Semaphore channel 13 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x00404070 /* Semaphore channel 14 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x00404074 /* Semaphore channel 15 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x00404078 /* General watchdog timer 0 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x0040407c /* General watchdog timer 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x00404080 /* General control register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x00404084 /* General control register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x00404088 /* General control register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x0040408c /* General control register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x00404090 /* General control register 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x00404094 /* General control register 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x00404098 /* General status register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x0040409c /* General status register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x004040a0 /* General status register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x00404100 /* Pinmux control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x00404104 /* Pinmux control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x00404108 /* Pinmux control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x0040410c /* Pinmux control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x00404110 /* Pinmux control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x00404114 /* Pinmux control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x00404118 /* Pinmux control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x0040411c /* Pinmux control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x00404120 /* Pinmux control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x00404124 /* Pinmux control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10        0x00404128 /* Pinmux control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11        0x0040412c /* Pinmux control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12        0x00404130 /* Pinmux control register 12 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13        0x00404134 /* Pinmux control register 13 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14        0x00404138 /* Pinmux control register 14 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15        0x0040413c /* Pinmux control register 15 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16        0x00404140 /* Pinmux control register 16 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17        0x00404144 /* Pinmux control register 17 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18        0x00404148 /* Pinmux control register 18 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x0040414c /* Pad pull-up/pull-down control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x00404150 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x00404154 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x00404158 /* Pad pull-up/pull-down control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x0040415c /* Pad pull-up/pull-down control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5     0x00404160 /* Pad pull-up/pull-down control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6     0x00404164 /* Pad pull-up/pull-down control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7     0x00404168 /* Pad pull-up/pull-down control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8     0x0040416c /* Pad pull-up/pull-down control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9     0x00404170 /* Pad pull-up/pull-down control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10    0x00404174 /* Pad pull-up/pull-down control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11    0x00404178 /* Pad pull-up/pull-down control register 11 */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x0040417c /* Bypass clock unselect register 0 */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x00404300 /* Reset control */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE    0x00404304 /* Reset source enable */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET        0x00404308 /* Software master reset */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION     0x0040430c /* Hardware reset extension */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR          0x00404310 /* Reset Monitor */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x00404314 /* Reset history */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET          0x00404318 /* Software init 0 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR        0x0040431c /* Software init 0 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS       0x00404320 /* Software init 0 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR  0x00404324 /* Security software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET          0x00404330 /* Software init 1 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR        0x00404334 /* Software init 1 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS       0x00404338 /* Software init 1 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR  0x0040433c /* Security software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x00404364 /* Scratch register */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x00404368 /* Spare control bits reserved for future use */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x00404380 /* Test port control */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x00404384 /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x00404388 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x0040438c /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x00404390 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x00404394 /* EJTAG input bus enables */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x00404398 /* EJTAG output select */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL        0x0040439c /* UART Router select */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL             0x004043a0 /* VTRAP Control */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS           0x004043a4 /* VTRAP Status */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x00404400 /* Serial Slave Port configuration register */
+#define BCHP_SUN_TOP_CTRL_SERS_REV               0x00404420 /* SERS Revision Register */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x00404424 /* SERS Configuration Register */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x00404514 /* Block select for RO testmode */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION     0x00404518 /* Test configuration */
+
+/***************************************************************************
+ *CHIP_FAMILY_ID - Chip family ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT    1933836304
+
+/***************************************************************************
+ *PRODUCT_ID - Product Revision ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK               0xffffffff
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT            1933836304
+
+/***************************************************************************
+ *BSP_FEATURE_TABLE_ADDR - BSP feature table address
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_VALUE_0 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xfffff800
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            11
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_reset_outb_def_val [10:10] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_DEFAULT 1
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [09:06] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK      0x000003c0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT   10
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_mips_freq [05:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_mips_freq_MASK       0x00000030
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_mips_freq_SHIFT      4
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_mips_freq_DEFAULT    0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [03:03] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_DEFAULT 0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd [02:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_MASK            0x00000007
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_DEFAULT         0
+
+/***************************************************************************
+ *STRAP_VALUE_1 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xffffffe0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            5
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias [04:02] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_MASK      0x0000001c
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_DEFAULT   2
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xtal_enable_ext_cml [01:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xtal_enable_ext_cml_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xtal_enable_ext_cml_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xtal_enable_ext_cml_DEFAULT 0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK     0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT  1
+
+/***************************************************************************
+ *BOND_STATUS - Bond option value register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1
+
+/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_0 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_1 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_0 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_freq_pllmips [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_freq_pllmips_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_freq_pllmips_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_freq_pllmips_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_genet1_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet1_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet1_disable_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet1_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_temp_sensor_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_svc_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_directv_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_pvtmon_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pvtmon_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pvtmon_disable_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pvtmon_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_moca_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sds0_tuner_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hd_display_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ephy_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tfec_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ldpc_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_adjust_voltage [14:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_adjust_voltage_MASK 0x00007c00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_adjust_voltage_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_adjust_voltage_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_1 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_30 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_29 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_28 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_27 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_26 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_25 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_24 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_23 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_22 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_21 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_20 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_19 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_18 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_17 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_16 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_15 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_14 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_0 [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_DEFAULT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_0 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_1 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_0 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_freq_pllmips [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_freq_pllmips_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_freq_pllmips_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_genet1_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet1_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet1_disable_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_temp_sensor_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_temp_sensor_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_temp_sensor_disable_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_svc_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_svc_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_svc_disable_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_directv_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_pvtmon_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pvtmon_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pvtmon_disable_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_moca_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sds0_tuner_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sds0_tuner_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sds0_tuner_disable_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hd_display_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ephy_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tfec_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec_disable_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ldpc_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc_disable_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_adjust_voltage [14:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_adjust_voltage_MASK 0x00007c00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_adjust_voltage_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_1 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_30 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_30_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_30_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_29 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_28 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_27 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_26 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_25 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_24 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_23 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_22 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_21 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_20 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_19 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_18 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_17 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_16 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_15 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_14 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 6
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 2
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_0 [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_SHIFT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_SHIFT 0
+
+/***************************************************************************
+ *SEMAPHORE_0 - Semaphore channel 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_1 - Semaphore channel 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_2 - Semaphore channel 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_3 - Semaphore channel 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_4 - Semaphore channel 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_5 - Semaphore channel 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_6 - Semaphore channel 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_7 - Semaphore channel 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_8 - Semaphore channel 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_9 - Semaphore channel 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_10 - Semaphore channel 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_11 - Semaphore channel 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_12 - Semaphore channel 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_13 - Semaphore channel 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_14 - Semaphore channel 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_15 - Semaphore channel 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *GEN_WATCHDOG_0 - General watchdog timer 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0
+
+/***************************************************************************
+ *GEN_WATCHDOG_1 - General watchdog timer 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK     0x80000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT    31
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK     0x40000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT    30
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK     0x20000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT    29
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK     0x10000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT    28
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK     0x02000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT    25
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK     0x01000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT    24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK     0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT    23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK     0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT    22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK     0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT    21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK     0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT    20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK     0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT    19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK     0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT    18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK     0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT    17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK     0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT    16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: mii_genet_mac_select [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_genet_mac_select_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_genet_mac_select_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_genet_mac_select_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_1 - General control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_2 - General control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_3 - General control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_4 - General control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_5 - General control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK          0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT         8
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_1 - General status register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_2 - General status register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   8
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_amp_en [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_sel [06:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_GMII_CMOS_3P3V 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_RGMII_CMOS_2P5V 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_HSTL_CLASS1_1P5V 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_HSTL_CLASS1_1P8V 3
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_rx_pad_amp_en [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_rx_pad_amp_en_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_rx_pad_amp_en_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_rx_pad_amp_en_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_tx_pad_amp_en [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_tx_pad_amp_en_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_tx_pad_amp_en_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_tx_pad_amp_en_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_slew [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_slew_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_slew_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_slew_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_sel [01:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_GMII_CMOS_3P3V 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_RGMII_CMOS_2P5V 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_HSTL_CLASS1_1P5V 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_HSTL_CLASS1_1P8V 3
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_31_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_31_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_30_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_29_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_29_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_28_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_27_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_26_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_26_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_26_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_25_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_24_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_24_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_24_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_21_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_21_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_21_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_19_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_19_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_19_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_18_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_18_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_18_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_16_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_16_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_15_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_15_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_vregcntl [14:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_MASK 0x00007ffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_pwrdn [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_MASK    0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_SHIFT   1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_vregcntl_en [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_DEFAULT 1
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK    0xff000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT   24
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: mii_drive_src_0 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: mii_drive_sel_0 [22:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_MASK 0x00700000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_4 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_4_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_4_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_4 [18:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_MASK 0x00070000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_3 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_3_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_3_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_3 [14:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_MASK 0x00007000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_2 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_2_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_2_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_2 [10:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_MASK 0x00000700
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_1 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_1_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_1_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_1 [06:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_MASK 0x00000070
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_0 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_0_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_0_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_0 [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_16MA 7
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xf0000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   28
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_51 [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_51_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_51_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_51_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_50 [26:26] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_50_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_50_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_50_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_49 [25:25] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_49_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_49_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_49_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_48 [24:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_48_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_48_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_48_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_47 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_47_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_47_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_47_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_46 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_46_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_46_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_46_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_45 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_45_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_45_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_45_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_44 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_44_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_44_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_44_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_19_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_19_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_19_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_18_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_18_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_18_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_17_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_16_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_16_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_15_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_15_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_14_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_14_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_13_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_12_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_11_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_10_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_10_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_09 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_09_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_09_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_09_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_08 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_08_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_08_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_08_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_07 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_07_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_07_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_07_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_06 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_06_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_06_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_06_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_05 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_05_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_05_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_05_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_04 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_04_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_04_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_04_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_03_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_03_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_03_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_02_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_02_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_02_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_01 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_01_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_01_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_01_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_00 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_00_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_00_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_00_DEFAULT 1
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_DEFAULT 0
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_75 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_GPIO_75           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_VO_656_7          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_SDIO_CMD          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_SDS0_DEMOD_ERROR  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_SDS0_BERT_ERROR   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_PM_GPIO_75        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_74 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_GPIO_74           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_VO_656_6          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_SDIO_WPROT        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_SDS0_DEMOD_VALID  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_SDS0_BERT_VALID   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_PM_GPIO_74        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_73 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_GPIO_73           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_VO_656_5          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_SDIO_PRES         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_SDS0_DEMOD_SYNC   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_SDS0_BERT_SYNC    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_PM_GPIO_73        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_72 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_GPIO_72           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_VO_656_4          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_SDIO_PWR0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_SDS0_DEMOD_DATA   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_SDS0_BERT_DATA    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_PM_GPIO_72        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_71 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_GPIO_71           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_VO_656_3          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_SDIO_DATA3        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_SDS0_DEMOD_CLK    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_SDS0_BERT_CLK     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_PM_GPIO_71        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_70 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_GPIO_70           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_VO_656_2          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_EXT_IRQB_15       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_SDIO_DATA2        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_PM_GPIO_70        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_69 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_GPIO_69           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_VO_656_1          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_EXT_IRQB_14       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_SDIO_DATA1        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_PM_GPIO_69        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_68 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_GPIO_68           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_VO_656_0          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_EXT_IRQB_13       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_SDIO_DATA0        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_PM_GPIO_68        4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data1 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data1_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data1_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data1_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data1_EBI_DATA1       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data1_ALT_TP_IN_01    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data0 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_EBI_DATA0       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_ALT_TP_IN_00    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: clk_acc [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_clk_acc_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_clk_acc_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_clk_acc_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_clk_acc_CLK_ACC           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_clk_acc_EXT_SC_CLK        1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: usb0_pwron [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_usb0_pwron_MASK           0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_usb0_pwron_SHIFT          16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_usb0_pwron_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_usb0_pwron_USB0_PWRON     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_usb0_pwron_TP_IN_20       1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: aud_spdif [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_aud_spdif_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_aud_spdif_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_aud_spdif_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_aud_spdif_AUD_SPDIF       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_aud_spdif_RO_TEST_OUT     1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_78 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_78_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_78_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_78_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_78_GPIO_78           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_78_TTX_DATA          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_78_EXT_IRQB_15       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_78_PM_GPIO_78        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_77 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_77_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_77_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_77_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_77_GPIO_77           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_77_TTX_REQ           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_77_SDIO_LED          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_77_PM_GPIO_77        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_76 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_76_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_76_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_76_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_76_GPIO_76           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_76_VO_656_CLK        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_76_SDIO_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_76_PM_GPIO_76        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data9 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data9_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data9_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data9_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data9_EBI_DATA9       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data9_ALT_TP_IN_09    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data8 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_EBI_DATA8       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_ALT_TP_IN_08    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data7 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_EBI_DATA7       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_ALT_TP_IN_07    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data6 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_EBI_DATA6       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_ALT_TP_IN_06    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data5 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_EBI_DATA5       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_ALT_TP_IN_05    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data4 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_EBI_DATA4       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_ALT_TP_IN_04    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data3 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_EBI_DATA3       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_ALT_TP_IN_03    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data2 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_EBI_DATA2       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_ALT_TP_IN_02    1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr1 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr1_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr1_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr1_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr1_EBI_ADDR1       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr1_ALT_TP_IN_17    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr0 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_EBI_ADDR0       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_ALT_TP_IN_16    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data15 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_MASK           0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_SHIFT          20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_EBI_DATA15     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_ALT_TP_IN_15   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data14 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_MASK           0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_SHIFT          16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_EBI_DATA14     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_ALT_TP_IN_14   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data13 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_MASK           0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_SHIFT          12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_EBI_DATA13     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_ALT_TP_IN_13   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data12 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_MASK           0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_EBI_DATA12     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_ALT_TP_IN_12   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data11 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_MASK           0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_SHIFT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_EBI_DATA11     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_ALT_TP_IN_11   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data10 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_MASK           0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_EBI_DATA10     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_ALT_TP_IN_10   1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_4 - Pinmux control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr9 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr9_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr9_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr9_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr9_EBI_ADDR9       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr9_ALT_TP_IN_25    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr8 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_EBI_ADDR8       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_ALT_TP_OUT_24   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr7 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_EBI_ADDR7       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_ALT_TP_IN_23    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr6 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_EBI_ADDR6       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_ALT_TP_IN_22    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr5 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_EBI_ADDR5       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_ALT_TP_IN_21    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr4 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_EBI_ADDR4       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_ALT_TP_IN_20    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr3 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_EBI_ADDR3       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_ALT_TP_IN_19    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr2 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_EBI_ADDR2       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_ALT_TP_IN_18    1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_5 - Pinmux control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_82 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_82_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_82_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_82_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_82_GPIO_82           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_82_USB2_PWRFLT       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_82_PM_GPIO_82        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_81 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_81_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_81_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_81_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_81_GPIO_81           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_81_USB2_PWRON        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_81_PM_GPIO_81        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr15 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_MASK           0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_SHIFT          20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_EBI_ADDR15     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_ALT_TP_IN_31   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr14 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_MASK           0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_SHIFT          16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_EBI_ADDR14     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_ALT_TP_IN_30   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr13 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_MASK           0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_SHIFT          12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_EBI_ADDR13     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_ALT_TP_IN_29   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr12 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_MASK           0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_EBI_ADDR12     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_ALT_TP_OUT_28  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr11 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_MASK           0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_SHIFT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_EBI_ADDR11     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_ALT_TP_IN_27   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr10 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_MASK           0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_EBI_ADDR10     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_ALT_TP_IN_26   1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_6 - Pinmux control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_05 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_GPIO_05           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_CHIP2CI_MDO_5     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_PPKT_O_DATA_5     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_SDS0_O_DATA_5     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_I2S_BIDIR_CLK_IN  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_I2S_BIDIR_CLK_OUT 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_TP_OUT_09         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_PM_GPIO_05        7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_04 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_GPIO_04           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_CHIP2CI_MDO_4     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_PPKT_O_DATA_4     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_SDS0_O_DATA_4     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_I2S_BIDIR_SYNC_IN 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_I2S_BIDIR_SYNC_OUT 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_TP_OUT_08         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_PM_GPIO_04        7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_03 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_GPIO_03           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_CHIP2CI_MDO_3     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_PPKT_O_DATA_3     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_SDS0_O_DATA_3     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_I2S_BIDIR_DATA_IN 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_I2S_BIDIR_DATA_OUT 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_TP_OUT_07         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_PM_GPIO_03        7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_02 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_GPIO_02           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_CHIP2CI_MDO_2     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_PPKT_O_DATA_2     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_SDS0_O_DATA_2     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_TP_OUT_06         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_PM_GPIO_02        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_01 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_GPIO_01           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_CHIP2CI_MDO_1     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_PPKT_O_DATA_1     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_SDS0_O_DATA_1     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_TP_OUT_05         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_PM_GPIO_01        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_00 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_GPIO_00           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_CHIP2CI_MDO_0     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_PPKT_O_DATA_0     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_SDS0_O_DATA_0     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_TP_OUT_04         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_PM_GPIO_00        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_84 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_84_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_84_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_84_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_84_GPIO_84           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_84_USB3_PWRFLT       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_84_PM_GPIO_84        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_83 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_83_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_83_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_83_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_83_GPIO_83           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_83_USB3_PWRON        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_83_PM_GPIO_83        2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_7 - Pinmux control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_13 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_GPIO_13           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_CI2CHIP_MIVAL     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_PPKT_I_VALID      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_TP_OUT_17         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_PM_GPIO_13        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_12 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_GPIO_12           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_CI2CHIP_MISTRT    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_PPKT_I_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_TP_OUT_16         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_PM_GPIO_12        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_11 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_GPIO_11           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_CHIP2CI_MOCLK     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_PPKT_O_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_SDS0_O_CLK        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_CHIP2CI_MCLKO     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_TP_OUT_15         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_PM_GPIO_11        6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_10 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_GPIO_10           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_CHIP2CI_MCLKO     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_PPKT_O_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_SDS0_O_ERROR      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_CHIP2CI_MOCLK     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_TP_OUT_14         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_PM_GPIO_10        6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_09 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_GPIO_09           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_CHIP2CI_MOVAL     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_PPKT_O_VALID      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_SDS0_O_VALID      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_TP_OUT_13         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_PM_GPIO_09        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_08 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_GPIO_08           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_CHIP2CI_MOSTRT    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_PPKT_O_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_SDS0_O_SYNC       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_TP_OUT_12         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_PM_GPIO_08        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_07 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_GPIO_07           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_CHIP2CI_MDO_7     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_PPKT_O_DATA_7     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_SDS0_O_DATA_7     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_TP_OUT_11         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_PM_GPIO_07        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_06 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_GPIO_06           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_CHIP2CI_MDO_6     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_PPKT_O_DATA_6     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_SDS0_O_DATA_6     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_TP_OUT_10         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_PM_GPIO_06        5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_8 - Pinmux control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_24 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_GPIO_24           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_MII_RGMII_RXD_02  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_VEC_VSYNC_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_TP_IN_01          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_PM_GPIO_24        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_23 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_GPIO_23           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_MII_RGMII_RXD_03  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_VEC_VSYNC_0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_TP_IN_00          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_PM_GPIO_23        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_19 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_GPIO_19           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_SPI_S_MISO        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_PWM_3             2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_EXT_SC_CLK        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_AIO_EXTMCLK1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_CHIP2CC_SCTL      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_TP_OUT_23         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_PM_GPIO_19        7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_18 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_GPIO_18           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_SPI_S_SS0B        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_PWM_2             2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_AIO_EXTMCLK0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_CHIP2CC_SCLK      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_TP_OUT_22         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_PM_GPIO_18        6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_17 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_GPIO_17           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_I2S_O_SYNC        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_RMX_VALID0        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_CHIP2CC_SDO       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_TP_OUT_21         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_PM_GPIO_17        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_16 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_GPIO_16           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_I2S_O_DATA        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_RMX_PAUSE0        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_CC2CHIP_SDI       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_TP_OUT_20         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_PM_GPIO_16        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_15 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_GPIO_15           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_CI2CHIP_MICLK     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_PPKT_I_ERROR      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_CI2CHIP_MCLKI     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_TP_OUT_19         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_PM_GPIO_15        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_14 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_GPIO_14           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_CI2CHIP_MCLKI     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_PPKT_I_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_CI2CHIP_MICLK     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_TP_OUT_18         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_PM_GPIO_14        5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_9 - Pinmux control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_34 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_GPIO_34           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_MII_RGMII_TX_CLK  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_FSK_UART_MAN_DATA 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_TP_IN_11          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_PM_GPIO_34        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_31 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_31_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_31_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_31_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_31_GPIO_31           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_31_MII_RGMII_RX_CLK  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_31_TP_IN_08          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_31_PM_GPIO_31        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_30 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_30_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_30_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_30_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_30_GPIO_30           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_30_MII_COL           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_30_TP_IN_07          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_30_PM_GPIO_30        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_29 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_29_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_29_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_29_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_29_GPIO_29           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_29_MII_CRS           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_29_TP_IN_06          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_29_PM_GPIO_29        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_28 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_28_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_28_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_28_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_28_GPIO_28           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_28_MII_RXDV_RGMII_RXCTL 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_28_TP_IN_05          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_28_PM_GPIO_28        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_27 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_27_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_27_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_27_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_27_GPIO_27           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_27_MII_RX_ER         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_27_TP_IN_04          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_27_PM_GPIO_27        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_26 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_GPIO_26           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_MII_RGMII_RXD_00  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_VEC_HSYNC_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_TP_IN_03          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_PM_GPIO_26        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_25 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_GPIO_25           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_MII_RGMII_RXD_01  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_VEC_HSYNC_0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_TP_IN_02          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_PM_GPIO_25        4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_10 - Pinmux control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_33 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_GPIO_33          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_MII_MDC          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_EXT_IRQB_12      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_TP_IN_10         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_PM_GPIO_33       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_32 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_GPIO_32          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_MII_MDIO         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_EXT_IRQB_11      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_TP_IN_09         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_PM_GPIO_32       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_40 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_40_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_40_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_40_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_40_GPIO_40          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_40_MII_RGMII_TXD_00 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_40_TP_IN_17         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_40_PM_GPIO_40       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_39 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_39_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_39_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_39_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_39_GPIO_39          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_39_MII_RGMII_TXD_01 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_39_TP_IN_16         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_39_PM_GPIO_39       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_38 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_38_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_38_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_38_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_38_GPIO_38          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_38_MII_RGMII_TXD_02 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_38_TP_IN_15         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_38_PM_GPIO_38       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_37 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_37_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_37_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_37_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_37_GPIO_37          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_37_MII_RGMII_TXD_03 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_37_TP_IN_14         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_37_PM_GPIO_37       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_36 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_36_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_36_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_36_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_36_GPIO_36          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_36_MII_TXER         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_36_TP_IN_13         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_36_PM_GPIO_36       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_35 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_GPIO_35          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_MII_TXEN_RGMII_TXCTL 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_FSK_RX_DATA_BYP  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_TP_IN_12         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_PM_GPIO_35       4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_11 - Pinmux control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_49 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_GPIO_49          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_SC0_IO_AUX1      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_CI2CHIP_MDI_5    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_PPKT_I_DATA_5    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_TP_IN_26         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_PM_GPIO_49       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_48 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_GPIO_48          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_SC0_VCC          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_CI2CHIP_MDI_4    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_PPKT_I_DATA_4    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_TP_IN_25         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_PM_GPIO_48       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_47 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_GPIO_47          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_SC0_PRES         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_CI2CHIP_MDI_3    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_PPKT_I_DATA_3    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_TP_IN_24         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_PM_GPIO_47       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_46 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_GPIO_46          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_SC0_RST          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_CI2CHIP_MDI_2    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_PPKT_I_DATA_2    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_TP_IN_23         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_PM_GPIO_46       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_45 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_GPIO_45          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_SC0_CLK_OUT      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_CI2CHIP_MDI_1    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_PPKT_I_DATA_1    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_TP_IN_22         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_PM_GPIO_45       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_44 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_GPIO_44          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_SC0_IO           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_CI2CHIP_MDI_0    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_PPKT_I_DATA_0    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_TP_IN_21         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_PM_GPIO_44       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_42 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_42_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_42_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_42_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_42_GPIO_42          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_42_PWM_1            1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_42_TP_IN_19         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_42_PM_GPIO_42       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_41 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_GPIO_41          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_PWM_0            1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_PVTMON_DATA_FREQ 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_TP_IN_18         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_PM_GPIO_41       4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_12 - Pinmux control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_20 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_20_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_20_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_20_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_20_GPIO_20          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_20_SC1_IO_AUX1      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_20_PM_GPIO_20       2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_56 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_56_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_56_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_56_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_56_GPIO_56          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_56_SC1_VCC          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_56_ALT_TP_OUT_01    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_56_PM_GPIO_56       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_55 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_55_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_55_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_55_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_55_GPIO_55          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_55_SC1_PRES         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_55_ALT_TP_OUT_00    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_55_PM_GPIO_55       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_54 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_54_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_54_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_54_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_54_GPIO_54          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_54_SC1_RST          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_54_TP_IN_31         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_54_PM_GPIO_54       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_53 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_53_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_53_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_53_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_53_GPIO_53          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_53_SC1_CLK_OUT      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_53_TP_IN_30         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_53_PM_GPIO_53       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_52 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_52_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_52_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_52_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_52_GPIO_52          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_52_SC1_IO           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_52_TP_IN_29         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_52_PM_GPIO_52       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_51 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_GPIO_51          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_SC0_VPP          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_CI2CHIP_MDI_7    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_PPKT_I_DATA_7    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_TP_IN_28         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_PM_GPIO_51       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_50 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_GPIO_50          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_SC0_IO_AUX2      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_CI2CHIP_MDI_6    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_PPKT_I_DATA_6    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_TP_IN_27         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_PM_GPIO_50       5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_13 - Pinmux control register 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: rmx_clk0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_rmx_clk0_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_rmx_clk0_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_rmx_clk0_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_rmx_clk0_RMX_CLK0        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_rmx_clk0_ALT_TP_OUT_15   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: pkt_error0 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_MASK          0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_PKT_ERROR0    0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_SDS0_DEMOD_ERROR 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_SDS0_BERT_ERROR 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_MTSIF_RX_DATA_2 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_PM_PKT_ERROR0 4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: pkt_valid0 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_MASK          0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_SHIFT         20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_PKT_VALID0    0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_SDS0_DEMOD_VALID 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_SDS0_BERT_VALID 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_MTSIF_RX_DATA_1 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_PM_PKT_VALID0 4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: pkt_sync0 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_MASK           0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_SHIFT          16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_PKT_SYNC0      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_SDS0_DEMOD_SYNC 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_SDS0_BERT_SYNC 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_MTSIF_RX_SYNC  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_PM_PKT_SYNC0   4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: pkt_data0 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_MASK           0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_SHIFT          12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_PKT_DATA0      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_SDS0_DEMOD_DATA 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_SDS0_BERT_DATA 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_MTSIF_RX_DATA_0 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_PM_PKT_DATA0   4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: pkt_clk0 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_PKT_CLK0        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_SDS0_DEMOD_CLK  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_SDS0_BERT_CLK   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_MTSIF_RX_CLK    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_PM_PKT_CLK0     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_22 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_22_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_22_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_22_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_22_GPIO_22          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_22_SC1_VPP          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_22_PM_GPIO_22       2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_21 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_21_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_21_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_21_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_21_GPIO_21          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_21_SC1_IO_AUX2      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_21_PM_GPIO_21       2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_14 - Pinmux control register 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_62 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_GPIO_62          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_PKT_CLK2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_MTSIF_RX_DATA_7  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_ALT_TP_OUT_07    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_PM_GPIO_62       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_61 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_GPIO_61          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_PKT_ERROR1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_SDS0_DEMOD_ERROR 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_I2S_O_CLK        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_PM_GPIO_61       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_60 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_GPIO_60          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_PKT_VALID1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_SDS0_DEMOD_VALID 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_MTSIF_RX_DATA_6  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_PM_GPIO_60       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_59 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_GPIO_59          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_PKT_SYNC1        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_SDS0_DEMOD_SYNC  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_MTSIF_RX_DATA_5  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_PM_GPIO_59       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_58 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_GPIO_58          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_PKT_DATA1        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_SDS0_DEMOD_DATA  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_MTSIF_RX_DATA_4  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_PM_GPIO_58       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_57 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_GPIO_57          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_PKT_CLK1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_SDS0_DEMOD_CLK   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_MTSIF_RX_DATA_3  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_PM_GPIO_57       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: rmx_sync0 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_sync0_MASK           0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_sync0_SHIFT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_sync0_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_sync0_RMX_SYNC0      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_sync0_ALT_TP_OUT_17  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: rmx_data0 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_data0_MASK           0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_data0_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_data0_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_data0_RMX_DATA0      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_data0_ALT_TP_OUT_16  1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_15 - Pinmux control register 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_80 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_80_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_80_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_80_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_80_GPIO_80          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_80_MOCA_ACTIVITY_N  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_80_EXT_IRQB_20      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_80_PM_GPIO_80       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_79 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_79_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_79_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_79_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_79_GPIO_79          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_79_MOCA_LINK_N      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_79_EXT_IRQB_19      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_79_PM_GPIO_79       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_66 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_GPIO_66          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_ENET_ACTIVITY    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_MOCA_ACTIVE_N    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_ALT_TP_OUT_14    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_PM_GPIO_66       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_43 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_GPIO_43          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_ENET_LINK        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_MOCA_LINK_N      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_ALT_TP_OUT_13    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_PM_GPIO_43       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_67 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_GPIO_67          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_PKT_ERROR2       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_MTSIC_ATS_RESET  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_ALT_TP_OUT_12    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_PM_GPIO_67       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_65 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_GPIO_65          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_PKT_VALID2       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_MTSIF_ATS_INC    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_ALT_TP_OUT_11    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_PM_GPIO_65       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_64 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_GPIO_64          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_PKT_SYNC2        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_EXT_IRQB_18      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_ALT_TP_OUT_10    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_PM_GPIO_64       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_63 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_GPIO_63          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_PKT_DATA2        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_EXT_IRQB_17      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_ALT_TP_OUT_09    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_PM_GPIO_63       4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_16 - Pinmux control register 16
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: codec_sdi [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sdi_MASK           0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sdi_SHIFT          28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sdi_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sdi_CODEC_SDI      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sdi_ALT_TP_OUT_21  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sdi_PM_CODEC_SDI   2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: codec_sclk [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sclk_MASK          0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sclk_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sclk_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sclk_CODEC_SCLK    0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sclk_I2S_O_SYNC    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sclk_ALT_TP_OUT_20 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sclk_PM_CODEC_SCLK 3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: codec_mclk [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_MASK          0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_SHIFT         20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_CODEC_MCLK    0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_I2S_O_DATA    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_ALT_TP_OUT_19 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_PM_CODEC_MCLK 3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: ir_out [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_IR_OUT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_ALT_TP_OUT_18     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_PM_IR_OUT         2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_05 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_05_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_05_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_05_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_05_SGPIO_05        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_05_BSC_M3_SDA      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_04 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_SGPIO_04        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_BSC_M3_SCL      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_03 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_SGPIO_03        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_BSC_M1_SDA      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_02 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_SGPIO_02        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_BSC_M1_SCL      1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_17 - Pinmux control register 17
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: uart_txdb [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txdb_MASK           0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txdb_SHIFT          28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txdb_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txdb_UART_TXDB      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txdb_ALT_TP_OUT_29  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: uart_rxdb [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxdb_MASK           0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxdb_SHIFT          24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxdb_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxdb_UART_RXDB      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxdb_ALT_TP_IN_28   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: uart_rtsab [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rtsab_MASK          0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rtsab_SHIFT         20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rtsab_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rtsab_UART_RTSAB    0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rtsab_ALT_TP_OUT_27 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: uart_ctsab [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_ctsab_MASK          0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_ctsab_SHIFT         16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_ctsab_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_ctsab_UART_CTSAB    0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_ctsab_ALT_TP_OUT_26 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: uart_txda [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txda_MASK           0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txda_SHIFT          12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txda_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txda_UART_TXDA      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txda_ALT_TP_OUT_25  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: uart_rxda [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxda_MASK           0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxda_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxda_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxda_UART_RXDA      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxda_ALT_TP_IN_24   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: codec_fsync [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_MASK         0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_SHIFT        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_DEFAULT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_CODEC_FSYNC  0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_ALT_TP_OUT_23 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_PM_CODEC_FSYNC 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: codec_sdo [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_MASK           0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_CODEC_SDO      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_I2S_O_CLK      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_ALT_TP_OUT_22  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_PM_CODEC_SDO   3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_18 - Pinmux control register 18
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_reserved0_MASK           0xffffff00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_reserved0_SHIFT          8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: uart_rtsbb [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rtsbb_MASK          0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rtsbb_SHIFT         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rtsbb_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rtsbb_UART_RTSBB    0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rtsbb_ALT_TP_OUT_31 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: uart_ctsbb [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_ctsbb_MASK          0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_ctsbb_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_ctsbb_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_ctsbb_UART_CTSBB    0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_ctsbb_ALT_TP_OUT_30 1
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [29:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x3f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       24
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_78_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_78_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_78_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_78_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_78_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_78_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_78_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_77_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_77_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_77_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_77_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_77_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_77_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_77_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_76_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_76_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_76_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_76_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_76_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_76_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_76_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_75_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_75_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_75_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_75_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_75_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_75_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_75_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_74_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_74_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_74_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_74_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_74_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_74_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_74_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_73_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_73_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_73_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_73_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_73_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_73_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_73_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_72_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_72_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_72_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_72_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_72_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_72_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_72_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_71_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_71_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_71_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_71_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_71_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_71_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_71_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_70_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_70_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_70_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_70_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_70_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_70_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_70_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_69_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_69_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_69_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_69_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_69_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_69_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_69_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_68_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_68_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_68_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_68_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_68_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_68_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_68_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved1 [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_MASK        0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0x3fffffff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [29:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK        0x3fffffff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: reserved0 [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved0_MASK        0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_addr23_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr23_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr23_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr23_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr23_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr23_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr23_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: reserved1 [25:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved1_MASK        0x03ffffff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved1_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_84_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_84_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_84_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_84_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_84_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_84_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_84_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_83_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_83_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_83_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_83_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_83_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_83_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_83_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_82_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_82_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_82_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_82_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_82_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_82_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_82_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_81_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_81_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_81_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_81_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_81_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_81_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_81_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved0 [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_MASK        0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_SHIFT       20
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_dsb_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_tsb_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved1 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved1_MASK        0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved1_SHIFT       12
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr27_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr26_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr25_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr24_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved2 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved2_MASK        0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved2_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_14_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_14_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_14_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_14_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_14_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_13_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_13_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_13_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_13_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_13_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_12_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_12_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_12_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_12_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_12_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_11_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_11_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_11_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_11_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_11_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_10_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_10_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_10_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_10_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_10_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_09_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_09_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_09_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_09_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_09_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_08_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_08_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_08_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_08_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_08_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_07_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_07_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_07_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_07_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_07_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_06_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_06_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_06_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_06_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_06_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_05_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_05_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_05_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_05_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_05_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_04_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_04_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_04_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_04_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_04_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_03_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_03_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_03_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_03_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_03_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_02_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_02_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_02_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_02_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_02_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_02_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_01_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_00_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_34_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_34_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_34_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_34_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_34_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_34_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_34_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_31_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_31_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_31_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_31_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_31_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_31_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_31_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_30_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_30_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_30_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_30_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_30_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_30_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_30_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_29_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_29_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_29_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_29_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_29_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_29_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_29_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_28_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_28_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_28_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_28_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_28_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_28_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_28_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_27_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_27_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_27_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_27_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_27_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_27_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_27_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_26_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_26_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_26_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_26_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_26_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_26_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_26_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_25_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_25_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_25_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_25_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_25_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_25_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_25_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_24_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_24_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_24_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_24_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_24_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_24_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_24_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_23_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_23_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_23_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_23_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_23_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_23_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_23_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_19_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_19_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_19_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_19_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_19_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_19_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_18_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_18_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_18_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_18_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_18_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_18_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_18_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_17_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_17_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_17_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_17_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_17_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_17_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_16_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_15_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_48_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_48_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_48_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_48_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_48_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_48_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_48_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_47_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_47_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_47_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_47_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_47_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_47_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_47_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_46_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_46_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_46_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_46_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_46_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_46_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_46_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_45_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_45_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_45_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_45_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_45_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_45_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_45_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_44_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_44_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_44_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_44_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_44_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_44_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_44_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_42_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_42_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_42_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_42_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_42_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_42_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_42_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_41_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_41_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_41_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_41_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_41_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_41_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_41_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_33_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_33_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_33_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_33_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_33_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_33_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_33_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_32_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_32_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_32_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_32_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_32_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_32_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_32_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_40_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_40_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_40_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_40_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_40_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_40_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_40_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_39_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_39_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_39_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_39_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_39_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_39_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_39_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_38_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_38_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_38_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_38_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_38_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_38_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_38_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_37_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_37_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_37_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_37_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_37_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_37_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_37_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_36_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_36_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_36_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_36_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_36_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_36_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_36_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_35_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_35_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_35_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_35_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_35_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_35_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_35_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved0 [29:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_MASK        0x3fc00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_SHIFT       22
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_22_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_22_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_22_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_22_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_22_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_22_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_22_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_21_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_21_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_21_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_21_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_21_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_21_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_21_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_20_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_20_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_20_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_20_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_20_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_20_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_56_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_56_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_56_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_56_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_56_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_56_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_56_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_55_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_55_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_55_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_55_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_55_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_55_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_55_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_54_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_54_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_54_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_54_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_54_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_54_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_54_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_53_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_53_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_53_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_53_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_53_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_53_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_53_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_52_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_52_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_52_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_52_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_52_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_52_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_52_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_51_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_51_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_51_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_51_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_51_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_51_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_51_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_50_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_50_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_50_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_50_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_50_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_50_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_50_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_49_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_49_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_49_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_49_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_49_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_49_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_49_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_9 - Pad pull-up/pull-down control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: spare_pad_ctrl_9 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_43_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_43_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_43_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_43_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_43_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_43_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_43_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_67_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_67_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_67_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_67_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_67_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_67_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_67_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_65_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_65_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_65_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_65_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_65_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_65_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_65_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_64_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_64_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_64_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_64_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_64_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_64_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_64_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_63_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_63_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_63_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_63_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_63_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_63_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_63_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_62_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_61_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_60_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_59_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_58_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_57_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: reserved0 [07:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved0_MASK        0x000000ff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_10 - Pad pull-up/pull-down control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: spare_pad_ctrl_10 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: reserved0 [29:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_reserved0_MASK       0x3fffffc0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_reserved0_SHIFT      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_80_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_80_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_80_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_80_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_80_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_80_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_80_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_79_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_79_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_79_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_79_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_79_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_79_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_79_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_66_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_11 - Pad pull-up/pull-down control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved0_MASK       0xffff0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved0_SHIFT      16
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: spare_pad_ctrl_11 [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: reserved1 [13:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved1_MASK       0x00003fff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved1_SHIFT      0
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:21] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xffe00000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       21
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_79 [20:20] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_79_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_79_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_79_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_59 [19:19] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_59_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_59_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_59_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_58 [18:18] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_58_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_58_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_58_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_57 [17:17] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_57_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_57_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_57_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_pkt_valid0 [16:16] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pkt_valid0_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pkt_valid0_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pkt_valid0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_pkt_clk0 [15:15] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pkt_clk0_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pkt_clk0_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pkt_clk0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_cs3b [14:14] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs3b_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs3b_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs3b_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_nand_rbb [13:13] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_nand_rbb_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_nand_rbb_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_nand_rbb_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_cs5b [12:12] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs5b_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs5b_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs5b_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_cs4b [11:11] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs4b_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs4b_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs4b_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_cpu_clk [10:10] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_cpu_clk_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_cpu_clk_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_cpu_clk_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_moca_clk [09:09] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_moca_clk_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_moca_clk_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_moca_clk_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_clk_acc [08:08] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_clk_acc_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_clk_acc_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_clk_acc_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_vcxo27 [07:07] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_vcxo27_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_vcxo27_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_vcxo27_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_usb1_pwrflt [06:06] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_usb1_pwrflt_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_usb1_pwrflt_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_usb1_pwrflt_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_usb0_pwrflt [05:05] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_usb0_pwrflt_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_usb0_pwrflt_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_usb0_pwrflt_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_76 [04:04] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_76_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_76_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_76_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_72 [03:03] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_72_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_72_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_72_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_71 [02:02] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_71_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_71_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_71_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_69 [01:01] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_69_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_69_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_69_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_68 [00:00] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_68_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_68_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_68_DEFAULT 0
+
+/***************************************************************************
+ *RESET_CTRL - Reset control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0xfffffffe
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               1
+
+/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT   0
+
+/***************************************************************************
+ *RESET_SOURCE_ENABLE - Reset source enable
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK       0xfffffc00
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT      10
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0
+
+/***************************************************************************
+ *SW_MASTER_RESET - Software master reset
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK           0xfffffffe
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT          1
+
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0
+
+/***************************************************************************
+ *HW_RESET_EXTENSION - Hardware reset extension
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0
+
+/***************************************************************************
+ *RESET_MONITOR - Reset Monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT  7
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT   6
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT   4
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset history
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:17] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xfffe0000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            17
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [16:16] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 16
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [15:15] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 15
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [14:14] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 14
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [13:13] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 13
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_reset [12:12] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_MASK    0x00001000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT   12
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_reset [11:11] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT    11
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [10:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT       10
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK       0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT      9
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_dl_sw_reset [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK  0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT 8
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 7
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 6
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK   0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT  4
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0
+
+/***************************************************************************
+ *SW_INIT_0_SET - Software init 0 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: reserved0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved0_MASK             0xe0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved0_SHIFT            29
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_MASK          0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_SHIFT         28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_MASK        0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_SHIFT       27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK        0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT       26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_MASK          0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_SHIFT         25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK          0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK   0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT  23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_MASK   0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_SHIFT  22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK          0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT         21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_MASK   0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_SHIFT  20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK         0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT        19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK           0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT          18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK   0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT  17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_MASK         0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_SHIFT        16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK           0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT          15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK           0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT          14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_MASK   0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_SHIFT  13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_MASK          0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_MASK   0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_SHIFT  11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT       10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK           0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT          9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK           0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK           0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT          6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_SHIFT   4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT   0
+
+/***************************************************************************
+ *SW_INIT_0_CLEAR - Software init 0 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: reserved0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved0_MASK           0xe0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved0_SHIFT          29
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_MASK        0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_SHIFT       28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_MASK      0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_SHIFT     27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK      0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT     26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_MASK        0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_SHIFT       25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK        0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT       24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK        0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT       21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK       0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT      19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK         0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT        18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_MASK       0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK         0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT        15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK         0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT        14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_MASK        0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_SHIFT       12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK      0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT     10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK         0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT        9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK         0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK         0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT        6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT  0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *SW_INIT_0_STATUS - Software init 0 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: reserved0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved0_MASK          0xe0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved0_SHIFT         29
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_MASK       0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_SHIFT      28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_DEFAULT    1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_MASK       0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_SHIFT      25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK       0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK       0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT      21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK      0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT     19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK        0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT       18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_MASK      0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_DEFAULT   1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK        0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT       15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK        0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT       14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_MASK       0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_DEFAULT    1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK        0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT   2
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT       1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: reserved0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved0_MASK     0xe0000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved0_SHIFT    29
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_MASK  0x10000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_MASK  0x02000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK  0x01000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK  0x00200000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK   0x00040000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT  18
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK   0x00008000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT  15
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK   0x00004000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT  14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_svd0_sw_init_MASK  0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK   0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT  9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK   0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT  8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT  6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: reserved0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved0_MASK 0xe0000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved0_SHIFT 29
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: reserved0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved0_MASK   0xe0000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved0_SHIFT  29
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_1_SET - Software init 1 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK             0xffffff80
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT            7
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK        0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT       5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_MASK        0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_SHIFT       4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_SHIFT   2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_uhfr_sw_init_MASK          0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_uhfr_sw_init_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_uhfr_sw_init_DEFAULT       0
+
+/***************************************************************************
+ *SW_INIT_1_CLEAR - Software init 1 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT          7
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_uhfr_sw_init_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_uhfr_sw_init_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_uhfr_sw_init_DEFAULT     0
+
+/***************************************************************************
+ *SW_INIT_1_STATUS - Software init 1 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT         7
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK     0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT    6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK     0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT    5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT  0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_MASK   0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_SHIFT  3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_SHIFT       1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_uhfr_sw_init_MASK       0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_uhfr_sw_init_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_uhfr_sw_init_DEFAULT    1
+
+/***************************************************************************
+ *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK     0xffffff80
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT    7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_uhfr_sw_init_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_uhfr_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xffffff80
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_uhfr_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK   0xffffff80
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT  7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_uhfr_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK  0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: reserved0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved0_MASK 0xe0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved0_SHIFT 29
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 1
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xffffff80
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 7
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_uhfr_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_uhfr_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: reserved0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved0_MASK 0xe0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved0_SHIFT 29
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 1
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xffffff80
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 7
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_uhfr_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_uhfr_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0
+
+/***************************************************************************
+ *SPARE_CTRL - Spare control bits reserved for future use
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT         0
+
+/***************************************************************************
+ *TEST_PORT_CTRL - Test port control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SOFT_MODEM_TP 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT         0
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 127
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0  0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET1  1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU     2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R  4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_A  5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T  6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS     16
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK     17
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON     18
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     20
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     21
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE    22
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM    23
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC     25
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DVP_HT  26
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SVD0    27
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GFX     29
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO     30
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA   31
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     33
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0   35
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0    45
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB1    46
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MOCA    47
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_UHFR    50
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_FTM     51
+
+/***************************************************************************
+ *TEST_PORT_OUT_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_OUT_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0
+
+/***************************************************************************
+ *EJTAG_INPUT_EN - EJTAG input bus enables
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xfffffff0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           4
+
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [03:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x0000000f
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA_CPU_ONE_HOT 4
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 8
+
+/***************************************************************************
+ *EJTAG_OUTPUT_SEL - EJTAG output select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         3
+
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA_CPU 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 3
+
+/***************************************************************************
+ *UART_ROUTER_SEL - UART Router select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK      0xf0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT     28
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK      0x0f000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT     24
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK      0x00f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK      0x000f0000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK      0x0000f000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK      0x00000f00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK      0x0000000f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15
+
+/***************************************************************************
+ *VTRAP_CTRL - VTRAP Control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK                0xfffff000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT               12
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_threshold [11:11] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_threshold [10:10] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_threshold [09:09] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_DEFAULT 1
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [08:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x000001f8
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 24
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_status_clear [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_status_clear [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_status_clear [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_DEFAULT 0
+
+/***************************************************************************
+ *VTRAP_STATUS - VTRAP Status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK              0xfffffff8
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT             3
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_status [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_status [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_status [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_DEFAULT 0
+
+/***************************************************************************
+ *SSP_CONFIG - Serial Slave Port configuration register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT        4
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT           0
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT     1
+
+/***************************************************************************
+ *SERS_REV - SERS Revision Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16
+
+/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT     0
+
+/***************************************************************************
+ *SERS_CFG - SERS Configuration Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT                1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT           0
+
+/* union - case mapped_buffer_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0
+
+/* union - case cmd_fifo_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 31
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 16
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT  0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT                 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT            0
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x00404428
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0
+
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x00404448
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0
+
+
+/***************************************************************************
+ *RO_TEST_BLOCK_SEL - Block select for RO testmode
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xffffffe0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        5
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_pwenb [04:04] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DEFAULT  1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_ENABLED  0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DISABLED 1
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [03:02] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MIN_LOAD 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MED_LOAD 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MAX_LOAD 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SVT_MIN_LOAD 3
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
+
+/***************************************************************************
+ *TEST_CONFIGURATION - Test configuration
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0
+
+#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_timer.h b/include/linux/brcmstb/7344b0/bchp_timer.h
new file mode 100644
index 0000000..41dbc16
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_timer.h
@@ -0,0 +1,340 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:31:37 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_timer.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 2:26p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_TIMER_H__
+#define BCHP_TIMER_H__
+
+/***************************************************************************
+ *TIMER - Watchdog & Programmable Timers
+ ***************************************************************************/
+#define BCHP_TIMER_TIMER_IS                      0x004067c0 /* TIMER INTERRUPT STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE0                     0x004067c4 /* TIMER CPU INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_TIMER0_CTRL                   0x004067c8 /* TIMER0 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER1_CTRL                   0x004067cc /* TIMER1 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER2_CTRL                   0x004067d0 /* TIMER2 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER3_CTRL                   0x004067d4 /* TIMER3 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER0_STAT                   0x004067d8 /* TIMER0 STATUS REGISTER */
+#define BCHP_TIMER_TIMER1_STAT                   0x004067dc /* TIMER1 STATUS REGISTER */
+#define BCHP_TIMER_TIMER2_STAT                   0x004067e0 /* TIMER2 STATUS REGISTER */
+#define BCHP_TIMER_TIMER3_STAT                   0x004067e4 /* TIMER3 STATUS REGISTER */
+#define BCHP_TIMER_WDTIMEOUT                     0x004067e8 /* WATCHDOG TIMEOUT REGISTER */
+#define BCHP_TIMER_WDCMD                         0x004067ec /* WATCHDOG COMMAND REGISTER */
+#define BCHP_TIMER_WDCHIPRST_CNT                 0x004067f0 /* WATCHDOG CHIP RESET COUNT REGISTER */
+#define BCHP_TIMER_WDCRS                         0x004067f4 /* WATCHDOG CHIP RESET STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE1                     0x004067f8 /* TIMER PCI INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_WDCTRL                        0x004067fc /* WATCHDOG CONTROL REGISTER */
+
+/***************************************************************************
+ *TIMER_IS - TIMER INTERRUPT STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IS :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IS_reserved0_MASK                         0xffffffe0
+#define BCHP_TIMER_TIMER_IS_reserved0_SHIFT                        5
+
+/* TIMER :: TIMER_IS :: WDINT [04:04] */
+#define BCHP_TIMER_TIMER_IS_WDINT_MASK                             0x00000010
+#define BCHP_TIMER_TIMER_IS_WDINT_SHIFT                            4
+#define BCHP_TIMER_TIMER_IS_WDINT_DEFAULT                          0
+
+/* TIMER :: TIMER_IS :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IS_TMR3TO_MASK                            0x00000008
+#define BCHP_TIMER_TIMER_IS_TMR3TO_SHIFT                           3
+#define BCHP_TIMER_TIMER_IS_TMR3TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IS_TMR2TO_MASK                            0x00000004
+#define BCHP_TIMER_TIMER_IS_TMR2TO_SHIFT                           2
+#define BCHP_TIMER_TIMER_IS_TMR2TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IS_TMR1TO_MASK                            0x00000002
+#define BCHP_TIMER_TIMER_IS_TMR1TO_SHIFT                           1
+#define BCHP_TIMER_TIMER_IS_TMR1TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IS_TMR0TO_MASK                            0x00000001
+#define BCHP_TIMER_TIMER_IS_TMR0TO_SHIFT                           0
+#define BCHP_TIMER_TIMER_IS_TMR0TO_DEFAULT                         0
+
+/***************************************************************************
+ *TIMER_IE0 - TIMER CPU INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE0 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE0_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE0_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE0 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_DEFAULT                     0
+
+/* TIMER :: TIMER_IE0 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_DEFAULT                        0
+
+/***************************************************************************
+ *TIMER0_CTRL - TIMER0 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER0_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER0_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER0_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER0_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER0_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER0_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER0_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER0_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER1_CTRL - TIMER1 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER1_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER1_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER1_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER1_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER1_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER1_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER1_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER1_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER2_CTRL - TIMER2 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER2_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER2_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER2_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER2_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER2_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER2_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER2_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER2_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER3_CTRL - TIMER3 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER3_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER3_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER3_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER3_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER3_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER3_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER3_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER3_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER0_STAT - TIMER0 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER0_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER0_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER0_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER1_STAT - TIMER1 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER1_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER1_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER1_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER2_STAT - TIMER2 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER2_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER2_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER2_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER3_STAT - TIMER3 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER3_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER3_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER3_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *WDTIMEOUT - WATCHDOG TIMEOUT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDTIMEOUT :: WDTIMEOUT_VAL [31:00] */
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_MASK                    0xffffffff
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *WDCMD - WATCHDOG COMMAND REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCMD :: WDCMD [31:00] */
+#define BCHP_TIMER_WDCMD_WDCMD_MASK                                0xffffffff
+#define BCHP_TIMER_WDCMD_WDCMD_SHIFT                               0
+#define BCHP_TIMER_WDCMD_WDCMD_DEFAULT                             0
+
+/***************************************************************************
+ *WDCHIPRST_CNT - WATCHDOG CHIP RESET COUNT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCHIPRST_CNT :: reserved0 [31:26] */
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_MASK                    0xfc000000
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_SHIFT                   26
+
+/* TIMER :: WDCHIPRST_CNT :: WDCHIPRST_CNT [25:00] */
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_MASK                0x03ffffff
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_SHIFT               0
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_DEFAULT             50331647
+
+/***************************************************************************
+ *WDCRS - WATCHDOG CHIP RESET STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCRS :: reserved0 [31:01] */
+#define BCHP_TIMER_WDCRS_reserved0_MASK                            0xfffffffe
+#define BCHP_TIMER_WDCRS_reserved0_SHIFT                           1
+
+/* TIMER :: WDCRS :: WDCR [00:00] */
+#define BCHP_TIMER_WDCRS_WDCR_MASK                                 0x00000001
+#define BCHP_TIMER_WDCRS_WDCR_SHIFT                                0
+#define BCHP_TIMER_WDCRS_WDCR_DEFAULT                              0
+
+/***************************************************************************
+ *TIMER_IE1 - TIMER PCI INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE1 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE1_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE1_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE1 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_DEFAULT                     0
+
+/* TIMER :: TIMER_IE1 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_DEFAULT                        0
+
+/***************************************************************************
+ *WDCTRL - WATCHDOG CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCTRL :: reserved0 [31:03] */
+#define BCHP_TIMER_WDCTRL_reserved0_MASK                           0xfffffff8
+#define BCHP_TIMER_WDCTRL_reserved0_SHIFT                          3
+
+/* TIMER :: WDCTRL :: WD_COUNT_MODE [02:02] */
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_MASK                       0x00000004
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_SHIFT                      2
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_DEFAULT                    0
+
+/* TIMER :: WDCTRL :: WD_EVENT_MODE [01:00] */
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_MASK                       0x00000003
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_SHIFT                      0
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_DEFAULT                    0
+
+#endif /* #ifndef BCHP_TIMER_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_uarta.h b/include/linux/brcmstb/7344b0/bchp_uarta.h
new file mode 100644
index 0000000..febb3bf
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_uarta.h
@@ -0,0 +1,394 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:45:48 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_uarta.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 2:28p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTA_H__
+#define BCHP_UARTA_H__
+
+/***************************************************************************
+ *UARTA - UART A
+ ***************************************************************************/
+#define BCHP_UARTA_RBR                           0x00406900 /* Receive Buffer Register */
+#define BCHP_UARTA_THR                           0x00406900 /* Transmit Holding Register */
+#define BCHP_UARTA_DLH                           0x00406904 /* Divisor Latch High */
+#define BCHP_UARTA_DLL                           0x00406900 /* Divisor Latch Low */
+#define BCHP_UARTA_IER                           0x00406904 /* Interrupt Enable Register */
+#define BCHP_UARTA_IIR                           0x00406908 /* Interrupt Identity Register */
+#define BCHP_UARTA_FCR                           0x00406908 /* FIFO Control Register */
+#define BCHP_UARTA_LCR                           0x0040690c /* Line Control Register */
+#define BCHP_UARTA_MCR                           0x00406910 /* Modem Control Register */
+#define BCHP_UARTA_LSR                           0x00406914 /* Line Status Register */
+#define BCHP_UARTA_MSR                           0x00406918 /* Modem Status Register */
+#define BCHP_UARTA_SCR                           0x0040691c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTA :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTA_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_RBR_reserved0_SHIFT                             8
+
+/* UARTA :: RBR :: RBR [07:00] */
+#define BCHP_UARTA_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTA_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTA_RBR_RBR_DEFAULT                                 0
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTA :: THR :: reserved0 [31:08] */
+#define BCHP_UARTA_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_THR_reserved0_SHIFT                             8
+
+/* UARTA :: THR :: THR [07:00] */
+#define BCHP_UARTA_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTA_THR_THR_SHIFT                                   0
+#define BCHP_UARTA_THR_THR_DEFAULT                                 0
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTA :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTA_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLH_reserved0_SHIFT                             8
+
+/* UARTA :: DLH :: DLH [07:00] */
+#define BCHP_UARTA_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTA_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTA_DLH_DLH_DEFAULT                                 0
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTA :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTA_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLL_reserved0_SHIFT                             8
+
+/* UARTA :: DLL :: DLL [07:00] */
+#define BCHP_UARTA_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTA_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTA_DLL_DLL_DEFAULT                                 0
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTA :: IER :: reserved0 [31:08] */
+#define BCHP_UARTA_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IER_reserved0_SHIFT                             8
+
+/* UARTA :: IER :: PTIME [07:07] */
+#define BCHP_UARTA_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTA_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTA_IER_PTIME_DEFAULT                               0
+
+/* UARTA :: IER :: reserved1 [06:04] */
+#define BCHP_UARTA_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTA_IER_reserved1_SHIFT                             4
+
+/* UARTA :: IER :: EDSSI [03:03] */
+#define BCHP_UARTA_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTA_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTA_IER_EDSSI_DEFAULT                               0
+
+/* UARTA :: IER :: ELSI [02:02] */
+#define BCHP_UARTA_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTA_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTA_IER_ELSI_DEFAULT                                0
+
+/* UARTA :: IER :: ETBEI [01:01] */
+#define BCHP_UARTA_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTA_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTA_IER_ETBEI_DEFAULT                               0
+
+/* UARTA :: IER :: ERBFI [00:00] */
+#define BCHP_UARTA_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTA_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTA_IER_ERBFI_DEFAULT                               0
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTA :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTA_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IIR_reserved0_SHIFT                             8
+
+/* UARTA :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTA_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTA_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTA_IIR_FIFOSE_DEFAULT                              0
+
+/* UARTA :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTA_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTA_IIR_reserved1_SHIFT                             4
+
+/* UARTA :: IIR :: IID [03:00] */
+#define BCHP_UARTA_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTA_IIR_IID_SHIFT                                   0
+#define BCHP_UARTA_IIR_IID_DEFAULT                                 1
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTA :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTA_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_FCR_reserved0_SHIFT                             8
+
+/* UARTA :: FCR :: RT [07:06] */
+#define BCHP_UARTA_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTA_FCR_RT_SHIFT                                    6
+#define BCHP_UARTA_FCR_RT_DEFAULT                                  0
+
+/* UARTA :: FCR :: TET [05:04] */
+#define BCHP_UARTA_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTA_FCR_TET_SHIFT                                   4
+#define BCHP_UARTA_FCR_TET_DEFAULT                                 0
+
+/* UARTA :: FCR :: DMAM [03:03] */
+#define BCHP_UARTA_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTA_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTA_FCR_DMAM_DEFAULT                                0
+
+/* UARTA :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTA_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTA_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTA_FCR_XFIFOR_DEFAULT                              0
+
+/* UARTA :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTA_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTA_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTA_FCR_RFIFOR_DEFAULT                              0
+
+/* UARTA :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTA_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTA_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTA_FCR_FIFOE_DEFAULT                               0
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTA :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTA_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LCR_reserved0_SHIFT                             8
+
+/* UARTA :: LCR :: DLAB [07:07] */
+#define BCHP_UARTA_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTA_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTA_LCR_DLAB_DEFAULT                                0
+
+/* UARTA :: LCR :: BC [06:06] */
+#define BCHP_UARTA_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTA_LCR_BC_SHIFT                                    6
+#define BCHP_UARTA_LCR_BC_DEFAULT                                  0
+
+/* UARTA :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTA_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTA_LCR_reserved1_SHIFT                             5
+
+/* UARTA :: LCR :: EPS [04:04] */
+#define BCHP_UARTA_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTA_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTA_LCR_EPS_DEFAULT                                 0
+
+/* UARTA :: LCR :: PEN [03:03] */
+#define BCHP_UARTA_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTA_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTA_LCR_PEN_DEFAULT                                 0
+
+/* UARTA :: LCR :: STOP [02:02] */
+#define BCHP_UARTA_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTA_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTA_LCR_STOP_DEFAULT                                0
+
+/* UARTA :: LCR :: DLS [01:00] */
+#define BCHP_UARTA_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTA_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTA_LCR_DLS_DEFAULT                                 0
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTA :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTA_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTA_MCR_reserved0_SHIFT                             7
+
+/* UARTA :: MCR :: SIRE [06:06] */
+#define BCHP_UARTA_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTA_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTA_MCR_SIRE_DEFAULT                                0
+
+/* UARTA :: MCR :: AFCE [05:05] */
+#define BCHP_UARTA_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTA_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTA_MCR_AFCE_DEFAULT                                0
+
+/* UARTA :: MCR :: LB [04:04] */
+#define BCHP_UARTA_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTA_MCR_LB_SHIFT                                    4
+#define BCHP_UARTA_MCR_LB_DEFAULT                                  0
+
+/* UARTA :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTA_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTA_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTA_MCR_OUT2_DEFAULT                                0
+
+/* UARTA :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTA_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTA_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTA_MCR_OUT1_DEFAULT                                0
+
+/* UARTA :: MCR :: RTS [01:01] */
+#define BCHP_UARTA_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTA_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTA_MCR_RTS_DEFAULT                                 0
+
+/* UARTA :: MCR :: DTR [00:00] */
+#define BCHP_UARTA_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTA_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTA_MCR_DTR_DEFAULT                                 0
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTA :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTA_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LSR_reserved0_SHIFT                             8
+
+/* UARTA :: LSR :: RFE [07:07] */
+#define BCHP_UARTA_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTA_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTA_LSR_RFE_DEFAULT                                 0
+
+/* UARTA :: LSR :: TEMT [06:06] */
+#define BCHP_UARTA_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTA_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTA_LSR_TEMT_DEFAULT                                1
+
+/* UARTA :: LSR :: THRE [05:05] */
+#define BCHP_UARTA_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTA_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTA_LSR_THRE_DEFAULT                                1
+
+/* UARTA :: LSR :: BI [04:04] */
+#define BCHP_UARTA_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTA_LSR_BI_SHIFT                                    4
+#define BCHP_UARTA_LSR_BI_DEFAULT                                  0
+
+/* UARTA :: LSR :: FE [03:03] */
+#define BCHP_UARTA_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTA_LSR_FE_SHIFT                                    3
+#define BCHP_UARTA_LSR_FE_DEFAULT                                  0
+
+/* UARTA :: LSR :: PE [02:02] */
+#define BCHP_UARTA_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTA_LSR_PE_SHIFT                                    2
+#define BCHP_UARTA_LSR_PE_DEFAULT                                  0
+
+/* UARTA :: LSR :: OE [01:01] */
+#define BCHP_UARTA_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTA_LSR_OE_SHIFT                                    1
+#define BCHP_UARTA_LSR_OE_DEFAULT                                  0
+
+/* UARTA :: LSR :: DR [00:00] */
+#define BCHP_UARTA_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTA_LSR_DR_SHIFT                                    0
+#define BCHP_UARTA_LSR_DR_DEFAULT                                  0
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTA :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTA_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_MSR_reserved0_SHIFT                             8
+
+/* UARTA :: MSR :: DCD [07:07] */
+#define BCHP_UARTA_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTA_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTA_MSR_DCD_DEFAULT                                 0
+
+/* UARTA :: MSR :: RI [06:06] */
+#define BCHP_UARTA_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTA_MSR_RI_SHIFT                                    6
+#define BCHP_UARTA_MSR_RI_DEFAULT                                  0
+
+/* UARTA :: MSR :: DSR [05:05] */
+#define BCHP_UARTA_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTA_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTA_MSR_DSR_DEFAULT                                 0
+
+/* UARTA :: MSR :: CTS [04:04] */
+#define BCHP_UARTA_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTA_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTA_MSR_CTS_DEFAULT                                 0
+
+/* UARTA :: MSR :: DDCD [03:03] */
+#define BCHP_UARTA_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTA_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTA_MSR_DDCD_DEFAULT                                0
+
+/* UARTA :: MSR :: TERI [02:02] */
+#define BCHP_UARTA_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTA_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTA_MSR_TERI_DEFAULT                                0
+
+/* UARTA :: MSR :: DDSR [01:01] */
+#define BCHP_UARTA_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTA_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTA_MSR_DDSR_DEFAULT                                0
+
+/* UARTA :: MSR :: DCTS [00:00] */
+#define BCHP_UARTA_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTA_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTA_MSR_DCTS_DEFAULT                                0
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTA :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTA_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_SCR_reserved0_SHIFT                             8
+
+/* UARTA :: SCR :: SCR [07:00] */
+#define BCHP_UARTA_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTA_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTA_SCR_SCR_DEFAULT                                 0
+
+#endif /* #ifndef BCHP_UARTA_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_uartb.h b/include/linux/brcmstb/7344b0/bchp_uartb.h
new file mode 100644
index 0000000..6e98458
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_uartb.h
@@ -0,0 +1,60 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri May 21 13:10:53 2010
+ *                 MD5 Checksum         34dd0d3bbf3478606c423cca67439a45
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTB_H__
+#define BCHP_UARTB_H__
+
+/***************************************************************************
+ *UARTB - UART B
+ ***************************************************************************/
+#define BCHP_UARTB_RBR                           0x00406940 /* Receive Buffer Register */
+#define BCHP_UARTB_THR                           0x00406940 /* Transmit Holding Register */
+#define BCHP_UARTB_DLH                           0x00406944 /* Divisor Latch High */
+#define BCHP_UARTB_DLL                           0x00406940 /* Divisor Latch Low */
+#define BCHP_UARTB_IER                           0x00406944 /* Interrupt Enable Register */
+#define BCHP_UARTB_IIR                           0x00406948 /* Interrupt Identity Register */
+#define BCHP_UARTB_FCR                           0x00406948 /* FIFO Control Register */
+#define BCHP_UARTB_LCR                           0x0040694c /* Line Control Register */
+#define BCHP_UARTB_MCR                           0x00406950 /* Modem Control Register */
+#define BCHP_UARTB_LSR                           0x00406954 /* Line Status Register */
+#define BCHP_UARTB_MSR                           0x00406958 /* Modem Status Register */
+#define BCHP_UARTB_SCR                           0x0040695c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTB_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_uartc.h b/include/linux/brcmstb/7344b0/bchp_uartc.h
new file mode 100644
index 0000000..ee6b0a5
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_uartc.h
@@ -0,0 +1,60 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri May 21 13:01:00 2010
+ *                 MD5 Checksum         34dd0d3bbf3478606c423cca67439a45
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTC_H__
+#define BCHP_UARTC_H__
+
+/***************************************************************************
+ *UARTC - UART C
+ ***************************************************************************/
+#define BCHP_UARTC_RBR                           0x00406980 /* Receive Buffer Register */
+#define BCHP_UARTC_THR                           0x00406980 /* Transmit Holding Register */
+#define BCHP_UARTC_DLH                           0x00406984 /* Divisor Latch High */
+#define BCHP_UARTC_DLL                           0x00406980 /* Divisor Latch Low */
+#define BCHP_UARTC_IER                           0x00406984 /* Interrupt Enable Register */
+#define BCHP_UARTC_IIR                           0x00406988 /* Interrupt Identity Register */
+#define BCHP_UARTC_FCR                           0x00406988 /* FIFO Control Register */
+#define BCHP_UARTC_LCR                           0x0040698c /* Line Control Register */
+#define BCHP_UARTC_MCR                           0x00406990 /* Modem Control Register */
+#define BCHP_UARTC_LSR                           0x00406994 /* Line Status Register */
+#define BCHP_UARTC_MSR                           0x00406998 /* Modem Status Register */
+#define BCHP_UARTC_SCR                           0x0040699c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_usb1_ctrl.h b/include/linux/brcmstb/7344b0/bchp_usb1_ctrl.h
new file mode 100644
index 0000000..9fe8a3d
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_usb1_ctrl.h
@@ -0,0 +1,66 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:30:48 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_usb1_ctrl.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 2:30p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB1_CTRL_H__
+#define BCHP_USB1_CTRL_H__
+
+/***************************************************************************
+ *USB1_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB1_CTRL_SETUP                     0x00490200 /* Setup Register */
+#define BCHP_USB1_CTRL_PLL_CTL                   0x00490204 /* PLL Control Register */
+#define BCHP_USB1_CTRL_FLADJ_VALUE               0x00490208 /* Frame Adjust Value */
+#define BCHP_USB1_CTRL_EBRIDGE                   0x0049020c /* Control Register for EHCI Bridge */
+#define BCHP_USB1_CTRL_OBRIDGE                   0x00490210 /* Control Register for OHCI Bridge */
+#define BCHP_USB1_CTRL_MDIO                      0x00490214 /* MDIO Interface Programming Register */
+#define BCHP_USB1_CTRL_MDIO2                     0x00490218 /* MDIO Interface Read Register */
+#define BCHP_USB1_CTRL_TEST_PORT_CTL             0x0049021c /* Test Port Control Register */
+#define BCHP_USB1_CTRL_USB_SIMCTL                0x00490220 /* Simulation Register */
+#define BCHP_USB1_CTRL_USB_TESTCTL               0x00490224 /* Throutput Test Control */
+#define BCHP_USB1_CTRL_USB_TESTMON               0x00490228 /* Throughput Test Monitor */
+#define BCHP_USB1_CTRL_UTMI_CTL_1                0x0049022c /* UTMI Control Register */
+#define BCHP_USB1_CTRL_UTMI_CTL_2                0x00490230 /* UTMI Control 2 Register */
+#define BCHP_USB1_CTRL_SPARE1                    0x00490234 /* Spare1 Register for future use */
+#define BCHP_USB1_CTRL_SPARE2                    0x00490238 /* Spare2 Register for future use */
+
+#endif /* #ifndef BCHP_USB1_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_usb_ctrl.h b/include/linux/brcmstb/7344b0/bchp_usb_ctrl.h
new file mode 100644
index 0000000..9aacc97
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_usb_ctrl.h
@@ -0,0 +1,685 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:37:40 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_usb_ctrl.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 2:32p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB_CTRL_H__
+#define BCHP_USB_CTRL_H__
+
+/***************************************************************************
+ *USB_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB_CTRL_SETUP                      0x00480200 /* Setup Register */
+#define BCHP_USB_CTRL_PLL_CTL                    0x00480204 /* PLL Control Register */
+#define BCHP_USB_CTRL_FLADJ_VALUE                0x00480208 /* Frame Adjust Value */
+#define BCHP_USB_CTRL_EBRIDGE                    0x0048020c /* Control Register for EHCI Bridge */
+#define BCHP_USB_CTRL_OBRIDGE                    0x00480210 /* Control Register for OHCI Bridge */
+#define BCHP_USB_CTRL_MDIO                       0x00480214 /* MDIO Interface Programming Register */
+#define BCHP_USB_CTRL_MDIO2                      0x00480218 /* MDIO Interface Read Register */
+#define BCHP_USB_CTRL_TEST_PORT_CTL              0x0048021c /* Test Port Control Register */
+#define BCHP_USB_CTRL_USB_SIMCTL                 0x00480220 /* Simulation Register */
+#define BCHP_USB_CTRL_USB_TESTCTL                0x00480224 /* Throutput Test Control */
+#define BCHP_USB_CTRL_USB_TESTMON                0x00480228 /* Throughput Test Monitor */
+#define BCHP_USB_CTRL_UTMI_CTL_1                 0x0048022c /* UTMI Control Register */
+#define BCHP_USB_CTRL_UTMI_CTL_2                 0x00480230 /* UTMI Control 2 Register */
+#define BCHP_USB_CTRL_SPARE1                     0x00480234 /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE2                     0x00480238 /* Spare2 Register for future use */
+
+/***************************************************************************
+ *SETUP - Setup Register
+ ***************************************************************************/
+/* USB_CTRL :: SETUP :: OC_DISABLE [31:28] */
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK                        0xf0000000
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT                       28
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT                     0
+
+/* USB_CTRL :: SETUP :: SRAM_CS_DIS [27:25] */
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_MASK                       0x0e000000
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_SHIFT                      25
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: SETUP_SPARE [24:15] */
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK                       0x01ff8000
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT                      15
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: scb_client_swap [14:14] */
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_MASK                   0x00004000
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_SHIFT                  14
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_DEFAULT                0
+
+/* USB_CTRL :: SETUP :: scb1_en [13:13] */
+#define BCHP_USB_CTRL_SETUP_scb1_en_MASK                           0x00002000
+#define BCHP_USB_CTRL_SETUP_scb1_en_SHIFT                          13
+#define BCHP_USB_CTRL_SETUP_scb1_en_DEFAULT                        0
+
+/* USB_CTRL :: SETUP :: async_expire_dis [12:12] */
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK                  0x00001000
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT                 12
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT               0
+
+/* USB_CTRL :: SETUP :: discon_intr_en [11:11] */
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_MASK                    0x00000800
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_SHIFT                   11
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_DEFAULT                 0
+
+/* USB_CTRL :: SETUP :: con_intr_en [10:10] */
+#define BCHP_USB_CTRL_SETUP_con_intr_en_MASK                       0x00000400
+#define BCHP_USB_CTRL_SETUP_con_intr_en_SHIFT                      10
+#define BCHP_USB_CTRL_SETUP_con_intr_en_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: soft_shutdown [09:09] */
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_MASK                     0x00000200
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_SHIFT                    9
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_DEFAULT                  0
+
+/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK                    0x00000100
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT                   8
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT                 0
+
+/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK                       0x00000080
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT                      7
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: soft_reset [06:06] */
+#define BCHP_USB_CTRL_SETUP_soft_reset_MASK                        0x00000040
+#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT                       6
+#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT                     0
+
+/* USB_CTRL :: SETUP :: IPP [05:05] */
+#define BCHP_USB_CTRL_SETUP_IPP_MASK                               0x00000020
+#define BCHP_USB_CTRL_SETUP_IPP_SHIFT                              5
+#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT                            0
+
+/* USB_CTRL :: SETUP :: IOC [04:04] */
+#define BCHP_USB_CTRL_SETUP_IOC_MASK                               0x00000010
+#define BCHP_USB_CTRL_SETUP_IOC_SHIFT                              4
+#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT                            0
+
+/* USB_CTRL :: SETUP :: WABO [03:03] */
+#define BCHP_USB_CTRL_SETUP_WABO_MASK                              0x00000008
+#define BCHP_USB_CTRL_SETUP_WABO_SHIFT                             3
+#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: FNBO [02:02] */
+#define BCHP_USB_CTRL_SETUP_FNBO_MASK                              0x00000004
+#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT                             2
+#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: FNHW [01:01] */
+#define BCHP_USB_CTRL_SETUP_FNHW_MASK                              0x00000002
+#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT                             1
+#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: BABO [00:00] */
+#define BCHP_USB_CTRL_SETUP_BABO_MASK                              0x00000001
+#define BCHP_USB_CTRL_SETUP_BABO_SHIFT                             0
+#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT                           0
+
+/***************************************************************************
+ *PLL_CTL - PLL Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK                  0x80000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT                 31
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT               0
+
+/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK                      0x40000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT                     30
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                   1
+
+/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK                      0x20000000
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                     29
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                   0
+
+/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                     0x10000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                    28
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                  1
+
+/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                  0x08000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                 27
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT               0
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK                          0x07000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT                         24
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT                       3
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                   0x00800000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                  23
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK                          0x00700000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT                         20
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT                       3
+
+/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK                          0x000f0000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT                         16
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT                       10
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE2 [15:15] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_MASK                   0x00008000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_SHIFT                  15
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_pdiv [14:12] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK                        0x00007000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT                       12
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                     1
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                   0x00000c00
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                  10
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK                        0x000003ff
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT                       0
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                     40
+
+/***************************************************************************
+ *FLADJ_VALUE - Frame Adjust Value
+ ***************************************************************************/
+/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                   0xffffffff
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                  0
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT                786464
+
+/***************************************************************************
+ *EBRIDGE - Control Register for EHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT               0
+
+/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT                  0
+
+/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT           0
+
+/* USB_CTRL :: EBRIDGE :: ebr_size_sel [28:28] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_DEFAULT                 0
+
+/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT                2
+
+/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                 4
+
+/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT                     0
+
+/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                   0
+
+/***************************************************************************
+ *OBRIDGE - Control Register for OHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT               0
+
+/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT                  0
+
+/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT           0
+
+/* USB_CTRL :: OBRIDGE :: obr_size_sel [28:28] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_DEFAULT                 0
+
+/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT                2
+
+/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                 4
+
+/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT                     0
+
+/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                   0
+
+/***************************************************************************
+ *MDIO - MDIO Interface Programming Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO :: MDIO_CLK_SEL [31:31] */
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_MASK                       0x80000000
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_SHIFT                      31
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_DEFAULT                    0
+
+/* USB_CTRL :: MDIO :: MDIO_XVER_SELECT [30:29] */
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_MASK                   0x60000000
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_SHIFT                  29
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_DEFAULT                0
+
+/* USB_CTRL :: MDIO :: MDIO_TERM_SELECT [28:28] */
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_MASK                   0x10000000
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_SHIFT                  28
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_DEFAULT                0
+
+/* USB_CTRL :: MDIO :: MDIO_FS_XVER_OWN [27:27] */
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_MASK                   0x08000000
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_SHIFT                  27
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_DEFAULT                0
+
+/* USB_CTRL :: MDIO :: MDIO_TESTMODE [26:26] */
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_MASK                      0x04000000
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_SHIFT                     26
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_DEFAULT                   0
+
+/* USB_CTRL :: MDIO :: WR_START [25:25] */
+#define BCHP_USB_CTRL_MDIO_WR_START_MASK                           0x02000000
+#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT                          25
+#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT                        0
+
+/* USB_CTRL :: MDIO :: RD_START [24:24] */
+#define BCHP_USB_CTRL_MDIO_RD_START_MASK                           0x01000000
+#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT                          24
+#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT                        0
+
+/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK                          0x00ff0000
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT                         16
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT                       0
+
+/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK                          0x0000ffff
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT                         0
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT                       0
+
+/***************************************************************************
+ *MDIO2 - MDIO Interface Read Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO2 :: SYNOPSIS_CORE_ID [31:16] */
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_MASK                  0xffff0000
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_SHIFT                 16
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_DEFAULT               9994
+
+/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK                      0x0000ffff
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                     0
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                   0
+
+/***************************************************************************
+ *TEST_PORT_CTL - Test Port Control Register
+ ***************************************************************************/
+/* USB_CTRL :: TEST_PORT_CTL :: TP_EN [31:31] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_MASK                     0x80000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_SHIFT                    31
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_DEFAULT                  0
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [30:27] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK               0x78000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT              27
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT            0
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb1_wr_data_sel [26:26] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_MASK          0x04000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_SHIFT         26
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_DEFAULT       0
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb0_wr_data_sel [25:25] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_MASK          0x02000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_SHIFT         25
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_DEFAULT       0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [24:24] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK                0x01000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT               24
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT             0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt2_oe [23:23] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_MASK                0x00800000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_SHIFT               23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_DEFAULT             0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron1_tstsel [22:22] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_MASK             0x00400000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_SHIFT            22
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron2_tstsel [21:21] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_MASK             0x00200000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_SHIFT            21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: test_clksel [20:19] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_MASK               0x00180000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_SHIFT              19
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_DEFAULT            0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_tstsel [18:16] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_MASK             0x00070000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_SHIFT            16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: UTMI_TEST_SEL [15:08] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_MASK             0x0000ff00
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_SHIFT            8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                 0x000000ff
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT                0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT              0
+
+/***************************************************************************
+ *USB_SIMCTL - Simulation Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK                  0x80000000
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                 31
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT               0
+
+/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK                0x40000000
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT               30
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT             0
+
+/* USB_CTRL :: USB_SIMCTL :: otg_scale_down_en [29:28] */
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_MASK            0x30000000
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_SHIFT           28
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_DEFAULT         0
+
+/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK                    0x08000000
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT                   27
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT                 0
+
+/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK        0x04000000
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT       26
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT     0
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:01] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                 0x03fffffe
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT                1
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT              0
+
+/* USB_CTRL :: USB_SIMCTL :: USB_CAP_DIS [00:00] */
+#define BCHP_USB_CTRL_USB_SIMCTL_USB_CAP_DIS_MASK                  0x00000001
+#define BCHP_USB_CTRL_USB_SIMCTL_USB_CAP_DIS_SHIFT                 0
+#define BCHP_USB_CTRL_USB_SIMCTL_USB_CAP_DIS_DEFAULT               0
+
+/***************************************************************************
+ *USB_TESTCTL - Throutput Test Control
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:23] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK              0xff800000
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT             23
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT           0
+
+/* USB_CTRL :: USB_TESTCTL :: CTRLLER_SEL [22:21] */
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_MASK                 0x00600000
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_SHIFT                21
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_DEFAULT              0
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK                     0x00100000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                    20
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                  0
+
+/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK                   0x00080000
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                  19
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT                0
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK                    0x00070000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                   16
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                 0
+
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK              0x0000fc00
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT             10
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT           0
+
+/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK              0x000003ff
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT             0
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT           0
+
+/***************************************************************************
+ *USB_TESTMON - Throughput Test Monitor
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [31:00] */
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK                0xffffffff
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT               0
+
+/***************************************************************************
+ *UTMI_CTL_1 - UTMI Control Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB_P1 [31:31] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_MASK              0x80000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_SHIFT             31
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK             0x70000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT            28
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT          0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK_P1 [27:27] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_MASK                0x08000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_SHIFT               27
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE3 [26:25] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_MASK              0x06000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_SHIFT             25
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY_P1 [24:24] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_MASK                0x01000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_SHIFT               24
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK                0x00800000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT               23
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK                0x00400000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT               22
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK                0x00200000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT               21
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK                0x00100000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT               20
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                  0x000c0000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                 18
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT               0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT       1
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK           0x00010000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT          16
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT        0
+
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB [15:15] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_MASK                 0x00008000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_SHIFT                15
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_DEFAULT              0
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK                0x00007000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT               12
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK [11:11] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_MASK                   0x00000800
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_SHIFT                  11
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE1 [10:09] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_MASK              0x00000600
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_SHIFT             9
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY [08:08] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_MASK                   0x00000100
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_SHIFT                  8
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                   0x00000080
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                  7
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                   0x00000040
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                  6
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                   0x00000020
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                  5
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                   0x00000010
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                  4
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK                     0x0000000c
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                    2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                  0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT          1
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK              0x00000001
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT             0
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT           0
+
+/***************************************************************************
+ *UTMI_CTL_2 - UTMI Control 2 Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK               0xffffffff
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT              0
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT            0
+
+/***************************************************************************
+ *SPARE1 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE1 :: SPARE1_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_DEFAULT                   0
+
+/***************************************************************************
+ *SPARE2 - Spare2 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE2 :: SPARE2_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_DEFAULT                   0
+
+#endif /* #ifndef BCHP_USB_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_wktmr.h b/include/linux/brcmstb/7344b0/bchp_wktmr.h
new file mode 100644
index 0000000..37afa67
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_wktmr.h
@@ -0,0 +1,108 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:31:43 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_wktmr.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 2:39p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_WKTMR_H__
+#define BCHP_WKTMR_H__
+
+/***************************************************************************
+ *WKTMR - Wakeup timer
+ ***************************************************************************/
+#define BCHP_WKTMR_EVENT                         0x00408e80 /* Wakeup Timer Register */
+#define BCHP_WKTMR_COUNTER                       0x00408e84 /* Wakeup Counter */
+#define BCHP_WKTMR_ALARM                         0x00408e88 /* Wakeup Timer Alarm */
+#define BCHP_WKTMR_PRESCALER                     0x00408e8c /* Wakeup Timer Prescaler */
+#define BCHP_WKTMR_PRESCALER_VAL                 0x00408e90 /* Wakeup Timer Prescaler Value */
+
+/***************************************************************************
+ *EVENT - Wakeup Timer Register
+ ***************************************************************************/
+/* WKTMR :: EVENT :: reserved0 [31:01] */
+#define BCHP_WKTMR_EVENT_reserved0_MASK                            0xfffffffe
+#define BCHP_WKTMR_EVENT_reserved0_SHIFT                           1
+
+/* WKTMR :: EVENT :: wktmr_alarm_event [00:00] */
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_MASK                    0x00000001
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_SHIFT                   0
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_DEFAULT                 0
+
+/***************************************************************************
+ *COUNTER - Wakeup Counter
+ ***************************************************************************/
+/* WKTMR :: COUNTER :: wktmr_counter [31:00] */
+#define BCHP_WKTMR_COUNTER_wktmr_counter_MASK                      0xffffffff
+#define BCHP_WKTMR_COUNTER_wktmr_counter_SHIFT                     0
+#define BCHP_WKTMR_COUNTER_wktmr_counter_DEFAULT                   0
+
+/***************************************************************************
+ *ALARM - Wakeup Timer Alarm
+ ***************************************************************************/
+/* WKTMR :: ALARM :: wktmr_alarm [31:00] */
+#define BCHP_WKTMR_ALARM_wktmr_alarm_MASK                          0xffffffff
+#define BCHP_WKTMR_ALARM_wktmr_alarm_SHIFT                         0
+#define BCHP_WKTMR_ALARM_wktmr_alarm_DEFAULT                       0
+
+/***************************************************************************
+ *PRESCALER - Wakeup Timer Prescaler
+ ***************************************************************************/
+/* WKTMR :: PRESCALER :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_reserved0_MASK                        0xfe000000
+#define BCHP_WKTMR_PRESCALER_reserved0_SHIFT                       25
+
+/* WKTMR :: PRESCALER :: wktmr_prescaler [24:00] */
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_MASK                  0x01ffffff
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_SHIFT                 0
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_DEFAULT               27000000
+
+/***************************************************************************
+ *PRESCALER_VAL - Wakeup Timer Prescaler Value
+ ***************************************************************************/
+/* WKTMR :: PRESCALER_VAL :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_MASK                    0xfe000000
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_SHIFT                   25
+
+/* WKTMR :: PRESCALER_VAL :: wktmr_prescaler_val [24:00] */
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_MASK          0x01ffffff
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_SHIFT         0
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_DEFAULT       0
+
+#endif /* #ifndef BCHP_WKTMR_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/brcmirq.h b/include/linux/brcmstb/7344b0/brcmirq.h
new file mode 100644
index 0000000..0a3ce03
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/brcmirq.h
@@ -0,0 +1,47 @@
+/*
+ * 7344b0 IRQ header file autogenerated by update_bchp.pl
+ * DO NOT EDIT THIS FILE BY HAND.
+ *
+ * Copyright (C) 2011 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BRCMIRQ_H_
+#define _BRCMIRQ_H_
+
+#define BRCM_IRQ_EHCI0_0	69
+#define BRCM_IRQ_EHCI0_1	70
+#define BRCM_IRQ_EHCI1_0	74
+#define BRCM_IRQ_EHCI1_1	75
+#define BRCM_IRQ_GENET_0_A	31
+#define BRCM_IRQ_GENET_0_B	32
+#define BRCM_IRQ_GENET_1_A	33
+#define BRCM_IRQ_GENET_1_B	34
+#define BRCM_IRQ_HIF		37
+#define BRCM_IRQ_HIF_SPI	38
+#define BRCM_IRQ_MOCA		42
+#define BRCM_IRQ_OHCI0_0	71
+#define BRCM_IRQ_OHCI0_1	72
+#define BRCM_IRQ_OHCI1_0	76
+#define BRCM_IRQ_OHCI1_1	77
+#define BRCM_IRQ_SDIO0		86
+#define BRCM_IRQ_STANDBY	54
+#define BRCM_IRQ_UARTA		65
+#define BRCM_IRQ_UARTB		66
+#define BRCM_IRQ_UARTC		67
+#define BRCM_IRQLIST_EHCI	{ 69, 70, 74, 75 }
+#define BRCM_IRQLIST_OHCI	{ 71, 72, 76, 77 }
+
+#endif /* _BRCMIRQ_H_ */
diff --git a/include/linux/brcmstb/7346b0/bchp_aon_ctrl.h b/include/linux/brcmstb/7346b0/bchp_aon_ctrl.h
new file mode 100644
index 0000000..d672f40
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_aon_ctrl.h
@@ -0,0 +1,1606 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 24 13:17:52 2011
+ *                 MD5 Checksum         20406eb4287081a441630135cf8f15e2
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_aon_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   5/24/11 5:51p albertl
+ * SW7346-143: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_CTRL_H__
+#define BCHP_AON_CTRL_H__
+
+/***************************************************************************
+ *AON_CTRL - AON Control Registers
+ ***************************************************************************/
+#define BCHP_AON_CTRL_RESET_CTRL                 0x00408000 /* Reset Control register for AON */
+#define BCHP_AON_CTRL_PM_CTRL                    0x00408004 /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_STATUS                  0x00408008 /* Status register for Power Controller */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS        0x0040800c /* Power Management IRQ input status */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT         0x00408010 /* Power Management Wait counter in place of Wait for MIPS IRQ */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER        0x00408014 /* Deep Standby Assertion Timer */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER         0x00408018 /* Deep Standby Wakeup Timer */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE    0x0040801c /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_LED_CTRL                0x00408020 /* LED set control register */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES     0x00408024 /* LED set control register */
+#define BCHP_AON_CTRL_HLCD_CTRL                  0x00408030 /* HW LED Clock Driver Control */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER    0x00408034 /* Second Fraction Counter Initial value */
+#define BCHP_AON_CTRL_TIME_COUNTER               0x00408038 /* Hour/Minute Counter Initial value */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0           0x0040803c /* Digit Code for digit 0, 1, 2, 3 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1           0x00408040 /* Digit Code for digit 4, 5, 6, 7 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2           0x00408044 /* Digit Code for digit 8, 9 */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET      0x00408048 /* Hour MSD/LSD and minute MSD/LSD address offset */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL            0x0040804c /* LED status control */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0             0x00408050 /* General control register 0 */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0           0x00408054 /* General status register 0 */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0     0x00408058 /* General control register without scan 0 */
+#define BCHP_AON_CTRL_SPARE_CTRL_0               0x00408060 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_SPARE_CTRL_1               0x00408064 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH          0x00408068 /* Scratch register */
+#define BCHP_AON_CTRL_RESET_HISTORY              0x0040806c /* Reset History Register For AON */
+#define BCHP_AON_CTRL_NMI_CTRL                   0x00408070 /* Control register for NMI */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL           0x00408074 /* Ana xtal low cur 40g m7fc gisb control */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL         0x00408078 /* Test_mode control register */
+#define BCHP_AON_CTRL_SUB_TEST_MODE              0x0040807c /* Register source for sub_test_mode */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE          0x00408080 /* Final latched testmode value */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE      0x00408084 /* Final latched sub-testmode value */
+#define BCHP_AON_CTRL_PM_INITIATE                0x00408088 /* Power down initiate */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS             0x0040808c /* Power up restore */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL   0x00408090 /* Ana xtal low cur 40g m7fc external CML control */
+
+/***************************************************************************
+ *RESET_CTRL - Reset Control register for AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_CTRL :: reserved0 [31:04] */
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_MASK                    0xfffffff0
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_SHIFT                   4
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [03:03] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000008
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 3
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_DEFAULT 0
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable [02:02] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_MASK     0x00000004
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT    2
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_DEFAULT  0
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_polarity [01:01] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK   0x00000002
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT  1
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_DEFAULT 0
+
+/* AON_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_MASK          0x00000001
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_SHIFT         0
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_DEFAULT       0
+
+/***************************************************************************
+ *PM_CTRL - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_CTRL :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_MASK                       0xffffff00
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_SHIFT                      8
+
+/* AON_CTRL :: PM_CTRL :: min_s3_width_timer_bypass [07:07] */
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_MASK       0x00000080
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_SHIFT      7
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_DEFAULT    0
+
+/* AON_CTRL :: PM_CTRL :: pm_fast_power_down [06:06] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_MASK              0x00000040
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_SHIFT             6
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_DEFAULT           0
+
+/* AON_CTRL :: PM_CTRL :: pm_warm_boot [05:05] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_MASK                    0x00000020
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_SHIFT                   5
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_DEFAULT                 0
+
+/* AON_CTRL :: PM_CTRL :: pm_deep_standby [04:04] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_MASK                 0x00000010
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_SHIFT                4
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_DEFAULT              0
+
+/* AON_CTRL :: PM_CTRL :: pm_clk_divider_reset_en [03:03] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK         0x00000008
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_SHIFT        3
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_DEFAULT      1
+
+/* AON_CTRL :: PM_CTRL :: pm_use_mips_ready_ctrl [02:02] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_MASK          0x00000004
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_SHIFT         2
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_DEFAULT       0
+
+/* AON_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK             0x00000002
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT            1
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_DEFAULT          0
+
+/* AON_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_MASK                  0x00000001
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT                 0
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_DEFAULT               0
+
+/***************************************************************************
+ *PM_STATUS - Status register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_STATUS :: pm_wait_count_upper_bits [31:26] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_MASK      0xfc000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_SHIFT     26
+
+/* AON_CTRL :: PM_STATUS :: pm_wait_counter_active [25:25] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_MASK        0x02000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_SHIFT       25
+
+/* AON_CTRL :: PM_STATUS :: pm_s3_wakeup_reset_ [24:24] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__MASK           0x01000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__SHIFT          24
+
+/* AON_CTRL :: PM_STATUS :: pm_boundary_scan_request [23:23] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_MASK      0x00800000
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_SHIFT     23
+
+/* AON_CTRL :: PM_STATUS :: pm_fast_pd_precharge_valid [22:22] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_MASK    0x00400000
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_SHIFT   22
+
+/* AON_CTRL :: PM_STATUS :: pm_led_out [21:21] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_MASK                    0x00200000
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_SHIFT                   21
+
+/* AON_CTRL :: PM_STATUS :: pm_standby_b [20:20] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_MASK                  0x00100000
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_SHIFT                 20
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs_ng [19:19] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_MASK           0x00080000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_SHIFT          19
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs [18:18] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_MASK              0x00040000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_SHIFT             18
+
+/* AON_CTRL :: PM_STATUS :: pm_rst_clock_div [17:17] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_MASK              0x00020000
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_SHIFT             17
+
+/* AON_CTRL :: PM_STATUS :: pm_pwrdn_pll_req [16:16] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_MASK              0x00010000
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_SHIFT             16
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_xtal_clocks [15:15] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_MASK            0x00008000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_SHIFT           15
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_all_clocks [14:14] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_MASK             0x00004000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_SHIFT            14
+
+/* AON_CTRL :: PM_STATUS :: pm_dphy_standby [13:13] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_MASK               0x00002000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_SHIFT              13
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_cpu_clock [12:12] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_MASK              0x00001000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_SHIFT             12
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_avd_rptd_clock [11:11] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_MASK         0x00000800
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_SHIFT        11
+
+/* AON_CTRL :: PM_STATUS :: pm_power_ctrl_disable [10:10] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_MASK         0x00000400
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_SHIFT        10
+
+/* AON_CTRL :: PM_STATUS :: pm_pll_lock [09:09] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_MASK                   0x00000200
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_SHIFT                  9
+
+/* AON_CTRL :: PM_STATUS :: pm_dram_ready_for_pwrdn [08:08] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_MASK       0x00000100
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_SHIFT      8
+
+/* AON_CTRL :: PM_STATUS :: pm_bsp_ready_for_pwrdn [07:07] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK        0x00000080
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_SHIFT       7
+
+/* AON_CTRL :: PM_STATUS :: pm_mips_ready_for_pwrdn [06:06] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_MASK       0x00000040
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_SHIFT      6
+
+/* AON_CTRL :: PM_STATUS :: pm_sec_avd_rptd_clk_disable [05:05] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_MASK   0x00000020
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_SHIFT  5
+
+/* AON_CTRL :: PM_STATUS :: pm_state [04:00] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_MASK                      0x0000001f
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_SHIFT                     0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_ACTIVE                 0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_PWRDN_RDY              1
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_AVD_RPTD       2
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_CPU            3
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_STANDBY  4
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY                5
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY_WITH_PLLS_ON   6
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_RESET_216_108_CLKS     7
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_ACTIVE   8
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_FAST_PWRDN             9
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S1  10
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_COLD_ENTRY_S2 11
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_WARM_ENTRY_S2 12
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S3  13
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY           14
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S1   15
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S2   16
+
+/***************************************************************************
+ *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
+ ***************************************************************************/
+/* AON_CTRL :: PM_IRQ_INPUT_STATUS :: pm_irq_input_status [31:00] */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_MASK 0xffffffff
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_SHIFT 0
+
+/***************************************************************************
+ *PM_MIPS_WAIT_COUNT - Power Management Wait counter in place of Wait for MIPS IRQ
+ ***************************************************************************/
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_MASK            0xffff0000
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_SHIFT           16
+
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: counter_start_value [15:00] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_MASK  0x0000ffff
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_DEFAULT 16
+
+/***************************************************************************
+ *PM_S3_STANDBY_TIMER - Deep Standby Assertion Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_MASK           0xf8000000
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_SHIFT          27
+
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_MASK 0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_DEFAULT 540000
+
+/***************************************************************************
+ *PM_S3_WAKEUP_TIMER - Deep Standby Wakeup Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_MASK            0xf8000000
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_SHIFT           27
+
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_MASK  0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_DEFAULT 540000
+
+/***************************************************************************
+ *PM_FAST_PWRDN_PRECHARGE - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: reserved0 [31:24] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_MASK       0xff000000
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_SHIFT      24
+
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: pm_fast_power_down_precharge [23:00] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_MASK 0x00ffffff
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_SHIFT 0
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_DEFAULT 0
+
+/***************************************************************************
+ *PM_LED_CTRL - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_CTRL :: reserved0 [31:03] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_MASK                   0xfffffff8
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_SHIFT                  3
+
+/* AON_CTRL :: PM_LED_CTRL :: led_status [02:02] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_MASK                  0x00000004
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_SHIFT                 2
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_on [01:01] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_MASK                 0x00000002
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_SHIFT                1
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_off [00:00] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_MASK                0x00000001
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_SHIFT               0
+
+/***************************************************************************
+ *PM_LED_AUTO_ON_ENABLES - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_AUTO_ON_ENABLES :: led_status [31:00] */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_MASK       0xffffffff
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_SHIFT      0
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_DEFAULT    0
+
+/***************************************************************************
+ *HLCD_CTRL - HW LED Clock Driver Control
+ ***************************************************************************/
+/* AON_CTRL :: HLCD_CTRL :: reserved0 [31:02] */
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_MASK                     0xfffffffc
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_SHIFT                    2
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable_status [01:01] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_MASK            0x00000002
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_SHIFT           1
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable [00:00] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_MASK                   0x00000001
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_SHIFT                  0
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_DEFAULT                0
+
+/***************************************************************************
+ *SECOND_FRACTION_COUNTER - Second Fraction Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: reserved0 [31:25] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_MASK       0xfe000000
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_SHIFT      25
+
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: second_fraction_counter_init [24:00] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_MASK 0x01ffffff
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_SHIFT 0
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_DEFAULT 0
+
+/***************************************************************************
+ *TIME_COUNTER - Hour/Minute Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: TIME_COUNTER :: reserved0 [31:20] */
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_MASK                  0xfff00000
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_SHIFT                 20
+
+/* AON_CTRL :: TIME_COUNTER :: hour_display_mode [19:19] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_MASK          0x00080000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_SHIFT         19
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: mode_12h_24h_init [18:18] */
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_MASK          0x00040000
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_SHIFT         18
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: am_pm_counter_init [17:17] */
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_MASK         0x00020000
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_SHIFT        17
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_DEFAULT      0
+
+/* AON_CTRL :: TIME_COUNTER :: hour_counter_init [16:12] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_MASK          0x0001f000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_SHIFT         12
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: minute_counter_init [11:06] */
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_MASK        0x00000fc0
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_SHIFT       6
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_DEFAULT     0
+
+/* AON_CTRL :: TIME_COUNTER :: second_counter_init [05:00] */
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_MASK        0x0000003f
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_SHIFT       0
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_DEFAULT     0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_0 - Digit Code for digit 0, 1, 2, 3
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_3 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_2 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_1 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_0 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_1 - Digit Code for digit 4, 5, 6, 7
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_7 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_6 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_5 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_4 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_2 - Digit Code for digit 8, 9
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_MASK              0xffff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_SHIFT             16
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_9 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_8 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_ADDR_OFFSET - Hour MSD/LSD and minute MSD/LSD address offset
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_msd_addr_offset [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_MASK 0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_SHIFT 24
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_DEFAULT 32
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_lsd_addr_offset [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_MASK 0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_SHIFT 16
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_DEFAULT 36
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_msd_addr_offset [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_MASK 0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_SHIFT 8
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_DEFAULT 24
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_lsd_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_MASK 0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_SHIFT 0
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_DEFAULT 28
+
+/***************************************************************************
+ *LED_STATUS_CTRL - LED status control
+ ***************************************************************************/
+/* AON_CTRL :: LED_STATUS_CTRL :: reserved0 [31:28] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_MASK               0xf0000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_SHIFT              28
+
+/* AON_CTRL :: LED_STATUS_CTRL :: hlcd_state [27:25] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_MASK              0x0e000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_SHIFT             25
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_IDLE         0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_COUNT        1
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_LSD 2
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_MSD 3
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_LSD 4
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_MSD 5
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_STATUS 6
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_update_enable [24:24] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_MASK    0x01000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_SHIFT   24
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_DEFAULT 0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_mask [23:12] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_MASK             0x00fff000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_SHIFT            12
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_DEFAULT          0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_bit_offset [11:08] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_MASK       0x00000f00
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_SHIFT      8
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_DEFAULT    0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_MASK      0x000000ff
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_SHIFT     0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK         0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT        31
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK         0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT        30
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK         0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT        29
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK         0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT        28
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK         0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT        27
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK         0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT        26
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK         0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT        25
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK         0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT        24
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK         0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT        23
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK         0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT        22
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK         0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT        21
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK         0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT        20
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK         0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT        19
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK         0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT        18
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK         0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT        17
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK         0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT        16
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK         0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT        15
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK         0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT        14
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK         0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT        13
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK         0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT        12
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK         0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT        11
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK         0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT        10
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK          0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT         9
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK          0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT         8
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK          0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT         7
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK          0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT         6
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK          0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT         5
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK          0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT         4
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK          0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT         3
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK          0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT         2
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK          0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT         1
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK          0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT         0
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT       0
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_MASK              0xffffff00
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_SHIFT             8
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_MASK      0x00000080
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT     7
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_MASK      0x00000040
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT     6
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_MASK      0x00000020
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT     5
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_MASK      0x00000010
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT     4
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_MASK      0x00000008
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT     3
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_MASK      0x00000004
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT     2
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_MASK      0x00000002
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT     1
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: ejtag_ce_wakeup_event [00:00] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_MASK  0x00000001
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_MASK 0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_SHIFT 31
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_MASK 0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_SHIFT 30
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_MASK 0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_SHIFT 29
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_MASK 0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_SHIFT 28
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_MASK 0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_SHIFT 27
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_MASK 0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_SHIFT 26
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_MASK 0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_SHIFT 25
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_MASK 0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_SHIFT 24
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_MASK 0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_SHIFT 23
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_MASK 0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_SHIFT 22
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_MASK 0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_SHIFT 21
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_MASK 0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_SHIFT 20
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_MASK 0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_SHIFT 19
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_MASK 0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_SHIFT 18
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_MASK 0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_SHIFT 17
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_MASK 0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_SHIFT 16
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_MASK 0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_SHIFT 15
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_MASK 0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_SHIFT 14
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_MASK 0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_SHIFT 13
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_MASK 0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_SHIFT 12
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_MASK 0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_SHIFT 11
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_MASK 0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_SHIFT 10
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_MASK 0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_SHIFT 5
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_MASK 0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_SHIFT 4
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_MASK 0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_SHIFT 3
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_MASK 0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_SHIFT 2
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_MASK 0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_SHIFT 0
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_DEFAULT 0
+
+/***************************************************************************
+ *SPARE_CTRL_0 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_DEFAULT           0
+
+/***************************************************************************
+ *SPARE_CTRL_1 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_DEFAULT           0
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* AON_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK     0xffffffff
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT    0
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT  0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset History Register For AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_HISTORY :: reserved0 [31:19] */
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_MASK                 0xfff80000
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_SHIFT                19
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [18:18] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK    0x00040000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT   18
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [17:17] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK    0x00020000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT   17
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [16:16] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK     0x00010000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT    16
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [15:15] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK     0x00008000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT    15
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [14:14] */
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK           0x00004000
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT          14
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_DEFAULT        0
+
+/* AON_CTRL :: RESET_HISTORY :: overtemp_reset [13:13] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_MASK            0x00002000
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_SHIFT           13
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_DEFAULT         0
+
+/* AON_CTRL :: RESET_HISTORY :: overvoltage_reset [12:12] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_MASK         0x00001000
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT        12
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_DEFAULT      0
+
+/* AON_CTRL :: RESET_HISTORY :: undervoltage_reset [11:11] */
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_MASK        0x00000800
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT       11
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_DEFAULT     0
+
+/* AON_CTRL :: RESET_HISTORY :: security_dl_sw_reset [10:10] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK      0x00000400
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT     10
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_DEFAULT   0
+
+/* AON_CTRL :: RESET_HISTORY :: security_master_reset [09:09] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_MASK     0x00000200
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_SHIFT    9
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: software_master_reset [08:08] */
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_MASK     0x00000100
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_SHIFT    8
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [07:07] */
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK       0x00000080
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT      7
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_DEFAULT    0
+
+/* AON_CTRL :: RESET_HISTORY :: watchdog_timer_reset [06:06] */
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK      0x00000040
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT     6
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_DEFAULT   0
+
+/* AON_CTRL :: RESET_HISTORY :: smartcard_insert_reset [05:05] */
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK    0x00000020
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT   5
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: s3_wakeup_reset [04:04] */
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_MASK           0x00000010
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_SHIFT          4
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_DEFAULT        0
+
+/* AON_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [03:03] */
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK    0x00000008
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT   3
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: tap_in_system_reset [02:02] */
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_MASK       0x00000004
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_SHIFT      2
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_DEFAULT    0
+
+/* AON_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_MASK     0x00000002
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT    1
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_MASK            0x00000001
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_SHIFT           0
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_DEFAULT         1
+
+/***************************************************************************
+ *NMI_CTRL - Control register for NMI
+ ***************************************************************************/
+/* AON_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_MASK                0x80000000
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_SHIFT               31
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_DEFAULT             0
+
+/* AON_CTRL :: NMI_CTRL :: reserved0 [30:03] */
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_MASK                      0x7ffffff8
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_SHIFT                     3
+
+/* AON_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_MASK                0x00000004
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT               2
+
+/* AON_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_MASK            0x00000002
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT           1
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_DEFAULT         0
+
+/* AON_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_MASK                0x00000001
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT               0
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_DEFAULT             1
+
+/***************************************************************************
+ *ANA_XTAL_CONTROL - Ana xtal low cur 40g m7fc gisb control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_CONTROL :: reserved0 [31:09] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_MASK              0xfffffe00
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_SHIFT             9
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_test_select_gisb_control [08:08] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_MASK 0x00000100
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_SHIFT 8
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_select_current_gisb_control [07:07] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_MASK 0x00000080
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_SHIFT 7
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_cml_sel_pd [06:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_MASK         0x00000078
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_SHIFT        3
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_DEFAULT      8
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_d2cbias_gisb_control [02:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_MASK 0x00000007
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_SHIFT 0
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_DEFAULT 4
+
+/***************************************************************************
+ *SUB_TEST_MODE_CTRL - Test_mode control register
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: reserved0 [31:01] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_MASK            0xfffffffe
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_SHIFT           1
+
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: use_sub_test_mode_reg_src [00:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_MASK 0x00000001
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_SHIFT 0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_DEFAULT 0
+
+/***************************************************************************
+ *SUB_TEST_MODE - Register source for sub_test_mode
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_MASK                 0xffffff00
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_SHIFT                8
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [07:07] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK     0x00000080
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT    7
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_DEFAULT  0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_alternate_enable [06:06] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_alternate_enable_MASK 0x00000040
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_alternate_enable_SHIFT 6
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_alternate_enable_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [05:05] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK   0x00000020
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT  5
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_mips_in_reset [04:04] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_MASK 0x00000010
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_SHIFT 4
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [03:03] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000008
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 3
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [02:02] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000004
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 2
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK   0x00000003
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT  0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_DEFAULT 0
+
+/***************************************************************************
+ *LATCHED_TEST_MODE - Final latched testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK     0xffffffff
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT    0
+
+/***************************************************************************
+ *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0
+
+/***************************************************************************
+ *PM_INITIATE - Power down initiate
+ ***************************************************************************/
+/* AON_CTRL :: PM_INITIATE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_MASK                   0xffffff00
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_SHIFT                  8
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_7 [07:07] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_MASK               0x00000080
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_SHIFT              7
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_6 [06:06] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_MASK               0x00000040
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_SHIFT              6
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_5 [05:05] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_MASK               0x00000020
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_SHIFT              5
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_4 [04:04] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_MASK               0x00000010
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_SHIFT              4
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_3 [03:03] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_MASK               0x00000008
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_SHIFT              3
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_2 [02:02] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_MASK               0x00000004
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_SHIFT              2
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_1 [01:01] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_MASK               0x00000002
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_SHIFT              1
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_0 [00:00] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_MASK               0x00000001
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_SHIFT              0
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_DEFAULT            0
+
+/***************************************************************************
+ *HOST_MISC_CMDS - Power up restore
+ ***************************************************************************/
+/* AON_CTRL :: HOST_MISC_CMDS :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_MASK                0xffffff00
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_SHIFT               8
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_7 [07:07] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_MASK         0x00000080
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_SHIFT        7
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_6 [06:06] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_MASK         0x00000040
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_SHIFT        6
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_5 [05:05] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_MASK         0x00000020
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_SHIFT        5
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_4 [04:04] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_MASK         0x00000010
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_SHIFT        4
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_3 [03:03] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_MASK         0x00000008
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_SHIFT        3
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_2 [02:02] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_MASK         0x00000004
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_SHIFT        2
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: dram_scram_key_reuse_req [01:01] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_MASK 0x00000002
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_SHIFT 1
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_DEFAULT 0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: pm_restore [00:00] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_MASK               0x00000001
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_SHIFT              0
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_DEFAULT            0
+
+/***************************************************************************
+ *ANA_XTAL_EXT_CML_CONTROL - Ana xtal low cur 40g m7fc external CML control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: reserved0 [31:06] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_reserved0_MASK      0xffffffc0
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_reserved0_SHIFT     6
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_PMSM_S3_pd_buffer [05:05] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_MASK 0x00000020
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_SHIFT 5
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_override_strap [04:04] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_MASK 0x00000010
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_SHIFT 4
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_pd_buffer [03:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_MASK  0x00000008
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_SHIFT 3
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_div2_sel [02:02] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_MASK   0x00000004
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_SHIFT  2
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_DEFAULT 1
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_current [01:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_MASK    0x00000003
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_SHIFT   0
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_DEFAULT 1
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_BASE                  0x00408200
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_START                 0
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_END                   127
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_ELEMENT_SIZE          32
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_RAMi :: SYSTEM_DATA_RAM [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_MASK        0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_SHIFT       0
+
+
+#endif /* #ifndef BCHP_AON_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_aon_pin_ctrl.h b/include/linux/brcmstb/7346b0/bchp_aon_pin_ctrl.h
new file mode 100644
index 0000000..2dd9862
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_aon_pin_ctrl.h
@@ -0,0 +1,658 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 24 13:05:37 2011
+ *                 MD5 Checksum         20406eb4287081a441630135cf8f15e2
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_aon_pin_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   5/24/11 5:51p albertl
+ * SW7346-143: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PIN_CTRL_H__
+#define BCHP_AON_PIN_CTRL_H__
+
+/***************************************************************************
+ *AON_PIN_CTRL - AON Pinmux Control Registers
+ ***************************************************************************/
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0         0x00408500 /* Pinmux control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1         0x00408504 /* Pinmux control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2         0x00408508 /* Pinmux control register 2 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3         0x0040850c /* Pinmux control register 3 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0     0x00408510 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1     0x00408514 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2     0x00408518 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0     0x0040851c /* Bypass clock unselect register 0 */
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_005 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_005_MASK         0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_005_SHIFT        28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_005_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_005_AON_GPIO_005 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_005_LED_LS_1     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_005_SC0_PRES     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_005_CI2CHIP_MDI3 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_005_PKT_VALID4   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_005_TP_OUT_05    5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_004 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_004_MASK         0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_004_SHIFT        24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_004_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_004_AON_GPIO_004 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_004_LED_LS_0     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_004_SC0_RST      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_004_CI2CHIP_MDI2 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_004_PKT_DATA4    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_004_TP_OUT_04    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_004_PM_AON_GPIO_004 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_sgpio_03 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_03_MASK         0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_03_SHIFT        20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_03_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_03_AON_SGPIO_03 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_03_LED_KD_3     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_03_BSC_M4_SDA   2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_sgpio_02 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_02_MASK         0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_02_SHIFT        16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_02_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_02_AON_SGPIO_02 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_02_LED_KD_2     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_02_BSC_M4_SCL   2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_001 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_001_MASK         0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_001_SHIFT        12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_001_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_001_AON_GPIO_001 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_001_LED_KD_1     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_001_SC_EXT_CLK   2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_001_CI2CHIP_MIVAL 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_001_PM_AON_GPIO_001 4
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_000 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_000_MASK         0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_000_SHIFT        8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_000_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_000_AON_GPIO_000 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_000_LED_KD_0     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_000_SC_CLK_OUT   2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_000_CI2CHIP_MISTRT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_000_PM_AON_GPIO_000 4
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_ir_in0 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_MASK           0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_SHIFT          4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_DEFAULT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_AON_IR_IN0     0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_TP_IN_03       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_PM_AON_IR_IN0  2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: hdmi_htplg [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_hdmi_htplg_MASK           0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_hdmi_htplg_SHIFT          0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_hdmi_htplg_DEFAULT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_hdmi_htplg_HDMI_HTPLG     0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_hdmi_htplg_ALT_TP_OUT_26  1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_013 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_013_MASK         0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_013_SHIFT        28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_013_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_013_AON_GPIO_013 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_013_LED_LD_4     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_013_SC1_RST      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_013_CHIP2CI_MDO0 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_013_EXT_IRQB_1   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_013_SPI_M_SS0B   5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_013_TP_OUT_13    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_013_PM_AON_GPIO_013 7
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_012 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_012_MASK         0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_012_SHIFT        24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_012_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_012_AON_GPIO_012 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_012_LED_LD_3     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_012_SC1_PRES     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_012_CHIP2CI_MOSTRT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_012_EXT_IRQB_0   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_012_TP_OUT_12    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_012_PM_AON_GPIO_012 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_011 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_011_MASK         0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_011_SHIFT        20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_011_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_011_AON_GPIO_011 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_011_LED_LD_2     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_011_SC1_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_011_CHIP2CI_MOVAL 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_011_IR_OUT       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_011_TP_OUT_19    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_011_PM_AON_GPIO_011 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_010 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_010_MASK         0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_010_SHIFT        16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_010_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_010_AON_GPIO_010 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_010_LED_LD_1     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_010_SC1_IO       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_010_CI2CHIP_MICLK 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_010_PM_AON_GPIO_010 4
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_009 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_009_MASK         0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_009_SHIFT        12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_009_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_009_AON_GPIO_009 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_009_LED_LD_0     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_009_SC0_VPP      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_009_CI2CHIP_MDI7 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_009_I2S_LR1_OUT  4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_009_I2S_LR1_IN   5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_009_PM_AON_GPIO_009 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_008 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_MASK         0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_SHIFT        8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_AON_GPIO_008 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_LED_LS_4     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_SC0_AUX_2    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_CI2CHIP_MDI6 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_I2S_DATA1_OUT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_I2S_DATA1_IN 5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_PKT_CLK4     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_TP_OUT_08    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_PM_AON_GPIO_008 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_007 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_MASK         0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_SHIFT        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_AON_GPIO_007 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_LED_LS_3     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_SC0_AUX_1    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_CI2CHIP_MDI5 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_I2S_CLK1_OUT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_I2S_CLK1_IN  5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_PKT_ERROR4   6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_TP_OUT_24    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_PM_AON_GPIO_007 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_006 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_006_MASK         0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_006_SHIFT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_006_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_006_AON_GPIO_006 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_006_LED_LS_2     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_006_SC0_VCC      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_006_CI2CHIP_MDI4 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_006_PKT_SYNC4    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_006_TP_OUT_06    5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_021 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_021_MASK         0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_021_SHIFT        28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_021_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_021_AON_GPIO_021 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_021_SPI_M_SCK    1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_021_CHIP2CI_MOCLK 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_021_TTX0_REQ     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_021_VEC_VSYNC_0  4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_021_VEC_HSYNC_0  5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_021_TP_IN_07     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_021_PM_AON_GPIO_021 7
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_020 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_020_MASK         0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_020_SHIFT        24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_020_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_020_AON_GPIO_020 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_020_SPI_M_MISO   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_020_CHIP2CI_MDO7 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_020_VEC_VSYNC_1  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_020_VEC_HSYNC_1  4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_020_TTX0_DATA    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_020_TP_OUT_22    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_020_PM_AON_GPIO_020 7
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_019 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_019_MASK         0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_019_SHIFT        20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_019_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_019_AON_GPIO_019 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_019_SPI_M_MOSI   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_019_CHIP2CI_MDO6 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_019_VEC_VSYNC_0  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_019_VEC_HSYNC_0  4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_019_TP_OUT_27    5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_018 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_018_MASK         0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_018_SHIFT        16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_018_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_018_AON_GPIO_018 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_018_SPI_M_SCK    1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_018_CHIP2CI_MDO5 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_018_TP_OUT_16    3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_017 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_017_MASK         0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_017_SHIFT        12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_017_DEFAULT      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_017_AON_GPIO_017 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_017_IR_OUT       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_017_SC1_VPP      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_017_CHIP2CI_MDO4 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_017_LED_OUT      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_017_TP_OUT_15    5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_016 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_016_MASK         0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_016_SHIFT        8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_016_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_016_AON_GPIO_016 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_016_LED_LD_7     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_016_SC1_AUX_2    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_016_CHIP2CI_MDO3 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_016_EXT_IRQB_4   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_016_SPI_M_MISO   5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_016_TP_IN_21     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_016_PM_AON_GPIO_016 7
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_015 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_015_MASK         0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_015_SHIFT        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_015_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_015_AON_GPIO_015 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_015_LED_LD_6     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_015_SC1_AUX_1    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_015_CHIP2CI_MDO2 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_015_EXT_IRQB_3   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_015_SPI_M_MOSI   5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_015_TP_IN_04     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_015_PM_AON_GPIO_015 7
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_014 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_014_MASK         0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_014_SHIFT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_014_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_014_AON_GPIO_014 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_014_LED_LD_5     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_014_SC1_VCC      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_014_CHIP2CI_MDO1 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_014_EXT_IRQB_2   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_014_SPI_M_SCK    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_014_TP_OUT_14    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_014_PM_AON_GPIO_014 7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: reserved0 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_MASK            0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_SHIFT           28
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_01 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_MASK         0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_SHIFT        24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_AON_SGPIO_01 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_BSC_M0_SDA   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_TP_IN_22     2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_00 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_00_MASK         0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_00_SHIFT        20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_00_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_00_AON_SGPIO_00 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_00_BSC_M0_SCL   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_00_TP_IN_23     2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_gpio_026 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_026_MASK         0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_026_SHIFT        16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_026_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_026_AON_GPIO_026 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_026_IR_IN1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_026_AUD_FS_CLK1  2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_026_SDS1_DSEC_TXEN 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_026_CI2CHIP_MDI1 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_026_TP_OUT_00    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_026_PM_AON_GPIO_026 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_gpio_025 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_025_MASK         0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_025_SHIFT        12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_025_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_025_AON_GPIO_025 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_025_IR_INT       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_025_AUD_FS_CLK0  2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_025_SDS1_DSEC_TXOUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_025_CI2CHIP_MDI0 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_025_TP_IN_29     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_025_PM_AON_GPIO_025 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_gpio_024 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_024_MASK         0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_024_SHIFT        8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_024_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_024_AON_GPIO_024 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_024_SPI_M_SS0B   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_024_AUD_FS_CLK1  2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_024_CI2CHIP_MCLKI 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_024_SC0_CLK      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_024_TP_IN_28     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_024_PM_AON_GPIO_024 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_gpio_023 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_023_MASK         0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_023_SHIFT        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_023_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_023_AON_GPIO_023 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_023_SPI_M_SS1B   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_023_AUD_FS_CLK0  2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_023_CHIP2CI_MCLKO 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_023_SC0_IO       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_023_TP_OUT_10    5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_gpio_022 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_022_MASK         0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_022_SHIFT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_022_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_022_AON_GPIO_022 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_022_SPI_M_SS2B   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_022_TP_OUT_09    2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_012_pad_ctrl [29:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_012_pad_ctrl_MASK 0x30000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_012_pad_ctrl_SHIFT 28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_012_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_012_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_012_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_012_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_011_pad_ctrl [27:26] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_011_pad_ctrl_MASK 0x0c000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_011_pad_ctrl_SHIFT 26
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_011_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_011_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_011_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_011_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_010_pad_ctrl [25:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_010_pad_ctrl_MASK 0x03000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_010_pad_ctrl_SHIFT 24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_010_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_010_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_010_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_010_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_009_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_009_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_009_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_009_pad_ctrl_DEFAULT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_009_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_009_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_009_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_008_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_008_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_008_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_008_pad_ctrl_DEFAULT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_008_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_008_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_008_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_007_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_007_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_007_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_007_pad_ctrl_DEFAULT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_007_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_007_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_007_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [17:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x0003c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       14
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_004_pad_ctrl [13:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_004_pad_ctrl_MASK 0x00003000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_004_pad_ctrl_SHIFT 12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_004_pad_ctrl_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_004_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_004_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_004_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved1 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_MASK        0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_SHIFT       8
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_001_pad_ctrl [07:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_001_pad_ctrl_MASK 0x000000c0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_001_pad_ctrl_SHIFT 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_001_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_001_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_001_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_001_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_000_pad_ctrl [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_000_pad_ctrl_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_000_pad_ctrl_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_000_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_000_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_000_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_000_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_ir_in0_pad_ctrl [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_ir_in0_pad_ctrl_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_ir_in0_pad_ctrl_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_ir_in0_pad_ctrl_DEFAULT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_ir_in0_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_ir_in0_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_ir_in0_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved2 [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved2_MASK        0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved2_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0x30000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       28
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_026_pad_ctrl [27:26] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_026_pad_ctrl_MASK 0x0c000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_026_pad_ctrl_SHIFT 26
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_026_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_026_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_026_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_026_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_025_pad_ctrl [25:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_025_pad_ctrl_MASK 0x03000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_025_pad_ctrl_SHIFT 24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_025_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_025_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_025_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_025_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_024_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_024_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_024_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_024_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_024_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_024_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_024_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved1 [21:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved1_MASK        0x003c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved1_SHIFT       18
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_021_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_021_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_021_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_021_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_021_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_021_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_021_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_020_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_020_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_020_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_020_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_020_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_020_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_020_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved2 [13:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved2_MASK        0x00003f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved2_SHIFT       8
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_016_pad_ctrl [07:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_016_pad_ctrl_MASK 0x000000c0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_016_pad_ctrl_SHIFT 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_016_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_016_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_016_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_016_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_015_pad_ctrl [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_015_pad_ctrl_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_015_pad_ctrl_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_015_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_015_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_015_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_015_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_014_pad_ctrl [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_014_pad_ctrl_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_014_pad_ctrl_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_014_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_014_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_014_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_014_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_013_pad_ctrl [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_013_pad_ctrl_MASK 0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_013_pad_ctrl_SHIFT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_013_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_013_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_013_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_013_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [31:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK        0xfffffff0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT       4
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved1 [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_MASK        0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_SHIFT       0
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:04] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffff0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       4
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_010 [03:03] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_010_MASK 0x00000008
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_010_SHIFT 3
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_010_DEFAULT 0
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_009 [02:02] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_009_MASK 0x00000004
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_009_SHIFT 2
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_009_DEFAULT 0
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_001 [01:01] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_001_MASK 0x00000002
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_001_SHIFT 1
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_001_DEFAULT 0
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_000 [00:00] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_000_MASK 0x00000001
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_000_SHIFT 0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_000_DEFAULT 0
+
+#endif /* #ifndef BCHP_AON_PIN_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_aon_pm_l2.h b/include/linux/brcmstb/7346b0/bchp_aon_pm_l2.h
new file mode 100644
index 0000000..f511dfd
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_aon_pm_l2.h
@@ -0,0 +1,1647 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:11:10 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_aon_pm_l2.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 2:26p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PM_L2_H__
+#define BCHP_AON_PM_L2_H__
+
+/***************************************************************************
+ *AON_PM_L2 - AON Power Management L2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_AON_PM_L2_CPU_STATUS                0x00408440 /* CPU interrupt Status Register */
+#define BCHP_AON_PM_L2_CPU_SET                   0x00408444 /* CPU interrupt Set Register */
+#define BCHP_AON_PM_L2_CPU_CLEAR                 0x00408448 /* CPU interrupt Clear Register */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS           0x0040844c /* CPU interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_CPU_MASK_SET              0x00408450 /* CPU interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR            0x00408454 /* CPU interrupt Mask Clear Register */
+#define BCHP_AON_PM_L2_PCI_STATUS                0x00408458 /* PCI interrupt Status Register */
+#define BCHP_AON_PM_L2_PCI_SET                   0x0040845c /* PCI interrupt Set Register */
+#define BCHP_AON_PM_L2_PCI_CLEAR                 0x00408460 /* PCI interrupt Clear Register */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS           0x00408464 /* PCI interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_PCI_MASK_SET              0x00408468 /* PCI interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR            0x0040846c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_STATUS :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_MASK                   0xfe000000
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_SHIFT                  25
+
+/* AON_PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x01000000
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       24
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0
+
+/* AON_PM_L2 :: CPU_STATUS :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_MASK                    0x00800000
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_SHIFT                   23
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00400000
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_SHIFT          22
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0
+
+/* AON_PM_L2 :: CPU_STATUS :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_MASK                        0x00200000
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_SHIFT                       21
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_MASK                        0x00100000
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_SHIFT                       20
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_MASK                        0x00080000
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_SHIFT                       19
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_MASK                     0x00040000
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_SHIFT                    18
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_STATUS :: FTM [17:17] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_MASK                         0x00020000
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_SHIFT                        17
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_AFEC_MASK                   0x00010000
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_AFEC_SHIFT                  16
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_AFEC_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_TFEC_MASK                   0x00008000
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_TFEC_SHIFT                  15
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_TFEC_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_RCVR_1_MASK                 0x00004000
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_RCVR_1_SHIFT                14
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_RCVR_1_DEFAULT              0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_RCVR_0_MASK                 0x00002000
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_RCVR_0_SHIFT                13
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_RCVR_0_DEFAULT              0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_MASK                   0x00001000
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_SHIFT                  12
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_MASK                   0x00000800
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_SHIFT                  11
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_MASK                 0x00000400
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_SHIFT                10
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_DEFAULT              0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_MASK                 0x00000200
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_SHIFT                9
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_DEFAULT              0
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_MASK                    0x00000100
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_SHIFT                   8
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_MASK                    0x00000080
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_SHIFT                   7
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_STATUS_UHFR_MASK                        0x00000040
+#define BCHP_AON_PM_L2_CPU_STATUS_UHFR_SHIFT                       6
+#define BCHP_AON_PM_L2_CPU_STATUS_UHFR_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_DEFAULT                 0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_SET :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_MASK                      0xfe000000
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_SHIFT                     25
+
+/* AON_PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_MASK           0x01000000
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_SHIFT          24
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0
+
+/* AON_PM_L2 :: CPU_SET :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_MASK                       0x00800000
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_SHIFT                      23
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_MASK              0x00400000
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_SHIFT             22
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_DEFAULT           0
+
+/* AON_PM_L2 :: CPU_SET :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_CPU_SET_USB1_MASK                           0x00200000
+#define BCHP_AON_PM_L2_CPU_SET_USB1_SHIFT                          21
+#define BCHP_AON_PM_L2_CPU_SET_USB1_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_SET_USB0_MASK                           0x00100000
+#define BCHP_AON_PM_L2_CPU_SET_USB0_SHIFT                          20
+#define BCHP_AON_PM_L2_CPU_SET_USB0_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_MASK                           0x00080000
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_SHIFT                          19
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_MASK                        0x00040000
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_SHIFT                       18
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_SET :: FTM [17:17] */
+#define BCHP_AON_PM_L2_CPU_SET_FTM_MASK                            0x00020000
+#define BCHP_AON_PM_L2_CPU_SET_FTM_SHIFT                           17
+#define BCHP_AON_PM_L2_CPU_SET_FTM_DEFAULT                         0
+
+/* AON_PM_L2 :: CPU_SET :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_AFEC_MASK                      0x00010000
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_AFEC_SHIFT                     16
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_AFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_SET :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_TFEC_MASK                      0x00008000
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_TFEC_SHIFT                     15
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_TFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_SET :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_RCVR_1_MASK                    0x00004000
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_RCVR_1_SHIFT                   14
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_RCVR_1_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_SET :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_RCVR_0_MASK                    0x00002000
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_RCVR_0_SHIFT                   13
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_RCVR_0_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_MASK                      0x00001000
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_SHIFT                     12
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_MASK                      0x00000800
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_SHIFT                     11
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_MASK                    0x00000400
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_SHIFT                   10
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_MASK                    0x00000200
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_SHIFT                   9
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_MASK                       0x00000100
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_SHIFT                      8
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_MOCA_MASK                       0x00000080
+#define BCHP_AON_PM_L2_CPU_SET_WOL_MOCA_SHIFT                      7
+#define BCHP_AON_PM_L2_CPU_SET_WOL_MOCA_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_SET_UHFR_MASK                           0x00000040
+#define BCHP_AON_PM_L2_CPU_SET_UHFR_SHIFT                          6
+#define BCHP_AON_PM_L2_CPU_SET_UHFR_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_DEFAULT                    0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_CLEAR :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_MASK                    0xfe000000
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_SHIFT                   25
+
+/* AON_PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x01000000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        24
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_MASK                     0x00800000
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_SHIFT                    23
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00400000
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           22
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0
+
+/* AON_PM_L2 :: CPU_CLEAR :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_MASK                         0x00200000
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_SHIFT                        21
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_MASK                         0x00100000
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_SHIFT                        20
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_MASK                         0x00080000
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_SHIFT                        19
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_MASK                      0x00040000
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT                     18
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_CLEAR :: FTM [17:17] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_MASK                          0x00020000
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_SHIFT                         17
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_DEFAULT                       0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_AFEC_MASK                    0x00010000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_AFEC_SHIFT                   16
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_AFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_TFEC_MASK                    0x00008000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_TFEC_SHIFT                   15
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_TFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_RCVR_1_MASK                  0x00004000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_RCVR_1_SHIFT                 14
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_RCVR_1_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_RCVR_0_MASK                  0x00002000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_RCVR_0_SHIFT                 13
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_RCVR_0_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_MASK                    0x00001000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_SHIFT                   12
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_MASK                    0x00000800
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_SHIFT                   11
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_MASK                  0x00000400
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_SHIFT                 10
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_MASK                  0x00000200
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_SHIFT                 9
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_MASK                     0x00000100
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_SHIFT                    8
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_MOCA_MASK                     0x00000080
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_MOCA_SHIFT                    7
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_MOCA_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_UHFR_MASK                         0x00000040
+#define BCHP_AON_PM_L2_CPU_CLEAR_UHFR_SHIFT                        6
+#define BCHP_AON_PM_L2_CPU_CLEAR_UHFR_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_DEFAULT                  0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_MASK              0xfe000000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT             25
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x01000000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  24
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_MASK               0x00800000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_SHIFT              23
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00400000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     22
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_MASK                   0x00200000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_SHIFT                  21
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_MASK                   0x00100000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_SHIFT                  20
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_MASK                   0x00080000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_SHIFT                  19
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK                0x00040000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT               18
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FTM [17:17] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_MASK                    0x00020000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_SHIFT                   17
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_AFEC_MASK              0x00010000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_AFEC_SHIFT             16
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_AFEC_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_TFEC_MASK              0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_TFEC_SHIFT             15
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_TFEC_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_RCVR_1_MASK            0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_RCVR_1_SHIFT           14
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_RCVR_1_DEFAULT         1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_RCVR_0_MASK            0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_RCVR_0_SHIFT           13
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_RCVR_0_DEFAULT         1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_MASK              0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_SHIFT             12
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_MASK              0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_SHIFT             11
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_MASK            0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_SHIFT           10
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_DEFAULT         1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_MASK            0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_SHIFT           9
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_DEFAULT         1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_MASK               0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_SHIFT              8
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_MOCA_MASK               0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_MOCA_SHIFT              7
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_MOCA_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_UHFR_MASK                   0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_UHFR_SHIFT                  6
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_UHFR_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_DEFAULT            1
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_SET :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_MASK                 0xfe000000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_SHIFT                25
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x01000000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     24
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_MASK                  0x00800000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_SHIFT                 23
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00400000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        22
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_MASK                      0x00200000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_SHIFT                     21
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_MASK                      0x00100000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_SHIFT                     20
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_MASK                      0x00080000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_SHIFT                     19
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_MASK                   0x00040000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT                  18
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FTM [17:17] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_MASK                       0x00020000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_SHIFT                      17
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_DEFAULT                    1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_AFEC_MASK                 0x00010000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_AFEC_SHIFT                16
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_AFEC_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_TFEC_MASK                 0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_TFEC_SHIFT                15
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_TFEC_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_RCVR_1_MASK               0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_RCVR_1_SHIFT              14
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_RCVR_1_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_RCVR_0_MASK               0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_RCVR_0_SHIFT              13
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_RCVR_0_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_MASK                 0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_SHIFT                12
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_MASK                 0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_SHIFT                11
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_MASK               0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_SHIFT              10
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_MASK               0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_SHIFT              9
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_MASK                  0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_SHIFT                 8
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_MOCA_MASK                  0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_MOCA_SHIFT                 7
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_MOCA_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_UHFR_MASK                      0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_SET_UHFR_SHIFT                     6
+#define BCHP_AON_PM_L2_CPU_MASK_SET_UHFR_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_DEFAULT               1
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_MASK               0xfe000000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT              25
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x01000000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   24
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_MASK                0x00800000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_SHIFT               23
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00400000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      22
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_MASK                    0x00200000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_SHIFT                   21
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_MASK                    0x00100000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_SHIFT                   20
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_MASK                    0x00080000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_SHIFT                   19
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK                 0x00040000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT                18
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FTM [17:17] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_MASK                     0x00020000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_SHIFT                    17
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_DEFAULT                  1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_AFEC_MASK               0x00010000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_AFEC_SHIFT              16
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_AFEC_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_TFEC_MASK               0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_TFEC_SHIFT              15
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_TFEC_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_RCVR_1_MASK             0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_RCVR_1_SHIFT            14
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_RCVR_1_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_RCVR_0_MASK             0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_RCVR_0_SHIFT            13
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_RCVR_0_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_MASK               0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_SHIFT              12
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_MASK               0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_SHIFT              11
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_MASK             0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_SHIFT            10
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_MASK             0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_SHIFT            9
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_MASK                0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_SHIFT               8
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_MASK                0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_SHIFT               7
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_UHFR_MASK                    0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_UHFR_SHIFT                   6
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_UHFR_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_DEFAULT             1
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_STATUS :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_MASK                   0xfe000000
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_SHIFT                  25
+
+/* AON_PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x01000000
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       24
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0
+
+/* AON_PM_L2 :: PCI_STATUS :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_MASK                    0x00800000
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_SHIFT                   23
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00400000
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_SHIFT          22
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0
+
+/* AON_PM_L2 :: PCI_STATUS :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_MASK                        0x00200000
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_SHIFT                       21
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_MASK                        0x00100000
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_SHIFT                       20
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_MASK                        0x00080000
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_SHIFT                       19
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_MASK                     0x00040000
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_SHIFT                    18
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_STATUS :: FTM [17:17] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_MASK                         0x00020000
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_SHIFT                        17
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_AFEC_MASK                   0x00010000
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_AFEC_SHIFT                  16
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_AFEC_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_TFEC_MASK                   0x00008000
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_TFEC_SHIFT                  15
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_TFEC_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_RCVR_1_MASK                 0x00004000
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_RCVR_1_SHIFT                14
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_RCVR_1_DEFAULT              0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_RCVR_0_MASK                 0x00002000
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_RCVR_0_SHIFT                13
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_RCVR_0_DEFAULT              0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_MASK                   0x00001000
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_SHIFT                  12
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_MASK                   0x00000800
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_SHIFT                  11
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_MASK                 0x00000400
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_SHIFT                10
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_DEFAULT              0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_MASK                 0x00000200
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_SHIFT                9
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_DEFAULT              0
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_MASK                    0x00000100
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_SHIFT                   8
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_MOCA_MASK                    0x00000080
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_MOCA_SHIFT                   7
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_MOCA_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_STATUS_UHFR_MASK                        0x00000040
+#define BCHP_AON_PM_L2_PCI_STATUS_UHFR_SHIFT                       6
+#define BCHP_AON_PM_L2_PCI_STATUS_UHFR_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_DEFAULT                 0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_SET :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_MASK                      0xfe000000
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_SHIFT                     25
+
+/* AON_PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_MASK           0x01000000
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_SHIFT          24
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0
+
+/* AON_PM_L2 :: PCI_SET :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_MASK                       0x00800000
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_SHIFT                      23
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_MASK              0x00400000
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_SHIFT             22
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_DEFAULT           0
+
+/* AON_PM_L2 :: PCI_SET :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_PCI_SET_USB1_MASK                           0x00200000
+#define BCHP_AON_PM_L2_PCI_SET_USB1_SHIFT                          21
+#define BCHP_AON_PM_L2_PCI_SET_USB1_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_SET_USB0_MASK                           0x00100000
+#define BCHP_AON_PM_L2_PCI_SET_USB0_SHIFT                          20
+#define BCHP_AON_PM_L2_PCI_SET_USB0_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_MASK                           0x00080000
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_SHIFT                          19
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_MASK                        0x00040000
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_SHIFT                       18
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_SET :: FTM [17:17] */
+#define BCHP_AON_PM_L2_PCI_SET_FTM_MASK                            0x00020000
+#define BCHP_AON_PM_L2_PCI_SET_FTM_SHIFT                           17
+#define BCHP_AON_PM_L2_PCI_SET_FTM_DEFAULT                         0
+
+/* AON_PM_L2 :: PCI_SET :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_AFEC_MASK                      0x00010000
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_AFEC_SHIFT                     16
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_AFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_SET :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_TFEC_MASK                      0x00008000
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_TFEC_SHIFT                     15
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_TFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_SET :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_RCVR_1_MASK                    0x00004000
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_RCVR_1_SHIFT                   14
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_RCVR_1_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_SET :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_RCVR_0_MASK                    0x00002000
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_RCVR_0_SHIFT                   13
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_RCVR_0_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_MASK                      0x00001000
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_SHIFT                     12
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_MASK                      0x00000800
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_SHIFT                     11
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_MASK                    0x00000400
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_SHIFT                   10
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_MASK                    0x00000200
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_SHIFT                   9
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_MASK                       0x00000100
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_SHIFT                      8
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_MOCA_MASK                       0x00000080
+#define BCHP_AON_PM_L2_PCI_SET_WOL_MOCA_SHIFT                      7
+#define BCHP_AON_PM_L2_PCI_SET_WOL_MOCA_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_SET_UHFR_MASK                           0x00000040
+#define BCHP_AON_PM_L2_PCI_SET_UHFR_SHIFT                          6
+#define BCHP_AON_PM_L2_PCI_SET_UHFR_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_DEFAULT                    0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_CLEAR :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_MASK                    0xfe000000
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_SHIFT                   25
+
+/* AON_PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x01000000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        24
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_MASK                     0x00800000
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_SHIFT                    23
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00400000
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           22
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0
+
+/* AON_PM_L2 :: PCI_CLEAR :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_MASK                         0x00200000
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_SHIFT                        21
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_MASK                         0x00100000
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_SHIFT                        20
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_MASK                         0x00080000
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_SHIFT                        19
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_MASK                      0x00040000
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT                     18
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_CLEAR :: FTM [17:17] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_MASK                          0x00020000
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_SHIFT                         17
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_DEFAULT                       0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_AFEC_MASK                    0x00010000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_AFEC_SHIFT                   16
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_AFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_TFEC_MASK                    0x00008000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_TFEC_SHIFT                   15
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_TFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_RCVR_1_MASK                  0x00004000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_RCVR_1_SHIFT                 14
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_RCVR_1_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_RCVR_0_MASK                  0x00002000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_RCVR_0_SHIFT                 13
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_RCVR_0_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_MASK                    0x00001000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_SHIFT                   12
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_MASK                    0x00000800
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_SHIFT                   11
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_MASK                  0x00000400
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_SHIFT                 10
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_MASK                  0x00000200
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_SHIFT                 9
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_MASK                     0x00000100
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_SHIFT                    8
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_MOCA_MASK                     0x00000080
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_MOCA_SHIFT                    7
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_MOCA_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_UHFR_MASK                         0x00000040
+#define BCHP_AON_PM_L2_PCI_CLEAR_UHFR_SHIFT                        6
+#define BCHP_AON_PM_L2_PCI_CLEAR_UHFR_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_DEFAULT                  0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_MASK              0xfe000000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT             25
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x01000000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  24
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_MASK               0x00800000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_SHIFT              23
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00400000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     22
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_MASK                   0x00200000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_SHIFT                  21
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_MASK                   0x00100000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_SHIFT                  20
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_MASK                   0x00080000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_SHIFT                  19
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK                0x00040000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT               18
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FTM [17:17] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_MASK                    0x00020000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_SHIFT                   17
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_AFEC_MASK              0x00010000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_AFEC_SHIFT             16
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_AFEC_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_TFEC_MASK              0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_TFEC_SHIFT             15
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_TFEC_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_RCVR_1_MASK            0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_RCVR_1_SHIFT           14
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_RCVR_1_DEFAULT         1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_RCVR_0_MASK            0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_RCVR_0_SHIFT           13
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_RCVR_0_DEFAULT         1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_MASK              0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_SHIFT             12
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_MASK              0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_SHIFT             11
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_MASK            0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_SHIFT           10
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_DEFAULT         1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_MASK            0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_SHIFT           9
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_DEFAULT         1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_MASK               0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_SHIFT              8
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_MOCA_MASK               0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_MOCA_SHIFT              7
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_MOCA_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_UHFR_MASK                   0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_UHFR_SHIFT                  6
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_UHFR_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_DEFAULT            1
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_SET :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_MASK                 0xfe000000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_SHIFT                25
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x01000000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     24
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_MASK                  0x00800000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_SHIFT                 23
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00400000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        22
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_MASK                      0x00200000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_SHIFT                     21
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_MASK                      0x00100000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_SHIFT                     20
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_MASK                      0x00080000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_SHIFT                     19
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_MASK                   0x00040000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT                  18
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FTM [17:17] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_MASK                       0x00020000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_SHIFT                      17
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_DEFAULT                    1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_AFEC_MASK                 0x00010000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_AFEC_SHIFT                16
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_AFEC_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_TFEC_MASK                 0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_TFEC_SHIFT                15
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_TFEC_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_RCVR_1_MASK               0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_RCVR_1_SHIFT              14
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_RCVR_1_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_RCVR_0_MASK               0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_RCVR_0_SHIFT              13
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_RCVR_0_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_MASK                 0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_SHIFT                12
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_MASK                 0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_SHIFT                11
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_MASK               0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_SHIFT              10
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_MASK               0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_SHIFT              9
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_MASK                  0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_SHIFT                 8
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_MOCA_MASK                  0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_MOCA_SHIFT                 7
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_MOCA_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_UHFR_MASK                      0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_SET_UHFR_SHIFT                     6
+#define BCHP_AON_PM_L2_PCI_MASK_SET_UHFR_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_DEFAULT               1
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_MASK               0xfe000000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT              25
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x01000000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   24
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_MASK                0x00800000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_SHIFT               23
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00400000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      22
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_MASK                    0x00200000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_SHIFT                   21
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_MASK                    0x00100000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_SHIFT                   20
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_MASK                    0x00080000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_SHIFT                   19
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK                 0x00040000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT                18
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FTM [17:17] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_MASK                     0x00020000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_SHIFT                    17
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_DEFAULT                  1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_AFEC_MASK               0x00010000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_AFEC_SHIFT              16
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_AFEC_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_TFEC_MASK               0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_TFEC_SHIFT              15
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_TFEC_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_RCVR_1_MASK             0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_RCVR_1_SHIFT            14
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_RCVR_1_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_RCVR_0_MASK             0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_RCVR_0_SHIFT            13
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_RCVR_0_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_MASK               0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_SHIFT              12
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_MASK               0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_SHIFT              11
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_MASK             0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_SHIFT            10
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_MASK             0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_SHIFT            9
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_MASK                0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_SHIFT               8
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_MASK                0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_SHIFT               7
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_UHFR_MASK                    0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_UHFR_SHIFT                   6
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_UHFR_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_DEFAULT             1
+
+#endif /* #ifndef BCHP_AON_PM_L2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_bspi.h b/include/linux/brcmstb/7346b0/bchp_bspi.h
new file mode 100644
index 0000000..7de2788
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_bspi.h
@@ -0,0 +1,446 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:28:30 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_bspi.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 3:00p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_H__
+#define BCHP_BSPI_H__
+
+/***************************************************************************
+ *BSPI - Public BSPI Control Registers
+ ***************************************************************************/
+#define BCHP_BSPI_REVISION_ID                    0x00413000 /* Revision ID */
+#define BCHP_BSPI_SCRATCH                        0x00413004 /* Revision ID */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL               0x00413008 /* Master/Boot SPI Control Register */
+#define BCHP_BSPI_BUSY_STATUS                    0x0041300c /* BSPI Busy Status Register */
+#define BCHP_BSPI_INTR_STATUS                    0x00413010 /* Interrupt Status Register */
+#define BCHP_BSPI_B0_STATUS                      0x00413014 /* Prefetch Buffer 0 Status Register */
+#define BCHP_BSPI_B0_CTRL                        0x00413018 /* Prefetch Buffer 0 Control Register */
+#define BCHP_BSPI_B1_STATUS                      0x0041301c /* Prefetch Buffer 1 Status Register */
+#define BCHP_BSPI_B1_CTRL                        0x00413020 /* Prefetch Buffer 1 Control Register */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL            0x00413024 /* Dual/Single Receive Mode Control Register */
+#define BCHP_BSPI_FLEX_MODE_ENABLE               0x00413028 /* Flexible Control Mode Enable Register */
+#define BCHP_BSPI_BITS_PER_CYCLE                 0x0041302c /* Bits per cycle "b-p-c" Control Register */
+#define BCHP_BSPI_BITS_PER_PHASE                 0x00413030 /* Bits per Phase "b-p-p" Control Register */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE              0x00413034 /* Command and Mode Data Register */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE     0x00413038 /* Bspi FLash upper address byte register */
+#define BCHP_BSPI_BSPI_XOR_VALUE                 0x0041303c /* BSPI FLASH XOR Value Register */
+#define BCHP_BSPI_BSPI_XOR_ENABLE                0x00413040 /* BSPI FLASH XOR Enable Register */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE           0x00413044 /* BSPI Pin  Programmed IO Mode Enable Register */
+#define BCHP_BSPI_BSPI_PIO_IODIR                 0x00413048 /* BSPI Pin  Programmed IO Mode Direction Register */
+#define BCHP_BSPI_BSPI_PIO_DATA                  0x0041304c /* BSPI Pin  Programmed IO Mode Data Register */
+
+/***************************************************************************
+ *REVISION_ID - Revision ID
+ ***************************************************************************/
+/* BSPI :: REVISION_ID :: reserved0 [31:16] */
+#define BCHP_BSPI_REVISION_ID_reserved0_MASK                       0xffff0000
+#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT                      16
+
+/* BSPI :: REVISION_ID :: MAJOR [15:08] */
+#define BCHP_BSPI_REVISION_ID_MAJOR_MASK                           0x0000ff00
+#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT                          8
+#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT                        4
+
+/* BSPI :: REVISION_ID :: MINOR [07:00] */
+#define BCHP_BSPI_REVISION_ID_MINOR_MASK                           0x000000ff
+#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT                          0
+#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT                        0
+
+/***************************************************************************
+ *SCRATCH - Revision ID
+ ***************************************************************************/
+/* BSPI :: SCRATCH :: SCRATCH [31:00] */
+#define BCHP_BSPI_SCRATCH_SCRATCH_MASK                             0xffffffff
+#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT                            0
+#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT                          0
+
+/***************************************************************************
+ *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
+ ***************************************************************************/
+/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT                 1
+
+/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK                0x00000001
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT               0
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT             0
+
+/***************************************************************************
+ *BUSY_STATUS - BSPI Busy Status Register
+ ***************************************************************************/
+/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
+#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK                       0xfffffffe
+#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT                      1
+
+/* BSPI :: BUSY_STATUS :: busy [00:00] */
+#define BCHP_BSPI_BUSY_STATUS_busy_MASK                            0x00000001
+#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT                           0
+#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT                         0
+
+/***************************************************************************
+ *INTR_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
+#define BCHP_BSPI_INTR_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT                      2
+
+/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
+#define BCHP_BSPI_INTR_STATUS_intr_1_MASK                          0x00000002
+#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT                         1
+#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT                       0
+
+/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
+#define BCHP_BSPI_INTR_STATUS_intr_0_MASK                          0x00000001
+#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT                         0
+#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT                       0
+
+/***************************************************************************
+ *B0_STATUS - Prefetch Buffer 0 Status Register
+ ***************************************************************************/
+/* BSPI :: B0_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B0_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT             0
+
+/* BSPI :: B0_STATUS :: b0_full [29:29] */
+#define BCHP_BSPI_B0_STATUS_b0_full_MASK                           0x20000000
+#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT                          29
+#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT                        0
+
+/* BSPI :: B0_STATUS :: b0_empty [28:28] */
+#define BCHP_BSPI_B0_STATUS_b0_empty_MASK                          0x10000000
+#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT                         28
+#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT                       1
+
+/* BSPI :: B0_STATUS :: b0_miss [27:27] */
+#define BCHP_BSPI_B0_STATUS_b0_miss_MASK                           0x08000000
+#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT                          27
+#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT                        0
+
+/* BSPI :: B0_STATUS :: b0_hit [26:26] */
+#define BCHP_BSPI_B0_STATUS_b0_hit_MASK                            0x04000000
+#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT                           26
+#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT                         0
+
+/* BSPI :: B0_STATUS :: b0_address [25:00] */
+#define BCHP_BSPI_B0_STATUS_b0_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT                       0
+#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT                     0
+
+/***************************************************************************
+ *B0_CTRL - Prefetch Buffer 0 Control Register
+ ***************************************************************************/
+/* BSPI :: B0_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B0_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B0_CTRL :: b0_flush [00:00] */
+#define BCHP_BSPI_B0_CTRL_b0_flush_MASK                            0x00000001
+#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT                           0
+#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT                         0
+
+/***************************************************************************
+ *B1_STATUS - Prefetch Buffer 1 Status Register
+ ***************************************************************************/
+/* BSPI :: B1_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B1_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT             0
+
+/* BSPI :: B1_STATUS :: b1_full [29:29] */
+#define BCHP_BSPI_B1_STATUS_b1_full_MASK                           0x20000000
+#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT                          29
+#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT                        0
+
+/* BSPI :: B1_STATUS :: b1_empty [28:28] */
+#define BCHP_BSPI_B1_STATUS_b1_empty_MASK                          0x10000000
+#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT                         28
+#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT                       1
+
+/* BSPI :: B1_STATUS :: b1_miss [27:27] */
+#define BCHP_BSPI_B1_STATUS_b1_miss_MASK                           0x08000000
+#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT                          27
+#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT                        0
+
+/* BSPI :: B1_STATUS :: b1_hit [26:26] */
+#define BCHP_BSPI_B1_STATUS_b1_hit_MASK                            0x04000000
+#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT                           26
+#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT                         0
+
+/* BSPI :: B1_STATUS :: b1_address [25:00] */
+#define BCHP_BSPI_B1_STATUS_b1_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT                       0
+#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT                     0
+
+/***************************************************************************
+ *B1_CTRL - Prefetch Buffer 1 Control Register
+ ***************************************************************************/
+/* BSPI :: B1_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B1_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B1_CTRL :: b1_flush [00:00] */
+#define BCHP_BSPI_B1_CTRL_b1_flush_MASK                            0x00000001
+#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT                           0
+#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT                         0
+
+/***************************************************************************
+ *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
+ ***************************************************************************/
+/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK               0xffffffe0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT              5
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK             0x00000010
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT            4
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT          0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK               0x00000008
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT              3
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT            0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK      0x00000004
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT     2
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT   0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK         0x00000002
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT        1
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT      0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK                0x00000001
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT               0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT             0
+
+/***************************************************************************
+ *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT                 1
+
+/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK      0x00000001
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT     0
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT   0
+
+/***************************************************************************
+ *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK                    0xfc000000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT                   26
+
+/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK               0x03000000
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT            0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK                    0x00fc0000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT                   18
+
+/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK              0x00030000
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK                    0x0000fc00
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT                   10
+
+/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK              0x00000300
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT             8
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK                    0x000000fc
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT                   2
+
+/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK              0x00000003
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT             0
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT           0
+
+/***************************************************************************
+ *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK                    0xfe000000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT                   25
+
+/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK               0x01000000
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT            0
+
+/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK                    0x00fe0000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT                   17
+
+/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK              0x00010000
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK                    0x0000fe00
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT                   9
+
+/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK                     0x00000100
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT                    8
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT                  0
+
+/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK                 0x000000ff
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT                0
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT              8
+
+/***************************************************************************
+ *CMD_AND_MODE_BYTE - Command and Mode Data Register
+ ***************************************************************************/
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK                 0xff000000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT                24
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK            0x00ff0000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT           16
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT         0
+
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK                 0x0000ff00
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT                8
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK             0x000000ff
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT            0
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT          11
+
+/***************************************************************************
+ *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
+ ***************************************************************************/
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0
+
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK        0x00ffffff
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT       0
+
+/***************************************************************************
+ *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK               0xfff00000
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT              20
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT            0
+
+/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK                    0x000fffff
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT                  1
+
+/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK             0x00000001
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT            0
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT          0
+
+/***************************************************************************
+ *BSPI_PIO_MODE_ENABLE - BSPI Pin  Programmed IO Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK              0xfffffffe
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT             1
+
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK          0x00000001
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT         0
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT       0
+
+/***************************************************************************
+ *BSPI_PIO_IODIR - BSPI Pin  Programmed IO Mode Direction Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK                    0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT                   3
+
+/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT              3
+
+/***************************************************************************
+ *BSPI_PIO_DATA - BSPI Pin  Programmed IO Mode Data Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK                     0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT                    3
+
+/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT              0
+
+#endif /* #ifndef BCHP_BSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_bspi_raf.h b/include/linux/brcmstb/7346b0/bchp_bspi_raf.h
new file mode 100644
index 0000000..30c2244
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_bspi_raf.h
@@ -0,0 +1,163 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:36:17 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_bspi_raf.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 3:00p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_RAF_H__
+#define BCHP_BSPI_RAF_H__
+
+/***************************************************************************
+ *BSPI_RAF - Public Linear Read BSPI Pipe Registers
+ ***************************************************************************/
+#define BCHP_BSPI_RAF_START_ADDR                 0x00413100 /* Physical Starting Address Location in Flash device */
+#define BCHP_BSPI_RAF_NUM_WORDS                  0x00413104 /* Number of Words to be fetched */
+#define BCHP_BSPI_RAF_CTRL                       0x00413108 /* RAF Session Control Register */
+#define BCHP_BSPI_RAF_FULLNESS                   0x0041310c /* Fullness indicator for the read ahead buffer */
+#define BCHP_BSPI_RAF_WATERMARK                  0x00413110 /* Watermark level in the read ahead buffer that triggers an interrupt */
+#define BCHP_BSPI_RAF_STATUS                     0x00413114 /* Linear Read Status Register */
+#define BCHP_BSPI_RAF_READ_DATA                  0x00413118 /* Read data from Raf-buffer */
+#define BCHP_BSPI_RAF_WORD_CNT                   0x0041311c /* Current number of words fetched from Flash */
+#define BCHP_BSPI_RAF_CURR_ADDR                  0x00413120 /* Current read address for the linear read session */
+
+/***************************************************************************
+ *START_ADDR - Physical Starting Address Location in Flash device
+ ***************************************************************************/
+/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK                   0xffffffff
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT                  0
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT                0
+
+/***************************************************************************
+ *NUM_WORDS - Number of Words to be fetched
+ ***************************************************************************/
+/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK                      0xffffffff
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT                     0
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT                   0
+
+/***************************************************************************
+ *CTRL - RAF Session Control Register
+ ***************************************************************************/
+/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT                         2
+
+/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
+#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK                              0x00000002
+#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT                             1
+#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT                           0
+
+/* BSPI_RAF :: CTRL :: START [00:00] */
+#define BCHP_BSPI_RAF_CTRL_START_MASK                              0x00000001
+#define BCHP_BSPI_RAF_CTRL_START_SHIFT                             0
+#define BCHP_BSPI_RAF_CTRL_START_DEFAULT                           0
+
+/***************************************************************************
+ *FULLNESS - Fullness indicator for the read ahead buffer
+ ***************************************************************************/
+/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK                      0xffffff80
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT                     7
+
+/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK                       0x0000007f
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT                      0
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT                    0
+
+/***************************************************************************
+ *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
+ ***************************************************************************/
+/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK                     0xfffffffc
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT                    2
+
+/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK            0x00000003
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT           0
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT         0
+
+/***************************************************************************
+ *STATUS - Linear Read Status Register
+ ***************************************************************************/
+/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
+#define BCHP_BSPI_RAF_STATUS_reserved0_MASK                        0xfffffff8
+#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT                       3
+
+/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK                        0x00000004
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT                       2
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT                     0
+
+/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK                       0x00000002
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT                      1
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT                    1
+
+/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK                     0x00000001
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT                    0
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT                  0
+
+/***************************************************************************
+ *READ_DATA - Read data from Raf-buffer
+ ***************************************************************************/
+/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
+#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK                          0xffffffff
+#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT                         0
+#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT                       0
+
+/***************************************************************************
+ *WORD_CNT - Current number of words fetched from Flash
+ ***************************************************************************/
+/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK             0xffffffff
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT            0
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *CURR_ADDR - Current read address for the linear read session
+ ***************************************************************************/
+/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK               0xffffffff
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT              0
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT            0
+
+#endif /* #ifndef BCHP_BSPI_RAF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_clkgen.h b/include/linux/brcmstb/7346b0/bchp_clkgen.h
new file mode 100644
index 0000000..f5fdf2c
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_clkgen.h
@@ -0,0 +1,6147 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 31 16:33:38 2011
+ *                 MD5 Checksum         0b9cc5de2a03cabbf9a0a767bc10763a
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_clkgen.h $
+ * 
+ * Hydra_Software_Devel/3   5/31/11 5:25p albertl
+ * SW7346-143: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_CLKGEN_H__
+#define BCHP_CLKGEN_H__
+
+/***************************************************************************
+ *CLKGEN - clkgen registers
+ ***************************************************************************/
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN           0x00420000 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL         0x00420004 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV             0x00420008 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 0x0042000c /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN            0x00420010 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x00420014 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x00420018 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC            0x0042001c /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2           0x00420020 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS     0x00420024 /* Lock Status */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS          0x00420028 /* Test Status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET            0x0042002c /* Resets */
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN            0x00420030 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL          0x00420034 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV              0x00420038 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0 0x0042003c /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1 0x00420040 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2 0x00420044 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN             0x00420048 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW 0x0042004c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH 0x00420050 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC             0x00420054 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS      0x00420058 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS           0x0042005c /* Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET         0x00420060 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN         0x00420064 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL       0x00420068 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV           0x0042006c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN          0x00420070 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x00420074 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x00420078 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS   0x0042007c /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS        0x00420080 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET           0x00420084 /* Resets */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN           0x00420088 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL         0x0042008c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV             0x00420090 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 0x00420094 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 0x00420098 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 0x0042009c /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 0x004200a0 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN            0x004200a4 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW 0x004200a8 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH 0x004200ac /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC            0x004200b0 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2           0x004200b4 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS     0x004200b8 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS          0x004200bc /* Test Status */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET           0x004200c0 /* Resets */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN           0x004200c4 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL         0x004200c8 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV             0x004200cc /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 0x004200d0 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 0x004200d4 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 0x004200d8 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 0x004200dc /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 0x004200e0 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 0x004200e4 /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN            0x004200e8 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW 0x004200ec /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH 0x004200f0 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC            0x004200f4 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2           0x004200f8 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS     0x004200fc /* Lock Status */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS          0x00420100 /* Test Status */
+#define BCHP_CLKGEN_SCRATCH5                     0x00420104 /* clkgen  Scratch register */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL         0x00420108 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_SCRATCH3                     0x0042010c /* clkgen  Scratch register */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x00420110 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x00420114 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x00420118 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x0042011c /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x00420120 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x00420124 /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN            0x00420128 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x0042012c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x00420130 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC            0x00420134 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2           0x00420138 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS     0x0042013c /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS          0x00420140 /* Test Status */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET          0x00420144 /* Resets */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN          0x00420148 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL        0x0042014c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV            0x00420150 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 0x00420154 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN           0x0042015c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW 0x00420160 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH 0x00420164 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC           0x00420168 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS    0x0042016c /* Lock Status */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS         0x00420170 /* Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET             0x00420174 /* Resets */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN             0x00420178 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL           0x0042017c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV               0x00420180 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0 0x00420184 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1 0x00420188 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2 0x0042018c /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN              0x00420190 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW 0x00420194 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH 0x00420198 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC              0x0042019c /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS       0x004201a0 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS            0x004201a4 /* Test Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET           0x004201a8 /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN           0x004201ac /* Powerdowns */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL         0x004201b0 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV             0x004201b4 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC            0x004201b8 /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 0x004201bc /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 0x004201c0 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 0x004201c4 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 0x004201c8 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN            0x004201cc /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW 0x004201d0 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH 0x004201d4 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC            0x004201d8 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS     0x004201dc /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS          0x004201e0 /* Test Status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET         0x004201e4 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN         0x004201e8 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL       0x004201ec /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV           0x004201f0 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN          0x004201f4 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x004201f8 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x004201fc /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS   0x00420200 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS        0x00420204 /* Test Status */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE       0x00420208 /* Disable HIF_INST's clocks */
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE 0x0042020c /* Memsys 32 inst memory standby enable */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE  0x00420210 /* Disable SDS0_TOP_INST's clocks */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK      0x00420214 /* Usb1 inst observe clock */
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE    0x00420218 /* Ftm top inst clock enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE 0x0042021c /* Disable VEC_AIO_TOP_INST's clocks */
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE 0x00420220 /* Usb0 inst memory standby enable */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE   0x00420224 /* Graphics inst clock enable */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL       0x00420228 /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE 0x0042022c /* Disable DUAL_GENET_TOP_DUAL_RGMII_INST's clocks */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE  0x00420230 /* Disable SYS_CTRL_INST's clocks */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE 0x00420234 /* Sds0 afec top inst memory standby enable */
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION  0x00420238 /* Select observation clk */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE  0x0042023c /* Memsys 32 inst clock enable */
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE 0x00420240 /* Usb1 inst memory standby enable */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA 0x00420244 /* Sectop inst clock enable */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE            0x00420248 /* Disable PAD's clocks */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE  0x0042024c /* Disable UHFR_TOP_INST's clocks */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT          0x00420250 /* Mux selects for Internal clocks */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE    0x00420254 /* Disable DVP_HT_INST's clocks */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK      0x00420258 /* Usb0 inst observe clock */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE      0x0042025c /* Disable USB0_INST's clocks */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE  0x00420260 /* Disable CORE_XPT_INST's clocks */
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE 0x00420264 /* Dvp ht inst memory standby enable */
+#define BCHP_CLKGEN_PAD_MUX_SELECT               0x00420268 /* Mux selects for Pad clocks */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK   0x0042026c /* Sys aon inst observe clock */
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY 0x00420270 /* Uhfr top inst power switch memory */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A 0x00420274 /* Dual genet top dual rgmii inst power switch memory a */
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY 0x00420278 /* Usb0 inst power switch memory */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT         0x0042027c /* Mux selects for Smartcard clocks */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE      0x00420280 /* Disable USB1_INST's clocks */
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_DISABLE  0x00420284 /* Disable SDS1_TOP_INST's clocks */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE  0x00420288 /* Disable GRAPHICS_INST's clocks */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_CLOCK_ENABLE 0x0042028c /* Sds1 afec top inst clock enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO 0x00420290 /* Vec aio top inst clock enable aio */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK 0x00420294 /* Sds0 afec top inst observe clock */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO 0x00420298 /* Vec aio top inst memory standby enable aio */
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY 0x0042029c /* Dvp ht inst power switch memory */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A 0x004202a0 /* Dual genet top dual rgmii inst memory standby enable a */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE     0x004202a4 /* Dvp ht inst clock enable */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK 0x004202a8 /* Memsys 32 inst observe clock */
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT 0x004202ac /* Memsys 32 inst power management */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE   0x004202b0 /* Core xpt inst clock enable */
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE 0x004202b4 /* Core xpt inst memory standby enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK 0x004202b8 /* Vec aio top inst observe clock */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE 0x004202bc /* Graphics inst memory standby enable */
+#define BCHP_CLKGEN_SCRATCH7                     0x004202c0 /* clkgen  Scratch register */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK  0x004202c4 /* Uhfr top inst observe clock */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK    0x004202c8 /* Dvp ht inst observe clock */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT 0x004202cc /* Dual genet top dual rgmii inst clock select */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2          0x004202d0 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_FTM_TOP_INST_MEMORY_STANDBY_ENABLE 0x004202d4 /* Ftm top inst memory standby enable */
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE 0x004202d8 /* Uhfr top inst memory standby enable */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE 0x004202dc /* Sds1 afec top inst memory standby enable */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE  0x004202e0 /* Disable ZCPU_TOP_INST's clocks */
+#define BCHP_CLKGEN_SCRATCH6                     0x004202e4 /* clkgen  Scratch register */
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK 0x004202e8 /* Sds1 receiver inst observe clock */
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK 0x004202ec /* Sds1 tfec top inst observe clock */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE 0x004202f0 /* Vec aio top inst clock enable */
+#define BCHP_CLKGEN_FTM_TOP_INST_POWER_SWITCH_MEMORY 0x004202f4 /* Ftm top inst power switch memory */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC 0x004202f8 /* Vec aio top inst memory standby enable vec */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE 0x004202fc /* Sds0 afec top inst clock enable */
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK 0x00420300 /* Sds0 receiver inst observe clock */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO 0x00420304 /* Vec aio top inst power switch memory aio */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY 0x00420308 /* Raaga dsp top inst power switch memory */
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE 0x0042030c /* Moca top inst memory standby enable */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION   0x00420310 /* Select observation clk */
+#define BCHP_CLKGEN_SVD_TOP_INST_MEMORY_STANDBY_ENABLE 0x00420314 /* Svd top inst memory standby enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK 0x00420318 /* Raaga Dsp top inst observe clock */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE 0x0042031c /* Raaga dsp top inst clock enable */
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE 0x00420320 /* Bvn top inst memory standby enable */
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY 0x00420324 /* Bvn top inst power switch memory */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT  0x00420328 /* Sata3 top inst clock select */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC 0x0042032c /* Vec aio top inst power switch memory vec */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK 0x00420330 /* Sds1 afec top inst observe clock */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE   0x00420334 /* Sds0  top inst clock enable */
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY 0x00420338 /* Usb1 inst power switch memory */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE       0x0042033c /* Usb0 inst clock enable */
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE 0x00420340 /* Sata3 top inst memory standby enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC 0x00420344 /* Vec aio top inst clock enable vec */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK  0x00420348 /* Moca top inst observe clock */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION        0x0042034c /* Select observation clk */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK    0x00420350 /* Sectop inst observe clock */
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY 0x00420354 /* Memsys 32 inst power switch memory */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY 0x00420358 /* Graphics inst power switch memory */
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK 0x0042035c /* Sds0 tfec top inst observe clock */
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY 0x00420360 /* Sata3 top inst power switch memory */
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE    0x00420364 /* Svd top inst clock enable */
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY 0x00420368 /* Hif inst power switch memory */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE  0x0042036c /* Sata3 top inst clock enable */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK  0x00420370 /* Core xpt inst observe clock */
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE 0x00420374 /* Hif inst memory standby enable */
+#define BCHP_CLKGEN_SCRATCH8                     0x00420378 /* clkgen  Scratch register */
+#define BCHP_CLKGEN_SVD_TOP_INST_POWER_SWITCH_MEMORY 0x0042037c /* Svd top inst power switch memory */
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_ENABLE   0x00420380 /* Sds1 top inst clock enable */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE   0x00420384 /* Uhfr top inst clock enable */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY 0x00420388 /* Sds1 afec top inst power switch memory */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE       0x0042038c /* Usb1 inst clock enable */
+#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE     0x00420390 /* Disable SATA3_TOP_INST's clocks */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK 0x00420394 /* Sata3 top inst observe clock */
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE 0x00420398 /* Sys ctrl inst memory standby enable */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK 0x0042039c /* Dual genet top dual rgmii inst observe clock */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE 0x004203a0 /* Dual genet top dual rgmii inst clock enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE 0x004203a4 /* Raaga dsp top inst memory standby enable */
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY 0x004203a8 /* Core xpt inst power switch memory */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION       0x004203ac /* Select observation clk */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK  0x004203b0 /* Zcpu top inst observe clock */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK  0x004203b4 /* Graphics inst observe clock */
+#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE 0x004203b8 /* Disable GRAPHICS_INST's m2mc clock */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL       0x004203bc /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY 0x004203c0 /* Sds0 afec top inst power switch memory */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK  0x004203c4 /* Sys ctrl inst observe clock */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE    0x004203c8 /* Bvn top inst clock enable */
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY 0x004203cc /* Sys ctrl inst power switch memory */
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY 0x004203d0 /* Moca top inst power switch memory */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE   0x004203d4 /* Moca top inst clock enable */
+#define BCHP_CLKGEN_SCRATCH4                     0x004203d8 /* clkgen  Scratch register */
+#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS      0x004203dc /* Lock Status */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x004203e0 /* pll alive in standby mode */
+#define BCHP_CLKGEN_SPI_CLOCK_SELECT             0x004203e4 /* spi clock control */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS 0x004203e8 /* Bypass DUAL_GENET_TOP_DUAL_RGMII_INST clocks */
+#define BCHP_CLKGEN_SCRATCH2                     0x004203ec /* clkgen  Scratch register */
+#define BCHP_CLKGEN_GRAPHICS_INST_V3D_CLOCK_ENABLE 0x004203f0 /* Graphics inst V3D clock enable */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL                0x004203f4 /* Mips PLL Control Register */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS    0x004203f8 /* Resets status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS  0x004203fc /* Resets status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS  0x00420400 /* Resets status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS     0x00420404 /* Resets status */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS    0x00420408 /* Resets status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS    0x0042040c /* Resets status */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS   0x00420410 /* Resets status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS    0x00420414 /* Resets status */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS      0x00420418 /* Resets status */
+#define BCHP_CLKGEN_TESTPORT                     0x0042041c /* Special Testport Controls */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET           0x00420428 /* Resets */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_PWRDN           0x0042042c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CONTROL         0x00420430 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_DIV             0x00420434 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 0x00420438 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 0x0042043c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 0x00420440 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN            0x00420444 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW 0x00420448 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH 0x0042044c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC            0x00420450 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_LOCK_STATUS     0x00420454 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_STATUS          0x00420458 /* Status */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS    0x0042045c /* Resets status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2            0x00420460 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL        0x00420464 /* Clock Monitor Control */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT      0x00420468 /* Clock Monitor Max Reference Count */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER    0x0042046c /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE       0x00420470 /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER   0x00420474 /* Clock Monitor View Counter */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP           0x00420478 /* Power management LDO PLL */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM        0x0042047c /* Power management LDO PLL state machine */
+
+/***************************************************************************
+ *PLL_MIPS_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MIPS_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_MIPS_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_SHIFT               3
+
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_MASK                     0x00000007
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_SHIFT                    0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_DEFAULT                  3
+
+/***************************************************************************
+ *PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:06] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 6
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 6
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000007
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2
+
+/***************************************************************************
+ *PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: LDO_REF_SEL [30:30] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_MASK             0x40000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT            30
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: POR_BYPASS [29:29] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_MASK              0x20000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_SHIFT             29
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_DEFAULT           0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: NDIV_RELOCK [28:28] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_MASK             0x10000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT            28
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: FAST_LOCK [27:27] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_MASK               0x08000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_SHIFT              27
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_DEFAULT              0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: VCO_DLY [25:24] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_MASK                 0x03000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_SHIFT                24
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: PWM_RATE [23:22] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_MASK                0x00c00000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_SHIFT               22
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_DEFAULT             0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_MODE [21:20] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_MASK               0x00300000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_SHIFT              20
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_MASK                0x00080000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_SHIFT               19
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_MASK             0x00020000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_SHIFT            17
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_MASK             0x0001c000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_SHIFT            14
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__MASK             0x00002000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__SHIFT            13
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_DEFAULT               0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_MASK             0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT            1
+
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_AVD_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_MASK               0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_SHIFT              2
+
+/* CLKGEN :: PLL_AVD_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_MASK                  0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_SHIFT                 1
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_DEFAULT               0
+
+/* CLKGEN :: PLL_AVD_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_SHIFT                 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_DEFAULT               0
+
+/***************************************************************************
+ *PLL_AVD_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_AVD_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_SHIFT              0
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_AVD_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_SHIFT              0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AVD_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_MASK                 0xffffe000
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_SHIFT                13
+
+/* CLKGEN :: PLL_AVD_PLL_DIV :: NDIV_INT [12:03] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_MASK                  0x00001ff8
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_SHIFT                 3
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_DEFAULT               142
+
+/* CLKGEN :: PLL_AVD_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_MASK                      0x00000007
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_SHIFT                     0
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_DEFAULT                   3
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x00003fc0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   6
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 6
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK    0x00003fc0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT   6
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 8
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK    0x00003fc0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT   6
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 100
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_MASK                0xff000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_SHIFT               24
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 6
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x00000007
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       0
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     2
+
+/***************************************************************************
+ *PLL_AVD_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_reserved0_MASK                0x80000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_reserved0_SHIFT               31
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: LDO_REF_SEL [30:30] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_MASK              0x40000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_SHIFT             30
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: POR_BYPASS [29:29] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_MASK               0x20000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_SHIFT              29
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_DEFAULT            0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: NDIV_RELOCK [28:28] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_MASK              0x10000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_SHIFT             28
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: FAST_LOCK [27:27] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_MASK                0x08000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_SHIFT               27
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_DEFAULT             0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_MASK                  0x04000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_SHIFT                 26
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_DEFAULT               0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: VCO_DLY [25:24] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_MASK                  0x03000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_SHIFT                 24
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_DEFAULT               0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: PWM_RATE [23:22] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_MASK                 0x00c00000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_SHIFT                22
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_DEFAULT              0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_MODE [21:20] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_MASK                0x00300000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_SHIFT               20
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_DEFAULT             0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_MASK                 0x00080000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_SHIFT                19
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_DEFAULT              0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_MASK                0x00040000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_SHIFT               18
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_DEFAULT             0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_SHIFT             17
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_MASK              0x0001c000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_SHIFT             14
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__MASK              0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__SHIFT             13
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00001000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  12
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         0
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0
+
+/***************************************************************************
+ *PLL_AVD_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_MASK              0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_SHIFT             1
+
+/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_MASK         0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_SHIFT        0
+
+/***************************************************************************
+ *PLL_AVD_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_MASK              0xfffff000
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_SHIFT             12
+
+/* CLKGEN :: PLL_AVD_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_SHIFT           0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT            0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT                1
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  1
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: NDIV_INT [12:03] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_MASK                 0x00001ff8
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_SHIFT                3
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_DEFAULT              125
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_MASK                     0x00000007
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_SHIFT                    0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_DEFAULT                  3
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  6
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 9
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  6
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 18
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  6
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 9
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [13:06] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  6
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 90
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 6
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000007
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: LDO_REF_SEL [30:30] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_LDO_REF_SEL_MASK             0x40000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_LDO_REF_SEL_SHIFT            30
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_LDO_REF_SEL_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: POR_BYPASS [29:29] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_POR_BYPASS_MASK              0x20000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_POR_BYPASS_SHIFT             29
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_POR_BYPASS_DEFAULT           0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: NDIV_RELOCK [28:28] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_NDIV_RELOCK_MASK             0x10000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_NDIV_RELOCK_SHIFT            28
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_NDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: FAST_LOCK [27:27] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_MASK               0x08000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_SHIFT              27
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCO_DLY [25:24] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_MASK                 0x03000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_SHIFT                24
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: PWM_RATE [23:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_MASK                0x00c00000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_SHIFT               22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_DEFAULT             0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_MODE [21:20] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_MASK               0x00300000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_SHIFT              20
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_MASK                0x00080000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_SHIFT               19
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_MASK             0x00020000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_SHIFT            17
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_MASK             0x0001c000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_SHIFT            14
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__MASK             0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__SHIFT            13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2_SPARE_DEFAULT               0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: LOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_MASK             0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_SHIFT            1
+
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: LOCK_LOST [11:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_LOCK_LOST_MASK             0x00000fff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_LOCK_LOST_SHIFT            0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MOCA_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_MOCA_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: NDIV_INT [12:03] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_MASK                 0x00001ff8
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_SHIFT                3
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_DEFAULT              200
+
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_MASK                     0x00000007
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_SHIFT                    0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_DEFAULT                  3
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  6
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 9
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  6
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 16
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  6
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 36
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [13:06] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  6
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 72
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [05:05] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 5
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [04:04] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 4
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [03:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [13:06] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  6
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 9
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [05:05] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 5
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [04:04] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 4
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [03:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [13:06] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  6
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 36
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [05:05] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 5
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [04:04] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 4
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [03:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 3
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000007
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2
+
+/***************************************************************************
+ *PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: LDO_REF_SEL [30:30] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_MASK             0x40000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_SHIFT            30
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_DEFAULT          0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: POR_BYPASS [29:29] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_MASK              0x20000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_SHIFT             29
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_DEFAULT           0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: NDIV_RELOCK [28:28] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_MASK             0x10000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_SHIFT            28
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: FAST_LOCK [27:27] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_MASK               0x08000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_SHIFT              27
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_DEFAULT              1
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_DLY [25:24] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_MASK                 0x03000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_SHIFT                24
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: PWM_RATE [23:22] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_MASK                0x00c00000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_SHIFT               22
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_DEFAULT             2
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_MODE [21:20] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_MASK               0x00300000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_SHIFT              20
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_MASK                0x00080000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_SHIFT               19
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_MASK             0x00020000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_SHIFT            17
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_MASK             0x0001c000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_SHIFT            14
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__MASK             0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__SHIFT            13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_DEFAULT               0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_MASK             0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_SHIFT            1
+
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_MOCA_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *SCRATCH5 - clkgen  Scratch register
+ ***************************************************************************/
+/* CLKGEN :: SCRATCH5 :: VALUE [31:00] */
+#define BCHP_CLKGEN_SCRATCH5_VALUE_MASK                            0xffffffff
+#define BCHP_CLKGEN_SCRATCH5_VALUE_SHIFT                           0
+#define BCHP_CLKGEN_SCRATCH5_VALUE_DEFAULT                         0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *SCRATCH3 - clkgen  Scratch register
+ ***************************************************************************/
+/* CLKGEN :: SCRATCH3 :: VALUE [31:00] */
+#define BCHP_CLKGEN_SCRATCH3_VALUE_MASK                            0xffffffff
+#define BCHP_CLKGEN_SCRATCH3_VALUE_SHIFT                           0
+#define BCHP_CLKGEN_SCRATCH3_VALUE_DEFAULT                         0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffffe0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 5
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [03:03] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000008
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 3
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [02:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000007
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:06] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 6
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  6
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 48
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [13:06] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  6
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [13:06] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  6
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 10
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [13:06] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  6
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 144
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 9
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 4
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000007
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [30:30] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK             0x40000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT            30
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [29:29] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK              0x20000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT             29
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT           0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [28:28] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK             0x10000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT            28
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [27:27] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK               0x08000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT              27
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT              1
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [25:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK                 0x03000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT                24
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [23:22] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK                0x00c00000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT               22
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT             2
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [21:20] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK               0x00300000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT              20
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK                0x00080000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT               19
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK             0x00020000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT            17
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK             0x0001c000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT            14
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK             0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT            13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT               0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK             0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT            1
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_MASK             0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_SHIFT            2
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_MASK                0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_SHIFT               1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_DEFAULT             0
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_SHIFT               0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_DEFAULT             0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_RAAGA_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_SHIFT            0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_DEFAULT          0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_RAAGA_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_SHIFT            0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_DEFAULT          0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_MASK               0xffffe000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_SHIFT              13
+
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: NDIV_INT [12:03] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_MASK                0x00001ff8
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_SHIFT               3
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_DEFAULT             143
+
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_MASK                    0x00000007
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_SHIFT                   0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_DEFAULT                 2
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x00003fc0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 6
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 7
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_MASK              0xff000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_SHIFT             24
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 9
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 4
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x00000007
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   2
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_reserved0_MASK              0x80000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_reserved0_SHIFT             31
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: LDO_REF_SEL [30:30] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_MASK            0x40000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_SHIFT           30
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_DEFAULT         0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: POR_BYPASS [29:29] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_MASK             0x20000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_SHIFT            29
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_DEFAULT          0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: NDIV_RELOCK [28:28] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_MASK            0x10000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_SHIFT           28
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_DEFAULT         0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: FAST_LOCK [27:27] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_MASK              0x08000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_SHIFT             27
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_DEFAULT           0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_MASK                0x04000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_SHIFT               26
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_DEFAULT             1
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_DLY [25:24] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_MASK                0x03000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_SHIFT               24
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_DEFAULT             0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PWM_RATE [23:22] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_MASK               0x00c00000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_SHIFT              22
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_DEFAULT            2
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_MODE [21:20] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_MASK              0x00300000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_SHIFT             20
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_DEFAULT           0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_MASK               0x00080000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_SHIFT              19
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_DEFAULT            0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_MASK              0x00040000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_SHIFT             18
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_DEFAULT           0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_MASK            0x00020000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_SHIFT           17
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_DEFAULT         0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_MASK            0x0001c000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_SHIFT           14
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_DEFAULT         0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__MASK            0x00002000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__SHIFT           13
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__DEFAULT         0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00000fff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_MASK            0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_SHIFT           1
+
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_MASK       0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT      0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_MASK            0xfffff000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_SHIFT           12
+
+/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_SHIFT         0
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_SHIFT               2
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_MASK                   0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_SHIFT                  1
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_DEFAULT                0
+
+/***************************************************************************
+ *PLL_SC_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_SHIFT               1
+
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SC_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SC_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_MASK                  0xffffe000
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_SHIFT                 13
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: NDIV_INT [12:03] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_MASK                   0x00001ff8
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_SHIFT                  3
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_DEFAULT                64
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_MASK                       0x00000007
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_SHIFT                      0
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_DEFAULT                    1
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK     0x00003fc0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT    6
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT  40
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK     0x00003fc0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT    6
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT  40
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK     0x00003fc0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT    6
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT  40
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_MASK                 0xff000000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_SHIFT                24
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK         0x00000007
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT        0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT      1
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK  0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_MASK                 0xc0000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_SHIFT                30
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: MDIV_RELOCK [29:29] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_MASK               0x20000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_SHIFT              29
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: FAST_LOCK [28:28] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_SHIFT                28
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2 [27:27] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_MASK                   0x08000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_SHIFT                  27
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCO_DLY [26:25] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_MASK                   0x06000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_SHIFT                  25
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: PWM_RATE [24:23] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_MASK                  0x01800000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_SHIFT                 23
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_DEFAULT               0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_MASK                 0x00600000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_SHIFT                21
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2_POST [20:20] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_MASK              0x00100000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_SHIFT             20
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_DEFAULT           0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_MASK                  0x00080000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_SHIFT                 19
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_DEFAULT               0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_MASK                 0x00040000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_SHIFT                18
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_MASK               0x00020000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_SHIFT              17
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_MASK               0x0001c000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_SHIFT              14
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__MASK               0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__SHIFT              13
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK    0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT   12
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_SHIFT          0
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT        0
+
+/***************************************************************************
+ *PLL_SC_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_SHIFT              0
+
+/***************************************************************************
+ *PLL_SC_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_MASK               0xfffff000
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_SHIFT              12
+
+/* CLKGEN :: PLL_SC_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_MASK             0x00000fff
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_SHIFT            0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: NDIV_INT [12:03] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_MASK                 0x00001ff8
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_SHIFT                3
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_DEFAULT              64
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_MASK                     0x00000007
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_SHIFT                    0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_DEFAULT                  2
+
+/***************************************************************************
+ *PLL_VCXO_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_MASK               0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_SHIFT              20
+
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_MASK            0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_SHIFT           0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  6
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 64
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  6
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 250
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  6
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 75
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [13:06] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  6
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 4
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [05:05] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 5
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [04:04] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 4
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [03:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000007
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    1
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: MDIV_RELOCK [29:29] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_MASK             0x20000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_SHIFT            29
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: FAST_LOCK [28:28] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_MASK               0x10000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_SHIFT              28
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2 [27:27] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_MASK                 0x08000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_SHIFT                27
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCO_DLY [26:25] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_MASK                 0x06000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_SHIFT                25
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: PWM_RATE [24:23] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_MASK                0x01800000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_SHIFT               23
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_DEFAULT             0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2_POST [20:20] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_MASK            0x00100000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_SHIFT           20
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_DEFAULT         0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_MASK                0x00080000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_SHIFT               19
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_MASK             0x00020000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_SHIFT            17
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_MASK             0x0001c000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_SHIFT            14
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__MASK             0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__SHIFT            13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT            0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT                1
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  1
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *HIF_INST_CLOCK_DISABLE - Disable HIF_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_MASK          0xfffffff8
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_SHIFT         3
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CLOCK [02:02] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_DEFAULT 0
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [01:01] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_EBI_CLOCK [00:00] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_32_INST_MEMORY_STANDBY_ENABLE - Memsys 32 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MEMSYS_32_INST_MEMORY_STANDBY_ENABLE :: DDR_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_DDR_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_DDR_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_DDR_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SDS0_TOP_INST_CLOCK_DISABLE - Disable SDS0_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: SDS0_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1
+
+/* CLKGEN :: SDS0_TOP_INST_CLOCK_DISABLE :: DISABLE_SDS_108_PRESPMBALANCE_CLOCK [00:00] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_DISABLE_SDS_108_PRESPMBALANCE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_DISABLE_SDS_108_PRESPMBALANCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_DISABLE_SDS_108_PRESPMBALANCE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB1_INST_OBSERVE_CLOCK - Usb1 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *FTM_TOP_INST_CLOCK_ENABLE - Ftm top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: FTM_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffff8
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      3
+
+/* CLKGEN :: FTM_TOP_INST_CLOCK_ENABLE :: FTM_CH1_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_CH1_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_CH1_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_CH1_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: FTM_TOP_INST_CLOCK_ENABLE :: FTM_CH0_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_CH0_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_CH0_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_CH0_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: FTM_TOP_INST_CLOCK_ENABLE :: FTM_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_DISABLE - Disable VEC_AIO_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_MASK  0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_ITU656_CLOCK [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_DEFAULT 0
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB0_INST_MEMORY_STANDBY_ENABLE - Usb0 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: USB0_INST_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE - Graphics inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_SHIFT     2
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *PM_CLOCK_216_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_SHIFT         1
+
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_MASK   0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT  0
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE - Disable DUAL_GENET_TOP_DUAL_RGMII_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: reserved0 [31:08] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_reserved0_MASK 0xffffff00
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_reserved0_SHIFT 8
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET_ALWAYSON_CLOCK [07:07] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_MASK 0x00000080
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_SHIFT 7
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK [06:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_MASK 0x00000040
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_SHIFT 6
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_PM_CLOCK [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_FAST_CLOCK [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_FAST_CLOCK [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_EPHY_PLL_INPUT_CLOCK [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_EPHY_PLL_INPUT_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_EPHY_PLL_INPUT_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_EPHY_PLL_INPUT_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_INST_CLOCK_DISABLE - Disable SYS_CTRL_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffff0
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_SHIFT    4
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [03:03] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK [02:02] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE - Sds0 afec top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE :: SDSAFEC0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_OBSERVE_PLL_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_OBSERVE_PLL_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_reserved0_MASK     0xfffffe00
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_reserved0_SHIFT    9
+
+/* CLKGEN :: PAD_OBSERVE_PLL_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_OBSERVE_PLL_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_OBSERVE_PLL_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_32_INST_CLOCK_ENABLE - Memsys 32 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_reserved0_SHIFT    2
+
+/* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE :: DDR_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_DDR_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_DDR_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_DDR_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE :: DDR_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_DDR_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_DDR_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_DDR_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *USB1_INST_MEMORY_STANDBY_ENABLE - Usb1 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: USB1_INST_MEMORY_STANDBY_ENABLE :: USB1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SECTOP_INST_CLOCK_ENABLE_M2MDMA - Sectop inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_reserved0_SHIFT 1
+
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA :: M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_DEFAULT 1
+
+/***************************************************************************
+ *PAD_CLOCK_DISABLE - Disable PAD's clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:06] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK               0xffffffc0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT              6
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_SC_CLOCK [05:05] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_VCXO27_CLOCK [04:04] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_OBSERVE_PLL_CLOCK [03:03] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_OBSERVE_PLL_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_OBSERVE_PLL_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_OBSERVE_PLL_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [02:02] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLKUSB_CLOCK [01:01] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKUSB_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKUSB_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKUSB_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *UHFR_TOP_INST_CLOCK_DISABLE - Disable UHFR_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1
+
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE :: DISABLE_UHFR_ALWAYSON_CLOCK [00:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
+ ***************************************************************************/
+/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:02] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK             0xfffffffc
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT            2
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [01:01] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [00:00] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_INST_CLOCK_DISABLE - Disable DVP_HT_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB0_INST_OBSERVE_CLOCK - Usb0 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB0_INST_CLOCK_DISABLE - Disable USB0_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_reserved0_SHIFT        2
+
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: DISABLE_USB0_54_FREERUN_CLOCK [01:01] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_FREERUN_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_FREERUN_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_FREERUN_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: DISABLE_USB0_54_MDIO_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_CLOCK_DISABLE - Disable CORE_XPT_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_MASK     0xffffffe0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_SHIFT    5
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_INST_MEMORY_STANDBY_ENABLE - Dvp ht inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: DVP_HT_INST_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_MUX_SELECT - Mux selects for Pad clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK                  0xfffffff8
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT                 3
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_VCXO27_CLOCK [02:02] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_MASK    0x00000004
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_SHIFT   2
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLKUSB_CLOCK [01:01] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLKUSB_CLOCK_MASK    0x00000002
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLKUSB_CLOCK_SHIFT   1
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLKUSB_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_MASK     0x00000001
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_SHIFT    0
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_DEFAULT  0
+
+/***************************************************************************
+ *SYS_AON_INST_OBSERVE_CLOCK - Sys aon inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *UHFR_TOP_INST_POWER_SWITCH_MEMORY - Uhfr top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: UHFR_TOP_INST_POWER_SWITCH_MEMORY :: UHFR_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A - Dual genet top dual rgmii inst power switch memory a
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A :: GENET0_POWER_SWITCH_MEMORY_A [01:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_MASK 0x00000003
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_DEFAULT 0
+
+/***************************************************************************
+ *USB0_INST_POWER_SWITCH_MEMORY - Usb0 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: USB0_INST_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
+ ***************************************************************************/
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:11] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK            0xfffff800
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT           11
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC_OUT_CLOCK [10:08] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_MASK         0x00000700
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_SHIFT        8
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_DEFAULT      0
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [07:05] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK            0x000000e0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT           5
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT         0
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [04:02] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK            0x0000001c
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT           2
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT         0
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: PLLSC_REFERENCE_CLOCK [01:00] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_MASK 0x00000003
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB1_INST_CLOCK_DISABLE - Disable USB1_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_reserved0_SHIFT        2
+
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: DISABLE_USB1_54_FREERUN_CLOCK [01:01] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_FREERUN_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_FREERUN_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_FREERUN_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: DISABLE_USB1_54_MDIO_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SDS1_TOP_INST_CLOCK_DISABLE - Disable SDS1_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: SDS1_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1
+
+/* CLKGEN :: SDS1_TOP_INST_CLOCK_DISABLE :: DISABLE_SDS_108_PRESPMBALANCE_CLOCK [00:00] */
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_DISABLE_DISABLE_SDS_108_PRESPMBALANCE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_DISABLE_DISABLE_SDS_108_PRESPMBALANCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_DISABLE_DISABLE_SDS_108_PRESPMBALANCE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_DISABLE - Disable GRAPHICS_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_reserved0_SHIFT    1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_DISABLE :: DISABLE_GFX_M2MC_CORE_CLOCK [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SDS1_AFEC_TOP_INST_CLOCK_ENABLE - Sds1 afec top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS1_AFEC_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS1_AFEC_TOP_INST_CLOCK_ENABLE :: SDSAFEC1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC1_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO - Vec aio top inst clock enable aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_DEFAULT 1
+
+/***************************************************************************
+ *SDS0_AFEC_TOP_INST_OBSERVE_CLOCK - Sds0 afec top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO - Vec aio top inst memory standby enable aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO :: AIO_MEMORY_STANDBY_ENABLE_AIO [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_INST_POWER_SWITCH_MEMORY - Dvp ht inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: DVP_HT_INST_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A - Dual genet top dual rgmii inst memory standby enable a
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: GENET0_MEMORY_STANDBY_ENABLE_A [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_INST_CLOCK_ENABLE - Dvp ht inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_MASK        0xffffffc0
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_SHIFT       6
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_CLK_VEC_ENABLE [05:05] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_VEC_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_VEC_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_VEC_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_CLK_MAX_ENABLE [04:04] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_MAX_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_MAX_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_MAX_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_ALTERNATE_216_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_ALTERNATE_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *MEMSYS_32_INST_OBSERVE_CLOCK - Memsys 32 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_reserved0_MASK    0xffffffc0
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_reserved0_SHIFT   6
+
+/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: DDR_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: DDR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: DDR_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_32_INST_POWER_MANAGEMENT - Memsys 32 inst power management
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_POWER_MANAGEMENT :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT_reserved0_SHIFT 1
+
+/* CLKGEN :: MEMSYS_32_INST_POWER_MANAGEMENT :: MEMSYS_PLL_PWRDN_POWER_MANAGEMENT [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_CLOCK_ENABLE - Core xpt inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_SHIFT     2
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *CORE_XPT_INST_MEMORY_STANDBY_ENABLE - Core xpt inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: CORE_XPT_INST_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_OBSERVE_CLOCK - Vec aio top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_AIO_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_AIO_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_MEMORY_STANDBY_ENABLE - Graphics inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE :: GFX_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH7 - clkgen  Scratch register
+ ***************************************************************************/
+/* CLKGEN :: SCRATCH7 :: VALUE [31:00] */
+#define BCHP_CLKGEN_SCRATCH7_VALUE_MASK                            0xffffffff
+#define BCHP_CLKGEN_SCRATCH7_VALUE_SHIFT                           0
+#define BCHP_CLKGEN_SCRATCH7_VALUE_DEFAULT                         0
+
+/***************************************************************************
+ *UHFR_TOP_INST_OBSERVE_CLOCK - Uhfr top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_INST_OBSERVE_CLOCK - Dvp ht inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT - Dual genet top dual rgmii inst clock select
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: reserved0 [31:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_reserved0_SHIFT 4
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: GENET1_GMII_CLOCK_SELECT [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: GENET1_CLOCK_SELECT [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: GENET0_GMII_CLOCK_SELECT [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: GENET0_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_SHIFT                0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_DEFAULT              0
+
+/***************************************************************************
+ *FTM_TOP_INST_MEMORY_STANDBY_ENABLE - Ftm top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: FTM_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_FTM_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_FTM_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: FTM_TOP_INST_MEMORY_STANDBY_ENABLE :: FTM_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_FTM_TOP_INST_MEMORY_STANDBY_ENABLE_FTM_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_FTM_TOP_INST_MEMORY_STANDBY_ENABLE_FTM_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_FTM_TOP_INST_MEMORY_STANDBY_ENABLE_FTM_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *UHFR_TOP_INST_MEMORY_STANDBY_ENABLE - Uhfr top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: UHFR_TOP_INST_MEMORY_STANDBY_ENABLE :: UHFR_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE - Sds1 afec top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE :: SDSAFEC1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC1_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *ZCPU_TOP_INST_CLOCK_DISABLE - Disable ZCPU_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1
+
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_DISABLE :: DISABLE_ZMIPS_FUNC_BYP_CLOCK [00:00] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_FUNC_BYP_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_FUNC_BYP_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_FUNC_BYP_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH6 - clkgen  Scratch register
+ ***************************************************************************/
+/* CLKGEN :: SCRATCH6 :: VALUE [31:00] */
+#define BCHP_CLKGEN_SCRATCH6_VALUE_MASK                            0xffffffff
+#define BCHP_CLKGEN_SCRATCH6_VALUE_SHIFT                           0
+#define BCHP_CLKGEN_SCRATCH6_VALUE_DEFAULT                         0
+
+/***************************************************************************
+ *SDS1_RECEIVER_INST_OBSERVE_CLOCK - Sds1 receiver inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS1_RECEIVER_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: SDS1_RECEIVER_INST_OBSERVE_CLOCK :: SDSRCVR1_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS1_RECEIVER_INST_OBSERVE_CLOCK :: SDSRCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS1_RECEIVER_INST_OBSERVE_CLOCK :: SDSRCVR1_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SDS1_TFEC_TOP_INST_OBSERVE_CLOCK - Sds1 tfec top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS1_TFEC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: SDS1_TFEC_TOP_INST_OBSERVE_CLOCK :: SDTFECR1_ENABLE_DIVIDER_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDTFECR1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDTFECR1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDTFECR1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS1_TFEC_TOP_INST_OBSERVE_CLOCK :: SDSTFEC1_ENABLE_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC1_ENABLE_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC1_ENABLE_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC1_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS1_TFEC_TOP_INST_OBSERVE_CLOCK :: SDSTFEC1_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC1_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC1_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE - Vec aio top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_AIO_ALTERNATE_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *FTM_TOP_INST_POWER_SWITCH_MEMORY - Ftm top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: FTM_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_FTM_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_FTM_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: FTM_TOP_INST_POWER_SWITCH_MEMORY :: FTM_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_FTM_TOP_INST_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_FTM_TOP_INST_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_FTM_TOP_INST_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC - Vec aio top inst memory standby enable vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC :: VEC_MEMORY_STANDBY_ENABLE_VEC [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_DEFAULT 0
+
+/***************************************************************************
+ *SDS0_AFEC_TOP_INST_CLOCK_ENABLE - Sds0 afec top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS0_AFEC_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_CLOCK_ENABLE :: SDSAFEC0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SDS0_RECEIVER_INST_OBSERVE_CLOCK - Sds0 receiver inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS0_RECEIVER_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: SDS0_RECEIVER_INST_OBSERVE_CLOCK :: SDSRCVR0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_RECEIVER_INST_OBSERVE_CLOCK :: SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_RECEIVER_INST_OBSERVE_CLOCK :: SDSRCVR0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO - Vec aio top inst power switch memory aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO :: AIO_POWER_SWITCH_MEMORY_AIO [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_DEFAULT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY - Raaga dsp top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY :: RAAGA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *MOCA_TOP_INST_MEMORY_STANDBY_ENABLE - Moca top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MOCA_TOP_INST_MEMORY_STANDBY_ENABLE :: MOCA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CODEC_MCLK_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_MASK      0xfffffe00
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_SHIFT     9
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SVD_TOP_INST_MEMORY_STANDBY_ENABLE - Svd top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SVD_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SVD_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SVD_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SVD_TOP_INST_MEMORY_STANDBY_ENABLE :: SVD_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SVD_TOP_INST_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SVD_TOP_INST_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SVD_TOP_INST_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_OBSERVE_CLOCK - Raaga Dsp top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_CLOCK_ENABLE - Raaga dsp top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_DSP_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *BVN_TOP_INST_MEMORY_STANDBY_ENABLE - Bvn top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: BVN_TOP_INST_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *BVN_TOP_INST_POWER_SWITCH_MEMORY - Bvn top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: BVN_TOP_INST_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SATA3_TOP_INST_CLOCK_SELECT - Sata3 top inst clock select
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_SHIFT    1
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: SATA3_REF_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_DEFAULT 1
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC - Vec aio top inst power switch memory vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC :: VEC_POWER_SWITCH_MEMORY_VEC [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_DEFAULT 0
+
+/***************************************************************************
+ *SDS1_AFEC_TOP_INST_OBSERVE_CLOCK - Sds1 afec top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS1_AFEC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: SDS1_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC1_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS1_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS1_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC1_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SDS0_TOP_INST_CLOCK_ENABLE - Sds0  top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: SDS0_TOP_INST_CLOCK_ENABLE :: SDS0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_SDS0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_SDS0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_SDS0_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *USB1_INST_POWER_SWITCH_MEMORY - Usb1 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: USB1_INST_POWER_SWITCH_MEMORY :: USB1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *USB0_INST_CLOCK_ENABLE - Usb0 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: USB0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SATA3_TOP_INST_MEMORY_STANDBY_ENABLE - Sata3 top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SATA3_TOP_INST_MEMORY_STANDBY_ENABLE :: SATA3_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC - Vec aio top inst clock enable vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: reserved0 [31:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_SHIFT 5
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_SCB_CLOCK_ENABLE_VEC [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_QDAC_216_CLOCK_ENABLE_VEC [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_SHIFT 3
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_ALTERNATE_216_CLOCK_ENABLE_VEC [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_216_CLOCK_ENABLE_VEC [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_108_CLOCK_ENABLE_VEC [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/***************************************************************************
+ *MOCA_TOP_INST_OBSERVE_CLOCK - Moca top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLK27_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_MASK           0xfffffe00
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_SHIFT          9
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_MASK  0x00000100
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_MASK  0x000000fe
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK  0x00000001
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_32_INST_POWER_SWITCH_MEMORY - Memsys 32 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: MEMSYS_32_INST_POWER_SWITCH_MEMORY :: DDR_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_DDR_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_DDR_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_DDR_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_POWER_SWITCH_MEMORY - Graphics inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY :: GFX_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SDS0_TFEC_TOP_INST_OBSERVE_CLOCK - Sds0 tfec top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS0_TFEC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: SDS0_TFEC_TOP_INST_OBSERVE_CLOCK :: SDTFECR0_ENABLE_DIVIDER_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDTFECR0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDTFECR0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDTFECR0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_TFEC_TOP_INST_OBSERVE_CLOCK :: SDSTFEC0_ENABLE_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_TFEC_TOP_INST_OBSERVE_CLOCK :: SDSTFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SATA3_TOP_INST_POWER_SWITCH_MEMORY - Sata3 top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SATA3_TOP_INST_POWER_SWITCH_MEMORY :: SATA3_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SVD_TOP_INST_CLOCK_ENABLE - Svd top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SVD_TOP_INST_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xffffffe0
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      5
+
+/* CLKGEN :: SVD_TOP_INST_CLOCK_ENABLE :: SVD_SCB_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SVD_TOP_INST_CLOCK_ENABLE :: SVD_CPU_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SVD_TOP_INST_CLOCK_ENABLE :: SVD_AVD_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SVD_TOP_INST_CLOCK_ENABLE :: SVD_ALTERNATE_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SVD_TOP_INST_CLOCK_ENABLE :: SVD_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *HIF_INST_POWER_SWITCH_MEMORY - Hif inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: HIF_INST_POWER_SWITCH_MEMORY :: HIF_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SATA3_TOP_INST_CLOCK_ENABLE - Sata3 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT    2
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *CORE_XPT_INST_OBSERVE_CLOCK - Core xpt inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *HIF_INST_MEMORY_STANDBY_ENABLE - Hif inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: HIF_INST_MEMORY_STANDBY_ENABLE :: HIF_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH8 - clkgen  Scratch register
+ ***************************************************************************/
+/* CLKGEN :: SCRATCH8 :: VALUE [31:00] */
+#define BCHP_CLKGEN_SCRATCH8_VALUE_MASK                            0xffffffff
+#define BCHP_CLKGEN_SCRATCH8_VALUE_SHIFT                           0
+#define BCHP_CLKGEN_SCRATCH8_VALUE_DEFAULT                         0
+
+/***************************************************************************
+ *SVD_TOP_INST_POWER_SWITCH_MEMORY - Svd top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SVD_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SVD_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SVD_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SVD_TOP_INST_POWER_SWITCH_MEMORY :: SVD_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SVD_TOP_INST_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SVD_TOP_INST_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SVD_TOP_INST_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SDS1_TOP_INST_CLOCK_ENABLE - Sds1 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS1_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: SDS1_TOP_INST_CLOCK_ENABLE :: SDS1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_ENABLE_SDS1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_ENABLE_SDS1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_ENABLE_SDS1_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *UHFR_TOP_INST_CLOCK_ENABLE - Uhfr top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE :: UHFR_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY - Sds1 afec top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY :: SDSAFEC1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC1_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *USB1_INST_CLOCK_ENABLE - Usb1 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: USB1_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: USB1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SATA3_INST_CLOCK_DISABLE - Disable SATA3_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: SATA3_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_reserved0_SHIFT       1
+
+/* CLKGEN :: SATA3_INST_CLOCK_DISABLE :: DISABLE_27_FUNC_CLK_30 [00:00] */
+#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_DISABLE_27_FUNC_CLK_30_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_DISABLE_27_FUNC_CLK_30_SHIFT 0
+#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_DISABLE_27_FUNC_CLK_30_DEFAULT 0
+
+/***************************************************************************
+ *SATA3_TOP_INST_OBSERVE_CLOCK - Sata3 top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_MASK    0xffffffc0
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT   6
+
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_INST_MEMORY_STANDBY_ENABLE - Sys ctrl inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SYS_CTRL_INST_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK - Dual genet top dual rgmii inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE - Dual genet top dual rgmii inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: reserved0 [31:16] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_reserved0_SHIFT 16
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [15:15] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00008000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 15
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET_108_CLOCK_ENABLE [14:14] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_MASK 0x00004000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_SHIFT 14
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE [13:13] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE [12:12] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00001000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_L2INTR_CLOCK_ENABLE [11:11] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_MASK 0x00000800
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_SHIFT 11
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_HFB_CLOCK_ENABLE [10:10] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_MASK 0x00000400
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_SHIFT 10
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_GMII_CLOCK_ENABLE [09:09] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_MASK 0x00000200
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_SHIFT 9
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_EEE_CLOCK_ENABLE [08:08] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_MASK 0x00000100
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_SHIFT 8
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_CLK_250_CLOCK_ENABLE [07:07] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_MASK 0x00000080
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_SHIFT 7
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_L2INTR_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_HFB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_GMII_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_EEE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_CLK_250_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE - Raaga dsp top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE :: RAAGAA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_POWER_SWITCH_MEMORY - Core xpt inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: CORE_XPT_INST_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *PAD_VCXO27_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_MASK          0xfffffe00
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_SHIFT         9
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *ZCPU_TOP_INST_OBSERVE_CLOCK - Zcpu top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_OBSERVE_CLOCK - Graphics inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_M2MC_CLOCK_ENABLE - Disable GRAPHICS_INST's m2mc clock
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_M2MC_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_M2MC_CLOCK_ENABLE :: GFX_M2MC_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *PM_CLOCK_108_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: reserved0 [31:05] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_SHIFT         5
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDS1 [04:04] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS1_MASK  0x00000010
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS1_SHIFT 4
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS1_DEFAULT 0
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDS0 [03:03] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS0_MASK  0x00000008
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS0_SHIFT 3
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS0_DEFAULT 0
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSAFEC1 [02:02] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC1_MASK 0x00000004
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC1_SHIFT 2
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC1_DEFAULT 0
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSAFEC0 [01:01] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC0_MASK 0x00000002
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC0_SHIFT 1
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC0_DEFAULT 0
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_FTM [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_FTM_MASK   0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_FTM_SHIFT  0
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_FTM_DEFAULT 0
+
+/***************************************************************************
+ *SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY - Sds0 afec top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY :: SDSAFEC0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_INST_OBSERVE_CLOCK - Sys ctrl inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *BVN_TOP_INST_CLOCK_ENABLE - Bvn top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffff8
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      3
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SYS_CTRL_INST_POWER_SWITCH_MEMORY - Sys ctrl inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SYS_CTRL_INST_POWER_SWITCH_MEMORY :: SYS_CTRL_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *MOCA_TOP_INST_POWER_SWITCH_MEMORY - Moca top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: MOCA_TOP_INST_POWER_SWITCH_MEMORY :: MOCA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *MOCA_TOP_INST_CLOCK_ENABLE - Moca top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     2
+
+/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: MOCA_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: MOCA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SCRATCH4 - clkgen  Scratch register
+ ***************************************************************************/
+/* CLKGEN :: SCRATCH4 :: VALUE [31:00] */
+#define BCHP_CLKGEN_SCRATCH4_VALUE_MASK                            0xffffffff
+#define BCHP_CLKGEN_SCRATCH4_VALUE_SHIFT                           0
+#define BCHP_CLKGEN_SCRATCH4_VALUE_DEFAULT                         0
+
+/***************************************************************************
+ *PLL_DDR_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_DDR_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_reserved0_SHIFT        1
+
+/* CLKGEN :: PLL_DDR_PLL_LOCK_STATUS :: DDR_LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_DDR_LOCK_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_DDR_LOCK_SHIFT         0
+
+/***************************************************************************
+ *PM_PLL_ALIVE_SEL - pll alive in standby mode
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               3
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_DDR [02:02] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR_MASK                  0x00000004
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR_SHIFT                 2
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR_DEFAULT               0
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_MIPS [01:01] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_MASK                 0x00000002
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_SHIFT                1
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_DEFAULT              0
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [00:00] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK                 0x00000001
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT                0
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT              0
+
+/***************************************************************************
+ *SPI_CLOCK_SELECT - spi clock control
+ ***************************************************************************/
+/* CLKGEN :: SPI_CLOCK_SELECT :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SPI_CLOCK_SELECT_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_SPI_CLOCK_SELECT_reserved0_SHIFT               1
+
+/* CLKGEN :: SPI_CLOCK_SELECT :: SPI_CLOCK_OVERRIDE_STRAP [00:00] */
+#define BCHP_CLKGEN_SPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_MASK 0x00000001
+#define BCHP_CLKGEN_SPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_SHIFT 0
+#define BCHP_CLKGEN_SPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS - Bypass DUAL_GENET_TOP_DUAL_RGMII_INST clocks
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_reserved0_SHIFT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS :: EEE_25_CLOCK_BYPASS [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH2 - clkgen  Scratch register
+ ***************************************************************************/
+/* CLKGEN :: SCRATCH2 :: VALUE [31:00] */
+#define BCHP_CLKGEN_SCRATCH2_VALUE_MASK                            0xffffffff
+#define BCHP_CLKGEN_SCRATCH2_VALUE_SHIFT                           0
+#define BCHP_CLKGEN_SCRATCH2_VALUE_DEFAULT                         0
+
+/***************************************************************************
+ *GRAPHICS_INST_V3D_CLOCK_ENABLE - Graphics inst V3D clock enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_V3D_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_V3D_CLOCK_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_V3D_CLOCK_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_V3D_CLOCK_ENABLE :: GFX_V3D_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_V3D_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_V3D_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_V3D_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *PLL_MIPS_CTRL - Mips PLL Control Register
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_CTRL :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_reserved0_MASK                   0x80000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_reserved0_SHIFT                  31
+
+/* CLKGEN :: PLL_MIPS_CTRL :: BYPASS_PLL_RQ [30:30] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_RQ_MASK               0x40000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_RQ_SHIFT              30
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_RQ_DEFAULT            0
+
+/* CLKGEN :: PLL_MIPS_CTRL :: BYPASS_PLL_STATE [29:29] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_MASK            0x20000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_SHIFT           29
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_DEFAULT         0
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_normal_PLL_mode 0
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_bypassed_PLL_mode 1
+
+/* union - case normal_PLL_mode [28:23] */
+/* CLKGEN :: PLL_MIPS_CTRL :: normal_PLL_mode :: A_RST_PLL [28:28] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_A_RST_PLL_MASK   0x10000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_A_RST_PLL_SHIFT  28
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_A_RST_PLL_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_CTRL :: normal_PLL_mode :: D_RST_PLL [27:27] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_D_RST_PLL_MASK   0x08000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_D_RST_PLL_SHIFT  27
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_D_RST_PLL_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_CTRL :: normal_PLL_mode :: CPU_FREQ [26:24] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_CPU_FREQ_MASK    0x07000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_CPU_FREQ_SHIFT   24
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_CPU_FREQ_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_CTRL :: normal_PLL_mode :: OVERRIDE_CPU_FREQ_PIN_STRAP [23:23] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_SHIFT 23
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_DEFAULT 0
+
+/* union - case bypassed_PLL_mode [28:23] */
+/* CLKGEN :: PLL_MIPS_CTRL :: bypassed_PLL_mode :: A_RST_PLL [28:28] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_A_RST_PLL_MASK 0x10000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_A_RST_PLL_SHIFT 28
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_A_RST_PLL_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_CTRL :: bypassed_PLL_mode :: D_RST_PLL [27:27] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_D_RST_PLL_MASK 0x08000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_D_RST_PLL_SHIFT 27
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_D_RST_PLL_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_CTRL :: bypassed_PLL_mode :: CPU_FREQ [26:24] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_CPU_FREQ_MASK  0x07000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_CPU_FREQ_SHIFT 24
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_CPU_FREQ_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_CTRL :: bypassed_PLL_mode :: OVERRIDE_CPU_FREQ_PIN_STRAP [23:23] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_SHIFT 23
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_CTRL :: reserved1 [22:00] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_reserved1_MASK                   0x007fffff
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_reserved1_SHIFT                  0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETD_MASK          0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETD_SHIFT         1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETD_DEFAULT       1
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETA_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETA_SHIFT         0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETA_DEFAULT       1
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETD_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETD_SHIFT       1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETD_DEFAULT     1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETA_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETA_SHIFT       0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETA_DEFAULT     1
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETD_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETD_SHIFT       1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETD_DEFAULT     1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETA_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETA_SHIFT       0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETA_DEFAULT     1
+
+/***************************************************************************
+ *PLL_AVD_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_RESETD_MASK           0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_RESETD_SHIFT          1
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_RESETD_DEFAULT        1
+
+/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_RESETA_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_RESETA_SHIFT          0
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_RESETA_DEFAULT        1
+
+/***************************************************************************
+ *PLL_MOCA_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETD_MASK          0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETD_SHIFT         1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETD_DEFAULT       1
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETA_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETA_SHIFT         0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETA_DEFAULT       1
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_RESETD_MASK          0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_RESETD_SHIFT         1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_RESETD_DEFAULT       1
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_RESETA_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_RESETA_SHIFT         0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_RESETA_DEFAULT       1
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_SHIFT     2
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETD_MASK         0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETD_SHIFT        1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETD_DEFAULT      1
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETA_MASK         0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETA_SHIFT        0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETA_DEFAULT      1
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_RESETD_MASK          0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_RESETD_SHIFT         1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_RESETD_DEFAULT       1
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_RESETA_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_RESETA_SHIFT         0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_RESETA_DEFAULT       1
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETD_MASK            0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETD_SHIFT           1
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETD_DEFAULT         1
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETA_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETA_SHIFT           0
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETA_DEFAULT         1
+
+/***************************************************************************
+ *TESTPORT - Special Testport Controls
+ ***************************************************************************/
+/* CLKGEN :: TESTPORT :: reserved0 [31:04] */
+#define BCHP_CLKGEN_TESTPORT_reserved0_MASK                        0xfffffff0
+#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT                       4
+
+/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [03:00] */
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK           0x0000000f
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT          0
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT        0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_AFEC_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_AFEC_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_AFEC_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_AFEC_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_AFEC_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AFEC_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_AFEC_PLL_DIV :: NDIV_INT [12:03] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_NDIV_INT_MASK                 0x00001ff8
+#define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_NDIV_INT_SHIFT                3
+#define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_NDIV_INT_DEFAULT              64
+
+/* CLKGEN :: PLL_AFEC_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_PDIV_MASK                     0x00000007
+#define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_PDIV_SHIFT                    0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_PDIV_DEFAULT                  2
+
+/***************************************************************************
+ *PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  6
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 4
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  6
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 36
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  6
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 36
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_AFEC_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8
+
+/* CLKGEN :: PLL_AFEC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AFEC_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000007
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    1
+
+/***************************************************************************
+ *PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: MDIV_RELOCK [29:29] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_MDIV_RELOCK_MASK             0x20000000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_MDIV_RELOCK_SHIFT            29
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_MDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: FAST_LOCK [28:28] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_FAST_LOCK_MASK               0x10000000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_FAST_LOCK_SHIFT              28
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: VCODIV2 [27:27] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCODIV2_MASK                 0x08000000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCODIV2_SHIFT                27
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCODIV2_DEFAULT              0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: VCO_DLY [26:25] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCO_DLY_MASK                 0x06000000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCO_DLY_SHIFT                25
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: PWM_RATE [24:23] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_PWM_RATE_MASK                0x01800000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_PWM_RATE_SHIFT               23
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_PWM_RATE_DEFAULT             0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: VCODIV2_POST [20:20] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCODIV2_POST_MASK            0x00100000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCODIV2_POST_SHIFT           20
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCODIV2_POST_DEFAULT         0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_AUX_CTRL_MASK                0x00080000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_AUX_CTRL_SHIFT               19
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_UPDATE_MASK             0x00020000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_UPDATE_SHIFT            17
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_SELECT_MASK             0x0001c000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_SELECT_SHIFT            14
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_RESET__MASK             0x00002000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_RESET__SHIFT            13
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_AFEC_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_AFEC_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_AFEC_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_AFEC_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_AFEC_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_AFEC_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_RESETD_MASK          0x00000002
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_RESETD_SHIFT         1
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_RESETD_DEFAULT       1
+
+/* CLKGEN :: PLL_AFEC_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_RESETA_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_RESETA_SHIFT         0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_RESETA_DEFAULT       1
+
+/***************************************************************************
+ *PLL_AVD_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_AVD_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_DEFAULT                0
+
+/***************************************************************************
+ *CLOCK_MONITOR_CONTROL - Clock Monitor Control
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT          4
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK   0x00000008
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT  3
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK    0x00000004
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT   2
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK      0x00000002
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT     1
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT   1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 1
+
+/***************************************************************************
+ *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK  0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT         1
+
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK     0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT    0
+
+/***************************************************************************
+ *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *PM_PLL_LDO_POWERUP - Power management LDO PLL
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_MASK              0xfffffff0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_SHIFT             4
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_SYS1 [03:03] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SYS1_MASK     0x00000008
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SYS1_SHIFT    3
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SYS1_DEFAULT  1
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_RAAGA [02:02] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_MASK    0x00000004
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_SHIFT   2
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_DEFAULT 1
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_MOCA [01:01] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_MASK     0x00000002
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_SHIFT    1
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_DEFAULT  1
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AVD [00:00] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_MASK      0x00000001
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_SHIFT     0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_DEFAULT   1
+
+/***************************************************************************
+ *PM_PLL_LDO_POWERUP_SM - Power management LDO PLL state machine
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: reserved0 [31:27] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_MASK           0xf8000000
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_SHIFT          27
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_POWERUP_WAIT_TIME [26:14] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_MASK 0x07ffc000
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_SHIFT 14
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_DEFAULT 5400
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_CLK_STOP_WAIT_TIME [13:01] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_MASK 0x00003ffe
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_SHIFT 1
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_DEFAULT 200
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: GISB_OVERRIDE_SM [00:00] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_MASK    0x00000001
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_SHIFT   0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_DEFAULT 0
+
+#endif /* #ifndef BCHP_CLKGEN_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_common.h b/include/linux/brcmstb/7346b0/bchp_common.h
new file mode 100644
index 0000000..6350d1b
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_common.h
@@ -0,0 +1,2396 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 31 16:16:36 2011
+ *                 MD5 Checksum         0b9cc5de2a03cabbf9a0a767bc10763a
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_common.h $
+ * 
+ * Hydra_Software_Devel/3   5/31/11 5:25p albertl
+ * SW7346-143: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_COMMON_H__
+#define BCHP_COMMON_H__
+
+/***************************************************************************
+ *BCM7346_B0
+ ***************************************************************************/
+#define BCHP_PHYSICAL_OFFSET                               0x10000000
+#define BCHP_REGISTER_START                                0x00000000 /* DECODE_RBNODE_REGS_0 is first */
+#define BCHP_REGISTER_END                                  0x00a3f004 /* XPT_SECURE_BUS_IF is last */
+#define BCHP_REGISTER_SIZE                                 0x0028fc01 /* Number of registers */
+
+/****************************************************************************
+ * Core instance register start address.
+ ***************************************************************************/
+#define BCHP_DECODE_RBNODE_REGS_0_REG_START                0x00000000
+#define BCHP_DECODE_RBNODE_REGS_0_REG_END                  0x0000007c
+#define BCHP_DECODE_MAIN_0_REG_START                       0x00000100
+#define BCHP_DECODE_MAIN_0_REG_END                         0x000001fc
+#define BCHP_SDRAM_DEBUG_0_REG_START                       0x00000200
+#define BCHP_SDRAM_DEBUG_0_REG_END                         0x0000027c
+#define BCHP_DECODE_MCOM_0_REG_START                       0x00000300
+#define BCHP_DECODE_MCOM_0_REG_END                         0x0000031c
+#define BCHP_DECODE_SPRE_0_REG_START                       0x00000320
+#define BCHP_DECODE_SPRE_0_REG_END                         0x0000033c
+#define BCHP_DECODE_WPRD_0_REG_START                       0x00000340
+#define BCHP_DECODE_WPRD_0_REG_END                         0x0000035c
+#define BCHP_DECODE_DQNT_0_REG_START                       0x00000400
+#define BCHP_DECODE_DQNT_0_REG_END                         0x0000045c
+#define BCHP_DECODE_DQNT_8X8_0_REG_START                   0x00000500
+#define BCHP_DECODE_DQNT_8X8_0_REG_END                     0x0000057c
+#define BCHP_DECODE_VP8_XFRM_0_REG_START                   0x00000600
+#define BCHP_DECODE_VP8_XFRM_0_REG_END                     0x0000060c
+#define BCHP_DECODE_XFRM_0_REG_START                       0x00000700
+#define BCHP_DECODE_XFRM_0_REG_END                         0x0000071c
+#define BCHP_DECODE_DBLK_0_REG_START                       0x00000720
+#define BCHP_DECODE_DBLK_0_REG_END                         0x0000073c
+#define BCHP_DECODE_MB_0_REG_START                         0x00000740
+#define BCHP_DECODE_MB_0_REG_END                           0x0000075c
+#define BCHP_REG_CABAC2BINS_0_REG_START                    0x00000b00
+#define BCHP_REG_CABAC2BINS_0_REG_END                      0x00000bfc
+#define BCHP_DECODE_SINT_0_REG_START                       0x00000c00
+#define BCHP_DECODE_SINT_0_REG_END                         0x00000dfc
+#define BCHP_DECODE_RVC_0_REG_START                        0x00000e00
+#define BCHP_DECODE_RVC_0_REG_END                          0x00000efc
+#define BCHP_DECODE_CPUREGS_0_REG_START                    0x00000f00
+#define BCHP_DECODE_CPUREGS_0_REG_END                      0x00000f7c
+#define BCHP_DECODE_CPUREGS2_0_REG_START                   0x00000f80
+#define BCHP_DECODE_CPUREGS2_0_REG_END                     0x00000ffc
+#define BCHP_DECODE_CPUDMA_0_REG_START                     0x00001800
+#define BCHP_DECODE_CPUDMA_0_REG_END                       0x000018fc
+#define BCHP_DECODE_DMAMEM_0_REG_START                     0x00001a00
+#define BCHP_DECODE_DMAMEM_0_REG_END                       0x000021fc
+#define BCHP_REG_CABAC2BINS2_0_REG_START                   0x00002400
+#define BCHP_REG_CABAC2BINS2_0_REG_END                     0x000027fc
+#define BCHP_DECODE_WPTBL_0_REG_START                      0x00003000
+#define BCHP_DECODE_WPTBL_0_REG_END                        0x000031fc
+#define BCHP_DECODE_SINT_OLOOP_0_REG_START                 0x0000cc00
+#define BCHP_DECODE_SINT_OLOOP_0_REG_END                   0x0000ccfc
+#define BCHP_DECODE_SD_0_REG_START                         0x00040800
+#define BCHP_DECODE_SD_0_REG_END                           0x00040ffc
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_START             0x00041000
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_END               0x0004107c
+#define BCHP_DECODE_CPUCORE_0_REG_START                    0x00044000
+#define BCHP_DECODE_CPUCORE_0_REG_END                      0x00044ffc
+#define BCHP_DECODE_CPUAUX_0_REG_START                     0x00045000
+#define BCHP_DECODE_CPUAUX_0_REG_END                       0x00045ffc
+#define BCHP_DECODE_CPUIMEM_0_REG_START                    0x00046000
+#define BCHP_DECODE_CPUIMEM_0_REG_END                      0x00047ffc
+#define BCHP_DECODE_CPUDMEM_0_REG_START                    0x00048000
+#define BCHP_DECODE_CPUDMEM_0_REG_END                      0x0004fffc
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_START            0x00051000
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_END              0x0005107c
+#define BCHP_DECODE_CPUDMA2_0_REG_START                    0x00051800
+#define BCHP_DECODE_CPUDMA2_0_REG_END                      0x000518fc
+#define BCHP_DECODE_DMAMEM2_0_REG_START                    0x00051a00
+#define BCHP_DECODE_DMAMEM2_0_REG_END                      0x000521fc
+#define BCHP_DECODE_CPUCORE2_0_REG_START                   0x00054000
+#define BCHP_DECODE_CPUCORE2_0_REG_END                     0x00054ffc
+#define BCHP_DECODE_CPUAUX2_0_REG_START                    0x00055000
+#define BCHP_DECODE_CPUAUX2_0_REG_END                      0x00055ffc
+#define BCHP_DECODE_CPUIMEM2_0_REG_START                   0x00056000
+#define BCHP_DECODE_CPUIMEM2_0_REG_END                     0x00057ffc
+#define BCHP_DECODE_CPUDMEM2_0_REG_START                   0x00058000
+#define BCHP_DECODE_CPUDMEM2_0_REG_END                     0x0005fffc
+#define BCHP_DECODE_IP_SHIM_0_REG_START                    0x00060000
+#define BCHP_DECODE_IP_SHIM_0_REG_END                      0x00060084
+#define BCHP_AVD_CACHE_0_REG_START                         0x00062000
+#define BCHP_AVD_CACHE_0_REG_END                           0x0006203c
+#define BCHP_ILS_REGS_0_REG_START                          0x00070000
+#define BCHP_ILS_REGS_0_REG_END                            0x0007007c
+#define BCHP_ILS_SCALE_ADDR_0_REG_START                    0x00070100
+#define BCHP_ILS_SCALE_ADDR_0_REG_END                      0x0007010c
+#define BCHP_ILS_SPSCALE_FILL_0_REG_START                  0x00070180
+#define BCHP_ILS_SPSCALE_FILL_0_REG_END                    0x00070180
+#define BCHP_ILS_MVSCALE_0_REG_START                       0x00070200
+#define BCHP_ILS_MVSCALE_0_REG_END                         0x0007038c
+#define BCHP_SVD_INTR2_0_REG_START                         0x00080000
+#define BCHP_SVD_INTR2_0_REG_END                           0x0008002c
+#define BCHP_SVD_RGR_0_REG_START                           0x00080400
+#define BCHP_SVD_RGR_0_REG_END                             0x00080410
+#define BCHP_BLD_DECODE_RBNODE_REGS_0_REG_START            0x00100000
+#define BCHP_BLD_DECODE_RBNODE_REGS_0_REG_END              0x0010007c
+#define BCHP_BLD_DECODE_MAIN_0_REG_START                   0x00100100
+#define BCHP_BLD_DECODE_MAIN_0_REG_END                     0x001001fc
+#define BCHP_BLD_SDRAM_DEBUG_0_REG_START                   0x00100200
+#define BCHP_BLD_SDRAM_DEBUG_0_REG_END                     0x0010027c
+#define BCHP_BLD_DECODE_MCOM_0_REG_START                   0x00100300
+#define BCHP_BLD_DECODE_MCOM_0_REG_END                     0x0010031c
+#define BCHP_BLD_DECODE_SPRE_0_REG_START                   0x00100320
+#define BCHP_BLD_DECODE_SPRE_0_REG_END                     0x0010033c
+#define BCHP_BLD_DECODE_WPRD_0_REG_START                   0x00100340
+#define BCHP_BLD_DECODE_WPRD_0_REG_END                     0x0010035c
+#define BCHP_BLD_DECODE_DQNT_0_REG_START                   0x00100400
+#define BCHP_BLD_DECODE_DQNT_0_REG_END                     0x0010045c
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_START               0x00100500
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_END                 0x0010057c
+#define BCHP_BLD_DECODE_VP8_XFRM_0_REG_START               0x00100600
+#define BCHP_BLD_DECODE_VP8_XFRM_0_REG_END                 0x0010060c
+#define BCHP_BLD_DECODE_XFRM_0_REG_START                   0x00100700
+#define BCHP_BLD_DECODE_XFRM_0_REG_END                     0x0010071c
+#define BCHP_BLD_DECODE_DBLK_0_REG_START                   0x00100720
+#define BCHP_BLD_DECODE_DBLK_0_REG_END                     0x0010073c
+#define BCHP_BLD_DECODE_MB_0_REG_START                     0x00100740
+#define BCHP_BLD_DECODE_MB_0_REG_END                       0x0010075c
+#define BCHP_BLD_REG_CABAC2BINS_0_REG_START                0x00100b00
+#define BCHP_BLD_REG_CABAC2BINS_0_REG_END                  0x00100bfc
+#define BCHP_BLD_DECODE_SINT_0_REG_START                   0x00100c00
+#define BCHP_BLD_DECODE_SINT_0_REG_END                     0x00100dfc
+#define BCHP_BLD_DECODE_RVC_0_REG_START                    0x00100e00
+#define BCHP_BLD_DECODE_RVC_0_REG_END                      0x00100efc
+#define BCHP_BLD_DECODE_CPUREGS_0_REG_START                0x00100f00
+#define BCHP_BLD_DECODE_CPUREGS_0_REG_END                  0x00100f7c
+#define BCHP_BLD_DECODE_CPUREGS2_0_REG_START               0x00100f80
+#define BCHP_BLD_DECODE_CPUREGS2_0_REG_END                 0x00100ffc
+#define BCHP_BLD_DECODE_CPUDMA_0_REG_START                 0x00101800
+#define BCHP_BLD_DECODE_CPUDMA_0_REG_END                   0x001018fc
+#define BCHP_BLD_DECODE_DMAMEM_0_REG_START                 0x00101a00
+#define BCHP_BLD_DECODE_DMAMEM_0_REG_END                   0x001021fc
+#define BCHP_BLD_REG_CABAC2BINS2_0_REG_START               0x00102400
+#define BCHP_BLD_REG_CABAC2BINS2_0_REG_END                 0x001027fc
+#define BCHP_BLD_DECODE_WPTBL_0_REG_START                  0x00103000
+#define BCHP_BLD_DECODE_WPTBL_0_REG_END                    0x001031fc
+#define BCHP_BLD_DECODE_SINT_OLOOP_0_REG_START             0x0010cc00
+#define BCHP_BLD_DECODE_SINT_OLOOP_0_REG_END               0x0010ccfc
+#define BCHP_BLD_DECODE_SD_0_REG_START                     0x00140800
+#define BCHP_BLD_DECODE_SD_0_REG_END                       0x00140ffc
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS_0_REG_START         0x00141000
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS_0_REG_END           0x0014107c
+#define BCHP_BLD_DECODE_CPUCORE_0_REG_START                0x00144000
+#define BCHP_BLD_DECODE_CPUCORE_0_REG_END                  0x00144ffc
+#define BCHP_BLD_DECODE_CPUAUX_0_REG_START                 0x00145000
+#define BCHP_BLD_DECODE_CPUAUX_0_REG_END                   0x00145ffc
+#define BCHP_BLD_DECODE_CPUIMEM_0_REG_START                0x00146000
+#define BCHP_BLD_DECODE_CPUIMEM_0_REG_END                  0x00147ffc
+#define BCHP_BLD_DECODE_CPUDMEM_0_REG_START                0x00148000
+#define BCHP_BLD_DECODE_CPUDMEM_0_REG_END                  0x0014fffc
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS2_0_REG_START        0x00151000
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS2_0_REG_END          0x0015107c
+#define BCHP_BLD_DECODE_CPUDMA2_0_REG_START                0x00151800
+#define BCHP_BLD_DECODE_CPUDMA2_0_REG_END                  0x001518fc
+#define BCHP_BLD_DECODE_DMAMEM2_0_REG_START                0x00151a00
+#define BCHP_BLD_DECODE_DMAMEM2_0_REG_END                  0x001521fc
+#define BCHP_BLD_DECODE_CPUCORE2_0_REG_START               0x00154000
+#define BCHP_BLD_DECODE_CPUCORE2_0_REG_END                 0x00154ffc
+#define BCHP_BLD_DECODE_CPUAUX2_0_REG_START                0x00155000
+#define BCHP_BLD_DECODE_CPUAUX2_0_REG_END                  0x00155ffc
+#define BCHP_BLD_DECODE_CPUIMEM2_0_REG_START               0x00156000
+#define BCHP_BLD_DECODE_CPUIMEM2_0_REG_END                 0x00157ffc
+#define BCHP_BLD_DECODE_CPUDMEM2_0_REG_START               0x00158000
+#define BCHP_BLD_DECODE_CPUDMEM2_0_REG_END                 0x0015fffc
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_START                0x00160000
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_END                  0x00160084
+#define BCHP_BLD_AVD_CACHE_0_REG_START                     0x00162000
+#define BCHP_BLD_AVD_CACHE_0_REG_END                       0x0016203c
+#define BCHP_VICH_0_REG_START                              0x00170000
+#define BCHP_VICH_0_REG_END                                0x0017008b
+#define BCHP_SATA_GRB_REG_START                            0x00180000
+#define BCHP_SATA_GRB_REG_END                              0x0018000c
+#define BCHP_SATA_TOP_CTRL_REG_START                       0x00180020
+#define BCHP_SATA_TOP_CTRL_REG_END                         0x00180038
+#define BCHP_SATA3_INTR2_REG_START                         0x00180080
+#define BCHP_SATA3_INTR2_REG_END                           0x001800ac
+#define BCHP_SATA_AHCI_GHC_REG_START                       0x00181000
+#define BCHP_SATA_AHCI_GHC_REG_END                         0x00181028
+#define BCHP_SATA_GLOBAL_RESERVED_REG_START                0x0018102c
+#define BCHP_SATA_GLOBAL_RESERVED_REG_END                  0x0018109c
+#define BCHP_SATA_PORT0_AHCI_S1_REG_START                  0x00181100
+#define BCHP_SATA_PORT0_AHCI_S1_REG_END                    0x0018111c
+#define BCHP_SATA_PORT0_AHCI_S2_REG_START                  0x00181120
+#define BCHP_SATA_PORT0_AHCI_S2_REG_END                    0x00181134
+#define BCHP_SATA_PORT0_AHCI_S3_REG_START                  0x00181138
+#define BCHP_SATA_PORT0_AHCI_S3_REG_END                    0x0018117c
+#define BCHP_SATA_PORT1_AHCI_S1_REG_START                  0x00181180
+#define BCHP_SATA_PORT1_AHCI_S1_REG_END                    0x0018119c
+#define BCHP_SATA_PORT1_AHCI_S2_REG_START                  0x001811a0
+#define BCHP_SATA_PORT1_AHCI_S2_REG_END                    0x001811b4
+#define BCHP_SATA_PORT1_AHCI_S3_REG_START                  0x001811b8
+#define BCHP_SATA_PORT1_AHCI_S3_REG_END                    0x001811fc
+#define BCHP_SATA_AHCI_PCICFG_REG_START                    0x00181600
+#define BCHP_SATA_AHCI_PCICFG_REG_END                      0x00181664
+#define BCHP_SATA_PORT0_CTRL_REG_START                     0x00181700
+#define BCHP_SATA_PORT0_CTRL_REG_END                       0x00181730
+#define BCHP_SATA_PORT0_CJPAT_REG_START                    0x00181740
+#define BCHP_SATA_PORT0_CJPAT_REG_END                      0x00181764
+#define BCHP_SATA_PORT1_CTRL_REG_START                     0x00181780
+#define BCHP_SATA_PORT1_CTRL_REG_END                       0x001817b0
+#define BCHP_SATA_PORT1_CJPAT_REG_START                    0x001817c0
+#define BCHP_SATA_PORT1_CJPAT_REG_END                      0x001817e4
+#define BCHP_SATA_LEG_PCICFG_REG_START                     0x00181800
+#define BCHP_SATA_LEG_PCICFG_REG_END                       0x00181880
+#define BCHP_SATA_PORT0_LEG_S1_REG_START                   0x00181900
+#define BCHP_SATA_PORT0_LEG_S1_REG_END                     0x00181934
+#define BCHP_SATA_PORT0_LEG_S2_REG_START                   0x00181940
+#define BCHP_SATA_PORT0_LEG_S2_REG_END                     0x00181954
+#define BCHP_SATA_PORT0_LEG_S3_REG_START                   0x00181958
+#define BCHP_SATA_PORT0_LEG_S3_REG_END                     0x00181998
+#define BCHP_SATA_PORT1_LEG_S1_REG_START                   0x00181a00
+#define BCHP_SATA_PORT1_LEG_S1_REG_END                     0x00181a34
+#define BCHP_SATA_PORT1_LEG_S2_REG_START                   0x00181a40
+#define BCHP_SATA_PORT1_LEG_S2_REG_END                     0x00181a54
+#define BCHP_SATA_PORT1_LEG_S3_REG_START                   0x00181a58
+#define BCHP_SATA_PORT1_LEG_S3_REG_END                     0x00181a98
+#define BCHP_DATA_MEM_REG_START                            0x00200000
+#define BCHP_DATA_MEM_REG_END                              0x0023fffc
+#define BCHP_CNTL_MEM_REG_START                            0x00240000
+#define BCHP_CNTL_MEM_REG_END                              0x0025fffc
+#define BCHP_MOCA_DMA_Channel0_REG_START                   0x00280000
+#define BCHP_MOCA_DMA_Channel0_REG_END                     0x0028000c
+#define BCHP_MOCA_DMA_Channel1_REG_START                   0x00280010
+#define BCHP_MOCA_DMA_Channel1_REG_END                     0x0028001c
+#define BCHP_MOCA_DMA_Channel2_REG_START                   0x00280020
+#define BCHP_MOCA_DMA_Channel2_REG_END                     0x0028002c
+#define BCHP_MOCA_DMA_Channel3_REG_START                   0x00280030
+#define BCHP_MOCA_DMA_Channel3_REG_END                     0x0028003c
+#define BCHP_MOCA_DMA_Channel4_REG_START                   0x00280040
+#define BCHP_MOCA_DMA_Channel4_REG_END                     0x0028004c
+#define BCHP_MOCA_DMA_Channel5_REG_START                   0x00280050
+#define BCHP_MOCA_DMA_Channel5_REG_END                     0x0028005c
+#define BCHP_MOCA_DMA_Channel6_REG_START                   0x00280060
+#define BCHP_MOCA_DMA_Channel6_REG_END                     0x0028006c
+#define BCHP_MOCA_MAC_REG_START                            0x00280400
+#define BCHP_MOCA_MAC_REG_END                              0x00280480
+#define BCHP_MOCA_PHY_REG_START                            0x00288000
+#define BCHP_MOCA_PHY_REG_END                              0x0028a9fc
+#define BCHP_MOCA_TRX_REG_START                            0x0028c000
+#define BCHP_MOCA_TRX_REG_END                              0x0028c0d0
+#define BCHP_MOCA_GMII_REG_START                           0x00290000
+#define BCHP_MOCA_GMII_REG_END                             0x00290058
+#define BCHP_MOCA_DMA_Channel_rx_REG_START                 0x00290400
+#define BCHP_MOCA_DMA_Channel_rx_REG_END                   0x0029040c
+#define BCHP_MOCA_DMA_Channel_tx_REG_START                 0x00290410
+#define BCHP_MOCA_DMA_Channel_tx_REG_END                   0x0029041c
+#define BCHP_MOCA_ECL_REG_START                            0x00290800
+#define BCHP_MOCA_ECL_REG_END                              0x00290848
+#define BCHP_MOCA_PRI_REG_START                            0x00292000
+#define BCHP_MOCA_PRI_REG_END                              0x0029207c
+#define BCHP_MOCA_NID_REG_START                            0x00294000
+#define BCHP_MOCA_NID_REG_END                              0x002943fc
+#define BCHP_MOCA_TIMER_0_REG_START                        0x002a0000
+#define BCHP_MOCA_TIMER_0_REG_END                          0x002a0010
+#define BCHP_MOCA_TIMER_1_REG_START                        0x002a0020
+#define BCHP_MOCA_TIMER_1_REG_END                          0x002a0030
+#define BCHP_MOCA_TIMER_2_REG_START                        0x002a0040
+#define BCHP_MOCA_TIMER_2_REG_END                          0x002a0050
+#define BCHP_MOCA_GPIO_REG_START                           0x002a1000
+#define BCHP_MOCA_GPIO_REG_END                             0x002a1018
+#define BCHP_MOCA_EXTRAS_REG_START                         0x002a1400
+#define BCHP_MOCA_EXTRAS_REG_END                           0x002a1494
+#define BCHP_MOCA_HOSTM2M_REG_START                        0x002a2000
+#define BCHP_MOCA_HOSTM2M_REG_END                          0x002a200c
+#define BCHP_MOCA_HOSTMISC_REG_START                       0x002a2040
+#define BCHP_MOCA_HOSTMISC_REG_END                         0x002a2064
+#define BCHP_MOCA_L2_REG_START                             0x002a2080
+#define BCHP_MOCA_L2_REG_END                               0x002a20ac
+#define BCHP_MOCA_GR_BRIDGE_REG_START                      0x002a20c0
+#define BCHP_MOCA_GR_BRIDGE_REG_END                        0x002a20cc
+#define BCHP_MOCA_HOSTMISC_MMP_REG_START                   0x002a2100
+#define BCHP_MOCA_HOSTMISC_MMP_REG_END                     0x002a212c
+#define BCHP_BSP_CMDBUF_REG_START                          0x00329800
+#define BCHP_BSP_CMDBUF_REG_END                            0x00329ffc
+#define BCHP_BSP_GLB_CONTROL_REG_START                     0x0032b000
+#define BCHP_BSP_GLB_CONTROL_REG_END                       0x0032b098
+#define BCHP_BSP_PKL_REG_START                             0x0032b300
+#define BCHP_BSP_PKL_REG_END                               0x0032b37c
+#define BCHP_BSP_INST_PATCH_CTRL_REG_START                 0x0032b400
+#define BCHP_BSP_INST_PATCH_CTRL_REG_END                   0x0032b404
+#define BCHP_BSP_CONTROL_INTR2_REG_START                   0x0032b800
+#define BCHP_BSP_CONTROL_INTR2_REG_END                     0x0032b82c
+#define BCHP_BSP_INST_PATCHRAM_REG_START                   0x0032c000
+#define BCHP_BSP_INST_PATCHRAM_REG_END                     0x0032fffc
+#define BCHP_XPT_SECURITY_REG_START                        0x00360000
+#define BCHP_XPT_SECURITY_REG_END                          0x0036fffc
+#define BCHP_MMSCRAM_REG_START                             0x00370000
+#define BCHP_MMSCRAM_REG_END                               0x00371ffc
+#define BCHP_MEM_DMA_SECURE_REG_START                      0x00372000
+#define BCHP_MEM_DMA_SECURE_REG_END                        0x0037200c
+#define BCHP_SECTOP_GRB_REG_START                          0x00374000
+#define BCHP_SECTOP_GRB_REG_END                            0x0037400c
+#define BCHP_JTAG_OTP_REG_START                            0x00374100
+#define BCHP_JTAG_OTP_REG_END                              0x00374138
+#define BCHP_MEM_DMA_0_REG_START                           0x00374200
+#define BCHP_MEM_DMA_0_REG_END                             0x00374224
+#define BCHP_XPT_SECURITY_NS_REG_START                     0x00374300
+#define BCHP_XPT_SECURITY_NS_REG_END                       0x00374310
+#define BCHP_MEMC_GEN_0_REG_START                          0x003b0000
+#define BCHP_MEMC_GEN_0_REG_END                            0x003b04f4
+#define BCHP_MEMC_ARB_0_REG_START                          0x003b1000
+#define BCHP_MEMC_ARB_0_REG_END                            0x003b1244
+#define BCHP_MEMC_DDR_0_REG_START                          0x003b2000
+#define BCHP_MEMC_DDR_0_REG_END                            0x003b22fc
+#define BCHP_MEMC_L2_0_REG_START                           0x003b3000
+#define BCHP_MEMC_L2_0_REG_END                             0x003b302c
+#define BCHP_MEMC_L2_1_0_REG_START                         0x003b3800
+#define BCHP_MEMC_L2_1_0_REG_END                           0x003b382c
+#define BCHP_MEMC_RGRB_0_REG_START                         0x003b4000
+#define BCHP_MEMC_RGRB_0_REG_END                           0x003b4010
+#define BCHP_MEMC_MISC_0_REG_START                         0x003b5000
+#define BCHP_MEMC_MISC_0_REG_END                           0x003b5010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_START            0x003b6000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_END              0x003b60c4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_START             0x003b6200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_END               0x003b63b0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_REG_START             0x003b6400
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_REG_END               0x003b65b0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_START         0x003b8000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_END           0x003b8138
+#define BCHP_S_MEMC_0_REG_START                            0x003ba000
+#define BCHP_S_MEMC_0_REG_END                              0x003ba220
+#define BCHP_SUN_GISB_ARB_REG_START                        0x00400000
+#define BCHP_SUN_GISB_ARB_REG_END                          0x004000d8
+#define BCHP_SUN_RGR_REG_START                             0x00400400
+#define BCHP_SUN_RGR_REG_END                               0x00400410
+#define BCHP_SUN_RG_REG_START                              0x00400800
+#define BCHP_SUN_RG_REG_END                                0x0040080c
+#define BCHP_TPCAP_REG_START                               0x00400c00
+#define BCHP_TPCAP_REG_END                                 0x00400c84
+#define BCHP_SUN_L2_REG_START                              0x00403000
+#define BCHP_SUN_L2_REG_END                                0x0040302c
+#define BCHP_SM_L2_REG_START                               0x00403400
+#define BCHP_SM_L2_REG_END                                 0x0040342c
+#define BCHP_SM_REG_START                                  0x00403800
+#define BCHP_SM_REG_END                                    0x00403824
+#define BCHP_SM_FAST_REG_START                             0x00403c00
+#define BCHP_SM_FAST_REG_END                               0x00403c18
+#define BCHP_SUN_TOP_CTRL_REG_START                        0x00404000
+#define BCHP_SUN_TOP_CTRL_REG_END                          0x00404518
+#define BCHP_IRB_REG_START                                 0x00406000
+#define BCHP_IRB_REG_END                                   0x00406138
+#define BCHP_PM_REG_START                                  0x00406180
+#define BCHP_PM_REG_END                                    0x00406188
+#define BCHP_BSCA_REG_START                                0x00406200
+#define BCHP_BSCA_REG_END                                  0x00406254
+#define BCHP_BSCB_REG_START                                0x00406280
+#define BCHP_BSCB_REG_END                                  0x004062d4
+#define BCHP_BSCC_REG_START                                0x00406300
+#define BCHP_BSCC_REG_END                                  0x00406354
+#define BCHP_BSCD_REG_START                                0x00406380
+#define BCHP_BSCD_REG_END                                  0x004063d4
+#define BCHP_PWM_REG_START                                 0x00406580
+#define BCHP_PWM_REG_END                                   0x004065a4
+#define BCHP_GIO_REG_START                                 0x00406700
+#define BCHP_GIO_REG_END                                   0x0040675c
+#define BCHP_IRQ0_REG_START                                0x00406780
+#define BCHP_IRQ0_REG_END                                  0x00406784
+#define BCHP_IRQ1_REG_START                                0x00406788
+#define BCHP_IRQ1_REG_END                                  0x0040678c
+#define BCHP_TIMER_REG_START                               0x004067c0
+#define BCHP_TIMER_REG_END                                 0x004067fc
+#define BCHP_PWMB_REG_START                                0x00406800
+#define BCHP_PWMB_REG_END                                  0x00406824
+#define BCHP_UARTA_REG_START                               0x00406900
+#define BCHP_UARTA_REG_END                                 0x0040691c
+#define BCHP_UARTB_REG_START                               0x00406940
+#define BCHP_UARTB_REG_END                                 0x0040695c
+#define BCHP_UARTC_REG_START                               0x00406980
+#define BCHP_UARTC_REG_END                                 0x0040699c
+#define BCHP_SCA_REG_START                                 0x00406a00
+#define BCHP_SCA_REG_END                                   0x00406abc
+#define BCHP_SCB_REG_START                                 0x00406ac0
+#define BCHP_SCB_REG_END                                   0x00406b7c
+#define BCHP_SCIRQ0_REG_START                              0x00406c40
+#define BCHP_SCIRQ0_REG_END                                0x00406c44
+#define BCHP_SCIRQ1_REG_START                              0x00406c48
+#define BCHP_SCIRQ1_REG_END                                0x00406c4c
+#define BCHP_UPG_AUX_INTR2_REG_START                       0x00406d00
+#define BCHP_UPG_AUX_INTR2_REG_END                         0x00406d2c
+#define BCHP_TMON_REG_START                                0x00406d80
+#define BCHP_TMON_REG_END                                  0x00406dd0
+#define BCHP_AON_CTRL_REG_START                            0x00408000
+#define BCHP_AON_CTRL_REG_END                              0x004083fc
+#define BCHP_AON_L2_REG_START                              0x00408400
+#define BCHP_AON_L2_REG_END                                0x0040842c
+#define BCHP_AON_PM_L2_REG_START                           0x00408440
+#define BCHP_AON_PM_L2_REG_END                             0x0040846c
+#define BCHP_AON_PIN_CTRL_REG_START                        0x00408500
+#define BCHP_AON_PIN_CTRL_REG_END                          0x0040851c
+#define BCHP_AON_HDMI_TX_REG_START                         0x00408600
+#define BCHP_AON_HDMI_TX_REG_END                           0x00408698
+#define BCHP_LDK_REG_START                                 0x00408800
+#define BCHP_LDK_REG_END                                   0x0040883c
+#define BCHP_PM_AON_REG_START                              0x00408840
+#define BCHP_PM_AON_REG_END                                0x00408848
+#define BCHP_ICAP_REG_START                                0x00408880
+#define BCHP_ICAP_REG_END                                  0x004088bc
+#define BCHP_KBD1_REG_START                                0x004088c0
+#define BCHP_KBD1_REG_END                                  0x004088fc
+#define BCHP_KBD2_REG_START                                0x00408900
+#define BCHP_KBD2_REG_END                                  0x0040893c
+#define BCHP_KBD3_REG_START                                0x00408940
+#define BCHP_KBD3_REG_END                                  0x0040897c
+#define BCHP_BSCE_REG_START                                0x00408980
+#define BCHP_BSCE_REG_END                                  0x004089d4
+#define BCHP_MSPI_REG_START                                0x00408a00
+#define BCHP_MSPI_REG_END                                  0x00408b7c
+#define BCHP_IRQ0_AON_REG_START                            0x00408b80
+#define BCHP_IRQ0_AON_REG_END                              0x00408b84
+#define BCHP_IRQ1_AON_REG_START                            0x00408b88
+#define BCHP_IRQ1_AON_REG_END                              0x00408b8c
+#define BCHP_GIO_AON_REG_START                             0x00408c00
+#define BCHP_GIO_AON_REG_END                               0x00408c5c
+#define BCHP_BICAP_REG_START                               0x00408e00
+#define BCHP_BICAP_REG_END                                 0x00408e38
+#define BCHP_UPG_AUX_AON_INTR2_REG_START                   0x00408e40
+#define BCHP_UPG_AUX_AON_INTR2_REG_END                     0x00408e6c
+#define BCHP_WKTMR_REG_START                               0x00408e80
+#define BCHP_WKTMR_REG_END                                 0x00408e90
+#define BCHP_SYS_GISB_ARB_SEC_REG_START                    0x0040e000
+#define BCHP_SYS_GISB_ARB_SEC_REG_END                      0x0040e0b4
+#define BCHP_SYS_TOP_CTRL_SEC_REG_START                    0x0040e700
+#define BCHP_SYS_TOP_CTRL_SEC_REG_END                      0x0040e704
+#define BCHP_AON_CTRL_SECURE_REG_START                     0x0040e800
+#define BCHP_AON_CTRL_SECURE_REG_END                       0x0040e87c
+#define BCHP_EBI_REG_START                                 0x00410800
+#define BCHP_EBI_REG_END                                   0x00410bfc
+#define BCHP_HIF_INTR2_REG_START                           0x00411000
+#define BCHP_HIF_INTR2_REG_END                             0x0041102c
+#define BCHP_IPI0_INTR2_REG_START                          0x00411100
+#define BCHP_IPI0_INTR2_REG_END                            0x0041112c
+#define BCHP_IPI1_INTR2_REG_START                          0x00411200
+#define BCHP_IPI1_INTR2_REG_END                            0x0041122c
+#define BCHP_HIF_CPU_INTR1_REG_START                       0x00411400
+#define BCHP_HIF_CPU_INTR1_REG_END                         0x0041142c
+#define BCHP_HIF_CPU_TP1_INTR1_REG_START                   0x00411600
+#define BCHP_HIF_CPU_TP1_INTR1_REG_END                     0x0041162c
+#define BCHP_HIF_RGR_REG_START                             0x00411800
+#define BCHP_HIF_RGR_REG_END                               0x00411810
+#define BCHP_HIF_SPI_INTR2_REG_START                       0x00411d00
+#define BCHP_HIF_SPI_INTR2_REG_END                         0x00411d2c
+#define BCHP_HIF_TOP_CTRL_REG_START                        0x00412400
+#define BCHP_HIF_TOP_CTRL_REG_END                          0x00412418
+#define BCHP_NAND_REG_START                                0x00412800
+#define BCHP_NAND_REG_END                                  0x00412bfc
+#define BCHP_BSPI_REG_START                                0x00413000
+#define BCHP_BSPI_REG_END                                  0x0041304c
+#define BCHP_BSPI_RAF_REG_START                            0x00413100
+#define BCHP_BSPI_RAF_REG_END                              0x00413120
+#define BCHP_HIF_MSPI_REG_START                            0x00413200
+#define BCHP_HIF_MSPI_REG_END                              0x00413384
+#define BCHP_SDIO_0_HOST_REG_START                         0x00413500
+#define BCHP_SDIO_0_HOST_REG_END                           0x004135fc
+#define BCHP_SDIO_0_CFG_REG_START                          0x00413600
+#define BCHP_SDIO_0_CFG_REG_END                            0x004136fc
+#define BCHP_MICH_REG_START                                0x00414000
+#define BCHP_MICH_REG_END                                  0x00414000
+#define BCHP_HIF_SECURE_CTRL_REG_START                     0x00414100
+#define BCHP_HIF_SECURE_CTRL_REG_END                       0x00414100
+#define BCHP_HIF_SECURE_BSPI_REG_START                     0x00414200
+#define BCHP_HIF_SECURE_BSPI_REG_END                       0x00414200
+#define BCHP_HIF_SECURE_LR_SPI_REG_START                   0x00414300
+#define BCHP_HIF_SECURE_LR_SPI_REG_END                     0x00414300
+#define BCHP_NAND_SECURE_REG_START                         0x00414400
+#define BCHP_NAND_SECURE_REG_END                           0x00414400
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_START        0x00414800
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_END          0x00414800
+#define BCHP_UHFR_REG_START                                0x00416000
+#define BCHP_UHFR_REG_END                                  0x004160f8
+#define BCHP_UHFR_INTR2_REG_START                          0x00416200
+#define BCHP_UHFR_INTR2_REG_END                            0x0041622c
+#define BCHP_UHFR_GR_BRIDGE_REG_START                      0x00416300
+#define BCHP_UHFR_GR_BRIDGE_REG_END                        0x0041630c
+#define BCHP_CLKGEN_REG_START                              0x00420000
+#define BCHP_CLKGEN_REG_END                                0x0042047c
+#define BCHP_VCXO_RM_REG_START                             0x00422000
+#define BCHP_VCXO_RM_REG_END                               0x0042202c
+#define BCHP_AVS_HW_MNTR_REG_START                         0x00422800
+#define BCHP_AVS_HW_MNTR_REG_END                           0x00422874
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_START                 0x00422900
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_END                   0x0042291c
+#define BCHP_AVS_ASB_REGISTERS_REG_START                   0x00422a00
+#define BCHP_AVS_ASB_REGISTERS_REG_END                     0x00422a18
+#define BCHP_AVS_RO_REGISTERS_0_REG_START                  0x00422b00
+#define BCHP_AVS_RO_REGISTERS_0_REG_END                    0x00422bdc
+#define BCHP_AVS_RO_REGISTERS_1_REG_START                  0x00422c00
+#define BCHP_AVS_RO_REGISTERS_1_REG_END                    0x00422ca4
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_START                0x00422d00
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_END                  0x00422de4
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_START                0x00422e00
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_END                  0x00422ee4
+#define BCHP_CLKGEN_INTR2_REG_START                        0x00422f00
+#define BCHP_CLKGEN_INTR2_REG_END                          0x00422f2c
+#define BCHP_CLKGEN_GR_REG_START                           0x00423300
+#define BCHP_CLKGEN_GR_REG_END                             0x0042330c
+#define BCHP_GENET_0_SYS_REG_START                         0x00430000
+#define BCHP_GENET_0_SYS_REG_END                           0x0043000c
+#define BCHP_GENET_0_GR_BRIDGE_REG_START                   0x00430040
+#define BCHP_GENET_0_GR_BRIDGE_REG_END                     0x0043004c
+#define BCHP_GENET_0_EXT_REG_START                         0x00430080
+#define BCHP_GENET_0_EXT_REG_END                           0x00430098
+#define BCHP_GENET_0_INTRL2_0_REG_START                    0x00430200
+#define BCHP_GENET_0_INTRL2_0_REG_END                      0x0043022c
+#define BCHP_GENET_0_INTRL2_1_REG_START                    0x00430240
+#define BCHP_GENET_0_INTRL2_1_REG_END                      0x0043026c
+#define BCHP_GENET_0_RBUF_REG_START                        0x00430300
+#define BCHP_GENET_0_RBUF_REG_END                          0x004303ec
+#define BCHP_GENET_0_TBUF_REG_START                        0x00430600
+#define BCHP_GENET_0_TBUF_REG_END                          0x00430628
+#define BCHP_GENET_0_UMAC_REG_START                        0x00430800
+#define BCHP_GENET_0_UMAC_REG_END                          0x00430ed8
+#define BCHP_GENET_0_HFB_REG_START                         0x00431000
+#define BCHP_GENET_0_HFB_REG_END                           0x00432010
+#define BCHP_GENET_0_RDMA_REG_START                        0x00433000
+#define BCHP_GENET_0_RDMA_REG_END                          0x00433cb4
+#define BCHP_GENET_0_TDMA_REG_START                        0x00434000
+#define BCHP_GENET_0_TDMA_REG_END                          0x00434c88
+#define BCHP_GENET_1_SYS_REG_START                         0x00438000
+#define BCHP_GENET_1_SYS_REG_END                           0x0043800c
+#define BCHP_GENET_1_GR_BRIDGE_REG_START                   0x00438040
+#define BCHP_GENET_1_GR_BRIDGE_REG_END                     0x0043804c
+#define BCHP_GENET_1_EXT_REG_START                         0x00438080
+#define BCHP_GENET_1_EXT_REG_END                           0x00438098
+#define BCHP_GENET_1_INTRL2_0_REG_START                    0x00438200
+#define BCHP_GENET_1_INTRL2_0_REG_END                      0x0043822c
+#define BCHP_GENET_1_INTRL2_1_REG_START                    0x00438240
+#define BCHP_GENET_1_INTRL2_1_REG_END                      0x0043826c
+#define BCHP_GENET_1_RBUF_REG_START                        0x00438300
+#define BCHP_GENET_1_RBUF_REG_END                          0x004383ec
+#define BCHP_GENET_1_TBUF_REG_START                        0x00438600
+#define BCHP_GENET_1_TBUF_REG_END                          0x00438628
+#define BCHP_GENET_1_UMAC_REG_START                        0x00438800
+#define BCHP_GENET_1_UMAC_REG_END                          0x00438ed8
+#define BCHP_GENET_1_HFB_REG_START                         0x00439000
+#define BCHP_GENET_1_HFB_REG_END                           0x0043a010
+#define BCHP_GENET_1_RDMA_REG_START                        0x0043b000
+#define BCHP_GENET_1_RDMA_REG_END                          0x0043bcb4
+#define BCHP_GENET_1_TDMA_REG_START                        0x0043c000
+#define BCHP_GENET_1_TDMA_REG_END                          0x0043cc88
+#define BCHP_SID_REG_START                                 0x00440100
+#define BCHP_SID_REG_END                                   0x0044019c
+#define BCHP_SID_RLE_REG_START                             0x00440300
+#define BCHP_SID_RLE_REG_END                               0x0044039c
+#define BCHP_SID_DQ_REG_START                              0x00440400
+#define BCHP_SID_DQ_REG_END                                0x004404bc
+#define BCHP_SID_STRM_REG_START                            0x00440800
+#define BCHP_SID_STRM_REG_END                              0x0044087c
+#define BCHP_SID_OUTPUT_REG_START                          0x00440c00
+#define BCHP_SID_OUTPUT_REG_END                            0x00440c40
+#define BCHP_SID_ARC_REG_START                             0x00440f00
+#define BCHP_SID_ARC_REG_END                               0x00440f3c
+#define BCHP_SID_ARCDMA_REG_START                          0x00441800
+#define BCHP_SID_ARCDMA_REG_END                            0x00441840
+#define BCHP_SID_DMARAM_REG_START                          0x00441a00
+#define BCHP_SID_DMARAM_REG_END                            0x00441bfc
+#define BCHP_SID_PEEK_BITS_REG_START                       0x00442b00
+#define BCHP_SID_PEEK_BITS_REG_END                         0x00442b3c
+#define BCHP_SID_EXTRACT_BITS_REG_START                    0x00442b40
+#define BCHP_SID_EXTRACT_BITS_REG_END                      0x00442b7c
+#define BCHP_SID_HUFF_SYMB_REG_START                       0x00443000
+#define BCHP_SID_HUFF_SYMB_REG_END                         0x004437fc
+#define BCHP_SID_HUFF_CODE_REG_START                       0x00443900
+#define BCHP_SID_HUFF_CODE_REG_END                         0x004439fc
+#define BCHP_SID_SYMB_REG_START                            0x00443a00
+#define BCHP_SID_SYMB_REG_END                              0x00443a10
+#define BCHP_SID_SYMB_JPEG_REG_START                       0x00443a80
+#define BCHP_SID_SYMB_JPEG_REG_END                         0x00443a8c
+#define BCHP_SID_BIGRAM_REG_START                          0x00448000
+#define BCHP_SID_BIGRAM_REG_END                            0x0044fffc
+#define BCHP_SID_ARC_DBG_REG_START                         0x00451000
+#define BCHP_SID_ARC_DBG_REG_END                           0x00451010
+#define BCHP_SID_ARC_CORE_REG_START                        0x00455000
+#define BCHP_SID_ARC_CORE_REG_END                          0x00455014
+#define BCHP_M2MC_REG_START                                0x00460000
+#define BCHP_M2MC_REG_END                                  0x004607fc
+#define BCHP_V3D_CTL_REG_START                             0x00461000
+#define BCHP_V3D_CTL_REG_END                               0x00461040
+#define BCHP_V3D_CLE_REG_START                             0x00461100
+#define BCHP_V3D_CLE_REG_END                               0x00461138
+#define BCHP_V3D_PTB_REG_START                             0x00461300
+#define BCHP_V3D_PTB_REG_END                               0x00461310
+#define BCHP_V3D_QPS_REG_START                             0x00461400
+#define BCHP_V3D_QPS_REG_END                               0x0046143c
+#define BCHP_V3D_VPM_REG_START                             0x00461500
+#define BCHP_V3D_VPM_REG_END                               0x00461504
+#define BCHP_V3D_PCTR_REG_START                            0x00461600
+#define BCHP_V3D_PCTR_REG_END                              0x004616fc
+#define BCHP_V3D_GCA_REG_START                             0x00461a00
+#define BCHP_V3D_GCA_REG_END                               0x00461a54
+#define BCHP_V3D_DBG_REG_START                             0x00461e00
+#define BCHP_V3D_DBG_REG_END                               0x00461f20
+#define BCHP_GFX_L2_REG_START                              0x00463000
+#define BCHP_GFX_L2_REG_END                                0x0046302c
+#define BCHP_GFX_GR_REG_START                              0x00464000
+#define BCHP_GFX_GR_REG_END                                0x0046400c
+#define BCHP_SICH_REG_START                                0x00468000
+#define BCHP_SICH_REG_END                                  0x0046803c
+#define BCHP_USB_CAPS_REG_START                            0x00480000
+#define BCHP_USB_CAPS_REG_END                              0x0048002c
+#define BCHP_USB_GR_BRIDGE_REG_START                       0x00480100
+#define BCHP_USB_GR_BRIDGE_REG_END                         0x0048010c
+#define BCHP_USB_INTR2_REG_START                           0x00480180
+#define BCHP_USB_INTR2_REG_END                             0x004801ac
+#define BCHP_USB_CTRL_REG_START                            0x00480200
+#define BCHP_USB_CTRL_REG_END                              0x00480238
+#define BCHP_USB_EHCI_REG_START                            0x00480300
+#define BCHP_USB_EHCI_REG_END                              0x004803a4
+#define BCHP_USB_OHCI_REG_START                            0x00480400
+#define BCHP_USB_OHCI_REG_END                              0x00480454
+#define BCHP_USB_EHCI1_REG_START                           0x00480500
+#define BCHP_USB_EHCI1_REG_END                             0x004805a4
+#define BCHP_USB_OHCI1_REG_START                           0x00480600
+#define BCHP_USB_OHCI1_REG_END                             0x00480654
+#define BCHP_USB_OTG_REG_START                             0x00482000
+#define BCHP_USB_OTG_REG_END                               0x00482e00
+#define BCHP_USB1_CAPS_REG_START                           0x00490000
+#define BCHP_USB1_CAPS_REG_END                             0x0049002c
+#define BCHP_USB1_GR_BRIDGE_REG_START                      0x00490100
+#define BCHP_USB1_GR_BRIDGE_REG_END                        0x0049010c
+#define BCHP_USB1_INTR2_REG_START                          0x00490180
+#define BCHP_USB1_INTR2_REG_END                            0x004901ac
+#define BCHP_USB1_CTRL_REG_START                           0x00490200
+#define BCHP_USB1_CTRL_REG_END                             0x00490238
+#define BCHP_USB1_EHCI_REG_START                           0x00490300
+#define BCHP_USB1_EHCI_REG_END                             0x004903a4
+#define BCHP_USB1_OHCI_REG_START                           0x00490400
+#define BCHP_USB1_OHCI_REG_END                             0x00490454
+#define BCHP_USB1_EHCI1_REG_START                          0x00490500
+#define BCHP_USB1_EHCI1_REG_END                            0x004905a4
+#define BCHP_USB1_OHCI1_REG_START                          0x00490600
+#define BCHP_USB1_OHCI1_REG_END                            0x00490654
+#define BCHP_USB1_OTG_REG_START                            0x00492000
+#define BCHP_USB1_OTG_REG_END                              0x00492e00
+#define BCHP_BOOTROM_REG_START                             0x00500000
+#define BCHP_BOOTROM_REG_END                               0x00500ffc
+#define BCHP_MFD_0_REG_START                               0x00600000
+#define BCHP_MFD_0_REG_END                                 0x00600264
+#define BCHP_MFD_1_REG_START                               0x00600400
+#define BCHP_MFD_1_REG_END                                 0x006005fc
+#define BCHP_VFD_0_REG_START                               0x00601000
+#define BCHP_VFD_0_REG_END                                 0x006011fc
+#define BCHP_VFD_1_REG_START                               0x00601200
+#define BCHP_VFD_1_REG_END                                 0x006013fc
+#define BCHP_VFD_2_REG_START                               0x00601400
+#define BCHP_VFD_2_REG_END                                 0x006015fc
+#define BCHP_VFD_3_REG_START                               0x00601600
+#define BCHP_VFD_3_REG_END                                 0x006017fc
+#define BCHP_RDC_REG_START                                 0x00602000
+#define BCHP_RDC_REG_END                                   0x006029fc
+#define BCHP_BVNF_INTR2_0_REG_START                        0x00603000
+#define BCHP_BVNF_INTR2_0_REG_END                          0x0060302c
+#define BCHP_BVNF_INTR2_1_REG_START                        0x00603100
+#define BCHP_BVNF_INTR2_1_REG_END                          0x0060312c
+#define BCHP_BVNF_INTR2_3_REG_START                        0x00603300
+#define BCHP_BVNF_INTR2_3_REG_END                          0x0060332c
+#define BCHP_BVNF_INTR2_4_REG_START                        0x00603400
+#define BCHP_BVNF_INTR2_4_REG_END                          0x0060342c
+#define BCHP_BVNF_INTR2_5_REG_START                        0x00603500
+#define BCHP_BVNF_INTR2_5_REG_END                          0x0060352c
+#define BCHP_FMISC_REG_START                               0x00604000
+#define BCHP_FMISC_REG_END                                 0x00604020
+#define BCHP_SCL_0_REG_START                               0x00620000
+#define BCHP_SCL_0_REG_END                                 0x006203fc
+#define BCHP_SCL_1_REG_START                               0x00620400
+#define BCHP_SCL_1_REG_END                                 0x006207fc
+#define BCHP_SCL_2_REG_START                               0x00620800
+#define BCHP_SCL_2_REG_END                                 0x00620bfc
+#define BCHP_SCL_3_REG_START                               0x00620c00
+#define BCHP_SCL_3_REG_END                                 0x00620ffc
+#define BCHP_VNET_F_REG_START                              0x00622000
+#define BCHP_VNET_F_REG_END                                0x006220ac
+#define BCHP_VNET_B_REG_START                              0x00622200
+#define BCHP_VNET_B_REG_END                                0x006222bc
+#define BCHP_MMISC_REG_START                               0x00622800
+#define BCHP_MMISC_REG_END                                 0x00622820
+#define BCHP_LBOX_0_REG_START                              0x00625000
+#define BCHP_LBOX_0_REG_END                                0x00625070
+#define BCHP_LBOX_1_REG_START                              0x00625200
+#define BCHP_LBOX_1_REG_END                                0x00625270
+#define BCHP_BVNM_INTR2_0_REG_START                        0x00626000
+#define BCHP_BVNM_INTR2_0_REG_END                          0x0062602c
+#define BCHP_DNR_0_REG_START                               0x00627000
+#define BCHP_DNR_0_REG_END                                 0x006270a4
+#define BCHP_CAP_0_REG_START                               0x00640000
+#define BCHP_CAP_0_REG_END                                 0x0064007c
+#define BCHP_CAP_1_REG_START                               0x00640200
+#define BCHP_CAP_1_REG_END                                 0x0064027c
+#define BCHP_CAP_2_REG_START                               0x00640400
+#define BCHP_CAP_2_REG_END                                 0x0064047c
+#define BCHP_CAP_3_REG_START                               0x00640600
+#define BCHP_CAP_3_REG_END                                 0x0064067c
+#define BCHP_GFD_0_REG_START                               0x00641000
+#define BCHP_GFD_0_REG_END                                 0x00641228
+#define BCHP_GFD_1_REG_START                               0x00641400
+#define BCHP_GFD_1_REG_END                                 0x00641554
+#define BCHP_CMP_0_REG_START                               0x00642000
+#define BCHP_CMP_0_REG_END                                 0x006424b4
+#define BCHP_CMP_1_REG_START                               0x00642800
+#define BCHP_CMP_1_REG_END                                 0x00642cb4
+#define BCHP_TNT_CMP_0_V0_REG_START                        0x00643000
+#define BCHP_TNT_CMP_0_V0_REG_END                          0x006430a4
+#define BCHP_MASK_0_REG_START                              0x00643400
+#define BCHP_MASK_0_REG_END                                0x00643420
+#define BCHP_PEP_CMP_0_V0_REG_START                        0x00644000
+#define BCHP_PEP_CMP_0_V0_REG_END                          0x00645484
+#define BCHP_BVNB_INTR2_REG_START                          0x00646000
+#define BCHP_BVNB_INTR2_REG_END                            0x0064602c
+#define BCHP_BMISC_REG_START                               0x00646400
+#define BCHP_BMISC_REG_END                                 0x0064641c
+#define BCHP_MVP_TOP_0_REG_START                           0x00660000
+#define BCHP_MVP_TOP_0_REG_END                             0x0066002c
+#define BCHP_SIOB_0_REG_START                              0x00660200
+#define BCHP_SIOB_0_REG_END                                0x006602fc
+#define BCHP_HSCL_0_REG_START                              0x00660400
+#define BCHP_HSCL_0_REG_END                                0x006607fc
+#define BCHP_MDI_TOP_0_REG_START                           0x00662000
+#define BCHP_MDI_TOP_0_REG_END                             0x00662044
+#define BCHP_MDI_PPB_0_REG_START                           0x00662800
+#define BCHP_MDI_PPB_0_REG_END                             0x00662bfc
+#define BCHP_MDI_FCN_0_REG_START                           0x00662c00
+#define BCHP_MDI_FCN_0_REG_END                             0x00662ffc
+#define BCHP_MISC_REG_START                                0x00680000
+#define BCHP_MISC_REG_END                                  0x0068009c
+#define BCHP_IT_0_REG_START                                0x00681000
+#define BCHP_IT_0_REG_END                                  0x006817fc
+#define BCHP_IT_1_REG_START                                0x00682000
+#define BCHP_IT_1_REG_END                                  0x006827fc
+#define BCHP_VF_0_REG_START                                0x00683000
+#define BCHP_VF_0_REG_END                                  0x00683134
+#define BCHP_VF_1_REG_START                                0x00683200
+#define BCHP_VF_1_REG_END                                  0x00683334
+#define BCHP_SECAM_0_REG_START                             0x00683400
+#define BCHP_SECAM_0_REG_END                               0x00683414
+#define BCHP_SM_0_REG_START                                0x00683480
+#define BCHP_SM_0_REG_END                                  0x006834ac
+#define BCHP_SDSRC_0_REG_START                             0x00683500
+#define BCHP_SDSRC_0_REG_END                               0x0068350c
+#define BCHP_HDSRC_0_REG_START                             0x00683520
+#define BCHP_HDSRC_0_REG_END                               0x0068353c
+#define BCHP_CSC_0_REG_START                               0x00683580
+#define BCHP_CSC_0_REG_END                                 0x006835b0
+#define BCHP_CSC_1_REG_START                               0x00683600
+#define BCHP_CSC_1_REG_END                                 0x00683630
+#define BCHP_RM_0_REG_START                                0x00683680
+#define BCHP_RM_0_REG_END                                  0x006836a4
+#define BCHP_RM_1_REG_START                                0x006836c0
+#define BCHP_RM_1_REG_END                                  0x006836e4
+#define BCHP_ANA_DEBUG_0_REG_START                         0x00683700
+#define BCHP_ANA_DEBUG_0_REG_END                           0x00683744
+#define BCHP_DTRAM_0_REG_START                             0x00683800
+#define BCHP_DTRAM_0_REG_END                               0x00683c7c
+#define BCHP_DVI_DTG_0_REG_START                           0x00684000
+#define BCHP_DVI_DTG_0_REG_END                             0x00684154
+#define BCHP_DVI_CSC_0_REG_START                           0x00684200
+#define BCHP_DVI_CSC_0_REG_END                             0x00684230
+#define BCHP_DVI_DVF_0_REG_START                           0x00684300
+#define BCHP_DVI_DVF_0_REG_END                             0x00684314
+#define BCHP_DVI_DEBUG_0_REG_START                         0x00684400
+#define BCHP_DVI_DEBUG_0_REG_END                           0x00684444
+#define BCHP_ITU656_DTG_0_REG_START                        0x00684800
+#define BCHP_ITU656_DTG_0_REG_END                          0x00684954
+#define BCHP_ITU656_CSC_0_REG_START                        0x00684a00
+#define BCHP_ITU656_CSC_0_REG_END                          0x00684a30
+#define BCHP_ITU656_DVF_0_REG_START                        0x00684b00
+#define BCHP_ITU656_DVF_0_REG_END                          0x00684b14
+#define BCHP_ITU656_0_REG_START                            0x00684c00
+#define BCHP_ITU656_0_REG_END                              0x00684c20
+#define BCHP_VEC_CFG_REG_START                             0x00685000
+#define BCHP_VEC_CFG_REG_END                               0x00685100
+#define BCHP_VIDEO_ENC_INTR2_REG_START                     0x00685400
+#define BCHP_VIDEO_ENC_INTR2_REG_END                       0x0068542c
+#define BCHP_VIDEO_ENC_TPG_0_REG_START                     0x00685500
+#define BCHP_VIDEO_ENC_TPG_0_REG_END                       0x00685518
+#define BCHP_VIDEO_ENC_DECIM_0_REG_START                   0x00685600
+#define BCHP_VIDEO_ENC_DECIM_0_REG_END                     0x00685608
+#define BCHP_DVP_TVG_0_REG_START                           0x00685700
+#define BCHP_DVP_TVG_0_REG_END                             0x00685788
+#define BCHP_VBI_ENC_REG_START                             0x00686000
+#define BCHP_VBI_ENC_REG_END                               0x00686074
+#define BCHP_CCE_0_REG_START                               0x00686400
+#define BCHP_CCE_0_REG_END                                 0x00686458
+#define BCHP_CCE_1_REG_START                               0x00686500
+#define BCHP_CCE_1_REG_END                                 0x00686558
+#define BCHP_WSE_0_REG_START                               0x00686600
+#define BCHP_WSE_0_REG_END                                 0x00686614
+#define BCHP_WSE_1_REG_START                               0x00686700
+#define BCHP_WSE_1_REG_END                                 0x00686714
+#define BCHP_CGMSAE_0_REG_START                            0x00686800
+#define BCHP_CGMSAE_0_REG_END                              0x00686858
+#define BCHP_CGMSAE_1_REG_START                            0x00686900
+#define BCHP_CGMSAE_1_REG_END                              0x00686958
+#define BCHP_TTE_0_REG_START                               0x00686a00
+#define BCHP_TTE_0_REG_END                                 0x00686a28
+#define BCHP_TTE_1_REG_START                               0x00686b00
+#define BCHP_TTE_1_REG_END                                 0x00686b28
+#define BCHP_GSE_0_REG_START                               0x00686c00
+#define BCHP_GSE_0_REG_END                                 0x00686c80
+#define BCHP_GSE_1_REG_START                               0x00686d00
+#define BCHP_GSE_1_REG_END                                 0x00686d80
+#define BCHP_AMOLE_0_REG_START                             0x00686e00
+#define BCHP_AMOLE_0_REG_END                               0x00686e8c
+#define BCHP_AMOLE_1_REG_START                             0x00686f00
+#define BCHP_AMOLE_1_REG_END                               0x00686f8c
+#define BCHP_CCE_ANCIL_0_REG_START                         0x00687000
+#define BCHP_CCE_ANCIL_0_REG_END                           0x00687054
+#define BCHP_WSE_ANCIL_0_REG_START                         0x00687100
+#define BCHP_WSE_ANCIL_0_REG_END                           0x0068710c
+#define BCHP_TTE_ANCIL_0_REG_START                         0x00687200
+#define BCHP_TTE_ANCIL_0_REG_END                           0x00687228
+#define BCHP_GSE_ANCIL_0_REG_START                         0x00687300
+#define BCHP_GSE_ANCIL_0_REG_END                           0x00687380
+#define BCHP_AMOLE_ANCIL_0_REG_START                       0x00687400
+#define BCHP_AMOLE_ANCIL_0_REG_END                         0x0068748c
+#define BCHP_ANCI656_ANCIL_0_REG_START                     0x00687500
+#define BCHP_ANCI656_ANCIL_0_REG_END                       0x00687524
+#define BCHP_DVP_HT_REG_START                              0x006a0000
+#define BCHP_DVP_HT_REG_END                                0x006a00d4
+#define BCHP_HDMI_REG_START                                0x006a0800
+#define BCHP_HDMI_REG_END                                  0x006a0994
+#define BCHP_HDMI_TX_PHY_REG_START                         0x006a0a80
+#define BCHP_HDMI_TX_PHY_REG_END                           0x006a0ad8
+#define BCHP_HDMI_RM_REG_START                             0x006a0b00
+#define BCHP_HDMI_RM_REG_END                               0x006a0b2c
+#define BCHP_HDMI_TX_INTR2_REG_START                       0x006a0b40
+#define BCHP_HDMI_TX_INTR2_REG_END                         0x006a0b6c
+#define BCHP_HDMI_RAM_REG_START                            0x006a0c00
+#define BCHP_HDMI_RAM_REG_END                              0x006a0dfc
+#define BCHP_BVN_RGR_REG_START                             0x006a8000
+#define BCHP_BVN_RGR_REG_END                               0x006a8010
+#define BCHP_SDS_CG_0_REG_START                            0x00700000
+#define BCHP_SDS_CG_0_REG_END                              0x00700038
+#define BCHP_SDS_FE_0_REG_START                            0x00700080
+#define BCHP_SDS_FE_0_REG_END                              0x007000bc
+#define BCHP_SDS_AGC_0_REG_START                           0x00700100
+#define BCHP_SDS_AGC_0_REG_END                             0x00700124
+#define BCHP_SDS_BL_0_REG_START                            0x00700140
+#define BCHP_SDS_BL_0_REG_END                              0x00700160
+#define BCHP_SDS_CL_0_REG_START                            0x00700180
+#define BCHP_SDS_CL_0_REG_END                              0x007001fc
+#define BCHP_SDS_EQ_0_REG_START                            0x00700200
+#define BCHP_SDS_EQ_0_REG_END                              0x0070028c
+#define BCHP_SDS_HP_0_REG_START                            0x00700300
+#define BCHP_SDS_HP_0_REG_END                              0x007003d4
+#define BCHP_SDS_VIT_0_REG_START                           0x00700400
+#define BCHP_SDS_VIT_0_REG_END                             0x00700428
+#define BCHP_SDS_FEC_0_REG_START                           0x00700440
+#define BCHP_SDS_FEC_0_REG_END                             0x00700454
+#define BCHP_SDS_OI_0_REG_START                            0x00700480
+#define BCHP_SDS_OI_0_REG_END                              0x007004c8
+#define BCHP_SDS_SNR_0_REG_START                           0x00700500
+#define BCHP_SDS_SNR_0_REG_END                             0x00700518
+#define BCHP_SDS_BERT_0_REG_START                          0x00700540
+#define BCHP_SDS_BERT_0_REG_END                            0x0070055c
+#define BCHP_SDS_DFT_0_REG_START                           0x00700580
+#define BCHP_SDS_DFT_0_REG_END                             0x007005a8
+#define BCHP_SDS_CWC_0_REG_START                           0x00700600
+#define BCHP_SDS_CWC_0_REG_END                             0x00700694
+#define BCHP_SDS_MISC_0_REG_START                          0x00700700
+#define BCHP_SDS_MISC_0_REG_END                            0x00700798
+#define BCHP_SDS_DSEC_0_REG_START                          0x00700800
+#define BCHP_SDS_DSEC_0_REG_END                            0x007008c8
+#define BCHP_SDS_TUNER_0_REG_START                         0x00700900
+#define BCHP_SDS_TUNER_0_REG_END                           0x007009fc
+#define BCHP_SDS_INTR2_0_0_REG_START                       0x00700a00
+#define BCHP_SDS_INTR2_0_0_REG_END                         0x00700a2c
+#define BCHP_SDS_INTR2_1_0_REG_START                       0x00700b00
+#define BCHP_SDS_INTR2_1_0_REG_END                         0x00700b2c
+#define BCHP_SDS_GR_BRIDGE_0_REG_START                     0x00700c00
+#define BCHP_SDS_GR_BRIDGE_0_REG_END                       0x00700c0c
+#define BCHP_SDS_CG_1_REG_START                            0x00701000
+#define BCHP_SDS_CG_1_REG_END                              0x00701038
+#define BCHP_SDS_FE_1_REG_START                            0x00701080
+#define BCHP_SDS_FE_1_REG_END                              0x007010bc
+#define BCHP_SDS_AGC_1_REG_START                           0x00701100
+#define BCHP_SDS_AGC_1_REG_END                             0x00701124
+#define BCHP_SDS_BL_1_REG_START                            0x00701140
+#define BCHP_SDS_BL_1_REG_END                              0x00701160
+#define BCHP_SDS_CL_1_REG_START                            0x00701180
+#define BCHP_SDS_CL_1_REG_END                              0x007011fc
+#define BCHP_SDS_EQ_1_REG_START                            0x00701200
+#define BCHP_SDS_EQ_1_REG_END                              0x0070128c
+#define BCHP_SDS_HP_1_REG_START                            0x00701300
+#define BCHP_SDS_HP_1_REG_END                              0x007013d4
+#define BCHP_SDS_VIT_1_REG_START                           0x00701400
+#define BCHP_SDS_VIT_1_REG_END                             0x00701428
+#define BCHP_SDS_FEC_1_REG_START                           0x00701440
+#define BCHP_SDS_FEC_1_REG_END                             0x00701454
+#define BCHP_SDS_OI_1_REG_START                            0x00701480
+#define BCHP_SDS_OI_1_REG_END                              0x007014c8
+#define BCHP_SDS_SNR_1_REG_START                           0x00701500
+#define BCHP_SDS_SNR_1_REG_END                             0x00701518
+#define BCHP_SDS_BERT_1_REG_START                          0x00701540
+#define BCHP_SDS_BERT_1_REG_END                            0x0070155c
+#define BCHP_SDS_DFT_1_REG_START                           0x00701580
+#define BCHP_SDS_DFT_1_REG_END                             0x007015a8
+#define BCHP_SDS_CWC_1_REG_START                           0x00701600
+#define BCHP_SDS_CWC_1_REG_END                             0x00701694
+#define BCHP_SDS_MISC_1_REG_START                          0x00701700
+#define BCHP_SDS_MISC_1_REG_END                            0x00701798
+#define BCHP_SDS_DSEC_1_REG_START                          0x00701800
+#define BCHP_SDS_DSEC_1_REG_END                            0x007018c8
+#define BCHP_SDS_TUNER_1_REG_START                         0x00701900
+#define BCHP_SDS_TUNER_1_REG_END                           0x007019fc
+#define BCHP_SDS_INTR2_0_1_REG_START                       0x00701a00
+#define BCHP_SDS_INTR2_0_1_REG_END                         0x00701a2c
+#define BCHP_SDS_INTR2_1_1_REG_START                       0x00701b00
+#define BCHP_SDS_INTR2_1_1_REG_END                         0x00701b2c
+#define BCHP_SDS_GR_BRIDGE_1_REG_START                     0x00701c00
+#define BCHP_SDS_GR_BRIDGE_1_REG_END                       0x00701c0c
+#define BCHP_TFEC_0_REG_START                              0x00702000
+#define BCHP_TFEC_0_REG_END                                0x00702060
+#define BCHP_TFEC_MISC_0_REG_START                         0x00702100
+#define BCHP_TFEC_MISC_0_REG_END                           0x00702108
+#define BCHP_TFEC_INTR2_0_REG_START                        0x00702200
+#define BCHP_TFEC_INTR2_0_REG_END                          0x0070222c
+#define BCHP_TFEC_GR_BRIDGE_0_REG_START                    0x00702300
+#define BCHP_TFEC_GR_BRIDGE_0_REG_END                      0x0070230c
+#define BCHP_TFEC_1_REG_START                              0x00703000
+#define BCHP_TFEC_1_REG_END                                0x00703060
+#define BCHP_TFEC_MISC_1_REG_START                         0x00703100
+#define BCHP_TFEC_MISC_1_REG_END                           0x00703108
+#define BCHP_TFEC_INTR2_1_REG_START                        0x00703200
+#define BCHP_TFEC_INTR2_1_REG_END                          0x0070322c
+#define BCHP_TFEC_GR_BRIDGE_1_REG_START                    0x00703300
+#define BCHP_TFEC_GR_BRIDGE_1_REG_END                      0x0070330c
+#define BCHP_AFEC_0_REG_START                              0x00704000
+#define BCHP_AFEC_0_REG_END                                0x007043fc
+#define BCHP_AFEC_INTR_CTRL2_0_REG_START                   0x00704800
+#define BCHP_AFEC_INTR_CTRL2_0_REG_END                     0x0070482c
+#define BCHP_AFEC_GR_BRIDGE_0_REG_START                    0x00704900
+#define BCHP_AFEC_GR_BRIDGE_0_REG_END                      0x0070490c
+#define BCHP_AFEC_GLOBAL_0_REG_START                       0x00704a00
+#define BCHP_AFEC_GLOBAL_0_REG_END                         0x00704a0c
+#define BCHP_AFEC_1_REG_START                              0x00705000
+#define BCHP_AFEC_1_REG_END                                0x007053fc
+#define BCHP_AFEC_INTR_CTRL2_1_REG_START                   0x00705800
+#define BCHP_AFEC_INTR_CTRL2_1_REG_END                     0x0070582c
+#define BCHP_AFEC_GR_BRIDGE_1_REG_START                    0x00705900
+#define BCHP_AFEC_GR_BRIDGE_1_REG_END                      0x0070590c
+#define BCHP_AFEC_GLOBAL_1_REG_START                       0x00705a00
+#define BCHP_AFEC_GLOBAL_1_REG_END                         0x00705a0c
+#define BCHP_FTM_UART_REG_START                            0x00706000
+#define BCHP_FTM_UART_REG_END                              0x007060fc
+#define BCHP_FTM_PHY_REG_START                             0x00706000
+#define BCHP_FTM_PHY_REG_END                               0x007061fc
+#define BCHP_FTM_PHY_ANA_REG_START                         0x00706000
+#define BCHP_FTM_PHY_ANA_REG_END                           0x00706210
+#define BCHP_FTM_SKIT_REG_START                            0x00706000
+#define BCHP_FTM_SKIT_REG_END                              0x00706248
+#define BCHP_FTM_INTR2_REG_START                           0x00706000
+#define BCHP_FTM_INTR2_REG_END                             0x0070632c
+#define BCHP_FTM_GR_BRIDGE_REG_START                       0x00706000
+#define BCHP_FTM_GR_BRIDGE_REG_END                         0x0070633c
+#define BCHP_FTM_SW_SPARE_REG_START                        0x00706000
+#define BCHP_FTM_SW_SPARE_REG_END                          0x00706344
+#define BCHP_RAAGA_DSP_RGR_REG_START                       0x00800000
+#define BCHP_RAAGA_DSP_RGR_REG_END                         0x00800008
+#define BCHP_RAAGA_DSP_MISC_REG_START                      0x00820000
+#define BCHP_RAAGA_DSP_MISC_REG_END                        0x0082044c
+#define BCHP_RAAGA_DSP_TIMERS_REG_START                    0x00821000
+#define BCHP_RAAGA_DSP_TIMERS_REG_END                      0x00821058
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START             0x00821080
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END               0x0082109c
+#define BCHP_RAAGA_DSP_PERI_SW_REG_START                   0x00821100
+#define BCHP_RAAGA_DSP_PERI_SW_REG_END                     0x00821154
+#define BCHP_RAAGA_DSP_DMA_REG_START                       0x00821400
+#define BCHP_RAAGA_DSP_DMA_REG_END                         0x00821664
+#define BCHP_RAAGA_DSP_ESR_SI_REG_START                    0x00822000
+#define BCHP_RAAGA_DSP_ESR_SI_REG_END                      0x00822014
+#define BCHP_RAAGA_DSP_INTH_REG_START                      0x00822200
+#define BCHP_RAAGA_DSP_INTH_REG_END                        0x0082222c
+#define BCHP_RAAGA_DSP_FW_INTH_REG_START                   0x00822400
+#define BCHP_RAAGA_DSP_FW_INTH_REG_END                     0x0082242c
+#define BCHP_RAAGA_DSP_FW_CFG_REG_START                    0x00823000
+#define BCHP_RAAGA_DSP_FW_CFG_REG_END                      0x0082357c
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START             0x00830000
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END               0x0083bffc
+#define BCHP_AIO_MISC_REG_START                            0x00880000
+#define BCHP_AIO_MISC_REG_END                              0x00880010
+#define BCHP_AIO_INTH_REG_START                            0x00880800
+#define BCHP_AIO_INTH_REG_END                              0x0088082c
+#define BCHP_AIO_INTD0_REG_START                           0x00880a00
+#define BCHP_AIO_INTD0_REG_END                             0x00880a14
+#define BCHP_AUD_FMM_MISC_REG_START                        0x008a0000
+#define BCHP_AUD_FMM_MISC_REG_END                          0x008a010c
+#define BCHP_AUD_FMM_BF_CTRL_REG_START                     0x008a2000
+#define BCHP_AUD_FMM_BF_CTRL_REG_END                       0x008a2b7c
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_START                   0x008a3000
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_END                     0x008a3014
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_START                   0x008a3020
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_END                     0x008a3034
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_START                   0x008a3040
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_END                     0x008a3054
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_START                  0x008a3100
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_END                    0x008a3114
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_START                  0x008a3120
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_END                    0x008a3134
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_START                  0x008a3140
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_END                    0x008a3154
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_START                   0x008a4000
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_END                     0x008a4bfc
+#define BCHP_AUD_FMM_SRC_ESR0_REG_START                    0x008a5000
+#define BCHP_AUD_FMM_SRC_ESR0_REG_END                      0x008a5014
+#define BCHP_AUD_FMM_DP_CTRL0_REG_START                    0x008a8000
+#define BCHP_AUD_FMM_DP_CTRL0_REG_END                      0x008a98ec
+#define BCHP_AUD_FMM_DP_ESR00_REG_START                    0x008abc00
+#define BCHP_AUD_FMM_DP_ESR00_REG_END                      0x008abc14
+#define BCHP_AUD_FMM_DP_ESR20_REG_START                    0x008abc80
+#define BCHP_AUD_FMM_DP_ESR20_REG_END                      0x008abc94
+#define BCHP_AUD_FMM_IOP_CTRL_REG_START                    0x008b8000
+#define BCHP_AUD_FMM_IOP_CTRL_REG_END                      0x008b8144
+#define BCHP_AUD_FMM_IOP_ESR_REG_START                     0x008b8400
+#define BCHP_AUD_FMM_IOP_ESR_REG_END                       0x008b8414
+#define BCHP_AUD_FMM_OP_CTRL_REG_START                     0x008ba000
+#define BCHP_AUD_FMM_OP_CTRL_REG_END                       0x008ba1fc
+#define BCHP_AUD_FMM_OP_ESR_REG_START                      0x008ba400
+#define BCHP_AUD_FMM_OP_ESR_REG_END                        0x008ba414
+#define BCHP_AUD_FMM_PLL0_REG_START                        0x008ba800
+#define BCHP_AUD_FMM_PLL0_REG_END                          0x008ba834
+#define BCHP_AUD_FMM_PLL1_REG_START                        0x008ba900
+#define BCHP_AUD_FMM_PLL1_REG_END                          0x008ba934
+#define BCHP_HIFIDAC_CTRL0_REG_START                       0x008bb000
+#define BCHP_HIFIDAC_CTRL0_REG_END                         0x008bb1fc
+#define BCHP_HIFIDAC_RM0_REG_START                         0x008bb200
+#define BCHP_HIFIDAC_RM0_REG_END                           0x008bb224
+#define BCHP_HIFIDAC_ESR0_REG_START                        0x008bb300
+#define BCHP_HIFIDAC_ESR0_REG_END                          0x008bb314
+#define BCHP_AUD_FMM_MS_CTRL_REG_START                     0x008bc000
+#define BCHP_AUD_FMM_MS_CTRL_REG_END                       0x008bdbfc
+#define BCHP_AUD_FMM_MS_ESR_REG_START                      0x008be000
+#define BCHP_AUD_FMM_MS_ESR_REG_END                        0x008be014
+#define BCHP_RAAGA_DSP_SEC0_REG_START                      0x00900000
+#define BCHP_RAAGA_DSP_SEC0_REG_END                        0x00900000
+#define BCHP_XPT_BUS_IF_REG_START                          0x00a00000
+#define BCHP_XPT_BUS_IF_REG_END                            0x00a00078
+#define BCHP_XPT_XMEMIF_REG_START                          0x00a00100
+#define BCHP_XPT_XMEMIF_REG_END                            0x00a001a0
+#define BCHP_XPT_PMU_REG_START                             0x00a00200
+#define BCHP_XPT_PMU_REG_END                               0x00a00208
+#define BCHP_XPT_GR_REG_START                              0x00a00300
+#define BCHP_XPT_GR_REG_END                                0x00a0030c
+#define BCHP_XPT_RMX0_IO_REG_START                         0x00a00400
+#define BCHP_XPT_RMX0_IO_REG_END                           0x00a00420
+#define BCHP_XPT_RMX1_IO_REG_START                         0x00a00500
+#define BCHP_XPT_RMX1_IO_REG_END                           0x00a00520
+#define BCHP_XPT_WAKEUP_REG_START                          0x00a01000
+#define BCHP_XPT_WAKEUP_REG_END                            0x00a01fbc
+#define BCHP_XPT_FE_REG_START                              0x00a04000
+#define BCHP_XPT_FE_REG_END                                0x00a057fc
+#define BCHP_XPT_DPCR0_REG_START                           0x00a07000
+#define BCHP_XPT_DPCR0_REG_END                             0x00a07074
+#define BCHP_XPT_DPCR1_REG_START                           0x00a07080
+#define BCHP_XPT_DPCR1_REG_END                             0x00a070f4
+#define BCHP_XPT_DPCR2_REG_START                           0x00a07100
+#define BCHP_XPT_DPCR2_REG_END                             0x00a07174
+#define BCHP_XPT_DPCR3_REG_START                           0x00a07180
+#define BCHP_XPT_DPCR3_REG_END                             0x00a071f4
+#define BCHP_XPT_DPCR4_REG_START                           0x00a07200
+#define BCHP_XPT_DPCR4_REG_END                             0x00a07274
+#define BCHP_XPT_DPCR5_REG_START                           0x00a07280
+#define BCHP_XPT_DPCR5_REG_END                             0x00a072f4
+#define BCHP_XPT_DPCR6_REG_START                           0x00a07300
+#define BCHP_XPT_DPCR6_REG_END                             0x00a07374
+#define BCHP_XPT_DPCR7_REG_START                           0x00a07380
+#define BCHP_XPT_DPCR7_REG_END                             0x00a073f4
+#define BCHP_XPT_DPCR_PP_REG_START                         0x00a07400
+#define BCHP_XPT_DPCR_PP_REG_END                           0x00a07404
+#define BCHP_XPT_PSUB_REG_START                            0x00a07a00
+#define BCHP_XPT_PSUB_REG_END                              0x00a07ac8
+#define BCHP_XPT_MPOD_REG_START                            0x00a07c00
+#define BCHP_XPT_MPOD_REG_END                              0x00a07c20
+#define BCHP_XPT_RMX0_REG_START                            0x00a07d00
+#define BCHP_XPT_RMX0_REG_END                              0x00a07d08
+#define BCHP_XPT_RMX1_REG_START                            0x00a07e00
+#define BCHP_XPT_RMX1_REG_END                              0x00a07e08
+#define BCHP_XPT_PB_TOP_REG_START                          0x00a08000
+#define BCHP_XPT_PB_TOP_REG_END                            0x00a08084
+#define BCHP_XPT_PB0_REG_START                             0x00a08100
+#define BCHP_XPT_PB0_REG_END                               0x00a08174
+#define BCHP_XPT_PB1_REG_START                             0x00a08180
+#define BCHP_XPT_PB1_REG_END                               0x00a081f4
+#define BCHP_XPT_PB2_REG_START                             0x00a08200
+#define BCHP_XPT_PB2_REG_END                               0x00a08274
+#define BCHP_XPT_PB3_REG_START                             0x00a08280
+#define BCHP_XPT_PB3_REG_END                               0x00a082f4
+#define BCHP_XPT_PB4_REG_START                             0x00a08300
+#define BCHP_XPT_PB4_REG_END                               0x00a08374
+#define BCHP_XPT_PB5_REG_START                             0x00a08380
+#define BCHP_XPT_PB5_REG_END                               0x00a083f4
+#define BCHP_XPT_PB6_REG_START                             0x00a08400
+#define BCHP_XPT_PB6_REG_END                               0x00a08474
+#define BCHP_XPT_PB7_REG_START                             0x00a08480
+#define BCHP_XPT_PB7_REG_END                               0x00a084f4
+#define BCHP_XPT_PB8_REG_START                             0x00a08500
+#define BCHP_XPT_PB8_REG_END                               0x00a08574
+#define BCHP_XPT_PB9_REG_START                             0x00a08580
+#define BCHP_XPT_PB9_REG_END                               0x00a085f4
+#define BCHP_XPT_PB10_REG_START                            0x00a08600
+#define BCHP_XPT_PB10_REG_END                              0x00a08674
+#define BCHP_XPT_PB11_REG_START                            0x00a08680
+#define BCHP_XPT_PB11_REG_END                              0x00a086f4
+#define BCHP_XPT_PB12_REG_START                            0x00a08700
+#define BCHP_XPT_PB12_REG_END                              0x00a08774
+#define BCHP_XPT_PB13_REG_START                            0x00a08780
+#define BCHP_XPT_PB13_REG_END                              0x00a087f4
+#define BCHP_XPT_PB14_REG_START                            0x00a08800
+#define BCHP_XPT_PB14_REG_END                              0x00a08874
+#define BCHP_XPT_PB15_REG_START                            0x00a08880
+#define BCHP_XPT_PB15_REG_END                              0x00a088f4
+#define BCHP_XPT_PCROFFSET_REG_START                       0x00a0c000
+#define BCHP_XPT_PCROFFSET_REG_END                         0x00a0d8fc
+#define BCHP_XPT_FULL_PID_PARSER_REG_START                 0x00a10000
+#define BCHP_XPT_FULL_PID_PARSER_REG_END                   0x00a12050
+#define BCHP_XPT_RSBUFF_REG_START                          0x00a15000
+#define BCHP_XPT_RSBUFF_REG_END                            0x00a15b44
+#define BCHP_XPT_XCBUFF_REG_START                          0x00a16000
+#define BCHP_XPT_XCBUFF_REG_END                            0x00a17ccc
+#define BCHP_XPT_MSG_REG_START                             0x00a18000
+#define BCHP_XPT_MSG_REG_END                               0x00a1e014
+#define BCHP_XPT_RAVE_REG_START                            0x00a20000
+#define BCHP_XPT_RAVE_REG_END                              0x00a2c79c
+#define BCHP_XPT_XPU_REG_START                             0x00a30000
+#define BCHP_XPT_XPU_REG_END                               0x00a347fc
+#define BCHP_XPT_SECURE_BUS_IF_REG_START                   0x00a3f000
+#define BCHP_XPT_SECURE_BUS_IF_REG_END                     0x00a3f000
+
+
+/***************************************************************************
+ *AUD_FMM_MS_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK  0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
+
+/***************************************************************************
+ *AUD_FMM_OP_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
+ ***************************************************************************/
+/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD1
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_VFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *GFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK      0xffffffff
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT     0
+
+/***************************************************************************
+ *GFD_1
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD_1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK    0xffffffff
+#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT   0
+
+/***************************************************************************
+ *HIFIDAC_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_MUTE_USAGE - Mute usage
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *M2MC
+ ***************************************************************************/
+/***************************************************************************
+ *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK          0xffffffff
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT         0
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK              0xf0000000
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT             28
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK          0x0fffffe0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT         5
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK              0x0000001e
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT             1
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK           0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT          0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid   0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK              0xffff8000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT             15
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK   0x00004000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT  14
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK   0x00002000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT  13
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK         0x00000800
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT        11
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE   1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE  0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK  0x00000400
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK  0x00000200
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK          0x00000100
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT         8
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE   0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK   0x00000020
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT  5
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK     0x00000002
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK     0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT    0
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/***************************************************************************
+ *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK        0xffffffff
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT       0
+
+/***************************************************************************
+ *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK         0xffffffff
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT        0
+
+/***************************************************************************
+ *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_11_DST_COLOR_MATRIX_N - Linked-List Packet Word N for group DST_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_11_DST_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_12_OUTPUT_COLOR_MATRIX_N - Linked-List Packet Word N for group OUTPUT_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_12_OUTPUT_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_13_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *LIST_PKT_14_DST_CLUT - Linked-List Packet Word for group DST_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_14_DST_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_14_DST_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *TYPE_CLUT_COLOR_DATA - color data for color look up table
+ ***************************************************************************/
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK                  0xff000000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT                 24
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK                    0x00ff0000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT                   16
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK                  0x0000ff00
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT                 8
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK                   0x000000ff
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT                  0
+
+/***************************************************************************
+ *MEM_DMA
+ ***************************************************************************/
+/***************************************************************************
+ *DESC_WORD0 - MEM DMA Descriptor Word 0
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD0 :: READ_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD1 - MEM DMA Descriptor Word 1
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD1 :: WRITE_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_MASK                    0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD2 - MEM DMA Descriptor Word 2
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD2 :: INTR_ENABLE [31:31] */
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK                   0x80000000
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_SHIFT                  31
+
+/* MEM_DMA :: DESC_WORD2 :: LAST [30:30] */
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_MASK                          0x40000000
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_SHIFT                         30
+
+/* MEM_DMA :: DESC_WORD2 :: AUTO_APPEND [29:29] */
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_MASK                   0x20000000
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_SHIFT                  29
+
+/* MEM_DMA :: DESC_WORD2 :: reserved0 [28:25] */
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_MASK                     0x1e000000
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_SHIFT                    25
+
+/* MEM_DMA :: DESC_WORD2 :: TRANSFER_SIZE [24:00] */
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK                 0x01ffffff
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_SHIFT                0
+
+/***************************************************************************
+ *DESC_WORD3 - MEM DMA Descriptor Word 3
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD3 :: NEXT_DESC_ADDR [31:05] */
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK                0xffffffe0
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_SHIFT               5
+
+/* MEM_DMA :: DESC_WORD3 :: reserved0 [04:03] */
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_MASK                     0x00000018
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_SHIFT                    3
+
+/* MEM_DMA :: DESC_WORD3 :: READ_ENDIAN_MODE [02:02] */
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_MASK              0x00000004
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_SHIFT             2
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_BIG_ENDIAN        0
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_LITTLE_ENDIAN     1
+
+/* MEM_DMA :: DESC_WORD3 :: WRITE_ENDIAN_XLATE_MODE [01:00] */
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_MASK       0x00000003
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_SHIFT      0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_WORD_ALIGNED 0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_HALF_WORD_ALIGNED 1
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_BYTE_ALIGNED 2
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_reserved   3
+
+/***************************************************************************
+ *DESC_WORD4 - MEM DMA Descriptor Word 4
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD4 :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_SHIFT                    16
+
+/* MEM_DMA :: DESC_WORD4 :: SCRAM_CTRL_RSV [15:14] */
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_MASK                0x0000c000
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_SHIFT               14
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_END [13:13] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK                  0x00002000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_SHIFT                 13
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_START [12:12] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK                0x00001000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_SHIFT               12
+
+/* MEM_DMA :: DESC_WORD4 :: SG_ENABLE [11:11] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK                     0x00000800
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_SHIFT                    11
+
+/* MEM_DMA :: DESC_WORD4 :: ENC_DEC_INIT [10:10] */
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_MASK                  0x00000400
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_SHIFT                 10
+
+/* MEM_DMA :: DESC_WORD4 :: MODE_SEL [09:08] */
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_MASK                      0x00000300
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT                     8
+
+/* MEM_DMA :: DESC_WORD4 :: KEY_SELECT [07:00] */
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_MASK                    0x000000ff
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD5 - MEM DMA Descriptor Word 5
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD5 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD6 - MEM DMA Descriptor Word 6
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD6 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD7 - MEM DMA Descriptor Word 7
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD7 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *RAAGA_REGSET_DSP_CFG
+ ***************************************************************************/
+/***************************************************************************
+ *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK     0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT    0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo   2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono     1
+
+/***************************************************************************
+ *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
+
+/***************************************************************************
+ *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off     0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On      1
+
+/***************************************************************************
+ *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt  1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo  2
+
+/***************************************************************************
+ *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK       0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT      0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono    1
+
+/***************************************************************************
+ *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK   0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *RDC
+ ***************************************************************************/
+/***************************************************************************
+ *RUL - RUL Command.
+ ***************************************************************************/
+/* RDC :: RUL :: opcode [31:24] */
+#define BCHP_RDC_RUL_opcode_MASK                                   0xff000000
+#define BCHP_RDC_RUL_opcode_SHIFT                                  24
+#define BCHP_RDC_RUL_opcode_NOP                                    0
+#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM                          1
+#define BCHP_RDC_RUL_opcode_REG_WRITE                              2
+#define BCHP_RDC_RUL_opcode_REG_READ                               3
+#define BCHP_RDC_RUL_opcode_LOAD_IMM                               4
+#define BCHP_RDC_RUL_opcode_WINDOW_WRITE                           5
+#define BCHP_RDC_RUL_opcode_BLOCK_WRITE                            6
+#define BCHP_RDC_RUL_opcode_WINDOW_COPY                            7
+#define BCHP_RDC_RUL_opcode_BLOCK_COPY                             8
+#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK                        9
+#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW                        10
+#define BCHP_RDC_RUL_opcode_AND                                    11
+#define BCHP_RDC_RUL_opcode_AND_IMM                                12
+#define BCHP_RDC_RUL_opcode_OR                                     13
+#define BCHP_RDC_RUL_opcode_OR_IMM                                 14
+#define BCHP_RDC_RUL_opcode_XOR                                    15
+#define BCHP_RDC_RUL_opcode_XOR_IMM                                16
+#define BCHP_RDC_RUL_opcode_NOT                                    17
+#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT                           18
+#define BCHP_RDC_RUL_opcode_SUM                                    19
+#define BCHP_RDC_RUL_opcode_SUM_IMM                                20
+#define BCHP_RDC_RUL_opcode_COND_SKIP                              21
+#define BCHP_RDC_RUL_opcode_SKIP                                   22
+#define BCHP_RDC_RUL_opcode_EXIT                                   23
+#define BCHP_RDC_RUL_opcode_PLACEHOLDER                            255
+
+/* RDC :: RUL :: reserved0 [23:23] */
+#define BCHP_RDC_RUL_reserved0_MASK                                0x00800000
+#define BCHP_RDC_RUL_reserved0_SHIFT                               23
+
+/* union - case rdc_args [22:00] */
+/* RDC :: RUL :: rdc_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_rdc_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: rdc_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_rdc_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_rdc_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: rdc_args :: src2 [11:06] */
+#define BCHP_RDC_RUL_rdc_args_src2_MASK                            0x00000fc0
+#define BCHP_RDC_RUL_rdc_args_src2_SHIFT                           6
+
+/* RDC :: RUL :: rdc_args :: dest [05:00] */
+#define BCHP_RDC_RUL_rdc_args_dest_MASK                            0x0000003f
+#define BCHP_RDC_RUL_rdc_args_dest_SHIFT                           0
+
+/* union - case reg_args [22:00] */
+/* RDC :: RUL :: reg_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_reg_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_reg_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: reg_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_reg_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_reg_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: reg_args :: count [11:00] */
+#define BCHP_RDC_RUL_reg_args_count_MASK                           0x00000fff
+#define BCHP_RDC_RUL_reg_args_count_SHIFT                          0
+
+/***************************************************************************
+ *XPT_PB
+ ***************************************************************************/
+/***************************************************************************
+ *DESCRIPTOR_ABSTRACT - Playback Linked-List Descriptor Abstract
+ ***************************************************************************/
+/* XPT_PB :: DESCRIPTOR_ABSTRACT :: DESCRIPTOR_FORMAT [31:00] */
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_MASK     0xffffffff
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_SHIFT    0
+
+/***************************************************************************
+ *DESC_0 - Playback Linked-List Descriptor Word 0
+ ***************************************************************************/
+/* XPT_PB :: DESC_0 :: PB_BUFFER_START_ADDR [31:00] */
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_MASK               0xffffffff
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_SHIFT              0
+
+/***************************************************************************
+ *DESC_1 - Playback Linked-List Descriptor Word 1
+ ***************************************************************************/
+/* XPT_PB :: DESC_1 :: PB_BUFFER_LENGTH [31:00] */
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_MASK                   0xffffffff
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_SHIFT                  0
+
+/***************************************************************************
+ *DESC_2 - Playback Linked-List Descriptor Word 2
+ ***************************************************************************/
+/* XPT_PB :: DESC_2 :: PB_INTERRUPT_ENABLE [31:31] */
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_MASK                0x80000000
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_SHIFT               31
+
+/* XPT_PB :: DESC_2 :: PB_FORCE_RESYNC [30:30] */
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_MASK                    0x40000000
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_SHIFT                   30
+
+/* XPT_PB :: DESC_2 :: PB_HOST_DATA_INS_EN [29:29] */
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_MASK                0x20000000
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_SHIFT               29
+
+/* XPT_PB :: DESC_2 :: PUSH_PARTIAL_PACKET [28:28] */
+#define BCHP_XPT_PB_DESC_2_PUSH_PARTIAL_PACKET_MASK                0x10000000
+#define BCHP_XPT_PB_DESC_2_PUSH_PARTIAL_PACKET_SHIFT               28
+
+/* XPT_PB :: DESC_2 :: PB_DESC_TAG_ID [27:24] */
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_MASK                     0x0f000000
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_SHIFT                    24
+
+/* XPT_PB :: DESC_2 :: reserved0 [23:00] */
+#define BCHP_XPT_PB_DESC_2_reserved0_MASK                          0x00ffffff
+#define BCHP_XPT_PB_DESC_2_reserved0_SHIFT                         0
+
+/***************************************************************************
+ *DESC_3 - Playback Linked-List Descriptor Word 3
+ ***************************************************************************/
+/* XPT_PB :: DESC_3 :: PB_NEXT_DESC_ADDR [31:04] */
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_MASK                  0xfffffff0
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_SHIFT                 4
+
+/* XPT_PB :: DESC_3 :: reserved0 [03:01] */
+#define BCHP_XPT_PB_DESC_3_reserved0_MASK                          0x0000000e
+#define BCHP_XPT_PB_DESC_3_reserved0_SHIFT                         1
+
+/* XPT_PB :: DESC_3 :: PB_LAST_DESC_IND [00:00] */
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_MASK                   0x00000001
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_SHIFT                  0
+
+/***************************************************************************
+ *DESC_4 - Playback Linked-List Descriptor Word 4
+ ***************************************************************************/
+/* XPT_PB :: DESC_4 :: reserved0 [31:00] */
+#define BCHP_XPT_PB_DESC_4_reserved0_MASK                          0xffffffff
+#define BCHP_XPT_PB_DESC_4_reserved0_SHIFT                         0
+
+/***************************************************************************
+ *DESC_5 - Playback Linked-List Descriptor Word 5
+ ***************************************************************************/
+/* XPT_PB :: DESC_5 :: reserved0 [31:03] */
+#define BCHP_XPT_PB_DESC_5_reserved0_MASK                          0xfffffff8
+#define BCHP_XPT_PB_DESC_5_reserved0_SHIFT                         3
+
+/* XPT_PB :: DESC_5 :: RANDOM_ACCESS_INDICATION [02:02] */
+#define BCHP_XPT_PB_DESC_5_RANDOM_ACCESS_INDICATION_MASK           0x00000004
+#define BCHP_XPT_PB_DESC_5_RANDOM_ACCESS_INDICATION_SHIFT          2
+
+/* XPT_PB :: DESC_5 :: NEXT_PACKET_PACING_TIMESTAMP_VALID [01:01] */
+#define BCHP_XPT_PB_DESC_5_NEXT_PACKET_PACING_TIMESTAMP_VALID_MASK 0x00000002
+#define BCHP_XPT_PB_DESC_5_NEXT_PACKET_PACING_TIMESTAMP_VALID_SHIFT 1
+
+/* XPT_PB :: DESC_5 :: PKT2PKT_PACING_TIMESTAMP_DELTA_VALID [00:00] */
+#define BCHP_XPT_PB_DESC_5_PKT2PKT_PACING_TIMESTAMP_DELTA_VALID_MASK 0x00000001
+#define BCHP_XPT_PB_DESC_5_PKT2PKT_PACING_TIMESTAMP_DELTA_VALID_SHIFT 0
+
+/***************************************************************************
+ *DESC_6 - Playback Linked-List Descriptor Word 6
+ ***************************************************************************/
+/* XPT_PB :: DESC_6 :: NEXT_PACKET_PACING_TIMESTAMP [31:00] */
+#define BCHP_XPT_PB_DESC_6_NEXT_PACKET_PACING_TIMESTAMP_MASK       0xffffffff
+#define BCHP_XPT_PB_DESC_6_NEXT_PACKET_PACING_TIMESTAMP_SHIFT      0
+
+/***************************************************************************
+ *DESC_7 - Playback Linked-List Descriptor Word 7
+ ***************************************************************************/
+/* XPT_PB :: DESC_7 :: PKT2PKT_PACING_TIMESTAMP_DELTA [31:00] */
+#define BCHP_XPT_PB_DESC_7_PKT2PKT_PACING_TIMESTAMP_DELTA_MASK     0xffffffff
+#define BCHP_XPT_PB_DESC_7_PKT2PKT_PACING_TIMESTAMP_DELTA_SHIFT    0
+
+/***************************************************************************
+ *XPT_RAVE
+ ***************************************************************************/
+/***************************************************************************
+ *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
+
+/***************************************************************************
+ *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
+
+/***************************************************************************
+ *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
+ ***************************************************************************/
+/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
+
+#endif /* #ifndef BCHP_COMMON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_ddr40_phy_control_regs_0.h b/include/linux/brcmstb/7346b0/bchp_ddr40_phy_control_regs_0.h
new file mode 100644
index 0000000..3da7241
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_ddr40_phy_control_regs_0.h
@@ -0,0 +1,1513 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:14:22 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_ddr40_phy_control_regs_0.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 3:13p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_CONTROL_REGS_0 - DDR40 DDR40 physical interface control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION   0x003b6000 /* Address & Control revision register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL 0x003b6004 /* PHY clock power management control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS 0x003b6010 /* PHY PLL status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG 0x003b6014 /* PHY PLL configuration register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL 0x003b6018 /* PHY PLL control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS 0x003b601c /* PHY PLL dividers control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL 0x003b6020 /* Aux Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL 0x003b6030 /* Address & Control coarse VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL 0x003b6034 /* Address & Control fine VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL 0x003b6038 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL 0x003b603c /* PVT Compensation control and status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL 0x003b6040 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS 0x003b6044 /* PHY Auto Init rd_data_dly result register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE 0x003b6048 /* PHY VDL calibration control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS 0x003b604c /* PHY VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS 0x003b6050 /* PHY DQ VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS 0x003b6054 /* PHY Write Channel VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS 0x003b6058 /* PHY Read Enable VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL 0x003b605c /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS 0x003b6060 /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS 0x003b6064 /* Virtual VTT Connections register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE 0x003b6068 /* Virtual VTT Override register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL 0x003b606c /* VREF DAC Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL 0x003b6070 /* PhyBist Control Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED 0x003b6074 /* PhyBist Seed Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS 0x003b6078 /* PhyBist General Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS 0x003b607c /* PhyBist Per-Bit Control Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS 0x003b6080 /* PhyBist Per-Bit DQ Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS 0x003b6084 /* PhyBist Per-Bit DM and CK Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG 0x003b6090 /* DRAM Command Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0  0x003b6094 /* Mode Register 0 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1  0x003b6098 /* Mode Register 1 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2  0x003b609c /* Mode Register 2 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3  0x003b60a0 /* Mode Register 3 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL 0x003b60a4 /* Standby Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL 0x003b60b0 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2 0x003b60b4 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS 0x003b60b8 /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2 0x003b60bc /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE 0x003b60c0 /* Freeze-on-error enable register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK 0x003b60c4 /* Datapth Loopback control register */
+
+/***************************************************************************
+ *REVISION - Address & Control revision register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_MASK      0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_SHIFT     16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_MASK          0x0000ff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_SHIFT         8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_DEFAULT       64
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_MASK          0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_DEFAULT       5
+
+/***************************************************************************
+ *CLK_PM_CTRL - PHY clock power management control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_MASK   0xfffffffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_SHIFT  1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_DEFAULT 0
+
+/***************************************************************************
+ *PLL_STATUS - PHY PLL status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_MASK    0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_SHIFT   27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK_LOST [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_MASK    0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_SHIFT   26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: DDR_MHZ [25:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_MASK      0x03ffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_SHIFT     14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_4X [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: STATUS [12:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_MASK       0x00001ffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_SHIFT      1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_MASK         0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_CONFIG - PHY PLL configuration register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved0 [31:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_MASK    0xffffff80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_SHIFT   7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LP40_PLL_POST_RESET [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET_POST_DIV [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LDO_CTRL [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_MASK     0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_SHIFT    3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_DEFAULT  2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved1 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_MASK    0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_SHIFT   2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_MASK        0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_SHIFT       1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_DEFAULT     1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PWRDN [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_MASK        0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_SHIFT       0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_DEFAULT     0
+
+/***************************************************************************
+ *PLL_CONTROL - PHY PLL control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: reserved0 [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_SHIFT  31
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_kp [30:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_MASK        0x78000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_SHIFT       27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_DEFAULT     10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ki [26:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_MASK        0x07000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_SHIFT       24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_DEFAULT     3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ka [23:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_MASK        0x00e00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_SHIFT       21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_DEFAULT     3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: PLL_CONTROL [20:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_MASK 0x001fffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_DEFAULT 0
+
+/***************************************************************************
+ *PLL_DIVIDERS - PHY PLL dividers control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_MASK  0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_SHIFT 16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_HI [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_MASK 0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_LO [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: POST_DIV [13:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_MASK   0x00003800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_SHIFT  11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_DEFAULT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: PDIV [10:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_MASK       0x00000700
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_SHIFT      8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_DEFAULT    4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_MASK       0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_DEFAULT    32
+
+/***************************************************************************
+ *AUX_CONTROL - Aux Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved0 [31:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_MASK   0xfffffc00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_SHIFT  10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_cs [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_MASK       0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_SHIFT      7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_ad [06:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_MASK       0x00000070
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_SHIFT      4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_odt [03:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_MASK      0x0000000e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_SHIFT     1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: override [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_CTL - Address & Control coarse VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BIT_CTL - Address & Control fine VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_SHIFT  31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved0 [30:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ffffe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: rxenb [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_MASK  0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved1 [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_SHIFT 7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_reb [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_DEFAULT 0
+
+/***************************************************************************
+ *ZQ_PVT_COMP_CTL - PVT Compensation control and status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: update_mode [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_done [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_done [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_done [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: auto_sample_en [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_MASK 0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_en [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_ovr_en [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_ovr_en [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_comp [17:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_MASK 0x00038000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_comp [14:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_MASK 0x00007000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [11:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_MASK 0x00000e00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [08:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_MASK 0x000001c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_DEFAULT 0
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: auto_oeb [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a15 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_MASK  0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a14 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_MASK  0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a13 [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_MASK  0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_aux [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_MASK  0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: half_strength [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_MASK     0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_SHIFT    2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_MASK  0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_MASK     0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_SHIFT    0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_DEFAULT  0
+
+/***************************************************************************
+ *VDL_RD_DATA_DLY_STATUS - PHY Auto Init rd_data_dly result register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_SHIFT 12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: auto_init_state [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_MASK 0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_max [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_min [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_DEFAULT 7
+
+/***************************************************************************
+ *VDL_CALIBRATE - PHY VDL calibration control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_SHIFT 29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: use_straps [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: auto_init [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: skip_rst [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_MASK  0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_SHIFT 26
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: exit_in_sr [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_dly_cal [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_refresh [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_wr_dq [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: dq0_only [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_MASK  0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_mr_mpr [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_cal [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_MASK   0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_SHIFT  19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_en_cal [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_clocks [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_pair [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_steps [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_auto [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_ftm [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_phybist [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_byte [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_clocks [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_test [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_always [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_once [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_fast [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_DEFAULT 0
+
+/***************************************************************************
+ *VDL_CALIB_STATUS - PHY VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_MASK 0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_fail [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_MASK 0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_SHIFT 29
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_done [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_rd_data_dly_error [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_read_en_error [26:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_MASK 0x07800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_error [22:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_MASK 0x00780000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_sel [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_total [11:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_MASK 0x00000ffc
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_DEFAULT 1
+
+/***************************************************************************
+ *VDL_DQ_CALIB_STATUS - PHY DQ VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_total [25:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_MASK 0x03ff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_clocks [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_mode [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VDL_WR_CHAN_CALIB_STATUS - PHY Write Channel VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VDL_RD_EN_CALIB_STATUS - PHY Read Enable VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: low_vtt [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: high_vtt [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: error_reset [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_ctl_idle [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cs_idle [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cke_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error [18:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_MASK 0x0007fff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_low [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_high [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ready [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_DEFAULT 16777215
+
+/***************************************************************************
+ *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_DEFAULT 262143
+
+/***************************************************************************
+ *VREF_DAC_CONTROL - VREF DAC Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK1_GT_INT [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK0_GT_INT [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_GT_INT [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: EXT_GT_INT [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_TESTOUT_MUX_CTL [16:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_MASK 0x00018000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TEST [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_MASK   0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_SHIFT  14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_MASK   0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_SHIFT  13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_MASK   0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_SHIFT  12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_MASK   0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_SHIFT  6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_DEFAULT 32
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_MASK   0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_SHIFT  0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_DEFAULT 32
+
+/***************************************************************************
+ *PHYBIST_CNTRL - PhyBist Control Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_error_sel [13:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_MASK 0x00003f00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved1 [07:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_MASK 0x000000e0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_SHIFT 5
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: bench_mode [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_dat_error [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_ctl_error [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: int_loopback [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_DEFAULT 0
+
+/***************************************************************************
+ *PHYBIST_SEED - PhyBist Seed Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_SEED :: seed [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_MASK       0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_DEFAULT    621693686
+
+/***************************************************************************
+ *PHYBIST_STATUS - PhyBist General Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_pass [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_pass [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_SHIFT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_done [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_done [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: ctl_errors [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_DQ_STATUS - PhyBist Per-Bit DQ Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_STATUS :: dat_errors [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_MASK 0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_MISC_STATUS - PhyBist Per-Bit DM and CK Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: ck_errors [07:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_MASK 0x000000f0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: dm_errors [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_SHIFT 0
+
+/***************************************************************************
+ *COMMAND_REG - DRAM Command Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_MASK   0xfe000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_SHIFT  25
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: aux [24:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_MASK         0x01c00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_SHIFT        22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: we [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_MASK          0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_SHIFT         21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_DEFAULT       0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: cas [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_MASK         0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_SHIFT        20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ras [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_MASK         0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_SHIFT        19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ba [18:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_MASK          0x00070000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_SHIFT         16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_DEFAULT       0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_MASK          0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_DEFAULT       0
+
+/***************************************************************************
+ *MODE_REG0 - Mode Register 0
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG1 - Mode Register 1
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG2 - Mode Register 2
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG3 - Mode Register 3
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_DEFAULT         0
+
+/***************************************************************************
+ *STANDBY_CONTROL - Standby Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_ready [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_exit_pin_en [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_active [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: armed [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_MASK   0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_SHIFT  15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: warmstart [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_ldo_volts [13:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_MASK 0x00003000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_skip_mrs [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_rst_n [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_cke [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: ldo_volts [08:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_MASK 0x00000180
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_DEFAULT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: skip_mrs [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: rst_n [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_MASK   0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_SHIFT  5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: cke [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_MASK     0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_SHIFT    4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_CONTROL - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: reserved0 [31:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_MASK 0xf0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_MASK       0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_SHIFT      16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_MASK  0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_MASK 0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_MASK     0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_SHIFT    12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_MASK      0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_SHIFT     11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_MASK      0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_SHIFT     8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_CONTROL2 - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_MASK     0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_SHIFT    20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_MASK       0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_SHIFT      17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_MASK       0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_SHIFT      12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_MASK      0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_SHIFT     7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_MASK       0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_DEFAULT    0
+
+/***************************************************************************
+ *STRAP_STATUS - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_MASK  0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_reg [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_MASK   0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_SHIFT  29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_memc [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_MASK  0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_MASK        0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_SHIFT       16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_MASK   0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_SHIFT  14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_MASK      0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_SHIFT     12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_MASK       0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_SHIFT      11
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_SHIFT 10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_MASK       0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_SHIFT      8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_MASK  0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_SHIFT 0
+
+/***************************************************************************
+ *STRAP_STATUS2 - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_MASK      0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_SHIFT     20
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_MASK        0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_SHIFT       17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_MASK        0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_SHIFT       12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_MASK       0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_SHIFT      7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_MASK        0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_SHIFT       0
+
+/***************************************************************************
+ *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl1 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl0 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl1 [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl0 [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_DEFAULT 0
+
+/***************************************************************************
+ *DATAPATH_LOOPBACK - Datapth Loopback control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: xor_dm_rd_en [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: use_addr_ctl [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_DEFAULT 0
+
+#endif /* #ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_ddr40_phy_word_lane_0_0.h b/include/linux/brcmstb/7346b0/bchp_ddr40_phy_word_lane_0_0.h
new file mode 100644
index 0000000..44e513d
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_ddr40_phy_word_lane_0_0.h
@@ -0,0 +1,3334 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:28:33 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_ddr40_phy_word_lane_0_0.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 3:14p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_0_0 - DDR40 DDR40 word lane #0 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN 0x003b6200 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W 0x003b6204 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P 0x003b6208 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N 0x003b620c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W 0x003b6210 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W 0x003b6214 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W 0x003b6218 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W 0x003b621c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W 0x003b6220 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W 0x003b6224 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W 0x003b6228 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W 0x003b622c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W 0x003b6230 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003b6234 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003b6238 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003b623c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003b6240 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003b6244 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003b6248 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003b624c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003b6250 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003b6254 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003b6258 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003b625c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003b6260 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003b6264 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003b6268 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003b626c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003b6270 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003b6274 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W 0x003b62a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P 0x003b62a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N 0x003b62ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W 0x003b62b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W 0x003b62b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W 0x003b62b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W 0x003b62bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W 0x003b62c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W 0x003b62c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W 0x003b62c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W 0x003b62cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W 0x003b62d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003b62d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003b62d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003b62dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003b62e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003b62e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003b62e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003b62ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003b62f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003b62f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003b62f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003b62fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003b6300 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003b6304 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003b6308 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003b630c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003b6310 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003b6314 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x003b6328 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x003b632c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003b6330 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003b6334 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W 0x003b6338 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003b633c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x003b6348 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x003b634c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003b6350 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003b6354 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W 0x003b6358 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003b635c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY 0x003b6360 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL 0x003b6364 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0 0x003b6370 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1 0x003b6374 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2 0x003b6378 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3 0x003b637c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0 0x003b6380 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1 0x003b6384 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2 0x003b6388 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3 0x003b638c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS 0x003b6390 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR 0x003b6394 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL 0x003b63a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL 0x003b63a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE 0x003b63a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE 0x003b63ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ 0x003b63b0 /* PHYBIST mode VDL step select adjustment register */
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_RD_EN - Read Enable Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *READ_DATA_DLY - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_MASK  0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: rd_data_dly [02:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_MASK 0x00000007
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_DEFAULT 1
+
+/***************************************************************************
+ *READ_CONTROL - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_MASK   0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_SHIFT  3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_enable [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_te_adj [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_le_adj [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_DEFAULT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status1 [07:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_MASK 0x000000f0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status0 [03:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_MASK 0x0000000f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_DEFAULT 0
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: clear [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_DEFAULT 0
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_MASK    0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_SHIFT   31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_SHIFT 24
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_MASK 0x00c00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_SHIFT 22
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_MASK 0x00300000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_SHIFT 20
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00080000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 19
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00040000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_SHIFT 18
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_MASK  0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_MASK  0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00008000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 15
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00004000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 14
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00002000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 13
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00001000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 12
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_MASK 0x00000008
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_DEFAULT 0
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_MASK  0xfffff000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_SHIFT 12
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: no_dqs_rd [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_MASK  0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_MASK    0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_SHIFT   6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_MASK      0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_SHIFT     2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_DEFAULT   0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_MASK   0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_SHIFT  1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_MASK      0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_SHIFT     0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_DEFAULT   0
+
+/***************************************************************************
+ *CLOCK_PAD_DISABLE - Clock pad disable register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_DEFAULT 0
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffc
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_SHIFT 2
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: long [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_MASK    0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_SHIFT   1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: mode [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_DEFAULT 0
+
+/***************************************************************************
+ *PHYBIST_VDL_ADJ - PHYBIST mode VDL step select adjustment register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_SHIFT 29
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq1_vdl_adj [28:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_MASK 0x1f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved1 [23:21] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_MASK 0x00e00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_SHIFT 21
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq0_vdl_adj [20:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_MASK 0x001f0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved2 [15:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_MASK 0x0000e000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_SHIFT 13
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs1_vdl_adj [12:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_MASK 0x00001f00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved3 [07:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_MASK 0x000000e0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_SHIFT 5
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs0_vdl_adj [04:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_MASK 0x0000001f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_DEFAULT 0
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_ddr40_phy_word_lane_1_0.h b/include/linux/brcmstb/7346b0/bchp_ddr40_phy_word_lane_1_0.h
new file mode 100644
index 0000000..9cd00d4
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_ddr40_phy_word_lane_1_0.h
@@ -0,0 +1,139 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:16:13 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_ddr40_phy_word_lane_1_0.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 3:14p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_1_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_1_0 - DDR40 DDR40 word lane #1 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN 0x003b6400 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W 0x003b6404 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P 0x003b6408 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N 0x003b640c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W 0x003b6410 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W 0x003b6414 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W 0x003b6418 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W 0x003b641c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W 0x003b6420 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W 0x003b6424 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W 0x003b6428 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W 0x003b642c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W 0x003b6430 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003b6434 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003b6438 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003b643c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003b6440 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003b6444 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003b6448 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003b644c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003b6450 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003b6454 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003b6458 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003b645c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003b6460 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003b6464 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003b6468 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003b646c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003b6470 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003b6474 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W 0x003b64a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P 0x003b64a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N 0x003b64ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W 0x003b64b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W 0x003b64b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W 0x003b64b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W 0x003b64bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W 0x003b64c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W 0x003b64c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W 0x003b64c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W 0x003b64cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W 0x003b64d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003b64d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003b64d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003b64dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003b64e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003b64e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003b64e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003b64ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003b64f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003b64f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003b64f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003b64fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003b6500 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003b6504 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003b6508 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003b650c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003b6510 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003b6514 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x003b6528 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x003b652c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003b6530 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003b6534 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W 0x003b6538 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003b653c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x003b6548 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x003b654c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003b6550 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003b6554 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W 0x003b6558 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003b655c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_DATA_DLY 0x003b6560 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_CONTROL 0x003b6564 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_0 0x003b6570 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_1 0x003b6574 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_2 0x003b6578 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_3 0x003b657c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_0 0x003b6580 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_1 0x003b6584 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_2 0x003b6588 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_3 0x003b658c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_STATUS 0x003b6590 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_CLEAR 0x003b6594 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL 0x003b65a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL 0x003b65a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_CLOCK_PAD_DISABLE 0x003b65a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_WR_PREAMBLE_MODE 0x003b65ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ 0x003b65b0 /* PHYBIST mode VDL step select adjustment register */
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_1_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_ebi.h b/include/linux/brcmstb/7346b0/bchp_ebi.h
new file mode 100644
index 0000000..4da641f
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_ebi.h
@@ -0,0 +1,1711 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:14:00 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_ebi.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 3:31p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EBI_H__
+#define BCHP_EBI_H__
+
+/***************************************************************************
+ *EBI - EBI Registers
+ ***************************************************************************/
+#define BCHP_EBI_CS_BASE_0                       0x00410800 /* EBI CS Base 0 Register */
+#define BCHP_EBI_CS_CONFIG_0                     0x00410804 /* EBI CS Config 0 Register */
+#define BCHP_EBI_CS_BASE_1                       0x00410808 /* EBI CS Base 1 Register */
+#define BCHP_EBI_CS_CONFIG_1                     0x0041080c /* EBI CS Config 1 Register */
+#define BCHP_EBI_CS_BASE_2                       0x00410810 /* EBI CS Base 2 Register */
+#define BCHP_EBI_CS_CONFIG_2                     0x00410814 /* EBI CS Config 2 Register */
+#define BCHP_EBI_CS_BASE_3                       0x00410818 /* EBI CS Base 3 Register */
+#define BCHP_EBI_CS_CONFIG_3                     0x0041081c /* EBI CS Config 3 Register */
+#define BCHP_EBI_CS_BASE_4                       0x00410820 /* EBI CS Base 4 Register */
+#define BCHP_EBI_CS_CONFIG_4                     0x00410824 /* EBI CS Config 4 Register */
+#define BCHP_EBI_CS_BASE_5                       0x00410828 /* EBI CS Base 5 Register */
+#define BCHP_EBI_CS_CONFIG_5                     0x0041082c /* EBI CS Config 5 Register */
+#define BCHP_EBI_BURST_CFG_0                     0x00410840 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_1                     0x00410844 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_2                     0x00410848 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_3                     0x0041084c /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_4                     0x00410850 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_5                     0x00410854 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_ECR                             0x00410900 /* EBI Configuration Register */
+#define BCHP_EBI_CS_TRISTATE_CFG                 0x00410918 /* EBI CS Tristate Configuration Register */
+#define BCHP_EBI_TA_CFG                          0x0041091c /* EBI TA Configuration Register */
+#define BCHP_EBI_CS_SPI_SELECT                   0x00410920 /* SPI CS Select */
+#define BCHP_EBI_ARRAY_ADDRESS                   0x004109f0 /* EBI Data Array Address */
+
+/***************************************************************************
+ *CS_BASE_0 - EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_0 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_0_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT                         13
+
+/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_0_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_0 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_0_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_0_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_0 - EBI CS Config 0 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_0_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT                       1
+
+/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_0_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_0 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_0_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_0_le_SHIFT                              10
+
+/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_0_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_0_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT                       4
+
+/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_0_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT                        1
+
+/***************************************************************************
+ *CS_BASE_1 - EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_1 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_1_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_1_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_1 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_1_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_1_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_1_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_1 - EBI CS Config 1 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_1_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_1_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_1 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_1_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_1_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_1_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_1_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_1_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_2 - EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_2 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_2_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_2_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_2 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_2_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_2_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_2_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_2 - EBI CS Config 2 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_2_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_2_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_2 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_2_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_2_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_2_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_2_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_2_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_3 - EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_3 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_3_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_3_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_3 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_3_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_3_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_3_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_3 - EBI CS Config 3 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_3_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_3_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_3 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_3_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_3_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_3_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_3_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_3_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_4 - EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_4 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_4_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_4_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_4 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_4_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_4_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_4_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_4 - EBI CS Config 4 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_4_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_4_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_4 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_4_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_4_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_4_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_4_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_4_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_5 - EBI CS Base 5 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_5 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_5_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_5_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_5_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_5 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_5_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_5_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_5 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_5_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_5_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_5_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_5_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_5_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_5_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_5_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_5 - EBI CS Config 5 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_5 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_5_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_5_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_5_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_5_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_5_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_5_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_5 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_5_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_5_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_5_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_5 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_5_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_5_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_5_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_5_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_5_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_5_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_5_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_5_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_5_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_5 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_5_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_5_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_5_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_5 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_5_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_5_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_5_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_5 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_5_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_5_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_5_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_5 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_5_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_5_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_5_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_5 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_5_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_5_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_5_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_5 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_5_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_5_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_5_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_5 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_5_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_5_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_5_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_5 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_5_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_5_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_5_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_5 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_5_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_5_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_5_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_5_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_5_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_5_enable_DEFAULT                        0
+
+/***************************************************************************
+ *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_0_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_0_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_0 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_0_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_0_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_0_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_0_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_0_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_1_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_1_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_1 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_1_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_1_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_1_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_1_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_1_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_2_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_2_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_2 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_2_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_2_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_2_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_2_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_2_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_3_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_3_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_3 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_3_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_3_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_3_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_3_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_3_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_4_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_4_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_4 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_4_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_4_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_4_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_4_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_4_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_5 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_5 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_5 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_5_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_5_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_5_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_5 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_5 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_5 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_5 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_5_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_5_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_5 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_5 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_5_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_5_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_5_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_5 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_5 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_5 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_5_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_5_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_5 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_5_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_5_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_5_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_5 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_5_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_5_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_5 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_5_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_5_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_5_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_5 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_5_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_5_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_5_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *ECR - EBI Configuration Register
+ ***************************************************************************/
+/* EBI :: ECR :: reserved0 [31:28] */
+#define BCHP_EBI_ECR_reserved0_MASK                                0xf0000000
+#define BCHP_EBI_ECR_reserved0_SHIFT                               28
+
+/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK                            0x08000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT                           27
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT                         0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only  1
+
+/* EBI :: ECR :: reserved1 [26:26] */
+#define BCHP_EBI_ECR_reserved1_MASK                                0x04000000
+#define BCHP_EBI_ECR_reserved1_SHIFT                               26
+
+/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK                          0x02000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT                         25
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT                       0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10         0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00         1
+
+/* EBI :: ECR :: reserved2 [24:11] */
+#define BCHP_EBI_ECR_reserved2_MASK                                0x01fff800
+#define BCHP_EBI_ECR_reserved2_SHIFT                               11
+
+/* EBI :: ECR :: timeout_count [10:00] */
+#define BCHP_EBI_ECR_timeout_count_MASK                            0x000007ff
+#define BCHP_EBI_ECR_timeout_count_SHIFT                           0
+#define BCHP_EBI_ECR_timeout_count_DEFAULT                         1024
+
+/***************************************************************************
+ *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
+ ***************************************************************************/
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK             0x80000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT            31
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK             0x40000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT            30
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK             0x20000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT            29
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK             0x10000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT            28
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK            0x08000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT           27
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT         0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK            0x04000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT           26
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT         0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK         0x02000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT        25
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT      0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK         0x01000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT        24
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT      0
+
+/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:06] */
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK                    0x00ffffc0
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT                   6
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs5 [05:05] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_MASK             0x00000020
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_SHIFT            5
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK             0x00000010
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT            4
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK             0x00000008
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT            3
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK             0x00000004
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT            2
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK             0x00000002
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT            1
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK             0x00000001
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT            0
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT          0
+
+/***************************************************************************
+ *TA_CFG - EBI TA Configuration Register
+ ***************************************************************************/
+/* EBI :: TA_CFG :: reserved0 [31:04] */
+#define BCHP_EBI_TA_CFG_reserved0_MASK                             0xfffffff0
+#define BCHP_EBI_TA_CFG_reserved0_SHIFT                            4
+
+/* EBI :: TA_CFG :: use_ta3 [03:03] */
+#define BCHP_EBI_TA_CFG_use_ta3_MASK                               0x00000008
+#define BCHP_EBI_TA_CFG_use_ta3_SHIFT                              3
+#define BCHP_EBI_TA_CFG_use_ta3_DEFAULT                            1
+
+/* EBI :: TA_CFG :: use_ta2 [02:02] */
+#define BCHP_EBI_TA_CFG_use_ta2_MASK                               0x00000004
+#define BCHP_EBI_TA_CFG_use_ta2_SHIFT                              2
+#define BCHP_EBI_TA_CFG_use_ta2_DEFAULT                            0
+
+/* EBI :: TA_CFG :: use_ta1 [01:01] */
+#define BCHP_EBI_TA_CFG_use_ta1_MASK                               0x00000002
+#define BCHP_EBI_TA_CFG_use_ta1_SHIFT                              1
+#define BCHP_EBI_TA_CFG_use_ta1_DEFAULT                            1
+
+/* EBI :: TA_CFG :: reserved1 [00:00] */
+#define BCHP_EBI_TA_CFG_reserved1_MASK                             0x00000001
+#define BCHP_EBI_TA_CFG_reserved1_SHIFT                            0
+
+/***************************************************************************
+ *CS_SPI_SELECT - SPI CS Select
+ ***************************************************************************/
+/* EBI :: CS_SPI_SELECT :: reserved0 [31:16] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK                      0xffff0000
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT                     16
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_7_USES_SPI [15:15] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_MASK              0x00008000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_SHIFT             15
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK              0x00004000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT             14
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK              0x00002000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT             13
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK              0x00001000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT             12
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK              0x00000800
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT             11
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK              0x00000400
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT             10
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK              0x00000200
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT             9
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK              0x00000100
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT             8
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_7_SEL [07:07] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_MASK               0x00000080
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_SHIFT              7
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK               0x00000040
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT              6
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK               0x00000020
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT              5
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK               0x00000010
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT              4
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK               0x00000008
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT              3
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK               0x00000004
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT              2
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK               0x00000002
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT              1
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK               0x00000001
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT              0
+
+/***************************************************************************
+ *ARRAY_ADDRESS - EBI Data Array Address
+ ***************************************************************************/
+/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK                        0xfffffe00
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT                       9
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT                     0
+
+/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK                      0x000001f8
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT                     3
+
+/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK                         0x00000007
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT                        0
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT                      0
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE                            0x00410a00
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_START                           0
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_END                             127
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE                    32
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+/* EBI :: DATA_ARRAYi :: WORD [31:00] */
+#define BCHP_EBI_DATA_ARRAYi_WORD_MASK                             0xffffffff
+#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT                            0
+
+
+#endif /* #ifndef BCHP_EBI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_hif_cpu_intr1.h b/include/linux/brcmstb/7346b0/bchp_hif_cpu_intr1.h
new file mode 100644
index 0000000..bcae0dc
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_hif_cpu_intr1.h
@@ -0,0 +1,1835 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:23:13 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_hif_cpu_intr1.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 3:50p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_INTR1_H__
+#define BCHP_HIF_CPU_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_INTR1 - HIF CPU Thread Processor 0 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS        0x00411400 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS        0x00411404 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS        0x00411408 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS   0x0041140c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS   0x00411410 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS   0x00411414 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET      0x00411418 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET      0x0041141c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET      0x00411420 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR    0x00411424 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR    0x00411428 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR    0x0041142c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK    0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT   31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK        0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT       30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK    0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT   29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_MASK        0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_SHIFT       28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_MASK  0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_MASK  0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK  0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK  0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_MASK        0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_SHIFT       23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK     0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT    7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK     0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT    6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK     0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT    5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK     0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT    4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK     0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT    3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK     0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT    2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK        0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT       1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK        0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT       0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT     0
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK    0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT   31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK     0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT    29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK    0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT   25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_MASK        0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_SHIFT       22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK     0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT    21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK    0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT   20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK        0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT       19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_MASK     0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_SHIFT    18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_MASK  0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_MASK  0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_MASK  0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_MASK  0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_MASK  0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK      0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT     5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT   0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK    0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT   4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_MASK       0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_SHIFT      3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_DEFAULT    0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_MASK      0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_SHIFT     2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_DEFAULT   0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_MASK       0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_SHIFT      1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_DEFAULT    0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_MASK       0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_SHIFT      0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_DEFAULT    0
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: reserved0 [31:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved0_MASK           0xffc00000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved0_SHIFT          22
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_MASK    0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_SHIFT   21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK    0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT   19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK    0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT   18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK   0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT  17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK    0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT   15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK     0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT    14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK        0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT       13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK   0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT  30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_MASK   0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_SHIFT  28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_MASK   0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_SHIFT  23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_MASK   0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_SHIFT  22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_MASK  0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: reserved0 [31:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved0_MASK      0xffc00000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved0_SHIFT     22
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK   0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT  13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK      0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT     30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_MASK      0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_SHIFT     28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_MASK      0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_SHIFT     23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK      0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT     1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK      0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT     0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT   1
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK   0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT  29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK  0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_MASK  0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_MASK      0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_SHIFT     22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK   0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT  21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK  0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK      0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT     19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_MASK   0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_SHIFT  18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK    0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT   5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK  0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_MASK     0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_SHIFT    3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_DEFAULT  1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_MASK    0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_SHIFT   2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_MASK     0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_SHIFT    1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_DEFAULT  1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_MASK     0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_SHIFT    0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_DEFAULT  1
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: reserved0 [31:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved0_MASK         0xffc00000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved0_SHIFT        22
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_MASK  0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK  0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK  0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK  0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK   0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT  14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK      0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT     13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_MASK    0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_SHIFT   28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_MASK    0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_SHIFT   22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK    0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT   19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK  0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: reserved0 [31:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved0_MASK       0xffc00000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved0_SHIFT      22
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK    0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT   13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 1
+
+#endif /* #ifndef BCHP_HIF_CPU_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_hif_cpu_tp1_intr1.h b/include/linux/brcmstb/7346b0/bchp_hif_cpu_tp1_intr1.h
new file mode 100644
index 0000000..c7c393a
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_hif_cpu_tp1_intr1.h
@@ -0,0 +1,1835 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:17:08 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_hif_cpu_tp1_intr1.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 3:51p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_TP1_INTR1_H__
+#define BCHP_HIF_CPU_TP1_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_TP1_INTR1 - HIF CPU Thread Processor 1 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS    0x00411600 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS    0x00411604 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS    0x00411608 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS 0x0041160c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS 0x00411610 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS 0x00411614 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET  0x00411618 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET  0x0041161c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET  0x00411620 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR 0x00411624 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR 0x00411628 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR 0x0041162c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_MASK    0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_SHIFT   28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_MASK    0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_SHIFT   22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK    0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT   19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK  0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: reserved0 [31:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_reserved0_MASK       0xffc00000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_reserved0_SHIFT      22
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK    0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT   13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: reserved0 [31:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_reserved0_MASK  0xffc00000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_reserved0_SHIFT 22
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_MASK  0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_MASK  0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK  0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: reserved0 [31:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_reserved0_MASK     0xffc00000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_reserved0_SHIFT    22
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK  0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: reserved0 [31:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_reserved0_MASK   0xffc00000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_reserved0_SHIFT  22
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 1
+
+#endif /* #ifndef BCHP_HIF_CPU_TP1_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_hif_intr2.h b/include/linux/brcmstb/7346b0/bchp_hif_intr2.h
new file mode 100644
index 0000000..e794d43
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_hif_intr2.h
@@ -0,0 +1,1035 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:18:50 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_hif_intr2.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 3:51p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_INTR2_H__
+#define BCHP_HIF_INTR2_H__
+
+/***************************************************************************
+ *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_INTR2_CPU_STATUS                0x00411000 /* CPU interrupt Status Register */
+#define BCHP_HIF_INTR2_CPU_SET                   0x00411004 /* CPU interrupt Set Register */
+#define BCHP_HIF_INTR2_CPU_CLEAR                 0x00411008 /* CPU interrupt Clear Register */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS           0x0041100c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_CPU_MASK_SET              0x00411010 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR            0x00411014 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_INTR2_PCI_STATUS                0x00411018 /* PCI interrupt Status Register */
+#define BCHP_HIF_INTR2_PCI_SET                   0x0041101c /* PCI interrupt Set Register */
+#define BCHP_HIF_INTR2_PCI_CLEAR                 0x00411020 /* PCI interrupt Clear Register */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS           0x00411024 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_PCI_MASK_SET              0x00411028 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR            0x0041102c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_MASK          0x00080000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_SHIFT         19
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_DEFAULT       0
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_MASK          0x00008000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_SHIFT         15
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_DEFAULT       0
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK                   0x00007ffe
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT               0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_MASK             0x00080000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_SHIFT            19
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_MASK             0x00008000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_SHIFT            15
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_SET :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK                      0x00007ffe
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: CPU_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_MASK           0x00008000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_SHIFT          15
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK                    0x00007ffe
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_MASK     0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_SHIFT    19
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_DEFAULT  1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_MASK     0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_SHIFT    15
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_DEFAULT  1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK              0x00007ffe
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 1
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT          1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_MASK        0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_SHIFT       19
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_MASK        0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_SHIFT       15
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK                 0x00007ffe
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    1
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_MASK      0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_SHIFT     15
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK               0x00007ffe
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  1
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_MASK          0x00080000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_SHIFT         19
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_DEFAULT       0
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_MASK          0x00008000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_SHIFT         15
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_DEFAULT       0
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK                   0x00007ffe
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT               0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_MASK             0x00080000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_SHIFT            19
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_MASK             0x00008000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_SHIFT            15
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_SET :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK                      0x00007ffe
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: PCI_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_MASK           0x00008000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_SHIFT          15
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK                    0x00007ffe
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_MASK     0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_SHIFT    19
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_DEFAULT  1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_MASK     0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_SHIFT    15
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_DEFAULT  1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK              0x00007ffe
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 1
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT          1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_MASK        0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_SHIFT       19
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_MASK        0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_SHIFT       15
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK                 0x00007ffe
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    1
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_MASK      0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_SHIFT     15
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK               0x00007ffe
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  1
+
+#endif /* #ifndef BCHP_HIF_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_hif_mspi.h b/include/linux/brcmstb/7346b0/bchp_hif_mspi.h
new file mode 100644
index 0000000..1052015
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_hif_mspi.h
@@ -0,0 +1,1214 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:20:45 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_hif_mspi.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 3:51p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_MSPI_H__
+#define BCHP_HIF_MSPI_H__
+
+/***************************************************************************
+ *HIF_MSPI - Public MSPI Registers
+ ***************************************************************************/
+#define BCHP_HIF_MSPI_SPCR0_LSB                  0x00413200 /* SPCR0_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR0_MSB                  0x00413204 /* SPCR0_MSB Register */
+#define BCHP_HIF_MSPI_SPCR1_LSB                  0x00413208 /* SPCR1_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR1_MSB                  0x0041320c /* SPCR1_MSB REGISTER */
+#define BCHP_HIF_MSPI_NEWQP                      0x00413210 /* NEWQP REGISTER */
+#define BCHP_HIF_MSPI_ENDQP                      0x00413214 /* ENDQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR2                      0x00413218 /* SPCR2 REGISTER */
+#define BCHP_HIF_MSPI_MSPI_STATUS                0x00413220 /* MSPI STATUS REGISTER */
+#define BCHP_HIF_MSPI_CPTQP                      0x00413224 /* CPTQP REGISTER */
+#define BCHP_HIF_MSPI_TXRAM00                    0x00413240 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM01                    0x00413244 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM02                    0x00413248 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM03                    0x0041324c /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM04                    0x00413250 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM05                    0x00413254 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM06                    0x00413258 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM07                    0x0041325c /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM08                    0x00413260 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM09                    0x00413264 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM10                    0x00413268 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM11                    0x0041326c /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM12                    0x00413270 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM13                    0x00413274 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM14                    0x00413278 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM15                    0x0041327c /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM16                    0x00413280 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM17                    0x00413284 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM18                    0x00413288 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM19                    0x0041328c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM20                    0x00413290 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM21                    0x00413294 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM22                    0x00413298 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM23                    0x0041329c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM24                    0x004132a0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM25                    0x004132a4 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM26                    0x004132a8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM27                    0x004132ac /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM28                    0x004132b0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM29                    0x004132b4 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM30                    0x004132b8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_TXRAM31                    0x004132bc /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM00                    0x004132c0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM01                    0x004132c4 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM02                    0x004132c8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM03                    0x004132cc /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM04                    0x004132d0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM05                    0x004132d4 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM06                    0x004132d8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM07                    0x004132dc /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM08                    0x004132e0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM09                    0x004132e4 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM10                    0x004132e8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM11                    0x004132ec /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM12                    0x004132f0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM13                    0x004132f4 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM14                    0x004132f8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM15                    0x004132fc /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM16                    0x00413300 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM17                    0x00413304 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM18                    0x00413308 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM19                    0x0041330c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM20                    0x00413310 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM21                    0x00413314 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM22                    0x00413318 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM23                    0x0041331c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM24                    0x00413320 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM25                    0x00413324 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM26                    0x00413328 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM27                    0x0041332c /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM28                    0x00413330 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM29                    0x00413334 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM30                    0x00413338 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM31                    0x0041333c /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_CDRAM00                    0x00413340 /* 8-bit command (queue pointer = 0) */
+#define BCHP_HIF_MSPI_CDRAM01                    0x00413344 /* 8-bit command (queue pointer = 1) */
+#define BCHP_HIF_MSPI_CDRAM02                    0x00413348 /* 8-bit command (queue pointer = 2) */
+#define BCHP_HIF_MSPI_CDRAM03                    0x0041334c /* 8-bit command (queue pointer = 3) */
+#define BCHP_HIF_MSPI_CDRAM04                    0x00413350 /* 8-bit command (queue pointer = 4) */
+#define BCHP_HIF_MSPI_CDRAM05                    0x00413354 /* 8-bit command (queue pointer = 5) */
+#define BCHP_HIF_MSPI_CDRAM06                    0x00413358 /* 8-bit command (queue pointer = 6) */
+#define BCHP_HIF_MSPI_CDRAM07                    0x0041335c /* 8-bit command (queue pointer = 7) */
+#define BCHP_HIF_MSPI_CDRAM08                    0x00413360 /* 8-bit command (queue pointer = 8) */
+#define BCHP_HIF_MSPI_CDRAM09                    0x00413364 /* 8-bit command (queue pointer = 9) */
+#define BCHP_HIF_MSPI_CDRAM10                    0x00413368 /* 8-bit command (queue pointer = a) */
+#define BCHP_HIF_MSPI_CDRAM11                    0x0041336c /* 8-bit command (queue pointer = b) */
+#define BCHP_HIF_MSPI_CDRAM12                    0x00413370 /* 8-bit command (queue pointer = c) */
+#define BCHP_HIF_MSPI_CDRAM13                    0x00413374 /* 8-bit command (queue pointer = d) */
+#define BCHP_HIF_MSPI_CDRAM14                    0x00413378 /* 8-bit command (queue pointer = e) */
+#define BCHP_HIF_MSPI_CDRAM15                    0x0041337c /* 8-bit command (queue pointer = f) */
+#define BCHP_HIF_MSPI_WRITE_LOCK                 0x00413380 /* Control bit to lock group of write commands */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN          0x00413384 /* Debug bit to mask the generation of flush signals from Mspi */
+
+/***************************************************************************
+ *SPCR0_LSB - SPCR0_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK                          0x000000ff
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT                       0
+
+/***************************************************************************
+ *SPCR0_MSB - SPCR0_MSB Register
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_MSB :: MSTR [07:07] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_MASK                          0x00000080
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_SHIFT                         7
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_DEFAULT                       1
+
+/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [06:06] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK               0x00000040
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT              6
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT            0
+
+/* HIF_MSPI :: SPCR0_MSB :: BitS [05:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_MASK                          0x0000003c
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_SHIFT                         2
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_DEFAULT                       0
+
+/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK                          0x00000002
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT                         1
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT                       0
+
+/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK                          0x00000001
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT                       0
+
+/***************************************************************************
+ *SPCR1_LSB - SPCR1_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT                          0
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT                        0
+
+/***************************************************************************
+ *SPCR1_MSB - SPCR1_MSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK                        0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT                       0
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT                     0
+
+/***************************************************************************
+ *NEWQP - NEWQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: NEWQP :: newqp [03:00] */
+#define BCHP_HIF_MSPI_NEWQP_newqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT                            0
+#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT                          0
+
+/***************************************************************************
+ *ENDQP - ENDQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: ENDQP :: endqp [03:00] */
+#define BCHP_HIF_MSPI_ENDQP_endqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT                            0
+#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT                          0
+
+/***************************************************************************
+ *SPCR2 - SPCR2 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK                         0xffffff00
+#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT                        8
+
+/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK                    0x00000080
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT                   7
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT                 0
+
+/* HIF_MSPI :: SPCR2 :: spe [06:06] */
+#define BCHP_HIF_MSPI_SPCR2_spe_MASK                               0x00000040
+#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT                              6
+#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT                            0
+
+/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
+#define BCHP_HIF_MSPI_SPCR2_spifie_MASK                            0x00000020
+#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT                           5
+#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT                         0
+
+/* HIF_MSPI :: SPCR2 :: wren [04:04] */
+#define BCHP_HIF_MSPI_SPCR2_wren_MASK                              0x00000010
+#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT                             4
+#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT                           0
+
+/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
+#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK                              0x00000008
+#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT                             3
+#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT                           0
+
+/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
+#define BCHP_HIF_MSPI_SPCR2_loopq_MASK                             0x00000004
+#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT                            2
+#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT                          0
+
+/* HIF_MSPI :: SPCR2 :: hie [01:01] */
+#define BCHP_HIF_MSPI_SPCR2_hie_MASK                               0x00000002
+#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT                              1
+#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT                            0
+
+/* HIF_MSPI :: SPCR2 :: halt [00:00] */
+#define BCHP_HIF_MSPI_SPCR2_halt_MASK                              0x00000001
+#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT                             0
+#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT                           0
+
+/***************************************************************************
+ *MSPI_STATUS - MSPI STATUS REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK                   0xfffffffc
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT                  2
+
+/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK                       0x00000002
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT                      1
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT                    0
+
+/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK                        0x00000001
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT                       0
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT                     0
+
+/***************************************************************************
+ *CPTQP - CPTQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
+#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT                            0
+#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT                          0
+
+/***************************************************************************
+ *TXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM00_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM01_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM02_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM03_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM04_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM05_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM06_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM07_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM08_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM09_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM10_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM11_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM12_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM13_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM14_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM15_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM16_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM17_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM18_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM19_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM20_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM21_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM22_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM23_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM24_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM25_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM26_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM27_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM28_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM29_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM30_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM31_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM00 - 8-bit command (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM00 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM01 - 8-bit command (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM01 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM02 - 8-bit command (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM02 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM03 - 8-bit command (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM03 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM04 - 8-bit command (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM04 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM05 - 8-bit command (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM05 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM06 - 8-bit command (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM06 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM07 - 8-bit command (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM07 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM08 - 8-bit command (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM08 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM09 - 8-bit command (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM09 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM10 - 8-bit command (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM10 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM11 - 8-bit command (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM11 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM12 - 8-bit command (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM12 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM13 - 8-bit command (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM13 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM14 - 8-bit command (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM14 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM15 - 8-bit command (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM15 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT                          0
+
+/***************************************************************************
+ *WRITE_LOCK - Control bit to lock group of write commands
+ ***************************************************************************/
+/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK                    0xfffffffe
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT                   1
+
+/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK                    0x00000001
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT                   0
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT                 0
+
+/***************************************************************************
+ *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
+ ***************************************************************************/
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK             0xfffffffe
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT            1
+
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK       0x00000001
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT      0
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT    0
+
+#endif /* #ifndef BCHP_HIF_MSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/7346b0/bchp_hif_spi_intr2.h
new file mode 100644
index 0000000..498fe38
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_hif_spi_intr2.h
@@ -0,0 +1,567 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:11:04 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_hif_spi_intr2.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 3:54p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_SPI_INTR2_H__
+#define BCHP_HIF_SPI_INTR2_H__
+
+/***************************************************************************
+ *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
+ ***************************************************************************/
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS            0x00411d00 /* CPU interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_SET               0x00411d04 /* CPU interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR             0x00411d08 /* CPU interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS       0x00411d0c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET          0x00411d10 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR        0x00411d14 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS            0x00411d18 /* PCI interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_SET               0x00411d1c /* PCI interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR             0x00411d20 /* PCI interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS       0x00411d24 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET          0x00411d28 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR        0x00411d2c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT            0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT               0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT         0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT           0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT            0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT               0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT         0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT           0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_irq0.h b/include/linux/brcmstb/7346b0/bchp_irq0.h
new file mode 100644
index 0000000..09e1629
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_irq0.h
@@ -0,0 +1,227 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Thu Sep 29 16:50:59 2011
+ *                 MD5 Checksum         8155245fdf91c26162667953fda076c2
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_irq0.h $
+ * 
+ * Hydra_Software_Devel/2   9/30/11 10:50a pntruong
+ * SW7346-170: Resync with central RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ0_H__
+#define BCHP_IRQ0_H__
+
+/***************************************************************************
+ *IRQ0 - Level 2 CPU Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ0_IRQEN                          0x00406780 /* Interrupt Enable */
+#define BCHP_IRQ0_IRQSTAT                        0x00406784 /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ0 :: IRQEN :: reserved0 [31:28] */
+#define BCHP_IRQ0_IRQEN_reserved0_MASK                             0xf0000000
+#define BCHP_IRQ0_IRQEN_reserved0_SHIFT                            28
+
+/* IRQ0 :: IRQEN :: iicd_irqen [27:27] */
+#define BCHP_IRQ0_IRQEN_iicd_irqen_MASK                            0x08000000
+#define BCHP_IRQ0_IRQEN_iicd_irqen_SHIFT                           27
+#define BCHP_IRQ0_IRQEN_iicd_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: iicc_irqen [26:26] */
+#define BCHP_IRQ0_IRQEN_iicc_irqen_MASK                            0x04000000
+#define BCHP_IRQ0_IRQEN_iicc_irqen_SHIFT                           26
+#define BCHP_IRQ0_IRQEN_iicc_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: iicb_irqen [25:25] */
+#define BCHP_IRQ0_IRQEN_iicb_irqen_MASK                            0x02000000
+#define BCHP_IRQ0_IRQEN_iicb_irqen_SHIFT                           25
+#define BCHP_IRQ0_IRQEN_iicb_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: iica_irqen [24:24] */
+#define BCHP_IRQ0_IRQEN_iica_irqen_MASK                            0x01000000
+#define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT                           24
+#define BCHP_IRQ0_IRQEN_iica_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQEN_reserved1_MASK                             0x00f80000
+#define BCHP_IRQ0_IRQEN_reserved1_SHIFT                            19
+
+/* IRQ0 :: IRQEN :: uartc_irqen [18:18] */
+#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK                           0x00040000
+#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT                          18
+#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: uartb_irqen [17:17] */
+#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK                           0x00020000
+#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT                          17
+#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: uarta_irqen [16:16] */
+#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK                           0x00010000
+#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT                          16
+#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQEN_reserved2_MASK                             0x0000fc00
+#define BCHP_IRQ0_IRQEN_reserved2_SHIFT                            10
+
+/* IRQ0 :: IRQEN :: uc_irqen [09:09] */
+#define BCHP_IRQ0_IRQEN_uc_irqen_MASK                              0x00000200
+#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT                             9
+#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQEN_reserved3_MASK                             0x00000180
+#define BCHP_IRQ0_IRQEN_reserved3_SHIFT                            7
+
+/* IRQ0 :: IRQEN :: gio_irqen [06:06] */
+#define BCHP_IRQ0_IRQEN_gio_irqen_MASK                             0x00000040
+#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT                            6
+#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT                          0
+
+/* IRQ0 :: IRQEN :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQEN_reserved4_MASK                             0x00000020
+#define BCHP_IRQ0_IRQEN_reserved4_SHIFT                            5
+
+/* IRQ0 :: IRQEN :: ua_irqen [04:04] */
+#define BCHP_IRQ0_IRQEN_ua_irqen_MASK                              0x00000010
+#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT                             4
+#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: ub_irqen [03:03] */
+#define BCHP_IRQ0_IRQEN_ub_irqen_MASK                              0x00000008
+#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT                             3
+#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: irb_irqen [02:02] */
+#define BCHP_IRQ0_IRQEN_irb_irqen_MASK                             0x00000004
+#define BCHP_IRQ0_IRQEN_irb_irqen_SHIFT                            2
+#define BCHP_IRQ0_IRQEN_irb_irqen_DEFAULT                          0
+
+/* IRQ0 :: IRQEN :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQEN_reserved5_MASK                             0x00000003
+#define BCHP_IRQ0_IRQEN_reserved5_SHIFT                            0
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ0 :: IRQSTAT :: reserved0 [31:28] */
+#define BCHP_IRQ0_IRQSTAT_reserved0_MASK                           0xf0000000
+#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT                          28
+
+/* IRQ0 :: IRQSTAT :: iicdirq [27:27] */
+#define BCHP_IRQ0_IRQSTAT_iicdirq_MASK                             0x08000000
+#define BCHP_IRQ0_IRQSTAT_iicdirq_SHIFT                            27
+#define BCHP_IRQ0_IRQSTAT_iicdirq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: iiccirq [26:26] */
+#define BCHP_IRQ0_IRQSTAT_iiccirq_MASK                             0x04000000
+#define BCHP_IRQ0_IRQSTAT_iiccirq_SHIFT                            26
+#define BCHP_IRQ0_IRQSTAT_iiccirq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: iicbirq [25:25] */
+#define BCHP_IRQ0_IRQSTAT_iicbirq_MASK                             0x02000000
+#define BCHP_IRQ0_IRQSTAT_iicbirq_SHIFT                            25
+#define BCHP_IRQ0_IRQSTAT_iicbirq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: iicairq [24:24] */
+#define BCHP_IRQ0_IRQSTAT_iicairq_MASK                             0x01000000
+#define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT                            24
+#define BCHP_IRQ0_IRQSTAT_iicairq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQSTAT_reserved1_MASK                           0x00f80000
+#define BCHP_IRQ0_IRQSTAT_reserved1_SHIFT                          19
+
+/* IRQ0 :: IRQSTAT :: uartc_irq [18:18] */
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK                           0x00040000
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT                          18
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: uartb_irq [17:17] */
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK                           0x00020000
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT                          17
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: uarta_irq [16:16] */
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK                           0x00010000
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT                          16
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQSTAT_reserved2_MASK                           0x0000fc00
+#define BCHP_IRQ0_IRQSTAT_reserved2_SHIFT                          10
+
+/* IRQ0 :: IRQSTAT :: ucirq [09:09] */
+#define BCHP_IRQ0_IRQSTAT_ucirq_MASK                               0x00000200
+#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT                              9
+#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQSTAT_reserved3_MASK                           0x00000180
+#define BCHP_IRQ0_IRQSTAT_reserved3_SHIFT                          7
+
+/* IRQ0 :: IRQSTAT :: gioirq [06:06] */
+#define BCHP_IRQ0_IRQSTAT_gioirq_MASK                              0x00000040
+#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT                             6
+#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT                           0
+
+/* IRQ0 :: IRQSTAT :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQSTAT_reserved4_MASK                           0x00000020
+#define BCHP_IRQ0_IRQSTAT_reserved4_SHIFT                          5
+
+/* IRQ0 :: IRQSTAT :: uairq [04:04] */
+#define BCHP_IRQ0_IRQSTAT_uairq_MASK                               0x00000010
+#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT                              4
+#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: ubirq [03:03] */
+#define BCHP_IRQ0_IRQSTAT_ubirq_MASK                               0x00000008
+#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT                              3
+#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: irbirq [02:02] */
+#define BCHP_IRQ0_IRQSTAT_irbirq_MASK                              0x00000004
+#define BCHP_IRQ0_IRQSTAT_irbirq_SHIFT                             2
+#define BCHP_IRQ0_IRQSTAT_irbirq_DEFAULT                           0
+
+/* IRQ0 :: IRQSTAT :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQSTAT_reserved5_MASK                           0x00000003
+#define BCHP_IRQ0_IRQSTAT_reserved5_SHIFT                          0
+
+#endif /* #ifndef BCHP_IRQ0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_irq1.h b/include/linux/brcmstb/7346b0/bchp_irq1.h
new file mode 100644
index 0000000..2ec0b49
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_irq1.h
@@ -0,0 +1,53 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug  2 15:16:18 2010
+ *                 MD5 Checksum         616c5da46e7f2e811fb57b174083665d
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/a0/bchp_irq1.h $
+ * 
+ * Hydra_Software_Devel/1   8/2/10 6:34p pntruong
+ * SW7346-2: Initial version.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ1_H__
+#define BCHP_IRQ1_H__
+
+/***************************************************************************
+ *IRQ1 - Level 2 PCI Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ1_IRQEN                          0x00406788 /* Interrupt Enable */
+#define BCHP_IRQ1_IRQSTAT                        0x0040678c /* Interrupt Status */
+
+#endif /* #ifndef BCHP_IRQ1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_mem_dma_0.h b/include/linux/brcmstb/7346b0/bchp_mem_dma_0.h
new file mode 100644
index 0000000..3ac5ec0
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_mem_dma_0.h
@@ -0,0 +1,157 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:23:22 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_mem_dma_0.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 4:30p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEM_DMA_0_H__
+#define BCHP_MEM_DMA_0_H__
+
+/***************************************************************************
+ *MEM_DMA_0 - MEM_DMA_0 Registers
+ ***************************************************************************/
+#define BCHP_MEM_DMA_0_REVISION                  0x00374200 /* MEM_DMA REVISION */
+#define BCHP_MEM_DMA_0_FIRST_DESC                0x00374204 /* MEM_DMA First Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CTRL                      0x00374208 /* MEM_DMA Control Register */
+#define BCHP_MEM_DMA_0_WAKE_CTRL                 0x0037420c /* MEM_DMA Wake Control Register */
+#define BCHP_MEM_DMA_0_STATUS                    0x00374214 /* MEM_DMA Status Register */
+#define BCHP_MEM_DMA_0_CUR_DESC                  0x00374218 /* MEM_DMA Current Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CUR_BYTE                  0x0037421c /* MEM_DMA Current Byte Count Register */
+#define BCHP_MEM_DMA_0_SCRATCH                   0x00374224 /* MEM_DMA Scratch Register */
+
+/***************************************************************************
+ *REVISION - MEM_DMA REVISION
+ ***************************************************************************/
+/* MEM_DMA_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_0_REVISION_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_0_REVISION_reserved0_SHIFT                    16
+
+/* MEM_DMA_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_MASK                         0x0000ff00
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_SHIFT                        8
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_DEFAULT                      2
+
+/* MEM_DMA_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_MEM_DMA_0_REVISION_MINOR_MASK                         0x000000ff
+#define BCHP_MEM_DMA_0_REVISION_MINOR_SHIFT                        0
+#define BCHP_MEM_DMA_0_REVISION_MINOR_DEFAULT                      10
+
+/***************************************************************************
+ *FIRST_DESC - MEM_DMA First Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: FIRST_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_MASK                        0xffffffff
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_SHIFT                       0
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_DEFAULT                     0
+
+/***************************************************************************
+ *CTRL - MEM_DMA Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CTRL :: reserved0 [31:01] */
+#define BCHP_MEM_DMA_0_CTRL_reserved0_MASK                         0xfffffffe
+#define BCHP_MEM_DMA_0_CTRL_reserved0_SHIFT                        1
+
+/* MEM_DMA_0 :: CTRL :: RUN [00:00] */
+#define BCHP_MEM_DMA_0_CTRL_RUN_MASK                               0x00000001
+#define BCHP_MEM_DMA_0_CTRL_RUN_SHIFT                              0
+#define BCHP_MEM_DMA_0_CTRL_RUN_DEFAULT                            0
+
+/***************************************************************************
+ *WAKE_CTRL - MEM_DMA Wake Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: WAKE_CTRL :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_MASK                    0xfffffffc
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_SHIFT                   2
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE_MODE [01:01] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_MASK                    0x00000002
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_SHIFT                   1
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_DEFAULT                 0
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE [00:00] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MASK                         0x00000001
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_SHIFT                        0
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_DEFAULT                      0
+
+/***************************************************************************
+ *STATUS - MEM_DMA Status Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: STATUS :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_MEM_DMA_0_STATUS_reserved0_SHIFT                      2
+
+/* MEM_DMA_0 :: STATUS :: DMA_STATUS [01:00] */
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_MASK                      0x00000003
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_SHIFT                     0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_DEFAULT                   0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Idle                      0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Busy                      1
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Sleep                     2
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Reserved                  3
+
+/***************************************************************************
+ *CUR_DESC - MEM_DMA Current Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_MASK                          0xffffffff
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_SHIFT                         0
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_DEFAULT                       0
+
+/***************************************************************************
+ *CUR_BYTE - MEM_DMA Current Byte Count Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_BYTE :: reserved0 [31:25] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_MASK                     0xfe000000
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_SHIFT                    25
+
+/* MEM_DMA_0 :: CUR_BYTE :: COUNT [24:00] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_MASK                         0x01ffffff
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_SHIFT                        0
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_DEFAULT                      0
+
+/***************************************************************************
+ *SCRATCH - MEM_DMA Scratch Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_MASK                    0xffffffff
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_SHIFT                   0
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_DEFAULT                 0
+
+#endif /* #ifndef BCHP_MEM_DMA_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_memc_ddr_0.h b/include/linux/brcmstb/7346b0/bchp_memc_ddr_0.h
new file mode 100644
index 0000000..defb723
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_memc_ddr_0.h
@@ -0,0 +1,2665 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:54:00 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_memc_ddr_0.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 4:32p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR_0_H__
+#define BCHP_MEMC_DDR_0_H__
+
+/***************************************************************************
+ *MEMC_DDR_0 - Memory Controller Sequencer (DDR Param/Control) Registers 0
+ ***************************************************************************/
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG            0x003b2000 /* Memory Controller Mode-Configuration Register. */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL          0x003b2004 /* Dram iniitialization control */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS         0x003b2008 /* Dram iniitialization status */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0              0x003b200c /* Dram Mode0 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1              0x003b2010 /* Dram Mode1 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2              0x003b2014 /* Dram Mode2 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3              0x003b2018 /* Dram Mode3 register */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG               0x003b201c /* Precharge power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG              0x003b2020 /* Self-refresh power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SSPD_CMD                 0x003b2024 /* Software standby power down mode */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS        0x003b2028 /* Power down status */
+#define BCHP_MEMC_DDR_0_WARM_BOOT                0x003b202c /* Warm boot control registers */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0            0x003b2030 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1            0x003b2034 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2            0x003b2038 /* Read to Write & write to read timing register */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3            0x003b203c /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4            0x003b2040 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5            0x003b2044 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ         0x003b2048 /* Memory Controller Sequencer Enable */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT        0x003b204c /* Memory Controller , state machine timeout register. */
+#define BCHP_MEMC_DDR_0_BANK_STATUS              0x003b2050 /* Memory Controller, Bank Status Register. */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY           0x003b2054 /* Memory Controller, Tester Latency Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0               0x003b2058 /* Memory Controller, DATA_PINMAP_BYTE0_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1               0x003b205c /* Memory Controller, DATA_PINMAP_BYTE1_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2               0x003b2060 /* Memory Controller, DATA_PINMAP_BYTE2_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3               0x003b2064 /* Memory Controller, DATA_PINMAP_BYTE3_SEL Register. */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD   0x003b2068 /* Memory Controller, DDR3 DRAM reset Register. */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL             0x003b206c /* Statistics Control register */
+#define BCHP_MEMC_DDR_0_STAT_TIMER               0x003b2070 /* Statistics Timer */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP            0x003b2074 /* DRAM Idle_NOP Cycle Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP        0x003b2078 /* Maximum DRAM idle_NOP cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL             0x003b207c /* CAS Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL         0x003b2080 /* Maximum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL         0x003b2084 /* DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL 0x003b2088 /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL      0x003b208c /* Number of overall system memory read transactions. */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL     0x003b2090 /* Number of overall system memory write transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL       0x003b2094 /* Maximum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL       0x003b2098 /* Minimum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS  0x003b209c /* Service CAS Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS 0x003b20a0 /* Maximum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS 0x003b20a4 /* Minimum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY 0x003b20a8 /* Service Intra DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY 0x003b20ac /* Service Post DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES 0x003b20b0 /* Maximum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES 0x003b20b4 /* Minimum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ 0x003b20b8 /* Service Read Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE 0x003b20bc /* Service Write Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS 0x003b20c0 /* Maximum service Transaction count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS 0x003b20c4 /* Minimum service cycle Transaction register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY 0x003b20c8 /* Service Latency Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY 0x003b20cc /* Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY 0x003b20d0 /* Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x003b20d4 /* Absolute Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x003b20d8 /* Absolute Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH             0x003b20dc /* Total number of refreshes issuedr. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0        0x003b20e0 /* CAS cycle count register for client 0. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1        0x003b20e4 /* CAS cycle count register for client 1. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2        0x003b20e8 /* CAS cycle count register for client 2. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3        0x003b20ec /* CAS cycle count register for client 3. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4        0x003b20f0 /* CAS cycle count register for client 4. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5        0x003b20f4 /* CAS cycle count register for client 5. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6        0x003b20f8 /* CAS cycle count register for client 6. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7        0x003b20fc /* CAS cycle count register for client 7. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8        0x003b2100 /* CAS cycle count register for client 8. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9        0x003b2104 /* CAS cycle count register for client 9. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10       0x003b2108 /* CAS cycle count register for client 10. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11       0x003b210c /* CAS cycle count register for client 11. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12       0x003b2110 /* CAS cycle count register for client 12. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13       0x003b2114 /* CAS cycle count register for client 13. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14       0x003b2118 /* CAS cycle count register for client 14. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15       0x003b211c /* CAS cycle count register for client 15. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16       0x003b2120 /* CAS cycle count register for client 16. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17       0x003b2124 /* CAS cycle count register for client 17. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18       0x003b2128 /* CAS cycle count register for client 18. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19       0x003b212c /* CAS cycle count register for client 19. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20       0x003b2130 /* CAS cycle count register for client 20. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21       0x003b2134 /* CAS cycle count register for client 21. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22       0x003b2138 /* CAS cycle count register for client 22. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23       0x003b213c /* CAS cycle count register for client 23. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24       0x003b2140 /* CAS cycle count register for client 24. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25       0x003b2144 /* CAS cycle count register for client 25. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26       0x003b2148 /* CAS cycle count register for client 26. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27       0x003b214c /* CAS cycle count register for client 27. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28       0x003b2150 /* CAS cycle count register for client 28. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29       0x003b2154 /* CAS cycle count register for client 29. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30       0x003b2158 /* CAS cycle count register for client 30. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31       0x003b215c /* CAS cycle count register for client 31. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32       0x003b2160 /* CAS cycle count register for client 32. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33       0x003b2164 /* CAS cycle count register for client 33. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34       0x003b2168 /* CAS cycle count register for client 34. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35       0x003b216c /* CAS cycle count register for client 35. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36       0x003b2170 /* CAS cycle count register for client 36. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37       0x003b2174 /* CAS cycle count register for client 37. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38       0x003b2178 /* CAS cycle count register for client 38. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39       0x003b217c /* CAS cycle count register for client 39. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40       0x003b2180 /* CAS cycle count register for client 40. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41       0x003b2184 /* CAS cycle count register for client 41. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42       0x003b2188 /* CAS cycle count register for client 42. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43       0x003b218c /* CAS cycle count register for client 43. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44       0x003b2190 /* CAS cycle count register for client 44. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45       0x003b2194 /* CAS cycle count register for client 45. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46       0x003b2198 /* CAS cycle count register for client 46. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47       0x003b219c /* CAS cycle count register for client 47. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48       0x003b21a0 /* CAS cycle count register for client 48. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49       0x003b21a4 /* CAS cycle count register for client 49. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50       0x003b21a8 /* CAS cycle count register for client 50. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51       0x003b21ac /* CAS cycle count register for client 51. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52       0x003b21b0 /* CAS cycle count register for client 52. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53       0x003b21b4 /* CAS cycle count register for client 53. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54       0x003b21b8 /* CAS cycle count register for client 54. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55       0x003b21bc /* CAS cycle count register for client 55. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56       0x003b21c0 /* CAS cycle count register for client 56. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57       0x003b21c4 /* CAS cycle count register for client 57. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58       0x003b21c8 /* CAS cycle count register for client 58. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59       0x003b21cc /* CAS cycle count register for client 59. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60       0x003b21d0 /* CAS cycle count register for client 60. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61       0x003b21d4 /* CAS cycle count register for client 61. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62       0x003b21d8 /* CAS cycle count register for client 62. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63       0x003b21dc /* CAS cycle count register for client 63. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64       0x003b21e0 /* CAS cycle count register for client 64. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65       0x003b21e4 /* CAS cycle count register for client 65. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66       0x003b21e8 /* CAS cycle count register for client 66. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67       0x003b21ec /* CAS cycle count register for client 67. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68       0x003b21f0 /* CAS cycle count register for client 68. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69       0x003b21f4 /* CAS cycle count register for client 69. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70       0x003b21f8 /* CAS cycle count register for client 70. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71       0x003b21fc /* CAS cycle count register for client 71. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72       0x003b2200 /* CAS cycle count register for client 72. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73       0x003b2204 /* CAS cycle count register for client 73. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74       0x003b2208 /* CAS cycle count register for client 74. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75       0x003b220c /* CAS cycle count register for client 75. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76       0x003b2210 /* CAS cycle count register for client 76. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77       0x003b2214 /* CAS cycle count register for client 77. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78       0x003b2218 /* CAS cycle count register for client 78. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79       0x003b221c /* CAS cycle count register for client 79. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80       0x003b2220 /* CAS cycle count register for client 80. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81       0x003b2224 /* CAS cycle count register for client 81. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82       0x003b2228 /* CAS cycle count register for client 82. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83       0x003b222c /* CAS cycle count register for client 83. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84       0x003b2230 /* CAS cycle count register for client 84. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85       0x003b2234 /* CAS cycle count register for client 85. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86       0x003b2238 /* CAS cycle count register for client 86. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87       0x003b223c /* CAS cycle count register for client 87. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88       0x003b2240 /* CAS cycle count register for client 88. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89       0x003b2244 /* CAS cycle count register for client 89. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90       0x003b2248 /* CAS cycle count register for client 90. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91       0x003b224c /* CAS cycle count register for client 91. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92       0x003b2250 /* CAS cycle count register for client 92. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93       0x003b2254 /* CAS cycle count register for client 93. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94       0x003b2258 /* CAS cycle count register for client 94. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95       0x003b225c /* CAS cycle count register for client 95. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96       0x003b2260 /* CAS cycle count register for client 96. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97       0x003b2264 /* CAS cycle count register for client 97. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98       0x003b2268 /* CAS cycle count register for client 98. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99       0x003b226c /* CAS cycle count register for client 99. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100      0x003b2270 /* CAS cycle count register for client 100. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101      0x003b2274 /* CAS cycle count register for client 101. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102      0x003b2278 /* CAS cycle count register for client 102. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103      0x003b227c /* CAS cycle count register for client 103. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104      0x003b2280 /* CAS cycle count register for client 104. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105      0x003b2284 /* CAS cycle count register for client 105. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106      0x003b2288 /* CAS cycle count register for client 106. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107      0x003b228c /* CAS cycle count register for client 107. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108      0x003b2290 /* CAS cycle count register for client 108. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109      0x003b2294 /* CAS cycle count register for client 109. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110      0x003b2298 /* CAS cycle count register for client 110. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111      0x003b229c /* CAS cycle count register for client 111. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112      0x003b22a0 /* CAS cycle count register for client 112. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113      0x003b22a4 /* CAS cycle count register for client 113. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114      0x003b22a8 /* CAS cycle count register for client 114. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115      0x003b22ac /* CAS cycle count register for client 115. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116      0x003b22b0 /* CAS cycle count register for client 116. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117      0x003b22b4 /* CAS cycle count register for client 117. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118      0x003b22b8 /* CAS cycle count register for client 118. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119      0x003b22bc /* CAS cycle count register for client 119. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120      0x003b22c0 /* CAS cycle count register for client 120. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121      0x003b22c4 /* CAS cycle count register for client 121. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122      0x003b22c8 /* CAS cycle count register for client 122. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123      0x003b22cc /* CAS cycle count register for client 123. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124      0x003b22d0 /* CAS cycle count register for client 124. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125      0x003b22d4 /* CAS cycle count register for client 125. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126      0x003b22d8 /* CAS cycle count register for client 126. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127      0x003b22dc /* CAS cycle count register for client 127. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL         0x003b22e0 /* Minimum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL 0x003b22e4 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL 0x003b22e8 /* MEMSYS Auto Init Control. */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS  0x003b22ec /* MEMSYS Auto Init Status. */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE 0x003b22f0 /* PHY VDL calibrate override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE 0x003b22f4 /* SHIM PLL pndiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE 0x003b22f8 /* SHIM PLL mdiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY          0x003b22fc /* Dynamic VDL shmoo command delay. */
+
+/***************************************************************************
+ *CNTRLR_CONFIG - Memory Controller Mode-Configuration Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_MASK               0xfffffff8
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_SHIFT              3
+
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DEVICE_TECH [02:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_SHIFT            0
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_DEFAULT          3
+
+/***************************************************************************
+ *DRAM_INIT_CNTRL - Dram iniitialization control
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_MASK             0xfffffff8
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_SHIFT            3
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: BYPASS_PHY_INIT_RDY [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_MASK   0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_SHIFT  2
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR_TECH [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DEFAULT           1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR2              0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR3              1
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR3_INIT_MODE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_MASK        0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_SHIFT       0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_DEFAULT     0
+
+/***************************************************************************
+ *DRAM_INIT_STATUS - Dram iniitialization status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_SHIFT           0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_DEFAULT         0
+
+/***************************************************************************
+ *DRAM_MODE_0 - Dram Mode0 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: PD_EXIT [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_MASK              0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_SHIFT             12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_DEFAULT                7
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_DEFAULT         0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: CL [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_MASK                   0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_DEFAULT                0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BL [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_DEFAULT                2
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK        0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT       12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT     0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_DEFAULT                4
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT         0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_MASK               0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_SHIFT              4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT            4
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_DEFAULT               0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_MASK                 0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_SHIFT                2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_DEFAULT              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_MASK                   0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_MODE_1 - Dram Mode1 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DEFAULT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: RDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DQSB [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_MASK                 0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_SHIFT                10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_ENABLE               0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DISABLE              1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: OCD_CAL [09:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_MASK              0x00000380
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_SHIFT             7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_DEFAULT       1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: AL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_MASK                   0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DRV_IMP [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DISABLE            1
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_MASK             0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_SHIFT            10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK          0x00000200
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT         9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_MASK             0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT            7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT          0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE           1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK   0x00000020
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT  5
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_MASK                   0x00000018
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT       1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK   0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT  1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DISABLE            1
+
+/***************************************************************************
+ *DRAM_MODE_2 - Dram Mode2 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_1 [12:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_MASK             0x00001f00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: HT_SRF [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_ENABLE             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DISABLE            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_2 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_MASK             0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_SHIFT            4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: DCC_ENABLE [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_MASK           0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_SHIFT          3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DEFAULT        0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_ENABLE         1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DISABLE        0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_DEFAULT              0
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_MASK             0x00001800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_SHIFT            11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_MASK               0x00000600
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_SHIFT              9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT            1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT             6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT           1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_MASK                  0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_DEFAULT               1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_MODE_3 - Dram Mode3 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: unused_0 [15:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_MASK                  0x0000fff8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_DEFAULT               0
+
+/* union - case DDR2 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR2 :: unused_1 [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_SHIFT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_DEFAULT          0
+
+/* union - case DDR3 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_MASK                  0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_SHIFT                 2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_DEFAULT               0
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_MASK              0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT           0
+
+/***************************************************************************
+ *PPD_CONFIG - Precharge power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PPD_CONFIG :: reserved0 [31:13] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_MASK                  0xffffe000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_SHIFT                 13
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_EN [12:12] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_MASK                     0x00001000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_SHIFT                    12
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_DEFAULT                  0
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: INACT_COUNT [11:00] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_MASK                0x00000fff
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *SRPD_CONFIG - Self-refresh power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SRPD_CONFIG :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_MASK                 0xfffe0000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_SHIFT                17
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: SRPD_EN [16:16] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_MASK                   0x00010000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_SHIFT                  16
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_DEFAULT                0
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *SSPD_CMD - Software standby power down mode
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SSPD_CMD :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_MASK                    0xfffffffe
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_SHIFT                   1
+
+/* MEMC_DDR_0 :: SSPD_CMD :: SSPD [00:00] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK                         0x00000001
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_SHIFT                        0
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_DEFAULT                      0
+
+/***************************************************************************
+ *POWER_DOWN_STATUS - Power down status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_MASK           0xfffffff8
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_SHIFT          3
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SSPD [02:02] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK                0x00000004
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_SHIFT               2
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_DEFAULT             0
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SRPD [01:01] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_MASK                0x00000002
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_SHIFT               1
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_DEFAULT             0
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: PPD [00:00] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_MASK                 0x00000001
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_SHIFT                0
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_DEFAULT              0
+
+/***************************************************************************
+ *WARM_BOOT - Warm boot control registers
+ ***************************************************************************/
+/* MEMC_DDR_0 :: WARM_BOOT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_MASK                   0xfffffffe
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_SHIFT                  1
+
+/* MEMC_DDR_0 :: WARM_BOOT :: WARM_BOOT [00:00] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_MASK                   0x00000001
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_TIMING_0 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_MASK                0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_SHIFT               24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_DEFAULT             6
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_MASK                0x00ff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_SHIFT               16
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_DEFAULT             8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_MASK                 0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_SHIFT                8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_DEFAULT              8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_DEFAULT             20
+
+/***************************************************************************
+ *DRAM_TIMING_1 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_MASK                0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_SHIFT               8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_DEFAULT             27
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_DEFAULT             4
+
+/***************************************************************************
+ *DRAM_TIMING_2 - Read to Write & write to read timing register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_MASK               0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_SHIFT              8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_DEFAULT            14
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_MASK               0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_DEFAULT            9
+
+/***************************************************************************
+ *DRAM_TIMING_3 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: reserved0 [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_MASK               0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_SHIFT              24
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT      12
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: POWERUP_CKE_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_MASK       0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_SHIFT      10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_DEFAULT    94
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: DLL_LOCK_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_MASK          0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_SHIFT         0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_DEFAULT       512
+
+/***************************************************************************
+ *DRAM_TIMING_4 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: PRECHARGE_ALL_DELAY [28:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_MASK     0x1f000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_SHIFT    24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_DEFAULT  8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: LOAD_MODE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_DEFAULT      12
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: REFRESH_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_MASK           0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_SHIFT          10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT        88
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_MASK           0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT          0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT        512
+
+/***************************************************************************
+ *DRAM_TIMING_5 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_ASSETION_DELAY [28:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_MASK      0x1ff80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_SHIFT     19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_DEFAULT   261
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [18:15] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK           0x00078000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT          15
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT        3
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [14:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK         0x00007c00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT        10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT      13
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK      0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT     0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT   512
+
+/***************************************************************************
+ *CNTRLR_START_SEQ - Memory Controller Sequencer Enable
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: START_SEQ [00:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_SHIFT           0
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_DEFAULT         0
+
+/***************************************************************************
+ *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_MASK           0xfffe0000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_SHIFT          17
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_MASK              0x00010000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT             16
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT           0
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT            65535
+
+/***************************************************************************
+ *BANK_STATUS - Memory Controller, Bank Status Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: BANK_STATUS :: reserved0 [31:08] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_SHIFT                8
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK7_STATUS [07:07] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_SHIFT             7
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK6_STATUS [06:06] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_SHIFT             6
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK5_STATUS [05:05] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_MASK              0x00000020
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_SHIFT             5
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK4_STATUS [04:04] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_MASK              0x00000010
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_SHIFT             4
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK3_STATUS [03:03] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_MASK              0x00000008
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_SHIFT             3
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK2_STATUS [02:02] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_MASK              0x00000004
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_SHIFT             2
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK1_STATUS [01:01] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_SHIFT             1
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK0_STATUS [00:00] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_MASK              0x00000001
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_SHIFT             0
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_DEFAULT           1
+
+/***************************************************************************
+ *TESTER_LATENCY - Memory Controller, Tester Latency Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: TESTER_LATENCY :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_MASK              0xffffff80
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_SHIFT             7
+
+/* MEMC_DDR_0 :: TESTER_LATENCY :: TLATENCY_SEL [06:00] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_MASK           0x0000007f
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_SHIFT          0
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_DEFAULT        0
+
+/***************************************************************************
+ *DTPM_BYTE0 - Memory Controller, DATA_PINMAP_BYTE0_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE1 - Memory Controller, DATA_PINMAP_BYTE1_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE2 - Memory Controller, DATA_PINMAP_BYTE2_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE3 - Memory Controller, DATA_PINMAP_BYTE3_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_DDR3_RESET_PERIOD - Memory Controller, DDR3 DRAM reset Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: reserved0 [31:20] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_MASK      0xfff00000
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_SHIFT     20
+
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: DRAM_RESET_PERIOD [19:00] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_MASK 0x000fffff
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_SHIFT 0
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_DEFAULT 43200
+
+/***************************************************************************
+ *STAT_CONTROL - Statistics Control register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CONTROL :: reserved0 [31:09] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_MASK                0xfffffe00
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_SHIFT               9
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: COUNTER_MODE [08:08] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_SHIFT            8
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_DEFAULT          0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT    1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_NORMAL           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: STAT_ENABLE [07:07] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_SHIFT             7
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DEFAULT           0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_ENABLE            1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DISABLE           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: CLIENT_ID [06:00] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_MASK                0x0000007f
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_DEFAULT             0
+
+/***************************************************************************
+ *STAT_TIMER - Statistics Timer
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TIMER :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_MASK                      0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_SHIFT                     0
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_DEFAULT                   0
+
+/***************************************************************************
+ *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_MASK                   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_DEFAULT                0
+
+/***************************************************************************
+ *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_ALL - CAS Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_DEFAULT                 0
+
+/***************************************************************************
+ *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_PENALTY_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT    0
+
+/***************************************************************************
+ *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_MASK            0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_SHIFT           0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT         0
+
+/***************************************************************************
+ *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_DEFAULT           4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_MASK         0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT        0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT      0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT  4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT  0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_REFRESH - Total number of refreshes issuedr.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_REFRESH :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_DEFAULT                 0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_0 - CAS cycle count register for client 0.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_1 - CAS cycle count register for client 1.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_2 - CAS cycle count register for client 2.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_3 - CAS cycle count register for client 3.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_4 - CAS cycle count register for client 4.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_5 - CAS cycle count register for client 5.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_6 - CAS cycle count register for client 6.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_7 - CAS cycle count register for client 7.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_8 - CAS cycle count register for client 8.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_9 - CAS cycle count register for client 9.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_10 - CAS cycle count register for client 10.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_11 - CAS cycle count register for client 11.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_12 - CAS cycle count register for client 12.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_13 - CAS cycle count register for client 13.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_14 - CAS cycle count register for client 14.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_15 - CAS cycle count register for client 15.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_16 - CAS cycle count register for client 16.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_17 - CAS cycle count register for client 17.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_18 - CAS cycle count register for client 18.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_19 - CAS cycle count register for client 19.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_20 - CAS cycle count register for client 20.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_21 - CAS cycle count register for client 21.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_22 - CAS cycle count register for client 22.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_23 - CAS cycle count register for client 23.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_24 - CAS cycle count register for client 24.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_25 - CAS cycle count register for client 25.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_26 - CAS cycle count register for client 26.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_27 - CAS cycle count register for client 27.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_28 - CAS cycle count register for client 28.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_29 - CAS cycle count register for client 29.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_30 - CAS cycle count register for client 30.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_31 - CAS cycle count register for client 31.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_32 - CAS cycle count register for client 32.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_33 - CAS cycle count register for client 33.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_34 - CAS cycle count register for client 34.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_35 - CAS cycle count register for client 35.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_36 - CAS cycle count register for client 36.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_37 - CAS cycle count register for client 37.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_38 - CAS cycle count register for client 38.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_39 - CAS cycle count register for client 39.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_40 - CAS cycle count register for client 40.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_41 - CAS cycle count register for client 41.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_42 - CAS cycle count register for client 42.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_43 - CAS cycle count register for client 43.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_44 - CAS cycle count register for client 44.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_45 - CAS cycle count register for client 45.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_46 - CAS cycle count register for client 46.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_47 - CAS cycle count register for client 47.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_48 - CAS cycle count register for client 48.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_49 - CAS cycle count register for client 49.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_50 - CAS cycle count register for client 50.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_51 - CAS cycle count register for client 51.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_52 - CAS cycle count register for client 52.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_53 - CAS cycle count register for client 53.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_54 - CAS cycle count register for client 54.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_55 - CAS cycle count register for client 55.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_56 - CAS cycle count register for client 56.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_57 - CAS cycle count register for client 57.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_58 - CAS cycle count register for client 58.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_59 - CAS cycle count register for client 59.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_60 - CAS cycle count register for client 60.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_61 - CAS cycle count register for client 61.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_62 - CAS cycle count register for client 62.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_63 - CAS cycle count register for client 63.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_64 - CAS cycle count register for client 64.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_65 - CAS cycle count register for client 65.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_66 - CAS cycle count register for client 66.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_67 - CAS cycle count register for client 67.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_68 - CAS cycle count register for client 68.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_69 - CAS cycle count register for client 69.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_70 - CAS cycle count register for client 70.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_71 - CAS cycle count register for client 71.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_72 - CAS cycle count register for client 72.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_73 - CAS cycle count register for client 73.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_74 - CAS cycle count register for client 74.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_75 - CAS cycle count register for client 75.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_76 - CAS cycle count register for client 76.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_77 - CAS cycle count register for client 77.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_78 - CAS cycle count register for client 78.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_79 - CAS cycle count register for client 79.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_80 - CAS cycle count register for client 80.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_81 - CAS cycle count register for client 81.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_82 - CAS cycle count register for client 82.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_83 - CAS cycle count register for client 83.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_84 - CAS cycle count register for client 84.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_85 - CAS cycle count register for client 85.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_86 - CAS cycle count register for client 86.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_87 - CAS cycle count register for client 87.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_88 - CAS cycle count register for client 88.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_89 - CAS cycle count register for client 89.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_90 - CAS cycle count register for client 90.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_91 - CAS cycle count register for client 91.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_92 - CAS cycle count register for client 92.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_93 - CAS cycle count register for client 93.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_94 - CAS cycle count register for client 94.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_95 - CAS cycle count register for client 95.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_96 - CAS cycle count register for client 96.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_97 - CAS cycle count register for client 97.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_98 - CAS cycle count register for client 98.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_99 - CAS cycle count register for client 99.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_100 - CAS cycle count register for client 100.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_101 - CAS cycle count register for client 101.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_102 - CAS cycle count register for client 102.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_103 - CAS cycle count register for client 103.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_104 - CAS cycle count register for client 104.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_105 - CAS cycle count register for client 105.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_106 - CAS cycle count register for client 106.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_107 - CAS cycle count register for client 107.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_108 - CAS cycle count register for client 108.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_109 - CAS cycle count register for client 109.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_110 - CAS cycle count register for client 110.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_111 - CAS cycle count register for client 111.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_112 - CAS cycle count register for client 112.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_113 - CAS cycle count register for client 113.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_114 - CAS cycle count register for client 114.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_115 - CAS cycle count register for client 115.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_116 - CAS cycle count register for client 116.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_117 - CAS cycle count register for client 117.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_118 - CAS cycle count register for client 118.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_119 - CAS cycle count register for client 119.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_120 - CAS cycle count register for client 120.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_121 - CAS cycle count register for client 121.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_122 - CAS cycle count register for client 122.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_123 - CAS cycle count register for client 123.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_124 - CAS cycle count register for client 124.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_125 - CAS cycle count register for client 125.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_126 - CAS cycle count register for client 126.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_127 - CAS cycle count register for client 127.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_DEFAULT             4294967295
+
+/***************************************************************************
+ *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT    4294967295
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_CONTROL - MEMSYS Auto Init Control.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: reserved0 [31:10] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_MASK    0xfffffc00
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_SHIFT   10
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_DIVIDER [09:09] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_MASK 0x00000200
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_SHIFT 9
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_VDL_CALIB_AUTO_INIT [08:08] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_MASK 0x00000100
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_SHIFT 8
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_DRAM_INIT_DONE_SET [07:07] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_MASK 0x00000080
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_SHIFT 7
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_RESET [06:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_MASK 0x00000040
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_SET [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_READY_SET [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_AUTO_INIT_ACTIVE_RESET [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_MASK 0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_SHIFT 3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: SKIP_PHY_AUTO_INIT [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: MEMSYS_AUTO_INIT_START [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_STATUS - MEMSYS Auto Init Status.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_MASK     0xfffff000
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_SHIFT    12
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMC_AUTO_INIT_STATES [11:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_MASK 0x00000fc0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: AUTO_INIT_ACTIVE [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_STRAP_VALID [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_READY [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_MASK     0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_SHIFT    3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_DEFAULT  0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: DRAM_INIT_DONE [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_FAIL [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_DEFAULT 0
+
+/***************************************************************************
+ *PHY_VDL_CALIB_AUTO_INIT_OVERRIDE - PHY VDL calibrate override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PHY_VDL_CALIB_AUTO_INIT_OVERRIDE :: PHY_VDL_CALIB_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_DEFAULT 268435456
+
+/***************************************************************************
+ *SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE - SHIM PLL pndiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_PNDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_DEFAULT 598736896
+
+/***************************************************************************
+ *SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE - SHIM PLL mdiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_MDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_DEFAULT 4099
+
+/***************************************************************************
+ *DYN_VDL_CMD_DLY - Dynamic VDL shmoo command delay.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_MASK             0xfffff000
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_SHIFT            12
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: END_CAS_DLY [11:06] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_MASK           0x00000fc0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_SHIFT          6
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_DEFAULT        0
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: START_CAS_DLY [05:00] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_MASK         0x0000003f
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_SHIFT        0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_DEFAULT      0
+
+#endif /* #ifndef BCHP_MEMC_DDR_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_moca_hostmisc.h b/include/linux/brcmstb/7346b0/bchp_moca_hostmisc.h
new file mode 100644
index 0000000..3bc447e
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_moca_hostmisc.h
@@ -0,0 +1,195 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:17:58 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_moca_hostmisc.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 4:45p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MOCA_HOSTMISC_H__
+#define BCHP_MOCA_HOSTMISC_H__
+
+/***************************************************************************
+ *MOCA_HOSTMISC - MOCA_HOSTMISC registers
+ ***************************************************************************/
+#define BCHP_MOCA_HOSTMISC_SW_RESET              0x002a2040 /* Moca Software Reset */
+#define BCHP_MOCA_HOSTMISC_SCRATCH               0x002a2044 /* Moca Scratch Register */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG      0x002a204c /* MoCA version register */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP0             0x002a2050 /* Moca Host Messaging Register 0 */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP1             0x002a2054 /* Moca Host Messaging Register 1 */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP2             0x002a2058 /* Moca Host Messaging Register 2 */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP3             0x002a205c /* Moca Host Messaging Register 3 */
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG          0x002a2060 /* Host-to-MoCA Interrupt Trigger */
+#define BCHP_MOCA_HOSTMISC_WAKEUP                0x002a2064 /* Host-to-MoCA Wakeup Interrupt */
+
+/***************************************************************************
+ *SW_RESET - Moca Software Reset
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: SW_RESET :: spare_control [31:15] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_control_MASK             0xffff8000
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_control_SHIFT            15
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_control_DEFAULT          131071
+
+/* MOCA_HOSTMISC :: SW_RESET :: spare_status [14:08] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_status_MASK              0x00007f00
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_status_SHIFT             8
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_status_DEFAULT           127
+
+/* MOCA_HOSTMISC :: SW_RESET :: moca_disable_clocks [07:07] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_disable_clocks_MASK       0x00000080
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_disable_clocks_SHIFT      7
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_disable_clocks_DEFAULT    0
+
+/* MOCA_HOSTMISC :: SW_RESET :: spare_reset2 [06:04] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset2_MASK              0x00000070
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset2_SHIFT             4
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset2_DEFAULT           7
+
+/* MOCA_HOSTMISC :: SW_RESET :: moca_gmii_sw_init [03:03] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_gmii_sw_init_MASK         0x00000008
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_gmii_sw_init_SHIFT        3
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_gmii_sw_init_DEFAULT      0
+
+/* MOCA_HOSTMISC :: SW_RESET :: spare_reset [02:02] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset_MASK               0x00000004
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset_SHIFT              2
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset_DEFAULT            1
+
+/* MOCA_HOSTMISC :: SW_RESET :: moca_sys_reset [01:01] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_sys_reset_MASK            0x00000002
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_sys_reset_SHIFT           1
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_sys_reset_DEFAULT         1
+
+/* MOCA_HOSTMISC :: SW_RESET :: moca_cpu_reset [00:00] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_cpu_reset_MASK            0x00000001
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_cpu_reset_SHIFT           0
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_cpu_reset_DEFAULT         1
+
+/***************************************************************************
+ *SCRATCH - Moca Scratch Register
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: SCRATCH :: VALUE [31:00] */
+#define BCHP_MOCA_HOSTMISC_SCRATCH_VALUE_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_SCRATCH_VALUE_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_SCRATCH_VALUE_DEFAULT                   0
+
+/***************************************************************************
+ *MOCA_VERSION_REG - MoCA version register
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: MOCA_VERSION_REG :: moca_id [31:16] */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_id_MASK           0xffff0000
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_id_SHIFT          16
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_id_DEFAULT        26146
+
+/* MOCA_HOSTMISC :: MOCA_VERSION_REG :: moca_spec_ver [15:12] */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_spec_ver_MASK     0x0000f000
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_spec_ver_SHIFT    12
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_spec_ver_DEFAULT  1
+
+/* MOCA_HOSTMISC :: MOCA_VERSION_REG :: core_version [11:08] */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_version_MASK      0x00000f00
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_version_SHIFT     8
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_version_DEFAULT   1
+
+/* MOCA_HOSTMISC :: MOCA_VERSION_REG :: core_revision [07:04] */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_revision_MASK     0x000000f0
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_revision_SHIFT    4
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_revision_DEFAULT  1
+
+/* MOCA_HOSTMISC :: MOCA_VERSION_REG :: core_mask [03:00] */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_mask_MASK         0x0000000f
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_mask_SHIFT        0
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_mask_DEFAULT      0
+
+/***************************************************************************
+ *HOST_MMP0 - Moca Host Messaging Register 0
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: HOST_MMP0 :: MMP [31:00] */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP0_MMP_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_HOST_MMP0_MMP_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_HOST_MMP0_MMP_DEFAULT                   0
+
+/***************************************************************************
+ *HOST_MMP1 - Moca Host Messaging Register 1
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: HOST_MMP1 :: MMP [31:00] */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP1_MMP_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_HOST_MMP1_MMP_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_HOST_MMP1_MMP_DEFAULT                   0
+
+/***************************************************************************
+ *HOST_MMP2 - Moca Host Messaging Register 2
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: HOST_MMP2 :: MMP [31:00] */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP2_MMP_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_HOST_MMP2_MMP_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_HOST_MMP2_MMP_DEFAULT                   0
+
+/***************************************************************************
+ *HOST_MMP3 - Moca Host Messaging Register 3
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: HOST_MMP3 :: MMP [31:00] */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP3_MMP_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_HOST_MMP3_MMP_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_HOST_MMP3_MMP_DEFAULT                   0
+
+/***************************************************************************
+ *H2M_INT_TRIG - Host-to-MoCA Interrupt Trigger
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_INT_TRIG :: reserved0 [31:08] */
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_reserved0_MASK             0xffffff00
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_reserved0_SHIFT            8
+
+/* MOCA_HOSTMISC :: H2M_INT_TRIG :: INT_TRIG [07:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_MASK              0x000000ff
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_SHIFT             0
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_DEFAULT           0
+
+/***************************************************************************
+ *WAKEUP - Host-to-MoCA Wakeup Interrupt
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: WAKEUP :: reserved0 [31:01] */
+#define BCHP_MOCA_HOSTMISC_WAKEUP_reserved0_MASK                   0xfffffffe
+#define BCHP_MOCA_HOSTMISC_WAKEUP_reserved0_SHIFT                  1
+
+/* MOCA_HOSTMISC :: WAKEUP :: wakeup_int [00:00] */
+#define BCHP_MOCA_HOSTMISC_WAKEUP_wakeup_int_MASK                  0x00000001
+#define BCHP_MOCA_HOSTMISC_WAKEUP_wakeup_int_SHIFT                 0
+#define BCHP_MOCA_HOSTMISC_WAKEUP_wakeup_int_DEFAULT               0
+
+#endif /* #ifndef BCHP_MOCA_HOSTMISC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_nand.h b/include/linux/brcmstb/7346b0/bchp_nand.h
new file mode 100644
index 0000000..37c451b
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_nand.h
@@ -0,0 +1,2486 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:29:45 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_nand.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 4:51p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_NAND_H__
+#define BCHP_NAND_H__
+
+/***************************************************************************
+ *NAND - Nand Flash Control Registers
+ ***************************************************************************/
+#define BCHP_NAND_REVISION                       0x00412800 /* NAND Revision */
+#define BCHP_NAND_CMD_START                      0x00412804 /* Nand Flash Command Start */
+#define BCHP_NAND_CMD_EXT_ADDRESS                0x00412808 /* Nand Flash Command Extended Address */
+#define BCHP_NAND_CMD_ADDRESS                    0x0041280c /* Nand Flash Command Address */
+#define BCHP_NAND_CMD_END_ADDRESS                0x00412810 /* Nand Flash Command End Address */
+#define BCHP_NAND_CS_NAND_SELECT                 0x00412814 /* Nand Flash EBI CS Select */
+#define BCHP_NAND_CS_NAND_XOR                    0x00412818 /* Nand Flash EBI CS Address XOR with 1FC0 Control */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0          0x00412820 /* Nand Flash Spare Area Read Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4          0x00412824 /* Nand Flash Spare Area Read Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8          0x00412828 /* Nand Flash Spare Area Read Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C          0x0041282c /* Nand Flash Spare Area Read Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0         0x00412830 /* Nand Flash Spare Area Write Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4         0x00412834 /* Nand Flash Spare Area Write Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8         0x00412838 /* Nand Flash Spare Area Write Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C         0x0041283c /* Nand Flash Spare Area Write Bytes 12-15 */
+#define BCHP_NAND_ACC_CONTROL                    0x00412840 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG                         0x00412848 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1                       0x00412850 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2                       0x00412854 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SEMAPHORE                      0x00412858 /* Semaphore */
+#define BCHP_NAND_FLASH_DEVICE_ID                0x00412860 /* Nand Flash Device ID */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT            0x00412864 /* Nand Flash Extended Device ID */
+#define BCHP_NAND_BLOCK_LOCK_STATUS              0x00412868 /* Nand Flash Block Lock Status */
+#define BCHP_NAND_INTFC_STATUS                   0x0041286c /* Nand Flash Interface Status */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR              0x00412870 /* ECC Correctable Error Extended Address */
+#define BCHP_NAND_ECC_CORR_ADDR                  0x00412874 /* ECC Correctable Error Address */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR               0x00412878 /* ECC Uncorrectable Error Extended Address */
+#define BCHP_NAND_ECC_UNC_ADDR                   0x0041287c /* ECC Uncorrectable Error Address */
+#define BCHP_NAND_READ_ERROR_COUNT               0x00412880 /* Read Error Count */
+#define BCHP_NAND_CORR_STAT_THRESHOLD            0x00412884 /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_ONFI_STATUS                    0x00412888 /* ONFI Status */
+#define BCHP_NAND_ONFI_DEBUG_DATA                0x0041288c /* ONFI Debug Data */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR            0x00412890 /* Flash Read Data Extended Address */
+#define BCHP_NAND_FLASH_READ_ADDR                0x00412894 /* Flash Read Data Address */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR          0x00412898 /* Page Program Extended Address */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR              0x0041289c /* Page Program Address */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR             0x004128a0 /* Copy Back Extended Address */
+#define BCHP_NAND_COPY_BACK_ADDR                 0x004128a4 /* Copy Back Address */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR           0x004128a8 /* Block Erase Extended Address */
+#define BCHP_NAND_BLOCK_ERASE_ADDR               0x004128ac /* Block Erase Address */
+#define BCHP_NAND_INV_READ_EXT_ADDR              0x004128b0 /* Flash Invalid Data Extended Address */
+#define BCHP_NAND_INV_READ_ADDR                  0x004128b4 /* Flash Invalid Data Address */
+#define BCHP_NAND_BLK_WR_PROTECT                 0x004128c0 /* Block Write Protect Enable and Size for EBI_CS0b */
+#define BCHP_NAND_ACC_CONTROL_CS1                0x004128d0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS1                     0x004128d4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS1                   0x004128d8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS1                   0x004128dc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS2                0x004128e0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS2                     0x004128e4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS2                   0x004128e8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS2                   0x004128ec /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS3                0x004128f0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS3                     0x004128f4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS3                   0x004128f8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS3                   0x004128fc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS4                0x00412900 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS4                     0x00412904 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS4                   0x00412908 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS4                   0x0041290c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS5                0x00412910 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS5                     0x00412914 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS5                   0x00412918 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS5                   0x0041291c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10         0x00412930 /* Nand Flash Spare Area Read Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14         0x00412934 /* Nand Flash Spare Area Read Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18         0x00412938 /* Nand Flash Spare Area Read Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C         0x0041293c /* Nand Flash Spare Area Read Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10        0x00412940 /* Nand Flash Spare Area Write Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14        0x00412944 /* Nand Flash Spare Area Write Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18        0x00412948 /* Nand Flash Spare Area Write Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C        0x0041294c /* Nand Flash Spare Area Write Bytes 28-31 */
+#define BCHP_NAND_LL_OP                          0x00412978 /* Nand Flash Low Level Operation */
+#define BCHP_NAND_LL_RDDATA                      0x0041297c /* Nand Flash Low Level Read Data */
+
+/***************************************************************************
+ *REVISION - NAND Revision
+ ***************************************************************************/
+/* NAND :: REVISION :: 8KB_PAGE_SUPPORT [31:31] */
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_MASK                   0x80000000
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_SHIFT                  31
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_DEFAULT                1
+
+/* NAND :: REVISION :: reserved0 [30:16] */
+#define BCHP_NAND_REVISION_reserved0_MASK                          0x7fff0000
+#define BCHP_NAND_REVISION_reserved0_SHIFT                         16
+
+/* NAND :: REVISION :: MAJOR [15:08] */
+#define BCHP_NAND_REVISION_MAJOR_MASK                              0x0000ff00
+#define BCHP_NAND_REVISION_MAJOR_SHIFT                             8
+#define BCHP_NAND_REVISION_MAJOR_DEFAULT                           5
+
+/* NAND :: REVISION :: MINOR [07:00] */
+#define BCHP_NAND_REVISION_MINOR_MASK                              0x000000ff
+#define BCHP_NAND_REVISION_MINOR_SHIFT                             0
+#define BCHP_NAND_REVISION_MINOR_DEFAULT                           0
+
+/***************************************************************************
+ *CMD_START - Nand Flash Command Start
+ ***************************************************************************/
+/* NAND :: CMD_START :: reserved0 [31:29] */
+#define BCHP_NAND_CMD_START_reserved0_MASK                         0xe0000000
+#define BCHP_NAND_CMD_START_reserved0_SHIFT                        29
+
+/* NAND :: CMD_START :: OPCODE [28:24] */
+#define BCHP_NAND_CMD_START_OPCODE_MASK                            0x1f000000
+#define BCHP_NAND_CMD_START_OPCODE_SHIFT                           24
+#define BCHP_NAND_CMD_START_OPCODE_DEFAULT                         0
+#define BCHP_NAND_CMD_START_OPCODE_NULL                            0
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ                       1
+#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ                 2
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ                     3
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE                    4
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA              5
+#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK                       6
+#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ                  7
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE                     8
+#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET                     9
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK                     10
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN                11
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK                   12
+#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS         13
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ                  14
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL            15
+#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP                    16
+
+/* NAND :: CMD_START :: reserved1 [23:00] */
+#define BCHP_NAND_CMD_START_reserved1_MASK                         0x00ffffff
+#define BCHP_NAND_CMD_START_reserved1_SHIFT                        0
+
+/***************************************************************************
+ *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
+ ***************************************************************************/
+/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK                   0xfff80000
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT                  19
+
+/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK                      0x00070000
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT                     16
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT                   0
+
+/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK                 0x0000ffff
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT                0
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT              0
+
+/***************************************************************************
+ *CMD_ADDRESS - Nand Flash Command Address
+ ***************************************************************************/
+/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK                         0xffffffff
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT                        0
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT                      0
+
+/***************************************************************************
+ *CMD_END_ADDRESS - Nand Flash Command End Address
+ ***************************************************************************/
+/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT                    0
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT                  0
+
+/***************************************************************************
+ *CS_NAND_SELECT - Nand Flash EBI CS Select
+ ***************************************************************************/
+/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT                     31
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT                   0
+
+/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK        0x40000000
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT       30
+
+/* NAND :: CS_NAND_SELECT :: reserved0 [29:29] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK                    0x20000000
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT                   29
+
+/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK              0x10000000
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT             28
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT           0
+
+/* NAND :: CS_NAND_SELECT :: reserved1 [27:16] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_MASK                    0x0fff0000
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_SHIFT                   16
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK           0x00008000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT          15
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK           0x00004000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT          14
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK           0x00002000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT          13
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK           0x00001000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT          12
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK           0x00000800
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT          11
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK           0x00000400
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT          10
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK           0x00000200
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT          9
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK           0x00000100
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT          8
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK                 0x00000080
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT                7
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK                 0x00000040
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT                6
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK                 0x00000020
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT                5
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK                 0x00000010
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT                4
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK                 0x00000008
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT                3
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK                 0x00000004
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT                2
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK                 0x00000002
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT                1
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK                 0x00000001
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT                0
+
+/***************************************************************************
+ *CS_NAND_XOR - Nand Flash EBI CS Address XOR with 1FC0 Control
+ ***************************************************************************/
+/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_1FC0_XOR [31:31] */
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_MASK           0x80000000
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_SHIFT          31
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_DEFAULT        0
+
+/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
+#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK                       0x7fffff00
+#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT                      8
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_1FC0_XOR [07:07] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_MASK          0x00000080
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_SHIFT         7
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_1FC0_XOR [06:06] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_MASK          0x00000040
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_SHIFT         6
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_1FC0_XOR [05:05] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_MASK          0x00000020
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_SHIFT         5
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_1FC0_XOR [04:04] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_MASK          0x00000010
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_SHIFT         4
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_1FC0_XOR [03:03] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_MASK          0x00000008
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_SHIFT         3
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_1FC0_XOR [02:02] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_MASK          0x00000004
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_SHIFT         2
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_1FC0_XOR [01:01] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_MASK          0x00000002
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_SHIFT         1
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_1FC0_XOR [00:00] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_MASK          0x00000001
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_SHIFT         0
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT         255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT         255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT       255
+
+/***************************************************************************
+ *ACC_CONTROL - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_MASK                       0x80000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_SHIFT                      31
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_DEFAULT                    1
+
+/* NAND :: ACC_CONTROL :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_MASK                       0x40000000
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_SHIFT                      30
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_DEFAULT                    1
+
+/* NAND :: ACC_CONTROL :: RD_ECC_BLK0_EN [29:29] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_MASK                  0x20000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_SHIFT                 29
+
+/* NAND :: ACC_CONTROL :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_SHIFT                  28
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_MASK                0x08000000
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_SHIFT               27
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_DEFAULT             0
+
+/* NAND :: ACC_CONTROL :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_MASK                 0x04000000
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_SHIFT                26
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_MASK                   0x02000000
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_SHIFT                  25
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_MASK                     0x01000000
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_SHIFT                    24
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_DEFAULT                  1
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL_0 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_MASK                     0x00f00000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_SHIFT                    20
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_DEFAULT                  15
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_MASK                       0x000f0000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_SHIFT                      16
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_DEFAULT                    15
+
+/* NAND :: ACC_CONTROL :: reserved0 [15:15] */
+#define BCHP_NAND_ACC_CONTROL_reserved0_MASK                       0x00008000
+#define BCHP_NAND_ACC_CONTROL_reserved0_SHIFT                      15
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K_0 [14:14] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_MASK                0x00004000
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_SHIFT               14
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_DEFAULT             0
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE_0 [13:08] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_MASK               0x00003f00
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_SHIFT              8
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_DEFAULT            16
+
+/* NAND :: ACC_CONTROL :: reserved1 [07:07] */
+#define BCHP_NAND_ACC_CONTROL_reserved1_MASK                       0x00000080
+#define BCHP_NAND_ACC_CONTROL_reserved1_SHIFT                      7
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_MASK                  0x00000040
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_SHIFT                 6
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_DEFAULT               0
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_MASK                 0x0000003f
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_SHIFT                0
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_DEFAULT              16
+
+/***************************************************************************
+ *CONFIG - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_MASK                          0x80000000
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_SHIFT                         31
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_DEFAULT                       0
+
+/* NAND :: CONFIG :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_MASK                           0x70000000
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_SHIFT                          28
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_2048KB                 6
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_1024KB                 5
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_512KB                  3
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_128KB                  1
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_16KB                   0
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_8KB                    2
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_256KB                  4
+
+/* NAND :: CONFIG :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_MASK                          0x0f000000
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_SHIFT                         24
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4MB                  0
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8MB                  1
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16MB                 2
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32MB                 3
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64MB                 4
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128MB                5
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_256MB                6
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_512MB                7
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_1GB                  8
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_2GB                  9
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4GB                  10
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8GB                  11
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16GB                 12
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32GB                 13
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64GB                 14
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128GB                15
+
+/* NAND :: CONFIG :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_MASK                         0x00800000
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_SHIFT                        23
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_8                  0
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_16                 1
+
+/* NAND :: CONFIG :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_reserved0_MASK                            0x00400000
+#define BCHP_NAND_CONFIG_reserved0_SHIFT                           22
+
+/* NAND :: CONFIG :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_PAGE_SIZE_MASK                            0x00300000
+#define BCHP_NAND_CONFIG_PAGE_SIZE_SHIFT                           20
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_512                     0
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_2KB                     1
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_4KB                     2
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_8KB                     3
+
+/* NAND :: CONFIG :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_reserved1_MASK                            0x00080000
+#define BCHP_NAND_CONFIG_reserved1_SHIFT                           19
+
+/* NAND :: CONFIG :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_MASK                        0x00070000
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_SHIFT                       16
+
+/* NAND :: CONFIG :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_reserved2_MASK                            0x00008000
+#define BCHP_NAND_CONFIG_reserved2_SHIFT                           15
+
+/* NAND :: CONFIG :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_MASK                        0x00007000
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_SHIFT                       12
+
+/* NAND :: CONFIG :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_reserved3_MASK                            0x00000800
+#define BCHP_NAND_CONFIG_reserved3_SHIFT                           11
+
+/* NAND :: CONFIG :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_MASK                        0x00000700
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_SHIFT                       8
+
+/* NAND :: CONFIG :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_reserved4_MASK                            0x000000ff
+#define BCHP_NAND_CONFIG_reserved4_SHIFT                           0
+
+/***************************************************************************
+ *TIMING_1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_tWP_MASK                                0xf0000000
+#define BCHP_NAND_TIMING_1_tWP_SHIFT                               28
+#define BCHP_NAND_TIMING_1_tWP_DEFAULT                             6
+
+/* NAND :: TIMING_1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_tWH_MASK                                0x0f000000
+#define BCHP_NAND_TIMING_1_tWH_SHIFT                               24
+#define BCHP_NAND_TIMING_1_tWH_DEFAULT                             5
+
+/* NAND :: TIMING_1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_tRP_MASK                                0x00f00000
+#define BCHP_NAND_TIMING_1_tRP_SHIFT                               20
+#define BCHP_NAND_TIMING_1_tRP_DEFAULT                             7
+
+/* NAND :: TIMING_1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_tREH_MASK                               0x000f0000
+#define BCHP_NAND_TIMING_1_tREH_SHIFT                              16
+#define BCHP_NAND_TIMING_1_tREH_DEFAULT                            4
+
+/* NAND :: TIMING_1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_tCS_MASK                                0x0000f000
+#define BCHP_NAND_TIMING_1_tCS_SHIFT                               12
+#define BCHP_NAND_TIMING_1_tCS_DEFAULT                             8
+
+/* NAND :: TIMING_1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_tCLH_MASK                               0x00000f00
+#define BCHP_NAND_TIMING_1_tCLH_SHIFT                              8
+#define BCHP_NAND_TIMING_1_tCLH_DEFAULT                            4
+
+/* NAND :: TIMING_1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_tALH_MASK                               0x000000f0
+#define BCHP_NAND_TIMING_1_tALH_SHIFT                              4
+#define BCHP_NAND_TIMING_1_tALH_DEFAULT                            5
+
+/* NAND :: TIMING_1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_tADL_MASK                               0x0000000f
+#define BCHP_NAND_TIMING_1_tADL_SHIFT                              0
+#define BCHP_NAND_TIMING_1_tADL_DEFAULT                            11
+
+/***************************************************************************
+ *TIMING_2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CLK_SELECT_MASK                         0x80000000
+#define BCHP_NAND_TIMING_2_CLK_SELECT_SHIFT                        31
+#define BCHP_NAND_TIMING_2_CLK_SELECT_DEFAULT                      0
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_108                      0
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_216                      1
+
+/* NAND :: TIMING_2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_reserved0_MASK                          0x7fffe000
+#define BCHP_NAND_TIMING_2_reserved0_SHIFT                         13
+
+/* NAND :: TIMING_2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_tWB_MASK                                0x00001e00
+#define BCHP_NAND_TIMING_2_tWB_SHIFT                               9
+#define BCHP_NAND_TIMING_2_tWB_DEFAULT                             15
+
+/* NAND :: TIMING_2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_tWHR_MASK                               0x000001f0
+#define BCHP_NAND_TIMING_2_tWHR_SHIFT                              4
+#define BCHP_NAND_TIMING_2_tWHR_DEFAULT                            9
+
+/* NAND :: TIMING_2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_tREAD_MASK                              0x0000000f
+#define BCHP_NAND_TIMING_2_tREAD_SHIFT                             0
+#define BCHP_NAND_TIMING_2_tREAD_DEFAULT                           6
+
+/***************************************************************************
+ *SEMAPHORE - Semaphore
+ ***************************************************************************/
+/* NAND :: SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_NAND_SEMAPHORE_reserved0_MASK                         0xffffff00
+#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT                        8
+
+/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK                    0x000000ff
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT                   0
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT                 0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID - Nand Flash Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK                      0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT                     24
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK                      0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT                     16
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK                      0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT                     8
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK                      0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT                     0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK                  0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT                 24
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK                  0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT                 16
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK                  0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT                 8
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK                  0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT                 0
+
+/***************************************************************************
+ *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
+ ***************************************************************************/
+/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT                8
+
+/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK                    0x000000ff
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT                   0
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT                 0
+
+/***************************************************************************
+ *INTFC_STATUS - Nand Flash Interface Status
+ ***************************************************************************/
+/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK                     0x80000000
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT                    31
+
+/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK                    0x40000000
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT                   30
+
+/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK                    0x20000000
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT                   29
+
+/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK               0x10000000
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT              28
+
+/* NAND :: INTFC_STATUS :: ERASED [27:27] */
+#define BCHP_NAND_INTFC_STATUS_ERASED_MASK                         0x08000000
+#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT                        27
+
+/* NAND :: INTFC_STATUS :: reserved0 [26:08] */
+#define BCHP_NAND_INTFC_STATUS_reserved0_MASK                      0x07ffff00
+#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT                     8
+
+/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK                   0x000000ff
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT                  0
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT                0
+
+/***************************************************************************
+ *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT                 0
+
+/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT            0
+
+/***************************************************************************
+ *ECC_CORR_ADDR - ECC Correctable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT                    0
+
+/***************************************************************************
+ *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK                  0xfff80000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT                 19
+
+/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK                     0x00070000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT                    16
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT                  0
+
+/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK                0x0000ffff
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT               0
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT             0
+
+/***************************************************************************
+ *ECC_UNC_ADDR - ECC Uncorrectable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK                        0xffffffff
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT                       0
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT                     0
+
+/***************************************************************************
+ *READ_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT        0
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:05] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK               0xffffffe0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT              5
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD [04:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_MASK     0x0000001f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_SHIFT    0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_DEFAULT  1
+
+/***************************************************************************
+ *ONFI_STATUS - ONFI Status
+ ***************************************************************************/
+/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK                  0xf0000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT                 28
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT               0
+
+/* NAND :: ONFI_STATUS :: reserved0 [27:06] */
+#define BCHP_NAND_ONFI_STATUS_reserved0_MASK                       0x0fffffc0
+#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT                      6
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK              0x00000020
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT             5
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK              0x00000010
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT             4
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK              0x00000008
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT             3
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK              0x00000004
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT             2
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK              0x00000002
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT             1
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK              0x00000001
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT             0
+
+/***************************************************************************
+ *ONFI_DEBUG_DATA - ONFI Debug Data
+ ***************************************************************************/
+/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK             0xffffffff
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT            0
+
+/***************************************************************************
+ *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK               0xfff80000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT              19
+
+/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK                  0x00070000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT                 16
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT               0
+
+/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK             0x0000ffff
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT            0
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT          0
+
+/***************************************************************************
+ *FLASH_READ_ADDR - Flash Read Data Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT                    0
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT                  0
+
+/***************************************************************************
+ *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK             0xfff80000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT            19
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK                0x00070000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT               16
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT             0
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK           0x0000ffff
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT          0
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT        0
+
+/***************************************************************************
+ *PROGRAM_PAGE_ADDR - Page Program Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK                   0xffffffff
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT                  0
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT                0
+
+/***************************************************************************
+ *COPY_BACK_EXT_ADDR - Copy Back Extended Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK                0xfff80000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT               19
+
+/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK                   0x00070000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT                  16
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT                0
+
+/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK              0x0000ffff
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT             0
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT           0
+
+/***************************************************************************
+ *COPY_BACK_ADDR - Copy Back Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK                      0xffffffff
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT                     0
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT                   0
+
+/***************************************************************************
+ *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK              0xfff80000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT             19
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK                 0x00070000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT                16
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT              0
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK            0x0000ffff
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT           0
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT         0
+
+/***************************************************************************
+ *BLOCK_ERASE_ADDR - Block Erase Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK                    0xffffffff
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT                   0
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT                 0
+
+/***************************************************************************
+ *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
+ ***************************************************************************/
+/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT                 0
+
+/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT            0
+
+/***************************************************************************
+ *INV_READ_ADDR - Flash Invalid Data Address
+ ***************************************************************************/
+/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT                    0
+
+/***************************************************************************
+ *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
+ ***************************************************************************/
+/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK                 0xffffffff
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT                0
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT              0
+
+/***************************************************************************
+ *ACC_CONTROL_CS1 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS1 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS1 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS1 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS1 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS1_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS1 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS1 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS1_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS1_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS1_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS1_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS1_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS1_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS1_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS1_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS1_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS1_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS1_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS1 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS1 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS1_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS2 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS2 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS2 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS2 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS2 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS2_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS2 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS2 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS2_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS2_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS2_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS2_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS2 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS2_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS2_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS2_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS2_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS2_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS2_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS2_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS2_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS3 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS3 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS3 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS3 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS3 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS3_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS3 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS3 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS3_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS3_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS3_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS3_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS3 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS3_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS3_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS3_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS3_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS3_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS3_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS3_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS3 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS3 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS3_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS4 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS4 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS4 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS4 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS4 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS4_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS4 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS4 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS4_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS4_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS4_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS4_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS4 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS4_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS4_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS4_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS4_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS4_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS4_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS4_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS4 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS4 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS4_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS5 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS5 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS5 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS5 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS5 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS5 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS5 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS5 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS5 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS5 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS5 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS5 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS5 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS5 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS5 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS5_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS5_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS5 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS5 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS5_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS5_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS5 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS5 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS5_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS5_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS5 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS5 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS5_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS5_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS5 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS5 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS5_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS5_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS5 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS5 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS5_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS5_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS5_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS5 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS5_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS5_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS5_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS5 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS5_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS5_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS5_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS5 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS5_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS5_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS5_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS5 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS5_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS5_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS5_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS5 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS5_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS5_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS5_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS5 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS5_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS5_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS5_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS5 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS5_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS5_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS5_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS5 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS5 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS5 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS5_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS5_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS5 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS5_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS5_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS5_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS5 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS5_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS5_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS5_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS5 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS5_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS5_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS5_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT      255
+
+/***************************************************************************
+ *LL_OP - Nand Flash Low Level Operation
+ ***************************************************************************/
+/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
+#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK                           0x80000000
+#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT                          31
+#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT                        0
+
+/* NAND :: LL_OP :: reserved0 [30:20] */
+#define BCHP_NAND_LL_OP_reserved0_MASK                             0x7ff00000
+#define BCHP_NAND_LL_OP_reserved0_SHIFT                            20
+
+/* NAND :: LL_OP :: CLE [19:19] */
+#define BCHP_NAND_LL_OP_CLE_MASK                                   0x00080000
+#define BCHP_NAND_LL_OP_CLE_SHIFT                                  19
+#define BCHP_NAND_LL_OP_CLE_DEFAULT                                0
+
+/* NAND :: LL_OP :: ALE [18:18] */
+#define BCHP_NAND_LL_OP_ALE_MASK                                   0x00040000
+#define BCHP_NAND_LL_OP_ALE_SHIFT                                  18
+#define BCHP_NAND_LL_OP_ALE_DEFAULT                                0
+
+/* NAND :: LL_OP :: WE [17:17] */
+#define BCHP_NAND_LL_OP_WE_MASK                                    0x00020000
+#define BCHP_NAND_LL_OP_WE_SHIFT                                   17
+#define BCHP_NAND_LL_OP_WE_DEFAULT                                 0
+
+/* NAND :: LL_OP :: RE [16:16] */
+#define BCHP_NAND_LL_OP_RE_MASK                                    0x00010000
+#define BCHP_NAND_LL_OP_RE_SHIFT                                   16
+#define BCHP_NAND_LL_OP_RE_DEFAULT                                 0
+
+/* NAND :: LL_OP :: DATA [15:00] */
+#define BCHP_NAND_LL_OP_DATA_MASK                                  0x0000ffff
+#define BCHP_NAND_LL_OP_DATA_SHIFT                                 0
+#define BCHP_NAND_LL_OP_DATA_DEFAULT                               0
+
+/***************************************************************************
+ *LL_RDDATA - Nand Flash Low Level Read Data
+ ***************************************************************************/
+/* NAND :: LL_RDDATA :: reserved0 [31:16] */
+#define BCHP_NAND_LL_RDDATA_reserved0_MASK                         0xffff0000
+#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT                        16
+
+/* NAND :: LL_RDDATA :: DATA [15:00] */
+#define BCHP_NAND_LL_RDDATA_DATA_MASK                              0x0000ffff
+#define BCHP_NAND_LL_RDDATA_DATA_SHIFT                             0
+#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT                           0
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE                          0x00412a00
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_START                         0
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_END                           127
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE                  32
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+/* NAND :: FLASH_CACHEi :: WORD [31:00] */
+#define BCHP_NAND_FLASH_CACHEi_WORD_MASK                           0xffffffff
+#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT                          0
+
+
+#endif /* #ifndef BCHP_NAND_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_sata_top_ctrl.h b/include/linux/brcmstb/7346b0/bchp_sata_top_ctrl.h
new file mode 100644
index 0000000..b54f228
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_sata_top_ctrl.h
@@ -0,0 +1,164 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 24 13:12:38 2011
+ *                 MD5 Checksum         20406eb4287081a441630135cf8f15e2
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_sata_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   5/24/11 5:55p albertl
+ * SW7346-143: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SATA_TOP_CTRL_H__
+#define BCHP_SATA_TOP_CTRL_H__
+
+/***************************************************************************
+ *SATA_TOP_CTRL - SATA3 MISC Control Registers
+ ***************************************************************************/
+#define BCHP_SATA_TOP_CTRL_Version               0x00180020 /* SATA3 Version Register */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL              0x00180024 /* SATA3 System Bus Access Control Register */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL               0x00180028 /* SATA3 Test Port Control register */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1            0x0018002c /* SATA3 phy interface control 1 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2            0x00180030 /* SATA3 phy interface control 2 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3            0x00180034 /* SATA3 phy interface control 3 */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT           0x00180038 /* SATA3 TP OUT */
+
+/***************************************************************************
+ *Version - SATA3 Version Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: Version :: reserved0 [31:08] */
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_MASK                  0xffffff00
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_SHIFT                 8
+
+/* SATA_TOP_CTRL :: Version :: major_version [07:04] */
+#define BCHP_SATA_TOP_CTRL_Version_major_version_MASK              0x000000f0
+#define BCHP_SATA_TOP_CTRL_Version_major_version_SHIFT             4
+#define BCHP_SATA_TOP_CTRL_Version_major_version_DEFAULT           0
+
+/* SATA_TOP_CTRL :: Version :: minor_version [03:00] */
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_MASK              0x0000000f
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_SHIFT             0
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_DEFAULT           1
+
+/***************************************************************************
+ *BUS_CTRL - SATA3 System Bus Access Control Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_31_17 [31:17] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_MASK            0xfffe0000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_SHIFT           17
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_DEFAULT         0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: overide_hwinit_registers [16:16] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_MASK  0x00010000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_SHIFT 16
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_DEFAULT 0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_15_8 [15:08] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_MASK             0x0000ff00
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_SHIFT            8
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_DEFAULT          0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: piodata_endian_ctrl [07:06] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_MASK       0x000000c0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SHIFT      6
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_DEFAULT    0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadata_endian_ctrl [05:04] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_MASK       0x00000030
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SHIFT      4
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_DEFAULT    0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadesc_endian_ctrl [03:02] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_MASK       0x0000000c
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SHIFT      2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_DEFAULT    0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: reg_endian_ctrl [01:00] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_MASK           0x00000003
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SHIFT          0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_DEFAULT        0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SwapEndianess  2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_HalfWordSwap   1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_NoSwap         0
+
+/***************************************************************************
+ *TP_CTRL - SATA3 Test Port Control register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: TP_CTRL :: tp_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_MASK                    0xffffffff
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_SHIFT                   0
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_DEFAULT                 0
+
+/***************************************************************************
+ *PHY_CTRL_1 - SATA3 phy interface control 1
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_1 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_DEFAULT             0
+
+/***************************************************************************
+ *PHY_CTRL_2 - SATA3 phy interface control 2
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_2 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_DEFAULT             0
+
+/***************************************************************************
+ *PHY_CTRL_3 - SATA3 phy interface control 3
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_3 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_DEFAULT             0
+
+/***************************************************************************
+ *SATA_TP_OUT - SATA3 TP OUT
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: SATA_TP_OUT :: TP_OUT [31:00] */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_MASK                 0xffffffff
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_SHIFT                0
+
+#endif /* #ifndef BCHP_SATA_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_sdio_0_cfg.h b/include/linux/brcmstb/7346b0/bchp_sdio_0_cfg.h
new file mode 100644
index 0000000..1ac557f
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_sdio_0_cfg.h
@@ -0,0 +1,589 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 24 13:15:22 2011
+ *                 MD5 Checksum         20406eb4287081a441630135cf8f15e2
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_sdio_0_cfg.h $
+ * 
+ * Hydra_Software_Devel/2   5/24/11 5:55p albertl
+ * SW7346-143: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SDIO_0_CFG_H__
+#define BCHP_SDIO_0_CFG_H__
+
+/***************************************************************************
+ *SDIO_0_CFG - SDIO (CARD) Configuration Registers
+ ***************************************************************************/
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1          0x00413600 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2          0x00413604 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL               0x00413608 /* SDIO TP_OUT Control Register */
+#define BCHP_SDIO_0_CFG_CAP_REG0                 0x0041360c /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_CAP_REG1                 0x00413610 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET1                  0x00413614 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET2                  0x00413618 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY           0x0041361c /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV               0x00413620 /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_IP_DLY                   0x00413630 /* SDIO Host input delay register */
+#define BCHP_SDIO_0_CFG_OP_DLY                   0x00413634 /* SDIO Host output delay register */
+#define BCHP_SDIO_0_CFG_SCRATCH                  0x004136fc /* SDIO Scratch Register */
+#define BCHP_SDIO_0_CFG_VERSION                  0x004136f0 /* SDIO VERSION Register */
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL1 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_SEL_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_MASK    0x80000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_SHIFT   31
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_DEFAULT 0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_LEV [30:30] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_MASK       0x40000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_SHIFT      30
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_DEFAULT    1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: CFG_RESERVED [29:29] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_MASK          0x20000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_SHIFT         29
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_DEFAULT       0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: RETUNING_REQ [28:28] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_MASK          0x10000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_SHIFT         28
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_DEFAULT       0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DDR_TAP_DELAY [27:24] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_MASK         0x0f000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_SHIFT        24
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_DEFAULT      0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DELAY_CTRL [23:21] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_MASK            0x00e00000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_SHIFT           21
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_DEFAULT         0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_ENA [20:20] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_MASK       0x00100000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_SHIFT      20
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_DEFAULT    1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_PULSE [19:19] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_MASK     0x00080000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_SHIFT    19
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_DEFAULT  0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DATA_PENDING [18:18] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_MASK          0x00040000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_SHIFT         18
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_DEFAULT       0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WR_FLUSH [17:17] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_MASK              0x00020000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_SHIFT             17
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_DEFAULT           0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: MF_NUM_WR [16:16] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_MASK             0x00010000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_SHIFT            16
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_DEFAULT          0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WORD_ABO [15:15] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_MASK              0x00008000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_SHIFT             15
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_DEFAULT           0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NBO [14:14] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_MASK             0x00004000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_SHIFT            14
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_DEFAULT          0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NHW [13:13] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_MASK             0x00002000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_SHIFT            13
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_DEFAULT          1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: BUFFER_ABO [12:12] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_MASK            0x00001000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_SHIFT           12
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_DEFAULT         1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_BUF_ACC [11:11] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_MASK           0x00000800
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_SHIFT          11
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_DEFAULT        1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SEQ_EN [10:10] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_MASK            0x00000400
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_SHIFT           10
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_DEFAULT         0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_RD_THRESH [09:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_MASK         0x000003e0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_SHIFT        5
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_DEFAULT      2
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SIZE [04:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_MASK              0x0000001f
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_SHIFT             0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_DEFAULT           4
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL2 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved0 [31:08] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_MASK             0xffffff00
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_SHIFT            8
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_BYTE [07:06] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_MASK     0x000000c0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_SHIFT    6
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_DEFAULT  0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved1 [05:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_MASK             0x00000020
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_SHIFT            5
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_HW [04:04] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_MASK       0x00000010
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_SHIFT      4
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_DEFAULT    0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_WR [03:02] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_MASK      0x0000000c
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_SHIFT     2
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_DEFAULT   0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_RD [01:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_MASK      0x00000003
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_SHIFT     0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_DEFAULT   0
+
+/***************************************************************************
+ *TP_OUT_SEL - SDIO TP_OUT Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TP_OUT_SEL :: reserved0 [31:01] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_MASK                  0xfffffffe
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_SHIFT                 1
+
+/* SDIO_0_CFG :: TP_OUT_SEL :: TP_OUT_SELECT [00:00] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_MASK              0x00000001
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_SHIFT             0
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_DEFAULT           0
+
+/***************************************************************************
+ *CAP_REG0 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG0 :: DDR50_SUPPORT [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_SHIFT               31
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_DEFAULT             0
+
+/* SDIO_0_CFG :: CAP_REG0 :: SD104_SUPPORT [30:30] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_MASK                0x40000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_SHIFT               30
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_DEFAULT             0
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDR50 [29:29] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_MASK                        0x20000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_SHIFT                       29
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_DEFAULT                     0
+
+/* SDIO_0_CFG :: CAP_REG0 :: SLOT_TYPE [28:27] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_MASK                    0x18000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_SHIFT                   27
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_DEFAULT                 0
+
+/* SDIO_0_CFG :: CAP_REG0 :: ASYNCH_INT_SUPPORT [26:26] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_MASK           0x04000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_SHIFT          26
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_DEFAULT        0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 64B_SYS_BUS_SUPPORT [25:25] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_MASK          0x02000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_SHIFT         25
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_DEFAULT       0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 1_8V_SUPPORT [24:24] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_MASK                 0x01000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_SHIFT                24
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_DEFAULT              0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_0V_SUPPORT [23:23] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_MASK                 0x00800000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_SHIFT                23
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_DEFAULT              0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_3V_SUPPORT [22:22] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_MASK                 0x00400000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_SHIFT                22
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_DEFAULT              1
+
+/* SDIO_0_CFG :: CAP_REG0 :: SUSP_RES_SUPPORT [21:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_MASK             0x00200000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_SHIFT            21
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_DEFAULT          1
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDMA_SUPPORT [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_MASK                 0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_SHIFT                20
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_DEFAULT              1
+
+/* SDIO_0_CFG :: CAP_REG0 :: HIGH_SPEED_SUPPORT [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_MASK           0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_SHIFT          19
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_DEFAULT        1
+
+/* SDIO_0_CFG :: CAP_REG0 :: ADMA2_SUPPORT [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_MASK                0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_SHIFT               18
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_DEFAULT             1
+
+/* SDIO_0_CFG :: CAP_REG0 :: EXTENDED_MEDIA_SUPPORT [17:17] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_MASK       0x00020000
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_SHIFT      17
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_DEFAULT    1
+
+/* SDIO_0_CFG :: CAP_REG0 :: MAX_BL [16:15] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_MASK                       0x00018000
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_SHIFT                      15
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_DEFAULT                    1
+
+/* SDIO_0_CFG :: CAP_REG0 :: BASE_FREQ [14:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_MASK                    0x00007f80
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_SHIFT                   7
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_DEFAULT                 100
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_CLK_UNIT [06:06] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_MASK             0x00000040
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_SHIFT            6
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_DEFAULT          1
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_FREQ [05:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_MASK                 0x0000003f
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_SHIFT                0
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_DEFAULT              50
+
+/***************************************************************************
+ *CAP_REG1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_REG_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_MASK             0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_SHIFT            31
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_DEFAULT          0
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved0 [30:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_MASK                    0x7fe00000
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_SHIFT                   21
+
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_1_stuff [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_MASK                  0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_SHIFT                 20
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_DEFAULT               0
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_BLK_MODE [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_MASK                 0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_SHIFT                19
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_DEFAULT              0
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_MODE [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_MASK                     0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_SHIFT                    18
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_DEFAULT                  1
+
+/* SDIO_0_CFG :: CAP_REG1 :: CLK_MULT [17:10] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_MASK                     0x0003fc00
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_SHIFT                    10
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_DEFAULT                  0
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_MODES [09:08] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_MASK               0x00000300
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_SHIFT              8
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_DEFAULT            2
+
+/* SDIO_0_CFG :: CAP_REG1 :: USE_TUNING [07:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_MASK                   0x00000080
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_SHIFT                  7
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_DEFAULT                0
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_TIMER [06:03] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_MASK               0x00000078
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_SHIFT              3
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_DEFAULT            10
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_D_SUPPORT [02:02] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_MASK             0x00000004
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_SHIFT            2
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_DEFAULT          0
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_C_SUPPORT [01:01] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_MASK             0x00000002
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_SHIFT            1
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_DEFAULT          0
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_A_SUPPORT [00:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_MASK             0x00000001
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_SHIFT            0
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_DEFAULT          0
+
+/***************************************************************************
+ *PRESET1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET1 :: PRESET1_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_DEFAULT           0
+
+/* SDIO_0_CFG :: PRESET1 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET100 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_MASK                     0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_SHIFT                    16
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_DEFAULT                  0
+
+/* SDIO_0_CFG :: PRESET1 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET50 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_MASK                      0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_SHIFT                     0
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_DEFAULT                   1
+
+/***************************************************************************
+ *PRESET2 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET2 :: PRESET2_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_DEFAULT           0
+
+/* SDIO_0_CFG :: PRESET2 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET25 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_MASK                      0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_SHIFT                     16
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_DEFAULT                   2
+
+/* SDIO_0_CFG :: PRESET2 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET12P5 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_MASK                    0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_SHIFT                   0
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_DEFAULT                 3
+
+/***************************************************************************
+ *SD_CLOCK_DELAY - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_SEL [31:31] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_MASK        0x80000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_SHIFT       31
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_DEFAULT     1
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY_OVERRIDE [30:30] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_MASK 0x40000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_SHIFT 30
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_DEFAULT 0
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved0 [29:12] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_MASK              0x3ffff000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_SHIFT             12
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: OUTPUT_CLOCK_DELAY [11:08] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_MASK     0x00000f00
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_SHIFT    8
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_DEFAULT  0
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INTERNAL_CLOCK_DELAY [07:04] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_MASK   0x000000f0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_SHIFT  4
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_DEFAULT 0
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_MASK      0x0000000f
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_SHIFT     0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_DEFAULT   0
+
+/***************************************************************************
+ *SD_PAD_DRV - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_PAD_DRV :: OVERRIDE_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_SHIFT               31
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_DEFAULT             0
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved0 [30:23] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_MASK                  0x7f800000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_SHIFT                 23
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CLK_VAL [22:20] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_MASK                    0x00700000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_SHIFT                   20
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_DEFAULT                 5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved1 [19:19] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_MASK                  0x00080000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_SHIFT                 19
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CMD_VAL [18:16] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_MASK                    0x00070000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_SHIFT                   16
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_DEFAULT                 5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved2 [15:15] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_MASK                  0x00008000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_SHIFT                 15
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT3_VAL [14:12] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_MASK                   0x00007000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_SHIFT                  12
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_DEFAULT                5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved3 [11:11] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_MASK                  0x00000800
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_SHIFT                 11
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT2_VAL [10:08] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_MASK                   0x00000700
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_SHIFT                  8
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_DEFAULT                5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved4 [07:07] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_MASK                  0x00000080
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_SHIFT                 7
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT1_VAL [06:04] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_MASK                   0x00000070
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_SHIFT                  4
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_DEFAULT                5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved5 [03:03] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_MASK                  0x00000008
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_SHIFT                 3
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT0_VAL [02:00] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_MASK                   0x00000007
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_SHIFT                  0
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_DEFAULT                5
+
+/***************************************************************************
+ *IP_DLY - SDIO Host input delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_DEFAULT                   0
+
+/* SDIO_0_CFG :: IP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: IP_DLY :: IP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_DEFAULT               3
+
+/* SDIO_0_CFG :: IP_DLY :: reserved1 [15:06] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_MASK                      0x0000ffc0
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_SHIFT                     6
+
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_DELAY [05:00] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_MASK                   0x0000003f
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_DEFAULT                0
+
+/***************************************************************************
+ *OP_DLY - SDIO Host output delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_DEFAULT                   0
+
+/* SDIO_0_CFG :: OP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: OP_DLY :: OP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_DEFAULT               3
+
+/* SDIO_0_CFG :: OP_DLY :: reserved1 [15:04] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_MASK                      0x0000fff0
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_SHIFT                     4
+
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_MASK                   0x0000000f
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_DEFAULT                0
+
+/***************************************************************************
+ *SCRATCH - SDIO Scratch Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SCRATCH :: SCRATCH_BITS [31:00] */
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_MASK                  0xffffffff
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_SHIFT                 0
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_DEFAULT               0
+
+/***************************************************************************
+ *VERSION - SDIO VERSION Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VERSION :: SD_VER [31:24] */
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_MASK                        0xff000000
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_SHIFT                       24
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_DEFAULT                     48
+
+/* SDIO_0_CFG :: VERSION :: MMC_VER [23:16] */
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_MASK                       0x00ff0000
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_SHIFT                      16
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_DEFAULT                    67
+
+/* SDIO_0_CFG :: VERSION :: REV [15:08] */
+#define BCHP_SDIO_0_CFG_VERSION_REV_MASK                           0x0000ff00
+#define BCHP_SDIO_0_CFG_VERSION_REV_SHIFT                          8
+#define BCHP_SDIO_0_CFG_VERSION_REV_DEFAULT                        160
+
+/* SDIO_0_CFG :: VERSION :: A2S_VER [07:00] */
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_MASK                       0x000000ff
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_SHIFT                      0
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_DEFAULT                    1
+
+#endif /* #ifndef BCHP_SDIO_0_CFG_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/7346b0/bchp_sun_top_ctrl.h
new file mode 100644
index 0000000..d6e212b
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_sun_top_ctrl.h
@@ -0,0 +1,6596 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug  8 22:03:23 2011
+ *                 MD5 Checksum         311e89d3d4fe94a8e2842dfaef9c3871
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_sun_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/4   8/9/11 2:40p pntruong
+ * SW7346-143: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SUN_TOP_CTRL_H__
+#define BCHP_SUN_TOP_CTRL_H__
+
+/***************************************************************************
+ *SUN_TOP_CTRL - Top Control registers
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID         0x00404000 /* Chip family ID */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID             0x00404004 /* Product Revision ID */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x0040401c /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x00404020 /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x00404024 /* Bond option value register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x00404028 /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x0040402c /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x00404030 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x00404034 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x00404038 /* Semaphore channel 0 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x0040403c /* Semaphore channel 1 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x00404040 /* Semaphore channel 2 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x00404044 /* Semaphore channel 3 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x00404048 /* Semaphore channel 4 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x0040404c /* Semaphore channel 5 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x00404050 /* Semaphore channel 6 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x00404054 /* Semaphore channel 7 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x00404058 /* Semaphore channel 8 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x0040405c /* Semaphore channel 9 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x00404060 /* Semaphore channel 10 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x00404064 /* Semaphore channel 11 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x00404068 /* Semaphore channel 12 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x0040406c /* Semaphore channel 13 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x00404070 /* Semaphore channel 14 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x00404074 /* Semaphore channel 15 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x00404078 /* General watchdog timer 0 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x0040407c /* General watchdog timer 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x00404080 /* General control register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x00404084 /* General control register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x00404088 /* General control register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x0040408c /* General control register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x00404090 /* General control register 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x00404094 /* General control register 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x00404098 /* General status register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x0040409c /* General status register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x004040a0 /* General status register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x00404100 /* Pinmux control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x00404104 /* Pinmux control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x00404108 /* Pinmux control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x0040410c /* Pinmux control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x00404110 /* Pinmux control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x00404114 /* Pinmux control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x00404118 /* Pinmux control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x0040411c /* Pinmux control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x00404120 /* Pinmux control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x00404124 /* Pinmux control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10        0x00404128 /* Pinmux control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11        0x0040412c /* Pinmux control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12        0x00404130 /* Pinmux control register 12 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13        0x00404134 /* Pinmux control register 13 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14        0x00404138 /* Pinmux control register 14 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15        0x0040413c /* Pinmux control register 15 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16        0x00404140 /* Pinmux control register 16 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17        0x00404144 /* Pinmux control register 17 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18        0x00404148 /* Pinmux control register 18 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x0040414c /* Pad pull-up/pull-down control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x00404150 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x00404154 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x00404158 /* Pad pull-up/pull-down control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x0040415c /* Pad pull-up/pull-down control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5     0x00404160 /* Pad pull-up/pull-down control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6     0x00404164 /* Pad pull-up/pull-down control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7     0x00404168 /* Pad pull-up/pull-down control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8     0x0040416c /* Pad pull-up/pull-down control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9     0x00404170 /* Pad pull-up/pull-down control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10    0x00404174 /* Pad pull-up/pull-down control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11    0x00404178 /* Pad pull-up/pull-down control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12    0x0040417c /* Pad pull-up/pull-down control register 12 */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x00404180 /* Bypass clock unselect register 0 */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x00404300 /* Reset control */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE    0x00404304 /* Reset source enable */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET        0x00404308 /* Software master reset */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION     0x0040430c /* Hardware reset extension */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR          0x00404310 /* Reset Monitor */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x00404314 /* Reset history */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET          0x00404318 /* Software init 0 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR        0x0040431c /* Software init 0 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS       0x00404320 /* Software init 0 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR  0x00404324 /* Security software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET          0x00404330 /* Software init 1 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR        0x00404334 /* Software init 1 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS       0x00404338 /* Software init 1 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR  0x0040433c /* Security software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x00404364 /* Scratch register */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x00404368 /* Spare control bits reserved for future use */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x00404380 /* Test port control */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x00404384 /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x00404388 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x0040438c /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x00404390 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x00404394 /* EJTAG input bus enables */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x00404398 /* EJTAG output select */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL        0x0040439c /* UART Router select */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL             0x004043a0 /* VTRAP Control */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS           0x004043a4 /* VTRAP Status */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x00404400 /* Serial Slave Port configuration register */
+#define BCHP_SUN_TOP_CTRL_SERS_REV               0x00404420 /* SERS Revision Register */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x00404424 /* SERS Configuration Register */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x00404514 /* Block select for RO testmode */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION     0x00404518 /* Test configuration */
+
+/***************************************************************************
+ *CHIP_FAMILY_ID - Chip family ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT    1933967376
+
+/***************************************************************************
+ *PRODUCT_ID - Product Revision ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK               0xffffffff
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT            1933967376
+
+/***************************************************************************
+ *BSP_FEATURE_TABLE_ADDR - BSP feature table address
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_VALUE_0 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xfffff800
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            11
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_reset_outb_def_val [10:10] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_DEFAULT 1
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [09:06] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK      0x000003c0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT   10
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_cpu_freq [05:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_cpu_freq_MASK        0x00000030
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_cpu_freq_SHIFT       4
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_cpu_freq_DEFAULT     0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [03:03] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_DEFAULT 0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_spare0 [02:02] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare0_MASK          0x00000004
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare0_SHIFT         2
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare0_DEFAULT       0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_ebi_pad_config [01:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_pad_config_MASK  0x00000003
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_pad_config_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_pad_config_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_VALUE_1 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xffffffe0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            5
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xtal_xcore_bias [04:02] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xtal_xcore_bias_MASK 0x0000001c
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xtal_xcore_bias_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xtal_xcore_bias_DEFAULT 2
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xtal_enable_ext_cml [01:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xtal_enable_ext_cml_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xtal_enable_ext_cml_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xtal_enable_ext_cml_DEFAULT 0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK     0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT  0
+
+/***************************************************************************
+ *BOND_STATUS - Bond option value register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1
+
+/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_0 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_0 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_temp_sensor_disable [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_out_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_out_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_out_disable_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_out_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_genet0_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet0_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet0_disable_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet0_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_svc_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_uhf_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_uhf_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_uhf_disable_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_uhf_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_directv_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_moca_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tuner1_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tuner1_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tuner1_disable_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tuner1_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tuner0_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tuner0_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tuner0_disable_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tuner0_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hd_display_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sata_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ephy_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tfec0_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec0_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec0_disable_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec0_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ldpc0_disable [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc0_disable_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc0_disable_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc0_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tfec1_disable [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec1_disable_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec1_disable_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec1_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ldpc1_disable [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc1_disable_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc1_disable_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc1_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb23_otg_disable [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb23_otg_disable_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb23_otg_disable_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb23_otg_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb01_otg_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb01_otg_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb01_otg_disable_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb01_otg_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_1 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_25 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_24 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_23 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_22 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_21 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_20 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_19 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_18 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_17 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_16 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_15 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_14 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_0 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb3_disable [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb2_disable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb2_disable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb2_disable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb2_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb1_disable [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb1_disable_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb1_disable_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb1_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb0_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb0_disable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb0_disable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb0_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_genet1_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_genet1_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_genet1_disable_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_genet1_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_DEFAULT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_0 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_0 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_temp_sensor_disable [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_temp_sensor_disable_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_temp_sensor_disable_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_out_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_out_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_out_disable_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_genet0_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet0_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet0_disable_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_svc_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_svc_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_svc_disable_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_uhf_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_uhf_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_uhf_disable_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_directv_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_moca_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tuner1_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tuner1_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tuner1_disable_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tuner0_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tuner0_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tuner0_disable_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hd_display_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sata_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ephy_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tfec0_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec0_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec0_disable_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ldpc0_disable [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc0_disable_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc0_disable_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tfec1_disable [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec1_disable_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec1_disable_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ldpc1_disable [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc1_disable_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc1_disable_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb23_otg_disable [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb23_otg_disable_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb23_otg_disable_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb01_otg_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb01_otg_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb01_otg_disable_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_1 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_25 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_24 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_23 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_22 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_21 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_20 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_19 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_18 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_17 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_16 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_15 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_14 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_0 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_SHIFT 6
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb3_disable [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb3_disable_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb3_disable_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb2_disable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb2_disable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb2_disable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb1_disable [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb1_disable_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb1_disable_SHIFT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb0_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb0_disable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb0_disable_SHIFT 2
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_genet1_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_genet1_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_genet1_disable_SHIFT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_SHIFT 0
+
+/***************************************************************************
+ *SEMAPHORE_0 - Semaphore channel 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_1 - Semaphore channel 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_2 - Semaphore channel 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_3 - Semaphore channel 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_4 - Semaphore channel 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_5 - Semaphore channel 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_6 - Semaphore channel 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_7 - Semaphore channel 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_8 - Semaphore channel 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_9 - Semaphore channel 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_10 - Semaphore channel 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_11 - Semaphore channel 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_12 - Semaphore channel 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_13 - Semaphore channel 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_14 - Semaphore channel 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_15 - Semaphore channel 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *GEN_WATCHDOG_0 - General watchdog timer 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0
+
+/***************************************************************************
+ *GEN_WATCHDOG_1 - General watchdog timer 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK     0x80000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT    31
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK     0x40000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT    30
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK     0x20000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT    29
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK     0x10000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT    28
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK     0x02000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT    25
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK     0x01000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT    24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK     0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT    23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK     0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT    22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK     0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT    21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK     0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT    20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK     0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT    19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK     0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT    18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK     0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT    17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK     0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT    16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb1_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_mode_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_mode_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_mode_DEFAULT         0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb0_mode [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_DEFAULT         0
+
+/***************************************************************************
+ *GENERAL_CTRL_1 - General control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_2 - General control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_3 - General control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_4 - General control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_5 - General control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK          0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT         8
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_1 - General status register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_2 - General status register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xfffc0000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   18
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: sdio_pad_amp_en [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_sdio_pad_amp_en_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_sdio_pad_amp_en_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_sdio_pad_amp_en_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: sdio_pad_slew [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_sdio_pad_slew_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_sdio_pad_slew_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_sdio_pad_slew_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_sel_1 [15:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_1_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_1_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_1_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_1_GMII_CMOS_3P3V 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_1_RGMII_CMOS_2P5V 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_1_HSTL_CLASS1_1P5V 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_1_HSTL_CLASS1_1P8V 3
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_amp_en [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_slew [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_slew_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_slew_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_slew_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_sel [11:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_GMII_CMOS_3P3V 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_RGMII_CMOS_2P5V 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_HSTL_CLASS1_1P5V 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_HSTL_CLASS1_1P8V 3
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_rx_pad_amp_en [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_rx_pad_amp_en_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_rx_pad_amp_en_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_rx_pad_amp_en_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_tx_pad_amp_en [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_tx_pad_amp_en_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_tx_pad_amp_en_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_tx_pad_amp_en_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_slew [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_slew_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_slew_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_slew_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_sel_0 [06:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_0_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_0_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_0_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_0_GMII_CMOS_3P3V 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_0_RGMII_CMOS_2P5V 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_0_HSTL_CLASS1_1P5V 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_0_HSTL_CLASS1_1P8V 3
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_rx_pad_amp_en [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_rx_pad_amp_en_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_rx_pad_amp_en_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_rx_pad_amp_en_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_tx_pad_amp_en [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_tx_pad_amp_en_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_tx_pad_amp_en_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_tx_pad_amp_en_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_slew [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_slew_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_slew_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_slew_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_sel [01:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_GMII_CMOS_3P3V 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_RGMII_CMOS_2P5V 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_HSTL_CLASS1_1P5V 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_HSTL_CLASS1_1P8V 3
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_1_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK    0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT   8
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: mii_drive_src_1 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_1_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_1_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: mii_drive_sel_1 [06:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_1_MASK 0x00000070
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_1_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_1_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_1_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_1_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_1_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_1_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_1_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_1_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_1_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_1_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: mii_drive_src_0 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: mii_drive_sel_0 [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_16MA 7
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_DEFAULT 0
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: mii_col [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_col_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_col_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_col_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_col_MII_COL           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_col_SDS1_PKTP_DAT_4   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_col_SDS0_PKTP_DAT_4   2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: mii_rxer [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_rxer_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_rxer_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_rxer_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_rxer_MII_RXER         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_rxer_SDS1_PKTP_DAT_3  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_rxer_SDS0_PKTP_DAT_3  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_rxer_TP_IN_30         3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: rgmii_rxctl [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxctl_MASK          0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxctl_SHIFT         20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxctl_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxctl_RGMII_RXCTL   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxctl_SDS1_PKTP_DAT_2 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxctl_SDS0_PKTP_DAT_2 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxctl_ALT_TP_IN_01  3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: rgmii_rxclk [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxclk_MASK          0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxclk_SHIFT         16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxclk_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxclk_RGMII_RXCLK   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxclk_SDS1_PKTP_DAT_1 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxclk_SDS0_PKTP_DAT_1 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxclk_TP_IN_26      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: rgmii_rxd_03 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_03_MASK         0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_03_SHIFT        12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_03_DEFAULT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_03_RGMII_RXD_03 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_03_SDS1_PKTP_DAT_0 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_03_SDS0_PKTP_DAT_0 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_03_TP_IN_25     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: rgmii_rxd_02 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_02_MASK         0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_02_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_02_DEFAULT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_02_RGMII_RXD_02 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_02_SDS1_PKTP_SYNC 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_02_SDS0_PKTP_SYNC 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_02_TP_IN_31     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: rgmii_rxd_01 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_01_MASK         0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_01_SHIFT        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_01_DEFAULT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_01_RGMII_RXD_01 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_01_SDS1_PKTP_VALID 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_01_SDS0_PKTP_VALID 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_01_ALT_TP_IN_00 3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: rgmii_rxd_00 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_00_MASK         0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_00_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_00_DEFAULT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_00_RGMII_RXD_00 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_00_SDS1_PKTP_ERROR 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_00_SDS0_PKTP_ERROR 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_00_ALT_TP_OUT_25 3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_EBI_DATA0       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_ALT_TP_OUT_23   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: mii_txer [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_mii_txer_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_mii_txer_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_mii_txer_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_mii_txer_MII_TXER         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_mii_txer_UART_TXD_2       1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: rgmii_txctl [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txctl_MASK          0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txctl_SHIFT         20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txctl_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txctl_RGMII_TXCTL   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txctl_UART_RTS_1    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: rgmii_txd_03 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_03_MASK         0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_03_SHIFT        16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_03_DEFAULT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_03_RGMII_TXD_03 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_03_UART_RTS_2   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: rgmii_txd_02 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_02_MASK         0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_02_SHIFT        12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_02_DEFAULT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_02_RGMII_TXD_02 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_02_UART_TXD_1   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: rgmii_txd_01 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_01_MASK         0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_01_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_01_DEFAULT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_01_RGMII_TXD_01 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_01_UART_RTS_0   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: rgmii_txd_00 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_00_MASK         0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_00_SHIFT        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_00_DEFAULT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_00_RGMII_TXD_00 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_00_UART_TXD_0   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: mii_crs [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_mii_crs_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_mii_crs_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_mii_crs_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_mii_crs_MII_CRS           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_mii_crs_TP_IN_24          1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data8 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_EBI_DATA8       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_ALT_TP_IN_08    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data7 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_EBI_DATA7       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_ALT_TP_IN_07    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data6 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_EBI_DATA6       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_ALT_TP_IN_06    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data5 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_EBI_DATA5       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_ALT_TP_IN_05    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data4 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_EBI_DATA4       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_ALT_TP_IN_04    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data3 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_EBI_DATA3       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_ALT_TP_IN_03    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data2 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_EBI_DATA2       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_ALT_TP_IN_02    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data1 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data1_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data1_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data1_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data1_EBI_DATA1       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data1_ALT_TP_OUT_24   1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_EBI_ADDR0       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_ALT_TP_IN_16    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data15 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_MASK           0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_SHIFT          24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_EBI_DATA15     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_ALT_TP_IN_15   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data14 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_MASK           0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_SHIFT          20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_EBI_DATA14     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_ALT_TP_IN_14   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data13 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_MASK           0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_SHIFT          16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_EBI_DATA13     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_ALT_TP_IN_13   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data12 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_MASK           0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_SHIFT          12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_EBI_DATA12     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_ALT_TP_IN_12   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data11 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_MASK           0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_EBI_DATA11     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_ALT_TP_IN_11   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data10 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_MASK           0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_SHIFT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_EBI_DATA10     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_ALT_TP_IN_10   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data9 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data9_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data9_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data9_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data9_EBI_DATA9       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data9_ALT_TP_IN_09    1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_4 - Pinmux control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr8 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_EBI_ADDR8       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_ALT_TP_IN_24    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr7 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_EBI_ADDR7       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_ALT_TP_IN_23    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr6 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_EBI_ADDR6       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_ALT_TP_IN_22    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr5 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_EBI_ADDR5       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_ALT_TP_IN_21    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr4 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_EBI_ADDR4       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_ALT_TP_IN_20    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr3 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_EBI_ADDR3       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_ALT_TP_IN_19    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr2 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_EBI_ADDR2       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_ALT_TP_IN_18    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr1 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr1_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr1_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr1_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr1_EBI_ADDR1       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr1_ALT_TP_IN_17    1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_5 - Pinmux control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr16 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr16_MASK           0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr16_SHIFT          28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr16_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr16_EBI_ADDR16     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr16_ALT_TP_OUT_11  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr15 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_MASK           0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_SHIFT          24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_EBI_ADDR15     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_ALT_TP_IN_31   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr14 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_MASK           0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_SHIFT          20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_EBI_ADDR14     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_ALT_TP_IN_30   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr13 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_MASK           0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_SHIFT          16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_EBI_ADDR13     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_ALT_TP_IN_29   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr12 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_MASK           0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_SHIFT          12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_EBI_ADDR12     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_ALT_TP_IN_28   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr11 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_MASK           0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_EBI_ADDR11     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_ALT_TP_IN_27   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr10 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_MASK           0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_SHIFT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_EBI_ADDR10     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_ALT_TP_OUT_10  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr9 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr9_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr9_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr9_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr9_EBI_ADDR9       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr9_ALT_TP_IN_25    1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_6 - Pinmux control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_addr23 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr23_MASK           0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr23_SHIFT          28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr23_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr23_EBI_ADDR23     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr23_ALT_TP_OUT_02  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_addr22 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr22_MASK           0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr22_SHIFT          24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr22_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr22_EBI_ADDR22     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr22_ALT_TP_OUT_01  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_addr21 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr21_MASK           0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr21_SHIFT          20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr21_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr21_EBI_ADDR21     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr21_ALT_TP_OUT_00  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_waitb [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_waitb_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_waitb_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_waitb_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_waitb_EBI_WAITB       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_waitb_ALT_TP_OUT_03   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_addr20 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr20_MASK           0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr20_SHIFT          12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr20_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr20_EBI_ADDR20     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr20_ALT_TP_OUT_31  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_addr19 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr19_MASK           0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr19_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr19_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr19_EBI_ADDR19     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr19_ALT_TP_OUT_30  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_addr18 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr18_MASK           0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr18_SHIFT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr18_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr18_EBI_ADDR18     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr18_ALT_TP_OUT_29  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_addr17 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr17_MASK           0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr17_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr17_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr17_EBI_ADDR17     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr17_ALT_TP_OUT_28  1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_7 - Pinmux control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_004 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_GPIO_004         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_CODEC_FSYNCB     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_EXT_IRQB_13      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_UART_TXD_0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_PM_GPIO_004      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_003 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_GPIO_003         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_CODEC_SCLK       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_EXT_IRQB_12      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_UART_RTS_0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_PM_GPIO_003      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_002 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_GPIO_002         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_CODEC_SDI        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_EXT_IRQB_11      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_UART_CTS_0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_P1_INTR_0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_ALT_TP_OUT_04    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_PM_GPIO_002      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_001 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_GPIO_001         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_IR_IN1           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_PWM_1            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_EXT_IRQB_6       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_AUD_FS_CLK1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_TP_OUT_18        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_PM_GPIO_001      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_000 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_GPIO_000         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_IR_INT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_PWM_0            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_EXT_IRQB_5       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_AUD_FS_CLK0      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_TP_OUT_17        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_PM_GPIO_000      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: usb_clkout25 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_usb_clkout25_MASK         0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_usb_clkout25_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_usb_clkout25_DEFAULT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_usb_clkout25_USB_CLKOUT25 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_usb_clkout25_MDIO_SATA    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: ebi_addr25 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_addr25_MASK           0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_addr25_SHIFT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_addr25_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_addr25_EBI_ADDR25     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_addr25_ALT_TP_OUT_14  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: ebi_cs4b [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_cs4b_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_cs4b_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_cs4b_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_cs4b_EBI_CS4B         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_cs4b_MDCLK            1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_8 - Pinmux control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_012 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_012_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_012_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_012_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_012_GPIO_012         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_012_SC0_VCC          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_012_TP_IN_09         2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_011 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_011_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_011_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_011_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_011_GPIO_011         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_011_SC0_PRES         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_011_TP_OUT_28        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_010 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_GPIO_010         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_SC0_RST          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_TP_IN_27         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_PM_GPIO_010      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_009 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_GPIO_009         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_SC0_CLK          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_TP_OUT_26        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_PM_GPIO_009      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_008 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_GPIO_008         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_SC0_IO           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_TNR0_TST_MISO    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_TP_OUT_25        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_007 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_GPIO_007         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_GENET0_LINK      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_GENET1_LINK      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_EXT_IRQB_8       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_UART_RTS_1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_TP_IN_05         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_PM_GPIO_007      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_006 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_GPIO_006         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_GENET0_ACTIVITY  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_GENET1_ACTIVITY  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_EXT_IRQB_7       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_UART_TXD_1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_TP_OUT_01        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_PM_GPIO_006      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_005 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_GPIO_005         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_CODEC_MCLK       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_EXT_IRQB_14      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_UART_RXD_0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_PM_GPIO_005      4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_9 - Pinmux control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_020 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_GPIO_020         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_UART_RTS_1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_EXT_IRQB_12      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_LED_LS_3         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_PKT_SYNC3        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_VEC_VSYNC_0      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_SC0_AUX_2        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_TP_OUT_20        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_PM_GPIO_020      8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_019 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_GPIO_019         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_UART_CTS_1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_I2S_LR0          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_LED_LS_2         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_PKT_DATA3        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_VEC_VSYNC_1      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_SC0_AUX_1        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_PM_GPIO_019      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_018 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_GPIO_018         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_UART_RXD_1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_EXT_IRQB_11      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_LED_LS_1         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_PKT_ERROR3       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_TP_IN_02         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_PM_GPIO_018      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_017 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_GPIO_017         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_UART_TXD_1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_EXT_IRQB_10      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_LED_LS_0         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_PKT_SYNC2        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_TP_OUT_03        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_PM_GPIO_017      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_016 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_GPIO_016         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_UART_RTS_0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_I2S_DATA0        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_LED_KD_3         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_PKT_ERROR2       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_EXT_IRQB_8       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_VEC_HSYNC_1      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_TP_OUT_31        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_PM_GPIO_016      8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_015 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_GPIO_015         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_UART_CTS_0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_I2S_CLK0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_LED_KD_2         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_PKT_DATA2        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_EXT_IRQB_7       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_VEC_HSYNC_0      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_SC0_VPP          7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_TP_IN_01         8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_PM_GPIO_015      9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_014 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_GPIO_014         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_UART_RXD_0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_PWM_1            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_LED_KD_1         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_PKT_CLK2         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_EXT_IRQB_6       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_IR_IN1           6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_TP_IN_00         7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_PM_GPIO_014      8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_013 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_GPIO_013         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_UART_TXD_0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_PWM_0            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_LED_KD_0         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_PKT_VALID2       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_EXT_IRQB_5       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_IR_INT           6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_TP_OUT_30        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_PM_GPIO_013      8
+
+/***************************************************************************
+ *PIN_MUX_CTRL_10 - Pinmux control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_028 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_GPIO_028        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_SC1_RST         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_LED_LD_3        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_PKT_ERROR3      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_TP_IN_13        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_027 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_GPIO_027        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_SC1_PRES        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_LED_LD_2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_PKT_DATA3       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_TP_IN_12        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_PM_GPIO_027     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_026 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_GPIO_026        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_SC1_CLK         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_LED_LD_1        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_PKT_CLK3        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_TP_OUT_11       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_PM_GPIO_026     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_025 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_GPIO_025        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_SC1_IO          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_LED_LD_0        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_PKT_VALID3      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_UART_CTS_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_TP_IN_10        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_024 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_GPIO_024        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_UART_RTS_2      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_CHIP2CI_MCLKO   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_RMX_PAUSE1      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_SC_EXT_CLK      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_P1_INTR_1       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_TP_OUT_29       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_PM_GPIO_024     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_023 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_GPIO_023        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_UART_CTS_2      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_CI2CHIP_MCLKI   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_RMX_PAUSE0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_SC_CLK_OUT      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_TP_IN_08        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_PM_GPIO_023     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_022 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_GPIO_022        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_UART_RXD_2      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_EXT_IRQB_14     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_PKT_ERROR1      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_CHIP2CI_MOSTRT  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_TP_IN_06        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_PM_GPIO_022     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_021 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_GPIO_021        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_UART_TXD_2      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_EXT_IRQB_13     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_LED_LS_4        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_PKT_ERROR0      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_CHIP2CI_MOVAL   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_TP_OUT_07       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_PM_GPIO_021     7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_11 - Pinmux control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_036 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_GPIO_036        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_CI2CHIP_MIVAL   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_PPKT_VALID      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_PKT_ERROR1      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_RGMII_1_RXD_00  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_MTSIF_RX1_CLK   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_ALT_TP_OUT_06   6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_035 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_GPIO_035        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_CI2CHIP_MISTRT  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_PPKT_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_PKT_ERROR0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_MTSIF_RX0_DATA_0 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_ALT_TP_OUT_05   5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_034 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_GPIO_034        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_SC_EXT_CLK      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_PPKT_ERROR      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_MTSIF_ATS_RESET 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_TP_IN_19        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_PM_GPIO_034     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_033 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_GPIO_033        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_SC_CLK_OUT      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_MTSIF_ATS_INC   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_TP_IN_18        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_PM_GPIO_033     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_032 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_GPIO_032        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_SC1_VPP         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_LED_LD_7        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_I2S_LR0         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_TP_IN_17        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_PM_GPIO_032     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_031 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_GPIO_031        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_SC1_AUX_2       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_LED_LD_6        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_I2S_DATA0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_TP_IN_16        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_PM_GPIO_031     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_030 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_GPIO_030        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_SC1_AUX_1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_LED_LD_5        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_I2S_CLK0        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_TP_IN_15        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_PM_GPIO_030     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_029 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_GPIO_029        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_SC1_VCC         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_LED_LD_4        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_PKT_SYNC3       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_TP_IN_14        4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_12 - Pinmux control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_044 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_GPIO_044        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_CI2CHIP_MDI7    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_PPKT_DATA7      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_PKT_SYNC1       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_RGMII_1_TXD_02  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_MTSIF_RX1_DATA_6 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_TP_OUT_23       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_043 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_GPIO_043        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_CI2CHIP_MDI6    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_PPKT_DATA6      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_PKT_SYNC0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_RGMII_1_TXD_01  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_MTSIF_RX1_DATA_5 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_ALT_TP_OUT_09   6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_042 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_GPIO_042        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_CI2CHIP_MDI5    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_PPKT_DATA5      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_PKT_DATA1       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_RGMII_1_TXD_00  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_MTSIF_RX1_DATA_4 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_ALT_TP_OUT_08   6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_041 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_GPIO_041        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_CI2CHIP_MDI4    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_PPKT_DATA4      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_PKT_DATA0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_RGMII_1_RXCTL   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_MTSIF_RX1_DATA_3 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_ALT_TP_OUT_07   6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_040 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_GPIO_040        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_CI2CHIP_MDI3    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_PPKT_DATA3      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_PKT_CLK1        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_RGMII_1_RXCLK   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_SDS1_IF_AGC     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_MTSIF_RX1_DATA_2 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_ALT_TP_OUT_27   7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_039 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_GPIO_039        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_CI2CHIP_MDI2    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_PPKT_DATA2      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_PKT_CLK0        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_RGMII_1_RXD_03  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_SDS1_RF_AGC     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_MTSIF_RX1_DATA_1 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_038 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_GPIO_038        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_CI2CHIP_MDI1    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_PPKT_DATA1      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_PKT_VALID1      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_RGMII_1_RXD_02  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_UART_RTS_2      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_MTSIF_RX1_DATA_0 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_037 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_GPIO_037        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_CI2CHIP_MDI0    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_PPKT_DATA0      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_PKT_VALID0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_RGMII_1_RXD_01  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_UART_TXD_2      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_MTSIF_RX1_SYNC  6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_13 - Pinmux control register 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_052 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_GPIO_052        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_CHIP2CI_MDO4    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_RMXP_DATA4      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_PKT_CLK3        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_MII_1_CRS       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_EXT_IRQB_11     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_ALT_TP_OUT_18   6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_051 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_GPIO_051        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_CHIP2CI_MDO3    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_RMXP_DATA3      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_MII_1_COL       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_EXT_IRQB_10     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_ALT_TP_OUT_17   5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_050 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_GPIO_050        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_CHIP2CI_MDO2    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_RMXP_DATA2      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_MII_1_RXER      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_EXT_IRQB_9      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_ALT_TP_OUT_16   5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_049 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_GPIO_049        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_CHIP2CI_MDO1    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_RMXP_DATA1      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_EXT_IRQB_8      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_RGMII_1_MDIO    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_RMX_PAUSE1      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_PKT_SYNC5       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_ALT_TP_OUT_15   7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_048 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_GPIO_048        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_CHIP2CI_MDO0    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_RMXP_DATA0      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_EXT_IRQB_7      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_RGMII_1_MDC     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_RMX_PAUSE0      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_PKT_ERROR5      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_047 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_GPIO_047        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_CHIP2CI_MOSTRT  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_RMXP_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_EXT_IRQB_6      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_RGMII_1_TXCTL   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_SPI_M_SS2B      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_PKT_DATA5       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_ALT_TP_OUT_13   7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_046 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_GPIO_046        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_CHIP2CI_MOVAL   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_RMXP_VALID      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_EXT_IRQB_5      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_RGMII_1_TXCLK   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_SPI_M_SS1B      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_PKT_CLK5        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_ALT_TP_OUT_12   7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_045 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_GPIO_045        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_CI2CHIP_MICLK   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_PPKT_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_PKT_VALID5      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_RGMII_1_TXD_03  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_MTSIF_RX1_DATA_7 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_PM_GPIO_045     6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_14 - Pinmux control register 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_060 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_GPIO_060        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_SDS1_PKTP_DAT_5 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_SDS0_PKTP_DAT_5 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_SDS0_IF_AGC     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_PKT_SYNC5       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_059 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_GPIO_059        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_SDS1_PKTP_CLK   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_SDS0_PKTP_CLK   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_SDS0_RF_AGC     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_PKT_ERROR5      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_058 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_GPIO_058        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_SPI_M_MISO      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_PKT_DATA5       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_MTSIF_RX0_SYNC  3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_057 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_GPIO_057        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_SPI_M_MOSI      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_PKT_CLK5        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_VEC_VSYNC_1     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_VEC_HSYNC_1     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_056 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_GPIO_056        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_CHIP2CI_MOCLK   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_RMXP_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_PKT_SYNC3       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_EXT_IRQB_2      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_I2S_LR1_OUT     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_I2S_LR1_IN      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_SC0_VPP         7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_ALT_TP_OUT_22   8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_PM_GPIO_056     9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_055 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_GPIO_055        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_CHIP2CI_MDO7    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_RMXP_DATA7      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_PKT_ERROR3      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_EXT_IRQB_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_I2S_DATA1_OUT   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_I2S_DATA1_IN    6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_SC0_AUX_2       7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_ALT_TP_OUT_21   8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_PM_GPIO_055     9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_054 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_GPIO_054        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_CHIP2CI_MDO6    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_RMXP_DATA6      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_PKT_DATA3       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_EXT_IRQB_0      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_I2S_CLK1_OUT    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_I2S_CLK1_IN     6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_SC0_AUX_1       7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_ALT_TP_OUT_20   8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_PM_GPIO_054     9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_053 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_GPIO_053        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_CHIP2CI_MDO5    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_RMXP_DATA5      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_PKT_VALID3      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_MII_1_TXER      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_EXT_IRQB_12     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_ALT_TP_OUT_19   6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_15 - Pinmux control register 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_068 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_GPIO_068        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_GENET0_ACTIVITY 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_GENET1_LINK     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_SPI_M_SS0B      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_EXT_IRQB_5      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_MTSIF_RX0_CLK   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_TP_OUT_02       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_067 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_GPIO_067        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_SDS1_BERT_ERROR 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_SDS1_DEMOD_ERROR 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_SDS0_BERT_ERROR 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_SDS0_DEMOD_ERROR 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_PKT_ERROR2      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_MTSIF_RX0_DATA_5 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_066 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_GPIO_066        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_TNR_TSPI_RSTB   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_SDS1_BERT_VALID 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_SDS1_DEMOD_VALID 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_SDS0_BERT_VALID 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_SDS0_DEMOD_VALID 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_PKT_VALID2      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_MTSIF_RX0_DATA_4 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_065 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_GPIO_065        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_TNR_TST_MOSI    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_SDS1_BERT_SYNC  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_SDS1_DEMOD_SYNC 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_SDS0_BERT_SYNC  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_SDS0_DEMOD_SYNC 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_PKT_SYNC2       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_MTSIF_RX0_DATA_3 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_064 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_GPIO_064        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_TNR1_TST_SS_N   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_SDS1_BERT_DATA  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_SDS1_DEMOD_DATA 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_SDS0_BERT_DATA  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_SDS0_DEMOD_DATA 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_PKT_DATA2       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_MTSIF_RX0_DATA_7 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_063 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_GPIO_063        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_TNR0_TST_SS_N   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_SDS1_BERT_CLK   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_SDS1_DEMOD_CLK  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_SDS0_BERT_CLK   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_SDS0_DEMOD_CLK  5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_PKT_CLK2        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_MTSIF_RX0_DATA_6 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_062 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_GPIO_062        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_TNR_TST_SCK     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_SDS1_PKTP_DAT_7 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_SDS0_PKTP_DAT_7 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_SPI_S_MISO      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_SDS1_IF_AGC     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_TTX0_REQ        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_EXT_IRQB_3      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_061 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_GPIO_061        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_SDS1_PKTP_DAT_6 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_SDS0_PKTP_DAT_6 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_SPI_S_SS0B      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_SDS1_RF_AGC     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_TTX0_DATA       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_PKT_VALID5      6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_16 - Pinmux control register 16
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_04 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_SGPIO_04        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_BSC_M2_SCL      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_SDS0_RF_AGC     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_03 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_SGPIO_03        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_BSC_M1_SDA      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_UHFR_GLB_PWRDN  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_TP_IN_20        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_02 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_SGPIO_02        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_BSC_M1_SCL      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_UHFR_GLB_PWRDN  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_SDIO_LED        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_01 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_01_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_01_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_01_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_01_SGPIO_01        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_01_BSC_M3_SDA      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_00 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_00_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_00_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_00_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_00_SGPIO_00        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_00_BSC_M3_SCL      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_071 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_071_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_071_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_071_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_071_GPIO_071        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_071_CODEC_SDO       1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_070 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_GPIO_070        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_GENET1_LINK     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_TNR1_TST_MISO   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_EXT_IRQB_7      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_SPI_S_MISO      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_MTSIF_RX0_DATA_2 5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_069 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_GPIO_069        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_GENET1_ACTIVITY 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_EXT_IRQB_6      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_MTSIF_RX0_DATA_1 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_SPI_S_SS0B      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_TP_OUT_21       5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_17 - Pinmux control register 17
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: vo_656_5 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_5_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_5_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_5_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_5_VO_656_5        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_5_UART_CTS_2      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_5_SDIO_PRES       2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: vo_656_4 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_4_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_4_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_4_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_4_VO_656_4        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_4_SDIO_PWR0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_4_SDS1_BERT_ERROR 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_4_SDS1_DEMOD_ERROR 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_4_SDS0_BERT_ERROR 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_4_SDS0_DEMOD_ERROR 5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: vo_656_3 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_3_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_3_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_3_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_3_VO_656_3        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_3_UART_CTS_1      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_3_SDIO_DAT3       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_3_SDS1_BERT_VALID 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_3_SDS1_DEMOD_VALID 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_3_SDS0_BERT_VALID 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_3_SDS0_DEMOD_VALID 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: vo_656_2 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_2_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_2_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_2_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_2_VO_656_2        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_2_UART_RXD_1      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_2_SDIO_DAT2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_2_SDS1_BERT_SYNC  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_2_SDS1_DEMOD_SYNC 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_2_SDS0_BERT_SYNC  5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_2_SDS0_DEMOD_SYNC 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: vo_656_1 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_1_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_1_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_1_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_1_VO_656_1        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_1_UART_CTS_0      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_1_SDIO_DAT1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_1_SDS1_BERT_DATA  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_1_SDS1_DEMOD_DATA 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_1_SDS0_BERT_DATA  5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_1_SDS0_DEMOD_DATA 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: vo_656_0 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_0_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_0_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_0_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_0_VO_656_0        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_0_UART_RXD_0      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_0_SDIO_DAT0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_0_SDS1_BERT_CLK   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_0_SDS1_DEMOD_CLK  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_0_SDS0_BERT_CLK   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_0_SDS0_DEMOD_CLK  6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: clk27_out [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_clk27_out_MASK           0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_clk27_out_SHIFT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_clk27_out_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_clk27_out_CLK27_OUT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_clk27_out_TP_IN_11       1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: sgpio_05 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_05_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_05_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_05_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_05_SGPIO_05        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_05_BSC_M2_SDA      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_05_SDS0_IF_AGC     2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_18 - Pinmux control register 18
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_reserved0_MASK           0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_reserved0_SHIFT          28
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: sds1_dsec_selvtop [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_selvtop_MASK   0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_selvtop_SHIFT  24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_selvtop_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_selvtop_SDS1_DSEC_SELVTOP 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_selvtop_FTM_TXEN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_selvtop_ALT_TP_IN_26 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: sds1_dsec_txen [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_txen_MASK      0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_txen_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_txen_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_txen_SDS1_DSEC_TXEN 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_txen_FTM_RX_DATA_BYP 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: sds1_dsec_txout [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_txout_MASK     0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_txout_SHIFT    16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_txout_DEFAULT  0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_txout_SDS1_DSEC_TXOUT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_txout_FTM_UART_MAN_DATA 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: sds0_dsec_selvtop [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds0_dsec_selvtop_MASK   0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds0_dsec_selvtop_SHIFT  12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds0_dsec_selvtop_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds0_dsec_selvtop_SDS0_DSEC_SELVTOP 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds0_dsec_selvtop_FTM_TXEN 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: vo_656_clk [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_clk_MASK          0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_clk_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_clk_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_clk_VO_656_CLK    0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_clk_SDIO_CLK      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: vo_656_7 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_7_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_7_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_7_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_7_VO_656_7        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_7_SDIO_CMD        1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: vo_656_6 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_6_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_6_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_6_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_6_VO_656_6        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_6_UART_RXD_2      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_6_SDIO_WPROT      2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [29:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x3fffffff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0x3fffffff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [29:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK        0x3fffffff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: reserved0 [29:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved0_MASK        0x3fffffff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved0 [29:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_MASK        0x3c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_SHIFT       26
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr27_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr26_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr25_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr24_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved1 [17:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved1_MASK        0x0003f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved1_SHIFT       12
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr23_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr23_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr23_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr23_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr23_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr23_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr23_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved2 [09:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved2_MASK        0x000003ff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved2_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_000_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: reserved0 [27:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_MASK        0x0fffff00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_SHIFT       8
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: ebi_dsb_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_dsb_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_dsb_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_dsb_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_dsb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_dsb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_dsb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: ebi_tsb_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_tsb_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_tsb_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_tsb_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_tsb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_tsb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_tsb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: reserved1 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved1_MASK        0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved1_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_015_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_014_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_013_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: reserved0 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved0_MASK        0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved0_SHIFT       20
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_010_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_010_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_010_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_010_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_010_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_010_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_010_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_009_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_009_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_009_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_009_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_009_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_009_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_009_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: reserved1 [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved1_MASK        0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved1_SHIFT       14
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_007_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_007_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_007_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_007_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_007_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_007_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_007_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_006_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_006_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_006_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_006_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_006_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_006_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_006_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_005_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_005_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_005_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_005_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_005_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_005_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_005_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_004_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_004_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_004_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_004_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_004_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_004_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_004_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_003_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_003_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_003_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_003_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_003_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_003_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_003_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_002_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_002_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_002_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_002_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_002_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_002_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_002_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_001_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_001_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_001_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_001_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_001_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_001_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_001_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_030_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: reserved0 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_reserved0_MASK        0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_reserved0_SHIFT       24
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_027_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_026_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: reserved1 [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_reserved1_MASK        0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_reserved1_SHIFT       18
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_024_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_024_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_024_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_024_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_024_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_024_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_024_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_023_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_023_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_023_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_023_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_023_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_023_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_023_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_022_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_022_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_022_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_022_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_022_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_022_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_022_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_021_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_021_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_021_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_021_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_021_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_021_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_021_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_020_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_020_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_020_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_020_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_020_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_020_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_020_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_019_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_019_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_019_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_019_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_019_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_019_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_019_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_018_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_018_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_018_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_018_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_018_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_018_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_018_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_017_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_017_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_017_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_017_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_017_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_017_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_017_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_016_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_016_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_016_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_016_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_016_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_016_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_016_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_045_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_044_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_043_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_042_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_041_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_040_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_040_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_040_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_040_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_040_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_040_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_040_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_039_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_039_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_039_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_039_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_039_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_039_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_039_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_038_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_038_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_038_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_038_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_038_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_038_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_038_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_037_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_037_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_037_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_037_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_037_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_037_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_037_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_036_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_036_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_036_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_036_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_036_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_036_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_036_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_035_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_035_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_035_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_035_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_035_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_035_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_035_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_034_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_034_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_034_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_034_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_034_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_034_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_034_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_033_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_033_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_033_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_033_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_033_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_033_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_033_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_032_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_032_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_032_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_032_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_032_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_032_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_032_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_031_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_031_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_031_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_031_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_031_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_031_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_031_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_9 - Pad pull-up/pull-down control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: spare_pad_ctrl_9 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_060_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_059_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_058_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_057_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_056_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_055_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_055_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_055_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_055_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_055_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_055_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_055_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_054_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_054_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_054_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_054_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_054_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_054_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_054_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_053_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_053_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_053_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_053_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_053_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_053_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_053_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_052_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_052_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_052_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_052_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_052_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_052_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_052_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_051_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_051_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_051_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_051_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_051_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_051_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_051_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_050_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_050_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_050_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_050_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_050_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_050_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_050_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_049_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_049_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_049_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_049_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_049_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_049_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_049_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_048_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_048_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_048_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_048_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_048_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_048_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_048_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_047_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_047_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_047_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_047_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_047_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_047_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_047_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_046_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_046_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_046_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_046_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_046_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_046_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_046_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_10 - Pad pull-up/pull-down control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: spare_pad_ctrl_10 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: reserved0 [29:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_reserved0_MASK       0x3fc00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_reserved0_SHIFT      22
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_071_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_070_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_070_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_070_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_070_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_070_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_070_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_070_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_069_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_069_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_069_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_069_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_069_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_069_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_069_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_068_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_068_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_068_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_068_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_068_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_068_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_068_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_067_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_067_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_067_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_067_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_067_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_067_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_067_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_066_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_066_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_066_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_066_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_066_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_066_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_066_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_065_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_065_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_065_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_065_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_065_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_065_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_065_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_064_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_064_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_064_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_064_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_064_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_064_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_064_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_063_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_063_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_063_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_063_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_063_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_063_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_063_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_062_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_062_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_062_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_062_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_062_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_062_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_062_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_061_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_061_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_061_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_061_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_061_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_061_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_061_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_11 - Pad pull-up/pull-down control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: spare_pad_ctrl_11 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: reserved0 [29:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved0_MASK       0x3fffffff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved0_SHIFT      0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_12 - Pad pull-up/pull-down control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: reserved0 [31:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_reserved0_MASK       0xfc000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_reserved0_SHIFT      26
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: spare_pad_ctrl_12 [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: reserved1 [23:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_reserved1_MASK       0x00ffffff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_reserved1_SHIFT      0
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xc0000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       30
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_dsp_clk [29:29] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_dsp_clk_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_dsp_clk_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_dsp_clk_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_avd_clk [28:28] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_avd_clk_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_avd_clk_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_avd_clk_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_cpu_clk [27:27] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_cpu_clk_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_cpu_clk_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_cpu_clk_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_sys9_clk [26:26] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_sys9_clk_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_sys9_clk_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_sys9_clk_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_068 [25:25] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_068_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_068_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_068_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_058 [24:24] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_058_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_058_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_058_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_057 [23:23] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_057_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_057_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_057_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_056 [22:22] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_056_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_056_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_056_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_055 [21:21] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_055_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_055_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_055_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_054 [20:20] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_054_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_054_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_054_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_053 [19:19] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_053_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_053_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_053_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_052 [18:18] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_052_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_052_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_052_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_051 [17:17] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_051_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_051_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_051_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_050 [16:16] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_050_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_050_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_050_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_049 [15:15] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_049_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_049_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_049_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_048 [14:14] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_048_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_048_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_048_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_045 [13:13] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_045_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_045_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_045_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_040 [12:12] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_040_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_040_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_040_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_039 [11:11] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_039_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_039_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_039_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_038 [10:10] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_038_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_038_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_038_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_037 [09:09] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_037_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_037_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_037_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_019 [08:08] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_019_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_019_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_019_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_005 [07:07] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_005_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_005_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_005_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_004 [06:06] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_004_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_004_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_004_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_003 [05:05] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_003_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_003_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_003_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_cs3b [04:04] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs3b_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs3b_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs3b_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_cs2b [03:03] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs2b_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs2b_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs2b_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_cs1b [02:02] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs1b_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs1b_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs1b_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_cs4b [01:01] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs4b_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs4b_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs4b_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_mii_col [00:00] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_mii_col_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_mii_col_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_mii_col_DEFAULT 0
+
+/***************************************************************************
+ *RESET_CTRL - Reset control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0xfffffffe
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               1
+
+/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT   0
+
+/***************************************************************************
+ *RESET_SOURCE_ENABLE - Reset source enable
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK       0xfffffc00
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT      10
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0
+
+/***************************************************************************
+ *SW_MASTER_RESET - Software master reset
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK           0xfffffffe
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT          1
+
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0
+
+/***************************************************************************
+ *HW_RESET_EXTENSION - Hardware reset extension
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0
+
+/***************************************************************************
+ *RESET_MONITOR - Reset Monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT  7
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT   6
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT   4
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset history
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:17] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xfffe0000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            17
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [16:16] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 16
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [15:15] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 15
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [14:14] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 14
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [13:13] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 13
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_reset [12:12] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_MASK    0x00001000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT   12
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_reset [11:11] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT    11
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [10:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT       10
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK       0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT      9
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_dl_sw_reset [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK  0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT 8
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 7
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 6
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK   0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT  4
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0
+
+/***************************************************************************
+ *SW_INIT_0_SET - Software init 0 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved0_MASK             0xc0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved0_SHIFT            30
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_MASK          0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_MASK          0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_SHIFT         28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_MASK        0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_SHIFT       27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK        0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT       26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_MASK          0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_SHIFT         25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK          0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK   0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT  23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_MASK   0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_SHIFT  22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK          0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT         21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_MASK   0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_SHIFT  20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK         0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT        19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK           0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT          18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK   0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT  17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_MASK         0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_SHIFT        16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK           0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT          15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK           0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT          14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_MASK   0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_SHIFT  13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_MASK          0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_MASK   0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_SHIFT  11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT       10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK           0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT          9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK           0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK           0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT          6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_SHIFT   4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT   0
+
+/***************************************************************************
+ *SW_INIT_0_CLEAR - Software init 0 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved0_MASK           0xc0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved0_SHIFT          30
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_MASK        0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_SHIFT       29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_MASK        0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_SHIFT       28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_MASK      0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_SHIFT     27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK      0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT     26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_MASK        0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_SHIFT       25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK        0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT       24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK        0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT       21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK       0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT      19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK         0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT        18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_MASK       0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK         0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT        15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK         0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT        14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_MASK        0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_SHIFT       12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK      0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT     10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK         0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT        9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK         0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK         0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT        6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT  0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *SW_INIT_0_STATUS - Software init 0 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved0_MASK          0xc0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved0_SHIFT         30
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_MASK       0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_SHIFT      29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_DEFAULT    1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_MASK       0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_SHIFT      28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_DEFAULT    1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_MASK       0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_SHIFT      25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK       0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK       0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT      21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK      0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT     19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK        0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT       18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_MASK      0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_DEFAULT   1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK        0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT       15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK        0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT       14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_MASK       0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_DEFAULT    1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK        0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT   2
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT       1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved0_MASK     0xc0000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved0_SHIFT    30
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_MASK  0x20000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_MASK  0x10000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_MASK  0x02000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK  0x01000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK  0x00200000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK   0x00040000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT  18
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK   0x00008000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT  15
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK   0x00004000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT  14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_svd0_sw_init_MASK  0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK   0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT  9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK   0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT  8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT  6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved0_SHIFT 30
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved0_MASK   0xc0000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved0_SHIFT  30
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_1_SET - Software init 1 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK             0xfffffc00
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT            10
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK        0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds1_a_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_a_sw_init_MASK        0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_a_sw_init_SHIFT       7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_a_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds1_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top_sw_init_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top_sw_init_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_5_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_5_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_MASK        0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_SHIFT       4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_SHIFT   2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_uhfr_sw_init_MASK          0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_uhfr_sw_init_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_uhfr_sw_init_DEFAULT       0
+
+/***************************************************************************
+ *SW_INIT_1_CLEAR - Software init 1 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK           0xfffffc00
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT          10
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds1_a_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_a_sw_init_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_a_sw_init_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_a_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds1_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top_sw_init_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top_sw_init_SHIFT   6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_uhfr_sw_init_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_uhfr_sw_init_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_uhfr_sw_init_DEFAULT     0
+
+/***************************************************************************
+ *SW_INIT_1_STATUS - Software init 1 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK          0xfffffc00
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT         10
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK     0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT    9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK     0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT    8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT  0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds1_a_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_a_sw_init_MASK     0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_a_sw_init_SHIFT    7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_a_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds1_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top_sw_init_SHIFT  6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top_sw_init_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_5_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_MASK   0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_SHIFT  3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_SHIFT       1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_uhfr_sw_init_MASK       0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_uhfr_sw_init_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_uhfr_sw_init_DEFAULT    1
+
+/***************************************************************************
+ *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK     0xfffffc00
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT    10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds1_a_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_a_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_a_sw_init_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds1_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_uhfr_sw_init_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_uhfr_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xfffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds1_a_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_a_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_a_sw_init_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds1_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_uhfr_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK   0xfffffc00
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT  10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds1_a_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_a_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_a_sw_init_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds1_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_uhfr_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK  0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved0_SHIFT 30
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 1
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xfffffc00
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 10
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds1_a_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_a_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_a_sw_init_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_a_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds1_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_uhfr_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_uhfr_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved0_SHIFT 30
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 1
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xfffffc00
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 10
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds1_a_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_a_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_a_sw_init_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_a_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds1_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_uhfr_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_uhfr_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0
+
+/***************************************************************************
+ *SPARE_CTRL - Spare control bits reserved for future use
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT         0
+
+/***************************************************************************
+ *TEST_PORT_CTRL - Test port control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SOFT_MODEM_TP 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT         0
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 127
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0  0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET1  1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU     2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SATA    3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R  4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_A  5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T  6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_R  7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_A  8
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_T  9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS     16
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK     17
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON     18
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     20
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     21
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE    22
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM    23
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC     25
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DVP_HT  26
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SVD0    27
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GFX     29
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO     30
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA   31
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     33
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0   35
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0    45
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB1    46
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MOCA    47
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_UHFR    50
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_FTM     51
+
+/***************************************************************************
+ *TEST_PORT_OUT_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_OUT_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0
+
+/***************************************************************************
+ *EJTAG_INPUT_EN - EJTAG input bus enables
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xfffffff0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           4
+
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [03:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x0000000f
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA_CPU_ONE_HOT 4
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 8
+
+/***************************************************************************
+ *EJTAG_OUTPUT_SEL - EJTAG output select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         3
+
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA_CPU 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 3
+
+/***************************************************************************
+ *UART_ROUTER_SEL - UART Router select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK      0xf0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT     28
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK      0x0f000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT     24
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK      0x00f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK      0x000f0000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK      0x0000f000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK      0x00000f00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK      0x0000000f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15
+
+/***************************************************************************
+ *VTRAP_CTRL - VTRAP Control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK                0xfffff000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT               12
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_threshold [11:11] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_threshold [10:10] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_threshold [09:09] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_DEFAULT 1
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [08:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x000001f8
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 24
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_status_clear [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_status_clear [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_status_clear [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_DEFAULT 0
+
+/***************************************************************************
+ *VTRAP_STATUS - VTRAP Status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK              0xfffffff8
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT             3
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_status [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_status [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_status [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_DEFAULT 0
+
+/***************************************************************************
+ *SSP_CONFIG - Serial Slave Port configuration register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT        4
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT           0
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT     1
+
+/***************************************************************************
+ *SERS_REV - SERS Revision Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16
+
+/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT     0
+
+/***************************************************************************
+ *SERS_CFG - SERS Configuration Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT                1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT           0
+
+/* union - case mapped_buffer_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0
+
+/* union - case cmd_fifo_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 31
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 16
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT  0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT                 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT            0
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x00404428
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0
+
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x00404448
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0
+
+
+/***************************************************************************
+ *RO_TEST_BLOCK_SEL - Block select for RO testmode
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xffffffe0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        5
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_pwenb [04:04] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DEFAULT  1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_ENABLED  0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DISABLED 1
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [03:02] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MIN_LOAD 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MED_LOAD 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MAX_LOAD 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SVT_MIN_LOAD 3
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
+
+/***************************************************************************
+ *TEST_CONFIGURATION - Test configuration
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0
+
+#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_timer.h b/include/linux/brcmstb/7346b0/bchp_timer.h
new file mode 100644
index 0000000..7680ffc
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_timer.h
@@ -0,0 +1,340 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:26:15 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_timer.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 5:53p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_TIMER_H__
+#define BCHP_TIMER_H__
+
+/***************************************************************************
+ *TIMER - Watchdog & Programmable Timers
+ ***************************************************************************/
+#define BCHP_TIMER_TIMER_IS                      0x004067c0 /* TIMER INTERRUPT STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE0                     0x004067c4 /* TIMER CPU INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_TIMER0_CTRL                   0x004067c8 /* TIMER0 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER1_CTRL                   0x004067cc /* TIMER1 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER2_CTRL                   0x004067d0 /* TIMER2 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER3_CTRL                   0x004067d4 /* TIMER3 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER0_STAT                   0x004067d8 /* TIMER0 STATUS REGISTER */
+#define BCHP_TIMER_TIMER1_STAT                   0x004067dc /* TIMER1 STATUS REGISTER */
+#define BCHP_TIMER_TIMER2_STAT                   0x004067e0 /* TIMER2 STATUS REGISTER */
+#define BCHP_TIMER_TIMER3_STAT                   0x004067e4 /* TIMER3 STATUS REGISTER */
+#define BCHP_TIMER_WDTIMEOUT                     0x004067e8 /* WATCHDOG TIMEOUT REGISTER */
+#define BCHP_TIMER_WDCMD                         0x004067ec /* WATCHDOG COMMAND REGISTER */
+#define BCHP_TIMER_WDCHIPRST_CNT                 0x004067f0 /* WATCHDOG CHIP RESET COUNT REGISTER */
+#define BCHP_TIMER_WDCRS                         0x004067f4 /* WATCHDOG CHIP RESET STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE1                     0x004067f8 /* TIMER PCI INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_WDCTRL                        0x004067fc /* WATCHDOG CONTROL REGISTER */
+
+/***************************************************************************
+ *TIMER_IS - TIMER INTERRUPT STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IS :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IS_reserved0_MASK                         0xffffffe0
+#define BCHP_TIMER_TIMER_IS_reserved0_SHIFT                        5
+
+/* TIMER :: TIMER_IS :: WDINT [04:04] */
+#define BCHP_TIMER_TIMER_IS_WDINT_MASK                             0x00000010
+#define BCHP_TIMER_TIMER_IS_WDINT_SHIFT                            4
+#define BCHP_TIMER_TIMER_IS_WDINT_DEFAULT                          0
+
+/* TIMER :: TIMER_IS :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IS_TMR3TO_MASK                            0x00000008
+#define BCHP_TIMER_TIMER_IS_TMR3TO_SHIFT                           3
+#define BCHP_TIMER_TIMER_IS_TMR3TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IS_TMR2TO_MASK                            0x00000004
+#define BCHP_TIMER_TIMER_IS_TMR2TO_SHIFT                           2
+#define BCHP_TIMER_TIMER_IS_TMR2TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IS_TMR1TO_MASK                            0x00000002
+#define BCHP_TIMER_TIMER_IS_TMR1TO_SHIFT                           1
+#define BCHP_TIMER_TIMER_IS_TMR1TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IS_TMR0TO_MASK                            0x00000001
+#define BCHP_TIMER_TIMER_IS_TMR0TO_SHIFT                           0
+#define BCHP_TIMER_TIMER_IS_TMR0TO_DEFAULT                         0
+
+/***************************************************************************
+ *TIMER_IE0 - TIMER CPU INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE0 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE0_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE0_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE0 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_DEFAULT                     0
+
+/* TIMER :: TIMER_IE0 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_DEFAULT                        0
+
+/***************************************************************************
+ *TIMER0_CTRL - TIMER0 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER0_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER0_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER0_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER0_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER0_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER0_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER0_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER0_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER1_CTRL - TIMER1 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER1_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER1_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER1_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER1_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER1_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER1_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER1_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER1_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER2_CTRL - TIMER2 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER2_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER2_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER2_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER2_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER2_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER2_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER2_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER2_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER3_CTRL - TIMER3 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER3_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER3_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER3_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER3_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER3_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER3_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER3_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER3_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER0_STAT - TIMER0 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER0_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER0_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER0_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER1_STAT - TIMER1 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER1_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER1_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER1_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER2_STAT - TIMER2 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER2_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER2_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER2_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER3_STAT - TIMER3 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER3_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER3_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER3_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *WDTIMEOUT - WATCHDOG TIMEOUT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDTIMEOUT :: WDTIMEOUT_VAL [31:00] */
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_MASK                    0xffffffff
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *WDCMD - WATCHDOG COMMAND REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCMD :: WDCMD [31:00] */
+#define BCHP_TIMER_WDCMD_WDCMD_MASK                                0xffffffff
+#define BCHP_TIMER_WDCMD_WDCMD_SHIFT                               0
+#define BCHP_TIMER_WDCMD_WDCMD_DEFAULT                             0
+
+/***************************************************************************
+ *WDCHIPRST_CNT - WATCHDOG CHIP RESET COUNT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCHIPRST_CNT :: reserved0 [31:26] */
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_MASK                    0xfc000000
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_SHIFT                   26
+
+/* TIMER :: WDCHIPRST_CNT :: WDCHIPRST_CNT [25:00] */
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_MASK                0x03ffffff
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_SHIFT               0
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_DEFAULT             50331647
+
+/***************************************************************************
+ *WDCRS - WATCHDOG CHIP RESET STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCRS :: reserved0 [31:01] */
+#define BCHP_TIMER_WDCRS_reserved0_MASK                            0xfffffffe
+#define BCHP_TIMER_WDCRS_reserved0_SHIFT                           1
+
+/* TIMER :: WDCRS :: WDCR [00:00] */
+#define BCHP_TIMER_WDCRS_WDCR_MASK                                 0x00000001
+#define BCHP_TIMER_WDCRS_WDCR_SHIFT                                0
+#define BCHP_TIMER_WDCRS_WDCR_DEFAULT                              0
+
+/***************************************************************************
+ *TIMER_IE1 - TIMER PCI INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE1 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE1_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE1_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE1 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_DEFAULT                     0
+
+/* TIMER :: TIMER_IE1 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_DEFAULT                        0
+
+/***************************************************************************
+ *WDCTRL - WATCHDOG CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCTRL :: reserved0 [31:03] */
+#define BCHP_TIMER_WDCTRL_reserved0_MASK                           0xfffffff8
+#define BCHP_TIMER_WDCTRL_reserved0_SHIFT                          3
+
+/* TIMER :: WDCTRL :: WD_COUNT_MODE [02:02] */
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_MASK                       0x00000004
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_SHIFT                      2
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_DEFAULT                    0
+
+/* TIMER :: WDCTRL :: WD_EVENT_MODE [01:00] */
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_MASK                       0x00000003
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_SHIFT                      0
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_DEFAULT                    0
+
+#endif /* #ifndef BCHP_TIMER_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_uarta.h b/include/linux/brcmstb/7346b0/bchp_uarta.h
new file mode 100644
index 0000000..b537d8e
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_uarta.h
@@ -0,0 +1,394 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:35:13 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_uarta.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 5:55p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTA_H__
+#define BCHP_UARTA_H__
+
+/***************************************************************************
+ *UARTA - UART A
+ ***************************************************************************/
+#define BCHP_UARTA_RBR                           0x00406900 /* Receive Buffer Register */
+#define BCHP_UARTA_THR                           0x00406900 /* Transmit Holding Register */
+#define BCHP_UARTA_DLH                           0x00406904 /* Divisor Latch High */
+#define BCHP_UARTA_DLL                           0x00406900 /* Divisor Latch Low */
+#define BCHP_UARTA_IER                           0x00406904 /* Interrupt Enable Register */
+#define BCHP_UARTA_IIR                           0x00406908 /* Interrupt Identity Register */
+#define BCHP_UARTA_FCR                           0x00406908 /* FIFO Control Register */
+#define BCHP_UARTA_LCR                           0x0040690c /* Line Control Register */
+#define BCHP_UARTA_MCR                           0x00406910 /* Modem Control Register */
+#define BCHP_UARTA_LSR                           0x00406914 /* Line Status Register */
+#define BCHP_UARTA_MSR                           0x00406918 /* Modem Status Register */
+#define BCHP_UARTA_SCR                           0x0040691c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTA :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTA_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_RBR_reserved0_SHIFT                             8
+
+/* UARTA :: RBR :: RBR [07:00] */
+#define BCHP_UARTA_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTA_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTA_RBR_RBR_DEFAULT                                 0
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTA :: THR :: reserved0 [31:08] */
+#define BCHP_UARTA_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_THR_reserved0_SHIFT                             8
+
+/* UARTA :: THR :: THR [07:00] */
+#define BCHP_UARTA_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTA_THR_THR_SHIFT                                   0
+#define BCHP_UARTA_THR_THR_DEFAULT                                 0
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTA :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTA_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLH_reserved0_SHIFT                             8
+
+/* UARTA :: DLH :: DLH [07:00] */
+#define BCHP_UARTA_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTA_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTA_DLH_DLH_DEFAULT                                 0
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTA :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTA_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLL_reserved0_SHIFT                             8
+
+/* UARTA :: DLL :: DLL [07:00] */
+#define BCHP_UARTA_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTA_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTA_DLL_DLL_DEFAULT                                 0
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTA :: IER :: reserved0 [31:08] */
+#define BCHP_UARTA_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IER_reserved0_SHIFT                             8
+
+/* UARTA :: IER :: PTIME [07:07] */
+#define BCHP_UARTA_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTA_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTA_IER_PTIME_DEFAULT                               0
+
+/* UARTA :: IER :: reserved1 [06:04] */
+#define BCHP_UARTA_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTA_IER_reserved1_SHIFT                             4
+
+/* UARTA :: IER :: EDSSI [03:03] */
+#define BCHP_UARTA_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTA_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTA_IER_EDSSI_DEFAULT                               0
+
+/* UARTA :: IER :: ELSI [02:02] */
+#define BCHP_UARTA_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTA_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTA_IER_ELSI_DEFAULT                                0
+
+/* UARTA :: IER :: ETBEI [01:01] */
+#define BCHP_UARTA_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTA_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTA_IER_ETBEI_DEFAULT                               0
+
+/* UARTA :: IER :: ERBFI [00:00] */
+#define BCHP_UARTA_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTA_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTA_IER_ERBFI_DEFAULT                               0
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTA :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTA_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IIR_reserved0_SHIFT                             8
+
+/* UARTA :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTA_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTA_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTA_IIR_FIFOSE_DEFAULT                              0
+
+/* UARTA :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTA_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTA_IIR_reserved1_SHIFT                             4
+
+/* UARTA :: IIR :: IID [03:00] */
+#define BCHP_UARTA_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTA_IIR_IID_SHIFT                                   0
+#define BCHP_UARTA_IIR_IID_DEFAULT                                 1
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTA :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTA_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_FCR_reserved0_SHIFT                             8
+
+/* UARTA :: FCR :: RT [07:06] */
+#define BCHP_UARTA_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTA_FCR_RT_SHIFT                                    6
+#define BCHP_UARTA_FCR_RT_DEFAULT                                  0
+
+/* UARTA :: FCR :: TET [05:04] */
+#define BCHP_UARTA_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTA_FCR_TET_SHIFT                                   4
+#define BCHP_UARTA_FCR_TET_DEFAULT                                 0
+
+/* UARTA :: FCR :: DMAM [03:03] */
+#define BCHP_UARTA_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTA_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTA_FCR_DMAM_DEFAULT                                0
+
+/* UARTA :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTA_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTA_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTA_FCR_XFIFOR_DEFAULT                              0
+
+/* UARTA :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTA_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTA_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTA_FCR_RFIFOR_DEFAULT                              0
+
+/* UARTA :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTA_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTA_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTA_FCR_FIFOE_DEFAULT                               0
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTA :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTA_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LCR_reserved0_SHIFT                             8
+
+/* UARTA :: LCR :: DLAB [07:07] */
+#define BCHP_UARTA_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTA_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTA_LCR_DLAB_DEFAULT                                0
+
+/* UARTA :: LCR :: BC [06:06] */
+#define BCHP_UARTA_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTA_LCR_BC_SHIFT                                    6
+#define BCHP_UARTA_LCR_BC_DEFAULT                                  0
+
+/* UARTA :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTA_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTA_LCR_reserved1_SHIFT                             5
+
+/* UARTA :: LCR :: EPS [04:04] */
+#define BCHP_UARTA_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTA_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTA_LCR_EPS_DEFAULT                                 0
+
+/* UARTA :: LCR :: PEN [03:03] */
+#define BCHP_UARTA_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTA_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTA_LCR_PEN_DEFAULT                                 0
+
+/* UARTA :: LCR :: STOP [02:02] */
+#define BCHP_UARTA_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTA_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTA_LCR_STOP_DEFAULT                                0
+
+/* UARTA :: LCR :: DLS [01:00] */
+#define BCHP_UARTA_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTA_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTA_LCR_DLS_DEFAULT                                 0
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTA :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTA_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTA_MCR_reserved0_SHIFT                             7
+
+/* UARTA :: MCR :: SIRE [06:06] */
+#define BCHP_UARTA_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTA_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTA_MCR_SIRE_DEFAULT                                0
+
+/* UARTA :: MCR :: AFCE [05:05] */
+#define BCHP_UARTA_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTA_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTA_MCR_AFCE_DEFAULT                                0
+
+/* UARTA :: MCR :: LB [04:04] */
+#define BCHP_UARTA_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTA_MCR_LB_SHIFT                                    4
+#define BCHP_UARTA_MCR_LB_DEFAULT                                  0
+
+/* UARTA :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTA_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTA_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTA_MCR_OUT2_DEFAULT                                0
+
+/* UARTA :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTA_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTA_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTA_MCR_OUT1_DEFAULT                                0
+
+/* UARTA :: MCR :: RTS [01:01] */
+#define BCHP_UARTA_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTA_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTA_MCR_RTS_DEFAULT                                 0
+
+/* UARTA :: MCR :: DTR [00:00] */
+#define BCHP_UARTA_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTA_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTA_MCR_DTR_DEFAULT                                 0
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTA :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTA_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LSR_reserved0_SHIFT                             8
+
+/* UARTA :: LSR :: RFE [07:07] */
+#define BCHP_UARTA_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTA_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTA_LSR_RFE_DEFAULT                                 0
+
+/* UARTA :: LSR :: TEMT [06:06] */
+#define BCHP_UARTA_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTA_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTA_LSR_TEMT_DEFAULT                                1
+
+/* UARTA :: LSR :: THRE [05:05] */
+#define BCHP_UARTA_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTA_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTA_LSR_THRE_DEFAULT                                1
+
+/* UARTA :: LSR :: BI [04:04] */
+#define BCHP_UARTA_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTA_LSR_BI_SHIFT                                    4
+#define BCHP_UARTA_LSR_BI_DEFAULT                                  0
+
+/* UARTA :: LSR :: FE [03:03] */
+#define BCHP_UARTA_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTA_LSR_FE_SHIFT                                    3
+#define BCHP_UARTA_LSR_FE_DEFAULT                                  0
+
+/* UARTA :: LSR :: PE [02:02] */
+#define BCHP_UARTA_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTA_LSR_PE_SHIFT                                    2
+#define BCHP_UARTA_LSR_PE_DEFAULT                                  0
+
+/* UARTA :: LSR :: OE [01:01] */
+#define BCHP_UARTA_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTA_LSR_OE_SHIFT                                    1
+#define BCHP_UARTA_LSR_OE_DEFAULT                                  0
+
+/* UARTA :: LSR :: DR [00:00] */
+#define BCHP_UARTA_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTA_LSR_DR_SHIFT                                    0
+#define BCHP_UARTA_LSR_DR_DEFAULT                                  0
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTA :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTA_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_MSR_reserved0_SHIFT                             8
+
+/* UARTA :: MSR :: DCD [07:07] */
+#define BCHP_UARTA_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTA_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTA_MSR_DCD_DEFAULT                                 0
+
+/* UARTA :: MSR :: RI [06:06] */
+#define BCHP_UARTA_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTA_MSR_RI_SHIFT                                    6
+#define BCHP_UARTA_MSR_RI_DEFAULT                                  0
+
+/* UARTA :: MSR :: DSR [05:05] */
+#define BCHP_UARTA_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTA_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTA_MSR_DSR_DEFAULT                                 0
+
+/* UARTA :: MSR :: CTS [04:04] */
+#define BCHP_UARTA_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTA_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTA_MSR_CTS_DEFAULT                                 0
+
+/* UARTA :: MSR :: DDCD [03:03] */
+#define BCHP_UARTA_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTA_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTA_MSR_DDCD_DEFAULT                                0
+
+/* UARTA :: MSR :: TERI [02:02] */
+#define BCHP_UARTA_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTA_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTA_MSR_TERI_DEFAULT                                0
+
+/* UARTA :: MSR :: DDSR [01:01] */
+#define BCHP_UARTA_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTA_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTA_MSR_DDSR_DEFAULT                                0
+
+/* UARTA :: MSR :: DCTS [00:00] */
+#define BCHP_UARTA_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTA_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTA_MSR_DCTS_DEFAULT                                0
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTA :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTA_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_SCR_reserved0_SHIFT                             8
+
+/* UARTA :: SCR :: SCR [07:00] */
+#define BCHP_UARTA_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTA_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTA_SCR_SCR_DEFAULT                                 0
+
+#endif /* #ifndef BCHP_UARTA_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_uartb.h b/include/linux/brcmstb/7346b0/bchp_uartb.h
new file mode 100644
index 0000000..dad148b
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_uartb.h
@@ -0,0 +1,63 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug  2 15:19:59 2010
+ *                 MD5 Checksum         616c5da46e7f2e811fb57b174083665d
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/a0/bchp_uartb.h $
+ * 
+ * Hydra_Software_Devel/1   8/2/10 7:58p pntruong
+ * SW7346-2: Initial version.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTB_H__
+#define BCHP_UARTB_H__
+
+/***************************************************************************
+ *UARTB - UART B
+ ***************************************************************************/
+#define BCHP_UARTB_RBR                           0x00406940 /* Receive Buffer Register */
+#define BCHP_UARTB_THR                           0x00406940 /* Transmit Holding Register */
+#define BCHP_UARTB_DLH                           0x00406944 /* Divisor Latch High */
+#define BCHP_UARTB_DLL                           0x00406940 /* Divisor Latch Low */
+#define BCHP_UARTB_IER                           0x00406944 /* Interrupt Enable Register */
+#define BCHP_UARTB_IIR                           0x00406948 /* Interrupt Identity Register */
+#define BCHP_UARTB_FCR                           0x00406948 /* FIFO Control Register */
+#define BCHP_UARTB_LCR                           0x0040694c /* Line Control Register */
+#define BCHP_UARTB_MCR                           0x00406950 /* Modem Control Register */
+#define BCHP_UARTB_LSR                           0x00406954 /* Line Status Register */
+#define BCHP_UARTB_MSR                           0x00406958 /* Modem Status Register */
+#define BCHP_UARTB_SCR                           0x0040695c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTB_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_uartc.h b/include/linux/brcmstb/7346b0/bchp_uartc.h
new file mode 100644
index 0000000..547c9ab
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_uartc.h
@@ -0,0 +1,63 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug  2 15:05:39 2010
+ *                 MD5 Checksum         616c5da46e7f2e811fb57b174083665d
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/a0/bchp_uartc.h $
+ * 
+ * Hydra_Software_Devel/1   8/2/10 7:59p pntruong
+ * SW7346-2: Initial version.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTC_H__
+#define BCHP_UARTC_H__
+
+/***************************************************************************
+ *UARTC - UART C
+ ***************************************************************************/
+#define BCHP_UARTC_RBR                           0x00406980 /* Receive Buffer Register */
+#define BCHP_UARTC_THR                           0x00406980 /* Transmit Holding Register */
+#define BCHP_UARTC_DLH                           0x00406984 /* Divisor Latch High */
+#define BCHP_UARTC_DLL                           0x00406980 /* Divisor Latch Low */
+#define BCHP_UARTC_IER                           0x00406984 /* Interrupt Enable Register */
+#define BCHP_UARTC_IIR                           0x00406988 /* Interrupt Identity Register */
+#define BCHP_UARTC_FCR                           0x00406988 /* FIFO Control Register */
+#define BCHP_UARTC_LCR                           0x0040698c /* Line Control Register */
+#define BCHP_UARTC_MCR                           0x00406990 /* Modem Control Register */
+#define BCHP_UARTC_LSR                           0x00406994 /* Line Status Register */
+#define BCHP_UARTC_MSR                           0x00406998 /* Modem Status Register */
+#define BCHP_UARTC_SCR                           0x0040699c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_usb1_ctrl.h b/include/linux/brcmstb/7346b0/bchp_usb1_ctrl.h
new file mode 100644
index 0000000..6a1e949
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_usb1_ctrl.h
@@ -0,0 +1,66 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:11:35 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_usb1_ctrl.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 6:01p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB1_CTRL_H__
+#define BCHP_USB1_CTRL_H__
+
+/***************************************************************************
+ *USB1_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB1_CTRL_SETUP                     0x00490200 /* Setup Register */
+#define BCHP_USB1_CTRL_PLL_CTL                   0x00490204 /* PLL Control Register */
+#define BCHP_USB1_CTRL_FLADJ_VALUE               0x00490208 /* Frame Adjust Value */
+#define BCHP_USB1_CTRL_EBRIDGE                   0x0049020c /* Control Register for EHCI Bridge */
+#define BCHP_USB1_CTRL_OBRIDGE                   0x00490210 /* Control Register for OHCI Bridge */
+#define BCHP_USB1_CTRL_MDIO                      0x00490214 /* MDIO Interface Programming Register */
+#define BCHP_USB1_CTRL_MDIO2                     0x00490218 /* MDIO Interface Read Register */
+#define BCHP_USB1_CTRL_TEST_PORT_CTL             0x0049021c /* Test Port Control Register */
+#define BCHP_USB1_CTRL_USB_SIMCTL                0x00490220 /* Simulation Register */
+#define BCHP_USB1_CTRL_USB_TESTCTL               0x00490224 /* Throutput Test Control */
+#define BCHP_USB1_CTRL_USB_TESTMON               0x00490228 /* Throughput Test Monitor */
+#define BCHP_USB1_CTRL_UTMI_CTL_1                0x0049022c /* UTMI Control Register */
+#define BCHP_USB1_CTRL_UTMI_CTL_2                0x00490230 /* UTMI Control 2 Register */
+#define BCHP_USB1_CTRL_SPARE1                    0x00490234 /* Spare1 Register for future use */
+#define BCHP_USB1_CTRL_SPARE2                    0x00490238 /* Spare2 Register for future use */
+
+#endif /* #ifndef BCHP_USB1_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_usb_ctrl.h b/include/linux/brcmstb/7346b0/bchp_usb_ctrl.h
new file mode 100644
index 0000000..f214143
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_usb_ctrl.h
@@ -0,0 +1,675 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:30:07 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_usb_ctrl.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 5:58p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB_CTRL_H__
+#define BCHP_USB_CTRL_H__
+
+/***************************************************************************
+ *USB_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB_CTRL_SETUP                      0x00480200 /* Setup Register */
+#define BCHP_USB_CTRL_PLL_CTL                    0x00480204 /* PLL Control Register */
+#define BCHP_USB_CTRL_FLADJ_VALUE                0x00480208 /* Frame Adjust Value */
+#define BCHP_USB_CTRL_EBRIDGE                    0x0048020c /* Control Register for EHCI Bridge */
+#define BCHP_USB_CTRL_OBRIDGE                    0x00480210 /* Control Register for OHCI Bridge */
+#define BCHP_USB_CTRL_MDIO                       0x00480214 /* MDIO Interface Programming Register */
+#define BCHP_USB_CTRL_MDIO2                      0x00480218 /* MDIO Interface Read Register */
+#define BCHP_USB_CTRL_TEST_PORT_CTL              0x0048021c /* Test Port Control Register */
+#define BCHP_USB_CTRL_USB_SIMCTL                 0x00480220 /* Simulation Register */
+#define BCHP_USB_CTRL_USB_TESTCTL                0x00480224 /* Throutput Test Control */
+#define BCHP_USB_CTRL_USB_TESTMON                0x00480228 /* Throughput Test Monitor */
+#define BCHP_USB_CTRL_UTMI_CTL_1                 0x0048022c /* UTMI Control Register */
+#define BCHP_USB_CTRL_UTMI_CTL_2                 0x00480230 /* UTMI Control 2 Register */
+#define BCHP_USB_CTRL_SPARE1                     0x00480234 /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE2                     0x00480238 /* Spare2 Register for future use */
+
+/***************************************************************************
+ *SETUP - Setup Register
+ ***************************************************************************/
+/* USB_CTRL :: SETUP :: OC_DISABLE [31:28] */
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK                        0xf0000000
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT                       28
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT                     0
+
+/* USB_CTRL :: SETUP :: SRAM_CS_DIS [27:25] */
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_MASK                       0x0e000000
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_SHIFT                      25
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: SETUP_SPARE [24:15] */
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK                       0x01ff8000
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT                      15
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: scb_client_swap [14:14] */
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_MASK                   0x00004000
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_SHIFT                  14
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_DEFAULT                0
+
+/* USB_CTRL :: SETUP :: scb1_en [13:13] */
+#define BCHP_USB_CTRL_SETUP_scb1_en_MASK                           0x00002000
+#define BCHP_USB_CTRL_SETUP_scb1_en_SHIFT                          13
+#define BCHP_USB_CTRL_SETUP_scb1_en_DEFAULT                        0
+
+/* USB_CTRL :: SETUP :: async_expire_dis [12:12] */
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK                  0x00001000
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT                 12
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT               0
+
+/* USB_CTRL :: SETUP :: discon_intr_en [11:11] */
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_MASK                    0x00000800
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_SHIFT                   11
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_DEFAULT                 0
+
+/* USB_CTRL :: SETUP :: con_intr_en [10:10] */
+#define BCHP_USB_CTRL_SETUP_con_intr_en_MASK                       0x00000400
+#define BCHP_USB_CTRL_SETUP_con_intr_en_SHIFT                      10
+#define BCHP_USB_CTRL_SETUP_con_intr_en_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: soft_shutdown [09:09] */
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_MASK                     0x00000200
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_SHIFT                    9
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_DEFAULT                  0
+
+/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK                    0x00000100
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT                   8
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT                 0
+
+/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK                       0x00000080
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT                      7
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: soft_reset [06:06] */
+#define BCHP_USB_CTRL_SETUP_soft_reset_MASK                        0x00000040
+#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT                       6
+#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT                     0
+
+/* USB_CTRL :: SETUP :: IPP [05:05] */
+#define BCHP_USB_CTRL_SETUP_IPP_MASK                               0x00000020
+#define BCHP_USB_CTRL_SETUP_IPP_SHIFT                              5
+#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT                            0
+
+/* USB_CTRL :: SETUP :: IOC [04:04] */
+#define BCHP_USB_CTRL_SETUP_IOC_MASK                               0x00000010
+#define BCHP_USB_CTRL_SETUP_IOC_SHIFT                              4
+#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT                            0
+
+/* USB_CTRL :: SETUP :: WABO [03:03] */
+#define BCHP_USB_CTRL_SETUP_WABO_MASK                              0x00000008
+#define BCHP_USB_CTRL_SETUP_WABO_SHIFT                             3
+#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: FNBO [02:02] */
+#define BCHP_USB_CTRL_SETUP_FNBO_MASK                              0x00000004
+#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT                             2
+#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: FNHW [01:01] */
+#define BCHP_USB_CTRL_SETUP_FNHW_MASK                              0x00000002
+#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT                             1
+#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: BABO [00:00] */
+#define BCHP_USB_CTRL_SETUP_BABO_MASK                              0x00000001
+#define BCHP_USB_CTRL_SETUP_BABO_SHIFT                             0
+#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT                           0
+
+/***************************************************************************
+ *PLL_CTL - PLL Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK                  0x80000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT                 31
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT               0
+
+/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK                      0x40000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT                     30
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                   1
+
+/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK                      0x20000000
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                     29
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                   0
+
+/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                     0x10000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                    28
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                  1
+
+/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                  0x08000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                 27
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT               0
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK                          0x07000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT                         24
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT                       3
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                   0x00800000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                  23
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK                          0x00700000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT                         20
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT                       3
+
+/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK                          0x000f0000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT                         16
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT                       10
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE2 [15:15] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_MASK                   0x00008000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_SHIFT                  15
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_pdiv [14:12] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK                        0x00007000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT                       12
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                     1
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                   0x00000c00
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                  10
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK                        0x000003ff
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT                       0
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                     40
+
+/***************************************************************************
+ *FLADJ_VALUE - Frame Adjust Value
+ ***************************************************************************/
+/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                   0xffffffff
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                  0
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT                786464
+
+/***************************************************************************
+ *EBRIDGE - Control Register for EHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT               0
+
+/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT                  0
+
+/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT           0
+
+/* USB_CTRL :: EBRIDGE :: ebr_size_sel [28:28] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_DEFAULT                 0
+
+/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT                2
+
+/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                 4
+
+/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT                     0
+
+/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                   0
+
+/***************************************************************************
+ *OBRIDGE - Control Register for OHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT               0
+
+/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT                  0
+
+/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT           0
+
+/* USB_CTRL :: OBRIDGE :: obr_size_sel [28:28] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_DEFAULT                 0
+
+/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT                2
+
+/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                 4
+
+/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT                     0
+
+/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                   0
+
+/***************************************************************************
+ *MDIO - MDIO Interface Programming Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO :: MDIO_CLK_SEL [31:31] */
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_MASK                       0x80000000
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_SHIFT                      31
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_DEFAULT                    0
+
+/* USB_CTRL :: MDIO :: MDIO_XVER_SELECT [30:29] */
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_MASK                   0x60000000
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_SHIFT                  29
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_DEFAULT                0
+
+/* USB_CTRL :: MDIO :: MDIO_TERM_SELECT [28:28] */
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_MASK                   0x10000000
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_SHIFT                  28
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_DEFAULT                0
+
+/* USB_CTRL :: MDIO :: MDIO_FS_XVER_OWN [27:27] */
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_MASK                   0x08000000
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_SHIFT                  27
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_DEFAULT                0
+
+/* USB_CTRL :: MDIO :: MDIO_TESTMODE [26:26] */
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_MASK                      0x04000000
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_SHIFT                     26
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_DEFAULT                   0
+
+/* USB_CTRL :: MDIO :: WR_START [25:25] */
+#define BCHP_USB_CTRL_MDIO_WR_START_MASK                           0x02000000
+#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT                          25
+#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT                        0
+
+/* USB_CTRL :: MDIO :: RD_START [24:24] */
+#define BCHP_USB_CTRL_MDIO_RD_START_MASK                           0x01000000
+#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT                          24
+#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT                        0
+
+/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK                          0x00ff0000
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT                         16
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT                       0
+
+/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK                          0x0000ffff
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT                         0
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT                       0
+
+/***************************************************************************
+ *MDIO2 - MDIO Interface Read Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO2 :: SYNOPSIS_CORE_ID [31:16] */
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_MASK                  0xffff0000
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_SHIFT                 16
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_DEFAULT               9994
+
+/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK                      0x0000ffff
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                     0
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                   0
+
+/***************************************************************************
+ *TEST_PORT_CTL - Test Port Control Register
+ ***************************************************************************/
+/* USB_CTRL :: TEST_PORT_CTL :: TP_EN [31:31] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_MASK                     0x80000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_SHIFT                    31
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_DEFAULT                  0
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [30:26] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK               0x7c000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT              26
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT            0
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb0_wr_data_sel [25:25] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_MASK          0x02000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_SHIFT         25
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_DEFAULT       0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [24:24] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK                0x01000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT               24
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT             0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt2_oe [23:23] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_MASK                0x00800000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_SHIFT               23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_DEFAULT             0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron1_tstsel [22:22] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_MASK             0x00400000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_SHIFT            22
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron2_tstsel [21:21] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_MASK             0x00200000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_SHIFT            21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: test_clksel [20:19] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_MASK               0x00180000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_SHIFT              19
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_DEFAULT            0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_tstsel [18:16] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_MASK             0x00070000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_SHIFT            16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: UTMI_TEST_SEL [15:08] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_MASK             0x0000ff00
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_SHIFT            8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                 0x000000ff
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT                0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT              0
+
+/***************************************************************************
+ *USB_SIMCTL - Simulation Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK                  0x80000000
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                 31
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT               0
+
+/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK                0x40000000
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT               30
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT             0
+
+/* USB_CTRL :: USB_SIMCTL :: otg_scale_down_en [29:28] */
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_MASK            0x30000000
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_SHIFT           28
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_DEFAULT         0
+
+/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK                    0x08000000
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT                   27
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT                 0
+
+/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK        0x04000000
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT       26
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT     0
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:00] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                 0x03ffffff
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT                0
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT              0
+
+/***************************************************************************
+ *USB_TESTCTL - Throutput Test Control
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:23] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK              0xff800000
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT             23
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT           0
+
+/* USB_CTRL :: USB_TESTCTL :: CTRLLER_SEL [22:21] */
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_MASK                 0x00600000
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_SHIFT                21
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_DEFAULT              0
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK                     0x00100000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                    20
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                  0
+
+/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK                   0x00080000
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                  19
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT                0
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK                    0x00070000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                   16
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                 0
+
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK              0x0000fc00
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT             10
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT           0
+
+/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK              0x000003ff
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT             0
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT           0
+
+/***************************************************************************
+ *USB_TESTMON - Throughput Test Monitor
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [31:00] */
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK                0xffffffff
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT               0
+
+/***************************************************************************
+ *UTMI_CTL_1 - UTMI Control Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB_P1 [31:31] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_MASK              0x80000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_SHIFT             31
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK             0x70000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT            28
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT          0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK_P1 [27:27] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_MASK                0x08000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_SHIFT               27
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE3 [26:25] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_MASK              0x06000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_SHIFT             25
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY_P1 [24:24] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_MASK                0x01000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_SHIFT               24
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK                0x00800000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT               23
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK                0x00400000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT               22
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK                0x00200000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT               21
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK                0x00100000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT               20
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                  0x000c0000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                 18
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT               0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT       1
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK           0x00010000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT          16
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT        0
+
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB [15:15] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_MASK                 0x00008000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_SHIFT                15
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_DEFAULT              0
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK                0x00007000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT               12
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK [11:11] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_MASK                   0x00000800
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_SHIFT                  11
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE1 [10:09] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_MASK              0x00000600
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_SHIFT             9
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY [08:08] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_MASK                   0x00000100
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_SHIFT                  8
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                   0x00000080
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                  7
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                   0x00000040
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                  6
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                   0x00000020
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                  5
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                   0x00000010
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                  4
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK                     0x0000000c
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                    2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                  0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT          1
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK              0x00000001
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT             0
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT           0
+
+/***************************************************************************
+ *UTMI_CTL_2 - UTMI Control 2 Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK               0xffffffff
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT              0
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT            0
+
+/***************************************************************************
+ *SPARE1 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE1 :: SPARE1_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_DEFAULT                   0
+
+/***************************************************************************
+ *SPARE2 - Spare2 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE2 :: SPARE2_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_DEFAULT                   0
+
+#endif /* #ifndef BCHP_USB_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_wktmr.h b/include/linux/brcmstb/7346b0/bchp_wktmr.h
new file mode 100644
index 0000000..d54f903
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_wktmr.h
@@ -0,0 +1,108 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:12:06 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_wktmr.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 6:12p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_WKTMR_H__
+#define BCHP_WKTMR_H__
+
+/***************************************************************************
+ *WKTMR - Wakeup timer
+ ***************************************************************************/
+#define BCHP_WKTMR_EVENT                         0x00408e80 /* Wakeup Timer Register */
+#define BCHP_WKTMR_COUNTER                       0x00408e84 /* Wakeup Counter */
+#define BCHP_WKTMR_ALARM                         0x00408e88 /* Wakeup Timer Alarm */
+#define BCHP_WKTMR_PRESCALER                     0x00408e8c /* Wakeup Timer Prescaler */
+#define BCHP_WKTMR_PRESCALER_VAL                 0x00408e90 /* Wakeup Timer Prescaler Value */
+
+/***************************************************************************
+ *EVENT - Wakeup Timer Register
+ ***************************************************************************/
+/* WKTMR :: EVENT :: reserved0 [31:01] */
+#define BCHP_WKTMR_EVENT_reserved0_MASK                            0xfffffffe
+#define BCHP_WKTMR_EVENT_reserved0_SHIFT                           1
+
+/* WKTMR :: EVENT :: wktmr_alarm_event [00:00] */
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_MASK                    0x00000001
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_SHIFT                   0
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_DEFAULT                 0
+
+/***************************************************************************
+ *COUNTER - Wakeup Counter
+ ***************************************************************************/
+/* WKTMR :: COUNTER :: wktmr_counter [31:00] */
+#define BCHP_WKTMR_COUNTER_wktmr_counter_MASK                      0xffffffff
+#define BCHP_WKTMR_COUNTER_wktmr_counter_SHIFT                     0
+#define BCHP_WKTMR_COUNTER_wktmr_counter_DEFAULT                   0
+
+/***************************************************************************
+ *ALARM - Wakeup Timer Alarm
+ ***************************************************************************/
+/* WKTMR :: ALARM :: wktmr_alarm [31:00] */
+#define BCHP_WKTMR_ALARM_wktmr_alarm_MASK                          0xffffffff
+#define BCHP_WKTMR_ALARM_wktmr_alarm_SHIFT                         0
+#define BCHP_WKTMR_ALARM_wktmr_alarm_DEFAULT                       0
+
+/***************************************************************************
+ *PRESCALER - Wakeup Timer Prescaler
+ ***************************************************************************/
+/* WKTMR :: PRESCALER :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_reserved0_MASK                        0xfe000000
+#define BCHP_WKTMR_PRESCALER_reserved0_SHIFT                       25
+
+/* WKTMR :: PRESCALER :: wktmr_prescaler [24:00] */
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_MASK                  0x01ffffff
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_SHIFT                 0
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_DEFAULT               27000000
+
+/***************************************************************************
+ *PRESCALER_VAL - Wakeup Timer Prescaler Value
+ ***************************************************************************/
+/* WKTMR :: PRESCALER_VAL :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_MASK                    0xfe000000
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_SHIFT                   25
+
+/* WKTMR :: PRESCALER_VAL :: wktmr_prescaler_val [24:00] */
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_MASK          0x01ffffff
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_SHIFT         0
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_DEFAULT       0
+
+#endif /* #ifndef BCHP_WKTMR_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/brcmirq.h b/include/linux/brcmstb/7346b0/brcmirq.h
new file mode 100644
index 0000000..ef2f3cb
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/brcmirq.h
@@ -0,0 +1,48 @@
+/*
+ * 7346b0 IRQ header file autogenerated by update_bchp.pl
+ * DO NOT EDIT THIS FILE BY HAND.
+ *
+ * Copyright (C) 2011 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BRCMIRQ_H_
+#define _BRCMIRQ_H_
+
+#define BRCM_IRQ_EHCI0_0	69
+#define BRCM_IRQ_EHCI0_1	70
+#define BRCM_IRQ_EHCI1_0	74
+#define BRCM_IRQ_EHCI1_1	75
+#define BRCM_IRQ_GENET_0_A	25
+#define BRCM_IRQ_GENET_0_B	26
+#define BRCM_IRQ_GENET_1_A	27
+#define BRCM_IRQ_GENET_1_B	28
+#define BRCM_IRQ_HIF		31
+#define BRCM_IRQ_HIF_SPI	32
+#define BRCM_IRQ_MOCA		36
+#define BRCM_IRQ_OHCI0_0	71
+#define BRCM_IRQ_OHCI0_1	72
+#define BRCM_IRQ_OHCI1_0	76
+#define BRCM_IRQ_OHCI1_1	77
+#define BRCM_IRQ_SATA		41
+#define BRCM_IRQ_SDIO0		86
+#define BRCM_IRQ_STANDBY	54
+#define BRCM_IRQ_UARTA		65
+#define BRCM_IRQ_UARTB		66
+#define BRCM_IRQ_UARTC		67
+#define BRCM_IRQLIST_EHCI	{ 69, 70, 74, 75 }
+#define BRCM_IRQLIST_OHCI	{ 71, 72, 76, 77 }
+
+#endif /* _BRCMIRQ_H_ */
diff --git a/include/linux/brcmstb/7358a0/bchp_aon_ctrl.h b/include/linux/brcmstb/7358a0/bchp_aon_ctrl.h
new file mode 100644
index 0000000..4b53fb3
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_aon_ctrl.h
@@ -0,0 +1,1970 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:48:56 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_aon_ctrl.h $
+ * 
+ * Hydra_Software_Devel/4   9/20/11 11:28a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_CTRL_H__
+#define BCHP_AON_CTRL_H__
+
+/***************************************************************************
+ *AON_CTRL - AON Control Registers
+ ***************************************************************************/
+#define BCHP_AON_CTRL_RESET_CTRL                 0x00408000 /* Reset Control register for AON */
+#define BCHP_AON_CTRL_PM_CTRL                    0x00408004 /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_STATUS                  0x00408008 /* Status register for Power Controller */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS        0x0040800c /* Power Management IRQ input status */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT         0x00408010 /* Power Management Wait counter in place of Wait for MIPS IRQ */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER        0x00408014 /* Deep Standby Assertion Timer */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER         0x00408018 /* Deep Standby Wakeup Timer */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE    0x0040801c /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_LED_CTRL                0x00408020 /* LED set control register */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES     0x00408024 /* LED set control register */
+#define BCHP_AON_CTRL_HASH_VALUE_0               0x00408030 /* DRAM Hash Value */
+#define BCHP_AON_CTRL_HASH_VALUE_1               0x00408034 /* DRAM Hash Value */
+#define BCHP_AON_CTRL_HASH_VALUE_2               0x00408038 /* DRAM Hash Value */
+#define BCHP_AON_CTRL_HASH_VALUE_3               0x0040803c /* DRAM Hash Value */
+#define BCHP_AON_CTRL_HASH_VALUE_4               0x00408040 /* DRAM Hash Value */
+#define BCHP_AON_CTRL_HASH_VALUE_5               0x00408044 /* DRAM Hash Value */
+#define BCHP_AON_CTRL_HASH_VALUE_6               0x00408048 /* DRAM Hash Value */
+#define BCHP_AON_CTRL_HASH_VALUE_7               0x0040804c /* DRAM Hash Value */
+#define BCHP_AON_CTRL_DRAM_START_0               0x00408050 /* DRAM Start Address 0 */
+#define BCHP_AON_CTRL_DRAM_END_0                 0x00408054 /* DRAM End Address 0 */
+#define BCHP_AON_CTRL_DRAM_START_1               0x00408058 /* DRAM Start Address 1 */
+#define BCHP_AON_CTRL_DRAM_END_1                 0x0040805c /* DRAM End Address 1 */
+#define BCHP_AON_CTRL_DRAM_START_2               0x00408060 /* DRAM Start Address 2 */
+#define BCHP_AON_CTRL_DRAM_END_2                 0x00408064 /* DRAM End Address 2 */
+#define BCHP_AON_CTRL_DRAM_START_3               0x00408068 /* DRAM Start Address 3 */
+#define BCHP_AON_CTRL_DRAM_END_3                 0x0040806c /* DRAM End Address 3 */
+#define BCHP_AON_CTRL_DRAM_START_4               0x00408070 /* DRAM Start Address 4 */
+#define BCHP_AON_CTRL_DRAM_END_4                 0x00408074 /* DRAM End Address 4 */
+#define BCHP_AON_CTRL_DRAM_START_5               0x00408078 /* DRAM Start Address 5 */
+#define BCHP_AON_CTRL_DRAM_END_5                 0x0040807c /* DRAM End Address 5 */
+#define BCHP_AON_CTRL_DRAM_START_6               0x00408080 /* DRAM Start Address 6 */
+#define BCHP_AON_CTRL_DRAM_END_6                 0x00408084 /* DRAM End Address 6 */
+#define BCHP_AON_CTRL_DRAM_START_7               0x00408088 /* DRAM Start Address 7 */
+#define BCHP_AON_CTRL_DRAM_END_7                 0x0040808c /* DRAM End Address 7 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_00             0x00408090 /* System Data 00 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_01             0x00408094 /* System Data 01 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_02             0x00408098 /* System Data 02 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_03             0x0040809c /* System Data 03 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_04             0x004080a0 /* System Data 04 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_05             0x004080a4 /* System Data 05 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_06             0x004080a8 /* System Data 06 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_07             0x004080ac /* System Data 07 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_08             0x004080b0 /* System Data 08 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_09             0x004080b4 /* System Data 09 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_10             0x004080b8 /* System Data 10 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_11             0x004080bc /* System Data 11 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_12             0x004080c0 /* System Data 12 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_13             0x004080c4 /* System Data 13 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_14             0x004080c8 /* System Data 14 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_15             0x004080cc /* System Data 15 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_16             0x004080d0 /* System Data 16 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_17             0x004080d4 /* System Data 17 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_18             0x004080d8 /* System Data 18 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_19             0x004080dc /* System Data 19 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_20             0x004080e0 /* System Data 20 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_21             0x004080e4 /* System Data 21 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_22             0x004080e8 /* System Data 22 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_23             0x004080ec /* System Data 23 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_24             0x004080f0 /* System Data 24 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_25             0x004080f4 /* System Data 25 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_26             0x004080f8 /* System Data 26 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_27             0x004080fc /* System Data 27 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_28             0x00408100 /* System Data 28 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_29             0x00408104 /* System Data 29 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_30             0x00408108 /* System Data 30 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_31             0x0040810c /* System Data 31 */
+#define BCHP_AON_CTRL_HLCD_CTRL                  0x00408120 /* HW LED Clock Driver Control */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER    0x00408124 /* Second Fraction Counter Initial value */
+#define BCHP_AON_CTRL_TIME_COUNTER               0x00408128 /* Hour/Minute Counter Initial value */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0           0x00408130 /* Digit Code for digit 0, 1, 2, 3 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1           0x00408134 /* Digit Code for digit 4, 5, 6, 7 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2           0x00408138 /* Digit Code for digit 8, 9 */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET      0x0040813c /* Hour MSD/LSD and minute MSD/LSD address offset */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL            0x00408140 /* LED status control */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0             0x00408150 /* General control register 0 */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0           0x00408154 /* General status register 0 */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0     0x00408158 /* General control register without scan 0 */
+#define BCHP_AON_CTRL_SPARE_CTRL_0               0x00408180 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_SPARE_CTRL_1               0x00408184 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH          0x00408190 /* Scratch register */
+#define BCHP_AON_CTRL_RESET_HISTORY              0x00408194 /* Reset History Register For AON */
+#define BCHP_AON_CTRL_NMI_CTRL                   0x00408198 /* Control register for NMI */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL           0x004081a0 /* Ana xtal low cur 40g m7fc gisb control */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL         0x004081b0 /* Test_mode control register */
+#define BCHP_AON_CTRL_SUB_TEST_MODE              0x004081b4 /* Register source for sub_test_mode */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE          0x004081b8 /* Final latched testmode value */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE      0x004081bc /* Final latched sub-testmode value */
+
+/***************************************************************************
+ *RESET_CTRL - Reset Control register for AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_CTRL :: reserved0 [31:04] */
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_MASK                    0xfffffff0
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_SHIFT                   4
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [03:03] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000008
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 3
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_DEFAULT 0
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable [02:02] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_MASK     0x00000004
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT    2
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_DEFAULT  0
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_polarity [01:01] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK   0x00000002
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT  1
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_DEFAULT 0
+
+/* AON_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_MASK          0x00000001
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_SHIFT         0
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_DEFAULT       0
+
+/***************************************************************************
+ *PM_CTRL - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_CTRL :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_MASK                       0xffffff00
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_SHIFT                      8
+
+/* AON_CTRL :: PM_CTRL :: min_s3_width_timer_bypass [07:07] */
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_MASK       0x00000080
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_SHIFT      7
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_DEFAULT    0
+
+/* AON_CTRL :: PM_CTRL :: pm_fast_power_down [06:06] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_MASK              0x00000040
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_SHIFT             6
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_DEFAULT           0
+
+/* AON_CTRL :: PM_CTRL :: pm_warm_boot [05:05] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_MASK                    0x00000020
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_SHIFT                   5
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_DEFAULT                 0
+
+/* AON_CTRL :: PM_CTRL :: pm_deep_standby [04:04] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_MASK                 0x00000010
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_SHIFT                4
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_DEFAULT              0
+
+/* AON_CTRL :: PM_CTRL :: pm_clk_divider_reset_en [03:03] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK         0x00000008
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_SHIFT        3
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_DEFAULT      1
+
+/* AON_CTRL :: PM_CTRL :: pm_use_mips_ready_ctrl [02:02] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_MASK          0x00000004
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_SHIFT         2
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_DEFAULT       0
+
+/* AON_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK             0x00000002
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT            1
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_DEFAULT          0
+
+/* AON_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_MASK                  0x00000001
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT                 0
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_DEFAULT               0
+
+/***************************************************************************
+ *PM_STATUS - Status register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_STATUS :: pm_wait_count_upper_bits [31:26] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_MASK      0xfc000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_SHIFT     26
+
+/* AON_CTRL :: PM_STATUS :: pm_wait_counter_active [25:25] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_MASK        0x02000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_SHIFT       25
+
+/* AON_CTRL :: PM_STATUS :: pm_s3_wakeup_reset_ [24:24] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__MASK           0x01000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__SHIFT          24
+
+/* AON_CTRL :: PM_STATUS :: pm_boundary_scan_request [23:23] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_MASK      0x00800000
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_SHIFT     23
+
+/* AON_CTRL :: PM_STATUS :: pm_fast_pd_precharge_valid [22:22] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_MASK    0x00400000
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_SHIFT   22
+
+/* AON_CTRL :: PM_STATUS :: pm_led_out [21:21] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_MASK                    0x00200000
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_SHIFT                   21
+
+/* AON_CTRL :: PM_STATUS :: pm_standby_b [20:20] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_MASK                  0x00100000
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_SHIFT                 20
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs_ng [19:19] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_MASK           0x00080000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_SHIFT          19
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs [18:18] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_MASK              0x00040000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_SHIFT             18
+
+/* AON_CTRL :: PM_STATUS :: pm_rst_clock_div [17:17] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_MASK              0x00020000
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_SHIFT             17
+
+/* AON_CTRL :: PM_STATUS :: pm_pwrdn_pll_req [16:16] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_MASK              0x00010000
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_SHIFT             16
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_xtal_clocks [15:15] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_MASK            0x00008000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_SHIFT           15
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_all_clocks [14:14] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_MASK             0x00004000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_SHIFT            14
+
+/* AON_CTRL :: PM_STATUS :: pm_dphy_standby [13:13] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_MASK               0x00002000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_SHIFT              13
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_cpu_clock [12:12] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_MASK              0x00001000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_SHIFT             12
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_avd_rptd_clock [11:11] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_MASK         0x00000800
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_SHIFT        11
+
+/* AON_CTRL :: PM_STATUS :: pm_power_ctrl_disable [10:10] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_MASK         0x00000400
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_SHIFT        10
+
+/* AON_CTRL :: PM_STATUS :: pm_pll_lock [09:09] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_MASK                   0x00000200
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_SHIFT                  9
+
+/* AON_CTRL :: PM_STATUS :: pm_dram_ready_for_pwrdn [08:08] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_MASK       0x00000100
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_SHIFT      8
+
+/* AON_CTRL :: PM_STATUS :: pm_bsp_ready_for_pwrdn [07:07] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK        0x00000080
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_SHIFT       7
+
+/* AON_CTRL :: PM_STATUS :: pm_mips_ready_for_pwrdn [06:06] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_MASK       0x00000040
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_SHIFT      6
+
+/* AON_CTRL :: PM_STATUS :: pm_sec_avd_rptd_clk_disable [05:05] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_MASK   0x00000020
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_SHIFT  5
+
+/* AON_CTRL :: PM_STATUS :: pm_state [04:00] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_MASK                      0x0000001f
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_SHIFT                     0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_ACTIVE                 0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_PWRDN_RDY              1
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_AVD_RPTD       2
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_CPU            3
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_STANDBY  4
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY                5
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY_WITH_PLLS_ON   6
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_RESET_216_108_CLKS     7
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_ACTIVE   8
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_FAST_PWRDN             9
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S1  10
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_COLD_ENTRY_S2 11
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_WARM_ENTRY_S2 12
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S3  13
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY           14
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S1   15
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S2   16
+
+/***************************************************************************
+ *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
+ ***************************************************************************/
+/* AON_CTRL :: PM_IRQ_INPUT_STATUS :: pm_irq_input_status [31:00] */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_MASK 0xffffffff
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_SHIFT 0
+
+/***************************************************************************
+ *PM_MIPS_WAIT_COUNT - Power Management Wait counter in place of Wait for MIPS IRQ
+ ***************************************************************************/
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_MASK            0xffff0000
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_SHIFT           16
+
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: counter_start_value [15:00] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_MASK  0x0000ffff
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_DEFAULT 16
+
+/***************************************************************************
+ *PM_S3_STANDBY_TIMER - Deep Standby Assertion Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_MASK           0xf8000000
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_SHIFT          27
+
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_MASK 0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_DEFAULT 540000
+
+/***************************************************************************
+ *PM_S3_WAKEUP_TIMER - Deep Standby Wakeup Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_MASK            0xf8000000
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_SHIFT           27
+
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_MASK  0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_DEFAULT 540000
+
+/***************************************************************************
+ *PM_FAST_PWRDN_PRECHARGE - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: reserved0 [31:24] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_MASK       0xff000000
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_SHIFT      24
+
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: pm_fast_power_down_precharge [23:00] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_MASK 0x00ffffff
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_SHIFT 0
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_DEFAULT 0
+
+/***************************************************************************
+ *PM_LED_CTRL - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_CTRL :: reserved0 [31:03] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_MASK                   0xfffffff8
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_SHIFT                  3
+
+/* AON_CTRL :: PM_LED_CTRL :: led_status [02:02] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_MASK                  0x00000004
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_SHIFT                 2
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_on [01:01] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_MASK                 0x00000002
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_SHIFT                1
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_off [00:00] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_MASK                0x00000001
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_SHIFT               0
+
+/***************************************************************************
+ *PM_LED_AUTO_ON_ENABLES - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_AUTO_ON_ENABLES :: led_status [31:00] */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_MASK       0xffffffff
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_SHIFT      0
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_DEFAULT    0
+
+/***************************************************************************
+ *HASH_VALUE_0 - DRAM Hash Value
+ ***************************************************************************/
+/* AON_CTRL :: HASH_VALUE_0 :: hash_value [31:00] */
+#define BCHP_AON_CTRL_HASH_VALUE_0_hash_value_MASK                 0xffffffff
+#define BCHP_AON_CTRL_HASH_VALUE_0_hash_value_SHIFT                0
+#define BCHP_AON_CTRL_HASH_VALUE_0_hash_value_DEFAULT              0
+
+/***************************************************************************
+ *HASH_VALUE_1 - DRAM Hash Value
+ ***************************************************************************/
+/* AON_CTRL :: HASH_VALUE_1 :: hash_value [31:00] */
+#define BCHP_AON_CTRL_HASH_VALUE_1_hash_value_MASK                 0xffffffff
+#define BCHP_AON_CTRL_HASH_VALUE_1_hash_value_SHIFT                0
+#define BCHP_AON_CTRL_HASH_VALUE_1_hash_value_DEFAULT              0
+
+/***************************************************************************
+ *HASH_VALUE_2 - DRAM Hash Value
+ ***************************************************************************/
+/* AON_CTRL :: HASH_VALUE_2 :: hash_value [31:00] */
+#define BCHP_AON_CTRL_HASH_VALUE_2_hash_value_MASK                 0xffffffff
+#define BCHP_AON_CTRL_HASH_VALUE_2_hash_value_SHIFT                0
+#define BCHP_AON_CTRL_HASH_VALUE_2_hash_value_DEFAULT              0
+
+/***************************************************************************
+ *HASH_VALUE_3 - DRAM Hash Value
+ ***************************************************************************/
+/* AON_CTRL :: HASH_VALUE_3 :: hash_value [31:00] */
+#define BCHP_AON_CTRL_HASH_VALUE_3_hash_value_MASK                 0xffffffff
+#define BCHP_AON_CTRL_HASH_VALUE_3_hash_value_SHIFT                0
+#define BCHP_AON_CTRL_HASH_VALUE_3_hash_value_DEFAULT              0
+
+/***************************************************************************
+ *HASH_VALUE_4 - DRAM Hash Value
+ ***************************************************************************/
+/* AON_CTRL :: HASH_VALUE_4 :: hash_value [31:00] */
+#define BCHP_AON_CTRL_HASH_VALUE_4_hash_value_MASK                 0xffffffff
+#define BCHP_AON_CTRL_HASH_VALUE_4_hash_value_SHIFT                0
+#define BCHP_AON_CTRL_HASH_VALUE_4_hash_value_DEFAULT              0
+
+/***************************************************************************
+ *HASH_VALUE_5 - DRAM Hash Value
+ ***************************************************************************/
+/* AON_CTRL :: HASH_VALUE_5 :: hash_value [31:00] */
+#define BCHP_AON_CTRL_HASH_VALUE_5_hash_value_MASK                 0xffffffff
+#define BCHP_AON_CTRL_HASH_VALUE_5_hash_value_SHIFT                0
+#define BCHP_AON_CTRL_HASH_VALUE_5_hash_value_DEFAULT              0
+
+/***************************************************************************
+ *HASH_VALUE_6 - DRAM Hash Value
+ ***************************************************************************/
+/* AON_CTRL :: HASH_VALUE_6 :: hash_value [31:00] */
+#define BCHP_AON_CTRL_HASH_VALUE_6_hash_value_MASK                 0xffffffff
+#define BCHP_AON_CTRL_HASH_VALUE_6_hash_value_SHIFT                0
+#define BCHP_AON_CTRL_HASH_VALUE_6_hash_value_DEFAULT              0
+
+/***************************************************************************
+ *HASH_VALUE_7 - DRAM Hash Value
+ ***************************************************************************/
+/* AON_CTRL :: HASH_VALUE_7 :: hash_value [31:00] */
+#define BCHP_AON_CTRL_HASH_VALUE_7_hash_value_MASK                 0xffffffff
+#define BCHP_AON_CTRL_HASH_VALUE_7_hash_value_SHIFT                0
+#define BCHP_AON_CTRL_HASH_VALUE_7_hash_value_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_START_0 - DRAM Start Address 0
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_START_0 :: dram_start [31:00] */
+#define BCHP_AON_CTRL_DRAM_START_0_dram_start_MASK                 0xffffffff
+#define BCHP_AON_CTRL_DRAM_START_0_dram_start_SHIFT                0
+#define BCHP_AON_CTRL_DRAM_START_0_dram_start_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_END_0 - DRAM End Address 0
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_END_0 :: dram_end [31:00] */
+#define BCHP_AON_CTRL_DRAM_END_0_dram_end_MASK                     0xffffffff
+#define BCHP_AON_CTRL_DRAM_END_0_dram_end_SHIFT                    0
+#define BCHP_AON_CTRL_DRAM_END_0_dram_end_DEFAULT                  0
+
+/***************************************************************************
+ *DRAM_START_1 - DRAM Start Address 1
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_START_1 :: dram_start [31:00] */
+#define BCHP_AON_CTRL_DRAM_START_1_dram_start_MASK                 0xffffffff
+#define BCHP_AON_CTRL_DRAM_START_1_dram_start_SHIFT                0
+#define BCHP_AON_CTRL_DRAM_START_1_dram_start_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_END_1 - DRAM End Address 1
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_END_1 :: dram_end [31:00] */
+#define BCHP_AON_CTRL_DRAM_END_1_dram_end_MASK                     0xffffffff
+#define BCHP_AON_CTRL_DRAM_END_1_dram_end_SHIFT                    0
+#define BCHP_AON_CTRL_DRAM_END_1_dram_end_DEFAULT                  0
+
+/***************************************************************************
+ *DRAM_START_2 - DRAM Start Address 2
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_START_2 :: dram_start [31:00] */
+#define BCHP_AON_CTRL_DRAM_START_2_dram_start_MASK                 0xffffffff
+#define BCHP_AON_CTRL_DRAM_START_2_dram_start_SHIFT                0
+#define BCHP_AON_CTRL_DRAM_START_2_dram_start_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_END_2 - DRAM End Address 2
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_END_2 :: dram_end [31:00] */
+#define BCHP_AON_CTRL_DRAM_END_2_dram_end_MASK                     0xffffffff
+#define BCHP_AON_CTRL_DRAM_END_2_dram_end_SHIFT                    0
+#define BCHP_AON_CTRL_DRAM_END_2_dram_end_DEFAULT                  0
+
+/***************************************************************************
+ *DRAM_START_3 - DRAM Start Address 3
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_START_3 :: dram_start [31:00] */
+#define BCHP_AON_CTRL_DRAM_START_3_dram_start_MASK                 0xffffffff
+#define BCHP_AON_CTRL_DRAM_START_3_dram_start_SHIFT                0
+#define BCHP_AON_CTRL_DRAM_START_3_dram_start_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_END_3 - DRAM End Address 3
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_END_3 :: dram_end [31:00] */
+#define BCHP_AON_CTRL_DRAM_END_3_dram_end_MASK                     0xffffffff
+#define BCHP_AON_CTRL_DRAM_END_3_dram_end_SHIFT                    0
+#define BCHP_AON_CTRL_DRAM_END_3_dram_end_DEFAULT                  0
+
+/***************************************************************************
+ *DRAM_START_4 - DRAM Start Address 4
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_START_4 :: dram_start [31:00] */
+#define BCHP_AON_CTRL_DRAM_START_4_dram_start_MASK                 0xffffffff
+#define BCHP_AON_CTRL_DRAM_START_4_dram_start_SHIFT                0
+#define BCHP_AON_CTRL_DRAM_START_4_dram_start_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_END_4 - DRAM End Address 4
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_END_4 :: dram_end [31:00] */
+#define BCHP_AON_CTRL_DRAM_END_4_dram_end_MASK                     0xffffffff
+#define BCHP_AON_CTRL_DRAM_END_4_dram_end_SHIFT                    0
+#define BCHP_AON_CTRL_DRAM_END_4_dram_end_DEFAULT                  0
+
+/***************************************************************************
+ *DRAM_START_5 - DRAM Start Address 5
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_START_5 :: dram_start [31:00] */
+#define BCHP_AON_CTRL_DRAM_START_5_dram_start_MASK                 0xffffffff
+#define BCHP_AON_CTRL_DRAM_START_5_dram_start_SHIFT                0
+#define BCHP_AON_CTRL_DRAM_START_5_dram_start_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_END_5 - DRAM End Address 5
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_END_5 :: dram_end [31:00] */
+#define BCHP_AON_CTRL_DRAM_END_5_dram_end_MASK                     0xffffffff
+#define BCHP_AON_CTRL_DRAM_END_5_dram_end_SHIFT                    0
+#define BCHP_AON_CTRL_DRAM_END_5_dram_end_DEFAULT                  0
+
+/***************************************************************************
+ *DRAM_START_6 - DRAM Start Address 6
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_START_6 :: dram_start [31:00] */
+#define BCHP_AON_CTRL_DRAM_START_6_dram_start_MASK                 0xffffffff
+#define BCHP_AON_CTRL_DRAM_START_6_dram_start_SHIFT                0
+#define BCHP_AON_CTRL_DRAM_START_6_dram_start_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_END_6 - DRAM End Address 6
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_END_6 :: dram_end [31:00] */
+#define BCHP_AON_CTRL_DRAM_END_6_dram_end_MASK                     0xffffffff
+#define BCHP_AON_CTRL_DRAM_END_6_dram_end_SHIFT                    0
+#define BCHP_AON_CTRL_DRAM_END_6_dram_end_DEFAULT                  0
+
+/***************************************************************************
+ *DRAM_START_7 - DRAM Start Address 7
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_START_7 :: dram_start [31:00] */
+#define BCHP_AON_CTRL_DRAM_START_7_dram_start_MASK                 0xffffffff
+#define BCHP_AON_CTRL_DRAM_START_7_dram_start_SHIFT                0
+#define BCHP_AON_CTRL_DRAM_START_7_dram_start_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_END_7 - DRAM End Address 7
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_END_7 :: dram_end [31:00] */
+#define BCHP_AON_CTRL_DRAM_END_7_dram_end_MASK                     0xffffffff
+#define BCHP_AON_CTRL_DRAM_END_7_dram_end_SHIFT                    0
+#define BCHP_AON_CTRL_DRAM_END_7_dram_end_DEFAULT                  0
+
+/***************************************************************************
+ *SYSTEM_DATA_00 - System Data 00
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_00 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_00_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_00_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_00_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_01 - System Data 01
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_01 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_01_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_01_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_01_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_02 - System Data 02
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_02 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_02_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_02_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_02_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_03 - System Data 03
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_03 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_03_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_03_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_03_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_04 - System Data 04
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_04 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_04_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_04_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_04_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_05 - System Data 05
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_05 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_05_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_05_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_05_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_06 - System Data 06
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_06 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_06_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_06_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_06_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_07 - System Data 07
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_07 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_07_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_07_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_07_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_08 - System Data 08
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_08 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_08_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_08_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_08_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_09 - System Data 09
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_09 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_09_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_09_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_09_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_10 - System Data 10
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_10 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_10_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_10_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_10_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_11 - System Data 11
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_11 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_11_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_11_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_11_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_12 - System Data 12
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_12 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_12_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_12_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_12_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_13 - System Data 13
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_13 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_13_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_13_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_13_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_14 - System Data 14
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_14 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_14_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_14_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_14_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_15 - System Data 15
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_15 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_15_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_15_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_15_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_16 - System Data 16
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_16 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_16_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_16_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_16_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_17 - System Data 17
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_17 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_17_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_17_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_17_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_18 - System Data 18
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_18 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_18_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_18_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_18_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_19 - System Data 19
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_19 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_19_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_19_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_19_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_20 - System Data 20
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_20 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_20_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_20_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_20_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_21 - System Data 21
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_21 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_21_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_21_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_21_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_22 - System Data 22
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_22 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_22_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_22_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_22_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_23 - System Data 23
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_23 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_23_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_23_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_23_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_24 - System Data 24
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_24 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_24_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_24_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_24_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_25 - System Data 25
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_25 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_25_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_25_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_25_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_26 - System Data 26
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_26 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_26_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_26_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_26_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_27 - System Data 27
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_27 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_27_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_27_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_27_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_28 - System Data 28
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_28 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_28_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_28_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_28_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_29 - System Data 29
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_29 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_29_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_29_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_29_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_30 - System Data 30
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_30 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_30_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_30_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_30_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_31 - System Data 31
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_31 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_31_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_31_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_31_system_data_DEFAULT           0
+
+/***************************************************************************
+ *HLCD_CTRL - HW LED Clock Driver Control
+ ***************************************************************************/
+/* AON_CTRL :: HLCD_CTRL :: reserved0 [31:02] */
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_MASK                     0xfffffffc
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_SHIFT                    2
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable_status [01:01] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_MASK            0x00000002
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_SHIFT           1
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable [00:00] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_MASK                   0x00000001
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_SHIFT                  0
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_DEFAULT                0
+
+/***************************************************************************
+ *SECOND_FRACTION_COUNTER - Second Fraction Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: reserved0 [31:25] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_MASK       0xfe000000
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_SHIFT      25
+
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: second_fraction_counter_init [24:00] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_MASK 0x01ffffff
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_SHIFT 0
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_DEFAULT 0
+
+/***************************************************************************
+ *TIME_COUNTER - Hour/Minute Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: TIME_COUNTER :: reserved0 [31:20] */
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_MASK                  0xfff00000
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_SHIFT                 20
+
+/* AON_CTRL :: TIME_COUNTER :: hour_display_mode [19:19] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_MASK          0x00080000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_SHIFT         19
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: mode_12h_24h_init [18:18] */
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_MASK          0x00040000
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_SHIFT         18
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: am_pm_counter_init [17:17] */
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_MASK         0x00020000
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_SHIFT        17
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_DEFAULT      0
+
+/* AON_CTRL :: TIME_COUNTER :: hour_counter_init [16:12] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_MASK          0x0001f000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_SHIFT         12
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: minute_counter_init [11:06] */
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_MASK        0x00000fc0
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_SHIFT       6
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_DEFAULT     0
+
+/* AON_CTRL :: TIME_COUNTER :: second_counter_init [05:00] */
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_MASK        0x0000003f
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_SHIFT       0
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_DEFAULT     0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_0 - Digit Code for digit 0, 1, 2, 3
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_3 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_2 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_1 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_0 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_1 - Digit Code for digit 4, 5, 6, 7
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_7 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_6 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_5 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_4 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_2 - Digit Code for digit 8, 9
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_MASK              0xffff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_SHIFT             16
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_9 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_8 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_ADDR_OFFSET - Hour MSD/LSD and minute MSD/LSD address offset
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_msd_addr_offset [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_MASK 0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_SHIFT 24
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_DEFAULT 32
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_lsd_addr_offset [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_MASK 0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_SHIFT 16
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_DEFAULT 36
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_msd_addr_offset [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_MASK 0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_SHIFT 8
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_DEFAULT 24
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_lsd_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_MASK 0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_SHIFT 0
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_DEFAULT 28
+
+/***************************************************************************
+ *LED_STATUS_CTRL - LED status control
+ ***************************************************************************/
+/* AON_CTRL :: LED_STATUS_CTRL :: reserved0 [31:28] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_MASK               0xf0000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_SHIFT              28
+
+/* AON_CTRL :: LED_STATUS_CTRL :: hlcd_state [27:25] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_MASK              0x0e000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_SHIFT             25
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_IDLE         0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_COUNT        1
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_LSD 2
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_MSD 3
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_LSD 4
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_MSD 5
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_STATUS 6
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_update_enable [24:24] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_MASK    0x01000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_SHIFT   24
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_DEFAULT 0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_mask [23:12] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_MASK             0x00fff000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_SHIFT            12
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_DEFAULT          0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_bit_offset [11:08] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_MASK       0x00000f00
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_SHIFT      8
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_DEFAULT    0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_MASK      0x000000ff
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_SHIFT     0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK         0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT        31
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK         0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT        30
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK         0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT        29
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK         0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT        28
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK         0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT        27
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK         0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT        26
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK         0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT        25
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK         0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT        24
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK         0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT        23
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK         0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT        22
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK         0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT        21
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK         0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT        20
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK         0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT        19
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK         0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT        18
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK         0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT        17
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK         0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT        16
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK         0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT        15
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK         0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT        14
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK         0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT        13
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK         0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT        12
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK         0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT        11
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK         0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT        10
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK          0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT         9
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK          0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT         8
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK          0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT         7
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK          0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT         6
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK          0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT         5
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK          0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT         4
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK          0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT         3
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK          0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT         2
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK          0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT         1
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK          0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT         0
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT       0
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_MASK              0xffffff00
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_SHIFT             8
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_MASK      0x00000080
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT     7
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_MASK      0x00000040
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT     6
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_MASK      0x00000020
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT     5
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_MASK      0x00000010
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT     4
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_MASK      0x00000008
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT     3
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_MASK      0x00000004
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT     2
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_MASK      0x00000002
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT     1
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: ejtag_ce_wakeup_event [00:00] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_MASK  0x00000001
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_MASK 0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_SHIFT 31
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_MASK 0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_SHIFT 30
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_MASK 0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_SHIFT 29
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_MASK 0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_SHIFT 28
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_MASK 0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_SHIFT 27
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_MASK 0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_SHIFT 26
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_MASK 0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_SHIFT 25
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_MASK 0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_SHIFT 24
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_MASK 0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_SHIFT 23
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_MASK 0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_SHIFT 22
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_MASK 0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_SHIFT 21
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_MASK 0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_SHIFT 20
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_MASK 0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_SHIFT 19
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_MASK 0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_SHIFT 18
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_MASK 0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_SHIFT 17
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_MASK 0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_SHIFT 16
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_MASK 0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_SHIFT 15
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_MASK 0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_SHIFT 14
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_MASK 0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_SHIFT 13
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_MASK 0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_SHIFT 12
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_MASK 0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_SHIFT 11
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_MASK 0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_SHIFT 10
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_MASK 0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_SHIFT 5
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_MASK 0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_SHIFT 4
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_MASK 0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_SHIFT 3
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_MASK 0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_SHIFT 2
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_MASK 0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_SHIFT 0
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_DEFAULT 0
+
+/***************************************************************************
+ *SPARE_CTRL_0 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_DEFAULT           0
+
+/***************************************************************************
+ *SPARE_CTRL_1 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_DEFAULT           0
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* AON_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK     0xffffffff
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT    0
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT  0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset History Register For AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_HISTORY :: reserved0 [31:19] */
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_MASK                 0xfff80000
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_SHIFT                19
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [18:18] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK    0x00040000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT   18
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [17:17] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK    0x00020000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT   17
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [16:16] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK     0x00010000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT    16
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [15:15] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK     0x00008000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT    15
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [14:14] */
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK           0x00004000
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT          14
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_DEFAULT        0
+
+/* AON_CTRL :: RESET_HISTORY :: overtemp_reset [13:13] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_MASK            0x00002000
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_SHIFT           13
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_DEFAULT         0
+
+/* AON_CTRL :: RESET_HISTORY :: overvoltage_reset [12:12] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_MASK         0x00001000
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT        12
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_DEFAULT      0
+
+/* AON_CTRL :: RESET_HISTORY :: undervoltage_reset [11:11] */
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_MASK        0x00000800
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT       11
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_DEFAULT     0
+
+/* AON_CTRL :: RESET_HISTORY :: security_dl_sw_reset [10:10] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK      0x00000400
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT     10
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_DEFAULT   0
+
+/* AON_CTRL :: RESET_HISTORY :: security_master_reset [09:09] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_MASK     0x00000200
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_SHIFT    9
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: software_master_reset [08:08] */
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_MASK     0x00000100
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_SHIFT    8
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [07:07] */
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK       0x00000080
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT      7
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_DEFAULT    0
+
+/* AON_CTRL :: RESET_HISTORY :: watchdog_timer_reset [06:06] */
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK      0x00000040
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT     6
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_DEFAULT   0
+
+/* AON_CTRL :: RESET_HISTORY :: smartcard_insert_reset [05:05] */
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK    0x00000020
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT   5
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: s3_wakeup_reset [04:04] */
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_MASK           0x00000010
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_SHIFT          4
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_DEFAULT        0
+
+/* AON_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [03:03] */
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK    0x00000008
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT   3
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: tap_in_system_reset [02:02] */
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_MASK       0x00000004
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_SHIFT      2
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_DEFAULT    0
+
+/* AON_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_MASK     0x00000002
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT    1
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_MASK            0x00000001
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_SHIFT           0
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_DEFAULT         1
+
+/***************************************************************************
+ *NMI_CTRL - Control register for NMI
+ ***************************************************************************/
+/* AON_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_MASK                0x80000000
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_SHIFT               31
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_DEFAULT             0
+
+/* AON_CTRL :: NMI_CTRL :: reserved0 [30:03] */
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_MASK                      0x7ffffff8
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_SHIFT                     3
+
+/* AON_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_MASK                0x00000004
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT               2
+
+/* AON_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_MASK            0x00000002
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT           1
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_DEFAULT         0
+
+/* AON_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_MASK                0x00000001
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT               0
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_DEFAULT             1
+
+/***************************************************************************
+ *ANA_XTAL_CONTROL - Ana xtal low cur 40g m7fc gisb control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_CONTROL :: reserved0 [31:07] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_MASK              0xffffff80
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_SHIFT             7
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_test_select_gisb_control [06:06] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_MASK 0x00000040
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_SHIFT 6
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_select_current_gisb_control [05:05] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_MASK 0x00000020
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_SHIFT 5
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_cml_sel_pd [04:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_MASK         0x00000018
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_SHIFT        3
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_DEFAULT      0
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_d2cbias_gisb_control [02:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_MASK 0x00000007
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_SHIFT 0
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_DEFAULT 4
+
+/***************************************************************************
+ *SUB_TEST_MODE_CTRL - Test_mode control register
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: reserved0 [31:01] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_MASK            0xfffffffe
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_SHIFT           1
+
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: use_sub_test_mode_reg_src [00:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_MASK 0x00000001
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_SHIFT 0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_DEFAULT 0
+
+/***************************************************************************
+ *SUB_TEST_MODE - Register source for sub_test_mode
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE :: reserved0 [31:09] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_MASK                 0xfffffe00
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_SHIFT                9
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [08:08] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK     0x00000100
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT    8
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_DEFAULT  0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [07:07] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK     0x00000080
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT    7
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_DEFAULT  0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_d2cdiff_ac [06:06] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_MASK  0x00000040
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_SHIFT 6
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [05:05] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK   0x00000020
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT  5
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_mips_in_reset [04:04] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_MASK 0x00000010
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_SHIFT 4
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [03:03] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000008
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 3
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [02:02] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000004
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 2
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK   0x00000003
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT  0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_DEFAULT 0
+
+/***************************************************************************
+ *LATCHED_TEST_MODE - Final latched testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK     0xffffffff
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT    0
+
+/***************************************************************************
+ *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0
+
+#endif /* #ifndef BCHP_AON_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_aon_pin_ctrl.h b/include/linux/brcmstb/7358a0/bchp_aon_pin_ctrl.h
new file mode 100644
index 0000000..a11f191
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_aon_pin_ctrl.h
@@ -0,0 +1,609 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:38:03 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_aon_pin_ctrl.h $
+ * 
+ * Hydra_Software_Devel/5   9/20/11 11:29a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PIN_CTRL_H__
+#define BCHP_AON_PIN_CTRL_H__
+
+/***************************************************************************
+ *AON_PIN_CTRL - AON Pinmux Control Registers
+ ***************************************************************************/
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0         0x00408300 /* Pinmux control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1         0x00408304 /* Pinmux control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2         0x00408308 /* Pinmux control register 2 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3         0x0040830c /* Pinmux control register 3 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0     0x00408310 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1     0x00408314 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0     0x00408318 /* Bypass clock unselect register 0 */
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_05 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_AON_GPIO_05   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_LD1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PKT5_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_I2S_DATA0_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SC_CLK_OUT    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MTSIF_ATS_RTS 5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SDS0_DSEC_SELVTOP 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SC1_AUX1      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_TP_IN_05      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PM_AON_GPIO_05 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_04 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_AON_GPIO_04   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_LD0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PKT5_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_I2S_CLK0_OUT  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_EXT_IRQ1      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_IR_OUT        5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SDS0_TNR_SDA  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SC1_VPP       7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_TP_IN_04      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PM_AON_GPIO_04 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_03 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_GPIO_03   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_OUT       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PWR_BUTTON    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_FP_4SEC_RESETB 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_EXT_IRQ0      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_IR_OUT        5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SDS0_TNR_SCL  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SDIO0_PRES    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_TP_IN_03      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PM_AON_GPIO_03 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_01 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AON_GPIO_01   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET_LINK     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_PWM0          2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET_ACTIVITY 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_IR_OUT        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_VEC_HSYNC     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_RMX1_VALID    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SDS0_TNR_SCL  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_TP_OUT_01     8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_00 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AON_GPIO_00   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AUD_SPDIF     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_CLK_OBSRV1    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_TP_OUT_00     3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_hdmi_htplg [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_MASK       0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_SHIFT      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_DEFAULT    0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_AON_HDMI_HTPLG 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_TP_IN_02   1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_s3_standbyb [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_MASK      0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_SHIFT     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_DEFAULT   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_AON_S3_STANDBYB 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_TP_IN_01  1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_ir_in0 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_MASK           0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_SHIFT          0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_DEFAULT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_AON_IR_IN0     0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_TP_IN_00       1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_13 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_AON_GPIO_13   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_LED_LS1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PKT2_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_I2S_DATA0_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PWM0          4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SDIO0_CLK     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_USB0_PWRFLT_1 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MTSIF0_DATA0  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_TP_OUT_05     8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PM_AON_GPIO_13 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_12 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_AON_GPIO_12   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_LS0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PKT2_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_I2S_CLK0_OUT  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_OUT       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SDIO0_PWR0    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MTSIF0_CLK    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_TP_OUT_04     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PM_AON_GPIO_12 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_11 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_GPIO_11   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_LED_LD7       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SC1_CLK       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_CODEC_MCLK    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_CLK_27    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SPI_M_SCK     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_TP_OUT_03     6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_10 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_AON_GPIO_10   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_LED_LD6       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SC1_VCC       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_CODEC_SDO     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_UART_RTS2     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SPI_M_SS0B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_TP_OUT_02     6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_09 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_AON_GPIO_09   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_LED_LD5       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SC1_RST       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_CODEC_SCLK    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_UART_TX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SPI_M_MOSI    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_FSK_RX_BYP_DATA 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MTSIF0_DATA5  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_TP_IN_09      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_PM_AON_GPIO_09 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_08 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_AON_GPIO_08   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_LED_LD4       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SC1_IO        2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_CODEC_FSYNCB  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_UART_CTS2     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SPI_M_SS1B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SDIO0_PRES    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MTSIF0_DATA1  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_TP_IN_08      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_PM_AON_GPIO_08 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_07 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_AON_GPIO_07   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_LED_LD3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SC1_PRES      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_CODEC_SDI     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_UART_RX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SPI_M_MISO    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_FSK_UART_DATA 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MTSIF0_VALID  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_TP_IN_07      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_PM_AON_GPIO_07 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_06 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_AON_GPIO_06   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_LED_LD2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PKT5_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_I2S_LR0_OUT   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SC_EXT_CLK    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_VEC_VSYNC     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SDS0_DSEC_VCTL 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SC1_AUX2      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_TP_IN_06      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PM_AON_GPIO_06 9
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_00 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_MASK         0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SHIFT        28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_AON_SGPIO_00 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_BSC_M3_SCL   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_USB0_PWRFLT_1 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_EXT_IRQ2     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SDS0_TNR_SCL 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_TP_IN_16     5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_20 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_GPIO_20   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_LED_KD3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PKT4_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_CLK_OBSRV0    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_CLK_27    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SDIO0_WPROT   5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_RO_OBSRV      6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MTSIF0_DATA7  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_TP_IN_15      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PM_AON_GPIO_20 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_19 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_AON_GPIO_19   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_LED_KD2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_PKT4_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SC1_PRES      3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SPI_M_MISO    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SDIO0_CMD     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MTSIF0_DATA6  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_TP_IN_14      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_PM_AON_GPIO_19 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_18 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_AON_GPIO_18   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_LED_KD1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PKT4_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SC1_IO        3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SPI_M_SS1B    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SDIO0_DAT3    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MTSIF_ATS_INC 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_TP_IN_13      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PM_AON_GPIO_18 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_17 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_AON_GPIO_17   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_LED_KD0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PKT3_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SC1_RST       3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SPI_M_MOSI    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SDIO0_DAT2    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PWR_BUTTON    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MTSIF0_DATA4  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_TP_IN_12      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PM_AON_GPIO_17 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_16 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_AON_GPIO_16   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_LED_LS4       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PKT3_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SC1_CLK       3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SPI_M_SCK     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SDIO0_DAT1    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MTSIF0_DATA3  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_TP_IN_11      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PM_AON_GPIO_16 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_15 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_AON_GPIO_15   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_LED_LS3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PKT3_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SC1_VCC       3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SPI_M_SS0B    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SDIO0_DAT0    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_MTSIF0_DATA2  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_TP_IN_10      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PM_AON_GPIO_15 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_14 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_AON_GPIO_14   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_LED_LS2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_PKT2_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_I2S_LR0_OUT   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SDIO0_LED     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_USB0_PWRFLT_2 5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_MTSIF0_SYNC   6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_TP_OUT_06     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_PM_AON_GPIO_14 8
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: reserved0 [31:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_MASK            0xfffffff0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_SHIFT           4
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_01 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_MASK         0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_SHIFT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_AON_SGPIO_01 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_BSC_M3_SDA   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_USB0_PWRFLT_2 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_EXT_IRQ3     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_SDS0_TNR_SDA 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_TP_IN_17     5
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_08_pad_ctrl [29:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_MASK 0x30000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_SHIFT 28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_07_pad_ctrl [27:26] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_MASK 0x0c000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_SHIFT 26
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_06_pad_ctrl [25:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_MASK 0x03000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_SHIFT 24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_05_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_04_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_03_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_01_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_00_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [13:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x00003fff
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       30
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [29:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0x30000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved1 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved1_MASK        0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved1_SHIFT       24
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_20_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_19_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_18_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_17_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_16_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_15_pad_ctrl [13:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_MASK 0x00003000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_SHIFT 12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_14_pad_ctrl [11:10] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_MASK 0x00000c00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_SHIFT 10
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_13_pad_ctrl [09:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_MASK 0x00000300
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_SHIFT 8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_12_pad_ctrl [07:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_MASK 0x000000c0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_SHIFT 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_11_pad_ctrl [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_10_pad_ctrl [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_09_pad_ctrl [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_MASK 0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_SHIFT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:02] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffffc
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       2
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_nmib [01:01] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_MASK 0x00000002
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_SHIFT 1
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_DEFAULT 0
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_reset_outb [00:00] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_MASK 0x00000001
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_SHIFT 0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_DEFAULT 0
+
+#endif /* #ifndef BCHP_AON_PIN_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_aon_pm_l2.h b/include/linux/brcmstb/7358a0/bchp_aon_pm_l2.h
new file mode 100644
index 0000000..f893dfc
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_aon_pm_l2.h
@@ -0,0 +1,1047 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:36:00 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_aon_pm_l2.h $
+ * 
+ * Hydra_Software_Devel/2   9/20/11 11:29a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PM_L2_H__
+#define BCHP_AON_PM_L2_H__
+
+/***************************************************************************
+ *AON_PM_L2 - AON Power Management L2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_AON_PM_L2_CPU_STATUS                0x00408240 /* CPU interrupt Status Register */
+#define BCHP_AON_PM_L2_CPU_SET                   0x00408244 /* CPU interrupt Set Register */
+#define BCHP_AON_PM_L2_CPU_CLEAR                 0x00408248 /* CPU interrupt Clear Register */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS           0x0040824c /* CPU interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_CPU_MASK_SET              0x00408250 /* CPU interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR            0x00408254 /* CPU interrupt Mask Clear Register */
+#define BCHP_AON_PM_L2_PCI_STATUS                0x00408258 /* PCI interrupt Status Register */
+#define BCHP_AON_PM_L2_PCI_SET                   0x0040825c /* PCI interrupt Set Register */
+#define BCHP_AON_PM_L2_PCI_CLEAR                 0x00408260 /* PCI interrupt Clear Register */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS           0x00408264 /* PCI interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_PCI_MASK_SET              0x00408268 /* PCI interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR            0x0040826c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_STATUS :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_MASK                   0xffff8000
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_SHIFT                  15
+
+/* AON_PM_L2 :: CPU_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_MASK                    0x00004000
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_SHIFT                   14
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00002000
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_SHIFT          13
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0
+
+/* AON_PM_L2 :: CPU_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_MASK                     0x00001000
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_SHIFT                    12
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_MASK                         0x00000800
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_SHIFT                        11
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_MASK                   0x00000400
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_SHIFT                  10
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_MASK                   0x00000200
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_SHIFT                  9
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_MASK                 0x00000100
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_SHIFT                8
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_DEFAULT              0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_MASK                 0x00000080
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_SHIFT                7
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_DEFAULT              0
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_MASK                    0x00000040
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_SHIFT                   6
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_DEFAULT                 0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_SET :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_MASK                      0xffff8000
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_SHIFT                     15
+
+/* AON_PM_L2 :: CPU_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_MASK                       0x00004000
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_SHIFT                      14
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_MASK              0x00002000
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_SHIFT             13
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_DEFAULT           0
+
+/* AON_PM_L2 :: CPU_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_MASK                        0x00001000
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_SHIFT                       12
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_SET_FTM_MASK                            0x00000800
+#define BCHP_AON_PM_L2_CPU_SET_FTM_SHIFT                           11
+#define BCHP_AON_PM_L2_CPU_SET_FTM_DEFAULT                         0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_MASK                      0x00000400
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_SHIFT                     10
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_MASK                      0x00000200
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_SHIFT                     9
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_MASK                    0x00000100
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_SHIFT                   8
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_MASK                    0x00000080
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_SHIFT                   7
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_MASK                       0x00000040
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_SHIFT                      6
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_DEFAULT                    0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_CLEAR :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_MASK                    0xffff8000
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_SHIFT                   15
+
+/* AON_PM_L2 :: CPU_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_MASK                     0x00004000
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_SHIFT                    14
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00002000
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           13
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0
+
+/* AON_PM_L2 :: CPU_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_MASK                      0x00001000
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT                     12
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_MASK                          0x00000800
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_SHIFT                         11
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_DEFAULT                       0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_MASK                    0x00000400
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_SHIFT                   10
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_MASK                    0x00000200
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_SHIFT                   9
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_MASK                  0x00000100
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_SHIFT                 8
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_MASK                  0x00000080
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_SHIFT                 7
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_MASK                     0x00000040
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_SHIFT                    6
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_DEFAULT                  0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_MASK              0xffff8000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT             15
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_MASK               0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_SHIFT              14
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     13
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK                0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT               12
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_MASK                    0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_SHIFT                   11
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_MASK              0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_SHIFT             10
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_MASK              0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_SHIFT             9
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_MASK            0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_SHIFT           8
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_DEFAULT         1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_MASK            0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_SHIFT           7
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_DEFAULT         1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_MASK               0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_SHIFT              6
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_DEFAULT            1
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_SET :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_MASK                 0xffff8000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_SHIFT                15
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_MASK                  0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_SHIFT                 14
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        13
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_MASK                   0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT                  12
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_MASK                       0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_SHIFT                      11
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_DEFAULT                    1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_MASK                 0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_SHIFT                10
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_MASK                 0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_SHIFT                9
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_MASK               0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_SHIFT              8
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_MASK               0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_SHIFT              7
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_MASK                  0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_SHIFT                 6
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_DEFAULT               1
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_MASK               0xffff8000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT              15
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_MASK                0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_SHIFT               14
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      13
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK                 0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT                12
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_MASK                     0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_SHIFT                    11
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_DEFAULT                  1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_MASK               0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_SHIFT              10
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_MASK               0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_SHIFT              9
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_MASK             0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_SHIFT            8
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_MASK             0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_SHIFT            7
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_MASK                0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_SHIFT               6
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_DEFAULT             1
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_STATUS :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_MASK                   0xffff8000
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_SHIFT                  15
+
+/* AON_PM_L2 :: PCI_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_MASK                    0x00004000
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_SHIFT                   14
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00002000
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_SHIFT          13
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0
+
+/* AON_PM_L2 :: PCI_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_MASK                     0x00001000
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_SHIFT                    12
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_MASK                         0x00000800
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_SHIFT                        11
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_MASK                   0x00000400
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_SHIFT                  10
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_MASK                   0x00000200
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_SHIFT                  9
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_MASK                 0x00000100
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_SHIFT                8
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_DEFAULT              0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_MASK                 0x00000080
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_SHIFT                7
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_DEFAULT              0
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_MASK                    0x00000040
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_SHIFT                   6
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_DEFAULT                 0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_SET :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_MASK                      0xffff8000
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_SHIFT                     15
+
+/* AON_PM_L2 :: PCI_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_MASK                       0x00004000
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_SHIFT                      14
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_MASK              0x00002000
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_SHIFT             13
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_DEFAULT           0
+
+/* AON_PM_L2 :: PCI_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_MASK                        0x00001000
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_SHIFT                       12
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_SET_FTM_MASK                            0x00000800
+#define BCHP_AON_PM_L2_PCI_SET_FTM_SHIFT                           11
+#define BCHP_AON_PM_L2_PCI_SET_FTM_DEFAULT                         0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_MASK                      0x00000400
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_SHIFT                     10
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_MASK                      0x00000200
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_SHIFT                     9
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_MASK                    0x00000100
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_SHIFT                   8
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_MASK                    0x00000080
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_SHIFT                   7
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_MASK                       0x00000040
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_SHIFT                      6
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_DEFAULT                    0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_CLEAR :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_MASK                    0xffff8000
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_SHIFT                   15
+
+/* AON_PM_L2 :: PCI_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_MASK                     0x00004000
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_SHIFT                    14
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00002000
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           13
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0
+
+/* AON_PM_L2 :: PCI_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_MASK                      0x00001000
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT                     12
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_MASK                          0x00000800
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_SHIFT                         11
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_DEFAULT                       0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_MASK                    0x00000400
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_SHIFT                   10
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_MASK                    0x00000200
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_SHIFT                   9
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_MASK                  0x00000100
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_SHIFT                 8
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_MASK                  0x00000080
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_SHIFT                 7
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_MASK                     0x00000040
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_SHIFT                    6
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_DEFAULT                  0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_MASK              0xffff8000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT             15
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_MASK               0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_SHIFT              14
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     13
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK                0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT               12
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_MASK                    0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_SHIFT                   11
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_MASK              0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_SHIFT             10
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_MASK              0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_SHIFT             9
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_MASK            0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_SHIFT           8
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_DEFAULT         1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_MASK            0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_SHIFT           7
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_DEFAULT         1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_MASK               0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_SHIFT              6
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_DEFAULT            1
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_SET :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_MASK                 0xffff8000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_SHIFT                15
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_MASK                  0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_SHIFT                 14
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        13
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_MASK                   0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT                  12
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_MASK                       0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_SHIFT                      11
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_DEFAULT                    1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_MASK                 0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_SHIFT                10
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_MASK                 0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_SHIFT                9
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_MASK               0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_SHIFT              8
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_MASK               0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_SHIFT              7
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_MASK                  0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_SHIFT                 6
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_DEFAULT               1
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_MASK               0xffff8000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT              15
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_MASK                0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_SHIFT               14
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      13
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK                 0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT                12
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_MASK                     0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_SHIFT                    11
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_DEFAULT                  1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_MASK               0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_SHIFT              10
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_MASK               0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_SHIFT              9
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_MASK             0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_SHIFT            8
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_MASK             0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_SHIFT            7
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_MASK                0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_SHIFT               6
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_DEFAULT             1
+
+#endif /* #ifndef BCHP_AON_PM_L2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_bspi.h b/include/linux/brcmstb/7358a0/bchp_bspi.h
new file mode 100644
index 0000000..dbd3ad7
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_bspi.h
@@ -0,0 +1,446 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:38:55 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_bspi.h $
+ * 
+ * Hydra_Software_Devel/2   9/20/11 11:38a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_H__
+#define BCHP_BSPI_H__
+
+/***************************************************************************
+ *BSPI - Public BSPI Control Registers
+ ***************************************************************************/
+#define BCHP_BSPI_REVISION_ID                    0x00413000 /* Revision ID */
+#define BCHP_BSPI_SCRATCH                        0x00413004 /* Revision ID */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL               0x00413008 /* Master/Boot SPI Control Register */
+#define BCHP_BSPI_BUSY_STATUS                    0x0041300c /* BSPI Busy Status Register */
+#define BCHP_BSPI_INTR_STATUS                    0x00413010 /* Interrupt Status Register */
+#define BCHP_BSPI_B0_STATUS                      0x00413014 /* Prefetch Buffer 0 Status Register */
+#define BCHP_BSPI_B0_CTRL                        0x00413018 /* Prefetch Buffer 0 Control Register */
+#define BCHP_BSPI_B1_STATUS                      0x0041301c /* Prefetch Buffer 1 Status Register */
+#define BCHP_BSPI_B1_CTRL                        0x00413020 /* Prefetch Buffer 1 Control Register */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL            0x00413024 /* Dual/Single Receive Mode Control Register */
+#define BCHP_BSPI_FLEX_MODE_ENABLE               0x00413028 /* Flexible Control Mode Enable Register */
+#define BCHP_BSPI_BITS_PER_CYCLE                 0x0041302c /* Bits per cycle "b-p-c" Control Register */
+#define BCHP_BSPI_BITS_PER_PHASE                 0x00413030 /* Bits per Phase "b-p-p" Control Register */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE              0x00413034 /* Command and Mode Data Register */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE     0x00413038 /* Bspi FLash upper address byte register */
+#define BCHP_BSPI_BSPI_XOR_VALUE                 0x0041303c /* BSPI FLASH XOR Value Register */
+#define BCHP_BSPI_BSPI_XOR_ENABLE                0x00413040 /* BSPI FLASH XOR Enable Register */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE           0x00413044 /* BSPI Pin  Programmed IO Mode Enable Register */
+#define BCHP_BSPI_BSPI_PIO_IODIR                 0x00413048 /* BSPI Pin  Programmed IO Mode Direction Register */
+#define BCHP_BSPI_BSPI_PIO_DATA                  0x0041304c /* BSPI Pin  Programmed IO Mode Data Register */
+
+/***************************************************************************
+ *REVISION_ID - Revision ID
+ ***************************************************************************/
+/* BSPI :: REVISION_ID :: reserved0 [31:16] */
+#define BCHP_BSPI_REVISION_ID_reserved0_MASK                       0xffff0000
+#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT                      16
+
+/* BSPI :: REVISION_ID :: MAJOR [15:08] */
+#define BCHP_BSPI_REVISION_ID_MAJOR_MASK                           0x0000ff00
+#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT                          8
+#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT                        4
+
+/* BSPI :: REVISION_ID :: MINOR [07:00] */
+#define BCHP_BSPI_REVISION_ID_MINOR_MASK                           0x000000ff
+#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT                          0
+#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT                        0
+
+/***************************************************************************
+ *SCRATCH - Revision ID
+ ***************************************************************************/
+/* BSPI :: SCRATCH :: SCRATCH [31:00] */
+#define BCHP_BSPI_SCRATCH_SCRATCH_MASK                             0xffffffff
+#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT                            0
+#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT                          0
+
+/***************************************************************************
+ *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
+ ***************************************************************************/
+/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT                 1
+
+/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK                0x00000001
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT               0
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT             0
+
+/***************************************************************************
+ *BUSY_STATUS - BSPI Busy Status Register
+ ***************************************************************************/
+/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
+#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK                       0xfffffffe
+#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT                      1
+
+/* BSPI :: BUSY_STATUS :: busy [00:00] */
+#define BCHP_BSPI_BUSY_STATUS_busy_MASK                            0x00000001
+#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT                           0
+#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT                         0
+
+/***************************************************************************
+ *INTR_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
+#define BCHP_BSPI_INTR_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT                      2
+
+/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
+#define BCHP_BSPI_INTR_STATUS_intr_1_MASK                          0x00000002
+#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT                         1
+#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT                       0
+
+/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
+#define BCHP_BSPI_INTR_STATUS_intr_0_MASK                          0x00000001
+#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT                         0
+#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT                       0
+
+/***************************************************************************
+ *B0_STATUS - Prefetch Buffer 0 Status Register
+ ***************************************************************************/
+/* BSPI :: B0_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B0_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT             0
+
+/* BSPI :: B0_STATUS :: b0_full [29:29] */
+#define BCHP_BSPI_B0_STATUS_b0_full_MASK                           0x20000000
+#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT                          29
+#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT                        0
+
+/* BSPI :: B0_STATUS :: b0_empty [28:28] */
+#define BCHP_BSPI_B0_STATUS_b0_empty_MASK                          0x10000000
+#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT                         28
+#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT                       1
+
+/* BSPI :: B0_STATUS :: b0_miss [27:27] */
+#define BCHP_BSPI_B0_STATUS_b0_miss_MASK                           0x08000000
+#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT                          27
+#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT                        0
+
+/* BSPI :: B0_STATUS :: b0_hit [26:26] */
+#define BCHP_BSPI_B0_STATUS_b0_hit_MASK                            0x04000000
+#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT                           26
+#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT                         0
+
+/* BSPI :: B0_STATUS :: b0_address [25:00] */
+#define BCHP_BSPI_B0_STATUS_b0_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT                       0
+#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT                     0
+
+/***************************************************************************
+ *B0_CTRL - Prefetch Buffer 0 Control Register
+ ***************************************************************************/
+/* BSPI :: B0_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B0_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B0_CTRL :: b0_flush [00:00] */
+#define BCHP_BSPI_B0_CTRL_b0_flush_MASK                            0x00000001
+#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT                           0
+#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT                         0
+
+/***************************************************************************
+ *B1_STATUS - Prefetch Buffer 1 Status Register
+ ***************************************************************************/
+/* BSPI :: B1_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B1_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT             0
+
+/* BSPI :: B1_STATUS :: b1_full [29:29] */
+#define BCHP_BSPI_B1_STATUS_b1_full_MASK                           0x20000000
+#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT                          29
+#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT                        0
+
+/* BSPI :: B1_STATUS :: b1_empty [28:28] */
+#define BCHP_BSPI_B1_STATUS_b1_empty_MASK                          0x10000000
+#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT                         28
+#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT                       1
+
+/* BSPI :: B1_STATUS :: b1_miss [27:27] */
+#define BCHP_BSPI_B1_STATUS_b1_miss_MASK                           0x08000000
+#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT                          27
+#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT                        0
+
+/* BSPI :: B1_STATUS :: b1_hit [26:26] */
+#define BCHP_BSPI_B1_STATUS_b1_hit_MASK                            0x04000000
+#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT                           26
+#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT                         0
+
+/* BSPI :: B1_STATUS :: b1_address [25:00] */
+#define BCHP_BSPI_B1_STATUS_b1_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT                       0
+#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT                     0
+
+/***************************************************************************
+ *B1_CTRL - Prefetch Buffer 1 Control Register
+ ***************************************************************************/
+/* BSPI :: B1_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B1_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B1_CTRL :: b1_flush [00:00] */
+#define BCHP_BSPI_B1_CTRL_b1_flush_MASK                            0x00000001
+#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT                           0
+#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT                         0
+
+/***************************************************************************
+ *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
+ ***************************************************************************/
+/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK               0xffffffe0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT              5
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK             0x00000010
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT            4
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT          0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK               0x00000008
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT              3
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT            0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK      0x00000004
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT     2
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT   0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK         0x00000002
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT        1
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT      0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK                0x00000001
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT               0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT             0
+
+/***************************************************************************
+ *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT                 1
+
+/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK      0x00000001
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT     0
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT   0
+
+/***************************************************************************
+ *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK                    0xfc000000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT                   26
+
+/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK               0x03000000
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT            0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK                    0x00fc0000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT                   18
+
+/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK              0x00030000
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK                    0x0000fc00
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT                   10
+
+/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK              0x00000300
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT             8
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK                    0x000000fc
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT                   2
+
+/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK              0x00000003
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT             0
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT           0
+
+/***************************************************************************
+ *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK                    0xfe000000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT                   25
+
+/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK               0x01000000
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT            0
+
+/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK                    0x00fe0000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT                   17
+
+/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK              0x00010000
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK                    0x0000fe00
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT                   9
+
+/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK                     0x00000100
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT                    8
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT                  0
+
+/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK                 0x000000ff
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT                0
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT              8
+
+/***************************************************************************
+ *CMD_AND_MODE_BYTE - Command and Mode Data Register
+ ***************************************************************************/
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK                 0xff000000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT                24
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK            0x00ff0000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT           16
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT         0
+
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK                 0x0000ff00
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT                8
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK             0x000000ff
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT            0
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT          11
+
+/***************************************************************************
+ *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
+ ***************************************************************************/
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0
+
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK        0x00ffffff
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT       0
+
+/***************************************************************************
+ *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK               0xfff00000
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT              20
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT            0
+
+/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK                    0x000fffff
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT                  1
+
+/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK             0x00000001
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT            0
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT          0
+
+/***************************************************************************
+ *BSPI_PIO_MODE_ENABLE - BSPI Pin  Programmed IO Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK              0xfffffffe
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT             1
+
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK          0x00000001
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT         0
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT       0
+
+/***************************************************************************
+ *BSPI_PIO_IODIR - BSPI Pin  Programmed IO Mode Direction Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK                    0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT                   3
+
+/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT              3
+
+/***************************************************************************
+ *BSPI_PIO_DATA - BSPI Pin  Programmed IO Mode Data Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK                     0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT                    3
+
+/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT              0
+
+#endif /* #ifndef BCHP_BSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_bspi_raf.h b/include/linux/brcmstb/7358a0/bchp_bspi_raf.h
new file mode 100644
index 0000000..cb96e23
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_bspi_raf.h
@@ -0,0 +1,163 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:45:43 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_bspi_raf.h $
+ * 
+ * Hydra_Software_Devel/2   9/20/11 11:38a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_RAF_H__
+#define BCHP_BSPI_RAF_H__
+
+/***************************************************************************
+ *BSPI_RAF - Public Linear Read BSPI Pipe Registers
+ ***************************************************************************/
+#define BCHP_BSPI_RAF_START_ADDR                 0x00413100 /* Physical Starting Address Location in Flash device */
+#define BCHP_BSPI_RAF_NUM_WORDS                  0x00413104 /* Number of Words to be fetched */
+#define BCHP_BSPI_RAF_CTRL                       0x00413108 /* RAF Session Control Register */
+#define BCHP_BSPI_RAF_FULLNESS                   0x0041310c /* Fullness indicator for the read ahead buffer */
+#define BCHP_BSPI_RAF_WATERMARK                  0x00413110 /* Watermark level in the read ahead buffer that triggers an interrupt */
+#define BCHP_BSPI_RAF_STATUS                     0x00413114 /* Linear Read Status Register */
+#define BCHP_BSPI_RAF_READ_DATA                  0x00413118 /* Read data from Raf-buffer */
+#define BCHP_BSPI_RAF_WORD_CNT                   0x0041311c /* Current number of words fetched from Flash */
+#define BCHP_BSPI_RAF_CURR_ADDR                  0x00413120 /* Current read address for the linear read session */
+
+/***************************************************************************
+ *START_ADDR - Physical Starting Address Location in Flash device
+ ***************************************************************************/
+/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK                   0xffffffff
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT                  0
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT                0
+
+/***************************************************************************
+ *NUM_WORDS - Number of Words to be fetched
+ ***************************************************************************/
+/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK                      0xffffffff
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT                     0
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT                   0
+
+/***************************************************************************
+ *CTRL - RAF Session Control Register
+ ***************************************************************************/
+/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT                         2
+
+/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
+#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK                              0x00000002
+#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT                             1
+#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT                           0
+
+/* BSPI_RAF :: CTRL :: START [00:00] */
+#define BCHP_BSPI_RAF_CTRL_START_MASK                              0x00000001
+#define BCHP_BSPI_RAF_CTRL_START_SHIFT                             0
+#define BCHP_BSPI_RAF_CTRL_START_DEFAULT                           0
+
+/***************************************************************************
+ *FULLNESS - Fullness indicator for the read ahead buffer
+ ***************************************************************************/
+/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK                      0xffffff80
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT                     7
+
+/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK                       0x0000007f
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT                      0
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT                    0
+
+/***************************************************************************
+ *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
+ ***************************************************************************/
+/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK                     0xfffffffc
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT                    2
+
+/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK            0x00000003
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT           0
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT         0
+
+/***************************************************************************
+ *STATUS - Linear Read Status Register
+ ***************************************************************************/
+/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
+#define BCHP_BSPI_RAF_STATUS_reserved0_MASK                        0xfffffff8
+#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT                       3
+
+/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK                        0x00000004
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT                       2
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT                     0
+
+/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK                       0x00000002
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT                      1
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT                    1
+
+/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK                     0x00000001
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT                    0
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT                  0
+
+/***************************************************************************
+ *READ_DATA - Read data from Raf-buffer
+ ***************************************************************************/
+/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
+#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK                          0xffffffff
+#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT                         0
+#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT                       0
+
+/***************************************************************************
+ *WORD_CNT - Current number of words fetched from Flash
+ ***************************************************************************/
+/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK             0xffffffff
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT            0
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *CURR_ADDR - Current read address for the linear read session
+ ***************************************************************************/
+/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK               0xffffffff
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT              0
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT            0
+
+#endif /* #ifndef BCHP_BSPI_RAF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_clkgen.h b/include/linux/brcmstb/7358a0/bchp_clkgen.h
new file mode 100644
index 0000000..bcebaef
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_clkgen.h
@@ -0,0 +1,4808 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:38:24 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_clkgen.h $
+ * 
+ * Hydra_Software_Devel/6   9/20/11 11:42a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_CLKGEN_H__
+#define BCHP_CLKGEN_H__
+
+/***************************************************************************
+ *CLKGEN - clkgen registers
+ ***************************************************************************/
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL       0x00420000 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV           0x00420004 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN          0x00420008 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS   0x0042000c /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN         0x00420010 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET         0x00420014 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x00420018 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x0042001c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS        0x00420020 /* Test Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL       0x00420024 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV           0x00420028 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN          0x0042002c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS   0x00420030 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN         0x00420034 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET         0x00420038 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x0042003c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x00420040 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS        0x00420044 /* Test Status */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 0x00420048 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 0x0042004c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 0x00420050 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 0x00420054 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL     0x00420058 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV         0x0042005c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN        0x00420060 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS 0x00420064 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC        0x00420068 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2       0x0042006c /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN       0x00420070 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x00420074 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x00420078 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS      0x0042007c /* Test Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0 0x00420080 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1 0x00420084 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2 0x00420088 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3 0x0042008c /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL           0x00420090 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV               0x00420094 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN              0x00420098 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS       0x0042009c /* Lock Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC              0x004200a0 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN             0x004200a4 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET             0x004200a8 /* Resets */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH 0x004200ac /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW 0x004200b0 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS            0x004200b4 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x004200b8 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x004200bc /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x004200c0 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x004200c4 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x004200c8 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x004200cc /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL         0x004200d0 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV             0x004200d4 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN            0x004200d8 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS     0x004200dc /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC            0x004200e0 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2           0x004200e4 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN           0x004200e8 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x004200ec /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x004200f0 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS          0x004200f4 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 0x004200f8 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 0x004200fc /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 0x00420100 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 0x00420104 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 0x00420108 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 0x0042010c /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL         0x00420110 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV             0x00420114 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN            0x00420118 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS     0x0042011c /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC            0x00420120 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN           0x00420124 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET           0x00420128 /* Resets */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH 0x0042012c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW 0x00420130 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS          0x00420134 /* Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 0x00420138 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 0x0042013c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 0x00420140 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL         0x00420144 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV             0x00420148 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC            0x0042014c /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN            0x00420150 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS     0x00420154 /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC            0x00420158 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN           0x0042015c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET           0x00420160 /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH 0x00420164 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW 0x00420168 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS          0x0042016c /* Status */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE        0x00420170 /* Avd0 top clock enable */
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE 0x00420174 /* Avd0 top memory standby enable */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK       0x00420178 /* Avd0 top observe clock */
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY 0x0042017c /* Avd0 top power switch memory */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE   0x00420180 /* Disable BCM_MIPS_TOP's clocks */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE    0x00420184 /* Bcm mips top clock enable */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE 0x00420188 /* Bcm mips top memory standby enable */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK   0x0042018c /* Bcm mips top observe clock */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY 0x00420190 /* Bcm mips top power switch memory */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT          0x00420194 /* Bcm mips top select */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE               0x00420198 /* Bvn top enable */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE 0x0042019c /* Bvn top memory standby enable */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY  0x004201a0 /* Bvn top power switch memory */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201a4 /* Cktap 108 0 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201a8 /* Cktap 108 1 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201ac /* Cktap 108 2 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201b0 /* Cktap 216 0 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK 0x004201b4 /* CKTAP CPU Adjustment System 108 Clock */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK 0x004201b8 /* CKTAP CPU Adjustment System 216 Clock */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK 0x004201bc /* CKTAP CPU Adjustment System Scb Clock */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201c0 /* Cktap scb 0 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201c4 /* Cktap scb 1 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE         0x004201c8 /* Disable CLKGEN's clocks */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL        0x004201cc /* Clock Monitor Control */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT      0x004201d0 /* Clock Monitor Max Reference Count */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER    0x004201d4 /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE       0x004201d8 /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER   0x004201dc /* Clock Monitor View Counter */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE       0x004201e0 /* Disable CORE_XPT's clocks */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE        0x004201e4 /* Core xpt clock enable */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE 0x004201e8 /* Core xpt memory standby enable */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK       0x004201ec /* Core xpt observe clock */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY 0x004201f0 /* Core xpt power switch memory */
+#define BCHP_CLKGEN_DS_TOP_OBSERVE_CLOCK         0x004201f4 /* Ds top observe clock */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE         0x004201f8 /* Disable DVP_HT's clocks */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE          0x004201fc /* Dvp ht clock enable */
+#define BCHP_CLKGEN_DVP_HT_ENABLE                0x00420200 /* Dvp ht enable */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE 0x00420204 /* Dvp ht memory standby enable */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK         0x00420208 /* Dvp ht observe clock */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY   0x0042020c /* Dvp ht power switch memory */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE         0x00420210 /* Fsk top clock enable */
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE 0x00420214 /* Fsk top memory standby enable */
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY  0x00420218 /* Fsk top power switch memory */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE 0x0042021c /* Disable GENET_TOP_RGMII_INST's clocks */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE 0x00420220 /* Genet top rgmii inst clock enable */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT 0x00420224 /* Genet top rgmii inst clock select */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A 0x00420228 /* Genet top rgmii inst memory standby enable a */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK 0x0042022c /* Genet top rgmii inst observe clock */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A 0x00420230 /* Genet top rgmii inst power switch memory a */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE       0x00420234 /* Disable GRAPHICS's clocks */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE        0x00420238 /* Graphics clock enable */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE 0x0042023c /* Graphics memory standby enable */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK       0x00420240 /* Graphics observe clock */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY 0x00420244 /* Graphics power switch memory */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE            0x00420248 /* Disable HIF's clocks */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE             0x0042024c /* Hif clock enable */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE    0x00420250 /* Hif memory standby enable */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY      0x00420254 /* Hif power switch memory */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT          0x00420258 /* Mux selects for Internal clocks */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE       0x0042025c /* Memsys 16 clock enable */
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE 0x00420260 /* Memsys 16 memory standby enable */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK      0x00420264 /* Memsys 16 observe clock */
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY 0x00420268 /* Memsys 16 power switch memory */
+#define BCHP_CLKGEN_MEMSYS_16_STATUS             0x0042026c /* Memsys 16 status */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION   0x00420270 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION   0x00420274 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION   0x00420278 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION   0x0042027c /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE            0x00420280 /* Disable PAD's clocks */
+#define BCHP_CLKGEN_PAD_MUX_SELECT               0x00420284 /* Mux selects for Pad clocks */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS  0x00420288 /* PLL_AUDIO0 Reset Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS  0x0042028c /* PLL_AUDIO1 Reset Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS      0x00420290 /* PLL_SC Reset Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS    0x00420294 /* PLL_SYS1 Reset Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS    0x00420298 /* PLL_VCXO Reset Status */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL       0x0042029c /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL       0x004202a0 /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x004202a4 /* PLL Alive in Standby Mode */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE   0x004202a8 /* Raaga dsp top clock enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE 0x004202ac /* Raaga dsp top memory standby enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK  0x004202b0 /* Raaga dsp top observe clock */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY 0x004202b4 /* Raaga dsp top power switch memory */
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE         0x004202b8 /* Rfm top clock enable */
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE 0x004202bc /* Rfm top memory standby enable */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK        0x004202c0 /* Rfm top observe clock */
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY  0x004202c4 /* Rfm top power switch memory */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE    0x004202c8 /* Sds afec top clock enable */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE 0x004202cc /* Sds afec top memory standby enable */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK   0x004202d0 /* Sds afec top observe clock */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY 0x004202d4 /* Sds afec top power switch memory */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE   0x004202d8 /* Disable SDS_RECEIVER's clocks */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE    0x004202dc /* Sds receiver clock enable */
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE 0x004202e0 /* Sds receiver memory standby enable */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK   0x004202e4 /* Sds receiver observe clock */
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY 0x004202e8 /* Sds receiver power switch memory */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE    0x004202ec /* Sds tfec top clock enable */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE 0x004202f0 /* Sds tfec top memory standby enable */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK   0x004202f4 /* Sds tfec top observe clock */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY 0x004202f8 /* Sds tfec top power switch memory */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE     0x004202fc /* Sectop inst clock enable */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE 0x00420300 /* Sectop inst memory standby enable */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK    0x00420304 /* Sectop inst observe clock */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT         0x00420308 /* Mux selects for Smartcard clocks */
+#define BCHP_CLKGEN_SPARE                        0x0042030c /* Spares */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK        0x00420310 /* Sys aon observe clock */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE       0x00420314 /* Disable SYS_CTRL's clocks */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE        0x00420318 /* Sys ctrl clock enable */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE 0x0042031c /* Sys ctrl memory standby enable */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK       0x00420320 /* Sys ctrl observe clock */
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY 0x00420324 /* Sys ctrl power switch memory */
+#define BCHP_CLKGEN_TESTPORT                     0x00420328 /* Special Testport Controls */
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE         0x0042032c /* Thd top clock enable */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP               0x00420330 /* Ts ctrl0 cktap */
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP               0x00420334 /* Ts ctrl1 cktap */
+#define BCHP_CLKGEN_TS_CTRL2_CKTAP               0x00420338 /* Ts ctrl2 cktap */
+#define BCHP_CLKGEN_TS_CTRL_CLK_MUX_SELECT       0x0042033c /* Mux selects for TS_CTRL_CLK clocks */
+#define BCHP_CLKGEN_TS_CTRL_DATA_CKTAP           0x00420340 /* Ts ctrl data cktap */
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE            0x00420344 /* Disable USB's clocks */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE             0x00420348 /* Usb clock enable */
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE    0x0042034c /* Usb memory standby enable */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK            0x00420350 /* Usb observe clock */
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY      0x00420354 /* Usb power switch memory */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE    0x00420358 /* Disable VEC_AIO_TOP's clocks */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE     0x0042035c /* Vec aio top clock enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A 0x00420360 /* Vec aio top memory standby enable a */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B 0x00420364 /* Vec aio top memory standby enable b */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK    0x00420368 /* Vec aio top observe clock */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A 0x0042036c /* Vec aio top power switch memory a */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B 0x00420370 /* Vec aio top power switch memory b */
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT                1
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT            0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT                1
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT            0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 6
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 10
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 8
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 8
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_SHIFT         0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_DEFAULT       0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_reserved0_MASK            0xffffe000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_reserved0_SHIFT           13
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_MASK                 0x00001c00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_SHIFT                10
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_DEFAULT              3
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_MASK             0x000003ff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_SHIFT            0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_DEFAULT          167
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_reserved0_MASK           0xff000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_reserved0_SHIFT          24
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 6
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK   0x000000e0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT  5
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 2
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT   2
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK    0x00000002
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT   1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_MASK         0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_reserved0_MASK           0x80000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_reserved0_SHIFT          31
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_MASK             0x60000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_SHIFT            29
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_DEFAULT          0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_MASK             0x10000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_SHIFT            28
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_DEFAULT          0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_MASK         0x08000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_SHIFT        27
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT      0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_MASK         0x07000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_SHIFT        24
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_DEFAULT      0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__MASK         0x00800000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__SHIFT        23
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__DEFAULT      0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_MASK           0x00600000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_SHIFT          21
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_DEFAULT        0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_MASK           0x00100000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_SHIFT          20
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_DEFAULT        0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_MASK            0x000c0000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_SHIFT           18
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_DEFAULT         0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_MASK          0x00020000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_SHIFT         17
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_DEFAULT       0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_MASK         0x00010000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT        16
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT      0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_MASK         0x00008000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT        15
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT      0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_MASK           0x00004000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_SHIFT          14
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_DEFAULT        0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK     0x00001ffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT    1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT  0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_SHIFT             0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_DEFAULT           0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_SHIFT         0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_DEFAULT       0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_reserved0_MASK         0xfffff000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_reserved0_SHIFT        12
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_TEST_STATUS_MASK       0x00000fff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_TEST_STATUS_SHIFT      0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT  40
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT  40
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT  8
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT  50
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SC_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_MASK                  0xffffe000
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_SHIFT                 13
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_MASK                       0x00001c00
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_SHIFT                      10
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_DEFAULT                    1
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_MASK                   0x000003ff
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_DEFAULT                64
+
+/***************************************************************************
+ *PLL_SC_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_MASK                 0xff000000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_SHIFT                24
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK         0x000000e0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT        5
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT      1
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_SHIFT              0
+
+/***************************************************************************
+ *PLL_SC_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_MASK                 0xc0000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_SHIFT                30
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_MASK                   0x30000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_SHIFT                  28
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_MASK              0x08000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_SHIFT             27
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_DEFAULT           0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_MASK                   0x04000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_SHIFT                  26
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_MASK               0x02000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_SHIFT              25
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_MASK               0x01c00000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_SHIFT              22
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__MASK               0x00200000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__SHIFT              21
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_MASK                 0x00180000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_SHIFT                19
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_MASK                 0x00040000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_SHIFT                18
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_MASK                  0x00030000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_SHIFT                 16
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_DEFAULT               0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_MASK               0x00008000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_SHIFT              15
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_MASK                 0x00004000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_SHIFT                14
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK    0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT   13
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_MASK           0x00001ffe
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_SHIFT          1
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT        0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_DEFAULT               0
+
+/***************************************************************************
+ *PLL_SC_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_SHIFT               1
+
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_SHIFT               2
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_MASK                   0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_SHIFT                  1
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_DEFAULT                0
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK  0x00400000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_MASK               0xfffff000
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_SHIFT              12
+
+/* CLKGEN :: PLL_SC_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_MASK             0x00000fff
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 6
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 12
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 8
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 12
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 96
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 54
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT                  2
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT              96
+
+/***************************************************************************
+ *PLL_SYS0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 3
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT             0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT           0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT               0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 9
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 18
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 90
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 9
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 90
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 9
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_DEFAULT                  3
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_DEFAULT              125
+
+/***************************************************************************
+ *PLL_SYS1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    1
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_MASK                 0x30000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_SHIFT           27
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_DEFAULT         0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_DEFAULT              1
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_MASK             0x02000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_SHIFT            25
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_MASK             0x01c00000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_SHIFT            22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__MASK             0x00200000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__SHIFT            21
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_SHIFT              19
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_MASK                0x00030000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_SHIFT               16
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_DEFAULT             2
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 75
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 75
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 250
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_DEFAULT                  2
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_DEFAULT              64
+
+/***************************************************************************
+ *PLL_VCXO_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_MASK               0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_SHIFT              20
+
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_MASK            0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_SHIFT           0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    1
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_MASK                 0x30000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_SHIFT                28
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_SHIFT           27
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_DEFAULT         0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_MASK             0x02000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_SHIFT            25
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_MASK             0x01c00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_SHIFT            22
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__MASK             0x00200000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__SHIFT            21
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_SHIFT              19
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_MASK                0x00030000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_SHIFT               16
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_DEFAULT             0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_SHIFT            15
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *AVD0_TOP_CLOCK_ENABLE - Avd0 top clock enable
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_reserved0_MASK           0xffffffe0
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_reserved0_SHIFT          5
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_SCB_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_CPU_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_AVD_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_ALTERNATE_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *AVD0_TOP_MEMORY_STANDBY_ENABLE - Avd0 top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: AVD0_TOP_MEMORY_STANDBY_ENABLE :: SVD_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *AVD0_TOP_OBSERVE_CLOCK - Avd0 top observe clock
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: reserved0 [31:03] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_reserved0_MASK          0xfffffff8
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_reserved0_SHIFT         3
+
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_ENABLE_OBSERVE_CLOCK [02:02] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_ENABLE_DIVIDER_OBSERVE_CLOCK [01:01] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_CONTROL_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *AVD0_TOP_POWER_SWITCH_MEMORY - Avd0 top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: AVD0_TOP_POWER_SWITCH_MEMORY :: SVD_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *BCM_MIPS_TOP_CLOCK_DISABLE - Disable BCM_MIPS_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_DISABLE :: DISABLE_MIPS_SYSTEM_216_CLOCK [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_DISABLE_MIPS_SYSTEM_216_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_DISABLE_MIPS_SYSTEM_216_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_DISABLE_MIPS_SYSTEM_216_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *BCM_MIPS_TOP_CLOCK_ENABLE - Bcm mips top clock enable
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffff0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_SHIFT      4
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_MIPS_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_MIPS_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_MIPS_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_MIPS_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE - Bcm mips top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: MIPS_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *BCM_MIPS_TOP_OBSERVE_CLOCK - Bcm mips top observe clock
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *BCM_MIPS_TOP_POWER_SWITCH_MEMORY - Bcm mips top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: MIPS_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *BCM_MIPS_TOP_SELECT - Bcm mips top select
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_SELECT :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_reserved0_SHIFT            1
+
+/* CLKGEN :: BCM_MIPS_TOP_SELECT :: MIPS_PLL_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_MIPS_PLL_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_MIPS_PLL_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_MIPS_PLL_CLOCK_SELECT_DEFAULT 0
+
+/***************************************************************************
+ *BVN_TOP_ENABLE - Bvn top enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_reserved0_MASK                  0xfffffff8
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_reserved0_SHIFT                 3
+
+/* CLKGEN :: BVN_TOP_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK       0x00000004
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT      2
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT    1
+
+/* CLKGEN :: BVN_TOP_ENABLE :: BVN_216_CLK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_MASK         0x00000002
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_SHIFT        1
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_DEFAULT      1
+
+/* CLKGEN :: BVN_TOP_ENABLE :: BVN_108_CLK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_MASK         0x00000001
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_SHIFT        0
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_DEFAULT      1
+
+/***************************************************************************
+ *BVN_TOP_MEMORY_STANDBY_ENABLE - Bvn top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: BVN_TOP_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *BVN_TOP_POWER_SWITCH_MEMORY - Bvn top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: BVN_TOP_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 0 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION [31:28] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 28
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/***************************************************************************
+ *CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 1 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:28] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 28
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: THD_108_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_THD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_THD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_THD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/***************************************************************************
+ *CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 2 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:16] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 16
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/***************************************************************************
+ *CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 216 0 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:28] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 28
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: THD_216_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_THD_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_THD_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_THD_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/***************************************************************************
+ *CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK - CKTAP CPU Adjustment System 108 Clock
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: CKTAP_UPDATE [01:01] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_MASK 0x00000002
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_SHIFT 1
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_DEFAULT 0
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: CKTAP_REG_SELECT [00:00] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_DEFAULT 0
+
+/***************************************************************************
+ *CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK - CKTAP CPU Adjustment System 216 Clock
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: CKTAP_UPDATE [01:01] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_MASK 0x00000002
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_SHIFT 1
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_DEFAULT 0
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: CKTAP_REG_SELECT [00:00] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_DEFAULT 0
+
+/***************************************************************************
+ *CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK - CKTAP CPU Adjustment System Scb Clock
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: CKTAP_UPDATE [01:01] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_MASK 0x00000002
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_SHIFT 1
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_DEFAULT 0
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: CKTAP_REG_SELECT [00:00] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_DEFAULT 0
+
+/***************************************************************************
+ *CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap scb 0 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [31:28] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 28
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/***************************************************************************
+ *CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap scb 1 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:16] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 16
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: THD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_THD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_THD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_THD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/***************************************************************************
+ *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks
+ ***************************************************************************/
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT           2
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_OSC_DIGITAL_CLOCK [01:01] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_AVS_CLOCK [00:00] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_MASK    0x00000001
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_SHIFT   0
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_CONTROL - Clock Monitor Control
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT          4
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK   0x00000008
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT  3
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK    0x00000004
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT   2
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK      0x00000002
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT     1
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT   1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 1
+
+/***************************************************************************
+ *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK  0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT         1
+
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK     0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT    0
+
+/***************************************************************************
+ *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CORE_XPT_CLOCK_DISABLE - Disable CORE_XPT's clocks
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_SHIFT         5
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_CLOCK_ENABLE - Core xpt clock enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_MASK           0xfffffff8
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_SHIFT          3
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *CORE_XPT_MEMORY_STANDBY_ENABLE - Core xpt memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_OBSERVE_CLOCK - Core xpt observe clock
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_POWER_SWITCH_MEMORY - Core xpt power switch memory
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *DS_TOP_OBSERVE_CLOCK - Ds top observe clock
+ ***************************************************************************/
+/* CLKGEN :: DS_TOP_OBSERVE_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DS_TOP_OBSERVE_CLOCK_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_DS_TOP_OBSERVE_CLOCK_reserved0_SHIFT           2
+
+/* CLKGEN :: DS_TOP_OBSERVE_CLOCK :: DSTOP_ENABLE_OBSERVE_CLOCK [01:01] */
+#define BCHP_CLKGEN_DS_TOP_OBSERVE_CLOCK_DSTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_DS_TOP_OBSERVE_CLOCK_DSTOP_ENABLE_OBSERVE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_DS_TOP_OBSERVE_CLOCK_DSTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DS_TOP_OBSERVE_CLOCK :: DSTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_DS_TOP_OBSERVE_CLOCK_DSTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DS_TOP_OBSERVE_CLOCK_DSTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DS_TOP_OBSERVE_CLOCK_DSTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_CLOCK_DISABLE - Disable DVP_HT's clocks
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_SHIFT           1
+
+/* CLKGEN :: DVP_HT_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_CLOCK_ENABLE - Dvp ht clock enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_MASK             0xfffffff0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_SHIFT            4
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_ALTERNATE_216_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_ALTERNATE_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *DVP_HT_ENABLE - Dvp ht enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_ENABLE_reserved0_SHIFT                  1
+
+/* CLKGEN :: DVP_HT_ENABLE :: DVPHT_CLK_MAX_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_MASK        0x00000001
+#define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_SHIFT       0
+#define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_DEFAULT     1
+
+/***************************************************************************
+ *DVP_HT_MEMORY_STANDBY_ENABLE - Dvp ht memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_MASK    0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT   1
+
+/* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_OBSERVE_CLOCK - Dvp ht observe clock
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_MASK            0xffffffc0
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_SHIFT           6
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_POWER_SWITCH_MEMORY - Dvp ht power switch memory
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_SHIFT     2
+
+/* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *FSK_TOP_CLOCK_ENABLE - Fsk top clock enable
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_reserved0_MASK            0xfffffff8
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_reserved0_SHIFT           3
+
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: FSK_PHY_PRIMARY_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_PHY_PRIMARY_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_PHY_PRIMARY_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_PHY_PRIMARY_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: FSK_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: FSK_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *FSK_TOP_MEMORY_STANDBY_ENABLE - Fsk top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: FSK_TOP_MEMORY_STANDBY_ENABLE :: FSK_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_FSK_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_FSK_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_FSK_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *FSK_TOP_POWER_SWITCH_MEMORY - Fsk top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: FSK_TOP_POWER_SWITCH_MEMORY :: FTM_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_CLOCK_DISABLE - Disable GENET_TOP_RGMII_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_SHIFT 4
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET_ALWAYSON_CLOCK [03:03] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [02:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [01:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_FAST_CLOCK [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_CLOCK_ENABLE - Genet top rgmii inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: reserved0 [31:09] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_SHIFT 9
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [08:08] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00000100
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 8
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_108_CLOCK_ENABLE [07:07] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_MASK 0x00000080
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_SHIFT 7
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_L2INTR_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_HFB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_GMII_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_EEE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_CLK_250_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_CLOCK_SELECT - Genet top rgmii inst clock select
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_reserved0_SHIFT 2
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET0_GMII_CLOCK_SELECT [01:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_MASK 0x00000002
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_SHIFT 1
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_DEFAULT 0
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET0_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_DEFAULT 0
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A - Genet top rgmii inst memory standby enable a
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: GENET0_MEMORY_STANDBY_ENABLE_A [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_DEFAULT 0
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_OBSERVE_CLOCK - Genet top rgmii inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A - Genet top rgmii inst power switch memory a
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A :: GENET0_POWER_SWITCH_MEMORY_A [01:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_MASK 0x00000003
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_CLOCK_DISABLE - Disable GRAPHICS's clocks
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_reserved0_SHIFT         1
+
+/* CLKGEN :: GRAPHICS_CLOCK_DISABLE :: DISABLE_GFX_M2MC_CORE_CLOCK [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_CLOCK_ENABLE - Graphics clock enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_reserved0_SHIFT          4
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_M2MC_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_ALTERNATE_108_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *GRAPHICS_MEMORY_STANDBY_ENABLE - Graphics memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE :: GFX_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_OBSERVE_CLOCK - Graphics observe clock
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_POWER_SWITCH_MEMORY - Graphics power switch memory
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY :: GFX_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *HIF_CLOCK_DISABLE - Disable HIF's clocks
+ ***************************************************************************/
+/* CLKGEN :: HIF_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_reserved0_MASK               0xfffffff0
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_reserved0_SHIFT              4
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_SDIO_48_CLOCK [03:03] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_MASK   0x00000008
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_SHIFT  3
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_DEFAULT 0
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [02:02] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK   0x00000004
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT  2
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_EBI_CLOCK [01:01] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_MASK   0x00000002
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_SHIFT  1
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_DEFAULT 0
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_54_SCANCLOCK [00:00] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_SHIFT 0
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_DEFAULT 0
+
+/***************************************************************************
+ *HIF_CLOCK_ENABLE - Hif clock enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_reserved0_SHIFT               3
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_MASK     0x00000004
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_SHIFT    2
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_DEFAULT  1
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_MASK     0x00000002
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_SHIFT    1
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_DEFAULT  1
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_MASK     0x00000001
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_SHIFT    0
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_DEFAULT  1
+
+/***************************************************************************
+ *HIF_MEMORY_STANDBY_ENABLE - Hif memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE :: HIF_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *HIF_POWER_SWITCH_MEMORY - Hif power switch memory
+ ***************************************************************************/
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_reserved0_SHIFT        2
+
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY :: HIF_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
+ ***************************************************************************/
+/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK             0xfffffff8
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT            3
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [02:02] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [01:01] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: GFX_M2MC_CORE_CLOCK [00:00] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_MASK   0x00000001
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_SHIFT  0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_16_CLOCK_ENABLE - Memsys 16 clock enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: DDR1_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: DDR1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *MEMSYS_16_MEMORY_STANDBY_ENABLE - Memsys 16 memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MEMSYS_16_MEMORY_STANDBY_ENABLE :: DDR1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_16_OBSERVE_CLOCK - Memsys 16 observe clock
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_16_POWER_SWITCH_MEMORY - Memsys 16 power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: MEMSYS_16_POWER_SWITCH_MEMORY :: DDR1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_16_STATUS - Memsys 16 status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_reserved0_SHIFT               1
+
+/* CLKGEN :: MEMSYS_16_STATUS :: MEMSYS_PLL_LOCKED_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_MEMSYS_PLL_LOCKED_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_MEMSYS_PLL_LOCKED_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PAD_CLK_OBSRV0_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLK_OBSRV1_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLK_OBSRV2_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLK_OBSRV3_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLOCK_DISABLE - Disable PAD's clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK               0xfffffff8
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT              3
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_SC_OUT_CLOCK [02:02] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_MASK    0x00000004
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_SHIFT   2
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *PAD_MUX_SELECT - Mux selects for Pad clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK                  0xfffffff8
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT                 3
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK27_CLOCK [02:00] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_MASK     0x00000007
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_SHIFT    0
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_DEFAULT  0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET_STATUS - PLL_AUDIO0 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET_STATUS - PLL_AUDIO1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET_STATUS - PLL_SC Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET_STATUS - PLL_SYS1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET_STATUS - PLL_VCXO Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PM_CLOCK_108_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_MASK          0xfffffff0
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_SHIFT         4
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSTFEC [03:03] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTFEC_MASK 0x00000008
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTFEC_SHIFT 3
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTFEC_DEFAULT 0
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSRCVR [02:02] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSRCVR_MASK 0x00000004
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSRCVR_SHIFT 2
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSRCVR_DEFAULT 0
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSAFEC [01:01] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC_MASK 0x00000002
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC_SHIFT 1
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC_DEFAULT 0
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_ [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG__MASK      0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG__SHIFT     0
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG__DEFAULT   0
+
+/***************************************************************************
+ *PM_CLOCK_216_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_SHIFT         1
+
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_MASK   0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT  0
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_DEFAULT 0
+
+/***************************************************************************
+ *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               3
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys_PLL [02:02] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_MASK               0x00000004
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_SHIFT              2
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_DEFAULT            0
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [01:01] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK                 0x00000002
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT                1
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT              0
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_AVD_MIPS [00:00] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_MASK             0x00000001
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_SHIFT            0
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_DEFAULT          0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_CLOCK_ENABLE - Raaga dsp top clock enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_reserved0_MASK      0xfffffff8
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_reserved0_SHIFT     3
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_DSP_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE - Raaga dsp top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE :: RAAGAA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_OBSERVE_CLOCK - Raaga dsp top observe clock
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_reserved0_SHIFT    2
+
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: RAAGA_ENABLE_OBSERVE_CLOCK [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_POWER_SWITCH_MEMORY - Raaga dsp top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_POWER_SWITCH_MEMORY :: RAAGA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *RFM_TOP_CLOCK_ENABLE - Rfm top clock enable
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_reserved0_SHIFT           1
+
+/* CLKGEN :: RFM_TOP_CLOCK_ENABLE :: RFM_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *RFM_TOP_MEMORY_STANDBY_ENABLE - Rfm top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: RFM_TOP_MEMORY_STANDBY_ENABLE :: RFMA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *RFM_TOP_OBSERVE_CLOCK - Rfm top observe clock
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_reserved0_MASK           0xffffffc0
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_reserved0_SHIFT          6
+
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *RFM_TOP_POWER_SWITCH_MEMORY - Rfm top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: RFM_TOP_POWER_SWITCH_MEMORY :: RFM_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SDS_AFEC_TOP_CLOCK_ENABLE - Sds afec top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: SDS_AFEC_TOP_CLOCK_ENABLE :: SDSAFEC0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE - Sds afec top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE :: SDSAFEC0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SDS_AFEC_TOP_OBSERVE_CLOCK - Sds afec top observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: SDSAFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SDS_AFEC_TOP_POWER_SWITCH_MEMORY - Sds afec top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS_AFEC_TOP_POWER_SWITCH_MEMORY :: SDSAFEC0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SDS_RECEIVER_CLOCK_DISABLE - Disable SDS_RECEIVER's clocks
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: SDS_RECEIVER_CLOCK_DISABLE :: DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK [00:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SDS_RECEIVER_CLOCK_ENABLE - Sds receiver clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: SDS_RECEIVER_CLOCK_ENABLE :: SDSRCVR0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_SDSRCVR0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_SDSRCVR0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_SDSRCVR0_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SDS_RECEIVER_MEMORY_STANDBY_ENABLE - Sds receiver memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS_RECEIVER_MEMORY_STANDBY_ENABLE :: SDSRCVR0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_SDSRCVR0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_SDSRCVR0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_SDSRCVR0_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SDS_RECEIVER_OBSERVE_CLOCK - Sds receiver observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: SDSRCVR0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: SDSRCVR0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SDS_RECEIVER_POWER_SWITCH_MEMORY - Sds receiver power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS_RECEIVER_POWER_SWITCH_MEMORY :: SDSRCVR0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_SDSRCVR0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_SDSRCVR0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_SDSRCVR0_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SDS_TFEC_TOP_CLOCK_ENABLE - Sds tfec top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: SDS_TFEC_TOP_CLOCK_ENABLE :: SDSTFEC0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_SDSTFEC0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_SDSTFEC0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_SDSTFEC0_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE - Sds tfec top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE :: SDS_TFEC0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_SDS_TFEC0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_SDS_TFEC0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_SDS_TFEC0_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SDS_TFEC_TOP_OBSERVE_CLOCK - Sds tfec top observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: SDS_TFEC0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: SDS_TFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SDS_TFEC_TOP_POWER_SWITCH_MEMORY - Sds tfec top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS_TFEC_TOP_POWER_SWITCH_MEMORY :: SDS_TFEC0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_SDS_TFEC0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_SDS_TFEC0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_SDS_TFEC0_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SECTOP_INST_CLOCK_ENABLE - Sectop inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_SHIFT       1
+
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: SEC_ALTERNATE_SCB_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SECTOP_INST_MEMORY_STANDBY_ENABLE - Sectop inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SECTOP_INST_MEMORY_STANDBY_ENABLE :: SEC_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
+ ***************************************************************************/
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:11] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK            0xfffff800
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT           11
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC_OUT_CLOCK [10:08] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_MASK         0x00000700
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_SHIFT        8
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_DEFAULT      0
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [07:05] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK            0x000000e0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT           5
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT         0
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [04:02] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK            0x0000001c
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT           2
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT         0
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: PLLSC_REFERENCE_CLOCK [01:00] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_MASK 0x00000003
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SPARE - Spares
+ ***************************************************************************/
+/* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK                     0xfffff000
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT                    12
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT                  0
+
+/* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK                    0x00000fff
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT                   0
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT                 0
+
+/***************************************************************************
+ *SYS_AON_OBSERVE_CLOCK - Sys aon observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_MASK           0xffffffc0
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_SHIFT          6
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_CLOCK_DISABLE - Disable SYS_CTRL's clocks
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_SHIFT         5
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK [03:03] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK [02:02] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK_SHIFT 2
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK  0x00000002
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK  0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_CLOCK_ENABLE - Sys ctrl clock enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_MASK           0xfffffffc
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_SHIFT          2
+
+/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: SYS_CTRL_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: SYS_CTRL_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SYS_CTRL_MEMORY_STANDBY_ENABLE - Sys ctrl memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_OBSERVE_CLOCK - Sys ctrl observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_POWER_SWITCH_MEMORY - Sys ctrl power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: SYS_CTRL_POWER_SWITCH_MEMORY :: SYS_CTRL_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *TESTPORT - Special Testport Controls
+ ***************************************************************************/
+/* CLKGEN :: TESTPORT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_TESTPORT_reserved0_MASK                        0xfffffff8
+#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT                       3
+
+/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [02:00] */
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK           0x00000007
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT          0
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT        0
+
+/***************************************************************************
+ *THD_TOP_CLOCK_ENABLE - Thd top clock enable
+ ***************************************************************************/
+/* CLKGEN :: THD_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_reserved0_MASK            0xfffffff8
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_reserved0_SHIFT           3
+
+/* CLKGEN :: THD_TOP_CLOCK_ENABLE :: THD_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: THD_TOP_CLOCK_ENABLE :: THD_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: THD_TOP_CLOCK_ENABLE :: THD_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *TS_CTRL0_CKTAP - Ts ctrl0 cktap
+ ***************************************************************************/
+/* CLKGEN :: TS_CTRL0_CKTAP :: reserved0 [31:22] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_reserved0_MASK                  0xffc00000
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_reserved0_SHIFT                 22
+
+/* CLKGEN :: TS_CTRL0_CKTAP :: TOGGLE_CNT_CKTAP [21:17] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_TOGGLE_CNT_CKTAP_MASK           0x003e0000
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_TOGGLE_CNT_CKTAP_SHIFT          17
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_TOGGLE_CNT_CKTAP_DEFAULT        0
+
+/* CLKGEN :: TS_CTRL0_CKTAP :: SEL_MUX2_CKTAP [16:16] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_SEL_MUX2_CKTAP_MASK             0x00010000
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_SEL_MUX2_CKTAP_SHIFT            16
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_SEL_MUX2_CKTAP_DEFAULT          0
+
+/* CLKGEN :: TS_CTRL0_CKTAP :: SEL_MUX1_CKTAP [15:15] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_SEL_MUX1_CKTAP_MASK             0x00008000
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_SEL_MUX1_CKTAP_SHIFT            15
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_SEL_MUX1_CKTAP_DEFAULT          0
+
+/* CLKGEN :: TS_CTRL0_CKTAP :: RO_SEL_CKTAP [14:14] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_RO_SEL_CKTAP_MASK               0x00004000
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_RO_SEL_CKTAP_SHIFT              14
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_RO_SEL_CKTAP_DEFAULT            0
+
+/* CLKGEN :: TS_CTRL0_CKTAP :: RO_EN_CKTAP [13:13] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_RO_EN_CKTAP_MASK                0x00002000
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_RO_EN_CKTAP_SHIFT               13
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_RO_EN_CKTAP_DEFAULT             0
+
+/* CLKGEN :: TS_CTRL0_CKTAP :: GATE_CTRL_EN_CKTAP [12:12] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_GATE_CTRL_EN_CKTAP_MASK         0x00001000
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_GATE_CTRL_EN_CKTAP_SHIFT        12
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_GATE_CTRL_EN_CKTAP_DEFAULT      0
+
+/* CLKGEN :: TS_CTRL0_CKTAP :: EN_RAND_CKTAP [11:08] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_EN_RAND_CKTAP_MASK              0x00000f00
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_EN_RAND_CKTAP_SHIFT             8
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_EN_RAND_CKTAP_DEFAULT           0
+
+/* CLKGEN :: TS_CTRL0_CKTAP :: EN_ORD_CKTAP [07:04] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_EN_ORD_CKTAP_MASK               0x000000f0
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_EN_ORD_CKTAP_SHIFT              4
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_EN_ORD_CKTAP_DEFAULT            0
+
+/* CLKGEN :: TS_CTRL0_CKTAP :: DIV2SEL_CKTAP [03:03] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_DIV2SEL_CKTAP_MASK              0x00000008
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_DIV2SEL_CKTAP_SHIFT             3
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_DIV2SEL_CKTAP_DEFAULT           0
+
+/* CLKGEN :: TS_CTRL0_CKTAP :: CLK_GATE_EN_CKTAP [02:02] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_CLK_GATE_EN_CKTAP_MASK          0x00000004
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_CLK_GATE_EN_CKTAP_SHIFT         2
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_CLK_GATE_EN_CKTAP_DEFAULT       0
+
+/* CLKGEN :: TS_CTRL0_CKTAP :: CKTAP_SEL_CKTAP [01:00] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_CKTAP_SEL_CKTAP_MASK            0x00000003
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_CKTAP_SEL_CKTAP_SHIFT           0
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_CKTAP_SEL_CKTAP_DEFAULT         0
+
+/***************************************************************************
+ *TS_CTRL1_CKTAP - Ts ctrl1 cktap
+ ***************************************************************************/
+/* CLKGEN :: TS_CTRL1_CKTAP :: reserved0 [31:26] */
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_reserved0_MASK                  0xfc000000
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_reserved0_SHIFT                 26
+
+/* CLKGEN :: TS_CTRL1_CKTAP :: TAP3VAL_CKTAP [25:22] */
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP3VAL_CKTAP_MASK              0x03c00000
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP3VAL_CKTAP_SHIFT             22
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP3VAL_CKTAP_DEFAULT           0
+
+/* CLKGEN :: TS_CTRL1_CKTAP :: TAP2VAL_CKTAP [21:18] */
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP2VAL_CKTAP_MASK              0x003c0000
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP2VAL_CKTAP_SHIFT             18
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP2VAL_CKTAP_DEFAULT           0
+
+/* CLKGEN :: TS_CTRL1_CKTAP :: TAP1VAL_CKTAP [17:14] */
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP1VAL_CKTAP_MASK              0x0003c000
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP1VAL_CKTAP_SHIFT             14
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP1VAL_CKTAP_DEFAULT           0
+
+/* CLKGEN :: TS_CTRL1_CKTAP :: TAP0VAL_CKTAP [13:10] */
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP0VAL_CKTAP_MASK              0x00003c00
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP0VAL_CKTAP_SHIFT             10
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP0VAL_CKTAP_DEFAULT           0
+
+/* CLKGEN :: TS_CTRL1_CKTAP :: RISE_VAL_CKTAP [09:07] */
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_RISE_VAL_CKTAP_MASK             0x00000380
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_RISE_VAL_CKTAP_SHIFT            7
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_RISE_VAL_CKTAP_DEFAULT          0
+
+/* CLKGEN :: TS_CTRL1_CKTAP :: FALL_VAL_CKTAP [06:04] */
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_FALL_VAL_CKTAP_MASK             0x00000070
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_FALL_VAL_CKTAP_SHIFT            4
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_FALL_VAL_CKTAP_DEFAULT          0
+
+/* CLKGEN :: TS_CTRL1_CKTAP :: FALL_TRANS_CKTAP [03:03] */
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_FALL_TRANS_CKTAP_MASK           0x00000008
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_FALL_TRANS_CKTAP_SHIFT          3
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_FALL_TRANS_CKTAP_DEFAULT        0
+
+/* CLKGEN :: TS_CTRL1_CKTAP :: APRIOR_SWITCH_CNT_CKTAP [02:00] */
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_APRIOR_SWITCH_CNT_CKTAP_MASK    0x00000007
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_APRIOR_SWITCH_CNT_CKTAP_SHIFT   0
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_APRIOR_SWITCH_CNT_CKTAP_DEFAULT 0
+
+/***************************************************************************
+ *TS_CTRL2_CKTAP - Ts ctrl2 cktap
+ ***************************************************************************/
+/* CLKGEN :: TS_CTRL2_CKTAP :: reserved0 [31:02] */
+#define BCHP_CLKGEN_TS_CTRL2_CKTAP_reserved0_MASK                  0xfffffffc
+#define BCHP_CLKGEN_TS_CTRL2_CKTAP_reserved0_SHIFT                 2
+
+/* CLKGEN :: TS_CTRL2_CKTAP :: START_CKTAP [01:01] */
+#define BCHP_CLKGEN_TS_CTRL2_CKTAP_START_CKTAP_MASK                0x00000002
+#define BCHP_CLKGEN_TS_CTRL2_CKTAP_START_CKTAP_SHIFT               1
+#define BCHP_CLKGEN_TS_CTRL2_CKTAP_START_CKTAP_DEFAULT             0
+
+/* CLKGEN :: TS_CTRL2_CKTAP :: CLEAR_CKTAP [00:00] */
+#define BCHP_CLKGEN_TS_CTRL2_CKTAP_CLEAR_CKTAP_MASK                0x00000001
+#define BCHP_CLKGEN_TS_CTRL2_CKTAP_CLEAR_CKTAP_SHIFT               0
+#define BCHP_CLKGEN_TS_CTRL2_CKTAP_CLEAR_CKTAP_DEFAULT             0
+
+/***************************************************************************
+ *TS_CTRL_CLK_MUX_SELECT - Mux selects for TS_CTRL_CLK clocks
+ ***************************************************************************/
+/* CLKGEN :: TS_CTRL_CLK_MUX_SELECT :: reserved0 [31:02] */
+#define BCHP_CLKGEN_TS_CTRL_CLK_MUX_SELECT_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_TS_CTRL_CLK_MUX_SELECT_reserved0_SHIFT         2
+
+/* CLKGEN :: TS_CTRL_CLK_MUX_SELECT :: CKTAP_TS_CLK [01:00] */
+#define BCHP_CLKGEN_TS_CTRL_CLK_MUX_SELECT_CKTAP_TS_CLK_MASK       0x00000003
+#define BCHP_CLKGEN_TS_CTRL_CLK_MUX_SELECT_CKTAP_TS_CLK_SHIFT      0
+#define BCHP_CLKGEN_TS_CTRL_CLK_MUX_SELECT_CKTAP_TS_CLK_DEFAULT    0
+
+/***************************************************************************
+ *TS_CTRL_DATA_CKTAP - Ts ctrl data cktap
+ ***************************************************************************/
+/* CLKGEN :: TS_CTRL_DATA_CKTAP :: reserved0 [31:31] */
+#define BCHP_CLKGEN_TS_CTRL_DATA_CKTAP_reserved0_MASK              0x80000000
+#define BCHP_CLKGEN_TS_CTRL_DATA_CKTAP_reserved0_SHIFT             31
+
+/* CLKGEN :: TS_CTRL_DATA_CKTAP :: TS_DATA_VALID_STATUS_CKTAP [30:30] */
+#define BCHP_CLKGEN_TS_CTRL_DATA_CKTAP_TS_DATA_VALID_STATUS_CKTAP_MASK 0x40000000
+#define BCHP_CLKGEN_TS_CTRL_DATA_CKTAP_TS_DATA_VALID_STATUS_CKTAP_SHIFT 30
+
+/* CLKGEN :: TS_CTRL_DATA_CKTAP :: TS_DATA_STATUS_CKTAP [29:00] */
+#define BCHP_CLKGEN_TS_CTRL_DATA_CKTAP_TS_DATA_STATUS_CKTAP_MASK   0x3fffffff
+#define BCHP_CLKGEN_TS_CTRL_DATA_CKTAP_TS_DATA_STATUS_CKTAP_SHIFT  0
+
+/***************************************************************************
+ *USB_CLOCK_DISABLE - Disable USB's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_reserved0_SHIFT              1
+
+/* CLKGEN :: USB_CLOCK_DISABLE :: DISABLE_USB_54_MDIO_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB_CLOCK_ENABLE - Usb clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_reserved0_SHIFT               2
+
+/* CLKGEN :: USB_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK    0x00000002
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT   1
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: USB_CLOCK_ENABLE :: USB0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK    0x00000001
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT   0
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *USB_MEMORY_STANDBY_ENABLE - Usb memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: USB_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *USB_OBSERVE_CLOCK - Usb observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_reserved0_MASK               0xffffffc0
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_reserved0_SHIFT              6
+
+/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB_POWER_SWITCH_MEMORY - Usb power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_reserved0_SHIFT        2
+
+/* CLKGEN :: USB_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_CLOCK_DISABLE - Disable VEC_AIO_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_CLOCK_ENABLE - Vec aio top clock enable
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: reserved0 [31:07] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_reserved0_MASK        0xffffff80
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_reserved0_SHIFT       7
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_SCB_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_SCB_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_216_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_108_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE2_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A - Vec aio top memory standby enable a
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A :: VEC_MEMORY_STANDBY_ENABLE_A [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B - Vec aio top memory standby enable b
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B :: AIO_MEMORY_STANDBY_ENABLE_B [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_OBSERVE_CLOCK - Vec aio top observe clock
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_POWER_SWITCH_MEMORY_A - Vec aio top power switch memory a
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_A :: VEC_POWER_SWITCH_MEMORY_A [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_POWER_SWITCH_MEMORY_B - Vec aio top power switch memory b
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_B :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_B :: AIO_POWER_SWITCH_MEMORY_B [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_DEFAULT 0
+
+#endif /* #ifndef BCHP_CLKGEN_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_common.h b/include/linux/brcmstb/7358a0/bchp_common.h
new file mode 100644
index 0000000..3c90fdb
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_common.h
@@ -0,0 +1,1896 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:35:36 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_common.h $
+ * 
+ * Hydra_Software_Devel/7   9/20/11 11:42a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_COMMON_H__
+#define BCHP_COMMON_H__
+
+/***************************************************************************
+ *BCM7358_A0
+ ***************************************************************************/
+#define BCHP_PHYSICAL_OFFSET                               0x10000000
+#define BCHP_REGISTER_START                                0x00000000 /* DECODE_RBNODE_REGS_0 is first */
+#define BCHP_REGISTER_END                                  0x00a2c800 /* XPT_XPU is last */
+#define BCHP_REGISTER_SIZE                                 0x0028b200 /* Number of registers */
+
+/****************************************************************************
+ * Core instance register start address.
+ ***************************************************************************/
+#define BCHP_DECODE_RBNODE_REGS_0_REG_START                0x00000000
+#define BCHP_DECODE_RBNODE_REGS_0_REG_END                  0x0000007c
+#define BCHP_DECODE_MAIN_0_REG_START                       0x00000100
+#define BCHP_DECODE_MAIN_0_REG_END                         0x000001fc
+#define BCHP_SDRAM_DEBUG_0_REG_START                       0x00000200
+#define BCHP_SDRAM_DEBUG_0_REG_END                         0x0000027c
+#define BCHP_DECODE_MCOM_0_REG_START                       0x00000300
+#define BCHP_DECODE_MCOM_0_REG_END                         0x0000031c
+#define BCHP_DECODE_SPRE_0_REG_START                       0x00000320
+#define BCHP_DECODE_SPRE_0_REG_END                         0x0000033c
+#define BCHP_DECODE_WPRD_0_REG_START                       0x00000340
+#define BCHP_DECODE_WPRD_0_REG_END                         0x0000035c
+#define BCHP_DECODE_DQNT_0_REG_START                       0x00000400
+#define BCHP_DECODE_DQNT_0_REG_END                         0x0000045c
+#define BCHP_DECODE_DQNT_8X8_0_REG_START                   0x00000500
+#define BCHP_DECODE_DQNT_8X8_0_REG_END                     0x0000057c
+#define BCHP_DECODE_XFRM_0_REG_START                       0x00000700
+#define BCHP_DECODE_XFRM_0_REG_END                         0x0000071c
+#define BCHP_DECODE_DBLK_0_REG_START                       0x00000720
+#define BCHP_DECODE_DBLK_0_REG_END                         0x0000073c
+#define BCHP_DECODE_MB_0_REG_START                         0x00000740
+#define BCHP_DECODE_MB_0_REG_END                           0x0000075c
+#define BCHP_REG_CABAC2BINS_0_REG_START                    0x00000b00
+#define BCHP_REG_CABAC2BINS_0_REG_END                      0x00000bfc
+#define BCHP_DECODE_SINT_0_REG_START                       0x00000c00
+#define BCHP_DECODE_SINT_0_REG_END                         0x00000dfc
+#define BCHP_DECODE_RVC_0_REG_START                        0x00000e00
+#define BCHP_DECODE_RVC_0_REG_END                          0x00000efc
+#define BCHP_DECODE_CPUREGS_0_REG_START                    0x00000f00
+#define BCHP_DECODE_CPUREGS_0_REG_END                      0x00000f7c
+#define BCHP_DECODE_CPUREGS2_0_REG_START                   0x00000f80
+#define BCHP_DECODE_CPUREGS2_0_REG_END                     0x00000ffc
+#define BCHP_DECODE_CPUDMA_0_REG_START                     0x00001800
+#define BCHP_DECODE_CPUDMA_0_REG_END                       0x000018fc
+#define BCHP_DECODE_DMAMEM_0_REG_START                     0x00001a00
+#define BCHP_DECODE_DMAMEM_0_REG_END                       0x000021fc
+#define BCHP_REG_CABAC2BINS2_0_REG_START                   0x00002400
+#define BCHP_REG_CABAC2BINS2_0_REG_END                     0x000027fc
+#define BCHP_DECODE_WPTBL_0_REG_START                      0x00003000
+#define BCHP_DECODE_WPTBL_0_REG_END                        0x000031fc
+#define BCHP_DECODE_SINT_OLOOP_0_REG_START                 0x0000cc00
+#define BCHP_DECODE_SINT_OLOOP_0_REG_END                   0x0000ccfc
+#define BCHP_DECODE_SD_0_REG_START                         0x00040800
+#define BCHP_DECODE_SD_0_REG_END                           0x00040ffc
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_START             0x00041000
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_END               0x0004107c
+#define BCHP_DECODE_CPUCORE_0_REG_START                    0x00044000
+#define BCHP_DECODE_CPUCORE_0_REG_END                      0x00044ffc
+#define BCHP_DECODE_CPUAUX_0_REG_START                     0x00045000
+#define BCHP_DECODE_CPUAUX_0_REG_END                       0x00045ffc
+#define BCHP_DECODE_CPUIMEM_0_REG_START                    0x00046000
+#define BCHP_DECODE_CPUIMEM_0_REG_END                      0x00047ffc
+#define BCHP_DECODE_CPUDMEM_0_REG_START                    0x00048000
+#define BCHP_DECODE_CPUDMEM_0_REG_END                      0x0004fffc
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_START            0x00051000
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_END              0x0005107c
+#define BCHP_DECODE_CPUDMA2_0_REG_START                    0x00051800
+#define BCHP_DECODE_CPUDMA2_0_REG_END                      0x000518fc
+#define BCHP_DECODE_DMAMEM2_0_REG_START                    0x00051a00
+#define BCHP_DECODE_DMAMEM2_0_REG_END                      0x000521fc
+#define BCHP_DECODE_CPUCORE2_0_REG_START                   0x00054000
+#define BCHP_DECODE_CPUCORE2_0_REG_END                     0x00054ffc
+#define BCHP_DECODE_CPUAUX2_0_REG_START                    0x00055000
+#define BCHP_DECODE_CPUAUX2_0_REG_END                      0x00055ffc
+#define BCHP_DECODE_CPUIMEM2_0_REG_START                   0x00056000
+#define BCHP_DECODE_CPUIMEM2_0_REG_END                     0x00057ffc
+#define BCHP_DECODE_CPUDMEM2_0_REG_START                   0x00058000
+#define BCHP_DECODE_CPUDMEM2_0_REG_END                     0x0005fffc
+#define BCHP_DECODE_IP_SHIM_0_REG_START                    0x00060000
+#define BCHP_DECODE_IP_SHIM_0_REG_END                      0x00060080
+#define BCHP_AVD_CACHE_0_REG_START                         0x00062000
+#define BCHP_AVD_CACHE_0_REG_END                           0x0006203c
+#define BCHP_AVD_INTR2_0_REG_START                         0x00080000
+#define BCHP_AVD_INTR2_0_REG_END                           0x0008002c
+#define BCHP_AVD_RGR_0_REG_START                           0x00080400
+#define BCHP_AVD_RGR_0_REG_END                             0x00080410
+#define BCHP_VICH_0_REG_START                              0x00170000
+#define BCHP_VICH_0_REG_END                                0x0017008b
+#define BCHP_BESTROM_REG_START                             0x00200000
+#define BCHP_BESTROM_REG_END                               0x00203ffc
+#define BCHP_BSP_CMDBUF_REG_START                          0x00328800
+#define BCHP_BSP_CMDBUF_REG_END                            0x00328ffc
+#define BCHP_BSP_GLB_CONTROL_REG_START                     0x0032b000
+#define BCHP_BSP_GLB_CONTROL_REG_END                       0x0032b08c
+#define BCHP_BSP_INST_PATCH_CTRL_REG_START                 0x0032b400
+#define BCHP_BSP_INST_PATCH_CTRL_REG_END                   0x0032b404
+#define BCHP_BSP_CONTROL_INTR2_REG_START                   0x0032b800
+#define BCHP_BSP_CONTROL_INTR2_REG_END                     0x0032b82c
+#define BCHP_BSP_INST_PATCHRAM_REG_START                   0x0032c000
+#define BCHP_BSP_INST_PATCHRAM_REG_END                     0x0032fffc
+#define BCHP_SECTOP_GRB_REG_START                          0x00360000
+#define BCHP_SECTOP_GRB_REG_END                            0x0036000c
+#define BCHP_JTAG_OTP_REG_START                            0x00360100
+#define BCHP_JTAG_OTP_REG_END                              0x00360138
+#define BCHP_MEM_DMA_0_REG_START                           0x00360200
+#define BCHP_MEM_DMA_0_REG_END                             0x00360224
+#define BCHP_MMSCRAM_REG_START                             0x00364000
+#define BCHP_MMSCRAM_REG_END                               0x00364ffc
+#define BCHP_MEM_DMA_SECURE_REG_START                      0x00366000
+#define BCHP_MEM_DMA_SECURE_REG_END                        0x0036600c
+#define BCHP_MEMC_GEN_0_REG_START                          0x003b0000
+#define BCHP_MEMC_GEN_0_REG_END                            0x003b03c8
+#define BCHP_MEMC_ARB_0_REG_START                          0x003b1000
+#define BCHP_MEMC_ARB_0_REG_END                            0x003b1244
+#define BCHP_MEMC_DDR_0_REG_START                          0x003b2000
+#define BCHP_MEMC_DDR_0_REG_END                            0x003b22f8
+#define BCHP_MEMC_L2_0_REG_START                           0x003b3000
+#define BCHP_MEMC_L2_0_REG_END                             0x003b302c
+#define BCHP_MEMC_L2_1_0_REG_START                         0x003b3800
+#define BCHP_MEMC_L2_1_0_REG_END                           0x003b382c
+#define BCHP_MEMC_RGRB_0_REG_START                         0x003b4000
+#define BCHP_MEMC_RGRB_0_REG_END                           0x003b4010
+#define BCHP_MEMC_MISC_0_REG_START                         0x003b5000
+#define BCHP_MEMC_MISC_0_REG_END                           0x003b5010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_START            0x003b6000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_END              0x003b60c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_START             0x003b6200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_END               0x003b63ac
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_START         0x003b8000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_END           0x003b80e4
+#define BCHP_S_MEMC_0_REG_START                            0x003ba000
+#define BCHP_S_MEMC_0_REG_END                              0x003ba220
+#define BCHP_SUN_GISB_ARB_REG_START                        0x00400000
+#define BCHP_SUN_GISB_ARB_REG_END                          0x004000d8
+#define BCHP_SUN_RGR_REG_START                             0x00400400
+#define BCHP_SUN_RGR_REG_END                               0x00400410
+#define BCHP_SUN_RG_REG_START                              0x00400800
+#define BCHP_SUN_RG_REG_END                                0x0040080c
+#define BCHP_SUN_L2_REG_START                              0x00403000
+#define BCHP_SUN_L2_REG_END                                0x0040302c
+#define BCHP_SM_L2_REG_START                               0x00403400
+#define BCHP_SM_L2_REG_END                                 0x0040342c
+#define BCHP_SM_REG_START                                  0x00403800
+#define BCHP_SM_REG_END                                    0x00403824
+#define BCHP_SM_FAST_REG_START                             0x00403c00
+#define BCHP_SM_FAST_REG_END                               0x00403c18
+#define BCHP_SUN_TOP_CTRL_REG_START                        0x00404000
+#define BCHP_SUN_TOP_CTRL_REG_END                          0x00404518
+#define BCHP_IRB_REG_START                                 0x00406000
+#define BCHP_IRB_REG_END                                   0x00406138
+#define BCHP_PM_REG_START                                  0x00406180
+#define BCHP_PM_REG_END                                    0x00406188
+#define BCHP_BSCA_REG_START                                0x00406200
+#define BCHP_BSCA_REG_END                                  0x00406254
+#define BCHP_BSCB_REG_START                                0x00406280
+#define BCHP_BSCB_REG_END                                  0x004062d4
+#define BCHP_BSCC_REG_START                                0x00406300
+#define BCHP_BSCC_REG_END                                  0x00406354
+#define BCHP_PWM_REG_START                                 0x00406400
+#define BCHP_PWM_REG_END                                   0x00406424
+#define BCHP_GIO_REG_START                                 0x00406500
+#define BCHP_GIO_REG_END                                   0x0040659c
+#define BCHP_IRQ0_REG_START                                0x00406600
+#define BCHP_IRQ0_REG_END                                  0x00406604
+#define BCHP_IRQ1_REG_START                                0x00406640
+#define BCHP_IRQ1_REG_END                                  0x00406644
+#define BCHP_TIMER_REG_START                               0x00406680
+#define BCHP_TIMER_REG_END                                 0x004066bc
+#define BCHP_PWMB_REG_START                                0x00406700
+#define BCHP_PWMB_REG_END                                  0x00406724
+#define BCHP_UARTA_REG_START                               0x00406800
+#define BCHP_UARTA_REG_END                                 0x0040681c
+#define BCHP_UARTB_REG_START                               0x00406840
+#define BCHP_UARTB_REG_END                                 0x0040685c
+#define BCHP_UARTC_REG_START                               0x00406880
+#define BCHP_UARTC_REG_END                                 0x0040689c
+#define BCHP_SCA_REG_START                                 0x00406a00
+#define BCHP_SCA_REG_END                                   0x00406abc
+#define BCHP_SCB_REG_START                                 0x00406b00
+#define BCHP_SCB_REG_END                                   0x00406bbc
+#define BCHP_SCIRQ0_REG_START                              0x00406c00
+#define BCHP_SCIRQ0_REG_END                                0x00406c04
+#define BCHP_SCIRQ1_REG_START                              0x00406c80
+#define BCHP_SCIRQ1_REG_END                                0x00406c84
+#define BCHP_AON_CTRL_REG_START                            0x00408000
+#define BCHP_AON_CTRL_REG_END                              0x004081bc
+#define BCHP_AON_L2_REG_START                              0x00408200
+#define BCHP_AON_L2_REG_END                                0x0040822c
+#define BCHP_AON_PM_L2_REG_START                           0x00408240
+#define BCHP_AON_PM_L2_REG_END                             0x0040826c
+#define BCHP_AON_PIN_CTRL_REG_START                        0x00408300
+#define BCHP_AON_PIN_CTRL_REG_END                          0x00408318
+#define BCHP_AON_HDMI_TX_REG_START                         0x00408400
+#define BCHP_AON_HDMI_TX_REG_END                           0x00408498
+#define BCHP_LDK_REG_START                                 0x00408800
+#define BCHP_LDK_REG_END                                   0x0040883c
+#define BCHP_PM_AON_REG_START                              0x00408840
+#define BCHP_PM_AON_REG_END                                0x00408848
+#define BCHP_ICAP_REG_START                                0x00408880
+#define BCHP_ICAP_REG_END                                  0x004088bc
+#define BCHP_KBD1_REG_START                                0x004088c0
+#define BCHP_KBD1_REG_END                                  0x004088fc
+#define BCHP_KBD2_REG_START                                0x00408900
+#define BCHP_KBD2_REG_END                                  0x0040893c
+#define BCHP_KBD3_REG_START                                0x00408940
+#define BCHP_KBD3_REG_END                                  0x0040897c
+#define BCHP_BSCD_REG_START                                0x00408980
+#define BCHP_BSCD_REG_END                                  0x004089d4
+#define BCHP_MSPI_REG_START                                0x00408a00
+#define BCHP_MSPI_REG_END                                  0x00408b7c
+#define BCHP_IRQ0_AON_REG_START                            0x00408b80
+#define BCHP_IRQ0_AON_REG_END                              0x00408b84
+#define BCHP_IRQ1_AON_REG_START                            0x00408b88
+#define BCHP_IRQ1_AON_REG_END                              0x00408b8c
+#define BCHP_GIO_AON_REG_START                             0x00408c00
+#define BCHP_GIO_AON_REG_END                               0x00408c5c
+#define BCHP_BICAP_REG_START                               0x00408e00
+#define BCHP_BICAP_REG_END                                 0x00408e38
+#define BCHP_UPG_AUX_AON_INTR2_REG_START                   0x00408e40
+#define BCHP_UPG_AUX_AON_INTR2_REG_END                     0x00408e6c
+#define BCHP_WKTMR_REG_START                               0x00408e80
+#define BCHP_WKTMR_REG_END                                 0x00408e90
+#define BCHP_SYS_GISB_ARB_SEC_REG_START                    0x0040e000
+#define BCHP_SYS_GISB_ARB_SEC_REG_END                      0x0040e0b4
+#define BCHP_SYS_TOP_CTRL_SEC_REG_START                    0x0040e700
+#define BCHP_SYS_TOP_CTRL_SEC_REG_END                      0x0040e704
+#define BCHP_AON_CTRL_SECURE_REG_START                     0x0040e800
+#define BCHP_AON_CTRL_SECURE_REG_END                       0x0040e830
+#define BCHP_MISB_BRIDGE_REG_START                         0x00410400
+#define BCHP_MISB_BRIDGE_REG_END                           0x00410410
+#define BCHP_EBI_REG_START                                 0x00410800
+#define BCHP_EBI_REG_END                                   0x00410bfc
+#define BCHP_HIF_INTR2_REG_START                           0x00411000
+#define BCHP_HIF_INTR2_REG_END                             0x0041102c
+#define BCHP_IPI0_INTR2_REG_START                          0x00411100
+#define BCHP_IPI0_INTR2_REG_END                            0x0041112c
+#define BCHP_IPI1_INTR2_REG_START                          0x00411200
+#define BCHP_IPI1_INTR2_REG_END                            0x0041122c
+#define BCHP_HIF_CPU_INTR1_REG_START                       0x00411400
+#define BCHP_HIF_CPU_INTR1_REG_END                         0x0041142c
+#define BCHP_HIF_RGR_REG_START                             0x00411800
+#define BCHP_HIF_RGR_REG_END                               0x00411810
+#define BCHP_HIF_SPI_INTR2_REG_START                       0x00411d00
+#define BCHP_HIF_SPI_INTR2_REG_END                         0x00411d2c
+#define BCHP_HIF_TOP_CTRL_REG_START                        0x00412400
+#define BCHP_HIF_TOP_CTRL_REG_END                          0x0041241c
+#define BCHP_NAND_REG_START                                0x00412800
+#define BCHP_NAND_REG_END                                  0x00412bfc
+#define BCHP_BSPI_REG_START                                0x00413000
+#define BCHP_BSPI_REG_END                                  0x0041304c
+#define BCHP_BSPI_RAF_REG_START                            0x00413100
+#define BCHP_BSPI_RAF_REG_END                              0x00413120
+#define BCHP_HIF_MSPI_REG_START                            0x00413200
+#define BCHP_HIF_MSPI_REG_END                              0x00413384
+#define BCHP_MICH_REG_START                                0x00414000
+#define BCHP_MICH_REG_END                                  0x00414000
+#define BCHP_HIF_SECURE_CTRL_REG_START                     0x00414100
+#define BCHP_HIF_SECURE_CTRL_REG_END                       0x00414100
+#define BCHP_HIF_SECURE_BSPI_REG_START                     0x00414200
+#define BCHP_HIF_SECURE_BSPI_REG_END                       0x00414200
+#define BCHP_HIF_SECURE_LR_SPI_REG_START                   0x00414300
+#define BCHP_HIF_SECURE_LR_SPI_REG_END                     0x00414300
+#define BCHP_NAND_SECURE_REG_START                         0x00414400
+#define BCHP_NAND_SECURE_REG_END                           0x00414400
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_START        0x00414800
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_END          0x00414800
+#define BCHP_CLKGEN_REG_START                              0x00420000
+#define BCHP_CLKGEN_REG_END                                0x00420370
+#define BCHP_VCXO_RM_REG_START                             0x00422800
+#define BCHP_VCXO_RM_REG_END                               0x0042282c
+#define BCHP_AVS_HW_MNTR_REG_START                         0x00423000
+#define BCHP_AVS_HW_MNTR_REG_END                           0x00423074
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_START                 0x00423100
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_END                   0x0042311c
+#define BCHP_AVS_ASB_REGISTERS_REG_START                   0x00423200
+#define BCHP_AVS_ASB_REGISTERS_REG_END                     0x00423218
+#define BCHP_AVS_RO_REGISTERS_0_REG_START                  0x00423300
+#define BCHP_AVS_RO_REGISTERS_0_REG_END                    0x004233dc
+#define BCHP_AVS_RO_REGISTERS_1_REG_START                  0x00423400
+#define BCHP_AVS_RO_REGISTERS_1_REG_END                    0x004234a4
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_START                0x00423500
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_END                  0x004235e4
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_START                0x00423600
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_END                  0x004236e4
+#define BCHP_CLKGEN_INTR2_REG_START                        0x00424000
+#define BCHP_CLKGEN_INTR2_REG_END                          0x0042402c
+#define BCHP_CLKGEN_GR_REG_START                           0x00424800
+#define BCHP_CLKGEN_GR_REG_END                             0x0042480c
+#define BCHP_GENET_0_SYS_REG_START                         0x00430000
+#define BCHP_GENET_0_SYS_REG_END                           0x0043000c
+#define BCHP_GENET_0_GR_BRIDGE_REG_START                   0x00430040
+#define BCHP_GENET_0_GR_BRIDGE_REG_END                     0x0043004c
+#define BCHP_GENET_0_EXT_REG_START                         0x00430080
+#define BCHP_GENET_0_EXT_REG_END                           0x00430098
+#define BCHP_GENET_0_INTRL2_0_REG_START                    0x00430200
+#define BCHP_GENET_0_INTRL2_0_REG_END                      0x0043022c
+#define BCHP_GENET_0_INTRL2_1_REG_START                    0x00430240
+#define BCHP_GENET_0_INTRL2_1_REG_END                      0x0043026c
+#define BCHP_GENET_0_RBUF_REG_START                        0x00430300
+#define BCHP_GENET_0_RBUF_REG_END                          0x004303ec
+#define BCHP_GENET_0_TBUF_REG_START                        0x00430600
+#define BCHP_GENET_0_TBUF_REG_END                          0x00430628
+#define BCHP_GENET_0_UMAC_REG_START                        0x00430800
+#define BCHP_GENET_0_UMAC_REG_END                          0x00430ed8
+#define BCHP_GENET_0_HFB_REG_START                         0x00431000
+#define BCHP_GENET_0_HFB_REG_END                           0x00432010
+#define BCHP_GENET_0_RDMA_REG_START                        0x00433000
+#define BCHP_GENET_0_RDMA_REG_END                          0x00433cb4
+#define BCHP_GENET_0_TDMA_REG_START                        0x00434000
+#define BCHP_GENET_0_TDMA_REG_END                          0x00434c88
+#define BCHP_M2MC_REG_START                                0x00450000
+#define BCHP_M2MC_REG_END                                  0x004507fc
+#define BCHP_M2MC_TOP_L2_REG_START                         0x00451000
+#define BCHP_M2MC_TOP_L2_REG_END                           0x0045102c
+#define BCHP_M2MC_TOP_GR_BRIDGE_REG_START                  0x00452000
+#define BCHP_M2MC_TOP_GR_BRIDGE_REG_END                    0x0045200c
+#define BCHP_USB_INTR2_REG_START                           0x00480000
+#define BCHP_USB_INTR2_REG_END                             0x0048002c
+#define BCHP_USB_GR_BRIDGE_REG_START                       0x00480100
+#define BCHP_USB_GR_BRIDGE_REG_END                         0x0048010c
+#define BCHP_USB_CTRL_REG_START                            0x00480200
+#define BCHP_USB_CTRL_REG_END                              0x00480238
+#define BCHP_USB_EHCI_REG_START                            0x00480300
+#define BCHP_USB_EHCI_REG_END                              0x004803a4
+#define BCHP_USB_OHCI_REG_START                            0x00480400
+#define BCHP_USB_OHCI_REG_END                              0x00480458
+#define BCHP_BOOTROM_REG_START                             0x00500000
+#define BCHP_BOOTROM_REG_END                               0x00503ffc
+#define BCHP_MFD_0_REG_START                               0x00600000
+#define BCHP_MFD_0_REG_END                                 0x006001fc
+#define BCHP_VFD_0_REG_START                               0x00601000
+#define BCHP_VFD_0_REG_END                                 0x006011fc
+#define BCHP_VFD_1_REG_START                               0x00601200
+#define BCHP_VFD_1_REG_END                                 0x006013fc
+#define BCHP_RDC_REG_START                                 0x00602000
+#define BCHP_RDC_REG_END                                   0x006029fc
+#define BCHP_BVNF_INTR2_0_REG_START                        0x00603000
+#define BCHP_BVNF_INTR2_0_REG_END                          0x0060302c
+#define BCHP_BVNF_INTR2_1_REG_START                        0x00603100
+#define BCHP_BVNF_INTR2_1_REG_END                          0x0060312c
+#define BCHP_BVNF_INTR2_3_REG_START                        0x00603300
+#define BCHP_BVNF_INTR2_3_REG_END                          0x0060332c
+#define BCHP_BVNF_INTR2_4_REG_START                        0x00603400
+#define BCHP_BVNF_INTR2_4_REG_END                          0x0060342c
+#define BCHP_BVNF_INTR2_5_REG_START                        0x00603500
+#define BCHP_BVNF_INTR2_5_REG_END                          0x0060352c
+#define BCHP_FMISC_REG_START                               0x00604000
+#define BCHP_FMISC_REG_END                                 0x00604020
+#define BCHP_SCL_0_REG_START                               0x00620000
+#define BCHP_SCL_0_REG_END                                 0x006203fc
+#define BCHP_SCL_1_REG_START                               0x00620800
+#define BCHP_SCL_1_REG_END                                 0x00620bfc
+#define BCHP_VNET_F_REG_START                              0x00622000
+#define BCHP_VNET_F_REG_END                                0x0062209c
+#define BCHP_VNET_B_REG_START                              0x00622200
+#define BCHP_VNET_B_REG_END                                0x006222ac
+#define BCHP_MMISC_REG_START                               0x00622800
+#define BCHP_MMISC_REG_END                                 0x00622820
+#define BCHP_LBOX_0_REG_START                              0x00625000
+#define BCHP_LBOX_0_REG_END                                0x00625070
+#define BCHP_BVNM_INTR2_0_REG_START                        0x00626000
+#define BCHP_BVNM_INTR2_0_REG_END                          0x0062602c
+#define BCHP_DNR_0_REG_START                               0x00627000
+#define BCHP_DNR_0_REG_END                                 0x006270a4
+#define BCHP_CAP_0_REG_START                               0x00640000
+#define BCHP_CAP_0_REG_END                                 0x0064007c
+#define BCHP_CAP_1_REG_START                               0x00640200
+#define BCHP_CAP_1_REG_END                                 0x0064027c
+#define BCHP_GFD_0_REG_START                               0x00641000
+#define BCHP_GFD_0_REG_END                                 0x00641228
+#define BCHP_GFD_1_REG_START                               0x00641400
+#define BCHP_GFD_1_REG_END                                 0x00641628
+#define BCHP_CMP_0_REG_START                               0x00642000
+#define BCHP_CMP_0_REG_END                                 0x00642264
+#define BCHP_CMP_1_REG_START                               0x00642800
+#define BCHP_CMP_1_REG_END                                 0x00642cb4
+#define BCHP_TNT_CMP_0_V0_REG_START                        0x00643000
+#define BCHP_TNT_CMP_0_V0_REG_END                          0x006430a4
+#define BCHP_MASK_0_REG_START                              0x00643400
+#define BCHP_MASK_0_REG_END                                0x0064341c
+#define BCHP_PEP_CMP_0_V0_REG_START                        0x00644000
+#define BCHP_PEP_CMP_0_V0_REG_END                          0x00645484
+#define BCHP_BVNB_INTR2_REG_START                          0x00646000
+#define BCHP_BVNB_INTR2_REG_END                            0x0064602c
+#define BCHP_BMISC_REG_START                               0x00646400
+#define BCHP_BMISC_REG_END                                 0x0064641c
+#define BCHP_MVP_TOP_0_REG_START                           0x00660000
+#define BCHP_MVP_TOP_0_REG_END                             0x0066002c
+#define BCHP_SIOB_0_REG_START                              0x00660200
+#define BCHP_SIOB_0_REG_END                                0x006602fc
+#define BCHP_HSCL_0_REG_START                              0x00660400
+#define BCHP_HSCL_0_REG_END                                0x006607fc
+#define BCHP_MDI_TOP_0_REG_START                           0x00662000
+#define BCHP_MDI_TOP_0_REG_END                             0x00662044
+#define BCHP_MDI_PPB_0_REG_START                           0x00662800
+#define BCHP_MDI_PPB_0_REG_END                             0x00662bfc
+#define BCHP_MDI_FCN_0_REG_START                           0x00662c00
+#define BCHP_MDI_FCN_0_REG_END                             0x00662ffc
+#define BCHP_MISC_REG_START                                0x00680000
+#define BCHP_MISC_REG_END                                  0x0068007c
+#define BCHP_IT_0_REG_START                                0x00681000
+#define BCHP_IT_0_REG_END                                  0x006817fc
+#define BCHP_IT_1_REG_START                                0x00682000
+#define BCHP_IT_1_REG_END                                  0x006827fc
+#define BCHP_VF_0_REG_START                                0x00683000
+#define BCHP_VF_0_REG_END                                  0x00683134
+#define BCHP_VF_1_REG_START                                0x00683200
+#define BCHP_VF_1_REG_END                                  0x00683334
+#define BCHP_SECAM_0_REG_START                             0x00683400
+#define BCHP_SECAM_0_REG_END                               0x00683414
+#define BCHP_SM_0_REG_START                                0x00683480
+#define BCHP_SM_0_REG_END                                  0x006834ac
+#define BCHP_SDSRC_0_REG_START                             0x00683500
+#define BCHP_SDSRC_0_REG_END                               0x0068350c
+#define BCHP_HDSRC_0_REG_START                             0x00683520
+#define BCHP_HDSRC_0_REG_END                               0x0068353c
+#define BCHP_CSC_0_REG_START                               0x00683580
+#define BCHP_CSC_0_REG_END                                 0x006835b0
+#define BCHP_CSC_1_REG_START                               0x00683600
+#define BCHP_CSC_1_REG_END                                 0x00683630
+#define BCHP_RM_0_REG_START                                0x00683680
+#define BCHP_RM_0_REG_END                                  0x006836a4
+#define BCHP_RM_1_REG_START                                0x006836c0
+#define BCHP_RM_1_REG_END                                  0x006836e4
+#define BCHP_ANA_DEBUG_0_REG_START                         0x00683700
+#define BCHP_ANA_DEBUG_0_REG_END                           0x00683744
+#define BCHP_GRPD_0_REG_START                              0x00683800
+#define BCHP_GRPD_0_REG_END                                0x006838ec
+#define BCHP_DTRAM_0_REG_START                             0x00684000
+#define BCHP_DTRAM_0_REG_END                               0x0068447c
+#define BCHP_DVI_DTG_0_REG_START                           0x00684800
+#define BCHP_DVI_DTG_0_REG_END                             0x00684954
+#define BCHP_DVI_CSC_0_REG_START                           0x00684a00
+#define BCHP_DVI_CSC_0_REG_END                             0x00684a30
+#define BCHP_DVI_DVF_0_REG_START                           0x00684b00
+#define BCHP_DVI_DVF_0_REG_END                             0x00684b14
+#define BCHP_DVI_DEBUG_0_REG_START                         0x00684c00
+#define BCHP_DVI_DEBUG_0_REG_END                           0x00684c44
+#define BCHP_VEC_CFG_REG_START                             0x00685000
+#define BCHP_VEC_CFG_REG_END                               0x006850d4
+#define BCHP_VIDEO_ENC_INTR2_REG_START                     0x00685400
+#define BCHP_VIDEO_ENC_INTR2_REG_END                       0x0068542c
+#define BCHP_VIDEO_ENC_TPG_0_REG_START                     0x00685500
+#define BCHP_VIDEO_ENC_TPG_0_REG_END                       0x00685518
+#define BCHP_VIDEO_ENC_DECIM_0_REG_START                   0x00685600
+#define BCHP_VIDEO_ENC_DECIM_0_REG_END                     0x00685608
+#define BCHP_DVP_DGEN_0_REG_START                          0x00685700
+#define BCHP_DVP_DGEN_0_REG_END                            0x00685738
+#define BCHP_VBI_ENC_REG_START                             0x00686000
+#define BCHP_VBI_ENC_REG_END                               0x00686054
+#define BCHP_CCE_0_REG_START                               0x00686400
+#define BCHP_CCE_0_REG_END                                 0x00686458
+#define BCHP_CCE_1_REG_START                               0x00686500
+#define BCHP_CCE_1_REG_END                                 0x00686558
+#define BCHP_WSE_0_REG_START                               0x00686600
+#define BCHP_WSE_0_REG_END                                 0x00686614
+#define BCHP_WSE_1_REG_START                               0x00686700
+#define BCHP_WSE_1_REG_END                                 0x00686714
+#define BCHP_CGMSAE_0_REG_START                            0x00686800
+#define BCHP_CGMSAE_0_REG_END                              0x00686858
+#define BCHP_CGMSAE_1_REG_START                            0x00686900
+#define BCHP_CGMSAE_1_REG_END                              0x00686958
+#define BCHP_TTE_0_REG_START                               0x00686a00
+#define BCHP_TTE_0_REG_END                                 0x00686a28
+#define BCHP_TTE_1_REG_START                               0x00686b00
+#define BCHP_TTE_1_REG_END                                 0x00686b28
+#define BCHP_GSE_0_REG_START                               0x00686c00
+#define BCHP_GSE_0_REG_END                                 0x00686c80
+#define BCHP_GSE_1_REG_START                               0x00686d00
+#define BCHP_GSE_1_REG_END                                 0x00686d80
+#define BCHP_AMOLE_0_REG_START                             0x00686e00
+#define BCHP_AMOLE_0_REG_END                               0x00686e8c
+#define BCHP_AMOLE_1_REG_START                             0x00686f00
+#define BCHP_AMOLE_1_REG_END                               0x00686f8c
+#define BCHP_DVP_HT_REG_START                              0x006a0000
+#define BCHP_DVP_HT_REG_END                                0x006a0070
+#define BCHP_HDMI_REG_START                                0x006a0800
+#define BCHP_HDMI_REG_END                                  0x006a09b4
+#define BCHP_HDMI_TX_PHY_REG_START                         0x006a0a80
+#define BCHP_HDMI_TX_PHY_REG_END                           0x006a0ac0
+#define BCHP_HDMI_RM_REG_START                             0x006a0b00
+#define BCHP_HDMI_RM_REG_END                               0x006a0b2c
+#define BCHP_HDMI_TX_INTR2_REG_START                       0x006a0b40
+#define BCHP_HDMI_TX_INTR2_REG_END                         0x006a0b6c
+#define BCHP_HDMI_RAM_REG_START                            0x006a0c00
+#define BCHP_HDMI_RAM_REG_END                              0x006a0dfc
+#define BCHP_BVN_RGR_REG_START                             0x006a8000
+#define BCHP_BVN_RGR_REG_END                               0x006a8010
+#define BCHP_SDS_CG_REG_START                              0x00700000
+#define BCHP_SDS_CG_REG_END                                0x00700038
+#define BCHP_SDS_FE_REG_START                              0x00700080
+#define BCHP_SDS_FE_REG_END                                0x007000bc
+#define BCHP_SDS_AGC_REG_START                             0x00700100
+#define BCHP_SDS_AGC_REG_END                               0x00700124
+#define BCHP_SDS_BL_REG_START                              0x00700140
+#define BCHP_SDS_BL_REG_END                                0x00700160
+#define BCHP_SDS_CL_REG_START                              0x00700180
+#define BCHP_SDS_CL_REG_END                                0x007001fc
+#define BCHP_SDS_EQ_REG_START                              0x00700200
+#define BCHP_SDS_EQ_REG_END                                0x0070028c
+#define BCHP_SDS_HP_REG_START                              0x00700300
+#define BCHP_SDS_HP_REG_END                                0x007003d4
+#define BCHP_SDS_VIT_REG_START                             0x00700400
+#define BCHP_SDS_VIT_REG_END                               0x00700428
+#define BCHP_SDS_FEC_REG_START                             0x00700440
+#define BCHP_SDS_FEC_REG_END                               0x00700454
+#define BCHP_SDS_OI_REG_START                              0x00700480
+#define BCHP_SDS_OI_REG_END                                0x007004c8
+#define BCHP_SDS_SNR_REG_START                             0x00700500
+#define BCHP_SDS_SNR_REG_END                               0x00700518
+#define BCHP_SDS_BERT_REG_START                            0x00700540
+#define BCHP_SDS_BERT_REG_END                              0x0070055c
+#define BCHP_SDS_DFT_REG_START                             0x00700580
+#define BCHP_SDS_DFT_REG_END                               0x007005a8
+#define BCHP_SDS_NTCH_REG_START                            0x007005c0
+#define BCHP_SDS_NTCH_REG_END                              0x007005e0
+#define BCHP_SDS_MISC_REG_START                            0x00700600
+#define BCHP_SDS_MISC_REG_END                              0x00700698
+#define BCHP_SDS_DSEC_REG_START                            0x00700700
+#define BCHP_SDS_DSEC_REG_END                              0x007007c8
+#define BCHP_SDS_TUNER_REG_START                           0x00700800
+#define BCHP_SDS_TUNER_REG_END                             0x007008fc
+#define BCHP_SDS_INTR2_0_REG_START                         0x00700a00
+#define BCHP_SDS_INTR2_0_REG_END                           0x00700a2c
+#define BCHP_SDS_INTR2_1_REG_START                         0x00700b00
+#define BCHP_SDS_INTR2_1_REG_END                           0x00700b2c
+#define BCHP_SDS_GR_BRIDGE_REG_START                       0x00700c00
+#define BCHP_SDS_GR_BRIDGE_REG_END                         0x00700c0c
+#define BCHP_TFEC_REG_START                                0x00702000
+#define BCHP_TFEC_REG_END                                  0x0070205c
+#define BCHP_TFEC_MISC_REG_START                           0x00702100
+#define BCHP_TFEC_MISC_REG_END                             0x00702108
+#define BCHP_TFEC_INTR2_REG_START                          0x00702200
+#define BCHP_TFEC_INTR2_REG_END                            0x0070222c
+#define BCHP_TFEC_GR_BRIDGE_REG_START                      0x00702300
+#define BCHP_TFEC_GR_BRIDGE_REG_END                        0x0070230c
+#define BCHP_AFEC_REG_START                                0x00704000
+#define BCHP_AFEC_REG_END                                  0x007043fc
+#define BCHP_AFEC_INTR_CTRL2_REG_START                     0x00704800
+#define BCHP_AFEC_INTR_CTRL2_REG_END                       0x0070482c
+#define BCHP_AFEC_GR_BRIDGE_REG_START                      0x00704900
+#define BCHP_AFEC_GR_BRIDGE_REG_END                        0x0070490c
+#define BCHP_AFEC_GLOBAL_REG_START                         0x00704a00
+#define BCHP_AFEC_GLOBAL_REG_END                           0x00704a0c
+#define BCHP_FTM_UART_REG_START                            0x00706000
+#define BCHP_FTM_UART_REG_END                              0x007060fc
+#define BCHP_FTM_PHY_REG_START                             0x00706000
+#define BCHP_FTM_PHY_REG_END                               0x00706210
+#define BCHP_FTM_SKIT_REG_START                            0x00706000
+#define BCHP_FTM_SKIT_REG_END                              0x00706248
+#define BCHP_FTM_INTR2_REG_START                           0x00706000
+#define BCHP_FTM_INTR2_REG_END                             0x0070632c
+#define BCHP_FTM_GR_BRIDGE_REG_START                       0x00706000
+#define BCHP_FTM_GR_BRIDGE_REG_END                         0x0070633c
+#define BCHP_RAAGA_DSP_RGR_REG_START                       0x00800000
+#define BCHP_RAAGA_DSP_RGR_REG_END                         0x00800008
+#define BCHP_RAAGA_DSP_MISC_REG_START                      0x00820000
+#define BCHP_RAAGA_DSP_MISC_REG_END                        0x0082040c
+#define BCHP_RAAGA_DSP_TIMERS_REG_START                    0x00821000
+#define BCHP_RAAGA_DSP_TIMERS_REG_END                      0x00821058
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START             0x00821080
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END               0x0082109c
+#define BCHP_RAAGA_DSP_PERI_SW_REG_START                   0x00821100
+#define BCHP_RAAGA_DSP_PERI_SW_REG_END                     0x00821154
+#define BCHP_RAAGA_DSP_DMA_REG_START                       0x00821200
+#define BCHP_RAAGA_DSP_DMA_REG_END                         0x00821364
+#define BCHP_RAAGA_DSP_ESR_SI_REG_START                    0x00822000
+#define BCHP_RAAGA_DSP_ESR_SI_REG_END                      0x00822014
+#define BCHP_RAAGA_DSP_INTH_REG_START                      0x00822200
+#define BCHP_RAAGA_DSP_INTH_REG_END                        0x0082222c
+#define BCHP_RAAGA_DSP_FW_INTH_REG_START                   0x00822400
+#define BCHP_RAAGA_DSP_FW_INTH_REG_END                     0x0082242c
+#define BCHP_RAAGA_DSP_FW_CFG_REG_START                    0x00823000
+#define BCHP_RAAGA_DSP_FW_CFG_REG_END                      0x0082357c
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START             0x00830000
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END               0x0083bffc
+#define BCHP_AIO_MISC_REG_START                            0x00880000
+#define BCHP_AIO_MISC_REG_END                              0x00880010
+#define BCHP_AIO_INTH_REG_START                            0x00880800
+#define BCHP_AIO_INTH_REG_END                              0x0088082c
+#define BCHP_AIO_INTD0_REG_START                           0x00880a00
+#define BCHP_AIO_INTD0_REG_END                             0x00880a14
+#define BCHP_AUD_FMM_MISC_REG_START                        0x008a0000
+#define BCHP_AUD_FMM_MISC_REG_END                          0x008a010c
+#define BCHP_AUD_FMM_BF_CTRL_REG_START                     0x008a2000
+#define BCHP_AUD_FMM_BF_CTRL_REG_END                       0x008a2b7c
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_START                   0x008a3000
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_END                     0x008a3014
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_START                   0x008a3020
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_END                     0x008a3034
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_START                   0x008a3040
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_END                     0x008a3054
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_START                  0x008a3100
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_END                    0x008a3114
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_START                  0x008a3120
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_END                    0x008a3134
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_START                  0x008a3140
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_END                    0x008a3154
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_START                   0x008a4000
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_END                     0x008a4bfc
+#define BCHP_AUD_FMM_SRC_ESR0_REG_START                    0x008a5000
+#define BCHP_AUD_FMM_SRC_ESR0_REG_END                      0x008a5014
+#define BCHP_AUD_FMM_DP_CTRL0_REG_START                    0x008a8000
+#define BCHP_AUD_FMM_DP_CTRL0_REG_END                      0x008a98ec
+#define BCHP_AUD_FMM_DP_ESR00_REG_START                    0x008abc00
+#define BCHP_AUD_FMM_DP_ESR00_REG_END                      0x008abc14
+#define BCHP_AUD_FMM_DP_ESR20_REG_START                    0x008abc80
+#define BCHP_AUD_FMM_DP_ESR20_REG_END                      0x008abc94
+#define BCHP_AUD_FMM_IOP_CTRL_REG_START                    0x008b8000
+#define BCHP_AUD_FMM_IOP_CTRL_REG_END                      0x008b8144
+#define BCHP_AUD_FMM_IOP_ESR_REG_START                     0x008b8400
+#define BCHP_AUD_FMM_IOP_ESR_REG_END                       0x008b8414
+#define BCHP_AUD_FMM_OP_CTRL_REG_START                     0x008ba000
+#define BCHP_AUD_FMM_OP_CTRL_REG_END                       0x008ba1fc
+#define BCHP_AUD_FMM_OP_ESR_REG_START                      0x008ba400
+#define BCHP_AUD_FMM_OP_ESR_REG_END                        0x008ba414
+#define BCHP_AUD_FMM_PLL0_REG_START                        0x008ba800
+#define BCHP_AUD_FMM_PLL0_REG_END                          0x008ba834
+#define BCHP_AUD_FMM_PLL1_REG_START                        0x008ba900
+#define BCHP_AUD_FMM_PLL1_REG_END                          0x008ba934
+#define BCHP_HIFIDAC_CTRL0_REG_START                       0x008bb000
+#define BCHP_HIFIDAC_CTRL0_REG_END                         0x008bb1fc
+#define BCHP_HIFIDAC_RM0_REG_START                         0x008bb200
+#define BCHP_HIFIDAC_RM0_REG_END                           0x008bb224
+#define BCHP_HIFIDAC_ESR0_REG_START                        0x008bb300
+#define BCHP_HIFIDAC_ESR0_REG_END                          0x008bb314
+#define BCHP_AUD_FMM_MS_CTRL_REG_START                     0x008bc000
+#define BCHP_AUD_FMM_MS_CTRL_REG_END                       0x008bdbfc
+#define BCHP_AUD_FMM_MS_ESR_REG_START                      0x008be000
+#define BCHP_AUD_FMM_MS_ESR_REG_END                        0x008be014
+#define BCHP_RAAGA_DSP_SEC0_REG_START                      0x00900000
+#define BCHP_RAAGA_DSP_SEC0_REG_END                        0x00900000
+#define BCHP_XPT_BUS_IF_REG_START                          0x00a00000
+#define BCHP_XPT_BUS_IF_REG_END                            0x00a00078
+#define BCHP_XPT_XMEMIF_REG_START                          0x00a01000
+#define BCHP_XPT_XMEMIF_REG_END                            0x00a0109c
+#define BCHP_XPT_PMU_REG_START                             0x00a01800
+#define BCHP_XPT_PMU_REG_END                               0x00a01808
+#define BCHP_XPT_WAKEUP_REG_START                          0x00a02000
+#define BCHP_XPT_WAKEUP_REG_END                            0x00a02fbc
+#define BCHP_XPT_RMX0_IO_REG_START                         0x00a03000
+#define BCHP_XPT_RMX0_IO_REG_END                           0x00a03020
+#define BCHP_XPT_RMX1_IO_REG_START                         0x00a03100
+#define BCHP_XPT_RMX1_IO_REG_END                           0x00a03120
+#define BCHP_XPT_FE_REG_START                              0x00a04000
+#define BCHP_XPT_FE_REG_END                                0x00a04ffc
+#define BCHP_XPT_DPCR0_REG_START                           0x00a06000
+#define BCHP_XPT_DPCR0_REG_END                             0x00a06074
+#define BCHP_XPT_DPCR1_REG_START                           0x00a06080
+#define BCHP_XPT_DPCR1_REG_END                             0x00a060f4
+#define BCHP_XPT_DPCR2_REG_START                           0x00a06100
+#define BCHP_XPT_DPCR2_REG_END                             0x00a06174
+#define BCHP_XPT_DPCR3_REG_START                           0x00a06180
+#define BCHP_XPT_DPCR3_REG_END                             0x00a061f4
+#define BCHP_XPT_DPCR_PP_REG_START                         0x00a06400
+#define BCHP_XPT_DPCR_PP_REG_END                           0x00a06404
+#define BCHP_XPT_PSUB_REG_START                            0x00a06600
+#define BCHP_XPT_PSUB_REG_END                              0x00a066c8
+#define BCHP_XPT_RSBUFF_REG_START                          0x00a06800
+#define BCHP_XPT_RSBUFF_REG_END                            0x00a06f2c
+#define BCHP_XPT_PB0_REG_START                             0x00a07000
+#define BCHP_XPT_PB0_REG_END                               0x00a07060
+#define BCHP_XPT_PB1_REG_START                             0x00a07080
+#define BCHP_XPT_PB1_REG_END                               0x00a070e0
+#define BCHP_XPT_PB2_REG_START                             0x00a07100
+#define BCHP_XPT_PB2_REG_END                               0x00a07160
+#define BCHP_XPT_PB3_REG_START                             0x00a07180
+#define BCHP_XPT_PB3_REG_END                               0x00a071e0
+#define BCHP_XPT_MPOD_REG_START                            0x00a08000
+#define BCHP_XPT_MPOD_REG_END                              0x00a08020
+#define BCHP_XPT_RMX0_REG_START                            0x00a08400
+#define BCHP_XPT_RMX0_REG_END                              0x00a08408
+#define BCHP_XPT_RMX1_REG_START                            0x00a08500
+#define BCHP_XPT_RMX1_REG_END                              0x00a08508
+#define BCHP_XPT_XCBUFF_REG_START                          0x00a0a000
+#define BCHP_XPT_XCBUFF_REG_END                            0x00a0bcc8
+#define BCHP_XPT_RAVE_REG_START                            0x00a10000
+#define BCHP_XPT_RAVE_REG_END                              0x00a1a69c
+#define BCHP_XPT_PCROFFSET_REG_START                       0x00a1b000
+#define BCHP_XPT_PCROFFSET_REG_END                         0x00a1bffc
+#define BCHP_XPT_MSG_REG_START                             0x00a20000
+#define BCHP_XPT_MSG_REG_END                               0x00a24814
+#define BCHP_XPT_GR_REG_START                              0x00a25000
+#define BCHP_XPT_GR_REG_END                                0x00a2500c
+#define BCHP_XPT_FULL_PID_PARSER_REG_START                 0x00a26000
+#define BCHP_XPT_FULL_PID_PARSER_REG_END                   0x00a27050
+#define BCHP_XPT_XPU_REG_START                             0x00a28000
+#define BCHP_XPT_XPU_REG_END                               0x00a2c7fc
+
+
+/***************************************************************************
+ *AUD_FMM_MS_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK  0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
+
+/***************************************************************************
+ *AUD_FMM_OP_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
+ ***************************************************************************/
+/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *BVN_MFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK  0xffffffff
+#define BCHP_BVN_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_VFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK  0xffffffff
+#define BCHP_BVN_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *GFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK      0xffffffff
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT     0
+
+/***************************************************************************
+ *HIFIDAC_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_MUTE_USAGE - Mute usage
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *M2MC
+ ***************************************************************************/
+/***************************************************************************
+ *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK          0xffffffff
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT         0
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK              0xf0000000
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT             28
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK          0x0fffffe0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT         5
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK              0x0000001e
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT             1
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK           0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT          0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid   0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK              0xffff8000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT             15
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK   0x00004000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT  14
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK   0x00002000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT  13
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK         0x00000800
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT        11
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE   1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE  0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK  0x00000400
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK  0x00000200
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK          0x00000100
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT         8
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE   0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK   0x00000020
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT  5
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK     0x00000002
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK     0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT    0
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/***************************************************************************
+ *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK        0xffffffff
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT       0
+
+/***************************************************************************
+ *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK         0xffffffff
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT        0
+
+/***************************************************************************
+ *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_11_DST_COLOR_MATRIX_N - Linked-List Packet Word N for group DST_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_11_DST_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_12_OUTPUT_COLOR_MATRIX_N - Linked-List Packet Word N for group OUTPUT_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_12_OUTPUT_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_13_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *LIST_PKT_14_DST_CLUT - Linked-List Packet Word for group DST_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_14_DST_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_14_DST_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *TYPE_CLUT_COLOR_DATA - color data for color look up table
+ ***************************************************************************/
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK                  0xff000000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT                 24
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK                    0x00ff0000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT                   16
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK                  0x0000ff00
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT                 8
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK                   0x000000ff
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT                  0
+
+/***************************************************************************
+ *MEM_DMA
+ ***************************************************************************/
+/***************************************************************************
+ *DESC_WORD0 - MEM DMA Descriptor Word 0
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD0 :: READ_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD1 - MEM DMA Descriptor Word 1
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD1 :: WRITE_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_MASK                    0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD2 - MEM DMA Descriptor Word 2
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD2 :: INTR_ENABLE [31:31] */
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK                   0x80000000
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_SHIFT                  31
+
+/* MEM_DMA :: DESC_WORD2 :: LAST [30:30] */
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_MASK                          0x40000000
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_SHIFT                         30
+
+/* MEM_DMA :: DESC_WORD2 :: AUTO_APPEND [29:29] */
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_MASK                   0x20000000
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_SHIFT                  29
+
+/* MEM_DMA :: DESC_WORD2 :: reserved0 [28:25] */
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_MASK                     0x1e000000
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_SHIFT                    25
+
+/* MEM_DMA :: DESC_WORD2 :: TRANSFER_SIZE [24:00] */
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK                 0x01ffffff
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_SHIFT                0
+
+/***************************************************************************
+ *DESC_WORD3 - MEM DMA Descriptor Word 3
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD3 :: NEXT_DESC_ADDR [31:05] */
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK                0xffffffe0
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_SHIFT               5
+
+/* MEM_DMA :: DESC_WORD3 :: reserved0 [04:03] */
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_MASK                     0x00000018
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_SHIFT                    3
+
+/* MEM_DMA :: DESC_WORD3 :: READ_ENDIAN_MODE [02:02] */
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_MASK              0x00000004
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_SHIFT             2
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_BIG_ENDIAN        0
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_LITTLE_ENDIAN     1
+
+/* MEM_DMA :: DESC_WORD3 :: WRITE_ENDIAN_XLATE_MODE [01:00] */
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_MASK       0x00000003
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_SHIFT      0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_WORD_ALIGNED 0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_HALF_WORD_ALIGNED 1
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_BYTE_ALIGNED 2
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_reserved   3
+
+/***************************************************************************
+ *DESC_WORD4 - MEM DMA Descriptor Word 4
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD4 :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_SHIFT                    16
+
+/* MEM_DMA :: DESC_WORD4 :: SCRAM_CTRL_RSV [15:14] */
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_MASK                0x0000c000
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_SHIFT               14
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_END [13:13] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK                  0x00002000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_SHIFT                 13
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_START [12:12] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK                0x00001000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_SHIFT               12
+
+/* MEM_DMA :: DESC_WORD4 :: SG_ENABLE [11:11] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK                     0x00000800
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_SHIFT                    11
+
+/* MEM_DMA :: DESC_WORD4 :: ENC_DEC_INIT [10:10] */
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_MASK                  0x00000400
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_SHIFT                 10
+
+/* MEM_DMA :: DESC_WORD4 :: MODE_SEL [09:08] */
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_MASK                      0x00000300
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT                     8
+
+/* MEM_DMA :: DESC_WORD4 :: KEY_SELECT [07:00] */
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_MASK                    0x000000ff
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD5 - MEM DMA Descriptor Word 5
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD5 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD6 - MEM DMA Descriptor Word 6
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD6 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD7 - MEM DMA Descriptor Word 7
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD7 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *RAAGA_REGSET_DSP_CFG
+ ***************************************************************************/
+/***************************************************************************
+ *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK     0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT    0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo   2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono     1
+
+/***************************************************************************
+ *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
+
+/***************************************************************************
+ *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off     0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On      1
+
+/***************************************************************************
+ *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt  1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo  2
+
+/***************************************************************************
+ *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK       0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT      0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono    1
+
+/***************************************************************************
+ *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK   0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *RDC
+ ***************************************************************************/
+/***************************************************************************
+ *RUL - RUL Command.
+ ***************************************************************************/
+/* RDC :: RUL :: opcode [31:24] */
+#define BCHP_RDC_RUL_opcode_MASK                                   0xff000000
+#define BCHP_RDC_RUL_opcode_SHIFT                                  24
+#define BCHP_RDC_RUL_opcode_NOP                                    0
+#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM                          1
+#define BCHP_RDC_RUL_opcode_REG_WRITE                              2
+#define BCHP_RDC_RUL_opcode_REG_READ                               3
+#define BCHP_RDC_RUL_opcode_LOAD_IMM                               4
+#define BCHP_RDC_RUL_opcode_WINDOW_WRITE                           5
+#define BCHP_RDC_RUL_opcode_BLOCK_WRITE                            6
+#define BCHP_RDC_RUL_opcode_WINDOW_COPY                            7
+#define BCHP_RDC_RUL_opcode_BLOCK_COPY                             8
+#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK                        9
+#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW                        10
+#define BCHP_RDC_RUL_opcode_AND                                    11
+#define BCHP_RDC_RUL_opcode_AND_IMM                                12
+#define BCHP_RDC_RUL_opcode_OR                                     13
+#define BCHP_RDC_RUL_opcode_OR_IMM                                 14
+#define BCHP_RDC_RUL_opcode_XOR                                    15
+#define BCHP_RDC_RUL_opcode_XOR_IMM                                16
+#define BCHP_RDC_RUL_opcode_NOT                                    17
+#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT                           18
+#define BCHP_RDC_RUL_opcode_SUM                                    19
+#define BCHP_RDC_RUL_opcode_SUM_IMM                                20
+#define BCHP_RDC_RUL_opcode_COND_SKIP                              21
+#define BCHP_RDC_RUL_opcode_SKIP                                   22
+#define BCHP_RDC_RUL_opcode_EXIT                                   23
+#define BCHP_RDC_RUL_opcode_PLACEHOLDER                            255
+
+/* RDC :: RUL :: reserved0 [23:23] */
+#define BCHP_RDC_RUL_reserved0_MASK                                0x00800000
+#define BCHP_RDC_RUL_reserved0_SHIFT                               23
+
+/* union - case rdc_args [22:00] */
+/* RDC :: RUL :: rdc_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_rdc_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: rdc_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_rdc_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_rdc_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: rdc_args :: src2 [11:06] */
+#define BCHP_RDC_RUL_rdc_args_src2_MASK                            0x00000fc0
+#define BCHP_RDC_RUL_rdc_args_src2_SHIFT                           6
+
+/* RDC :: RUL :: rdc_args :: dest [05:00] */
+#define BCHP_RDC_RUL_rdc_args_dest_MASK                            0x0000003f
+#define BCHP_RDC_RUL_rdc_args_dest_SHIFT                           0
+
+/* union - case reg_args [22:00] */
+/* RDC :: RUL :: reg_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_reg_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_reg_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: reg_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_reg_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_reg_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: reg_args :: count [11:00] */
+#define BCHP_RDC_RUL_reg_args_count_MASK                           0x00000fff
+#define BCHP_RDC_RUL_reg_args_count_SHIFT                          0
+
+/***************************************************************************
+ *XPT_PB
+ ***************************************************************************/
+/***************************************************************************
+ *DESCRIPTOR_ABSTRACT - Playback Linked-List Descriptor Abstract
+ ***************************************************************************/
+/* XPT_PB :: DESCRIPTOR_ABSTRACT :: DESCRIPTOR_FORMAT [31:00] */
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_MASK     0xffffffff
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_SHIFT    0
+
+/***************************************************************************
+ *DESC_0 - Playback Linked-List Descriptor Word 0
+ ***************************************************************************/
+/* XPT_PB :: DESC_0 :: PB_BUFFER_START_ADDR [31:00] */
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_MASK               0xffffffff
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_SHIFT              0
+
+/***************************************************************************
+ *DESC_1 - Playback Linked-List Descriptor Word 1
+ ***************************************************************************/
+/* XPT_PB :: DESC_1 :: PB_BUFFER_LENGTH [31:00] */
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_MASK                   0xffffffff
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_SHIFT                  0
+
+/***************************************************************************
+ *DESC_2 - Playback Linked-List Descriptor Word 2
+ ***************************************************************************/
+/* XPT_PB :: DESC_2 :: PB_INTERRUPT_ENABLE [31:31] */
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_MASK                0x80000000
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_SHIFT               31
+
+/* XPT_PB :: DESC_2 :: PB_FORCE_RESYNC [30:30] */
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_MASK                    0x40000000
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_SHIFT                   30
+
+/* XPT_PB :: DESC_2 :: PB_HOST_DATA_INS_EN [29:29] */
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_MASK                0x20000000
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_SHIFT               29
+
+/* XPT_PB :: DESC_2 :: reserved0 [28:28] */
+#define BCHP_XPT_PB_DESC_2_reserved0_MASK                          0x10000000
+#define BCHP_XPT_PB_DESC_2_reserved0_SHIFT                         28
+
+/* XPT_PB :: DESC_2 :: PB_DESC_TAG_ID [27:24] */
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_MASK                     0x0f000000
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_SHIFT                    24
+
+/* XPT_PB :: DESC_2 :: reserved1 [23:00] */
+#define BCHP_XPT_PB_DESC_2_reserved1_MASK                          0x00ffffff
+#define BCHP_XPT_PB_DESC_2_reserved1_SHIFT                         0
+
+/***************************************************************************
+ *DESC_3 - Playback Linked-List Descriptor Word 3
+ ***************************************************************************/
+/* XPT_PB :: DESC_3 :: PB_NEXT_DESC_ADDR [31:04] */
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_MASK                  0xfffffff0
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_SHIFT                 4
+
+/* XPT_PB :: DESC_3 :: reserved0 [03:01] */
+#define BCHP_XPT_PB_DESC_3_reserved0_MASK                          0x0000000e
+#define BCHP_XPT_PB_DESC_3_reserved0_SHIFT                         1
+
+/* XPT_PB :: DESC_3 :: PB_LAST_DESC_IND [00:00] */
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_MASK                   0x00000001
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_SHIFT                  0
+
+/***************************************************************************
+ *XPT_RAVE
+ ***************************************************************************/
+/***************************************************************************
+ *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
+
+/***************************************************************************
+ *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
+
+/***************************************************************************
+ *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
+ ***************************************************************************/
+/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
+
+#endif /* #ifndef BCHP_COMMON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_ddr40_phy_control_regs_0.h b/include/linux/brcmstb/7358a0/bchp_ddr40_phy_control_regs_0.h
new file mode 100644
index 0000000..2c04cab
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_ddr40_phy_control_regs_0.h
@@ -0,0 +1,1490 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:38:50 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_ddr40_phy_control_regs_0.h $
+ * 
+ * Hydra_Software_Devel/3   9/20/11 11:43a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_CONTROL_REGS_0 - DDR40 DDR40 physical interface control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION   0x003b6000 /* Address & Control revision register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL 0x003b6004 /* PHY clock power management control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS 0x003b6010 /* PHY PLL status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG 0x003b6014 /* PHY PLL configuration register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL 0x003b6018 /* PHY PLL control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS 0x003b601c /* PHY PLL dividers control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL 0x003b6020 /* Aux Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL 0x003b6030 /* Address & Control coarse VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL 0x003b6034 /* Address & Control fine VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL 0x003b6038 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL 0x003b603c /* PVT Compensation control and status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL 0x003b6040 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS 0x003b6044 /* PHY Auto Init rd_data_dly result register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE 0x003b6048 /* PHY VDL calibration control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS 0x003b604c /* PHY VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS 0x003b6050 /* PHY DQ VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS 0x003b6054 /* PHY Write Channel VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS 0x003b6058 /* PHY Read Enable VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL 0x003b605c /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS 0x003b6060 /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS 0x003b6064 /* Virtual VTT Connections register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE 0x003b6068 /* Virtual VTT Override register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL 0x003b606c /* VREF DAC Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL 0x003b6070 /* PhyBist Control Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED 0x003b6074 /* PhyBist Seed Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS 0x003b6078 /* PhyBist General Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS 0x003b607c /* PhyBist Per-Bit Control Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS 0x003b6080 /* PhyBist Per-Bit DQ Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS 0x003b6084 /* PhyBist Per-Bit DM and CK Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG 0x003b6090 /* DRAM Command Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0  0x003b6094 /* Mode Register 0 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1  0x003b6098 /* Mode Register 1 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2  0x003b609c /* Mode Register 2 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3  0x003b60a0 /* Mode Register 3 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL 0x003b60a4 /* Standby Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL 0x003b60b0 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2 0x003b60b4 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS 0x003b60b8 /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2 0x003b60bc /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE 0x003b60c0 /* Freeze-on-error enable register */
+
+/***************************************************************************
+ *REVISION - Address & Control revision register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_MASK      0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_SHIFT     16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_MASK          0x0000ff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_SHIFT         8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_DEFAULT       64
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_MASK          0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_DEFAULT       4
+
+/***************************************************************************
+ *CLK_PM_CTRL - PHY clock power management control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_MASK   0xfffffffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_SHIFT  1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_DEFAULT 0
+
+/***************************************************************************
+ *PLL_STATUS - PHY PLL status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_MASK    0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_SHIFT   27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK_LOST [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_MASK    0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_SHIFT   26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: DDR_MHZ [25:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_MASK      0x03ffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_SHIFT     14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_4X [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: STATUS [12:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_MASK       0x00001ffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_SHIFT      1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_MASK         0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_CONFIG - PHY PLL configuration register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved0 [31:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_MASK    0xffffff80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_SHIFT   7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LP40_PLL_POST_RESET [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET_POST_DIV [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LDO_CTRL [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_MASK     0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_SHIFT    3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_DEFAULT  2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved1 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_MASK    0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_SHIFT   2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_MASK        0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_SHIFT       1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_DEFAULT     1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PWRDN [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_MASK        0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_SHIFT       0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_DEFAULT     0
+
+/***************************************************************************
+ *PLL_CONTROL - PHY PLL control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: reserved0 [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_SHIFT  31
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_kp [30:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_MASK        0x78000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_SHIFT       27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_DEFAULT     10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ki [26:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_MASK        0x07000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_SHIFT       24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_DEFAULT     3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ka [23:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_MASK        0x00e00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_SHIFT       21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_DEFAULT     3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: PLL_CONTROL [20:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_MASK 0x001fffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_DEFAULT 0
+
+/***************************************************************************
+ *PLL_DIVIDERS - PHY PLL dividers control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_MASK  0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_SHIFT 16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_HI [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_MASK 0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_LO [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: POST_DIV [13:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_MASK   0x00003800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_SHIFT  11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_DEFAULT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: PDIV [10:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_MASK       0x00000700
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_SHIFT      8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_DEFAULT    4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_MASK       0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_DEFAULT    32
+
+/***************************************************************************
+ *AUX_CONTROL - Aux Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved0 [31:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_MASK   0xfffffc00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_SHIFT  10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_cs [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_MASK       0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_SHIFT      7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_ad [06:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_MASK       0x00000070
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_SHIFT      4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_odt [03:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_MASK      0x0000000e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_SHIFT     1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: override [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_CTL - Address & Control coarse VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BIT_CTL - Address & Control fine VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_SHIFT  31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved0 [30:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ffffe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: rxenb [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_MASK  0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved1 [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_SHIFT 7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_reb [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_DEFAULT 0
+
+/***************************************************************************
+ *ZQ_PVT_COMP_CTL - PVT Compensation control and status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: update_mode [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_done [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_done [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_done [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: auto_sample_en [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_MASK 0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_en [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_ovr_en [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_ovr_en [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_comp [17:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_MASK 0x00038000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_comp [14:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_MASK 0x00007000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [11:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_MASK 0x00000e00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [08:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_MASK 0x000001c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_DEFAULT 0
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: auto_oeb [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a15 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_MASK  0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a14 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_MASK  0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a13 [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_MASK  0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_aux [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_MASK  0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: half_strength [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_MASK     0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_SHIFT    2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_MASK  0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_MASK     0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_SHIFT    0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_DEFAULT  0
+
+/***************************************************************************
+ *VDL_RD_DATA_DLY_STATUS - PHY Auto Init rd_data_dly result register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_SHIFT 12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: auto_init_state [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_MASK 0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_max [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_min [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_DEFAULT 7
+
+/***************************************************************************
+ *VDL_CALIBRATE - PHY VDL calibration control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_SHIFT 29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: use_straps [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: auto_init [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: skip_rst [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_MASK  0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_SHIFT 26
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: exit_in_sr [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_dly_cal [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_refresh [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_wr_dq [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: dq0_only [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_MASK  0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_mr_mpr [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_cal [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_MASK   0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_SHIFT  19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_en_cal [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_clocks [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_pair [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_steps [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_auto [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_ftm [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_phybist [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_byte [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_clocks [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_test [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_always [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_once [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_fast [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_DEFAULT 0
+
+/***************************************************************************
+ *VDL_CALIB_STATUS - PHY VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_MASK 0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_fail [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_MASK 0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_SHIFT 29
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_done [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_rd_data_dly_error [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_read_en_error [26:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_MASK 0x07800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_error [22:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_MASK 0x00780000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_sel [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_total [11:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_MASK 0x00000ffc
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_DEFAULT 1
+
+/***************************************************************************
+ *VDL_DQ_CALIB_STATUS - PHY DQ VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_total [25:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_MASK 0x03ff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_clocks [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_mode [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VDL_WR_CHAN_CALIB_STATUS - PHY Write Channel VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VDL_RD_EN_CALIB_STATUS - PHY Read Enable VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: low_vtt [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: high_vtt [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: error_reset [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_ctl_idle [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cs_idle [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cke_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error [18:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_MASK 0x0007fff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_low [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_high [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ready [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_DEFAULT 16777215
+
+/***************************************************************************
+ *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_DEFAULT 262143
+
+/***************************************************************************
+ *VREF_DAC_CONTROL - VREF DAC Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK1_GT_INT [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK0_GT_INT [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_GT_INT [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: EXT_GT_INT [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_TESTOUT_MUX_CTL [16:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_MASK 0x00018000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TEST [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_MASK   0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_SHIFT  14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_MASK   0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_SHIFT  13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_MASK   0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_SHIFT  12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_MASK   0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_SHIFT  6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_DEFAULT 32
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_MASK   0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_SHIFT  0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_DEFAULT 32
+
+/***************************************************************************
+ *PHYBIST_CNTRL - PhyBist Control Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_error_sel [13:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_MASK 0x00003f00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved1 [07:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_MASK 0x000000e0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_SHIFT 5
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: bench_mode [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_dat_error [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_ctl_error [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: int_loopback [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_DEFAULT 0
+
+/***************************************************************************
+ *PHYBIST_SEED - PhyBist Seed Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_SEED :: seed [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_MASK       0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_DEFAULT    621693686
+
+/***************************************************************************
+ *PHYBIST_STATUS - PhyBist General Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_pass [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_pass [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_SHIFT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_done [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_done [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: ctl_errors [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_DQ_STATUS - PhyBist Per-Bit DQ Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_STATUS :: dat_errors [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_MASK 0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_MISC_STATUS - PhyBist Per-Bit DM and CK Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: ck_errors [07:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_MASK 0x000000f0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: dm_errors [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_SHIFT 0
+
+/***************************************************************************
+ *COMMAND_REG - DRAM Command Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_MASK   0xfe000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_SHIFT  25
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: aux [24:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_MASK         0x01c00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_SHIFT        22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: we [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_MASK          0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_SHIFT         21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_DEFAULT       0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: cas [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_MASK         0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_SHIFT        20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ras [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_MASK         0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_SHIFT        19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ba [18:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_MASK          0x00070000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_SHIFT         16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_DEFAULT       0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_MASK          0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_DEFAULT       0
+
+/***************************************************************************
+ *MODE_REG0 - Mode Register 0
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG1 - Mode Register 1
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG2 - Mode Register 2
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG3 - Mode Register 3
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_DEFAULT         0
+
+/***************************************************************************
+ *STANDBY_CONTROL - Standby Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_ready [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_exit_pin_en [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_active [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: armed [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_MASK   0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_SHIFT  15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: warmstart [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_ldo_volts [13:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_MASK 0x00003000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_skip_mrs [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_rst_n [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_cke [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: ldo_volts [08:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_MASK 0x00000180
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_DEFAULT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: skip_mrs [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: rst_n [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_MASK   0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_SHIFT  5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: cke [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_MASK     0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_SHIFT    4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_CONTROL - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: reserved0 [31:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_MASK 0xf0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_MASK       0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_SHIFT      16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_MASK  0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_MASK 0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_MASK     0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_SHIFT    12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_MASK      0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_SHIFT     11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_MASK      0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_SHIFT     8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_CONTROL2 - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_MASK     0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_SHIFT    20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_MASK       0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_SHIFT      17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_MASK       0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_SHIFT      12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_MASK      0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_SHIFT     7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_MASK       0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_DEFAULT    0
+
+/***************************************************************************
+ *STRAP_STATUS - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_MASK  0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_reg [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_MASK   0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_SHIFT  29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_memc [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_MASK  0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_MASK        0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_SHIFT       16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_MASK   0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_SHIFT  14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_MASK      0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_SHIFT     12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_MASK       0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_SHIFT      11
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_SHIFT 10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_MASK       0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_SHIFT      8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_MASK  0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_SHIFT 0
+
+/***************************************************************************
+ *STRAP_STATUS2 - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_MASK      0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_SHIFT     20
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_MASK        0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_SHIFT       17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_MASK        0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_SHIFT       12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_MASK       0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_SHIFT      7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_MASK        0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_SHIFT       0
+
+/***************************************************************************
+ *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl1 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl0 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl1 [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl0 [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_DEFAULT 0
+
+#endif /* #ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_ddr40_phy_word_lane_0_0.h b/include/linux/brcmstb/7358a0/bchp_ddr40_phy_word_lane_0_0.h
new file mode 100644
index 0000000..0cc131a
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_ddr40_phy_word_lane_0_0.h
@@ -0,0 +1,3259 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:39:04 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_ddr40_phy_word_lane_0_0.h $
+ * 
+ * Hydra_Software_Devel/3   9/20/11 11:43a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_0_0 - DDR40 DDR40 word lane #0 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN 0x003b6200 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W 0x003b6204 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P 0x003b6208 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N 0x003b620c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W 0x003b6210 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W 0x003b6214 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W 0x003b6218 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W 0x003b621c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W 0x003b6220 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W 0x003b6224 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W 0x003b6228 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W 0x003b622c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W 0x003b6230 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003b6234 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003b6238 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003b623c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003b6240 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003b6244 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003b6248 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003b624c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003b6250 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003b6254 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003b6258 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003b625c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003b6260 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003b6264 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003b6268 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003b626c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003b6270 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003b6274 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W 0x003b62a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P 0x003b62a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N 0x003b62ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W 0x003b62b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W 0x003b62b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W 0x003b62b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W 0x003b62bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W 0x003b62c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W 0x003b62c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W 0x003b62c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W 0x003b62cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W 0x003b62d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003b62d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003b62d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003b62dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003b62e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003b62e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003b62e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003b62ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003b62f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003b62f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003b62f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003b62fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003b6300 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003b6304 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003b6308 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003b630c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003b6310 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003b6314 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x003b6328 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x003b632c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003b6330 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003b6334 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W 0x003b6338 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003b633c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x003b6348 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x003b634c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003b6350 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003b6354 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W 0x003b6358 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003b635c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY 0x003b6360 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL 0x003b6364 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0 0x003b6370 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1 0x003b6374 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2 0x003b6378 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3 0x003b637c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0 0x003b6380 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1 0x003b6384 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2 0x003b6388 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3 0x003b638c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS 0x003b6390 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR 0x003b6394 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL 0x003b63a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL 0x003b63a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE 0x003b63a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE 0x003b63ac /* Write cycle preamble control register */
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_RD_EN - Read Enable Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *READ_DATA_DLY - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_MASK  0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: rd_data_dly [02:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_MASK 0x00000007
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_DEFAULT 1
+
+/***************************************************************************
+ *READ_CONTROL - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_MASK   0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_SHIFT  3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_enable [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_te_adj [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_le_adj [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_DEFAULT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status1 [07:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_MASK 0x000000f0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status0 [03:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_MASK 0x0000000f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_DEFAULT 0
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: clear [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_DEFAULT 0
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_MASK    0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_SHIFT   31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_SHIFT 24
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_MASK 0x00c00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_SHIFT 22
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_MASK 0x00300000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_SHIFT 20
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00080000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 19
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00040000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_SHIFT 18
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_MASK  0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_MASK  0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00008000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 15
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00004000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 14
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00002000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 13
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00001000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 12
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_MASK 0x00000008
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_DEFAULT 0
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: reserved0 [31:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_MASK  0xfffff800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_SHIFT 11
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_MASK    0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_SHIFT   6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_MASK      0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_SHIFT     2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_DEFAULT   0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_MASK   0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_SHIFT  1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_MASK      0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_SHIFT     0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_DEFAULT   0
+
+/***************************************************************************
+ *CLOCK_PAD_DISABLE - Clock pad disable register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_DEFAULT 0
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffc
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_SHIFT 2
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: long [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_MASK    0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_SHIFT   1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: mode [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_DEFAULT 0
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_ebi.h b/include/linux/brcmstb/7358a0/bchp_ebi.h
new file mode 100644
index 0000000..3b89081
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_ebi.h
@@ -0,0 +1,1472 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:38:29 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_ebi.h $
+ * 
+ * Hydra_Software_Devel/3   9/20/11 11:46a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EBI_H__
+#define BCHP_EBI_H__
+
+/***************************************************************************
+ *EBI - EBI Registers
+ ***************************************************************************/
+#define BCHP_EBI_CS_BASE_0                       0x00410800 /* EBI CS Base 0 Register */
+#define BCHP_EBI_CS_CONFIG_0                     0x00410804 /* EBI CS Config 0 Register */
+#define BCHP_EBI_CS_BASE_1                       0x00410808 /* EBI CS Base 1 Register */
+#define BCHP_EBI_CS_CONFIG_1                     0x0041080c /* EBI CS Config 1 Register */
+#define BCHP_EBI_CS_BASE_2                       0x00410810 /* EBI CS Base 2 Register */
+#define BCHP_EBI_CS_CONFIG_2                     0x00410814 /* EBI CS Config 2 Register */
+#define BCHP_EBI_CS_BASE_3                       0x00410818 /* EBI CS Base 3 Register */
+#define BCHP_EBI_CS_CONFIG_3                     0x0041081c /* EBI CS Config 3 Register */
+#define BCHP_EBI_CS_BASE_4                       0x00410820 /* EBI CS Base 4 Register */
+#define BCHP_EBI_CS_CONFIG_4                     0x00410824 /* EBI CS Config 4 Register */
+#define BCHP_EBI_BURST_CFG_0                     0x00410840 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_1                     0x00410844 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_2                     0x00410848 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_3                     0x0041084c /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_4                     0x00410850 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_ECR                             0x00410900 /* EBI Configuration Register */
+#define BCHP_EBI_CS_TRISTATE_CFG                 0x00410918 /* EBI CS Tristate Configuration Register */
+#define BCHP_EBI_TA_CFG                          0x0041091c /* EBI TA Configuration Register */
+#define BCHP_EBI_CS_SPI_SELECT                   0x00410920 /* SPI CS Select */
+#define BCHP_EBI_ARRAY_ADDRESS                   0x004109f0 /* EBI Data Array Address */
+
+/***************************************************************************
+ *CS_BASE_0 - EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_0 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_0_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT                         13
+
+/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_0_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_0 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_0_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_0_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_0 - EBI CS Config 0 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_0_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT                       1
+
+/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_0_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_0 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_0_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_0_le_SHIFT                              10
+
+/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_0_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_0_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT                       4
+
+/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_0_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT                        1
+
+/***************************************************************************
+ *CS_BASE_1 - EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_1 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_1_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_1_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_1 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_1_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_1_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_1_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_1 - EBI CS Config 1 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_1_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_1_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_1 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_1_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_1_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_1_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_1_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_1_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_2 - EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_2 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_2_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_2_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_2 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_2_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_2_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_2_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_2 - EBI CS Config 2 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_2_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_2_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_2 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_2_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_2_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_2_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_2_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_2_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_3 - EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_3 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_3_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_3_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_3 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_3_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_3_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_3_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_3 - EBI CS Config 3 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_3_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_3_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_3 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_3_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_3_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_3_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_3_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_3_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_4 - EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_4 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_4_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_4_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_4 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_4_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_4_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_4_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_4 - EBI CS Config 4 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_4_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_4_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_4 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_4_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_4_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_4_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_4_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_4_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT                        0
+
+/***************************************************************************
+ *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_0_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_0_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_0 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_0_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_0_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_0_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_0_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_0_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_1_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_1_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_1 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_1_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_1_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_1_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_1_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_1_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_2_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_2_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_2 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_2_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_2_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_2_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_2_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_2_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_3_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_3_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_3 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_3_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_3_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_3_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_3_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_3_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_4_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_4_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_4 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_4_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_4_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_4_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_4_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_4_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *ECR - EBI Configuration Register
+ ***************************************************************************/
+/* EBI :: ECR :: reserved0 [31:28] */
+#define BCHP_EBI_ECR_reserved0_MASK                                0xf0000000
+#define BCHP_EBI_ECR_reserved0_SHIFT                               28
+
+/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK                            0x08000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT                           27
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT                         0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only  1
+
+/* EBI :: ECR :: reserved1 [26:26] */
+#define BCHP_EBI_ECR_reserved1_MASK                                0x04000000
+#define BCHP_EBI_ECR_reserved1_SHIFT                               26
+
+/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK                          0x02000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT                         25
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT                       0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10         0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00         1
+
+/* EBI :: ECR :: reserved2 [24:11] */
+#define BCHP_EBI_ECR_reserved2_MASK                                0x01fff800
+#define BCHP_EBI_ECR_reserved2_SHIFT                               11
+
+/* EBI :: ECR :: timeout_count [10:00] */
+#define BCHP_EBI_ECR_timeout_count_MASK                            0x000007ff
+#define BCHP_EBI_ECR_timeout_count_SHIFT                           0
+#define BCHP_EBI_ECR_timeout_count_DEFAULT                         1024
+
+/***************************************************************************
+ *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
+ ***************************************************************************/
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK             0x80000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT            31
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK             0x40000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT            30
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK             0x20000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT            29
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK             0x10000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT            28
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK            0x08000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT           27
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT         0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK            0x04000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT           26
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT         0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK         0x02000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT        25
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT      0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK         0x01000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT        24
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT      0
+
+/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:05] */
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK                    0x00ffffe0
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT                   5
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK             0x00000010
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT            4
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK             0x00000008
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT            3
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK             0x00000004
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT            2
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK             0x00000002
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT            1
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK             0x00000001
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT            0
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT          0
+
+/***************************************************************************
+ *TA_CFG - EBI TA Configuration Register
+ ***************************************************************************/
+/* EBI :: TA_CFG :: reserved0 [31:04] */
+#define BCHP_EBI_TA_CFG_reserved0_MASK                             0xfffffff0
+#define BCHP_EBI_TA_CFG_reserved0_SHIFT                            4
+
+/* EBI :: TA_CFG :: use_ta3 [03:03] */
+#define BCHP_EBI_TA_CFG_use_ta3_MASK                               0x00000008
+#define BCHP_EBI_TA_CFG_use_ta3_SHIFT                              3
+#define BCHP_EBI_TA_CFG_use_ta3_DEFAULT                            1
+
+/* EBI :: TA_CFG :: use_ta2 [02:02] */
+#define BCHP_EBI_TA_CFG_use_ta2_MASK                               0x00000004
+#define BCHP_EBI_TA_CFG_use_ta2_SHIFT                              2
+#define BCHP_EBI_TA_CFG_use_ta2_DEFAULT                            0
+
+/* EBI :: TA_CFG :: use_ta1 [01:01] */
+#define BCHP_EBI_TA_CFG_use_ta1_MASK                               0x00000002
+#define BCHP_EBI_TA_CFG_use_ta1_SHIFT                              1
+#define BCHP_EBI_TA_CFG_use_ta1_DEFAULT                            1
+
+/* EBI :: TA_CFG :: reserved1 [00:00] */
+#define BCHP_EBI_TA_CFG_reserved1_MASK                             0x00000001
+#define BCHP_EBI_TA_CFG_reserved1_SHIFT                            0
+
+/***************************************************************************
+ *CS_SPI_SELECT - SPI CS Select
+ ***************************************************************************/
+/* EBI :: CS_SPI_SELECT :: reserved0 [31:16] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK                      0xffff0000
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT                     16
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_7_USES_SPI [15:15] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_MASK              0x00008000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_SHIFT             15
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK              0x00004000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT             14
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK              0x00002000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT             13
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK              0x00001000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT             12
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK              0x00000800
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT             11
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK              0x00000400
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT             10
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK              0x00000200
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT             9
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK              0x00000100
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT             8
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_7_SEL [07:07] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_MASK               0x00000080
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_SHIFT              7
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK               0x00000040
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT              6
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK               0x00000020
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT              5
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK               0x00000010
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT              4
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK               0x00000008
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT              3
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK               0x00000004
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT              2
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK               0x00000002
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT              1
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK               0x00000001
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT              0
+
+/***************************************************************************
+ *ARRAY_ADDRESS - EBI Data Array Address
+ ***************************************************************************/
+/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK                        0xfffffe00
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT                       9
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT                     0
+
+/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK                      0x000001f8
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT                     3
+
+/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK                         0x00000007
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT                        0
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT                      0
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE                            0x00410a00
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_START                           0
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_END                             127
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE                    32
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+/* EBI :: DATA_ARRAYi :: WORD [31:00] */
+#define BCHP_EBI_DATA_ARRAYi_WORD_MASK                             0xffffffff
+#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT                            0
+
+
+#endif /* #ifndef BCHP_EBI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_hif_cpu_intr1.h b/include/linux/brcmstb/7358a0/bchp_hif_cpu_intr1.h
new file mode 100644
index 0000000..5a0b103
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_hif_cpu_intr1.h
@@ -0,0 +1,1931 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:46:47 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_hif_cpu_intr1.h $
+ * 
+ * Hydra_Software_Devel/7   9/20/11 11:54a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_INTR1_H__
+#define BCHP_HIF_CPU_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_INTR1 - HIF CPU Thread Processor 0 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS        0x00411400 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS        0x00411404 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS        0x00411408 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS   0x0041140c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS   0x00411410 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS   0x00411414 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET      0x00411418 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET      0x0041141c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET      0x00411420 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR    0x00411424 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR    0x00411428 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR    0x0041142c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK    0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT   31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK        0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT       30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK    0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT   29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_MASK       0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_SHIFT      28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_DEFAULT    0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK  0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK  0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_MASK        0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_SHIFT       23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK     0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT    7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK     0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT    6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK     0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT    5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK     0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT    4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK     0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT    3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK     0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT    2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK        0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT       1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK        0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT       0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT     0
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK    0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT   28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK    0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT   27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK     0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT    26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK   0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT  24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK    0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT   22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_MASK   0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_SHIFT  20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK     0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT    18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK    0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT   17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK        0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT       16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_MASK   0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_SHIFT  14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_MASK   0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_SHIFT  13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_MASK   0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_SHIFT  12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_MASK   0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_SHIFT  11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_MASK  0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_MASK  0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK      0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT     5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT   0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK    0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT   4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_MASK     0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_SHIFT    2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_MASK       0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_SHIFT      1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_DEFAULT    0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_MASK       0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_SHIFT      0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_DEFAULT    0
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_21_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_MASK   0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_SHIFT  31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: MCIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_MCIF_CPU_INTR_MASK       0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_MCIF_CPU_INTR_SHIFT      30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_MCIF_CPU_INTR_DEFAULT    0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_20_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_20_CPU_INTR_MASK   0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_20_CPU_INTR_SHIFT  29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_20_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_19_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_19_CPU_INTR_MASK   0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_19_CPU_INTR_SHIFT  28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_19_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: reserved0 [27:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved0_MASK           0x0f800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved0_SHIFT          23
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_18_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_MASK   0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_SHIFT  22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_17_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_MASK   0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_SHIFT  21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_MASK     0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_SHIFT    20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: reserved1 [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved1_MASK           0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved1_SHIFT          18
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK    0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT   16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK    0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT   15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK   0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT  14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK    0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT   12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK     0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT    11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK        0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT       10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_MASK   0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_SHIFT  9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_MASK   0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_SHIFT  8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK   0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT  30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_MASK   0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_SHIFT  23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK   0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT  16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_21_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: MCIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_MCIF_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_MCIF_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_MCIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_20_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_20_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_20_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_20_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_19_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_19_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_19_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_19_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: reserved0 [27:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved0_MASK      0x0f800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved0_SHIFT     23
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_18_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_17_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: reserved1 [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved1_MASK      0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved1_SHIFT     18
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK   0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT  10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK      0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT     30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_MASK     0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_SHIFT    28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_DEFAULT  1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_MASK      0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_SHIFT     23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK      0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT     1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK      0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT     0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT   1
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK  0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK  0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK   0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT  18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK  0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK      0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT     16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK    0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT   5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK  0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_MASK     0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_SHIFT    1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_DEFAULT  1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_MASK     0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_SHIFT    0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_DEFAULT  1
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_21_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: MCIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_MCIF_CPU_INTR_MASK     0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_MCIF_CPU_INTR_SHIFT    30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_MCIF_CPU_INTR_DEFAULT  1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_20_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_20_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_20_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_20_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_19_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_19_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_19_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_19_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: reserved0 [27:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved0_MASK         0x0f800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved0_SHIFT        23
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_18_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_17_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_MASK   0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_SHIFT  20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: reserved1 [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved1_MASK         0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved1_SHIFT        18
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK  0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK  0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK  0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK   0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT  11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK      0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT     10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_MASK   0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_SHIFT  28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK    0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT   16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK  0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_21_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: MCIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_MCIF_CPU_INTR_MASK   0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_MCIF_CPU_INTR_SHIFT  30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_MCIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_20_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_20_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_20_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_20_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_19_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_19_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_19_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_19_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: reserved0 [27:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved0_MASK       0x0f800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved0_SHIFT      23
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_18_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_17_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: reserved1 [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved1_MASK       0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved1_SHIFT      18
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK    0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT   10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_DEFAULT 1
+
+#endif /* #ifndef BCHP_HIF_CPU_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_hif_intr2.h b/include/linux/brcmstb/7358a0/bchp_hif_intr2.h
new file mode 100644
index 0000000..5b3dff8
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_hif_intr2.h
@@ -0,0 +1,975 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:42:55 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_hif_intr2.h $
+ * 
+ * Hydra_Software_Devel/2   9/20/11 11:54a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_INTR2_H__
+#define BCHP_HIF_INTR2_H__
+
+/***************************************************************************
+ *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_INTR2_CPU_STATUS                0x00411000 /* CPU interrupt Status Register */
+#define BCHP_HIF_INTR2_CPU_SET                   0x00411004 /* CPU interrupt Set Register */
+#define BCHP_HIF_INTR2_CPU_CLEAR                 0x00411008 /* CPU interrupt Clear Register */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS           0x0041100c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_CPU_MASK_SET              0x00411010 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR            0x00411014 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_INTR2_PCI_STATUS                0x00411018 /* PCI interrupt Status Register */
+#define BCHP_HIF_INTR2_PCI_SET                   0x0041101c /* PCI interrupt Set Register */
+#define BCHP_HIF_INTR2_PCI_CLEAR                 0x00411020 /* PCI interrupt Clear Register */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS           0x00411024 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_PCI_MASK_SET              0x00411028 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR            0x0041102c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK                   0x0000fffe
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT               0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_MASK              0x00080000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_SHIFT             19
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: CPU_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK                      0x0000fffe
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: CPU_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_MASK            0x00080000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_SHIFT           19
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK                    0x0000fffe
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK              0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 1
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT          1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_MASK         0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_SHIFT        19
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK                 0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    1
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_MASK       0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_SHIFT      19
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK               0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  1
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK                   0x0000fffe
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT               0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_MASK              0x00080000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_SHIFT             19
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: PCI_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK                      0x0000fffe
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: PCI_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_MASK            0x00080000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_SHIFT           19
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK                    0x0000fffe
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK              0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 1
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT          1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_MASK         0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_SHIFT        19
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK                 0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    1
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_MASK       0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_SHIFT      19
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK               0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  1
+
+#endif /* #ifndef BCHP_HIF_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_hif_mspi.h b/include/linux/brcmstb/7358a0/bchp_hif_mspi.h
new file mode 100644
index 0000000..a5a98b3
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_hif_mspi.h
@@ -0,0 +1,1214 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:44:08 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_hif_mspi.h $
+ * 
+ * Hydra_Software_Devel/2   9/20/11 11:55a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_MSPI_H__
+#define BCHP_HIF_MSPI_H__
+
+/***************************************************************************
+ *HIF_MSPI - Public MSPI Registers
+ ***************************************************************************/
+#define BCHP_HIF_MSPI_SPCR0_LSB                  0x00413200 /* SPCR0_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR0_MSB                  0x00413204 /* SPCR0_MSB Register */
+#define BCHP_HIF_MSPI_SPCR1_LSB                  0x00413208 /* SPCR1_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR1_MSB                  0x0041320c /* SPCR1_MSB REGISTER */
+#define BCHP_HIF_MSPI_NEWQP                      0x00413210 /* NEWQP REGISTER */
+#define BCHP_HIF_MSPI_ENDQP                      0x00413214 /* ENDQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR2                      0x00413218 /* SPCR2 REGISTER */
+#define BCHP_HIF_MSPI_MSPI_STATUS                0x00413220 /* MSPI STATUS REGISTER */
+#define BCHP_HIF_MSPI_CPTQP                      0x00413224 /* CPTQP REGISTER */
+#define BCHP_HIF_MSPI_TXRAM00                    0x00413240 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM01                    0x00413244 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM02                    0x00413248 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM03                    0x0041324c /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM04                    0x00413250 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM05                    0x00413254 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM06                    0x00413258 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM07                    0x0041325c /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM08                    0x00413260 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM09                    0x00413264 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM10                    0x00413268 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM11                    0x0041326c /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM12                    0x00413270 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM13                    0x00413274 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM14                    0x00413278 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM15                    0x0041327c /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM16                    0x00413280 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM17                    0x00413284 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM18                    0x00413288 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM19                    0x0041328c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM20                    0x00413290 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM21                    0x00413294 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM22                    0x00413298 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM23                    0x0041329c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM24                    0x004132a0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM25                    0x004132a4 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM26                    0x004132a8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM27                    0x004132ac /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM28                    0x004132b0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM29                    0x004132b4 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM30                    0x004132b8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_TXRAM31                    0x004132bc /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM00                    0x004132c0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM01                    0x004132c4 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM02                    0x004132c8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM03                    0x004132cc /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM04                    0x004132d0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM05                    0x004132d4 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM06                    0x004132d8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM07                    0x004132dc /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM08                    0x004132e0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM09                    0x004132e4 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM10                    0x004132e8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM11                    0x004132ec /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM12                    0x004132f0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM13                    0x004132f4 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM14                    0x004132f8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM15                    0x004132fc /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM16                    0x00413300 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM17                    0x00413304 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM18                    0x00413308 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM19                    0x0041330c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM20                    0x00413310 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM21                    0x00413314 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM22                    0x00413318 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM23                    0x0041331c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM24                    0x00413320 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM25                    0x00413324 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM26                    0x00413328 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM27                    0x0041332c /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM28                    0x00413330 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM29                    0x00413334 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM30                    0x00413338 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM31                    0x0041333c /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_CDRAM00                    0x00413340 /* 8-bit command (queue pointer = 0) */
+#define BCHP_HIF_MSPI_CDRAM01                    0x00413344 /* 8-bit command (queue pointer = 1) */
+#define BCHP_HIF_MSPI_CDRAM02                    0x00413348 /* 8-bit command (queue pointer = 2) */
+#define BCHP_HIF_MSPI_CDRAM03                    0x0041334c /* 8-bit command (queue pointer = 3) */
+#define BCHP_HIF_MSPI_CDRAM04                    0x00413350 /* 8-bit command (queue pointer = 4) */
+#define BCHP_HIF_MSPI_CDRAM05                    0x00413354 /* 8-bit command (queue pointer = 5) */
+#define BCHP_HIF_MSPI_CDRAM06                    0x00413358 /* 8-bit command (queue pointer = 6) */
+#define BCHP_HIF_MSPI_CDRAM07                    0x0041335c /* 8-bit command (queue pointer = 7) */
+#define BCHP_HIF_MSPI_CDRAM08                    0x00413360 /* 8-bit command (queue pointer = 8) */
+#define BCHP_HIF_MSPI_CDRAM09                    0x00413364 /* 8-bit command (queue pointer = 9) */
+#define BCHP_HIF_MSPI_CDRAM10                    0x00413368 /* 8-bit command (queue pointer = a) */
+#define BCHP_HIF_MSPI_CDRAM11                    0x0041336c /* 8-bit command (queue pointer = b) */
+#define BCHP_HIF_MSPI_CDRAM12                    0x00413370 /* 8-bit command (queue pointer = c) */
+#define BCHP_HIF_MSPI_CDRAM13                    0x00413374 /* 8-bit command (queue pointer = d) */
+#define BCHP_HIF_MSPI_CDRAM14                    0x00413378 /* 8-bit command (queue pointer = e) */
+#define BCHP_HIF_MSPI_CDRAM15                    0x0041337c /* 8-bit command (queue pointer = f) */
+#define BCHP_HIF_MSPI_WRITE_LOCK                 0x00413380 /* Control bit to lock group of write commands */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN          0x00413384 /* Debug bit to mask the generation of flush signals from Mspi */
+
+/***************************************************************************
+ *SPCR0_LSB - SPCR0_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK                          0x000000ff
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT                       0
+
+/***************************************************************************
+ *SPCR0_MSB - SPCR0_MSB Register
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_MSB :: MSTR [07:07] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_MASK                          0x00000080
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_SHIFT                         7
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_DEFAULT                       1
+
+/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [06:06] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK               0x00000040
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT              6
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT            0
+
+/* HIF_MSPI :: SPCR0_MSB :: BitS [05:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_MASK                          0x0000003c
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_SHIFT                         2
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_DEFAULT                       0
+
+/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK                          0x00000002
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT                         1
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT                       0
+
+/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK                          0x00000001
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT                       0
+
+/***************************************************************************
+ *SPCR1_LSB - SPCR1_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT                          0
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT                        0
+
+/***************************************************************************
+ *SPCR1_MSB - SPCR1_MSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK                        0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT                       0
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT                     0
+
+/***************************************************************************
+ *NEWQP - NEWQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: NEWQP :: newqp [03:00] */
+#define BCHP_HIF_MSPI_NEWQP_newqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT                            0
+#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT                          0
+
+/***************************************************************************
+ *ENDQP - ENDQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: ENDQP :: endqp [03:00] */
+#define BCHP_HIF_MSPI_ENDQP_endqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT                            0
+#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT                          0
+
+/***************************************************************************
+ *SPCR2 - SPCR2 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK                         0xffffff00
+#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT                        8
+
+/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK                    0x00000080
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT                   7
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT                 0
+
+/* HIF_MSPI :: SPCR2 :: spe [06:06] */
+#define BCHP_HIF_MSPI_SPCR2_spe_MASK                               0x00000040
+#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT                              6
+#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT                            0
+
+/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
+#define BCHP_HIF_MSPI_SPCR2_spifie_MASK                            0x00000020
+#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT                           5
+#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT                         0
+
+/* HIF_MSPI :: SPCR2 :: wren [04:04] */
+#define BCHP_HIF_MSPI_SPCR2_wren_MASK                              0x00000010
+#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT                             4
+#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT                           0
+
+/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
+#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK                              0x00000008
+#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT                             3
+#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT                           0
+
+/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
+#define BCHP_HIF_MSPI_SPCR2_loopq_MASK                             0x00000004
+#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT                            2
+#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT                          0
+
+/* HIF_MSPI :: SPCR2 :: hie [01:01] */
+#define BCHP_HIF_MSPI_SPCR2_hie_MASK                               0x00000002
+#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT                              1
+#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT                            0
+
+/* HIF_MSPI :: SPCR2 :: halt [00:00] */
+#define BCHP_HIF_MSPI_SPCR2_halt_MASK                              0x00000001
+#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT                             0
+#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT                           0
+
+/***************************************************************************
+ *MSPI_STATUS - MSPI STATUS REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK                   0xfffffffc
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT                  2
+
+/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK                       0x00000002
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT                      1
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT                    0
+
+/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK                        0x00000001
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT                       0
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT                     0
+
+/***************************************************************************
+ *CPTQP - CPTQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
+#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT                            0
+#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT                          0
+
+/***************************************************************************
+ *TXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM00_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM01_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM02_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM03_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM04_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM05_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM06_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM07_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM08_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM09_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM10_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM11_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM12_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM13_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM14_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM15_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM16_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM17_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM18_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM19_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM20_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM21_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM22_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM23_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM24_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM25_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM26_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM27_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM28_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM29_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM30_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM31_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM00 - 8-bit command (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM00 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM01 - 8-bit command (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM01 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM02 - 8-bit command (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM02 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM03 - 8-bit command (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM03 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM04 - 8-bit command (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM04 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM05 - 8-bit command (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM05 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM06 - 8-bit command (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM06 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM07 - 8-bit command (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM07 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM08 - 8-bit command (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM08 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM09 - 8-bit command (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM09 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM10 - 8-bit command (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM10 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM11 - 8-bit command (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM11 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM12 - 8-bit command (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM12 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM13 - 8-bit command (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM13 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM14 - 8-bit command (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM14 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM15 - 8-bit command (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM15 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT                          0
+
+/***************************************************************************
+ *WRITE_LOCK - Control bit to lock group of write commands
+ ***************************************************************************/
+/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK                    0xfffffffe
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT                   1
+
+/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK                    0x00000001
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT                   0
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT                 0
+
+/***************************************************************************
+ *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
+ ***************************************************************************/
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK             0xfffffffe
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT            1
+
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK       0x00000001
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT      0
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT    0
+
+#endif /* #ifndef BCHP_HIF_MSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/7358a0/bchp_hif_spi_intr2.h
new file mode 100644
index 0000000..94ca7ec
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_hif_spi_intr2.h
@@ -0,0 +1,567 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:35:53 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_hif_spi_intr2.h $
+ * 
+ * Hydra_Software_Devel/2   9/20/11 11:55a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_SPI_INTR2_H__
+#define BCHP_HIF_SPI_INTR2_H__
+
+/***************************************************************************
+ *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
+ ***************************************************************************/
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS            0x00411d00 /* CPU interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_SET               0x00411d04 /* CPU interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR             0x00411d08 /* CPU interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS       0x00411d0c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET          0x00411d10 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR        0x00411d14 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS            0x00411d18 /* PCI interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_SET               0x00411d1c /* PCI interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR             0x00411d20 /* PCI interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS       0x00411d24 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET          0x00411d28 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR        0x00411d2c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT            0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT               0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT         0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT           0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT            0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT               0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT         0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT           0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_hif_top_ctrl.h b/include/linux/brcmstb/7358a0/bchp_hif_top_ctrl.h
new file mode 100644
index 0000000..4f52679
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_hif_top_ctrl.h
@@ -0,0 +1,527 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:42:41 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_hif_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/4   9/20/11 11:56a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_TOP_CTRL_H__
+#define BCHP_HIF_TOP_CTRL_H__
+
+/***************************************************************************
+ *HIF_TOP_CTRL - HIF Top Control Registers
+ ***************************************************************************/
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2               0x00412418 /* HIF Power Management Control Register:used to control SDIO_0 (CARD) */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL          0x00412400 /* External IRQ Active Level Control Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0               0x00412404 /* HIF Power Management Control0 Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1               0x00412408 /* HIF Power Management Control1 Register */
+#define BCHP_HIF_TOP_CTRL_SCRATCH                0x0041240c /* HIF Scratch Register */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE             0x00412410 /* HIF Decoded Flash Type */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL            0x00412414 /* SPI test port select register */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL               0x0041241c /* HIF HIF_CTRL Register */
+
+/***************************************************************************
+ *PM_CTRL2 - HIF Power Management Control Register:used to control SDIO_0 (CARD)
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved0 [31:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_MASK                  0xff000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_SHIFT                 24
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_MASK 0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_SHIFT 22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_MASK 0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_SHIFT 20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_IN_DRIVE_INACTIVE [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_IN_DRIVE_INACTIVE [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_MASK 0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_SHIFT 16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved1 [15:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_MASK                  0x0000f000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_VOLTAGE_PM_OUT_CTRL [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_LOW    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_HIGH   2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_POWER_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_MASK     0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_SHIFT    8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_DEFAULT  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_LOW      1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_HIGH     2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_LED_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_MASK       0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_SHIFT      6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_MASK      0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_MASK       0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_SHIFT      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_Tristate   3
+
+/***************************************************************************
+ *EXT_IRQ_LEVEL - External IRQ Active Level Control Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: reserved0 [31:15] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_MASK             0xffff8000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_SHIFT            15
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_14_level [14:14] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_MASK      0x00004000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_SHIFT     14
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_13_level [13:13] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_MASK      0x00002000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_SHIFT     13
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_12_level [12:12] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_MASK      0x00001000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_SHIFT     12
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_11_level [11:11] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_MASK      0x00000800
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_SHIFT     11
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_10_level [10:10] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_MASK      0x00000400
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_SHIFT     10
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_09_level [09:09] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_MASK      0x00000200
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_SHIFT     9
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_08_level [08:08] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_MASK      0x00000100
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_SHIFT     8
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_07_level [07:07] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_MASK      0x00000080
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_SHIFT     7
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_06_level [06:06] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_MASK      0x00000040
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_SHIFT     6
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_05_level [05:05] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_MASK      0x00000020
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_SHIFT     5
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_04_level [04:04] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_MASK      0x00000010
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_03_level [03:03] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_MASK      0x00000008
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_SHIFT     3
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_02_level [02:02] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_MASK      0x00000004
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_SHIFT     2
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_01_level [01:01] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_MASK      0x00000002
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_SHIFT     1
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_00_level [00:00] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_MASK      0x00000001
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_SHIFT     0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_HIGH      1
+
+/***************************************************************************
+ *PM_CTRL0 - HIF Power Management Control0 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_PM_IN_DRIVE_INACTIVE [31:30] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_MASK   0xc0000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_SHIFT  30
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_IN_DRIVE_INACTIVE [29:28] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x30000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 28
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: reserved0 [27:26] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_reserved0_MASK                  0x0c000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_reserved0_SHIFT                 26
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_DATA_PM_OUT_CTRL [25:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_MASK       0x03000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_SHIFT      24
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_ADDR_PM_OUT_CTRL [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_MASK       0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_SHIFT      22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_CTRL_PM_OUT_CTRL [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_MASK       0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_SHIFT      20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_OUT_CTRL [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_MASK      0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_SHIFT     18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_CTRL_PM_OUT_CTRL [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_MASK      0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_SHIFT     16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS7 [15:14] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_MASK            0x0000c000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_SHIFT           14
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS6 [13:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_MASK            0x00003000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_SHIFT           12
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS5 [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_MASK            0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_SHIFT           10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS4 [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_MASK            0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_SHIFT           8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS3 [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_MASK            0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_SHIFT           6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS2 [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_MASK            0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_SHIFT           4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS1 [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_MASK            0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_SHIFT           2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS0 [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_MASK            0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_SHIFT           0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_Tristate        3
+
+/***************************************************************************
+ *PM_CTRL1 - HIF Power Management Control1 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL1 :: reserved0 [31:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_MASK                  0xfffff000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_PM_IN_DRIVE_INACTIVE [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_WPB_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_MASK        0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_SHIFT       8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_DEFAULT     0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_Tristate    3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_HOLDB_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_MASK      0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_SHIFT     6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MISO_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_MASK       0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_SHIFT      4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MOSI_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_MASK        0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_SHIFT       0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_DEFAULT     0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_Tristate    3
+
+/***************************************************************************
+ *SCRATCH - HIF Scratch Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_MASK                 0xffffffff
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_SHIFT                0
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_DEFAULT              0
+
+/***************************************************************************
+ *FLASH_TYPE - HIF Decoded Flash Type
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: FLASH_TYPE :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_MASK                0xfffffff8
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_SHIFT               3
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: InvalidStrap [02:02] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_MASK             0x00000004
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_SHIFT            2
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_DEFAULT          0
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: FLASH_TYPE [01:00] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_MASK               0x00000003
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SHIFT              0
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_DEFAULT            0
+
+/***************************************************************************
+ *SPI_DBG_SEL - SPI test port select register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_MASK               0xfffffff8
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_SHIFT              3
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: DISABLE_MSPI_FLUSH [02:02] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_MASK      0x00000004
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_SHIFT     2
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_DEFAULT   0
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SPI_RBUS_TIMER_EN [01:01] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_MASK       0x00000002
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_SHIFT      1
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_DEFAULT    0
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SPI_TP_SEL [00:00] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_TP_SEL_MASK              0x00000001
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_TP_SEL_SHIFT             0
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_TP_SEL_DEFAULT           0
+
+/***************************************************************************
+ *HIF_CTRL - HIF HIF_CTRL Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: HIF_CTRL :: reserved0 [31:01] */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_reserved0_SHIFT                 1
+
+/* HIF_TOP_CTRL :: HIF_CTRL :: ENABLE_FULL_USE_OF_EBI [00:00] */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_MASK     0x00000001
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_SHIFT    0
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_DEFAULT  0
+
+#endif /* #ifndef BCHP_HIF_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_irq0.h b/include/linux/brcmstb/7358a0/bchp_irq0.h
new file mode 100644
index 0000000..904a491
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_irq0.h
@@ -0,0 +1,217 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:37:56 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_irq0.h $
+ * 
+ * Hydra_Software_Devel/3   9/20/11 11:58a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ0_H__
+#define BCHP_IRQ0_H__
+
+/***************************************************************************
+ *IRQ0 - Level 2 CPU Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ0_IRQEN                          0x00406600 /* Interrupt Enable */
+#define BCHP_IRQ0_IRQSTAT                        0x00406604 /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ0 :: IRQEN :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQEN_reserved0_MASK                             0xf8000000
+#define BCHP_IRQ0_IRQEN_reserved0_SHIFT                            27
+
+/* IRQ0 :: IRQEN :: iicc_irqen [26:26] */
+#define BCHP_IRQ0_IRQEN_iicc_irqen_MASK                            0x04000000
+#define BCHP_IRQ0_IRQEN_iicc_irqen_SHIFT                           26
+#define BCHP_IRQ0_IRQEN_iicc_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: iicb_irqen [25:25] */
+#define BCHP_IRQ0_IRQEN_iicb_irqen_MASK                            0x02000000
+#define BCHP_IRQ0_IRQEN_iicb_irqen_SHIFT                           25
+#define BCHP_IRQ0_IRQEN_iicb_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: iica_irqen [24:24] */
+#define BCHP_IRQ0_IRQEN_iica_irqen_MASK                            0x01000000
+#define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT                           24
+#define BCHP_IRQ0_IRQEN_iica_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQEN_reserved1_MASK                             0x00f80000
+#define BCHP_IRQ0_IRQEN_reserved1_SHIFT                            19
+
+/* IRQ0 :: IRQEN :: uartc_irqen [18:18] */
+#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK                           0x00040000
+#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT                          18
+#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: uartb_irqen [17:17] */
+#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK                           0x00020000
+#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT                          17
+#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: uarta_irqen [16:16] */
+#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK                           0x00010000
+#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT                          16
+#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQEN_reserved2_MASK                             0x0000fc00
+#define BCHP_IRQ0_IRQEN_reserved2_SHIFT                            10
+
+/* IRQ0 :: IRQEN :: uc_irqen [09:09] */
+#define BCHP_IRQ0_IRQEN_uc_irqen_MASK                              0x00000200
+#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT                             9
+#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQEN_reserved3_MASK                             0x00000180
+#define BCHP_IRQ0_IRQEN_reserved3_SHIFT                            7
+
+/* IRQ0 :: IRQEN :: gio_irqen [06:06] */
+#define BCHP_IRQ0_IRQEN_gio_irqen_MASK                             0x00000040
+#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT                            6
+#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT                          0
+
+/* IRQ0 :: IRQEN :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQEN_reserved4_MASK                             0x00000020
+#define BCHP_IRQ0_IRQEN_reserved4_SHIFT                            5
+
+/* IRQ0 :: IRQEN :: ua_irqen [04:04] */
+#define BCHP_IRQ0_IRQEN_ua_irqen_MASK                              0x00000010
+#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT                             4
+#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: ub_irqen [03:03] */
+#define BCHP_IRQ0_IRQEN_ub_irqen_MASK                              0x00000008
+#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT                             3
+#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: irb_irqen [02:02] */
+#define BCHP_IRQ0_IRQEN_irb_irqen_MASK                             0x00000004
+#define BCHP_IRQ0_IRQEN_irb_irqen_SHIFT                            2
+#define BCHP_IRQ0_IRQEN_irb_irqen_DEFAULT                          0
+
+/* IRQ0 :: IRQEN :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQEN_reserved5_MASK                             0x00000003
+#define BCHP_IRQ0_IRQEN_reserved5_SHIFT                            0
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ0 :: IRQSTAT :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQSTAT_reserved0_MASK                           0xf8000000
+#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT                          27
+
+/* IRQ0 :: IRQSTAT :: iiccirq [26:26] */
+#define BCHP_IRQ0_IRQSTAT_iiccirq_MASK                             0x04000000
+#define BCHP_IRQ0_IRQSTAT_iiccirq_SHIFT                            26
+#define BCHP_IRQ0_IRQSTAT_iiccirq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: iicbirq [25:25] */
+#define BCHP_IRQ0_IRQSTAT_iicbirq_MASK                             0x02000000
+#define BCHP_IRQ0_IRQSTAT_iicbirq_SHIFT                            25
+#define BCHP_IRQ0_IRQSTAT_iicbirq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: iicairq [24:24] */
+#define BCHP_IRQ0_IRQSTAT_iicairq_MASK                             0x01000000
+#define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT                            24
+#define BCHP_IRQ0_IRQSTAT_iicairq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQSTAT_reserved1_MASK                           0x00f80000
+#define BCHP_IRQ0_IRQSTAT_reserved1_SHIFT                          19
+
+/* IRQ0 :: IRQSTAT :: uartc_irq [18:18] */
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK                           0x00040000
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT                          18
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: uartb_irq [17:17] */
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK                           0x00020000
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT                          17
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: uarta_irq [16:16] */
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK                           0x00010000
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT                          16
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQSTAT_reserved2_MASK                           0x0000fc00
+#define BCHP_IRQ0_IRQSTAT_reserved2_SHIFT                          10
+
+/* IRQ0 :: IRQSTAT :: ucirq [09:09] */
+#define BCHP_IRQ0_IRQSTAT_ucirq_MASK                               0x00000200
+#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT                              9
+#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQSTAT_reserved3_MASK                           0x00000180
+#define BCHP_IRQ0_IRQSTAT_reserved3_SHIFT                          7
+
+/* IRQ0 :: IRQSTAT :: gioirq [06:06] */
+#define BCHP_IRQ0_IRQSTAT_gioirq_MASK                              0x00000040
+#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT                             6
+#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT                           0
+
+/* IRQ0 :: IRQSTAT :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQSTAT_reserved4_MASK                           0x00000020
+#define BCHP_IRQ0_IRQSTAT_reserved4_SHIFT                          5
+
+/* IRQ0 :: IRQSTAT :: uairq [04:04] */
+#define BCHP_IRQ0_IRQSTAT_uairq_MASK                               0x00000010
+#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT                              4
+#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: ubirq [03:03] */
+#define BCHP_IRQ0_IRQSTAT_ubirq_MASK                               0x00000008
+#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT                              3
+#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: irbirq [02:02] */
+#define BCHP_IRQ0_IRQSTAT_irbirq_MASK                              0x00000004
+#define BCHP_IRQ0_IRQSTAT_irbirq_SHIFT                             2
+#define BCHP_IRQ0_IRQSTAT_irbirq_DEFAULT                           0
+
+/* IRQ0 :: IRQSTAT :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQSTAT_reserved5_MASK                           0x00000003
+#define BCHP_IRQ0_IRQSTAT_reserved5_SHIFT                          0
+
+#endif /* #ifndef BCHP_IRQ0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_irq1.h b/include/linux/brcmstb/7358a0/bchp_irq1.h
new file mode 100644
index 0000000..a43a82a
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_irq1.h
@@ -0,0 +1,53 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug 16 11:01:23 2010
+ *                 MD5 Checksum         442d8de773a92e76786307c9f37b5c82
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_irq1.h $
+ * 
+ * Hydra_Software_Devel/2   8/16/10 12:17p pntruong
+ * SW7358-2: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ1_H__
+#define BCHP_IRQ1_H__
+
+/***************************************************************************
+ *IRQ1 - Level 2 PCI Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ1_IRQEN                          0x00406640 /* Interrupt Enable */
+#define BCHP_IRQ1_IRQSTAT                        0x00406644 /* Interrupt Status */
+
+#endif /* #ifndef BCHP_IRQ1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_mem_dma_0.h b/include/linux/brcmstb/7358a0/bchp_mem_dma_0.h
new file mode 100644
index 0000000..e47974b
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_mem_dma_0.h
@@ -0,0 +1,157 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:47:01 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_mem_dma_0.h $
+ * 
+ * Hydra_Software_Devel/2   9/20/11 12:03p pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEM_DMA_0_H__
+#define BCHP_MEM_DMA_0_H__
+
+/***************************************************************************
+ *MEM_DMA_0 - MEM_DMA_0 Registers
+ ***************************************************************************/
+#define BCHP_MEM_DMA_0_REVISION                  0x00360200 /* MEM_DMA REVISION */
+#define BCHP_MEM_DMA_0_FIRST_DESC                0x00360204 /* MEM_DMA First Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CTRL                      0x00360208 /* MEM_DMA Control Register */
+#define BCHP_MEM_DMA_0_WAKE_CTRL                 0x0036020c /* MEM_DMA Wake Control Register */
+#define BCHP_MEM_DMA_0_STATUS                    0x00360214 /* MEM_DMA Status Register */
+#define BCHP_MEM_DMA_0_CUR_DESC                  0x00360218 /* MEM_DMA Current Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CUR_BYTE                  0x0036021c /* MEM_DMA Current Byte Count Register */
+#define BCHP_MEM_DMA_0_SCRATCH                   0x00360224 /* MEM_DMA Scratch Register */
+
+/***************************************************************************
+ *REVISION - MEM_DMA REVISION
+ ***************************************************************************/
+/* MEM_DMA_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_0_REVISION_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_0_REVISION_reserved0_SHIFT                    16
+
+/* MEM_DMA_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_MASK                         0x0000ff00
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_SHIFT                        8
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_DEFAULT                      2
+
+/* MEM_DMA_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_MEM_DMA_0_REVISION_MINOR_MASK                         0x000000ff
+#define BCHP_MEM_DMA_0_REVISION_MINOR_SHIFT                        0
+#define BCHP_MEM_DMA_0_REVISION_MINOR_DEFAULT                      10
+
+/***************************************************************************
+ *FIRST_DESC - MEM_DMA First Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: FIRST_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_MASK                        0xffffffff
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_SHIFT                       0
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_DEFAULT                     0
+
+/***************************************************************************
+ *CTRL - MEM_DMA Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CTRL :: reserved0 [31:01] */
+#define BCHP_MEM_DMA_0_CTRL_reserved0_MASK                         0xfffffffe
+#define BCHP_MEM_DMA_0_CTRL_reserved0_SHIFT                        1
+
+/* MEM_DMA_0 :: CTRL :: RUN [00:00] */
+#define BCHP_MEM_DMA_0_CTRL_RUN_MASK                               0x00000001
+#define BCHP_MEM_DMA_0_CTRL_RUN_SHIFT                              0
+#define BCHP_MEM_DMA_0_CTRL_RUN_DEFAULT                            0
+
+/***************************************************************************
+ *WAKE_CTRL - MEM_DMA Wake Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: WAKE_CTRL :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_MASK                    0xfffffffc
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_SHIFT                   2
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE_MODE [01:01] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_MASK                    0x00000002
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_SHIFT                   1
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_DEFAULT                 0
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE [00:00] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MASK                         0x00000001
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_SHIFT                        0
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_DEFAULT                      0
+
+/***************************************************************************
+ *STATUS - MEM_DMA Status Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: STATUS :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_MEM_DMA_0_STATUS_reserved0_SHIFT                      2
+
+/* MEM_DMA_0 :: STATUS :: DMA_STATUS [01:00] */
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_MASK                      0x00000003
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_SHIFT                     0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_DEFAULT                   0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Idle                      0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Busy                      1
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Sleep                     2
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Reserved                  3
+
+/***************************************************************************
+ *CUR_DESC - MEM_DMA Current Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_MASK                          0xffffffff
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_SHIFT                         0
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_DEFAULT                       0
+
+/***************************************************************************
+ *CUR_BYTE - MEM_DMA Current Byte Count Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_BYTE :: reserved0 [31:25] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_MASK                     0xfe000000
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_SHIFT                    25
+
+/* MEM_DMA_0 :: CUR_BYTE :: COUNT [24:00] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_MASK                         0x01ffffff
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_SHIFT                        0
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_DEFAULT                      0
+
+/***************************************************************************
+ *SCRATCH - MEM_DMA Scratch Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_MASK                    0xffffffff
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_SHIFT                   0
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_DEFAULT                 0
+
+#endif /* #ifndef BCHP_MEM_DMA_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_memc_ddr_0.h b/include/linux/brcmstb/7358a0/bchp_memc_ddr_0.h
new file mode 100644
index 0000000..76c0469
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_memc_ddr_0.h
@@ -0,0 +1,2647 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 22:00:00 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_memc_ddr_0.h $
+ * 
+ * Hydra_Software_Devel/4   9/20/11 12:03p pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR_0_H__
+#define BCHP_MEMC_DDR_0_H__
+
+/***************************************************************************
+ *MEMC_DDR_0 - Memory Controller Sequencer (DDR Param/Control) Registers 0
+ ***************************************************************************/
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG            0x003b2000 /* Memory Controller Mode-Configuration Register. */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL          0x003b2004 /* Dram iniitialization control */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS         0x003b2008 /* Dram iniitialization status */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0              0x003b200c /* Dram Mode0 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1              0x003b2010 /* Dram Mode1 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2              0x003b2014 /* Dram Mode2 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3              0x003b2018 /* Dram Mode3 register */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG               0x003b201c /* Precharge power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG              0x003b2020 /* Self-refresh power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SSPD_CMD                 0x003b2024 /* Software standby power down mode */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS        0x003b2028 /* Power down status */
+#define BCHP_MEMC_DDR_0_WARM_BOOT                0x003b202c /* Warm boot control registers */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0            0x003b2030 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1            0x003b2034 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2            0x003b2038 /* Read to Write & write to read timing register */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3            0x003b203c /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4            0x003b2040 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5            0x003b2044 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ         0x003b2048 /* Memory Controller Sequencer Enable */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT        0x003b204c /* Memory Controller , state machine timeout register. */
+#define BCHP_MEMC_DDR_0_BANK_STATUS              0x003b2050 /* Memory Controller, Bank Status Register. */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY           0x003b2054 /* Memory Controller, Tester Latency Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0               0x003b2058 /* Memory Controller, DATA_PINMAP_BYTE0_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1               0x003b205c /* Memory Controller, DATA_PINMAP_BYTE1_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2               0x003b2060 /* Memory Controller, DATA_PINMAP_BYTE2_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3               0x003b2064 /* Memory Controller, DATA_PINMAP_BYTE3_SEL Register. */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD   0x003b2068 /* Memory Controller, DDR3 DRAM reset Register. */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL             0x003b206c /* Statistics Control register */
+#define BCHP_MEMC_DDR_0_STAT_TIMER               0x003b2070 /* Statistics Timer */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP            0x003b2074 /* DRAM Idle_NOP Cycle Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP        0x003b2078 /* Maximum DRAM idle_NOP cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL             0x003b207c /* CAS Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL         0x003b2080 /* Maximum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL         0x003b2084 /* DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL 0x003b2088 /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL      0x003b208c /* Number of overall system memory read transactions. */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL     0x003b2090 /* Number of overall system memory write transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL       0x003b2094 /* Maximum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL       0x003b2098 /* Minimum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS  0x003b209c /* Service CAS Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS 0x003b20a0 /* Maximum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS 0x003b20a4 /* Minimum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY 0x003b20a8 /* Service Intra DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY 0x003b20ac /* Service Post DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES 0x003b20b0 /* Maximum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES 0x003b20b4 /* Minimum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ 0x003b20b8 /* Service Read Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE 0x003b20bc /* Service Write Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS 0x003b20c0 /* Maximum service Transaction count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS 0x003b20c4 /* Minimum service cycle Transaction register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY 0x003b20c8 /* Service Latency Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY 0x003b20cc /* Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY 0x003b20d0 /* Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x003b20d4 /* Absolute Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x003b20d8 /* Absolute Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH             0x003b20dc /* Total number of refreshes issuedr. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0        0x003b20e0 /* CAS cycle count register for client 0. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1        0x003b20e4 /* CAS cycle count register for client 1. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2        0x003b20e8 /* CAS cycle count register for client 2. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3        0x003b20ec /* CAS cycle count register for client 3. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4        0x003b20f0 /* CAS cycle count register for client 4. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5        0x003b20f4 /* CAS cycle count register for client 5. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6        0x003b20f8 /* CAS cycle count register for client 6. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7        0x003b20fc /* CAS cycle count register for client 7. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8        0x003b2100 /* CAS cycle count register for client 8. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9        0x003b2104 /* CAS cycle count register for client 9. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10       0x003b2108 /* CAS cycle count register for client 10. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11       0x003b210c /* CAS cycle count register for client 11. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12       0x003b2110 /* CAS cycle count register for client 12. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13       0x003b2114 /* CAS cycle count register for client 13. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14       0x003b2118 /* CAS cycle count register for client 14. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15       0x003b211c /* CAS cycle count register for client 15. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16       0x003b2120 /* CAS cycle count register for client 16. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17       0x003b2124 /* CAS cycle count register for client 17. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18       0x003b2128 /* CAS cycle count register for client 18. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19       0x003b212c /* CAS cycle count register for client 19. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20       0x003b2130 /* CAS cycle count register for client 20. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21       0x003b2134 /* CAS cycle count register for client 21. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22       0x003b2138 /* CAS cycle count register for client 22. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23       0x003b213c /* CAS cycle count register for client 23. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24       0x003b2140 /* CAS cycle count register for client 24. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25       0x003b2144 /* CAS cycle count register for client 25. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26       0x003b2148 /* CAS cycle count register for client 26. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27       0x003b214c /* CAS cycle count register for client 27. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28       0x003b2150 /* CAS cycle count register for client 28. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29       0x003b2154 /* CAS cycle count register for client 29. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30       0x003b2158 /* CAS cycle count register for client 30. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31       0x003b215c /* CAS cycle count register for client 31. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32       0x003b2160 /* CAS cycle count register for client 32. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33       0x003b2164 /* CAS cycle count register for client 33. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34       0x003b2168 /* CAS cycle count register for client 34. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35       0x003b216c /* CAS cycle count register for client 35. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36       0x003b2170 /* CAS cycle count register for client 36. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37       0x003b2174 /* CAS cycle count register for client 37. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38       0x003b2178 /* CAS cycle count register for client 38. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39       0x003b217c /* CAS cycle count register for client 39. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40       0x003b2180 /* CAS cycle count register for client 40. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41       0x003b2184 /* CAS cycle count register for client 41. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42       0x003b2188 /* CAS cycle count register for client 42. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43       0x003b218c /* CAS cycle count register for client 43. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44       0x003b2190 /* CAS cycle count register for client 44. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45       0x003b2194 /* CAS cycle count register for client 45. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46       0x003b2198 /* CAS cycle count register for client 46. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47       0x003b219c /* CAS cycle count register for client 47. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48       0x003b21a0 /* CAS cycle count register for client 48. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49       0x003b21a4 /* CAS cycle count register for client 49. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50       0x003b21a8 /* CAS cycle count register for client 50. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51       0x003b21ac /* CAS cycle count register for client 51. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52       0x003b21b0 /* CAS cycle count register for client 52. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53       0x003b21b4 /* CAS cycle count register for client 53. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54       0x003b21b8 /* CAS cycle count register for client 54. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55       0x003b21bc /* CAS cycle count register for client 55. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56       0x003b21c0 /* CAS cycle count register for client 56. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57       0x003b21c4 /* CAS cycle count register for client 57. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58       0x003b21c8 /* CAS cycle count register for client 58. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59       0x003b21cc /* CAS cycle count register for client 59. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60       0x003b21d0 /* CAS cycle count register for client 60. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61       0x003b21d4 /* CAS cycle count register for client 61. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62       0x003b21d8 /* CAS cycle count register for client 62. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63       0x003b21dc /* CAS cycle count register for client 63. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64       0x003b21e0 /* CAS cycle count register for client 64. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65       0x003b21e4 /* CAS cycle count register for client 65. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66       0x003b21e8 /* CAS cycle count register for client 66. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67       0x003b21ec /* CAS cycle count register for client 67. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68       0x003b21f0 /* CAS cycle count register for client 68. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69       0x003b21f4 /* CAS cycle count register for client 69. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70       0x003b21f8 /* CAS cycle count register for client 70. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71       0x003b21fc /* CAS cycle count register for client 71. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72       0x003b2200 /* CAS cycle count register for client 72. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73       0x003b2204 /* CAS cycle count register for client 73. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74       0x003b2208 /* CAS cycle count register for client 74. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75       0x003b220c /* CAS cycle count register for client 75. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76       0x003b2210 /* CAS cycle count register for client 76. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77       0x003b2214 /* CAS cycle count register for client 77. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78       0x003b2218 /* CAS cycle count register for client 78. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79       0x003b221c /* CAS cycle count register for client 79. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80       0x003b2220 /* CAS cycle count register for client 80. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81       0x003b2224 /* CAS cycle count register for client 81. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82       0x003b2228 /* CAS cycle count register for client 82. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83       0x003b222c /* CAS cycle count register for client 83. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84       0x003b2230 /* CAS cycle count register for client 84. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85       0x003b2234 /* CAS cycle count register for client 85. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86       0x003b2238 /* CAS cycle count register for client 86. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87       0x003b223c /* CAS cycle count register for client 87. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88       0x003b2240 /* CAS cycle count register for client 88. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89       0x003b2244 /* CAS cycle count register for client 89. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90       0x003b2248 /* CAS cycle count register for client 90. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91       0x003b224c /* CAS cycle count register for client 91. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92       0x003b2250 /* CAS cycle count register for client 92. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93       0x003b2254 /* CAS cycle count register for client 93. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94       0x003b2258 /* CAS cycle count register for client 94. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95       0x003b225c /* CAS cycle count register for client 95. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96       0x003b2260 /* CAS cycle count register for client 96. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97       0x003b2264 /* CAS cycle count register for client 97. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98       0x003b2268 /* CAS cycle count register for client 98. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99       0x003b226c /* CAS cycle count register for client 99. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100      0x003b2270 /* CAS cycle count register for client 100. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101      0x003b2274 /* CAS cycle count register for client 101. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102      0x003b2278 /* CAS cycle count register for client 102. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103      0x003b227c /* CAS cycle count register for client 103. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104      0x003b2280 /* CAS cycle count register for client 104. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105      0x003b2284 /* CAS cycle count register for client 105. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106      0x003b2288 /* CAS cycle count register for client 106. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107      0x003b228c /* CAS cycle count register for client 107. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108      0x003b2290 /* CAS cycle count register for client 108. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109      0x003b2294 /* CAS cycle count register for client 109. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110      0x003b2298 /* CAS cycle count register for client 110. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111      0x003b229c /* CAS cycle count register for client 111. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112      0x003b22a0 /* CAS cycle count register for client 112. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113      0x003b22a4 /* CAS cycle count register for client 113. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114      0x003b22a8 /* CAS cycle count register for client 114. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115      0x003b22ac /* CAS cycle count register for client 115. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116      0x003b22b0 /* CAS cycle count register for client 116. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117      0x003b22b4 /* CAS cycle count register for client 117. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118      0x003b22b8 /* CAS cycle count register for client 118. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119      0x003b22bc /* CAS cycle count register for client 119. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120      0x003b22c0 /* CAS cycle count register for client 120. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121      0x003b22c4 /* CAS cycle count register for client 121. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122      0x003b22c8 /* CAS cycle count register for client 122. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123      0x003b22cc /* CAS cycle count register for client 123. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124      0x003b22d0 /* CAS cycle count register for client 124. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125      0x003b22d4 /* CAS cycle count register for client 125. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126      0x003b22d8 /* CAS cycle count register for client 126. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127      0x003b22dc /* CAS cycle count register for client 127. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL         0x003b22e0 /* Minimum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL 0x003b22e4 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL 0x003b22e8 /* MEMSYS Auto Init Control. */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS  0x003b22ec /* MEMSYS Auto Init Status. */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE 0x003b22f0 /* PHY VDL calibrate override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE 0x003b22f4 /* SHIM PLL pndiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE 0x003b22f8 /* SHIM PLL mdiv override from memc auto init. */
+
+/***************************************************************************
+ *CNTRLR_CONFIG - Memory Controller Mode-Configuration Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_MASK               0xfffffff8
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_SHIFT              3
+
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DEVICE_TECH [02:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_SHIFT            0
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_DEFAULT          3
+
+/***************************************************************************
+ *DRAM_INIT_CNTRL - Dram iniitialization control
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_MASK             0xfffffff8
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_SHIFT            3
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: BYPASS_PHY_INIT_RDY [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_MASK   0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_SHIFT  2
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR_TECH [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DEFAULT           1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR2              0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR3              1
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR3_INIT_MODE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_MASK        0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_SHIFT       0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_DEFAULT     0
+
+/***************************************************************************
+ *DRAM_INIT_STATUS - Dram iniitialization status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_SHIFT           0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_DEFAULT         0
+
+/***************************************************************************
+ *DRAM_MODE_0 - Dram Mode0 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: PD_EXIT [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_MASK              0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_SHIFT             12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_DEFAULT                7
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_DEFAULT         0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: CL [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_MASK                   0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_DEFAULT                0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BL [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_DEFAULT                2
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK        0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT       12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT     0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_DEFAULT                4
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT         0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_MASK               0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_SHIFT              4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT            4
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_DEFAULT               0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_MASK                 0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_SHIFT                2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_DEFAULT              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_MASK                   0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_MODE_1 - Dram Mode1 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DEFAULT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: RDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DQSB [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_MASK                 0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_SHIFT                10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_ENABLE               0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DISABLE              1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: OCD_CAL [09:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_MASK              0x00000380
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_SHIFT             7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_DEFAULT       1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: AL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_MASK                   0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DRV_IMP [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DISABLE            1
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_MASK             0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_SHIFT            10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK          0x00000200
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT         9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_MASK             0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT            7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT          0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE           1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK   0x00000020
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT  5
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_MASK                   0x00000018
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT       1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK   0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT  1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DISABLE            1
+
+/***************************************************************************
+ *DRAM_MODE_2 - Dram Mode2 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_1 [12:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_MASK             0x00001f00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: HT_SRF [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_ENABLE             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DISABLE            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_2 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_MASK             0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_SHIFT            4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: DCC_ENABLE [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_MASK           0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_SHIFT          3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DEFAULT        0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_ENABLE         1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DISABLE        0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_DEFAULT              0
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_MASK             0x00001800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_SHIFT            11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_MASK               0x00000600
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_SHIFT              9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT            1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT             6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT           1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_MASK                  0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_DEFAULT               1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_MODE_3 - Dram Mode3 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: unused_0 [15:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_MASK                  0x0000fff8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_DEFAULT               0
+
+/* union - case DDR2 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR2 :: unused_1 [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_SHIFT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_DEFAULT          0
+
+/* union - case DDR3 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_MASK                  0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_SHIFT                 2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_DEFAULT               0
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_MASK              0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT           0
+
+/***************************************************************************
+ *PPD_CONFIG - Precharge power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PPD_CONFIG :: reserved0 [31:13] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_MASK                  0xffffe000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_SHIFT                 13
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_EN [12:12] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_MASK                     0x00001000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_SHIFT                    12
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_DEFAULT                  0
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: INACT_COUNT [11:00] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_MASK                0x00000fff
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *SRPD_CONFIG - Self-refresh power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SRPD_CONFIG :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_MASK                 0xfffe0000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_SHIFT                17
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: SRPD_EN [16:16] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_MASK                   0x00010000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_SHIFT                  16
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_DEFAULT                0
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *SSPD_CMD - Software standby power down mode
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SSPD_CMD :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_MASK                    0xfffffffe
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_SHIFT                   1
+
+/* MEMC_DDR_0 :: SSPD_CMD :: SSPD [00:00] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK                         0x00000001
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_SHIFT                        0
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_DEFAULT                      0
+
+/***************************************************************************
+ *POWER_DOWN_STATUS - Power down status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_MASK           0xfffffff8
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_SHIFT          3
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SSPD [02:02] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK                0x00000004
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_SHIFT               2
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_DEFAULT             0
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SRPD [01:01] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_MASK                0x00000002
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_SHIFT               1
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_DEFAULT             0
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: PPD [00:00] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_MASK                 0x00000001
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_SHIFT                0
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_DEFAULT              0
+
+/***************************************************************************
+ *WARM_BOOT - Warm boot control registers
+ ***************************************************************************/
+/* MEMC_DDR_0 :: WARM_BOOT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_MASK                   0xfffffffe
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_SHIFT                  1
+
+/* MEMC_DDR_0 :: WARM_BOOT :: WARM_BOOT [00:00] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_MASK                   0x00000001
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_TIMING_0 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_MASK                0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_SHIFT               24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_DEFAULT             6
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_MASK                0x00ff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_SHIFT               16
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_DEFAULT             8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_MASK                 0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_SHIFT                8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_DEFAULT              8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_DEFAULT             20
+
+/***************************************************************************
+ *DRAM_TIMING_1 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_MASK                0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_SHIFT               8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_DEFAULT             27
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_DEFAULT             4
+
+/***************************************************************************
+ *DRAM_TIMING_2 - Read to Write & write to read timing register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_MASK               0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_SHIFT              8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_DEFAULT            14
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_MASK               0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_DEFAULT            9
+
+/***************************************************************************
+ *DRAM_TIMING_3 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: reserved0 [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_MASK               0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_SHIFT              24
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT      12
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: POWERUP_CKE_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_MASK       0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_SHIFT      10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_DEFAULT    94
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: DLL_LOCK_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_MASK          0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_SHIFT         0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_DEFAULT       512
+
+/***************************************************************************
+ *DRAM_TIMING_4 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: PRECHARGE_ALL_DELAY [28:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_MASK     0x1f000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_SHIFT    24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_DEFAULT  8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: LOAD_MODE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_DEFAULT      12
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: REFRESH_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_MASK           0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_SHIFT          10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT        88
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_MASK           0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT          0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT        512
+
+/***************************************************************************
+ *DRAM_TIMING_5 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_ASSETION_DELAY [28:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_MASK      0x1ff80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_SHIFT     19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_DEFAULT   261
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [18:15] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK           0x00078000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT          15
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT        3
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [14:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK         0x00007c00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT        10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT      13
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK      0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT     0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT   512
+
+/***************************************************************************
+ *CNTRLR_START_SEQ - Memory Controller Sequencer Enable
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: START_SEQ [00:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_SHIFT           0
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_DEFAULT         0
+
+/***************************************************************************
+ *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_MASK           0xfffe0000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_SHIFT          17
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_MASK              0x00010000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT             16
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT           0
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT            65535
+
+/***************************************************************************
+ *BANK_STATUS - Memory Controller, Bank Status Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: BANK_STATUS :: reserved0 [31:08] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_SHIFT                8
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK7_STATUS [07:07] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_SHIFT             7
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK6_STATUS [06:06] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_SHIFT             6
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK5_STATUS [05:05] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_MASK              0x00000020
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_SHIFT             5
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK4_STATUS [04:04] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_MASK              0x00000010
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_SHIFT             4
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK3_STATUS [03:03] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_MASK              0x00000008
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_SHIFT             3
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK2_STATUS [02:02] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_MASK              0x00000004
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_SHIFT             2
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK1_STATUS [01:01] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_SHIFT             1
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK0_STATUS [00:00] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_MASK              0x00000001
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_SHIFT             0
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_DEFAULT           1
+
+/***************************************************************************
+ *TESTER_LATENCY - Memory Controller, Tester Latency Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: TESTER_LATENCY :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_MASK              0xffffff80
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_SHIFT             7
+
+/* MEMC_DDR_0 :: TESTER_LATENCY :: TLATENCY_SEL [06:00] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_MASK           0x0000007f
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_SHIFT          0
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_DEFAULT        0
+
+/***************************************************************************
+ *DTPM_BYTE0 - Memory Controller, DATA_PINMAP_BYTE0_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE1 - Memory Controller, DATA_PINMAP_BYTE1_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE2 - Memory Controller, DATA_PINMAP_BYTE2_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE3 - Memory Controller, DATA_PINMAP_BYTE3_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_DDR3_RESET_PERIOD - Memory Controller, DDR3 DRAM reset Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: reserved0 [31:20] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_MASK      0xfff00000
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_SHIFT     20
+
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: DRAM_RESET_PERIOD [19:00] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_MASK 0x000fffff
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_SHIFT 0
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_DEFAULT 43200
+
+/***************************************************************************
+ *STAT_CONTROL - Statistics Control register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CONTROL :: reserved0 [31:09] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_MASK                0xfffffe00
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_SHIFT               9
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: COUNTER_MODE [08:08] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_SHIFT            8
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_DEFAULT          0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT    1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_NORMAL           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: STAT_ENABLE [07:07] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_SHIFT             7
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DEFAULT           0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_ENABLE            1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DISABLE           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: CLIENT_ID [06:00] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_MASK                0x0000007f
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_DEFAULT             0
+
+/***************************************************************************
+ *STAT_TIMER - Statistics Timer
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TIMER :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_MASK                      0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_SHIFT                     0
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_DEFAULT                   0
+
+/***************************************************************************
+ *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_MASK                   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_DEFAULT                0
+
+/***************************************************************************
+ *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_ALL - CAS Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_DEFAULT                 0
+
+/***************************************************************************
+ *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_PENALTY_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT    0
+
+/***************************************************************************
+ *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_MASK            0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_SHIFT           0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT         0
+
+/***************************************************************************
+ *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_DEFAULT           4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_MASK         0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT        0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT      0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT  4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT  0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_REFRESH - Total number of refreshes issuedr.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_REFRESH :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_DEFAULT                 0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_0 - CAS cycle count register for client 0.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_1 - CAS cycle count register for client 1.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_2 - CAS cycle count register for client 2.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_3 - CAS cycle count register for client 3.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_4 - CAS cycle count register for client 4.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_5 - CAS cycle count register for client 5.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_6 - CAS cycle count register for client 6.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_7 - CAS cycle count register for client 7.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_8 - CAS cycle count register for client 8.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_9 - CAS cycle count register for client 9.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_10 - CAS cycle count register for client 10.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_11 - CAS cycle count register for client 11.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_12 - CAS cycle count register for client 12.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_13 - CAS cycle count register for client 13.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_14 - CAS cycle count register for client 14.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_15 - CAS cycle count register for client 15.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_16 - CAS cycle count register for client 16.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_17 - CAS cycle count register for client 17.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_18 - CAS cycle count register for client 18.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_19 - CAS cycle count register for client 19.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_20 - CAS cycle count register for client 20.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_21 - CAS cycle count register for client 21.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_22 - CAS cycle count register for client 22.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_23 - CAS cycle count register for client 23.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_24 - CAS cycle count register for client 24.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_25 - CAS cycle count register for client 25.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_26 - CAS cycle count register for client 26.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_27 - CAS cycle count register for client 27.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_28 - CAS cycle count register for client 28.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_29 - CAS cycle count register for client 29.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_30 - CAS cycle count register for client 30.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_31 - CAS cycle count register for client 31.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_32 - CAS cycle count register for client 32.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_33 - CAS cycle count register for client 33.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_34 - CAS cycle count register for client 34.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_35 - CAS cycle count register for client 35.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_36 - CAS cycle count register for client 36.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_37 - CAS cycle count register for client 37.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_38 - CAS cycle count register for client 38.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_39 - CAS cycle count register for client 39.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_40 - CAS cycle count register for client 40.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_41 - CAS cycle count register for client 41.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_42 - CAS cycle count register for client 42.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_43 - CAS cycle count register for client 43.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_44 - CAS cycle count register for client 44.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_45 - CAS cycle count register for client 45.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_46 - CAS cycle count register for client 46.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_47 - CAS cycle count register for client 47.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_48 - CAS cycle count register for client 48.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_49 - CAS cycle count register for client 49.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_50 - CAS cycle count register for client 50.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_51 - CAS cycle count register for client 51.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_52 - CAS cycle count register for client 52.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_53 - CAS cycle count register for client 53.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_54 - CAS cycle count register for client 54.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_55 - CAS cycle count register for client 55.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_56 - CAS cycle count register for client 56.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_57 - CAS cycle count register for client 57.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_58 - CAS cycle count register for client 58.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_59 - CAS cycle count register for client 59.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_60 - CAS cycle count register for client 60.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_61 - CAS cycle count register for client 61.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_62 - CAS cycle count register for client 62.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_63 - CAS cycle count register for client 63.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_64 - CAS cycle count register for client 64.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_65 - CAS cycle count register for client 65.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_66 - CAS cycle count register for client 66.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_67 - CAS cycle count register for client 67.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_68 - CAS cycle count register for client 68.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_69 - CAS cycle count register for client 69.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_70 - CAS cycle count register for client 70.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_71 - CAS cycle count register for client 71.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_72 - CAS cycle count register for client 72.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_73 - CAS cycle count register for client 73.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_74 - CAS cycle count register for client 74.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_75 - CAS cycle count register for client 75.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_76 - CAS cycle count register for client 76.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_77 - CAS cycle count register for client 77.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_78 - CAS cycle count register for client 78.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_79 - CAS cycle count register for client 79.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_80 - CAS cycle count register for client 80.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_81 - CAS cycle count register for client 81.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_82 - CAS cycle count register for client 82.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_83 - CAS cycle count register for client 83.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_84 - CAS cycle count register for client 84.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_85 - CAS cycle count register for client 85.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_86 - CAS cycle count register for client 86.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_87 - CAS cycle count register for client 87.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_88 - CAS cycle count register for client 88.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_89 - CAS cycle count register for client 89.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_90 - CAS cycle count register for client 90.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_91 - CAS cycle count register for client 91.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_92 - CAS cycle count register for client 92.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_93 - CAS cycle count register for client 93.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_94 - CAS cycle count register for client 94.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_95 - CAS cycle count register for client 95.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_96 - CAS cycle count register for client 96.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_97 - CAS cycle count register for client 97.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_98 - CAS cycle count register for client 98.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_99 - CAS cycle count register for client 99.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_100 - CAS cycle count register for client 100.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_101 - CAS cycle count register for client 101.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_102 - CAS cycle count register for client 102.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_103 - CAS cycle count register for client 103.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_104 - CAS cycle count register for client 104.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_105 - CAS cycle count register for client 105.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_106 - CAS cycle count register for client 106.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_107 - CAS cycle count register for client 107.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_108 - CAS cycle count register for client 108.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_109 - CAS cycle count register for client 109.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_110 - CAS cycle count register for client 110.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_111 - CAS cycle count register for client 111.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_112 - CAS cycle count register for client 112.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_113 - CAS cycle count register for client 113.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_114 - CAS cycle count register for client 114.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_115 - CAS cycle count register for client 115.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_116 - CAS cycle count register for client 116.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_117 - CAS cycle count register for client 117.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_118 - CAS cycle count register for client 118.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_119 - CAS cycle count register for client 119.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_120 - CAS cycle count register for client 120.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_121 - CAS cycle count register for client 121.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_122 - CAS cycle count register for client 122.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_123 - CAS cycle count register for client 123.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_124 - CAS cycle count register for client 124.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_125 - CAS cycle count register for client 125.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_126 - CAS cycle count register for client 126.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_127 - CAS cycle count register for client 127.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_DEFAULT             4294967295
+
+/***************************************************************************
+ *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT    4294967295
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_CONTROL - MEMSYS Auto Init Control.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: reserved0 [31:10] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_MASK    0xfffffc00
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_SHIFT   10
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_DIVIDER [09:09] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_MASK 0x00000200
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_SHIFT 9
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_VDL_CALIB_AUTO_INIT [08:08] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_MASK 0x00000100
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_SHIFT 8
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_DRAM_INIT_DONE_SET [07:07] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_MASK 0x00000080
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_SHIFT 7
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_RESET [06:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_MASK 0x00000040
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_SET [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_READY_SET [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_AUTO_INIT_ACTIVE_RESET [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_MASK 0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_SHIFT 3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: SKIP_PHY_AUTO_INIT [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: MEMSYS_AUTO_INIT_START [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_STATUS - MEMSYS Auto Init Status.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_MASK     0xfffff000
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_SHIFT    12
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMC_AUTO_INIT_STATES [11:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_MASK 0x00000fc0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: AUTO_INIT_ACTIVE [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_STRAP_VALID [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_READY [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_MASK     0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_SHIFT    3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_DEFAULT  0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: DRAM_INIT_DONE [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_FAIL [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_DEFAULT 0
+
+/***************************************************************************
+ *PHY_VDL_CALIB_AUTO_INIT_OVERRIDE - PHY VDL calibrate override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PHY_VDL_CALIB_AUTO_INIT_OVERRIDE :: PHY_VDL_CALIB_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_DEFAULT 268435456
+
+/***************************************************************************
+ *SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE - SHIM PLL pndiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_PNDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_DEFAULT 598736896
+
+/***************************************************************************
+ *SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE - SHIM PLL mdiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_MDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_DEFAULT 4099
+
+#endif /* #ifndef BCHP_MEMC_DDR_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_misb_bridge.h b/include/linux/brcmstb/7358a0/bchp_misb_bridge.h
new file mode 100644
index 0000000..6a04b96
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_misb_bridge.h
@@ -0,0 +1,126 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:48:30 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_misb_bridge.h $
+ * 
+ * Hydra_Software_Devel/3   9/20/11 12:05p pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MISB_BRIDGE_H__
+#define BCHP_MISB_BRIDGE_H__
+
+/***************************************************************************
+ *MISB_BRIDGE - MISB_BRIDGE Registers
+ ***************************************************************************/
+#define BCHP_MISB_BRIDGE_CORE_REV_ID             0x00410400 /* MISB Bridge Revision ID Register. */
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET 0x00410404 /* "Exception Vector Offset Address" */
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID            0x00410408 /* Processor ID Register. */
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT       0x0041040c /* Write Gathering Mode & Timeout. */
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE         0x00410410 /* MISB Split Mode */
+
+/***************************************************************************
+ *CORE_REV_ID - MISB Bridge Revision ID Register.
+ ***************************************************************************/
+/* MISB_BRIDGE :: CORE_REV_ID :: reserved0 [31:16] */
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_reserved0_MASK                0xffff0000
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_reserved0_SHIFT               16
+
+/* MISB_BRIDGE :: CORE_REV_ID :: MAJOR [15:08] */
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MAJOR_MASK                    0x0000ff00
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MAJOR_SHIFT                   8
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MAJOR_DEFAULT                 0
+
+/* MISB_BRIDGE :: CORE_REV_ID :: MINOR [07:00] */
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MINOR_MASK                    0x000000ff
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MINOR_SHIFT                   0
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MINOR_DEFAULT                 4
+
+/***************************************************************************
+ *EXCEPTION_VECTOR_OFFSET - "Exception Vector Offset Address"
+ ***************************************************************************/
+/* MISB_BRIDGE :: EXCEPTION_VECTOR_OFFSET :: ADDRS [31:00] */
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET_ADDRS_MASK        0xffffffff
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET_ADDRS_SHIFT       0
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET_ADDRS_DEFAULT     0
+
+/***************************************************************************
+ *PROCESSOR_ID - Processor ID Register.
+ ***************************************************************************/
+/* MISB_BRIDGE :: PROCESSOR_ID :: reserved0 [31:08] */
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_reserved0_MASK               0xffffff00
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_reserved0_SHIFT              8
+
+/* MISB_BRIDGE :: PROCESSOR_ID :: ID [07:00] */
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_ID_MASK                      0x000000ff
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_ID_SHIFT                     0
+
+/***************************************************************************
+ *WG_MODE_N_TIMEOUT - Write Gathering Mode & Timeout.
+ ***************************************************************************/
+/* MISB_BRIDGE :: WG_MODE_N_TIMEOUT :: reserved0 [31:10] */
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_reserved0_MASK          0xfffffc00
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_reserved0_SHIFT         10
+
+/* MISB_BRIDGE :: WG_MODE_N_TIMEOUT :: MODE [09:08] */
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_MASK               0x00000300
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_SHIFT              8
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_DEFAULT            0
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_MODE_0             0
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_MODE_1             1
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_MODE_2             2
+
+/* MISB_BRIDGE :: WG_MODE_N_TIMEOUT :: TIMEOUT [07:00] */
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_TIMEOUT_MASK            0x000000ff
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_TIMEOUT_SHIFT           0
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_TIMEOUT_DEFAULT         100
+
+/***************************************************************************
+ *MISB_SPLIT_MODE - MISB Split Mode
+ ***************************************************************************/
+/* MISB_BRIDGE :: MISB_SPLIT_MODE :: reserved0 [31:01] */
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_reserved0_MASK            0xfffffffe
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_reserved0_SHIFT           1
+
+/* MISB_BRIDGE :: MISB_SPLIT_MODE :: SPLIT_MODE [00:00] */
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_SPLIT_MODE_MASK           0x00000001
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_SPLIT_MODE_SHIFT          0
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_SPLIT_MODE_DEFAULT        0
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_SPLIT_MODE_ENABLE         1
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_SPLIT_MODE_DISABLE        0
+
+#endif /* #ifndef BCHP_MISB_BRIDGE_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_nand.h b/include/linux/brcmstb/7358a0/bchp_nand.h
new file mode 100644
index 0000000..d0dd5f8
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_nand.h
@@ -0,0 +1,2260 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:39:49 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_nand.h $
+ * 
+ * Hydra_Software_Devel/3   9/20/11 12:07p pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_NAND_H__
+#define BCHP_NAND_H__
+
+/***************************************************************************
+ *NAND - Nand Flash Control Registers
+ ***************************************************************************/
+#define BCHP_NAND_REVISION                       0x00412800 /* NAND Revision */
+#define BCHP_NAND_CMD_START                      0x00412804 /* Nand Flash Command Start */
+#define BCHP_NAND_CMD_EXT_ADDRESS                0x00412808 /* Nand Flash Command Extended Address */
+#define BCHP_NAND_CMD_ADDRESS                    0x0041280c /* Nand Flash Command Address */
+#define BCHP_NAND_CMD_END_ADDRESS                0x00412810 /* Nand Flash Command End Address */
+#define BCHP_NAND_CS_NAND_SELECT                 0x00412814 /* Nand Flash EBI CS Select */
+#define BCHP_NAND_CS_NAND_XOR                    0x00412818 /* Nand Flash EBI CS Address XOR with 1FC0 Control */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0          0x00412820 /* Nand Flash Spare Area Read Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4          0x00412824 /* Nand Flash Spare Area Read Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8          0x00412828 /* Nand Flash Spare Area Read Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C          0x0041282c /* Nand Flash Spare Area Read Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0         0x00412830 /* Nand Flash Spare Area Write Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4         0x00412834 /* Nand Flash Spare Area Write Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8         0x00412838 /* Nand Flash Spare Area Write Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C         0x0041283c /* Nand Flash Spare Area Write Bytes 12-15 */
+#define BCHP_NAND_ACC_CONTROL                    0x00412840 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG                         0x00412848 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1                       0x00412850 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2                       0x00412854 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SEMAPHORE                      0x00412858 /* Semaphore */
+#define BCHP_NAND_FLASH_DEVICE_ID                0x00412860 /* Nand Flash Device ID */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT            0x00412864 /* Nand Flash Extended Device ID */
+#define BCHP_NAND_BLOCK_LOCK_STATUS              0x00412868 /* Nand Flash Block Lock Status */
+#define BCHP_NAND_INTFC_STATUS                   0x0041286c /* Nand Flash Interface Status */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR              0x00412870 /* ECC Correctable Error Extended Address */
+#define BCHP_NAND_ECC_CORR_ADDR                  0x00412874 /* ECC Correctable Error Address */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR               0x00412878 /* ECC Uncorrectable Error Extended Address */
+#define BCHP_NAND_ECC_UNC_ADDR                   0x0041287c /* ECC Uncorrectable Error Address */
+#define BCHP_NAND_READ_ERROR_COUNT               0x00412880 /* Read Error Count */
+#define BCHP_NAND_CORR_STAT_THRESHOLD            0x00412884 /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_ONFI_STATUS                    0x00412888 /* ONFI Status */
+#define BCHP_NAND_ONFI_DEBUG_DATA                0x0041288c /* ONFI Debug Data */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR            0x00412890 /* Flash Read Data Extended Address */
+#define BCHP_NAND_FLASH_READ_ADDR                0x00412894 /* Flash Read Data Address */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR          0x00412898 /* Page Program Extended Address */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR              0x0041289c /* Page Program Address */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR             0x004128a0 /* Copy Back Extended Address */
+#define BCHP_NAND_COPY_BACK_ADDR                 0x004128a4 /* Copy Back Address */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR           0x004128a8 /* Block Erase Extended Address */
+#define BCHP_NAND_BLOCK_ERASE_ADDR               0x004128ac /* Block Erase Address */
+#define BCHP_NAND_INV_READ_EXT_ADDR              0x004128b0 /* Flash Invalid Data Extended Address */
+#define BCHP_NAND_INV_READ_ADDR                  0x004128b4 /* Flash Invalid Data Address */
+#define BCHP_NAND_BLK_WR_PROTECT                 0x004128c0 /* Block Write Protect Enable and Size for EBI_CS0b */
+#define BCHP_NAND_ACC_CONTROL_CS1                0x004128d0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS1                     0x004128d4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS1                   0x004128d8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS1                   0x004128dc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS2                0x004128e0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS2                     0x004128e4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS2                   0x004128e8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS2                   0x004128ec /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS3                0x004128f0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS3                     0x004128f4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS3                   0x004128f8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS3                   0x004128fc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS4                0x00412900 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS4                     0x00412904 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS4                   0x00412908 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS4                   0x0041290c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10         0x00412930 /* Nand Flash Spare Area Read Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14         0x00412934 /* Nand Flash Spare Area Read Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18         0x00412938 /* Nand Flash Spare Area Read Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C         0x0041293c /* Nand Flash Spare Area Read Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10        0x00412940 /* Nand Flash Spare Area Write Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14        0x00412944 /* Nand Flash Spare Area Write Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18        0x00412948 /* Nand Flash Spare Area Write Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C        0x0041294c /* Nand Flash Spare Area Write Bytes 28-31 */
+#define BCHP_NAND_LL_OP                          0x00412978 /* Nand Flash Low Level Operation */
+#define BCHP_NAND_LL_RDDATA                      0x0041297c /* Nand Flash Low Level Read Data */
+
+/***************************************************************************
+ *REVISION - NAND Revision
+ ***************************************************************************/
+/* NAND :: REVISION :: 8KB_PAGE_SUPPORT [31:31] */
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_MASK                   0x80000000
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_SHIFT                  31
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_DEFAULT                1
+
+/* NAND :: REVISION :: reserved0 [30:16] */
+#define BCHP_NAND_REVISION_reserved0_MASK                          0x7fff0000
+#define BCHP_NAND_REVISION_reserved0_SHIFT                         16
+
+/* NAND :: REVISION :: MAJOR [15:08] */
+#define BCHP_NAND_REVISION_MAJOR_MASK                              0x0000ff00
+#define BCHP_NAND_REVISION_MAJOR_SHIFT                             8
+#define BCHP_NAND_REVISION_MAJOR_DEFAULT                           5
+
+/* NAND :: REVISION :: MINOR [07:00] */
+#define BCHP_NAND_REVISION_MINOR_MASK                              0x000000ff
+#define BCHP_NAND_REVISION_MINOR_SHIFT                             0
+#define BCHP_NAND_REVISION_MINOR_DEFAULT                           0
+
+/***************************************************************************
+ *CMD_START - Nand Flash Command Start
+ ***************************************************************************/
+/* NAND :: CMD_START :: reserved0 [31:29] */
+#define BCHP_NAND_CMD_START_reserved0_MASK                         0xe0000000
+#define BCHP_NAND_CMD_START_reserved0_SHIFT                        29
+
+/* NAND :: CMD_START :: OPCODE [28:24] */
+#define BCHP_NAND_CMD_START_OPCODE_MASK                            0x1f000000
+#define BCHP_NAND_CMD_START_OPCODE_SHIFT                           24
+#define BCHP_NAND_CMD_START_OPCODE_DEFAULT                         0
+#define BCHP_NAND_CMD_START_OPCODE_NULL                            0
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ                       1
+#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ                 2
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ                     3
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE                    4
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA              5
+#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK                       6
+#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ                  7
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE                     8
+#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET                     9
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK                     10
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN                11
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK                   12
+#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS         13
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ                  14
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL            15
+#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP                    16
+
+/* NAND :: CMD_START :: reserved1 [23:00] */
+#define BCHP_NAND_CMD_START_reserved1_MASK                         0x00ffffff
+#define BCHP_NAND_CMD_START_reserved1_SHIFT                        0
+
+/***************************************************************************
+ *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
+ ***************************************************************************/
+/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK                   0xfff80000
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT                  19
+
+/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK                      0x00070000
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT                     16
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT                   0
+
+/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK                 0x0000ffff
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT                0
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT              0
+
+/***************************************************************************
+ *CMD_ADDRESS - Nand Flash Command Address
+ ***************************************************************************/
+/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK                         0xffffffff
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT                        0
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT                      0
+
+/***************************************************************************
+ *CMD_END_ADDRESS - Nand Flash Command End Address
+ ***************************************************************************/
+/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT                    0
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT                  0
+
+/***************************************************************************
+ *CS_NAND_SELECT - Nand Flash EBI CS Select
+ ***************************************************************************/
+/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT                     31
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT                   0
+
+/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK        0x40000000
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT       30
+
+/* NAND :: CS_NAND_SELECT :: reserved0 [29:29] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK                    0x20000000
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT                   29
+
+/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK              0x10000000
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT             28
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT           0
+
+/* NAND :: CS_NAND_SELECT :: reserved1 [27:16] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_MASK                    0x0fff0000
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_SHIFT                   16
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK           0x00008000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT          15
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK           0x00004000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT          14
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK           0x00002000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT          13
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK           0x00001000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT          12
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK           0x00000800
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT          11
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK           0x00000400
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT          10
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK           0x00000200
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT          9
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK           0x00000100
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT          8
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK                 0x00000080
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT                7
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK                 0x00000040
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT                6
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK                 0x00000020
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT                5
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK                 0x00000010
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT                4
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK                 0x00000008
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT                3
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK                 0x00000004
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT                2
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK                 0x00000002
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT                1
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK                 0x00000001
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT                0
+
+/***************************************************************************
+ *CS_NAND_XOR - Nand Flash EBI CS Address XOR with 1FC0 Control
+ ***************************************************************************/
+/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_1FC0_XOR [31:31] */
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_MASK           0x80000000
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_SHIFT          31
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_DEFAULT        0
+
+/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
+#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK                       0x7fffff00
+#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT                      8
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_1FC0_XOR [07:07] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_MASK          0x00000080
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_SHIFT         7
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_1FC0_XOR [06:06] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_MASK          0x00000040
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_SHIFT         6
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_1FC0_XOR [05:05] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_MASK          0x00000020
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_SHIFT         5
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_1FC0_XOR [04:04] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_MASK          0x00000010
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_SHIFT         4
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_1FC0_XOR [03:03] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_MASK          0x00000008
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_SHIFT         3
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_1FC0_XOR [02:02] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_MASK          0x00000004
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_SHIFT         2
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_1FC0_XOR [01:01] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_MASK          0x00000002
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_SHIFT         1
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_1FC0_XOR [00:00] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_MASK          0x00000001
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_SHIFT         0
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT         255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT         255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT       255
+
+/***************************************************************************
+ *ACC_CONTROL - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_MASK                       0x80000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_SHIFT                      31
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_DEFAULT                    1
+
+/* NAND :: ACC_CONTROL :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_MASK                       0x40000000
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_SHIFT                      30
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_DEFAULT                    1
+
+/* NAND :: ACC_CONTROL :: RD_ECC_BLK0_EN [29:29] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_MASK                  0x20000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_SHIFT                 29
+
+/* NAND :: ACC_CONTROL :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_SHIFT                  28
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_MASK                0x08000000
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_SHIFT               27
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_DEFAULT             0
+
+/* NAND :: ACC_CONTROL :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_MASK                 0x04000000
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_SHIFT                26
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_MASK                   0x02000000
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_SHIFT                  25
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_MASK                     0x01000000
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_SHIFT                    24
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_DEFAULT                  1
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL_0 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_MASK                     0x00f00000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_SHIFT                    20
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_DEFAULT                  15
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_MASK                       0x000f0000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_SHIFT                      16
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_DEFAULT                    15
+
+/* NAND :: ACC_CONTROL :: reserved0 [15:15] */
+#define BCHP_NAND_ACC_CONTROL_reserved0_MASK                       0x00008000
+#define BCHP_NAND_ACC_CONTROL_reserved0_SHIFT                      15
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K_0 [14:14] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_MASK                0x00004000
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_SHIFT               14
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_DEFAULT             0
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE_0 [13:08] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_MASK               0x00003f00
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_SHIFT              8
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_DEFAULT            16
+
+/* NAND :: ACC_CONTROL :: reserved1 [07:07] */
+#define BCHP_NAND_ACC_CONTROL_reserved1_MASK                       0x00000080
+#define BCHP_NAND_ACC_CONTROL_reserved1_SHIFT                      7
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_MASK                  0x00000040
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_SHIFT                 6
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_DEFAULT               0
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_MASK                 0x0000003f
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_SHIFT                0
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_DEFAULT              16
+
+/***************************************************************************
+ *CONFIG - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_MASK                          0x80000000
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_SHIFT                         31
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_DEFAULT                       0
+
+/* NAND :: CONFIG :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_MASK                           0x70000000
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_SHIFT                          28
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_2048KB                 6
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_1024KB                 5
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_512KB                  3
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_128KB                  1
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_16KB                   0
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_8KB                    2
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_256KB                  4
+
+/* NAND :: CONFIG :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_MASK                          0x0f000000
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_SHIFT                         24
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4MB                  0
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8MB                  1
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16MB                 2
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32MB                 3
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64MB                 4
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128MB                5
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_256MB                6
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_512MB                7
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_1GB                  8
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_2GB                  9
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4GB                  10
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8GB                  11
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16GB                 12
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32GB                 13
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64GB                 14
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128GB                15
+
+/* NAND :: CONFIG :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_MASK                         0x00800000
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_SHIFT                        23
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_8                  0
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_16                 1
+
+/* NAND :: CONFIG :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_reserved0_MASK                            0x00400000
+#define BCHP_NAND_CONFIG_reserved0_SHIFT                           22
+
+/* NAND :: CONFIG :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_PAGE_SIZE_MASK                            0x00300000
+#define BCHP_NAND_CONFIG_PAGE_SIZE_SHIFT                           20
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_512                     0
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_2KB                     1
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_4KB                     2
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_8KB                     3
+
+/* NAND :: CONFIG :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_reserved1_MASK                            0x00080000
+#define BCHP_NAND_CONFIG_reserved1_SHIFT                           19
+
+/* NAND :: CONFIG :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_MASK                        0x00070000
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_SHIFT                       16
+
+/* NAND :: CONFIG :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_reserved2_MASK                            0x00008000
+#define BCHP_NAND_CONFIG_reserved2_SHIFT                           15
+
+/* NAND :: CONFIG :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_MASK                        0x00007000
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_SHIFT                       12
+
+/* NAND :: CONFIG :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_reserved3_MASK                            0x00000800
+#define BCHP_NAND_CONFIG_reserved3_SHIFT                           11
+
+/* NAND :: CONFIG :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_MASK                        0x00000700
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_SHIFT                       8
+
+/* NAND :: CONFIG :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_reserved4_MASK                            0x000000ff
+#define BCHP_NAND_CONFIG_reserved4_SHIFT                           0
+
+/***************************************************************************
+ *TIMING_1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_tWP_MASK                                0xf0000000
+#define BCHP_NAND_TIMING_1_tWP_SHIFT                               28
+#define BCHP_NAND_TIMING_1_tWP_DEFAULT                             6
+
+/* NAND :: TIMING_1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_tWH_MASK                                0x0f000000
+#define BCHP_NAND_TIMING_1_tWH_SHIFT                               24
+#define BCHP_NAND_TIMING_1_tWH_DEFAULT                             5
+
+/* NAND :: TIMING_1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_tRP_MASK                                0x00f00000
+#define BCHP_NAND_TIMING_1_tRP_SHIFT                               20
+#define BCHP_NAND_TIMING_1_tRP_DEFAULT                             7
+
+/* NAND :: TIMING_1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_tREH_MASK                               0x000f0000
+#define BCHP_NAND_TIMING_1_tREH_SHIFT                              16
+#define BCHP_NAND_TIMING_1_tREH_DEFAULT                            4
+
+/* NAND :: TIMING_1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_tCS_MASK                                0x0000f000
+#define BCHP_NAND_TIMING_1_tCS_SHIFT                               12
+#define BCHP_NAND_TIMING_1_tCS_DEFAULT                             8
+
+/* NAND :: TIMING_1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_tCLH_MASK                               0x00000f00
+#define BCHP_NAND_TIMING_1_tCLH_SHIFT                              8
+#define BCHP_NAND_TIMING_1_tCLH_DEFAULT                            4
+
+/* NAND :: TIMING_1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_tALH_MASK                               0x000000f0
+#define BCHP_NAND_TIMING_1_tALH_SHIFT                              4
+#define BCHP_NAND_TIMING_1_tALH_DEFAULT                            5
+
+/* NAND :: TIMING_1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_tADL_MASK                               0x0000000f
+#define BCHP_NAND_TIMING_1_tADL_SHIFT                              0
+#define BCHP_NAND_TIMING_1_tADL_DEFAULT                            11
+
+/***************************************************************************
+ *TIMING_2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CLK_SELECT_MASK                         0x80000000
+#define BCHP_NAND_TIMING_2_CLK_SELECT_SHIFT                        31
+#define BCHP_NAND_TIMING_2_CLK_SELECT_DEFAULT                      0
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_108                      0
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_216                      1
+
+/* NAND :: TIMING_2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_reserved0_MASK                          0x7fffe000
+#define BCHP_NAND_TIMING_2_reserved0_SHIFT                         13
+
+/* NAND :: TIMING_2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_tWB_MASK                                0x00001e00
+#define BCHP_NAND_TIMING_2_tWB_SHIFT                               9
+#define BCHP_NAND_TIMING_2_tWB_DEFAULT                             15
+
+/* NAND :: TIMING_2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_tWHR_MASK                               0x000001f0
+#define BCHP_NAND_TIMING_2_tWHR_SHIFT                              4
+#define BCHP_NAND_TIMING_2_tWHR_DEFAULT                            9
+
+/* NAND :: TIMING_2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_tREAD_MASK                              0x0000000f
+#define BCHP_NAND_TIMING_2_tREAD_SHIFT                             0
+#define BCHP_NAND_TIMING_2_tREAD_DEFAULT                           6
+
+/***************************************************************************
+ *SEMAPHORE - Semaphore
+ ***************************************************************************/
+/* NAND :: SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_NAND_SEMAPHORE_reserved0_MASK                         0xffffff00
+#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT                        8
+
+/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK                    0x000000ff
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT                   0
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT                 0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID - Nand Flash Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK                      0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT                     24
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK                      0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT                     16
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK                      0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT                     8
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK                      0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT                     0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK                  0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT                 24
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK                  0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT                 16
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK                  0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT                 8
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK                  0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT                 0
+
+/***************************************************************************
+ *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
+ ***************************************************************************/
+/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT                8
+
+/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK                    0x000000ff
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT                   0
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT                 0
+
+/***************************************************************************
+ *INTFC_STATUS - Nand Flash Interface Status
+ ***************************************************************************/
+/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK                     0x80000000
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT                    31
+
+/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK                    0x40000000
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT                   30
+
+/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK                    0x20000000
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT                   29
+
+/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK               0x10000000
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT              28
+
+/* NAND :: INTFC_STATUS :: ERASED [27:27] */
+#define BCHP_NAND_INTFC_STATUS_ERASED_MASK                         0x08000000
+#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT                        27
+
+/* NAND :: INTFC_STATUS :: reserved0 [26:08] */
+#define BCHP_NAND_INTFC_STATUS_reserved0_MASK                      0x07ffff00
+#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT                     8
+
+/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK                   0x000000ff
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT                  0
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT                0
+
+/***************************************************************************
+ *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT                 0
+
+/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT            0
+
+/***************************************************************************
+ *ECC_CORR_ADDR - ECC Correctable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT                    0
+
+/***************************************************************************
+ *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK                  0xfff80000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT                 19
+
+/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK                     0x00070000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT                    16
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT                  0
+
+/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK                0x0000ffff
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT               0
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT             0
+
+/***************************************************************************
+ *ECC_UNC_ADDR - ECC Uncorrectable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK                        0xffffffff
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT                       0
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT                     0
+
+/***************************************************************************
+ *READ_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT        0
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:05] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK               0xffffffe0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT              5
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD [04:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_MASK     0x0000001f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_SHIFT    0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_DEFAULT  1
+
+/***************************************************************************
+ *ONFI_STATUS - ONFI Status
+ ***************************************************************************/
+/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK                  0xf0000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT                 28
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT               0
+
+/* NAND :: ONFI_STATUS :: reserved0 [27:06] */
+#define BCHP_NAND_ONFI_STATUS_reserved0_MASK                       0x0fffffc0
+#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT                      6
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK              0x00000020
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT             5
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK              0x00000010
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT             4
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK              0x00000008
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT             3
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK              0x00000004
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT             2
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK              0x00000002
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT             1
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK              0x00000001
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT             0
+
+/***************************************************************************
+ *ONFI_DEBUG_DATA - ONFI Debug Data
+ ***************************************************************************/
+/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK             0xffffffff
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT            0
+
+/***************************************************************************
+ *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK               0xfff80000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT              19
+
+/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK                  0x00070000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT                 16
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT               0
+
+/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK             0x0000ffff
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT            0
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT          0
+
+/***************************************************************************
+ *FLASH_READ_ADDR - Flash Read Data Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT                    0
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT                  0
+
+/***************************************************************************
+ *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK             0xfff80000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT            19
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK                0x00070000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT               16
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT             0
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK           0x0000ffff
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT          0
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT        0
+
+/***************************************************************************
+ *PROGRAM_PAGE_ADDR - Page Program Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK                   0xffffffff
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT                  0
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT                0
+
+/***************************************************************************
+ *COPY_BACK_EXT_ADDR - Copy Back Extended Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK                0xfff80000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT               19
+
+/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK                   0x00070000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT                  16
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT                0
+
+/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK              0x0000ffff
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT             0
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT           0
+
+/***************************************************************************
+ *COPY_BACK_ADDR - Copy Back Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK                      0xffffffff
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT                     0
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT                   0
+
+/***************************************************************************
+ *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK              0xfff80000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT             19
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK                 0x00070000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT                16
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT              0
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK            0x0000ffff
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT           0
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT         0
+
+/***************************************************************************
+ *BLOCK_ERASE_ADDR - Block Erase Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK                    0xffffffff
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT                   0
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT                 0
+
+/***************************************************************************
+ *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
+ ***************************************************************************/
+/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT                 0
+
+/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT            0
+
+/***************************************************************************
+ *INV_READ_ADDR - Flash Invalid Data Address
+ ***************************************************************************/
+/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT                    0
+
+/***************************************************************************
+ *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
+ ***************************************************************************/
+/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK                 0xffffffff
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT                0
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT              0
+
+/***************************************************************************
+ *ACC_CONTROL_CS1 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS1 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS1 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS1 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS1 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS1_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS1 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS1 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS1_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS1_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS1_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS1_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS1_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS1_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS1_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS1_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS1_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS1_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS1_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS1 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS1 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS1_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS2 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS2 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS2 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS2 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS2 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS2_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS2 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS2 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS2_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS2_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS2_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS2_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS2 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS2_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS2_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS2_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS2_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS2_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS2_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS2_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS2_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS3 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS3 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS3 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS3 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS3 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS3_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS3 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS3 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS3_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS3_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS3_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS3_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS3 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS3_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS3_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS3_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS3_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS3_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS3_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS3_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS3 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS3 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS3_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS4 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS4 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS4 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS4 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS4 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS4_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS4 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS4 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS4_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS4_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS4_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS4_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS4 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS4_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS4_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS4_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS4_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS4_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS4_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS4_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS4 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS4 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS4_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT      255
+
+/***************************************************************************
+ *LL_OP - Nand Flash Low Level Operation
+ ***************************************************************************/
+/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
+#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK                           0x80000000
+#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT                          31
+#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT                        0
+
+/* NAND :: LL_OP :: reserved0 [30:20] */
+#define BCHP_NAND_LL_OP_reserved0_MASK                             0x7ff00000
+#define BCHP_NAND_LL_OP_reserved0_SHIFT                            20
+
+/* NAND :: LL_OP :: CLE [19:19] */
+#define BCHP_NAND_LL_OP_CLE_MASK                                   0x00080000
+#define BCHP_NAND_LL_OP_CLE_SHIFT                                  19
+#define BCHP_NAND_LL_OP_CLE_DEFAULT                                0
+
+/* NAND :: LL_OP :: ALE [18:18] */
+#define BCHP_NAND_LL_OP_ALE_MASK                                   0x00040000
+#define BCHP_NAND_LL_OP_ALE_SHIFT                                  18
+#define BCHP_NAND_LL_OP_ALE_DEFAULT                                0
+
+/* NAND :: LL_OP :: WE [17:17] */
+#define BCHP_NAND_LL_OP_WE_MASK                                    0x00020000
+#define BCHP_NAND_LL_OP_WE_SHIFT                                   17
+#define BCHP_NAND_LL_OP_WE_DEFAULT                                 0
+
+/* NAND :: LL_OP :: RE [16:16] */
+#define BCHP_NAND_LL_OP_RE_MASK                                    0x00010000
+#define BCHP_NAND_LL_OP_RE_SHIFT                                   16
+#define BCHP_NAND_LL_OP_RE_DEFAULT                                 0
+
+/* NAND :: LL_OP :: DATA [15:00] */
+#define BCHP_NAND_LL_OP_DATA_MASK                                  0x0000ffff
+#define BCHP_NAND_LL_OP_DATA_SHIFT                                 0
+#define BCHP_NAND_LL_OP_DATA_DEFAULT                               0
+
+/***************************************************************************
+ *LL_RDDATA - Nand Flash Low Level Read Data
+ ***************************************************************************/
+/* NAND :: LL_RDDATA :: reserved0 [31:16] */
+#define BCHP_NAND_LL_RDDATA_reserved0_MASK                         0xffff0000
+#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT                        16
+
+/* NAND :: LL_RDDATA :: DATA [15:00] */
+#define BCHP_NAND_LL_RDDATA_DATA_MASK                              0x0000ffff
+#define BCHP_NAND_LL_RDDATA_DATA_SHIFT                             0
+#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT                           0
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE                          0x00412a00
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_START                         0
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_END                           127
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE                  32
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+/* NAND :: FLASH_CACHEi :: WORD [31:00] */
+#define BCHP_NAND_FLASH_CACHEi_WORD_MASK                           0xffffffff
+#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT                          0
+
+
+#endif /* #ifndef BCHP_NAND_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/7358a0/bchp_sun_top_ctrl.h
new file mode 100644
index 0000000..aedb2fe
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_sun_top_ctrl.h
@@ -0,0 +1,6324 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:48:00 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_sun_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/6   9/20/11 12:21p pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SUN_TOP_CTRL_H__
+#define BCHP_SUN_TOP_CTRL_H__
+
+/***************************************************************************
+ *SUN_TOP_CTRL - Top Control registers
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID         0x00404000 /* Chip family ID */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID             0x00404004 /* Product Revision ID */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x0040401c /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x00404020 /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x00404024 /* Bond option value register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x00404028 /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x0040402c /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x00404030 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x00404034 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x00404038 /* Semaphore channel 0 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x0040403c /* Semaphore channel 1 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x00404040 /* Semaphore channel 2 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x00404044 /* Semaphore channel 3 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x00404048 /* Semaphore channel 4 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x0040404c /* Semaphore channel 5 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x00404050 /* Semaphore channel 6 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x00404054 /* Semaphore channel 7 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x00404058 /* Semaphore channel 8 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x0040405c /* Semaphore channel 9 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x00404060 /* Semaphore channel 10 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x00404064 /* Semaphore channel 11 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x00404068 /* Semaphore channel 12 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x0040406c /* Semaphore channel 13 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x00404070 /* Semaphore channel 14 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x00404074 /* Semaphore channel 15 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x00404078 /* General watchdog timer 0 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x0040407c /* General watchdog timer 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x00404080 /* General control register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x00404084 /* General control register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x00404088 /* General control register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x0040408c /* General control register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x00404090 /* General control register 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x00404094 /* General control register 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x00404098 /* General status register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x0040409c /* General status register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x004040a0 /* General status register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x00404100 /* Pinmux control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x00404104 /* Pinmux control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x00404108 /* Pinmux control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x0040410c /* Pinmux control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x00404110 /* Pinmux control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x00404114 /* Pinmux control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x00404118 /* Pinmux control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x0040411c /* Pinmux control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x00404120 /* Pinmux control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x00404124 /* Pinmux control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10        0x00404128 /* Pinmux control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11        0x0040412c /* Pinmux control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12        0x00404130 /* Pinmux control register 12 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13        0x00404134 /* Pinmux control register 13 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14        0x00404138 /* Pinmux control register 14 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15        0x0040413c /* Pinmux control register 15 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16        0x00404140 /* Pinmux control register 16 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x00404144 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x00404148 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x0040414c /* Pad pull-up/pull-down control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x00404150 /* Pad pull-up/pull-down control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x00404154 /* Pad pull-up/pull-down control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5     0x00404158 /* Pad pull-up/pull-down control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6     0x0040415c /* Pad pull-up/pull-down control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7     0x00404160 /* Pad pull-up/pull-down control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8     0x00404164 /* Pad pull-up/pull-down control register 8 */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x00404168 /* Bypass clock unselect register 0 */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x00404300 /* Reset control */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE    0x00404304 /* Reset source enable */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET        0x00404308 /* Software master reset */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION     0x0040430c /* Hardware reset extension */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR          0x00404310 /* Reset Monitor */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x00404314 /* Reset history */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET          0x00404318 /* Software init 0 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR        0x0040431c /* Software init 0 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS       0x00404320 /* Software init 0 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR  0x00404324 /* Security software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET          0x00404330 /* Software init 1 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR        0x00404334 /* Software init 1 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS       0x00404338 /* Software init 1 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR  0x0040433c /* Security software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x00404364 /* Scratch register */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x00404368 /* Spare control bits reserved for future use */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x00404380 /* Test port control */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x00404384 /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x00404388 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x0040438c /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x00404390 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x00404394 /* EJTAG input bus enables */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x00404398 /* EJTAG output select */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL        0x0040439c /* UART Router select */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL             0x004043a0 /* VTRAP Control */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS           0x004043a4 /* VTRAP Status */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x00404400 /* Serial Slave Port configuration register */
+#define BCHP_SUN_TOP_CTRL_SERS_REV               0x00404420 /* SERS Revision Register */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x00404424 /* SERS Configuration Register */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x00404514 /* Block select for RO testmode */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION     0x00404518 /* Test configuration */
+
+/***************************************************************************
+ *CHIP_FAMILY_ID - Chip family ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT    1935147008
+
+/***************************************************************************
+ *PRODUCT_ID - Product Revision ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK               0xffffffff
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT            1935147008
+
+/***************************************************************************
+ *BSP_FEATURE_TABLE_ADDR - BSP feature table address
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_VALUE_0 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [07:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT   7
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [03:03] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_DEFAULT 0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd [02:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_MASK            0x00000007
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_DEFAULT         0
+
+/***************************************************************************
+ *STRAP_VALUE_1 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xfffffff0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            4
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias_sel [03:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_MASK  0x0000000e
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_DEFAULT 4
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK     0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT  1
+
+/***************************************************************************
+ *BOND_STATUS - Bond option value register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1
+
+/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_0 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_1 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_0 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_isdbt_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_isdbt_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_isdbt_disable_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_isdbt_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_genet_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet_disable_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avc_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_2 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_directv_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_3 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tuner_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tuner_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tuner_disable_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tuner_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hd_display_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ephy_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tfec_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ldpc_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spares [14:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spares_MASK 0x00007c00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spares_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spares_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_1 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_31_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_31_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_DEFAULT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_0 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_1 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_0 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_isdbt_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_isdbt_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_isdbt_disable_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_genet_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet_disable_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avc_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avc_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avc_disable_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_2 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_2_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_2_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_directv_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_3 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_3_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_3_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tuner_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tuner_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tuner_disable_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hd_display_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ephy_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tfec_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec_disable_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ldpc_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc_disable_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spares [14:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spares_MASK 0x00007c00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spares_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_1 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_31_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_SHIFT 0
+
+/***************************************************************************
+ *SEMAPHORE_0 - Semaphore channel 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_1 - Semaphore channel 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_2 - Semaphore channel 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_3 - Semaphore channel 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_4 - Semaphore channel 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_5 - Semaphore channel 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_6 - Semaphore channel 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_7 - Semaphore channel 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_8 - Semaphore channel 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_9 - Semaphore channel 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_10 - Semaphore channel 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_11 - Semaphore channel 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_12 - Semaphore channel 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_13 - Semaphore channel 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_14 - Semaphore channel 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_15 - Semaphore channel 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *GEN_WATCHDOG_0 - General watchdog timer 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0
+
+/***************************************************************************
+ *GEN_WATCHDOG_1 - General watchdog timer 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_reserved0_MASK            0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_reserved0_SHIFT           8
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ib2_source [07:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ib2_source_MASK           0x000000f0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ib2_source_SHIFT          4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ib2_source_DEFAULT        0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ib1_source [03:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ib1_source_MASK           0x0000000c
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ib1_source_SHIFT          2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ib1_source_DEFAULT        0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ib0_source [01:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ib0_source_MASK           0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ib0_source_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ib0_source_DEFAULT        0
+
+/***************************************************************************
+ *GENERAL_CTRL_1 - General control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0xffff0000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           16
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_2 - General control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: usb0_pwrflt_2_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: usb0_pwrflt_1_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_3 - General control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_4 - General control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_5 - General control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK          0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT         8
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_1 - General status register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_2 - General status register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   8
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_mode [07:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_MASK 0x000000f0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_mode [03:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK    0xffff8000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT   15
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_vregcntl [14:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_MASK 0x00007ffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_pwrdn [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_MASK    0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_SHIFT   1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_vregcntl_en [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_DEFAULT 1
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK    0xff000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT   24
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: mii_drive_src_0 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: mii_drive_sel_0 [22:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_MASK 0x00700000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_4 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_4_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_4_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_4 [18:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_MASK 0x00070000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_3 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_3_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_3_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_3 [14:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_MASK 0x00007000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_2 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_2_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_2_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_2 [10:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_MASK 0x00000700
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_1 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_1_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_1_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_1 [06:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_MASK 0x00000070
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_0 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_0_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_0_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_0 [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_16MA 7
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xffc00000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   22
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_pwrdn [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_MASK    0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_SHIFT   21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_vregcntl [20:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_MASK 0x001ffffe
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_vregcntl_en [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_DEFAULT 1
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_DEFAULT 0
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_02 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_GPIO_02           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_EBI_ADDR2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MII_TX_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_PM_GPIO_02        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_01 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_GPIO_01           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_EBI_ADDR1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MII_RX_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_PM_GPIO_01        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_00 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_GPIO_00           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_EBI_ADDR0         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MII_RX_DV         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_PM_GPIO_00        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_sck [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_MASK               0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_SHIFT              16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_DEFAULT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_SF_SCK             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_PM_SF_SCK          1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_mosi [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_SF_MOSI           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_PM_SF_MOSI        1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_miso [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_SF_MISO           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_PM_SF_MISO        1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_24 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_GPIO_24           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_SDS0_DSEC_TXEN    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_OOB_AGC_CTL       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_PM_GPIO_24        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_23 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_GPIO_23           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_SDS0_DSEC_TXOUT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_DS_AGC_CTL        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_PM_GPIO_23        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_10 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_GPIO_10           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_EBI_ADDR10        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MII_TXD_00        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_PM_GPIO_10        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_09 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_GPIO_09           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_EBI_ADDR9         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MII_TXD_01        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_PM_GPIO_09        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_08 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_GPIO_08           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_EBI_ADDR8         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MII_TXD_02        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_PM_GPIO_08        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_07 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_GPIO_07           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_EBI_ADDR7         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_MII_TXD_03        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_PM_GPIO_07        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_06 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_GPIO_06           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_EBI_ADDR6         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_MII_RXD_00        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_PM_GPIO_06        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_05 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_GPIO_05           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_EBI_ADDR5         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_MII_RXD_01        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_PM_GPIO_05        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_04 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_GPIO_04           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_EBI_ADDR4         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_MII_RXD_02        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_PM_GPIO_04        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_03 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_GPIO_03           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_EBI_ADDR3         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_MII_RXD_03        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_PM_GPIO_03        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_18 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_GPIO_18           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_EBI_CS0B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_PM_GPIO_18        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_17 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_GPIO_17           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_EBI_RWB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_PM_GPIO_17        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_16 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_GPIO_16           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_EBI_WE1B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_PM_GPIO_16        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_15 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_GPIO_15           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_EBI_WAITB         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_PM_GPIO_15        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_14 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_GPIO_14           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_EBI_ADDR14        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_MII_COL           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_PM_GPIO_14        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_13 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_GPIO_13           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_EBI_ADDR13        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_MII_TX_ER         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_PM_GPIO_13        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_12 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_GPIO_12           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_EBI_ADDR12        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_MII_RX_ER         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_PM_GPIO_12        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_11 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_GPIO_11           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_EBI_ADDR11        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_MII_TX_EN         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_PM_GPIO_11        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_28 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_GPIO_28           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_EBI_DATA3         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_TP_OUT_23         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_TP_IN_23          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_PM_GPIO_28        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_27 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_GPIO_27           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_EBI_DATA2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_TP_OUT_22         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_TP_IN_22          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_PM_GPIO_27        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_26 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_GPIO_26           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_EBI_DATA1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_TP_OUT_21         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_TP_IN_21          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_PM_GPIO_26        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_25 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_GPIO_25           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_EBI_DATA0         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_TP_OUT_20         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_TP_IN_20          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_PM_GPIO_25        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_22 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_GPIO_22           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_EBI_CS4B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_SPI_M_SS0B        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_PM_GPIO_22        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_21 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_GPIO_21           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_EBI_CS3B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_PM_GPIO_21        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_20 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_GPIO_20           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_EBI_CS2B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_TP_OUT_07         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_PM_GPIO_20        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_19 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_GPIO_19           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_EBI_CS1B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_PM_GPIO_19        2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_4 - Pinmux control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_36 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_GPIO_36           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_EBI_DATA11        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_SC1_IO            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_PM_GPIO_36        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_35 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_GPIO_35           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_EBI_DATA10        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_SC1_RST           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_PM_GPIO_35        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_34 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_GPIO_34           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_EBI_DATA9         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_SC1_CLK           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_PM_GPIO_34        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_33 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_GPIO_33           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_EBI_DATA8         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_SC1_VCC           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_PM_GPIO_33        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_32 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_GPIO_32           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_EBI_DATA7         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_OUT_27         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_IN_27          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_OUT_21         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_PM_GPIO_32        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_31 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_GPIO_31           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_EBI_DATA6         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_OUT_26         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_IN_26          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_OUT_20         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_PM_GPIO_31        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_30 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_GPIO_30           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_EBI_DATA5         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_TP_OUT_25         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_TP_IN_25          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_PM_GPIO_30        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_29 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_GPIO_29           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_EBI_DATA4         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_TP_OUT_24         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_TP_IN_24          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_PM_GPIO_29        4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_5 - Pinmux control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_44 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_GPIO_44           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_EBI_TSB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_OUT_31         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_IN_31          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_IN_19          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_OUT_26         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_PM_GPIO_44        6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_43 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_GPIO_43           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_EBI_DSB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_OUT_30         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_IN_30          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_IN_18          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_OUT_25         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_PM_GPIO_43        6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_42 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_GPIO_42           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_EBI_WE0B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_OUT_29         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_IN_29          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_OUT_23         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_PM_GPIO_42        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_41 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_GPIO_41           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_EBI_RDB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_OUT_28         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_IN_28          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_OUT_22         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_PM_GPIO_41        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_40 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_GPIO_40           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_EBI_DATA15        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SPI_M_SCK         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_MII_COL           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SC1_AUX2          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_PM_GPIO_40        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_39 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_GPIO_39           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_EBI_DATA14        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SPI_M_MISO        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_MII_TX_ER         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SC1_AUX1          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_PM_GPIO_39        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_38 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_GPIO_38           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_EBI_DATA13        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SPI_M_MOSI        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_MII_RX_ER         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SC1_VPP           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_PM_GPIO_38        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_37 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_GPIO_37           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_EBI_DATA12        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_SC1_PRES          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_PM_GPIO_37        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_6 - Pinmux control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_52 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_GPIO_52           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_POD2CHIP_MDI5     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_PPKT_I_DATA_5     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_PM_GPIO_52        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_51 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_GPIO_51           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_POD2CHIP_MDI4     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_PPKT_I_DATA_4     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_PM_GPIO_51        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_50 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_GPIO_50           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_POD2CHIP_MDI3     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_PPKT_I_DATA_3     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_PM_GPIO_50        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_49 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_GPIO_49           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_POD2CHIP_MDI2     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_PPKT_I_DATA_2     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_PM_GPIO_49        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_48 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_GPIO_48           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_POD2CHIP_MDI1     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_PPKT_I_DATA_1     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_PM_GPIO_48        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_47 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_GPIO_47           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_POD2CHIP_MDI0     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_PPKT_I_DATA_0     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_PM_GPIO_47        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_46 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_GPIO_46           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_POD2CHIP_MCLKI    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_PPKT_I_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_EBI_ADDR14        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_PM_GPIO_46        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_45 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_GPIO_45           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_NAND_RBB          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_TP_OUT_16         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_PM_GPIO_45        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_7 - Pinmux control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_60 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_GPIO_60           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_CHIP2POD_MDO2     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_RMXP_DATA2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_EBI_ADDR20        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_SDS0_O_DATA_2     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_PM_GPIO_60        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_59 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_GPIO_59           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_CHIP2POD_MDO1     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_RMXP_DATA1        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_EBI_ADDR19        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_SDS0_O_DATA_1     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_PM_GPIO_59        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_58 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_GPIO_58           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_CHIP2POD_MDO0     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_RMXP_DATA0        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_EBI_ADDR18        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_SDS0_O_DATA_0     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_PM_GPIO_58        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_57 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_GPIO_57           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_CHIP2POD_MCLKO    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_RMXP_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_EBI_ADDR15        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_SDS0_O_CLK        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_PM_GPIO_57        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_56 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_GPIO_56           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_POD2CHIP_MIVAL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_PPKT_I_VALID      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_PM_GPIO_56        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_55 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_GPIO_55           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_POD2CHIP_MISTRT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_PPKT_I_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_PM_GPIO_55        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_54 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_GPIO_54           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_POD2CHIP_MDI7     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_PPKT_I_DATA_7     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_PM_GPIO_54        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_53 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_GPIO_53           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_POD2CHIP_MDI6     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_PPKT_I_DATA_6     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_PM_GPIO_53        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_8 - Pinmux control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_68 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_GPIO_68           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_POD2CHIP_MICLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_PPKT_I_ERROR      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_EBI_ADDR13        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_PM_GPIO_68        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_67 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_GPIO_67           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_CHIP2POD_MOVAL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_RMXP_VALID        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_EBI_ADDR16        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_SDS0_O_VALID      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_PM_GPIO_67        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_66 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_GPIO_66           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_CHIP2POD_MOSTRT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_RMXP_SYNC         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_EBI_ADDR17        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_SDS0_O_SYNC       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_PM_GPIO_66        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_65 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_GPIO_65           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_CHIP2POD_MDO7     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_RMXP_DATA7        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_EBI_ADDR25        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_SDS0_O_DATA_7     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_PM_GPIO_65        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_64 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_GPIO_64           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_CHIP2POD_MDO6     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_RMXP_DATA6        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_EBI_ADDR24        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_SDS0_O_DATA_6     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_PM_GPIO_64        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_63 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_GPIO_63           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_CHIP2POD_MDO5     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_RMXP_DATA5        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_EBI_ADDR23        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_SDS0_O_DATA_5     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_PM_GPIO_63        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_62 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_GPIO_62           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_CHIP2POD_MDO4     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_RMXP_DATA4        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_EBI_ADDR22        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_SDS0_O_DATA_4     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_PM_GPIO_62        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_61 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_GPIO_61           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_CHIP2POD_MDO3     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_RMXP_DATA3        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_EBI_ADDR21        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_SDS0_O_DATA_3     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_PM_GPIO_61        5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_9 - Pinmux control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_76 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_GPIO_76           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_RMX0_SYNC         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_PKT1_SYNC         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_SDS0_DEMOD_SYNC   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_PM_GPIO_76        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_75 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_GPIO_75           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_RMX0_DATA         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_PKT1_DATA         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_CLK_OBSRV3        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_SDS0_DEMOD_DATA   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_PM_GPIO_75        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_74 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_GPIO_74           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_RMX0_CLK          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_PKT1_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_CLK_OBSRV2        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_SDS0_DEMOD_CLK    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_PM_GPIO_74        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_73 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_GPIO_73           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_MPOD_M_SDI        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_PM_GPIO_73        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_72 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_DEFAULT           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_GPIO_72           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_MPOD_M_SDO        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_EBI_ADDR0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_PM_GPIO_72        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_71 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_DEFAULT           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_GPIO_71           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_MPOD_SCLK         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_EBI_ADDR1         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_PM_GPIO_71        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_70 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_DEFAULT           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_GPIO_70           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_MPOD_SCTL         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_EBI_ADDR2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_SDS0_O_ERROR      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_PM_GPIO_70        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_69 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_GPIO_69           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_CHIP2POD_MOCLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_RMXP_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_EBI_ADDR12        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_AUD_FS_CLK1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_PM_GPIO_69        5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_10 - Pinmux control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_84 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_GPIO_84          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_SC0_AUX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_I2S_DATA0_IN     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_TP_OUT_13        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_PM_GPIO_84       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_83 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_GPIO_83          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_SC0_PRES         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_I2S_CLK0_IN      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_TP_OUT_12        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_PM_GPIO_83       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_82 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_GPIO_82          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_SC0_IO           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_TP_OUT_11        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_PM_GPIO_82       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_81 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_GPIO_81          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_SC0_RST          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_TP_OUT_10        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_PM_GPIO_81       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_80 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_GPIO_80          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_SC0_CLK          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_TP_OUT_09        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_PM_GPIO_80       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_79 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_GPIO_79          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_SC0_VCC          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_TP_OUT_08        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_PM_GPIO_79       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_78 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_GPIO_78          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_RMX0_PAUSE       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PKT1_ERROR       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PKT3_DATA        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_I2S_LR0_IN       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SDS0_DSEC_VCTL   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SDS0_DEMOD_ERR   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PM_GPIO_78       7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_77 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_GPIO_77          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_RMX0_VALID       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PKT1_VALID       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PKT3_CLK         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SPI_M_SS1B       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SDS0_DSEC_SELVTOP 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SDS0_DEMOD_VALID 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PM_GPIO_77       7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_11 - Pinmux control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_92 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_GPIO_92          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_UART_RX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_IR_OUT           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_ALT_TP_IN_02     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_POD2CHIP_MCLKI   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_PM_GPIO_92       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_91 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_GPIO_91          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_UART_TX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_PWM0             2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_ALT_TP_OUT_02    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_POD_EBI_DSB      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_PM_GPIO_91       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_90 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_GPIO_90          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_UART_RX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_VEC_VSYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_ALT_TP_IN_01     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_POD_EBI_WE0B     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_PM_GPIO_90       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_89 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_GPIO_89          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_UART_TX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_VEC_HSYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_ALT_TP_OUT_01    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_POD_EBI_RDB      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_PM_GPIO_89       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_88 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_GPIO_88          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_SPI_S_SSB        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_UART_RX0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_ALT_TP_IN_00     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_PM_GPIO_88       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_87 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_GPIO_87          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_SPI_S_MISO       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_UART_TX0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_ALT_TP_OUT_00    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_PM_GPIO_87       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_86 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_GPIO_86          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_SC0_VPP          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_USB0_PWRFLT_1    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_TP_OUT_15        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_PM_GPIO_86       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_85 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_GPIO_85          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_SC0_AUX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_I2S_LR0_IN       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_TP_OUT_14        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_USB0_PWRFLT_2    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_PM_GPIO_85       5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_12 - Pinmux control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_101 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_GPIO_101        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_USB0_PWRON_1    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_RMX1_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SDS0_DSEC_SELVTOP 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_TP_OUT_17       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SDS0_RF_AGC     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_ENET_ACTIVITY   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_PM_GPIO_101     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_100 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_GPIO_100        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_PKT2_ERROR      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SC1_VPP         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_VEC_HSYNC       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_UART_CTS2       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_CODEC_FSYNCB    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SPI_M_SS1B      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SC1_PRES        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_PM_GPIO_100     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_99 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_GPIO_99          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PKT2_VALID       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PKT3_SYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_IR_OUT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_UART_RX2         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_CODEC_SDI        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SPI_M_MISO       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SC1_IO           7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PM_GPIO_99       8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_98 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_GPIO_98          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_PKT2_SYNC        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_CODEC_MCLK       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SPI_M_SCK        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SC1_RST          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_PM_GPIO_98       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_97 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_GPIO_97          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_PKT2_DATA        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_UART_RTS2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_CODEC_SDO        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SPI_M_SS0B       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SC1_CLK          5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_PM_GPIO_97       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_96 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_GPIO_96          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_PKT2_CLK         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_UART_TX2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_CODEC_SCLK       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SPI_M_MOSI       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SC1_VCC          5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_PM_GPIO_96       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_94 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_GPIO_94          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SF_WPB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_EXT_IRQ3         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_PWM0             3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_UART_RTS0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_I2S_DATA0_IN     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SDS0_DSEC_TXEN   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_PM_GPIO_94       7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_93 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_GPIO_93          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SF_HOLDB         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_EXT_IRQ2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_VEC_VSYNC        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_UART_CTS0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_I2S_CLK0_IN      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SDS0_DSEC_TXOUT  6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_PM_GPIO_93       7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_13 - Pinmux control register 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_110 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_GPIO_110        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_MII_CRS         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_EBI_ADDR15      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_PM_GPIO_110     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_109 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_GPIO_109        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_MII_COL         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_PKT4_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR0_IN      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR0_OUT     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR1_OUT     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_SC1_AUX2        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_PM_GPIO_109     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_108 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_GPIO_108        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_MII_TX_ER       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_PKT4_DATA       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA0_IN    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA0_OUT   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA1_OUT   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_SC1_AUX1        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_TP_IN_31        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_PM_GPIO_108     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_107 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_GPIO_107        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_MII_RX_ER       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_PKT4_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK0_IN     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK0_OUT    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK1_OUT    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_SC1_VPP         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_TP_IN_30        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_PM_GPIO_107     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_105 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_GPIO_105        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_ENET_ACTIVITY   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_PWM1            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_CLK_OBSRV0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_CLK_27          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_AUD_FS_CLK0     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_SC_CLK_OUT      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_TP_OUT_19       7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_PM_GPIO_105     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_104 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_GPIO_104        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_USB0_PWRFLT_2   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_EXT_IRQ5        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_RMX1_SYNC       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_IR_INT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_PM_GPIO_104     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_103 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_GPIO_103        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_USB0_PWRFLT_1   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_EXT_IRQ4        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_RMX1_PAUSE      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_P1_INTR_1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_PM_GPIO_103     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_102 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_GPIO_102        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_USB0_PWRON_2    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_RMX1_DATA       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SDS0_DSEC_VCTL  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_TP_OUT_18       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SDS0_IF_AGC     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_ENET_LINK       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_PM_GPIO_102     7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_14 - Pinmux control register 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_118 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_GPIO_118        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_RGMII_TXD_03    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_EBI_ADDR23      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SDIO0_DAT3      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_TP_OUT_27       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_PM_GPIO_118     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_117 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_GPIO_117        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_RGMII_RXD_00    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_EBI_ADDR22      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SDIO0_LED       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_TP_OUT_26       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_PM_GPIO_117     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_116 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_GPIO_116        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_RGMII_RXD_01    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_EBI_ADDR21      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SDIO0_CLK       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_TP_OUT_25       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_PM_GPIO_116     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_115 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_GPIO_115        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_RGMII_RXD_02    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_EBI_ADDR20      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_SDIO0_PWR0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_TP_OUT_24       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_PM_GPIO_115     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_114 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_GPIO_114        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_RGMII_RXD_03    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_EBI_ADDR19      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_SDIO0_WPROT     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_TP_OUT_23       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_PM_GPIO_114     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_113 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_GPIO_113        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_RGMII_TX_CLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_EBI_ADDR18      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_SDIO0_PRES      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_TP_OUT_22       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_PM_GPIO_113     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_112 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_GPIO_112        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_RGMII_RX_CLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_EBI_ADDR17      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_SDIO_VCTL       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_TP_OUT_21       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_PM_GPIO_112     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_111 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_GPIO_111        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_RGMII_RX_DV     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_EBI_ADDR16      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_TP_OUT_20       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_PM_GPIO_111     4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_15 - Pinmux control register 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: sgpio_01 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_01_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_01_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_01_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_01_SGPIO_01        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_01_BSC_M0_SDA      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: sgpio_00 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_00_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_00_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_00_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_00_SGPIO_00        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_00_BSC_M0_SCL      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_124 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_GPIO_124        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_RGMII_MDIO      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_PM_GPIO_124     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_123 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_GPIO_123        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_RGMII_MDC       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_PM_GPIO_123     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_122 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_GPIO_122        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_RGMII_TX_EN     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_EBI_ADDR27      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_SDIO0_CMD       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_TP_OUT_31       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_PM_GPIO_122     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_121 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_GPIO_121        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_RGMII_TXD_00    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_EBI_ADDR26      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_SDIO0_DAT0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_TP_OUT_30       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_PM_GPIO_121     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_120 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_GPIO_120        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_RGMII_TXD_01    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_EBI_ADDR25      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_SDIO0_DAT1      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_TP_OUT_29       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_PM_GPIO_120     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_119 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_GPIO_119        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_RGMII_TXD_02    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_EBI_ADDR24      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_SDIO0_DAT2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_TP_OUT_28       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_PM_GPIO_119     5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_16 - Pinmux control register 16
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_reserved0_MASK           0xffffff00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_reserved0_SHIFT          8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_03 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_SGPIO_03        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_BSC_M1_SDA      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_EXT_IRQ7        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_P1_INTR_1       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_02 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_SGPIO_02        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_BSC_M1_SCL      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_EXT_IRQ6        2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_07_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_06_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_05_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_04_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_03_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_02_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_01_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_00_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [13:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x00003c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       10
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_sck_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_MASK  0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_mosi_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_miso_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_24_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_23_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_22_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_21_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_20_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_19_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_18_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_17_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_16_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_15_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_14_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_13_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_12_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_11_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_10_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_09_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_08_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_39_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_38_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_37_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_36_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_35_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_34_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_33_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_32_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_31_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_30_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_29_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_28_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_27_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_26_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_25_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_54_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_53_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_52_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_51_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_50_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_49_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_48_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_47_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_46_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_45_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_44_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_43_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_42_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_41_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_40_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_69_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_68_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_67_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_66_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_65_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_64_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_63_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_62_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_61_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_60_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_59_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_58_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_57_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_56_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_55_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_84_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_83_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_82_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_81_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_80_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_79_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_78_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_77_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_76_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_75_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_74_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_73_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_72_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_71_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_70_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_100_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_99_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_98_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_97_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_96_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_94_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_93_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_92_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_91_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_90_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_89_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_88_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_87_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_86_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_85_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_116_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_115_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_114_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_113_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_112_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_111_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_110_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_109_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_108_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_107_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_105_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_104_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_103_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_102_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_101_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved0 [31:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_MASK        0xfc000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_SHIFT       26
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved1 [23:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_MASK        0x00ff0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_SHIFT       16
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_124_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_123_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_122_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_121_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_120_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_119_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_118_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_117_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_01 [03:03] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_00 [02:02] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_24 [01:01] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_23 [00:00] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_DEFAULT 0
+
+/***************************************************************************
+ *RESET_CTRL - Reset control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0xfffffffe
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               1
+
+/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT   0
+
+/***************************************************************************
+ *RESET_SOURCE_ENABLE - Reset source enable
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK       0xfffffc00
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT      10
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0
+
+/***************************************************************************
+ *SW_MASTER_RESET - Software master reset
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK           0xfffffffe
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT          1
+
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0
+
+/***************************************************************************
+ *HW_RESET_EXTENSION - Hardware reset extension
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0
+
+/***************************************************************************
+ *RESET_MONITOR - Reset Monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT  7
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT   6
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT   4
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset history
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:17] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xfffe0000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            17
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [16:16] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 16
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [15:15] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 15
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [14:14] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 14
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [13:13] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 13
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_reset [12:12] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_MASK    0x00001000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT   12
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_reset [11:11] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT    11
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [10:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT       10
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK       0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT      9
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_dl_sw_reset [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK  0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT 8
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 7
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 6
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK   0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT  4
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0
+
+/***************************************************************************
+ *SW_INIT_0_SET - Software init 0 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: reserved0 [31:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved0_MASK             0xf8000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved0_SHIFT            27
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK        0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT       26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_MASK   0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_SHIFT  25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK          0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK   0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT  23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_MASK   0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_SHIFT  22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK          0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT         21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_MASK   0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_SHIFT  20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK         0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT        19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK           0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT          18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK   0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT  17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_MASK         0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_SHIFT        16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK           0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT          15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK           0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT          14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_MASK          0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_SHIFT         13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_MASK   0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_SHIFT  12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_MASK   0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_SHIFT  11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT       10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK           0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT          9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK           0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK           0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT          6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_SHIFT   4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT   0
+
+/***************************************************************************
+ *SW_INIT_0_CLEAR - Software init 0 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: reserved0 [31:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved0_MASK           0xf8000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved0_SHIFT          27
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK      0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT     26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK        0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT       24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK        0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT       21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK       0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT      19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK         0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT        18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_MASK       0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK         0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT        15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK         0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT        14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_MASK        0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_SHIFT       13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK      0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT     10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK         0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT        9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK         0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK         0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT        6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT  0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *SW_INIT_0_STATUS - Software init 0 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: reserved0 [31:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved0_MASK          0xf8000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved0_SHIFT         27
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK       0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK       0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT      21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK      0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT     19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK        0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT       18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_MASK      0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_DEFAULT   1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK        0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT       15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK        0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT       14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_MASK       0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_SHIFT      13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_DEFAULT    1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK        0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT   2
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT       1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: reserved0 [31:27] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved0_MASK     0xf8000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved0_SHIFT    27
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK  0x01000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK  0x00200000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK   0x00040000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT  18
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK   0x00008000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT  15
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK   0x00004000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT  14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_avd0_sw_init_MASK  0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK   0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT  9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK   0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT  8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT  6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: reserved0 [31:27] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved0_MASK 0xf8000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved0_SHIFT 27
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: reserved0 [31:27] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved0_MASK   0xf8000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved0_SHIFT  27
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_1_SET - Software init 1 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK             0xfffffc00
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT            10
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK        0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_7_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_7_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_6_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_6_SHIFT   6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_6_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_5_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_5_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_MASK        0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_SHIFT       4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_r_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_r_sw_init_MASK        0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_r_sw_init_SHIFT       3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_r_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_SHIFT   2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_0_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_0_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_0_DEFAULT 0
+
+/***************************************************************************
+ *SW_INIT_1_CLEAR - Software init 1 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK           0xfffffc00
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT          10
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_6_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_6_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_6_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_r_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_r_sw_init_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_r_sw_init_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_r_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_0_DEFAULT 0
+
+/***************************************************************************
+ *SW_INIT_1_STATUS - Software init 1 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK          0xfffffc00
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT         10
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK     0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT    9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK     0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT    8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT  0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_7_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_6_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_6_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_6_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_5_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_r_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_r_sw_init_MASK     0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_r_sw_init_SHIFT    3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_r_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_SHIFT       1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_0_DEFAULT 1
+
+/***************************************************************************
+ *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK     0xfffffc00
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT    10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_6_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_r_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_r_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_r_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_0_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xfffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_6_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_r_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_r_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_r_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_0_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK   0xfffffc00
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT  10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_6_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_r_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_r_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_r_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_0_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK  0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: reserved0 [31:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved0_MASK 0xf8000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved0_SHIFT 27
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 1
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xfffffc00
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 10
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_6_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_6_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_6_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_r_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_r_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_r_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_r_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_0_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: reserved0 [31:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved0_MASK 0xf8000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved0_SHIFT 27
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 1
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xfffffc00
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 10
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_6_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_6_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_6_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_r_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_r_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_r_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_r_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_0_DEFAULT 0
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0
+
+/***************************************************************************
+ *SPARE_CTRL - Spare control bits reserved for future use
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT         0
+
+/***************************************************************************
+ *TEST_PORT_CTRL - Test port control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SOFT_MODEM_TP 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT         0
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 127
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0  0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU     1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R  2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_A  3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T  4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS     16
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK     17
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON     18
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     20
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     21
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE    22
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM    23
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC     25
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DVP_HT  26
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVD0    27
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO     30
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA   31
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     33
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0   35
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0    45
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_FTM     51
+
+/***************************************************************************
+ *TEST_PORT_OUT_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_OUT_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0
+
+/***************************************************************************
+ *EJTAG_INPUT_EN - EJTAG input bus enables
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           3
+
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 4
+
+/***************************************************************************
+ *EJTAG_OUTPUT_SEL - EJTAG output select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         3
+
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 2
+
+/***************************************************************************
+ *UART_ROUTER_SEL - UART Router select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK      0xf0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT     28
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_DEFAULT   0
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK      0x0f000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT     24
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_DEFAULT   0
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK      0x00f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_DEFAULT   0
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK      0x000f0000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_DEFAULT   0
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK      0x0000f000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_DEFAULT   0
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK      0x00000f00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_04 4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_05 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_04 4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_05 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK      0x0000000f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_04 4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_05 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15
+
+/***************************************************************************
+ *VTRAP_CTRL - VTRAP Control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK                0xfffff000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT               12
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_threshold [11:11] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_threshold [10:10] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_threshold [09:09] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_DEFAULT 1
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [08:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x000001f8
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 24
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_status_clear [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_status_clear [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_status_clear [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_DEFAULT 0
+
+/***************************************************************************
+ *VTRAP_STATUS - VTRAP Status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK              0xfffffff8
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT             3
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_status [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_status [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_status [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_DEFAULT 0
+
+/***************************************************************************
+ *SSP_CONFIG - Serial Slave Port configuration register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT        4
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT           0
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT     1
+
+/***************************************************************************
+ *SERS_REV - SERS Revision Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16
+
+/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT     0
+
+/***************************************************************************
+ *SERS_CFG - SERS Configuration Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT                1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT           0
+
+/* union - case mapped_buffer_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0
+
+/* union - case cmd_fifo_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 31
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 16
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT  0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT                 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT            0
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x00404428
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0
+
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x00404448
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0
+
+
+/***************************************************************************
+ *RO_TEST_BLOCK_SEL - Block select for RO testmode
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xffffffe0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        5
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_pwenb [04:04] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DEFAULT  1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_ENABLED  0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DISABLED 1
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [03:02] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MIN_LOAD 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MED_LOAD 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MAX_LOAD 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SVT_MIN_LOAD 3
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
+
+/***************************************************************************
+ *TEST_CONFIGURATION - Test configuration
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0
+
+#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_timer.h b/include/linux/brcmstb/7358a0/bchp_timer.h
new file mode 100644
index 0000000..51d25e2
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_timer.h
@@ -0,0 +1,340 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:36:57 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_timer.h $
+ * 
+ * Hydra_Software_Devel/3   9/20/11 12:22p pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_TIMER_H__
+#define BCHP_TIMER_H__
+
+/***************************************************************************
+ *TIMER - Watchdog & Programmable Timers
+ ***************************************************************************/
+#define BCHP_TIMER_TIMER_IS                      0x00406680 /* TIMER INTERRUPT STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE0                     0x00406684 /* TIMER CPU INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_TIMER0_CTRL                   0x00406688 /* TIMER0 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER1_CTRL                   0x0040668c /* TIMER1 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER2_CTRL                   0x00406690 /* TIMER2 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER3_CTRL                   0x00406694 /* TIMER3 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER0_STAT                   0x00406698 /* TIMER0 STATUS REGISTER */
+#define BCHP_TIMER_TIMER1_STAT                   0x0040669c /* TIMER1 STATUS REGISTER */
+#define BCHP_TIMER_TIMER2_STAT                   0x004066a0 /* TIMER2 STATUS REGISTER */
+#define BCHP_TIMER_TIMER3_STAT                   0x004066a4 /* TIMER3 STATUS REGISTER */
+#define BCHP_TIMER_WDTIMEOUT                     0x004066a8 /* WATCHDOG TIMEOUT REGISTER */
+#define BCHP_TIMER_WDCMD                         0x004066ac /* WATCHDOG COMMAND REGISTER */
+#define BCHP_TIMER_WDCHIPRST_CNT                 0x004066b0 /* WATCHDOG CHIP RESET COUNT REGISTER */
+#define BCHP_TIMER_WDCRS                         0x004066b4 /* WATCHDOG CHIP RESET STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE1                     0x004066b8 /* TIMER PCI INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_WDCTRL                        0x004066bc /* WATCHDOG CONTROL REGISTER */
+
+/***************************************************************************
+ *TIMER_IS - TIMER INTERRUPT STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IS :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IS_reserved0_MASK                         0xffffffe0
+#define BCHP_TIMER_TIMER_IS_reserved0_SHIFT                        5
+
+/* TIMER :: TIMER_IS :: WDINT [04:04] */
+#define BCHP_TIMER_TIMER_IS_WDINT_MASK                             0x00000010
+#define BCHP_TIMER_TIMER_IS_WDINT_SHIFT                            4
+#define BCHP_TIMER_TIMER_IS_WDINT_DEFAULT                          0
+
+/* TIMER :: TIMER_IS :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IS_TMR3TO_MASK                            0x00000008
+#define BCHP_TIMER_TIMER_IS_TMR3TO_SHIFT                           3
+#define BCHP_TIMER_TIMER_IS_TMR3TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IS_TMR2TO_MASK                            0x00000004
+#define BCHP_TIMER_TIMER_IS_TMR2TO_SHIFT                           2
+#define BCHP_TIMER_TIMER_IS_TMR2TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IS_TMR1TO_MASK                            0x00000002
+#define BCHP_TIMER_TIMER_IS_TMR1TO_SHIFT                           1
+#define BCHP_TIMER_TIMER_IS_TMR1TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IS_TMR0TO_MASK                            0x00000001
+#define BCHP_TIMER_TIMER_IS_TMR0TO_SHIFT                           0
+#define BCHP_TIMER_TIMER_IS_TMR0TO_DEFAULT                         0
+
+/***************************************************************************
+ *TIMER_IE0 - TIMER CPU INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE0 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE0_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE0_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE0 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_DEFAULT                     0
+
+/* TIMER :: TIMER_IE0 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_DEFAULT                        0
+
+/***************************************************************************
+ *TIMER0_CTRL - TIMER0 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER0_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER0_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER0_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER0_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER0_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER0_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER0_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER0_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER1_CTRL - TIMER1 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER1_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER1_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER1_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER1_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER1_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER1_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER1_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER1_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER2_CTRL - TIMER2 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER2_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER2_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER2_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER2_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER2_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER2_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER2_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER2_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER3_CTRL - TIMER3 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER3_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER3_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER3_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER3_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER3_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER3_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER3_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER3_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER0_STAT - TIMER0 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER0_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER0_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER0_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER1_STAT - TIMER1 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER1_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER1_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER1_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER2_STAT - TIMER2 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER2_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER2_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER2_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER3_STAT - TIMER3 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER3_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER3_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER3_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *WDTIMEOUT - WATCHDOG TIMEOUT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDTIMEOUT :: WDTIMEOUT_VAL [31:00] */
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_MASK                    0xffffffff
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *WDCMD - WATCHDOG COMMAND REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCMD :: WDCMD [31:00] */
+#define BCHP_TIMER_WDCMD_WDCMD_MASK                                0xffffffff
+#define BCHP_TIMER_WDCMD_WDCMD_SHIFT                               0
+#define BCHP_TIMER_WDCMD_WDCMD_DEFAULT                             0
+
+/***************************************************************************
+ *WDCHIPRST_CNT - WATCHDOG CHIP RESET COUNT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCHIPRST_CNT :: reserved0 [31:26] */
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_MASK                    0xfc000000
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_SHIFT                   26
+
+/* TIMER :: WDCHIPRST_CNT :: WDCHIPRST_CNT [25:00] */
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_MASK                0x03ffffff
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_SHIFT               0
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_DEFAULT             50331647
+
+/***************************************************************************
+ *WDCRS - WATCHDOG CHIP RESET STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCRS :: reserved0 [31:01] */
+#define BCHP_TIMER_WDCRS_reserved0_MASK                            0xfffffffe
+#define BCHP_TIMER_WDCRS_reserved0_SHIFT                           1
+
+/* TIMER :: WDCRS :: WDCR [00:00] */
+#define BCHP_TIMER_WDCRS_WDCR_MASK                                 0x00000001
+#define BCHP_TIMER_WDCRS_WDCR_SHIFT                                0
+#define BCHP_TIMER_WDCRS_WDCR_DEFAULT                              0
+
+/***************************************************************************
+ *TIMER_IE1 - TIMER PCI INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE1 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE1_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE1_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE1 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_DEFAULT                     0
+
+/* TIMER :: TIMER_IE1 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_DEFAULT                        0
+
+/***************************************************************************
+ *WDCTRL - WATCHDOG CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCTRL :: reserved0 [31:03] */
+#define BCHP_TIMER_WDCTRL_reserved0_MASK                           0xfffffff8
+#define BCHP_TIMER_WDCTRL_reserved0_SHIFT                          3
+
+/* TIMER :: WDCTRL :: WD_COUNT_MODE [02:02] */
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_MASK                       0x00000004
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_SHIFT                      2
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_DEFAULT                    0
+
+/* TIMER :: WDCTRL :: WD_EVENT_MODE [01:00] */
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_MASK                       0x00000003
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_SHIFT                      0
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_DEFAULT                    0
+
+#endif /* #ifndef BCHP_TIMER_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_uarta.h b/include/linux/brcmstb/7358a0/bchp_uarta.h
new file mode 100644
index 0000000..cfc3fcf
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_uarta.h
@@ -0,0 +1,394 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:44:58 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_uarta.h $
+ * 
+ * Hydra_Software_Devel/3   9/20/11 12:23p pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTA_H__
+#define BCHP_UARTA_H__
+
+/***************************************************************************
+ *UARTA - UART A
+ ***************************************************************************/
+#define BCHP_UARTA_RBR                           0x00406800 /* Receive Buffer Register */
+#define BCHP_UARTA_THR                           0x00406800 /* Transmit Holding Register */
+#define BCHP_UARTA_DLH                           0x00406804 /* Divisor Latch High */
+#define BCHP_UARTA_DLL                           0x00406800 /* Divisor Latch Low */
+#define BCHP_UARTA_IER                           0x00406804 /* Interrupt Enable Register */
+#define BCHP_UARTA_IIR                           0x00406808 /* Interrupt Identity Register */
+#define BCHP_UARTA_FCR                           0x00406808 /* FIFO Control Register */
+#define BCHP_UARTA_LCR                           0x0040680c /* Line Control Register */
+#define BCHP_UARTA_MCR                           0x00406810 /* Modem Control Register */
+#define BCHP_UARTA_LSR                           0x00406814 /* Line Status Register */
+#define BCHP_UARTA_MSR                           0x00406818 /* Modem Status Register */
+#define BCHP_UARTA_SCR                           0x0040681c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTA :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTA_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_RBR_reserved0_SHIFT                             8
+
+/* UARTA :: RBR :: RBR [07:00] */
+#define BCHP_UARTA_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTA_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTA_RBR_RBR_DEFAULT                                 0
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTA :: THR :: reserved0 [31:08] */
+#define BCHP_UARTA_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_THR_reserved0_SHIFT                             8
+
+/* UARTA :: THR :: THR [07:00] */
+#define BCHP_UARTA_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTA_THR_THR_SHIFT                                   0
+#define BCHP_UARTA_THR_THR_DEFAULT                                 0
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTA :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTA_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLH_reserved0_SHIFT                             8
+
+/* UARTA :: DLH :: DLH [07:00] */
+#define BCHP_UARTA_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTA_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTA_DLH_DLH_DEFAULT                                 0
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTA :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTA_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLL_reserved0_SHIFT                             8
+
+/* UARTA :: DLL :: DLL [07:00] */
+#define BCHP_UARTA_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTA_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTA_DLL_DLL_DEFAULT                                 0
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTA :: IER :: reserved0 [31:08] */
+#define BCHP_UARTA_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IER_reserved0_SHIFT                             8
+
+/* UARTA :: IER :: PTIME [07:07] */
+#define BCHP_UARTA_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTA_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTA_IER_PTIME_DEFAULT                               0
+
+/* UARTA :: IER :: reserved1 [06:04] */
+#define BCHP_UARTA_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTA_IER_reserved1_SHIFT                             4
+
+/* UARTA :: IER :: EDSSI [03:03] */
+#define BCHP_UARTA_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTA_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTA_IER_EDSSI_DEFAULT                               0
+
+/* UARTA :: IER :: ELSI [02:02] */
+#define BCHP_UARTA_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTA_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTA_IER_ELSI_DEFAULT                                0
+
+/* UARTA :: IER :: ETBEI [01:01] */
+#define BCHP_UARTA_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTA_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTA_IER_ETBEI_DEFAULT                               0
+
+/* UARTA :: IER :: ERBFI [00:00] */
+#define BCHP_UARTA_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTA_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTA_IER_ERBFI_DEFAULT                               0
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTA :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTA_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IIR_reserved0_SHIFT                             8
+
+/* UARTA :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTA_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTA_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTA_IIR_FIFOSE_DEFAULT                              0
+
+/* UARTA :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTA_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTA_IIR_reserved1_SHIFT                             4
+
+/* UARTA :: IIR :: IID [03:00] */
+#define BCHP_UARTA_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTA_IIR_IID_SHIFT                                   0
+#define BCHP_UARTA_IIR_IID_DEFAULT                                 1
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTA :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTA_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_FCR_reserved0_SHIFT                             8
+
+/* UARTA :: FCR :: RT [07:06] */
+#define BCHP_UARTA_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTA_FCR_RT_SHIFT                                    6
+#define BCHP_UARTA_FCR_RT_DEFAULT                                  0
+
+/* UARTA :: FCR :: TET [05:04] */
+#define BCHP_UARTA_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTA_FCR_TET_SHIFT                                   4
+#define BCHP_UARTA_FCR_TET_DEFAULT                                 0
+
+/* UARTA :: FCR :: DMAM [03:03] */
+#define BCHP_UARTA_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTA_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTA_FCR_DMAM_DEFAULT                                0
+
+/* UARTA :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTA_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTA_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTA_FCR_XFIFOR_DEFAULT                              0
+
+/* UARTA :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTA_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTA_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTA_FCR_RFIFOR_DEFAULT                              0
+
+/* UARTA :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTA_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTA_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTA_FCR_FIFOE_DEFAULT                               0
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTA :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTA_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LCR_reserved0_SHIFT                             8
+
+/* UARTA :: LCR :: DLAB [07:07] */
+#define BCHP_UARTA_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTA_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTA_LCR_DLAB_DEFAULT                                0
+
+/* UARTA :: LCR :: BC [06:06] */
+#define BCHP_UARTA_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTA_LCR_BC_SHIFT                                    6
+#define BCHP_UARTA_LCR_BC_DEFAULT                                  0
+
+/* UARTA :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTA_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTA_LCR_reserved1_SHIFT                             5
+
+/* UARTA :: LCR :: EPS [04:04] */
+#define BCHP_UARTA_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTA_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTA_LCR_EPS_DEFAULT                                 0
+
+/* UARTA :: LCR :: PEN [03:03] */
+#define BCHP_UARTA_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTA_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTA_LCR_PEN_DEFAULT                                 0
+
+/* UARTA :: LCR :: STOP [02:02] */
+#define BCHP_UARTA_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTA_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTA_LCR_STOP_DEFAULT                                0
+
+/* UARTA :: LCR :: DLS [01:00] */
+#define BCHP_UARTA_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTA_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTA_LCR_DLS_DEFAULT                                 0
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTA :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTA_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTA_MCR_reserved0_SHIFT                             7
+
+/* UARTA :: MCR :: SIRE [06:06] */
+#define BCHP_UARTA_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTA_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTA_MCR_SIRE_DEFAULT                                0
+
+/* UARTA :: MCR :: AFCE [05:05] */
+#define BCHP_UARTA_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTA_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTA_MCR_AFCE_DEFAULT                                0
+
+/* UARTA :: MCR :: LB [04:04] */
+#define BCHP_UARTA_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTA_MCR_LB_SHIFT                                    4
+#define BCHP_UARTA_MCR_LB_DEFAULT                                  0
+
+/* UARTA :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTA_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTA_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTA_MCR_OUT2_DEFAULT                                0
+
+/* UARTA :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTA_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTA_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTA_MCR_OUT1_DEFAULT                                0
+
+/* UARTA :: MCR :: RTS [01:01] */
+#define BCHP_UARTA_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTA_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTA_MCR_RTS_DEFAULT                                 0
+
+/* UARTA :: MCR :: DTR [00:00] */
+#define BCHP_UARTA_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTA_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTA_MCR_DTR_DEFAULT                                 0
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTA :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTA_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LSR_reserved0_SHIFT                             8
+
+/* UARTA :: LSR :: RFE [07:07] */
+#define BCHP_UARTA_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTA_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTA_LSR_RFE_DEFAULT                                 0
+
+/* UARTA :: LSR :: TEMT [06:06] */
+#define BCHP_UARTA_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTA_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTA_LSR_TEMT_DEFAULT                                1
+
+/* UARTA :: LSR :: THRE [05:05] */
+#define BCHP_UARTA_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTA_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTA_LSR_THRE_DEFAULT                                1
+
+/* UARTA :: LSR :: BI [04:04] */
+#define BCHP_UARTA_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTA_LSR_BI_SHIFT                                    4
+#define BCHP_UARTA_LSR_BI_DEFAULT                                  0
+
+/* UARTA :: LSR :: FE [03:03] */
+#define BCHP_UARTA_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTA_LSR_FE_SHIFT                                    3
+#define BCHP_UARTA_LSR_FE_DEFAULT                                  0
+
+/* UARTA :: LSR :: PE [02:02] */
+#define BCHP_UARTA_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTA_LSR_PE_SHIFT                                    2
+#define BCHP_UARTA_LSR_PE_DEFAULT                                  0
+
+/* UARTA :: LSR :: OE [01:01] */
+#define BCHP_UARTA_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTA_LSR_OE_SHIFT                                    1
+#define BCHP_UARTA_LSR_OE_DEFAULT                                  0
+
+/* UARTA :: LSR :: DR [00:00] */
+#define BCHP_UARTA_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTA_LSR_DR_SHIFT                                    0
+#define BCHP_UARTA_LSR_DR_DEFAULT                                  0
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTA :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTA_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_MSR_reserved0_SHIFT                             8
+
+/* UARTA :: MSR :: DCD [07:07] */
+#define BCHP_UARTA_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTA_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTA_MSR_DCD_DEFAULT                                 0
+
+/* UARTA :: MSR :: RI [06:06] */
+#define BCHP_UARTA_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTA_MSR_RI_SHIFT                                    6
+#define BCHP_UARTA_MSR_RI_DEFAULT                                  0
+
+/* UARTA :: MSR :: DSR [05:05] */
+#define BCHP_UARTA_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTA_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTA_MSR_DSR_DEFAULT                                 0
+
+/* UARTA :: MSR :: CTS [04:04] */
+#define BCHP_UARTA_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTA_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTA_MSR_CTS_DEFAULT                                 0
+
+/* UARTA :: MSR :: DDCD [03:03] */
+#define BCHP_UARTA_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTA_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTA_MSR_DDCD_DEFAULT                                0
+
+/* UARTA :: MSR :: TERI [02:02] */
+#define BCHP_UARTA_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTA_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTA_MSR_TERI_DEFAULT                                0
+
+/* UARTA :: MSR :: DDSR [01:01] */
+#define BCHP_UARTA_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTA_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTA_MSR_DDSR_DEFAULT                                0
+
+/* UARTA :: MSR :: DCTS [00:00] */
+#define BCHP_UARTA_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTA_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTA_MSR_DCTS_DEFAULT                                0
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTA :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTA_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_SCR_reserved0_SHIFT                             8
+
+/* UARTA :: SCR :: SCR [07:00] */
+#define BCHP_UARTA_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTA_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTA_SCR_SCR_DEFAULT                                 0
+
+#endif /* #ifndef BCHP_UARTA_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_uartb.h b/include/linux/brcmstb/7358a0/bchp_uartb.h
new file mode 100644
index 0000000..bfaf8d6
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_uartb.h
@@ -0,0 +1,63 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug 16 11:03:36 2010
+ *                 MD5 Checksum         442d8de773a92e76786307c9f37b5c82
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_uartb.h $
+ * 
+ * Hydra_Software_Devel/2   8/16/10 12:22p pntruong
+ * SW7358-2: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTB_H__
+#define BCHP_UARTB_H__
+
+/***************************************************************************
+ *UARTB - UART B
+ ***************************************************************************/
+#define BCHP_UARTB_RBR                           0x00406840 /* Receive Buffer Register */
+#define BCHP_UARTB_THR                           0x00406840 /* Transmit Holding Register */
+#define BCHP_UARTB_DLH                           0x00406844 /* Divisor Latch High */
+#define BCHP_UARTB_DLL                           0x00406840 /* Divisor Latch Low */
+#define BCHP_UARTB_IER                           0x00406844 /* Interrupt Enable Register */
+#define BCHP_UARTB_IIR                           0x00406848 /* Interrupt Identity Register */
+#define BCHP_UARTB_FCR                           0x00406848 /* FIFO Control Register */
+#define BCHP_UARTB_LCR                           0x0040684c /* Line Control Register */
+#define BCHP_UARTB_MCR                           0x00406850 /* Modem Control Register */
+#define BCHP_UARTB_LSR                           0x00406854 /* Line Status Register */
+#define BCHP_UARTB_MSR                           0x00406858 /* Modem Status Register */
+#define BCHP_UARTB_SCR                           0x0040685c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTB_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_uartc.h b/include/linux/brcmstb/7358a0/bchp_uartc.h
new file mode 100644
index 0000000..ea77c9f
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_uartc.h
@@ -0,0 +1,63 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug 16 10:54:53 2010
+ *                 MD5 Checksum         442d8de773a92e76786307c9f37b5c82
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_uartc.h $
+ * 
+ * Hydra_Software_Devel/2   8/16/10 12:22p pntruong
+ * SW7358-2: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTC_H__
+#define BCHP_UARTC_H__
+
+/***************************************************************************
+ *UARTC - UART C
+ ***************************************************************************/
+#define BCHP_UARTC_RBR                           0x00406880 /* Receive Buffer Register */
+#define BCHP_UARTC_THR                           0x00406880 /* Transmit Holding Register */
+#define BCHP_UARTC_DLH                           0x00406884 /* Divisor Latch High */
+#define BCHP_UARTC_DLL                           0x00406880 /* Divisor Latch Low */
+#define BCHP_UARTC_IER                           0x00406884 /* Interrupt Enable Register */
+#define BCHP_UARTC_IIR                           0x00406888 /* Interrupt Identity Register */
+#define BCHP_UARTC_FCR                           0x00406888 /* FIFO Control Register */
+#define BCHP_UARTC_LCR                           0x0040688c /* Line Control Register */
+#define BCHP_UARTC_MCR                           0x00406890 /* Modem Control Register */
+#define BCHP_UARTC_LSR                           0x00406894 /* Line Status Register */
+#define BCHP_UARTC_MSR                           0x00406898 /* Modem Status Register */
+#define BCHP_UARTC_SCR                           0x0040689c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_usb_ctrl.h b/include/linux/brcmstb/7358a0/bchp_usb_ctrl.h
new file mode 100644
index 0000000..eba3dd8
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_usb_ctrl.h
@@ -0,0 +1,655 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:40:10 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_usb_ctrl.h $
+ * 
+ * Hydra_Software_Devel/3   9/20/11 12:23p pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB_CTRL_H__
+#define BCHP_USB_CTRL_H__
+
+/***************************************************************************
+ *USB_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB_CTRL_SETUP                      0x00480200 /* Setup Register */
+#define BCHP_USB_CTRL_PLL_CTL                    0x00480204 /* PLL Control Register */
+#define BCHP_USB_CTRL_FLADJ_VALUE                0x00480208 /* Frame Adjust Value */
+#define BCHP_USB_CTRL_EBRIDGE                    0x0048020c /* Control Register for EHCI Bridge */
+#define BCHP_USB_CTRL_OBRIDGE                    0x00480210 /* Control Register for OHCI Bridge */
+#define BCHP_USB_CTRL_MDIO                       0x00480214 /* MDIO Interface Programming Register */
+#define BCHP_USB_CTRL_MDIO2                      0x00480218 /* MDIO Interface Read Register */
+#define BCHP_USB_CTRL_TEST_PORT_CTL              0x0048021c /* Test Port Control Register */
+#define BCHP_USB_CTRL_USB_SIMCTL                 0x00480220 /* Simulation Register */
+#define BCHP_USB_CTRL_USB_TESTCTL                0x00480224 /* Throutput Test Control */
+#define BCHP_USB_CTRL_USB_TESTMON                0x00480228 /* Throughput Test Monitor */
+#define BCHP_USB_CTRL_UTMI_CTL_1                 0x0048022c /* UTMI Control Register */
+#define BCHP_USB_CTRL_UTMI_CTL_2                 0x00480230 /* UTMI Control 2 Register */
+#define BCHP_USB_CTRL_SPARE1                     0x00480234 /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE2                     0x00480238 /* Spare2 Register for future use */
+
+/***************************************************************************
+ *SETUP - Setup Register
+ ***************************************************************************/
+/* USB_CTRL :: SETUP :: OC_DISABLE [31:28] */
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK                        0xf0000000
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT                       28
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT                     0
+
+/* USB_CTRL :: SETUP :: SRAM_CS_DIS [27:26] */
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_MASK                       0x0c000000
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_SHIFT                      26
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: SETUP_SPARE [25:13] */
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK                       0x03ffe000
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT                      13
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: async_expire_dis [12:12] */
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK                  0x00001000
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT                 12
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT               0
+
+/* USB_CTRL :: SETUP :: discon_intr_en [11:11] */
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_MASK                    0x00000800
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_SHIFT                   11
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_DEFAULT                 0
+
+/* USB_CTRL :: SETUP :: con_intr_en [10:10] */
+#define BCHP_USB_CTRL_SETUP_con_intr_en_MASK                       0x00000400
+#define BCHP_USB_CTRL_SETUP_con_intr_en_SHIFT                      10
+#define BCHP_USB_CTRL_SETUP_con_intr_en_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: SOFT_SHUTDOWN [09:09] */
+#define BCHP_USB_CTRL_SETUP_SOFT_SHUTDOWN_MASK                     0x00000200
+#define BCHP_USB_CTRL_SETUP_SOFT_SHUTDOWN_SHIFT                    9
+#define BCHP_USB_CTRL_SETUP_SOFT_SHUTDOWN_DEFAULT                  0
+
+/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK                    0x00000100
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT                   8
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT                 0
+
+/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK                       0x00000080
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT                      7
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: soft_reset [06:06] */
+#define BCHP_USB_CTRL_SETUP_soft_reset_MASK                        0x00000040
+#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT                       6
+#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT                     0
+
+/* USB_CTRL :: SETUP :: IPP [05:05] */
+#define BCHP_USB_CTRL_SETUP_IPP_MASK                               0x00000020
+#define BCHP_USB_CTRL_SETUP_IPP_SHIFT                              5
+#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT                            0
+
+/* USB_CTRL :: SETUP :: IOC [04:04] */
+#define BCHP_USB_CTRL_SETUP_IOC_MASK                               0x00000010
+#define BCHP_USB_CTRL_SETUP_IOC_SHIFT                              4
+#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT                            0
+
+/* USB_CTRL :: SETUP :: WABO [03:03] */
+#define BCHP_USB_CTRL_SETUP_WABO_MASK                              0x00000008
+#define BCHP_USB_CTRL_SETUP_WABO_SHIFT                             3
+#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: FNBO [02:02] */
+#define BCHP_USB_CTRL_SETUP_FNBO_MASK                              0x00000004
+#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT                             2
+#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: FNHW [01:01] */
+#define BCHP_USB_CTRL_SETUP_FNHW_MASK                              0x00000002
+#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT                             1
+#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: BABO [00:00] */
+#define BCHP_USB_CTRL_SETUP_BABO_MASK                              0x00000001
+#define BCHP_USB_CTRL_SETUP_BABO_SHIFT                             0
+#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT                           0
+
+/***************************************************************************
+ *PLL_CTL - PLL Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK                  0x80000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT                 31
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT               0
+
+/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK                      0x40000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT                     30
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                   1
+
+/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK                      0x20000000
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                     29
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                   0
+
+/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                     0x10000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                    28
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                  1
+
+/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                  0x08000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                 27
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT               0
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK                          0x07000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT                         24
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT                       3
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                   0x00800000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                  23
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK                          0x00700000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT                         20
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT                       3
+
+/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK                          0x000f0000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT                         16
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT                       10
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE2 [15:15] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_MASK                   0x00008000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_SHIFT                  15
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_pdiv [14:12] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK                        0x00007000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT                       12
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                     1
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                   0x00000c00
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                  10
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK                        0x000003ff
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT                       0
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                     40
+
+/***************************************************************************
+ *FLADJ_VALUE - Frame Adjust Value
+ ***************************************************************************/
+/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                   0xffffffff
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                  0
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT                786464
+
+/***************************************************************************
+ *EBRIDGE - Control Register for EHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT               0
+
+/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT                  0
+
+/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT           0
+
+/* USB_CTRL :: EBRIDGE :: ebr_rdgwordcnt_sel [28:28] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_rdgwordcnt_sel_MASK              0x10000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_rdgwordcnt_sel_SHIFT             28
+#define BCHP_USB_CTRL_EBRIDGE_ebr_rdgwordcnt_sel_DEFAULT           0
+
+/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT                2
+
+/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                 4
+
+/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT                     0
+
+/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                   0
+
+/***************************************************************************
+ *OBRIDGE - Control Register for OHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT               0
+
+/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT                  0
+
+/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT           0
+
+/* USB_CTRL :: OBRIDGE :: obr_rdgwordcnt_sel [28:28] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_rdgwordcnt_sel_MASK              0x10000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_rdgwordcnt_sel_SHIFT             28
+#define BCHP_USB_CTRL_OBRIDGE_obr_rdgwordcnt_sel_DEFAULT           0
+
+/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT                2
+
+/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                 4
+
+/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT                     0
+
+/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                   0
+
+/***************************************************************************
+ *MDIO - MDIO Interface Programming Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO :: MDIO_SPARE [31:26] */
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_MASK                         0xfc000000
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_SHIFT                        26
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_DEFAULT                      0
+
+/* USB_CTRL :: MDIO :: WR_START [25:25] */
+#define BCHP_USB_CTRL_MDIO_WR_START_MASK                           0x02000000
+#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT                          25
+#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT                        0
+
+/* USB_CTRL :: MDIO :: RD_START [24:24] */
+#define BCHP_USB_CTRL_MDIO_RD_START_MASK                           0x01000000
+#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT                          24
+#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT                        0
+
+/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK                          0x00ff0000
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT                         16
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT                       0
+
+/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK                          0x0000ffff
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT                         0
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT                       0
+
+/***************************************************************************
+ *MDIO2 - MDIO Interface Read Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO2 :: SYNOPSIS_CORE_ID [31:16] */
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_MASK                  0xffff0000
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_SHIFT                 16
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_DEFAULT               9994
+
+/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK                      0x0000ffff
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                     0
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                   0
+
+/***************************************************************************
+ *TEST_PORT_CTL - Test Port Control Register
+ ***************************************************************************/
+/* USB_CTRL :: TEST_PORT_CTL :: TP_EN [31:31] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_MASK                     0x80000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_SHIFT                    31
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_DEFAULT                  0
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [30:24] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK               0x7f000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT              24
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT            0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [23:23] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK                0x00800000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT               23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT             0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt2_oe [22:22] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_MASK                0x00400000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_SHIFT               22
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_DEFAULT             0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron1_tstsel [21:21] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_MASK             0x00200000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_SHIFT            21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron2_tstsel [20:20] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_MASK             0x00100000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_SHIFT            20
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: test_clksel [19:18] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_MASK               0x000c0000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_SHIFT              18
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_DEFAULT            0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_tstsel [17:16] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_MASK             0x00030000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_SHIFT            16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: UTMI_TEST_SEL [15:08] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_MASK             0x0000ff00
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_SHIFT            8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                 0x000000ff
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT                0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT              0
+
+/***************************************************************************
+ *USB_SIMCTL - Simulation Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK                  0x80000000
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                 31
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT               0
+
+/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK                0x40000000
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT               30
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT             0
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE1 [29:28] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_MASK                0x30000000
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_SHIFT               28
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_DEFAULT             0
+
+/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK                    0x08000000
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT                   27
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT                 0
+
+/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK        0x04000000
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT       26
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT     0
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:01] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                 0x03fffffe
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT                1
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT              0
+
+/* USB_CTRL :: USB_SIMCTL :: FS_DLY_EN [00:00] */
+#define BCHP_USB_CTRL_USB_SIMCTL_FS_DLY_EN_MASK                    0x00000001
+#define BCHP_USB_CTRL_USB_SIMCTL_FS_DLY_EN_SHIFT                   0
+#define BCHP_USB_CTRL_USB_SIMCTL_FS_DLY_EN_DEFAULT                 0
+
+/***************************************************************************
+ *USB_TESTCTL - Throutput Test Control
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:22] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK              0xffc00000
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT             22
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT           0
+
+/* USB_CTRL :: USB_TESTCTL :: CTRLLER_SEL [21:21] */
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_MASK                 0x00200000
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_SHIFT                21
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_DEFAULT              0
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK                     0x00100000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                    20
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                  0
+
+/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK                   0x00080000
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                  19
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT                0
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK                    0x00070000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                   16
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                 0
+
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK              0x0000fc00
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT             10
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT           0
+
+/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK              0x000003ff
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT             0
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT           0
+
+/***************************************************************************
+ *USB_TESTMON - Throughput Test Monitor
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [31:00] */
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK                0xffffffff
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT               0
+
+/***************************************************************************
+ *UTMI_CTL_1 - UTMI Control Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE3 [31:31] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_MASK              0x80000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_SHIFT             31
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK             0x70000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT            28
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT          0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK_P1 [27:27] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_MASK                0x08000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_SHIFT               27
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_LPBACK_P1 [26:26] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_P1_MASK                0x04000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_P1_SHIFT               26
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE2 [25:25] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE2_MASK              0x02000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE2_SHIFT             25
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE2_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY_P1 [24:24] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_MASK                0x01000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_SHIFT               24
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK                0x00800000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT               23
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK                0x00400000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT               22
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK                0x00200000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT               21
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK                0x00100000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT               20
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                  0x000c0000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                 18
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT               0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT       1
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK           0x00010000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT          16
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT        0
+
+/* USB_CTRL :: UTMI_CTL_1 :: PLL_SUSPEND_EN [15:15] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PLL_SUSPEND_EN_MASK               0x00008000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PLL_SUSPEND_EN_SHIFT              15
+#define BCHP_USB_CTRL_UTMI_CTL_1_PLL_SUSPEND_EN_DEFAULT            0
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK                0x00007000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT               12
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK [11:11] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_MASK                   0x00000800
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_SHIFT                  11
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_LPBACK [10:10] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_MASK                   0x00000400
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_SHIFT                  10
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE1 [09:09] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_MASK              0x00000200
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_SHIFT             9
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY [08:08] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_MASK                   0x00000100
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_SHIFT                  8
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                   0x00000080
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                  7
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                   0x00000040
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                  6
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                   0x00000020
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                  5
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                   0x00000010
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                  4
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK                     0x0000000c
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                    2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                  0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT          1
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK              0x00000001
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT             0
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT           0
+
+/***************************************************************************
+ *UTMI_CTL_2 - UTMI Control 2 Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK               0xffffffff
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT              0
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT            0
+
+/***************************************************************************
+ *SPARE1 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE1 :: SPARE1_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_DEFAULT                   0
+
+/***************************************************************************
+ *SPARE2 - Spare2 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE2 :: SPARE2_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_DEFAULT                   0
+
+#endif /* #ifndef BCHP_USB_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_wktmr.h b/include/linux/brcmstb/7358a0/bchp_wktmr.h
new file mode 100644
index 0000000..a2b07ef
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_wktmr.h
@@ -0,0 +1,108 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:36:59 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_wktmr.h $
+ * 
+ * Hydra_Software_Devel/3   9/20/11 12:26p pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_WKTMR_H__
+#define BCHP_WKTMR_H__
+
+/***************************************************************************
+ *WKTMR - Wakeup timer
+ ***************************************************************************/
+#define BCHP_WKTMR_EVENT                         0x00408e80 /* Wakeup Timer Register */
+#define BCHP_WKTMR_COUNTER                       0x00408e84 /* Wakeup Counter */
+#define BCHP_WKTMR_ALARM                         0x00408e88 /* Wakeup Timer Alarm */
+#define BCHP_WKTMR_PRESCALER                     0x00408e8c /* Wakeup Timer Prescaler */
+#define BCHP_WKTMR_PRESCALER_VAL                 0x00408e90 /* Wakeup Timer Prescaler Value */
+
+/***************************************************************************
+ *EVENT - Wakeup Timer Register
+ ***************************************************************************/
+/* WKTMR :: EVENT :: reserved0 [31:01] */
+#define BCHP_WKTMR_EVENT_reserved0_MASK                            0xfffffffe
+#define BCHP_WKTMR_EVENT_reserved0_SHIFT                           1
+
+/* WKTMR :: EVENT :: wktmr_alarm_event [00:00] */
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_MASK                    0x00000001
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_SHIFT                   0
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_DEFAULT                 0
+
+/***************************************************************************
+ *COUNTER - Wakeup Counter
+ ***************************************************************************/
+/* WKTMR :: COUNTER :: wktmr_counter [31:00] */
+#define BCHP_WKTMR_COUNTER_wktmr_counter_MASK                      0xffffffff
+#define BCHP_WKTMR_COUNTER_wktmr_counter_SHIFT                     0
+#define BCHP_WKTMR_COUNTER_wktmr_counter_DEFAULT                   0
+
+/***************************************************************************
+ *ALARM - Wakeup Timer Alarm
+ ***************************************************************************/
+/* WKTMR :: ALARM :: wktmr_alarm [31:00] */
+#define BCHP_WKTMR_ALARM_wktmr_alarm_MASK                          0xffffffff
+#define BCHP_WKTMR_ALARM_wktmr_alarm_SHIFT                         0
+#define BCHP_WKTMR_ALARM_wktmr_alarm_DEFAULT                       0
+
+/***************************************************************************
+ *PRESCALER - Wakeup Timer Prescaler
+ ***************************************************************************/
+/* WKTMR :: PRESCALER :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_reserved0_MASK                        0xfe000000
+#define BCHP_WKTMR_PRESCALER_reserved0_SHIFT                       25
+
+/* WKTMR :: PRESCALER :: wktmr_prescaler [24:00] */
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_MASK                  0x01ffffff
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_SHIFT                 0
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_DEFAULT               27000000
+
+/***************************************************************************
+ *PRESCALER_VAL - Wakeup Timer Prescaler Value
+ ***************************************************************************/
+/* WKTMR :: PRESCALER_VAL :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_MASK                    0xfe000000
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_SHIFT                   25
+
+/* WKTMR :: PRESCALER_VAL :: wktmr_prescaler_val [24:00] */
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_MASK          0x01ffffff
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_SHIFT         0
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_DEFAULT       0
+
+#endif /* #ifndef BCHP_WKTMR_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/brcmirq.h b/include/linux/brcmstb/7358a0/brcmirq.h
new file mode 100644
index 0000000..629b174
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/brcmirq.h
@@ -0,0 +1,37 @@
+/*
+ * 7358a0 IRQ header file autogenerated by update_bchp.pl
+ * DO NOT EDIT THIS FILE BY HAND.
+ *
+ * Copyright (C) 2011 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BRCMIRQ_H_
+#define _BRCMIRQ_H_
+
+#define BRCM_IRQ_EHCI0_0	66
+#define BRCM_IRQ_GENET_0_A	25
+#define BRCM_IRQ_GENET_0_B	26
+#define BRCM_IRQ_HIF		31
+#define BRCM_IRQ_HIF_SPI	32
+#define BRCM_IRQ_OHCI0_0	67
+#define BRCM_IRQ_STANDBY	51
+#define BRCM_IRQ_UARTA		62
+#define BRCM_IRQ_UARTB		63
+#define BRCM_IRQ_UARTC		64
+#define BRCM_IRQLIST_EHCI	{ 66 }
+#define BRCM_IRQLIST_OHCI	{ 67 }
+
+#endif /* _BRCMIRQ_H_ */
diff --git a/include/linux/brcmstb/7360a0/bchp_aon_ctrl.h b/include/linux/brcmstb/7360a0/bchp_aon_ctrl.h
new file mode 100644
index 0000000..9bf2b28
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_aon_ctrl.h
@@ -0,0 +1,1578 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_aon_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:24a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_CTRL_H__
+#define BCHP_AON_CTRL_H__
+
+/***************************************************************************
+ *AON_CTRL - AON Control Registers
+ ***************************************************************************/
+#define BCHP_AON_CTRL_RESET_CTRL                 0x00408000 /* Reset Control register for AON */
+#define BCHP_AON_CTRL_PM_CTRL                    0x00408004 /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_STATUS                  0x00408008 /* Status register for Power Controller */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS        0x0040800c /* Power Management IRQ input status */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT         0x00408010 /* Power Management Wait counter in place of Wait for MIPS IRQ */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER        0x00408014 /* Deep Standby Assertion Timer */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER         0x00408018 /* Deep Standby Wakeup Timer */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE    0x0040801c /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_LED_CTRL                0x00408020 /* LED set control register */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES     0x00408024 /* LED set control register */
+#define BCHP_AON_CTRL_HLCD_CTRL                  0x00408030 /* HW LED Clock Driver Control */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER    0x00408034 /* Second Fraction Counter Initial value */
+#define BCHP_AON_CTRL_TIME_COUNTER               0x00408038 /* Hour/Minute Counter Initial value */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0           0x0040803c /* Digit Code for digit 0, 1, 2, 3 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1           0x00408040 /* Digit Code for digit 4, 5, 6, 7 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2           0x00408044 /* Digit Code for digit 8, 9 */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET      0x00408048 /* Hour MSD/LSD and minute MSD/LSD address offset */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL            0x0040804c /* LED status control */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0             0x00408050 /* General control register 0 */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0           0x00408054 /* General status register 0 */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0     0x00408058 /* General control register without scan 0 */
+#define BCHP_AON_CTRL_SPARE_CTRL_0               0x00408060 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_SPARE_CTRL_1               0x00408064 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH          0x00408068 /* Scratch register */
+#define BCHP_AON_CTRL_RESET_HISTORY              0x0040806c /* Reset History Register For AON */
+#define BCHP_AON_CTRL_NMI_CTRL                   0x00408070 /* Control register for NMI */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL           0x00408074 /* Ana xtal low cur 40g m7fc gisb control */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL         0x00408078 /* Test_mode control register */
+#define BCHP_AON_CTRL_SUB_TEST_MODE              0x0040807c /* Register source for sub_test_mode */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE          0x00408080 /* Final latched testmode value */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE      0x00408084 /* Final latched sub-testmode value */
+#define BCHP_AON_CTRL_PM_INITIATE                0x00408088 /* Power down initiate */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS             0x0040808c /* Power up restore */
+
+/***************************************************************************
+ *RESET_CTRL - Reset Control register for AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_CTRL :: reserved0 [31:04] */
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_MASK                    0xfffffff0
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_SHIFT                   4
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [03:03] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000008
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 3
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable [02:02] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_MASK     0x00000004
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT    2
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_polarity [01:01] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK   0x00000002
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT  1
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_MASK          0x00000001
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_SHIFT         0
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PM_CTRL - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_CTRL :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_MASK                       0xffffff00
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_SHIFT                      8
+
+/* AON_CTRL :: PM_CTRL :: min_s3_width_timer_bypass [07:07] */
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_MASK       0x00000080
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_SHIFT      7
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_DEFAULT    0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_fast_power_down [06:06] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_MASK              0x00000040
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_SHIFT             6
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_DEFAULT           0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_warm_boot [05:05] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_MASK                    0x00000020
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_SHIFT                   5
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_DEFAULT                 0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_deep_standby [04:04] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_MASK                 0x00000010
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_SHIFT                4
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_DEFAULT              0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_clk_divider_reset_en [03:03] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK         0x00000008
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_SHIFT        3
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_DEFAULT      0x00000001
+
+/* AON_CTRL :: PM_CTRL :: pm_use_mips_ready_ctrl [02:02] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_MASK          0x00000004
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_SHIFT         2
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_DEFAULT       0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK             0x00000002
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT            1
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_DEFAULT          0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_MASK                  0x00000001
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT                 0
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PM_STATUS - Status register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_STATUS :: pm_wait_count_upper_bits [31:26] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_MASK      0xfc000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_SHIFT     26
+
+/* AON_CTRL :: PM_STATUS :: pm_wait_counter_active [25:25] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_MASK        0x02000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_SHIFT       25
+
+/* AON_CTRL :: PM_STATUS :: pm_s3_wakeup_reset_ [24:24] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__MASK           0x01000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__SHIFT          24
+
+/* AON_CTRL :: PM_STATUS :: pm_boundary_scan_request [23:23] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_MASK      0x00800000
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_SHIFT     23
+
+/* AON_CTRL :: PM_STATUS :: pm_fast_pd_precharge_valid [22:22] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_MASK    0x00400000
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_SHIFT   22
+
+/* AON_CTRL :: PM_STATUS :: pm_led_out [21:21] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_MASK                    0x00200000
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_SHIFT                   21
+
+/* AON_CTRL :: PM_STATUS :: pm_standby_b [20:20] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_MASK                  0x00100000
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_SHIFT                 20
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs_ng [19:19] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_MASK           0x00080000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_SHIFT          19
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs [18:18] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_MASK              0x00040000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_SHIFT             18
+
+/* AON_CTRL :: PM_STATUS :: pm_rst_clock_div [17:17] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_MASK              0x00020000
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_SHIFT             17
+
+/* AON_CTRL :: PM_STATUS :: pm_pwrdn_pll_req [16:16] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_MASK              0x00010000
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_SHIFT             16
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_xtal_clocks [15:15] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_MASK            0x00008000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_SHIFT           15
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_all_clocks [14:14] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_MASK             0x00004000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_SHIFT            14
+
+/* AON_CTRL :: PM_STATUS :: pm_dphy_standby [13:13] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_MASK               0x00002000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_SHIFT              13
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_cpu_clock [12:12] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_MASK              0x00001000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_SHIFT             12
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_avd_rptd_clock [11:11] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_MASK         0x00000800
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_SHIFT        11
+
+/* AON_CTRL :: PM_STATUS :: pm_power_ctrl_disable [10:10] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_MASK         0x00000400
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_SHIFT        10
+
+/* AON_CTRL :: PM_STATUS :: pm_pll_lock [09:09] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_MASK                   0x00000200
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_SHIFT                  9
+
+/* AON_CTRL :: PM_STATUS :: pm_dram_ready_for_pwrdn [08:08] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_MASK       0x00000100
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_SHIFT      8
+
+/* AON_CTRL :: PM_STATUS :: pm_bsp_ready_for_pwrdn [07:07] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK        0x00000080
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_SHIFT       7
+
+/* AON_CTRL :: PM_STATUS :: pm_mips_ready_for_pwrdn [06:06] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_MASK       0x00000040
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_SHIFT      6
+
+/* AON_CTRL :: PM_STATUS :: pm_sec_avd_rptd_clk_disable [05:05] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_MASK   0x00000020
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_SHIFT  5
+
+/* AON_CTRL :: PM_STATUS :: pm_state [04:00] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_MASK                      0x0000001f
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_SHIFT                     0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_ACTIVE                 0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_PWRDN_RDY              1
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_AVD_RPTD       2
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_CPU            3
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_STANDBY  4
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY                5
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY_WITH_PLLS_ON   6
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_RESET_216_108_CLKS     7
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_ACTIVE   8
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_FAST_PWRDN             9
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S1  10
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_COLD_ENTRY_S2 11
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_WARM_ENTRY_S2 12
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S3  13
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY           14
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S1   15
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S2   16
+
+/***************************************************************************
+ *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
+ ***************************************************************************/
+/* AON_CTRL :: PM_IRQ_INPUT_STATUS :: pm_irq_input_status [31:00] */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_MASK 0xffffffff
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_SHIFT 0
+
+/***************************************************************************
+ *PM_MIPS_WAIT_COUNT - Power Management Wait counter in place of Wait for MIPS IRQ
+ ***************************************************************************/
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_MASK            0xffff0000
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_SHIFT           16
+
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: counter_start_value [15:00] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_MASK  0x0000ffff
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_DEFAULT 0x00000010
+
+/***************************************************************************
+ *PM_S3_STANDBY_TIMER - Deep Standby Assertion Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_MASK           0xf8000000
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_SHIFT          27
+
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_MASK 0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_DEFAULT 0x00083d60
+
+/***************************************************************************
+ *PM_S3_WAKEUP_TIMER - Deep Standby Wakeup Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_MASK            0xf8000000
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_SHIFT           27
+
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_MASK  0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_DEFAULT 0x00083d60
+
+/***************************************************************************
+ *PM_FAST_PWRDN_PRECHARGE - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: reserved0 [31:24] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_MASK       0xff000000
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_SHIFT      24
+
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: pm_fast_power_down_precharge [23:00] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_MASK 0x00ffffff
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_SHIFT 0
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PM_LED_CTRL - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_CTRL :: reserved0 [31:03] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_MASK                   0xfffffff8
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_SHIFT                  3
+
+/* AON_CTRL :: PM_LED_CTRL :: led_status [02:02] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_MASK                  0x00000004
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_SHIFT                 2
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_on [01:01] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_MASK                 0x00000002
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_SHIFT                1
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_off [00:00] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_MASK                0x00000001
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_SHIFT               0
+
+/***************************************************************************
+ *PM_LED_AUTO_ON_ENABLES - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_AUTO_ON_ENABLES :: led_status [31:00] */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_MASK       0xffffffff
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_SHIFT      0
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_DEFAULT    0x00000000
+
+/***************************************************************************
+ *HLCD_CTRL - HW LED Clock Driver Control
+ ***************************************************************************/
+/* AON_CTRL :: HLCD_CTRL :: reserved0 [31:02] */
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_MASK                     0xfffffffc
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_SHIFT                    2
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable_status [01:01] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_MASK            0x00000002
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_SHIFT           1
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable [00:00] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_MASK                   0x00000001
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_SHIFT                  0
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_DEFAULT                0x00000000
+
+/***************************************************************************
+ *SECOND_FRACTION_COUNTER - Second Fraction Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: reserved0 [31:25] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_MASK       0xfe000000
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_SHIFT      25
+
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: second_fraction_counter_init [24:00] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_MASK 0x01ffffff
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_SHIFT 0
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TIME_COUNTER - Hour/Minute Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: TIME_COUNTER :: reserved0 [31:20] */
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_MASK                  0xfff00000
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_SHIFT                 20
+
+/* AON_CTRL :: TIME_COUNTER :: hour_display_mode [19:19] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_MASK          0x00080000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_SHIFT         19
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: mode_12h_24h_init [18:18] */
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_MASK          0x00040000
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_SHIFT         18
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: am_pm_counter_init [17:17] */
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_MASK         0x00020000
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_SHIFT        17
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_DEFAULT      0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: hour_counter_init [16:12] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_MASK          0x0001f000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_SHIFT         12
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: minute_counter_init [11:06] */
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_MASK        0x00000fc0
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_SHIFT       6
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_DEFAULT     0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: second_counter_init [05:00] */
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_MASK        0x0000003f
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_SHIFT       0
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_DEFAULT     0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_0 - Digit Code for digit 0, 1, 2, 3
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_3 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_2 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_1 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_0 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_1 - Digit Code for digit 4, 5, 6, 7
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_7 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_6 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_5 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_4 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_2 - Digit Code for digit 8, 9
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_MASK              0xffff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_SHIFT             16
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_9 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_8 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_ADDR_OFFSET - Hour MSD/LSD and minute MSD/LSD address offset
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_msd_addr_offset [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_MASK 0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_SHIFT 24
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_DEFAULT 0x00000020
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_lsd_addr_offset [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_MASK 0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_SHIFT 16
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_DEFAULT 0x00000024
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_msd_addr_offset [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_MASK 0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_SHIFT 8
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_DEFAULT 0x00000018
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_lsd_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_MASK 0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_SHIFT 0
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_DEFAULT 0x0000001c
+
+/***************************************************************************
+ *LED_STATUS_CTRL - LED status control
+ ***************************************************************************/
+/* AON_CTRL :: LED_STATUS_CTRL :: reserved0 [31:28] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_MASK               0xf0000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_SHIFT              28
+
+/* AON_CTRL :: LED_STATUS_CTRL :: hlcd_state [27:25] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_MASK              0x0e000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_SHIFT             25
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_IDLE         0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_COUNT        1
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_LSD 2
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_MSD 3
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_LSD 4
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_MSD 5
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_STATUS 6
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_update_enable [24:24] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_MASK    0x01000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_SHIFT   24
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_DEFAULT 0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_mask [23:12] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_MASK             0x00fff000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_SHIFT            12
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_DEFAULT          0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_bit_offset [11:08] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_MASK       0x00000f00
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_SHIFT      8
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_DEFAULT    0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_MASK      0x000000ff
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_SHIFT     0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK         0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT        31
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK         0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT        30
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK         0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT        29
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK         0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT        28
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK         0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT        27
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK         0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT        26
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK         0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT        25
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK         0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT        24
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK         0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT        23
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK         0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT        22
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK         0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT        21
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK         0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT        20
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK         0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT        19
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK         0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT        18
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK         0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT        17
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK         0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT        16
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK         0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT        15
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK         0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT        14
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK         0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT        13
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK         0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT        12
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK         0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT        11
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK         0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT        10
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK          0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT         9
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK          0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT         8
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK          0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT         7
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK          0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT         6
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK          0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT         5
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK          0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT         4
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK          0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT         3
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK          0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT         2
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK          0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT         1
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK          0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT         0
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT       0x00000000
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_MASK              0xffffff00
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_SHIFT             8
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_MASK      0x00000080
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT     7
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_MASK      0x00000040
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT     6
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_MASK      0x00000020
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT     5
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_MASK      0x00000010
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT     4
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_MASK      0x00000008
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT     3
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_MASK      0x00000004
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT     2
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_MASK      0x00000002
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT     1
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: ejtag_ce_wakeup_event [00:00] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_MASK  0x00000001
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_MASK 0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_SHIFT 31
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_MASK 0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_SHIFT 30
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_MASK 0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_SHIFT 29
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_MASK 0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_SHIFT 28
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_MASK 0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_SHIFT 27
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_MASK 0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_SHIFT 26
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_MASK 0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_SHIFT 25
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_MASK 0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_SHIFT 24
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_MASK 0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_SHIFT 23
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_MASK 0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_SHIFT 22
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_MASK 0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_SHIFT 21
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_MASK 0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_SHIFT 20
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_MASK 0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_SHIFT 19
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_MASK 0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_SHIFT 18
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_MASK 0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_SHIFT 17
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_MASK 0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_SHIFT 16
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_MASK 0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_SHIFT 15
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_MASK 0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_SHIFT 14
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_MASK 0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_SHIFT 13
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_MASK 0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_SHIFT 12
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_MASK 0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_SHIFT 11
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_MASK 0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_SHIFT 10
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_MASK 0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_SHIFT 5
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_MASK 0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_SHIFT 4
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_MASK 0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_SHIFT 3
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_MASK 0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_SHIFT 2
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_hys_en [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_hys_en_MASK     0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_hys_en_SHIFT    0
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_hys_en_DEFAULT  0x00000001
+
+/***************************************************************************
+ *SPARE_CTRL_0 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_DEFAULT           0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL_1 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_DEFAULT           0x00000000
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* AON_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK     0xffffffff
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT    0
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT  0x00000000
+
+/***************************************************************************
+ *RESET_HISTORY - Reset History Register For AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_HISTORY :: reserved0 [31:19] */
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_MASK                 0xfff80000
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_SHIFT                19
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [18:18] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK    0x00040000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT   18
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [17:17] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK    0x00020000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT   17
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [16:16] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK     0x00010000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT    16
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [15:15] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK     0x00008000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT    15
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [14:14] */
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK           0x00004000
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT          14
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_DEFAULT        0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: overtemp_reset [13:13] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_MASK            0x00002000
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_SHIFT           13
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_DEFAULT         0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: overvoltage_reset [12:12] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_MASK         0x00001000
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT        12
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_DEFAULT      0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: undervoltage_reset [11:11] */
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_MASK        0x00000800
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT       11
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_DEFAULT     0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: security_dl_sw_reset [10:10] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK      0x00000400
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT     10
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_DEFAULT   0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: security_master_reset [09:09] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_MASK     0x00000200
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_SHIFT    9
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: software_master_reset [08:08] */
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_MASK     0x00000100
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_SHIFT    8
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [07:07] */
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK       0x00000080
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT      7
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_DEFAULT    0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: watchdog_timer_reset [06:06] */
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK      0x00000040
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT     6
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_DEFAULT   0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: smartcard_insert_reset [05:05] */
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK    0x00000020
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT   5
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: s3_wakeup_reset [04:04] */
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_MASK           0x00000010
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_SHIFT          4
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_DEFAULT        0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [03:03] */
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK    0x00000008
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT   3
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: tap_in_system_reset [02:02] */
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_MASK       0x00000004
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_SHIFT      2
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_DEFAULT    0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_MASK     0x00000002
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT    1
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_MASK            0x00000001
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_SHIFT           0
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_DEFAULT         0x00000001
+
+/***************************************************************************
+ *NMI_CTRL - Control register for NMI
+ ***************************************************************************/
+/* AON_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_MASK                0x80000000
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_SHIFT               31
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_DEFAULT             0x00000000
+
+/* AON_CTRL :: NMI_CTRL :: reserved0 [30:03] */
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_MASK                      0x7ffffff8
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_SHIFT                     3
+
+/* AON_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_MASK                0x00000004
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT               2
+
+/* AON_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_MASK            0x00000002
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT           1
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_DEFAULT         0x00000000
+
+/* AON_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_MASK                0x00000001
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT               0
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_DEFAULT             0x00000001
+
+/***************************************************************************
+ *ANA_XTAL_CONTROL - Ana xtal low cur 40g m7fc gisb control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_CONTROL :: reserved0 [31:07] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_MASK              0xffffff80
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_SHIFT             7
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_test_select_gisb_control [06:06] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_MASK 0x00000040
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_SHIFT 6
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_select_current_gisb_control [05:05] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_MASK 0x00000020
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_SHIFT 5
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_cml_sel_pd [04:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_MASK         0x00000018
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_SHIFT        3
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_DEFAULT      0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_d2cbias_gisb_control [02:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_MASK 0x00000007
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_SHIFT 0
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_DEFAULT 0x00000004
+
+/***************************************************************************
+ *SUB_TEST_MODE_CTRL - Test_mode control register
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: reserved0 [31:01] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_MASK            0xfffffffe
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_SHIFT           1
+
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: use_sub_test_mode_reg_src [00:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_MASK 0x00000001
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_SHIFT 0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SUB_TEST_MODE - Register source for sub_test_mode
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE :: reserved0 [31:09] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_MASK                 0xfffffe00
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_SHIFT                9
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [08:08] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK     0x00000100
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT    8
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_DEFAULT  0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [07:07] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK     0x00000080
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT    7
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_DEFAULT  0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_d2cdiff_ac [06:06] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_MASK  0x00000040
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_SHIFT 6
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [05:05] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK   0x00000020
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT  5
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_mips_in_reset [04:04] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_MASK 0x00000010
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_SHIFT 4
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [03:03] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000008
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 3
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [02:02] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000004
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 2
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK   0x00000003
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT  0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_DEFAULT 0x00000000
+
+/***************************************************************************
+ *LATCHED_TEST_MODE - Final latched testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK     0xffffffff
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT    0
+
+/***************************************************************************
+ *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0
+
+/***************************************************************************
+ *PM_INITIATE - Power down initiate
+ ***************************************************************************/
+/* AON_CTRL :: PM_INITIATE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_MASK                   0xffffff00
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_SHIFT                  8
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_7 [07:07] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_MASK               0x00000080
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_SHIFT              7
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_6 [06:06] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_MASK               0x00000040
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_SHIFT              6
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_5 [05:05] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_MASK               0x00000020
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_SHIFT              5
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_4 [04:04] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_MASK               0x00000010
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_SHIFT              4
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_3 [03:03] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_MASK               0x00000008
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_SHIFT              3
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_2 [02:02] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_MASK               0x00000004
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_SHIFT              2
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_1 [01:01] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_MASK               0x00000002
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_SHIFT              1
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_0 [00:00] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_MASK               0x00000001
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_SHIFT              0
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_DEFAULT            0x00000000
+
+/***************************************************************************
+ *HOST_MISC_CMDS - Power up restore
+ ***************************************************************************/
+/* AON_CTRL :: HOST_MISC_CMDS :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_MASK                0xffffff00
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_SHIFT               8
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_7 [07:07] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_MASK         0x00000080
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_SHIFT        7
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_6 [06:06] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_MASK         0x00000040
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_SHIFT        6
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_5 [05:05] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_MASK         0x00000020
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_SHIFT        5
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_4 [04:04] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_MASK         0x00000010
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_SHIFT        4
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_3 [03:03] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_MASK         0x00000008
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_SHIFT        3
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_2 [02:02] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_MASK         0x00000004
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_SHIFT        2
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: dram_scram_key_reuse_req [01:01] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_MASK 0x00000002
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_SHIFT 1
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_DEFAULT 0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: pm_restore [00:00] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_MASK               0x00000001
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_SHIFT              0
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_BASE                  0x00408200
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_START                 0
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_END                   127
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_ELEMENT_SIZE          32
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_RAMi :: SYSTEM_DATA_RAM [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_MASK        0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_SHIFT       0
+
+
+#endif /* #ifndef BCHP_AON_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_aon_pin_ctrl.h b/include/linux/brcmstb/7360a0/bchp_aon_pin_ctrl.h
new file mode 100644
index 0000000..aa67f14
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_aon_pin_ctrl.h
@@ -0,0 +1,651 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_aon_pin_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:25a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PIN_CTRL_H__
+#define BCHP_AON_PIN_CTRL_H__
+
+/***************************************************************************
+ *AON_PIN_CTRL - AON Pinmux Control Registers
+ ***************************************************************************/
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0         0x00408500 /* Pinmux control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1         0x00408504 /* Pinmux control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2         0x00408508 /* Pinmux control register 2 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3         0x0040850c /* Pinmux control register 3 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0     0x00408510 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1     0x00408514 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2     0x00408518 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0     0x0040851c /* Bypass clock unselect register 0 */
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_05 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_AON_GPIO_05   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_LD1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PKT5_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_I2S_DATA0_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SC_CLK_OUT    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MTSIF_ATS_RST 5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SDS0_DSEC_SELVTOP 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SC1_AUX1      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_TP_IN_05      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PM_AON_GPIO_05 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_04 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_AON_GPIO_04   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_LD0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PKT5_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_I2S_CLK0_OUT  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_EXT_IRQ1      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_IR_OUT        5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SDS0_TNR_SDA  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SC1_VPP       7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_TP_IN_04      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PM_AON_GPIO_04 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_03 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_GPIO_03   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_OUT       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PWR_BUTTON    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_FP_4SEC_RESETB 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_EXT_IRQ0      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_IR_OUT        5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SDS0_TNR_SCL  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SDIO0_PRES    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_TP_IN_03      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PM_AON_GPIO_03 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_01 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AON_GPIO_01   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET_LINK     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_PWM0          2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET_ACTIVITY 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_IR_OUT        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_VEC_HSYNC     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_RMX1_VALID    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SDS0_TNR_SCL  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_TP_OUT_01     8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_00 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AON_GPIO_00   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AUD_SPDIF     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_CLK_OBSRV1    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_TP_OUT_00     3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_hdmi_htplg [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_MASK       0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_SHIFT      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_DEFAULT    0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_AON_HDMI_HTPLG 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_TP_IN_02   1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_s3_standbyb [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_MASK      0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_SHIFT     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_DEFAULT   0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_AON_S3_STANDBYB 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_TP_IN_01  1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_ir_in0 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_MASK           0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_SHIFT          0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_DEFAULT        0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_AON_IR_IN0     0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_TP_IN_00       1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_13 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_AON_GPIO_13   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_LED_LS1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PKT2_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_I2S_DATA0_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PWM0          4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SDIO0_CLK     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_USB0_PWRFLT_1 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MTSIF0_DATA0  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_TP_OUT_05     8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PM_AON_GPIO_13 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_12 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_AON_GPIO_12   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_LS0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PKT2_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_I2S_CLK0_OUT  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_OUT       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SDIO0_PWR0    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MTSIF0_CLK    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_TP_OUT_04     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PM_AON_GPIO_12 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_11 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_GPIO_11   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_LED_LD7       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SC1_CLK       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_CODEC_MCLK    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_CLK_27    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SPI_M_SCK     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_TP_OUT_03     6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_10 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_AON_GPIO_10   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_LED_LD6       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SC1_VCC       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_CODEC_SDO     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_UART_RTS2     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SPI_M_SS0B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_TP_OUT_02     6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_09 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_AON_GPIO_09   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_LED_LD5       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SC1_RST       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_CODEC_SCLK    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_UART_TX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SPI_M_MOSI    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_FSK_RX_BYP_DATA 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MTSIF0_DATA5  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_TP_IN_09      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_PM_AON_GPIO_09 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_08 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_AON_GPIO_08   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_LED_LD4       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SC1_IO        2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_CODEC_FSYNCB  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_UART_CTS2     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SPI_M_SS1B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SDIO0_PRES    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MTSIF0_DATA1  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_TP_IN_08      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_PM_AON_GPIO_08 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_07 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_AON_GPIO_07   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_LED_LD3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SC1_PRES      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_CODEC_SDI     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_UART_RX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SPI_M_MISO    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_FSK_UART_DATA 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MTSIF0_VALID  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_TP_IN_07      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_PM_AON_GPIO_07 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_06 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_AON_GPIO_06   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_LED_LD2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PKT5_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_I2S_LR0_OUT   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SC_EXT_CLK    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_VEC_VSYNC     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SDS0_DSEC_VCTL 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SC1_AUX2      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_TP_IN_06      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PM_AON_GPIO_06 9
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_00 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_MASK         0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SHIFT        28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_AON_SGPIO_00 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_BSC_M3_SCL   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_USB0_PWRFLT_1 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_EXT_IRQ2     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SDS0_TNR_SCL 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_TP_IN_16     5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_20 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_GPIO_20   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_LED_KD3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PKT4_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_CLK_OBSRV0    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_CLK_27    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SDIO0_WPROT   5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_RO_OBSRV      6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MTSIF0_DATA7  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_TP_IN_15      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PM_AON_GPIO_20 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_19 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_AON_GPIO_19   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_LED_KD2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_PKT4_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SC1_PRES      3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SPI_M_MISO    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SDIO0_CMD     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MTSIF0_DATA6  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_TP_IN_14      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_PM_AON_GPIO_19 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_18 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_AON_GPIO_18   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_LED_KD1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PKT4_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SC1_IO        3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SPI_M_SS1B    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SDIO0_DAT3    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MTSIF_ATS_INC 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_TP_IN_13      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PM_AON_GPIO_18 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_17 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_AON_GPIO_17   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_LED_KD0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PKT3_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SC1_RST       3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SPI_M_MOSI    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SDIO0_DAT2    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PWR_BUTTON    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MTSIF0_DATA4  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_TP_IN_12      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PM_AON_GPIO_17 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_16 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_AON_GPIO_16   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_LED_LS4       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PKT3_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SC1_CLK       3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SPI_M_SCK     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SDIO0_DAT1    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MTSIF0_DATA3  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_TP_IN_11      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PM_AON_GPIO_16 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_15 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_AON_GPIO_15   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_LED_LS3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PKT3_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SC1_VCC       3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SPI_M_SS0B    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SDIO0_DAT0    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_MTSIF0_DATA2  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_TP_IN_10      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PM_AON_GPIO_15 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_14 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_AON_GPIO_14   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_LED_LS2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_PKT2_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_I2S_LR0_OUT   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SDIO0_LED     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_USB0_PWRFLT_2 5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_MTSIF0_SYNC   6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_TP_OUT_06     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_PM_AON_GPIO_14 8
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: reserved0 [31:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_MASK            0xfffff000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_SHIFT           12
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: sgpio_01 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_MASK             0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_SHIFT            8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_DEFAULT          0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_SGPIO_01         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_BSC_M0_SDA       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_HDMI_TX_BSC_SDA  2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: sgpio_00 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_MASK             0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_SHIFT            4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_DEFAULT          0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_SGPIO_00         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_BSC_M0_SCL       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_HDMI_TX_BSC_SCL  2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_01 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_MASK         0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_SHIFT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_AON_SGPIO_01 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_BSC_M3_SDA   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_USB0_PWRFLT_2 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_EXT_IRQ3     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_SDS0_TNR_SDA 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_TP_IN_17     5
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_08_pad_ctrl [29:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_MASK 0x30000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_SHIFT 28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_07_pad_ctrl [27:26] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_MASK 0x0c000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_SHIFT 26
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_06_pad_ctrl [25:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_MASK 0x03000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_SHIFT 24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_05_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_04_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_03_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_01_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_00_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [13:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x00003fff
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0x3f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       24
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_20_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_19_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_18_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_17_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_16_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_15_pad_ctrl [13:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_MASK 0x00003000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_SHIFT 12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_14_pad_ctrl [11:10] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_MASK 0x00000c00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_SHIFT 10
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_13_pad_ctrl [09:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_MASK 0x00000300
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_SHIFT 8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_12_pad_ctrl [07:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_MASK 0x000000c0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_SHIFT 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_11_pad_ctrl [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_10_pad_ctrl [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_09_pad_ctrl [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_MASK 0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_SHIFT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [31:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK        0xfffffff0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT       4
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved1 [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_MASK        0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_SHIFT       0
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:04] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffff0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       4
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_01 [03:03] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_MASK 0x00000008
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_SHIFT 3
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_00 [02:02] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_MASK 0x00000004
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_SHIFT 2
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_nmib [01:01] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_MASK 0x00000002
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_SHIFT 1
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_reset_outb [00:00] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_MASK 0x00000001
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_SHIFT 0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_AON_PIN_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_aon_pm_l2.h b/include/linux/brcmstb/7360a0/bchp_aon_pm_l2.h
new file mode 100644
index 0000000..f4e7e25
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_aon_pm_l2.h
@@ -0,0 +1,1107 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_aon_pm_l2.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:25a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PM_L2_H__
+#define BCHP_AON_PM_L2_H__
+
+/***************************************************************************
+ *AON_PM_L2 - AON Power Management L2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_AON_PM_L2_CPU_STATUS                0x00408440 /* CPU interrupt Status Register */
+#define BCHP_AON_PM_L2_CPU_SET                   0x00408444 /* CPU interrupt Set Register */
+#define BCHP_AON_PM_L2_CPU_CLEAR                 0x00408448 /* CPU interrupt Clear Register */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS           0x0040844c /* CPU interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_CPU_MASK_SET              0x00408450 /* CPU interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR            0x00408454 /* CPU interrupt Mask Clear Register */
+#define BCHP_AON_PM_L2_PCI_STATUS                0x00408458 /* PCI interrupt Status Register */
+#define BCHP_AON_PM_L2_PCI_SET                   0x0040845c /* PCI interrupt Set Register */
+#define BCHP_AON_PM_L2_PCI_CLEAR                 0x00408460 /* PCI interrupt Clear Register */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS           0x00408464 /* PCI interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_PCI_MASK_SET              0x00408468 /* PCI interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR            0x0040846c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_STATUS :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_MASK                   0xffff0000
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_SHIFT                  16
+
+/* AON_PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x00008000
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       15
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_MASK                    0x00004000
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_SHIFT                   14
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00002000
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_SHIFT          13
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_MASK                     0x00001000
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_SHIFT                    12
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_MASK                         0x00000800
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_SHIFT                        11
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_MASK                   0x00000400
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_SHIFT                  10
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_MASK                   0x00000200
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_SHIFT                  9
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_MASK                 0x00000100
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_SHIFT                8
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_DEFAULT              0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_MASK                 0x00000080
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_SHIFT                7
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_DEFAULT              0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_MASK                    0x00000040
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_SHIFT                   6
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_SET :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_MASK                      0xffff0000
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_SHIFT                     16
+
+/* AON_PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_MASK           0x00008000
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_SHIFT          15
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_MASK                       0x00004000
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_SHIFT                      14
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_MASK              0x00002000
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_SHIFT             13
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_DEFAULT           0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_MASK                        0x00001000
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_SHIFT                       12
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_SET_FTM_MASK                            0x00000800
+#define BCHP_AON_PM_L2_CPU_SET_FTM_SHIFT                           11
+#define BCHP_AON_PM_L2_CPU_SET_FTM_DEFAULT                         0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_MASK                      0x00000400
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_SHIFT                     10
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_MASK                      0x00000200
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_SHIFT                     9
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_MASK                    0x00000100
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_SHIFT                   8
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_MASK                    0x00000080
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_SHIFT                   7
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_MASK                       0x00000040
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_SHIFT                      6
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_CLEAR :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_MASK                    0xffff0000
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_SHIFT                   16
+
+/* AON_PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x00008000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        15
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_MASK                     0x00004000
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_SHIFT                    14
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00002000
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           13
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_MASK                      0x00001000
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT                     12
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_MASK                          0x00000800
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_SHIFT                         11
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_DEFAULT                       0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_MASK                    0x00000400
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_SHIFT                   10
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_MASK                    0x00000200
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_SHIFT                   9
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_MASK                  0x00000100
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_SHIFT                 8
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_MASK                  0x00000080
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_SHIFT                 7
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_MASK                     0x00000040
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_SHIFT                    6
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_MASK              0xffff0000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT             16
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  15
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_MASK               0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_SHIFT              14
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     13
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK                0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT               12
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_MASK                    0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_SHIFT                   11
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_MASK              0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_SHIFT             10
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_MASK              0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_SHIFT             9
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_MASK            0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_SHIFT           8
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_DEFAULT         0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_MASK            0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_SHIFT           7
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_DEFAULT         0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_MASK               0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_SHIFT              6
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_DEFAULT            0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_SET :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_MASK                 0xffff0000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_SHIFT                16
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     15
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_MASK                  0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_SHIFT                 14
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        13
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_MASK                   0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT                  12
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_MASK                       0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_SHIFT                      11
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_DEFAULT                    0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_MASK                 0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_SHIFT                10
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_MASK                 0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_SHIFT                9
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_MASK               0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_SHIFT              8
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_MASK               0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_SHIFT              7
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_MASK                  0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_SHIFT                 6
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_DEFAULT               0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_MASK               0xffff0000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT              16
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   15
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_MASK                0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_SHIFT               14
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      13
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK                 0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT                12
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_MASK                     0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_SHIFT                    11
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_DEFAULT                  0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_MASK               0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_SHIFT              10
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_MASK               0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_SHIFT              9
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_MASK             0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_SHIFT            8
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_MASK             0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_SHIFT            7
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_MASK                0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_SHIFT               6
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_DEFAULT             0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_STATUS :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_MASK                   0xffff0000
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_SHIFT                  16
+
+/* AON_PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x00008000
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       15
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_MASK                    0x00004000
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_SHIFT                   14
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00002000
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_SHIFT          13
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_MASK                     0x00001000
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_SHIFT                    12
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_MASK                         0x00000800
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_SHIFT                        11
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_MASK                   0x00000400
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_SHIFT                  10
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_MASK                   0x00000200
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_SHIFT                  9
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_MASK                 0x00000100
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_SHIFT                8
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_DEFAULT              0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_MASK                 0x00000080
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_SHIFT                7
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_DEFAULT              0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_MASK                    0x00000040
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_SHIFT                   6
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_SET :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_MASK                      0xffff0000
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_SHIFT                     16
+
+/* AON_PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_MASK           0x00008000
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_SHIFT          15
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_MASK                       0x00004000
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_SHIFT                      14
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_MASK              0x00002000
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_SHIFT             13
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_DEFAULT           0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_MASK                        0x00001000
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_SHIFT                       12
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_SET_FTM_MASK                            0x00000800
+#define BCHP_AON_PM_L2_PCI_SET_FTM_SHIFT                           11
+#define BCHP_AON_PM_L2_PCI_SET_FTM_DEFAULT                         0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_MASK                      0x00000400
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_SHIFT                     10
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_MASK                      0x00000200
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_SHIFT                     9
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_MASK                    0x00000100
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_SHIFT                   8
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_MASK                    0x00000080
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_SHIFT                   7
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_MASK                       0x00000040
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_SHIFT                      6
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_CLEAR :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_MASK                    0xffff0000
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_SHIFT                   16
+
+/* AON_PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x00008000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        15
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_MASK                     0x00004000
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_SHIFT                    14
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00002000
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           13
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_MASK                      0x00001000
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT                     12
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_MASK                          0x00000800
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_SHIFT                         11
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_DEFAULT                       0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_MASK                    0x00000400
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_SHIFT                   10
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_MASK                    0x00000200
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_SHIFT                   9
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_MASK                  0x00000100
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_SHIFT                 8
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_MASK                  0x00000080
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_SHIFT                 7
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_MASK                     0x00000040
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_SHIFT                    6
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_MASK              0xffff0000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT             16
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  15
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_MASK               0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_SHIFT              14
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     13
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK                0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT               12
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_MASK                    0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_SHIFT                   11
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_MASK              0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_SHIFT             10
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_MASK              0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_SHIFT             9
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_MASK            0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_SHIFT           8
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_DEFAULT         0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_MASK            0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_SHIFT           7
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_DEFAULT         0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_MASK               0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_SHIFT              6
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_DEFAULT            0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_SET :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_MASK                 0xffff0000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_SHIFT                16
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     15
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_MASK                  0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_SHIFT                 14
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        13
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_MASK                   0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT                  12
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_MASK                       0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_SHIFT                      11
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_DEFAULT                    0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_MASK                 0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_SHIFT                10
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_MASK                 0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_SHIFT                9
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_MASK               0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_SHIFT              8
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_MASK               0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_SHIFT              7
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_MASK                  0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_SHIFT                 6
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_DEFAULT               0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_MASK               0xffff0000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT              16
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   15
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_MASK                0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_SHIFT               14
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      13
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK                 0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT                12
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_MASK                     0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_SHIFT                    11
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_DEFAULT                  0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_MASK               0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_SHIFT              10
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_MASK               0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_SHIFT              9
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_MASK             0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_SHIFT            8
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_MASK             0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_SHIFT            7
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_MASK                0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_SHIFT               6
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_DEFAULT             0x00000001
+
+#endif /* #ifndef BCHP_AON_PM_L2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_bspi.h b/include/linux/brcmstb/7360a0/bchp_bspi.h
new file mode 100644
index 0000000..35cd173
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_bspi.h
@@ -0,0 +1,446 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_bspi.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:37a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_H__
+#define BCHP_BSPI_H__
+
+/***************************************************************************
+ *BSPI - Public BSPI Control Registers
+ ***************************************************************************/
+#define BCHP_BSPI_REVISION_ID                    0x00413000 /* Revision ID */
+#define BCHP_BSPI_SCRATCH                        0x00413004 /* Revision ID */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL               0x00413008 /* Master/Boot SPI Control Register */
+#define BCHP_BSPI_BUSY_STATUS                    0x0041300c /* BSPI Busy Status Register */
+#define BCHP_BSPI_INTR_STATUS                    0x00413010 /* Interrupt Status Register */
+#define BCHP_BSPI_B0_STATUS                      0x00413014 /* Prefetch Buffer 0 Status Register */
+#define BCHP_BSPI_B0_CTRL                        0x00413018 /* Prefetch Buffer 0 Control Register */
+#define BCHP_BSPI_B1_STATUS                      0x0041301c /* Prefetch Buffer 1 Status Register */
+#define BCHP_BSPI_B1_CTRL                        0x00413020 /* Prefetch Buffer 1 Control Register */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL            0x00413024 /* Dual/Single Receive Mode Control Register */
+#define BCHP_BSPI_FLEX_MODE_ENABLE               0x00413028 /* Flexible Control Mode Enable Register */
+#define BCHP_BSPI_BITS_PER_CYCLE                 0x0041302c /* Bits per cycle "b-p-c" Control Register */
+#define BCHP_BSPI_BITS_PER_PHASE                 0x00413030 /* Bits per Phase "b-p-p" Control Register */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE              0x00413034 /* Command and Mode Data Register */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE     0x00413038 /* Bspi FLash upper address byte register */
+#define BCHP_BSPI_BSPI_XOR_VALUE                 0x0041303c /* BSPI FLASH XOR Value Register */
+#define BCHP_BSPI_BSPI_XOR_ENABLE                0x00413040 /* BSPI FLASH XOR Enable Register */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE           0x00413044 /* BSPI Pin  Programmed IO Mode Enable Register */
+#define BCHP_BSPI_BSPI_PIO_IODIR                 0x00413048 /* BSPI Pin  Programmed IO Mode Direction Register */
+#define BCHP_BSPI_BSPI_PIO_DATA                  0x0041304c /* BSPI Pin  Programmed IO Mode Data Register */
+
+/***************************************************************************
+ *REVISION_ID - Revision ID
+ ***************************************************************************/
+/* BSPI :: REVISION_ID :: reserved0 [31:16] */
+#define BCHP_BSPI_REVISION_ID_reserved0_MASK                       0xffff0000
+#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT                      16
+
+/* BSPI :: REVISION_ID :: MAJOR [15:08] */
+#define BCHP_BSPI_REVISION_ID_MAJOR_MASK                           0x0000ff00
+#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT                          8
+#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT                        0x00000004
+
+/* BSPI :: REVISION_ID :: MINOR [07:00] */
+#define BCHP_BSPI_REVISION_ID_MINOR_MASK                           0x000000ff
+#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT                          0
+#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT                        0x00000001
+
+/***************************************************************************
+ *SCRATCH - Revision ID
+ ***************************************************************************/
+/* BSPI :: SCRATCH :: SCRATCH [31:00] */
+#define BCHP_BSPI_SCRATCH_SCRATCH_MASK                             0xffffffff
+#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT                            0
+#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
+ ***************************************************************************/
+/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT                 1
+
+/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK                0x00000001
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT               0
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT             0x00000000
+
+/***************************************************************************
+ *BUSY_STATUS - BSPI Busy Status Register
+ ***************************************************************************/
+/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
+#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK                       0xfffffffe
+#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT                      1
+
+/* BSPI :: BUSY_STATUS :: busy [00:00] */
+#define BCHP_BSPI_BUSY_STATUS_busy_MASK                            0x00000001
+#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT                           0
+#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *INTR_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
+#define BCHP_BSPI_INTR_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT                      2
+
+/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
+#define BCHP_BSPI_INTR_STATUS_intr_1_MASK                          0x00000002
+#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT                         1
+#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT                       0x00000000
+
+/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
+#define BCHP_BSPI_INTR_STATUS_intr_0_MASK                          0x00000001
+#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT                         0
+#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *B0_STATUS - Prefetch Buffer 0 Status Register
+ ***************************************************************************/
+/* BSPI :: B0_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B0_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B0_STATUS :: b0_full [29:29] */
+#define BCHP_BSPI_B0_STATUS_b0_full_MASK                           0x20000000
+#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT                          29
+#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_empty [28:28] */
+#define BCHP_BSPI_B0_STATUS_b0_empty_MASK                          0x10000000
+#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT                         28
+#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B0_STATUS :: b0_miss [27:27] */
+#define BCHP_BSPI_B0_STATUS_b0_miss_MASK                           0x08000000
+#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT                          27
+#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_hit [26:26] */
+#define BCHP_BSPI_B0_STATUS_b0_hit_MASK                            0x04000000
+#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT                           26
+#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B0_STATUS :: b0_address [25:00] */
+#define BCHP_BSPI_B0_STATUS_b0_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT                       0
+#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B0_CTRL - Prefetch Buffer 0 Control Register
+ ***************************************************************************/
+/* BSPI :: B0_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B0_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B0_CTRL :: b0_flush [00:00] */
+#define BCHP_BSPI_B0_CTRL_b0_flush_MASK                            0x00000001
+#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT                           0
+#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *B1_STATUS - Prefetch Buffer 1 Status Register
+ ***************************************************************************/
+/* BSPI :: B1_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B1_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B1_STATUS :: b1_full [29:29] */
+#define BCHP_BSPI_B1_STATUS_b1_full_MASK                           0x20000000
+#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT                          29
+#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_empty [28:28] */
+#define BCHP_BSPI_B1_STATUS_b1_empty_MASK                          0x10000000
+#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT                         28
+#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B1_STATUS :: b1_miss [27:27] */
+#define BCHP_BSPI_B1_STATUS_b1_miss_MASK                           0x08000000
+#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT                          27
+#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_hit [26:26] */
+#define BCHP_BSPI_B1_STATUS_b1_hit_MASK                            0x04000000
+#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT                           26
+#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B1_STATUS :: b1_address [25:00] */
+#define BCHP_BSPI_B1_STATUS_b1_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT                       0
+#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B1_CTRL - Prefetch Buffer 1 Control Register
+ ***************************************************************************/
+/* BSPI :: B1_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B1_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B1_CTRL :: b1_flush [00:00] */
+#define BCHP_BSPI_B1_CTRL_b1_flush_MASK                            0x00000001
+#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT                           0
+#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
+ ***************************************************************************/
+/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK               0xffffffe0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT              5
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK             0x00000010
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT            4
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT          0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK               0x00000008
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT              3
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT            0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK      0x00000004
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT     2
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT   0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK         0x00000002
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT        1
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT      0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK                0x00000001
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT               0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT             0x00000000
+
+/***************************************************************************
+ *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT                 1
+
+/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK      0x00000001
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT     0
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT   0x00000000
+
+/***************************************************************************
+ *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK                    0xfc000000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT                   26
+
+/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK               0x03000000
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK                    0x00fc0000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT                   18
+
+/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK              0x00030000
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK                    0x0000fc00
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT                   10
+
+/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK              0x00000300
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT             8
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK                    0x000000fc
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT                   2
+
+/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK              0x00000003
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT             0
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT           0x00000000
+
+/***************************************************************************
+ *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK                    0xfe000000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT                   25
+
+/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK               0x01000000
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK                    0x00fe0000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT                   17
+
+/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK              0x00010000
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK                    0x0000fe00
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT                   9
+
+/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK                     0x00000100
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT                    8
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT                  0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK                 0x000000ff
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT                0
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT              0x00000008
+
+/***************************************************************************
+ *CMD_AND_MODE_BYTE - Command and Mode Data Register
+ ***************************************************************************/
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK                 0xff000000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT                24
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK            0x00ff0000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT           16
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT         0x00000000
+
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK                 0x0000ff00
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT                8
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK             0x000000ff
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT            0
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT          0x0000000b
+
+/***************************************************************************
+ *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
+ ***************************************************************************/
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0x00000000
+
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK        0x00ffffff
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT       0
+
+/***************************************************************************
+ *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK               0xfff00000
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT              20
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT            0x00000000
+
+/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK                    0x000fffff
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT                  1
+
+/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK             0x00000001
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT            0
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT          0x00000000
+
+/***************************************************************************
+ *BSPI_PIO_MODE_ENABLE - BSPI Pin  Programmed IO Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK              0xfffffffe
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT             1
+
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK          0x00000001
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT         0
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT       0x00000000
+
+/***************************************************************************
+ *BSPI_PIO_IODIR - BSPI Pin  Programmed IO Mode Direction Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK                    0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT                   3
+
+/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT              0x00000003
+
+/***************************************************************************
+ *BSPI_PIO_DATA - BSPI Pin  Programmed IO Mode Data Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK                     0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT                    3
+
+/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT              0x00000000
+
+#endif /* #ifndef BCHP_BSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_bspi_raf.h b/include/linux/brcmstb/7360a0/bchp_bspi_raf.h
new file mode 100644
index 0000000..22407cc
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_bspi_raf.h
@@ -0,0 +1,163 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_bspi_raf.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:37a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_RAF_H__
+#define BCHP_BSPI_RAF_H__
+
+/***************************************************************************
+ *BSPI_RAF - Public Linear Read BSPI Pipe Registers
+ ***************************************************************************/
+#define BCHP_BSPI_RAF_START_ADDR                 0x00413100 /* Physical Starting Address Location in Flash device */
+#define BCHP_BSPI_RAF_NUM_WORDS                  0x00413104 /* Number of Words to be fetched */
+#define BCHP_BSPI_RAF_CTRL                       0x00413108 /* RAF Session Control Register */
+#define BCHP_BSPI_RAF_FULLNESS                   0x0041310c /* Fullness indicator for the read ahead buffer */
+#define BCHP_BSPI_RAF_WATERMARK                  0x00413110 /* Watermark level in the read ahead buffer that triggers an interrupt */
+#define BCHP_BSPI_RAF_STATUS                     0x00413114 /* Linear Read Status Register */
+#define BCHP_BSPI_RAF_READ_DATA                  0x00413118 /* Read data from Raf-buffer */
+#define BCHP_BSPI_RAF_WORD_CNT                   0x0041311c /* Current number of words fetched from Flash */
+#define BCHP_BSPI_RAF_CURR_ADDR                  0x00413120 /* Current read address for the linear read session */
+
+/***************************************************************************
+ *START_ADDR - Physical Starting Address Location in Flash device
+ ***************************************************************************/
+/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK                   0xffffffff
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT                  0
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT                0x00000000
+
+/***************************************************************************
+ *NUM_WORDS - Number of Words to be fetched
+ ***************************************************************************/
+/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK                      0xffffffff
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT                     0
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *CTRL - RAF Session Control Register
+ ***************************************************************************/
+/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT                         2
+
+/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
+#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK                              0x00000002
+#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT                             1
+#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT                           0x00000000
+
+/* BSPI_RAF :: CTRL :: START [00:00] */
+#define BCHP_BSPI_RAF_CTRL_START_MASK                              0x00000001
+#define BCHP_BSPI_RAF_CTRL_START_SHIFT                             0
+#define BCHP_BSPI_RAF_CTRL_START_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *FULLNESS - Fullness indicator for the read ahead buffer
+ ***************************************************************************/
+/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK                      0xffffff80
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT                     7
+
+/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK                       0x0000007f
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT                      0
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
+ ***************************************************************************/
+/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK                     0xfffffffc
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT                    2
+
+/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK            0x00000003
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT           0
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STATUS - Linear Read Status Register
+ ***************************************************************************/
+/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
+#define BCHP_BSPI_RAF_STATUS_reserved0_MASK                        0xfffffff8
+#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT                       3
+
+/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK                        0x00000004
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT                       2
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT                     0x00000000
+
+/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK                       0x00000002
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT                      1
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT                    0x00000001
+
+/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK                     0x00000001
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT                    0
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *READ_DATA - Read data from Raf-buffer
+ ***************************************************************************/
+/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
+#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK                          0xffffffff
+#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT                         0
+#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *WORD_CNT - Current number of words fetched from Flash
+ ***************************************************************************/
+/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK             0xffffffff
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT            0
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *CURR_ADDR - Current read address for the linear read session
+ ***************************************************************************/
+/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK               0xffffffff
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT              0
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT            0x00000000
+
+#endif /* #ifndef BCHP_BSPI_RAF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_clkgen.h b/include/linux/brcmstb/7360a0/bchp_clkgen.h
new file mode 100644
index 0000000..097fbb9
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_clkgen.h
@@ -0,0 +1,4636 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_clkgen.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:41a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_CLKGEN_H__
+#define BCHP_CLKGEN_H__
+
+/***************************************************************************
+ *CLKGEN - clkgen registers
+ ***************************************************************************/
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL       0x00420000 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV           0x00420004 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN          0x00420008 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS   0x0042000c /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN         0x00420010 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET         0x00420014 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x00420018 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x0042001c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS        0x00420020 /* Test Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL       0x00420024 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV           0x00420028 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN          0x0042002c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS   0x00420030 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN         0x00420034 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET         0x00420038 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x0042003c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x00420040 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS        0x00420044 /* Test Status */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 0x00420048 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 0x0042004c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 0x00420050 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 0x00420054 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL     0x00420058 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV         0x0042005c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN        0x00420060 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS 0x00420064 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC        0x00420068 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2       0x0042006c /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN       0x00420070 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x00420074 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x00420078 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS      0x0042007c /* Test Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0 0x00420080 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1 0x00420084 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3 0x00420088 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL           0x0042008c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV               0x00420090 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN              0x00420094 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS       0x00420098 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC              0x0042009c /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN             0x004200a0 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET             0x004200a4 /* Resets */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH 0x004200a8 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW 0x004200ac /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS            0x004200b0 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x004200b4 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x004200b8 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x004200bc /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x004200c0 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x004200c4 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x004200c8 /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL         0x004200cc /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV             0x004200d0 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN            0x004200d4 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS     0x004200d8 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC            0x004200dc /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2           0x004200e0 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN           0x004200e4 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x004200e8 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x004200ec /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS          0x004200f0 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 0x004200f4 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 0x004200f8 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 0x004200fc /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 0x00420100 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 0x00420104 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL         0x00420108 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV             0x0042010c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN            0x00420110 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS     0x00420114 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC            0x00420118 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN           0x0042011c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET           0x00420120 /* Resets */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH 0x00420124 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW 0x00420128 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS          0x0042012c /* Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 0x00420130 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 0x00420134 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 0x00420138 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL         0x0042013c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV             0x00420140 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC            0x00420144 /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN            0x00420148 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS     0x0042014c /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC            0x00420150 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN           0x00420154 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET           0x00420158 /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH 0x0042015c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW 0x00420160 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS          0x00420164 /* Status */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE        0x00420168 /* Avd0 top clock enable */
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE 0x0042016c /* Avd0 top memory standby enable */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK       0x00420170 /* Avd0 top observe clock */
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY 0x00420174 /* Avd0 top power switch memory */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE   0x00420178 /* Disable BCM_MIPS_TOP's clocks */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE    0x0042017c /* Bcm mips top clock enable */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE 0x00420180 /* Bcm mips top memory standby enable */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK   0x00420184 /* Bcm mips top observe clock */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY 0x00420188 /* Bcm mips top power switch memory */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT          0x0042018c /* Bcm mips top select */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE               0x00420190 /* Bvn top enable */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE 0x00420194 /* Bvn top memory standby enable */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY  0x00420198 /* Bvn top power switch memory */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x0042019c /* Cktap 108 0 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201a0 /* Cktap 108 1 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201a4 /* Cktap 108 2 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201a8 /* Cktap 216 0 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK 0x004201ac /* CKTAP CPU Adjustment System 108 Clock */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK 0x004201b0 /* CKTAP CPU Adjustment System 216 Clock */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK 0x004201b4 /* CKTAP CPU Adjustment System Scb Clock */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201b8 /* Cktap scb 0 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201bc /* Cktap scb 1 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE         0x004201c0 /* Disable CLKGEN's clocks */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL        0x004201c4 /* Clock Monitor Control */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT      0x004201c8 /* Clock Monitor Max Reference Count */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER    0x004201cc /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE       0x004201d0 /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER   0x004201d4 /* Clock Monitor View Counter */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE       0x004201d8 /* Disable CORE_XPT's clocks */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE        0x004201dc /* Core xpt clock enable */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE 0x004201e0 /* Core xpt memory standby enable */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK       0x004201e4 /* Core xpt observe clock */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY 0x004201e8 /* Core xpt power switch memory */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE         0x004201ec /* Disable DVP_HT's clocks */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE          0x004201f0 /* Dvp ht clock enable */
+#define BCHP_CLKGEN_DVP_HT_ENABLE                0x004201f4 /* Dvp ht enable */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE 0x004201f8 /* Dvp ht memory standby enable */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK         0x004201fc /* Dvp ht observe clock */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY   0x00420200 /* Dvp ht power switch memory */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE         0x00420204 /* Fsk top clock enable */
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE 0x00420208 /* Fsk top memory standby enable */
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY  0x0042020c /* Fsk top power switch memory */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE 0x00420210 /* Disable GENET_TOP_RGMII_INST's clocks */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE 0x00420214 /* Genet top rgmii inst clock enable */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT 0x00420218 /* Genet top rgmii inst clock select */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A 0x0042021c /* Genet top rgmii inst memory standby enable a */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK 0x00420220 /* Genet top rgmii inst observe clock */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A 0x00420224 /* Genet top rgmii inst power switch memory a */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE       0x00420228 /* Disable GRAPHICS's clocks */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE        0x0042022c /* Graphics clock enable */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE 0x00420230 /* Graphics memory standby enable */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK       0x00420234 /* Graphics observe clock */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY 0x00420238 /* Graphics power switch memory */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE            0x0042023c /* Disable HIF's clocks */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE             0x00420240 /* Hif clock enable */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE    0x00420244 /* Hif memory standby enable */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY      0x00420248 /* Hif power switch memory */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT          0x0042024c /* Mux selects for Internal clocks */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE       0x00420250 /* Memsys 16 clock enable */
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE 0x00420254 /* Memsys 16 memory standby enable */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK      0x00420258 /* Memsys 16 observe clock */
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY 0x0042025c /* Memsys 16 power switch memory */
+#define BCHP_CLKGEN_MEMSYS_16_STATUS             0x00420260 /* Memsys 16 status */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION   0x00420264 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION   0x00420268 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION   0x0042026c /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION   0x00420270 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE            0x00420274 /* Disable PAD's clocks */
+#define BCHP_CLKGEN_PAD_MUX_SELECT               0x00420278 /* Mux selects for Pad clocks */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS  0x0042027c /* PLL_AUDIO0 Reset Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS  0x00420280 /* PLL_AUDIO1 Reset Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS      0x00420284 /* PLL_SC Reset Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS    0x00420288 /* PLL_SYS1 Reset Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS    0x0042028c /* PLL_VCXO Reset Status */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL       0x00420290 /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL       0x00420294 /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x00420298 /* PLL Alive in Standby Mode */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE   0x0042029c /* Raaga dsp top clock enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE 0x004202a0 /* Raaga dsp top memory standby enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK  0x004202a4 /* Raaga dsp top observe clock */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY 0x004202a8 /* Raaga dsp top power switch memory */
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE         0x004202ac /* Rfm top clock enable */
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE 0x004202b0 /* Rfm top memory standby enable */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK        0x004202b4 /* Rfm top observe clock */
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY  0x004202b8 /* Rfm top power switch memory */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE       0x004202bc /* Sata3 top clock enable */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE      0x004202c0 /* Disable SATA3_TOP's clocks */
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE 0x004202c4 /* Sata3 memory standby enable */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK      0x004202c8 /* Sata3 top observe clock */
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL         0x004202cc /* Sata3 top PLL Ref Sel */
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY 0x004202d0 /* Sata3 top power switch memory */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE    0x004202d4 /* Sds afec top clock enable */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE 0x004202d8 /* Sds afec top memory standby enable */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK   0x004202dc /* Sds afec top observe clock */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY 0x004202e0 /* Sds afec top power switch memory */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE   0x004202e4 /* Disable SDS_RECEIVER's clocks */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE    0x004202e8 /* Sds receiver clock enable */
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE 0x004202ec /* Sds receiver memory standby enable */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK   0x004202f0 /* Sds receiver observe clock */
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY 0x004202f4 /* Sds receiver power switch memory */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE    0x004202f8 /* Sds tfec top clock enable */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE 0x004202fc /* Sds tfec top memory standby enable */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK   0x00420300 /* Sds tfec top observe clock */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY 0x00420304 /* Sds tfec top power switch memory */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE     0x00420308 /* Sectop inst clock enable */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE 0x0042030c /* Sectop inst memory standby enable */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK    0x00420310 /* Sectop inst observe clock */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT         0x00420314 /* Mux selects for Smartcard clocks */
+#define BCHP_CLKGEN_SPARE                        0x00420318 /* Spares */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK        0x0042031c /* Sys aon observe clock */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE       0x00420320 /* Disable SYS_CTRL's clocks */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE        0x00420324 /* Sys ctrl clock enable */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE 0x00420328 /* Sys ctrl memory standby enable */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK       0x0042032c /* Sys ctrl observe clock */
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY 0x00420330 /* Sys ctrl power switch memory */
+#define BCHP_CLKGEN_TESTPORT                     0x00420334 /* Special Testport Controls */
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE            0x00420338 /* Disable USB's clocks */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE             0x0042033c /* Usb clock enable */
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE    0x00420340 /* Usb memory standby enable */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK            0x00420344 /* Usb observe clock */
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY      0x00420348 /* Usb power switch memory */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE    0x0042034c /* Disable VEC_AIO_TOP's clocks */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE     0x00420350 /* Vec aio top clock enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A 0x00420354 /* Vec aio top memory standby enable a */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B 0x00420358 /* Vec aio top memory standby enable b */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK    0x0042035c /* Vec aio top observe clock */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A 0x00420360 /* Vec aio top power switch memory a */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B 0x00420364 /* Vec aio top power switch memory b */
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT                0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000001
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT                0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000001
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000005
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000a
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_SHIFT         0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_reserved0_MASK            0xffffe000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_reserved0_SHIFT           13
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_MASK                 0x00001c00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_SHIFT                10
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_DEFAULT              0x00000003
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_MASK             0x000003ff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_SHIFT            0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_DEFAULT          0x000000a7
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_reserved0_MASK           0xff000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_reserved0_SHIFT          24
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK   0x000000e0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT  5
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT   2
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK    0x00000002
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT   1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_MASK         0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_reserved0_MASK           0x80000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_reserved0_SHIFT          31
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_MASK             0x60000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_SHIFT            29
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_MASK             0x10000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_SHIFT            28
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_MASK         0x08000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_SHIFT        27
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_MASK         0x07000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_SHIFT        24
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__MASK         0x00800000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__SHIFT        23
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_MASK           0x00600000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_SHIFT          21
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_MASK           0x00100000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_SHIFT          20
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_MASK            0x000c0000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_SHIFT           18
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_MASK          0x00020000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_SHIFT         17
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_MASK         0x00010000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT        16
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_MASK         0x00008000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT        15
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_MASK           0x00004000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_SHIFT          14
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK     0x00001ffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT    1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT  0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_SHIFT             0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_SHIFT         0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_reserved0_MASK         0xfffff000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_reserved0_SHIFT        12
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_TEST_STATUS_MASK       0x00000fff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_TEST_STATUS_SHIFT      0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT  0x00000028
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT  0x00000028
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT  0x00000032
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_MASK                  0xffffe000
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_SHIFT                 13
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_MASK                       0x00001c00
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_SHIFT                      10
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_DEFAULT                    0x00000001
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_MASK                   0x000003ff
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_DEFAULT                0x00000040
+
+/***************************************************************************
+ *PLL_SC_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_MASK                 0xff000000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_SHIFT                24
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK         0x000000e0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT        5
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT      0x00000001
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_SHIFT              0
+
+/***************************************************************************
+ *PLL_SC_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_MASK                 0xc0000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_SHIFT                30
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_MASK                   0x30000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_SHIFT                  28
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_DEFAULT                0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_MASK              0x08000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_SHIFT             27
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_MASK                   0x04000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_SHIFT                  26
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_DEFAULT                0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_MASK               0x02000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_SHIFT              25
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_MASK               0x01c00000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_SHIFT              22
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__MASK               0x00200000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__SHIFT              21
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_MASK                 0x00180000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_SHIFT                19
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_MASK                 0x00040000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_SHIFT                18
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_MASK                  0x00030000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_SHIFT                 16
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_MASK               0x00008000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_SHIFT              15
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_MASK                 0x00004000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_SHIFT                14
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK    0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT   13
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_MASK           0x00001ffe
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_SHIFT          1
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_SHIFT               1
+
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_SHIFT               2
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_MASK                   0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_SHIFT                  1
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_DEFAULT                0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_DEFAULT                0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK  0x00400000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_MASK               0xfffff000
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_SHIFT              12
+
+/* CLKGEN :: PLL_SC_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_MASK             0x00000fff
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000c
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000c
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000060
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000036
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT                  0x00000002
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT              0x00000060
+
+/***************************************************************************
+ *PLL_SYS0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000002
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000012
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000005a
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x0000005a
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_DEFAULT                  0x00000003
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_DEFAULT              0x0000007d
+
+/***************************************************************************
+ *PLL_SYS1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000001
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_MASK                 0x30000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_SHIFT           27
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_DEFAULT              0x00000001
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_MASK             0x02000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_SHIFT            25
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_MASK             0x01c00000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_SHIFT            22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__MASK             0x00200000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__SHIFT            21
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_SHIFT              19
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_MASK                0x00030000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_SHIFT               16
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_DEFAULT             0x00000002
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000004b
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000004b
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x000000fa
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_DEFAULT                  0x00000002
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_DEFAULT              0x00000040
+
+/***************************************************************************
+ *PLL_VCXO_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_MASK               0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_SHIFT              20
+
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_MASK            0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_SHIFT           0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000001
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_MASK                 0x30000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_SHIFT                28
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_SHIFT           27
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_MASK             0x02000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_SHIFT            25
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_MASK             0x01c00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_SHIFT            22
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__MASK             0x00200000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__SHIFT            21
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_SHIFT              19
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_MASK                0x00030000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_SHIFT               16
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_SHIFT            15
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *AVD0_TOP_CLOCK_ENABLE - Avd0 top clock enable
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_reserved0_MASK           0xffffffe0
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_reserved0_SHIFT          5
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_SCB_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_CPU_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_AVD_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_ALTERNATE_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *AVD0_TOP_MEMORY_STANDBY_ENABLE - Avd0 top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: AVD0_TOP_MEMORY_STANDBY_ENABLE :: SVD_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AVD0_TOP_OBSERVE_CLOCK - Avd0 top observe clock
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AVD0_TOP_POWER_SWITCH_MEMORY - Avd0 top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: AVD0_TOP_POWER_SWITCH_MEMORY :: SVD_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_CLOCK_DISABLE - Disable BCM_MIPS_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_DISABLE :: DISABLE_MIPS_SYSTEM_216_CLOCK [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_DISABLE_MIPS_SYSTEM_216_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_DISABLE_MIPS_SYSTEM_216_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_DISABLE_MIPS_SYSTEM_216_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_CLOCK_ENABLE - Bcm mips top clock enable
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffff0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_SHIFT      4
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_MIPS_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_MIPS_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_MIPS_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_MIPS_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE - Bcm mips top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: MIPS_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_OBSERVE_CLOCK - Bcm mips top observe clock
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_POWER_SWITCH_MEMORY - Bcm mips top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: MIPS_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_SELECT - Bcm mips top select
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_SELECT :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_reserved0_SHIFT            1
+
+/* CLKGEN :: BCM_MIPS_TOP_SELECT :: MIPS_PLL_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_MIPS_PLL_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_MIPS_PLL_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_MIPS_PLL_CLOCK_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BVN_TOP_ENABLE - Bvn top enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_reserved0_MASK                  0xfffffff8
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_reserved0_SHIFT                 3
+
+/* CLKGEN :: BVN_TOP_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK       0x00000004
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT      2
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT    0x00000001
+
+/* CLKGEN :: BVN_TOP_ENABLE :: BVN_216_CLK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_MASK         0x00000002
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_SHIFT        1
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_DEFAULT      0x00000001
+
+/* CLKGEN :: BVN_TOP_ENABLE :: BVN_108_CLK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_MASK         0x00000001
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_SHIFT        0
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_DEFAULT      0x00000001
+
+/***************************************************************************
+ *BVN_TOP_MEMORY_STANDBY_ENABLE - Bvn top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: BVN_TOP_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BVN_TOP_POWER_SWITCH_MEMORY - Bvn top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: BVN_TOP_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 0 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION [31:28] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 28
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 1 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:28] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 28
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SATA_108_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 2 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:16] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 16
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 216 0 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:28] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 28
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SATA_216_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK - CKTAP CPU Adjustment System 108 Clock
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: reserved0 [31:08] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_reserved0_MASK 0xffffff00
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_reserved0_SHIFT 8
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: CKTAP_WAIT_COUNT [07:02] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_WAIT_COUNT_MASK 0x000000fc
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_WAIT_COUNT_SHIFT 2
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_WAIT_COUNT_DEFAULT 0x0000000f
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: CKTAP_UPDATE [01:01] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_MASK 0x00000002
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_SHIFT 1
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: CKTAP_REG_SELECT [00:00] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK - CKTAP CPU Adjustment System 216 Clock
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: CKTAP_UPDATE [01:01] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_MASK 0x00000002
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_SHIFT 1
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: CKTAP_REG_SELECT [00:00] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK - CKTAP CPU Adjustment System Scb Clock
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: CKTAP_UPDATE [01:01] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_MASK 0x00000002
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_SHIFT 1
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: CKTAP_REG_SELECT [00:00] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap scb 0 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [31:28] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 28
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap scb 1 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:16] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 16
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SATA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks
+ ***************************************************************************/
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT           2
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_OSC_DIGITAL_CLOCK [01:01] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_AVS_CLOCK [00:00] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_MASK    0x00000001
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_SHIFT   0
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CLOCK_MONITOR_CONTROL - Clock Monitor Control
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT          4
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK   0x00000008
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT  3
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK    0x00000004
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT   2
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK      0x00000002
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT     1
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT   0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK  0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT         1
+
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK     0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT    0
+
+/***************************************************************************
+ *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CORE_XPT_CLOCK_DISABLE - Disable CORE_XPT's clocks
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_SHIFT         5
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_CLOCK_ENABLE - Core xpt clock enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_MASK           0xfffffff8
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_SHIFT          3
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CORE_XPT_MEMORY_STANDBY_ENABLE - Core xpt memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_OBSERVE_CLOCK - Core xpt observe clock
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_POWER_SWITCH_MEMORY - Core xpt power switch memory
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_CLOCK_DISABLE - Disable DVP_HT's clocks
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_SHIFT           1
+
+/* CLKGEN :: DVP_HT_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_CLOCK_ENABLE - Dvp ht clock enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_MASK             0xfffffff0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_SHIFT            4
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_ALTERNATE_216_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_ALTERNATE_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DVP_HT_ENABLE - Dvp ht enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_ENABLE_reserved0_SHIFT                  1
+
+/* CLKGEN :: DVP_HT_ENABLE :: DVPHT_CLK_MAX_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_MASK        0x00000001
+#define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_SHIFT       0
+#define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_DEFAULT     0x00000001
+
+/***************************************************************************
+ *DVP_HT_MEMORY_STANDBY_ENABLE - Dvp ht memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_MASK    0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT   1
+
+/* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_OBSERVE_CLOCK - Dvp ht observe clock
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_MASK            0xffffffc0
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_SHIFT           6
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_POWER_SWITCH_MEMORY - Dvp ht power switch memory
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_SHIFT     2
+
+/* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FSK_TOP_CLOCK_ENABLE - Fsk top clock enable
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_reserved0_MASK            0xfffffff8
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_reserved0_SHIFT           3
+
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: FSK_PHY_PRIMARY_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_PHY_PRIMARY_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_PHY_PRIMARY_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_PHY_PRIMARY_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: FSK_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: FSK_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *FSK_TOP_MEMORY_STANDBY_ENABLE - Fsk top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: FSK_TOP_MEMORY_STANDBY_ENABLE :: FSK_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_FSK_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_FSK_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_FSK_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FSK_TOP_POWER_SWITCH_MEMORY - Fsk top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: FSK_TOP_POWER_SWITCH_MEMORY :: FTM_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_CLOCK_DISABLE - Disable GENET_TOP_RGMII_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_SHIFT 4
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET_ALWAYSON_CLOCK [03:03] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [02:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [01:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_FAST_CLOCK [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_CLOCK_ENABLE - Genet top rgmii inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: reserved0 [31:09] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_SHIFT 9
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [08:08] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00000100
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 8
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_108_CLOCK_ENABLE [07:07] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_MASK 0x00000080
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_SHIFT 7
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_L2INTR_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_HFB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_GMII_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_EEE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_CLK_250_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_CLOCK_SELECT - Genet top rgmii inst clock select
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_reserved0_SHIFT 2
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET0_GMII_CLOCK_SELECT [01:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_MASK 0x00000002
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_SHIFT 1
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET0_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A - Genet top rgmii inst memory standby enable a
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: GENET0_MEMORY_STANDBY_ENABLE_A [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_OBSERVE_CLOCK - Genet top rgmii inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A - Genet top rgmii inst power switch memory a
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A :: GENET0_POWER_SWITCH_MEMORY_A [01:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_MASK 0x00000003
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_CLOCK_DISABLE - Disable GRAPHICS's clocks
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_reserved0_SHIFT         1
+
+/* CLKGEN :: GRAPHICS_CLOCK_DISABLE :: DISABLE_GFX_M2MC_CORE_CLOCK [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_CLOCK_ENABLE - Graphics clock enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_reserved0_SHIFT          4
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_M2MC_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_ALTERNATE_108_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GRAPHICS_MEMORY_STANDBY_ENABLE - Graphics memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE :: GFX_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_OBSERVE_CLOCK - Graphics observe clock
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_POWER_SWITCH_MEMORY - Graphics power switch memory
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY :: GFX_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_CLOCK_DISABLE - Disable HIF's clocks
+ ***************************************************************************/
+/* CLKGEN :: HIF_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_reserved0_MASK               0xfffffff0
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_reserved0_SHIFT              4
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_SDIO_48_CLOCK [03:03] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_MASK   0x00000008
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_SHIFT  3
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [02:02] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK   0x00000004
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT  2
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_EBI_CLOCK [01:01] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_MASK   0x00000002
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_SHIFT  1
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_54_SCANCLOCK [00:00] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_SHIFT 0
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_CLOCK_ENABLE - Hif clock enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_reserved0_SHIFT               3
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_MASK     0x00000004
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_SHIFT    2
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_DEFAULT  0x00000001
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_MASK     0x00000002
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_SHIFT    1
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_DEFAULT  0x00000001
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_MASK     0x00000001
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_SHIFT    0
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_DEFAULT  0x00000001
+
+/***************************************************************************
+ *HIF_MEMORY_STANDBY_ENABLE - Hif memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE :: HIF_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_POWER_SWITCH_MEMORY - Hif power switch memory
+ ***************************************************************************/
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_reserved0_SHIFT        2
+
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY :: HIF_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
+ ***************************************************************************/
+/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK             0xfffffff8
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT            3
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [02:02] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [01:01] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: GFX_M2MC_CORE_CLOCK [00:00] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_MASK   0x00000001
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_SHIFT  0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_16_CLOCK_ENABLE - Memsys 16 clock enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: DDR1_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: DDR1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *MEMSYS_16_MEMORY_STANDBY_ENABLE - Memsys 16 memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MEMSYS_16_MEMORY_STANDBY_ENABLE :: DDR1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_16_OBSERVE_CLOCK - Memsys 16 observe clock
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_16_POWER_SWITCH_MEMORY - Memsys 16 power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: MEMSYS_16_POWER_SWITCH_MEMORY :: DDR1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_16_STATUS - Memsys 16 status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_reserved0_SHIFT               1
+
+/* CLKGEN :: MEMSYS_16_STATUS :: MEMSYS_PLL_LOCKED_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_MEMSYS_PLL_LOCKED_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_MEMSYS_PLL_LOCKED_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PAD_CLK_OBSRV0_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLK_OBSRV1_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLK_OBSRV2_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLK_OBSRV3_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLOCK_DISABLE - Disable PAD's clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK               0xfffffff8
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT              3
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_SC_OUT_CLOCK [02:02] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_MASK    0x00000004
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_SHIFT   2
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_MUX_SELECT - Mux selects for Pad clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK                  0xfffffff8
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT                 3
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK27_CLOCK [02:00] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_MASK     0x00000007
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_SHIFT    0
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_DEFAULT  0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET_STATUS - PLL_AUDIO0 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET_STATUS - PLL_AUDIO1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET_STATUS - PLL_SC Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET_STATUS - PLL_SYS1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET_STATUS - PLL_VCXO Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PM_CLOCK_108_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_MASK          0xfffffff0
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_SHIFT         4
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSTFEC [03:03] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTFEC_MASK 0x00000008
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTFEC_SHIFT 3
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTFEC_DEFAULT 0x00000000
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSRCVR [02:02] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSRCVR_MASK 0x00000004
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSRCVR_SHIFT 2
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSRCVR_DEFAULT 0x00000000
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSAFEC [01:01] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC_MASK 0x00000002
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC_SHIFT 1
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC_DEFAULT 0x00000000
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_ [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG__MASK      0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG__SHIFT     0
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG__DEFAULT   0x00000000
+
+/***************************************************************************
+ *PM_CLOCK_216_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_SHIFT         1
+
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_MASK   0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT  0
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               3
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys_PLL [02:02] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_MASK               0x00000004
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_SHIFT              2
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_DEFAULT            0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [01:01] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK                 0x00000002
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT                1
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT              0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_AVD_MIPS [00:00] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_MASK             0x00000001
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_SHIFT            0
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_CLOCK_ENABLE - Raaga dsp top clock enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_reserved0_MASK      0xfffffff8
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_reserved0_SHIFT     3
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_DSP_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE - Raaga dsp top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE :: RAAGAA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_OBSERVE_CLOCK - Raaga dsp top observe clock
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_reserved0_SHIFT    2
+
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: RAAGA_ENABLE_OBSERVE_CLOCK [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_POWER_SWITCH_MEMORY - Raaga dsp top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_POWER_SWITCH_MEMORY :: RAAGA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RFM_TOP_CLOCK_ENABLE - Rfm top clock enable
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_reserved0_SHIFT           1
+
+/* CLKGEN :: RFM_TOP_CLOCK_ENABLE :: RFM_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RFM_TOP_MEMORY_STANDBY_ENABLE - Rfm top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: RFM_TOP_MEMORY_STANDBY_ENABLE :: RFMA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RFM_TOP_OBSERVE_CLOCK - Rfm top observe clock
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_reserved0_MASK           0xffffffc0
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_reserved0_SHIFT          6
+
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RFM_TOP_POWER_SWITCH_MEMORY - Rfm top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: RFM_TOP_POWER_SWITCH_MEMORY :: RFM_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_CLOCK_ENABLE - Sata3 top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: SATA_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: SATA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SATA3_TOP_CLOCK_DISABLE - Disable SATA3_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_reserved0_SHIFT        1
+
+/* CLKGEN :: SATA3_TOP_CLOCK_DISABLE :: DISABLE_SATA_FUNC_30_CLOCK [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_FUNC_30_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_FUNC_30_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_FUNC_30_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_MEMORY_STANDBY_ENABLE - Sata3 memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SATA3_TOP_MEMORY_STANDBY_ENABLE :: SATA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_OBSERVE_CLOCK - Sata3 top observe clock
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: SATA_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: SATA_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: SATA_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_PLLREF_SEL - Sata3 top PLL Ref Sel
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_PLLREF_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_reserved0_SHIFT           1
+
+/* CLKGEN :: SATA3_TOP_PLLREF_SEL :: SATA_TOP_PLLREF_SEL [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_SATA_TOP_PLLREF_SEL_MASK  0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_SATA_TOP_PLLREF_SEL_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_SATA_TOP_PLLREF_SEL_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SATA3_TOP_POWER_SWITCH_MEMORY - Sata3 top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: SATA3_TOP_POWER_SWITCH_MEMORY :: SATA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_AFEC_TOP_CLOCK_ENABLE - Sds afec top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: SDS_AFEC_TOP_CLOCK_ENABLE :: SDSAFEC0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE - Sds afec top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE :: SDSAFEC0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_AFEC_TOP_OBSERVE_CLOCK - Sds afec top observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: SDSAFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_AFEC_TOP_POWER_SWITCH_MEMORY - Sds afec top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS_AFEC_TOP_POWER_SWITCH_MEMORY :: SDSAFEC0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_RECEIVER_CLOCK_DISABLE - Disable SDS_RECEIVER's clocks
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: SDS_RECEIVER_CLOCK_DISABLE :: DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK [00:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_RECEIVER_CLOCK_ENABLE - Sds receiver clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: SDS_RECEIVER_CLOCK_ENABLE :: SDSRCVR0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_SDSRCVR0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_SDSRCVR0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_SDSRCVR0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SDS_RECEIVER_MEMORY_STANDBY_ENABLE - Sds receiver memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS_RECEIVER_MEMORY_STANDBY_ENABLE :: SDSRCVR0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_SDSRCVR0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_SDSRCVR0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_SDSRCVR0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_RECEIVER_OBSERVE_CLOCK - Sds receiver observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: SDSRCVR0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: SDSRCVR0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_RECEIVER_POWER_SWITCH_MEMORY - Sds receiver power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS_RECEIVER_POWER_SWITCH_MEMORY :: SDSRCVR0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_SDSRCVR0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_SDSRCVR0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_SDSRCVR0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_TFEC_TOP_CLOCK_ENABLE - Sds tfec top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: SDS_TFEC_TOP_CLOCK_ENABLE :: SDSTFEC0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_SDSTFEC0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_SDSTFEC0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_SDSTFEC0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE - Sds tfec top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE :: SDS_TFEC0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_SDS_TFEC0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_SDS_TFEC0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_SDS_TFEC0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_TFEC_TOP_OBSERVE_CLOCK - Sds tfec top observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: SDS_TFEC0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: SDS_TFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_TFEC_TOP_POWER_SWITCH_MEMORY - Sds tfec top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS_TFEC_TOP_POWER_SWITCH_MEMORY :: SDS_TFEC0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_SDS_TFEC0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_SDS_TFEC0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_SDS_TFEC0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SECTOP_INST_CLOCK_ENABLE - Sectop inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_SHIFT       1
+
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: SEC_ALTERNATE_SCB_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SECTOP_INST_MEMORY_STANDBY_ENABLE - Sectop inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SECTOP_INST_MEMORY_STANDBY_ENABLE :: SEC_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
+ ***************************************************************************/
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:11] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK            0xfffff800
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT           11
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC_OUT_CLOCK [10:08] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_MASK         0x00000700
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_SHIFT        8
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_DEFAULT      0x00000000
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [07:05] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK            0x000000e0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT           5
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [04:02] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK            0x0000001c
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT           2
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: PLLSC_REFERENCE_CLOCK [01:00] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_MASK 0x00000003
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE - Spares
+ ***************************************************************************/
+/* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK                     0xfffff000
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT                    12
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT                  0x00000000
+
+/* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK                    0x00000fff
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT                   0
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *SYS_AON_OBSERVE_CLOCK - Sys aon observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_MASK           0xffffffc0
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_SHIFT          6
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_CLOCK_DISABLE - Disable SYS_CTRL's clocks
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_SHIFT         5
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK [03:03] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK [02:02] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK_SHIFT 2
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK  0x00000002
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK  0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_CLOCK_ENABLE - Sys ctrl clock enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_SHIFT          1
+
+/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: SYS_CTRL_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SYS_CTRL_MEMORY_STANDBY_ENABLE - Sys ctrl memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_OBSERVE_CLOCK - Sys ctrl observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_POWER_SWITCH_MEMORY - Sys ctrl power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: SYS_CTRL_POWER_SWITCH_MEMORY :: SYS_CTRL_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TESTPORT - Special Testport Controls
+ ***************************************************************************/
+/* CLKGEN :: TESTPORT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_TESTPORT_reserved0_MASK                        0xfffffff8
+#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT                       3
+
+/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [02:00] */
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK           0x00000007
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT          0
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *USB_CLOCK_DISABLE - Disable USB's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_reserved0_SHIFT              1
+
+/* CLKGEN :: USB_CLOCK_DISABLE :: DISABLE_USB_54_MDIO_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB_CLOCK_ENABLE - Usb clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_reserved0_SHIFT               2
+
+/* CLKGEN :: USB_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK    0x00000002
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT   1
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: USB_CLOCK_ENABLE :: USB0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK    0x00000001
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT   0
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *USB_MEMORY_STANDBY_ENABLE - Usb memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: USB_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB_OBSERVE_CLOCK - Usb observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_reserved0_MASK               0xffffffc0
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_reserved0_SHIFT              6
+
+/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB_POWER_SWITCH_MEMORY - Usb power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_reserved0_SHIFT        2
+
+/* CLKGEN :: USB_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_CLOCK_DISABLE - Disable VEC_AIO_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_CLOCK_ENABLE - Vec aio top clock enable
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: reserved0 [31:07] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_reserved0_MASK        0xffffff80
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_reserved0_SHIFT       7
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_SCB_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_SCB_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_216_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_108_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE2_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A - Vec aio top memory standby enable a
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A :: VEC_MEMORY_STANDBY_ENABLE_A [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B - Vec aio top memory standby enable b
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B :: AIO_MEMORY_STANDBY_ENABLE_B [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_OBSERVE_CLOCK - Vec aio top observe clock
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_POWER_SWITCH_MEMORY_A - Vec aio top power switch memory a
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_A :: VEC_POWER_SWITCH_MEMORY_A [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_POWER_SWITCH_MEMORY_B - Vec aio top power switch memory b
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_B :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_B :: AIO_POWER_SWITCH_MEMORY_B [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_CLKGEN_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_common.h b/include/linux/brcmstb/7360a0/bchp_common.h
new file mode 100644
index 0000000..a4d4a73
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_common.h
@@ -0,0 +1,1969 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Apr 23 03:10:04 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_COMMON_H__
+#define BCHP_COMMON_H__
+
+/***************************************************************************
+ *BCM7360_A0
+ ***************************************************************************/
+#define BCHP_PHYSICAL_OFFSET                               0x10000000
+#define BCHP_REGISTER_START                                0x00000000 /* DECODE_RBNODE_REGS_0 is first */
+#define BCHP_REGISTER_END                                  0x00b01010 /* RFM_GRB is last */
+#define BCHP_REGISTER_SIZE                                 0x002c0404 /* Number of registers */
+
+/****************************************************************************
+ * Core instance register start address.
+ ***************************************************************************/
+#define BCHP_DECODE_RBNODE_REGS_0_REG_START                0x00000000
+#define BCHP_DECODE_RBNODE_REGS_0_REG_END                  0x0000007c
+#define BCHP_DECODE_MAIN_0_REG_START                       0x00000100
+#define BCHP_DECODE_MAIN_0_REG_END                         0x000001fc
+#define BCHP_SDRAM_DEBUG_0_REG_START                       0x00000200
+#define BCHP_SDRAM_DEBUG_0_REG_END                         0x0000027c
+#define BCHP_DECODE_MCOM_0_REG_START                       0x00000300
+#define BCHP_DECODE_MCOM_0_REG_END                         0x0000031c
+#define BCHP_DECODE_SPRE_0_REG_START                       0x00000320
+#define BCHP_DECODE_SPRE_0_REG_END                         0x0000033c
+#define BCHP_DECODE_WPRD_0_REG_START                       0x00000340
+#define BCHP_DECODE_WPRD_0_REG_END                         0x0000035c
+#define BCHP_DECODE_DQNT_0_REG_START                       0x00000400
+#define BCHP_DECODE_DQNT_0_REG_END                         0x0000045c
+#define BCHP_DECODE_DQNT_8X8_0_REG_START                   0x00000500
+#define BCHP_DECODE_DQNT_8X8_0_REG_END                     0x0000057c
+#define BCHP_DECODE_VP8_XFRM_0_REG_START                   0x00000600
+#define BCHP_DECODE_VP8_XFRM_0_REG_END                     0x0000060c
+#define BCHP_DECODE_XFRM_0_REG_START                       0x00000700
+#define BCHP_DECODE_XFRM_0_REG_END                         0x0000071c
+#define BCHP_DECODE_DBLK_0_REG_START                       0x00000720
+#define BCHP_DECODE_DBLK_0_REG_END                         0x0000073c
+#define BCHP_DECODE_MB_0_REG_START                         0x00000740
+#define BCHP_DECODE_MB_0_REG_END                           0x0000075c
+#define BCHP_REG_CABAC2BINS_0_REG_START                    0x00000b00
+#define BCHP_REG_CABAC2BINS_0_REG_END                      0x00000bfc
+#define BCHP_DECODE_SINT_0_REG_START                       0x00000c00
+#define BCHP_DECODE_SINT_0_REG_END                         0x00000dfc
+#define BCHP_DECODE_RVC_0_REG_START                        0x00000e00
+#define BCHP_DECODE_RVC_0_REG_END                          0x00000efc
+#define BCHP_DECODE_CPUREGS_0_REG_START                    0x00000f00
+#define BCHP_DECODE_CPUREGS_0_REG_END                      0x00000f7c
+#define BCHP_DECODE_CPUREGS2_0_REG_START                   0x00000f80
+#define BCHP_DECODE_CPUREGS2_0_REG_END                     0x00000ffc
+#define BCHP_DECODE_CPUDMA_0_REG_START                     0x00001800
+#define BCHP_DECODE_CPUDMA_0_REG_END                       0x000018fc
+#define BCHP_DECODE_DMAMEM_0_REG_START                     0x00001a00
+#define BCHP_DECODE_DMAMEM_0_REG_END                       0x000021fc
+#define BCHP_REG_CABAC2BINS2_0_REG_START                   0x00002400
+#define BCHP_REG_CABAC2BINS2_0_REG_END                     0x000027fc
+#define BCHP_DECODE_WPTBL_0_REG_START                      0x00003000
+#define BCHP_DECODE_WPTBL_0_REG_END                        0x000031fc
+#define BCHP_DECODE_SINT_OLOOP_0_REG_START                 0x0000cc00
+#define BCHP_DECODE_SINT_OLOOP_0_REG_END                   0x0000ccfc
+#define BCHP_DECODE_SD_0_REG_START                         0x00040800
+#define BCHP_DECODE_SD_0_REG_END                           0x00040ffc
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_START             0x00041000
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_END               0x0004107c
+#define BCHP_DECODE_CPUCORE_0_REG_START                    0x00044000
+#define BCHP_DECODE_CPUCORE_0_REG_END                      0x00044ffc
+#define BCHP_DECODE_CPUAUX_0_REG_START                     0x00045000
+#define BCHP_DECODE_CPUAUX_0_REG_END                       0x00045ffc
+#define BCHP_DECODE_CPUIMEM_0_REG_START                    0x00046000
+#define BCHP_DECODE_CPUIMEM_0_REG_END                      0x00047ffc
+#define BCHP_DECODE_CPUDMEM_0_REG_START                    0x00048000
+#define BCHP_DECODE_CPUDMEM_0_REG_END                      0x0004fffc
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_START            0x00051000
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_END              0x0005107c
+#define BCHP_DECODE_CPUDMA2_0_REG_START                    0x00051800
+#define BCHP_DECODE_CPUDMA2_0_REG_END                      0x000518fc
+#define BCHP_DECODE_DMAMEM2_0_REG_START                    0x00051a00
+#define BCHP_DECODE_DMAMEM2_0_REG_END                      0x000521fc
+#define BCHP_DECODE_CPUCORE2_0_REG_START                   0x00054000
+#define BCHP_DECODE_CPUCORE2_0_REG_END                     0x00054ffc
+#define BCHP_DECODE_CPUAUX2_0_REG_START                    0x00055000
+#define BCHP_DECODE_CPUAUX2_0_REG_END                      0x00055ffc
+#define BCHP_DECODE_CPUIMEM2_0_REG_START                   0x00056000
+#define BCHP_DECODE_CPUIMEM2_0_REG_END                     0x00057ffc
+#define BCHP_DECODE_CPUDMEM2_0_REG_START                   0x00058000
+#define BCHP_DECODE_CPUDMEM2_0_REG_END                     0x0005fffc
+#define BCHP_DECODE_IP_SHIM_0_REG_START                    0x00060000
+#define BCHP_DECODE_IP_SHIM_0_REG_END                      0x00060084
+#define BCHP_AVD_CACHE_0_REG_START                         0x00062000
+#define BCHP_AVD_CACHE_0_REG_END                           0x0006203c
+#define BCHP_AVD_INTR2_0_REG_START                         0x00080000
+#define BCHP_AVD_INTR2_0_REG_END                           0x0008002c
+#define BCHP_AVD_RGR_0_REG_START                           0x00080400
+#define BCHP_AVD_RGR_0_REG_END                             0x00080410
+#define BCHP_VICH_0_REG_START                              0x00170000
+#define BCHP_VICH_0_REG_END                                0x0017008b
+#define BCHP_SATA_GRB_REG_START                            0x00180000
+#define BCHP_SATA_GRB_REG_END                              0x0018000c
+#define BCHP_SATA_TOP_CTRL_REG_START                       0x00180020
+#define BCHP_SATA_TOP_CTRL_REG_END                         0x00180038
+#define BCHP_SATA3_INTR2_REG_START                         0x00180080
+#define BCHP_SATA3_INTR2_REG_END                           0x001800ac
+#define BCHP_SATA_AHCI_GHC_REG_START                       0x00181000
+#define BCHP_SATA_AHCI_GHC_REG_END                         0x00181028
+#define BCHP_SATA_GLOBAL_RESERVED_REG_START                0x0018102c
+#define BCHP_SATA_GLOBAL_RESERVED_REG_END                  0x0018109c
+#define BCHP_SATA_PORT0_AHCI_S1_REG_START                  0x00181100
+#define BCHP_SATA_PORT0_AHCI_S1_REG_END                    0x0018111c
+#define BCHP_SATA_PORT0_AHCI_S2_REG_START                  0x00181120
+#define BCHP_SATA_PORT0_AHCI_S2_REG_END                    0x00181134
+#define BCHP_SATA_PORT0_AHCI_S3_REG_START                  0x00181138
+#define BCHP_SATA_PORT0_AHCI_S3_REG_END                    0x0018117c
+#define BCHP_SATA_PORT1_AHCI_S1_REG_START                  0x00181180
+#define BCHP_SATA_PORT1_AHCI_S1_REG_END                    0x0018119c
+#define BCHP_SATA_PORT1_AHCI_S2_REG_START                  0x001811a0
+#define BCHP_SATA_PORT1_AHCI_S2_REG_END                    0x001811b4
+#define BCHP_SATA_PORT1_AHCI_S3_REG_START                  0x001811b8
+#define BCHP_SATA_PORT1_AHCI_S3_REG_END                    0x001811fc
+#define BCHP_SATA_AHCI_PCICFG_REG_START                    0x00181600
+#define BCHP_SATA_AHCI_PCICFG_REG_END                      0x00181664
+#define BCHP_SATA_PORT0_CTRL_REG_START                     0x00181700
+#define BCHP_SATA_PORT0_CTRL_REG_END                       0x00181730
+#define BCHP_SATA_PORT0_CJPAT_REG_START                    0x00181740
+#define BCHP_SATA_PORT0_CJPAT_REG_END                      0x00181764
+#define BCHP_SATA_PORT1_CTRL_REG_START                     0x00181780
+#define BCHP_SATA_PORT1_CTRL_REG_END                       0x001817b0
+#define BCHP_SATA_PORT1_CJPAT_REG_START                    0x001817c0
+#define BCHP_SATA_PORT1_CJPAT_REG_END                      0x001817e4
+#define BCHP_SATA_LEG_PCICFG_REG_START                     0x00181800
+#define BCHP_SATA_LEG_PCICFG_REG_END                       0x00181880
+#define BCHP_SATA_PORT0_LEG_S1_REG_START                   0x00181900
+#define BCHP_SATA_PORT0_LEG_S1_REG_END                     0x00181934
+#define BCHP_SATA_PORT0_LEG_S2_REG_START                   0x00181940
+#define BCHP_SATA_PORT0_LEG_S2_REG_END                     0x00181954
+#define BCHP_SATA_PORT0_LEG_S3_REG_START                   0x00181958
+#define BCHP_SATA_PORT0_LEG_S3_REG_END                     0x00181998
+#define BCHP_SATA_PORT1_LEG_S1_REG_START                   0x00181a00
+#define BCHP_SATA_PORT1_LEG_S1_REG_END                     0x00181a34
+#define BCHP_SATA_PORT1_LEG_S2_REG_START                   0x00181a40
+#define BCHP_SATA_PORT1_LEG_S2_REG_END                     0x00181a54
+#define BCHP_SATA_PORT1_LEG_S3_REG_START                   0x00181a58
+#define BCHP_SATA_PORT1_LEG_S3_REG_END                     0x00181a98
+#define BCHP_BESTROM_REG_START                             0x00200000
+#define BCHP_BESTROM_REG_END                               0x00203ffc
+#define BCHP_BSP_CMDBUF_REG_START                          0x00329800
+#define BCHP_BSP_CMDBUF_REG_END                            0x00329ffc
+#define BCHP_BSP_GLB_CONTROL_REG_START                     0x0032b000
+#define BCHP_BSP_GLB_CONTROL_REG_END                       0x0032b098
+#define BCHP_BSP_PKL_REG_START                             0x0032b300
+#define BCHP_BSP_PKL_REG_END                               0x0032b37c
+#define BCHP_BSP_INST_PATCH_CTRL_REG_START                 0x0032b400
+#define BCHP_BSP_INST_PATCH_CTRL_REG_END                   0x0032b404
+#define BCHP_BSP_CONTROL_INTR2_REG_START                   0x0032b800
+#define BCHP_BSP_CONTROL_INTR2_REG_END                     0x0032b82c
+#define BCHP_BSP_INST_PATCHRAM_REG_START                   0x0032c000
+#define BCHP_BSP_INST_PATCHRAM_REG_END                     0x0032fffc
+#define BCHP_XPT_SECURITY_REG_START                        0x00360000
+#define BCHP_XPT_SECURITY_REG_END                          0x0036fffc
+#define BCHP_MMSCRAM_REG_START                             0x00370000
+#define BCHP_MMSCRAM_REG_END                               0x00371ffc
+#define BCHP_MEM_DMA_SECURE_REG_START                      0x00372000
+#define BCHP_MEM_DMA_SECURE_REG_END                        0x0037200c
+#define BCHP_SECTOP_GRB_REG_START                          0x00374000
+#define BCHP_SECTOP_GRB_REG_END                            0x0037400c
+#define BCHP_JTAG_OTP_REG_START                            0x00374100
+#define BCHP_JTAG_OTP_REG_END                              0x00374138
+#define BCHP_MEM_DMA_0_REG_START                           0x00374200
+#define BCHP_MEM_DMA_0_REG_END                             0x00374224
+#define BCHP_XPT_SECURITY_NS_REG_START                     0x00374300
+#define BCHP_XPT_SECURITY_NS_REG_END                       0x00374310
+#define BCHP_MEMC_GEN_0_REG_START                          0x003b0000
+#define BCHP_MEMC_GEN_0_REG_END                            0x003b04f8
+#define BCHP_MEMC_GEN_2_0_REG_START                        0x003b0600
+#define BCHP_MEMC_GEN_2_0_REG_END                          0x003b06ec
+#define BCHP_MEMC_ARB_0_REG_START                          0x003b1000
+#define BCHP_MEMC_ARB_0_REG_END                            0x003b1244
+#define BCHP_MEMC_DDR_0_REG_START                          0x003b2000
+#define BCHP_MEMC_DDR_0_REG_END                            0x003b22fc
+#define BCHP_MEMC_L2_0_REG_START                           0x003b3000
+#define BCHP_MEMC_L2_0_REG_END                             0x003b302c
+#define BCHP_MEMC_L2_1_0_REG_START                         0x003b3800
+#define BCHP_MEMC_L2_1_0_REG_END                           0x003b382c
+#define BCHP_MEMC_RGRB_0_REG_START                         0x003b4000
+#define BCHP_MEMC_RGRB_0_REG_END                           0x003b4010
+#define BCHP_MEMC_MISC_0_REG_START                         0x003b5000
+#define BCHP_MEMC_MISC_0_REG_END                           0x003b5010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_START            0x003b6000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_END              0x003b60c4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_START             0x003b6200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_END               0x003b63b0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_START         0x003b8000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_END           0x003b8138
+#define BCHP_S_MEMC_0_REG_START                            0x003ba000
+#define BCHP_S_MEMC_0_REG_END                              0x003ba220
+#define BCHP_SUN_GISB_ARB_REG_START                        0x00400000
+#define BCHP_SUN_GISB_ARB_REG_END                          0x004000d8
+#define BCHP_SUN_RGR_REG_START                             0x00400400
+#define BCHP_SUN_RGR_REG_END                               0x00400410
+#define BCHP_SUN_RG_REG_START                              0x00400800
+#define BCHP_SUN_RG_REG_END                                0x0040080c
+#define BCHP_SUN_L2_REG_START                              0x00403000
+#define BCHP_SUN_L2_REG_END                                0x0040302c
+#define BCHP_SM_L2_REG_START                               0x00403400
+#define BCHP_SM_L2_REG_END                                 0x0040342c
+#define BCHP_SM_REG_START                                  0x00403800
+#define BCHP_SM_REG_END                                    0x00403824
+#define BCHP_SM_FAST_REG_START                             0x00403c00
+#define BCHP_SM_FAST_REG_END                               0x00403c18
+#define BCHP_SUN_TOP_CTRL_REG_START                        0x00404000
+#define BCHP_SUN_TOP_CTRL_REG_END                          0x00404518
+#define BCHP_IRB_REG_START                                 0x00406000
+#define BCHP_IRB_REG_END                                   0x00406138
+#define BCHP_PM_REG_START                                  0x00406180
+#define BCHP_PM_REG_END                                    0x00406188
+#define BCHP_BSCA_REG_START                                0x00406200
+#define BCHP_BSCA_REG_END                                  0x00406254
+#define BCHP_BSCB_REG_START                                0x00406280
+#define BCHP_BSCB_REG_END                                  0x004062d4
+#define BCHP_BSCC_REG_START                                0x00406300
+#define BCHP_BSCC_REG_END                                  0x00406354
+#define BCHP_PWM_REG_START                                 0x00406400
+#define BCHP_PWM_REG_END                                   0x00406424
+#define BCHP_GIO_REG_START                                 0x00406500
+#define BCHP_GIO_REG_END                                   0x0040659c
+#define BCHP_IRQ0_REG_START                                0x00406600
+#define BCHP_IRQ0_REG_END                                  0x00406604
+#define BCHP_IRQ1_REG_START                                0x00406640
+#define BCHP_IRQ1_REG_END                                  0x00406644
+#define BCHP_TIMER_REG_START                               0x00406680
+#define BCHP_TIMER_REG_END                                 0x004066bc
+#define BCHP_UARTA_REG_START                               0x00406800
+#define BCHP_UARTA_REG_END                                 0x0040681c
+#define BCHP_UARTB_REG_START                               0x00406840
+#define BCHP_UARTB_REG_END                                 0x0040685c
+#define BCHP_UARTC_REG_START                               0x00406880
+#define BCHP_UARTC_REG_END                                 0x0040689c
+#define BCHP_SCA_REG_START                                 0x00406a00
+#define BCHP_SCA_REG_END                                   0x00406abc
+#define BCHP_SCB_REG_START                                 0x00406b00
+#define BCHP_SCB_REG_END                                   0x00406bbc
+#define BCHP_SCIRQ0_REG_START                              0x00406c00
+#define BCHP_SCIRQ0_REG_END                                0x00406c04
+#define BCHP_SCIRQ1_REG_START                              0x00406c80
+#define BCHP_SCIRQ1_REG_END                                0x00406c84
+#define BCHP_AON_CTRL_REG_START                            0x00408000
+#define BCHP_AON_CTRL_REG_END                              0x004083fc
+#define BCHP_AON_L2_REG_START                              0x00408400
+#define BCHP_AON_L2_REG_END                                0x0040842c
+#define BCHP_AON_PM_L2_REG_START                           0x00408440
+#define BCHP_AON_PM_L2_REG_END                             0x0040846c
+#define BCHP_AON_PIN_CTRL_REG_START                        0x00408500
+#define BCHP_AON_PIN_CTRL_REG_END                          0x0040851c
+#define BCHP_AON_HDMI_TX_REG_START                         0x00408600
+#define BCHP_AON_HDMI_TX_REG_END                           0x00408698
+#define BCHP_LDK_REG_START                                 0x00408800
+#define BCHP_LDK_REG_END                                   0x0040883c
+#define BCHP_PM_AON_REG_START                              0x00408840
+#define BCHP_PM_AON_REG_END                                0x00408848
+#define BCHP_ICAP_REG_START                                0x00408880
+#define BCHP_ICAP_REG_END                                  0x004088bc
+#define BCHP_KBD1_REG_START                                0x004088c0
+#define BCHP_KBD1_REG_END                                  0x004088fc
+#define BCHP_KBD2_REG_START                                0x00408900
+#define BCHP_KBD2_REG_END                                  0x0040893c
+#define BCHP_KBD3_REG_START                                0x00408940
+#define BCHP_KBD3_REG_END                                  0x0040897c
+#define BCHP_BSCD_REG_START                                0x00408980
+#define BCHP_BSCD_REG_END                                  0x004089d4
+#define BCHP_MSPI_REG_START                                0x00408a00
+#define BCHP_MSPI_REG_END                                  0x00408b7c
+#define BCHP_IRQ0_AON_REG_START                            0x00408b80
+#define BCHP_IRQ0_AON_REG_END                              0x00408b84
+#define BCHP_IRQ1_AON_REG_START                            0x00408b88
+#define BCHP_IRQ1_AON_REG_END                              0x00408b8c
+#define BCHP_GIO_AON_REG_START                             0x00408c00
+#define BCHP_GIO_AON_REG_END                               0x00408c5c
+#define BCHP_BICAP_REG_START                               0x00408e00
+#define BCHP_BICAP_REG_END                                 0x00408e38
+#define BCHP_UPG_AUX_AON_INTR2_REG_START                   0x00408e40
+#define BCHP_UPG_AUX_AON_INTR2_REG_END                     0x00408e6c
+#define BCHP_WKTMR_REG_START                               0x00408e80
+#define BCHP_WKTMR_REG_END                                 0x00408e90
+#define BCHP_SYS_GISB_ARB_SEC_REG_START                    0x0040e000
+#define BCHP_SYS_GISB_ARB_SEC_REG_END                      0x0040e0b4
+#define BCHP_SYS_TOP_CTRL_SEC_REG_START                    0x0040e700
+#define BCHP_SYS_TOP_CTRL_SEC_REG_END                      0x0040e704
+#define BCHP_AON_CTRL_SECURE_REG_START                     0x0040e800
+#define BCHP_AON_CTRL_SECURE_REG_END                       0x0040e87c
+#define BCHP_SDIO_0_HOST_REG_START                         0x00410000
+#define BCHP_SDIO_0_HOST_REG_END                           0x004100fc
+#define BCHP_SDIO_0_CFG_REG_START                          0x00410100
+#define BCHP_SDIO_0_CFG_REG_END                            0x004101fc
+#define BCHP_MISB_BRIDGE_REG_START                         0x00410400
+#define BCHP_MISB_BRIDGE_REG_END                           0x00410410
+#define BCHP_EBI_REG_START                                 0x00410800
+#define BCHP_EBI_REG_END                                   0x00410bfc
+#define BCHP_HIF_INTR2_REG_START                           0x00411000
+#define BCHP_HIF_INTR2_REG_END                             0x0041102c
+#define BCHP_IPI0_INTR2_REG_START                          0x00411100
+#define BCHP_IPI0_INTR2_REG_END                            0x0041112c
+#define BCHP_IPI1_INTR2_REG_START                          0x00411200
+#define BCHP_IPI1_INTR2_REG_END                            0x0041122c
+#define BCHP_HIF_CPU_INTR1_REG_START                       0x00411400
+#define BCHP_HIF_CPU_INTR1_REG_END                         0x0041142c
+#define BCHP_HIF_RGR_REG_START                             0x00411800
+#define BCHP_HIF_RGR_REG_END                               0x00411810
+#define BCHP_HIF_SPI_INTR2_REG_START                       0x00411d00
+#define BCHP_HIF_SPI_INTR2_REG_END                         0x00411d2c
+#define BCHP_HIF_TOP_CTRL_REG_START                        0x00412400
+#define BCHP_HIF_TOP_CTRL_REG_END                          0x0041241c
+#define BCHP_NAND_REG_START                                0x00412800
+#define BCHP_NAND_REG_END                                  0x00412bfc
+#define BCHP_BSPI_REG_START                                0x00413000
+#define BCHP_BSPI_REG_END                                  0x0041304c
+#define BCHP_BSPI_RAF_REG_START                            0x00413100
+#define BCHP_BSPI_RAF_REG_END                              0x00413120
+#define BCHP_HIF_MSPI_REG_START                            0x00413200
+#define BCHP_HIF_MSPI_REG_END                              0x00413384
+#define BCHP_MICH_REG_START                                0x00414000
+#define BCHP_MICH_REG_END                                  0x00414000
+#define BCHP_HIF_SECURE_CTRL_REG_START                     0x00414100
+#define BCHP_HIF_SECURE_CTRL_REG_END                       0x00414100
+#define BCHP_HIF_SECURE_BSPI_REG_START                     0x00414200
+#define BCHP_HIF_SECURE_BSPI_REG_END                       0x00414200
+#define BCHP_HIF_SECURE_LR_SPI_REG_START                   0x00414300
+#define BCHP_HIF_SECURE_LR_SPI_REG_END                     0x00414300
+#define BCHP_NAND_SECURE_REG_START                         0x00414400
+#define BCHP_NAND_SECURE_REG_END                           0x00414400
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_START        0x00414800
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_END          0x00414800
+#define BCHP_CLKGEN_REG_START                              0x00420000
+#define BCHP_CLKGEN_REG_END                                0x00420364
+#define BCHP_VCXO_RM_REG_START                             0x00422800
+#define BCHP_VCXO_RM_REG_END                               0x0042282c
+#define BCHP_AVS_HW_MNTR_REG_START                         0x00423000
+#define BCHP_AVS_HW_MNTR_REG_END                           0x00423074
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_START                 0x00423100
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_END                   0x0042311c
+#define BCHP_AVS_ASB_REGISTERS_REG_START                   0x00423200
+#define BCHP_AVS_ASB_REGISTERS_REG_END                     0x00423218
+#define BCHP_AVS_RO_REGISTERS_0_REG_START                  0x00423300
+#define BCHP_AVS_RO_REGISTERS_0_REG_END                    0x004233dc
+#define BCHP_AVS_RO_REGISTERS_1_REG_START                  0x00423400
+#define BCHP_AVS_RO_REGISTERS_1_REG_END                    0x0042349c
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_START                0x00423500
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_END                  0x004235e4
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_START                0x00423600
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_END                  0x004236e4
+#define BCHP_CLKGEN_INTR2_REG_START                        0x00424000
+#define BCHP_CLKGEN_INTR2_REG_END                          0x0042402c
+#define BCHP_CLKGEN_GR_REG_START                           0x00424800
+#define BCHP_CLKGEN_GR_REG_END                             0x0042480c
+#define BCHP_GENET_0_SYS_REG_START                         0x00430000
+#define BCHP_GENET_0_SYS_REG_END                           0x0043000c
+#define BCHP_GENET_0_GR_BRIDGE_REG_START                   0x00430040
+#define BCHP_GENET_0_GR_BRIDGE_REG_END                     0x0043004c
+#define BCHP_GENET_0_EXT_REG_START                         0x00430080
+#define BCHP_GENET_0_EXT_REG_END                           0x00430098
+#define BCHP_GENET_0_INTRL2_0_REG_START                    0x00430200
+#define BCHP_GENET_0_INTRL2_0_REG_END                      0x0043022c
+#define BCHP_GENET_0_INTRL2_1_REG_START                    0x00430240
+#define BCHP_GENET_0_INTRL2_1_REG_END                      0x0043026c
+#define BCHP_GENET_0_RBUF_REG_START                        0x00430300
+#define BCHP_GENET_0_RBUF_REG_END                          0x004303ec
+#define BCHP_GENET_0_TBUF_REG_START                        0x00430600
+#define BCHP_GENET_0_TBUF_REG_END                          0x00430628
+#define BCHP_GENET_0_UMAC_REG_START                        0x00430800
+#define BCHP_GENET_0_UMAC_REG_END                          0x00430ed8
+#define BCHP_GENET_0_HFB_REG_START                         0x00431000
+#define BCHP_GENET_0_HFB_REG_END                           0x00432010
+#define BCHP_GENET_0_RDMA_REG_START                        0x00433000
+#define BCHP_GENET_0_RDMA_REG_END                          0x00433cb4
+#define BCHP_GENET_0_TDMA_REG_START                        0x00434000
+#define BCHP_GENET_0_TDMA_REG_END                          0x00434c88
+#define BCHP_M2MC_REG_START                                0x00450000
+#define BCHP_M2MC_REG_END                                  0x004507fc
+#define BCHP_M2MC_TOP_L2_REG_START                         0x00451000
+#define BCHP_M2MC_TOP_L2_REG_END                           0x0045102c
+#define BCHP_M2MC_TOP_GR_BRIDGE_REG_START                  0x00452000
+#define BCHP_M2MC_TOP_GR_BRIDGE_REG_END                    0x0045200c
+#define BCHP_USB_INTR2_REG_START                           0x00480000
+#define BCHP_USB_INTR2_REG_END                             0x0048002c
+#define BCHP_USB_GR_BRIDGE_REG_START                       0x00480100
+#define BCHP_USB_GR_BRIDGE_REG_END                         0x0048010c
+#define BCHP_USB_CTRL_REG_START                            0x00480200
+#define BCHP_USB_CTRL_REG_END                              0x00480238
+#define BCHP_USB_EHCI_REG_START                            0x00480300
+#define BCHP_USB_EHCI_REG_END                              0x004803a4
+#define BCHP_USB_OHCI_REG_START                            0x00480400
+#define BCHP_USB_OHCI_REG_END                              0x00480458
+#define BCHP_BOOTROM_REG_START                             0x00500000
+#define BCHP_BOOTROM_REG_END                               0x00500ffc
+#define BCHP_MFD_0_REG_START                               0x00600000
+#define BCHP_MFD_0_REG_END                                 0x006001fc
+#define BCHP_VFD_0_REG_START                               0x00601000
+#define BCHP_VFD_0_REG_END                                 0x006011fc
+#define BCHP_VFD_1_REG_START                               0x00601200
+#define BCHP_VFD_1_REG_END                                 0x006013fc
+#define BCHP_RDC_REG_START                                 0x00602000
+#define BCHP_RDC_REG_END                                   0x006029fc
+#define BCHP_BVNF_INTR2_0_REG_START                        0x00603000
+#define BCHP_BVNF_INTR2_0_REG_END                          0x0060302c
+#define BCHP_BVNF_INTR2_1_REG_START                        0x00603100
+#define BCHP_BVNF_INTR2_1_REG_END                          0x0060312c
+#define BCHP_BVNF_INTR2_3_REG_START                        0x00603300
+#define BCHP_BVNF_INTR2_3_REG_END                          0x0060332c
+#define BCHP_BVNF_INTR2_4_REG_START                        0x00603400
+#define BCHP_BVNF_INTR2_4_REG_END                          0x0060342c
+#define BCHP_BVNF_INTR2_5_REG_START                        0x00603500
+#define BCHP_BVNF_INTR2_5_REG_END                          0x0060352c
+#define BCHP_BVNF_INTR2_6_REG_START                        0x00603600
+#define BCHP_BVNF_INTR2_6_REG_END                          0x0060362c
+#define BCHP_BVNF_INTR2_7_REG_START                        0x00603700
+#define BCHP_BVNF_INTR2_7_REG_END                          0x0060372c
+#define BCHP_FMISC_REG_START                               0x00604000
+#define BCHP_FMISC_REG_END                                 0x00604020
+#define BCHP_SCL_0_REG_START                               0x00620000
+#define BCHP_SCL_0_REG_END                                 0x006203fc
+#define BCHP_SCL_1_REG_START                               0x00620800
+#define BCHP_SCL_1_REG_END                                 0x00620bfc
+#define BCHP_VNET_F_REG_START                              0x00622000
+#define BCHP_VNET_F_REG_END                                0x0062209c
+#define BCHP_VNET_B_REG_START                              0x00622200
+#define BCHP_VNET_B_REG_END                                0x006222ac
+#define BCHP_MMISC_REG_START                               0x00622800
+#define BCHP_MMISC_REG_END                                 0x00622820
+#define BCHP_LBOX_0_REG_START                              0x00625000
+#define BCHP_LBOX_0_REG_END                                0x00625070
+#define BCHP_BVNM_INTR2_0_REG_START                        0x00626000
+#define BCHP_BVNM_INTR2_0_REG_END                          0x0062602c
+#define BCHP_DNR_0_REG_START                               0x00627000
+#define BCHP_DNR_0_REG_END                                 0x006270a4
+#define BCHP_CAP_0_REG_START                               0x00640000
+#define BCHP_CAP_0_REG_END                                 0x0064007c
+#define BCHP_CAP_1_REG_START                               0x00640200
+#define BCHP_CAP_1_REG_END                                 0x0064027c
+#define BCHP_GFD_0_REG_START                               0x00641000
+#define BCHP_GFD_0_REG_END                                 0x00641228
+#define BCHP_GFD_1_REG_START                               0x00641400
+#define BCHP_GFD_1_REG_END                                 0x00641628
+#define BCHP_CMP_0_REG_START                               0x00642000
+#define BCHP_CMP_0_REG_END                                 0x00642264
+#define BCHP_CMP_1_REG_START                               0x00642800
+#define BCHP_CMP_1_REG_END                                 0x00642a64
+#define BCHP_TNT_CMP_0_V0_REG_START                        0x00643000
+#define BCHP_TNT_CMP_0_V0_REG_END                          0x006430a4
+#define BCHP_MASK_0_REG_START                              0x00643400
+#define BCHP_MASK_0_REG_END                                0x0064341c
+#define BCHP_PEP_CMP_0_V0_REG_START                        0x00644000
+#define BCHP_PEP_CMP_0_V0_REG_END                          0x00645484
+#define BCHP_BVNB_INTR2_REG_START                          0x00646000
+#define BCHP_BVNB_INTR2_REG_END                            0x0064602c
+#define BCHP_BMISC_REG_START                               0x00646400
+#define BCHP_BMISC_REG_END                                 0x0064641c
+#define BCHP_MVP_TOP_0_REG_START                           0x00660000
+#define BCHP_MVP_TOP_0_REG_END                             0x0066002c
+#define BCHP_SIOB_0_REG_START                              0x00660200
+#define BCHP_SIOB_0_REG_END                                0x006602fc
+#define BCHP_HSCL_0_REG_START                              0x00660400
+#define BCHP_HSCL_0_REG_END                                0x006607fc
+#define BCHP_MDI_TOP_0_REG_START                           0x00662000
+#define BCHP_MDI_TOP_0_REG_END                             0x00662044
+#define BCHP_MDI_PPB_0_REG_START                           0x00662800
+#define BCHP_MDI_PPB_0_REG_END                             0x00662bfc
+#define BCHP_MDI_FCN_0_REG_START                           0x00662c00
+#define BCHP_MDI_FCN_0_REG_END                             0x00662ffc
+#define BCHP_MISC_REG_START                                0x00680000
+#define BCHP_MISC_REG_END                                  0x00680080
+#define BCHP_IT_0_REG_START                                0x00681000
+#define BCHP_IT_0_REG_END                                  0x006817fc
+#define BCHP_IT_1_REG_START                                0x00682000
+#define BCHP_IT_1_REG_END                                  0x006827fc
+#define BCHP_VF_0_REG_START                                0x00683000
+#define BCHP_VF_0_REG_END                                  0x00683134
+#define BCHP_VF_1_REG_START                                0x00683200
+#define BCHP_VF_1_REG_END                                  0x00683334
+#define BCHP_SECAM_0_REG_START                             0x00683400
+#define BCHP_SECAM_0_REG_END                               0x00683414
+#define BCHP_SM_0_REG_START                                0x00683480
+#define BCHP_SM_0_REG_END                                  0x006834ac
+#define BCHP_SDSRC_0_REG_START                             0x00683500
+#define BCHP_SDSRC_0_REG_END                               0x0068350c
+#define BCHP_HDSRC_0_REG_START                             0x00683520
+#define BCHP_HDSRC_0_REG_END                               0x0068353c
+#define BCHP_CSC_0_REG_START                               0x00683580
+#define BCHP_CSC_0_REG_END                                 0x006835b0
+#define BCHP_CSC_1_REG_START                               0x00683600
+#define BCHP_CSC_1_REG_END                                 0x00683630
+#define BCHP_RM_0_REG_START                                0x00683680
+#define BCHP_RM_0_REG_END                                  0x006836a4
+#define BCHP_RM_1_REG_START                                0x006836c0
+#define BCHP_RM_1_REG_END                                  0x006836e4
+#define BCHP_ANA_DEBUG_0_REG_START                         0x00683700
+#define BCHP_ANA_DEBUG_0_REG_END                           0x00683744
+#define BCHP_GRPD_0_REG_START                              0x00683800
+#define BCHP_GRPD_0_REG_END                                0x006838ec
+#define BCHP_DTRAM_0_REG_START                             0x00684000
+#define BCHP_DTRAM_0_REG_END                               0x0068447c
+#define BCHP_DVI_DTG_0_REG_START                           0x00684800
+#define BCHP_DVI_DTG_0_REG_END                             0x00684954
+#define BCHP_DVI_CSC_0_REG_START                           0x00684a00
+#define BCHP_DVI_CSC_0_REG_END                             0x00684a30
+#define BCHP_DVI_DVF_0_REG_START                           0x00684b00
+#define BCHP_DVI_DVF_0_REG_END                             0x00684b14
+#define BCHP_DVI_DEBUG_0_REG_START                         0x00684c00
+#define BCHP_DVI_DEBUG_0_REG_END                           0x00684c44
+#define BCHP_VEC_CFG_REG_START                             0x00685000
+#define BCHP_VEC_CFG_REG_END                               0x006850d4
+#define BCHP_VIDEO_ENC_INTR2_REG_START                     0x00685400
+#define BCHP_VIDEO_ENC_INTR2_REG_END                       0x0068542c
+#define BCHP_VIDEO_ENC_TPG_0_REG_START                     0x00685500
+#define BCHP_VIDEO_ENC_TPG_0_REG_END                       0x00685518
+#define BCHP_VIDEO_ENC_DECIM_0_REG_START                   0x00685600
+#define BCHP_VIDEO_ENC_DECIM_0_REG_END                     0x00685608
+#define BCHP_DVP_TVG_0_REG_START                           0x00685700
+#define BCHP_DVP_TVG_0_REG_END                             0x00685788
+#define BCHP_VBI_ENC_REG_START                             0x00686000
+#define BCHP_VBI_ENC_REG_END                               0x00686054
+#define BCHP_CCE_0_REG_START                               0x00686400
+#define BCHP_CCE_0_REG_END                                 0x00686458
+#define BCHP_CCE_1_REG_START                               0x00686500
+#define BCHP_CCE_1_REG_END                                 0x00686558
+#define BCHP_WSE_0_REG_START                               0x00686600
+#define BCHP_WSE_0_REG_END                                 0x00686614
+#define BCHP_WSE_1_REG_START                               0x00686700
+#define BCHP_WSE_1_REG_END                                 0x00686714
+#define BCHP_CGMSAE_0_REG_START                            0x00686800
+#define BCHP_CGMSAE_0_REG_END                              0x00686858
+#define BCHP_CGMSAE_1_REG_START                            0x00686900
+#define BCHP_CGMSAE_1_REG_END                              0x00686958
+#define BCHP_TTE_0_REG_START                               0x00686a00
+#define BCHP_TTE_0_REG_END                                 0x00686a28
+#define BCHP_TTE_1_REG_START                               0x00686b00
+#define BCHP_TTE_1_REG_END                                 0x00686b28
+#define BCHP_GSE_0_REG_START                               0x00686c00
+#define BCHP_GSE_0_REG_END                                 0x00686c80
+#define BCHP_GSE_1_REG_START                               0x00686d00
+#define BCHP_GSE_1_REG_END                                 0x00686d80
+#define BCHP_AMOLE_0_REG_START                             0x00686e00
+#define BCHP_AMOLE_0_REG_END                               0x00686e8c
+#define BCHP_AMOLE_1_REG_START                             0x00686f00
+#define BCHP_AMOLE_1_REG_END                               0x00686f8c
+#define BCHP_DVP_HT_REG_START                              0x006a0000
+#define BCHP_DVP_HT_REG_END                                0x006a00dc
+#define BCHP_HDMI_REG_START                                0x006a0800
+#define BCHP_HDMI_REG_END                                  0x006a0994
+#define BCHP_HDMI_TX_PHY_REG_START                         0x006a0a80
+#define BCHP_HDMI_TX_PHY_REG_END                           0x006a0ad8
+#define BCHP_HDMI_RM_REG_START                             0x006a0b00
+#define BCHP_HDMI_RM_REG_END                               0x006a0b2c
+#define BCHP_HDMI_TX_INTR2_REG_START                       0x006a0b40
+#define BCHP_HDMI_TX_INTR2_REG_END                         0x006a0b6c
+#define BCHP_HDMI_RAM_REG_START                            0x006a0c00
+#define BCHP_HDMI_RAM_REG_END                              0x006a0dfc
+#define BCHP_BVN_RGR_REG_START                             0x006a8000
+#define BCHP_BVN_RGR_REG_END                               0x006a8010
+#define BCHP_SDS_CG_REG_START                              0x00700000
+#define BCHP_SDS_CG_REG_END                                0x00700038
+#define BCHP_SDS_FE_REG_START                              0x00700080
+#define BCHP_SDS_FE_REG_END                                0x007000bc
+#define BCHP_SDS_AGC_REG_START                             0x00700100
+#define BCHP_SDS_AGC_REG_END                               0x00700124
+#define BCHP_SDS_BL_REG_START                              0x00700140
+#define BCHP_SDS_BL_REG_END                                0x00700160
+#define BCHP_SDS_CL_REG_START                              0x00700180
+#define BCHP_SDS_CL_REG_END                                0x007001fc
+#define BCHP_SDS_EQ_REG_START                              0x00700200
+#define BCHP_SDS_EQ_REG_END                                0x0070028c
+#define BCHP_SDS_HP_REG_START                              0x00700300
+#define BCHP_SDS_HP_REG_END                                0x007003d4
+#define BCHP_SDS_VIT_REG_START                             0x00700400
+#define BCHP_SDS_VIT_REG_END                               0x00700428
+#define BCHP_SDS_FEC_REG_START                             0x00700440
+#define BCHP_SDS_FEC_REG_END                               0x00700454
+#define BCHP_SDS_OI_REG_START                              0x00700480
+#define BCHP_SDS_OI_REG_END                                0x007004c8
+#define BCHP_SDS_SNR_REG_START                             0x00700500
+#define BCHP_SDS_SNR_REG_END                               0x00700518
+#define BCHP_SDS_BERT_REG_START                            0x00700540
+#define BCHP_SDS_BERT_REG_END                              0x0070055c
+#define BCHP_SDS_DFT_REG_START                             0x00700580
+#define BCHP_SDS_DFT_REG_END                               0x007005a8
+#define BCHP_SDS_CWC_REG_START                             0x00700600
+#define BCHP_SDS_CWC_REG_END                               0x00700694
+#define BCHP_SDS_MISC_REG_START                            0x00700700
+#define BCHP_SDS_MISC_REG_END                              0x00700798
+#define BCHP_SDS_DSEC_REG_START                            0x00700800
+#define BCHP_SDS_DSEC_REG_END                              0x007008c8
+#define BCHP_SDS_TUNER_REG_START                           0x00700900
+#define BCHP_SDS_TUNER_REG_END                             0x007009fc
+#define BCHP_SDS_INTR2_0_REG_START                         0x00700a00
+#define BCHP_SDS_INTR2_0_REG_END                           0x00700a2c
+#define BCHP_SDS_INTR2_1_REG_START                         0x00700b00
+#define BCHP_SDS_INTR2_1_REG_END                           0x00700b2c
+#define BCHP_SDS_GR_BRIDGE_REG_START                       0x00700c00
+#define BCHP_SDS_GR_BRIDGE_REG_END                         0x00700c0c
+#define BCHP_TFEC_REG_START                                0x00702000
+#define BCHP_TFEC_REG_END                                  0x00702060
+#define BCHP_TFEC_MISC_REG_START                           0x00702100
+#define BCHP_TFEC_MISC_REG_END                             0x00702108
+#define BCHP_TFEC_INTR2_REG_START                          0x00702200
+#define BCHP_TFEC_INTR2_REG_END                            0x0070222c
+#define BCHP_TFEC_GR_BRIDGE_REG_START                      0x00702300
+#define BCHP_TFEC_GR_BRIDGE_REG_END                        0x0070230c
+#define BCHP_AFEC_REG_START                                0x00704000
+#define BCHP_AFEC_REG_END                                  0x007043fc
+#define BCHP_AFEC_INTR_CTRL2_REG_START                     0x00704800
+#define BCHP_AFEC_INTR_CTRL2_REG_END                       0x0070482c
+#define BCHP_AFEC_GR_BRIDGE_REG_START                      0x00704900
+#define BCHP_AFEC_GR_BRIDGE_REG_END                        0x0070490c
+#define BCHP_AFEC_GLOBAL_REG_START                         0x00704a00
+#define BCHP_AFEC_GLOBAL_REG_END                           0x00704a0c
+#define BCHP_FTM_UART_REG_START                            0x00706000
+#define BCHP_FTM_UART_REG_END                              0x007060fc
+#define BCHP_FTM_PHY_REG_START                             0x00706000
+#define BCHP_FTM_PHY_REG_END                               0x007061fc
+#define BCHP_FTM_PHY_ANA_REG_START                         0x00706000
+#define BCHP_FTM_PHY_ANA_REG_END                           0x00706210
+#define BCHP_FTM_SKIT_REG_START                            0x00706000
+#define BCHP_FTM_SKIT_REG_END                              0x00706248
+#define BCHP_FTM_INTR2_REG_START                           0x00706000
+#define BCHP_FTM_INTR2_REG_END                             0x0070632c
+#define BCHP_FTM_GR_BRIDGE_REG_START                       0x00706000
+#define BCHP_FTM_GR_BRIDGE_REG_END                         0x0070633c
+#define BCHP_FTM_SW_SPARE_REG_START                        0x00706000
+#define BCHP_FTM_SW_SPARE_REG_END                          0x00706344
+#define BCHP_RAAGA_DSP_RGR_REG_START                       0x00800000
+#define BCHP_RAAGA_DSP_RGR_REG_END                         0x00800008
+#define BCHP_RAAGA_DSP_MISC_REG_START                      0x00820000
+#define BCHP_RAAGA_DSP_MISC_REG_END                        0x0082044c
+#define BCHP_RAAGA_DSP_TIMERS_REG_START                    0x00821000
+#define BCHP_RAAGA_DSP_TIMERS_REG_END                      0x00821058
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START             0x00821080
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END               0x0082109c
+#define BCHP_RAAGA_DSP_PERI_SW_REG_START                   0x00821100
+#define BCHP_RAAGA_DSP_PERI_SW_REG_END                     0x00821154
+#define BCHP_RAAGA_DSP_DMA_REG_START                       0x00821400
+#define BCHP_RAAGA_DSP_DMA_REG_END                         0x00821664
+#define BCHP_RAAGA_DSP_ESR_SI_REG_START                    0x00822000
+#define BCHP_RAAGA_DSP_ESR_SI_REG_END                      0x00822014
+#define BCHP_RAAGA_DSP_INTH_REG_START                      0x00822200
+#define BCHP_RAAGA_DSP_INTH_REG_END                        0x0082222c
+#define BCHP_RAAGA_DSP_FW_INTH_REG_START                   0x00822400
+#define BCHP_RAAGA_DSP_FW_INTH_REG_END                     0x0082242c
+#define BCHP_RAAGA_DSP_FW_CFG_REG_START                    0x00823000
+#define BCHP_RAAGA_DSP_FW_CFG_REG_END                      0x0082357c
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START             0x00830000
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END               0x0083bffc
+#define BCHP_AIO_MISC_REG_START                            0x00880000
+#define BCHP_AIO_MISC_REG_END                              0x00880010
+#define BCHP_AIO_INTH_REG_START                            0x00880800
+#define BCHP_AIO_INTH_REG_END                              0x0088082c
+#define BCHP_AIO_INTD0_REG_START                           0x00880a00
+#define BCHP_AIO_INTD0_REG_END                             0x00880a14
+#define BCHP_AUD_FMM_MISC_REG_START                        0x008a0000
+#define BCHP_AUD_FMM_MISC_REG_END                          0x008a010c
+#define BCHP_AUD_FMM_BF_CTRL_REG_START                     0x008a2000
+#define BCHP_AUD_FMM_BF_CTRL_REG_END                       0x008a2b7c
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_START                   0x008a3000
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_END                     0x008a3014
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_START                   0x008a3020
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_END                     0x008a3034
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_START                   0x008a3040
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_END                     0x008a3054
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_START                  0x008a3100
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_END                    0x008a3114
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_START                  0x008a3120
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_END                    0x008a3134
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_START                  0x008a3140
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_END                    0x008a3154
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_START                   0x008a4000
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_END                     0x008a4bfc
+#define BCHP_AUD_FMM_SRC_ESR0_REG_START                    0x008a5000
+#define BCHP_AUD_FMM_SRC_ESR0_REG_END                      0x008a5014
+#define BCHP_AUD_FMM_DP_CTRL0_REG_START                    0x008a8000
+#define BCHP_AUD_FMM_DP_CTRL0_REG_END                      0x008a98ec
+#define BCHP_AUD_FMM_DP_ESR00_REG_START                    0x008abc00
+#define BCHP_AUD_FMM_DP_ESR00_REG_END                      0x008abc14
+#define BCHP_AUD_FMM_DP_ESR20_REG_START                    0x008abc80
+#define BCHP_AUD_FMM_DP_ESR20_REG_END                      0x008abc94
+#define BCHP_AUD_FMM_IOP_CTRL_REG_START                    0x008b8000
+#define BCHP_AUD_FMM_IOP_CTRL_REG_END                      0x008b8144
+#define BCHP_AUD_FMM_IOP_ESR_REG_START                     0x008b8400
+#define BCHP_AUD_FMM_IOP_ESR_REG_END                       0x008b8414
+#define BCHP_AUD_FMM_OP_CTRL_REG_START                     0x008ba000
+#define BCHP_AUD_FMM_OP_CTRL_REG_END                       0x008ba1fc
+#define BCHP_AUD_FMM_OP_ESR_REG_START                      0x008ba400
+#define BCHP_AUD_FMM_OP_ESR_REG_END                        0x008ba414
+#define BCHP_AUD_FMM_PLL0_REG_START                        0x008ba800
+#define BCHP_AUD_FMM_PLL0_REG_END                          0x008ba834
+#define BCHP_AUD_FMM_PLL1_REG_START                        0x008ba900
+#define BCHP_AUD_FMM_PLL1_REG_END                          0x008ba934
+#define BCHP_HIFIDAC_CTRL0_REG_START                       0x008bb000
+#define BCHP_HIFIDAC_CTRL0_REG_END                         0x008bb1fc
+#define BCHP_HIFIDAC_RM0_REG_START                         0x008bb200
+#define BCHP_HIFIDAC_RM0_REG_END                           0x008bb224
+#define BCHP_HIFIDAC_ESR0_REG_START                        0x008bb300
+#define BCHP_HIFIDAC_ESR0_REG_END                          0x008bb314
+#define BCHP_AUD_FMM_MS_CTRL_REG_START                     0x008bc000
+#define BCHP_AUD_FMM_MS_CTRL_REG_END                       0x008bdbfc
+#define BCHP_AUD_FMM_MS_ESR_REG_START                      0x008be000
+#define BCHP_AUD_FMM_MS_ESR_REG_END                        0x008be014
+#define BCHP_RAAGA_DSP_SEC0_REG_START                      0x00900000
+#define BCHP_RAAGA_DSP_SEC0_REG_END                        0x00900000
+#define BCHP_XPT_BUS_IF_REG_START                          0x00a00000
+#define BCHP_XPT_BUS_IF_REG_END                            0x00a00088
+#define BCHP_XPT_XMEMIF_REG_START                          0x00a01000
+#define BCHP_XPT_XMEMIF_REG_END                            0x00a0109c
+#define BCHP_XPT_PMU_REG_START                             0x00a01800
+#define BCHP_XPT_PMU_REG_END                               0x00a01808
+#define BCHP_XPT_WAKEUP_REG_START                          0x00a02000
+#define BCHP_XPT_WAKEUP_REG_END                            0x00a02fbc
+#define BCHP_XPT_RMX0_IO_REG_START                         0x00a03000
+#define BCHP_XPT_RMX0_IO_REG_END                           0x00a03020
+#define BCHP_XPT_RMX1_IO_REG_START                         0x00a03100
+#define BCHP_XPT_RMX1_IO_REG_END                           0x00a03120
+#define BCHP_XPT_FE_REG_START                              0x00a04000
+#define BCHP_XPT_FE_REG_END                                0x00a04ffc
+#define BCHP_XPT_DPCR0_REG_START                           0x00a06000
+#define BCHP_XPT_DPCR0_REG_END                             0x00a06074
+#define BCHP_XPT_DPCR1_REG_START                           0x00a06080
+#define BCHP_XPT_DPCR1_REG_END                             0x00a060f4
+#define BCHP_XPT_DPCR2_REG_START                           0x00a06100
+#define BCHP_XPT_DPCR2_REG_END                             0x00a06174
+#define BCHP_XPT_DPCR3_REG_START                           0x00a06180
+#define BCHP_XPT_DPCR3_REG_END                             0x00a061f4
+#define BCHP_XPT_DPCR_PP_REG_START                         0x00a06400
+#define BCHP_XPT_DPCR_PP_REG_END                           0x00a06404
+#define BCHP_XPT_PSUB_REG_START                            0x00a06600
+#define BCHP_XPT_PSUB_REG_END                              0x00a066c8
+#define BCHP_XPT_RSBUFF_REG_START                          0x00a06800
+#define BCHP_XPT_RSBUFF_REG_END                            0x00a06f2c
+#define BCHP_XPT_PB0_REG_START                             0x00a07000
+#define BCHP_XPT_PB0_REG_END                               0x00a07060
+#define BCHP_XPT_PB1_REG_START                             0x00a07080
+#define BCHP_XPT_PB1_REG_END                               0x00a070e0
+#define BCHP_XPT_PB2_REG_START                             0x00a07100
+#define BCHP_XPT_PB2_REG_END                               0x00a07160
+#define BCHP_XPT_PB3_REG_START                             0x00a07180
+#define BCHP_XPT_PB3_REG_END                               0x00a071e0
+#define BCHP_XPT_MPOD_REG_START                            0x00a08000
+#define BCHP_XPT_MPOD_REG_END                              0x00a08020
+#define BCHP_XPT_RMX0_REG_START                            0x00a08400
+#define BCHP_XPT_RMX0_REG_END                              0x00a08408
+#define BCHP_XPT_RMX1_REG_START                            0x00a08500
+#define BCHP_XPT_RMX1_REG_END                              0x00a08508
+#define BCHP_XPT_XCBUFF_REG_START                          0x00a0a000
+#define BCHP_XPT_XCBUFF_REG_END                            0x00a0bcc8
+#define BCHP_XPT_RAVE_REG_START                            0x00a10000
+#define BCHP_XPT_RAVE_REG_END                              0x00a1a69c
+#define BCHP_XPT_PCROFFSET_REG_START                       0x00a1b000
+#define BCHP_XPT_PCROFFSET_REG_END                         0x00a1bffc
+#define BCHP_XPT_MSG_REG_START                             0x00a20000
+#define BCHP_XPT_MSG_REG_END                               0x00a24814
+#define BCHP_XPT_GR_REG_START                              0x00a25000
+#define BCHP_XPT_GR_REG_END                                0x00a2500c
+#define BCHP_XPT_FULL_PID_PARSER_REG_START                 0x00a26000
+#define BCHP_XPT_FULL_PID_PARSER_REG_END                   0x00a27050
+#define BCHP_XPT_XPU_REG_START                             0x00a28000
+#define BCHP_XPT_XPU_REG_END                               0x00a2c7fc
+#define BCHP_XPT_SECURE_BUS_IF_REG_START                   0x00a38000
+#define BCHP_XPT_SECURE_BUS_IF_REG_END                     0x00a38000
+#define BCHP_RFM_SYSCLK_REG_START                          0x00b00000
+#define BCHP_RFM_SYSCLK_REG_END                            0x00b00118
+#define BCHP_RFM_CLK27_REG_START                           0x00b00000
+#define BCHP_RFM_CLK27_REG_END                             0x00b00470
+#define BCHP_RFM_L2_REG_START                              0x00b00c00
+#define BCHP_RFM_L2_REG_END                                0x00b00c2c
+#define BCHP_RFM_GRB_REG_START                             0x00b01000
+#define BCHP_RFM_GRB_REG_END                               0x00b0100c
+
+
+/***************************************************************************
+ *AUD_FMM_MS_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK  0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
+
+/***************************************************************************
+ *AUD_FMM_OP_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
+ ***************************************************************************/
+/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_VFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *GFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK      0xffffffff
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT     0
+
+/***************************************************************************
+ *HIFIDAC_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_MUTE_USAGE - Mute usage
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *M2MC
+ ***************************************************************************/
+/***************************************************************************
+ *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK          0xffffffff
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT         0
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK              0xf0000000
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT             28
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK          0x0fffffe0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT         5
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK              0x0000001e
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT             1
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK           0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT          0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid   0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK              0xffff8000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT             15
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK   0x00004000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT  14
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK   0x00002000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT  13
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK         0x00000800
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT        11
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE   1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE  0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK  0x00000400
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK  0x00000200
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK          0x00000100
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT         8
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE   0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK   0x00000020
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT  5
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK     0x00000002
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK     0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT    0
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/***************************************************************************
+ *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK        0xffffffff
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT       0
+
+/***************************************************************************
+ *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK         0xffffffff
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT        0
+
+/***************************************************************************
+ *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_11_DST_COLOR_MATRIX_N - Linked-List Packet Word N for group DST_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_11_DST_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_12_OUTPUT_COLOR_MATRIX_N - Linked-List Packet Word N for group OUTPUT_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_12_OUTPUT_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_13_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *LIST_PKT_14_DST_CLUT - Linked-List Packet Word for group DST_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_14_DST_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_14_DST_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *TYPE_CLUT_COLOR_DATA - color data for color look up table
+ ***************************************************************************/
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK                  0xff000000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT                 24
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK                    0x00ff0000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT                   16
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK                  0x0000ff00
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT                 8
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK                   0x000000ff
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT                  0
+
+/***************************************************************************
+ *MEM_DMA
+ ***************************************************************************/
+/***************************************************************************
+ *DESC_WORD0 - MEM DMA Descriptor Word 0
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD0 :: READ_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD1 - MEM DMA Descriptor Word 1
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD1 :: WRITE_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_MASK                    0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD2 - MEM DMA Descriptor Word 2
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD2 :: INTR_ENABLE [31:31] */
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK                   0x80000000
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_SHIFT                  31
+
+/* MEM_DMA :: DESC_WORD2 :: LAST [30:30] */
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_MASK                          0x40000000
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_SHIFT                         30
+
+/* MEM_DMA :: DESC_WORD2 :: AUTO_APPEND [29:29] */
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_MASK                   0x20000000
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_SHIFT                  29
+
+/* MEM_DMA :: DESC_WORD2 :: reserved0 [28:25] */
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_MASK                     0x1e000000
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_SHIFT                    25
+
+/* MEM_DMA :: DESC_WORD2 :: TRANSFER_SIZE [24:00] */
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK                 0x01ffffff
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_SHIFT                0
+
+/***************************************************************************
+ *DESC_WORD3 - MEM DMA Descriptor Word 3
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD3 :: NEXT_DESC_ADDR [31:05] */
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK                0xffffffe0
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_SHIFT               5
+
+/* MEM_DMA :: DESC_WORD3 :: reserved0 [04:03] */
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_MASK                     0x00000018
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_SHIFT                    3
+
+/* MEM_DMA :: DESC_WORD3 :: READ_ENDIAN_MODE [02:02] */
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_MASK              0x00000004
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_SHIFT             2
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_BIG_ENDIAN        0
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_LITTLE_ENDIAN     1
+
+/* MEM_DMA :: DESC_WORD3 :: WRITE_ENDIAN_XLATE_MODE [01:00] */
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_MASK       0x00000003
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_SHIFT      0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_WORD_ALIGNED 0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_HALF_WORD_ALIGNED 1
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_BYTE_ALIGNED 2
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_reserved   3
+
+/***************************************************************************
+ *DESC_WORD4 - MEM DMA Descriptor Word 4
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD4 :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_SHIFT                    16
+
+/* MEM_DMA :: DESC_WORD4 :: SCRAM_CTRL_RSV [15:14] */
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_MASK                0x0000c000
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_SHIFT               14
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_END [13:13] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK                  0x00002000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_SHIFT                 13
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_START [12:12] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK                0x00001000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_SHIFT               12
+
+/* MEM_DMA :: DESC_WORD4 :: SG_ENABLE [11:11] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK                     0x00000800
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_SHIFT                    11
+
+/* MEM_DMA :: DESC_WORD4 :: ENC_DEC_INIT [10:10] */
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_MASK                  0x00000400
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_SHIFT                 10
+
+/* MEM_DMA :: DESC_WORD4 :: MODE_SEL [09:08] */
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_MASK                      0x00000300
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT                     8
+
+/* MEM_DMA :: DESC_WORD4 :: KEY_SELECT [07:00] */
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_MASK                    0x000000ff
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD5 - MEM DMA Descriptor Word 5
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD5 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD6 - MEM DMA Descriptor Word 6
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD6 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD7 - MEM DMA Descriptor Word 7
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD7 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *RAAGA_REGSET_DSP_CFG
+ ***************************************************************************/
+/***************************************************************************
+ *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK     0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT    0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo   2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono     1
+
+/***************************************************************************
+ *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right -2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right -2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right -2147483648
+
+/***************************************************************************
+ *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
+
+/***************************************************************************
+ *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off     0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On      1
+
+/***************************************************************************
+ *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt  1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo  2
+
+/***************************************************************************
+ *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK       0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT      0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono    1
+
+/***************************************************************************
+ *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK   0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *RDC
+ ***************************************************************************/
+/***************************************************************************
+ *RUL - RUL Command.
+ ***************************************************************************/
+/* RDC :: RUL :: opcode [31:24] */
+#define BCHP_RDC_RUL_opcode_MASK                                   0xff000000
+#define BCHP_RDC_RUL_opcode_SHIFT                                  24
+#define BCHP_RDC_RUL_opcode_NOP                                    0
+#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM                          1
+#define BCHP_RDC_RUL_opcode_REG_WRITE                              2
+#define BCHP_RDC_RUL_opcode_REG_READ                               3
+#define BCHP_RDC_RUL_opcode_LOAD_IMM                               4
+#define BCHP_RDC_RUL_opcode_WINDOW_WRITE                           5
+#define BCHP_RDC_RUL_opcode_BLOCK_WRITE                            6
+#define BCHP_RDC_RUL_opcode_WINDOW_COPY                            7
+#define BCHP_RDC_RUL_opcode_BLOCK_COPY                             8
+#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK                        9
+#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW                        10
+#define BCHP_RDC_RUL_opcode_AND                                    11
+#define BCHP_RDC_RUL_opcode_AND_IMM                                12
+#define BCHP_RDC_RUL_opcode_OR                                     13
+#define BCHP_RDC_RUL_opcode_OR_IMM                                 14
+#define BCHP_RDC_RUL_opcode_XOR                                    15
+#define BCHP_RDC_RUL_opcode_XOR_IMM                                16
+#define BCHP_RDC_RUL_opcode_NOT                                    17
+#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT                           18
+#define BCHP_RDC_RUL_opcode_SUM                                    19
+#define BCHP_RDC_RUL_opcode_SUM_IMM                                20
+#define BCHP_RDC_RUL_opcode_COND_SKIP                              21
+#define BCHP_RDC_RUL_opcode_SKIP                                   22
+#define BCHP_RDC_RUL_opcode_EXIT                                   23
+#define BCHP_RDC_RUL_opcode_PLACEHOLDER                            255
+
+/* RDC :: RUL :: reserved0 [23:23] */
+#define BCHP_RDC_RUL_reserved0_MASK                                0x00800000
+#define BCHP_RDC_RUL_reserved0_SHIFT                               23
+
+/* union - case rdc_args [22:00] */
+/* RDC :: RUL :: rdc_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_rdc_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: rdc_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_rdc_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_rdc_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: rdc_args :: src2 [11:06] */
+#define BCHP_RDC_RUL_rdc_args_src2_MASK                            0x00000fc0
+#define BCHP_RDC_RUL_rdc_args_src2_SHIFT                           6
+
+/* RDC :: RUL :: rdc_args :: dest [05:00] */
+#define BCHP_RDC_RUL_rdc_args_dest_MASK                            0x0000003f
+#define BCHP_RDC_RUL_rdc_args_dest_SHIFT                           0
+
+/* union - case reg_args [22:00] */
+/* RDC :: RUL :: reg_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_reg_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_reg_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: reg_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_reg_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_reg_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: reg_args :: count [11:00] */
+#define BCHP_RDC_RUL_reg_args_count_MASK                           0x00000fff
+#define BCHP_RDC_RUL_reg_args_count_SHIFT                          0
+
+/***************************************************************************
+ *XPT_PB
+ ***************************************************************************/
+/***************************************************************************
+ *DESCRIPTOR_ABSTRACT - Playback Linked-List Descriptor Abstract
+ ***************************************************************************/
+/* XPT_PB :: DESCRIPTOR_ABSTRACT :: DESCRIPTOR_FORMAT [31:00] */
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_MASK     0xffffffff
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_SHIFT    0
+
+/***************************************************************************
+ *DESC_0 - Playback Linked-List Descriptor Word 0
+ ***************************************************************************/
+/* XPT_PB :: DESC_0 :: PB_BUFFER_START_ADDR [31:00] */
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_MASK               0xffffffff
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_SHIFT              0
+
+/***************************************************************************
+ *DESC_1 - Playback Linked-List Descriptor Word 1
+ ***************************************************************************/
+/* XPT_PB :: DESC_1 :: PB_BUFFER_LENGTH [31:00] */
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_MASK                   0xffffffff
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_SHIFT                  0
+
+/***************************************************************************
+ *DESC_2 - Playback Linked-List Descriptor Word 2
+ ***************************************************************************/
+/* XPT_PB :: DESC_2 :: PB_INTERRUPT_ENABLE [31:31] */
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_MASK                0x80000000
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_SHIFT               31
+
+/* XPT_PB :: DESC_2 :: PB_FORCE_RESYNC [30:30] */
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_MASK                    0x40000000
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_SHIFT                   30
+
+/* XPT_PB :: DESC_2 :: PB_HOST_DATA_INS_EN [29:29] */
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_MASK                0x20000000
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_SHIFT               29
+
+/* XPT_PB :: DESC_2 :: reserved0 [28:28] */
+#define BCHP_XPT_PB_DESC_2_reserved0_MASK                          0x10000000
+#define BCHP_XPT_PB_DESC_2_reserved0_SHIFT                         28
+
+/* XPT_PB :: DESC_2 :: PB_DESC_TAG_ID [27:24] */
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_MASK                     0x0f000000
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_SHIFT                    24
+
+/* XPT_PB :: DESC_2 :: reserved1 [23:00] */
+#define BCHP_XPT_PB_DESC_2_reserved1_MASK                          0x00ffffff
+#define BCHP_XPT_PB_DESC_2_reserved1_SHIFT                         0
+
+/***************************************************************************
+ *DESC_3 - Playback Linked-List Descriptor Word 3
+ ***************************************************************************/
+/* XPT_PB :: DESC_3 :: PB_NEXT_DESC_ADDR [31:04] */
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_MASK                  0xfffffff0
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_SHIFT                 4
+
+/* XPT_PB :: DESC_3 :: reserved0 [03:01] */
+#define BCHP_XPT_PB_DESC_3_reserved0_MASK                          0x0000000e
+#define BCHP_XPT_PB_DESC_3_reserved0_SHIFT                         1
+
+/* XPT_PB :: DESC_3 :: PB_LAST_DESC_IND [00:00] */
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_MASK                   0x00000001
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_SHIFT                  0
+
+/***************************************************************************
+ *XPT_RAVE
+ ***************************************************************************/
+/***************************************************************************
+ *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
+
+/***************************************************************************
+ *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
+
+/***************************************************************************
+ *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
+ ***************************************************************************/
+/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
+
+#endif /* #ifndef BCHP_COMMON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_ddr40_phy_control_regs_0.h b/include/linux/brcmstb/7360a0/bchp_ddr40_phy_control_regs_0.h
new file mode 100644
index 0000000..3549fcd
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_ddr40_phy_control_regs_0.h
@@ -0,0 +1,1539 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_ddr40_phy_control_regs_0.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:43a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_CONTROL_REGS_0 - DDR40 DDR40 physical interface control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION   0x003b6000 /* Address & Control revision register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL 0x003b6004 /* PHY clock power management control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS 0x003b6010 /* PHY PLL status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG 0x003b6014 /* PHY PLL configuration register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL 0x003b6018 /* PHY PLL control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS 0x003b601c /* PHY PLL dividers control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL 0x003b6020 /* Aux Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL 0x003b6030 /* Address & Control coarse VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL 0x003b6034 /* Address & Control fine VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL 0x003b6038 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL 0x003b603c /* PVT Compensation control and status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL 0x003b6040 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS 0x003b6044 /* PHY Auto Init rd_data_dly result register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE 0x003b6048 /* PHY VDL calibration control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS 0x003b604c /* PHY VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS 0x003b6050 /* PHY DQ VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS 0x003b6054 /* PHY Write Channel VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS 0x003b6058 /* PHY Read Enable VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL 0x003b605c /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS 0x003b6060 /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS 0x003b6064 /* Virtual VTT Connections register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE 0x003b6068 /* Virtual VTT Override register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL 0x003b606c /* VREF DAC Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL 0x003b6070 /* PhyBist Control Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED 0x003b6074 /* PhyBist Seed Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS 0x003b6078 /* PhyBist General Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS 0x003b607c /* PhyBist Per-Bit Control Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS 0x003b6080 /* PhyBist Per-Bit DQ Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS 0x003b6084 /* PhyBist Per-Bit DM and CK Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG 0x003b6090 /* DRAM Command Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0  0x003b6094 /* Mode Register 0 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1  0x003b6098 /* Mode Register 1 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2  0x003b609c /* Mode Register 2 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3  0x003b60a0 /* Mode Register 3 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL 0x003b60a4 /* Standby Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL 0x003b60b0 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2 0x003b60b4 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS 0x003b60b8 /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2 0x003b60bc /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE 0x003b60c0 /* Freeze-on-error enable register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK 0x003b60c4 /* Datapth Loopback control register */
+
+/***************************************************************************
+ *REVISION - Address & Control revision register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: reserved0 [31:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_MASK      0xff800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_SHIFT     23
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: TECHNOLOGY [22:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_TECHNOLOGY_MASK     0x00700000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_TECHNOLOGY_SHIFT    20
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: WB [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_WB_MASK             0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_WB_SHIFT            19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: BITS [18:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_BITS_MASK           0x00070000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_BITS_SHIFT          16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_MASK          0x0000ff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_SHIFT         8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_DEFAULT       0x00000040
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_MASK          0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_DEFAULT       0x00000006
+
+/***************************************************************************
+ *CLK_PM_CTRL - PHY clock power management control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_MASK   0xfffffffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_SHIFT  1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_STATUS - PHY PLL status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_MASK    0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_SHIFT   27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK_LOST [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_MASK    0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_SHIFT   26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: DDR_MHZ [25:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_MASK      0x03ffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_SHIFT     14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_4X [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: STATUS [12:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_MASK       0x00001ffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_SHIFT      1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_MASK         0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_CONFIG - PHY PLL configuration register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved0 [31:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_MASK    0xffffff80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_SHIFT   7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LP40_PLL_POST_RESET [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET_POST_DIV [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LDO_CTRL [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_MASK     0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_SHIFT    3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_DEFAULT  0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved1 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_MASK    0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_SHIFT   2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_MASK        0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_SHIFT       1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_DEFAULT     0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PWRDN [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_MASK        0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_SHIFT       0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PLL_CONTROL - PHY PLL control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: reserved0 [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_SHIFT  31
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_kp [30:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_MASK        0x78000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_SHIFT       27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_DEFAULT     0x0000000a
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ki [26:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_MASK        0x07000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_SHIFT       24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_DEFAULT     0x00000003
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ka [23:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_MASK        0x00e00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_SHIFT       21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_DEFAULT     0x00000003
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: PLL_CONTROL [20:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_MASK 0x001fffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_DIVIDERS - PHY PLL dividers control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_MASK  0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_SHIFT 16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_HI [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_MASK 0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_LO [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: POST_DIV [13:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_MASK   0x00003800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_SHIFT  11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_DEFAULT 0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: PDIV [10:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_MASK       0x00000700
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_SHIFT      8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_DEFAULT    0x00000004
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_MASK       0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_DEFAULT    0x00000020
+
+/***************************************************************************
+ *AUX_CONTROL - Aux Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved0 [31:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_MASK   0xfffffc00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_SHIFT  10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_cs [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_MASK       0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_SHIFT      7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_ad [06:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_MASK       0x00000070
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_SHIFT      4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_odt [03:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_MASK      0x0000000e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_SHIFT     1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: override [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_CTL - Address & Control coarse VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BIT_CTL - Address & Control fine VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_SHIFT  31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved0 [30:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ffffe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: rxenb [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_MASK  0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved1 [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_SHIFT 7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_reb [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ZQ_PVT_COMP_CTL - PVT Compensation control and status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: update_mode [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_done [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_done [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_done [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: auto_sample_en [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_MASK 0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_en [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_ovr_en [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_ovr_en [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_comp [17:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_MASK 0x00038000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_comp [14:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_MASK 0x00007000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [11:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_MASK 0x00000e00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [08:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_MASK 0x000001c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: auto_oeb [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a15 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_MASK  0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a14 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_MASK  0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a13 [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_MASK  0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_aux [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_MASK  0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: half_strength [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_MASK     0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_SHIFT    2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_MASK  0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_MASK     0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_SHIFT    0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_DEFAULT  0x00000000
+
+/***************************************************************************
+ *VDL_RD_DATA_DLY_STATUS - PHY Auto Init rd_data_dly result register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_SHIFT 12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: auto_init_state [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_MASK 0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_max [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_min [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_DEFAULT 0x00000007
+
+/***************************************************************************
+ *VDL_CALIBRATE - PHY VDL calibration control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_MASK 0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: single_cycle [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_single_cycle_MASK 0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_single_cycle_SHIFT 29
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_single_cycle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: use_straps [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: auto_init [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: skip_rst [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_MASK  0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_SHIFT 26
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: exit_in_sr [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_dly_cal [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_refresh [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_wr_dq [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: dq0_only [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_MASK  0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_mr_mpr [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_cal [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_MASK   0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_SHIFT  19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_en_cal [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_clocks [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_pair [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_steps [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_auto [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_ftm [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_phybist [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_byte [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_clocks [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_test [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_always [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_once [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_fast [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CALIB_STATUS - PHY VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_MASK 0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_fail [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_MASK 0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_SHIFT 29
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_done [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_rd_data_dly_error [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_read_en_error [26:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_MASK 0x07800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_error [22:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_MASK 0x00780000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_sel [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_total [11:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_MASK 0x00000ffc
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VDL_DQ_CALIB_STATUS - PHY DQ VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_total [25:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_MASK 0x03ff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_clocks [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_mode [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_WR_CHAN_CALIB_STATUS - PHY Write Channel VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_RD_EN_CALIB_STATUS - PHY Read Enable VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: low_vtt [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: high_vtt [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: error_reset [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_ctl_idle [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cs_idle [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cke_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error [18:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_MASK 0x0007fff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_low [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_high [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ready [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_DEFAULT 0x00ffffff
+
+/***************************************************************************
+ *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_DEFAULT 0x0003ffff
+
+/***************************************************************************
+ *VREF_DAC_CONTROL - VREF DAC Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK1_GT_INT [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK0_GT_INT [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_GT_INT [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: EXT_GT_INT [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_TESTOUT_MUX_CTL [16:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_MASK 0x00018000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TEST [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_MASK   0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_SHIFT  14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_MASK   0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_SHIFT  13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_MASK   0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_SHIFT  12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_MASK   0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_SHIFT  6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_DEFAULT 0x00000020
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_MASK   0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_SHIFT  0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_DEFAULT 0x00000020
+
+/***************************************************************************
+ *PHYBIST_CNTRL - PhyBist Control Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_error_sel [13:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_MASK 0x00003f00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved1 [07:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_MASK 0x000000e0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_SHIFT 5
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: bench_mode [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_dat_error [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_ctl_error [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: int_loopback [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHYBIST_SEED - PhyBist Seed Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_SEED :: seed [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_MASK       0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_DEFAULT    0x250e4af6
+
+/***************************************************************************
+ *PHYBIST_STATUS - PhyBist General Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_pass [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_pass [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_SHIFT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_done [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_done [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: ctl_errors [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_DQ_STATUS - PhyBist Per-Bit DQ Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_STATUS :: dat_errors [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_MASK 0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_MISC_STATUS - PhyBist Per-Bit DM and CK Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: ck_errors [07:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_MASK 0x000000f0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: dm_errors [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_SHIFT 0
+
+/***************************************************************************
+ *COMMAND_REG - DRAM Command Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_MASK   0xe0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_SHIFT  29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: mpr_mode [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_mpr_mode_MASK    0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_mpr_mode_SHIFT   28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_mpr_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved1 [27:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved1_MASK   0x0e000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved1_SHIFT  25
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: aux [24:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_MASK         0x01c00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_SHIFT        22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: we [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_MASK          0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_SHIFT         21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_DEFAULT       0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: cas [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_MASK         0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_SHIFT        20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ras [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_MASK         0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_SHIFT        19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ba [18:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_MASK          0x00070000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_SHIFT         16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_DEFAULT       0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_MASK          0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_DEFAULT       0x00000000
+
+/***************************************************************************
+ *MODE_REG0 - Mode Register 0
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG1 - Mode Register 1
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG2 - Mode Register 2
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG3 - Mode Register 3
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STANDBY_CONTROL - Standby Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_ready [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_exit_pin_en [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_active [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: armed [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_MASK   0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_SHIFT  15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: warmstart [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_ldo_volts [13:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_MASK 0x00003000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_skip_mrs [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_rst_n [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_cke [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: ldo_volts [08:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_MASK 0x00000180
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_DEFAULT 0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: skip_mrs [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: rst_n [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_MASK   0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_SHIFT  5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: cke [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_MASK     0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_SHIFT    4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_CONTROL - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: reserved0 [31:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_MASK 0xf0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_MASK       0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_SHIFT      16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_MASK  0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_MASK 0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_MASK     0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_SHIFT    12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_MASK      0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_SHIFT     11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_MASK      0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_SHIFT     8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_CONTROL2 - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_MASK     0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_SHIFT    20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_MASK       0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_SHIFT      17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_MASK       0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_SHIFT      12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_MASK      0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_SHIFT     7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_MASK       0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_DEFAULT    0x00000000
+
+/***************************************************************************
+ *STRAP_STATUS - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_MASK  0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_reg [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_MASK   0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_SHIFT  29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_memc [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_MASK  0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_MASK        0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_SHIFT       16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_MASK   0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_SHIFT  14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_MASK      0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_SHIFT     12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_MASK       0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_SHIFT      11
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_SHIFT 10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_MASK       0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_SHIFT      8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_MASK  0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_SHIFT 0
+
+/***************************************************************************
+ *STRAP_STATUS2 - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_MASK      0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_SHIFT     20
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_MASK        0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_SHIFT       17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_MASK        0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_SHIFT       12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_MASK       0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_SHIFT      7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_MASK        0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_SHIFT       0
+
+/***************************************************************************
+ *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl1 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl0 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl1 [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl0 [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DATAPATH_LOOPBACK - Datapth Loopback control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: xor_dm_rd_en [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: use_addr_ctl [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_ddr40_phy_word_lane_0_0.h b/include/linux/brcmstb/7360a0/bchp_ddr40_phy_word_lane_0_0.h
new file mode 100644
index 0000000..c7800bb
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_ddr40_phy_word_lane_0_0.h
@@ -0,0 +1,3334 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_ddr40_phy_word_lane_0_0.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:44a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_0_0 - DDR40 DDR40 word lane #0 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN 0x003b6200 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W 0x003b6204 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P 0x003b6208 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N 0x003b620c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W 0x003b6210 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W 0x003b6214 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W 0x003b6218 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W 0x003b621c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W 0x003b6220 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W 0x003b6224 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W 0x003b6228 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W 0x003b622c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W 0x003b6230 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003b6234 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003b6238 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003b623c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003b6240 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003b6244 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003b6248 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003b624c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003b6250 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003b6254 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003b6258 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003b625c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003b6260 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003b6264 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003b6268 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003b626c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003b6270 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003b6274 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W 0x003b62a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P 0x003b62a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N 0x003b62ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W 0x003b62b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W 0x003b62b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W 0x003b62b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W 0x003b62bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W 0x003b62c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W 0x003b62c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W 0x003b62c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W 0x003b62cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W 0x003b62d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003b62d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003b62d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003b62dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003b62e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003b62e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003b62e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003b62ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003b62f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003b62f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003b62f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003b62fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003b6300 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003b6304 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003b6308 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003b630c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003b6310 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003b6314 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x003b6328 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x003b632c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003b6330 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003b6334 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W 0x003b6338 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003b633c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x003b6348 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x003b634c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003b6350 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003b6354 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W 0x003b6358 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003b635c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY 0x003b6360 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL 0x003b6364 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0 0x003b6370 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1 0x003b6374 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2 0x003b6378 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3 0x003b637c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0 0x003b6380 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1 0x003b6384 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2 0x003b6388 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3 0x003b638c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS 0x003b6390 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR 0x003b6394 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL 0x003b63a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL 0x003b63a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE 0x003b63a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE 0x003b63ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ 0x003b63b0 /* PHYBIST mode VDL step select adjustment register */
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_RD_EN - Read Enable Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_DATA_DLY - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_MASK  0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: rd_data_dly [02:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_MASK 0x00000007
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_DEFAULT 0x00000001
+
+/***************************************************************************
+ *READ_CONTROL - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_MASK   0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_SHIFT  3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_enable [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_te_adj [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_le_adj [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status1 [07:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_MASK 0x000000f0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status0 [03:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_MASK 0x0000000f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: clear [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_MASK    0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_SHIFT   31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_SHIFT 24
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_MASK 0x00c00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_SHIFT 22
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_MASK 0x00300000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_SHIFT 20
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00080000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 19
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00040000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_SHIFT 18
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_MASK  0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_MASK  0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00008000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 15
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00004000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 14
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00002000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 13
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00001000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 12
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_MASK 0x00000008
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_MASK  0xfffff000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_SHIFT 12
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: no_dqs_rd [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_MASK  0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_MASK    0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_SHIFT   6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_MASK      0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_SHIFT     2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_DEFAULT   0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_MASK   0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_SHIFT  1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_MASK      0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_SHIFT     0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_DEFAULT   0x00000000
+
+/***************************************************************************
+ *CLOCK_PAD_DISABLE - Clock pad disable register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffc
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_SHIFT 2
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: long [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_MASK    0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_SHIFT   1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: mode [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHYBIST_VDL_ADJ - PHYBIST mode VDL step select adjustment register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_SHIFT 29
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq1_vdl_adj [28:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_MASK 0x1f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved1 [23:21] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_MASK 0x00e00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_SHIFT 21
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq0_vdl_adj [20:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_MASK 0x001f0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved2 [15:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_MASK 0x0000e000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_SHIFT 13
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs1_vdl_adj [12:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_MASK 0x00001f00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved3 [07:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_MASK 0x000000e0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_SHIFT 5
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs0_vdl_adj [04:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_MASK 0x0000001f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_ebi.h b/include/linux/brcmstb/7360a0/bchp_ebi.h
new file mode 100644
index 0000000..ef241e7
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_ebi.h
@@ -0,0 +1,1472 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_ebi.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:47a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EBI_H__
+#define BCHP_EBI_H__
+
+/***************************************************************************
+ *EBI - EBI Registers
+ ***************************************************************************/
+#define BCHP_EBI_CS_BASE_0                       0x00410800 /* EBI CS Base 0 Register */
+#define BCHP_EBI_CS_CONFIG_0                     0x00410804 /* EBI CS Config 0 Register */
+#define BCHP_EBI_CS_BASE_1                       0x00410808 /* EBI CS Base 1 Register */
+#define BCHP_EBI_CS_CONFIG_1                     0x0041080c /* EBI CS Config 1 Register */
+#define BCHP_EBI_CS_BASE_2                       0x00410810 /* EBI CS Base 2 Register */
+#define BCHP_EBI_CS_CONFIG_2                     0x00410814 /* EBI CS Config 2 Register */
+#define BCHP_EBI_CS_BASE_3                       0x00410818 /* EBI CS Base 3 Register */
+#define BCHP_EBI_CS_CONFIG_3                     0x0041081c /* EBI CS Config 3 Register */
+#define BCHP_EBI_CS_BASE_4                       0x00410820 /* EBI CS Base 4 Register */
+#define BCHP_EBI_CS_CONFIG_4                     0x00410824 /* EBI CS Config 4 Register */
+#define BCHP_EBI_BURST_CFG_0                     0x00410840 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_1                     0x00410844 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_2                     0x00410848 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_3                     0x0041084c /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_4                     0x00410850 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_ECR                             0x00410900 /* EBI Configuration Register */
+#define BCHP_EBI_CS_TRISTATE_CFG                 0x00410918 /* EBI CS Tristate Configuration Register */
+#define BCHP_EBI_TA_CFG                          0x0041091c /* EBI TA Configuration Register */
+#define BCHP_EBI_CS_SPI_SELECT                   0x00410920 /* SPI CS Select */
+#define BCHP_EBI_ARRAY_ADDRESS                   0x004109f0 /* EBI Data Array Address */
+
+/***************************************************************************
+ *CS_BASE_0 - EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_0 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_0_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT                         13
+
+/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_0_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_0 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_0_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_0_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_0 - EBI CS Config 0 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_0_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT                       0x00000001
+
+/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_0_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_0_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_0_le_SHIFT                              10
+
+/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_0_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_0_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT                       4
+
+/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_0_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT                        0x00000001
+
+/***************************************************************************
+ *CS_BASE_1 - EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_1 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_1_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_1_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_1 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_1_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_1_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_1_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_1 - EBI CS Config 1 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_1_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_1_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_1_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_1_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_1_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_1_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_1_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_2 - EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_2 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_2_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_2_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_2 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_2_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_2_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_2_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_2 - EBI CS Config 2 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_2_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_2_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_2_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_2_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_2_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_2_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_2_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_3 - EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_3 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_3_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_3_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_3 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_3_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_3_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_3_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_3 - EBI CS Config 3 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_3_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_3_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_3_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_3_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_3_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_3_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_3_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_4 - EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_4 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_4_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_4_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_4 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_4_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_4_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_4_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_4 - EBI CS Config 4 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_4_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_4_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_4_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_4_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_4_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_4_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_4_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_0_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_0_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_0 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_0_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_0_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_0_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_0_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_0_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_1_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_1_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_1 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_1_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_1_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_1_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_1_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_1_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_2_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_2_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_2 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_2_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_2_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_2_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_2_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_2_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_3_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_3_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_3 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_3_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_3_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_3_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_3_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_3_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_4_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_4_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_4 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_4_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_4_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_4_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_4_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_4_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *ECR - EBI Configuration Register
+ ***************************************************************************/
+/* EBI :: ECR :: reserved0 [31:28] */
+#define BCHP_EBI_ECR_reserved0_MASK                                0xf0000000
+#define BCHP_EBI_ECR_reserved0_SHIFT                               28
+
+/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK                            0x08000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT                           27
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT                         0x00000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only  1
+
+/* EBI :: ECR :: reserved1 [26:26] */
+#define BCHP_EBI_ECR_reserved1_MASK                                0x04000000
+#define BCHP_EBI_ECR_reserved1_SHIFT                               26
+
+/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK                          0x02000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT                         25
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT                       0x00000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10         0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00         1
+
+/* EBI :: ECR :: reserved2 [24:11] */
+#define BCHP_EBI_ECR_reserved2_MASK                                0x01fff800
+#define BCHP_EBI_ECR_reserved2_SHIFT                               11
+
+/* EBI :: ECR :: timeout_count [10:00] */
+#define BCHP_EBI_ECR_timeout_count_MASK                            0x000007ff
+#define BCHP_EBI_ECR_timeout_count_SHIFT                           0
+#define BCHP_EBI_ECR_timeout_count_DEFAULT                         0x00000400
+
+/***************************************************************************
+ *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
+ ***************************************************************************/
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK             0x80000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT            31
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK             0x40000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT            30
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK             0x20000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT            29
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK             0x10000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT            28
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK            0x08000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT           27
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK            0x04000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT           26
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK         0x02000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT        25
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK         0x01000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT        24
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:05] */
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK                    0x00ffffe0
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT                   5
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK             0x00000010
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT            4
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK             0x00000008
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT            3
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK             0x00000004
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT            2
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK             0x00000002
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT            1
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK             0x00000001
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT            0
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TA_CFG - EBI TA Configuration Register
+ ***************************************************************************/
+/* EBI :: TA_CFG :: reserved0 [31:04] */
+#define BCHP_EBI_TA_CFG_reserved0_MASK                             0xfffffff0
+#define BCHP_EBI_TA_CFG_reserved0_SHIFT                            4
+
+/* EBI :: TA_CFG :: use_ta3 [03:03] */
+#define BCHP_EBI_TA_CFG_use_ta3_MASK                               0x00000008
+#define BCHP_EBI_TA_CFG_use_ta3_SHIFT                              3
+#define BCHP_EBI_TA_CFG_use_ta3_DEFAULT                            0x00000001
+
+/* EBI :: TA_CFG :: use_ta2 [02:02] */
+#define BCHP_EBI_TA_CFG_use_ta2_MASK                               0x00000004
+#define BCHP_EBI_TA_CFG_use_ta2_SHIFT                              2
+#define BCHP_EBI_TA_CFG_use_ta2_DEFAULT                            0x00000000
+
+/* EBI :: TA_CFG :: use_ta1 [01:01] */
+#define BCHP_EBI_TA_CFG_use_ta1_MASK                               0x00000002
+#define BCHP_EBI_TA_CFG_use_ta1_SHIFT                              1
+#define BCHP_EBI_TA_CFG_use_ta1_DEFAULT                            0x00000001
+
+/* EBI :: TA_CFG :: reserved1 [00:00] */
+#define BCHP_EBI_TA_CFG_reserved1_MASK                             0x00000001
+#define BCHP_EBI_TA_CFG_reserved1_SHIFT                            0
+
+/***************************************************************************
+ *CS_SPI_SELECT - SPI CS Select
+ ***************************************************************************/
+/* EBI :: CS_SPI_SELECT :: reserved0 [31:16] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK                      0xffff0000
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT                     16
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_7_USES_SPI [15:15] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_MASK              0x00008000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_SHIFT             15
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK              0x00004000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT             14
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK              0x00002000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT             13
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK              0x00001000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT             12
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK              0x00000800
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT             11
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK              0x00000400
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT             10
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK              0x00000200
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT             9
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK              0x00000100
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT             8
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_7_SEL [07:07] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_MASK               0x00000080
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_SHIFT              7
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK               0x00000040
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT              6
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK               0x00000020
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT              5
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK               0x00000010
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT              4
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK               0x00000008
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT              3
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK               0x00000004
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT              2
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK               0x00000002
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT              1
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK               0x00000001
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT              0
+
+/***************************************************************************
+ *ARRAY_ADDRESS - EBI Data Array Address
+ ***************************************************************************/
+/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK                        0xfffffe00
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT                       9
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT                     0x00000000
+
+/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK                      0x000001f8
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT                     3
+
+/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK                         0x00000007
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT                        0
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE                            0x00410a00
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_START                           0
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_END                             127
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE                    32
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+/* EBI :: DATA_ARRAYi :: WORD [31:00] */
+#define BCHP_EBI_DATA_ARRAYi_WORD_MASK                             0xffffffff
+#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT                            0
+
+
+#endif /* #ifndef BCHP_EBI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_hif_cpu_intr1.h b/include/linux/brcmstb/7360a0/bchp_hif_cpu_intr1.h
new file mode 100644
index 0000000..d2b8491
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_hif_cpu_intr1.h
@@ -0,0 +1,2019 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_hif_cpu_intr1.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:55a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_INTR1_H__
+#define BCHP_HIF_CPU_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_INTR1 - HIF CPU Thread Processor 0 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS        0x00411400 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS        0x00411404 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS        0x00411408 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS   0x0041140c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS   0x00411410 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS   0x00411414 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET      0x00411418 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET      0x0041141c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET      0x00411420 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR    0x00411424 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR    0x00411428 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR    0x0041142c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK    0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT   31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK        0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT       30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK    0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT   29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_MASK       0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_SHIFT      28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_DEFAULT    0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK  0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK  0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_MASK        0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_SHIFT       23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK     0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT    7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK     0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT    6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK     0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT    5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK     0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT    4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK     0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT    3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK     0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT    2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK        0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT       1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK        0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT       0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK    0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT   28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK    0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT   27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK     0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT    26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK   0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT  24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK    0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT   22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_MASK   0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_SHIFT  20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK     0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT    18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK    0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT   17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK        0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT       16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_MASK   0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_SHIFT  14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_MASK   0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_SHIFT  13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_MASK   0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_SHIFT  12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_MASK   0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_SHIFT  11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_MASK  0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_MASK  0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK      0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT     5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT   0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK    0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT   4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_MASK     0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_SHIFT    2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_MASK       0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_SHIFT      1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_DEFAULT    0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_MASK       0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_SHIFT      0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_DEFAULT    0x00000000
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_24_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_24_CPU_INTR_MASK   0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_24_CPU_INTR_SHIFT  31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_24_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_23_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_23_CPU_INTR_MASK   0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_23_CPU_INTR_SHIFT  30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_23_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_22_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_22_CPU_INTR_MASK   0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_22_CPU_INTR_SHIFT  29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_22_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_21_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_MASK   0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_SHIFT  28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_20_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_20_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_20_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_20_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_19_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_19_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_19_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_19_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_18_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_MASK   0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_SHIFT  25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_17_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_MASK   0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_SHIFT  24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: RFM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_RFM_CPU_INTR_MASK        0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_RFM_CPU_INTR_SHIFT       23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_RFM_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SATA_AHCI_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_AHCI_CPU_INTR_MASK  0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_AHCI_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SATA_GRB_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_GRB_CPU_INTR_MASK   0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_GRB_CPU_INTR_SHIFT  21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_MASK     0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_SHIFT    20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SDIO0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_MASK    0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_SHIFT   18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK    0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT   16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK    0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT   15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK   0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT  14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK    0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT   12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK     0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT    11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK        0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT       10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_MASK   0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_SHIFT  9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_MASK   0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_SHIFT  8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK   0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT  30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_MASK   0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_SHIFT  23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK   0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT  16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_24_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_24_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_24_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_24_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_23_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_23_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_23_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_23_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_22_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_22_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_22_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_22_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_21_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_20_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_20_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_20_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_20_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_19_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_19_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_19_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_19_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_18_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_17_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: RFM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_RFM_CPU_INTR_MASK   0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_RFM_CPU_INTR_SHIFT  23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_RFM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SATA_AHCI_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_AHCI_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SATA_GRB_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_GRB_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_GRB_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SDIO0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK   0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT  10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK      0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT     30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_MASK     0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_SHIFT    28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_DEFAULT  0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_MASK      0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_SHIFT     23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK      0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT     1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK      0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT     0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK  0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK  0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK   0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT  18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK  0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK      0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT     16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK    0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT   5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK  0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_MASK     0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_SHIFT    1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_DEFAULT  0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_MASK     0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_SHIFT    0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_DEFAULT  0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_24_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_24_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_24_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_24_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_23_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_23_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_23_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_23_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_22_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_22_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_22_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_22_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_21_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_20_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_20_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_20_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_20_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_19_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_19_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_19_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_19_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_18_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_17_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: RFM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_RFM_CPU_INTR_MASK      0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_RFM_CPU_INTR_SHIFT     23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_RFM_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SATA_AHCI_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_AHCI_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_AHCI_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SATA_GRB_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_GRB_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_GRB_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_MASK   0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_SHIFT  20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SDIO0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_MASK  0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK  0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK  0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK  0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK   0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT  11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK      0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT     10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_MASK   0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_SHIFT  28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK    0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT   16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK  0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_24_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_24_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_24_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_24_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_23_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_23_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_23_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_23_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_22_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_22_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_22_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_22_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_21_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_20_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_20_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_20_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_20_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_19_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_19_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_19_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_19_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_18_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_17_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: RFM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_RFM_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_RFM_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_RFM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SATA_AHCI_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_AHCI_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_AHCI_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SATA_GRB_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_GRB_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_GRB_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SDIO0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK    0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT   10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+#endif /* #ifndef BCHP_HIF_CPU_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_hif_intr2.h b/include/linux/brcmstb/7360a0/bchp_hif_intr2.h
new file mode 100644
index 0000000..89a2bf1
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_hif_intr2.h
@@ -0,0 +1,975 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_hif_intr2.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:56a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_INTR2_H__
+#define BCHP_HIF_INTR2_H__
+
+/***************************************************************************
+ *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_INTR2_CPU_STATUS                0x00411000 /* CPU interrupt Status Register */
+#define BCHP_HIF_INTR2_CPU_SET                   0x00411004 /* CPU interrupt Set Register */
+#define BCHP_HIF_INTR2_CPU_CLEAR                 0x00411008 /* CPU interrupt Clear Register */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS           0x0041100c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_CPU_MASK_SET              0x00411010 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR            0x00411014 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_INTR2_PCI_STATUS                0x00411018 /* PCI interrupt Status Register */
+#define BCHP_HIF_INTR2_PCI_SET                   0x0041101c /* PCI interrupt Set Register */
+#define BCHP_HIF_INTR2_PCI_CLEAR                 0x00411020 /* PCI interrupt Clear Register */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS           0x00411024 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_PCI_MASK_SET              0x00411028 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR            0x0041102c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK                   0x0000fffe
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_MASK              0x00080000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_SHIFT             19
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK                      0x0000fffe
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: CPU_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_MASK            0x00080000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_SHIFT           19
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK                    0x0000fffe
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK              0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_MASK         0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_SHIFT        19
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK                 0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_MASK       0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_SHIFT      19
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK               0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK                   0x0000fffe
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_MASK              0x00080000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_SHIFT             19
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK                      0x0000fffe
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: PCI_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_MASK            0x00080000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_SHIFT           19
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK                    0x0000fffe
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK              0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_MASK         0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_SHIFT        19
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK                 0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_MASK       0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_SHIFT      19
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK               0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  0x00000001
+
+#endif /* #ifndef BCHP_HIF_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_hif_mspi.h b/include/linux/brcmstb/7360a0/bchp_hif_mspi.h
new file mode 100644
index 0000000..65e2169
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_hif_mspi.h
@@ -0,0 +1,1214 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_hif_mspi.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:56a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_MSPI_H__
+#define BCHP_HIF_MSPI_H__
+
+/***************************************************************************
+ *HIF_MSPI - Public MSPI Registers
+ ***************************************************************************/
+#define BCHP_HIF_MSPI_SPCR0_LSB                  0x00413200 /* SPCR0_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR0_MSB                  0x00413204 /* SPCR0_MSB Register */
+#define BCHP_HIF_MSPI_SPCR1_LSB                  0x00413208 /* SPCR1_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR1_MSB                  0x0041320c /* SPCR1_MSB REGISTER */
+#define BCHP_HIF_MSPI_NEWQP                      0x00413210 /* NEWQP REGISTER */
+#define BCHP_HIF_MSPI_ENDQP                      0x00413214 /* ENDQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR2                      0x00413218 /* SPCR2 REGISTER */
+#define BCHP_HIF_MSPI_MSPI_STATUS                0x00413220 /* MSPI STATUS REGISTER */
+#define BCHP_HIF_MSPI_CPTQP                      0x00413224 /* CPTQP REGISTER */
+#define BCHP_HIF_MSPI_TXRAM00                    0x00413240 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM01                    0x00413244 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM02                    0x00413248 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM03                    0x0041324c /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM04                    0x00413250 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM05                    0x00413254 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM06                    0x00413258 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM07                    0x0041325c /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM08                    0x00413260 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM09                    0x00413264 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM10                    0x00413268 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM11                    0x0041326c /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM12                    0x00413270 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM13                    0x00413274 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM14                    0x00413278 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM15                    0x0041327c /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM16                    0x00413280 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM17                    0x00413284 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM18                    0x00413288 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM19                    0x0041328c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM20                    0x00413290 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM21                    0x00413294 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM22                    0x00413298 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM23                    0x0041329c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM24                    0x004132a0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM25                    0x004132a4 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM26                    0x004132a8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM27                    0x004132ac /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM28                    0x004132b0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM29                    0x004132b4 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM30                    0x004132b8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_TXRAM31                    0x004132bc /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM00                    0x004132c0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM01                    0x004132c4 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM02                    0x004132c8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM03                    0x004132cc /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM04                    0x004132d0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM05                    0x004132d4 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM06                    0x004132d8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM07                    0x004132dc /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM08                    0x004132e0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM09                    0x004132e4 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM10                    0x004132e8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM11                    0x004132ec /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM12                    0x004132f0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM13                    0x004132f4 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM14                    0x004132f8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM15                    0x004132fc /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM16                    0x00413300 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM17                    0x00413304 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM18                    0x00413308 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM19                    0x0041330c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM20                    0x00413310 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM21                    0x00413314 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM22                    0x00413318 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM23                    0x0041331c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM24                    0x00413320 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM25                    0x00413324 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM26                    0x00413328 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM27                    0x0041332c /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM28                    0x00413330 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM29                    0x00413334 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM30                    0x00413338 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM31                    0x0041333c /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_CDRAM00                    0x00413340 /* 8-bit command (queue pointer = 0) */
+#define BCHP_HIF_MSPI_CDRAM01                    0x00413344 /* 8-bit command (queue pointer = 1) */
+#define BCHP_HIF_MSPI_CDRAM02                    0x00413348 /* 8-bit command (queue pointer = 2) */
+#define BCHP_HIF_MSPI_CDRAM03                    0x0041334c /* 8-bit command (queue pointer = 3) */
+#define BCHP_HIF_MSPI_CDRAM04                    0x00413350 /* 8-bit command (queue pointer = 4) */
+#define BCHP_HIF_MSPI_CDRAM05                    0x00413354 /* 8-bit command (queue pointer = 5) */
+#define BCHP_HIF_MSPI_CDRAM06                    0x00413358 /* 8-bit command (queue pointer = 6) */
+#define BCHP_HIF_MSPI_CDRAM07                    0x0041335c /* 8-bit command (queue pointer = 7) */
+#define BCHP_HIF_MSPI_CDRAM08                    0x00413360 /* 8-bit command (queue pointer = 8) */
+#define BCHP_HIF_MSPI_CDRAM09                    0x00413364 /* 8-bit command (queue pointer = 9) */
+#define BCHP_HIF_MSPI_CDRAM10                    0x00413368 /* 8-bit command (queue pointer = a) */
+#define BCHP_HIF_MSPI_CDRAM11                    0x0041336c /* 8-bit command (queue pointer = b) */
+#define BCHP_HIF_MSPI_CDRAM12                    0x00413370 /* 8-bit command (queue pointer = c) */
+#define BCHP_HIF_MSPI_CDRAM13                    0x00413374 /* 8-bit command (queue pointer = d) */
+#define BCHP_HIF_MSPI_CDRAM14                    0x00413378 /* 8-bit command (queue pointer = e) */
+#define BCHP_HIF_MSPI_CDRAM15                    0x0041337c /* 8-bit command (queue pointer = f) */
+#define BCHP_HIF_MSPI_WRITE_LOCK                 0x00413380 /* Control bit to lock group of write commands */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN          0x00413384 /* Debug bit to mask the generation of flush signals from Mspi */
+
+/***************************************************************************
+ *SPCR0_LSB - SPCR0_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK                          0x000000ff
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR0_MSB - SPCR0_MSB Register
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_MSB :: MSTR [07:07] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_MASK                          0x00000080
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_SHIFT                         7
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_DEFAULT                       0x00000001
+
+/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [06:06] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK               0x00000040
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT              6
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT            0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: BitS [05:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_MASK                          0x0000003c
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_SHIFT                         2
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_DEFAULT                       0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK                          0x00000002
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT                         1
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT                       0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK                          0x00000001
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR1_LSB - SPCR1_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT                          0
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *SPCR1_MSB - SPCR1_MSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK                        0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT                       0
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *NEWQP - NEWQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: NEWQP :: newqp [03:00] */
+#define BCHP_HIF_MSPI_NEWQP_newqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT                            0
+#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *ENDQP - ENDQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: ENDQP :: endqp [03:00] */
+#define BCHP_HIF_MSPI_ENDQP_endqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT                            0
+#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *SPCR2 - SPCR2 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK                         0xffffff00
+#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT                        8
+
+/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK                    0x00000080
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT                   7
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT                 0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spe [06:06] */
+#define BCHP_HIF_MSPI_SPCR2_spe_MASK                               0x00000040
+#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT                              6
+#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
+#define BCHP_HIF_MSPI_SPCR2_spifie_MASK                            0x00000020
+#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT                           5
+#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT                         0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wren [04:04] */
+#define BCHP_HIF_MSPI_SPCR2_wren_MASK                              0x00000010
+#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT                             4
+#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
+#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK                              0x00000008
+#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT                             3
+#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
+#define BCHP_HIF_MSPI_SPCR2_loopq_MASK                             0x00000004
+#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT                            2
+#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT                          0x00000000
+
+/* HIF_MSPI :: SPCR2 :: hie [01:01] */
+#define BCHP_HIF_MSPI_SPCR2_hie_MASK                               0x00000002
+#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT                              1
+#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: halt [00:00] */
+#define BCHP_HIF_MSPI_SPCR2_halt_MASK                              0x00000001
+#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT                             0
+#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *MSPI_STATUS - MSPI STATUS REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK                   0xfffffffc
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT                  2
+
+/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK                       0x00000002
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT                      1
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT                    0x00000000
+
+/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK                        0x00000001
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT                       0
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *CPTQP - CPTQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
+#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT                            0
+#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *TXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM00_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM01_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM02_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM03_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM04_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM05_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM06_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM07_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM08_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM09_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM10_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM11_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM12_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM13_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM14_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM15_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM16_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM17_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM18_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM19_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM20_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM21_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM22_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM23_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM24_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM25_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM26_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM27_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM28_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM29_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM30_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM31_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM00 - 8-bit command (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM00 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM01 - 8-bit command (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM01 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM02 - 8-bit command (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM02 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM03 - 8-bit command (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM03 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM04 - 8-bit command (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM04 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM05 - 8-bit command (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM05 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM06 - 8-bit command (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM06 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM07 - 8-bit command (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM07 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM08 - 8-bit command (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM08 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM09 - 8-bit command (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM09 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM10 - 8-bit command (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM10 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM11 - 8-bit command (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM11 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM12 - 8-bit command (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM12 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM13 - 8-bit command (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM13 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM14 - 8-bit command (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM14 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM15 - 8-bit command (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM15 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT                          0
+
+/***************************************************************************
+ *WRITE_LOCK - Control bit to lock group of write commands
+ ***************************************************************************/
+/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK                    0xfffffffe
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT                   1
+
+/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK                    0x00000001
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT                   0
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
+ ***************************************************************************/
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK             0xfffffffe
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT            1
+
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK       0x00000001
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT      0
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT    0x00000000
+
+#endif /* #ifndef BCHP_HIF_MSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/7360a0/bchp_hif_spi_intr2.h
new file mode 100644
index 0000000..dabf442
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_hif_spi_intr2.h
@@ -0,0 +1,567 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_hif_spi_intr2.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:56a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_SPI_INTR2_H__
+#define BCHP_HIF_SPI_INTR2_H__
+
+/***************************************************************************
+ *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
+ ***************************************************************************/
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS            0x00411d00 /* CPU interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_SET               0x00411d04 /* CPU interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR             0x00411d08 /* CPU interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS       0x00411d0c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET          0x00411d10 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR        0x00411d14 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS            0x00411d18 /* PCI interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_SET               0x00411d1c /* PCI interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR             0x00411d20 /* PCI interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS       0x00411d24 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET          0x00411d28 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR        0x00411d2c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_hif_top_ctrl.h b/include/linux/brcmstb/7360a0/bchp_hif_top_ctrl.h
new file mode 100644
index 0000000..855a502
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_hif_top_ctrl.h
@@ -0,0 +1,530 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_hif_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:57a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_TOP_CTRL_H__
+#define BCHP_HIF_TOP_CTRL_H__
+
+/***************************************************************************
+ *HIF_TOP_CTRL - HIF Top Control Registers
+ ***************************************************************************/
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2               0x00412418 /* HIF Power Management Control Register:used to control SDIO_0 (CARD) */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL          0x00412400 /* External IRQ Active Level Control Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0               0x00412404 /* HIF Power Management Control0 Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1               0x00412408 /* HIF Power Management Control1 Register */
+#define BCHP_HIF_TOP_CTRL_SCRATCH                0x0041240c /* HIF Scratch Register */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE             0x00412410 /* HIF Decoded Flash Type */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL            0x00412414 /* SPI test port select register */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL               0x0041241c /* HIF HIF_CTRL Register */
+
+/***************************************************************************
+ *PM_CTRL2 - HIF Power Management Control Register:used to control SDIO_0 (CARD)
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved0 [31:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_MASK                  0xff000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_SHIFT                 24
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_MASK 0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_SHIFT 22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_MASK 0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_SHIFT 20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_IN_DRIVE_INACTIVE [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_IN_DRIVE_INACTIVE [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_MASK 0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_SHIFT 16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved1 [15:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_MASK                  0x0000f000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_VOLTAGE_PM_OUT_CTRL [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_LOW    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_HIGH   2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_POWER_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_MASK     0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_SHIFT    8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_DEFAULT  0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_LOW      1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_HIGH     2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_LED_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_MASK       0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_SHIFT      6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_MASK      0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_MASK       0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_SHIFT      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_Tristate   3
+
+/***************************************************************************
+ *EXT_IRQ_LEVEL - External IRQ Active Level Control Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: reserved0 [31:15] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_MASK             0xffff8000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_SHIFT            15
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_14_level [14:14] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_MASK      0x00004000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_SHIFT     14
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_13_level [13:13] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_MASK      0x00002000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_SHIFT     13
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_12_level [12:12] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_MASK      0x00001000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_SHIFT     12
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_11_level [11:11] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_MASK      0x00000800
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_SHIFT     11
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_10_level [10:10] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_MASK      0x00000400
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_SHIFT     10
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_09_level [09:09] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_MASK      0x00000200
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_SHIFT     9
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_08_level [08:08] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_MASK      0x00000100
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_SHIFT     8
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_07_level [07:07] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_MASK      0x00000080
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_SHIFT     7
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_06_level [06:06] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_MASK      0x00000040
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_SHIFT     6
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_05_level [05:05] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_MASK      0x00000020
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_SHIFT     5
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_04_level [04:04] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_MASK      0x00000010
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_03_level [03:03] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_MASK      0x00000008
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_SHIFT     3
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_02_level [02:02] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_MASK      0x00000004
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_SHIFT     2
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_01_level [01:01] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_MASK      0x00000002
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_SHIFT     1
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_00_level [00:00] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_MASK      0x00000001
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_SHIFT     0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_HIGH      1
+
+/***************************************************************************
+ *PM_CTRL0 - HIF Power Management Control0 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_PM_IN_DRIVE_INACTIVE [31:30] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_MASK   0xc0000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_SHIFT  30
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_IN_DRIVE_INACTIVE [29:28] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x30000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 28
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: reserved0 [27:26] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_reserved0_MASK                  0x0c000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_reserved0_SHIFT                 26
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_DATA_PM_OUT_CTRL [25:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_MASK       0x03000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_SHIFT      24
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_ADDR_PM_OUT_CTRL [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_MASK       0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_SHIFT      22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_CTRL_PM_OUT_CTRL [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_MASK       0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_SHIFT      20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_OUT_CTRL [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_MASK      0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_SHIFT     18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_CTRL_PM_OUT_CTRL [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_MASK      0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_SHIFT     16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS7 [15:14] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_MASK            0x0000c000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_SHIFT           14
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS6 [13:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_MASK            0x00003000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_SHIFT           12
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS5 [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_MASK            0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_SHIFT           10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS4 [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_MASK            0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_SHIFT           8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS3 [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_MASK            0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_SHIFT           6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS2 [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_MASK            0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_SHIFT           4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS1 [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_MASK            0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_SHIFT           2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS0 [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_MASK            0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_SHIFT           0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_Tristate        3
+
+/***************************************************************************
+ *PM_CTRL1 - HIF Power Management Control1 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL1 :: reserved0 [31:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_MASK                  0xfffff000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_PM_IN_DRIVE_INACTIVE [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_WPB_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_MASK        0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_SHIFT       8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_DEFAULT     0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_Tristate    3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_HOLDB_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_MASK      0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_SHIFT     6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MISO_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_MASK       0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_SHIFT      4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MOSI_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_MASK        0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_SHIFT       0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_DEFAULT     0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_Tristate    3
+
+/***************************************************************************
+ *SCRATCH - HIF Scratch Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_MASK                 0xffffffff
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_SHIFT                0
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *FLASH_TYPE - HIF Decoded Flash Type
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: FLASH_TYPE :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_MASK                0xfffffff8
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_SHIFT               3
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: InvalidStrap [02:02] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_MASK             0x00000004
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_SHIFT            2
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_DEFAULT          0x00000000
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: FLASH_TYPE [01:00] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_MASK               0x00000003
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SHIFT              0
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_ParallelNOR        0
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_Nand               1
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SerialNOR          2
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_UnSupport          3
+
+/***************************************************************************
+ *SPI_DBG_SEL - SPI test port select register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_MASK               0xfffffff8
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_SHIFT              3
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: DISABLE_MSPI_FLUSH [02:02] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_MASK      0x00000004
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_SHIFT     2
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_DEFAULT   0x00000000
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SPI_RBUS_TIMER_EN [01:01] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_MASK       0x00000002
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_SHIFT      1
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_DEFAULT    0x00000000
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SPI_TP_SEL [00:00] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_TP_SEL_MASK              0x00000001
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_TP_SEL_SHIFT             0
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_TP_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *HIF_CTRL - HIF HIF_CTRL Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: HIF_CTRL :: reserved0 [31:01] */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_reserved0_SHIFT                 1
+
+/* HIF_TOP_CTRL :: HIF_CTRL :: ENABLE_FULL_USE_OF_EBI [00:00] */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_MASK     0x00000001
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_SHIFT    0
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_DEFAULT  0x00000000
+
+#endif /* #ifndef BCHP_HIF_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_irq0.h b/include/linux/brcmstb/7360a0/bchp_irq0.h
new file mode 100644
index 0000000..15148a3
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_irq0.h
@@ -0,0 +1,217 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_irq0.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:59a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ0_H__
+#define BCHP_IRQ0_H__
+
+/***************************************************************************
+ *IRQ0 - Level 2 CPU Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ0_IRQEN                          0x00406600 /* Interrupt Enable */
+#define BCHP_IRQ0_IRQSTAT                        0x00406604 /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ0 :: IRQEN :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQEN_reserved0_MASK                             0xf8000000
+#define BCHP_IRQ0_IRQEN_reserved0_SHIFT                            27
+
+/* IRQ0 :: IRQEN :: iicc_irqen [26:26] */
+#define BCHP_IRQ0_IRQEN_iicc_irqen_MASK                            0x04000000
+#define BCHP_IRQ0_IRQEN_iicc_irqen_SHIFT                           26
+#define BCHP_IRQ0_IRQEN_iicc_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: iicb_irqen [25:25] */
+#define BCHP_IRQ0_IRQEN_iicb_irqen_MASK                            0x02000000
+#define BCHP_IRQ0_IRQEN_iicb_irqen_SHIFT                           25
+#define BCHP_IRQ0_IRQEN_iicb_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: iica_irqen [24:24] */
+#define BCHP_IRQ0_IRQEN_iica_irqen_MASK                            0x01000000
+#define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT                           24
+#define BCHP_IRQ0_IRQEN_iica_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQEN_reserved1_MASK                             0x00f80000
+#define BCHP_IRQ0_IRQEN_reserved1_SHIFT                            19
+
+/* IRQ0 :: IRQEN :: uartc_irqen [18:18] */
+#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK                           0x00040000
+#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT                          18
+#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uartb_irqen [17:17] */
+#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK                           0x00020000
+#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT                          17
+#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uarta_irqen [16:16] */
+#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK                           0x00010000
+#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT                          16
+#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQEN_reserved2_MASK                             0x0000fc00
+#define BCHP_IRQ0_IRQEN_reserved2_SHIFT                            10
+
+/* IRQ0 :: IRQEN :: uc_irqen [09:09] */
+#define BCHP_IRQ0_IRQEN_uc_irqen_MASK                              0x00000200
+#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT                             9
+#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQEN_reserved3_MASK                             0x00000180
+#define BCHP_IRQ0_IRQEN_reserved3_SHIFT                            7
+
+/* IRQ0 :: IRQEN :: gio_irqen [06:06] */
+#define BCHP_IRQ0_IRQEN_gio_irqen_MASK                             0x00000040
+#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT                            6
+#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQEN :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQEN_reserved4_MASK                             0x00000020
+#define BCHP_IRQ0_IRQEN_reserved4_SHIFT                            5
+
+/* IRQ0 :: IRQEN :: ua_irqen [04:04] */
+#define BCHP_IRQ0_IRQEN_ua_irqen_MASK                              0x00000010
+#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT                             4
+#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: ub_irqen [03:03] */
+#define BCHP_IRQ0_IRQEN_ub_irqen_MASK                              0x00000008
+#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT                             3
+#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: irb_irqen [02:02] */
+#define BCHP_IRQ0_IRQEN_irb_irqen_MASK                             0x00000004
+#define BCHP_IRQ0_IRQEN_irb_irqen_SHIFT                            2
+#define BCHP_IRQ0_IRQEN_irb_irqen_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQEN :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQEN_reserved5_MASK                             0x00000003
+#define BCHP_IRQ0_IRQEN_reserved5_SHIFT                            0
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ0 :: IRQSTAT :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQSTAT_reserved0_MASK                           0xf8000000
+#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT                          27
+
+/* IRQ0 :: IRQSTAT :: iiccirq [26:26] */
+#define BCHP_IRQ0_IRQSTAT_iiccirq_MASK                             0x04000000
+#define BCHP_IRQ0_IRQSTAT_iiccirq_SHIFT                            26
+#define BCHP_IRQ0_IRQSTAT_iiccirq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: iicbirq [25:25] */
+#define BCHP_IRQ0_IRQSTAT_iicbirq_MASK                             0x02000000
+#define BCHP_IRQ0_IRQSTAT_iicbirq_SHIFT                            25
+#define BCHP_IRQ0_IRQSTAT_iicbirq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: iicairq [24:24] */
+#define BCHP_IRQ0_IRQSTAT_iicairq_MASK                             0x01000000
+#define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT                            24
+#define BCHP_IRQ0_IRQSTAT_iicairq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQSTAT_reserved1_MASK                           0x00f80000
+#define BCHP_IRQ0_IRQSTAT_reserved1_SHIFT                          19
+
+/* IRQ0 :: IRQSTAT :: uartc_irq [18:18] */
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK                           0x00040000
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT                          18
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uartb_irq [17:17] */
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK                           0x00020000
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT                          17
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uarta_irq [16:16] */
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK                           0x00010000
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT                          16
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQSTAT_reserved2_MASK                           0x0000fc00
+#define BCHP_IRQ0_IRQSTAT_reserved2_SHIFT                          10
+
+/* IRQ0 :: IRQSTAT :: ucirq [09:09] */
+#define BCHP_IRQ0_IRQSTAT_ucirq_MASK                               0x00000200
+#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT                              9
+#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQSTAT_reserved3_MASK                           0x00000180
+#define BCHP_IRQ0_IRQSTAT_reserved3_SHIFT                          7
+
+/* IRQ0 :: IRQSTAT :: gioirq [06:06] */
+#define BCHP_IRQ0_IRQSTAT_gioirq_MASK                              0x00000040
+#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT                             6
+#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQSTAT_reserved4_MASK                           0x00000020
+#define BCHP_IRQ0_IRQSTAT_reserved4_SHIFT                          5
+
+/* IRQ0 :: IRQSTAT :: uairq [04:04] */
+#define BCHP_IRQ0_IRQSTAT_uairq_MASK                               0x00000010
+#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT                              4
+#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: ubirq [03:03] */
+#define BCHP_IRQ0_IRQSTAT_ubirq_MASK                               0x00000008
+#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT                              3
+#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: irbirq [02:02] */
+#define BCHP_IRQ0_IRQSTAT_irbirq_MASK                              0x00000004
+#define BCHP_IRQ0_IRQSTAT_irbirq_SHIFT                             2
+#define BCHP_IRQ0_IRQSTAT_irbirq_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQSTAT_reserved5_MASK                           0x00000003
+#define BCHP_IRQ0_IRQSTAT_reserved5_SHIFT                          0
+
+#endif /* #ifndef BCHP_IRQ0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_irq1.h b/include/linux/brcmstb/7360a0/bchp_irq1.h
new file mode 100644
index 0000000..a43a82a
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_irq1.h
@@ -0,0 +1,53 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug 16 11:01:23 2010
+ *                 MD5 Checksum         442d8de773a92e76786307c9f37b5c82
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_irq1.h $
+ * 
+ * Hydra_Software_Devel/2   8/16/10 12:17p pntruong
+ * SW7358-2: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ1_H__
+#define BCHP_IRQ1_H__
+
+/***************************************************************************
+ *IRQ1 - Level 2 PCI Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ1_IRQEN                          0x00406640 /* Interrupt Enable */
+#define BCHP_IRQ1_IRQSTAT                        0x00406644 /* Interrupt Status */
+
+#endif /* #ifndef BCHP_IRQ1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_mem_dma_0.h b/include/linux/brcmstb/7360a0/bchp_mem_dma_0.h
new file mode 100644
index 0000000..8c5d18b
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_mem_dma_0.h
@@ -0,0 +1,157 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_mem_dma_0.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:04p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEM_DMA_0_H__
+#define BCHP_MEM_DMA_0_H__
+
+/***************************************************************************
+ *MEM_DMA_0 - MEM_DMA_0 Registers
+ ***************************************************************************/
+#define BCHP_MEM_DMA_0_REVISION                  0x00374200 /* MEM_DMA REVISION */
+#define BCHP_MEM_DMA_0_FIRST_DESC                0x00374204 /* MEM_DMA First Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CTRL                      0x00374208 /* MEM_DMA Control Register */
+#define BCHP_MEM_DMA_0_WAKE_CTRL                 0x0037420c /* MEM_DMA Wake Control Register */
+#define BCHP_MEM_DMA_0_STATUS                    0x00374214 /* MEM_DMA Status Register */
+#define BCHP_MEM_DMA_0_CUR_DESC                  0x00374218 /* MEM_DMA Current Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CUR_BYTE                  0x0037421c /* MEM_DMA Current Byte Count Register */
+#define BCHP_MEM_DMA_0_SCRATCH                   0x00374224 /* MEM_DMA Scratch Register */
+
+/***************************************************************************
+ *REVISION - MEM_DMA REVISION
+ ***************************************************************************/
+/* MEM_DMA_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_0_REVISION_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_0_REVISION_reserved0_SHIFT                    16
+
+/* MEM_DMA_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_MASK                         0x0000ff00
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_SHIFT                        8
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_DEFAULT                      0x00000002
+
+/* MEM_DMA_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_MEM_DMA_0_REVISION_MINOR_MASK                         0x000000ff
+#define BCHP_MEM_DMA_0_REVISION_MINOR_SHIFT                        0
+#define BCHP_MEM_DMA_0_REVISION_MINOR_DEFAULT                      0x0000000a
+
+/***************************************************************************
+ *FIRST_DESC - MEM_DMA First Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: FIRST_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_MASK                        0xffffffff
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_SHIFT                       0
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *CTRL - MEM_DMA Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CTRL :: reserved0 [31:01] */
+#define BCHP_MEM_DMA_0_CTRL_reserved0_MASK                         0xfffffffe
+#define BCHP_MEM_DMA_0_CTRL_reserved0_SHIFT                        1
+
+/* MEM_DMA_0 :: CTRL :: RUN [00:00] */
+#define BCHP_MEM_DMA_0_CTRL_RUN_MASK                               0x00000001
+#define BCHP_MEM_DMA_0_CTRL_RUN_SHIFT                              0
+#define BCHP_MEM_DMA_0_CTRL_RUN_DEFAULT                            0x00000000
+
+/***************************************************************************
+ *WAKE_CTRL - MEM_DMA Wake Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: WAKE_CTRL :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_MASK                    0xfffffffc
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_SHIFT                   2
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE_MODE [01:01] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_MASK                    0x00000002
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_SHIFT                   1
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_DEFAULT                 0x00000000
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE [00:00] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MASK                         0x00000001
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_SHIFT                        0
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *STATUS - MEM_DMA Status Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: STATUS :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_MEM_DMA_0_STATUS_reserved0_SHIFT                      2
+
+/* MEM_DMA_0 :: STATUS :: DMA_STATUS [01:00] */
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_MASK                      0x00000003
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_SHIFT                     0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_DEFAULT                   0x00000000
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Idle                      0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Busy                      1
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Sleep                     2
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Reserved                  3
+
+/***************************************************************************
+ *CUR_DESC - MEM_DMA Current Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_MASK                          0xffffffff
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_SHIFT                         0
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *CUR_BYTE - MEM_DMA Current Byte Count Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_BYTE :: reserved0 [31:25] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_MASK                     0xfe000000
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_SHIFT                    25
+
+/* MEM_DMA_0 :: CUR_BYTE :: COUNT [24:00] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_MASK                         0x01ffffff
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_SHIFT                        0
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *SCRATCH - MEM_DMA Scratch Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_MASK                    0xffffffff
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_SHIFT                   0
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_DEFAULT                 0x00000000
+
+#endif /* #ifndef BCHP_MEM_DMA_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_memc_ddr_0.h b/include/linux/brcmstb/7360a0/bchp_memc_ddr_0.h
new file mode 100644
index 0000000..6c9890d
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_memc_ddr_0.h
@@ -0,0 +1,2665 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:25:00 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_memc_ddr_0.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:05p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR_0_H__
+#define BCHP_MEMC_DDR_0_H__
+
+/***************************************************************************
+ *MEMC_DDR_0 - Memory Controller Sequencer (DDR Param/Control) Registers 0
+ ***************************************************************************/
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG            0x003b2000 /* Memory Controller Mode-Configuration Register. */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL          0x003b2004 /* Dram iniitialization control */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS         0x003b2008 /* Dram iniitialization status */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0              0x003b200c /* Dram Mode0 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1              0x003b2010 /* Dram Mode1 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2              0x003b2014 /* Dram Mode2 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3              0x003b2018 /* Dram Mode3 register */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG               0x003b201c /* Precharge power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG              0x003b2020 /* Self-refresh power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SSPD_CMD                 0x003b2024 /* Software standby power down mode */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS        0x003b2028 /* Power down status */
+#define BCHP_MEMC_DDR_0_WARM_BOOT                0x003b202c /* Warm boot control registers */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0            0x003b2030 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1            0x003b2034 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2            0x003b2038 /* Read to Write & write to read timing register */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3            0x003b203c /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4            0x003b2040 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5            0x003b2044 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ         0x003b2048 /* Memory Controller Sequencer Enable */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT        0x003b204c /* Memory Controller , state machine timeout register. */
+#define BCHP_MEMC_DDR_0_BANK_STATUS              0x003b2050 /* Memory Controller, Bank Status Register. */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY           0x003b2054 /* Memory Controller, Tester Latency Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0               0x003b2058 /* Memory Controller, DATA_PINMAP_BYTE0_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1               0x003b205c /* Memory Controller, DATA_PINMAP_BYTE1_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2               0x003b2060 /* Memory Controller, DATA_PINMAP_BYTE2_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3               0x003b2064 /* Memory Controller, DATA_PINMAP_BYTE3_SEL Register. */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD   0x003b2068 /* Memory Controller, DDR3 DRAM reset Register. */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL             0x003b206c /* Statistics Control register */
+#define BCHP_MEMC_DDR_0_STAT_TIMER               0x003b2070 /* Statistics Timer */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP            0x003b2074 /* DRAM Idle_NOP Cycle Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP        0x003b2078 /* Maximum DRAM idle_NOP cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL             0x003b207c /* CAS Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL         0x003b2080 /* Maximum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL         0x003b2084 /* DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL 0x003b2088 /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL      0x003b208c /* Number of overall system memory read transactions. */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL     0x003b2090 /* Number of overall system memory write transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL       0x003b2094 /* Maximum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL       0x003b2098 /* Minimum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS  0x003b209c /* Service CAS Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS 0x003b20a0 /* Maximum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS 0x003b20a4 /* Minimum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY 0x003b20a8 /* Service Intra DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY 0x003b20ac /* Service Post DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES 0x003b20b0 /* Maximum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES 0x003b20b4 /* Minimum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ 0x003b20b8 /* Service Read Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE 0x003b20bc /* Service Write Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS 0x003b20c0 /* Maximum service Transaction count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS 0x003b20c4 /* Minimum service cycle Transaction register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY 0x003b20c8 /* Service Latency Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY 0x003b20cc /* Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY 0x003b20d0 /* Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x003b20d4 /* Absolute Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x003b20d8 /* Absolute Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH             0x003b20dc /* Total number of refreshes issuedr. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0        0x003b20e0 /* CAS cycle count register for client 0. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1        0x003b20e4 /* CAS cycle count register for client 1. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2        0x003b20e8 /* CAS cycle count register for client 2. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3        0x003b20ec /* CAS cycle count register for client 3. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4        0x003b20f0 /* CAS cycle count register for client 4. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5        0x003b20f4 /* CAS cycle count register for client 5. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6        0x003b20f8 /* CAS cycle count register for client 6. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7        0x003b20fc /* CAS cycle count register for client 7. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8        0x003b2100 /* CAS cycle count register for client 8. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9        0x003b2104 /* CAS cycle count register for client 9. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10       0x003b2108 /* CAS cycle count register for client 10. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11       0x003b210c /* CAS cycle count register for client 11. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12       0x003b2110 /* CAS cycle count register for client 12. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13       0x003b2114 /* CAS cycle count register for client 13. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14       0x003b2118 /* CAS cycle count register for client 14. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15       0x003b211c /* CAS cycle count register for client 15. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16       0x003b2120 /* CAS cycle count register for client 16. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17       0x003b2124 /* CAS cycle count register for client 17. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18       0x003b2128 /* CAS cycle count register for client 18. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19       0x003b212c /* CAS cycle count register for client 19. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20       0x003b2130 /* CAS cycle count register for client 20. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21       0x003b2134 /* CAS cycle count register for client 21. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22       0x003b2138 /* CAS cycle count register for client 22. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23       0x003b213c /* CAS cycle count register for client 23. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24       0x003b2140 /* CAS cycle count register for client 24. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25       0x003b2144 /* CAS cycle count register for client 25. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26       0x003b2148 /* CAS cycle count register for client 26. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27       0x003b214c /* CAS cycle count register for client 27. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28       0x003b2150 /* CAS cycle count register for client 28. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29       0x003b2154 /* CAS cycle count register for client 29. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30       0x003b2158 /* CAS cycle count register for client 30. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31       0x003b215c /* CAS cycle count register for client 31. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32       0x003b2160 /* CAS cycle count register for client 32. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33       0x003b2164 /* CAS cycle count register for client 33. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34       0x003b2168 /* CAS cycle count register for client 34. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35       0x003b216c /* CAS cycle count register for client 35. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36       0x003b2170 /* CAS cycle count register for client 36. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37       0x003b2174 /* CAS cycle count register for client 37. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38       0x003b2178 /* CAS cycle count register for client 38. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39       0x003b217c /* CAS cycle count register for client 39. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40       0x003b2180 /* CAS cycle count register for client 40. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41       0x003b2184 /* CAS cycle count register for client 41. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42       0x003b2188 /* CAS cycle count register for client 42. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43       0x003b218c /* CAS cycle count register for client 43. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44       0x003b2190 /* CAS cycle count register for client 44. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45       0x003b2194 /* CAS cycle count register for client 45. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46       0x003b2198 /* CAS cycle count register for client 46. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47       0x003b219c /* CAS cycle count register for client 47. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48       0x003b21a0 /* CAS cycle count register for client 48. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49       0x003b21a4 /* CAS cycle count register for client 49. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50       0x003b21a8 /* CAS cycle count register for client 50. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51       0x003b21ac /* CAS cycle count register for client 51. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52       0x003b21b0 /* CAS cycle count register for client 52. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53       0x003b21b4 /* CAS cycle count register for client 53. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54       0x003b21b8 /* CAS cycle count register for client 54. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55       0x003b21bc /* CAS cycle count register for client 55. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56       0x003b21c0 /* CAS cycle count register for client 56. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57       0x003b21c4 /* CAS cycle count register for client 57. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58       0x003b21c8 /* CAS cycle count register for client 58. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59       0x003b21cc /* CAS cycle count register for client 59. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60       0x003b21d0 /* CAS cycle count register for client 60. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61       0x003b21d4 /* CAS cycle count register for client 61. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62       0x003b21d8 /* CAS cycle count register for client 62. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63       0x003b21dc /* CAS cycle count register for client 63. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64       0x003b21e0 /* CAS cycle count register for client 64. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65       0x003b21e4 /* CAS cycle count register for client 65. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66       0x003b21e8 /* CAS cycle count register for client 66. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67       0x003b21ec /* CAS cycle count register for client 67. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68       0x003b21f0 /* CAS cycle count register for client 68. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69       0x003b21f4 /* CAS cycle count register for client 69. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70       0x003b21f8 /* CAS cycle count register for client 70. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71       0x003b21fc /* CAS cycle count register for client 71. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72       0x003b2200 /* CAS cycle count register for client 72. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73       0x003b2204 /* CAS cycle count register for client 73. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74       0x003b2208 /* CAS cycle count register for client 74. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75       0x003b220c /* CAS cycle count register for client 75. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76       0x003b2210 /* CAS cycle count register for client 76. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77       0x003b2214 /* CAS cycle count register for client 77. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78       0x003b2218 /* CAS cycle count register for client 78. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79       0x003b221c /* CAS cycle count register for client 79. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80       0x003b2220 /* CAS cycle count register for client 80. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81       0x003b2224 /* CAS cycle count register for client 81. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82       0x003b2228 /* CAS cycle count register for client 82. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83       0x003b222c /* CAS cycle count register for client 83. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84       0x003b2230 /* CAS cycle count register for client 84. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85       0x003b2234 /* CAS cycle count register for client 85. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86       0x003b2238 /* CAS cycle count register for client 86. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87       0x003b223c /* CAS cycle count register for client 87. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88       0x003b2240 /* CAS cycle count register for client 88. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89       0x003b2244 /* CAS cycle count register for client 89. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90       0x003b2248 /* CAS cycle count register for client 90. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91       0x003b224c /* CAS cycle count register for client 91. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92       0x003b2250 /* CAS cycle count register for client 92. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93       0x003b2254 /* CAS cycle count register for client 93. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94       0x003b2258 /* CAS cycle count register for client 94. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95       0x003b225c /* CAS cycle count register for client 95. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96       0x003b2260 /* CAS cycle count register for client 96. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97       0x003b2264 /* CAS cycle count register for client 97. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98       0x003b2268 /* CAS cycle count register for client 98. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99       0x003b226c /* CAS cycle count register for client 99. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100      0x003b2270 /* CAS cycle count register for client 100. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101      0x003b2274 /* CAS cycle count register for client 101. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102      0x003b2278 /* CAS cycle count register for client 102. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103      0x003b227c /* CAS cycle count register for client 103. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104      0x003b2280 /* CAS cycle count register for client 104. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105      0x003b2284 /* CAS cycle count register for client 105. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106      0x003b2288 /* CAS cycle count register for client 106. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107      0x003b228c /* CAS cycle count register for client 107. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108      0x003b2290 /* CAS cycle count register for client 108. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109      0x003b2294 /* CAS cycle count register for client 109. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110      0x003b2298 /* CAS cycle count register for client 110. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111      0x003b229c /* CAS cycle count register for client 111. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112      0x003b22a0 /* CAS cycle count register for client 112. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113      0x003b22a4 /* CAS cycle count register for client 113. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114      0x003b22a8 /* CAS cycle count register for client 114. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115      0x003b22ac /* CAS cycle count register for client 115. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116      0x003b22b0 /* CAS cycle count register for client 116. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117      0x003b22b4 /* CAS cycle count register for client 117. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118      0x003b22b8 /* CAS cycle count register for client 118. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119      0x003b22bc /* CAS cycle count register for client 119. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120      0x003b22c0 /* CAS cycle count register for client 120. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121      0x003b22c4 /* CAS cycle count register for client 121. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122      0x003b22c8 /* CAS cycle count register for client 122. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123      0x003b22cc /* CAS cycle count register for client 123. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124      0x003b22d0 /* CAS cycle count register for client 124. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125      0x003b22d4 /* CAS cycle count register for client 125. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126      0x003b22d8 /* CAS cycle count register for client 126. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127      0x003b22dc /* CAS cycle count register for client 127. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL         0x003b22e0 /* Minimum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL 0x003b22e4 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL 0x003b22e8 /* MEMSYS Auto Init Control. */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS  0x003b22ec /* MEMSYS Auto Init Status. */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE 0x003b22f0 /* PHY VDL calibrate override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE 0x003b22f4 /* SHIM PLL pndiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE 0x003b22f8 /* SHIM PLL mdiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY          0x003b22fc /* Dynamic VDL shmoo command delay. */
+
+/***************************************************************************
+ *CNTRLR_CONFIG - Memory Controller Mode-Configuration Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_MASK               0xfffffff8
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_SHIFT              3
+
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DEVICE_TECH [02:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_SHIFT            0
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_DEFAULT          0x00000003
+
+/***************************************************************************
+ *DRAM_INIT_CNTRL - Dram iniitialization control
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_MASK             0xfffffff8
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_SHIFT            3
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: BYPASS_PHY_INIT_RDY [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_MASK   0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_SHIFT  2
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR_TECH [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DEFAULT           0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR2              0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR3              1
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR3_INIT_MODE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_MASK        0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_SHIFT       0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *DRAM_INIT_STATUS - Dram iniitialization status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_SHIFT           0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_DEFAULT         0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_0 - Dram Mode0 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: PD_EXIT [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_MASK              0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_SHIFT             12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_DEFAULT         0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: CL [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_MASK                   0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_DEFAULT                0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BL [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_DEFAULT                0x00000002
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK        0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT       12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT     0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT         0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_MASK               0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_SHIFT              4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT            0x00000004
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_DEFAULT               0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_MASK                 0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_SHIFT                2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_DEFAULT              0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_MASK                   0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_1 - Dram Mode1 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DEFAULT             0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: RDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DQSB [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_MASK                 0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_SHIFT                10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_ENABLE               0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DISABLE              1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: OCD_CAL [09:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_MASK              0x00000380
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_SHIFT             7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_DEFAULT       0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: AL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_MASK                   0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DRV_IMP [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DISABLE            1
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT             0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_MASK             0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_SHIFT            10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK          0x00000200
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT         9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_MASK             0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT            7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT          0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE           1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK   0x00000020
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT  5
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_MASK                   0x00000018
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT       0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK   0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT  1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DISABLE            1
+
+/***************************************************************************
+ *DRAM_MODE_2 - Dram Mode2 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_1 [12:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_MASK             0x00001f00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: HT_SRF [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_ENABLE             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DISABLE            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_2 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_MASK             0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_SHIFT            4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: DCC_ENABLE [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_MASK           0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_SHIFT          3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DEFAULT        0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_ENABLE         1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DISABLE        0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_DEFAULT              0x00000000
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_MASK             0x00001800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_SHIFT            11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_MASK               0x00000600
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_SHIFT              9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT            0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT            0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT             6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_MASK                  0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_DEFAULT               0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_3 - Dram Mode3 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: unused_0 [15:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_MASK                  0x0000fff8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR2 :: unused_1 [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_SHIFT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_DEFAULT          0x00000000
+
+/* union - case DDR3 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_MASK                  0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_SHIFT                 2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_DEFAULT               0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_MASK              0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PPD_CONFIG - Precharge power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PPD_CONFIG :: reserved0 [31:13] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_MASK                  0xffffe000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_SHIFT                 13
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_EN [12:12] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_MASK                     0x00001000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_SHIFT                    12
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_DEFAULT                  0x00000000
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: INACT_COUNT [11:00] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_MASK                0x00000fff
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *SRPD_CONFIG - Self-refresh power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SRPD_CONFIG :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_MASK                 0xfffe0000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_SHIFT                17
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: SRPD_EN [16:16] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_MASK                   0x00010000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_SHIFT                  16
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_DEFAULT                0x00000000
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SSPD_CMD - Software standby power down mode
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SSPD_CMD :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_MASK                    0xfffffffe
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_SHIFT                   1
+
+/* MEMC_DDR_0 :: SSPD_CMD :: SSPD [00:00] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK                         0x00000001
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_SHIFT                        0
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *POWER_DOWN_STATUS - Power down status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_MASK           0xfffffff8
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_SHIFT          3
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SSPD [02:02] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK                0x00000004
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_SHIFT               2
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_DEFAULT             0x00000000
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SRPD [01:01] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_MASK                0x00000002
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_SHIFT               1
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_DEFAULT             0x00000000
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: PPD [00:00] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_MASK                 0x00000001
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_SHIFT                0
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_DEFAULT              0x00000000
+
+/***************************************************************************
+ *WARM_BOOT - Warm boot control registers
+ ***************************************************************************/
+/* MEMC_DDR_0 :: WARM_BOOT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_MASK                   0xfffffffe
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_SHIFT                  1
+
+/* MEMC_DDR_0 :: WARM_BOOT :: WARM_BOOT [00:00] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_MASK                   0x00000001
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_TIMING_0 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_MASK                0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_SHIFT               24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_DEFAULT             0x00000006
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_MASK                0x00ff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_SHIFT               16
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_DEFAULT             0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_MASK                 0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_SHIFT                8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_DEFAULT              0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_DEFAULT             0x00000014
+
+/***************************************************************************
+ *DRAM_TIMING_1 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_MASK                0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_SHIFT               8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_DEFAULT             0x0000001b
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_DEFAULT             0x00000004
+
+/***************************************************************************
+ *DRAM_TIMING_2 - Read to Write & write to read timing register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_MASK               0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_SHIFT              8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_DEFAULT            0x0000000e
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_MASK               0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_DEFAULT            0x00000009
+
+/***************************************************************************
+ *DRAM_TIMING_3 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: reserved0 [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_MASK               0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_SHIFT              24
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT      0x0000000c
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: POWERUP_CKE_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_MASK       0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_SHIFT      10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_DEFAULT    0x0000005e
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: DLL_LOCK_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_MASK          0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_SHIFT         0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_DEFAULT       0x00000200
+
+/***************************************************************************
+ *DRAM_TIMING_4 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: PRECHARGE_ALL_DELAY [28:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_MASK     0x1f000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_SHIFT    24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_DEFAULT  0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: LOAD_MODE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_DEFAULT      0x0000000c
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: REFRESH_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_MASK           0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_SHIFT          10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT        0x00000058
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_MASK           0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT          0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT        0x00000200
+
+/***************************************************************************
+ *DRAM_TIMING_5 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_ASSETION_DELAY [28:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_MASK      0x1ff80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_SHIFT     19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_DEFAULT   0x00000105
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [18:15] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK           0x00078000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT          15
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT        0x00000003
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [14:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK         0x00007c00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT        10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT      0x0000000d
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK      0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT     0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT   0x00000200
+
+/***************************************************************************
+ *CNTRLR_START_SEQ - Memory Controller Sequencer Enable
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: START_SEQ [00:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_SHIFT           0
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_MASK           0xfffe0000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_SHIFT          17
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_MASK              0x00010000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT             16
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT            0x0000ffff
+
+/***************************************************************************
+ *BANK_STATUS - Memory Controller, Bank Status Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: BANK_STATUS :: reserved0 [31:08] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_SHIFT                8
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK7_STATUS [07:07] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_SHIFT             7
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK6_STATUS [06:06] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_SHIFT             6
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK5_STATUS [05:05] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_MASK              0x00000020
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_SHIFT             5
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK4_STATUS [04:04] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_MASK              0x00000010
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_SHIFT             4
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK3_STATUS [03:03] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_MASK              0x00000008
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_SHIFT             3
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK2_STATUS [02:02] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_MASK              0x00000004
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_SHIFT             2
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK1_STATUS [01:01] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_SHIFT             1
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK0_STATUS [00:00] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_MASK              0x00000001
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_SHIFT             0
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_DEFAULT           0x00000001
+
+/***************************************************************************
+ *TESTER_LATENCY - Memory Controller, Tester Latency Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: TESTER_LATENCY :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_MASK              0xffffff80
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_SHIFT             7
+
+/* MEMC_DDR_0 :: TESTER_LATENCY :: TLATENCY_SEL [06:00] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_MASK           0x0000007f
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_SHIFT          0
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE0 - Memory Controller, DATA_PINMAP_BYTE0_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE1 - Memory Controller, DATA_PINMAP_BYTE1_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE2 - Memory Controller, DATA_PINMAP_BYTE2_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE3 - Memory Controller, DATA_PINMAP_BYTE3_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_DDR3_RESET_PERIOD - Memory Controller, DDR3 DRAM reset Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: reserved0 [31:20] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_MASK      0xfff00000
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_SHIFT     20
+
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: DRAM_RESET_PERIOD [19:00] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_MASK 0x000fffff
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_SHIFT 0
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_DEFAULT 0x0000a8c0
+
+/***************************************************************************
+ *STAT_CONTROL - Statistics Control register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CONTROL :: reserved0 [31:09] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_MASK                0xfffffe00
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_SHIFT               9
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: COUNTER_MODE [08:08] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_SHIFT            8
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_DEFAULT          0x00000000
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT    1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_NORMAL           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: STAT_ENABLE [07:07] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_SHIFT             7
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DEFAULT           0x00000000
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_ENABLE            1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DISABLE           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: CLIENT_ID [06:00] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_MASK                0x0000007f
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_TIMER - Statistics Timer
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TIMER :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_MASK                      0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_SHIFT                     0
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_MASK                   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_ALL - CAS Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_PENALTY_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_MASK            0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_SHIFT           0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_DEFAULT           0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_MASK         0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT        0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_REFRESH - Total number of refreshes issuedr.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_REFRESH :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_0 - CAS cycle count register for client 0.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_1 - CAS cycle count register for client 1.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_2 - CAS cycle count register for client 2.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_3 - CAS cycle count register for client 3.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_4 - CAS cycle count register for client 4.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_5 - CAS cycle count register for client 5.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_6 - CAS cycle count register for client 6.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_7 - CAS cycle count register for client 7.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_8 - CAS cycle count register for client 8.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_9 - CAS cycle count register for client 9.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_10 - CAS cycle count register for client 10.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_11 - CAS cycle count register for client 11.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_12 - CAS cycle count register for client 12.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_13 - CAS cycle count register for client 13.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_14 - CAS cycle count register for client 14.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_15 - CAS cycle count register for client 15.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_16 - CAS cycle count register for client 16.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_17 - CAS cycle count register for client 17.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_18 - CAS cycle count register for client 18.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_19 - CAS cycle count register for client 19.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_20 - CAS cycle count register for client 20.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_21 - CAS cycle count register for client 21.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_22 - CAS cycle count register for client 22.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_23 - CAS cycle count register for client 23.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_24 - CAS cycle count register for client 24.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_25 - CAS cycle count register for client 25.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_26 - CAS cycle count register for client 26.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_27 - CAS cycle count register for client 27.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_28 - CAS cycle count register for client 28.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_29 - CAS cycle count register for client 29.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_30 - CAS cycle count register for client 30.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_31 - CAS cycle count register for client 31.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_32 - CAS cycle count register for client 32.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_33 - CAS cycle count register for client 33.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_34 - CAS cycle count register for client 34.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_35 - CAS cycle count register for client 35.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_36 - CAS cycle count register for client 36.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_37 - CAS cycle count register for client 37.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_38 - CAS cycle count register for client 38.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_39 - CAS cycle count register for client 39.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_40 - CAS cycle count register for client 40.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_41 - CAS cycle count register for client 41.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_42 - CAS cycle count register for client 42.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_43 - CAS cycle count register for client 43.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_44 - CAS cycle count register for client 44.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_45 - CAS cycle count register for client 45.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_46 - CAS cycle count register for client 46.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_47 - CAS cycle count register for client 47.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_48 - CAS cycle count register for client 48.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_49 - CAS cycle count register for client 49.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_50 - CAS cycle count register for client 50.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_51 - CAS cycle count register for client 51.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_52 - CAS cycle count register for client 52.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_53 - CAS cycle count register for client 53.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_54 - CAS cycle count register for client 54.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_55 - CAS cycle count register for client 55.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_56 - CAS cycle count register for client 56.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_57 - CAS cycle count register for client 57.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_58 - CAS cycle count register for client 58.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_59 - CAS cycle count register for client 59.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_60 - CAS cycle count register for client 60.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_61 - CAS cycle count register for client 61.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_62 - CAS cycle count register for client 62.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_63 - CAS cycle count register for client 63.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_64 - CAS cycle count register for client 64.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_65 - CAS cycle count register for client 65.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_66 - CAS cycle count register for client 66.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_67 - CAS cycle count register for client 67.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_68 - CAS cycle count register for client 68.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_69 - CAS cycle count register for client 69.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_70 - CAS cycle count register for client 70.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_71 - CAS cycle count register for client 71.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_72 - CAS cycle count register for client 72.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_73 - CAS cycle count register for client 73.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_74 - CAS cycle count register for client 74.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_75 - CAS cycle count register for client 75.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_76 - CAS cycle count register for client 76.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_77 - CAS cycle count register for client 77.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_78 - CAS cycle count register for client 78.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_79 - CAS cycle count register for client 79.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_80 - CAS cycle count register for client 80.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_81 - CAS cycle count register for client 81.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_82 - CAS cycle count register for client 82.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_83 - CAS cycle count register for client 83.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_84 - CAS cycle count register for client 84.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_85 - CAS cycle count register for client 85.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_86 - CAS cycle count register for client 86.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_87 - CAS cycle count register for client 87.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_88 - CAS cycle count register for client 88.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_89 - CAS cycle count register for client 89.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_90 - CAS cycle count register for client 90.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_91 - CAS cycle count register for client 91.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_92 - CAS cycle count register for client 92.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_93 - CAS cycle count register for client 93.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_94 - CAS cycle count register for client 94.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_95 - CAS cycle count register for client 95.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_96 - CAS cycle count register for client 96.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_97 - CAS cycle count register for client 97.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_98 - CAS cycle count register for client 98.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_99 - CAS cycle count register for client 99.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_100 - CAS cycle count register for client 100.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_101 - CAS cycle count register for client 101.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_102 - CAS cycle count register for client 102.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_103 - CAS cycle count register for client 103.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_104 - CAS cycle count register for client 104.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_105 - CAS cycle count register for client 105.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_106 - CAS cycle count register for client 106.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_107 - CAS cycle count register for client 107.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_108 - CAS cycle count register for client 108.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_109 - CAS cycle count register for client 109.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_110 - CAS cycle count register for client 110.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_111 - CAS cycle count register for client 111.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_112 - CAS cycle count register for client 112.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_113 - CAS cycle count register for client 113.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_114 - CAS cycle count register for client 114.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_115 - CAS cycle count register for client 115.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_116 - CAS cycle count register for client 116.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_117 - CAS cycle count register for client 117.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_118 - CAS cycle count register for client 118.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_119 - CAS cycle count register for client 119.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_120 - CAS cycle count register for client 120.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_121 - CAS cycle count register for client 121.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_122 - CAS cycle count register for client 122.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_123 - CAS cycle count register for client 123.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_124 - CAS cycle count register for client 124.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_125 - CAS cycle count register for client 125.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_126 - CAS cycle count register for client 126.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_127 - CAS cycle count register for client 127.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_DEFAULT             0xffffffff
+
+/***************************************************************************
+ *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT    0xffffffff
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_CONTROL - MEMSYS Auto Init Control.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: reserved0 [31:10] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_MASK    0xfffffc00
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_SHIFT   10
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_DIVIDER [09:09] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_MASK 0x00000200
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_SHIFT 9
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_VDL_CALIB_AUTO_INIT [08:08] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_MASK 0x00000100
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_SHIFT 8
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_DRAM_INIT_DONE_SET [07:07] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_MASK 0x00000080
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_SHIFT 7
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_RESET [06:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_MASK 0x00000040
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_SET [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_READY_SET [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_AUTO_INIT_ACTIVE_RESET [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_MASK 0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_SHIFT 3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: SKIP_PHY_AUTO_INIT [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: MEMSYS_AUTO_INIT_START [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_STATUS - MEMSYS Auto Init Status.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_MASK     0xfffff000
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_SHIFT    12
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMC_AUTO_INIT_STATES [11:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_MASK 0x00000fc0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: AUTO_INIT_ACTIVE [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_STRAP_VALID [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_READY [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_MASK     0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_SHIFT    3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_DEFAULT  0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: DRAM_INIT_DONE [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_FAIL [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHY_VDL_CALIB_AUTO_INIT_OVERRIDE - PHY VDL calibrate override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PHY_VDL_CALIB_AUTO_INIT_OVERRIDE :: PHY_VDL_CALIB_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_DEFAULT 0x10000000
+
+/***************************************************************************
+ *SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE - SHIM PLL pndiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_PNDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_DEFAULT 0x23b00000
+
+/***************************************************************************
+ *SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE - SHIM PLL mdiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_MDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_DEFAULT 0x00001003
+
+/***************************************************************************
+ *DYN_VDL_CMD_DLY - Dynamic VDL shmoo command delay.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_MASK             0xfffff000
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_SHIFT            12
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: END_CAS_DLY [11:06] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_MASK           0x00000fc0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_SHIFT          6
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_DEFAULT        0x00000000
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: START_CAS_DLY [05:00] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_MASK         0x0000003f
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_SHIFT        0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_DEFAULT      0x00000000
+
+#endif /* #ifndef BCHP_MEMC_DDR_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_misb_bridge.h b/include/linux/brcmstb/7360a0/bchp_misb_bridge.h
new file mode 100644
index 0000000..f44fd74
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_misb_bridge.h
@@ -0,0 +1,126 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_misb_bridge.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:07p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MISB_BRIDGE_H__
+#define BCHP_MISB_BRIDGE_H__
+
+/***************************************************************************
+ *MISB_BRIDGE - MISB_BRIDGE Registers
+ ***************************************************************************/
+#define BCHP_MISB_BRIDGE_CORE_REV_ID             0x00410400 /* MISB Bridge Revision ID Register. */
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET 0x00410404 /* "Exception Vector Offset Address" */
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID            0x00410408 /* Processor ID Register. */
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT       0x0041040c /* Write Gathering Mode & Timeout. */
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE         0x00410410 /* MISB Split Mode */
+
+/***************************************************************************
+ *CORE_REV_ID - MISB Bridge Revision ID Register.
+ ***************************************************************************/
+/* MISB_BRIDGE :: CORE_REV_ID :: reserved0 [31:16] */
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_reserved0_MASK                0xffff0000
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_reserved0_SHIFT               16
+
+/* MISB_BRIDGE :: CORE_REV_ID :: MAJOR [15:08] */
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MAJOR_MASK                    0x0000ff00
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MAJOR_SHIFT                   8
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MAJOR_DEFAULT                 0x00000000
+
+/* MISB_BRIDGE :: CORE_REV_ID :: MINOR [07:00] */
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MINOR_MASK                    0x000000ff
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MINOR_SHIFT                   0
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MINOR_DEFAULT                 0x00000004
+
+/***************************************************************************
+ *EXCEPTION_VECTOR_OFFSET - "Exception Vector Offset Address"
+ ***************************************************************************/
+/* MISB_BRIDGE :: EXCEPTION_VECTOR_OFFSET :: ADDRS [31:00] */
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET_ADDRS_MASK        0xffffffff
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET_ADDRS_SHIFT       0
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET_ADDRS_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PROCESSOR_ID - Processor ID Register.
+ ***************************************************************************/
+/* MISB_BRIDGE :: PROCESSOR_ID :: reserved0 [31:08] */
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_reserved0_MASK               0xffffff00
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_reserved0_SHIFT              8
+
+/* MISB_BRIDGE :: PROCESSOR_ID :: ID [07:00] */
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_ID_MASK                      0x000000ff
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_ID_SHIFT                     0
+
+/***************************************************************************
+ *WG_MODE_N_TIMEOUT - Write Gathering Mode & Timeout.
+ ***************************************************************************/
+/* MISB_BRIDGE :: WG_MODE_N_TIMEOUT :: reserved0 [31:10] */
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_reserved0_MASK          0xfffffc00
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_reserved0_SHIFT         10
+
+/* MISB_BRIDGE :: WG_MODE_N_TIMEOUT :: MODE [09:08] */
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_MASK               0x00000300
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_SHIFT              8
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_DEFAULT            0x00000000
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_MODE_0             0
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_MODE_1             1
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_MODE_2             2
+
+/* MISB_BRIDGE :: WG_MODE_N_TIMEOUT :: TIMEOUT [07:00] */
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_TIMEOUT_MASK            0x000000ff
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_TIMEOUT_SHIFT           0
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_TIMEOUT_DEFAULT         0x00000064
+
+/***************************************************************************
+ *MISB_SPLIT_MODE - MISB Split Mode
+ ***************************************************************************/
+/* MISB_BRIDGE :: MISB_SPLIT_MODE :: reserved0 [31:01] */
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_reserved0_MASK            0xfffffffe
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_reserved0_SHIFT           1
+
+/* MISB_BRIDGE :: MISB_SPLIT_MODE :: SPLIT_MODE [00:00] */
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_SPLIT_MODE_MASK           0x00000001
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_SPLIT_MODE_SHIFT          0
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_SPLIT_MODE_DEFAULT        0x00000000
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_SPLIT_MODE_ENABLE         1
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_SPLIT_MODE_DISABLE        0
+
+#endif /* #ifndef BCHP_MISB_BRIDGE_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_nand.h b/include/linux/brcmstb/7360a0/bchp_nand.h
new file mode 100644
index 0000000..6ad6a8e
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_nand.h
@@ -0,0 +1,2260 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_nand.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:09p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_NAND_H__
+#define BCHP_NAND_H__
+
+/***************************************************************************
+ *NAND - Nand Flash Control Registers
+ ***************************************************************************/
+#define BCHP_NAND_REVISION                       0x00412800 /* NAND Revision */
+#define BCHP_NAND_CMD_START                      0x00412804 /* Nand Flash Command Start */
+#define BCHP_NAND_CMD_EXT_ADDRESS                0x00412808 /* Nand Flash Command Extended Address */
+#define BCHP_NAND_CMD_ADDRESS                    0x0041280c /* Nand Flash Command Address */
+#define BCHP_NAND_CMD_END_ADDRESS                0x00412810 /* Nand Flash Command End Address */
+#define BCHP_NAND_CS_NAND_SELECT                 0x00412814 /* Nand Flash EBI CS Select */
+#define BCHP_NAND_CS_NAND_XOR                    0x00412818 /* Nand Flash EBI CS Address XOR with 1FC0 Control */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0          0x00412820 /* Nand Flash Spare Area Read Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4          0x00412824 /* Nand Flash Spare Area Read Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8          0x00412828 /* Nand Flash Spare Area Read Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C          0x0041282c /* Nand Flash Spare Area Read Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0         0x00412830 /* Nand Flash Spare Area Write Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4         0x00412834 /* Nand Flash Spare Area Write Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8         0x00412838 /* Nand Flash Spare Area Write Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C         0x0041283c /* Nand Flash Spare Area Write Bytes 12-15 */
+#define BCHP_NAND_ACC_CONTROL                    0x00412840 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG                         0x00412848 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1                       0x00412850 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2                       0x00412854 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SEMAPHORE                      0x00412858 /* Semaphore */
+#define BCHP_NAND_FLASH_DEVICE_ID                0x00412860 /* Nand Flash Device ID */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT            0x00412864 /* Nand Flash Extended Device ID */
+#define BCHP_NAND_BLOCK_LOCK_STATUS              0x00412868 /* Nand Flash Block Lock Status */
+#define BCHP_NAND_INTFC_STATUS                   0x0041286c /* Nand Flash Interface Status */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR              0x00412870 /* ECC Correctable Error Extended Address */
+#define BCHP_NAND_ECC_CORR_ADDR                  0x00412874 /* ECC Correctable Error Address */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR               0x00412878 /* ECC Uncorrectable Error Extended Address */
+#define BCHP_NAND_ECC_UNC_ADDR                   0x0041287c /* ECC Uncorrectable Error Address */
+#define BCHP_NAND_READ_ERROR_COUNT               0x00412880 /* Read Error Count */
+#define BCHP_NAND_CORR_STAT_THRESHOLD            0x00412884 /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_ONFI_STATUS                    0x00412888 /* ONFI Status */
+#define BCHP_NAND_ONFI_DEBUG_DATA                0x0041288c /* ONFI Debug Data */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR            0x00412890 /* Flash Read Data Extended Address */
+#define BCHP_NAND_FLASH_READ_ADDR                0x00412894 /* Flash Read Data Address */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR          0x00412898 /* Page Program Extended Address */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR              0x0041289c /* Page Program Address */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR             0x004128a0 /* Copy Back Extended Address */
+#define BCHP_NAND_COPY_BACK_ADDR                 0x004128a4 /* Copy Back Address */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR           0x004128a8 /* Block Erase Extended Address */
+#define BCHP_NAND_BLOCK_ERASE_ADDR               0x004128ac /* Block Erase Address */
+#define BCHP_NAND_INV_READ_EXT_ADDR              0x004128b0 /* Flash Invalid Data Extended Address */
+#define BCHP_NAND_INV_READ_ADDR                  0x004128b4 /* Flash Invalid Data Address */
+#define BCHP_NAND_BLK_WR_PROTECT                 0x004128c0 /* Block Write Protect Enable and Size for EBI_CS0b */
+#define BCHP_NAND_ACC_CONTROL_CS1                0x004128d0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS1                     0x004128d4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS1                   0x004128d8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS1                   0x004128dc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS2                0x004128e0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS2                     0x004128e4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS2                   0x004128e8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS2                   0x004128ec /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS3                0x004128f0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS3                     0x004128f4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS3                   0x004128f8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS3                   0x004128fc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS4                0x00412900 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS4                     0x00412904 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS4                   0x00412908 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS4                   0x0041290c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10         0x00412930 /* Nand Flash Spare Area Read Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14         0x00412934 /* Nand Flash Spare Area Read Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18         0x00412938 /* Nand Flash Spare Area Read Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C         0x0041293c /* Nand Flash Spare Area Read Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10        0x00412940 /* Nand Flash Spare Area Write Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14        0x00412944 /* Nand Flash Spare Area Write Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18        0x00412948 /* Nand Flash Spare Area Write Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C        0x0041294c /* Nand Flash Spare Area Write Bytes 28-31 */
+#define BCHP_NAND_LL_OP                          0x00412978 /* Nand Flash Low Level Operation */
+#define BCHP_NAND_LL_RDDATA                      0x0041297c /* Nand Flash Low Level Read Data */
+
+/***************************************************************************
+ *REVISION - NAND Revision
+ ***************************************************************************/
+/* NAND :: REVISION :: 8KB_PAGE_SUPPORT [31:31] */
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_MASK                   0x80000000
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_SHIFT                  31
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_DEFAULT                0x00000001
+
+/* NAND :: REVISION :: reserved0 [30:16] */
+#define BCHP_NAND_REVISION_reserved0_MASK                          0x7fff0000
+#define BCHP_NAND_REVISION_reserved0_SHIFT                         16
+
+/* NAND :: REVISION :: MAJOR [15:08] */
+#define BCHP_NAND_REVISION_MAJOR_MASK                              0x0000ff00
+#define BCHP_NAND_REVISION_MAJOR_SHIFT                             8
+#define BCHP_NAND_REVISION_MAJOR_DEFAULT                           0x00000005
+
+/* NAND :: REVISION :: MINOR [07:00] */
+#define BCHP_NAND_REVISION_MINOR_MASK                              0x000000ff
+#define BCHP_NAND_REVISION_MINOR_SHIFT                             0
+#define BCHP_NAND_REVISION_MINOR_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *CMD_START - Nand Flash Command Start
+ ***************************************************************************/
+/* NAND :: CMD_START :: reserved0 [31:29] */
+#define BCHP_NAND_CMD_START_reserved0_MASK                         0xe0000000
+#define BCHP_NAND_CMD_START_reserved0_SHIFT                        29
+
+/* NAND :: CMD_START :: OPCODE [28:24] */
+#define BCHP_NAND_CMD_START_OPCODE_MASK                            0x1f000000
+#define BCHP_NAND_CMD_START_OPCODE_SHIFT                           24
+#define BCHP_NAND_CMD_START_OPCODE_DEFAULT                         0x00000000
+#define BCHP_NAND_CMD_START_OPCODE_NULL                            0
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ                       1
+#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ                 2
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ                     3
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE                    4
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA              5
+#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK                       6
+#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ                  7
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE                     8
+#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET                     9
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK                     10
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN                11
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK                   12
+#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS         13
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ                  14
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL            15
+#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP                    16
+
+/* NAND :: CMD_START :: reserved1 [23:00] */
+#define BCHP_NAND_CMD_START_reserved1_MASK                         0x00ffffff
+#define BCHP_NAND_CMD_START_reserved1_SHIFT                        0
+
+/***************************************************************************
+ *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
+ ***************************************************************************/
+/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK                   0xfff80000
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT                  19
+
+/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK                      0x00070000
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT                     16
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT                   0x00000000
+
+/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK                 0x0000ffff
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT                0
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CMD_ADDRESS - Nand Flash Command Address
+ ***************************************************************************/
+/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK                         0xffffffff
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT                        0
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *CMD_END_ADDRESS - Nand Flash Command End Address
+ ***************************************************************************/
+/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT                    0
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *CS_NAND_SELECT - Nand Flash EBI CS Select
+ ***************************************************************************/
+/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT                     31
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK        0x40000000
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT       30
+
+/* NAND :: CS_NAND_SELECT :: reserved0 [29:29] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK                    0x20000000
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT                   29
+
+/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK              0x10000000
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT             28
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT           0x00000000
+
+/* NAND :: CS_NAND_SELECT :: reserved1 [27:16] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_MASK                    0x0fff0000
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_SHIFT                   16
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK           0x00008000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT          15
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK           0x00004000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT          14
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK           0x00002000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT          13
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK           0x00001000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT          12
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK           0x00000800
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT          11
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK           0x00000400
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT          10
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK           0x00000200
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT          9
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK           0x00000100
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT          8
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK                 0x00000080
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT                7
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK                 0x00000040
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT                6
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK                 0x00000020
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT                5
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK                 0x00000010
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT                4
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK                 0x00000008
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT                3
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK                 0x00000004
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT                2
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK                 0x00000002
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT                1
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK                 0x00000001
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT                0
+
+/***************************************************************************
+ *CS_NAND_XOR - Nand Flash EBI CS Address XOR with 1FC0 Control
+ ***************************************************************************/
+/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_1FC0_XOR [31:31] */
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_MASK           0x80000000
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_SHIFT          31
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
+#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK                       0x7fffff00
+#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT                      8
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_1FC0_XOR [07:07] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_MASK          0x00000080
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_SHIFT         7
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_1FC0_XOR [06:06] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_MASK          0x00000040
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_SHIFT         6
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_1FC0_XOR [05:05] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_MASK          0x00000020
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_SHIFT         5
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_1FC0_XOR [04:04] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_MASK          0x00000010
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_SHIFT         4
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_1FC0_XOR [03:03] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_MASK          0x00000008
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_SHIFT         3
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_1FC0_XOR [02:02] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_MASK          0x00000004
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_SHIFT         2
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_1FC0_XOR [01:01] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_MASK          0x00000002
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_SHIFT         1
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_1FC0_XOR [00:00] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_MASK          0x00000001
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_SHIFT         0
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *ACC_CONTROL - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_MASK                       0x80000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_SHIFT                      31
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_DEFAULT                    0x00000001
+
+/* NAND :: ACC_CONTROL :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_MASK                       0x40000000
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_SHIFT                      30
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_DEFAULT                    0x00000001
+
+/* NAND :: ACC_CONTROL :: RD_ECC_BLK0_EN [29:29] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_MASK                  0x20000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_SHIFT                 29
+
+/* NAND :: ACC_CONTROL :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_SHIFT                  28
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_MASK                0x08000000
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_SHIFT               27
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_DEFAULT             0x00000000
+
+/* NAND :: ACC_CONTROL :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_MASK                 0x04000000
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_SHIFT                26
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_MASK                   0x02000000
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_SHIFT                  25
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_MASK                     0x01000000
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_SHIFT                    24
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_DEFAULT                  0x00000001
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL_0 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_MASK                     0x00f00000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_SHIFT                    20
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_DEFAULT                  0x0000000f
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_MASK                       0x000f0000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_SHIFT                      16
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_DEFAULT                    0x0000000f
+
+/* NAND :: ACC_CONTROL :: reserved0 [15:15] */
+#define BCHP_NAND_ACC_CONTROL_reserved0_MASK                       0x00008000
+#define BCHP_NAND_ACC_CONTROL_reserved0_SHIFT                      15
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K_0 [14:14] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_MASK                0x00004000
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_SHIFT               14
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_DEFAULT             0x00000000
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE_0 [13:08] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_MASK               0x00003f00
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_SHIFT              8
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_DEFAULT            0x00000010
+
+/* NAND :: ACC_CONTROL :: reserved1 [07:07] */
+#define BCHP_NAND_ACC_CONTROL_reserved1_MASK                       0x00000080
+#define BCHP_NAND_ACC_CONTROL_reserved1_SHIFT                      7
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_MASK                  0x00000040
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_SHIFT                 6
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_DEFAULT               0x00000000
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_MASK                 0x0000003f
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_SHIFT                0
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_DEFAULT              0x00000010
+
+/***************************************************************************
+ *CONFIG - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_MASK                          0x80000000
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_SHIFT                         31
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_DEFAULT                       0x00000000
+
+/* NAND :: CONFIG :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_MASK                           0x70000000
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_SHIFT                          28
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_2048KB                 6
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_1024KB                 5
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_512KB                  3
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_128KB                  1
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_16KB                   0
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_8KB                    2
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_256KB                  4
+
+/* NAND :: CONFIG :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_MASK                          0x0f000000
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_SHIFT                         24
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4MB                  0
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8MB                  1
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16MB                 2
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32MB                 3
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64MB                 4
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128MB                5
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_256MB                6
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_512MB                7
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_1GB                  8
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_2GB                  9
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4GB                  10
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8GB                  11
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16GB                 12
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32GB                 13
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64GB                 14
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128GB                15
+
+/* NAND :: CONFIG :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_MASK                         0x00800000
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_SHIFT                        23
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_8                  0
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_16                 1
+
+/* NAND :: CONFIG :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_reserved0_MASK                            0x00400000
+#define BCHP_NAND_CONFIG_reserved0_SHIFT                           22
+
+/* NAND :: CONFIG :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_PAGE_SIZE_MASK                            0x00300000
+#define BCHP_NAND_CONFIG_PAGE_SIZE_SHIFT                           20
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_512                     0
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_2KB                     1
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_4KB                     2
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_8KB                     3
+
+/* NAND :: CONFIG :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_reserved1_MASK                            0x00080000
+#define BCHP_NAND_CONFIG_reserved1_SHIFT                           19
+
+/* NAND :: CONFIG :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_MASK                        0x00070000
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_SHIFT                       16
+
+/* NAND :: CONFIG :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_reserved2_MASK                            0x00008000
+#define BCHP_NAND_CONFIG_reserved2_SHIFT                           15
+
+/* NAND :: CONFIG :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_MASK                        0x00007000
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_SHIFT                       12
+
+/* NAND :: CONFIG :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_reserved3_MASK                            0x00000800
+#define BCHP_NAND_CONFIG_reserved3_SHIFT                           11
+
+/* NAND :: CONFIG :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_MASK                        0x00000700
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_SHIFT                       8
+
+/* NAND :: CONFIG :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_reserved4_MASK                            0x000000ff
+#define BCHP_NAND_CONFIG_reserved4_SHIFT                           0
+
+/***************************************************************************
+ *TIMING_1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_tWP_MASK                                0xf0000000
+#define BCHP_NAND_TIMING_1_tWP_SHIFT                               28
+#define BCHP_NAND_TIMING_1_tWP_DEFAULT                             0x00000006
+
+/* NAND :: TIMING_1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_tWH_MASK                                0x0f000000
+#define BCHP_NAND_TIMING_1_tWH_SHIFT                               24
+#define BCHP_NAND_TIMING_1_tWH_DEFAULT                             0x00000005
+
+/* NAND :: TIMING_1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_tRP_MASK                                0x00f00000
+#define BCHP_NAND_TIMING_1_tRP_SHIFT                               20
+#define BCHP_NAND_TIMING_1_tRP_DEFAULT                             0x00000007
+
+/* NAND :: TIMING_1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_tREH_MASK                               0x000f0000
+#define BCHP_NAND_TIMING_1_tREH_SHIFT                              16
+#define BCHP_NAND_TIMING_1_tREH_DEFAULT                            0x00000004
+
+/* NAND :: TIMING_1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_tCS_MASK                                0x0000f000
+#define BCHP_NAND_TIMING_1_tCS_SHIFT                               12
+#define BCHP_NAND_TIMING_1_tCS_DEFAULT                             0x00000008
+
+/* NAND :: TIMING_1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_tCLH_MASK                               0x00000f00
+#define BCHP_NAND_TIMING_1_tCLH_SHIFT                              8
+#define BCHP_NAND_TIMING_1_tCLH_DEFAULT                            0x00000004
+
+/* NAND :: TIMING_1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_tALH_MASK                               0x000000f0
+#define BCHP_NAND_TIMING_1_tALH_SHIFT                              4
+#define BCHP_NAND_TIMING_1_tALH_DEFAULT                            0x00000005
+
+/* NAND :: TIMING_1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_tADL_MASK                               0x0000000f
+#define BCHP_NAND_TIMING_1_tADL_SHIFT                              0
+#define BCHP_NAND_TIMING_1_tADL_DEFAULT                            0x0000000b
+
+/***************************************************************************
+ *TIMING_2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CLK_SELECT_MASK                         0x80000000
+#define BCHP_NAND_TIMING_2_CLK_SELECT_SHIFT                        31
+#define BCHP_NAND_TIMING_2_CLK_SELECT_DEFAULT                      0x00000000
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_108                      0
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_216                      1
+
+/* NAND :: TIMING_2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_reserved0_MASK                          0x7fffe000
+#define BCHP_NAND_TIMING_2_reserved0_SHIFT                         13
+
+/* NAND :: TIMING_2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_tWB_MASK                                0x00001e00
+#define BCHP_NAND_TIMING_2_tWB_SHIFT                               9
+#define BCHP_NAND_TIMING_2_tWB_DEFAULT                             0x0000000f
+
+/* NAND :: TIMING_2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_tWHR_MASK                               0x000001f0
+#define BCHP_NAND_TIMING_2_tWHR_SHIFT                              4
+#define BCHP_NAND_TIMING_2_tWHR_DEFAULT                            0x00000009
+
+/* NAND :: TIMING_2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_tREAD_MASK                              0x0000000f
+#define BCHP_NAND_TIMING_2_tREAD_SHIFT                             0
+#define BCHP_NAND_TIMING_2_tREAD_DEFAULT                           0x00000006
+
+/***************************************************************************
+ *SEMAPHORE - Semaphore
+ ***************************************************************************/
+/* NAND :: SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_NAND_SEMAPHORE_reserved0_MASK                         0xffffff00
+#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT                        8
+
+/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK                    0x000000ff
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT                   0
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *FLASH_DEVICE_ID - Nand Flash Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK                      0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT                     24
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK                      0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT                     16
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK                      0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT                     8
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK                      0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT                     0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK                  0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT                 24
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK                  0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT                 16
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK                  0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT                 8
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK                  0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT                 0
+
+/***************************************************************************
+ *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
+ ***************************************************************************/
+/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT                8
+
+/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK                    0x000000ff
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT                   0
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *INTFC_STATUS - Nand Flash Interface Status
+ ***************************************************************************/
+/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK                     0x80000000
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT                    31
+
+/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK                    0x40000000
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT                   30
+
+/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK                    0x20000000
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT                   29
+
+/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK               0x10000000
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT              28
+
+/* NAND :: INTFC_STATUS :: ERASED [27:27] */
+#define BCHP_NAND_INTFC_STATUS_ERASED_MASK                         0x08000000
+#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT                        27
+
+/* NAND :: INTFC_STATUS :: reserved0 [26:08] */
+#define BCHP_NAND_INTFC_STATUS_reserved0_MASK                      0x07ffff00
+#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT                     8
+
+/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK                   0x000000ff
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT                  0
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ECC_CORR_ADDR - ECC Correctable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK                  0xfff80000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT                 19
+
+/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK                     0x00070000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT                    16
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT                  0x00000000
+
+/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK                0x0000ffff
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT               0
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT             0x00000000
+
+/***************************************************************************
+ *ECC_UNC_ADDR - ECC Uncorrectable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK                        0xffffffff
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT                       0
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *READ_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:05] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK               0xffffffe0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT              5
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD [04:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_MASK     0x0000001f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_SHIFT    0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_DEFAULT  0x00000001
+
+/***************************************************************************
+ *ONFI_STATUS - ONFI Status
+ ***************************************************************************/
+/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK                  0xf0000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT                 28
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT               0x00000000
+
+/* NAND :: ONFI_STATUS :: reserved0 [27:06] */
+#define BCHP_NAND_ONFI_STATUS_reserved0_MASK                       0x0fffffc0
+#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT                      6
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK              0x00000020
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT             5
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK              0x00000010
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT             4
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK              0x00000008
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT             3
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK              0x00000004
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT             2
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK              0x00000002
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT             1
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK              0x00000001
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT             0
+
+/***************************************************************************
+ *ONFI_DEBUG_DATA - ONFI Debug Data
+ ***************************************************************************/
+/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK             0xffffffff
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT            0
+
+/***************************************************************************
+ *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK               0xfff80000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT              19
+
+/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK                  0x00070000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT                 16
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT               0x00000000
+
+/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK             0x0000ffff
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT            0
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT          0x00000000
+
+/***************************************************************************
+ *FLASH_READ_ADDR - Flash Read Data Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT                    0
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK             0xfff80000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT            19
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK                0x00070000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT               16
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT             0x00000000
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK           0x0000ffff
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT          0
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_ADDR - Page Program Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK                   0xffffffff
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT                  0
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *COPY_BACK_EXT_ADDR - Copy Back Extended Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK                0xfff80000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT               19
+
+/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK                   0x00070000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT                  16
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT                0x00000000
+
+/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK              0x0000ffff
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT             0
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT           0x00000000
+
+/***************************************************************************
+ *COPY_BACK_ADDR - Copy Back Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK                      0xffffffff
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT                     0
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK              0xfff80000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT             19
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK                 0x00070000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT                16
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT              0x00000000
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK            0x0000ffff
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT           0
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_ADDR - Block Erase Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK                    0xffffffff
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT                   0
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
+ ***************************************************************************/
+/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *INV_READ_ADDR - Flash Invalid Data Address
+ ***************************************************************************/
+/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
+ ***************************************************************************/
+/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK                 0xffffffff
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT                0
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *ACC_CONTROL_CS1 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS1 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS1 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS1 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS1 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS1_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS1 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS1 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS1_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS1_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS1_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS1_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS1_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS1_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS1_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS1_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS1_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS1_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS1_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS1 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS1 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS1_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS2 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS2 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS2 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS2 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS2 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS2_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS2 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS2 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS2_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS2_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS2_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS2_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS2 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS2_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS2_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS2_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS2_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS2_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS2_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS2_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS2_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS3 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS3 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS3 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS3 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS3 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS3_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS3 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS3 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS3_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS3_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS3_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS3_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS3 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS3_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS3_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS3_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS3_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS3_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS3_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS3_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS3 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS3 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS3_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS4 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS4 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS4 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS4 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS4 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS4_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS4 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS4 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS4_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS4_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS4_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS4_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS4 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS4_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS4_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS4_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS4_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS4_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS4_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS4_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS4 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS4 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS4_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *LL_OP - Nand Flash Low Level Operation
+ ***************************************************************************/
+/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
+#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK                           0x80000000
+#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT                          31
+#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT                        0x00000000
+
+/* NAND :: LL_OP :: reserved0 [30:20] */
+#define BCHP_NAND_LL_OP_reserved0_MASK                             0x7ff00000
+#define BCHP_NAND_LL_OP_reserved0_SHIFT                            20
+
+/* NAND :: LL_OP :: CLE [19:19] */
+#define BCHP_NAND_LL_OP_CLE_MASK                                   0x00080000
+#define BCHP_NAND_LL_OP_CLE_SHIFT                                  19
+#define BCHP_NAND_LL_OP_CLE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: ALE [18:18] */
+#define BCHP_NAND_LL_OP_ALE_MASK                                   0x00040000
+#define BCHP_NAND_LL_OP_ALE_SHIFT                                  18
+#define BCHP_NAND_LL_OP_ALE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: WE [17:17] */
+#define BCHP_NAND_LL_OP_WE_MASK                                    0x00020000
+#define BCHP_NAND_LL_OP_WE_SHIFT                                   17
+#define BCHP_NAND_LL_OP_WE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: RE [16:16] */
+#define BCHP_NAND_LL_OP_RE_MASK                                    0x00010000
+#define BCHP_NAND_LL_OP_RE_SHIFT                                   16
+#define BCHP_NAND_LL_OP_RE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: DATA [15:00] */
+#define BCHP_NAND_LL_OP_DATA_MASK                                  0x0000ffff
+#define BCHP_NAND_LL_OP_DATA_SHIFT                                 0
+#define BCHP_NAND_LL_OP_DATA_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *LL_RDDATA - Nand Flash Low Level Read Data
+ ***************************************************************************/
+/* NAND :: LL_RDDATA :: reserved0 [31:16] */
+#define BCHP_NAND_LL_RDDATA_reserved0_MASK                         0xffff0000
+#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT                        16
+
+/* NAND :: LL_RDDATA :: DATA [15:00] */
+#define BCHP_NAND_LL_RDDATA_DATA_MASK                              0x0000ffff
+#define BCHP_NAND_LL_RDDATA_DATA_SHIFT                             0
+#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE                          0x00412a00
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_START                         0
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_END                           127
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE                  32
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+/* NAND :: FLASH_CACHEi :: WORD [31:00] */
+#define BCHP_NAND_FLASH_CACHEi_WORD_MASK                           0xffffffff
+#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT                          0
+
+
+#endif /* #ifndef BCHP_NAND_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_sata_top_ctrl.h b/include/linux/brcmstb/7360a0/bchp_sata_top_ctrl.h
new file mode 100644
index 0000000..8b921ce
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_sata_top_ctrl.h
@@ -0,0 +1,164 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_sata_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:19p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SATA_TOP_CTRL_H__
+#define BCHP_SATA_TOP_CTRL_H__
+
+/***************************************************************************
+ *SATA_TOP_CTRL - SATA3 MISC Control Registers
+ ***************************************************************************/
+#define BCHP_SATA_TOP_CTRL_Version               0x00180020 /* SATA3 Version Register */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL              0x00180024 /* SATA3 System Bus Access Control Register */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL               0x00180028 /* SATA3 Test Port Control register */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1            0x0018002c /* SATA3 phy interface control 1 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2            0x00180030 /* SATA3 phy interface control 2 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3            0x00180034 /* SATA3 phy interface control 3 */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT           0x00180038 /* SATA3 TP OUT */
+
+/***************************************************************************
+ *Version - SATA3 Version Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: Version :: reserved0 [31:08] */
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_MASK                  0xffffff00
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_SHIFT                 8
+
+/* SATA_TOP_CTRL :: Version :: major_version [07:04] */
+#define BCHP_SATA_TOP_CTRL_Version_major_version_MASK              0x000000f0
+#define BCHP_SATA_TOP_CTRL_Version_major_version_SHIFT             4
+#define BCHP_SATA_TOP_CTRL_Version_major_version_DEFAULT           0x00000000
+
+/* SATA_TOP_CTRL :: Version :: minor_version [03:00] */
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_MASK              0x0000000f
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_SHIFT             0
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_DEFAULT           0x00000001
+
+/***************************************************************************
+ *BUS_CTRL - SATA3 System Bus Access Control Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_31_17 [31:17] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_MASK            0xfffe0000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_SHIFT           17
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_DEFAULT         0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: overide_hwinit_registers [16:16] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_MASK  0x00010000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_SHIFT 16
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_DEFAULT 0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_15_8 [15:08] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_MASK             0x0000ff00
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_SHIFT            8
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_DEFAULT          0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: piodata_endian_ctrl [07:06] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_MASK       0x000000c0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SHIFT      6
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadata_endian_ctrl [05:04] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_MASK       0x00000030
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SHIFT      4
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadesc_endian_ctrl [03:02] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_MASK       0x0000000c
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SHIFT      2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: reg_endian_ctrl [01:00] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_MASK           0x00000003
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SHIFT          0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_DEFAULT        0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SwapEndianess  2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_HalfWordSwap   1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_NoSwap         0
+
+/***************************************************************************
+ *TP_CTRL - SATA3 Test Port Control register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: TP_CTRL :: tp_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_MASK                    0xffffffff
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_SHIFT                   0
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_1 - SATA3 phy interface control 1
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_1 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_2 - SATA3 phy interface control 2
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_2 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_3 - SATA3 phy interface control 3
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_3 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *SATA_TP_OUT - SATA3 TP OUT
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: SATA_TP_OUT :: TP_OUT [31:00] */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_MASK                 0xffffffff
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_SHIFT                0
+
+#endif /* #ifndef BCHP_SATA_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_sdio_0_cfg.h b/include/linux/brcmstb/7360a0/bchp_sdio_0_cfg.h
new file mode 100644
index 0000000..72e3555
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_sdio_0_cfg.h
@@ -0,0 +1,627 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Apr 23 03:10:13 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SDIO_0_CFG_H__
+#define BCHP_SDIO_0_CFG_H__
+
+/***************************************************************************
+ *SDIO_0_CFG - SDIO_0 (CARD) Configuration Registers
+ ***************************************************************************/
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1          0x00410100 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2          0x00410104 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL               0x00410108 /* SDIO TP_OUT Control Register */
+#define BCHP_SDIO_0_CFG_CAP_REG0                 0x0041010c /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_CAP_REG1                 0x00410110 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET1                  0x00410114 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET2                  0x00410118 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY           0x0041011c /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV               0x00410120 /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_IP_DLY                   0x00410130 /* SDIO Host input delay register */
+#define BCHP_SDIO_0_CFG_OP_DLY                   0x00410134 /* SDIO Host output delay register */
+#define BCHP_SDIO_0_CFG_TUNING                   0x00410138 /* SDIO Host tuning configuration register */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL                0x0041013c /* SDIO Host 1p8V control logic select register */
+#define BCHP_SDIO_0_CFG_SCRATCH                  0x004101fc /* SDIO Scratch Register */
+#define BCHP_SDIO_0_CFG_VERSION                  0x004101f0 /* SDIO VERSION Register */
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL1 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_SEL_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_MASK    0x80000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_SHIFT   31
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_DEFAULT 0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_LEV [30:30] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_MASK       0x40000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_SHIFT      30
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: CFG_RESERVED [29:29] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_MASK          0x20000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_SHIFT         29
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: RETUNING_REQ [28:28] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_MASK          0x10000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_SHIFT         28
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DDR_TAP_DELAY [27:24] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_MASK         0x0f000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_SHIFT        24
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_DEFAULT      0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DELAY_CTRL [23:21] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_MASK            0x00e00000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_SHIFT           21
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_DEFAULT         0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_ENA [20:20] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_MASK       0x00100000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_SHIFT      20
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_PULSE [19:19] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_MASK     0x00080000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_SHIFT    19
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DATA_PENDING [18:18] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_MASK          0x00040000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_SHIFT         18
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WR_FLUSH [17:17] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_MASK              0x00020000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_SHIFT             17
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: MF_NUM_WR [16:16] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_MASK             0x00010000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_SHIFT            16
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WORD_ABO [15:15] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_MASK              0x00008000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_SHIFT             15
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NBO [14:14] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_MASK             0x00004000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_SHIFT            14
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NHW [13:13] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_MASK             0x00002000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_SHIFT            13
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: BUFFER_ABO [12:12] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_MASK            0x00001000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_SHIFT           12
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_DEFAULT         0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_BUF_ACC [11:11] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_MASK           0x00000800
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_SHIFT          11
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_DEFAULT        0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SEQ_EN [10:10] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_MASK            0x00000400
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_SHIFT           10
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_DEFAULT         0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_RD_THRESH [09:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_MASK         0x000003e0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_SHIFT        5
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_DEFAULT      0x00000002
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SIZE [04:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_MASK              0x0000001f
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_SHIFT             0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_DEFAULT           0x00000004
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL2 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved0 [31:08] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_MASK             0xffffff00
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_SHIFT            8
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_BYTE [07:06] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_MASK     0x000000c0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_SHIFT    6
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved1 [05:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_MASK             0x00000020
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_SHIFT            5
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_HW [04:04] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_MASK       0x00000010
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_SHIFT      4
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_DEFAULT    0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_WR [03:02] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_MASK      0x0000000c
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_SHIFT     2
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_DEFAULT   0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_RD [01:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_MASK      0x00000003
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_SHIFT     0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_DEFAULT   0x00000000
+
+/***************************************************************************
+ *TP_OUT_SEL - SDIO TP_OUT Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TP_OUT_SEL :: reserved0 [31:01] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_MASK                  0xfffffffe
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_SHIFT                 1
+
+/* SDIO_0_CFG :: TP_OUT_SEL :: TP_OUT_SELECT [00:00] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_MASK              0x00000001
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_SHIFT             0
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *CAP_REG0 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG0 :: DDR50_SUPPORT [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_SHIFT               31
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_DEFAULT             0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SD104_SUPPORT [30:30] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_MASK                0x40000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_SHIFT               30
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDR50 [29:29] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_MASK                        0x20000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_SHIFT                       29
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_DEFAULT                     0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SLOT_TYPE [28:27] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_MASK                    0x18000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_SHIFT                   27
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_DEFAULT                 0x00000002
+
+/* SDIO_0_CFG :: CAP_REG0 :: ASYNCH_INT_SUPPORT [26:26] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_MASK           0x04000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_SHIFT          26
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_DEFAULT        0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 64B_SYS_BUS_SUPPORT [25:25] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_MASK          0x02000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_SHIFT         25
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 1_8V_SUPPORT [24:24] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_MASK                 0x01000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_SHIFT                24
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_DEFAULT              0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_0V_SUPPORT [23:23] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_MASK                 0x00800000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_SHIFT                23
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_3V_SUPPORT [22:22] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_MASK                 0x00400000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_SHIFT                22
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_DEFAULT              0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SUSP_RES_SUPPORT [21:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_MASK             0x00200000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_SHIFT            21
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDMA_SUPPORT [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_MASK                 0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_SHIFT                20
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_DEFAULT              0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: HIGH_SPEED_SUPPORT [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_MASK           0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_SHIFT          19
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_DEFAULT        0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: ADMA2_SUPPORT [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_MASK                0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_SHIFT               18
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_DEFAULT             0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: EXTENDED_MEDIA_SUPPORT [17:17] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_MASK       0x00020000
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_SHIFT      17
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: MAX_BL [16:15] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_MASK                       0x00018000
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_SHIFT                      15
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_DEFAULT                    0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: BASE_FREQ [14:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_MASK                    0x00007f80
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_SHIFT                   7
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_DEFAULT                 0x00000064
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_CLK_UNIT [06:06] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_MASK             0x00000040
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_SHIFT            6
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_FREQ [05:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_MASK                 0x0000003f
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_SHIFT                0
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_DEFAULT              0x00000032
+
+/***************************************************************************
+ *CAP_REG1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_REG_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_MASK             0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_SHIFT            31
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved0 [30:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_MASK                    0x7fe00000
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_SHIFT                   21
+
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_1_stuff [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_MASK                  0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_SHIFT                 20
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_BLK_MODE [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_MASK                 0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_SHIFT                19
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_MODE [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_MASK                     0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_SHIFT                    18
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_DEFAULT                  0x00000001
+
+/* SDIO_0_CFG :: CAP_REG1 :: CLK_MULT [17:10] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_MASK                     0x0003fc00
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_SHIFT                    10
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_MODES [09:08] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_MASK               0x00000300
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_SHIFT              8
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_DEFAULT            0x00000002
+
+/* SDIO_0_CFG :: CAP_REG1 :: USE_TUNING [07:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_MASK                   0x00000080
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_SHIFT                  7
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_DEFAULT                0x00000001
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_TIMER [06:03] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_MASK               0x00000078
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_SHIFT              3
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_DEFAULT            0x0000000a
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_D_SUPPORT [02:02] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_MASK             0x00000004
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_SHIFT            2
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_C_SUPPORT [01:01] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_MASK             0x00000002
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_SHIFT            1
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_A_SUPPORT [00:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_MASK             0x00000001
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_SHIFT            0
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PRESET1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET1 :: PRESET1_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET100 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_MASK                     0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_SHIFT                    16
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET50 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_MASK                      0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_SHIFT                     0
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_DEFAULT                   0x00000001
+
+/***************************************************************************
+ *PRESET2 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET2 :: PRESET2_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET2 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET25 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_MASK                      0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_SHIFT                     16
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_DEFAULT                   0x00000002
+
+/* SDIO_0_CFG :: PRESET2 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET12P5 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_MASK                    0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_SHIFT                   0
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_DEFAULT                 0x00000003
+
+/***************************************************************************
+ *SD_CLOCK_DELAY - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_SEL [31:31] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_MASK        0x80000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_SHIFT       31
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_DEFAULT     0x00000001
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY_OVERRIDE [30:30] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_MASK 0x40000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_SHIFT 30
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_DEFAULT 0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved0 [29:12] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_MASK              0x3ffff000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_SHIFT             12
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: OUTPUT_CLOCK_DELAY [11:08] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_MASK     0x00000f00
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_SHIFT    8
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INTERNAL_CLOCK_DELAY [07:04] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_MASK   0x000000f0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_SHIFT  4
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_DEFAULT 0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_MASK      0x0000000f
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_SHIFT     0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_DEFAULT   0x00000000
+
+/***************************************************************************
+ *SD_PAD_DRV - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_PAD_DRV :: OVERRIDE_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_SHIFT               31
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved0 [30:23] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_MASK                  0x7f800000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_SHIFT                 23
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CLK_VAL [22:20] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_MASK                    0x00700000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_SHIFT                   20
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved1 [19:19] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_MASK                  0x00080000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_SHIFT                 19
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CMD_VAL [18:16] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_MASK                    0x00070000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_SHIFT                   16
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved2 [15:15] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_MASK                  0x00008000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_SHIFT                 15
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT3_VAL [14:12] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_MASK                   0x00007000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_SHIFT                  12
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved3 [11:11] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_MASK                  0x00000800
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_SHIFT                 11
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT2_VAL [10:08] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_MASK                   0x00000700
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_SHIFT                  8
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved4 [07:07] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_MASK                  0x00000080
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_SHIFT                 7
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT1_VAL [06:04] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_MASK                   0x00000070
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_SHIFT                  4
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved5 [03:03] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_MASK                  0x00000008
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_SHIFT                 3
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT0_VAL [02:00] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_MASK                   0x00000007
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_SHIFT                  0
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_DEFAULT                0x00000005
+
+/***************************************************************************
+ *IP_DLY - SDIO Host input delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_DEFAULT                   0x00000000
+
+/* SDIO_0_CFG :: IP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: IP_DLY :: IP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_DEFAULT               0x00000003
+
+/* SDIO_0_CFG :: IP_DLY :: reserved1 [15:06] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_MASK                      0x0000ffc0
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_SHIFT                     6
+
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_DELAY [05:00] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_MASK                   0x0000003f
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_DEFAULT                0x00000000
+
+/***************************************************************************
+ *OP_DLY - SDIO Host output delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_DEFAULT                   0x00000000
+
+/* SDIO_0_CFG :: OP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: OP_DLY :: OP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_DEFAULT               0x00000003
+
+/* SDIO_0_CFG :: OP_DLY :: reserved1 [15:04] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_MASK                      0x0000fff0
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_SHIFT                     4
+
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_MASK                   0x0000000f
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TUNING - SDIO Host tuning configuration register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TUNING :: reserved0 [31:04] */
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_MASK                      0xfffffff0
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_SHIFT                     4
+
+/* SDIO_0_CFG :: TUNING :: TUNING_CMD_SUCCESS_CNT [03:00] */
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_MASK         0x0000000f
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_SHIFT        0
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_DEFAULT      0x00000008
+
+/***************************************************************************
+ *VOLT_CTRL - SDIO Host 1p8V control logic select register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VOLT_CTRL :: reserved0 [31:05] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_MASK                   0xffffffe0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_SHIFT                  5
+
+/* SDIO_0_CFG :: VOLT_CTRL :: POW_INV_EN [04:04] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_MASK                  0x00000010
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_SHIFT                 4
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_VAL [03:03] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_MASK                    0x00000008
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_SHIFT                   3
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_DEFAULT                 0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_INV_EN [02:02] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_MASK                 0x00000004
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_SHIFT                2
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_CTRL_SEL [01:00] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_MASK               0x00000003
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_SHIFT              0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SCRATCH - SDIO Scratch Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SCRATCH :: SCRATCH_BITS [31:00] */
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_MASK                  0xffffffff
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_SHIFT                 0
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_DEFAULT               0x00000000
+
+/***************************************************************************
+ *VERSION - SDIO VERSION Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VERSION :: SD_VER [31:24] */
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_MASK                        0xff000000
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_SHIFT                       24
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_DEFAULT                     0x00000030
+
+/* SDIO_0_CFG :: VERSION :: MMC_VER [23:16] */
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_MASK                       0x00ff0000
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_SHIFT                      16
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_DEFAULT                    0x00000044
+
+/* SDIO_0_CFG :: VERSION :: REV [15:08] */
+#define BCHP_SDIO_0_CFG_VERSION_REV_MASK                           0x0000ff00
+#define BCHP_SDIO_0_CFG_VERSION_REV_SHIFT                          8
+#define BCHP_SDIO_0_CFG_VERSION_REV_DEFAULT                        0x000000a7
+
+/* SDIO_0_CFG :: VERSION :: A2S_VER [07:00] */
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_MASK                       0x000000ff
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_SHIFT                      0
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_DEFAULT                    0x00000001
+
+#endif /* #ifndef BCHP_SDIO_0_CFG_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/7360a0/bchp_sun_top_ctrl.h
new file mode 100644
index 0000000..bbbc757
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_sun_top_ctrl.h
@@ -0,0 +1,6201 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Jan 27 16:43:37 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_sun_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/3   1/27/12 5:26p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SUN_TOP_CTRL_H__
+#define BCHP_SUN_TOP_CTRL_H__
+
+/***************************************************************************
+ *SUN_TOP_CTRL - Top Control registers
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID         0x00404000 /* Chip family ID */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID             0x00404004 /* Product Revision ID */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x0040401c /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x00404020 /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x00404024 /* Bond option value register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x00404028 /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x0040402c /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x00404030 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x00404034 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x00404038 /* Semaphore channel 0 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x0040403c /* Semaphore channel 1 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x00404040 /* Semaphore channel 2 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x00404044 /* Semaphore channel 3 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x00404048 /* Semaphore channel 4 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x0040404c /* Semaphore channel 5 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x00404050 /* Semaphore channel 6 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x00404054 /* Semaphore channel 7 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x00404058 /* Semaphore channel 8 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x0040405c /* Semaphore channel 9 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x00404060 /* Semaphore channel 10 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x00404064 /* Semaphore channel 11 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x00404068 /* Semaphore channel 12 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x0040406c /* Semaphore channel 13 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x00404070 /* Semaphore channel 14 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x00404074 /* Semaphore channel 15 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x00404078 /* General watchdog timer 0 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x0040407c /* General watchdog timer 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x00404080 /* General control register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x00404084 /* General control register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x00404088 /* General control register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x0040408c /* General control register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x00404090 /* General control register 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x00404094 /* General control register 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x00404098 /* General status register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x0040409c /* General status register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x004040a0 /* General status register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x00404100 /* Pinmux control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x00404104 /* Pinmux control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x00404108 /* Pinmux control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x0040410c /* Pinmux control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x00404110 /* Pinmux control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x00404114 /* Pinmux control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x00404118 /* Pinmux control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x0040411c /* Pinmux control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x00404120 /* Pinmux control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x00404124 /* Pinmux control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10        0x00404128 /* Pinmux control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11        0x0040412c /* Pinmux control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12        0x00404130 /* Pinmux control register 12 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13        0x00404134 /* Pinmux control register 13 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14        0x00404138 /* Pinmux control register 14 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15        0x0040413c /* Pinmux control register 15 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x00404140 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x00404144 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x00404148 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x0040414c /* Pad pull-up/pull-down control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x00404150 /* Pad pull-up/pull-down control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5     0x00404154 /* Pad pull-up/pull-down control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6     0x00404158 /* Pad pull-up/pull-down control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7     0x0040415c /* Pad pull-up/pull-down control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8     0x00404160 /* Pad pull-up/pull-down control register 8 */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x00404164 /* Bypass clock unselect register 0 */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x00404300 /* Reset control */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE    0x00404304 /* Reset source enable */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET        0x00404308 /* Software master reset */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION     0x0040430c /* Hardware reset extension */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR          0x00404310 /* Reset Monitor */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x00404314 /* Reset history */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET          0x00404318 /* Software init 0 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR        0x0040431c /* Software init 0 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS       0x00404320 /* Software init 0 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR  0x00404324 /* Security software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET          0x00404330 /* Software init 1 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR        0x00404334 /* Software init 1 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS       0x00404338 /* Software init 1 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR  0x0040433c /* Security software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x00404364 /* Scratch register */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x00404368 /* Spare control bits reserved for future use */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x00404380 /* Test port control */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x00404384 /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x00404388 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x0040438c /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x00404390 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x00404394 /* EJTAG input bus enables */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x00404398 /* EJTAG output select */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL        0x0040439c /* UART Router select */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL             0x004043a0 /* VTRAP Control */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS           0x004043a4 /* VTRAP Status */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x00404400 /* Serial Slave Port configuration register */
+#define BCHP_SUN_TOP_CTRL_SERS_REV               0x00404420 /* SERS Revision Register */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x00404424 /* SERS Configuration Register */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x00404514 /* Block select for RO testmode */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION     0x00404518 /* Test configuration */
+
+/***************************************************************************
+ *CHIP_FAMILY_ID - Chip family ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT    0x73600000
+
+/***************************************************************************
+ *PRODUCT_ID - Product Revision ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK               0xffffffff
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT            0x73600000
+
+/***************************************************************************
+ *BSP_FEATURE_TABLE_ADDR - BSP feature table address
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_VALUE_0 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [07:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT   0x00000007
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [03:03] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd [02:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_MASK            0x00000007
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STRAP_VALUE_1 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xfffffff0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            4
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias_sel [03:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_MASK  0x0000000e
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_DEFAULT 0x00000004
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK     0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT  0x00000001
+
+/***************************************************************************
+ *BOND_STATUS - Bond option value register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1
+
+/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_0 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_0 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rsvd_ob_disable [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ob_disable_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ob_disable_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ob_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rsvd_ds_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ds_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ds_disable_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ds_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rsvd_isdbt_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_isdbt_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_isdbt_disable_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_isdbt_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_genet_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet_disable_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avc_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_directv_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sata_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sds0_tuner_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hd_display_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ephy_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tfec_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ldpc_disable [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_chip_variant [13:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_chip_variant_MASK 0x00003c00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_chip_variant_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_chip_variant_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 0x00000003
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_TEST_1 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_29 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_28 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_27 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_26 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_25 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_24 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_23 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_22 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_21 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_20 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_19 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_18 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_17 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_16 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_15 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_14 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_0 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_alt_prod_base_rev_enable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_alt_prod_base_rev_enable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_alt_prod_base_rev_enable_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_alt_prod_base_rev_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_0 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_0 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rsvd_ob_disable [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_ob_disable_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_ob_disable_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rsvd_ds_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_ds_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_ds_disable_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rsvd_isdbt_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_isdbt_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_isdbt_disable_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_genet_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet_disable_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avc_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avc_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avc_disable_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_directv_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sata_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sds0_tuner_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sds0_tuner_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sds0_tuner_disable_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hd_display_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ephy_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tfec_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec_disable_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ldpc_disable [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc_disable_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc_disable_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_chip_variant [13:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_chip_variant_MASK 0x00003c00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_chip_variant_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_1 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_29 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_28 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_27 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_26 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_25 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_24 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_23 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_22 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_21 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_20 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_19 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_18 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_17 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_16 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_15 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_14 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 6
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_0 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_SHIFT 2
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_alt_prod_base_rev_enable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_alt_prod_base_rev_enable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_alt_prod_base_rev_enable_SHIFT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_SHIFT 0
+
+/***************************************************************************
+ *SEMAPHORE_0 - Semaphore channel 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_1 - Semaphore channel 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_2 - Semaphore channel 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_3 - Semaphore channel 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_4 - Semaphore channel 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_5 - Semaphore channel 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_6 - Semaphore channel 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_7 - Semaphore channel 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_8 - Semaphore channel 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_9 - Semaphore channel 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_10 - Semaphore channel 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_11 - Semaphore channel 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_12 - Semaphore channel 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_13 - Semaphore channel 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_14 - Semaphore channel 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_15 - Semaphore channel 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_0 - General watchdog timer 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_1 - General watchdog timer 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_1 - General control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0xffff0000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           16
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_2 - General control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: usb0_pwrflt_2_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: usb0_pwrflt_1_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_3 - General control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_4 - General control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_5 - General control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK          0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT         8
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_1 - General status register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_2 - General status register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   8
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_mode [07:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_MASK 0x000000f0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_mode [03:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK    0xffff8000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT   15
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_vregcntl [14:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_MASK 0x00007ffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_pwrdn [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_MASK    0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_SHIFT   1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_vregcntl_en [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK    0xfffffff0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT   4
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_3_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_2_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xffc00000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   22
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_pwrdn [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_MASK    0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_SHIFT   21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_vregcntl [20:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_MASK 0x001ffffe
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_vregcntl_en [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xffffff80
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_hys_en [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_oeb [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_do [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_src [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_16MA 7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_02 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_GPIO_02           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_EBI_ADDR2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MII_TX_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_PM_GPIO_02        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_01 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_GPIO_01           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_EBI_ADDR1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MII_RX_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_PM_GPIO_01        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_00 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_GPIO_00           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_EBI_ADDR0         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MII_RX_DV         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_PM_GPIO_00        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_sck [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_MASK               0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_SHIFT              16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_DEFAULT            0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_SF_SCK             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_PM_SF_SCK          1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_mosi [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_SF_MOSI           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_PM_SF_MOSI        1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_miso [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_SF_MISO           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_PM_SF_MISO        1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_24 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_GPIO_24           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_SDS0_DSEC_TXEN    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_PM_GPIO_24        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_23 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_GPIO_23           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_SDS0_DSEC_TXOUT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_PM_GPIO_23        2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_10 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_GPIO_10           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_EBI_ADDR10        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MII_TXD_00        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_PM_GPIO_10        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_09 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_GPIO_09           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_EBI_ADDR9         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MII_TXD_01        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_PM_GPIO_09        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_08 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_GPIO_08           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_EBI_ADDR8         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MII_TXD_02        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_PM_GPIO_08        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_07 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_GPIO_07           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_EBI_ADDR7         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_MII_TXD_03        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_PM_GPIO_07        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_06 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_GPIO_06           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_EBI_ADDR6         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_MII_RXD_00        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_PM_GPIO_06        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_05 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_GPIO_05           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_EBI_ADDR5         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_MII_RXD_01        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_PM_GPIO_05        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_04 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_GPIO_04           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_EBI_ADDR4         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_MII_RXD_02        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_PM_GPIO_04        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_03 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_GPIO_03           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_EBI_ADDR3         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_MII_RXD_03        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_PM_GPIO_03        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_18 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_GPIO_18           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_EBI_CS0B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_PM_GPIO_18        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_17 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_GPIO_17           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_EBI_RWB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_PM_GPIO_17        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_16 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_GPIO_16           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_EBI_WE1B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_PM_GPIO_16        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_15 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_GPIO_15           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_EBI_WAITB         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_PM_GPIO_15        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_14 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_GPIO_14           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_EBI_ADDR14        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_MII_COL           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_PM_GPIO_14        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_13 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_GPIO_13           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_EBI_ADDR13        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_MII_TX_ER         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_PM_GPIO_13        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_12 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_GPIO_12           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_EBI_ADDR12        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_MII_RX_ER         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_PM_GPIO_12        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_11 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_GPIO_11           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_EBI_ADDR11        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_MII_TX_EN         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_PM_GPIO_11        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_28 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_GPIO_28           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_EBI_DATA3         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_TP_OUT_23         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_TP_IN_23          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_PM_GPIO_28        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_27 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_GPIO_27           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_EBI_DATA2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_TP_OUT_22         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_TP_IN_22          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_PM_GPIO_27        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_26 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_GPIO_26           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_EBI_DATA1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_TP_OUT_21         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_TP_IN_21          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_PM_GPIO_26        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_25 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_GPIO_25           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_EBI_DATA0         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_TP_OUT_20         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_TEST_THP          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_TP_IN_20          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_PM_GPIO_25        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_22 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_GPIO_22           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_EBI_CS4B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_SPI_M_SS0B        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_PM_GPIO_22        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_21 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_GPIO_21           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_EBI_CS3B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_PM_GPIO_21        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_20 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_GPIO_20           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_EBI_CS2B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_TP_OUT_07         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_PM_GPIO_20        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_19 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_GPIO_19           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_EBI_CS1B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_PM_GPIO_19        2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_4 - Pinmux control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_36 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_GPIO_36           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_EBI_DATA11        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_SC1_IO            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_PM_GPIO_36        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_35 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_GPIO_35           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_EBI_DATA10        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_SC1_RST           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_PM_GPIO_35        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_34 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_GPIO_34           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_EBI_DATA9         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_SC1_CLK           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_PM_GPIO_34        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_33 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_GPIO_33           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_EBI_DATA8         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_SC1_VCC           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_PM_GPIO_33        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_32 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_GPIO_32           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_EBI_DATA7         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_OUT_27         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_IN_27          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_OUT_21         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_PM_GPIO_32        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_31 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_GPIO_31           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_EBI_DATA6         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_OUT_26         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_IN_26          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_OUT_20         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_PM_GPIO_31        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_30 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_GPIO_30           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_EBI_DATA5         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_TP_OUT_25         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_TP_IN_25          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_PM_GPIO_30        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_29 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_GPIO_29           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_EBI_DATA4         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_TP_OUT_24         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_TP_IN_24          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_PM_GPIO_29        4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_5 - Pinmux control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_44 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_GPIO_44           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_EBI_TSB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_OUT_31         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_IN_31          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_IN_19          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_OUT_26         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_PM_GPIO_44        6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_43 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_GPIO_43           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_EBI_DSB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_OUT_30         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_IN_30          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_IN_18          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_OUT_25         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_PM_GPIO_43        6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_42 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_GPIO_42           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_EBI_WE0B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_OUT_29         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_IN_29          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_OUT_23         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_PM_GPIO_42        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_41 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_GPIO_41           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_EBI_RDB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_OUT_28         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_IN_28          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_OUT_22         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_PM_GPIO_41        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_40 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_GPIO_40           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_EBI_DATA15        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SPI_M_SCK         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_MII_COL           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SC1_AUX2          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_PM_GPIO_40        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_39 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_GPIO_39           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_EBI_DATA14        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SPI_M_MISO        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_MII_TX_ER         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SC1_AUX1          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_PM_GPIO_39        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_38 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_GPIO_38           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_EBI_DATA13        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SPI_M_MOSI        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_MII_RX_ER         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SC1_VPP           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_PM_GPIO_38        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_37 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_GPIO_37           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_EBI_DATA12        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_SC1_PRES          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_PM_GPIO_37        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_6 - Pinmux control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_52 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_GPIO_52           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_POD2CHIP_MDI5     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_PPKT_I_DATA_5     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_PM_GPIO_52        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_51 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_GPIO_51           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_POD2CHIP_MDI4     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_PPKT_I_DATA_4     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_PM_GPIO_51        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_50 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_GPIO_50           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_POD2CHIP_MDI3     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_PPKT_I_DATA_3     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_PM_GPIO_50        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_49 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_GPIO_49           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_POD2CHIP_MDI2     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_PPKT_I_DATA_2     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_PM_GPIO_49        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_48 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_GPIO_48           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_POD2CHIP_MDI1     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_PPKT_I_DATA_1     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_PM_GPIO_48        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_47 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_GPIO_47           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_POD2CHIP_MDI0     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_PPKT_I_DATA_0     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_PM_GPIO_47        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_46 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_GPIO_46           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_POD2CHIP_MCLKI    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_PPKT_I_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_EBI_ADDR14        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_PM_GPIO_46        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_45 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_GPIO_45           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_NAND_RBB          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_TP_OUT_16         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_PM_GPIO_45        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_7 - Pinmux control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_60 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_GPIO_60           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_CHIP2POD_MDO2     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_RMXP_DATA2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_EBI_ADDR20        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_SDS0_O_DATA_2     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_PM_GPIO_60        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_59 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_GPIO_59           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_CHIP2POD_MDO1     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_RMXP_DATA1        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_EBI_ADDR19        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_SDS0_O_DATA_1     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_PM_GPIO_59        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_58 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_GPIO_58           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_CHIP2POD_MDO0     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_RMXP_DATA0        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_EBI_ADDR18        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_SDS0_O_DATA_0     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_PM_GPIO_58        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_57 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_GPIO_57           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_CHIP2POD_MCLKO    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_RMXP_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_EBI_ADDR15        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_SDS0_O_CLK        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_PM_GPIO_57        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_56 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_GPIO_56           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_POD2CHIP_MIVAL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_PPKT_I_VALID      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_PM_GPIO_56        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_55 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_GPIO_55           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_POD2CHIP_MISTRT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_PPKT_I_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_PM_GPIO_55        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_54 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_GPIO_54           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_POD2CHIP_MDI7     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_PPKT_I_DATA_7     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_PM_GPIO_54        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_53 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_GPIO_53           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_POD2CHIP_MDI6     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_PPKT_I_DATA_6     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_PM_GPIO_53        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_8 - Pinmux control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_68 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_GPIO_68           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_POD2CHIP_MICLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_PPKT_I_ERROR      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_EBI_ADDR13        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_PM_GPIO_68        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_67 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_GPIO_67           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_CHIP2POD_MOVAL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_RMXP_VALID        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_EBI_ADDR16        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_SDS0_O_VALID      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_PM_GPIO_67        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_66 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_GPIO_66           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_CHIP2POD_MOSTRT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_RMXP_SYNC         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_EBI_ADDR17        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_SDS0_O_SYNC       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_PM_GPIO_66        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_65 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_GPIO_65           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_CHIP2POD_MDO7     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_RMXP_DATA7        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_EBI_ADDR25        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_SDS0_O_DATA_7     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_PM_GPIO_65        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_64 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_GPIO_64           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_CHIP2POD_MDO6     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_RMXP_DATA6        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_EBI_ADDR24        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_SDS0_O_DATA_6     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_PM_GPIO_64        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_63 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_GPIO_63           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_CHIP2POD_MDO5     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_RMXP_DATA5        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_EBI_ADDR23        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_SDS0_O_DATA_5     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_PM_GPIO_63        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_62 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_GPIO_62           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_CHIP2POD_MDO4     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_RMXP_DATA4        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_EBI_ADDR22        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_SDS0_O_DATA_4     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_PM_GPIO_62        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_61 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_GPIO_61           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_CHIP2POD_MDO3     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_RMXP_DATA3        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_EBI_ADDR21        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_SDS0_O_DATA_3     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_PM_GPIO_61        5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_9 - Pinmux control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_76 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_GPIO_76           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_RMX0_SYNC         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_PKT1_SYNC         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_SDS0_DEMOD_SYNC   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_PM_GPIO_76        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_75 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_GPIO_75           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_RMX0_DATA         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_PKT1_DATA         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_CLK_OBSRV3        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_SDS0_DEMOD_DATA   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_PM_GPIO_75        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_74 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_GPIO_74           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_RMX0_CLK          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_PKT1_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_CLK_OBSRV2        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_SDS0_DEMOD_CLK    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_PM_GPIO_74        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_73 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_GPIO_73           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_RSVD_MPOD_M_SDI   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_PM_GPIO_73        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_72 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_DEFAULT           0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_GPIO_72           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_RSVD_MPOD_M_SDO   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_EBI_ADDR0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_PM_GPIO_72        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_71 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_DEFAULT           0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_GPIO_71           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_RSVD_MPOD_SCLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_EBI_ADDR1         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_PM_GPIO_71        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_70 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_DEFAULT           0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_GPIO_70           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_RSVD_MPOD_SCTL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_EBI_ADDR2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_SDS0_O_ERROR      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_PM_GPIO_70        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_69 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_GPIO_69           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_CHIP2POD_MOCLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_RMXP_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_EBI_ADDR12        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_AUD_FS_CLK1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_PM_GPIO_69        5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_10 - Pinmux control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_84 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_GPIO_84          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_SC0_AUX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_I2S_DATA0_IN     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_TP_OUT_13        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_PM_GPIO_84       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_83 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_GPIO_83          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_SC0_PRES         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_I2S_CLK0_IN      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_TP_OUT_12        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_PM_GPIO_83       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_82 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_GPIO_82          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_SC0_IO           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_TP_OUT_11        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_PM_GPIO_82       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_81 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_GPIO_81          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_SC0_RST          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_TP_OUT_10        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_PM_GPIO_81       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_80 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_GPIO_80          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_SC0_CLK          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_TP_OUT_09        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_PM_GPIO_80       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_79 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_GPIO_79          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_SC0_VCC          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_TP_OUT_08        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_PM_GPIO_79       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_78 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_GPIO_78          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_RMX0_PAUSE       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PKT1_ERROR       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PKT3_DATA        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_I2S_LR0_IN       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SDS0_DSEC_VCTL   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SDS0_DEMOD_ERR   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PM_GPIO_78       7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_77 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_GPIO_77          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_RMX0_VALID       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PKT1_VALID       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PKT3_CLK         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SPI_M_SS1B       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SDS0_DSEC_SELVTOP 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SDS0_DEMOD_VALID 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PM_GPIO_77       7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_11 - Pinmux control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_92 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_GPIO_92          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_UART_RX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_IR_OUT           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_ALT_TP_IN_02     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_POD2CHIP_MCLKI   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_PM_GPIO_92       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_91 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_GPIO_91          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_UART_TX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_PWM0             2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_ALT_TP_OUT_02    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_POD_EBI_DSB      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_PM_GPIO_91       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_90 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_GPIO_90          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_UART_RX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_VEC_VSYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_ALT_TP_IN_01     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_POD_EBI_WE0B     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_PM_GPIO_90       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_89 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_GPIO_89          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_UART_TX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_VEC_HSYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_ALT_TP_OUT_01    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_POD_EBI_RDB      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_PM_GPIO_89       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_88 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_GPIO_88          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_SPI_S_SSB        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_UART_RX0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_ALT_TP_IN_00     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_PM_GPIO_88       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_87 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_GPIO_87          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_SPI_S_MISO       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_UART_TX0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_ALT_TP_OUT_00    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_PM_GPIO_87       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_86 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_GPIO_86          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_SC0_VPP          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_USB0_PWRFLT_1    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_TP_OUT_15        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_PM_GPIO_86       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_85 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_GPIO_85          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_SC0_AUX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_I2S_LR0_IN       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_TP_OUT_14        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_USB0_PWRFLT_2    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_PM_GPIO_85       5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_12 - Pinmux control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_101 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_GPIO_101        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_USB0_PWRON_1    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_RMX1_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SDS0_DSEC_SELVTOP 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_TP_OUT_17       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SDS0_RF_AGC     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_ENET_ACTIVITY   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_PM_GPIO_101     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_100 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_GPIO_100        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_PKT2_ERROR      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SC1_VPP         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_VEC_HSYNC       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_UART_CTS2       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_CODEC_FSYNCB    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SPI_M_SS1B      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SC1_PRES        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_PM_GPIO_100     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_99 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_GPIO_99          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PKT2_VALID       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PKT3_SYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_IR_OUT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_UART_RX2         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_CODEC_SDI        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SPI_M_MISO       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SC1_IO           7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PM_GPIO_99       8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_98 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_GPIO_98          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_PKT2_SYNC        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_CODEC_MCLK       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SPI_M_SCK        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SC1_RST          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_PM_GPIO_98       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_97 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_GPIO_97          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_PKT2_DATA        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_UART_RTS2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_CODEC_SDO        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SPI_M_SS0B       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SC1_CLK          5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_PM_GPIO_97       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_96 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_GPIO_96          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_PKT2_CLK         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_UART_TX2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_CODEC_SCLK       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SPI_M_MOSI       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SC1_VCC          5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_PM_GPIO_96       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_94 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_GPIO_94          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SF_WPB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_EXT_IRQ3         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_PWM0             3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_UART_RTS0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_I2S_DATA0_IN     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SDS0_DSEC_TXEN   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_PM_GPIO_94       7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_93 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_GPIO_93          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SF_HOLDB         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_EXT_IRQ2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_VEC_VSYNC        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_UART_CTS0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_I2S_CLK0_IN      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SDS0_DSEC_TXOUT  6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_PM_GPIO_93       7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_13 - Pinmux control register 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_110 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_GPIO_110        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_MII_CRS         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_EBI_ADDR15      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_PM_GPIO_110     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_109 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_GPIO_109        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_MII_COL         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_PKT4_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR0_IN      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR0_OUT     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR1_OUT     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_SC1_AUX2        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_PM_GPIO_109     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_108 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_GPIO_108        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_MII_TX_ER       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_PKT4_DATA       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA0_IN    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA0_OUT   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA1_OUT   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_SC1_AUX1        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_TP_IN_31        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_PM_GPIO_108     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_107 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_GPIO_107        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_MII_RX_ER       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_PKT4_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK0_IN     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK0_OUT    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK1_OUT    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_SC1_VPP         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_TP_IN_30        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_PM_GPIO_107     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_105 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_GPIO_105        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_ENET_ACTIVITY   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_PWM1            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_CLK_OBSRV0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_CLK_27          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_AUD_FS_CLK0     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_SC_CLK_OUT      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_TP_OUT_19       7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_PM_GPIO_105     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_104 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_GPIO_104        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_USB0_PWRFLT_2   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_EXT_IRQ5        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_RMX1_SYNC       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_IR_INT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_SATA_MDCLK      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_PM_GPIO_104     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_103 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_GPIO_103        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_USB0_PWRFLT_1   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_EXT_IRQ4        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_RMX1_PAUSE      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_P1_INTR_1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_SATA_MDIO       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_PM_GPIO_103     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_102 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_GPIO_102        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_USB0_PWRON_2    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_RMX1_DATA       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SDS0_DSEC_VCTL  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_TP_OUT_18       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SDS0_IF_AGC     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_ENET_LINK       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_PM_GPIO_102     7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_14 - Pinmux control register 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_118 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_GPIO_118        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_RGMII_TXD_03    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_EBI_ADDR23      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SDIO0_DAT3      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_TP_OUT_27       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_PM_GPIO_118     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_117 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_GPIO_117        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_RGMII_RXD_00    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_EBI_ADDR22      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SDIO0_LED       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_TP_OUT_26       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_PM_GPIO_117     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_116 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_GPIO_116        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_RGMII_RXD_01    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_EBI_ADDR21      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SDIO0_CLK       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_TP_OUT_25       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_PM_GPIO_116     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_115 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_GPIO_115        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_RGMII_RXD_02    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_EBI_ADDR20      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_SDIO0_PWR0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_TP_OUT_24       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_PM_GPIO_115     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_114 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_GPIO_114        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_RGMII_RXD_03    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_EBI_ADDR19      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_SDIO0_WPROT     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_TP_OUT_23       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_PM_GPIO_114     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_113 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_GPIO_113        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_RGMII_TX_CLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_EBI_ADDR18      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_SDIO0_PRES      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_TP_OUT_22       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_PM_GPIO_113     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_112 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_GPIO_112        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_RGMII_RX_CLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_EBI_ADDR17      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_SDIO_VCTL       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_TP_OUT_21       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_PM_GPIO_112     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_111 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_GPIO_111        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_RGMII_RX_DV     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_EBI_ADDR16      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_TP_OUT_20       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_PM_GPIO_111     4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_15 - Pinmux control register 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: sgpio_03 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_SGPIO_03        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_BSC_M1_SDA      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_EXT_IRQ7        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_P1_INTR_1       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: sgpio_02 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_SGPIO_02        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_BSC_M1_SCL      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_EXT_IRQ6        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_124 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_GPIO_124        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_RGMII_MDIO      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_PM_GPIO_124     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_123 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_GPIO_123        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_RGMII_MDC       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_PM_GPIO_123     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_122 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_GPIO_122        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_RGMII_TX_EN     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_EBI_ADDR27      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_SDIO0_CMD       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_TP_OUT_31       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_PM_GPIO_122     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_121 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_GPIO_121        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_RGMII_TXD_00    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_EBI_ADDR26      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_SDIO0_DAT0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_TP_OUT_30       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_PM_GPIO_121     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_120 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_GPIO_120        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_RGMII_TXD_01    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_EBI_ADDR25      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_SDIO0_DAT1      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_TP_OUT_29       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_PM_GPIO_120     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_119 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_GPIO_119        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_RGMII_TXD_02    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_EBI_ADDR24      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_SDIO0_DAT2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_TP_OUT_28       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_PM_GPIO_119     5
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_07_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_06_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_05_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_04_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_03_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_02_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_01_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_00_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [13:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x00003c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       10
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_sck_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_MASK  0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_mosi_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_miso_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_24_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_23_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_22_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_21_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_20_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_19_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_18_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_17_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_16_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_15_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_14_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_13_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_12_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_11_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_10_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_09_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_08_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_39_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_38_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_37_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_36_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_35_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_34_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_33_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_32_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_31_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_30_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_29_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_28_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_27_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_26_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_25_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_54_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_53_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_52_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_51_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_50_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_49_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_48_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_47_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_46_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_45_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_44_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_43_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_42_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_41_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_40_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_69_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_68_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_67_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_66_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_65_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_64_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_63_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_62_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_61_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_60_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_59_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_58_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_57_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_56_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_55_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_84_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_83_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_82_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_81_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_80_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_79_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_78_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_77_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_76_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_75_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_74_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_73_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_72_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_71_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_70_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_100_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_99_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_98_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_97_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_96_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_94_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_93_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_92_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_91_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_90_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_89_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_88_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_87_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_86_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_85_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_116_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_115_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_114_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_113_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_112_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_111_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_110_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_109_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_108_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_107_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_105_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_104_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_103_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_102_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_101_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved0 [31:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_MASK        0xffc00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_SHIFT       22
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved1 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_MASK        0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_SHIFT       16
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_124_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_123_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_122_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_121_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_120_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_119_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_118_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_117_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffffc
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       2
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_24 [01:01] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_23 [00:00] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_CTRL - Reset control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0xfffffffe
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               1
+
+/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT   0x00000000
+
+/***************************************************************************
+ *RESET_SOURCE_ENABLE - Reset source enable
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK       0xfffffc00
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT      10
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_MASTER_RESET - Software master reset
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK           0xfffffffe
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT          1
+
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HW_RESET_EXTENSION - Hardware reset extension
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_MONITOR - Reset Monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT  7
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT   6
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT   4
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset history
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:17] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xfffe0000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            17
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [16:16] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 16
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [15:15] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 15
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [14:14] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 14
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [13:13] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 13
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_reset [12:12] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_MASK    0x00001000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT   12
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_reset [11:11] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT    11
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [10:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT       10
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK       0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT      9
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_dl_sw_reset [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK  0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT 8
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 7
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 6
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK   0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT  4
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0
+
+/***************************************************************************
+ *SW_INIT_0_SET - Software init 0 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_MASK           0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_SHIFT          31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_MASK   0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_SHIFT  30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_MASK          0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_MASK   0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_SHIFT  28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_MASK   0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_SHIFT  27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK        0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT       26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_MASK   0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_SHIFT  25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK          0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK   0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT  23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_MASK   0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_SHIFT  22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK          0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT         21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_MASK   0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_SHIFT  20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK         0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT        19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK           0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT          18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK   0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT  17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_MASK         0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_SHIFT        16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK           0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT          15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK           0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT          14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_MASK          0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_SHIFT         13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_MASK   0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_SHIFT  12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_MASK   0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_SHIFT  11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT       10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK           0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT          9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK           0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK           0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT          6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_SHIFT   4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT   0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_CLEAR - Software init 0 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_MASK         0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_SHIFT        31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_MASK        0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_SHIFT       29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK      0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT     26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK        0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT       24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK        0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT       21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK       0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT      19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK         0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT        18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_MASK       0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK         0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT        15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK         0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT        14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_MASK        0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_SHIFT       13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK      0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT     10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK         0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT        9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK         0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK         0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT        6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_STATUS - Software init 0 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_MASK        0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_SHIFT       31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_MASK       0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_SHIFT      29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK       0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK       0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT      21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK      0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT     19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK        0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT       18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_MASK      0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK        0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT       15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK        0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT       14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_MASK       0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_SHIFT      13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK        0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT   2
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT       1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_MASK   0x80000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT  31
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_MASK  0x20000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK  0x01000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK  0x00200000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK   0x00040000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT  18
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK   0x00008000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT  15
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK   0x00004000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT  14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_avd0_sw_init_MASK  0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK   0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT  9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK   0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT  8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT  6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_1_SET - Software init 1 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK             0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT            5
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK        0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT       4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK        0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT       3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_MASK        0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_SHIFT       2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_DEFAULT        0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_CLEAR - Software init 1 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK           0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT          5
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_MASK    0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_SHIFT   1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_MASK         0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_STATUS - Software init 1 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK          0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT         5
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK     0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT    3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_SHIFT  1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_DEFAULT     0x00000001
+
+/***************************************************************************
+ *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK     0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT    5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT  0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xffffffe0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK   0xffffffe0
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT  5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK  0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xffffffe0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 5
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xffffffe0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 5
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL - Spare control bits reserved for future use
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT         0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTRL - Test port control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SOFT_MODEM_TP 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_ICID_TP_OUT 14
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0  0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU     1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R  2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_A  3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T  4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SATA    5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RFM     6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS     16
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK     17
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON     18
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     20
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     21
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE    22
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM    23
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC     25
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVD0    27
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO     30
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA   31
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     33
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0   35
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0    45
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_FTM     51
+
+/***************************************************************************
+ *TEST_PORT_OUT_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_OUT_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TEST_PORT_IN_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EJTAG_INPUT_EN - EJTAG input bus enables
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           3
+
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 4
+
+/***************************************************************************
+ *EJTAG_OUTPUT_SEL - EJTAG output select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         3
+
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 2
+
+/***************************************************************************
+ *UART_ROUTER_SEL - UART Router select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK      0xf0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT     28
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK      0x0f000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT     24
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK      0x00f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK      0x000f0000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK      0x0000f000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK      0x00000f00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_04 4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_05 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_04 4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_05 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK      0x0000000f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_04 4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_05 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15
+
+/***************************************************************************
+ *VTRAP_CTRL - VTRAP Control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK                0xfffff000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT               12
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_threshold [11:11] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_threshold [10:10] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_threshold [09:09] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [08:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x000001f8
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 0x00000018
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_status_clear [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_status_clear [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_status_clear [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VTRAP_STATUS - VTRAP Status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK              0xfffffff8
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT             3
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_status [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_status [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_status [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SSP_CONFIG - Serial Slave Port configuration register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT        0x00000004
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT           0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT     0x00000001
+
+/***************************************************************************
+ *SERS_REV - SERS Revision Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16
+
+/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT     0x00000000
+
+/***************************************************************************
+ *SERS_CFG - SERS Configuration Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT                0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT           0x00000000
+
+/* union - case mapped_buffer_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0x00000000
+
+/* union - case cmd_fifo_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 0x0000001f
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 0x00000010
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT                 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x00404428
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0
+
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x00404448
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0
+
+
+/***************************************************************************
+ *RO_TEST_BLOCK_SEL - Block select for RO testmode
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xffffffe0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        5
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_pwenb [04:04] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DEFAULT  0x00000001
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_ENABLED  0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DISABLED 1
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [03:02] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MIN_LOAD 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MED_LOAD 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MAX_LOAD 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SVT_MIN_LOAD 3
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
+
+/***************************************************************************
+ *TEST_CONFIGURATION - Test configuration
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_timer.h b/include/linux/brcmstb/7360a0/bchp_timer.h
new file mode 100644
index 0000000..65a3318
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_timer.h
@@ -0,0 +1,327 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_timer.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:32p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_TIMER_H__
+#define BCHP_TIMER_H__
+
+/***************************************************************************
+ *TIMER - Watchdog & Programmable Timers
+ ***************************************************************************/
+#define BCHP_TIMER_TIMER_IS                      0x00406680 /* TIMER INTERRUPT STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE0                     0x00406684 /* TIMER CPU INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_TIMER0_CTRL                   0x00406688 /* TIMER0 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER1_CTRL                   0x0040668c /* TIMER1 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER2_CTRL                   0x00406690 /* TIMER2 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER3_CTRL                   0x00406694 /* TIMER3 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER0_STAT                   0x00406698 /* TIMER0 STATUS REGISTER */
+#define BCHP_TIMER_TIMER1_STAT                   0x0040669c /* TIMER1 STATUS REGISTER */
+#define BCHP_TIMER_TIMER2_STAT                   0x004066a0 /* TIMER2 STATUS REGISTER */
+#define BCHP_TIMER_TIMER3_STAT                   0x004066a4 /* TIMER3 STATUS REGISTER */
+#define BCHP_TIMER_WDTIMEOUT                     0x004066a8 /* WATCHDOG TIMEOUT REGISTER */
+#define BCHP_TIMER_WDCMD                         0x004066ac /* WATCHDOG COMMAND REGISTER */
+#define BCHP_TIMER_WDCHIPRST_CNT                 0x004066b0 /* WATCHDOG CHIP RESET COUNT REGISTER */
+#define BCHP_TIMER_TIMER_IE1                     0x004066b8 /* TIMER PCI INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_WDCTRL                        0x004066bc /* WATCHDOG CONTROL REGISTER */
+
+/***************************************************************************
+ *TIMER_IS - TIMER INTERRUPT STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IS :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IS_reserved0_MASK                         0xffffffe0
+#define BCHP_TIMER_TIMER_IS_reserved0_SHIFT                        5
+
+/* TIMER :: TIMER_IS :: WDINT [04:04] */
+#define BCHP_TIMER_TIMER_IS_WDINT_MASK                             0x00000010
+#define BCHP_TIMER_TIMER_IS_WDINT_SHIFT                            4
+#define BCHP_TIMER_TIMER_IS_WDINT_DEFAULT                          0x00000000
+
+/* TIMER :: TIMER_IS :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IS_TMR3TO_MASK                            0x00000008
+#define BCHP_TIMER_TIMER_IS_TMR3TO_SHIFT                           3
+#define BCHP_TIMER_TIMER_IS_TMR3TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IS_TMR2TO_MASK                            0x00000004
+#define BCHP_TIMER_TIMER_IS_TMR2TO_SHIFT                           2
+#define BCHP_TIMER_TIMER_IS_TMR2TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IS_TMR1TO_MASK                            0x00000002
+#define BCHP_TIMER_TIMER_IS_TMR1TO_SHIFT                           1
+#define BCHP_TIMER_TIMER_IS_TMR1TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IS_TMR0TO_MASK                            0x00000001
+#define BCHP_TIMER_TIMER_IS_TMR0TO_SHIFT                           0
+#define BCHP_TIMER_TIMER_IS_TMR0TO_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *TIMER_IE0 - TIMER CPU INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE0 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE0_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE0_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE0 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_DEFAULT                     0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *TIMER0_CTRL - TIMER0 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER0_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER0_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER0_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER0_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER0_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER0_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER0_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER0_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER1_CTRL - TIMER1 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER1_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER1_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER1_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER1_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER1_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER1_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER1_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER1_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER2_CTRL - TIMER2 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER2_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER2_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER2_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER2_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER2_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER2_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER2_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER2_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER3_CTRL - TIMER3 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER3_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER3_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER3_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER3_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER3_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER3_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER3_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER3_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER0_STAT - TIMER0 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER0_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER0_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER0_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER1_STAT - TIMER1 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER1_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER1_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER1_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER2_STAT - TIMER2 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER2_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER2_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER2_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER3_STAT - TIMER3 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER3_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER3_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER3_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *WDTIMEOUT - WATCHDOG TIMEOUT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDTIMEOUT :: WDTIMEOUT_VAL [31:00] */
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_MASK                    0xffffffff
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *WDCMD - WATCHDOG COMMAND REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCMD :: WDCMD [31:00] */
+#define BCHP_TIMER_WDCMD_WDCMD_MASK                                0xffffffff
+#define BCHP_TIMER_WDCMD_WDCMD_SHIFT                               0
+#define BCHP_TIMER_WDCMD_WDCMD_DEFAULT                             0x00000000
+
+/***************************************************************************
+ *WDCHIPRST_CNT - WATCHDOG CHIP RESET COUNT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCHIPRST_CNT :: reserved0 [31:26] */
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_MASK                    0xfc000000
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_SHIFT                   26
+
+/* TIMER :: WDCHIPRST_CNT :: WDCHIPRST_CNT [25:00] */
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_MASK                0x03ffffff
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_SHIFT               0
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_DEFAULT             0x02ffffff
+
+/***************************************************************************
+ *TIMER_IE1 - TIMER PCI INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE1 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE1_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE1_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE1 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_DEFAULT                     0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *WDCTRL - WATCHDOG CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCTRL :: reserved0 [31:03] */
+#define BCHP_TIMER_WDCTRL_reserved0_MASK                           0xfffffff8
+#define BCHP_TIMER_WDCTRL_reserved0_SHIFT                          3
+
+/* TIMER :: WDCTRL :: WD_COUNT_MODE [02:02] */
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_MASK                       0x00000004
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_SHIFT                      2
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_DEFAULT                    0x00000000
+
+/* TIMER :: WDCTRL :: WD_EVENT_MODE [01:00] */
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_MASK                       0x00000003
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_SHIFT                      0
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_DEFAULT                    0x00000000
+
+#endif /* #ifndef BCHP_TIMER_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_uarta.h b/include/linux/brcmstb/7360a0/bchp_uarta.h
new file mode 100644
index 0000000..3c5e61a
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_uarta.h
@@ -0,0 +1,394 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_uarta.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:33p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTA_H__
+#define BCHP_UARTA_H__
+
+/***************************************************************************
+ *UARTA - UART A
+ ***************************************************************************/
+#define BCHP_UARTA_RBR                           0x00406800 /* Receive Buffer Register */
+#define BCHP_UARTA_THR                           0x00406800 /* Transmit Holding Register */
+#define BCHP_UARTA_DLH                           0x00406804 /* Divisor Latch High */
+#define BCHP_UARTA_DLL                           0x00406800 /* Divisor Latch Low */
+#define BCHP_UARTA_IER                           0x00406804 /* Interrupt Enable Register */
+#define BCHP_UARTA_IIR                           0x00406808 /* Interrupt Identity Register */
+#define BCHP_UARTA_FCR                           0x00406808 /* FIFO Control Register */
+#define BCHP_UARTA_LCR                           0x0040680c /* Line Control Register */
+#define BCHP_UARTA_MCR                           0x00406810 /* Modem Control Register */
+#define BCHP_UARTA_LSR                           0x00406814 /* Line Status Register */
+#define BCHP_UARTA_MSR                           0x00406818 /* Modem Status Register */
+#define BCHP_UARTA_SCR                           0x0040681c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTA :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTA_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_RBR_reserved0_SHIFT                             8
+
+/* UARTA :: RBR :: RBR [07:00] */
+#define BCHP_UARTA_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTA_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTA_RBR_RBR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTA :: THR :: reserved0 [31:08] */
+#define BCHP_UARTA_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_THR_reserved0_SHIFT                             8
+
+/* UARTA :: THR :: THR [07:00] */
+#define BCHP_UARTA_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTA_THR_THR_SHIFT                                   0
+#define BCHP_UARTA_THR_THR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTA :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTA_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLH_reserved0_SHIFT                             8
+
+/* UARTA :: DLH :: DLH [07:00] */
+#define BCHP_UARTA_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTA_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTA_DLH_DLH_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTA :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTA_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLL_reserved0_SHIFT                             8
+
+/* UARTA :: DLL :: DLL [07:00] */
+#define BCHP_UARTA_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTA_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTA_DLL_DLL_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTA :: IER :: reserved0 [31:08] */
+#define BCHP_UARTA_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IER_reserved0_SHIFT                             8
+
+/* UARTA :: IER :: PTIME [07:07] */
+#define BCHP_UARTA_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTA_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTA_IER_PTIME_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: reserved1 [06:04] */
+#define BCHP_UARTA_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTA_IER_reserved1_SHIFT                             4
+
+/* UARTA :: IER :: EDSSI [03:03] */
+#define BCHP_UARTA_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTA_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTA_IER_EDSSI_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: ELSI [02:02] */
+#define BCHP_UARTA_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTA_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTA_IER_ELSI_DEFAULT                                0x00000000
+
+/* UARTA :: IER :: ETBEI [01:01] */
+#define BCHP_UARTA_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTA_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTA_IER_ETBEI_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: ERBFI [00:00] */
+#define BCHP_UARTA_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTA_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTA_IER_ERBFI_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTA :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTA_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IIR_reserved0_SHIFT                             8
+
+/* UARTA :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTA_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTA_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTA_IIR_FIFOSE_DEFAULT                              0x00000000
+
+/* UARTA :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTA_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTA_IIR_reserved1_SHIFT                             4
+
+/* UARTA :: IIR :: IID [03:00] */
+#define BCHP_UARTA_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTA_IIR_IID_SHIFT                                   0
+#define BCHP_UARTA_IIR_IID_DEFAULT                                 0x00000001
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTA :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTA_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_FCR_reserved0_SHIFT                             8
+
+/* UARTA :: FCR :: RT [07:06] */
+#define BCHP_UARTA_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTA_FCR_RT_SHIFT                                    6
+#define BCHP_UARTA_FCR_RT_DEFAULT                                  0x00000000
+
+/* UARTA :: FCR :: TET [05:04] */
+#define BCHP_UARTA_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTA_FCR_TET_SHIFT                                   4
+#define BCHP_UARTA_FCR_TET_DEFAULT                                 0x00000000
+
+/* UARTA :: FCR :: DMAM [03:03] */
+#define BCHP_UARTA_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTA_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTA_FCR_DMAM_DEFAULT                                0x00000000
+
+/* UARTA :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTA_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTA_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTA_FCR_XFIFOR_DEFAULT                              0x00000000
+
+/* UARTA :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTA_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTA_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTA_FCR_RFIFOR_DEFAULT                              0x00000000
+
+/* UARTA :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTA_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTA_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTA_FCR_FIFOE_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTA :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTA_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LCR_reserved0_SHIFT                             8
+
+/* UARTA :: LCR :: DLAB [07:07] */
+#define BCHP_UARTA_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTA_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTA_LCR_DLAB_DEFAULT                                0x00000000
+
+/* UARTA :: LCR :: BC [06:06] */
+#define BCHP_UARTA_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTA_LCR_BC_SHIFT                                    6
+#define BCHP_UARTA_LCR_BC_DEFAULT                                  0x00000000
+
+/* UARTA :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTA_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTA_LCR_reserved1_SHIFT                             5
+
+/* UARTA :: LCR :: EPS [04:04] */
+#define BCHP_UARTA_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTA_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTA_LCR_EPS_DEFAULT                                 0x00000000
+
+/* UARTA :: LCR :: PEN [03:03] */
+#define BCHP_UARTA_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTA_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTA_LCR_PEN_DEFAULT                                 0x00000000
+
+/* UARTA :: LCR :: STOP [02:02] */
+#define BCHP_UARTA_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTA_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTA_LCR_STOP_DEFAULT                                0x00000000
+
+/* UARTA :: LCR :: DLS [01:00] */
+#define BCHP_UARTA_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTA_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTA_LCR_DLS_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTA :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTA_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTA_MCR_reserved0_SHIFT                             7
+
+/* UARTA :: MCR :: SIRE [06:06] */
+#define BCHP_UARTA_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTA_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTA_MCR_SIRE_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: AFCE [05:05] */
+#define BCHP_UARTA_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTA_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTA_MCR_AFCE_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: LB [04:04] */
+#define BCHP_UARTA_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTA_MCR_LB_SHIFT                                    4
+#define BCHP_UARTA_MCR_LB_DEFAULT                                  0x00000000
+
+/* UARTA :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTA_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTA_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTA_MCR_OUT2_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTA_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTA_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTA_MCR_OUT1_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: RTS [01:01] */
+#define BCHP_UARTA_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTA_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTA_MCR_RTS_DEFAULT                                 0x00000000
+
+/* UARTA :: MCR :: DTR [00:00] */
+#define BCHP_UARTA_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTA_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTA_MCR_DTR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTA :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTA_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LSR_reserved0_SHIFT                             8
+
+/* UARTA :: LSR :: RFE [07:07] */
+#define BCHP_UARTA_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTA_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTA_LSR_RFE_DEFAULT                                 0x00000000
+
+/* UARTA :: LSR :: TEMT [06:06] */
+#define BCHP_UARTA_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTA_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTA_LSR_TEMT_DEFAULT                                0x00000001
+
+/* UARTA :: LSR :: THRE [05:05] */
+#define BCHP_UARTA_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTA_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTA_LSR_THRE_DEFAULT                                0x00000001
+
+/* UARTA :: LSR :: BI [04:04] */
+#define BCHP_UARTA_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTA_LSR_BI_SHIFT                                    4
+#define BCHP_UARTA_LSR_BI_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: FE [03:03] */
+#define BCHP_UARTA_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTA_LSR_FE_SHIFT                                    3
+#define BCHP_UARTA_LSR_FE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: PE [02:02] */
+#define BCHP_UARTA_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTA_LSR_PE_SHIFT                                    2
+#define BCHP_UARTA_LSR_PE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: OE [01:01] */
+#define BCHP_UARTA_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTA_LSR_OE_SHIFT                                    1
+#define BCHP_UARTA_LSR_OE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: DR [00:00] */
+#define BCHP_UARTA_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTA_LSR_DR_SHIFT                                    0
+#define BCHP_UARTA_LSR_DR_DEFAULT                                  0x00000000
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTA :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTA_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_MSR_reserved0_SHIFT                             8
+
+/* UARTA :: MSR :: DCD [07:07] */
+#define BCHP_UARTA_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTA_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTA_MSR_DCD_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: RI [06:06] */
+#define BCHP_UARTA_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTA_MSR_RI_SHIFT                                    6
+#define BCHP_UARTA_MSR_RI_DEFAULT                                  0x00000000
+
+/* UARTA :: MSR :: DSR [05:05] */
+#define BCHP_UARTA_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTA_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTA_MSR_DSR_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: CTS [04:04] */
+#define BCHP_UARTA_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTA_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTA_MSR_CTS_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: DDCD [03:03] */
+#define BCHP_UARTA_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTA_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTA_MSR_DDCD_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: TERI [02:02] */
+#define BCHP_UARTA_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTA_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTA_MSR_TERI_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: DDSR [01:01] */
+#define BCHP_UARTA_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTA_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTA_MSR_DDSR_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: DCTS [00:00] */
+#define BCHP_UARTA_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTA_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTA_MSR_DCTS_DEFAULT                                0x00000000
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTA :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTA_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_SCR_reserved0_SHIFT                             8
+
+/* UARTA :: SCR :: SCR [07:00] */
+#define BCHP_UARTA_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTA_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTA_SCR_SCR_DEFAULT                                 0x00000000
+
+#endif /* #ifndef BCHP_UARTA_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_uartb.h b/include/linux/brcmstb/7360a0/bchp_uartb.h
new file mode 100644
index 0000000..bfaf8d6
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_uartb.h
@@ -0,0 +1,63 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug 16 11:03:36 2010
+ *                 MD5 Checksum         442d8de773a92e76786307c9f37b5c82
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_uartb.h $
+ * 
+ * Hydra_Software_Devel/2   8/16/10 12:22p pntruong
+ * SW7358-2: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTB_H__
+#define BCHP_UARTB_H__
+
+/***************************************************************************
+ *UARTB - UART B
+ ***************************************************************************/
+#define BCHP_UARTB_RBR                           0x00406840 /* Receive Buffer Register */
+#define BCHP_UARTB_THR                           0x00406840 /* Transmit Holding Register */
+#define BCHP_UARTB_DLH                           0x00406844 /* Divisor Latch High */
+#define BCHP_UARTB_DLL                           0x00406840 /* Divisor Latch Low */
+#define BCHP_UARTB_IER                           0x00406844 /* Interrupt Enable Register */
+#define BCHP_UARTB_IIR                           0x00406848 /* Interrupt Identity Register */
+#define BCHP_UARTB_FCR                           0x00406848 /* FIFO Control Register */
+#define BCHP_UARTB_LCR                           0x0040684c /* Line Control Register */
+#define BCHP_UARTB_MCR                           0x00406850 /* Modem Control Register */
+#define BCHP_UARTB_LSR                           0x00406854 /* Line Status Register */
+#define BCHP_UARTB_MSR                           0x00406858 /* Modem Status Register */
+#define BCHP_UARTB_SCR                           0x0040685c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTB_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_uartc.h b/include/linux/brcmstb/7360a0/bchp_uartc.h
new file mode 100644
index 0000000..ea77c9f
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_uartc.h
@@ -0,0 +1,63 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug 16 10:54:53 2010
+ *                 MD5 Checksum         442d8de773a92e76786307c9f37b5c82
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_uartc.h $
+ * 
+ * Hydra_Software_Devel/2   8/16/10 12:22p pntruong
+ * SW7358-2: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTC_H__
+#define BCHP_UARTC_H__
+
+/***************************************************************************
+ *UARTC - UART C
+ ***************************************************************************/
+#define BCHP_UARTC_RBR                           0x00406880 /* Receive Buffer Register */
+#define BCHP_UARTC_THR                           0x00406880 /* Transmit Holding Register */
+#define BCHP_UARTC_DLH                           0x00406884 /* Divisor Latch High */
+#define BCHP_UARTC_DLL                           0x00406880 /* Divisor Latch Low */
+#define BCHP_UARTC_IER                           0x00406884 /* Interrupt Enable Register */
+#define BCHP_UARTC_IIR                           0x00406888 /* Interrupt Identity Register */
+#define BCHP_UARTC_FCR                           0x00406888 /* FIFO Control Register */
+#define BCHP_UARTC_LCR                           0x0040688c /* Line Control Register */
+#define BCHP_UARTC_MCR                           0x00406890 /* Modem Control Register */
+#define BCHP_UARTC_LSR                           0x00406894 /* Line Status Register */
+#define BCHP_UARTC_MSR                           0x00406898 /* Modem Status Register */
+#define BCHP_UARTC_SCR                           0x0040689c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_usb_ctrl.h b/include/linux/brcmstb/7360a0/bchp_usb_ctrl.h
new file mode 100644
index 0000000..e116fa2
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_usb_ctrl.h
@@ -0,0 +1,655 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_usb_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:33p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB_CTRL_H__
+#define BCHP_USB_CTRL_H__
+
+/***************************************************************************
+ *USB_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB_CTRL_SETUP                      0x00480200 /* Setup Register */
+#define BCHP_USB_CTRL_PLL_CTL                    0x00480204 /* PLL Control Register */
+#define BCHP_USB_CTRL_FLADJ_VALUE                0x00480208 /* Frame Adjust Value */
+#define BCHP_USB_CTRL_EBRIDGE                    0x0048020c /* Control Register for EHCI Bridge */
+#define BCHP_USB_CTRL_OBRIDGE                    0x00480210 /* Control Register for OHCI Bridge */
+#define BCHP_USB_CTRL_MDIO                       0x00480214 /* MDIO Interface Programming Register */
+#define BCHP_USB_CTRL_MDIO2                      0x00480218 /* MDIO Interface Read Register */
+#define BCHP_USB_CTRL_TEST_PORT_CTL              0x0048021c /* Test Port Control Register */
+#define BCHP_USB_CTRL_USB_SIMCTL                 0x00480220 /* Simulation Register */
+#define BCHP_USB_CTRL_USB_TESTCTL                0x00480224 /* Throutput Test Control */
+#define BCHP_USB_CTRL_USB_TESTMON                0x00480228 /* Throughput Test Monitor */
+#define BCHP_USB_CTRL_UTMI_CTL_1                 0x0048022c /* UTMI Control Register */
+#define BCHP_USB_CTRL_UTMI_CTL_2                 0x00480230 /* UTMI Control 2 Register */
+#define BCHP_USB_CTRL_SPARE1                     0x00480234 /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE2                     0x00480238 /* Spare2 Register for future use */
+
+/***************************************************************************
+ *SETUP - Setup Register
+ ***************************************************************************/
+/* USB_CTRL :: SETUP :: OC_DISABLE [31:28] */
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK                        0xf0000000
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT                       28
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: SRAM_CS_DIS [27:26] */
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_MASK                       0x0c000000
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_SHIFT                      26
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: SETUP_SPARE [25:13] */
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK                       0x03ffe000
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT                      13
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: async_expire_dis [12:12] */
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK                  0x00001000
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT                 12
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT               0x00000000
+
+/* USB_CTRL :: SETUP :: discon_intr_en [11:11] */
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_MASK                    0x00000800
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_SHIFT                   11
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: con_intr_en [10:10] */
+#define BCHP_USB_CTRL_SETUP_con_intr_en_MASK                       0x00000400
+#define BCHP_USB_CTRL_SETUP_con_intr_en_SHIFT                      10
+#define BCHP_USB_CTRL_SETUP_con_intr_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: SOFT_SHUTDOWN [09:09] */
+#define BCHP_USB_CTRL_SETUP_SOFT_SHUTDOWN_MASK                     0x00000200
+#define BCHP_USB_CTRL_SETUP_SOFT_SHUTDOWN_SHIFT                    9
+#define BCHP_USB_CTRL_SETUP_SOFT_SHUTDOWN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK                    0x00000100
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT                   8
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK                       0x00000080
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT                      7
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: soft_reset [06:06] */
+#define BCHP_USB_CTRL_SETUP_soft_reset_MASK                        0x00000040
+#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT                       6
+#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: IPP [05:05] */
+#define BCHP_USB_CTRL_SETUP_IPP_MASK                               0x00000020
+#define BCHP_USB_CTRL_SETUP_IPP_SHIFT                              5
+#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: IOC [04:04] */
+#define BCHP_USB_CTRL_SETUP_IOC_MASK                               0x00000010
+#define BCHP_USB_CTRL_SETUP_IOC_SHIFT                              4
+#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: WABO [03:03] */
+#define BCHP_USB_CTRL_SETUP_WABO_MASK                              0x00000008
+#define BCHP_USB_CTRL_SETUP_WABO_SHIFT                             3
+#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNBO [02:02] */
+#define BCHP_USB_CTRL_SETUP_FNBO_MASK                              0x00000004
+#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT                             2
+#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNHW [01:01] */
+#define BCHP_USB_CTRL_SETUP_FNHW_MASK                              0x00000002
+#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT                             1
+#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: BABO [00:00] */
+#define BCHP_USB_CTRL_SETUP_BABO_MASK                              0x00000001
+#define BCHP_USB_CTRL_SETUP_BABO_SHIFT                             0
+#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *PLL_CTL - PLL Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK                  0x80000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT                 31
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT               0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK                      0x40000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT                     30
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                   0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK                      0x20000000
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                     29
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                   0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                     0x10000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                    28
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                  0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                  0x08000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                 27
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT               0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK                          0x07000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT                         24
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT                       0x00000003
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                   0x00800000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                  23
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK                          0x00700000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT                         20
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT                       0x00000003
+
+/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK                          0x000f0000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT                         16
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT                       0x0000000a
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE2 [15:15] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_MASK                   0x00008000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_SHIFT                  15
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_pdiv [14:12] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK                        0x00007000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT                       12
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                     0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                   0x00000c00
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                  10
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK                        0x000003ff
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT                       0
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                     0x00000028
+
+/***************************************************************************
+ *FLADJ_VALUE - Frame Adjust Value
+ ***************************************************************************/
+/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                   0xffffffff
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                  0
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT                0x000c0020
+
+/***************************************************************************
+ *EBRIDGE - Control Register for EHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_rdgwordcnt_sel [28:28] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_rdgwordcnt_sel_MASK              0x10000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_rdgwordcnt_sel_SHIFT             28
+#define BCHP_USB_CTRL_EBRIDGE_ebr_rdgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *OBRIDGE - Control Register for OHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_rdgwordcnt_sel [28:28] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_rdgwordcnt_sel_MASK              0x10000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_rdgwordcnt_sel_SHIFT             28
+#define BCHP_USB_CTRL_OBRIDGE_obr_rdgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *MDIO - MDIO Interface Programming Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO :: MDIO_SPARE [31:26] */
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_MASK                         0xfc000000
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_SHIFT                        26
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_DEFAULT                      0x00000000
+
+/* USB_CTRL :: MDIO :: WR_START [25:25] */
+#define BCHP_USB_CTRL_MDIO_WR_START_MASK                           0x02000000
+#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT                          25
+#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: RD_START [24:24] */
+#define BCHP_USB_CTRL_MDIO_RD_START_MASK                           0x01000000
+#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT                          24
+#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK                          0x00ff0000
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT                         16
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT                       0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK                          0x0000ffff
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT                         0
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *MDIO2 - MDIO Interface Read Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO2 :: SYNOPSIS_CORE_ID [31:16] */
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_MASK                  0xffff0000
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_SHIFT                 16
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_DEFAULT               0x0000270a
+
+/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK                      0x0000ffff
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                     0
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTL - Test Port Control Register
+ ***************************************************************************/
+/* USB_CTRL :: TEST_PORT_CTL :: TP_EN [31:31] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_MASK                     0x80000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_SHIFT                    31
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [30:24] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK               0x7f000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT              24
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [23:23] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK                0x00800000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT               23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt2_oe [22:22] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_MASK                0x00400000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_SHIFT               22
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron1_tstsel [21:21] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_MASK             0x00200000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_SHIFT            21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron2_tstsel [20:20] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_MASK             0x00100000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_SHIFT            20
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: test_clksel [19:18] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_MASK               0x000c0000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_SHIFT              18
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_tstsel [17:16] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_MASK             0x00030000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_SHIFT            16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: UTMI_TEST_SEL [15:08] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_MASK             0x0000ff00
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_SHIFT            8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                 0x000000ff
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT                0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *USB_SIMCTL - Simulation Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK                  0x80000000
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                 31
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK                0x40000000
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT               30
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE1 [29:28] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_MASK                0x30000000
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_SHIFT               28
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK                    0x08000000
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT                   27
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK        0x04000000
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT       26
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT     0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:01] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                 0x03fffffe
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT                1
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: FS_DLY_EN [00:00] */
+#define BCHP_USB_CTRL_USB_SIMCTL_FS_DLY_EN_MASK                    0x00000001
+#define BCHP_USB_CTRL_USB_SIMCTL_FS_DLY_EN_SHIFT                   0
+#define BCHP_USB_CTRL_USB_SIMCTL_FS_DLY_EN_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *USB_TESTCTL - Throutput Test Control
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:22] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK              0xffc00000
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT             22
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: CTRLLER_SEL [21:21] */
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_MASK                 0x00200000
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_SHIFT                21
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK                     0x00100000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                    20
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK                   0x00080000
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                  19
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT                0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK                    0x00070000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                   16
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK              0x0000fc00
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT             10
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK              0x000003ff
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT             0
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT           0x00000000
+
+/***************************************************************************
+ *USB_TESTMON - Throughput Test Monitor
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [31:00] */
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK                0xffffffff
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT               0
+
+/***************************************************************************
+ *UTMI_CTL_1 - UTMI Control Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE3 [31:31] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_MASK              0x80000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_SHIFT             31
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK             0x70000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT            28
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT          0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK_P1 [27:27] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_MASK                0x08000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_SHIFT               27
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_LPBACK_P1 [26:26] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_P1_MASK                0x04000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_P1_SHIFT               26
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE2 [25:25] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE2_MASK              0x02000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE2_SHIFT             25
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE2_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY_P1 [24:24] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_MASK                0x01000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_SHIFT               24
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK                0x00800000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT               23
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK                0x00400000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT               22
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK                0x00200000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT               21
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK                0x00100000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT               20
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                  0x000c0000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                 18
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT               0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT       0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK           0x00010000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT          16
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT        0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PLL_SUSPEND_EN [15:15] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PLL_SUSPEND_EN_MASK               0x00008000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PLL_SUSPEND_EN_SHIFT              15
+#define BCHP_USB_CTRL_UTMI_CTL_1_PLL_SUSPEND_EN_DEFAULT            0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK                0x00007000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT               12
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK [11:11] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_MASK                   0x00000800
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_SHIFT                  11
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_LPBACK [10:10] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_MASK                   0x00000400
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_SHIFT                  10
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE1 [09:09] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_MASK              0x00000200
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_SHIFT             9
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY [08:08] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_MASK                   0x00000100
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_SHIFT                  8
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                   0x00000080
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                  7
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                   0x00000040
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                  6
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                   0x00000020
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                  5
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                   0x00000010
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                  4
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK                     0x0000000c
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                    2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                  0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT          0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK              0x00000001
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT             0
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT           0x00000000
+
+/***************************************************************************
+ *UTMI_CTL_2 - UTMI Control 2 Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK               0xffffffff
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT              0
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SPARE1 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE1 :: SPARE1_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *SPARE2 - Spare2 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE2 :: SPARE2_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_DEFAULT                   0x00000000
+
+#endif /* #ifndef BCHP_USB_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_wktmr.h b/include/linux/brcmstb/7360a0/bchp_wktmr.h
new file mode 100644
index 0000000..e0d95f7
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_wktmr.h
@@ -0,0 +1,108 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_wktmr.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:38p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_WKTMR_H__
+#define BCHP_WKTMR_H__
+
+/***************************************************************************
+ *WKTMR - Wakeup timer
+ ***************************************************************************/
+#define BCHP_WKTMR_EVENT                         0x00408e80 /* Wakeup Timer Register */
+#define BCHP_WKTMR_COUNTER                       0x00408e84 /* Wakeup Counter */
+#define BCHP_WKTMR_ALARM                         0x00408e88 /* Wakeup Timer Alarm */
+#define BCHP_WKTMR_PRESCALER                     0x00408e8c /* Wakeup Timer Prescaler */
+#define BCHP_WKTMR_PRESCALER_VAL                 0x00408e90 /* Wakeup Timer Prescaler Value */
+
+/***************************************************************************
+ *EVENT - Wakeup Timer Register
+ ***************************************************************************/
+/* WKTMR :: EVENT :: reserved0 [31:01] */
+#define BCHP_WKTMR_EVENT_reserved0_MASK                            0xfffffffe
+#define BCHP_WKTMR_EVENT_reserved0_SHIFT                           1
+
+/* WKTMR :: EVENT :: wktmr_alarm_event [00:00] */
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_MASK                    0x00000001
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_SHIFT                   0
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *COUNTER - Wakeup Counter
+ ***************************************************************************/
+/* WKTMR :: COUNTER :: wktmr_counter [31:00] */
+#define BCHP_WKTMR_COUNTER_wktmr_counter_MASK                      0xffffffff
+#define BCHP_WKTMR_COUNTER_wktmr_counter_SHIFT                     0
+#define BCHP_WKTMR_COUNTER_wktmr_counter_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *ALARM - Wakeup Timer Alarm
+ ***************************************************************************/
+/* WKTMR :: ALARM :: wktmr_alarm [31:00] */
+#define BCHP_WKTMR_ALARM_wktmr_alarm_MASK                          0xffffffff
+#define BCHP_WKTMR_ALARM_wktmr_alarm_SHIFT                         0
+#define BCHP_WKTMR_ALARM_wktmr_alarm_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *PRESCALER - Wakeup Timer Prescaler
+ ***************************************************************************/
+/* WKTMR :: PRESCALER :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_reserved0_MASK                        0xfe000000
+#define BCHP_WKTMR_PRESCALER_reserved0_SHIFT                       25
+
+/* WKTMR :: PRESCALER :: wktmr_prescaler [24:00] */
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_MASK                  0x01ffffff
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_SHIFT                 0
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_DEFAULT               0x019bfcc0
+
+/***************************************************************************
+ *PRESCALER_VAL - Wakeup Timer Prescaler Value
+ ***************************************************************************/
+/* WKTMR :: PRESCALER_VAL :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_MASK                    0xfe000000
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_SHIFT                   25
+
+/* WKTMR :: PRESCALER_VAL :: wktmr_prescaler_val [24:00] */
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_MASK          0x01ffffff
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_SHIFT         0
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_DEFAULT       0x00000000
+
+#endif /* #ifndef BCHP_WKTMR_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/brcmirq.h b/include/linux/brcmstb/7360a0/brcmirq.h
new file mode 100644
index 0000000..b899a30
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/brcmirq.h
@@ -0,0 +1,39 @@
+/*
+ * 7360a0 IRQ header file autogenerated by update_bchp.pl
+ * DO NOT EDIT THIS FILE BY HAND.
+ *
+ * Copyright (C) 2012 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BRCMIRQ_H_
+#define _BRCMIRQ_H_
+
+#define BRCM_IRQ_EHCI0_0	66
+#define BRCM_IRQ_GENET_0_A	25
+#define BRCM_IRQ_GENET_0_B	26
+#define BRCM_IRQ_HIF		31
+#define BRCM_IRQ_HIF_SPI	32
+#define BRCM_IRQ_OHCI0_0	67
+#define BRCM_IRQ_SATA		87
+#define BRCM_IRQ_SDIO0		83
+#define BRCM_IRQ_STANDBY	51
+#define BRCM_IRQ_UARTA		62
+#define BRCM_IRQ_UARTB		63
+#define BRCM_IRQ_UARTC		64
+#define BRCM_IRQLIST_EHCI	{ 66 }
+#define BRCM_IRQLIST_OHCI	{ 67 }
+
+#endif /* _BRCMIRQ_H_ */
diff --git a/include/linux/brcmstb/7362a0/bchp_aon_ctrl.h b/include/linux/brcmstb/7362a0/bchp_aon_ctrl.h
new file mode 100644
index 0000000..9bf2b28
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_aon_ctrl.h
@@ -0,0 +1,1578 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_aon_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:24a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_CTRL_H__
+#define BCHP_AON_CTRL_H__
+
+/***************************************************************************
+ *AON_CTRL - AON Control Registers
+ ***************************************************************************/
+#define BCHP_AON_CTRL_RESET_CTRL                 0x00408000 /* Reset Control register for AON */
+#define BCHP_AON_CTRL_PM_CTRL                    0x00408004 /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_STATUS                  0x00408008 /* Status register for Power Controller */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS        0x0040800c /* Power Management IRQ input status */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT         0x00408010 /* Power Management Wait counter in place of Wait for MIPS IRQ */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER        0x00408014 /* Deep Standby Assertion Timer */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER         0x00408018 /* Deep Standby Wakeup Timer */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE    0x0040801c /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_LED_CTRL                0x00408020 /* LED set control register */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES     0x00408024 /* LED set control register */
+#define BCHP_AON_CTRL_HLCD_CTRL                  0x00408030 /* HW LED Clock Driver Control */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER    0x00408034 /* Second Fraction Counter Initial value */
+#define BCHP_AON_CTRL_TIME_COUNTER               0x00408038 /* Hour/Minute Counter Initial value */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0           0x0040803c /* Digit Code for digit 0, 1, 2, 3 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1           0x00408040 /* Digit Code for digit 4, 5, 6, 7 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2           0x00408044 /* Digit Code for digit 8, 9 */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET      0x00408048 /* Hour MSD/LSD and minute MSD/LSD address offset */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL            0x0040804c /* LED status control */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0             0x00408050 /* General control register 0 */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0           0x00408054 /* General status register 0 */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0     0x00408058 /* General control register without scan 0 */
+#define BCHP_AON_CTRL_SPARE_CTRL_0               0x00408060 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_SPARE_CTRL_1               0x00408064 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH          0x00408068 /* Scratch register */
+#define BCHP_AON_CTRL_RESET_HISTORY              0x0040806c /* Reset History Register For AON */
+#define BCHP_AON_CTRL_NMI_CTRL                   0x00408070 /* Control register for NMI */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL           0x00408074 /* Ana xtal low cur 40g m7fc gisb control */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL         0x00408078 /* Test_mode control register */
+#define BCHP_AON_CTRL_SUB_TEST_MODE              0x0040807c /* Register source for sub_test_mode */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE          0x00408080 /* Final latched testmode value */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE      0x00408084 /* Final latched sub-testmode value */
+#define BCHP_AON_CTRL_PM_INITIATE                0x00408088 /* Power down initiate */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS             0x0040808c /* Power up restore */
+
+/***************************************************************************
+ *RESET_CTRL - Reset Control register for AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_CTRL :: reserved0 [31:04] */
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_MASK                    0xfffffff0
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_SHIFT                   4
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [03:03] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000008
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 3
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable [02:02] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_MASK     0x00000004
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT    2
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_polarity [01:01] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK   0x00000002
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT  1
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_MASK          0x00000001
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_SHIFT         0
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PM_CTRL - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_CTRL :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_MASK                       0xffffff00
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_SHIFT                      8
+
+/* AON_CTRL :: PM_CTRL :: min_s3_width_timer_bypass [07:07] */
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_MASK       0x00000080
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_SHIFT      7
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_DEFAULT    0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_fast_power_down [06:06] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_MASK              0x00000040
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_SHIFT             6
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_DEFAULT           0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_warm_boot [05:05] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_MASK                    0x00000020
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_SHIFT                   5
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_DEFAULT                 0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_deep_standby [04:04] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_MASK                 0x00000010
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_SHIFT                4
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_DEFAULT              0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_clk_divider_reset_en [03:03] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK         0x00000008
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_SHIFT        3
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_DEFAULT      0x00000001
+
+/* AON_CTRL :: PM_CTRL :: pm_use_mips_ready_ctrl [02:02] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_MASK          0x00000004
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_SHIFT         2
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_DEFAULT       0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK             0x00000002
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT            1
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_DEFAULT          0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_MASK                  0x00000001
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT                 0
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PM_STATUS - Status register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_STATUS :: pm_wait_count_upper_bits [31:26] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_MASK      0xfc000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_SHIFT     26
+
+/* AON_CTRL :: PM_STATUS :: pm_wait_counter_active [25:25] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_MASK        0x02000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_SHIFT       25
+
+/* AON_CTRL :: PM_STATUS :: pm_s3_wakeup_reset_ [24:24] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__MASK           0x01000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__SHIFT          24
+
+/* AON_CTRL :: PM_STATUS :: pm_boundary_scan_request [23:23] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_MASK      0x00800000
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_SHIFT     23
+
+/* AON_CTRL :: PM_STATUS :: pm_fast_pd_precharge_valid [22:22] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_MASK    0x00400000
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_SHIFT   22
+
+/* AON_CTRL :: PM_STATUS :: pm_led_out [21:21] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_MASK                    0x00200000
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_SHIFT                   21
+
+/* AON_CTRL :: PM_STATUS :: pm_standby_b [20:20] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_MASK                  0x00100000
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_SHIFT                 20
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs_ng [19:19] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_MASK           0x00080000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_SHIFT          19
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs [18:18] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_MASK              0x00040000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_SHIFT             18
+
+/* AON_CTRL :: PM_STATUS :: pm_rst_clock_div [17:17] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_MASK              0x00020000
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_SHIFT             17
+
+/* AON_CTRL :: PM_STATUS :: pm_pwrdn_pll_req [16:16] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_MASK              0x00010000
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_SHIFT             16
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_xtal_clocks [15:15] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_MASK            0x00008000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_SHIFT           15
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_all_clocks [14:14] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_MASK             0x00004000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_SHIFT            14
+
+/* AON_CTRL :: PM_STATUS :: pm_dphy_standby [13:13] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_MASK               0x00002000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_SHIFT              13
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_cpu_clock [12:12] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_MASK              0x00001000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_SHIFT             12
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_avd_rptd_clock [11:11] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_MASK         0x00000800
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_SHIFT        11
+
+/* AON_CTRL :: PM_STATUS :: pm_power_ctrl_disable [10:10] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_MASK         0x00000400
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_SHIFT        10
+
+/* AON_CTRL :: PM_STATUS :: pm_pll_lock [09:09] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_MASK                   0x00000200
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_SHIFT                  9
+
+/* AON_CTRL :: PM_STATUS :: pm_dram_ready_for_pwrdn [08:08] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_MASK       0x00000100
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_SHIFT      8
+
+/* AON_CTRL :: PM_STATUS :: pm_bsp_ready_for_pwrdn [07:07] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK        0x00000080
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_SHIFT       7
+
+/* AON_CTRL :: PM_STATUS :: pm_mips_ready_for_pwrdn [06:06] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_MASK       0x00000040
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_SHIFT      6
+
+/* AON_CTRL :: PM_STATUS :: pm_sec_avd_rptd_clk_disable [05:05] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_MASK   0x00000020
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_SHIFT  5
+
+/* AON_CTRL :: PM_STATUS :: pm_state [04:00] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_MASK                      0x0000001f
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_SHIFT                     0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_ACTIVE                 0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_PWRDN_RDY              1
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_AVD_RPTD       2
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_CPU            3
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_STANDBY  4
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY                5
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY_WITH_PLLS_ON   6
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_RESET_216_108_CLKS     7
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_ACTIVE   8
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_FAST_PWRDN             9
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S1  10
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_COLD_ENTRY_S2 11
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_WARM_ENTRY_S2 12
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S3  13
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY           14
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S1   15
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S2   16
+
+/***************************************************************************
+ *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
+ ***************************************************************************/
+/* AON_CTRL :: PM_IRQ_INPUT_STATUS :: pm_irq_input_status [31:00] */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_MASK 0xffffffff
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_SHIFT 0
+
+/***************************************************************************
+ *PM_MIPS_WAIT_COUNT - Power Management Wait counter in place of Wait for MIPS IRQ
+ ***************************************************************************/
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_MASK            0xffff0000
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_SHIFT           16
+
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: counter_start_value [15:00] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_MASK  0x0000ffff
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_DEFAULT 0x00000010
+
+/***************************************************************************
+ *PM_S3_STANDBY_TIMER - Deep Standby Assertion Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_MASK           0xf8000000
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_SHIFT          27
+
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_MASK 0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_DEFAULT 0x00083d60
+
+/***************************************************************************
+ *PM_S3_WAKEUP_TIMER - Deep Standby Wakeup Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_MASK            0xf8000000
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_SHIFT           27
+
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_MASK  0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_DEFAULT 0x00083d60
+
+/***************************************************************************
+ *PM_FAST_PWRDN_PRECHARGE - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: reserved0 [31:24] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_MASK       0xff000000
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_SHIFT      24
+
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: pm_fast_power_down_precharge [23:00] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_MASK 0x00ffffff
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_SHIFT 0
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PM_LED_CTRL - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_CTRL :: reserved0 [31:03] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_MASK                   0xfffffff8
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_SHIFT                  3
+
+/* AON_CTRL :: PM_LED_CTRL :: led_status [02:02] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_MASK                  0x00000004
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_SHIFT                 2
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_on [01:01] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_MASK                 0x00000002
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_SHIFT                1
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_off [00:00] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_MASK                0x00000001
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_SHIFT               0
+
+/***************************************************************************
+ *PM_LED_AUTO_ON_ENABLES - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_AUTO_ON_ENABLES :: led_status [31:00] */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_MASK       0xffffffff
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_SHIFT      0
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_DEFAULT    0x00000000
+
+/***************************************************************************
+ *HLCD_CTRL - HW LED Clock Driver Control
+ ***************************************************************************/
+/* AON_CTRL :: HLCD_CTRL :: reserved0 [31:02] */
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_MASK                     0xfffffffc
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_SHIFT                    2
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable_status [01:01] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_MASK            0x00000002
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_SHIFT           1
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable [00:00] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_MASK                   0x00000001
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_SHIFT                  0
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_DEFAULT                0x00000000
+
+/***************************************************************************
+ *SECOND_FRACTION_COUNTER - Second Fraction Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: reserved0 [31:25] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_MASK       0xfe000000
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_SHIFT      25
+
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: second_fraction_counter_init [24:00] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_MASK 0x01ffffff
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_SHIFT 0
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TIME_COUNTER - Hour/Minute Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: TIME_COUNTER :: reserved0 [31:20] */
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_MASK                  0xfff00000
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_SHIFT                 20
+
+/* AON_CTRL :: TIME_COUNTER :: hour_display_mode [19:19] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_MASK          0x00080000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_SHIFT         19
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: mode_12h_24h_init [18:18] */
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_MASK          0x00040000
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_SHIFT         18
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: am_pm_counter_init [17:17] */
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_MASK         0x00020000
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_SHIFT        17
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_DEFAULT      0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: hour_counter_init [16:12] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_MASK          0x0001f000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_SHIFT         12
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: minute_counter_init [11:06] */
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_MASK        0x00000fc0
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_SHIFT       6
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_DEFAULT     0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: second_counter_init [05:00] */
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_MASK        0x0000003f
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_SHIFT       0
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_DEFAULT     0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_0 - Digit Code for digit 0, 1, 2, 3
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_3 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_2 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_1 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_0 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_1 - Digit Code for digit 4, 5, 6, 7
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_7 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_6 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_5 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_4 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_2 - Digit Code for digit 8, 9
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_MASK              0xffff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_SHIFT             16
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_9 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_8 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_ADDR_OFFSET - Hour MSD/LSD and minute MSD/LSD address offset
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_msd_addr_offset [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_MASK 0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_SHIFT 24
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_DEFAULT 0x00000020
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_lsd_addr_offset [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_MASK 0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_SHIFT 16
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_DEFAULT 0x00000024
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_msd_addr_offset [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_MASK 0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_SHIFT 8
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_DEFAULT 0x00000018
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_lsd_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_MASK 0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_SHIFT 0
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_DEFAULT 0x0000001c
+
+/***************************************************************************
+ *LED_STATUS_CTRL - LED status control
+ ***************************************************************************/
+/* AON_CTRL :: LED_STATUS_CTRL :: reserved0 [31:28] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_MASK               0xf0000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_SHIFT              28
+
+/* AON_CTRL :: LED_STATUS_CTRL :: hlcd_state [27:25] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_MASK              0x0e000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_SHIFT             25
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_IDLE         0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_COUNT        1
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_LSD 2
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_MSD 3
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_LSD 4
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_MSD 5
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_STATUS 6
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_update_enable [24:24] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_MASK    0x01000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_SHIFT   24
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_DEFAULT 0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_mask [23:12] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_MASK             0x00fff000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_SHIFT            12
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_DEFAULT          0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_bit_offset [11:08] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_MASK       0x00000f00
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_SHIFT      8
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_DEFAULT    0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_MASK      0x000000ff
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_SHIFT     0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK         0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT        31
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK         0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT        30
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK         0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT        29
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK         0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT        28
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK         0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT        27
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK         0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT        26
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK         0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT        25
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK         0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT        24
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK         0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT        23
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK         0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT        22
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK         0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT        21
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK         0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT        20
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK         0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT        19
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK         0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT        18
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK         0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT        17
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK         0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT        16
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK         0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT        15
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK         0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT        14
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK         0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT        13
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK         0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT        12
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK         0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT        11
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK         0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT        10
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK          0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT         9
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK          0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT         8
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK          0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT         7
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK          0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT         6
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK          0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT         5
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK          0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT         4
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK          0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT         3
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK          0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT         2
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK          0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT         1
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK          0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT         0
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT       0x00000000
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_MASK              0xffffff00
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_SHIFT             8
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_MASK      0x00000080
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT     7
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_MASK      0x00000040
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT     6
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_MASK      0x00000020
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT     5
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_MASK      0x00000010
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT     4
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_MASK      0x00000008
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT     3
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_MASK      0x00000004
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT     2
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_MASK      0x00000002
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT     1
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: ejtag_ce_wakeup_event [00:00] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_MASK  0x00000001
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_MASK 0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_SHIFT 31
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_MASK 0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_SHIFT 30
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_MASK 0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_SHIFT 29
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_MASK 0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_SHIFT 28
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_MASK 0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_SHIFT 27
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_MASK 0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_SHIFT 26
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_MASK 0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_SHIFT 25
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_MASK 0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_SHIFT 24
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_MASK 0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_SHIFT 23
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_MASK 0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_SHIFT 22
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_MASK 0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_SHIFT 21
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_MASK 0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_SHIFT 20
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_MASK 0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_SHIFT 19
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_MASK 0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_SHIFT 18
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_MASK 0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_SHIFT 17
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_MASK 0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_SHIFT 16
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_MASK 0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_SHIFT 15
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_MASK 0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_SHIFT 14
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_MASK 0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_SHIFT 13
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_MASK 0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_SHIFT 12
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_MASK 0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_SHIFT 11
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_MASK 0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_SHIFT 10
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_MASK 0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_SHIFT 5
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_MASK 0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_SHIFT 4
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_MASK 0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_SHIFT 3
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_MASK 0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_SHIFT 2
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_hys_en [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_hys_en_MASK     0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_hys_en_SHIFT    0
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_hys_en_DEFAULT  0x00000001
+
+/***************************************************************************
+ *SPARE_CTRL_0 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_DEFAULT           0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL_1 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_DEFAULT           0x00000000
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* AON_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK     0xffffffff
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT    0
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT  0x00000000
+
+/***************************************************************************
+ *RESET_HISTORY - Reset History Register For AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_HISTORY :: reserved0 [31:19] */
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_MASK                 0xfff80000
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_SHIFT                19
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [18:18] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK    0x00040000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT   18
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [17:17] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK    0x00020000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT   17
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [16:16] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK     0x00010000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT    16
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [15:15] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK     0x00008000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT    15
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [14:14] */
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK           0x00004000
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT          14
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_DEFAULT        0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: overtemp_reset [13:13] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_MASK            0x00002000
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_SHIFT           13
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_DEFAULT         0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: overvoltage_reset [12:12] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_MASK         0x00001000
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT        12
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_DEFAULT      0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: undervoltage_reset [11:11] */
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_MASK        0x00000800
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT       11
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_DEFAULT     0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: security_dl_sw_reset [10:10] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK      0x00000400
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT     10
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_DEFAULT   0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: security_master_reset [09:09] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_MASK     0x00000200
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_SHIFT    9
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: software_master_reset [08:08] */
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_MASK     0x00000100
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_SHIFT    8
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [07:07] */
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK       0x00000080
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT      7
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_DEFAULT    0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: watchdog_timer_reset [06:06] */
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK      0x00000040
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT     6
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_DEFAULT   0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: smartcard_insert_reset [05:05] */
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK    0x00000020
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT   5
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: s3_wakeup_reset [04:04] */
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_MASK           0x00000010
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_SHIFT          4
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_DEFAULT        0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [03:03] */
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK    0x00000008
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT   3
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: tap_in_system_reset [02:02] */
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_MASK       0x00000004
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_SHIFT      2
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_DEFAULT    0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_MASK     0x00000002
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT    1
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_MASK            0x00000001
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_SHIFT           0
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_DEFAULT         0x00000001
+
+/***************************************************************************
+ *NMI_CTRL - Control register for NMI
+ ***************************************************************************/
+/* AON_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_MASK                0x80000000
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_SHIFT               31
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_DEFAULT             0x00000000
+
+/* AON_CTRL :: NMI_CTRL :: reserved0 [30:03] */
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_MASK                      0x7ffffff8
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_SHIFT                     3
+
+/* AON_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_MASK                0x00000004
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT               2
+
+/* AON_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_MASK            0x00000002
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT           1
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_DEFAULT         0x00000000
+
+/* AON_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_MASK                0x00000001
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT               0
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_DEFAULT             0x00000001
+
+/***************************************************************************
+ *ANA_XTAL_CONTROL - Ana xtal low cur 40g m7fc gisb control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_CONTROL :: reserved0 [31:07] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_MASK              0xffffff80
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_SHIFT             7
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_test_select_gisb_control [06:06] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_MASK 0x00000040
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_SHIFT 6
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_select_current_gisb_control [05:05] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_MASK 0x00000020
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_SHIFT 5
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_cml_sel_pd [04:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_MASK         0x00000018
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_SHIFT        3
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_DEFAULT      0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_d2cbias_gisb_control [02:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_MASK 0x00000007
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_SHIFT 0
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_DEFAULT 0x00000004
+
+/***************************************************************************
+ *SUB_TEST_MODE_CTRL - Test_mode control register
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: reserved0 [31:01] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_MASK            0xfffffffe
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_SHIFT           1
+
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: use_sub_test_mode_reg_src [00:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_MASK 0x00000001
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_SHIFT 0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SUB_TEST_MODE - Register source for sub_test_mode
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE :: reserved0 [31:09] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_MASK                 0xfffffe00
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_SHIFT                9
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [08:08] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK     0x00000100
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT    8
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_DEFAULT  0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [07:07] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK     0x00000080
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT    7
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_DEFAULT  0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_d2cdiff_ac [06:06] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_MASK  0x00000040
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_SHIFT 6
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [05:05] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK   0x00000020
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT  5
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_mips_in_reset [04:04] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_MASK 0x00000010
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_SHIFT 4
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [03:03] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000008
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 3
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [02:02] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000004
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 2
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK   0x00000003
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT  0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_DEFAULT 0x00000000
+
+/***************************************************************************
+ *LATCHED_TEST_MODE - Final latched testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK     0xffffffff
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT    0
+
+/***************************************************************************
+ *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0
+
+/***************************************************************************
+ *PM_INITIATE - Power down initiate
+ ***************************************************************************/
+/* AON_CTRL :: PM_INITIATE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_MASK                   0xffffff00
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_SHIFT                  8
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_7 [07:07] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_MASK               0x00000080
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_SHIFT              7
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_6 [06:06] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_MASK               0x00000040
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_SHIFT              6
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_5 [05:05] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_MASK               0x00000020
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_SHIFT              5
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_4 [04:04] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_MASK               0x00000010
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_SHIFT              4
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_3 [03:03] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_MASK               0x00000008
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_SHIFT              3
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_2 [02:02] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_MASK               0x00000004
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_SHIFT              2
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_1 [01:01] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_MASK               0x00000002
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_SHIFT              1
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_0 [00:00] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_MASK               0x00000001
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_SHIFT              0
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_DEFAULT            0x00000000
+
+/***************************************************************************
+ *HOST_MISC_CMDS - Power up restore
+ ***************************************************************************/
+/* AON_CTRL :: HOST_MISC_CMDS :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_MASK                0xffffff00
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_SHIFT               8
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_7 [07:07] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_MASK         0x00000080
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_SHIFT        7
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_6 [06:06] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_MASK         0x00000040
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_SHIFT        6
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_5 [05:05] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_MASK         0x00000020
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_SHIFT        5
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_4 [04:04] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_MASK         0x00000010
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_SHIFT        4
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_3 [03:03] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_MASK         0x00000008
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_SHIFT        3
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_2 [02:02] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_MASK         0x00000004
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_SHIFT        2
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: dram_scram_key_reuse_req [01:01] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_MASK 0x00000002
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_SHIFT 1
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_DEFAULT 0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: pm_restore [00:00] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_MASK               0x00000001
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_SHIFT              0
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_BASE                  0x00408200
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_START                 0
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_END                   127
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_ELEMENT_SIZE          32
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_RAMi :: SYSTEM_DATA_RAM [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_MASK        0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_SHIFT       0
+
+
+#endif /* #ifndef BCHP_AON_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_aon_pin_ctrl.h b/include/linux/brcmstb/7362a0/bchp_aon_pin_ctrl.h
new file mode 100644
index 0000000..aa67f14
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_aon_pin_ctrl.h
@@ -0,0 +1,651 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_aon_pin_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:25a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PIN_CTRL_H__
+#define BCHP_AON_PIN_CTRL_H__
+
+/***************************************************************************
+ *AON_PIN_CTRL - AON Pinmux Control Registers
+ ***************************************************************************/
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0         0x00408500 /* Pinmux control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1         0x00408504 /* Pinmux control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2         0x00408508 /* Pinmux control register 2 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3         0x0040850c /* Pinmux control register 3 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0     0x00408510 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1     0x00408514 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2     0x00408518 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0     0x0040851c /* Bypass clock unselect register 0 */
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_05 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_AON_GPIO_05   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_LD1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PKT5_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_I2S_DATA0_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SC_CLK_OUT    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MTSIF_ATS_RST 5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SDS0_DSEC_SELVTOP 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SC1_AUX1      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_TP_IN_05      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PM_AON_GPIO_05 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_04 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_AON_GPIO_04   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_LD0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PKT5_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_I2S_CLK0_OUT  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_EXT_IRQ1      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_IR_OUT        5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SDS0_TNR_SDA  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SC1_VPP       7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_TP_IN_04      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PM_AON_GPIO_04 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_03 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_GPIO_03   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_OUT       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PWR_BUTTON    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_FP_4SEC_RESETB 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_EXT_IRQ0      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_IR_OUT        5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SDS0_TNR_SCL  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SDIO0_PRES    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_TP_IN_03      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PM_AON_GPIO_03 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_01 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AON_GPIO_01   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET_LINK     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_PWM0          2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET_ACTIVITY 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_IR_OUT        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_VEC_HSYNC     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_RMX1_VALID    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SDS0_TNR_SCL  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_TP_OUT_01     8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_00 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AON_GPIO_00   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AUD_SPDIF     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_CLK_OBSRV1    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_TP_OUT_00     3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_hdmi_htplg [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_MASK       0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_SHIFT      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_DEFAULT    0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_AON_HDMI_HTPLG 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_TP_IN_02   1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_s3_standbyb [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_MASK      0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_SHIFT     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_DEFAULT   0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_AON_S3_STANDBYB 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_TP_IN_01  1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_ir_in0 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_MASK           0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_SHIFT          0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_DEFAULT        0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_AON_IR_IN0     0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_TP_IN_00       1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_13 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_AON_GPIO_13   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_LED_LS1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PKT2_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_I2S_DATA0_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PWM0          4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SDIO0_CLK     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_USB0_PWRFLT_1 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MTSIF0_DATA0  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_TP_OUT_05     8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PM_AON_GPIO_13 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_12 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_AON_GPIO_12   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_LS0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PKT2_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_I2S_CLK0_OUT  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_OUT       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SDIO0_PWR0    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MTSIF0_CLK    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_TP_OUT_04     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PM_AON_GPIO_12 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_11 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_GPIO_11   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_LED_LD7       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SC1_CLK       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_CODEC_MCLK    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_CLK_27    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SPI_M_SCK     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_TP_OUT_03     6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_10 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_AON_GPIO_10   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_LED_LD6       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SC1_VCC       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_CODEC_SDO     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_UART_RTS2     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SPI_M_SS0B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_TP_OUT_02     6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_09 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_AON_GPIO_09   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_LED_LD5       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SC1_RST       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_CODEC_SCLK    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_UART_TX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SPI_M_MOSI    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_FSK_RX_BYP_DATA 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MTSIF0_DATA5  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_TP_IN_09      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_PM_AON_GPIO_09 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_08 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_AON_GPIO_08   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_LED_LD4       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SC1_IO        2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_CODEC_FSYNCB  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_UART_CTS2     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SPI_M_SS1B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SDIO0_PRES    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MTSIF0_DATA1  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_TP_IN_08      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_PM_AON_GPIO_08 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_07 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_AON_GPIO_07   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_LED_LD3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SC1_PRES      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_CODEC_SDI     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_UART_RX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SPI_M_MISO    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_FSK_UART_DATA 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MTSIF0_VALID  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_TP_IN_07      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_PM_AON_GPIO_07 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_06 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_AON_GPIO_06   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_LED_LD2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PKT5_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_I2S_LR0_OUT   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SC_EXT_CLK    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_VEC_VSYNC     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SDS0_DSEC_VCTL 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SC1_AUX2      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_TP_IN_06      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PM_AON_GPIO_06 9
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_00 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_MASK         0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SHIFT        28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_AON_SGPIO_00 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_BSC_M3_SCL   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_USB0_PWRFLT_1 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_EXT_IRQ2     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SDS0_TNR_SCL 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_TP_IN_16     5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_20 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_GPIO_20   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_LED_KD3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PKT4_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_CLK_OBSRV0    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_CLK_27    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SDIO0_WPROT   5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_RO_OBSRV      6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MTSIF0_DATA7  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_TP_IN_15      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PM_AON_GPIO_20 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_19 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_AON_GPIO_19   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_LED_KD2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_PKT4_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SC1_PRES      3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SPI_M_MISO    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SDIO0_CMD     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MTSIF0_DATA6  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_TP_IN_14      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_PM_AON_GPIO_19 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_18 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_AON_GPIO_18   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_LED_KD1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PKT4_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SC1_IO        3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SPI_M_SS1B    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SDIO0_DAT3    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MTSIF_ATS_INC 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_TP_IN_13      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PM_AON_GPIO_18 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_17 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_AON_GPIO_17   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_LED_KD0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PKT3_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SC1_RST       3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SPI_M_MOSI    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SDIO0_DAT2    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PWR_BUTTON    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MTSIF0_DATA4  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_TP_IN_12      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PM_AON_GPIO_17 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_16 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_AON_GPIO_16   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_LED_LS4       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PKT3_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SC1_CLK       3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SPI_M_SCK     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SDIO0_DAT1    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MTSIF0_DATA3  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_TP_IN_11      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PM_AON_GPIO_16 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_15 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_AON_GPIO_15   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_LED_LS3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PKT3_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SC1_VCC       3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SPI_M_SS0B    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SDIO0_DAT0    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_MTSIF0_DATA2  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_TP_IN_10      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PM_AON_GPIO_15 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_14 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_AON_GPIO_14   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_LED_LS2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_PKT2_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_I2S_LR0_OUT   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SDIO0_LED     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_USB0_PWRFLT_2 5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_MTSIF0_SYNC   6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_TP_OUT_06     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_PM_AON_GPIO_14 8
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: reserved0 [31:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_MASK            0xfffff000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_SHIFT           12
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: sgpio_01 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_MASK             0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_SHIFT            8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_DEFAULT          0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_SGPIO_01         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_BSC_M0_SDA       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_HDMI_TX_BSC_SDA  2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: sgpio_00 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_MASK             0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_SHIFT            4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_DEFAULT          0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_SGPIO_00         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_BSC_M0_SCL       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_HDMI_TX_BSC_SCL  2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_01 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_MASK         0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_SHIFT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_AON_SGPIO_01 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_BSC_M3_SDA   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_USB0_PWRFLT_2 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_EXT_IRQ3     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_SDS0_TNR_SDA 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_TP_IN_17     5
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_08_pad_ctrl [29:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_MASK 0x30000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_SHIFT 28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_07_pad_ctrl [27:26] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_MASK 0x0c000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_SHIFT 26
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_06_pad_ctrl [25:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_MASK 0x03000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_SHIFT 24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_05_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_04_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_03_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_01_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_00_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [13:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x00003fff
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0x3f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       24
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_20_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_19_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_18_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_17_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_16_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_15_pad_ctrl [13:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_MASK 0x00003000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_SHIFT 12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_14_pad_ctrl [11:10] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_MASK 0x00000c00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_SHIFT 10
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_13_pad_ctrl [09:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_MASK 0x00000300
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_SHIFT 8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_12_pad_ctrl [07:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_MASK 0x000000c0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_SHIFT 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_11_pad_ctrl [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_10_pad_ctrl [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_09_pad_ctrl [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_MASK 0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_SHIFT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [31:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK        0xfffffff0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT       4
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved1 [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_MASK        0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_SHIFT       0
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:04] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffff0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       4
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_01 [03:03] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_MASK 0x00000008
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_SHIFT 3
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_00 [02:02] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_MASK 0x00000004
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_SHIFT 2
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_nmib [01:01] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_MASK 0x00000002
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_SHIFT 1
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_reset_outb [00:00] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_MASK 0x00000001
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_SHIFT 0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_AON_PIN_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_aon_pm_l2.h b/include/linux/brcmstb/7362a0/bchp_aon_pm_l2.h
new file mode 100644
index 0000000..f4e7e25
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_aon_pm_l2.h
@@ -0,0 +1,1107 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_aon_pm_l2.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:25a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PM_L2_H__
+#define BCHP_AON_PM_L2_H__
+
+/***************************************************************************
+ *AON_PM_L2 - AON Power Management L2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_AON_PM_L2_CPU_STATUS                0x00408440 /* CPU interrupt Status Register */
+#define BCHP_AON_PM_L2_CPU_SET                   0x00408444 /* CPU interrupt Set Register */
+#define BCHP_AON_PM_L2_CPU_CLEAR                 0x00408448 /* CPU interrupt Clear Register */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS           0x0040844c /* CPU interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_CPU_MASK_SET              0x00408450 /* CPU interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR            0x00408454 /* CPU interrupt Mask Clear Register */
+#define BCHP_AON_PM_L2_PCI_STATUS                0x00408458 /* PCI interrupt Status Register */
+#define BCHP_AON_PM_L2_PCI_SET                   0x0040845c /* PCI interrupt Set Register */
+#define BCHP_AON_PM_L2_PCI_CLEAR                 0x00408460 /* PCI interrupt Clear Register */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS           0x00408464 /* PCI interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_PCI_MASK_SET              0x00408468 /* PCI interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR            0x0040846c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_STATUS :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_MASK                   0xffff0000
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_SHIFT                  16
+
+/* AON_PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x00008000
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       15
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_MASK                    0x00004000
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_SHIFT                   14
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00002000
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_SHIFT          13
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_MASK                     0x00001000
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_SHIFT                    12
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_MASK                         0x00000800
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_SHIFT                        11
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_MASK                   0x00000400
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_SHIFT                  10
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_MASK                   0x00000200
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_SHIFT                  9
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_MASK                 0x00000100
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_SHIFT                8
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_DEFAULT              0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_MASK                 0x00000080
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_SHIFT                7
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_DEFAULT              0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_MASK                    0x00000040
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_SHIFT                   6
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_SET :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_MASK                      0xffff0000
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_SHIFT                     16
+
+/* AON_PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_MASK           0x00008000
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_SHIFT          15
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_MASK                       0x00004000
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_SHIFT                      14
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_MASK              0x00002000
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_SHIFT             13
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_DEFAULT           0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_MASK                        0x00001000
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_SHIFT                       12
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_SET_FTM_MASK                            0x00000800
+#define BCHP_AON_PM_L2_CPU_SET_FTM_SHIFT                           11
+#define BCHP_AON_PM_L2_CPU_SET_FTM_DEFAULT                         0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_MASK                      0x00000400
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_SHIFT                     10
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_MASK                      0x00000200
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_SHIFT                     9
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_MASK                    0x00000100
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_SHIFT                   8
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_MASK                    0x00000080
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_SHIFT                   7
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_MASK                       0x00000040
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_SHIFT                      6
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_CLEAR :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_MASK                    0xffff0000
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_SHIFT                   16
+
+/* AON_PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x00008000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        15
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_MASK                     0x00004000
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_SHIFT                    14
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00002000
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           13
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_MASK                      0x00001000
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT                     12
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_MASK                          0x00000800
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_SHIFT                         11
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_DEFAULT                       0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_MASK                    0x00000400
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_SHIFT                   10
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_MASK                    0x00000200
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_SHIFT                   9
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_MASK                  0x00000100
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_SHIFT                 8
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_MASK                  0x00000080
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_SHIFT                 7
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_MASK                     0x00000040
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_SHIFT                    6
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_MASK              0xffff0000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT             16
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  15
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_MASK               0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_SHIFT              14
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     13
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK                0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT               12
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_MASK                    0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_SHIFT                   11
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_MASK              0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_SHIFT             10
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_MASK              0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_SHIFT             9
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_MASK            0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_SHIFT           8
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_DEFAULT         0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_MASK            0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_SHIFT           7
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_DEFAULT         0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_MASK               0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_SHIFT              6
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_DEFAULT            0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_SET :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_MASK                 0xffff0000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_SHIFT                16
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     15
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_MASK                  0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_SHIFT                 14
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        13
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_MASK                   0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT                  12
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_MASK                       0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_SHIFT                      11
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_DEFAULT                    0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_MASK                 0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_SHIFT                10
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_MASK                 0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_SHIFT                9
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_MASK               0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_SHIFT              8
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_MASK               0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_SHIFT              7
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_MASK                  0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_SHIFT                 6
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_DEFAULT               0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_MASK               0xffff0000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT              16
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   15
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_MASK                0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_SHIFT               14
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      13
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK                 0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT                12
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_MASK                     0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_SHIFT                    11
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_DEFAULT                  0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_MASK               0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_SHIFT              10
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_MASK               0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_SHIFT              9
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_MASK             0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_SHIFT            8
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_MASK             0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_SHIFT            7
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_MASK                0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_SHIFT               6
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_DEFAULT             0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_STATUS :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_MASK                   0xffff0000
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_SHIFT                  16
+
+/* AON_PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x00008000
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       15
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_MASK                    0x00004000
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_SHIFT                   14
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00002000
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_SHIFT          13
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_MASK                     0x00001000
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_SHIFT                    12
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_MASK                         0x00000800
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_SHIFT                        11
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_MASK                   0x00000400
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_SHIFT                  10
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_MASK                   0x00000200
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_SHIFT                  9
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_MASK                 0x00000100
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_SHIFT                8
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_DEFAULT              0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_MASK                 0x00000080
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_SHIFT                7
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_DEFAULT              0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_MASK                    0x00000040
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_SHIFT                   6
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_SET :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_MASK                      0xffff0000
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_SHIFT                     16
+
+/* AON_PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_MASK           0x00008000
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_SHIFT          15
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_MASK                       0x00004000
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_SHIFT                      14
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_MASK              0x00002000
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_SHIFT             13
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_DEFAULT           0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_MASK                        0x00001000
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_SHIFT                       12
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_SET_FTM_MASK                            0x00000800
+#define BCHP_AON_PM_L2_PCI_SET_FTM_SHIFT                           11
+#define BCHP_AON_PM_L2_PCI_SET_FTM_DEFAULT                         0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_MASK                      0x00000400
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_SHIFT                     10
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_MASK                      0x00000200
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_SHIFT                     9
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_MASK                    0x00000100
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_SHIFT                   8
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_MASK                    0x00000080
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_SHIFT                   7
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_MASK                       0x00000040
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_SHIFT                      6
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_CLEAR :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_MASK                    0xffff0000
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_SHIFT                   16
+
+/* AON_PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x00008000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        15
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_MASK                     0x00004000
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_SHIFT                    14
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00002000
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           13
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_MASK                      0x00001000
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT                     12
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_MASK                          0x00000800
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_SHIFT                         11
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_DEFAULT                       0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_MASK                    0x00000400
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_SHIFT                   10
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_MASK                    0x00000200
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_SHIFT                   9
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_MASK                  0x00000100
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_SHIFT                 8
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_MASK                  0x00000080
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_SHIFT                 7
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_MASK                     0x00000040
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_SHIFT                    6
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_MASK              0xffff0000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT             16
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  15
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_MASK               0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_SHIFT              14
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     13
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK                0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT               12
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_MASK                    0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_SHIFT                   11
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_MASK              0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_SHIFT             10
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_MASK              0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_SHIFT             9
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_MASK            0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_SHIFT           8
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_DEFAULT         0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_MASK            0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_SHIFT           7
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_DEFAULT         0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_MASK               0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_SHIFT              6
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_DEFAULT            0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_SET :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_MASK                 0xffff0000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_SHIFT                16
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     15
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_MASK                  0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_SHIFT                 14
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        13
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_MASK                   0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT                  12
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_MASK                       0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_SHIFT                      11
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_DEFAULT                    0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_MASK                 0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_SHIFT                10
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_MASK                 0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_SHIFT                9
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_MASK               0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_SHIFT              8
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_MASK               0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_SHIFT              7
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_MASK                  0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_SHIFT                 6
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_DEFAULT               0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_MASK               0xffff0000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT              16
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   15
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_MASK                0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_SHIFT               14
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      13
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK                 0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT                12
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_MASK                     0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_SHIFT                    11
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_DEFAULT                  0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_MASK               0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_SHIFT              10
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_MASK               0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_SHIFT              9
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_MASK             0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_SHIFT            8
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_MASK             0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_SHIFT            7
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_MASK                0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_SHIFT               6
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_DEFAULT             0x00000001
+
+#endif /* #ifndef BCHP_AON_PM_L2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_bspi.h b/include/linux/brcmstb/7362a0/bchp_bspi.h
new file mode 100644
index 0000000..35cd173
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_bspi.h
@@ -0,0 +1,446 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_bspi.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:37a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_H__
+#define BCHP_BSPI_H__
+
+/***************************************************************************
+ *BSPI - Public BSPI Control Registers
+ ***************************************************************************/
+#define BCHP_BSPI_REVISION_ID                    0x00413000 /* Revision ID */
+#define BCHP_BSPI_SCRATCH                        0x00413004 /* Revision ID */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL               0x00413008 /* Master/Boot SPI Control Register */
+#define BCHP_BSPI_BUSY_STATUS                    0x0041300c /* BSPI Busy Status Register */
+#define BCHP_BSPI_INTR_STATUS                    0x00413010 /* Interrupt Status Register */
+#define BCHP_BSPI_B0_STATUS                      0x00413014 /* Prefetch Buffer 0 Status Register */
+#define BCHP_BSPI_B0_CTRL                        0x00413018 /* Prefetch Buffer 0 Control Register */
+#define BCHP_BSPI_B1_STATUS                      0x0041301c /* Prefetch Buffer 1 Status Register */
+#define BCHP_BSPI_B1_CTRL                        0x00413020 /* Prefetch Buffer 1 Control Register */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL            0x00413024 /* Dual/Single Receive Mode Control Register */
+#define BCHP_BSPI_FLEX_MODE_ENABLE               0x00413028 /* Flexible Control Mode Enable Register */
+#define BCHP_BSPI_BITS_PER_CYCLE                 0x0041302c /* Bits per cycle "b-p-c" Control Register */
+#define BCHP_BSPI_BITS_PER_PHASE                 0x00413030 /* Bits per Phase "b-p-p" Control Register */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE              0x00413034 /* Command and Mode Data Register */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE     0x00413038 /* Bspi FLash upper address byte register */
+#define BCHP_BSPI_BSPI_XOR_VALUE                 0x0041303c /* BSPI FLASH XOR Value Register */
+#define BCHP_BSPI_BSPI_XOR_ENABLE                0x00413040 /* BSPI FLASH XOR Enable Register */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE           0x00413044 /* BSPI Pin  Programmed IO Mode Enable Register */
+#define BCHP_BSPI_BSPI_PIO_IODIR                 0x00413048 /* BSPI Pin  Programmed IO Mode Direction Register */
+#define BCHP_BSPI_BSPI_PIO_DATA                  0x0041304c /* BSPI Pin  Programmed IO Mode Data Register */
+
+/***************************************************************************
+ *REVISION_ID - Revision ID
+ ***************************************************************************/
+/* BSPI :: REVISION_ID :: reserved0 [31:16] */
+#define BCHP_BSPI_REVISION_ID_reserved0_MASK                       0xffff0000
+#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT                      16
+
+/* BSPI :: REVISION_ID :: MAJOR [15:08] */
+#define BCHP_BSPI_REVISION_ID_MAJOR_MASK                           0x0000ff00
+#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT                          8
+#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT                        0x00000004
+
+/* BSPI :: REVISION_ID :: MINOR [07:00] */
+#define BCHP_BSPI_REVISION_ID_MINOR_MASK                           0x000000ff
+#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT                          0
+#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT                        0x00000001
+
+/***************************************************************************
+ *SCRATCH - Revision ID
+ ***************************************************************************/
+/* BSPI :: SCRATCH :: SCRATCH [31:00] */
+#define BCHP_BSPI_SCRATCH_SCRATCH_MASK                             0xffffffff
+#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT                            0
+#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
+ ***************************************************************************/
+/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT                 1
+
+/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK                0x00000001
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT               0
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT             0x00000000
+
+/***************************************************************************
+ *BUSY_STATUS - BSPI Busy Status Register
+ ***************************************************************************/
+/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
+#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK                       0xfffffffe
+#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT                      1
+
+/* BSPI :: BUSY_STATUS :: busy [00:00] */
+#define BCHP_BSPI_BUSY_STATUS_busy_MASK                            0x00000001
+#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT                           0
+#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *INTR_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
+#define BCHP_BSPI_INTR_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT                      2
+
+/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
+#define BCHP_BSPI_INTR_STATUS_intr_1_MASK                          0x00000002
+#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT                         1
+#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT                       0x00000000
+
+/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
+#define BCHP_BSPI_INTR_STATUS_intr_0_MASK                          0x00000001
+#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT                         0
+#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *B0_STATUS - Prefetch Buffer 0 Status Register
+ ***************************************************************************/
+/* BSPI :: B0_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B0_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B0_STATUS :: b0_full [29:29] */
+#define BCHP_BSPI_B0_STATUS_b0_full_MASK                           0x20000000
+#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT                          29
+#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_empty [28:28] */
+#define BCHP_BSPI_B0_STATUS_b0_empty_MASK                          0x10000000
+#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT                         28
+#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B0_STATUS :: b0_miss [27:27] */
+#define BCHP_BSPI_B0_STATUS_b0_miss_MASK                           0x08000000
+#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT                          27
+#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_hit [26:26] */
+#define BCHP_BSPI_B0_STATUS_b0_hit_MASK                            0x04000000
+#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT                           26
+#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B0_STATUS :: b0_address [25:00] */
+#define BCHP_BSPI_B0_STATUS_b0_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT                       0
+#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B0_CTRL - Prefetch Buffer 0 Control Register
+ ***************************************************************************/
+/* BSPI :: B0_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B0_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B0_CTRL :: b0_flush [00:00] */
+#define BCHP_BSPI_B0_CTRL_b0_flush_MASK                            0x00000001
+#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT                           0
+#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *B1_STATUS - Prefetch Buffer 1 Status Register
+ ***************************************************************************/
+/* BSPI :: B1_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B1_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B1_STATUS :: b1_full [29:29] */
+#define BCHP_BSPI_B1_STATUS_b1_full_MASK                           0x20000000
+#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT                          29
+#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_empty [28:28] */
+#define BCHP_BSPI_B1_STATUS_b1_empty_MASK                          0x10000000
+#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT                         28
+#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B1_STATUS :: b1_miss [27:27] */
+#define BCHP_BSPI_B1_STATUS_b1_miss_MASK                           0x08000000
+#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT                          27
+#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_hit [26:26] */
+#define BCHP_BSPI_B1_STATUS_b1_hit_MASK                            0x04000000
+#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT                           26
+#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B1_STATUS :: b1_address [25:00] */
+#define BCHP_BSPI_B1_STATUS_b1_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT                       0
+#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B1_CTRL - Prefetch Buffer 1 Control Register
+ ***************************************************************************/
+/* BSPI :: B1_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B1_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B1_CTRL :: b1_flush [00:00] */
+#define BCHP_BSPI_B1_CTRL_b1_flush_MASK                            0x00000001
+#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT                           0
+#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
+ ***************************************************************************/
+/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK               0xffffffe0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT              5
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK             0x00000010
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT            4
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT          0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK               0x00000008
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT              3
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT            0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK      0x00000004
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT     2
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT   0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK         0x00000002
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT        1
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT      0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK                0x00000001
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT               0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT             0x00000000
+
+/***************************************************************************
+ *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT                 1
+
+/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK      0x00000001
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT     0
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT   0x00000000
+
+/***************************************************************************
+ *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK                    0xfc000000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT                   26
+
+/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK               0x03000000
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK                    0x00fc0000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT                   18
+
+/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK              0x00030000
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK                    0x0000fc00
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT                   10
+
+/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK              0x00000300
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT             8
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK                    0x000000fc
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT                   2
+
+/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK              0x00000003
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT             0
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT           0x00000000
+
+/***************************************************************************
+ *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK                    0xfe000000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT                   25
+
+/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK               0x01000000
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK                    0x00fe0000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT                   17
+
+/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK              0x00010000
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK                    0x0000fe00
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT                   9
+
+/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK                     0x00000100
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT                    8
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT                  0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK                 0x000000ff
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT                0
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT              0x00000008
+
+/***************************************************************************
+ *CMD_AND_MODE_BYTE - Command and Mode Data Register
+ ***************************************************************************/
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK                 0xff000000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT                24
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK            0x00ff0000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT           16
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT         0x00000000
+
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK                 0x0000ff00
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT                8
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK             0x000000ff
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT            0
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT          0x0000000b
+
+/***************************************************************************
+ *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
+ ***************************************************************************/
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0x00000000
+
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK        0x00ffffff
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT       0
+
+/***************************************************************************
+ *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK               0xfff00000
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT              20
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT            0x00000000
+
+/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK                    0x000fffff
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT                  1
+
+/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK             0x00000001
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT            0
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT          0x00000000
+
+/***************************************************************************
+ *BSPI_PIO_MODE_ENABLE - BSPI Pin  Programmed IO Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK              0xfffffffe
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT             1
+
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK          0x00000001
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT         0
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT       0x00000000
+
+/***************************************************************************
+ *BSPI_PIO_IODIR - BSPI Pin  Programmed IO Mode Direction Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK                    0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT                   3
+
+/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT              0x00000003
+
+/***************************************************************************
+ *BSPI_PIO_DATA - BSPI Pin  Programmed IO Mode Data Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK                     0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT                    3
+
+/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT              0x00000000
+
+#endif /* #ifndef BCHP_BSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_bspi_raf.h b/include/linux/brcmstb/7362a0/bchp_bspi_raf.h
new file mode 100644
index 0000000..22407cc
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_bspi_raf.h
@@ -0,0 +1,163 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_bspi_raf.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:37a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_RAF_H__
+#define BCHP_BSPI_RAF_H__
+
+/***************************************************************************
+ *BSPI_RAF - Public Linear Read BSPI Pipe Registers
+ ***************************************************************************/
+#define BCHP_BSPI_RAF_START_ADDR                 0x00413100 /* Physical Starting Address Location in Flash device */
+#define BCHP_BSPI_RAF_NUM_WORDS                  0x00413104 /* Number of Words to be fetched */
+#define BCHP_BSPI_RAF_CTRL                       0x00413108 /* RAF Session Control Register */
+#define BCHP_BSPI_RAF_FULLNESS                   0x0041310c /* Fullness indicator for the read ahead buffer */
+#define BCHP_BSPI_RAF_WATERMARK                  0x00413110 /* Watermark level in the read ahead buffer that triggers an interrupt */
+#define BCHP_BSPI_RAF_STATUS                     0x00413114 /* Linear Read Status Register */
+#define BCHP_BSPI_RAF_READ_DATA                  0x00413118 /* Read data from Raf-buffer */
+#define BCHP_BSPI_RAF_WORD_CNT                   0x0041311c /* Current number of words fetched from Flash */
+#define BCHP_BSPI_RAF_CURR_ADDR                  0x00413120 /* Current read address for the linear read session */
+
+/***************************************************************************
+ *START_ADDR - Physical Starting Address Location in Flash device
+ ***************************************************************************/
+/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK                   0xffffffff
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT                  0
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT                0x00000000
+
+/***************************************************************************
+ *NUM_WORDS - Number of Words to be fetched
+ ***************************************************************************/
+/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK                      0xffffffff
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT                     0
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *CTRL - RAF Session Control Register
+ ***************************************************************************/
+/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT                         2
+
+/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
+#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK                              0x00000002
+#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT                             1
+#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT                           0x00000000
+
+/* BSPI_RAF :: CTRL :: START [00:00] */
+#define BCHP_BSPI_RAF_CTRL_START_MASK                              0x00000001
+#define BCHP_BSPI_RAF_CTRL_START_SHIFT                             0
+#define BCHP_BSPI_RAF_CTRL_START_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *FULLNESS - Fullness indicator for the read ahead buffer
+ ***************************************************************************/
+/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK                      0xffffff80
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT                     7
+
+/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK                       0x0000007f
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT                      0
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
+ ***************************************************************************/
+/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK                     0xfffffffc
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT                    2
+
+/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK            0x00000003
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT           0
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STATUS - Linear Read Status Register
+ ***************************************************************************/
+/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
+#define BCHP_BSPI_RAF_STATUS_reserved0_MASK                        0xfffffff8
+#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT                       3
+
+/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK                        0x00000004
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT                       2
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT                     0x00000000
+
+/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK                       0x00000002
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT                      1
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT                    0x00000001
+
+/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK                     0x00000001
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT                    0
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *READ_DATA - Read data from Raf-buffer
+ ***************************************************************************/
+/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
+#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK                          0xffffffff
+#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT                         0
+#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *WORD_CNT - Current number of words fetched from Flash
+ ***************************************************************************/
+/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK             0xffffffff
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT            0
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *CURR_ADDR - Current read address for the linear read session
+ ***************************************************************************/
+/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK               0xffffffff
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT              0
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT            0x00000000
+
+#endif /* #ifndef BCHP_BSPI_RAF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_clkgen.h b/include/linux/brcmstb/7362a0/bchp_clkgen.h
new file mode 100644
index 0000000..39493d2
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_clkgen.h
@@ -0,0 +1,4689 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 24 17:25:41 2013
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_CLKGEN_H__
+#define BCHP_CLKGEN_H__
+
+/***************************************************************************
+ *CLKGEN - clkgen registers
+ ***************************************************************************/
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL       0x00420000 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV           0x00420004 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN          0x00420008 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS   0x0042000c /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN         0x00420010 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET         0x00420014 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x00420018 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x0042001c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS        0x00420020 /* Test Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL       0x00420024 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV           0x00420028 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN          0x0042002c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS   0x00420030 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN         0x00420034 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET         0x00420038 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x0042003c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x00420040 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS        0x00420044 /* Test Status */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 0x00420048 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 0x0042004c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 0x00420050 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 0x00420054 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL     0x00420058 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV         0x0042005c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN        0x00420060 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS 0x00420064 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC        0x00420068 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2       0x0042006c /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN       0x00420070 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x00420074 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x00420078 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS      0x0042007c /* Test Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0 0x00420080 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1 0x00420084 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3 0x00420088 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL           0x0042008c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV               0x00420090 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN              0x00420094 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS       0x00420098 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC              0x0042009c /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN             0x004200a0 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET             0x004200a4 /* Resets */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH 0x004200a8 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW 0x004200ac /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS            0x004200b0 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x004200b4 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x004200b8 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x004200bc /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x004200c0 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x004200c4 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x004200c8 /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL         0x004200cc /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV             0x004200d0 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN            0x004200d4 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS     0x004200d8 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC            0x004200dc /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2           0x004200e0 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN           0x004200e4 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x004200e8 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x004200ec /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS          0x004200f0 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 0x004200f4 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 0x004200f8 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 0x004200fc /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 0x00420100 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 0x00420104 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL         0x00420108 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV             0x0042010c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN            0x00420110 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS     0x00420114 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC            0x00420118 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN           0x0042011c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET           0x00420120 /* Resets */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH 0x00420124 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW 0x00420128 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS          0x0042012c /* Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 0x00420130 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 0x00420134 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 0x00420138 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL         0x0042013c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV             0x00420140 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC            0x00420144 /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN            0x00420148 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS     0x0042014c /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC            0x00420150 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN           0x00420154 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET           0x00420158 /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH 0x0042015c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW 0x00420160 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS          0x00420164 /* Status */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE        0x00420168 /* Avd0 top clock enable */
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE 0x0042016c /* Avd0 top memory standby enable */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK       0x00420170 /* Avd0 top observe clock */
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY 0x00420174 /* Avd0 top power switch memory */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE   0x00420178 /* Disable BCM_MIPS_TOP's clocks */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE    0x0042017c /* Bcm mips top clock enable */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE 0x00420180 /* Bcm mips top memory standby enable */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK   0x00420184 /* Bcm mips top observe clock */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY 0x00420188 /* Bcm mips top power switch memory */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT          0x0042018c /* Bcm mips top select */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE               0x00420190 /* Bvn top enable */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE 0x00420194 /* Bvn top memory standby enable */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY  0x00420198 /* Bvn top power switch memory */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x0042019c /* Cktap 108 0 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201a0 /* Cktap 108 1 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201a4 /* Cktap 108 2 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201a8 /* Cktap 216 0 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK 0x004201ac /* CKTAP CPU Adjustment System 108 Clock */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK 0x004201b0 /* CKTAP CPU Adjustment System 216 Clock */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK 0x004201b4 /* CKTAP CPU Adjustment System Scb Clock */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201b8 /* Cktap scb 0 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201bc /* Cktap scb 1 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE         0x004201c0 /* Disable CLKGEN's clocks */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL        0x004201c4 /* Clock Monitor Control */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT      0x004201c8 /* Clock Monitor Max Reference Count */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER    0x004201cc /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE       0x004201d0 /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER   0x004201d4 /* Clock Monitor View Counter */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE       0x004201d8 /* Disable CORE_XPT's clocks */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE        0x004201dc /* Core xpt clock enable */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE 0x004201e0 /* Core xpt memory standby enable */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK       0x004201e4 /* Core xpt observe clock */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY 0x004201e8 /* Core xpt power switch memory */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE         0x004201ec /* Disable DVP_HT's clocks */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE          0x004201f0 /* Dvp ht clock enable */
+#define BCHP_CLKGEN_DVP_HT_ENABLE                0x004201f4 /* Dvp ht enable */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE 0x004201f8 /* Dvp ht memory standby enable */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK         0x004201fc /* Dvp ht observe clock */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY   0x00420200 /* Dvp ht power switch memory */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE         0x00420204 /* Fsk top clock enable */
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE 0x00420208 /* Fsk top memory standby enable */
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY  0x0042020c /* Fsk top power switch memory */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE 0x00420210 /* Disable GENET_TOP_RGMII_INST's clocks */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE 0x00420214 /* Genet top rgmii inst clock enable */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT 0x00420218 /* Genet top rgmii inst clock select */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A 0x0042021c /* Genet top rgmii inst memory standby enable a */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK 0x00420220 /* Genet top rgmii inst observe clock */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A 0x00420224 /* Genet top rgmii inst power switch memory a */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE       0x00420228 /* Disable GRAPHICS's clocks */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE        0x0042022c /* Graphics clock enable */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE 0x00420230 /* Graphics memory standby enable */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK       0x00420234 /* Graphics observe clock */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY 0x00420238 /* Graphics power switch memory */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE            0x0042023c /* Disable HIF's clocks */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE             0x00420240 /* Hif clock enable */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE    0x00420244 /* Hif memory standby enable */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY      0x00420248 /* Hif power switch memory */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT          0x0042024c /* Mux selects for Internal clocks */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE       0x00420250 /* Memsys 16 clock enable */
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE 0x00420254 /* Memsys 16 memory standby enable */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK      0x00420258 /* Memsys 16 observe clock */
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY 0x0042025c /* Memsys 16 power switch memory */
+#define BCHP_CLKGEN_MEMSYS_16_STATUS             0x00420260 /* Memsys 16 status */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION   0x00420264 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION   0x00420268 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION   0x0042026c /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION   0x00420270 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE            0x00420274 /* Disable PAD's clocks */
+#define BCHP_CLKGEN_PAD_MUX_SELECT               0x00420278 /* Mux selects for Pad clocks */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS  0x0042027c /* PLL_AUDIO0 Reset Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS  0x00420280 /* PLL_AUDIO1 Reset Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS      0x00420284 /* PLL_SC Reset Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS    0x00420288 /* PLL_SYS1 Reset Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS    0x0042028c /* PLL_VCXO Reset Status */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL       0x00420290 /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL       0x00420294 /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x00420298 /* PLL Alive in Standby Mode */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE   0x0042029c /* Raaga dsp top clock enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE 0x004202a0 /* Raaga dsp top memory standby enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK  0x004202a4 /* Raaga dsp top observe clock */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY 0x004202a8 /* Raaga dsp top power switch memory */
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE         0x004202ac /* Rfm top clock enable */
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE 0x004202b0 /* Rfm top memory standby enable */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK        0x004202b4 /* Rfm top observe clock */
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY  0x004202b8 /* Rfm top power switch memory */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE       0x004202bc /* Sata3 top clock enable */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE      0x004202c0 /* Disable SATA3_TOP's clocks */
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE 0x004202c4 /* Sata3 memory standby enable */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK      0x004202c8 /* Sata3 top observe clock */
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL         0x004202cc /* Sata3 top PLL Ref Sel */
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY 0x004202d0 /* Sata3 top power switch memory */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE    0x004202d4 /* Sds afec top clock enable */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE 0x004202d8 /* Sds afec top memory standby enable */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK   0x004202dc /* Sds afec top observe clock */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY 0x004202e0 /* Sds afec top power switch memory */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE   0x004202e4 /* Disable SDS_RECEIVER's clocks */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE    0x004202e8 /* Sds receiver clock enable */
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE 0x004202ec /* Sds receiver memory standby enable */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK   0x004202f0 /* Sds receiver observe clock */
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY 0x004202f4 /* Sds receiver power switch memory */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE    0x004202f8 /* Sds tfec top clock enable */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE 0x004202fc /* Sds tfec top memory standby enable */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK   0x00420300 /* Sds tfec top observe clock */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY 0x00420304 /* Sds tfec top power switch memory */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE     0x00420308 /* Sectop inst clock enable */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE 0x0042030c /* Sectop inst memory standby enable */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK    0x00420310 /* Sectop inst observe clock */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT         0x00420314 /* Mux selects for Smartcard clocks */
+#define BCHP_CLKGEN_SPARE                        0x00420318 /* Spares */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK        0x0042031c /* Sys aon observe clock */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE       0x00420320 /* Disable SYS_CTRL's clocks */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE        0x00420324 /* Sys ctrl clock enable */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE 0x00420328 /* Sys ctrl memory standby enable */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK       0x0042032c /* Sys ctrl observe clock */
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY 0x00420330 /* Sys ctrl power switch memory */
+#define BCHP_CLKGEN_TESTPORT                     0x00420334 /* Special Testport Controls */
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE            0x00420338 /* Disable USB's clocks */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE             0x0042033c /* Usb clock enable */
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE    0x00420340 /* Usb memory standby enable */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK            0x00420344 /* Usb observe clock */
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY      0x00420348 /* Usb power switch memory */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE    0x0042034c /* Disable VEC_AIO_TOP's clocks */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE     0x00420350 /* Vec aio top clock enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A 0x00420354 /* Vec aio top memory standby enable a */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B 0x00420358 /* Vec aio top memory standby enable b */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK    0x0042035c /* Vec aio top observe clock */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A 0x00420360 /* Vec aio top power switch memory a */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B 0x00420364 /* Vec aio top power switch memory b */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 0x00420368 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT            0x0042036c /* spi clock control */
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT                0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000001
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT                0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000001
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000005
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000a
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_SHIFT         0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_reserved0_MASK            0xffffe000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_reserved0_SHIFT           13
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_MASK                 0x00001c00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_SHIFT                10
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_DEFAULT              0x00000003
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_MASK             0x000003ff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_SHIFT            0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_DEFAULT          0x000000a7
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_reserved0_MASK           0xff000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_reserved0_SHIFT          24
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK   0x000000e0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT  5
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT   2
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK    0x00000002
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT   1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_MASK         0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_reserved0_MASK           0x80000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_reserved0_SHIFT          31
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_MASK             0x60000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_SHIFT            29
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_MASK             0x10000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_SHIFT            28
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_MASK         0x08000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_SHIFT        27
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_MASK         0x07000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_SHIFT        24
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__MASK         0x00800000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__SHIFT        23
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_MASK           0x00600000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_SHIFT          21
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_MASK           0x00100000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_SHIFT          20
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_MASK            0x000c0000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_SHIFT           18
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_MASK          0x00020000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_SHIFT         17
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_MASK         0x00010000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT        16
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_MASK         0x00008000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT        15
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_MASK           0x00004000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_SHIFT          14
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK     0x00001ffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT    1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT  0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_SHIFT             0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_SHIFT         0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_reserved0_MASK         0xfffff000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_reserved0_SHIFT        12
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_TEST_STATUS_MASK       0x00000fff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_TEST_STATUS_SHIFT      0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT  0x00000028
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT  0x00000028
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT  0x00000032
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_MASK                  0xffffe000
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_SHIFT                 13
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_MASK                       0x00001c00
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_SHIFT                      10
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_DEFAULT                    0x00000001
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_MASK                   0x000003ff
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_DEFAULT                0x00000040
+
+/***************************************************************************
+ *PLL_SC_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_MASK                 0xff000000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_SHIFT                24
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK         0x000000e0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT        5
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT      0x00000001
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_SHIFT              0
+
+/***************************************************************************
+ *PLL_SC_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_MASK                 0xc0000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_SHIFT                30
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_MASK                   0x30000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_SHIFT                  28
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_DEFAULT                0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_MASK              0x08000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_SHIFT             27
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_MASK                   0x04000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_SHIFT                  26
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_DEFAULT                0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_MASK               0x02000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_SHIFT              25
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_MASK               0x01c00000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_SHIFT              22
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__MASK               0x00200000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__SHIFT              21
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_MASK                 0x00180000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_SHIFT                19
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_MASK                 0x00040000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_SHIFT                18
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_MASK                  0x00030000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_SHIFT                 16
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_MASK               0x00008000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_SHIFT              15
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_MASK                 0x00004000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_SHIFT                14
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK    0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT   13
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_MASK           0x00001ffe
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_SHIFT          1
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_SHIFT               1
+
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_SHIFT               2
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_MASK                   0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_SHIFT                  1
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_DEFAULT                0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_DEFAULT                0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK  0x00400000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_MASK               0xfffff000
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_SHIFT              12
+
+/* CLKGEN :: PLL_SC_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_MASK             0x00000fff
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000c
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000c
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000060
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000036
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT                  0x00000002
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT              0x00000060
+
+/***************************************************************************
+ *PLL_SYS0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000002
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000012
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000005a
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x0000005a
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_DEFAULT                  0x00000003
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_DEFAULT              0x0000007d
+
+/***************************************************************************
+ *PLL_SYS1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000001
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_MASK                 0x30000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_SHIFT           27
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_DEFAULT              0x00000001
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_MASK             0x02000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_SHIFT            25
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_MASK             0x01c00000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_SHIFT            22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__MASK             0x00200000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__SHIFT            21
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_SHIFT              19
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_MASK                0x00030000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_SHIFT               16
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_DEFAULT             0x00000002
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000004b
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000004b
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x000000fa
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_DEFAULT                  0x00000002
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_DEFAULT              0x00000040
+
+/***************************************************************************
+ *PLL_VCXO_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_MASK               0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_SHIFT              20
+
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_MASK            0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_SHIFT           0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000001
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_MASK                 0x30000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_SHIFT                28
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_SHIFT           27
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_MASK             0x02000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_SHIFT            25
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_MASK             0x01c00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_SHIFT            22
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__MASK             0x00200000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__SHIFT            21
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_SHIFT              19
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_MASK                0x00030000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_SHIFT               16
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_SHIFT            15
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *AVD0_TOP_CLOCK_ENABLE - Avd0 top clock enable
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_reserved0_MASK           0xffffffe0
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_reserved0_SHIFT          5
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_SCB_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_CPU_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_AVD_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_ALTERNATE_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *AVD0_TOP_MEMORY_STANDBY_ENABLE - Avd0 top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: AVD0_TOP_MEMORY_STANDBY_ENABLE :: SVD_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AVD0_TOP_OBSERVE_CLOCK - Avd0 top observe clock
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AVD0_TOP_POWER_SWITCH_MEMORY - Avd0 top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: AVD0_TOP_POWER_SWITCH_MEMORY :: SVD_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_CLOCK_DISABLE - Disable BCM_MIPS_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_DISABLE :: DISABLE_MIPS_SYSTEM_216_CLOCK [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_DISABLE_MIPS_SYSTEM_216_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_DISABLE_MIPS_SYSTEM_216_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_DISABLE_MIPS_SYSTEM_216_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_CLOCK_ENABLE - Bcm mips top clock enable
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffff0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_SHIFT      4
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_MIPS_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_MIPS_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_MIPS_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_MIPS_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE - Bcm mips top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: MIPS_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_OBSERVE_CLOCK - Bcm mips top observe clock
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_POWER_SWITCH_MEMORY - Bcm mips top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: MIPS_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_SELECT - Bcm mips top select
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_SELECT :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_reserved0_SHIFT            1
+
+/* CLKGEN :: BCM_MIPS_TOP_SELECT :: MIPS_PLL_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_MIPS_PLL_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_MIPS_PLL_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_MIPS_PLL_CLOCK_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BVN_TOP_ENABLE - Bvn top enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_reserved0_MASK                  0xfffffff8
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_reserved0_SHIFT                 3
+
+/* CLKGEN :: BVN_TOP_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK       0x00000004
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT      2
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT    0x00000001
+
+/* CLKGEN :: BVN_TOP_ENABLE :: BVN_216_CLK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_MASK         0x00000002
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_SHIFT        1
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_DEFAULT      0x00000001
+
+/* CLKGEN :: BVN_TOP_ENABLE :: BVN_108_CLK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_MASK         0x00000001
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_SHIFT        0
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_DEFAULT      0x00000001
+
+/***************************************************************************
+ *BVN_TOP_MEMORY_STANDBY_ENABLE - Bvn top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: BVN_TOP_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BVN_TOP_POWER_SWITCH_MEMORY - Bvn top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: BVN_TOP_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 0 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION [31:28] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 28
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 1 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:28] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 28
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SATA_108_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 2 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:16] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 16
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 216 0 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:28] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 28
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SATA_216_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK - CKTAP CPU Adjustment System 108 Clock
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: reserved0 [31:08] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_reserved0_MASK 0xffffff00
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_reserved0_SHIFT 8
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: CKTAP_WAIT_COUNT [07:02] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_WAIT_COUNT_MASK 0x000000fc
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_WAIT_COUNT_SHIFT 2
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_WAIT_COUNT_DEFAULT 0x0000000f
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: CKTAP_UPDATE [01:01] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_MASK 0x00000002
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_SHIFT 1
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: CKTAP_REG_SELECT [00:00] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK - CKTAP CPU Adjustment System 216 Clock
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: CKTAP_UPDATE [01:01] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_MASK 0x00000002
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_SHIFT 1
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: CKTAP_REG_SELECT [00:00] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK - CKTAP CPU Adjustment System Scb Clock
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: CKTAP_UPDATE [01:01] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_MASK 0x00000002
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_SHIFT 1
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: CKTAP_REG_SELECT [00:00] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap scb 0 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [31:28] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 28
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap scb 1 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:16] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 16
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SATA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks
+ ***************************************************************************/
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT           2
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_OSC_DIGITAL_CLOCK [01:01] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_AVS_CLOCK [00:00] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_MASK    0x00000001
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_SHIFT   0
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CLOCK_MONITOR_CONTROL - Clock Monitor Control
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT          4
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK   0x00000008
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT  3
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK    0x00000004
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT   2
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK      0x00000002
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT     1
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT   0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK  0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT         1
+
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK     0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT    0
+
+/***************************************************************************
+ *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CORE_XPT_CLOCK_DISABLE - Disable CORE_XPT's clocks
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_SHIFT         5
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_CLOCK_ENABLE - Core xpt clock enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_MASK           0xfffffff8
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_SHIFT          3
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CORE_XPT_MEMORY_STANDBY_ENABLE - Core xpt memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_OBSERVE_CLOCK - Core xpt observe clock
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_POWER_SWITCH_MEMORY - Core xpt power switch memory
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_CLOCK_DISABLE - Disable DVP_HT's clocks
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_SHIFT           1
+
+/* CLKGEN :: DVP_HT_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_CLOCK_ENABLE - Dvp ht clock enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_MASK             0xfffffff0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_SHIFT            4
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_ALTERNATE_216_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_ALTERNATE_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DVP_HT_ENABLE - Dvp ht enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_ENABLE_reserved0_SHIFT                  1
+
+/* CLKGEN :: DVP_HT_ENABLE :: DVPHT_CLK_MAX_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_MASK        0x00000001
+#define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_SHIFT       0
+#define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_DEFAULT     0x00000001
+
+/***************************************************************************
+ *DVP_HT_MEMORY_STANDBY_ENABLE - Dvp ht memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_MASK    0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT   1
+
+/* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_OBSERVE_CLOCK - Dvp ht observe clock
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_MASK            0xffffffc0
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_SHIFT           6
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_POWER_SWITCH_MEMORY - Dvp ht power switch memory
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_SHIFT     2
+
+/* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FSK_TOP_CLOCK_ENABLE - Fsk top clock enable
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_reserved0_MASK            0xfffffff8
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_reserved0_SHIFT           3
+
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: FSK_PHY_PRIMARY_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_PHY_PRIMARY_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_PHY_PRIMARY_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_PHY_PRIMARY_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: FSK_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: FSK_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *FSK_TOP_MEMORY_STANDBY_ENABLE - Fsk top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: FSK_TOP_MEMORY_STANDBY_ENABLE :: FSK_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_FSK_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_FSK_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_FSK_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FSK_TOP_POWER_SWITCH_MEMORY - Fsk top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: FSK_TOP_POWER_SWITCH_MEMORY :: FTM_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_CLOCK_DISABLE - Disable GENET_TOP_RGMII_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_SHIFT 4
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET_ALWAYSON_CLOCK [03:03] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [02:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [01:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_FAST_CLOCK [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_CLOCK_ENABLE - Genet top rgmii inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: reserved0 [31:09] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_SHIFT 9
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [08:08] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00000100
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 8
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_108_CLOCK_ENABLE [07:07] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_MASK 0x00000080
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_SHIFT 7
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_L2INTR_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_HFB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_GMII_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_EEE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_CLK_250_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_CLOCK_SELECT - Genet top rgmii inst clock select
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_reserved0_SHIFT 2
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET0_GMII_CLOCK_SELECT [01:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_MASK 0x00000002
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_SHIFT 1
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET0_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A - Genet top rgmii inst memory standby enable a
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: GENET0_MEMORY_STANDBY_ENABLE_A [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_OBSERVE_CLOCK - Genet top rgmii inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A - Genet top rgmii inst power switch memory a
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A :: GENET0_POWER_SWITCH_MEMORY_A [01:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_MASK 0x00000003
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_CLOCK_DISABLE - Disable GRAPHICS's clocks
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_reserved0_SHIFT         1
+
+/* CLKGEN :: GRAPHICS_CLOCK_DISABLE :: DISABLE_GFX_M2MC_CORE_CLOCK [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_CLOCK_ENABLE - Graphics clock enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_reserved0_SHIFT          4
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_M2MC_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_ALTERNATE_108_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GRAPHICS_MEMORY_STANDBY_ENABLE - Graphics memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE :: GFX_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_OBSERVE_CLOCK - Graphics observe clock
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_POWER_SWITCH_MEMORY - Graphics power switch memory
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY :: GFX_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_CLOCK_DISABLE - Disable HIF's clocks
+ ***************************************************************************/
+/* CLKGEN :: HIF_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_reserved0_MASK               0xfffffff0
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_reserved0_SHIFT              4
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_SDIO_48_CLOCK [03:03] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_MASK   0x00000008
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_SHIFT  3
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [02:02] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK   0x00000004
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT  2
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_EBI_CLOCK [01:01] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_MASK   0x00000002
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_SHIFT  1
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_54_SCANCLOCK [00:00] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_SHIFT 0
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_CLOCK_ENABLE - Hif clock enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_reserved0_SHIFT               3
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_MASK     0x00000004
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_SHIFT    2
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_DEFAULT  0x00000001
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_MASK     0x00000002
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_SHIFT    1
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_DEFAULT  0x00000001
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_MASK     0x00000001
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_SHIFT    0
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_DEFAULT  0x00000001
+
+/***************************************************************************
+ *HIF_MEMORY_STANDBY_ENABLE - Hif memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE :: HIF_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_POWER_SWITCH_MEMORY - Hif power switch memory
+ ***************************************************************************/
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_reserved0_SHIFT        2
+
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY :: HIF_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
+ ***************************************************************************/
+/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:04] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK             0xfffffff0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT            4
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: GFX_M2MC_USE_PROG_CLK [03:03] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_USE_PROG_CLK_MASK 0x00000008
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_USE_PROG_CLK_SHIFT 3
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_USE_PROG_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [02:02] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [01:01] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: GFX_M2MC_CORE_CLOCK [00:00] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_MASK   0x00000001
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_SHIFT  0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_16_CLOCK_ENABLE - Memsys 16 clock enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: DDR1_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: DDR1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *MEMSYS_16_MEMORY_STANDBY_ENABLE - Memsys 16 memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MEMSYS_16_MEMORY_STANDBY_ENABLE :: DDR1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_16_OBSERVE_CLOCK - Memsys 16 observe clock
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_16_POWER_SWITCH_MEMORY - Memsys 16 power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: MEMSYS_16_POWER_SWITCH_MEMORY :: DDR1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_16_STATUS - Memsys 16 status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_reserved0_SHIFT               1
+
+/* CLKGEN :: MEMSYS_16_STATUS :: MEMSYS_PLL_LOCKED_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_MEMSYS_PLL_LOCKED_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_MEMSYS_PLL_LOCKED_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PAD_CLK_OBSRV0_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLK_OBSRV1_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLK_OBSRV2_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLK_OBSRV3_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLOCK_DISABLE - Disable PAD's clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK               0xfffffff8
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT              3
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_SC_OUT_CLOCK [02:02] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_MASK    0x00000004
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_SHIFT   2
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_MUX_SELECT - Mux selects for Pad clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK                  0xfffffff8
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT                 3
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK27_CLOCK [02:00] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_MASK     0x00000007
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_SHIFT    0
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_DEFAULT  0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET_STATUS - PLL_AUDIO0 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET_STATUS - PLL_AUDIO1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET_STATUS - PLL_SC Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET_STATUS - PLL_SYS1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET_STATUS - PLL_VCXO Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PM_CLOCK_108_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_MASK          0xfffffff0
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_SHIFT         4
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSTFEC [03:03] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTFEC_MASK 0x00000008
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTFEC_SHIFT 3
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTFEC_DEFAULT 0x00000000
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSRCVR [02:02] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSRCVR_MASK 0x00000004
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSRCVR_SHIFT 2
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSRCVR_DEFAULT 0x00000000
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSAFEC [01:01] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC_MASK 0x00000002
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC_SHIFT 1
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC_DEFAULT 0x00000000
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_ [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG__MASK      0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG__SHIFT     0
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG__DEFAULT   0x00000000
+
+/***************************************************************************
+ *PM_CLOCK_216_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_SHIFT         1
+
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_MASK   0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT  0
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               3
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys_PLL [02:02] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_MASK               0x00000004
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_SHIFT              2
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_DEFAULT            0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [01:01] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK                 0x00000002
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT                1
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT              0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_AVD_MIPS [00:00] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_MASK             0x00000001
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_SHIFT            0
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_CLOCK_ENABLE - Raaga dsp top clock enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_reserved0_MASK      0xfffffff8
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_reserved0_SHIFT     3
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_DSP_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE - Raaga dsp top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE :: RAAGAA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_OBSERVE_CLOCK - Raaga dsp top observe clock
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_reserved0_SHIFT    2
+
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: RAAGA_ENABLE_OBSERVE_CLOCK [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_POWER_SWITCH_MEMORY - Raaga dsp top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_POWER_SWITCH_MEMORY :: RAAGA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RFM_TOP_CLOCK_ENABLE - Rfm top clock enable
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_reserved0_SHIFT           1
+
+/* CLKGEN :: RFM_TOP_CLOCK_ENABLE :: RFM_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RFM_TOP_MEMORY_STANDBY_ENABLE - Rfm top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: RFM_TOP_MEMORY_STANDBY_ENABLE :: RFMA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RFM_TOP_OBSERVE_CLOCK - Rfm top observe clock
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_reserved0_MASK           0xffffffc0
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_reserved0_SHIFT          6
+
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RFM_TOP_POWER_SWITCH_MEMORY - Rfm top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: RFM_TOP_POWER_SWITCH_MEMORY :: RFM_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_CLOCK_ENABLE - Sata3 top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: SATA_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: SATA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SATA3_TOP_CLOCK_DISABLE - Disable SATA3_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_reserved0_SHIFT        1
+
+/* CLKGEN :: SATA3_TOP_CLOCK_DISABLE :: DISABLE_SATA_FUNC_30_CLOCK [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_FUNC_30_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_FUNC_30_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_FUNC_30_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_MEMORY_STANDBY_ENABLE - Sata3 memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SATA3_TOP_MEMORY_STANDBY_ENABLE :: SATA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_OBSERVE_CLOCK - Sata3 top observe clock
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: SATA_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: SATA_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: SATA_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_PLLREF_SEL - Sata3 top PLL Ref Sel
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_PLLREF_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_reserved0_SHIFT           1
+
+/* CLKGEN :: SATA3_TOP_PLLREF_SEL :: SATA_TOP_PLLREF_SEL [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_SATA_TOP_PLLREF_SEL_MASK  0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_SATA_TOP_PLLREF_SEL_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_SATA_TOP_PLLREF_SEL_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SATA3_TOP_POWER_SWITCH_MEMORY - Sata3 top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: SATA3_TOP_POWER_SWITCH_MEMORY :: SATA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_AFEC_TOP_CLOCK_ENABLE - Sds afec top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: SDS_AFEC_TOP_CLOCK_ENABLE :: SDSAFEC0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE - Sds afec top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE :: SDSAFEC0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_AFEC_TOP_OBSERVE_CLOCK - Sds afec top observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: SDSAFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_AFEC_TOP_POWER_SWITCH_MEMORY - Sds afec top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS_AFEC_TOP_POWER_SWITCH_MEMORY :: SDSAFEC0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_RECEIVER_CLOCK_DISABLE - Disable SDS_RECEIVER's clocks
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: SDS_RECEIVER_CLOCK_DISABLE :: DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK [00:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_RECEIVER_CLOCK_ENABLE - Sds receiver clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: SDS_RECEIVER_CLOCK_ENABLE :: SDSRCVR0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_SDSRCVR0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_SDSRCVR0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_SDSRCVR0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SDS_RECEIVER_MEMORY_STANDBY_ENABLE - Sds receiver memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS_RECEIVER_MEMORY_STANDBY_ENABLE :: SDSRCVR0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_SDSRCVR0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_SDSRCVR0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_SDSRCVR0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_RECEIVER_OBSERVE_CLOCK - Sds receiver observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: SDSRCVR0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: SDSRCVR0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_RECEIVER_POWER_SWITCH_MEMORY - Sds receiver power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS_RECEIVER_POWER_SWITCH_MEMORY :: SDSRCVR0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_SDSRCVR0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_SDSRCVR0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_SDSRCVR0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_TFEC_TOP_CLOCK_ENABLE - Sds tfec top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: SDS_TFEC_TOP_CLOCK_ENABLE :: SDSTFEC0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_SDSTFEC0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_SDSTFEC0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_SDSTFEC0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE - Sds tfec top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE :: SDS_TFEC0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_SDS_TFEC0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_SDS_TFEC0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_SDS_TFEC0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_TFEC_TOP_OBSERVE_CLOCK - Sds tfec top observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: SDS_TFEC0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: SDS_TFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_TFEC_TOP_POWER_SWITCH_MEMORY - Sds tfec top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS_TFEC_TOP_POWER_SWITCH_MEMORY :: SDS_TFEC0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_SDS_TFEC0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_SDS_TFEC0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_SDS_TFEC0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SECTOP_INST_CLOCK_ENABLE - Sectop inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_SHIFT       1
+
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: SEC_ALTERNATE_SCB_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SECTOP_INST_MEMORY_STANDBY_ENABLE - Sectop inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SECTOP_INST_MEMORY_STANDBY_ENABLE :: SEC_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
+ ***************************************************************************/
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:11] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK            0xfffff800
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT           11
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC_OUT_CLOCK [10:08] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_MASK         0x00000700
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_SHIFT        8
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_DEFAULT      0x00000000
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [07:05] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK            0x000000e0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT           5
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [04:02] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK            0x0000001c
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT           2
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: PLLSC_REFERENCE_CLOCK [01:00] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_MASK 0x00000003
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE - Spares
+ ***************************************************************************/
+/* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK                     0xfffff000
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT                    12
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT                  0x00000000
+
+/* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK                    0x00000fff
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT                   0
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *SYS_AON_OBSERVE_CLOCK - Sys aon observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_MASK           0xffffffc0
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_SHIFT          6
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_CLOCK_DISABLE - Disable SYS_CTRL's clocks
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_SHIFT         5
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK [03:03] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK [02:02] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK_SHIFT 2
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK  0x00000002
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK  0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_CLOCK_ENABLE - Sys ctrl clock enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_SHIFT          1
+
+/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: SYS_CTRL_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SYS_CTRL_MEMORY_STANDBY_ENABLE - Sys ctrl memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_OBSERVE_CLOCK - Sys ctrl observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_POWER_SWITCH_MEMORY - Sys ctrl power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: SYS_CTRL_POWER_SWITCH_MEMORY :: SYS_CTRL_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TESTPORT - Special Testport Controls
+ ***************************************************************************/
+/* CLKGEN :: TESTPORT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_TESTPORT_reserved0_MASK                        0xfffffff8
+#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT                       3
+
+/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [02:00] */
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK           0x00000007
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT          0
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *USB_CLOCK_DISABLE - Disable USB's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_reserved0_SHIFT              1
+
+/* CLKGEN :: USB_CLOCK_DISABLE :: DISABLE_USB_54_MDIO_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB_CLOCK_ENABLE - Usb clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_reserved0_SHIFT               2
+
+/* CLKGEN :: USB_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK    0x00000002
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT   1
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: USB_CLOCK_ENABLE :: USB0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK    0x00000001
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT   0
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *USB_MEMORY_STANDBY_ENABLE - Usb memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: USB_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB_OBSERVE_CLOCK - Usb observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_reserved0_MASK               0xffffffc0
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_reserved0_SHIFT              6
+
+/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB_POWER_SWITCH_MEMORY - Usb power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_reserved0_SHIFT        2
+
+/* CLKGEN :: USB_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_CLOCK_DISABLE - Disable VEC_AIO_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_CLOCK_ENABLE - Vec aio top clock enable
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: reserved0 [31:07] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_reserved0_MASK        0xffffff80
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_reserved0_SHIFT       7
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_SCB_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_SCB_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_216_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_108_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE2_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A - Vec aio top memory standby enable a
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A :: VEC_MEMORY_STANDBY_ENABLE_A [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B - Vec aio top memory standby enable b
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B :: AIO_MEMORY_STANDBY_ENABLE_B [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_OBSERVE_CLOCK - Vec aio top observe clock
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_POWER_SWITCH_MEMORY_A - Vec aio top power switch memory a
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_A :: VEC_POWER_SWITCH_MEMORY_A [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_POWER_SWITCH_MEMORY_B - Vec aio top power switch memory b
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_B :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_B :: AIO_POWER_SWITCH_MEMORY_B [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BSPI_CLOCK_SELECT - spi clock control
+ ***************************************************************************/
+/* CLKGEN :: BSPI_CLOCK_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_MASK               0xfffffff8
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_SHIFT              3
+
+/* CLKGEN :: BSPI_CLOCK_SELECT :: SPI_CLOCK_FREQ_SEL [02:01] */
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_MASK      0x00000006
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_SHIFT     1
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_DEFAULT   0x00000000
+
+/* CLKGEN :: BSPI_CLOCK_SELECT :: SPI_CLOCK_OVERRIDE_STRAP [00:00] */
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_MASK 0x00000001
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_SHIFT 0
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_CLKGEN_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_common.h b/include/linux/brcmstb/7362a0/bchp_common.h
new file mode 100644
index 0000000..5dbe6e9
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_common.h
@@ -0,0 +1,1986 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 24 17:25:33 2013
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_COMMON_H__
+#define BCHP_COMMON_H__
+
+/**
+ * m = memory, c = core, r = register, f = field, d = data.
+ */
+#if !defined(GET_FIELD) && !defined(SET_FIELD)
+#define BRCM_MASK(c,r,f)    c##_##r##_##f##_MASK
+#define BRCM_SHIFT(c,r,f)   c##_##r##_##f##_SHIFT
+
+#define GET_FIELD(m,c,r,f) \
+((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)))
+
+#define SET_FIELD(m,c,r,f,d) \
+((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d)) << BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))))
+
+#define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d)
+#define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d)
+#define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d)
+
+#endif /* GET & SET */
+
+/***************************************************************************
+ *BCM7362_A0
+ ***************************************************************************/
+#define BCHP_PHYSICAL_OFFSET                               0x10000000
+#define BCHP_REGISTER_START                                0x00000000 /* DECODE_RBNODE_REGS_0 is first */
+#define BCHP_REGISTER_END                                  0x00b01010 /* RFM_GRB is last */
+#define BCHP_REGISTER_SIZE                                 0x002c0404 /* Number of registers */
+
+/****************************************************************************
+ * Core instance register start address.
+ ***************************************************************************/
+#define BCHP_DECODE_RBNODE_REGS_0_REG_START                0x00000000
+#define BCHP_DECODE_RBNODE_REGS_0_REG_END                  0x0000007c
+#define BCHP_DECODE_MAIN_0_REG_START                       0x00000100
+#define BCHP_DECODE_MAIN_0_REG_END                         0x000001fc
+#define BCHP_SDRAM_DEBUG_0_REG_START                       0x00000200
+#define BCHP_SDRAM_DEBUG_0_REG_END                         0x0000027c
+#define BCHP_DECODE_MCOM_0_REG_START                       0x00000300
+#define BCHP_DECODE_MCOM_0_REG_END                         0x0000031c
+#define BCHP_DECODE_SPRE_0_REG_START                       0x00000320
+#define BCHP_DECODE_SPRE_0_REG_END                         0x0000033c
+#define BCHP_DECODE_WPRD_0_REG_START                       0x00000340
+#define BCHP_DECODE_WPRD_0_REG_END                         0x0000035c
+#define BCHP_DECODE_DQNT_0_REG_START                       0x00000400
+#define BCHP_DECODE_DQNT_0_REG_END                         0x0000045c
+#define BCHP_DECODE_DQNT_8X8_0_REG_START                   0x00000500
+#define BCHP_DECODE_DQNT_8X8_0_REG_END                     0x0000057c
+#define BCHP_DECODE_VP8_XFRM_0_REG_START                   0x00000600
+#define BCHP_DECODE_VP8_XFRM_0_REG_END                     0x0000060c
+#define BCHP_DECODE_XFRM_0_REG_START                       0x00000700
+#define BCHP_DECODE_XFRM_0_REG_END                         0x0000071c
+#define BCHP_DECODE_DBLK_0_REG_START                       0x00000720
+#define BCHP_DECODE_DBLK_0_REG_END                         0x0000073c
+#define BCHP_DECODE_MB_0_REG_START                         0x00000740
+#define BCHP_DECODE_MB_0_REG_END                           0x0000075c
+#define BCHP_REG_CABAC2BINS_0_REG_START                    0x00000b00
+#define BCHP_REG_CABAC2BINS_0_REG_END                      0x00000bfc
+#define BCHP_DECODE_SINT_0_REG_START                       0x00000c00
+#define BCHP_DECODE_SINT_0_REG_END                         0x00000dfc
+#define BCHP_DECODE_RVC_0_REG_START                        0x00000e00
+#define BCHP_DECODE_RVC_0_REG_END                          0x00000efc
+#define BCHP_DECODE_CPUREGS_0_REG_START                    0x00000f00
+#define BCHP_DECODE_CPUREGS_0_REG_END                      0x00000f7c
+#define BCHP_DECODE_CPUREGS2_0_REG_START                   0x00000f80
+#define BCHP_DECODE_CPUREGS2_0_REG_END                     0x00000ffc
+#define BCHP_DECODE_CPUDMA_0_REG_START                     0x00001800
+#define BCHP_DECODE_CPUDMA_0_REG_END                       0x000018fc
+#define BCHP_DECODE_DMAMEM_0_REG_START                     0x00001a00
+#define BCHP_DECODE_DMAMEM_0_REG_END                       0x000021fc
+#define BCHP_REG_CABAC2BINS2_0_REG_START                   0x00002400
+#define BCHP_REG_CABAC2BINS2_0_REG_END                     0x000027fc
+#define BCHP_DECODE_WPTBL_0_REG_START                      0x00003000
+#define BCHP_DECODE_WPTBL_0_REG_END                        0x000031fc
+#define BCHP_DECODE_SINT_OLOOP_0_REG_START                 0x0000cc00
+#define BCHP_DECODE_SINT_OLOOP_0_REG_END                   0x0000ccfc
+#define BCHP_DECODE_SD_0_REG_START                         0x00040800
+#define BCHP_DECODE_SD_0_REG_END                           0x00040ffc
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_START             0x00041000
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_END               0x0004107c
+#define BCHP_DECODE_CPUCORE_0_REG_START                    0x00044000
+#define BCHP_DECODE_CPUCORE_0_REG_END                      0x00044ffc
+#define BCHP_DECODE_CPUAUX_0_REG_START                     0x00045000
+#define BCHP_DECODE_CPUAUX_0_REG_END                       0x00045ffc
+#define BCHP_DECODE_CPUIMEM_0_REG_START                    0x00046000
+#define BCHP_DECODE_CPUIMEM_0_REG_END                      0x00047ffc
+#define BCHP_DECODE_CPUDMEM_0_REG_START                    0x00048000
+#define BCHP_DECODE_CPUDMEM_0_REG_END                      0x0004fffc
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_START            0x00051000
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_END              0x0005107c
+#define BCHP_DECODE_CPUDMA2_0_REG_START                    0x00051800
+#define BCHP_DECODE_CPUDMA2_0_REG_END                      0x000518fc
+#define BCHP_DECODE_DMAMEM2_0_REG_START                    0x00051a00
+#define BCHP_DECODE_DMAMEM2_0_REG_END                      0x000521fc
+#define BCHP_DECODE_CPUCORE2_0_REG_START                   0x00054000
+#define BCHP_DECODE_CPUCORE2_0_REG_END                     0x00054ffc
+#define BCHP_DECODE_CPUAUX2_0_REG_START                    0x00055000
+#define BCHP_DECODE_CPUAUX2_0_REG_END                      0x00055ffc
+#define BCHP_DECODE_CPUIMEM2_0_REG_START                   0x00056000
+#define BCHP_DECODE_CPUIMEM2_0_REG_END                     0x00057ffc
+#define BCHP_DECODE_CPUDMEM2_0_REG_START                   0x00058000
+#define BCHP_DECODE_CPUDMEM2_0_REG_END                     0x0005fffc
+#define BCHP_DECODE_IP_SHIM_0_REG_START                    0x00060000
+#define BCHP_DECODE_IP_SHIM_0_REG_END                      0x00060084
+#define BCHP_AVD_CACHE_0_REG_START                         0x00062000
+#define BCHP_AVD_CACHE_0_REG_END                           0x0006203c
+#define BCHP_AVD_INTR2_0_REG_START                         0x00080000
+#define BCHP_AVD_INTR2_0_REG_END                           0x0008002c
+#define BCHP_AVD_RGR_0_REG_START                           0x00080400
+#define BCHP_AVD_RGR_0_REG_END                             0x00080410
+#define BCHP_VICH_0_REG_START                              0x00170000
+#define BCHP_VICH_0_REG_END                                0x0017008b
+#define BCHP_SATA_GRB_REG_START                            0x00180000
+#define BCHP_SATA_GRB_REG_END                              0x0018000c
+#define BCHP_SATA_TOP_CTRL_REG_START                       0x00180020
+#define BCHP_SATA_TOP_CTRL_REG_END                         0x00180038
+#define BCHP_SATA3_INTR2_REG_START                         0x00180080
+#define BCHP_SATA3_INTR2_REG_END                           0x001800ac
+#define BCHP_SATA_AHCI_GHC_REG_START                       0x00181000
+#define BCHP_SATA_AHCI_GHC_REG_END                         0x00181028
+#define BCHP_SATA_GLOBAL_RESERVED_REG_START                0x0018102c
+#define BCHP_SATA_GLOBAL_RESERVED_REG_END                  0x0018109c
+#define BCHP_SATA_PORT0_AHCI_S1_REG_START                  0x00181100
+#define BCHP_SATA_PORT0_AHCI_S1_REG_END                    0x0018111c
+#define BCHP_SATA_PORT0_AHCI_S2_REG_START                  0x00181120
+#define BCHP_SATA_PORT0_AHCI_S2_REG_END                    0x00181134
+#define BCHP_SATA_PORT0_AHCI_S3_REG_START                  0x00181138
+#define BCHP_SATA_PORT0_AHCI_S3_REG_END                    0x0018117c
+#define BCHP_SATA_PORT1_AHCI_S1_REG_START                  0x00181180
+#define BCHP_SATA_PORT1_AHCI_S1_REG_END                    0x0018119c
+#define BCHP_SATA_PORT1_AHCI_S2_REG_START                  0x001811a0
+#define BCHP_SATA_PORT1_AHCI_S2_REG_END                    0x001811b4
+#define BCHP_SATA_PORT1_AHCI_S3_REG_START                  0x001811b8
+#define BCHP_SATA_PORT1_AHCI_S3_REG_END                    0x001811fc
+#define BCHP_SATA_AHCI_PCICFG_REG_START                    0x00181600
+#define BCHP_SATA_AHCI_PCICFG_REG_END                      0x00181664
+#define BCHP_SATA_PORT0_CTRL_REG_START                     0x00181700
+#define BCHP_SATA_PORT0_CTRL_REG_END                       0x00181730
+#define BCHP_SATA_PORT0_CJPAT_REG_START                    0x00181740
+#define BCHP_SATA_PORT0_CJPAT_REG_END                      0x00181764
+#define BCHP_SATA_PORT1_CTRL_REG_START                     0x00181780
+#define BCHP_SATA_PORT1_CTRL_REG_END                       0x001817b0
+#define BCHP_SATA_PORT1_CJPAT_REG_START                    0x001817c0
+#define BCHP_SATA_PORT1_CJPAT_REG_END                      0x001817e4
+#define BCHP_SATA_LEG_PCICFG_REG_START                     0x00181800
+#define BCHP_SATA_LEG_PCICFG_REG_END                       0x00181880
+#define BCHP_SATA_PORT0_LEG_S1_REG_START                   0x00181900
+#define BCHP_SATA_PORT0_LEG_S1_REG_END                     0x00181934
+#define BCHP_SATA_PORT0_LEG_S2_REG_START                   0x00181940
+#define BCHP_SATA_PORT0_LEG_S2_REG_END                     0x00181954
+#define BCHP_SATA_PORT0_LEG_S3_REG_START                   0x00181958
+#define BCHP_SATA_PORT0_LEG_S3_REG_END                     0x00181998
+#define BCHP_SATA_PORT1_LEG_S1_REG_START                   0x00181a00
+#define BCHP_SATA_PORT1_LEG_S1_REG_END                     0x00181a34
+#define BCHP_SATA_PORT1_LEG_S2_REG_START                   0x00181a40
+#define BCHP_SATA_PORT1_LEG_S2_REG_END                     0x00181a54
+#define BCHP_SATA_PORT1_LEG_S3_REG_START                   0x00181a58
+#define BCHP_SATA_PORT1_LEG_S3_REG_END                     0x00181a98
+#define BCHP_BESTROM_REG_START                             0x00200000
+#define BCHP_BESTROM_REG_END                               0x00203ffc
+#define BCHP_BSP_CMDBUF_REG_START                          0x00329800
+#define BCHP_BSP_CMDBUF_REG_END                            0x00329ffc
+#define BCHP_BSP_GLB_CONTROL_REG_START                     0x0032b000
+#define BCHP_BSP_GLB_CONTROL_REG_END                       0x0032b098
+#define BCHP_BSP_PKL_REG_START                             0x0032b300
+#define BCHP_BSP_PKL_REG_END                               0x0032b37c
+#define BCHP_BSP_INST_PATCH_CTRL_REG_START                 0x0032b400
+#define BCHP_BSP_INST_PATCH_CTRL_REG_END                   0x0032b404
+#define BCHP_BSP_CONTROL_INTR2_REG_START                   0x0032b800
+#define BCHP_BSP_CONTROL_INTR2_REG_END                     0x0032b82c
+#define BCHP_BSP_INST_PATCHRAM_REG_START                   0x0032c000
+#define BCHP_BSP_INST_PATCHRAM_REG_END                     0x0032fffc
+#define BCHP_XPT_SECURITY_REG_START                        0x00360000
+#define BCHP_XPT_SECURITY_REG_END                          0x0036fffc
+#define BCHP_MMSCRAM_REG_START                             0x00370000
+#define BCHP_MMSCRAM_REG_END                               0x00371ffc
+#define BCHP_MEM_DMA_SECURE_REG_START                      0x00372000
+#define BCHP_MEM_DMA_SECURE_REG_END                        0x0037200c
+#define BCHP_SECTOP_GRB_REG_START                          0x00374000
+#define BCHP_SECTOP_GRB_REG_END                            0x0037400c
+#define BCHP_JTAG_OTP_REG_START                            0x00374100
+#define BCHP_JTAG_OTP_REG_END                              0x00374138
+#define BCHP_MEM_DMA_0_REG_START                           0x00374200
+#define BCHP_MEM_DMA_0_REG_END                             0x00374224
+#define BCHP_XPT_SECURITY_NS_REG_START                     0x00374300
+#define BCHP_XPT_SECURITY_NS_REG_END                       0x00374310
+#define BCHP_MEMC_GEN_0_REG_START                          0x003b0000
+#define BCHP_MEMC_GEN_0_REG_END                            0x003b04f8
+#define BCHP_MEMC_GEN_2_0_REG_START                        0x003b0600
+#define BCHP_MEMC_GEN_2_0_REG_END                          0x003b06ec
+#define BCHP_MEMC_ARB_0_REG_START                          0x003b1000
+#define BCHP_MEMC_ARB_0_REG_END                            0x003b1244
+#define BCHP_MEMC_DDR_0_REG_START                          0x003b2000
+#define BCHP_MEMC_DDR_0_REG_END                            0x003b22fc
+#define BCHP_MEMC_L2_0_REG_START                           0x003b3000
+#define BCHP_MEMC_L2_0_REG_END                             0x003b302c
+#define BCHP_MEMC_L2_1_0_REG_START                         0x003b3800
+#define BCHP_MEMC_L2_1_0_REG_END                           0x003b382c
+#define BCHP_MEMC_RGRB_0_REG_START                         0x003b4000
+#define BCHP_MEMC_RGRB_0_REG_END                           0x003b4010
+#define BCHP_MEMC_MISC_0_REG_START                         0x003b5000
+#define BCHP_MEMC_MISC_0_REG_END                           0x003b5010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_START            0x003b6000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_END              0x003b60c4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_START             0x003b6200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_END               0x003b63b0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_START         0x003b8000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_END           0x003b8138
+#define BCHP_S_MEMC_0_REG_START                            0x003ba000
+#define BCHP_S_MEMC_0_REG_END                              0x003ba220
+#define BCHP_SUN_GISB_ARB_REG_START                        0x00400000
+#define BCHP_SUN_GISB_ARB_REG_END                          0x004000d8
+#define BCHP_SUN_RGR_REG_START                             0x00400400
+#define BCHP_SUN_RGR_REG_END                               0x00400410
+#define BCHP_SUN_RG_REG_START                              0x00400800
+#define BCHP_SUN_RG_REG_END                                0x0040080c
+#define BCHP_SUN_L2_REG_START                              0x00403000
+#define BCHP_SUN_L2_REG_END                                0x0040302c
+#define BCHP_SM_L2_REG_START                               0x00403400
+#define BCHP_SM_L2_REG_END                                 0x0040342c
+#define BCHP_SM_REG_START                                  0x00403800
+#define BCHP_SM_REG_END                                    0x00403824
+#define BCHP_SM_FAST_REG_START                             0x00403c00
+#define BCHP_SM_FAST_REG_END                               0x00403c18
+#define BCHP_SUN_TOP_CTRL_REG_START                        0x00404000
+#define BCHP_SUN_TOP_CTRL_REG_END                          0x00404518
+#define BCHP_IRB_REG_START                                 0x00406000
+#define BCHP_IRB_REG_END                                   0x00406138
+#define BCHP_PM_REG_START                                  0x00406180
+#define BCHP_PM_REG_END                                    0x00406188
+#define BCHP_BSCA_REG_START                                0x00406200
+#define BCHP_BSCA_REG_END                                  0x00406254
+#define BCHP_BSCB_REG_START                                0x00406280
+#define BCHP_BSCB_REG_END                                  0x004062d4
+#define BCHP_PWM_REG_START                                 0x00406400
+#define BCHP_PWM_REG_END                                   0x00406424
+#define BCHP_GIO_REG_START                                 0x00406500
+#define BCHP_GIO_REG_END                                   0x0040659c
+#define BCHP_IRQ0_REG_START                                0x00406600
+#define BCHP_IRQ0_REG_END                                  0x00406604
+#define BCHP_IRQ1_REG_START                                0x00406640
+#define BCHP_IRQ1_REG_END                                  0x00406644
+#define BCHP_TIMER_REG_START                               0x00406680
+#define BCHP_TIMER_REG_END                                 0x004066bc
+#define BCHP_UARTA_REG_START                               0x00406800
+#define BCHP_UARTA_REG_END                                 0x0040681c
+#define BCHP_UARTB_REG_START                               0x00406840
+#define BCHP_UARTB_REG_END                                 0x0040685c
+#define BCHP_UARTC_REG_START                               0x00406880
+#define BCHP_UARTC_REG_END                                 0x0040689c
+#define BCHP_SCA_REG_START                                 0x00406a00
+#define BCHP_SCA_REG_END                                   0x00406abc
+#define BCHP_SCB_REG_START                                 0x00406b00
+#define BCHP_SCB_REG_END                                   0x00406bbc
+#define BCHP_SCIRQ0_REG_START                              0x00406c00
+#define BCHP_SCIRQ0_REG_END                                0x00406c04
+#define BCHP_SCIRQ1_REG_START                              0x00406c80
+#define BCHP_SCIRQ1_REG_END                                0x00406c84
+#define BCHP_AON_CTRL_REG_START                            0x00408000
+#define BCHP_AON_CTRL_REG_END                              0x004083fc
+#define BCHP_AON_L2_REG_START                              0x00408400
+#define BCHP_AON_L2_REG_END                                0x0040842c
+#define BCHP_AON_PM_L2_REG_START                           0x00408440
+#define BCHP_AON_PM_L2_REG_END                             0x0040846c
+#define BCHP_AON_PIN_CTRL_REG_START                        0x00408500
+#define BCHP_AON_PIN_CTRL_REG_END                          0x0040851c
+#define BCHP_AON_HDMI_TX_REG_START                         0x00408600
+#define BCHP_AON_HDMI_TX_REG_END                           0x00408698
+#define BCHP_LDK_REG_START                                 0x00408800
+#define BCHP_LDK_REG_END                                   0x0040883c
+#define BCHP_PM_AON_REG_START                              0x00408840
+#define BCHP_PM_AON_REG_END                                0x00408848
+#define BCHP_ICAP_REG_START                                0x00408880
+#define BCHP_ICAP_REG_END                                  0x004088bc
+#define BCHP_KBD1_REG_START                                0x004088c0
+#define BCHP_KBD1_REG_END                                  0x004088fc
+#define BCHP_KBD2_REG_START                                0x00408900
+#define BCHP_KBD2_REG_END                                  0x0040893c
+#define BCHP_BSCD_REG_START                                0x00408980
+#define BCHP_BSCD_REG_END                                  0x004089d4
+#define BCHP_MSPI_REG_START                                0x00408a00
+#define BCHP_MSPI_REG_END                                  0x00408b7c
+#define BCHP_IRQ0_AON_REG_START                            0x00408b80
+#define BCHP_IRQ0_AON_REG_END                              0x00408b84
+#define BCHP_IRQ1_AON_REG_START                            0x00408b88
+#define BCHP_IRQ1_AON_REG_END                              0x00408b8c
+#define BCHP_GIO_AON_REG_START                             0x00408c00
+#define BCHP_GIO_AON_REG_END                               0x00408c5c
+#define BCHP_BICAP_REG_START                               0x00408e00
+#define BCHP_BICAP_REG_END                                 0x00408e38
+#define BCHP_UPG_AUX_AON_INTR2_REG_START                   0x00408e40
+#define BCHP_UPG_AUX_AON_INTR2_REG_END                     0x00408e6c
+#define BCHP_WKTMR_REG_START                               0x00408e80
+#define BCHP_WKTMR_REG_END                                 0x00408e90
+#define BCHP_SYS_GISB_ARB_SEC_REG_START                    0x0040e000
+#define BCHP_SYS_GISB_ARB_SEC_REG_END                      0x0040e0b4
+#define BCHP_SYS_TOP_CTRL_SEC_REG_START                    0x0040e700
+#define BCHP_SYS_TOP_CTRL_SEC_REG_END                      0x0040e704
+#define BCHP_AON_CTRL_SECURE_REG_START                     0x0040e800
+#define BCHP_AON_CTRL_SECURE_REG_END                       0x0040e87c
+#define BCHP_SDIO_0_HOST_REG_START                         0x00410000
+#define BCHP_SDIO_0_HOST_REG_END                           0x004100fc
+#define BCHP_SDIO_0_CFG_REG_START                          0x00410100
+#define BCHP_SDIO_0_CFG_REG_END                            0x004101fc
+#define BCHP_MISB_BRIDGE_REG_START                         0x00410400
+#define BCHP_MISB_BRIDGE_REG_END                           0x00410408
+#define BCHP_EBI_REG_START                                 0x00410800
+#define BCHP_EBI_REG_END                                   0x00410bfc
+#define BCHP_HIF_INTR2_REG_START                           0x00411000
+#define BCHP_HIF_INTR2_REG_END                             0x0041102c
+#define BCHP_IPI0_INTR2_REG_START                          0x00411100
+#define BCHP_IPI0_INTR2_REG_END                            0x0041112c
+#define BCHP_IPI1_INTR2_REG_START                          0x00411200
+#define BCHP_IPI1_INTR2_REG_END                            0x0041122c
+#define BCHP_HIF_CPU_INTR1_REG_START                       0x00411400
+#define BCHP_HIF_CPU_INTR1_REG_END                         0x0041142c
+#define BCHP_HIF_CPU_TP1_INTR1_REG_START                   0x00411600
+#define BCHP_HIF_CPU_TP1_INTR1_REG_END                     0x0041162c
+#define BCHP_HIF_RGR_REG_START                             0x00411800
+#define BCHP_HIF_RGR_REG_END                               0x00411810
+#define BCHP_HIF_SPI_INTR2_REG_START                       0x00411d00
+#define BCHP_HIF_SPI_INTR2_REG_END                         0x00411d2c
+#define BCHP_HIF_TOP_CTRL_REG_START                        0x00412400
+#define BCHP_HIF_TOP_CTRL_REG_END                          0x0041241c
+#define BCHP_NAND_REG_START                                0x00412800
+#define BCHP_NAND_REG_END                                  0x00412bfc
+#define BCHP_BSPI_REG_START                                0x00413000
+#define BCHP_BSPI_REG_END                                  0x0041304c
+#define BCHP_BSPI_RAF_REG_START                            0x00413100
+#define BCHP_BSPI_RAF_REG_END                              0x00413120
+#define BCHP_HIF_MSPI_REG_START                            0x00413200
+#define BCHP_HIF_MSPI_REG_END                              0x00413384
+#define BCHP_MICH_REG_START                                0x00414000
+#define BCHP_MICH_REG_END                                  0x00414000
+#define BCHP_HIF_SECURE_CTRL_REG_START                     0x00414100
+#define BCHP_HIF_SECURE_CTRL_REG_END                       0x00414100
+#define BCHP_HIF_SECURE_BSPI_REG_START                     0x00414200
+#define BCHP_HIF_SECURE_BSPI_REG_END                       0x00414200
+#define BCHP_HIF_SECURE_LR_SPI_REG_START                   0x00414300
+#define BCHP_HIF_SECURE_LR_SPI_REG_END                     0x00414300
+#define BCHP_NAND_SECURE_REG_START                         0x00414400
+#define BCHP_NAND_SECURE_REG_END                           0x00414400
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_START        0x00414800
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_END          0x00414800
+#define BCHP_CLKGEN_REG_START                              0x00420000
+#define BCHP_CLKGEN_REG_END                                0x0042036c
+#define BCHP_VCXO_RM_REG_START                             0x00422800
+#define BCHP_VCXO_RM_REG_END                               0x0042282c
+#define BCHP_AVS_HW_MNTR_REG_START                         0x00423000
+#define BCHP_AVS_HW_MNTR_REG_END                           0x00423074
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_START                 0x00423100
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_END                   0x0042311c
+#define BCHP_AVS_ASB_REGISTERS_REG_START                   0x00423200
+#define BCHP_AVS_ASB_REGISTERS_REG_END                     0x00423218
+#define BCHP_AVS_RO_REGISTERS_0_REG_START                  0x00423300
+#define BCHP_AVS_RO_REGISTERS_0_REG_END                    0x004233dc
+#define BCHP_AVS_RO_REGISTERS_1_REG_START                  0x00423400
+#define BCHP_AVS_RO_REGISTERS_1_REG_END                    0x0042349c
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_START                0x00423500
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_END                  0x004235e4
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_START                0x00423600
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_END                  0x004236e4
+#define BCHP_CLKGEN_INTR2_REG_START                        0x00424000
+#define BCHP_CLKGEN_INTR2_REG_END                          0x0042402c
+#define BCHP_CLKGEN_GR_REG_START                           0x00424800
+#define BCHP_CLKGEN_GR_REG_END                             0x0042480c
+#define BCHP_GENET_0_SYS_REG_START                         0x00430000
+#define BCHP_GENET_0_SYS_REG_END                           0x0043000c
+#define BCHP_GENET_0_GR_BRIDGE_REG_START                   0x00430040
+#define BCHP_GENET_0_GR_BRIDGE_REG_END                     0x0043004c
+#define BCHP_GENET_0_EXT_REG_START                         0x00430080
+#define BCHP_GENET_0_EXT_REG_END                           0x00430098
+#define BCHP_GENET_0_INTRL2_0_REG_START                    0x00430200
+#define BCHP_GENET_0_INTRL2_0_REG_END                      0x0043022c
+#define BCHP_GENET_0_INTRL2_1_REG_START                    0x00430240
+#define BCHP_GENET_0_INTRL2_1_REG_END                      0x0043026c
+#define BCHP_GENET_0_RBUF_REG_START                        0x00430300
+#define BCHP_GENET_0_RBUF_REG_END                          0x004303ec
+#define BCHP_GENET_0_TBUF_REG_START                        0x00430600
+#define BCHP_GENET_0_TBUF_REG_END                          0x00430628
+#define BCHP_GENET_0_UMAC_REG_START                        0x00430800
+#define BCHP_GENET_0_UMAC_REG_END                          0x00430ed8
+#define BCHP_GENET_0_HFB_REG_START                         0x00431000
+#define BCHP_GENET_0_HFB_REG_END                           0x00432010
+#define BCHP_GENET_0_RDMA_REG_START                        0x00433000
+#define BCHP_GENET_0_RDMA_REG_END                          0x00433cb4
+#define BCHP_GENET_0_TDMA_REG_START                        0x00434000
+#define BCHP_GENET_0_TDMA_REG_END                          0x00434c88
+#define BCHP_M2MC_REG_START                                0x00450000
+#define BCHP_M2MC_REG_END                                  0x004507fc
+#define BCHP_M2MC_TOP_L2_REG_START                         0x00451000
+#define BCHP_M2MC_TOP_L2_REG_END                           0x0045102c
+#define BCHP_M2MC_TOP_GR_BRIDGE_REG_START                  0x00452000
+#define BCHP_M2MC_TOP_GR_BRIDGE_REG_END                    0x0045200c
+#define BCHP_USB_INTR2_REG_START                           0x00480000
+#define BCHP_USB_INTR2_REG_END                             0x0048002c
+#define BCHP_USB_GR_BRIDGE_REG_START                       0x00480100
+#define BCHP_USB_GR_BRIDGE_REG_END                         0x0048010c
+#define BCHP_USB_CTRL_REG_START                            0x00480200
+#define BCHP_USB_CTRL_REG_END                              0x00480238
+#define BCHP_USB_EHCI_REG_START                            0x00480300
+#define BCHP_USB_EHCI_REG_END                              0x004803a4
+#define BCHP_USB_OHCI_REG_START                            0x00480400
+#define BCHP_USB_OHCI_REG_END                              0x00480458
+#define BCHP_BOOTROM_REG_START                             0x00500000
+#define BCHP_BOOTROM_REG_END                               0x00500ffc
+#define BCHP_MFD_0_REG_START                               0x00600000
+#define BCHP_MFD_0_REG_END                                 0x006001fc
+#define BCHP_VFD_0_REG_START                               0x00601000
+#define BCHP_VFD_0_REG_END                                 0x006011fc
+#define BCHP_VFD_1_REG_START                               0x00601200
+#define BCHP_VFD_1_REG_END                                 0x006013fc
+#define BCHP_RDC_REG_START                                 0x00602000
+#define BCHP_RDC_REG_END                                   0x006029fc
+#define BCHP_BVNF_INTR2_0_REG_START                        0x00603000
+#define BCHP_BVNF_INTR2_0_REG_END                          0x0060302c
+#define BCHP_BVNF_INTR2_1_REG_START                        0x00603100
+#define BCHP_BVNF_INTR2_1_REG_END                          0x0060312c
+#define BCHP_BVNF_INTR2_3_REG_START                        0x00603300
+#define BCHP_BVNF_INTR2_3_REG_END                          0x0060332c
+#define BCHP_BVNF_INTR2_4_REG_START                        0x00603400
+#define BCHP_BVNF_INTR2_4_REG_END                          0x0060342c
+#define BCHP_BVNF_INTR2_5_REG_START                        0x00603500
+#define BCHP_BVNF_INTR2_5_REG_END                          0x0060352c
+#define BCHP_BVNF_INTR2_6_REG_START                        0x00603600
+#define BCHP_BVNF_INTR2_6_REG_END                          0x0060362c
+#define BCHP_BVNF_INTR2_7_REG_START                        0x00603700
+#define BCHP_BVNF_INTR2_7_REG_END                          0x0060372c
+#define BCHP_FMISC_REG_START                               0x00604000
+#define BCHP_FMISC_REG_END                                 0x00604020
+#define BCHP_SCL_0_REG_START                               0x00620000
+#define BCHP_SCL_0_REG_END                                 0x006203fc
+#define BCHP_SCL_1_REG_START                               0x00620800
+#define BCHP_SCL_1_REG_END                                 0x00620bfc
+#define BCHP_VNET_F_REG_START                              0x00622000
+#define BCHP_VNET_F_REG_END                                0x0062209c
+#define BCHP_VNET_B_REG_START                              0x00622200
+#define BCHP_VNET_B_REG_END                                0x006222ac
+#define BCHP_MMISC_REG_START                               0x00622800
+#define BCHP_MMISC_REG_END                                 0x00622820
+#define BCHP_LBOX_0_REG_START                              0x00625000
+#define BCHP_LBOX_0_REG_END                                0x00625070
+#define BCHP_BVNM_INTR2_0_REG_START                        0x00626000
+#define BCHP_BVNM_INTR2_0_REG_END                          0x0062602c
+#define BCHP_DNR_0_REG_START                               0x00627000
+#define BCHP_DNR_0_REG_END                                 0x006270a4
+#define BCHP_CAP_0_REG_START                               0x00640000
+#define BCHP_CAP_0_REG_END                                 0x0064007c
+#define BCHP_CAP_1_REG_START                               0x00640200
+#define BCHP_CAP_1_REG_END                                 0x0064027c
+#define BCHP_GFD_0_REG_START                               0x00641000
+#define BCHP_GFD_0_REG_END                                 0x00641228
+#define BCHP_GFD_1_REG_START                               0x00641400
+#define BCHP_GFD_1_REG_END                                 0x00641628
+#define BCHP_CMP_0_REG_START                               0x00642000
+#define BCHP_CMP_0_REG_END                                 0x00642264
+#define BCHP_CMP_1_REG_START                               0x00642800
+#define BCHP_CMP_1_REG_END                                 0x00642a64
+#define BCHP_TNT_CMP_0_V0_REG_START                        0x00643000
+#define BCHP_TNT_CMP_0_V0_REG_END                          0x006430a4
+#define BCHP_MASK_0_REG_START                              0x00643400
+#define BCHP_MASK_0_REG_END                                0x0064341c
+#define BCHP_PEP_CMP_0_V0_REG_START                        0x00644000
+#define BCHP_PEP_CMP_0_V0_REG_END                          0x00645484
+#define BCHP_BVNB_INTR2_REG_START                          0x00646000
+#define BCHP_BVNB_INTR2_REG_END                            0x0064602c
+#define BCHP_BMISC_REG_START                               0x00646400
+#define BCHP_BMISC_REG_END                                 0x0064641c
+#define BCHP_MVP_TOP_0_REG_START                           0x00660000
+#define BCHP_MVP_TOP_0_REG_END                             0x0066002c
+#define BCHP_SIOB_0_REG_START                              0x00660200
+#define BCHP_SIOB_0_REG_END                                0x006602fc
+#define BCHP_HSCL_0_REG_START                              0x00660400
+#define BCHP_HSCL_0_REG_END                                0x006607fc
+#define BCHP_MDI_TOP_0_REG_START                           0x00662000
+#define BCHP_MDI_TOP_0_REG_END                             0x00662044
+#define BCHP_MDI_PPB_0_REG_START                           0x00662800
+#define BCHP_MDI_PPB_0_REG_END                             0x00662bfc
+#define BCHP_MDI_FCN_0_REG_START                           0x00662c00
+#define BCHP_MDI_FCN_0_REG_END                             0x00662ffc
+#define BCHP_MISC_REG_START                                0x00680000
+#define BCHP_MISC_REG_END                                  0x00680080
+#define BCHP_IT_0_REG_START                                0x00681000
+#define BCHP_IT_0_REG_END                                  0x006817fc
+#define BCHP_IT_1_REG_START                                0x00682000
+#define BCHP_IT_1_REG_END                                  0x006827fc
+#define BCHP_VF_0_REG_START                                0x00683000
+#define BCHP_VF_0_REG_END                                  0x00683134
+#define BCHP_VF_1_REG_START                                0x00683200
+#define BCHP_VF_1_REG_END                                  0x00683334
+#define BCHP_SECAM_0_REG_START                             0x00683400
+#define BCHP_SECAM_0_REG_END                               0x00683414
+#define BCHP_SM_0_REG_START                                0x00683480
+#define BCHP_SM_0_REG_END                                  0x006834ac
+#define BCHP_SDSRC_0_REG_START                             0x00683500
+#define BCHP_SDSRC_0_REG_END                               0x0068350c
+#define BCHP_HDSRC_0_REG_START                             0x00683520
+#define BCHP_HDSRC_0_REG_END                               0x0068353c
+#define BCHP_CSC_0_REG_START                               0x00683580
+#define BCHP_CSC_0_REG_END                                 0x006835b0
+#define BCHP_CSC_1_REG_START                               0x00683600
+#define BCHP_CSC_1_REG_END                                 0x00683630
+#define BCHP_RM_0_REG_START                                0x00683680
+#define BCHP_RM_0_REG_END                                  0x006836a4
+#define BCHP_RM_1_REG_START                                0x006836c0
+#define BCHP_RM_1_REG_END                                  0x006836e4
+#define BCHP_ANA_DEBUG_0_REG_START                         0x00683700
+#define BCHP_ANA_DEBUG_0_REG_END                           0x00683744
+#define BCHP_GRPD_0_REG_START                              0x00683800
+#define BCHP_GRPD_0_REG_END                                0x006838ec
+#define BCHP_DTRAM_0_REG_START                             0x00684000
+#define BCHP_DTRAM_0_REG_END                               0x0068447c
+#define BCHP_DVI_DTG_0_REG_START                           0x00684800
+#define BCHP_DVI_DTG_0_REG_END                             0x00684954
+#define BCHP_DVI_CSC_0_REG_START                           0x00684a00
+#define BCHP_DVI_CSC_0_REG_END                             0x00684a30
+#define BCHP_DVI_DVF_0_REG_START                           0x00684b00
+#define BCHP_DVI_DVF_0_REG_END                             0x00684b14
+#define BCHP_DVI_DEBUG_0_REG_START                         0x00684c00
+#define BCHP_DVI_DEBUG_0_REG_END                           0x00684c44
+#define BCHP_VEC_CFG_REG_START                             0x00685000
+#define BCHP_VEC_CFG_REG_END                               0x006850d4
+#define BCHP_VIDEO_ENC_INTR2_REG_START                     0x00685400
+#define BCHP_VIDEO_ENC_INTR2_REG_END                       0x0068542c
+#define BCHP_VIDEO_ENC_TPG_0_REG_START                     0x00685500
+#define BCHP_VIDEO_ENC_TPG_0_REG_END                       0x00685518
+#define BCHP_VIDEO_ENC_DECIM_0_REG_START                   0x00685600
+#define BCHP_VIDEO_ENC_DECIM_0_REG_END                     0x00685608
+#define BCHP_DVP_TVG_0_REG_START                           0x00685700
+#define BCHP_DVP_TVG_0_REG_END                             0x00685788
+#define BCHP_VBI_ENC_REG_START                             0x00686000
+#define BCHP_VBI_ENC_REG_END                               0x00686054
+#define BCHP_CCE_0_REG_START                               0x00686400
+#define BCHP_CCE_0_REG_END                                 0x00686458
+#define BCHP_CCE_1_REG_START                               0x00686500
+#define BCHP_CCE_1_REG_END                                 0x00686558
+#define BCHP_WSE_0_REG_START                               0x00686600
+#define BCHP_WSE_0_REG_END                                 0x00686614
+#define BCHP_WSE_1_REG_START                               0x00686700
+#define BCHP_WSE_1_REG_END                                 0x00686714
+#define BCHP_CGMSAE_0_REG_START                            0x00686800
+#define BCHP_CGMSAE_0_REG_END                              0x00686858
+#define BCHP_CGMSAE_1_REG_START                            0x00686900
+#define BCHP_CGMSAE_1_REG_END                              0x00686958
+#define BCHP_TTE_0_REG_START                               0x00686a00
+#define BCHP_TTE_0_REG_END                                 0x00686a28
+#define BCHP_TTE_1_REG_START                               0x00686b00
+#define BCHP_TTE_1_REG_END                                 0x00686b28
+#define BCHP_GSE_0_REG_START                               0x00686c00
+#define BCHP_GSE_0_REG_END                                 0x00686c80
+#define BCHP_GSE_1_REG_START                               0x00686d00
+#define BCHP_GSE_1_REG_END                                 0x00686d80
+#define BCHP_AMOLE_0_REG_START                             0x00686e00
+#define BCHP_AMOLE_0_REG_END                               0x00686e8c
+#define BCHP_AMOLE_1_REG_START                             0x00686f00
+#define BCHP_AMOLE_1_REG_END                               0x00686f8c
+#define BCHP_DVP_HT_REG_START                              0x006a0000
+#define BCHP_DVP_HT_REG_END                                0x006a00dc
+#define BCHP_HDMI_REG_START                                0x006a0800
+#define BCHP_HDMI_REG_END                                  0x006a0994
+#define BCHP_HDMI_TX_PHY_REG_START                         0x006a0a80
+#define BCHP_HDMI_TX_PHY_REG_END                           0x006a0ad8
+#define BCHP_HDMI_RM_REG_START                             0x006a0b00
+#define BCHP_HDMI_RM_REG_END                               0x006a0b2c
+#define BCHP_HDMI_TX_INTR2_REG_START                       0x006a0b40
+#define BCHP_HDMI_TX_INTR2_REG_END                         0x006a0b6c
+#define BCHP_HDMI_RAM_REG_START                            0x006a0c00
+#define BCHP_HDMI_RAM_REG_END                              0x006a0dfc
+#define BCHP_BVN_RGR_REG_START                             0x006a8000
+#define BCHP_BVN_RGR_REG_END                               0x006a8010
+#define BCHP_SDS_CG_REG_START                              0x00700000
+#define BCHP_SDS_CG_REG_END                                0x00700038
+#define BCHP_SDS_FE_REG_START                              0x00700080
+#define BCHP_SDS_FE_REG_END                                0x007000bc
+#define BCHP_SDS_AGC_REG_START                             0x00700100
+#define BCHP_SDS_AGC_REG_END                               0x00700124
+#define BCHP_SDS_BL_REG_START                              0x00700140
+#define BCHP_SDS_BL_REG_END                                0x00700160
+#define BCHP_SDS_CL_REG_START                              0x00700180
+#define BCHP_SDS_CL_REG_END                                0x007001fc
+#define BCHP_SDS_EQ_REG_START                              0x00700200
+#define BCHP_SDS_EQ_REG_END                                0x0070028c
+#define BCHP_SDS_HP_REG_START                              0x00700300
+#define BCHP_SDS_HP_REG_END                                0x007003d4
+#define BCHP_SDS_VIT_REG_START                             0x00700400
+#define BCHP_SDS_VIT_REG_END                               0x00700428
+#define BCHP_SDS_FEC_REG_START                             0x00700440
+#define BCHP_SDS_FEC_REG_END                               0x00700454
+#define BCHP_SDS_OI_REG_START                              0x00700480
+#define BCHP_SDS_OI_REG_END                                0x007004c8
+#define BCHP_SDS_SNR_REG_START                             0x00700500
+#define BCHP_SDS_SNR_REG_END                               0x00700518
+#define BCHP_SDS_BERT_REG_START                            0x00700540
+#define BCHP_SDS_BERT_REG_END                              0x0070055c
+#define BCHP_SDS_DFT_REG_START                             0x00700580
+#define BCHP_SDS_DFT_REG_END                               0x007005a8
+#define BCHP_SDS_CWC_REG_START                             0x00700600
+#define BCHP_SDS_CWC_REG_END                               0x00700694
+#define BCHP_SDS_MISC_REG_START                            0x00700700
+#define BCHP_SDS_MISC_REG_END                              0x00700798
+#define BCHP_SDS_DSEC_REG_START                            0x00700800
+#define BCHP_SDS_DSEC_REG_END                              0x007008c8
+#define BCHP_SDS_TUNER_REG_START                           0x00700900
+#define BCHP_SDS_TUNER_REG_END                             0x007009fc
+#define BCHP_SDS_INTR2_0_REG_START                         0x00700a00
+#define BCHP_SDS_INTR2_0_REG_END                           0x00700a2c
+#define BCHP_SDS_INTR2_1_REG_START                         0x00700b00
+#define BCHP_SDS_INTR2_1_REG_END                           0x00700b2c
+#define BCHP_SDS_GR_BRIDGE_REG_START                       0x00700c00
+#define BCHP_SDS_GR_BRIDGE_REG_END                         0x00700c0c
+#define BCHP_TFEC_REG_START                                0x00702000
+#define BCHP_TFEC_REG_END                                  0x00702060
+#define BCHP_TFEC_MISC_REG_START                           0x00702100
+#define BCHP_TFEC_MISC_REG_END                             0x00702108
+#define BCHP_TFEC_INTR2_REG_START                          0x00702200
+#define BCHP_TFEC_INTR2_REG_END                            0x0070222c
+#define BCHP_TFEC_GR_BRIDGE_REG_START                      0x00702300
+#define BCHP_TFEC_GR_BRIDGE_REG_END                        0x0070230c
+#define BCHP_AFEC_REG_START                                0x00704000
+#define BCHP_AFEC_REG_END                                  0x007043fc
+#define BCHP_AFEC_INTR_CTRL2_REG_START                     0x00704800
+#define BCHP_AFEC_INTR_CTRL2_REG_END                       0x0070482c
+#define BCHP_AFEC_GR_BRIDGE_REG_START                      0x00704900
+#define BCHP_AFEC_GR_BRIDGE_REG_END                        0x0070490c
+#define BCHP_AFEC_GLOBAL_REG_START                         0x00704a00
+#define BCHP_AFEC_GLOBAL_REG_END                           0x00704a0c
+#define BCHP_FTM_UART_REG_START                            0x00706000
+#define BCHP_FTM_UART_REG_END                              0x007060fc
+#define BCHP_FTM_PHY_REG_START                             0x00706000
+#define BCHP_FTM_PHY_REG_END                               0x007061fc
+#define BCHP_FTM_PHY_ANA_REG_START                         0x00706000
+#define BCHP_FTM_PHY_ANA_REG_END                           0x00706210
+#define BCHP_FTM_SKIT_REG_START                            0x00706000
+#define BCHP_FTM_SKIT_REG_END                              0x00706248
+#define BCHP_FTM_INTR2_REG_START                           0x00706000
+#define BCHP_FTM_INTR2_REG_END                             0x0070632c
+#define BCHP_FTM_GR_BRIDGE_REG_START                       0x00706000
+#define BCHP_FTM_GR_BRIDGE_REG_END                         0x0070633c
+#define BCHP_FTM_SW_SPARE_REG_START                        0x00706000
+#define BCHP_FTM_SW_SPARE_REG_END                          0x00706344
+#define BCHP_RAAGA_DSP_RGR_REG_START                       0x00800000
+#define BCHP_RAAGA_DSP_RGR_REG_END                         0x00800008
+#define BCHP_RAAGA_DSP_MISC_REG_START                      0x00820000
+#define BCHP_RAAGA_DSP_MISC_REG_END                        0x0082044c
+#define BCHP_RAAGA_DSP_TIMERS_REG_START                    0x00821000
+#define BCHP_RAAGA_DSP_TIMERS_REG_END                      0x00821058
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START             0x00821080
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END               0x0082109c
+#define BCHP_RAAGA_DSP_PERI_SW_REG_START                   0x00821100
+#define BCHP_RAAGA_DSP_PERI_SW_REG_END                     0x00821154
+#define BCHP_RAAGA_DSP_DMA_REG_START                       0x00821400
+#define BCHP_RAAGA_DSP_DMA_REG_END                         0x00821664
+#define BCHP_RAAGA_DSP_ESR_SI_REG_START                    0x00822000
+#define BCHP_RAAGA_DSP_ESR_SI_REG_END                      0x00822014
+#define BCHP_RAAGA_DSP_INTH_REG_START                      0x00822200
+#define BCHP_RAAGA_DSP_INTH_REG_END                        0x0082222c
+#define BCHP_RAAGA_DSP_FW_INTH_REG_START                   0x00822400
+#define BCHP_RAAGA_DSP_FW_INTH_REG_END                     0x0082242c
+#define BCHP_RAAGA_DSP_FW_CFG_REG_START                    0x00823000
+#define BCHP_RAAGA_DSP_FW_CFG_REG_END                      0x0082357c
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START             0x00830000
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END               0x0083bffc
+#define BCHP_AIO_MISC_REG_START                            0x00880000
+#define BCHP_AIO_MISC_REG_END                              0x00880010
+#define BCHP_AIO_INTH_REG_START                            0x00880800
+#define BCHP_AIO_INTH_REG_END                              0x0088082c
+#define BCHP_AIO_INTD0_REG_START                           0x00880a00
+#define BCHP_AIO_INTD0_REG_END                             0x00880a14
+#define BCHP_AUD_FMM_MISC_REG_START                        0x008a0000
+#define BCHP_AUD_FMM_MISC_REG_END                          0x008a010c
+#define BCHP_AUD_FMM_BF_CTRL_REG_START                     0x008a2000
+#define BCHP_AUD_FMM_BF_CTRL_REG_END                       0x008a2b7c
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_START                   0x008a3000
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_END                     0x008a3014
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_START                   0x008a3020
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_END                     0x008a3034
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_START                   0x008a3040
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_END                     0x008a3054
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_START                  0x008a3100
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_END                    0x008a3114
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_START                  0x008a3120
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_END                    0x008a3134
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_START                  0x008a3140
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_END                    0x008a3154
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_START                   0x008a4000
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_END                     0x008a4bfc
+#define BCHP_AUD_FMM_SRC_ESR0_REG_START                    0x008a5000
+#define BCHP_AUD_FMM_SRC_ESR0_REG_END                      0x008a5014
+#define BCHP_AUD_FMM_DP_CTRL0_REG_START                    0x008a8000
+#define BCHP_AUD_FMM_DP_CTRL0_REG_END                      0x008a98ec
+#define BCHP_AUD_FMM_DP_ESR00_REG_START                    0x008abc00
+#define BCHP_AUD_FMM_DP_ESR00_REG_END                      0x008abc14
+#define BCHP_AUD_FMM_DP_ESR20_REG_START                    0x008abc80
+#define BCHP_AUD_FMM_DP_ESR20_REG_END                      0x008abc94
+#define BCHP_AUD_FMM_IOP_CTRL_REG_START                    0x008b8000
+#define BCHP_AUD_FMM_IOP_CTRL_REG_END                      0x008b8144
+#define BCHP_AUD_FMM_IOP_ESR_REG_START                     0x008b8400
+#define BCHP_AUD_FMM_IOP_ESR_REG_END                       0x008b8414
+#define BCHP_AUD_FMM_OP_CTRL_REG_START                     0x008ba000
+#define BCHP_AUD_FMM_OP_CTRL_REG_END                       0x008ba1fc
+#define BCHP_AUD_FMM_OP_ESR_REG_START                      0x008ba400
+#define BCHP_AUD_FMM_OP_ESR_REG_END                        0x008ba414
+#define BCHP_AUD_FMM_PLL0_REG_START                        0x008ba800
+#define BCHP_AUD_FMM_PLL0_REG_END                          0x008ba834
+#define BCHP_AUD_FMM_PLL1_REG_START                        0x008ba900
+#define BCHP_AUD_FMM_PLL1_REG_END                          0x008ba934
+#define BCHP_HIFIDAC_CTRL0_REG_START                       0x008bb000
+#define BCHP_HIFIDAC_CTRL0_REG_END                         0x008bb1fc
+#define BCHP_HIFIDAC_RM0_REG_START                         0x008bb200
+#define BCHP_HIFIDAC_RM0_REG_END                           0x008bb224
+#define BCHP_HIFIDAC_ESR0_REG_START                        0x008bb300
+#define BCHP_HIFIDAC_ESR0_REG_END                          0x008bb314
+#define BCHP_AUD_FMM_MS_CTRL_REG_START                     0x008bc000
+#define BCHP_AUD_FMM_MS_CTRL_REG_END                       0x008bdbfc
+#define BCHP_AUD_FMM_MS_ESR_REG_START                      0x008be000
+#define BCHP_AUD_FMM_MS_ESR_REG_END                        0x008be014
+#define BCHP_RAAGA_DSP_SEC0_REG_START                      0x00900000
+#define BCHP_RAAGA_DSP_SEC0_REG_END                        0x00900000
+#define BCHP_XPT_BUS_IF_REG_START                          0x00a00000
+#define BCHP_XPT_BUS_IF_REG_END                            0x00a00088
+#define BCHP_XPT_XMEMIF_REG_START                          0x00a01000
+#define BCHP_XPT_XMEMIF_REG_END                            0x00a0109c
+#define BCHP_XPT_PMU_REG_START                             0x00a01800
+#define BCHP_XPT_PMU_REG_END                               0x00a01808
+#define BCHP_XPT_WAKEUP_REG_START                          0x00a02000
+#define BCHP_XPT_WAKEUP_REG_END                            0x00a02fbc
+#define BCHP_XPT_RMX0_IO_REG_START                         0x00a03000
+#define BCHP_XPT_RMX0_IO_REG_END                           0x00a03020
+#define BCHP_XPT_RMX1_IO_REG_START                         0x00a03100
+#define BCHP_XPT_RMX1_IO_REG_END                           0x00a03120
+#define BCHP_XPT_FE_REG_START                              0x00a04000
+#define BCHP_XPT_FE_REG_END                                0x00a04ffc
+#define BCHP_XPT_DPCR0_REG_START                           0x00a06000
+#define BCHP_XPT_DPCR0_REG_END                             0x00a06074
+#define BCHP_XPT_DPCR1_REG_START                           0x00a06080
+#define BCHP_XPT_DPCR1_REG_END                             0x00a060f4
+#define BCHP_XPT_DPCR2_REG_START                           0x00a06100
+#define BCHP_XPT_DPCR2_REG_END                             0x00a06174
+#define BCHP_XPT_DPCR3_REG_START                           0x00a06180
+#define BCHP_XPT_DPCR3_REG_END                             0x00a061f4
+#define BCHP_XPT_DPCR_PP_REG_START                         0x00a06400
+#define BCHP_XPT_DPCR_PP_REG_END                           0x00a06404
+#define BCHP_XPT_PSUB_REG_START                            0x00a06600
+#define BCHP_XPT_PSUB_REG_END                              0x00a066c8
+#define BCHP_XPT_RSBUFF_REG_START                          0x00a06800
+#define BCHP_XPT_RSBUFF_REG_END                            0x00a06f2c
+#define BCHP_XPT_PB0_REG_START                             0x00a07000
+#define BCHP_XPT_PB0_REG_END                               0x00a07060
+#define BCHP_XPT_PB1_REG_START                             0x00a07080
+#define BCHP_XPT_PB1_REG_END                               0x00a070e0
+#define BCHP_XPT_PB2_REG_START                             0x00a07100
+#define BCHP_XPT_PB2_REG_END                               0x00a07160
+#define BCHP_XPT_PB3_REG_START                             0x00a07180
+#define BCHP_XPT_PB3_REG_END                               0x00a071e0
+#define BCHP_XPT_MPOD_REG_START                            0x00a08000
+#define BCHP_XPT_MPOD_REG_END                              0x00a08020
+#define BCHP_XPT_RMX0_REG_START                            0x00a08400
+#define BCHP_XPT_RMX0_REG_END                              0x00a08408
+#define BCHP_XPT_RMX1_REG_START                            0x00a08500
+#define BCHP_XPT_RMX1_REG_END                              0x00a08508
+#define BCHP_XPT_XCBUFF_REG_START                          0x00a0a000
+#define BCHP_XPT_XCBUFF_REG_END                            0x00a0bcc8
+#define BCHP_XPT_RAVE_REG_START                            0x00a10000
+#define BCHP_XPT_RAVE_REG_END                              0x00a1a69c
+#define BCHP_XPT_PCROFFSET_REG_START                       0x00a1b000
+#define BCHP_XPT_PCROFFSET_REG_END                         0x00a1bffc
+#define BCHP_XPT_MSG_REG_START                             0x00a20000
+#define BCHP_XPT_MSG_REG_END                               0x00a24814
+#define BCHP_XPT_GR_REG_START                              0x00a25000
+#define BCHP_XPT_GR_REG_END                                0x00a2500c
+#define BCHP_XPT_FULL_PID_PARSER_REG_START                 0x00a26000
+#define BCHP_XPT_FULL_PID_PARSER_REG_END                   0x00a27050
+#define BCHP_XPT_XPU_REG_START                             0x00a28000
+#define BCHP_XPT_XPU_REG_END                               0x00a2c7fc
+#define BCHP_XPT_SECURE_BUS_IF_REG_START                   0x00a38000
+#define BCHP_XPT_SECURE_BUS_IF_REG_END                     0x00a38000
+#define BCHP_RFM_SYSCLK_REG_START                          0x00b00000
+#define BCHP_RFM_SYSCLK_REG_END                            0x00b00118
+#define BCHP_RFM_CLK27_REG_START                           0x00b00000
+#define BCHP_RFM_CLK27_REG_END                             0x00b00470
+#define BCHP_RFM_L2_REG_START                              0x00b00c00
+#define BCHP_RFM_L2_REG_END                                0x00b00c2c
+#define BCHP_RFM_GRB_REG_START                             0x00b01000
+#define BCHP_RFM_GRB_REG_END                               0x00b0100c
+
+
+/***************************************************************************
+ *AUD_FMM_MS_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK  0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
+
+/***************************************************************************
+ *AUD_FMM_OP_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
+ ***************************************************************************/
+/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_VFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *GFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK      0xffffffff
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT     0
+
+/***************************************************************************
+ *HIFIDAC_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_MUTE_USAGE - Mute usage
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *M2MC
+ ***************************************************************************/
+/***************************************************************************
+ *TYPE_CLUT_COLOR_DATA - color data for color look up table
+ ***************************************************************************/
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK                  0xff000000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT                 24
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK                    0x00ff0000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT                   16
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK                  0x0000ff00
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT                 8
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK                   0x000000ff
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT                  0
+
+/***************************************************************************
+ *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK          0xffffffff
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT         0
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK              0xf0000000
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT             28
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK          0x0fffffe0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT         5
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK              0x0000001e
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT             1
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK           0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT          0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid   0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK              0xffff8000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT             15
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK   0x00004000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT  14
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK   0x00002000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT  13
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK         0x00000800
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT        11
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE   1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE  0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK  0x00000400
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK  0x00000200
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK          0x00000100
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT         8
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE   0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK   0x00000020
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT  5
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK     0x00000002
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK     0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT    0
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/***************************************************************************
+ *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK        0xffffffff
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT       0
+
+/***************************************************************************
+ *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK         0xffffffff
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT        0
+
+/***************************************************************************
+ *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_11_DST_COLOR_MATRIX_N - Linked-List Packet Word N for group DST_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_11_DST_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_12_OUTPUT_COLOR_MATRIX_N - Linked-List Packet Word N for group OUTPUT_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_12_OUTPUT_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_13_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *LIST_PKT_14_DST_CLUT - Linked-List Packet Word for group DST_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_14_DST_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_14_DST_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *MEM_DMA
+ ***************************************************************************/
+/***************************************************************************
+ *DESC_WORD0 - MEM DMA Descriptor Word 0
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD0 :: READ_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD1 - MEM DMA Descriptor Word 1
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD1 :: WRITE_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_MASK                    0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD2 - MEM DMA Descriptor Word 2
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD2 :: INTR_ENABLE [31:31] */
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK                   0x80000000
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_SHIFT                  31
+
+/* MEM_DMA :: DESC_WORD2 :: LAST [30:30] */
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_MASK                          0x40000000
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_SHIFT                         30
+
+/* MEM_DMA :: DESC_WORD2 :: AUTO_APPEND [29:29] */
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_MASK                   0x20000000
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_SHIFT                  29
+
+/* MEM_DMA :: DESC_WORD2 :: reserved0 [28:25] */
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_MASK                     0x1e000000
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_SHIFT                    25
+
+/* MEM_DMA :: DESC_WORD2 :: TRANSFER_SIZE [24:00] */
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK                 0x01ffffff
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_SHIFT                0
+
+/***************************************************************************
+ *DESC_WORD3 - MEM DMA Descriptor Word 3
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD3 :: NEXT_DESC_ADDR [31:05] */
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK                0xffffffe0
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_SHIFT               5
+
+/* MEM_DMA :: DESC_WORD3 :: reserved0 [04:03] */
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_MASK                     0x00000018
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_SHIFT                    3
+
+/* MEM_DMA :: DESC_WORD3 :: READ_ENDIAN_MODE [02:02] */
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_MASK              0x00000004
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_SHIFT             2
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_BIG_ENDIAN        0
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_LITTLE_ENDIAN     1
+
+/* MEM_DMA :: DESC_WORD3 :: WRITE_ENDIAN_XLATE_MODE [01:00] */
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_MASK       0x00000003
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_SHIFT      0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_WORD_ALIGNED 0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_HALF_WORD_ALIGNED 1
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_BYTE_ALIGNED 2
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_reserved   3
+
+/***************************************************************************
+ *DESC_WORD4 - MEM DMA Descriptor Word 4
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD4 :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_SHIFT                    16
+
+/* MEM_DMA :: DESC_WORD4 :: SCRAM_CTRL_RSV [15:14] */
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_MASK                0x0000c000
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_SHIFT               14
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_END [13:13] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK                  0x00002000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_SHIFT                 13
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_START [12:12] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK                0x00001000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_SHIFT               12
+
+/* MEM_DMA :: DESC_WORD4 :: SG_ENABLE [11:11] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK                     0x00000800
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_SHIFT                    11
+
+/* MEM_DMA :: DESC_WORD4 :: ENC_DEC_INIT [10:10] */
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_MASK                  0x00000400
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_SHIFT                 10
+
+/* MEM_DMA :: DESC_WORD4 :: MODE_SEL [09:08] */
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_MASK                      0x00000300
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT                     8
+
+/* MEM_DMA :: DESC_WORD4 :: KEY_SELECT [07:00] */
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_MASK                    0x000000ff
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD5 - MEM DMA Descriptor Word 5
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD5 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD6 - MEM DMA Descriptor Word 6
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD6 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD7 - MEM DMA Descriptor Word 7
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD7 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *RAAGA_REGSET_DSP_CFG
+ ***************************************************************************/
+/***************************************************************************
+ *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
+
+/***************************************************************************
+ *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off     0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On      1
+
+/***************************************************************************
+ *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt  1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo  2
+
+/***************************************************************************
+ *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK       0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT      0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right -2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right -2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right -2147483648
+
+/***************************************************************************
+ *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK     0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT    0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo   2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono     1
+
+/***************************************************************************
+ *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono    1
+
+/***************************************************************************
+ *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK   0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *RDC
+ ***************************************************************************/
+/***************************************************************************
+ *RUL - RUL Command.
+ ***************************************************************************/
+/* RDC :: RUL :: opcode [31:24] */
+#define BCHP_RDC_RUL_opcode_MASK                                   0xff000000
+#define BCHP_RDC_RUL_opcode_SHIFT                                  24
+#define BCHP_RDC_RUL_opcode_NOP                                    0
+#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM                          1
+#define BCHP_RDC_RUL_opcode_REG_WRITE                              2
+#define BCHP_RDC_RUL_opcode_REG_READ                               3
+#define BCHP_RDC_RUL_opcode_LOAD_IMM                               4
+#define BCHP_RDC_RUL_opcode_WINDOW_WRITE                           5
+#define BCHP_RDC_RUL_opcode_BLOCK_WRITE                            6
+#define BCHP_RDC_RUL_opcode_WINDOW_COPY                            7
+#define BCHP_RDC_RUL_opcode_BLOCK_COPY                             8
+#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK                        9
+#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW                        10
+#define BCHP_RDC_RUL_opcode_AND                                    11
+#define BCHP_RDC_RUL_opcode_AND_IMM                                12
+#define BCHP_RDC_RUL_opcode_OR                                     13
+#define BCHP_RDC_RUL_opcode_OR_IMM                                 14
+#define BCHP_RDC_RUL_opcode_XOR                                    15
+#define BCHP_RDC_RUL_opcode_XOR_IMM                                16
+#define BCHP_RDC_RUL_opcode_NOT                                    17
+#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT                           18
+#define BCHP_RDC_RUL_opcode_SUM                                    19
+#define BCHP_RDC_RUL_opcode_SUM_IMM                                20
+#define BCHP_RDC_RUL_opcode_COND_SKIP                              21
+#define BCHP_RDC_RUL_opcode_SKIP                                   22
+#define BCHP_RDC_RUL_opcode_EXIT                                   23
+#define BCHP_RDC_RUL_opcode_PLACEHOLDER                            255
+
+/* RDC :: RUL :: reserved0 [23:23] */
+#define BCHP_RDC_RUL_reserved0_MASK                                0x00800000
+#define BCHP_RDC_RUL_reserved0_SHIFT                               23
+
+/* union - case rdc_args [22:00] */
+/* RDC :: RUL :: rdc_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_rdc_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: rdc_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_rdc_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_rdc_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: rdc_args :: src2 [11:06] */
+#define BCHP_RDC_RUL_rdc_args_src2_MASK                            0x00000fc0
+#define BCHP_RDC_RUL_rdc_args_src2_SHIFT                           6
+
+/* RDC :: RUL :: rdc_args :: dest [05:00] */
+#define BCHP_RDC_RUL_rdc_args_dest_MASK                            0x0000003f
+#define BCHP_RDC_RUL_rdc_args_dest_SHIFT                           0
+
+/* union - case reg_args [22:00] */
+/* RDC :: RUL :: reg_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_reg_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_reg_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: reg_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_reg_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_reg_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: reg_args :: count [11:00] */
+#define BCHP_RDC_RUL_reg_args_count_MASK                           0x00000fff
+#define BCHP_RDC_RUL_reg_args_count_SHIFT                          0
+
+/***************************************************************************
+ *XPT_PB
+ ***************************************************************************/
+/***************************************************************************
+ *DESCRIPTOR_ABSTRACT - Playback Linked-List Descriptor Abstract
+ ***************************************************************************/
+/* XPT_PB :: DESCRIPTOR_ABSTRACT :: DESCRIPTOR_FORMAT [31:00] */
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_MASK     0xffffffff
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_SHIFT    0
+
+/***************************************************************************
+ *DESC_0 - Playback Linked-List Descriptor Word 0
+ ***************************************************************************/
+/* XPT_PB :: DESC_0 :: PB_BUFFER_START_ADDR [31:00] */
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_MASK               0xffffffff
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_SHIFT              0
+
+/***************************************************************************
+ *DESC_1 - Playback Linked-List Descriptor Word 1
+ ***************************************************************************/
+/* XPT_PB :: DESC_1 :: PB_BUFFER_LENGTH [31:00] */
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_MASK                   0xffffffff
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_SHIFT                  0
+
+/***************************************************************************
+ *DESC_2 - Playback Linked-List Descriptor Word 2
+ ***************************************************************************/
+/* XPT_PB :: DESC_2 :: PB_INTERRUPT_ENABLE [31:31] */
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_MASK                0x80000000
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_SHIFT               31
+
+/* XPT_PB :: DESC_2 :: PB_FORCE_RESYNC [30:30] */
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_MASK                    0x40000000
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_SHIFT                   30
+
+/* XPT_PB :: DESC_2 :: PB_HOST_DATA_INS_EN [29:29] */
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_MASK                0x20000000
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_SHIFT               29
+
+/* XPT_PB :: DESC_2 :: reserved0 [28:28] */
+#define BCHP_XPT_PB_DESC_2_reserved0_MASK                          0x10000000
+#define BCHP_XPT_PB_DESC_2_reserved0_SHIFT                         28
+
+/* XPT_PB :: DESC_2 :: PB_DESC_TAG_ID [27:24] */
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_MASK                     0x0f000000
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_SHIFT                    24
+
+/* XPT_PB :: DESC_2 :: reserved1 [23:00] */
+#define BCHP_XPT_PB_DESC_2_reserved1_MASK                          0x00ffffff
+#define BCHP_XPT_PB_DESC_2_reserved1_SHIFT                         0
+
+/***************************************************************************
+ *DESC_3 - Playback Linked-List Descriptor Word 3
+ ***************************************************************************/
+/* XPT_PB :: DESC_3 :: PB_NEXT_DESC_ADDR [31:04] */
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_MASK                  0xfffffff0
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_SHIFT                 4
+
+/* XPT_PB :: DESC_3 :: reserved0 [03:01] */
+#define BCHP_XPT_PB_DESC_3_reserved0_MASK                          0x0000000e
+#define BCHP_XPT_PB_DESC_3_reserved0_SHIFT                         1
+
+/* XPT_PB :: DESC_3 :: PB_LAST_DESC_IND [00:00] */
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_MASK                   0x00000001
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_SHIFT                  0
+
+/***************************************************************************
+ *XPT_RAVE
+ ***************************************************************************/
+/***************************************************************************
+ *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
+
+/***************************************************************************
+ *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
+
+/***************************************************************************
+ *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
+ ***************************************************************************/
+/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
+
+#endif /* #ifndef BCHP_COMMON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_ddr40_phy_control_regs_0.h b/include/linux/brcmstb/7362a0/bchp_ddr40_phy_control_regs_0.h
new file mode 100644
index 0000000..3549fcd
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_ddr40_phy_control_regs_0.h
@@ -0,0 +1,1539 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_ddr40_phy_control_regs_0.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:43a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_CONTROL_REGS_0 - DDR40 DDR40 physical interface control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION   0x003b6000 /* Address & Control revision register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL 0x003b6004 /* PHY clock power management control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS 0x003b6010 /* PHY PLL status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG 0x003b6014 /* PHY PLL configuration register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL 0x003b6018 /* PHY PLL control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS 0x003b601c /* PHY PLL dividers control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL 0x003b6020 /* Aux Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL 0x003b6030 /* Address & Control coarse VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL 0x003b6034 /* Address & Control fine VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL 0x003b6038 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL 0x003b603c /* PVT Compensation control and status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL 0x003b6040 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS 0x003b6044 /* PHY Auto Init rd_data_dly result register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE 0x003b6048 /* PHY VDL calibration control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS 0x003b604c /* PHY VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS 0x003b6050 /* PHY DQ VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS 0x003b6054 /* PHY Write Channel VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS 0x003b6058 /* PHY Read Enable VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL 0x003b605c /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS 0x003b6060 /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS 0x003b6064 /* Virtual VTT Connections register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE 0x003b6068 /* Virtual VTT Override register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL 0x003b606c /* VREF DAC Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL 0x003b6070 /* PhyBist Control Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED 0x003b6074 /* PhyBist Seed Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS 0x003b6078 /* PhyBist General Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS 0x003b607c /* PhyBist Per-Bit Control Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS 0x003b6080 /* PhyBist Per-Bit DQ Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS 0x003b6084 /* PhyBist Per-Bit DM and CK Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG 0x003b6090 /* DRAM Command Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0  0x003b6094 /* Mode Register 0 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1  0x003b6098 /* Mode Register 1 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2  0x003b609c /* Mode Register 2 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3  0x003b60a0 /* Mode Register 3 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL 0x003b60a4 /* Standby Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL 0x003b60b0 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2 0x003b60b4 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS 0x003b60b8 /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2 0x003b60bc /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE 0x003b60c0 /* Freeze-on-error enable register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK 0x003b60c4 /* Datapth Loopback control register */
+
+/***************************************************************************
+ *REVISION - Address & Control revision register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: reserved0 [31:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_MASK      0xff800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_SHIFT     23
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: TECHNOLOGY [22:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_TECHNOLOGY_MASK     0x00700000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_TECHNOLOGY_SHIFT    20
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: WB [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_WB_MASK             0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_WB_SHIFT            19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: BITS [18:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_BITS_MASK           0x00070000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_BITS_SHIFT          16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_MASK          0x0000ff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_SHIFT         8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_DEFAULT       0x00000040
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_MASK          0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_DEFAULT       0x00000006
+
+/***************************************************************************
+ *CLK_PM_CTRL - PHY clock power management control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_MASK   0xfffffffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_SHIFT  1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_STATUS - PHY PLL status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_MASK    0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_SHIFT   27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK_LOST [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_MASK    0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_SHIFT   26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: DDR_MHZ [25:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_MASK      0x03ffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_SHIFT     14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_4X [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: STATUS [12:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_MASK       0x00001ffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_SHIFT      1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_MASK         0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_CONFIG - PHY PLL configuration register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved0 [31:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_MASK    0xffffff80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_SHIFT   7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LP40_PLL_POST_RESET [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET_POST_DIV [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LDO_CTRL [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_MASK     0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_SHIFT    3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_DEFAULT  0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved1 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_MASK    0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_SHIFT   2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_MASK        0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_SHIFT       1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_DEFAULT     0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PWRDN [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_MASK        0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_SHIFT       0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PLL_CONTROL - PHY PLL control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: reserved0 [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_SHIFT  31
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_kp [30:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_MASK        0x78000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_SHIFT       27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_DEFAULT     0x0000000a
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ki [26:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_MASK        0x07000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_SHIFT       24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_DEFAULT     0x00000003
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ka [23:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_MASK        0x00e00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_SHIFT       21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_DEFAULT     0x00000003
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: PLL_CONTROL [20:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_MASK 0x001fffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_DIVIDERS - PHY PLL dividers control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_MASK  0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_SHIFT 16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_HI [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_MASK 0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_LO [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: POST_DIV [13:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_MASK   0x00003800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_SHIFT  11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_DEFAULT 0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: PDIV [10:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_MASK       0x00000700
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_SHIFT      8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_DEFAULT    0x00000004
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_MASK       0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_DEFAULT    0x00000020
+
+/***************************************************************************
+ *AUX_CONTROL - Aux Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved0 [31:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_MASK   0xfffffc00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_SHIFT  10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_cs [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_MASK       0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_SHIFT      7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_ad [06:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_MASK       0x00000070
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_SHIFT      4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_odt [03:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_MASK      0x0000000e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_SHIFT     1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: override [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_CTL - Address & Control coarse VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BIT_CTL - Address & Control fine VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_SHIFT  31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved0 [30:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ffffe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: rxenb [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_MASK  0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved1 [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_SHIFT 7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_reb [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ZQ_PVT_COMP_CTL - PVT Compensation control and status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: update_mode [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_done [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_done [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_done [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: auto_sample_en [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_MASK 0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_en [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_ovr_en [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_ovr_en [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_comp [17:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_MASK 0x00038000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_comp [14:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_MASK 0x00007000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [11:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_MASK 0x00000e00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [08:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_MASK 0x000001c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: auto_oeb [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a15 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_MASK  0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a14 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_MASK  0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a13 [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_MASK  0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_aux [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_MASK  0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: half_strength [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_MASK     0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_SHIFT    2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_MASK  0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_MASK     0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_SHIFT    0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_DEFAULT  0x00000000
+
+/***************************************************************************
+ *VDL_RD_DATA_DLY_STATUS - PHY Auto Init rd_data_dly result register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_SHIFT 12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: auto_init_state [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_MASK 0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_max [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_min [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_DEFAULT 0x00000007
+
+/***************************************************************************
+ *VDL_CALIBRATE - PHY VDL calibration control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_MASK 0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: single_cycle [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_single_cycle_MASK 0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_single_cycle_SHIFT 29
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_single_cycle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: use_straps [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: auto_init [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: skip_rst [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_MASK  0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_SHIFT 26
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: exit_in_sr [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_dly_cal [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_refresh [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_wr_dq [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: dq0_only [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_MASK  0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_mr_mpr [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_cal [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_MASK   0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_SHIFT  19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_en_cal [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_clocks [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_pair [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_steps [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_auto [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_ftm [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_phybist [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_byte [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_clocks [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_test [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_always [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_once [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_fast [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CALIB_STATUS - PHY VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_MASK 0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_fail [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_MASK 0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_SHIFT 29
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_done [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_rd_data_dly_error [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_read_en_error [26:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_MASK 0x07800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_error [22:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_MASK 0x00780000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_sel [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_total [11:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_MASK 0x00000ffc
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VDL_DQ_CALIB_STATUS - PHY DQ VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_total [25:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_MASK 0x03ff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_clocks [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_mode [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_WR_CHAN_CALIB_STATUS - PHY Write Channel VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_RD_EN_CALIB_STATUS - PHY Read Enable VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: low_vtt [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: high_vtt [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: error_reset [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_ctl_idle [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cs_idle [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cke_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error [18:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_MASK 0x0007fff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_low [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_high [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ready [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_DEFAULT 0x00ffffff
+
+/***************************************************************************
+ *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_DEFAULT 0x0003ffff
+
+/***************************************************************************
+ *VREF_DAC_CONTROL - VREF DAC Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK1_GT_INT [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK0_GT_INT [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_GT_INT [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: EXT_GT_INT [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_TESTOUT_MUX_CTL [16:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_MASK 0x00018000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TEST [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_MASK   0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_SHIFT  14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_MASK   0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_SHIFT  13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_MASK   0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_SHIFT  12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_MASK   0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_SHIFT  6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_DEFAULT 0x00000020
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_MASK   0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_SHIFT  0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_DEFAULT 0x00000020
+
+/***************************************************************************
+ *PHYBIST_CNTRL - PhyBist Control Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_error_sel [13:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_MASK 0x00003f00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved1 [07:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_MASK 0x000000e0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_SHIFT 5
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: bench_mode [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_dat_error [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_ctl_error [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: int_loopback [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHYBIST_SEED - PhyBist Seed Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_SEED :: seed [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_MASK       0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_DEFAULT    0x250e4af6
+
+/***************************************************************************
+ *PHYBIST_STATUS - PhyBist General Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_pass [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_pass [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_SHIFT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_done [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_done [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: ctl_errors [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_DQ_STATUS - PhyBist Per-Bit DQ Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_STATUS :: dat_errors [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_MASK 0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_MISC_STATUS - PhyBist Per-Bit DM and CK Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: ck_errors [07:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_MASK 0x000000f0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: dm_errors [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_SHIFT 0
+
+/***************************************************************************
+ *COMMAND_REG - DRAM Command Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_MASK   0xe0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_SHIFT  29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: mpr_mode [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_mpr_mode_MASK    0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_mpr_mode_SHIFT   28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_mpr_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved1 [27:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved1_MASK   0x0e000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved1_SHIFT  25
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: aux [24:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_MASK         0x01c00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_SHIFT        22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: we [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_MASK          0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_SHIFT         21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_DEFAULT       0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: cas [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_MASK         0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_SHIFT        20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ras [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_MASK         0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_SHIFT        19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ba [18:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_MASK          0x00070000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_SHIFT         16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_DEFAULT       0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_MASK          0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_DEFAULT       0x00000000
+
+/***************************************************************************
+ *MODE_REG0 - Mode Register 0
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG1 - Mode Register 1
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG2 - Mode Register 2
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG3 - Mode Register 3
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STANDBY_CONTROL - Standby Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_ready [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_exit_pin_en [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_active [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: armed [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_MASK   0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_SHIFT  15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: warmstart [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_ldo_volts [13:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_MASK 0x00003000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_skip_mrs [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_rst_n [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_cke [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: ldo_volts [08:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_MASK 0x00000180
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_DEFAULT 0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: skip_mrs [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: rst_n [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_MASK   0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_SHIFT  5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: cke [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_MASK     0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_SHIFT    4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_CONTROL - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: reserved0 [31:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_MASK 0xf0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_MASK       0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_SHIFT      16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_MASK  0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_MASK 0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_MASK     0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_SHIFT    12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_MASK      0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_SHIFT     11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_MASK      0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_SHIFT     8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_CONTROL2 - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_MASK     0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_SHIFT    20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_MASK       0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_SHIFT      17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_MASK       0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_SHIFT      12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_MASK      0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_SHIFT     7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_MASK       0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_DEFAULT    0x00000000
+
+/***************************************************************************
+ *STRAP_STATUS - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_MASK  0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_reg [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_MASK   0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_SHIFT  29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_memc [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_MASK  0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_MASK        0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_SHIFT       16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_MASK   0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_SHIFT  14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_MASK      0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_SHIFT     12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_MASK       0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_SHIFT      11
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_SHIFT 10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_MASK       0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_SHIFT      8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_MASK  0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_SHIFT 0
+
+/***************************************************************************
+ *STRAP_STATUS2 - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_MASK      0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_SHIFT     20
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_MASK        0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_SHIFT       17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_MASK        0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_SHIFT       12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_MASK       0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_SHIFT      7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_MASK        0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_SHIFT       0
+
+/***************************************************************************
+ *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl1 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl0 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl1 [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl0 [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DATAPATH_LOOPBACK - Datapth Loopback control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: xor_dm_rd_en [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: use_addr_ctl [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_ddr40_phy_word_lane_0_0.h b/include/linux/brcmstb/7362a0/bchp_ddr40_phy_word_lane_0_0.h
new file mode 100644
index 0000000..c7800bb
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_ddr40_phy_word_lane_0_0.h
@@ -0,0 +1,3334 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_ddr40_phy_word_lane_0_0.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:44a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_0_0 - DDR40 DDR40 word lane #0 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN 0x003b6200 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W 0x003b6204 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P 0x003b6208 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N 0x003b620c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W 0x003b6210 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W 0x003b6214 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W 0x003b6218 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W 0x003b621c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W 0x003b6220 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W 0x003b6224 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W 0x003b6228 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W 0x003b622c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W 0x003b6230 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003b6234 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003b6238 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003b623c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003b6240 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003b6244 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003b6248 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003b624c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003b6250 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003b6254 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003b6258 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003b625c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003b6260 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003b6264 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003b6268 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003b626c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003b6270 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003b6274 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W 0x003b62a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P 0x003b62a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N 0x003b62ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W 0x003b62b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W 0x003b62b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W 0x003b62b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W 0x003b62bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W 0x003b62c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W 0x003b62c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W 0x003b62c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W 0x003b62cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W 0x003b62d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003b62d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003b62d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003b62dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003b62e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003b62e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003b62e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003b62ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003b62f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003b62f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003b62f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003b62fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003b6300 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003b6304 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003b6308 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003b630c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003b6310 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003b6314 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x003b6328 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x003b632c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003b6330 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003b6334 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W 0x003b6338 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003b633c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x003b6348 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x003b634c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003b6350 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003b6354 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W 0x003b6358 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003b635c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY 0x003b6360 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL 0x003b6364 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0 0x003b6370 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1 0x003b6374 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2 0x003b6378 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3 0x003b637c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0 0x003b6380 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1 0x003b6384 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2 0x003b6388 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3 0x003b638c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS 0x003b6390 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR 0x003b6394 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL 0x003b63a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL 0x003b63a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE 0x003b63a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE 0x003b63ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ 0x003b63b0 /* PHYBIST mode VDL step select adjustment register */
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_RD_EN - Read Enable Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_DATA_DLY - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_MASK  0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: rd_data_dly [02:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_MASK 0x00000007
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_DEFAULT 0x00000001
+
+/***************************************************************************
+ *READ_CONTROL - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_MASK   0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_SHIFT  3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_enable [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_te_adj [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_le_adj [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status1 [07:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_MASK 0x000000f0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status0 [03:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_MASK 0x0000000f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: clear [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_MASK    0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_SHIFT   31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_SHIFT 24
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_MASK 0x00c00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_SHIFT 22
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_MASK 0x00300000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_SHIFT 20
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00080000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 19
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00040000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_SHIFT 18
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_MASK  0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_MASK  0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00008000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 15
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00004000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 14
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00002000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 13
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00001000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 12
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_MASK 0x00000008
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_MASK  0xfffff000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_SHIFT 12
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: no_dqs_rd [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_MASK  0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_MASK    0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_SHIFT   6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_MASK      0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_SHIFT     2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_DEFAULT   0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_MASK   0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_SHIFT  1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_MASK      0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_SHIFT     0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_DEFAULT   0x00000000
+
+/***************************************************************************
+ *CLOCK_PAD_DISABLE - Clock pad disable register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffc
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_SHIFT 2
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: long [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_MASK    0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_SHIFT   1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: mode [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHYBIST_VDL_ADJ - PHYBIST mode VDL step select adjustment register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_SHIFT 29
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq1_vdl_adj [28:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_MASK 0x1f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved1 [23:21] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_MASK 0x00e00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_SHIFT 21
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq0_vdl_adj [20:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_MASK 0x001f0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved2 [15:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_MASK 0x0000e000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_SHIFT 13
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs1_vdl_adj [12:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_MASK 0x00001f00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved3 [07:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_MASK 0x000000e0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_SHIFT 5
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs0_vdl_adj [04:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_MASK 0x0000001f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_ebi.h b/include/linux/brcmstb/7362a0/bchp_ebi.h
new file mode 100644
index 0000000..ef241e7
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_ebi.h
@@ -0,0 +1,1472 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_ebi.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:47a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EBI_H__
+#define BCHP_EBI_H__
+
+/***************************************************************************
+ *EBI - EBI Registers
+ ***************************************************************************/
+#define BCHP_EBI_CS_BASE_0                       0x00410800 /* EBI CS Base 0 Register */
+#define BCHP_EBI_CS_CONFIG_0                     0x00410804 /* EBI CS Config 0 Register */
+#define BCHP_EBI_CS_BASE_1                       0x00410808 /* EBI CS Base 1 Register */
+#define BCHP_EBI_CS_CONFIG_1                     0x0041080c /* EBI CS Config 1 Register */
+#define BCHP_EBI_CS_BASE_2                       0x00410810 /* EBI CS Base 2 Register */
+#define BCHP_EBI_CS_CONFIG_2                     0x00410814 /* EBI CS Config 2 Register */
+#define BCHP_EBI_CS_BASE_3                       0x00410818 /* EBI CS Base 3 Register */
+#define BCHP_EBI_CS_CONFIG_3                     0x0041081c /* EBI CS Config 3 Register */
+#define BCHP_EBI_CS_BASE_4                       0x00410820 /* EBI CS Base 4 Register */
+#define BCHP_EBI_CS_CONFIG_4                     0x00410824 /* EBI CS Config 4 Register */
+#define BCHP_EBI_BURST_CFG_0                     0x00410840 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_1                     0x00410844 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_2                     0x00410848 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_3                     0x0041084c /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_4                     0x00410850 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_ECR                             0x00410900 /* EBI Configuration Register */
+#define BCHP_EBI_CS_TRISTATE_CFG                 0x00410918 /* EBI CS Tristate Configuration Register */
+#define BCHP_EBI_TA_CFG                          0x0041091c /* EBI TA Configuration Register */
+#define BCHP_EBI_CS_SPI_SELECT                   0x00410920 /* SPI CS Select */
+#define BCHP_EBI_ARRAY_ADDRESS                   0x004109f0 /* EBI Data Array Address */
+
+/***************************************************************************
+ *CS_BASE_0 - EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_0 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_0_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT                         13
+
+/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_0_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_0 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_0_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_0_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_0 - EBI CS Config 0 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_0_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT                       0x00000001
+
+/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_0_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_0_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_0_le_SHIFT                              10
+
+/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_0_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_0_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT                       4
+
+/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_0_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT                        0x00000001
+
+/***************************************************************************
+ *CS_BASE_1 - EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_1 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_1_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_1_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_1 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_1_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_1_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_1_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_1 - EBI CS Config 1 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_1_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_1_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_1_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_1_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_1_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_1_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_1_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_2 - EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_2 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_2_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_2_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_2 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_2_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_2_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_2_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_2 - EBI CS Config 2 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_2_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_2_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_2_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_2_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_2_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_2_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_2_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_3 - EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_3 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_3_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_3_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_3 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_3_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_3_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_3_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_3 - EBI CS Config 3 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_3_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_3_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_3_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_3_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_3_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_3_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_3_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_4 - EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_4 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_4_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_4_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_4 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_4_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_4_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_4_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_4 - EBI CS Config 4 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_4_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_4_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_4_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_4_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_4_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_4_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_4_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_0_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_0_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_0 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_0_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_0_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_0_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_0_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_0_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_1_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_1_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_1 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_1_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_1_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_1_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_1_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_1_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_2_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_2_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_2 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_2_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_2_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_2_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_2_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_2_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_3_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_3_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_3 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_3_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_3_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_3_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_3_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_3_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_4_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_4_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_4 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_4_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_4_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_4_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_4_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_4_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *ECR - EBI Configuration Register
+ ***************************************************************************/
+/* EBI :: ECR :: reserved0 [31:28] */
+#define BCHP_EBI_ECR_reserved0_MASK                                0xf0000000
+#define BCHP_EBI_ECR_reserved0_SHIFT                               28
+
+/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK                            0x08000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT                           27
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT                         0x00000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only  1
+
+/* EBI :: ECR :: reserved1 [26:26] */
+#define BCHP_EBI_ECR_reserved1_MASK                                0x04000000
+#define BCHP_EBI_ECR_reserved1_SHIFT                               26
+
+/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK                          0x02000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT                         25
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT                       0x00000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10         0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00         1
+
+/* EBI :: ECR :: reserved2 [24:11] */
+#define BCHP_EBI_ECR_reserved2_MASK                                0x01fff800
+#define BCHP_EBI_ECR_reserved2_SHIFT                               11
+
+/* EBI :: ECR :: timeout_count [10:00] */
+#define BCHP_EBI_ECR_timeout_count_MASK                            0x000007ff
+#define BCHP_EBI_ECR_timeout_count_SHIFT                           0
+#define BCHP_EBI_ECR_timeout_count_DEFAULT                         0x00000400
+
+/***************************************************************************
+ *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
+ ***************************************************************************/
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK             0x80000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT            31
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK             0x40000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT            30
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK             0x20000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT            29
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK             0x10000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT            28
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK            0x08000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT           27
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK            0x04000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT           26
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK         0x02000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT        25
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK         0x01000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT        24
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:05] */
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK                    0x00ffffe0
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT                   5
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK             0x00000010
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT            4
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK             0x00000008
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT            3
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK             0x00000004
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT            2
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK             0x00000002
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT            1
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK             0x00000001
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT            0
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TA_CFG - EBI TA Configuration Register
+ ***************************************************************************/
+/* EBI :: TA_CFG :: reserved0 [31:04] */
+#define BCHP_EBI_TA_CFG_reserved0_MASK                             0xfffffff0
+#define BCHP_EBI_TA_CFG_reserved0_SHIFT                            4
+
+/* EBI :: TA_CFG :: use_ta3 [03:03] */
+#define BCHP_EBI_TA_CFG_use_ta3_MASK                               0x00000008
+#define BCHP_EBI_TA_CFG_use_ta3_SHIFT                              3
+#define BCHP_EBI_TA_CFG_use_ta3_DEFAULT                            0x00000001
+
+/* EBI :: TA_CFG :: use_ta2 [02:02] */
+#define BCHP_EBI_TA_CFG_use_ta2_MASK                               0x00000004
+#define BCHP_EBI_TA_CFG_use_ta2_SHIFT                              2
+#define BCHP_EBI_TA_CFG_use_ta2_DEFAULT                            0x00000000
+
+/* EBI :: TA_CFG :: use_ta1 [01:01] */
+#define BCHP_EBI_TA_CFG_use_ta1_MASK                               0x00000002
+#define BCHP_EBI_TA_CFG_use_ta1_SHIFT                              1
+#define BCHP_EBI_TA_CFG_use_ta1_DEFAULT                            0x00000001
+
+/* EBI :: TA_CFG :: reserved1 [00:00] */
+#define BCHP_EBI_TA_CFG_reserved1_MASK                             0x00000001
+#define BCHP_EBI_TA_CFG_reserved1_SHIFT                            0
+
+/***************************************************************************
+ *CS_SPI_SELECT - SPI CS Select
+ ***************************************************************************/
+/* EBI :: CS_SPI_SELECT :: reserved0 [31:16] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK                      0xffff0000
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT                     16
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_7_USES_SPI [15:15] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_MASK              0x00008000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_SHIFT             15
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK              0x00004000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT             14
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK              0x00002000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT             13
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK              0x00001000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT             12
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK              0x00000800
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT             11
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK              0x00000400
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT             10
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK              0x00000200
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT             9
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK              0x00000100
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT             8
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_7_SEL [07:07] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_MASK               0x00000080
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_SHIFT              7
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK               0x00000040
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT              6
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK               0x00000020
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT              5
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK               0x00000010
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT              4
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK               0x00000008
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT              3
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK               0x00000004
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT              2
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK               0x00000002
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT              1
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK               0x00000001
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT              0
+
+/***************************************************************************
+ *ARRAY_ADDRESS - EBI Data Array Address
+ ***************************************************************************/
+/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK                        0xfffffe00
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT                       9
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT                     0x00000000
+
+/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK                      0x000001f8
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT                     3
+
+/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK                         0x00000007
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT                        0
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE                            0x00410a00
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_START                           0
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_END                             127
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE                    32
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+/* EBI :: DATA_ARRAYi :: WORD [31:00] */
+#define BCHP_EBI_DATA_ARRAYi_WORD_MASK                             0xffffffff
+#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT                            0
+
+
+#endif /* #ifndef BCHP_EBI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_hif_cpu_intr1.h b/include/linux/brcmstb/7362a0/bchp_hif_cpu_intr1.h
new file mode 100644
index 0000000..d2b8491
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_hif_cpu_intr1.h
@@ -0,0 +1,2019 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_hif_cpu_intr1.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:55a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_INTR1_H__
+#define BCHP_HIF_CPU_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_INTR1 - HIF CPU Thread Processor 0 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS        0x00411400 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS        0x00411404 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS        0x00411408 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS   0x0041140c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS   0x00411410 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS   0x00411414 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET      0x00411418 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET      0x0041141c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET      0x00411420 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR    0x00411424 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR    0x00411428 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR    0x0041142c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK    0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT   31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK        0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT       30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK    0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT   29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_MASK       0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_SHIFT      28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_DEFAULT    0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK  0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK  0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_MASK        0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_SHIFT       23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK     0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT    7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK     0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT    6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK     0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT    5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK     0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT    4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK     0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT    3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK     0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT    2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK        0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT       1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK        0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT       0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK    0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT   28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK    0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT   27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK     0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT    26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK   0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT  24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK    0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT   22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_MASK   0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_SHIFT  20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK     0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT    18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK    0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT   17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK        0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT       16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_MASK   0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_SHIFT  14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_MASK   0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_SHIFT  13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_MASK   0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_SHIFT  12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_MASK   0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_SHIFT  11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_MASK  0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_MASK  0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK      0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT     5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT   0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK    0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT   4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_MASK     0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_SHIFT    2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_MASK       0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_SHIFT      1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_DEFAULT    0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_MASK       0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_SHIFT      0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_DEFAULT    0x00000000
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_24_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_24_CPU_INTR_MASK   0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_24_CPU_INTR_SHIFT  31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_24_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_23_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_23_CPU_INTR_MASK   0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_23_CPU_INTR_SHIFT  30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_23_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_22_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_22_CPU_INTR_MASK   0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_22_CPU_INTR_SHIFT  29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_22_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_21_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_MASK   0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_SHIFT  28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_20_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_20_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_20_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_20_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_19_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_19_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_19_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_19_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_18_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_MASK   0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_SHIFT  25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_17_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_MASK   0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_SHIFT  24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: RFM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_RFM_CPU_INTR_MASK        0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_RFM_CPU_INTR_SHIFT       23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_RFM_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SATA_AHCI_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_AHCI_CPU_INTR_MASK  0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_AHCI_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SATA_GRB_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_GRB_CPU_INTR_MASK   0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_GRB_CPU_INTR_SHIFT  21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_MASK     0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_SHIFT    20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SDIO0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_MASK    0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_SHIFT   18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK    0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT   16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK    0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT   15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK   0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT  14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK    0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT   12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK     0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT    11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK        0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT       10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_MASK   0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_SHIFT  9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_MASK   0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_SHIFT  8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK   0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT  30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_MASK   0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_SHIFT  23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK   0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT  16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_24_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_24_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_24_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_24_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_23_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_23_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_23_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_23_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_22_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_22_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_22_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_22_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_21_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_20_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_20_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_20_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_20_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_19_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_19_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_19_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_19_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_18_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_17_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: RFM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_RFM_CPU_INTR_MASK   0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_RFM_CPU_INTR_SHIFT  23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_RFM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SATA_AHCI_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_AHCI_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SATA_GRB_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_GRB_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_GRB_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SDIO0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK   0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT  10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK      0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT     30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_MASK     0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_SHIFT    28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_DEFAULT  0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_MASK      0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_SHIFT     23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK      0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT     1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK      0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT     0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK  0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK  0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK   0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT  18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK  0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK      0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT     16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK    0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT   5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK  0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_MASK     0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_SHIFT    1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_DEFAULT  0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_MASK     0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_SHIFT    0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_DEFAULT  0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_24_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_24_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_24_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_24_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_23_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_23_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_23_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_23_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_22_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_22_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_22_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_22_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_21_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_20_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_20_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_20_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_20_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_19_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_19_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_19_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_19_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_18_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_17_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: RFM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_RFM_CPU_INTR_MASK      0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_RFM_CPU_INTR_SHIFT     23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_RFM_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SATA_AHCI_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_AHCI_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_AHCI_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SATA_GRB_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_GRB_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_GRB_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_MASK   0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_SHIFT  20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SDIO0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_MASK  0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK  0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK  0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK  0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK   0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT  11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK      0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT     10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_MASK   0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_SHIFT  28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK    0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT   16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK  0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_24_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_24_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_24_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_24_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_23_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_23_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_23_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_23_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_22_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_22_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_22_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_22_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_21_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_20_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_20_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_20_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_20_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_19_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_19_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_19_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_19_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_18_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_17_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: RFM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_RFM_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_RFM_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_RFM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SATA_AHCI_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_AHCI_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_AHCI_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SATA_GRB_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_GRB_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_GRB_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SDIO0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK    0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT   10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+#endif /* #ifndef BCHP_HIF_CPU_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_hif_intr2.h b/include/linux/brcmstb/7362a0/bchp_hif_intr2.h
new file mode 100644
index 0000000..89a2bf1
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_hif_intr2.h
@@ -0,0 +1,975 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_hif_intr2.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:56a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_INTR2_H__
+#define BCHP_HIF_INTR2_H__
+
+/***************************************************************************
+ *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_INTR2_CPU_STATUS                0x00411000 /* CPU interrupt Status Register */
+#define BCHP_HIF_INTR2_CPU_SET                   0x00411004 /* CPU interrupt Set Register */
+#define BCHP_HIF_INTR2_CPU_CLEAR                 0x00411008 /* CPU interrupt Clear Register */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS           0x0041100c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_CPU_MASK_SET              0x00411010 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR            0x00411014 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_INTR2_PCI_STATUS                0x00411018 /* PCI interrupt Status Register */
+#define BCHP_HIF_INTR2_PCI_SET                   0x0041101c /* PCI interrupt Set Register */
+#define BCHP_HIF_INTR2_PCI_CLEAR                 0x00411020 /* PCI interrupt Clear Register */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS           0x00411024 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_PCI_MASK_SET              0x00411028 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR            0x0041102c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK                   0x0000fffe
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_MASK              0x00080000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_SHIFT             19
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK                      0x0000fffe
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: CPU_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_MASK            0x00080000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_SHIFT           19
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK                    0x0000fffe
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK              0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_MASK         0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_SHIFT        19
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK                 0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_MASK       0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_SHIFT      19
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK               0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK                   0x0000fffe
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_MASK              0x00080000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_SHIFT             19
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK                      0x0000fffe
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: PCI_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_MASK            0x00080000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_SHIFT           19
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK                    0x0000fffe
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK              0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_MASK         0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_SHIFT        19
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK                 0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_MASK       0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_SHIFT      19
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK               0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  0x00000001
+
+#endif /* #ifndef BCHP_HIF_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_hif_mspi.h b/include/linux/brcmstb/7362a0/bchp_hif_mspi.h
new file mode 100644
index 0000000..65e2169
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_hif_mspi.h
@@ -0,0 +1,1214 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_hif_mspi.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:56a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_MSPI_H__
+#define BCHP_HIF_MSPI_H__
+
+/***************************************************************************
+ *HIF_MSPI - Public MSPI Registers
+ ***************************************************************************/
+#define BCHP_HIF_MSPI_SPCR0_LSB                  0x00413200 /* SPCR0_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR0_MSB                  0x00413204 /* SPCR0_MSB Register */
+#define BCHP_HIF_MSPI_SPCR1_LSB                  0x00413208 /* SPCR1_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR1_MSB                  0x0041320c /* SPCR1_MSB REGISTER */
+#define BCHP_HIF_MSPI_NEWQP                      0x00413210 /* NEWQP REGISTER */
+#define BCHP_HIF_MSPI_ENDQP                      0x00413214 /* ENDQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR2                      0x00413218 /* SPCR2 REGISTER */
+#define BCHP_HIF_MSPI_MSPI_STATUS                0x00413220 /* MSPI STATUS REGISTER */
+#define BCHP_HIF_MSPI_CPTQP                      0x00413224 /* CPTQP REGISTER */
+#define BCHP_HIF_MSPI_TXRAM00                    0x00413240 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM01                    0x00413244 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM02                    0x00413248 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM03                    0x0041324c /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM04                    0x00413250 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM05                    0x00413254 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM06                    0x00413258 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM07                    0x0041325c /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM08                    0x00413260 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM09                    0x00413264 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM10                    0x00413268 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM11                    0x0041326c /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM12                    0x00413270 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM13                    0x00413274 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM14                    0x00413278 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM15                    0x0041327c /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM16                    0x00413280 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM17                    0x00413284 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM18                    0x00413288 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM19                    0x0041328c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM20                    0x00413290 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM21                    0x00413294 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM22                    0x00413298 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM23                    0x0041329c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM24                    0x004132a0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM25                    0x004132a4 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM26                    0x004132a8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM27                    0x004132ac /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM28                    0x004132b0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM29                    0x004132b4 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM30                    0x004132b8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_TXRAM31                    0x004132bc /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM00                    0x004132c0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM01                    0x004132c4 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM02                    0x004132c8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM03                    0x004132cc /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM04                    0x004132d0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM05                    0x004132d4 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM06                    0x004132d8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM07                    0x004132dc /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM08                    0x004132e0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM09                    0x004132e4 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM10                    0x004132e8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM11                    0x004132ec /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM12                    0x004132f0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM13                    0x004132f4 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM14                    0x004132f8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM15                    0x004132fc /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM16                    0x00413300 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM17                    0x00413304 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM18                    0x00413308 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM19                    0x0041330c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM20                    0x00413310 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM21                    0x00413314 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM22                    0x00413318 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM23                    0x0041331c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM24                    0x00413320 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM25                    0x00413324 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM26                    0x00413328 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM27                    0x0041332c /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM28                    0x00413330 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM29                    0x00413334 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM30                    0x00413338 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM31                    0x0041333c /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_CDRAM00                    0x00413340 /* 8-bit command (queue pointer = 0) */
+#define BCHP_HIF_MSPI_CDRAM01                    0x00413344 /* 8-bit command (queue pointer = 1) */
+#define BCHP_HIF_MSPI_CDRAM02                    0x00413348 /* 8-bit command (queue pointer = 2) */
+#define BCHP_HIF_MSPI_CDRAM03                    0x0041334c /* 8-bit command (queue pointer = 3) */
+#define BCHP_HIF_MSPI_CDRAM04                    0x00413350 /* 8-bit command (queue pointer = 4) */
+#define BCHP_HIF_MSPI_CDRAM05                    0x00413354 /* 8-bit command (queue pointer = 5) */
+#define BCHP_HIF_MSPI_CDRAM06                    0x00413358 /* 8-bit command (queue pointer = 6) */
+#define BCHP_HIF_MSPI_CDRAM07                    0x0041335c /* 8-bit command (queue pointer = 7) */
+#define BCHP_HIF_MSPI_CDRAM08                    0x00413360 /* 8-bit command (queue pointer = 8) */
+#define BCHP_HIF_MSPI_CDRAM09                    0x00413364 /* 8-bit command (queue pointer = 9) */
+#define BCHP_HIF_MSPI_CDRAM10                    0x00413368 /* 8-bit command (queue pointer = a) */
+#define BCHP_HIF_MSPI_CDRAM11                    0x0041336c /* 8-bit command (queue pointer = b) */
+#define BCHP_HIF_MSPI_CDRAM12                    0x00413370 /* 8-bit command (queue pointer = c) */
+#define BCHP_HIF_MSPI_CDRAM13                    0x00413374 /* 8-bit command (queue pointer = d) */
+#define BCHP_HIF_MSPI_CDRAM14                    0x00413378 /* 8-bit command (queue pointer = e) */
+#define BCHP_HIF_MSPI_CDRAM15                    0x0041337c /* 8-bit command (queue pointer = f) */
+#define BCHP_HIF_MSPI_WRITE_LOCK                 0x00413380 /* Control bit to lock group of write commands */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN          0x00413384 /* Debug bit to mask the generation of flush signals from Mspi */
+
+/***************************************************************************
+ *SPCR0_LSB - SPCR0_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK                          0x000000ff
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR0_MSB - SPCR0_MSB Register
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_MSB :: MSTR [07:07] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_MASK                          0x00000080
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_SHIFT                         7
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_DEFAULT                       0x00000001
+
+/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [06:06] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK               0x00000040
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT              6
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT            0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: BitS [05:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_MASK                          0x0000003c
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_SHIFT                         2
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_DEFAULT                       0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK                          0x00000002
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT                         1
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT                       0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK                          0x00000001
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR1_LSB - SPCR1_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT                          0
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *SPCR1_MSB - SPCR1_MSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK                        0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT                       0
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *NEWQP - NEWQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: NEWQP :: newqp [03:00] */
+#define BCHP_HIF_MSPI_NEWQP_newqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT                            0
+#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *ENDQP - ENDQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: ENDQP :: endqp [03:00] */
+#define BCHP_HIF_MSPI_ENDQP_endqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT                            0
+#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *SPCR2 - SPCR2 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK                         0xffffff00
+#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT                        8
+
+/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK                    0x00000080
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT                   7
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT                 0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spe [06:06] */
+#define BCHP_HIF_MSPI_SPCR2_spe_MASK                               0x00000040
+#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT                              6
+#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
+#define BCHP_HIF_MSPI_SPCR2_spifie_MASK                            0x00000020
+#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT                           5
+#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT                         0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wren [04:04] */
+#define BCHP_HIF_MSPI_SPCR2_wren_MASK                              0x00000010
+#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT                             4
+#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
+#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK                              0x00000008
+#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT                             3
+#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
+#define BCHP_HIF_MSPI_SPCR2_loopq_MASK                             0x00000004
+#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT                            2
+#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT                          0x00000000
+
+/* HIF_MSPI :: SPCR2 :: hie [01:01] */
+#define BCHP_HIF_MSPI_SPCR2_hie_MASK                               0x00000002
+#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT                              1
+#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: halt [00:00] */
+#define BCHP_HIF_MSPI_SPCR2_halt_MASK                              0x00000001
+#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT                             0
+#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *MSPI_STATUS - MSPI STATUS REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK                   0xfffffffc
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT                  2
+
+/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK                       0x00000002
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT                      1
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT                    0x00000000
+
+/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK                        0x00000001
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT                       0
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *CPTQP - CPTQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
+#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT                            0
+#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *TXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM00_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM01_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM02_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM03_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM04_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM05_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM06_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM07_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM08_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM09_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM10_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM11_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM12_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM13_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM14_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM15_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM16_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM17_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM18_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM19_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM20_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM21_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM22_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM23_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM24_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM25_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM26_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM27_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM28_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM29_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM30_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM31_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM00 - 8-bit command (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM00 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM01 - 8-bit command (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM01 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM02 - 8-bit command (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM02 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM03 - 8-bit command (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM03 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM04 - 8-bit command (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM04 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM05 - 8-bit command (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM05 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM06 - 8-bit command (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM06 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM07 - 8-bit command (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM07 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM08 - 8-bit command (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM08 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM09 - 8-bit command (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM09 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM10 - 8-bit command (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM10 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM11 - 8-bit command (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM11 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM12 - 8-bit command (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM12 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM13 - 8-bit command (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM13 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM14 - 8-bit command (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM14 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM15 - 8-bit command (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM15 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT                          0
+
+/***************************************************************************
+ *WRITE_LOCK - Control bit to lock group of write commands
+ ***************************************************************************/
+/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK                    0xfffffffe
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT                   1
+
+/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK                    0x00000001
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT                   0
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
+ ***************************************************************************/
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK             0xfffffffe
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT            1
+
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK       0x00000001
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT      0
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT    0x00000000
+
+#endif /* #ifndef BCHP_HIF_MSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/7362a0/bchp_hif_spi_intr2.h
new file mode 100644
index 0000000..dabf442
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_hif_spi_intr2.h
@@ -0,0 +1,567 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_hif_spi_intr2.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:56a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_SPI_INTR2_H__
+#define BCHP_HIF_SPI_INTR2_H__
+
+/***************************************************************************
+ *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
+ ***************************************************************************/
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS            0x00411d00 /* CPU interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_SET               0x00411d04 /* CPU interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR             0x00411d08 /* CPU interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS       0x00411d0c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET          0x00411d10 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR        0x00411d14 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS            0x00411d18 /* PCI interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_SET               0x00411d1c /* PCI interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR             0x00411d20 /* PCI interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS       0x00411d24 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET          0x00411d28 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR        0x00411d2c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_hif_top_ctrl.h b/include/linux/brcmstb/7362a0/bchp_hif_top_ctrl.h
new file mode 100644
index 0000000..bff221e
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_hif_top_ctrl.h
@@ -0,0 +1,527 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 24 17:25:42 2013
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_TOP_CTRL_H__
+#define BCHP_HIF_TOP_CTRL_H__
+
+/***************************************************************************
+ *HIF_TOP_CTRL - HIF Top Control Registers
+ ***************************************************************************/
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2               0x00412418 /* HIF Power Management Control Register:used to control SDIO_0 (CARD) */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL          0x00412400 /* External IRQ Active Level Control Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0               0x00412404 /* HIF Power Management Control0 Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1               0x00412408 /* HIF Power Management Control1 Register */
+#define BCHP_HIF_TOP_CTRL_SCRATCH                0x0041240c /* HIF Scratch Register */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE             0x00412410 /* HIF Decoded Flash Type */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL            0x00412414 /* SPI test port select register */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL               0x0041241c /* HIF HIF_CTRL Register */
+
+/***************************************************************************
+ *PM_CTRL2 - HIF Power Management Control Register:used to control SDIO_0 (CARD)
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved0 [31:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_MASK                  0xff000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_SHIFT                 24
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_MASK 0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_SHIFT 22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_MASK 0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_SHIFT 20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_IN_DRIVE_INACTIVE [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_IN_DRIVE_INACTIVE [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_MASK 0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_SHIFT 16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved1 [15:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_MASK                  0x0000f000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_VOLTAGE_PM_OUT_CTRL [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_LOW    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_HIGH   2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_POWER_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_MASK     0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_SHIFT    8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_DEFAULT  0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_LOW      1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_HIGH     2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_LED_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_MASK       0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_SHIFT      6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_MASK      0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_MASK       0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_SHIFT      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_Tristate   3
+
+/***************************************************************************
+ *EXT_IRQ_LEVEL - External IRQ Active Level Control Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: reserved0 [31:15] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_MASK             0xffff8000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_SHIFT            15
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_14_level [14:14] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_MASK      0x00004000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_SHIFT     14
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_13_level [13:13] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_MASK      0x00002000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_SHIFT     13
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_12_level [12:12] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_MASK      0x00001000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_SHIFT     12
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_11_level [11:11] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_MASK      0x00000800
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_SHIFT     11
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_10_level [10:10] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_MASK      0x00000400
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_SHIFT     10
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_09_level [09:09] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_MASK      0x00000200
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_SHIFT     9
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_08_level [08:08] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_MASK      0x00000100
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_SHIFT     8
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_07_level [07:07] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_MASK      0x00000080
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_SHIFT     7
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_06_level [06:06] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_MASK      0x00000040
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_SHIFT     6
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_05_level [05:05] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_MASK      0x00000020
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_SHIFT     5
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_04_level [04:04] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_MASK      0x00000010
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_03_level [03:03] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_MASK      0x00000008
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_SHIFT     3
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_02_level [02:02] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_MASK      0x00000004
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_SHIFT     2
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_01_level [01:01] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_MASK      0x00000002
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_SHIFT     1
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_00_level [00:00] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_MASK      0x00000001
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_SHIFT     0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_HIGH      1
+
+/***************************************************************************
+ *PM_CTRL0 - HIF Power Management Control0 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_PM_IN_DRIVE_INACTIVE [31:30] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_MASK   0xc0000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_SHIFT  30
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_IN_DRIVE_INACTIVE [29:28] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x30000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 28
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: reserved0 [27:26] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_reserved0_MASK                  0x0c000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_reserved0_SHIFT                 26
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_DATA_PM_OUT_CTRL [25:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_MASK       0x03000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_SHIFT      24
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_ADDR_PM_OUT_CTRL [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_MASK       0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_SHIFT      22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_CTRL_PM_OUT_CTRL [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_MASK       0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_SHIFT      20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_OUT_CTRL [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_MASK      0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_SHIFT     18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_CTRL_PM_OUT_CTRL [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_MASK      0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_SHIFT     16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS7 [15:14] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_MASK            0x0000c000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_SHIFT           14
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS6 [13:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_MASK            0x00003000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_SHIFT           12
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS5 [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_MASK            0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_SHIFT           10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS4 [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_MASK            0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_SHIFT           8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS3 [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_MASK            0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_SHIFT           6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS2 [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_MASK            0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_SHIFT           4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS1 [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_MASK            0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_SHIFT           2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS0 [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_MASK            0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_SHIFT           0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_Tristate        3
+
+/***************************************************************************
+ *PM_CTRL1 - HIF Power Management Control1 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL1 :: reserved0 [31:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_MASK                  0xfffff000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_PM_IN_DRIVE_INACTIVE [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_WPB_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_MASK        0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_SHIFT       8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_DEFAULT     0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_Tristate    3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_HOLDB_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_MASK      0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_SHIFT     6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MISO_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_MASK       0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_SHIFT      4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MOSI_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_MASK        0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_SHIFT       0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_DEFAULT     0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_Tristate    3
+
+/***************************************************************************
+ *SCRATCH - HIF Scratch Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_MASK                 0xffffffff
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_SHIFT                0
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *FLASH_TYPE - HIF Decoded Flash Type
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: FLASH_TYPE :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_MASK                0xfffffff8
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_SHIFT               3
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: InvalidStrap [02:02] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_MASK             0x00000004
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_SHIFT            2
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_DEFAULT          0x00000000
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: FLASH_TYPE [01:00] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_MASK               0x00000003
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SHIFT              0
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_ParallelNOR        0
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_Nand               1
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SerialNOR          2
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_eMMC               3
+
+/***************************************************************************
+ *SPI_DBG_SEL - SPI test port select register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_MASK               0xfffffff8
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_SHIFT              3
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: DISABLE_MSPI_FLUSH [02:02] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_MASK      0x00000004
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_SHIFT     2
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_DEFAULT   0x00000000
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SPI_RBUS_TIMER_EN [01:01] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_MASK       0x00000002
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_SHIFT      1
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_DEFAULT    0x00000000
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SPI_TP_SEL [00:00] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_TP_SEL_MASK              0x00000001
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_TP_SEL_SHIFT             0
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_TP_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *HIF_CTRL - HIF HIF_CTRL Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: HIF_CTRL :: reserved0 [31:01] */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_reserved0_SHIFT                 1
+
+/* HIF_TOP_CTRL :: HIF_CTRL :: ENABLE_FULL_USE_OF_EBI [00:00] */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_MASK     0x00000001
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_SHIFT    0
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_DEFAULT  0x00000000
+
+#endif /* #ifndef BCHP_HIF_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_irq0.h b/include/linux/brcmstb/7362a0/bchp_irq0.h
new file mode 100644
index 0000000..15148a3
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_irq0.h
@@ -0,0 +1,217 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_irq0.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:59a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ0_H__
+#define BCHP_IRQ0_H__
+
+/***************************************************************************
+ *IRQ0 - Level 2 CPU Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ0_IRQEN                          0x00406600 /* Interrupt Enable */
+#define BCHP_IRQ0_IRQSTAT                        0x00406604 /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ0 :: IRQEN :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQEN_reserved0_MASK                             0xf8000000
+#define BCHP_IRQ0_IRQEN_reserved0_SHIFT                            27
+
+/* IRQ0 :: IRQEN :: iicc_irqen [26:26] */
+#define BCHP_IRQ0_IRQEN_iicc_irqen_MASK                            0x04000000
+#define BCHP_IRQ0_IRQEN_iicc_irqen_SHIFT                           26
+#define BCHP_IRQ0_IRQEN_iicc_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: iicb_irqen [25:25] */
+#define BCHP_IRQ0_IRQEN_iicb_irqen_MASK                            0x02000000
+#define BCHP_IRQ0_IRQEN_iicb_irqen_SHIFT                           25
+#define BCHP_IRQ0_IRQEN_iicb_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: iica_irqen [24:24] */
+#define BCHP_IRQ0_IRQEN_iica_irqen_MASK                            0x01000000
+#define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT                           24
+#define BCHP_IRQ0_IRQEN_iica_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQEN_reserved1_MASK                             0x00f80000
+#define BCHP_IRQ0_IRQEN_reserved1_SHIFT                            19
+
+/* IRQ0 :: IRQEN :: uartc_irqen [18:18] */
+#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK                           0x00040000
+#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT                          18
+#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uartb_irqen [17:17] */
+#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK                           0x00020000
+#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT                          17
+#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uarta_irqen [16:16] */
+#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK                           0x00010000
+#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT                          16
+#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQEN_reserved2_MASK                             0x0000fc00
+#define BCHP_IRQ0_IRQEN_reserved2_SHIFT                            10
+
+/* IRQ0 :: IRQEN :: uc_irqen [09:09] */
+#define BCHP_IRQ0_IRQEN_uc_irqen_MASK                              0x00000200
+#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT                             9
+#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQEN_reserved3_MASK                             0x00000180
+#define BCHP_IRQ0_IRQEN_reserved3_SHIFT                            7
+
+/* IRQ0 :: IRQEN :: gio_irqen [06:06] */
+#define BCHP_IRQ0_IRQEN_gio_irqen_MASK                             0x00000040
+#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT                            6
+#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQEN :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQEN_reserved4_MASK                             0x00000020
+#define BCHP_IRQ0_IRQEN_reserved4_SHIFT                            5
+
+/* IRQ0 :: IRQEN :: ua_irqen [04:04] */
+#define BCHP_IRQ0_IRQEN_ua_irqen_MASK                              0x00000010
+#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT                             4
+#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: ub_irqen [03:03] */
+#define BCHP_IRQ0_IRQEN_ub_irqen_MASK                              0x00000008
+#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT                             3
+#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: irb_irqen [02:02] */
+#define BCHP_IRQ0_IRQEN_irb_irqen_MASK                             0x00000004
+#define BCHP_IRQ0_IRQEN_irb_irqen_SHIFT                            2
+#define BCHP_IRQ0_IRQEN_irb_irqen_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQEN :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQEN_reserved5_MASK                             0x00000003
+#define BCHP_IRQ0_IRQEN_reserved5_SHIFT                            0
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ0 :: IRQSTAT :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQSTAT_reserved0_MASK                           0xf8000000
+#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT                          27
+
+/* IRQ0 :: IRQSTAT :: iiccirq [26:26] */
+#define BCHP_IRQ0_IRQSTAT_iiccirq_MASK                             0x04000000
+#define BCHP_IRQ0_IRQSTAT_iiccirq_SHIFT                            26
+#define BCHP_IRQ0_IRQSTAT_iiccirq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: iicbirq [25:25] */
+#define BCHP_IRQ0_IRQSTAT_iicbirq_MASK                             0x02000000
+#define BCHP_IRQ0_IRQSTAT_iicbirq_SHIFT                            25
+#define BCHP_IRQ0_IRQSTAT_iicbirq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: iicairq [24:24] */
+#define BCHP_IRQ0_IRQSTAT_iicairq_MASK                             0x01000000
+#define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT                            24
+#define BCHP_IRQ0_IRQSTAT_iicairq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQSTAT_reserved1_MASK                           0x00f80000
+#define BCHP_IRQ0_IRQSTAT_reserved1_SHIFT                          19
+
+/* IRQ0 :: IRQSTAT :: uartc_irq [18:18] */
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK                           0x00040000
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT                          18
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uartb_irq [17:17] */
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK                           0x00020000
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT                          17
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uarta_irq [16:16] */
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK                           0x00010000
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT                          16
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQSTAT_reserved2_MASK                           0x0000fc00
+#define BCHP_IRQ0_IRQSTAT_reserved2_SHIFT                          10
+
+/* IRQ0 :: IRQSTAT :: ucirq [09:09] */
+#define BCHP_IRQ0_IRQSTAT_ucirq_MASK                               0x00000200
+#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT                              9
+#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQSTAT_reserved3_MASK                           0x00000180
+#define BCHP_IRQ0_IRQSTAT_reserved3_SHIFT                          7
+
+/* IRQ0 :: IRQSTAT :: gioirq [06:06] */
+#define BCHP_IRQ0_IRQSTAT_gioirq_MASK                              0x00000040
+#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT                             6
+#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQSTAT_reserved4_MASK                           0x00000020
+#define BCHP_IRQ0_IRQSTAT_reserved4_SHIFT                          5
+
+/* IRQ0 :: IRQSTAT :: uairq [04:04] */
+#define BCHP_IRQ0_IRQSTAT_uairq_MASK                               0x00000010
+#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT                              4
+#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: ubirq [03:03] */
+#define BCHP_IRQ0_IRQSTAT_ubirq_MASK                               0x00000008
+#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT                              3
+#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: irbirq [02:02] */
+#define BCHP_IRQ0_IRQSTAT_irbirq_MASK                              0x00000004
+#define BCHP_IRQ0_IRQSTAT_irbirq_SHIFT                             2
+#define BCHP_IRQ0_IRQSTAT_irbirq_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQSTAT_reserved5_MASK                           0x00000003
+#define BCHP_IRQ0_IRQSTAT_reserved5_SHIFT                          0
+
+#endif /* #ifndef BCHP_IRQ0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_irq1.h b/include/linux/brcmstb/7362a0/bchp_irq1.h
new file mode 100644
index 0000000..ab0551e
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_irq1.h
@@ -0,0 +1,214 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 24 17:25:43 2013
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ1_H__
+#define BCHP_IRQ1_H__
+
+/***************************************************************************
+ *IRQ1 - Level 2 PCI Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ1_IRQEN                          0x00406640 /* Interrupt Enable */
+#define BCHP_IRQ1_IRQSTAT                        0x00406644 /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ1 :: IRQEN :: reserved0 [31:27] */
+#define BCHP_IRQ1_IRQEN_reserved0_MASK                             0xf8000000
+#define BCHP_IRQ1_IRQEN_reserved0_SHIFT                            27
+
+/* IRQ1 :: IRQEN :: iicc_irqen [26:26] */
+#define BCHP_IRQ1_IRQEN_iicc_irqen_MASK                            0x04000000
+#define BCHP_IRQ1_IRQEN_iicc_irqen_SHIFT                           26
+#define BCHP_IRQ1_IRQEN_iicc_irqen_DEFAULT                         0x00000000
+
+/* IRQ1 :: IRQEN :: iicb_irqen [25:25] */
+#define BCHP_IRQ1_IRQEN_iicb_irqen_MASK                            0x02000000
+#define BCHP_IRQ1_IRQEN_iicb_irqen_SHIFT                           25
+#define BCHP_IRQ1_IRQEN_iicb_irqen_DEFAULT                         0x00000000
+
+/* IRQ1 :: IRQEN :: iica_irqen [24:24] */
+#define BCHP_IRQ1_IRQEN_iica_irqen_MASK                            0x01000000
+#define BCHP_IRQ1_IRQEN_iica_irqen_SHIFT                           24
+#define BCHP_IRQ1_IRQEN_iica_irqen_DEFAULT                         0x00000000
+
+/* IRQ1 :: IRQEN :: reserved1 [23:19] */
+#define BCHP_IRQ1_IRQEN_reserved1_MASK                             0x00f80000
+#define BCHP_IRQ1_IRQEN_reserved1_SHIFT                            19
+
+/* IRQ1 :: IRQEN :: uartc_irqen [18:18] */
+#define BCHP_IRQ1_IRQEN_uartc_irqen_MASK                           0x00040000
+#define BCHP_IRQ1_IRQEN_uartc_irqen_SHIFT                          18
+#define BCHP_IRQ1_IRQEN_uartc_irqen_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQEN :: uartb_irqen [17:17] */
+#define BCHP_IRQ1_IRQEN_uartb_irqen_MASK                           0x00020000
+#define BCHP_IRQ1_IRQEN_uartb_irqen_SHIFT                          17
+#define BCHP_IRQ1_IRQEN_uartb_irqen_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQEN :: uarta_irqen [16:16] */
+#define BCHP_IRQ1_IRQEN_uarta_irqen_MASK                           0x00010000
+#define BCHP_IRQ1_IRQEN_uarta_irqen_SHIFT                          16
+#define BCHP_IRQ1_IRQEN_uarta_irqen_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQEN :: reserved2 [15:10] */
+#define BCHP_IRQ1_IRQEN_reserved2_MASK                             0x0000fc00
+#define BCHP_IRQ1_IRQEN_reserved2_SHIFT                            10
+
+/* IRQ1 :: IRQEN :: uc_irqen [09:09] */
+#define BCHP_IRQ1_IRQEN_uc_irqen_MASK                              0x00000200
+#define BCHP_IRQ1_IRQEN_uc_irqen_SHIFT                             9
+#define BCHP_IRQ1_IRQEN_uc_irqen_DEFAULT                           0x00000000
+
+/* IRQ1 :: IRQEN :: reserved3 [08:07] */
+#define BCHP_IRQ1_IRQEN_reserved3_MASK                             0x00000180
+#define BCHP_IRQ1_IRQEN_reserved3_SHIFT                            7
+
+/* IRQ1 :: IRQEN :: gio_irqen [06:06] */
+#define BCHP_IRQ1_IRQEN_gio_irqen_MASK                             0x00000040
+#define BCHP_IRQ1_IRQEN_gio_irqen_SHIFT                            6
+#define BCHP_IRQ1_IRQEN_gio_irqen_DEFAULT                          0x00000000
+
+/* IRQ1 :: IRQEN :: reserved4 [05:05] */
+#define BCHP_IRQ1_IRQEN_reserved4_MASK                             0x00000020
+#define BCHP_IRQ1_IRQEN_reserved4_SHIFT                            5
+
+/* IRQ1 :: IRQEN :: ua_irqen [04:04] */
+#define BCHP_IRQ1_IRQEN_ua_irqen_MASK                              0x00000010
+#define BCHP_IRQ1_IRQEN_ua_irqen_SHIFT                             4
+#define BCHP_IRQ1_IRQEN_ua_irqen_DEFAULT                           0x00000000
+
+/* IRQ1 :: IRQEN :: ub_irqen [03:03] */
+#define BCHP_IRQ1_IRQEN_ub_irqen_MASK                              0x00000008
+#define BCHP_IRQ1_IRQEN_ub_irqen_SHIFT                             3
+#define BCHP_IRQ1_IRQEN_ub_irqen_DEFAULT                           0x00000000
+
+/* IRQ1 :: IRQEN :: irb_irqen [02:02] */
+#define BCHP_IRQ1_IRQEN_irb_irqen_MASK                             0x00000004
+#define BCHP_IRQ1_IRQEN_irb_irqen_SHIFT                            2
+#define BCHP_IRQ1_IRQEN_irb_irqen_DEFAULT                          0x00000000
+
+/* IRQ1 :: IRQEN :: reserved5 [01:00] */
+#define BCHP_IRQ1_IRQEN_reserved5_MASK                             0x00000003
+#define BCHP_IRQ1_IRQEN_reserved5_SHIFT                            0
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ1 :: IRQSTAT :: reserved0 [31:27] */
+#define BCHP_IRQ1_IRQSTAT_reserved0_MASK                           0xf8000000
+#define BCHP_IRQ1_IRQSTAT_reserved0_SHIFT                          27
+
+/* IRQ1 :: IRQSTAT :: iiccirq [26:26] */
+#define BCHP_IRQ1_IRQSTAT_iiccirq_MASK                             0x04000000
+#define BCHP_IRQ1_IRQSTAT_iiccirq_SHIFT                            26
+#define BCHP_IRQ1_IRQSTAT_iiccirq_DEFAULT                          0x00000000
+
+/* IRQ1 :: IRQSTAT :: iicbirq [25:25] */
+#define BCHP_IRQ1_IRQSTAT_iicbirq_MASK                             0x02000000
+#define BCHP_IRQ1_IRQSTAT_iicbirq_SHIFT                            25
+#define BCHP_IRQ1_IRQSTAT_iicbirq_DEFAULT                          0x00000000
+
+/* IRQ1 :: IRQSTAT :: iicairq [24:24] */
+#define BCHP_IRQ1_IRQSTAT_iicairq_MASK                             0x01000000
+#define BCHP_IRQ1_IRQSTAT_iicairq_SHIFT                            24
+#define BCHP_IRQ1_IRQSTAT_iicairq_DEFAULT                          0x00000000
+
+/* IRQ1 :: IRQSTAT :: reserved1 [23:19] */
+#define BCHP_IRQ1_IRQSTAT_reserved1_MASK                           0x00f80000
+#define BCHP_IRQ1_IRQSTAT_reserved1_SHIFT                          19
+
+/* IRQ1 :: IRQSTAT :: uartc_irq [18:18] */
+#define BCHP_IRQ1_IRQSTAT_uartc_irq_MASK                           0x00040000
+#define BCHP_IRQ1_IRQSTAT_uartc_irq_SHIFT                          18
+#define BCHP_IRQ1_IRQSTAT_uartc_irq_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQSTAT :: uartb_irq [17:17] */
+#define BCHP_IRQ1_IRQSTAT_uartb_irq_MASK                           0x00020000
+#define BCHP_IRQ1_IRQSTAT_uartb_irq_SHIFT                          17
+#define BCHP_IRQ1_IRQSTAT_uartb_irq_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQSTAT :: uarta_irq [16:16] */
+#define BCHP_IRQ1_IRQSTAT_uarta_irq_MASK                           0x00010000
+#define BCHP_IRQ1_IRQSTAT_uarta_irq_SHIFT                          16
+#define BCHP_IRQ1_IRQSTAT_uarta_irq_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQSTAT :: reserved2 [15:10] */
+#define BCHP_IRQ1_IRQSTAT_reserved2_MASK                           0x0000fc00
+#define BCHP_IRQ1_IRQSTAT_reserved2_SHIFT                          10
+
+/* IRQ1 :: IRQSTAT :: ucirq [09:09] */
+#define BCHP_IRQ1_IRQSTAT_ucirq_MASK                               0x00000200
+#define BCHP_IRQ1_IRQSTAT_ucirq_SHIFT                              9
+#define BCHP_IRQ1_IRQSTAT_ucirq_DEFAULT                            0x00000000
+
+/* IRQ1 :: IRQSTAT :: reserved3 [08:07] */
+#define BCHP_IRQ1_IRQSTAT_reserved3_MASK                           0x00000180
+#define BCHP_IRQ1_IRQSTAT_reserved3_SHIFT                          7
+
+/* IRQ1 :: IRQSTAT :: gioirq [06:06] */
+#define BCHP_IRQ1_IRQSTAT_gioirq_MASK                              0x00000040
+#define BCHP_IRQ1_IRQSTAT_gioirq_SHIFT                             6
+#define BCHP_IRQ1_IRQSTAT_gioirq_DEFAULT                           0x00000000
+
+/* IRQ1 :: IRQSTAT :: reserved4 [05:05] */
+#define BCHP_IRQ1_IRQSTAT_reserved4_MASK                           0x00000020
+#define BCHP_IRQ1_IRQSTAT_reserved4_SHIFT                          5
+
+/* IRQ1 :: IRQSTAT :: uairq [04:04] */
+#define BCHP_IRQ1_IRQSTAT_uairq_MASK                               0x00000010
+#define BCHP_IRQ1_IRQSTAT_uairq_SHIFT                              4
+#define BCHP_IRQ1_IRQSTAT_uairq_DEFAULT                            0x00000000
+
+/* IRQ1 :: IRQSTAT :: ubirq [03:03] */
+#define BCHP_IRQ1_IRQSTAT_ubirq_MASK                               0x00000008
+#define BCHP_IRQ1_IRQSTAT_ubirq_SHIFT                              3
+#define BCHP_IRQ1_IRQSTAT_ubirq_DEFAULT                            0x00000000
+
+/* IRQ1 :: IRQSTAT :: irbirq [02:02] */
+#define BCHP_IRQ1_IRQSTAT_irbirq_MASK                              0x00000004
+#define BCHP_IRQ1_IRQSTAT_irbirq_SHIFT                             2
+#define BCHP_IRQ1_IRQSTAT_irbirq_DEFAULT                           0x00000000
+
+/* IRQ1 :: IRQSTAT :: reserved5 [01:00] */
+#define BCHP_IRQ1_IRQSTAT_reserved5_MASK                           0x00000003
+#define BCHP_IRQ1_IRQSTAT_reserved5_SHIFT                          0
+
+#endif /* #ifndef BCHP_IRQ1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_mem_dma_0.h b/include/linux/brcmstb/7362a0/bchp_mem_dma_0.h
new file mode 100644
index 0000000..8c5d18b
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_mem_dma_0.h
@@ -0,0 +1,157 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_mem_dma_0.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:04p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEM_DMA_0_H__
+#define BCHP_MEM_DMA_0_H__
+
+/***************************************************************************
+ *MEM_DMA_0 - MEM_DMA_0 Registers
+ ***************************************************************************/
+#define BCHP_MEM_DMA_0_REVISION                  0x00374200 /* MEM_DMA REVISION */
+#define BCHP_MEM_DMA_0_FIRST_DESC                0x00374204 /* MEM_DMA First Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CTRL                      0x00374208 /* MEM_DMA Control Register */
+#define BCHP_MEM_DMA_0_WAKE_CTRL                 0x0037420c /* MEM_DMA Wake Control Register */
+#define BCHP_MEM_DMA_0_STATUS                    0x00374214 /* MEM_DMA Status Register */
+#define BCHP_MEM_DMA_0_CUR_DESC                  0x00374218 /* MEM_DMA Current Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CUR_BYTE                  0x0037421c /* MEM_DMA Current Byte Count Register */
+#define BCHP_MEM_DMA_0_SCRATCH                   0x00374224 /* MEM_DMA Scratch Register */
+
+/***************************************************************************
+ *REVISION - MEM_DMA REVISION
+ ***************************************************************************/
+/* MEM_DMA_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_0_REVISION_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_0_REVISION_reserved0_SHIFT                    16
+
+/* MEM_DMA_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_MASK                         0x0000ff00
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_SHIFT                        8
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_DEFAULT                      0x00000002
+
+/* MEM_DMA_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_MEM_DMA_0_REVISION_MINOR_MASK                         0x000000ff
+#define BCHP_MEM_DMA_0_REVISION_MINOR_SHIFT                        0
+#define BCHP_MEM_DMA_0_REVISION_MINOR_DEFAULT                      0x0000000a
+
+/***************************************************************************
+ *FIRST_DESC - MEM_DMA First Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: FIRST_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_MASK                        0xffffffff
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_SHIFT                       0
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *CTRL - MEM_DMA Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CTRL :: reserved0 [31:01] */
+#define BCHP_MEM_DMA_0_CTRL_reserved0_MASK                         0xfffffffe
+#define BCHP_MEM_DMA_0_CTRL_reserved0_SHIFT                        1
+
+/* MEM_DMA_0 :: CTRL :: RUN [00:00] */
+#define BCHP_MEM_DMA_0_CTRL_RUN_MASK                               0x00000001
+#define BCHP_MEM_DMA_0_CTRL_RUN_SHIFT                              0
+#define BCHP_MEM_DMA_0_CTRL_RUN_DEFAULT                            0x00000000
+
+/***************************************************************************
+ *WAKE_CTRL - MEM_DMA Wake Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: WAKE_CTRL :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_MASK                    0xfffffffc
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_SHIFT                   2
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE_MODE [01:01] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_MASK                    0x00000002
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_SHIFT                   1
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_DEFAULT                 0x00000000
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE [00:00] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MASK                         0x00000001
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_SHIFT                        0
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *STATUS - MEM_DMA Status Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: STATUS :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_MEM_DMA_0_STATUS_reserved0_SHIFT                      2
+
+/* MEM_DMA_0 :: STATUS :: DMA_STATUS [01:00] */
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_MASK                      0x00000003
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_SHIFT                     0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_DEFAULT                   0x00000000
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Idle                      0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Busy                      1
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Sleep                     2
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Reserved                  3
+
+/***************************************************************************
+ *CUR_DESC - MEM_DMA Current Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_MASK                          0xffffffff
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_SHIFT                         0
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *CUR_BYTE - MEM_DMA Current Byte Count Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_BYTE :: reserved0 [31:25] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_MASK                     0xfe000000
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_SHIFT                    25
+
+/* MEM_DMA_0 :: CUR_BYTE :: COUNT [24:00] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_MASK                         0x01ffffff
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_SHIFT                        0
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *SCRATCH - MEM_DMA Scratch Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_MASK                    0xffffffff
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_SHIFT                   0
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_DEFAULT                 0x00000000
+
+#endif /* #ifndef BCHP_MEM_DMA_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_memc_ddr_0.h b/include/linux/brcmstb/7362a0/bchp_memc_ddr_0.h
new file mode 100644
index 0000000..6c9890d
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_memc_ddr_0.h
@@ -0,0 +1,2665 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:25:00 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_memc_ddr_0.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:05p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR_0_H__
+#define BCHP_MEMC_DDR_0_H__
+
+/***************************************************************************
+ *MEMC_DDR_0 - Memory Controller Sequencer (DDR Param/Control) Registers 0
+ ***************************************************************************/
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG            0x003b2000 /* Memory Controller Mode-Configuration Register. */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL          0x003b2004 /* Dram iniitialization control */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS         0x003b2008 /* Dram iniitialization status */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0              0x003b200c /* Dram Mode0 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1              0x003b2010 /* Dram Mode1 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2              0x003b2014 /* Dram Mode2 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3              0x003b2018 /* Dram Mode3 register */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG               0x003b201c /* Precharge power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG              0x003b2020 /* Self-refresh power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SSPD_CMD                 0x003b2024 /* Software standby power down mode */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS        0x003b2028 /* Power down status */
+#define BCHP_MEMC_DDR_0_WARM_BOOT                0x003b202c /* Warm boot control registers */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0            0x003b2030 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1            0x003b2034 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2            0x003b2038 /* Read to Write & write to read timing register */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3            0x003b203c /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4            0x003b2040 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5            0x003b2044 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ         0x003b2048 /* Memory Controller Sequencer Enable */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT        0x003b204c /* Memory Controller , state machine timeout register. */
+#define BCHP_MEMC_DDR_0_BANK_STATUS              0x003b2050 /* Memory Controller, Bank Status Register. */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY           0x003b2054 /* Memory Controller, Tester Latency Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0               0x003b2058 /* Memory Controller, DATA_PINMAP_BYTE0_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1               0x003b205c /* Memory Controller, DATA_PINMAP_BYTE1_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2               0x003b2060 /* Memory Controller, DATA_PINMAP_BYTE2_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3               0x003b2064 /* Memory Controller, DATA_PINMAP_BYTE3_SEL Register. */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD   0x003b2068 /* Memory Controller, DDR3 DRAM reset Register. */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL             0x003b206c /* Statistics Control register */
+#define BCHP_MEMC_DDR_0_STAT_TIMER               0x003b2070 /* Statistics Timer */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP            0x003b2074 /* DRAM Idle_NOP Cycle Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP        0x003b2078 /* Maximum DRAM idle_NOP cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL             0x003b207c /* CAS Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL         0x003b2080 /* Maximum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL         0x003b2084 /* DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL 0x003b2088 /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL      0x003b208c /* Number of overall system memory read transactions. */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL     0x003b2090 /* Number of overall system memory write transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL       0x003b2094 /* Maximum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL       0x003b2098 /* Minimum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS  0x003b209c /* Service CAS Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS 0x003b20a0 /* Maximum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS 0x003b20a4 /* Minimum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY 0x003b20a8 /* Service Intra DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY 0x003b20ac /* Service Post DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES 0x003b20b0 /* Maximum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES 0x003b20b4 /* Minimum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ 0x003b20b8 /* Service Read Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE 0x003b20bc /* Service Write Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS 0x003b20c0 /* Maximum service Transaction count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS 0x003b20c4 /* Minimum service cycle Transaction register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY 0x003b20c8 /* Service Latency Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY 0x003b20cc /* Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY 0x003b20d0 /* Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x003b20d4 /* Absolute Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x003b20d8 /* Absolute Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH             0x003b20dc /* Total number of refreshes issuedr. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0        0x003b20e0 /* CAS cycle count register for client 0. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1        0x003b20e4 /* CAS cycle count register for client 1. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2        0x003b20e8 /* CAS cycle count register for client 2. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3        0x003b20ec /* CAS cycle count register for client 3. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4        0x003b20f0 /* CAS cycle count register for client 4. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5        0x003b20f4 /* CAS cycle count register for client 5. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6        0x003b20f8 /* CAS cycle count register for client 6. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7        0x003b20fc /* CAS cycle count register for client 7. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8        0x003b2100 /* CAS cycle count register for client 8. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9        0x003b2104 /* CAS cycle count register for client 9. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10       0x003b2108 /* CAS cycle count register for client 10. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11       0x003b210c /* CAS cycle count register for client 11. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12       0x003b2110 /* CAS cycle count register for client 12. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13       0x003b2114 /* CAS cycle count register for client 13. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14       0x003b2118 /* CAS cycle count register for client 14. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15       0x003b211c /* CAS cycle count register for client 15. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16       0x003b2120 /* CAS cycle count register for client 16. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17       0x003b2124 /* CAS cycle count register for client 17. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18       0x003b2128 /* CAS cycle count register for client 18. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19       0x003b212c /* CAS cycle count register for client 19. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20       0x003b2130 /* CAS cycle count register for client 20. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21       0x003b2134 /* CAS cycle count register for client 21. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22       0x003b2138 /* CAS cycle count register for client 22. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23       0x003b213c /* CAS cycle count register for client 23. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24       0x003b2140 /* CAS cycle count register for client 24. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25       0x003b2144 /* CAS cycle count register for client 25. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26       0x003b2148 /* CAS cycle count register for client 26. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27       0x003b214c /* CAS cycle count register for client 27. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28       0x003b2150 /* CAS cycle count register for client 28. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29       0x003b2154 /* CAS cycle count register for client 29. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30       0x003b2158 /* CAS cycle count register for client 30. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31       0x003b215c /* CAS cycle count register for client 31. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32       0x003b2160 /* CAS cycle count register for client 32. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33       0x003b2164 /* CAS cycle count register for client 33. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34       0x003b2168 /* CAS cycle count register for client 34. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35       0x003b216c /* CAS cycle count register for client 35. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36       0x003b2170 /* CAS cycle count register for client 36. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37       0x003b2174 /* CAS cycle count register for client 37. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38       0x003b2178 /* CAS cycle count register for client 38. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39       0x003b217c /* CAS cycle count register for client 39. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40       0x003b2180 /* CAS cycle count register for client 40. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41       0x003b2184 /* CAS cycle count register for client 41. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42       0x003b2188 /* CAS cycle count register for client 42. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43       0x003b218c /* CAS cycle count register for client 43. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44       0x003b2190 /* CAS cycle count register for client 44. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45       0x003b2194 /* CAS cycle count register for client 45. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46       0x003b2198 /* CAS cycle count register for client 46. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47       0x003b219c /* CAS cycle count register for client 47. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48       0x003b21a0 /* CAS cycle count register for client 48. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49       0x003b21a4 /* CAS cycle count register for client 49. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50       0x003b21a8 /* CAS cycle count register for client 50. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51       0x003b21ac /* CAS cycle count register for client 51. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52       0x003b21b0 /* CAS cycle count register for client 52. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53       0x003b21b4 /* CAS cycle count register for client 53. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54       0x003b21b8 /* CAS cycle count register for client 54. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55       0x003b21bc /* CAS cycle count register for client 55. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56       0x003b21c0 /* CAS cycle count register for client 56. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57       0x003b21c4 /* CAS cycle count register for client 57. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58       0x003b21c8 /* CAS cycle count register for client 58. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59       0x003b21cc /* CAS cycle count register for client 59. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60       0x003b21d0 /* CAS cycle count register for client 60. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61       0x003b21d4 /* CAS cycle count register for client 61. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62       0x003b21d8 /* CAS cycle count register for client 62. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63       0x003b21dc /* CAS cycle count register for client 63. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64       0x003b21e0 /* CAS cycle count register for client 64. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65       0x003b21e4 /* CAS cycle count register for client 65. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66       0x003b21e8 /* CAS cycle count register for client 66. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67       0x003b21ec /* CAS cycle count register for client 67. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68       0x003b21f0 /* CAS cycle count register for client 68. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69       0x003b21f4 /* CAS cycle count register for client 69. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70       0x003b21f8 /* CAS cycle count register for client 70. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71       0x003b21fc /* CAS cycle count register for client 71. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72       0x003b2200 /* CAS cycle count register for client 72. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73       0x003b2204 /* CAS cycle count register for client 73. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74       0x003b2208 /* CAS cycle count register for client 74. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75       0x003b220c /* CAS cycle count register for client 75. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76       0x003b2210 /* CAS cycle count register for client 76. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77       0x003b2214 /* CAS cycle count register for client 77. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78       0x003b2218 /* CAS cycle count register for client 78. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79       0x003b221c /* CAS cycle count register for client 79. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80       0x003b2220 /* CAS cycle count register for client 80. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81       0x003b2224 /* CAS cycle count register for client 81. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82       0x003b2228 /* CAS cycle count register for client 82. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83       0x003b222c /* CAS cycle count register for client 83. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84       0x003b2230 /* CAS cycle count register for client 84. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85       0x003b2234 /* CAS cycle count register for client 85. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86       0x003b2238 /* CAS cycle count register for client 86. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87       0x003b223c /* CAS cycle count register for client 87. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88       0x003b2240 /* CAS cycle count register for client 88. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89       0x003b2244 /* CAS cycle count register for client 89. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90       0x003b2248 /* CAS cycle count register for client 90. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91       0x003b224c /* CAS cycle count register for client 91. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92       0x003b2250 /* CAS cycle count register for client 92. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93       0x003b2254 /* CAS cycle count register for client 93. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94       0x003b2258 /* CAS cycle count register for client 94. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95       0x003b225c /* CAS cycle count register for client 95. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96       0x003b2260 /* CAS cycle count register for client 96. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97       0x003b2264 /* CAS cycle count register for client 97. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98       0x003b2268 /* CAS cycle count register for client 98. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99       0x003b226c /* CAS cycle count register for client 99. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100      0x003b2270 /* CAS cycle count register for client 100. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101      0x003b2274 /* CAS cycle count register for client 101. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102      0x003b2278 /* CAS cycle count register for client 102. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103      0x003b227c /* CAS cycle count register for client 103. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104      0x003b2280 /* CAS cycle count register for client 104. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105      0x003b2284 /* CAS cycle count register for client 105. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106      0x003b2288 /* CAS cycle count register for client 106. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107      0x003b228c /* CAS cycle count register for client 107. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108      0x003b2290 /* CAS cycle count register for client 108. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109      0x003b2294 /* CAS cycle count register for client 109. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110      0x003b2298 /* CAS cycle count register for client 110. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111      0x003b229c /* CAS cycle count register for client 111. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112      0x003b22a0 /* CAS cycle count register for client 112. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113      0x003b22a4 /* CAS cycle count register for client 113. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114      0x003b22a8 /* CAS cycle count register for client 114. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115      0x003b22ac /* CAS cycle count register for client 115. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116      0x003b22b0 /* CAS cycle count register for client 116. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117      0x003b22b4 /* CAS cycle count register for client 117. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118      0x003b22b8 /* CAS cycle count register for client 118. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119      0x003b22bc /* CAS cycle count register for client 119. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120      0x003b22c0 /* CAS cycle count register for client 120. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121      0x003b22c4 /* CAS cycle count register for client 121. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122      0x003b22c8 /* CAS cycle count register for client 122. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123      0x003b22cc /* CAS cycle count register for client 123. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124      0x003b22d0 /* CAS cycle count register for client 124. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125      0x003b22d4 /* CAS cycle count register for client 125. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126      0x003b22d8 /* CAS cycle count register for client 126. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127      0x003b22dc /* CAS cycle count register for client 127. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL         0x003b22e0 /* Minimum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL 0x003b22e4 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL 0x003b22e8 /* MEMSYS Auto Init Control. */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS  0x003b22ec /* MEMSYS Auto Init Status. */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE 0x003b22f0 /* PHY VDL calibrate override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE 0x003b22f4 /* SHIM PLL pndiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE 0x003b22f8 /* SHIM PLL mdiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY          0x003b22fc /* Dynamic VDL shmoo command delay. */
+
+/***************************************************************************
+ *CNTRLR_CONFIG - Memory Controller Mode-Configuration Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_MASK               0xfffffff8
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_SHIFT              3
+
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DEVICE_TECH [02:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_SHIFT            0
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_DEFAULT          0x00000003
+
+/***************************************************************************
+ *DRAM_INIT_CNTRL - Dram iniitialization control
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_MASK             0xfffffff8
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_SHIFT            3
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: BYPASS_PHY_INIT_RDY [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_MASK   0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_SHIFT  2
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR_TECH [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DEFAULT           0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR2              0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR3              1
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR3_INIT_MODE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_MASK        0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_SHIFT       0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *DRAM_INIT_STATUS - Dram iniitialization status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_SHIFT           0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_DEFAULT         0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_0 - Dram Mode0 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: PD_EXIT [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_MASK              0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_SHIFT             12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_DEFAULT         0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: CL [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_MASK                   0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_DEFAULT                0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BL [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_DEFAULT                0x00000002
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK        0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT       12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT     0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT         0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_MASK               0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_SHIFT              4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT            0x00000004
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_DEFAULT               0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_MASK                 0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_SHIFT                2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_DEFAULT              0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_MASK                   0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_1 - Dram Mode1 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DEFAULT             0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: RDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DQSB [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_MASK                 0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_SHIFT                10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_ENABLE               0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DISABLE              1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: OCD_CAL [09:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_MASK              0x00000380
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_SHIFT             7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_DEFAULT       0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: AL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_MASK                   0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DRV_IMP [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DISABLE            1
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT             0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_MASK             0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_SHIFT            10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK          0x00000200
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT         9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_MASK             0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT            7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT          0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE           1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK   0x00000020
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT  5
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_MASK                   0x00000018
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT       0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK   0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT  1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DISABLE            1
+
+/***************************************************************************
+ *DRAM_MODE_2 - Dram Mode2 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_1 [12:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_MASK             0x00001f00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: HT_SRF [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_ENABLE             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DISABLE            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_2 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_MASK             0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_SHIFT            4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: DCC_ENABLE [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_MASK           0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_SHIFT          3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DEFAULT        0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_ENABLE         1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DISABLE        0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_DEFAULT              0x00000000
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_MASK             0x00001800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_SHIFT            11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_MASK               0x00000600
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_SHIFT              9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT            0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT            0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT             6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_MASK                  0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_DEFAULT               0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_3 - Dram Mode3 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: unused_0 [15:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_MASK                  0x0000fff8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR2 :: unused_1 [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_SHIFT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_DEFAULT          0x00000000
+
+/* union - case DDR3 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_MASK                  0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_SHIFT                 2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_DEFAULT               0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_MASK              0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PPD_CONFIG - Precharge power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PPD_CONFIG :: reserved0 [31:13] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_MASK                  0xffffe000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_SHIFT                 13
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_EN [12:12] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_MASK                     0x00001000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_SHIFT                    12
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_DEFAULT                  0x00000000
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: INACT_COUNT [11:00] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_MASK                0x00000fff
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *SRPD_CONFIG - Self-refresh power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SRPD_CONFIG :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_MASK                 0xfffe0000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_SHIFT                17
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: SRPD_EN [16:16] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_MASK                   0x00010000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_SHIFT                  16
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_DEFAULT                0x00000000
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SSPD_CMD - Software standby power down mode
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SSPD_CMD :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_MASK                    0xfffffffe
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_SHIFT                   1
+
+/* MEMC_DDR_0 :: SSPD_CMD :: SSPD [00:00] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK                         0x00000001
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_SHIFT                        0
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *POWER_DOWN_STATUS - Power down status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_MASK           0xfffffff8
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_SHIFT          3
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SSPD [02:02] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK                0x00000004
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_SHIFT               2
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_DEFAULT             0x00000000
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SRPD [01:01] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_MASK                0x00000002
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_SHIFT               1
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_DEFAULT             0x00000000
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: PPD [00:00] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_MASK                 0x00000001
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_SHIFT                0
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_DEFAULT              0x00000000
+
+/***************************************************************************
+ *WARM_BOOT - Warm boot control registers
+ ***************************************************************************/
+/* MEMC_DDR_0 :: WARM_BOOT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_MASK                   0xfffffffe
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_SHIFT                  1
+
+/* MEMC_DDR_0 :: WARM_BOOT :: WARM_BOOT [00:00] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_MASK                   0x00000001
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_TIMING_0 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_MASK                0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_SHIFT               24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_DEFAULT             0x00000006
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_MASK                0x00ff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_SHIFT               16
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_DEFAULT             0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_MASK                 0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_SHIFT                8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_DEFAULT              0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_DEFAULT             0x00000014
+
+/***************************************************************************
+ *DRAM_TIMING_1 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_MASK                0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_SHIFT               8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_DEFAULT             0x0000001b
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_DEFAULT             0x00000004
+
+/***************************************************************************
+ *DRAM_TIMING_2 - Read to Write & write to read timing register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_MASK               0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_SHIFT              8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_DEFAULT            0x0000000e
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_MASK               0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_DEFAULT            0x00000009
+
+/***************************************************************************
+ *DRAM_TIMING_3 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: reserved0 [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_MASK               0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_SHIFT              24
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT      0x0000000c
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: POWERUP_CKE_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_MASK       0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_SHIFT      10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_DEFAULT    0x0000005e
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: DLL_LOCK_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_MASK          0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_SHIFT         0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_DEFAULT       0x00000200
+
+/***************************************************************************
+ *DRAM_TIMING_4 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: PRECHARGE_ALL_DELAY [28:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_MASK     0x1f000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_SHIFT    24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_DEFAULT  0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: LOAD_MODE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_DEFAULT      0x0000000c
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: REFRESH_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_MASK           0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_SHIFT          10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT        0x00000058
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_MASK           0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT          0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT        0x00000200
+
+/***************************************************************************
+ *DRAM_TIMING_5 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_ASSETION_DELAY [28:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_MASK      0x1ff80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_SHIFT     19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_DEFAULT   0x00000105
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [18:15] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK           0x00078000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT          15
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT        0x00000003
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [14:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK         0x00007c00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT        10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT      0x0000000d
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK      0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT     0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT   0x00000200
+
+/***************************************************************************
+ *CNTRLR_START_SEQ - Memory Controller Sequencer Enable
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: START_SEQ [00:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_SHIFT           0
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_MASK           0xfffe0000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_SHIFT          17
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_MASK              0x00010000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT             16
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT            0x0000ffff
+
+/***************************************************************************
+ *BANK_STATUS - Memory Controller, Bank Status Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: BANK_STATUS :: reserved0 [31:08] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_SHIFT                8
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK7_STATUS [07:07] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_SHIFT             7
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK6_STATUS [06:06] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_SHIFT             6
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK5_STATUS [05:05] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_MASK              0x00000020
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_SHIFT             5
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK4_STATUS [04:04] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_MASK              0x00000010
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_SHIFT             4
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK3_STATUS [03:03] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_MASK              0x00000008
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_SHIFT             3
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK2_STATUS [02:02] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_MASK              0x00000004
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_SHIFT             2
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK1_STATUS [01:01] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_SHIFT             1
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK0_STATUS [00:00] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_MASK              0x00000001
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_SHIFT             0
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_DEFAULT           0x00000001
+
+/***************************************************************************
+ *TESTER_LATENCY - Memory Controller, Tester Latency Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: TESTER_LATENCY :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_MASK              0xffffff80
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_SHIFT             7
+
+/* MEMC_DDR_0 :: TESTER_LATENCY :: TLATENCY_SEL [06:00] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_MASK           0x0000007f
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_SHIFT          0
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE0 - Memory Controller, DATA_PINMAP_BYTE0_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE1 - Memory Controller, DATA_PINMAP_BYTE1_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE2 - Memory Controller, DATA_PINMAP_BYTE2_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE3 - Memory Controller, DATA_PINMAP_BYTE3_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_DDR3_RESET_PERIOD - Memory Controller, DDR3 DRAM reset Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: reserved0 [31:20] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_MASK      0xfff00000
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_SHIFT     20
+
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: DRAM_RESET_PERIOD [19:00] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_MASK 0x000fffff
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_SHIFT 0
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_DEFAULT 0x0000a8c0
+
+/***************************************************************************
+ *STAT_CONTROL - Statistics Control register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CONTROL :: reserved0 [31:09] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_MASK                0xfffffe00
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_SHIFT               9
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: COUNTER_MODE [08:08] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_SHIFT            8
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_DEFAULT          0x00000000
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT    1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_NORMAL           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: STAT_ENABLE [07:07] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_SHIFT             7
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DEFAULT           0x00000000
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_ENABLE            1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DISABLE           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: CLIENT_ID [06:00] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_MASK                0x0000007f
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_TIMER - Statistics Timer
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TIMER :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_MASK                      0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_SHIFT                     0
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_MASK                   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_ALL - CAS Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_PENALTY_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_MASK            0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_SHIFT           0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_DEFAULT           0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_MASK         0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT        0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_REFRESH - Total number of refreshes issuedr.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_REFRESH :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_0 - CAS cycle count register for client 0.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_1 - CAS cycle count register for client 1.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_2 - CAS cycle count register for client 2.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_3 - CAS cycle count register for client 3.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_4 - CAS cycle count register for client 4.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_5 - CAS cycle count register for client 5.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_6 - CAS cycle count register for client 6.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_7 - CAS cycle count register for client 7.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_8 - CAS cycle count register for client 8.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_9 - CAS cycle count register for client 9.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_10 - CAS cycle count register for client 10.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_11 - CAS cycle count register for client 11.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_12 - CAS cycle count register for client 12.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_13 - CAS cycle count register for client 13.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_14 - CAS cycle count register for client 14.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_15 - CAS cycle count register for client 15.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_16 - CAS cycle count register for client 16.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_17 - CAS cycle count register for client 17.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_18 - CAS cycle count register for client 18.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_19 - CAS cycle count register for client 19.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_20 - CAS cycle count register for client 20.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_21 - CAS cycle count register for client 21.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_22 - CAS cycle count register for client 22.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_23 - CAS cycle count register for client 23.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_24 - CAS cycle count register for client 24.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_25 - CAS cycle count register for client 25.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_26 - CAS cycle count register for client 26.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_27 - CAS cycle count register for client 27.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_28 - CAS cycle count register for client 28.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_29 - CAS cycle count register for client 29.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_30 - CAS cycle count register for client 30.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_31 - CAS cycle count register for client 31.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_32 - CAS cycle count register for client 32.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_33 - CAS cycle count register for client 33.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_34 - CAS cycle count register for client 34.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_35 - CAS cycle count register for client 35.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_36 - CAS cycle count register for client 36.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_37 - CAS cycle count register for client 37.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_38 - CAS cycle count register for client 38.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_39 - CAS cycle count register for client 39.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_40 - CAS cycle count register for client 40.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_41 - CAS cycle count register for client 41.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_42 - CAS cycle count register for client 42.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_43 - CAS cycle count register for client 43.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_44 - CAS cycle count register for client 44.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_45 - CAS cycle count register for client 45.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_46 - CAS cycle count register for client 46.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_47 - CAS cycle count register for client 47.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_48 - CAS cycle count register for client 48.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_49 - CAS cycle count register for client 49.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_50 - CAS cycle count register for client 50.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_51 - CAS cycle count register for client 51.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_52 - CAS cycle count register for client 52.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_53 - CAS cycle count register for client 53.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_54 - CAS cycle count register for client 54.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_55 - CAS cycle count register for client 55.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_56 - CAS cycle count register for client 56.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_57 - CAS cycle count register for client 57.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_58 - CAS cycle count register for client 58.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_59 - CAS cycle count register for client 59.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_60 - CAS cycle count register for client 60.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_61 - CAS cycle count register for client 61.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_62 - CAS cycle count register for client 62.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_63 - CAS cycle count register for client 63.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_64 - CAS cycle count register for client 64.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_65 - CAS cycle count register for client 65.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_66 - CAS cycle count register for client 66.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_67 - CAS cycle count register for client 67.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_68 - CAS cycle count register for client 68.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_69 - CAS cycle count register for client 69.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_70 - CAS cycle count register for client 70.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_71 - CAS cycle count register for client 71.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_72 - CAS cycle count register for client 72.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_73 - CAS cycle count register for client 73.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_74 - CAS cycle count register for client 74.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_75 - CAS cycle count register for client 75.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_76 - CAS cycle count register for client 76.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_77 - CAS cycle count register for client 77.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_78 - CAS cycle count register for client 78.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_79 - CAS cycle count register for client 79.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_80 - CAS cycle count register for client 80.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_81 - CAS cycle count register for client 81.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_82 - CAS cycle count register for client 82.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_83 - CAS cycle count register for client 83.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_84 - CAS cycle count register for client 84.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_85 - CAS cycle count register for client 85.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_86 - CAS cycle count register for client 86.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_87 - CAS cycle count register for client 87.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_88 - CAS cycle count register for client 88.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_89 - CAS cycle count register for client 89.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_90 - CAS cycle count register for client 90.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_91 - CAS cycle count register for client 91.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_92 - CAS cycle count register for client 92.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_93 - CAS cycle count register for client 93.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_94 - CAS cycle count register for client 94.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_95 - CAS cycle count register for client 95.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_96 - CAS cycle count register for client 96.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_97 - CAS cycle count register for client 97.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_98 - CAS cycle count register for client 98.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_99 - CAS cycle count register for client 99.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_100 - CAS cycle count register for client 100.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_101 - CAS cycle count register for client 101.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_102 - CAS cycle count register for client 102.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_103 - CAS cycle count register for client 103.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_104 - CAS cycle count register for client 104.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_105 - CAS cycle count register for client 105.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_106 - CAS cycle count register for client 106.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_107 - CAS cycle count register for client 107.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_108 - CAS cycle count register for client 108.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_109 - CAS cycle count register for client 109.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_110 - CAS cycle count register for client 110.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_111 - CAS cycle count register for client 111.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_112 - CAS cycle count register for client 112.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_113 - CAS cycle count register for client 113.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_114 - CAS cycle count register for client 114.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_115 - CAS cycle count register for client 115.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_116 - CAS cycle count register for client 116.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_117 - CAS cycle count register for client 117.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_118 - CAS cycle count register for client 118.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_119 - CAS cycle count register for client 119.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_120 - CAS cycle count register for client 120.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_121 - CAS cycle count register for client 121.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_122 - CAS cycle count register for client 122.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_123 - CAS cycle count register for client 123.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_124 - CAS cycle count register for client 124.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_125 - CAS cycle count register for client 125.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_126 - CAS cycle count register for client 126.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_127 - CAS cycle count register for client 127.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_DEFAULT             0xffffffff
+
+/***************************************************************************
+ *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT    0xffffffff
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_CONTROL - MEMSYS Auto Init Control.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: reserved0 [31:10] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_MASK    0xfffffc00
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_SHIFT   10
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_DIVIDER [09:09] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_MASK 0x00000200
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_SHIFT 9
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_VDL_CALIB_AUTO_INIT [08:08] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_MASK 0x00000100
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_SHIFT 8
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_DRAM_INIT_DONE_SET [07:07] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_MASK 0x00000080
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_SHIFT 7
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_RESET [06:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_MASK 0x00000040
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_SET [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_READY_SET [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_AUTO_INIT_ACTIVE_RESET [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_MASK 0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_SHIFT 3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: SKIP_PHY_AUTO_INIT [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: MEMSYS_AUTO_INIT_START [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_STATUS - MEMSYS Auto Init Status.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_MASK     0xfffff000
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_SHIFT    12
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMC_AUTO_INIT_STATES [11:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_MASK 0x00000fc0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: AUTO_INIT_ACTIVE [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_STRAP_VALID [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_READY [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_MASK     0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_SHIFT    3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_DEFAULT  0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: DRAM_INIT_DONE [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_FAIL [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHY_VDL_CALIB_AUTO_INIT_OVERRIDE - PHY VDL calibrate override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PHY_VDL_CALIB_AUTO_INIT_OVERRIDE :: PHY_VDL_CALIB_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_DEFAULT 0x10000000
+
+/***************************************************************************
+ *SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE - SHIM PLL pndiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_PNDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_DEFAULT 0x23b00000
+
+/***************************************************************************
+ *SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE - SHIM PLL mdiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_MDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_DEFAULT 0x00001003
+
+/***************************************************************************
+ *DYN_VDL_CMD_DLY - Dynamic VDL shmoo command delay.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_MASK             0xfffff000
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_SHIFT            12
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: END_CAS_DLY [11:06] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_MASK           0x00000fc0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_SHIFT          6
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_DEFAULT        0x00000000
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: START_CAS_DLY [05:00] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_MASK         0x0000003f
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_SHIFT        0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_DEFAULT      0x00000000
+
+#endif /* #ifndef BCHP_MEMC_DDR_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_misb_bridge.h b/include/linux/brcmstb/7362a0/bchp_misb_bridge.h
new file mode 100644
index 0000000..1785df3a1
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_misb_bridge.h
@@ -0,0 +1,87 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 24 17:25:43 2013
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MISB_BRIDGE_H__
+#define BCHP_MISB_BRIDGE_H__
+
+/***************************************************************************
+ *MISB_BRIDGE - MISB_BRIDGE Registers
+ ***************************************************************************/
+#define BCHP_MISB_BRIDGE_CORE_REV_ID             0x00410400 /* MISB Bridge Revision ID Register. */
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET 0x00410404 /* "Exception Vector Offset Address" */
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID            0x00410408 /* Processor ID Register. */
+
+/***************************************************************************
+ *CORE_REV_ID - MISB Bridge Revision ID Register.
+ ***************************************************************************/
+/* MISB_BRIDGE :: CORE_REV_ID :: reserved0 [31:16] */
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_reserved0_MASK                0xffff0000
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_reserved0_SHIFT               16
+
+/* MISB_BRIDGE :: CORE_REV_ID :: MAJOR [15:08] */
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MAJOR_MASK                    0x0000ff00
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MAJOR_SHIFT                   8
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MAJOR_DEFAULT                 0x00000000
+
+/* MISB_BRIDGE :: CORE_REV_ID :: MINOR [07:00] */
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MINOR_MASK                    0x000000ff
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MINOR_SHIFT                   0
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MINOR_DEFAULT                 0x00000001
+
+/***************************************************************************
+ *EXCEPTION_VECTOR_OFFSET - "Exception Vector Offset Address"
+ ***************************************************************************/
+/* MISB_BRIDGE :: EXCEPTION_VECTOR_OFFSET :: ADDRS [31:00] */
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET_ADDRS_MASK        0xffffffff
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET_ADDRS_SHIFT       0
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET_ADDRS_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PROCESSOR_ID - Processor ID Register.
+ ***************************************************************************/
+/* MISB_BRIDGE :: PROCESSOR_ID :: reserved0 [31:08] */
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_reserved0_MASK               0xffffff00
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_reserved0_SHIFT              8
+
+/* MISB_BRIDGE :: PROCESSOR_ID :: ID [07:00] */
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_ID_MASK                      0x000000ff
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_ID_SHIFT                     0
+
+#endif /* #ifndef BCHP_MISB_BRIDGE_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_nand.h b/include/linux/brcmstb/7362a0/bchp_nand.h
new file mode 100644
index 0000000..6ad6a8e
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_nand.h
@@ -0,0 +1,2260 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_nand.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:09p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_NAND_H__
+#define BCHP_NAND_H__
+
+/***************************************************************************
+ *NAND - Nand Flash Control Registers
+ ***************************************************************************/
+#define BCHP_NAND_REVISION                       0x00412800 /* NAND Revision */
+#define BCHP_NAND_CMD_START                      0x00412804 /* Nand Flash Command Start */
+#define BCHP_NAND_CMD_EXT_ADDRESS                0x00412808 /* Nand Flash Command Extended Address */
+#define BCHP_NAND_CMD_ADDRESS                    0x0041280c /* Nand Flash Command Address */
+#define BCHP_NAND_CMD_END_ADDRESS                0x00412810 /* Nand Flash Command End Address */
+#define BCHP_NAND_CS_NAND_SELECT                 0x00412814 /* Nand Flash EBI CS Select */
+#define BCHP_NAND_CS_NAND_XOR                    0x00412818 /* Nand Flash EBI CS Address XOR with 1FC0 Control */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0          0x00412820 /* Nand Flash Spare Area Read Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4          0x00412824 /* Nand Flash Spare Area Read Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8          0x00412828 /* Nand Flash Spare Area Read Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C          0x0041282c /* Nand Flash Spare Area Read Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0         0x00412830 /* Nand Flash Spare Area Write Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4         0x00412834 /* Nand Flash Spare Area Write Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8         0x00412838 /* Nand Flash Spare Area Write Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C         0x0041283c /* Nand Flash Spare Area Write Bytes 12-15 */
+#define BCHP_NAND_ACC_CONTROL                    0x00412840 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG                         0x00412848 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1                       0x00412850 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2                       0x00412854 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SEMAPHORE                      0x00412858 /* Semaphore */
+#define BCHP_NAND_FLASH_DEVICE_ID                0x00412860 /* Nand Flash Device ID */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT            0x00412864 /* Nand Flash Extended Device ID */
+#define BCHP_NAND_BLOCK_LOCK_STATUS              0x00412868 /* Nand Flash Block Lock Status */
+#define BCHP_NAND_INTFC_STATUS                   0x0041286c /* Nand Flash Interface Status */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR              0x00412870 /* ECC Correctable Error Extended Address */
+#define BCHP_NAND_ECC_CORR_ADDR                  0x00412874 /* ECC Correctable Error Address */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR               0x00412878 /* ECC Uncorrectable Error Extended Address */
+#define BCHP_NAND_ECC_UNC_ADDR                   0x0041287c /* ECC Uncorrectable Error Address */
+#define BCHP_NAND_READ_ERROR_COUNT               0x00412880 /* Read Error Count */
+#define BCHP_NAND_CORR_STAT_THRESHOLD            0x00412884 /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_ONFI_STATUS                    0x00412888 /* ONFI Status */
+#define BCHP_NAND_ONFI_DEBUG_DATA                0x0041288c /* ONFI Debug Data */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR            0x00412890 /* Flash Read Data Extended Address */
+#define BCHP_NAND_FLASH_READ_ADDR                0x00412894 /* Flash Read Data Address */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR          0x00412898 /* Page Program Extended Address */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR              0x0041289c /* Page Program Address */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR             0x004128a0 /* Copy Back Extended Address */
+#define BCHP_NAND_COPY_BACK_ADDR                 0x004128a4 /* Copy Back Address */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR           0x004128a8 /* Block Erase Extended Address */
+#define BCHP_NAND_BLOCK_ERASE_ADDR               0x004128ac /* Block Erase Address */
+#define BCHP_NAND_INV_READ_EXT_ADDR              0x004128b0 /* Flash Invalid Data Extended Address */
+#define BCHP_NAND_INV_READ_ADDR                  0x004128b4 /* Flash Invalid Data Address */
+#define BCHP_NAND_BLK_WR_PROTECT                 0x004128c0 /* Block Write Protect Enable and Size for EBI_CS0b */
+#define BCHP_NAND_ACC_CONTROL_CS1                0x004128d0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS1                     0x004128d4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS1                   0x004128d8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS1                   0x004128dc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS2                0x004128e0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS2                     0x004128e4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS2                   0x004128e8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS2                   0x004128ec /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS3                0x004128f0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS3                     0x004128f4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS3                   0x004128f8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS3                   0x004128fc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS4                0x00412900 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS4                     0x00412904 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS4                   0x00412908 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS4                   0x0041290c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10         0x00412930 /* Nand Flash Spare Area Read Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14         0x00412934 /* Nand Flash Spare Area Read Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18         0x00412938 /* Nand Flash Spare Area Read Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C         0x0041293c /* Nand Flash Spare Area Read Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10        0x00412940 /* Nand Flash Spare Area Write Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14        0x00412944 /* Nand Flash Spare Area Write Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18        0x00412948 /* Nand Flash Spare Area Write Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C        0x0041294c /* Nand Flash Spare Area Write Bytes 28-31 */
+#define BCHP_NAND_LL_OP                          0x00412978 /* Nand Flash Low Level Operation */
+#define BCHP_NAND_LL_RDDATA                      0x0041297c /* Nand Flash Low Level Read Data */
+
+/***************************************************************************
+ *REVISION - NAND Revision
+ ***************************************************************************/
+/* NAND :: REVISION :: 8KB_PAGE_SUPPORT [31:31] */
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_MASK                   0x80000000
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_SHIFT                  31
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_DEFAULT                0x00000001
+
+/* NAND :: REVISION :: reserved0 [30:16] */
+#define BCHP_NAND_REVISION_reserved0_MASK                          0x7fff0000
+#define BCHP_NAND_REVISION_reserved0_SHIFT                         16
+
+/* NAND :: REVISION :: MAJOR [15:08] */
+#define BCHP_NAND_REVISION_MAJOR_MASK                              0x0000ff00
+#define BCHP_NAND_REVISION_MAJOR_SHIFT                             8
+#define BCHP_NAND_REVISION_MAJOR_DEFAULT                           0x00000005
+
+/* NAND :: REVISION :: MINOR [07:00] */
+#define BCHP_NAND_REVISION_MINOR_MASK                              0x000000ff
+#define BCHP_NAND_REVISION_MINOR_SHIFT                             0
+#define BCHP_NAND_REVISION_MINOR_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *CMD_START - Nand Flash Command Start
+ ***************************************************************************/
+/* NAND :: CMD_START :: reserved0 [31:29] */
+#define BCHP_NAND_CMD_START_reserved0_MASK                         0xe0000000
+#define BCHP_NAND_CMD_START_reserved0_SHIFT                        29
+
+/* NAND :: CMD_START :: OPCODE [28:24] */
+#define BCHP_NAND_CMD_START_OPCODE_MASK                            0x1f000000
+#define BCHP_NAND_CMD_START_OPCODE_SHIFT                           24
+#define BCHP_NAND_CMD_START_OPCODE_DEFAULT                         0x00000000
+#define BCHP_NAND_CMD_START_OPCODE_NULL                            0
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ                       1
+#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ                 2
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ                     3
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE                    4
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA              5
+#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK                       6
+#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ                  7
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE                     8
+#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET                     9
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK                     10
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN                11
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK                   12
+#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS         13
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ                  14
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL            15
+#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP                    16
+
+/* NAND :: CMD_START :: reserved1 [23:00] */
+#define BCHP_NAND_CMD_START_reserved1_MASK                         0x00ffffff
+#define BCHP_NAND_CMD_START_reserved1_SHIFT                        0
+
+/***************************************************************************
+ *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
+ ***************************************************************************/
+/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK                   0xfff80000
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT                  19
+
+/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK                      0x00070000
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT                     16
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT                   0x00000000
+
+/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK                 0x0000ffff
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT                0
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CMD_ADDRESS - Nand Flash Command Address
+ ***************************************************************************/
+/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK                         0xffffffff
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT                        0
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *CMD_END_ADDRESS - Nand Flash Command End Address
+ ***************************************************************************/
+/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT                    0
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *CS_NAND_SELECT - Nand Flash EBI CS Select
+ ***************************************************************************/
+/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT                     31
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK        0x40000000
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT       30
+
+/* NAND :: CS_NAND_SELECT :: reserved0 [29:29] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK                    0x20000000
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT                   29
+
+/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK              0x10000000
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT             28
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT           0x00000000
+
+/* NAND :: CS_NAND_SELECT :: reserved1 [27:16] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_MASK                    0x0fff0000
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_SHIFT                   16
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK           0x00008000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT          15
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK           0x00004000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT          14
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK           0x00002000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT          13
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK           0x00001000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT          12
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK           0x00000800
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT          11
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK           0x00000400
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT          10
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK           0x00000200
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT          9
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK           0x00000100
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT          8
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK                 0x00000080
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT                7
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK                 0x00000040
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT                6
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK                 0x00000020
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT                5
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK                 0x00000010
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT                4
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK                 0x00000008
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT                3
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK                 0x00000004
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT                2
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK                 0x00000002
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT                1
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK                 0x00000001
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT                0
+
+/***************************************************************************
+ *CS_NAND_XOR - Nand Flash EBI CS Address XOR with 1FC0 Control
+ ***************************************************************************/
+/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_1FC0_XOR [31:31] */
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_MASK           0x80000000
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_SHIFT          31
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
+#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK                       0x7fffff00
+#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT                      8
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_1FC0_XOR [07:07] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_MASK          0x00000080
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_SHIFT         7
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_1FC0_XOR [06:06] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_MASK          0x00000040
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_SHIFT         6
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_1FC0_XOR [05:05] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_MASK          0x00000020
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_SHIFT         5
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_1FC0_XOR [04:04] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_MASK          0x00000010
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_SHIFT         4
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_1FC0_XOR [03:03] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_MASK          0x00000008
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_SHIFT         3
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_1FC0_XOR [02:02] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_MASK          0x00000004
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_SHIFT         2
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_1FC0_XOR [01:01] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_MASK          0x00000002
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_SHIFT         1
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_1FC0_XOR [00:00] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_MASK          0x00000001
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_SHIFT         0
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *ACC_CONTROL - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_MASK                       0x80000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_SHIFT                      31
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_DEFAULT                    0x00000001
+
+/* NAND :: ACC_CONTROL :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_MASK                       0x40000000
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_SHIFT                      30
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_DEFAULT                    0x00000001
+
+/* NAND :: ACC_CONTROL :: RD_ECC_BLK0_EN [29:29] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_MASK                  0x20000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_SHIFT                 29
+
+/* NAND :: ACC_CONTROL :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_SHIFT                  28
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_MASK                0x08000000
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_SHIFT               27
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_DEFAULT             0x00000000
+
+/* NAND :: ACC_CONTROL :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_MASK                 0x04000000
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_SHIFT                26
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_MASK                   0x02000000
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_SHIFT                  25
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_MASK                     0x01000000
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_SHIFT                    24
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_DEFAULT                  0x00000001
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL_0 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_MASK                     0x00f00000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_SHIFT                    20
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_DEFAULT                  0x0000000f
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_MASK                       0x000f0000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_SHIFT                      16
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_DEFAULT                    0x0000000f
+
+/* NAND :: ACC_CONTROL :: reserved0 [15:15] */
+#define BCHP_NAND_ACC_CONTROL_reserved0_MASK                       0x00008000
+#define BCHP_NAND_ACC_CONTROL_reserved0_SHIFT                      15
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K_0 [14:14] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_MASK                0x00004000
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_SHIFT               14
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_DEFAULT             0x00000000
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE_0 [13:08] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_MASK               0x00003f00
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_SHIFT              8
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_DEFAULT            0x00000010
+
+/* NAND :: ACC_CONTROL :: reserved1 [07:07] */
+#define BCHP_NAND_ACC_CONTROL_reserved1_MASK                       0x00000080
+#define BCHP_NAND_ACC_CONTROL_reserved1_SHIFT                      7
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_MASK                  0x00000040
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_SHIFT                 6
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_DEFAULT               0x00000000
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_MASK                 0x0000003f
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_SHIFT                0
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_DEFAULT              0x00000010
+
+/***************************************************************************
+ *CONFIG - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_MASK                          0x80000000
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_SHIFT                         31
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_DEFAULT                       0x00000000
+
+/* NAND :: CONFIG :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_MASK                           0x70000000
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_SHIFT                          28
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_2048KB                 6
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_1024KB                 5
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_512KB                  3
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_128KB                  1
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_16KB                   0
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_8KB                    2
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_256KB                  4
+
+/* NAND :: CONFIG :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_MASK                          0x0f000000
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_SHIFT                         24
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4MB                  0
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8MB                  1
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16MB                 2
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32MB                 3
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64MB                 4
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128MB                5
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_256MB                6
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_512MB                7
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_1GB                  8
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_2GB                  9
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4GB                  10
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8GB                  11
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16GB                 12
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32GB                 13
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64GB                 14
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128GB                15
+
+/* NAND :: CONFIG :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_MASK                         0x00800000
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_SHIFT                        23
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_8                  0
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_16                 1
+
+/* NAND :: CONFIG :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_reserved0_MASK                            0x00400000
+#define BCHP_NAND_CONFIG_reserved0_SHIFT                           22
+
+/* NAND :: CONFIG :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_PAGE_SIZE_MASK                            0x00300000
+#define BCHP_NAND_CONFIG_PAGE_SIZE_SHIFT                           20
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_512                     0
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_2KB                     1
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_4KB                     2
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_8KB                     3
+
+/* NAND :: CONFIG :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_reserved1_MASK                            0x00080000
+#define BCHP_NAND_CONFIG_reserved1_SHIFT                           19
+
+/* NAND :: CONFIG :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_MASK                        0x00070000
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_SHIFT                       16
+
+/* NAND :: CONFIG :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_reserved2_MASK                            0x00008000
+#define BCHP_NAND_CONFIG_reserved2_SHIFT                           15
+
+/* NAND :: CONFIG :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_MASK                        0x00007000
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_SHIFT                       12
+
+/* NAND :: CONFIG :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_reserved3_MASK                            0x00000800
+#define BCHP_NAND_CONFIG_reserved3_SHIFT                           11
+
+/* NAND :: CONFIG :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_MASK                        0x00000700
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_SHIFT                       8
+
+/* NAND :: CONFIG :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_reserved4_MASK                            0x000000ff
+#define BCHP_NAND_CONFIG_reserved4_SHIFT                           0
+
+/***************************************************************************
+ *TIMING_1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_tWP_MASK                                0xf0000000
+#define BCHP_NAND_TIMING_1_tWP_SHIFT                               28
+#define BCHP_NAND_TIMING_1_tWP_DEFAULT                             0x00000006
+
+/* NAND :: TIMING_1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_tWH_MASK                                0x0f000000
+#define BCHP_NAND_TIMING_1_tWH_SHIFT                               24
+#define BCHP_NAND_TIMING_1_tWH_DEFAULT                             0x00000005
+
+/* NAND :: TIMING_1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_tRP_MASK                                0x00f00000
+#define BCHP_NAND_TIMING_1_tRP_SHIFT                               20
+#define BCHP_NAND_TIMING_1_tRP_DEFAULT                             0x00000007
+
+/* NAND :: TIMING_1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_tREH_MASK                               0x000f0000
+#define BCHP_NAND_TIMING_1_tREH_SHIFT                              16
+#define BCHP_NAND_TIMING_1_tREH_DEFAULT                            0x00000004
+
+/* NAND :: TIMING_1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_tCS_MASK                                0x0000f000
+#define BCHP_NAND_TIMING_1_tCS_SHIFT                               12
+#define BCHP_NAND_TIMING_1_tCS_DEFAULT                             0x00000008
+
+/* NAND :: TIMING_1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_tCLH_MASK                               0x00000f00
+#define BCHP_NAND_TIMING_1_tCLH_SHIFT                              8
+#define BCHP_NAND_TIMING_1_tCLH_DEFAULT                            0x00000004
+
+/* NAND :: TIMING_1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_tALH_MASK                               0x000000f0
+#define BCHP_NAND_TIMING_1_tALH_SHIFT                              4
+#define BCHP_NAND_TIMING_1_tALH_DEFAULT                            0x00000005
+
+/* NAND :: TIMING_1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_tADL_MASK                               0x0000000f
+#define BCHP_NAND_TIMING_1_tADL_SHIFT                              0
+#define BCHP_NAND_TIMING_1_tADL_DEFAULT                            0x0000000b
+
+/***************************************************************************
+ *TIMING_2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CLK_SELECT_MASK                         0x80000000
+#define BCHP_NAND_TIMING_2_CLK_SELECT_SHIFT                        31
+#define BCHP_NAND_TIMING_2_CLK_SELECT_DEFAULT                      0x00000000
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_108                      0
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_216                      1
+
+/* NAND :: TIMING_2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_reserved0_MASK                          0x7fffe000
+#define BCHP_NAND_TIMING_2_reserved0_SHIFT                         13
+
+/* NAND :: TIMING_2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_tWB_MASK                                0x00001e00
+#define BCHP_NAND_TIMING_2_tWB_SHIFT                               9
+#define BCHP_NAND_TIMING_2_tWB_DEFAULT                             0x0000000f
+
+/* NAND :: TIMING_2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_tWHR_MASK                               0x000001f0
+#define BCHP_NAND_TIMING_2_tWHR_SHIFT                              4
+#define BCHP_NAND_TIMING_2_tWHR_DEFAULT                            0x00000009
+
+/* NAND :: TIMING_2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_tREAD_MASK                              0x0000000f
+#define BCHP_NAND_TIMING_2_tREAD_SHIFT                             0
+#define BCHP_NAND_TIMING_2_tREAD_DEFAULT                           0x00000006
+
+/***************************************************************************
+ *SEMAPHORE - Semaphore
+ ***************************************************************************/
+/* NAND :: SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_NAND_SEMAPHORE_reserved0_MASK                         0xffffff00
+#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT                        8
+
+/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK                    0x000000ff
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT                   0
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *FLASH_DEVICE_ID - Nand Flash Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK                      0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT                     24
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK                      0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT                     16
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK                      0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT                     8
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK                      0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT                     0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK                  0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT                 24
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK                  0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT                 16
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK                  0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT                 8
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK                  0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT                 0
+
+/***************************************************************************
+ *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
+ ***************************************************************************/
+/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT                8
+
+/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK                    0x000000ff
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT                   0
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *INTFC_STATUS - Nand Flash Interface Status
+ ***************************************************************************/
+/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK                     0x80000000
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT                    31
+
+/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK                    0x40000000
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT                   30
+
+/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK                    0x20000000
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT                   29
+
+/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK               0x10000000
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT              28
+
+/* NAND :: INTFC_STATUS :: ERASED [27:27] */
+#define BCHP_NAND_INTFC_STATUS_ERASED_MASK                         0x08000000
+#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT                        27
+
+/* NAND :: INTFC_STATUS :: reserved0 [26:08] */
+#define BCHP_NAND_INTFC_STATUS_reserved0_MASK                      0x07ffff00
+#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT                     8
+
+/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK                   0x000000ff
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT                  0
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ECC_CORR_ADDR - ECC Correctable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK                  0xfff80000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT                 19
+
+/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK                     0x00070000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT                    16
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT                  0x00000000
+
+/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK                0x0000ffff
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT               0
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT             0x00000000
+
+/***************************************************************************
+ *ECC_UNC_ADDR - ECC Uncorrectable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK                        0xffffffff
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT                       0
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *READ_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:05] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK               0xffffffe0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT              5
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD [04:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_MASK     0x0000001f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_SHIFT    0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_DEFAULT  0x00000001
+
+/***************************************************************************
+ *ONFI_STATUS - ONFI Status
+ ***************************************************************************/
+/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK                  0xf0000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT                 28
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT               0x00000000
+
+/* NAND :: ONFI_STATUS :: reserved0 [27:06] */
+#define BCHP_NAND_ONFI_STATUS_reserved0_MASK                       0x0fffffc0
+#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT                      6
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK              0x00000020
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT             5
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK              0x00000010
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT             4
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK              0x00000008
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT             3
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK              0x00000004
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT             2
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK              0x00000002
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT             1
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK              0x00000001
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT             0
+
+/***************************************************************************
+ *ONFI_DEBUG_DATA - ONFI Debug Data
+ ***************************************************************************/
+/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK             0xffffffff
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT            0
+
+/***************************************************************************
+ *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK               0xfff80000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT              19
+
+/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK                  0x00070000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT                 16
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT               0x00000000
+
+/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK             0x0000ffff
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT            0
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT          0x00000000
+
+/***************************************************************************
+ *FLASH_READ_ADDR - Flash Read Data Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT                    0
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK             0xfff80000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT            19
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK                0x00070000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT               16
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT             0x00000000
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK           0x0000ffff
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT          0
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_ADDR - Page Program Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK                   0xffffffff
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT                  0
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *COPY_BACK_EXT_ADDR - Copy Back Extended Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK                0xfff80000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT               19
+
+/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK                   0x00070000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT                  16
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT                0x00000000
+
+/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK              0x0000ffff
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT             0
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT           0x00000000
+
+/***************************************************************************
+ *COPY_BACK_ADDR - Copy Back Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK                      0xffffffff
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT                     0
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK              0xfff80000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT             19
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK                 0x00070000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT                16
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT              0x00000000
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK            0x0000ffff
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT           0
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_ADDR - Block Erase Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK                    0xffffffff
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT                   0
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
+ ***************************************************************************/
+/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *INV_READ_ADDR - Flash Invalid Data Address
+ ***************************************************************************/
+/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
+ ***************************************************************************/
+/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK                 0xffffffff
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT                0
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *ACC_CONTROL_CS1 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS1 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS1 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS1 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS1 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS1_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS1 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS1 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS1_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS1_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS1_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS1_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS1_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS1_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS1_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS1_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS1_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS1_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS1_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS1 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS1 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS1_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS2 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS2 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS2 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS2 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS2 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS2_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS2 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS2 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS2_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS2_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS2_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS2_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS2 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS2_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS2_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS2_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS2_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS2_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS2_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS2_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS2_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS3 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS3 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS3 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS3 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS3 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS3_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS3 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS3 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS3_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS3_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS3_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS3_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS3 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS3_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS3_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS3_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS3_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS3_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS3_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS3_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS3 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS3 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS3_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS4 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS4 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS4 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS4 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS4 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS4_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS4 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS4 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS4_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS4_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS4_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS4_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS4 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS4_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS4_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS4_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS4_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS4_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS4_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS4_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS4 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS4 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS4_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *LL_OP - Nand Flash Low Level Operation
+ ***************************************************************************/
+/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
+#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK                           0x80000000
+#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT                          31
+#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT                        0x00000000
+
+/* NAND :: LL_OP :: reserved0 [30:20] */
+#define BCHP_NAND_LL_OP_reserved0_MASK                             0x7ff00000
+#define BCHP_NAND_LL_OP_reserved0_SHIFT                            20
+
+/* NAND :: LL_OP :: CLE [19:19] */
+#define BCHP_NAND_LL_OP_CLE_MASK                                   0x00080000
+#define BCHP_NAND_LL_OP_CLE_SHIFT                                  19
+#define BCHP_NAND_LL_OP_CLE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: ALE [18:18] */
+#define BCHP_NAND_LL_OP_ALE_MASK                                   0x00040000
+#define BCHP_NAND_LL_OP_ALE_SHIFT                                  18
+#define BCHP_NAND_LL_OP_ALE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: WE [17:17] */
+#define BCHP_NAND_LL_OP_WE_MASK                                    0x00020000
+#define BCHP_NAND_LL_OP_WE_SHIFT                                   17
+#define BCHP_NAND_LL_OP_WE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: RE [16:16] */
+#define BCHP_NAND_LL_OP_RE_MASK                                    0x00010000
+#define BCHP_NAND_LL_OP_RE_SHIFT                                   16
+#define BCHP_NAND_LL_OP_RE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: DATA [15:00] */
+#define BCHP_NAND_LL_OP_DATA_MASK                                  0x0000ffff
+#define BCHP_NAND_LL_OP_DATA_SHIFT                                 0
+#define BCHP_NAND_LL_OP_DATA_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *LL_RDDATA - Nand Flash Low Level Read Data
+ ***************************************************************************/
+/* NAND :: LL_RDDATA :: reserved0 [31:16] */
+#define BCHP_NAND_LL_RDDATA_reserved0_MASK                         0xffff0000
+#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT                        16
+
+/* NAND :: LL_RDDATA :: DATA [15:00] */
+#define BCHP_NAND_LL_RDDATA_DATA_MASK                              0x0000ffff
+#define BCHP_NAND_LL_RDDATA_DATA_SHIFT                             0
+#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE                          0x00412a00
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_START                         0
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_END                           127
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE                  32
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+/* NAND :: FLASH_CACHEi :: WORD [31:00] */
+#define BCHP_NAND_FLASH_CACHEi_WORD_MASK                           0xffffffff
+#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT                          0
+
+
+#endif /* #ifndef BCHP_NAND_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_sata_top_ctrl.h b/include/linux/brcmstb/7362a0/bchp_sata_top_ctrl.h
new file mode 100644
index 0000000..8b921ce
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_sata_top_ctrl.h
@@ -0,0 +1,164 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_sata_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:19p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SATA_TOP_CTRL_H__
+#define BCHP_SATA_TOP_CTRL_H__
+
+/***************************************************************************
+ *SATA_TOP_CTRL - SATA3 MISC Control Registers
+ ***************************************************************************/
+#define BCHP_SATA_TOP_CTRL_Version               0x00180020 /* SATA3 Version Register */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL              0x00180024 /* SATA3 System Bus Access Control Register */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL               0x00180028 /* SATA3 Test Port Control register */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1            0x0018002c /* SATA3 phy interface control 1 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2            0x00180030 /* SATA3 phy interface control 2 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3            0x00180034 /* SATA3 phy interface control 3 */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT           0x00180038 /* SATA3 TP OUT */
+
+/***************************************************************************
+ *Version - SATA3 Version Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: Version :: reserved0 [31:08] */
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_MASK                  0xffffff00
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_SHIFT                 8
+
+/* SATA_TOP_CTRL :: Version :: major_version [07:04] */
+#define BCHP_SATA_TOP_CTRL_Version_major_version_MASK              0x000000f0
+#define BCHP_SATA_TOP_CTRL_Version_major_version_SHIFT             4
+#define BCHP_SATA_TOP_CTRL_Version_major_version_DEFAULT           0x00000000
+
+/* SATA_TOP_CTRL :: Version :: minor_version [03:00] */
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_MASK              0x0000000f
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_SHIFT             0
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_DEFAULT           0x00000001
+
+/***************************************************************************
+ *BUS_CTRL - SATA3 System Bus Access Control Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_31_17 [31:17] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_MASK            0xfffe0000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_SHIFT           17
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_DEFAULT         0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: overide_hwinit_registers [16:16] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_MASK  0x00010000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_SHIFT 16
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_DEFAULT 0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_15_8 [15:08] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_MASK             0x0000ff00
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_SHIFT            8
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_DEFAULT          0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: piodata_endian_ctrl [07:06] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_MASK       0x000000c0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SHIFT      6
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadata_endian_ctrl [05:04] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_MASK       0x00000030
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SHIFT      4
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadesc_endian_ctrl [03:02] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_MASK       0x0000000c
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SHIFT      2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: reg_endian_ctrl [01:00] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_MASK           0x00000003
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SHIFT          0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_DEFAULT        0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SwapEndianess  2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_HalfWordSwap   1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_NoSwap         0
+
+/***************************************************************************
+ *TP_CTRL - SATA3 Test Port Control register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: TP_CTRL :: tp_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_MASK                    0xffffffff
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_SHIFT                   0
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_1 - SATA3 phy interface control 1
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_1 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_2 - SATA3 phy interface control 2
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_2 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_3 - SATA3 phy interface control 3
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_3 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *SATA_TP_OUT - SATA3 TP OUT
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: SATA_TP_OUT :: TP_OUT [31:00] */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_MASK                 0xffffffff
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_SHIFT                0
+
+#endif /* #ifndef BCHP_SATA_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_sdio_0_cfg.h b/include/linux/brcmstb/7362a0/bchp_sdio_0_cfg.h
new file mode 100644
index 0000000..7ccf567
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_sdio_0_cfg.h
@@ -0,0 +1,635 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 24 17:25:43 2013
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SDIO_0_CFG_H__
+#define BCHP_SDIO_0_CFG_H__
+
+/***************************************************************************
+ *SDIO_0_CFG - SDIO_0 (CARD) Configuration Registers
+ ***************************************************************************/
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1          0x00410100 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2          0x00410104 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL               0x00410108 /* SDIO TP_OUT Control Register */
+#define BCHP_SDIO_0_CFG_CAP_REG0                 0x0041010c /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_CAP_REG1                 0x00410110 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET1                  0x00410114 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET2                  0x00410118 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY           0x0041011c /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV               0x00410120 /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_IP_DLY                   0x00410130 /* SDIO Host input delay register */
+#define BCHP_SDIO_0_CFG_OP_DLY                   0x00410134 /* SDIO Host output delay register */
+#define BCHP_SDIO_0_CFG_TUNING                   0x00410138 /* SDIO Host tuning configuration register */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL                0x0041013c /* SDIO Host 1p8V control logic select register */
+#define BCHP_SDIO_0_CFG_SCRATCH                  0x004101fc /* SDIO Scratch Register */
+#define BCHP_SDIO_0_CFG_VERSION                  0x004101f0 /* SDIO VERSION Register */
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL1 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_SEL_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_MASK    0x80000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_SHIFT   31
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_DEFAULT 0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_LEV [30:30] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_MASK       0x40000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_SHIFT      30
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved0 [29:29] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved0_MASK             0x20000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved0_SHIFT            29
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: RETUNING_REQ [28:28] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_MASK          0x10000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_SHIFT         28
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DDR_TAP_DELAY [27:24] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_MASK         0x0f000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_SHIFT        24
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_DEFAULT      0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DELAY_CTRL [23:21] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_MASK            0x00e00000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_SHIFT           21
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_DEFAULT         0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_ENA [20:20] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_MASK       0x00100000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_SHIFT      20
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_PULSE [19:19] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_MASK     0x00080000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_SHIFT    19
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DATA_PENDING [18:18] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_MASK          0x00040000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_SHIFT         18
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WR_FLUSH [17:17] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_MASK              0x00020000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_SHIFT             17
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: MF_NUM_WR [16:16] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_MASK             0x00010000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_SHIFT            16
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WORD_ABO [15:15] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_MASK              0x00008000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_SHIFT             15
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NBO [14:14] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_MASK             0x00004000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_SHIFT            14
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NHW [13:13] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_MASK             0x00002000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_SHIFT            13
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: BUFFER_ABO [12:12] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_MASK            0x00001000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_SHIFT           12
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_DEFAULT         0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_BUF_ACC [11:11] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_MASK           0x00000800
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_SHIFT          11
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_DEFAULT        0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SEQ_EN [10:10] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_MASK            0x00000400
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_SHIFT           10
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_DEFAULT         0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_RD_THRESH [09:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_MASK         0x000003e0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_SHIFT        5
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_DEFAULT      0x00000002
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SIZE [04:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_MASK              0x0000001f
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_SHIFT             0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_DEFAULT           0x00000004
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL2 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved0 [31:08] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_MASK             0xffffff00
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_SHIFT            8
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_BYTE [07:06] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_MASK     0x000000c0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_SHIFT    6
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved1 [05:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_MASK             0x00000020
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_SHIFT            5
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_HW [04:04] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_MASK       0x00000010
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_SHIFT      4
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_DEFAULT    0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_RD [03:02] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_MASK      0x0000000c
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_SHIFT     2
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_DEFAULT   0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_WR [01:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_MASK      0x00000003
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_SHIFT     0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_DEFAULT   0x00000000
+
+/***************************************************************************
+ *TP_OUT_SEL - SDIO TP_OUT Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TP_OUT_SEL :: reserved0 [31:01] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_MASK                  0xfffffffe
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_SHIFT                 1
+
+/* SDIO_0_CFG :: TP_OUT_SEL :: TP_OUT_SELECT [00:00] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_MASK              0x00000001
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_SHIFT             0
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *CAP_REG0 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG0 :: DDR50_SUPPORT [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_SHIFT               31
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SD104_SUPPORT [30:30] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_MASK                0x40000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_SHIFT               30
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDR50 [29:29] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_MASK                        0x20000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_SHIFT                       29
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_DEFAULT                     0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SLOT_TYPE [28:27] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_MASK                    0x18000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_SHIFT                   27
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_DEFAULT                 0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: ASYNCH_INT_SUPPORT [26:26] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_MASK           0x04000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_SHIFT          26
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_DEFAULT        0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 64B_SYS_BUS_SUPPORT [25:25] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_MASK          0x02000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_SHIFT         25
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_DEFAULT       0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: 1_8V_SUPPORT [24:24] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_MASK                 0x01000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_SHIFT                24
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_0V_SUPPORT [23:23] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_MASK                 0x00800000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_SHIFT                23
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_3V_SUPPORT [22:22] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_MASK                 0x00400000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_SHIFT                22
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_DEFAULT              0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SUSP_RES_SUPPORT [21:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_MASK             0x00200000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_SHIFT            21
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDMA_SUPPORT [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_MASK                 0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_SHIFT                20
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_DEFAULT              0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: HIGH_SPEED_SUPPORT [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_MASK           0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_SHIFT          19
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_DEFAULT        0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: ADMA2_SUPPORT [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_MASK                0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_SHIFT               18
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_DEFAULT             0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: EXTENDED_MEDIA_SUPPORT [17:17] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_MASK       0x00020000
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_SHIFT      17
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_DEFAULT    0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: MAX_BL [16:15] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_MASK                       0x00018000
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_SHIFT                      15
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_DEFAULT                    0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: BASE_FREQ [14:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_MASK                    0x00007f80
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_SHIFT                   7
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_DEFAULT                 0x00000032
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_CLK_UNIT [06:06] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_MASK             0x00000040
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_SHIFT            6
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_FREQ [05:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_MASK                 0x0000003f
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_SHIFT                0
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_DEFAULT              0x00000032
+
+/***************************************************************************
+ *CAP_REG1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_REG_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_MASK             0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_SHIFT            31
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved0 [30:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_MASK                    0x7fe00000
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_SHIFT                   21
+
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_1_stuff [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_MASK                  0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_SHIFT                 20
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_BLK_MODE [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_MASK                 0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_SHIFT                19
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_MODE [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_MASK                     0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_SHIFT                    18
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_DEFAULT                  0x00000001
+
+/* SDIO_0_CFG :: CAP_REG1 :: CLK_MULT [17:10] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_MASK                     0x0003fc00
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_SHIFT                    10
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_MODES [09:08] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_MASK               0x00000300
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_SHIFT              8
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_DEFAULT            0x00000002
+
+/* SDIO_0_CFG :: CAP_REG1 :: USE_TUNING [07:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_MASK                   0x00000080
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_SHIFT                  7
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_DEFAULT                0x00000001
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_TIMER [06:03] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_MASK               0x00000078
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_SHIFT              3
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_DEFAULT            0x0000000a
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_D_SUPPORT [02:02] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_MASK             0x00000004
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_SHIFT            2
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_C_SUPPORT [01:01] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_MASK             0x00000002
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_SHIFT            1
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_A_SUPPORT [00:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_MASK             0x00000001
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_SHIFT            0
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PRESET1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET1 :: PRESET1_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET100 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_MASK                     0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_SHIFT                    16
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET50 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_MASK                      0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_SHIFT                     0
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_DEFAULT                   0x00000001
+
+/***************************************************************************
+ *PRESET2 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET2 :: PRESET2_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET2 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET25 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_MASK                      0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_SHIFT                     16
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_DEFAULT                   0x00000002
+
+/* SDIO_0_CFG :: PRESET2 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET12P5 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_MASK                    0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_SHIFT                   0
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_DEFAULT                 0x00000003
+
+/***************************************************************************
+ *SD_CLOCK_DELAY - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved0 [31:31] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_SHIFT             31
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: CLOCK_DELAY_OVERRIDE [30:30] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_MASK   0x40000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_SHIFT  30
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_DEFAULT 0x00000001
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_SEL [29:29] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_MASK        0x20000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_SHIFT       29
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_DEFAULT     0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved1 [28:12] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved1_MASK              0x1ffff000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved1_SHIFT             12
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: OUTPUT_CLOCK_DELAY [11:08] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_MASK     0x00000f00
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_SHIFT    8
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INTERNAL_CLOCK_DELAY [07:04] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_MASK   0x000000f0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_SHIFT  4
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_DEFAULT 0x0000000f
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_MASK      0x0000000f
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_SHIFT     0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_DEFAULT   0x0000000f
+
+/***************************************************************************
+ *SD_PAD_DRV - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_PAD_DRV :: OVERRIDE_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_SHIFT               31
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved0 [30:23] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_MASK                  0x7f800000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_SHIFT                 23
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CLK_VAL [22:20] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_MASK                    0x00700000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_SHIFT                   20
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved1 [19:19] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_MASK                  0x00080000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_SHIFT                 19
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CMD_VAL [18:16] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_MASK                    0x00070000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_SHIFT                   16
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved2 [15:15] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_MASK                  0x00008000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_SHIFT                 15
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT3_VAL [14:12] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_MASK                   0x00007000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_SHIFT                  12
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved3 [11:11] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_MASK                  0x00000800
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_SHIFT                 11
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT2_VAL [10:08] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_MASK                   0x00000700
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_SHIFT                  8
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved4 [07:07] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_MASK                  0x00000080
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_SHIFT                 7
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT1_VAL [06:04] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_MASK                   0x00000070
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_SHIFT                  4
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved5 [03:03] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_MASK                  0x00000008
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_SHIFT                 3
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT0_VAL [02:00] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_MASK                   0x00000007
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_SHIFT                  0
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_DEFAULT                0x00000005
+
+/***************************************************************************
+ *IP_DLY - SDIO Host input delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_DEFAULT                   0x00000000
+
+/* SDIO_0_CFG :: IP_DLY :: FORCE_USE_IP_TUNE_CLK [30:30] */
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_MASK          0x40000000
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_SHIFT         30
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: IP_DLY :: reserved0 [29:18] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_MASK                      0x3ffc0000
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: IP_DLY :: IP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_DEFAULT               0x00000003
+
+/* SDIO_0_CFG :: IP_DLY :: reserved1 [15:06] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_MASK                      0x0000ffc0
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_SHIFT                     6
+
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_DELAY [05:00] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_MASK                   0x0000003f
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_DEFAULT                0x00000028
+
+/***************************************************************************
+ *OP_DLY - SDIO Host output delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_DEFAULT                   0x00000000
+
+/* SDIO_0_CFG :: OP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: OP_DLY :: OP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: OP_DLY :: reserved1 [15:04] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_MASK                      0x0000fff0
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_SHIFT                     4
+
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_MASK                   0x0000000f
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TUNING - SDIO Host tuning configuration register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TUNING :: reserved0 [31:04] */
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_MASK                      0xfffffff0
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_SHIFT                     4
+
+/* SDIO_0_CFG :: TUNING :: TUNING_CMD_SUCCESS_CNT [03:00] */
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_MASK         0x0000000f
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_SHIFT        0
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_DEFAULT      0x00000008
+
+/***************************************************************************
+ *VOLT_CTRL - SDIO Host 1p8V control logic select register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VOLT_CTRL :: reserved0 [31:05] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_MASK                   0xffffffe0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_SHIFT                  5
+
+/* SDIO_0_CFG :: VOLT_CTRL :: POW_INV_EN [04:04] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_MASK                  0x00000010
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_SHIFT                 4
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_VAL [03:03] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_MASK                    0x00000008
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_SHIFT                   3
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_DEFAULT                 0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_INV_EN [02:02] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_MASK                 0x00000004
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_SHIFT                2
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_CTRL_SEL [01:00] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_MASK               0x00000003
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_SHIFT              0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SCRATCH - SDIO Scratch Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SCRATCH :: SCRATCH_BITS [31:00] */
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_MASK                  0xffffffff
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_SHIFT                 0
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_DEFAULT               0x00000000
+
+/***************************************************************************
+ *VERSION - SDIO VERSION Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VERSION :: SD_VER [31:24] */
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_MASK                        0xff000000
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_SHIFT                       24
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_DEFAULT                     0x00000030
+
+/* SDIO_0_CFG :: VERSION :: MMC_VER [23:16] */
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_MASK                       0x00ff0000
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_SHIFT                      16
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_DEFAULT                    0x00000044
+
+/* SDIO_0_CFG :: VERSION :: REV [15:08] */
+#define BCHP_SDIO_0_CFG_VERSION_REV_MASK                           0x0000ff00
+#define BCHP_SDIO_0_CFG_VERSION_REV_SHIFT                          8
+#define BCHP_SDIO_0_CFG_VERSION_REV_DEFAULT                        0x000000a9
+
+/* SDIO_0_CFG :: VERSION :: A2S_VER [07:00] */
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_MASK                       0x000000ff
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_SHIFT                      0
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_DEFAULT                    0x00000001
+
+#endif /* #ifndef BCHP_SDIO_0_CFG_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/7362a0/bchp_sun_top_ctrl.h
new file mode 100644
index 0000000..d4ca962
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_sun_top_ctrl.h
@@ -0,0 +1,6198 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 24 17:25:43 2013
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SUN_TOP_CTRL_H__
+#define BCHP_SUN_TOP_CTRL_H__
+
+/***************************************************************************
+ *SUN_TOP_CTRL - Top Control registers
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID         0x00404000 /* Chip family ID */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID             0x00404004 /* Product Revision ID */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x0040401c /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x00404020 /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x00404024 /* Bond option value register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x00404028 /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x0040402c /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x00404030 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x00404034 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x00404038 /* Semaphore channel 0 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x0040403c /* Semaphore channel 1 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x00404040 /* Semaphore channel 2 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x00404044 /* Semaphore channel 3 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x00404048 /* Semaphore channel 4 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x0040404c /* Semaphore channel 5 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x00404050 /* Semaphore channel 6 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x00404054 /* Semaphore channel 7 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x00404058 /* Semaphore channel 8 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x0040405c /* Semaphore channel 9 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x00404060 /* Semaphore channel 10 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x00404064 /* Semaphore channel 11 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x00404068 /* Semaphore channel 12 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x0040406c /* Semaphore channel 13 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x00404070 /* Semaphore channel 14 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x00404074 /* Semaphore channel 15 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x00404078 /* General watchdog timer 0 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x0040407c /* General watchdog timer 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x00404080 /* General control register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x00404084 /* General control register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x00404088 /* General control register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x0040408c /* General control register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x00404090 /* General control register 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x00404094 /* General control register 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x00404098 /* General status register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x0040409c /* General status register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x004040a0 /* General status register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x00404100 /* Pinmux control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x00404104 /* Pinmux control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x00404108 /* Pinmux control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x0040410c /* Pinmux control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x00404110 /* Pinmux control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x00404114 /* Pinmux control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x00404118 /* Pinmux control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x0040411c /* Pinmux control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x00404120 /* Pinmux control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x00404124 /* Pinmux control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10        0x00404128 /* Pinmux control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11        0x0040412c /* Pinmux control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12        0x00404130 /* Pinmux control register 12 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13        0x00404134 /* Pinmux control register 13 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14        0x00404138 /* Pinmux control register 14 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15        0x0040413c /* Pinmux control register 15 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x00404140 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x00404144 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x00404148 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x0040414c /* Pad pull-up/pull-down control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x00404150 /* Pad pull-up/pull-down control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5     0x00404154 /* Pad pull-up/pull-down control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6     0x00404158 /* Pad pull-up/pull-down control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7     0x0040415c /* Pad pull-up/pull-down control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8     0x00404160 /* Pad pull-up/pull-down control register 8 */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x00404164 /* Bypass clock unselect register 0 */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x00404300 /* Reset control */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE    0x00404304 /* Reset source enable */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET        0x00404308 /* Software master reset */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION     0x0040430c /* Hardware reset extension */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR          0x00404310 /* Reset Monitor */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x00404314 /* Reset history */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET          0x00404318 /* Software init 0 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR        0x0040431c /* Software init 0 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS       0x00404320 /* Software init 0 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR  0x00404324 /* Security software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET          0x00404330 /* Software init 1 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR        0x00404334 /* Software init 1 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS       0x00404338 /* Software init 1 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR  0x0040433c /* Security software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x00404364 /* Scratch register */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x00404368 /* Spare control bits reserved for future use */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x00404380 /* Test port control */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x00404384 /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x00404388 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x0040438c /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x00404390 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x00404394 /* EJTAG input bus enables */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x00404398 /* EJTAG output select */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL        0x0040439c /* UART Router select */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL             0x004043a0 /* VTRAP Control */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS           0x004043a4 /* VTRAP Status */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x00404400 /* Serial Slave Port configuration register */
+#define BCHP_SUN_TOP_CTRL_SERS_REV               0x00404420 /* SERS Revision Register */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x00404424 /* SERS Configuration Register */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x00404514 /* Block select for RO testmode */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION     0x00404518 /* Test configuration */
+
+/***************************************************************************
+ *CHIP_FAMILY_ID - Chip family ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT    0x73620000
+
+/***************************************************************************
+ *PRODUCT_ID - Product Revision ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK               0xffffffff
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT            0x73620000
+
+/***************************************************************************
+ *BSP_FEATURE_TABLE_ADDR - BSP feature table address
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_VALUE_0 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [07:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT   0x00000007
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [03:03] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd [02:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_MASK            0x00000007
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STRAP_VALUE_1 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xfffffff0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            4
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias_sel [03:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_MASK  0x0000000e
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_DEFAULT 0x00000004
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK     0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT  0x00000001
+
+/***************************************************************************
+ *BOND_STATUS - Bond option value register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1
+
+/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_0 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_0 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rsvd_ob_disable [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ob_disable_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ob_disable_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ob_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rsvd_ds_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ds_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ds_disable_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ds_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rsvd_isdbt_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_isdbt_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_isdbt_disable_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_isdbt_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_genet_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet_disable_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avc_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_directv_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sata_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sds0_tuner_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hd_display_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ephy_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tfec_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ldpc_disable [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_chip_variant [13:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_chip_variant_MASK 0x00003c00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_chip_variant_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_chip_variant_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 0x00000003
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_TEST_1 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_29 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_28 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_27 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_26 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_25 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_24 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_23 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_22 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_21 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_20 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_19 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_18 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_17 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_16 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_15 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_14 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_0 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_alt_prod_base_rev_enable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_alt_prod_base_rev_enable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_alt_prod_base_rev_enable_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_alt_prod_base_rev_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_0 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_0 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rsvd_ob_disable [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_ob_disable_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_ob_disable_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rsvd_ds_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_ds_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_ds_disable_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rsvd_isdbt_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_isdbt_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_isdbt_disable_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_genet_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet_disable_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avc_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avc_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avc_disable_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_directv_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sata_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sds0_tuner_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sds0_tuner_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sds0_tuner_disable_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hd_display_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ephy_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tfec_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec_disable_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ldpc_disable [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc_disable_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc_disable_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_chip_variant [13:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_chip_variant_MASK 0x00003c00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_chip_variant_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_1 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_29 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_28 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_27 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_26 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_25 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_24 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_23 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_22 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_21 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_20 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_19 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_18 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_17 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_16 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_15 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_14 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 6
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_0 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_SHIFT 2
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_alt_prod_base_rev_enable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_alt_prod_base_rev_enable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_alt_prod_base_rev_enable_SHIFT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_SHIFT 0
+
+/***************************************************************************
+ *SEMAPHORE_0 - Semaphore channel 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_1 - Semaphore channel 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_2 - Semaphore channel 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_3 - Semaphore channel 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_4 - Semaphore channel 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_5 - Semaphore channel 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_6 - Semaphore channel 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_7 - Semaphore channel 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_8 - Semaphore channel 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_9 - Semaphore channel 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_10 - Semaphore channel 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_11 - Semaphore channel 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_12 - Semaphore channel 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_13 - Semaphore channel 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_14 - Semaphore channel 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_15 - Semaphore channel 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_0 - General watchdog timer 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_1 - General watchdog timer 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_1 - General control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0xffff0000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           16
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_2 - General control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: usb0_pwrflt_2_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: usb0_pwrflt_1_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_3 - General control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_4 - General control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_5 - General control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK          0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT         8
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_1 - General status register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_2 - General status register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   8
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_mode [07:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_MASK 0x000000f0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_mode [03:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK    0xffff8000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT   15
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_vregcntl [14:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_MASK 0x00007ffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_pwrdn [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_MASK    0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_SHIFT   1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_vregcntl_en [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK    0xfffffff0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT   4
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_3_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_2_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xffc00000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   22
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_pwrdn [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_MASK    0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_SHIFT   21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_vregcntl [20:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_MASK 0x001ffffe
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_vregcntl_en [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xffffff80
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_hys_en [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_oeb [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_do [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_src [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_16MA 7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_02 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_GPIO_02           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_EBI_ADDR2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MII_TX_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_PM_GPIO_02        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_01 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_GPIO_01           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_EBI_ADDR1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MII_RX_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_PM_GPIO_01        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_00 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_GPIO_00           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_EBI_ADDR0         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MII_RX_DV         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_PM_GPIO_00        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_sck [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_MASK               0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_SHIFT              16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_DEFAULT            0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_SF_SCK             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_PM_SF_SCK          1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_mosi [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_SF_MOSI           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_PM_SF_MOSI        1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_miso [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_SF_MISO           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_PM_SF_MISO        1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_24 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_GPIO_24           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_SDS0_DSEC_TXEN    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_PM_GPIO_24        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_23 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_GPIO_23           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_SDS0_DSEC_TXOUT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_PM_GPIO_23        2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_10 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_GPIO_10           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_EBI_ADDR10        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MII_TXD_00        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_PM_GPIO_10        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_09 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_GPIO_09           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_EBI_ADDR9         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MII_TXD_01        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_PM_GPIO_09        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_08 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_GPIO_08           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_EBI_ADDR8         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MII_TXD_02        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_PM_GPIO_08        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_07 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_GPIO_07           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_EBI_ADDR7         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_MII_TXD_03        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_PM_GPIO_07        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_06 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_GPIO_06           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_EBI_ADDR6         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_MII_RXD_00        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_PM_GPIO_06        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_05 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_GPIO_05           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_EBI_ADDR5         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_MII_RXD_01        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_PM_GPIO_05        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_04 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_GPIO_04           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_EBI_ADDR4         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_MII_RXD_02        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_PM_GPIO_04        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_03 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_GPIO_03           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_EBI_ADDR3         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_MII_RXD_03        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_PM_GPIO_03        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_18 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_GPIO_18           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_EBI_CS0B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_PM_GPIO_18        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_17 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_GPIO_17           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_EBI_RWB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_PM_GPIO_17        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_16 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_GPIO_16           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_EBI_WE1B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_PM_GPIO_16        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_15 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_GPIO_15           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_EBI_WAITB         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_PM_GPIO_15        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_14 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_GPIO_14           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_EBI_ADDR14        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_MII_COL           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_PM_GPIO_14        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_13 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_GPIO_13           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_EBI_ADDR13        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_MII_TX_ER         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_PM_GPIO_13        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_12 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_GPIO_12           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_EBI_ADDR12        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_MII_RX_ER         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_PM_GPIO_12        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_11 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_GPIO_11           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_EBI_ADDR11        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_MII_TX_EN         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_PM_GPIO_11        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_28 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_GPIO_28           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_EBI_DATA3         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_TP_OUT_23         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_TP_IN_23          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_PM_GPIO_28        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_27 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_GPIO_27           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_EBI_DATA2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_TP_OUT_22         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_TP_IN_22          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_PM_GPIO_27        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_26 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_GPIO_26           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_EBI_DATA1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_TP_OUT_21         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_TP_IN_21          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_PM_GPIO_26        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_25 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_GPIO_25           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_EBI_DATA0         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_TP_OUT_20         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_TEST_THP          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_TP_IN_20          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_PM_GPIO_25        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_22 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_GPIO_22           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_EBI_CS4B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_SPI_M_SS0B        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_PM_GPIO_22        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_21 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_GPIO_21           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_EBI_CS3B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_PM_GPIO_21        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_20 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_GPIO_20           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_EBI_CS2B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_TP_OUT_07         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_PM_GPIO_20        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_19 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_GPIO_19           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_EBI_CS1B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_PM_GPIO_19        2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_4 - Pinmux control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_36 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_GPIO_36           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_EBI_DATA11        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_SC1_IO            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_PM_GPIO_36        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_35 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_GPIO_35           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_EBI_DATA10        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_SC1_RST           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_PM_GPIO_35        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_34 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_GPIO_34           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_EBI_DATA9         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_SC1_CLK           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_PM_GPIO_34        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_33 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_GPIO_33           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_EBI_DATA8         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_SC1_VCC           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_PM_GPIO_33        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_32 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_GPIO_32           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_EBI_DATA7         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_OUT_27         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_IN_27          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_OUT_21         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_PM_GPIO_32        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_31 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_GPIO_31           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_EBI_DATA6         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_OUT_26         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_IN_26          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_OUT_20         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_PM_GPIO_31        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_30 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_GPIO_30           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_EBI_DATA5         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_TP_OUT_25         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_TP_IN_25          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_PM_GPIO_30        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_29 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_GPIO_29           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_EBI_DATA4         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_TP_OUT_24         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_TP_IN_24          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_PM_GPIO_29        4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_5 - Pinmux control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_44 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_GPIO_44           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_EBI_TSB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_OUT_31         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_IN_31          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_IN_19          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_OUT_26         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_PM_GPIO_44        6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_43 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_GPIO_43           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_EBI_DSB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_OUT_30         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_IN_30          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_IN_18          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_OUT_25         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_PM_GPIO_43        6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_42 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_GPIO_42           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_EBI_WE0B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_OUT_29         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_IN_29          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_OUT_23         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_PM_GPIO_42        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_41 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_GPIO_41           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_EBI_RDB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_OUT_28         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_IN_28          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_OUT_22         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_PM_GPIO_41        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_40 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_GPIO_40           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_EBI_DATA15        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SPI_M_SCK         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_MII_COL           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SC1_AUX2          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_PM_GPIO_40        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_39 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_GPIO_39           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_EBI_DATA14        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SPI_M_MISO        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_MII_TX_ER         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SC1_AUX1          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_PM_GPIO_39        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_38 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_GPIO_38           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_EBI_DATA13        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SPI_M_MOSI        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_MII_RX_ER         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SC1_VPP           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_PM_GPIO_38        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_37 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_GPIO_37           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_EBI_DATA12        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_SC1_PRES          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_PM_GPIO_37        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_6 - Pinmux control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_52 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_GPIO_52           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_POD2CHIP_MDI5     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_PPKT_I_DATA_5     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_PM_GPIO_52        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_51 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_GPIO_51           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_POD2CHIP_MDI4     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_PPKT_I_DATA_4     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_PM_GPIO_51        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_50 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_GPIO_50           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_POD2CHIP_MDI3     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_PPKT_I_DATA_3     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_PM_GPIO_50        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_49 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_GPIO_49           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_POD2CHIP_MDI2     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_PPKT_I_DATA_2     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_PM_GPIO_49        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_48 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_GPIO_48           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_POD2CHIP_MDI1     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_PPKT_I_DATA_1     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_PM_GPIO_48        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_47 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_GPIO_47           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_POD2CHIP_MDI0     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_PPKT_I_DATA_0     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_PM_GPIO_47        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_46 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_GPIO_46           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_POD2CHIP_MCLKI    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_PPKT_I_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_EBI_ADDR14        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_PM_GPIO_46        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_45 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_GPIO_45           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_NAND_RBB          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_TP_OUT_16         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_PM_GPIO_45        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_7 - Pinmux control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_60 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_GPIO_60           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_CHIP2POD_MDO2     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_RMXP_DATA2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_EBI_ADDR20        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_SDS0_O_DATA_2     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_PM_GPIO_60        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_59 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_GPIO_59           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_CHIP2POD_MDO1     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_RMXP_DATA1        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_EBI_ADDR19        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_SDS0_O_DATA_1     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_PM_GPIO_59        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_58 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_GPIO_58           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_CHIP2POD_MDO0     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_RMXP_DATA0        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_EBI_ADDR18        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_SDS0_O_DATA_0     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_PM_GPIO_58        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_57 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_GPIO_57           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_CHIP2POD_MCLKO    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_RMXP_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_EBI_ADDR15        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_SDS0_O_CLK        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_PM_GPIO_57        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_56 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_GPIO_56           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_POD2CHIP_MIVAL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_PPKT_I_VALID      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_PM_GPIO_56        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_55 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_GPIO_55           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_POD2CHIP_MISTRT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_PPKT_I_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_PM_GPIO_55        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_54 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_GPIO_54           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_POD2CHIP_MDI7     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_PPKT_I_DATA_7     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_PM_GPIO_54        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_53 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_GPIO_53           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_POD2CHIP_MDI6     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_PPKT_I_DATA_6     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_PM_GPIO_53        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_8 - Pinmux control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_68 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_GPIO_68           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_POD2CHIP_MICLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_PPKT_I_ERROR      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_EBI_ADDR13        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_PM_GPIO_68        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_67 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_GPIO_67           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_CHIP2POD_MOVAL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_RMXP_VALID        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_EBI_ADDR16        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_SDS0_O_VALID      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_PM_GPIO_67        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_66 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_GPIO_66           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_CHIP2POD_MOSTRT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_RMXP_SYNC         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_EBI_ADDR17        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_SDS0_O_SYNC       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_PM_GPIO_66        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_65 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_GPIO_65           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_CHIP2POD_MDO7     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_RMXP_DATA7        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_EBI_ADDR25        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_SDS0_O_DATA_7     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_PM_GPIO_65        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_64 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_GPIO_64           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_CHIP2POD_MDO6     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_RMXP_DATA6        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_EBI_ADDR24        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_SDS0_O_DATA_6     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_PM_GPIO_64        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_63 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_GPIO_63           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_CHIP2POD_MDO5     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_RMXP_DATA5        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_EBI_ADDR23        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_SDS0_O_DATA_5     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_PM_GPIO_63        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_62 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_GPIO_62           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_CHIP2POD_MDO4     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_RMXP_DATA4        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_EBI_ADDR22        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_SDS0_O_DATA_4     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_PM_GPIO_62        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_61 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_GPIO_61           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_CHIP2POD_MDO3     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_RMXP_DATA3        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_EBI_ADDR21        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_SDS0_O_DATA_3     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_PM_GPIO_61        5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_9 - Pinmux control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_76 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_GPIO_76           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_RMX0_SYNC         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_PKT1_SYNC         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_SDS0_DEMOD_SYNC   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_PM_GPIO_76        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_75 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_GPIO_75           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_RMX0_DATA         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_PKT1_DATA         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_CLK_OBSRV3        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_SDS0_DEMOD_DATA   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_PM_GPIO_75        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_74 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_GPIO_74           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_RMX0_CLK          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_PKT1_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_CLK_OBSRV2        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_SDS0_DEMOD_CLK    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_PM_GPIO_74        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_73 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_GPIO_73           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_RSVD_MPOD_M_SDI   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_PM_GPIO_73        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_72 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_DEFAULT           0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_GPIO_72           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_RSVD_MPOD_M_SDO   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_EBI_ADDR0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_PM_GPIO_72        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_71 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_DEFAULT           0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_GPIO_71           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_RSVD_MPOD_SCLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_EBI_ADDR1         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_PM_GPIO_71        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_70 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_DEFAULT           0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_GPIO_70           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_RSVD_MPOD_SCTL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_EBI_ADDR2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_SDS0_O_ERROR      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_PM_GPIO_70        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_69 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_GPIO_69           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_CHIP2POD_MOCLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_RMXP_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_EBI_ADDR12        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_AUD_FS_CLK1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_PM_GPIO_69        5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_10 - Pinmux control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_84 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_GPIO_84          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_SC0_AUX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_I2S_DATA0_IN     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_TP_OUT_13        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_PM_GPIO_84       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_83 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_GPIO_83          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_SC0_PRES         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_I2S_CLK0_IN      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_TP_OUT_12        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_PM_GPIO_83       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_82 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_GPIO_82          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_SC0_IO           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_TP_OUT_11        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_PM_GPIO_82       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_81 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_GPIO_81          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_SC0_RST          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_TP_OUT_10        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_PM_GPIO_81       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_80 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_GPIO_80          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_SC0_CLK          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_TP_OUT_09        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_PM_GPIO_80       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_79 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_GPIO_79          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_SC0_VCC          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_TP_OUT_08        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_PM_GPIO_79       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_78 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_GPIO_78          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_RMX0_PAUSE       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PKT1_ERROR       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PKT3_DATA        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_I2S_LR0_IN       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SDS0_DSEC_VCTL   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SDS0_DEMOD_ERR   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PM_GPIO_78       7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_77 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_GPIO_77          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_RMX0_VALID       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PKT1_VALID       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PKT3_CLK         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SPI_M_SS1B       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SDS0_DSEC_SELVTOP 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SDS0_DEMOD_VALID 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PM_GPIO_77       7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_11 - Pinmux control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_92 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_GPIO_92          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_UART_RX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_IR_OUT           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_ALT_TP_IN_02     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_POD2CHIP_MCLKI   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_PM_GPIO_92       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_91 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_GPIO_91          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_UART_TX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_PWM0             2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_ALT_TP_OUT_02    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_POD_EBI_DSB      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_PM_GPIO_91       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_90 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_GPIO_90          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_UART_RX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_VEC_VSYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_ALT_TP_IN_01     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_POD_EBI_WE0B     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_PM_GPIO_90       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_89 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_GPIO_89          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_UART_TX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_VEC_HSYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_ALT_TP_OUT_01    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_POD_EBI_RDB      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_PM_GPIO_89       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_88 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_GPIO_88          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_SPI_S_SSB        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_UART_RX0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_ALT_TP_IN_00     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_PM_GPIO_88       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_87 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_GPIO_87          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_SPI_S_MISO       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_UART_TX0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_ALT_TP_OUT_00    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_PM_GPIO_87       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_86 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_GPIO_86          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_SC0_VPP          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_USB0_PWRFLT_1    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_TP_OUT_15        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_PM_GPIO_86       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_85 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_GPIO_85          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_SC0_AUX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_I2S_LR0_IN       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_TP_OUT_14        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_USB0_PWRFLT_2    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_PM_GPIO_85       5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_12 - Pinmux control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_101 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_GPIO_101        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_USB0_PWRON_1    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_RMX1_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SDS0_DSEC_SELVTOP 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_TP_OUT_17       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SDS0_RF_AGC     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_ENET_ACTIVITY   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_PM_GPIO_101     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_100 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_GPIO_100        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_PKT2_ERROR      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SC1_VPP         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_VEC_HSYNC       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_UART_CTS2       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_CODEC_FSYNCB    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SPI_M_SS1B      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SC1_PRES        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_PM_GPIO_100     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_99 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_GPIO_99          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PKT2_VALID       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PKT3_SYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_IR_OUT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_UART_RX2         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_CODEC_SDI        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SPI_M_MISO       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SC1_IO           7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PM_GPIO_99       8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_98 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_GPIO_98          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_PKT2_SYNC        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_CODEC_MCLK       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SPI_M_SCK        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SC1_RST          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_PM_GPIO_98       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_97 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_GPIO_97          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_PKT2_DATA        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_UART_RTS2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_CODEC_SDO        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SPI_M_SS0B       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SC1_CLK          5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_PM_GPIO_97       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_96 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_GPIO_96          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_PKT2_CLK         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_UART_TX2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_CODEC_SCLK       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SPI_M_MOSI       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SC1_VCC          5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_PM_GPIO_96       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_94 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_GPIO_94          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SF_WPB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_EXT_IRQ3         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_PWM0             3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_UART_RTS0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_I2S_DATA0_IN     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SDS0_DSEC_TXEN   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_PM_GPIO_94       7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_93 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_GPIO_93          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SF_HOLDB         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_EXT_IRQ2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_VEC_VSYNC        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_UART_CTS0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_I2S_CLK0_IN      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SDS0_DSEC_TXOUT  6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_PM_GPIO_93       7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_13 - Pinmux control register 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_110 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_GPIO_110        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_MII_CRS         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_EBI_ADDR15      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_PM_GPIO_110     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_109 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_GPIO_109        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_MII_COL         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_PKT4_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR0_IN      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR0_OUT     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR1_OUT     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_SC1_AUX2        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_PM_GPIO_109     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_108 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_GPIO_108        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_MII_TX_ER       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_PKT4_DATA       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA0_IN    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA0_OUT   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA1_OUT   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_SC1_AUX1        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_TP_IN_31        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_PM_GPIO_108     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_107 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_GPIO_107        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_MII_RX_ER       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_PKT4_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK0_IN     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK0_OUT    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK1_OUT    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_SC1_VPP         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_TP_IN_30        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_PM_GPIO_107     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_105 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_GPIO_105        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_ENET_ACTIVITY   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_PWM1            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_CLK_OBSRV0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_CLK_27          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_AUD_FS_CLK0     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_SC_CLK_OUT      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_TP_OUT_19       7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_PM_GPIO_105     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_104 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_GPIO_104        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_USB0_PWRFLT_2   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_EXT_IRQ5        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_RMX1_SYNC       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_IR_INT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_SATA_MDCLK      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_PM_GPIO_104     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_103 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_GPIO_103        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_USB0_PWRFLT_1   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_EXT_IRQ4        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_RMX1_PAUSE      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_P1_INTR_1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_SATA_MDIO       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_PM_GPIO_103     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_102 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_GPIO_102        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_USB0_PWRON_2    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_RMX1_DATA       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SDS0_DSEC_VCTL  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_TP_OUT_18       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SDS0_IF_AGC     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_ENET_LINK       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_PM_GPIO_102     7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_14 - Pinmux control register 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_118 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_GPIO_118        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_RGMII_TXD_03    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_EBI_ADDR23      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SDIO0_DAT3      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_TP_OUT_27       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_PM_GPIO_118     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_117 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_GPIO_117        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_RGMII_RXD_00    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_EBI_ADDR22      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SDIO0_LED       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_TP_OUT_26       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_PM_GPIO_117     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_116 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_GPIO_116        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_RGMII_RXD_01    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_EBI_ADDR21      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SDIO0_CLK       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_TP_OUT_25       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_PM_GPIO_116     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_115 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_GPIO_115        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_RGMII_RXD_02    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_EBI_ADDR20      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_SDIO0_PWR0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_TP_OUT_24       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_PM_GPIO_115     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_114 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_GPIO_114        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_RGMII_RXD_03    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_EBI_ADDR19      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_SDIO0_WPROT     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_TP_OUT_23       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_PM_GPIO_114     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_113 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_GPIO_113        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_RGMII_TX_CLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_EBI_ADDR18      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_SDIO0_PRES      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_TP_OUT_22       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_PM_GPIO_113     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_112 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_GPIO_112        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_RGMII_RX_CLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_EBI_ADDR17      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_SDIO_VCTL       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_TP_OUT_21       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_PM_GPIO_112     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_111 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_GPIO_111        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_RGMII_RX_DV     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_EBI_ADDR16      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_TP_OUT_20       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_PM_GPIO_111     4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_15 - Pinmux control register 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: sgpio_03 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_SGPIO_03        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_BSC_M1_SDA      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_EXT_IRQ7        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_P1_INTR_1       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: sgpio_02 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_SGPIO_02        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_BSC_M1_SCL      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_EXT_IRQ6        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_124 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_GPIO_124        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_RGMII_MDIO      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_PM_GPIO_124     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_123 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_GPIO_123        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_RGMII_MDC       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_PM_GPIO_123     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_122 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_GPIO_122        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_RGMII_TX_EN     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_EBI_ADDR27      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_SDIO0_CMD       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_TP_OUT_31       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_PM_GPIO_122     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_121 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_GPIO_121        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_RGMII_TXD_00    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_EBI_ADDR26      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_SDIO0_DAT0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_TP_OUT_30       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_PM_GPIO_121     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_120 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_GPIO_120        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_RGMII_TXD_01    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_EBI_ADDR25      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_SDIO0_DAT1      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_TP_OUT_29       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_PM_GPIO_120     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_119 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_GPIO_119        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_RGMII_TXD_02    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_EBI_ADDR24      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_SDIO0_DAT2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_TP_OUT_28       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_PM_GPIO_119     5
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_07_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_06_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_05_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_04_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_03_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_02_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_01_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_00_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [13:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x00003c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       10
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_sck_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_MASK  0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_mosi_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_miso_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_24_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_23_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_22_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_21_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_20_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_19_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_18_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_17_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_16_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_15_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_14_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_13_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_12_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_11_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_10_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_09_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_08_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_39_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_38_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_37_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_36_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_35_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_34_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_33_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_32_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_31_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_30_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_29_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_28_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_27_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_26_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_25_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_54_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_53_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_52_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_51_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_50_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_49_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_48_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_47_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_46_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_45_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_44_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_43_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_42_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_41_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_40_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_69_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_68_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_67_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_66_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_65_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_64_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_63_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_62_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_61_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_60_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_59_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_58_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_57_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_56_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_55_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_84_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_83_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_82_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_81_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_80_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_79_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_78_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_77_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_76_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_75_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_74_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_73_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_72_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_71_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_70_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_100_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_99_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_98_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_97_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_96_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_94_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_93_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_92_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_91_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_90_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_89_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_88_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_87_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_86_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_85_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_116_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_115_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_114_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_113_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_112_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_111_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_110_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_109_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_108_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_107_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_105_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_104_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_103_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_102_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_101_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved0 [31:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_MASK        0xffc00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_SHIFT       22
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved1 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_MASK        0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_SHIFT       16
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_124_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_123_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_122_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_121_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_120_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_119_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_118_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_117_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffffc
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       2
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_24 [01:01] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_23 [00:00] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_CTRL - Reset control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0xfffffffe
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               1
+
+/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT   0x00000000
+
+/***************************************************************************
+ *RESET_SOURCE_ENABLE - Reset source enable
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK       0xfffffc00
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT      10
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_MASTER_RESET - Software master reset
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK           0xfffffffe
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT          1
+
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HW_RESET_EXTENSION - Hardware reset extension
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_MONITOR - Reset Monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT  7
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT   6
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT   4
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset history
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:17] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xfffe0000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            17
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [16:16] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 16
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [15:15] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 15
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [14:14] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 14
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [13:13] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 13
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_reset [12:12] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_MASK    0x00001000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT   12
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_reset [11:11] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT    11
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [10:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT       10
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK       0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT      9
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_dl_sw_reset [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK  0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT 8
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 7
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 6
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK   0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT  4
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0
+
+/***************************************************************************
+ *SW_INIT_0_SET - Software init 0 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_MASK           0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_SHIFT          31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_MASK   0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_SHIFT  30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_MASK          0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_MASK   0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_SHIFT  28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_MASK   0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_SHIFT  27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK        0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT       26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_MASK   0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_SHIFT  25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK          0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK   0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT  23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_MASK   0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_SHIFT  22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK          0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT         21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_MASK   0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_SHIFT  20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK         0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT        19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK           0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT          18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK   0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT  17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_MASK         0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_SHIFT        16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK           0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT          15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK           0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT          14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_MASK          0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_SHIFT         13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_MASK   0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_SHIFT  12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_MASK   0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_SHIFT  11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT       10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK           0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT          9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK           0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK           0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT          6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_SHIFT   4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT   0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_CLEAR - Software init 0 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_MASK         0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_SHIFT        31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_MASK        0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_SHIFT       29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK      0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT     26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK        0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT       24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK        0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT       21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK       0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT      19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK         0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT        18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_MASK       0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK         0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT        15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK         0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT        14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_MASK        0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_SHIFT       13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK      0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT     10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK         0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT        9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK         0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK         0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT        6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_STATUS - Software init 0 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_MASK        0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_SHIFT       31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_MASK       0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_SHIFT      29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK       0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK       0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT      21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK      0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT     19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK        0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT       18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_MASK      0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK        0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT       15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK        0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT       14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_MASK       0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_SHIFT      13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK        0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT   2
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT       1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_MASK   0x80000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT  31
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_MASK  0x20000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK  0x01000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK  0x00200000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK   0x00040000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT  18
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK   0x00008000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT  15
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK   0x00004000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT  14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_avd0_sw_init_MASK  0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK   0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT  9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK   0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT  8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT  6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_1_SET - Software init 1 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK             0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT            5
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK        0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT       4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK        0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT       3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_MASK        0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_SHIFT       2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_DEFAULT        0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_CLEAR - Software init 1 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK           0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT          5
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_MASK    0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_SHIFT   1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_MASK         0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_STATUS - Software init 1 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK          0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT         5
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK     0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT    3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_SHIFT  1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_DEFAULT     0x00000001
+
+/***************************************************************************
+ *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK     0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT    5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT  0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xffffffe0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK   0xffffffe0
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT  5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK  0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xffffffe0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 5
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xffffffe0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 5
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL - Spare control bits reserved for future use
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT         0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTRL - Test port control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SOFT_MODEM_TP 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_ICID_TP_OUT 14
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0  0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU     1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R  2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_A  3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T  4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SATA    5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RFM     6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS     16
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK     17
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON     18
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     20
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     21
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE    22
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM    23
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC     25
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVD0    27
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO     30
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA   31
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     33
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0   35
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0    45
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_FTM     51
+
+/***************************************************************************
+ *TEST_PORT_OUT_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_OUT_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TEST_PORT_IN_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EJTAG_INPUT_EN - EJTAG input bus enables
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           3
+
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 4
+
+/***************************************************************************
+ *EJTAG_OUTPUT_SEL - EJTAG output select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         3
+
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 2
+
+/***************************************************************************
+ *UART_ROUTER_SEL - UART Router select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK      0xf0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT     28
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK      0x0f000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT     24
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK      0x00f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK      0x000f0000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK      0x0000f000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK      0x00000f00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_04 4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_05 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_04 4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_05 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK      0x0000000f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_04 4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_05 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15
+
+/***************************************************************************
+ *VTRAP_CTRL - VTRAP Control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK                0xfffff000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT               12
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_threshold [11:11] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_threshold [10:10] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_threshold [09:09] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [08:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x000001f8
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 0x00000018
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_status_clear [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_status_clear [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_status_clear [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VTRAP_STATUS - VTRAP Status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK              0xfffffff8
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT             3
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_status [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_status [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_status [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SSP_CONFIG - Serial Slave Port configuration register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT        0x00000004
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT           0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT     0x00000001
+
+/***************************************************************************
+ *SERS_REV - SERS Revision Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16
+
+/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT     0x00000000
+
+/***************************************************************************
+ *SERS_CFG - SERS Configuration Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT                0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT           0x00000000
+
+/* union - case mapped_buffer_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0x00000000
+
+/* union - case cmd_fifo_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 0x0000001f
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 0x00000010
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT                 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x00404428
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0
+
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x00404448
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0
+
+
+/***************************************************************************
+ *RO_TEST_BLOCK_SEL - Block select for RO testmode
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xffffffe0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        5
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_pwenb [04:04] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DEFAULT  0x00000001
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_ENABLED  0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DISABLED 1
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [03:02] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MIN_LOAD 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MED_LOAD 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MAX_LOAD 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SVT_MIN_LOAD 3
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
+
+/***************************************************************************
+ *TEST_CONFIGURATION - Test configuration
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_timer.h b/include/linux/brcmstb/7362a0/bchp_timer.h
new file mode 100644
index 0000000..65a3318
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_timer.h
@@ -0,0 +1,327 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_timer.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:32p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_TIMER_H__
+#define BCHP_TIMER_H__
+
+/***************************************************************************
+ *TIMER - Watchdog & Programmable Timers
+ ***************************************************************************/
+#define BCHP_TIMER_TIMER_IS                      0x00406680 /* TIMER INTERRUPT STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE0                     0x00406684 /* TIMER CPU INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_TIMER0_CTRL                   0x00406688 /* TIMER0 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER1_CTRL                   0x0040668c /* TIMER1 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER2_CTRL                   0x00406690 /* TIMER2 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER3_CTRL                   0x00406694 /* TIMER3 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER0_STAT                   0x00406698 /* TIMER0 STATUS REGISTER */
+#define BCHP_TIMER_TIMER1_STAT                   0x0040669c /* TIMER1 STATUS REGISTER */
+#define BCHP_TIMER_TIMER2_STAT                   0x004066a0 /* TIMER2 STATUS REGISTER */
+#define BCHP_TIMER_TIMER3_STAT                   0x004066a4 /* TIMER3 STATUS REGISTER */
+#define BCHP_TIMER_WDTIMEOUT                     0x004066a8 /* WATCHDOG TIMEOUT REGISTER */
+#define BCHP_TIMER_WDCMD                         0x004066ac /* WATCHDOG COMMAND REGISTER */
+#define BCHP_TIMER_WDCHIPRST_CNT                 0x004066b0 /* WATCHDOG CHIP RESET COUNT REGISTER */
+#define BCHP_TIMER_TIMER_IE1                     0x004066b8 /* TIMER PCI INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_WDCTRL                        0x004066bc /* WATCHDOG CONTROL REGISTER */
+
+/***************************************************************************
+ *TIMER_IS - TIMER INTERRUPT STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IS :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IS_reserved0_MASK                         0xffffffe0
+#define BCHP_TIMER_TIMER_IS_reserved0_SHIFT                        5
+
+/* TIMER :: TIMER_IS :: WDINT [04:04] */
+#define BCHP_TIMER_TIMER_IS_WDINT_MASK                             0x00000010
+#define BCHP_TIMER_TIMER_IS_WDINT_SHIFT                            4
+#define BCHP_TIMER_TIMER_IS_WDINT_DEFAULT                          0x00000000
+
+/* TIMER :: TIMER_IS :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IS_TMR3TO_MASK                            0x00000008
+#define BCHP_TIMER_TIMER_IS_TMR3TO_SHIFT                           3
+#define BCHP_TIMER_TIMER_IS_TMR3TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IS_TMR2TO_MASK                            0x00000004
+#define BCHP_TIMER_TIMER_IS_TMR2TO_SHIFT                           2
+#define BCHP_TIMER_TIMER_IS_TMR2TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IS_TMR1TO_MASK                            0x00000002
+#define BCHP_TIMER_TIMER_IS_TMR1TO_SHIFT                           1
+#define BCHP_TIMER_TIMER_IS_TMR1TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IS_TMR0TO_MASK                            0x00000001
+#define BCHP_TIMER_TIMER_IS_TMR0TO_SHIFT                           0
+#define BCHP_TIMER_TIMER_IS_TMR0TO_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *TIMER_IE0 - TIMER CPU INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE0 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE0_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE0_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE0 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_DEFAULT                     0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *TIMER0_CTRL - TIMER0 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER0_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER0_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER0_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER0_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER0_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER0_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER0_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER0_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER1_CTRL - TIMER1 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER1_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER1_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER1_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER1_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER1_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER1_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER1_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER1_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER2_CTRL - TIMER2 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER2_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER2_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER2_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER2_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER2_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER2_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER2_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER2_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER3_CTRL - TIMER3 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER3_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER3_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER3_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER3_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER3_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER3_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER3_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER3_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER0_STAT - TIMER0 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER0_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER0_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER0_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER1_STAT - TIMER1 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER1_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER1_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER1_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER2_STAT - TIMER2 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER2_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER2_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER2_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER3_STAT - TIMER3 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER3_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER3_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER3_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *WDTIMEOUT - WATCHDOG TIMEOUT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDTIMEOUT :: WDTIMEOUT_VAL [31:00] */
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_MASK                    0xffffffff
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *WDCMD - WATCHDOG COMMAND REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCMD :: WDCMD [31:00] */
+#define BCHP_TIMER_WDCMD_WDCMD_MASK                                0xffffffff
+#define BCHP_TIMER_WDCMD_WDCMD_SHIFT                               0
+#define BCHP_TIMER_WDCMD_WDCMD_DEFAULT                             0x00000000
+
+/***************************************************************************
+ *WDCHIPRST_CNT - WATCHDOG CHIP RESET COUNT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCHIPRST_CNT :: reserved0 [31:26] */
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_MASK                    0xfc000000
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_SHIFT                   26
+
+/* TIMER :: WDCHIPRST_CNT :: WDCHIPRST_CNT [25:00] */
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_MASK                0x03ffffff
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_SHIFT               0
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_DEFAULT             0x02ffffff
+
+/***************************************************************************
+ *TIMER_IE1 - TIMER PCI INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE1 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE1_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE1_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE1 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_DEFAULT                     0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *WDCTRL - WATCHDOG CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCTRL :: reserved0 [31:03] */
+#define BCHP_TIMER_WDCTRL_reserved0_MASK                           0xfffffff8
+#define BCHP_TIMER_WDCTRL_reserved0_SHIFT                          3
+
+/* TIMER :: WDCTRL :: WD_COUNT_MODE [02:02] */
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_MASK                       0x00000004
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_SHIFT                      2
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_DEFAULT                    0x00000000
+
+/* TIMER :: WDCTRL :: WD_EVENT_MODE [01:00] */
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_MASK                       0x00000003
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_SHIFT                      0
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_DEFAULT                    0x00000000
+
+#endif /* #ifndef BCHP_TIMER_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_uarta.h b/include/linux/brcmstb/7362a0/bchp_uarta.h
new file mode 100644
index 0000000..3c5e61a
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_uarta.h
@@ -0,0 +1,394 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_uarta.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:33p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTA_H__
+#define BCHP_UARTA_H__
+
+/***************************************************************************
+ *UARTA - UART A
+ ***************************************************************************/
+#define BCHP_UARTA_RBR                           0x00406800 /* Receive Buffer Register */
+#define BCHP_UARTA_THR                           0x00406800 /* Transmit Holding Register */
+#define BCHP_UARTA_DLH                           0x00406804 /* Divisor Latch High */
+#define BCHP_UARTA_DLL                           0x00406800 /* Divisor Latch Low */
+#define BCHP_UARTA_IER                           0x00406804 /* Interrupt Enable Register */
+#define BCHP_UARTA_IIR                           0x00406808 /* Interrupt Identity Register */
+#define BCHP_UARTA_FCR                           0x00406808 /* FIFO Control Register */
+#define BCHP_UARTA_LCR                           0x0040680c /* Line Control Register */
+#define BCHP_UARTA_MCR                           0x00406810 /* Modem Control Register */
+#define BCHP_UARTA_LSR                           0x00406814 /* Line Status Register */
+#define BCHP_UARTA_MSR                           0x00406818 /* Modem Status Register */
+#define BCHP_UARTA_SCR                           0x0040681c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTA :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTA_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_RBR_reserved0_SHIFT                             8
+
+/* UARTA :: RBR :: RBR [07:00] */
+#define BCHP_UARTA_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTA_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTA_RBR_RBR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTA :: THR :: reserved0 [31:08] */
+#define BCHP_UARTA_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_THR_reserved0_SHIFT                             8
+
+/* UARTA :: THR :: THR [07:00] */
+#define BCHP_UARTA_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTA_THR_THR_SHIFT                                   0
+#define BCHP_UARTA_THR_THR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTA :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTA_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLH_reserved0_SHIFT                             8
+
+/* UARTA :: DLH :: DLH [07:00] */
+#define BCHP_UARTA_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTA_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTA_DLH_DLH_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTA :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTA_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLL_reserved0_SHIFT                             8
+
+/* UARTA :: DLL :: DLL [07:00] */
+#define BCHP_UARTA_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTA_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTA_DLL_DLL_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTA :: IER :: reserved0 [31:08] */
+#define BCHP_UARTA_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IER_reserved0_SHIFT                             8
+
+/* UARTA :: IER :: PTIME [07:07] */
+#define BCHP_UARTA_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTA_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTA_IER_PTIME_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: reserved1 [06:04] */
+#define BCHP_UARTA_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTA_IER_reserved1_SHIFT                             4
+
+/* UARTA :: IER :: EDSSI [03:03] */
+#define BCHP_UARTA_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTA_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTA_IER_EDSSI_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: ELSI [02:02] */
+#define BCHP_UARTA_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTA_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTA_IER_ELSI_DEFAULT                                0x00000000
+
+/* UARTA :: IER :: ETBEI [01:01] */
+#define BCHP_UARTA_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTA_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTA_IER_ETBEI_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: ERBFI [00:00] */
+#define BCHP_UARTA_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTA_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTA_IER_ERBFI_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTA :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTA_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IIR_reserved0_SHIFT                             8
+
+/* UARTA :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTA_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTA_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTA_IIR_FIFOSE_DEFAULT                              0x00000000
+
+/* UARTA :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTA_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTA_IIR_reserved1_SHIFT                             4
+
+/* UARTA :: IIR :: IID [03:00] */
+#define BCHP_UARTA_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTA_IIR_IID_SHIFT                                   0
+#define BCHP_UARTA_IIR_IID_DEFAULT                                 0x00000001
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTA :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTA_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_FCR_reserved0_SHIFT                             8
+
+/* UARTA :: FCR :: RT [07:06] */
+#define BCHP_UARTA_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTA_FCR_RT_SHIFT                                    6
+#define BCHP_UARTA_FCR_RT_DEFAULT                                  0x00000000
+
+/* UARTA :: FCR :: TET [05:04] */
+#define BCHP_UARTA_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTA_FCR_TET_SHIFT                                   4
+#define BCHP_UARTA_FCR_TET_DEFAULT                                 0x00000000
+
+/* UARTA :: FCR :: DMAM [03:03] */
+#define BCHP_UARTA_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTA_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTA_FCR_DMAM_DEFAULT                                0x00000000
+
+/* UARTA :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTA_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTA_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTA_FCR_XFIFOR_DEFAULT                              0x00000000
+
+/* UARTA :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTA_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTA_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTA_FCR_RFIFOR_DEFAULT                              0x00000000
+
+/* UARTA :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTA_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTA_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTA_FCR_FIFOE_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTA :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTA_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LCR_reserved0_SHIFT                             8
+
+/* UARTA :: LCR :: DLAB [07:07] */
+#define BCHP_UARTA_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTA_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTA_LCR_DLAB_DEFAULT                                0x00000000
+
+/* UARTA :: LCR :: BC [06:06] */
+#define BCHP_UARTA_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTA_LCR_BC_SHIFT                                    6
+#define BCHP_UARTA_LCR_BC_DEFAULT                                  0x00000000
+
+/* UARTA :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTA_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTA_LCR_reserved1_SHIFT                             5
+
+/* UARTA :: LCR :: EPS [04:04] */
+#define BCHP_UARTA_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTA_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTA_LCR_EPS_DEFAULT                                 0x00000000
+
+/* UARTA :: LCR :: PEN [03:03] */
+#define BCHP_UARTA_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTA_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTA_LCR_PEN_DEFAULT                                 0x00000000
+
+/* UARTA :: LCR :: STOP [02:02] */
+#define BCHP_UARTA_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTA_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTA_LCR_STOP_DEFAULT                                0x00000000
+
+/* UARTA :: LCR :: DLS [01:00] */
+#define BCHP_UARTA_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTA_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTA_LCR_DLS_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTA :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTA_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTA_MCR_reserved0_SHIFT                             7
+
+/* UARTA :: MCR :: SIRE [06:06] */
+#define BCHP_UARTA_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTA_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTA_MCR_SIRE_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: AFCE [05:05] */
+#define BCHP_UARTA_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTA_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTA_MCR_AFCE_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: LB [04:04] */
+#define BCHP_UARTA_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTA_MCR_LB_SHIFT                                    4
+#define BCHP_UARTA_MCR_LB_DEFAULT                                  0x00000000
+
+/* UARTA :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTA_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTA_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTA_MCR_OUT2_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTA_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTA_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTA_MCR_OUT1_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: RTS [01:01] */
+#define BCHP_UARTA_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTA_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTA_MCR_RTS_DEFAULT                                 0x00000000
+
+/* UARTA :: MCR :: DTR [00:00] */
+#define BCHP_UARTA_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTA_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTA_MCR_DTR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTA :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTA_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LSR_reserved0_SHIFT                             8
+
+/* UARTA :: LSR :: RFE [07:07] */
+#define BCHP_UARTA_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTA_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTA_LSR_RFE_DEFAULT                                 0x00000000
+
+/* UARTA :: LSR :: TEMT [06:06] */
+#define BCHP_UARTA_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTA_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTA_LSR_TEMT_DEFAULT                                0x00000001
+
+/* UARTA :: LSR :: THRE [05:05] */
+#define BCHP_UARTA_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTA_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTA_LSR_THRE_DEFAULT                                0x00000001
+
+/* UARTA :: LSR :: BI [04:04] */
+#define BCHP_UARTA_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTA_LSR_BI_SHIFT                                    4
+#define BCHP_UARTA_LSR_BI_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: FE [03:03] */
+#define BCHP_UARTA_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTA_LSR_FE_SHIFT                                    3
+#define BCHP_UARTA_LSR_FE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: PE [02:02] */
+#define BCHP_UARTA_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTA_LSR_PE_SHIFT                                    2
+#define BCHP_UARTA_LSR_PE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: OE [01:01] */
+#define BCHP_UARTA_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTA_LSR_OE_SHIFT                                    1
+#define BCHP_UARTA_LSR_OE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: DR [00:00] */
+#define BCHP_UARTA_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTA_LSR_DR_SHIFT                                    0
+#define BCHP_UARTA_LSR_DR_DEFAULT                                  0x00000000
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTA :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTA_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_MSR_reserved0_SHIFT                             8
+
+/* UARTA :: MSR :: DCD [07:07] */
+#define BCHP_UARTA_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTA_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTA_MSR_DCD_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: RI [06:06] */
+#define BCHP_UARTA_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTA_MSR_RI_SHIFT                                    6
+#define BCHP_UARTA_MSR_RI_DEFAULT                                  0x00000000
+
+/* UARTA :: MSR :: DSR [05:05] */
+#define BCHP_UARTA_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTA_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTA_MSR_DSR_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: CTS [04:04] */
+#define BCHP_UARTA_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTA_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTA_MSR_CTS_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: DDCD [03:03] */
+#define BCHP_UARTA_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTA_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTA_MSR_DDCD_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: TERI [02:02] */
+#define BCHP_UARTA_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTA_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTA_MSR_TERI_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: DDSR [01:01] */
+#define BCHP_UARTA_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTA_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTA_MSR_DDSR_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: DCTS [00:00] */
+#define BCHP_UARTA_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTA_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTA_MSR_DCTS_DEFAULT                                0x00000000
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTA :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTA_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_SCR_reserved0_SHIFT                             8
+
+/* UARTA :: SCR :: SCR [07:00] */
+#define BCHP_UARTA_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTA_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTA_SCR_SCR_DEFAULT                                 0x00000000
+
+#endif /* #ifndef BCHP_UARTA_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_uartb.h b/include/linux/brcmstb/7362a0/bchp_uartb.h
new file mode 100644
index 0000000..8eede69
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_uartb.h
@@ -0,0 +1,391 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 24 17:25:43 2013
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTB_H__
+#define BCHP_UARTB_H__
+
+/***************************************************************************
+ *UARTB - UART B
+ ***************************************************************************/
+#define BCHP_UARTB_RBR                           0x00406840 /* Receive Buffer Register */
+#define BCHP_UARTB_THR                           0x00406840 /* Transmit Holding Register */
+#define BCHP_UARTB_DLH                           0x00406844 /* Divisor Latch High */
+#define BCHP_UARTB_DLL                           0x00406840 /* Divisor Latch Low */
+#define BCHP_UARTB_IER                           0x00406844 /* Interrupt Enable Register */
+#define BCHP_UARTB_IIR                           0x00406848 /* Interrupt Identity Register */
+#define BCHP_UARTB_FCR                           0x00406848 /* FIFO Control Register */
+#define BCHP_UARTB_LCR                           0x0040684c /* Line Control Register */
+#define BCHP_UARTB_MCR                           0x00406850 /* Modem Control Register */
+#define BCHP_UARTB_LSR                           0x00406854 /* Line Status Register */
+#define BCHP_UARTB_MSR                           0x00406858 /* Modem Status Register */
+#define BCHP_UARTB_SCR                           0x0040685c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTB :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTB_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_RBR_reserved0_SHIFT                             8
+
+/* UARTB :: RBR :: RBR [07:00] */
+#define BCHP_UARTB_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTB_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTB_RBR_RBR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTB :: THR :: reserved0 [31:08] */
+#define BCHP_UARTB_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_THR_reserved0_SHIFT                             8
+
+/* UARTB :: THR :: THR [07:00] */
+#define BCHP_UARTB_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTB_THR_THR_SHIFT                                   0
+#define BCHP_UARTB_THR_THR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTB :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTB_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_DLH_reserved0_SHIFT                             8
+
+/* UARTB :: DLH :: DLH [07:00] */
+#define BCHP_UARTB_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTB_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTB_DLH_DLH_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTB :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTB_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_DLL_reserved0_SHIFT                             8
+
+/* UARTB :: DLL :: DLL [07:00] */
+#define BCHP_UARTB_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTB_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTB_DLL_DLL_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTB :: IER :: reserved0 [31:08] */
+#define BCHP_UARTB_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_IER_reserved0_SHIFT                             8
+
+/* UARTB :: IER :: PTIME [07:07] */
+#define BCHP_UARTB_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTB_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTB_IER_PTIME_DEFAULT                               0x00000000
+
+/* UARTB :: IER :: reserved1 [06:04] */
+#define BCHP_UARTB_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTB_IER_reserved1_SHIFT                             4
+
+/* UARTB :: IER :: EDSSI [03:03] */
+#define BCHP_UARTB_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTB_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTB_IER_EDSSI_DEFAULT                               0x00000000
+
+/* UARTB :: IER :: ELSI [02:02] */
+#define BCHP_UARTB_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTB_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTB_IER_ELSI_DEFAULT                                0x00000000
+
+/* UARTB :: IER :: ETBEI [01:01] */
+#define BCHP_UARTB_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTB_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTB_IER_ETBEI_DEFAULT                               0x00000000
+
+/* UARTB :: IER :: ERBFI [00:00] */
+#define BCHP_UARTB_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTB_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTB_IER_ERBFI_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTB :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTB_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_IIR_reserved0_SHIFT                             8
+
+/* UARTB :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTB_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTB_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTB_IIR_FIFOSE_DEFAULT                              0x00000000
+
+/* UARTB :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTB_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTB_IIR_reserved1_SHIFT                             4
+
+/* UARTB :: IIR :: IID [03:00] */
+#define BCHP_UARTB_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTB_IIR_IID_SHIFT                                   0
+#define BCHP_UARTB_IIR_IID_DEFAULT                                 0x00000001
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTB :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTB_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_FCR_reserved0_SHIFT                             8
+
+/* UARTB :: FCR :: RT [07:06] */
+#define BCHP_UARTB_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTB_FCR_RT_SHIFT                                    6
+#define BCHP_UARTB_FCR_RT_DEFAULT                                  0x00000000
+
+/* UARTB :: FCR :: TET [05:04] */
+#define BCHP_UARTB_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTB_FCR_TET_SHIFT                                   4
+#define BCHP_UARTB_FCR_TET_DEFAULT                                 0x00000000
+
+/* UARTB :: FCR :: DMAM [03:03] */
+#define BCHP_UARTB_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTB_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTB_FCR_DMAM_DEFAULT                                0x00000000
+
+/* UARTB :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTB_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTB_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTB_FCR_XFIFOR_DEFAULT                              0x00000000
+
+/* UARTB :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTB_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTB_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTB_FCR_RFIFOR_DEFAULT                              0x00000000
+
+/* UARTB :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTB_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTB_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTB_FCR_FIFOE_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTB :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTB_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_LCR_reserved0_SHIFT                             8
+
+/* UARTB :: LCR :: DLAB [07:07] */
+#define BCHP_UARTB_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTB_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTB_LCR_DLAB_DEFAULT                                0x00000000
+
+/* UARTB :: LCR :: BC [06:06] */
+#define BCHP_UARTB_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTB_LCR_BC_SHIFT                                    6
+#define BCHP_UARTB_LCR_BC_DEFAULT                                  0x00000000
+
+/* UARTB :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTB_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTB_LCR_reserved1_SHIFT                             5
+
+/* UARTB :: LCR :: EPS [04:04] */
+#define BCHP_UARTB_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTB_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTB_LCR_EPS_DEFAULT                                 0x00000000
+
+/* UARTB :: LCR :: PEN [03:03] */
+#define BCHP_UARTB_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTB_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTB_LCR_PEN_DEFAULT                                 0x00000000
+
+/* UARTB :: LCR :: STOP [02:02] */
+#define BCHP_UARTB_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTB_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTB_LCR_STOP_DEFAULT                                0x00000000
+
+/* UARTB :: LCR :: DLS [01:00] */
+#define BCHP_UARTB_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTB_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTB_LCR_DLS_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTB :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTB_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTB_MCR_reserved0_SHIFT                             7
+
+/* UARTB :: MCR :: SIRE [06:06] */
+#define BCHP_UARTB_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTB_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTB_MCR_SIRE_DEFAULT                                0x00000000
+
+/* UARTB :: MCR :: AFCE [05:05] */
+#define BCHP_UARTB_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTB_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTB_MCR_AFCE_DEFAULT                                0x00000000
+
+/* UARTB :: MCR :: LB [04:04] */
+#define BCHP_UARTB_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTB_MCR_LB_SHIFT                                    4
+#define BCHP_UARTB_MCR_LB_DEFAULT                                  0x00000000
+
+/* UARTB :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTB_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTB_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTB_MCR_OUT2_DEFAULT                                0x00000000
+
+/* UARTB :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTB_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTB_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTB_MCR_OUT1_DEFAULT                                0x00000000
+
+/* UARTB :: MCR :: RTS [01:01] */
+#define BCHP_UARTB_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTB_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTB_MCR_RTS_DEFAULT                                 0x00000000
+
+/* UARTB :: MCR :: DTR [00:00] */
+#define BCHP_UARTB_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTB_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTB_MCR_DTR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTB :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTB_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_LSR_reserved0_SHIFT                             8
+
+/* UARTB :: LSR :: RFE [07:07] */
+#define BCHP_UARTB_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTB_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTB_LSR_RFE_DEFAULT                                 0x00000000
+
+/* UARTB :: LSR :: TEMT [06:06] */
+#define BCHP_UARTB_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTB_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTB_LSR_TEMT_DEFAULT                                0x00000001
+
+/* UARTB :: LSR :: THRE [05:05] */
+#define BCHP_UARTB_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTB_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTB_LSR_THRE_DEFAULT                                0x00000001
+
+/* UARTB :: LSR :: BI [04:04] */
+#define BCHP_UARTB_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTB_LSR_BI_SHIFT                                    4
+#define BCHP_UARTB_LSR_BI_DEFAULT                                  0x00000000
+
+/* UARTB :: LSR :: FE [03:03] */
+#define BCHP_UARTB_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTB_LSR_FE_SHIFT                                    3
+#define BCHP_UARTB_LSR_FE_DEFAULT                                  0x00000000
+
+/* UARTB :: LSR :: PE [02:02] */
+#define BCHP_UARTB_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTB_LSR_PE_SHIFT                                    2
+#define BCHP_UARTB_LSR_PE_DEFAULT                                  0x00000000
+
+/* UARTB :: LSR :: OE [01:01] */
+#define BCHP_UARTB_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTB_LSR_OE_SHIFT                                    1
+#define BCHP_UARTB_LSR_OE_DEFAULT                                  0x00000000
+
+/* UARTB :: LSR :: DR [00:00] */
+#define BCHP_UARTB_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTB_LSR_DR_SHIFT                                    0
+#define BCHP_UARTB_LSR_DR_DEFAULT                                  0x00000000
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTB :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTB_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_MSR_reserved0_SHIFT                             8
+
+/* UARTB :: MSR :: DCD [07:07] */
+#define BCHP_UARTB_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTB_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTB_MSR_DCD_DEFAULT                                 0x00000000
+
+/* UARTB :: MSR :: RI [06:06] */
+#define BCHP_UARTB_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTB_MSR_RI_SHIFT                                    6
+#define BCHP_UARTB_MSR_RI_DEFAULT                                  0x00000000
+
+/* UARTB :: MSR :: DSR [05:05] */
+#define BCHP_UARTB_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTB_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTB_MSR_DSR_DEFAULT                                 0x00000000
+
+/* UARTB :: MSR :: CTS [04:04] */
+#define BCHP_UARTB_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTB_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTB_MSR_CTS_DEFAULT                                 0x00000000
+
+/* UARTB :: MSR :: DDCD [03:03] */
+#define BCHP_UARTB_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTB_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTB_MSR_DDCD_DEFAULT                                0x00000000
+
+/* UARTB :: MSR :: TERI [02:02] */
+#define BCHP_UARTB_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTB_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTB_MSR_TERI_DEFAULT                                0x00000000
+
+/* UARTB :: MSR :: DDSR [01:01] */
+#define BCHP_UARTB_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTB_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTB_MSR_DDSR_DEFAULT                                0x00000000
+
+/* UARTB :: MSR :: DCTS [00:00] */
+#define BCHP_UARTB_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTB_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTB_MSR_DCTS_DEFAULT                                0x00000000
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTB :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTB_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_SCR_reserved0_SHIFT                             8
+
+/* UARTB :: SCR :: SCR [07:00] */
+#define BCHP_UARTB_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTB_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTB_SCR_SCR_DEFAULT                                 0x00000000
+
+#endif /* #ifndef BCHP_UARTB_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_uartc.h b/include/linux/brcmstb/7362a0/bchp_uartc.h
new file mode 100644
index 0000000..c1f7dad
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_uartc.h
@@ -0,0 +1,391 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 24 17:25:42 2013
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTC_H__
+#define BCHP_UARTC_H__
+
+/***************************************************************************
+ *UARTC - UART C
+ ***************************************************************************/
+#define BCHP_UARTC_RBR                           0x00406880 /* Receive Buffer Register */
+#define BCHP_UARTC_THR                           0x00406880 /* Transmit Holding Register */
+#define BCHP_UARTC_DLH                           0x00406884 /* Divisor Latch High */
+#define BCHP_UARTC_DLL                           0x00406880 /* Divisor Latch Low */
+#define BCHP_UARTC_IER                           0x00406884 /* Interrupt Enable Register */
+#define BCHP_UARTC_IIR                           0x00406888 /* Interrupt Identity Register */
+#define BCHP_UARTC_FCR                           0x00406888 /* FIFO Control Register */
+#define BCHP_UARTC_LCR                           0x0040688c /* Line Control Register */
+#define BCHP_UARTC_MCR                           0x00406890 /* Modem Control Register */
+#define BCHP_UARTC_LSR                           0x00406894 /* Line Status Register */
+#define BCHP_UARTC_MSR                           0x00406898 /* Modem Status Register */
+#define BCHP_UARTC_SCR                           0x0040689c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTC :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTC_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_RBR_reserved0_SHIFT                             8
+
+/* UARTC :: RBR :: RBR [07:00] */
+#define BCHP_UARTC_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTC_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTC_RBR_RBR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTC :: THR :: reserved0 [31:08] */
+#define BCHP_UARTC_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_THR_reserved0_SHIFT                             8
+
+/* UARTC :: THR :: THR [07:00] */
+#define BCHP_UARTC_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTC_THR_THR_SHIFT                                   0
+#define BCHP_UARTC_THR_THR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTC :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTC_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_DLH_reserved0_SHIFT                             8
+
+/* UARTC :: DLH :: DLH [07:00] */
+#define BCHP_UARTC_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTC_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTC_DLH_DLH_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTC :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTC_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_DLL_reserved0_SHIFT                             8
+
+/* UARTC :: DLL :: DLL [07:00] */
+#define BCHP_UARTC_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTC_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTC_DLL_DLL_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTC :: IER :: reserved0 [31:08] */
+#define BCHP_UARTC_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_IER_reserved0_SHIFT                             8
+
+/* UARTC :: IER :: PTIME [07:07] */
+#define BCHP_UARTC_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTC_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTC_IER_PTIME_DEFAULT                               0x00000000
+
+/* UARTC :: IER :: reserved1 [06:04] */
+#define BCHP_UARTC_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTC_IER_reserved1_SHIFT                             4
+
+/* UARTC :: IER :: EDSSI [03:03] */
+#define BCHP_UARTC_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTC_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTC_IER_EDSSI_DEFAULT                               0x00000000
+
+/* UARTC :: IER :: ELSI [02:02] */
+#define BCHP_UARTC_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTC_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTC_IER_ELSI_DEFAULT                                0x00000000
+
+/* UARTC :: IER :: ETBEI [01:01] */
+#define BCHP_UARTC_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTC_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTC_IER_ETBEI_DEFAULT                               0x00000000
+
+/* UARTC :: IER :: ERBFI [00:00] */
+#define BCHP_UARTC_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTC_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTC_IER_ERBFI_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTC :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTC_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_IIR_reserved0_SHIFT                             8
+
+/* UARTC :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTC_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTC_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTC_IIR_FIFOSE_DEFAULT                              0x00000000
+
+/* UARTC :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTC_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTC_IIR_reserved1_SHIFT                             4
+
+/* UARTC :: IIR :: IID [03:00] */
+#define BCHP_UARTC_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTC_IIR_IID_SHIFT                                   0
+#define BCHP_UARTC_IIR_IID_DEFAULT                                 0x00000001
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTC :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTC_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_FCR_reserved0_SHIFT                             8
+
+/* UARTC :: FCR :: RT [07:06] */
+#define BCHP_UARTC_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTC_FCR_RT_SHIFT                                    6
+#define BCHP_UARTC_FCR_RT_DEFAULT                                  0x00000000
+
+/* UARTC :: FCR :: TET [05:04] */
+#define BCHP_UARTC_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTC_FCR_TET_SHIFT                                   4
+#define BCHP_UARTC_FCR_TET_DEFAULT                                 0x00000000
+
+/* UARTC :: FCR :: DMAM [03:03] */
+#define BCHP_UARTC_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTC_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTC_FCR_DMAM_DEFAULT                                0x00000000
+
+/* UARTC :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTC_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTC_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTC_FCR_XFIFOR_DEFAULT                              0x00000000
+
+/* UARTC :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTC_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTC_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTC_FCR_RFIFOR_DEFAULT                              0x00000000
+
+/* UARTC :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTC_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTC_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTC_FCR_FIFOE_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTC :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTC_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_LCR_reserved0_SHIFT                             8
+
+/* UARTC :: LCR :: DLAB [07:07] */
+#define BCHP_UARTC_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTC_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTC_LCR_DLAB_DEFAULT                                0x00000000
+
+/* UARTC :: LCR :: BC [06:06] */
+#define BCHP_UARTC_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTC_LCR_BC_SHIFT                                    6
+#define BCHP_UARTC_LCR_BC_DEFAULT                                  0x00000000
+
+/* UARTC :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTC_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTC_LCR_reserved1_SHIFT                             5
+
+/* UARTC :: LCR :: EPS [04:04] */
+#define BCHP_UARTC_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTC_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTC_LCR_EPS_DEFAULT                                 0x00000000
+
+/* UARTC :: LCR :: PEN [03:03] */
+#define BCHP_UARTC_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTC_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTC_LCR_PEN_DEFAULT                                 0x00000000
+
+/* UARTC :: LCR :: STOP [02:02] */
+#define BCHP_UARTC_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTC_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTC_LCR_STOP_DEFAULT                                0x00000000
+
+/* UARTC :: LCR :: DLS [01:00] */
+#define BCHP_UARTC_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTC_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTC_LCR_DLS_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTC :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTC_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTC_MCR_reserved0_SHIFT                             7
+
+/* UARTC :: MCR :: SIRE [06:06] */
+#define BCHP_UARTC_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTC_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTC_MCR_SIRE_DEFAULT                                0x00000000
+
+/* UARTC :: MCR :: AFCE [05:05] */
+#define BCHP_UARTC_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTC_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTC_MCR_AFCE_DEFAULT                                0x00000000
+
+/* UARTC :: MCR :: LB [04:04] */
+#define BCHP_UARTC_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTC_MCR_LB_SHIFT                                    4
+#define BCHP_UARTC_MCR_LB_DEFAULT                                  0x00000000
+
+/* UARTC :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTC_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTC_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTC_MCR_OUT2_DEFAULT                                0x00000000
+
+/* UARTC :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTC_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTC_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTC_MCR_OUT1_DEFAULT                                0x00000000
+
+/* UARTC :: MCR :: RTS [01:01] */
+#define BCHP_UARTC_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTC_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTC_MCR_RTS_DEFAULT                                 0x00000000
+
+/* UARTC :: MCR :: DTR [00:00] */
+#define BCHP_UARTC_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTC_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTC_MCR_DTR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTC :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTC_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_LSR_reserved0_SHIFT                             8
+
+/* UARTC :: LSR :: RFE [07:07] */
+#define BCHP_UARTC_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTC_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTC_LSR_RFE_DEFAULT                                 0x00000000
+
+/* UARTC :: LSR :: TEMT [06:06] */
+#define BCHP_UARTC_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTC_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTC_LSR_TEMT_DEFAULT                                0x00000001
+
+/* UARTC :: LSR :: THRE [05:05] */
+#define BCHP_UARTC_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTC_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTC_LSR_THRE_DEFAULT                                0x00000001
+
+/* UARTC :: LSR :: BI [04:04] */
+#define BCHP_UARTC_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTC_LSR_BI_SHIFT                                    4
+#define BCHP_UARTC_LSR_BI_DEFAULT                                  0x00000000
+
+/* UARTC :: LSR :: FE [03:03] */
+#define BCHP_UARTC_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTC_LSR_FE_SHIFT                                    3
+#define BCHP_UARTC_LSR_FE_DEFAULT                                  0x00000000
+
+/* UARTC :: LSR :: PE [02:02] */
+#define BCHP_UARTC_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTC_LSR_PE_SHIFT                                    2
+#define BCHP_UARTC_LSR_PE_DEFAULT                                  0x00000000
+
+/* UARTC :: LSR :: OE [01:01] */
+#define BCHP_UARTC_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTC_LSR_OE_SHIFT                                    1
+#define BCHP_UARTC_LSR_OE_DEFAULT                                  0x00000000
+
+/* UARTC :: LSR :: DR [00:00] */
+#define BCHP_UARTC_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTC_LSR_DR_SHIFT                                    0
+#define BCHP_UARTC_LSR_DR_DEFAULT                                  0x00000000
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTC :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTC_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_MSR_reserved0_SHIFT                             8
+
+/* UARTC :: MSR :: DCD [07:07] */
+#define BCHP_UARTC_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTC_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTC_MSR_DCD_DEFAULT                                 0x00000000
+
+/* UARTC :: MSR :: RI [06:06] */
+#define BCHP_UARTC_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTC_MSR_RI_SHIFT                                    6
+#define BCHP_UARTC_MSR_RI_DEFAULT                                  0x00000000
+
+/* UARTC :: MSR :: DSR [05:05] */
+#define BCHP_UARTC_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTC_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTC_MSR_DSR_DEFAULT                                 0x00000000
+
+/* UARTC :: MSR :: CTS [04:04] */
+#define BCHP_UARTC_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTC_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTC_MSR_CTS_DEFAULT                                 0x00000000
+
+/* UARTC :: MSR :: DDCD [03:03] */
+#define BCHP_UARTC_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTC_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTC_MSR_DDCD_DEFAULT                                0x00000000
+
+/* UARTC :: MSR :: TERI [02:02] */
+#define BCHP_UARTC_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTC_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTC_MSR_TERI_DEFAULT                                0x00000000
+
+/* UARTC :: MSR :: DDSR [01:01] */
+#define BCHP_UARTC_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTC_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTC_MSR_DDSR_DEFAULT                                0x00000000
+
+/* UARTC :: MSR :: DCTS [00:00] */
+#define BCHP_UARTC_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTC_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTC_MSR_DCTS_DEFAULT                                0x00000000
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTC :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTC_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_SCR_reserved0_SHIFT                             8
+
+/* UARTC :: SCR :: SCR [07:00] */
+#define BCHP_UARTC_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTC_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTC_SCR_SCR_DEFAULT                                 0x00000000
+
+#endif /* #ifndef BCHP_UARTC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_usb_ctrl.h b/include/linux/brcmstb/7362a0/bchp_usb_ctrl.h
new file mode 100644
index 0000000..e116fa2
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_usb_ctrl.h
@@ -0,0 +1,655 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_usb_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:33p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB_CTRL_H__
+#define BCHP_USB_CTRL_H__
+
+/***************************************************************************
+ *USB_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB_CTRL_SETUP                      0x00480200 /* Setup Register */
+#define BCHP_USB_CTRL_PLL_CTL                    0x00480204 /* PLL Control Register */
+#define BCHP_USB_CTRL_FLADJ_VALUE                0x00480208 /* Frame Adjust Value */
+#define BCHP_USB_CTRL_EBRIDGE                    0x0048020c /* Control Register for EHCI Bridge */
+#define BCHP_USB_CTRL_OBRIDGE                    0x00480210 /* Control Register for OHCI Bridge */
+#define BCHP_USB_CTRL_MDIO                       0x00480214 /* MDIO Interface Programming Register */
+#define BCHP_USB_CTRL_MDIO2                      0x00480218 /* MDIO Interface Read Register */
+#define BCHP_USB_CTRL_TEST_PORT_CTL              0x0048021c /* Test Port Control Register */
+#define BCHP_USB_CTRL_USB_SIMCTL                 0x00480220 /* Simulation Register */
+#define BCHP_USB_CTRL_USB_TESTCTL                0x00480224 /* Throutput Test Control */
+#define BCHP_USB_CTRL_USB_TESTMON                0x00480228 /* Throughput Test Monitor */
+#define BCHP_USB_CTRL_UTMI_CTL_1                 0x0048022c /* UTMI Control Register */
+#define BCHP_USB_CTRL_UTMI_CTL_2                 0x00480230 /* UTMI Control 2 Register */
+#define BCHP_USB_CTRL_SPARE1                     0x00480234 /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE2                     0x00480238 /* Spare2 Register for future use */
+
+/***************************************************************************
+ *SETUP - Setup Register
+ ***************************************************************************/
+/* USB_CTRL :: SETUP :: OC_DISABLE [31:28] */
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK                        0xf0000000
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT                       28
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: SRAM_CS_DIS [27:26] */
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_MASK                       0x0c000000
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_SHIFT                      26
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: SETUP_SPARE [25:13] */
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK                       0x03ffe000
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT                      13
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: async_expire_dis [12:12] */
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK                  0x00001000
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT                 12
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT               0x00000000
+
+/* USB_CTRL :: SETUP :: discon_intr_en [11:11] */
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_MASK                    0x00000800
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_SHIFT                   11
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: con_intr_en [10:10] */
+#define BCHP_USB_CTRL_SETUP_con_intr_en_MASK                       0x00000400
+#define BCHP_USB_CTRL_SETUP_con_intr_en_SHIFT                      10
+#define BCHP_USB_CTRL_SETUP_con_intr_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: SOFT_SHUTDOWN [09:09] */
+#define BCHP_USB_CTRL_SETUP_SOFT_SHUTDOWN_MASK                     0x00000200
+#define BCHP_USB_CTRL_SETUP_SOFT_SHUTDOWN_SHIFT                    9
+#define BCHP_USB_CTRL_SETUP_SOFT_SHUTDOWN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK                    0x00000100
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT                   8
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK                       0x00000080
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT                      7
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: soft_reset [06:06] */
+#define BCHP_USB_CTRL_SETUP_soft_reset_MASK                        0x00000040
+#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT                       6
+#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: IPP [05:05] */
+#define BCHP_USB_CTRL_SETUP_IPP_MASK                               0x00000020
+#define BCHP_USB_CTRL_SETUP_IPP_SHIFT                              5
+#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: IOC [04:04] */
+#define BCHP_USB_CTRL_SETUP_IOC_MASK                               0x00000010
+#define BCHP_USB_CTRL_SETUP_IOC_SHIFT                              4
+#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: WABO [03:03] */
+#define BCHP_USB_CTRL_SETUP_WABO_MASK                              0x00000008
+#define BCHP_USB_CTRL_SETUP_WABO_SHIFT                             3
+#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNBO [02:02] */
+#define BCHP_USB_CTRL_SETUP_FNBO_MASK                              0x00000004
+#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT                             2
+#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNHW [01:01] */
+#define BCHP_USB_CTRL_SETUP_FNHW_MASK                              0x00000002
+#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT                             1
+#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: BABO [00:00] */
+#define BCHP_USB_CTRL_SETUP_BABO_MASK                              0x00000001
+#define BCHP_USB_CTRL_SETUP_BABO_SHIFT                             0
+#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *PLL_CTL - PLL Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK                  0x80000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT                 31
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT               0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK                      0x40000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT                     30
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                   0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK                      0x20000000
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                     29
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                   0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                     0x10000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                    28
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                  0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                  0x08000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                 27
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT               0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK                          0x07000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT                         24
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT                       0x00000003
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                   0x00800000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                  23
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK                          0x00700000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT                         20
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT                       0x00000003
+
+/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK                          0x000f0000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT                         16
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT                       0x0000000a
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE2 [15:15] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_MASK                   0x00008000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_SHIFT                  15
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_pdiv [14:12] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK                        0x00007000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT                       12
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                     0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                   0x00000c00
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                  10
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK                        0x000003ff
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT                       0
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                     0x00000028
+
+/***************************************************************************
+ *FLADJ_VALUE - Frame Adjust Value
+ ***************************************************************************/
+/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                   0xffffffff
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                  0
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT                0x000c0020
+
+/***************************************************************************
+ *EBRIDGE - Control Register for EHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_rdgwordcnt_sel [28:28] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_rdgwordcnt_sel_MASK              0x10000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_rdgwordcnt_sel_SHIFT             28
+#define BCHP_USB_CTRL_EBRIDGE_ebr_rdgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *OBRIDGE - Control Register for OHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_rdgwordcnt_sel [28:28] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_rdgwordcnt_sel_MASK              0x10000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_rdgwordcnt_sel_SHIFT             28
+#define BCHP_USB_CTRL_OBRIDGE_obr_rdgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *MDIO - MDIO Interface Programming Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO :: MDIO_SPARE [31:26] */
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_MASK                         0xfc000000
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_SHIFT                        26
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_DEFAULT                      0x00000000
+
+/* USB_CTRL :: MDIO :: WR_START [25:25] */
+#define BCHP_USB_CTRL_MDIO_WR_START_MASK                           0x02000000
+#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT                          25
+#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: RD_START [24:24] */
+#define BCHP_USB_CTRL_MDIO_RD_START_MASK                           0x01000000
+#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT                          24
+#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK                          0x00ff0000
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT                         16
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT                       0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK                          0x0000ffff
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT                         0
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *MDIO2 - MDIO Interface Read Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO2 :: SYNOPSIS_CORE_ID [31:16] */
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_MASK                  0xffff0000
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_SHIFT                 16
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_DEFAULT               0x0000270a
+
+/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK                      0x0000ffff
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                     0
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTL - Test Port Control Register
+ ***************************************************************************/
+/* USB_CTRL :: TEST_PORT_CTL :: TP_EN [31:31] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_MASK                     0x80000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_SHIFT                    31
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [30:24] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK               0x7f000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT              24
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [23:23] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK                0x00800000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT               23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt2_oe [22:22] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_MASK                0x00400000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_SHIFT               22
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron1_tstsel [21:21] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_MASK             0x00200000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_SHIFT            21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron2_tstsel [20:20] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_MASK             0x00100000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_SHIFT            20
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: test_clksel [19:18] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_MASK               0x000c0000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_SHIFT              18
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_tstsel [17:16] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_MASK             0x00030000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_SHIFT            16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: UTMI_TEST_SEL [15:08] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_MASK             0x0000ff00
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_SHIFT            8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                 0x000000ff
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT                0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *USB_SIMCTL - Simulation Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK                  0x80000000
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                 31
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK                0x40000000
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT               30
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE1 [29:28] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_MASK                0x30000000
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_SHIFT               28
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK                    0x08000000
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT                   27
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK        0x04000000
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT       26
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT     0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:01] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                 0x03fffffe
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT                1
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: FS_DLY_EN [00:00] */
+#define BCHP_USB_CTRL_USB_SIMCTL_FS_DLY_EN_MASK                    0x00000001
+#define BCHP_USB_CTRL_USB_SIMCTL_FS_DLY_EN_SHIFT                   0
+#define BCHP_USB_CTRL_USB_SIMCTL_FS_DLY_EN_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *USB_TESTCTL - Throutput Test Control
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:22] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK              0xffc00000
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT             22
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: CTRLLER_SEL [21:21] */
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_MASK                 0x00200000
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_SHIFT                21
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK                     0x00100000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                    20
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK                   0x00080000
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                  19
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT                0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK                    0x00070000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                   16
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK              0x0000fc00
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT             10
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK              0x000003ff
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT             0
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT           0x00000000
+
+/***************************************************************************
+ *USB_TESTMON - Throughput Test Monitor
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [31:00] */
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK                0xffffffff
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT               0
+
+/***************************************************************************
+ *UTMI_CTL_1 - UTMI Control Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE3 [31:31] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_MASK              0x80000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_SHIFT             31
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK             0x70000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT            28
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT          0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK_P1 [27:27] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_MASK                0x08000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_SHIFT               27
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_LPBACK_P1 [26:26] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_P1_MASK                0x04000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_P1_SHIFT               26
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE2 [25:25] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE2_MASK              0x02000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE2_SHIFT             25
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE2_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY_P1 [24:24] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_MASK                0x01000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_SHIFT               24
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK                0x00800000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT               23
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK                0x00400000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT               22
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK                0x00200000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT               21
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK                0x00100000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT               20
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                  0x000c0000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                 18
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT               0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT       0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK           0x00010000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT          16
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT        0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PLL_SUSPEND_EN [15:15] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PLL_SUSPEND_EN_MASK               0x00008000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PLL_SUSPEND_EN_SHIFT              15
+#define BCHP_USB_CTRL_UTMI_CTL_1_PLL_SUSPEND_EN_DEFAULT            0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK                0x00007000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT               12
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK [11:11] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_MASK                   0x00000800
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_SHIFT                  11
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_LPBACK [10:10] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_MASK                   0x00000400
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_SHIFT                  10
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE1 [09:09] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_MASK              0x00000200
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_SHIFT             9
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY [08:08] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_MASK                   0x00000100
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_SHIFT                  8
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                   0x00000080
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                  7
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                   0x00000040
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                  6
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                   0x00000020
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                  5
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                   0x00000010
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                  4
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK                     0x0000000c
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                    2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                  0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT          0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK              0x00000001
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT             0
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT           0x00000000
+
+/***************************************************************************
+ *UTMI_CTL_2 - UTMI Control 2 Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK               0xffffffff
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT              0
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SPARE1 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE1 :: SPARE1_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *SPARE2 - Spare2 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE2 :: SPARE2_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_DEFAULT                   0x00000000
+
+#endif /* #ifndef BCHP_USB_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_wktmr.h b/include/linux/brcmstb/7362a0/bchp_wktmr.h
new file mode 100644
index 0000000..e0d95f7
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_wktmr.h
@@ -0,0 +1,108 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_wktmr.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:38p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_WKTMR_H__
+#define BCHP_WKTMR_H__
+
+/***************************************************************************
+ *WKTMR - Wakeup timer
+ ***************************************************************************/
+#define BCHP_WKTMR_EVENT                         0x00408e80 /* Wakeup Timer Register */
+#define BCHP_WKTMR_COUNTER                       0x00408e84 /* Wakeup Counter */
+#define BCHP_WKTMR_ALARM                         0x00408e88 /* Wakeup Timer Alarm */
+#define BCHP_WKTMR_PRESCALER                     0x00408e8c /* Wakeup Timer Prescaler */
+#define BCHP_WKTMR_PRESCALER_VAL                 0x00408e90 /* Wakeup Timer Prescaler Value */
+
+/***************************************************************************
+ *EVENT - Wakeup Timer Register
+ ***************************************************************************/
+/* WKTMR :: EVENT :: reserved0 [31:01] */
+#define BCHP_WKTMR_EVENT_reserved0_MASK                            0xfffffffe
+#define BCHP_WKTMR_EVENT_reserved0_SHIFT                           1
+
+/* WKTMR :: EVENT :: wktmr_alarm_event [00:00] */
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_MASK                    0x00000001
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_SHIFT                   0
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *COUNTER - Wakeup Counter
+ ***************************************************************************/
+/* WKTMR :: COUNTER :: wktmr_counter [31:00] */
+#define BCHP_WKTMR_COUNTER_wktmr_counter_MASK                      0xffffffff
+#define BCHP_WKTMR_COUNTER_wktmr_counter_SHIFT                     0
+#define BCHP_WKTMR_COUNTER_wktmr_counter_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *ALARM - Wakeup Timer Alarm
+ ***************************************************************************/
+/* WKTMR :: ALARM :: wktmr_alarm [31:00] */
+#define BCHP_WKTMR_ALARM_wktmr_alarm_MASK                          0xffffffff
+#define BCHP_WKTMR_ALARM_wktmr_alarm_SHIFT                         0
+#define BCHP_WKTMR_ALARM_wktmr_alarm_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *PRESCALER - Wakeup Timer Prescaler
+ ***************************************************************************/
+/* WKTMR :: PRESCALER :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_reserved0_MASK                        0xfe000000
+#define BCHP_WKTMR_PRESCALER_reserved0_SHIFT                       25
+
+/* WKTMR :: PRESCALER :: wktmr_prescaler [24:00] */
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_MASK                  0x01ffffff
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_SHIFT                 0
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_DEFAULT               0x019bfcc0
+
+/***************************************************************************
+ *PRESCALER_VAL - Wakeup Timer Prescaler Value
+ ***************************************************************************/
+/* WKTMR :: PRESCALER_VAL :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_MASK                    0xfe000000
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_SHIFT                   25
+
+/* WKTMR :: PRESCALER_VAL :: wktmr_prescaler_val [24:00] */
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_MASK          0x01ffffff
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_SHIFT         0
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_DEFAULT       0x00000000
+
+#endif /* #ifndef BCHP_WKTMR_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/brcmirq.h b/include/linux/brcmstb/7362a0/brcmirq.h
new file mode 100644
index 0000000..b899a30
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/brcmirq.h
@@ -0,0 +1,39 @@
+/*
+ * 7360a0 IRQ header file autogenerated by update_bchp.pl
+ * DO NOT EDIT THIS FILE BY HAND.
+ *
+ * Copyright (C) 2012 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BRCMIRQ_H_
+#define _BRCMIRQ_H_
+
+#define BRCM_IRQ_EHCI0_0	66
+#define BRCM_IRQ_GENET_0_A	25
+#define BRCM_IRQ_GENET_0_B	26
+#define BRCM_IRQ_HIF		31
+#define BRCM_IRQ_HIF_SPI	32
+#define BRCM_IRQ_OHCI0_0	67
+#define BRCM_IRQ_SATA		87
+#define BRCM_IRQ_SDIO0		83
+#define BRCM_IRQ_STANDBY	51
+#define BRCM_IRQ_UARTA		62
+#define BRCM_IRQ_UARTB		63
+#define BRCM_IRQ_UARTC		64
+#define BRCM_IRQLIST_EHCI	{ 66 }
+#define BRCM_IRQLIST_OHCI	{ 67 }
+
+#endif /* _BRCMIRQ_H_ */
diff --git a/include/linux/brcmstb/7425b0/bchp_aon_ctrl.h b/include/linux/brcmstb/7425b0/bchp_aon_ctrl.h
new file mode 100644
index 0000000..3f16d4f
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_aon_ctrl.h
@@ -0,0 +1,1570 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:45 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_CTRL_H__
+#define BCHP_AON_CTRL_H__
+
+/***************************************************************************
+ *AON_CTRL - AON Control Registers
+ ***************************************************************************/
+#define BCHP_AON_CTRL_RESET_CTRL                 0x00408000 /* Reset Control register for AON */
+#define BCHP_AON_CTRL_PM_CTRL                    0x00408004 /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_STATUS                  0x00408008 /* Status register for Power Controller */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS        0x0040800c /* Power Management IRQ input status */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT         0x00408010 /* Power Management Wait counter in place of Wait for MIPS IRQ */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER        0x00408014 /* Deep Standby Assertion Timer */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER         0x00408018 /* Deep Standby Wakeup Timer */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE    0x0040801c /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_LED_CTRL                0x00408020 /* LED set control register */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES     0x00408024 /* LED set control register */
+#define BCHP_AON_CTRL_HLCD_CTRL                  0x00408030 /* HW LED Clock Driver Control */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER    0x00408034 /* Second Fraction Counter Initial value */
+#define BCHP_AON_CTRL_TIME_COUNTER               0x00408038 /* Hour/Minute Counter Initial value */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0           0x0040803c /* Digit Code for digit 0, 1, 2, 3 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1           0x00408040 /* Digit Code for digit 4, 5, 6, 7 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2           0x00408044 /* Digit Code for digit 8, 9 */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET      0x00408048 /* Hour MSD/LSD and minute MSD/LSD address offset */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL            0x0040804c /* LED status control */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0             0x00408050 /* General control register 0 */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0           0x00408054 /* General status register 0 */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0     0x00408058 /* General control register without scan 0 */
+#define BCHP_AON_CTRL_SPARE_CTRL_0               0x00408060 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_SPARE_CTRL_1               0x00408064 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH          0x00408068 /* Scratch register */
+#define BCHP_AON_CTRL_RESET_HISTORY              0x0040806c /* Reset History Register For AON */
+#define BCHP_AON_CTRL_NMI_CTRL                   0x00408070 /* Control register for NMI */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL           0x00408074 /* Ana xtal low cur 40g m7fc gisb control */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL         0x00408078 /* Test_mode control register */
+#define BCHP_AON_CTRL_SUB_TEST_MODE              0x0040807c /* Register source for sub_test_mode */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE          0x00408080 /* Final latched testmode value */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE      0x00408084 /* Final latched sub-testmode value */
+#define BCHP_AON_CTRL_PM_INITIATE                0x00408088 /* Power down initiate */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS             0x0040808c /* Power up restore */
+
+/***************************************************************************
+ *RESET_CTRL - Reset Control register for AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_CTRL :: reserved0 [31:04] */
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_MASK                    0xfffffff0
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_SHIFT                   4
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [03:03] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000008
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 3
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable [02:02] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_MASK     0x00000004
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT    2
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_polarity [01:01] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK   0x00000002
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT  1
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_MASK          0x00000001
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_SHIFT         0
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PM_CTRL - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_CTRL :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_MASK                       0xffffff00
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_SHIFT                      8
+
+/* AON_CTRL :: PM_CTRL :: min_s3_width_timer_bypass [07:07] */
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_MASK       0x00000080
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_SHIFT      7
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_DEFAULT    0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_fast_power_down [06:06] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_MASK              0x00000040
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_SHIFT             6
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_DEFAULT           0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_warm_boot [05:05] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_MASK                    0x00000020
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_SHIFT                   5
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_DEFAULT                 0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_deep_standby [04:04] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_MASK                 0x00000010
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_SHIFT                4
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_DEFAULT              0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_clk_divider_reset_en [03:03] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK         0x00000008
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_SHIFT        3
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_DEFAULT      0x00000001
+
+/* AON_CTRL :: PM_CTRL :: pm_use_mips_ready_ctrl [02:02] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_MASK          0x00000004
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_SHIFT         2
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_DEFAULT       0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK             0x00000002
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT            1
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_DEFAULT          0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_MASK                  0x00000001
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT                 0
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PM_STATUS - Status register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_STATUS :: pm_wait_count_upper_bits [31:26] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_MASK      0xfc000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_SHIFT     26
+
+/* AON_CTRL :: PM_STATUS :: pm_wait_counter_active [25:25] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_MASK        0x02000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_SHIFT       25
+
+/* AON_CTRL :: PM_STATUS :: pm_s3_wakeup_reset_ [24:24] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__MASK           0x01000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__SHIFT          24
+
+/* AON_CTRL :: PM_STATUS :: pm_boundary_scan_request [23:23] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_MASK      0x00800000
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_SHIFT     23
+
+/* AON_CTRL :: PM_STATUS :: pm_fast_pd_precharge_valid [22:22] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_MASK    0x00400000
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_SHIFT   22
+
+/* AON_CTRL :: PM_STATUS :: pm_led_out [21:21] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_MASK                    0x00200000
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_SHIFT                   21
+
+/* AON_CTRL :: PM_STATUS :: pm_standby_b [20:20] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_MASK                  0x00100000
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_SHIFT                 20
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs_ng [19:19] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_MASK           0x00080000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_SHIFT          19
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs [18:18] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_MASK              0x00040000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_SHIFT             18
+
+/* AON_CTRL :: PM_STATUS :: pm_rst_clock_div [17:17] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_MASK              0x00020000
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_SHIFT             17
+
+/* AON_CTRL :: PM_STATUS :: pm_pwrdn_pll_req [16:16] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_MASK              0x00010000
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_SHIFT             16
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_xtal_clocks [15:15] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_MASK            0x00008000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_SHIFT           15
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_all_clocks [14:14] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_MASK             0x00004000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_SHIFT            14
+
+/* AON_CTRL :: PM_STATUS :: pm_dphy_standby [13:13] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_MASK               0x00002000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_SHIFT              13
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_cpu_clock [12:12] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_MASK              0x00001000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_SHIFT             12
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_avd_rptd_clock [11:11] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_MASK         0x00000800
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_SHIFT        11
+
+/* AON_CTRL :: PM_STATUS :: pm_power_ctrl_disable [10:10] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_MASK         0x00000400
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_SHIFT        10
+
+/* AON_CTRL :: PM_STATUS :: pm_pll_lock [09:09] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_MASK                   0x00000200
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_SHIFT                  9
+
+/* AON_CTRL :: PM_STATUS :: pm_dram_ready_for_pwrdn [08:08] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_MASK       0x00000100
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_SHIFT      8
+
+/* AON_CTRL :: PM_STATUS :: pm_bsp_ready_for_pwrdn [07:07] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK        0x00000080
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_SHIFT       7
+
+/* AON_CTRL :: PM_STATUS :: pm_mips_ready_for_pwrdn [06:06] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_MASK       0x00000040
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_SHIFT      6
+
+/* AON_CTRL :: PM_STATUS :: pm_sec_avd_rptd_clk_disable [05:05] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_MASK   0x00000020
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_SHIFT  5
+
+/* AON_CTRL :: PM_STATUS :: pm_state [04:00] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_MASK                      0x0000001f
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_SHIFT                     0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_ACTIVE                 0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_PWRDN_RDY              1
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_AVD_RPTD       2
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_CPU            3
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_STANDBY  4
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY                5
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY_WITH_PLLS_ON   6
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_RESET_216_108_CLKS     7
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_ACTIVE   8
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_FAST_PWRDN             9
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S1  10
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_COLD_ENTRY_S2 11
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_WARM_ENTRY_S2 12
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S3  13
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY           14
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S1   15
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S2   16
+
+/***************************************************************************
+ *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
+ ***************************************************************************/
+/* AON_CTRL :: PM_IRQ_INPUT_STATUS :: pm_irq_input_status [31:00] */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_MASK 0xffffffff
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_SHIFT 0
+
+/***************************************************************************
+ *PM_MIPS_WAIT_COUNT - Power Management Wait counter in place of Wait for MIPS IRQ
+ ***************************************************************************/
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_MASK            0xffff0000
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_SHIFT           16
+
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: counter_start_value [15:00] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_MASK  0x0000ffff
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_DEFAULT 0x00000010
+
+/***************************************************************************
+ *PM_S3_STANDBY_TIMER - Deep Standby Assertion Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_MASK           0xf8000000
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_SHIFT          27
+
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_MASK 0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_DEFAULT 0x00083d60
+
+/***************************************************************************
+ *PM_S3_WAKEUP_TIMER - Deep Standby Wakeup Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_MASK            0xf8000000
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_SHIFT           27
+
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_MASK  0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_DEFAULT 0x00083d60
+
+/***************************************************************************
+ *PM_FAST_PWRDN_PRECHARGE - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: reserved0 [31:24] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_MASK       0xff000000
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_SHIFT      24
+
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: pm_fast_power_down_precharge [23:00] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_MASK 0x00ffffff
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_SHIFT 0
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PM_LED_CTRL - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_CTRL :: reserved0 [31:03] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_MASK                   0xfffffff8
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_SHIFT                  3
+
+/* AON_CTRL :: PM_LED_CTRL :: led_status [02:02] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_MASK                  0x00000004
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_SHIFT                 2
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_on [01:01] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_MASK                 0x00000002
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_SHIFT                1
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_off [00:00] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_MASK                0x00000001
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_SHIFT               0
+
+/***************************************************************************
+ *PM_LED_AUTO_ON_ENABLES - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_AUTO_ON_ENABLES :: led_status [31:00] */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_MASK       0xffffffff
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_SHIFT      0
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_DEFAULT    0x00000000
+
+/***************************************************************************
+ *HLCD_CTRL - HW LED Clock Driver Control
+ ***************************************************************************/
+/* AON_CTRL :: HLCD_CTRL :: reserved0 [31:02] */
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_MASK                     0xfffffffc
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_SHIFT                    2
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable_status [01:01] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_MASK            0x00000002
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_SHIFT           1
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable [00:00] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_MASK                   0x00000001
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_SHIFT                  0
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_DEFAULT                0x00000000
+
+/***************************************************************************
+ *SECOND_FRACTION_COUNTER - Second Fraction Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: reserved0 [31:25] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_MASK       0xfe000000
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_SHIFT      25
+
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: second_fraction_counter_init [24:00] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_MASK 0x01ffffff
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_SHIFT 0
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TIME_COUNTER - Hour/Minute Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: TIME_COUNTER :: reserved0 [31:20] */
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_MASK                  0xfff00000
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_SHIFT                 20
+
+/* AON_CTRL :: TIME_COUNTER :: hour_display_mode [19:19] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_MASK          0x00080000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_SHIFT         19
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: mode_12h_24h_init [18:18] */
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_MASK          0x00040000
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_SHIFT         18
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: am_pm_counter_init [17:17] */
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_MASK         0x00020000
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_SHIFT        17
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_DEFAULT      0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: hour_counter_init [16:12] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_MASK          0x0001f000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_SHIFT         12
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: minute_counter_init [11:06] */
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_MASK        0x00000fc0
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_SHIFT       6
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_DEFAULT     0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: second_counter_init [05:00] */
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_MASK        0x0000003f
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_SHIFT       0
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_DEFAULT     0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_0 - Digit Code for digit 0, 1, 2, 3
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_3 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_2 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_1 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_0 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_1 - Digit Code for digit 4, 5, 6, 7
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_7 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_6 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_5 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_4 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_2 - Digit Code for digit 8, 9
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_MASK              0xffff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_SHIFT             16
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_9 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_8 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_ADDR_OFFSET - Hour MSD/LSD and minute MSD/LSD address offset
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_msd_addr_offset [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_MASK 0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_SHIFT 24
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_DEFAULT 0x00000020
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_lsd_addr_offset [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_MASK 0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_SHIFT 16
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_DEFAULT 0x00000024
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_msd_addr_offset [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_MASK 0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_SHIFT 8
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_DEFAULT 0x00000018
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_lsd_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_MASK 0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_SHIFT 0
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_DEFAULT 0x0000001c
+
+/***************************************************************************
+ *LED_STATUS_CTRL - LED status control
+ ***************************************************************************/
+/* AON_CTRL :: LED_STATUS_CTRL :: reserved0 [31:28] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_MASK               0xf0000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_SHIFT              28
+
+/* AON_CTRL :: LED_STATUS_CTRL :: hlcd_state [27:25] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_MASK              0x0e000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_SHIFT             25
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_IDLE         0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_COUNT        1
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_LSD 2
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_MSD 3
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_LSD 4
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_MSD 5
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_STATUS 6
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_update_enable [24:24] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_MASK    0x01000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_SHIFT   24
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_DEFAULT 0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_mask [23:12] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_MASK             0x00fff000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_SHIFT            12
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_DEFAULT          0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_bit_offset [11:08] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_MASK       0x00000f00
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_SHIFT      8
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_DEFAULT    0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_MASK      0x000000ff
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_SHIFT     0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK         0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT        31
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK         0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT        30
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK         0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT        29
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK         0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT        28
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK         0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT        27
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK         0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT        26
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK         0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT        25
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK         0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT        24
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK         0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT        23
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK         0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT        22
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK         0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT        21
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK         0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT        20
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK         0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT        19
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK         0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT        18
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK         0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT        17
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK         0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT        16
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK         0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT        15
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK         0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT        14
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK         0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT        13
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK         0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT        12
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK         0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT        11
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK         0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT        10
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK          0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT         9
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK          0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT         8
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK          0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT         7
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK          0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT         6
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK          0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT         5
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK          0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT         4
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK          0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT         3
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK          0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT         2
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK          0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT         1
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK          0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT         0
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT       0x00000000
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_MASK              0xffffff00
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_SHIFT             8
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_MASK      0x00000080
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT     7
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_MASK      0x00000040
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT     6
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_MASK      0x00000020
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT     5
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_MASK      0x00000010
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT     4
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_MASK      0x00000008
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT     3
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_MASK      0x00000004
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT     2
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_MASK      0x00000002
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT     1
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: ejtag_ce_wakeup_event [00:00] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_MASK  0x00000001
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_MASK 0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_SHIFT 31
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_MASK 0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_SHIFT 30
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_MASK 0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_SHIFT 29
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_MASK 0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_SHIFT 28
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_MASK 0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_SHIFT 27
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_MASK 0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_SHIFT 26
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_MASK 0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_SHIFT 25
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_MASK 0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_SHIFT 24
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_MASK 0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_SHIFT 23
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_MASK 0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_SHIFT 22
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_MASK 0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_SHIFT 21
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_MASK 0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_SHIFT 20
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_MASK 0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_SHIFT 19
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_MASK 0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_SHIFT 18
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_MASK 0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_SHIFT 17
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_MASK 0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_SHIFT 16
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_MASK 0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_SHIFT 15
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_MASK 0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_SHIFT 14
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_MASK 0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_SHIFT 13
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_MASK 0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_SHIFT 12
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_MASK 0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_SHIFT 11
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_MASK 0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_SHIFT 10
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_MASK 0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_SHIFT 5
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_MASK 0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_SHIFT 4
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_MASK 0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_SHIFT 3
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_MASK 0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_SHIFT 2
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_MASK 0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_SHIFT 0
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL_0 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_DEFAULT           0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL_1 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_DEFAULT           0x00000000
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* AON_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK     0xffffffff
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT    0
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT  0x00000000
+
+/***************************************************************************
+ *RESET_HISTORY - Reset History Register For AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_HISTORY :: reserved0 [31:19] */
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_MASK                 0xfff80000
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_SHIFT                19
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [18:18] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK    0x00040000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT   18
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [17:17] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK    0x00020000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT   17
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [16:16] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK     0x00010000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT    16
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [15:15] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK     0x00008000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT    15
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [14:14] */
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK           0x00004000
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT          14
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_DEFAULT        0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: overtemp_reset [13:13] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_MASK            0x00002000
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_SHIFT           13
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_DEFAULT         0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: overvoltage_reset [12:12] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_MASK         0x00001000
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT        12
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_DEFAULT      0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: undervoltage_reset [11:11] */
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_MASK        0x00000800
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT       11
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_DEFAULT     0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: security_dl_sw_reset [10:10] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK      0x00000400
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT     10
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_DEFAULT   0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: security_master_reset [09:09] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_MASK     0x00000200
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_SHIFT    9
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: software_master_reset [08:08] */
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_MASK     0x00000100
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_SHIFT    8
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [07:07] */
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK       0x00000080
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT      7
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_DEFAULT    0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: watchdog_timer_reset [06:06] */
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK      0x00000040
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT     6
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_DEFAULT   0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: smartcard_insert_reset [05:05] */
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK    0x00000020
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT   5
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: s3_wakeup_reset [04:04] */
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_MASK           0x00000010
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_SHIFT          4
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_DEFAULT        0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [03:03] */
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK    0x00000008
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT   3
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: tap_in_system_reset [02:02] */
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_MASK       0x00000004
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_SHIFT      2
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_DEFAULT    0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_MASK     0x00000002
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT    1
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_MASK            0x00000001
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_SHIFT           0
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_DEFAULT         0x00000001
+
+/***************************************************************************
+ *NMI_CTRL - Control register for NMI
+ ***************************************************************************/
+/* AON_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_MASK                0x80000000
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_SHIFT               31
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_DEFAULT             0x00000000
+
+/* AON_CTRL :: NMI_CTRL :: reserved0 [30:03] */
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_MASK                      0x7ffffff8
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_SHIFT                     3
+
+/* AON_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_MASK                0x00000004
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT               2
+
+/* AON_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_MASK            0x00000002
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT           1
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_DEFAULT         0x00000000
+
+/* AON_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_MASK                0x00000001
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT               0
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_DEFAULT             0x00000001
+
+/***************************************************************************
+ *ANA_XTAL_CONTROL - Ana xtal low cur 40g m7fc gisb control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_CONTROL :: reserved0 [31:07] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_MASK              0xffffff80
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_SHIFT             7
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_test_select_gisb_control [06:06] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_MASK 0x00000040
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_SHIFT 6
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_select_current_gisb_control [05:05] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_MASK 0x00000020
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_SHIFT 5
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_cml_sel_pd [04:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_MASK         0x00000018
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_SHIFT        3
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_DEFAULT      0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_d2cbias_gisb_control [02:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_MASK 0x00000007
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_SHIFT 0
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_DEFAULT 0x00000004
+
+/***************************************************************************
+ *SUB_TEST_MODE_CTRL - Test_mode control register
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: reserved0 [31:01] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_MASK            0xfffffffe
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_SHIFT           1
+
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: use_sub_test_mode_reg_src [00:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_MASK 0x00000001
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_SHIFT 0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SUB_TEST_MODE - Register source for sub_test_mode
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_MASK                 0xffffff00
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_SHIFT                8
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [07:07] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK     0x00000080
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT    7
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_DEFAULT  0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [06:06] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK     0x00000040
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT    6
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_DEFAULT  0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [05:05] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK   0x00000020
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT  5
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_mips_in_reset [04:04] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_MASK 0x00000010
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_SHIFT 4
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [03:03] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000008
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 3
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [02:02] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000004
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 2
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK   0x00000003
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT  0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_DEFAULT 0x00000000
+
+/***************************************************************************
+ *LATCHED_TEST_MODE - Final latched testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK     0xffffffff
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT    0
+
+/***************************************************************************
+ *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0
+
+/***************************************************************************
+ *PM_INITIATE - Power down initiate
+ ***************************************************************************/
+/* AON_CTRL :: PM_INITIATE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_MASK                   0xffffff00
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_SHIFT                  8
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_7 [07:07] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_MASK               0x00000080
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_SHIFT              7
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_6 [06:06] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_MASK               0x00000040
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_SHIFT              6
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_5 [05:05] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_MASK               0x00000020
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_SHIFT              5
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_4 [04:04] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_MASK               0x00000010
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_SHIFT              4
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_3 [03:03] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_MASK               0x00000008
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_SHIFT              3
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_2 [02:02] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_MASK               0x00000004
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_SHIFT              2
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_1 [01:01] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_MASK               0x00000002
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_SHIFT              1
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_0 [00:00] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_MASK               0x00000001
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_SHIFT              0
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_DEFAULT            0x00000000
+
+/***************************************************************************
+ *HOST_MISC_CMDS - Power up restore
+ ***************************************************************************/
+/* AON_CTRL :: HOST_MISC_CMDS :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_MASK                0xffffff00
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_SHIFT               8
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_7 [07:07] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_MASK         0x00000080
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_SHIFT        7
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_6 [06:06] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_MASK         0x00000040
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_SHIFT        6
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_5 [05:05] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_MASK         0x00000020
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_SHIFT        5
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_4 [04:04] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_MASK         0x00000010
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_SHIFT        4
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_3 [03:03] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_MASK         0x00000008
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_SHIFT        3
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_2 [02:02] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_MASK         0x00000004
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_SHIFT        2
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: dram_scram_key_reuse_req [01:01] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_MASK 0x00000002
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_SHIFT 1
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_DEFAULT 0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: pm_restore [00:00] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_MASK               0x00000001
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_SHIFT              0
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_BASE                  0x00408200
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_START                 0
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_END                   127
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_ELEMENT_SIZE          32
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_RAMi :: SYSTEM_DATA_RAM [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_MASK        0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_SHIFT       0
+
+
+#endif /* #ifndef BCHP_AON_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_aon_pin_ctrl.h b/include/linux/brcmstb/7425b0/bchp_aon_pin_ctrl.h
new file mode 100644
index 0000000..0761fa8
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_aon_pin_ctrl.h
@@ -0,0 +1,544 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:43 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PIN_CTRL_H__
+#define BCHP_AON_PIN_CTRL_H__
+
+/***************************************************************************
+ *AON_PIN_CTRL - AON Pinmux Control Registers
+ ***************************************************************************/
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0         0x00408500 /* Pinmux control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1         0x00408504 /* Pinmux control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2         0x00408508 /* Pinmux control register 2 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3         0x0040850c /* Pinmux control register 3 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0     0x00408510 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1     0x00408514 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0     0x00408518 /* Bypass clock unselect register 0 */
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_07 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_AON_GPIO_07   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_LED_LS_3      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_UART_CTS_0    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_SATA_MDCLK    3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_06 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_AON_GPIO_06   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_LED_LS_2      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_UART_TXD_0    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_MDIO_SATA     3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_05 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_AON_GPIO_05   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_LS_1      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_UART_RXD_0    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SPI_M_SS1B    3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_04 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_AON_GPIO_04   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_LS_0      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_EMAC0_IRQ     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_EMAC1_IRQ     3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_03 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_GPIO_03   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_KD_3      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_I2S_LR0_IN    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_I2S_LR0_OUT   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MDC_PCIE      4
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_02 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_AON_GPIO_02   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_LED_KD_2      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_I2S_DATA0_IN  2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_I2S_DATA0_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_MDIO_PCIE     4
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_01 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AON_GPIO_01   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_LED_KD_1      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_I2S_CLK0_IN   2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_I2S_CLK0_OUT  3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_00 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AON_GPIO_00   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_LED_KD_0      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_EMAC0_IRQ     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_EMAC1_IRQ     3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_15 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_AON_GPIO_15   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_LED_LD_6      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_UART_CTS_2    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_SPI_M_MISO    3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_14 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_AON_GPIO_14   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_LED_LD_5      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_UART_TXD_2    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_SPI_M_MOSI    3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_13 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_AON_GPIO_13   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_LED_LD_4      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_UART_RXD_2    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SPI_M_SCK     3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_12 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_AON_GPIO_12   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_LD_3      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_UART_CTS_1    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_I2S_LR0_OUT   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_I2S_LR0_IN    4
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_11 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_GPIO_11   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_LED_LD_2      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_UART_RTS_1    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_I2S_DATA0_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_I2S_DATA0_IN  4
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_10 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_AON_GPIO_10   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_LED_LD_1      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_UART_TXD_1    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_I2S_CLK0_OUT  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_I2S_CLK0_IN   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SPI_M_SS2B    5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_09 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_AON_GPIO_09   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_LED_LD_0      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_UART_RXD_1    2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_08 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_AON_GPIO_08   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_LED_LS_4      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_UART_RTS_0    2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_01 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_MASK         0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_SHIFT        28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_AON_SGPIO_01 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_BSC_M0_SDA   1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_00 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_MASK         0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SHIFT        24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_AON_SGPIO_00 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_BSC_M0_SCL   1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: gpio_102 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_102_MASK             0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_102_SHIFT            20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_102_DEFAULT          0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_102_GPIO_102         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_102_VO0_656_0        1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_102_VO1_656_0        2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_102_RMX_CLK0         3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_102_TP_OUT_03        4
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: gpio_101 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_101_MASK             0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_101_SHIFT            16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_101_DEFAULT          0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_101_GPIO_101         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_101_IR_INT           1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_101_SC_CLK_OUT       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_101_BT_CLK_26087     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_101_LED_LD_12        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_101_TP_OUT_02        5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: gpio_100 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_100_MASK             0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_100_SHIFT            12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_100_DEFAULT          0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_100_GPIO_100         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_100_PWM_1            1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_100_AUD_FS_CLK1      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_100_VEC_VSYNC_1      3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_100_SPI_M_SS2B       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_100_SDIO0_VOLT       5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_100_TP_OUT_01        6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: gpio_099 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_099_MASK             0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_099_SHIFT            8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_099_DEFAULT          0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_099_GPIO_099         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_099_PWM_0            1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_099_AUD_FS_CLK0      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_099_VEC_VSYNC_0      3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_099_LED_LD_11        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_099_TP_OUT_00        5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_17 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_DEFAULT       0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_AON_GPIO_17   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_LED_OUT       1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_16 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_AON_GPIO_16   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_LED_LD_7      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_UART_RTS_2    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SPI_M_SS0B    3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: reserved0 [31:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_MASK            0xffff0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_SHIFT           16
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_05 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_MASK         0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_SHIFT        12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_AON_SGPIO_05 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_BSC_M4_SDA   1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_04 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_MASK         0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_SHIFT        8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_AON_SGPIO_04 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_BSC_M4_SCL   1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_03 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_MASK         0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_SHIFT        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_AON_SGPIO_03 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_BSC_M1_SDA   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_BSC_S1_SDA   2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_02 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_02_MASK         0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_02_SHIFT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_02_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_02_AON_SGPIO_02 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_02_BSC_M1_SCL   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_02_BSC_S1_SCL   2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_12_pad_ctrl [29:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_MASK 0x30000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_SHIFT 28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_11_pad_ctrl [27:26] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_MASK 0x0c000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_SHIFT 26
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_10_pad_ctrl [25:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_10_pad_ctrl_MASK 0x03000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_10_pad_ctrl_SHIFT 24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_10_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_10_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_09_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_08_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_07_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_06_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_05_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_04_pad_ctrl [13:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_MASK 0x00003000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_SHIFT 12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_03_pad_ctrl [11:10] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_MASK 0x00000c00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_SHIFT 10
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_02_pad_ctrl [09:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_MASK 0x00000300
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_SHIFT 8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_01_pad_ctrl [07:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_MASK 0x000000c0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_SHIFT 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_00_pad_ctrl [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:10] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0x3ffffc00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       10
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_17_pad_ctrl [09:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_MASK 0x00000300
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_SHIFT 8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_16_pad_ctrl [07:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_MASK 0x000000c0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_SHIFT 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_15_pad_ctrl [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_14_pad_ctrl [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_13_pad_ctrl [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_MASK 0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_SHIFT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:08] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xffffff00
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       8
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_10 [07:07] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_10_MASK 0x00000080
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_10_SHIFT 7
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_10_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_09 [06:06] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_09_MASK 0x00000040
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_09_SHIFT 6
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_09_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_07 [05:05] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_07_MASK 0x00000020
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_07_SHIFT 5
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_07_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_06 [04:04] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_06_MASK 0x00000010
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_06_SHIFT 4
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_06_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_05 [03:03] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_05_MASK 0x00000008
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_05_SHIFT 3
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_05_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_04 [02:02] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_04_MASK 0x00000004
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_04_SHIFT 2
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_04_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_03 [01:01] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_03_MASK 0x00000002
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_03_SHIFT 1
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_03_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_02 [00:00] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_02_MASK 0x00000001
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_02_SHIFT 0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_02_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_AON_PIN_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_aon_pm_l2.h b/include/linux/brcmstb/7425b0/bchp_aon_pm_l2.h
new file mode 100644
index 0000000..07ab0619
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_aon_pm_l2.h
@@ -0,0 +1,1164 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:42 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PM_L2_H__
+#define BCHP_AON_PM_L2_H__
+
+/***************************************************************************
+ *AON_PM_L2 - AON Power Management L2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_AON_PM_L2_CPU_STATUS                0x00408440 /* CPU interrupt Status Register */
+#define BCHP_AON_PM_L2_CPU_SET                   0x00408444 /* CPU interrupt Set Register */
+#define BCHP_AON_PM_L2_CPU_CLEAR                 0x00408448 /* CPU interrupt Clear Register */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS           0x0040844c /* CPU interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_CPU_MASK_SET              0x00408450 /* CPU interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR            0x00408454 /* CPU interrupt Mask Clear Register */
+#define BCHP_AON_PM_L2_PCI_STATUS                0x00408458 /* PCI interrupt Status Register */
+#define BCHP_AON_PM_L2_PCI_SET                   0x0040845c /* PCI interrupt Set Register */
+#define BCHP_AON_PM_L2_PCI_CLEAR                 0x00408460 /* PCI interrupt Clear Register */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS           0x00408464 /* PCI interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_PCI_MASK_SET              0x00408468 /* PCI interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR            0x0040846c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_STATUS :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_MASK                   0xfffe0000
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_SHIFT                  17
+
+/* AON_PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x00010000
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       16
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_MASK                    0x00008000
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_SHIFT                   15
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00004000
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_SHIFT          14
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_MASK                        0x00002000
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_SHIFT                       13
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_MASK                        0x00001000
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_SHIFT                       12
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_MASK                        0x00000800
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_SHIFT                       11
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_MASK                     0x00000400
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_SHIFT                    10
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: CAP [09:09] */
+#define BCHP_AON_PM_L2_CPU_STATUS_CAP_MASK                         0x00000200
+#define BCHP_AON_PM_L2_CPU_STATUS_CAP_SHIFT                        9
+#define BCHP_AON_PM_L2_CPU_STATUS_CAP_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_MASK                    0x00000100
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_SHIFT                   8
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_MASK                    0x00000080
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_SHIFT                   7
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_STATUS_UHFR_MASK                        0x00000040
+#define BCHP_AON_PM_L2_CPU_STATUS_UHFR_SHIFT                       6
+#define BCHP_AON_PM_L2_CPU_STATUS_UHFR_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_SET :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_MASK                      0xfffe0000
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_SHIFT                     17
+
+/* AON_PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_MASK           0x00010000
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_SHIFT          16
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_MASK                       0x00008000
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_SHIFT                      15
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_MASK              0x00004000
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_SHIFT             14
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_DEFAULT           0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_CPU_SET_USB1_MASK                           0x00002000
+#define BCHP_AON_PM_L2_CPU_SET_USB1_SHIFT                          13
+#define BCHP_AON_PM_L2_CPU_SET_USB1_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_CPU_SET_USB0_MASK                           0x00001000
+#define BCHP_AON_PM_L2_CPU_SET_USB0_SHIFT                          12
+#define BCHP_AON_PM_L2_CPU_SET_USB0_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_MASK                           0x00000800
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_SHIFT                          11
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_MASK                        0x00000400
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_SHIFT                       10
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: CAP [09:09] */
+#define BCHP_AON_PM_L2_CPU_SET_CAP_MASK                            0x00000200
+#define BCHP_AON_PM_L2_CPU_SET_CAP_SHIFT                           9
+#define BCHP_AON_PM_L2_CPU_SET_CAP_DEFAULT                         0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_MASK                       0x00000100
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_SHIFT                      8
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_MOCA_MASK                       0x00000080
+#define BCHP_AON_PM_L2_CPU_SET_WOL_MOCA_SHIFT                      7
+#define BCHP_AON_PM_L2_CPU_SET_WOL_MOCA_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_SET_UHFR_MASK                           0x00000040
+#define BCHP_AON_PM_L2_CPU_SET_UHFR_SHIFT                          6
+#define BCHP_AON_PM_L2_CPU_SET_UHFR_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_CLEAR :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_MASK                    0xfffe0000
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_SHIFT                   17
+
+/* AON_PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x00010000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        16
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_MASK                     0x00008000
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_SHIFT                    15
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00004000
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           14
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_MASK                         0x00002000
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_SHIFT                        13
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_MASK                         0x00001000
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_SHIFT                        12
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_MASK                         0x00000800
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_SHIFT                        11
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_MASK                      0x00000400
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT                     10
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: CAP [09:09] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_CAP_MASK                          0x00000200
+#define BCHP_AON_PM_L2_CPU_CLEAR_CAP_SHIFT                         9
+#define BCHP_AON_PM_L2_CPU_CLEAR_CAP_DEFAULT                       0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_MASK                     0x00000100
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_SHIFT                    8
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_MOCA_MASK                     0x00000080
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_MOCA_SHIFT                    7
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_MOCA_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_UHFR_MASK                         0x00000040
+#define BCHP_AON_PM_L2_CPU_CLEAR_UHFR_SHIFT                        6
+#define BCHP_AON_PM_L2_CPU_CLEAR_UHFR_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_MASK              0xfffe0000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT             17
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x00010000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  16
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_MASK               0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_SHIFT              15
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     14
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_MASK                   0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_SHIFT                  13
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_MASK                   0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_SHIFT                  12
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_MASK                   0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_SHIFT                  11
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK                0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT               10
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: CAP [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CAP_MASK                    0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CAP_SHIFT                   9
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CAP_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_MASK               0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_SHIFT              8
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_MOCA_MASK               0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_MOCA_SHIFT              7
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_MOCA_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_UHFR_MASK                   0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_UHFR_SHIFT                  6
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_UHFR_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_DEFAULT            0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_SET :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_MASK                 0xfffe0000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_SHIFT                17
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x00010000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     16
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_MASK                  0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_SHIFT                 15
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        14
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_MASK                      0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_SHIFT                     13
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_MASK                      0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_SHIFT                     12
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_MASK                      0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_SHIFT                     11
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_MASK                   0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT                  10
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: CAP [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CAP_MASK                       0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CAP_SHIFT                      9
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CAP_DEFAULT                    0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_MASK                  0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_SHIFT                 8
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_MOCA_MASK                  0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_MOCA_SHIFT                 7
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_MOCA_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_UHFR_MASK                      0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_SET_UHFR_SHIFT                     6
+#define BCHP_AON_PM_L2_CPU_MASK_SET_UHFR_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_DEFAULT               0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_MASK               0xfffe0000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT              17
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x00010000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   16
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_MASK                0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_SHIFT               15
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      14
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_MASK                    0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_SHIFT                   13
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_MASK                    0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_SHIFT                   12
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_MASK                    0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_SHIFT                   11
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK                 0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT                10
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: CAP [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CAP_MASK                     0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CAP_SHIFT                    9
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CAP_DEFAULT                  0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_MASK                0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_SHIFT               8
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_MASK                0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_SHIFT               7
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_UHFR_MASK                    0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_UHFR_SHIFT                   6
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_UHFR_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_DEFAULT             0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_STATUS :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_MASK                   0xfffe0000
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_SHIFT                  17
+
+/* AON_PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x00010000
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       16
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_MASK                    0x00008000
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_SHIFT                   15
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00004000
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_SHIFT          14
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_MASK                        0x00002000
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_SHIFT                       13
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_MASK                        0x00001000
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_SHIFT                       12
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_MASK                        0x00000800
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_SHIFT                       11
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_MASK                     0x00000400
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_SHIFT                    10
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: CAP [09:09] */
+#define BCHP_AON_PM_L2_PCI_STATUS_CAP_MASK                         0x00000200
+#define BCHP_AON_PM_L2_PCI_STATUS_CAP_SHIFT                        9
+#define BCHP_AON_PM_L2_PCI_STATUS_CAP_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_MASK                    0x00000100
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_SHIFT                   8
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_MOCA_MASK                    0x00000080
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_MOCA_SHIFT                   7
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_MOCA_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_STATUS_UHFR_MASK                        0x00000040
+#define BCHP_AON_PM_L2_PCI_STATUS_UHFR_SHIFT                       6
+#define BCHP_AON_PM_L2_PCI_STATUS_UHFR_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_SET :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_MASK                      0xfffe0000
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_SHIFT                     17
+
+/* AON_PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_MASK           0x00010000
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_SHIFT          16
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_MASK                       0x00008000
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_SHIFT                      15
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_MASK              0x00004000
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_SHIFT             14
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_DEFAULT           0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_PCI_SET_USB1_MASK                           0x00002000
+#define BCHP_AON_PM_L2_PCI_SET_USB1_SHIFT                          13
+#define BCHP_AON_PM_L2_PCI_SET_USB1_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_PCI_SET_USB0_MASK                           0x00001000
+#define BCHP_AON_PM_L2_PCI_SET_USB0_SHIFT                          12
+#define BCHP_AON_PM_L2_PCI_SET_USB0_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_MASK                           0x00000800
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_SHIFT                          11
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_MASK                        0x00000400
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_SHIFT                       10
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: CAP [09:09] */
+#define BCHP_AON_PM_L2_PCI_SET_CAP_MASK                            0x00000200
+#define BCHP_AON_PM_L2_PCI_SET_CAP_SHIFT                           9
+#define BCHP_AON_PM_L2_PCI_SET_CAP_DEFAULT                         0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_MASK                       0x00000100
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_SHIFT                      8
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_MOCA_MASK                       0x00000080
+#define BCHP_AON_PM_L2_PCI_SET_WOL_MOCA_SHIFT                      7
+#define BCHP_AON_PM_L2_PCI_SET_WOL_MOCA_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_SET_UHFR_MASK                           0x00000040
+#define BCHP_AON_PM_L2_PCI_SET_UHFR_SHIFT                          6
+#define BCHP_AON_PM_L2_PCI_SET_UHFR_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_CLEAR :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_MASK                    0xfffe0000
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_SHIFT                   17
+
+/* AON_PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x00010000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        16
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_MASK                     0x00008000
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_SHIFT                    15
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00004000
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           14
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_MASK                         0x00002000
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_SHIFT                        13
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_MASK                         0x00001000
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_SHIFT                        12
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_MASK                         0x00000800
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_SHIFT                        11
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_MASK                      0x00000400
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT                     10
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: CAP [09:09] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_CAP_MASK                          0x00000200
+#define BCHP_AON_PM_L2_PCI_CLEAR_CAP_SHIFT                         9
+#define BCHP_AON_PM_L2_PCI_CLEAR_CAP_DEFAULT                       0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_MASK                     0x00000100
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_SHIFT                    8
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_MOCA_MASK                     0x00000080
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_MOCA_SHIFT                    7
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_MOCA_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_UHFR_MASK                         0x00000040
+#define BCHP_AON_PM_L2_PCI_CLEAR_UHFR_SHIFT                        6
+#define BCHP_AON_PM_L2_PCI_CLEAR_UHFR_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_MASK              0xfffe0000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT             17
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x00010000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  16
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_MASK               0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_SHIFT              15
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     14
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_MASK                   0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_SHIFT                  13
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_MASK                   0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_SHIFT                  12
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_MASK                   0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_SHIFT                  11
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK                0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT               10
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: CAP [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CAP_MASK                    0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CAP_SHIFT                   9
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CAP_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_MASK               0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_SHIFT              8
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_MOCA_MASK               0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_MOCA_SHIFT              7
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_MOCA_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_UHFR_MASK                   0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_UHFR_SHIFT                  6
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_UHFR_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_DEFAULT            0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_SET :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_MASK                 0xfffe0000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_SHIFT                17
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x00010000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     16
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_MASK                  0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_SHIFT                 15
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        14
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_MASK                      0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_SHIFT                     13
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_MASK                      0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_SHIFT                     12
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_MASK                      0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_SHIFT                     11
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_MASK                   0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT                  10
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: CAP [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CAP_MASK                       0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CAP_SHIFT                      9
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CAP_DEFAULT                    0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_MASK                  0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_SHIFT                 8
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_MOCA_MASK                  0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_MOCA_SHIFT                 7
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_MOCA_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_UHFR_MASK                      0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_SET_UHFR_SHIFT                     6
+#define BCHP_AON_PM_L2_PCI_MASK_SET_UHFR_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_DEFAULT               0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_MASK               0xfffe0000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT              17
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x00010000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   16
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_MASK                0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_SHIFT               15
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      14
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_MASK                    0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_SHIFT                   13
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_MASK                    0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_SHIFT                   12
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_MASK                    0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_SHIFT                   11
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK                 0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT                10
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: CAP [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CAP_MASK                     0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CAP_SHIFT                    9
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CAP_DEFAULT                  0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_MASK                0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_SHIFT               8
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_MASK                0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_SHIFT               7
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_UHFR_MASK                    0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_UHFR_SHIFT                   6
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_UHFR_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_DEFAULT             0x00000001
+
+#endif /* #ifndef BCHP_AON_PM_L2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_bspi.h b/include/linux/brcmstb/7425b0/bchp_bspi.h
new file mode 100644
index 0000000..d44fab4
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_bspi.h
@@ -0,0 +1,443 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:44 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_H__
+#define BCHP_BSPI_H__
+
+/***************************************************************************
+ *BSPI - Public BSPI Control Registers
+ ***************************************************************************/
+#define BCHP_BSPI_REVISION_ID                    0x0041c000 /* Revision ID */
+#define BCHP_BSPI_SCRATCH                        0x0041c004 /* Revision ID */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL               0x0041c008 /* Master/Boot SPI Control Register */
+#define BCHP_BSPI_BUSY_STATUS                    0x0041c00c /* BSPI Busy Status Register */
+#define BCHP_BSPI_INTR_STATUS                    0x0041c010 /* Interrupt Status Register */
+#define BCHP_BSPI_B0_STATUS                      0x0041c014 /* Prefetch Buffer 0 Status Register */
+#define BCHP_BSPI_B0_CTRL                        0x0041c018 /* Prefetch Buffer 0 Control Register */
+#define BCHP_BSPI_B1_STATUS                      0x0041c01c /* Prefetch Buffer 1 Status Register */
+#define BCHP_BSPI_B1_CTRL                        0x0041c020 /* Prefetch Buffer 1 Control Register */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL            0x0041c024 /* Dual/Single Receive Mode Control Register */
+#define BCHP_BSPI_FLEX_MODE_ENABLE               0x0041c028 /* Flexible Control Mode Enable Register */
+#define BCHP_BSPI_BITS_PER_CYCLE                 0x0041c02c /* Bits per cycle "b-p-c" Control Register */
+#define BCHP_BSPI_BITS_PER_PHASE                 0x0041c030 /* Bits per Phase "b-p-p" Control Register */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE              0x0041c034 /* Command and Mode Data Register */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE     0x0041c038 /* Bspi FLash upper address byte register */
+#define BCHP_BSPI_BSPI_XOR_VALUE                 0x0041c03c /* BSPI FLASH XOR Value Register */
+#define BCHP_BSPI_BSPI_XOR_ENABLE                0x0041c040 /* BSPI FLASH XOR Enable Register */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE           0x0041c044 /* BSPI Pin  Programmed IO Mode Enable Register */
+#define BCHP_BSPI_BSPI_PIO_IODIR                 0x0041c048 /* BSPI Pin  Programmed IO Mode Direction Register */
+#define BCHP_BSPI_BSPI_PIO_DATA                  0x0041c04c /* BSPI Pin  Programmed IO Mode Data Register */
+
+/***************************************************************************
+ *REVISION_ID - Revision ID
+ ***************************************************************************/
+/* BSPI :: REVISION_ID :: reserved0 [31:16] */
+#define BCHP_BSPI_REVISION_ID_reserved0_MASK                       0xffff0000
+#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT                      16
+
+/* BSPI :: REVISION_ID :: MAJOR [15:08] */
+#define BCHP_BSPI_REVISION_ID_MAJOR_MASK                           0x0000ff00
+#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT                          8
+#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT                        0x00000004
+
+/* BSPI :: REVISION_ID :: MINOR [07:00] */
+#define BCHP_BSPI_REVISION_ID_MINOR_MASK                           0x000000ff
+#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT                          0
+#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *SCRATCH - Revision ID
+ ***************************************************************************/
+/* BSPI :: SCRATCH :: SCRATCH [31:00] */
+#define BCHP_BSPI_SCRATCH_SCRATCH_MASK                             0xffffffff
+#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT                            0
+#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
+ ***************************************************************************/
+/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT                 1
+
+/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK                0x00000001
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT               0
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT             0x00000000
+
+/***************************************************************************
+ *BUSY_STATUS - BSPI Busy Status Register
+ ***************************************************************************/
+/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
+#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK                       0xfffffffe
+#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT                      1
+
+/* BSPI :: BUSY_STATUS :: busy [00:00] */
+#define BCHP_BSPI_BUSY_STATUS_busy_MASK                            0x00000001
+#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT                           0
+#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *INTR_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
+#define BCHP_BSPI_INTR_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT                      2
+
+/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
+#define BCHP_BSPI_INTR_STATUS_intr_1_MASK                          0x00000002
+#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT                         1
+#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT                       0x00000000
+
+/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
+#define BCHP_BSPI_INTR_STATUS_intr_0_MASK                          0x00000001
+#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT                         0
+#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *B0_STATUS - Prefetch Buffer 0 Status Register
+ ***************************************************************************/
+/* BSPI :: B0_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B0_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B0_STATUS :: b0_full [29:29] */
+#define BCHP_BSPI_B0_STATUS_b0_full_MASK                           0x20000000
+#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT                          29
+#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_empty [28:28] */
+#define BCHP_BSPI_B0_STATUS_b0_empty_MASK                          0x10000000
+#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT                         28
+#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B0_STATUS :: b0_miss [27:27] */
+#define BCHP_BSPI_B0_STATUS_b0_miss_MASK                           0x08000000
+#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT                          27
+#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_hit [26:26] */
+#define BCHP_BSPI_B0_STATUS_b0_hit_MASK                            0x04000000
+#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT                           26
+#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B0_STATUS :: b0_address [25:00] */
+#define BCHP_BSPI_B0_STATUS_b0_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT                       0
+#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B0_CTRL - Prefetch Buffer 0 Control Register
+ ***************************************************************************/
+/* BSPI :: B0_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B0_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B0_CTRL :: b0_flush [00:00] */
+#define BCHP_BSPI_B0_CTRL_b0_flush_MASK                            0x00000001
+#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT                           0
+#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *B1_STATUS - Prefetch Buffer 1 Status Register
+ ***************************************************************************/
+/* BSPI :: B1_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B1_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B1_STATUS :: b1_full [29:29] */
+#define BCHP_BSPI_B1_STATUS_b1_full_MASK                           0x20000000
+#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT                          29
+#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_empty [28:28] */
+#define BCHP_BSPI_B1_STATUS_b1_empty_MASK                          0x10000000
+#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT                         28
+#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B1_STATUS :: b1_miss [27:27] */
+#define BCHP_BSPI_B1_STATUS_b1_miss_MASK                           0x08000000
+#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT                          27
+#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_hit [26:26] */
+#define BCHP_BSPI_B1_STATUS_b1_hit_MASK                            0x04000000
+#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT                           26
+#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B1_STATUS :: b1_address [25:00] */
+#define BCHP_BSPI_B1_STATUS_b1_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT                       0
+#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B1_CTRL - Prefetch Buffer 1 Control Register
+ ***************************************************************************/
+/* BSPI :: B1_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B1_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B1_CTRL :: b1_flush [00:00] */
+#define BCHP_BSPI_B1_CTRL_b1_flush_MASK                            0x00000001
+#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT                           0
+#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
+ ***************************************************************************/
+/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK               0xffffffe0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT              5
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK             0x00000010
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT            4
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT          0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK               0x00000008
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT              3
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT            0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK      0x00000004
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT     2
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT   0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK         0x00000002
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT        1
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT      0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK                0x00000001
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT               0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT             0x00000000
+
+/***************************************************************************
+ *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT                 1
+
+/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK      0x00000001
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT     0
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT   0x00000000
+
+/***************************************************************************
+ *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK                    0xfc000000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT                   26
+
+/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK               0x03000000
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK                    0x00fc0000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT                   18
+
+/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK              0x00030000
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK                    0x0000fc00
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT                   10
+
+/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK              0x00000300
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT             8
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK                    0x000000fc
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT                   2
+
+/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK              0x00000003
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT             0
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT           0x00000000
+
+/***************************************************************************
+ *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK                    0xfe000000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT                   25
+
+/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK               0x01000000
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK                    0x00fe0000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT                   17
+
+/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK              0x00010000
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK                    0x0000fe00
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT                   9
+
+/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK                     0x00000100
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT                    8
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT                  0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK                 0x000000ff
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT                0
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT              0x00000008
+
+/***************************************************************************
+ *CMD_AND_MODE_BYTE - Command and Mode Data Register
+ ***************************************************************************/
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK                 0xff000000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT                24
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK            0x00ff0000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT           16
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT         0x00000000
+
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK                 0x0000ff00
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT                8
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK             0x000000ff
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT            0
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT          0x0000000b
+
+/***************************************************************************
+ *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
+ ***************************************************************************/
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0x00000000
+
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK        0x00ffffff
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT       0
+
+/***************************************************************************
+ *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK               0xfff00000
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT              20
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT            0x00000000
+
+/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK                    0x000fffff
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT                  1
+
+/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK             0x00000001
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT            0
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT          0x00000000
+
+/***************************************************************************
+ *BSPI_PIO_MODE_ENABLE - BSPI Pin  Programmed IO Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK              0xfffffffe
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT             1
+
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK          0x00000001
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT         0
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT       0x00000000
+
+/***************************************************************************
+ *BSPI_PIO_IODIR - BSPI Pin  Programmed IO Mode Direction Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK                    0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT                   3
+
+/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT              0x00000003
+
+/***************************************************************************
+ *BSPI_PIO_DATA - BSPI Pin  Programmed IO Mode Data Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK                     0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT                    3
+
+/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT              0x00000000
+
+#endif /* #ifndef BCHP_BSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_bspi_raf.h b/include/linux/brcmstb/7425b0/bchp_bspi_raf.h
new file mode 100644
index 0000000..68b9df6
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_bspi_raf.h
@@ -0,0 +1,160 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:44 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_RAF_H__
+#define BCHP_BSPI_RAF_H__
+
+/***************************************************************************
+ *BSPI_RAF - Public Linear Read BSPI Pipe Registers
+ ***************************************************************************/
+#define BCHP_BSPI_RAF_START_ADDR                 0x0041c100 /* Physical Starting Address Location in Flash device */
+#define BCHP_BSPI_RAF_NUM_WORDS                  0x0041c104 /* Number of Words to be fetched */
+#define BCHP_BSPI_RAF_CTRL                       0x0041c108 /* RAF Session Control Register */
+#define BCHP_BSPI_RAF_FULLNESS                   0x0041c10c /* Fullness indicator for the read ahead buffer */
+#define BCHP_BSPI_RAF_WATERMARK                  0x0041c110 /* Watermark level in the read ahead buffer that triggers an interrupt */
+#define BCHP_BSPI_RAF_STATUS                     0x0041c114 /* Linear Read Status Register */
+#define BCHP_BSPI_RAF_READ_DATA                  0x0041c118 /* Read data from Raf-buffer */
+#define BCHP_BSPI_RAF_WORD_CNT                   0x0041c11c /* Current number of words fetched from Flash */
+#define BCHP_BSPI_RAF_CURR_ADDR                  0x0041c120 /* Current read address for the linear read session */
+
+/***************************************************************************
+ *START_ADDR - Physical Starting Address Location in Flash device
+ ***************************************************************************/
+/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK                   0xffffffff
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT                  0
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT                0x00000000
+
+/***************************************************************************
+ *NUM_WORDS - Number of Words to be fetched
+ ***************************************************************************/
+/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK                      0xffffffff
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT                     0
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *CTRL - RAF Session Control Register
+ ***************************************************************************/
+/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT                         2
+
+/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
+#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK                              0x00000002
+#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT                             1
+#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT                           0x00000000
+
+/* BSPI_RAF :: CTRL :: START [00:00] */
+#define BCHP_BSPI_RAF_CTRL_START_MASK                              0x00000001
+#define BCHP_BSPI_RAF_CTRL_START_SHIFT                             0
+#define BCHP_BSPI_RAF_CTRL_START_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *FULLNESS - Fullness indicator for the read ahead buffer
+ ***************************************************************************/
+/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK                      0xffffff80
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT                     7
+
+/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK                       0x0000007f
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT                      0
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
+ ***************************************************************************/
+/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK                     0xfffffffc
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT                    2
+
+/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK            0x00000003
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT           0
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STATUS - Linear Read Status Register
+ ***************************************************************************/
+/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
+#define BCHP_BSPI_RAF_STATUS_reserved0_MASK                        0xfffffff8
+#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT                       3
+
+/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK                        0x00000004
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT                       2
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT                     0x00000000
+
+/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK                       0x00000002
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT                      1
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT                    0x00000001
+
+/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK                     0x00000001
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT                    0
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *READ_DATA - Read data from Raf-buffer
+ ***************************************************************************/
+/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
+#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK                          0xffffffff
+#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT                         0
+#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *WORD_CNT - Current number of words fetched from Flash
+ ***************************************************************************/
+/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK             0xffffffff
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT            0
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *CURR_ADDR - Current read address for the linear read session
+ ***************************************************************************/
+/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK               0xffffffff
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT              0
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT            0x00000000
+
+#endif /* #ifndef BCHP_BSPI_RAF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_clkgen.h b/include/linux/brcmstb/7425b0/bchp_clkgen.h
new file mode 100644
index 0000000..7586b9b
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_clkgen.h
@@ -0,0 +1,7055 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:43 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_CLKGEN_H__
+#define BCHP_CLKGEN_H__
+
+/***************************************************************************
+ *CLKGEN - clkgen registers
+ ***************************************************************************/
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL         0x00430004 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV             0x00430008 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 0x0043000c /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN            0x00430010 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x00430014 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x00430018 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC            0x0043001c /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2           0x00430020 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS     0x00430024 /* Lock Status */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS          0x00430028 /* Test Status */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET           0x0043002c /* Resets */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN           0x00430030 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL         0x00430034 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV             0x00430038 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 0x0043003c /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 0x00430040 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 0x00430044 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 0x00430048 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN            0x00430050 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW 0x00430054 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH 0x00430058 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC            0x0043005c /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2           0x00430060 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS     0x00430064 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_STATUS          0x00430068 /* Test Status */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET          0x0043006c /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN          0x00430070 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL        0x00430074 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV            0x00430078 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC           0x0043007c /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 0x00430080 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 0x00430084 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 0x00430088 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN           0x0043008c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW 0x00430090 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH 0x00430094 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC           0x00430098 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS    0x0043009c /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS         0x004300a0 /* Test Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET         0x004300a4 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN         0x004300a8 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL       0x004300ac /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV           0x004300b0 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN          0x004300b4 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x004300b8 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x004300bc /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS   0x004300c0 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS        0x004300c4 /* Test Status */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET          0x004300c8 /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN          0x004300cc /* Powerdowns */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL        0x004300d0 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV            0x004300d4 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC           0x004300d8 /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 0x004300dc /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 0x004300e0 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 0x004300e4 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN           0x004300e8 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW 0x004300ec /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH 0x004300f0 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC           0x004300f4 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS    0x004300f8 /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS         0x004300fc /* Test Status */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET         0x00430100 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN         0x00430104 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL       0x00430108 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV           0x0043010c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN          0x00430110 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW 0x00430114 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH 0x00430118 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS   0x0043011c /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS        0x00430120 /* Test Status */
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET            0x00430124 /* Resets */
+#define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN            0x00430128 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL          0x0043012c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_HIF_PLL_DIV              0x00430130 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0 0x00430134 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1 0x00430138 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN             0x0043013c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC             0x00430140 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_HIF_PLL_LOCK_STATUS      0x00430144 /* Lock Status */
+#define BCHP_CLKGEN_PLL_HIF_PLL_STATUS           0x00430148 /* Test Status */
+#define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN           0x0043014c /* Cml buffer Tristate enable */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET           0x00430150 /* Resets */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN           0x00430154 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL         0x00430158 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV             0x0043015c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 0x00430160 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 0x00430164 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 0x00430168 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 0x0043016c /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 0x00430170 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 0x00430174 /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN            0x00430178 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW 0x0043017c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH 0x00430180 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC            0x00430184 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2           0x00430188 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS     0x0043018c /* Lock Status */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS          0x00430190 /* Test Status */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET          0x00430194 /* Resets */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN          0x00430198 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL        0x0043019c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV            0x004301a0 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 0x004301a4 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 0x004301a8 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN           0x004301ac /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW 0x004301b0 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH 0x004301b4 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC           0x004301b8 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2          0x004301bc /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS    0x004301c0 /* Lock Status */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS         0x004301c4 /* Test Status */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET        0x004301c8 /* Resets */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN        0x004301cc /* Powerdowns */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL      0x004301d0 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV          0x004301d4 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 0x004301d8 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 0x004301dc /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 0x004301e0 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN         0x004301e4 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW 0x004301e8 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH 0x004301ec /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC         0x004301f0 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2        0x004301f4 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS  0x004301f8 /* Lock Status */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS       0x004301fc /* Test Status */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_VEC_DACADC_CLOCK_DISABLE 0x00430200 /* Disable VEC_AIO_TOP_INST's vec_dacadc clocks */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL         0x00430204 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY 0x00430208 /* V3D_TOP inst power switch memory */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x0043020c /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x00430210 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x00430214 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x00430218 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x0043021c /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x00430220 /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN            0x00430224 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x00430228 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x0043022c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC            0x00430230 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2           0x00430234 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS     0x00430238 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS          0x0043023c /* Test Status */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET          0x00430240 /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN          0x00430244 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL        0x00430248 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV            0x0043024c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC           0x00430250 /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 0x00430254 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 0x00430258 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 0x0043025c /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN           0x00430260 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW 0x00430264 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH 0x00430268 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC           0x0043026c /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS    0x00430270 /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS         0x00430274 /* Test Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET             0x00430278 /* Resets */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN             0x0043027c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL           0x00430280 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV               0x00430284 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0 0x00430288 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN              0x0043028c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW 0x00430290 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH 0x00430294 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC              0x00430298 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS       0x0043029c /* Lock Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS            0x004302a0 /* Test Status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET         0x004302a4 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN         0x004302a8 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL       0x004302ac /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV           0x004302b0 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN          0x004302b4 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x004302b8 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x004302bc /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS   0x004302c0 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS        0x004302c4 /* Test Status */
+#define BCHP_CLKGEN_AVD1_TOP_INST_POWER_SWITCH_MEMORY 0x004302c8 /* Avd1 top inst power switch memory */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK  0x004302cc /* Uhfr top inst observe clock */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE   0x004302d0 /* Core xpt inst clock enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC 0x004302d4 /* Vec aio top inst clock enable vec */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE  0x004302dc /* Disable SYS_CTRL_INST's clocks */
+#define BCHP_CLKGEN_PAD_MUX_SELECT               0x004302e0 /* Mux selects for Pad clocks */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE    0x004302e4 /* Disable DVP_HT_INST's clocks */
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE 0x004302e8 /* Core xpt inst memory standby enable */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE  0x004302ec /* Disable ZCPU_TOP_INST's clocks */
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY 0x004302f0 /* Sys ctrl inst power switch memory */
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE 0x004302f4 /* Uhfr top inst memory standby enable */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE      0x004302f8 /* Disable USB0_INST's clocks */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE            0x004302fc /* Disable PAD's clocks */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT         0x00430300 /* Mux selects for Smartcard clocks */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE   0x00430304 /* Uhfr top inst clock enable */
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE 0x0043030c /* Hif inst memory standby enable */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE  0x00430310 /* Disable CORE_XPT_INST's clocks */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT          0x00430314 /* Mux selects for Internal clocks */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK  0x00430318 /* Moca top inst observe clock */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE 0x0043031c /* Graphics inst memory standby enable */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK  0x00430320 /* Sys ctrl inst observe clock */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE 0x00430324 /* Disable VEC_AIO_TOP_INST's clocks */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE  0x00430328 /* Disable UHFR_TOP_INST's clocks */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION        0x0043032c /* Select observation clk */
+#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE 0x00430330 /* Disable GRAPHICS_INST's m2mc clock */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE      0x00430334 /* Disable USB1_INST's clocks */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE 0x00430338 /* Disable DUAL_GENET_TOP_DUAL_RGMII_INST's clocks */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE       0x0043033c /* Hif inst clock disable */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE       0x00430340 /* Usb0 inst clock enable */
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE      0x00430344 /* Vice2 inst clock enable */
+#define BCHP_CLKGEN_SCRATCH0                     0x00430348 /* clkgen  Scratch register */
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE 0x0043034c /* Usb1 inst memory standby enable */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_B 0x00430350 /* Dual genet top dual rgmii inst power switch memory b */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE 0x00430354 /* Memsys 32 0 inst clock enable */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY 0x00430358 /* Memsys 32 1 inst power switch memory */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE   0x0043035c /* Svd0 top inst clock enable */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK      0x00430360 /* Usb0 inst observe clock */
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY 0x00430364 /* Core xpt inst power switch memory */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK 0x00430368 /* Vec aio top inst observe clock */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A 0x0043036c /* Dual genet top dual rgmii inst memory standby enable a */
+#define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY 0x00430370 /* Vice2 inst power switch memory */
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK    0x00430374 /* Dvp hr inst observe clock */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT  0x00430378 /* Sata3 top inst clock select */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY 0x0043037c /* Raaga dsp top inst power switch memory */
+#define BCHP_CLKGEN_AVD1_TOP_INST_MEMORY_STANDBY_ENABLE 0x00430380 /* Avd0 top inst memory standby enable */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK      0x00430384 /* Usb1 inst observe clock */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK 0x00430388 /* Memsys 32 1 inst observe clock */
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_MEMORY_STANDBY_ENABLE 0x0043038c /* BVN_MCVP_TOP inst memory standby enable */
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY 0x00430390 /* Moca top inst power switch memory */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK 0x00430394 /* Memsys 32 0 inst observe clock */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE 0x00430398 /* Raaga dsp top inst memory standby enable */
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE 0x0043039c /* BVN_MCVP_TOP inst clock enable */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY 0x004303a0 /* Memsys 32 0 inst power switch memory */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE 0x004303a4 /* Memsys 32 0 inst memory standby enable */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE 0x004303a8 /* Memsys 32 1 inst clock enable */
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE 0x004303ac /* Sata3 top inst memory standby enable */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK  0x004303b0 /* Zcpu top inst observe clock */
+#define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE 0x004303b4 /* V3D_TOP inst memory standby enable */
+#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY 0x004303b8 /* Dvp hr inst power switch memory */
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY 0x004303bc /* Usb1 inst power switch memory */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK 0x004303c0 /* Dual genet top dual rgmii inst observe clock */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE     0x004303c4 /* Dvp ht inst clock enable */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE   0x004303c8 /* Graphics inst clock enable */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK  0x004303cc /* Graphics inst observe clock */
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY 0x004303d0 /* Bvn top inst power switch memory */
+#define BCHP_CLKGEN_TESTPORT                     0x004303d4 /* Special Testport Controls */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION   0x004303d8 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION  0x004303dc /* Select observation clk */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL       0x004303e0 /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO 0x004303e4 /* Vec aio top inst clock enable aio */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE 0x004303e8 /* Vec aio top inst clock enable */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK    0x004303ec /* Sectop inst observe clock */
+#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE   0x004303f0 /* Avd0 top inst clock enable */
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE 0x004303f4 /* Dvp ht inst memory standby enable */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE  0x004303f8 /* Sata3 top inst clock enable */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE    0x004303fc /* Bvn top inst clock enable */
+#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK  0x00430400 /* Avd0 top inst observe clock */
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY 0x00430404 /* Usb0 inst power switch memory */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY 0x00430408 /* Graphics inst power switch memory */
+#define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE 0x0043040c /* Vice2 inst memory standby enable */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK  0x00430410 /* Core xpt inst observe clock */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO 0x00430414 /* Vec aio top inst memory standby enable aio */
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE 0x00430418 /* Sys ctrl inst memory standby enable */
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY 0x0043041c /* Hif inst power switch memory */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE 0x00430420 /* Memsys 32 1 inst memory standby enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO 0x00430424 /* Vec aio top inst power switch memory aio */
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK       0x00430428 /* Hif inst observe clock */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE    0x0043042c /* V3D_TOP inst clock enable */
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE 0x00430430 /* Moca top inst memory standby enable */
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY 0x00430434 /* Svd0 top inst power switch memory */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT 0x00430438 /* Dual genet top dual rgmii inst clock select */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_MEMORY_STANDBY_ENABLE 0x0043043c /* Zcpu top inst memory standby enable */
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY 0x00430440 /* Uhfr top inst power switch memory */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC 0x00430444 /* Vec aio top inst power switch memory vec */
+#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE 0x00430448 /* Dvp hr inst memory standby enable */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK 0x0043044c /* Sata3 top inst observe clock */
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE 0x00430450 /* Usb0 inst memory standby enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC 0x00430454 /* Vec aio top inst memory standby enable vec */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE     0x00430458 /* Dvp hr inst clock enable */
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY 0x0043045c /* Dvp ht inst power switch memory */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE 0x00430460 /* Dual genet top dual rgmii inst clock enable */
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY 0x00430464 /* Sata3 top inst power switch memory */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE   0x00430468 /* Moca top inst clock enable */
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_POWER_SWITCH_MEMORY 0x0043046c /* BVN_MCVP_TOP inst power switch memory */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK   0x00430470 /* Sys aon inst observe clock */
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE 0x00430474 /* Bvn top inst memory standby enable */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION       0x00430478 /* Select observation clk */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE       0x0043047c /* Usb1 inst clock enable */
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE 0x00430480 /* Svd0 top inst memory standby enable */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A 0x00430484 /* Dual genet top dual rgmii inst power switch memory a */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK    0x00430488 /* Dvp ht inst observe clock */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA 0x0043048c /* Sectop inst clock enable */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE 0x00430490 /* Sectop inst memory standby enable */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE   0x00430494 /* Zcpu top inst clock enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE 0x00430498 /* Raaga dsp top inst clock enable */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS    0x0043049c /* Resets status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS  0x004304a0 /* Resets status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS  0x004304a4 /* Resets status */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS  0x004304a8 /* Resets status */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS    0x004304ac /* Resets status */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS   0x004304b0 /* Resets status */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS    0x004304b4 /* Resets status */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS   0x004304b8 /* Resets status */
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS     0x004304bc /* Resets status */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS   0x004304c0 /* Resets status */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS 0x004304c4 /* Resets status */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS   0x004304c8 /* Resets status */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS      0x004304cc /* Resets status */
+#define BCHP_CLKGEN_MEMSYS_0_32_POWER_MANAGEMENT 0x004304d0 /* Memsys_0 32 power management */
+#define BCHP_CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT 0x004304d4 /* Memsys_1 32 power management */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x004304d8 /* pll alive in standby mode */
+#define BCHP_CLKGEN_SPI_CLOCK_SELECT             0x004304dc /* spi clock control */
+#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS      0x004304e0 /* Lock Status */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL                0x004304e4 /* Mips PLL Control Register */
+#define BCHP_CLKGEN_SCRATCH1                     0x004304e8 /* clkgen  Scratch register */
+#define BCHP_CLKGEN_V3D_TOP_INST_V3D_CLOCK_ENABLE 0x004304ec /* V3d_top inst V3D clock enable */
+#define BCHP_CLKGEN_SCRATCH2                     0x004304f4 /* clkgen  Scratch register */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1 0x004304f8 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE     0x00430504 /* Disable SATA3_TOP_INST's clocks */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK 0x00430508 /* Raaga Dsp top inst observe clock */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL        0x0043050c /* Clock Monitor Control */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT      0x00430510 /* Clock Monitor Max Reference Count */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER    0x00430514 /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE       0x00430518 /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER   0x0043051c /* Clock Monitor View Counter */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP           0x00430520 /* Power management LDO PLL */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM        0x00430524 /* Power management LDO PLL state machine */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS 0x00430528 /* Bypass GENET_TOP_DUAL_RGMII_INST's cl;ocks */
+
+/***************************************************************************
+ *PLL_MIPS_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_MIPS_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_SHIFT               3
+
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_MASK                     0x00000007
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_SHIFT                    0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_DEFAULT                  0x00000003
+
+/***************************************************************************
+ *PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:06] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 6
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000007
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000002
+
+/***************************************************************************
+ *PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: LDO_REF_SEL [30:30] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_MASK             0x40000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT            30
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: POR_BYPASS [29:29] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_MASK              0x20000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_SHIFT             29
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: NDIV_RELOCK [28:28] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_MASK             0x10000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT            28
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: FAST_LOCK [27:27] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_MASK               0x08000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_SHIFT              27
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: VCO_DLY [25:24] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_MASK                 0x03000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_SHIFT                24
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: PWM_RATE [23:22] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_MASK                0x00c00000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_SHIFT               22
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_MODE [21:20] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_MASK               0x00300000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_SHIFT              20
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_MASK                0x00080000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_SHIFT               19
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_MASK             0x00020000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_SHIFT            17
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_MASK             0x0001c000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_SHIFT            14
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__MASK             0x00002000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__SHIFT            13
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_MASK             0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT            1
+
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_AVD1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_AVD1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_RESETD_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_RESETA_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_AVD1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AVD1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_AVD1_PLL_DIV :: NDIV_INT [12:03] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_NDIV_INT_MASK                 0x00001ff8
+#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_NDIV_INT_SHIFT                3
+#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_NDIV_INT_DEFAULT              0x000000a4
+
+/* CLKGEN :: PLL_AVD1_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_PDIV_MASK                     0x00000007
+#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_PDIV_SHIFT                    0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_PDIV_DEFAULT                  0x00000003
+
+/***************************************************************************
+ *PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  6
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  6
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  6
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [13:06] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  6
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [05:05] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 5
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [04:04] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 4
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [03:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_AVD1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_AVD1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AVD1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000007
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000002
+
+/***************************************************************************
+ *PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: LDO_REF_SEL [30:30] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_LDO_REF_SEL_MASK             0x40000000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_LDO_REF_SEL_SHIFT            30
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_LDO_REF_SEL_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: POR_BYPASS [29:29] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_POR_BYPASS_MASK              0x20000000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_POR_BYPASS_SHIFT             29
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_POR_BYPASS_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: NDIV_RELOCK [28:28] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_NDIV_RELOCK_MASK             0x10000000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_NDIV_RELOCK_SHIFT            28
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: FAST_LOCK [27:27] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_FAST_LOCK_MASK               0x08000000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_FAST_LOCK_SHIFT              27
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCODIV2_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: VCO_DLY [25:24] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCO_DLY_MASK                 0x03000000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCO_DLY_SHIFT                24
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: PWM_RATE [23:22] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_PWM_RATE_MASK                0x00c00000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_PWM_RATE_SHIFT               22
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_PWM_RATE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: STAT_MODE [21:20] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_MODE_MASK               0x00300000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_MODE_SHIFT              20
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_AUX_CTRL_MASK                0x00080000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_AUX_CTRL_SHIFT               19
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_UPDATE_MASK             0x00020000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_UPDATE_SHIFT            17
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_SELECT_MASK             0x0001c000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_SELECT_SHIFT            14
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_RESET__MASK             0x00002000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_RESET__SHIFT            13
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2_SPARE_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_AVD1_PLL_LOCK_STATUS :: LOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_LOCK_MASK             0x00000002
+#define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_LOCK_SHIFT            1
+
+/* CLKGEN :: PLL_AVD1_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       0
+
+/***************************************************************************
+ *PLL_AVD1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_AVD1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_AVD1_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_reserved0_MASK             0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_reserved0_SHIFT            2
+
+/* CLKGEN :: PLL_VCXO2_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_MASK                0x00000002
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_SHIFT               1
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_VCXO2_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN_PWRDN_PLL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN_PWRDN_PLL_SHIFT            0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN_PWRDN_PLL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_VCXO2_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL_REF_SEL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL_REF_SEL_SHIFT            0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL_REF_SEL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_reserved0_MASK               0xffffe000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_reserved0_SHIFT              13
+
+/* CLKGEN :: PLL_VCXO2_PLL_DIV :: NDIV_INT [12:03] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_MASK                0x00001ff8
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_SHIFT               3
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_DEFAULT             0x00000040
+
+/* CLKGEN :: PLL_VCXO2_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_MASK                    0x00000007
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_SHIFT                   0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_DEFAULT                 0x00000002
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_reserved0_MASK              0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_reserved0_SHIFT             20
+
+/* CLKGEN :: PLL_VCXO2_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_MASK           0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_SHIFT          0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x00003fc0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 6
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x00003fc0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 6
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x00003fc0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 6
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000004b
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_reserved0_MASK              0xff000000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_reserved0_SHIFT             24
+
+/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x00000007
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000001
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_reserved0_MASK              0xc0000000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_reserved0_SHIFT             30
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: MDIV_RELOCK [29:29] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_MDIV_RELOCK_MASK            0x20000000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_MDIV_RELOCK_SHIFT           29
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_MDIV_RELOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: FAST_LOCK [28:28] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_MASK              0x10000000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_SHIFT             28
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCODIV2 [27:27] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_MASK                0x08000000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_SHIFT               27
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCO_DLY [26:25] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DLY_MASK                0x06000000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DLY_SHIFT               25
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DLY_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: PWM_RATE [24:23] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_MASK               0x01800000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_SHIFT              23
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_MASK              0x00600000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_SHIFT             21
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCODIV2_POST [20:20] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_POST_MASK           0x00100000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_POST_SHIFT          20
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_POST_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_MASK               0x00080000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_SHIFT              19
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REFCLKOUT_MASK              0x00040000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REFCLKOUT_SHIFT             18
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REFCLKOUT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_MASK            0x00020000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_SHIFT           17
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_MASK            0x0001c000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_SHIFT           14
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET__MASK            0x00002000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET__SHIFT           13
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET__DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_reserved0_SHIFT      1
+
+/* CLKGEN :: PLL_VCXO2_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_SHIFT           0
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_reserved0_MASK            0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_reserved0_SHIFT           12
+
+/* CLKGEN :: PLL_VCXO2_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_TEST_STATUS_SHIFT         0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT                0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_reserved0_MASK             0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_reserved0_SHIFT            2
+
+/* CLKGEN :: PLL_VCXO1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_MASK                0x00000002
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_SHIFT               1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_VCXO1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_PWRDN_PLL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_PWRDN_PLL_SHIFT            0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_PWRDN_PLL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_VCXO1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_REF_SEL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_REF_SEL_SHIFT            0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_REF_SEL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_reserved0_MASK               0xffffe000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_reserved0_SHIFT              13
+
+/* CLKGEN :: PLL_VCXO1_PLL_DIV :: NDIV_INT [12:03] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_MASK                0x00001ff8
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_SHIFT               3
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_DEFAULT             0x00000040
+
+/* CLKGEN :: PLL_VCXO1_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_MASK                    0x00000007
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_SHIFT                   0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_DEFAULT                 0x00000002
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_reserved0_MASK              0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_reserved0_SHIFT             20
+
+/* CLKGEN :: PLL_VCXO1_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_MASK           0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_SHIFT          0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x00003fc0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 6
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x00003fc0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 6
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x00003fc0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 6
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000004b
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_reserved0_MASK              0xff000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_reserved0_SHIFT             24
+
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x00000007
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000001
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_reserved0_MASK              0xc0000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_reserved0_SHIFT             30
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: MDIV_RELOCK [29:29] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_MDIV_RELOCK_MASK            0x20000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_MDIV_RELOCK_SHIFT           29
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_MDIV_RELOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: FAST_LOCK [28:28] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_MASK              0x10000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_SHIFT             28
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCODIV2 [27:27] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_MASK                0x08000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_SHIFT               27
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_DLY [26:25] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DLY_MASK                0x06000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DLY_SHIFT               25
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DLY_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: PWM_RATE [24:23] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_MASK               0x01800000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_SHIFT              23
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_MASK              0x00600000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_SHIFT             21
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCODIV2_POST [20:20] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_POST_MASK           0x00100000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_POST_SHIFT          20
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_POST_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_MASK               0x00080000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_SHIFT              19
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REFCLKOUT_MASK              0x00040000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REFCLKOUT_SHIFT             18
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REFCLKOUT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_MASK            0x00020000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_SHIFT           17
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_MASK            0x0001c000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_SHIFT           14
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET__MASK            0x00002000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET__SHIFT           13
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET__DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_reserved0_SHIFT      1
+
+/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_SHIFT           0
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_reserved0_MASK            0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_reserved0_SHIFT           12
+
+/* CLKGEN :: PLL_VCXO1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_TEST_STATUS_SHIFT         0
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO2_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETD_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AUDIO2_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO2_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN_PWRDN_PLL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO2_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL_REF_SEL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO2_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_PDIV_DEFAULT                0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO2_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO2_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_HIF_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_reserved0_MASK               0xfffffffc
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_reserved0_SHIFT              2
+
+/* CLKGEN :: PLL_HIF_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETD_MASK                  0x00000002
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETD_SHIFT                 1
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETD_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETA_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETA_SHIFT                 0
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETA_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_HIF_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_HIF_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN_PWRDN_PLL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN_PWRDN_PLL_SHIFT              0
+#define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN_PWRDN_PLL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_HIF_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_HIF_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL_REF_SEL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL_REF_SEL_SHIFT              0
+#define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL_REF_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_HIF_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_DIV :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_reserved0_MASK                 0xfffff800
+#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_reserved0_SHIFT                11
+
+/* CLKGEN :: PLL_HIF_PLL_DIV :: NDIV_INT [10:03] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_NDIV_INT_MASK                  0x000007f8
+#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_NDIV_INT_SHIFT                 3
+#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_NDIV_INT_DEFAULT               0x00000032
+
+/* CLKGEN :: PLL_HIF_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_PDIV_MASK                      0x00000007
+#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_PDIV_SHIFT                     0
+#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_PDIV_DEFAULT                   0x00000001
+
+/***************************************************************************
+ *PLL_HIF_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:15] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xffff8000
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  15
+
+/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: CML_CLOCK_EN_CH0 [14:14] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CML_CLOCK_EN_CH0_MASK 0x00004000
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CML_CLOCK_EN_CH0_SHIFT 14
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CML_CLOCK_EN_CH0_DEFAULT 0x00000001
+
+/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x00003fc0
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   6
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000001b
+
+/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_HIF_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:15] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK   0xffff8000
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT  15
+
+/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_1 :: CML_CLOCK_EN_CH1 [14:14] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_CML_CLOCK_EN_CH1_MASK 0x00004000
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_CML_CLOCK_EN_CH1_SHIFT 14
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_CML_CLOCK_EN_CH1_DEFAULT 0x00000001
+
+/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK    0x00003fc0
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT   6
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000067
+
+/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_HIF_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_GAIN :: reserved0 [31:10] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_reserved0_MASK                0xfffffc00
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_reserved0_SHIFT               10
+
+/* CLKGEN :: PLL_HIF_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_HIF_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003
+
+/* CLKGEN :: PLL_HIF_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x00000007
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       0
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     0x00000003
+
+/***************************************************************************
+ *PLL_HIF_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_MISC :: reserved0 [31:28] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_reserved0_MASK                0xf0000000
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_reserved0_SHIFT               28
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: DIGITAL_LDO_CONTROL [27:26] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DIGITAL_LDO_CONTROL_MASK      0x0c000000
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DIGITAL_LDO_CONTROL_SHIFT     26
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DIGITAL_LDO_CONTROL_DEFAULT   0x00000001
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: ANALOG_LDO_CONTROL [25:24] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_ANALOG_LDO_CONTROL_MASK       0x03000000
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_ANALOG_LDO_CONTROL_SHIFT      24
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_ANALOG_LDO_CONTROL_DEFAULT    0x00000001
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: LDO_CONTROL [23:22] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_LDO_CONTROL_MASK              0x00c00000
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_LDO_CONTROL_SHIFT             22
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_LDO_CONTROL_DEFAULT           0x00000001
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: HYST_EN [21:21] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_HYST_EN_MASK                  0x00200000
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_HYST_EN_SHIFT                 21
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_HYST_EN_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: VCODIV2 [20:20] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_VCODIV2_MASK                  0x00100000
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_VCODIV2_SHIFT                 20
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_VCODIV2_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_AUX_CTRL_MASK                 0x00080000
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_AUX_CTRL_SHIFT                19
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_AUX_CTRL_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_REFCLKOUT_MASK                0x00040000
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_REFCLKOUT_SHIFT               18
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_REFCLKOUT_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_UPDATE_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_UPDATE_SHIFT             17
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_UPDATE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_SELECT_MASK              0x0001c000
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_SELECT_SHIFT             14
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_SELECT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_RESET__MASK              0x00002000
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_RESET__SHIFT             13
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_RESET__DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00001000
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  12
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         0
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_HIF_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_PLL_HIF_PLL_LOCK_STATUS_reserved0_SHIFT        1
+
+/* CLKGEN :: PLL_HIF_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_HIF_PLL_LOCK_STATUS_LOCK_SHIFT             0
+
+/***************************************************************************
+ *PLL_HIF_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_STATUS_reserved0_MASK              0xfffff000
+#define BCHP_CLKGEN_PLL_HIF_PLL_STATUS_reserved0_SHIFT             12
+
+/* CLKGEN :: PLL_HIF_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
+#define BCHP_CLKGEN_PLL_HIF_PLL_STATUS_TEST_STATUS_SHIFT           0
+
+/***************************************************************************
+ *PLL_HIF_PLL_TRI_EN - Cml buffer Tristate enable
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_TRI_EN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_HIF_PLL_TRI_EN :: TRI_EN [00:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN_TRI_EN_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN_TRI_EN_SHIFT                0
+#define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN_TRI_EN_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MOCA_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_MOCA_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: NDIV_INT [12:03] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_MASK                 0x00001ff8
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_SHIFT                3
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_DEFAULT              0x000000c8
+
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_MASK                     0x00000007
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_SHIFT                    0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_DEFAULT                  0x00000003
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  6
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  6
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000c
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  6
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000024
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [13:06] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  6
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000048
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [05:05] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 5
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [04:04] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 4
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [03:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [13:06] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  6
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000024
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [05:05] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 5
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [04:04] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 4
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [03:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [13:06] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  6
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000048
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [05:05] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 5
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [04:04] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 4
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [03:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000007
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000002
+
+/***************************************************************************
+ *PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: LDO_REF_SEL [30:30] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_MASK             0x40000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_SHIFT            30
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: POR_BYPASS [29:29] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_MASK              0x20000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_SHIFT             29
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: NDIV_RELOCK [28:28] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_MASK             0x10000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_SHIFT            28
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: FAST_LOCK [27:27] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_MASK               0x08000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_SHIFT              27
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_DEFAULT              0x00000001
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_DLY [25:24] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_MASK                 0x03000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_SHIFT                24
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: PWM_RATE [23:22] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_MASK                0x00c00000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_SHIFT               22
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_DEFAULT             0x00000002
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_MODE [21:20] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_MASK               0x00300000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_SHIFT              20
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_MASK                0x00080000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_SHIFT               19
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_MASK             0x00020000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_SHIFT            17
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_MASK             0x0001c000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_SHIFT            14
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__MASK             0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__SHIFT            13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_MASK             0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_SHIFT            1
+
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_MOCA_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_MASK             0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_SHIFT            2
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_MASK                0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_SHIFT               1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_SHIFT               0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_RAAGA_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_SHIFT            0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_RAAGA_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_SHIFT            0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_MASK               0xffffe000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_SHIFT              13
+
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: NDIV_INT [12:03] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_MASK                0x00001ff8
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_SHIFT               3
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_DEFAULT             0x0000008f
+
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_MASK                    0x00000007
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_SHIFT                   0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_DEFAULT                 0x00000002
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x00003fc0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 6
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000000b
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x00003fc0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 6
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_MASK              0xff000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_SHIFT             24
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x00000007
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000002
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_reserved0_MASK              0x80000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_reserved0_SHIFT             31
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: LDO_REF_SEL [30:30] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_MASK            0x40000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_SHIFT           30
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: POR_BYPASS [29:29] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_MASK             0x20000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_SHIFT            29
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: NDIV_RELOCK [28:28] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_MASK            0x10000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_SHIFT           28
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: FAST_LOCK [27:27] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_MASK              0x08000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_SHIFT             27
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_MASK                0x04000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_SHIFT               26
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_DEFAULT             0x00000001
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_DLY [25:24] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_MASK                0x03000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_SHIFT               24
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PWM_RATE [23:22] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_MASK               0x00c00000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_SHIFT              22
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_DEFAULT            0x00000002
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_MODE [21:20] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_MASK              0x00300000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_SHIFT             20
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_MASK               0x00080000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_SHIFT              19
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_MASK              0x00040000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_SHIFT             18
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_MASK            0x00020000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_SHIFT           17
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_MASK            0x0001c000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_SHIFT           14
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__MASK            0x00002000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__SHIFT           13
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00000fff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_SHIFT                0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_MASK            0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_SHIFT           1
+
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_MASK       0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT      0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_MASK            0xfffff000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_SHIFT           12
+
+/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_SHIFT         0
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_reserved0_MASK           0xfffffffc
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_reserved0_SHIFT          2
+
+/* CLKGEN :: PLL_NETWORK_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETD_MASK              0x00000002
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETD_SHIFT             1
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETD_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETA_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETA_SHIFT             0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETA_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_NETWORK_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN_PWRDN_PLL_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN_PWRDN_PLL_SHIFT          0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN_PWRDN_PLL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL_reserved0_SHIFT        1
+
+/* CLKGEN :: PLL_NETWORK_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL_REF_SEL_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL_REF_SEL_SHIFT          0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL_REF_SEL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_reserved0_MASK             0xffffe000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_reserved0_SHIFT            13
+
+/* CLKGEN :: PLL_NETWORK_PLL_DIV :: NDIV_INT [12:03] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_NDIV_INT_MASK              0x00001ff8
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_NDIV_INT_SHIFT             3
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_NDIV_INT_DEFAULT           0x0000007d
+
+/* CLKGEN :: PLL_NETWORK_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_PDIV_MASK                  0x00000007
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_PDIV_SHIFT                 0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_PDIV_DEFAULT               0x00000003
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x00003fc0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 6
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x00003fc0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 6
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000012
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x00003fc0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 6
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000005a
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_reserved0_MASK            0xff000000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_reserved0_SHIFT           24
+
+/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK    0x00000007
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT   0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000002
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_reserved0_MASK            0x80000000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_reserved0_SHIFT           31
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: LDO_REF_SEL [30:30] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_LDO_REF_SEL_MASK          0x40000000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_LDO_REF_SEL_SHIFT         30
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_LDO_REF_SEL_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: POR_BYPASS [29:29] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_POR_BYPASS_MASK           0x20000000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_POR_BYPASS_SHIFT          29
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_POR_BYPASS_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: NDIV_RELOCK [28:28] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_NDIV_RELOCK_MASK          0x10000000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_NDIV_RELOCK_SHIFT         28
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_NDIV_RELOCK_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: FAST_LOCK [27:27] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_FAST_LOCK_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_FAST_LOCK_SHIFT           27
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_FAST_LOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCODIV2_MASK              0x04000000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCODIV2_SHIFT             26
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCODIV2_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: VCO_DLY [25:24] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_DLY_MASK              0x03000000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_DLY_SHIFT             24
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_DLY_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: PWM_RATE [23:22] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PWM_RATE_MASK             0x00c00000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PWM_RATE_SHIFT            22
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PWM_RATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_MODE [21:20] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_MODE_MASK            0x00300000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_MODE_SHIFT           20
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_MODE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_AUX_CTRL_MASK             0x00080000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_AUX_CTRL_SHIFT            19
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_AUX_CTRL_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_REFCLKOUT_MASK            0x00040000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_REFCLKOUT_SHIFT           18
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_REFCLKOUT_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_UPDATE_MASK          0x00020000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_UPDATE_SHIFT         17
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_UPDATE_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_SELECT_MASK          0x0001c000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_SELECT_SHIFT         14
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_SELECT_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_RESET__MASK          0x00002000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_RESET__SHIFT         13
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_RESET__DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_MASK      0x00000fff
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_SHIFT     0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT   0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_SPARE_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_SPARE_SHIFT              0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_SPARE_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_NETWORK_PLL_LOCK_STATUS :: LOCK [01:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_MASK          0x00000002
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_SHIFT         1
+
+/* CLKGEN :: PLL_NETWORK_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_LOST_MASK     0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_LOST_SHIFT    0
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_reserved0_MASK          0xfffff000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_reserved0_SHIFT         12
+
+/* CLKGEN :: PLL_NETWORK_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_TEST_STATUS_MASK        0x00000fff
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_TEST_STATUS_SHIFT       0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_VEC_DACADC_CLOCK_DISABLE - Disable VEC_AIO_TOP_INST's vec_dacadc clocks
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_VEC_DACADC_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_VEC_DACADC_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_VEC_DACADC_CLOCK_DISABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_VEC_DACADC_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_VEC_DACADC_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_VEC_DACADC_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_VEC_DACADC_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *V3D_TOP_INST_POWER_SWITCH_MEMORY - V3D_TOP inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: V3D_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: V3D_TOP_INST_POWER_SWITCH_MEMORY :: V3D_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY_V3D_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY_V3D_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY_V3D_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:06] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 6
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  6
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000a
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  6
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000000a
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [13:06] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  6
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000e
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [13:06] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  6
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000051
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [13:06] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  6
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x0000000c
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x0000000a
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000007
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000003
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [30:30] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK             0x40000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT            30
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [29:29] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK              0x20000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT             29
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [28:28] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK             0x10000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT            28
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [27:27] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK               0x08000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT              27
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT              0x00000001
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [25:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK                 0x03000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT                24
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [23:22] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK                0x00c00000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT               22
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT             0x00000002
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [21:20] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK               0x00300000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT              20
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK                0x00080000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT               19
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK             0x00020000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT            17
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK             0x0001c000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT            14
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK             0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT            13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK             0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT            1
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_reserved0_MASK             0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_reserved0_SHIFT            2
+
+/* CLKGEN :: PLL_VCXO0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_MASK                0x00000002
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_SHIFT               1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_VCXO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_PWRDN_PLL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_PWRDN_PLL_SHIFT            0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_PWRDN_PLL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_VCXO0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_REF_SEL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_REF_SEL_SHIFT            0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_REF_SEL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_reserved0_MASK               0xffffe000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_reserved0_SHIFT              13
+
+/* CLKGEN :: PLL_VCXO0_PLL_DIV :: NDIV_INT [12:03] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_MASK                0x00001ff8
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_SHIFT               3
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_DEFAULT             0x00000040
+
+/* CLKGEN :: PLL_VCXO0_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_MASK                    0x00000007
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_SHIFT                   0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_DEFAULT                 0x00000002
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_reserved0_MASK              0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_reserved0_SHIFT             20
+
+/* CLKGEN :: PLL_VCXO0_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_MASK           0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_SHIFT          0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x00003fc0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 6
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x00003fc0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 6
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x00003fc0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 6
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000004b
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_reserved0_MASK              0xff000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_reserved0_SHIFT             24
+
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x00000007
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000001
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_reserved0_MASK              0xc0000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_reserved0_SHIFT             30
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: MDIV_RELOCK [29:29] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_MDIV_RELOCK_MASK            0x20000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_MDIV_RELOCK_SHIFT           29
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_MDIV_RELOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: FAST_LOCK [28:28] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_MASK              0x10000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_SHIFT             28
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCODIV2 [27:27] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_MASK                0x08000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_SHIFT               27
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_DLY [26:25] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DLY_MASK                0x06000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DLY_SHIFT               25
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DLY_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: PWM_RATE [24:23] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_MASK               0x01800000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_SHIFT              23
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_MASK              0x00600000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_SHIFT             21
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCODIV2_POST [20:20] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_POST_MASK           0x00100000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_POST_SHIFT          20
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_POST_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_MASK               0x00080000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_SHIFT              19
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REFCLKOUT_MASK              0x00040000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REFCLKOUT_SHIFT             18
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REFCLKOUT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_MASK            0x00020000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_SHIFT           17
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_MASK            0x0001c000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_SHIFT           14
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET__MASK            0x00002000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET__SHIFT           13
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET__DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_reserved0_SHIFT      1
+
+/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_SHIFT           0
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_reserved0_MASK            0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_reserved0_SHIFT           12
+
+/* CLKGEN :: PLL_VCXO0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_TEST_STATUS_SHIFT         0
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_SHIFT               2
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_MASK                   0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_SHIFT                  1
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_DEFAULT                0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_DEFAULT                0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_SHIFT               1
+
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_MASK                  0xffffe000
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_SHIFT                 13
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: NDIV_INT [12:03] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_MASK                   0x00001ff8
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_SHIFT                  3
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_DEFAULT                0x00000040
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_MASK                       0x00000007
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_SHIFT                      0
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_DEFAULT                    0x00000001
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK     0x00003fc0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT    6
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT  0x00000030
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_MASK                 0xff000000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_SHIFT                24
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK         0x00000007
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT        0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT      0x00000001
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK  0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_MASK                 0xc0000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_SHIFT                30
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: MDIV_RELOCK [29:29] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_MASK               0x20000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_SHIFT              29
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: FAST_LOCK [28:28] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_SHIFT                28
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2 [27:27] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_MASK                   0x08000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_SHIFT                  27
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_DEFAULT                0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCO_DLY [26:25] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_MASK                   0x06000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_SHIFT                  25
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_DEFAULT                0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: PWM_RATE [24:23] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_MASK                  0x01800000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_SHIFT                 23
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_MASK                 0x00600000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_SHIFT                21
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2_POST [20:20] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_MASK              0x00100000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_SHIFT             20
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_MASK                  0x00080000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_SHIFT                 19
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_MASK                 0x00040000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_SHIFT                18
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_MASK               0x00020000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_SHIFT              17
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_MASK               0x0001c000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_SHIFT              14
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__MASK               0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__SHIFT              13
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK    0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT   12
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_SHIFT          0
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_SHIFT              0
+
+/***************************************************************************
+ *PLL_SC_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_MASK               0xfffff000
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_SHIFT              12
+
+/* CLKGEN :: PLL_SC_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_MASK             0x00000fff
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_SHIFT            0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT                0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *AVD1_TOP_INST_POWER_SWITCH_MEMORY - Avd1 top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: AVD1_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_AVD1_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_AVD1_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: AVD1_TOP_INST_POWER_SWITCH_MEMORY :: AVD1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_AVD1_TOP_INST_POWER_SWITCH_MEMORY_AVD1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_AVD1_TOP_INST_POWER_SWITCH_MEMORY_AVD1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_AVD1_TOP_INST_POWER_SWITCH_MEMORY_AVD1_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UHFR_TOP_INST_OBSERVE_CLOCK - Uhfr top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_INST_CLOCK_ENABLE - Core xpt inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_SHIFT     2
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC - Vec aio top inst clock enable vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_SHIFT 6
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_AIO_CLK_324_ENABLE_VEC [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_AIO_CLK_324_ENABLE_VEC_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_AIO_CLK_324_ENABLE_VEC_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_AIO_CLK_324_ENABLE_VEC_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_SCB_CLOCK_ENABLE_VEC [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_QDAC_216_CLOCK_ENABLE_VEC [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_SHIFT 3
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_ALTERNATE_216_CLOCK_ENABLE_VEC [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_216_CLOCK_ENABLE_VEC [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_108_CLOCK_ENABLE_VEC [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SYS_CTRL_INST_CLOCK_DISABLE - Disable SYS_CTRL_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffff0
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_SHIFT    4
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [03:03] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK [02:02] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_MUX_SELECT - Mux selects for Pad clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK                  0xfffffff0
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT                 4
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_VCXO27_CLOCK [03:02] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_MASK    0x0000000c
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_SHIFT   2
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_OBSERVE_PLL_CLOCK [01:01] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_OBSERVE_PLL_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_OBSERVE_PLL_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_OBSERVE_PLL_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_MASK     0x00000001
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_SHIFT    0
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_DEFAULT  0x00000000
+
+/***************************************************************************
+ *DVP_HT_INST_CLOCK_DISABLE - Disable DVP_HT_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_INST_MEMORY_STANDBY_ENABLE - Core xpt inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: CORE_XPT_INST_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ZCPU_TOP_INST_CLOCK_DISABLE - Disable ZCPU_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1
+
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_DISABLE :: DISABLE_ZMIPS_FUNC_BYP_CLOCK [00:00] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_FUNC_BYP_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_FUNC_BYP_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_FUNC_BYP_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_INST_POWER_SWITCH_MEMORY - Sys ctrl inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SYS_CTRL_INST_POWER_SWITCH_MEMORY :: SYS_CTRL_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UHFR_TOP_INST_MEMORY_STANDBY_ENABLE - Uhfr top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: UHFR_TOP_INST_MEMORY_STANDBY_ENABLE :: UHFR_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB0_INST_CLOCK_DISABLE - Disable USB0_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_reserved0_SHIFT        2
+
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: DISABLE_USB0_54_FREERUN_CLOCK [01:01] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_FREERUN_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_FREERUN_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_FREERUN_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: DISABLE_USB0_54_MDIO_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLOCK_DISABLE - Disable PAD's clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK               0xffffffe0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT              5
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_SC_CLOCK [04:04] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_VCXO27_CLOCK [03:03] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_OBSERVE_PLL_CLOCK [02:02] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_OBSERVE_PLL_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_OBSERVE_PLL_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_OBSERVE_PLL_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
+ ***************************************************************************/
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:11] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK            0xfffff800
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT           11
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC_OUT_CLOCK [10:08] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_MASK         0x00000700
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_SHIFT        8
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_DEFAULT      0x00000000
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [07:05] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK            0x000000e0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT           5
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [04:02] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK            0x0000001c
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT           2
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: PLLSC_REFERENCE_CLOCK [01:00] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_MASK 0x00000003
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UHFR_TOP_INST_CLOCK_ENABLE - Uhfr top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE :: UHFR_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *HIF_INST_MEMORY_STANDBY_ENABLE - Hif inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: HIF_INST_MEMORY_STANDBY_ENABLE :: HIF_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_INST_CLOCK_DISABLE - Disable CORE_XPT_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_MASK     0xffffffe0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_SHIFT    5
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
+ ***************************************************************************/
+/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:10] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK             0xfffffc00
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT            10
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: VECAIO_ITU656_1_CLOCK [09:08] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_VECAIO_ITU656_1_CLOCK_MASK 0x00000300
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_VECAIO_ITU656_1_CLOCK_SHIFT 8
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_VECAIO_ITU656_1_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: VECAIO_ITU656_0_CLOCK [07:06] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_VECAIO_ITU656_0_CLOCK_MASK 0x000000c0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_VECAIO_ITU656_0_CLOCK_SHIFT 6
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_VECAIO_ITU656_0_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO2_REFERENCE_CLOCK [05:04] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_MASK 0x00000030
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [03:02] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x0000000c
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [01:00] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000003
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MOCA_TOP_INST_OBSERVE_CLOCK - Moca top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_INST_MEMORY_STANDBY_ENABLE - Graphics inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE :: GFX_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_INST_OBSERVE_CLOCK - Sys ctrl inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_DISABLE - Disable VEC_AIO_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_MASK  0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_ITU656_1_CLOCK [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_1_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_1_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_1_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_ITU656_0_CLOCK [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UHFR_TOP_INST_CLOCK_DISABLE - Disable UHFR_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1
+
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE :: DISABLE_UHFR_ALWAYSON_CLOCK [00:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLK27_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_MASK           0xfffffe00
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_SHIFT          9
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_MASK  0x00000100
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_MASK  0x000000fe
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK  0x00000001
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_INST_M2MC_CLOCK_ENABLE - Disable GRAPHICS_INST's m2mc clock
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_M2MC_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_M2MC_CLOCK_ENABLE :: GFX_M2MC_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *USB1_INST_CLOCK_DISABLE - Disable USB1_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_reserved0_SHIFT        2
+
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: DISABLE_USB1_54_FREERUN_CLOCK [01:01] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_FREERUN_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_FREERUN_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_FREERUN_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: DISABLE_USB1_54_MDIO_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE - Disable DUAL_GENET_TOP_DUAL_RGMII_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_reserved0_SHIFT 5
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET_ALWAYSON_CLOCK [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_PM_CLOCK [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_INST_CLOCK_DISABLE - Hif inst clock disable
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_SHIFT         5
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CARD_CLOCK [04:04] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: HIF_PAD_BT_CLOCK_DISABLE [03:03] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_HIF_PAD_BT_CLOCK_DISABLE_MASK 0x00000008
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_HIF_PAD_BT_CLOCK_DISABLE_SHIFT 3
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_HIF_PAD_BT_CLOCK_DISABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_EBI_CLOCK [02:02] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [01:01] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CLOCK [00:00] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB0_INST_CLOCK_ENABLE - Usb0 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: USB_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: USB_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VICE2_INST_CLOCK_ENABLE - Vice2 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: VICE2_INST_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_reserved0_MASK         0xfffffff0
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_reserved0_SHIFT        4
+
+/* CLKGEN :: VICE2_INST_CLOCK_ENABLE :: VICE_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VICE2_INST_CLOCK_ENABLE :: VICE_GISB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_GISB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_GISB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VICE2_INST_CLOCK_ENABLE :: VICE_CORE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_CORE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_CORE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VICE2_INST_CLOCK_ENABLE :: VICE_BVB_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_BVB_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_BVB_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_BVB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SCRATCH0 - clkgen  Scratch register
+ ***************************************************************************/
+/* CLKGEN :: SCRATCH0 :: VALUE [31:00] */
+#define BCHP_CLKGEN_SCRATCH0_VALUE_MASK                            0xffffffff
+#define BCHP_CLKGEN_SCRATCH0_VALUE_SHIFT                           0
+#define BCHP_CLKGEN_SCRATCH0_VALUE_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *USB1_INST_MEMORY_STANDBY_ENABLE - Usb1 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: USB1_INST_MEMORY_STANDBY_ENABLE :: USB1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_B - Dual genet top dual rgmii inst power switch memory b
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_B :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_B_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_B_reserved0_SHIFT 2
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_B :: GENET1_POWER_SWITCH_MEMORY_B [01:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_B_GENET1_POWER_SWITCH_MEMORY_B_MASK 0x00000003
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_B_GENET1_POWER_SWITCH_MEMORY_B_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_B_GENET1_POWER_SWITCH_MEMORY_B_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_32_0_INST_CLOCK_ENABLE - Memsys 32 0 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_reserved0_SHIFT  2
+
+/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: DDR0_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: DDR0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *MEMSYS_32_1_INST_POWER_SWITCH_MEMORY - Memsys 32 1 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_1_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: MEMSYS_32_1_INST_POWER_SWITCH_MEMORY :: DDR1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SVD0_TOP_INST_CLOCK_ENABLE - Svd0 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffff0
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     4
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD0_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD0_CPU_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CPU_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CPU_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CPU_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD0_CORE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CORE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CORE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *USB0_INST_OBSERVE_CLOCK - Usb0 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_INST_POWER_SWITCH_MEMORY - Core xpt inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: CORE_XPT_INST_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_OBSERVE_CLOCK - Vec aio top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A - Dual genet top dual rgmii inst memory standby enable a
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 2
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: GENET1_MEMORY_STANDBY_ENABLE_A [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET1_MEMORY_STANDBY_ENABLE_A_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET1_MEMORY_STANDBY_ENABLE_A_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET1_MEMORY_STANDBY_ENABLE_A_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: GENET0_MEMORY_STANDBY_ENABLE_A [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VICE2_INST_POWER_SWITCH_MEMORY - Vice2 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: VICE2_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY_reserved0_MASK  0xfffffffc
+#define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: VICE2_INST_POWER_SWITCH_MEMORY :: VICE_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY_VICE_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY_VICE_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY_VICE_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HR_INST_OBSERVE_CLOCK - Dvp hr inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_INST_CLOCK_SELECT - Sata3 top inst clock select
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_SHIFT    1
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: SATA3_REF_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY - Raaga dsp top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY :: RAAGA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AVD1_TOP_INST_MEMORY_STANDBY_ENABLE - Avd0 top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: AVD1_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_AVD1_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_AVD1_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: AVD1_TOP_INST_MEMORY_STANDBY_ENABLE :: AVD1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_AVD1_TOP_INST_MEMORY_STANDBY_ENABLE_AVD1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_AVD1_TOP_INST_MEMORY_STANDBY_ENABLE_AVD1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_AVD1_TOP_INST_MEMORY_STANDBY_ENABLE_AVD1_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB1_INST_OBSERVE_CLOCK - Usb1 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_32_1_INST_OBSERVE_CLOCK - Memsys 32 1 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: DDR1_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: DDR1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: DDR1_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BVN_MCVP_TOP_INST_MEMORY_STANDBY_ENABLE - BVN_MCVP_TOP inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_MCVP_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: BVN_MCVP_TOP_INST_MEMORY_STANDBY_ENABLE :: BVN_MCVP_TOP_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MCVP_TOP_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MCVP_TOP_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MCVP_TOP_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MOCA_TOP_INST_POWER_SWITCH_MEMORY - Moca top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: MOCA_TOP_INST_POWER_SWITCH_MEMORY :: MOCA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_32_0_INST_OBSERVE_CLOCK - Memsys 32 0 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: DDR0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: DDR0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: DDR0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE - Raaga dsp top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE :: RAAGA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BVN_MCVP_TOP_INST_CLOCK_ENABLE - BVN_MCVP_TOP inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_MCVP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE_reserved0_MASK  0xfffffff8
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3
+
+/* CLKGEN :: BVN_MCVP_TOP_INST_CLOCK_ENABLE :: BVND_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BVN_MCVP_TOP_INST_CLOCK_ENABLE :: BVND_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE_BVND_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE_BVND_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE_BVND_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BVN_MCVP_TOP_INST_CLOCK_ENABLE :: BVND_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *MEMSYS_32_0_INST_POWER_SWITCH_MEMORY - Memsys 32 0 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_0_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: MEMSYS_32_0_INST_POWER_SWITCH_MEMORY :: DDR0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY_DDR0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY_DDR0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY_DDR0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE - Memsys 32 0 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE :: DDR0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE_DDR0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE_DDR0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE_DDR0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_32_1_INST_CLOCK_ENABLE - Memsys 32 1 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_reserved0_SHIFT  2
+
+/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE :: DDR1_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE :: DDR1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SATA3_TOP_INST_MEMORY_STANDBY_ENABLE - Sata3 top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SATA3_TOP_INST_MEMORY_STANDBY_ENABLE :: SATA3_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ZCPU_TOP_INST_OBSERVE_CLOCK - Zcpu top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *V3D_TOP_INST_MEMORY_STANDBY_ENABLE - V3D_TOP inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: V3D_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: V3D_TOP_INST_MEMORY_STANDBY_ENABLE :: V3D_TOP_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE_V3D_TOP_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE_V3D_TOP_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE_V3D_TOP_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HR_INST_POWER_SWITCH_MEMORY - Dvp hr inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: DVP_HR_INST_POWER_SWITCH_MEMORY :: DVPHR_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_DVPHR_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_DVPHR_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_DVPHR_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB1_INST_POWER_SWITCH_MEMORY - Usb1 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: USB1_INST_POWER_SWITCH_MEMORY :: USB1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK - Dual genet top dual rgmii inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_INST_CLOCK_ENABLE - Dvp ht inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_MASK        0xffffffc0
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_SHIFT       6
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_CLK_VEC_ENABLE [05:05] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_VEC_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_VEC_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_VEC_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_CLK_MAX_ENABLE [04:04] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_MAX_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_MAX_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_MAX_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_ALTERNATE_216_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_ALTERNATE_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE - Graphics inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_MASK      0xffffffe0
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_SHIFT     5
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_SCB_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_ALTERNATE_216_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_ALTERNATE_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GRAPHICS_INST_OBSERVE_CLOCK - Graphics inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BVN_TOP_INST_POWER_SWITCH_MEMORY - Bvn top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: BVN_TOP_INST_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TESTPORT - Special Testport Controls
+ ***************************************************************************/
+/* CLKGEN :: TESTPORT :: reserved0 [31:04] */
+#define BCHP_CLKGEN_TESTPORT_reserved0_MASK                        0xfffffff0
+#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT                       4
+
+/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [03:00] */
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK           0x0000000f
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT          0
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PAD_CODEC_MCLK_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_MASK      0xfffffe00
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_SHIFT     9
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_OBSERVE_PLL_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_OBSERVE_PLL_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_reserved0_MASK     0xfffffe00
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_reserved0_SHIFT    9
+
+/* CLKGEN :: PAD_OBSERVE_PLL_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_OBSERVE_PLL_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_OBSERVE_PLL_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PM_CLOCK_216_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_SHIFT         1
+
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_MASK   0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT  0
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO - Vec aio top inst clock enable aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: reserved0 [31:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_SHIFT 3
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE - Vec aio top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_AIO_ALTERNATE_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AVD1_TOP_INST_CLOCK_ENABLE - Avd0 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: AVD1_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffff0
+#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     4
+
+/* CLKGEN :: AVD1_TOP_INST_CLOCK_ENABLE :: AVD1_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD1_TOP_INST_CLOCK_ENABLE :: AVD1_CPU_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_CPU_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_CPU_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_CPU_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD1_TOP_INST_CLOCK_ENABLE :: AVD1_CORE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_CORE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_CORE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD1_TOP_INST_CLOCK_ENABLE :: AVD1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DVP_HT_INST_MEMORY_STANDBY_ENABLE - Dvp ht inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: DVP_HT_INST_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_INST_CLOCK_ENABLE - Sata3 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT    2
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *BVN_TOP_INST_CLOCK_ENABLE - Bvn top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffff8
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      3
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *AVD1_TOP_INST_OBSERVE_CLOCK - Avd0 top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: AVD1_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: AVD1_TOP_INST_OBSERVE_CLOCK :: AVD1_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: AVD1_TOP_INST_OBSERVE_CLOCK :: AVD1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: AVD1_TOP_INST_OBSERVE_CLOCK :: AVD1_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK_AVD1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK_AVD1_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK_AVD1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB0_INST_POWER_SWITCH_MEMORY - Usb0 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: USB0_INST_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_INST_POWER_SWITCH_MEMORY - Graphics inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY :: GFX_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VICE2_INST_MEMORY_STANDBY_ENABLE - Vice2 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: VICE2_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: VICE2_INST_MEMORY_STANDBY_ENABLE :: VICE_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE_VICE_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE_VICE_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE_VICE_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_INST_OBSERVE_CLOCK - Core xpt inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO - Vec aio top inst memory standby enable aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO :: AIO_MEMORY_STANDBY_ENABLE_AIO [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_INST_MEMORY_STANDBY_ENABLE - Sys ctrl inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SYS_CTRL_INST_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_INST_POWER_SWITCH_MEMORY - Hif inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: HIF_INST_POWER_SWITCH_MEMORY :: HIF_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE - Memsys 32 1 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE :: DDR1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO - Vec aio top inst power switch memory aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO :: AIO_POWER_SWITCH_MEMORY_AIO [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_INST_OBSERVE_CLOCK - Hif inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *V3D_TOP_INST_CLOCK_ENABLE - V3D_TOP inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      2
+
+/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *MOCA_TOP_INST_MEMORY_STANDBY_ENABLE - Moca top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MOCA_TOP_INST_MEMORY_STANDBY_ENABLE :: MOCA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SVD0_TOP_INST_POWER_SWITCH_MEMORY - Svd0 top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SVD0_TOP_INST_POWER_SWITCH_MEMORY :: SVD0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT - Dual genet top dual rgmii inst clock select
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: reserved0 [31:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_reserved0_SHIFT 4
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: GENET1_GMII_CLOCK_SELECT [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: GENET1_CLOCK_SELECT [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: GENET0_GMII_CLOCK_SELECT [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: GENET0_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ZCPU_TOP_INST_MEMORY_STANDBY_ENABLE - Zcpu top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_ZCPU_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: ZCPU_TOP_INST_MEMORY_STANDBY_ENABLE :: ZMIPS_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_MEMORY_STANDBY_ENABLE_ZMIPS_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_ZCPU_TOP_INST_MEMORY_STANDBY_ENABLE_ZMIPS_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_MEMORY_STANDBY_ENABLE_ZMIPS_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UHFR_TOP_INST_POWER_SWITCH_MEMORY - Uhfr top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: UHFR_TOP_INST_POWER_SWITCH_MEMORY :: UHFR_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC - Vec aio top inst power switch memory vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC :: VEC_POWER_SWITCH_MEMORY_VEC [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HR_INST_MEMORY_STANDBY_ENABLE - Dvp hr inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: DVP_HR_INST_MEMORY_STANDBY_ENABLE :: DVPHR_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_DVPHR_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_DVPHR_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_DVPHR_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_INST_OBSERVE_CLOCK - Sata3 top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_MASK    0xffffffc0
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT   6
+
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB0_INST_MEMORY_STANDBY_ENABLE - Usb0 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: USB0_INST_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC - Vec aio top inst memory standby enable vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC :: VEC_MEMORY_STANDBY_ENABLE_VEC [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HR_INST_CLOCK_ENABLE - Dvp hr inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_reserved0_MASK        0xffffffe0
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_reserved0_SHIFT       5
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_CLK_324_ENABLE [04:04] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_CLK_324_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_CLK_324_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_CLK_324_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_ALTERNATE_216_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_ALTERNATE_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DVP_HT_INST_POWER_SWITCH_MEMORY - Dvp ht inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: DVP_HT_INST_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE - Dual genet top dual rgmii inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: reserved0 [31:16] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_reserved0_SHIFT 16
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [15:15] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00008000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 15
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET_108_CLOCK_ENABLE [14:14] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_MASK 0x00004000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_SHIFT 14
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE [13:13] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE [12:12] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00001000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_L2INTR_CLOCK_ENABLE [11:11] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_MASK 0x00000800
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_SHIFT 11
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_HFB_CLOCK_ENABLE [10:10] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_MASK 0x00000400
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_SHIFT 10
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_GMII_CLOCK_ENABLE [09:09] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_MASK 0x00000200
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_SHIFT 9
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_EEE_CLOCK_ENABLE [08:08] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_MASK 0x00000100
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_SHIFT 8
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_CLK_250_CLOCK_ENABLE [07:07] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_MASK 0x00000080
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_SHIFT 7
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_L2INTR_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_HFB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_GMII_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_EEE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_CLK_250_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SATA3_TOP_INST_POWER_SWITCH_MEMORY - Sata3 top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SATA3_TOP_INST_POWER_SWITCH_MEMORY :: SATA3_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MOCA_TOP_INST_CLOCK_ENABLE - Moca top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     2
+
+/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: MOCA_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: MOCA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *BVN_MCVP_TOP_INST_POWER_SWITCH_MEMORY - BVN_MCVP_TOP inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BVN_MCVP_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: BVN_MCVP_TOP_INST_POWER_SWITCH_MEMORY :: BVN_MCVP_TOP_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_POWER_SWITCH_MEMORY_BVN_MCVP_TOP_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_POWER_SWITCH_MEMORY_BVN_MCVP_TOP_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_POWER_SWITCH_MEMORY_BVN_MCVP_TOP_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_AON_INST_OBSERVE_CLOCK - Sys aon inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BVN_TOP_INST_MEMORY_STANDBY_ENABLE - Bvn top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: BVN_TOP_INST_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_VCXO27_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_MASK          0xfffffe00
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_SHIFT         9
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB1_INST_CLOCK_ENABLE - Usb1 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: USB1_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: USB1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SVD0_TOP_INST_MEMORY_STANDBY_ENABLE - Svd0 top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SVD0_TOP_INST_MEMORY_STANDBY_ENABLE :: SVD0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A - Dual genet top dual rgmii inst power switch memory a
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A :: GENET0_POWER_SWITCH_MEMORY_A [01:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_MASK 0x00000003
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_INST_OBSERVE_CLOCK - Dvp ht inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SECTOP_INST_CLOCK_ENABLE_M2MDMA - Sectop inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_reserved0_SHIFT 1
+
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA :: M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SECTOP_INST_MEMORY_STANDBY_ENABLE - Sectop inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SECTOP_INST_MEMORY_STANDBY_ENABLE :: SEC_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *ZCPU_TOP_INST_CLOCK_ENABLE - Zcpu top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE :: ZMIPS_SCB_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_CLOCK_ENABLE - Raaga dsp top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_DSP_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PLL_MIPS_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETD_MASK          0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETD_SHIFT         1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETD_DEFAULT       0x00000001
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETA_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETA_SHIFT         0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETA_DEFAULT       0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETD_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETD_SHIFT       1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETD_DEFAULT     0x00000001
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETA_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETA_SHIFT       0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETA_DEFAULT     0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETD_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETD_SHIFT       1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETD_DEFAULT     0x00000001
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETA_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETA_SHIFT       0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETA_DEFAULT     0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO2_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_RESETD_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_RESETD_SHIFT       1
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_RESETD_DEFAULT     0x00000001
+
+/* CLKGEN :: PLL_AUDIO2_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_RESETA_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_RESETA_SHIFT       0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_RESETA_DEFAULT     0x00000001
+
+/***************************************************************************
+ *PLL_AVD1_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_AVD1_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS_RESETD_MASK          0x00000002
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS_RESETD_SHIFT         1
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS_RESETD_DEFAULT       0x00000001
+
+/* CLKGEN :: PLL_AVD1_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS_RESETA_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS_RESETA_SHIFT         0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS_RESETA_DEFAULT       0x00000001
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_reserved0_SHIFT     2
+
+/* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_RESETD_MASK         0x00000002
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_RESETD_SHIFT        1
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_RESETD_DEFAULT      0x00000001
+
+/* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_RESETA_MASK         0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_RESETA_SHIFT        0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_RESETA_DEFAULT      0x00000001
+
+/***************************************************************************
+ *PLL_MOCA_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETD_MASK          0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETD_SHIFT         1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETD_DEFAULT       0x00000001
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETA_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETA_SHIFT         0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETA_DEFAULT       0x00000001
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_reserved0_SHIFT     2
+
+/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_RESETD_MASK         0x00000002
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_RESETD_SHIFT        1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_RESETD_DEFAULT      0x00000001
+
+/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_RESETA_MASK         0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_RESETA_SHIFT        0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_RESETA_DEFAULT      0x00000001
+
+/***************************************************************************
+ *PLL_HIF_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_HIF_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_RESETD_MASK           0x00000002
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_RESETD_SHIFT          1
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_RESETD_DEFAULT        0x00000001
+
+/* CLKGEN :: PLL_HIF_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_RESETA_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_RESETA_SHIFT          0
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_RESETA_DEFAULT        0x00000001
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_SHIFT     2
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETD_MASK         0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETD_SHIFT        1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETD_DEFAULT      0x00000001
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETA_MASK         0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETA_SHIFT        0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETA_DEFAULT      0x00000001
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_reserved0_SHIFT   2
+
+/* CLKGEN :: PLL_NETWORK_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_RESETD_MASK       0x00000002
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_RESETD_SHIFT      1
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_RESETD_DEFAULT    0x00000001
+
+/* CLKGEN :: PLL_NETWORK_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_RESETA_MASK       0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_RESETA_SHIFT      0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_RESETA_DEFAULT    0x00000001
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_reserved0_SHIFT     2
+
+/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_RESETD_MASK         0x00000002
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_RESETD_SHIFT        1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_RESETD_DEFAULT      0x00000001
+
+/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_RESETA_MASK         0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_RESETA_SHIFT        0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_RESETA_DEFAULT      0x00000001
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETD_MASK            0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETD_SHIFT           1
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETD_DEFAULT         0x00000001
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETA_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETA_SHIFT           0
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETA_DEFAULT         0x00000001
+
+/***************************************************************************
+ *MEMSYS_0_32_POWER_MANAGEMENT - Memsys_0 32 power management
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_0_32_POWER_MANAGEMENT :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_0_32_POWER_MANAGEMENT_reserved0_MASK    0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_0_32_POWER_MANAGEMENT_reserved0_SHIFT   1
+
+/* CLKGEN :: MEMSYS_0_32_POWER_MANAGEMENT :: MEMSYS_PLL_PWRDN_POWER_MANAGEMENT [00:00] */
+#define BCHP_CLKGEN_MEMSYS_0_32_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_0_32_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_0_32_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_1_32_POWER_MANAGEMENT - Memsys_1 32 power management
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_1_32_POWER_MANAGEMENT :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT_reserved0_MASK    0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT_reserved0_SHIFT   1
+
+/* CLKGEN :: MEMSYS_1_32_POWER_MANAGEMENT :: MEMSYS_PLL_PWRDN_POWER_MANAGEMENT [00:00] */
+#define BCHP_CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PM_PLL_ALIVE_SEL - pll alive in standby mode
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xfffffff0
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               4
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_DDR1 [03:03] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR1_MASK                 0x00000008
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR1_SHIFT                3
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR1_DEFAULT              0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_DDR0 [02:02] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR0_MASK                 0x00000004
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR0_SHIFT                2
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR0_DEFAULT              0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_MIPS [01:01] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_MASK                 0x00000002
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_SHIFT                1
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_DEFAULT              0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [00:00] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK                 0x00000001
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT                0
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT              0x00000000
+
+/***************************************************************************
+ *SPI_CLOCK_SELECT - spi clock control
+ ***************************************************************************/
+/* CLKGEN :: SPI_CLOCK_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_SPI_CLOCK_SELECT_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_SPI_CLOCK_SELECT_reserved0_SHIFT               3
+
+/* CLKGEN :: SPI_CLOCK_SELECT :: SPI_CLOCK_FREQ_SEL [02:01] */
+#define BCHP_CLKGEN_SPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_MASK       0x00000006
+#define BCHP_CLKGEN_SPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_SHIFT      1
+#define BCHP_CLKGEN_SPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_DEFAULT    0x00000000
+
+/* CLKGEN :: SPI_CLOCK_SELECT :: SPI_CLOCK_OVERRIDE_STRAP [00:00] */
+#define BCHP_CLKGEN_SPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_MASK 0x00000001
+#define BCHP_CLKGEN_SPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_SHIFT 0
+#define BCHP_CLKGEN_SPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_DDR_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_DDR_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_DDR_PLL_LOCK_STATUS :: DDR1_LOCK [01:01] */
+#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_DDR1_LOCK_MASK         0x00000002
+#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_DDR1_LOCK_SHIFT        1
+
+/* CLKGEN :: PLL_DDR_PLL_LOCK_STATUS :: DDR0_LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_DDR0_LOCK_MASK         0x00000001
+#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_DDR0_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_MIPS_CTRL - Mips PLL Control Register
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_CTRL :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_reserved0_MASK                   0x80000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_reserved0_SHIFT                  31
+
+/* CLKGEN :: PLL_MIPS_CTRL :: BYPASS_PLL_RQ [30:30] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_RQ_MASK               0x40000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_RQ_SHIFT              30
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_RQ_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_MIPS_CTRL :: BYPASS_PLL_STATE [29:29] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_MASK            0x20000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_SHIFT           29
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_DEFAULT         0x00000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_normal_PLL_mode 0
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_bypassed_PLL_mode 1
+
+/* union - case normal_PLL_mode [28:23] */
+/* CLKGEN :: PLL_MIPS_CTRL :: normal_PLL_mode :: A_RST_PLL [28:28] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_A_RST_PLL_MASK   0x10000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_A_RST_PLL_SHIFT  28
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_A_RST_PLL_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_CTRL :: normal_PLL_mode :: D_RST_PLL [27:27] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_D_RST_PLL_MASK   0x08000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_D_RST_PLL_SHIFT  27
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_D_RST_PLL_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_CTRL :: normal_PLL_mode :: CPU_FREQ [26:24] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_CPU_FREQ_MASK    0x07000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_CPU_FREQ_SHIFT   24
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_CPU_FREQ_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_CTRL :: normal_PLL_mode :: OVERRIDE_CPU_FREQ_PIN_STRAP [23:23] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_SHIFT 23
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_DEFAULT 0x00000000
+
+/* union - case bypassed_PLL_mode [28:23] */
+/* CLKGEN :: PLL_MIPS_CTRL :: bypassed_PLL_mode :: A_RST_PLL [28:28] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_A_RST_PLL_MASK 0x10000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_A_RST_PLL_SHIFT 28
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_A_RST_PLL_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_CTRL :: bypassed_PLL_mode :: D_RST_PLL [27:27] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_D_RST_PLL_MASK 0x08000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_D_RST_PLL_SHIFT 27
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_D_RST_PLL_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_CTRL :: bypassed_PLL_mode :: CPU_FREQ [26:24] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_CPU_FREQ_MASK  0x07000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_CPU_FREQ_SHIFT 24
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_CPU_FREQ_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_CTRL :: bypassed_PLL_mode :: OVERRIDE_CPU_FREQ_PIN_STRAP [23:23] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_SHIFT 23
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_CTRL :: reserved1 [22:00] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_reserved1_MASK                   0x007fffff
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_reserved1_SHIFT                  0
+
+/***************************************************************************
+ *SCRATCH1 - clkgen  Scratch register
+ ***************************************************************************/
+/* CLKGEN :: SCRATCH1 :: VALUE [31:00] */
+#define BCHP_CLKGEN_SCRATCH1_VALUE_MASK                            0xffffffff
+#define BCHP_CLKGEN_SCRATCH1_VALUE_SHIFT                           0
+#define BCHP_CLKGEN_SCRATCH1_VALUE_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *V3D_TOP_INST_V3D_CLOCK_ENABLE - V3d_top inst V3D clock enable
+ ***************************************************************************/
+/* CLKGEN :: V3D_TOP_INST_V3D_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_V3D_TOP_INST_V3D_CLOCK_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_V3D_TOP_INST_V3D_CLOCK_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: V3D_TOP_INST_V3D_CLOCK_ENABLE :: V3D_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_V3D_TOP_INST_V3D_CLOCK_ENABLE_V3D_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_V3D_TOP_INST_V3D_CLOCK_ENABLE_V3D_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_V3D_TOP_INST_V3D_CLOCK_ENABLE_V3D_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SCRATCH2 - clkgen  Scratch register
+ ***************************************************************************/
+/* CLKGEN :: SCRATCH2 :: VALUE [31:00] */
+#define BCHP_CLKGEN_SCRATCH2_VALUE_MASK                            0xffffffff
+#define BCHP_CLKGEN_SCRATCH2_VALUE_SHIFT                           0
+#define BCHP_CLKGEN_SCRATCH2_VALUE_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK     0x00003fc0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT    6
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT  0x00000030
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_INST_CLOCK_DISABLE - Disable SATA3_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: SATA3_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_reserved0_SHIFT       1
+
+/* CLKGEN :: SATA3_INST_CLOCK_DISABLE :: DISABLE_27_FUNC_CLK_30 [00:00] */
+#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_DISABLE_27_FUNC_CLK_30_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_DISABLE_27_FUNC_CLK_30_SHIFT 0
+#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_DISABLE_27_FUNC_CLK_30_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_OBSERVE_CLOCK - Raaga Dsp top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CLOCK_MONITOR_CONTROL - Clock Monitor Control
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT          4
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK   0x00000008
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT  3
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK    0x00000004
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT   2
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK      0x00000002
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT     1
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT   0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK  0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT         1
+
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK     0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT    0
+
+/***************************************************************************
+ *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *PM_PLL_LDO_POWERUP - Power management LDO PLL
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_MASK              0xfffffff0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_SHIFT             4
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_MOCA [03:03] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_MASK     0x00000008
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_SHIFT    3
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_DEFAULT  0x00000001
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_RAAGA [02:02] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_MASK    0x00000004
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_SHIFT   2
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_DEFAULT 0x00000001
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_NETWORK [01:01] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_NETWORK_MASK  0x00000002
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_NETWORK_SHIFT 1
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_NETWORK_DEFAULT 0x00000001
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AVD [00:00] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_MASK      0x00000001
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_SHIFT     0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_DEFAULT   0x00000001
+
+/***************************************************************************
+ *PM_PLL_LDO_POWERUP_SM - Power management LDO PLL state machine
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: reserved0 [31:27] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_MASK           0xf8000000
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_SHIFT          27
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_POWERUP_WAIT_TIME [26:14] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_MASK 0x07ffc000
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_SHIFT 14
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_DEFAULT 0x00001518
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_CLK_STOP_WAIT_TIME [13:01] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_MASK 0x00003ffe
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_SHIFT 1
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_DEFAULT 0x000000c8
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: GISB_OVERRIDE_SM [00:00] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_MASK    0x00000001
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_SHIFT   0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS - Bypass GENET_TOP_DUAL_RGMII_INST's cl;ocks
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_reserved0_SHIFT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS :: EEE_25_CLOCK_BYPASS [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_CLKGEN_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_common.h b/include/linux/brcmstb/7425b0/bchp_common.h
new file mode 100644
index 0000000..dbbdad8
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_common.h
@@ -0,0 +1,3096 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:28 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_COMMON_H__
+#define BCHP_COMMON_H__
+
+/***************************************************************************
+ *BCM7425_B0
+ ***************************************************************************/
+#define BCHP_PHYSICAL_OFFSET                               0x10000000
+#define BCHP_REGISTER_START                                0x00000000 /* DECODE_RBNODE_REGS_1 is first */
+#define BCHP_REGISTER_END                                  0x00fffd98 /* MOCA_HOSTMISC is last */
+#define BCHP_REGISTER_SIZE                                 0x003fff66 /* Number of registers */
+
+/****************************************************************************
+ * Core instance register start address.
+ ***************************************************************************/
+#define BCHP_DECODE_RBNODE_REGS_1_REG_START                0x00000000
+#define BCHP_DECODE_RBNODE_REGS_1_REG_END                  0x0000007c
+#define BCHP_DECODE_MAIN_1_REG_START                       0x00000100
+#define BCHP_DECODE_MAIN_1_REG_END                         0x000001fc
+#define BCHP_SDRAM_DEBUG_1_REG_START                       0x00000200
+#define BCHP_SDRAM_DEBUG_1_REG_END                         0x0000027c
+#define BCHP_DECODE_MCOM_1_REG_START                       0x00000300
+#define BCHP_DECODE_MCOM_1_REG_END                         0x0000031c
+#define BCHP_DECODE_SPRE_1_REG_START                       0x00000320
+#define BCHP_DECODE_SPRE_1_REG_END                         0x0000033c
+#define BCHP_DECODE_WPRD_1_REG_START                       0x00000340
+#define BCHP_DECODE_WPRD_1_REG_END                         0x0000035c
+#define BCHP_DECODE_DQNT_1_REG_START                       0x00000400
+#define BCHP_DECODE_DQNT_1_REG_END                         0x0000045c
+#define BCHP_DECODE_DQNT_8X8_1_REG_START                   0x00000500
+#define BCHP_DECODE_DQNT_8X8_1_REG_END                     0x0000057c
+#define BCHP_DECODE_VP8_XFRM_1_REG_START                   0x00000600
+#define BCHP_DECODE_VP8_XFRM_1_REG_END                     0x0000060c
+#define BCHP_DECODE_XFRM_1_REG_START                       0x00000700
+#define BCHP_DECODE_XFRM_1_REG_END                         0x0000071c
+#define BCHP_DECODE_DBLK_1_REG_START                       0x00000720
+#define BCHP_DECODE_DBLK_1_REG_END                         0x0000073c
+#define BCHP_DECODE_MB_1_REG_START                         0x00000740
+#define BCHP_DECODE_MB_1_REG_END                           0x0000075c
+#define BCHP_REG_CABAC2BINS_1_REG_START                    0x00000b00
+#define BCHP_REG_CABAC2BINS_1_REG_END                      0x00000bfc
+#define BCHP_DECODE_SINT_1_REG_START                       0x00000c00
+#define BCHP_DECODE_SINT_1_REG_END                         0x00000dfc
+#define BCHP_DECODE_RVC_1_REG_START                        0x00000e00
+#define BCHP_DECODE_RVC_1_REG_END                          0x00000efc
+#define BCHP_DECODE_CPUREGS_1_REG_START                    0x00000f00
+#define BCHP_DECODE_CPUREGS_1_REG_END                      0x00000f7c
+#define BCHP_DECODE_CPUREGS2_1_REG_START                   0x00000f80
+#define BCHP_DECODE_CPUREGS2_1_REG_END                     0x00000ffc
+#define BCHP_DECODE_CPUDMA_1_REG_START                     0x00001800
+#define BCHP_DECODE_CPUDMA_1_REG_END                       0x000018fc
+#define BCHP_DECODE_DMAMEM_1_REG_START                     0x00001a00
+#define BCHP_DECODE_DMAMEM_1_REG_END                       0x000021fc
+#define BCHP_REG_CABAC2BINS2_1_REG_START                   0x00002400
+#define BCHP_REG_CABAC2BINS2_1_REG_END                     0x000027fc
+#define BCHP_DECODE_WPTBL_1_REG_START                      0x00003000
+#define BCHP_DECODE_WPTBL_1_REG_END                        0x000031fc
+#define BCHP_DECODE_SINT_OLOOP_1_REG_START                 0x0000cc00
+#define BCHP_DECODE_SINT_OLOOP_1_REG_END                   0x0000ccfc
+#define BCHP_DECODE_SD_1_REG_START                         0x00040800
+#define BCHP_DECODE_SD_1_REG_END                           0x00040ffc
+#define BCHP_DECODE_IND_SDRAM_REGS_1_REG_START             0x00041000
+#define BCHP_DECODE_IND_SDRAM_REGS_1_REG_END               0x0004107c
+#define BCHP_DECODE_CPUCORE_1_REG_START                    0x00044000
+#define BCHP_DECODE_CPUCORE_1_REG_END                      0x00044ffc
+#define BCHP_DECODE_CPUAUX_1_REG_START                     0x00045000
+#define BCHP_DECODE_CPUAUX_1_REG_END                       0x00045ffc
+#define BCHP_DECODE_CPUIMEM_1_REG_START                    0x00046000
+#define BCHP_DECODE_CPUIMEM_1_REG_END                      0x00047ffc
+#define BCHP_DECODE_CPUDMEM_1_REG_START                    0x00048000
+#define BCHP_DECODE_CPUDMEM_1_REG_END                      0x0004fffc
+#define BCHP_DECODE_IND_SDRAM_REGS2_1_REG_START            0x00051000
+#define BCHP_DECODE_IND_SDRAM_REGS2_1_REG_END              0x0005107c
+#define BCHP_DECODE_CPUDMA2_1_REG_START                    0x00051800
+#define BCHP_DECODE_CPUDMA2_1_REG_END                      0x000518fc
+#define BCHP_DECODE_DMAMEM2_1_REG_START                    0x00051a00
+#define BCHP_DECODE_DMAMEM2_1_REG_END                      0x000521fc
+#define BCHP_DECODE_CPUCORE2_1_REG_START                   0x00054000
+#define BCHP_DECODE_CPUCORE2_1_REG_END                     0x00054ffc
+#define BCHP_DECODE_CPUAUX2_1_REG_START                    0x00055000
+#define BCHP_DECODE_CPUAUX2_1_REG_END                      0x00055ffc
+#define BCHP_DECODE_CPUIMEM2_1_REG_START                   0x00056000
+#define BCHP_DECODE_CPUIMEM2_1_REG_END                     0x00057ffc
+#define BCHP_DECODE_CPUDMEM2_1_REG_START                   0x00058000
+#define BCHP_DECODE_CPUDMEM2_1_REG_END                     0x0005fffc
+#define BCHP_DECODE_IP_SHIM_1_REG_START                    0x00060000
+#define BCHP_DECODE_IP_SHIM_1_REG_END                      0x00060084
+#define BCHP_AVD_CACHE_1_REG_START                         0x00062000
+#define BCHP_AVD_CACHE_1_REG_END                           0x0006203c
+#define BCHP_AVD_INTR2_1_REG_START                         0x00080000
+#define BCHP_AVD_INTR2_1_REG_END                           0x0008002c
+#define BCHP_AVD_RGR_1_REG_START                           0x00080400
+#define BCHP_AVD_RGR_1_REG_END                             0x00080410
+#define BCHP_VICH_1_REG_START                              0x00104000
+#define BCHP_VICH_1_REG_END                                0x0010408b
+#define BCHP_SATA_GRB_REG_START                            0x00180000
+#define BCHP_SATA_GRB_REG_END                              0x0018000c
+#define BCHP_SATA_TOP_CTRL_REG_START                       0x00180020
+#define BCHP_SATA_TOP_CTRL_REG_END                         0x00180038
+#define BCHP_SATA3_INTR2_REG_START                         0x00180080
+#define BCHP_SATA3_INTR2_REG_END                           0x001800ac
+#define BCHP_SATA_AHCI_GHC_REG_START                       0x00181000
+#define BCHP_SATA_AHCI_GHC_REG_END                         0x00181028
+#define BCHP_SATA_GLOBAL_RESERVED_REG_START                0x0018102c
+#define BCHP_SATA_GLOBAL_RESERVED_REG_END                  0x0018109c
+#define BCHP_SATA_PORT0_AHCI_S1_REG_START                  0x00181100
+#define BCHP_SATA_PORT0_AHCI_S1_REG_END                    0x0018111c
+#define BCHP_SATA_PORT0_AHCI_S2_REG_START                  0x00181120
+#define BCHP_SATA_PORT0_AHCI_S2_REG_END                    0x00181134
+#define BCHP_SATA_PORT0_AHCI_S3_REG_START                  0x00181138
+#define BCHP_SATA_PORT0_AHCI_S3_REG_END                    0x0018117c
+#define BCHP_SATA_PORT1_AHCI_S1_REG_START                  0x00181180
+#define BCHP_SATA_PORT1_AHCI_S1_REG_END                    0x0018119c
+#define BCHP_SATA_PORT1_AHCI_S2_REG_START                  0x001811a0
+#define BCHP_SATA_PORT1_AHCI_S2_REG_END                    0x001811b4
+#define BCHP_SATA_PORT1_AHCI_S3_REG_START                  0x001811b8
+#define BCHP_SATA_PORT1_AHCI_S3_REG_END                    0x001811fc
+#define BCHP_SATA_AHCI_PCICFG_REG_START                    0x00181600
+#define BCHP_SATA_AHCI_PCICFG_REG_END                      0x00181664
+#define BCHP_SATA_PORT0_CTRL_REG_START                     0x00181700
+#define BCHP_SATA_PORT0_CTRL_REG_END                       0x00181730
+#define BCHP_SATA_PORT0_CJPAT_REG_START                    0x00181740
+#define BCHP_SATA_PORT0_CJPAT_REG_END                      0x00181764
+#define BCHP_SATA_PORT1_CTRL_REG_START                     0x00181780
+#define BCHP_SATA_PORT1_CTRL_REG_END                       0x001817b0
+#define BCHP_SATA_PORT1_CJPAT_REG_START                    0x001817c0
+#define BCHP_SATA_PORT1_CJPAT_REG_END                      0x001817e4
+#define BCHP_SATA_LEG_PCICFG_REG_START                     0x00181800
+#define BCHP_SATA_LEG_PCICFG_REG_END                       0x00181880
+#define BCHP_SATA_PORT0_LEG_S1_REG_START                   0x00181900
+#define BCHP_SATA_PORT0_LEG_S1_REG_END                     0x00181934
+#define BCHP_SATA_PORT0_LEG_S2_REG_START                   0x00181940
+#define BCHP_SATA_PORT0_LEG_S2_REG_END                     0x00181954
+#define BCHP_SATA_PORT0_LEG_S3_REG_START                   0x00181958
+#define BCHP_SATA_PORT0_LEG_S3_REG_END                     0x00181998
+#define BCHP_SATA_PORT1_LEG_S1_REG_START                   0x00181a00
+#define BCHP_SATA_PORT1_LEG_S1_REG_END                     0x00181a34
+#define BCHP_SATA_PORT1_LEG_S2_REG_START                   0x00181a40
+#define BCHP_SATA_PORT1_LEG_S2_REG_END                     0x00181a54
+#define BCHP_SATA_PORT1_LEG_S3_REG_START                   0x00181a58
+#define BCHP_SATA_PORT1_LEG_S3_REG_END                     0x00181a98
+#define BCHP_BSP_CMDBUF_REG_START                          0x00329800
+#define BCHP_BSP_CMDBUF_REG_END                            0x00329ffc
+#define BCHP_BSP_GLB_CONTROL_REG_START                     0x0032b000
+#define BCHP_BSP_GLB_CONTROL_REG_END                       0x0032b098
+#define BCHP_BSP_PKL_REG_START                             0x0032b300
+#define BCHP_BSP_PKL_REG_END                               0x0032b37c
+#define BCHP_BSP_INST_PATCH_CTRL_REG_START                 0x0032b400
+#define BCHP_BSP_INST_PATCH_CTRL_REG_END                   0x0032b404
+#define BCHP_BSP_CONTROL_INTR2_REG_START                   0x0032b800
+#define BCHP_BSP_CONTROL_INTR2_REG_END                     0x0032b82c
+#define BCHP_BSP_INST_PATCHRAM_REG_START                   0x0032c000
+#define BCHP_BSP_INST_PATCHRAM_REG_END                     0x0032fffc
+#define BCHP_XPT_SECURITY_REG_START                        0x00360000
+#define BCHP_XPT_SECURITY_REG_END                          0x0036fffc
+#define BCHP_MMSCRAM_REG_START                             0x00370000
+#define BCHP_MMSCRAM_REG_END                               0x00371ffc
+#define BCHP_MEM_DMA_SECURE_REG_START                      0x00372000
+#define BCHP_MEM_DMA_SECURE_REG_END                        0x0037200c
+#define BCHP_SECTOP_GRB_REG_START                          0x00374000
+#define BCHP_SECTOP_GRB_REG_END                            0x0037400c
+#define BCHP_JTAG_OTP_REG_START                            0x00374100
+#define BCHP_JTAG_OTP_REG_END                              0x00374138
+#define BCHP_MEM_DMA_0_REG_START                           0x00374200
+#define BCHP_MEM_DMA_0_REG_END                             0x00374224
+#define BCHP_XPT_SECURITY_NS_REG_START                     0x00374300
+#define BCHP_XPT_SECURITY_NS_REG_END                       0x00374310
+#define BCHP_MEMC_GEN_0_REG_START                          0x003b0000
+#define BCHP_MEMC_GEN_0_REG_END                            0x003b04f4
+#define BCHP_MEMC_ARB_0_REG_START                          0x003b1000
+#define BCHP_MEMC_ARB_0_REG_END                            0x003b1244
+#define BCHP_MEMC_DDR_0_REG_START                          0x003b2000
+#define BCHP_MEMC_DDR_0_REG_END                            0x003b22fc
+#define BCHP_MEMC_L2_0_REG_START                           0x003b3000
+#define BCHP_MEMC_L2_0_REG_END                             0x003b302c
+#define BCHP_MEMC_L2_1_0_REG_START                         0x003b3800
+#define BCHP_MEMC_L2_1_0_REG_END                           0x003b382c
+#define BCHP_MEMC_RGRB_0_REG_START                         0x003b4000
+#define BCHP_MEMC_RGRB_0_REG_END                           0x003b4010
+#define BCHP_MEMC_MISC_0_REG_START                         0x003b5000
+#define BCHP_MEMC_MISC_0_REG_END                           0x003b5010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_START            0x003b6000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_END              0x003b60c4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_START             0x003b6200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_END               0x003b63b0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_REG_START             0x003b6400
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_REG_END               0x003b65b0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_START         0x003b8000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_END           0x003b8138
+#define BCHP_S_MEMC_0_REG_START                            0x003ba000
+#define BCHP_S_MEMC_0_REG_END                              0x003ba220
+#define BCHP_MEMC_GEN_1_REG_START                          0x003c0000
+#define BCHP_MEMC_GEN_1_REG_END                            0x003c04f4
+#define BCHP_MEMC_ARB_1_REG_START                          0x003c1000
+#define BCHP_MEMC_ARB_1_REG_END                            0x003c1244
+#define BCHP_MEMC_DDR_1_REG_START                          0x003c2000
+#define BCHP_MEMC_DDR_1_REG_END                            0x003c22fc
+#define BCHP_MEMC_L2_1_REG_START                           0x003c3000
+#define BCHP_MEMC_L2_1_REG_END                             0x003c302c
+#define BCHP_MEMC_L2_1_1_REG_START                         0x003c3800
+#define BCHP_MEMC_L2_1_1_REG_END                           0x003c382c
+#define BCHP_MEMC_RGRB_1_REG_START                         0x003c4000
+#define BCHP_MEMC_RGRB_1_REG_END                           0x003c4010
+#define BCHP_MEMC_MISC_1_REG_START                         0x003c5000
+#define BCHP_MEMC_MISC_1_REG_END                           0x003c5010
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_REG_START            0x003c6000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_REG_END              0x003c60c4
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_REG_START             0x003c6200
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_REG_END               0x003c63b0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_REG_START             0x003c6400
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_REG_END               0x003c65b0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_REG_START         0x003c8000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_REG_END           0x003c8138
+#define BCHP_S_MEMC_1_REG_START                            0x003ca000
+#define BCHP_S_MEMC_1_REG_END                              0x003ca220
+#define BCHP_SUN_GISB_ARB_REG_START                        0x00400000
+#define BCHP_SUN_GISB_ARB_REG_END                          0x004000d8
+#define BCHP_SUN_RGR_REG_START                             0x00400400
+#define BCHP_SUN_RGR_REG_END                               0x00400410
+#define BCHP_SUN_RG_REG_START                              0x00400800
+#define BCHP_SUN_RG_REG_END                                0x0040080c
+#define BCHP_TPCAP_REG_START                               0x00400c00
+#define BCHP_TPCAP_REG_END                                 0x00400c84
+#define BCHP_SUN_L2_REG_START                              0x00403000
+#define BCHP_SUN_L2_REG_END                                0x0040302c
+#define BCHP_SM_L2_REG_START                               0x00403400
+#define BCHP_SM_L2_REG_END                                 0x0040342c
+#define BCHP_SM_REG_START                                  0x00403800
+#define BCHP_SM_REG_END                                    0x00403824
+#define BCHP_SM_FAST_REG_START                             0x00403c00
+#define BCHP_SM_FAST_REG_END                               0x00403c18
+#define BCHP_SUN_TOP_CTRL_REG_START                        0x00404000
+#define BCHP_SUN_TOP_CTRL_REG_END                          0x00404518
+#define BCHP_IRB_REG_START                                 0x00406000
+#define BCHP_IRB_REG_END                                   0x00406138
+#define BCHP_PM_REG_START                                  0x00406180
+#define BCHP_PM_REG_END                                    0x00406188
+#define BCHP_BSCC_REG_START                                0x00406200
+#define BCHP_BSCC_REG_END                                  0x00406254
+#define BCHP_BSCD_REG_START                                0x00406280
+#define BCHP_BSCD_REG_END                                  0x004062d4
+#define BCHP_BSCE_REG_START                                0x00406300
+#define BCHP_BSCE_REG_END                                  0x00406354
+#define BCHP_PWM_REG_START                                 0x00406580
+#define BCHP_PWM_REG_END                                   0x004065a4
+#define BCHP_GIO_REG_START                                 0x00406700
+#define BCHP_GIO_REG_END                                   0x0040677c
+#define BCHP_IRQ0_REG_START                                0x00406780
+#define BCHP_IRQ0_REG_END                                  0x00406784
+#define BCHP_IRQ1_REG_START                                0x00406788
+#define BCHP_IRQ1_REG_END                                  0x0040678c
+#define BCHP_TIMER_REG_START                               0x004067c0
+#define BCHP_TIMER_REG_END                                 0x004067fc
+#define BCHP_PWMB_REG_START                                0x00406800
+#define BCHP_PWMB_REG_END                                  0x00406824
+#define BCHP_UARTA_REG_START                               0x00406b00
+#define BCHP_UARTA_REG_END                                 0x00406b1c
+#define BCHP_UARTB_REG_START                               0x00406b40
+#define BCHP_UARTB_REG_END                                 0x00406b5c
+#define BCHP_UARTC_REG_START                               0x00406b80
+#define BCHP_UARTC_REG_END                                 0x00406b9c
+#define BCHP_SCA_REG_START                                 0x00406c00
+#define BCHP_SCA_REG_END                                   0x00406cbc
+#define BCHP_SCB_REG_START                                 0x00406cc0
+#define BCHP_SCB_REG_END                                   0x00406d7c
+#define BCHP_SCIRQ0_REG_START                              0x00406e40
+#define BCHP_SCIRQ0_REG_END                                0x00406e44
+#define BCHP_SCIRQ1_REG_START                              0x00406e48
+#define BCHP_SCIRQ1_REG_END                                0x00406e4c
+#define BCHP_MCIF_REG_START                                0x00407000
+#define BCHP_MCIF_REG_END                                  0x00407020
+#define BCHP_MCIF_INTR2_REG_START                          0x00407040
+#define BCHP_MCIF_INTR2_REG_END                            0x0040706c
+#define BCHP_TMON_REG_START                                0x00407080
+#define BCHP_TMON_REG_END                                  0x004070d0
+#define BCHP_UPG_AUX_INTR2_REG_START                       0x00407100
+#define BCHP_UPG_AUX_INTR2_REG_END                         0x0040712c
+#define BCHP_CTK_REG_START                                 0x00407200
+#define BCHP_CTK_REG_END                                   0x00407378
+#define BCHP_UPG_UART_DMA_REG_START                        0x00407400
+#define BCHP_UPG_UART_DMA_REG_END                          0x00407428
+#define BCHP_AON_CTRL_REG_START                            0x00408000
+#define BCHP_AON_CTRL_REG_END                              0x004083fc
+#define BCHP_AON_L2_REG_START                              0x00408400
+#define BCHP_AON_L2_REG_END                                0x0040842c
+#define BCHP_AON_PM_L2_REG_START                           0x00408440
+#define BCHP_AON_PM_L2_REG_END                             0x0040846c
+#define BCHP_AON_PIN_CTRL_REG_START                        0x00408500
+#define BCHP_AON_PIN_CTRL_REG_END                          0x00408518
+#define BCHP_AON_HDMI_TX_REG_START                         0x00408600
+#define BCHP_AON_HDMI_TX_REG_END                           0x00408698
+#define BCHP_AON_HDMI_RX_REG_START                         0x00408800
+#define BCHP_AON_HDMI_RX_REG_END                           0x00408908
+#define BCHP_LDK_REG_START                                 0x00409000
+#define BCHP_LDK_REG_END                                   0x0040903c
+#define BCHP_PM_AON_REG_START                              0x00409040
+#define BCHP_PM_AON_REG_END                                0x00409048
+#define BCHP_ICAP_REG_START                                0x00409080
+#define BCHP_ICAP_REG_END                                  0x004090bc
+#define BCHP_KBD1_REG_START                                0x004090c0
+#define BCHP_KBD1_REG_END                                  0x004090fc
+#define BCHP_KBD2_REG_START                                0x00409100
+#define BCHP_KBD2_REG_END                                  0x0040913c
+#define BCHP_KBD3_REG_START                                0x00409140
+#define BCHP_KBD3_REG_END                                  0x0040917c
+#define BCHP_BSCA_REG_START                                0x00409180
+#define BCHP_BSCA_REG_END                                  0x004091d4
+#define BCHP_MSPI_REG_START                                0x00409200
+#define BCHP_MSPI_REG_END                                  0x0040937c
+#define BCHP_BSCB_REG_START                                0x00409400
+#define BCHP_BSCB_REG_END                                  0x00409454
+#define BCHP_IRQ0_AON_REG_START                            0x00409480
+#define BCHP_IRQ0_AON_REG_END                              0x00409484
+#define BCHP_IRQ1_AON_REG_START                            0x00409488
+#define BCHP_IRQ1_AON_REG_END                              0x0040948c
+#define BCHP_GIO_AON_REG_START                             0x004094c0
+#define BCHP_GIO_AON_REG_END                               0x004094fc
+#define BCHP_BICAP_REG_START                               0x00409500
+#define BCHP_BICAP_REG_END                                 0x00409538
+#define BCHP_UPG_AUX_AON_INTR2_REG_START                   0x00409540
+#define BCHP_UPG_AUX_AON_INTR2_REG_END                     0x0040956c
+#define BCHP_WKTMR_REG_START                               0x00409580
+#define BCHP_WKTMR_REG_END                                 0x00409590
+#define BCHP_SYS_GISB_ARB_SEC_REG_START                    0x0040e000
+#define BCHP_SYS_GISB_ARB_SEC_REG_END                      0x0040e0b4
+#define BCHP_SYS_TOP_CTRL_SEC_REG_START                    0x0040e700
+#define BCHP_SYS_TOP_CTRL_SEC_REG_END                      0x0040e704
+#define BCHP_AON_CTRL_SECURE_REG_START                     0x0040e800
+#define BCHP_AON_CTRL_SECURE_REG_END                       0x0040e87c
+#define BCHP_PCIE_RC_CFG_TYPE1_REG_START                   0x00410000
+#define BCHP_PCIE_RC_CFG_TYPE1_REG_END                     0x0041003c
+#define BCHP_PCIE_RC_CFG_PM_REG_START                      0x00410048
+#define BCHP_PCIE_RC_CFG_PM_REG_END                        0x0041004c
+#define BCHP_PCIE_RC_CFG_PCIE_REG_START                    0x004100ac
+#define BCHP_PCIE_RC_CFG_PCIE_REG_END                      0x004100e4
+#define BCHP_PCIE_RC_CFG_AER_REG_START                     0x00410100
+#define BCHP_PCIE_RC_CFG_AER_REG_END                       0x00410134
+#define BCHP_PCIE_RC_CFG_VC_REG_START                      0x00410160
+#define BCHP_PCIE_RC_CFG_VC_REG_END                        0x00410178
+#define BCHP_PCIE_RC_CFG_VENDOR_REG_START                  0x00410180
+#define BCHP_PCIE_RC_CFG_VENDOR_REG_END                    0x004101a4
+#define BCHP_PCIE_RC_CFG_PRIV0_REG_START                   0x00410404
+#define BCHP_PCIE_RC_CFG_PRIV0_REG_END                     0x00410418
+#define BCHP_PCIE_RC_CFG_PRIV1_REG_START                   0x00410428
+#define BCHP_PCIE_RC_CFG_PRIV1_REG_END                     0x00410564
+#define BCHP_PCIE_RC_TL_REG_START                          0x00410800
+#define BCHP_PCIE_RC_TL_REG_END                            0x00410998
+#define BCHP_PCIE_RC_DL_REG_START                          0x00411000
+#define BCHP_PCIE_RC_DL_REG_END                            0x00411424
+#define BCHP_PCIE_RC_PL_REG_START                          0x00411800
+#define BCHP_PCIE_RC_PL_REG_END                            0x00411d30
+#define BCHP_PCIE_EP_CFG_TYPE0_REG_START                   0x00412000
+#define BCHP_PCIE_EP_CFG_TYPE0_REG_END                     0x0041203c
+#define BCHP_PCIE_EP_CFG_PM_REG_START                      0x00412048
+#define BCHP_PCIE_EP_CFG_PM_REG_END                        0x0041204c
+#define BCHP_PCIE_EP_CFG_VPD_REG_START                     0x00412050
+#define BCHP_PCIE_EP_CFG_VPD_REG_END                       0x00412054
+#define BCHP_PCIE_EP_CFG_MSI_REG_START                     0x00412058
+#define BCHP_PCIE_EP_CFG_MSI_REG_END                       0x00412064
+#define BCHP_PCIE_EP_CFG_MSIX_REG_START                    0x004120a0
+#define BCHP_PCIE_EP_CFG_MSIX_REG_END                      0x004120a8
+#define BCHP_PCIE_EP_CFG_PCIE_REG_START                    0x004120ac
+#define BCHP_PCIE_EP_CFG_PCIE_REG_END                      0x004120e4
+#define BCHP_PCIE_EP_CFG_AER_REG_START                     0x00412100
+#define BCHP_PCIE_EP_CFG_AER_REG_END                       0x00412134
+#define BCHP_PCIE_EP_CFG_DEV_REG_START                     0x0041213c
+#define BCHP_PCIE_EP_CFG_DEV_REG_END                       0x00412144
+#define BCHP_PCIE_EP_CFG_PB_REG_START                      0x00412150
+#define BCHP_PCIE_EP_CFG_PB_REG_END                        0x0041215c
+#define BCHP_PCIE_EP_CFG_VC_REG_START                      0x00412160
+#define BCHP_PCIE_EP_CFG_VC_REG_END                        0x00412178
+#define BCHP_PCIE_EP_CFG_VENDOR_REG_START                  0x00412180
+#define BCHP_PCIE_EP_CFG_VENDOR_REG_END                    0x004121a4
+#define BCHP_PCIE_EP_CFG_PRIV0_REG_START                   0x00412404
+#define BCHP_PCIE_EP_CFG_PRIV0_REG_END                     0x00412418
+#define BCHP_PCIE_EP_CFG_PRIV1_REG_START                   0x00412428
+#define BCHP_PCIE_EP_CFG_PRIV1_REG_END                     0x00412564
+#define BCHP_PCIE_EP_TL_REG_START                          0x00412800
+#define BCHP_PCIE_EP_TL_REG_END                            0x00412998
+#define BCHP_PCIE_EP_DL_REG_START                          0x00413000
+#define BCHP_PCIE_EP_DL_REG_END                            0x00413424
+#define BCHP_PCIE_EP_PL_REG_START                          0x00413800
+#define BCHP_PCIE_EP_PL_REG_END                            0x00413d30
+#define BCHP_PCIE_MISC_REG_START                           0x00414000
+#define BCHP_PCIE_MISC_REG_END                             0x00414094
+#define BCHP_PCIE_MISC_PERST_REG_START                     0x00414100
+#define BCHP_PCIE_MISC_PERST_REG_END                       0x00414104
+#define BCHP_PCIE_MISC_HARD_REG_START                      0x00414200
+#define BCHP_PCIE_MISC_HARD_REG_END                        0x00414204
+#define BCHP_PCIE_INTR2_REG_START                          0x00414300
+#define BCHP_PCIE_INTR2_REG_END                            0x0041432c
+#define BCHP_PCIE_DMA_REG_START                            0x00414400
+#define BCHP_PCIE_DMA_REG_END                              0x0041446c
+#define BCHP_HIF_RGR1_REG_START                            0x00418000
+#define BCHP_HIF_RGR1_REG_END                              0x00418010
+#define BCHP_HIF_PCIe_RG_REG_START                         0x00418200
+#define BCHP_HIF_PCIe_RG_REG_END                           0x0041820c
+#define BCHP_PCIE_EXT_CFG_REG_START                        0x00418300
+#define BCHP_PCIE_EXT_CFG_REG_END                          0x00418308
+#define BCHP_SDIO_0_HOST_REG_START                         0x00419000
+#define BCHP_SDIO_0_HOST_REG_END                           0x004190fc
+#define BCHP_SDIO_0_CFG_REG_START                          0x00419100
+#define BCHP_SDIO_0_CFG_REG_END                            0x004191fc
+#define BCHP_SDIO_1_HOST_REG_START                         0x00419200
+#define BCHP_SDIO_1_HOST_REG_END                           0x004192fc
+#define BCHP_SDIO_1_CFG_REG_START                          0x00419300
+#define BCHP_SDIO_1_CFG_REG_END                            0x004193fc
+#define BCHP_SDIO_1_BOOT_REG_START                         0x00419400
+#define BCHP_SDIO_1_BOOT_REG_END                           0x0041943c
+#define BCHP_EBI_REG_START                                 0x00419800
+#define BCHP_EBI_REG_END                                   0x00419bfc
+#define BCHP_HIF_INTR2_REG_START                           0x0041a000
+#define BCHP_HIF_INTR2_REG_END                             0x0041a02c
+#define BCHP_IPI0_INTR2_REG_START                          0x0041a100
+#define BCHP_IPI0_INTR2_REG_END                            0x0041a12c
+#define BCHP_IPI1_INTR2_REG_START                          0x0041a200
+#define BCHP_IPI1_INTR2_REG_END                            0x0041a22c
+#define BCHP_HIF_CPU_INTR1_REG_START                       0x0041a400
+#define BCHP_HIF_CPU_INTR1_REG_END                         0x0041a42c
+#define BCHP_HIF_CPU_TP1_INTR1_REG_START                   0x0041a600
+#define BCHP_HIF_CPU_TP1_INTR1_REG_END                     0x0041a62c
+#define BCHP_PCI_PCIE_INTR1_REG_START                      0x0041a700
+#define BCHP_PCI_PCIE_INTR1_REG_END                        0x0041a72c
+#define BCHP_HIF_RGR2_REG_START                            0x0041a800
+#define BCHP_HIF_RGR2_REG_END                              0x0041a810
+#define BCHP_HIF_SPI_INTR2_REG_START                       0x0041ad00
+#define BCHP_HIF_SPI_INTR2_REG_END                         0x0041ad2c
+#define BCHP_HIF_TOP_CTRL_REG_START                        0x0041b400
+#define BCHP_HIF_TOP_CTRL_REG_END                          0x0041b41c
+#define BCHP_NAND_REG_START                                0x0041b800
+#define BCHP_NAND_REG_END                                  0x0041bbfc
+#define BCHP_EDU_REG_START                                 0x0041bc00
+#define BCHP_EDU_REG_END                                   0x0041bc20
+#define BCHP_BSPI_REG_START                                0x0041c000
+#define BCHP_BSPI_REG_END                                  0x0041c04c
+#define BCHP_BSPI_RAF_REG_START                            0x0041c100
+#define BCHP_BSPI_RAF_REG_END                              0x0041c120
+#define BCHP_HIF_MSPI_REG_START                            0x0041c200
+#define BCHP_HIF_MSPI_REG_END                              0x0041c384
+#define BCHP_MICH_REG_START                                0x00429000
+#define BCHP_MICH_REG_END                                  0x00429000
+#define BCHP_HIF_SECURE_CTRL_REG_START                     0x00429100
+#define BCHP_HIF_SECURE_CTRL_REG_END                       0x00429100
+#define BCHP_HIF_SECURE_BSPI_REG_START                     0x00429200
+#define BCHP_HIF_SECURE_BSPI_REG_END                       0x00429200
+#define BCHP_HIF_SECURE_LR_SPI_REG_START                   0x00429300
+#define BCHP_HIF_SECURE_LR_SPI_REG_END                     0x00429300
+#define BCHP_NAND_SECURE_REG_START                         0x00429400
+#define BCHP_NAND_SECURE_REG_END                           0x00429400
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_START        0x00429800
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_END          0x00429800
+#define BCHP_CLKGEN_REG_START                              0x00430000
+#define BCHP_CLKGEN_REG_END                                0x00430528
+#define BCHP_VCXO_2_RM_REG_START                           0x00432000
+#define BCHP_VCXO_2_RM_REG_END                             0x0043202c
+#define BCHP_VCXO_1_RM_REG_START                           0x00432080
+#define BCHP_VCXO_1_RM_REG_END                             0x004320ac
+#define BCHP_VCXO_0_RM_REG_START                           0x00432100
+#define BCHP_VCXO_0_RM_REG_END                             0x0043212c
+#define BCHP_AVS_HW_MNTR_REG_START                         0x00432800
+#define BCHP_AVS_HW_MNTR_REG_END                           0x00432874
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_START                 0x00432900
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_END                   0x0043291c
+#define BCHP_AVS_ASB_REGISTERS_REG_START                   0x00432a00
+#define BCHP_AVS_ASB_REGISTERS_REG_END                     0x00432a18
+#define BCHP_AVS_RO_REGISTERS_0_REG_START                  0x00432b00
+#define BCHP_AVS_RO_REGISTERS_0_REG_END                    0x00432bdc
+#define BCHP_AVS_RO_REGISTERS_1_REG_START                  0x00432c00
+#define BCHP_AVS_RO_REGISTERS_1_REG_END                    0x00432c8c
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_START                0x00432d00
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_END                  0x00432de4
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_START                0x00432e00
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_END                  0x00432ee4
+#define BCHP_CLKGEN_INTR2_REG_START                        0x00433000
+#define BCHP_CLKGEN_INTR2_REG_END                          0x0043302c
+#define BCHP_CLKGEN_GR_REG_START                           0x00433400
+#define BCHP_CLKGEN_GR_REG_END                             0x0043340c
+#define BCHP_UHFR_REG_START                                0x00438000
+#define BCHP_UHFR_REG_END                                  0x004380f8
+#define BCHP_UHFR_INTR2_REG_START                          0x00438200
+#define BCHP_UHFR_INTR2_REG_END                            0x0043822c
+#define BCHP_UHFR_GR_BRIDGE_REG_START                      0x00438300
+#define BCHP_UHFR_GR_BRIDGE_REG_END                        0x0043830c
+#define BCHP_USB_CAPS_REG_START                            0x00480000
+#define BCHP_USB_CAPS_REG_END                              0x0048002c
+#define BCHP_USB_GR_BRIDGE_REG_START                       0x00480100
+#define BCHP_USB_GR_BRIDGE_REG_END                         0x0048010c
+#define BCHP_USB_INTR2_REG_START                           0x00480180
+#define BCHP_USB_INTR2_REG_END                             0x004801ac
+#define BCHP_USB_CTRL_REG_START                            0x00480200
+#define BCHP_USB_CTRL_REG_END                              0x00480238
+#define BCHP_USB_EHCI_REG_START                            0x00480300
+#define BCHP_USB_EHCI_REG_END                              0x004803a4
+#define BCHP_USB_OHCI_REG_START                            0x00480400
+#define BCHP_USB_OHCI_REG_END                              0x00480454
+#define BCHP_USB_EHCI1_REG_START                           0x00480500
+#define BCHP_USB_EHCI1_REG_END                             0x004805a4
+#define BCHP_USB_OHCI1_REG_START                           0x00480600
+#define BCHP_USB_OHCI1_REG_END                             0x00480654
+#define BCHP_USB1_CAPS_REG_START                           0x00490000
+#define BCHP_USB1_CAPS_REG_END                             0x0049002c
+#define BCHP_USB1_GR_BRIDGE_REG_START                      0x00490100
+#define BCHP_USB1_GR_BRIDGE_REG_END                        0x0049010c
+#define BCHP_USB1_INTR2_REG_START                          0x00490180
+#define BCHP_USB1_INTR2_REG_END                            0x004901ac
+#define BCHP_USB1_CTRL_REG_START                           0x00490200
+#define BCHP_USB1_CTRL_REG_END                             0x00490238
+#define BCHP_USB1_EHCI_REG_START                           0x00490300
+#define BCHP_USB1_EHCI_REG_END                             0x004903a4
+#define BCHP_USB1_OHCI_REG_START                           0x00490400
+#define BCHP_USB1_OHCI_REG_END                             0x00490454
+#define BCHP_USB1_EHCI1_REG_START                          0x00490500
+#define BCHP_USB1_EHCI1_REG_END                            0x004905a4
+#define BCHP_USB1_OHCI1_REG_START                          0x00490600
+#define BCHP_USB1_OHCI1_REG_END                            0x00490654
+#define BCHP_BOOTROM_REG_START                             0x00500000
+#define BCHP_BOOTROM_REG_END                               0x00500ffc
+#define BCHP_MFD_0_REG_START                               0x00600000
+#define BCHP_MFD_0_REG_END                                 0x00600264
+#define BCHP_MFD_1_REG_START                               0x00600400
+#define BCHP_MFD_1_REG_END                                 0x006005fc
+#define BCHP_MFD_2_REG_START                               0x00600800
+#define BCHP_MFD_2_REG_END                                 0x006009fc
+#define BCHP_VFD_0_REG_START                               0x00601000
+#define BCHP_VFD_0_REG_END                                 0x006011fc
+#define BCHP_VFD_1_REG_START                               0x00601200
+#define BCHP_VFD_1_REG_END                                 0x006013fc
+#define BCHP_VFD_2_REG_START                               0x00601400
+#define BCHP_VFD_2_REG_END                                 0x006015fc
+#define BCHP_VFD_3_REG_START                               0x00601600
+#define BCHP_VFD_3_REG_END                                 0x006017fc
+#define BCHP_VFD_4_REG_START                               0x00601800
+#define BCHP_VFD_4_REG_END                                 0x006019fc
+#define BCHP_RDC_REG_START                                 0x00602000
+#define BCHP_RDC_REG_END                                   0x006029fc
+#define BCHP_BVNF_INTR2_0_REG_START                        0x00603000
+#define BCHP_BVNF_INTR2_0_REG_END                          0x0060302c
+#define BCHP_BVNF_INTR2_1_REG_START                        0x00603100
+#define BCHP_BVNF_INTR2_1_REG_END                          0x0060312c
+#define BCHP_BVNF_INTR2_3_REG_START                        0x00603300
+#define BCHP_BVNF_INTR2_3_REG_END                          0x0060332c
+#define BCHP_BVNF_INTR2_4_REG_START                        0x00603400
+#define BCHP_BVNF_INTR2_4_REG_END                          0x0060342c
+#define BCHP_BVNF_INTR2_5_REG_START                        0x00603500
+#define BCHP_BVNF_INTR2_5_REG_END                          0x0060352c
+#define BCHP_FMISC_REG_START                               0x00604000
+#define BCHP_FMISC_REG_END                                 0x00604020
+#define BCHP_SCL_0_REG_START                               0x00620000
+#define BCHP_SCL_0_REG_END                                 0x006203fc
+#define BCHP_SCL_1_REG_START                               0x00620400
+#define BCHP_SCL_1_REG_END                                 0x006207fc
+#define BCHP_SCL_2_REG_START                               0x00620800
+#define BCHP_SCL_2_REG_END                                 0x00620bfc
+#define BCHP_SCL_3_REG_START                               0x00620c00
+#define BCHP_SCL_3_REG_END                                 0x00620ffc
+#define BCHP_SCL_4_REG_START                               0x00621000
+#define BCHP_SCL_4_REG_END                                 0x006213fc
+#define BCHP_VNET_F_REG_START                              0x00622000
+#define BCHP_VNET_F_REG_END                                0x006220bc
+#define BCHP_VNET_B_REG_START                              0x00622200
+#define BCHP_VNET_B_REG_END                                0x006222ac
+#define BCHP_MMISC_REG_START                               0x00622800
+#define BCHP_MMISC_REG_END                                 0x00622820
+#define BCHP_LBOX_0_REG_START                              0x00624000
+#define BCHP_LBOX_0_REG_END                                0x00624070
+#define BCHP_LBOX_1_REG_START                              0x00624200
+#define BCHP_LBOX_1_REG_END                                0x00624270
+#define BCHP_LBOX_2_REG_START                              0x00624400
+#define BCHP_LBOX_2_REG_END                                0x00624470
+#define BCHP_LBOX_3_REG_START                              0x00624600
+#define BCHP_LBOX_3_REG_END                                0x00624670
+#define BCHP_DNR_0_REG_START                               0x00626000
+#define BCHP_DNR_0_REG_END                                 0x006260a4
+#define BCHP_DNR_1_REG_START                               0x00626400
+#define BCHP_DNR_1_REG_END                                 0x006264a4
+#define BCHP_DNR_2_REG_START                               0x00626600
+#define BCHP_DNR_2_REG_END                                 0x006266a4
+#define BCHP_BVNM_INTR2_0_REG_START                        0x00627000
+#define BCHP_BVNM_INTR2_0_REG_END                          0x0062702c
+#define BCHP_BVNM_INTR2_1_REG_START                        0x00627100
+#define BCHP_BVNM_INTR2_1_REG_END                          0x0062712c
+#define BCHP_CAP_0_REG_START                               0x00640000
+#define BCHP_CAP_0_REG_END                                 0x0064007c
+#define BCHP_CAP_1_REG_START                               0x00640200
+#define BCHP_CAP_1_REG_END                                 0x0064027c
+#define BCHP_CAP_2_REG_START                               0x00640400
+#define BCHP_CAP_2_REG_END                                 0x0064047c
+#define BCHP_CAP_3_REG_START                               0x00640600
+#define BCHP_CAP_3_REG_END                                 0x0064067c
+#define BCHP_CAP_4_REG_START                               0x00640800
+#define BCHP_CAP_4_REG_END                                 0x0064087c
+#define BCHP_GFD_0_REG_START                               0x00641000
+#define BCHP_GFD_0_REG_END                                 0x00641228
+#define BCHP_GFD_1_REG_START                               0x00641400
+#define BCHP_GFD_1_REG_END                                 0x00641554
+#define BCHP_GFD_2_REG_START                               0x00641800
+#define BCHP_GFD_2_REG_END                                 0x00641a28
+#define BCHP_GFD_3_REG_START                               0x00641c00
+#define BCHP_GFD_3_REG_END                                 0x00641e28
+#define BCHP_CMP_0_REG_START                               0x00642000
+#define BCHP_CMP_0_REG_END                                 0x006424b4
+#define BCHP_CMP_1_REG_START                               0x00642800
+#define BCHP_CMP_1_REG_END                                 0x00642cb4
+#define BCHP_CMP_2_REG_START                               0x00643000
+#define BCHP_CMP_2_REG_END                                 0x00643264
+#define BCHP_CMP_3_REG_START                               0x00643800
+#define BCHP_CMP_3_REG_END                                 0x00643a64
+#define BCHP_TNT_CMP_0_V0_REG_START                        0x00644000
+#define BCHP_TNT_CMP_0_V0_REG_END                          0x006440a4
+#define BCHP_MASK_0_REG_START                              0x00644400
+#define BCHP_MASK_0_REG_END                                0x00644420
+#define BCHP_PEP_CMP_0_V0_REG_START                        0x00646000
+#define BCHP_PEP_CMP_0_V0_REG_END                          0x00647484
+#define BCHP_BVNB_INTR2_REG_START                          0x00648000
+#define BCHP_BVNB_INTR2_REG_END                            0x0064802c
+#define BCHP_BMISC_REG_START                               0x00648400
+#define BCHP_BMISC_REG_END                                 0x0064841c
+#define BCHP_MVP_TOP_0_REG_START                           0x00660000
+#define BCHP_MVP_TOP_0_REG_END                             0x0066002c
+#define BCHP_SIOB_0_REG_START                              0x00660200
+#define BCHP_SIOB_0_REG_END                                0x006602fc
+#define BCHP_HSCL_0_REG_START                              0x00660400
+#define BCHP_HSCL_0_REG_END                                0x006607fc
+#define BCHP_HD_ANR_MCTF_0_REG_START                       0x00661000
+#define BCHP_HD_ANR_MCTF_0_REG_END                         0x0066127c
+#define BCHP_HD_ANR_AND_0_REG_START                        0x00661800
+#define BCHP_HD_ANR_AND_0_REG_END                          0x00661888
+#define BCHP_MDI_TOP_0_REG_START                           0x00662000
+#define BCHP_MDI_TOP_0_REG_END                             0x00662054
+#define BCHP_MDI_FCB_0_REG_START                           0x00662400
+#define BCHP_MDI_FCB_0_REG_END                             0x006627fc
+#define BCHP_MDI_PPB_0_REG_START                           0x00662800
+#define BCHP_MDI_PPB_0_REG_END                             0x00662bfc
+#define BCHP_MDI_FCN_0_REG_START                           0x00662c00
+#define BCHP_MDI_FCN_0_REG_END                             0x00662ffc
+#define BCHP_MVP_TOP_1_REG_START                           0x00670000
+#define BCHP_MVP_TOP_1_REG_END                             0x0067002c
+#define BCHP_SIOB_1_REG_START                              0x00670200
+#define BCHP_SIOB_1_REG_END                                0x006702fc
+#define BCHP_HSCL_1_REG_START                              0x00670400
+#define BCHP_HSCL_1_REG_END                                0x006707fc
+#define BCHP_MDI_TOP_1_REG_START                           0x00672000
+#define BCHP_MDI_TOP_1_REG_END                             0x00672044
+#define BCHP_MDI_PPB_1_REG_START                           0x00672800
+#define BCHP_MDI_PPB_1_REG_END                             0x00672bfc
+#define BCHP_MDI_FCN_1_REG_START                           0x00672c00
+#define BCHP_MDI_FCN_1_REG_END                             0x00672ffc
+#define BCHP_MVP_TOP_2_REG_START                           0x00680000
+#define BCHP_MVP_TOP_2_REG_END                             0x0068002c
+#define BCHP_SIOB_2_REG_START                              0x00680200
+#define BCHP_SIOB_2_REG_END                                0x006802fc
+#define BCHP_HSCL_2_REG_START                              0x00680400
+#define BCHP_HSCL_2_REG_END                                0x006807fc
+#define BCHP_MDI_TOP_2_REG_START                           0x00682000
+#define BCHP_MDI_TOP_2_REG_END                             0x00682044
+#define BCHP_MDI_PPB_2_REG_START                           0x00682800
+#define BCHP_MDI_PPB_2_REG_END                             0x00682bfc
+#define BCHP_MDI_FCN_2_REG_START                           0x00682c00
+#define BCHP_MDI_FCN_2_REG_END                             0x00682ffc
+#define BCHP_MISC_REG_START                                0x00690000
+#define BCHP_MISC_REG_END                                  0x006900a8
+#define BCHP_IT_0_REG_START                                0x00691000
+#define BCHP_IT_0_REG_END                                  0x006917fc
+#define BCHP_IT_1_REG_START                                0x00692000
+#define BCHP_IT_1_REG_END                                  0x006927fc
+#define BCHP_VF_0_REG_START                                0x00693000
+#define BCHP_VF_0_REG_END                                  0x00693134
+#define BCHP_VF_1_REG_START                                0x00693200
+#define BCHP_VF_1_REG_END                                  0x00693334
+#define BCHP_SECAM_0_REG_START                             0x00693400
+#define BCHP_SECAM_0_REG_END                               0x00693414
+#define BCHP_SM_0_REG_START                                0x00693480
+#define BCHP_SM_0_REG_END                                  0x006934ac
+#define BCHP_SDSRC_0_REG_START                             0x00693500
+#define BCHP_SDSRC_0_REG_END                               0x0069350c
+#define BCHP_HDSRC_0_REG_START                             0x00693520
+#define BCHP_HDSRC_0_REG_END                               0x0069353c
+#define BCHP_CSC_0_REG_START                               0x00693580
+#define BCHP_CSC_0_REG_END                                 0x006935b0
+#define BCHP_CSC_1_REG_START                               0x00693600
+#define BCHP_CSC_1_REG_END                                 0x00693630
+#define BCHP_RM_0_REG_START                                0x00693680
+#define BCHP_RM_0_REG_END                                  0x006936a4
+#define BCHP_RM_1_REG_START                                0x006936c0
+#define BCHP_RM_1_REG_END                                  0x006936e4
+#define BCHP_ANA_DEBUG_0_REG_START                         0x00693700
+#define BCHP_ANA_DEBUG_0_REG_END                           0x00693744
+#define BCHP_DTRAM_0_REG_START                             0x00693800
+#define BCHP_DTRAM_0_REG_END                               0x00693c7c
+#define BCHP_DVI_DTG_0_REG_START                           0x00694000
+#define BCHP_DVI_DTG_0_REG_END                             0x00694174
+#define BCHP_DVI_DTG_RM_0_REG_START                        0x00694800
+#define BCHP_DVI_DTG_RM_0_REG_END                          0x00694824
+#define BCHP_DVI_CSC_0_REG_START                           0x00694900
+#define BCHP_DVI_CSC_0_REG_END                             0x00694930
+#define BCHP_DVI_DVF_0_REG_START                           0x00694a00
+#define BCHP_DVI_DVF_0_REG_END                             0x00694a18
+#define BCHP_DVI_DEBUG_0_REG_START                         0x00694b00
+#define BCHP_DVI_DEBUG_0_REG_END                           0x00694b44
+#define BCHP_ITU656_DTG_0_REG_START                        0x00695000
+#define BCHP_ITU656_DTG_0_REG_END                          0x00695174
+#define BCHP_ITU656_CSC_0_REG_START                        0x00695200
+#define BCHP_ITU656_CSC_0_REG_END                          0x00695230
+#define BCHP_ITU656_DVF_0_REG_START                        0x00695300
+#define BCHP_ITU656_DVF_0_REG_END                          0x00695318
+#define BCHP_ITU656_0_REG_START                            0x00695400
+#define BCHP_ITU656_0_REG_END                              0x00695420
+#define BCHP_ITU656_DTG_1_REG_START                        0x00695800
+#define BCHP_ITU656_DTG_1_REG_END                          0x00695974
+#define BCHP_ITU656_CSC_1_REG_START                        0x00695a00
+#define BCHP_ITU656_CSC_1_REG_END                          0x00695a30
+#define BCHP_ITU656_DVF_1_REG_START                        0x00695b00
+#define BCHP_ITU656_DVF_1_REG_END                          0x00695b18
+#define BCHP_ITU656_1_REG_START                            0x00695c00
+#define BCHP_ITU656_1_REG_END                              0x00695c20
+#define BCHP_VEC_CFG_REG_START                             0x00696000
+#define BCHP_VEC_CFG_REG_END                               0x00696168
+#define BCHP_VIDEO_ENC_INTR2_REG_START                     0x00696400
+#define BCHP_VIDEO_ENC_INTR2_REG_END                       0x0069642c
+#define BCHP_VIDEO_ENC_TPG_0_REG_START                     0x00696500
+#define BCHP_VIDEO_ENC_TPG_0_REG_END                       0x00696518
+#define BCHP_VIDEO_ENC_STG_0_REG_START                     0x00696600
+#define BCHP_VIDEO_ENC_STG_0_REG_END                       0x00696640
+#define BCHP_VIDEO_ENC_STG_1_REG_START                     0x00696700
+#define BCHP_VIDEO_ENC_STG_1_REG_END                       0x00696740
+#define BCHP_DSCL_0_REG_START                              0x00696c00
+#define BCHP_DSCL_0_REG_END                                0x00696ffc
+#define BCHP_VIDEO_ENC_DECIM_0_REG_START                   0x00697200
+#define BCHP_VIDEO_ENC_DECIM_0_REG_END                     0x00697208
+#define BCHP_DVP_TVG_0_REG_START                           0x00697300
+#define BCHP_DVP_TVG_0_REG_END                             0x00697388
+#define BCHP_VBI_ENC_REG_START                             0x00698000
+#define BCHP_VBI_ENC_REG_END                               0x00698094
+#define BCHP_CCE_0_REG_START                               0x00698400
+#define BCHP_CCE_0_REG_END                                 0x00698458
+#define BCHP_CCE_1_REG_START                               0x00698500
+#define BCHP_CCE_1_REG_END                                 0x00698558
+#define BCHP_WSE_0_REG_START                               0x00698600
+#define BCHP_WSE_0_REG_END                                 0x00698614
+#define BCHP_WSE_1_REG_START                               0x00698700
+#define BCHP_WSE_1_REG_END                                 0x00698714
+#define BCHP_CGMSAE_0_REG_START                            0x00698800
+#define BCHP_CGMSAE_0_REG_END                              0x00698858
+#define BCHP_CGMSAE_1_REG_START                            0x00698900
+#define BCHP_CGMSAE_1_REG_END                              0x00698958
+#define BCHP_TTE_0_REG_START                               0x00698a00
+#define BCHP_TTE_0_REG_END                                 0x00698a28
+#define BCHP_TTE_1_REG_START                               0x00698b00
+#define BCHP_TTE_1_REG_END                                 0x00698b28
+#define BCHP_GSE_0_REG_START                               0x00698c00
+#define BCHP_GSE_0_REG_END                                 0x00698c80
+#define BCHP_GSE_1_REG_START                               0x00698d00
+#define BCHP_GSE_1_REG_END                                 0x00698d80
+#define BCHP_AMOLE_0_REG_START                             0x00698e00
+#define BCHP_AMOLE_0_REG_END                               0x00698e8c
+#define BCHP_AMOLE_1_REG_START                             0x00698f00
+#define BCHP_AMOLE_1_REG_END                               0x00698f8c
+#define BCHP_CCE_ANCIL_0_REG_START                         0x00699000
+#define BCHP_CCE_ANCIL_0_REG_END                           0x00699054
+#define BCHP_CCE_ANCIL_1_REG_START                         0x00699100
+#define BCHP_CCE_ANCIL_1_REG_END                           0x00699154
+#define BCHP_WSE_ANCIL_0_REG_START                         0x00699200
+#define BCHP_WSE_ANCIL_0_REG_END                           0x0069920c
+#define BCHP_WSE_ANCIL_1_REG_START                         0x00699300
+#define BCHP_WSE_ANCIL_1_REG_END                           0x0069930c
+#define BCHP_TTE_ANCIL_0_REG_START                         0x00699400
+#define BCHP_TTE_ANCIL_0_REG_END                           0x00699428
+#define BCHP_TTE_ANCIL_1_REG_START                         0x00699500
+#define BCHP_TTE_ANCIL_1_REG_END                           0x00699528
+#define BCHP_GSE_ANCIL_0_REG_START                         0x00699600
+#define BCHP_GSE_ANCIL_0_REG_END                           0x00699680
+#define BCHP_GSE_ANCIL_1_REG_START                         0x00699700
+#define BCHP_GSE_ANCIL_1_REG_END                           0x00699780
+#define BCHP_AMOLE_ANCIL_0_REG_START                       0x00699800
+#define BCHP_AMOLE_ANCIL_0_REG_END                         0x0069988c
+#define BCHP_AMOLE_ANCIL_1_REG_START                       0x00699900
+#define BCHP_AMOLE_ANCIL_1_REG_END                         0x0069998c
+#define BCHP_ANCI656_ANCIL_0_REG_START                     0x00699a00
+#define BCHP_ANCI656_ANCIL_0_REG_END                       0x00699a24
+#define BCHP_ANCI656_ANCIL_1_REG_START                     0x00699b00
+#define BCHP_ANCI656_ANCIL_1_REG_END                       0x00699b24
+#define BCHP_DVP_HT_REG_START                              0x006a0000
+#define BCHP_DVP_HT_REG_END                                0x006a010c
+#define BCHP_HDMI_REG_START                                0x006a0800
+#define BCHP_HDMI_REG_END                                  0x006a0994
+#define BCHP_HDMI_TX_PHY_REG_START                         0x006a0a80
+#define BCHP_HDMI_TX_PHY_REG_END                           0x006a0ad8
+#define BCHP_HDMI_RM_REG_START                             0x006a0b00
+#define BCHP_HDMI_RM_REG_END                               0x006a0b2c
+#define BCHP_HDMI_TX_INTR2_REG_START                       0x006a0b40
+#define BCHP_HDMI_TX_INTR2_REG_END                         0x006a0b6c
+#define BCHP_HDMI_RAM_REG_START                            0x006a0c00
+#define BCHP_HDMI_RAM_REG_END                              0x006a0dfc
+#define BCHP_DVP_HR_REG_START                              0x006a6000
+#define BCHP_DVP_HR_REG_END                                0x006a61bc
+#define BCHP_DVP_HR_INTR2_REG_START                        0x006a61c0
+#define BCHP_DVP_HR_INTR2_REG_END                          0x006a61ec
+#define BCHP_DVP_HR_DVP_OTP_REG_START                      0x006a6200
+#define BCHP_DVP_HR_DVP_OTP_REG_END                        0x006a6240
+#define BCHP_DVP_HR_KEY_RAM_REG_START                      0x006a6300
+#define BCHP_DVP_HR_KEY_RAM_REG_END                        0x006a6314
+#define BCHP_HDMI_RX_FE_0_REG_START                        0x006a6400
+#define BCHP_HDMI_RX_FE_0_REG_END                          0x006a65fc
+#define BCHP_HDMI_RX_EQ_0_REG_START                        0x006a6600
+#define BCHP_HDMI_RX_EQ_0_REG_END                          0x006a67f0
+#define BCHP_HDMI_RX_0_REG_START                           0x006a8000
+#define BCHP_HDMI_RX_0_REG_END                             0x006a887c
+#define BCHP_HDMI_RX_INTR2_0_REG_START                     0x006a8880
+#define BCHP_HDMI_RX_INTR2_0_REG_END                       0x006a88ac
+#define BCHP_HD_DVI_0_REG_START                            0x006aa000
+#define BCHP_HD_DVI_0_REG_END                              0x006aa1fc
+#define BCHP_DVP_HR_TMR_REG_START                          0x006aacc0
+#define BCHP_DVP_HR_TMR_REG_END                            0x006aacfc
+#define BCHP_BVN_RGR_REG_START                             0x006ae000
+#define BCHP_BVN_RGR_REG_END                               0x006ae010
+#define BCHP_VICE2_CME_0_REG_START                         0x00700800
+#define BCHP_VICE2_CME_0_REG_END                           0x0070089c
+#define BCHP_VICE2_FME_0_REG_START                         0x00700c00
+#define BCHP_VICE2_FME_0_REG_END                           0x00700c80
+#define BCHP_VICE2_MC_0_REG_START                          0x00701000
+#define BCHP_VICE2_MC_0_REG_END                            0x00701080
+#define BCHP_VICE2_MAU_0_REG_START                         0x00701400
+#define BCHP_VICE2_MAU_0_REG_END                           0x007014f4
+#define BCHP_VICE2_IMD_0_REG_START                         0x00701800
+#define BCHP_VICE2_IMD_0_REG_END                           0x0070187c
+#define BCHP_VICE2_CABAC_0_REG_START                       0x00701c00
+#define BCHP_VICE2_CABAC_0_REG_END                         0x00701cec
+#define BCHP_VICE2_HA_0_REG_START                          0x00702000
+#define BCHP_VICE2_HA_0_REG_END                            0x00702088
+#define BCHP_VICE2_SG_0_REG_START                          0x00702400
+#define BCHP_VICE2_SG_0_REG_END                            0x00702474
+#define BCHP_VICE2_DBLK_0_REG_START                        0x00702800
+#define BCHP_VICE2_DBLK_0_REG_END                          0x00702888
+#define BCHP_VICE2_VIP_0_REG_START                         0x00703000
+#define BCHP_VICE2_VIP_0_REG_END                           0x00703224
+#define BCHP_VICE2_VIP1_0_REG_START                        0x00703800
+#define BCHP_VICE2_VIP1_0_REG_END                          0x00703a24
+#define BCHP_VICE2_XQ_0_REG_START                          0x00704000
+#define BCHP_VICE2_XQ_0_REG_END                            0x00706198
+#define BCHP_VICE2_ARCSS_ESS_CTRL_0_REG_START              0x00710000
+#define BCHP_VICE2_ARCSS_ESS_CTRL_0_REG_END                0x007100a0
+#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_0_REG_START        0x00710400
+#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_0_REG_END          0x0071042c
+#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_0_REG_START          0x00710600
+#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_0_REG_END            0x0071062c
+#define BCHP_VICE2_ARCSS_ESS_HOSTIF_0_REG_START            0x00712000
+#define BCHP_VICE2_ARCSS_ESS_HOSTIF_0_REG_END              0x007133fc
+#define BCHP_VICE2_ARCSS_ESS_DCCM_0_REG_START              0x00714000
+#define BCHP_VICE2_ARCSS_ESS_DCCM_0_REG_END                0x00717ffc
+#define BCHP_VICE2_ARCSS_ESS_ADI_0_REG_START               0x00718000
+#define BCHP_VICE2_ARCSS_ESS_ADI_0_REG_END                 0x007182ac
+#define BCHP_VICE2_ARCSS_ESS_CTRL_1_REG_START              0x00750000
+#define BCHP_VICE2_ARCSS_ESS_CTRL_1_REG_END                0x007500a0
+#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_1_REG_START        0x00750400
+#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_1_REG_END          0x0075042c
+#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_1_REG_START          0x00750600
+#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_1_REG_END            0x0075062c
+#define BCHP_VICE2_ARCSS_ESS_HOSTIF_1_REG_START            0x00752000
+#define BCHP_VICE2_ARCSS_ESS_HOSTIF_1_REG_END              0x007533fc
+#define BCHP_VICE2_ARCSS_ESS_DCCM_1_REG_START              0x00754000
+#define BCHP_VICE2_ARCSS_ESS_DCCM_1_REG_END                0x00757ffc
+#define BCHP_VICE2_ARCSS_ESS_ADI_1_REG_START               0x00758000
+#define BCHP_VICE2_ARCSS_ESS_ADI_1_REG_END                 0x007582a4
+#define BCHP_VICE2_RGR_REG_START                           0x00780000
+#define BCHP_VICE2_RGR_REG_END                             0x0078000c
+#define BCHP_VICE2_MISC_REG_START                          0x00781000
+#define BCHP_VICE2_MISC_REG_END                            0x00781020
+#define BCHP_VICE2_L2_REG_START                            0x00781100
+#define BCHP_VICE2_L2_REG_END                              0x0078112c
+#define BCHP_VICE2_ARCSS_MISC_REG_START                    0x00782000
+#define BCHP_VICE2_ARCSS_MISC_REG_END                      0x00782030
+#define BCHP_VICE2_SEC_CTRL_REG_START                      0x00800000
+#define BCHP_VICE2_SEC_CTRL_REG_END                        0x00800080
+#define BCHP_XPT_BUS_IF_REG_START                          0x00900000
+#define BCHP_XPT_BUS_IF_REG_END                            0x00900078
+#define BCHP_XPT_XMEMIF_REG_START                          0x00900100
+#define BCHP_XPT_XMEMIF_REG_END                            0x009001a0
+#define BCHP_XPT_PMU_REG_START                             0x00900200
+#define BCHP_XPT_PMU_REG_END                               0x00900208
+#define BCHP_XPT_GR_REG_START                              0x00900300
+#define BCHP_XPT_GR_REG_END                                0x0090030c
+#define BCHP_XPT_RMX0_IO_REG_START                         0x00900400
+#define BCHP_XPT_RMX0_IO_REG_END                           0x00900420
+#define BCHP_XPT_RMX1_IO_REG_START                         0x00900500
+#define BCHP_XPT_RMX1_IO_REG_END                           0x00900520
+#define BCHP_XPT_WAKEUP_REG_START                          0x00901000
+#define BCHP_XPT_WAKEUP_REG_END                            0x00901fbc
+#define BCHP_XPT_FE_REG_START                              0x00904000
+#define BCHP_XPT_FE_REG_END                                0x009057fc
+#define BCHP_XPT_DPCR0_REG_START                           0x00907000
+#define BCHP_XPT_DPCR0_REG_END                             0x00907074
+#define BCHP_XPT_DPCR1_REG_START                           0x00907080
+#define BCHP_XPT_DPCR1_REG_END                             0x009070f4
+#define BCHP_XPT_DPCR2_REG_START                           0x00907100
+#define BCHP_XPT_DPCR2_REG_END                             0x00907174
+#define BCHP_XPT_DPCR3_REG_START                           0x00907180
+#define BCHP_XPT_DPCR3_REG_END                             0x009071f4
+#define BCHP_XPT_DPCR4_REG_START                           0x00907200
+#define BCHP_XPT_DPCR4_REG_END                             0x00907274
+#define BCHP_XPT_DPCR5_REG_START                           0x00907280
+#define BCHP_XPT_DPCR5_REG_END                             0x009072f4
+#define BCHP_XPT_DPCR6_REG_START                           0x00907300
+#define BCHP_XPT_DPCR6_REG_END                             0x00907374
+#define BCHP_XPT_DPCR7_REG_START                           0x00907380
+#define BCHP_XPT_DPCR7_REG_END                             0x009073f4
+#define BCHP_XPT_DPCR_PP_REG_START                         0x00907400
+#define BCHP_XPT_DPCR_PP_REG_END                           0x00907404
+#define BCHP_XPT_PSUB_REG_START                            0x00907a00
+#define BCHP_XPT_PSUB_REG_END                              0x00907ac8
+#define BCHP_XPT_MPOD_REG_START                            0x00907c00
+#define BCHP_XPT_MPOD_REG_END                              0x00907c20
+#define BCHP_XPT_RMX0_REG_START                            0x00907d00
+#define BCHP_XPT_RMX0_REG_END                              0x00907d08
+#define BCHP_XPT_RMX1_REG_START                            0x00907e00
+#define BCHP_XPT_RMX1_REG_END                              0x00907e08
+#define BCHP_XPT_PB_TOP_REG_START                          0x00908000
+#define BCHP_XPT_PB_TOP_REG_END                            0x00908084
+#define BCHP_XPT_PB0_REG_START                             0x00908100
+#define BCHP_XPT_PB0_REG_END                               0x00908174
+#define BCHP_XPT_PB1_REG_START                             0x00908180
+#define BCHP_XPT_PB1_REG_END                               0x009081f4
+#define BCHP_XPT_PB2_REG_START                             0x00908200
+#define BCHP_XPT_PB2_REG_END                               0x00908274
+#define BCHP_XPT_PB3_REG_START                             0x00908280
+#define BCHP_XPT_PB3_REG_END                               0x009082f4
+#define BCHP_XPT_PB4_REG_START                             0x00908300
+#define BCHP_XPT_PB4_REG_END                               0x00908374
+#define BCHP_XPT_PB5_REG_START                             0x00908380
+#define BCHP_XPT_PB5_REG_END                               0x009083f4
+#define BCHP_XPT_PB6_REG_START                             0x00908400
+#define BCHP_XPT_PB6_REG_END                               0x00908474
+#define BCHP_XPT_PB7_REG_START                             0x00908480
+#define BCHP_XPT_PB7_REG_END                               0x009084f4
+#define BCHP_XPT_PB8_REG_START                             0x00908500
+#define BCHP_XPT_PB8_REG_END                               0x00908574
+#define BCHP_XPT_PB9_REG_START                             0x00908580
+#define BCHP_XPT_PB9_REG_END                               0x009085f4
+#define BCHP_XPT_PB10_REG_START                            0x00908600
+#define BCHP_XPT_PB10_REG_END                              0x00908674
+#define BCHP_XPT_PB11_REG_START                            0x00908680
+#define BCHP_XPT_PB11_REG_END                              0x009086f4
+#define BCHP_XPT_PB12_REG_START                            0x00908700
+#define BCHP_XPT_PB12_REG_END                              0x00908774
+#define BCHP_XPT_PB13_REG_START                            0x00908780
+#define BCHP_XPT_PB13_REG_END                              0x009087f4
+#define BCHP_XPT_PB14_REG_START                            0x00908800
+#define BCHP_XPT_PB14_REG_END                              0x00908874
+#define BCHP_XPT_PB15_REG_START                            0x00908880
+#define BCHP_XPT_PB15_REG_END                              0x009088f4
+#define BCHP_XPT_PCROFFSET_REG_START                       0x0090c000
+#define BCHP_XPT_PCROFFSET_REG_END                         0x0090d8fc
+#define BCHP_XPT_FULL_PID_PARSER_REG_START                 0x00910000
+#define BCHP_XPT_FULL_PID_PARSER_REG_END                   0x00912050
+#define BCHP_XPT_RSBUFF_REG_START                          0x00915000
+#define BCHP_XPT_RSBUFF_REG_END                            0x00915b44
+#define BCHP_XPT_XCBUFF_REG_START                          0x00916000
+#define BCHP_XPT_XCBUFF_REG_END                            0x00917ccc
+#define BCHP_XPT_MSG_REG_START                             0x00918000
+#define BCHP_XPT_MSG_REG_END                               0x0091e014
+#define BCHP_XPT_RAVE_REG_START                            0x00920000
+#define BCHP_XPT_RAVE_REG_END                              0x0092c79c
+#define BCHP_XPT_XPU_REG_START                             0x00930000
+#define BCHP_XPT_XPU_REG_END                               0x009347fc
+#define BCHP_XPT_SECURE_BUS_IF_REG_START                   0x0093f000
+#define BCHP_XPT_SECURE_BUS_IF_REG_END                     0x0093f000
+#define BCHP_DECODE_RBNODE_REGS_0_REG_START                0x00a00000
+#define BCHP_DECODE_RBNODE_REGS_0_REG_END                  0x00a0007c
+#define BCHP_DECODE_MAIN_0_REG_START                       0x00a00100
+#define BCHP_DECODE_MAIN_0_REG_END                         0x00a001fc
+#define BCHP_SDRAM_DEBUG_0_REG_START                       0x00a00200
+#define BCHP_SDRAM_DEBUG_0_REG_END                         0x00a0027c
+#define BCHP_DECODE_MCOM_0_REG_START                       0x00a00300
+#define BCHP_DECODE_MCOM_0_REG_END                         0x00a0031c
+#define BCHP_DECODE_SPRE_0_REG_START                       0x00a00320
+#define BCHP_DECODE_SPRE_0_REG_END                         0x00a0033c
+#define BCHP_DECODE_WPRD_0_REG_START                       0x00a00340
+#define BCHP_DECODE_WPRD_0_REG_END                         0x00a0035c
+#define BCHP_DECODE_DQNT_0_REG_START                       0x00a00400
+#define BCHP_DECODE_DQNT_0_REG_END                         0x00a0045c
+#define BCHP_DECODE_DQNT_8X8_0_REG_START                   0x00a00500
+#define BCHP_DECODE_DQNT_8X8_0_REG_END                     0x00a0057c
+#define BCHP_DECODE_VP8_XFRM_0_REG_START                   0x00a00600
+#define BCHP_DECODE_VP8_XFRM_0_REG_END                     0x00a0060c
+#define BCHP_DECODE_XFRM_0_REG_START                       0x00a00700
+#define BCHP_DECODE_XFRM_0_REG_END                         0x00a0071c
+#define BCHP_DECODE_DBLK_0_REG_START                       0x00a00720
+#define BCHP_DECODE_DBLK_0_REG_END                         0x00a0073c
+#define BCHP_DECODE_MB_0_REG_START                         0x00a00740
+#define BCHP_DECODE_MB_0_REG_END                           0x00a0075c
+#define BCHP_REG_CABAC2BINS_0_REG_START                    0x00a00b00
+#define BCHP_REG_CABAC2BINS_0_REG_END                      0x00a00bfc
+#define BCHP_DECODE_SINT_0_REG_START                       0x00a00c00
+#define BCHP_DECODE_SINT_0_REG_END                         0x00a00dfc
+#define BCHP_DECODE_RVC_0_REG_START                        0x00a00e00
+#define BCHP_DECODE_RVC_0_REG_END                          0x00a00efc
+#define BCHP_DECODE_CPUREGS_0_REG_START                    0x00a00f00
+#define BCHP_DECODE_CPUREGS_0_REG_END                      0x00a00f7c
+#define BCHP_DECODE_CPUREGS2_0_REG_START                   0x00a00f80
+#define BCHP_DECODE_CPUREGS2_0_REG_END                     0x00a00ffc
+#define BCHP_DECODE_CPUDMA_0_REG_START                     0x00a01800
+#define BCHP_DECODE_CPUDMA_0_REG_END                       0x00a018fc
+#define BCHP_DECODE_DMAMEM_0_REG_START                     0x00a01a00
+#define BCHP_DECODE_DMAMEM_0_REG_END                       0x00a021fc
+#define BCHP_REG_CABAC2BINS2_0_REG_START                   0x00a02400
+#define BCHP_REG_CABAC2BINS2_0_REG_END                     0x00a027fc
+#define BCHP_DECODE_WPTBL_0_REG_START                      0x00a03000
+#define BCHP_DECODE_WPTBL_0_REG_END                        0x00a031fc
+#define BCHP_DECODE_SINT_OLOOP_0_REG_START                 0x00a0cc00
+#define BCHP_DECODE_SINT_OLOOP_0_REG_END                   0x00a0ccfc
+#define BCHP_DECODE_SD_0_REG_START                         0x00a40800
+#define BCHP_DECODE_SD_0_REG_END                           0x00a40ffc
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_START             0x00a41000
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_END               0x00a4107c
+#define BCHP_DECODE_CPUCORE_0_REG_START                    0x00a44000
+#define BCHP_DECODE_CPUCORE_0_REG_END                      0x00a44ffc
+#define BCHP_DECODE_CPUAUX_0_REG_START                     0x00a45000
+#define BCHP_DECODE_CPUAUX_0_REG_END                       0x00a45ffc
+#define BCHP_DECODE_CPUIMEM_0_REG_START                    0x00a46000
+#define BCHP_DECODE_CPUIMEM_0_REG_END                      0x00a47ffc
+#define BCHP_DECODE_CPUDMEM_0_REG_START                    0x00a48000
+#define BCHP_DECODE_CPUDMEM_0_REG_END                      0x00a4fffc
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_START            0x00a51000
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_END              0x00a5107c
+#define BCHP_DECODE_CPUDMA2_0_REG_START                    0x00a51800
+#define BCHP_DECODE_CPUDMA2_0_REG_END                      0x00a518fc
+#define BCHP_DECODE_DMAMEM2_0_REG_START                    0x00a51a00
+#define BCHP_DECODE_DMAMEM2_0_REG_END                      0x00a521fc
+#define BCHP_DECODE_CPUCORE2_0_REG_START                   0x00a54000
+#define BCHP_DECODE_CPUCORE2_0_REG_END                     0x00a54ffc
+#define BCHP_DECODE_CPUAUX2_0_REG_START                    0x00a55000
+#define BCHP_DECODE_CPUAUX2_0_REG_END                      0x00a55ffc
+#define BCHP_DECODE_CPUIMEM2_0_REG_START                   0x00a56000
+#define BCHP_DECODE_CPUIMEM2_0_REG_END                     0x00a57ffc
+#define BCHP_DECODE_CPUDMEM2_0_REG_START                   0x00a58000
+#define BCHP_DECODE_CPUDMEM2_0_REG_END                     0x00a5fffc
+#define BCHP_DECODE_IP_SHIM_0_REG_START                    0x00a60000
+#define BCHP_DECODE_IP_SHIM_0_REG_END                      0x00a60084
+#define BCHP_AVD_CACHE_0_REG_START                         0x00a62000
+#define BCHP_AVD_CACHE_0_REG_END                           0x00a6203c
+#define BCHP_ILS_REGS_0_REG_START                          0x00a70000
+#define BCHP_ILS_REGS_0_REG_END                            0x00a7007c
+#define BCHP_ILS_SCALE_ADDR_0_REG_START                    0x00a70100
+#define BCHP_ILS_SCALE_ADDR_0_REG_END                      0x00a7010c
+#define BCHP_ILS_SPSCALE_FILL_0_REG_START                  0x00a70180
+#define BCHP_ILS_SPSCALE_FILL_0_REG_END                    0x00a70180
+#define BCHP_ILS_MVSCALE_0_REG_START                       0x00a70200
+#define BCHP_ILS_MVSCALE_0_REG_END                         0x00a7038c
+#define BCHP_SVD_INTR2_0_REG_START                         0x00a80000
+#define BCHP_SVD_INTR2_0_REG_END                           0x00a8002c
+#define BCHP_SVD_RGR_0_REG_START                           0x00a80400
+#define BCHP_SVD_RGR_0_REG_END                             0x00a80410
+#define BCHP_BLD_DECODE_RBNODE_REGS_0_REG_START            0x00b00000
+#define BCHP_BLD_DECODE_RBNODE_REGS_0_REG_END              0x00b0007c
+#define BCHP_BLD_DECODE_MAIN_0_REG_START                   0x00b00100
+#define BCHP_BLD_DECODE_MAIN_0_REG_END                     0x00b001fc
+#define BCHP_BLD_SDRAM_DEBUG_0_REG_START                   0x00b00200
+#define BCHP_BLD_SDRAM_DEBUG_0_REG_END                     0x00b0027c
+#define BCHP_BLD_DECODE_MCOM_0_REG_START                   0x00b00300
+#define BCHP_BLD_DECODE_MCOM_0_REG_END                     0x00b0031c
+#define BCHP_BLD_DECODE_SPRE_0_REG_START                   0x00b00320
+#define BCHP_BLD_DECODE_SPRE_0_REG_END                     0x00b0033c
+#define BCHP_BLD_DECODE_WPRD_0_REG_START                   0x00b00340
+#define BCHP_BLD_DECODE_WPRD_0_REG_END                     0x00b0035c
+#define BCHP_BLD_DECODE_DQNT_0_REG_START                   0x00b00400
+#define BCHP_BLD_DECODE_DQNT_0_REG_END                     0x00b0045c
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_START               0x00b00500
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_END                 0x00b0057c
+#define BCHP_BLD_DECODE_VP8_XFRM_0_REG_START               0x00b00600
+#define BCHP_BLD_DECODE_VP8_XFRM_0_REG_END                 0x00b0060c
+#define BCHP_BLD_DECODE_XFRM_0_REG_START                   0x00b00700
+#define BCHP_BLD_DECODE_XFRM_0_REG_END                     0x00b0071c
+#define BCHP_BLD_DECODE_DBLK_0_REG_START                   0x00b00720
+#define BCHP_BLD_DECODE_DBLK_0_REG_END                     0x00b0073c
+#define BCHP_BLD_DECODE_MB_0_REG_START                     0x00b00740
+#define BCHP_BLD_DECODE_MB_0_REG_END                       0x00b0075c
+#define BCHP_BLD_REG_CABAC2BINS_0_REG_START                0x00b00b00
+#define BCHP_BLD_REG_CABAC2BINS_0_REG_END                  0x00b00bfc
+#define BCHP_BLD_DECODE_SINT_0_REG_START                   0x00b00c00
+#define BCHP_BLD_DECODE_SINT_0_REG_END                     0x00b00dfc
+#define BCHP_BLD_DECODE_RVC_0_REG_START                    0x00b00e00
+#define BCHP_BLD_DECODE_RVC_0_REG_END                      0x00b00efc
+#define BCHP_BLD_DECODE_CPUREGS_0_REG_START                0x00b00f00
+#define BCHP_BLD_DECODE_CPUREGS_0_REG_END                  0x00b00f7c
+#define BCHP_BLD_DECODE_CPUREGS2_0_REG_START               0x00b00f80
+#define BCHP_BLD_DECODE_CPUREGS2_0_REG_END                 0x00b00ffc
+#define BCHP_BLD_DECODE_CPUDMA_0_REG_START                 0x00b01800
+#define BCHP_BLD_DECODE_CPUDMA_0_REG_END                   0x00b018fc
+#define BCHP_BLD_DECODE_DMAMEM_0_REG_START                 0x00b01a00
+#define BCHP_BLD_DECODE_DMAMEM_0_REG_END                   0x00b021fc
+#define BCHP_BLD_REG_CABAC2BINS2_0_REG_START               0x00b02400
+#define BCHP_BLD_REG_CABAC2BINS2_0_REG_END                 0x00b027fc
+#define BCHP_BLD_DECODE_WPTBL_0_REG_START                  0x00b03000
+#define BCHP_BLD_DECODE_WPTBL_0_REG_END                    0x00b031fc
+#define BCHP_BLD_DECODE_SINT_OLOOP_0_REG_START             0x00b0cc00
+#define BCHP_BLD_DECODE_SINT_OLOOP_0_REG_END               0x00b0ccfc
+#define BCHP_BLD_DECODE_SD_0_REG_START                     0x00b40800
+#define BCHP_BLD_DECODE_SD_0_REG_END                       0x00b40ffc
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS_0_REG_START         0x00b41000
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS_0_REG_END           0x00b4107c
+#define BCHP_BLD_DECODE_CPUCORE_0_REG_START                0x00b44000
+#define BCHP_BLD_DECODE_CPUCORE_0_REG_END                  0x00b44ffc
+#define BCHP_BLD_DECODE_CPUAUX_0_REG_START                 0x00b45000
+#define BCHP_BLD_DECODE_CPUAUX_0_REG_END                   0x00b45ffc
+#define BCHP_BLD_DECODE_CPUIMEM_0_REG_START                0x00b46000
+#define BCHP_BLD_DECODE_CPUIMEM_0_REG_END                  0x00b47ffc
+#define BCHP_BLD_DECODE_CPUDMEM_0_REG_START                0x00b48000
+#define BCHP_BLD_DECODE_CPUDMEM_0_REG_END                  0x00b4fffc
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS2_0_REG_START        0x00b51000
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS2_0_REG_END          0x00b5107c
+#define BCHP_BLD_DECODE_CPUDMA2_0_REG_START                0x00b51800
+#define BCHP_BLD_DECODE_CPUDMA2_0_REG_END                  0x00b518fc
+#define BCHP_BLD_DECODE_DMAMEM2_0_REG_START                0x00b51a00
+#define BCHP_BLD_DECODE_DMAMEM2_0_REG_END                  0x00b521fc
+#define BCHP_BLD_DECODE_CPUCORE2_0_REG_START               0x00b54000
+#define BCHP_BLD_DECODE_CPUCORE2_0_REG_END                 0x00b54ffc
+#define BCHP_BLD_DECODE_CPUAUX2_0_REG_START                0x00b55000
+#define BCHP_BLD_DECODE_CPUAUX2_0_REG_END                  0x00b55ffc
+#define BCHP_BLD_DECODE_CPUIMEM2_0_REG_START               0x00b56000
+#define BCHP_BLD_DECODE_CPUIMEM2_0_REG_END                 0x00b57ffc
+#define BCHP_BLD_DECODE_CPUDMEM2_0_REG_START               0x00b58000
+#define BCHP_BLD_DECODE_CPUDMEM2_0_REG_END                 0x00b5fffc
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_START                0x00b60000
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_END                  0x00b60084
+#define BCHP_BLD_AVD_CACHE_0_REG_START                     0x00b62000
+#define BCHP_BLD_AVD_CACHE_0_REG_END                       0x00b6203c
+#define BCHP_VICH_0_REG_START                              0x00b70000
+#define BCHP_VICH_0_REG_END                                0x00b7008b
+#define BCHP_GENET_0_SYS_REG_START                         0x00b80000
+#define BCHP_GENET_0_SYS_REG_END                           0x00b8000c
+#define BCHP_GENET_0_GR_BRIDGE_REG_START                   0x00b80040
+#define BCHP_GENET_0_GR_BRIDGE_REG_END                     0x00b8004c
+#define BCHP_GENET_0_EXT_REG_START                         0x00b80080
+#define BCHP_GENET_0_EXT_REG_END                           0x00b80098
+#define BCHP_GENET_0_INTRL2_0_REG_START                    0x00b80200
+#define BCHP_GENET_0_INTRL2_0_REG_END                      0x00b8022c
+#define BCHP_GENET_0_INTRL2_1_REG_START                    0x00b80240
+#define BCHP_GENET_0_INTRL2_1_REG_END                      0x00b8026c
+#define BCHP_GENET_0_RBUF_REG_START                        0x00b80300
+#define BCHP_GENET_0_RBUF_REG_END                          0x00b803b4
+#define BCHP_GENET_0_TBUF_REG_START                        0x00b80600
+#define BCHP_GENET_0_TBUF_REG_END                          0x00b80628
+#define BCHP_GENET_0_UMAC_REG_START                        0x00b80800
+#define BCHP_GENET_0_UMAC_REG_END                          0x00b80ed8
+#define BCHP_GENET_0_HFB_REG_START                         0x00b88000
+#define BCHP_GENET_0_HFB_REG_END                           0x00b8fc48
+#define BCHP_GENET_0_RDMA_REG_START                        0x00b90000
+#define BCHP_GENET_0_RDMA_REG_END                          0x00b90cd4
+#define BCHP_GENET_0_TDMA_REG_START                        0x00b91000
+#define BCHP_GENET_0_TDMA_REG_END                          0x00b91c84
+#define BCHP_GENET_1_SYS_REG_START                         0x00ba0000
+#define BCHP_GENET_1_SYS_REG_END                           0x00ba000c
+#define BCHP_GENET_1_GR_BRIDGE_REG_START                   0x00ba0040
+#define BCHP_GENET_1_GR_BRIDGE_REG_END                     0x00ba004c
+#define BCHP_GENET_1_EXT_REG_START                         0x00ba0080
+#define BCHP_GENET_1_EXT_REG_END                           0x00ba0098
+#define BCHP_GENET_1_INTRL2_0_REG_START                    0x00ba0200
+#define BCHP_GENET_1_INTRL2_0_REG_END                      0x00ba022c
+#define BCHP_GENET_1_INTRL2_1_REG_START                    0x00ba0240
+#define BCHP_GENET_1_INTRL2_1_REG_END                      0x00ba026c
+#define BCHP_GENET_1_RBUF_REG_START                        0x00ba0300
+#define BCHP_GENET_1_RBUF_REG_END                          0x00ba03b4
+#define BCHP_GENET_1_TBUF_REG_START                        0x00ba0600
+#define BCHP_GENET_1_TBUF_REG_END                          0x00ba0628
+#define BCHP_GENET_1_UMAC_REG_START                        0x00ba0800
+#define BCHP_GENET_1_UMAC_REG_END                          0x00ba0ed8
+#define BCHP_GENET_1_HFB_REG_START                         0x00ba8000
+#define BCHP_GENET_1_HFB_REG_END                           0x00bafc48
+#define BCHP_GENET_1_RDMA_REG_START                        0x00bb0000
+#define BCHP_GENET_1_RDMA_REG_END                          0x00bb0cd4
+#define BCHP_GENET_1_TDMA_REG_START                        0x00bb1000
+#define BCHP_GENET_1_TDMA_REG_END                          0x00bb1c84
+#define BCHP_SID_REG_START                                 0x00bc0100
+#define BCHP_SID_REG_END                                   0x00bc019c
+#define BCHP_SID_RLE_REG_START                             0x00bc0300
+#define BCHP_SID_RLE_REG_END                               0x00bc039c
+#define BCHP_SID_DQ_REG_START                              0x00bc0400
+#define BCHP_SID_DQ_REG_END                                0x00bc04bc
+#define BCHP_SID_STRM_REG_START                            0x00bc0800
+#define BCHP_SID_STRM_REG_END                              0x00bc087c
+#define BCHP_SID_OUTPUT_REG_START                          0x00bc0c00
+#define BCHP_SID_OUTPUT_REG_END                            0x00bc0c40
+#define BCHP_SID_ARC_REG_START                             0x00bc0f00
+#define BCHP_SID_ARC_REG_END                               0x00bc0f3c
+#define BCHP_SID_ARCDMA_REG_START                          0x00bc1800
+#define BCHP_SID_ARCDMA_REG_END                            0x00bc1840
+#define BCHP_SID_DMARAM_REG_START                          0x00bc1a00
+#define BCHP_SID_DMARAM_REG_END                            0x00bc1bfc
+#define BCHP_SID_PEEK_BITS_REG_START                       0x00bc2b00
+#define BCHP_SID_PEEK_BITS_REG_END                         0x00bc2b3c
+#define BCHP_SID_EXTRACT_BITS_REG_START                    0x00bc2b40
+#define BCHP_SID_EXTRACT_BITS_REG_END                      0x00bc2b7c
+#define BCHP_SID_HUFF_SYMB_REG_START                       0x00bc3000
+#define BCHP_SID_HUFF_SYMB_REG_END                         0x00bc37fc
+#define BCHP_SID_HUFF_CODE_REG_START                       0x00bc3900
+#define BCHP_SID_HUFF_CODE_REG_END                         0x00bc39fc
+#define BCHP_SID_SYMB_REG_START                            0x00bc3a00
+#define BCHP_SID_SYMB_REG_END                              0x00bc3a10
+#define BCHP_SID_SYMB_JPEG_REG_START                       0x00bc3a80
+#define BCHP_SID_SYMB_JPEG_REG_END                         0x00bc3a8c
+#define BCHP_SID_BIGRAM_REG_START                          0x00bc8000
+#define BCHP_SID_BIGRAM_REG_END                            0x00bcfffc
+#define BCHP_SID_ARC_DBG_REG_START                         0x00bd1000
+#define BCHP_SID_ARC_DBG_REG_END                           0x00bd1010
+#define BCHP_SID_ARC_CORE_REG_START                        0x00bd5000
+#define BCHP_SID_ARC_CORE_REG_END                          0x00bd5014
+#define BCHP_M2MC_REG_START                                0x00be0000
+#define BCHP_M2MC_REG_END                                  0x00be07fc
+#define BCHP_GFX_L2_REG_START                              0x00be3000
+#define BCHP_GFX_L2_REG_END                                0x00be302c
+#define BCHP_GFX_GR_REG_START                              0x00be4000
+#define BCHP_GFX_GR_REG_END                                0x00be400c
+#define BCHP_SICH_REG_START                                0x00be8000
+#define BCHP_SICH_REG_END                                  0x00be803c
+#define BCHP_V3D_CTL_REG_START                             0x00bea000
+#define BCHP_V3D_CTL_REG_END                               0x00bea040
+#define BCHP_V3D_CLE_REG_START                             0x00bea100
+#define BCHP_V3D_CLE_REG_END                               0x00bea138
+#define BCHP_V3D_PTB_REG_START                             0x00bea300
+#define BCHP_V3D_PTB_REG_END                               0x00bea310
+#define BCHP_V3D_QPS_REG_START                             0x00bea400
+#define BCHP_V3D_QPS_REG_END                               0x00bea43c
+#define BCHP_V3D_VPM_REG_START                             0x00bea500
+#define BCHP_V3D_VPM_REG_END                               0x00bea504
+#define BCHP_V3D_PCTR_REG_START                            0x00bea600
+#define BCHP_V3D_PCTR_REG_END                              0x00bea6fc
+#define BCHP_V3D_TOP_GR_BRIDGE_REG_START                   0x00bea800
+#define BCHP_V3D_TOP_GR_BRIDGE_REG_END                     0x00bea80c
+#define BCHP_V3D_GCA_REG_START                             0x00beaa00
+#define BCHP_V3D_GCA_REG_END                               0x00beaa54
+#define BCHP_V3D_DBG_REG_START                             0x00beae00
+#define BCHP_V3D_DBG_REG_END                               0x00beaf20
+#define BCHP_RAAGA_DSP_RGR_REG_START                       0x00c00000
+#define BCHP_RAAGA_DSP_RGR_REG_END                         0x00c00008
+#define BCHP_RAAGA_DSP_MISC_REG_START                      0x00c20000
+#define BCHP_RAAGA_DSP_MISC_REG_END                        0x00c2044c
+#define BCHP_RAAGA_DSP_TIMERS_REG_START                    0x00c21000
+#define BCHP_RAAGA_DSP_TIMERS_REG_END                      0x00c21058
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START             0x00c21080
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END               0x00c2109c
+#define BCHP_RAAGA_DSP_PERI_SW_REG_START                   0x00c21100
+#define BCHP_RAAGA_DSP_PERI_SW_REG_END                     0x00c21154
+#define BCHP_RAAGA_DSP_DMA_REG_START                       0x00c21400
+#define BCHP_RAAGA_DSP_DMA_REG_END                         0x00c21664
+#define BCHP_RAAGA_DSP_ESR_SI_REG_START                    0x00c22000
+#define BCHP_RAAGA_DSP_ESR_SI_REG_END                      0x00c22014
+#define BCHP_RAAGA_DSP_INTH_REG_START                      0x00c22200
+#define BCHP_RAAGA_DSP_INTH_REG_END                        0x00c2222c
+#define BCHP_RAAGA_DSP_FW_INTH_REG_START                   0x00c22400
+#define BCHP_RAAGA_DSP_FW_INTH_REG_END                     0x00c2242c
+#define BCHP_RAAGA_DSP_FW_CFG_REG_START                    0x00c23000
+#define BCHP_RAAGA_DSP_FW_CFG_REG_END                      0x00c2357c
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START             0x00c30000
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END               0x00c3bffc
+#define BCHP_AIO_MISC_REG_START                            0x00c80000
+#define BCHP_AIO_MISC_REG_END                              0x00c80010
+#define BCHP_AIO_INTH_REG_START                            0x00c80100
+#define BCHP_AIO_INTH_REG_END                              0x00c8012c
+#define BCHP_AIO_INTD0_REG_START                           0x00c80200
+#define BCHP_AIO_INTD0_REG_END                             0x00c80214
+#define BCHP_AUD_FMM_MISC_REG_START                        0x00c80400
+#define BCHP_AUD_FMM_MISC_REG_END                          0x00c8050c
+#define BCHP_AUD_FMM_BF_CTRL_REG_START                     0x00c90000
+#define BCHP_AUD_FMM_BF_CTRL_REG_END                       0x00c90d3c
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_START                   0x00c91000
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_END                     0x00c91014
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_START                   0x00c91020
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_END                     0x00c91034
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_START                   0x00c91040
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_END                     0x00c91054
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_START                  0x00c91100
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_END                    0x00c91114
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_START                  0x00c91120
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_END                    0x00c91134
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_START                  0x00c91140
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_END                    0x00c91154
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_START                   0x00c92000
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_END                     0x00c92bfc
+#define BCHP_AUD_FMM_SRC_ESR0_REG_START                    0x00c93000
+#define BCHP_AUD_FMM_SRC_ESR0_REG_END                      0x00c93014
+#define BCHP_AUD_FMM_DP_CTRL0_REG_START                    0x00c94000
+#define BCHP_AUD_FMM_DP_CTRL0_REG_END                      0x00c9612c
+#define BCHP_AUD_FMM_DP_ESR0_H0_REG_START                  0x00c97c00
+#define BCHP_AUD_FMM_DP_ESR0_H0_REG_END                    0x00c97c14
+#define BCHP_AUD_FMM_DP_ESR1_H0_REG_START                  0x00c97c40
+#define BCHP_AUD_FMM_DP_ESR1_H0_REG_END                    0x00c97c54
+#define BCHP_AUD_FMM_DP_ESR0_D00_REG_START                 0x00c97c80
+#define BCHP_AUD_FMM_DP_ESR0_D00_REG_END                   0x00c97c94
+#define BCHP_AUD_FMM_DP_ESR1_D00_REG_START                 0x00c97cc0
+#define BCHP_AUD_FMM_DP_ESR1_D00_REG_END                   0x00c97cd4
+#define BCHP_AUD_FMM_IOP_CTRL_REG_START                    0x00c98000
+#define BCHP_AUD_FMM_IOP_CTRL_REG_END                      0x00c98148
+#define BCHP_AUD_FMM_IOP_ESR_REG_START                     0x00c98400
+#define BCHP_AUD_FMM_IOP_ESR_REG_END                       0x00c98414
+#define BCHP_SPDIF_RCVR_CTRL_REG_START                     0x00c99000
+#define BCHP_SPDIF_RCVR_CTRL_REG_END                       0x00c9907c
+#define BCHP_SPDIF_RCVR_ESR_REG_START                      0x00c99400
+#define BCHP_SPDIF_RCVR_ESR_REG_END                        0x00c99414
+#define BCHP_HDMI_RCVR_CTRL_REG_START                      0x00c99800
+#define BCHP_HDMI_RCVR_CTRL_REG_END                        0x00c9987c
+#define BCHP_HDMI_RCVR_ESR_REG_START                       0x00c99c00
+#define BCHP_HDMI_RCVR_ESR_REG_END                         0x00c99c14
+#define BCHP_AUD_FMM_OP_CTRL_REG_START                     0x00c9a000
+#define BCHP_AUD_FMM_OP_CTRL_REG_END                       0x00c9a1fc
+#define BCHP_AUD_FMM_OP_ESR_REG_START                      0x00c9a400
+#define BCHP_AUD_FMM_OP_ESR_REG_END                        0x00c9a414
+#define BCHP_AUD_FMM_OP_MCLKGEN_REG_START                  0x00c9a500
+#define BCHP_AUD_FMM_OP_MCLKGEN_REG_END                    0x00c9a564
+#define BCHP_AUD_FMM_PLL0_REG_START                        0x00c9a800
+#define BCHP_AUD_FMM_PLL0_REG_END                          0x00c9a834
+#define BCHP_AUD_FMM_PLL1_REG_START                        0x00c9a900
+#define BCHP_AUD_FMM_PLL1_REG_END                          0x00c9a934
+#define BCHP_AUD_FMM_PLL2_REG_START                        0x00c9aa00
+#define BCHP_AUD_FMM_PLL2_REG_END                          0x00c9aa34
+#define BCHP_HIFIDAC_CTRL0_REG_START                       0x00c9b000
+#define BCHP_HIFIDAC_CTRL0_REG_END                         0x00c9b1fc
+#define BCHP_HIFIDAC_RM0_REG_START                         0x00c9b200
+#define BCHP_HIFIDAC_RM0_REG_END                           0x00c9b224
+#define BCHP_HIFIDAC_ESR0_REG_START                        0x00c9b300
+#define BCHP_HIFIDAC_ESR0_REG_END                          0x00c9b314
+#define BCHP_HIFIDAC_CTRL1_REG_START                       0x00c9b400
+#define BCHP_HIFIDAC_CTRL1_REG_END                         0x00c9b5fc
+#define BCHP_HIFIDAC_RM1_REG_START                         0x00c9b600
+#define BCHP_HIFIDAC_RM1_REG_END                           0x00c9b624
+#define BCHP_HIFIDAC_ESR1_REG_START                        0x00c9b700
+#define BCHP_HIFIDAC_ESR1_REG_END                          0x00c9b714
+#define BCHP_AUD_FMM_MS_CTRL_REG_START                     0x00c9c000
+#define BCHP_AUD_FMM_MS_CTRL_REG_END                       0x00c9dbfc
+#define BCHP_AUD_FMM_MS_ESR_REG_START                      0x00c9e000
+#define BCHP_AUD_FMM_MS_ESR_REG_END                        0x00c9e014
+#define BCHP_RAAGA_DSP_SEC0_REG_START                      0x00d00000
+#define BCHP_RAAGA_DSP_SEC0_REG_END                        0x00d00000
+#define BCHP_DATA_MEM_REG_START                            0x00e00000
+#define BCHP_DATA_MEM_REG_END                              0x00e47ffc
+#define BCHP_CNTL_MEM_REG_START                            0x00f20000
+#define BCHP_CNTL_MEM_REG_END                              0x00f67ffc
+#define BCHP_DMA_AHB_ECL_CMD_SCH0_REG_START                0x00fc0000
+#define BCHP_DMA_AHB_ECL_CMD_SCH0_REG_END                  0x00fc0000
+#define BCHP_DMA_AHB_ECL_CMD_SCH1_REG_START                0x00fc0010
+#define BCHP_DMA_AHB_ECL_CMD_SCH1_REG_END                  0x00fc0010
+#define BCHP_DMA_AHB_ECL_CMD_SCH2_REG_START                0x00fc0020
+#define BCHP_DMA_AHB_ECL_CMD_SCH2_REG_END                  0x00fc0020
+#define BCHP_DMA_AHB_ECL_CMD_SCH3_REG_START                0x00fc0030
+#define BCHP_DMA_AHB_ECL_CMD_SCH3_REG_END                  0x00fc0030
+#define BCHP_DMA_AHB_ECL_CMD_SCH4_REG_START                0x00fc0040
+#define BCHP_DMA_AHB_ECL_CMD_SCH4_REG_END                  0x00fc0040
+#define BCHP_DMA_AHB_ECL_CMD_SCH5_REG_START                0x00fc0050
+#define BCHP_DMA_AHB_ECL_CMD_SCH5_REG_END                  0x00fc0050
+#define BCHP_DMA_AHB_ECL_CMD_SCH6_REG_START                0x00fc0060
+#define BCHP_DMA_AHB_ECL_CMD_SCH6_REG_END                  0x00fc0060
+#define BCHP_DMA_AHB_ECL_CMD_SCH7_REG_START                0x00fc0070
+#define BCHP_DMA_AHB_ECL_CMD_SCH7_REG_END                  0x00fc0070
+#define BCHP_DMA_AHB_ECL_CMD_SCH8_REG_START                0x00fc0080
+#define BCHP_DMA_AHB_ECL_CMD_SCH8_REG_END                  0x00fc0080
+#define BCHP_DMA_AHB_ECL_CMD_SCH9_REG_START                0x00fc0090
+#define BCHP_DMA_AHB_ECL_CMD_SCH9_REG_END                  0x00fc0090
+#define BCHP_DMA_AHB_ECL_CMD_SCH10_REG_START               0x00fc00a0
+#define BCHP_DMA_AHB_ECL_CMD_SCH10_REG_END                 0x00fc00a0
+#define BCHP_DMA_AHB_ECL_CMD_SCH11_REG_START               0x00fc00b0
+#define BCHP_DMA_AHB_ECL_CMD_SCH11_REG_END                 0x00fc00b0
+#define BCHP_DMA_AHB_ECL_CMD_SCH12_REG_START               0x00fc00c0
+#define BCHP_DMA_AHB_ECL_CMD_SCH12_REG_END                 0x00fc00c0
+#define BCHP_DMA_AHB_ECL_CMD_SCH13_REG_START               0x00fc00d0
+#define BCHP_DMA_AHB_ECL_CMD_SCH13_REG_END                 0x00fc00d0
+#define BCHP_DMA_AHB_ECL_CMD_SCH14_REG_START               0x00fc00e0
+#define BCHP_DMA_AHB_ECL_CMD_SCH14_REG_END                 0x00fc00e0
+#define BCHP_DMA_AHB_ECL_CMD_SCH15_REG_START               0x00fc00f0
+#define BCHP_DMA_AHB_ECL_CMD_SCH15_REG_END                 0x00fc00f0
+#define BCHP_DMA_AHB_ECL_CMD_SCH16_REG_START               0x00fc0100
+#define BCHP_DMA_AHB_ECL_CMD_SCH16_REG_END                 0x00fc0100
+#define BCHP_DMA_AHB_ECL_CMD_SCH17_REG_START               0x00fc0110
+#define BCHP_DMA_AHB_ECL_CMD_SCH17_REG_END                 0x00fc0110
+#define BCHP_DMA_AHB_ECL_CMD_SCH18_REG_START               0x00fc0120
+#define BCHP_DMA_AHB_ECL_CMD_SCH18_REG_END                 0x00fc0120
+#define BCHP_DMA_AHB_ECL_CMD_SCH19_REG_START               0x00fc0130
+#define BCHP_DMA_AHB_ECL_CMD_SCH19_REG_END                 0x00fc0130
+#define BCHP_DMA_AHB_ECL_CMD_RX_REG_START                  0x00fc0800
+#define BCHP_DMA_AHB_ECL_CMD_RX_REG_END                    0x00fc0800
+#define BCHP_DMA_AHB_CMD_RX_SCH0_REG_START                 0x00fc4000
+#define BCHP_DMA_AHB_CMD_RX_SCH0_REG_END                   0x00fc4000
+#define BCHP_DMA_AHB_CMD_RX_SCH1_REG_START                 0x00fc4010
+#define BCHP_DMA_AHB_CMD_RX_SCH1_REG_END                   0x00fc4010
+#define BCHP_DMA_AHB_CMD_RX_SCH2_REG_START                 0x00fc4020
+#define BCHP_DMA_AHB_CMD_RX_SCH2_REG_END                   0x00fc4020
+#define BCHP_DMA_AHB_CMD_RX_SCH3_REG_START                 0x00fc4030
+#define BCHP_DMA_AHB_CMD_RX_SCH3_REG_END                   0x00fc4030
+#define BCHP_DMA_AHB_CMD_RX_SCH4_REG_START                 0x00fc4040
+#define BCHP_DMA_AHB_CMD_RX_SCH4_REG_END                   0x00fc4040
+#define BCHP_DMA_AHB_CMD_RX_SCH5_REG_START                 0x00fc4050
+#define BCHP_DMA_AHB_CMD_RX_SCH5_REG_END                   0x00fc4050
+#define BCHP_DMA_AHB_CMD_RX_SCH6_REG_START                 0x00fc4060
+#define BCHP_DMA_AHB_CMD_RX_SCH6_REG_END                   0x00fc4060
+#define BCHP_DMA_AHB_CMD_RX_SCH7_REG_START                 0x00fc4070
+#define BCHP_DMA_AHB_CMD_RX_SCH7_REG_END                   0x00fc4070
+#define BCHP_DMA_AHB_CMD_RX_SCH8_REG_START                 0x00fc4080
+#define BCHP_DMA_AHB_CMD_RX_SCH8_REG_END                   0x00fc4080
+#define BCHP_DMA_AHB_CMD_RX_SCH9_REG_START                 0x00fc4090
+#define BCHP_DMA_AHB_CMD_RX_SCH9_REG_END                   0x00fc4090
+#define BCHP_DMA_AHB_CMD_RX_SCH10_REG_START                0x00fc40a0
+#define BCHP_DMA_AHB_CMD_RX_SCH10_REG_END                  0x00fc40a0
+#define BCHP_DMA_AHB_CMD_RX_SCH11_REG_START                0x00fc40b0
+#define BCHP_DMA_AHB_CMD_RX_SCH11_REG_END                  0x00fc40b0
+#define BCHP_DMA_AHB_CMD_RX_SCH12_REG_START                0x00fc40c0
+#define BCHP_DMA_AHB_CMD_RX_SCH12_REG_END                  0x00fc40c0
+#define BCHP_DMA_AHB_CMD_RX_SCH13_REG_START                0x00fc40d0
+#define BCHP_DMA_AHB_CMD_RX_SCH13_REG_END                  0x00fc40d0
+#define BCHP_DMA_AHB_CMD_RX_SCH14_REG_START                0x00fc40e0
+#define BCHP_DMA_AHB_CMD_RX_SCH14_REG_END                  0x00fc40e0
+#define BCHP_DMA_AHB_CMD_RX_SCH15_REG_START                0x00fc40f0
+#define BCHP_DMA_AHB_CMD_RX_SCH15_REG_END                  0x00fc40f0
+#define BCHP_DMA_AHB_CMD_RX_SCH16_REG_START                0x00fc4100
+#define BCHP_DMA_AHB_CMD_RX_SCH16_REG_END                  0x00fc4100
+#define BCHP_DMA_AHB_CMD_RX_SCH17_REG_START                0x00fc4110
+#define BCHP_DMA_AHB_CMD_RX_SCH17_REG_END                  0x00fc4110
+#define BCHP_DMA_AHB_CMD_RX_SCH18_REG_START                0x00fc4120
+#define BCHP_DMA_AHB_CMD_RX_SCH18_REG_END                  0x00fc4120
+#define BCHP_DMA_AHB_CMD_RX_SCH19_REG_START                0x00fc4130
+#define BCHP_DMA_AHB_CMD_RX_SCH19_REG_END                  0x00fc4130
+#define BCHP_DMA_AHB_CMD_RES0_SCH0_REG_START               0x00fc4200
+#define BCHP_DMA_AHB_CMD_RES0_SCH0_REG_END                 0x00fc4200
+#define BCHP_DMA_AHB_CMD_RES0_SCH1_REG_START               0x00fc4210
+#define BCHP_DMA_AHB_CMD_RES0_SCH1_REG_END                 0x00fc4210
+#define BCHP_DMA_AHB_CMD_RES0_SCH2_REG_START               0x00fc4220
+#define BCHP_DMA_AHB_CMD_RES0_SCH2_REG_END                 0x00fc4220
+#define BCHP_DMA_AHB_CMD_RES0_SCH3_REG_START               0x00fc4230
+#define BCHP_DMA_AHB_CMD_RES0_SCH3_REG_END                 0x00fc4230
+#define BCHP_DMA_AHB_CMD_RES0_SCH4_REG_START               0x00fc4240
+#define BCHP_DMA_AHB_CMD_RES0_SCH4_REG_END                 0x00fc4240
+#define BCHP_DMA_AHB_CMD_RES0_SCH5_REG_START               0x00fc4250
+#define BCHP_DMA_AHB_CMD_RES0_SCH5_REG_END                 0x00fc4250
+#define BCHP_DMA_AHB_CMD_RES0_SCH6_REG_START               0x00fc4260
+#define BCHP_DMA_AHB_CMD_RES0_SCH6_REG_END                 0x00fc4260
+#define BCHP_DMA_AHB_CMD_RES0_SCH7_REG_START               0x00fc4270
+#define BCHP_DMA_AHB_CMD_RES0_SCH7_REG_END                 0x00fc4270
+#define BCHP_DMA_AHB_CMD_TX0_REG_START                     0x00fc4800
+#define BCHP_DMA_AHB_CMD_TX0_REG_END                       0x00fc4800
+#define BCHP_DMA_AHB_CMD_TX1_REG_START                     0x00fc4a00
+#define BCHP_DMA_AHB_CMD_TX1_REG_END                       0x00fc4a00
+#define BCHP_DMA_AHB_CMD_CONF0_REG_START                   0x00fc4c00
+#define BCHP_DMA_AHB_CMD_CONF0_REG_END                     0x00fc4c00
+#define BCHP_MAC_AHB_REG_START                             0x00fc5000
+#define BCHP_MAC_AHB_REG_END                               0x00fc500c
+#define BCHP_LLM_AHB_REG_START                             0x00fc8000
+#define BCHP_LLM_AHB_REG_END                               0x00fc805c
+#define BCHP_PHY_REG_START                                 0x00fe0000
+#define BCHP_PHY_REG_END                                   0x00fe47fc
+#define BCHP_ECL_REG_START                                 0x00fe8000
+#define BCHP_ECL_REG_END                                   0x00fec924
+#define BCHP_DMA_IO2MEM_CH_ECL_TX_Global_REG_START         0x00fed000
+#define BCHP_DMA_IO2MEM_CH_ECL_TX_Global_REG_END           0x00fed014
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH0_REG_START      0x00fed040
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH0_REG_END        0x00fed06c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH1_REG_START      0x00fed080
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH1_REG_END        0x00fed0ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH2_REG_START      0x00fed0c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH2_REG_END        0x00fed0ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH3_REG_START      0x00fed100
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH3_REG_END        0x00fed12c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH4_REG_START      0x00fed140
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH4_REG_END        0x00fed16c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH5_REG_START      0x00fed180
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH5_REG_END        0x00fed1ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH6_REG_START      0x00fed1c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH6_REG_END        0x00fed1ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH7_REG_START      0x00fed200
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH7_REG_END        0x00fed22c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH8_REG_START      0x00fed240
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH8_REG_END        0x00fed26c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH9_REG_START      0x00fed280
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH9_REG_END        0x00fed2ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH10_REG_START     0x00fed2c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH10_REG_END       0x00fed2ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH11_REG_START     0x00fed300
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH11_REG_END       0x00fed32c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH12_REG_START     0x00fed340
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH12_REG_END       0x00fed36c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH13_REG_START     0x00fed380
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH13_REG_END       0x00fed3ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH14_REG_START     0x00fed3c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH14_REG_END       0x00fed3ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH15_REG_START     0x00fed400
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH15_REG_END       0x00fed42c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH16_REG_START     0x00fed440
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH16_REG_END       0x00fed46c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH17_REG_START     0x00fed480
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH17_REG_END       0x00fed4ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH18_REG_START     0x00fed4c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH18_REG_END       0x00fed4ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH19_REG_START     0x00fed500
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH19_REG_END       0x00fed52c
+#define BCHP_DMA_MEM2IO_CH_ECL_RX_REG_START                0x00fed800
+#define BCHP_DMA_MEM2IO_CH_ECL_RX_REG_END                  0x00fed828
+#define BCHP_GMII_REG_START                                0x00fedc00
+#define BCHP_GMII_REG_END                                  0x00fedc58
+#define BCHP_MAC_APB_REG_START                             0x00ff0000
+#define BCHP_MAC_APB_REG_END                               0x00ff14fc
+#define BCHP_DMA_IO2MEM_CH_MAC_RX_Global_REG_START         0x00ff4000
+#define BCHP_DMA_IO2MEM_CH_MAC_RX_Global_REG_END           0x00ff4014
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH0_REG_START      0x00ff4040
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH0_REG_END        0x00ff406c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH1_REG_START      0x00ff4080
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH1_REG_END        0x00ff40ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH2_REG_START      0x00ff40c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH2_REG_END        0x00ff40ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH3_REG_START      0x00ff4100
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH3_REG_END        0x00ff412c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH4_REG_START      0x00ff4140
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH4_REG_END        0x00ff416c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH5_REG_START      0x00ff4180
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH5_REG_END        0x00ff41ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH6_REG_START      0x00ff41c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH6_REG_END        0x00ff41ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH7_REG_START      0x00ff4200
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH7_REG_END        0x00ff422c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH8_REG_START      0x00ff4240
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH8_REG_END        0x00ff426c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH9_REG_START      0x00ff4280
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH9_REG_END        0x00ff42ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH10_REG_START     0x00ff42c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH10_REG_END       0x00ff42ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH11_REG_START     0x00ff4300
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH11_REG_END       0x00ff432c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH12_REG_START     0x00ff4340
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH12_REG_END       0x00ff436c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH13_REG_START     0x00ff4380
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH13_REG_END       0x00ff43ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH14_REG_START     0x00ff43c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH14_REG_END       0x00ff43ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH15_REG_START     0x00ff4400
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH15_REG_END       0x00ff442c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH16_REG_START     0x00ff4440
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH16_REG_END       0x00ff446c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH17_REG_START     0x00ff4480
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH17_REG_END       0x00ff44ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH18_REG_START     0x00ff44c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH18_REG_END       0x00ff44ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH19_REG_START     0x00ff4500
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH19_REG_END       0x00ff452c
+#define BCHP_DMA_IO2MEM_CH_PHY0_Global_REG_START           0x00ff4800
+#define BCHP_DMA_IO2MEM_CH_PHY0_Global_REG_END             0x00ff4814
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH0_REG_START        0x00ff4840
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH0_REG_END          0x00ff486c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH1_REG_START        0x00ff4880
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH1_REG_END          0x00ff48ac
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH2_REG_START        0x00ff48c0
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH2_REG_END          0x00ff48ec
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH3_REG_START        0x00ff4900
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH3_REG_END          0x00ff492c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH4_REG_START        0x00ff4940
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH4_REG_END          0x00ff496c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH5_REG_START        0x00ff4980
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH5_REG_END          0x00ff49ac
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH6_REG_START        0x00ff49c0
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH6_REG_END          0x00ff49ec
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH7_REG_START        0x00ff4a00
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH7_REG_END          0x00ff4a2c
+#define BCHP_DMA_MEM2IO_CH_MAC_TX0_REG_START               0x00ff6000
+#define BCHP_DMA_MEM2IO_CH_MAC_TX0_REG_END                 0x00ff6028
+#define BCHP_DMA_MEM2IO_CH_MAC_TX1_REG_START               0x00ff6400
+#define BCHP_DMA_MEM2IO_CH_MAC_TX1_REG_END                 0x00ff6428
+#define BCHP_DMA_MEM2IO_CH_PHY0_CONFIG_REG_START           0x00ff6800
+#define BCHP_DMA_MEM2IO_CH_PHY0_CONFIG_REG_END             0x00ff6828
+#define BCHP_MOCA_INTC_L2_HI_REG_START                     0x00ff8000
+#define BCHP_MOCA_INTC_L2_HI_REG_END                       0x00ff8584
+#define BCHP_MOCA_INTC_L2_LO_REG_START                     0x00ff8800
+#define BCHP_MOCA_INTC_L2_LO_REG_END                       0x00ff8d84
+#define BCHP_LLM_APB_REG_START                             0x00ffc000
+#define BCHP_LLM_APB_REG_END                               0x00ffd00c
+#define BCHP_TRX_REG_START                                 0x00ffe000
+#define BCHP_TRX_REG_END                                   0x00ffe0d0
+#define BCHP_MOCA_TIMER_REG_START                          0x00ffe400
+#define BCHP_MOCA_TIMER_REG_END                            0x00ffe4ec
+#define BCHP_MOCA_GPIO_REG_START                           0x00ffe800
+#define BCHP_MOCA_GPIO_REG_END                             0x00ffe818
+#define BCHP_EXTRAS_REG_START                              0x00ffec00
+#define BCHP_EXTRAS_REG_END                                0x00ffecec
+#define BCHP_MOCA_HOSTM2M_REG_START                        0x00fffc00
+#define BCHP_MOCA_HOSTM2M_REG_END                          0x00fffc0c
+#define BCHP_MOCA_L2_REG_START                             0x00fffc40
+#define BCHP_MOCA_L2_REG_END                               0x00fffc6c
+#define BCHP_MOCA_GR_BRIDGE_REG_START                      0x00fffc80
+#define BCHP_MOCA_GR_BRIDGE_REG_END                        0x00fffc8c
+#define BCHP_MOCA_HOSTMISC_REG_START                       0x00fffd00
+#define BCHP_MOCA_HOSTMISC_REG_END                         0x00fffd94
+
+
+/***************************************************************************
+ *AUD_FMM_MS_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK  0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
+
+/***************************************************************************
+ *AUD_FMM_OP_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
+ ***************************************************************************/
+/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD1
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_VFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *GFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK      0xffffffff
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT     0
+
+/***************************************************************************
+ *GFD_1
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD_1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK    0xffffffff
+#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT   0
+
+/***************************************************************************
+ *HIFIDAC_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_MUTE_USAGE - Mute usage
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *M2MC
+ ***************************************************************************/
+/***************************************************************************
+ *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK          0xffffffff
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT         0
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK              0xf0000000
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT             28
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK          0x0fffffe0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT         5
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK              0x0000001e
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT             1
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK           0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT          0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid   0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK              0xffff8000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT             15
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK   0x00004000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT  14
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK   0x00002000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT  13
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK         0x00000800
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT        11
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE   1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE  0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK  0x00000400
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK  0x00000200
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK          0x00000100
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT         8
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE   0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK   0x00000020
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT  5
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK     0x00000002
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK     0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT    0
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/***************************************************************************
+ *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK        0xffffffff
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT       0
+
+/***************************************************************************
+ *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK         0xffffffff
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT        0
+
+/***************************************************************************
+ *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_11_DST_COLOR_MATRIX_N - Linked-List Packet Word N for group DST_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_11_DST_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_12_OUTPUT_COLOR_MATRIX_N - Linked-List Packet Word N for group OUTPUT_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_12_OUTPUT_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_13_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *LIST_PKT_14_DST_CLUT - Linked-List Packet Word for group DST_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_14_DST_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_14_DST_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *TYPE_CLUT_COLOR_DATA - color data for color look up table
+ ***************************************************************************/
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK                  0xff000000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT                 24
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK                    0x00ff0000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT                   16
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK                  0x0000ff00
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT                 8
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK                   0x000000ff
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT                  0
+
+/***************************************************************************
+ *MEM_DMA
+ ***************************************************************************/
+/***************************************************************************
+ *DESC_WORD0 - MEM DMA Descriptor Word 0
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD0 :: READ_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD1 - MEM DMA Descriptor Word 1
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD1 :: WRITE_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_MASK                    0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD2 - MEM DMA Descriptor Word 2
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD2 :: INTR_ENABLE [31:31] */
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK                   0x80000000
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_SHIFT                  31
+
+/* MEM_DMA :: DESC_WORD2 :: LAST [30:30] */
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_MASK                          0x40000000
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_SHIFT                         30
+
+/* MEM_DMA :: DESC_WORD2 :: AUTO_APPEND [29:29] */
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_MASK                   0x20000000
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_SHIFT                  29
+
+/* MEM_DMA :: DESC_WORD2 :: reserved0 [28:25] */
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_MASK                     0x1e000000
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_SHIFT                    25
+
+/* MEM_DMA :: DESC_WORD2 :: TRANSFER_SIZE [24:00] */
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK                 0x01ffffff
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_SHIFT                0
+
+/***************************************************************************
+ *DESC_WORD3 - MEM DMA Descriptor Word 3
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD3 :: NEXT_DESC_ADDR [31:05] */
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK                0xffffffe0
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_SHIFT               5
+
+/* MEM_DMA :: DESC_WORD3 :: reserved0 [04:03] */
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_MASK                     0x00000018
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_SHIFT                    3
+
+/* MEM_DMA :: DESC_WORD3 :: READ_ENDIAN_MODE [02:02] */
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_MASK              0x00000004
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_SHIFT             2
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_BIG_ENDIAN        0
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_LITTLE_ENDIAN     1
+
+/* MEM_DMA :: DESC_WORD3 :: WRITE_ENDIAN_XLATE_MODE [01:00] */
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_MASK       0x00000003
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_SHIFT      0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_WORD_ALIGNED 0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_HALF_WORD_ALIGNED 1
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_BYTE_ALIGNED 2
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_reserved   3
+
+/***************************************************************************
+ *DESC_WORD4 - MEM DMA Descriptor Word 4
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD4 :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_SHIFT                    16
+
+/* MEM_DMA :: DESC_WORD4 :: SCRAM_CTRL_RSV [15:14] */
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_MASK                0x0000c000
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_SHIFT               14
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_END [13:13] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK                  0x00002000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_SHIFT                 13
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_START [12:12] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK                0x00001000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_SHIFT               12
+
+/* MEM_DMA :: DESC_WORD4 :: SG_ENABLE [11:11] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK                     0x00000800
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_SHIFT                    11
+
+/* MEM_DMA :: DESC_WORD4 :: ENC_DEC_INIT [10:10] */
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_MASK                  0x00000400
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_SHIFT                 10
+
+/* MEM_DMA :: DESC_WORD4 :: MODE_SEL [09:08] */
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_MASK                      0x00000300
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT                     8
+
+/* MEM_DMA :: DESC_WORD4 :: KEY_SELECT [07:00] */
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_MASK                    0x000000ff
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD5 - MEM DMA Descriptor Word 5
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD5 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD6 - MEM DMA Descriptor Word 6
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD6 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD7 - MEM DMA Descriptor Word 7
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD7 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *PCIE_DMA
+ ***************************************************************************/
+/***************************************************************************
+ *DESC_WORD0 - PCIE DMA Descriptor Word 0
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD0 :: MEMORY_ADDRESS [31:02] */
+#define BCHP_PCIE_DMA_DESC_WORD0_MEMORY_ADDRESS_MASK               0xfffffffc
+#define BCHP_PCIE_DMA_DESC_WORD0_MEMORY_ADDRESS_SHIFT              2
+
+/* PCIE_DMA :: DESC_WORD0 :: reserved0 [01:00] */
+#define BCHP_PCIE_DMA_DESC_WORD0_reserved0_MASK                    0x00000003
+#define BCHP_PCIE_DMA_DESC_WORD0_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD1 - PCIE DMA Descriptor Word 1
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD1 :: PCIE_ADDRESS_LO [31:02] */
+#define BCHP_PCIE_DMA_DESC_WORD1_PCIE_ADDRESS_LO_MASK              0xfffffffc
+#define BCHP_PCIE_DMA_DESC_WORD1_PCIE_ADDRESS_LO_SHIFT             2
+
+/* PCIE_DMA :: DESC_WORD1 :: reserved0 [01:00] */
+#define BCHP_PCIE_DMA_DESC_WORD1_reserved0_MASK                    0x00000003
+#define BCHP_PCIE_DMA_DESC_WORD1_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD2 - PCIE DMA Descriptor Word 2
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD2 :: PCIE_ADDRESS_HI [31:00] */
+#define BCHP_PCIE_DMA_DESC_WORD2_PCIE_ADDRESS_HI_MASK              0xffffffff
+#define BCHP_PCIE_DMA_DESC_WORD2_PCIE_ADDRESS_HI_SHIFT             0
+
+/***************************************************************************
+ *DESC_WORD3 - PCIE DMA Descriptor Word 3
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD3 :: INTERRUPT_ENABLE [31:31] */
+#define BCHP_PCIE_DMA_DESC_WORD3_INTERRUPT_ENABLE_MASK             0x80000000
+#define BCHP_PCIE_DMA_DESC_WORD3_INTERRUPT_ENABLE_SHIFT            31
+
+/* PCIE_DMA :: DESC_WORD3 :: reserved0 [30:25] */
+#define BCHP_PCIE_DMA_DESC_WORD3_reserved0_MASK                    0x7e000000
+#define BCHP_PCIE_DMA_DESC_WORD3_reserved0_SHIFT                   25
+
+/* PCIE_DMA :: DESC_WORD3 :: DMA_TRANSFER_SIZE [24:02] */
+#define BCHP_PCIE_DMA_DESC_WORD3_DMA_TRANSFER_SIZE_MASK            0x01fffffc
+#define BCHP_PCIE_DMA_DESC_WORD3_DMA_TRANSFER_SIZE_SHIFT           2
+
+/* PCIE_DMA :: DESC_WORD3 :: reserved1 [01:00] */
+#define BCHP_PCIE_DMA_DESC_WORD3_reserved1_MASK                    0x00000003
+#define BCHP_PCIE_DMA_DESC_WORD3_reserved1_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD4 - PCIE DMA Descriptor Word 4
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD4 :: LAST_RECORD_INDICATOR [31:31] */
+#define BCHP_PCIE_DMA_DESC_WORD4_LAST_RECORD_INDICATOR_MASK        0x80000000
+#define BCHP_PCIE_DMA_DESC_WORD4_LAST_RECORD_INDICATOR_SHIFT       31
+
+/* PCIE_DMA :: DESC_WORD4 :: DMA_DIRECTION [30:30] */
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_MASK                0x40000000
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_SHIFT               30
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_PCIE_TO_MEMORY      1
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_MEMORY_TO_PCIE      0
+
+/* PCIE_DMA :: DESC_WORD4 :: reserved0 [29:03] */
+#define BCHP_PCIE_DMA_DESC_WORD4_reserved0_MASK                    0x3ffffff8
+#define BCHP_PCIE_DMA_DESC_WORD4_reserved0_SHIFT                   3
+
+/* PCIE_DMA :: DESC_WORD4 :: DESC_CONTIGUOUS [02:02] */
+#define BCHP_PCIE_DMA_DESC_WORD4_DESC_CONTIGUOUS_MASK              0x00000004
+#define BCHP_PCIE_DMA_DESC_WORD4_DESC_CONTIGUOUS_SHIFT             2
+
+/* PCIE_DMA :: DESC_WORD4 :: ENDIAN_XLATE_MODE [01:00] */
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_MASK            0x00000003
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SHIFT           0
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_NO_SWAP         0
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SWAP_16_IN_32   1
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SWAP_32         2
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_reserved        3
+
+/***************************************************************************
+ *DESC_WORD5 - PCIE DMA Descriptor Word 5
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD5 :: NEXT_DESC_ADDRESS_LO [31:05] */
+#define BCHP_PCIE_DMA_DESC_WORD5_NEXT_DESC_ADDRESS_LO_MASK         0xffffffe0
+#define BCHP_PCIE_DMA_DESC_WORD5_NEXT_DESC_ADDRESS_LO_SHIFT        5
+
+/* PCIE_DMA :: DESC_WORD5 :: reserved0 [04:00] */
+#define BCHP_PCIE_DMA_DESC_WORD5_reserved0_MASK                    0x0000001f
+#define BCHP_PCIE_DMA_DESC_WORD5_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD6 - PCIE DMA Descriptor Word 6
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD6 :: NEXT_DESC_ADDRESS_HI [31:00] */
+#define BCHP_PCIE_DMA_DESC_WORD6_NEXT_DESC_ADDRESS_HI_MASK         0xffffffff
+#define BCHP_PCIE_DMA_DESC_WORD6_NEXT_DESC_ADDRESS_HI_SHIFT        0
+
+/***************************************************************************
+ *DESC_WORD7 - PCIE DMA Descriptor Word 7
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD7 :: reserved0 [31:00] */
+#define BCHP_PCIE_DMA_DESC_WORD7_reserved0_MASK                    0xffffffff
+#define BCHP_PCIE_DMA_DESC_WORD7_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *RAAGA_REGSET_DSP_CFG
+ ***************************************************************************/
+/***************************************************************************
+ *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK     0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT    0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo   2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono     1
+
+/***************************************************************************
+ *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right -2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right -2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right -2147483648
+
+/***************************************************************************
+ *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
+
+/***************************************************************************
+ *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off     0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On      1
+
+/***************************************************************************
+ *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt  1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo  2
+
+/***************************************************************************
+ *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK       0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT      0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono    1
+
+/***************************************************************************
+ *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK   0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *RDC
+ ***************************************************************************/
+/***************************************************************************
+ *RUL - RUL Command.
+ ***************************************************************************/
+/* RDC :: RUL :: opcode [31:24] */
+#define BCHP_RDC_RUL_opcode_MASK                                   0xff000000
+#define BCHP_RDC_RUL_opcode_SHIFT                                  24
+#define BCHP_RDC_RUL_opcode_NOP                                    0
+#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM                          1
+#define BCHP_RDC_RUL_opcode_REG_WRITE                              2
+#define BCHP_RDC_RUL_opcode_REG_READ                               3
+#define BCHP_RDC_RUL_opcode_LOAD_IMM                               4
+#define BCHP_RDC_RUL_opcode_WINDOW_WRITE                           5
+#define BCHP_RDC_RUL_opcode_BLOCK_WRITE                            6
+#define BCHP_RDC_RUL_opcode_WINDOW_COPY                            7
+#define BCHP_RDC_RUL_opcode_BLOCK_COPY                             8
+#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK                        9
+#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW                        10
+#define BCHP_RDC_RUL_opcode_AND                                    11
+#define BCHP_RDC_RUL_opcode_AND_IMM                                12
+#define BCHP_RDC_RUL_opcode_OR                                     13
+#define BCHP_RDC_RUL_opcode_OR_IMM                                 14
+#define BCHP_RDC_RUL_opcode_XOR                                    15
+#define BCHP_RDC_RUL_opcode_XOR_IMM                                16
+#define BCHP_RDC_RUL_opcode_NOT                                    17
+#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT                           18
+#define BCHP_RDC_RUL_opcode_SUM                                    19
+#define BCHP_RDC_RUL_opcode_SUM_IMM                                20
+#define BCHP_RDC_RUL_opcode_COND_SKIP                              21
+#define BCHP_RDC_RUL_opcode_SKIP                                   22
+#define BCHP_RDC_RUL_opcode_EXIT                                   23
+#define BCHP_RDC_RUL_opcode_PLACEHOLDER                            255
+
+/* RDC :: RUL :: reserved0 [23:23] */
+#define BCHP_RDC_RUL_reserved0_MASK                                0x00800000
+#define BCHP_RDC_RUL_reserved0_SHIFT                               23
+
+/* union - case rdc_args [22:00] */
+/* RDC :: RUL :: rdc_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_rdc_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: rdc_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_rdc_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_rdc_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: rdc_args :: src2 [11:06] */
+#define BCHP_RDC_RUL_rdc_args_src2_MASK                            0x00000fc0
+#define BCHP_RDC_RUL_rdc_args_src2_SHIFT                           6
+
+/* RDC :: RUL :: rdc_args :: dest [05:00] */
+#define BCHP_RDC_RUL_rdc_args_dest_MASK                            0x0000003f
+#define BCHP_RDC_RUL_rdc_args_dest_SHIFT                           0
+
+/* union - case reg_args [22:00] */
+/* RDC :: RUL :: reg_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_reg_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_reg_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: reg_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_reg_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_reg_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: reg_args :: count [11:00] */
+#define BCHP_RDC_RUL_reg_args_count_MASK                           0x00000fff
+#define BCHP_RDC_RUL_reg_args_count_SHIFT                          0
+
+/***************************************************************************
+ *SPDIF_RCVR_ESR
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_INTERRUPT_HANDLING - Interrupt Handling
+ ***************************************************************************/
+/* SPDIF_RCVR_ESR :: ABSTRACT_INTERRUPT_HANDLING :: MORE_INFORMATION [31:00] */
+#define BCHP_SPDIF_RCVR_ESR_ABSTRACT_INTERRUPT_HANDLING_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_SPDIF_RCVR_ESR_ABSTRACT_INTERRUPT_HANDLING_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *VICE2_REGSET_MISC
+ ***************************************************************************/
+/***************************************************************************
+ *DCCM - registers interface address offset in DCCM.
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: DCCM :: INTERFACE [31:16] */
+#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_MASK                 0xffff0000
+#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_SHIFT                16
+#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_HOST2VICE_OFFSET     0
+#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_VICE2HOST_OFFSET     4
+#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_BVN2VICE_OFFSET      8
+#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_MBOX_0_START         16
+#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_MBOX_1_START         36
+
+/* VICE2_REGSET_MISC :: DCCM :: REVISION [15:00] */
+#define BCHP_VICE2_REGSET_MISC_DCCM_REVISION_MASK                  0x0000ffff
+#define BCHP_VICE2_REGSET_MISC_DCCM_REVISION_SHIFT                 0
+#define BCHP_VICE2_REGSET_MISC_DCCM_REVISION_ID                    1
+
+/***************************************************************************
+ *DWORD_00_BVB_PIC_SIZE - BVB Picture Size
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: DWORD_00_BVB_PIC_SIZE :: H_SIZE [31:16] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_H_SIZE_MASK   0xffff0000
+#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_H_SIZE_SHIFT  16
+
+/* VICE2_REGSET_MISC :: DWORD_00_BVB_PIC_SIZE :: V_SIZE [15:00] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_V_SIZE_MASK   0x0000ffff
+#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_V_SIZE_SHIFT  0
+
+/***************************************************************************
+ *DWORD_01_SAMPLE_ASPECT_RATIO - Sample Aspect Ratio
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: DWORD_01_SAMPLE_ASPECT_RATIO :: H_SIZE [31:16] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_H_SIZE_MASK 0xffff0000
+#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_H_SIZE_SHIFT 16
+
+/* VICE2_REGSET_MISC :: DWORD_01_SAMPLE_ASPECT_RATIO :: V_SIZE [15:00] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_V_SIZE_MASK 0x0000ffff
+#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_V_SIZE_SHIFT 0
+
+/***************************************************************************
+ *DWORD_02_PIC_INFO - Picture Information
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: FRAME_RATE [31:16] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_FRAME_RATE_MASK   0xffff0000
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_FRAME_RATE_SHIFT  16
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: SRC_PIC_TYPE [15:12] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_MASK 0x0000f000
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_SHIFT 12
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_UNKNOWN 0
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_I    1
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_P    2
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_B    3
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: POLARITY [11:10] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_MASK     0x00000c00
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_SHIFT    10
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_TOP      0
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_BOT      1
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_FRAME    2
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: REPEAT [09:09] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_MASK       0x00000200
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_SHIFT      9
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_DISABLE    0
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_ENABLE     1
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: IGNORE [08:08] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_MASK       0x00000100
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_SHIFT      8
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_DISABLE    0
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_ENABLE     1
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: LAST [07:07] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_MASK         0x00000080
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_SHIFT        7
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_FALSE        0
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_TRUE         1
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: CHANNELCHANGE [06:06] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_MASK 0x00000040
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_SHIFT 6
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_FALSE 0
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_TRUE 1
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: reserved0 [05:00] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_reserved0_MASK    0x0000003f
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_reserved0_SHIFT   0
+
+/***************************************************************************
+ *DWORD_03_ORIGINAL_PTS - Source PTS Value
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: DWORD_03_ORIGINAL_PTS :: VAL [31:00] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_03_ORIGINAL_PTS_VAL_MASK      0xffffffff
+#define BCHP_VICE2_REGSET_MISC_DWORD_03_ORIGINAL_PTS_VAL_SHIFT     0
+
+/***************************************************************************
+ *DWORD_04_STG_PICTURE_ID - STG Picture ID
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: DWORD_04_STG_PICTURE_ID :: VAL [31:00] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_04_STG_PICTURE_ID_VAL_MASK    0xffffffff
+#define BCHP_VICE2_REGSET_MISC_DWORD_04_STG_PICTURE_ID_VAL_SHIFT   0
+
+/***************************************************************************
+ *MBOX - MBOX registers interface address offset.
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: MBOX :: INTERFACE [31:16] */
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_MASK                 0xffff0000
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_SHIFT                16
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_00_BVB_PIC_SIZE_OFFSET 0
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_01_SAMPLE_ASPECT_RATIO_OFFSET 4
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_02_PIC_INFO_OFFSET 8
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_03_ORIGINAL_PTS_OFFSET 12
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_04_STG_PICTURE_ID_OFFSET 16
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_SIZE                 5
+
+/* VICE2_REGSET_MISC :: MBOX :: REVISION [15:00] */
+#define BCHP_VICE2_REGSET_MISC_MBOX_REVISION_MASK                  0x0000ffff
+#define BCHP_VICE2_REGSET_MISC_MBOX_REVISION_SHIFT                 0
+#define BCHP_VICE2_REGSET_MISC_MBOX_REVISION_ID                    3
+
+/***************************************************************************
+ *XPT_PB
+ ***************************************************************************/
+/***************************************************************************
+ *DESCRIPTOR_ABSTRACT - Playback Linked-List Descriptor Abstract
+ ***************************************************************************/
+/* XPT_PB :: DESCRIPTOR_ABSTRACT :: DESCRIPTOR_FORMAT [31:00] */
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_MASK     0xffffffff
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_SHIFT    0
+
+/***************************************************************************
+ *DESC_0 - Playback Linked-List Descriptor Word 0
+ ***************************************************************************/
+/* XPT_PB :: DESC_0 :: PB_BUFFER_START_ADDR [31:00] */
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_MASK               0xffffffff
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_SHIFT              0
+
+/***************************************************************************
+ *DESC_1 - Playback Linked-List Descriptor Word 1
+ ***************************************************************************/
+/* XPT_PB :: DESC_1 :: PB_BUFFER_LENGTH [31:00] */
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_MASK                   0xffffffff
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_SHIFT                  0
+
+/***************************************************************************
+ *DESC_2 - Playback Linked-List Descriptor Word 2
+ ***************************************************************************/
+/* XPT_PB :: DESC_2 :: PB_INTERRUPT_ENABLE [31:31] */
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_MASK                0x80000000
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_SHIFT               31
+
+/* XPT_PB :: DESC_2 :: PB_FORCE_RESYNC [30:30] */
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_MASK                    0x40000000
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_SHIFT                   30
+
+/* XPT_PB :: DESC_2 :: PB_HOST_DATA_INS_EN [29:29] */
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_MASK                0x20000000
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_SHIFT               29
+
+/* XPT_PB :: DESC_2 :: PUSH_PARTIAL_PACKET [28:28] */
+#define BCHP_XPT_PB_DESC_2_PUSH_PARTIAL_PACKET_MASK                0x10000000
+#define BCHP_XPT_PB_DESC_2_PUSH_PARTIAL_PACKET_SHIFT               28
+
+/* XPT_PB :: DESC_2 :: PB_DESC_TAG_ID [27:24] */
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_MASK                     0x0f000000
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_SHIFT                    24
+
+/* XPT_PB :: DESC_2 :: reserved0 [23:00] */
+#define BCHP_XPT_PB_DESC_2_reserved0_MASK                          0x00ffffff
+#define BCHP_XPT_PB_DESC_2_reserved0_SHIFT                         0
+
+/***************************************************************************
+ *DESC_3 - Playback Linked-List Descriptor Word 3
+ ***************************************************************************/
+/* XPT_PB :: DESC_3 :: PB_NEXT_DESC_ADDR [31:04] */
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_MASK                  0xfffffff0
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_SHIFT                 4
+
+/* XPT_PB :: DESC_3 :: reserved0 [03:01] */
+#define BCHP_XPT_PB_DESC_3_reserved0_MASK                          0x0000000e
+#define BCHP_XPT_PB_DESC_3_reserved0_SHIFT                         1
+
+/* XPT_PB :: DESC_3 :: PB_LAST_DESC_IND [00:00] */
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_MASK                   0x00000001
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_SHIFT                  0
+
+/***************************************************************************
+ *DESC_4 - Playback Linked-List Descriptor Word 4
+ ***************************************************************************/
+/* XPT_PB :: DESC_4 :: reserved0 [31:00] */
+#define BCHP_XPT_PB_DESC_4_reserved0_MASK                          0xffffffff
+#define BCHP_XPT_PB_DESC_4_reserved0_SHIFT                         0
+
+/***************************************************************************
+ *DESC_5 - Playback Linked-List Descriptor Word 5
+ ***************************************************************************/
+/* XPT_PB :: DESC_5 :: reserved0 [31:03] */
+#define BCHP_XPT_PB_DESC_5_reserved0_MASK                          0xfffffff8
+#define BCHP_XPT_PB_DESC_5_reserved0_SHIFT                         3
+
+/* XPT_PB :: DESC_5 :: RANDOM_ACCESS_INDICATION [02:02] */
+#define BCHP_XPT_PB_DESC_5_RANDOM_ACCESS_INDICATION_MASK           0x00000004
+#define BCHP_XPT_PB_DESC_5_RANDOM_ACCESS_INDICATION_SHIFT          2
+
+/* XPT_PB :: DESC_5 :: NEXT_PACKET_PACING_TIMESTAMP_VALID [01:01] */
+#define BCHP_XPT_PB_DESC_5_NEXT_PACKET_PACING_TIMESTAMP_VALID_MASK 0x00000002
+#define BCHP_XPT_PB_DESC_5_NEXT_PACKET_PACING_TIMESTAMP_VALID_SHIFT 1
+
+/* XPT_PB :: DESC_5 :: PKT2PKT_PACING_TIMESTAMP_DELTA_VALID [00:00] */
+#define BCHP_XPT_PB_DESC_5_PKT2PKT_PACING_TIMESTAMP_DELTA_VALID_MASK 0x00000001
+#define BCHP_XPT_PB_DESC_5_PKT2PKT_PACING_TIMESTAMP_DELTA_VALID_SHIFT 0
+
+/***************************************************************************
+ *DESC_6 - Playback Linked-List Descriptor Word 6
+ ***************************************************************************/
+/* XPT_PB :: DESC_6 :: NEXT_PACKET_PACING_TIMESTAMP [31:00] */
+#define BCHP_XPT_PB_DESC_6_NEXT_PACKET_PACING_TIMESTAMP_MASK       0xffffffff
+#define BCHP_XPT_PB_DESC_6_NEXT_PACKET_PACING_TIMESTAMP_SHIFT      0
+
+/***************************************************************************
+ *DESC_7 - Playback Linked-List Descriptor Word 7
+ ***************************************************************************/
+/* XPT_PB :: DESC_7 :: PKT2PKT_PACING_TIMESTAMP_DELTA [31:00] */
+#define BCHP_XPT_PB_DESC_7_PKT2PKT_PACING_TIMESTAMP_DELTA_MASK     0xffffffff
+#define BCHP_XPT_PB_DESC_7_PKT2PKT_PACING_TIMESTAMP_DELTA_SHIFT    0
+
+/***************************************************************************
+ *XPT_RAVE
+ ***************************************************************************/
+/***************************************************************************
+ *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
+
+/***************************************************************************
+ *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
+
+/***************************************************************************
+ *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
+ ***************************************************************************/
+/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_DVD_AC3_AUDIO_ES_SETUP - ES Setup - DVD_AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_DVD_AC3_AUDIO_ES_SETUP :: DVD_AUDIO_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_DVD_AC3_AUDIO_ES_SETUP_DVD_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_DVD_AC3_AUDIO_ES_SETUP_DVD_AUDIO_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEI_DVD_LPCM_AUDIO_ES_SETUP - ES Setup - DVD_LPCM Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEI_DVD_LPCM_AUDIO_ES_SETUP :: DVD_AUDIO_LPCM_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEI_DVD_LPCM_AUDIO_ES_SETUP_DVD_AUDIO_LPCM_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEI_DVD_LPCM_AUDIO_ES_SETUP_DVD_AUDIO_LPCM_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
+
+#endif /* #ifndef BCHP_COMMON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_ddr40_phy_control_regs_0.h b/include/linux/brcmstb/7425b0/bchp_ddr40_phy_control_regs_0.h
new file mode 100644
index 0000000..81abbcc
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_ddr40_phy_control_regs_0.h
@@ -0,0 +1,1510 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:42 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_CONTROL_REGS_0 - DDR40 DDR40 physical interface control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION   0x003b6000 /* Address & Control revision register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL 0x003b6004 /* PHY clock power management control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS 0x003b6010 /* PHY PLL status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG 0x003b6014 /* PHY PLL configuration register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL 0x003b6018 /* PHY PLL control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS 0x003b601c /* PHY PLL dividers control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL 0x003b6020 /* Aux Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL 0x003b6030 /* Address & Control coarse VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL 0x003b6034 /* Address & Control fine VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL 0x003b6038 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL 0x003b603c /* PVT Compensation control and status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL 0x003b6040 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS 0x003b6044 /* PHY Auto Init rd_data_dly result register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE 0x003b6048 /* PHY VDL calibration control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS 0x003b604c /* PHY VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS 0x003b6050 /* PHY DQ VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS 0x003b6054 /* PHY Write Channel VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS 0x003b6058 /* PHY Read Enable VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL 0x003b605c /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS 0x003b6060 /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS 0x003b6064 /* Virtual VTT Connections register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE 0x003b6068 /* Virtual VTT Override register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL 0x003b606c /* VREF DAC Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL 0x003b6070 /* PhyBist Control Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED 0x003b6074 /* PhyBist Seed Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS 0x003b6078 /* PhyBist General Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS 0x003b607c /* PhyBist Per-Bit Control Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS 0x003b6080 /* PhyBist Per-Bit DQ Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS 0x003b6084 /* PhyBist Per-Bit DM and CK Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG 0x003b6090 /* DRAM Command Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0  0x003b6094 /* Mode Register 0 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1  0x003b6098 /* Mode Register 1 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2  0x003b609c /* Mode Register 2 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3  0x003b60a0 /* Mode Register 3 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL 0x003b60a4 /* Standby Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL 0x003b60b0 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2 0x003b60b4 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS 0x003b60b8 /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2 0x003b60bc /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE 0x003b60c0 /* Freeze-on-error enable register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK 0x003b60c4 /* Datapth Loopback control register */
+
+/***************************************************************************
+ *REVISION - Address & Control revision register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_MASK      0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_SHIFT     16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_MASK          0x0000ff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_SHIFT         8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_DEFAULT       0x00000040
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_MASK          0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_DEFAULT       0x00000005
+
+/***************************************************************************
+ *CLK_PM_CTRL - PHY clock power management control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_MASK   0xfffffffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_SHIFT  1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_STATUS - PHY PLL status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_MASK    0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_SHIFT   27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK_LOST [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_MASK    0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_SHIFT   26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: DDR_MHZ [25:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_MASK      0x03ffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_SHIFT     14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_4X [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: STATUS [12:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_MASK       0x00001ffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_SHIFT      1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_MASK         0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_CONFIG - PHY PLL configuration register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved0 [31:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_MASK    0xffffff80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_SHIFT   7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LP40_PLL_POST_RESET [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET_POST_DIV [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LDO_CTRL [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_MASK     0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_SHIFT    3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_DEFAULT  0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved1 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_MASK    0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_SHIFT   2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_MASK        0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_SHIFT       1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_DEFAULT     0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PWRDN [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_MASK        0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_SHIFT       0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PLL_CONTROL - PHY PLL control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: reserved0 [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_SHIFT  31
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_kp [30:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_MASK        0x78000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_SHIFT       27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_DEFAULT     0x0000000a
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ki [26:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_MASK        0x07000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_SHIFT       24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_DEFAULT     0x00000003
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ka [23:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_MASK        0x00e00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_SHIFT       21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_DEFAULT     0x00000003
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: PLL_CONTROL [20:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_MASK 0x001fffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_DIVIDERS - PHY PLL dividers control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_MASK  0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_SHIFT 16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_HI [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_MASK 0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_LO [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: POST_DIV [13:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_MASK   0x00003800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_SHIFT  11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_DEFAULT 0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: PDIV [10:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_MASK       0x00000700
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_SHIFT      8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_DEFAULT    0x00000004
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_MASK       0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_DEFAULT    0x00000020
+
+/***************************************************************************
+ *AUX_CONTROL - Aux Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved0 [31:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_MASK   0xfffffc00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_SHIFT  10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_cs [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_MASK       0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_SHIFT      7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_ad [06:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_MASK       0x00000070
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_SHIFT      4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_odt [03:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_MASK      0x0000000e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_SHIFT     1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: override [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_CTL - Address & Control coarse VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BIT_CTL - Address & Control fine VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_SHIFT  31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved0 [30:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ffffe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: rxenb [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_MASK  0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved1 [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_SHIFT 7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_reb [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ZQ_PVT_COMP_CTL - PVT Compensation control and status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: update_mode [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_done [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_done [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_done [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: auto_sample_en [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_MASK 0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_en [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_ovr_en [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_ovr_en [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_comp [17:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_MASK 0x00038000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_comp [14:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_MASK 0x00007000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [11:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_MASK 0x00000e00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [08:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_MASK 0x000001c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: auto_oeb [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a15 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_MASK  0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a14 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_MASK  0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a13 [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_MASK  0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_aux [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_MASK  0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: half_strength [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_MASK     0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_SHIFT    2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_MASK  0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_MASK     0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_SHIFT    0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_DEFAULT  0x00000000
+
+/***************************************************************************
+ *VDL_RD_DATA_DLY_STATUS - PHY Auto Init rd_data_dly result register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_SHIFT 12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: auto_init_state [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_MASK 0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_max [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_min [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_DEFAULT 0x00000007
+
+/***************************************************************************
+ *VDL_CALIBRATE - PHY VDL calibration control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_SHIFT 29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: use_straps [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: auto_init [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: skip_rst [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_MASK  0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_SHIFT 26
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: exit_in_sr [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_dly_cal [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_refresh [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_wr_dq [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: dq0_only [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_MASK  0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_mr_mpr [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_cal [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_MASK   0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_SHIFT  19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_en_cal [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_clocks [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_pair [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_steps [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_auto [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_ftm [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_phybist [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_byte [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_clocks [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_test [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_always [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_once [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_fast [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CALIB_STATUS - PHY VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_MASK 0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_fail [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_MASK 0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_SHIFT 29
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_done [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_rd_data_dly_error [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_read_en_error [26:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_MASK 0x07800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_error [22:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_MASK 0x00780000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_sel [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_total [11:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_MASK 0x00000ffc
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VDL_DQ_CALIB_STATUS - PHY DQ VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_total [25:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_MASK 0x03ff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_clocks [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_mode [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_WR_CHAN_CALIB_STATUS - PHY Write Channel VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_RD_EN_CALIB_STATUS - PHY Read Enable VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: low_vtt [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: high_vtt [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: error_reset [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_ctl_idle [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cs_idle [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cke_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error [18:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_MASK 0x0007fff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_low [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_high [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ready [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_DEFAULT 0x00ffffff
+
+/***************************************************************************
+ *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_DEFAULT 0x0003ffff
+
+/***************************************************************************
+ *VREF_DAC_CONTROL - VREF DAC Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK1_GT_INT [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK0_GT_INT [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_GT_INT [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: EXT_GT_INT [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_TESTOUT_MUX_CTL [16:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_MASK 0x00018000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TEST [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_MASK   0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_SHIFT  14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_MASK   0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_SHIFT  13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_MASK   0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_SHIFT  12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_MASK   0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_SHIFT  6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_DEFAULT 0x00000020
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_MASK   0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_SHIFT  0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_DEFAULT 0x00000020
+
+/***************************************************************************
+ *PHYBIST_CNTRL - PhyBist Control Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_error_sel [13:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_MASK 0x00003f00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved1 [07:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_MASK 0x000000e0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_SHIFT 5
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: bench_mode [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_dat_error [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_ctl_error [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: int_loopback [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHYBIST_SEED - PhyBist Seed Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_SEED :: seed [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_MASK       0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_DEFAULT    0x250e4af6
+
+/***************************************************************************
+ *PHYBIST_STATUS - PhyBist General Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_pass [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_pass [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_SHIFT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_done [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_done [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: ctl_errors [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_DQ_STATUS - PhyBist Per-Bit DQ Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_STATUS :: dat_errors [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_MASK 0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_MISC_STATUS - PhyBist Per-Bit DM and CK Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: ck_errors [07:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_MASK 0x000000f0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: dm_errors [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_SHIFT 0
+
+/***************************************************************************
+ *COMMAND_REG - DRAM Command Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_MASK   0xfe000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_SHIFT  25
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: aux [24:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_MASK         0x01c00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_SHIFT        22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: we [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_MASK          0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_SHIFT         21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_DEFAULT       0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: cas [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_MASK         0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_SHIFT        20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ras [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_MASK         0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_SHIFT        19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ba [18:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_MASK          0x00070000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_SHIFT         16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_DEFAULT       0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_MASK          0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_DEFAULT       0x00000000
+
+/***************************************************************************
+ *MODE_REG0 - Mode Register 0
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG1 - Mode Register 1
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG2 - Mode Register 2
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG3 - Mode Register 3
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STANDBY_CONTROL - Standby Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_ready [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_exit_pin_en [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_active [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: armed [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_MASK   0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_SHIFT  15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: warmstart [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_ldo_volts [13:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_MASK 0x00003000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_skip_mrs [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_rst_n [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_cke [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: ldo_volts [08:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_MASK 0x00000180
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_DEFAULT 0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: skip_mrs [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: rst_n [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_MASK   0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_SHIFT  5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: cke [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_MASK     0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_SHIFT    4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_CONTROL - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: reserved0 [31:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_MASK 0xf0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_MASK       0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_SHIFT      16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_MASK  0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_MASK 0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_MASK     0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_SHIFT    12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_MASK      0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_SHIFT     11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_MASK      0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_SHIFT     8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_CONTROL2 - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_MASK     0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_SHIFT    20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_MASK       0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_SHIFT      17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_MASK       0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_SHIFT      12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_MASK      0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_SHIFT     7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_MASK       0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_DEFAULT    0x00000000
+
+/***************************************************************************
+ *STRAP_STATUS - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_MASK  0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_reg [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_MASK   0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_SHIFT  29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_memc [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_MASK  0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_MASK        0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_SHIFT       16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_MASK   0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_SHIFT  14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_MASK      0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_SHIFT     12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_MASK       0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_SHIFT      11
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_SHIFT 10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_MASK       0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_SHIFT      8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_MASK  0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_SHIFT 0
+
+/***************************************************************************
+ *STRAP_STATUS2 - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_MASK      0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_SHIFT     20
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_MASK        0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_SHIFT       17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_MASK        0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_SHIFT       12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_MASK       0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_SHIFT      7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_MASK        0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_SHIFT       0
+
+/***************************************************************************
+ *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl1 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl0 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl1 [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl0 [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DATAPATH_LOOPBACK - Datapth Loopback control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: xor_dm_rd_en [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: use_addr_ctl [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_ddr40_phy_control_regs_1.h b/include/linux/brcmstb/7425b0/bchp_ddr40_phy_control_regs_1.h
new file mode 100644
index 0000000..5955309
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_ddr40_phy_control_regs_1.h
@@ -0,0 +1,92 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Jun 13 14:02:37 2011
+ *                 MD5 Checksum         a14f8e7f638a7ebe759043ff756befc5
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7425/rdb/b0/bchp_ddr40_phy_control_regs_1.h $
+ * 
+ * Hydra_Software_Devel/3   6/14/11 1:15p vanessah
+ * SW7425-715: 7425 B0 RDB resync
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_CONTROL_REGS_1_H__
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_H__
+
+/***************************************************************************
+ *DDR40_PHY_CONTROL_REGS_1 - DDR40 DDR40 physical interface control registers 1
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_REVISION   0x003c6000 /* Address & Control revision register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_CLK_PM_CTRL 0x003c6004 /* PHY clock power management control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_STATUS 0x003c6010 /* PHY PLL status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG 0x003c6014 /* PHY PLL configuration register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONTROL 0x003c6018 /* PHY PLL control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_DIVIDERS 0x003c601c /* PHY PLL dividers control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_AUX_CONTROL 0x003c6020 /* Aux Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BYTE_CTL 0x003c6030 /* Address & Control coarse VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BIT_CTL 0x003c6034 /* Address & Control fine VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL 0x003c6038 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL 0x003c603c /* PVT Compensation control and status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL 0x003c6040 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_DATA_DLY_STATUS 0x003c6044 /* PHY Auto Init rd_data_dly result register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE 0x003c6048 /* PHY VDL calibration control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS 0x003c604c /* PHY VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS 0x003c6050 /* PHY DQ VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS 0x003c6054 /* PHY Write Channel VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS 0x003c6058 /* PHY Read Enable VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL 0x003c605c /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS 0x003c6060 /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONNECTIONS 0x003c6064 /* Virtual VTT Connections register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_OVERRIDE 0x003c6068 /* Virtual VTT Override register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL 0x003c606c /* VREF DAC Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL 0x003c6070 /* PhyBist Control Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_SEED 0x003c6074 /* PhyBist Seed Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_STATUS 0x003c6078 /* PhyBist General Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CTL_STATUS 0x003c607c /* PhyBist Per-Bit Control Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_DQ_STATUS 0x003c6080 /* PhyBist Per-Bit DQ Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_MISC_STATUS 0x003c6084 /* PhyBist Per-Bit DM and CK Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_COMMAND_REG 0x003c6090 /* DRAM Command Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG0  0x003c6094 /* Mode Register 0 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG1  0x003c6098 /* Mode Register 1 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG2  0x003c609c /* Mode Register 2 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG3  0x003c60a0 /* Mode Register 3 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL 0x003c60a4 /* Standby Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL 0x003c60b0 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL2 0x003c60b4 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS 0x003c60b8 /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS2 0x003c60bc /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE 0x003c60c0 /* Freeze-on-error enable register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DATAPATH_LOOPBACK 0x003c60c4 /* Datapth Loopback control register */
+
+#endif /* #ifndef BCHP_DDR40_PHY_CONTROL_REGS_1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_ddr40_phy_word_lane_0_0.h b/include/linux/brcmstb/7425b0/bchp_ddr40_phy_word_lane_0_0.h
new file mode 100644
index 0000000..7addfe5
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_ddr40_phy_word_lane_0_0.h
@@ -0,0 +1,3331 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:44 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_0_0 - DDR40 DDR40 word lane #0 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN 0x003b6200 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W 0x003b6204 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P 0x003b6208 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N 0x003b620c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W 0x003b6210 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W 0x003b6214 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W 0x003b6218 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W 0x003b621c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W 0x003b6220 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W 0x003b6224 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W 0x003b6228 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W 0x003b622c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W 0x003b6230 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003b6234 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003b6238 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003b623c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003b6240 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003b6244 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003b6248 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003b624c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003b6250 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003b6254 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003b6258 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003b625c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003b6260 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003b6264 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003b6268 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003b626c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003b6270 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003b6274 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W 0x003b62a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P 0x003b62a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N 0x003b62ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W 0x003b62b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W 0x003b62b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W 0x003b62b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W 0x003b62bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W 0x003b62c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W 0x003b62c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W 0x003b62c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W 0x003b62cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W 0x003b62d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003b62d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003b62d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003b62dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003b62e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003b62e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003b62e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003b62ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003b62f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003b62f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003b62f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003b62fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003b6300 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003b6304 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003b6308 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003b630c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003b6310 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003b6314 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x003b6328 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x003b632c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003b6330 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003b6334 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W 0x003b6338 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003b633c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x003b6348 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x003b634c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003b6350 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003b6354 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W 0x003b6358 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003b635c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY 0x003b6360 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL 0x003b6364 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0 0x003b6370 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1 0x003b6374 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2 0x003b6378 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3 0x003b637c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0 0x003b6380 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1 0x003b6384 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2 0x003b6388 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3 0x003b638c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS 0x003b6390 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR 0x003b6394 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL 0x003b63a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL 0x003b63a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE 0x003b63a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE 0x003b63ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ 0x003b63b0 /* PHYBIST mode VDL step select adjustment register */
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_RD_EN - Read Enable Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_DATA_DLY - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_MASK  0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: rd_data_dly [02:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_MASK 0x00000007
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_DEFAULT 0x00000001
+
+/***************************************************************************
+ *READ_CONTROL - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_MASK   0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_SHIFT  3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_enable [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_te_adj [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_le_adj [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status1 [07:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_MASK 0x000000f0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status0 [03:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_MASK 0x0000000f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: clear [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_MASK    0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_SHIFT   31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_SHIFT 24
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_MASK 0x00c00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_SHIFT 22
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_MASK 0x00300000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_SHIFT 20
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00080000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 19
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00040000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_SHIFT 18
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_MASK  0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_MASK  0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00008000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 15
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00004000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 14
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00002000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 13
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00001000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 12
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_MASK 0x00000008
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_MASK  0xfffff000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_SHIFT 12
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: no_dqs_rd [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_MASK  0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_MASK    0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_SHIFT   6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_MASK      0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_SHIFT     2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_DEFAULT   0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_MASK   0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_SHIFT  1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_MASK      0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_SHIFT     0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_DEFAULT   0x00000000
+
+/***************************************************************************
+ *CLOCK_PAD_DISABLE - Clock pad disable register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffc
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_SHIFT 2
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: long [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_MASK    0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_SHIFT   1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: mode [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHYBIST_VDL_ADJ - PHYBIST mode VDL step select adjustment register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_SHIFT 29
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq1_vdl_adj [28:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_MASK 0x1f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved1 [23:21] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_MASK 0x00e00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_SHIFT 21
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq0_vdl_adj [20:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_MASK 0x001f0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved2 [15:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_MASK 0x0000e000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_SHIFT 13
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs1_vdl_adj [12:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_MASK 0x00001f00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved3 [07:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_MASK 0x000000e0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_SHIFT 5
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs0_vdl_adj [04:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_MASK 0x0000001f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_ddr40_phy_word_lane_0_1.h b/include/linux/brcmstb/7425b0/bchp_ddr40_phy_word_lane_0_1.h
new file mode 100644
index 0000000..c703411
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_ddr40_phy_word_lane_0_1.h
@@ -0,0 +1,139 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Apr 11 12:23:07 2011
+ *                 MD5 Checksum         8cf142ad25caa9f873c54e8bb2bb1755
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7425/rdb/b0/bchp_ddr40_phy_word_lane_0_1.h $
+ * 
+ * Hydra_Software_Devel/2   4/11/11 11:57p vanessah
+ * SW7425-112: Update rdb files for 7425 B0.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_0_1_H__
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_0_1 - DDR40 DDR40 word lane #0 control registers 1
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN 0x003c6200 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W 0x003c6204 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P 0x003c6208 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N 0x003c620c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W 0x003c6210 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W 0x003c6214 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W 0x003c6218 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W 0x003c621c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W 0x003c6220 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W 0x003c6224 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W 0x003c6228 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W 0x003c622c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W 0x003c6230 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003c6234 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003c6238 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003c623c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003c6240 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003c6244 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003c6248 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003c624c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003c6250 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003c6254 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003c6258 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003c625c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003c6260 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003c6264 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003c6268 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003c626c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003c6270 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003c6274 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W 0x003c62a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P 0x003c62a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N 0x003c62ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W 0x003c62b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W 0x003c62b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W 0x003c62b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W 0x003c62bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W 0x003c62c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W 0x003c62c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W 0x003c62c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W 0x003c62cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W 0x003c62d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003c62d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003c62d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003c62dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003c62e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003c62e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003c62e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003c62ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003c62f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003c62f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003c62f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003c62fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003c6300 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003c6304 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003c6308 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003c630c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003c6310 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003c6314 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_P 0x003c6328 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_N 0x003c632c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003c6330 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003c6334 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_W 0x003c6338 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003c633c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_P 0x003c6348 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_N 0x003c634c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003c6350 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003c6354 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_W 0x003c6358 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003c635c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_DATA_DLY 0x003c6360 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_CONTROL 0x003c6364 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_0 0x003c6370 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_1 0x003c6374 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_2 0x003c6378 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_3 0x003c637c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_0 0x003c6380 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_1 0x003c6384 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_2 0x003c6388 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_3 0x003c638c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_STATUS 0x003c6390 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_CLEAR 0x003c6394 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL 0x003c63a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL 0x003c63a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_CLOCK_PAD_DISABLE 0x003c63a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_WR_PREAMBLE_MODE 0x003c63ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ 0x003c63b0 /* PHYBIST mode VDL step select adjustment register */
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_0_1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_ddr40_phy_word_lane_1_0.h b/include/linux/brcmstb/7425b0/bchp_ddr40_phy_word_lane_1_0.h
new file mode 100644
index 0000000..575c82e
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_ddr40_phy_word_lane_1_0.h
@@ -0,0 +1,139 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Apr 11 12:01:44 2011
+ *                 MD5 Checksum         8cf142ad25caa9f873c54e8bb2bb1755
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7425/rdb/b0/bchp_ddr40_phy_word_lane_1_0.h $
+ * 
+ * Hydra_Software_Devel/2   4/11/11 11:57p vanessah
+ * SW7425-112: Update rdb files for 7425 B0.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_1_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_1_0 - DDR40 DDR40 word lane #1 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN 0x003b6400 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W 0x003b6404 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P 0x003b6408 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N 0x003b640c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W 0x003b6410 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W 0x003b6414 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W 0x003b6418 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W 0x003b641c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W 0x003b6420 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W 0x003b6424 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W 0x003b6428 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W 0x003b642c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W 0x003b6430 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003b6434 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003b6438 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003b643c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003b6440 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003b6444 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003b6448 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003b644c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003b6450 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003b6454 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003b6458 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003b645c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003b6460 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003b6464 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003b6468 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003b646c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003b6470 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003b6474 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W 0x003b64a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P 0x003b64a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N 0x003b64ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W 0x003b64b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W 0x003b64b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W 0x003b64b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W 0x003b64bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W 0x003b64c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W 0x003b64c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W 0x003b64c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W 0x003b64cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W 0x003b64d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003b64d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003b64d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003b64dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003b64e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003b64e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003b64e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003b64ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003b64f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003b64f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003b64f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003b64fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003b6500 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003b6504 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003b6508 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003b650c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003b6510 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003b6514 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x003b6528 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x003b652c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003b6530 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003b6534 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W 0x003b6538 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003b653c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x003b6548 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x003b654c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003b6550 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003b6554 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W 0x003b6558 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003b655c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_DATA_DLY 0x003b6560 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_CONTROL 0x003b6564 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_0 0x003b6570 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_1 0x003b6574 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_2 0x003b6578 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_3 0x003b657c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_0 0x003b6580 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_1 0x003b6584 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_2 0x003b6588 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_3 0x003b658c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_STATUS 0x003b6590 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_CLEAR 0x003b6594 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL 0x003b65a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL 0x003b65a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_CLOCK_PAD_DISABLE 0x003b65a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_WR_PREAMBLE_MODE 0x003b65ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ 0x003b65b0 /* PHYBIST mode VDL step select adjustment register */
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_1_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_ddr40_phy_word_lane_1_1.h b/include/linux/brcmstb/7425b0/bchp_ddr40_phy_word_lane_1_1.h
new file mode 100644
index 0000000..cf85e15
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_ddr40_phy_word_lane_1_1.h
@@ -0,0 +1,139 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Apr 11 12:04:18 2011
+ *                 MD5 Checksum         8cf142ad25caa9f873c54e8bb2bb1755
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7425/rdb/b0/bchp_ddr40_phy_word_lane_1_1.h $
+ * 
+ * Hydra_Software_Devel/2   4/11/11 11:58p vanessah
+ * SW7425-112: Update rdb files for 7425 B0.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_1_1_H__
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_1_1 - DDR40 DDR40 word lane #1 control registers 1
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN 0x003c6400 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W 0x003c6404 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P 0x003c6408 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N 0x003c640c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W 0x003c6410 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W 0x003c6414 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W 0x003c6418 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W 0x003c641c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W 0x003c6420 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W 0x003c6424 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W 0x003c6428 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W 0x003c642c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W 0x003c6430 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003c6434 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003c6438 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003c643c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003c6440 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003c6444 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003c6448 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003c644c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003c6450 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003c6454 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003c6458 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003c645c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003c6460 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003c6464 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003c6468 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003c646c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003c6470 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003c6474 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W 0x003c64a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P 0x003c64a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N 0x003c64ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W 0x003c64b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W 0x003c64b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W 0x003c64b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W 0x003c64bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W 0x003c64c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W 0x003c64c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W 0x003c64c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W 0x003c64cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W 0x003c64d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003c64d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003c64d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003c64dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003c64e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003c64e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003c64e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003c64ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003c64f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003c64f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003c64f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003c64fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003c6500 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003c6504 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003c6508 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003c650c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003c6510 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003c6514 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_P 0x003c6528 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_N 0x003c652c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003c6530 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003c6534 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_W 0x003c6538 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003c653c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_P 0x003c6548 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_N 0x003c654c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003c6550 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003c6554 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_W 0x003c6558 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003c655c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_DATA_DLY 0x003c6560 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_CONTROL 0x003c6564 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_0 0x003c6570 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_1 0x003c6574 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_2 0x003c6578 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_3 0x003c657c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_0 0x003c6580 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_1 0x003c6584 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_2 0x003c6588 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_3 0x003c658c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_STATUS 0x003c6590 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_CLEAR 0x003c6594 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL 0x003c65a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL 0x003c65a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_CLOCK_PAD_DISABLE 0x003c65a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_WR_PREAMBLE_MODE 0x003c65ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ 0x003c65b0 /* PHYBIST mode VDL step select adjustment register */
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_1_1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_ebi.h b/include/linux/brcmstb/7425b0/bchp_ebi.h
new file mode 100644
index 0000000..cbc19d2
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_ebi.h
@@ -0,0 +1,1708 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:42 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EBI_H__
+#define BCHP_EBI_H__
+
+/***************************************************************************
+ *EBI - EBI Registers
+ ***************************************************************************/
+#define BCHP_EBI_CS_BASE_0                       0x00419800 /* EBI CS Base 0 Register */
+#define BCHP_EBI_CS_CONFIG_0                     0x00419804 /* EBI CS Config 0 Register */
+#define BCHP_EBI_CS_BASE_1                       0x00419808 /* EBI CS Base 1 Register */
+#define BCHP_EBI_CS_CONFIG_1                     0x0041980c /* EBI CS Config 1 Register */
+#define BCHP_EBI_CS_BASE_2                       0x00419810 /* EBI CS Base 2 Register */
+#define BCHP_EBI_CS_CONFIG_2                     0x00419814 /* EBI CS Config 2 Register */
+#define BCHP_EBI_CS_BASE_3                       0x00419818 /* EBI CS Base 3 Register */
+#define BCHP_EBI_CS_CONFIG_3                     0x0041981c /* EBI CS Config 3 Register */
+#define BCHP_EBI_CS_BASE_4                       0x00419820 /* EBI CS Base 4 Register */
+#define BCHP_EBI_CS_CONFIG_4                     0x00419824 /* EBI CS Config 4 Register */
+#define BCHP_EBI_CS_BASE_5                       0x00419828 /* EBI CS Base 5 Register */
+#define BCHP_EBI_CS_CONFIG_5                     0x0041982c /* EBI CS Config 5 Register */
+#define BCHP_EBI_BURST_CFG_0                     0x00419840 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_1                     0x00419844 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_2                     0x00419848 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_3                     0x0041984c /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_4                     0x00419850 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_5                     0x00419854 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_ECR                             0x00419900 /* EBI Configuration Register */
+#define BCHP_EBI_CS_TRISTATE_CFG                 0x00419918 /* EBI CS Tristate Configuration Register */
+#define BCHP_EBI_TA_CFG                          0x0041991c /* EBI TA Configuration Register */
+#define BCHP_EBI_CS_SPI_SELECT                   0x00419920 /* SPI CS Select */
+#define BCHP_EBI_ARRAY_ADDRESS                   0x004199f0 /* EBI Data Array Address */
+
+/***************************************************************************
+ *CS_BASE_0 - EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_0 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_0_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT                         13
+
+/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_0_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_0 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_0_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_0_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_0 - EBI CS Config 0 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_0_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT                       0x00000001
+
+/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_0_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_0_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_0_le_SHIFT                              10
+
+/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_0_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_0_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT                       4
+
+/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_0_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT                        0x00000001
+
+/***************************************************************************
+ *CS_BASE_1 - EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_1 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_1_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_1_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_1 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_1_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_1_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_1_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_1 - EBI CS Config 1 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_1_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_1_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_1_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_1_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_1_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_1_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_1_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_2 - EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_2 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_2_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_2_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_2 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_2_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_2_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_2_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_2 - EBI CS Config 2 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_2_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_2_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_2_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_2_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_2_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_2_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_2_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_3 - EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_3 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_3_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_3_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_3 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_3_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_3_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_3_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_3 - EBI CS Config 3 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_3_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_3_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_3_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_3_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_3_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_3_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_3_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_4 - EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_4 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_4_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_4_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_4 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_4_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_4_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_4_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_4 - EBI CS Config 4 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_4_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_4_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_4_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_4_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_4_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_4_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_4_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_5 - EBI CS Base 5 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_5 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_5_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_5_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_5_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_5 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_5_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_5_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_5 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_5_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_5_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_5_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_5_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_5_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_5_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_5_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_5 - EBI CS Config 5 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_5 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_5_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_5_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_5_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_5_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_5_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_5_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_5 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_5_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_5_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_5_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_5 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_5_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_5_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_5_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_5_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_5_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_5_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_5_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_5_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_5_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_5 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_5_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_5_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_5_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_5 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_5_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_5_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_5_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_5 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_5_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_5_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_5_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_5 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_5_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_5_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_5_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_5 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_5_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_5_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_5_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_5 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_5_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_5_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_5_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_5 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_5_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_5_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_5_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_5 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_5_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_5_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_5_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_5_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_5_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_5_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_5_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_5_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_5_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_0_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_0_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_0 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_0_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_0_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_0_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_0_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_0_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_1_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_1_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_1 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_1_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_1_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_1_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_1_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_1_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_2_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_2_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_2 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_2_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_2_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_2_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_2_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_2_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_3_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_3_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_3 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_3_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_3_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_3_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_3_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_3_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_4_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_4_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_4 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_4_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_4_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_4_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_4_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_4_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_5 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_5 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_5 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_5_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_5_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_5_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_5 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_5 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_5 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_5 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_5_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_5_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_5 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_5 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_5_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_5_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_5_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_5 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_5 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_5 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_5_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_5_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_5 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_5_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_5_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_5_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_5 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_5_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_5_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_5 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_5_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_5_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_5_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_5 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_5_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_5_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_5_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *ECR - EBI Configuration Register
+ ***************************************************************************/
+/* EBI :: ECR :: reserved0 [31:28] */
+#define BCHP_EBI_ECR_reserved0_MASK                                0xf0000000
+#define BCHP_EBI_ECR_reserved0_SHIFT                               28
+
+/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK                            0x08000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT                           27
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT                         0x00000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only  1
+
+/* EBI :: ECR :: reserved1 [26:26] */
+#define BCHP_EBI_ECR_reserved1_MASK                                0x04000000
+#define BCHP_EBI_ECR_reserved1_SHIFT                               26
+
+/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK                          0x02000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT                         25
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT                       0x00000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10         0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00         1
+
+/* EBI :: ECR :: reserved2 [24:11] */
+#define BCHP_EBI_ECR_reserved2_MASK                                0x01fff800
+#define BCHP_EBI_ECR_reserved2_SHIFT                               11
+
+/* EBI :: ECR :: timeout_count [10:00] */
+#define BCHP_EBI_ECR_timeout_count_MASK                            0x000007ff
+#define BCHP_EBI_ECR_timeout_count_SHIFT                           0
+#define BCHP_EBI_ECR_timeout_count_DEFAULT                         0x00000400
+
+/***************************************************************************
+ *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
+ ***************************************************************************/
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK             0x80000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT            31
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK             0x40000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT            30
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK             0x20000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT            29
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK             0x10000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT            28
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK            0x08000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT           27
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK            0x04000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT           26
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK         0x02000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT        25
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK         0x01000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT        24
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:06] */
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK                    0x00ffffc0
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT                   6
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs5 [05:05] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_MASK             0x00000020
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_SHIFT            5
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK             0x00000010
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT            4
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK             0x00000008
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT            3
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK             0x00000004
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT            2
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK             0x00000002
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT            1
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK             0x00000001
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT            0
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TA_CFG - EBI TA Configuration Register
+ ***************************************************************************/
+/* EBI :: TA_CFG :: reserved0 [31:04] */
+#define BCHP_EBI_TA_CFG_reserved0_MASK                             0xfffffff0
+#define BCHP_EBI_TA_CFG_reserved0_SHIFT                            4
+
+/* EBI :: TA_CFG :: use_ta3 [03:03] */
+#define BCHP_EBI_TA_CFG_use_ta3_MASK                               0x00000008
+#define BCHP_EBI_TA_CFG_use_ta3_SHIFT                              3
+#define BCHP_EBI_TA_CFG_use_ta3_DEFAULT                            0x00000001
+
+/* EBI :: TA_CFG :: use_ta2 [02:02] */
+#define BCHP_EBI_TA_CFG_use_ta2_MASK                               0x00000004
+#define BCHP_EBI_TA_CFG_use_ta2_SHIFT                              2
+#define BCHP_EBI_TA_CFG_use_ta2_DEFAULT                            0x00000000
+
+/* EBI :: TA_CFG :: use_ta1 [01:01] */
+#define BCHP_EBI_TA_CFG_use_ta1_MASK                               0x00000002
+#define BCHP_EBI_TA_CFG_use_ta1_SHIFT                              1
+#define BCHP_EBI_TA_CFG_use_ta1_DEFAULT                            0x00000001
+
+/* EBI :: TA_CFG :: reserved1 [00:00] */
+#define BCHP_EBI_TA_CFG_reserved1_MASK                             0x00000001
+#define BCHP_EBI_TA_CFG_reserved1_SHIFT                            0
+
+/***************************************************************************
+ *CS_SPI_SELECT - SPI CS Select
+ ***************************************************************************/
+/* EBI :: CS_SPI_SELECT :: reserved0 [31:16] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK                      0xffff0000
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT                     16
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_7_USES_SPI [15:15] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_MASK              0x00008000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_SHIFT             15
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK              0x00004000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT             14
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK              0x00002000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT             13
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK              0x00001000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT             12
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK              0x00000800
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT             11
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK              0x00000400
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT             10
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK              0x00000200
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT             9
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK              0x00000100
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT             8
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_7_SEL [07:07] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_MASK               0x00000080
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_SHIFT              7
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK               0x00000040
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT              6
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK               0x00000020
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT              5
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK               0x00000010
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT              4
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK               0x00000008
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT              3
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK               0x00000004
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT              2
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK               0x00000002
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT              1
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK               0x00000001
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT              0
+
+/***************************************************************************
+ *ARRAY_ADDRESS - EBI Data Array Address
+ ***************************************************************************/
+/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK                        0xfffffe00
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT                       9
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT                     0x00000000
+
+/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK                      0x000001f8
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT                     3
+
+/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK                         0x00000007
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT                        0
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE                            0x00419a00
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_START                           0
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_END                             127
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE                    32
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+/* EBI :: DATA_ARRAYi :: WORD [31:00] */
+#define BCHP_EBI_DATA_ARRAYi_WORD_MASK                             0xffffffff
+#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT                            0
+
+
+#endif /* #ifndef BCHP_EBI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_edu.h b/include/linux/brcmstb/7425b0/bchp_edu.h
new file mode 100644
index 0000000..2d2420a
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_edu.h
@@ -0,0 +1,190 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:42 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EDU_H__
+#define BCHP_EDU_H__
+
+/***************************************************************************
+ *EDU - EDU Registers
+ ***************************************************************************/
+#define BCHP_EDU_CONFIG                          0x0041bc00 /* EDU Config */
+#define BCHP_EDU_DRAM_ADDR                       0x0041bc04 /* DRAM Address for transaction */
+#define BCHP_EDU_EXT_ADDR                        0x0041bc08 /* External Address for transaction */
+#define BCHP_EDU_LENGTH                          0x0041bc0c /* Length of transaction */
+#define BCHP_EDU_CMD                             0x0041bc10 /* Command Type and Start */
+#define BCHP_EDU_STOP                            0x0041bc14 /* Stop */
+#define BCHP_EDU_STATUS                          0x0041bc18 /* EDU Status bits */
+#define BCHP_EDU_DONE                            0x0041bc1c /* EDU Done bits */
+#define BCHP_EDU_ERR_STATUS                      0x0041bc20 /* EDU Error Status */
+
+/***************************************************************************
+ *CONFIG - EDU Config
+ ***************************************************************************/
+/* EDU :: CONFIG :: reserved0 [31:03] */
+#define BCHP_EDU_CONFIG_reserved0_MASK                             0xfffffff8
+#define BCHP_EDU_CONFIG_reserved0_SHIFT                            3
+
+/* EDU :: CONFIG :: Swap [02:01] */
+#define BCHP_EDU_CONFIG_Swap_MASK                                  0x00000006
+#define BCHP_EDU_CONFIG_Swap_SHIFT                                 1
+#define BCHP_EDU_CONFIG_Swap_DEFAULT                               0x00000000
+
+/* EDU :: CONFIG :: Mode [00:00] */
+#define BCHP_EDU_CONFIG_Mode_MASK                                  0x00000001
+#define BCHP_EDU_CONFIG_Mode_SHIFT                                 0
+#define BCHP_EDU_CONFIG_Mode_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *DRAM_ADDR - DRAM Address for transaction
+ ***************************************************************************/
+/* EDU :: DRAM_ADDR :: Address [31:02] */
+#define BCHP_EDU_DRAM_ADDR_Address_MASK                            0xfffffffc
+#define BCHP_EDU_DRAM_ADDR_Address_SHIFT                           2
+#define BCHP_EDU_DRAM_ADDR_Address_DEFAULT                         0x00000000
+
+/* EDU :: DRAM_ADDR :: reserved0 [01:00] */
+#define BCHP_EDU_DRAM_ADDR_reserved0_MASK                          0x00000003
+#define BCHP_EDU_DRAM_ADDR_reserved0_SHIFT                         0
+
+/***************************************************************************
+ *EXT_ADDR - External Address for transaction
+ ***************************************************************************/
+/* EDU :: EXT_ADDR :: Address [31:02] */
+#define BCHP_EDU_EXT_ADDR_Address_MASK                             0xfffffffc
+#define BCHP_EDU_EXT_ADDR_Address_SHIFT                            2
+#define BCHP_EDU_EXT_ADDR_Address_DEFAULT                          0x00000000
+
+/* EDU :: EXT_ADDR :: reserved0 [01:00] */
+#define BCHP_EDU_EXT_ADDR_reserved0_MASK                           0x00000003
+#define BCHP_EDU_EXT_ADDR_reserved0_SHIFT                          0
+
+/***************************************************************************
+ *LENGTH - Length of transaction
+ ***************************************************************************/
+/* EDU :: LENGTH :: reserved0 [31:10] */
+#define BCHP_EDU_LENGTH_reserved0_MASK                             0xfffffc00
+#define BCHP_EDU_LENGTH_reserved0_SHIFT                            10
+
+/* EDU :: LENGTH :: Length [09:00] */
+#define BCHP_EDU_LENGTH_Length_MASK                                0x000003ff
+#define BCHP_EDU_LENGTH_Length_SHIFT                               0
+#define BCHP_EDU_LENGTH_Length_DEFAULT                             0x00000000
+
+/***************************************************************************
+ *CMD - Command Type and Start
+ ***************************************************************************/
+/* EDU :: CMD :: reserved0 [31:01] */
+#define BCHP_EDU_CMD_reserved0_MASK                                0xfffffffe
+#define BCHP_EDU_CMD_reserved0_SHIFT                               1
+
+/* EDU :: CMD :: Cmd [00:00] */
+#define BCHP_EDU_CMD_Cmd_MASK                                      0x00000001
+#define BCHP_EDU_CMD_Cmd_SHIFT                                     0
+#define BCHP_EDU_CMD_Cmd_DEFAULT                                   0x00000000
+
+/***************************************************************************
+ *STOP - Stop
+ ***************************************************************************/
+/* EDU :: STOP :: reserved0 [31:01] */
+#define BCHP_EDU_STOP_reserved0_MASK                               0xfffffffe
+#define BCHP_EDU_STOP_reserved0_SHIFT                              1
+
+/* EDU :: STOP :: Stop [00:00] */
+#define BCHP_EDU_STOP_Stop_MASK                                    0x00000001
+#define BCHP_EDU_STOP_Stop_SHIFT                                   0
+#define BCHP_EDU_STOP_Stop_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *STATUS - EDU Status bits
+ ***************************************************************************/
+/* EDU :: STATUS :: reserved0 [31:02] */
+#define BCHP_EDU_STATUS_reserved0_MASK                             0xfffffffc
+#define BCHP_EDU_STATUS_reserved0_SHIFT                            2
+
+/* EDU :: STATUS :: Pending [01:01] */
+#define BCHP_EDU_STATUS_Pending_MASK                               0x00000002
+#define BCHP_EDU_STATUS_Pending_SHIFT                              1
+#define BCHP_EDU_STATUS_Pending_DEFAULT                            0x00000000
+
+/* EDU :: STATUS :: Active [00:00] */
+#define BCHP_EDU_STATUS_Active_MASK                                0x00000001
+#define BCHP_EDU_STATUS_Active_SHIFT                               0
+#define BCHP_EDU_STATUS_Active_DEFAULT                             0x00000000
+
+/***************************************************************************
+ *DONE - EDU Done bits
+ ***************************************************************************/
+/* EDU :: DONE :: reserved0 [31:02] */
+#define BCHP_EDU_DONE_reserved0_MASK                               0xfffffffc
+#define BCHP_EDU_DONE_reserved0_SHIFT                              2
+
+/* EDU :: DONE :: Done [01:00] */
+#define BCHP_EDU_DONE_Done_MASK                                    0x00000003
+#define BCHP_EDU_DONE_Done_SHIFT                                   0
+#define BCHP_EDU_DONE_Done_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *ERR_STATUS - EDU Error Status
+ ***************************************************************************/
+/* EDU :: ERR_STATUS :: reserved0 [31:04] */
+#define BCHP_EDU_ERR_STATUS_reserved0_MASK                         0xfffffff0
+#define BCHP_EDU_ERR_STATUS_reserved0_SHIFT                        4
+
+/* EDU :: ERR_STATUS :: NandWrErr [03:03] */
+#define BCHP_EDU_ERR_STATUS_NandWrErr_MASK                         0x00000008
+#define BCHP_EDU_ERR_STATUS_NandWrErr_SHIFT                        3
+#define BCHP_EDU_ERR_STATUS_NandWrErr_DEFAULT                      0x00000000
+
+/* EDU :: ERR_STATUS :: NandECCuncor [02:02] */
+#define BCHP_EDU_ERR_STATUS_NandECCuncor_MASK                      0x00000004
+#define BCHP_EDU_ERR_STATUS_NandECCuncor_SHIFT                     2
+#define BCHP_EDU_ERR_STATUS_NandECCuncor_DEFAULT                   0x00000000
+
+/* EDU :: ERR_STATUS :: NandECCcor [01:01] */
+#define BCHP_EDU_ERR_STATUS_NandECCcor_MASK                        0x00000002
+#define BCHP_EDU_ERR_STATUS_NandECCcor_SHIFT                       1
+#define BCHP_EDU_ERR_STATUS_NandECCcor_DEFAULT                     0x00000000
+
+/* EDU :: ERR_STATUS :: ErrAck [00:00] */
+#define BCHP_EDU_ERR_STATUS_ErrAck_MASK                            0x00000001
+#define BCHP_EDU_ERR_STATUS_ErrAck_SHIFT                           0
+#define BCHP_EDU_ERR_STATUS_ErrAck_DEFAULT                         0x00000000
+
+#endif /* #ifndef BCHP_EDU_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_gio.h b/include/linux/brcmstb/7425b0/bchp_gio.h
new file mode 100644
index 0000000..a3b9a36
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_gio.h
@@ -0,0 +1,368 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:42 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_GIO_H__
+#define BCHP_GIO_H__
+
+/***************************************************************************
+ *GIO - GPIO
+ ***************************************************************************/
+#define BCHP_GIO_ODEN_LO                         0x00406700 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE [31:0] */
+#define BCHP_GIO_DATA_LO                         0x00406704 /* GENERAL PURPOSE I/O DATA [31:0] */
+#define BCHP_GIO_IODIR_LO                        0x00406708 /* GENERAL PURPOSE I/O DIRECTION [31:0] */
+#define BCHP_GIO_EC_LO                           0x0040670c /* GENERAL PURPOSE I/O EDGE CONFIGURATION [31:0] */
+#define BCHP_GIO_EI_LO                           0x00406710 /* GENERAL PURPOSE I/O EDGE INSENSITIVE [31:0] */
+#define BCHP_GIO_MASK_LO                         0x00406714 /* GENERAL PURPOSE I/O INTERRUPT MASK [31:0] */
+#define BCHP_GIO_LEVEL_LO                        0x00406718 /* GENERAL PURPOSE I/O INTERRUPT TYPE [31:0] */
+#define BCHP_GIO_STAT_LO                         0x0040671c /* GENERAL PURPOSE I/O INTERRUPT STATUS [31:0] */
+#define BCHP_GIO_ODEN_HI                         0x00406720 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE [63:32] */
+#define BCHP_GIO_DATA_HI                         0x00406724 /* GENERAL PURPOSE I/O DATA [63:32] */
+#define BCHP_GIO_IODIR_HI                        0x00406728 /* GENERAL PURPOSE I/O DIRECTION [63:32] */
+#define BCHP_GIO_EC_HI                           0x0040672c /* GENERAL PURPOSE I/O EDGE CONFIGURATION [63:32] */
+#define BCHP_GIO_EI_HI                           0x00406730 /* GENERAL PURPOSE I/O EDGE INSENSITIVE [63:32] */
+#define BCHP_GIO_MASK_HI                         0x00406734 /* GENERAL PURPOSE I/O INTERRUPT MASK [63:32] */
+#define BCHP_GIO_LEVEL_HI                        0x00406738 /* GENERAL PURPOSE I/O INTERRUPT TYPE [63:32] */
+#define BCHP_GIO_STAT_HI                         0x0040673c /* GENERAL PURPOSE I/O INTERRUPT STATUS [63:32] */
+#define BCHP_GIO_ODEN_EXT                        0x00406740 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE [95:64] (GPIO[89:64], AON_SGPIO[5:4], SGPIO[3:0]) */
+#define BCHP_GIO_DATA_EXT                        0x00406744 /* GENERAL PURPOSE I/O DATA [95:64] (GPIO[89:64], AON_SGPIO[5:4], SGPIO[3:0]) */
+#define BCHP_GIO_IODIR_EXT                       0x00406748 /* GENERAL PURPOSE I/O DIRECTION [95:64] (GPIO[89:64], AON_SGPIO[5:4], SGPIO[3:0]) */
+#define BCHP_GIO_EC_EXT                          0x0040674c /* GENERAL PURPOSE I/O EDGE CONFIGURATION [95:64] (GPIO[89:64], AON_SGPIO[5:4], SGPIO[3:0]) */
+#define BCHP_GIO_EI_EXT                          0x00406750 /* GENERAL PURPOSE I/O EDGE INSENSITIVE [95:64] (GPIO[89:64], AON_SGPIO[5:4], SGPIO[3:0]) */
+#define BCHP_GIO_MASK_EXT                        0x00406754 /* GENERAL PURPOSE I/O INTERRUPT MASK [95:64] (GPIO[89:64], AON_SGPIO[5:4], SGPIO[3:0]) */
+#define BCHP_GIO_LEVEL_EXT                       0x00406758 /* GENERAL PURPOSE I/O INTERRUPT TYPE [95:64] (GPIO[89:64], AON_SGPIO[5:4], SGPIO[3:0]) */
+#define BCHP_GIO_STAT_EXT                        0x0040675c /* GENERAL PURPOSE I/O INTERRUPT STATUS [95:64] (GPIO[89:64], AON_SGPIO[5:4], SGPIO[3:0]) */
+#define BCHP_GIO_ODEN_EXT_HI                     0x00406760 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE [116:96] (GPIO[110:90]) */
+#define BCHP_GIO_DATA_EXT_HI                     0x00406764 /* GENERAL PURPOSE I/O DATA [116:96] (GPIO[110:90]) */
+#define BCHP_GIO_IODIR_EXT_HI                    0x00406768 /* GENERAL PURPOSE I/O DIRECTION [116:96] (GPIO[110:90]) */
+#define BCHP_GIO_EC_EXT_HI                       0x0040676c /* GENERAL PURPOSE I/O EDGE CONFIGURATION [116:96] (GPIO[110:90]) */
+#define BCHP_GIO_EI_EXT_HI                       0x00406770 /* GENERAL PURPOSE I/O EDGE INSENSITIVE [116:96] (GPIO[110:90]) */
+#define BCHP_GIO_MASK_EXT_HI                     0x00406774 /* GENERAL PURPOSE I/O INTERRUPT MASK [116:96] (GPIO[110:90]) */
+#define BCHP_GIO_LEVEL_EXT_HI                    0x00406778 /* GENERAL PURPOSE I/O INTERRUPT TYPE [116:96] (GPIO[110:90]) */
+#define BCHP_GIO_STAT_EXT_HI                     0x0040677c /* GENERAL PURPOSE I/O INTERRUPT STATUS [116:96] (GPIO[110:90]) */
+
+/***************************************************************************
+ *ODEN_LO - GENERAL PURPOSE I/O OPEN DRAIN ENABLE [31:0]
+ ***************************************************************************/
+/* GIO :: ODEN_LO :: oden [31:00] */
+#define BCHP_GIO_ODEN_LO_oden_MASK                                 0xffffffff
+#define BCHP_GIO_ODEN_LO_oden_SHIFT                                0
+#define BCHP_GIO_ODEN_LO_oden_DEFAULT                              0x00000000
+
+/***************************************************************************
+ *DATA_LO - GENERAL PURPOSE I/O DATA [31:0]
+ ***************************************************************************/
+/* GIO :: DATA_LO :: data [31:00] */
+#define BCHP_GIO_DATA_LO_data_MASK                                 0xffffffff
+#define BCHP_GIO_DATA_LO_data_SHIFT                                0
+#define BCHP_GIO_DATA_LO_data_DEFAULT                              0x00000000
+
+/***************************************************************************
+ *IODIR_LO - GENERAL PURPOSE I/O DIRECTION [31:0]
+ ***************************************************************************/
+/* GIO :: IODIR_LO :: iodir [31:00] */
+#define BCHP_GIO_IODIR_LO_iodir_MASK                               0xffffffff
+#define BCHP_GIO_IODIR_LO_iodir_SHIFT                              0
+#define BCHP_GIO_IODIR_LO_iodir_DEFAULT                            0xffffffff
+
+/***************************************************************************
+ *EC_LO - GENERAL PURPOSE I/O EDGE CONFIGURATION [31:0]
+ ***************************************************************************/
+/* GIO :: EC_LO :: edge_config [31:00] */
+#define BCHP_GIO_EC_LO_edge_config_MASK                            0xffffffff
+#define BCHP_GIO_EC_LO_edge_config_SHIFT                           0
+#define BCHP_GIO_EC_LO_edge_config_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *EI_LO - GENERAL PURPOSE I/O EDGE INSENSITIVE [31:0]
+ ***************************************************************************/
+/* GIO :: EI_LO :: edge_insensitive [31:00] */
+#define BCHP_GIO_EI_LO_edge_insensitive_MASK                       0xffffffff
+#define BCHP_GIO_EI_LO_edge_insensitive_SHIFT                      0
+#define BCHP_GIO_EI_LO_edge_insensitive_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *MASK_LO - GENERAL PURPOSE I/O INTERRUPT MASK [31:0]
+ ***************************************************************************/
+/* GIO :: MASK_LO :: irq_mask [31:00] */
+#define BCHP_GIO_MASK_LO_irq_mask_MASK                             0xffffffff
+#define BCHP_GIO_MASK_LO_irq_mask_SHIFT                            0
+#define BCHP_GIO_MASK_LO_irq_mask_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *LEVEL_LO - GENERAL PURPOSE I/O INTERRUPT TYPE [31:0]
+ ***************************************************************************/
+/* GIO :: LEVEL_LO :: level [31:00] */
+#define BCHP_GIO_LEVEL_LO_level_MASK                               0xffffffff
+#define BCHP_GIO_LEVEL_LO_level_SHIFT                              0
+#define BCHP_GIO_LEVEL_LO_level_DEFAULT                            0x00000000
+
+/***************************************************************************
+ *STAT_LO - GENERAL PURPOSE I/O INTERRUPT STATUS [31:0]
+ ***************************************************************************/
+/* GIO :: STAT_LO :: irq_status [31:00] */
+#define BCHP_GIO_STAT_LO_irq_status_MASK                           0xffffffff
+#define BCHP_GIO_STAT_LO_irq_status_SHIFT                          0
+#define BCHP_GIO_STAT_LO_irq_status_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *ODEN_HI - GENERAL PURPOSE I/O OPEN DRAIN ENABLE [63:32]
+ ***************************************************************************/
+/* GIO :: ODEN_HI :: oden [31:00] */
+#define BCHP_GIO_ODEN_HI_oden_MASK                                 0xffffffff
+#define BCHP_GIO_ODEN_HI_oden_SHIFT                                0
+#define BCHP_GIO_ODEN_HI_oden_DEFAULT                              0x00000000
+
+/***************************************************************************
+ *DATA_HI - GENERAL PURPOSE I/O DATA [63:32]
+ ***************************************************************************/
+/* GIO :: DATA_HI :: data [31:00] */
+#define BCHP_GIO_DATA_HI_data_MASK                                 0xffffffff
+#define BCHP_GIO_DATA_HI_data_SHIFT                                0
+#define BCHP_GIO_DATA_HI_data_DEFAULT                              0x00000000
+
+/***************************************************************************
+ *IODIR_HI - GENERAL PURPOSE I/O DIRECTION [63:32]
+ ***************************************************************************/
+/* GIO :: IODIR_HI :: iodir [31:00] */
+#define BCHP_GIO_IODIR_HI_iodir_MASK                               0xffffffff
+#define BCHP_GIO_IODIR_HI_iodir_SHIFT                              0
+#define BCHP_GIO_IODIR_HI_iodir_DEFAULT                            0x000001ff
+
+/***************************************************************************
+ *EC_HI - GENERAL PURPOSE I/O EDGE CONFIGURATION [63:32]
+ ***************************************************************************/
+/* GIO :: EC_HI :: edge_config [31:00] */
+#define BCHP_GIO_EC_HI_edge_config_MASK                            0xffffffff
+#define BCHP_GIO_EC_HI_edge_config_SHIFT                           0
+#define BCHP_GIO_EC_HI_edge_config_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *EI_HI - GENERAL PURPOSE I/O EDGE INSENSITIVE [63:32]
+ ***************************************************************************/
+/* GIO :: EI_HI :: edge_insensitive [31:00] */
+#define BCHP_GIO_EI_HI_edge_insensitive_MASK                       0xffffffff
+#define BCHP_GIO_EI_HI_edge_insensitive_SHIFT                      0
+#define BCHP_GIO_EI_HI_edge_insensitive_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *MASK_HI - GENERAL PURPOSE I/O INTERRUPT MASK [63:32]
+ ***************************************************************************/
+/* GIO :: MASK_HI :: irq_mask [31:00] */
+#define BCHP_GIO_MASK_HI_irq_mask_MASK                             0xffffffff
+#define BCHP_GIO_MASK_HI_irq_mask_SHIFT                            0
+#define BCHP_GIO_MASK_HI_irq_mask_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *LEVEL_HI - GENERAL PURPOSE I/O INTERRUPT TYPE [63:32]
+ ***************************************************************************/
+/* GIO :: LEVEL_HI :: level [31:00] */
+#define BCHP_GIO_LEVEL_HI_level_MASK                               0xffffffff
+#define BCHP_GIO_LEVEL_HI_level_SHIFT                              0
+#define BCHP_GIO_LEVEL_HI_level_DEFAULT                            0x00000000
+
+/***************************************************************************
+ *STAT_HI - GENERAL PURPOSE I/O INTERRUPT STATUS [63:32]
+ ***************************************************************************/
+/* GIO :: STAT_HI :: irq_status [31:00] */
+#define BCHP_GIO_STAT_HI_irq_status_MASK                           0xffffffff
+#define BCHP_GIO_STAT_HI_irq_status_SHIFT                          0
+#define BCHP_GIO_STAT_HI_irq_status_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *ODEN_EXT - GENERAL PURPOSE I/O OPEN DRAIN ENABLE [95:64] (GPIO[89:64], AON_SGPIO[5:4], SGPIO[3:0])
+ ***************************************************************************/
+/* GIO :: ODEN_EXT :: oden [31:00] */
+#define BCHP_GIO_ODEN_EXT_oden_MASK                                0xffffffff
+#define BCHP_GIO_ODEN_EXT_oden_SHIFT                               0
+#define BCHP_GIO_ODEN_EXT_oden_DEFAULT                             0x00000000
+
+/***************************************************************************
+ *DATA_EXT - GENERAL PURPOSE I/O DATA [95:64] (GPIO[89:64], AON_SGPIO[5:4], SGPIO[3:0])
+ ***************************************************************************/
+/* GIO :: DATA_EXT :: data [31:00] */
+#define BCHP_GIO_DATA_EXT_data_MASK                                0xffffffff
+#define BCHP_GIO_DATA_EXT_data_SHIFT                               0
+#define BCHP_GIO_DATA_EXT_data_DEFAULT                             0x00000000
+
+/***************************************************************************
+ *IODIR_EXT - GENERAL PURPOSE I/O DIRECTION [95:64] (GPIO[89:64], AON_SGPIO[5:4], SGPIO[3:0])
+ ***************************************************************************/
+/* GIO :: IODIR_EXT :: iodir [31:00] */
+#define BCHP_GIO_IODIR_EXT_iodir_MASK                              0xffffffff
+#define BCHP_GIO_IODIR_EXT_iodir_SHIFT                             0
+#define BCHP_GIO_IODIR_EXT_iodir_DEFAULT                           0xffffffff
+
+/***************************************************************************
+ *EC_EXT - GENERAL PURPOSE I/O EDGE CONFIGURATION [95:64] (GPIO[89:64], AON_SGPIO[5:4], SGPIO[3:0])
+ ***************************************************************************/
+/* GIO :: EC_EXT :: edge_config [31:00] */
+#define BCHP_GIO_EC_EXT_edge_config_MASK                           0xffffffff
+#define BCHP_GIO_EC_EXT_edge_config_SHIFT                          0
+#define BCHP_GIO_EC_EXT_edge_config_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *EI_EXT - GENERAL PURPOSE I/O EDGE INSENSITIVE [95:64] (GPIO[89:64], AON_SGPIO[5:4], SGPIO[3:0])
+ ***************************************************************************/
+/* GIO :: EI_EXT :: edge_insensitive [31:00] */
+#define BCHP_GIO_EI_EXT_edge_insensitive_MASK                      0xffffffff
+#define BCHP_GIO_EI_EXT_edge_insensitive_SHIFT                     0
+#define BCHP_GIO_EI_EXT_edge_insensitive_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *MASK_EXT - GENERAL PURPOSE I/O INTERRUPT MASK [95:64] (GPIO[89:64], AON_SGPIO[5:4], SGPIO[3:0])
+ ***************************************************************************/
+/* GIO :: MASK_EXT :: irq_mask [31:00] */
+#define BCHP_GIO_MASK_EXT_irq_mask_MASK                            0xffffffff
+#define BCHP_GIO_MASK_EXT_irq_mask_SHIFT                           0
+#define BCHP_GIO_MASK_EXT_irq_mask_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *LEVEL_EXT - GENERAL PURPOSE I/O INTERRUPT TYPE [95:64] (GPIO[89:64], AON_SGPIO[5:4], SGPIO[3:0])
+ ***************************************************************************/
+/* GIO :: LEVEL_EXT :: level [31:00] */
+#define BCHP_GIO_LEVEL_EXT_level_MASK                              0xffffffff
+#define BCHP_GIO_LEVEL_EXT_level_SHIFT                             0
+#define BCHP_GIO_LEVEL_EXT_level_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *STAT_EXT - GENERAL PURPOSE I/O INTERRUPT STATUS [95:64] (GPIO[89:64], AON_SGPIO[5:4], SGPIO[3:0])
+ ***************************************************************************/
+/* GIO :: STAT_EXT :: irq_status [31:00] */
+#define BCHP_GIO_STAT_EXT_irq_status_MASK                          0xffffffff
+#define BCHP_GIO_STAT_EXT_irq_status_SHIFT                         0
+#define BCHP_GIO_STAT_EXT_irq_status_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *ODEN_EXT_HI - GENERAL PURPOSE I/O OPEN DRAIN ENABLE [116:96] (GPIO[110:90])
+ ***************************************************************************/
+/* GIO :: ODEN_EXT_HI :: reserved0 [31:21] */
+#define BCHP_GIO_ODEN_EXT_HI_reserved0_MASK                        0xffe00000
+#define BCHP_GIO_ODEN_EXT_HI_reserved0_SHIFT                       21
+
+/* GIO :: ODEN_EXT_HI :: oden [20:00] */
+#define BCHP_GIO_ODEN_EXT_HI_oden_MASK                             0x001fffff
+#define BCHP_GIO_ODEN_EXT_HI_oden_SHIFT                            0
+#define BCHP_GIO_ODEN_EXT_HI_oden_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *DATA_EXT_HI - GENERAL PURPOSE I/O DATA [116:96] (GPIO[110:90])
+ ***************************************************************************/
+/* GIO :: DATA_EXT_HI :: reserved0 [31:21] */
+#define BCHP_GIO_DATA_EXT_HI_reserved0_MASK                        0xffe00000
+#define BCHP_GIO_DATA_EXT_HI_reserved0_SHIFT                       21
+
+/* GIO :: DATA_EXT_HI :: data [20:00] */
+#define BCHP_GIO_DATA_EXT_HI_data_MASK                             0x001fffff
+#define BCHP_GIO_DATA_EXT_HI_data_SHIFT                            0
+#define BCHP_GIO_DATA_EXT_HI_data_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *IODIR_EXT_HI - GENERAL PURPOSE I/O DIRECTION [116:96] (GPIO[110:90])
+ ***************************************************************************/
+/* GIO :: IODIR_EXT_HI :: reserved0 [31:21] */
+#define BCHP_GIO_IODIR_EXT_HI_reserved0_MASK                       0xffe00000
+#define BCHP_GIO_IODIR_EXT_HI_reserved0_SHIFT                      21
+
+/* GIO :: IODIR_EXT_HI :: iodir [20:00] */
+#define BCHP_GIO_IODIR_EXT_HI_iodir_MASK                           0x001fffff
+#define BCHP_GIO_IODIR_EXT_HI_iodir_SHIFT                          0
+#define BCHP_GIO_IODIR_EXT_HI_iodir_DEFAULT                        0x001fffff
+
+/***************************************************************************
+ *EC_EXT_HI - GENERAL PURPOSE I/O EDGE CONFIGURATION [116:96] (GPIO[110:90])
+ ***************************************************************************/
+/* GIO :: EC_EXT_HI :: reserved0 [31:21] */
+#define BCHP_GIO_EC_EXT_HI_reserved0_MASK                          0xffe00000
+#define BCHP_GIO_EC_EXT_HI_reserved0_SHIFT                         21
+
+/* GIO :: EC_EXT_HI :: edge_config [20:00] */
+#define BCHP_GIO_EC_EXT_HI_edge_config_MASK                        0x001fffff
+#define BCHP_GIO_EC_EXT_HI_edge_config_SHIFT                       0
+#define BCHP_GIO_EC_EXT_HI_edge_config_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *EI_EXT_HI - GENERAL PURPOSE I/O EDGE INSENSITIVE [116:96] (GPIO[110:90])
+ ***************************************************************************/
+/* GIO :: EI_EXT_HI :: reserved0 [31:21] */
+#define BCHP_GIO_EI_EXT_HI_reserved0_MASK                          0xffe00000
+#define BCHP_GIO_EI_EXT_HI_reserved0_SHIFT                         21
+
+/* GIO :: EI_EXT_HI :: edge_insensitive [20:00] */
+#define BCHP_GIO_EI_EXT_HI_edge_insensitive_MASK                   0x001fffff
+#define BCHP_GIO_EI_EXT_HI_edge_insensitive_SHIFT                  0
+#define BCHP_GIO_EI_EXT_HI_edge_insensitive_DEFAULT                0x00000000
+
+/***************************************************************************
+ *MASK_EXT_HI - GENERAL PURPOSE I/O INTERRUPT MASK [116:96] (GPIO[110:90])
+ ***************************************************************************/
+/* GIO :: MASK_EXT_HI :: reserved0 [31:21] */
+#define BCHP_GIO_MASK_EXT_HI_reserved0_MASK                        0xffe00000
+#define BCHP_GIO_MASK_EXT_HI_reserved0_SHIFT                       21
+
+/* GIO :: MASK_EXT_HI :: irq_mask [20:00] */
+#define BCHP_GIO_MASK_EXT_HI_irq_mask_MASK                         0x001fffff
+#define BCHP_GIO_MASK_EXT_HI_irq_mask_SHIFT                        0
+#define BCHP_GIO_MASK_EXT_HI_irq_mask_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *LEVEL_EXT_HI - GENERAL PURPOSE I/O INTERRUPT TYPE [116:96] (GPIO[110:90])
+ ***************************************************************************/
+/* GIO :: LEVEL_EXT_HI :: reserved0 [31:21] */
+#define BCHP_GIO_LEVEL_EXT_HI_reserved0_MASK                       0xffe00000
+#define BCHP_GIO_LEVEL_EXT_HI_reserved0_SHIFT                      21
+
+/* GIO :: LEVEL_EXT_HI :: level [20:00] */
+#define BCHP_GIO_LEVEL_EXT_HI_level_MASK                           0x001fffff
+#define BCHP_GIO_LEVEL_EXT_HI_level_SHIFT                          0
+#define BCHP_GIO_LEVEL_EXT_HI_level_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *STAT_EXT_HI - GENERAL PURPOSE I/O INTERRUPT STATUS [116:96] (GPIO[110:90])
+ ***************************************************************************/
+/* GIO :: STAT_EXT_HI :: reserved0 [31:21] */
+#define BCHP_GIO_STAT_EXT_HI_reserved0_MASK                        0xffe00000
+#define BCHP_GIO_STAT_EXT_HI_reserved0_SHIFT                       21
+
+/* GIO :: STAT_EXT_HI :: irq_status [20:00] */
+#define BCHP_GIO_STAT_EXT_HI_irq_status_MASK                       0x001fffff
+#define BCHP_GIO_STAT_EXT_HI_irq_status_SHIFT                      0
+#define BCHP_GIO_STAT_EXT_HI_irq_status_DEFAULT                    0x00000000
+
+#endif /* #ifndef BCHP_GIO_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_gio_aon.h b/include/linux/brcmstb/7425b0/bchp_gio_aon.h
new file mode 100644
index 0000000..4febf2a
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_gio_aon.h
@@ -0,0 +1,256 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:44 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_GIO_AON_H__
+#define BCHP_GIO_AON_H__
+
+/***************************************************************************
+ *GIO_AON - GPIO
+ ***************************************************************************/
+#define BCHP_GIO_AON_ODEN_LO                     0x004094c0 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE [17:0] */
+#define BCHP_GIO_AON_DATA_LO                     0x004094c4 /* GENERAL PURPOSE I/O DATA [17:0] */
+#define BCHP_GIO_AON_IODIR_LO                    0x004094c8 /* GENERAL PURPOSE I/O DIRECTION [17:0] */
+#define BCHP_GIO_AON_EC_LO                       0x004094cc /* GENERAL PURPOSE I/O EDGE CONFIGURATION [17:0] */
+#define BCHP_GIO_AON_EI_LO                       0x004094d0 /* GENERAL PURPOSE I/O EDGE INSENSITIVE [17:0] */
+#define BCHP_GIO_AON_MASK_LO                     0x004094d4 /* GENERAL PURPOSE I/O INTERRUPT MASK [17:0] */
+#define BCHP_GIO_AON_LEVEL_LO                    0x004094d8 /* GENERAL PURPOSE I/O INTERRUPT TYPE [17:0] */
+#define BCHP_GIO_AON_STAT_LO                     0x004094dc /* GENERAL PURPOSE I/O INTERRUPT STATUS [17:0] */
+#define BCHP_GIO_AON_ODEN_EXT                    0x004094e0 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE [65:64] (SGPIO[3:0]) */
+#define BCHP_GIO_AON_DATA_EXT                    0x004094e4 /* GENERAL PURPOSE I/O DATA [65:64] (SGPIO[3:0]) */
+#define BCHP_GIO_AON_IODIR_EXT                   0x004094e8 /* GENERAL PURPOSE I/O DIRECTION [65:64] (SGPIO[3:0]) */
+#define BCHP_GIO_AON_EC_EXT                      0x004094ec /* GENERAL PURPOSE I/O EDGE CONFIGURATION [65:64] (SGPIO[3:0]) */
+#define BCHP_GIO_AON_EI_EXT                      0x004094f0 /* GENERAL PURPOSE I/O EDGE INSENSITIVE [65:64] (SGPIO[3:0]) */
+#define BCHP_GIO_AON_MASK_EXT                    0x004094f4 /* GENERAL PURPOSE I/O INTERRUPT MASK [65:64] (SGPIO[3:0]) */
+#define BCHP_GIO_AON_LEVEL_EXT                   0x004094f8 /* GENERAL PURPOSE I/O INTERRUPT TYPE [65:64] (SGPIO[3:0]) */
+#define BCHP_GIO_AON_STAT_EXT                    0x004094fc /* GENERAL PURPOSE I/O INTERRUPT STATUS [65:64] (SGPIO[3:0]) */
+
+/***************************************************************************
+ *ODEN_LO - GENERAL PURPOSE I/O OPEN DRAIN ENABLE [17:0]
+ ***************************************************************************/
+/* GIO_AON :: ODEN_LO :: reserved0 [31:18] */
+#define BCHP_GIO_AON_ODEN_LO_reserved0_MASK                        0xfffc0000
+#define BCHP_GIO_AON_ODEN_LO_reserved0_SHIFT                       18
+
+/* GIO_AON :: ODEN_LO :: oden [17:00] */
+#define BCHP_GIO_AON_ODEN_LO_oden_MASK                             0x0003ffff
+#define BCHP_GIO_AON_ODEN_LO_oden_SHIFT                            0
+#define BCHP_GIO_AON_ODEN_LO_oden_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *DATA_LO - GENERAL PURPOSE I/O DATA [17:0]
+ ***************************************************************************/
+/* GIO_AON :: DATA_LO :: reserved0 [31:18] */
+#define BCHP_GIO_AON_DATA_LO_reserved0_MASK                        0xfffc0000
+#define BCHP_GIO_AON_DATA_LO_reserved0_SHIFT                       18
+
+/* GIO_AON :: DATA_LO :: data [17:00] */
+#define BCHP_GIO_AON_DATA_LO_data_MASK                             0x0003ffff
+#define BCHP_GIO_AON_DATA_LO_data_SHIFT                            0
+#define BCHP_GIO_AON_DATA_LO_data_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *IODIR_LO - GENERAL PURPOSE I/O DIRECTION [17:0]
+ ***************************************************************************/
+/* GIO_AON :: IODIR_LO :: reserved0 [31:18] */
+#define BCHP_GIO_AON_IODIR_LO_reserved0_MASK                       0xfffc0000
+#define BCHP_GIO_AON_IODIR_LO_reserved0_SHIFT                      18
+
+/* GIO_AON :: IODIR_LO :: iodir [17:00] */
+#define BCHP_GIO_AON_IODIR_LO_iodir_MASK                           0x0003ffff
+#define BCHP_GIO_AON_IODIR_LO_iodir_SHIFT                          0
+#define BCHP_GIO_AON_IODIR_LO_iodir_DEFAULT                        0x0003ffff
+
+/***************************************************************************
+ *EC_LO - GENERAL PURPOSE I/O EDGE CONFIGURATION [17:0]
+ ***************************************************************************/
+/* GIO_AON :: EC_LO :: reserved0 [31:18] */
+#define BCHP_GIO_AON_EC_LO_reserved0_MASK                          0xfffc0000
+#define BCHP_GIO_AON_EC_LO_reserved0_SHIFT                         18
+
+/* GIO_AON :: EC_LO :: edge_config [17:00] */
+#define BCHP_GIO_AON_EC_LO_edge_config_MASK                        0x0003ffff
+#define BCHP_GIO_AON_EC_LO_edge_config_SHIFT                       0
+#define BCHP_GIO_AON_EC_LO_edge_config_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *EI_LO - GENERAL PURPOSE I/O EDGE INSENSITIVE [17:0]
+ ***************************************************************************/
+/* GIO_AON :: EI_LO :: reserved0 [31:18] */
+#define BCHP_GIO_AON_EI_LO_reserved0_MASK                          0xfffc0000
+#define BCHP_GIO_AON_EI_LO_reserved0_SHIFT                         18
+
+/* GIO_AON :: EI_LO :: edge_insensitive [17:00] */
+#define BCHP_GIO_AON_EI_LO_edge_insensitive_MASK                   0x0003ffff
+#define BCHP_GIO_AON_EI_LO_edge_insensitive_SHIFT                  0
+#define BCHP_GIO_AON_EI_LO_edge_insensitive_DEFAULT                0x00000000
+
+/***************************************************************************
+ *MASK_LO - GENERAL PURPOSE I/O INTERRUPT MASK [17:0]
+ ***************************************************************************/
+/* GIO_AON :: MASK_LO :: reserved0 [31:18] */
+#define BCHP_GIO_AON_MASK_LO_reserved0_MASK                        0xfffc0000
+#define BCHP_GIO_AON_MASK_LO_reserved0_SHIFT                       18
+
+/* GIO_AON :: MASK_LO :: irq_mask [17:00] */
+#define BCHP_GIO_AON_MASK_LO_irq_mask_MASK                         0x0003ffff
+#define BCHP_GIO_AON_MASK_LO_irq_mask_SHIFT                        0
+#define BCHP_GIO_AON_MASK_LO_irq_mask_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *LEVEL_LO - GENERAL PURPOSE I/O INTERRUPT TYPE [17:0]
+ ***************************************************************************/
+/* GIO_AON :: LEVEL_LO :: reserved0 [31:18] */
+#define BCHP_GIO_AON_LEVEL_LO_reserved0_MASK                       0xfffc0000
+#define BCHP_GIO_AON_LEVEL_LO_reserved0_SHIFT                      18
+
+/* GIO_AON :: LEVEL_LO :: level [17:00] */
+#define BCHP_GIO_AON_LEVEL_LO_level_MASK                           0x0003ffff
+#define BCHP_GIO_AON_LEVEL_LO_level_SHIFT                          0
+#define BCHP_GIO_AON_LEVEL_LO_level_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *STAT_LO - GENERAL PURPOSE I/O INTERRUPT STATUS [17:0]
+ ***************************************************************************/
+/* GIO_AON :: STAT_LO :: reserved0 [31:18] */
+#define BCHP_GIO_AON_STAT_LO_reserved0_MASK                        0xfffc0000
+#define BCHP_GIO_AON_STAT_LO_reserved0_SHIFT                       18
+
+/* GIO_AON :: STAT_LO :: irq_status [17:00] */
+#define BCHP_GIO_AON_STAT_LO_irq_status_MASK                       0x0003ffff
+#define BCHP_GIO_AON_STAT_LO_irq_status_SHIFT                      0
+#define BCHP_GIO_AON_STAT_LO_irq_status_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *ODEN_EXT - GENERAL PURPOSE I/O OPEN DRAIN ENABLE [65:64] (SGPIO[3:0])
+ ***************************************************************************/
+/* GIO_AON :: ODEN_EXT :: reserved0 [31:04] */
+#define BCHP_GIO_AON_ODEN_EXT_reserved0_MASK                       0xfffffff0
+#define BCHP_GIO_AON_ODEN_EXT_reserved0_SHIFT                      4
+
+/* GIO_AON :: ODEN_EXT :: oden [03:00] */
+#define BCHP_GIO_AON_ODEN_EXT_oden_MASK                            0x0000000f
+#define BCHP_GIO_AON_ODEN_EXT_oden_SHIFT                           0
+#define BCHP_GIO_AON_ODEN_EXT_oden_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *DATA_EXT - GENERAL PURPOSE I/O DATA [65:64] (SGPIO[3:0])
+ ***************************************************************************/
+/* GIO_AON :: DATA_EXT :: reserved0 [31:04] */
+#define BCHP_GIO_AON_DATA_EXT_reserved0_MASK                       0xfffffff0
+#define BCHP_GIO_AON_DATA_EXT_reserved0_SHIFT                      4
+
+/* GIO_AON :: DATA_EXT :: data [03:00] */
+#define BCHP_GIO_AON_DATA_EXT_data_MASK                            0x0000000f
+#define BCHP_GIO_AON_DATA_EXT_data_SHIFT                           0
+#define BCHP_GIO_AON_DATA_EXT_data_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *IODIR_EXT - GENERAL PURPOSE I/O DIRECTION [65:64] (SGPIO[3:0])
+ ***************************************************************************/
+/* GIO_AON :: IODIR_EXT :: reserved0 [31:04] */
+#define BCHP_GIO_AON_IODIR_EXT_reserved0_MASK                      0xfffffff0
+#define BCHP_GIO_AON_IODIR_EXT_reserved0_SHIFT                     4
+
+/* GIO_AON :: IODIR_EXT :: iodir [03:00] */
+#define BCHP_GIO_AON_IODIR_EXT_iodir_MASK                          0x0000000f
+#define BCHP_GIO_AON_IODIR_EXT_iodir_SHIFT                         0
+#define BCHP_GIO_AON_IODIR_EXT_iodir_DEFAULT                       0x00000003
+
+/***************************************************************************
+ *EC_EXT - GENERAL PURPOSE I/O EDGE CONFIGURATION [65:64] (SGPIO[3:0])
+ ***************************************************************************/
+/* GIO_AON :: EC_EXT :: reserved0 [31:04] */
+#define BCHP_GIO_AON_EC_EXT_reserved0_MASK                         0xfffffff0
+#define BCHP_GIO_AON_EC_EXT_reserved0_SHIFT                        4
+
+/* GIO_AON :: EC_EXT :: edge_config [03:00] */
+#define BCHP_GIO_AON_EC_EXT_edge_config_MASK                       0x0000000f
+#define BCHP_GIO_AON_EC_EXT_edge_config_SHIFT                      0
+#define BCHP_GIO_AON_EC_EXT_edge_config_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *EI_EXT - GENERAL PURPOSE I/O EDGE INSENSITIVE [65:64] (SGPIO[3:0])
+ ***************************************************************************/
+/* GIO_AON :: EI_EXT :: reserved0 [31:04] */
+#define BCHP_GIO_AON_EI_EXT_reserved0_MASK                         0xfffffff0
+#define BCHP_GIO_AON_EI_EXT_reserved0_SHIFT                        4
+
+/* GIO_AON :: EI_EXT :: edge_insensitive [03:00] */
+#define BCHP_GIO_AON_EI_EXT_edge_insensitive_MASK                  0x0000000f
+#define BCHP_GIO_AON_EI_EXT_edge_insensitive_SHIFT                 0
+#define BCHP_GIO_AON_EI_EXT_edge_insensitive_DEFAULT               0x00000000
+
+/***************************************************************************
+ *MASK_EXT - GENERAL PURPOSE I/O INTERRUPT MASK [65:64] (SGPIO[3:0])
+ ***************************************************************************/
+/* GIO_AON :: MASK_EXT :: reserved0 [31:04] */
+#define BCHP_GIO_AON_MASK_EXT_reserved0_MASK                       0xfffffff0
+#define BCHP_GIO_AON_MASK_EXT_reserved0_SHIFT                      4
+
+/* GIO_AON :: MASK_EXT :: irq_mask [03:00] */
+#define BCHP_GIO_AON_MASK_EXT_irq_mask_MASK                        0x0000000f
+#define BCHP_GIO_AON_MASK_EXT_irq_mask_SHIFT                       0
+#define BCHP_GIO_AON_MASK_EXT_irq_mask_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *LEVEL_EXT - GENERAL PURPOSE I/O INTERRUPT TYPE [65:64] (SGPIO[3:0])
+ ***************************************************************************/
+/* GIO_AON :: LEVEL_EXT :: reserved0 [31:04] */
+#define BCHP_GIO_AON_LEVEL_EXT_reserved0_MASK                      0xfffffff0
+#define BCHP_GIO_AON_LEVEL_EXT_reserved0_SHIFT                     4
+
+/* GIO_AON :: LEVEL_EXT :: level [03:00] */
+#define BCHP_GIO_AON_LEVEL_EXT_level_MASK                          0x0000000f
+#define BCHP_GIO_AON_LEVEL_EXT_level_SHIFT                         0
+#define BCHP_GIO_AON_LEVEL_EXT_level_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *STAT_EXT - GENERAL PURPOSE I/O INTERRUPT STATUS [65:64] (SGPIO[3:0])
+ ***************************************************************************/
+/* GIO_AON :: STAT_EXT :: reserved0 [31:04] */
+#define BCHP_GIO_AON_STAT_EXT_reserved0_MASK                       0xfffffff0
+#define BCHP_GIO_AON_STAT_EXT_reserved0_SHIFT                      4
+
+/* GIO_AON :: STAT_EXT :: irq_status [03:00] */
+#define BCHP_GIO_AON_STAT_EXT_irq_status_MASK                      0x0000000f
+#define BCHP_GIO_AON_STAT_EXT_irq_status_SHIFT                     0
+#define BCHP_GIO_AON_STAT_EXT_irq_status_DEFAULT                   0x00000000
+
+#endif /* #ifndef BCHP_GIO_AON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_hif_cpu_intr1.h b/include/linux/brcmstb/7425b0/bchp_hif_cpu_intr1.h
new file mode 100644
index 0000000..314114e
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_hif_cpu_intr1.h
@@ -0,0 +1,1792 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:43 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_INTR1_H__
+#define BCHP_HIF_CPU_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_INTR1 - HIF CPU1 Thread Processor 0 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS        0x0041a400 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS        0x0041a404 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS        0x0041a408 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS   0x0041a40c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS   0x0041a410 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS   0x0041a414 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET      0x0041a418 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET      0x0041a41c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET      0x0041a420 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR    0x0041a424 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR    0x0041a428 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR    0x0041a42c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: NMI_PIN_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_NMI_PIN_CPU_INTR_MASK    0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_NMI_PIN_CPU_INTR_SHIFT   31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: MOCA_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MOCA_CPU_INTR_MASK       0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MOCA_CPU_INTR_SHIFT      30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MOCA_CPU_INTR_DEFAULT    0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: MEMC1_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MEMC1_CPU_INTR_MASK      0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MEMC1_CPU_INTR_SHIFT     29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MEMC1_CPU_INTR_DEFAULT   0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: MEMC0_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MEMC0_CPU_INTR_MASK      0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MEMC0_CPU_INTR_SHIFT     28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MEMC0_CPU_INTR_DEFAULT   0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: IPI1_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI1_CPU_INTR_MASK       0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI1_CPU_INTR_SHIFT      27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI1_CPU_INTR_DEFAULT    0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: IPI0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI0_CPU_INTR_MASK       0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI0_CPU_INTR_SHIFT      26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI0_CPU_INTR_DEFAULT    0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK    0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT   25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK        0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT       24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HDMI_RX_0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_RX_0_CPU_INTR_MASK  0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_RX_0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GFX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_MASK        0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_SHIFT       21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_1_B_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_MASK  0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_1_A_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_MASK  0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK  0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK  0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: DVP_HR_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_DVP_HR_CPU_INTR_MASK     0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_DVP_HR_CPU_INTR_SHIFT    10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_DVP_HR_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK     0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT    9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNM_1_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_1_CPU_INTR_MASK     0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_1_CPU_INTR_SHIFT    8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_1_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK     0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT    7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK     0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT    6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK     0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT    5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK     0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT    4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK     0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT    3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK        0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT       2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: AVD1_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AVD1_0_CPU_INTR_MASK     0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AVD1_0_CPU_INTR_SHIFT    1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AVD1_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK        0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT       0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK    0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT   28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK    0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT   27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK     0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT    26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MC_CPU_INTR_MASK     0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MC_CPU_INTR_SHIFT    25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MC_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK   0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT  23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK    0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT   21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_MASK    0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_SHIFT   19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UHF_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_MASK        0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_SHIFT       18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK     0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT    17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK    0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT   16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK        0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT       15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SVD0_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_MASK     0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_SHIFT    14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDIO1_0_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDIO1_0_CPU_INTR_MASK    0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDIO1_0_CPU_INTR_SHIFT   12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDIO1_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDIO0_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDIO0_0_CPU_INTR_MASK    0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDIO0_0_CPU_INTR_SHIFT   11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SATA_GRB_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_MASK   0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_SHIFT  10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SATA_AHCI_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_MASK  0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK   0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT  8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK      0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT     7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT   0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: PCIE_NMI_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_NMI_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_NMI_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_NMI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: PCIE_INTR_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTR_CPU_INTR_MASK  0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTR_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: PCIE_INTD_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTD_CPU_INTR_MASK  0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTD_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTD_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: PCIE_INTC_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTC_CPU_INTR_MASK  0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTC_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: PCIE_INTB_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTB_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTB_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTB_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: PCIE_INTA_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTA_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTA_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTA_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: PCIE_ERR_ATTN_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_ERR_ATTN_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_ERR_ATTN_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_ERR_ATTN_CPU_INTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: reserved0 [31:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved0_MASK           0xfff00000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved0_SHIFT          20
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK    0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT   18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK    0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT   17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK   0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT  16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK    0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT   14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK     0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT    13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: VICE0_0_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VICE0_0_CPU_INTR_MASK    0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VICE0_0_CPU_INTR_SHIFT   12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VICE0_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK        0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT       11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: V3D_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_V3D_CPU_INTR_MASK        0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_V3D_CPU_INTR_SHIFT       10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_V3D_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_BRIDGE_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_1_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: NMI_PIN_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: MOCA_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MOCA_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MOCA_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MOCA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: MEMC1_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MEMC1_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MEMC1_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MEMC1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: MEMC0_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MEMC0_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MEMC0_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MEMC0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: IPI1_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI1_CPU_INTR_MASK  0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI1_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: IPI0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI0_CPU_INTR_MASK  0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI0_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK   0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT  24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_RX_0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_RX_0_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_RX_0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GFX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_MASK   0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_SHIFT  21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_B_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_A_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: DVP_HR_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_DVP_HR_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_DVP_HR_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_DVP_HR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_1_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_1_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_1_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: AVD1_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AVD1_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AVD1_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AVD1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UHF_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_MASK   0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_SHIFT  18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK   0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT  15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SVD0_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDIO1_0_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDIO1_0_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDIO1_0_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDIO1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDIO0_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SATA_GRB_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SATA_AHCI_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_NMI_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_NMI_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_NMI_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_NMI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTR_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTR_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTR_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTD_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTD_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTD_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTD_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTC_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTC_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTC_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTB_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTB_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTB_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTA_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTA_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTA_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_ERR_ATTN_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_ERR_ATTN_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_ERR_ATTN_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_ERR_ATTN_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: reserved0 [31:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved0_MASK      0xfff00000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved0_SHIFT     20
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: VICE0_0_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VICE0_0_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VICE0_0_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VICE0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK   0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT  11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: V3D_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_V3D_CPU_INTR_MASK   0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_V3D_CPU_INTR_SHIFT  10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_V3D_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_BRIDGE_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_1_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: NMI_PIN_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_NMI_PIN_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: MOCA_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MOCA_CPU_INTR_MASK     0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MOCA_CPU_INTR_SHIFT    30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MOCA_CPU_INTR_DEFAULT  0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: MEMC1_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MEMC1_CPU_INTR_MASK    0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MEMC1_CPU_INTR_SHIFT   29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MEMC1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: MEMC0_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MEMC0_CPU_INTR_MASK    0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MEMC0_CPU_INTR_SHIFT   28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MEMC0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: IPI1_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI1_CPU_INTR_MASK     0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI1_CPU_INTR_SHIFT    27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI1_CPU_INTR_DEFAULT  0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: IPI0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI0_CPU_INTR_MASK     0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI0_CPU_INTR_SHIFT    26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI0_CPU_INTR_DEFAULT  0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK  0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK      0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT     24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK  0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HDMI_RX_0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_RX_0_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_RX_0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GFX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_MASK      0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_SHIFT     21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_1_B_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_1_A_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: DVP_HR_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_DVP_HR_CPU_INTR_MASK   0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_DVP_HR_CPU_INTR_SHIFT  10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_DVP_HR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK   0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT  9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNM_1_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_1_CPU_INTR_MASK   0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_1_CPU_INTR_SHIFT  8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK      0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT     2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: AVD1_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AVD1_0_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AVD1_0_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AVD1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK      0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT     0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK  0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MC_CPU_INTR_MASK   0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MC_CPU_INTR_SHIFT  25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK  0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_MASK  0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UHF_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_MASK      0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_SHIFT     18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK   0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT  17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK  0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK      0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT     15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SVD0_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_MASK   0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_SHIFT  14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDIO1_0_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDIO1_0_CPU_INTR_MASK  0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDIO1_0_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDIO1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDIO0_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDIO0_0_CPU_INTR_MASK  0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SATA_GRB_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SATA_AHCI_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK    0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT   7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: PCIE_NMI_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_NMI_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_NMI_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_NMI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTR_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTR_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTR_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTD_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTD_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTD_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTD_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTC_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTC_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTC_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTB_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTB_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTB_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTA_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTA_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTA_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: PCIE_ERR_ATTN_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_ERR_ATTN_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_ERR_ATTN_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_ERR_ATTN_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: reserved0 [31:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved0_MASK         0xfff00000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved0_SHIFT        20
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK  0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK  0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK  0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK   0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT  13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: VICE0_0_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VICE0_0_CPU_INTR_MASK  0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VICE0_0_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VICE0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK      0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT     11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: V3D_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_V3D_CPU_INTR_MASK      0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_V3D_CPU_INTR_SHIFT     10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_V3D_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_BRIDGE_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_1_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: NMI_PIN_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: MOCA_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MOCA_CPU_INTR_MASK   0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MOCA_CPU_INTR_SHIFT  30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MOCA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: MEMC1_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MEMC1_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MEMC1_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MEMC1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: MEMC0_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MEMC0_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MEMC0_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MEMC0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: IPI1_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI1_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI1_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: IPI0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI0_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI0_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK    0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT   24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_RX_0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_RX_0_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_RX_0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GFX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_MASK    0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_SHIFT   21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_B_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_A_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: DVP_HR_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_DVP_HR_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_DVP_HR_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_DVP_HR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_1_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_1_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_1_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK    0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT   2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: AVD1_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AVD1_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AVD1_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AVD1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UHF_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_MASK    0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_SHIFT   18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK    0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT   15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SVD0_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDIO1_0_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDIO1_0_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDIO1_0_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDIO1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDIO0_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_GRB_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_AHCI_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK  0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_NMI_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_NMI_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_NMI_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_NMI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTR_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTR_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTR_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTD_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTD_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTD_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTD_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTC_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTC_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTC_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTB_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTB_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTB_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTA_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTA_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTA_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_ERR_ATTN_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_ERR_ATTN_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_ERR_ATTN_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_ERR_ATTN_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: reserved0 [31:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved0_MASK       0xfff00000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved0_SHIFT      20
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: VICE0_0_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VICE0_0_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VICE0_0_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VICE0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK    0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT   11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: V3D_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_V3D_CPU_INTR_MASK    0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_V3D_CPU_INTR_SHIFT   10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_V3D_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_BRIDGE_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_1_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+#endif /* #ifndef BCHP_HIF_CPU_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_hif_cpu_tp1_intr1.h b/include/linux/brcmstb/7425b0/bchp_hif_cpu_tp1_intr1.h
new file mode 100644
index 0000000..12ae47f
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_hif_cpu_tp1_intr1.h
@@ -0,0 +1,1792 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:42 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_TP1_INTR1_H__
+#define BCHP_HIF_CPU_TP1_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_TP1_INTR1 - HIF CPU1 Thread Processor 1 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS    0x0041a600 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS    0x0041a604 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS    0x0041a608 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS 0x0041a60c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS 0x0041a610 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS 0x0041a614 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET  0x0041a618 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET  0x0041a61c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET  0x0041a620 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR 0x0041a624 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR 0x0041a628 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR 0x0041a62c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: NMI_PIN_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_NMI_PIN_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_NMI_PIN_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: MOCA_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MOCA_CPU_INTR_MASK   0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MOCA_CPU_INTR_SHIFT  30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MOCA_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: MEMC1_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC1_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC1_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: MEMC0_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC0_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC0_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: IPI1_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI1_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI1_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: IPI0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI0_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI0_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK    0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT   24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HDMI_RX_0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_RX_0_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_RX_0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GFX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_MASK    0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_SHIFT   21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_1_B_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_1_A_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: DVP_HR_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_DVP_HR_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_DVP_HR_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_DVP_HR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNM_1_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_1_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_1_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK    0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT   2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: AVD1_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AVD1_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AVD1_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AVD1_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_AUX_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UHF_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_MASK    0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_SHIFT   18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK    0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT   15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SVD0_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDIO1_0_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO1_0_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO1_0_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO1_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDIO0_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO0_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO0_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SATA_GRB_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SATA_AHCI_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK  0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCIE_NMI_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_NMI_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_NMI_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_NMI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCIE_INTR_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTR_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTR_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCIE_INTD_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTD_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTD_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTD_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCIE_INTC_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTC_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTC_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCIE_INTB_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTB_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTB_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTB_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCIE_INTA_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTA_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTA_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTA_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCIE_ERR_ATTN_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_ERR_ATTN_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_ERR_ATTN_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_ERR_ATTN_CPU_INTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: reserved0 [31:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_reserved0_MASK       0xfff00000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_reserved0_SHIFT      20
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: VICE0_0_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VICE0_0_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VICE0_0_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VICE0_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK    0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT   11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: V3D_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_V3D_CPU_INTR_MASK    0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_V3D_CPU_INTR_SHIFT   10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_V3D_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_BRIDGE_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_1_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: NMI_PIN_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: MOCA_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MOCA_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MOCA_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MOCA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: MEMC1_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC1_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC1_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: MEMC0_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC0_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC0_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: IPI1_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI1_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI1_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: IPI0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI0_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI0_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_RX_0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_RX_0_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_RX_0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GFX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_B_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_A_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: DVP_HR_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_DVP_HR_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_DVP_HR_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_DVP_HR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_1_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_1_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_1_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: AVD1_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AVD1_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AVD1_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AVD1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UHF_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SVD0_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDIO1_0_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO1_0_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO1_0_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDIO0_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SATA_GRB_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SATA_AHCI_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_NMI_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_NMI_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_NMI_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_NMI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTR_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTR_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTR_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTD_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTD_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTD_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTD_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTC_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTC_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTC_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTB_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTB_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTB_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTA_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTA_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTA_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_ERR_ATTN_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_ERR_ATTN_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_ERR_ATTN_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_ERR_ATTN_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: reserved0 [31:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_reserved0_MASK  0xfff00000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_reserved0_SHIFT 20
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: VICE0_0_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VICE0_0_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VICE0_0_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VICE0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: V3D_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_V3D_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_V3D_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_V3D_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_BRIDGE_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_1_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: NMI_PIN_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_NMI_PIN_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: MOCA_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MOCA_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MOCA_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MOCA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: MEMC1_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC1_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC1_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: MEMC0_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC0_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC0_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: IPI1_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI1_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI1_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: IPI0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI0_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI0_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK  0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HDMI_RX_0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_RX_0_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_RX_0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GFX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_MASK  0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_1_B_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_1_A_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: DVP_HR_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_DVP_HR_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_DVP_HR_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_DVP_HR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNM_1_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_1_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_1_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: AVD1_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AVD1_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AVD1_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AVD1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UHF_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_MASK  0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK  0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SVD0_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDIO1_0_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO1_0_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO1_0_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDIO0_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO0_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SATA_GRB_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SATA_AHCI_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCIE_NMI_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_NMI_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_NMI_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_NMI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTR_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTR_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTR_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTD_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTD_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTD_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTD_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTC_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTC_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTC_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTB_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTB_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTB_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTA_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTA_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTA_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCIE_ERR_ATTN_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_ERR_ATTN_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_ERR_ATTN_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_ERR_ATTN_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: reserved0 [31:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_reserved0_MASK     0xfff00000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_reserved0_SHIFT    20
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: VICE0_0_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VICE0_0_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VICE0_0_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VICE0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK  0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: V3D_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_V3D_CPU_INTR_MASK  0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_V3D_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_V3D_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_BRIDGE_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_1_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: NMI_PIN_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: MOCA_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MOCA_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MOCA_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MOCA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: MEMC1_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC1_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC1_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: MEMC0_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC0_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC0_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: IPI1_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI1_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI1_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: IPI0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI0_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI0_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_RX_0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_RX_0_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_RX_0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GFX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_B_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_A_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: DVP_HR_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_DVP_HR_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_DVP_HR_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_DVP_HR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_1_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_1_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_1_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: AVD1_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AVD1_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AVD1_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AVD1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UHF_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SVD0_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDIO1_0_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO1_0_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO1_0_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDIO0_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_GRB_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_AHCI_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_NMI_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_NMI_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_NMI_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_NMI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTR_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTR_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTR_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTD_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTD_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTD_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTD_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTC_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTC_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTC_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTB_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTB_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTB_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTA_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTA_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTA_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_ERR_ATTN_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_ERR_ATTN_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_ERR_ATTN_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_ERR_ATTN_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: reserved0 [31:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_reserved0_MASK   0xfff00000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_reserved0_SHIFT  20
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: VICE0_0_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VICE0_0_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VICE0_0_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VICE0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: V3D_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_V3D_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_V3D_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_V3D_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_BRIDGE_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_1_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+#endif /* #ifndef BCHP_HIF_CPU_TP1_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_hif_intr2.h b/include/linux/brcmstb/7425b0/bchp_hif_intr2.h
new file mode 100644
index 0000000..27b697d
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_hif_intr2.h
@@ -0,0 +1,1392 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:43 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_INTR2_H__
+#define BCHP_HIF_INTR2_H__
+
+/***************************************************************************
+ *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_INTR2_CPU_STATUS                0x0041a000 /* CPU interrupt Status Register */
+#define BCHP_HIF_INTR2_CPU_SET                   0x0041a004 /* CPU interrupt Set Register */
+#define BCHP_HIF_INTR2_CPU_CLEAR                 0x0041a008 /* CPU interrupt Clear Register */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS           0x0041a00c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_CPU_MASK_SET              0x0041a010 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR            0x0041a014 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_INTR2_PCI_STATUS                0x0041a018 /* PCI interrupt Status Register */
+#define BCHP_HIF_INTR2_PCI_SET                   0x0041a01c /* PCI interrupt Set Register */
+#define BCHP_HIF_INTR2_PCI_CLEAR                 0x0041a020 /* PCI interrupt Clear Register */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS           0x0041a024 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_PCI_MASK_SET              0x0041a028 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR            0x0041a02c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKDOWN_INTR_MASK          0x80000000
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKDOWN_INTR_SHIFT         31
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKDOWN_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKUP_INTR_MASK            0x40000000
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKUP_INTR_SHIFT           30
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKUP_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EDU_DONE_INTR_MASK               0x20000000
+#define BCHP_HIF_INTR2_CPU_STATUS_EDU_DONE_INTR_SHIFT              29
+#define BCHP_HIF_INTR2_CPU_STATUS_EDU_DONE_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EDU_ERR_INTR_MASK                0x10000000
+#define BCHP_HIF_INTR2_CPU_STATUS_EDU_ERR_INTR_SHIFT               28
+#define BCHP_HIF_INTR2_CPU_STATUS_EDU_ERR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_MASK          0x00080000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_SHIFT         19
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_MASK          0x00008000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_SHIFT         15
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK                   0x00004000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT                  14
+
+/* HIF_INTR2 :: CPU_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RG_BRIDGE_INTR_MASK         0x00002000
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT        13
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RG_BRIDGE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR1_BRIDGE_INTR_MASK        0x00001000
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR1_BRIDGE_INTR_SHIFT       12
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR1_BRIDGE_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved1 [11:01] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK                   0x00000ffe
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_MASK        0x00000001
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT       0
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_SET :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKDOWN_INTR_MASK             0x80000000
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKDOWN_INTR_SHIFT            31
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKDOWN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKUP_INTR_MASK               0x40000000
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKUP_INTR_SHIFT              30
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKUP_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_CPU_SET_EDU_DONE_INTR_MASK                  0x20000000
+#define BCHP_HIF_INTR2_CPU_SET_EDU_DONE_INTR_SHIFT                 29
+#define BCHP_HIF_INTR2_CPU_SET_EDU_DONE_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_CPU_SET_EDU_ERR_INTR_MASK                   0x10000000
+#define BCHP_HIF_INTR2_CPU_SET_EDU_ERR_INTR_SHIFT                  28
+#define BCHP_HIF_INTR2_CPU_SET_EDU_ERR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_MASK             0x00080000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_SHIFT            19
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_MASK             0x00008000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_SHIFT            15
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK                      0x00004000
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT                     14
+
+/* HIF_INTR2 :: CPU_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_RG_BRIDGE_INTR_MASK            0x00002000
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_RG_BRIDGE_INTR_SHIFT           13
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_RG_BRIDGE_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR1_BRIDGE_INTR_MASK           0x00001000
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR1_BRIDGE_INTR_SHIFT          12
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR1_BRIDGE_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved1 [11:01] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK                      0x00000ffe
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: CPU_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_MASK           0x00000001
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_SHIFT          0
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT        0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKDOWN_INTR_MASK           0x80000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKDOWN_INTR_SHIFT          31
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKDOWN_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKUP_INTR_MASK             0x40000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKUP_INTR_SHIFT            30
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKUP_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EDU_DONE_INTR_MASK                0x20000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EDU_DONE_INTR_SHIFT               29
+#define BCHP_HIF_INTR2_CPU_CLEAR_EDU_DONE_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EDU_ERR_INTR_MASK                 0x10000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EDU_ERR_INTR_SHIFT                28
+#define BCHP_HIF_INTR2_CPU_CLEAR_EDU_ERR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_MASK           0x00008000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_SHIFT          15
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK                    0x00004000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT                   14
+
+/* HIF_INTR2 :: CPU_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RG_BRIDGE_INTR_MASK          0x00002000
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT         13
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RG_BRIDGE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR1_BRIDGE_INTR_MASK         0x00001000
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR1_BRIDGE_INTR_SHIFT        12
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR1_BRIDGE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [11:01] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK                    0x00000ffe
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKDOWN_INTR_MASK     0x80000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKDOWN_INTR_SHIFT    31
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKDOWN_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKUP_INTR_MASK       0x40000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKUP_INTR_SHIFT      30
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKUP_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EDU_DONE_INTR_MASK          0x20000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EDU_DONE_INTR_SHIFT         29
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EDU_DONE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EDU_ERR_INTR_MASK           0x10000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EDU_ERR_INTR_SHIFT          28
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EDU_ERR_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_MASK     0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_SHIFT    19
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_MASK     0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_SHIFT    15
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK              0x00004000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT             14
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RG_BRIDGE_INTR_MASK    0x00002000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT   13
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RG_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR1_BRIDGE_INTR_MASK   0x00001000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR1_BRIDGE_INTR_SHIFT  12
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR1_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [11:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK              0x00000ffe
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK   0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT  0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKDOWN_INTR_MASK        0x80000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKDOWN_INTR_SHIFT       31
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKDOWN_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKUP_INTR_MASK          0x40000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKUP_INTR_SHIFT         30
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKUP_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EDU_DONE_INTR_MASK             0x20000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EDU_DONE_INTR_SHIFT            29
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EDU_DONE_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EDU_ERR_INTR_MASK              0x10000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EDU_ERR_INTR_SHIFT             28
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EDU_ERR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_MASK        0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_SHIFT       19
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_MASK        0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_SHIFT       15
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK                 0x00004000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT                14
+
+/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RG_BRIDGE_INTR_MASK       0x00002000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RG_BRIDGE_INTR_SHIFT      13
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RG_BRIDGE_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR1_BRIDGE_INTR_MASK      0x00001000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR1_BRIDGE_INTR_SHIFT     12
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR1_BRIDGE_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [11:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK                 0x00000ffe
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK      0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT     0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKDOWN_INTR_MASK      0x80000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKDOWN_INTR_SHIFT     31
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKDOWN_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKUP_INTR_MASK        0x40000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKUP_INTR_SHIFT       30
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKUP_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EDU_DONE_INTR_MASK           0x20000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EDU_DONE_INTR_SHIFT          29
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EDU_DONE_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EDU_ERR_INTR_MASK            0x10000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EDU_ERR_INTR_SHIFT           28
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EDU_ERR_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_MASK      0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_SHIFT     15
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK               0x00004000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT              14
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_MASK     0x00002000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT    13
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR1_BRIDGE_INTR_MASK    0x00001000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR1_BRIDGE_INTR_SHIFT   12
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR1_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [11:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK               0x00000ffe
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKDOWN_INTR_MASK          0x80000000
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKDOWN_INTR_SHIFT         31
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKDOWN_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKUP_INTR_MASK            0x40000000
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKUP_INTR_SHIFT           30
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKUP_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EDU_DONE_INTR_MASK               0x20000000
+#define BCHP_HIF_INTR2_PCI_STATUS_EDU_DONE_INTR_SHIFT              29
+#define BCHP_HIF_INTR2_PCI_STATUS_EDU_DONE_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EDU_ERR_INTR_MASK                0x10000000
+#define BCHP_HIF_INTR2_PCI_STATUS_EDU_ERR_INTR_SHIFT               28
+#define BCHP_HIF_INTR2_PCI_STATUS_EDU_ERR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_MASK          0x00080000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_SHIFT         19
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_MASK          0x00008000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_SHIFT         15
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK                   0x00004000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT                  14
+
+/* HIF_INTR2 :: PCI_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RG_BRIDGE_INTR_MASK         0x00002000
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT        13
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RG_BRIDGE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR1_BRIDGE_INTR_MASK        0x00001000
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR1_BRIDGE_INTR_SHIFT       12
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR1_BRIDGE_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved1 [11:01] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK                   0x00000ffe
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_MASK        0x00000001
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT       0
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_SET :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKDOWN_INTR_MASK             0x80000000
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKDOWN_INTR_SHIFT            31
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKDOWN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKUP_INTR_MASK               0x40000000
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKUP_INTR_SHIFT              30
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKUP_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_PCI_SET_EDU_DONE_INTR_MASK                  0x20000000
+#define BCHP_HIF_INTR2_PCI_SET_EDU_DONE_INTR_SHIFT                 29
+#define BCHP_HIF_INTR2_PCI_SET_EDU_DONE_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_PCI_SET_EDU_ERR_INTR_MASK                   0x10000000
+#define BCHP_HIF_INTR2_PCI_SET_EDU_ERR_INTR_SHIFT                  28
+#define BCHP_HIF_INTR2_PCI_SET_EDU_ERR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_MASK             0x00080000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_SHIFT            19
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_MASK             0x00008000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_SHIFT            15
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK                      0x00004000
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT                     14
+
+/* HIF_INTR2 :: PCI_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_RG_BRIDGE_INTR_MASK            0x00002000
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_RG_BRIDGE_INTR_SHIFT           13
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_RG_BRIDGE_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR1_BRIDGE_INTR_MASK           0x00001000
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR1_BRIDGE_INTR_SHIFT          12
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR1_BRIDGE_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved1 [11:01] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK                      0x00000ffe
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: PCI_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_MASK           0x00000001
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_SHIFT          0
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKDOWN_INTR_MASK           0x80000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKDOWN_INTR_SHIFT          31
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKDOWN_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKUP_INTR_MASK             0x40000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKUP_INTR_SHIFT            30
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKUP_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EDU_DONE_INTR_MASK                0x20000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EDU_DONE_INTR_SHIFT               29
+#define BCHP_HIF_INTR2_PCI_CLEAR_EDU_DONE_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EDU_ERR_INTR_MASK                 0x10000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EDU_ERR_INTR_SHIFT                28
+#define BCHP_HIF_INTR2_PCI_CLEAR_EDU_ERR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_MASK           0x00008000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_SHIFT          15
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK                    0x00004000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT                   14
+
+/* HIF_INTR2 :: PCI_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RG_BRIDGE_INTR_MASK          0x00002000
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT         13
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RG_BRIDGE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR1_BRIDGE_INTR_MASK         0x00001000
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR1_BRIDGE_INTR_SHIFT        12
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR1_BRIDGE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [11:01] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK                    0x00000ffe
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKDOWN_INTR_MASK     0x80000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKDOWN_INTR_SHIFT    31
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKDOWN_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKUP_INTR_MASK       0x40000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKUP_INTR_SHIFT      30
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKUP_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EDU_DONE_INTR_MASK          0x20000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EDU_DONE_INTR_SHIFT         29
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EDU_DONE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EDU_ERR_INTR_MASK           0x10000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EDU_ERR_INTR_SHIFT          28
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EDU_ERR_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_MASK     0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_SHIFT    19
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_MASK     0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_SHIFT    15
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK              0x00004000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT             14
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RG_BRIDGE_INTR_MASK    0x00002000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT   13
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RG_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR1_BRIDGE_INTR_MASK   0x00001000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR1_BRIDGE_INTR_SHIFT  12
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR1_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [11:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK              0x00000ffe
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK   0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT  0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKDOWN_INTR_MASK        0x80000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKDOWN_INTR_SHIFT       31
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKDOWN_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKUP_INTR_MASK          0x40000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKUP_INTR_SHIFT         30
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKUP_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EDU_DONE_INTR_MASK             0x20000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EDU_DONE_INTR_SHIFT            29
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EDU_DONE_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EDU_ERR_INTR_MASK              0x10000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EDU_ERR_INTR_SHIFT             28
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EDU_ERR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_MASK        0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_SHIFT       19
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_MASK        0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_SHIFT       15
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK                 0x00004000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT                14
+
+/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RG_BRIDGE_INTR_MASK       0x00002000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RG_BRIDGE_INTR_SHIFT      13
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RG_BRIDGE_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR1_BRIDGE_INTR_MASK      0x00001000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR1_BRIDGE_INTR_SHIFT     12
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR1_BRIDGE_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [11:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK                 0x00000ffe
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK      0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT     0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKDOWN_INTR_MASK      0x80000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKDOWN_INTR_SHIFT     31
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKDOWN_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKUP_INTR_MASK        0x40000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKUP_INTR_SHIFT       30
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKUP_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EDU_DONE_INTR_MASK           0x20000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EDU_DONE_INTR_SHIFT          29
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EDU_DONE_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EDU_ERR_INTR_MASK            0x10000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EDU_ERR_INTR_SHIFT           28
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EDU_ERR_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_MASK      0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_SHIFT     15
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK               0x00004000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT              14
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_MASK     0x00002000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT    13
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR1_BRIDGE_INTR_MASK    0x00001000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR1_BRIDGE_INTR_SHIFT   12
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR1_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [11:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK               0x00000ffe
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+#endif /* #ifndef BCHP_HIF_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_hif_mspi.h b/include/linux/brcmstb/7425b0/bchp_hif_mspi.h
new file mode 100644
index 0000000..bba0857
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_hif_mspi.h
@@ -0,0 +1,1211 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:43 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_MSPI_H__
+#define BCHP_HIF_MSPI_H__
+
+/***************************************************************************
+ *HIF_MSPI - Public MSPI Registers
+ ***************************************************************************/
+#define BCHP_HIF_MSPI_SPCR0_LSB                  0x0041c200 /* SPCR0_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR0_MSB                  0x0041c204 /* SPCR0_MSB Register */
+#define BCHP_HIF_MSPI_SPCR1_LSB                  0x0041c208 /* SPCR1_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR1_MSB                  0x0041c20c /* SPCR1_MSB REGISTER */
+#define BCHP_HIF_MSPI_NEWQP                      0x0041c210 /* NEWQP REGISTER */
+#define BCHP_HIF_MSPI_ENDQP                      0x0041c214 /* ENDQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR2                      0x0041c218 /* SPCR2 REGISTER */
+#define BCHP_HIF_MSPI_MSPI_STATUS                0x0041c220 /* MSPI STATUS REGISTER */
+#define BCHP_HIF_MSPI_CPTQP                      0x0041c224 /* CPTQP REGISTER */
+#define BCHP_HIF_MSPI_TXRAM00                    0x0041c240 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM01                    0x0041c244 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM02                    0x0041c248 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM03                    0x0041c24c /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM04                    0x0041c250 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM05                    0x0041c254 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM06                    0x0041c258 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM07                    0x0041c25c /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM08                    0x0041c260 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM09                    0x0041c264 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM10                    0x0041c268 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM11                    0x0041c26c /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM12                    0x0041c270 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM13                    0x0041c274 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM14                    0x0041c278 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM15                    0x0041c27c /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM16                    0x0041c280 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM17                    0x0041c284 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM18                    0x0041c288 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM19                    0x0041c28c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM20                    0x0041c290 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM21                    0x0041c294 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM22                    0x0041c298 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM23                    0x0041c29c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM24                    0x0041c2a0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM25                    0x0041c2a4 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM26                    0x0041c2a8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM27                    0x0041c2ac /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM28                    0x0041c2b0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM29                    0x0041c2b4 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM30                    0x0041c2b8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_TXRAM31                    0x0041c2bc /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM00                    0x0041c2c0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM01                    0x0041c2c4 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM02                    0x0041c2c8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM03                    0x0041c2cc /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM04                    0x0041c2d0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM05                    0x0041c2d4 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM06                    0x0041c2d8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM07                    0x0041c2dc /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM08                    0x0041c2e0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM09                    0x0041c2e4 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM10                    0x0041c2e8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM11                    0x0041c2ec /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM12                    0x0041c2f0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM13                    0x0041c2f4 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM14                    0x0041c2f8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM15                    0x0041c2fc /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM16                    0x0041c300 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM17                    0x0041c304 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM18                    0x0041c308 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM19                    0x0041c30c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM20                    0x0041c310 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM21                    0x0041c314 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM22                    0x0041c318 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM23                    0x0041c31c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM24                    0x0041c320 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM25                    0x0041c324 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM26                    0x0041c328 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM27                    0x0041c32c /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM28                    0x0041c330 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM29                    0x0041c334 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM30                    0x0041c338 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM31                    0x0041c33c /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_CDRAM00                    0x0041c340 /* 8-bit command (queue pointer = 0) */
+#define BCHP_HIF_MSPI_CDRAM01                    0x0041c344 /* 8-bit command (queue pointer = 1) */
+#define BCHP_HIF_MSPI_CDRAM02                    0x0041c348 /* 8-bit command (queue pointer = 2) */
+#define BCHP_HIF_MSPI_CDRAM03                    0x0041c34c /* 8-bit command (queue pointer = 3) */
+#define BCHP_HIF_MSPI_CDRAM04                    0x0041c350 /* 8-bit command (queue pointer = 4) */
+#define BCHP_HIF_MSPI_CDRAM05                    0x0041c354 /* 8-bit command (queue pointer = 5) */
+#define BCHP_HIF_MSPI_CDRAM06                    0x0041c358 /* 8-bit command (queue pointer = 6) */
+#define BCHP_HIF_MSPI_CDRAM07                    0x0041c35c /* 8-bit command (queue pointer = 7) */
+#define BCHP_HIF_MSPI_CDRAM08                    0x0041c360 /* 8-bit command (queue pointer = 8) */
+#define BCHP_HIF_MSPI_CDRAM09                    0x0041c364 /* 8-bit command (queue pointer = 9) */
+#define BCHP_HIF_MSPI_CDRAM10                    0x0041c368 /* 8-bit command (queue pointer = a) */
+#define BCHP_HIF_MSPI_CDRAM11                    0x0041c36c /* 8-bit command (queue pointer = b) */
+#define BCHP_HIF_MSPI_CDRAM12                    0x0041c370 /* 8-bit command (queue pointer = c) */
+#define BCHP_HIF_MSPI_CDRAM13                    0x0041c374 /* 8-bit command (queue pointer = d) */
+#define BCHP_HIF_MSPI_CDRAM14                    0x0041c378 /* 8-bit command (queue pointer = e) */
+#define BCHP_HIF_MSPI_CDRAM15                    0x0041c37c /* 8-bit command (queue pointer = f) */
+#define BCHP_HIF_MSPI_WRITE_LOCK                 0x0041c380 /* Control bit to lock group of write commands */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN          0x0041c384 /* Debug bit to mask the generation of flush signals from Mspi */
+
+/***************************************************************************
+ *SPCR0_LSB - SPCR0_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK                          0x000000ff
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR0_MSB - SPCR0_MSB Register
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_MSB :: MSTR [07:07] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_MASK                          0x00000080
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_SHIFT                         7
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_DEFAULT                       0x00000001
+
+/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [06:06] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK               0x00000040
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT              6
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT            0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: BitS [05:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_MASK                          0x0000003c
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_SHIFT                         2
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_DEFAULT                       0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK                          0x00000002
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT                         1
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT                       0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK                          0x00000001
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR1_LSB - SPCR1_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT                          0
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *SPCR1_MSB - SPCR1_MSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK                        0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT                       0
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *NEWQP - NEWQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: NEWQP :: newqp [03:00] */
+#define BCHP_HIF_MSPI_NEWQP_newqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT                            0
+#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *ENDQP - ENDQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: ENDQP :: endqp [03:00] */
+#define BCHP_HIF_MSPI_ENDQP_endqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT                            0
+#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *SPCR2 - SPCR2 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK                         0xffffff00
+#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT                        8
+
+/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK                    0x00000080
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT                   7
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT                 0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spe [06:06] */
+#define BCHP_HIF_MSPI_SPCR2_spe_MASK                               0x00000040
+#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT                              6
+#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
+#define BCHP_HIF_MSPI_SPCR2_spifie_MASK                            0x00000020
+#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT                           5
+#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT                         0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wren [04:04] */
+#define BCHP_HIF_MSPI_SPCR2_wren_MASK                              0x00000010
+#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT                             4
+#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
+#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK                              0x00000008
+#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT                             3
+#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
+#define BCHP_HIF_MSPI_SPCR2_loopq_MASK                             0x00000004
+#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT                            2
+#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT                          0x00000000
+
+/* HIF_MSPI :: SPCR2 :: hie [01:01] */
+#define BCHP_HIF_MSPI_SPCR2_hie_MASK                               0x00000002
+#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT                              1
+#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: halt [00:00] */
+#define BCHP_HIF_MSPI_SPCR2_halt_MASK                              0x00000001
+#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT                             0
+#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *MSPI_STATUS - MSPI STATUS REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK                   0xfffffffc
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT                  2
+
+/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK                       0x00000002
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT                      1
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT                    0x00000000
+
+/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK                        0x00000001
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT                       0
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *CPTQP - CPTQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
+#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT                            0
+#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *TXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM00_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM01_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM02_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM03_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM04_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM05_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM06_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM07_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM08_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM09_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM10_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM11_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM12_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM13_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM14_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM15_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM16_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM17_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM18_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM19_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM20_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM21_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM22_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM23_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM24_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM25_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM26_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM27_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM28_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM29_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM30_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM31_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM00 - 8-bit command (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM00 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM01 - 8-bit command (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM01 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM02 - 8-bit command (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM02 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM03 - 8-bit command (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM03 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM04 - 8-bit command (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM04 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM05 - 8-bit command (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM05 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM06 - 8-bit command (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM06 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM07 - 8-bit command (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM07 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM08 - 8-bit command (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM08 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM09 - 8-bit command (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM09 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM10 - 8-bit command (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM10 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM11 - 8-bit command (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM11 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM12 - 8-bit command (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM12 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM13 - 8-bit command (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM13 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM14 - 8-bit command (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM14 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM15 - 8-bit command (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM15 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT                          0
+
+/***************************************************************************
+ *WRITE_LOCK - Control bit to lock group of write commands
+ ***************************************************************************/
+/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK                    0xfffffffe
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT                   1
+
+/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK                    0x00000001
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT                   0
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
+ ***************************************************************************/
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK             0xfffffffe
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT            1
+
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK       0x00000001
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT      0
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT    0x00000000
+
+#endif /* #ifndef BCHP_HIF_MSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_hif_rgr1.h b/include/linux/brcmstb/7425b0/bchp_hif_rgr1.h
new file mode 100644
index 0000000..71b7448
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_hif_rgr1.h
@@ -0,0 +1,134 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:42 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_RGR1_H__
+#define BCHP_HIF_RGR1_H__
+
+/***************************************************************************
+ *HIF_RGR1 - HIF RBUS-GISB-RBUS Bridge Registers
+ ***************************************************************************/
+#define BCHP_HIF_RGR1_REVISION                   0x00418000 /* RGR Bridge Revision */
+#define BCHP_HIF_RGR1_CTRL                       0x00418004 /* RGR Bridge Control Register */
+#define BCHP_HIF_RGR1_RBUS_TIMER                 0x00418008 /* RGR Bridge RBUS Timer Register */
+#define BCHP_HIF_RGR1_SW_INIT_0                  0x0041800c /* RGR Bridge Software Reset 0 Register */
+#define BCHP_HIF_RGR1_SW_INIT_1                  0x00418010 /* RGR Bridge Software Reset 1 Register */
+
+/***************************************************************************
+ *REVISION - RGR Bridge Revision
+ ***************************************************************************/
+/* HIF_RGR1 :: REVISION :: reserved0 [31:16] */
+#define BCHP_HIF_RGR1_REVISION_reserved0_MASK                      0xffff0000
+#define BCHP_HIF_RGR1_REVISION_reserved0_SHIFT                     16
+
+/* HIF_RGR1 :: REVISION :: MAJOR [15:08] */
+#define BCHP_HIF_RGR1_REVISION_MAJOR_MASK                          0x0000ff00
+#define BCHP_HIF_RGR1_REVISION_MAJOR_SHIFT                         8
+#define BCHP_HIF_RGR1_REVISION_MAJOR_DEFAULT                       0x00000002
+
+/* HIF_RGR1 :: REVISION :: MINOR [07:00] */
+#define BCHP_HIF_RGR1_REVISION_MINOR_MASK                          0x000000ff
+#define BCHP_HIF_RGR1_REVISION_MINOR_SHIFT                         0
+#define BCHP_HIF_RGR1_REVISION_MINOR_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *CTRL - RGR Bridge Control Register
+ ***************************************************************************/
+/* HIF_RGR1 :: CTRL :: reserved0 [31:02] */
+#define BCHP_HIF_RGR1_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_HIF_RGR1_CTRL_reserved0_SHIFT                         2
+
+/* HIF_RGR1 :: CTRL :: rbus_error_intr [01:01] */
+#define BCHP_HIF_RGR1_CTRL_rbus_error_intr_MASK                    0x00000002
+#define BCHP_HIF_RGR1_CTRL_rbus_error_intr_SHIFT                   1
+#define BCHP_HIF_RGR1_CTRL_rbus_error_intr_DEFAULT                 0x00000000
+#define BCHP_HIF_RGR1_CTRL_rbus_error_intr_INTR_DISABLE            0
+#define BCHP_HIF_RGR1_CTRL_rbus_error_intr_INTR_ENABLE             1
+
+/* HIF_RGR1 :: CTRL :: gisb_error_intr [00:00] */
+#define BCHP_HIF_RGR1_CTRL_gisb_error_intr_MASK                    0x00000001
+#define BCHP_HIF_RGR1_CTRL_gisb_error_intr_SHIFT                   0
+#define BCHP_HIF_RGR1_CTRL_gisb_error_intr_DEFAULT                 0x00000000
+#define BCHP_HIF_RGR1_CTRL_gisb_error_intr_INTR_DISABLE            0
+#define BCHP_HIF_RGR1_CTRL_gisb_error_intr_INTR_ENABLE             1
+
+/***************************************************************************
+ *RBUS_TIMER - RGR Bridge RBUS Timer Register
+ ***************************************************************************/
+/* HIF_RGR1 :: RBUS_TIMER :: timer_value [31:00] */
+#define BCHP_HIF_RGR1_RBUS_TIMER_timer_value_MASK                  0xffffffff
+#define BCHP_HIF_RGR1_RBUS_TIMER_timer_value_SHIFT                 0
+#define BCHP_HIF_RGR1_RBUS_TIMER_timer_value_DEFAULT               0x0e297d00
+
+/***************************************************************************
+ *SW_INIT_0 - RGR Bridge Software Reset 0 Register
+ ***************************************************************************/
+/* HIF_RGR1 :: SW_INIT_0 :: reserved0 [31:01] */
+#define BCHP_HIF_RGR1_SW_INIT_0_reserved0_MASK                     0xfffffffe
+#define BCHP_HIF_RGR1_SW_INIT_0_reserved0_SHIFT                    1
+
+/* HIF_RGR1 :: SW_INIT_0 :: SPARE_SW_INIT [00:00] */
+#define BCHP_HIF_RGR1_SW_INIT_0_SPARE_SW_INIT_MASK                 0x00000001
+#define BCHP_HIF_RGR1_SW_INIT_0_SPARE_SW_INIT_SHIFT                0
+#define BCHP_HIF_RGR1_SW_INIT_0_SPARE_SW_INIT_DEFAULT              0x00000000
+#define BCHP_HIF_RGR1_SW_INIT_0_SPARE_SW_INIT_DEASSERT             0
+#define BCHP_HIF_RGR1_SW_INIT_0_SPARE_SW_INIT_ASSERT               1
+
+/***************************************************************************
+ *SW_INIT_1 - RGR Bridge Software Reset 1 Register
+ ***************************************************************************/
+/* HIF_RGR1 :: SW_INIT_1 :: reserved0 [31:02] */
+#define BCHP_HIF_RGR1_SW_INIT_1_reserved0_MASK                     0xfffffffc
+#define BCHP_HIF_RGR1_SW_INIT_1_reserved0_SHIFT                    2
+
+/* HIF_RGR1 :: SW_INIT_1 :: PCIE_BRIDGE_SW_INIT [01:01] */
+#define BCHP_HIF_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_MASK           0x00000002
+#define BCHP_HIF_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_SHIFT          1
+#define BCHP_HIF_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_DEFAULT        0x00000001
+#define BCHP_HIF_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_DEASSERT       0
+#define BCHP_HIF_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_ASSERT         1
+
+/* HIF_RGR1 :: SW_INIT_1 :: PCIE_SW_PERST [00:00] */
+#define BCHP_HIF_RGR1_SW_INIT_1_PCIE_SW_PERST_MASK                 0x00000001
+#define BCHP_HIF_RGR1_SW_INIT_1_PCIE_SW_PERST_SHIFT                0
+#define BCHP_HIF_RGR1_SW_INIT_1_PCIE_SW_PERST_DEFAULT              0x00000001
+#define BCHP_HIF_RGR1_SW_INIT_1_PCIE_SW_PERST_DEASSERT             0
+#define BCHP_HIF_RGR1_SW_INIT_1_PCIE_SW_PERST_ASSERT               1
+
+#endif /* #ifndef BCHP_HIF_RGR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/7425b0/bchp_hif_spi_intr2.h
new file mode 100644
index 0000000..af58b33
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_hif_spi_intr2.h
@@ -0,0 +1,564 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:42 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_SPI_INTR2_H__
+#define BCHP_HIF_SPI_INTR2_H__
+
+/***************************************************************************
+ *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
+ ***************************************************************************/
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS            0x0041ad00 /* CPU interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_SET               0x0041ad04 /* CPU interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR             0x0041ad08 /* CPU interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS       0x0041ad0c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET          0x0041ad10 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR        0x0041ad14 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS            0x0041ad18 /* PCI interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_SET               0x0041ad1c /* PCI interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR             0x0041ad20 /* PCI interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS       0x0041ad24 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET          0x0041ad28 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR        0x0041ad2c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_hif_top_ctrl.h b/include/linux/brcmstb/7425b0/bchp_hif_top_ctrl.h
new file mode 100644
index 0000000..f5f751d
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_hif_top_ctrl.h
@@ -0,0 +1,510 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:43 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_TOP_CTRL_H__
+#define BCHP_HIF_TOP_CTRL_H__
+
+/***************************************************************************
+ *HIF_TOP_CTRL - HIF Top Control Registers
+ ***************************************************************************/
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL          0x0041b400 /* External IRQ Active Level Control Register */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL            0x0041b404 /* SPI test port select register */
+#define BCHP_HIF_TOP_CTRL_SCRATCH                0x0041b408 /* HIF Scratch Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0               0x0041b40c /* HIF Power Management Control0 Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1               0x0041b410 /* HIF Power Management Control1 Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2               0x0041b414 /* HIF Power Management Control Register:used to control SDIO_0 (CARD) */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3               0x0041b418 /* HIF Power Management Control Register:used to control SDIO_1 (EMMC) */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE             0x0041b41c /* HIF Decoded Flash Type */
+
+/***************************************************************************
+ *EXT_IRQ_LEVEL - External IRQ Active Level Control Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: reserved0 [31:06] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_MASK             0xffffffc0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_SHIFT            6
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_5_level [05:05] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_MASK       0x00000020
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_SHIFT      5
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_LOW        0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_HIGH       1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_4_level [04:04] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_MASK       0x00000010
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_SHIFT      4
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_LOW        0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_HIGH       1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_3_level [03:03] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_MASK       0x00000008
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_SHIFT      3
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_LOW        0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_HIGH       1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_2_level [02:02] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_MASK       0x00000004
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_LOW        0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_HIGH       1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_1_level [01:01] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_MASK       0x00000002
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_SHIFT      1
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_LOW        0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_HIGH       1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_0_level [00:00] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_MASK       0x00000001
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_SHIFT      0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_LOW        0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_HIGH       1
+
+/***************************************************************************
+ *SPI_DBG_SEL - SPI test port select register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_MASK               0xfffffff8
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_SHIFT              3
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: DISABLE_MSPI_FLUSH [02:02] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_MASK      0x00000004
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_SHIFT     2
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_DEFAULT   0x00000000
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SPI_RBUS_TIMER_EN [01:01] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_MASK       0x00000002
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_SHIFT      1
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_DEFAULT    0x00000000
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SDIO_TP_SEL [00:00] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SDIO_TP_SEL_MASK             0x00000001
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SDIO_TP_SEL_SHIFT            0
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SDIO_TP_SEL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *SCRATCH - HIF Scratch Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SCRATCH :: SCRATCH_BITS [31:00] */
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BITS_MASK                0xffffffff
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BITS_SHIFT               0
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BITS_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PM_CTRL0 - HIF Power Management Control0 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_PM_IN_DRIVE_INACTIVE [31:30] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_MASK   0xc0000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_SHIFT  30
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_IN_DRIVE_INACTIVE [29:28] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x30000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 28
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_CTRL_PM_IN_DRIVE_INACTIVE [27:26] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_MASK 0x0c000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_SHIFT 26
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_NOT_USED 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_DATA_PM_OUT_CTRL [25:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_MASK       0x03000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_SHIFT      24
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_ADDR_PM_OUT_CTRL [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_MASK       0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_SHIFT      22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_CTRL_PM_OUT_CTRL [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_MASK       0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_SHIFT      20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_OUT_CTRL [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_MASK      0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_SHIFT     18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_CTRL_PM_OUT_CTRL [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_MASK      0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_SHIFT     16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS7 [15:14] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_MASK            0x0000c000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_SHIFT           14
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS6 [13:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_MASK            0x00003000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_SHIFT           12
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS5 [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_MASK            0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_SHIFT           10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS4 [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_MASK            0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_SHIFT           8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS3 [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_MASK            0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_SHIFT           6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS2 [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_MASK            0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_SHIFT           4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS1 [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_MASK            0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_SHIFT           2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS0 [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_MASK            0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_SHIFT           0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_Tristate        3
+
+/***************************************************************************
+ *PM_CTRL1 - HIF Power Management Control1 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL1 :: reserved0 [31:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_MASK                  0xfffff000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_PM_IN_DRIVE_INACTIVE [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_WPB_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_MASK        0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_SHIFT       8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_DEFAULT     0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_Tristate    3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_HOLDB_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_MASK      0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_SHIFT     6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MISO_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_MASK       0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_SHIFT      4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MOSI_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_MASK        0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_SHIFT       0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_DEFAULT     0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_Tristate    3
+
+/***************************************************************************
+ *PM_CTRL2 - HIF Power Management Control Register:used to control SDIO_0 (CARD)
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved0 [31:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_MASK                  0xff000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_SHIFT                 24
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_MASK 0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_SHIFT 22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_MASK 0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_SHIFT 20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_IN_DRIVE_INACTIVE [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_IN_DRIVE_INACTIVE [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_MASK 0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_SHIFT 16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved1 [15:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_MASK                  0x0000f000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_VOLTAGE_PM_OUT_CTRL [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_LOW    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_HIGH   2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_POWER_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_MASK     0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_SHIFT    8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_DEFAULT  0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_LOW      1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_HIGH     2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_LED_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_MASK       0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_SHIFT      6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_MASK      0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_MASK       0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_SHIFT      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_Tristate   3
+
+/***************************************************************************
+ *PM_CTRL3 - HIF Power Management Control Register:used to control SDIO_1 (EMMC)
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL3 :: reserved0 [31:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved0_MASK                  0xfff00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved0_SHIFT                 20
+
+/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_DATA_PM_IN_DRIVE_INACTIVE [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_CMD_PM_IN_DRIVE_INACTIVE [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_MASK 0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_SHIFT 16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL3 :: reserved1 [15:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved1_MASK                  0x0000ffc0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved1_SHIFT                 6
+
+/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_DATA_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_MASK      0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_CMD_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_MASK       0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_SHIFT      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_Tristate   3
+
+/***************************************************************************
+ *FLASH_TYPE - HIF Decoded Flash Type
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: FLASH_TYPE :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_MASK                0xfffffff8
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_SHIFT               3
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: InvalidStrap [02:02] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_MASK             0x00000004
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_SHIFT            2
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_DEFAULT          0x00000000
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: FLASH_TYPE [01:00] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_MASK               0x00000003
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SHIFT              0
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_ParallelNOR        0
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_Nand               1
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SerialNOR          2
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_eMMC               3
+
+#endif /* #ifndef BCHP_HIF_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_irq0.h b/include/linux/brcmstb/7425b0/bchp_irq0.h
new file mode 100644
index 0000000..e5f6892
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_irq0.h
@@ -0,0 +1,214 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:43 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ0_H__
+#define BCHP_IRQ0_H__
+
+/***************************************************************************
+ *IRQ0 - Level 2 CPU Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ0_IRQEN                          0x00406780 /* Interrupt Enable */
+#define BCHP_IRQ0_IRQSTAT                        0x00406784 /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ0 :: IRQEN :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQEN_reserved0_MASK                             0xf8000000
+#define BCHP_IRQ0_IRQEN_reserved0_SHIFT                            27
+
+/* IRQ0 :: IRQEN :: iice_irqen [26:26] */
+#define BCHP_IRQ0_IRQEN_iice_irqen_MASK                            0x04000000
+#define BCHP_IRQ0_IRQEN_iice_irqen_SHIFT                           26
+#define BCHP_IRQ0_IRQEN_iice_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: iicd_irqen [25:25] */
+#define BCHP_IRQ0_IRQEN_iicd_irqen_MASK                            0x02000000
+#define BCHP_IRQ0_IRQEN_iicd_irqen_SHIFT                           25
+#define BCHP_IRQ0_IRQEN_iicd_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: iicc_irqen [24:24] */
+#define BCHP_IRQ0_IRQEN_iicc_irqen_MASK                            0x01000000
+#define BCHP_IRQ0_IRQEN_iicc_irqen_SHIFT                           24
+#define BCHP_IRQ0_IRQEN_iicc_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQEN_reserved1_MASK                             0x00f80000
+#define BCHP_IRQ0_IRQEN_reserved1_SHIFT                            19
+
+/* IRQ0 :: IRQEN :: uartc_irqen [18:18] */
+#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK                           0x00040000
+#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT                          18
+#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uartb_irqen [17:17] */
+#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK                           0x00020000
+#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT                          17
+#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uarta_irqen [16:16] */
+#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK                           0x00010000
+#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT                          16
+#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQEN_reserved2_MASK                             0x0000fc00
+#define BCHP_IRQ0_IRQEN_reserved2_SHIFT                            10
+
+/* IRQ0 :: IRQEN :: uc_irqen [09:09] */
+#define BCHP_IRQ0_IRQEN_uc_irqen_MASK                              0x00000200
+#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT                             9
+#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQEN_reserved3_MASK                             0x00000180
+#define BCHP_IRQ0_IRQEN_reserved3_SHIFT                            7
+
+/* IRQ0 :: IRQEN :: gio_irqen [06:06] */
+#define BCHP_IRQ0_IRQEN_gio_irqen_MASK                             0x00000040
+#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT                            6
+#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQEN :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQEN_reserved4_MASK                             0x00000020
+#define BCHP_IRQ0_IRQEN_reserved4_SHIFT                            5
+
+/* IRQ0 :: IRQEN :: ua_irqen [04:04] */
+#define BCHP_IRQ0_IRQEN_ua_irqen_MASK                              0x00000010
+#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT                             4
+#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: ub_irqen [03:03] */
+#define BCHP_IRQ0_IRQEN_ub_irqen_MASK                              0x00000008
+#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT                             3
+#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: irb_irqen [02:02] */
+#define BCHP_IRQ0_IRQEN_irb_irqen_MASK                             0x00000004
+#define BCHP_IRQ0_IRQEN_irb_irqen_SHIFT                            2
+#define BCHP_IRQ0_IRQEN_irb_irqen_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQEN :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQEN_reserved5_MASK                             0x00000003
+#define BCHP_IRQ0_IRQEN_reserved5_SHIFT                            0
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ0 :: IRQSTAT :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQSTAT_reserved0_MASK                           0xf8000000
+#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT                          27
+
+/* IRQ0 :: IRQSTAT :: iiceirq [26:26] */
+#define BCHP_IRQ0_IRQSTAT_iiceirq_MASK                             0x04000000
+#define BCHP_IRQ0_IRQSTAT_iiceirq_SHIFT                            26
+#define BCHP_IRQ0_IRQSTAT_iiceirq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: iicdirq [25:25] */
+#define BCHP_IRQ0_IRQSTAT_iicdirq_MASK                             0x02000000
+#define BCHP_IRQ0_IRQSTAT_iicdirq_SHIFT                            25
+#define BCHP_IRQ0_IRQSTAT_iicdirq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: iiccirq [24:24] */
+#define BCHP_IRQ0_IRQSTAT_iiccirq_MASK                             0x01000000
+#define BCHP_IRQ0_IRQSTAT_iiccirq_SHIFT                            24
+#define BCHP_IRQ0_IRQSTAT_iiccirq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQSTAT_reserved1_MASK                           0x00f80000
+#define BCHP_IRQ0_IRQSTAT_reserved1_SHIFT                          19
+
+/* IRQ0 :: IRQSTAT :: uartc_irq [18:18] */
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK                           0x00040000
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT                          18
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uartb_irq [17:17] */
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK                           0x00020000
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT                          17
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uarta_irq [16:16] */
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK                           0x00010000
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT                          16
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQSTAT_reserved2_MASK                           0x0000fc00
+#define BCHP_IRQ0_IRQSTAT_reserved2_SHIFT                          10
+
+/* IRQ0 :: IRQSTAT :: ucirq [09:09] */
+#define BCHP_IRQ0_IRQSTAT_ucirq_MASK                               0x00000200
+#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT                              9
+#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQSTAT_reserved3_MASK                           0x00000180
+#define BCHP_IRQ0_IRQSTAT_reserved3_SHIFT                          7
+
+/* IRQ0 :: IRQSTAT :: gioirq [06:06] */
+#define BCHP_IRQ0_IRQSTAT_gioirq_MASK                              0x00000040
+#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT                             6
+#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQSTAT_reserved4_MASK                           0x00000020
+#define BCHP_IRQ0_IRQSTAT_reserved4_SHIFT                          5
+
+/* IRQ0 :: IRQSTAT :: uairq [04:04] */
+#define BCHP_IRQ0_IRQSTAT_uairq_MASK                               0x00000010
+#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT                              4
+#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: ubirq [03:03] */
+#define BCHP_IRQ0_IRQSTAT_ubirq_MASK                               0x00000008
+#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT                              3
+#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: irbirq [02:02] */
+#define BCHP_IRQ0_IRQSTAT_irbirq_MASK                              0x00000004
+#define BCHP_IRQ0_IRQSTAT_irbirq_SHIFT                             2
+#define BCHP_IRQ0_IRQSTAT_irbirq_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQSTAT_reserved5_MASK                           0x00000003
+#define BCHP_IRQ0_IRQSTAT_reserved5_SHIFT                          0
+
+#endif /* #ifndef BCHP_IRQ0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_irq1.h b/include/linux/brcmstb/7425b0/bchp_irq1.h
new file mode 100644
index 0000000..9248f2d
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_irq1.h
@@ -0,0 +1,50 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon May 17 04:26:48 2010
+ *                 MD5 Checksum         d3eddea23beec7e33d13b4bcb5193126
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ1_H__
+#define BCHP_IRQ1_H__
+
+/***************************************************************************
+ *IRQ1 - Level 2 PCI Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ1_IRQEN                          0x00406788 /* Interrupt Enable */
+#define BCHP_IRQ1_IRQSTAT                        0x0040678c /* Interrupt Status */
+
+#endif /* #ifndef BCHP_IRQ1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_mem_dma_0.h b/include/linux/brcmstb/7425b0/bchp_mem_dma_0.h
new file mode 100644
index 0000000..bad04b8
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_mem_dma_0.h
@@ -0,0 +1,154 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:43 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEM_DMA_0_H__
+#define BCHP_MEM_DMA_0_H__
+
+/***************************************************************************
+ *MEM_DMA_0 - MEM_DMA_0 Registers
+ ***************************************************************************/
+#define BCHP_MEM_DMA_0_REVISION                  0x00374200 /* MEM_DMA REVISION */
+#define BCHP_MEM_DMA_0_FIRST_DESC                0x00374204 /* MEM_DMA First Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CTRL                      0x00374208 /* MEM_DMA Control Register */
+#define BCHP_MEM_DMA_0_WAKE_CTRL                 0x0037420c /* MEM_DMA Wake Control Register */
+#define BCHP_MEM_DMA_0_STATUS                    0x00374214 /* MEM_DMA Status Register */
+#define BCHP_MEM_DMA_0_CUR_DESC                  0x00374218 /* MEM_DMA Current Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CUR_BYTE                  0x0037421c /* MEM_DMA Current Byte Count Register */
+#define BCHP_MEM_DMA_0_SCRATCH                   0x00374224 /* MEM_DMA Scratch Register */
+
+/***************************************************************************
+ *REVISION - MEM_DMA REVISION
+ ***************************************************************************/
+/* MEM_DMA_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_0_REVISION_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_0_REVISION_reserved0_SHIFT                    16
+
+/* MEM_DMA_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_MASK                         0x0000ff00
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_SHIFT                        8
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_DEFAULT                      0x00000002
+
+/* MEM_DMA_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_MEM_DMA_0_REVISION_MINOR_MASK                         0x000000ff
+#define BCHP_MEM_DMA_0_REVISION_MINOR_SHIFT                        0
+#define BCHP_MEM_DMA_0_REVISION_MINOR_DEFAULT                      0x0000000a
+
+/***************************************************************************
+ *FIRST_DESC - MEM_DMA First Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: FIRST_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_MASK                        0xffffffff
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_SHIFT                       0
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *CTRL - MEM_DMA Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CTRL :: reserved0 [31:01] */
+#define BCHP_MEM_DMA_0_CTRL_reserved0_MASK                         0xfffffffe
+#define BCHP_MEM_DMA_0_CTRL_reserved0_SHIFT                        1
+
+/* MEM_DMA_0 :: CTRL :: RUN [00:00] */
+#define BCHP_MEM_DMA_0_CTRL_RUN_MASK                               0x00000001
+#define BCHP_MEM_DMA_0_CTRL_RUN_SHIFT                              0
+#define BCHP_MEM_DMA_0_CTRL_RUN_DEFAULT                            0x00000000
+
+/***************************************************************************
+ *WAKE_CTRL - MEM_DMA Wake Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: WAKE_CTRL :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_MASK                    0xfffffffc
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_SHIFT                   2
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE_MODE [01:01] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_MASK                    0x00000002
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_SHIFT                   1
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_DEFAULT                 0x00000000
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE [00:00] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MASK                         0x00000001
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_SHIFT                        0
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *STATUS - MEM_DMA Status Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: STATUS :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_MEM_DMA_0_STATUS_reserved0_SHIFT                      2
+
+/* MEM_DMA_0 :: STATUS :: DMA_STATUS [01:00] */
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_MASK                      0x00000003
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_SHIFT                     0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_DEFAULT                   0x00000000
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Idle                      0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Busy                      1
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Sleep                     2
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Reserved                  3
+
+/***************************************************************************
+ *CUR_DESC - MEM_DMA Current Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_MASK                          0xffffffff
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_SHIFT                         0
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *CUR_BYTE - MEM_DMA Current Byte Count Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_BYTE :: reserved0 [31:25] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_MASK                     0xfe000000
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_SHIFT                    25
+
+/* MEM_DMA_0 :: CUR_BYTE :: COUNT [24:00] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_MASK                         0x01ffffff
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_SHIFT                        0
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *SCRATCH - MEM_DMA Scratch Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_MASK                    0xffffffff
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_SHIFT                   0
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_DEFAULT                 0x00000000
+
+#endif /* #ifndef BCHP_MEM_DMA_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_memc_arb_1.h b/include/linux/brcmstb/7425b0/bchp_memc_arb_1.h
new file mode 100644
index 0000000..5f49122
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_memc_arb_1.h
@@ -0,0 +1,4089 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Jun 13 15:31:36 2011
+ *                 MD5 Checksum         a14f8e7f638a7ebe759043ff756befc5
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7425/rdb/b0/bchp_memc_arb_1.h $
+ * 
+ * Hydra_Software_Devel/3   6/14/11 2:29p vanessah
+ * SW7425-715: 7425 B0 RDB resync
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_ARB_1_H__
+#define BCHP_MEMC_ARB_1_H__
+
+/***************************************************************************
+ *MEMC_ARB_1 - Memory Controller Arbitration & Client Info Registers 1
+ ***************************************************************************/
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER 0x003c1000 /* MEMC CORE and IOBUF Interface Debug Register */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0            0x003c1004 /* Client Programming register for client 0. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1            0x003c1008 /* Client Programming register for client 1. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2            0x003c100c /* Client Programming register for client 2. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3            0x003c1010 /* Client Programming register for client 3. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4            0x003c1014 /* Client Programming register for client 4. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5            0x003c1018 /* Client Programming register for client 5. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6            0x003c101c /* Client Programming register for client 6. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7            0x003c1020 /* Client Programming register for client 7. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8            0x003c1024 /* Client Programming register for client 8. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9            0x003c1028 /* Client Programming register for client 9. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10           0x003c102c /* Client Programming register for client 10. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11           0x003c1030 /* Client Programming register for client 11. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12           0x003c1034 /* Client Programming register for client 12. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13           0x003c1038 /* Client Programming register for client 13. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14           0x003c103c /* Client Programming register for client 14. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15           0x003c1040 /* Client Programming register for client 15. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16           0x003c1044 /* Client Programming register for client 16. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17           0x003c1048 /* Client Programming register for client 17. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18           0x003c104c /* Client Programming register for client 18. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19           0x003c1050 /* Client Programming register for client 19. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20           0x003c1054 /* Client Programming register for client 20. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21           0x003c1058 /* Client Programming register for client 21. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22           0x003c105c /* Client Programming register for client 22. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23           0x003c1060 /* Client Programming register for client 23. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24           0x003c1064 /* Client Programming register for client 24. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25           0x003c1068 /* Client Programming register for client 25. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26           0x003c106c /* Client Programming register for client 26. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27           0x003c1070 /* Client Programming register for client 27. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28           0x003c1074 /* Client Programming register for client 28. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29           0x003c1078 /* Client Programming register for client 29. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30           0x003c107c /* Client Programming register for client 30. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31           0x003c1080 /* Client Programming register for client 31. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32           0x003c1084 /* Client Programming register for client 32. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33           0x003c1088 /* Client Programming register for client 33. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34           0x003c108c /* Client Programming register for client 34. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35           0x003c1090 /* Client Programming register for client 35. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36           0x003c1094 /* Client Programming register for client 36. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37           0x003c1098 /* Client Programming register for client 37. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38           0x003c109c /* Client Programming register for client 38. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39           0x003c10a0 /* Client Programming register for client 39. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40           0x003c10a4 /* Client Programming register for client 40. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41           0x003c10a8 /* Client Programming register for client 41. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42           0x003c10ac /* Client Programming register for client 42. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43           0x003c10b0 /* Client Programming register for client 43. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44           0x003c10b4 /* Client Programming register for client 44. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45           0x003c10b8 /* Client Programming register for client 45. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46           0x003c10bc /* Client Programming register for client 46. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47           0x003c10c0 /* Client Programming register for client 47. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48           0x003c10c4 /* Client Programming register for client 48. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49           0x003c10c8 /* Client Programming register for client 49. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50           0x003c10cc /* Client Programming register for client 50. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51           0x003c10d0 /* Client Programming register for client 51. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52           0x003c10d4 /* Client Programming register for client 52. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53           0x003c10d8 /* Client Programming register for client 53. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54           0x003c10dc /* Client Programming register for client 54. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55           0x003c10e0 /* Client Programming register for client 55. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56           0x003c10e4 /* Client Programming register for client 56. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57           0x003c10e8 /* Client Programming register for client 57. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58           0x003c10ec /* Client Programming register for client 58. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59           0x003c10f0 /* Client Programming register for client 59. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60           0x003c10f4 /* Client Programming register for client 60. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61           0x003c10f8 /* Client Programming register for client 61. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62           0x003c10fc /* Client Programming register for client 62. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63           0x003c1100 /* Client Programming register for client 63. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64           0x003c1104 /* Client Programming register for client 64. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65           0x003c1108 /* Client Programming register for client 65. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66           0x003c110c /* Client Programming register for client 66. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67           0x003c1110 /* Client Programming register for client 67. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68           0x003c1114 /* Client Programming register for client 68. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69           0x003c1118 /* Client Programming register for client 69. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70           0x003c111c /* Client Programming register for client 70. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71           0x003c1120 /* Client Programming register for client 71. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72           0x003c1124 /* Client Programming register for client 72. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73           0x003c1128 /* Client Programming register for client 73. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74           0x003c112c /* Client Programming register for client 74. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75           0x003c1130 /* Client Programming register for client 75. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76           0x003c1134 /* Client Programming register for client 76. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77           0x003c1138 /* Client Programming register for client 77. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78           0x003c113c /* Client Programming register for client 78. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79           0x003c1140 /* Client Programming register for client 79. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80           0x003c1144 /* Client Programming register for client 80. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81           0x003c1148 /* Client Programming register for client 81. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82           0x003c114c /* Client Programming register for client 82. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83           0x003c1150 /* Client Programming register for client 83. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84           0x003c1154 /* Client Programming register for client 84. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85           0x003c1158 /* Client Programming register for client 85. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86           0x003c115c /* Client Programming register for client 86. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87           0x003c1160 /* Client Programming register for client 87. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88           0x003c1164 /* Client Programming register for client 88. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89           0x003c1168 /* Client Programming register for client 89. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90           0x003c116c /* Client Programming register for client 90. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91           0x003c1170 /* Client Programming register for client 91. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92           0x003c1174 /* Client Programming register for client 92. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93           0x003c1178 /* Client Programming register for client 93. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94           0x003c117c /* Client Programming register for client 94. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95           0x003c1180 /* Client Programming register for client 95. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96           0x003c1184 /* Client Programming register for client 96. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97           0x003c1188 /* Client Programming register for client 97. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98           0x003c118c /* Client Programming register for client 98. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99           0x003c1190 /* Client Programming register for client 99. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100          0x003c1194 /* Client Programming register for client 100. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101          0x003c1198 /* Client Programming register for client 101. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102          0x003c119c /* Client Programming register for client 102. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103          0x003c11a0 /* Client Programming register for client 103. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104          0x003c11a4 /* Client Programming register for client 104. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105          0x003c11a8 /* Client Programming register for client 105. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106          0x003c11ac /* Client Programming register for client 106. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107          0x003c11b0 /* Client Programming register for client 107. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108          0x003c11b4 /* Client Programming register for client 108. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109          0x003c11b8 /* Client Programming register for client 109. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110          0x003c11bc /* Client Programming register for client 110. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111          0x003c11c0 /* Client Programming register for client 111. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112          0x003c11c4 /* Client Programming register for client 112. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113          0x003c11c8 /* Client Programming register for client 113. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114          0x003c11cc /* Client Programming register for client 114. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115          0x003c11d0 /* Client Programming register for client 115. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116          0x003c11d4 /* Client Programming register for client 116. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117          0x003c11d8 /* Client Programming register for client 117. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118          0x003c11dc /* Client Programming register for client 118. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119          0x003c11e0 /* Client Programming register for client 119. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120          0x003c11e4 /* Client Programming register for client 120. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121          0x003c11e8 /* Client Programming register for client 121. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122          0x003c11ec /* Client Programming register for client 122. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123          0x003c11f0 /* Client Programming register for client 123. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124          0x003c11f4 /* Client Programming register for client 124. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125          0x003c11f8 /* Client Programming register for client 125. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126          0x003c11fc /* Client Programming register for client 126. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127          0x003c1200 /* Client Programming register for client 127 */
+#define BCHP_MEMC_ARB_1_REQ_MASK_0               0x003c1204 /* Request Mask register for Clients 0 to 31 */
+#define BCHP_MEMC_ARB_1_REQ_MASK_1               0x003c1208 /* Request Mask register for Clients 32 to 63 */
+#define BCHP_MEMC_ARB_1_REQ_MASK_2               0x003c120c /* Request Mask register for Clients 64 to 95 */
+#define BCHP_MEMC_ARB_1_REQ_MASK_3               0x003c1210 /* Request Mask register for Clients 96 to 127 */
+#define BCHP_MEMC_ARB_1_ARB_WINNER               0x003c1214 /* SCB-Arbitration Winner. */
+#define BCHP_MEMC_ARB_1_RTS_ERR_0                0x003c1218 /* RTS Deadline miss register for Clients 0 to 31 */
+#define BCHP_MEMC_ARB_1_RTS_ERR_1                0x003c121c /* RTS Deadline miss register for Clients 32 to 63 */
+#define BCHP_MEMC_ARB_1_RTS_ERR_2                0x003c1220 /* RTS Deadline miss register for Clients 64 to 95 */
+#define BCHP_MEMC_ARB_1_RTS_ERR_3                0x003c1224 /* RTS Deadline miss register for Clients 96 to 127 */
+#define BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD       0x003c1228 /* Arbiter fullness threshold register */
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE     0x003c122c /* Minimum command size register */
+#define BCHP_MEMC_ARB_1_RTS_ERR_INFO_WRITE_CLEAR 0x003c1230 /* MEMC RTS_ERR_INFO write clear register */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER 0x003c1234 /* MEMC SCB Interface and Arbiter State Machine and FIFO Debug Register */
+#define BCHP_MEMC_ARB_1_SPARE_1                  0x003c1238 /* Spare Register 1 . */
+#define BCHP_MEMC_ARB_1_SPARE_2                  0x003c123c /* Spare Register 2 . */
+#define BCHP_MEMC_ARB_1_SPARE_RO_1               0x003c1240 /* Read only Spare Register 1 . */
+#define BCHP_MEMC_ARB_1_SPARE_RO_2               0x003c1244 /* Read only Spare Register 2 . */
+
+/***************************************************************************
+ *ANALOG_PHY_DEBUG_REGISTER - MEMC CORE and IOBUF Interface Debug Register
+ ***************************************************************************/
+/* MEMC_ARB_1 :: ANALOG_PHY_DEBUG_REGISTER :: reserved0 [31:08] */
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_reserved0_MASK   0xffffff00
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_reserved0_SHIFT  8
+
+/* MEMC_ARB_1 :: ANALOG_PHY_DEBUG_REGISTER :: PMC2MEMC_BSP_RDY [07:07] */
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_PMC2MEMC_BSP_RDY_MASK 0x00000080
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_PMC2MEMC_BSP_RDY_SHIFT 7
+
+/* MEMC_ARB_1 :: ANALOG_PHY_DEBUG_REGISTER :: PHY2CORE_INIT_RDY [06:06] */
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_PHY2CORE_INIT_RDY_MASK 0x00000040
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_PHY2CORE_INIT_RDY_SHIFT 6
+
+/* MEMC_ARB_1 :: ANALOG_PHY_DEBUG_REGISTER :: PHY2CORE_POWERDOWN_RDY [05:05] */
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_PHY2CORE_POWERDOWN_RDY_MASK 0x00000020
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_PHY2CORE_POWERDOWN_RDY_SHIFT 5
+
+/* MEMC_ARB_1 :: ANALOG_PHY_DEBUG_REGISTER :: IO2C_CMD_DATA_FIFO_FULL [04:04] */
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_IO2C_CMD_DATA_FIFO_FULL_MASK 0x00000010
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_IO2C_CMD_DATA_FIFO_FULL_SHIFT 4
+
+/* MEMC_ARB_1 :: ANALOG_PHY_DEBUG_REGISTER :: IO2C_RD_DATA_FIFO_EMPTY [03:03] */
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_IO2C_RD_DATA_FIFO_EMPTY_MASK 0x00000008
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_IO2C_RD_DATA_FIFO_EMPTY_SHIFT 3
+
+/* MEMC_ARB_1 :: ANALOG_PHY_DEBUG_REGISTER :: C2IO_CMD_DATA_FIFO_PUSH [02:02] */
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_C2IO_CMD_DATA_FIFO_PUSH_MASK 0x00000004
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_C2IO_CMD_DATA_FIFO_PUSH_SHIFT 2
+
+/* MEMC_ARB_1 :: ANALOG_PHY_DEBUG_REGISTER :: DRAM_RD_DATA_FIFO_POP [01:01] */
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_DRAM_RD_DATA_FIFO_POP_MASK 0x00000002
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_DRAM_RD_DATA_FIFO_POP_SHIFT 1
+
+/* MEMC_ARB_1 :: ANALOG_PHY_DEBUG_REGISTER :: CORE2PHY_PLL_DLL_SHUTDOWN_REQ [00:00] */
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_CORE2PHY_PLL_DLL_SHUTDOWN_REQ_MASK 0x00000001
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_CORE2PHY_PLL_DLL_SHUTDOWN_REQ_SHIFT 0
+
+/***************************************************************************
+ *CLIENT_INFO_0 - Client Programming register for client 0.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_0 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_RR_EN_MASK                   0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_RR_EN_SHIFT                  31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_RR_EN_DEFAULT                1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_RR_EN_DISABLED               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_RR_EN_ENABLED                1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_0 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_reserved0_MASK               0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_reserved0_SHIFT              27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_0 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_BO_VAL_MASK                  0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_BO_VAL_SHIFT                 12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_BO_VAL_DEFAULT               0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_0 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_reserved1_MASK               0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_reserved1_SHIFT              7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_0 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_PR_TAG_MASK                  0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_PR_TAG_SHIFT                 0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_PR_TAG_DEFAULT               0
+
+/***************************************************************************
+ *CLIENT_INFO_1 - Client Programming register for client 1.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_1 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_RR_EN_MASK                   0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_RR_EN_SHIFT                  31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_RR_EN_DEFAULT                1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_RR_EN_DISABLED               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_RR_EN_ENABLED                1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_1 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_reserved0_MASK               0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_reserved0_SHIFT              27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_1 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_BO_VAL_MASK                  0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_BO_VAL_SHIFT                 12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_BO_VAL_DEFAULT               0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_1 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_reserved1_MASK               0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_reserved1_SHIFT              7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_1 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_PR_TAG_MASK                  0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_PR_TAG_SHIFT                 0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_PR_TAG_DEFAULT               0
+
+/***************************************************************************
+ *CLIENT_INFO_2 - Client Programming register for client 2.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_2 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_RR_EN_MASK                   0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_RR_EN_SHIFT                  31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_RR_EN_DEFAULT                1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_RR_EN_DISABLED               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_RR_EN_ENABLED                1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_2 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_reserved0_MASK               0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_reserved0_SHIFT              27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_2 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_BO_VAL_MASK                  0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_BO_VAL_SHIFT                 12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_BO_VAL_DEFAULT               0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_2 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_reserved1_MASK               0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_reserved1_SHIFT              7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_2 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_PR_TAG_MASK                  0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_PR_TAG_SHIFT                 0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_PR_TAG_DEFAULT               0
+
+/***************************************************************************
+ *CLIENT_INFO_3 - Client Programming register for client 3.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_3 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_RR_EN_MASK                   0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_RR_EN_SHIFT                  31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_RR_EN_DEFAULT                1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_RR_EN_DISABLED               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_RR_EN_ENABLED                1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_3 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_reserved0_MASK               0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_reserved0_SHIFT              27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_3 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_BO_VAL_MASK                  0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_BO_VAL_SHIFT                 12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_BO_VAL_DEFAULT               0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_3 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_reserved1_MASK               0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_reserved1_SHIFT              7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_3 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_PR_TAG_MASK                  0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_PR_TAG_SHIFT                 0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_PR_TAG_DEFAULT               0
+
+/***************************************************************************
+ *CLIENT_INFO_4 - Client Programming register for client 4.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_4 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_RR_EN_MASK                   0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_RR_EN_SHIFT                  31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_RR_EN_DEFAULT                1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_RR_EN_DISABLED               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_RR_EN_ENABLED                1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_4 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_reserved0_MASK               0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_reserved0_SHIFT              27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_4 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_BO_VAL_MASK                  0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_BO_VAL_SHIFT                 12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_BO_VAL_DEFAULT               0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_4 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_reserved1_MASK               0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_reserved1_SHIFT              7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_4 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_PR_TAG_MASK                  0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_PR_TAG_SHIFT                 0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_PR_TAG_DEFAULT               0
+
+/***************************************************************************
+ *CLIENT_INFO_5 - Client Programming register for client 5.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_5 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_RR_EN_MASK                   0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_RR_EN_SHIFT                  31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_RR_EN_DEFAULT                1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_RR_EN_DISABLED               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_RR_EN_ENABLED                1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_5 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_reserved0_MASK               0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_reserved0_SHIFT              27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_5 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_BO_VAL_MASK                  0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_BO_VAL_SHIFT                 12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_BO_VAL_DEFAULT               0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_5 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_reserved1_MASK               0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_reserved1_SHIFT              7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_5 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_PR_TAG_MASK                  0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_PR_TAG_SHIFT                 0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_PR_TAG_DEFAULT               0
+
+/***************************************************************************
+ *CLIENT_INFO_6 - Client Programming register for client 6.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_6 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_RR_EN_MASK                   0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_RR_EN_SHIFT                  31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_RR_EN_DEFAULT                1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_RR_EN_DISABLED               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_RR_EN_ENABLED                1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_6 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_reserved0_MASK               0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_reserved0_SHIFT              27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_6 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_BO_VAL_MASK                  0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_BO_VAL_SHIFT                 12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_BO_VAL_DEFAULT               0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_6 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_reserved1_MASK               0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_reserved1_SHIFT              7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_6 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_PR_TAG_MASK                  0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_PR_TAG_SHIFT                 0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_PR_TAG_DEFAULT               0
+
+/***************************************************************************
+ *CLIENT_INFO_7 - Client Programming register for client 7.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_7 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_RR_EN_MASK                   0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_RR_EN_SHIFT                  31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_RR_EN_DEFAULT                1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_RR_EN_DISABLED               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_RR_EN_ENABLED                1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_7 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_reserved0_MASK               0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_reserved0_SHIFT              27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_7 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_BO_VAL_MASK                  0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_BO_VAL_SHIFT                 12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_BO_VAL_DEFAULT               0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_7 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_reserved1_MASK               0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_reserved1_SHIFT              7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_7 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_PR_TAG_MASK                  0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_PR_TAG_SHIFT                 0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_PR_TAG_DEFAULT               0
+
+/***************************************************************************
+ *CLIENT_INFO_8 - Client Programming register for client 8.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_8 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_RR_EN_MASK                   0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_RR_EN_SHIFT                  31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_RR_EN_DEFAULT                1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_RR_EN_DISABLED               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_RR_EN_ENABLED                1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_8 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_reserved0_MASK               0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_reserved0_SHIFT              27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_8 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_BO_VAL_MASK                  0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_BO_VAL_SHIFT                 12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_BO_VAL_DEFAULT               0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_8 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_reserved1_MASK               0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_reserved1_SHIFT              7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_8 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_PR_TAG_MASK                  0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_PR_TAG_SHIFT                 0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_PR_TAG_DEFAULT               0
+
+/***************************************************************************
+ *CLIENT_INFO_9 - Client Programming register for client 9.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_9 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_RR_EN_MASK                   0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_RR_EN_SHIFT                  31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_RR_EN_DEFAULT                1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_RR_EN_DISABLED               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_RR_EN_ENABLED                1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_9 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_reserved0_MASK               0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_reserved0_SHIFT              27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_9 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_BO_VAL_MASK                  0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_BO_VAL_SHIFT                 12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_BO_VAL_DEFAULT               0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_9 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_reserved1_MASK               0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_reserved1_SHIFT              7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_9 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_PR_TAG_MASK                  0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_PR_TAG_SHIFT                 0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_PR_TAG_DEFAULT               0
+
+/***************************************************************************
+ *CLIENT_INFO_10 - Client Programming register for client 10.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_10 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_10 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_10 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_10 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_10 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_11 - Client Programming register for client 11.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_11 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_11 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_11 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_11 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_11 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_12 - Client Programming register for client 12.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_12 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_12 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_12 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_12 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_12 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_13 - Client Programming register for client 13.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_13 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_13 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_13 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_13 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_13 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_14 - Client Programming register for client 14.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_14 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_14 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_14 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_14 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_14 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_15 - Client Programming register for client 15.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_15 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_15 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_15 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_15 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_15 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_16 - Client Programming register for client 16.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_16 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_16 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_16 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_16 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_16 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_17 - Client Programming register for client 17.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_17 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_17 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_17 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_17 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_17 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_18 - Client Programming register for client 18.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_18 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_18 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_18 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_18 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_18 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_19 - Client Programming register for client 19.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_19 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_19 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_19 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_19 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_19 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_20 - Client Programming register for client 20.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_20 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_20 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_20 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_20 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_20 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_21 - Client Programming register for client 21.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_21 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_21 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_21 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_21 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_21 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_22 - Client Programming register for client 22.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_22 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_22 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_22 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_22 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_22 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_23 - Client Programming register for client 23.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_23 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_23 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_23 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_23 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_23 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_24 - Client Programming register for client 24.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_24 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_24 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_24 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_24 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_24 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_25 - Client Programming register for client 25.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_25 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_25 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_25 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_25 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_25 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_26 - Client Programming register for client 26.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_26 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_26 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_26 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_26 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_26 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_27 - Client Programming register for client 27.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_27 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_27 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_27 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_27 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_27 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_28 - Client Programming register for client 28.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_28 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_28 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_28 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_28 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_28 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_29 - Client Programming register for client 29.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_29 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_29 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_29 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_29 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_29 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_30 - Client Programming register for client 30.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_30 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_30 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_30 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_30 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_30 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_31 - Client Programming register for client 31.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_31 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_31 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_31 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_31 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_31 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_32 - Client Programming register for client 32.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_32 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_32 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_32 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_32 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_32 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_33 - Client Programming register for client 33.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_33 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_33 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_33 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_33 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_33 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_34 - Client Programming register for client 34.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_34 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_34 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_34 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_34 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_34 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_35 - Client Programming register for client 35.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_35 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_35 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_35 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_35 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_35 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_36 - Client Programming register for client 36.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_36 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_36 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_36 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_36 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_36 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_37 - Client Programming register for client 37.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_37 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_37 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_37 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_37 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_37 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_38 - Client Programming register for client 38.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_38 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_38 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_38 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_38 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_38 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_39 - Client Programming register for client 39.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_39 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_39 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_39 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_39 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_39 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_40 - Client Programming register for client 40.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_40 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_40 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_40 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_40 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_40 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_41 - Client Programming register for client 41.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_41 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_41 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_41 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_41 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_41 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_42 - Client Programming register for client 42.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_42 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_42 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_42 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_42 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_42 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_43 - Client Programming register for client 43.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_43 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_43 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_43 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_43 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_43 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_44 - Client Programming register for client 44.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_44 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_44 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_44 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_44 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_44 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_45 - Client Programming register for client 45.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_45 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_45 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_45 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_45 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_45 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_46 - Client Programming register for client 46.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_46 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_46 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_46 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_46 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_46 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_47 - Client Programming register for client 47.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_47 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_47 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_47 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_47 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_47 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_48 - Client Programming register for client 48.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_48 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_48 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_48 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_48 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_48 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_49 - Client Programming register for client 49.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_49 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_49 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_49 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_49 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_49 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_50 - Client Programming register for client 50.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_50 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_50 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_50 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_50 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_50 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_51 - Client Programming register for client 51.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_51 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_51 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_51 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_51 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_51 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_52 - Client Programming register for client 52.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_52 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_52 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_52 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_52 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_52 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_53 - Client Programming register for client 53.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_53 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_53 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_53 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_53 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_53 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_54 - Client Programming register for client 54.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_54 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_54 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_54 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_54 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_54 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_55 - Client Programming register for client 55.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_55 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_55 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_55 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_55 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_55 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_56 - Client Programming register for client 56.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_56 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_56 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_56 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_56 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_56 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_57 - Client Programming register for client 57.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_57 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_57 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_57 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_57 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_57 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_58 - Client Programming register for client 58.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_58 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_58 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_58 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_58 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_58 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_59 - Client Programming register for client 59.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_59 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_59 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_59 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_59 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_59 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_60 - Client Programming register for client 60.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_60 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_60 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_60 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_60 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_60 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_61 - Client Programming register for client 61.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_61 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_61 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_61 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_61 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_61 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_62 - Client Programming register for client 62.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_62 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_62 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_62 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_62 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_62 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_63 - Client Programming register for client 63.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_63 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_63 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_63 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_63 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_63 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_64 - Client Programming register for client 64.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_64 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_64 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_64 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_64 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_64 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_65 - Client Programming register for client 65.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_65 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_65 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_65 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_65 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_65 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_66 - Client Programming register for client 66.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_66 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_66 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_66 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_66 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_66 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_67 - Client Programming register for client 67.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_67 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_67 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_67 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_67 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_67 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_68 - Client Programming register for client 68.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_68 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_68 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_68 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_68 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_68 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_69 - Client Programming register for client 69.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_69 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_69 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_69 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_69 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_69 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_70 - Client Programming register for client 70.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_70 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_70 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_70 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_70 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_70 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_71 - Client Programming register for client 71.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_71 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_71 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_71 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_71 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_71 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_72 - Client Programming register for client 72.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_72 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_72 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_72 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_72 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_72 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_73 - Client Programming register for client 73.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_73 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_73 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_73 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_73 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_73 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_74 - Client Programming register for client 74.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_74 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_74 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_74 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_74 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_74 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_75 - Client Programming register for client 75.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_75 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_75 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_75 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_75 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_75 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_76 - Client Programming register for client 76.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_76 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_76 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_76 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_76 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_76 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_77 - Client Programming register for client 77.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_77 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_77 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_77 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_77 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_77 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_78 - Client Programming register for client 78.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_78 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_78 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_78 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_78 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_78 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_79 - Client Programming register for client 79.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_79 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_79 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_79 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_79 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_79 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_80 - Client Programming register for client 80.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_80 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_80 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_80 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_80 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_80 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_81 - Client Programming register for client 81.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_81 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_81 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_81 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_81 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_81 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_82 - Client Programming register for client 82.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_82 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_82 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_82 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_82 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_82 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_83 - Client Programming register for client 83.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_83 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_83 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_83 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_83 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_83 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_84 - Client Programming register for client 84.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_84 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_84 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_84 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_84 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_84 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_85 - Client Programming register for client 85.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_85 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_85 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_85 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_85 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_85 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_86 - Client Programming register for client 86.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_86 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_86 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_86 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_86 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_86 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_87 - Client Programming register for client 87.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_87 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_87 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_87 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_87 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_87 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_88 - Client Programming register for client 88.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_88 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_88 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_88 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_88 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_88 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_89 - Client Programming register for client 89.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_89 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_89 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_89 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_89 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_89 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_90 - Client Programming register for client 90.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_90 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_90 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_90 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_90 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_90 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_91 - Client Programming register for client 91.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_91 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_91 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_91 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_91 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_91 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_92 - Client Programming register for client 92.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_92 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_92 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_92 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_92 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_92 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_93 - Client Programming register for client 93.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_93 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_93 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_93 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_93 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_93 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_94 - Client Programming register for client 94.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_94 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_94 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_94 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_94 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_94 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_95 - Client Programming register for client 95.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_95 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_95 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_95 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_95 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_95 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_96 - Client Programming register for client 96.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_96 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_96 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_96 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_96 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_96 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_97 - Client Programming register for client 97.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_97 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_97 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_97 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_97 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_97 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_98 - Client Programming register for client 98.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_98 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_98 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_98 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_98 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_98 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_99 - Client Programming register for client 99.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_99 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_RR_EN_DEFAULT               1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_99 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_99 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_BO_VAL_DEFAULT              0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_99 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_99 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_PR_TAG_DEFAULT              0
+
+/***************************************************************************
+ *CLIENT_INFO_100 - Client Programming register for client 100.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_100 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_100 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_100 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_100 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_100 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_101 - Client Programming register for client 101.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_101 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_101 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_101 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_101 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_101 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_102 - Client Programming register for client 102.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_102 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_102 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_102 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_102 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_102 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_103 - Client Programming register for client 103.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_103 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_103 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_103 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_103 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_103 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_104 - Client Programming register for client 104.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_104 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_104 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_104 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_104 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_104 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_105 - Client Programming register for client 105.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_105 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_105 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_105 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_105 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_105 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_106 - Client Programming register for client 106.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_106 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_106 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_106 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_106 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_106 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_107 - Client Programming register for client 107.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_107 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_107 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_107 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_107 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_107 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_108 - Client Programming register for client 108.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_108 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_108 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_108 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_108 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_108 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_109 - Client Programming register for client 109.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_109 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_109 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_109 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_109 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_109 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_110 - Client Programming register for client 110.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_110 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_110 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_110 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_110 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_110 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_111 - Client Programming register for client 111.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_111 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_111 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_111 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_111 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_111 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_112 - Client Programming register for client 112.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_112 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_112 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_112 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_112 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_112 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_113 - Client Programming register for client 113.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_113 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_113 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_113 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_113 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_113 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_114 - Client Programming register for client 114.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_114 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_114 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_114 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_114 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_114 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_115 - Client Programming register for client 115.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_115 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_115 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_115 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_115 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_115 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_116 - Client Programming register for client 116.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_116 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_116 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_116 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_116 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_116 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_117 - Client Programming register for client 117.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_117 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_117 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_117 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_117 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_117 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_118 - Client Programming register for client 118.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_118 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_118 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_118 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_118 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_118 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_119 - Client Programming register for client 119.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_119 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_119 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_119 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_119 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_119 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_120 - Client Programming register for client 120.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_120 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_120 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_120 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_120 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_120 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_121 - Client Programming register for client 121.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_121 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_121 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_121 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_121 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_121 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_122 - Client Programming register for client 122.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_122 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_122 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_122 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_122 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_122 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_123 - Client Programming register for client 123.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_123 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_123 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_123 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_123 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_123 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_124 - Client Programming register for client 124.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_124 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_124 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_124 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_124 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_124 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_125 - Client Programming register for client 125.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_125 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_125 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_125 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_125 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_125 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_126 - Client Programming register for client 126.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_126 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_RR_EN_DEFAULT              1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_126 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_126 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_BO_VAL_DEFAULT             0
+
+/* MEMC_ARB_1 :: CLIENT_INFO_126 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_126 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *CLIENT_INFO_127 - Client Programming register for client 127
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_127 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_RR_EN_DEFAULT              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_127 :: reserved0 [30:30] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_reserved0_MASK             0x40000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_reserved0_SHIFT            30
+
+/* MEMC_ARB_1 :: CLIENT_INFO_127 :: REF_CLUST [29:28] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_REF_CLUST_MASK             0x30000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_REF_CLUST_SHIFT            28
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_REF_CLUST_DEFAULT          0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_REF_CLUST_NO_CLUSTER       0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_REF_CLUST_CLUSTER_TWO      1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_REF_CLUST_CLUSTER_FOUR     2
+
+/* MEMC_ARB_1 :: CLIENT_INFO_127 :: REF_PRD [27:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_REF_PRD_MASK               0x0ffff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_REF_PRD_SHIFT              12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_REF_PRD_DEFAULT            2072
+
+/* MEMC_ARB_1 :: CLIENT_INFO_127 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_127 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_PR_TAG_DEFAULT             0
+
+/***************************************************************************
+ *REQ_MASK_0 - Request Mask register for Clients 0 to 31
+ ***************************************************************************/
+/* MEMC_ARB_1 :: REQ_MASK_0 :: MASK [31:00] */
+#define BCHP_MEMC_ARB_1_REQ_MASK_0_MASK_MASK                       0xffffffff
+#define BCHP_MEMC_ARB_1_REQ_MASK_0_MASK_SHIFT                      0
+#define BCHP_MEMC_ARB_1_REQ_MASK_0_MASK_DEFAULT                    0
+#define BCHP_MEMC_ARB_1_REQ_MASK_0_MASK_UNMASK                     0
+
+/***************************************************************************
+ *REQ_MASK_1 - Request Mask register for Clients 32 to 63
+ ***************************************************************************/
+/* MEMC_ARB_1 :: REQ_MASK_1 :: MASK [31:00] */
+#define BCHP_MEMC_ARB_1_REQ_MASK_1_MASK_MASK                       0xffffffff
+#define BCHP_MEMC_ARB_1_REQ_MASK_1_MASK_SHIFT                      0
+#define BCHP_MEMC_ARB_1_REQ_MASK_1_MASK_DEFAULT                    0
+#define BCHP_MEMC_ARB_1_REQ_MASK_1_MASK_UNMASK                     0
+
+/***************************************************************************
+ *REQ_MASK_2 - Request Mask register for Clients 64 to 95
+ ***************************************************************************/
+/* MEMC_ARB_1 :: REQ_MASK_2 :: MASK [31:00] */
+#define BCHP_MEMC_ARB_1_REQ_MASK_2_MASK_MASK                       0xffffffff
+#define BCHP_MEMC_ARB_1_REQ_MASK_2_MASK_SHIFT                      0
+#define BCHP_MEMC_ARB_1_REQ_MASK_2_MASK_DEFAULT                    0
+#define BCHP_MEMC_ARB_1_REQ_MASK_2_MASK_UNMASK                     0
+
+/***************************************************************************
+ *REQ_MASK_3 - Request Mask register for Clients 96 to 127
+ ***************************************************************************/
+/* MEMC_ARB_1 :: REQ_MASK_3 :: MASK [31:00] */
+#define BCHP_MEMC_ARB_1_REQ_MASK_3_MASK_MASK                       0xffffffff
+#define BCHP_MEMC_ARB_1_REQ_MASK_3_MASK_SHIFT                      0
+#define BCHP_MEMC_ARB_1_REQ_MASK_3_MASK_DEFAULT                    0
+#define BCHP_MEMC_ARB_1_REQ_MASK_3_MASK_UNMASK                     0
+
+/***************************************************************************
+ *ARB_WINNER - SCB-Arbitration Winner.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: ARB_WINNER :: reserved0 [31:07] */
+#define BCHP_MEMC_ARB_1_ARB_WINNER_reserved0_MASK                  0xffffff80
+#define BCHP_MEMC_ARB_1_ARB_WINNER_reserved0_SHIFT                 7
+
+/* MEMC_ARB_1 :: ARB_WINNER :: CLIENT_ID [06:00] */
+#define BCHP_MEMC_ARB_1_ARB_WINNER_CLIENT_ID_MASK                  0x0000007f
+#define BCHP_MEMC_ARB_1_ARB_WINNER_CLIENT_ID_SHIFT                 0
+#define BCHP_MEMC_ARB_1_ARB_WINNER_CLIENT_ID_DEFAULT               0
+
+/***************************************************************************
+ *RTS_ERR_0 - RTS Deadline miss register for Clients 0 to 31
+ ***************************************************************************/
+/* MEMC_ARB_1 :: RTS_ERR_0 :: CLIENT [31:00] */
+#define BCHP_MEMC_ARB_1_RTS_ERR_0_CLIENT_MASK                      0xffffffff
+#define BCHP_MEMC_ARB_1_RTS_ERR_0_CLIENT_SHIFT                     0
+#define BCHP_MEMC_ARB_1_RTS_ERR_0_CLIENT_DEFAULT                   0
+#define BCHP_MEMC_ARB_1_RTS_ERR_0_CLIENT_UNMASK                    0
+
+/***************************************************************************
+ *RTS_ERR_1 - RTS Deadline miss register for Clients 32 to 63
+ ***************************************************************************/
+/* MEMC_ARB_1 :: RTS_ERR_1 :: CLIENT [31:00] */
+#define BCHP_MEMC_ARB_1_RTS_ERR_1_CLIENT_MASK                      0xffffffff
+#define BCHP_MEMC_ARB_1_RTS_ERR_1_CLIENT_SHIFT                     0
+#define BCHP_MEMC_ARB_1_RTS_ERR_1_CLIENT_DEFAULT                   0
+#define BCHP_MEMC_ARB_1_RTS_ERR_1_CLIENT_UNMASK                    0
+
+/***************************************************************************
+ *RTS_ERR_2 - RTS Deadline miss register for Clients 64 to 95
+ ***************************************************************************/
+/* MEMC_ARB_1 :: RTS_ERR_2 :: CLIENT [31:00] */
+#define BCHP_MEMC_ARB_1_RTS_ERR_2_CLIENT_MASK                      0xffffffff
+#define BCHP_MEMC_ARB_1_RTS_ERR_2_CLIENT_SHIFT                     0
+#define BCHP_MEMC_ARB_1_RTS_ERR_2_CLIENT_DEFAULT                   0
+#define BCHP_MEMC_ARB_1_RTS_ERR_2_CLIENT_UNMASK                    0
+
+/***************************************************************************
+ *RTS_ERR_3 - RTS Deadline miss register for Clients 96 to 127
+ ***************************************************************************/
+/* MEMC_ARB_1 :: RTS_ERR_3 :: CLIENT [31:00] */
+#define BCHP_MEMC_ARB_1_RTS_ERR_3_CLIENT_MASK                      0xffffffff
+#define BCHP_MEMC_ARB_1_RTS_ERR_3_CLIENT_SHIFT                     0
+#define BCHP_MEMC_ARB_1_RTS_ERR_3_CLIENT_DEFAULT                   0
+#define BCHP_MEMC_ARB_1_RTS_ERR_3_CLIENT_UNMASK                    0
+
+/***************************************************************************
+ *FULLNESS_THRESHOLD - Arbiter fullness threshold register
+ ***************************************************************************/
+/* MEMC_ARB_1 :: FULLNESS_THRESHOLD :: reserved0 [31:06] */
+#define BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD_reserved0_MASK          0xffffffc0
+#define BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD_reserved0_SHIFT         6
+
+/* MEMC_ARB_1 :: FULLNESS_THRESHOLD :: FULLNESS_THRESHOLD_VALUE [05:00] */
+#define BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD_FULLNESS_THRESHOLD_VALUE_MASK 0x0000003f
+#define BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD_FULLNESS_THRESHOLD_VALUE_SHIFT 0
+#define BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD_FULLNESS_THRESHOLD_VALUE_DEFAULT 5
+
+/***************************************************************************
+ *MINIMUM_COMMAND_SIZE - Minimum command size register
+ ***************************************************************************/
+/* MEMC_ARB_1 :: MINIMUM_COMMAND_SIZE :: reserved0 [31:22] */
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_reserved0_MASK        0xffc00000
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_reserved0_SHIFT       22
+
+/* MEMC_ARB_1 :: MINIMUM_COMMAND_SIZE :: MINIMUM_LMB_COMMAND_SIZE [21:16] */
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_LMB_COMMAND_SIZE_MASK 0x003f0000
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_LMB_COMMAND_SIZE_SHIFT 16
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_LMB_COMMAND_SIZE_DEFAULT 3
+
+/* MEMC_ARB_1 :: MINIMUM_COMMAND_SIZE :: reserved1 [15:14] */
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_reserved1_MASK        0x0000c000
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_reserved1_SHIFT       14
+
+/* MEMC_ARB_1 :: MINIMUM_COMMAND_SIZE :: MINIMUM_PFRI_COMMAND_SIZE [13:08] */
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_PFRI_COMMAND_SIZE_MASK 0x00003f00
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_PFRI_COMMAND_SIZE_SHIFT 8
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_PFRI_COMMAND_SIZE_DEFAULT 3
+
+/* MEMC_ARB_1 :: MINIMUM_COMMAND_SIZE :: reserved2 [07:06] */
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_reserved2_MASK        0x000000c0
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_reserved2_SHIFT       6
+
+/* MEMC_ARB_1 :: MINIMUM_COMMAND_SIZE :: MINIMUM_SCB_COMMAND_SIZE [05:00] */
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_SCB_COMMAND_SIZE_MASK 0x0000003f
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_SCB_COMMAND_SIZE_SHIFT 0
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_SCB_COMMAND_SIZE_DEFAULT 3
+
+/***************************************************************************
+ *RTS_ERR_INFO_WRITE_CLEAR - MEMC RTS_ERR_INFO write clear register
+ ***************************************************************************/
+/* MEMC_ARB_1 :: RTS_ERR_INFO_WRITE_CLEAR :: reserved0 [31:01] */
+#define BCHP_MEMC_ARB_1_RTS_ERR_INFO_WRITE_CLEAR_reserved0_MASK    0xfffffffe
+#define BCHP_MEMC_ARB_1_RTS_ERR_INFO_WRITE_CLEAR_reserved0_SHIFT   1
+
+/* MEMC_ARB_1 :: RTS_ERR_INFO_WRITE_CLEAR :: WRITE_CLEAR [00:00] */
+#define BCHP_MEMC_ARB_1_RTS_ERR_INFO_WRITE_CLEAR_WRITE_CLEAR_MASK  0x00000001
+#define BCHP_MEMC_ARB_1_RTS_ERR_INFO_WRITE_CLEAR_WRITE_CLEAR_SHIFT 0
+#define BCHP_MEMC_ARB_1_RTS_ERR_INFO_WRITE_CLEAR_WRITE_CLEAR_DEFAULT 0
+
+/***************************************************************************
+ *SCB_ARBITER_DEBUG_REGISTER - MEMC SCB Interface and Arbiter State Machine and FIFO Debug Register
+ ***************************************************************************/
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: reserved0 [31:30] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved0_MASK  0xc0000000
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved0_SHIFT 30
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_RD_STATE [29:28] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_RD_STATE_MASK 0x30000000
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_RD_STATE_SHIFT 28
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: reserved1 [27:26] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved1_MASK  0x0c000000
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved1_SHIFT 26
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SS_WR_STRB_STATE [25:24] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SS_WR_STRB_STATE_MASK 0x03000000
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SS_WR_STRB_STATE_SHIFT 24
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: reserved2 [23:21] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved2_MASK  0x00e00000
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved2_SHIFT 21
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_LAST_WRITE_STATE [20:20] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_LAST_WRITE_STATE_MASK 0x00100000
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_LAST_WRITE_STATE_SHIFT 20
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: reserved3 [19:17] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved3_MASK  0x000e0000
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved3_SHIFT 17
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_WR_NATIVE_WORD_STATE [16:16] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_NATIVE_WORD_STATE_MASK 0x00010000
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_NATIVE_WORD_STATE_SHIFT 16
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: reserved4 [15:14] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved4_MASK  0x0000c000
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved4_SHIFT 14
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_WR_DATA_FIFO_FULL [13:13] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_DATA_FIFO_FULL_MASK 0x00002000
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_DATA_FIFO_FULL_SHIFT 13
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_WR_DATA_FIFO_EMPTY [12:12] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_DATA_FIFO_EMPTY_MASK 0x00001000
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_DATA_FIFO_EMPTY_SHIFT 12
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_WR_MASK_FIFO_FULL [11:11] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_MASK_FIFO_FULL_MASK 0x00000800
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_MASK_FIFO_FULL_SHIFT 11
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_WR_MASK_FIFO_EMPTY [10:10] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_MASK_FIFO_EMPTY_MASK 0x00000400
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_MASK_FIFO_EMPTY_SHIFT 10
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_CMD_FIFO_FULL [09:09] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_CMD_FIFO_FULL_MASK 0x00000200
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_CMD_FIFO_FULL_SHIFT 9
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_CMD_FIFO_EMPTY [08:08] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_CMD_FIFO_EMPTY_MASK 0x00000100
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_CMD_FIFO_EMPTY_SHIFT 8
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: reserved5 [07:03] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved5_MASK  0x000000f8
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved5_SHIFT 3
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: ARB_STATE [02:00] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_ARB_STATE_MASK  0x00000007
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_ARB_STATE_SHIFT 0
+
+/***************************************************************************
+ *SPARE_1 - Spare Register 1 .
+ ***************************************************************************/
+/* MEMC_ARB_1 :: SPARE_1 :: SPARE [31:03] */
+#define BCHP_MEMC_ARB_1_SPARE_1_SPARE_MASK                         0xfffffff8
+#define BCHP_MEMC_ARB_1_SPARE_1_SPARE_SHIFT                        3
+#define BCHP_MEMC_ARB_1_SPARE_1_SPARE_DEFAULT                      0
+
+/* MEMC_ARB_1 :: SPARE_1 :: LMB_PREA_FIX_ENABLE [02:02] */
+#define BCHP_MEMC_ARB_1_SPARE_1_LMB_PREA_FIX_ENABLE_MASK           0x00000004
+#define BCHP_MEMC_ARB_1_SPARE_1_LMB_PREA_FIX_ENABLE_SHIFT          2
+#define BCHP_MEMC_ARB_1_SPARE_1_LMB_PREA_FIX_ENABLE_DEFAULT        1
+
+/* MEMC_ARB_1 :: SPARE_1 :: FULLNESS_UPDATE_FIX_DISABLE [01:00] */
+#define BCHP_MEMC_ARB_1_SPARE_1_FULLNESS_UPDATE_FIX_DISABLE_MASK   0x00000003
+#define BCHP_MEMC_ARB_1_SPARE_1_FULLNESS_UPDATE_FIX_DISABLE_SHIFT  0
+#define BCHP_MEMC_ARB_1_SPARE_1_FULLNESS_UPDATE_FIX_DISABLE_DEFAULT 0
+
+/***************************************************************************
+ *SPARE_2 - Spare Register 2 .
+ ***************************************************************************/
+/* MEMC_ARB_1 :: SPARE_2 :: SPARE [31:03] */
+#define BCHP_MEMC_ARB_1_SPARE_2_SPARE_MASK                         0xfffffff8
+#define BCHP_MEMC_ARB_1_SPARE_2_SPARE_SHIFT                        3
+#define BCHP_MEMC_ARB_1_SPARE_2_SPARE_DEFAULT                      0
+
+/* MEMC_ARB_1 :: SPARE_2 :: LMB_PREA_FIX_ENABLE [02:02] */
+#define BCHP_MEMC_ARB_1_SPARE_2_LMB_PREA_FIX_ENABLE_MASK           0x00000004
+#define BCHP_MEMC_ARB_1_SPARE_2_LMB_PREA_FIX_ENABLE_SHIFT          2
+#define BCHP_MEMC_ARB_1_SPARE_2_LMB_PREA_FIX_ENABLE_DEFAULT        1
+
+/* MEMC_ARB_1 :: SPARE_2 :: FULLNESS_UPDATE_FIX_DISABLE [01:00] */
+#define BCHP_MEMC_ARB_1_SPARE_2_FULLNESS_UPDATE_FIX_DISABLE_MASK   0x00000003
+#define BCHP_MEMC_ARB_1_SPARE_2_FULLNESS_UPDATE_FIX_DISABLE_SHIFT  0
+#define BCHP_MEMC_ARB_1_SPARE_2_FULLNESS_UPDATE_FIX_DISABLE_DEFAULT 0
+
+/***************************************************************************
+ *SPARE_RO_1 - Read only Spare Register 1 .
+ ***************************************************************************/
+/* MEMC_ARB_1 :: SPARE_RO_1 :: SPARE_RO [31:00] */
+#define BCHP_MEMC_ARB_1_SPARE_RO_1_SPARE_RO_MASK                   0xffffffff
+#define BCHP_MEMC_ARB_1_SPARE_RO_1_SPARE_RO_SHIFT                  0
+#define BCHP_MEMC_ARB_1_SPARE_RO_1_SPARE_RO_DEFAULT                0
+
+/***************************************************************************
+ *SPARE_RO_2 - Read only Spare Register 2 .
+ ***************************************************************************/
+/* MEMC_ARB_1 :: SPARE_RO_2 :: SPARE_RO [31:00] */
+#define BCHP_MEMC_ARB_1_SPARE_RO_2_SPARE_RO_MASK                   0xffffffff
+#define BCHP_MEMC_ARB_1_SPARE_RO_2_SPARE_RO_SHIFT                  0
+#define BCHP_MEMC_ARB_1_SPARE_RO_2_SPARE_RO_DEFAULT                0
+
+#endif /* #ifndef BCHP_MEMC_ARB_1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_memc_ddr23_shim_addr_cntl_0.h b/include/linux/brcmstb/7425b0/bchp_memc_ddr23_shim_addr_cntl_0.h
new file mode 100644
index 0000000..d5015f1
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_memc_ddr23_shim_addr_cntl_0.h
@@ -0,0 +1,1075 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:42 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_H__
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_H__
+
+/***************************************************************************
+ *MEMC_DDR23_SHIM_ADDR_CNTL_0 - DDR23 SHIM Control Registers 0
+ ***************************************************************************/
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG  0x003b8000 /* DDR23_SHIM Config register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID 0x003b8004 /* DDR23_SHIM Revision ID Register. */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET   0x003b8008 /* DDR soft reset register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG 0x003b8038 /* ODT Configuration register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL 0x003b8044 /* DDR PHY USE DYN VDL Control register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING 0x003b8048 /* DDR PHY Idle power saving Control register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT 0x003b804c /* DDR PHY standby exit register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL 0x003b806c /* Analog macro register bypass control */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL 0x003b8070 /* DDR PLL external clock select register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_TEST_MODE_CNTRL_REG 0x003b8074 /* DDR23_SHIM testport control register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL 0x003b807c /* DDR bypass pll mode disable register. */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL 0x003b8088 /* DDR VECTOR PLL bypass mode clock select */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL 0x003b808c /* DDR Pad control register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE 0x003b8098 /* CLK_667_ENABLE Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS 0x003b809c /* DDR23_SHIM Status Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO 0x003b8028 /* Command and Data FIFO Status Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH 0x003b802c /* Read Datapath Status Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_FLAG_BUS 0x003b8030 /* TP_OUT bus value Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC    0x003b8034 /* Miscellaneous Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RW 0x003b80a4 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RW 0x003b80a8 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RO 0x003b80ac /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RO 0x003b80b0 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL 0x003b80b4 /* FORCE_DDR3_RESET Deassert  Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS 0x003b80b8 /* SYS PLL P and N Divider Controls */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN 0x003b80bc /* SYS PLL Gain Controls */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL 0x003b80c0 /* SYS PLL Control Vector */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP 0x003b80c4 /* SSC Step Size for all 6-chan PLLs */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT 0x003b80c8 /* SSC Limit for all 6-chan PLLs */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0 0x003b80cc /* SYS PLL M Divider Controls for Channel0 */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX 0x003b80d0 /* SYS PLL M Divider Controls for Extra Unused Channels */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT 0x003b80d4 /* SYS PLL Status */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel 0x003b80d8 /* SYS PLL power-down and reference clock selection */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET 0x003b80dc /* SYS PLL Reset and post-resetb selcection */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR 0x003b80e0 /* SYS PLL control and SR selcection */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK 0x003b80e4 /* Shim to PHY gated bypass_clock selection */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG0 0x003b80e8 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG1 0x003b80ec /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG2 0x003b80f0 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG3 0x003b80f4 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG4 0x003b80f8 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG5 0x003b80fc /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG6 0x003b8100 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG7 0x003b8104 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG8 0x003b8108 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG9 0x003b810c /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG10 0x003b8110 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG11 0x003b8114 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG12 0x003b8118 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG13 0x003b811c /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG14 0x003b8120 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG15 0x003b8124 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY 0x003b8128 /* Delay on phy_dyn_vdl to the PHY */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_0 0x003b812c /* DDR PHY data storage register 0 */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_1 0x003b8130 /* DDR PHY data storage register 0 */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_2 0x003b8134 /* DDR PHY data storage register 0 */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_3 0x003b8138 /* DDR PHY data storage register 0 */
+
+/***************************************************************************
+ *CONFIG - DDR23_SHIM Config register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: reserved0 [31:27] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_reserved0_MASK     0xf8000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_reserved0_SHIFT    27
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: LAST_RD_STRETCH [26:26] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_RD_STRETCH_MASK 0x04000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_RD_STRETCH_SHIFT 26
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_RD_STRETCH_DEFAULT 0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: ODT_LATENCY [25:21] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_ODT_LATENCY_MASK   0x03e00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_ODT_LATENCY_SHIFT  21
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_ODT_LATENCY_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: LAST_READ_LATENCY [20:15] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_READ_LATENCY_MASK 0x001f8000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_READ_LATENCY_SHIFT 15
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_READ_LATENCY_DEFAULT 0x0000000b
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: READ_LATENCY [14:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_READ_LATENCY_MASK  0x00007f00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_READ_LATENCY_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_READ_LATENCY_DEFAULT 0x00000007
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: WRITE_LATENCY [07:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_WRITE_LATENCY_MASK 0x000000f8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_WRITE_LATENCY_SHIFT 3
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_WRITE_LATENCY_DEFAULT 0x0000000e
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: DRAM_WIDTH [02:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DRAM_WIDTH_MASK    0x00000006
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DRAM_WIDTH_SHIFT   1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DRAM_WIDTH_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: DDR_MODE [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DDR_MODE_MASK      0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DDR_MODE_SHIFT     0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DDR_MODE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *DDR23_SHIM_REV_ID - DDR23_SHIM Revision ID Register.
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_REV_ID :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_reserved0_MASK 0xffff0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_reserved0_SHIFT 16
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_REV_ID :: MAJOR_ID [15:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MAJOR_ID_MASK 0x0000ff00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MAJOR_ID_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MAJOR_ID_DEFAULT 0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_REV_ID :: MINOR_ID [07:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MINOR_ID_MASK 0x000000ff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MINOR_ID_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MINOR_ID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET - DDR soft reset register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RESET :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_reserved0_MASK      0xfffffff8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_reserved0_SHIFT     3
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RESET :: DATAPATH_216_RESET [02:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_216_RESET_MASK 0x00000004
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_216_RESET_SHIFT 2
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_216_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RESET :: DATAPATH_DDR_RESET [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_DDR_RESET_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_DDR_RESET_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_DDR_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RESET :: PHY_PWRUP_RSB [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_PHY_PWRUP_RSB_MASK  0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_PHY_PWRUP_RSB_SHIFT 0
+
+/***************************************************************************
+ *ODT_CONFIG - ODT Configuration register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_reserved0_MASK 0xffff0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_reserved0_SHIFT 16
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: ODT_TIE_HIGH [15:15] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_TIE_HIGH_MASK 0x00008000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_TIE_HIGH_SHIFT 15
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_TIE_HIGH_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: ODT_ENABLE [14:14] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_ENABLE_MASK 0x00004000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_ENABLE_SHIFT 14
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_ENABLE_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: STRETCH [13:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_STRETCH_MASK   0x00003800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_STRETCH_SHIFT  11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_STRETCH_DEFAULT 0x00000003
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: EARLY [10:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_EARLY_MASK     0x000007c0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_EARLY_SHIFT    6
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_EARLY_DEFAULT  0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: DELAY [05:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_DELAY_MASK     0x0000003f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_DELAY_SHIFT    0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_DELAY_DEFAULT  0x00000002
+
+/***************************************************************************
+ *PHY_USE_DYN_VDL - DDR PHY USE DYN VDL Control register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_USE_DYN_VDL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_USE_DYN_VDL :: DISABLE [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL_DISABLE_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL_DISABLE_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL_DISABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_POWER_SAVING - DDR PHY Idle power saving Control register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: reserved0 [31:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_reserved0_MASK 0xffffffc0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_reserved0_SHIFT 6
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: PhyAddrCntl [05:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_PhyAddrCntl_MASK 0x00000030
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_PhyAddrCntl_SHIFT 4
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_PhyAddrCntl_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane3 [03:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane3_MASK 0x00000008
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane3_SHIFT 3
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane3_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane2 [02:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane2_MASK 0x00000004
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane2_SHIFT 2
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane2_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane1 [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane1_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane1_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane1_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane0 [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane0_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHY_STANDBY_EXIT - DDR PHY standby exit register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_STANDBY_EXIT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_STANDBY_EXIT :: ENABLE [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT_ENABLE_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT_ENABLE_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *ANALOG_BYPASS_CNTRL - Analog macro register bypass control
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ANALOG_BYPASS_CNTRL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ANALOG_BYPASS_CNTRL :: BYPASS_PLL [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_BYPASS_PLL_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_BYPASS_PLL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_BYPASS_PLL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DDR_PLL_EXT_CLKSEL - DDR PLL external clock select register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PLL_EXT_CLKSEL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PLL_EXT_CLKSEL :: EXT_CLK_SEL [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TEST_MODE_CNTRL_REG - DDR23_SHIM testport control register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: TEST_MODE_CNTRL_REG :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_TEST_MODE_CNTRL_REG_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_TEST_MODE_CNTRL_REG_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_TEST_MODE_CNTRL_REG_reserved_for_eco0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DISABLE_CHIP_BYPASS_PLL - DDR bypass pll mode disable register.
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DISABLE_CHIP_BYPASS_PLL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DISABLE_CHIP_BYPASS_PLL :: DISABLE_BYPASS_PLL [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VECTOR_MODE_CLK_SEL - DDR VECTOR PLL bypass mode clock select
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: VECTOR_MODE_CLK_SEL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: VECTOR_MODE_CLK_SEL :: SEL [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_SEL_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_SEL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DDR_PAD_CNTRL - DDR Pad control register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_reserved0_MASK 0xffffff80
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_reserved0_SHIFT 7
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: IDDQ_MODE_ON_SELFREF [06:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK 0x00000040
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_SHIFT 6
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: PHY_IDLE_ENABLE [05:05] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_MASK 0x00000020
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_SHIFT 5
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: HIZ_ON_SELFREF [04:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_HIZ_ON_SELFREF_MASK 0x00000010
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_HIZ_ON_SELFREF_SHIFT 4
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_HIZ_ON_SELFREF_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: CNTRL [03:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_CNTRL_MASK  0x0000000f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_CNTRL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_CNTRL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CLK_GATE - CLK_667_ENABLE Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CLK_GATE :: UNUSED [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_UNUSED_MASK      0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_UNUSED_SHIFT     1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_UNUSED_DEFAULT   0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CLK_GATE :: CLK_667_ENABLE [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_CLK_667_ENABLE_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_CLK_667_ENABLE_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_CLK_667_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DDR23_SHIM_STATUS - DDR23_SHIM Status Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_STATUS :: reserved0 [31:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_reserved0_SHIFT 4
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_STATUS :: BL0_AND_BL1_RDY_SLIP [03:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL0_AND_BL1_RDY_SLIP_MASK 0x00000008
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL0_AND_BL1_RDY_SLIP_SHIFT 3
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_STATUS :: BL0_RDY_SLIP [02:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL0_RDY_SLIP_MASK 0x00000004
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL0_RDY_SLIP_SHIFT 2
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_STATUS :: BL1_RDY_SLIP [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL1_RDY_SLIP_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL1_RDY_SLIP_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_STATUS :: READY [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_READY_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_READY_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_READY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CMD_DATA_FIFO - Command and Data FIFO Status Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: reserved0 [31:26] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_reserved0_MASK 0xfc000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_reserved0_SHIFT 26
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: FIFO_FULL [25:25] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_FULL_MASK 0x02000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_FULL_SHIFT 25
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: FIFO_EMPTY [24:24] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_EMPTY_MASK 0x01000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_EMPTY_SHIFT 24
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: reserved1 [23:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_reserved1_MASK 0x00ffff00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_reserved1_SHIFT 8
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: WR_PNTR [07:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_WR_PNTR_MASK 0x000000f0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_WR_PNTR_SHIFT 4
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: RD_PNTR [03:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_RD_PNTR_MASK 0x0000000f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_RD_PNTR_SHIFT 0
+
+/***************************************************************************
+ *RD_DATAPATH - Read Datapath Status Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: reserved0 [31:28] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_reserved0_MASK 0xf0000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_reserved0_SHIFT 28
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: F_RDY_3 [27:27] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_3_MASK  0x08000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_3_SHIFT 27
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: F_RDY_2 [26:26] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_2_MASK  0x04000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_2_SHIFT 26
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: F_RDY_1 [25:25] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_1_MASK  0x02000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_1_SHIFT 25
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: F_RDY_0 [24:24] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_0_MASK  0x01000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_0_SHIFT 24
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: DWORD3_CNT [23:20] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD3_CNT_MASK 0x00f00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD3_CNT_SHIFT 20
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: DWORD2_CNT [19:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD2_CNT_MASK 0x000f0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD2_CNT_SHIFT 16
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: DWORD1_CNT [15:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD1_CNT_MASK 0x0000f000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD1_CNT_SHIFT 12
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: DWORD0_CNT [11:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD0_CNT_MASK 0x00000f00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD0_CNT_SHIFT 8
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: WR_PNTR [07:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_WR_PNTR_MASK  0x000000f0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_WR_PNTR_SHIFT 4
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: RD_PNTR [03:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_RD_PNTR_MASK  0x0000000f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_RD_PNTR_SHIFT 0
+
+/***************************************************************************
+ *FLAG_BUS - TP_OUT bus value Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: FLAG_BUS :: FLAG_BUS [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_FLAG_BUS_FLAG_BUS_MASK    0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_FLAG_BUS_FLAG_BUS_SHIFT   0
+
+/***************************************************************************
+ *MISC - Miscellaneous Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: reserved_for_eco0 [31:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_reserved_for_eco0_MASK 0xfffff000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_reserved_for_eco0_SHIFT 12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_reserved_for_eco0_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: BL0_AND_BL1_RDY_SLIP_CLR [11:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_AND_BL1_RDY_SLIP_CLR_MASK 0x00000800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_AND_BL1_RDY_SLIP_CLR_SHIFT 11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_AND_BL1_RDY_SLIP_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: BL0_RDY_SLIP_CLR [10:10] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_RDY_SLIP_CLR_MASK 0x00000400
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_RDY_SLIP_CLR_SHIFT 10
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_RDY_SLIP_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: BL1_RDY_SLIP_CLR [09:09] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL1_RDY_SLIP_CLR_MASK 0x00000200
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL1_RDY_SLIP_CLR_SHIFT 9
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL1_RDY_SLIP_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: FUNC1 [08:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC1_MASK           0x00000100
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC1_SHIFT          8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC1_DEFAULT        0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: FUNC0 [07:07] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC0_MASK           0x00000080
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC0_SHIFT          7
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC0_DEFAULT        0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: C2IO_INIT_RDY_OVR [06:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_C2IO_INIT_RDY_OVR_MASK 0x00000040
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_C2IO_INIT_RDY_OVR_SHIFT 6
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_C2IO_INIT_RDY_OVR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: RD_FIFO_HOLD_CLR [05:05] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_RD_FIFO_HOLD_CLR_MASK 0x00000020
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_RD_FIFO_HOLD_CLR_SHIFT 5
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_RD_FIFO_HOLD_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: CMD_FIFO_HOLD_CLR [04:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_CMD_FIFO_HOLD_CLR_MASK 0x00000010
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_CMD_FIFO_HOLD_CLR_SHIFT 4
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_CMD_FIFO_HOLD_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: DWORD3_OVERRUN_CLR [03:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD3_OVERRUN_CLR_MASK 0x00000008
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD3_OVERRUN_CLR_SHIFT 3
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD3_OVERRUN_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: DWORD2_OVERRUN_CLR [02:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD2_OVERRUN_CLR_MASK 0x00000004
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD2_OVERRUN_CLR_SHIFT 2
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD2_OVERRUN_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: DWORD1_OVERRUN_CLR [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD1_OVERRUN_CLR_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD1_OVERRUN_CLR_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD1_OVERRUN_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: DWORD0_OVERRUN_CLR [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD0_OVERRUN_CLR_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD0_OVERRUN_CLR_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD0_OVERRUN_CLR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE0_RW - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SPARE0_RW :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RW_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RW_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RW_reserved_for_eco0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE1_RW - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SPARE1_RW :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RW_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RW_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RW_reserved_for_eco0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE0_RO - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SPARE0_RO :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RO_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RO_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RO_reserved_for_eco0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE1_RO - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SPARE1_RO :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RO_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RO_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RO_reserved_for_eco0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DDR3_RESET_CNTRL - FORCE_DDR3_RESET Deassert  Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR3_RESET_CNTRL :: UNUSED [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_UNUSED_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_UNUSED_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_UNUSED_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR3_RESET_CNTRL :: FORCE_DDR3_RESET [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PLL6CH_PNDIV_SYS - SYS PLL P and N Divider Controls
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PLL6CH_PNDIV_SYS :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_reserved0_MASK 0x80000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_reserved0_SHIFT 31
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PLL6CH_PNDIV_SYS :: PDIV [30:28] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_PDIV_MASK 0x70000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_PDIV_SHIFT 28
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_PDIV_DEFAULT 0x00000002
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PLL6CH_PNDIV_SYS :: NDIV_INT [27:20] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_INT_MASK 0x0ff00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_INT_SHIFT 20
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_INT_DEFAULT 0x0000004e
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PLL6CH_PNDIV_SYS :: NDIV_FRAC [19:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_FRAC_MASK 0x000fffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_FRAC_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_FRAC_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_PLL_GAIN - SYS PLL Gain Controls
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: reserved0 [31:23] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_reserved0_MASK 0xff800000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_reserved0_SHIFT 23
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: FB_PHASE_ENA [22:22] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_ENA_MASK 0x00400000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_ENA_SHIFT 22
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_ENA_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: FB_PHASE_OFFSET [21:10] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_OFFSET_MASK 0x003ffc00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_OFFSET_SHIFT 10
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_OFFSET_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: KP [09:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KP_MASK      0x000003c0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KP_SHIFT     6
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KP_DEFAULT   0x00000008
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: KI [05:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KI_MASK      0x00000038
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KI_SHIFT     3
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KI_DEFAULT   0x00000003
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: KA [02:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KA_MASK      0x00000007
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KA_SHIFT     0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KA_DEFAULT   0x00000001
+
+/***************************************************************************
+ *SYS_PLL_CTRL - SYS PLL Control Vector
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: reserved0 [31:23] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_reserved0_MASK 0xff800000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_reserved0_SHIFT 23
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: ENA_8PHASE [22:22] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_8PHASE_MASK 0x00400000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_8PHASE_SHIFT 22
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_8PHASE_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: ENA_SSC [21:21] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_SSC_MASK 0x00200000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_SSC_SHIFT 21
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_SSC_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: VCO_DIV2_EN [20:20] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_VCO_DIV2_EN_MASK 0x00100000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_VCO_DIV2_EN_SHIFT 20
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_VCO_DIV2_EN_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: AUX_CTRL [19:19] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_AUX_CTRL_MASK 0x00080000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_AUX_CTRL_SHIFT 19
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_AUX_CTRL_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: REFCLK_OUT [18:18] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_REFCLK_OUT_MASK 0x00040000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_REFCLK_OUT_SHIFT 18
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_REFCLK_OUT_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: STAT_UPDATE [17:17] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_UPDATE_MASK 0x00020000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_UPDATE_SHIFT 17
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_UPDATE_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: STAT_SELECT [16:14] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_SELECT_MASK 0x0001c000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_SELECT_SHIFT 14
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_SELECT_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: STAT_RESET [13:13] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_RESET_MASK 0x00002000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_RESET_SHIFT 13
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: DCO_CTRL_BYPASS_ENA [12:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_ENA_MASK 0x00001000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_ENA_SHIFT 12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_ENA_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_MASK 0x00000fff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SSC_STEP - SSC Step Size for all 6-chan PLLs
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SSC_STEP :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP_reserved0_MASK   0xffff0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP_reserved0_SHIFT  16
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SSC_STEP :: SSC_STEP [15:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP_SSC_STEP_MASK    0x0000ffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP_SSC_STEP_SHIFT   0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SSC_LIMIT - SSC Limit for all 6-chan PLLs
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SSC_LIMIT :: reserved0 [31:22] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT_reserved0_MASK  0xffc00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT_reserved0_SHIFT 22
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SSC_LIMIT :: SSC_LIMIT [21:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT_SSC_LIMIT_MASK  0x003fffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT_SSC_LIMIT_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_PLL_MDIV0 - SYS PLL M Divider Controls for Channel0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: reserved0 [31:14] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_reserved0_MASK 0xffffc000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_reserved0_SHIFT 14
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: CHAN_HOLD_OUTPUT [13:13] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_HOLD_OUTPUT_MASK 0x00002000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_HOLD_OUTPUT_SHIFT 13
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_HOLD_OUTPUT_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: CHAN_LOAD_MDIV [12:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_LOAD_MDIV_MASK 0x00001000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_LOAD_MDIV_SHIFT 12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_LOAD_MDIV_DEFAULT 0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: CHAN_ENA [11:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_ENA_MASK 0x00000800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_ENA_SHIFT 11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_ENA_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: CHAN_MDEL [10:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDEL_MASK 0x00000700
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDEL_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDEL_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: CHAN_MDIV [07:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDIV_MASK 0x000000ff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDIV_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDIV_DEFAULT 0x00000008
+
+/***************************************************************************
+ *SYS_PLL_MDIVX - SYS PLL M Divider Controls for Extra Unused Channels
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: reserved0 [31:14] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_reserved0_MASK 0xffffc000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_reserved0_SHIFT 14
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: CHAN_HOLD_OUTPUT [13:13] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_HOLD_OUTPUT_MASK 0x00002000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_HOLD_OUTPUT_SHIFT 13
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_HOLD_OUTPUT_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: CHAN_LOAD_MDIV [12:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_LOAD_MDIV_MASK 0x00001000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_LOAD_MDIV_SHIFT 12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_LOAD_MDIV_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: CHAN_ENA [11:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_ENA_MASK 0x00000800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_ENA_SHIFT 11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_ENA_DEFAULT 0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: CHAN_MDEL [10:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDEL_MASK 0x00000700
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDEL_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDEL_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: CHAN_MDIV [07:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDIV_MASK 0x000000ff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDIV_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDIV_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_PLL_STAT - SYS PLL Status
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_STAT :: reserved0 [31:25] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_reserved0_MASK 0xfe000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_reserved0_SHIFT 25
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_STAT :: DEBUG_OUTPUT [24:13] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_DEBUG_OUTPUT_MASK 0x01ffe000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_DEBUG_OUTPUT_SHIFT 13
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_DEBUG_OUTPUT_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_STAT :: LOCK [12:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_LOCK_MASK    0x00001000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_LOCK_SHIFT   12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_LOCK_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_STAT :: UNLOCK_COUNT [11:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_UNLOCK_COUNT_MASK 0x00000fff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_UNLOCK_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_UNLOCK_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_PLL_PWRDN_ref_clk_sel - SYS PLL power-down and reference clock selection
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_PWRDN_ref_clk_sel :: reserved0 [31:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_reserved0_MASK 0xfffffffc
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_reserved0_SHIFT 2
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_PWRDN_ref_clk_sel :: REFCLK_SEL [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_REFCLK_SEL_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_REFCLK_SEL_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_REFCLK_SEL_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_PWRDN_ref_clk_sel :: PWRDN [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_PWRDN_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_PWRDN_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_PWRDN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_PLL_RESET_POST_RESET - SYS PLL Reset and post-resetb selcection
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_RESET_POST_RESET :: reserved0 [31:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_reserved0_MASK 0xfffffffc
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_reserved0_SHIFT 2
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_RESET_POST_RESET :: POST_RESETB [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_POST_RESETB_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_POST_RESETB_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_POST_RESETB_DEFAULT 0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_RESET_POST_RESET :: GLOBAL_RESETB [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_GLOBAL_RESETB_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_GLOBAL_RESETB_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_GLOBAL_RESETB_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SYS_PLL_CTRL_SR - SYS PLL control and SR selcection
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL_SR :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_reserved0_MASK 0xe0000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_reserved0_SHIFT 29
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL_SR :: PLL_SR [28:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_SR_MASK 0x1ffff800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_SR_SHIFT 11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_SR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL_SR :: PLL_CTRL_1 [10:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_CTRL_1_MASK 0x000007fc
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_CTRL_1_SHIFT 2
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_CTRL_1_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL_SR :: NDIV_INT_1 [01:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_NDIV_INT_1_MASK 0x00000003
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_NDIV_INT_1_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_NDIV_INT_1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SHIM_TO_PHY_GATED_BYPASS_CLK - Shim to PHY gated bypass_clock selection
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SHIM_TO_PHY_GATED_BYPASS_CLK :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SHIM_TO_PHY_GATED_BYPASS_CLK :: BYPASS_CLK_GATED_TO_SHIM_PHY [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK_BYPASS_CLK_GATED_TO_SHIM_PHY_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK_BYPASS_CLK_GATED_TO_SHIM_PHY_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK_BYPASS_CLK_GATED_TO_SHIM_PHY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG0 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG0 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG0_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG0_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG0_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG1 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG1 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG1_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG1_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG1_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG2 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG2 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG2_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG2_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG2_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG3 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG3 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG3_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG3_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG3_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG4 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG4 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG4_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG4_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG4_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG5 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG5 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG5_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG5_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG5_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG6 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG6 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG6_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG6_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG6_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG7 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG7 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG7_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG7_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG7_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG8 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG8 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG8_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG8_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG8_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG9 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG9 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG9_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG9_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG9_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG10 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG10 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG10_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG10_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG10_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG11 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG11 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG11_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG11_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG11_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG12 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG12 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG12_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG12_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG12_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG13 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG13 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG13_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG13_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG13_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG14 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG14 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG14_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG14_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG14_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG15 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG15 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG15_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG15_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG15_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHY_DYN_VDL_DLY - Delay on phy_dyn_vdl to the PHY
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: reserved0 [31:28] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved0_MASK 0xf0000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved0_SHIFT 28
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: DYN_VDL_DEASSERT_TO_READ_ENB_DLY [27:24] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_READ_ENB_DLY_MASK 0x0f000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_READ_ENB_DLY_SHIFT 24
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_READ_ENB_DLY_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: reserved1 [23:20] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved1_MASK 0x00f00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved1_SHIFT 20
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: DYN_VDL_ASSERT_TO_READ_ENB_DLY [19:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_READ_ENB_DLY_MASK 0x000f0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_READ_ENB_DLY_SHIFT 16
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_READ_ENB_DLY_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: reserved2 [15:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved2_MASK 0x0000f000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved2_SHIFT 12
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: DYN_VDL_DEASSERT_TO_WR_VALID_DLY [11:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_WR_VALID_DLY_MASK 0x00000f00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_WR_VALID_DLY_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_WR_VALID_DLY_DEFAULT 0x00000002
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: reserved3 [07:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved3_MASK 0x000000f0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved3_SHIFT 4
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: DYN_VDL_ASSERT_TO_WR_VALID_DLY [03:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_WR_VALID_DLY_MASK 0x0000000f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_WR_VALID_DLY_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_WR_VALID_DLY_DEFAULT 0x00000002
+
+/***************************************************************************
+ *AON_STORAGE_IN_PHY_0 - DDR PHY data storage register 0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: AON_STORAGE_IN_PHY_0 :: DTATA [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_0_DTATA_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_0_DTATA_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_0_DTATA_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AON_STORAGE_IN_PHY_1 - DDR PHY data storage register 0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: AON_STORAGE_IN_PHY_1 :: DTATA [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_1_DTATA_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_1_DTATA_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_1_DTATA_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AON_STORAGE_IN_PHY_2 - DDR PHY data storage register 0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: AON_STORAGE_IN_PHY_2 :: DTATA [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_2_DTATA_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_2_DTATA_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_2_DTATA_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AON_STORAGE_IN_PHY_3 - DDR PHY data storage register 0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: AON_STORAGE_IN_PHY_3 :: DTATA [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_3_DTATA_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_3_DTATA_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_3_DTATA_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_memc_ddr23_shim_addr_cntl_1.h b/include/linux/brcmstb/7425b0/bchp_memc_ddr23_shim_addr_cntl_1.h
new file mode 100644
index 0000000..b48b704
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_memc_ddr23_shim_addr_cntl_1.h
@@ -0,0 +1,1078 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Jun 13 15:49:22 2011
+ *                 MD5 Checksum         a14f8e7f638a7ebe759043ff756befc5
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7425/rdb/b0/bchp_memc_ddr23_shim_addr_cntl_1.h $
+ * 
+ * Hydra_Software_Devel/3   6/14/11 2:33p vanessah
+ * SW7425-715: 7425 B0 RDB resync
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_H__
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_H__
+
+/***************************************************************************
+ *MEMC_DDR23_SHIM_ADDR_CNTL_1 - DDR23 SHIM Control Registers 1
+ ***************************************************************************/
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG  0x003c8000 /* DDR23_SHIM Config register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_REV_ID 0x003c8004 /* DDR23_SHIM Revision ID Register. */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RESET   0x003c8008 /* DDR soft reset register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG 0x003c8038 /* ODT Configuration register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_USE_DYN_VDL 0x003c8044 /* DDR PHY USE DYN VDL Control register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING 0x003c8048 /* DDR PHY Idle power saving Control register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_STANDBY_EXIT 0x003c804c /* DDR PHY standby exit register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ANALOG_BYPASS_CNTRL 0x003c806c /* Analog macro register bypass control */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PLL_EXT_CLKSEL 0x003c8070 /* DDR PLL external clock select register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_TEST_MODE_CNTRL_REG 0x003c8074 /* DDR23_SHIM testport control register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DISABLE_CHIP_BYPASS_PLL 0x003c807c /* DDR bypass pll mode disable register. */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_VECTOR_MODE_CLK_SEL 0x003c8088 /* DDR VECTOR PLL bypass mode clock select */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL 0x003c808c /* DDR Pad control register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CLK_GATE 0x003c8098 /* CLK_667_ENABLE Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS 0x003c809c /* DDR23_SHIM Status Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO 0x003c8028 /* Command and Data FIFO Status Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH 0x003c802c /* Read Datapath Status Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_FLAG_BUS 0x003c8030 /* TP_OUT bus value Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC    0x003c8034 /* Miscellaneous Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE0_RW 0x003c80a4 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE1_RW 0x003c80a8 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE0_RO 0x003c80ac /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE1_RO 0x003c80b0 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR3_RESET_CNTRL 0x003c80b4 /* FORCE_DDR3_RESET Deassert  Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS 0x003c80b8 /* SYS PLL P and N Divider Controls */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN 0x003c80bc /* SYS PLL Gain Controls */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL 0x003c80c0 /* SYS PLL Control Vector */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_STEP 0x003c80c4 /* SSC Step Size for all 6-chan PLLs */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_LIMIT 0x003c80c8 /* SSC Limit for all 6-chan PLLs */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0 0x003c80cc /* SYS PLL M Divider Controls for Channel0 */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX 0x003c80d0 /* SYS PLL M Divider Controls for Extra Unused Channels */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT 0x003c80d4 /* SYS PLL Status */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel 0x003c80d8 /* SYS PLL power-down and reference clock selection */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_RESET_POST_RESET 0x003c80dc /* SYS PLL Reset and post-resetb selcection */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR 0x003c80e0 /* SYS PLL control and SR selcection */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SHIM_TO_PHY_GATED_BYPASS_CLK 0x003c80e4 /* Shim to PHY gated bypass_clock selection */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG0 0x003c80e8 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG1 0x003c80ec /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG2 0x003c80f0 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG3 0x003c80f4 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG4 0x003c80f8 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG5 0x003c80fc /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG6 0x003c8100 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG7 0x003c8104 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG8 0x003c8108 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG9 0x003c810c /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG10 0x003c8110 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG11 0x003c8114 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG12 0x003c8118 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG13 0x003c811c /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG14 0x003c8120 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG15 0x003c8124 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY 0x003c8128 /* Delay on phy_dyn_vdl to the PHY */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_0 0x003c812c /* DDR PHY data storage register 0 */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_1 0x003c8130 /* DDR PHY data storage register 0 */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_2 0x003c8134 /* DDR PHY data storage register 0 */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_3 0x003c8138 /* DDR PHY data storage register 0 */
+
+/***************************************************************************
+ *CONFIG - DDR23_SHIM Config register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CONFIG :: reserved0 [31:27] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_reserved0_MASK     0xf8000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_reserved0_SHIFT    27
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CONFIG :: LAST_RD_STRETCH [26:26] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_LAST_RD_STRETCH_MASK 0x04000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_LAST_RD_STRETCH_SHIFT 26
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_LAST_RD_STRETCH_DEFAULT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CONFIG :: ODT_LATENCY [25:21] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_ODT_LATENCY_MASK   0x03e00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_ODT_LATENCY_SHIFT  21
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_ODT_LATENCY_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CONFIG :: LAST_READ_LATENCY [20:15] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_LAST_READ_LATENCY_MASK 0x001f8000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_LAST_READ_LATENCY_SHIFT 15
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_LAST_READ_LATENCY_DEFAULT 11
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CONFIG :: READ_LATENCY [14:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_READ_LATENCY_MASK  0x00007f00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_READ_LATENCY_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_READ_LATENCY_DEFAULT 7
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CONFIG :: WRITE_LATENCY [07:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_WRITE_LATENCY_MASK 0x000000f8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_WRITE_LATENCY_SHIFT 3
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_WRITE_LATENCY_DEFAULT 14
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CONFIG :: DRAM_WIDTH [02:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_DRAM_WIDTH_MASK    0x00000006
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_DRAM_WIDTH_SHIFT   1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_DRAM_WIDTH_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CONFIG :: DDR_MODE [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_DDR_MODE_MASK      0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_DDR_MODE_SHIFT     0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_DDR_MODE_DEFAULT   0
+
+/***************************************************************************
+ *DDR23_SHIM_REV_ID - DDR23_SHIM Revision ID Register.
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR23_SHIM_REV_ID :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_REV_ID_reserved0_MASK 0xffff0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_REV_ID_reserved0_SHIFT 16
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR23_SHIM_REV_ID :: MAJOR_ID [15:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_REV_ID_MAJOR_ID_MASK 0x0000ff00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_REV_ID_MAJOR_ID_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_REV_ID_MAJOR_ID_DEFAULT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR23_SHIM_REV_ID :: MINOR_ID [07:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_REV_ID_MINOR_ID_MASK 0x000000ff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_REV_ID_MINOR_ID_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_REV_ID_MINOR_ID_DEFAULT 0
+
+/***************************************************************************
+ *RESET - DDR soft reset register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RESET :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RESET_reserved0_MASK      0xfffffff8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RESET_reserved0_SHIFT     3
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RESET :: DATAPATH_216_RESET [02:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RESET_DATAPATH_216_RESET_MASK 0x00000004
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RESET_DATAPATH_216_RESET_SHIFT 2
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RESET_DATAPATH_216_RESET_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RESET :: DATAPATH_DDR_RESET [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RESET_DATAPATH_DDR_RESET_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RESET_DATAPATH_DDR_RESET_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RESET_DATAPATH_DDR_RESET_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RESET :: PHY_PWRUP_RSB [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RESET_PHY_PWRUP_RSB_MASK  0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RESET_PHY_PWRUP_RSB_SHIFT 0
+
+/***************************************************************************
+ *ODT_CONFIG - ODT Configuration register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: ODT_CONFIG :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_reserved0_MASK 0xffff0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_reserved0_SHIFT 16
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: ODT_CONFIG :: ODT_TIE_HIGH [15:15] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_ODT_TIE_HIGH_MASK 0x00008000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_ODT_TIE_HIGH_SHIFT 15
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_ODT_TIE_HIGH_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: ODT_CONFIG :: ODT_ENABLE [14:14] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_ODT_ENABLE_MASK 0x00004000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_ODT_ENABLE_SHIFT 14
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_ODT_ENABLE_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: ODT_CONFIG :: STRETCH [13:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_STRETCH_MASK   0x00003800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_STRETCH_SHIFT  11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_STRETCH_DEFAULT 3
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: ODT_CONFIG :: EARLY [10:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_EARLY_MASK     0x000007c0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_EARLY_SHIFT    6
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_EARLY_DEFAULT  1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: ODT_CONFIG :: DELAY [05:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_DELAY_MASK     0x0000003f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_DELAY_SHIFT    0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_DELAY_DEFAULT  2
+
+/***************************************************************************
+ *PHY_USE_DYN_VDL - DDR PHY USE DYN VDL Control register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_USE_DYN_VDL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_USE_DYN_VDL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_USE_DYN_VDL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_USE_DYN_VDL :: DISABLE [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_USE_DYN_VDL_DISABLE_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_USE_DYN_VDL_DISABLE_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_USE_DYN_VDL_DISABLE_DEFAULT 0
+
+/***************************************************************************
+ *IDLE_POWER_SAVING - DDR PHY Idle power saving Control register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: IDLE_POWER_SAVING :: reserved0 [31:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_reserved0_MASK 0xffffffc0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_reserved0_SHIFT 6
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: IDLE_POWER_SAVING :: PhyAddrCntl [05:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_PhyAddrCntl_MASK 0x00000030
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_PhyAddrCntl_SHIFT 4
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_PhyAddrCntl_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: IDLE_POWER_SAVING :: ByteLane3 [03:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane3_MASK 0x00000008
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane3_SHIFT 3
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane3_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: IDLE_POWER_SAVING :: ByteLane2 [02:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane2_MASK 0x00000004
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane2_SHIFT 2
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane2_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: IDLE_POWER_SAVING :: ByteLane1 [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane1_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane1_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane1_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: IDLE_POWER_SAVING :: ByteLane0 [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane0_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane0_DEFAULT 0
+
+/***************************************************************************
+ *PHY_STANDBY_EXIT - DDR PHY standby exit register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_STANDBY_EXIT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_STANDBY_EXIT_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_STANDBY_EXIT_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_STANDBY_EXIT :: ENABLE [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_STANDBY_EXIT_ENABLE_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_STANDBY_EXIT_ENABLE_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_STANDBY_EXIT_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *ANALOG_BYPASS_CNTRL - Analog macro register bypass control
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: ANALOG_BYPASS_CNTRL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ANALOG_BYPASS_CNTRL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ANALOG_BYPASS_CNTRL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: ANALOG_BYPASS_CNTRL :: BYPASS_PLL [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ANALOG_BYPASS_CNTRL_BYPASS_PLL_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ANALOG_BYPASS_CNTRL_BYPASS_PLL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ANALOG_BYPASS_CNTRL_BYPASS_PLL_DEFAULT 0
+
+/***************************************************************************
+ *DDR_PLL_EXT_CLKSEL - DDR PLL external clock select register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR_PLL_EXT_CLKSEL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PLL_EXT_CLKSEL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PLL_EXT_CLKSEL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR_PLL_EXT_CLKSEL :: EXT_CLK_SEL [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_DEFAULT 0
+
+/***************************************************************************
+ *TEST_MODE_CNTRL_REG - DDR23_SHIM testport control register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: TEST_MODE_CNTRL_REG :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_TEST_MODE_CNTRL_REG_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_TEST_MODE_CNTRL_REG_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_TEST_MODE_CNTRL_REG_reserved_for_eco0_DEFAULT 0
+
+/***************************************************************************
+ *DISABLE_CHIP_BYPASS_PLL - DDR bypass pll mode disable register.
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DISABLE_CHIP_BYPASS_PLL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DISABLE_CHIP_BYPASS_PLL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DISABLE_CHIP_BYPASS_PLL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DISABLE_CHIP_BYPASS_PLL :: DISABLE_BYPASS_PLL [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_DEFAULT 0
+
+/***************************************************************************
+ *VECTOR_MODE_CLK_SEL - DDR VECTOR PLL bypass mode clock select
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: VECTOR_MODE_CLK_SEL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_VECTOR_MODE_CLK_SEL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_VECTOR_MODE_CLK_SEL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: VECTOR_MODE_CLK_SEL :: SEL [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_VECTOR_MODE_CLK_SEL_SEL_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_VECTOR_MODE_CLK_SEL_SEL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_VECTOR_MODE_CLK_SEL_SEL_DEFAULT 0
+
+/***************************************************************************
+ *DDR_PAD_CNTRL - DDR Pad control register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR_PAD_CNTRL :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_reserved0_MASK 0xffffff80
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_reserved0_SHIFT 7
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR_PAD_CNTRL :: IDDQ_MODE_ON_SELFREF [06:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK 0x00000040
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_SHIFT 6
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR_PAD_CNTRL :: PHY_IDLE_ENABLE [05:05] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_MASK 0x00000020
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_SHIFT 5
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR_PAD_CNTRL :: HIZ_ON_SELFREF [04:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_HIZ_ON_SELFREF_MASK 0x00000010
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_HIZ_ON_SELFREF_SHIFT 4
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_HIZ_ON_SELFREF_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR_PAD_CNTRL :: CNTRL [03:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_CNTRL_MASK  0x0000000f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_CNTRL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_CNTRL_DEFAULT 0
+
+/***************************************************************************
+ *CLK_GATE - CLK_667_ENABLE Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CLK_GATE :: UNUSED [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CLK_GATE_UNUSED_MASK      0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CLK_GATE_UNUSED_SHIFT     1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CLK_GATE_UNUSED_DEFAULT   0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CLK_GATE :: CLK_667_ENABLE [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CLK_GATE_CLK_667_ENABLE_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CLK_GATE_CLK_667_ENABLE_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CLK_GATE_CLK_667_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *DDR23_SHIM_STATUS - DDR23_SHIM Status Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR23_SHIM_STATUS :: reserved0 [31:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS_reserved0_SHIFT 4
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR23_SHIM_STATUS :: BL0_AND_BL1_RDY_SLIP [03:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS_BL0_AND_BL1_RDY_SLIP_MASK 0x00000008
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS_BL0_AND_BL1_RDY_SLIP_SHIFT 3
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR23_SHIM_STATUS :: BL0_RDY_SLIP [02:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS_BL0_RDY_SLIP_MASK 0x00000004
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS_BL0_RDY_SLIP_SHIFT 2
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR23_SHIM_STATUS :: BL1_RDY_SLIP [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS_BL1_RDY_SLIP_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS_BL1_RDY_SLIP_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR23_SHIM_STATUS :: READY [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS_READY_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS_READY_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS_READY_DEFAULT 0
+
+/***************************************************************************
+ *CMD_DATA_FIFO - Command and Data FIFO Status Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CMD_DATA_FIFO :: reserved0 [31:26] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_reserved0_MASK 0xfc000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_reserved0_SHIFT 26
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CMD_DATA_FIFO :: FIFO_FULL [25:25] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_FIFO_FULL_MASK 0x02000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_FIFO_FULL_SHIFT 25
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CMD_DATA_FIFO :: FIFO_EMPTY [24:24] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_FIFO_EMPTY_MASK 0x01000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_FIFO_EMPTY_SHIFT 24
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CMD_DATA_FIFO :: reserved1 [23:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_reserved1_MASK 0x00ffff00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_reserved1_SHIFT 8
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CMD_DATA_FIFO :: WR_PNTR [07:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_WR_PNTR_MASK 0x000000f0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_WR_PNTR_SHIFT 4
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CMD_DATA_FIFO :: RD_PNTR [03:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_RD_PNTR_MASK 0x0000000f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_RD_PNTR_SHIFT 0
+
+/***************************************************************************
+ *RD_DATAPATH - Read Datapath Status Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RD_DATAPATH :: reserved0 [31:28] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_reserved0_MASK 0xf0000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_reserved0_SHIFT 28
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RD_DATAPATH :: F_RDY_3 [27:27] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_F_RDY_3_MASK  0x08000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_F_RDY_3_SHIFT 27
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RD_DATAPATH :: F_RDY_2 [26:26] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_F_RDY_2_MASK  0x04000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_F_RDY_2_SHIFT 26
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RD_DATAPATH :: F_RDY_1 [25:25] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_F_RDY_1_MASK  0x02000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_F_RDY_1_SHIFT 25
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RD_DATAPATH :: F_RDY_0 [24:24] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_F_RDY_0_MASK  0x01000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_F_RDY_0_SHIFT 24
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RD_DATAPATH :: DWORD3_CNT [23:20] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_DWORD3_CNT_MASK 0x00f00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_DWORD3_CNT_SHIFT 20
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RD_DATAPATH :: DWORD2_CNT [19:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_DWORD2_CNT_MASK 0x000f0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_DWORD2_CNT_SHIFT 16
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RD_DATAPATH :: DWORD1_CNT [15:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_DWORD1_CNT_MASK 0x0000f000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_DWORD1_CNT_SHIFT 12
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RD_DATAPATH :: DWORD0_CNT [11:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_DWORD0_CNT_MASK 0x00000f00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_DWORD0_CNT_SHIFT 8
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RD_DATAPATH :: WR_PNTR [07:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_WR_PNTR_MASK  0x000000f0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_WR_PNTR_SHIFT 4
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RD_DATAPATH :: RD_PNTR [03:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_RD_PNTR_MASK  0x0000000f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_RD_PNTR_SHIFT 0
+
+/***************************************************************************
+ *FLAG_BUS - TP_OUT bus value Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: FLAG_BUS :: FLAG_BUS [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_FLAG_BUS_FLAG_BUS_MASK    0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_FLAG_BUS_FLAG_BUS_SHIFT   0
+
+/***************************************************************************
+ *MISC - Miscellaneous Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: reserved_for_eco0 [31:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_reserved_for_eco0_MASK 0xfffff000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_reserved_for_eco0_SHIFT 12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_reserved_for_eco0_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: BL0_AND_BL1_RDY_SLIP_CLR [11:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_BL0_AND_BL1_RDY_SLIP_CLR_MASK 0x00000800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_BL0_AND_BL1_RDY_SLIP_CLR_SHIFT 11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_BL0_AND_BL1_RDY_SLIP_CLR_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: BL0_RDY_SLIP_CLR [10:10] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_BL0_RDY_SLIP_CLR_MASK 0x00000400
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_BL0_RDY_SLIP_CLR_SHIFT 10
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_BL0_RDY_SLIP_CLR_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: BL1_RDY_SLIP_CLR [09:09] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_BL1_RDY_SLIP_CLR_MASK 0x00000200
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_BL1_RDY_SLIP_CLR_SHIFT 9
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_BL1_RDY_SLIP_CLR_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: FUNC1 [08:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_FUNC1_MASK           0x00000100
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_FUNC1_SHIFT          8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_FUNC1_DEFAULT        0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: FUNC0 [07:07] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_FUNC0_MASK           0x00000080
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_FUNC0_SHIFT          7
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_FUNC0_DEFAULT        0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: C2IO_INIT_RDY_OVR [06:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_C2IO_INIT_RDY_OVR_MASK 0x00000040
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_C2IO_INIT_RDY_OVR_SHIFT 6
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_C2IO_INIT_RDY_OVR_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: RD_FIFO_HOLD_CLR [05:05] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_RD_FIFO_HOLD_CLR_MASK 0x00000020
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_RD_FIFO_HOLD_CLR_SHIFT 5
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_RD_FIFO_HOLD_CLR_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: CMD_FIFO_HOLD_CLR [04:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_CMD_FIFO_HOLD_CLR_MASK 0x00000010
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_CMD_FIFO_HOLD_CLR_SHIFT 4
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_CMD_FIFO_HOLD_CLR_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: DWORD3_OVERRUN_CLR [03:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD3_OVERRUN_CLR_MASK 0x00000008
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD3_OVERRUN_CLR_SHIFT 3
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD3_OVERRUN_CLR_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: DWORD2_OVERRUN_CLR [02:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD2_OVERRUN_CLR_MASK 0x00000004
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD2_OVERRUN_CLR_SHIFT 2
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD2_OVERRUN_CLR_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: DWORD1_OVERRUN_CLR [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD1_OVERRUN_CLR_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD1_OVERRUN_CLR_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD1_OVERRUN_CLR_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: DWORD0_OVERRUN_CLR [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD0_OVERRUN_CLR_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD0_OVERRUN_CLR_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD0_OVERRUN_CLR_DEFAULT 0
+
+/***************************************************************************
+ *SPARE0_RW - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SPARE0_RW :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE0_RW_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE0_RW_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE0_RW_reserved_for_eco0_DEFAULT 0
+
+/***************************************************************************
+ *SPARE1_RW - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SPARE1_RW :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE1_RW_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE1_RW_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE1_RW_reserved_for_eco0_DEFAULT 0
+
+/***************************************************************************
+ *SPARE0_RO - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SPARE0_RO :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE0_RO_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE0_RO_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE0_RO_reserved_for_eco0_DEFAULT 0
+
+/***************************************************************************
+ *SPARE1_RO - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SPARE1_RO :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE1_RO_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE1_RO_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE1_RO_reserved_for_eco0_DEFAULT 0
+
+/***************************************************************************
+ *DDR3_RESET_CNTRL - FORCE_DDR3_RESET Deassert  Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR3_RESET_CNTRL :: UNUSED [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR3_RESET_CNTRL_UNUSED_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR3_RESET_CNTRL_UNUSED_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR3_RESET_CNTRL_UNUSED_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR3_RESET_CNTRL :: FORCE_DDR3_RESET [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_DEFAULT 1
+
+/***************************************************************************
+ *PLL6CH_PNDIV_SYS - SYS PLL P and N Divider Controls
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PLL6CH_PNDIV_SYS :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS_reserved0_MASK 0x80000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS_reserved0_SHIFT 31
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PLL6CH_PNDIV_SYS :: PDIV [30:28] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS_PDIV_MASK 0x70000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS_PDIV_SHIFT 28
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS_PDIV_DEFAULT 2
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PLL6CH_PNDIV_SYS :: NDIV_INT [27:20] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS_NDIV_INT_MASK 0x0ff00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS_NDIV_INT_SHIFT 20
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS_NDIV_INT_DEFAULT 78
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PLL6CH_PNDIV_SYS :: NDIV_FRAC [19:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS_NDIV_FRAC_MASK 0x000fffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS_NDIV_FRAC_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS_NDIV_FRAC_DEFAULT 0
+
+/***************************************************************************
+ *SYS_PLL_GAIN - SYS PLL Gain Controls
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_GAIN :: reserved0 [31:23] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_reserved0_MASK 0xff800000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_reserved0_SHIFT 23
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_GAIN :: FB_PHASE_ENA [22:22] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_FB_PHASE_ENA_MASK 0x00400000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_FB_PHASE_ENA_SHIFT 22
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_FB_PHASE_ENA_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_GAIN :: FB_PHASE_OFFSET [21:10] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_FB_PHASE_OFFSET_MASK 0x003ffc00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_FB_PHASE_OFFSET_SHIFT 10
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_FB_PHASE_OFFSET_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_GAIN :: KP [09:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_KP_MASK      0x000003c0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_KP_SHIFT     6
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_KP_DEFAULT   8
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_GAIN :: KI [05:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_KI_MASK      0x00000038
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_KI_SHIFT     3
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_KI_DEFAULT   3
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_GAIN :: KA [02:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_KA_MASK      0x00000007
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_KA_SHIFT     0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_KA_DEFAULT   1
+
+/***************************************************************************
+ *SYS_PLL_CTRL - SYS PLL Control Vector
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL :: reserved0 [31:23] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_reserved0_MASK 0xff800000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_reserved0_SHIFT 23
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL :: ENA_8PHASE [22:22] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_ENA_8PHASE_MASK 0x00400000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_ENA_8PHASE_SHIFT 22
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_ENA_8PHASE_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL :: ENA_SSC [21:21] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_ENA_SSC_MASK 0x00200000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_ENA_SSC_SHIFT 21
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_ENA_SSC_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL :: VCO_DIV2_EN [20:20] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_VCO_DIV2_EN_MASK 0x00100000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_VCO_DIV2_EN_SHIFT 20
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_VCO_DIV2_EN_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL :: AUX_CTRL [19:19] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_AUX_CTRL_MASK 0x00080000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_AUX_CTRL_SHIFT 19
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_AUX_CTRL_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL :: REFCLK_OUT [18:18] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_REFCLK_OUT_MASK 0x00040000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_REFCLK_OUT_SHIFT 18
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_REFCLK_OUT_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL :: STAT_UPDATE [17:17] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_STAT_UPDATE_MASK 0x00020000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_STAT_UPDATE_SHIFT 17
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_STAT_UPDATE_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL :: STAT_SELECT [16:14] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_STAT_SELECT_MASK 0x0001c000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_STAT_SELECT_SHIFT 14
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_STAT_SELECT_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL :: STAT_RESET [13:13] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_STAT_RESET_MASK 0x00002000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_STAT_RESET_SHIFT 13
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_STAT_RESET_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL :: DCO_CTRL_BYPASS_ENA [12:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_DCO_CTRL_BYPASS_ENA_MASK 0x00001000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_DCO_CTRL_BYPASS_ENA_SHIFT 12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_DCO_CTRL_BYPASS_ENA_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_DCO_CTRL_BYPASS_MASK 0x00000fff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_DCO_CTRL_BYPASS_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_DCO_CTRL_BYPASS_DEFAULT 0
+
+/***************************************************************************
+ *SSC_STEP - SSC Step Size for all 6-chan PLLs
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SSC_STEP :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_STEP_reserved0_MASK   0xffff0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_STEP_reserved0_SHIFT  16
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SSC_STEP :: SSC_STEP [15:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_STEP_SSC_STEP_MASK    0x0000ffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_STEP_SSC_STEP_SHIFT   0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_STEP_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *SSC_LIMIT - SSC Limit for all 6-chan PLLs
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SSC_LIMIT :: reserved0 [31:22] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_LIMIT_reserved0_MASK  0xffc00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_LIMIT_reserved0_SHIFT 22
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SSC_LIMIT :: SSC_LIMIT [21:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_LIMIT_SSC_LIMIT_MASK  0x003fffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_LIMIT_SSC_LIMIT_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_LIMIT_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *SYS_PLL_MDIV0 - SYS PLL M Divider Controls for Channel0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIV0 :: reserved0 [31:14] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_reserved0_MASK 0xffffc000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_reserved0_SHIFT 14
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIV0 :: CHAN_HOLD_OUTPUT [13:13] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_HOLD_OUTPUT_MASK 0x00002000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_HOLD_OUTPUT_SHIFT 13
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_HOLD_OUTPUT_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIV0 :: CHAN_LOAD_MDIV [12:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_LOAD_MDIV_MASK 0x00001000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_LOAD_MDIV_SHIFT 12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_LOAD_MDIV_DEFAULT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIV0 :: CHAN_ENA [11:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_ENA_MASK 0x00000800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_ENA_SHIFT 11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_ENA_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIV0 :: CHAN_MDEL [10:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_MDEL_MASK 0x00000700
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_MDEL_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_MDEL_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIV0 :: CHAN_MDIV [07:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_MDIV_MASK 0x000000ff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_MDIV_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_MDIV_DEFAULT 8
+
+/***************************************************************************
+ *SYS_PLL_MDIVX - SYS PLL M Divider Controls for Extra Unused Channels
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIVX :: reserved0 [31:14] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_reserved0_MASK 0xffffc000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_reserved0_SHIFT 14
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIVX :: CHAN_HOLD_OUTPUT [13:13] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_HOLD_OUTPUT_MASK 0x00002000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_HOLD_OUTPUT_SHIFT 13
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_HOLD_OUTPUT_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIVX :: CHAN_LOAD_MDIV [12:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_LOAD_MDIV_MASK 0x00001000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_LOAD_MDIV_SHIFT 12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_LOAD_MDIV_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIVX :: CHAN_ENA [11:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_ENA_MASK 0x00000800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_ENA_SHIFT 11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_ENA_DEFAULT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIVX :: CHAN_MDEL [10:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_MDEL_MASK 0x00000700
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_MDEL_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_MDEL_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIVX :: CHAN_MDIV [07:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_MDIV_MASK 0x000000ff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_MDIV_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_MDIV_DEFAULT 0
+
+/***************************************************************************
+ *SYS_PLL_STAT - SYS PLL Status
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_STAT :: reserved0 [31:25] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT_reserved0_MASK 0xfe000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT_reserved0_SHIFT 25
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_STAT :: DEBUG_OUTPUT [24:13] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT_DEBUG_OUTPUT_MASK 0x01ffe000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT_DEBUG_OUTPUT_SHIFT 13
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT_DEBUG_OUTPUT_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_STAT :: LOCK [12:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT_LOCK_MASK    0x00001000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT_LOCK_SHIFT   12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT_LOCK_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_STAT :: UNLOCK_COUNT [11:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT_UNLOCK_COUNT_MASK 0x00000fff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT_UNLOCK_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT_UNLOCK_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *SYS_PLL_PWRDN_ref_clk_sel - SYS PLL power-down and reference clock selection
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_PWRDN_ref_clk_sel :: reserved0 [31:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel_reserved0_MASK 0xfffffffc
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel_reserved0_SHIFT 2
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_PWRDN_ref_clk_sel :: REFCLK_SEL [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel_REFCLK_SEL_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel_REFCLK_SEL_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel_REFCLK_SEL_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_PWRDN_ref_clk_sel :: PWRDN [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel_PWRDN_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel_PWRDN_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel_PWRDN_DEFAULT 0
+
+/***************************************************************************
+ *SYS_PLL_RESET_POST_RESET - SYS PLL Reset and post-resetb selcection
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_RESET_POST_RESET :: reserved0 [31:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_RESET_POST_RESET_reserved0_MASK 0xfffffffc
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_RESET_POST_RESET_reserved0_SHIFT 2
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_RESET_POST_RESET :: POST_RESETB [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_RESET_POST_RESET_POST_RESETB_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_RESET_POST_RESET_POST_RESETB_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_RESET_POST_RESET_POST_RESETB_DEFAULT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_RESET_POST_RESET :: GLOBAL_RESETB [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_RESET_POST_RESET_GLOBAL_RESETB_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_RESET_POST_RESET_GLOBAL_RESETB_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_RESET_POST_RESET_GLOBAL_RESETB_DEFAULT 1
+
+/***************************************************************************
+ *SYS_PLL_CTRL_SR - SYS PLL control and SR selcection
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL_SR :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR_reserved0_MASK 0xe0000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR_reserved0_SHIFT 29
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL_SR :: PLL_SR [28:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR_PLL_SR_MASK 0x1ffff800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR_PLL_SR_SHIFT 11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR_PLL_SR_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL_SR :: PLL_CTRL_1 [10:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR_PLL_CTRL_1_MASK 0x000007fc
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR_PLL_CTRL_1_SHIFT 2
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR_PLL_CTRL_1_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL_SR :: NDIV_INT_1 [01:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR_NDIV_INT_1_MASK 0x00000003
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR_NDIV_INT_1_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR_NDIV_INT_1_DEFAULT 0
+
+/***************************************************************************
+ *SHIM_TO_PHY_GATED_BYPASS_CLK - Shim to PHY gated bypass_clock selection
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SHIM_TO_PHY_GATED_BYPASS_CLK :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SHIM_TO_PHY_GATED_BYPASS_CLK_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SHIM_TO_PHY_GATED_BYPASS_CLK_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SHIM_TO_PHY_GATED_BYPASS_CLK :: BYPASS_CLK_GATED_TO_SHIM_PHY [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SHIM_TO_PHY_GATED_BYPASS_CLK_BYPASS_CLK_GATED_TO_SHIM_PHY_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SHIM_TO_PHY_GATED_BYPASS_CLK_BYPASS_CLK_GATED_TO_SHIM_PHY_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SHIM_TO_PHY_GATED_BYPASS_CLK_BYPASS_CLK_GATED_TO_SHIM_PHY_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH_REG0 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG0 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG0_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG0_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG0_reserved_for_schmoo_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH_REG1 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG1 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG1_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG1_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG1_reserved_for_schmoo_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH_REG2 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG2 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG2_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG2_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG2_reserved_for_schmoo_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH_REG3 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG3 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG3_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG3_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG3_reserved_for_schmoo_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH_REG4 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG4 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG4_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG4_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG4_reserved_for_schmoo_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH_REG5 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG5 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG5_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG5_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG5_reserved_for_schmoo_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH_REG6 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG6 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG6_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG6_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG6_reserved_for_schmoo_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH_REG7 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG7 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG7_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG7_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG7_reserved_for_schmoo_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH_REG8 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG8 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG8_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG8_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG8_reserved_for_schmoo_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH_REG9 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG9 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG9_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG9_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG9_reserved_for_schmoo_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH_REG10 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG10 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG10_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG10_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG10_reserved_for_schmoo_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH_REG11 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG11 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG11_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG11_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG11_reserved_for_schmoo_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH_REG12 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG12 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG12_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG12_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG12_reserved_for_schmoo_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH_REG13 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG13 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG13_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG13_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG13_reserved_for_schmoo_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH_REG14 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG14 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG14_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG14_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG14_reserved_for_schmoo_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH_REG15 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG15 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG15_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG15_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG15_reserved_for_schmoo_DEFAULT 0
+
+/***************************************************************************
+ *PHY_DYN_VDL_DLY - Delay on phy_dyn_vdl to the PHY
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_DYN_VDL_DLY :: reserved0 [31:28] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_reserved0_MASK 0xf0000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_reserved0_SHIFT 28
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_DYN_VDL_DLY :: DYN_VDL_DEASSERT_TO_READ_ENB_DLY [27:24] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_READ_ENB_DLY_MASK 0x0f000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_READ_ENB_DLY_SHIFT 24
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_READ_ENB_DLY_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_DYN_VDL_DLY :: reserved1 [23:20] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_reserved1_MASK 0x00f00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_reserved1_SHIFT 20
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_DYN_VDL_DLY :: DYN_VDL_ASSERT_TO_READ_ENB_DLY [19:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_READ_ENB_DLY_MASK 0x000f0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_READ_ENB_DLY_SHIFT 16
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_READ_ENB_DLY_DEFAULT 0
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_DYN_VDL_DLY :: reserved2 [15:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_reserved2_MASK 0x0000f000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_reserved2_SHIFT 12
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_DYN_VDL_DLY :: DYN_VDL_DEASSERT_TO_WR_VALID_DLY [11:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_WR_VALID_DLY_MASK 0x00000f00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_WR_VALID_DLY_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_WR_VALID_DLY_DEFAULT 2
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_DYN_VDL_DLY :: reserved3 [07:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_reserved3_MASK 0x000000f0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_reserved3_SHIFT 4
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_DYN_VDL_DLY :: DYN_VDL_ASSERT_TO_WR_VALID_DLY [03:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_WR_VALID_DLY_MASK 0x0000000f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_WR_VALID_DLY_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_WR_VALID_DLY_DEFAULT 2
+
+/***************************************************************************
+ *AON_STORAGE_IN_PHY_0 - DDR PHY data storage register 0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: AON_STORAGE_IN_PHY_0 :: DTATA [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_0_DTATA_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_0_DTATA_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_0_DTATA_DEFAULT 0
+
+/***************************************************************************
+ *AON_STORAGE_IN_PHY_1 - DDR PHY data storage register 0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: AON_STORAGE_IN_PHY_1 :: DTATA [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_1_DTATA_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_1_DTATA_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_1_DTATA_DEFAULT 0
+
+/***************************************************************************
+ *AON_STORAGE_IN_PHY_2 - DDR PHY data storage register 0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: AON_STORAGE_IN_PHY_2 :: DTATA [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_2_DTATA_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_2_DTATA_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_2_DTATA_DEFAULT 0
+
+/***************************************************************************
+ *AON_STORAGE_IN_PHY_3 - DDR PHY data storage register 0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: AON_STORAGE_IN_PHY_3 :: DTATA [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_3_DTATA_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_3_DTATA_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_3_DTATA_DEFAULT 0
+
+#endif /* #ifndef BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_memc_ddr_0.h b/include/linux/brcmstb/7425b0/bchp_memc_ddr_0.h
new file mode 100644
index 0000000..1cadd0d
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_memc_ddr_0.h
@@ -0,0 +1,2662 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:42 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR_0_H__
+#define BCHP_MEMC_DDR_0_H__
+
+/***************************************************************************
+ *MEMC_DDR_0 - Memory Controller Sequencer (DDR Param/Control) Registers 0
+ ***************************************************************************/
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG            0x003b2000 /* Memory Controller Mode-Configuration Register. */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL          0x003b2004 /* Dram iniitialization control */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS         0x003b2008 /* Dram iniitialization status */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0              0x003b200c /* Dram Mode0 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1              0x003b2010 /* Dram Mode1 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2              0x003b2014 /* Dram Mode2 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3              0x003b2018 /* Dram Mode3 register */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG               0x003b201c /* Precharge power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG              0x003b2020 /* Self-refresh power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SSPD_CMD                 0x003b2024 /* Software standby power down mode */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS        0x003b2028 /* Power down status */
+#define BCHP_MEMC_DDR_0_WARM_BOOT                0x003b202c /* Warm boot control registers */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0            0x003b2030 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1            0x003b2034 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2            0x003b2038 /* Read to Write & write to read timing register */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3            0x003b203c /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4            0x003b2040 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5            0x003b2044 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ         0x003b2048 /* Memory Controller Sequencer Enable */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT        0x003b204c /* Memory Controller , state machine timeout register. */
+#define BCHP_MEMC_DDR_0_BANK_STATUS              0x003b2050 /* Memory Controller, Bank Status Register. */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY           0x003b2054 /* Memory Controller, Tester Latency Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0               0x003b2058 /* Memory Controller, DATA_PINMAP_BYTE0_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1               0x003b205c /* Memory Controller, DATA_PINMAP_BYTE1_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2               0x003b2060 /* Memory Controller, DATA_PINMAP_BYTE2_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3               0x003b2064 /* Memory Controller, DATA_PINMAP_BYTE3_SEL Register. */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD   0x003b2068 /* Memory Controller, DDR3 DRAM reset Register. */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL             0x003b206c /* Statistics Control register */
+#define BCHP_MEMC_DDR_0_STAT_TIMER               0x003b2070 /* Statistics Timer */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP            0x003b2074 /* DRAM Idle_NOP Cycle Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP        0x003b2078 /* Maximum DRAM idle_NOP cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL             0x003b207c /* CAS Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL         0x003b2080 /* Maximum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL         0x003b2084 /* DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL 0x003b2088 /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL      0x003b208c /* Number of overall system memory read transactions. */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL     0x003b2090 /* Number of overall system memory write transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL       0x003b2094 /* Maximum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL       0x003b2098 /* Minimum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS  0x003b209c /* Service CAS Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS 0x003b20a0 /* Maximum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS 0x003b20a4 /* Minimum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY 0x003b20a8 /* Service Intra DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY 0x003b20ac /* Service Post DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES 0x003b20b0 /* Maximum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES 0x003b20b4 /* Minimum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ 0x003b20b8 /* Service Read Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE 0x003b20bc /* Service Write Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS 0x003b20c0 /* Maximum service Transaction count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS 0x003b20c4 /* Minimum service cycle Transaction register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY 0x003b20c8 /* Service Latency Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY 0x003b20cc /* Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY 0x003b20d0 /* Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x003b20d4 /* Absolute Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x003b20d8 /* Absolute Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH             0x003b20dc /* Total number of refreshes issuedr. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0        0x003b20e0 /* CAS cycle count register for client 0. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1        0x003b20e4 /* CAS cycle count register for client 1. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2        0x003b20e8 /* CAS cycle count register for client 2. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3        0x003b20ec /* CAS cycle count register for client 3. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4        0x003b20f0 /* CAS cycle count register for client 4. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5        0x003b20f4 /* CAS cycle count register for client 5. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6        0x003b20f8 /* CAS cycle count register for client 6. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7        0x003b20fc /* CAS cycle count register for client 7. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8        0x003b2100 /* CAS cycle count register for client 8. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9        0x003b2104 /* CAS cycle count register for client 9. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10       0x003b2108 /* CAS cycle count register for client 10. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11       0x003b210c /* CAS cycle count register for client 11. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12       0x003b2110 /* CAS cycle count register for client 12. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13       0x003b2114 /* CAS cycle count register for client 13. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14       0x003b2118 /* CAS cycle count register for client 14. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15       0x003b211c /* CAS cycle count register for client 15. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16       0x003b2120 /* CAS cycle count register for client 16. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17       0x003b2124 /* CAS cycle count register for client 17. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18       0x003b2128 /* CAS cycle count register for client 18. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19       0x003b212c /* CAS cycle count register for client 19. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20       0x003b2130 /* CAS cycle count register for client 20. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21       0x003b2134 /* CAS cycle count register for client 21. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22       0x003b2138 /* CAS cycle count register for client 22. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23       0x003b213c /* CAS cycle count register for client 23. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24       0x003b2140 /* CAS cycle count register for client 24. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25       0x003b2144 /* CAS cycle count register for client 25. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26       0x003b2148 /* CAS cycle count register for client 26. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27       0x003b214c /* CAS cycle count register for client 27. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28       0x003b2150 /* CAS cycle count register for client 28. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29       0x003b2154 /* CAS cycle count register for client 29. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30       0x003b2158 /* CAS cycle count register for client 30. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31       0x003b215c /* CAS cycle count register for client 31. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32       0x003b2160 /* CAS cycle count register for client 32. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33       0x003b2164 /* CAS cycle count register for client 33. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34       0x003b2168 /* CAS cycle count register for client 34. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35       0x003b216c /* CAS cycle count register for client 35. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36       0x003b2170 /* CAS cycle count register for client 36. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37       0x003b2174 /* CAS cycle count register for client 37. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38       0x003b2178 /* CAS cycle count register for client 38. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39       0x003b217c /* CAS cycle count register for client 39. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40       0x003b2180 /* CAS cycle count register for client 40. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41       0x003b2184 /* CAS cycle count register for client 41. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42       0x003b2188 /* CAS cycle count register for client 42. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43       0x003b218c /* CAS cycle count register for client 43. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44       0x003b2190 /* CAS cycle count register for client 44. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45       0x003b2194 /* CAS cycle count register for client 45. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46       0x003b2198 /* CAS cycle count register for client 46. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47       0x003b219c /* CAS cycle count register for client 47. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48       0x003b21a0 /* CAS cycle count register for client 48. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49       0x003b21a4 /* CAS cycle count register for client 49. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50       0x003b21a8 /* CAS cycle count register for client 50. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51       0x003b21ac /* CAS cycle count register for client 51. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52       0x003b21b0 /* CAS cycle count register for client 52. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53       0x003b21b4 /* CAS cycle count register for client 53. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54       0x003b21b8 /* CAS cycle count register for client 54. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55       0x003b21bc /* CAS cycle count register for client 55. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56       0x003b21c0 /* CAS cycle count register for client 56. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57       0x003b21c4 /* CAS cycle count register for client 57. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58       0x003b21c8 /* CAS cycle count register for client 58. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59       0x003b21cc /* CAS cycle count register for client 59. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60       0x003b21d0 /* CAS cycle count register for client 60. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61       0x003b21d4 /* CAS cycle count register for client 61. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62       0x003b21d8 /* CAS cycle count register for client 62. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63       0x003b21dc /* CAS cycle count register for client 63. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64       0x003b21e0 /* CAS cycle count register for client 64. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65       0x003b21e4 /* CAS cycle count register for client 65. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66       0x003b21e8 /* CAS cycle count register for client 66. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67       0x003b21ec /* CAS cycle count register for client 67. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68       0x003b21f0 /* CAS cycle count register for client 68. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69       0x003b21f4 /* CAS cycle count register for client 69. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70       0x003b21f8 /* CAS cycle count register for client 70. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71       0x003b21fc /* CAS cycle count register for client 71. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72       0x003b2200 /* CAS cycle count register for client 72. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73       0x003b2204 /* CAS cycle count register for client 73. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74       0x003b2208 /* CAS cycle count register for client 74. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75       0x003b220c /* CAS cycle count register for client 75. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76       0x003b2210 /* CAS cycle count register for client 76. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77       0x003b2214 /* CAS cycle count register for client 77. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78       0x003b2218 /* CAS cycle count register for client 78. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79       0x003b221c /* CAS cycle count register for client 79. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80       0x003b2220 /* CAS cycle count register for client 80. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81       0x003b2224 /* CAS cycle count register for client 81. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82       0x003b2228 /* CAS cycle count register for client 82. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83       0x003b222c /* CAS cycle count register for client 83. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84       0x003b2230 /* CAS cycle count register for client 84. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85       0x003b2234 /* CAS cycle count register for client 85. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86       0x003b2238 /* CAS cycle count register for client 86. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87       0x003b223c /* CAS cycle count register for client 87. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88       0x003b2240 /* CAS cycle count register for client 88. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89       0x003b2244 /* CAS cycle count register for client 89. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90       0x003b2248 /* CAS cycle count register for client 90. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91       0x003b224c /* CAS cycle count register for client 91. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92       0x003b2250 /* CAS cycle count register for client 92. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93       0x003b2254 /* CAS cycle count register for client 93. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94       0x003b2258 /* CAS cycle count register for client 94. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95       0x003b225c /* CAS cycle count register for client 95. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96       0x003b2260 /* CAS cycle count register for client 96. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97       0x003b2264 /* CAS cycle count register for client 97. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98       0x003b2268 /* CAS cycle count register for client 98. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99       0x003b226c /* CAS cycle count register for client 99. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100      0x003b2270 /* CAS cycle count register for client 100. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101      0x003b2274 /* CAS cycle count register for client 101. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102      0x003b2278 /* CAS cycle count register for client 102. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103      0x003b227c /* CAS cycle count register for client 103. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104      0x003b2280 /* CAS cycle count register for client 104. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105      0x003b2284 /* CAS cycle count register for client 105. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106      0x003b2288 /* CAS cycle count register for client 106. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107      0x003b228c /* CAS cycle count register for client 107. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108      0x003b2290 /* CAS cycle count register for client 108. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109      0x003b2294 /* CAS cycle count register for client 109. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110      0x003b2298 /* CAS cycle count register for client 110. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111      0x003b229c /* CAS cycle count register for client 111. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112      0x003b22a0 /* CAS cycle count register for client 112. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113      0x003b22a4 /* CAS cycle count register for client 113. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114      0x003b22a8 /* CAS cycle count register for client 114. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115      0x003b22ac /* CAS cycle count register for client 115. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116      0x003b22b0 /* CAS cycle count register for client 116. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117      0x003b22b4 /* CAS cycle count register for client 117. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118      0x003b22b8 /* CAS cycle count register for client 118. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119      0x003b22bc /* CAS cycle count register for client 119. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120      0x003b22c0 /* CAS cycle count register for client 120. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121      0x003b22c4 /* CAS cycle count register for client 121. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122      0x003b22c8 /* CAS cycle count register for client 122. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123      0x003b22cc /* CAS cycle count register for client 123. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124      0x003b22d0 /* CAS cycle count register for client 124. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125      0x003b22d4 /* CAS cycle count register for client 125. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126      0x003b22d8 /* CAS cycle count register for client 126. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127      0x003b22dc /* CAS cycle count register for client 127. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL         0x003b22e0 /* Minimum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL 0x003b22e4 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL 0x003b22e8 /* MEMSYS Auto Init Control. */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS  0x003b22ec /* MEMSYS Auto Init Status. */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE 0x003b22f0 /* PHY VDL calibrate override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE 0x003b22f4 /* SHIM PLL pndiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE 0x003b22f8 /* SHIM PLL mdiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY          0x003b22fc /* Dynamic VDL shmoo command delay. */
+
+/***************************************************************************
+ *CNTRLR_CONFIG - Memory Controller Mode-Configuration Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_MASK               0xfffffff8
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_SHIFT              3
+
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DEVICE_TECH [02:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_SHIFT            0
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_DEFAULT          0x00000003
+
+/***************************************************************************
+ *DRAM_INIT_CNTRL - Dram iniitialization control
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_MASK             0xfffffff8
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_SHIFT            3
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: BYPASS_PHY_INIT_RDY [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_MASK   0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_SHIFT  2
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR_TECH [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DEFAULT           0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR2              0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR3              1
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR3_INIT_MODE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_MASK        0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_SHIFT       0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *DRAM_INIT_STATUS - Dram iniitialization status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_SHIFT           0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_DEFAULT         0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_0 - Dram Mode0 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: PD_EXIT [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_MASK              0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_SHIFT             12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_DEFAULT         0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: CL [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_MASK                   0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_DEFAULT                0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BL [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_DEFAULT                0x00000002
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK        0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT       12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT     0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT         0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_MASK               0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_SHIFT              4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT            0x00000004
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_DEFAULT               0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_MASK                 0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_SHIFT                2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_DEFAULT              0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_MASK                   0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_1 - Dram Mode1 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DEFAULT             0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: RDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DQSB [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_MASK                 0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_SHIFT                10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_ENABLE               0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DISABLE              1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: OCD_CAL [09:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_MASK              0x00000380
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_SHIFT             7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_DEFAULT       0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: AL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_MASK                   0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DRV_IMP [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DISABLE            1
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT             0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_MASK             0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_SHIFT            10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK          0x00000200
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT         9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_MASK             0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT            7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT          0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE           1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK   0x00000020
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT  5
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_MASK                   0x00000018
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT       0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK   0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT  1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DISABLE            1
+
+/***************************************************************************
+ *DRAM_MODE_2 - Dram Mode2 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_1 [12:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_MASK             0x00001f00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: HT_SRF [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_ENABLE             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DISABLE            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_2 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_MASK             0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_SHIFT            4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: DCC_ENABLE [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_MASK           0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_SHIFT          3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DEFAULT        0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_ENABLE         1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DISABLE        0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_DEFAULT              0x00000000
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_MASK             0x00001800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_SHIFT            11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_MASK               0x00000600
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_SHIFT              9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT            0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT            0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT             6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_MASK                  0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_DEFAULT               0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_3 - Dram Mode3 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: unused_0 [15:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_MASK                  0x0000fff8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR2 :: unused_1 [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_SHIFT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_DEFAULT          0x00000000
+
+/* union - case DDR3 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_MASK                  0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_SHIFT                 2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_DEFAULT               0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_MASK              0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PPD_CONFIG - Precharge power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PPD_CONFIG :: reserved0 [31:13] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_MASK                  0xffffe000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_SHIFT                 13
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_EN [12:12] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_MASK                     0x00001000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_SHIFT                    12
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_DEFAULT                  0x00000000
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: INACT_COUNT [11:00] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_MASK                0x00000fff
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *SRPD_CONFIG - Self-refresh power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SRPD_CONFIG :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_MASK                 0xfffe0000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_SHIFT                17
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: SRPD_EN [16:16] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_MASK                   0x00010000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_SHIFT                  16
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_DEFAULT                0x00000000
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SSPD_CMD - Software standby power down mode
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SSPD_CMD :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_MASK                    0xfffffffe
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_SHIFT                   1
+
+/* MEMC_DDR_0 :: SSPD_CMD :: SSPD [00:00] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK                         0x00000001
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_SHIFT                        0
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *POWER_DOWN_STATUS - Power down status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_MASK           0xfffffff8
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_SHIFT          3
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SSPD [02:02] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK                0x00000004
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_SHIFT               2
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_DEFAULT             0x00000000
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SRPD [01:01] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_MASK                0x00000002
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_SHIFT               1
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_DEFAULT             0x00000000
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: PPD [00:00] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_MASK                 0x00000001
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_SHIFT                0
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_DEFAULT              0x00000000
+
+/***************************************************************************
+ *WARM_BOOT - Warm boot control registers
+ ***************************************************************************/
+/* MEMC_DDR_0 :: WARM_BOOT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_MASK                   0xfffffffe
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_SHIFT                  1
+
+/* MEMC_DDR_0 :: WARM_BOOT :: WARM_BOOT [00:00] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_MASK                   0x00000001
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_TIMING_0 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_MASK                0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_SHIFT               24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_DEFAULT             0x00000006
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_MASK                0x00ff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_SHIFT               16
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_DEFAULT             0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_MASK                 0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_SHIFT                8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_DEFAULT              0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_DEFAULT             0x00000014
+
+/***************************************************************************
+ *DRAM_TIMING_1 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_MASK                0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_SHIFT               8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_DEFAULT             0x0000001b
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_DEFAULT             0x00000004
+
+/***************************************************************************
+ *DRAM_TIMING_2 - Read to Write & write to read timing register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_MASK               0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_SHIFT              8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_DEFAULT            0x0000000e
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_MASK               0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_DEFAULT            0x00000009
+
+/***************************************************************************
+ *DRAM_TIMING_3 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: reserved0 [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_MASK               0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_SHIFT              24
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT      0x0000000c
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: POWERUP_CKE_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_MASK       0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_SHIFT      10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_DEFAULT    0x0000005e
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: DLL_LOCK_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_MASK          0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_SHIFT         0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_DEFAULT       0x00000200
+
+/***************************************************************************
+ *DRAM_TIMING_4 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: PRECHARGE_ALL_DELAY [28:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_MASK     0x1f000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_SHIFT    24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_DEFAULT  0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: LOAD_MODE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_DEFAULT      0x0000000c
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: REFRESH_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_MASK           0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_SHIFT          10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT        0x00000058
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_MASK           0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT          0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT        0x00000200
+
+/***************************************************************************
+ *DRAM_TIMING_5 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_ASSETION_DELAY [28:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_MASK      0x1ff80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_SHIFT     19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_DEFAULT   0x00000105
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [18:15] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK           0x00078000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT          15
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT        0x00000003
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [14:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK         0x00007c00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT        10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT      0x0000000d
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK      0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT     0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT   0x00000200
+
+/***************************************************************************
+ *CNTRLR_START_SEQ - Memory Controller Sequencer Enable
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: START_SEQ [00:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_SHIFT           0
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_MASK           0xfffe0000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_SHIFT          17
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_MASK              0x00010000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT             16
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT            0x0000ffff
+
+/***************************************************************************
+ *BANK_STATUS - Memory Controller, Bank Status Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: BANK_STATUS :: reserved0 [31:08] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_SHIFT                8
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK7_STATUS [07:07] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_SHIFT             7
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK6_STATUS [06:06] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_SHIFT             6
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK5_STATUS [05:05] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_MASK              0x00000020
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_SHIFT             5
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK4_STATUS [04:04] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_MASK              0x00000010
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_SHIFT             4
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK3_STATUS [03:03] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_MASK              0x00000008
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_SHIFT             3
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK2_STATUS [02:02] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_MASK              0x00000004
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_SHIFT             2
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK1_STATUS [01:01] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_SHIFT             1
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK0_STATUS [00:00] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_MASK              0x00000001
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_SHIFT             0
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_DEFAULT           0x00000001
+
+/***************************************************************************
+ *TESTER_LATENCY - Memory Controller, Tester Latency Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: TESTER_LATENCY :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_MASK              0xffffff80
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_SHIFT             7
+
+/* MEMC_DDR_0 :: TESTER_LATENCY :: TLATENCY_SEL [06:00] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_MASK           0x0000007f
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_SHIFT          0
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE0 - Memory Controller, DATA_PINMAP_BYTE0_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE1 - Memory Controller, DATA_PINMAP_BYTE1_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE2 - Memory Controller, DATA_PINMAP_BYTE2_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE3 - Memory Controller, DATA_PINMAP_BYTE3_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_DDR3_RESET_PERIOD - Memory Controller, DDR3 DRAM reset Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: reserved0 [31:20] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_MASK      0xfff00000
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_SHIFT     20
+
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: DRAM_RESET_PERIOD [19:00] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_MASK 0x000fffff
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_SHIFT 0
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_DEFAULT 0x0000a8c0
+
+/***************************************************************************
+ *STAT_CONTROL - Statistics Control register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CONTROL :: reserved0 [31:09] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_MASK                0xfffffe00
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_SHIFT               9
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: COUNTER_MODE [08:08] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_SHIFT            8
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_DEFAULT          0x00000000
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT    1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_NORMAL           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: STAT_ENABLE [07:07] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_SHIFT             7
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DEFAULT           0x00000000
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_ENABLE            1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DISABLE           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: CLIENT_ID [06:00] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_MASK                0x0000007f
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_TIMER - Statistics Timer
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TIMER :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_MASK                      0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_SHIFT                     0
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_MASK                   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_ALL - CAS Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_PENALTY_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_MASK            0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_SHIFT           0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_DEFAULT           0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_MASK         0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT        0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_REFRESH - Total number of refreshes issuedr.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_REFRESH :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_0 - CAS cycle count register for client 0.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_1 - CAS cycle count register for client 1.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_2 - CAS cycle count register for client 2.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_3 - CAS cycle count register for client 3.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_4 - CAS cycle count register for client 4.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_5 - CAS cycle count register for client 5.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_6 - CAS cycle count register for client 6.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_7 - CAS cycle count register for client 7.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_8 - CAS cycle count register for client 8.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_9 - CAS cycle count register for client 9.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_10 - CAS cycle count register for client 10.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_11 - CAS cycle count register for client 11.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_12 - CAS cycle count register for client 12.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_13 - CAS cycle count register for client 13.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_14 - CAS cycle count register for client 14.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_15 - CAS cycle count register for client 15.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_16 - CAS cycle count register for client 16.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_17 - CAS cycle count register for client 17.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_18 - CAS cycle count register for client 18.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_19 - CAS cycle count register for client 19.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_20 - CAS cycle count register for client 20.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_21 - CAS cycle count register for client 21.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_22 - CAS cycle count register for client 22.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_23 - CAS cycle count register for client 23.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_24 - CAS cycle count register for client 24.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_25 - CAS cycle count register for client 25.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_26 - CAS cycle count register for client 26.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_27 - CAS cycle count register for client 27.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_28 - CAS cycle count register for client 28.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_29 - CAS cycle count register for client 29.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_30 - CAS cycle count register for client 30.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_31 - CAS cycle count register for client 31.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_32 - CAS cycle count register for client 32.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_33 - CAS cycle count register for client 33.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_34 - CAS cycle count register for client 34.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_35 - CAS cycle count register for client 35.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_36 - CAS cycle count register for client 36.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_37 - CAS cycle count register for client 37.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_38 - CAS cycle count register for client 38.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_39 - CAS cycle count register for client 39.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_40 - CAS cycle count register for client 40.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_41 - CAS cycle count register for client 41.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_42 - CAS cycle count register for client 42.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_43 - CAS cycle count register for client 43.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_44 - CAS cycle count register for client 44.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_45 - CAS cycle count register for client 45.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_46 - CAS cycle count register for client 46.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_47 - CAS cycle count register for client 47.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_48 - CAS cycle count register for client 48.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_49 - CAS cycle count register for client 49.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_50 - CAS cycle count register for client 50.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_51 - CAS cycle count register for client 51.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_52 - CAS cycle count register for client 52.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_53 - CAS cycle count register for client 53.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_54 - CAS cycle count register for client 54.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_55 - CAS cycle count register for client 55.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_56 - CAS cycle count register for client 56.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_57 - CAS cycle count register for client 57.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_58 - CAS cycle count register for client 58.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_59 - CAS cycle count register for client 59.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_60 - CAS cycle count register for client 60.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_61 - CAS cycle count register for client 61.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_62 - CAS cycle count register for client 62.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_63 - CAS cycle count register for client 63.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_64 - CAS cycle count register for client 64.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_65 - CAS cycle count register for client 65.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_66 - CAS cycle count register for client 66.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_67 - CAS cycle count register for client 67.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_68 - CAS cycle count register for client 68.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_69 - CAS cycle count register for client 69.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_70 - CAS cycle count register for client 70.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_71 - CAS cycle count register for client 71.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_72 - CAS cycle count register for client 72.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_73 - CAS cycle count register for client 73.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_74 - CAS cycle count register for client 74.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_75 - CAS cycle count register for client 75.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_76 - CAS cycle count register for client 76.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_77 - CAS cycle count register for client 77.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_78 - CAS cycle count register for client 78.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_79 - CAS cycle count register for client 79.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_80 - CAS cycle count register for client 80.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_81 - CAS cycle count register for client 81.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_82 - CAS cycle count register for client 82.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_83 - CAS cycle count register for client 83.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_84 - CAS cycle count register for client 84.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_85 - CAS cycle count register for client 85.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_86 - CAS cycle count register for client 86.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_87 - CAS cycle count register for client 87.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_88 - CAS cycle count register for client 88.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_89 - CAS cycle count register for client 89.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_90 - CAS cycle count register for client 90.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_91 - CAS cycle count register for client 91.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_92 - CAS cycle count register for client 92.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_93 - CAS cycle count register for client 93.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_94 - CAS cycle count register for client 94.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_95 - CAS cycle count register for client 95.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_96 - CAS cycle count register for client 96.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_97 - CAS cycle count register for client 97.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_98 - CAS cycle count register for client 98.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_99 - CAS cycle count register for client 99.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_100 - CAS cycle count register for client 100.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_101 - CAS cycle count register for client 101.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_102 - CAS cycle count register for client 102.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_103 - CAS cycle count register for client 103.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_104 - CAS cycle count register for client 104.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_105 - CAS cycle count register for client 105.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_106 - CAS cycle count register for client 106.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_107 - CAS cycle count register for client 107.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_108 - CAS cycle count register for client 108.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_109 - CAS cycle count register for client 109.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_110 - CAS cycle count register for client 110.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_111 - CAS cycle count register for client 111.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_112 - CAS cycle count register for client 112.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_113 - CAS cycle count register for client 113.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_114 - CAS cycle count register for client 114.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_115 - CAS cycle count register for client 115.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_116 - CAS cycle count register for client 116.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_117 - CAS cycle count register for client 117.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_118 - CAS cycle count register for client 118.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_119 - CAS cycle count register for client 119.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_120 - CAS cycle count register for client 120.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_121 - CAS cycle count register for client 121.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_122 - CAS cycle count register for client 122.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_123 - CAS cycle count register for client 123.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_124 - CAS cycle count register for client 124.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_125 - CAS cycle count register for client 125.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_126 - CAS cycle count register for client 126.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_127 - CAS cycle count register for client 127.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_DEFAULT             0xffffffff
+
+/***************************************************************************
+ *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT    0xffffffff
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_CONTROL - MEMSYS Auto Init Control.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: reserved0 [31:10] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_MASK    0xfffffc00
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_SHIFT   10
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_DIVIDER [09:09] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_MASK 0x00000200
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_SHIFT 9
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_VDL_CALIB_AUTO_INIT [08:08] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_MASK 0x00000100
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_SHIFT 8
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_DRAM_INIT_DONE_SET [07:07] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_MASK 0x00000080
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_SHIFT 7
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_RESET [06:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_MASK 0x00000040
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_SET [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_READY_SET [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_AUTO_INIT_ACTIVE_RESET [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_MASK 0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_SHIFT 3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: SKIP_PHY_AUTO_INIT [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: MEMSYS_AUTO_INIT_START [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_STATUS - MEMSYS Auto Init Status.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_MASK     0xfffff000
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_SHIFT    12
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMC_AUTO_INIT_STATES [11:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_MASK 0x00000fc0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: AUTO_INIT_ACTIVE [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_STRAP_VALID [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_READY [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_MASK     0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_SHIFT    3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_DEFAULT  0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: DRAM_INIT_DONE [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_FAIL [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHY_VDL_CALIB_AUTO_INIT_OVERRIDE - PHY VDL calibrate override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PHY_VDL_CALIB_AUTO_INIT_OVERRIDE :: PHY_VDL_CALIB_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_DEFAULT 0x10000000
+
+/***************************************************************************
+ *SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE - SHIM PLL pndiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_PNDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_DEFAULT 0x23b00000
+
+/***************************************************************************
+ *SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE - SHIM PLL mdiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_MDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_DEFAULT 0x00001003
+
+/***************************************************************************
+ *DYN_VDL_CMD_DLY - Dynamic VDL shmoo command delay.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_MASK             0xfffff000
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_SHIFT            12
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: END_CAS_DLY [11:06] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_MASK           0x00000fc0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_SHIFT          6
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_DEFAULT        0x00000000
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: START_CAS_DLY [05:00] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_MASK         0x0000003f
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_SHIFT        0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_DEFAULT      0x00000000
+
+#endif /* #ifndef BCHP_MEMC_DDR_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_memc_ddr_1.h b/include/linux/brcmstb/7425b0/bchp_memc_ddr_1.h
new file mode 100644
index 0000000..0dd2407
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_memc_ddr_1.h
@@ -0,0 +1,2665 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Apr 11 13:43:31 2011
+ *                 MD5 Checksum         8cf142ad25caa9f873c54e8bb2bb1755
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7425/rdb/b0/bchp_memc_ddr_1.h $
+ * 
+ * Hydra_Software_Devel/2   4/12/11 9:00a vanessah
+ * SW7425-112: Update rdb files for 7425 B0.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR_1_H__
+#define BCHP_MEMC_DDR_1_H__
+
+/***************************************************************************
+ *MEMC_DDR_1 - Memory Controller Sequencer (DDR Param/Control) Registers 1
+ ***************************************************************************/
+#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG            0x003c2000 /* Memory Controller Mode-Configuration Register. */
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL          0x003c2004 /* Dram iniitialization control */
+#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS         0x003c2008 /* Dram iniitialization status */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0              0x003c200c /* Dram Mode0 register */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1              0x003c2010 /* Dram Mode1 register */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2              0x003c2014 /* Dram Mode2 register */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3              0x003c2018 /* Dram Mode3 register */
+#define BCHP_MEMC_DDR_1_PPD_CONFIG               0x003c201c /* Precharge power down mode configuration register */
+#define BCHP_MEMC_DDR_1_SRPD_CONFIG              0x003c2020 /* Self-refresh power down mode configuration register */
+#define BCHP_MEMC_DDR_1_SSPD_CMD                 0x003c2024 /* Software standby power down mode */
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS        0x003c2028 /* Power down status */
+#define BCHP_MEMC_DDR_1_WARM_BOOT                0x003c202c /* Warm boot control registers */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0            0x003c2030 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_1            0x003c2034 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_2            0x003c2038 /* Read to Write & write to read timing register */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3            0x003c203c /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4            0x003c2040 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5            0x003c2044 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_1_CNTRLR_START_SEQ         0x003c2048 /* Memory Controller Sequencer Enable */
+#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT        0x003c204c /* Memory Controller , state machine timeout register. */
+#define BCHP_MEMC_DDR_1_BANK_STATUS              0x003c2050 /* Memory Controller, Bank Status Register. */
+#define BCHP_MEMC_DDR_1_TESTER_LATENCY           0x003c2054 /* Memory Controller, Tester Latency Register. */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0               0x003c2058 /* Memory Controller, DATA_PINMAP_BYTE0_SEL Register. */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1               0x003c205c /* Memory Controller, DATA_PINMAP_BYTE1_SEL Register. */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2               0x003c2060 /* Memory Controller, DATA_PINMAP_BYTE2_SEL Register. */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3               0x003c2064 /* Memory Controller, DATA_PINMAP_BYTE3_SEL Register. */
+#define BCHP_MEMC_DDR_1_DRAM_DDR3_RESET_PERIOD   0x003c2068 /* Memory Controller, DDR3 DRAM reset Register. */
+#define BCHP_MEMC_DDR_1_STAT_CONTROL             0x003c206c /* Statistics Control register */
+#define BCHP_MEMC_DDR_1_STAT_TIMER               0x003c2070 /* Statistics Timer */
+#define BCHP_MEMC_DDR_1_STAT_IDLE_NOP            0x003c2074 /* DRAM Idle_NOP Cycle Count Register. */
+#define BCHP_MEMC_DDR_1_STAT_MAX_IDLE_NOP        0x003c2078 /* Maximum DRAM idle_NOP cycle count register. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_ALL             0x003c207c /* CAS Count Register. */
+#define BCHP_MEMC_DDR_1_STAT_MAX_CAS_ALL         0x003c2080 /* Maximum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_1_STAT_PENALTY_ALL         0x003c2084 /* DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_CYCLES_ALL 0x003c2088 /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_1_STAT_TRANS_READ_ALL      0x003c208c /* Number of overall system memory read transactions. */
+#define BCHP_MEMC_DDR_1_STAT_TRANS_WRITE_ALL     0x003c2090 /* Number of overall system memory write transactions. */
+#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_ALL       0x003c2094 /* Maximum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_ALL       0x003c2098 /* Minimum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_CAS  0x003c209c /* Service CAS Cycle Count register. */
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CAS 0x003c20a0 /* Maximum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CAS 0x003c20a4 /* Minimum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_INTR_PENALTY 0x003c20a8 /* Service Intra DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_POST_PENALTY 0x003c20ac /* Service Post DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CYCLES 0x003c20b0 /* Maximum service cycle count register. */
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CYCLES 0x003c20b4 /* Minimum service cycle count register. */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_READ 0x003c20b8 /* Service Read Transaction Count register. */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_WRITE 0x003c20bc /* Service Write Transaction Count register. */
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_TRANS 0x003c20c0 /* Maximum service Transaction count register. */
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_TRANS 0x003c20c4 /* Minimum service cycle Transaction register. */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_LATENCY 0x003c20c8 /* Service Latency Count register. */
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_LATENCY 0x003c20cc /* Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_LATENCY 0x003c20d0 /* Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x003c20d4 /* Absolute Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x003c20d8 /* Absolute Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_1_STAT_REFRESH             0x003c20dc /* Total number of refreshes issuedr. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_0        0x003c20e0 /* CAS cycle count register for client 0. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_1        0x003c20e4 /* CAS cycle count register for client 1. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_2        0x003c20e8 /* CAS cycle count register for client 2. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_3        0x003c20ec /* CAS cycle count register for client 3. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_4        0x003c20f0 /* CAS cycle count register for client 4. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_5        0x003c20f4 /* CAS cycle count register for client 5. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_6        0x003c20f8 /* CAS cycle count register for client 6. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_7        0x003c20fc /* CAS cycle count register for client 7. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_8        0x003c2100 /* CAS cycle count register for client 8. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_9        0x003c2104 /* CAS cycle count register for client 9. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_10       0x003c2108 /* CAS cycle count register for client 10. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_11       0x003c210c /* CAS cycle count register for client 11. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_12       0x003c2110 /* CAS cycle count register for client 12. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_13       0x003c2114 /* CAS cycle count register for client 13. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_14       0x003c2118 /* CAS cycle count register for client 14. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_15       0x003c211c /* CAS cycle count register for client 15. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_16       0x003c2120 /* CAS cycle count register for client 16. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_17       0x003c2124 /* CAS cycle count register for client 17. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_18       0x003c2128 /* CAS cycle count register for client 18. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_19       0x003c212c /* CAS cycle count register for client 19. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_20       0x003c2130 /* CAS cycle count register for client 20. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_21       0x003c2134 /* CAS cycle count register for client 21. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_22       0x003c2138 /* CAS cycle count register for client 22. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_23       0x003c213c /* CAS cycle count register for client 23. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_24       0x003c2140 /* CAS cycle count register for client 24. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_25       0x003c2144 /* CAS cycle count register for client 25. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_26       0x003c2148 /* CAS cycle count register for client 26. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_27       0x003c214c /* CAS cycle count register for client 27. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_28       0x003c2150 /* CAS cycle count register for client 28. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_29       0x003c2154 /* CAS cycle count register for client 29. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_30       0x003c2158 /* CAS cycle count register for client 30. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_31       0x003c215c /* CAS cycle count register for client 31. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_32       0x003c2160 /* CAS cycle count register for client 32. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_33       0x003c2164 /* CAS cycle count register for client 33. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_34       0x003c2168 /* CAS cycle count register for client 34. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_35       0x003c216c /* CAS cycle count register for client 35. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_36       0x003c2170 /* CAS cycle count register for client 36. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_37       0x003c2174 /* CAS cycle count register for client 37. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_38       0x003c2178 /* CAS cycle count register for client 38. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_39       0x003c217c /* CAS cycle count register for client 39. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_40       0x003c2180 /* CAS cycle count register for client 40. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_41       0x003c2184 /* CAS cycle count register for client 41. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_42       0x003c2188 /* CAS cycle count register for client 42. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_43       0x003c218c /* CAS cycle count register for client 43. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_44       0x003c2190 /* CAS cycle count register for client 44. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_45       0x003c2194 /* CAS cycle count register for client 45. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_46       0x003c2198 /* CAS cycle count register for client 46. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_47       0x003c219c /* CAS cycle count register for client 47. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_48       0x003c21a0 /* CAS cycle count register for client 48. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_49       0x003c21a4 /* CAS cycle count register for client 49. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_50       0x003c21a8 /* CAS cycle count register for client 50. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_51       0x003c21ac /* CAS cycle count register for client 51. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_52       0x003c21b0 /* CAS cycle count register for client 52. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_53       0x003c21b4 /* CAS cycle count register for client 53. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_54       0x003c21b8 /* CAS cycle count register for client 54. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_55       0x003c21bc /* CAS cycle count register for client 55. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_56       0x003c21c0 /* CAS cycle count register for client 56. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_57       0x003c21c4 /* CAS cycle count register for client 57. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_58       0x003c21c8 /* CAS cycle count register for client 58. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_59       0x003c21cc /* CAS cycle count register for client 59. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_60       0x003c21d0 /* CAS cycle count register for client 60. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_61       0x003c21d4 /* CAS cycle count register for client 61. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_62       0x003c21d8 /* CAS cycle count register for client 62. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_63       0x003c21dc /* CAS cycle count register for client 63. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_64       0x003c21e0 /* CAS cycle count register for client 64. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_65       0x003c21e4 /* CAS cycle count register for client 65. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_66       0x003c21e8 /* CAS cycle count register for client 66. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_67       0x003c21ec /* CAS cycle count register for client 67. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_68       0x003c21f0 /* CAS cycle count register for client 68. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_69       0x003c21f4 /* CAS cycle count register for client 69. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_70       0x003c21f8 /* CAS cycle count register for client 70. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_71       0x003c21fc /* CAS cycle count register for client 71. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_72       0x003c2200 /* CAS cycle count register for client 72. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_73       0x003c2204 /* CAS cycle count register for client 73. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_74       0x003c2208 /* CAS cycle count register for client 74. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_75       0x003c220c /* CAS cycle count register for client 75. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_76       0x003c2210 /* CAS cycle count register for client 76. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_77       0x003c2214 /* CAS cycle count register for client 77. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_78       0x003c2218 /* CAS cycle count register for client 78. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_79       0x003c221c /* CAS cycle count register for client 79. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_80       0x003c2220 /* CAS cycle count register for client 80. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_81       0x003c2224 /* CAS cycle count register for client 81. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_82       0x003c2228 /* CAS cycle count register for client 82. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_83       0x003c222c /* CAS cycle count register for client 83. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_84       0x003c2230 /* CAS cycle count register for client 84. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_85       0x003c2234 /* CAS cycle count register for client 85. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_86       0x003c2238 /* CAS cycle count register for client 86. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_87       0x003c223c /* CAS cycle count register for client 87. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_88       0x003c2240 /* CAS cycle count register for client 88. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_89       0x003c2244 /* CAS cycle count register for client 89. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_90       0x003c2248 /* CAS cycle count register for client 90. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_91       0x003c224c /* CAS cycle count register for client 91. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_92       0x003c2250 /* CAS cycle count register for client 92. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_93       0x003c2254 /* CAS cycle count register for client 93. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_94       0x003c2258 /* CAS cycle count register for client 94. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_95       0x003c225c /* CAS cycle count register for client 95. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_96       0x003c2260 /* CAS cycle count register for client 96. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_97       0x003c2264 /* CAS cycle count register for client 97. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_98       0x003c2268 /* CAS cycle count register for client 98. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_99       0x003c226c /* CAS cycle count register for client 99. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_100      0x003c2270 /* CAS cycle count register for client 100. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_101      0x003c2274 /* CAS cycle count register for client 101. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_102      0x003c2278 /* CAS cycle count register for client 102. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_103      0x003c227c /* CAS cycle count register for client 103. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_104      0x003c2280 /* CAS cycle count register for client 104. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_105      0x003c2284 /* CAS cycle count register for client 105. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_106      0x003c2288 /* CAS cycle count register for client 106. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_107      0x003c228c /* CAS cycle count register for client 107. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_108      0x003c2290 /* CAS cycle count register for client 108. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_109      0x003c2294 /* CAS cycle count register for client 109. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_110      0x003c2298 /* CAS cycle count register for client 110. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_111      0x003c229c /* CAS cycle count register for client 111. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_112      0x003c22a0 /* CAS cycle count register for client 112. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_113      0x003c22a4 /* CAS cycle count register for client 113. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_114      0x003c22a8 /* CAS cycle count register for client 114. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_115      0x003c22ac /* CAS cycle count register for client 115. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_116      0x003c22b0 /* CAS cycle count register for client 116. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_117      0x003c22b4 /* CAS cycle count register for client 117. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_118      0x003c22b8 /* CAS cycle count register for client 118. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_119      0x003c22bc /* CAS cycle count register for client 119. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_120      0x003c22c0 /* CAS cycle count register for client 120. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_121      0x003c22c4 /* CAS cycle count register for client 121. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_122      0x003c22c8 /* CAS cycle count register for client 122. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_123      0x003c22cc /* CAS cycle count register for client 123. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_124      0x003c22d0 /* CAS cycle count register for client 124. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_125      0x003c22d4 /* CAS cycle count register for client 125. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_126      0x003c22d8 /* CAS cycle count register for client 126. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_127      0x003c22dc /* CAS cycle count register for client 127. */
+#define BCHP_MEMC_DDR_1_STAT_MIN_CAS_ALL         0x003c22e0 /* Minimum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_CYCLES_ALL 0x003c22e4 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL 0x003c22e8 /* MEMSYS Auto Init Control. */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS  0x003c22ec /* MEMSYS Auto Init Status. */
+#define BCHP_MEMC_DDR_1_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE 0x003c22f0 /* PHY VDL calibrate override from memc auto init. */
+#define BCHP_MEMC_DDR_1_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE 0x003c22f4 /* SHIM PLL pndiv override from memc auto init. */
+#define BCHP_MEMC_DDR_1_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE 0x003c22f8 /* SHIM PLL mdiv override from memc auto init. */
+#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY          0x003c22fc /* Dynamic VDL shmoo command delay. */
+
+/***************************************************************************
+ *CNTRLR_CONFIG - Memory Controller Mode-Configuration Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: CNTRLR_CONFIG :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_reserved0_MASK               0xfffffff8
+#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_reserved0_SHIFT              3
+
+/* MEMC_DDR_1 :: CNTRLR_CONFIG :: DEVICE_TECH [02:00] */
+#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DEVICE_TECH_MASK             0x00000007
+#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DEVICE_TECH_SHIFT            0
+#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DEVICE_TECH_DEFAULT          3
+
+/***************************************************************************
+ *DRAM_INIT_CNTRL - Dram iniitialization control
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_INIT_CNTRL :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_reserved0_MASK             0xfffffff8
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_reserved0_SHIFT            3
+
+/* MEMC_DDR_1 :: DRAM_INIT_CNTRL :: BYPASS_PHY_INIT_RDY [02:02] */
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_MASK   0x00000004
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_SHIFT  2
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_DEFAULT 0
+
+/* MEMC_DDR_1 :: DRAM_INIT_CNTRL :: DDR_TECH [01:01] */
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR_TECH_MASK              0x00000002
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR_TECH_SHIFT             1
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR_TECH_DEFAULT           1
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR_TECH_DDR2              0
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR_TECH_DDR3              1
+
+/* MEMC_DDR_1 :: DRAM_INIT_CNTRL :: DDR3_INIT_MODE [00:00] */
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR3_INIT_MODE_MASK        0x00000001
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR3_INIT_MODE_SHIFT       0
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR3_INIT_MODE_DEFAULT     0
+
+/***************************************************************************
+ *DRAM_INIT_STATUS - Dram iniitialization status
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_INIT_STATUS :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_reserved0_SHIFT           1
+
+/* MEMC_DDR_1 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_INIT_DONE_MASK            0x00000001
+#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_INIT_DONE_SHIFT           0
+#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_INIT_DONE_DEFAULT         0
+
+/***************************************************************************
+ *DRAM_MODE_0 - Dram Mode0 register
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_reserved0_SHIFT                16
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR2 :: PD_EXIT [12:12] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_PD_EXIT_MASK              0x00001000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_PD_EXIT_SHIFT             12
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_PD_EXIT_DEFAULT           0
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR2 :: WR [11:09] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_WR_DEFAULT                7
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR2 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_DLL_RST_DEFAULT           0
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR2 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_TEST_MODE_DEFAULT         0
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR2 :: CL [06:04] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_CL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_CL_SHIFT                  4
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_CL_DEFAULT                7
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR2 :: BT [03:03] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_BT_MASK                   0x00000008
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_BT_SHIFT                  3
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_BT_DEFAULT                0
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR2 :: BL [02:00] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_BL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_BL_DEFAULT                2
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK        0x00001000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT       12
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT     0
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_WR_DEFAULT                4
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT           0
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT         0
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_3_1_MASK               0x00000070
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_3_1_SHIFT              4
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT            4
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_RBT_MASK                  0x00000008
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_RBT_SHIFT                 3
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_RBT_DEFAULT               0
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_0_MASK                 0x00000004
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_0_SHIFT                2
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_0_DEFAULT              0
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_BL_MASK                   0x00000003
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_BL_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_MODE_1 - Dram Mode1 register
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_reserved0_SHIFT                16
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_Q_OFF_DEFAULT             0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: RDQS [11:11] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_RDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_RDQS_SHIFT                11
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_RDQS_DEFAULT              0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_RDQS_ENABLE               1
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_RDQS_DISABLE              0
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: DQSB [10:10] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DQSB_MASK                 0x00000400
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DQSB_SHIFT                10
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DQSB_DEFAULT              0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DQSB_ENABLE               0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DQSB_DISABLE              1
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: OCD_CAL [09:07] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_OCD_CAL_MASK              0x00000380
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_OCD_CAL_SHIFT             7
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_OCD_CAL_DEFAULT           0
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_ODT_CNTRL_1_DEFAULT       1
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: AL [05:03] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_AL_MASK                   0x00000038
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_AL_DEFAULT                6
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_ODT_CNTRL_0_DEFAULT       0
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: DRV_IMP [01:01] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DRV_IMP_MASK              0x00000002
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DRV_IMP_SHIFT             1
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DRV_IMP_DEFAULT           0
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DLL_EN_DEFAULT            0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DLL_EN_DISABLE            1
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT             0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_TDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_TDQS_SHIFT                11
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_TDQS_DEFAULT              0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_TDQS_ENABLE               1
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_TDQS_DISABLE              0
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_1_MASK             0x00000400
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_1_SHIFT            10
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_1_DEFAULT          0
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK          0x00000200
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT         9
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT       0
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_2_DEFAULT          0
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_WR_LEVEL_MASK             0x00000080
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT            7
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT          0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE           1
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE          0
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT       0
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK   0x00000020
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT  5
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_AL_MASK                   0x00000018
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_AL_DEFAULT                1
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT       1
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK   0x00000002
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT  1
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT            0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DLL_EN_DISABLE            1
+
+/***************************************************************************
+ *DRAM_MODE_2 - Dram Mode2 register
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_reserved0_SHIFT                16
+
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR2 :: unused_1 [12:08] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_unused_1_MASK             0x00001f00
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_unused_1_SHIFT            8
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_unused_1_DEFAULT          0
+
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR2 :: HT_SRF [07:07] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_HT_SRF_MASK               0x00000080
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_HT_SRF_SHIFT              7
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_HT_SRF_DEFAULT            0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_HT_SRF_ENABLE             1
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_HT_SRF_DISABLE            0
+
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR2 :: unused_2 [06:04] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_unused_2_MASK             0x00000070
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_unused_2_SHIFT            4
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_unused_2_DEFAULT          0
+
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR2 :: DCC_ENABLE [03:03] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_DCC_ENABLE_MASK           0x00000008
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_DCC_ENABLE_SHIFT          3
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_DCC_ENABLE_DEFAULT        0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_DCC_ENABLE_ENABLE         1
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_DCC_ENABLE_DISABLE        0
+
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR2 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_PASR_DEFAULT              0
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_1_MASK             0x00001800
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_1_SHIFT            11
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_1_DEFAULT          0
+
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WR_ODT_MASK               0x00000600
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WR_ODT_SHIFT              9
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT            1
+
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_2_DEFAULT          0
+
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_SRF_TR_MASK               0x00000080
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_SRF_TR_SHIFT              7
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT            0
+
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_AUTO_SR_MASK              0x00000040
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT             6
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT           1
+
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WCL_MASK                  0x00000038
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WCL_SHIFT                 3
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WCL_DEFAULT               1
+
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_PASR_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_MODE_3 - Dram Mode3 register
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_MODE_3 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_reserved0_SHIFT                16
+
+/* MEMC_DDR_1 :: DRAM_MODE_3 :: unused_0 [15:03] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_unused_0_MASK                  0x0000fff8
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_unused_0_SHIFT                 3
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_unused_0_DEFAULT               0
+
+/* union - case DDR2 [02:00] */
+/* MEMC_DDR_1 :: DRAM_MODE_3 :: DDR2 :: unused_1 [02:00] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR2_unused_1_MASK             0x00000007
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR2_unused_1_SHIFT            0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR2_unused_1_DEFAULT          0
+
+/* union - case DDR3 [02:00] */
+/* MEMC_DDR_1 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_MASK                  0x00000004
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_SHIFT                 2
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_DEFAULT               0
+
+/* MEMC_DDR_1 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_LOC_MASK              0x00000003
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT             0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT           0
+
+/***************************************************************************
+ *PPD_CONFIG - Precharge power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_1 :: PPD_CONFIG :: reserved0 [31:13] */
+#define BCHP_MEMC_DDR_1_PPD_CONFIG_reserved0_MASK                  0xffffe000
+#define BCHP_MEMC_DDR_1_PPD_CONFIG_reserved0_SHIFT                 13
+
+/* MEMC_DDR_1 :: PPD_CONFIG :: PPD_EN [12:12] */
+#define BCHP_MEMC_DDR_1_PPD_CONFIG_PPD_EN_MASK                     0x00001000
+#define BCHP_MEMC_DDR_1_PPD_CONFIG_PPD_EN_SHIFT                    12
+#define BCHP_MEMC_DDR_1_PPD_CONFIG_PPD_EN_DEFAULT                  0
+
+/* MEMC_DDR_1 :: PPD_CONFIG :: INACT_COUNT [11:00] */
+#define BCHP_MEMC_DDR_1_PPD_CONFIG_INACT_COUNT_MASK                0x00000fff
+#define BCHP_MEMC_DDR_1_PPD_CONFIG_INACT_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_1_PPD_CONFIG_INACT_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *SRPD_CONFIG - Self-refresh power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_1 :: SRPD_CONFIG :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_1_SRPD_CONFIG_reserved0_MASK                 0xfffe0000
+#define BCHP_MEMC_DDR_1_SRPD_CONFIG_reserved0_SHIFT                17
+
+/* MEMC_DDR_1 :: SRPD_CONFIG :: SRPD_EN [16:16] */
+#define BCHP_MEMC_DDR_1_SRPD_CONFIG_SRPD_EN_MASK                   0x00010000
+#define BCHP_MEMC_DDR_1_SRPD_CONFIG_SRPD_EN_SHIFT                  16
+#define BCHP_MEMC_DDR_1_SRPD_CONFIG_SRPD_EN_DEFAULT                0
+
+/* MEMC_DDR_1 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
+#define BCHP_MEMC_DDR_1_SRPD_CONFIG_INACT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_1_SRPD_CONFIG_INACT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_SRPD_CONFIG_INACT_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *SSPD_CMD - Software standby power down mode
+ ***************************************************************************/
+/* MEMC_DDR_1 :: SSPD_CMD :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_1_SSPD_CMD_reserved0_MASK                    0xfffffffe
+#define BCHP_MEMC_DDR_1_SSPD_CMD_reserved0_SHIFT                   1
+
+/* MEMC_DDR_1 :: SSPD_CMD :: SSPD [00:00] */
+#define BCHP_MEMC_DDR_1_SSPD_CMD_SSPD_MASK                         0x00000001
+#define BCHP_MEMC_DDR_1_SSPD_CMD_SSPD_SHIFT                        0
+#define BCHP_MEMC_DDR_1_SSPD_CMD_SSPD_DEFAULT                      0
+
+/***************************************************************************
+ *POWER_DOWN_STATUS - Power down status
+ ***************************************************************************/
+/* MEMC_DDR_1 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_reserved0_MASK           0xfffffff8
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_reserved0_SHIFT          3
+
+/* MEMC_DDR_1 :: POWER_DOWN_STATUS :: SSPD [02:02] */
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SSPD_MASK                0x00000004
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SSPD_SHIFT               2
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SSPD_DEFAULT             0
+
+/* MEMC_DDR_1 :: POWER_DOWN_STATUS :: SRPD [01:01] */
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SRPD_MASK                0x00000002
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SRPD_SHIFT               1
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SRPD_DEFAULT             0
+
+/* MEMC_DDR_1 :: POWER_DOWN_STATUS :: PPD [00:00] */
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_PPD_MASK                 0x00000001
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_PPD_SHIFT                0
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_PPD_DEFAULT              0
+
+/***************************************************************************
+ *WARM_BOOT - Warm boot control registers
+ ***************************************************************************/
+/* MEMC_DDR_1 :: WARM_BOOT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_1_WARM_BOOT_reserved0_MASK                   0xfffffffe
+#define BCHP_MEMC_DDR_1_WARM_BOOT_reserved0_SHIFT                  1
+
+/* MEMC_DDR_1 :: WARM_BOOT :: WARM_BOOT [00:00] */
+#define BCHP_MEMC_DDR_1_WARM_BOOT_WARM_BOOT_MASK                   0x00000001
+#define BCHP_MEMC_DDR_1_WARM_BOOT_WARM_BOOT_SHIFT                  0
+#define BCHP_MEMC_DDR_1_WARM_BOOT_WARM_BOOT_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_TIMING_0 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRRD_NOP_MASK                0xff000000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRRD_NOP_SHIFT               24
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRRD_NOP_DEFAULT             6
+
+/* MEMC_DDR_1 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRCD_NOP_MASK                0x00ff0000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRCD_NOP_SHIFT               16
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRCD_NOP_DEFAULT             8
+
+/* MEMC_DDR_1 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRP_NOP_MASK                 0x0000ff00
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRP_NOP_SHIFT                8
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRP_NOP_DEFAULT              8
+
+/* MEMC_DDR_1 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRAS_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRAS_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRAS_NOP_DEFAULT             20
+
+/***************************************************************************
+ *DRAM_TIMING_1 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_TIMING_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_reserved0_SHIFT              16
+
+/* MEMC_DDR_1 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TFAW_NOP_MASK                0x0000ff00
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TFAW_NOP_SHIFT               8
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TFAW_NOP_DEFAULT             27
+
+/* MEMC_DDR_1 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TRTP_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TRTP_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TRTP_NOP_DEFAULT             4
+
+/***************************************************************************
+ *DRAM_TIMING_2 - Read to Write & write to read timing register
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_TIMING_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_reserved0_SHIFT              16
+
+/* MEMC_DDR_1 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_WR2RD_NOP_MASK               0x0000ff00
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_WR2RD_NOP_SHIFT              8
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_WR2RD_NOP_DEFAULT            14
+
+/* MEMC_DDR_1 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_RD2WR_NOP_MASK               0x000000ff
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_RD2WR_NOP_SHIFT              0
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_RD2WR_NOP_DEFAULT            9
+
+/***************************************************************************
+ *DRAM_TIMING_3 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_TIMING_3 :: reserved0 [31:24] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_reserved0_MASK               0xff000000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_reserved0_SHIFT              24
+
+/* MEMC_DDR_1 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT      12
+
+/* MEMC_DDR_1 :: DRAM_TIMING_3 :: POWERUP_CKE_DELAY [18:10] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_POWERUP_CKE_DELAY_MASK       0x0007fc00
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_POWERUP_CKE_DELAY_SHIFT      10
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_POWERUP_CKE_DELAY_DEFAULT    94
+
+/* MEMC_DDR_1 :: DRAM_TIMING_3 :: DLL_LOCK_DELAY [09:00] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_DLL_LOCK_DELAY_MASK          0x000003ff
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_DLL_LOCK_DELAY_SHIFT         0
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_DLL_LOCK_DELAY_DEFAULT       512
+
+/***************************************************************************
+ *DRAM_TIMING_4 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_TIMING_4 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_reserved0_SHIFT              29
+
+/* MEMC_DDR_1 :: DRAM_TIMING_4 :: PRECHARGE_ALL_DELAY [28:24] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_MASK     0x1f000000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_SHIFT    24
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_DEFAULT  8
+
+/* MEMC_DDR_1 :: DRAM_TIMING_4 :: LOAD_MODE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_LOAD_MODE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_LOAD_MODE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_LOAD_MODE_DELAY_DEFAULT      12
+
+/* MEMC_DDR_1 :: DRAM_TIMING_4 :: REFRESH_DELAY [18:10] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_REFRESH_DELAY_MASK           0x0007fc00
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_REFRESH_DELAY_SHIFT          10
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT        88
+
+/* MEMC_DDR_1 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [09:00] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_ZQCALIB_DELAY_MASK           0x000003ff
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT          0
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT        512
+
+/***************************************************************************
+ *DRAM_TIMING_5 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_TIMING_5 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_reserved0_SHIFT              29
+
+/* MEMC_DDR_1 :: DRAM_TIMING_5 :: CKE_ASSETION_DELAY [28:19] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_ASSETION_DELAY_MASK      0x1ff80000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_ASSETION_DELAY_SHIFT     19
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_ASSETION_DELAY_DEFAULT   261
+
+/* MEMC_DDR_1 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [18:15] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK           0x00078000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT          15
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT        3
+
+/* MEMC_DDR_1 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [14:10] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK         0x00007c00
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT        10
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT      13
+
+/* MEMC_DDR_1 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [09:00] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK      0x000003ff
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT     0
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT   512
+
+/***************************************************************************
+ *CNTRLR_START_SEQ - Memory Controller Sequencer Enable
+ ***************************************************************************/
+/* MEMC_DDR_1 :: CNTRLR_START_SEQ :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_1_CNTRLR_START_SEQ_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_1_CNTRLR_START_SEQ_reserved0_SHIFT           1
+
+/* MEMC_DDR_1 :: CNTRLR_START_SEQ :: START_SEQ [00:00] */
+#define BCHP_MEMC_DDR_1_CNTRLR_START_SEQ_START_SEQ_MASK            0x00000001
+#define BCHP_MEMC_DDR_1_CNTRLR_START_SEQ_START_SEQ_SHIFT           0
+#define BCHP_MEMC_DDR_1_CNTRLR_START_SEQ_START_SEQ_DEFAULT         0
+
+/***************************************************************************
+ *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_reserved0_MASK           0xfffe0000
+#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_reserved0_SHIFT          17
+
+/* MEMC_DDR_1 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
+#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_ENABLE_MASK              0x00010000
+#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT             16
+#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT           0
+
+/* MEMC_DDR_1 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
+#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT            65535
+
+/***************************************************************************
+ *BANK_STATUS - Memory Controller, Bank Status Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: BANK_STATUS :: reserved0 [31:08] */
+#define BCHP_MEMC_DDR_1_BANK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_MEMC_DDR_1_BANK_STATUS_reserved0_SHIFT                8
+
+/* MEMC_DDR_1 :: BANK_STATUS :: BANK7_STATUS [07:07] */
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK7_STATUS_MASK              0x00000080
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK7_STATUS_SHIFT             7
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK7_STATUS_DEFAULT           1
+
+/* MEMC_DDR_1 :: BANK_STATUS :: BANK6_STATUS [06:06] */
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK6_STATUS_MASK              0x00000040
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK6_STATUS_SHIFT             6
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK6_STATUS_DEFAULT           1
+
+/* MEMC_DDR_1 :: BANK_STATUS :: BANK5_STATUS [05:05] */
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK5_STATUS_MASK              0x00000020
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK5_STATUS_SHIFT             5
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK5_STATUS_DEFAULT           1
+
+/* MEMC_DDR_1 :: BANK_STATUS :: BANK4_STATUS [04:04] */
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK4_STATUS_MASK              0x00000010
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK4_STATUS_SHIFT             4
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK4_STATUS_DEFAULT           1
+
+/* MEMC_DDR_1 :: BANK_STATUS :: BANK3_STATUS [03:03] */
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK3_STATUS_MASK              0x00000008
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK3_STATUS_SHIFT             3
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK3_STATUS_DEFAULT           1
+
+/* MEMC_DDR_1 :: BANK_STATUS :: BANK2_STATUS [02:02] */
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK2_STATUS_MASK              0x00000004
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK2_STATUS_SHIFT             2
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK2_STATUS_DEFAULT           1
+
+/* MEMC_DDR_1 :: BANK_STATUS :: BANK1_STATUS [01:01] */
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK1_STATUS_MASK              0x00000002
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK1_STATUS_SHIFT             1
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK1_STATUS_DEFAULT           1
+
+/* MEMC_DDR_1 :: BANK_STATUS :: BANK0_STATUS [00:00] */
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK0_STATUS_MASK              0x00000001
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK0_STATUS_SHIFT             0
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK0_STATUS_DEFAULT           1
+
+/***************************************************************************
+ *TESTER_LATENCY - Memory Controller, Tester Latency Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: TESTER_LATENCY :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR_1_TESTER_LATENCY_reserved0_MASK              0xffffff80
+#define BCHP_MEMC_DDR_1_TESTER_LATENCY_reserved0_SHIFT             7
+
+/* MEMC_DDR_1 :: TESTER_LATENCY :: TLATENCY_SEL [06:00] */
+#define BCHP_MEMC_DDR_1_TESTER_LATENCY_TLATENCY_SEL_MASK           0x0000007f
+#define BCHP_MEMC_DDR_1_TESTER_LATENCY_TLATENCY_SEL_SHIFT          0
+#define BCHP_MEMC_DDR_1_TESTER_LATENCY_TLATENCY_SEL_DEFAULT        0
+
+/***************************************************************************
+ *DTPM_BYTE0 - Memory Controller, DATA_PINMAP_BYTE0_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved0_SHIFT                 31
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved1_SHIFT                 27
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved2_SHIFT                 23
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved3_SHIFT                 19
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved4_SHIFT                 15
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved5_SHIFT                 11
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved6_SHIFT                 7
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved7_SHIFT                 3
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE1 - Memory Controller, DATA_PINMAP_BYTE1_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved0_SHIFT                 31
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved1_SHIFT                 27
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved2_SHIFT                 23
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved3_SHIFT                 19
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved4_SHIFT                 15
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved5_SHIFT                 11
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved6_SHIFT                 7
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved7_SHIFT                 3
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE2 - Memory Controller, DATA_PINMAP_BYTE2_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved0_SHIFT                 31
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved1_SHIFT                 27
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved2_SHIFT                 23
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved3_SHIFT                 19
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved4_SHIFT                 15
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved5_SHIFT                 11
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved6_SHIFT                 7
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved7_SHIFT                 3
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE3 - Memory Controller, DATA_PINMAP_BYTE3_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved0_SHIFT                 31
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved1_SHIFT                 27
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved2_SHIFT                 23
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved3_SHIFT                 19
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved4_SHIFT                 15
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved5_SHIFT                 11
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved6_SHIFT                 7
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved7_SHIFT                 3
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_DDR3_RESET_PERIOD - Memory Controller, DDR3 DRAM reset Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_DDR3_RESET_PERIOD :: reserved0 [31:20] */
+#define BCHP_MEMC_DDR_1_DRAM_DDR3_RESET_PERIOD_reserved0_MASK      0xfff00000
+#define BCHP_MEMC_DDR_1_DRAM_DDR3_RESET_PERIOD_reserved0_SHIFT     20
+
+/* MEMC_DDR_1 :: DRAM_DDR3_RESET_PERIOD :: DRAM_RESET_PERIOD [19:00] */
+#define BCHP_MEMC_DDR_1_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_MASK 0x000fffff
+#define BCHP_MEMC_DDR_1_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_SHIFT 0
+#define BCHP_MEMC_DDR_1_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_DEFAULT 43200
+
+/***************************************************************************
+ *STAT_CONTROL - Statistics Control register
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CONTROL :: reserved0 [31:09] */
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_reserved0_MASK                0xfffffe00
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_reserved0_SHIFT               9
+
+/* MEMC_DDR_1 :: STAT_CONTROL :: COUNTER_MODE [08:08] */
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_COUNTER_MODE_MASK             0x00000100
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_COUNTER_MODE_SHIFT            8
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_COUNTER_MODE_DEFAULT          0
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT    1
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_COUNTER_MODE_NORMAL           0
+
+/* MEMC_DDR_1 :: STAT_CONTROL :: STAT_ENABLE [07:07] */
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_STAT_ENABLE_MASK              0x00000080
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_STAT_ENABLE_SHIFT             7
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_STAT_ENABLE_DEFAULT           0
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_STAT_ENABLE_ENABLE            1
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_STAT_ENABLE_DISABLE           0
+
+/* MEMC_DDR_1 :: STAT_CONTROL :: CLIENT_ID [06:00] */
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_CLIENT_ID_MASK                0x0000007f
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_CLIENT_ID_SHIFT               0
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_CLIENT_ID_DEFAULT             0
+
+/***************************************************************************
+ *STAT_TIMER - Statistics Timer
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_TIMER :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_TIMER_COUNT_MASK                      0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_TIMER_COUNT_SHIFT                     0
+#define BCHP_MEMC_DDR_1_STAT_TIMER_COUNT_DEFAULT                   0
+
+/***************************************************************************
+ *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_IDLE_NOP_COUNT_MASK                   0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_IDLE_NOP_COUNT_SHIFT                  0
+#define BCHP_MEMC_DDR_1_STAT_IDLE_NOP_COUNT_DEFAULT                0
+
+/***************************************************************************
+ *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MAX_IDLE_NOP_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MAX_IDLE_NOP_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_STAT_MAX_IDLE_NOP_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_ALL - CAS Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_ALL_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_ALL_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_1_STAT_CAS_ALL_COUNT_DEFAULT                 0
+
+/***************************************************************************
+ *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MAX_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MAX_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_1_STAT_MAX_CAS_ALL_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_PENALTY_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_PENALTY_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_PENALTY_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_1_STAT_PENALTY_ALL_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT    0
+
+/***************************************************************************
+ *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_TRANS_READ_ALL_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_TRANS_READ_ALL_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_TRANS_READ_ALL_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_TRANS_WRITE_ALL_COUNT_MASK            0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_TRANS_WRITE_ALL_COUNT_SHIFT           0
+#define BCHP_MEMC_DDR_1_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT         0
+
+/***************************************************************************
+ *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_ALL_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_ALL_COUNT_DEFAULT           4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_CAS_COUNT_MASK         0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT        0
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT      0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT  4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT  0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_REFRESH - Total number of refreshes issuedr.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_REFRESH :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_REFRESH_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_REFRESH_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_1_STAT_REFRESH_COUNT_DEFAULT                 0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_0 - CAS cycle count register for client 0.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_0_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_0_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_0_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_1 - CAS cycle count register for client 1.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_1_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_1_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_1_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_2 - CAS cycle count register for client 2.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_2_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_2_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_2_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_3 - CAS cycle count register for client 3.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_3_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_3_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_3_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_4 - CAS cycle count register for client 4.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_4_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_4_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_4_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_5 - CAS cycle count register for client 5.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_5_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_5_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_5_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_6 - CAS cycle count register for client 6.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_6_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_6_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_6_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_7 - CAS cycle count register for client 7.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_7_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_7_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_7_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_8 - CAS cycle count register for client 8.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_8_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_8_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_8_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_9 - CAS cycle count register for client 9.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_9_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_9_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_9_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_10 - CAS cycle count register for client 10.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_10_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_10_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_10_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_11 - CAS cycle count register for client 11.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_11_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_11_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_11_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_12 - CAS cycle count register for client 12.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_12_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_12_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_12_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_13 - CAS cycle count register for client 13.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_13_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_13_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_13_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_14 - CAS cycle count register for client 14.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_14_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_14_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_14_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_15 - CAS cycle count register for client 15.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_15_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_15_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_15_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_16 - CAS cycle count register for client 16.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_16_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_16_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_16_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_17 - CAS cycle count register for client 17.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_17_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_17_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_17_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_18 - CAS cycle count register for client 18.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_18_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_18_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_18_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_19 - CAS cycle count register for client 19.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_19_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_19_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_19_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_20 - CAS cycle count register for client 20.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_20_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_20_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_20_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_21 - CAS cycle count register for client 21.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_21_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_21_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_21_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_22 - CAS cycle count register for client 22.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_22_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_22_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_22_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_23 - CAS cycle count register for client 23.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_23_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_23_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_23_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_24 - CAS cycle count register for client 24.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_24_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_24_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_24_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_25 - CAS cycle count register for client 25.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_25_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_25_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_25_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_26 - CAS cycle count register for client 26.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_26_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_26_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_26_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_27 - CAS cycle count register for client 27.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_27_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_27_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_27_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_28 - CAS cycle count register for client 28.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_28_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_28_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_28_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_29 - CAS cycle count register for client 29.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_29_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_29_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_29_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_30 - CAS cycle count register for client 30.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_30_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_30_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_30_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_31 - CAS cycle count register for client 31.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_31_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_31_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_31_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_32 - CAS cycle count register for client 32.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_32_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_32_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_32_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_33 - CAS cycle count register for client 33.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_33_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_33_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_33_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_34 - CAS cycle count register for client 34.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_34_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_34_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_34_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_35 - CAS cycle count register for client 35.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_35_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_35_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_35_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_36 - CAS cycle count register for client 36.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_36_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_36_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_36_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_37 - CAS cycle count register for client 37.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_37_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_37_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_37_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_38 - CAS cycle count register for client 38.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_38_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_38_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_38_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_39 - CAS cycle count register for client 39.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_39_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_39_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_39_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_40 - CAS cycle count register for client 40.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_40_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_40_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_40_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_41 - CAS cycle count register for client 41.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_41_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_41_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_41_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_42 - CAS cycle count register for client 42.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_42_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_42_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_42_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_43 - CAS cycle count register for client 43.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_43_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_43_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_43_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_44 - CAS cycle count register for client 44.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_44_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_44_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_44_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_45 - CAS cycle count register for client 45.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_45_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_45_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_45_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_46 - CAS cycle count register for client 46.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_46_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_46_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_46_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_47 - CAS cycle count register for client 47.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_47_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_47_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_47_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_48 - CAS cycle count register for client 48.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_48_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_48_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_48_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_49 - CAS cycle count register for client 49.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_49_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_49_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_49_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_50 - CAS cycle count register for client 50.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_50_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_50_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_50_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_51 - CAS cycle count register for client 51.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_51_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_51_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_51_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_52 - CAS cycle count register for client 52.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_52_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_52_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_52_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_53 - CAS cycle count register for client 53.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_53_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_53_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_53_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_54 - CAS cycle count register for client 54.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_54_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_54_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_54_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_55 - CAS cycle count register for client 55.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_55_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_55_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_55_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_56 - CAS cycle count register for client 56.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_56_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_56_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_56_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_57 - CAS cycle count register for client 57.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_57_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_57_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_57_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_58 - CAS cycle count register for client 58.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_58_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_58_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_58_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_59 - CAS cycle count register for client 59.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_59_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_59_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_59_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_60 - CAS cycle count register for client 60.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_60_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_60_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_60_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_61 - CAS cycle count register for client 61.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_61_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_61_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_61_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_62 - CAS cycle count register for client 62.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_62_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_62_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_62_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_63 - CAS cycle count register for client 63.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_63_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_63_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_63_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_64 - CAS cycle count register for client 64.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_64_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_64_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_64_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_65 - CAS cycle count register for client 65.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_65_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_65_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_65_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_66 - CAS cycle count register for client 66.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_66_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_66_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_66_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_67 - CAS cycle count register for client 67.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_67_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_67_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_67_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_68 - CAS cycle count register for client 68.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_68_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_68_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_68_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_69 - CAS cycle count register for client 69.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_69_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_69_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_69_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_70 - CAS cycle count register for client 70.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_70_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_70_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_70_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_71 - CAS cycle count register for client 71.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_71_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_71_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_71_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_72 - CAS cycle count register for client 72.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_72_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_72_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_72_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_73 - CAS cycle count register for client 73.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_73_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_73_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_73_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_74 - CAS cycle count register for client 74.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_74_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_74_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_74_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_75 - CAS cycle count register for client 75.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_75_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_75_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_75_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_76 - CAS cycle count register for client 76.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_76_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_76_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_76_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_77 - CAS cycle count register for client 77.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_77_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_77_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_77_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_78 - CAS cycle count register for client 78.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_78_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_78_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_78_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_79 - CAS cycle count register for client 79.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_79_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_79_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_79_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_80 - CAS cycle count register for client 80.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_80_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_80_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_80_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_81 - CAS cycle count register for client 81.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_81_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_81_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_81_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_82 - CAS cycle count register for client 82.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_82_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_82_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_82_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_83 - CAS cycle count register for client 83.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_83_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_83_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_83_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_84 - CAS cycle count register for client 84.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_84_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_84_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_84_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_85 - CAS cycle count register for client 85.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_85_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_85_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_85_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_86 - CAS cycle count register for client 86.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_86_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_86_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_86_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_87 - CAS cycle count register for client 87.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_87_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_87_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_87_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_88 - CAS cycle count register for client 88.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_88_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_88_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_88_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_89 - CAS cycle count register for client 89.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_89_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_89_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_89_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_90 - CAS cycle count register for client 90.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_90_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_90_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_90_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_91 - CAS cycle count register for client 91.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_91_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_91_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_91_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_92 - CAS cycle count register for client 92.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_92_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_92_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_92_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_93 - CAS cycle count register for client 93.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_93_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_93_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_93_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_94 - CAS cycle count register for client 94.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_94_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_94_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_94_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_95 - CAS cycle count register for client 95.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_95_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_95_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_95_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_96 - CAS cycle count register for client 96.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_96_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_96_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_96_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_97 - CAS cycle count register for client 97.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_97_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_97_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_97_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_98 - CAS cycle count register for client 98.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_98_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_98_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_98_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_99 - CAS cycle count register for client 99.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_99_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_99_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_99_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_100 - CAS cycle count register for client 100.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_100_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_100_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_100_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_101 - CAS cycle count register for client 101.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_101_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_101_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_101_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_102 - CAS cycle count register for client 102.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_102_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_102_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_102_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_103 - CAS cycle count register for client 103.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_103_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_103_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_103_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_104 - CAS cycle count register for client 104.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_104_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_104_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_104_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_105 - CAS cycle count register for client 105.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_105_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_105_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_105_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_106 - CAS cycle count register for client 106.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_106_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_106_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_106_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_107 - CAS cycle count register for client 107.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_107_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_107_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_107_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_108 - CAS cycle count register for client 108.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_108_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_108_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_108_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_109 - CAS cycle count register for client 109.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_109_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_109_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_109_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_110 - CAS cycle count register for client 110.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_110_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_110_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_110_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_111 - CAS cycle count register for client 111.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_111_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_111_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_111_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_112 - CAS cycle count register for client 112.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_112_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_112_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_112_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_113 - CAS cycle count register for client 113.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_113_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_113_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_113_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_114 - CAS cycle count register for client 114.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_114_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_114_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_114_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_115 - CAS cycle count register for client 115.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_115_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_115_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_115_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_116 - CAS cycle count register for client 116.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_116_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_116_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_116_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_117 - CAS cycle count register for client 117.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_117_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_117_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_117_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_118 - CAS cycle count register for client 118.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_118_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_118_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_118_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_119 - CAS cycle count register for client 119.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_119_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_119_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_119_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_120 - CAS cycle count register for client 120.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_120_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_120_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_120_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_121 - CAS cycle count register for client 121.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_121_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_121_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_121_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_122 - CAS cycle count register for client 122.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_122_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_122_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_122_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_123 - CAS cycle count register for client 123.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_123_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_123_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_123_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_124 - CAS cycle count register for client 124.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_124_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_124_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_124_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_125 - CAS cycle count register for client 125.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_125_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_125_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_125_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_126 - CAS cycle count register for client 126.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_126_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_126_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_126_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_127 - CAS cycle count register for client 127.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_127_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_127_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_127_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MIN_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MIN_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_1_STAT_MIN_CAS_ALL_COUNT_DEFAULT             4294967295
+
+/***************************************************************************
+ *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT    4294967295
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_CONTROL - MEMSYS Auto Init Control.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: reserved0 [31:10] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_reserved0_MASK    0xfffffc00
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_reserved0_SHIFT   10
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_DIVIDER [09:09] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_MASK 0x00000200
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_SHIFT 9
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_DEFAULT 0
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_VDL_CALIB_AUTO_INIT [08:08] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_MASK 0x00000100
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_SHIFT 8
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_DEFAULT 0
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_DRAM_INIT_DONE_SET [07:07] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_MASK 0x00000080
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_SHIFT 7
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_DEFAULT 0
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_RESET [06:06] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_MASK 0x00000040
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_SHIFT 6
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_DEFAULT 0
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_SET [05:05] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_MASK 0x00000020
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_SHIFT 5
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_DEFAULT 0
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_READY_SET [04:04] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_MASK 0x00000010
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_SHIFT 4
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_DEFAULT 0
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_AUTO_INIT_ACTIVE_RESET [03:03] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_MASK 0x00000008
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_SHIFT 3
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_DEFAULT 0
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET [02:02] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_MASK 0x00000004
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_SHIFT 2
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_DEFAULT 0
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: SKIP_PHY_AUTO_INIT [01:01] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_MASK 0x00000002
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_SHIFT 1
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_DEFAULT 0
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: MEMSYS_AUTO_INIT_START [00:00] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_MASK 0x00000001
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_SHIFT 0
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_STATUS - MEMSYS Auto Init Status.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_reserved0_MASK     0xfffff000
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_reserved0_SHIFT    12
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: MEMC_AUTO_INIT_STATES [11:06] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_MASK 0x00000fc0
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_SHIFT 6
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_DEFAULT 0
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: AUTO_INIT_ACTIVE [05:05] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_MASK 0x00000020
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_SHIFT 5
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_DEFAULT 0
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: PHY_STRAP_VALID [04:04] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_MASK 0x00000010
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_SHIFT 4
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_DEFAULT 0
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: PHY_READY [03:03] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_PHY_READY_MASK     0x00000008
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_PHY_READY_SHIFT    3
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_PHY_READY_DEFAULT  0
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: DRAM_INIT_DONE [02:02] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_MASK 0x00000004
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_SHIFT 2
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_DEFAULT 0
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_FAIL [01:01] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_MASK 0x00000002
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_SHIFT 1
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_DEFAULT 0
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_MASK 0x00000001
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_SHIFT 0
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_DEFAULT 0
+
+/***************************************************************************
+ *PHY_VDL_CALIB_AUTO_INIT_OVERRIDE - PHY VDL calibrate override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: PHY_VDL_CALIB_AUTO_INIT_OVERRIDE :: PHY_VDL_CALIB_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_1_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_1_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_1_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_DEFAULT 268435456
+
+/***************************************************************************
+ *SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE - SHIM PLL pndiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_PNDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_1_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_1_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_1_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_DEFAULT 598736896
+
+/***************************************************************************
+ *SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE - SHIM PLL mdiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_MDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_1_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_1_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_1_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_DEFAULT 4099
+
+/***************************************************************************
+ *DYN_VDL_CMD_DLY - Dynamic VDL shmoo command delay.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DYN_VDL_CMD_DLY :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_reserved0_MASK             0xfffff000
+#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_reserved0_SHIFT            12
+
+/* MEMC_DDR_1 :: DYN_VDL_CMD_DLY :: END_CAS_DLY [11:06] */
+#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_END_CAS_DLY_MASK           0x00000fc0
+#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_END_CAS_DLY_SHIFT          6
+#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_END_CAS_DLY_DEFAULT        0
+
+/* MEMC_DDR_1 :: DYN_VDL_CMD_DLY :: START_CAS_DLY [05:00] */
+#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_START_CAS_DLY_MASK         0x0000003f
+#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_START_CAS_DLY_SHIFT        0
+#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_START_CAS_DLY_DEFAULT      0
+
+#endif /* #ifndef BCHP_MEMC_DDR_1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_memc_misc_1.h b/include/linux/brcmstb/7425b0/bchp_memc_misc_1.h
new file mode 100644
index 0000000..c68f757
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_memc_misc_1.h
@@ -0,0 +1,131 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Apr 11 13:39:59 2011
+ *                 MD5 Checksum         8cf142ad25caa9f873c54e8bb2bb1755
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7425/rdb/b0/bchp_memc_misc_1.h $
+ * 
+ * Hydra_Software_Devel/2   4/12/11 9:02a vanessah
+ * SW7425-112: Update rdb files for 7425 B0.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_MISC_1_H__
+#define BCHP_MEMC_MISC_1_H__
+
+/***************************************************************************
+ *MEMC_MISC_1 - MEMSYS Misc (Soft-Resets/Configuration) Registers 1
+ ***************************************************************************/
+#define BCHP_MEMC_MISC_1_SOFT_RESET              0x003c5000 /* MEMC_TOP layout block Soft Reset */
+#define BCHP_MEMC_MISC_1_MEMC_STRAP_DDR_CONFIG   0x003c5004 /* MEMC_STRAP_DDR_CONFIG Control Register */
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL       0x003c5008 /* MEMC MBIST TM Control Register */
+#define BCHP_MEMC_MISC_1_SCRATCH_0               0x003c5010 /* Scratch Register */
+
+/***************************************************************************
+ *SOFT_RESET - MEMC_TOP layout block Soft Reset
+ ***************************************************************************/
+/* MEMC_MISC_1 :: SOFT_RESET :: reserved0 [31:05] */
+#define BCHP_MEMC_MISC_1_SOFT_RESET_reserved0_MASK                 0xffffffe0
+#define BCHP_MEMC_MISC_1_SOFT_RESET_reserved0_SHIFT                5
+
+/* MEMC_MISC_1 :: SOFT_RESET :: MEMC_IOBUF_RBUS [04:04] */
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_IOBUF_RBUS_MASK           0x00000010
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_IOBUF_RBUS_SHIFT          4
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_IOBUF_RBUS_DEFAULT        0
+
+/* MEMC_MISC_1 :: SOFT_RESET :: MEMC_IOBUF [03:03] */
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_IOBUF_MASK                0x00000008
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_IOBUF_SHIFT               3
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_IOBUF_DEFAULT             0
+
+/* MEMC_MISC_1 :: SOFT_RESET :: MEMC_DRAM_INIT [02:02] */
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_DRAM_INIT_MASK            0x00000004
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_DRAM_INIT_SHIFT           2
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_DRAM_INIT_DEFAULT         0
+
+/* MEMC_MISC_1 :: SOFT_RESET :: MEMC_RBUS [01:01] */
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_RBUS_MASK                 0x00000002
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_RBUS_SHIFT                1
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_RBUS_DEFAULT              0
+
+/* MEMC_MISC_1 :: SOFT_RESET :: MEMC_CORE [00:00] */
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_CORE_MASK                 0x00000001
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_CORE_SHIFT                0
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_CORE_DEFAULT              0
+
+/***************************************************************************
+ *MEMC_STRAP_DDR_CONFIG - MEMC_STRAP_DDR_CONFIG Control Register
+ ***************************************************************************/
+/* MEMC_MISC_1 :: MEMC_STRAP_DDR_CONFIG :: reserved0 [31:02] */
+#define BCHP_MEMC_MISC_1_MEMC_STRAP_DDR_CONFIG_reserved0_MASK      0xfffffffc
+#define BCHP_MEMC_MISC_1_MEMC_STRAP_DDR_CONFIG_reserved0_SHIFT     2
+
+/* MEMC_MISC_1 :: MEMC_STRAP_DDR_CONFIG :: DDR_CONFIG [01:00] */
+#define BCHP_MEMC_MISC_1_MEMC_STRAP_DDR_CONFIG_DDR_CONFIG_MASK     0x00000003
+#define BCHP_MEMC_MISC_1_MEMC_STRAP_DDR_CONFIG_DDR_CONFIG_SHIFT    0
+#define BCHP_MEMC_MISC_1_MEMC_STRAP_DDR_CONFIG_DDR_CONFIG_DEFAULT  1
+#define BCHP_MEMC_MISC_1_MEMC_STRAP_DDR_CONFIG_DDR_CONFIG_DDR32BIT 1
+#define BCHP_MEMC_MISC_1_MEMC_STRAP_DDR_CONFIG_DDR_CONFIG_DDR16BIT 2
+
+/***************************************************************************
+ *MEMC_TOP_TM_CNTRL - MEMC MBIST TM Control Register
+ ***************************************************************************/
+/* MEMC_MISC_1 :: MEMC_TOP_TM_CNTRL :: reserved0 [31:06] */
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_reserved0_MASK          0xffffffc0
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_reserved0_SHIFT         6
+
+/* MEMC_MISC_1 :: MEMC_TOP_TM_CNTRL :: MEMC_PFRI_FIFO_2 [05:04] */
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_2_MASK   0x00000030
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_2_SHIFT  4
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_2_DEFAULT 0
+
+/* MEMC_MISC_1 :: MEMC_TOP_TM_CNTRL :: MEMC_PFRI_FIFO_1 [03:02] */
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_1_MASK   0x0000000c
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_1_SHIFT  2
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_1_DEFAULT 0
+
+/* MEMC_MISC_1 :: MEMC_TOP_TM_CNTRL :: MEMC_PFRI_FIFO_0 [01:00] */
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_0_MASK   0x00000003
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_0_SHIFT  0
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_0_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH_0 - Scratch Register
+ ***************************************************************************/
+/* MEMC_MISC_1 :: SCRATCH_0 :: VALUE [31:00] */
+#define BCHP_MEMC_MISC_1_SCRATCH_0_VALUE_MASK                      0xffffffff
+#define BCHP_MEMC_MISC_1_SCRATCH_0_VALUE_SHIFT                     0
+#define BCHP_MEMC_MISC_1_SCRATCH_0_VALUE_DEFAULT                   0
+
+#endif /* #ifndef BCHP_MEMC_MISC_1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_moca_hostmisc.h b/include/linux/brcmstb/7425b0/bchp_moca_hostmisc.h
new file mode 100644
index 0000000..34939f5
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_moca_hostmisc.h
@@ -0,0 +1,483 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:42 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MOCA_HOSTMISC_H__
+#define BCHP_MOCA_HOSTMISC_H__
+
+/***************************************************************************
+ *MOCA_HOSTMISC - MOCA_HOSTMISC registers
+ ***************************************************************************/
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL             0x00fffd00 /* Moca Software Reset */
+#define BCHP_MOCA_HOSTMISC_SCRATCH               0x00fffd04 /* Moca Scratch Register */
+#define BCHP_MOCA_HOSTMISC_VERSION               0x00fffd08 /* MoCA version register */
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG          0x00fffd0c /* Host-to-MoCA Interrupt Trigger */
+#define BCHP_MOCA_HOSTMISC_WAKEUP                0x00fffd10 /* Host-to-MoCA Wakeup Interrupt */
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG            0x00fffd14 /* Moca Subsystem configuration */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0      0x00fffd18 /* Host to MoCA MMP outbox registes , register set index 0. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1      0x00fffd1c /* Host to MoCA MMP outbox registes , register set index 1. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2      0x00fffd20 /* Host to MoCA MMP outbox registes , register set index 2. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3      0x00fffd24 /* Host to MoCA MMP outbox registes , register set index 3. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4      0x00fffd28 /* Host to MoCA MMP outbox registes , register set index 4. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5      0x00fffd2c /* Host to MoCA MMP outbox registes , register set index 5. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6      0x00fffd30 /* Host to MoCA MMP outbox registes , register set index 6. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7      0x00fffd34 /* Host to MoCA MMP outbox registes , register set index 7. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8      0x00fffd38 /* Host to MoCA MMP outbox registes , register set index 8. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9      0x00fffd3c /* Host to MoCA MMP outbox registes , register set index 9. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10     0x00fffd40 /* Host to MoCA MMP outbox registes , register set index 10. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11     0x00fffd44 /* Host to MoCA MMP outbox registes , register set index 11. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12     0x00fffd48 /* Host to MoCA MMP outbox registes , register set index 12. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13     0x00fffd4c /* Host to MoCA MMP outbox registes , register set index 13. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14     0x00fffd50 /* Host to MoCA MMP outbox registes , register set index 14. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15     0x00fffd54 /* Host to MoCA MMP outbox registes , register set index 15. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0       0x00fffd58 /* MoCA to Host MMP inbox registers , register set index 0. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1       0x00fffd5c /* MoCA to Host MMP inbox registers , register set index 1. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2       0x00fffd60 /* MoCA to Host MMP inbox registers , register set index 2. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3       0x00fffd64 /* MoCA to Host MMP inbox registers , register set index 3. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4       0x00fffd68 /* MoCA to Host MMP inbox registers , register set index 4. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5       0x00fffd6c /* MoCA to Host MMP inbox registers , register set index 5. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6       0x00fffd70 /* MoCA to Host MMP inbox registers , register set index 6. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7       0x00fffd74 /* MoCA to Host MMP inbox registers , register set index 7. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8       0x00fffd78 /* MoCA to Host MMP inbox registers , register set index 8. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9       0x00fffd7c /* MoCA to Host MMP inbox registers , register set index 9. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10      0x00fffd80 /* MoCA to Host MMP inbox registers , register set index 10. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11      0x00fffd84 /* MoCA to Host MMP inbox registers , register set index 11. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12      0x00fffd88 /* MoCA to Host MMP inbox registers , register set index 12. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13      0x00fffd8c /* MoCA to Host MMP inbox registers , register set index 13. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14      0x00fffd90 /* MoCA to Host MMP inbox registers , register set index 14. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15      0x00fffd94 /* MoCA to Host MMP inbox registers , register set index 15. */
+
+/***************************************************************************
+ *MISC_CTRL - Moca Software Reset
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: MISC_CTRL :: spare_ctrl [31:15] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_ctrl_MASK               0xffff8000
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_ctrl_SHIFT              15
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_ctrl_DEFAULT            0x0001ffff
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: spare_status [14:10] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_status_MASK             0x00007c00
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_status_SHIFT            10
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_status_DEFAULT          0x0000001f
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: spare_reset2 [09:08] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset2_MASK             0x00000300
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset2_SHIFT            8
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset2_DEFAULT          0x00000003
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: moca_disable_clocks [07:07] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_disable_clocks_MASK      0x00000080
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_disable_clocks_SHIFT     7
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_disable_clocks_DEFAULT   0x00000000
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: spare_reset [06:04] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset_MASK              0x00000070
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset_SHIFT             4
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset_DEFAULT           0x00000007
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: moca_gmii_sw_init [03:03] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_gmii_sw_init_MASK        0x00000008
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_gmii_sw_init_SHIFT       3
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_gmii_sw_init_DEFAULT     0x00000000
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: moca_cpu_l_reset [02:02] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_l_reset_MASK         0x00000004
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_l_reset_SHIFT        2
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_l_reset_DEFAULT      0x00000001
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: moca_sys_reset [01:01] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_sys_reset_MASK           0x00000002
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_sys_reset_SHIFT          1
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_sys_reset_DEFAULT        0x00000001
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: moca_cpu_h_reset [00:00] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_h_reset_MASK         0x00000001
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_h_reset_SHIFT        0
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_h_reset_DEFAULT      0x00000001
+
+/***************************************************************************
+ *SCRATCH - Moca Scratch Register
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: SCRATCH :: value [31:00] */
+#define BCHP_MOCA_HOSTMISC_SCRATCH_value_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_SCRATCH_value_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_SCRATCH_value_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *VERSION - MoCA version register
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: VERSION :: moca_id [31:16] */
+#define BCHP_MOCA_HOSTMISC_VERSION_moca_id_MASK                    0xffff0000
+#define BCHP_MOCA_HOSTMISC_VERSION_moca_id_SHIFT                   16
+#define BCHP_MOCA_HOSTMISC_VERSION_moca_id_DEFAULT                 0x00006622
+
+/* MOCA_HOSTMISC :: VERSION :: moca_spec_ver [15:12] */
+#define BCHP_MOCA_HOSTMISC_VERSION_moca_spec_ver_MASK              0x0000f000
+#define BCHP_MOCA_HOSTMISC_VERSION_moca_spec_ver_SHIFT             12
+#define BCHP_MOCA_HOSTMISC_VERSION_moca_spec_ver_DEFAULT           0x00000002
+
+/* MOCA_HOSTMISC :: VERSION :: core_version [11:08] */
+#define BCHP_MOCA_HOSTMISC_VERSION_core_version_MASK               0x00000f00
+#define BCHP_MOCA_HOSTMISC_VERSION_core_version_SHIFT              8
+#define BCHP_MOCA_HOSTMISC_VERSION_core_version_DEFAULT            0x00000001
+
+/* MOCA_HOSTMISC :: VERSION :: core_revision [07:04] */
+#define BCHP_MOCA_HOSTMISC_VERSION_core_revision_MASK              0x000000f0
+#define BCHP_MOCA_HOSTMISC_VERSION_core_revision_SHIFT             4
+#define BCHP_MOCA_HOSTMISC_VERSION_core_revision_DEFAULT           0x00000001
+
+/* MOCA_HOSTMISC :: VERSION :: core_mask [03:00] */
+#define BCHP_MOCA_HOSTMISC_VERSION_core_mask_MASK                  0x0000000f
+#define BCHP_MOCA_HOSTMISC_VERSION_core_mask_SHIFT                 0
+#define BCHP_MOCA_HOSTMISC_VERSION_core_mask_DEFAULT               0x00000000
+
+/***************************************************************************
+ *H2M_INT_TRIG - Host-to-MoCA Interrupt Trigger
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_INT_TRIG :: reserved0 [31:08] */
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_reserved0_MASK             0xffffff00
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_reserved0_SHIFT            8
+
+/* MOCA_HOSTMISC :: H2M_INT_TRIG :: INT_TRIG [07:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_MASK              0x000000ff
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_SHIFT             0
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_DEFAULT           0x00000000
+
+/***************************************************************************
+ *WAKEUP - Host-to-MoCA Wakeup Interrupt
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: WAKEUP :: reserved0 [31:02] */
+#define BCHP_MOCA_HOSTMISC_WAKEUP_reserved0_MASK                   0xfffffffc
+#define BCHP_MOCA_HOSTMISC_WAKEUP_reserved0_SHIFT                  2
+
+/* MOCA_HOSTMISC :: WAKEUP :: cpu_l_wakeup_int [01:01] */
+#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_l_wakeup_int_MASK            0x00000002
+#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_l_wakeup_int_SHIFT           1
+#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_l_wakeup_int_DEFAULT         0x00000000
+
+/* MOCA_HOSTMISC :: WAKEUP :: cpu_h_wakeup_int [00:00] */
+#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_h_wakeup_int_MASK            0x00000001
+#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_h_wakeup_int_SHIFT           0
+#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_h_wakeup_int_DEFAULT         0x00000000
+
+/***************************************************************************
+ *SUBSYS_CFG - Moca Subsystem configuration
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: SUBSYS_CFG :: spare_cfg [31:10] */
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_spare_cfg_MASK               0xfffffc00
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_spare_cfg_SHIFT              10
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_spare_cfg_DEFAULT            0x00000000
+
+/* MOCA_HOSTMISC :: SUBSYS_CFG :: moca_ctl_mem_split_reg [09:07] */
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_ctl_mem_split_reg_MASK  0x00000380
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_ctl_mem_split_reg_SHIFT 7
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_ctl_mem_split_reg_DEFAULT 0x00000004
+
+/* MOCA_HOSTMISC :: SUBSYS_CFG :: moca_cpu_dmem_split_reg [06:04] */
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_cpu_dmem_split_reg_MASK 0x00000070
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_cpu_dmem_split_reg_SHIFT 4
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_cpu_dmem_split_reg_DEFAULT 0x00000002
+
+/* MOCA_HOSTMISC :: SUBSYS_CFG :: moca_cpu_imem_split_reg [03:01] */
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_cpu_imem_split_reg_MASK 0x0000000e
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_cpu_imem_split_reg_SHIFT 1
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_cpu_imem_split_reg_DEFAULT 0x00000002
+
+/* MOCA_HOSTMISC :: SUBSYS_CFG :: moca_arb_rr_sel [00:00] */
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_arb_rr_sel_MASK         0x00000001
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_arb_rr_sel_SHIFT        0
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_arb_rr_sel_DEFAULT      0x00000001
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_0 - Host to MoCA MMP outbox registes , register set index 0.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_0 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_1 - Host to MoCA MMP outbox registes , register set index 1.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_1 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_2 - Host to MoCA MMP outbox registes , register set index 2.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_2 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_3 - Host to MoCA MMP outbox registes , register set index 3.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_3 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_4 - Host to MoCA MMP outbox registes , register set index 4.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_4 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_5 - Host to MoCA MMP outbox registes , register set index 5.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_5 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_6 - Host to MoCA MMP outbox registes , register set index 6.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_6 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_7 - Host to MoCA MMP outbox registes , register set index 7.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_7 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_8 - Host to MoCA MMP outbox registes , register set index 8.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_8 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_9 - Host to MoCA MMP outbox registes , register set index 9.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_9 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_10 - Host to MoCA MMP outbox registes , register set index 10.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_10 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10_m2h_mmp_outbox_MASK   0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10_m2h_mmp_outbox_SHIFT  0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_11 - Host to MoCA MMP outbox registes , register set index 11.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_11 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11_m2h_mmp_outbox_MASK   0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11_m2h_mmp_outbox_SHIFT  0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_12 - Host to MoCA MMP outbox registes , register set index 12.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_12 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12_m2h_mmp_outbox_MASK   0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12_m2h_mmp_outbox_SHIFT  0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_13 - Host to MoCA MMP outbox registes , register set index 13.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_13 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13_m2h_mmp_outbox_MASK   0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13_m2h_mmp_outbox_SHIFT  0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_14 - Host to MoCA MMP outbox registes , register set index 14.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_14 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14_m2h_mmp_outbox_MASK   0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14_m2h_mmp_outbox_SHIFT  0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_15 - Host to MoCA MMP outbox registes , register set index 15.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_15 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15_m2h_mmp_outbox_MASK   0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15_m2h_mmp_outbox_SHIFT  0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_0 - MoCA to Host MMP inbox registers , register set index 0.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_0 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_1 - MoCA to Host MMP inbox registers , register set index 1.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_1 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_2 - MoCA to Host MMP inbox registers , register set index 2.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_2 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_3 - MoCA to Host MMP inbox registers , register set index 3.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_3 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_4 - MoCA to Host MMP inbox registers , register set index 4.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_4 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_5 - MoCA to Host MMP inbox registers , register set index 5.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_5 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_6 - MoCA to Host MMP inbox registers , register set index 6.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_6 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_7 - MoCA to Host MMP inbox registers , register set index 7.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_7 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_8 - MoCA to Host MMP inbox registers , register set index 8.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_8 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_9 - MoCA to Host MMP inbox registers , register set index 9.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_9 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_10 - MoCA to Host MMP inbox registers , register set index 10.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_10 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10_h2m_mmp_inbox_MASK     0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10_h2m_mmp_inbox_SHIFT    0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10_h2m_mmp_inbox_DEFAULT  0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_11 - MoCA to Host MMP inbox registers , register set index 11.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_11 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11_h2m_mmp_inbox_MASK     0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11_h2m_mmp_inbox_SHIFT    0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11_h2m_mmp_inbox_DEFAULT  0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_12 - MoCA to Host MMP inbox registers , register set index 12.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_12 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12_h2m_mmp_inbox_MASK     0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12_h2m_mmp_inbox_SHIFT    0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12_h2m_mmp_inbox_DEFAULT  0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_13 - MoCA to Host MMP inbox registers , register set index 13.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_13 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13_h2m_mmp_inbox_MASK     0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13_h2m_mmp_inbox_SHIFT    0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13_h2m_mmp_inbox_DEFAULT  0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_14 - MoCA to Host MMP inbox registers , register set index 14.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_14 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14_h2m_mmp_inbox_MASK     0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14_h2m_mmp_inbox_SHIFT    0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14_h2m_mmp_inbox_DEFAULT  0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_15 - MoCA to Host MMP inbox registers , register set index 15.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_15 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15_h2m_mmp_inbox_MASK     0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15_h2m_mmp_inbox_SHIFT    0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15_h2m_mmp_inbox_DEFAULT  0x00000000
+
+#endif /* #ifndef BCHP_MOCA_HOSTMISC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_nand.h b/include/linux/brcmstb/7425b0/bchp_nand.h
new file mode 100644
index 0000000..0e50605
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_nand.h
@@ -0,0 +1,2483 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:44 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_NAND_H__
+#define BCHP_NAND_H__
+
+/***************************************************************************
+ *NAND - Nand Flash Control Registers
+ ***************************************************************************/
+#define BCHP_NAND_REVISION                       0x0041b800 /* NAND Revision */
+#define BCHP_NAND_CMD_START                      0x0041b804 /* Nand Flash Command Start */
+#define BCHP_NAND_CMD_EXT_ADDRESS                0x0041b808 /* Nand Flash Command Extended Address */
+#define BCHP_NAND_CMD_ADDRESS                    0x0041b80c /* Nand Flash Command Address */
+#define BCHP_NAND_CMD_END_ADDRESS                0x0041b810 /* Nand Flash Command End Address */
+#define BCHP_NAND_CS_NAND_SELECT                 0x0041b814 /* Nand Flash EBI CS Select */
+#define BCHP_NAND_CS_NAND_XOR                    0x0041b818 /* Nand Flash EBI CS Address XOR with 1FC0 Control */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0          0x0041b820 /* Nand Flash Spare Area Read Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4          0x0041b824 /* Nand Flash Spare Area Read Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8          0x0041b828 /* Nand Flash Spare Area Read Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C          0x0041b82c /* Nand Flash Spare Area Read Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0         0x0041b830 /* Nand Flash Spare Area Write Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4         0x0041b834 /* Nand Flash Spare Area Write Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8         0x0041b838 /* Nand Flash Spare Area Write Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C         0x0041b83c /* Nand Flash Spare Area Write Bytes 12-15 */
+#define BCHP_NAND_ACC_CONTROL                    0x0041b840 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG                         0x0041b848 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1                       0x0041b850 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2                       0x0041b854 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SEMAPHORE                      0x0041b858 /* Semaphore */
+#define BCHP_NAND_FLASH_DEVICE_ID                0x0041b860 /* Nand Flash Device ID */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT            0x0041b864 /* Nand Flash Extended Device ID */
+#define BCHP_NAND_BLOCK_LOCK_STATUS              0x0041b868 /* Nand Flash Block Lock Status */
+#define BCHP_NAND_INTFC_STATUS                   0x0041b86c /* Nand Flash Interface Status */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR              0x0041b870 /* ECC Correctable Error Extended Address */
+#define BCHP_NAND_ECC_CORR_ADDR                  0x0041b874 /* ECC Correctable Error Address */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR               0x0041b878 /* ECC Uncorrectable Error Extended Address */
+#define BCHP_NAND_ECC_UNC_ADDR                   0x0041b87c /* ECC Uncorrectable Error Address */
+#define BCHP_NAND_READ_ERROR_COUNT               0x0041b880 /* Read Error Count */
+#define BCHP_NAND_CORR_STAT_THRESHOLD            0x0041b884 /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_ONFI_STATUS                    0x0041b888 /* ONFI Status */
+#define BCHP_NAND_ONFI_DEBUG_DATA                0x0041b88c /* ONFI Debug Data */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR            0x0041b890 /* Flash Read Data Extended Address */
+#define BCHP_NAND_FLASH_READ_ADDR                0x0041b894 /* Flash Read Data Address */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR          0x0041b898 /* Page Program Extended Address */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR              0x0041b89c /* Page Program Address */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR             0x0041b8a0 /* Copy Back Extended Address */
+#define BCHP_NAND_COPY_BACK_ADDR                 0x0041b8a4 /* Copy Back Address */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR           0x0041b8a8 /* Block Erase Extended Address */
+#define BCHP_NAND_BLOCK_ERASE_ADDR               0x0041b8ac /* Block Erase Address */
+#define BCHP_NAND_INV_READ_EXT_ADDR              0x0041b8b0 /* Flash Invalid Data Extended Address */
+#define BCHP_NAND_INV_READ_ADDR                  0x0041b8b4 /* Flash Invalid Data Address */
+#define BCHP_NAND_BLK_WR_PROTECT                 0x0041b8c0 /* Block Write Protect Enable and Size for EBI_CS0b */
+#define BCHP_NAND_ACC_CONTROL_CS1                0x0041b8d0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS1                     0x0041b8d4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS1                   0x0041b8d8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS1                   0x0041b8dc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS2                0x0041b8e0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS2                     0x0041b8e4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS2                   0x0041b8e8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS2                   0x0041b8ec /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS3                0x0041b8f0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS3                     0x0041b8f4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS3                   0x0041b8f8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS3                   0x0041b8fc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS4                0x0041b900 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS4                     0x0041b904 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS4                   0x0041b908 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS4                   0x0041b90c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS5                0x0041b910 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS5                     0x0041b914 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS5                   0x0041b918 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS5                   0x0041b91c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10         0x0041b930 /* Nand Flash Spare Area Read Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14         0x0041b934 /* Nand Flash Spare Area Read Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18         0x0041b938 /* Nand Flash Spare Area Read Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C         0x0041b93c /* Nand Flash Spare Area Read Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10        0x0041b940 /* Nand Flash Spare Area Write Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14        0x0041b944 /* Nand Flash Spare Area Write Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18        0x0041b948 /* Nand Flash Spare Area Write Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C        0x0041b94c /* Nand Flash Spare Area Write Bytes 28-31 */
+#define BCHP_NAND_LL_OP                          0x0041b978 /* Nand Flash Low Level Operation */
+#define BCHP_NAND_LL_RDDATA                      0x0041b97c /* Nand Flash Low Level Read Data */
+
+/***************************************************************************
+ *REVISION - NAND Revision
+ ***************************************************************************/
+/* NAND :: REVISION :: 8KB_PAGE_SUPPORT [31:31] */
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_MASK                   0x80000000
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_SHIFT                  31
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_DEFAULT                0x00000001
+
+/* NAND :: REVISION :: reserved0 [30:16] */
+#define BCHP_NAND_REVISION_reserved0_MASK                          0x7fff0000
+#define BCHP_NAND_REVISION_reserved0_SHIFT                         16
+
+/* NAND :: REVISION :: MAJOR [15:08] */
+#define BCHP_NAND_REVISION_MAJOR_MASK                              0x0000ff00
+#define BCHP_NAND_REVISION_MAJOR_SHIFT                             8
+#define BCHP_NAND_REVISION_MAJOR_DEFAULT                           0x00000005
+
+/* NAND :: REVISION :: MINOR [07:00] */
+#define BCHP_NAND_REVISION_MINOR_MASK                              0x000000ff
+#define BCHP_NAND_REVISION_MINOR_SHIFT                             0
+#define BCHP_NAND_REVISION_MINOR_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *CMD_START - Nand Flash Command Start
+ ***************************************************************************/
+/* NAND :: CMD_START :: reserved0 [31:29] */
+#define BCHP_NAND_CMD_START_reserved0_MASK                         0xe0000000
+#define BCHP_NAND_CMD_START_reserved0_SHIFT                        29
+
+/* NAND :: CMD_START :: OPCODE [28:24] */
+#define BCHP_NAND_CMD_START_OPCODE_MASK                            0x1f000000
+#define BCHP_NAND_CMD_START_OPCODE_SHIFT                           24
+#define BCHP_NAND_CMD_START_OPCODE_DEFAULT                         0x00000000
+#define BCHP_NAND_CMD_START_OPCODE_NULL                            0
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ                       1
+#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ                 2
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ                     3
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE                    4
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA              5
+#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK                       6
+#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ                  7
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE                     8
+#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET                     9
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK                     10
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN                11
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK                   12
+#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS         13
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ                  14
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL            15
+#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP                    16
+
+/* NAND :: CMD_START :: reserved1 [23:00] */
+#define BCHP_NAND_CMD_START_reserved1_MASK                         0x00ffffff
+#define BCHP_NAND_CMD_START_reserved1_SHIFT                        0
+
+/***************************************************************************
+ *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
+ ***************************************************************************/
+/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK                   0xfff80000
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT                  19
+
+/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK                      0x00070000
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT                     16
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT                   0x00000000
+
+/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK                 0x0000ffff
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT                0
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CMD_ADDRESS - Nand Flash Command Address
+ ***************************************************************************/
+/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK                         0xffffffff
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT                        0
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *CMD_END_ADDRESS - Nand Flash Command End Address
+ ***************************************************************************/
+/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT                    0
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *CS_NAND_SELECT - Nand Flash EBI CS Select
+ ***************************************************************************/
+/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT                     31
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK        0x40000000
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT       30
+
+/* NAND :: CS_NAND_SELECT :: reserved0 [29:29] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK                    0x20000000
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT                   29
+
+/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK              0x10000000
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT             28
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT           0x00000000
+
+/* NAND :: CS_NAND_SELECT :: reserved1 [27:16] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_MASK                    0x0fff0000
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_SHIFT                   16
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK           0x00008000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT          15
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK           0x00004000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT          14
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK           0x00002000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT          13
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK           0x00001000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT          12
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK           0x00000800
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT          11
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK           0x00000400
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT          10
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK           0x00000200
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT          9
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK           0x00000100
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT          8
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK                 0x00000080
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT                7
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK                 0x00000040
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT                6
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK                 0x00000020
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT                5
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK                 0x00000010
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT                4
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK                 0x00000008
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT                3
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK                 0x00000004
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT                2
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK                 0x00000002
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT                1
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK                 0x00000001
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT                0
+
+/***************************************************************************
+ *CS_NAND_XOR - Nand Flash EBI CS Address XOR with 1FC0 Control
+ ***************************************************************************/
+/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_1FC0_XOR [31:31] */
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_MASK           0x80000000
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_SHIFT          31
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
+#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK                       0x7fffff00
+#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT                      8
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_1FC0_XOR [07:07] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_MASK          0x00000080
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_SHIFT         7
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_1FC0_XOR [06:06] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_MASK          0x00000040
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_SHIFT         6
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_1FC0_XOR [05:05] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_MASK          0x00000020
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_SHIFT         5
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_1FC0_XOR [04:04] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_MASK          0x00000010
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_SHIFT         4
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_1FC0_XOR [03:03] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_MASK          0x00000008
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_SHIFT         3
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_1FC0_XOR [02:02] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_MASK          0x00000004
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_SHIFT         2
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_1FC0_XOR [01:01] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_MASK          0x00000002
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_SHIFT         1
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_1FC0_XOR [00:00] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_MASK          0x00000001
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_SHIFT         0
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *ACC_CONTROL - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_MASK                       0x80000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_SHIFT                      31
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_DEFAULT                    0x00000001
+
+/* NAND :: ACC_CONTROL :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_MASK                       0x40000000
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_SHIFT                      30
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_DEFAULT                    0x00000001
+
+/* NAND :: ACC_CONTROL :: RD_ECC_BLK0_EN [29:29] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_MASK                  0x20000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_SHIFT                 29
+
+/* NAND :: ACC_CONTROL :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_SHIFT                  28
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_MASK                0x08000000
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_SHIFT               27
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_DEFAULT             0x00000000
+
+/* NAND :: ACC_CONTROL :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_MASK                 0x04000000
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_SHIFT                26
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_MASK                   0x02000000
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_SHIFT                  25
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_MASK                     0x01000000
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_SHIFT                    24
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_DEFAULT                  0x00000001
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL_0 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_MASK                     0x00f00000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_SHIFT                    20
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_DEFAULT                  0x0000000f
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_MASK                       0x000f0000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_SHIFT                      16
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_DEFAULT                    0x0000000f
+
+/* NAND :: ACC_CONTROL :: reserved0 [15:15] */
+#define BCHP_NAND_ACC_CONTROL_reserved0_MASK                       0x00008000
+#define BCHP_NAND_ACC_CONTROL_reserved0_SHIFT                      15
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K_0 [14:14] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_MASK                0x00004000
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_SHIFT               14
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_DEFAULT             0x00000000
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE_0 [13:08] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_MASK               0x00003f00
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_SHIFT              8
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_DEFAULT            0x00000010
+
+/* NAND :: ACC_CONTROL :: reserved1 [07:07] */
+#define BCHP_NAND_ACC_CONTROL_reserved1_MASK                       0x00000080
+#define BCHP_NAND_ACC_CONTROL_reserved1_SHIFT                      7
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_MASK                  0x00000040
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_SHIFT                 6
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_DEFAULT               0x00000000
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_MASK                 0x0000003f
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_SHIFT                0
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_DEFAULT              0x00000010
+
+/***************************************************************************
+ *CONFIG - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_MASK                          0x80000000
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_SHIFT                         31
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_DEFAULT                       0x00000000
+
+/* NAND :: CONFIG :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_MASK                           0x70000000
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_SHIFT                          28
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_2048KB                 6
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_1024KB                 5
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_512KB                  3
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_128KB                  1
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_16KB                   0
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_8KB                    2
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_256KB                  4
+
+/* NAND :: CONFIG :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_MASK                          0x0f000000
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_SHIFT                         24
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4MB                  0
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8MB                  1
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16MB                 2
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32MB                 3
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64MB                 4
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128MB                5
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_256MB                6
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_512MB                7
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_1GB                  8
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_2GB                  9
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4GB                  10
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8GB                  11
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16GB                 12
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32GB                 13
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64GB                 14
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128GB                15
+
+/* NAND :: CONFIG :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_MASK                         0x00800000
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_SHIFT                        23
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_8                  0
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_16                 1
+
+/* NAND :: CONFIG :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_reserved0_MASK                            0x00400000
+#define BCHP_NAND_CONFIG_reserved0_SHIFT                           22
+
+/* NAND :: CONFIG :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_PAGE_SIZE_MASK                            0x00300000
+#define BCHP_NAND_CONFIG_PAGE_SIZE_SHIFT                           20
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_512                     0
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_2KB                     1
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_4KB                     2
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_8KB                     3
+
+/* NAND :: CONFIG :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_reserved1_MASK                            0x00080000
+#define BCHP_NAND_CONFIG_reserved1_SHIFT                           19
+
+/* NAND :: CONFIG :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_MASK                        0x00070000
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_SHIFT                       16
+
+/* NAND :: CONFIG :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_reserved2_MASK                            0x00008000
+#define BCHP_NAND_CONFIG_reserved2_SHIFT                           15
+
+/* NAND :: CONFIG :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_MASK                        0x00007000
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_SHIFT                       12
+
+/* NAND :: CONFIG :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_reserved3_MASK                            0x00000800
+#define BCHP_NAND_CONFIG_reserved3_SHIFT                           11
+
+/* NAND :: CONFIG :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_MASK                        0x00000700
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_SHIFT                       8
+
+/* NAND :: CONFIG :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_reserved4_MASK                            0x000000ff
+#define BCHP_NAND_CONFIG_reserved4_SHIFT                           0
+
+/***************************************************************************
+ *TIMING_1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_tWP_MASK                                0xf0000000
+#define BCHP_NAND_TIMING_1_tWP_SHIFT                               28
+#define BCHP_NAND_TIMING_1_tWP_DEFAULT                             0x00000006
+
+/* NAND :: TIMING_1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_tWH_MASK                                0x0f000000
+#define BCHP_NAND_TIMING_1_tWH_SHIFT                               24
+#define BCHP_NAND_TIMING_1_tWH_DEFAULT                             0x00000005
+
+/* NAND :: TIMING_1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_tRP_MASK                                0x00f00000
+#define BCHP_NAND_TIMING_1_tRP_SHIFT                               20
+#define BCHP_NAND_TIMING_1_tRP_DEFAULT                             0x00000007
+
+/* NAND :: TIMING_1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_tREH_MASK                               0x000f0000
+#define BCHP_NAND_TIMING_1_tREH_SHIFT                              16
+#define BCHP_NAND_TIMING_1_tREH_DEFAULT                            0x00000004
+
+/* NAND :: TIMING_1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_tCS_MASK                                0x0000f000
+#define BCHP_NAND_TIMING_1_tCS_SHIFT                               12
+#define BCHP_NAND_TIMING_1_tCS_DEFAULT                             0x00000008
+
+/* NAND :: TIMING_1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_tCLH_MASK                               0x00000f00
+#define BCHP_NAND_TIMING_1_tCLH_SHIFT                              8
+#define BCHP_NAND_TIMING_1_tCLH_DEFAULT                            0x00000004
+
+/* NAND :: TIMING_1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_tALH_MASK                               0x000000f0
+#define BCHP_NAND_TIMING_1_tALH_SHIFT                              4
+#define BCHP_NAND_TIMING_1_tALH_DEFAULT                            0x00000005
+
+/* NAND :: TIMING_1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_tADL_MASK                               0x0000000f
+#define BCHP_NAND_TIMING_1_tADL_SHIFT                              0
+#define BCHP_NAND_TIMING_1_tADL_DEFAULT                            0x0000000b
+
+/***************************************************************************
+ *TIMING_2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CLK_SELECT_MASK                         0x80000000
+#define BCHP_NAND_TIMING_2_CLK_SELECT_SHIFT                        31
+#define BCHP_NAND_TIMING_2_CLK_SELECT_DEFAULT                      0x00000000
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_108                      0
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_216                      1
+
+/* NAND :: TIMING_2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_reserved0_MASK                          0x7fffe000
+#define BCHP_NAND_TIMING_2_reserved0_SHIFT                         13
+
+/* NAND :: TIMING_2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_tWB_MASK                                0x00001e00
+#define BCHP_NAND_TIMING_2_tWB_SHIFT                               9
+#define BCHP_NAND_TIMING_2_tWB_DEFAULT                             0x0000000f
+
+/* NAND :: TIMING_2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_tWHR_MASK                               0x000001f0
+#define BCHP_NAND_TIMING_2_tWHR_SHIFT                              4
+#define BCHP_NAND_TIMING_2_tWHR_DEFAULT                            0x00000009
+
+/* NAND :: TIMING_2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_tREAD_MASK                              0x0000000f
+#define BCHP_NAND_TIMING_2_tREAD_SHIFT                             0
+#define BCHP_NAND_TIMING_2_tREAD_DEFAULT                           0x00000006
+
+/***************************************************************************
+ *SEMAPHORE - Semaphore
+ ***************************************************************************/
+/* NAND :: SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_NAND_SEMAPHORE_reserved0_MASK                         0xffffff00
+#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT                        8
+
+/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK                    0x000000ff
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT                   0
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *FLASH_DEVICE_ID - Nand Flash Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK                      0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT                     24
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK                      0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT                     16
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK                      0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT                     8
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK                      0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT                     0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK                  0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT                 24
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK                  0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT                 16
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK                  0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT                 8
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK                  0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT                 0
+
+/***************************************************************************
+ *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
+ ***************************************************************************/
+/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT                8
+
+/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK                    0x000000ff
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT                   0
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *INTFC_STATUS - Nand Flash Interface Status
+ ***************************************************************************/
+/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK                     0x80000000
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT                    31
+
+/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK                    0x40000000
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT                   30
+
+/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK                    0x20000000
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT                   29
+
+/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK               0x10000000
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT              28
+
+/* NAND :: INTFC_STATUS :: ERASED [27:27] */
+#define BCHP_NAND_INTFC_STATUS_ERASED_MASK                         0x08000000
+#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT                        27
+
+/* NAND :: INTFC_STATUS :: reserved0 [26:08] */
+#define BCHP_NAND_INTFC_STATUS_reserved0_MASK                      0x07ffff00
+#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT                     8
+
+/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK                   0x000000ff
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT                  0
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ECC_CORR_ADDR - ECC Correctable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK                  0xfff80000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT                 19
+
+/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK                     0x00070000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT                    16
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT                  0x00000000
+
+/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK                0x0000ffff
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT               0
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT             0x00000000
+
+/***************************************************************************
+ *ECC_UNC_ADDR - ECC Uncorrectable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK                        0xffffffff
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT                       0
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *READ_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:05] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK               0xffffffe0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT              5
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD [04:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_MASK     0x0000001f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_SHIFT    0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_DEFAULT  0x00000001
+
+/***************************************************************************
+ *ONFI_STATUS - ONFI Status
+ ***************************************************************************/
+/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK                  0xf0000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT                 28
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT               0x00000000
+
+/* NAND :: ONFI_STATUS :: reserved0 [27:06] */
+#define BCHP_NAND_ONFI_STATUS_reserved0_MASK                       0x0fffffc0
+#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT                      6
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK              0x00000020
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT             5
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK              0x00000010
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT             4
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK              0x00000008
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT             3
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK              0x00000004
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT             2
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK              0x00000002
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT             1
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK              0x00000001
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT             0
+
+/***************************************************************************
+ *ONFI_DEBUG_DATA - ONFI Debug Data
+ ***************************************************************************/
+/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK             0xffffffff
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT            0
+
+/***************************************************************************
+ *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK               0xfff80000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT              19
+
+/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK                  0x00070000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT                 16
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT               0x00000000
+
+/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK             0x0000ffff
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT            0
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT          0x00000000
+
+/***************************************************************************
+ *FLASH_READ_ADDR - Flash Read Data Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT                    0
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK             0xfff80000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT            19
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK                0x00070000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT               16
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT             0x00000000
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK           0x0000ffff
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT          0
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_ADDR - Page Program Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK                   0xffffffff
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT                  0
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *COPY_BACK_EXT_ADDR - Copy Back Extended Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK                0xfff80000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT               19
+
+/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK                   0x00070000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT                  16
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT                0x00000000
+
+/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK              0x0000ffff
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT             0
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT           0x00000000
+
+/***************************************************************************
+ *COPY_BACK_ADDR - Copy Back Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK                      0xffffffff
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT                     0
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK              0xfff80000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT             19
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK                 0x00070000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT                16
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT              0x00000000
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK            0x0000ffff
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT           0
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_ADDR - Block Erase Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK                    0xffffffff
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT                   0
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
+ ***************************************************************************/
+/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *INV_READ_ADDR - Flash Invalid Data Address
+ ***************************************************************************/
+/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
+ ***************************************************************************/
+/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK                 0xffffffff
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT                0
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *ACC_CONTROL_CS1 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS1 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS1 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS1 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS1 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS1_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS1 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS1 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS1_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS1_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS1_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS1_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS1_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS1_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS1_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS1_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS1_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS1_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS1_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS1 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS1 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS1_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS2 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS2 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS2 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS2 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS2 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS2_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS2 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS2 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS2_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS2_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS2_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS2_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS2 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS2_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS2_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS2_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS2_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS2_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS2_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS2_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS2_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS3 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS3 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS3 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS3 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS3 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS3_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS3 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS3 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS3_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS3_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS3_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS3_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS3 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS3_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS3_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS3_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS3_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS3_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS3_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS3_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS3 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS3 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS3_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS4 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS4 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS4 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS4 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS4 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS4_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS4 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS4 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS4_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS4_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS4_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS4_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS4 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS4_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS4_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS4_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS4_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS4_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS4_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS4_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS4 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS4 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS4_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS5 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS5 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS5 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS5 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS5 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS5 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS5 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS5 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS5 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS5 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS5 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS5_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS5_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS5 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS5 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS5_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS5_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS5 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS5 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS5_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS5_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS5 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS5 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS5_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS5_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS5 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS5 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS5_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS5_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS5 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS5 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS5_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS5_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS5_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS5 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS5_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS5_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS5_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS5 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS5_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS5_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS5_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS5 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS5_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS5_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS5_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS5 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS5_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS5_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS5_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS5 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS5_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS5_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS5_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS5 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS5_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS5_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS5_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS5 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS5_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS5_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS5_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS5 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS5 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS5 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS5_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS5_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS5 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS5_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS5_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS5_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS5 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS5_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS5_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS5_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS5 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS5_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS5_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS5_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *LL_OP - Nand Flash Low Level Operation
+ ***************************************************************************/
+/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
+#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK                           0x80000000
+#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT                          31
+#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT                        0x00000000
+
+/* NAND :: LL_OP :: reserved0 [30:20] */
+#define BCHP_NAND_LL_OP_reserved0_MASK                             0x7ff00000
+#define BCHP_NAND_LL_OP_reserved0_SHIFT                            20
+
+/* NAND :: LL_OP :: CLE [19:19] */
+#define BCHP_NAND_LL_OP_CLE_MASK                                   0x00080000
+#define BCHP_NAND_LL_OP_CLE_SHIFT                                  19
+#define BCHP_NAND_LL_OP_CLE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: ALE [18:18] */
+#define BCHP_NAND_LL_OP_ALE_MASK                                   0x00040000
+#define BCHP_NAND_LL_OP_ALE_SHIFT                                  18
+#define BCHP_NAND_LL_OP_ALE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: WE [17:17] */
+#define BCHP_NAND_LL_OP_WE_MASK                                    0x00020000
+#define BCHP_NAND_LL_OP_WE_SHIFT                                   17
+#define BCHP_NAND_LL_OP_WE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: RE [16:16] */
+#define BCHP_NAND_LL_OP_RE_MASK                                    0x00010000
+#define BCHP_NAND_LL_OP_RE_SHIFT                                   16
+#define BCHP_NAND_LL_OP_RE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: DATA [15:00] */
+#define BCHP_NAND_LL_OP_DATA_MASK                                  0x0000ffff
+#define BCHP_NAND_LL_OP_DATA_SHIFT                                 0
+#define BCHP_NAND_LL_OP_DATA_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *LL_RDDATA - Nand Flash Low Level Read Data
+ ***************************************************************************/
+/* NAND :: LL_RDDATA :: reserved0 [31:16] */
+#define BCHP_NAND_LL_RDDATA_reserved0_MASK                         0xffff0000
+#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT                        16
+
+/* NAND :: LL_RDDATA :: DATA [15:00] */
+#define BCHP_NAND_LL_RDDATA_DATA_MASK                              0x0000ffff
+#define BCHP_NAND_LL_RDDATA_DATA_SHIFT                             0
+#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE                          0x0041ba00
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_START                         0
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_END                           127
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE                  32
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+/* NAND :: FLASH_CACHEi :: WORD [31:00] */
+#define BCHP_NAND_FLASH_CACHEi_WORD_MASK                           0xffffffff
+#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT                          0
+
+
+#endif /* #ifndef BCHP_NAND_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_pcie_dma.h b/include/linux/brcmstb/7425b0/bchp_pcie_dma.h
new file mode 100644
index 0000000..776cac1
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_pcie_dma.h
@@ -0,0 +1,707 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:44 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_PCIE_DMA_H__
+#define BCHP_PCIE_DMA_H__
+
+/***************************************************************************
+ *PCIE_DMA - PCI-E DMA Registers
+ ***************************************************************************/
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST0 0x00414400 /* Tx Descriptor List0 First Descriptor lower Address */
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_U_ADDR_LIST0 0x00414404 /* Tx Descriptor List0 First Descriptor Upper Address */
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST1 0x00414408 /* Tx Descriptor List1 First Descriptor Lower Address */
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_U_ADDR_LIST1 0x0041440c /* Tx Descriptor List1 First Descriptor Upper Address */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS   0x00414410 /* Tx Software Descriptor List Control and Status */
+#define BCHP_PCIE_DMA_TX_WAKE_CTRL               0x00414414 /* Tx Wake Control */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS            0x00414418 /* Tx Engine Error Status */
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR   0x0041441c /* Tx List0 Current Descriptor Lower Address */
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_U_ADDR   0x00414420 /* Tx List0 Current Descriptor Upper Address */
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_BYTE_CNT      0x00414424 /* Tx List0 Current Descriptor Byte Count */
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR   0x00414428 /* Tx List1 Current Descriptor Lower Address */
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_U_ADDR   0x0041442c /* Tx List1 Current Descriptor Upper Address */
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_BYTE_CNT      0x00414430 /* Tx List1 Current Descriptor Byte Count */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST0 0x00414434 /* Rx Descriptor List0 First Descriptor Lower Address */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_U_ADDR_LIST0 0x00414438 /* Rx Descriptor List0 First Descriptor Upper Address */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST1 0x0041443c /* Rx Descriptor List1 First Descriptor Lower Address */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_U_ADDR_LIST1 0x00414440 /* Rx Descriptor List1 First Descriptor Upper Address */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS   0x00414444 /* Rx Software Descriptor List Control and Status */
+#define BCHP_PCIE_DMA_RX_WAKE_CTRL               0x00414448 /* Rx DMA Wake Control */
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS            0x0041444c /* Rx Engine Error Status */
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR   0x00414450 /* Rx List0 Current Descriptor Lower Address */
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_U_ADDR   0x00414454 /* Rx List0 Current Descriptor Upper Address */
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_BYTE_CNT      0x00414458 /* Rx List0 Current Descriptor Byte Count */
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR   0x0041445c /* Rx List1 Current Descriptor Lower address */
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_U_ADDR   0x00414460 /* Rx List1 Current Descriptor Upper address */
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_BYTE_CNT      0x00414464 /* Rx List1 Current Descriptor Byte Count */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG      0x00414468 /* DMA Debug Options Register */
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS  0x0041446c /* Read Channel Error Status */
+
+/***************************************************************************
+ *TX_FIRST_DESC_L_ADDR_LIST0 - Tx Descriptor List0 First Descriptor lower Address
+ ***************************************************************************/
+/* PCIE_DMA :: TX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK    0xffffffe0
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT   5
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK    0x0000001e
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT   1
+
+/* PCIE_DMA :: TX_FIRST_DESC_L_ADDR_LIST0 :: TX_DESC_LIST0_VALID [00:00] */
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_MASK 0x00000001
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_SHIFT 0
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TX_FIRST_DESC_U_ADDR_LIST0 - Tx Descriptor List0 First Descriptor Upper Address
+ ***************************************************************************/
+/* PCIE_DMA :: TX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK    0xffffffff
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT   0
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TX_FIRST_DESC_L_ADDR_LIST1 - Tx Descriptor List1 First Descriptor Lower Address
+ ***************************************************************************/
+/* PCIE_DMA :: TX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK    0xffffffe0
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT   5
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK    0x0000001e
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT   1
+
+/* PCIE_DMA :: TX_FIRST_DESC_L_ADDR_LIST1 :: TX_DESC_LIST1_VALID [00:00] */
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_MASK 0x00000001
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_SHIFT 0
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TX_FIRST_DESC_U_ADDR_LIST1 - Tx Descriptor List1 First Descriptor Upper Address
+ ***************************************************************************/
+/* PCIE_DMA :: TX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK    0xffffffff
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT   0
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TX_SW_DESC_LIST_CTRL_STS - Tx Software Descriptor List Control and Status
+ ***************************************************************************/
+/* PCIE_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:14] */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved0_MASK      0xffffc000
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT     14
+
+/* PCIE_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DESC_ENDIAN_MODE [13:12] */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_MASK 0x00003000
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_SHIFT 12
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved1 [11:10] */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved1_MASK      0x00000c00
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved1_SHIFT     10
+
+/* PCIE_DMA :: TX_SW_DESC_LIST_CTRL_STS :: LOCAL_DESC [09:09] */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_MASK     0x00000200
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_SHIFT    9
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_DEFAULT  0x00000000
+
+/* PCIE_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DMA_MODE [08:08] */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_MODE_MASK       0x00000100
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_MODE_SHIFT      8
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_MODE_DEFAULT    0x00000000
+
+/* PCIE_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved2 [07:06] */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved2_MASK      0x000000c0
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved2_SHIFT     6
+
+/* PCIE_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DMA_STATUS [05:04] */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_MASK     0x00000030
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_SHIFT    4
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_DEFAULT  0x00000000
+
+/* PCIE_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK  0x00000004
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved3 [01:01] */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved3_MASK      0x00000002
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved3_SHIFT     1
+
+/* PCIE_DMA :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_RUN_STOP [00:00] */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK 0x00000001
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_SHIFT 0
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TX_WAKE_CTRL - Tx Wake Control
+ ***************************************************************************/
+/* PCIE_DMA :: TX_WAKE_CTRL :: reserved0 [31:02] */
+#define BCHP_PCIE_DMA_TX_WAKE_CTRL_reserved0_MASK                  0xfffffffc
+#define BCHP_PCIE_DMA_TX_WAKE_CTRL_reserved0_SHIFT                 2
+
+/* PCIE_DMA :: TX_WAKE_CTRL :: WAKE_MODE [01:01] */
+#define BCHP_PCIE_DMA_TX_WAKE_CTRL_WAKE_MODE_MASK                  0x00000002
+#define BCHP_PCIE_DMA_TX_WAKE_CTRL_WAKE_MODE_SHIFT                 1
+#define BCHP_PCIE_DMA_TX_WAKE_CTRL_WAKE_MODE_DEFAULT               0x00000000
+
+/* PCIE_DMA :: TX_WAKE_CTRL :: WAKE [00:00] */
+#define BCHP_PCIE_DMA_TX_WAKE_CTRL_WAKE_MASK                       0x00000001
+#define BCHP_PCIE_DMA_TX_WAKE_CTRL_WAKE_SHIFT                      0
+#define BCHP_PCIE_DMA_TX_WAKE_CTRL_WAKE_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *TX_ERROR_STATUS - Tx Engine Error Status
+ ***************************************************************************/
+/* PCIE_DMA :: TX_ERROR_STATUS :: reserved0 [31:10] */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_reserved0_MASK               0xfffffc00
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_reserved0_SHIFT              10
+
+/* PCIE_DMA :: TX_ERROR_STATUS :: TX_L1_DESC_TX_ABORT_ERRORS [09:09] */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_ERROR_STATUS :: reserved1 [08:08] */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_reserved1_MASK               0x00000100
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_reserved1_SHIFT              8
+
+/* PCIE_DMA :: TX_ERROR_STATUS :: TX_L0_DESC_TX_ABORT_ERRORS [07:07] */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_ERROR_STATUS :: reserved2 [06:06] */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_reserved2_MASK               0x00000040
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_reserved2_SHIFT              6
+
+/* PCIE_DMA :: TX_ERROR_STATUS :: TX_L1_DATA_TX_ABORT_ERRORS [05:05] */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L1_DATA_TX_ABORT_ERRORS_MASK 0x00000020
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L1_DATA_TX_ABORT_ERRORS_SHIFT 5
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L1_DATA_TX_ABORT_ERRORS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_ERROR_STATUS :: TX_L1_REPIN_ERRORS [04:04] */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L1_REPIN_ERRORS_MASK      0x00000010
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L1_REPIN_ERRORS_SHIFT     4
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L1_REPIN_ERRORS_DEFAULT   0x00000000
+
+/* PCIE_DMA :: TX_ERROR_STATUS :: reserved3 [03:03] */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_reserved3_MASK               0x00000008
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_reserved3_SHIFT              3
+
+/* PCIE_DMA :: TX_ERROR_STATUS :: TX_L0_DATA_TX_ABORT_ERRORS [02:02] */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L0_DATA_TX_ABORT_ERRORS_MASK 0x00000004
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L0_DATA_TX_ABORT_ERRORS_SHIFT 2
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L0_DATA_TX_ABORT_ERRORS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_ERROR_STATUS :: TX_L0_REPIN_ERRORS [01:01] */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L0_REPIN_ERRORS_MASK      0x00000002
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L0_REPIN_ERRORS_SHIFT     1
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L0_REPIN_ERRORS_DEFAULT   0x00000000
+
+/* PCIE_DMA :: TX_ERROR_STATUS :: reserved4 [00:00] */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_reserved4_MASK               0x00000001
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_reserved4_SHIFT              0
+
+/***************************************************************************
+ *TX_LIST0_CUR_DESC_L_ADDR - Tx List0 Current Descriptor Lower Address
+ ***************************************************************************/
+/* PCIE_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: TX_L0_CUR_DESC_L_ADDR [31:05] */
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_DESC_L_ADDR_SHIFT 5
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_DESC_L_ADDR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:04] */
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK      0x00000010
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT     4
+
+/* PCIE_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: TX_L0_CUR_LIST [03:03] */
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_LIST_MASK 0x00000008
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_LIST_SHIFT 3
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_LIST_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: TX_L0_CUR_IN_PROGRESS [02:02] */
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_IN_PROGRESS_MASK 0x00000004
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_IN_PROGRESS_SHIFT 2
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_IN_PROGRESS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: TX_L0_CUR_STATUS [01:00] */
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_STATUS_MASK 0x00000003
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_STATUS_SHIFT 0
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TX_LIST0_CUR_DESC_U_ADDR - Tx List0 Current Descriptor Upper Address
+ ***************************************************************************/
+/* PCIE_DMA :: TX_LIST0_CUR_DESC_U_ADDR :: TX_L0_CUR_DESC_U_ADDR [31:00] */
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_U_ADDR_TX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_U_ADDR_TX_L0_CUR_DESC_U_ADDR_SHIFT 0
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_U_ADDR_TX_L0_CUR_DESC_U_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TX_LIST0_CUR_BYTE_CNT - Tx List0 Current Descriptor Byte Count
+ ***************************************************************************/
+/* PCIE_DMA :: TX_LIST0_CUR_BYTE_CNT :: TX_L0_CUR_BYTE_CNT [31:00] */
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_BYTE_CNT_TX_L0_CUR_BYTE_CNT_MASK 0xffffffff
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_BYTE_CNT_TX_L0_CUR_BYTE_CNT_SHIFT 0
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_BYTE_CNT_TX_L0_CUR_BYTE_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TX_LIST1_CUR_DESC_L_ADDR - Tx List1 Current Descriptor Lower Address
+ ***************************************************************************/
+/* PCIE_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: TX_L1_CUR_DESC_L_ADDR [31:05] */
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_DESC_L_ADDR_SHIFT 5
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_DESC_L_ADDR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:04] */
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK      0x00000010
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT     4
+
+/* PCIE_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: TX_L1_CUR_LIST [03:03] */
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_LIST_MASK 0x00000008
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_LIST_SHIFT 3
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_LIST_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: TX_L1_CUR_IN_PROGRESS [02:02] */
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_IN_PROGRESS_MASK 0x00000004
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_IN_PROGRESS_SHIFT 2
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_IN_PROGRESS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: TX_L1_CUR_STATUS [01:00] */
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_STATUS_MASK 0x00000003
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_STATUS_SHIFT 0
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TX_LIST1_CUR_DESC_U_ADDR - Tx List1 Current Descriptor Upper Address
+ ***************************************************************************/
+/* PCIE_DMA :: TX_LIST1_CUR_DESC_U_ADDR :: TX_L1_CUR_DESC_U_ADDR [31:00] */
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_U_ADDR_TX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_U_ADDR_TX_L1_CUR_DESC_U_ADDR_SHIFT 0
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_U_ADDR_TX_L1_CUR_DESC_U_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TX_LIST1_CUR_BYTE_CNT - Tx List1 Current Descriptor Byte Count
+ ***************************************************************************/
+/* PCIE_DMA :: TX_LIST1_CUR_BYTE_CNT :: TX_L1_CUR_BYTE_CNT [31:00] */
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_BYTE_CNT_TX_L1_CUR_BYTE_CNT_MASK 0xffffffff
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_BYTE_CNT_TX_L1_CUR_BYTE_CNT_SHIFT 0
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_BYTE_CNT_TX_L1_CUR_BYTE_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_FIRST_DESC_L_ADDR_LIST0 - Rx Descriptor List0 First Descriptor Lower Address
+ ***************************************************************************/
+/* PCIE_DMA :: RX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK    0xffffffe0
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT   5
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK    0x0000001e
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT   1
+
+/* PCIE_DMA :: RX_FIRST_DESC_L_ADDR_LIST0 :: RX_DESC_LIST0_VALID [00:00] */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_MASK 0x00000001
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_SHIFT 0
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_FIRST_DESC_U_ADDR_LIST0 - Rx Descriptor List0 First Descriptor Upper Address
+ ***************************************************************************/
+/* PCIE_DMA :: RX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK    0xffffffff
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT   0
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_FIRST_DESC_L_ADDR_LIST1 - Rx Descriptor List1 First Descriptor Lower Address
+ ***************************************************************************/
+/* PCIE_DMA :: RX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK    0xffffffe0
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT   5
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK    0x0000001e
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT   1
+
+/* PCIE_DMA :: RX_FIRST_DESC_L_ADDR_LIST1 :: RX_DESC_LIST1_VALID [00:00] */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_MASK 0x00000001
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_SHIFT 0
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_FIRST_DESC_U_ADDR_LIST1 - Rx Descriptor List1 First Descriptor Upper Address
+ ***************************************************************************/
+/* PCIE_DMA :: RX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK    0xffffffff
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT   0
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_SW_DESC_LIST_CTRL_STS - Rx Software Descriptor List Control and Status
+ ***************************************************************************/
+/* PCIE_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:14] */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved0_MASK      0xffffc000
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT     14
+
+/* PCIE_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DESC_ENDIAN_MODE [13:12] */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_MASK 0x00003000
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_SHIFT 12
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved1 [11:10] */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved1_MASK      0x00000c00
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved1_SHIFT     10
+
+/* PCIE_DMA :: RX_SW_DESC_LIST_CTRL_STS :: LOCAL_DESC [09:09] */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_MASK     0x00000200
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_SHIFT    9
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_DEFAULT  0x00000000
+
+/* PCIE_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DMA_MODE [08:08] */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_MODE_MASK       0x00000100
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_MODE_SHIFT      8
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_MODE_DEFAULT    0x00000000
+
+/* PCIE_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved2 [07:06] */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved2_MASK      0x000000c0
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved2_SHIFT     6
+
+/* PCIE_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DMA_STATUS [05:04] */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_MASK     0x00000030
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_SHIFT    4
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_DEFAULT  0x00000000
+
+/* PCIE_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK  0x00000004
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved3 [01:01] */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved3_MASK      0x00000002
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved3_SHIFT     1
+
+/* PCIE_DMA :: RX_SW_DESC_LIST_CTRL_STS :: RX_DMA_RUN_STOP [00:00] */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_RX_DMA_RUN_STOP_MASK 0x00000001
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_RX_DMA_RUN_STOP_SHIFT 0
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_RX_DMA_RUN_STOP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_WAKE_CTRL - Rx DMA Wake Control
+ ***************************************************************************/
+/* PCIE_DMA :: RX_WAKE_CTRL :: reserved0 [31:02] */
+#define BCHP_PCIE_DMA_RX_WAKE_CTRL_reserved0_MASK                  0xfffffffc
+#define BCHP_PCIE_DMA_RX_WAKE_CTRL_reserved0_SHIFT                 2
+
+/* PCIE_DMA :: RX_WAKE_CTRL :: WAKE_MODE [01:01] */
+#define BCHP_PCIE_DMA_RX_WAKE_CTRL_WAKE_MODE_MASK                  0x00000002
+#define BCHP_PCIE_DMA_RX_WAKE_CTRL_WAKE_MODE_SHIFT                 1
+#define BCHP_PCIE_DMA_RX_WAKE_CTRL_WAKE_MODE_DEFAULT               0x00000000
+
+/* PCIE_DMA :: RX_WAKE_CTRL :: WAKE [00:00] */
+#define BCHP_PCIE_DMA_RX_WAKE_CTRL_WAKE_MASK                       0x00000001
+#define BCHP_PCIE_DMA_RX_WAKE_CTRL_WAKE_SHIFT                      0
+#define BCHP_PCIE_DMA_RX_WAKE_CTRL_WAKE_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *RX_ERROR_STATUS - Rx Engine Error Status
+ ***************************************************************************/
+/* PCIE_DMA :: RX_ERROR_STATUS :: reserved0 [31:10] */
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_reserved0_MASK               0xfffffc00
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_reserved0_SHIFT              10
+
+/* PCIE_DMA :: RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_ERROR_STATUS :: reserved1 [08:08] */
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_reserved1_MASK               0x00000100
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_reserved1_SHIFT              8
+
+/* PCIE_DMA :: RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_ERROR_STATUS :: reserved2 [06:06] */
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_reserved2_MASK               0x00000040
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_reserved2_SHIFT              6
+
+/* PCIE_DMA :: RX_ERROR_STATUS :: RX_L1_DATA_TX_ABORT_ERRORS [05:05] */
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L1_DATA_TX_ABORT_ERRORS_MASK 0x00000020
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L1_DATA_TX_ABORT_ERRORS_SHIFT 5
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L1_DATA_TX_ABORT_ERRORS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_ERROR_STATUS :: reserved3 [04:03] */
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_reserved3_MASK               0x00000018
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_reserved3_SHIFT              3
+
+/* PCIE_DMA :: RX_ERROR_STATUS :: RX_L0_DATA_TX_ABORT_ERRORS [02:02] */
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L0_DATA_TX_ABORT_ERRORS_MASK 0x00000004
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L0_DATA_TX_ABORT_ERRORS_SHIFT 2
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L0_DATA_TX_ABORT_ERRORS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_ERROR_STATUS :: reserved4 [01:00] */
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_reserved4_MASK               0x00000003
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_reserved4_SHIFT              0
+
+/***************************************************************************
+ *RX_LIST0_CUR_DESC_L_ADDR - Rx List0 Current Descriptor Lower Address
+ ***************************************************************************/
+/* PCIE_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_DESC_L_ADDR [31:05] */
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_SHIFT 5
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:04] */
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK      0x00000010
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT     4
+
+/* PCIE_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_LIST [03:03] */
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_LIST_MASK 0x00000008
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_LIST_SHIFT 3
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_LIST_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_IN_PROGRESS [02:02] */
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_IN_PROGRESS_MASK 0x00000004
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_IN_PROGRESS_SHIFT 2
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_IN_PROGRESS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_STATUS [01:00] */
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_STATUS_MASK 0x00000003
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_STATUS_SHIFT 0
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_LIST0_CUR_DESC_U_ADDR - Rx List0 Current Descriptor Upper Address
+ ***************************************************************************/
+/* PCIE_DMA :: RX_LIST0_CUR_DESC_U_ADDR :: RX_L0_CUR_DESC_U_ADDR [31:00] */
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_SHIFT 0
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_LIST0_CUR_BYTE_CNT - Rx List0 Current Descriptor Byte Count
+ ***************************************************************************/
+/* PCIE_DMA :: RX_LIST0_CUR_BYTE_CNT :: RX_L0_CUR_BYTE_CNT [31:00] */
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_MASK 0xffffffff
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_SHIFT 0
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_LIST1_CUR_DESC_L_ADDR - Rx List1 Current Descriptor Lower address
+ ***************************************************************************/
+/* PCIE_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_DESC_L_ADDR [31:05] */
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_SHIFT 5
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:04] */
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK      0x00000010
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT     4
+
+/* PCIE_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_LIST [03:03] */
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_LIST_MASK 0x00000008
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_LIST_SHIFT 3
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_LIST_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_IN_PROGRESS [02:02] */
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_IN_PROGRESS_MASK 0x00000004
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_IN_PROGRESS_SHIFT 2
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_IN_PROGRESS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_STATUS [01:00] */
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_STATUS_MASK 0x00000003
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_STATUS_SHIFT 0
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_LIST1_CUR_DESC_U_ADDR - Rx List1 Current Descriptor Upper address
+ ***************************************************************************/
+/* PCIE_DMA :: RX_LIST1_CUR_DESC_U_ADDR :: RX_L1_CUR_DESC_U_ADDR [31:00] */
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_SHIFT 0
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_LIST1_CUR_BYTE_CNT - Rx List1 Current Descriptor Byte Count
+ ***************************************************************************/
+/* PCIE_DMA :: RX_LIST1_CUR_BYTE_CNT :: RX_L1_CUR_BYTE_CNT [31:00] */
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_MASK 0xffffffff
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_SHIFT 0
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DMA_DEBUG_OPTIONS_REG - DMA Debug Options Register
+ ***************************************************************************/
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_SOFT_RST [31:31] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_MASK 0x80000000
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_SHIFT 31
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_SOFT_RST [30:30] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_MASK 0x40000000
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_SHIFT 30
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST [29:29] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_MASK 0x20000000
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_SHIFT 29
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST [28:28] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_MASK 0x10000000
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_SHIFT 28
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_0 [27:10] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_MASK  0x0ffffc00
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_SHIFT 10
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SPQ_SNAP_PW_DIS [09:09] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SPQ_SNAP_PW_DIS_MASK 0x00000200
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SPQ_SNAP_PW_DIS_SHIFT 9
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SPQ_SNAP_PW_DIS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_OUTCP_Q_RO [08:08] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_OUTCP_Q_RO_MASK 0x00000100
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_OUTCP_Q_RO_SHIFT 8
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_OUTCP_Q_RO_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_NO_TX_DESC [07:07] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_TX_DESC_MASK 0x00000080
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_TX_DESC_SHIFT 7
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_TX_DESC_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_NO_RX_DESC [06:06] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_RX_DESC_MASK 0x00000040
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_RX_DESC_SHIFT 6
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_RX_DESC_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SEL_RX_CNT [05:05] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_RX_CNT_MASK 0x00000020
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_RX_CNT_SHIFT 5
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_RX_CNT_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_EN_RX_DMA_XFER_CNT [04:04] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_MASK 0x00000010
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_SHIFT 4
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SEL_TX_CNT [03:03] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_TX_CNT_MASK 0x00000008
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_TX_CNT_SHIFT 3
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_TX_CNT_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_RD_Q [02:02] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_MASK 0x00000004
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_SHIFT 2
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_WR_Q [01:01] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_MASK 0x00000002
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_SHIFT 1
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RD_Q_RO [00:00] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RD_Q_RO_MASK 0x00000001
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RD_Q_RO_SHIFT 0
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RD_Q_RO_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_CHANNEL_ERROR_STATUS - Read Channel Error Status
+ ***************************************************************************/
+/* PCIE_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_7 [31:28] */
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_MASK 0xf0000000
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_SHIFT 28
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_DEFAULT 0x00000000
+
+/* PCIE_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_6 [27:24] */
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_MASK 0x0f000000
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_SHIFT 24
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_DEFAULT 0x00000000
+
+/* PCIE_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_5 [23:20] */
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_MASK 0x00f00000
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_SHIFT 20
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_DEFAULT 0x00000000
+
+/* PCIE_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_4 [19:16] */
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_MASK 0x000f0000
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_SHIFT 16
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_DEFAULT 0x00000000
+
+/* PCIE_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_3 [15:12] */
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_MASK 0x0000f000
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_SHIFT 12
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_DEFAULT 0x00000000
+
+/* PCIE_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_2 [11:08] */
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_MASK 0x00000f00
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_SHIFT 8
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_DEFAULT 0x00000000
+
+/* PCIE_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_1 [07:04] */
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_MASK 0x000000f0
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_SHIFT 4
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_DEFAULT 0x00000000
+
+/* PCIE_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_0 [03:00] */
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_MASK 0x0000000f
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_SHIFT 0
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_PCIE_DMA_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_pcie_ext_cfg.h b/include/linux/brcmstb/7425b0/bchp_pcie_ext_cfg.h
new file mode 100644
index 0000000..4c1ed11
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_pcie_ext_cfg.h
@@ -0,0 +1,100 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:43 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_PCIE_EXT_CFG_H__
+#define BCHP_PCIE_EXT_CFG_H__
+
+/***************************************************************************
+ *PCIE_EXT_CFG - HIF PCIE EXTERNAL CFG Registers
+ ***************************************************************************/
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX     0x00418300 /* PCIE External Configuration Access Index */
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_DATA      0x00418304 /* PCIE External Configuration Access Data */
+#define BCHP_PCIE_EXT_CFG_SCRATCH                0x00418308 /* Scratch Register */
+
+/***************************************************************************
+ *PCIE_EXT_CFG_INDEX - PCIE External Configuration Access Index
+ ***************************************************************************/
+/* PCIE_EXT_CFG :: PCIE_EXT_CFG_INDEX :: UNUSED_1 [31:28] */
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_1_MASK         0xf0000000
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_1_SHIFT        28
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_1_DEFAULT      0x00000000
+
+/* PCIE_EXT_CFG :: PCIE_EXT_CFG_INDEX :: BUS_NUM [27:20] */
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_BUS_NUM_MASK          0x0ff00000
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_BUS_NUM_SHIFT         20
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_BUS_NUM_DEFAULT       0x00000000
+
+/* PCIE_EXT_CFG :: PCIE_EXT_CFG_INDEX :: DEV_NUM [19:15] */
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_DEV_NUM_MASK          0x000f8000
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_DEV_NUM_SHIFT         15
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_DEV_NUM_DEFAULT       0x00000000
+
+/* PCIE_EXT_CFG :: PCIE_EXT_CFG_INDEX :: FUNC_NUM [14:12] */
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_FUNC_NUM_MASK         0x00007000
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_FUNC_NUM_SHIFT        12
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_FUNC_NUM_DEFAULT      0x00000000
+
+/* PCIE_EXT_CFG :: PCIE_EXT_CFG_INDEX :: REG_NUM [11:02] */
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_REG_NUM_MASK          0x00000ffc
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_REG_NUM_SHIFT         2
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_REG_NUM_DEFAULT       0x00000000
+
+/* PCIE_EXT_CFG :: PCIE_EXT_CFG_INDEX :: UNUSED_0 [01:00] */
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_0_MASK         0x00000003
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_0_SHIFT        0
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_0_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PCIE_EXT_CFG_DATA - PCIE External Configuration Access Data
+ ***************************************************************************/
+/* PCIE_EXT_CFG :: PCIE_EXT_CFG_DATA :: DATA [31:00] */
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_DATA_DATA_MASK              0xffffffff
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_DATA_DATA_SHIFT             0
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_DATA_DATA_DEFAULT           0x00000000
+
+/***************************************************************************
+ *SCRATCH - Scratch Register
+ ***************************************************************************/
+/* PCIE_EXT_CFG :: SCRATCH :: DATA [31:00] */
+#define BCHP_PCIE_EXT_CFG_SCRATCH_DATA_MASK                        0xffffffff
+#define BCHP_PCIE_EXT_CFG_SCRATCH_DATA_SHIFT                       0
+#define BCHP_PCIE_EXT_CFG_SCRATCH_DATA_DEFAULT                     0x00000000
+
+#endif /* #ifndef BCHP_PCIE_EXT_CFG_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_pcie_intr2.h b/include/linux/brcmstb/7425b0/bchp_pcie_intr2.h
new file mode 100644
index 0000000..7f51d1b
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_pcie_intr2.h
@@ -0,0 +1,2016 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:43 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_PCIE_INTR2_H__
+#define BCHP_PCIE_INTR2_H__
+
+/***************************************************************************
+ *PCIE_INTR2 - PCI-E L2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_PCIE_INTR2_CPU_STATUS               0x00414300 /* CPU interrupt Status Register */
+#define BCHP_PCIE_INTR2_CPU_SET                  0x00414304 /* CPU interrupt Set Register */
+#define BCHP_PCIE_INTR2_CPU_CLEAR                0x00414308 /* CPU interrupt Clear Register */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS          0x0041430c /* CPU interrupt Mask Status Register */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET             0x00414310 /* CPU interrupt Mask Set Register */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR           0x00414314 /* CPU interrupt Mask Clear Register */
+#define BCHP_PCIE_INTR2_PCI_STATUS               0x00414318 /* PCI interrupt Status Register */
+#define BCHP_PCIE_INTR2_PCI_SET                  0x0041431c /* PCI interrupt Set Register */
+#define BCHP_PCIE_INTR2_PCI_CLEAR                0x00414320 /* PCI interrupt Clear Register */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS          0x00414324 /* PCI interrupt Mask Status Register */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET             0x00414328 /* PCI interrupt Mask Set Register */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR           0x0041432c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: CPU_STATUS :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR07_MASK                 0x80000000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR07_SHIFT                31
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR07_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR06_MASK                 0x40000000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR06_SHIFT                30
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR06_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR05_MASK                 0x20000000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR05_SHIFT                29
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR05_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR04_MASK                 0x10000000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR04_SHIFT                28
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR04_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR03_MASK                 0x08000000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR03_SHIFT                27
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR03_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR02_MASK                 0x04000000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR02_SHIFT                26
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR02_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR01_MASK                 0x02000000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR01_SHIFT                25
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR01_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR00_MASK                 0x01000000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR00_SHIFT                24
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR00_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_23_MASK              0x00800000
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_23_SHIFT             23
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_23_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_22_MASK              0x00400000
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_22_SHIFT             22
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_22_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_21_MASK              0x00200000
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_21_SHIFT             21
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_21_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_20_MASK              0x00100000
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_20_SHIFT             20
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_20_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_3_MASK                  0x00080000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_3_SHIFT                 19
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_3_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_2_MASK                  0x00040000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_2_SHIFT                 18
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_2_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_1_MASK                  0x00020000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_1_SHIFT                 17
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_1_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_0_MASK                  0x00010000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_0_SHIFT                 16
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_0_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_FWD_ERR_MASK          0x00008000
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_FWD_ERR_SHIFT         15
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_FWD_ERR_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_RETRY_TIMEOUT_MASK    0x00004000
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_RETRY_TIMEOUT_SHIFT   14
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_CA_ATTN_MASK          0x00002000
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_CA_ATTN_SHIFT         13
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_CA_ATTN_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_UR_ATTN_MASK          0x00001000
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_UR_ATTN_SHIFT         12
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_UR_ATTN_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_11_MASK              0x00000800
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_11_SHIFT             11
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_11_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_10_MASK              0x00000400
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_10_SHIFT             10
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_10_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_TGT_BAD_ACCESS_MASK        0x00000200
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_TGT_BAD_ACCESS_SHIFT       9
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_TGT_BAD_ACCESS_DEFAULT     0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_TGT_BAD_ADDRESS_MASK       0x00000100
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_TGT_BAD_ADDRESS_SHIFT      8
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_TGT_BAD_ADDRESS_DEFAULT    0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_RX_DMA_ERR_INTR_MASK         0x00000080
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_RX_DMA_ERR_INTR_SHIFT        7
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_RX_DMA_ERR_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_RX_DMA_DONE_INTR_MASK        0x00000040
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_RX_DMA_DONE_INTR_SHIFT       6
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_RX_DMA_DONE_INTR_DEFAULT     0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_TX_DMA_ERR_INTR_MASK         0x00000020
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_TX_DMA_ERR_INTR_SHIFT        5
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_TX_DMA_ERR_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_TX_DMA_DONE_INTR_MASK        0x00000010
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_TX_DMA_DONE_INTR_SHIFT       4
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_TX_DMA_DONE_INTR_DEFAULT     0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_RX_DMA_ERR_INTR_MASK         0x00000008
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_RX_DMA_ERR_INTR_SHIFT        3
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_RX_DMA_ERR_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_RX_DMA_DONE_INTR_MASK        0x00000004
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_RX_DMA_DONE_INTR_SHIFT       2
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_RX_DMA_DONE_INTR_DEFAULT     0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_TX_DMA_ERR_INTR_MASK         0x00000002
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_TX_DMA_ERR_INTR_SHIFT        1
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_TX_DMA_ERR_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_TX_DMA_DONE_INTR_MASK        0x00000001
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_TX_DMA_DONE_INTR_SHIFT       0
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_TX_DMA_DONE_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: CPU_SET :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR07_MASK                    0x80000000
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR07_SHIFT                   31
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR07_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR06_MASK                    0x40000000
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR06_SHIFT                   30
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR06_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR05_MASK                    0x20000000
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR05_SHIFT                   29
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR05_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR04_MASK                    0x10000000
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR04_SHIFT                   28
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR04_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR03_MASK                    0x08000000
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR03_SHIFT                   27
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR03_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR02_MASK                    0x04000000
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR02_SHIFT                   26
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR02_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR01_MASK                    0x02000000
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR01_SHIFT                   25
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR01_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR00_MASK                    0x01000000
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR00_SHIFT                   24
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR00_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_23_MASK                 0x00800000
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_23_SHIFT                23
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_23_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_22_MASK                 0x00400000
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_22_SHIFT                22
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_22_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_21_MASK                 0x00200000
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_21_SHIFT                21
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_21_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_20_MASK                 0x00100000
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_20_SHIFT                20
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_20_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_3_MASK                     0x00080000
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_3_SHIFT                    19
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_3_DEFAULT                  0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_2_MASK                     0x00040000
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_2_SHIFT                    18
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_2_DEFAULT                  0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_1_MASK                     0x00020000
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_1_SHIFT                    17
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_1_DEFAULT                  0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_0_MASK                     0x00010000
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_0_SHIFT                    16
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_0_DEFAULT                  0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_FWD_ERR_MASK             0x00008000
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_FWD_ERR_SHIFT            15
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_FWD_ERR_DEFAULT          0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_RETRY_TIMEOUT_MASK       0x00004000
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_RETRY_TIMEOUT_SHIFT      14
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT    0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_CA_ATTN_MASK             0x00002000
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_CA_ATTN_SHIFT            13
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_CA_ATTN_DEFAULT          0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_UR_ATTN_MASK             0x00001000
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_UR_ATTN_SHIFT            12
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_UR_ATTN_DEFAULT          0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_11_MASK                 0x00000800
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_11_SHIFT                11
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_11_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_10_MASK                 0x00000400
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_10_SHIFT                10
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_10_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_TGT_BAD_ACCESS_MASK           0x00000200
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_TGT_BAD_ACCESS_SHIFT          9
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_TGT_BAD_ACCESS_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_TGT_BAD_ADDRESS_MASK          0x00000100
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_TGT_BAD_ADDRESS_SHIFT         8
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_TGT_BAD_ADDRESS_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_CPU_SET_L1_RX_DMA_ERR_INTR_MASK            0x00000080
+#define BCHP_PCIE_INTR2_CPU_SET_L1_RX_DMA_ERR_INTR_SHIFT           7
+#define BCHP_PCIE_INTR2_CPU_SET_L1_RX_DMA_ERR_INTR_DEFAULT         0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_CPU_SET_L1_RX_DMA_DONE_INTR_MASK           0x00000040
+#define BCHP_PCIE_INTR2_CPU_SET_L1_RX_DMA_DONE_INTR_SHIFT          6
+#define BCHP_PCIE_INTR2_CPU_SET_L1_RX_DMA_DONE_INTR_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_CPU_SET_L1_TX_DMA_ERR_INTR_MASK            0x00000020
+#define BCHP_PCIE_INTR2_CPU_SET_L1_TX_DMA_ERR_INTR_SHIFT           5
+#define BCHP_PCIE_INTR2_CPU_SET_L1_TX_DMA_ERR_INTR_DEFAULT         0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_CPU_SET_L1_TX_DMA_DONE_INTR_MASK           0x00000010
+#define BCHP_PCIE_INTR2_CPU_SET_L1_TX_DMA_DONE_INTR_SHIFT          4
+#define BCHP_PCIE_INTR2_CPU_SET_L1_TX_DMA_DONE_INTR_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_CPU_SET_L0_RX_DMA_ERR_INTR_MASK            0x00000008
+#define BCHP_PCIE_INTR2_CPU_SET_L0_RX_DMA_ERR_INTR_SHIFT           3
+#define BCHP_PCIE_INTR2_CPU_SET_L0_RX_DMA_ERR_INTR_DEFAULT         0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_CPU_SET_L0_RX_DMA_DONE_INTR_MASK           0x00000004
+#define BCHP_PCIE_INTR2_CPU_SET_L0_RX_DMA_DONE_INTR_SHIFT          2
+#define BCHP_PCIE_INTR2_CPU_SET_L0_RX_DMA_DONE_INTR_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_CPU_SET_L0_TX_DMA_ERR_INTR_MASK            0x00000002
+#define BCHP_PCIE_INTR2_CPU_SET_L0_TX_DMA_ERR_INTR_SHIFT           1
+#define BCHP_PCIE_INTR2_CPU_SET_L0_TX_DMA_ERR_INTR_DEFAULT         0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_CPU_SET_L0_TX_DMA_DONE_INTR_MASK           0x00000001
+#define BCHP_PCIE_INTR2_CPU_SET_L0_TX_DMA_DONE_INTR_SHIFT          0
+#define BCHP_PCIE_INTR2_CPU_SET_L0_TX_DMA_DONE_INTR_DEFAULT        0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: CPU_CLEAR :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR07_MASK                  0x80000000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR07_SHIFT                 31
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR07_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR06_MASK                  0x40000000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR06_SHIFT                 30
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR06_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR05_MASK                  0x20000000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR05_SHIFT                 29
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR05_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR04_MASK                  0x10000000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR04_SHIFT                 28
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR04_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR03_MASK                  0x08000000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR03_SHIFT                 27
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR03_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR02_MASK                  0x04000000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR02_SHIFT                 26
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR02_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR01_MASK                  0x02000000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR01_SHIFT                 25
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR01_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR00_MASK                  0x01000000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR00_SHIFT                 24
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR00_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_23_MASK               0x00800000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_23_SHIFT              23
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_23_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_22_MASK               0x00400000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_22_SHIFT              22
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_22_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_21_MASK               0x00200000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_21_SHIFT              21
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_21_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_20_MASK               0x00100000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_20_SHIFT              20
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_20_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_3_MASK                   0x00080000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_3_SHIFT                  19
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_3_DEFAULT                0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_2_MASK                   0x00040000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_2_SHIFT                  18
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_2_DEFAULT                0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_1_MASK                   0x00020000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_1_SHIFT                  17
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_1_DEFAULT                0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_0_MASK                   0x00010000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_0_SHIFT                  16
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_0_DEFAULT                0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_FWD_ERR_MASK           0x00008000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_FWD_ERR_SHIFT          15
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_FWD_ERR_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_MASK     0x00004000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_SHIFT    14
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT  0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_CA_ATTN_MASK           0x00002000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_CA_ATTN_SHIFT          13
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_CA_ATTN_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_UR_ATTN_MASK           0x00001000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_UR_ATTN_SHIFT          12
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_UR_ATTN_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_11_MASK               0x00000800
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_11_SHIFT              11
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_11_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_10_MASK               0x00000400
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_10_SHIFT              10
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_10_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ACCESS_MASK         0x00000200
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ACCESS_SHIFT        9
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ACCESS_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ADDRESS_MASK        0x00000100
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ADDRESS_SHIFT       8
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ADDRESS_DEFAULT     0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_RX_DMA_ERR_INTR_MASK          0x00000080
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_RX_DMA_ERR_INTR_SHIFT         7
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_RX_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_RX_DMA_DONE_INTR_MASK         0x00000040
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_RX_DMA_DONE_INTR_SHIFT        6
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_RX_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_TX_DMA_ERR_INTR_MASK          0x00000020
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_TX_DMA_ERR_INTR_SHIFT         5
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_TX_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_TX_DMA_DONE_INTR_MASK         0x00000010
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_TX_DMA_DONE_INTR_SHIFT        4
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_TX_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_RX_DMA_ERR_INTR_MASK          0x00000008
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_RX_DMA_ERR_INTR_SHIFT         3
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_RX_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_RX_DMA_DONE_INTR_MASK         0x00000004
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_RX_DMA_DONE_INTR_SHIFT        2
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_RX_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_TX_DMA_ERR_INTR_MASK          0x00000002
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_TX_DMA_ERR_INTR_SHIFT         1
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_TX_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_TX_DMA_DONE_INTR_MASK         0x00000001
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_TX_DMA_DONE_INTR_SHIFT        0
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_TX_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR07_MASK            0x80000000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR07_SHIFT           31
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR07_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR06_MASK            0x40000000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR06_SHIFT           30
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR06_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR05_MASK            0x20000000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR05_SHIFT           29
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR05_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR04_MASK            0x10000000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR04_SHIFT           28
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR04_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR03_MASK            0x08000000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR03_SHIFT           27
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR03_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR02_MASK            0x04000000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR02_SHIFT           26
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR02_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR01_MASK            0x02000000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR01_SHIFT           25
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR01_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR00_MASK            0x01000000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR00_SHIFT           24
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR00_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_23_MASK         0x00800000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_23_SHIFT        23
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_23_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_22_MASK         0x00400000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_22_SHIFT        22
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_22_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_21_MASK         0x00200000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_21_SHIFT        21
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_21_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_20_MASK         0x00100000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_20_SHIFT        20
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_20_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_3_MASK             0x00080000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_3_SHIFT            19
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_3_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_2_MASK             0x00040000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_2_SHIFT            18
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_2_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_1_MASK             0x00020000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_1_SHIFT            17
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_1_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_0_MASK             0x00010000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_0_SHIFT            16
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_0_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_FWD_ERR_MASK     0x00008000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_FWD_ERR_SHIFT    15
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_FWD_ERR_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_CA_ATTN_MASK     0x00002000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_CA_ATTN_SHIFT    13
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_CA_ATTN_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_UR_ATTN_MASK     0x00001000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_UR_ATTN_SHIFT    12
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_UR_ATTN_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_11_MASK         0x00000800
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_11_SHIFT        11
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_11_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_10_MASK         0x00000400
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_10_SHIFT        10
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_10_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ACCESS_MASK   0x00000200
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ACCESS_SHIFT  9
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_MASK  0x00000100
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_SHIFT 8
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_RX_DMA_ERR_INTR_MASK    0x00000080
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_RX_DMA_ERR_INTR_SHIFT   7
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_RX_DMA_DONE_INTR_MASK   0x00000040
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_RX_DMA_DONE_INTR_SHIFT  6
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_TX_DMA_ERR_INTR_MASK    0x00000020
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_TX_DMA_ERR_INTR_SHIFT   5
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_TX_DMA_DONE_INTR_MASK   0x00000010
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_TX_DMA_DONE_INTR_SHIFT  4
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_RX_DMA_ERR_INTR_MASK    0x00000008
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_RX_DMA_ERR_INTR_SHIFT   3
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_RX_DMA_DONE_INTR_MASK   0x00000004
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_RX_DMA_DONE_INTR_SHIFT  2
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_TX_DMA_ERR_INTR_MASK    0x00000002
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_TX_DMA_ERR_INTR_SHIFT   1
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_TX_DMA_DONE_INTR_MASK   0x00000001
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_TX_DMA_DONE_INTR_SHIFT  0
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: CPU_MASK_SET :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR07_MASK               0x80000000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR07_SHIFT              31
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR07_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR06_MASK               0x40000000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR06_SHIFT              30
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR06_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR05_MASK               0x20000000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR05_SHIFT              29
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR05_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR04_MASK               0x10000000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR04_SHIFT              28
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR04_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR03_MASK               0x08000000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR03_SHIFT              27
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR03_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR02_MASK               0x04000000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR02_SHIFT              26
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR02_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR01_MASK               0x02000000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR01_SHIFT              25
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR01_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR00_MASK               0x01000000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR00_SHIFT              24
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR00_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_23_MASK            0x00800000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_23_SHIFT           23
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_23_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_22_MASK            0x00400000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_22_SHIFT           22
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_22_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_21_MASK            0x00200000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_21_SHIFT           21
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_21_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_20_MASK            0x00100000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_20_SHIFT           20
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_20_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_3_MASK                0x00080000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_3_SHIFT               19
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_3_DEFAULT             0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_2_MASK                0x00040000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_2_SHIFT               18
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_2_DEFAULT             0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_1_MASK                0x00020000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_1_SHIFT               17
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_1_DEFAULT             0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_0_MASK                0x00010000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_0_SHIFT               16
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_0_DEFAULT             0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_FWD_ERR_MASK        0x00008000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_FWD_ERR_SHIFT       15
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_FWD_ERR_DEFAULT     0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_MASK  0x00004000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_CA_ATTN_MASK        0x00002000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_CA_ATTN_SHIFT       13
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_CA_ATTN_DEFAULT     0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_UR_ATTN_MASK        0x00001000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_UR_ATTN_SHIFT       12
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_UR_ATTN_DEFAULT     0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_11_MASK            0x00000800
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_11_SHIFT           11
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_11_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_10_MASK            0x00000400
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_10_SHIFT           10
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_10_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ACCESS_MASK      0x00000200
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ACCESS_SHIFT     9
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ACCESS_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ADDRESS_MASK     0x00000100
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ADDRESS_SHIFT    8
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ADDRESS_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_RX_DMA_ERR_INTR_MASK       0x00000080
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_RX_DMA_ERR_INTR_SHIFT      7
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_RX_DMA_ERR_INTR_DEFAULT    0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_RX_DMA_DONE_INTR_MASK      0x00000040
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_RX_DMA_DONE_INTR_SHIFT     6
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_RX_DMA_DONE_INTR_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_TX_DMA_ERR_INTR_MASK       0x00000020
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_TX_DMA_ERR_INTR_SHIFT      5
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_TX_DMA_ERR_INTR_DEFAULT    0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_TX_DMA_DONE_INTR_MASK      0x00000010
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_TX_DMA_DONE_INTR_SHIFT     4
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_TX_DMA_DONE_INTR_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_RX_DMA_ERR_INTR_MASK       0x00000008
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_RX_DMA_ERR_INTR_SHIFT      3
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_RX_DMA_ERR_INTR_DEFAULT    0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_RX_DMA_DONE_INTR_MASK      0x00000004
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_RX_DMA_DONE_INTR_SHIFT     2
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_RX_DMA_DONE_INTR_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_TX_DMA_ERR_INTR_MASK       0x00000002
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_TX_DMA_ERR_INTR_SHIFT      1
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_TX_DMA_ERR_INTR_DEFAULT    0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_TX_DMA_DONE_INTR_MASK      0x00000001
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_TX_DMA_DONE_INTR_SHIFT     0
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_TX_DMA_DONE_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR07_MASK             0x80000000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR07_SHIFT            31
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR07_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR06_MASK             0x40000000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR06_SHIFT            30
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR06_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR05_MASK             0x20000000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR05_SHIFT            29
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR05_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR04_MASK             0x10000000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR04_SHIFT            28
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR04_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR03_MASK             0x08000000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR03_SHIFT            27
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR03_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR02_MASK             0x04000000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR02_SHIFT            26
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR02_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR01_MASK             0x02000000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR01_SHIFT            25
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR01_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR00_MASK             0x01000000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR00_SHIFT            24
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR00_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_23_MASK          0x00800000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_23_SHIFT         23
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_23_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_22_MASK          0x00400000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_22_SHIFT         22
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_22_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_21_MASK          0x00200000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_21_SHIFT         21
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_21_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_20_MASK          0x00100000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_20_SHIFT         20
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_20_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_3_MASK              0x00080000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_3_SHIFT             19
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_3_DEFAULT           0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_2_MASK              0x00040000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_2_SHIFT             18
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_2_DEFAULT           0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_1_MASK              0x00020000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_1_SHIFT             17
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_1_DEFAULT           0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_0_MASK              0x00010000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_0_SHIFT             16
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_0_DEFAULT           0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_FWD_ERR_MASK      0x00008000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_FWD_ERR_SHIFT     15
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_FWD_ERR_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_CA_ATTN_MASK      0x00002000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_CA_ATTN_SHIFT     13
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_CA_ATTN_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_UR_ATTN_MASK      0x00001000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_UR_ATTN_SHIFT     12
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_UR_ATTN_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_11_MASK          0x00000800
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_11_SHIFT         11
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_11_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_10_MASK          0x00000400
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_10_SHIFT         10
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_10_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_MASK    0x00000200
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_SHIFT   9
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_MASK   0x00000100
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_SHIFT  8
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_ERR_INTR_MASK     0x00000080
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_ERR_INTR_SHIFT    7
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_ERR_INTR_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_DONE_INTR_MASK    0x00000040
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_DONE_INTR_SHIFT   6
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_ERR_INTR_MASK     0x00000020
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_ERR_INTR_SHIFT    5
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_ERR_INTR_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_DONE_INTR_MASK    0x00000010
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_DONE_INTR_SHIFT   4
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_ERR_INTR_MASK     0x00000008
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_ERR_INTR_SHIFT    3
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_ERR_INTR_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_DONE_INTR_MASK    0x00000004
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_DONE_INTR_SHIFT   2
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_ERR_INTR_MASK     0x00000002
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_ERR_INTR_SHIFT    1
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_ERR_INTR_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_DONE_INTR_MASK    0x00000001
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_DONE_INTR_SHIFT   0
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: PCI_STATUS :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR07_MASK                 0x80000000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR07_SHIFT                31
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR07_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR06_MASK                 0x40000000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR06_SHIFT                30
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR06_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR05_MASK                 0x20000000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR05_SHIFT                29
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR05_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR04_MASK                 0x10000000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR04_SHIFT                28
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR04_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR03_MASK                 0x08000000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR03_SHIFT                27
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR03_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR02_MASK                 0x04000000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR02_SHIFT                26
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR02_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR01_MASK                 0x02000000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR01_SHIFT                25
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR01_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR00_MASK                 0x01000000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR00_SHIFT                24
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR00_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_23_MASK              0x00800000
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_23_SHIFT             23
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_23_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_22_MASK              0x00400000
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_22_SHIFT             22
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_22_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_21_MASK              0x00200000
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_21_SHIFT             21
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_21_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_20_MASK              0x00100000
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_20_SHIFT             20
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_20_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_3_MASK                  0x00080000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_3_SHIFT                 19
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_3_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_2_MASK                  0x00040000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_2_SHIFT                 18
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_2_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_1_MASK                  0x00020000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_1_SHIFT                 17
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_1_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_0_MASK                  0x00010000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_0_SHIFT                 16
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_0_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_FWD_ERR_MASK          0x00008000
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_FWD_ERR_SHIFT         15
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_FWD_ERR_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_RETRY_TIMEOUT_MASK    0x00004000
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_RETRY_TIMEOUT_SHIFT   14
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_CA_ATTN_MASK          0x00002000
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_CA_ATTN_SHIFT         13
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_CA_ATTN_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_UR_ATTN_MASK          0x00001000
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_UR_ATTN_SHIFT         12
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_UR_ATTN_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_11_MASK              0x00000800
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_11_SHIFT             11
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_11_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_10_MASK              0x00000400
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_10_SHIFT             10
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_10_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_TGT_BAD_ACCESS_MASK        0x00000200
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_TGT_BAD_ACCESS_SHIFT       9
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_TGT_BAD_ACCESS_DEFAULT     0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_TGT_BAD_ADDRESS_MASK       0x00000100
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_TGT_BAD_ADDRESS_SHIFT      8
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_TGT_BAD_ADDRESS_DEFAULT    0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_RX_DMA_ERR_INTR_MASK         0x00000080
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_RX_DMA_ERR_INTR_SHIFT        7
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_RX_DMA_ERR_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_RX_DMA_DONE_INTR_MASK        0x00000040
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_RX_DMA_DONE_INTR_SHIFT       6
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_RX_DMA_DONE_INTR_DEFAULT     0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_TX_DMA_ERR_INTR_MASK         0x00000020
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_TX_DMA_ERR_INTR_SHIFT        5
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_TX_DMA_ERR_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_TX_DMA_DONE_INTR_MASK        0x00000010
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_TX_DMA_DONE_INTR_SHIFT       4
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_TX_DMA_DONE_INTR_DEFAULT     0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_RX_DMA_ERR_INTR_MASK         0x00000008
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_RX_DMA_ERR_INTR_SHIFT        3
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_RX_DMA_ERR_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_RX_DMA_DONE_INTR_MASK        0x00000004
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_RX_DMA_DONE_INTR_SHIFT       2
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_RX_DMA_DONE_INTR_DEFAULT     0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_TX_DMA_ERR_INTR_MASK         0x00000002
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_TX_DMA_ERR_INTR_SHIFT        1
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_TX_DMA_ERR_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_TX_DMA_DONE_INTR_MASK        0x00000001
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_TX_DMA_DONE_INTR_SHIFT       0
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_TX_DMA_DONE_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: PCI_SET :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR07_MASK                    0x80000000
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR07_SHIFT                   31
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR07_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR06_MASK                    0x40000000
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR06_SHIFT                   30
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR06_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR05_MASK                    0x20000000
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR05_SHIFT                   29
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR05_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR04_MASK                    0x10000000
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR04_SHIFT                   28
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR04_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR03_MASK                    0x08000000
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR03_SHIFT                   27
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR03_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR02_MASK                    0x04000000
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR02_SHIFT                   26
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR02_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR01_MASK                    0x02000000
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR01_SHIFT                   25
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR01_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR00_MASK                    0x01000000
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR00_SHIFT                   24
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR00_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_23_MASK                 0x00800000
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_23_SHIFT                23
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_23_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_22_MASK                 0x00400000
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_22_SHIFT                22
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_22_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_21_MASK                 0x00200000
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_21_SHIFT                21
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_21_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_20_MASK                 0x00100000
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_20_SHIFT                20
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_20_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_3_MASK                     0x00080000
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_3_SHIFT                    19
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_3_DEFAULT                  0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_2_MASK                     0x00040000
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_2_SHIFT                    18
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_2_DEFAULT                  0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_1_MASK                     0x00020000
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_1_SHIFT                    17
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_1_DEFAULT                  0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_0_MASK                     0x00010000
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_0_SHIFT                    16
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_0_DEFAULT                  0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_FWD_ERR_MASK             0x00008000
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_FWD_ERR_SHIFT            15
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_FWD_ERR_DEFAULT          0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_RETRY_TIMEOUT_MASK       0x00004000
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_RETRY_TIMEOUT_SHIFT      14
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT    0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_CA_ATTN_MASK             0x00002000
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_CA_ATTN_SHIFT            13
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_CA_ATTN_DEFAULT          0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_UR_ATTN_MASK             0x00001000
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_UR_ATTN_SHIFT            12
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_UR_ATTN_DEFAULT          0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_11_MASK                 0x00000800
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_11_SHIFT                11
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_11_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_10_MASK                 0x00000400
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_10_SHIFT                10
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_10_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_TGT_BAD_ACCESS_MASK           0x00000200
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_TGT_BAD_ACCESS_SHIFT          9
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_TGT_BAD_ACCESS_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_TGT_BAD_ADDRESS_MASK          0x00000100
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_TGT_BAD_ADDRESS_SHIFT         8
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_TGT_BAD_ADDRESS_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_PCI_SET_L1_RX_DMA_ERR_INTR_MASK            0x00000080
+#define BCHP_PCIE_INTR2_PCI_SET_L1_RX_DMA_ERR_INTR_SHIFT           7
+#define BCHP_PCIE_INTR2_PCI_SET_L1_RX_DMA_ERR_INTR_DEFAULT         0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_PCI_SET_L1_RX_DMA_DONE_INTR_MASK           0x00000040
+#define BCHP_PCIE_INTR2_PCI_SET_L1_RX_DMA_DONE_INTR_SHIFT          6
+#define BCHP_PCIE_INTR2_PCI_SET_L1_RX_DMA_DONE_INTR_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_PCI_SET_L1_TX_DMA_ERR_INTR_MASK            0x00000020
+#define BCHP_PCIE_INTR2_PCI_SET_L1_TX_DMA_ERR_INTR_SHIFT           5
+#define BCHP_PCIE_INTR2_PCI_SET_L1_TX_DMA_ERR_INTR_DEFAULT         0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_PCI_SET_L1_TX_DMA_DONE_INTR_MASK           0x00000010
+#define BCHP_PCIE_INTR2_PCI_SET_L1_TX_DMA_DONE_INTR_SHIFT          4
+#define BCHP_PCIE_INTR2_PCI_SET_L1_TX_DMA_DONE_INTR_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_PCI_SET_L0_RX_DMA_ERR_INTR_MASK            0x00000008
+#define BCHP_PCIE_INTR2_PCI_SET_L0_RX_DMA_ERR_INTR_SHIFT           3
+#define BCHP_PCIE_INTR2_PCI_SET_L0_RX_DMA_ERR_INTR_DEFAULT         0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_PCI_SET_L0_RX_DMA_DONE_INTR_MASK           0x00000004
+#define BCHP_PCIE_INTR2_PCI_SET_L0_RX_DMA_DONE_INTR_SHIFT          2
+#define BCHP_PCIE_INTR2_PCI_SET_L0_RX_DMA_DONE_INTR_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_PCI_SET_L0_TX_DMA_ERR_INTR_MASK            0x00000002
+#define BCHP_PCIE_INTR2_PCI_SET_L0_TX_DMA_ERR_INTR_SHIFT           1
+#define BCHP_PCIE_INTR2_PCI_SET_L0_TX_DMA_ERR_INTR_DEFAULT         0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_PCI_SET_L0_TX_DMA_DONE_INTR_MASK           0x00000001
+#define BCHP_PCIE_INTR2_PCI_SET_L0_TX_DMA_DONE_INTR_SHIFT          0
+#define BCHP_PCIE_INTR2_PCI_SET_L0_TX_DMA_DONE_INTR_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: PCI_CLEAR :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR07_MASK                  0x80000000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR07_SHIFT                 31
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR07_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR06_MASK                  0x40000000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR06_SHIFT                 30
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR06_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR05_MASK                  0x20000000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR05_SHIFT                 29
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR05_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR04_MASK                  0x10000000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR04_SHIFT                 28
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR04_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR03_MASK                  0x08000000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR03_SHIFT                 27
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR03_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR02_MASK                  0x04000000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR02_SHIFT                 26
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR02_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR01_MASK                  0x02000000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR01_SHIFT                 25
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR01_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR00_MASK                  0x01000000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR00_SHIFT                 24
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR00_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_23_MASK               0x00800000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_23_SHIFT              23
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_23_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_22_MASK               0x00400000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_22_SHIFT              22
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_22_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_21_MASK               0x00200000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_21_SHIFT              21
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_21_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_20_MASK               0x00100000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_20_SHIFT              20
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_20_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_3_MASK                   0x00080000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_3_SHIFT                  19
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_3_DEFAULT                0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_2_MASK                   0x00040000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_2_SHIFT                  18
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_2_DEFAULT                0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_1_MASK                   0x00020000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_1_SHIFT                  17
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_1_DEFAULT                0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_0_MASK                   0x00010000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_0_SHIFT                  16
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_0_DEFAULT                0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_FWD_ERR_MASK           0x00008000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_FWD_ERR_SHIFT          15
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_FWD_ERR_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_MASK     0x00004000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_SHIFT    14
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT  0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_CA_ATTN_MASK           0x00002000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_CA_ATTN_SHIFT          13
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_CA_ATTN_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_UR_ATTN_MASK           0x00001000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_UR_ATTN_SHIFT          12
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_UR_ATTN_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_11_MASK               0x00000800
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_11_SHIFT              11
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_11_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_10_MASK               0x00000400
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_10_SHIFT              10
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_10_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ACCESS_MASK         0x00000200
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ACCESS_SHIFT        9
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ACCESS_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ADDRESS_MASK        0x00000100
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ADDRESS_SHIFT       8
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ADDRESS_DEFAULT     0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_RX_DMA_ERR_INTR_MASK          0x00000080
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_RX_DMA_ERR_INTR_SHIFT         7
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_RX_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_RX_DMA_DONE_INTR_MASK         0x00000040
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_RX_DMA_DONE_INTR_SHIFT        6
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_RX_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_TX_DMA_ERR_INTR_MASK          0x00000020
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_TX_DMA_ERR_INTR_SHIFT         5
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_TX_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_TX_DMA_DONE_INTR_MASK         0x00000010
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_TX_DMA_DONE_INTR_SHIFT        4
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_TX_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_RX_DMA_ERR_INTR_MASK          0x00000008
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_RX_DMA_ERR_INTR_SHIFT         3
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_RX_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_RX_DMA_DONE_INTR_MASK         0x00000004
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_RX_DMA_DONE_INTR_SHIFT        2
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_RX_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_TX_DMA_ERR_INTR_MASK          0x00000002
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_TX_DMA_ERR_INTR_SHIFT         1
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_TX_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_TX_DMA_DONE_INTR_MASK         0x00000001
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_TX_DMA_DONE_INTR_SHIFT        0
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_TX_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR07_MASK            0x80000000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR07_SHIFT           31
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR07_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR06_MASK            0x40000000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR06_SHIFT           30
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR06_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR05_MASK            0x20000000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR05_SHIFT           29
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR05_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR04_MASK            0x10000000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR04_SHIFT           28
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR04_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR03_MASK            0x08000000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR03_SHIFT           27
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR03_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR02_MASK            0x04000000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR02_SHIFT           26
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR02_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR01_MASK            0x02000000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR01_SHIFT           25
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR01_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR00_MASK            0x01000000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR00_SHIFT           24
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR00_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_23_MASK         0x00800000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_23_SHIFT        23
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_23_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_22_MASK         0x00400000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_22_SHIFT        22
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_22_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_21_MASK         0x00200000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_21_SHIFT        21
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_21_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_20_MASK         0x00100000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_20_SHIFT        20
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_20_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_3_MASK             0x00080000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_3_SHIFT            19
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_3_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_2_MASK             0x00040000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_2_SHIFT            18
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_2_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_1_MASK             0x00020000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_1_SHIFT            17
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_1_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_0_MASK             0x00010000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_0_SHIFT            16
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_0_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_FWD_ERR_MASK     0x00008000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_FWD_ERR_SHIFT    15
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_FWD_ERR_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_CA_ATTN_MASK     0x00002000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_CA_ATTN_SHIFT    13
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_CA_ATTN_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_UR_ATTN_MASK     0x00001000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_UR_ATTN_SHIFT    12
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_UR_ATTN_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_11_MASK         0x00000800
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_11_SHIFT        11
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_11_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_10_MASK         0x00000400
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_10_SHIFT        10
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_10_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ACCESS_MASK   0x00000200
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ACCESS_SHIFT  9
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_MASK  0x00000100
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_SHIFT 8
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_RX_DMA_ERR_INTR_MASK    0x00000080
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_RX_DMA_ERR_INTR_SHIFT   7
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_RX_DMA_DONE_INTR_MASK   0x00000040
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_RX_DMA_DONE_INTR_SHIFT  6
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_TX_DMA_ERR_INTR_MASK    0x00000020
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_TX_DMA_ERR_INTR_SHIFT   5
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_TX_DMA_DONE_INTR_MASK   0x00000010
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_TX_DMA_DONE_INTR_SHIFT  4
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_RX_DMA_ERR_INTR_MASK    0x00000008
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_RX_DMA_ERR_INTR_SHIFT   3
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_RX_DMA_DONE_INTR_MASK   0x00000004
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_RX_DMA_DONE_INTR_SHIFT  2
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_TX_DMA_ERR_INTR_MASK    0x00000002
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_TX_DMA_ERR_INTR_SHIFT   1
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_TX_DMA_DONE_INTR_MASK   0x00000001
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_TX_DMA_DONE_INTR_SHIFT  0
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: PCI_MASK_SET :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR07_MASK               0x80000000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR07_SHIFT              31
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR07_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR06_MASK               0x40000000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR06_SHIFT              30
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR06_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR05_MASK               0x20000000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR05_SHIFT              29
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR05_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR04_MASK               0x10000000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR04_SHIFT              28
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR04_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR03_MASK               0x08000000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR03_SHIFT              27
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR03_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR02_MASK               0x04000000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR02_SHIFT              26
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR02_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR01_MASK               0x02000000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR01_SHIFT              25
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR01_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR00_MASK               0x01000000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR00_SHIFT              24
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR00_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_23_MASK            0x00800000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_23_SHIFT           23
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_23_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_22_MASK            0x00400000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_22_SHIFT           22
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_22_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_21_MASK            0x00200000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_21_SHIFT           21
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_21_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_20_MASK            0x00100000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_20_SHIFT           20
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_20_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_3_MASK                0x00080000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_3_SHIFT               19
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_3_DEFAULT             0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_2_MASK                0x00040000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_2_SHIFT               18
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_2_DEFAULT             0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_1_MASK                0x00020000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_1_SHIFT               17
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_1_DEFAULT             0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_0_MASK                0x00010000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_0_SHIFT               16
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_0_DEFAULT             0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_FWD_ERR_MASK        0x00008000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_FWD_ERR_SHIFT       15
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_FWD_ERR_DEFAULT     0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_MASK  0x00004000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_CA_ATTN_MASK        0x00002000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_CA_ATTN_SHIFT       13
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_CA_ATTN_DEFAULT     0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_UR_ATTN_MASK        0x00001000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_UR_ATTN_SHIFT       12
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_UR_ATTN_DEFAULT     0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_11_MASK            0x00000800
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_11_SHIFT           11
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_11_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_10_MASK            0x00000400
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_10_SHIFT           10
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_10_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ACCESS_MASK      0x00000200
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ACCESS_SHIFT     9
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ACCESS_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ADDRESS_MASK     0x00000100
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ADDRESS_SHIFT    8
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ADDRESS_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_RX_DMA_ERR_INTR_MASK       0x00000080
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_RX_DMA_ERR_INTR_SHIFT      7
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_RX_DMA_ERR_INTR_DEFAULT    0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_RX_DMA_DONE_INTR_MASK      0x00000040
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_RX_DMA_DONE_INTR_SHIFT     6
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_RX_DMA_DONE_INTR_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_TX_DMA_ERR_INTR_MASK       0x00000020
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_TX_DMA_ERR_INTR_SHIFT      5
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_TX_DMA_ERR_INTR_DEFAULT    0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_TX_DMA_DONE_INTR_MASK      0x00000010
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_TX_DMA_DONE_INTR_SHIFT     4
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_TX_DMA_DONE_INTR_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_RX_DMA_ERR_INTR_MASK       0x00000008
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_RX_DMA_ERR_INTR_SHIFT      3
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_RX_DMA_ERR_INTR_DEFAULT    0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_RX_DMA_DONE_INTR_MASK      0x00000004
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_RX_DMA_DONE_INTR_SHIFT     2
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_RX_DMA_DONE_INTR_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_TX_DMA_ERR_INTR_MASK       0x00000002
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_TX_DMA_ERR_INTR_SHIFT      1
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_TX_DMA_ERR_INTR_DEFAULT    0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_TX_DMA_DONE_INTR_MASK      0x00000001
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_TX_DMA_DONE_INTR_SHIFT     0
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_TX_DMA_DONE_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR07_MASK             0x80000000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR07_SHIFT            31
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR07_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR06_MASK             0x40000000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR06_SHIFT            30
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR06_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR05_MASK             0x20000000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR05_SHIFT            29
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR05_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR04_MASK             0x10000000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR04_SHIFT            28
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR04_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR03_MASK             0x08000000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR03_SHIFT            27
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR03_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR02_MASK             0x04000000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR02_SHIFT            26
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR02_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR01_MASK             0x02000000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR01_SHIFT            25
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR01_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR00_MASK             0x01000000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR00_SHIFT            24
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR00_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_23_MASK          0x00800000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_23_SHIFT         23
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_23_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_22_MASK          0x00400000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_22_SHIFT         22
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_22_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_21_MASK          0x00200000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_21_SHIFT         21
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_21_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_20_MASK          0x00100000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_20_SHIFT         20
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_20_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_3_MASK              0x00080000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_3_SHIFT             19
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_3_DEFAULT           0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_2_MASK              0x00040000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_2_SHIFT             18
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_2_DEFAULT           0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_1_MASK              0x00020000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_1_SHIFT             17
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_1_DEFAULT           0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_0_MASK              0x00010000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_0_SHIFT             16
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_0_DEFAULT           0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_FWD_ERR_MASK      0x00008000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_FWD_ERR_SHIFT     15
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_FWD_ERR_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_CA_ATTN_MASK      0x00002000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_CA_ATTN_SHIFT     13
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_CA_ATTN_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_UR_ATTN_MASK      0x00001000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_UR_ATTN_SHIFT     12
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_UR_ATTN_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_11_MASK          0x00000800
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_11_SHIFT         11
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_11_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_10_MASK          0x00000400
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_10_SHIFT         10
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_10_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_MASK    0x00000200
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_SHIFT   9
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_MASK   0x00000100
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_SHIFT  8
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_ERR_INTR_MASK     0x00000080
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_ERR_INTR_SHIFT    7
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_ERR_INTR_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_DONE_INTR_MASK    0x00000040
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_DONE_INTR_SHIFT   6
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_ERR_INTR_MASK     0x00000020
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_ERR_INTR_SHIFT    5
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_ERR_INTR_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_DONE_INTR_MASK    0x00000010
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_DONE_INTR_SHIFT   4
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_ERR_INTR_MASK     0x00000008
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_ERR_INTR_SHIFT    3
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_ERR_INTR_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_DONE_INTR_MASK    0x00000004
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_DONE_INTR_SHIFT   2
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_ERR_INTR_MASK     0x00000002
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_ERR_INTR_SHIFT    1
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_ERR_INTR_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_DONE_INTR_MASK    0x00000001
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_DONE_INTR_SHIFT   0
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+#endif /* #ifndef BCHP_PCIE_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_pcie_misc.h b/include/linux/brcmstb/7425b0/bchp_pcie_misc.h
new file mode 100644
index 0000000..8d6bd98
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_pcie_misc.h
@@ -0,0 +1,788 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:43 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_PCIE_MISC_H__
+#define BCHP_PCIE_MISC_H__
+
+/***************************************************************************
+ *PCIE_MISC - PCI-E Miscellaneous Registers
+ ***************************************************************************/
+#define BCHP_PCIE_MISC_RESET_CTRL                0x00414000 /* Reset Control Register */
+#define BCHP_PCIE_MISC_ECO_CTRL_CORE             0x00414004 /* ECO Core Reset Control Register */
+#define BCHP_PCIE_MISC_MISC_CTRL                 0x00414008 /* MISC Control Register */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO    0x0041400c /* CPU to PCIe Memory Window 0 Low */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI    0x00414010 /* CPU to PCIe Memory Window 0 High */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_LO    0x00414014 /* CPU to PCIe Memory Window 1 Low */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_HI    0x00414018 /* CPU to PCIe Memory Window 1 High */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_LO    0x0041401c /* CPU to PCIe Memory Window 2 Low */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_HI    0x00414020 /* CPU to PCIe Memory Window 2 High */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_LO    0x00414024 /* CPU to PCIe Memory Window 3 Low */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_HI    0x00414028 /* CPU to PCIe Memory Window 3 High */
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_LO         0x0041402c /* RC BAR1 Configuration Low Register */
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_HI         0x00414030 /* RC BAR1 Configuration High Register */
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_LO         0x00414034 /* RC BAR2 Configuration Low Register */
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_HI         0x00414038 /* RC BAR2 Configuration High Register */
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_LO         0x0041403c /* RC BAR3 Configuration Low Register */
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_HI         0x00414040 /* RC BAR3 Configuration High Register */
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_LO         0x00414044 /* Message Signaled Interrupt Base Address Low Register */
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_HI         0x00414048 /* Message Signaled Interrupt Base Address High Register */
+#define BCHP_PCIE_MISC_MSI_DATA_CONFIG           0x0041404c /* Message Signaled Interrupt Data Configuration Register */
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_LO         0x00414050 /* RC Bad Address Register Low */
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_HI         0x00414054 /* RC Bad Address Register High */
+#define BCHP_PCIE_MISC_RC_BAD_DATA               0x00414058 /* RC Bad Data Register */
+#define BCHP_PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT   0x0041405c /* RC Configuration Retry Timeout Register */
+#define BCHP_PCIE_MISC_EOI_CTRL                  0x00414060 /* End of Interrupt Control Register */
+#define BCHP_PCIE_MISC_PCIE_CTRL                 0x00414064 /* PCIe Control */
+#define BCHP_PCIE_MISC_PCIE_STATUS               0x00414068 /* PCIe Status */
+#define BCHP_PCIE_MISC_REVISION                  0x0041406c /* PCIe Revision */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x00414070 /* CPU to PCIe Memory Window 0 base/limit */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT 0x00414074 /* CPU to PCIe Memory Window 1 base/limit */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT 0x00414078 /* CPU to PCIe Memory Window 2 base/limit */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT 0x0041407c /* CPU to PCIe Memory Window 3 base/limit */
+#define BCHP_PCIE_MISC_UBUS_CTRL                 0x00414080 /* UBUS Control */
+#define BCHP_PCIE_MISC_UBUS_TIMEOUT              0x00414084 /* UBUS Timeout */
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP    0x00414088 /* UBUS BAR1 System Bus Address Remap Register */
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP    0x0041408c /* UBUS BAR2 System Bus Address Remap Register */
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP    0x00414090 /* UBUS BAR3 System Bus Address Remap Register */
+#define BCHP_PCIE_MISC_UBUS_STATUS               0x00414094 /* UBUS Status */
+
+/***************************************************************************
+ *RESET_CTRL - Reset Control Register
+ ***************************************************************************/
+/* PCIE_MISC :: RESET_CTRL :: reserved0 [31:01] */
+#define BCHP_PCIE_MISC_RESET_CTRL_reserved0_MASK                   0xfffffffe
+#define BCHP_PCIE_MISC_RESET_CTRL_reserved0_SHIFT                  1
+
+/* PCIE_MISC :: RESET_CTRL :: CORE_RESET [00:00] */
+#define BCHP_PCIE_MISC_RESET_CTRL_CORE_RESET_MASK                  0x00000001
+#define BCHP_PCIE_MISC_RESET_CTRL_CORE_RESET_SHIFT                 0
+#define BCHP_PCIE_MISC_RESET_CTRL_CORE_RESET_DEFAULT               0x00000000
+
+/***************************************************************************
+ *ECO_CTRL_CORE - ECO Core Reset Control Register
+ ***************************************************************************/
+/* PCIE_MISC :: ECO_CTRL_CORE :: reserved0 [31:16] */
+#define BCHP_PCIE_MISC_ECO_CTRL_CORE_reserved0_MASK                0xffff0000
+#define BCHP_PCIE_MISC_ECO_CTRL_CORE_reserved0_SHIFT               16
+
+/* PCIE_MISC :: ECO_CTRL_CORE :: ECO_CORE_RST_N [15:00] */
+#define BCHP_PCIE_MISC_ECO_CTRL_CORE_ECO_CORE_RST_N_MASK           0x0000ffff
+#define BCHP_PCIE_MISC_ECO_CTRL_CORE_ECO_CORE_RST_N_SHIFT          0
+#define BCHP_PCIE_MISC_ECO_CTRL_CORE_ECO_CORE_RST_N_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MISC_CTRL - MISC Control Register
+ ***************************************************************************/
+/* PCIE_MISC :: MISC_CTRL :: SCB0_SIZE [31:27] */
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK                    0xf8000000
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT                   27
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB0_SIZE_DEFAULT                 0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: SCB1_SIZE [26:22] */
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK                    0x07c00000
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT                   22
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB1_SIZE_DEFAULT                 0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: TBD_OPTION_21 [21:21] */
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_21_MASK                0x00200000
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_21_SHIFT               21
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_21_DEFAULT             0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: SCB_MAX_BURST_SIZE [20:20] */
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB_MAX_BURST_SIZE_MASK           0x00100000
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB_MAX_BURST_SIZE_SHIFT          20
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB_MAX_BURST_SIZE_DEFAULT        0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: TBD_OPTION_19 [19:19] */
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_19_MASK                0x00080000
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_19_SHIFT               19
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_19_DEFAULT             0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: TBD_OPTION_18 [18:18] */
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_18_MASK                0x00040000
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_18_SHIFT               18
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_18_DEFAULT             0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: CSR_CFG_MODE [17:17] */
+#define BCHP_PCIE_MISC_MISC_CTRL_CSR_CFG_MODE_MASK                 0x00020000
+#define BCHP_PCIE_MISC_MISC_CTRL_CSR_CFG_MODE_SHIFT                17
+#define BCHP_PCIE_MISC_MISC_CTRL_CSR_CFG_MODE_DEFAULT              0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: CSR_CFG_RETRY_EN [16:16] */
+#define BCHP_PCIE_MISC_MISC_CTRL_CSR_CFG_RETRY_EN_MASK             0x00010000
+#define BCHP_PCIE_MISC_MISC_CTRL_CSR_CFG_RETRY_EN_SHIFT            16
+#define BCHP_PCIE_MISC_MISC_CTRL_CSR_CFG_RETRY_EN_DEFAULT          0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: TBD_OPTION_15 [15:15] */
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_15_MASK                0x00008000
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_15_SHIFT               15
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_15_DEFAULT             0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: TBD_OPTION_14 [14:14] */
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_14_MASK                0x00004000
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_14_SHIFT               14
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_14_DEFAULT             0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: CFG_READ_UR_MODE [13:13] */
+#define BCHP_PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK             0x00002000
+#define BCHP_PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT            13
+#define BCHP_PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_DEFAULT          0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: SCB_ACCESS_EN [12:12] */
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK                0x00001000
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT               12
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_DEFAULT             0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: TBD_OPTION_11 [11:11] */
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_11_MASK                0x00000800
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_11_SHIFT               11
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_11_DEFAULT             0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: TBD_OPTION_10 [10:10] */
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_10_MASK                0x00000400
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_10_SHIFT               10
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_10_DEFAULT             0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: DESC_PRIORITY_EN [09:09] */
+#define BCHP_PCIE_MISC_MISC_CTRL_DESC_PRIORITY_EN_MASK             0x00000200
+#define BCHP_PCIE_MISC_MISC_CTRL_DESC_PRIORITY_EN_SHIFT            9
+#define BCHP_PCIE_MISC_MISC_CTRL_DESC_PRIORITY_EN_DEFAULT          0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: READ_PRIORITY_EN [08:08] */
+#define BCHP_PCIE_MISC_MISC_CTRL_READ_PRIORITY_EN_MASK             0x00000100
+#define BCHP_PCIE_MISC_MISC_CTRL_READ_PRIORITY_EN_SHIFT            8
+#define BCHP_PCIE_MISC_MISC_CTRL_READ_PRIORITY_EN_DEFAULT          0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: PCIE_RCB_64B_MODE [07:07] */
+#define BCHP_PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK            0x00000080
+#define BCHP_PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_SHIFT           7
+#define BCHP_PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_DEFAULT         0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: PCIE_OUT_CPL_RO [06:06] */
+#define BCHP_PCIE_MISC_MISC_CTRL_PCIE_OUT_CPL_RO_MASK              0x00000040
+#define BCHP_PCIE_MISC_MISC_CTRL_PCIE_OUT_CPL_RO_SHIFT             6
+#define BCHP_PCIE_MISC_MISC_CTRL_PCIE_OUT_CPL_RO_DEFAULT           0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: PCIE_IN_CPL_RO [05:05] */
+#define BCHP_PCIE_MISC_MISC_CTRL_PCIE_IN_CPL_RO_MASK               0x00000020
+#define BCHP_PCIE_MISC_MISC_CTRL_PCIE_IN_CPL_RO_SHIFT              5
+#define BCHP_PCIE_MISC_MISC_CTRL_PCIE_IN_CPL_RO_DEFAULT            0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: RELAXED_ORDERING [04:04] */
+#define BCHP_PCIE_MISC_MISC_CTRL_RELAXED_ORDERING_MASK             0x00000010
+#define BCHP_PCIE_MISC_MISC_CTRL_RELAXED_ORDERING_SHIFT            4
+#define BCHP_PCIE_MISC_MISC_CTRL_RELAXED_ORDERING_DEFAULT          0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: NO_SNOOP [03:03] */
+#define BCHP_PCIE_MISC_MISC_CTRL_NO_SNOOP_MASK                     0x00000008
+#define BCHP_PCIE_MISC_MISC_CTRL_NO_SNOOP_SHIFT                    3
+#define BCHP_PCIE_MISC_MISC_CTRL_NO_SNOOP_DEFAULT                  0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: TRAFFIC_CLASS [02:00] */
+#define BCHP_PCIE_MISC_MISC_CTRL_TRAFFIC_CLASS_MASK                0x00000007
+#define BCHP_PCIE_MISC_MISC_CTRL_TRAFFIC_CLASS_SHIFT               0
+#define BCHP_PCIE_MISC_MISC_CTRL_TRAFFIC_CLASS_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN0_LO - CPU to PCIe Memory Window 0 Low
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN0_LO :: BASE_ADDR [31:20] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO_BASE_ADDR_MASK       0xfff00000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO_BASE_ADDR_SHIFT      20
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO_BASE_ADDR_DEFAULT    0x00000000
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN0_LO :: reserved0 [19:02] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO_reserved0_MASK       0x000ffffc
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO_reserved0_SHIFT      2
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN0_LO :: ENDIAN_MODE [01:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO_ENDIAN_MODE_MASK     0x00000003
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO_ENDIAN_MODE_SHIFT    0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO_ENDIAN_MODE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN0_HI - CPU to PCIe Memory Window 0 High
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN0_HI :: BASE_ADDR [31:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI_BASE_ADDR_MASK       0xffffffff
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI_BASE_ADDR_SHIFT      0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI_BASE_ADDR_DEFAULT    0x00000000
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN1_LO - CPU to PCIe Memory Window 1 Low
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN1_LO :: BASE_ADDR [31:20] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_LO_BASE_ADDR_MASK       0xfff00000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_LO_BASE_ADDR_SHIFT      20
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_LO_BASE_ADDR_DEFAULT    0x00000000
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN1_LO :: reserved0 [19:02] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_LO_reserved0_MASK       0x000ffffc
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_LO_reserved0_SHIFT      2
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN1_LO :: ENDIAN_MODE [01:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_LO_ENDIAN_MODE_MASK     0x00000003
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_LO_ENDIAN_MODE_SHIFT    0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_LO_ENDIAN_MODE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN1_HI - CPU to PCIe Memory Window 1 High
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN1_HI :: BASE_ADDR [31:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_HI_BASE_ADDR_MASK       0xffffffff
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_HI_BASE_ADDR_SHIFT      0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_HI_BASE_ADDR_DEFAULT    0x00000000
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN2_LO - CPU to PCIe Memory Window 2 Low
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN2_LO :: BASE_ADDR [31:20] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_LO_BASE_ADDR_MASK       0xfff00000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_LO_BASE_ADDR_SHIFT      20
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_LO_BASE_ADDR_DEFAULT    0x00000000
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN2_LO :: reserved0 [19:02] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_LO_reserved0_MASK       0x000ffffc
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_LO_reserved0_SHIFT      2
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN2_LO :: ENDIAN_MODE [01:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_LO_ENDIAN_MODE_MASK     0x00000003
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_LO_ENDIAN_MODE_SHIFT    0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_LO_ENDIAN_MODE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN2_HI - CPU to PCIe Memory Window 2 High
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN2_HI :: BASE_ADDR [31:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_HI_BASE_ADDR_MASK       0xffffffff
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_HI_BASE_ADDR_SHIFT      0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_HI_BASE_ADDR_DEFAULT    0x00000000
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN3_LO - CPU to PCIe Memory Window 3 Low
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN3_LO :: BASE_ADDR [31:20] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_LO_BASE_ADDR_MASK       0xfff00000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_LO_BASE_ADDR_SHIFT      20
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_LO_BASE_ADDR_DEFAULT    0x00000000
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN3_LO :: reserved0 [19:02] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_LO_reserved0_MASK       0x000ffffc
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_LO_reserved0_SHIFT      2
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN3_LO :: ENDIAN_MODE [01:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_LO_ENDIAN_MODE_MASK     0x00000003
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_LO_ENDIAN_MODE_SHIFT    0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_LO_ENDIAN_MODE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN3_HI - CPU to PCIe Memory Window 3 High
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN3_HI :: BASE_ADDR [31:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_HI_BASE_ADDR_MASK       0xffffffff
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_HI_BASE_ADDR_SHIFT      0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_HI_BASE_ADDR_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RC_BAR1_CONFIG_LO - RC BAR1 Configuration Low Register
+ ***************************************************************************/
+/* PCIE_MISC :: RC_BAR1_CONFIG_LO :: MATCH_ADDRESS [31:16] */
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_LO_MATCH_ADDRESS_MASK        0xffff0000
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_LO_MATCH_ADDRESS_SHIFT       16
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_LO_MATCH_ADDRESS_DEFAULT     0x00000000
+
+/* PCIE_MISC :: RC_BAR1_CONFIG_LO :: reserved0 [15:05] */
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_LO_reserved0_MASK            0x0000ffe0
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_LO_reserved0_SHIFT           5
+
+/* PCIE_MISC :: RC_BAR1_CONFIG_LO :: SIZE [04:00] */
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK                 0x0000001f
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT                0
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RC_BAR1_CONFIG_HI - RC BAR1 Configuration High Register
+ ***************************************************************************/
+/* PCIE_MISC :: RC_BAR1_CONFIG_HI :: MATCH_ADDRESS [31:00] */
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_HI_MATCH_ADDRESS_MASK        0xffffffff
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_HI_MATCH_ADDRESS_SHIFT       0
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_HI_MATCH_ADDRESS_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RC_BAR2_CONFIG_LO - RC BAR2 Configuration Low Register
+ ***************************************************************************/
+/* PCIE_MISC :: RC_BAR2_CONFIG_LO :: MATCH_ADDRESS [31:16] */
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_LO_MATCH_ADDRESS_MASK        0xffff0000
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_LO_MATCH_ADDRESS_SHIFT       16
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_LO_MATCH_ADDRESS_DEFAULT     0x00000000
+
+/* PCIE_MISC :: RC_BAR2_CONFIG_LO :: reserved0 [15:05] */
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_LO_reserved0_MASK            0x0000ffe0
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_LO_reserved0_SHIFT           5
+
+/* PCIE_MISC :: RC_BAR2_CONFIG_LO :: SIZE [04:00] */
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK                 0x0000001f
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT                0
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RC_BAR2_CONFIG_HI - RC BAR2 Configuration High Register
+ ***************************************************************************/
+/* PCIE_MISC :: RC_BAR2_CONFIG_HI :: MATCH_ADDRESS [31:00] */
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_HI_MATCH_ADDRESS_MASK        0xffffffff
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_HI_MATCH_ADDRESS_SHIFT       0
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_HI_MATCH_ADDRESS_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RC_BAR3_CONFIG_LO - RC BAR3 Configuration Low Register
+ ***************************************************************************/
+/* PCIE_MISC :: RC_BAR3_CONFIG_LO :: MATCH_ADDRESS [31:16] */
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_LO_MATCH_ADDRESS_MASK        0xffff0000
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_LO_MATCH_ADDRESS_SHIFT       16
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_LO_MATCH_ADDRESS_DEFAULT     0x00000000
+
+/* PCIE_MISC :: RC_BAR3_CONFIG_LO :: reserved0 [15:05] */
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_LO_reserved0_MASK            0x0000ffe0
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_LO_reserved0_SHIFT           5
+
+/* PCIE_MISC :: RC_BAR3_CONFIG_LO :: SIZE [04:00] */
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK                 0x0000001f
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT                0
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RC_BAR3_CONFIG_HI - RC BAR3 Configuration High Register
+ ***************************************************************************/
+/* PCIE_MISC :: RC_BAR3_CONFIG_HI :: MATCH_ADDRESS [31:00] */
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_HI_MATCH_ADDRESS_MASK        0xffffffff
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_HI_MATCH_ADDRESS_SHIFT       0
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_HI_MATCH_ADDRESS_DEFAULT     0x00000000
+
+/***************************************************************************
+ *MSI_BAR_CONFIG_LO - Message Signaled Interrupt Base Address Low Register
+ ***************************************************************************/
+/* PCIE_MISC :: MSI_BAR_CONFIG_LO :: MATCH_ADDRESS [31:02] */
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_LO_MATCH_ADDRESS_MASK        0xfffffffc
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_LO_MATCH_ADDRESS_SHIFT       2
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_LO_MATCH_ADDRESS_DEFAULT     0x00000000
+
+/* PCIE_MISC :: MSI_BAR_CONFIG_LO :: reserved0 [01:01] */
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_LO_reserved0_MASK            0x00000002
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_LO_reserved0_SHIFT           1
+
+/* PCIE_MISC :: MSI_BAR_CONFIG_LO :: ENABLE [00:00] */
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_LO_ENABLE_MASK               0x00000001
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_LO_ENABLE_SHIFT              0
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_LO_ENABLE_DEFAULT            0x00000000
+
+/***************************************************************************
+ *MSI_BAR_CONFIG_HI - Message Signaled Interrupt Base Address High Register
+ ***************************************************************************/
+/* PCIE_MISC :: MSI_BAR_CONFIG_HI :: MATCH_ADDRESS [31:00] */
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_HI_MATCH_ADDRESS_MASK        0xffffffff
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_HI_MATCH_ADDRESS_SHIFT       0
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_HI_MATCH_ADDRESS_DEFAULT     0x00000000
+
+/***************************************************************************
+ *MSI_DATA_CONFIG - Message Signaled Interrupt Data Configuration Register
+ ***************************************************************************/
+/* PCIE_MISC :: MSI_DATA_CONFIG :: MASK [31:16] */
+#define BCHP_PCIE_MISC_MSI_DATA_CONFIG_MASK_MASK                   0xffff0000
+#define BCHP_PCIE_MISC_MSI_DATA_CONFIG_MASK_SHIFT                  16
+#define BCHP_PCIE_MISC_MSI_DATA_CONFIG_MASK_DEFAULT                0x00000000
+
+/* PCIE_MISC :: MSI_DATA_CONFIG :: DATA [15:00] */
+#define BCHP_PCIE_MISC_MSI_DATA_CONFIG_DATA_MASK                   0x0000ffff
+#define BCHP_PCIE_MISC_MSI_DATA_CONFIG_DATA_SHIFT                  0
+#define BCHP_PCIE_MISC_MSI_DATA_CONFIG_DATA_DEFAULT                0x00000000
+
+/***************************************************************************
+ *RC_BAD_ADDRESS_LO - RC Bad Address Register Low
+ ***************************************************************************/
+/* PCIE_MISC :: RC_BAD_ADDRESS_LO :: ADDRESS [31:02] */
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_LO_ADDRESS_MASK              0xfffffffc
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_LO_ADDRESS_SHIFT             2
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_LO_ADDRESS_DEFAULT           0x00000000
+
+/* PCIE_MISC :: RC_BAD_ADDRESS_LO :: reserved0 [01:01] */
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_LO_reserved0_MASK            0x00000002
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_LO_reserved0_SHIFT           1
+
+/* PCIE_MISC :: RC_BAD_ADDRESS_LO :: VALID [00:00] */
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_LO_VALID_MASK                0x00000001
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_LO_VALID_SHIFT               0
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_LO_VALID_DEFAULT             0x00000000
+
+/***************************************************************************
+ *RC_BAD_ADDRESS_HI - RC Bad Address Register High
+ ***************************************************************************/
+/* PCIE_MISC :: RC_BAD_ADDRESS_HI :: ADDRESS [31:00] */
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_HI_ADDRESS_MASK              0xffffffff
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_HI_ADDRESS_SHIFT             0
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_HI_ADDRESS_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RC_BAD_DATA - RC Bad Data Register
+ ***************************************************************************/
+/* PCIE_MISC :: RC_BAD_DATA :: DATA [31:00] */
+#define BCHP_PCIE_MISC_RC_BAD_DATA_DATA_MASK                       0xffffffff
+#define BCHP_PCIE_MISC_RC_BAD_DATA_DATA_SHIFT                      0
+#define BCHP_PCIE_MISC_RC_BAD_DATA_DATA_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *RC_CONFIG_RETRY_TIMEOUT - RC Configuration Retry Timeout Register
+ ***************************************************************************/
+/* PCIE_MISC :: RC_CONFIG_RETRY_TIMEOUT :: TIMER_VALUE [31:00] */
+#define BCHP_PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT_TIMER_VALUE_MASK    0xffffffff
+#define BCHP_PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT_TIMER_VALUE_SHIFT   0
+#define BCHP_PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT_TIMER_VALUE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EOI_CTRL - End of Interrupt Control Register
+ ***************************************************************************/
+/* PCIE_MISC :: EOI_CTRL :: reserved0 [31:01] */
+#define BCHP_PCIE_MISC_EOI_CTRL_reserved0_MASK                     0xfffffffe
+#define BCHP_PCIE_MISC_EOI_CTRL_reserved0_SHIFT                    1
+
+/* PCIE_MISC :: EOI_CTRL :: EOI [00:00] */
+#define BCHP_PCIE_MISC_EOI_CTRL_EOI_MASK                           0x00000001
+#define BCHP_PCIE_MISC_EOI_CTRL_EOI_SHIFT                          0
+#define BCHP_PCIE_MISC_EOI_CTRL_EOI_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *PCIE_CTRL - PCIe Control
+ ***************************************************************************/
+/* PCIE_MISC :: PCIE_CTRL :: reserved0 [31:02] */
+#define BCHP_PCIE_MISC_PCIE_CTRL_reserved0_MASK                    0xfffffffc
+#define BCHP_PCIE_MISC_PCIE_CTRL_reserved0_SHIFT                   2
+
+/* PCIE_MISC :: PCIE_CTRL :: PCIE_PME_REQUEST [01:01] */
+#define BCHP_PCIE_MISC_PCIE_CTRL_PCIE_PME_REQUEST_MASK             0x00000002
+#define BCHP_PCIE_MISC_PCIE_CTRL_PCIE_PME_REQUEST_SHIFT            1
+#define BCHP_PCIE_MISC_PCIE_CTRL_PCIE_PME_REQUEST_DEFAULT          0x00000000
+
+/* PCIE_MISC :: PCIE_CTRL :: PCIE_L23_REQUEST [00:00] */
+#define BCHP_PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK             0x00000001
+#define BCHP_PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT            0
+#define BCHP_PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PCIE_STATUS - PCIe Status
+ ***************************************************************************/
+/* PCIE_MISC :: PCIE_STATUS :: reserved0 [31:12] */
+#define BCHP_PCIE_MISC_PCIE_STATUS_reserved0_MASK                  0xfffff000
+#define BCHP_PCIE_MISC_PCIE_STATUS_reserved0_SHIFT                 12
+
+/* PCIE_MISC :: PCIE_STATUS :: PCIE_PM_STATE [11:10] */
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_PM_STATE_MASK              0x00000c00
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_PM_STATE_SHIFT             10
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_PM_STATE_DEFAULT           0x00000000
+
+/* PCIE_MISC :: PCIE_STATUS :: PCIE_WAKE [09:09] */
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_WAKE_MASK                  0x00000200
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_WAKE_SHIFT                 9
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_WAKE_DEFAULT               0x00000000
+
+/* PCIE_MISC :: PCIE_STATUS :: PCIE_PME_EVENT [08:08] */
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_PME_EVENT_MASK             0x00000100
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_PME_EVENT_SHIFT            8
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_PME_EVENT_DEFAULT          0x00000000
+
+/* PCIE_MISC :: PCIE_STATUS :: PCIE_PORT [07:07] */
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK                  0x00000080
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT                 7
+
+/* PCIE_MISC :: PCIE_STATUS :: PCIE_LINK_IN_L23 [06:06] */
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK           0x00000040
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT          6
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_DEFAULT        0x00000000
+
+/* PCIE_MISC :: PCIE_STATUS :: PCIE_DL_ACTIVE [05:05] */
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK             0x00000020
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT            5
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_DEFAULT          0x00000000
+
+/* PCIE_MISC :: PCIE_STATUS :: PCIE_PHYLINKUP [04:04] */
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK             0x00000010
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT            4
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_DEFAULT          0x00000000
+
+/* PCIE_MISC :: PCIE_STATUS :: PCIE_ERR_STATUS [03:00] */
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_ERR_STATUS_MASK            0x0000000f
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_ERR_STATUS_SHIFT           0
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_ERR_STATUS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *REVISION - PCIe Revision
+ ***************************************************************************/
+/* PCIE_MISC :: REVISION :: reserved0 [31:16] */
+#define BCHP_PCIE_MISC_REVISION_reserved0_MASK                     0xffff0000
+#define BCHP_PCIE_MISC_REVISION_reserved0_SHIFT                    16
+
+/* PCIE_MISC :: REVISION :: MAJOR [15:08] */
+#define BCHP_PCIE_MISC_REVISION_MAJOR_MASK                         0x0000ff00
+#define BCHP_PCIE_MISC_REVISION_MAJOR_SHIFT                        8
+#define BCHP_PCIE_MISC_REVISION_MAJOR_DEFAULT                      0x00000002
+
+/* PCIE_MISC :: REVISION :: MINOR [07:00] */
+#define BCHP_PCIE_MISC_REVISION_MINOR_MASK                         0x000000ff
+#define BCHP_PCIE_MISC_REVISION_MINOR_SHIFT                        0
+#define BCHP_PCIE_MISC_REVISION_MINOR_DEFAULT                      0x00000002
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN0_BASE_LIMIT - CPU to PCIe Memory Window 0 base/limit
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_LIMIT :: LIMIT [31:20] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK   0xfff00000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT  20
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_DEFAULT 0x00000000
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_LIMIT :: reserved0 [19:16] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_reserved0_MASK 0x000f0000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_reserved0_SHIFT 16
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_LIMIT :: BASE [15:04] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK    0x0000fff0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT   4
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_DEFAULT 0x00000001
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_LIMIT :: reserved1 [03:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_reserved1_MASK 0x0000000f
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_reserved1_SHIFT 0
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN1_BASE_LIMIT - CPU to PCIe Memory Window 1 base/limit
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_LIMIT :: LIMIT [31:20] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_LIMIT_MASK   0xfff00000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_LIMIT_SHIFT  20
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_LIMIT_DEFAULT 0x00000000
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_LIMIT :: reserved0 [19:16] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_reserved0_MASK 0x000f0000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_reserved0_SHIFT 16
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_LIMIT :: BASE [15:04] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_BASE_MASK    0x0000fff0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_BASE_SHIFT   4
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_BASE_DEFAULT 0x00000001
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_LIMIT :: reserved1 [03:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_reserved1_MASK 0x0000000f
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_reserved1_SHIFT 0
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN2_BASE_LIMIT - CPU to PCIe Memory Window 2 base/limit
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_LIMIT :: LIMIT [31:20] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_LIMIT_MASK   0xfff00000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_LIMIT_SHIFT  20
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_LIMIT_DEFAULT 0x00000000
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_LIMIT :: reserved0 [19:16] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_reserved0_MASK 0x000f0000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_reserved0_SHIFT 16
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_LIMIT :: BASE [15:04] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_BASE_MASK    0x0000fff0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_BASE_SHIFT   4
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_BASE_DEFAULT 0x00000001
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_LIMIT :: reserved1 [03:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_reserved1_MASK 0x0000000f
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_reserved1_SHIFT 0
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN3_BASE_LIMIT - CPU to PCIe Memory Window 3 base/limit
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_LIMIT :: LIMIT [31:20] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_LIMIT_MASK   0xfff00000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_LIMIT_SHIFT  20
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_LIMIT_DEFAULT 0x00000000
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_LIMIT :: reserved0 [19:16] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_reserved0_MASK 0x000f0000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_reserved0_SHIFT 16
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_LIMIT :: BASE [15:04] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_BASE_MASK    0x0000fff0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_BASE_SHIFT   4
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_BASE_DEFAULT 0x00000001
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_LIMIT :: reserved1 [03:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_reserved1_MASK 0x0000000f
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_reserved1_SHIFT 0
+
+/***************************************************************************
+ *UBUS_CTRL - UBUS Control
+ ***************************************************************************/
+/* PCIE_MISC :: UBUS_CTRL :: TBD_OPTION_31_17 [31:17] */
+#define BCHP_PCIE_MISC_UBUS_CTRL_TBD_OPTION_31_17_MASK             0xfffe0000
+#define BCHP_PCIE_MISC_UBUS_CTRL_TBD_OPTION_31_17_SHIFT            17
+#define BCHP_PCIE_MISC_UBUS_CTRL_TBD_OPTION_31_17_DEFAULT          0x00000000
+
+/* PCIE_MISC :: UBUS_CTRL :: UBUS_DMA_WR_WITH_REPLY [16:15] */
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_DMA_WR_WITH_REPLY_MASK       0x00018000
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_DMA_WR_WITH_REPLY_SHIFT      15
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_DMA_WR_WITH_REPLY_DEFAULT    0x00000000
+
+/* PCIE_MISC :: UBUS_CTRL :: UBUS_WR_WITH_REPLY [14:14] */
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_WR_WITH_REPLY_MASK           0x00004000
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_WR_WITH_REPLY_SHIFT          14
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_WR_WITH_REPLY_DEFAULT        0x00000000
+
+/* PCIE_MISC :: UBUS_CTRL :: UBUS_PCIE_REPLY_ERR_DIS [13:13] */
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK      0x00002000
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_SHIFT     13
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_DEFAULT   0x00000000
+
+/* PCIE_MISC :: UBUS_CTRL :: UBUS_REG_ACCESS_RO [12:12] */
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_REG_ACCESS_RO_MASK           0x00001000
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_REG_ACCESS_RO_SHIFT          12
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_REG_ACCESS_RO_DEFAULT        0x00000000
+
+/* PCIE_MISC :: UBUS_CTRL :: REQIN_HDR_THRESHOLD [11:06] */
+#define BCHP_PCIE_MISC_UBUS_CTRL_REQIN_HDR_THRESHOLD_MASK          0x00000fc0
+#define BCHP_PCIE_MISC_UBUS_CTRL_REQIN_HDR_THRESHOLD_SHIFT         6
+#define BCHP_PCIE_MISC_UBUS_CTRL_REQIN_HDR_THRESHOLD_DEFAULT       0x00000008
+
+/* PCIE_MISC :: UBUS_CTRL :: REQIN_WR_DATA_THRESHOLD [05:00] */
+#define BCHP_PCIE_MISC_UBUS_CTRL_REQIN_WR_DATA_THRESHOLD_MASK      0x0000003f
+#define BCHP_PCIE_MISC_UBUS_CTRL_REQIN_WR_DATA_THRESHOLD_SHIFT     0
+#define BCHP_PCIE_MISC_UBUS_CTRL_REQIN_WR_DATA_THRESHOLD_DEFAULT   0x00000020
+
+/***************************************************************************
+ *UBUS_TIMEOUT - UBUS Timeout
+ ***************************************************************************/
+/* PCIE_MISC :: UBUS_TIMEOUT :: TIMER_VALUE [31:00] */
+#define BCHP_PCIE_MISC_UBUS_TIMEOUT_TIMER_VALUE_MASK               0xffffffff
+#define BCHP_PCIE_MISC_UBUS_TIMEOUT_TIMER_VALUE_SHIFT              0
+#define BCHP_PCIE_MISC_UBUS_TIMEOUT_TIMER_VALUE_DEFAULT            0x00080000
+
+/***************************************************************************
+ *UBUS_BAR1_CONFIG_REMAP - UBUS BAR1 System Bus Address Remap Register
+ ***************************************************************************/
+/* PCIE_MISC :: UBUS_BAR1_CONFIG_REMAP :: OFFSET [31:16] */
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_OFFSET_MASK          0xffff0000
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_OFFSET_SHIFT         16
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_OFFSET_DEFAULT       0x00000000
+
+/* PCIE_MISC :: UBUS_BAR1_CONFIG_REMAP :: reserved0 [15:04] */
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_reserved0_MASK       0x0000fff0
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_reserved0_SHIFT      4
+
+/* PCIE_MISC :: UBUS_BAR1_CONFIG_REMAP :: UNUSED_3_1 [03:01] */
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_UNUSED_3_1_MASK      0x0000000e
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_UNUSED_3_1_SHIFT     1
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_UNUSED_3_1_DEFAULT   0x00000000
+
+/* PCIE_MISC :: UBUS_BAR1_CONFIG_REMAP :: ACCESS_EN [00:00] */
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_MASK       0x00000001
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_SHIFT      0
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_DEFAULT    0x00000000
+
+/***************************************************************************
+ *UBUS_BAR2_CONFIG_REMAP - UBUS BAR2 System Bus Address Remap Register
+ ***************************************************************************/
+/* PCIE_MISC :: UBUS_BAR2_CONFIG_REMAP :: OFFSET [31:16] */
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_OFFSET_MASK          0xffff0000
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_OFFSET_SHIFT         16
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_OFFSET_DEFAULT       0x00000000
+
+/* PCIE_MISC :: UBUS_BAR2_CONFIG_REMAP :: reserved0 [15:04] */
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_reserved0_MASK       0x0000fff0
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_reserved0_SHIFT      4
+
+/* PCIE_MISC :: UBUS_BAR2_CONFIG_REMAP :: UNUSED_3_1 [03:01] */
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_UNUSED_3_1_MASK      0x0000000e
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_UNUSED_3_1_SHIFT     1
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_UNUSED_3_1_DEFAULT   0x00000000
+
+/* PCIE_MISC :: UBUS_BAR2_CONFIG_REMAP :: ACCESS_EN [00:00] */
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_EN_MASK       0x00000001
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_EN_SHIFT      0
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_EN_DEFAULT    0x00000000
+
+/***************************************************************************
+ *UBUS_BAR3_CONFIG_REMAP - UBUS BAR3 System Bus Address Remap Register
+ ***************************************************************************/
+/* PCIE_MISC :: UBUS_BAR3_CONFIG_REMAP :: OFFSET [31:16] */
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP_OFFSET_MASK          0xffff0000
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP_OFFSET_SHIFT         16
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP_OFFSET_DEFAULT       0x00000000
+
+/* PCIE_MISC :: UBUS_BAR3_CONFIG_REMAP :: reserved0 [15:04] */
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP_reserved0_MASK       0x0000fff0
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP_reserved0_SHIFT      4
+
+/* PCIE_MISC :: UBUS_BAR3_CONFIG_REMAP :: UNUSED_3_1 [03:01] */
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP_UNUSED_3_1_MASK      0x0000000e
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP_UNUSED_3_1_SHIFT     1
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP_UNUSED_3_1_DEFAULT   0x00000000
+
+/* PCIE_MISC :: UBUS_BAR3_CONFIG_REMAP :: ACCESS_EN [00:00] */
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP_ACCESS_EN_MASK       0x00000001
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP_ACCESS_EN_SHIFT      0
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP_ACCESS_EN_DEFAULT    0x00000000
+
+/***************************************************************************
+ *UBUS_STATUS - UBUS Status
+ ***************************************************************************/
+/* PCIE_MISC :: UBUS_STATUS :: SLAVE_REPOUT_HSPACE [31:24] */
+#define BCHP_PCIE_MISC_UBUS_STATUS_SLAVE_REPOUT_HSPACE_MASK        0xff000000
+#define BCHP_PCIE_MISC_UBUS_STATUS_SLAVE_REPOUT_HSPACE_SHIFT       24
+#define BCHP_PCIE_MISC_UBUS_STATUS_SLAVE_REPOUT_HSPACE_DEFAULT     0x00000010
+
+/* PCIE_MISC :: UBUS_STATUS :: SLAVE_REPOUT_DSPACE [23:16] */
+#define BCHP_PCIE_MISC_UBUS_STATUS_SLAVE_REPOUT_DSPACE_MASK        0x00ff0000
+#define BCHP_PCIE_MISC_UBUS_STATUS_SLAVE_REPOUT_DSPACE_SHIFT       16
+#define BCHP_PCIE_MISC_UBUS_STATUS_SLAVE_REPOUT_DSPACE_DEFAULT     0x00000020
+
+/* PCIE_MISC :: UBUS_STATUS :: MASTER_REQOUT_HSPACE [15:08] */
+#define BCHP_PCIE_MISC_UBUS_STATUS_MASTER_REQOUT_HSPACE_MASK       0x0000ff00
+#define BCHP_PCIE_MISC_UBUS_STATUS_MASTER_REQOUT_HSPACE_SHIFT      8
+#define BCHP_PCIE_MISC_UBUS_STATUS_MASTER_REQOUT_HSPACE_DEFAULT    0x00000010
+
+/* PCIE_MISC :: UBUS_STATUS :: MASTER_REQOUT_DSPACE [07:00] */
+#define BCHP_PCIE_MISC_UBUS_STATUS_MASTER_REQOUT_DSPACE_MASK       0x000000ff
+#define BCHP_PCIE_MISC_UBUS_STATUS_MASTER_REQOUT_DSPACE_SHIFT      0
+#define BCHP_PCIE_MISC_UBUS_STATUS_MASTER_REQOUT_DSPACE_DEFAULT    0x00000020
+
+#endif /* #ifndef BCHP_PCIE_MISC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_pcie_misc_hard.h b/include/linux/brcmstb/7425b0/bchp_pcie_misc_hard.h
new file mode 100644
index 0000000..f7e9c71
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_pcie_misc_hard.h
@@ -0,0 +1,153 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sun Aug 19 03:05:53 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_PCIE_MISC_HARD_H__
+#define BCHP_PCIE_MISC_HARD_H__
+
+/***************************************************************************
+ *PCIE_MISC_HARD - PCI-E Miscellaneous Registers (Hard reset)
+ ***************************************************************************/
+#define BCHP_PCIE_MISC_HARD_ECO_CTRL_HARD        0x00414200 /* ECO Hard Reset Control Register */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG      0x00414204 /* PCIE Hard Debug Register */
+
+/***************************************************************************
+ *ECO_CTRL_HARD - ECO Hard Reset Control Register
+ ***************************************************************************/
+/* PCIE_MISC_HARD :: ECO_CTRL_HARD :: reserved0 [31:16] */
+#define BCHP_PCIE_MISC_HARD_ECO_CTRL_HARD_reserved0_MASK           0xffff0000
+#define BCHP_PCIE_MISC_HARD_ECO_CTRL_HARD_reserved0_SHIFT          16
+
+/* PCIE_MISC_HARD :: ECO_CTRL_HARD :: ECO_HARD [15:00] */
+#define BCHP_PCIE_MISC_HARD_ECO_CTRL_HARD_ECO_HARD_MASK            0x0000ffff
+#define BCHP_PCIE_MISC_HARD_ECO_CTRL_HARD_ECO_HARD_SHIFT           0
+#define BCHP_PCIE_MISC_HARD_ECO_CTRL_HARD_ECO_HARD_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PCIE_HARD_DEBUG - PCIE Hard Debug Register
+ ***************************************************************************/
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: reserved0 [31:24] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_reserved0_MASK         0xff000000
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_reserved0_SHIFT        24
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: SERDES_IDDQ [23:23] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK       0x00800000
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT      23
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_DEFAULT    0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: SERDES_RESET [22:22] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_RESET_MASK      0x00400000
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_RESET_SHIFT     22
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_RESET_DEFAULT   0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: SERDES_MDIO_RESET [21:21] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_MDIO_RESET_MASK 0x00200000
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_MDIO_RESET_SHIFT 21
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_MDIO_RESET_DEFAULT 0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: SERDES_TEST_MODE [20:20] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_TEST_MODE_MASK  0x00100000
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_TEST_MODE_SHIFT 20
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_TEST_MODE_DEFAULT 0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: reserved1 [19:19] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_reserved1_MASK         0x00080000
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_reserved1_SHIFT        19
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: REFCLK_OVERRIDE_OUT [18:18] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVERRIDE_OUT_MASK 0x00040000
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVERRIDE_OUT_SHIFT 18
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVERRIDE_OUT_DEFAULT 0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: REFCLK_OVERRIDE_IN [17:17] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVERRIDE_IN_MASK 0x00020000
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVERRIDE_IN_SHIFT 17
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVERRIDE_IN_DEFAULT 0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: REFCLK_OVERRIDE [16:16] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVERRIDE_MASK   0x00010000
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVERRIDE_SHIFT  16
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVERRIDE_DEFAULT 0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: PCIE_TMUX_SEL [15:08] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_PCIE_TMUX_SEL_MASK     0x0000ff00
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_PCIE_TMUX_SEL_SHIFT    8
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_PCIE_TMUX_SEL_DEFAULT  0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: WATCHDOG_PERST_CTRL [07:07] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_WATCHDOG_PERST_CTRL_MASK 0x00000080
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_WATCHDOG_PERST_CTRL_SHIFT 7
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_WATCHDOG_PERST_CTRL_DEFAULT 0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: LOCAL_PERST_CTRL [06:06] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_LOCAL_PERST_CTRL_MASK  0x00000040
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_LOCAL_PERST_CTRL_SHIFT 6
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_LOCAL_PERST_CTRL_DEFAULT 0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: LOCAL_BRIDGE_RESET_CTRL [05:05] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_LOCAL_BRIDGE_RESET_CTRL_MASK 0x00000020
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_LOCAL_BRIDGE_RESET_CTRL_SHIFT 5
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_LOCAL_BRIDGE_RESET_CTRL_DEFAULT 0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: AUXCLK_ENABLE [04:04] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_AUXCLK_ENABLE_MASK     0x00000010
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_AUXCLK_ENABLE_SHIFT    4
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_AUXCLK_ENABLE_DEFAULT  0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: DOWNSTREAM_PERST_DISABLE [03:03] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_DOWNSTREAM_PERST_DISABLE_MASK 0x00000008
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_DOWNSTREAM_PERST_DISABLE_SHIFT 3
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_DOWNSTREAM_PERST_DISABLE_DEFAULT 0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: PCIECORE_ADDR_MODE [02:02] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_PCIECORE_ADDR_MODE_MASK 0x00000004
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_PCIECORE_ADDR_MODE_SHIFT 2
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_PCIECORE_ADDR_MODE_DEFAULT 0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: CLKREQ_DEBUG_ENABLE [01:01] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x00000002
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_SHIFT 1
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_DEFAULT 0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: HOTRESET_DISABLE [00:00] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_HOTRESET_DISABLE_MASK  0x00000001
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_HOTRESET_DISABLE_SHIFT 0
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_HOTRESET_DISABLE_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_PCIE_MISC_HARD_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_pcie_misc_perst.h b/include/linux/brcmstb/7425b0/bchp_pcie_misc_perst.h
new file mode 100644
index 0000000..5834036
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_pcie_misc_perst.h
@@ -0,0 +1,85 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:45 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_PCIE_MISC_PERST_H__
+#define BCHP_PCIE_MISC_PERST_H__
+
+/***************************************************************************
+ *PCIE_MISC_PERST - PCI-E Miscellaneous Registers (Fundamental reset)
+ ***************************************************************************/
+#define BCHP_PCIE_MISC_PERST_ECO_CTRL_PERST      0x00414100 /* ECO PCIE Reset Control Register */
+#define BCHP_PCIE_MISC_PERST_CCE_STATUS          0x00414104 /* Config Copy Engine Status */
+
+/***************************************************************************
+ *ECO_CTRL_PERST - ECO PCIE Reset Control Register
+ ***************************************************************************/
+/* PCIE_MISC_PERST :: ECO_CTRL_PERST :: reserved0 [31:16] */
+#define BCHP_PCIE_MISC_PERST_ECO_CTRL_PERST_reserved0_MASK         0xffff0000
+#define BCHP_PCIE_MISC_PERST_ECO_CTRL_PERST_reserved0_SHIFT        16
+
+/* PCIE_MISC_PERST :: ECO_CTRL_PERST :: ECO_PERST_N [15:00] */
+#define BCHP_PCIE_MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_MASK       0x0000ffff
+#define BCHP_PCIE_MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_SHIFT      0
+#define BCHP_PCIE_MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_DEFAULT    0x00000000
+
+/***************************************************************************
+ *CCE_STATUS - Config Copy Engine Status
+ ***************************************************************************/
+/* PCIE_MISC_PERST :: CCE_STATUS :: CCE_DONE [31:31] */
+#define BCHP_PCIE_MISC_PERST_CCE_STATUS_CCE_DONE_MASK              0x80000000
+#define BCHP_PCIE_MISC_PERST_CCE_STATUS_CCE_DONE_SHIFT             31
+
+/* PCIE_MISC_PERST :: CCE_STATUS :: reserved0 [30:03] */
+#define BCHP_PCIE_MISC_PERST_CCE_STATUS_reserved0_MASK             0x7ffffff8
+#define BCHP_PCIE_MISC_PERST_CCE_STATUS_reserved0_SHIFT            3
+
+/* PCIE_MISC_PERST :: CCE_STATUS :: CCE_BAD_GISB_ACCESS [02:02] */
+#define BCHP_PCIE_MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_MASK   0x00000004
+#define BCHP_PCIE_MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_SHIFT  2
+
+/* PCIE_MISC_PERST :: CCE_STATUS :: CCE_BAD_I2C_ACCESS [01:01] */
+#define BCHP_PCIE_MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_MASK    0x00000002
+#define BCHP_PCIE_MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_SHIFT   1
+
+/* PCIE_MISC_PERST :: CCE_STATUS :: CCE_BAD_SECTION_ID [00:00] */
+#define BCHP_PCIE_MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_MASK    0x00000001
+#define BCHP_PCIE_MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_SHIFT   0
+
+#endif /* #ifndef BCHP_PCIE_MISC_PERST_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_pcie_rc_cfg_pcie.h b/include/linux/brcmstb/7425b0/bchp_pcie_rc_cfg_pcie.h
new file mode 100644
index 0000000..cf9129d
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_pcie_rc_cfg_pcie.h
@@ -0,0 +1,639 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:44 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_PCIE_RC_CFG_PCIE_H__
+#define BCHP_PCIE_RC_CFG_PCIE_H__
+
+/***************************************************************************
+ *PCIE_RC_CFG_PCIE
+ ***************************************************************************/
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY    0x004100ac /* pcie_capability */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY  0x004100b0 /* device_capability */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL 0x004100b4 /* device_status_control */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY    0x004100b8 /* link_capability */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL 0x004100bc /* link_status_control */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY    0x004100c0 /* slot_capability */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS 0x004100c4 /* slot_control_status */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL   0x004100c8 /* root_cap_control */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS        0x004100cc /* root_status */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_2 0x004100d0 /* device_capability_2 */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2 0x004100d4 /* device_status_control_2 */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_2  0x004100d8 /* link_capability_2 */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2 0x004100dc /* link_status_control_2 */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_2  0x004100e0 /* slot_capability_2 */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2 0x004100e4 /* slot_status_control_2 */
+
+/***************************************************************************
+ *PCIE_CAPABILITY - pcie_capability
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: PCIE_CAPABILITY :: RESERVED0 [31:30] */
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_RESERVED0_MASK       0xc0000000
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_RESERVED0_SHIFT      30
+
+/* PCIE_RC_CFG_PCIE :: PCIE_CAPABILITY :: MSG_NUM [29:25] */
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_MSG_NUM_MASK         0x3e000000
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_MSG_NUM_SHIFT        25
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_MSG_NUM_DEFAULT      0x00000000
+
+/* PCIE_RC_CFG_PCIE :: PCIE_CAPABILITY :: SLOT_IMPLEMENTED [24:24] */
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_SLOT_IMPLEMENTED_MASK 0x01000000
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_SLOT_IMPLEMENTED_SHIFT 24
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_SLOT_IMPLEMENTED_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: PCIE_CAPABILITY :: TYPE [23:20] */
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_TYPE_MASK            0x00f00000
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_TYPE_SHIFT           20
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_TYPE_DEFAULT         0x00000004
+
+/* PCIE_RC_CFG_PCIE :: PCIE_CAPABILITY :: VER [19:16] */
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_VER_MASK             0x000f0000
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_VER_SHIFT            16
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_VER_DEFAULT          0x00000002
+
+/* PCIE_RC_CFG_PCIE :: PCIE_CAPABILITY :: PCIE_NEXT_CAP_PTR [15:08] */
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_NEXT_CAP_PTR_MASK 0x0000ff00
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_NEXT_CAP_PTR_SHIFT 8
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_NEXT_CAP_PTR_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: PCIE_CAPABILITY :: PCIE_CAP_ID [07:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_CAP_ID_MASK     0x000000ff
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_CAP_ID_SHIFT    0
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_CAP_ID_DEFAULT  0x00000010
+
+/***************************************************************************
+ *DEVICE_CAPABILITY - device_capability
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY :: RESERVED3 [31:28] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED3_MASK     0xf0000000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED3_SHIFT    28
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY :: CAPTURED_SLOT_PWR_SCALE [27:26] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_SCALE_MASK 0x0c000000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_SCALE_SHIFT 26
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_SCALE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY :: CAPTURED_SLOT_PWR_VAL [25:18] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_VAL_MASK 0x03fc0000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_VAL_SHIFT 18
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_VAL_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY :: RESERVED2 [17:16] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED2_MASK     0x00030000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED2_SHIFT    16
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY :: ROLE_BASED_ERR_RPT [15:15] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT_MASK 0x00008000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT_SHIFT 15
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY :: RESERVED1 [14:12] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED1_MASK     0x00007000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED1_SHIFT    12
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY :: L1_ACCEPTABLE_LATENCY [11:09] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_MASK 0x00000e00
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_SHIFT 9
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY :: L0S_ACCEPTABLE_LATENCY [08:06] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY_MASK 0x000001c0
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY_SHIFT 6
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY :: EXTENDED_TAG_SUPPORT [05:05] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT_MASK 0x00000020
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT_SHIFT 5
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY :: RESERVED0 [04:03] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED0_MASK     0x00000018
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED0_SHIFT    3
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY :: MAX_PL_SIZE_SUPPORTED [02:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_MASK 0x00000007
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_SHIFT 0
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DEVICE_STATUS_CONTROL - device_status_control
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: RESERVED2 [31:22] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED2_MASK 0xffc00000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED2_SHIFT 22
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: NP_TRANSACTION_PEND [21:21] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NP_TRANSACTION_PEND_MASK 0x00200000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NP_TRANSACTION_PEND_SHIFT 21
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NP_TRANSACTION_PEND_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: AUX_PWR_DET [20:20] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_DET_MASK 0x00100000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_DET_SHIFT 20
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_DET_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: UNSUP_REQ_DET [19:19] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_UNSUP_REQ_DET_MASK 0x00080000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_UNSUP_REQ_DET_SHIFT 19
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_UNSUP_REQ_DET_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: FATAL_ERR_DET [18:18] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_DET_MASK 0x00040000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_DET_SHIFT 18
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_DET_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: NON_FATAL_ERR_DET [17:17] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NON_FATAL_ERR_DET_MASK 0x00020000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NON_FATAL_ERR_DET_SHIFT 17
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NON_FATAL_ERR_DET_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: CORR_ERR_DET [16:16] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_DET_MASK 0x00010000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_DET_SHIFT 16
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_DET_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: RESERVED1 [15:15] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED1_MASK 0x00008000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED1_SHIFT 15
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: MAX_READ_REQ_SIZ [14:12] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_READ_REQ_SIZ_MASK 0x00007000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_READ_REQ_SIZ_SHIFT 12
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_READ_REQ_SIZ_DEFAULT 0x00000002
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: NO_SNOOP_ENABLE [11:11] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NO_SNOOP_ENABLE_MASK 0x00000800
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NO_SNOOP_ENABLE_SHIFT 11
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NO_SNOOP_ENABLE_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: AUX_PWR_PM_ENA [10:10] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_PM_ENA_MASK 0x00000400
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_PM_ENA_SHIFT 10
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_PM_ENA_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: RESERVED0 [09:09] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED0_MASK 0x00000200
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED0_SHIFT 9
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: EXTENDED_TAG_EN [08:08] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_EXTENDED_TAG_EN_MASK 0x00000100
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_EXTENDED_TAG_EN_SHIFT 8
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_EXTENDED_TAG_EN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: MAX_PAYLOAD_SIZE [07:05] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_MASK 0x000000e0
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_SHIFT 5
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: RELAX_ORDERING_ENABLE [04:04] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RELAX_ORDERING_ENABLE_MASK 0x00000010
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RELAX_ORDERING_ENABLE_SHIFT 4
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RELAX_ORDERING_ENABLE_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: U_REQ_REPORT_EN [03:03] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_U_REQ_REPORT_EN_MASK 0x00000008
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_U_REQ_REPORT_EN_SHIFT 3
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_U_REQ_REPORT_EN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: FATAL_ERR_REPORT_EN [02:02] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_REPORT_EN_MASK 0x00000004
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_REPORT_EN_SHIFT 2
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_REPORT_EN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: NFATAL_ERR_REPORT_EN [01:01] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NFATAL_ERR_REPORT_EN_MASK 0x00000002
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NFATAL_ERR_REPORT_EN_SHIFT 1
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NFATAL_ERR_REPORT_EN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: CORR_ERR_REPORT_EN [00:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_REPORT_EN_MASK 0x00000001
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_REPORT_EN_SHIFT 0
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_REPORT_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *LINK_CAPABILITY - link_capability
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: PORT_NUMBER [31:24] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_PORT_NUMBER_MASK     0xff000000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_PORT_NUMBER_SHIFT    24
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_PORT_NUMBER_DEFAULT  0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: RESERVED0 [23:22] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_RESERVED0_MASK       0x00c00000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_RESERVED0_SHIFT      22
+
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: LINK_BW_NOTIFY [21:21] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_LINK_BW_NOTIFY_MASK  0x00200000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_LINK_BW_NOTIFY_SHIFT 21
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_LINK_BW_NOTIFY_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: DL_ACTIVE_REP [20:20] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_DL_ACTIVE_REP_MASK   0x00100000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_DL_ACTIVE_REP_SHIFT  20
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_DL_ACTIVE_REP_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: SUR_DWN_ERR_REP [19:19] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_SUR_DWN_ERR_REP_MASK 0x00080000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_SUR_DWN_ERR_REP_SHIFT 19
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_SUR_DWN_ERR_REP_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: CLK_PWR_MGMT [18:18] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_CLK_PWR_MGMT_MASK    0x00040000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_CLK_PWR_MGMT_SHIFT   18
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_CLK_PWR_MGMT_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: L1_EXIT_LAT [17:15] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_L1_EXIT_LAT_MASK     0x00038000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_L1_EXIT_LAT_SHIFT    15
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_L1_EXIT_LAT_DEFAULT  0x00000002
+
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: L0S_EXIT_LAT [14:12] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_L0S_EXIT_LAT_MASK    0x00007000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_L0S_EXIT_LAT_SHIFT   12
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_L0S_EXIT_LAT_DEFAULT 0x00000005
+
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: ASPM_SUPT [11:10] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_SUPT_MASK       0x00000c00
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_SUPT_SHIFT      10
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_SUPT_DEFAULT    0x00000003
+
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: MAX_LINK_WIDTH [09:04] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_WIDTH_MASK  0x000003f0
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_WIDTH_SHIFT 4
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_WIDTH_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: MAX_LINK_SPEED [03:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_SPEED_MASK  0x0000000f
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_SPEED_SHIFT 0
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_SPEED_DEFAULT 0x00000001
+
+/***************************************************************************
+ *LINK_STATUS_CONTROL - link_status_control
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RESERVED3 [31:30] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED3_MASK   0xc0000000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED3_SHIFT  30
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: DL_ACTIVE [29:29] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_DL_ACTIVE_MASK   0x20000000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_DL_ACTIVE_SHIFT  29
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_DL_ACTIVE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: SLOT_CLK_CONFIG [28:28] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_SLOT_CLK_CONFIG_MASK 0x10000000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_SLOT_CLK_CONFIG_SHIFT 28
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_SLOT_CLK_CONFIG_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_TRAINING [27:27] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_TRAINING_MASK 0x08000000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_TRAINING_SHIFT 27
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_TRAINING_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RESERVED2 [26:26] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED2_MASK   0x04000000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED2_SHIFT  26
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: NEG_LINK_WIDTH [25:20] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_MASK 0x03f00000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_SHIFT 20
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: NEG_LINK_SPEED [19:16] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_SPEED_MASK 0x000f0000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_SPEED_SHIFT 16
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_SPEED_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RESERVED1 [15:12] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED1_MASK   0x0000f000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED1_SHIFT  12
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_BW_INT_EN [11:11] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_INT_EN_MASK 0x00000800
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_INT_EN_SHIFT 11
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_INT_EN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_BW_MGMT_INT_EN [10:10] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_MGMT_INT_EN_MASK 0x00000400
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_MGMT_INT_EN_SHIFT 10
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_MGMT_INT_EN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: HW_AUTO_WIDTH_DIS [09:09] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_HW_AUTO_WIDTH_DIS_MASK 0x00000200
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_HW_AUTO_WIDTH_DIS_SHIFT 9
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_HW_AUTO_WIDTH_DIS_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: EN_CLK_PW_MGMT [08:08] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_EN_CLK_PW_MGMT_MASK 0x00000100
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_EN_CLK_PW_MGMT_SHIFT 8
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_EN_CLK_PW_MGMT_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_CR_EXT_SYNC [07:07] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_EXT_SYNC_MASK 0x00000080
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_EXT_SYNC_SHIFT 7
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_EXT_SYNC_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_CR_COMMON_CLK [06:06] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_COMMON_CLK_MASK 0x00000040
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_COMMON_CLK_SHIFT 6
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_COMMON_CLK_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: CFG_PSM_RETRAIN_LINK [05:05] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_RETRAIN_LINK_MASK 0x00000020
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_RETRAIN_LINK_SHIFT 5
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_RETRAIN_LINK_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: CFG_PSM_LINK_DISABLE [04:04] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_LINK_DISABLE_MASK 0x00000010
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_LINK_DISABLE_SHIFT 4
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_LINK_DISABLE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RCB [03:03] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_RCB_MASK         0x00000008
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_RCB_SHIFT        3
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_RCB_DEFAULT      0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RESERVED0 [02:02] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED0_MASK   0x00000004
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED0_SHIFT  2
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: ASPM_CTRL [01:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_ASPM_CTRL_MASK   0x00000003
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_ASPM_CTRL_SHIFT  0
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_ASPM_CTRL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SLOT_CAPABILITY - slot_capability
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: SLOT_CAPABILITY :: PHYSICAL_SLOT_NUMBER [31:19] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_PHYSICAL_SLOT_NUMBER_MASK 0xfff80000
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_PHYSICAL_SLOT_NUMBER_SHIFT 19
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_PHYSICAL_SLOT_NUMBER_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: SLOT_CAPABILITY :: UNUSED [18:17] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_MASK          0x00060000
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_SHIFT         17
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_DEFAULT       0x00000000
+
+/* PCIE_RC_CFG_PCIE :: SLOT_CAPABILITY :: SLOT_POWER_LIMIT_SCALE [16:15] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_SCALE_MASK 0x00018000
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_SCALE_SHIFT 15
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_SCALE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: SLOT_CAPABILITY :: SLOT_POWER_LIMIT_VALUE [14:07] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_VALUE_MASK 0x00007f80
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_VALUE_SHIFT 7
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_VALUE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: SLOT_CAPABILITY :: UNUSED_2 [06:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_2_MASK        0x0000007f
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_2_SHIFT       0
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_2_DEFAULT     0x00000000
+
+/***************************************************************************
+ *SLOT_CONTROL_STATUS - slot_control_status
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: SLOT_CONTROL_STATUS :: SLOT_STATUS [31:23] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_STATUS_MASK 0xff800000
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_STATUS_SHIFT 23
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_STATUS_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: SLOT_CONTROL_STATUS :: PRESENCE_DETECT [22:22] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_PRESENCE_DETECT_MASK 0x00400000
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_PRESENCE_DETECT_SHIFT 22
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_PRESENCE_DETECT_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: SLOT_CONTROL_STATUS :: UNUSED_1 [21:16] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_UNUSED_1_MASK    0x003f0000
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_UNUSED_1_SHIFT   16
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_UNUSED_1_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: SLOT_CONTROL_STATUS :: SLOT_CONTROL [15:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_CONTROL_MASK 0x0000ffff
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_CONTROL_SHIFT 0
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_CONTROL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ROOT_CAP_CONTROL - root_cap_control
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RESERVED1 [31:17] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RESERVED1_MASK      0xfffe0000
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RESERVED1_SHIFT     17
+
+/* PCIE_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_CRS_VISIBILITY [16:16] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_VISIBILITY_MASK 0x00010000
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_VISIBILITY_SHIFT 16
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_VISIBILITY_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RESERVED0 [15:05] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RESERVED0_MASK      0x0000ffe0
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RESERVED0_SHIFT     5
+
+/* PCIE_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_CRS_EN [04:04] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_MASK      0x00000010
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_SHIFT     4
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_DEFAULT   0x00000000
+
+/* PCIE_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_PME_INT_EN [03:03] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_PME_INT_EN_MASK  0x00000008
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_PME_INT_EN_SHIFT 3
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_PME_INT_EN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_FATAL_SERR_EN [02:02] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_FATAL_SERR_EN_MASK 0x00000004
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_FATAL_SERR_EN_SHIFT 2
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_FATAL_SERR_EN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_NONFATAL_SERR_EN [01:01] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_NONFATAL_SERR_EN_MASK 0x00000002
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_NONFATAL_SERR_EN_SHIFT 1
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_NONFATAL_SERR_EN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_CORR_SERR_EN [00:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CORR_SERR_EN_MASK 0x00000001
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CORR_SERR_EN_SHIFT 0
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CORR_SERR_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ROOT_STATUS - root_status
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: ROOT_STATUS :: RESERVED0 [31:18] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS_RESERVED0_MASK           0xfffc0000
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS_RESERVED0_SHIFT          18
+
+/* PCIE_RC_CFG_PCIE :: ROOT_STATUS :: RC_PME_PENDING [17:17] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS_RC_PME_PENDING_MASK      0x00020000
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS_RC_PME_PENDING_SHIFT     17
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS_RC_PME_PENDING_DEFAULT   0x00000000
+
+/* PCIE_RC_CFG_PCIE :: ROOT_STATUS :: RC_PME_STATUS [16:16] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS_RC_PME_STATUS_MASK       0x00010000
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS_RC_PME_STATUS_SHIFT      16
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS_RC_PME_STATUS_DEFAULT    0x00000000
+
+/* PCIE_RC_CFG_PCIE :: ROOT_STATUS :: RC_PME_REQ_ID [15:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS_RC_PME_REQ_ID_MASK       0x0000ffff
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS_RC_PME_REQ_ID_SHIFT      0
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS_RC_PME_REQ_ID_DEFAULT    0x00000000
+
+/***************************************************************************
+ *DEVICE_CAPABILITY_2 - device_capability_2
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY_2 :: RESERVED0 [31:05] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_2_RESERVED0_MASK   0xffffffe0
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_2_RESERVED0_SHIFT  5
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY_2 :: CMPL_TIMEOUT_DISABL_SUPPORTED [04:04] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_DISABL_SUPPORTED_MASK 0x00000010
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_DISABL_SUPPORTED_SHIFT 4
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_DISABL_SUPPORTED_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY_2 :: CMPL_TIMEOUT_RANGES_SUPPORTED [03:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_RANGES_SUPPORTED_MASK 0x0000000f
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_RANGES_SUPPORTED_SHIFT 0
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_RANGES_SUPPORTED_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *DEVICE_STATUS_CONTROL_2 - device_status_control_2
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL_2 :: DEVICE_STATUS_2 [31:16] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_DEVICE_STATUS_2_MASK 0xffff0000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_DEVICE_STATUS_2_SHIFT 16
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_DEVICE_STATUS_2_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL_2 :: RESERVED0 [15:05] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_RESERVED0_MASK 0x0000ffe0
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_RESERVED0_SHIFT 5
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL_2 :: CMPL_TIMEOUT_DISABLE [04:04] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_DISABLE_MASK 0x00000010
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_DISABLE_SHIFT 4
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_DISABLE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL_2 :: CMPL_TIMEOUT_VALUE [03:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_VALUE_MASK 0x0000000f
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_VALUE_SHIFT 0
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_VALUE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *LINK_CAPABILITY_2 - link_capability_2
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY_2 :: LINK_CAPABILITY_2 [31:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_2_LINK_CAPABILITY_2_MASK 0xffffffff
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_2_LINK_CAPABILITY_2_SHIFT 0
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_2_LINK_CAPABILITY_2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *LINK_STATUS_CONTROL_2 - link_status_control_2
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: LINK_STATUS_2 [31:17] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_LINK_STATUS_2_MASK 0xfffe0000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_LINK_STATUS_2_SHIFT 17
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_LINK_STATUS_2_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CURR_DEEMPH_LEVEL [16:16] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CURR_DEEMPH_LEVEL_MASK 0x00010000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CURR_DEEMPH_LEVEL_SHIFT 16
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CURR_DEEMPH_LEVEL_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: RESERVED0 [15:13] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_RESERVED0_MASK 0x0000e000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_RESERVED0_SHIFT 13
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CFG_COMPLIANCE_DEEMPH [12:12] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_DEEMPH_MASK 0x00001000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_DEEMPH_SHIFT 12
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_DEEMPH_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CFG_COMPLIANCE_SOS [11:11] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_SOS_MASK 0x00000800
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_SOS_SHIFT 11
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_SOS_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CFG_ENTER_MOD_COMPLIANCE [10:10] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_ENTER_MOD_COMPLIANCE_MASK 0x00000400
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_ENTER_MOD_COMPLIANCE_SHIFT 10
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_ENTER_MOD_COMPLIANCE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CFG_TX_MARGIN [09:07] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_TX_MARGIN_MASK 0x00000380
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_TX_MARGIN_SHIFT 7
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_TX_MARGIN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: SEL_DEEMPHASIS [06:06] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_SEL_DEEMPHASIS_MASK 0x00000040
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_SEL_DEEMPHASIS_SHIFT 6
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_SEL_DEEMPHASIS_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: HW_AUTO_SPEED_DISABLE [05:05] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_HW_AUTO_SPEED_DISABLE_MASK 0x00000020
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_HW_AUTO_SPEED_DISABLE_SHIFT 5
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_HW_AUTO_SPEED_DISABLE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: ENTER_COMPLIANCE [04:04] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_ENTER_COMPLIANCE_MASK 0x00000010
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_ENTER_COMPLIANCE_SHIFT 4
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_ENTER_COMPLIANCE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: TARGET_LINK_SPEED [03:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_MASK 0x0000000f
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_SHIFT 0
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SLOT_CAPABILITY_2 - slot_capability_2
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: SLOT_CAPABILITY_2 :: SLOT_CAPABILITY_2 [31:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_2_SLOT_CAPABILITY_2_MASK 0xffffffff
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_2_SLOT_CAPABILITY_2_SHIFT 0
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_2_SLOT_CAPABILITY_2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SLOT_STATUS_CONTROL_2 - slot_status_control_2
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: SLOT_STATUS_CONTROL_2 :: SLOT_STATUS_2 [31:16] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_STATUS_2_MASK 0xffff0000
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_STATUS_2_SHIFT 16
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_STATUS_2_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: SLOT_STATUS_CONTROL_2 :: SLOT_CONTROL_2 [15:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_CONTROL_2_MASK 0x0000ffff
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_CONTROL_2_SHIFT 0
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_CONTROL_2_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_PCIE_RC_CFG_PCIE_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_pcie_rc_cfg_type1.h b/include/linux/brcmstb/7425b0/bchp_pcie_rc_cfg_type1.h
new file mode 100644
index 0000000..9be7289b
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_pcie_rc_cfg_type1.h
@@ -0,0 +1,526 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:44 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_PCIE_RC_CFG_TYPE1_H__
+#define BCHP_PCIE_RC_CFG_TYPE1_H__
+
+/***************************************************************************
+ *PCIE_RC_CFG_TYPE1
+ ***************************************************************************/
+#define BCHP_PCIE_RC_CFG_TYPE1_DEVICE_VENDOR_ID  0x00410000 /* device_vendor_id */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND    0x00410004 /* status_command */
+#define BCHP_PCIE_RC_CFG_TYPE1_REV_ID_CLASS_CODE 0x00410008 /* rev_id_class_code */
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE 0x0041000c /* headertype_lat_cachelinesize */
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1             0x00410010 /* bar_1 */
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_2             0x00410014 /* bar_2 */
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO    0x00410018 /* pri_sec_bus_no */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT 0x0041001c /* sec_status_io_base_limit */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT 0x00410020 /* rc_mem_base_limit */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT 0x00410024 /* rc_pref_base_limit */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_HI   0x00410028 /* rc_pref_base_hi */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_LIM_HI    0x0041002c /* rc_pref_lim_hi */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_IO_BASE_LIMIT  0x00410030 /* rc_io_base_limit */
+#define BCHP_PCIE_RC_CFG_TYPE1_CAP_POINTER       0x00410034 /* cap_pointer */
+#define BCHP_PCIE_RC_CFG_TYPE1_EXP_ROM_BAR       0x00410038 /* exp_rom_bar */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL    0x0041003c /* bridge_control */
+
+/***************************************************************************
+ *DEVICE_VENDOR_ID - device_vendor_id
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: DEVICE_VENDOR_ID :: DEVICE_ID [31:16] */
+#define BCHP_PCIE_RC_CFG_TYPE1_DEVICE_VENDOR_ID_DEVICE_ID_MASK     0xffff0000
+#define BCHP_PCIE_RC_CFG_TYPE1_DEVICE_VENDOR_ID_DEVICE_ID_SHIFT    16
+
+/* PCIE_RC_CFG_TYPE1 :: DEVICE_VENDOR_ID :: VENDOR_ID [15:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_DEVICE_VENDOR_ID_VENDOR_ID_MASK     0x0000ffff
+#define BCHP_PCIE_RC_CFG_TYPE1_DEVICE_VENDOR_ID_VENDOR_ID_SHIFT    0
+#define BCHP_PCIE_RC_CFG_TYPE1_DEVICE_VENDOR_ID_VENDOR_ID_DEFAULT  0x000014e4
+
+/***************************************************************************
+ *STATUS_COMMAND - status_command
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: PAR_ERR [31:31] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_PAR_ERR_MASK         0x80000000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_PAR_ERR_SHIFT        31
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_PAR_ERR_DEFAULT      0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: SIG_SERR [30:30] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SIG_SERR_MASK        0x40000000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SIG_SERR_SHIFT       30
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SIG_SERR_DEFAULT     0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: RCV_MSTR_ABT [29:29] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RCV_MSTR_ABT_MASK    0x20000000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RCV_MSTR_ABT_SHIFT   29
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RCV_MSTR_ABT_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: RCV_TGT_ABT [28:28] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RCV_TGT_ABT_MASK     0x10000000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RCV_TGT_ABT_SHIFT    28
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RCV_TGT_ABT_DEFAULT  0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: SIG_TGT_ABT [27:27] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SIG_TGT_ABT_MASK     0x08000000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SIG_TGT_ABT_SHIFT    27
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SIG_TGT_ABT_DEFAULT  0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: DEVSEL_TIMING [26:25] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_DEVSEL_TIMING_MASK   0x06000000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_DEVSEL_TIMING_SHIFT  25
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_DEVSEL_TIMING_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: MSTR_PERR [24:24] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_MSTR_PERR_MASK       0x01000000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_MSTR_PERR_SHIFT      24
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_MSTR_PERR_DEFAULT    0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: FAST_B2B_CAP [23:23] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_CAP_MASK    0x00800000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_CAP_SHIFT   23
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_CAP_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: RESERVED1 [22:22] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED1_MASK       0x00400000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED1_SHIFT      22
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED1_DEFAULT    0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: CAP_66MHZ [21:21] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_CAP_66MHZ_MASK       0x00200000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_CAP_66MHZ_SHIFT      21
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_CAP_66MHZ_DEFAULT    0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: CAP_LIST [20:20] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_CAP_LIST_MASK        0x00100000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_CAP_LIST_SHIFT       20
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_CAP_LIST_DEFAULT     0x00000001
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: INT_STATUS [19:19] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_INT_STATUS_MASK      0x00080000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_INT_STATUS_SHIFT     19
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_INT_STATUS_DEFAULT   0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: RESERVED2 [18:16] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED2_MASK       0x00070000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED2_SHIFT      16
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED2_DEFAULT    0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: RESERVED [15:11] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED_MASK        0x0000f800
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED_SHIFT       11
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED_DEFAULT     0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: INT_DISABLE [10:10] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_INT_DISABLE_MASK     0x00000400
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_INT_DISABLE_SHIFT    10
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_INT_DISABLE_DEFAULT  0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: FAST_B2B [09:09] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_MASK        0x00000200
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_SHIFT       9
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_DEFAULT     0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: SERR_ENA [08:08] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SERR_ENA_MASK        0x00000100
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SERR_ENA_SHIFT       8
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SERR_ENA_DEFAULT     0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: STEPPING [07:07] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_STEPPING_MASK        0x00000080
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_STEPPING_SHIFT       7
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_STEPPING_DEFAULT     0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: PERR_ENA [06:06] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_PERR_ENA_MASK        0x00000040
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_PERR_ENA_SHIFT       6
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_PERR_ENA_DEFAULT     0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: VGA_SNOOP [05:05] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_VGA_SNOOP_MASK       0x00000020
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_VGA_SNOOP_SHIFT      5
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_VGA_SNOOP_DEFAULT    0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: MWI_CYCLES [04:04] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_MWI_CYCLES_MASK      0x00000010
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_MWI_CYCLES_SHIFT     4
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_MWI_CYCLES_DEFAULT   0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: SPECIAL_CYCLES [03:03] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SPECIAL_CYCLES_MASK  0x00000008
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SPECIAL_CYCLES_SHIFT 3
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SPECIAL_CYCLES_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: BUS_MASTER [02:02] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_BUS_MASTER_MASK      0x00000004
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_BUS_MASTER_SHIFT     2
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_BUS_MASTER_DEFAULT   0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: MEM_SPACE [01:01] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_MEM_SPACE_MASK       0x00000002
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_MEM_SPACE_SHIFT      1
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_MEM_SPACE_DEFAULT    0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: IO_SPACE [00:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_IO_SPACE_MASK        0x00000001
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_IO_SPACE_SHIFT       0
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_IO_SPACE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *REV_ID_CLASS_CODE - rev_id_class_code
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: REV_ID_CLASS_CODE :: CLASS_CODE [31:08] */
+#define BCHP_PCIE_RC_CFG_TYPE1_REV_ID_CLASS_CODE_CLASS_CODE_MASK   0xffffff00
+#define BCHP_PCIE_RC_CFG_TYPE1_REV_ID_CLASS_CODE_CLASS_CODE_SHIFT  8
+#define BCHP_PCIE_RC_CFG_TYPE1_REV_ID_CLASS_CODE_CLASS_CODE_DEFAULT 0x00020000
+
+/* PCIE_RC_CFG_TYPE1 :: REV_ID_CLASS_CODE :: REV_ID [07:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_REV_ID_CLASS_CODE_REV_ID_MASK       0x000000ff
+#define BCHP_PCIE_RC_CFG_TYPE1_REV_ID_CLASS_CODE_REV_ID_SHIFT      0
+
+/***************************************************************************
+ *HEADERTYPE_LAT_CACHELINESIZE - headertype_lat_cachelinesize
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: HEADERTYPE_LAT_CACHELINESIZE :: BIST [31:24] */
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_BIST_MASK 0xff000000
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_BIST_SHIFT 24
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_BIST_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: HEADERTYPE_LAT_CACHELINESIZE :: HEADER_TYPE [23:16] */
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_HEADER_TYPE_MASK 0x00ff0000
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_HEADER_TYPE_SHIFT 16
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_HEADER_TYPE_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_TYPE1 :: HEADERTYPE_LAT_CACHELINESIZE :: LATENCY_TIMER [15:08] */
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_LATENCY_TIMER_MASK 0x0000ff00
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_LATENCY_TIMER_SHIFT 8
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_LATENCY_TIMER_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: HEADERTYPE_LAT_CACHELINESIZE :: CACHE_LINE_SIZE [07:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_CACHE_LINE_SIZE_MASK 0x000000ff
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_CACHE_LINE_SIZE_SHIFT 0
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_CACHE_LINE_SIZE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BAR_1 - bar_1
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: BAR_1 :: ADDRESS [31:04] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_ADDRESS_MASK                  0xfffffff0
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_ADDRESS_SHIFT                 4
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_ADDRESS_DEFAULT               0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: BAR_1 :: PREFETCH [03:03] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_PREFETCH_MASK                 0x00000008
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_PREFETCH_SHIFT                3
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_PREFETCH_DEFAULT              0x00000001
+
+/* PCIE_RC_CFG_TYPE1 :: BAR_1 :: SPACE_TYPE [02:01] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_SPACE_TYPE_MASK               0x00000006
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_SPACE_TYPE_SHIFT              1
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_SPACE_TYPE_DEFAULT            0x00000002
+
+/* PCIE_RC_CFG_TYPE1 :: BAR_1 :: MEM_SPACE [00:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_MEM_SPACE_MASK                0x00000001
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_MEM_SPACE_SHIFT               0
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_MEM_SPACE_DEFAULT             0x00000000
+
+/***************************************************************************
+ *BAR_2 - bar_2
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: BAR_2 :: ADDR [31:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_2_ADDR_MASK                     0xffffffff
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_2_ADDR_SHIFT                    0
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_2_ADDR_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PRI_SEC_BUS_NO - pri_sec_bus_no
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: PRI_SEC_BUS_NO :: SEC_LATENCY_TIMER [31:24] */
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_LATENCY_TIMER_MASK 0xff000000
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_LATENCY_TIMER_SHIFT 24
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_LATENCY_TIMER_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: PRI_SEC_BUS_NO :: SUB_BUS_NO [23:16] */
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_MASK      0x00ff0000
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_SHIFT     16
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_DEFAULT   0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: PRI_SEC_BUS_NO :: SEC_BUS_NO [15:08] */
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_MASK      0x0000ff00
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_SHIFT     8
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_DEFAULT   0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: PRI_SEC_BUS_NO :: PRI_BUS_NO [07:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_MASK      0x000000ff
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_SHIFT     0
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_DEFAULT   0x00000000
+
+/***************************************************************************
+ *SEC_STATUS_IO_BASE_LIMIT - sec_status_io_base_limit
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_DETECTED_PARITY_ERROR [31:31] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_DETECTED_PARITY_ERROR_MASK 0x80000000
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_DETECTED_PARITY_ERROR_SHIFT 31
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_DETECTED_PARITY_ERROR_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_RECEIVED_SYSTEM_ERROR [30:30] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_SYSTEM_ERROR_MASK 0x40000000
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_SYSTEM_ERROR_SHIFT 30
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_SYSTEM_ERROR_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_RECEIVED_MASTER_ABORT [29:29] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_MASTER_ABORT_MASK 0x20000000
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_MASTER_ABORT_SHIFT 29
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_MASTER_ABORT_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_RECEIVED_TARGET_ABORT [28:28] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_TARGET_ABORT_MASK 0x10000000
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_TARGET_ABORT_SHIFT 28
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_TARGET_ABORT_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_SIGNALED_TARGET_ABORT [27:27] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_SIGNALED_TARGET_ABORT_MASK 0x08000000
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_SIGNALED_TARGET_ABORT_SHIFT 27
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_SIGNALED_TARGET_ABORT_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: DEVICE_TIMING [26:25] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_DEVICE_TIMING_MASK 0x06000000
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_DEVICE_TIMING_SHIFT 25
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_DEVICE_TIMING_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_MASTER_DATA_PARITY_ERROR [24:24] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_MASTER_DATA_PARITY_ERROR_MASK 0x01000000
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_MASTER_DATA_PARITY_ERROR_SHIFT 24
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_MASTER_DATA_PARITY_ERROR_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: FAST_B2B [23:23] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_FAST_B2B_MASK 0x00800000
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_FAST_B2B_SHIFT 23
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_FAST_B2B_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: RESERVED3 [22:22] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED3_MASK 0x00400000
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED3_SHIFT 22
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED3_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: CAP_66_MHZ [21:21] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_CAP_66_MHZ_MASK 0x00200000
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_CAP_66_MHZ_SHIFT 21
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_CAP_66_MHZ_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: RESERVED4 [20:16] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED4_MASK 0x001f0000
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED4_SHIFT 16
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED4_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: IO_LIMIT [15:08] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_LIMIT_MASK 0x0000ff00
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_LIMIT_SHIFT 8
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_LIMIT_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: IO_BASE [07:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_BASE_MASK 0x000000ff
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_BASE_SHIFT 0
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_BASE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RC_MEM_BASE_LIMIT - rc_mem_base_limit
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: RC_MEM_BASE_LIMIT :: RC_MEM_LIMIT [31:20] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_MASK 0xfff00000
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_SHIFT 20
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: RC_MEM_BASE_LIMIT :: RC_MEM_LIMIT_3TO0 [19:16] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_3TO0_MASK 0x000f0000
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_3TO0_SHIFT 16
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_3TO0_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: RC_MEM_BASE_LIMIT :: RC_MEM_BASE [15:04] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_MASK  0x0000fff0
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_SHIFT 4
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: RC_MEM_BASE_LIMIT :: RC_MEM_BASE_3TO0 [03:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_3TO0_MASK 0x0000000f
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_3TO0_SHIFT 0
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_3TO0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RC_PREF_BASE_LIMIT - rc_pref_base_limit
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: RC_PREF_BASE_LIMIT :: RC_PREF_LIM [31:20] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIM_MASK 0xfff00000
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIM_SHIFT 20
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIM_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: RC_PREF_BASE_LIMIT :: RC_PREF_LIMIT_3TO0 [19:16] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIMIT_3TO0_MASK 0x000f0000
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIMIT_3TO0_SHIFT 16
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIMIT_3TO0_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_TYPE1 :: RC_PREF_BASE_LIMIT :: RC_PREF_BASE [15:04] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_MASK 0x0000fff0
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_SHIFT 4
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: RC_PREF_BASE_LIMIT :: RC_PREF_BASE_3TO0 [03:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_3TO0_MASK 0x0000000f
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_3TO0_SHIFT 0
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_3TO0_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RC_PREF_BASE_HI - rc_pref_base_hi
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: RC_PREF_BASE_HI :: RC_PREF_BASE_HI [31:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_HI_RC_PREF_BASE_HI_MASK 0xffffffff
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_HI_RC_PREF_BASE_HI_SHIFT 0
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_HI_RC_PREF_BASE_HI_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RC_PREF_LIM_HI - rc_pref_lim_hi
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: RC_PREF_LIM_HI :: RC_PREF_BASE_HI [31:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_LIM_HI_RC_PREF_BASE_HI_MASK 0xffffffff
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_LIM_HI_RC_PREF_BASE_HI_SHIFT 0
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_LIM_HI_RC_PREF_BASE_HI_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RC_IO_BASE_LIMIT - rc_io_base_limit
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: RC_IO_BASE_LIMIT :: RC_IO_LIM_HI [31:16] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_LIM_HI_MASK  0xffff0000
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_LIM_HI_SHIFT 16
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_LIM_HI_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: RC_IO_BASE_LIMIT :: RC_IO_BASE_HI [15:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_BASE_HI_MASK 0x0000ffff
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_BASE_HI_SHIFT 0
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_BASE_HI_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CAP_POINTER - cap_pointer
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: CAP_POINTER :: RESERVED0 [31:08] */
+#define BCHP_PCIE_RC_CFG_TYPE1_CAP_POINTER_RESERVED0_MASK          0xffffff00
+#define BCHP_PCIE_RC_CFG_TYPE1_CAP_POINTER_RESERVED0_SHIFT         8
+
+/* PCIE_RC_CFG_TYPE1 :: CAP_POINTER :: CAP_POINTER [07:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_CAP_POINTER_CAP_POINTER_MASK        0x000000ff
+#define BCHP_PCIE_RC_CFG_TYPE1_CAP_POINTER_CAP_POINTER_SHIFT       0
+#define BCHP_PCIE_RC_CFG_TYPE1_CAP_POINTER_CAP_POINTER_DEFAULT     0x00000048
+
+/***************************************************************************
+ *EXP_ROM_BAR - exp_rom_bar
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: EXP_ROM_BAR :: RESERVED0 [31:08] */
+#define BCHP_PCIE_RC_CFG_TYPE1_EXP_ROM_BAR_RESERVED0_MASK          0xffffff00
+#define BCHP_PCIE_RC_CFG_TYPE1_EXP_ROM_BAR_RESERVED0_SHIFT         8
+
+/* PCIE_RC_CFG_TYPE1 :: EXP_ROM_BAR :: EXP_ROM_BAR [07:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_EXP_ROM_BAR_EXP_ROM_BAR_MASK        0x000000ff
+#define BCHP_PCIE_RC_CFG_TYPE1_EXP_ROM_BAR_EXP_ROM_BAR_SHIFT       0
+#define BCHP_PCIE_RC_CFG_TYPE1_EXP_ROM_BAR_EXP_ROM_BAR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *BRIDGE_CONTROL - bridge_control
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: RESERVED1 [31:28] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_RESERVED1_MASK       0xf0000000
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_RESERVED1_SHIFT      28
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: DISCARD_TIMER_SERR_EN [27:27] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_SERR_EN_MASK 0x08000000
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_SERR_EN_SHIFT 27
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_SERR_EN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: DISCARD_TIMER_STATUS [26:26] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_STATUS_MASK 0x04000000
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_STATUS_SHIFT 26
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_STATUS_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: SEC_DISCARD_TIMER [25:25] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_DISCARD_TIMER_MASK 0x02000000
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_DISCARD_TIMER_SHIFT 25
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_DISCARD_TIMER_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: PRIM_DISCARD_TIMER [24:24] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_PRIM_DISCARD_TIMER_MASK 0x01000000
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_PRIM_DISCARD_TIMER_SHIFT 24
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_PRIM_DISCARD_TIMER_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: FAST_B2B_EN [23:23] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_FAST_B2B_EN_MASK     0x00800000
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_FAST_B2B_EN_SHIFT    23
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_FAST_B2B_EN_DEFAULT  0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: SEC_BUS_RESET [22:22] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_BUS_RESET_MASK   0x00400000
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_BUS_RESET_SHIFT  22
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_BUS_RESET_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: MASTER_ABORT_MODE [21:21] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_MASTER_ABORT_MODE_MASK 0x00200000
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_MASTER_ABORT_MODE_SHIFT 21
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_MASTER_ABORT_MODE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: RESERVED0 [20:18] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_RESERVED0_MASK       0x001c0000
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_RESERVED0_SHIFT      18
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: SEC_SERR_EN [17:17] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_SERR_EN_MASK     0x00020000
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_SERR_EN_SHIFT    17
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_SERR_EN_DEFAULT  0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: SEC_PERR_RESP_EN [16:16] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_PERR_RESP_EN_MASK 0x00010000
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_PERR_RESP_EN_SHIFT 16
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_PERR_RESP_EN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: INT_PIN [15:08] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_PIN_MASK         0x0000ff00
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_PIN_SHIFT        8
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_PIN_DEFAULT      0x00000001
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: INT_LINE [07:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_LINE_MASK        0x000000ff
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_LINE_SHIFT       0
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_LINE_DEFAULT     0x00000000
+
+#endif /* #ifndef BCHP_PCIE_RC_CFG_TYPE1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_pcie_rc_cfg_vendor.h b/include/linux/brcmstb/7425b0/bchp_pcie_rc_cfg_vendor.h
new file mode 100644
index 0000000..01f65479
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_pcie_rc_cfg_vendor.h
@@ -0,0 +1,173 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:42 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_PCIE_RC_CFG_VENDOR_H__
+#define BCHP_PCIE_RC_CFG_VENDOR_H__
+
+/***************************************************************************
+ *PCIE_RC_CFG_VENDOR
+ ***************************************************************************/
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_CAP       0x00410180 /* vendor_cap */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER 0x00410184 /* vendor_specific_header */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x00410188 /* Vendor Specific User Register 1 */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG2 0x0041018c /* Vendor Specific User Register 2 */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG3 0x00410190 /* Vendor Specific User Register 3 */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG4 0x00410194 /* Vendor Specific User Register 4 */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG5 0x00410198 /* Vendor Specific User Register 5 */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG6 0x0041019c /* Vendor Specific User Register 6 */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG7 0x004101a0 /* Vendor Specific User Register 7 */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG8 0x004101a4 /* Vendor Specific User Register 8 */
+
+/***************************************************************************
+ *VENDOR_CAP - vendor_cap
+ ***************************************************************************/
+/* PCIE_RC_CFG_VENDOR :: VENDOR_CAP :: NEXT [31:20] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_CAP_NEXT_MASK               0xfff00000
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_CAP_NEXT_SHIFT              20
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_CAP_NEXT_DEFAULT            0x00000000
+
+/* PCIE_RC_CFG_VENDOR :: VENDOR_CAP :: CAP_VER [19:16] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_CAP_CAP_VER_MASK            0x000f0000
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_CAP_CAP_VER_SHIFT           16
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_CAP_CAP_VER_DEFAULT         0x00000001
+
+/* PCIE_RC_CFG_VENDOR :: VENDOR_CAP :: VENDOR_SPEC_CAP_ID [15:00] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_CAP_VENDOR_SPEC_CAP_ID_MASK 0x0000ffff
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_CAP_VENDOR_SPEC_CAP_ID_SHIFT 0
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_CAP_VENDOR_SPEC_CAP_ID_DEFAULT 0x0000000b
+
+/***************************************************************************
+ *VENDOR_SPECIFIC_HEADER - vendor_specific_header
+ ***************************************************************************/
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_HEADER :: VSEC_LENGTH [31:20] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH_MASK 0xfff00000
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH_SHIFT 20
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH_DEFAULT 0x00000028
+
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_HEADER :: VSEC_REV [19:16] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_REV_MASK 0x000f0000
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_REV_SHIFT 16
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_REV_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_HEADER :: VSEC_ID [15:00] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_ID_MASK 0x0000ffff
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_ID_SHIFT 0
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_ID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VENDOR_SPECIFIC_REG1 - Vendor Specific User Register 1
+ ***************************************************************************/
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG1 :: Undefined [31:06] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_Undefined_MASK 0xffffffc0
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_Undefined_SHIFT 6
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_Undefined_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG1 :: ENDIAN_MODE_BAR3 [05:04] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3_MASK 0x00000030
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3_SHIFT 4
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG1 :: ENDIAN_MODE_BAR2 [03:02] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0x0000000c
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT 2
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG1 :: ENDIAN_MODE_BAR1 [01:00] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1_MASK 0x00000003
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1_SHIFT 0
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VENDOR_SPECIFIC_REG2 - Vendor Specific User Register 2
+ ***************************************************************************/
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG2 :: Undefined [31:00] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG2_Undefined_MASK 0xffffffff
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG2_Undefined_SHIFT 0
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG2_Undefined_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VENDOR_SPECIFIC_REG3 - Vendor Specific User Register 3
+ ***************************************************************************/
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG3 :: Undefined [31:00] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG3_Undefined_MASK 0xffffffff
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG3_Undefined_SHIFT 0
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG3_Undefined_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VENDOR_SPECIFIC_REG4 - Vendor Specific User Register 4
+ ***************************************************************************/
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG4 :: Undefined [31:00] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG4_Undefined_MASK 0xffffffff
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG4_Undefined_SHIFT 0
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG4_Undefined_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VENDOR_SPECIFIC_REG5 - Vendor Specific User Register 5
+ ***************************************************************************/
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG5 :: Undefined [31:00] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG5_Undefined_MASK 0xffffffff
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG5_Undefined_SHIFT 0
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG5_Undefined_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VENDOR_SPECIFIC_REG6 - Vendor Specific User Register 6
+ ***************************************************************************/
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG6 :: Undefined [31:00] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG6_Undefined_MASK 0xffffffff
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG6_Undefined_SHIFT 0
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG6_Undefined_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VENDOR_SPECIFIC_REG7 - Vendor Specific User Register 7
+ ***************************************************************************/
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG7 :: Undefined [31:00] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG7_Undefined_MASK 0xffffffff
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG7_Undefined_SHIFT 0
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG7_Undefined_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VENDOR_SPECIFIC_REG8 - Vendor Specific User Register 8
+ ***************************************************************************/
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG8 :: Undefined [31:00] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG8_Undefined_MASK 0xffffffff
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG8_Undefined_SHIFT 0
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG8_Undefined_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_PCIE_RC_CFG_VENDOR_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_sata_top_ctrl.h b/include/linux/brcmstb/7425b0/bchp_sata_top_ctrl.h
new file mode 100644
index 0000000..7fe0235
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_sata_top_ctrl.h
@@ -0,0 +1,161 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:44 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SATA_TOP_CTRL_H__
+#define BCHP_SATA_TOP_CTRL_H__
+
+/***************************************************************************
+ *SATA_TOP_CTRL - SATA3 MISC Control Registers
+ ***************************************************************************/
+#define BCHP_SATA_TOP_CTRL_Version               0x00180020 /* SATA3 Version Register */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL              0x00180024 /* SATA3 System Bus Access Control Register */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL               0x00180028 /* SATA3 Test Port Control register */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1            0x0018002c /* SATA3 phy interface control 1 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2            0x00180030 /* SATA3 phy interface control 2 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3            0x00180034 /* SATA3 phy interface control 3 */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT           0x00180038 /* SATA3 TP OUT */
+
+/***************************************************************************
+ *Version - SATA3 Version Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: Version :: reserved0 [31:08] */
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_MASK                  0xffffff00
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_SHIFT                 8
+
+/* SATA_TOP_CTRL :: Version :: major_version [07:04] */
+#define BCHP_SATA_TOP_CTRL_Version_major_version_MASK              0x000000f0
+#define BCHP_SATA_TOP_CTRL_Version_major_version_SHIFT             4
+#define BCHP_SATA_TOP_CTRL_Version_major_version_DEFAULT           0x00000000
+
+/* SATA_TOP_CTRL :: Version :: minor_version [03:00] */
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_MASK              0x0000000f
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_SHIFT             0
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_DEFAULT           0x00000001
+
+/***************************************************************************
+ *BUS_CTRL - SATA3 System Bus Access Control Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_31_17 [31:17] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_MASK            0xfffe0000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_SHIFT           17
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_DEFAULT         0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: overide_hwinit_registers [16:16] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_MASK  0x00010000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_SHIFT 16
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_DEFAULT 0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_15_8 [15:08] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_MASK             0x0000ff00
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_SHIFT            8
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_DEFAULT          0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: piodata_endian_ctrl [07:06] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_MASK       0x000000c0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SHIFT      6
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadata_endian_ctrl [05:04] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_MASK       0x00000030
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SHIFT      4
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadesc_endian_ctrl [03:02] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_MASK       0x0000000c
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SHIFT      2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: reg_endian_ctrl [01:00] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_MASK           0x00000003
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SHIFT          0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_DEFAULT        0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SwapEndianess  2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_HalfWordSwap   1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_NoSwap         0
+
+/***************************************************************************
+ *TP_CTRL - SATA3 Test Port Control register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: TP_CTRL :: tp_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_MASK                    0xffffffff
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_SHIFT                   0
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_1 - SATA3 phy interface control 1
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_1 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_2 - SATA3 phy interface control 2
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_2 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_3 - SATA3 phy interface control 3
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_3 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *SATA_TP_OUT - SATA3 TP OUT
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: SATA_TP_OUT :: TP_OUT [31:00] */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_MASK                 0xffffffff
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_SHIFT                0
+
+#endif /* #ifndef BCHP_SATA_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_sdio_0_cfg.h b/include/linux/brcmstb/7425b0/bchp_sdio_0_cfg.h
new file mode 100644
index 0000000..9575a05
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_sdio_0_cfg.h
@@ -0,0 +1,627 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:44 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SDIO_0_CFG_H__
+#define BCHP_SDIO_0_CFG_H__
+
+/***************************************************************************
+ *SDIO_0_CFG - SDIO (CARD) Configuration Registers
+ ***************************************************************************/
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1          0x00419100 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2          0x00419104 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL               0x00419108 /* SDIO TP_OUT Control Register */
+#define BCHP_SDIO_0_CFG_CAP_REG0                 0x0041910c /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_CAP_REG1                 0x00419110 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET1                  0x00419114 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET2                  0x00419118 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY           0x0041911c /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV               0x00419120 /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_IP_DLY                   0x00419130 /* SDIO Host input delay register */
+#define BCHP_SDIO_0_CFG_OP_DLY                   0x00419134 /* SDIO Host output delay register */
+#define BCHP_SDIO_0_CFG_TUNING                   0x00419138 /* SDIO Host tuning configuration register */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL                0x0041913c /* SDIO Host 1p8V control logic select register */
+#define BCHP_SDIO_0_CFG_SCRATCH                  0x004191fc /* SDIO Scratch Register */
+#define BCHP_SDIO_0_CFG_VERSION                  0x004191f0 /* SDIO VERSION Register */
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL1 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_SEL_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_MASK    0x80000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_SHIFT   31
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_DEFAULT 0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_LEV [30:30] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_MASK       0x40000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_SHIFT      30
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: CFG_RESERVED [29:29] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_MASK          0x20000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_SHIFT         29
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: RETUNING_REQ [28:28] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_MASK          0x10000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_SHIFT         28
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DDR_TAP_DELAY [27:24] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_MASK         0x0f000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_SHIFT        24
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_DEFAULT      0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DELAY_CTRL [23:21] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_MASK            0x00e00000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_SHIFT           21
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_DEFAULT         0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_ENA [20:20] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_MASK       0x00100000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_SHIFT      20
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_PULSE [19:19] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_MASK     0x00080000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_SHIFT    19
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DATA_PENDING [18:18] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_MASK          0x00040000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_SHIFT         18
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WR_FLUSH [17:17] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_MASK              0x00020000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_SHIFT             17
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: MF_NUM_WR [16:16] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_MASK             0x00010000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_SHIFT            16
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WORD_ABO [15:15] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_MASK              0x00008000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_SHIFT             15
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NBO [14:14] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_MASK             0x00004000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_SHIFT            14
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NHW [13:13] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_MASK             0x00002000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_SHIFT            13
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: BUFFER_ABO [12:12] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_MASK            0x00001000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_SHIFT           12
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_DEFAULT         0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_BUF_ACC [11:11] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_MASK           0x00000800
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_SHIFT          11
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_DEFAULT        0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SEQ_EN [10:10] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_MASK            0x00000400
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_SHIFT           10
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_DEFAULT         0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_RD_THRESH [09:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_MASK         0x000003e0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_SHIFT        5
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_DEFAULT      0x00000002
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SIZE [04:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_MASK              0x0000001f
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_SHIFT             0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_DEFAULT           0x00000004
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL2 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved0 [31:08] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_MASK             0xffffff00
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_SHIFT            8
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_BYTE [07:06] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_MASK     0x000000c0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_SHIFT    6
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved1 [05:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_MASK             0x00000020
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_SHIFT            5
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_HW [04:04] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_MASK       0x00000010
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_SHIFT      4
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_DEFAULT    0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_WR [03:02] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_MASK      0x0000000c
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_SHIFT     2
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_DEFAULT   0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_RD [01:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_MASK      0x00000003
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_SHIFT     0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_DEFAULT   0x00000000
+
+/***************************************************************************
+ *TP_OUT_SEL - SDIO TP_OUT Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TP_OUT_SEL :: reserved0 [31:01] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_MASK                  0xfffffffe
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_SHIFT                 1
+
+/* SDIO_0_CFG :: TP_OUT_SEL :: TP_OUT_SELECT [00:00] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_MASK              0x00000001
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_SHIFT             0
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *CAP_REG0 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG0 :: DDR50_SUPPORT [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_SHIFT               31
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_DEFAULT             0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SD104_SUPPORT [30:30] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_MASK                0x40000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_SHIFT               30
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDR50 [29:29] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_MASK                        0x20000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_SHIFT                       29
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_DEFAULT                     0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SLOT_TYPE [28:27] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_MASK                    0x18000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_SHIFT                   27
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_DEFAULT                 0x00000002
+
+/* SDIO_0_CFG :: CAP_REG0 :: ASYNCH_INT_SUPPORT [26:26] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_MASK           0x04000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_SHIFT          26
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_DEFAULT        0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 64B_SYS_BUS_SUPPORT [25:25] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_MASK          0x02000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_SHIFT         25
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 1_8V_SUPPORT [24:24] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_MASK                 0x01000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_SHIFT                24
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_DEFAULT              0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_0V_SUPPORT [23:23] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_MASK                 0x00800000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_SHIFT                23
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_3V_SUPPORT [22:22] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_MASK                 0x00400000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_SHIFT                22
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_DEFAULT              0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SUSP_RES_SUPPORT [21:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_MASK             0x00200000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_SHIFT            21
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDMA_SUPPORT [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_MASK                 0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_SHIFT                20
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_DEFAULT              0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: HIGH_SPEED_SUPPORT [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_MASK           0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_SHIFT          19
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_DEFAULT        0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: ADMA2_SUPPORT [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_MASK                0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_SHIFT               18
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_DEFAULT             0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: EXTENDED_MEDIA_SUPPORT [17:17] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_MASK       0x00020000
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_SHIFT      17
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: MAX_BL [16:15] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_MASK                       0x00018000
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_SHIFT                      15
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_DEFAULT                    0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: BASE_FREQ [14:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_MASK                    0x00007f80
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_SHIFT                   7
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_DEFAULT                 0x00000064
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_CLK_UNIT [06:06] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_MASK             0x00000040
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_SHIFT            6
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_FREQ [05:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_MASK                 0x0000003f
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_SHIFT                0
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_DEFAULT              0x00000032
+
+/***************************************************************************
+ *CAP_REG1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_REG_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_MASK             0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_SHIFT            31
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved0 [30:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_MASK                    0x7fe00000
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_SHIFT                   21
+
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_1_stuff [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_MASK                  0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_SHIFT                 20
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_BLK_MODE [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_MASK                 0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_SHIFT                19
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_MODE [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_MASK                     0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_SHIFT                    18
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_DEFAULT                  0x00000001
+
+/* SDIO_0_CFG :: CAP_REG1 :: CLK_MULT [17:10] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_MASK                     0x0003fc00
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_SHIFT                    10
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_MODES [09:08] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_MASK               0x00000300
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_SHIFT              8
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_DEFAULT            0x00000002
+
+/* SDIO_0_CFG :: CAP_REG1 :: USE_TUNING [07:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_MASK                   0x00000080
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_SHIFT                  7
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_DEFAULT                0x00000001
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_TIMER [06:03] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_MASK               0x00000078
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_SHIFT              3
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_DEFAULT            0x0000000a
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_D_SUPPORT [02:02] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_MASK             0x00000004
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_SHIFT            2
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_C_SUPPORT [01:01] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_MASK             0x00000002
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_SHIFT            1
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_A_SUPPORT [00:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_MASK             0x00000001
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_SHIFT            0
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PRESET1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET1 :: PRESET1_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET100 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_MASK                     0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_SHIFT                    16
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET50 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_MASK                      0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_SHIFT                     0
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_DEFAULT                   0x00000001
+
+/***************************************************************************
+ *PRESET2 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET2 :: PRESET2_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET2 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET25 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_MASK                      0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_SHIFT                     16
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_DEFAULT                   0x00000002
+
+/* SDIO_0_CFG :: PRESET2 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET12P5 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_MASK                    0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_SHIFT                   0
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_DEFAULT                 0x00000003
+
+/***************************************************************************
+ *SD_CLOCK_DELAY - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_SEL [31:31] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_MASK        0x80000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_SHIFT       31
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_DEFAULT     0x00000001
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY_OVERRIDE [30:30] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_MASK 0x40000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_SHIFT 30
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_DEFAULT 0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved0 [29:12] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_MASK              0x3ffff000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_SHIFT             12
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: OUTPUT_CLOCK_DELAY [11:08] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_MASK     0x00000f00
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_SHIFT    8
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INTERNAL_CLOCK_DELAY [07:04] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_MASK   0x000000f0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_SHIFT  4
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_DEFAULT 0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_MASK      0x0000000f
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_SHIFT     0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_DEFAULT   0x00000000
+
+/***************************************************************************
+ *SD_PAD_DRV - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_PAD_DRV :: OVERRIDE_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_SHIFT               31
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved0 [30:23] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_MASK                  0x7f800000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_SHIFT                 23
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CLK_VAL [22:20] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_MASK                    0x00700000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_SHIFT                   20
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved1 [19:19] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_MASK                  0x00080000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_SHIFT                 19
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CMD_VAL [18:16] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_MASK                    0x00070000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_SHIFT                   16
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved2 [15:15] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_MASK                  0x00008000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_SHIFT                 15
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT3_VAL [14:12] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_MASK                   0x00007000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_SHIFT                  12
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved3 [11:11] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_MASK                  0x00000800
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_SHIFT                 11
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT2_VAL [10:08] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_MASK                   0x00000700
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_SHIFT                  8
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved4 [07:07] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_MASK                  0x00000080
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_SHIFT                 7
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT1_VAL [06:04] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_MASK                   0x00000070
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_SHIFT                  4
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved5 [03:03] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_MASK                  0x00000008
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_SHIFT                 3
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT0_VAL [02:00] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_MASK                   0x00000007
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_SHIFT                  0
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_DEFAULT                0x00000005
+
+/***************************************************************************
+ *IP_DLY - SDIO Host input delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_DEFAULT                   0x00000000
+
+/* SDIO_0_CFG :: IP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: IP_DLY :: IP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_DEFAULT               0x00000003
+
+/* SDIO_0_CFG :: IP_DLY :: reserved1 [15:06] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_MASK                      0x0000ffc0
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_SHIFT                     6
+
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_DELAY [05:00] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_MASK                   0x0000003f
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_DEFAULT                0x00000000
+
+/***************************************************************************
+ *OP_DLY - SDIO Host output delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_DEFAULT                   0x00000000
+
+/* SDIO_0_CFG :: OP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: OP_DLY :: OP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_DEFAULT               0x00000003
+
+/* SDIO_0_CFG :: OP_DLY :: reserved1 [15:04] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_MASK                      0x0000fff0
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_SHIFT                     4
+
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_MASK                   0x0000000f
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TUNING - SDIO Host tuning configuration register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TUNING :: reserved0 [31:04] */
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_MASK                      0xfffffff0
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_SHIFT                     4
+
+/* SDIO_0_CFG :: TUNING :: TUNING_CMD_SUCCESS_CNT [03:00] */
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_MASK         0x0000000f
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_SHIFT        0
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_DEFAULT      0x00000008
+
+/***************************************************************************
+ *VOLT_CTRL - SDIO Host 1p8V control logic select register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VOLT_CTRL :: reserved0 [31:05] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_MASK                   0xffffffe0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_SHIFT                  5
+
+/* SDIO_0_CFG :: VOLT_CTRL :: POW_INV_EN [04:04] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_MASK                  0x00000010
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_SHIFT                 4
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_VAL [03:03] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_MASK                    0x00000008
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_SHIFT                   3
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_DEFAULT                 0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_INV_EN [02:02] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_MASK                 0x00000004
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_SHIFT                2
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_CTRL_SEL [01:00] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_MASK               0x00000003
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_SHIFT              0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SCRATCH - SDIO Scratch Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SCRATCH :: SCRATCH_BITS [31:00] */
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_MASK                  0xffffffff
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_SHIFT                 0
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_DEFAULT               0x00000000
+
+/***************************************************************************
+ *VERSION - SDIO VERSION Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VERSION :: SD_VER [31:24] */
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_MASK                        0xff000000
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_SHIFT                       24
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_DEFAULT                     0x00000030
+
+/* SDIO_0_CFG :: VERSION :: MMC_VER [23:16] */
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_MASK                       0x00ff0000
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_SHIFT                      16
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_DEFAULT                    0x00000044
+
+/* SDIO_0_CFG :: VERSION :: REV [15:08] */
+#define BCHP_SDIO_0_CFG_VERSION_REV_MASK                           0x0000ff00
+#define BCHP_SDIO_0_CFG_VERSION_REV_SHIFT                          8
+#define BCHP_SDIO_0_CFG_VERSION_REV_DEFAULT                        0x000000a7
+
+/* SDIO_0_CFG :: VERSION :: A2S_VER [07:00] */
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_MASK                       0x000000ff
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_SHIFT                      0
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_DEFAULT                    0x00000001
+
+#endif /* #ifndef BCHP_SDIO_0_CFG_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/7425b0/bchp_sun_top_ctrl.h
new file mode 100644
index 0000000..bde9023
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_sun_top_ctrl.h
@@ -0,0 +1,7395 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:44 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SUN_TOP_CTRL_H__
+#define BCHP_SUN_TOP_CTRL_H__
+
+/***************************************************************************
+ *SUN_TOP_CTRL - Top Control registers
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID         0x00404000 /* Chip family ID */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID             0x00404004 /* Product Revision ID */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x0040401c /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x00404020 /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x00404024 /* Bond option value register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x00404028 /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x0040402c /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x00404030 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x00404034 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x00404038 /* Semaphore channel 0 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x0040403c /* Semaphore channel 1 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x00404040 /* Semaphore channel 2 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x00404044 /* Semaphore channel 3 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x00404048 /* Semaphore channel 4 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x0040404c /* Semaphore channel 5 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x00404050 /* Semaphore channel 6 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x00404054 /* Semaphore channel 7 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x00404058 /* Semaphore channel 8 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x0040405c /* Semaphore channel 9 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x00404060 /* Semaphore channel 10 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x00404064 /* Semaphore channel 11 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x00404068 /* Semaphore channel 12 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x0040406c /* Semaphore channel 13 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x00404070 /* Semaphore channel 14 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x00404074 /* Semaphore channel 15 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x00404078 /* General watchdog timer 0 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x0040407c /* General watchdog timer 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x00404080 /* General control register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x00404084 /* General control register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x00404088 /* General control register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x0040408c /* General control register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x00404090 /* General control register 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x00404094 /* General control register 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x00404098 /* General status register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x0040409c /* General status register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x004040a0 /* General status register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x00404100 /* Pinmux control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x00404104 /* Pinmux control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x00404108 /* Pinmux control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x0040410c /* Pinmux control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x00404110 /* Pinmux control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x00404114 /* Pinmux control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x00404118 /* Pinmux control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x0040411c /* Pinmux control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x00404120 /* Pinmux control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x00404124 /* Pinmux control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10        0x00404128 /* Pinmux control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11        0x0040412c /* Pinmux control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12        0x00404130 /* Pinmux control register 12 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13        0x00404134 /* Pinmux control register 13 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14        0x00404138 /* Pinmux control register 14 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15        0x0040413c /* Pinmux control register 15 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16        0x00404140 /* Pinmux control register 16 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17        0x00404144 /* Pinmux control register 17 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18        0x00404148 /* Pinmux control register 18 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19        0x0040414c /* Pinmux control register 19 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x00404150 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x00404154 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x00404158 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x0040415c /* Pad pull-up/pull-down control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x00404160 /* Pad pull-up/pull-down control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5     0x00404164 /* Pad pull-up/pull-down control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6     0x00404168 /* Pad pull-up/pull-down control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7     0x0040416c /* Pad pull-up/pull-down control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8     0x00404170 /* Pad pull-up/pull-down control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9     0x00404174 /* Pad pull-up/pull-down control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10    0x00404178 /* Pad pull-up/pull-down control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11    0x0040417c /* Pad pull-up/pull-down control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12    0x00404180 /* Pad pull-up/pull-down control register 12 */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x00404184 /* Bypass clock unselect register 0 */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x00404300 /* Reset control */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE    0x00404304 /* Reset source enable */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET        0x00404308 /* Software master reset */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION     0x0040430c /* Hardware reset extension */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR          0x00404310 /* Reset Monitor */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x00404314 /* Reset history */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET          0x00404318 /* Software init 0 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR        0x0040431c /* Software init 0 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS       0x00404320 /* Software init 0 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR  0x00404324 /* Security software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET          0x00404330 /* Software init 1 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR        0x00404334 /* Software init 1 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS       0x00404338 /* Software init 1 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR  0x0040433c /* Security software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x00404364 /* Scratch register */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x00404368 /* Spare control bits reserved for future use */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x00404380 /* Test port control */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x00404384 /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x00404388 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x0040438c /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x00404390 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x00404394 /* EJTAG input bus enables */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x00404398 /* EJTAG output select */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL        0x0040439c /* UART Router select */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL             0x004043a0 /* VTRAP Control */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS           0x004043a4 /* VTRAP Status */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x00404400 /* Serial Slave Port configuration register */
+#define BCHP_SUN_TOP_CTRL_SERS_REV               0x00404420 /* SERS Revision Register */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x00404424 /* SERS Configuration Register */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x00404514 /* Block select for RO testmode */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION     0x00404518 /* Test configuration */
+
+/***************************************************************************
+ *CHIP_FAMILY_ID - Chip family ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT    0x74250010
+
+/***************************************************************************
+ *PRODUCT_ID - Product Revision ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK               0xffffffff
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT            0x74250010
+
+/***************************************************************************
+ *BSP_FEATURE_TABLE_ADDR - BSP feature table address
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_VALUE_0 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:13] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xffffe000
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            13
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd [12:09] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_MASK            0x00001e00
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_SHIFT           9
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_ebi_pad_config [08:07] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_pad_config_MASK  0x00000180
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_pad_config_SHIFT 7
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_reset_outb_def_val [06:06] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_SHIFT 6
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rc_ep [05:05] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rc_ep_MASK           0x00000020
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rc_ep_SHIFT          5
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [04:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK      0x0000001e
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT   0x0000000a
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 0
+
+/***************************************************************************
+ *STRAP_VALUE_1 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xffffffe0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            5
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias [04:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_MASK      0x0000001e
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_SHIFT     1
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK     0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT    0
+
+/***************************************************************************
+ *BOND_STATUS - Bond option value register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1
+
+/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_0 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb2_disable [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb2_disable_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb2_disable_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb2_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb1_disable [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb1_disable_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb1_disable_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb1_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_temp_sensor_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avc_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_svc_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vice_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vice_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vice_disable_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vice_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_capsense_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_capsense_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_capsense_disable_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_capsense_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_moca_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_pcie_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie_disable_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_uhf_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_uhf_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_uhf_disable_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_uhf_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sata_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ephy_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_moca2_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca2_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca2_disable_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca2_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_chip_variant [14:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_chip_variant_MASK 0x00007800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_chip_variant_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_chip_variant_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [07:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x000000c0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 0x00000003
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [04:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000001e
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_pcie_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_pcie_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_pcie_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_pcie_enable_DEFAULT 0x00000001
+
+/***************************************************************************
+ *OTP_OPTION_TEST_1 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_28 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_27 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_26 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_25 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_24 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_23 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_22 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_21 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_20 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_19 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_18 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_17 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_16 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_15 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_14 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_0 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_pwm_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pwm_disable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pwm_disable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pwm_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb3_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_0 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb2_disable [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb2_disable_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb2_disable_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb1_disable [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb1_disable_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb1_disable_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_temp_sensor_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_temp_sensor_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_temp_sensor_disable_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avc_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avc_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avc_disable_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_svc_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_svc_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_svc_disable_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vice_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vice_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vice_disable_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_capsense_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_capsense_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_capsense_disable_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_moca_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_pcie_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pcie_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pcie_disable_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_uhf_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_uhf_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_uhf_disable_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sata_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ephy_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_moca2_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca2_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca2_disable_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_chip_variant [14:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_chip_variant_MASK 0x00007800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_chip_variant_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [07:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 6
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [04:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000001e
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_pcie_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_pcie_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_pcie_enable_SHIFT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_1 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_28 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_27 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_26 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_25 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_24 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_23 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_22 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_21 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_20 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_19 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_18 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_17 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_16 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_15 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_14 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 6
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_0 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_SHIFT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_pwm_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pwm_disable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pwm_disable_SHIFT 2
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb3_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb3_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb3_disable_SHIFT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_SHIFT 0
+
+/***************************************************************************
+ *SEMAPHORE_0 - Semaphore channel 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_1 - Semaphore channel 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_2 - Semaphore channel 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_3 - Semaphore channel 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_4 - Semaphore channel 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_5 - Semaphore channel 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_6 - Semaphore channel 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_7 - Semaphore channel 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_8 - Semaphore channel 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_9 - Semaphore channel 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_10 - Semaphore channel 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_11 - Semaphore channel 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_12 - Semaphore channel 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_13 - Semaphore channel 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_14 - Semaphore channel 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_15 - Semaphore channel 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_0 - General watchdog timer 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_1 - General watchdog timer 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK     0x80000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT    31
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK     0x40000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT    30
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK     0x20000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT    29
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK     0x10000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT    28
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK     0x02000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT    25
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK     0x01000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT    24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK     0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT    23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK     0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT    22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK     0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT    21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK     0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT    20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK     0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT    19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK     0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT    18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK     0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT    17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK     0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT    16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb1_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_mode_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_mode_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_mode_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb0_mode [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_DEFAULT         0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_1 - General control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0xffff0000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           16
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_2 - General control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_3 - General control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_4 - General control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_5 - General control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK          0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT         8
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_1 - General status register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_2 - General status register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xffff0000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   16
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: ebi_4_pad_slew [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_4_pad_slew_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_4_pad_slew_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_4_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: ebi_3_pad_slew [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_3_pad_slew_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_3_pad_slew_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_3_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: ebi_2_pad_slew [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_2_pad_slew_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_2_pad_slew_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_2_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: ebi_1_pad_slew [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_1_pad_slew_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_1_pad_slew_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_1_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: ebi_0_pad_slew [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_0_pad_slew_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_0_pad_slew_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_0_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: emmc_pad_slew [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_emmc_pad_slew_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_emmc_pad_slew_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_emmc_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: bspi_pad_slew [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_bspi_pad_slew_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_bspi_pad_slew_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_bspi_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_1_pad_slew [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_slew_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_slew_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_1_pad_sel [07:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_GMII_CMOS_3P3V 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_RGMII_CMOS_2P5V 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_HSTL_CLASS1_1P5V 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_HSTL_CLASS1_1P8V 3
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_slew [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_slew_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_slew_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_sel [04:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_MASK 0x00000018
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_GMII_CMOS_3P3V 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_RGMII_CMOS_2P5V 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_HSTL_CLASS1_1P5V 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_HSTL_CLASS1_1P8V 3
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_slew [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_slew_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_slew_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_sel [01:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_GMII_CMOS_3P3V 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_RGMII_CMOS_2P5V 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_HSTL_CLASS1_1P5V 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_HSTL_CLASS1_1P8V 3
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK    0xf0000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT   28
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_057 [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_056 [26:26] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_055 [25:25] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_054 [24:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_053 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_052 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_051 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_050 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_049 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_048 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_047 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_046 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_045 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_044 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_043 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_042 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_041 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_040 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_039 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_038 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_037 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_036 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_035 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_034 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_033 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_032 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_031 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_031_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_031_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_031_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_030 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_030_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_030_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_030_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xffffff80
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_hys_en [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_oeb [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_do [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_src [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_16MA 7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_07 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_MASK          0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_SHIFT         28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_EBI_DATA_07   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_ALT_TP_IN_07  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_06 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_MASK          0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_EBI_DATA_06   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_ALT_TP_IN_06  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_05 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_MASK          0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_SHIFT         20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_EBI_DATA_05   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_ALT_TP_IN_05  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_04 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_MASK          0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_SHIFT         16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_EBI_DATA_04   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_ALT_TP_IN_04  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_03 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_MASK          0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_EBI_DATA_03   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_ALT_TP_IN_03  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_02 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_MASK          0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_EBI_DATA_02   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_ALT_TP_IN_02  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_01 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_MASK          0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_SHIFT         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_EBI_DATA_01   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_ALT_TP_IN_01  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_00 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_MASK          0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_EBI_DATA_00   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_ALT_TP_IN_00  1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_15 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_15_MASK          0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_15_SHIFT         28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_15_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_15_EBI_DATA_15   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_15_ALT_TP_IN_15  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_14 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_14_MASK          0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_14_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_14_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_14_EBI_DATA_14   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_14_ALT_TP_IN_14  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_13 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_13_MASK          0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_13_SHIFT         20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_13_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_13_EBI_DATA_13   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_13_ALT_TP_IN_13  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_12 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_12_MASK          0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_12_SHIFT         16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_12_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_12_EBI_DATA_12   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_12_ALT_TP_IN_12  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_11 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_11_MASK          0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_11_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_11_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_11_EBI_DATA_11   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_11_ALT_TP_IN_11  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_10 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_10_MASK          0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_10_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_10_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_10_EBI_DATA_10   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_10_ALT_TP_IN_10  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_09 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_09_MASK          0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_09_SHIFT         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_09_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_09_EBI_DATA_09   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_09_ALT_TP_IN_09  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_08 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_08_MASK          0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_08_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_08_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_08_EBI_DATA_08   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_08_ALT_TP_IN_08  1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_07 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_07_MASK          0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_07_SHIFT         28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_07_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_07_EBI_ADDR_07   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_07_ALT_TP_OUT_07 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_06 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_06_MASK          0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_06_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_06_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_06_EBI_ADDR_06   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_06_ALT_TP_OUT_06 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_05 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_05_MASK          0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_05_SHIFT         20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_05_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_05_EBI_ADDR_05   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_05_ALT_TP_OUT_05 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_04 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_04_MASK          0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_04_SHIFT         16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_04_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_04_EBI_ADDR_04   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_04_ALT_TP_OUT_04 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_03 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_03_MASK          0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_03_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_03_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_03_EBI_ADDR_03   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_03_ALT_TP_OUT_03 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_02 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_02_MASK          0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_02_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_02_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_02_EBI_ADDR_02   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_02_ALT_TP_OUT_02 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_01 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_01_MASK          0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_01_SHIFT         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_01_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_01_EBI_ADDR_01   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_01_ALT_TP_OUT_01 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_00 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_00_MASK          0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_00_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_00_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_00_EBI_ADDR_00   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_00_ALT_TP_OUT_00 1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_23 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_23_MASK          0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_23_SHIFT         28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_23_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_23_EBI_ADDR_23   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_23_ALT_TP_OUT_23 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_22 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_22_MASK          0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_22_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_22_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_22_EBI_ADDR_22   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_22_ALT_TP_OUT_22 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_21 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_21_MASK          0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_21_SHIFT         20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_21_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_21_EBI_ADDR_21   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_21_ALT_TP_OUT_21 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_20 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_20_MASK          0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_20_SHIFT         16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_20_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_20_EBI_ADDR_20   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_20_ALT_TP_OUT_20 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_19 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_19_MASK          0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_19_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_19_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_19_EBI_ADDR_19   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_19_ALT_TP_OUT_19 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_18 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_18_MASK          0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_18_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_18_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_18_EBI_ADDR_18   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_18_ALT_TP_OUT_18 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_17 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_17_MASK          0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_17_SHIFT         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_17_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_17_EBI_ADDR_17   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_17_ALT_TP_OUT_17 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_16 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_16_MASK          0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_16_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_16_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_16_EBI_ADDR_16   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_16_ALT_TP_OUT_16 1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_4 - Pinmux control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_cs3b [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs3b_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs3b_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs3b_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs3b_EBI_CS3B         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs3b_ALT_TP_OUT_31    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_cs2b [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs2b_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs2b_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs2b_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs2b_EBI_CS2B         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs2b_ALT_TP_OUT_30    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_cs1b [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs1b_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs1b_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs1b_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs1b_EBI_CS1B         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs1b_ALT_TP_OUT_29    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_cs0b [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs0b_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs0b_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs0b_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs0b_EBI_CS0B         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs0b_ALT_TP_OUT_28    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr_27 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_27_MASK          0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_27_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_27_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_27_EBI_ADDR_27   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_27_ALT_TP_OUT_27 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr_26 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_26_MASK          0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_26_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_26_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_26_EBI_ADDR_26   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_26_ALT_TP_OUT_26 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr_25 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_25_MASK          0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_25_SHIFT         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_25_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_25_EBI_ADDR_25   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_25_ALT_TP_OUT_25 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr_24 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_24_MASK          0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_24_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_24_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_24_EBI_ADDR_24   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_24_ALT_TP_OUT_24 1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_5 - Pinmux control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_003 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_003_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_003_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_003_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_003_GPIO_003         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_003_EMAC0_RX_EN_CTL  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_003_UART_TXD_0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_003_PKT_DATA0        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_003_TP_OUT_15        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_003_PM_GPIO_003      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_002 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_002_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_002_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_002_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_002_GPIO_002         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_002_EMAC0_RX_CLK     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_002_UART_RXD_0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_002_PKT_CLK0         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_002_IR_IN1           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_002_TP_IN_05         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_002_PM_GPIO_002      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_001 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_001_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_001_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_001_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_001_GPIO_001         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_001_ENET_LINK        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_001_ENET_ACTIVITY    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_001_MII0_TX_ERR      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_001_TP_OUT_13        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_001_PM_GPIO_001      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_000 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_000_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_000_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_000_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_000_GPIO_000         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_000_ENET_ACTIVITY    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_000_ENET_LINK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_000_MII0_RX_ERR      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_000_TEST_THP         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_000_TP_OUT_12        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_000_PM_GPIO_000      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: sdio1_clk [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_sdio1_clk_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_sdio1_clk_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_sdio1_clk_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_sdio1_clk_SDIO1_CLK       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_sdio1_clk_PM_SDIO1_CLK    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: sdio1_cmd [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_sdio1_cmd_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_sdio1_cmd_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_sdio1_cmd_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_sdio1_cmd_SDIO1_CMD       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_sdio1_cmd_PM_SDIO1_CMD    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_waitb [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_waitb_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_waitb_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_waitb_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_waitb_EBI_WAITB       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_waitb_PM_EBI_WAITB    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_nand_rbb [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_nand_rbb_MASK         0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_nand_rbb_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_nand_rbb_DEFAULT      0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_nand_rbb_EBI_NAND_RBB 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_nand_rbb_PM_EBI_NAND_RBB 1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_6 - Pinmux control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_011 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_011_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_011_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_011_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_011_GPIO_011         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_011_EMAC0_TXD_01     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_011_UART_TXD_2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_011_PKT_VALID1       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_011_TTX0_DATA        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_011_TP_OUT_23        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_011_PM_GPIO_011      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_010 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_010_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_010_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_010_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_010_GPIO_010         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_010_EMAC0_TXD_00     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_010_UART_RXD_2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_010_PKT_ERROR1       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_010_TTX0_REQ         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_010_TP_IN_22         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_010_PM_GPIO_010      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_009 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_009_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_009_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_009_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_009_GPIO_009         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_009_EMAC0_TX_EN_CTL  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_009_UART_RTS_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_009_PKT_SYNC1        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_009_VEC_VSYNC_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_009_TP_OUT_21        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_009_PM_GPIO_009      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_008 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_008_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_008_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_008_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_008_GPIO_008         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_008_EMAC0_TX_CLK     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_008_UART_CTS_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_008_PKT_DATA1        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_008_VEC_VSYNC_0      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_008_TP_IN_20         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_008_PM_GPIO_008      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_007 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_007_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_007_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_007_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_007_GPIO_007         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_007_EMAC0_RXD_03     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_007_UART_TXD_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_007_PKT_CLK1         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_007_EXT_IRQB_4       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_007_TP_OUT_19        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_007_PM_GPIO_007      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_006 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_006_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_006_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_006_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_006_GPIO_006         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_006_EMAC0_RXD_02     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_006_UART_RXD_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_006_PKT_VALID0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_006_EXT_IRQB_3       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_006_TP_IN_18         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_006_PM_GPIO_006      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_005 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_005_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_005_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_005_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_005_GPIO_005         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_005_EMAC0_RXD_01     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_005_UART_RTS_0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_005_PKT_ERROR0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_005_VEC_HSYNC_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_005_TP_OUT_17        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_005_PM_GPIO_005      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_004 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_004_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_004_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_004_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_004_GPIO_004         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_004_EMAC0_RXD_00     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_004_UART_CTS_0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_004_PKT_SYNC0        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_004_VEC_HSYNC_0      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_004_TP_OUT_16        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_004_PM_GPIO_004      6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_7 - Pinmux control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_019 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_019_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_019_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_019_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_019_GPIO_019         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_019_PKT_ERROR0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_019_MTSIF0_DATA1     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_019_EMAC1_RXD_01     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_019_UART_RXD_0       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_019_PPKT_DATA1       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_019_PM_GPIO_019      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_018 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_018_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_018_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_018_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_018_GPIO_018         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_018_PKT_SYNC0        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_018_MTSIF0_SYNC      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_018_EMAC1_RXD_00     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_018_UART_RTS_0       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_018_PPKT_SYNC        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_018_TP_OUT_30        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_018_PM_GPIO_018      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_017 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_017_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_017_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_017_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_017_GPIO_017         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_017_PKT_DATA0        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_017_MTSIF0_DATA0     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_017_EMAC1_RX_EN_CTL  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_017_UART_CTS_0       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_017_PPKT_DATA0       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_017_TP_OUT_29        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_017_PM_GPIO_017      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_016 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_016_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_016_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_016_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_016_GPIO_016         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_016_PKT_CLK0         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_016_MTSIF0_CLK       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_016_EMAC1_RX_CLK     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_016_EXT_IRQB_0       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_016_PPKT_CLK         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_016_TP_OUT_28        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_016_PM_GPIO_016      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_015 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_015_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_015_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_015_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_015_GPIO_015         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_015_PKT_VALID5       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_015_EMAC0_MDC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_015_TTX0_DATA        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_015_PM_GPIO_015      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_014 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_014_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_014_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_014_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_014_GPIO_014         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_014_PKT_ERROR5       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_014_EMAC0_MDIO       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_014_TTX0_REQ         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_014_TP_OUT_26        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_014_PM_GPIO_014      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_013 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_013_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_013_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_013_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_013_GPIO_013         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_013_EMAC0_TXD_03     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_013_UART_RTS_2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_013_PKT_VALID2       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_013_TTX1_DATA        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_013_TP_OUT_25        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_013_PM_GPIO_013      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_012 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_012_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_012_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_012_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_012_GPIO_012         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_012_EMAC0_TXD_02     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_012_UART_CTS_2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_012_PKT_ERROR2       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_012_TTX1_REQ         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_012_TP_OUT_24        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_012_PM_GPIO_012      6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_8 - Pinmux control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_027 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_027_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_027_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_027_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_027_GPIO_027         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_027_PKT_VALID2       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_027_MTSIF0_DATA7     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_027_EMAC1_TXD_03     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_027_PPKT_DATA7       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_027_TP_IN_07         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_027_PM_GPIO_027      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_026 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_026_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_026_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_026_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_026_GPIO_026         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_026_PKT_ERROR2       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_026_MTSIF0_DATA6     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_026_EMAC1_TXD_02     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_026_PPKT_DATA6       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_026_TP_IN_06         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_026_PM_GPIO_026      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_025 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_025_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_025_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_025_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_025_GPIO_025         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_025_PKT_VALID1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_025_MTSIF_ATS_RST    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_025_EMAC1_TXD_01     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_025_UART_TXD_1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_025_TP_OUT_14        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_025_PM_GPIO_025      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_024 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_024_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_024_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_024_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_024_GPIO_024         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_024_PKT_ERROR1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_024_MTSIF0_DATA5     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_024_EMAC1_TXD_00     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_024_UART_RXD_1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_024_PPKT_DATA5       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_024_PM_GPIO_024      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_023 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_023_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_023_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_023_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_023_GPIO_023         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_023_PKT_SYNC1        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_023_MTSIF0_DATA4     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_023_EMAC1_TX_EN_CTL  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_023_UART_RTS_1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_023_PPKT_DATA4       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_023_PM_GPIO_023      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_022 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_022_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_022_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_022_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_022_GPIO_022         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_022_PKT_DATA1        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_022_MTSIF0_DATA3     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_022_EMAC1_TX_CLK     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_022_UART_CTS_1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_022_PPKT_DATA3       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_022_TP_IN_02         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_022_PM_GPIO_022      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_021 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_021_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_021_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_021_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_021_GPIO_021         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_021_PKT_CLK1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_021_MTSIF0_DATA2     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_021_EMAC1_RXD_03     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_021_EXT_IRQB_1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_021_PPKT_DATA2       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_021_TP_IN_01         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_021_PM_GPIO_021      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_020 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_020_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_020_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_020_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_020_GPIO_020         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_020_PKT_VALID0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_020_MTSIF0_VALID     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_020_EMAC1_RXD_02     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_020_UART_TXD_0       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_020_PPKT_VALID       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_020_PM_GPIO_020      6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_9 - Pinmux control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_035 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_035_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_035_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_035_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_035_GPIO_035         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_035_CHIP2POD_SCTL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_035_SPI_M_SS0B       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_035_EBI_ADDR_02      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_035_VEC_VSYNC_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_035_TP_IN_15         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_035_PM_GPIO_035      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_034 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_034_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_034_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_034_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_034_GPIO_034         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_034_CHIP2POD_SDO     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_034_SPI_M_MISO       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_034_EBI_ADDR_00      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_034_SC0_VPP          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_034_SC1_VPP          5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_034_TP_IN_14         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_034_PM_GPIO_034      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_033 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_GPIO_033         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_POD2CHIP_SDI     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_SPI_M_MOSI       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_LED_LD_11        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_SC0_AUX2         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_SC1_AUX2         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_VEC_VSYNC_0      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_TP_IN_13         7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_PM_GPIO_033      8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_032 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_032_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_032_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_032_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_032_GPIO_032         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_032_CHIP2POD_SCLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_032_SPI_M_SCK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_032_EBI_ADDR_01      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_032_SC0_AUX1         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_032_SC1_AUX1         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_032_VEC_VSYNC_0      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_032_PM_GPIO_032      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_031 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_031_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_031_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_031_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_031_GPIO_031         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_031_CHIP2POD_MCLKO   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_031_RMXP_CLK         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_031_EBI_ADDR_15      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_031_SPI_S_MISO       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_031_PM_GPIO_031      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_030 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_030_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_030_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_030_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_030_GPIO_030         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_030_POD2CHIP_MCLKI   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_030_PPKT_CLK         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_030_EBI_ADDR_14      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_030_SPI_S_SS0B       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_030_PM_GPIO_030      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_029 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_029_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_029_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_029_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_029_GPIO_029         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_029_PKT_SYNC3        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_029_EMAC1_MDC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_029_TP_IN_09         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_029_PM_GPIO_029      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_028 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_028_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_028_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_028_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_028_GPIO_028         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_028_PKT_DATA3        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_028_EMAC1_MDIO       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_028_TP_IN_08         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_028_PM_GPIO_028      4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_10 - Pinmux control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_043 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_043_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_043_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_043_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_043_GPIO_043        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_043_POD2CHIP_MDI5   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_043_PPKT_DATA5      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_043_VO1_656_5       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_043_SC0_AUX1        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_043_SC1_AUX1        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_043_TP_IN_23        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_043_PM_GPIO_043     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_042 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_042_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_042_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_042_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_042_GPIO_042        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_042_POD2CHIP_MDI4   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_042_PPKT_DATA4      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_042_VO1_656_4       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_042_UART_TXD_2      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_042_TP_OUT_22       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_042_PM_GPIO_042     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_041 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_041_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_041_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_041_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_041_GPIO_041        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_041_POD2CHIP_MDI3   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_041_PPKT_DATA3      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_041_VO1_656_3       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_041_UART_RXD_2      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_041_TP_IN_21        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_041_PM_GPIO_041     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_040 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_040_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_040_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_040_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_040_GPIO_040        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_040_POD2CHIP_MDI2   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_040_PPKT_DATA2      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_040_VO1_656_2       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_040_UART_TXD_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_040_TP_OUT_20       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_040_PM_GPIO_040     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_039 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_039_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_039_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_039_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_039_GPIO_039        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_039_POD2CHIP_MDI1   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_039_PPKT_DATA1      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_039_VO1_656_1       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_039_UART_RXD_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_039_TP_IN_19        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_039_PM_GPIO_039     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_038 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_038_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_038_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_038_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_038_GPIO_038        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_038_POD2CHIP_MDI0   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_038_PPKT_DATA0      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_038_VO1_656_0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_038_UART_TXD_0      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_038_TP_OUT_18       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_038_PM_GPIO_038     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_037 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_037_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_037_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_037_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_037_GPIO_037        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_037_POD2CHIP_MIVAL  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_037_PPKT_VALID      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_037_VO1_656_CLK     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_037_UART_RXD_0      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_037_TP_IN_17        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_037_PM_GPIO_037     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_036 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_036_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_036_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_036_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_036_GPIO_036        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_036_POD2CHIP_MISTRT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_036_PPKT_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_036_PM_GPIO_036     3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_11 - Pinmux control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_051 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_051_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_051_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_051_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_051_GPIO_051        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_051_CHIP2POD_MDO2   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_051_RMXP_DATA2      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_051_EBI_ADDR_20     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_051_LED_LD_4        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_051_TP_IN_31        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_051_PM_GPIO_051     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_050 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_050_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_050_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_050_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_050_GPIO_050        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_050_CHIP2POD_MDO1   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_050_RMXP_DATA1      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_050_EBI_ADDR_19     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_050_LED_LD_3        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_050_TP_IN_30        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_050_PM_GPIO_050     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_049 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_GPIO_049        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_CHIP2POD_MDO0   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_RMXP_DATA0      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_EBI_ADDR_18     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_LED_LD_2        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_SC0_VPP         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_SC1_VPP         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_TP_IN_29        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_PM_GPIO_049     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_048 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_GPIO_048        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_CHIP2POD_MOSTRT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_RMXP_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_EBI_ADDR_17     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_LED_LD_1        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_SC0_AUX2        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_SC1_AUX2        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_TP_IN_28        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_PM_GPIO_048     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_047 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_GPIO_047        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_CHIP2POD_MOVAL  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_RMXP_VALID      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_EBI_ADDR_16     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_LED_LD_0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_SC0_AUX1        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_SC1_AUX1        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_TP_IN_27        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_PM_GPIO_047     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_046 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_046_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_046_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_046_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_046_GPIO_046        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_046_POD2CHIP_MICLK  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_046_PPKT_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_046_EBI_ADDR_13     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_046_SPI_S_SS0B      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_046_POD2CHIP_MCLKI  5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_046_TP_IN_26        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_046_PM_GPIO_046     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_045 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_045_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_045_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_045_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_045_GPIO_045        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_045_POD2CHIP_MDI7   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_045_PPKT_DATA7      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_045_VO1_656_7       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_045_SC0_VPP         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_045_SC1_VPP         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_045_TP_IN_25        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_045_PM_GPIO_045     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_044 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_044_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_044_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_044_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_044_GPIO_044        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_044_POD2CHIP_MDI6   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_044_PPKT_DATA6      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_044_VO1_656_6       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_044_SC0_AUX2        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_044_SC1_AUX2        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_044_TP_IN_24        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_044_PM_GPIO_044     7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_12 - Pinmux control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_059 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_059_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_059_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_059_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_059_GPIO_059        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_059_PKT_DATA2       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_059_MTSIF1_CLK      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_059_ALT_TP_IN_22    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_059_PM_GPIO_059     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_058 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_058_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_058_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_058_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_058_GPIO_058        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_058_PKT_CLK2        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_058_MTSIF_ATS_INC   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_058_ALT_TP_IN_21    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_058_PM_GPIO_058     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_057 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_GPIO_057        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_CHIP2POD_MOCLK  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_RMXP_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_EBI_ADDR_12     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_LED_LD_10       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_I2S_CLK1        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_SPI_S_MISO      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_CHIP2POD_MCLKO  7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_ALT_TP_IN_20    8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_PM_GPIO_057     9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_056 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_056_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_056_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_056_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_056_GPIO_056        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_056_CHIP2POD_MDO7   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_056_RMXP_DATA7      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_056_EBI_ADDR_25     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_056_LED_LD_9        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_056_I2S_LR1         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_056_ALT_TP_IN_19    6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_056_PM_GPIO_056     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_055 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_055_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_055_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_055_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_055_GPIO_055        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_055_CHIP2POD_MDO6   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_055_RMXP_DATA6      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_055_EBI_ADDR_24     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_055_LED_LD_8        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_055_I2S_DATA1       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_055_ALT_TP_IN_18    6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_055_PM_GPIO_055     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_054 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_054_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_054_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_054_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_054_GPIO_054        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_054_CHIP2POD_MDO5   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_054_RMXP_DATA5      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_054_EBI_ADDR_23     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_054_LED_LD_7        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_054_ALT_TP_IN_17    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_054_PM_GPIO_054     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_053 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_053_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_053_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_053_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_053_GPIO_053        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_053_CHIP2POD_MDO4   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_053_RMXP_DATA4      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_053_EBI_ADDR_22     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_053_LED_LD_6        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_053_ALT_TP_IN_16    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_053_PM_GPIO_053     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_052 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_052_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_052_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_052_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_052_GPIO_052        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_052_CHIP2POD_MDO3   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_052_RMXP_DATA3      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_052_EBI_ADDR_21     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_052_LED_LD_5        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_052_PM_GPIO_052     5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_13 - Pinmux control register 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_067 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_GPIO_067        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_PKT_ERROR4      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_MTSIF_ATS_INC   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_UART_CTS_2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_UART_RXD_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_MII0_CRS        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_TTX1_REQ        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_ALT_TP_IN_29    7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_PM_GPIO_067     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_066 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_066_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_066_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_066_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_066_GPIO_066        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_066_PKT_SYNC4       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_066_MTSIF1_DATA4    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_066_ALT_TP_IN_28    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_066_PM_GPIO_066     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_065 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_065_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_065_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_065_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_065_GPIO_065        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_065_PKT_DATA4       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_065_MTSIF1_DATA3    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_065_PM_GPIO_065     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_064 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_064_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_064_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_064_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_064_GPIO_064        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_064_PKT_CLK4        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_064_MTSIF1_DATA2    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_064_ALT_TP_IN_26    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_064_PM_GPIO_064     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_063 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_063_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_063_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_063_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_063_GPIO_063        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_063_PKT_VALID3      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_063_MTSIF1_VALID    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_063_UART_TXD_2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_063_UART_RTS_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_063_MII1_COL        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_063_TP_OUT_31       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_063_PM_GPIO_063     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_062 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_062_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_062_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_062_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_062_GPIO_062        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_062_PKT_ERROR3      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_062_MTSIF1_DATA1    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_062_UART_RXD_2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_062_UART_CTS_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_062_MII1_CRS        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_062_ALT_TP_IN_25    6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_062_PM_GPIO_062     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_061 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_061_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_061_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_061_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_061_GPIO_061        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_061_PKT_CLK3        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_061_MTSIF1_SYNC     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_061_ALT_TP_IN_24    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_061_PM_GPIO_061     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_060 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_060_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_060_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_060_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_060_GPIO_060        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_060_PKT_SYNC2       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_060_MTSIF1_DATA0    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_060_ALT_TP_IN_23    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_060_PM_GPIO_060     4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_14 - Pinmux control register 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_075 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_075_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_075_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_075_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_075_GPIO_075        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_075_PKT_ERROR6      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_075_SDIO0_CLK       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_075_RMX_PAUSE0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_075_PWM_2           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_075_TP_IN_10        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_075_PM_GPIO_075     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_074 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_074_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_074_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_074_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_074_GPIO_074        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_074_PKT_SYNC6       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_074_SDIO0_PWR0      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_074_SC0_VPP         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_074_SC1_VPP         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_074_PM_GPIO_074     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_073 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_073_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_073_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_073_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_073_GPIO_073        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_073_PKT_DATA6       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_073_SDIO0_WPROT     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_073_SC0_AUX2        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_073_SC1_AUX2        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_073_PM_GPIO_073     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_072 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_072_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_072_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_072_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_072_GPIO_072        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_072_PKT_CLK6        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_072_SDIO0_CMD       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_072_SC0_AUX1        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_072_SC1_AUX1        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_072_ALT_TP_OUT_14   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_072_PM_GPIO_072     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_071 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_071_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_071_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_071_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_071_GPIO_071        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_071_PKT_SYNC5       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_071_MTSIF1_DATA5    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_071_ALT_TP_OUT_13   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_071_PM_GPIO_071     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_070 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_070_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_070_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_070_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_070_GPIO_070        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_070_PKT_DATA5       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_070_MTSIF1_DATA7    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_070_ALT_TP_IN_31    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_070_PM_GPIO_070     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_069 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_069_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_069_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_069_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_069_GPIO_069        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_069_PKT_CLK5        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_069_MTSIF1_DATA6    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_069_ALT_TP_IN_30    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_069_PM_GPIO_069     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_068 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_GPIO_068        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_PKT_VALID4      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_MTSIF_ATS_RST   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_UART_RTS_2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_UART_TXD_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_MII0_COL        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_TTX1_DATA       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_TP_OUT_27       7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_PM_GPIO_068     8
+
+/***************************************************************************
+ *PIN_MUX_CTRL_15 - Pinmux control register 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_083 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_083_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_083_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_083_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_083_GPIO_083        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_083_CODEC_SCLK      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_083_SC1_AUX1        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_083_SC0_AUX1        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_083_LED_LD_9        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_083_SPI_M_SS1B      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_083_TP_IN_16        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_083_PM_GPIO_083     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_082 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_082_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_082_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_082_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_082_GPIO_082        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_082_CODEC_SDI       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_082_SC_EXT_CLK      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_082_EXT_IRQB_5      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_082_LED_LD_8        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_082_SPI_M_SS1B      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_082_PM_GPIO_082     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_081 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_081_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_081_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_081_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_081_GPIO_081        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_081_PKT_VALID7      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_081_SDIO0_LED       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_081_EXT_IRQB_4      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_081_PWM_3           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_081_UART_TXD_0      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_081_ALT_TP_OUT_11   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_081_PM_GPIO_081     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_080 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_080_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_080_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_080_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_080_GPIO_080        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_080_PKT_ERROR7      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_080_SDIO0_PRES      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_080_EXT_IRQB_3      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_080_UART_CTS_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_080_UART_RXD_0      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_080_TP_IN_04        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_080_PM_GPIO_080     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_079 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_079_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_079_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_079_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_079_GPIO_079        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_079_PKT_SYNC7       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_079_SDIO0_DAT3      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_079_EXT_IRQB_2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_079_UART_RTS_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_079_TP_IN_03        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_079_PM_GPIO_079     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_078 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_078_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_078_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_078_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_078_GPIO_078        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_078_PKT_DATA7       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_078_SDIO0_DAT2      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_078_EXT_IRQB_1      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_078_UART_TXD_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_078_PM_GPIO_078     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_077 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_077_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_077_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_077_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_077_GPIO_077        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_077_PKT_CLK7        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_077_SDIO0_DAT1      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_077_EXT_IRQB_0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_077_UART_RXD_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_077_TP_IN_00        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_077_PM_GPIO_077     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_076 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_076_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_076_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_076_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_076_GPIO_076        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_076_PKT_VALID6      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_076_SDIO0_DAT0      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_076_RMX_PAUSE1      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_076_IR_IN1          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_076_TP_IN_11        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_076_PM_GPIO_076     6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_16 - Pinmux control register 16
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_091 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_091_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_091_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_091_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_091_GPIO_091        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_091_SC0_RST         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_091_PM_GPIO_091     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_090 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_090_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_090_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_090_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_090_GPIO_090        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_090_SC0_CLK         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_090_PWM_3           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_090_PM_GPIO_090     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_089 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_089_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_089_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_089_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_089_GPIO_089        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_089_SC0_IO          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_089_PWM_2           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_089_PM_GPIO_089     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_088 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_088_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_088_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_088_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_088_GPIO_088        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_088_MOCA_LINK       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_088_MOCA_ACTIVITY   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_088_MII1_TX_ERR     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_088_TP_IN_12        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_088_PM_GPIO_088     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_087 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_087_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_087_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_087_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_087_GPIO_087        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_087_MOCA_ACTIVITY   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_087_MOCA_LINK       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_087_MII1_RX_ERR     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_087_ALT_TP_OUT_10   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_087_PM_GPIO_087     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_086 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_086_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_086_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_086_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_086_GPIO_086        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_086_CODEC_SDO       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_086_IR_IN1          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_086_ALT_TP_OUT_09   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_086_PM_GPIO_086     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_085 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_085_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_085_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_085_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_085_GPIO_085        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_085_CODEC_MCLK      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_085_SC1_VPP         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_085_SC0_VPP         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_085_SPI_M_SS2B      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_085_ALT_TP_OUT_08   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_085_PM_GPIO_085     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_084 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_084_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_084_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_084_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_084_GPIO_084        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_084_CODEC_FSYNCB    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_084_SC1_AUX2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_084_SC0_AUX2        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_084_LED_LD_10       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_084_ALT_TP_IN_27    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_084_PM_GPIO_084     6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_17 - Pinmux control register 17
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_103 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_103_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_103_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_103_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_103_GPIO_103        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_103_VO0_656_1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_103_VO1_656_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_103_RMX_DATA0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_103_TP_OUT_04       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_103_PM_GPIO_103     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_098 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_098_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_098_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_098_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_098_GPIO_098        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_098_SC1_VCC         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_098_PM_GPIO_098     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_097 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_097_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_097_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_097_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_097_GPIO_097        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_097_SC1_PRES        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_097_PM_GPIO_097     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_096 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_096_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_096_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_096_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_096_GPIO_096        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_096_SC1_RST         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_096_ALT_TP_OUT_15   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_096_PM_GPIO_096     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_095 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_095_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_095_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_095_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_095_GPIO_095        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_095_SC1_CLK         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_095_ALT_TP_OUT_12   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_095_PM_GPIO_095     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_094 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_094_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_094_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_094_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_094_GPIO_094        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_094_SC1_IO          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_094_PM_GPIO_094     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_093 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_093_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_093_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_093_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_093_GPIO_093        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_093_SC0_VCC         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_093_PM_GPIO_093     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_092 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_092_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_092_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_092_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_092_GPIO_092        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_092_SC0_PRES        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_092_PM_GPIO_092     2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_18 - Pinmux control register 18
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: sgpio_00 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_00_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_00_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_00_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_00_SGPIO_00        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_00_BSC_M2_SCL      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_110 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_110_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_110_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_110_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_110_GPIO_110        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_110_VO0_656_CLK     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_110_VO1_656_CLK     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_110_BT_CLK_26087    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_110_LED_LD_15       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_110_TP_OUT_11       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_110_PM_GPIO_110     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_109 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_109_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_109_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_109_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_109_GPIO_109        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_109_VO0_656_7       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_109_VO1_656_7       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_109_PWM_2           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_109_LED_LD_14       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_109_TP_OUT_10       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_109_PM_GPIO_109     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_108 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_108_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_108_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_108_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_108_GPIO_108        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_108_VO0_656_6       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_108_VO1_656_6       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_108_UHF_LNA_PWRDN   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_108_LED_LD_13       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_108_TP_OUT_09       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_108_PM_GPIO_108     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_107 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_107_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_107_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_107_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_107_GPIO_107        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_107_VO0_656_5       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_107_VO1_656_5       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_107_RMX_SYNC1       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_107_TP_OUT_08       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_107_PM_GPIO_107     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_106 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_106_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_106_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_106_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_106_GPIO_106        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_106_VO0_656_4       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_106_VO1_656_4       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_106_RMX_DATA1       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_106_TP_OUT_07       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_106_PM_GPIO_106     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_105 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_105_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_105_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_105_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_105_GPIO_105        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_105_VO0_656_3       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_105_VO1_656_3       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_105_RMX_CLK1        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_105_TP_OUT_06       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_105_PM_GPIO_105     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_104 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_104_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_104_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_104_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_104_GPIO_104        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_104_VO0_656_2       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_104_VO1_656_2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_104_RMX_SYNC0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_104_TP_OUT_05       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_104_PM_GPIO_104     5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_19 - Pinmux control register 19
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_reserved0_MASK           0xfffff000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_reserved0_SHIFT          12
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: sgpio_03 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_03_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_03_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_03_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_03_SGPIO_03        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_03_BSC_M3_SDA      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_03_EMAC0_IRQ       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_03_EMAC1_IRQ       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: sgpio_02 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_02_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_02_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_02_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_02_SGPIO_02        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_02_BSC_M3_SCL      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_02_EMAC0_IRQ       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_02_EMAC1_IRQ       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: sgpio_01 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_01_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_01_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_01_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_01_SGPIO_01        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_01_BSC_M2_SDA      1
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_12_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_12_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_12_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_12_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_12_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_12_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_11_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_11_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_11_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_11_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_11_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_11_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_10_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_10_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_10_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_10_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_10_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_10_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_09_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_09_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_09_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_09_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_09_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_09_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_08_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_08_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_08_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_08_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_08_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_08_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_07_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_06_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_05_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_04_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_03_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_02_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_01_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_00_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_11_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_11_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_11_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_11_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_11_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_11_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_10_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_10_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_10_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_10_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_10_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_10_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_09_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_09_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_09_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_09_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_09_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_09_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_08_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_08_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_08_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_08_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_08_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_08_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_07_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_07_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_07_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_07_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_07_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_07_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_06_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_06_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_06_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_06_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_06_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_06_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_05_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_05_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_05_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_05_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_05_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_05_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_04_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_04_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_04_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_04_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_04_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_04_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_03_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_03_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_03_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_03_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_03_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_03_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_02_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_02_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_02_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_02_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_02_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_02_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_01_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_01_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_01_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_01_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_01_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_01_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_00_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_00_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_00_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_00_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_00_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_00_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_data_15_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_15_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_15_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_15_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_15_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_15_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_data_14_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_14_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_14_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_14_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_14_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_14_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_data_13_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_13_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_13_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_13_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_13_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_13_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_26_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_26_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_26_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_26_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_26_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_26_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_26_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_25_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_25_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_25_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_25_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_25_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_25_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_25_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_24_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_24_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_24_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_24_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_24_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_24_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_24_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_23_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_23_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_23_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_23_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_23_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_23_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_23_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_22_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_22_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_22_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_22_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_22_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_22_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_22_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_21_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_21_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_21_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_21_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_21_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_21_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_21_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_20_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_20_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_20_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_20_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_20_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_20_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_19_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_19_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_19_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_19_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_19_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_19_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_18_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_18_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_18_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_18_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_18_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_18_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_18_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_17_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_17_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_17_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_17_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_17_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_17_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_16_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_16_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_16_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_16_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_16_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_16_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_15_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_15_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_15_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_15_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_15_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_15_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_14_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_14_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_14_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_14_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_14_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_14_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_13_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_13_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_13_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_13_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_13_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_13_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_12_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_12_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_12_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_12_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_12_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_12_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_waitb_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_waitb_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_waitb_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_waitb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_waitb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_waitb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_waitb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_nand_rbb_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_dsb_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_tsb_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_rdb_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_we1b_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_we0b_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_rwb_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_cs5b_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs5b_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs5b_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs5b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs5b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs5b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs5b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_cs4b_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs4b_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs4b_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs4b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs4b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs4b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs4b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_cs3b_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs3b_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs3b_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs3b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs3b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs3b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs3b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_cs2b_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs2b_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs2b_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs2b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs2b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs2b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs2b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_cs1b_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs1b_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs1b_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs1b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs1b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs1b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs1b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_cs0b_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs0b_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs0b_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs0b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs0b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs0b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs0b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_addr_27_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_27_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_27_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_27_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_27_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_27_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_27_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved0 [29:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_MASK        0x3ffc0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_SHIFT       18
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: pcie_clkreqb_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_clkreqb_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_clkreqb_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_clkreqb_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_clkreqb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_clkreqb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_clkreqb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: pcie_rstb_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_rstb_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_rstb_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_rstb_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_rstb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_rstb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_rstb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: sdio1_clk_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_clk_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_clk_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_clk_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_clk_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_clk_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_clk_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: sdio1_cmd_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_cmd_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_cmd_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_cmd_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_cmd_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_cmd_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_cmd_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: sf_wpb_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_wpb_pad_ctrl_MASK  0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_wpb_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_wpb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_wpb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_wpb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_wpb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: sf_holdb_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_holdb_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_holdb_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_holdb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_holdb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_holdb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_holdb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: sf_mosi_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_mosi_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_mosi_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_mosi_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_mosi_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_mosi_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_mosi_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: sf_miso_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_miso_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_miso_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_miso_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_miso_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_miso_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_miso_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: sf_sck_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_sck_pad_ctrl_MASK  0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_sck_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_sck_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_sck_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_sck_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_sck_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_012_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_012_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_012_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_012_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_012_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_012_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_012_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_011_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_011_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_011_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_011_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_011_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_011_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_011_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_010_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_010_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_010_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_010_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_010_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_010_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_010_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_009_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_009_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_009_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_009_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_009_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_009_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_009_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_008_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_008_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_008_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_008_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_008_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_008_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_008_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_007_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_007_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_007_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_007_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_007_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_007_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_007_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_006_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_006_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_006_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_006_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_006_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_006_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_006_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_005_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_005_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_005_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_005_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_005_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_005_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_005_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_004_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_004_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_004_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_004_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_004_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_004_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_004_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_003_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_003_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_003_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_003_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_003_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_003_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_003_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_002_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_002_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_002_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_002_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_002_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_002_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_002_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_001_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_000_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: reserved0 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_MASK        0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_027_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_027_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_027_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_027_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_027_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_027_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_027_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_026_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_026_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_026_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_026_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_026_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_026_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_026_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_025_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_025_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_025_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_025_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_025_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_025_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_025_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_024_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_024_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_024_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_024_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_024_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_024_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_024_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_023_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_023_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_023_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_023_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_023_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_023_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_023_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_022_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_022_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_022_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_022_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_022_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_022_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_022_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_021_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_021_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_021_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_021_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_021_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_021_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_021_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_020_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_020_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_020_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_020_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_020_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_020_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_020_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_019_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_019_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_019_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_019_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_019_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_019_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_019_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_018_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_018_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_018_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_018_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_018_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_018_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_018_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_017_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_017_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_017_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_017_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_017_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_017_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_017_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_016_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_015_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_014_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_013_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_042_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_042_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_042_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_042_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_042_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_042_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_042_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_041_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_041_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_041_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_041_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_041_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_041_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_041_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_040_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_040_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_040_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_040_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_040_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_040_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_040_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_039_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_039_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_039_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_039_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_039_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_039_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_039_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_038_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_038_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_038_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_038_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_038_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_038_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_038_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_037_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_037_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_037_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_037_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_037_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_037_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_037_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_036_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_036_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_036_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_036_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_036_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_036_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_036_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_035_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_035_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_035_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_035_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_035_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_035_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_035_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_034_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_034_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_034_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_034_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_034_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_034_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_034_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_033_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_033_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_033_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_033_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_033_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_033_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_033_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_032_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_032_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_032_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_032_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_032_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_032_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_032_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_031_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_030_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_029_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_028_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_057_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_057_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_057_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_057_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_057_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_057_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_057_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_056_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_056_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_056_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_056_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_056_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_056_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_056_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_055_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_055_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_055_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_055_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_055_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_055_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_055_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_054_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_054_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_054_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_054_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_054_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_054_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_054_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_053_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_053_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_053_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_053_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_053_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_053_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_053_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_052_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_052_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_052_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_052_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_052_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_052_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_052_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_051_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_051_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_051_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_051_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_051_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_051_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_051_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_050_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_050_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_050_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_050_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_050_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_050_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_050_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_049_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_049_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_049_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_049_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_049_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_049_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_049_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_048_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_048_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_048_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_048_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_048_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_048_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_048_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_047_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_047_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_047_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_047_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_047_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_047_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_047_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_046_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_045_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_044_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_043_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_9 - Pad pull-up/pull-down control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: spare_pad_ctrl_9 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_072_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_072_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_072_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_072_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_072_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_072_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_072_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_071_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_071_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_071_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_071_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_071_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_071_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_071_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_070_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_070_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_070_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_070_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_070_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_070_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_070_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_069_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_069_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_069_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_069_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_069_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_069_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_069_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_068_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_068_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_068_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_068_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_068_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_068_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_068_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_067_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_067_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_067_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_067_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_067_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_067_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_067_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_066_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_066_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_066_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_066_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_066_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_066_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_066_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_065_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_065_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_065_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_065_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_065_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_065_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_065_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_064_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_064_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_064_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_064_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_064_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_064_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_064_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_063_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_063_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_063_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_063_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_063_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_063_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_063_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_062_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_062_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_062_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_062_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_062_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_062_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_062_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_061_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_060_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_059_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_058_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_10 - Pad pull-up/pull-down control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: spare_pad_ctrl_10 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_087_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_087_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_087_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_087_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_087_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_087_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_087_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_086_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_086_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_086_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_086_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_086_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_086_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_086_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_085_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_085_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_085_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_085_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_085_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_085_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_085_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_084_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_084_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_084_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_084_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_084_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_084_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_084_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_083_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_083_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_083_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_083_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_083_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_083_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_083_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_082_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_082_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_082_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_082_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_082_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_082_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_082_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_081_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_081_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_081_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_081_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_081_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_081_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_081_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_080_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_080_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_080_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_080_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_080_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_080_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_080_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_079_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_079_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_079_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_079_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_079_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_079_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_079_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_078_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_078_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_078_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_078_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_078_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_078_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_078_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_077_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_077_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_077_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_077_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_077_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_077_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_077_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_076_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_075_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_074_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_073_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_11 - Pad pull-up/pull-down control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: spare_pad_ctrl_11 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: reserved0 [29:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved0_MASK       0x3fc00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved0_SHIFT      22
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_098_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_098_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_098_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_098_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_098_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_098_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_098_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_097_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_097_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_097_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_097_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_097_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_097_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_097_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_096_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_096_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_096_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_096_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_096_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_096_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_096_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_095_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_095_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_095_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_095_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_095_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_095_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_095_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_094_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_094_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_094_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_094_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_094_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_094_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_094_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_093_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_093_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_093_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_093_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_093_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_093_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_093_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_092_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_092_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_092_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_092_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_092_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_092_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_092_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_091_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_090_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_089_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_088_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_12 - Pad pull-up/pull-down control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: spare_pad_ctrl_12 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: reserved0 [29:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_reserved0_MASK       0x3fffffff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_reserved0_SHIFT      0
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_324_clk [31:31] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_324_clk_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_324_clk_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_324_clk_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_216_clk [30:30] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_216_clk_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_216_clk_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_216_clk_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_108_clk [29:29] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_108_clk_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_108_clk_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_108_clk_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_mips_clk [28:28] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_mips_clk_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_mips_clk_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_mips_clk_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_098 [27:27] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_098_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_098_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_098_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_097 [26:26] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_097_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_097_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_097_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_089 [25:25] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_089_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_089_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_089_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_082 [24:24] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_082_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_082_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_082_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_074 [23:23] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_074_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_074_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_074_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_073 [22:22] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_073_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_073_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_073_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_065 [21:21] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_065_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_065_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_065_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_036 [20:20] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_036_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_036_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_036_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_032 [19:19] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_032_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_032_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_032_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_024 [18:18] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_024_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_024_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_024_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_023 [17:17] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_023_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_023_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_023_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_019 [16:16] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_019_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_019_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_019_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_015 [15:15] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_015_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_015_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_015_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sf_wpb [14:14] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_wpb_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_wpb_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_wpb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sf_holdb [13:13] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_holdb_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_holdb_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_holdb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_waitb [12:12] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_waitb_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_waitb_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_waitb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_dsb [11:11] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_dsb_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_dsb_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_dsb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_tsb [10:10] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_tsb_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_tsb_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_tsb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_we0b [09:09] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_we0b_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_we0b_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_we0b_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_rwb [08:08] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_rwb_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_rwb_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_rwb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_addr_15 [07:07] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_15_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_15_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_addr_14 [06:06] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_14_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_14_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_addr_13 [05:05] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_13_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_13_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_addr_12 [04:04] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_12_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_12_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_addr_11 [03:03] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_11_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_11_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_addr_10 [02:02] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_10_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_10_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_addr_09 [01:01] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_09_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_09_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_09_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_addr_08 [00:00] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_08_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_08_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_08_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_CTRL - Reset control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0xfffffffe
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               1
+
+/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT   0x00000000
+
+/***************************************************************************
+ *RESET_SOURCE_ENABLE - Reset source enable
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK       0xfffffc00
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT      10
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_MASTER_RESET - Software master reset
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK           0xfffffffe
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT          1
+
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HW_RESET_EXTENSION - Hardware reset extension
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_MONITOR - Reset Monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT  7
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT   6
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT   4
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset history
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:17] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xfffe0000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            17
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [16:16] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 16
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [15:15] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 15
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [14:14] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 14
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [13:13] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 13
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_reset [12:12] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_MASK    0x00001000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT   12
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_reset [11:11] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT    11
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [10:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT       10
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK       0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT      9
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_dl_sw_reset [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK  0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT 8
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 7
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 6
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK   0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT  4
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0
+
+/***************************************************************************
+ *SW_INIT_0_SET - Software init 0 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved0_MASK             0xc0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved0_SHIFT            30
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_MASK          0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_MASK          0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_SHIFT         28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_MASK        0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_SHIFT       27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK        0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT       26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_MASK          0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_SHIFT         25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK          0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK   0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT  23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_MASK          0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_SHIFT         22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK          0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT         21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc1_sw_init_MASK         0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc1_sw_init_SHIFT        20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc1_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK         0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT        19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK           0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT          18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK   0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT  17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_MASK         0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_SHIFT        16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK           0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT          15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK           0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT          14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_MASK          0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_SHIFT         13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_MASK          0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_MASK        0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_SHIFT       11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT       10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK           0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT          9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK           0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK           0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT          6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: pcie_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie_sw_init_MASK          0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie_sw_init_SHIFT         5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_SHIFT   4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT   0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_CLEAR - Software init 0 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved0_MASK           0xc0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved0_SHIFT          30
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_MASK        0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_SHIFT       29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_MASK        0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_SHIFT       28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_MASK      0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_SHIFT     27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK      0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT     26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_MASK        0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_SHIFT       25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK        0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT       24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_MASK        0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_SHIFT       22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK        0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT       21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc1_sw_init_MASK       0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc1_sw_init_SHIFT      20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc1_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK       0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT      19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK         0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT        18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_MASK       0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK         0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT        15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK         0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT        14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_MASK        0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_SHIFT       13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_MASK        0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_SHIFT       12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_MASK      0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_SHIFT     11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK      0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT     10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK         0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT        9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK         0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK         0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT        6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: pcie_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie_sw_init_MASK        0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie_sw_init_SHIFT       5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_STATUS - Software init 0 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved0_MASK          0xc0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved0_SHIFT         30
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_MASK       0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_SHIFT      29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_MASK       0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_SHIFT      28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_MASK       0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_SHIFT      25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK       0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_MASK       0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_SHIFT      22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK       0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT      21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc1_sw_init_MASK      0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc1_sw_init_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc1_sw_init_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK      0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT     19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK        0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT       18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_MASK      0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK        0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT       15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK        0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT       14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_MASK       0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_SHIFT      13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_MASK       0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK        0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: pcie_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie_sw_init_MASK       0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie_sw_init_SHIFT      5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT   2
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT       1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved0_MASK     0xc0000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved0_SHIFT    30
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_MASK  0x20000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_MASK  0x10000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_MASK  0x02000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK  0x01000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr1_sw_init_MASK  0x00400000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK  0x00200000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc1_sw_init_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc1_sw_init_SHIFT 20
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK   0x00040000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT  18
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK   0x00008000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT  15
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK   0x00004000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT  14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_avd0_sw_init_MASK  0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_svd0_sw_init_MASK  0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK   0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT  9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK   0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT  8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT  6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: pcie_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_pcie_sw_init_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_pcie_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved0_SHIFT 30
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr1_sw_init_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc1_sw_init_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc1_sw_init_SHIFT 20
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: pcie_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_pcie_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_pcie_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved0_MASK   0xc0000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved0_SHIFT  30
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr1_sw_init_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc1_sw_init_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc1_sw_init_SHIFT 20
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: pcie_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_pcie_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_pcie_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_1_SET - Software init 1 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK             0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT            5
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK        0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT       4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK        0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT       3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: v3d_top_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: vice2_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice2_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice2_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice2_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_uhfr_sw_init_MASK          0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_uhfr_sw_init_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_uhfr_sw_init_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_CLEAR - Software init 1 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK           0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT          5
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: v3d_top_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: vice2_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice2_sw_init_MASK       0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice2_sw_init_SHIFT      1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice2_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_uhfr_sw_init_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_uhfr_sw_init_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_uhfr_sw_init_DEFAULT     0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_STATUS - Software init 1 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK          0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT         5
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK     0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT    3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: v3d_top_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_SHIFT   2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: vice2_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice2_sw_init_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice2_sw_init_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice2_sw_init_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_uhfr_sw_init_MASK       0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_uhfr_sw_init_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_uhfr_sw_init_DEFAULT    0x00000001
+
+/***************************************************************************
+ *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK     0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT    5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: v3d_top_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: vice2_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vice2_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vice2_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_uhfr_sw_init_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_uhfr_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xffffffe0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: v3d_top_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: vice2_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vice2_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vice2_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_uhfr_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK   0xffffffe0
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT  5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: v3d_top_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: vice2_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vice2_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vice2_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_uhfr_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK  0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved0_SHIFT 30
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc1_sw_init_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc1_sw_init_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: pcie_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie_sw_init_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xffffffe0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 5
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: v3d_top_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: vice2_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice2_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice2_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice2_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_uhfr_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_uhfr_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved0_SHIFT 30
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc1_sw_init_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc1_sw_init_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: pcie_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie_sw_init_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xffffffe0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 5
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: v3d_top_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: vice2_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice2_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice2_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice2_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_uhfr_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_uhfr_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL - Spare control bits reserved for future use
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT         0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTRL - Test port control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SOFT_MODEM_TP 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0  0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET1  1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU     2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SATA    3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS     16
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK     17
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON     18
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     21
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE    22
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM    23
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC     25
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SVD0    27
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVD0    28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO     30
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA   31
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     33
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0   35
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC1   36
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VICE2   37
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0    45
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB1    46
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MOCA    47
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_UHFR    50
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_V3D_TOP 54
+
+/***************************************************************************
+ *TEST_PORT_OUT_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_OUT_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TEST_PORT_IN_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EJTAG_INPUT_EN - EJTAG input bus enables
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xffffff80
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           7
+
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [06:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x0000007f
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA0_CPU_ONE_HOT 4
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA1_CPU_ONE_HOT 8
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_VICE2_ARC0_ONE_HOT 16
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_VICE2_ARC1_ONE_HOT 32
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 64
+
+/***************************************************************************
+ *EJTAG_OUTPUT_SEL - EJTAG output select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         3
+
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA0_CPU 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA1_CPU 3
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_VICE2_ARC0_CPU 4
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_VICE2_ARC1_CPU 5
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 6
+
+/***************************************************************************
+ *UART_ROUTER_SEL - UART Router select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK      0xf0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT     28
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AVD0_OL   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AVD0_IL   6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SID       7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_VICE2_ARC0 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_VICE2_ARC1 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK      0x0f000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT     24
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AVD0_OL   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AVD0_IL   6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SID       7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_VICE2_ARC0 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_VICE2_ARC1 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK      0x00f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AVD0_OL   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AVD0_IL   6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SID       7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_VICE2_ARC0 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_VICE2_ARC1 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK      0x000f0000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AVD0_OL   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AVD0_IL   6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SID       7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_VICE2_ARC0 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_VICE2_ARC1 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK      0x0000f000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AVD0_OL   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AVD0_IL   6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SID       7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_VICE2_ARC0 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_VICE2_ARC1 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK      0x00000f00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_OL   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_IL   6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SID       7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_VICE2_ARC0 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_VICE2_ARC1 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_OL   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_IL   6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SID       7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_VICE2_ARC0 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_VICE2_ARC1 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK      0x0000000f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_OL   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_IL   6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SID       7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_VICE2_ARC0 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_VICE2_ARC1 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15
+
+/***************************************************************************
+ *VTRAP_CTRL - VTRAP Control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK                0xfffff000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT               12
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_threshold [11:11] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_threshold [10:10] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_threshold [09:09] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [08:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x000001f8
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 0x00000018
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_status_clear [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_status_clear [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_status_clear [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VTRAP_STATUS - VTRAP Status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK              0xfffffff8
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT             3
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_status [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_status [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_status [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SSP_CONFIG - Serial Slave Port configuration register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT        0x00000004
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT           0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT     0x00000001
+
+/***************************************************************************
+ *SERS_REV - SERS Revision Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16
+
+/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT     0x00000000
+
+/***************************************************************************
+ *SERS_CFG - SERS Configuration Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT                0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT           0x00000000
+
+/* union - case mapped_buffer_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0x00000000
+
+/* union - case cmd_fifo_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 0x0000001f
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 0x00000010
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT                 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x00404428
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0
+
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x00404448
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0
+
+
+/***************************************************************************
+ *RO_TEST_BLOCK_SEL - Block select for RO testmode
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xffffffe0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        5
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_pwenb [04:04] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DEFAULT  0x00000001
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_ENABLED  0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DISABLED 1
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [03:02] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MIN_LOAD 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MED_LOAD 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MAX_LOAD 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SVT_MIN_LOAD 3
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
+
+/***************************************************************************
+ *TEST_CONFIGURATION - Test configuration
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_timer.h b/include/linux/brcmstb/7425b0/bchp_timer.h
new file mode 100644
index 0000000..25fd513
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_timer.h
@@ -0,0 +1,337 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:43 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_TIMER_H__
+#define BCHP_TIMER_H__
+
+/***************************************************************************
+ *TIMER - Watchdog & Programmable Timers
+ ***************************************************************************/
+#define BCHP_TIMER_TIMER_IS                      0x004067c0 /* TIMER INTERRUPT STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE0                     0x004067c4 /* TIMER CPU INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_TIMER0_CTRL                   0x004067c8 /* TIMER0 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER1_CTRL                   0x004067cc /* TIMER1 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER2_CTRL                   0x004067d0 /* TIMER2 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER3_CTRL                   0x004067d4 /* TIMER3 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER0_STAT                   0x004067d8 /* TIMER0 STATUS REGISTER */
+#define BCHP_TIMER_TIMER1_STAT                   0x004067dc /* TIMER1 STATUS REGISTER */
+#define BCHP_TIMER_TIMER2_STAT                   0x004067e0 /* TIMER2 STATUS REGISTER */
+#define BCHP_TIMER_TIMER3_STAT                   0x004067e4 /* TIMER3 STATUS REGISTER */
+#define BCHP_TIMER_WDTIMEOUT                     0x004067e8 /* WATCHDOG TIMEOUT REGISTER */
+#define BCHP_TIMER_WDCMD                         0x004067ec /* WATCHDOG COMMAND REGISTER */
+#define BCHP_TIMER_WDCHIPRST_CNT                 0x004067f0 /* WATCHDOG CHIP RESET COUNT REGISTER */
+#define BCHP_TIMER_WDCRS                         0x004067f4 /* WATCHDOG CHIP RESET STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE1                     0x004067f8 /* TIMER PCI INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_WDCTRL                        0x004067fc /* WATCHDOG CONTROL REGISTER */
+
+/***************************************************************************
+ *TIMER_IS - TIMER INTERRUPT STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IS :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IS_reserved0_MASK                         0xffffffe0
+#define BCHP_TIMER_TIMER_IS_reserved0_SHIFT                        5
+
+/* TIMER :: TIMER_IS :: WDINT [04:04] */
+#define BCHP_TIMER_TIMER_IS_WDINT_MASK                             0x00000010
+#define BCHP_TIMER_TIMER_IS_WDINT_SHIFT                            4
+#define BCHP_TIMER_TIMER_IS_WDINT_DEFAULT                          0x00000000
+
+/* TIMER :: TIMER_IS :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IS_TMR3TO_MASK                            0x00000008
+#define BCHP_TIMER_TIMER_IS_TMR3TO_SHIFT                           3
+#define BCHP_TIMER_TIMER_IS_TMR3TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IS_TMR2TO_MASK                            0x00000004
+#define BCHP_TIMER_TIMER_IS_TMR2TO_SHIFT                           2
+#define BCHP_TIMER_TIMER_IS_TMR2TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IS_TMR1TO_MASK                            0x00000002
+#define BCHP_TIMER_TIMER_IS_TMR1TO_SHIFT                           1
+#define BCHP_TIMER_TIMER_IS_TMR1TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IS_TMR0TO_MASK                            0x00000001
+#define BCHP_TIMER_TIMER_IS_TMR0TO_SHIFT                           0
+#define BCHP_TIMER_TIMER_IS_TMR0TO_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *TIMER_IE0 - TIMER CPU INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE0 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE0_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE0_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE0 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_DEFAULT                     0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *TIMER0_CTRL - TIMER0 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER0_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER0_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER0_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER0_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER0_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER0_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER0_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER0_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER1_CTRL - TIMER1 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER1_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER1_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER1_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER1_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER1_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER1_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER1_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER1_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER2_CTRL - TIMER2 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER2_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER2_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER2_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER2_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER2_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER2_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER2_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER2_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER3_CTRL - TIMER3 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER3_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER3_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER3_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER3_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER3_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER3_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER3_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER3_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER0_STAT - TIMER0 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER0_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER0_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER0_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER1_STAT - TIMER1 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER1_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER1_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER1_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER2_STAT - TIMER2 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER2_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER2_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER2_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER3_STAT - TIMER3 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER3_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER3_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER3_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *WDTIMEOUT - WATCHDOG TIMEOUT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDTIMEOUT :: WDTIMEOUT_VAL [31:00] */
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_MASK                    0xffffffff
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *WDCMD - WATCHDOG COMMAND REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCMD :: WDCMD [31:00] */
+#define BCHP_TIMER_WDCMD_WDCMD_MASK                                0xffffffff
+#define BCHP_TIMER_WDCMD_WDCMD_SHIFT                               0
+#define BCHP_TIMER_WDCMD_WDCMD_DEFAULT                             0x00000000
+
+/***************************************************************************
+ *WDCHIPRST_CNT - WATCHDOG CHIP RESET COUNT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCHIPRST_CNT :: reserved0 [31:26] */
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_MASK                    0xfc000000
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_SHIFT                   26
+
+/* TIMER :: WDCHIPRST_CNT :: WDCHIPRST_CNT [25:00] */
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_MASK                0x03ffffff
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_SHIFT               0
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_DEFAULT             0x02ffffff
+
+/***************************************************************************
+ *WDCRS - WATCHDOG CHIP RESET STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCRS :: reserved0 [31:01] */
+#define BCHP_TIMER_WDCRS_reserved0_MASK                            0xfffffffe
+#define BCHP_TIMER_WDCRS_reserved0_SHIFT                           1
+
+/* TIMER :: WDCRS :: WDCR [00:00] */
+#define BCHP_TIMER_WDCRS_WDCR_MASK                                 0x00000001
+#define BCHP_TIMER_WDCRS_WDCR_SHIFT                                0
+#define BCHP_TIMER_WDCRS_WDCR_DEFAULT                              0x00000000
+
+/***************************************************************************
+ *TIMER_IE1 - TIMER PCI INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE1 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE1_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE1_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE1 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_DEFAULT                     0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *WDCTRL - WATCHDOG CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCTRL :: reserved0 [31:03] */
+#define BCHP_TIMER_WDCTRL_reserved0_MASK                           0xfffffff8
+#define BCHP_TIMER_WDCTRL_reserved0_SHIFT                          3
+
+/* TIMER :: WDCTRL :: WD_COUNT_MODE [02:02] */
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_MASK                       0x00000004
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_SHIFT                      2
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_DEFAULT                    0x00000000
+
+/* TIMER :: WDCTRL :: WD_EVENT_MODE [01:00] */
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_MASK                       0x00000003
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_SHIFT                      0
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_DEFAULT                    0x00000000
+
+#endif /* #ifndef BCHP_TIMER_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_uarta.h b/include/linux/brcmstb/7425b0/bchp_uarta.h
new file mode 100644
index 0000000..1095861
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_uarta.h
@@ -0,0 +1,391 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:44 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTA_H__
+#define BCHP_UARTA_H__
+
+/***************************************************************************
+ *UARTA - UART A
+ ***************************************************************************/
+#define BCHP_UARTA_RBR                           0x00406b00 /* Receive Buffer Register */
+#define BCHP_UARTA_THR                           0x00406b00 /* Transmit Holding Register */
+#define BCHP_UARTA_DLH                           0x00406b04 /* Divisor Latch High */
+#define BCHP_UARTA_DLL                           0x00406b00 /* Divisor Latch Low */
+#define BCHP_UARTA_IER                           0x00406b04 /* Interrupt Enable Register */
+#define BCHP_UARTA_IIR                           0x00406b08 /* Interrupt Identity Register */
+#define BCHP_UARTA_FCR                           0x00406b08 /* FIFO Control Register */
+#define BCHP_UARTA_LCR                           0x00406b0c /* Line Control Register */
+#define BCHP_UARTA_MCR                           0x00406b10 /* Modem Control Register */
+#define BCHP_UARTA_LSR                           0x00406b14 /* Line Status Register */
+#define BCHP_UARTA_MSR                           0x00406b18 /* Modem Status Register */
+#define BCHP_UARTA_SCR                           0x00406b1c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTA :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTA_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_RBR_reserved0_SHIFT                             8
+
+/* UARTA :: RBR :: RBR [07:00] */
+#define BCHP_UARTA_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTA_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTA_RBR_RBR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTA :: THR :: reserved0 [31:08] */
+#define BCHP_UARTA_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_THR_reserved0_SHIFT                             8
+
+/* UARTA :: THR :: THR [07:00] */
+#define BCHP_UARTA_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTA_THR_THR_SHIFT                                   0
+#define BCHP_UARTA_THR_THR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTA :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTA_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLH_reserved0_SHIFT                             8
+
+/* UARTA :: DLH :: DLH [07:00] */
+#define BCHP_UARTA_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTA_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTA_DLH_DLH_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTA :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTA_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLL_reserved0_SHIFT                             8
+
+/* UARTA :: DLL :: DLL [07:00] */
+#define BCHP_UARTA_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTA_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTA_DLL_DLL_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTA :: IER :: reserved0 [31:08] */
+#define BCHP_UARTA_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IER_reserved0_SHIFT                             8
+
+/* UARTA :: IER :: PTIME [07:07] */
+#define BCHP_UARTA_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTA_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTA_IER_PTIME_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: reserved1 [06:04] */
+#define BCHP_UARTA_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTA_IER_reserved1_SHIFT                             4
+
+/* UARTA :: IER :: EDSSI [03:03] */
+#define BCHP_UARTA_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTA_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTA_IER_EDSSI_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: ELSI [02:02] */
+#define BCHP_UARTA_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTA_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTA_IER_ELSI_DEFAULT                                0x00000000
+
+/* UARTA :: IER :: ETBEI [01:01] */
+#define BCHP_UARTA_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTA_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTA_IER_ETBEI_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: ERBFI [00:00] */
+#define BCHP_UARTA_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTA_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTA_IER_ERBFI_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTA :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTA_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IIR_reserved0_SHIFT                             8
+
+/* UARTA :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTA_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTA_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTA_IIR_FIFOSE_DEFAULT                              0x00000000
+
+/* UARTA :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTA_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTA_IIR_reserved1_SHIFT                             4
+
+/* UARTA :: IIR :: IID [03:00] */
+#define BCHP_UARTA_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTA_IIR_IID_SHIFT                                   0
+#define BCHP_UARTA_IIR_IID_DEFAULT                                 0x00000001
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTA :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTA_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_FCR_reserved0_SHIFT                             8
+
+/* UARTA :: FCR :: RT [07:06] */
+#define BCHP_UARTA_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTA_FCR_RT_SHIFT                                    6
+#define BCHP_UARTA_FCR_RT_DEFAULT                                  0x00000000
+
+/* UARTA :: FCR :: TET [05:04] */
+#define BCHP_UARTA_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTA_FCR_TET_SHIFT                                   4
+#define BCHP_UARTA_FCR_TET_DEFAULT                                 0x00000000
+
+/* UARTA :: FCR :: DMAM [03:03] */
+#define BCHP_UARTA_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTA_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTA_FCR_DMAM_DEFAULT                                0x00000000
+
+/* UARTA :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTA_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTA_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTA_FCR_XFIFOR_DEFAULT                              0x00000000
+
+/* UARTA :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTA_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTA_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTA_FCR_RFIFOR_DEFAULT                              0x00000000
+
+/* UARTA :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTA_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTA_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTA_FCR_FIFOE_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTA :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTA_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LCR_reserved0_SHIFT                             8
+
+/* UARTA :: LCR :: DLAB [07:07] */
+#define BCHP_UARTA_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTA_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTA_LCR_DLAB_DEFAULT                                0x00000000
+
+/* UARTA :: LCR :: BC [06:06] */
+#define BCHP_UARTA_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTA_LCR_BC_SHIFT                                    6
+#define BCHP_UARTA_LCR_BC_DEFAULT                                  0x00000000
+
+/* UARTA :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTA_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTA_LCR_reserved1_SHIFT                             5
+
+/* UARTA :: LCR :: EPS [04:04] */
+#define BCHP_UARTA_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTA_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTA_LCR_EPS_DEFAULT                                 0x00000000
+
+/* UARTA :: LCR :: PEN [03:03] */
+#define BCHP_UARTA_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTA_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTA_LCR_PEN_DEFAULT                                 0x00000000
+
+/* UARTA :: LCR :: STOP [02:02] */
+#define BCHP_UARTA_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTA_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTA_LCR_STOP_DEFAULT                                0x00000000
+
+/* UARTA :: LCR :: DLS [01:00] */
+#define BCHP_UARTA_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTA_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTA_LCR_DLS_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTA :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTA_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTA_MCR_reserved0_SHIFT                             7
+
+/* UARTA :: MCR :: SIRE [06:06] */
+#define BCHP_UARTA_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTA_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTA_MCR_SIRE_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: AFCE [05:05] */
+#define BCHP_UARTA_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTA_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTA_MCR_AFCE_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: LB [04:04] */
+#define BCHP_UARTA_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTA_MCR_LB_SHIFT                                    4
+#define BCHP_UARTA_MCR_LB_DEFAULT                                  0x00000000
+
+/* UARTA :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTA_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTA_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTA_MCR_OUT2_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTA_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTA_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTA_MCR_OUT1_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: RTS [01:01] */
+#define BCHP_UARTA_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTA_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTA_MCR_RTS_DEFAULT                                 0x00000000
+
+/* UARTA :: MCR :: DTR [00:00] */
+#define BCHP_UARTA_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTA_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTA_MCR_DTR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTA :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTA_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LSR_reserved0_SHIFT                             8
+
+/* UARTA :: LSR :: RFE [07:07] */
+#define BCHP_UARTA_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTA_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTA_LSR_RFE_DEFAULT                                 0x00000000
+
+/* UARTA :: LSR :: TEMT [06:06] */
+#define BCHP_UARTA_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTA_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTA_LSR_TEMT_DEFAULT                                0x00000001
+
+/* UARTA :: LSR :: THRE [05:05] */
+#define BCHP_UARTA_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTA_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTA_LSR_THRE_DEFAULT                                0x00000001
+
+/* UARTA :: LSR :: BI [04:04] */
+#define BCHP_UARTA_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTA_LSR_BI_SHIFT                                    4
+#define BCHP_UARTA_LSR_BI_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: FE [03:03] */
+#define BCHP_UARTA_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTA_LSR_FE_SHIFT                                    3
+#define BCHP_UARTA_LSR_FE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: PE [02:02] */
+#define BCHP_UARTA_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTA_LSR_PE_SHIFT                                    2
+#define BCHP_UARTA_LSR_PE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: OE [01:01] */
+#define BCHP_UARTA_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTA_LSR_OE_SHIFT                                    1
+#define BCHP_UARTA_LSR_OE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: DR [00:00] */
+#define BCHP_UARTA_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTA_LSR_DR_SHIFT                                    0
+#define BCHP_UARTA_LSR_DR_DEFAULT                                  0x00000000
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTA :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTA_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_MSR_reserved0_SHIFT                             8
+
+/* UARTA :: MSR :: DCD [07:07] */
+#define BCHP_UARTA_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTA_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTA_MSR_DCD_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: RI [06:06] */
+#define BCHP_UARTA_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTA_MSR_RI_SHIFT                                    6
+#define BCHP_UARTA_MSR_RI_DEFAULT                                  0x00000000
+
+/* UARTA :: MSR :: DSR [05:05] */
+#define BCHP_UARTA_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTA_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTA_MSR_DSR_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: CTS [04:04] */
+#define BCHP_UARTA_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTA_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTA_MSR_CTS_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: DDCD [03:03] */
+#define BCHP_UARTA_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTA_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTA_MSR_DDCD_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: TERI [02:02] */
+#define BCHP_UARTA_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTA_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTA_MSR_TERI_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: DDSR [01:01] */
+#define BCHP_UARTA_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTA_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTA_MSR_DDSR_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: DCTS [00:00] */
+#define BCHP_UARTA_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTA_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTA_MSR_DCTS_DEFAULT                                0x00000000
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTA :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTA_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_SCR_reserved0_SHIFT                             8
+
+/* UARTA :: SCR :: SCR [07:00] */
+#define BCHP_UARTA_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTA_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTA_SCR_SCR_DEFAULT                                 0x00000000
+
+#endif /* #ifndef BCHP_UARTA_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_uartb.h b/include/linux/brcmstb/7425b0/bchp_uartb.h
new file mode 100644
index 0000000..042f398
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_uartb.h
@@ -0,0 +1,60 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon May 17 04:43:02 2010
+ *                 MD5 Checksum         d3eddea23beec7e33d13b4bcb5193126
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTB_H__
+#define BCHP_UARTB_H__
+
+/***************************************************************************
+ *UARTB - UART B
+ ***************************************************************************/
+#define BCHP_UARTB_RBR                           0x00406b40 /* Receive Buffer Register */
+#define BCHP_UARTB_THR                           0x00406b40 /* Transmit Holding Register */
+#define BCHP_UARTB_DLH                           0x00406b44 /* Divisor Latch High */
+#define BCHP_UARTB_DLL                           0x00406b40 /* Divisor Latch Low */
+#define BCHP_UARTB_IER                           0x00406b44 /* Interrupt Enable Register */
+#define BCHP_UARTB_IIR                           0x00406b48 /* Interrupt Identity Register */
+#define BCHP_UARTB_FCR                           0x00406b48 /* FIFO Control Register */
+#define BCHP_UARTB_LCR                           0x00406b4c /* Line Control Register */
+#define BCHP_UARTB_MCR                           0x00406b50 /* Modem Control Register */
+#define BCHP_UARTB_LSR                           0x00406b54 /* Line Status Register */
+#define BCHP_UARTB_MSR                           0x00406b58 /* Modem Status Register */
+#define BCHP_UARTB_SCR                           0x00406b5c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTB_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_uartc.h b/include/linux/brcmstb/7425b0/bchp_uartc.h
new file mode 100644
index 0000000..7d24e18
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_uartc.h
@@ -0,0 +1,60 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon May 17 04:33:49 2010
+ *                 MD5 Checksum         d3eddea23beec7e33d13b4bcb5193126
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTC_H__
+#define BCHP_UARTC_H__
+
+/***************************************************************************
+ *UARTC - UART C
+ ***************************************************************************/
+#define BCHP_UARTC_RBR                           0x00406b80 /* Receive Buffer Register */
+#define BCHP_UARTC_THR                           0x00406b80 /* Transmit Holding Register */
+#define BCHP_UARTC_DLH                           0x00406b84 /* Divisor Latch High */
+#define BCHP_UARTC_DLL                           0x00406b80 /* Divisor Latch Low */
+#define BCHP_UARTC_IER                           0x00406b84 /* Interrupt Enable Register */
+#define BCHP_UARTC_IIR                           0x00406b88 /* Interrupt Identity Register */
+#define BCHP_UARTC_FCR                           0x00406b88 /* FIFO Control Register */
+#define BCHP_UARTC_LCR                           0x00406b8c /* Line Control Register */
+#define BCHP_UARTC_MCR                           0x00406b90 /* Modem Control Register */
+#define BCHP_UARTC_LSR                           0x00406b94 /* Line Status Register */
+#define BCHP_UARTC_MSR                           0x00406b98 /* Modem Status Register */
+#define BCHP_UARTC_SCR                           0x00406b9c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_usb1_ctrl.h b/include/linux/brcmstb/7425b0/bchp_usb1_ctrl.h
new file mode 100644
index 0000000..f343c90
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_usb1_ctrl.h
@@ -0,0 +1,66 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Feb 22 17:28:07 2011
+ *                 MD5 Checksum         13b50036766a17118468ab754c6bd032
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7425/rdb/b0/bchp_usb1_ctrl.h $
+ * 
+ * Hydra_Software_Devel/1   2/23/11 1:44p yuxiaz
+ * SW7425-112: Added rdb files for 7425 B0.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB1_CTRL_H__
+#define BCHP_USB1_CTRL_H__
+
+/***************************************************************************
+ *USB1_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB1_CTRL_SETUP                     0x00490200 /* Setup Register */
+#define BCHP_USB1_CTRL_PLL_CTL                   0x00490204 /* PLL Control Register */
+#define BCHP_USB1_CTRL_FLADJ_VALUE               0x00490208 /* Frame Adjust Value */
+#define BCHP_USB1_CTRL_EBRIDGE                   0x0049020c /* Control Register for EHCI Bridge */
+#define BCHP_USB1_CTRL_OBRIDGE                   0x00490210 /* Control Register for OHCI Bridge */
+#define BCHP_USB1_CTRL_MDIO                      0x00490214 /* MDIO Interface Programming Register */
+#define BCHP_USB1_CTRL_MDIO2                     0x00490218 /* MDIO Interface Read Register */
+#define BCHP_USB1_CTRL_TEST_PORT_CTL             0x0049021c /* Test Port Control Register */
+#define BCHP_USB1_CTRL_USB_SIMCTL                0x00490220 /* Simulation Register */
+#define BCHP_USB1_CTRL_USB_TESTCTL               0x00490224 /* Throutput Test Control */
+#define BCHP_USB1_CTRL_USB_TESTMON               0x00490228 /* Throughput Test Monitor */
+#define BCHP_USB1_CTRL_UTMI_CTL_1                0x0049022c /* UTMI Control Register */
+#define BCHP_USB1_CTRL_UTMI_CTL_2                0x00490230 /* UTMI Control 2 Register */
+#define BCHP_USB1_CTRL_SPARE1                    0x00490234 /* Spare1 Register for future use */
+#define BCHP_USB1_CTRL_SPARE2                    0x00490238 /* Spare2 Register for future use */
+
+#endif /* #ifndef BCHP_USB1_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_usb_ctrl.h b/include/linux/brcmstb/7425b0/bchp_usb_ctrl.h
new file mode 100644
index 0000000..b6eeb28
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_usb_ctrl.h
@@ -0,0 +1,667 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:44 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB_CTRL_H__
+#define BCHP_USB_CTRL_H__
+
+/***************************************************************************
+ *USB_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB_CTRL_SETUP                      0x00480200 /* Setup Register */
+#define BCHP_USB_CTRL_PLL_CTL                    0x00480204 /* PLL Control Register */
+#define BCHP_USB_CTRL_FLADJ_VALUE                0x00480208 /* Frame Adjust Value */
+#define BCHP_USB_CTRL_EBRIDGE                    0x0048020c /* Control Register for EHCI Bridge */
+#define BCHP_USB_CTRL_OBRIDGE                    0x00480210 /* Control Register for OHCI Bridge */
+#define BCHP_USB_CTRL_MDIO                       0x00480214 /* MDIO Interface Programming Register */
+#define BCHP_USB_CTRL_MDIO2                      0x00480218 /* MDIO Interface Read Register */
+#define BCHP_USB_CTRL_TEST_PORT_CTL              0x0048021c /* Test Port Control Register */
+#define BCHP_USB_CTRL_USB_SIMCTL                 0x00480220 /* Simulation Register */
+#define BCHP_USB_CTRL_USB_TESTCTL                0x00480224 /* Throutput Test Control */
+#define BCHP_USB_CTRL_USB_TESTMON                0x00480228 /* Throughput Test Monitor */
+#define BCHP_USB_CTRL_UTMI_CTL_1                 0x0048022c /* UTMI Control Register */
+#define BCHP_USB_CTRL_UTMI_CTL_2                 0x00480230 /* UTMI Control 2 Register */
+#define BCHP_USB_CTRL_SPARE1                     0x00480234 /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE2                     0x00480238 /* Spare2 Register for future use */
+
+/***************************************************************************
+ *SETUP - Setup Register
+ ***************************************************************************/
+/* USB_CTRL :: SETUP :: OC_DISABLE [31:28] */
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK                        0xf0000000
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT                       28
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: SRAM_CS_DIS [27:25] */
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_MASK                       0x0e000000
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_SHIFT                      25
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: SETUP_SPARE [24:13] */
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK                       0x01ffe000
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT                      13
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: async_expire_dis [12:12] */
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK                  0x00001000
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT                 12
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT               0x00000000
+
+/* USB_CTRL :: SETUP :: discon_intr_en [11:11] */
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_MASK                    0x00000800
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_SHIFT                   11
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: con_intr_en [10:10] */
+#define BCHP_USB_CTRL_SETUP_con_intr_en_MASK                       0x00000400
+#define BCHP_USB_CTRL_SETUP_con_intr_en_SHIFT                      10
+#define BCHP_USB_CTRL_SETUP_con_intr_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: soft_shutdown [09:09] */
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_MASK                     0x00000200
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_SHIFT                    9
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_DEFAULT                  0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK                    0x00000100
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT                   8
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK                       0x00000080
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT                      7
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: soft_reset [06:06] */
+#define BCHP_USB_CTRL_SETUP_soft_reset_MASK                        0x00000040
+#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT                       6
+#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: IPP [05:05] */
+#define BCHP_USB_CTRL_SETUP_IPP_MASK                               0x00000020
+#define BCHP_USB_CTRL_SETUP_IPP_SHIFT                              5
+#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: IOC [04:04] */
+#define BCHP_USB_CTRL_SETUP_IOC_MASK                               0x00000010
+#define BCHP_USB_CTRL_SETUP_IOC_SHIFT                              4
+#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: WABO [03:03] */
+#define BCHP_USB_CTRL_SETUP_WABO_MASK                              0x00000008
+#define BCHP_USB_CTRL_SETUP_WABO_SHIFT                             3
+#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNBO [02:02] */
+#define BCHP_USB_CTRL_SETUP_FNBO_MASK                              0x00000004
+#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT                             2
+#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNHW [01:01] */
+#define BCHP_USB_CTRL_SETUP_FNHW_MASK                              0x00000002
+#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT                             1
+#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: BABO [00:00] */
+#define BCHP_USB_CTRL_SETUP_BABO_MASK                              0x00000001
+#define BCHP_USB_CTRL_SETUP_BABO_SHIFT                             0
+#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *PLL_CTL - PLL Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK                  0x80000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT                 31
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT               0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK                      0x40000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT                     30
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                   0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK                      0x20000000
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                     29
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                   0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                     0x10000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                    28
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                  0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                  0x08000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                 27
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT               0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK                          0x07000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT                         24
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT                       0x00000003
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                   0x00800000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                  23
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK                          0x00700000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT                         20
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT                       0x00000003
+
+/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK                          0x000f0000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT                         16
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT                       0x0000000a
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE2 [15:15] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_MASK                   0x00008000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_SHIFT                  15
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_pdiv [14:12] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK                        0x00007000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT                       12
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                     0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                   0x00000c00
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                  10
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK                        0x000003ff
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT                       0
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                     0x00000028
+
+/***************************************************************************
+ *FLADJ_VALUE - Frame Adjust Value
+ ***************************************************************************/
+/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                   0xffffffff
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                  0
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT                0x000c0020
+
+/***************************************************************************
+ *EBRIDGE - Control Register for EHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_size_sel [28:28] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_DEFAULT                 0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *OBRIDGE - Control Register for OHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_size_sel [28:28] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_DEFAULT                 0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *MDIO - MDIO Interface Programming Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO :: MDIO_CLK_SEL [31:31] */
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_MASK                       0x80000000
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_SHIFT                      31
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_DEFAULT                    0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_XVER_SELECT [30:29] */
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_MASK                   0x60000000
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_SHIFT                  29
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_DEFAULT                0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_TERM_SELECT [28:28] */
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_MASK                   0x10000000
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_SHIFT                  28
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_DEFAULT                0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_FS_XVER_OWN [27:27] */
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_MASK                   0x08000000
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_SHIFT                  27
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_DEFAULT                0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_TESTMODE [26:26] */
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_MASK                      0x04000000
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_SHIFT                     26
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_DEFAULT                   0x00000000
+
+/* USB_CTRL :: MDIO :: WR_START [25:25] */
+#define BCHP_USB_CTRL_MDIO_WR_START_MASK                           0x02000000
+#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT                          25
+#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: RD_START [24:24] */
+#define BCHP_USB_CTRL_MDIO_RD_START_MASK                           0x01000000
+#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT                          24
+#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK                          0x00ff0000
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT                         16
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT                       0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK                          0x0000ffff
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT                         0
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *MDIO2 - MDIO Interface Read Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO2 :: SYNOPSIS_CORE_ID [31:16] */
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_MASK                  0xffff0000
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_SHIFT                 16
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_DEFAULT               0x0000270a
+
+/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK                      0x0000ffff
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                     0
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTL - Test Port Control Register
+ ***************************************************************************/
+/* USB_CTRL :: TEST_PORT_CTL :: TP_EN [31:31] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_MASK                     0x80000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_SHIFT                    31
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [30:27] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK               0x78000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT              27
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb1_wr_data_sel [26:26] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_MASK          0x04000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_SHIFT         26
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_DEFAULT       0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb0_wr_data_sel [25:25] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_MASK          0x02000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_SHIFT         25
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_DEFAULT       0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [24:24] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK                0x01000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT               24
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt2_oe [23:23] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_MASK                0x00800000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_SHIFT               23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron1_tstsel [22:22] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_MASK             0x00400000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_SHIFT            22
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron2_tstsel [21:21] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_MASK             0x00200000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_SHIFT            21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: test_clksel [20:19] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_MASK               0x00180000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_SHIFT              19
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_tstsel [18:16] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_MASK             0x00070000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_SHIFT            16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: UTMI_TEST_SEL [15:08] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_MASK             0x0000ff00
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_SHIFT            8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                 0x000000ff
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT                0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *USB_SIMCTL - Simulation Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK                  0x80000000
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                 31
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK                0x40000000
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT               30
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: otg_scale_down_en [29:28] */
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_MASK            0x30000000
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_SHIFT           28
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK                    0x08000000
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT                   27
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK        0x04000000
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT       26
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT     0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:00] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                 0x03ffffff
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT                0
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT              0x00000000
+
+/***************************************************************************
+ *USB_TESTCTL - Throutput Test Control
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:23] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK              0xff800000
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT             23
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: CTRLLER_SEL [22:21] */
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_MASK                 0x00600000
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_SHIFT                21
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK                     0x00100000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                    20
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK                   0x00080000
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                  19
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT                0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK                    0x00070000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                   16
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK              0x0000fc00
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT             10
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK              0x000003ff
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT             0
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT           0x00000000
+
+/***************************************************************************
+ *USB_TESTMON - Throughput Test Monitor
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [31:00] */
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK                0xffffffff
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT               0
+
+/***************************************************************************
+ *UTMI_CTL_1 - UTMI Control Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB_P1 [31:31] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_MASK              0x80000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_SHIFT             31
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK             0x70000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT            28
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT          0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK_P1 [27:27] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_MASK                0x08000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_SHIFT               27
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE3 [26:25] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_MASK              0x06000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_SHIFT             25
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY_P1 [24:24] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_MASK                0x01000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_SHIFT               24
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK                0x00800000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT               23
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK                0x00400000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT               22
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK                0x00200000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT               21
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK                0x00100000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT               20
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                  0x000c0000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                 18
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT               0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT       0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK           0x00010000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT          16
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT        0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB [15:15] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_MASK                 0x00008000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_SHIFT                15
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_DEFAULT              0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK                0x00007000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT               12
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK [11:11] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_MASK                   0x00000800
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_SHIFT                  11
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE1 [10:09] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_MASK              0x00000600
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_SHIFT             9
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY [08:08] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_MASK                   0x00000100
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_SHIFT                  8
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                   0x00000080
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                  7
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                   0x00000040
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                  6
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                   0x00000020
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                  5
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                   0x00000010
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                  4
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK                     0x0000000c
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                    2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                  0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT          0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK              0x00000001
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT             0
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT           0x00000000
+
+/***************************************************************************
+ *UTMI_CTL_2 - UTMI Control 2 Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK               0xffffffff
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT              0
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SPARE1 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE1 :: SPARE1_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *SPARE2 - Spare2 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE2 :: SPARE2_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_DEFAULT                   0x00000000
+
+#endif /* #ifndef BCHP_USB_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/bchp_wktmr.h b/include/linux/brcmstb/7425b0/bchp_wktmr.h
new file mode 100644
index 0000000..941535a
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/bchp_wktmr.h
@@ -0,0 +1,105 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:11:42 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_WKTMR_H__
+#define BCHP_WKTMR_H__
+
+/***************************************************************************
+ *WKTMR - Wakeup timer
+ ***************************************************************************/
+#define BCHP_WKTMR_EVENT                         0x00409580 /* Wakeup Timer Register */
+#define BCHP_WKTMR_COUNTER                       0x00409584 /* Wakeup Counter */
+#define BCHP_WKTMR_ALARM                         0x00409588 /* Wakeup Timer Alarm */
+#define BCHP_WKTMR_PRESCALER                     0x0040958c /* Wakeup Timer Prescaler */
+#define BCHP_WKTMR_PRESCALER_VAL                 0x00409590 /* Wakeup Timer Prescaler Value */
+
+/***************************************************************************
+ *EVENT - Wakeup Timer Register
+ ***************************************************************************/
+/* WKTMR :: EVENT :: reserved0 [31:01] */
+#define BCHP_WKTMR_EVENT_reserved0_MASK                            0xfffffffe
+#define BCHP_WKTMR_EVENT_reserved0_SHIFT                           1
+
+/* WKTMR :: EVENT :: wktmr_alarm_event [00:00] */
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_MASK                    0x00000001
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_SHIFT                   0
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *COUNTER - Wakeup Counter
+ ***************************************************************************/
+/* WKTMR :: COUNTER :: wktmr_counter [31:00] */
+#define BCHP_WKTMR_COUNTER_wktmr_counter_MASK                      0xffffffff
+#define BCHP_WKTMR_COUNTER_wktmr_counter_SHIFT                     0
+#define BCHP_WKTMR_COUNTER_wktmr_counter_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *ALARM - Wakeup Timer Alarm
+ ***************************************************************************/
+/* WKTMR :: ALARM :: wktmr_alarm [31:00] */
+#define BCHP_WKTMR_ALARM_wktmr_alarm_MASK                          0xffffffff
+#define BCHP_WKTMR_ALARM_wktmr_alarm_SHIFT                         0
+#define BCHP_WKTMR_ALARM_wktmr_alarm_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *PRESCALER - Wakeup Timer Prescaler
+ ***************************************************************************/
+/* WKTMR :: PRESCALER :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_reserved0_MASK                        0xfe000000
+#define BCHP_WKTMR_PRESCALER_reserved0_SHIFT                       25
+
+/* WKTMR :: PRESCALER :: wktmr_prescaler [24:00] */
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_MASK                  0x01ffffff
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_SHIFT                 0
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_DEFAULT               0x019bfcc0
+
+/***************************************************************************
+ *PRESCALER_VAL - Wakeup Timer Prescaler Value
+ ***************************************************************************/
+/* WKTMR :: PRESCALER_VAL :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_MASK                    0xfe000000
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_SHIFT                   25
+
+/* WKTMR :: PRESCALER_VAL :: wktmr_prescaler_val [24:00] */
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_MASK          0x01ffffff
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_SHIFT         0
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_DEFAULT       0x00000000
+
+#endif /* #ifndef BCHP_WKTMR_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7425b0/brcmirq.h b/include/linux/brcmstb/7425b0/brcmirq.h
new file mode 100644
index 0000000..a3f7833
--- /dev/null
+++ b/include/linux/brcmstb/7425b0/brcmirq.h
@@ -0,0 +1,53 @@
+/*
+ * 7425b0 IRQ header file autogenerated by update_bchp.pl
+ * DO NOT EDIT THIS FILE BY HAND.
+ *
+ * Copyright (C) 2011 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BRCMIRQ_H_
+#define _BRCMIRQ_H_
+
+#define BRCM_IRQ_EHCI0_0	66
+#define BRCM_IRQ_EHCI0_1	67
+#define BRCM_IRQ_EHCI1_0	71
+#define BRCM_IRQ_EHCI1_1	72
+#define BRCM_IRQ_GENET_0_A	18
+#define BRCM_IRQ_GENET_0_B	19
+#define BRCM_IRQ_GENET_1_A	20
+#define BRCM_IRQ_GENET_1_B	21
+#define BRCM_IRQ_HIF		25
+#define BRCM_IRQ_HIF_SPI	26
+#define BRCM_IRQ_MOCA		31
+#define BRCM_IRQ_OHCI0_0	68
+#define BRCM_IRQ_OHCI0_1	69
+#define BRCM_IRQ_OHCI1_0	73
+#define BRCM_IRQ_OHCI1_1	74
+#define BRCM_IRQ_PCIE_INTA	34
+#define BRCM_IRQ_PCIE_INTB	35
+#define BRCM_IRQ_PCIE_INTC	36
+#define BRCM_IRQ_PCIE_INTD	37
+#define BRCM_IRQ_SATA		42
+#define BRCM_IRQ_SDIO0		44
+#define BRCM_IRQ_SDIO1		45
+#define BRCM_IRQ_STANDBY	50
+#define BRCM_IRQ_UARTA		62
+#define BRCM_IRQ_UARTB		63
+#define BRCM_IRQ_UARTC		64
+#define BRCM_IRQLIST_EHCI	{ 66, 67, 71, 72 }
+#define BRCM_IRQLIST_OHCI	{ 68, 69, 73, 74 }
+
+#endif /* _BRCMIRQ_H_ */
diff --git a/include/linux/brcmstb/7429b0/bchp_aon_ctrl.h b/include/linux/brcmstb/7429b0/bchp_aon_ctrl.h
new file mode 100644
index 0000000..ef007e3
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_aon_ctrl.h
@@ -0,0 +1,1603 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:17 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_CTRL_H__
+#define BCHP_AON_CTRL_H__
+
+/***************************************************************************
+ *AON_CTRL - AON Control Registers
+ ***************************************************************************/
+#define BCHP_AON_CTRL_RESET_CTRL                 0x00408000 /* Reset Control register for AON */
+#define BCHP_AON_CTRL_PM_CTRL                    0x00408004 /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_STATUS                  0x00408008 /* Status register for Power Controller */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS        0x0040800c /* Power Management IRQ input status */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT         0x00408010 /* Power Management Wait counter in place of Wait for MIPS IRQ */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER        0x00408014 /* Deep Standby Assertion Timer */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER         0x00408018 /* Deep Standby Wakeup Timer */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE    0x0040801c /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_LED_CTRL                0x00408020 /* LED set control register */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES     0x00408024 /* LED set control register */
+#define BCHP_AON_CTRL_HLCD_CTRL                  0x00408030 /* HW LED Clock Driver Control */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER    0x00408034 /* Second Fraction Counter Initial value */
+#define BCHP_AON_CTRL_TIME_COUNTER               0x00408038 /* Hour/Minute Counter Initial value */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0           0x0040803c /* Digit Code for digit 0, 1, 2, 3 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1           0x00408040 /* Digit Code for digit 4, 5, 6, 7 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2           0x00408044 /* Digit Code for digit 8, 9 */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET      0x00408048 /* Hour MSD/LSD and minute MSD/LSD address offset */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL            0x0040804c /* LED status control */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0             0x00408050 /* General control register 0 */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0           0x00408054 /* General status register 0 */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0     0x00408058 /* General control register without scan 0 */
+#define BCHP_AON_CTRL_SPARE_CTRL_0               0x00408060 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_SPARE_CTRL_1               0x00408064 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH          0x00408068 /* Scratch register */
+#define BCHP_AON_CTRL_RESET_HISTORY              0x0040806c /* Reset History Register For AON */
+#define BCHP_AON_CTRL_NMI_CTRL                   0x00408070 /* Control register for NMI */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL           0x00408074 /* Ana xtal low cur 40g m7fc gisb control */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL         0x00408078 /* Test_mode control register */
+#define BCHP_AON_CTRL_SUB_TEST_MODE              0x0040807c /* Register source for sub_test_mode */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE          0x00408080 /* Final latched testmode value */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE      0x00408084 /* Final latched sub-testmode value */
+#define BCHP_AON_CTRL_PM_INITIATE                0x00408088 /* Power down initiate */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS             0x0040808c /* Power up restore */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL   0x00408090 /* Ana xtal low cur 40g m7fc external CML control */
+
+/***************************************************************************
+ *RESET_CTRL - Reset Control register for AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_CTRL :: reserved0 [31:04] */
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_MASK                    0xfffffff0
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_SHIFT                   4
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [03:03] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000008
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 3
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable [02:02] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_MASK     0x00000004
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT    2
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_polarity [01:01] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK   0x00000002
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT  1
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_MASK          0x00000001
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_SHIFT         0
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PM_CTRL - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_CTRL :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_MASK                       0xffffff00
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_SHIFT                      8
+
+/* AON_CTRL :: PM_CTRL :: min_s3_width_timer_bypass [07:07] */
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_MASK       0x00000080
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_SHIFT      7
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_DEFAULT    0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_fast_power_down [06:06] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_MASK              0x00000040
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_SHIFT             6
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_DEFAULT           0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_warm_boot [05:05] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_MASK                    0x00000020
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_SHIFT                   5
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_DEFAULT                 0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_deep_standby [04:04] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_MASK                 0x00000010
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_SHIFT                4
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_DEFAULT              0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_clk_divider_reset_en [03:03] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK         0x00000008
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_SHIFT        3
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_DEFAULT      0x00000001
+
+/* AON_CTRL :: PM_CTRL :: pm_use_mips_ready_ctrl [02:02] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_MASK          0x00000004
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_SHIFT         2
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_DEFAULT       0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK             0x00000002
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT            1
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_DEFAULT          0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_MASK                  0x00000001
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT                 0
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PM_STATUS - Status register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_STATUS :: pm_wait_count_upper_bits [31:26] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_MASK      0xfc000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_SHIFT     26
+
+/* AON_CTRL :: PM_STATUS :: pm_wait_counter_active [25:25] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_MASK        0x02000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_SHIFT       25
+
+/* AON_CTRL :: PM_STATUS :: pm_s3_wakeup_reset_ [24:24] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__MASK           0x01000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__SHIFT          24
+
+/* AON_CTRL :: PM_STATUS :: pm_boundary_scan_request [23:23] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_MASK      0x00800000
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_SHIFT     23
+
+/* AON_CTRL :: PM_STATUS :: pm_fast_pd_precharge_valid [22:22] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_MASK    0x00400000
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_SHIFT   22
+
+/* AON_CTRL :: PM_STATUS :: pm_led_out [21:21] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_MASK                    0x00200000
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_SHIFT                   21
+
+/* AON_CTRL :: PM_STATUS :: pm_standby_b [20:20] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_MASK                  0x00100000
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_SHIFT                 20
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs_ng [19:19] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_MASK           0x00080000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_SHIFT          19
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs [18:18] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_MASK              0x00040000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_SHIFT             18
+
+/* AON_CTRL :: PM_STATUS :: pm_rst_clock_div [17:17] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_MASK              0x00020000
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_SHIFT             17
+
+/* AON_CTRL :: PM_STATUS :: pm_pwrdn_pll_req [16:16] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_MASK              0x00010000
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_SHIFT             16
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_xtal_clocks [15:15] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_MASK            0x00008000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_SHIFT           15
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_all_clocks [14:14] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_MASK             0x00004000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_SHIFT            14
+
+/* AON_CTRL :: PM_STATUS :: pm_dphy_standby [13:13] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_MASK               0x00002000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_SHIFT              13
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_cpu_clock [12:12] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_MASK              0x00001000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_SHIFT             12
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_avd_rptd_clock [11:11] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_MASK         0x00000800
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_SHIFT        11
+
+/* AON_CTRL :: PM_STATUS :: pm_power_ctrl_disable [10:10] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_MASK         0x00000400
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_SHIFT        10
+
+/* AON_CTRL :: PM_STATUS :: pm_pll_lock [09:09] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_MASK                   0x00000200
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_SHIFT                  9
+
+/* AON_CTRL :: PM_STATUS :: pm_dram_ready_for_pwrdn [08:08] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_MASK       0x00000100
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_SHIFT      8
+
+/* AON_CTRL :: PM_STATUS :: pm_bsp_ready_for_pwrdn [07:07] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK        0x00000080
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_SHIFT       7
+
+/* AON_CTRL :: PM_STATUS :: pm_mips_ready_for_pwrdn [06:06] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_MASK       0x00000040
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_SHIFT      6
+
+/* AON_CTRL :: PM_STATUS :: pm_sec_avd_rptd_clk_disable [05:05] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_MASK   0x00000020
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_SHIFT  5
+
+/* AON_CTRL :: PM_STATUS :: pm_state [04:00] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_MASK                      0x0000001f
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_SHIFT                     0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_ACTIVE                 0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_PWRDN_RDY              1
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_AVD_RPTD       2
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_CPU            3
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_STANDBY  4
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY                5
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY_WITH_PLLS_ON   6
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_RESET_216_108_CLKS     7
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_ACTIVE   8
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_FAST_PWRDN             9
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S1  10
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_COLD_ENTRY_S2 11
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_WARM_ENTRY_S2 12
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S3  13
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY           14
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S1   15
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S2   16
+
+/***************************************************************************
+ *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
+ ***************************************************************************/
+/* AON_CTRL :: PM_IRQ_INPUT_STATUS :: pm_irq_input_status [31:00] */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_MASK 0xffffffff
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_SHIFT 0
+
+/***************************************************************************
+ *PM_MIPS_WAIT_COUNT - Power Management Wait counter in place of Wait for MIPS IRQ
+ ***************************************************************************/
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_MASK            0xffff0000
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_SHIFT           16
+
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: counter_start_value [15:00] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_MASK  0x0000ffff
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_DEFAULT 0x00000010
+
+/***************************************************************************
+ *PM_S3_STANDBY_TIMER - Deep Standby Assertion Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_MASK           0xf8000000
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_SHIFT          27
+
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_MASK 0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_DEFAULT 0x00083d60
+
+/***************************************************************************
+ *PM_S3_WAKEUP_TIMER - Deep Standby Wakeup Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_MASK            0xf8000000
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_SHIFT           27
+
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_MASK  0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_DEFAULT 0x00083d60
+
+/***************************************************************************
+ *PM_FAST_PWRDN_PRECHARGE - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: reserved0 [31:24] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_MASK       0xff000000
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_SHIFT      24
+
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: pm_fast_power_down_precharge [23:00] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_MASK 0x00ffffff
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_SHIFT 0
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PM_LED_CTRL - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_CTRL :: reserved0 [31:03] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_MASK                   0xfffffff8
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_SHIFT                  3
+
+/* AON_CTRL :: PM_LED_CTRL :: led_status [02:02] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_MASK                  0x00000004
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_SHIFT                 2
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_on [01:01] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_MASK                 0x00000002
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_SHIFT                1
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_off [00:00] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_MASK                0x00000001
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_SHIFT               0
+
+/***************************************************************************
+ *PM_LED_AUTO_ON_ENABLES - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_AUTO_ON_ENABLES :: led_status [31:00] */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_MASK       0xffffffff
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_SHIFT      0
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_DEFAULT    0x00000000
+
+/***************************************************************************
+ *HLCD_CTRL - HW LED Clock Driver Control
+ ***************************************************************************/
+/* AON_CTRL :: HLCD_CTRL :: reserved0 [31:02] */
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_MASK                     0xfffffffc
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_SHIFT                    2
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable_status [01:01] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_MASK            0x00000002
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_SHIFT           1
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable [00:00] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_MASK                   0x00000001
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_SHIFT                  0
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_DEFAULT                0x00000000
+
+/***************************************************************************
+ *SECOND_FRACTION_COUNTER - Second Fraction Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: reserved0 [31:25] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_MASK       0xfe000000
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_SHIFT      25
+
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: second_fraction_counter_init [24:00] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_MASK 0x01ffffff
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_SHIFT 0
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TIME_COUNTER - Hour/Minute Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: TIME_COUNTER :: reserved0 [31:20] */
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_MASK                  0xfff00000
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_SHIFT                 20
+
+/* AON_CTRL :: TIME_COUNTER :: hour_display_mode [19:19] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_MASK          0x00080000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_SHIFT         19
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: mode_12h_24h_init [18:18] */
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_MASK          0x00040000
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_SHIFT         18
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: am_pm_counter_init [17:17] */
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_MASK         0x00020000
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_SHIFT        17
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_DEFAULT      0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: hour_counter_init [16:12] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_MASK          0x0001f000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_SHIFT         12
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: minute_counter_init [11:06] */
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_MASK        0x00000fc0
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_SHIFT       6
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_DEFAULT     0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: second_counter_init [05:00] */
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_MASK        0x0000003f
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_SHIFT       0
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_DEFAULT     0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_0 - Digit Code for digit 0, 1, 2, 3
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_3 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_2 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_1 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_0 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_1 - Digit Code for digit 4, 5, 6, 7
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_7 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_6 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_5 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_4 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_2 - Digit Code for digit 8, 9
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_MASK              0xffff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_SHIFT             16
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_9 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_8 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_ADDR_OFFSET - Hour MSD/LSD and minute MSD/LSD address offset
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_msd_addr_offset [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_MASK 0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_SHIFT 24
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_DEFAULT 0x00000020
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_lsd_addr_offset [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_MASK 0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_SHIFT 16
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_DEFAULT 0x00000024
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_msd_addr_offset [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_MASK 0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_SHIFT 8
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_DEFAULT 0x00000018
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_lsd_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_MASK 0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_SHIFT 0
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_DEFAULT 0x0000001c
+
+/***************************************************************************
+ *LED_STATUS_CTRL - LED status control
+ ***************************************************************************/
+/* AON_CTRL :: LED_STATUS_CTRL :: reserved0 [31:28] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_MASK               0xf0000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_SHIFT              28
+
+/* AON_CTRL :: LED_STATUS_CTRL :: hlcd_state [27:25] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_MASK              0x0e000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_SHIFT             25
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_IDLE         0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_COUNT        1
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_LSD 2
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_MSD 3
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_LSD 4
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_MSD 5
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_STATUS 6
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_update_enable [24:24] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_MASK    0x01000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_SHIFT   24
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_DEFAULT 0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_mask [23:12] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_MASK             0x00fff000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_SHIFT            12
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_DEFAULT          0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_bit_offset [11:08] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_MASK       0x00000f00
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_SHIFT      8
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_DEFAULT    0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_MASK      0x000000ff
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_SHIFT     0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK         0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT        31
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK         0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT        30
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK         0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT        29
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK         0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT        28
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK         0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT        27
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK         0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT        26
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK         0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT        25
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK         0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT        24
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK         0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT        23
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK         0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT        22
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK         0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT        21
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK         0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT        20
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK         0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT        19
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK         0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT        18
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK         0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT        17
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK         0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT        16
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK         0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT        15
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK         0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT        14
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK         0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT        13
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK         0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT        12
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK         0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT        11
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK         0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT        10
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK          0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT         9
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK          0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT         8
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK          0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT         7
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK          0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT         6
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK          0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT         5
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK          0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT         4
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK          0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT         3
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK          0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT         2
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK          0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT         1
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK          0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT         0
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT       0x00000000
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_MASK              0xffffff00
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_SHIFT             8
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_MASK      0x00000080
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT     7
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_MASK      0x00000040
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT     6
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_MASK      0x00000020
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT     5
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_MASK      0x00000010
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT     4
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_MASK      0x00000008
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT     3
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_MASK      0x00000004
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT     2
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_MASK      0x00000002
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT     1
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: ejtag_ce_wakeup_event [00:00] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_MASK  0x00000001
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_MASK 0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_SHIFT 31
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_MASK 0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_SHIFT 30
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_MASK 0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_SHIFT 29
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_MASK 0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_SHIFT 28
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_MASK 0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_SHIFT 27
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_MASK 0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_SHIFT 26
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_MASK 0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_SHIFT 25
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_MASK 0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_SHIFT 24
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_MASK 0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_SHIFT 23
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_MASK 0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_SHIFT 22
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_MASK 0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_SHIFT 21
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_MASK 0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_SHIFT 20
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_MASK 0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_SHIFT 19
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_MASK 0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_SHIFT 18
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_MASK 0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_SHIFT 17
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_MASK 0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_SHIFT 16
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_MASK 0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_SHIFT 15
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_MASK 0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_SHIFT 14
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_MASK 0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_SHIFT 13
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_MASK 0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_SHIFT 12
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_MASK 0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_SHIFT 11
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_MASK 0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_SHIFT 10
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_MASK 0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_SHIFT 5
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_MASK 0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_SHIFT 4
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_MASK 0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_SHIFT 3
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_MASK 0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_SHIFT 2
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: aon_pad_slew_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_aon_pad_slew_0_MASK   0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_aon_pad_slew_0_SHIFT  0
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_aon_pad_slew_0_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SPARE_CTRL_0 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_DEFAULT           0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL_1 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_DEFAULT           0x00000000
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* AON_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK     0xffffffff
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT    0
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT  0x00000000
+
+/***************************************************************************
+ *RESET_HISTORY - Reset History Register For AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_HISTORY :: reserved0 [31:19] */
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_MASK                 0xfff80000
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_SHIFT                19
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [18:18] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK    0x00040000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT   18
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [17:17] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK    0x00020000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT   17
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [16:16] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK     0x00010000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT    16
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [15:15] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK     0x00008000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT    15
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [14:14] */
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK           0x00004000
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT          14
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_DEFAULT        0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: overtemp_reset [13:13] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_MASK            0x00002000
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_SHIFT           13
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_DEFAULT         0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: overvoltage_reset [12:12] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_MASK         0x00001000
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT        12
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_DEFAULT      0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: undervoltage_reset [11:11] */
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_MASK        0x00000800
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT       11
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_DEFAULT     0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: security_dl_sw_reset [10:10] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK      0x00000400
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT     10
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_DEFAULT   0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: security_master_reset [09:09] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_MASK     0x00000200
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_SHIFT    9
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: software_master_reset [08:08] */
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_MASK     0x00000100
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_SHIFT    8
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [07:07] */
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK       0x00000080
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT      7
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_DEFAULT    0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: watchdog_timer_reset [06:06] */
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK      0x00000040
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT     6
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_DEFAULT   0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: smartcard_insert_reset [05:05] */
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK    0x00000020
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT   5
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: s3_wakeup_reset [04:04] */
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_MASK           0x00000010
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_SHIFT          4
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_DEFAULT        0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [03:03] */
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK    0x00000008
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT   3
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: tap_in_system_reset [02:02] */
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_MASK       0x00000004
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_SHIFT      2
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_DEFAULT    0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_MASK     0x00000002
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT    1
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_MASK            0x00000001
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_SHIFT           0
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_DEFAULT         0x00000001
+
+/***************************************************************************
+ *NMI_CTRL - Control register for NMI
+ ***************************************************************************/
+/* AON_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_MASK                0x80000000
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_SHIFT               31
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_DEFAULT             0x00000000
+
+/* AON_CTRL :: NMI_CTRL :: reserved0 [30:03] */
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_MASK                      0x7ffffff8
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_SHIFT                     3
+
+/* AON_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_MASK                0x00000004
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT               2
+
+/* AON_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_MASK            0x00000002
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT           1
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_DEFAULT         0x00000000
+
+/* AON_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_MASK                0x00000001
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT               0
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_DEFAULT             0x00000001
+
+/***************************************************************************
+ *ANA_XTAL_CONTROL - Ana xtal low cur 40g m7fc gisb control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_CONTROL :: reserved0 [31:09] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_MASK              0xfffffe00
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_SHIFT             9
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_test_select_gisb_control [08:08] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_MASK 0x00000100
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_SHIFT 8
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_select_current_gisb_control [07:07] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_MASK 0x00000080
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_SHIFT 7
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_cml_sel_pd [06:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_MASK         0x00000078
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_SHIFT        3
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_DEFAULT      0x00000009
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_d2cbias_gisb_control [02:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_MASK 0x00000007
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_SHIFT 0
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_DEFAULT 0x00000004
+
+/***************************************************************************
+ *SUB_TEST_MODE_CTRL - Test_mode control register
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: reserved0 [31:01] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_MASK            0xfffffffe
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_SHIFT           1
+
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: use_sub_test_mode_reg_src [00:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_MASK 0x00000001
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_SHIFT 0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SUB_TEST_MODE - Register source for sub_test_mode
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_MASK                 0xffffff00
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_SHIFT                8
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [07:07] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK     0x00000080
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT    7
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_DEFAULT  0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [06:06] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK     0x00000040
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT    6
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_DEFAULT  0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [05:05] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK   0x00000020
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT  5
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_mips_in_reset [04:04] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_MASK 0x00000010
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_SHIFT 4
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [03:03] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000008
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 3
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [02:02] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000004
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 2
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK   0x00000003
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT  0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_DEFAULT 0x00000000
+
+/***************************************************************************
+ *LATCHED_TEST_MODE - Final latched testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK     0xffffffff
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT    0
+
+/***************************************************************************
+ *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0
+
+/***************************************************************************
+ *PM_INITIATE - Power down initiate
+ ***************************************************************************/
+/* AON_CTRL :: PM_INITIATE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_MASK                   0xffffff00
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_SHIFT                  8
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_7 [07:07] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_MASK               0x00000080
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_SHIFT              7
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_6 [06:06] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_MASK               0x00000040
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_SHIFT              6
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_5 [05:05] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_MASK               0x00000020
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_SHIFT              5
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_4 [04:04] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_MASK               0x00000010
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_SHIFT              4
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_3 [03:03] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_MASK               0x00000008
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_SHIFT              3
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_2 [02:02] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_MASK               0x00000004
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_SHIFT              2
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_1 [01:01] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_MASK               0x00000002
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_SHIFT              1
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_0 [00:00] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_MASK               0x00000001
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_SHIFT              0
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_DEFAULT            0x00000000
+
+/***************************************************************************
+ *HOST_MISC_CMDS - Power up restore
+ ***************************************************************************/
+/* AON_CTRL :: HOST_MISC_CMDS :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_MASK                0xffffff00
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_SHIFT               8
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_7 [07:07] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_MASK         0x00000080
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_SHIFT        7
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_6 [06:06] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_MASK         0x00000040
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_SHIFT        6
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_5 [05:05] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_MASK         0x00000020
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_SHIFT        5
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_4 [04:04] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_MASK         0x00000010
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_SHIFT        4
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_3 [03:03] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_MASK         0x00000008
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_SHIFT        3
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_2 [02:02] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_MASK         0x00000004
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_SHIFT        2
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: dram_scram_key_reuse_req [01:01] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_MASK 0x00000002
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_SHIFT 1
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_DEFAULT 0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: pm_restore [00:00] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_MASK               0x00000001
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_SHIFT              0
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ANA_XTAL_EXT_CML_CONTROL - Ana xtal low cur 40g m7fc external CML control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: reserved0 [31:06] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_reserved0_MASK      0xffffffc0
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_reserved0_SHIFT     6
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_PMSM_S3_pd_buffer [05:05] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_MASK 0x00000020
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_SHIFT 5
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_override_strap [04:04] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_MASK 0x00000010
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_SHIFT 4
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_pd_buffer [03:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_MASK  0x00000008
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_SHIFT 3
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_div2_sel [02:02] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_MASK   0x00000004
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_SHIFT  2
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_DEFAULT 0x00000001
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_current [01:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_MASK    0x00000003
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_SHIFT   0
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_BASE                  0x00408200
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_START                 0
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_END                   127
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_ELEMENT_SIZE          32
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_RAMi :: SYSTEM_DATA_RAM [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_MASK        0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_SHIFT       0
+
+
+#endif /* #ifndef BCHP_AON_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_aon_pin_ctrl.h b/include/linux/brcmstb/7429b0/bchp_aon_pin_ctrl.h
new file mode 100644
index 0000000..727fd4f
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_aon_pin_ctrl.h
@@ -0,0 +1,673 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:15 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PIN_CTRL_H__
+#define BCHP_AON_PIN_CTRL_H__
+
+/***************************************************************************
+ *AON_PIN_CTRL - AON Pinmux Control Registers
+ ***************************************************************************/
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0         0x00408500 /* Pinmux control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1         0x00408504 /* Pinmux control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2         0x00408508 /* Pinmux control register 2 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3         0x0040850c /* Pinmux control register 3 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0     0x00408510 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1     0x00408514 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2     0x00408518 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0     0x0040851c /* Bypass clock unselect register 0 */
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_05 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_AON_GPIO_05   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_LD1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PKT5_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_I2S_DATA0_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SC_CLK_OUT    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PWM0          5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SDIO0_WPROT   6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_HD_DVI0_16    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_I2S_DATA0_IN  8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_TP_OUT_06     9
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PM_AON_GPIO_05 10
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_04 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_AON_GPIO_04   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_LD0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PKT5_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_I2S_CLK0_OUT  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_EXT_IRQB_1    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_IR_OUT        5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SDIO0_CMD     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_HD_DVI0_17    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_I2S_CLK0_IN   8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_TP_OUT_05     9
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PM_AON_GPIO_04 10
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_03 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_DEFAULT       0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_GPIO_03   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_OUT       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_FP_4SEC_RESETB 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_EXT_IRQB_0    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_IR_OUT        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_IR_INT        5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_IR_IN1    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MOCA_ACTIVITY 7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_TP_OUT_04     8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PM_AON_GPIO_03 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_02 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_AON_GPIO_02   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_PM_AON_GPIO_02 1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_01 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AON_GPIO_01   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET0_LINK    1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_PWM0          2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET0_ACTIVITY 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_IR_OUT        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_VEC_VSYNC     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_RMX1_VALID    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AUD_FS_CLK1   7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET1_LINK    8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_TP_OUT_03     9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_00 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AON_GPIO_00   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AUD_SPDIF     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_TP_OUT_02     2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_s3_standbyb [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_MASK      0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_SHIFT     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_DEFAULT   0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_AON_S3_STANDBYB 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_TP_OUT_01 1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_ir_in0 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_MASK           0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_SHIFT          0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_DEFAULT        0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_AON_IR_IN0     0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_TP_IN_08       1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_13 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_AON_GPIO_13   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_LED_LS1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PKT2_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_VO0_656_0     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SC1_AUX1      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_AON_IR_IN1    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SDIO0_CLK     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_HD_DVI0_8     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_UART_CTS0     8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_TP_OUT_00     9
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PM_AON_GPIO_13 10
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_12 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_AON_GPIO_12   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_LS0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PKT2_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_VO0_656_CLK   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SC1_VPP       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SDIO0_PWR0    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_HD_DVI0_9     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_UART_RX0      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_ALT_TP_IN_01  8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PM_AON_GPIO_12 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_11 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_GPIO_11   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_LED_LD7       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SC1_CLK       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_CODEC_MCLK    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_CLK_27    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SPI_M_SCK     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_ENET0_ACTIVITY 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_MOCA_LINK     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_TP_OUT_09     8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_10 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_AON_GPIO_10   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_LED_LD6       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SC1_VCC       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_CODEC_SDO     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_UART_RTS2     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SPI_M_SS0B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_UART_TX1      6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_IR_OUT        7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_UART_RTS0     8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_ALT_TP_OUT_10 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_09 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_AON_GPIO_09   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_LED_LD5       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SC1_RST       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_CODEC_SCLK    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_UART_TX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SPI_M_MOSI    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_UART_RTS1     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_HD_DVI0_12    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_UART_TX0      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_ALT_TP_OUT_00 9
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_PM_AON_GPIO_09 10
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_08 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_AON_GPIO_08   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_LED_LD4       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SC1_IO        2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_CODEC_FSYNCB  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_UART_CTS2     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SPI_M_SS1B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_UART_RX1      6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_HD_DVI0_13    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_UART_CTS0     8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_ALT_TP_IN_10  9
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_PM_AON_GPIO_08 10
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_07 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_AON_GPIO_07   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_LED_LD3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SC1_PRES      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_CODEC_SDI     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_UART_RX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SPI_M_MISO    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_UART_CTS1     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_HD_DVI0_14    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_UART_RX0      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_ALT_TP_IN_00  9
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_PM_AON_GPIO_07 10
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_06 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_AON_GPIO_06   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_LED_LD2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PKT5_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_I2S_LR0_OUT   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SC_EXT_CLK    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_VEC_VSYNC     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_IR_INT        6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_HD_DVI0_15    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_I2S_LR0_IN    8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_TP_OUT_07     9
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PM_AON_GPIO_06 10
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_00 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_MASK         0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SHIFT        28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_AON_SGPIO_00 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_AON_BSC_M0_SCL 1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_20 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_GPIO_20   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_LED_KD3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PKT4_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_VO0_656_7     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_CLK_OBSRV     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_CLK_27    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AUD_FS_CLK1   6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_HD_DVI0_1     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_IR_IN1    8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_TP_OUT_15     9
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PM_AON_GPIO_20 10
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_19 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_AON_GPIO_19   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_LED_KD2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_PKT4_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_VO0_656_6     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SC1_PRES      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SPI_M_MISO    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SDIO0_PRES    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_HD_DVI0_2     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_TP_OUT_14     8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_PM_AON_GPIO_19 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_18 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_AON_GPIO_18   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_LED_KD1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PKT4_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_VO0_656_5     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SC1_IO        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SPI_M_SS1B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SDIO0_DAT3    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_HD_DVI0_3     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_TP_OUT_13     8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PM_AON_GPIO_18 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_17 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_AON_GPIO_17   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_LED_KD0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PKT3_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_VO0_656_4     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SC1_RST       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SPI_M_MOSI    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SDIO0_DAT2    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_HD_DVI0_4     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_TP_OUT_12     8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PM_AON_GPIO_17 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_16 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_AON_GPIO_16   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_LED_LS4       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PKT3_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_VO0_656_3     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SC1_CLK       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SPI_M_SCK     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SDIO0_DAT1    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_HD_DVI0_5     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_TP_OUT_11     8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PM_AON_GPIO_16 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_15 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_AON_GPIO_15   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_LED_LS3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PKT3_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_VO0_656_2     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SC1_VCC       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SPI_M_SS0B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SDIO0_DAT0    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_HD_DVI0_6     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_UART_RTS0     8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_TP_OUT_10     9
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PM_AON_GPIO_15 10
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_14 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_AON_GPIO_14   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_LED_LS2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_PKT2_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_VO0_656_1     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SC1_AUX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_MOCA_ACTIVITY 5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SDIO0_LED     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_HD_DVI0_7     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_UART_TX0      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_ALT_TP_OUT_01 9
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_PM_AON_GPIO_14 10
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: reserved0 [31:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_MASK            0xfff00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_SHIFT           20
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_05 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_MASK         0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_SHIFT        16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_AON_SGPIO_05 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_AON_BSC_M2_SDA 1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_04 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_MASK         0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_SHIFT        12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_AON_SGPIO_04 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_AON_BSC_M2_SCL 1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_03 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_MASK         0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_SHIFT        8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_AON_SGPIO_03 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_AON_BSC_M1_SDA 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_AON_BSC_S1_SDA 2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_02 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_02_MASK         0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_02_SHIFT        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_02_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_02_AON_SGPIO_02 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_02_AON_BSC_M1_SCL 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_02_AON_BSC_S1_SCL 2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_01 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_MASK         0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_SHIFT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_AON_SGPIO_01 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_AON_BSC_M0_SDA 1
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_07_pad_ctrl [29:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_MASK 0x30000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_SHIFT 28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_06_pad_ctrl [27:26] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_MASK 0x0c000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_SHIFT 26
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_05_pad_ctrl [25:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_MASK 0x03000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_SHIFT 24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_04_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_03_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_02_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_01_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_00_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [13:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x00003fff
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:26] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0x3c000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       26
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_20_pad_ctrl [25:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_MASK 0x03000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_SHIFT 24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_19_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_18_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_17_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_16_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_15_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_14_pad_ctrl [13:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_MASK 0x00003000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_SHIFT 12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_13_pad_ctrl [11:10] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_MASK 0x00000c00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_SHIFT 10
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_12_pad_ctrl [09:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_MASK 0x00000300
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_SHIFT 8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_11_pad_ctrl [07:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_MASK 0x000000c0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_SHIFT 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_10_pad_ctrl [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_09_pad_ctrl [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_08_pad_ctrl [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_08_pad_ctrl_MASK 0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_08_pad_ctrl_SHIFT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_08_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_08_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [31:10] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK        0xfffffc00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT       10
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [09:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0x00000300
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved1 [07:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_MASK        0x000000ff
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_SHIFT       0
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:02] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffffc
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       2
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_nmib [01:01] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_MASK 0x00000002
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_SHIFT 1
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_reset_outb [00:00] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_MASK 0x00000001
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_SHIFT 0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_AON_PIN_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_aon_pm_l2.h b/include/linux/brcmstb/7429b0/bchp_aon_pm_l2.h
new file mode 100644
index 0000000..10f7888
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_aon_pm_l2.h
@@ -0,0 +1,1044 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:14 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PM_L2_H__
+#define BCHP_AON_PM_L2_H__
+
+/***************************************************************************
+ *AON_PM_L2 - AON Power Management L2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_AON_PM_L2_CPU_STATUS                0x00408440 /* CPU interrupt Status Register */
+#define BCHP_AON_PM_L2_CPU_SET                   0x00408444 /* CPU interrupt Set Register */
+#define BCHP_AON_PM_L2_CPU_CLEAR                 0x00408448 /* CPU interrupt Clear Register */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS           0x0040844c /* CPU interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_CPU_MASK_SET              0x00408450 /* CPU interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR            0x00408454 /* CPU interrupt Mask Clear Register */
+#define BCHP_AON_PM_L2_PCI_STATUS                0x00408458 /* PCI interrupt Status Register */
+#define BCHP_AON_PM_L2_PCI_SET                   0x0040845c /* PCI interrupt Set Register */
+#define BCHP_AON_PM_L2_PCI_CLEAR                 0x00408460 /* PCI interrupt Clear Register */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS           0x00408464 /* PCI interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_PCI_MASK_SET              0x00408468 /* PCI interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR            0x0040846c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_STATUS :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_MASK                   0xffff8000
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_SHIFT                  15
+
+/* AON_PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_0 [14:14] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x00004000
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       14
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: FP_RESET [13:13] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_MASK                    0x00002000
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_SHIFT                   13
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: BOUNDARY_SCAN_REQ [12:12] */
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00001000
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_SHIFT          12
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: USB1 [11:11] */
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_MASK                        0x00000800
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_SHIFT                       11
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: USB0 [10:10] */
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_MASK                        0x00000400
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_SHIFT                       10
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: MOCA [09:09] */
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_MASK                        0x00000200
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_SHIFT                       9
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: XPT_PMU [08:08] */
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_MASK                     0x00000100
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_SHIFT                    8
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_ENET [07:07] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_MASK                    0x00000080
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_SHIFT                   7
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_MOCA [06:06] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_MASK                    0x00000040
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_SHIFT                   6
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_SET :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_MASK                      0xffff8000
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_SHIFT                     15
+
+/* AON_PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_0 [14:14] */
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_MASK           0x00004000
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_SHIFT          14
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: FP_RESET [13:13] */
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_MASK                       0x00002000
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_SHIFT                      13
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: BOUNDARY_SCAN_REQ [12:12] */
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_MASK              0x00001000
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_SHIFT             12
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_DEFAULT           0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: USB1 [11:11] */
+#define BCHP_AON_PM_L2_CPU_SET_USB1_MASK                           0x00000800
+#define BCHP_AON_PM_L2_CPU_SET_USB1_SHIFT                          11
+#define BCHP_AON_PM_L2_CPU_SET_USB1_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: USB0 [10:10] */
+#define BCHP_AON_PM_L2_CPU_SET_USB0_MASK                           0x00000400
+#define BCHP_AON_PM_L2_CPU_SET_USB0_SHIFT                          10
+#define BCHP_AON_PM_L2_CPU_SET_USB0_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: MOCA [09:09] */
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_MASK                           0x00000200
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_SHIFT                          9
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: XPT_PMU [08:08] */
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_MASK                        0x00000100
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_SHIFT                       8
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: WOL_ENET [07:07] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_MASK                       0x00000080
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_SHIFT                      7
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: WOL_MOCA [06:06] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_MOCA_MASK                       0x00000040
+#define BCHP_AON_PM_L2_CPU_SET_WOL_MOCA_SHIFT                      6
+#define BCHP_AON_PM_L2_CPU_SET_WOL_MOCA_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_CLEAR :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_MASK                    0xffff8000
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_SHIFT                   15
+
+/* AON_PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_0 [14:14] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x00004000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        14
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: FP_RESET [13:13] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_MASK                     0x00002000
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_SHIFT                    13
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: BOUNDARY_SCAN_REQ [12:12] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00001000
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           12
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: USB1 [11:11] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_MASK                         0x00000800
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_SHIFT                        11
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: USB0 [10:10] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_MASK                         0x00000400
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_SHIFT                        10
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: MOCA [09:09] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_MASK                         0x00000200
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_SHIFT                        9
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: XPT_PMU [08:08] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_MASK                      0x00000100
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT                     8
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_ENET [07:07] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_MASK                     0x00000080
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_SHIFT                    7
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_MOCA [06:06] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_MOCA_MASK                     0x00000040
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_MOCA_SHIFT                    6
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_MOCA_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_MASK              0xffff8000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT             15
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  14
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FP_RESET [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_MASK               0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_SHIFT              13
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: BOUNDARY_SCAN_REQ [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     12
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: USB1 [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_MASK                   0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_SHIFT                  11
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: USB0 [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_MASK                   0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_SHIFT                  10
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: MOCA [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_MASK                   0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_SHIFT                  9
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK                0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT               8
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_ENET [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_MASK               0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_SHIFT              7
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_MOCA [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_MOCA_MASK               0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_MOCA_SHIFT              6
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_MOCA_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_DEFAULT            0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_SET :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_MASK                 0xffff8000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_SHIFT                15
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_0 [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     14
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FP_RESET [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_MASK                  0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_SHIFT                 13
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: BOUNDARY_SCAN_REQ [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        12
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: USB1 [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_MASK                      0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_SHIFT                     11
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: USB0 [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_MASK                      0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_SHIFT                     10
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: MOCA [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_MASK                      0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_SHIFT                     9
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: XPT_PMU [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_MASK                   0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT                  8
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_ENET [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_MASK                  0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_SHIFT                 7
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_MOCA [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_MOCA_MASK                  0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_MOCA_SHIFT                 6
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_MOCA_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_DEFAULT               0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_MASK               0xffff8000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT              15
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   14
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FP_RESET [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_MASK                0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_SHIFT               13
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: BOUNDARY_SCAN_REQ [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      12
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB1 [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_MASK                    0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_SHIFT                   11
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB0 [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_MASK                    0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_SHIFT                   10
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: MOCA [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_MASK                    0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_SHIFT                   9
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK                 0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT                8
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_ENET [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_MASK                0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_SHIFT               7
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_MOCA [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_MASK                0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_SHIFT               6
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_DEFAULT             0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_STATUS :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_MASK                   0xffff8000
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_SHIFT                  15
+
+/* AON_PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_0 [14:14] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x00004000
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       14
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: FP_RESET [13:13] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_MASK                    0x00002000
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_SHIFT                   13
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: BOUNDARY_SCAN_REQ [12:12] */
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00001000
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_SHIFT          12
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: USB1 [11:11] */
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_MASK                        0x00000800
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_SHIFT                       11
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: USB0 [10:10] */
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_MASK                        0x00000400
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_SHIFT                       10
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: MOCA [09:09] */
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_MASK                        0x00000200
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_SHIFT                       9
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: XPT_PMU [08:08] */
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_MASK                     0x00000100
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_SHIFT                    8
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_ENET [07:07] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_MASK                    0x00000080
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_SHIFT                   7
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_MOCA [06:06] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_MOCA_MASK                    0x00000040
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_MOCA_SHIFT                   6
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_MOCA_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_SET :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_MASK                      0xffff8000
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_SHIFT                     15
+
+/* AON_PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_0 [14:14] */
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_MASK           0x00004000
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_SHIFT          14
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: FP_RESET [13:13] */
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_MASK                       0x00002000
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_SHIFT                      13
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: BOUNDARY_SCAN_REQ [12:12] */
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_MASK              0x00001000
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_SHIFT             12
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_DEFAULT           0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: USB1 [11:11] */
+#define BCHP_AON_PM_L2_PCI_SET_USB1_MASK                           0x00000800
+#define BCHP_AON_PM_L2_PCI_SET_USB1_SHIFT                          11
+#define BCHP_AON_PM_L2_PCI_SET_USB1_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: USB0 [10:10] */
+#define BCHP_AON_PM_L2_PCI_SET_USB0_MASK                           0x00000400
+#define BCHP_AON_PM_L2_PCI_SET_USB0_SHIFT                          10
+#define BCHP_AON_PM_L2_PCI_SET_USB0_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: MOCA [09:09] */
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_MASK                           0x00000200
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_SHIFT                          9
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: XPT_PMU [08:08] */
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_MASK                        0x00000100
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_SHIFT                       8
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: WOL_ENET [07:07] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_MASK                       0x00000080
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_SHIFT                      7
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: WOL_MOCA [06:06] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_MOCA_MASK                       0x00000040
+#define BCHP_AON_PM_L2_PCI_SET_WOL_MOCA_SHIFT                      6
+#define BCHP_AON_PM_L2_PCI_SET_WOL_MOCA_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_CLEAR :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_MASK                    0xffff8000
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_SHIFT                   15
+
+/* AON_PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_0 [14:14] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x00004000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        14
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: FP_RESET [13:13] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_MASK                     0x00002000
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_SHIFT                    13
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: BOUNDARY_SCAN_REQ [12:12] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00001000
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           12
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: USB1 [11:11] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_MASK                         0x00000800
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_SHIFT                        11
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: USB0 [10:10] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_MASK                         0x00000400
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_SHIFT                        10
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: MOCA [09:09] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_MASK                         0x00000200
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_SHIFT                        9
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: XPT_PMU [08:08] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_MASK                      0x00000100
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT                     8
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_ENET [07:07] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_MASK                     0x00000080
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_SHIFT                    7
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_MOCA [06:06] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_MOCA_MASK                     0x00000040
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_MOCA_SHIFT                    6
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_MOCA_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_MASK              0xffff8000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT             15
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  14
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FP_RESET [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_MASK               0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_SHIFT              13
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: BOUNDARY_SCAN_REQ [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     12
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: USB1 [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_MASK                   0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_SHIFT                  11
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: USB0 [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_MASK                   0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_SHIFT                  10
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: MOCA [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_MASK                   0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_SHIFT                  9
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK                0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT               8
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_ENET [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_MASK               0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_SHIFT              7
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_MOCA [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_MOCA_MASK               0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_MOCA_SHIFT              6
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_MOCA_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_DEFAULT            0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_SET :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_MASK                 0xffff8000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_SHIFT                15
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_0 [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     14
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FP_RESET [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_MASK                  0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_SHIFT                 13
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: BOUNDARY_SCAN_REQ [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        12
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: USB1 [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_MASK                      0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_SHIFT                     11
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: USB0 [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_MASK                      0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_SHIFT                     10
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: MOCA [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_MASK                      0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_SHIFT                     9
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: XPT_PMU [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_MASK                   0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT                  8
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_ENET [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_MASK                  0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_SHIFT                 7
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_MOCA [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_MOCA_MASK                  0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_MOCA_SHIFT                 6
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_MOCA_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_DEFAULT               0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_MASK               0xffff8000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT              15
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   14
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FP_RESET [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_MASK                0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_SHIFT               13
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: BOUNDARY_SCAN_REQ [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      12
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB1 [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_MASK                    0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_SHIFT                   11
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB0 [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_MASK                    0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_SHIFT                   10
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: MOCA [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_MASK                    0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_SHIFT                   9
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK                 0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT                8
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_ENET [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_MASK                0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_SHIFT               7
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_MOCA [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_MASK                0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_SHIFT               6
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_DEFAULT             0x00000001
+
+#endif /* #ifndef BCHP_AON_PM_L2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_bspi.h b/include/linux/brcmstb/7429b0/bchp_bspi.h
new file mode 100644
index 0000000..a2940db
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_bspi.h
@@ -0,0 +1,443 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:16 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_H__
+#define BCHP_BSPI_H__
+
+/***************************************************************************
+ *BSPI - Public BSPI Control Registers
+ ***************************************************************************/
+#define BCHP_BSPI_REVISION_ID                    0x00413000 /* Revision ID */
+#define BCHP_BSPI_SCRATCH                        0x00413004 /* Revision ID */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL               0x00413008 /* Master/Boot SPI Control Register */
+#define BCHP_BSPI_BUSY_STATUS                    0x0041300c /* BSPI Busy Status Register */
+#define BCHP_BSPI_INTR_STATUS                    0x00413010 /* Interrupt Status Register */
+#define BCHP_BSPI_B0_STATUS                      0x00413014 /* Prefetch Buffer 0 Status Register */
+#define BCHP_BSPI_B0_CTRL                        0x00413018 /* Prefetch Buffer 0 Control Register */
+#define BCHP_BSPI_B1_STATUS                      0x0041301c /* Prefetch Buffer 1 Status Register */
+#define BCHP_BSPI_B1_CTRL                        0x00413020 /* Prefetch Buffer 1 Control Register */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL            0x00413024 /* Dual/Single Receive Mode Control Register */
+#define BCHP_BSPI_FLEX_MODE_ENABLE               0x00413028 /* Flexible Control Mode Enable Register */
+#define BCHP_BSPI_BITS_PER_CYCLE                 0x0041302c /* Bits per cycle "b-p-c" Control Register */
+#define BCHP_BSPI_BITS_PER_PHASE                 0x00413030 /* Bits per Phase "b-p-p" Control Register */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE              0x00413034 /* Command and Mode Data Register */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE     0x00413038 /* Bspi FLash upper address byte register */
+#define BCHP_BSPI_BSPI_XOR_VALUE                 0x0041303c /* BSPI FLASH XOR Value Register */
+#define BCHP_BSPI_BSPI_XOR_ENABLE                0x00413040 /* BSPI FLASH XOR Enable Register */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE           0x00413044 /* BSPI Pin  Programmed IO Mode Enable Register */
+#define BCHP_BSPI_BSPI_PIO_IODIR                 0x00413048 /* BSPI Pin  Programmed IO Mode Direction Register */
+#define BCHP_BSPI_BSPI_PIO_DATA                  0x0041304c /* BSPI Pin  Programmed IO Mode Data Register */
+
+/***************************************************************************
+ *REVISION_ID - Revision ID
+ ***************************************************************************/
+/* BSPI :: REVISION_ID :: reserved0 [31:16] */
+#define BCHP_BSPI_REVISION_ID_reserved0_MASK                       0xffff0000
+#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT                      16
+
+/* BSPI :: REVISION_ID :: MAJOR [15:08] */
+#define BCHP_BSPI_REVISION_ID_MAJOR_MASK                           0x0000ff00
+#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT                          8
+#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT                        0x00000004
+
+/* BSPI :: REVISION_ID :: MINOR [07:00] */
+#define BCHP_BSPI_REVISION_ID_MINOR_MASK                           0x000000ff
+#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT                          0
+#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT                        0x00000001
+
+/***************************************************************************
+ *SCRATCH - Revision ID
+ ***************************************************************************/
+/* BSPI :: SCRATCH :: SCRATCH [31:00] */
+#define BCHP_BSPI_SCRATCH_SCRATCH_MASK                             0xffffffff
+#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT                            0
+#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
+ ***************************************************************************/
+/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT                 1
+
+/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK                0x00000001
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT               0
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT             0x00000000
+
+/***************************************************************************
+ *BUSY_STATUS - BSPI Busy Status Register
+ ***************************************************************************/
+/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
+#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK                       0xfffffffe
+#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT                      1
+
+/* BSPI :: BUSY_STATUS :: busy [00:00] */
+#define BCHP_BSPI_BUSY_STATUS_busy_MASK                            0x00000001
+#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT                           0
+#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *INTR_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
+#define BCHP_BSPI_INTR_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT                      2
+
+/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
+#define BCHP_BSPI_INTR_STATUS_intr_1_MASK                          0x00000002
+#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT                         1
+#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT                       0x00000000
+
+/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
+#define BCHP_BSPI_INTR_STATUS_intr_0_MASK                          0x00000001
+#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT                         0
+#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *B0_STATUS - Prefetch Buffer 0 Status Register
+ ***************************************************************************/
+/* BSPI :: B0_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B0_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B0_STATUS :: b0_full [29:29] */
+#define BCHP_BSPI_B0_STATUS_b0_full_MASK                           0x20000000
+#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT                          29
+#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_empty [28:28] */
+#define BCHP_BSPI_B0_STATUS_b0_empty_MASK                          0x10000000
+#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT                         28
+#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B0_STATUS :: b0_miss [27:27] */
+#define BCHP_BSPI_B0_STATUS_b0_miss_MASK                           0x08000000
+#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT                          27
+#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_hit [26:26] */
+#define BCHP_BSPI_B0_STATUS_b0_hit_MASK                            0x04000000
+#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT                           26
+#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B0_STATUS :: b0_address [25:00] */
+#define BCHP_BSPI_B0_STATUS_b0_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT                       0
+#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B0_CTRL - Prefetch Buffer 0 Control Register
+ ***************************************************************************/
+/* BSPI :: B0_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B0_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B0_CTRL :: b0_flush [00:00] */
+#define BCHP_BSPI_B0_CTRL_b0_flush_MASK                            0x00000001
+#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT                           0
+#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *B1_STATUS - Prefetch Buffer 1 Status Register
+ ***************************************************************************/
+/* BSPI :: B1_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B1_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B1_STATUS :: b1_full [29:29] */
+#define BCHP_BSPI_B1_STATUS_b1_full_MASK                           0x20000000
+#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT                          29
+#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_empty [28:28] */
+#define BCHP_BSPI_B1_STATUS_b1_empty_MASK                          0x10000000
+#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT                         28
+#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B1_STATUS :: b1_miss [27:27] */
+#define BCHP_BSPI_B1_STATUS_b1_miss_MASK                           0x08000000
+#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT                          27
+#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_hit [26:26] */
+#define BCHP_BSPI_B1_STATUS_b1_hit_MASK                            0x04000000
+#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT                           26
+#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B1_STATUS :: b1_address [25:00] */
+#define BCHP_BSPI_B1_STATUS_b1_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT                       0
+#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B1_CTRL - Prefetch Buffer 1 Control Register
+ ***************************************************************************/
+/* BSPI :: B1_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B1_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B1_CTRL :: b1_flush [00:00] */
+#define BCHP_BSPI_B1_CTRL_b1_flush_MASK                            0x00000001
+#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT                           0
+#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
+ ***************************************************************************/
+/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK               0xffffffe0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT              5
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK             0x00000010
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT            4
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT          0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK               0x00000008
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT              3
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT            0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK      0x00000004
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT     2
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT   0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK         0x00000002
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT        1
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT      0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK                0x00000001
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT               0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT             0x00000000
+
+/***************************************************************************
+ *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT                 1
+
+/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK      0x00000001
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT     0
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT   0x00000000
+
+/***************************************************************************
+ *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK                    0xfc000000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT                   26
+
+/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK               0x03000000
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK                    0x00fc0000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT                   18
+
+/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK              0x00030000
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK                    0x0000fc00
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT                   10
+
+/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK              0x00000300
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT             8
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK                    0x000000fc
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT                   2
+
+/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK              0x00000003
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT             0
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT           0x00000000
+
+/***************************************************************************
+ *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK                    0xfe000000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT                   25
+
+/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK               0x01000000
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK                    0x00fe0000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT                   17
+
+/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK              0x00010000
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK                    0x0000fe00
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT                   9
+
+/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK                     0x00000100
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT                    8
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT                  0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK                 0x000000ff
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT                0
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT              0x00000008
+
+/***************************************************************************
+ *CMD_AND_MODE_BYTE - Command and Mode Data Register
+ ***************************************************************************/
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK                 0xff000000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT                24
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK            0x00ff0000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT           16
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT         0x00000000
+
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK                 0x0000ff00
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT                8
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK             0x000000ff
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT            0
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT          0x0000000b
+
+/***************************************************************************
+ *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
+ ***************************************************************************/
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0x00000000
+
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK        0x00ffffff
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT       0
+
+/***************************************************************************
+ *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK               0xfff00000
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT              20
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT            0x00000000
+
+/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK                    0x000fffff
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT                  1
+
+/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK             0x00000001
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT            0
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT          0x00000000
+
+/***************************************************************************
+ *BSPI_PIO_MODE_ENABLE - BSPI Pin  Programmed IO Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK              0xfffffffe
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT             1
+
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK          0x00000001
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT         0
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT       0x00000000
+
+/***************************************************************************
+ *BSPI_PIO_IODIR - BSPI Pin  Programmed IO Mode Direction Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK                    0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT                   3
+
+/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT              0x00000003
+
+/***************************************************************************
+ *BSPI_PIO_DATA - BSPI Pin  Programmed IO Mode Data Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK                     0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT                    3
+
+/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT              0x00000000
+
+#endif /* #ifndef BCHP_BSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_bspi_raf.h b/include/linux/brcmstb/7429b0/bchp_bspi_raf.h
new file mode 100644
index 0000000..1793ba9
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_bspi_raf.h
@@ -0,0 +1,160 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:17 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_RAF_H__
+#define BCHP_BSPI_RAF_H__
+
+/***************************************************************************
+ *BSPI_RAF - Public Linear Read BSPI Pipe Registers
+ ***************************************************************************/
+#define BCHP_BSPI_RAF_START_ADDR                 0x00413100 /* Physical Starting Address Location in Flash device */
+#define BCHP_BSPI_RAF_NUM_WORDS                  0x00413104 /* Number of Words to be fetched */
+#define BCHP_BSPI_RAF_CTRL                       0x00413108 /* RAF Session Control Register */
+#define BCHP_BSPI_RAF_FULLNESS                   0x0041310c /* Fullness indicator for the read ahead buffer */
+#define BCHP_BSPI_RAF_WATERMARK                  0x00413110 /* Watermark level in the read ahead buffer that triggers an interrupt */
+#define BCHP_BSPI_RAF_STATUS                     0x00413114 /* Linear Read Status Register */
+#define BCHP_BSPI_RAF_READ_DATA                  0x00413118 /* Read data from Raf-buffer */
+#define BCHP_BSPI_RAF_WORD_CNT                   0x0041311c /* Current number of words fetched from Flash */
+#define BCHP_BSPI_RAF_CURR_ADDR                  0x00413120 /* Current read address for the linear read session */
+
+/***************************************************************************
+ *START_ADDR - Physical Starting Address Location in Flash device
+ ***************************************************************************/
+/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK                   0xffffffff
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT                  0
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT                0x00000000
+
+/***************************************************************************
+ *NUM_WORDS - Number of Words to be fetched
+ ***************************************************************************/
+/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK                      0xffffffff
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT                     0
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *CTRL - RAF Session Control Register
+ ***************************************************************************/
+/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT                         2
+
+/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
+#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK                              0x00000002
+#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT                             1
+#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT                           0x00000000
+
+/* BSPI_RAF :: CTRL :: START [00:00] */
+#define BCHP_BSPI_RAF_CTRL_START_MASK                              0x00000001
+#define BCHP_BSPI_RAF_CTRL_START_SHIFT                             0
+#define BCHP_BSPI_RAF_CTRL_START_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *FULLNESS - Fullness indicator for the read ahead buffer
+ ***************************************************************************/
+/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK                      0xffffff80
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT                     7
+
+/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK                       0x0000007f
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT                      0
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
+ ***************************************************************************/
+/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK                     0xfffffffc
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT                    2
+
+/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK            0x00000003
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT           0
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STATUS - Linear Read Status Register
+ ***************************************************************************/
+/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
+#define BCHP_BSPI_RAF_STATUS_reserved0_MASK                        0xfffffff8
+#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT                       3
+
+/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK                        0x00000004
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT                       2
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT                     0x00000000
+
+/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK                       0x00000002
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT                      1
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT                    0x00000001
+
+/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK                     0x00000001
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT                    0
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *READ_DATA - Read data from Raf-buffer
+ ***************************************************************************/
+/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
+#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK                          0xffffffff
+#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT                         0
+#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *WORD_CNT - Current number of words fetched from Flash
+ ***************************************************************************/
+/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK             0xffffffff
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT            0
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *CURR_ADDR - Current read address for the linear read session
+ ***************************************************************************/
+/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK               0xffffffff
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT              0
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT            0x00000000
+
+#endif /* #ifndef BCHP_BSPI_RAF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_clkgen.h b/include/linux/brcmstb/7429b0/bchp_clkgen.h
new file mode 100644
index 0000000..afb171f
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_clkgen.h
@@ -0,0 +1,7036 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:15 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_CLKGEN_H__
+#define BCHP_CLKGEN_H__
+
+/***************************************************************************
+ *CLKGEN - clkgen registers
+ ***************************************************************************/
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL       0x00420000 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV           0x00420004 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN          0x00420008 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS   0x0042000c /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN         0x00420010 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET         0x00420014 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x00420018 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x0042001c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS        0x00420020 /* Test Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL       0x00420024 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV           0x00420028 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN          0x0042002c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS   0x00420030 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN         0x00420034 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET         0x00420038 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x0042003c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x00420040 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS        0x00420044 /* Test Status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0 0x00420048 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1 0x0042004c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2 0x00420050 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL          0x00420054 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV              0x00420058 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN             0x0042005c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRDN        0x00420060 /* LDO Powerdowns */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS      0x00420064 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC             0x00420068 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2            0x0042006c /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN            0x00420070 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET            0x00420074 /* Resets */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH 0x00420078 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW 0x0042007c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS           0x00420080 /* Test Status */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 0x00420084 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 0x00420088 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL         0x0042008c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV             0x00420090 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN            0x00420094 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LDO_PWRDN       0x00420098 /* LDO Powerdowns */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS     0x0042009c /* Lock Status */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC            0x004200a0 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2           0x004200a4 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN           0x004200a8 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET           0x004200ac /* Resets */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x004200b0 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x004200b4 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS          0x004200b8 /* Test Status */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 0x004200bc /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 0x004200c0 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 0x004200c4 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 0x004200c8 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 0x004200cc /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 0x004200d0 /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL         0x004200d4 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV             0x004200d8 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN            0x004200dc /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRDN       0x004200e0 /* LDO Powerdowns */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS     0x004200e4 /* Lock Status */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC            0x004200e8 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2           0x004200ec /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN           0x004200f0 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET           0x004200f4 /* Resets */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH 0x004200f8 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW 0x004200fc /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS          0x00420100 /* Test Status */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 0x00420104 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL        0x00420108 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV            0x0042010c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN           0x00420110 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRDN      0x00420114 /* LDO Powerdowns */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS    0x00420118 /* Lock Status */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC           0x0042011c /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2          0x00420120 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN          0x00420124 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET          0x00420128 /* Resets */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH 0x0042012c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW 0x00420130 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS         0x00420134 /* Test Status */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0 0x00420138 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CONTROL          0x0042013c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV              0x00420140 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC             0x00420144 /* Fractional */
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN             0x00420148 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS      0x0042014c /* Lock Status */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC             0x00420150 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SC0_PLL_PWRDN            0x00420154 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET            0x00420158 /* Resets */
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH 0x0042015c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW 0x00420160 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS           0x00420164 /* Test Status */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0 0x00420168 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CONTROL          0x0042016c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV              0x00420170 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC             0x00420174 /* Fractional */
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN             0x00420178 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS      0x0042017c /* Lock Status */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC             0x00420180 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SC1_PLL_PWRDN            0x00420184 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET            0x00420188 /* Resets */
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH 0x0042018c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW 0x00420190 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS           0x00420194 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x00420198 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x0042019c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x004201a0 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x004201a4 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x004201a8 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x004201ac /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL         0x004201b0 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV             0x004201b4 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN            0x004201b8 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRDN       0x004201bc /* LDO Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS     0x004201c0 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC            0x004201c4 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2           0x004201c8 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN           0x004201cc /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET           0x004201d0 /* Resets */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x004201d4 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x004201d8 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS          0x004201dc /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 0x004201e0 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 0x004201e4 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 0x004201e8 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 0x004201ec /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL         0x004201f0 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV             0x004201f4 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN            0x004201f8 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LDO_PWRDN       0x004201fc /* LDO Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS     0x00420200 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC            0x00420204 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2           0x00420208 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN           0x0042020c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET           0x00420210 /* Resets */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH 0x00420214 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW 0x00420218 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS          0x0042021c /* Test Status */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 0x00420220 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 0x00420224 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 0x00420228 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL        0x0042022c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV            0x00420230 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC           0x00420234 /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN           0x00420238 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS    0x0042023c /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC           0x00420240 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN          0x00420244 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET          0x00420248 /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH 0x0042024c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW 0x00420250 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS         0x00420254 /* Status */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 0x00420258 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 0x0042025c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 0x00420260 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL        0x00420264 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV            0x00420268 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC           0x0042026c /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN           0x00420270 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS    0x00420274 /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC           0x00420278 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN          0x0042027c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET          0x00420280 /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH 0x00420284 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW 0x00420288 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS         0x0042028c /* Test Status */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE    0x00420290 /* Bvn top inst clock enable */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS 0x00420294 /* Clock Enable Status */
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE 0x00420298 /* Bvn top inst memory standby enable */
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY 0x0042029c /* Bvn top inst power switch memory */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE         0x004202a0 /* Disable CLKGEN's clocks */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS  0x004202a4 /* Clock Disable Status */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL        0x004202a8 /* Clock Monitor Control */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT      0x004202ac /* Clock Monitor Max Reference Count */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER    0x004202b0 /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE       0x004202b4 /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER   0x004202b8 /* Clock Monitor View Counter */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE  0x004202bc /* Disable CORE_XPT_INST's clocks */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS 0x004202c0 /* Clock Disable Status */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE   0x004202c4 /* Core xpt inst clock enable */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS 0x004202c8 /* Clock Enable Status */
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE 0x004202cc /* Core xpt inst memory standby enable */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK  0x004202d0 /* Core xpt inst observe clock */
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY 0x004202d4 /* Core xpt inst power switch memory */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0 0x004202d8 /* Disable DUAL_GENET_TOP_RGMII_INST's GENET0 clocks */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_STATUS 0x004202dc /* Clock Disable Status */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE 0x004202e0 /* Dual genet top rgmii inst clock enable */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 0x004202e4 /* Dual genet top rgmii inst clock enable genet0 */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS 0x004202e8 /* Clock Enable Status */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 0x004202ec /* Dual genet top rgmii inst clock enable genet1 */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS 0x004202f0 /* Clock Enable Status */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS 0x004202f4 /* Clock Enable Status */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0 0x004202f8 /* Dual genet top rgmii inst clock select genet0 */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1 0x004202fc /* Dual genet top rgmii inst clock select genet1 */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK 0x00420300 /* Dual genet top rgmii inst observe clock */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE    0x00420304 /* Disable DVP_HR_INST's clocks */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS 0x00420308 /* Clock Disable Status */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE     0x0042030c /* Dvp hr inst clock enable */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS 0x00420310 /* Clock Enable Status */
+#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE 0x00420314 /* Dvp hr inst memory standby enable */
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK    0x00420318 /* Dvp hr inst observe clock */
+#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY 0x0042031c /* Dvp hr inst power switch memory */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE    0x00420320 /* Disable DVP_HT_INST's clocks */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS 0x00420324 /* Clock Disable Status */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE     0x00420328 /* Dvp ht inst clock enable */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS 0x0042032c /* Clock Enable Status */
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE           0x00420330 /* Dvp ht inst enable */
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE 0x00420334 /* Dvp ht inst memory standby enable */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK    0x00420338 /* Dvp ht inst observe clock */
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY 0x0042033c /* Dvp ht inst power switch memory */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE   0x00420340 /* Graphics inst clock enable */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS 0x00420344 /* Clock Enable Status */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_V3D 0x00420348 /* Graphics inst clock enable v3d */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_V3D_STATUS 0x0042034c /* Clock Enable Status */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE 0x00420350 /* Graphics inst memory standby enable */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK  0x00420354 /* Graphics inst observe clock */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY 0x00420358 /* Graphics inst power switch memory */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE       0x0042035c /* Disable HIF_INST's clocks */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS 0x00420360 /* Clock Disable Status */
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE 0x00420364 /* Hif inst memory standby enable */
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK       0x00420368 /* Hif inst observe clock */
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY 0x0042036c /* Hif inst power switch memory */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT          0x00420370 /* Mux selects for Internal clocks */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE  0x00420374 /* Memsys 32 inst clock enable */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_STATUS 0x00420378 /* Clock Enable Status */
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE 0x0042037c /* Memsys 32 inst memory standby enable */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK 0x00420380 /* Memsys 32 inst observe clock */
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY 0x00420384 /* Memsys 32 inst power switch memory */
+#define BCHP_CLKGEN_MEMSYS_32_INST_STATUS        0x00420388 /* Memsys 32 inst status */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE   0x0042038c /* Moca top inst clock enable */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_STATUS 0x00420390 /* Clock Enable Status */
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE 0x00420394 /* Moca top inst memory standby enable */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK  0x00420398 /* Moca top inst observe clock */
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY 0x0042039c /* Moca top inst power switch memory */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION        0x004203a0 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE            0x004203a4 /* Disable PAD's clocks */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS     0x004203a8 /* Clock Disable Status */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION   0x004203ac /* Select observation clk */
+#define BCHP_CLKGEN_PAD_MUX_SELECT               0x004203b0 /* Mux selects for Pad clocks */
+#define BCHP_CLKGEN_PAD_OBSRV1_OBSERVATION       0x004203b4 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION       0x004203b8 /* Select observation clk */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS  0x004203bc /* PLL_AUDIO0 Reset Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS  0x004203c0 /* PLL_AUDIO1 Reset Status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS     0x004203c4 /* PLL_AVD Reset Status */
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL       0x004203c8 /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST 0x004203cc /* PLL_MIPS Glitchless Clock Switching */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS 0x004203d0 /* PLL_MIPS Glitchless Switching */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS    0x004203d4 /* PLL_MIPS Reset Status */
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL      0x004203d8 /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS    0x004203dc /* PLL_MOCA Reset Status */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS   0x004203e0 /* PLL_RAAGA Reset Status */
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL     0x004203e4 /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS     0x004203e8 /* PLL_SC0 Reset Status */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS     0x004203ec /* PLL_SC1 Reset Status */
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE           0x004203f0 /* Disable */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS    0x004203f4 /* PLL_SYS1 Reset Status */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS   0x004203f8 /* PLL_VCXO0 Reset Status */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS   0x004203fc /* PLL_VCXO1 Reset Status */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL       0x00420400 /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x00420404 /* PLL Alive in Standby Mode */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP           0x00420408 /* Power management LDO PLL */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM        0x0042040c /* Power management LDO PLL state machine */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE 0x00420410 /* Raaga dsp top inst clock enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_STATUS 0x00420414 /* Clock Enable Status */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE 0x00420418 /* Raaga dsp top inst memory standby enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK 0x0042041c /* Raaga dsp top inst observe clock */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY 0x00420420 /* Raaga dsp top inst power switch memory */
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE    0x00420424 /* Rfm top inst clock enable */
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS 0x00420428 /* Clock Enable Status */
+#define BCHP_CLKGEN_RFM_TOP_INST_MEMORY_STANDBY_ENABLE 0x0042042c /* Rfm top inst memory standby enable */
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK   0x00420430 /* Rfm top inst observe clock */
+#define BCHP_CLKGEN_RFM_TOP_INST_POWER_SWITCH_MEMORY 0x00420434 /* Rfm top inst power switch memory */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE 0x00420438 /* Disable SATA3_TOP_INST's clocks */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS 0x0042043c /* Clock Disable Status */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE  0x00420440 /* Sata3 top inst clock enable */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS 0x00420444 /* Clock Enable Status */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT  0x00420448 /* Sata3 top inst clock select */
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE 0x0042044c /* Sata3 top inst memory standby enable */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK 0x00420450 /* Sata3 top inst observe clock */
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY 0x00420454 /* Sata3 top inst power switch memory */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE     0x00420458 /* Sectop inst clock enable */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS 0x0042045c /* Clock Enable Status */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK    0x00420460 /* Sectop inst observe clock */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT         0x00420464 /* Mux selects for Smartcard clocks */
+#define BCHP_CLKGEN_SPARE                        0x00420468 /* Spares */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE   0x0042046c /* Svd0 top inst clock enable */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS 0x00420470 /* Clock Enable Status */
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE 0x00420474 /* Svd0 top inst memory standby enable */
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY 0x00420478 /* Svd0 top inst power switch memory */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK   0x0042047c /* Sys aon inst observe clock */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE  0x00420480 /* Disable SYS_CTRL_INST's clocks */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS 0x00420484 /* Clock Disable Status */
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE 0x00420488 /* Sys ctrl inst memory standby enable */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK  0x0042048c /* Sys ctrl inst observe clock */
+#define BCHP_CLKGEN_TESTPORT                     0x00420490 /* Special Testport Controls */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE      0x00420494 /* Disable USB0_INST's clocks */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_STATUS 0x00420498 /* Clock Disable Status */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE       0x0042049c /* Usb0 inst clock enable */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_STATUS 0x004204a0 /* Clock Enable Status */
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE 0x004204a4 /* Usb0 inst memory standby enable */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK      0x004204a8 /* Usb0 inst observe clock */
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY 0x004204ac /* Usb0 inst power switch memory */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE      0x004204b0 /* Disable USB1_INST's clocks */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_STATUS 0x004204b4 /* Clock Disable Status */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE       0x004204b8 /* Usb1 inst clock enable */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_STATUS 0x004204bc /* Clock Enable Status */
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE 0x004204c0 /* Usb1 inst memory standby enable */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK      0x004204c4 /* Usb1 inst observe clock */
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY 0x004204c8 /* Usb1 inst power switch memory */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE 0x004204cc /* Disable VEC_AIO_TOP_INST's clocks */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS 0x004204d0 /* Clock Disable Status */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO 0x004204d4 /* Vec aio top inst clock enable aio */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS 0x004204d8 /* Clock Enable Status */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC 0x004204dc /* Vec aio top inst clock enable vec */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS 0x004204e0 /* Clock Enable Status */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO 0x004204e4 /* Vec aio top inst memory standby enable aio */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC 0x004204e8 /* Vec aio top inst memory standby enable vec */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO 0x004204ec /* Vec aio top inst observe clock aio */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC 0x004204f0 /* Vec aio top inst observe clock vec */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO 0x004204f4 /* Vec aio top inst power switch memory aio */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC 0x004204f8 /* Vec aio top inst power switch memory vec */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE  0x004204fc /* Disable ZCPU_TOP_INST's clocks */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_STATUS 0x00420500 /* Clock Disable Status */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE   0x00420504 /* Zcpu top inst clock enable */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_STATUS 0x00420508 /* Clock Enable Status */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK  0x0042050c /* Zcpu top inst observe clock */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS 0x00420510 /* Bypass GENET_TOP_DUAL_RGMII_INST's clocks */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1 0x00420514 /* Disable DUAL_GENET_TOP_RGMII_INST's GENET1 clocks */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_STATUS 0x00420518 /* Clock Disable Status */
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT                0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000001
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT                0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000001
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT   1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT   1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000064
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PLL_AVD_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_AVD_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_SHIFT              0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AVD_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_MASK                 0xffffe000
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_SHIFT                13
+
+/* CLKGEN :: PLL_AVD_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_MASK                      0x00001c00
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_SHIFT                     10
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_DEFAULT                   0x00000003
+
+/* CLKGEN :: PLL_AVD_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_MASK                  0x000003ff
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_SHIFT                 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_DEFAULT               0x0000008e
+
+/***************************************************************************
+ *PLL_AVD_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_MASK                0xff000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_SHIFT               24
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x000000e0
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       5
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     0x00000002
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_PLL_LDO_PWRDN - LDO Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_LDO_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRDN_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRDN_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_AVD_PLL_LDO_PWRDN :: LDO_PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRDN_LDO_PWRDN_PLL_MASK       0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRDN_LDO_PWRDN_PLL_SHIFT      0
+#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRDN_LDO_PWRDN_PLL_DEFAULT    0x00000000
+
+/***************************************************************************
+ *PLL_AVD_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_MASK         0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_SHIFT        1
+
+/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_SHIFT             0
+
+/***************************************************************************
+ *PLL_AVD_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_reserved0_MASK                0x80000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_reserved0_SHIFT               31
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_MASK                  0x60000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_SHIFT                 29
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_MASK                  0x10000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_SHIFT                 28
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_MASK              0x08000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_SHIFT             27
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_MASK              0x07000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_SHIFT             24
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__MASK              0x00800000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__SHIFT             23
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_MASK                0x00600000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_SHIFT               21
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_MASK                0x00100000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_SHIFT               20
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_MASK                 0x000c0000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_SHIFT                18
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_MASK               0x00020000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_SHIFT              17
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_MASK              0x00010000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_SHIFT             16
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_MASK              0x00008000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_SHIFT             15
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_MASK                0x00004000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_SHIFT               14
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  13
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00001ffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         1
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_SHIFT                0
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_AVD_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_AVD_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_DEFAULT                0x00000000
+
+/***************************************************************************
+ *PLL_AVD_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_AVD_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_SHIFT              0
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AVD_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_MASK               0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_SHIFT              2
+
+/* CLKGEN :: PLL_AVD_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_MASK                  0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_SHIFT                 1
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_SHIFT                 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_MASK              0xfffff000
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_SHIFT             12
+
+/* CLKGEN :: PLL_AVD_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_SHIFT           0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000064
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PLL_MIPS_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_MIPS_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_DEFAULT                  0x00000003
+
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_DEFAULT              0x00000091
+
+/***************************************************************************
+ *PLL_MIPS_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000002
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_LDO_PWRDN - LDO Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_LDO_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LDO_PWRDN_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LDO_PWRDN_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_MIPS_PLL_LDO_PWRDN :: LDO_PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LDO_PWRDN_LDO_PWRDN_PLL_MASK      0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LDO_PWRDN_LDO_PWRDN_PLL_SHIFT     0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LDO_PWRDN_LDO_PWRDN_PLL_DEFAULT   0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MIPS_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000c
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000024
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000048
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000024
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x0000004b
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_MOCA_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_DEFAULT                  0x00000003
+
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_DEFAULT              0x000000c8
+
+/***************************************************************************
+ *PLL_MOCA_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000002
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_LDO_PWRDN - LDO Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_LDO_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRDN_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRDN_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_MOCA_PLL_LDO_PWRDN :: LDO_PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRDN_LDO_PWRDN_PLL_MASK      0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRDN_LDO_PWRDN_PLL_SHIFT     0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRDN_LDO_PWRDN_PLL_DEFAULT   0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_DEFAULT              0x00000001
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_DEFAULT             0x00000002
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MOCA_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_MOCA_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_RAAGA_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_SHIFT            0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_MASK               0xffffe000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_SHIFT              13
+
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_MASK                    0x00001c00
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_SHIFT                   10
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_DEFAULT                 0x00000002
+
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_MASK                0x000003ff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_SHIFT               0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_DEFAULT             0x0000008f
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_MASK              0xff000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_SHIFT             24
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x000000e0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     5
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000002
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_LDO_PWRDN - LDO Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_LDO_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRDN_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRDN_reserved0_SHIFT        1
+
+/* CLKGEN :: PLL_RAAGA_PLL_LDO_PWRDN :: LDO_PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRDN_LDO_PWRDN_PLL_MASK     0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRDN_LDO_PWRDN_PLL_SHIFT    0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRDN_LDO_PWRDN_PLL_DEFAULT  0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_MASK       0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT      1
+
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_SHIFT           0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_reserved0_MASK              0x80000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_reserved0_SHIFT             31
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_MASK                0x60000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_SHIFT               29
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_MASK                0x10000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_SHIFT               28
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_DEFAULT             0x00000001
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_SHIFT           27
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_MASK            0x07000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_SHIFT           24
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__MASK            0x00800000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__SHIFT           23
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_MASK              0x00600000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_SHIFT             21
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_MASK              0x00100000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_SHIFT             20
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_MASK               0x000c0000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_SHIFT              18
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_DEFAULT            0x00000002
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_MASK             0x00020000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_SHIFT            17
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_MASK            0x00010000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_SHIFT           16
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_MASK            0x00008000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_SHIFT           15
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_MASK              0x00004000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_SHIFT             14
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00001ffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_SHIFT              0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_SHIFT                0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_RAAGA_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_SHIFT            0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_MASK             0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_SHIFT            2
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_MASK                0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_SHIFT               1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_SHIFT               0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_MASK            0xfffff000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_SHIFT           12
+
+/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_SHIFT         0
+
+/***************************************************************************
+ *PLL_SC0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000030
+
+/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CONTROL_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_SC0_PLL_CONTROL_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_SC0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CONTROL_REF_SEL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC0_PLL_CONTROL_REF_SEL_SHIFT              0
+#define BCHP_CLKGEN_PLL_SC0_PLL_CONTROL_REF_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_reserved0_MASK                 0xffffe000
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_reserved0_SHIFT                13
+
+/* CLKGEN :: PLL_SC0_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_MASK                      0x00001c00
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_SHIFT                     10
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_DEFAULT                   0x00000001
+
+/* CLKGEN :: PLL_SC0_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_MASK                  0x000003ff
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_DEFAULT               0x00000018
+
+/***************************************************************************
+ *PLL_SC0_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_reserved0_MASK                0xfff00000
+#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_reserved0_SHIFT               20
+
+/* CLKGEN :: PLL_SC0_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_MASK             0x000fffff
+#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_SHIFT            0
+#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_reserved0_MASK                0xff000000
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_reserved0_SHIFT               24
+
+/* CLKGEN :: PLL_SC0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x000000e0
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       5
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     0x00000001
+
+/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_SC0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_reserved0_SHIFT        1
+
+/* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_SHIFT             0
+
+/***************************************************************************
+ *PLL_SC0_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_reserved0_MASK                0xc0000000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_reserved0_SHIFT               30
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_DLY_MASK                  0x30000000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_DLY_SHIFT                 28
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_DLY_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCODIV2_POST_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCODIV2_POST_SHIFT            27
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCODIV2_POST_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCODIV2_MASK                  0x04000000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCODIV2_SHIFT                 26
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCODIV2_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_MASK              0x02000000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_SHIFT             25
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_MASK              0x01c00000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_SHIFT             22
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET__MASK              0x00200000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET__SHIFT             21
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET__DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_MASK                0x00180000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_SHIFT               19
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_REFCLKOUT_MASK                0x00040000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_REFCLKOUT_SHIFT               18
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_REFCLKOUT_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_MASK                 0x00030000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_SHIFT                16
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_MDIV_RELOCK_MASK              0x00008000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_MDIV_RELOCK_SHIFT             15
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_MDIV_RELOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_MASK                0x00004000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_SHIFT               14
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00002000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  13
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00001ffe
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         1
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_AUX_CTRL_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_AUX_CTRL_SHIFT                0
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_AUX_CTRL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_PWRDN_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_SC0_PLL_PWRDN_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_SC0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_PWRDN_PWRDN_PLL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC0_PLL_PWRDN_PWRDN_PLL_SHIFT              0
+#define BCHP_CLKGEN_PLL_SC0_PLL_PWRDN_PWRDN_PLL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_reserved0_MASK               0xfffffffc
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_reserved0_SHIFT              2
+
+/* CLKGEN :: PLL_SC0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_MASK                  0x00000002
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_SHIFT                 1
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_reserved0_MASK              0xfffff000
+#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_reserved0_SHIFT             12
+
+/* CLKGEN :: PLL_SC0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
+#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_TEST_STATUS_SHIFT           0
+
+/***************************************************************************
+ *PLL_SC1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000030
+
+/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CONTROL_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_SC1_PLL_CONTROL_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_SC1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CONTROL_REF_SEL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC1_PLL_CONTROL_REF_SEL_SHIFT              0
+#define BCHP_CLKGEN_PLL_SC1_PLL_CONTROL_REF_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_reserved0_MASK                 0xffffe000
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_reserved0_SHIFT                13
+
+/* CLKGEN :: PLL_SC1_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_MASK                      0x00001c00
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_SHIFT                     10
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_DEFAULT                   0x00000001
+
+/* CLKGEN :: PLL_SC1_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_MASK                  0x000003ff
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_DEFAULT               0x00000018
+
+/***************************************************************************
+ *PLL_SC1_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_reserved0_MASK                0xfff00000
+#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_reserved0_SHIFT               20
+
+/* CLKGEN :: PLL_SC1_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_MASK             0x000fffff
+#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_SHIFT            0
+#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_reserved0_MASK                0xff000000
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_reserved0_SHIFT               24
+
+/* CLKGEN :: PLL_SC1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x000000e0
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       5
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     0x00000001
+
+/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_SC1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_reserved0_SHIFT        1
+
+/* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_SHIFT             0
+
+/***************************************************************************
+ *PLL_SC1_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_reserved0_MASK                0xc0000000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_reserved0_SHIFT               30
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_DLY_MASK                  0x30000000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_DLY_SHIFT                 28
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_DLY_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCODIV2_POST_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCODIV2_POST_SHIFT            27
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCODIV2_POST_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCODIV2_MASK                  0x04000000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCODIV2_SHIFT                 26
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCODIV2_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_MASK              0x02000000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_SHIFT             25
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_MASK              0x01c00000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_SHIFT             22
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET__MASK              0x00200000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET__SHIFT             21
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET__DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_MASK                0x00180000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_SHIFT               19
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_REFCLKOUT_MASK                0x00040000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_REFCLKOUT_SHIFT               18
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_REFCLKOUT_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_MASK                 0x00030000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_SHIFT                16
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_MDIV_RELOCK_MASK              0x00008000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_MDIV_RELOCK_SHIFT             15
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_MDIV_RELOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_MASK                0x00004000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_SHIFT               14
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00002000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  13
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00001ffe
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         1
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_AUX_CTRL_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_AUX_CTRL_SHIFT                0
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_AUX_CTRL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_PWRDN_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_SC1_PLL_PWRDN_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_SC1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_PWRDN_PWRDN_PLL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC1_PLL_PWRDN_PWRDN_PLL_SHIFT              0
+#define BCHP_CLKGEN_PLL_SC1_PLL_PWRDN_PWRDN_PLL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_reserved0_MASK               0xfffffffc
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_reserved0_SHIFT              2
+
+/* CLKGEN :: PLL_SC1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_MASK                  0x00000002
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_SHIFT                 1
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_reserved0_MASK              0xfffff000
+#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_reserved0_SHIFT             12
+
+/* CLKGEN :: PLL_SC1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
+#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_TEST_STATUS_SHIFT           0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000012
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000c
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000051
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000e
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x0000000a
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x0000000a
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT                  0x00000001
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT              0x00000048
+
+/***************************************************************************
+ *PLL_SYS0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x0000000a
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000003
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_LDO_PWRDN - LDO Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_LDO_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRDN_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRDN_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_SYS0_PLL_LDO_PWRDN :: LDO_PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRDN_LDO_PWRDN_PLL_MASK      0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRDN_LDO_PWRDN_PLL_SHIFT     0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRDN_LDO_PWRDN_PLL_DEFAULT   0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT              0x00000001
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT             0x00000002
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_RESET :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_RESET :: RESETD [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000012
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000005a
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000001c
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_DEFAULT                  0x00000003
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_DEFAULT              0x0000007d
+
+/***************************************************************************
+ *PLL_SYS1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000002
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_LDO_PWRDN - LDO Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_LDO_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LDO_PWRDN_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LDO_PWRDN_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_SYS1_PLL_LDO_PWRDN :: LDO_PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LDO_PWRDN_LDO_PWRDN_PLL_MASK      0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LDO_PWRDN_LDO_PWRDN_PLL_SHIFT     0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LDO_PWRDN_LDO_PWRDN_PLL_DEFAULT   0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_POR_BYPASS_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_LDO_REF_SEL_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2_SPARE_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000004b
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_VCXO0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_REF_SEL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_REF_SEL_SHIFT            0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_REF_SEL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_reserved0_MASK               0xffffe000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_reserved0_SHIFT              13
+
+/* CLKGEN :: PLL_VCXO0_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_MASK                    0x00001c00
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_SHIFT                   10
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_DEFAULT                 0x00000002
+
+/* CLKGEN :: PLL_VCXO0_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_MASK                0x000003ff
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_DEFAULT             0x00000040
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_reserved0_MASK              0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_reserved0_SHIFT             20
+
+/* CLKGEN :: PLL_VCXO0_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_MASK           0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_SHIFT          0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_reserved0_MASK              0xff000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_reserved0_SHIFT             24
+
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x000000e0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     5
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000001
+
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_reserved0_SHIFT      1
+
+/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_SHIFT           0
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_reserved0_MASK              0xc0000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_reserved0_SHIFT             30
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DLY_MASK                0x30000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DLY_SHIFT               28
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DLY_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_POST_MASK           0x08000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_POST_SHIFT          27
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_POST_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_MASK                0x04000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_SHIFT               26
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_MASK            0x02000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_SHIFT           25
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_MASK            0x01c00000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_SHIFT           22
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET__MASK            0x00200000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET__SHIFT           21
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET__DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_MASK              0x00180000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_SHIFT             19
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REFCLKOUT_MASK              0x00040000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REFCLKOUT_SHIFT             18
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REFCLKOUT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_MASK               0x00030000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_SHIFT              16
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_MDIV_RELOCK_MASK            0x00008000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_MDIV_RELOCK_SHIFT           15
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_MDIV_RELOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_MASK              0x00004000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_SHIFT             14
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00001ffe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_SHIFT              0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_VCXO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_PWRDN_PLL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_PWRDN_PLL_SHIFT            0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_PWRDN_PLL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_reserved0_MASK             0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_reserved0_SHIFT            2
+
+/* CLKGEN :: PLL_VCXO0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_MASK                0x00000002
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_SHIFT               1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_reserved0_MASK            0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_reserved0_SHIFT           12
+
+/* CLKGEN :: PLL_VCXO0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_TEST_STATUS_SHIFT         0
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000004b
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_VCXO1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_REF_SEL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_REF_SEL_SHIFT            0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_REF_SEL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_reserved0_MASK               0xffffe000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_reserved0_SHIFT              13
+
+/* CLKGEN :: PLL_VCXO1_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_MASK                    0x00001c00
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_SHIFT                   10
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_DEFAULT                 0x00000002
+
+/* CLKGEN :: PLL_VCXO1_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_MASK                0x000003ff
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_DEFAULT             0x00000040
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_reserved0_MASK              0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_reserved0_SHIFT             20
+
+/* CLKGEN :: PLL_VCXO1_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_MASK           0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_SHIFT          0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_reserved0_MASK              0xff000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_reserved0_SHIFT             24
+
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x000000e0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     5
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000001
+
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_reserved0_SHIFT      1
+
+/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_SHIFT           0
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_reserved0_MASK              0xc0000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_reserved0_SHIFT             30
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DLY_MASK                0x30000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DLY_SHIFT               28
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DLY_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_POST_MASK           0x08000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_POST_SHIFT          27
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_POST_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_MASK                0x04000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_SHIFT               26
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_MASK            0x02000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_SHIFT           25
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_MASK            0x01c00000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_SHIFT           22
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET__MASK            0x00200000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET__SHIFT           21
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET__DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_MASK              0x00180000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_SHIFT             19
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REFCLKOUT_MASK              0x00040000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REFCLKOUT_SHIFT             18
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REFCLKOUT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_MASK               0x00030000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_SHIFT              16
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_MDIV_RELOCK_MASK            0x00008000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_MDIV_RELOCK_SHIFT           15
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_MDIV_RELOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_MASK              0x00004000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_SHIFT             14
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00001ffe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_SHIFT              0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_VCXO1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_PWRDN_PLL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_PWRDN_PLL_SHIFT            0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_PWRDN_PLL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_reserved0_MASK             0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_reserved0_SHIFT            2
+
+/* CLKGEN :: PLL_VCXO1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_MASK                0x00000002
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_SHIFT               1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_reserved0_MASK            0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_reserved0_SHIFT           12
+
+/* CLKGEN :: PLL_VCXO1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_TEST_STATUS_SHIFT         0
+
+/***************************************************************************
+ *BVN_TOP_INST_CLOCK_ENABLE - Bvn top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffff8
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      3
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *BVN_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_SCB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_216_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_216_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *BVN_TOP_INST_MEMORY_STANDBY_ENABLE - Bvn top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: BVN_TOP_INST_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BVN_TOP_INST_POWER_SWITCH_MEMORY - Bvn top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: BVN_TOP_INST_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks
+ ***************************************************************************/
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT           2
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_OSC_DIGITAL_CLOCK [01:01] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_AVS_CLOCK [00:00] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_MASK    0x00000001
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_SHIFT   0
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CLKGEN_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: DISABLE_OSC_DIGITAL_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_OSC_DIGITAL_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_OSC_DIGITAL_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: DISABLE_AVS_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_AVS_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_AVS_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_CONTROL - Clock Monitor Control
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT          4
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK   0x00000008
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT  3
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK    0x00000004
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT   2
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK      0x00000002
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT     1
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT   0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK  0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT         1
+
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK     0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT    0
+
+/***************************************************************************
+ *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_CLOCK_DISABLE - Disable CORE_XPT_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_MASK     0xffffffe0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_SHIFT    5
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:05] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 5
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_81_CLOCK_STATUS [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_81_CLOCK_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_81_CLOCK_STATUS_SHIFT 4
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_54_CLOCK_STATUS [03:03] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_54_CLOCK_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_54_CLOCK_STATUS_SHIFT 3
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_40P5_CLOCK_STATUS [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_40P5_CLOCK_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_40P5_CLOCK_STATUS_SHIFT 2
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_27_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_27_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_27_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_20P25_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_20P25_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_20P25_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_CLOCK_ENABLE - Core xpt inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffff8
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_SHIFT     3
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CORE_XPT_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_SCB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_216_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_216_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_MEMORY_STANDBY_ENABLE - Core xpt inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: CORE_XPT_INST_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_INST_OBSERVE_CLOCK - Core xpt inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_INST_POWER_SWITCH_MEMORY - Core xpt inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: CORE_XPT_INST_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0 - Disable DUAL_GENET_TOP_RGMII_INST's GENET0 clocks
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0 :: reserved0 [31:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_reserved0_SHIFT 5
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0 :: DISABLE_GENET_25MHZ_CLOCK [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_DISABLE_GENET_25MHZ_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_DISABLE_GENET_25MHZ_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_DISABLE_GENET_25MHZ_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0 :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0 :: DISABLE_GENET0_SYSTEM_PM_CLOCK [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0 :: DISABLE_GENET0_SYSTEM_FAST_CLOCK [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_DISABLE_GENET0_SYSTEM_FAST_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_DISABLE_GENET0_SYSTEM_FAST_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_DISABLE_GENET0_SYSTEM_FAST_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0 :: DISABLE_GENET0_ALWAYSON_CLOCK [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_DISABLE_GENET0_ALWAYSON_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_DISABLE_GENET0_ALWAYSON_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_DISABLE_GENET0_ALWAYSON_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_STATUS :: reserved0 [31:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_STATUS_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_STATUS_reserved0_SHIFT 5
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_STATUS :: DISABLE_GENET_25MHZ_CLOCK_STATUS [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_STATUS_DISABLE_GENET_25MHZ_CLOCK_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_STATUS_DISABLE_GENET_25MHZ_CLOCK_STATUS_SHIFT 4
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_STATUS :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_STATUS_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_STATUS_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS_SHIFT 3
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_STATUS :: DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_STATUS_DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_STATUS_DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS_SHIFT 2
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_STATUS :: DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_STATUS_DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_STATUS_DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_STATUS :: DISABLE_GENET0_ALWAYSON_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_STATUS_DISABLE_GENET0_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0_STATUS_DISABLE_GENET0_ALWAYSON_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE - Dual genet top rgmii inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 - Dual genet top rgmii inst clock enable genet0
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: reserved0 [31:09] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_reserved0_SHIFT 9
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0 [08:08] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_MASK 0x00000100
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_SHIFT 8
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0 [07:07] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_MASK 0x00000080
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_SHIFT 7
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_SCB_CLOCK_ENABLE_GENET0 [06:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_SCB_CLOCK_ENABLE_GENET0_MASK 0x00000040
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_SCB_CLOCK_ENABLE_GENET0_SHIFT 6
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_SCB_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_L2INTR_CLOCK_ENABLE_GENET0 [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_L2INTR_CLOCK_ENABLE_GENET0_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_L2INTR_CLOCK_ENABLE_GENET0_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_L2INTR_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_HFB_CLOCK_ENABLE_GENET0 [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_HFB_CLOCK_ENABLE_GENET0_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_HFB_CLOCK_ENABLE_GENET0_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_HFB_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_GMII_CLOCK_ENABLE_GENET0 [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GMII_CLOCK_ENABLE_GENET0_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GMII_CLOCK_ENABLE_GENET0_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GMII_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_EEE_CLOCK_ENABLE_GENET0 [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_EEE_CLOCK_ENABLE_GENET0_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_EEE_CLOCK_ENABLE_GENET0_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_EEE_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_CLK_250_CLOCK_ENABLE_GENET0 [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_CLK_250_CLOCK_ENABLE_GENET0_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_CLK_250_CLOCK_ENABLE_GENET0_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_CLK_250_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_108_CLOCK_ENABLE_GENET0 [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_108_CLOCK_ENABLE_GENET0_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_108_CLOCK_ENABLE_GENET0_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_108_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: reserved0 [31:09] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_reserved0_SHIFT 9
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_STATUS [08:08] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000100
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_STATUS_SHIFT 8
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_STATUS [07:07] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000080
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_STATUS_SHIFT 7
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_SCB_CLOCK_ENABLE_GENET0_STATUS [06:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_SCB_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000040
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_SCB_CLOCK_ENABLE_GENET0_STATUS_SHIFT 6
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_L2INTR_CLOCK_ENABLE_GENET0_STATUS [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_L2INTR_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_L2INTR_CLOCK_ENABLE_GENET0_STATUS_SHIFT 5
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_HFB_CLOCK_ENABLE_GENET0_STATUS [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_HFB_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_HFB_CLOCK_ENABLE_GENET0_STATUS_SHIFT 4
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_GMII_CLOCK_ENABLE_GENET0_STATUS [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_GMII_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_GMII_CLOCK_ENABLE_GENET0_STATUS_SHIFT 3
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_EEE_CLOCK_ENABLE_GENET0_STATUS [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_EEE_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_EEE_CLOCK_ENABLE_GENET0_STATUS_SHIFT 2
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_CLK_250_CLOCK_ENABLE_GENET0_STATUS [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_CLK_250_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_CLK_250_CLOCK_ENABLE_GENET0_STATUS_SHIFT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_108_CLOCK_ENABLE_GENET0_STATUS [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_108_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_108_CLOCK_ENABLE_GENET0_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 - Dual genet top rgmii inst clock enable genet1
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: reserved0 [31:08] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_reserved0_MASK 0xffffff00
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_reserved0_SHIFT 8
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1 [07:07] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_MASK 0x00000080
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_SHIFT 7
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1 [06:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_MASK 0x00000040
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_SHIFT 6
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_SCB_CLOCK_ENABLE_GENET1 [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_SCB_CLOCK_ENABLE_GENET1_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_SCB_CLOCK_ENABLE_GENET1_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_SCB_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_L2INTR_CLOCK_ENABLE_GENET1 [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_L2INTR_CLOCK_ENABLE_GENET1_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_L2INTR_CLOCK_ENABLE_GENET1_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_L2INTR_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_HFB_CLOCK_ENABLE_GENET1 [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_HFB_CLOCK_ENABLE_GENET1_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_HFB_CLOCK_ENABLE_GENET1_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_HFB_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_GMII_CLOCK_ENABLE_GENET1 [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GMII_CLOCK_ENABLE_GENET1_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GMII_CLOCK_ENABLE_GENET1_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GMII_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_EEE_CLOCK_ENABLE_GENET1 [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_EEE_CLOCK_ENABLE_GENET1_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_EEE_CLOCK_ENABLE_GENET1_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_EEE_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_108_CLOCK_ENABLE_GENET1 [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_108_CLOCK_ENABLE_GENET1_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_108_CLOCK_ENABLE_GENET1_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_108_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: reserved0 [31:08] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_reserved0_SHIFT 8
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_STATUS [07:07] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000080
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_STATUS_SHIFT 7
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_STATUS [06:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000040
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_STATUS_SHIFT 6
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_SCB_CLOCK_ENABLE_GENET1_STATUS [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_SCB_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_SCB_CLOCK_ENABLE_GENET1_STATUS_SHIFT 5
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_L2INTR_CLOCK_ENABLE_GENET1_STATUS [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_L2INTR_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_L2INTR_CLOCK_ENABLE_GENET1_STATUS_SHIFT 4
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_HFB_CLOCK_ENABLE_GENET1_STATUS [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_HFB_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_HFB_CLOCK_ENABLE_GENET1_STATUS_SHIFT 3
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_GMII_CLOCK_ENABLE_GENET1_STATUS [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_GMII_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_GMII_CLOCK_ENABLE_GENET1_STATUS_SHIFT 2
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_EEE_CLOCK_ENABLE_GENET1_STATUS [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_EEE_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_EEE_CLOCK_ENABLE_GENET1_STATUS_SHIFT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_108_CLOCK_ENABLE_GENET1_STATUS [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_108_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_108_CLOCK_ENABLE_GENET1_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS :: GENET_SCB_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET_SCB_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0 - Dual genet top rgmii inst clock select genet0
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0 :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_reserved0_SHIFT 2
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0 :: GENET0_GMII_CLOCK_SELECT_GENET0 [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_GMII_CLOCK_SELECT_GENET0_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_GMII_CLOCK_SELECT_GENET0_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_GMII_CLOCK_SELECT_GENET0_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0 :: GENET0_CLOCK_SELECT_GENET0 [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_CLOCK_SELECT_GENET0_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_CLOCK_SELECT_GENET0_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_CLOCK_SELECT_GENET0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1 - Dual genet top rgmii inst clock select genet1
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1 :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_reserved0_SHIFT 2
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1 :: GENET1_GMII_CLOCK_SELECT_GENET1 [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_GMII_CLOCK_SELECT_GENET1_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_GMII_CLOCK_SELECT_GENET1_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_GMII_CLOCK_SELECT_GENET1_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1 :: GENET1_CLOCK_SELECT_GENET1 [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_CLOCK_SELECT_GENET1_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_CLOCK_SELECT_GENET1_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_CLOCK_SELECT_GENET1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK - Dual genet top rgmii inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: GENET_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HR_INST_CLOCK_DISABLE - Disable DVP_HR_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE :: DISABLE_DVPHR_ALWAYSON_CLOCK [00:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HR_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE_STATUS :: DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DVP_HR_INST_CLOCK_ENABLE - Dvp hr inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_reserved0_MASK        0xffffffe0
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_reserved0_SHIFT       5
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_CLK_MAX_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_CLK_MAX_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_CLK_MAX_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_CLK_MAX_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_ALTERNATE_216_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_ALTERNATE2_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE2_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE2_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE2_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DVP_HR_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_CLK_MAX_CLOCK_ENABLE_STATUS [04:04] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_CLK_MAX_CLOCK_ENABLE_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_CLK_MAX_CLOCK_ENABLE_STATUS_SHIFT 4
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_ALTERNATE_216_CLOCK_ENABLE_STATUS [03:03] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_ALTERNATE_216_CLOCK_ENABLE_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_ALTERNATE_216_CLOCK_ENABLE_STATUS_SHIFT 3
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_ALTERNATE2_108_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_ALTERNATE2_108_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_ALTERNATE2_108_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_216_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_216_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DVP_HR_INST_MEMORY_STANDBY_ENABLE - Dvp hr inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: DVP_HR_INST_MEMORY_STANDBY_ENABLE :: DVPHR_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_DVPHR_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_DVPHR_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_DVPHR_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HR_INST_OBSERVE_CLOCK - Dvp hr inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HR_INST_POWER_SWITCH_MEMORY - Dvp hr inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: DVP_HR_INST_POWER_SWITCH_MEMORY :: DVPHR_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_DVPHR_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_DVPHR_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_DVPHR_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_INST_CLOCK_DISABLE - Disable DVP_HT_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE_STATUS :: DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DVP_HT_INST_CLOCK_ENABLE - Dvp ht inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffff8
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_SHIFT       3
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_ALTERNATE_216_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DVP_HT_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_ALTERNATE_216_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_ALTERNATE_216_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_ALTERNATE_216_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_216_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_216_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DVP_HT_INST_ENABLE - Dvp ht inst enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE_reserved0_SHIFT             2
+
+/* CLKGEN :: DVP_HT_INST_ENABLE :: DVPHT_CLK_VEC_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE_DVPHT_CLK_VEC_ENABLE_MASK   0x00000002
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE_DVPHT_CLK_VEC_ENABLE_SHIFT  1
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE_DVPHT_CLK_VEC_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_INST_ENABLE :: DVPHT_CLK_MAX_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE_DVPHT_CLK_MAX_ENABLE_MASK   0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE_DVPHT_CLK_MAX_ENABLE_SHIFT  0
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE_DVPHT_CLK_MAX_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DVP_HT_INST_MEMORY_STANDBY_ENABLE - Dvp ht inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: DVP_HT_INST_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_INST_OBSERVE_CLOCK - Dvp ht inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_INST_POWER_SWITCH_MEMORY - Dvp ht inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: DVP_HT_INST_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE - Graphics inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_MASK      0xffffffe0
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_SHIFT     5
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_SCB_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_M2MC_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_ALTERNATE_216_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_216_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_STATUS :: GFX_SCB_CLOCK_ENABLE_STATUS [04:04] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_GFX_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_GFX_SCB_CLOCK_ENABLE_STATUS_SHIFT 4
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_STATUS :: GFX_M2MC_CLOCK_ENABLE_STATUS [03:03] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_GFX_M2MC_CLOCK_ENABLE_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_GFX_M2MC_CLOCK_ENABLE_STATUS_SHIFT 3
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_STATUS :: GFX_ALTERNATE_216_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_GFX_ALTERNATE_216_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_GFX_ALTERNATE_216_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_STATUS :: GFX_216_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_GFX_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_GFX_216_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_STATUS :: GFX_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_GFX_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_GFX_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE_V3D - Graphics inst clock enable v3d
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_V3D :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_V3D_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_V3D_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_V3D :: V3D_V3D_CLOCK_ENABLE_V3D [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_V3D_V3D_V3D_CLOCK_ENABLE_V3D_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_V3D_V3D_V3D_CLOCK_ENABLE_V3D_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_V3D_V3D_V3D_CLOCK_ENABLE_V3D_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE_V3D_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_V3D_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_V3D_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_V3D_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_V3D_STATUS :: V3D_V3D_CLOCK_ENABLE_V3D_STATUS [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_V3D_STATUS_V3D_V3D_CLOCK_ENABLE_V3D_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_V3D_STATUS_V3D_V3D_CLOCK_ENABLE_V3D_STATUS_SHIFT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_MEMORY_STANDBY_ENABLE - Graphics inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE :: GFX_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_INST_OBSERVE_CLOCK - Graphics inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_INST_POWER_SWITCH_MEMORY - Graphics inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY :: GFX_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_INST_CLOCK_DISABLE - Disable HIF_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_MASK          0xfffffff0
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_SHIFT         4
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [03:03] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_EMMC_CLOCK [02:02] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CARD_CLOCK [01:01] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_EBI_CLOCK [00:00] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:04] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_reserved0_MASK   0xfffffff0
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT  4
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SPI_CLOCK_STATUS [03:03] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_SHIFT 3
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS [02:02] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS_SHIFT 2
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_CARD_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_EBI_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_EBI_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_EBI_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *HIF_INST_MEMORY_STANDBY_ENABLE - Hif inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: HIF_INST_MEMORY_STANDBY_ENABLE :: HIF_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_INST_OBSERVE_CLOCK - Hif inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_INST_POWER_SWITCH_MEMORY - Hif inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: HIF_INST_POWER_SWITCH_MEMORY :: HIF_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
+ ***************************************************************************/
+/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:04] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK             0xfffffff0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT            4
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [03:02] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x0000000c
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [01:00] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000003
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_32_INST_CLOCK_ENABLE - Memsys 32 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_reserved0_SHIFT    2
+
+/* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE :: MEMSYS_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE :: MEMSYS_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *MEMSYS_32_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
+
+/* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE_STATUS :: MEMSYS_SCB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_STATUS_MEMSYS_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_STATUS_MEMSYS_SCB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE_STATUS :: MEMSYS_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_STATUS_MEMSYS_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_STATUS_MEMSYS_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *MEMSYS_32_INST_MEMORY_STANDBY_ENABLE - Memsys 32 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MEMSYS_32_INST_MEMORY_STANDBY_ENABLE :: MEMSYS_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_MEMSYS_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_MEMSYS_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_MEMSYS_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_32_INST_OBSERVE_CLOCK - Memsys 32 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_reserved0_MASK    0xffffffc0
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_reserved0_SHIFT   6
+
+/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: MEMSYS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: MEMSYS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_32_INST_POWER_SWITCH_MEMORY - Memsys 32 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: MEMSYS_32_INST_POWER_SWITCH_MEMORY :: MEMSYS_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_MEMSYS_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_MEMSYS_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_MEMSYS_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_32_INST_STATUS - Memsys 32 inst status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_STATUS_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_INST_STATUS_reserved0_SHIFT          1
+
+/* CLKGEN :: MEMSYS_32_INST_STATUS :: MEMSYS_PLL_LOCKED_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_STATUS_MEMSYS_PLL_LOCKED_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_INST_STATUS_MEMSYS_PLL_LOCKED_STATUS_SHIFT 0
+
+/***************************************************************************
+ *MOCA_TOP_INST_CLOCK_ENABLE - Moca top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     2
+
+/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: MOCA_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: MOCA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *MOCA_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
+
+/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE_STATUS :: MOCA_SCB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_STATUS_MOCA_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_STATUS_MOCA_SCB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE_STATUS :: MOCA_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_STATUS_MOCA_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_STATUS_MOCA_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *MOCA_TOP_INST_MEMORY_STANDBY_ENABLE - Moca top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MOCA_TOP_INST_MEMORY_STANDBY_ENABLE :: MOCA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MOCA_TOP_INST_OBSERVE_CLOCK - Moca top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MOCA_TOP_INST_POWER_SWITCH_MEMORY - Moca top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: MOCA_TOP_INST_POWER_SWITCH_MEMORY :: MOCA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLK27_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_MASK           0xfffffe00
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_SHIFT          9
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_MASK  0x00000100
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_MASK  0x000000fe
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK  0x00000001
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLOCK_DISABLE - Disable PAD's clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK               0xffffffe0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT              5
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_VCXO27_CLOCK [04:04] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_SC_CLOCK [03:03] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_OBSRV1_CLOCK [02:02] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_OBSRV1_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_OBSRV1_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_OBSRV1_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: reserved0 [31:05] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_MASK        0xffffffe0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_SHIFT       5
+
+/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_VCXO27_CLOCK_STATUS [04:04] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_STATUS_SHIFT 4
+
+/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_SC_CLOCK_STATUS [03:03] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_SC_CLOCK_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_SC_CLOCK_STATUS_SHIFT 3
+
+/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_OBSRV1_CLOCK_STATUS [02:02] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_OBSRV1_CLOCK_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_OBSRV1_CLOCK_STATUS_SHIFT 2
+
+/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CLK27_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK27_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK27_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PAD_CODEC_MCLK_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_MASK      0xfffffe00
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_SHIFT     9
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_MUX_SELECT - Mux selects for Pad clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:05] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK                  0xffffffe0
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT                 5
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_VCXO27_CLOCK [04:02] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_MASK    0x0000001c
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_SHIFT   2
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_SC_CLOCK [01:01] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_MASK        0x00000002
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_SHIFT       1
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_DEFAULT     0x00000000
+
+/* CLKGEN :: PAD_MUX_SELECT :: ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_OBSRV1_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_OBSRV1_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_OBSRV1_OBSERVATION_reserved0_MASK          0xfffffe00
+#define BCHP_CLKGEN_PAD_OBSRV1_OBSERVATION_reserved0_SHIFT         9
+
+/* CLKGEN :: PAD_OBSRV1_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
+#define BCHP_CLKGEN_PAD_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_OBSRV1_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
+#define BCHP_CLKGEN_PAD_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_OBSRV1_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_VCXO27_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_MASK          0xfffffe00
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_SHIFT         9
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET_STATUS - PLL_AUDIO0 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET_STATUS - PLL_AUDIO1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_RESET_STATUS - PLL_AVD Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AVD_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_RDB_MACRO_CTRL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_reserved0_MASK          0xfffffff0
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_reserved0_SHIFT         4
+
+/* CLKGEN :: PLL_AVD_RDB_MACRO_CTRL :: PLL_AVD_OPTIONS_DISABLE_RDB_MACRO [03:03] */
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_PLL_AVD_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_PLL_AVD_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_PLL_AVD_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_RDB_MACRO_CTRL :: OPTIONS [02:00] */
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_OPTIONS_MASK            0x00000007
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_OPTIONS_SHIFT           0
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_OPTIONS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_GLITCHLESS_SWITCH_REQUEST - PLL_MIPS Glitchless Clock Switching
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_reserved0_SHIFT 9
+
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: TRANSACTION_WAIT [08:01] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_DEFAULT 0x0000001f
+
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: PLL_BYPASS_REQUEST [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_GLITCHLESS_SWITCH_STATUS - PLL_MIPS Glitchless Switching
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_STATUS :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_reserved0_SHIFT 4
+
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_STATUS :: PLL_BYPASS_STATUS [03:00] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_MASK 0x0000000f
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_RESET_STATUS - PLL_MIPS Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_MIPS_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_RDB_MACRO_CTRL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_reserved0_MASK         0xfffffff0
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_reserved0_SHIFT        4
+
+/* CLKGEN :: PLL_MIPS_RDB_MACRO_CTRL :: PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO [03:03] */
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_RDB_MACRO_CTRL :: OPTIONS [02:00] */
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_OPTIONS_MASK           0x00000007
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_OPTIONS_SHIFT          0
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_OPTIONS_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_RESET_STATUS - PLL_MOCA Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_RESET_STATUS - PLL_RAAGA Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_SHIFT     2
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_RAAGA_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_MASK        0xfffffff0
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_SHIFT       4
+
+/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO [03:03] */
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: OPTIONS [02:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_MASK          0x00000007
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_SHIFT         0
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_RESET_STATUS - PLL_SC0 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SC1_PLL_RESET_STATUS - PLL_SC1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_STRAP_OVERRIDE - Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_STRAP_OVERRIDE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_STRAP_OVERRIDE :: STRAP_HIFSPI_DISABLE [01:01] */
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_HIFSPI_DISABLE_MASK   0x00000002
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_HIFSPI_DISABLE_SHIFT  1
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_HIFSPI_DISABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_STRAP_OVERRIDE :: STRAP_FREQ_PLLMIPS_DISABLE [00:00] */
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET_STATUS - PLL_SYS1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_RESET_STATUS - PLL_VCXO0 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_reserved0_SHIFT     2
+
+/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_RESET_STATUS - PLL_VCXO1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_reserved0_SHIFT     2
+
+/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PM_CLOCK_216_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_SHIFT         1
+
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_MASK   0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT  0
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               3
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys_PLL [02:02] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_MASK               0x00000004
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_SHIFT              2
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_DEFAULT            0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [01:01] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK                 0x00000002
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT                1
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT              0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_MIPS [00:00] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_MASK                 0x00000001
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_SHIFT                0
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PM_PLL_LDO_POWERUP - Power management LDO PLL
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_MASK              0xfffffff0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_SHIFT             4
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_SYS1 [03:03] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SYS1_MASK     0x00000008
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SYS1_SHIFT    3
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SYS1_DEFAULT  0x00000001
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_RAAGA [02:02] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_MASK    0x00000004
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_SHIFT   2
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_DEFAULT 0x00000001
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_MOCA [01:01] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_MASK     0x00000002
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_SHIFT    1
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_DEFAULT  0x00000001
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AVD [00:00] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_MASK      0x00000001
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_SHIFT     0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_DEFAULT   0x00000001
+
+/***************************************************************************
+ *PM_PLL_LDO_POWERUP_SM - Power management LDO PLL state machine
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: reserved0 [31:27] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_MASK           0xf8000000
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_SHIFT          27
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_POWERUP_WAIT_TIME [26:14] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_MASK 0x07ffc000
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_SHIFT 14
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_DEFAULT 0x00001518
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_CLK_STOP_WAIT_TIME [13:01] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_MASK 0x00003ffe
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_SHIFT 1
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_DEFAULT 0x000000c8
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: GISB_OVERRIDE_SM [00:00] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_MASK    0x00000001
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_SHIFT   0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_CLOCK_ENABLE - Raaga dsp top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 4
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_DSP_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE_STATUS :: RAAGA_SCB_CLOCK_ENABLE_STATUS [03:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_STATUS_RAAGA_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_STATUS_RAAGA_SCB_CLOCK_ENABLE_STATUS_SHIFT 3
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE_STATUS :: RAAGA_DSP_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_STATUS_RAAGA_DSP_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_STATUS_RAAGA_DSP_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE_STATUS :: RAAGA_216_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_STATUS_RAAGA_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_STATUS_RAAGA_216_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE_STATUS :: RAAGA_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_STATUS_RAAGA_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_STATUS_RAAGA_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE - Raaga dsp top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE :: RAAGAA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_OBSERVE_CLOCK - Raaga dsp top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_ENABLE_OBSERVE_CLOCK [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY - Raaga dsp top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY :: RAAGA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RFM_TOP_INST_CLOCK_ENABLE - Rfm top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: RFM_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RFM_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: RFM_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *RFM_TOP_INST_MEMORY_STANDBY_ENABLE - Rfm top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RFM_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_RFM_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: RFM_TOP_INST_MEMORY_STANDBY_ENABLE :: RFMA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RFM_TOP_INST_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RFM_TOP_INST_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_INST_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RFM_TOP_INST_OBSERVE_CLOCK - Rfm top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: SATA3_CONTROL_OBSERVE_CLOCK [04:01] */
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_MASK 0x0000001e
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: RFM_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RFM_TOP_INST_POWER_SWITCH_MEMORY - Rfm top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RFM_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RFM_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: RFM_TOP_INST_POWER_SWITCH_MEMORY :: RFM_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RFM_TOP_INST_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RFM_TOP_INST_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_INST_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_INST_CLOCK_DISABLE - Disable SATA3_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_reserved0_MASK    0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT   1
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE :: DISABLE_SATA3_AT_SPEED_SCAN_CLOCK [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *SATA3_TOP_INST_CLOCK_ENABLE - Sata3 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT    2
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SATA3_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: SATA3_SCB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_SCB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: SATA3_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *SATA3_TOP_INST_CLOCK_SELECT - Sata3 top inst clock select
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_SHIFT    1
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: SATA3_REF_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SATA3_TOP_INST_MEMORY_STANDBY_ENABLE - Sata3 top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SATA3_TOP_INST_MEMORY_STANDBY_ENABLE :: SATA3_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_INST_OBSERVE_CLOCK - Sata3 top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_MASK    0xffffffc0
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT   6
+
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_INST_POWER_SWITCH_MEMORY - Sata3 top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SATA3_TOP_INST_POWER_SWITCH_MEMORY :: SATA3_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SECTOP_INST_CLOCK_ENABLE - Sectop inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_SHIFT       1
+
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: SEC_ALTERNATE_SCB_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SECTOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_STATUS :: SEC_ALTERNATE_SCB_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_SEC_ALTERNATE_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_SEC_ALTERNATE_SCB_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SEC_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SEC_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SEC_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
+ ***************************************************************************/
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT           2
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [01:01] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK            0x00000002
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT           1
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [00:00] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK            0x00000001
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT           0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *SPARE - Spares
+ ***************************************************************************/
+/* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK                     0xfffff000
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT                    12
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT                  0x00000000
+
+/* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK                    0x00000fff
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT                   0
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *SVD0_TOP_INST_CLOCK_ENABLE - Svd0 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xffffffe0
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     5
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD_SCB_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD_CPU_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD_CORE_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CORE_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CORE_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD_ALTERNATE_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SVD0_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE_STATUS :: SVD_SCB_CLOCK_ENABLE_STATUS [04:04] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD_SCB_CLOCK_ENABLE_STATUS_SHIFT 4
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE_STATUS :: SVD_CPU_CLOCK_ENABLE_STATUS [03:03] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD_CPU_CLOCK_ENABLE_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD_CPU_CLOCK_ENABLE_STATUS_SHIFT 3
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE_STATUS :: SVD_CORE_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD_CORE_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE_STATUS :: SVD_ALTERNATE_SCB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD_ALTERNATE_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD_ALTERNATE_SCB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE_STATUS :: SVD_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *SVD0_TOP_INST_MEMORY_STANDBY_ENABLE - Svd0 top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SVD0_TOP_INST_MEMORY_STANDBY_ENABLE :: SVD_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SVD0_TOP_INST_POWER_SWITCH_MEMORY - Svd0 top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SVD0_TOP_INST_POWER_SWITCH_MEMORY :: SVD_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_AON_INST_OBSERVE_CLOCK - Sys aon inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_INST_CLOCK_DISABLE - Disable SYS_CTRL_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffff0
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_SHIFT    4
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [03:03] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK [02:02] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:04] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 4
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSCTRL_UPG_CLOCK_STATUS [03:03] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_SHIFT 3
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK_STATUS [02:02] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_STATUS_SHIFT 2
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SC1_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SC0_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *SYS_CTRL_INST_MEMORY_STANDBY_ENABLE - Sys ctrl inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SYS_CTRL_INST_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_INST_OBSERVE_CLOCK - Sys ctrl inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TESTPORT - Special Testport Controls
+ ***************************************************************************/
+/* CLKGEN :: TESTPORT :: reserved0 [31:04] */
+#define BCHP_CLKGEN_TESTPORT_reserved0_MASK                        0xfffffff0
+#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT                       4
+
+/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [03:00] */
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK           0x0000000f
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT          0
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *USB0_INST_CLOCK_DISABLE - Disable USB0_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_reserved0_SHIFT        2
+
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: DISABLE_USB_54_MDIO_CLOCK [01:01] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: DISABLE_USB0_27_FREERUN_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_27_FREERUN_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_27_FREERUN_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_27_FREERUN_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB0_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_STATUS_reserved0_MASK  0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
+
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB_54_MDIO_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_STATUS_DISABLE_USB_54_MDIO_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_STATUS_DISABLE_USB_54_MDIO_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB0_27_FREERUN_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_27_FREERUN_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_27_FREERUN_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *USB0_INST_CLOCK_ENABLE - Usb0 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: USB0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *USB0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT  2
+
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE_STATUS :: USB0_SCB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE_STATUS :: USB0_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_STATUS_USB0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_STATUS_USB0_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *USB0_INST_MEMORY_STANDBY_ENABLE - Usb0 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: USB0_INST_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB0_INST_OBSERVE_CLOCK - Usb0 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB0_INST_POWER_SWITCH_MEMORY - Usb0 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: USB0_INST_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB1_INST_CLOCK_DISABLE - Disable USB1_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_reserved0_SHIFT        2
+
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: DISABLE_USB_54_MDIO_CLOCK [01:01] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: DISABLE_USB1_27_FREERUN_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_27_FREERUN_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_27_FREERUN_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_27_FREERUN_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB1_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_STATUS_reserved0_MASK  0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
+
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB_54_MDIO_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_STATUS_DISABLE_USB_54_MDIO_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_STATUS_DISABLE_USB_54_MDIO_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB1_27_FREERUN_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_STATUS_DISABLE_USB1_27_FREERUN_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_STATUS_DISABLE_USB1_27_FREERUN_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *USB1_INST_CLOCK_ENABLE - Usb1 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: USB1_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: USB1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *USB1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT  2
+
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE_STATUS :: USB1_SCB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_STATUS_USB1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_STATUS_USB1_SCB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE_STATUS :: USB1_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_STATUS_USB1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_STATUS_USB1_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *USB1_INST_MEMORY_STANDBY_ENABLE - Usb1 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: USB1_INST_MEMORY_STANDBY_ENABLE :: USB1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB1_INST_OBSERVE_CLOCK - Usb1 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB1_INST_POWER_SWITCH_MEMORY - Usb1 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: USB1_INST_POWER_SWITCH_MEMORY :: USB1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_DISABLE - Disable VEC_AIO_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_MASK  0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_ITU656_0_CLOCK [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_VEC_ITU656_0_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_0_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_0_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_VEC_DACADC_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO - Vec aio top inst clock enable aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: reserved0 [31:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_SHIFT 3
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_STATUS [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_STATUS_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_STATUS [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_STATUS_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_STATUS [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_STATUS_SHIFT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC - Vec aio top inst clock enable vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_SHIFT 6
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_SCB_CLOCK_ENABLE_VEC [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_QDAC_216_CLOCK_ENABLE_VEC [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_ALTERNATE_216_CLOCK_ENABLE_VEC [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_SHIFT 3
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_324_CLOCK_ENABLE_VEC [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_324_CLOCK_ENABLE_VEC_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_324_CLOCK_ENABLE_VEC_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_324_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_216_CLOCK_ENABLE_VEC [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_108_CLOCK_ENABLE_VEC [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_reserved0_SHIFT 6
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_SCB_CLOCK_ENABLE_VEC_STATUS [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_SCB_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_SCB_CLOCK_ENABLE_VEC_STATUS_SHIFT 5
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_QDAC_216_CLOCK_ENABLE_VEC_STATUS [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_QDAC_216_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_QDAC_216_CLOCK_ENABLE_VEC_STATUS_SHIFT 4
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_STATUS [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_STATUS_SHIFT 3
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_324_CLOCK_ENABLE_VEC_STATUS [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_324_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_324_CLOCK_ENABLE_VEC_STATUS_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_216_CLOCK_ENABLE_VEC_STATUS [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_216_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_216_CLOCK_ENABLE_VEC_STATUS_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_108_CLOCK_ENABLE_VEC_STATUS [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_108_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_108_CLOCK_ENABLE_VEC_STATUS_SHIFT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO - Vec aio top inst memory standby enable aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO :: AIO_MEMORY_STANDBY_ENABLE_AIO [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC - Vec aio top inst memory standby enable vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC :: VEC_MEMORY_STANDBY_ENABLE_VEC [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO - Vec aio top inst observe clock aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_reserved0_SHIFT 6
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO :: AIO_ENABLE_OBSERVE_CLOCK_AIO [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_AIO_ENABLE_OBSERVE_CLOCK_AIO_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_AIO_ENABLE_OBSERVE_CLOCK_AIO_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_AIO_ENABLE_OBSERVE_CLOCK_AIO_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO :: AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_AIO [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_AIO_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_AIO_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_AIO_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO :: AIO_CONTROL_OBSERVE_CLOCK_AIO [03:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_AIO_CONTROL_OBSERVE_CLOCK_AIO_MASK 0x0000000f
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_AIO_CONTROL_OBSERVE_CLOCK_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_AIO_CONTROL_OBSERVE_CLOCK_AIO_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC - Vec aio top inst observe clock vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_reserved0_SHIFT 6
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC :: VEC_ENABLE_OBSERVE_CLOCK_VEC [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_VEC_ENABLE_OBSERVE_CLOCK_VEC_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_VEC_ENABLE_OBSERVE_CLOCK_VEC_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_VEC_ENABLE_OBSERVE_CLOCK_VEC_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC :: VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_VEC [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_VEC_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_VEC_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_VEC_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC :: VEC_CONTROL_OBSERVE_CLOCK_VEC [03:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_VEC_CONTROL_OBSERVE_CLOCK_VEC_MASK 0x0000000f
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_VEC_CONTROL_OBSERVE_CLOCK_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_VEC_CONTROL_OBSERVE_CLOCK_VEC_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO - Vec aio top inst power switch memory aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO :: AIO_POWER_SWITCH_MEMORY_AIO [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC - Vec aio top inst power switch memory vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC :: VEC_POWER_SWITCH_MEMORY_VEC [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ZCPU_TOP_INST_CLOCK_DISABLE - Disable ZCPU_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1
+
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_DISABLE :: DISABLE_ZMIPS_SLOWMIPS_CLOCK [00:00] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_SLOWMIPS_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_SLOWMIPS_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_SLOWMIPS_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ZCPU_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_ZMIPS_SLOWMIPS_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_ZMIPS_SLOWMIPS_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_ZMIPS_SLOWMIPS_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *ZCPU_TOP_INST_CLOCK_ENABLE - Zcpu top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffff8
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     3
+
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE :: ZMIPS_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE :: ZMIPS_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE :: ZMIPS_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *ZCPU_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE_STATUS :: ZMIPS_SCB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_STATUS_ZMIPS_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_STATUS_ZMIPS_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE_STATUS :: ZMIPS_216_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_STATUS_ZMIPS_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_STATUS_ZMIPS_216_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE_STATUS :: ZMIPS_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_STATUS_ZMIPS_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_STATUS_ZMIPS_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *ZCPU_TOP_INST_OBSERVE_CLOCK - Zcpu top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS - Bypass GENET_TOP_DUAL_RGMII_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_reserved0_SHIFT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS :: EEE_25_CLOCK_BYPASS [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1 - Disable DUAL_GENET_TOP_RGMII_INST's GENET1 clocks
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1 :: reserved0 [31:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_reserved0_SHIFT 4
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1 :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1 :: DISABLE_GENET1_SYSTEM_PM_CLOCK [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_DISABLE_GENET1_SYSTEM_PM_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_DISABLE_GENET1_SYSTEM_PM_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_DISABLE_GENET1_SYSTEM_PM_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1 :: DISABLE_GENET1_SYSTEM_FAST_CLOCK [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_DISABLE_GENET1_SYSTEM_FAST_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_DISABLE_GENET1_SYSTEM_FAST_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_DISABLE_GENET1_SYSTEM_FAST_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1 :: DISABLE_GENET1_ALWAYSON_CLOCK [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_DISABLE_GENET1_ALWAYSON_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_DISABLE_GENET1_ALWAYSON_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_DISABLE_GENET1_ALWAYSON_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_STATUS :: reserved0 [31:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_STATUS_reserved0_SHIFT 4
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_STATUS :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK_STATUS [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_STATUS_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_STATUS_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_STATUS_SHIFT 3
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_STATUS :: DISABLE_GENET1_SYSTEM_PM_CLOCK_STATUS [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_STATUS_DISABLE_GENET1_SYSTEM_PM_CLOCK_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_STATUS_DISABLE_GENET1_SYSTEM_PM_CLOCK_STATUS_SHIFT 2
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_STATUS :: DISABLE_GENET1_SYSTEM_FAST_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_STATUS_DISABLE_GENET1_SYSTEM_FAST_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_STATUS_DISABLE_GENET1_SYSTEM_FAST_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_STATUS :: DISABLE_GENET1_ALWAYSON_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_STATUS_DISABLE_GENET1_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1_STATUS_DISABLE_GENET1_ALWAYSON_CLOCK_STATUS_SHIFT 0
+
+#endif /* #ifndef BCHP_CLKGEN_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_common.h b/include/linux/brcmstb/7429b0/bchp_common.h
new file mode 100644
index 0000000..a583b0d
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_common.h
@@ -0,0 +1,2782 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:03 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_COMMON_H__
+#define BCHP_COMMON_H__
+
+/***************************************************************************
+ *BCM7429_B0
+ ***************************************************************************/
+#define BCHP_PHYSICAL_OFFSET                               0x10000000
+#define BCHP_REGISTER_START                                0x00000000 /* DECODE_RBNODE_REGS_0 is first */
+#define BCHP_REGISTER_END                                  0x00bffd98 /* MOCA_HOSTMISC is last */
+#define BCHP_REGISTER_SIZE                                 0x002fff66 /* Number of registers */
+
+/****************************************************************************
+ * Core instance register start address.
+ ***************************************************************************/
+#define BCHP_DECODE_RBNODE_REGS_0_REG_START                0x00000000
+#define BCHP_DECODE_RBNODE_REGS_0_REG_END                  0x0000007c
+#define BCHP_DECODE_MAIN_0_REG_START                       0x00000100
+#define BCHP_DECODE_MAIN_0_REG_END                         0x000001fc
+#define BCHP_SDRAM_DEBUG_0_REG_START                       0x00000200
+#define BCHP_SDRAM_DEBUG_0_REG_END                         0x0000027c
+#define BCHP_DECODE_MCOM_0_REG_START                       0x00000300
+#define BCHP_DECODE_MCOM_0_REG_END                         0x0000031c
+#define BCHP_DECODE_SPRE_0_REG_START                       0x00000320
+#define BCHP_DECODE_SPRE_0_REG_END                         0x0000033c
+#define BCHP_DECODE_WPRD_0_REG_START                       0x00000340
+#define BCHP_DECODE_WPRD_0_REG_END                         0x0000035c
+#define BCHP_DECODE_DQNT_0_REG_START                       0x00000400
+#define BCHP_DECODE_DQNT_0_REG_END                         0x0000045c
+#define BCHP_DECODE_DQNT_8X8_0_REG_START                   0x00000500
+#define BCHP_DECODE_DQNT_8X8_0_REG_END                     0x0000057c
+#define BCHP_DECODE_VP8_XFRM_0_REG_START                   0x00000600
+#define BCHP_DECODE_VP8_XFRM_0_REG_END                     0x0000060c
+#define BCHP_DECODE_XFRM_0_REG_START                       0x00000700
+#define BCHP_DECODE_XFRM_0_REG_END                         0x0000071c
+#define BCHP_DECODE_DBLK_0_REG_START                       0x00000720
+#define BCHP_DECODE_DBLK_0_REG_END                         0x0000073c
+#define BCHP_DECODE_MB_0_REG_START                         0x00000740
+#define BCHP_DECODE_MB_0_REG_END                           0x0000075c
+#define BCHP_REG_CABAC2BINS_0_REG_START                    0x00000b00
+#define BCHP_REG_CABAC2BINS_0_REG_END                      0x00000bfc
+#define BCHP_DECODE_SINT_0_REG_START                       0x00000c00
+#define BCHP_DECODE_SINT_0_REG_END                         0x00000dfc
+#define BCHP_DECODE_RVC_0_REG_START                        0x00000e00
+#define BCHP_DECODE_RVC_0_REG_END                          0x00000efc
+#define BCHP_DECODE_CPUREGS_0_REG_START                    0x00000f00
+#define BCHP_DECODE_CPUREGS_0_REG_END                      0x00000f7c
+#define BCHP_DECODE_CPUREGS2_0_REG_START                   0x00000f80
+#define BCHP_DECODE_CPUREGS2_0_REG_END                     0x00000ffc
+#define BCHP_DECODE_CPUDMA_0_REG_START                     0x00001800
+#define BCHP_DECODE_CPUDMA_0_REG_END                       0x000018fc
+#define BCHP_DECODE_DMAMEM_0_REG_START                     0x00001a00
+#define BCHP_DECODE_DMAMEM_0_REG_END                       0x000021fc
+#define BCHP_REG_CABAC2BINS2_0_REG_START                   0x00002400
+#define BCHP_REG_CABAC2BINS2_0_REG_END                     0x000027fc
+#define BCHP_DECODE_WPTBL_0_REG_START                      0x00003000
+#define BCHP_DECODE_WPTBL_0_REG_END                        0x000031fc
+#define BCHP_DECODE_SINT_OLOOP_0_REG_START                 0x0000cc00
+#define BCHP_DECODE_SINT_OLOOP_0_REG_END                   0x0000ccfc
+#define BCHP_DECODE_SD_0_REG_START                         0x00040800
+#define BCHP_DECODE_SD_0_REG_END                           0x00040ffc
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_START             0x00041000
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_END               0x0004107c
+#define BCHP_DECODE_CPUCORE_0_REG_START                    0x00044000
+#define BCHP_DECODE_CPUCORE_0_REG_END                      0x00044ffc
+#define BCHP_DECODE_CPUAUX_0_REG_START                     0x00045000
+#define BCHP_DECODE_CPUAUX_0_REG_END                       0x00045ffc
+#define BCHP_DECODE_CPUIMEM_0_REG_START                    0x00046000
+#define BCHP_DECODE_CPUIMEM_0_REG_END                      0x00047ffc
+#define BCHP_DECODE_CPUDMEM_0_REG_START                    0x00048000
+#define BCHP_DECODE_CPUDMEM_0_REG_END                      0x0004fffc
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_START            0x00051000
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_END              0x0005107c
+#define BCHP_DECODE_CPUDMA2_0_REG_START                    0x00051800
+#define BCHP_DECODE_CPUDMA2_0_REG_END                      0x000518fc
+#define BCHP_DECODE_DMAMEM2_0_REG_START                    0x00051a00
+#define BCHP_DECODE_DMAMEM2_0_REG_END                      0x000521fc
+#define BCHP_DECODE_CPUCORE2_0_REG_START                   0x00054000
+#define BCHP_DECODE_CPUCORE2_0_REG_END                     0x00054ffc
+#define BCHP_DECODE_CPUAUX2_0_REG_START                    0x00055000
+#define BCHP_DECODE_CPUAUX2_0_REG_END                      0x00055ffc
+#define BCHP_DECODE_CPUIMEM2_0_REG_START                   0x00056000
+#define BCHP_DECODE_CPUIMEM2_0_REG_END                     0x00057ffc
+#define BCHP_DECODE_CPUDMEM2_0_REG_START                   0x00058000
+#define BCHP_DECODE_CPUDMEM2_0_REG_END                     0x0005fffc
+#define BCHP_DECODE_IP_SHIM_0_REG_START                    0x00060000
+#define BCHP_DECODE_IP_SHIM_0_REG_END                      0x00060084
+#define BCHP_AVD_CACHE_0_REG_START                         0x00062000
+#define BCHP_AVD_CACHE_0_REG_END                           0x0006203c
+#define BCHP_ILS_REGS_0_REG_START                          0x00070000
+#define BCHP_ILS_REGS_0_REG_END                            0x0007007c
+#define BCHP_ILS_SCALE_ADDR_0_REG_START                    0x00070100
+#define BCHP_ILS_SCALE_ADDR_0_REG_END                      0x0007010c
+#define BCHP_ILS_SPSCALE_FILL_0_REG_START                  0x00070180
+#define BCHP_ILS_SPSCALE_FILL_0_REG_END                    0x00070180
+#define BCHP_ILS_MVSCALE_0_REG_START                       0x00070200
+#define BCHP_ILS_MVSCALE_0_REG_END                         0x0007038c
+#define BCHP_SVD_INTR2_0_REG_START                         0x00080000
+#define BCHP_SVD_INTR2_0_REG_END                           0x0008002c
+#define BCHP_SVD_RGR_0_REG_START                           0x00080400
+#define BCHP_SVD_RGR_0_REG_END                             0x00080410
+#define BCHP_BLD_DECODE_RBNODE_REGS_0_REG_START            0x00100000
+#define BCHP_BLD_DECODE_RBNODE_REGS_0_REG_END              0x0010007c
+#define BCHP_BLD_DECODE_MAIN_0_REG_START                   0x00100100
+#define BCHP_BLD_DECODE_MAIN_0_REG_END                     0x001001fc
+#define BCHP_BLD_SDRAM_DEBUG_0_REG_START                   0x00100200
+#define BCHP_BLD_SDRAM_DEBUG_0_REG_END                     0x0010027c
+#define BCHP_BLD_DECODE_MCOM_0_REG_START                   0x00100300
+#define BCHP_BLD_DECODE_MCOM_0_REG_END                     0x0010031c
+#define BCHP_BLD_DECODE_SPRE_0_REG_START                   0x00100320
+#define BCHP_BLD_DECODE_SPRE_0_REG_END                     0x0010033c
+#define BCHP_BLD_DECODE_WPRD_0_REG_START                   0x00100340
+#define BCHP_BLD_DECODE_WPRD_0_REG_END                     0x0010035c
+#define BCHP_BLD_DECODE_DQNT_0_REG_START                   0x00100400
+#define BCHP_BLD_DECODE_DQNT_0_REG_END                     0x0010045c
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_START               0x00100500
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_END                 0x0010057c
+#define BCHP_BLD_DECODE_VP8_XFRM_0_REG_START               0x00100600
+#define BCHP_BLD_DECODE_VP8_XFRM_0_REG_END                 0x0010060c
+#define BCHP_BLD_DECODE_XFRM_0_REG_START                   0x00100700
+#define BCHP_BLD_DECODE_XFRM_0_REG_END                     0x0010071c
+#define BCHP_BLD_DECODE_DBLK_0_REG_START                   0x00100720
+#define BCHP_BLD_DECODE_DBLK_0_REG_END                     0x0010073c
+#define BCHP_BLD_DECODE_MB_0_REG_START                     0x00100740
+#define BCHP_BLD_DECODE_MB_0_REG_END                       0x0010075c
+#define BCHP_BLD_REG_CABAC2BINS_0_REG_START                0x00100b00
+#define BCHP_BLD_REG_CABAC2BINS_0_REG_END                  0x00100bfc
+#define BCHP_BLD_DECODE_SINT_0_REG_START                   0x00100c00
+#define BCHP_BLD_DECODE_SINT_0_REG_END                     0x00100dfc
+#define BCHP_BLD_DECODE_RVC_0_REG_START                    0x00100e00
+#define BCHP_BLD_DECODE_RVC_0_REG_END                      0x00100efc
+#define BCHP_BLD_DECODE_CPUREGS_0_REG_START                0x00100f00
+#define BCHP_BLD_DECODE_CPUREGS_0_REG_END                  0x00100f7c
+#define BCHP_BLD_DECODE_CPUREGS2_0_REG_START               0x00100f80
+#define BCHP_BLD_DECODE_CPUREGS2_0_REG_END                 0x00100ffc
+#define BCHP_BLD_DECODE_CPUDMA_0_REG_START                 0x00101800
+#define BCHP_BLD_DECODE_CPUDMA_0_REG_END                   0x001018fc
+#define BCHP_BLD_DECODE_DMAMEM_0_REG_START                 0x00101a00
+#define BCHP_BLD_DECODE_DMAMEM_0_REG_END                   0x001021fc
+#define BCHP_BLD_REG_CABAC2BINS2_0_REG_START               0x00102400
+#define BCHP_BLD_REG_CABAC2BINS2_0_REG_END                 0x001027fc
+#define BCHP_BLD_DECODE_WPTBL_0_REG_START                  0x00103000
+#define BCHP_BLD_DECODE_WPTBL_0_REG_END                    0x001031fc
+#define BCHP_BLD_DECODE_SINT_OLOOP_0_REG_START             0x0010cc00
+#define BCHP_BLD_DECODE_SINT_OLOOP_0_REG_END               0x0010ccfc
+#define BCHP_BLD_DECODE_SD_0_REG_START                     0x00140800
+#define BCHP_BLD_DECODE_SD_0_REG_END                       0x00140ffc
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS_0_REG_START         0x00141000
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS_0_REG_END           0x0014107c
+#define BCHP_BLD_DECODE_CPUCORE_0_REG_START                0x00144000
+#define BCHP_BLD_DECODE_CPUCORE_0_REG_END                  0x00144ffc
+#define BCHP_BLD_DECODE_CPUAUX_0_REG_START                 0x00145000
+#define BCHP_BLD_DECODE_CPUAUX_0_REG_END                   0x00145ffc
+#define BCHP_BLD_DECODE_CPUIMEM_0_REG_START                0x00146000
+#define BCHP_BLD_DECODE_CPUIMEM_0_REG_END                  0x00147ffc
+#define BCHP_BLD_DECODE_CPUDMEM_0_REG_START                0x00148000
+#define BCHP_BLD_DECODE_CPUDMEM_0_REG_END                  0x0014fffc
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS2_0_REG_START        0x00151000
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS2_0_REG_END          0x0015107c
+#define BCHP_BLD_DECODE_CPUDMA2_0_REG_START                0x00151800
+#define BCHP_BLD_DECODE_CPUDMA2_0_REG_END                  0x001518fc
+#define BCHP_BLD_DECODE_DMAMEM2_0_REG_START                0x00151a00
+#define BCHP_BLD_DECODE_DMAMEM2_0_REG_END                  0x001521fc
+#define BCHP_BLD_DECODE_CPUCORE2_0_REG_START               0x00154000
+#define BCHP_BLD_DECODE_CPUCORE2_0_REG_END                 0x00154ffc
+#define BCHP_BLD_DECODE_CPUAUX2_0_REG_START                0x00155000
+#define BCHP_BLD_DECODE_CPUAUX2_0_REG_END                  0x00155ffc
+#define BCHP_BLD_DECODE_CPUIMEM2_0_REG_START               0x00156000
+#define BCHP_BLD_DECODE_CPUIMEM2_0_REG_END                 0x00157ffc
+#define BCHP_BLD_DECODE_CPUDMEM2_0_REG_START               0x00158000
+#define BCHP_BLD_DECODE_CPUDMEM2_0_REG_END                 0x0015fffc
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_START                0x00160000
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_END                  0x00160084
+#define BCHP_BLD_AVD_CACHE_0_REG_START                     0x00162000
+#define BCHP_BLD_AVD_CACHE_0_REG_END                       0x0016203c
+#define BCHP_VICH_0_REG_START                              0x00170000
+#define BCHP_VICH_0_REG_END                                0x0017008b
+#define BCHP_SATA_GRB_REG_START                            0x00180000
+#define BCHP_SATA_GRB_REG_END                              0x0018000c
+#define BCHP_SATA_TOP_CTRL_REG_START                       0x00180020
+#define BCHP_SATA_TOP_CTRL_REG_END                         0x00180038
+#define BCHP_SATA3_INTR2_REG_START                         0x00180080
+#define BCHP_SATA3_INTR2_REG_END                           0x001800ac
+#define BCHP_SATA_AHCI_GHC_REG_START                       0x00181000
+#define BCHP_SATA_AHCI_GHC_REG_END                         0x00181028
+#define BCHP_SATA_GLOBAL_RESERVED_REG_START                0x0018102c
+#define BCHP_SATA_GLOBAL_RESERVED_REG_END                  0x0018109c
+#define BCHP_SATA_PORT0_AHCI_S1_REG_START                  0x00181100
+#define BCHP_SATA_PORT0_AHCI_S1_REG_END                    0x0018111c
+#define BCHP_SATA_PORT0_AHCI_S2_REG_START                  0x00181120
+#define BCHP_SATA_PORT0_AHCI_S2_REG_END                    0x00181134
+#define BCHP_SATA_PORT0_AHCI_S3_REG_START                  0x00181138
+#define BCHP_SATA_PORT0_AHCI_S3_REG_END                    0x0018117c
+#define BCHP_SATA_PORT1_AHCI_S1_REG_START                  0x00181180
+#define BCHP_SATA_PORT1_AHCI_S1_REG_END                    0x0018119c
+#define BCHP_SATA_PORT1_AHCI_S2_REG_START                  0x001811a0
+#define BCHP_SATA_PORT1_AHCI_S2_REG_END                    0x001811b4
+#define BCHP_SATA_PORT1_AHCI_S3_REG_START                  0x001811b8
+#define BCHP_SATA_PORT1_AHCI_S3_REG_END                    0x001811fc
+#define BCHP_SATA_AHCI_PCICFG_REG_START                    0x00181600
+#define BCHP_SATA_AHCI_PCICFG_REG_END                      0x00181664
+#define BCHP_SATA_PORT0_CTRL_REG_START                     0x00181700
+#define BCHP_SATA_PORT0_CTRL_REG_END                       0x00181730
+#define BCHP_SATA_PORT0_CJPAT_REG_START                    0x00181740
+#define BCHP_SATA_PORT0_CJPAT_REG_END                      0x00181764
+#define BCHP_SATA_PORT1_CTRL_REG_START                     0x00181780
+#define BCHP_SATA_PORT1_CTRL_REG_END                       0x001817b0
+#define BCHP_SATA_PORT1_CJPAT_REG_START                    0x001817c0
+#define BCHP_SATA_PORT1_CJPAT_REG_END                      0x001817e4
+#define BCHP_SATA_LEG_PCICFG_REG_START                     0x00181800
+#define BCHP_SATA_LEG_PCICFG_REG_END                       0x00181880
+#define BCHP_SATA_PORT0_LEG_S1_REG_START                   0x00181900
+#define BCHP_SATA_PORT0_LEG_S1_REG_END                     0x00181934
+#define BCHP_SATA_PORT0_LEG_S2_REG_START                   0x00181940
+#define BCHP_SATA_PORT0_LEG_S2_REG_END                     0x00181954
+#define BCHP_SATA_PORT0_LEG_S3_REG_START                   0x00181958
+#define BCHP_SATA_PORT0_LEG_S3_REG_END                     0x00181998
+#define BCHP_SATA_PORT1_LEG_S1_REG_START                   0x00181a00
+#define BCHP_SATA_PORT1_LEG_S1_REG_END                     0x00181a34
+#define BCHP_SATA_PORT1_LEG_S2_REG_START                   0x00181a40
+#define BCHP_SATA_PORT1_LEG_S2_REG_END                     0x00181a54
+#define BCHP_SATA_PORT1_LEG_S3_REG_START                   0x00181a58
+#define BCHP_SATA_PORT1_LEG_S3_REG_END                     0x00181a98
+#define BCHP_XPT_BUS_IF_REG_START                          0x00200000
+#define BCHP_XPT_BUS_IF_REG_END                            0x00200078
+#define BCHP_XPT_XMEMIF_REG_START                          0x00200100
+#define BCHP_XPT_XMEMIF_REG_END                            0x002001bc
+#define BCHP_XPT_PMU_REG_START                             0x00200200
+#define BCHP_XPT_PMU_REG_END                               0x00200208
+#define BCHP_XPT_GR_REG_START                              0x00200300
+#define BCHP_XPT_GR_REG_END                                0x0020030c
+#define BCHP_XPT_RMX0_IO_REG_START                         0x00200400
+#define BCHP_XPT_RMX0_IO_REG_END                           0x00200420
+#define BCHP_XPT_RMX1_IO_REG_START                         0x00200500
+#define BCHP_XPT_RMX1_IO_REG_END                           0x00200520
+#define BCHP_XPT_WAKEUP_REG_START                          0x00201000
+#define BCHP_XPT_WAKEUP_REG_END                            0x00201fbc
+#define BCHP_XPT_FE_REG_START                              0x00204000
+#define BCHP_XPT_FE_REG_END                                0x002053fc
+#define BCHP_XPT_DPCR0_REG_START                           0x00207000
+#define BCHP_XPT_DPCR0_REG_END                             0x00207074
+#define BCHP_XPT_DPCR1_REG_START                           0x00207080
+#define BCHP_XPT_DPCR1_REG_END                             0x002070f4
+#define BCHP_XPT_DPCR2_REG_START                           0x00207100
+#define BCHP_XPT_DPCR2_REG_END                             0x00207174
+#define BCHP_XPT_DPCR3_REG_START                           0x00207180
+#define BCHP_XPT_DPCR3_REG_END                             0x002071f4
+#define BCHP_XPT_DPCR4_REG_START                           0x00207200
+#define BCHP_XPT_DPCR4_REG_END                             0x00207274
+#define BCHP_XPT_DPCR_PP_REG_START                         0x00207400
+#define BCHP_XPT_DPCR_PP_REG_END                           0x00207404
+#define BCHP_XPT_PSUB_REG_START                            0x00207a00
+#define BCHP_XPT_PSUB_REG_END                              0x00207b88
+#define BCHP_XPT_MPOD_REG_START                            0x00207c00
+#define BCHP_XPT_MPOD_REG_END                              0x00207c20
+#define BCHP_XPT_RMX0_REG_START                            0x00207d00
+#define BCHP_XPT_RMX0_REG_END                              0x00207d08
+#define BCHP_XPT_RMX1_REG_START                            0x00207e00
+#define BCHP_XPT_RMX1_REG_END                              0x00207e08
+#define BCHP_XPT_PB_TOP_REG_START                          0x00208000
+#define BCHP_XPT_PB_TOP_REG_END                            0x00208074
+#define BCHP_XPT_PB0_REG_START                             0x00208100
+#define BCHP_XPT_PB0_REG_END                               0x00208174
+#define BCHP_XPT_PB1_REG_START                             0x00208180
+#define BCHP_XPT_PB1_REG_END                               0x002081f4
+#define BCHP_XPT_PB2_REG_START                             0x00208200
+#define BCHP_XPT_PB2_REG_END                               0x00208274
+#define BCHP_XPT_PB3_REG_START                             0x00208280
+#define BCHP_XPT_PB3_REG_END                               0x002082f4
+#define BCHP_XPT_PB4_REG_START                             0x00208300
+#define BCHP_XPT_PB4_REG_END                               0x00208374
+#define BCHP_XPT_PB5_REG_START                             0x00208380
+#define BCHP_XPT_PB5_REG_END                               0x002083f4
+#define BCHP_XPT_PCROFFSET_REG_START                       0x0020c000
+#define BCHP_XPT_PCROFFSET_REG_END                         0x0020d8fc
+#define BCHP_XPT_FULL_PID_PARSER_REG_START                 0x00210000
+#define BCHP_XPT_FULL_PID_PARSER_REG_END                   0x00212050
+#define BCHP_XPT_RSBUFF_REG_START                          0x00215000
+#define BCHP_XPT_RSBUFF_REG_END                            0x00215b44
+#define BCHP_XPT_XCBUFF_REG_START                          0x00216000
+#define BCHP_XPT_XCBUFF_REG_END                            0x00217ccc
+#define BCHP_XPT_MSG_REG_START                             0x00218000
+#define BCHP_XPT_MSG_REG_END                               0x0021e014
+#define BCHP_XPT_RAVE_REG_START                            0x00220000
+#define BCHP_XPT_RAVE_REG_END                              0x00228dac
+#define BCHP_XPT_XPU_REG_START                             0x00230000
+#define BCHP_XPT_XPU_REG_END                               0x002347fc
+#define BCHP_XPT_SECURE_BUS_IF_REG_START                   0x0023f000
+#define BCHP_XPT_SECURE_BUS_IF_REG_END                     0x0023f000
+#define BCHP_BSP_CMDBUF_REG_START                          0x00329800
+#define BCHP_BSP_CMDBUF_REG_END                            0x00329ffc
+#define BCHP_BSP_GLB_CONTROL_REG_START                     0x0032b000
+#define BCHP_BSP_GLB_CONTROL_REG_END                       0x0032b098
+#define BCHP_BSP_PKL_REG_START                             0x0032b300
+#define BCHP_BSP_PKL_REG_END                               0x0032b37c
+#define BCHP_BSP_INST_PATCH_CTRL_REG_START                 0x0032b400
+#define BCHP_BSP_INST_PATCH_CTRL_REG_END                   0x0032b404
+#define BCHP_BSP_CONTROL_INTR2_REG_START                   0x0032b800
+#define BCHP_BSP_CONTROL_INTR2_REG_END                     0x0032b82c
+#define BCHP_BSP_INST_PATCHRAM_REG_START                   0x0032c000
+#define BCHP_BSP_INST_PATCHRAM_REG_END                     0x0032fffc
+#define BCHP_XPT_SECURITY_REG_START                        0x00360000
+#define BCHP_XPT_SECURITY_REG_END                          0x0036fffc
+#define BCHP_MMSCRAM_REG_START                             0x00370000
+#define BCHP_MMSCRAM_REG_END                               0x00371ffc
+#define BCHP_MEM_DMA_SECURE_REG_START                      0x00372000
+#define BCHP_MEM_DMA_SECURE_REG_END                        0x0037200c
+#define BCHP_SECTOP_GRB_REG_START                          0x00374000
+#define BCHP_SECTOP_GRB_REG_END                            0x0037400c
+#define BCHP_JTAG_OTP_REG_START                            0x00374100
+#define BCHP_JTAG_OTP_REG_END                              0x00374138
+#define BCHP_MEM_DMA_0_REG_START                           0x00374200
+#define BCHP_MEM_DMA_0_REG_END                             0x00374224
+#define BCHP_XPT_SECURITY_NS_REG_START                     0x00374300
+#define BCHP_XPT_SECURITY_NS_REG_END                       0x00374310
+#define BCHP_MEMC_GEN_0_REG_START                          0x003b0000
+#define BCHP_MEMC_GEN_0_REG_END                            0x003b04f8
+#define BCHP_MEMC_ARB_0_REG_START                          0x003b1000
+#define BCHP_MEMC_ARB_0_REG_END                            0x003b1244
+#define BCHP_MEMC_DDR_0_REG_START                          0x003b2000
+#define BCHP_MEMC_DDR_0_REG_END                            0x003b22fc
+#define BCHP_MEMC_L2_0_REG_START                           0x003b3000
+#define BCHP_MEMC_L2_0_REG_END                             0x003b302c
+#define BCHP_MEMC_L2_1_0_REG_START                         0x003b3800
+#define BCHP_MEMC_L2_1_0_REG_END                           0x003b382c
+#define BCHP_MEMC_RGRB_0_REG_START                         0x003b4000
+#define BCHP_MEMC_RGRB_0_REG_END                           0x003b4010
+#define BCHP_MEMC_MISC_0_REG_START                         0x003b5000
+#define BCHP_MEMC_MISC_0_REG_END                           0x003b5010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_START            0x003b6000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_END              0x003b60c4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_START             0x003b6200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_END               0x003b63b0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_REG_START             0x003b6400
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_REG_END               0x003b65b0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_START         0x003b8000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_END           0x003b8138
+#define BCHP_S_MEMC_0_REG_START                            0x003ba000
+#define BCHP_S_MEMC_0_REG_END                              0x003ba220
+#define BCHP_SUN_GISB_ARB_REG_START                        0x00400000
+#define BCHP_SUN_GISB_ARB_REG_END                          0x004000d8
+#define BCHP_SUN_RGR_REG_START                             0x00400400
+#define BCHP_SUN_RGR_REG_END                               0x00400410
+#define BCHP_SUN_RG_REG_START                              0x00400800
+#define BCHP_SUN_RG_REG_END                                0x0040080c
+#define BCHP_TPCAP_REG_START                               0x00400c00
+#define BCHP_TPCAP_REG_END                                 0x00400c84
+#define BCHP_SUN_L2_REG_START                              0x00403000
+#define BCHP_SUN_L2_REG_END                                0x0040302c
+#define BCHP_SM_L2_REG_START                               0x00403400
+#define BCHP_SM_L2_REG_END                                 0x0040342c
+#define BCHP_SM_REG_START                                  0x00403800
+#define BCHP_SM_REG_END                                    0x00403824
+#define BCHP_SM_FAST_REG_START                             0x00403c00
+#define BCHP_SM_FAST_REG_END                               0x00403c18
+#define BCHP_SUN_TOP_CTRL_REG_START                        0x00404000
+#define BCHP_SUN_TOP_CTRL_REG_END                          0x00404518
+#define BCHP_IRB_REG_START                                 0x00406000
+#define BCHP_IRB_REG_END                                   0x00406138
+#define BCHP_PM_REG_START                                  0x00406180
+#define BCHP_PM_REG_END                                    0x00406188
+#define BCHP_BSCD_REG_START                                0x00406200
+#define BCHP_BSCD_REG_END                                  0x00406254
+#define BCHP_BSCE_REG_START                                0x00406280
+#define BCHP_BSCE_REG_END                                  0x004062d4
+#define BCHP_PWM_REG_START                                 0x00406400
+#define BCHP_PWM_REG_END                                   0x00406424
+#define BCHP_GIO_REG_START                                 0x00406500
+#define BCHP_GIO_REG_END                                   0x0040659c
+#define BCHP_IRQ0_REG_START                                0x00406680
+#define BCHP_IRQ0_REG_END                                  0x00406684
+#define BCHP_IRQ1_REG_START                                0x00406688
+#define BCHP_IRQ1_REG_END                                  0x0040668c
+#define BCHP_TIMER_REG_START                               0x004066c0
+#define BCHP_TIMER_REG_END                                 0x004066fc
+#define BCHP_UARTA_REG_START                               0x00406700
+#define BCHP_UARTA_REG_END                                 0x0040671c
+#define BCHP_UARTB_REG_START                               0x00406740
+#define BCHP_UARTB_REG_END                                 0x0040675c
+#define BCHP_UARTC_REG_START                               0x00406780
+#define BCHP_UARTC_REG_END                                 0x0040679c
+#define BCHP_SCA_REG_START                                 0x00406800
+#define BCHP_SCA_REG_END                                   0x004068bc
+#define BCHP_SCB_REG_START                                 0x00406900
+#define BCHP_SCB_REG_END                                   0x004069bc
+#define BCHP_SCIRQ0_REG_START                              0x004069c0
+#define BCHP_SCIRQ0_REG_END                                0x004069c4
+#define BCHP_SCIRQ1_REG_START                              0x004069c8
+#define BCHP_SCIRQ1_REG_END                                0x004069cc
+#define BCHP_MCIF_REG_START                                0x00406c00
+#define BCHP_MCIF_REG_END                                  0x00406c20
+#define BCHP_MCIF_INTR2_REG_START                          0x00406c40
+#define BCHP_MCIF_INTR2_REG_END                            0x00406c6c
+#define BCHP_UPG_AUX_INTR2_REG_START                       0x00406c80
+#define BCHP_UPG_AUX_INTR2_REG_END                         0x00406cac
+#define BCHP_UPG_UART_DMA_REG_START                        0x00406e00
+#define BCHP_UPG_UART_DMA_REG_END                          0x00406e28
+#define BCHP_AON_CTRL_REG_START                            0x00408000
+#define BCHP_AON_CTRL_REG_END                              0x004083fc
+#define BCHP_AON_L2_REG_START                              0x00408400
+#define BCHP_AON_L2_REG_END                                0x0040842c
+#define BCHP_AON_PM_L2_REG_START                           0x00408440
+#define BCHP_AON_PM_L2_REG_END                             0x0040846c
+#define BCHP_AON_PIN_CTRL_REG_START                        0x00408500
+#define BCHP_AON_PIN_CTRL_REG_END                          0x0040851c
+#define BCHP_AON_HDMI_TX_REG_START                         0x00408600
+#define BCHP_AON_HDMI_TX_REG_END                           0x00408698
+#define BCHP_AON_HDMI_RX_REG_START                         0x00408800
+#define BCHP_AON_HDMI_RX_REG_END                           0x00408904
+#define BCHP_LDK_REG_START                                 0x00409000
+#define BCHP_LDK_REG_END                                   0x0040903c
+#define BCHP_PM_AON_REG_START                              0x00409040
+#define BCHP_PM_AON_REG_END                                0x00409048
+#define BCHP_ICAP_REG_START                                0x00409080
+#define BCHP_ICAP_REG_END                                  0x004090bc
+#define BCHP_KBD1_REG_START                                0x004090c0
+#define BCHP_KBD1_REG_END                                  0x004090fc
+#define BCHP_KBD2_REG_START                                0x00409100
+#define BCHP_KBD2_REG_END                                  0x0040913c
+#define BCHP_KBD3_REG_START                                0x00409140
+#define BCHP_KBD3_REG_END                                  0x0040917c
+#define BCHP_BSCA_REG_START                                0x00409180
+#define BCHP_BSCA_REG_END                                  0x004091d4
+#define BCHP_BSCB_REG_START                                0x00409200
+#define BCHP_BSCB_REG_END                                  0x00409254
+#define BCHP_BSCC_REG_START                                0x00409280
+#define BCHP_BSCC_REG_END                                  0x004092d4
+#define BCHP_MSPI_REG_START                                0x00409400
+#define BCHP_MSPI_REG_END                                  0x0040957c
+#define BCHP_IRQ0_AON_REG_START                            0x00409600
+#define BCHP_IRQ0_AON_REG_END                              0x00409604
+#define BCHP_IRQ1_AON_REG_START                            0x00409608
+#define BCHP_IRQ1_AON_REG_END                              0x0040960c
+#define BCHP_GIO_AON_REG_START                             0x00409800
+#define BCHP_GIO_AON_REG_END                               0x0040985c
+#define BCHP_BICAP_REG_START                               0x00409a00
+#define BCHP_BICAP_REG_END                                 0x00409a38
+#define BCHP_UPG_AUX_AON_INTR2_REG_START                   0x00409a40
+#define BCHP_UPG_AUX_AON_INTR2_REG_END                     0x00409a6c
+#define BCHP_WKTMR_REG_START                               0x00409a80
+#define BCHP_WKTMR_REG_END                                 0x00409a90
+#define BCHP_SYS_GISB_ARB_SEC_REG_START                    0x0040e000
+#define BCHP_SYS_GISB_ARB_SEC_REG_END                      0x0040e0b4
+#define BCHP_SYS_TOP_CTRL_SEC_REG_START                    0x0040e700
+#define BCHP_SYS_TOP_CTRL_SEC_REG_END                      0x0040e704
+#define BCHP_AON_CTRL_SECURE_REG_START                     0x0040e800
+#define BCHP_AON_CTRL_SECURE_REG_END                       0x0040e87c
+#define BCHP_EBI_REG_START                                 0x00410800
+#define BCHP_EBI_REG_END                                   0x00410bfc
+#define BCHP_HIF_INTR2_REG_START                           0x00411000
+#define BCHP_HIF_INTR2_REG_END                             0x0041102c
+#define BCHP_IPI0_INTR2_REG_START                          0x00411100
+#define BCHP_IPI0_INTR2_REG_END                            0x0041112c
+#define BCHP_IPI1_INTR2_REG_START                          0x00411200
+#define BCHP_IPI1_INTR2_REG_END                            0x0041122c
+#define BCHP_HIF_CPU_INTR1_REG_START                       0x00411400
+#define BCHP_HIF_CPU_INTR1_REG_END                         0x0041142c
+#define BCHP_HIF_CPU_TP1_INTR1_REG_START                   0x00411600
+#define BCHP_HIF_CPU_TP1_INTR1_REG_END                     0x0041162c
+#define BCHP_HIF_RGR_REG_START                             0x00411800
+#define BCHP_HIF_RGR_REG_END                               0x00411810
+#define BCHP_HIF_SPI_INTR2_REG_START                       0x00411d00
+#define BCHP_HIF_SPI_INTR2_REG_END                         0x00411d2c
+#define BCHP_HIF_TOP_CTRL_REG_START                        0x00412400
+#define BCHP_HIF_TOP_CTRL_REG_END                          0x0041242c
+#define BCHP_NAND_REG_START                                0x00412800
+#define BCHP_NAND_REG_END                                  0x00412dfc
+#define BCHP_EDU_REG_START                                 0x00412e00
+#define BCHP_EDU_REG_END                                   0x00412e20
+#define BCHP_BSPI_REG_START                                0x00413000
+#define BCHP_BSPI_REG_END                                  0x0041304c
+#define BCHP_BSPI_RAF_REG_START                            0x00413100
+#define BCHP_BSPI_RAF_REG_END                              0x00413120
+#define BCHP_HIF_MSPI_REG_START                            0x00413200
+#define BCHP_HIF_MSPI_REG_END                              0x00413384
+#define BCHP_SDIO_0_HOST_REG_START                         0x00413500
+#define BCHP_SDIO_0_HOST_REG_END                           0x004135fc
+#define BCHP_SDIO_0_CFG_REG_START                          0x00413600
+#define BCHP_SDIO_0_CFG_REG_END                            0x004136fc
+#define BCHP_SDIO_1_HOST_REG_START                         0x00413700
+#define BCHP_SDIO_1_HOST_REG_END                           0x004137fc
+#define BCHP_SDIO_1_CFG_REG_START                          0x00413800
+#define BCHP_SDIO_1_CFG_REG_END                            0x004138fc
+#define BCHP_SDIO_1_BOOT_REG_START                         0x00413900
+#define BCHP_SDIO_1_BOOT_REG_END                           0x0041393c
+#define BCHP_MICH_REG_START                                0x00414000
+#define BCHP_MICH_REG_END                                  0x00414000
+#define BCHP_HIF_SECURE_CTRL_REG_START                     0x00414100
+#define BCHP_HIF_SECURE_CTRL_REG_END                       0x00414100
+#define BCHP_HIF_SECURE_BSPI_REG_START                     0x00414200
+#define BCHP_HIF_SECURE_BSPI_REG_END                       0x00414200
+#define BCHP_HIF_SECURE_LR_SPI_REG_START                   0x00414300
+#define BCHP_HIF_SECURE_LR_SPI_REG_END                     0x00414300
+#define BCHP_NAND_SECURE_REG_START                         0x00414400
+#define BCHP_NAND_SECURE_REG_END                           0x00414400
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_START        0x00414800
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_END          0x00414800
+#define BCHP_RFM_SYSCLK_REG_START                          0x00416000
+#define BCHP_RFM_SYSCLK_REG_END                            0x00416118
+#define BCHP_RFM_CLK27_REG_START                           0x00416000
+#define BCHP_RFM_CLK27_REG_END                             0x00416470
+#define BCHP_RFM_L2_REG_START                              0x00416c00
+#define BCHP_RFM_L2_REG_END                                0x00416c2c
+#define BCHP_RFM_GRB_REG_START                             0x00417000
+#define BCHP_RFM_GRB_REG_END                               0x0041700c
+#define BCHP_CLKGEN_REG_START                              0x00420000
+#define BCHP_CLKGEN_REG_END                                0x00420518
+#define BCHP_VCXO_0_RM_REG_START                           0x00422800
+#define BCHP_VCXO_0_RM_REG_END                             0x0042282c
+#define BCHP_VCXO_1_RM_REG_START                           0x00422880
+#define BCHP_VCXO_1_RM_REG_END                             0x004228ac
+#define BCHP_AVS_HW_MNTR_REG_START                         0x00423000
+#define BCHP_AVS_HW_MNTR_REG_END                           0x00423074
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_START                 0x00423100
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_END                   0x0042311c
+#define BCHP_AVS_ASB_REGISTERS_REG_START                   0x00423200
+#define BCHP_AVS_ASB_REGISTERS_REG_END                     0x00423218
+#define BCHP_AVS_RO_REGISTERS_0_REG_START                  0x00423300
+#define BCHP_AVS_RO_REGISTERS_0_REG_END                    0x004233dc
+#define BCHP_AVS_RO_REGISTERS_1_REG_START                  0x00423400
+#define BCHP_AVS_RO_REGISTERS_1_REG_END                    0x0042348c
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_START                0x00423500
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_END                  0x004235e4
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_START                0x00423600
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_END                  0x004236e4
+#define BCHP_CLKGEN_INTR2_REG_START                        0x00424000
+#define BCHP_CLKGEN_INTR2_REG_END                          0x0042402c
+#define BCHP_CLKGEN_GR_REG_START                           0x00424800
+#define BCHP_CLKGEN_GR_REG_END                             0x0042480c
+#define BCHP_SID_REG_START                                 0x00440100
+#define BCHP_SID_REG_END                                   0x0044019c
+#define BCHP_SID_RLE_REG_START                             0x00440300
+#define BCHP_SID_RLE_REG_END                               0x0044039c
+#define BCHP_SID_DQ_REG_START                              0x00440400
+#define BCHP_SID_DQ_REG_END                                0x004404bc
+#define BCHP_SID_STRM_REG_START                            0x00440800
+#define BCHP_SID_STRM_REG_END                              0x0044087c
+#define BCHP_SID_OUTPUT_REG_START                          0x00440c00
+#define BCHP_SID_OUTPUT_REG_END                            0x00440c40
+#define BCHP_SID_ARC_REG_START                             0x00440f00
+#define BCHP_SID_ARC_REG_END                               0x00440f3c
+#define BCHP_SID_ARCDMA_REG_START                          0x00441800
+#define BCHP_SID_ARCDMA_REG_END                            0x00441840
+#define BCHP_SID_DMARAM_REG_START                          0x00441a00
+#define BCHP_SID_DMARAM_REG_END                            0x00441bfc
+#define BCHP_SID_PEEK_BITS_REG_START                       0x00442b00
+#define BCHP_SID_PEEK_BITS_REG_END                         0x00442b3c
+#define BCHP_SID_EXTRACT_BITS_REG_START                    0x00442b40
+#define BCHP_SID_EXTRACT_BITS_REG_END                      0x00442b7c
+#define BCHP_SID_HUFF_SYMB_REG_START                       0x00443000
+#define BCHP_SID_HUFF_SYMB_REG_END                         0x004437fc
+#define BCHP_SID_HUFF_CODE_REG_START                       0x00443900
+#define BCHP_SID_HUFF_CODE_REG_END                         0x004439fc
+#define BCHP_SID_SYMB_REG_START                            0x00443a00
+#define BCHP_SID_SYMB_REG_END                              0x00443a10
+#define BCHP_SID_SYMB_JPEG_REG_START                       0x00443a80
+#define BCHP_SID_SYMB_JPEG_REG_END                         0x00443a8c
+#define BCHP_SID_BIGRAM_REG_START                          0x00448000
+#define BCHP_SID_BIGRAM_REG_END                            0x0044fffc
+#define BCHP_SID_ARC_DBG_REG_START                         0x00451000
+#define BCHP_SID_ARC_DBG_REG_END                           0x00451010
+#define BCHP_SID_ARC_CORE_REG_START                        0x00455000
+#define BCHP_SID_ARC_CORE_REG_END                          0x00455014
+#define BCHP_M2MC_REG_START                                0x00460000
+#define BCHP_M2MC_REG_END                                  0x004607fc
+#define BCHP_V3D_CTL_REG_START                             0x00461000
+#define BCHP_V3D_CTL_REG_END                               0x00461040
+#define BCHP_V3D_CLE_REG_START                             0x00461100
+#define BCHP_V3D_CLE_REG_END                               0x00461138
+#define BCHP_V3D_PTB_REG_START                             0x00461300
+#define BCHP_V3D_PTB_REG_END                               0x00461310
+#define BCHP_V3D_QPS_REG_START                             0x00461400
+#define BCHP_V3D_QPS_REG_END                               0x0046143c
+#define BCHP_V3D_VPM_REG_START                             0x00461500
+#define BCHP_V3D_VPM_REG_END                               0x00461504
+#define BCHP_V3D_PCTR_REG_START                            0x00461600
+#define BCHP_V3D_PCTR_REG_END                              0x004616fc
+#define BCHP_V3D_GCA_REG_START                             0x00461a00
+#define BCHP_V3D_GCA_REG_END                               0x00461a54
+#define BCHP_V3D_DBG_REG_START                             0x00461e00
+#define BCHP_V3D_DBG_REG_END                               0x00461f20
+#define BCHP_GFX_L2_REG_START                              0x00463000
+#define BCHP_GFX_L2_REG_END                                0x0046302c
+#define BCHP_GFX_GR_REG_START                              0x00464000
+#define BCHP_GFX_GR_REG_END                                0x0046400c
+#define BCHP_SICH_REG_START                                0x00468000
+#define BCHP_SICH_REG_END                                  0x0046803c
+#define BCHP_USB_CAPS_REG_START                            0x00480000
+#define BCHP_USB_CAPS_REG_END                              0x0048002c
+#define BCHP_USB_GR_BRIDGE_REG_START                       0x00480100
+#define BCHP_USB_GR_BRIDGE_REG_END                         0x0048010c
+#define BCHP_USB_INTR2_REG_START                           0x00480180
+#define BCHP_USB_INTR2_REG_END                             0x004801ac
+#define BCHP_USB_CTRL_REG_START                            0x00480200
+#define BCHP_USB_CTRL_REG_END                              0x00480238
+#define BCHP_USB_EHCI_REG_START                            0x00480300
+#define BCHP_USB_EHCI_REG_END                              0x004803a4
+#define BCHP_USB_OHCI_REG_START                            0x00480400
+#define BCHP_USB_OHCI_REG_END                              0x00480454
+#define BCHP_USB_EHCI1_REG_START                           0x00480500
+#define BCHP_USB_EHCI1_REG_END                             0x004805a4
+#define BCHP_USB_OHCI1_REG_START                           0x00480600
+#define BCHP_USB_OHCI1_REG_END                             0x00480654
+#define BCHP_USB_OTG_REG_START                             0x00482000
+#define BCHP_USB_OTG_REG_END                               0x00482e00
+#define BCHP_USB1_CAPS_REG_START                           0x00490000
+#define BCHP_USB1_CAPS_REG_END                             0x0049002c
+#define BCHP_USB1_GR_BRIDGE_REG_START                      0x00490100
+#define BCHP_USB1_GR_BRIDGE_REG_END                        0x0049010c
+#define BCHP_USB1_INTR2_REG_START                          0x00490180
+#define BCHP_USB1_INTR2_REG_END                            0x004901ac
+#define BCHP_USB1_CTRL_REG_START                           0x00490200
+#define BCHP_USB1_CTRL_REG_END                             0x00490238
+#define BCHP_USB1_EHCI_REG_START                           0x00490300
+#define BCHP_USB1_EHCI_REG_END                             0x004903a4
+#define BCHP_USB1_OHCI_REG_START                           0x00490400
+#define BCHP_USB1_OHCI_REG_END                             0x00490454
+#define BCHP_USB1_EHCI1_REG_START                          0x00490500
+#define BCHP_USB1_EHCI1_REG_END                            0x004905a4
+#define BCHP_USB1_OHCI1_REG_START                          0x00490600
+#define BCHP_USB1_OHCI1_REG_END                            0x00490654
+#define BCHP_USB1_OTG_REG_START                            0x00492000
+#define BCHP_USB1_OTG_REG_END                              0x00492e00
+#define BCHP_BOOTROM_REG_START                             0x00500000
+#define BCHP_BOOTROM_REG_END                               0x00500ffc
+#define BCHP_MFD_0_REG_START                               0x00600000
+#define BCHP_MFD_0_REG_END                                 0x00600264
+#define BCHP_MFD_1_REG_START                               0x00600400
+#define BCHP_MFD_1_REG_END                                 0x006005fc
+#define BCHP_VFD_0_REG_START                               0x00601000
+#define BCHP_VFD_0_REG_END                                 0x006011fc
+#define BCHP_VFD_1_REG_START                               0x00601200
+#define BCHP_VFD_1_REG_END                                 0x006013fc
+#define BCHP_VFD_2_REG_START                               0x00601400
+#define BCHP_VFD_2_REG_END                                 0x006015fc
+#define BCHP_VFD_3_REG_START                               0x00601600
+#define BCHP_VFD_3_REG_END                                 0x006017fc
+#define BCHP_RDC_REG_START                                 0x00602000
+#define BCHP_RDC_REG_END                                   0x006029fc
+#define BCHP_BVNF_INTR2_0_REG_START                        0x00603000
+#define BCHP_BVNF_INTR2_0_REG_END                          0x0060302c
+#define BCHP_BVNF_INTR2_1_REG_START                        0x00603100
+#define BCHP_BVNF_INTR2_1_REG_END                          0x0060312c
+#define BCHP_BVNF_INTR2_3_REG_START                        0x00603300
+#define BCHP_BVNF_INTR2_3_REG_END                          0x0060332c
+#define BCHP_BVNF_INTR2_4_REG_START                        0x00603400
+#define BCHP_BVNF_INTR2_4_REG_END                          0x0060342c
+#define BCHP_BVNF_INTR2_5_REG_START                        0x00603500
+#define BCHP_BVNF_INTR2_5_REG_END                          0x0060352c
+#define BCHP_BVNF_INTR2_6_REG_START                        0x00603600
+#define BCHP_BVNF_INTR2_6_REG_END                          0x0060362c
+#define BCHP_BVNF_INTR2_7_REG_START                        0x00603700
+#define BCHP_BVNF_INTR2_7_REG_END                          0x0060372c
+#define BCHP_FMISC_REG_START                               0x00604000
+#define BCHP_FMISC_REG_END                                 0x00604020
+#define BCHP_SCL_0_REG_START                               0x00620000
+#define BCHP_SCL_0_REG_END                                 0x006203fc
+#define BCHP_SCL_1_REG_START                               0x00620400
+#define BCHP_SCL_1_REG_END                                 0x006207fc
+#define BCHP_SCL_2_REG_START                               0x00620800
+#define BCHP_SCL_2_REG_END                                 0x00620bfc
+#define BCHP_SCL_3_REG_START                               0x00620c00
+#define BCHP_SCL_3_REG_END                                 0x00620ffc
+#define BCHP_VNET_F_REG_START                              0x00622000
+#define BCHP_VNET_F_REG_END                                0x006220bc
+#define BCHP_VNET_B_REG_START                              0x00622200
+#define BCHP_VNET_B_REG_END                                0x006222bc
+#define BCHP_MMISC_REG_START                               0x00622800
+#define BCHP_MMISC_REG_END                                 0x00622820
+#define BCHP_LBOX_0_REG_START                              0x00625000
+#define BCHP_LBOX_0_REG_END                                0x00625070
+#define BCHP_LBOX_1_REG_START                              0x00625200
+#define BCHP_LBOX_1_REG_END                                0x00625270
+#define BCHP_BVNM_INTR2_0_REG_START                        0x00626000
+#define BCHP_BVNM_INTR2_0_REG_END                          0x0062602c
+#define BCHP_DNR_0_REG_START                               0x00627000
+#define BCHP_DNR_0_REG_END                                 0x006270a4
+#define BCHP_CAP_0_REG_START                               0x00640000
+#define BCHP_CAP_0_REG_END                                 0x0064007c
+#define BCHP_CAP_1_REG_START                               0x00640200
+#define BCHP_CAP_1_REG_END                                 0x0064027c
+#define BCHP_CAP_2_REG_START                               0x00640400
+#define BCHP_CAP_2_REG_END                                 0x0064047c
+#define BCHP_CAP_3_REG_START                               0x00640600
+#define BCHP_CAP_3_REG_END                                 0x0064067c
+#define BCHP_GFD_0_REG_START                               0x00641000
+#define BCHP_GFD_0_REG_END                                 0x00641228
+#define BCHP_GFD_1_REG_START                               0x00641400
+#define BCHP_GFD_1_REG_END                                 0x00641554
+#define BCHP_CMP_0_REG_START                               0x00642000
+#define BCHP_CMP_0_REG_END                                 0x006424b4
+#define BCHP_CMP_1_REG_START                               0x00642800
+#define BCHP_CMP_1_REG_END                                 0x00642cb4
+#define BCHP_TNT_CMP_0_V0_REG_START                        0x00643000
+#define BCHP_TNT_CMP_0_V0_REG_END                          0x006430a4
+#define BCHP_MASK_0_REG_START                              0x00643400
+#define BCHP_MASK_0_REG_END                                0x00643420
+#define BCHP_PEP_CMP_0_V0_REG_START                        0x00644000
+#define BCHP_PEP_CMP_0_V0_REG_END                          0x00645484
+#define BCHP_BVNB_INTR2_REG_START                          0x00646000
+#define BCHP_BVNB_INTR2_REG_END                            0x0064602c
+#define BCHP_BMISC_REG_START                               0x00646400
+#define BCHP_BMISC_REG_END                                 0x0064641c
+#define BCHP_MVP_TOP_0_REG_START                           0x00660000
+#define BCHP_MVP_TOP_0_REG_END                             0x0066002c
+#define BCHP_SIOB_0_REG_START                              0x00660200
+#define BCHP_SIOB_0_REG_END                                0x006602fc
+#define BCHP_HSCL_0_REG_START                              0x00660400
+#define BCHP_HSCL_0_REG_END                                0x006607fc
+#define BCHP_MDI_TOP_0_REG_START                           0x00662000
+#define BCHP_MDI_TOP_0_REG_END                             0x006620fc
+#define BCHP_MDI_PPB_0_REG_START                           0x00662800
+#define BCHP_MDI_PPB_0_REG_END                             0x00662bfc
+#define BCHP_MDI_FCN_0_REG_START                           0x00662c00
+#define BCHP_MDI_FCN_0_REG_END                             0x00662ffc
+#define BCHP_MISC_REG_START                                0x00680000
+#define BCHP_MISC_REG_END                                  0x006800a4
+#define BCHP_IT_0_REG_START                                0x00681000
+#define BCHP_IT_0_REG_END                                  0x006817fc
+#define BCHP_IT_1_REG_START                                0x00682000
+#define BCHP_IT_1_REG_END                                  0x006827fc
+#define BCHP_VF_0_REG_START                                0x00683000
+#define BCHP_VF_0_REG_END                                  0x00683134
+#define BCHP_VF_1_REG_START                                0x00683200
+#define BCHP_VF_1_REG_END                                  0x00683334
+#define BCHP_SECAM_0_REG_START                             0x00683400
+#define BCHP_SECAM_0_REG_END                               0x00683414
+#define BCHP_SM_0_REG_START                                0x00683480
+#define BCHP_SM_0_REG_END                                  0x006834ac
+#define BCHP_SDSRC_0_REG_START                             0x00683500
+#define BCHP_SDSRC_0_REG_END                               0x0068350c
+#define BCHP_HDSRC_0_REG_START                             0x00683520
+#define BCHP_HDSRC_0_REG_END                               0x0068353c
+#define BCHP_CSC_0_REG_START                               0x00683580
+#define BCHP_CSC_0_REG_END                                 0x006835b0
+#define BCHP_CSC_1_REG_START                               0x00683600
+#define BCHP_CSC_1_REG_END                                 0x00683630
+#define BCHP_RM_0_REG_START                                0x00683680
+#define BCHP_RM_0_REG_END                                  0x006836a4
+#define BCHP_RM_1_REG_START                                0x006836c0
+#define BCHP_RM_1_REG_END                                  0x006836e4
+#define BCHP_ANA_DEBUG_0_REG_START                         0x00683700
+#define BCHP_ANA_DEBUG_0_REG_END                           0x00683744
+#define BCHP_GRPD_0_REG_START                              0x00683800
+#define BCHP_GRPD_0_REG_END                                0x006838ec
+#define BCHP_DTRAM_0_REG_START                             0x00684000
+#define BCHP_DTRAM_0_REG_END                               0x0068447c
+#define BCHP_DVI_DTG_0_REG_START                           0x00684800
+#define BCHP_DVI_DTG_0_REG_END                             0x00684974
+#define BCHP_DVI_DTG_RM_0_REG_START                        0x00685000
+#define BCHP_DVI_DTG_RM_0_REG_END                          0x00685024
+#define BCHP_DVI_CSC_0_REG_START                           0x00685100
+#define BCHP_DVI_CSC_0_REG_END                             0x00685130
+#define BCHP_DVI_DVF_0_REG_START                           0x00685200
+#define BCHP_DVI_DVF_0_REG_END                             0x00685218
+#define BCHP_DVI_DEBUG_0_REG_START                         0x00685300
+#define BCHP_DVI_DEBUG_0_REG_END                           0x00685344
+#define BCHP_ITU656_DTG_0_REG_START                        0x00685800
+#define BCHP_ITU656_DTG_0_REG_END                          0x00685974
+#define BCHP_ITU656_CSC_0_REG_START                        0x00685a00
+#define BCHP_ITU656_CSC_0_REG_END                          0x00685a30
+#define BCHP_ITU656_DVF_0_REG_START                        0x00685b00
+#define BCHP_ITU656_DVF_0_REG_END                          0x00685b18
+#define BCHP_ITU656_0_REG_START                            0x00685c00
+#define BCHP_ITU656_0_REG_END                              0x00685c20
+#define BCHP_VEC_CFG_REG_START                             0x00686000
+#define BCHP_VEC_CFG_REG_END                               0x00686124
+#define BCHP_VIDEO_ENC_INTR2_REG_START                     0x00686400
+#define BCHP_VIDEO_ENC_INTR2_REG_END                       0x0068642c
+#define BCHP_VIDEO_ENC_TPG_0_REG_START                     0x00686500
+#define BCHP_VIDEO_ENC_TPG_0_REG_END                       0x00686518
+#define BCHP_DSCL_0_REG_START                              0x00686800
+#define BCHP_DSCL_0_REG_END                                0x00686bfc
+#define BCHP_VIDEO_ENC_DECIM_0_REG_START                   0x00687000
+#define BCHP_VIDEO_ENC_DECIM_0_REG_END                     0x00687008
+#define BCHP_DVP_TVG_0_REG_START                           0x00687100
+#define BCHP_DVP_TVG_0_REG_END                             0x00687188
+#define BCHP_VBI_ENC_REG_START                             0x00688000
+#define BCHP_VBI_ENC_REG_END                               0x00688074
+#define BCHP_CCE_0_REG_START                               0x00688400
+#define BCHP_CCE_0_REG_END                                 0x00688458
+#define BCHP_CCE_1_REG_START                               0x00688500
+#define BCHP_CCE_1_REG_END                                 0x00688558
+#define BCHP_WSE_0_REG_START                               0x00688600
+#define BCHP_WSE_0_REG_END                                 0x00688614
+#define BCHP_WSE_1_REG_START                               0x00688700
+#define BCHP_WSE_1_REG_END                                 0x00688714
+#define BCHP_CGMSAE_0_REG_START                            0x00688800
+#define BCHP_CGMSAE_0_REG_END                              0x00688858
+#define BCHP_CGMSAE_1_REG_START                            0x00688900
+#define BCHP_CGMSAE_1_REG_END                              0x00688958
+#define BCHP_TTE_0_REG_START                               0x00688a00
+#define BCHP_TTE_0_REG_END                                 0x00688a28
+#define BCHP_TTE_1_REG_START                               0x00688b00
+#define BCHP_TTE_1_REG_END                                 0x00688b28
+#define BCHP_GSE_0_REG_START                               0x00688c00
+#define BCHP_GSE_0_REG_END                                 0x00688c80
+#define BCHP_GSE_1_REG_START                               0x00688d00
+#define BCHP_GSE_1_REG_END                                 0x00688d80
+#define BCHP_AMOLE_0_REG_START                             0x00688e00
+#define BCHP_AMOLE_0_REG_END                               0x00688e8c
+#define BCHP_AMOLE_1_REG_START                             0x00688f00
+#define BCHP_AMOLE_1_REG_END                               0x00688f8c
+#define BCHP_CCE_ANCIL_0_REG_START                         0x00689000
+#define BCHP_CCE_ANCIL_0_REG_END                           0x00689054
+#define BCHP_WSE_ANCIL_0_REG_START                         0x00689100
+#define BCHP_WSE_ANCIL_0_REG_END                           0x0068910c
+#define BCHP_TTE_ANCIL_0_REG_START                         0x00689200
+#define BCHP_TTE_ANCIL_0_REG_END                           0x00689228
+#define BCHP_GSE_ANCIL_0_REG_START                         0x00689300
+#define BCHP_GSE_ANCIL_0_REG_END                           0x00689380
+#define BCHP_AMOLE_ANCIL_0_REG_START                       0x00689400
+#define BCHP_AMOLE_ANCIL_0_REG_END                         0x0068948c
+#define BCHP_ANCI656_ANCIL_0_REG_START                     0x00689500
+#define BCHP_ANCI656_ANCIL_0_REG_END                       0x00689524
+#define BCHP_DVP_HT_REG_START                              0x006a0000
+#define BCHP_DVP_HT_REG_END                                0x006a0118
+#define BCHP_HDMI_REG_START                                0x006a0800
+#define BCHP_HDMI_REG_END                                  0x006a0994
+#define BCHP_HDMI_TX_PHY_REG_START                         0x006a0a80
+#define BCHP_HDMI_TX_PHY_REG_END                           0x006a0ad8
+#define BCHP_HDMI_RM_REG_START                             0x006a0b00
+#define BCHP_HDMI_RM_REG_END                               0x006a0b2c
+#define BCHP_HDMI_TX_INTR2_REG_START                       0x006a0b40
+#define BCHP_HDMI_TX_INTR2_REG_END                         0x006a0b6c
+#define BCHP_HDMI_RAM_REG_START                            0x006a0c00
+#define BCHP_HDMI_RAM_REG_END                              0x006a0dfc
+#define BCHP_DVP_HR_REG_START                              0x006a4000
+#define BCHP_DVP_HR_REG_END                                0x006a41bc
+#define BCHP_DVP_HR_INTR2_REG_START                        0x006a41c0
+#define BCHP_DVP_HR_INTR2_REG_END                          0x006a41ec
+#define BCHP_DVP_HR_DVP_OTP_REG_START                      0x006a4200
+#define BCHP_DVP_HR_DVP_OTP_REG_END                        0x006a4240
+#define BCHP_DVP_HR_KEY_RAM_REG_START                      0x006a4300
+#define BCHP_DVP_HR_KEY_RAM_REG_END                        0x006a4314
+#define BCHP_HDMI_RX_FE_0_REG_START                        0x006a4400
+#define BCHP_HDMI_RX_FE_0_REG_END                          0x006a45fc
+#define BCHP_HDMI_RX_EQ_0_REG_START                        0x006a4600
+#define BCHP_HDMI_RX_EQ_0_REG_END                          0x006a47fc
+#define BCHP_HDMI_RX_0_REG_START                           0x006a6000
+#define BCHP_HDMI_RX_0_REG_END                             0x006a67bc
+#define BCHP_HDMI_RX_INTR2_0_REG_START                     0x006a67c0
+#define BCHP_HDMI_RX_INTR2_0_REG_END                       0x006a67ec
+#define BCHP_HD_DVI_0_REG_START                            0x006a8000
+#define BCHP_HD_DVI_0_REG_END                              0x006a81fc
+#define BCHP_DVP_HR_TMR_REG_START                          0x006a8cc0
+#define BCHP_DVP_HR_TMR_REG_END                            0x006a8cfc
+#define BCHP_BVN_RGR_REG_START                             0x006ac000
+#define BCHP_BVN_RGR_REG_END                               0x006ac010
+#define BCHP_GENET_0_SYS_REG_START                         0x00700000
+#define BCHP_GENET_0_SYS_REG_END                           0x0070000c
+#define BCHP_GENET_0_GR_BRIDGE_REG_START                   0x00700040
+#define BCHP_GENET_0_GR_BRIDGE_REG_END                     0x0070004c
+#define BCHP_GENET_0_EXT_REG_START                         0x00700080
+#define BCHP_GENET_0_EXT_REG_END                           0x00700098
+#define BCHP_GENET_0_INTRL2_0_REG_START                    0x00700200
+#define BCHP_GENET_0_INTRL2_0_REG_END                      0x0070022c
+#define BCHP_GENET_0_INTRL2_1_REG_START                    0x00700240
+#define BCHP_GENET_0_INTRL2_1_REG_END                      0x0070026c
+#define BCHP_GENET_0_RBUF_REG_START                        0x00700300
+#define BCHP_GENET_0_RBUF_REG_END                          0x007003b4
+#define BCHP_GENET_0_TBUF_REG_START                        0x00700600
+#define BCHP_GENET_0_TBUF_REG_END                          0x00700628
+#define BCHP_GENET_0_UMAC_REG_START                        0x00700800
+#define BCHP_GENET_0_UMAC_REG_END                          0x00700ed8
+#define BCHP_GENET_0_HFB_REG_START                         0x00708000
+#define BCHP_GENET_0_HFB_REG_END                           0x0070fc48
+#define BCHP_GENET_0_RDMA_REG_START                        0x00710000
+#define BCHP_GENET_0_RDMA_REG_END                          0x00710cd4
+#define BCHP_GENET_0_TDMA_REG_START                        0x00711000
+#define BCHP_GENET_0_TDMA_REG_END                          0x00711c84
+#define BCHP_GENET_1_SYS_REG_START                         0x00720000
+#define BCHP_GENET_1_SYS_REG_END                           0x0072000c
+#define BCHP_GENET_1_GR_BRIDGE_REG_START                   0x00720040
+#define BCHP_GENET_1_GR_BRIDGE_REG_END                     0x0072004c
+#define BCHP_GENET_1_EXT_REG_START                         0x00720080
+#define BCHP_GENET_1_EXT_REG_END                           0x00720098
+#define BCHP_GENET_1_INTRL2_0_REG_START                    0x00720200
+#define BCHP_GENET_1_INTRL2_0_REG_END                      0x0072022c
+#define BCHP_GENET_1_INTRL2_1_REG_START                    0x00720240
+#define BCHP_GENET_1_INTRL2_1_REG_END                      0x0072026c
+#define BCHP_GENET_1_RBUF_REG_START                        0x00720300
+#define BCHP_GENET_1_RBUF_REG_END                          0x007203b4
+#define BCHP_GENET_1_TBUF_REG_START                        0x00720600
+#define BCHP_GENET_1_TBUF_REG_END                          0x00720628
+#define BCHP_GENET_1_UMAC_REG_START                        0x00720800
+#define BCHP_GENET_1_UMAC_REG_END                          0x00720ed8
+#define BCHP_GENET_1_HFB_REG_START                         0x00728000
+#define BCHP_GENET_1_HFB_REG_END                           0x0072fc48
+#define BCHP_GENET_1_RDMA_REG_START                        0x00730000
+#define BCHP_GENET_1_RDMA_REG_END                          0x00730cd4
+#define BCHP_GENET_1_TDMA_REG_START                        0x00731000
+#define BCHP_GENET_1_TDMA_REG_END                          0x00731c84
+#define BCHP_RAAGA_DSP_RGR_REG_START                       0x00800000
+#define BCHP_RAAGA_DSP_RGR_REG_END                         0x00800008
+#define BCHP_RAAGA_DSP_MISC_REG_START                      0x00820000
+#define BCHP_RAAGA_DSP_MISC_REG_END                        0x0082044c
+#define BCHP_RAAGA_DSP_TIMERS_REG_START                    0x00821000
+#define BCHP_RAAGA_DSP_TIMERS_REG_END                      0x00821058
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START             0x00821080
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END               0x0082109c
+#define BCHP_RAAGA_DSP_PERI_SW_REG_START                   0x00821100
+#define BCHP_RAAGA_DSP_PERI_SW_REG_END                     0x00821154
+#define BCHP_RAAGA_DSP_DMA_REG_START                       0x00821400
+#define BCHP_RAAGA_DSP_DMA_REG_END                         0x00821664
+#define BCHP_RAAGA_DSP_ESR_SI_REG_START                    0x00822000
+#define BCHP_RAAGA_DSP_ESR_SI_REG_END                      0x00822014
+#define BCHP_RAAGA_DSP_INTH_REG_START                      0x00822200
+#define BCHP_RAAGA_DSP_INTH_REG_END                        0x0082222c
+#define BCHP_RAAGA_DSP_FW_INTH_REG_START                   0x00822400
+#define BCHP_RAAGA_DSP_FW_INTH_REG_END                     0x0082242c
+#define BCHP_RAAGA_DSP_FW_CFG_REG_START                    0x00823000
+#define BCHP_RAAGA_DSP_FW_CFG_REG_END                      0x0082357c
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START             0x00830000
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END               0x0083bffc
+#define BCHP_AUD_MISC_REG_START                            0x00880000
+#define BCHP_AUD_MISC_REG_END                              0x00880118
+#define BCHP_AUD_INTH_REG_START                            0x00880800
+#define BCHP_AUD_INTH_REG_END                              0x0088082c
+#define BCHP_AUD_FMM_BF_CTRL_REG_START                     0x008a0000
+#define BCHP_AUD_FMM_BF_CTRL_REG_END                       0x008a0d3c
+#define BCHP_AUD_FMM_BF_ESR_REG_START                      0x008a1000
+#define BCHP_AUD_FMM_BF_ESR_REG_END                        0x008a1074
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_START                   0x008a2000
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_END                     0x008a2bfc
+#define BCHP_AUD_FMM_SRC_ESR0_REG_START                    0x008a3000
+#define BCHP_AUD_FMM_SRC_ESR0_REG_END                      0x008a3014
+#define BCHP_AUD_FMM_DP_CTRL0_REG_START                    0x008a4000
+#define BCHP_AUD_FMM_DP_CTRL0_REG_END                      0x008a612c
+#define BCHP_AUD_FMM_DP_ESR0_REG_START                     0x008a7c00
+#define BCHP_AUD_FMM_DP_ESR0_REG_END                       0x008a7c2c
+#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_0_REG_START        0x008b0000
+#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_0_REG_END          0x008b0084
+#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_1_REG_START        0x008b0100
+#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_1_REG_END          0x008b0184
+#define BCHP_AUD_FMM_IOP_OUT_SPDIF_0_REG_START             0x008b0200
+#define BCHP_AUD_FMM_IOP_OUT_SPDIF_0_REG_END               0x008b0284
+#define BCHP_AUD_FMM_IOP_OUT_MAI_0_REG_START               0x008b0300
+#define BCHP_AUD_FMM_IOP_OUT_MAI_0_REG_END                 0x008b0384
+#define BCHP_HIFIDAC_CTRL_0_REG_START                      0x008b0800
+#define BCHP_HIFIDAC_CTRL_0_REG_END                        0x008b09fc
+#define BCHP_HIFIDAC_RM_0_REG_START                        0x008b0a00
+#define BCHP_HIFIDAC_RM_0_REG_END                          0x008b0a24
+#define BCHP_HIFIDAC_ESR_0_REG_START                       0x008b0b00
+#define BCHP_HIFIDAC_ESR_0_REG_END                         0x008b0b14
+#define BCHP_AUD_FMM_IOP_OUT_DAC_CTRL_0_REG_START          0x008b0c00
+#define BCHP_AUD_FMM_IOP_OUT_DAC_CTRL_0_REG_END            0x008b0c10
+#define BCHP_AUD_FMM_IOP_PLL_0_REG_START                   0x008b0d00
+#define BCHP_AUD_FMM_IOP_PLL_0_REG_END                     0x008b0d34
+#define BCHP_AUD_FMM_IOP_PLL_1_REG_START                   0x008b0e00
+#define BCHP_AUD_FMM_IOP_PLL_1_REG_END                     0x008b0e34
+#define BCHP_AUD_FMM_IOP_NCO_0_REG_START                   0x008b0f00
+#define BCHP_AUD_FMM_IOP_NCO_0_REG_END                     0x008b0f24
+#define BCHP_AUD_FMM_IOP_LOOPBACK_0_REG_START              0x008b1000
+#define BCHP_AUD_FMM_IOP_LOOPBACK_0_REG_END                0x008b1124
+#define BCHP_AUD_FMM_IOP_DUMMYSINK_0_REG_START             0x008b1200
+#define BCHP_AUD_FMM_IOP_DUMMYSINK_0_REG_END               0x008b1254
+#define BCHP_AUD_FMM_IOP_IN_SPDIF_0_REG_START              0x008b1800
+#define BCHP_AUD_FMM_IOP_IN_SPDIF_0_REG_END                0x008b18fc
+#define BCHP_AUD_FMM_IOP_IN_HDMI_0_REG_START               0x008b2000
+#define BCHP_AUD_FMM_IOP_IN_HDMI_0_REG_END                 0x008b20ac
+#define BCHP_AUD_FMM_IOP_IN_I2S_STEREO_0_REG_START         0x008b2800
+#define BCHP_AUD_FMM_IOP_IN_I2S_STEREO_0_REG_END           0x008b2864
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_0_REG_START       0x008b4000
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_0_REG_END         0x008b41fc
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_0_REG_START       0x008b4400
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_0_REG_END         0x008b4414
+#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_0_REG_START           0x008b6000
+#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_0_REG_END             0x008b7bfc
+#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_0_REG_START            0x008b7d00
+#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_0_REG_END              0x008b7d14
+#define BCHP_AUD_FMM_IOP_MISC_REG_START                    0x008b8100
+#define BCHP_AUD_FMM_IOP_MISC_REG_END                      0x008b8154
+#define BCHP_RAAGA_DSP_SEC0_REG_START                      0x00900000
+#define BCHP_RAAGA_DSP_SEC0_REG_END                        0x00900000
+#define BCHP_DATA_MEM_REG_START                            0x00a00000
+#define BCHP_DATA_MEM_REG_END                              0x00a47ffc
+#define BCHP_CNTL_MEM_REG_START                            0x00b20000
+#define BCHP_CNTL_MEM_REG_END                              0x00b67ffc
+#define BCHP_DMA_AHB_ECL_CMD_SCH0_REG_START                0x00bc0000
+#define BCHP_DMA_AHB_ECL_CMD_SCH0_REG_END                  0x00bc0000
+#define BCHP_DMA_AHB_ECL_CMD_SCH1_REG_START                0x00bc0010
+#define BCHP_DMA_AHB_ECL_CMD_SCH1_REG_END                  0x00bc0010
+#define BCHP_DMA_AHB_ECL_CMD_SCH2_REG_START                0x00bc0020
+#define BCHP_DMA_AHB_ECL_CMD_SCH2_REG_END                  0x00bc0020
+#define BCHP_DMA_AHB_ECL_CMD_SCH3_REG_START                0x00bc0030
+#define BCHP_DMA_AHB_ECL_CMD_SCH3_REG_END                  0x00bc0030
+#define BCHP_DMA_AHB_ECL_CMD_SCH4_REG_START                0x00bc0040
+#define BCHP_DMA_AHB_ECL_CMD_SCH4_REG_END                  0x00bc0040
+#define BCHP_DMA_AHB_ECL_CMD_SCH5_REG_START                0x00bc0050
+#define BCHP_DMA_AHB_ECL_CMD_SCH5_REG_END                  0x00bc0050
+#define BCHP_DMA_AHB_ECL_CMD_SCH6_REG_START                0x00bc0060
+#define BCHP_DMA_AHB_ECL_CMD_SCH6_REG_END                  0x00bc0060
+#define BCHP_DMA_AHB_ECL_CMD_SCH7_REG_START                0x00bc0070
+#define BCHP_DMA_AHB_ECL_CMD_SCH7_REG_END                  0x00bc0070
+#define BCHP_DMA_AHB_ECL_CMD_SCH8_REG_START                0x00bc0080
+#define BCHP_DMA_AHB_ECL_CMD_SCH8_REG_END                  0x00bc0080
+#define BCHP_DMA_AHB_ECL_CMD_SCH9_REG_START                0x00bc0090
+#define BCHP_DMA_AHB_ECL_CMD_SCH9_REG_END                  0x00bc0090
+#define BCHP_DMA_AHB_ECL_CMD_SCH10_REG_START               0x00bc00a0
+#define BCHP_DMA_AHB_ECL_CMD_SCH10_REG_END                 0x00bc00a0
+#define BCHP_DMA_AHB_ECL_CMD_SCH11_REG_START               0x00bc00b0
+#define BCHP_DMA_AHB_ECL_CMD_SCH11_REG_END                 0x00bc00b0
+#define BCHP_DMA_AHB_ECL_CMD_SCH12_REG_START               0x00bc00c0
+#define BCHP_DMA_AHB_ECL_CMD_SCH12_REG_END                 0x00bc00c0
+#define BCHP_DMA_AHB_ECL_CMD_SCH13_REG_START               0x00bc00d0
+#define BCHP_DMA_AHB_ECL_CMD_SCH13_REG_END                 0x00bc00d0
+#define BCHP_DMA_AHB_ECL_CMD_SCH14_REG_START               0x00bc00e0
+#define BCHP_DMA_AHB_ECL_CMD_SCH14_REG_END                 0x00bc00e0
+#define BCHP_DMA_AHB_ECL_CMD_SCH15_REG_START               0x00bc00f0
+#define BCHP_DMA_AHB_ECL_CMD_SCH15_REG_END                 0x00bc00f0
+#define BCHP_DMA_AHB_ECL_CMD_SCH16_REG_START               0x00bc0100
+#define BCHP_DMA_AHB_ECL_CMD_SCH16_REG_END                 0x00bc0100
+#define BCHP_DMA_AHB_ECL_CMD_SCH17_REG_START               0x00bc0110
+#define BCHP_DMA_AHB_ECL_CMD_SCH17_REG_END                 0x00bc0110
+#define BCHP_DMA_AHB_ECL_CMD_SCH18_REG_START               0x00bc0120
+#define BCHP_DMA_AHB_ECL_CMD_SCH18_REG_END                 0x00bc0120
+#define BCHP_DMA_AHB_ECL_CMD_SCH19_REG_START               0x00bc0130
+#define BCHP_DMA_AHB_ECL_CMD_SCH19_REG_END                 0x00bc0130
+#define BCHP_DMA_AHB_ECL_CMD_RX_REG_START                  0x00bc0800
+#define BCHP_DMA_AHB_ECL_CMD_RX_REG_END                    0x00bc0800
+#define BCHP_DMA_AHB_CMD_RX_SCH0_REG_START                 0x00bc4000
+#define BCHP_DMA_AHB_CMD_RX_SCH0_REG_END                   0x00bc4000
+#define BCHP_DMA_AHB_CMD_RX_SCH1_REG_START                 0x00bc4010
+#define BCHP_DMA_AHB_CMD_RX_SCH1_REG_END                   0x00bc4010
+#define BCHP_DMA_AHB_CMD_RX_SCH2_REG_START                 0x00bc4020
+#define BCHP_DMA_AHB_CMD_RX_SCH2_REG_END                   0x00bc4020
+#define BCHP_DMA_AHB_CMD_RX_SCH3_REG_START                 0x00bc4030
+#define BCHP_DMA_AHB_CMD_RX_SCH3_REG_END                   0x00bc4030
+#define BCHP_DMA_AHB_CMD_RX_SCH4_REG_START                 0x00bc4040
+#define BCHP_DMA_AHB_CMD_RX_SCH4_REG_END                   0x00bc4040
+#define BCHP_DMA_AHB_CMD_RX_SCH5_REG_START                 0x00bc4050
+#define BCHP_DMA_AHB_CMD_RX_SCH5_REG_END                   0x00bc4050
+#define BCHP_DMA_AHB_CMD_RX_SCH6_REG_START                 0x00bc4060
+#define BCHP_DMA_AHB_CMD_RX_SCH6_REG_END                   0x00bc4060
+#define BCHP_DMA_AHB_CMD_RX_SCH7_REG_START                 0x00bc4070
+#define BCHP_DMA_AHB_CMD_RX_SCH7_REG_END                   0x00bc4070
+#define BCHP_DMA_AHB_CMD_RX_SCH8_REG_START                 0x00bc4080
+#define BCHP_DMA_AHB_CMD_RX_SCH8_REG_END                   0x00bc4080
+#define BCHP_DMA_AHB_CMD_RX_SCH9_REG_START                 0x00bc4090
+#define BCHP_DMA_AHB_CMD_RX_SCH9_REG_END                   0x00bc4090
+#define BCHP_DMA_AHB_CMD_RX_SCH10_REG_START                0x00bc40a0
+#define BCHP_DMA_AHB_CMD_RX_SCH10_REG_END                  0x00bc40a0
+#define BCHP_DMA_AHB_CMD_RX_SCH11_REG_START                0x00bc40b0
+#define BCHP_DMA_AHB_CMD_RX_SCH11_REG_END                  0x00bc40b0
+#define BCHP_DMA_AHB_CMD_RX_SCH12_REG_START                0x00bc40c0
+#define BCHP_DMA_AHB_CMD_RX_SCH12_REG_END                  0x00bc40c0
+#define BCHP_DMA_AHB_CMD_RX_SCH13_REG_START                0x00bc40d0
+#define BCHP_DMA_AHB_CMD_RX_SCH13_REG_END                  0x00bc40d0
+#define BCHP_DMA_AHB_CMD_RX_SCH14_REG_START                0x00bc40e0
+#define BCHP_DMA_AHB_CMD_RX_SCH14_REG_END                  0x00bc40e0
+#define BCHP_DMA_AHB_CMD_RX_SCH15_REG_START                0x00bc40f0
+#define BCHP_DMA_AHB_CMD_RX_SCH15_REG_END                  0x00bc40f0
+#define BCHP_DMA_AHB_CMD_RX_SCH16_REG_START                0x00bc4100
+#define BCHP_DMA_AHB_CMD_RX_SCH16_REG_END                  0x00bc4100
+#define BCHP_DMA_AHB_CMD_RX_SCH17_REG_START                0x00bc4110
+#define BCHP_DMA_AHB_CMD_RX_SCH17_REG_END                  0x00bc4110
+#define BCHP_DMA_AHB_CMD_RX_SCH18_REG_START                0x00bc4120
+#define BCHP_DMA_AHB_CMD_RX_SCH18_REG_END                  0x00bc4120
+#define BCHP_DMA_AHB_CMD_RX_SCH19_REG_START                0x00bc4130
+#define BCHP_DMA_AHB_CMD_RX_SCH19_REG_END                  0x00bc4130
+#define BCHP_DMA_AHB_CMD_RES0_SCH0_REG_START               0x00bc4200
+#define BCHP_DMA_AHB_CMD_RES0_SCH0_REG_END                 0x00bc4200
+#define BCHP_DMA_AHB_CMD_RES0_SCH1_REG_START               0x00bc4210
+#define BCHP_DMA_AHB_CMD_RES0_SCH1_REG_END                 0x00bc4210
+#define BCHP_DMA_AHB_CMD_RES0_SCH2_REG_START               0x00bc4220
+#define BCHP_DMA_AHB_CMD_RES0_SCH2_REG_END                 0x00bc4220
+#define BCHP_DMA_AHB_CMD_RES0_SCH3_REG_START               0x00bc4230
+#define BCHP_DMA_AHB_CMD_RES0_SCH3_REG_END                 0x00bc4230
+#define BCHP_DMA_AHB_CMD_RES0_SCH4_REG_START               0x00bc4240
+#define BCHP_DMA_AHB_CMD_RES0_SCH4_REG_END                 0x00bc4240
+#define BCHP_DMA_AHB_CMD_RES0_SCH5_REG_START               0x00bc4250
+#define BCHP_DMA_AHB_CMD_RES0_SCH5_REG_END                 0x00bc4250
+#define BCHP_DMA_AHB_CMD_RES0_SCH6_REG_START               0x00bc4260
+#define BCHP_DMA_AHB_CMD_RES0_SCH6_REG_END                 0x00bc4260
+#define BCHP_DMA_AHB_CMD_RES0_SCH7_REG_START               0x00bc4270
+#define BCHP_DMA_AHB_CMD_RES0_SCH7_REG_END                 0x00bc4270
+#define BCHP_DMA_AHB_CMD_TX0_REG_START                     0x00bc4800
+#define BCHP_DMA_AHB_CMD_TX0_REG_END                       0x00bc4800
+#define BCHP_DMA_AHB_CMD_TX1_REG_START                     0x00bc4a00
+#define BCHP_DMA_AHB_CMD_TX1_REG_END                       0x00bc4a00
+#define BCHP_DMA_AHB_CMD_CONF0_REG_START                   0x00bc4c00
+#define BCHP_DMA_AHB_CMD_CONF0_REG_END                     0x00bc4c00
+#define BCHP_MAC_AHB_REG_START                             0x00bc5000
+#define BCHP_MAC_AHB_REG_END                               0x00bc500c
+#define BCHP_LLM_AHB_REG_START                             0x00bc8000
+#define BCHP_LLM_AHB_REG_END                               0x00bc805c
+#define BCHP_PHY_REG_START                                 0x00be0000
+#define BCHP_PHY_REG_END                                   0x00be47fc
+#define BCHP_ECL_REG_START                                 0x00be8000
+#define BCHP_ECL_REG_END                                   0x00bec924
+#define BCHP_DMA_IO2MEM_CH_ECL_TX_Global_REG_START         0x00bed000
+#define BCHP_DMA_IO2MEM_CH_ECL_TX_Global_REG_END           0x00bed014
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH0_REG_START      0x00bed040
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH0_REG_END        0x00bed06c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH1_REG_START      0x00bed080
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH1_REG_END        0x00bed0ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH2_REG_START      0x00bed0c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH2_REG_END        0x00bed0ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH3_REG_START      0x00bed100
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH3_REG_END        0x00bed12c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH4_REG_START      0x00bed140
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH4_REG_END        0x00bed16c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH5_REG_START      0x00bed180
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH5_REG_END        0x00bed1ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH6_REG_START      0x00bed1c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH6_REG_END        0x00bed1ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH7_REG_START      0x00bed200
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH7_REG_END        0x00bed22c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH8_REG_START      0x00bed240
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH8_REG_END        0x00bed26c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH9_REG_START      0x00bed280
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH9_REG_END        0x00bed2ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH10_REG_START     0x00bed2c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH10_REG_END       0x00bed2ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH11_REG_START     0x00bed300
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH11_REG_END       0x00bed32c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH12_REG_START     0x00bed340
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH12_REG_END       0x00bed36c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH13_REG_START     0x00bed380
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH13_REG_END       0x00bed3ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH14_REG_START     0x00bed3c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH14_REG_END       0x00bed3ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH15_REG_START     0x00bed400
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH15_REG_END       0x00bed42c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH16_REG_START     0x00bed440
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH16_REG_END       0x00bed46c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH17_REG_START     0x00bed480
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH17_REG_END       0x00bed4ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH18_REG_START     0x00bed4c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH18_REG_END       0x00bed4ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH19_REG_START     0x00bed500
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH19_REG_END       0x00bed52c
+#define BCHP_DMA_MEM2IO_CH_ECL_RX_REG_START                0x00bed800
+#define BCHP_DMA_MEM2IO_CH_ECL_RX_REG_END                  0x00bed828
+#define BCHP_GMII_REG_START                                0x00bedc00
+#define BCHP_GMII_REG_END                                  0x00bedc58
+#define BCHP_MAC_APB_REG_START                             0x00bf0000
+#define BCHP_MAC_APB_REG_END                               0x00bf14fc
+#define BCHP_DMA_IO2MEM_CH_MAC_RX_Global_REG_START         0x00bf4000
+#define BCHP_DMA_IO2MEM_CH_MAC_RX_Global_REG_END           0x00bf4014
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH0_REG_START      0x00bf4040
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH0_REG_END        0x00bf406c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH1_REG_START      0x00bf4080
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH1_REG_END        0x00bf40ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH2_REG_START      0x00bf40c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH2_REG_END        0x00bf40ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH3_REG_START      0x00bf4100
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH3_REG_END        0x00bf412c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH4_REG_START      0x00bf4140
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH4_REG_END        0x00bf416c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH5_REG_START      0x00bf4180
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH5_REG_END        0x00bf41ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH6_REG_START      0x00bf41c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH6_REG_END        0x00bf41ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH7_REG_START      0x00bf4200
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH7_REG_END        0x00bf422c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH8_REG_START      0x00bf4240
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH8_REG_END        0x00bf426c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH9_REG_START      0x00bf4280
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH9_REG_END        0x00bf42ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH10_REG_START     0x00bf42c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH10_REG_END       0x00bf42ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH11_REG_START     0x00bf4300
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH11_REG_END       0x00bf432c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH12_REG_START     0x00bf4340
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH12_REG_END       0x00bf436c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH13_REG_START     0x00bf4380
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH13_REG_END       0x00bf43ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH14_REG_START     0x00bf43c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH14_REG_END       0x00bf43ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH15_REG_START     0x00bf4400
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH15_REG_END       0x00bf442c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH16_REG_START     0x00bf4440
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH16_REG_END       0x00bf446c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH17_REG_START     0x00bf4480
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH17_REG_END       0x00bf44ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH18_REG_START     0x00bf44c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH18_REG_END       0x00bf44ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH19_REG_START     0x00bf4500
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH19_REG_END       0x00bf452c
+#define BCHP_DMA_IO2MEM_CH_PHY0_Global_REG_START           0x00bf4800
+#define BCHP_DMA_IO2MEM_CH_PHY0_Global_REG_END             0x00bf4814
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH0_REG_START        0x00bf4840
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH0_REG_END          0x00bf486c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH1_REG_START        0x00bf4880
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH1_REG_END          0x00bf48ac
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH2_REG_START        0x00bf48c0
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH2_REG_END          0x00bf48ec
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH3_REG_START        0x00bf4900
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH3_REG_END          0x00bf492c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH4_REG_START        0x00bf4940
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH4_REG_END          0x00bf496c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH5_REG_START        0x00bf4980
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH5_REG_END          0x00bf49ac
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH6_REG_START        0x00bf49c0
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH6_REG_END          0x00bf49ec
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH7_REG_START        0x00bf4a00
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH7_REG_END          0x00bf4a2c
+#define BCHP_DMA_MEM2IO_CH_MAC_TX0_REG_START               0x00bf6000
+#define BCHP_DMA_MEM2IO_CH_MAC_TX0_REG_END                 0x00bf6028
+#define BCHP_DMA_MEM2IO_CH_MAC_TX1_REG_START               0x00bf6400
+#define BCHP_DMA_MEM2IO_CH_MAC_TX1_REG_END                 0x00bf6428
+#define BCHP_DMA_MEM2IO_CH_PHY0_CONFIG_REG_START           0x00bf6800
+#define BCHP_DMA_MEM2IO_CH_PHY0_CONFIG_REG_END             0x00bf6828
+#define BCHP_MOCA_INTC_L2_HI_REG_START                     0x00bf8000
+#define BCHP_MOCA_INTC_L2_HI_REG_END                       0x00bf8584
+#define BCHP_MOCA_INTC_L2_LO_REG_START                     0x00bf8800
+#define BCHP_MOCA_INTC_L2_LO_REG_END                       0x00bf8d84
+#define BCHP_LLM_APB_REG_START                             0x00bfc000
+#define BCHP_LLM_APB_REG_END                               0x00bfd00c
+#define BCHP_TRX_REG_START                                 0x00bfe000
+#define BCHP_TRX_REG_END                                   0x00bfe0dc
+#define BCHP_MOCA_TIMER_REG_START                          0x00bfe400
+#define BCHP_MOCA_TIMER_REG_END                            0x00bfe4ec
+#define BCHP_MOCA_GPIO_REG_START                           0x00bfe800
+#define BCHP_MOCA_GPIO_REG_END                             0x00bfe818
+#define BCHP_EXTRAS_REG_START                              0x00bfec00
+#define BCHP_EXTRAS_REG_END                                0x00bfecec
+#define BCHP_MOCA_HOSTM2M_REG_START                        0x00bffc00
+#define BCHP_MOCA_HOSTM2M_REG_END                          0x00bffc0c
+#define BCHP_MOCA_L2_REG_START                             0x00bffc40
+#define BCHP_MOCA_L2_REG_END                               0x00bffc6c
+#define BCHP_MOCA_GR_BRIDGE_REG_START                      0x00bffc80
+#define BCHP_MOCA_GR_BRIDGE_REG_END                        0x00bffc8c
+#define BCHP_MOCA_HOSTMISC_REG_START                       0x00bffd00
+#define BCHP_MOCA_HOSTMISC_REG_END                         0x00bffd94
+
+
+/***************************************************************************
+ *AUD_FMM_MS_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK  0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
+
+/***************************************************************************
+ *AUD_FMM_OP_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
+ ***************************************************************************/
+/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD1
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_VFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *GFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK      0xffffffff
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT     0
+
+/***************************************************************************
+ *GFD_1
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD_1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK    0xffffffff
+#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT   0
+
+/***************************************************************************
+ *HIFIDAC_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_MUTE_USAGE - Mute usage
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *M2MC
+ ***************************************************************************/
+/***************************************************************************
+ *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK          0xffffffff
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT         0
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK              0xf0000000
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT             28
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK          0x0fffffe0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT         5
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK              0x0000001e
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT             1
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK           0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT          0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid   0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK              0xffff8000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT             15
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK   0x00004000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT  14
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK   0x00002000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT  13
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK         0x00000800
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT        11
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE   1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE  0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK  0x00000400
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK  0x00000200
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK          0x00000100
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT         8
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE   0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK   0x00000020
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT  5
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK     0x00000002
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK     0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT    0
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/***************************************************************************
+ *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK        0xffffffff
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT       0
+
+/***************************************************************************
+ *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK         0xffffffff
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT        0
+
+/***************************************************************************
+ *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_11_DST_COLOR_MATRIX_N - Linked-List Packet Word N for group DST_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_11_DST_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_12_OUTPUT_COLOR_MATRIX_N - Linked-List Packet Word N for group OUTPUT_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_12_OUTPUT_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_13_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *LIST_PKT_14_DST_CLUT - Linked-List Packet Word for group DST_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_14_DST_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_14_DST_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *TYPE_CLUT_COLOR_DATA - color data for color look up table
+ ***************************************************************************/
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK                  0xff000000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT                 24
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK                    0x00ff0000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT                   16
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK                  0x0000ff00
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT                 8
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK                   0x000000ff
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT                  0
+
+/***************************************************************************
+ *MEM_DMA
+ ***************************************************************************/
+/***************************************************************************
+ *DESC_WORD0 - MEM DMA Descriptor Word 0
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD0 :: READ_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD1 - MEM DMA Descriptor Word 1
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD1 :: WRITE_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_MASK                    0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD2 - MEM DMA Descriptor Word 2
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD2 :: INTR_ENABLE [31:31] */
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK                   0x80000000
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_SHIFT                  31
+
+/* MEM_DMA :: DESC_WORD2 :: LAST [30:30] */
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_MASK                          0x40000000
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_SHIFT                         30
+
+/* MEM_DMA :: DESC_WORD2 :: AUTO_APPEND [29:29] */
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_MASK                   0x20000000
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_SHIFT                  29
+
+/* MEM_DMA :: DESC_WORD2 :: reserved0 [28:25] */
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_MASK                     0x1e000000
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_SHIFT                    25
+
+/* MEM_DMA :: DESC_WORD2 :: TRANSFER_SIZE [24:00] */
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK                 0x01ffffff
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_SHIFT                0
+
+/***************************************************************************
+ *DESC_WORD3 - MEM DMA Descriptor Word 3
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD3 :: NEXT_DESC_ADDR [31:05] */
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK                0xffffffe0
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_SHIFT               5
+
+/* MEM_DMA :: DESC_WORD3 :: reserved0 [04:03] */
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_MASK                     0x00000018
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_SHIFT                    3
+
+/* MEM_DMA :: DESC_WORD3 :: READ_ENDIAN_MODE [02:02] */
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_MASK              0x00000004
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_SHIFT             2
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_BIG_ENDIAN        0
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_LITTLE_ENDIAN     1
+
+/* MEM_DMA :: DESC_WORD3 :: WRITE_ENDIAN_XLATE_MODE [01:00] */
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_MASK       0x00000003
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_SHIFT      0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_WORD_ALIGNED 0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_HALF_WORD_ALIGNED 1
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_BYTE_ALIGNED 2
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_reserved   3
+
+/***************************************************************************
+ *DESC_WORD4 - MEM DMA Descriptor Word 4
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD4 :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_SHIFT                    16
+
+/* MEM_DMA :: DESC_WORD4 :: SCRAM_CTRL_RSV [15:14] */
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_MASK                0x0000c000
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_SHIFT               14
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_END [13:13] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK                  0x00002000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_SHIFT                 13
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_START [12:12] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK                0x00001000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_SHIFT               12
+
+/* MEM_DMA :: DESC_WORD4 :: SG_ENABLE [11:11] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK                     0x00000800
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_SHIFT                    11
+
+/* MEM_DMA :: DESC_WORD4 :: ENC_DEC_INIT [10:10] */
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_MASK                  0x00000400
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_SHIFT                 10
+
+/* MEM_DMA :: DESC_WORD4 :: MODE_SEL [09:08] */
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_MASK                      0x00000300
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT                     8
+
+/* MEM_DMA :: DESC_WORD4 :: KEY_SELECT [07:00] */
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_MASK                    0x000000ff
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD5 - MEM DMA Descriptor Word 5
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD5 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD6 - MEM DMA Descriptor Word 6
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD6 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD7 - MEM DMA Descriptor Word 7
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD7 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *RAAGA_REGSET_DSP_CFG
+ ***************************************************************************/
+/***************************************************************************
+ *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK     0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT    0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo   2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono     1
+
+/***************************************************************************
+ *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right -2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right -2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right -2147483648
+
+/***************************************************************************
+ *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
+
+/***************************************************************************
+ *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off     0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On      1
+
+/***************************************************************************
+ *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt  1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo  2
+
+/***************************************************************************
+ *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK       0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT      0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono    1
+
+/***************************************************************************
+ *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK   0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *RDC
+ ***************************************************************************/
+/***************************************************************************
+ *EOP_ID_256 - EOP_ID
+ ***************************************************************************/
+/* RDC :: EOP_ID_256 :: eop_id [255:00] */
+#define BCHP_RDC_EOP_ID_256_eop_id_MASK                            0x00000000000000000000000000000000000000000000000000000000ffffffff
+#define BCHP_RDC_EOP_ID_256_eop_id_SHIFT                           0
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_0                    0
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_1                    1
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_2                    2
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_3                    3
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_4                    4
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_5                    5
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_6                    6
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_7                    7
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_0                    8
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_1                    9
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_2                    10
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_3                    11
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_4                    12
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_5                    13
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_6                    14
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_7                    15
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_0                    16
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_1                    17
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_2                    18
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_3                    19
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_4                    20
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_5                    21
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_6                    22
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_7                    23
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_0                   24
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_1                   25
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_2                   26
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_3                   27
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_4                   28
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_5                   29
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_6                   30
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_pfa_0                    31
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_0                   32
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_1                   33
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_2                   34
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_3                   35
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_4                   36
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_5                   37
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_6                   38
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_7                   39
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_nvp_0                    40
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_s3dh_0                   41
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_v0_be                    42
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_0               43
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_1               44
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_2               45
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_3               46
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_4               47
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_0                    48
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_1                    49
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_2                    50
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_3                    51
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_4                    52
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_5                    53
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_6                    54
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_7                    55
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_8                    56
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_9                    57
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_10                   58
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_11                   59
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_5               60
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_6               61
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_7               62
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_8               63
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_0                           64
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_1                           65
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_2                           66
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_3                           67
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_4                           68
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_5                           69
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_6                           70
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_7                           71
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_0                           72
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_1                           73
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_2                           74
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_3                           75
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_4                           76
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_5                           77
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_6                           78
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_7                           79
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_0                           80
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_1                           81
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_2                           82
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_3                           83
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_4                           84
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_5                           85
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_6                           86
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_7                           87
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_0                           88
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_1                           89
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_2                           90
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_3                           91
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_4                           92
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_5                           93
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_6                           94
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_7                           95
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_0                           96
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_1                           97
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_2                           98
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_3                           99
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_4                           100
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_5                           101
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_6                           102
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_7                           103
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_0                          104
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_1                          105
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_2                          106
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_3                          107
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_4                          108
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_5                          109
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_6                          110
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_7                          111
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_0                           112
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_1                           113
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_2                           114
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_3                           115
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_4                           116
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_5                           117
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_6                           118
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_7                           119
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_0                           120
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_1                           121
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_2                           122
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_3                           123
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_4                           124
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_5                           125
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_6                           126
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_7                           127
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_0                           128
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_1                           129
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_2                           130
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_3                           131
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_4                           132
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_5                           133
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_6                           134
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_7                           135
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_0                        136
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_1                        137
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_2                        138
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_3                        139
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_4                        140
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_5                        141
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_6                        142
+#define BCHP_RDC_EOP_ID_256_eop_id_tpg_0                           143
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_0                           144
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_1                           145
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_2                           146
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_3                           147
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_4                           148
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_5                           149
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_6                           150
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_7                           151
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_0                          152
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_1                          153
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_2                          154
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_3                          155
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_4                          156
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_5                          157
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_6                          158
+#define BCHP_RDC_EOP_ID_256_eop_id_pfa_0                           159
+#define BCHP_RDC_EOP_ID_256_eop_id_crc_0                           160
+#define BCHP_RDC_EOP_ID_256_eop_id_crc_1                           161
+#define BCHP_RDC_EOP_ID_256_eop_id_crc_2                           162
+#define BCHP_RDC_EOP_ID_256_eop_id_crc_3                           163
+#define BCHP_RDC_EOP_ID_256_eop_id_hist_0                          164
+#define BCHP_RDC_EOP_ID_256_eop_id_hist_1                          165
+#define BCHP_RDC_EOP_ID_256_eop_id_psm_0                           166
+#define BCHP_RDC_EOP_ID_256_eop_id_plm_0                           167
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_0                    168
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_1                    169
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_2                    170
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_3                    171
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_4                    172
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_5                    173
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_6                    174
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_7                    175
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_0                    176
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_1                    177
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_2                    178
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_3                    179
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_hist_0                   180
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_hist_1                   181
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_psm_0                    182
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_plm_0                    183
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_0_v0                 184
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_1_v0                 185
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_2_v0                 186
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_3_v0                 187
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_4_v0                 188
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_5_v0                 189
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_6_v0                 190
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_7_v0                 191
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_0_v1                 192
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_1_v1                 193
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_2_v1                 194
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_3_v1                 195
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_4_v1                 196
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_5_v1                 197
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_6_v1                 198
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_7_v1                 199
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_0                   200
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_1                   201
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_2                   202
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_3                   203
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_4                   204
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_5                   205
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_6                   206
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_7                   207
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_b3dc_0                   208
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_frc_0                    209
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_0               210
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_1               211
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_2               212
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_3               213
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_4               214
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_5               215
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_0               216
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_1               217
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_2               218
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_3               219
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_4               220
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_5               221
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_6               222
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_7               223
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_8               224
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_9               225
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_10              226
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_11              227
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_6               228
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_7               229
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_8               230
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_9               231
+#define BCHP_RDC_EOP_ID_256_eop_id_nvp_0                           232
+#define BCHP_RDC_EOP_ID_256_eop_id_s3dh_0                          233
+#define BCHP_RDC_EOP_ID_256_eop_id_v0_be                           234
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_0                      235
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_1                      236
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_2                      237
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_3                      238
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_4                      239
+#define BCHP_RDC_EOP_ID_256_eop_id_b3dc_0                          240
+#define BCHP_RDC_EOP_ID_256_eop_id_frc_0                           241
+#define BCHP_RDC_EOP_ID_256_eop_id_pdpf_0                          242
+#define BCHP_RDC_EOP_ID_256_eop_id_pdpb_0                          243
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_5                      244
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_6                      245
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_7                      246
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_8                      247
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_9                      248
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_10                     249
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_11                     250
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_12                     251
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_13                     252
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_14                     253
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_15                     254
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_16                     255
+
+/***************************************************************************
+ *RUL - RUL Command.
+ ***************************************************************************/
+/* RDC :: RUL :: opcode [31:24] */
+#define BCHP_RDC_RUL_opcode_MASK                                   0xff000000
+#define BCHP_RDC_RUL_opcode_SHIFT                                  24
+#define BCHP_RDC_RUL_opcode_NOP                                    0
+#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM                          1
+#define BCHP_RDC_RUL_opcode_REG_WRITE                              2
+#define BCHP_RDC_RUL_opcode_REG_READ                               3
+#define BCHP_RDC_RUL_opcode_LOAD_IMM                               4
+#define BCHP_RDC_RUL_opcode_WINDOW_WRITE                           5
+#define BCHP_RDC_RUL_opcode_BLOCK_WRITE                            6
+#define BCHP_RDC_RUL_opcode_WINDOW_COPY                            7
+#define BCHP_RDC_RUL_opcode_BLOCK_COPY                             8
+#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK                        9
+#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW                        10
+#define BCHP_RDC_RUL_opcode_AND                                    11
+#define BCHP_RDC_RUL_opcode_AND_IMM                                12
+#define BCHP_RDC_RUL_opcode_OR                                     13
+#define BCHP_RDC_RUL_opcode_OR_IMM                                 14
+#define BCHP_RDC_RUL_opcode_XOR                                    15
+#define BCHP_RDC_RUL_opcode_XOR_IMM                                16
+#define BCHP_RDC_RUL_opcode_NOT                                    17
+#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT                           18
+#define BCHP_RDC_RUL_opcode_SUM                                    19
+#define BCHP_RDC_RUL_opcode_SUM_IMM                                20
+#define BCHP_RDC_RUL_opcode_COND_SKIP                              21
+#define BCHP_RDC_RUL_opcode_SKIP                                   22
+#define BCHP_RDC_RUL_opcode_EXIT                                   23
+#define BCHP_RDC_RUL_opcode_WAIT_EOP                               24
+#define BCHP_RDC_RUL_opcode_PLACEHOLDER                            255
+
+/* RDC :: RUL :: reserved0 [23:23] */
+#define BCHP_RDC_RUL_reserved0_MASK                                0x00800000
+#define BCHP_RDC_RUL_reserved0_SHIFT                               23
+
+/* union - case rdc_args [22:00] */
+/* RDC :: RUL :: rdc_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_rdc_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: rdc_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_rdc_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_rdc_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: rdc_args :: src2 [11:06] */
+#define BCHP_RDC_RUL_rdc_args_src2_MASK                            0x00000fc0
+#define BCHP_RDC_RUL_rdc_args_src2_SHIFT                           6
+
+/* RDC :: RUL :: rdc_args :: dest [05:00] */
+#define BCHP_RDC_RUL_rdc_args_dest_MASK                            0x0000003f
+#define BCHP_RDC_RUL_rdc_args_dest_SHIFT                           0
+
+/* union - case reg_args [22:00] */
+/* RDC :: RUL :: reg_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_reg_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_reg_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: reg_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_reg_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_reg_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: reg_args :: count [11:00] */
+#define BCHP_RDC_RUL_reg_args_count_MASK                           0x00000fff
+#define BCHP_RDC_RUL_reg_args_count_SHIFT                          0
+
+/* union - case eop_args [22:00] */
+/* RDC :: RUL :: eop_args :: reserved0 [22:08] */
+#define BCHP_RDC_RUL_eop_args_reserved0_MASK                       0x007fff00
+#define BCHP_RDC_RUL_eop_args_reserved0_SHIFT                      8
+
+/* RDC :: RUL :: eop_args :: eop [07:00] */
+#define BCHP_RDC_RUL_eop_args_eop_MASK                             0x000000ff
+#define BCHP_RDC_RUL_eop_args_eop_SHIFT                            0
+
+/***************************************************************************
+ *SPDIF_RCVR_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_INTERRUPT_HANDLING - Interrupt Handling
+ ***************************************************************************/
+/* SPDIF_RCVR_CTRL :: ABSTRACT_INTERRUPT_HANDLING :: MORE_INFORMATION [31:00] */
+#define BCHP_SPDIF_RCVR_CTRL_ABSTRACT_INTERRUPT_HANDLING_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_SPDIF_RCVR_CTRL_ABSTRACT_INTERRUPT_HANDLING_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *XPT_PB
+ ***************************************************************************/
+/***************************************************************************
+ *DESCRIPTOR_ABSTRACT - Playback Linked-List Descriptor Abstract
+ ***************************************************************************/
+/* XPT_PB :: DESCRIPTOR_ABSTRACT :: DESCRIPTOR_FORMAT [31:00] */
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_MASK     0xffffffff
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_SHIFT    0
+
+/***************************************************************************
+ *DESC_0 - Playback Linked-List Descriptor Word 0
+ ***************************************************************************/
+/* XPT_PB :: DESC_0 :: PB_BUFFER_START_ADDR [31:00] */
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_MASK               0xffffffff
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_SHIFT              0
+
+/***************************************************************************
+ *DESC_1 - Playback Linked-List Descriptor Word 1
+ ***************************************************************************/
+/* XPT_PB :: DESC_1 :: PB_BUFFER_LENGTH [31:00] */
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_MASK                   0xffffffff
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_SHIFT                  0
+
+/***************************************************************************
+ *DESC_2 - Playback Linked-List Descriptor Word 2
+ ***************************************************************************/
+/* XPT_PB :: DESC_2 :: PB_INTERRUPT_ENABLE [31:31] */
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_MASK                0x80000000
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_SHIFT               31
+
+/* XPT_PB :: DESC_2 :: PB_FORCE_RESYNC [30:30] */
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_MASK                    0x40000000
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_SHIFT                   30
+
+/* XPT_PB :: DESC_2 :: PB_HOST_DATA_INS_EN [29:29] */
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_MASK                0x20000000
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_SHIFT               29
+
+/* XPT_PB :: DESC_2 :: PUSH_PARTIAL_PACKET [28:28] */
+#define BCHP_XPT_PB_DESC_2_PUSH_PARTIAL_PACKET_MASK                0x10000000
+#define BCHP_XPT_PB_DESC_2_PUSH_PARTIAL_PACKET_SHIFT               28
+
+/* XPT_PB :: DESC_2 :: PB_DESC_TAG_ID [27:24] */
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_MASK                     0x0f000000
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_SHIFT                    24
+
+/* XPT_PB :: DESC_2 :: PB_DESC_BAND_ID_EN [23:23] */
+#define BCHP_XPT_PB_DESC_2_PB_DESC_BAND_ID_EN_MASK                 0x00800000
+#define BCHP_XPT_PB_DESC_2_PB_DESC_BAND_ID_EN_SHIFT                23
+
+/* XPT_PB :: DESC_2 :: PB_DESC_PARSER_SEL [22:22] */
+#define BCHP_XPT_PB_DESC_2_PB_DESC_PARSER_SEL_MASK                 0x00400000
+#define BCHP_XPT_PB_DESC_2_PB_DESC_PARSER_SEL_SHIFT                22
+
+/* XPT_PB :: DESC_2 :: PB_DESC_BAND_ID [21:16] */
+#define BCHP_XPT_PB_DESC_2_PB_DESC_BAND_ID_MASK                    0x003f0000
+#define BCHP_XPT_PB_DESC_2_PB_DESC_BAND_ID_SHIFT                   16
+
+/* XPT_PB :: DESC_2 :: reserved0 [15:00] */
+#define BCHP_XPT_PB_DESC_2_reserved0_MASK                          0x0000ffff
+#define BCHP_XPT_PB_DESC_2_reserved0_SHIFT                         0
+
+/***************************************************************************
+ *DESC_3 - Playback Linked-List Descriptor Word 3
+ ***************************************************************************/
+/* XPT_PB :: DESC_3 :: PB_NEXT_DESC_ADDR [31:04] */
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_MASK                  0xfffffff0
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_SHIFT                 4
+
+/* XPT_PB :: DESC_3 :: reserved0 [03:01] */
+#define BCHP_XPT_PB_DESC_3_reserved0_MASK                          0x0000000e
+#define BCHP_XPT_PB_DESC_3_reserved0_SHIFT                         1
+
+/* XPT_PB :: DESC_3 :: PB_LAST_DESC_IND [00:00] */
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_MASK                   0x00000001
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_SHIFT                  0
+
+/***************************************************************************
+ *DESC_4 - Playback Linked-List Descriptor Word 4
+ ***************************************************************************/
+/* XPT_PB :: DESC_4 :: reserved0 [31:00] */
+#define BCHP_XPT_PB_DESC_4_reserved0_MASK                          0xffffffff
+#define BCHP_XPT_PB_DESC_4_reserved0_SHIFT                         0
+
+/***************************************************************************
+ *DESC_5 - Playback Linked-List Descriptor Word 5
+ ***************************************************************************/
+/* XPT_PB :: DESC_5 :: reserved0 [31:03] */
+#define BCHP_XPT_PB_DESC_5_reserved0_MASK                          0xfffffff8
+#define BCHP_XPT_PB_DESC_5_reserved0_SHIFT                         3
+
+/* XPT_PB :: DESC_5 :: RANDOM_ACCESS_INDICATION [02:02] */
+#define BCHP_XPT_PB_DESC_5_RANDOM_ACCESS_INDICATION_MASK           0x00000004
+#define BCHP_XPT_PB_DESC_5_RANDOM_ACCESS_INDICATION_SHIFT          2
+
+/* XPT_PB :: DESC_5 :: NEXT_PACKET_PACING_TIMESTAMP_VALID [01:01] */
+#define BCHP_XPT_PB_DESC_5_NEXT_PACKET_PACING_TIMESTAMP_VALID_MASK 0x00000002
+#define BCHP_XPT_PB_DESC_5_NEXT_PACKET_PACING_TIMESTAMP_VALID_SHIFT 1
+
+/* XPT_PB :: DESC_5 :: PKT2PKT_PACING_TIMESTAMP_DELTA_VALID [00:00] */
+#define BCHP_XPT_PB_DESC_5_PKT2PKT_PACING_TIMESTAMP_DELTA_VALID_MASK 0x00000001
+#define BCHP_XPT_PB_DESC_5_PKT2PKT_PACING_TIMESTAMP_DELTA_VALID_SHIFT 0
+
+/***************************************************************************
+ *DESC_6 - Playback Linked-List Descriptor Word 6
+ ***************************************************************************/
+/* XPT_PB :: DESC_6 :: NEXT_PACKET_PACING_TIMESTAMP [31:00] */
+#define BCHP_XPT_PB_DESC_6_NEXT_PACKET_PACING_TIMESTAMP_MASK       0xffffffff
+#define BCHP_XPT_PB_DESC_6_NEXT_PACKET_PACING_TIMESTAMP_SHIFT      0
+
+/***************************************************************************
+ *DESC_7 - Playback Linked-List Descriptor Word 7
+ ***************************************************************************/
+/* XPT_PB :: DESC_7 :: PKT2PKT_PACING_TIMESTAMP_DELTA [31:00] */
+#define BCHP_XPT_PB_DESC_7_PKT2PKT_PACING_TIMESTAMP_DELTA_MASK     0xffffffff
+#define BCHP_XPT_PB_DESC_7_PKT2PKT_PACING_TIMESTAMP_DELTA_SHIFT    0
+
+/***************************************************************************
+ *XPT_RAVE
+ ***************************************************************************/
+/***************************************************************************
+ *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
+
+/***************************************************************************
+ *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
+
+/***************************************************************************
+ *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
+ ***************************************************************************/
+/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
+
+#endif /* #ifndef BCHP_COMMON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_ddr40_phy_control_regs_0.h b/include/linux/brcmstb/7429b0/bchp_ddr40_phy_control_regs_0.h
new file mode 100644
index 0000000..29d946b
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_ddr40_phy_control_regs_0.h
@@ -0,0 +1,1510 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:14 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_CONTROL_REGS_0 - DDR40 DDR40 physical interface control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION   0x003b6000 /* Address & Control revision register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL 0x003b6004 /* PHY clock power management control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS 0x003b6010 /* PHY PLL status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG 0x003b6014 /* PHY PLL configuration register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL 0x003b6018 /* PHY PLL control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS 0x003b601c /* PHY PLL dividers control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL 0x003b6020 /* Aux Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL 0x003b6030 /* Address & Control coarse VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL 0x003b6034 /* Address & Control fine VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL 0x003b6038 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL 0x003b603c /* PVT Compensation control and status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL 0x003b6040 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS 0x003b6044 /* PHY Auto Init rd_data_dly result register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE 0x003b6048 /* PHY VDL calibration control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS 0x003b604c /* PHY VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS 0x003b6050 /* PHY DQ VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS 0x003b6054 /* PHY Write Channel VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS 0x003b6058 /* PHY Read Enable VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL 0x003b605c /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS 0x003b6060 /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS 0x003b6064 /* Virtual VTT Connections register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE 0x003b6068 /* Virtual VTT Override register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL 0x003b606c /* VREF DAC Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL 0x003b6070 /* PhyBist Control Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED 0x003b6074 /* PhyBist Seed Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS 0x003b6078 /* PhyBist General Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS 0x003b607c /* PhyBist Per-Bit Control Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS 0x003b6080 /* PhyBist Per-Bit DQ Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS 0x003b6084 /* PhyBist Per-Bit DM and CK Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG 0x003b6090 /* DRAM Command Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0  0x003b6094 /* Mode Register 0 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1  0x003b6098 /* Mode Register 1 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2  0x003b609c /* Mode Register 2 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3  0x003b60a0 /* Mode Register 3 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL 0x003b60a4 /* Standby Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL 0x003b60b0 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2 0x003b60b4 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS 0x003b60b8 /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2 0x003b60bc /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE 0x003b60c0 /* Freeze-on-error enable register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK 0x003b60c4 /* Datapth Loopback control register */
+
+/***************************************************************************
+ *REVISION - Address & Control revision register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_MASK      0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_SHIFT     16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_MASK          0x0000ff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_SHIFT         8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_DEFAULT       0x00000040
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_MASK          0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_DEFAULT       0x00000005
+
+/***************************************************************************
+ *CLK_PM_CTRL - PHY clock power management control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_MASK   0xfffffffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_SHIFT  1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_STATUS - PHY PLL status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_MASK    0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_SHIFT   27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK_LOST [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_MASK    0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_SHIFT   26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: DDR_MHZ [25:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_MASK      0x03ffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_SHIFT     14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_4X [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: STATUS [12:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_MASK       0x00001ffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_SHIFT      1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_MASK         0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_CONFIG - PHY PLL configuration register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved0 [31:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_MASK    0xffffff80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_SHIFT   7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LP40_PLL_POST_RESET [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET_POST_DIV [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LDO_CTRL [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_MASK     0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_SHIFT    3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_DEFAULT  0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved1 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_MASK    0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_SHIFT   2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_MASK        0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_SHIFT       1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_DEFAULT     0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PWRDN [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_MASK        0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_SHIFT       0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PLL_CONTROL - PHY PLL control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: reserved0 [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_SHIFT  31
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_kp [30:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_MASK        0x78000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_SHIFT       27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_DEFAULT     0x0000000a
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ki [26:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_MASK        0x07000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_SHIFT       24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_DEFAULT     0x00000003
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ka [23:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_MASK        0x00e00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_SHIFT       21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_DEFAULT     0x00000003
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: PLL_CONTROL [20:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_MASK 0x001fffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_DIVIDERS - PHY PLL dividers control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_MASK  0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_SHIFT 16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_HI [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_MASK 0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_LO [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: POST_DIV [13:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_MASK   0x00003800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_SHIFT  11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_DEFAULT 0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: PDIV [10:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_MASK       0x00000700
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_SHIFT      8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_DEFAULT    0x00000004
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_MASK       0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_DEFAULT    0x00000020
+
+/***************************************************************************
+ *AUX_CONTROL - Aux Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved0 [31:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_MASK   0xfffffc00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_SHIFT  10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_cs [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_MASK       0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_SHIFT      7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_ad [06:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_MASK       0x00000070
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_SHIFT      4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_odt [03:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_MASK      0x0000000e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_SHIFT     1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: override [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_CTL - Address & Control coarse VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BIT_CTL - Address & Control fine VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_SHIFT  31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved0 [30:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ffffe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: rxenb [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_MASK  0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved1 [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_SHIFT 7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_reb [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ZQ_PVT_COMP_CTL - PVT Compensation control and status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: update_mode [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_done [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_done [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_done [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: auto_sample_en [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_MASK 0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_en [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_ovr_en [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_ovr_en [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_comp [17:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_MASK 0x00038000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_comp [14:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_MASK 0x00007000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [11:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_MASK 0x00000e00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [08:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_MASK 0x000001c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: auto_oeb [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a15 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_MASK  0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a14 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_MASK  0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a13 [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_MASK  0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_aux [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_MASK  0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: half_strength [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_MASK     0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_SHIFT    2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_MASK  0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_MASK     0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_SHIFT    0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_DEFAULT  0x00000000
+
+/***************************************************************************
+ *VDL_RD_DATA_DLY_STATUS - PHY Auto Init rd_data_dly result register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_SHIFT 12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: auto_init_state [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_MASK 0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_max [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_min [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_DEFAULT 0x00000007
+
+/***************************************************************************
+ *VDL_CALIBRATE - PHY VDL calibration control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_SHIFT 29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: use_straps [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: auto_init [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: skip_rst [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_MASK  0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_SHIFT 26
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: exit_in_sr [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_dly_cal [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_refresh [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_wr_dq [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: dq0_only [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_MASK  0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_mr_mpr [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_cal [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_MASK   0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_SHIFT  19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_en_cal [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_clocks [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_pair [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_steps [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_auto [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_ftm [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_phybist [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_byte [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_clocks [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_test [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_always [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_once [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_fast [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CALIB_STATUS - PHY VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_MASK 0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_fail [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_MASK 0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_SHIFT 29
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_done [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_rd_data_dly_error [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_read_en_error [26:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_MASK 0x07800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_error [22:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_MASK 0x00780000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_sel [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_total [11:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_MASK 0x00000ffc
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VDL_DQ_CALIB_STATUS - PHY DQ VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_total [25:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_MASK 0x03ff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_clocks [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_mode [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_WR_CHAN_CALIB_STATUS - PHY Write Channel VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_RD_EN_CALIB_STATUS - PHY Read Enable VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: low_vtt [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: high_vtt [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: error_reset [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_ctl_idle [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cs_idle [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cke_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error [18:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_MASK 0x0007fff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_low [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_high [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ready [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_DEFAULT 0x00ffffff
+
+/***************************************************************************
+ *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_DEFAULT 0x0003ffff
+
+/***************************************************************************
+ *VREF_DAC_CONTROL - VREF DAC Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK1_GT_INT [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK0_GT_INT [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_GT_INT [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: EXT_GT_INT [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_TESTOUT_MUX_CTL [16:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_MASK 0x00018000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TEST [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_MASK   0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_SHIFT  14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_MASK   0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_SHIFT  13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_MASK   0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_SHIFT  12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_MASK   0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_SHIFT  6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_DEFAULT 0x00000020
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_MASK   0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_SHIFT  0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_DEFAULT 0x00000020
+
+/***************************************************************************
+ *PHYBIST_CNTRL - PhyBist Control Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_error_sel [13:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_MASK 0x00003f00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved1 [07:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_MASK 0x000000e0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_SHIFT 5
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: bench_mode [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_dat_error [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_ctl_error [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: int_loopback [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHYBIST_SEED - PhyBist Seed Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_SEED :: seed [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_MASK       0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_DEFAULT    0x250e4af6
+
+/***************************************************************************
+ *PHYBIST_STATUS - PhyBist General Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_pass [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_pass [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_SHIFT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_done [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_done [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: ctl_errors [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_DQ_STATUS - PhyBist Per-Bit DQ Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_STATUS :: dat_errors [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_MASK 0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_MISC_STATUS - PhyBist Per-Bit DM and CK Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: ck_errors [07:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_MASK 0x000000f0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: dm_errors [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_SHIFT 0
+
+/***************************************************************************
+ *COMMAND_REG - DRAM Command Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_MASK   0xfe000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_SHIFT  25
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: aux [24:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_MASK         0x01c00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_SHIFT        22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: we [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_MASK          0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_SHIFT         21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_DEFAULT       0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: cas [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_MASK         0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_SHIFT        20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ras [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_MASK         0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_SHIFT        19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ba [18:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_MASK          0x00070000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_SHIFT         16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_DEFAULT       0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_MASK          0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_DEFAULT       0x00000000
+
+/***************************************************************************
+ *MODE_REG0 - Mode Register 0
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG1 - Mode Register 1
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG2 - Mode Register 2
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG3 - Mode Register 3
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STANDBY_CONTROL - Standby Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_ready [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_exit_pin_en [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_active [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: armed [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_MASK   0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_SHIFT  15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: warmstart [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_ldo_volts [13:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_MASK 0x00003000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_skip_mrs [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_rst_n [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_cke [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: ldo_volts [08:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_MASK 0x00000180
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_DEFAULT 0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: skip_mrs [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: rst_n [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_MASK   0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_SHIFT  5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: cke [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_MASK     0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_SHIFT    4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_CONTROL - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: reserved0 [31:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_MASK 0xf0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_MASK       0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_SHIFT      16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_MASK  0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_MASK 0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_MASK     0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_SHIFT    12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_MASK      0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_SHIFT     11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_MASK      0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_SHIFT     8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_CONTROL2 - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_MASK     0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_SHIFT    20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_MASK       0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_SHIFT      17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_MASK       0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_SHIFT      12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_MASK      0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_SHIFT     7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_MASK       0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_DEFAULT    0x00000000
+
+/***************************************************************************
+ *STRAP_STATUS - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_MASK  0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_reg [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_MASK   0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_SHIFT  29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_memc [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_MASK  0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_MASK        0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_SHIFT       16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_MASK   0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_SHIFT  14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_MASK      0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_SHIFT     12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_MASK       0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_SHIFT      11
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_SHIFT 10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_MASK       0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_SHIFT      8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_MASK  0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_SHIFT 0
+
+/***************************************************************************
+ *STRAP_STATUS2 - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_MASK      0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_SHIFT     20
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_MASK        0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_SHIFT       17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_MASK        0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_SHIFT       12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_MASK       0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_SHIFT      7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_MASK        0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_SHIFT       0
+
+/***************************************************************************
+ *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl1 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl0 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl1 [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl0 [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DATAPATH_LOOPBACK - Datapth Loopback control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: xor_dm_rd_en [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: use_addr_ctl [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_ddr40_phy_word_lane_0_0.h b/include/linux/brcmstb/7429b0/bchp_ddr40_phy_word_lane_0_0.h
new file mode 100644
index 0000000..eb96820
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_ddr40_phy_word_lane_0_0.h
@@ -0,0 +1,3331 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:16 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_0_0 - DDR40 DDR40 word lane #0 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN 0x003b6200 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W 0x003b6204 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P 0x003b6208 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N 0x003b620c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W 0x003b6210 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W 0x003b6214 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W 0x003b6218 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W 0x003b621c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W 0x003b6220 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W 0x003b6224 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W 0x003b6228 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W 0x003b622c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W 0x003b6230 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003b6234 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003b6238 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003b623c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003b6240 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003b6244 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003b6248 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003b624c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003b6250 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003b6254 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003b6258 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003b625c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003b6260 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003b6264 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003b6268 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003b626c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003b6270 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003b6274 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W 0x003b62a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P 0x003b62a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N 0x003b62ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W 0x003b62b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W 0x003b62b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W 0x003b62b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W 0x003b62bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W 0x003b62c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W 0x003b62c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W 0x003b62c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W 0x003b62cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W 0x003b62d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003b62d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003b62d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003b62dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003b62e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003b62e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003b62e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003b62ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003b62f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003b62f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003b62f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003b62fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003b6300 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003b6304 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003b6308 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003b630c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003b6310 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003b6314 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x003b6328 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x003b632c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003b6330 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003b6334 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W 0x003b6338 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003b633c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x003b6348 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x003b634c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003b6350 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003b6354 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W 0x003b6358 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003b635c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY 0x003b6360 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL 0x003b6364 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0 0x003b6370 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1 0x003b6374 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2 0x003b6378 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3 0x003b637c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0 0x003b6380 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1 0x003b6384 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2 0x003b6388 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3 0x003b638c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS 0x003b6390 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR 0x003b6394 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL 0x003b63a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL 0x003b63a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE 0x003b63a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE 0x003b63ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ 0x003b63b0 /* PHYBIST mode VDL step select adjustment register */
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_RD_EN - Read Enable Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_DATA_DLY - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_MASK  0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: rd_data_dly [02:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_MASK 0x00000007
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_DEFAULT 0x00000001
+
+/***************************************************************************
+ *READ_CONTROL - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_MASK   0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_SHIFT  3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_enable [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_te_adj [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_le_adj [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status1 [07:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_MASK 0x000000f0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status0 [03:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_MASK 0x0000000f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: clear [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_MASK    0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_SHIFT   31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_SHIFT 24
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_MASK 0x00c00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_SHIFT 22
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_MASK 0x00300000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_SHIFT 20
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00080000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 19
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00040000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_SHIFT 18
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_MASK  0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_MASK  0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00008000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 15
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00004000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 14
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00002000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 13
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00001000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 12
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_MASK 0x00000008
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_MASK  0xfffff000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_SHIFT 12
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: no_dqs_rd [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_MASK  0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_MASK    0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_SHIFT   6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_MASK      0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_SHIFT     2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_DEFAULT   0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_MASK   0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_SHIFT  1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_MASK      0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_SHIFT     0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_DEFAULT   0x00000000
+
+/***************************************************************************
+ *CLOCK_PAD_DISABLE - Clock pad disable register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffc
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_SHIFT 2
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: long [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_MASK    0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_SHIFT   1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: mode [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHYBIST_VDL_ADJ - PHYBIST mode VDL step select adjustment register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_SHIFT 29
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq1_vdl_adj [28:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_MASK 0x1f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved1 [23:21] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_MASK 0x00e00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_SHIFT 21
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq0_vdl_adj [20:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_MASK 0x001f0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved2 [15:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_MASK 0x0000e000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_SHIFT 13
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs1_vdl_adj [12:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_MASK 0x00001f00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved3 [07:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_MASK 0x000000e0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_SHIFT 5
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs0_vdl_adj [04:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_MASK 0x0000001f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_ddr40_phy_word_lane_1_0.h b/include/linux/brcmstb/7429b0/bchp_ddr40_phy_word_lane_1_0.h
new file mode 100644
index 0000000..575c82e
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_ddr40_phy_word_lane_1_0.h
@@ -0,0 +1,139 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Apr 11 12:01:44 2011
+ *                 MD5 Checksum         8cf142ad25caa9f873c54e8bb2bb1755
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7425/rdb/b0/bchp_ddr40_phy_word_lane_1_0.h $
+ * 
+ * Hydra_Software_Devel/2   4/11/11 11:57p vanessah
+ * SW7425-112: Update rdb files for 7425 B0.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_1_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_1_0 - DDR40 DDR40 word lane #1 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN 0x003b6400 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W 0x003b6404 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P 0x003b6408 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N 0x003b640c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W 0x003b6410 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W 0x003b6414 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W 0x003b6418 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W 0x003b641c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W 0x003b6420 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W 0x003b6424 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W 0x003b6428 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W 0x003b642c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W 0x003b6430 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003b6434 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003b6438 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003b643c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003b6440 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003b6444 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003b6448 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003b644c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003b6450 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003b6454 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003b6458 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003b645c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003b6460 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003b6464 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003b6468 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003b646c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003b6470 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003b6474 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W 0x003b64a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P 0x003b64a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N 0x003b64ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W 0x003b64b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W 0x003b64b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W 0x003b64b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W 0x003b64bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W 0x003b64c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W 0x003b64c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W 0x003b64c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W 0x003b64cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W 0x003b64d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003b64d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003b64d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003b64dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003b64e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003b64e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003b64e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003b64ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003b64f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003b64f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003b64f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003b64fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003b6500 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003b6504 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003b6508 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003b650c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003b6510 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003b6514 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x003b6528 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x003b652c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003b6530 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003b6534 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W 0x003b6538 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003b653c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x003b6548 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x003b654c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003b6550 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003b6554 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W 0x003b6558 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003b655c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_DATA_DLY 0x003b6560 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_CONTROL 0x003b6564 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_0 0x003b6570 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_1 0x003b6574 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_2 0x003b6578 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_3 0x003b657c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_0 0x003b6580 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_1 0x003b6584 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_2 0x003b6588 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_3 0x003b658c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_STATUS 0x003b6590 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_CLEAR 0x003b6594 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL 0x003b65a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL 0x003b65a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_CLOCK_PAD_DISABLE 0x003b65a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_WR_PREAMBLE_MODE 0x003b65ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ 0x003b65b0 /* PHYBIST mode VDL step select adjustment register */
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_1_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_ebi.h b/include/linux/brcmstb/7429b0/bchp_ebi.h
new file mode 100644
index 0000000..1e1f780
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_ebi.h
@@ -0,0 +1,1469 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:14 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EBI_H__
+#define BCHP_EBI_H__
+
+/***************************************************************************
+ *EBI - EBI Registers
+ ***************************************************************************/
+#define BCHP_EBI_CS_BASE_0                       0x00410800 /* EBI CS Base 0 Register */
+#define BCHP_EBI_CS_CONFIG_0                     0x00410804 /* EBI CS Config 0 Register */
+#define BCHP_EBI_CS_BASE_1                       0x00410808 /* EBI CS Base 1 Register */
+#define BCHP_EBI_CS_CONFIG_1                     0x0041080c /* EBI CS Config 1 Register */
+#define BCHP_EBI_CS_BASE_2                       0x00410810 /* EBI CS Base 2 Register */
+#define BCHP_EBI_CS_CONFIG_2                     0x00410814 /* EBI CS Config 2 Register */
+#define BCHP_EBI_CS_BASE_3                       0x00410818 /* EBI CS Base 3 Register */
+#define BCHP_EBI_CS_CONFIG_3                     0x0041081c /* EBI CS Config 3 Register */
+#define BCHP_EBI_CS_BASE_4                       0x00410820 /* EBI CS Base 4 Register */
+#define BCHP_EBI_CS_CONFIG_4                     0x00410824 /* EBI CS Config 4 Register */
+#define BCHP_EBI_BURST_CFG_0                     0x00410840 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_1                     0x00410844 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_2                     0x00410848 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_3                     0x0041084c /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_4                     0x00410850 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_ECR                             0x00410900 /* EBI Configuration Register */
+#define BCHP_EBI_CS_TRISTATE_CFG                 0x00410918 /* EBI CS Tristate Configuration Register */
+#define BCHP_EBI_TA_CFG                          0x0041091c /* EBI TA Configuration Register */
+#define BCHP_EBI_CS_SPI_SELECT                   0x00410920 /* SPI CS Select */
+#define BCHP_EBI_ARRAY_ADDRESS                   0x004109f0 /* EBI Data Array Address */
+
+/***************************************************************************
+ *CS_BASE_0 - EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_0 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_0_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT                         13
+
+/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_0_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_0 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_0_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_0_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_0 - EBI CS Config 0 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_0_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT                       0x00000001
+
+/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_0_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_0_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_0_le_SHIFT                              10
+
+/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_0_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_0_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT                       4
+
+/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_0_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT                        0x00000001
+
+/***************************************************************************
+ *CS_BASE_1 - EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_1 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_1_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_1_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_1 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_1_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_1_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_1_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_1 - EBI CS Config 1 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_1_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_1_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_1_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_1_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_1_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_1_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_1_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_2 - EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_2 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_2_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_2_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_2 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_2_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_2_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_2_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_2 - EBI CS Config 2 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_2_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_2_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_2_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_2_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_2_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_2_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_2_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_3 - EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_3 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_3_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_3_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_3 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_3_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_3_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_3_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_3 - EBI CS Config 3 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_3_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_3_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_3_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_3_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_3_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_3_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_3_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_4 - EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_4 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_4_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_4_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_4 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_4_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_4_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_4_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_4 - EBI CS Config 4 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_4_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_4_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_4_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_4_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_4_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_4_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_4_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_0_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_0_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_0 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_0_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_0_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_0_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_0_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_0_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_1_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_1_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_1 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_1_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_1_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_1_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_1_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_1_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_2_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_2_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_2 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_2_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_2_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_2_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_2_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_2_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_3_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_3_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_3 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_3_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_3_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_3_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_3_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_3_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_4_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_4_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_4 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_4_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_4_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_4_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_4_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_4_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *ECR - EBI Configuration Register
+ ***************************************************************************/
+/* EBI :: ECR :: reserved0 [31:28] */
+#define BCHP_EBI_ECR_reserved0_MASK                                0xf0000000
+#define BCHP_EBI_ECR_reserved0_SHIFT                               28
+
+/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK                            0x08000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT                           27
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT                         0x00000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only  1
+
+/* EBI :: ECR :: reserved1 [26:26] */
+#define BCHP_EBI_ECR_reserved1_MASK                                0x04000000
+#define BCHP_EBI_ECR_reserved1_SHIFT                               26
+
+/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK                          0x02000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT                         25
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT                       0x00000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10         0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00         1
+
+/* EBI :: ECR :: reserved2 [24:11] */
+#define BCHP_EBI_ECR_reserved2_MASK                                0x01fff800
+#define BCHP_EBI_ECR_reserved2_SHIFT                               11
+
+/* EBI :: ECR :: timeout_count [10:00] */
+#define BCHP_EBI_ECR_timeout_count_MASK                            0x000007ff
+#define BCHP_EBI_ECR_timeout_count_SHIFT                           0
+#define BCHP_EBI_ECR_timeout_count_DEFAULT                         0x00000400
+
+/***************************************************************************
+ *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
+ ***************************************************************************/
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK             0x80000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT            31
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK             0x40000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT            30
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK             0x20000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT            29
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK             0x10000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT            28
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK            0x08000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT           27
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK            0x04000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT           26
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK         0x02000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT        25
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK         0x01000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT        24
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:05] */
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK                    0x00ffffe0
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT                   5
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK             0x00000010
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT            4
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK             0x00000008
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT            3
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK             0x00000004
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT            2
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK             0x00000002
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT            1
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK             0x00000001
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT            0
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TA_CFG - EBI TA Configuration Register
+ ***************************************************************************/
+/* EBI :: TA_CFG :: reserved0 [31:04] */
+#define BCHP_EBI_TA_CFG_reserved0_MASK                             0xfffffff0
+#define BCHP_EBI_TA_CFG_reserved0_SHIFT                            4
+
+/* EBI :: TA_CFG :: use_ta3 [03:03] */
+#define BCHP_EBI_TA_CFG_use_ta3_MASK                               0x00000008
+#define BCHP_EBI_TA_CFG_use_ta3_SHIFT                              3
+#define BCHP_EBI_TA_CFG_use_ta3_DEFAULT                            0x00000001
+
+/* EBI :: TA_CFG :: use_ta2 [02:02] */
+#define BCHP_EBI_TA_CFG_use_ta2_MASK                               0x00000004
+#define BCHP_EBI_TA_CFG_use_ta2_SHIFT                              2
+#define BCHP_EBI_TA_CFG_use_ta2_DEFAULT                            0x00000000
+
+/* EBI :: TA_CFG :: use_ta1 [01:01] */
+#define BCHP_EBI_TA_CFG_use_ta1_MASK                               0x00000002
+#define BCHP_EBI_TA_CFG_use_ta1_SHIFT                              1
+#define BCHP_EBI_TA_CFG_use_ta1_DEFAULT                            0x00000001
+
+/* EBI :: TA_CFG :: reserved1 [00:00] */
+#define BCHP_EBI_TA_CFG_reserved1_MASK                             0x00000001
+#define BCHP_EBI_TA_CFG_reserved1_SHIFT                            0
+
+/***************************************************************************
+ *CS_SPI_SELECT - SPI CS Select
+ ***************************************************************************/
+/* EBI :: CS_SPI_SELECT :: reserved0 [31:16] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK                      0xffff0000
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT                     16
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_7_USES_SPI [15:15] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_MASK              0x00008000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_SHIFT             15
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK              0x00004000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT             14
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK              0x00002000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT             13
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK              0x00001000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT             12
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK              0x00000800
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT             11
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK              0x00000400
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT             10
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK              0x00000200
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT             9
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK              0x00000100
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT             8
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_7_SEL [07:07] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_MASK               0x00000080
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_SHIFT              7
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK               0x00000040
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT              6
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK               0x00000020
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT              5
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK               0x00000010
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT              4
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK               0x00000008
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT              3
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK               0x00000004
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT              2
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK               0x00000002
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT              1
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK               0x00000001
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT              0
+
+/***************************************************************************
+ *ARRAY_ADDRESS - EBI Data Array Address
+ ***************************************************************************/
+/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK                        0xfffffe00
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT                       9
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT                     0x00000000
+
+/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK                      0x000001f8
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT                     3
+
+/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK                         0x00000007
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT                        0
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE                            0x00410a00
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_START                           0
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_END                             127
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE                    32
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+/* EBI :: DATA_ARRAYi :: WORD [31:00] */
+#define BCHP_EBI_DATA_ARRAYi_WORD_MASK                             0xffffffff
+#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT                            0
+
+
+#endif /* #ifndef BCHP_EBI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_edu.h b/include/linux/brcmstb/7429b0/bchp_edu.h
new file mode 100644
index 0000000..9ae8200
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_edu.h
@@ -0,0 +1,190 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:14 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EDU_H__
+#define BCHP_EDU_H__
+
+/***************************************************************************
+ *EDU - EDU Registers
+ ***************************************************************************/
+#define BCHP_EDU_CONFIG                          0x00412e00 /* EDU Config */
+#define BCHP_EDU_DRAM_ADDR                       0x00412e04 /* DRAM Address for transaction */
+#define BCHP_EDU_EXT_ADDR                        0x00412e08 /* External Address for transaction */
+#define BCHP_EDU_LENGTH                          0x00412e0c /* Length of transaction */
+#define BCHP_EDU_CMD                             0x00412e10 /* Command Type and Start */
+#define BCHP_EDU_STOP                            0x00412e14 /* Stop */
+#define BCHP_EDU_STATUS                          0x00412e18 /* EDU Status bits */
+#define BCHP_EDU_DONE                            0x00412e1c /* EDU Done bits */
+#define BCHP_EDU_ERR_STATUS                      0x00412e20 /* EDU Error Status */
+
+/***************************************************************************
+ *CONFIG - EDU Config
+ ***************************************************************************/
+/* EDU :: CONFIG :: reserved0 [31:03] */
+#define BCHP_EDU_CONFIG_reserved0_MASK                             0xfffffff8
+#define BCHP_EDU_CONFIG_reserved0_SHIFT                            3
+
+/* EDU :: CONFIG :: Swap [02:01] */
+#define BCHP_EDU_CONFIG_Swap_MASK                                  0x00000006
+#define BCHP_EDU_CONFIG_Swap_SHIFT                                 1
+#define BCHP_EDU_CONFIG_Swap_DEFAULT                               0x00000000
+
+/* EDU :: CONFIG :: Mode [00:00] */
+#define BCHP_EDU_CONFIG_Mode_MASK                                  0x00000001
+#define BCHP_EDU_CONFIG_Mode_SHIFT                                 0
+#define BCHP_EDU_CONFIG_Mode_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *DRAM_ADDR - DRAM Address for transaction
+ ***************************************************************************/
+/* EDU :: DRAM_ADDR :: Address [31:02] */
+#define BCHP_EDU_DRAM_ADDR_Address_MASK                            0xfffffffc
+#define BCHP_EDU_DRAM_ADDR_Address_SHIFT                           2
+#define BCHP_EDU_DRAM_ADDR_Address_DEFAULT                         0x00000000
+
+/* EDU :: DRAM_ADDR :: reserved0 [01:00] */
+#define BCHP_EDU_DRAM_ADDR_reserved0_MASK                          0x00000003
+#define BCHP_EDU_DRAM_ADDR_reserved0_SHIFT                         0
+
+/***************************************************************************
+ *EXT_ADDR - External Address for transaction
+ ***************************************************************************/
+/* EDU :: EXT_ADDR :: Address [31:02] */
+#define BCHP_EDU_EXT_ADDR_Address_MASK                             0xfffffffc
+#define BCHP_EDU_EXT_ADDR_Address_SHIFT                            2
+#define BCHP_EDU_EXT_ADDR_Address_DEFAULT                          0x00000000
+
+/* EDU :: EXT_ADDR :: reserved0 [01:00] */
+#define BCHP_EDU_EXT_ADDR_reserved0_MASK                           0x00000003
+#define BCHP_EDU_EXT_ADDR_reserved0_SHIFT                          0
+
+/***************************************************************************
+ *LENGTH - Length of transaction
+ ***************************************************************************/
+/* EDU :: LENGTH :: reserved0 [31:10] */
+#define BCHP_EDU_LENGTH_reserved0_MASK                             0xfffffc00
+#define BCHP_EDU_LENGTH_reserved0_SHIFT                            10
+
+/* EDU :: LENGTH :: Length [09:00] */
+#define BCHP_EDU_LENGTH_Length_MASK                                0x000003ff
+#define BCHP_EDU_LENGTH_Length_SHIFT                               0
+#define BCHP_EDU_LENGTH_Length_DEFAULT                             0x00000000
+
+/***************************************************************************
+ *CMD - Command Type and Start
+ ***************************************************************************/
+/* EDU :: CMD :: reserved0 [31:01] */
+#define BCHP_EDU_CMD_reserved0_MASK                                0xfffffffe
+#define BCHP_EDU_CMD_reserved0_SHIFT                               1
+
+/* EDU :: CMD :: Cmd [00:00] */
+#define BCHP_EDU_CMD_Cmd_MASK                                      0x00000001
+#define BCHP_EDU_CMD_Cmd_SHIFT                                     0
+#define BCHP_EDU_CMD_Cmd_DEFAULT                                   0x00000000
+
+/***************************************************************************
+ *STOP - Stop
+ ***************************************************************************/
+/* EDU :: STOP :: reserved0 [31:01] */
+#define BCHP_EDU_STOP_reserved0_MASK                               0xfffffffe
+#define BCHP_EDU_STOP_reserved0_SHIFT                              1
+
+/* EDU :: STOP :: Stop [00:00] */
+#define BCHP_EDU_STOP_Stop_MASK                                    0x00000001
+#define BCHP_EDU_STOP_Stop_SHIFT                                   0
+#define BCHP_EDU_STOP_Stop_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *STATUS - EDU Status bits
+ ***************************************************************************/
+/* EDU :: STATUS :: reserved0 [31:02] */
+#define BCHP_EDU_STATUS_reserved0_MASK                             0xfffffffc
+#define BCHP_EDU_STATUS_reserved0_SHIFT                            2
+
+/* EDU :: STATUS :: Pending [01:01] */
+#define BCHP_EDU_STATUS_Pending_MASK                               0x00000002
+#define BCHP_EDU_STATUS_Pending_SHIFT                              1
+#define BCHP_EDU_STATUS_Pending_DEFAULT                            0x00000000
+
+/* EDU :: STATUS :: Active [00:00] */
+#define BCHP_EDU_STATUS_Active_MASK                                0x00000001
+#define BCHP_EDU_STATUS_Active_SHIFT                               0
+#define BCHP_EDU_STATUS_Active_DEFAULT                             0x00000000
+
+/***************************************************************************
+ *DONE - EDU Done bits
+ ***************************************************************************/
+/* EDU :: DONE :: reserved0 [31:02] */
+#define BCHP_EDU_DONE_reserved0_MASK                               0xfffffffc
+#define BCHP_EDU_DONE_reserved0_SHIFT                              2
+
+/* EDU :: DONE :: Done [01:00] */
+#define BCHP_EDU_DONE_Done_MASK                                    0x00000003
+#define BCHP_EDU_DONE_Done_SHIFT                                   0
+#define BCHP_EDU_DONE_Done_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *ERR_STATUS - EDU Error Status
+ ***************************************************************************/
+/* EDU :: ERR_STATUS :: reserved0 [31:04] */
+#define BCHP_EDU_ERR_STATUS_reserved0_MASK                         0xfffffff0
+#define BCHP_EDU_ERR_STATUS_reserved0_SHIFT                        4
+
+/* EDU :: ERR_STATUS :: NandWrErr [03:03] */
+#define BCHP_EDU_ERR_STATUS_NandWrErr_MASK                         0x00000008
+#define BCHP_EDU_ERR_STATUS_NandWrErr_SHIFT                        3
+#define BCHP_EDU_ERR_STATUS_NandWrErr_DEFAULT                      0x00000000
+
+/* EDU :: ERR_STATUS :: NandECCuncor [02:02] */
+#define BCHP_EDU_ERR_STATUS_NandECCuncor_MASK                      0x00000004
+#define BCHP_EDU_ERR_STATUS_NandECCuncor_SHIFT                     2
+#define BCHP_EDU_ERR_STATUS_NandECCuncor_DEFAULT                   0x00000000
+
+/* EDU :: ERR_STATUS :: NandECCcor [01:01] */
+#define BCHP_EDU_ERR_STATUS_NandECCcor_MASK                        0x00000002
+#define BCHP_EDU_ERR_STATUS_NandECCcor_SHIFT                       1
+#define BCHP_EDU_ERR_STATUS_NandECCcor_DEFAULT                     0x00000000
+
+/* EDU :: ERR_STATUS :: ErrAck [00:00] */
+#define BCHP_EDU_ERR_STATUS_ErrAck_MASK                            0x00000001
+#define BCHP_EDU_ERR_STATUS_ErrAck_SHIFT                           0
+#define BCHP_EDU_ERR_STATUS_ErrAck_DEFAULT                         0x00000000
+
+#endif /* #ifndef BCHP_EDU_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_gio.h b/include/linux/brcmstb/7429b0/bchp_gio.h
new file mode 100644
index 0000000..f0dab70
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_gio.h
@@ -0,0 +1,440 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:14 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_GIO_H__
+#define BCHP_GIO_H__
+
+/***************************************************************************
+ *GIO - GPIO
+ ***************************************************************************/
+#define BCHP_GIO_ODEN_LO                         0x00406500 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE [31:0] */
+#define BCHP_GIO_DATA_LO                         0x00406504 /* GENERAL PURPOSE I/O DATA [31:0] */
+#define BCHP_GIO_IODIR_LO                        0x00406508 /* GENERAL PURPOSE I/O DIRECTION [31:0] */
+#define BCHP_GIO_EC_LO                           0x0040650c /* GENERAL PURPOSE I/O EDGE CONFIGURATION [31:0] */
+#define BCHP_GIO_EI_LO                           0x00406510 /* GENERAL PURPOSE I/O EDGE INSENSITIVE [31:0] */
+#define BCHP_GIO_MASK_LO                         0x00406514 /* GENERAL PURPOSE I/O INTERRUPT MASK [31:0] */
+#define BCHP_GIO_LEVEL_LO                        0x00406518 /* GENERAL PURPOSE I/O INTERRUPT TYPE [31:0] */
+#define BCHP_GIO_STAT_LO                         0x0040651c /* GENERAL PURPOSE I/O INTERRUPT STATUS [31:0] */
+#define BCHP_GIO_ODEN_HI                         0x00406520 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE [63:32] */
+#define BCHP_GIO_DATA_HI                         0x00406524 /* GENERAL PURPOSE I/O DATA [63:32] */
+#define BCHP_GIO_IODIR_HI                        0x00406528 /* GENERAL PURPOSE I/O DIRECTION [63:32] */
+#define BCHP_GIO_EC_HI                           0x0040652c /* GENERAL PURPOSE I/O EDGE CONFIGURATION [63:32] */
+#define BCHP_GIO_EI_HI                           0x00406530 /* GENERAL PURPOSE I/O EDGE INSENSITIVE [63:32] */
+#define BCHP_GIO_MASK_HI                         0x00406534 /* GENERAL PURPOSE I/O INTERRUPT MASK [63:32] */
+#define BCHP_GIO_LEVEL_HI                        0x00406538 /* GENERAL PURPOSE I/O INTERRUPT TYPE [63:32] */
+#define BCHP_GIO_STAT_HI                         0x0040653c /* GENERAL PURPOSE I/O INTERRUPT STATUS [63:32] */
+#define BCHP_GIO_ODEN_EXT                        0x00406540 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE [95:64] (GPIO[91:64], SGPIO[3:0]) */
+#define BCHP_GIO_DATA_EXT                        0x00406544 /* GENERAL PURPOSE I/O DATA [95:64] (GPIO[91:64], SGPIO[3:0]) */
+#define BCHP_GIO_IODIR_EXT                       0x00406548 /* GENERAL PURPOSE I/O DIRECTION [95:64] (GPIO[91:64], SGPIO[3:0]) */
+#define BCHP_GIO_EC_EXT                          0x0040654c /* GENERAL PURPOSE I/O EDGE CONFIGURATION [95:64] (GPIO[91:64], SGPIO[3:0]) */
+#define BCHP_GIO_EI_EXT                          0x00406550 /* GENERAL PURPOSE I/O EDGE INSENSITIVE [95:64] (GPIO[91:64], SGPIO[3:0]) */
+#define BCHP_GIO_MASK_EXT                        0x00406554 /* GENERAL PURPOSE I/O INTERRUPT MASK [95:64] (GPIO[91:64], SGPIO[3:0]) */
+#define BCHP_GIO_LEVEL_EXT                       0x00406558 /* GENERAL PURPOSE I/O INTERRUPT TYPE [95:64] (GPIO[91:64], SGPIO[3:0]) */
+#define BCHP_GIO_STAT_EXT                        0x0040655c /* GENERAL PURPOSE I/O INTERRUPT STATUS [95:64] (GPIO[91:64], SGPIO[3:0]) */
+#define BCHP_GIO_ODEN_EXT_HI                     0x00406560 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE [127:96] (GPIO[123:92]) */
+#define BCHP_GIO_DATA_EXT_HI                     0x00406564 /* GENERAL PURPOSE I/O DATA [127:96] (GPIO[123:92]) */
+#define BCHP_GIO_IODIR_EXT_HI                    0x00406568 /* GENERAL PURPOSE I/O DIRECTION [127:96] (GPIO[123:92]) */
+#define BCHP_GIO_EC_EXT_HI                       0x0040656c /* GENERAL PURPOSE I/O EDGE CONFIGURATION [127:96] (GPIO[123:92]) */
+#define BCHP_GIO_EI_EXT_HI                       0x00406570 /* GENERAL PURPOSE I/O EDGE INSENSITIVE [127:96] (GPIO[123:92]) */
+#define BCHP_GIO_MASK_EXT_HI                     0x00406574 /* GENERAL PURPOSE I/O INTERRUPT MASK [127:96] (GPIO[123:92]) */
+#define BCHP_GIO_LEVEL_EXT_HI                    0x00406578 /* GENERAL PURPOSE I/O INTERRUPT TYPE [127:96] (GPIO[123:92]) */
+#define BCHP_GIO_STAT_EXT_HI                     0x0040657c /* GENERAL PURPOSE I/O INTERRUPT STATUS [127:96] (GPIO[123:92]) */
+#define BCHP_GIO_ODEN_EXT2                       0x00406580 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE [153:128] (GPIO[149:124]) */
+#define BCHP_GIO_DATA_EXT2                       0x00406584 /* GENERAL PURPOSE I/O DATA [153:128] (GPIO[149:124]) */
+#define BCHP_GIO_IODIR_EXT2                      0x00406588 /* GENERAL PURPOSE I/O DIRECTION [153:128] (GPIO[149:124]) */
+#define BCHP_GIO_EC_EXT2                         0x0040658c /* GENERAL PURPOSE I/O EDGE CONFIGURATION [153:128] (GPIO[149:124]) */
+#define BCHP_GIO_EI_EXT2                         0x00406590 /* GENERAL PURPOSE I/O EDGE INSENSITIVE [153:128] (GPIO[149:124]) */
+#define BCHP_GIO_MASK_EXT2                       0x00406594 /* GENERAL PURPOSE I/O INTERRUPT MASK [153:128] (GPIO[149:124]) */
+#define BCHP_GIO_LEVEL_EXT2                      0x00406598 /* GENERAL PURPOSE I/O INTERRUPT TYPE [153:128] (GPIO[149:124]) */
+#define BCHP_GIO_STAT_EXT2                       0x0040659c /* GENERAL PURPOSE I/O INTERRUPT STATUS [153:128] (GPIO[149:124]) */
+
+/***************************************************************************
+ *ODEN_LO - GENERAL PURPOSE I/O OPEN DRAIN ENABLE [31:0]
+ ***************************************************************************/
+/* GIO :: ODEN_LO :: oden [31:00] */
+#define BCHP_GIO_ODEN_LO_oden_MASK                                 0xffffffff
+#define BCHP_GIO_ODEN_LO_oden_SHIFT                                0
+#define BCHP_GIO_ODEN_LO_oden_DEFAULT                              0x00000000
+
+/***************************************************************************
+ *DATA_LO - GENERAL PURPOSE I/O DATA [31:0]
+ ***************************************************************************/
+/* GIO :: DATA_LO :: data [31:00] */
+#define BCHP_GIO_DATA_LO_data_MASK                                 0xffffffff
+#define BCHP_GIO_DATA_LO_data_SHIFT                                0
+#define BCHP_GIO_DATA_LO_data_DEFAULT                              0x00000000
+
+/***************************************************************************
+ *IODIR_LO - GENERAL PURPOSE I/O DIRECTION [31:0]
+ ***************************************************************************/
+/* GIO :: IODIR_LO :: iodir [31:00] */
+#define BCHP_GIO_IODIR_LO_iodir_MASK                               0xffffffff
+#define BCHP_GIO_IODIR_LO_iodir_SHIFT                              0
+#define BCHP_GIO_IODIR_LO_iodir_DEFAULT                            0xffffffff
+
+/***************************************************************************
+ *EC_LO - GENERAL PURPOSE I/O EDGE CONFIGURATION [31:0]
+ ***************************************************************************/
+/* GIO :: EC_LO :: edge_config [31:00] */
+#define BCHP_GIO_EC_LO_edge_config_MASK                            0xffffffff
+#define BCHP_GIO_EC_LO_edge_config_SHIFT                           0
+#define BCHP_GIO_EC_LO_edge_config_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *EI_LO - GENERAL PURPOSE I/O EDGE INSENSITIVE [31:0]
+ ***************************************************************************/
+/* GIO :: EI_LO :: edge_insensitive [31:00] */
+#define BCHP_GIO_EI_LO_edge_insensitive_MASK                       0xffffffff
+#define BCHP_GIO_EI_LO_edge_insensitive_SHIFT                      0
+#define BCHP_GIO_EI_LO_edge_insensitive_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *MASK_LO - GENERAL PURPOSE I/O INTERRUPT MASK [31:0]
+ ***************************************************************************/
+/* GIO :: MASK_LO :: irq_mask [31:00] */
+#define BCHP_GIO_MASK_LO_irq_mask_MASK                             0xffffffff
+#define BCHP_GIO_MASK_LO_irq_mask_SHIFT                            0
+#define BCHP_GIO_MASK_LO_irq_mask_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *LEVEL_LO - GENERAL PURPOSE I/O INTERRUPT TYPE [31:0]
+ ***************************************************************************/
+/* GIO :: LEVEL_LO :: level [31:00] */
+#define BCHP_GIO_LEVEL_LO_level_MASK                               0xffffffff
+#define BCHP_GIO_LEVEL_LO_level_SHIFT                              0
+#define BCHP_GIO_LEVEL_LO_level_DEFAULT                            0x00000000
+
+/***************************************************************************
+ *STAT_LO - GENERAL PURPOSE I/O INTERRUPT STATUS [31:0]
+ ***************************************************************************/
+/* GIO :: STAT_LO :: irq_status [31:00] */
+#define BCHP_GIO_STAT_LO_irq_status_MASK                           0xffffffff
+#define BCHP_GIO_STAT_LO_irq_status_SHIFT                          0
+#define BCHP_GIO_STAT_LO_irq_status_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *ODEN_HI - GENERAL PURPOSE I/O OPEN DRAIN ENABLE [63:32]
+ ***************************************************************************/
+/* GIO :: ODEN_HI :: oden [31:00] */
+#define BCHP_GIO_ODEN_HI_oden_MASK                                 0xffffffff
+#define BCHP_GIO_ODEN_HI_oden_SHIFT                                0
+#define BCHP_GIO_ODEN_HI_oden_DEFAULT                              0x00000000
+
+/***************************************************************************
+ *DATA_HI - GENERAL PURPOSE I/O DATA [63:32]
+ ***************************************************************************/
+/* GIO :: DATA_HI :: data [31:00] */
+#define BCHP_GIO_DATA_HI_data_MASK                                 0xffffffff
+#define BCHP_GIO_DATA_HI_data_SHIFT                                0
+#define BCHP_GIO_DATA_HI_data_DEFAULT                              0x00000000
+
+/***************************************************************************
+ *IODIR_HI - GENERAL PURPOSE I/O DIRECTION [63:32]
+ ***************************************************************************/
+/* GIO :: IODIR_HI :: iodir [31:00] */
+#define BCHP_GIO_IODIR_HI_iodir_MASK                               0xffffffff
+#define BCHP_GIO_IODIR_HI_iodir_SHIFT                              0
+#define BCHP_GIO_IODIR_HI_iodir_DEFAULT                            0xffffffff
+
+/***************************************************************************
+ *EC_HI - GENERAL PURPOSE I/O EDGE CONFIGURATION [63:32]
+ ***************************************************************************/
+/* GIO :: EC_HI :: edge_config [31:00] */
+#define BCHP_GIO_EC_HI_edge_config_MASK                            0xffffffff
+#define BCHP_GIO_EC_HI_edge_config_SHIFT                           0
+#define BCHP_GIO_EC_HI_edge_config_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *EI_HI - GENERAL PURPOSE I/O EDGE INSENSITIVE [63:32]
+ ***************************************************************************/
+/* GIO :: EI_HI :: edge_insensitive [31:00] */
+#define BCHP_GIO_EI_HI_edge_insensitive_MASK                       0xffffffff
+#define BCHP_GIO_EI_HI_edge_insensitive_SHIFT                      0
+#define BCHP_GIO_EI_HI_edge_insensitive_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *MASK_HI - GENERAL PURPOSE I/O INTERRUPT MASK [63:32]
+ ***************************************************************************/
+/* GIO :: MASK_HI :: irq_mask [31:00] */
+#define BCHP_GIO_MASK_HI_irq_mask_MASK                             0xffffffff
+#define BCHP_GIO_MASK_HI_irq_mask_SHIFT                            0
+#define BCHP_GIO_MASK_HI_irq_mask_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *LEVEL_HI - GENERAL PURPOSE I/O INTERRUPT TYPE [63:32]
+ ***************************************************************************/
+/* GIO :: LEVEL_HI :: level [31:00] */
+#define BCHP_GIO_LEVEL_HI_level_MASK                               0xffffffff
+#define BCHP_GIO_LEVEL_HI_level_SHIFT                              0
+#define BCHP_GIO_LEVEL_HI_level_DEFAULT                            0x00000000
+
+/***************************************************************************
+ *STAT_HI - GENERAL PURPOSE I/O INTERRUPT STATUS [63:32]
+ ***************************************************************************/
+/* GIO :: STAT_HI :: irq_status [31:00] */
+#define BCHP_GIO_STAT_HI_irq_status_MASK                           0xffffffff
+#define BCHP_GIO_STAT_HI_irq_status_SHIFT                          0
+#define BCHP_GIO_STAT_HI_irq_status_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *ODEN_EXT - GENERAL PURPOSE I/O OPEN DRAIN ENABLE [95:64] (GPIO[91:64], SGPIO[3:0])
+ ***************************************************************************/
+/* GIO :: ODEN_EXT :: oden [31:00] */
+#define BCHP_GIO_ODEN_EXT_oden_MASK                                0xffffffff
+#define BCHP_GIO_ODEN_EXT_oden_SHIFT                               0
+#define BCHP_GIO_ODEN_EXT_oden_DEFAULT                             0x00000000
+
+/***************************************************************************
+ *DATA_EXT - GENERAL PURPOSE I/O DATA [95:64] (GPIO[91:64], SGPIO[3:0])
+ ***************************************************************************/
+/* GIO :: DATA_EXT :: data [31:00] */
+#define BCHP_GIO_DATA_EXT_data_MASK                                0xffffffff
+#define BCHP_GIO_DATA_EXT_data_SHIFT                               0
+#define BCHP_GIO_DATA_EXT_data_DEFAULT                             0x00000000
+
+/***************************************************************************
+ *IODIR_EXT - GENERAL PURPOSE I/O DIRECTION [95:64] (GPIO[91:64], SGPIO[3:0])
+ ***************************************************************************/
+/* GIO :: IODIR_EXT :: iodir [31:00] */
+#define BCHP_GIO_IODIR_EXT_iodir_MASK                              0xffffffff
+#define BCHP_GIO_IODIR_EXT_iodir_SHIFT                             0
+#define BCHP_GIO_IODIR_EXT_iodir_DEFAULT                           0xffffffff
+
+/***************************************************************************
+ *EC_EXT - GENERAL PURPOSE I/O EDGE CONFIGURATION [95:64] (GPIO[91:64], SGPIO[3:0])
+ ***************************************************************************/
+/* GIO :: EC_EXT :: edge_config [31:00] */
+#define BCHP_GIO_EC_EXT_edge_config_MASK                           0xffffffff
+#define BCHP_GIO_EC_EXT_edge_config_SHIFT                          0
+#define BCHP_GIO_EC_EXT_edge_config_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *EI_EXT - GENERAL PURPOSE I/O EDGE INSENSITIVE [95:64] (GPIO[91:64], SGPIO[3:0])
+ ***************************************************************************/
+/* GIO :: EI_EXT :: edge_insensitive [31:00] */
+#define BCHP_GIO_EI_EXT_edge_insensitive_MASK                      0xffffffff
+#define BCHP_GIO_EI_EXT_edge_insensitive_SHIFT                     0
+#define BCHP_GIO_EI_EXT_edge_insensitive_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *MASK_EXT - GENERAL PURPOSE I/O INTERRUPT MASK [95:64] (GPIO[91:64], SGPIO[3:0])
+ ***************************************************************************/
+/* GIO :: MASK_EXT :: irq_mask [31:00] */
+#define BCHP_GIO_MASK_EXT_irq_mask_MASK                            0xffffffff
+#define BCHP_GIO_MASK_EXT_irq_mask_SHIFT                           0
+#define BCHP_GIO_MASK_EXT_irq_mask_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *LEVEL_EXT - GENERAL PURPOSE I/O INTERRUPT TYPE [95:64] (GPIO[91:64], SGPIO[3:0])
+ ***************************************************************************/
+/* GIO :: LEVEL_EXT :: level [31:00] */
+#define BCHP_GIO_LEVEL_EXT_level_MASK                              0xffffffff
+#define BCHP_GIO_LEVEL_EXT_level_SHIFT                             0
+#define BCHP_GIO_LEVEL_EXT_level_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *STAT_EXT - GENERAL PURPOSE I/O INTERRUPT STATUS [95:64] (GPIO[91:64], SGPIO[3:0])
+ ***************************************************************************/
+/* GIO :: STAT_EXT :: irq_status [31:00] */
+#define BCHP_GIO_STAT_EXT_irq_status_MASK                          0xffffffff
+#define BCHP_GIO_STAT_EXT_irq_status_SHIFT                         0
+#define BCHP_GIO_STAT_EXT_irq_status_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *ODEN_EXT_HI - GENERAL PURPOSE I/O OPEN DRAIN ENABLE [127:96] (GPIO[123:92])
+ ***************************************************************************/
+/* GIO :: ODEN_EXT_HI :: oden [31:00] */
+#define BCHP_GIO_ODEN_EXT_HI_oden_MASK                             0xffffffff
+#define BCHP_GIO_ODEN_EXT_HI_oden_SHIFT                            0
+#define BCHP_GIO_ODEN_EXT_HI_oden_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *DATA_EXT_HI - GENERAL PURPOSE I/O DATA [127:96] (GPIO[123:92])
+ ***************************************************************************/
+/* GIO :: DATA_EXT_HI :: data [31:00] */
+#define BCHP_GIO_DATA_EXT_HI_data_MASK                             0xffffffff
+#define BCHP_GIO_DATA_EXT_HI_data_SHIFT                            0
+#define BCHP_GIO_DATA_EXT_HI_data_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *IODIR_EXT_HI - GENERAL PURPOSE I/O DIRECTION [127:96] (GPIO[123:92])
+ ***************************************************************************/
+/* GIO :: IODIR_EXT_HI :: iodir [31:00] */
+#define BCHP_GIO_IODIR_EXT_HI_iodir_MASK                           0xffffffff
+#define BCHP_GIO_IODIR_EXT_HI_iodir_SHIFT                          0
+#define BCHP_GIO_IODIR_EXT_HI_iodir_DEFAULT                        0xffffffff
+
+/***************************************************************************
+ *EC_EXT_HI - GENERAL PURPOSE I/O EDGE CONFIGURATION [127:96] (GPIO[123:92])
+ ***************************************************************************/
+/* GIO :: EC_EXT_HI :: edge_config [31:00] */
+#define BCHP_GIO_EC_EXT_HI_edge_config_MASK                        0xffffffff
+#define BCHP_GIO_EC_EXT_HI_edge_config_SHIFT                       0
+#define BCHP_GIO_EC_EXT_HI_edge_config_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *EI_EXT_HI - GENERAL PURPOSE I/O EDGE INSENSITIVE [127:96] (GPIO[123:92])
+ ***************************************************************************/
+/* GIO :: EI_EXT_HI :: edge_insensitive [31:00] */
+#define BCHP_GIO_EI_EXT_HI_edge_insensitive_MASK                   0xffffffff
+#define BCHP_GIO_EI_EXT_HI_edge_insensitive_SHIFT                  0
+#define BCHP_GIO_EI_EXT_HI_edge_insensitive_DEFAULT                0x00000000
+
+/***************************************************************************
+ *MASK_EXT_HI - GENERAL PURPOSE I/O INTERRUPT MASK [127:96] (GPIO[123:92])
+ ***************************************************************************/
+/* GIO :: MASK_EXT_HI :: irq_mask [31:00] */
+#define BCHP_GIO_MASK_EXT_HI_irq_mask_MASK                         0xffffffff
+#define BCHP_GIO_MASK_EXT_HI_irq_mask_SHIFT                        0
+#define BCHP_GIO_MASK_EXT_HI_irq_mask_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *LEVEL_EXT_HI - GENERAL PURPOSE I/O INTERRUPT TYPE [127:96] (GPIO[123:92])
+ ***************************************************************************/
+/* GIO :: LEVEL_EXT_HI :: level [31:00] */
+#define BCHP_GIO_LEVEL_EXT_HI_level_MASK                           0xffffffff
+#define BCHP_GIO_LEVEL_EXT_HI_level_SHIFT                          0
+#define BCHP_GIO_LEVEL_EXT_HI_level_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *STAT_EXT_HI - GENERAL PURPOSE I/O INTERRUPT STATUS [127:96] (GPIO[123:92])
+ ***************************************************************************/
+/* GIO :: STAT_EXT_HI :: irq_status [31:00] */
+#define BCHP_GIO_STAT_EXT_HI_irq_status_MASK                       0xffffffff
+#define BCHP_GIO_STAT_EXT_HI_irq_status_SHIFT                      0
+#define BCHP_GIO_STAT_EXT_HI_irq_status_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *ODEN_EXT2 - GENERAL PURPOSE I/O OPEN DRAIN ENABLE [153:128] (GPIO[149:124])
+ ***************************************************************************/
+/* GIO :: ODEN_EXT2 :: reserved0 [31:26] */
+#define BCHP_GIO_ODEN_EXT2_reserved0_MASK                          0xfc000000
+#define BCHP_GIO_ODEN_EXT2_reserved0_SHIFT                         26
+
+/* GIO :: ODEN_EXT2 :: oden [25:00] */
+#define BCHP_GIO_ODEN_EXT2_oden_MASK                               0x03ffffff
+#define BCHP_GIO_ODEN_EXT2_oden_SHIFT                              0
+#define BCHP_GIO_ODEN_EXT2_oden_DEFAULT                            0x00000000
+
+/***************************************************************************
+ *DATA_EXT2 - GENERAL PURPOSE I/O DATA [153:128] (GPIO[149:124])
+ ***************************************************************************/
+/* GIO :: DATA_EXT2 :: reserved0 [31:26] */
+#define BCHP_GIO_DATA_EXT2_reserved0_MASK                          0xfc000000
+#define BCHP_GIO_DATA_EXT2_reserved0_SHIFT                         26
+
+/* GIO :: DATA_EXT2 :: data [25:00] */
+#define BCHP_GIO_DATA_EXT2_data_MASK                               0x03ffffff
+#define BCHP_GIO_DATA_EXT2_data_SHIFT                              0
+#define BCHP_GIO_DATA_EXT2_data_DEFAULT                            0x00000000
+
+/***************************************************************************
+ *IODIR_EXT2 - GENERAL PURPOSE I/O DIRECTION [153:128] (GPIO[149:124])
+ ***************************************************************************/
+/* GIO :: IODIR_EXT2 :: reserved0 [31:26] */
+#define BCHP_GIO_IODIR_EXT2_reserved0_MASK                         0xfc000000
+#define BCHP_GIO_IODIR_EXT2_reserved0_SHIFT                        26
+
+/* GIO :: IODIR_EXT2 :: iodir [25:00] */
+#define BCHP_GIO_IODIR_EXT2_iodir_MASK                             0x03ffffff
+#define BCHP_GIO_IODIR_EXT2_iodir_SHIFT                            0
+#define BCHP_GIO_IODIR_EXT2_iodir_DEFAULT                          0x03ffffff
+
+/***************************************************************************
+ *EC_EXT2 - GENERAL PURPOSE I/O EDGE CONFIGURATION [153:128] (GPIO[149:124])
+ ***************************************************************************/
+/* GIO :: EC_EXT2 :: reserved0 [31:26] */
+#define BCHP_GIO_EC_EXT2_reserved0_MASK                            0xfc000000
+#define BCHP_GIO_EC_EXT2_reserved0_SHIFT                           26
+
+/* GIO :: EC_EXT2 :: edge_config [25:00] */
+#define BCHP_GIO_EC_EXT2_edge_config_MASK                          0x03ffffff
+#define BCHP_GIO_EC_EXT2_edge_config_SHIFT                         0
+#define BCHP_GIO_EC_EXT2_edge_config_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *EI_EXT2 - GENERAL PURPOSE I/O EDGE INSENSITIVE [153:128] (GPIO[149:124])
+ ***************************************************************************/
+/* GIO :: EI_EXT2 :: reserved0 [31:26] */
+#define BCHP_GIO_EI_EXT2_reserved0_MASK                            0xfc000000
+#define BCHP_GIO_EI_EXT2_reserved0_SHIFT                           26
+
+/* GIO :: EI_EXT2 :: edge_insensitive [25:00] */
+#define BCHP_GIO_EI_EXT2_edge_insensitive_MASK                     0x03ffffff
+#define BCHP_GIO_EI_EXT2_edge_insensitive_SHIFT                    0
+#define BCHP_GIO_EI_EXT2_edge_insensitive_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *MASK_EXT2 - GENERAL PURPOSE I/O INTERRUPT MASK [153:128] (GPIO[149:124])
+ ***************************************************************************/
+/* GIO :: MASK_EXT2 :: reserved0 [31:26] */
+#define BCHP_GIO_MASK_EXT2_reserved0_MASK                          0xfc000000
+#define BCHP_GIO_MASK_EXT2_reserved0_SHIFT                         26
+
+/* GIO :: MASK_EXT2 :: irq_mask [25:00] */
+#define BCHP_GIO_MASK_EXT2_irq_mask_MASK                           0x03ffffff
+#define BCHP_GIO_MASK_EXT2_irq_mask_SHIFT                          0
+#define BCHP_GIO_MASK_EXT2_irq_mask_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *LEVEL_EXT2 - GENERAL PURPOSE I/O INTERRUPT TYPE [153:128] (GPIO[149:124])
+ ***************************************************************************/
+/* GIO :: LEVEL_EXT2 :: reserved0 [31:26] */
+#define BCHP_GIO_LEVEL_EXT2_reserved0_MASK                         0xfc000000
+#define BCHP_GIO_LEVEL_EXT2_reserved0_SHIFT                        26
+
+/* GIO :: LEVEL_EXT2 :: level [25:00] */
+#define BCHP_GIO_LEVEL_EXT2_level_MASK                             0x03ffffff
+#define BCHP_GIO_LEVEL_EXT2_level_SHIFT                            0
+#define BCHP_GIO_LEVEL_EXT2_level_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *STAT_EXT2 - GENERAL PURPOSE I/O INTERRUPT STATUS [153:128] (GPIO[149:124])
+ ***************************************************************************/
+/* GIO :: STAT_EXT2 :: reserved0 [31:26] */
+#define BCHP_GIO_STAT_EXT2_reserved0_MASK                          0xfc000000
+#define BCHP_GIO_STAT_EXT2_reserved0_SHIFT                         26
+
+/* GIO :: STAT_EXT2 :: irq_status [25:00] */
+#define BCHP_GIO_STAT_EXT2_irq_status_MASK                         0x03ffffff
+#define BCHP_GIO_STAT_EXT2_irq_status_SHIFT                        0
+#define BCHP_GIO_STAT_EXT2_irq_status_DEFAULT                      0x00000000
+
+#endif /* #ifndef BCHP_GIO_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_gio_aon.h b/include/linux/brcmstb/7429b0/bchp_gio_aon.h
new file mode 100644
index 0000000..567895f
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_gio_aon.h
@@ -0,0 +1,264 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:16 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_GIO_AON_H__
+#define BCHP_GIO_AON_H__
+
+/***************************************************************************
+ *GIO_AON - GPIO
+ ***************************************************************************/
+#define BCHP_GIO_AON_ODEN_LO                     0x00409800 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE [20:0] */
+#define BCHP_GIO_AON_DATA_LO                     0x00409804 /* GENERAL PURPOSE I/O DATA [20:0] */
+#define BCHP_GIO_AON_IODIR_LO                    0x00409808 /* GENERAL PURPOSE I/O DIRECTION [20:0] */
+#define BCHP_GIO_AON_EC_LO                       0x0040980c /* GENERAL PURPOSE I/O EDGE CONFIGURATION [20:0] */
+#define BCHP_GIO_AON_EI_LO                       0x00409810 /* GENERAL PURPOSE I/O EDGE INSENSITIVE [20:0] */
+#define BCHP_GIO_AON_MASK_LO                     0x00409814 /* GENERAL PURPOSE I/O INTERRUPT MASK [20:0] */
+#define BCHP_GIO_AON_LEVEL_LO                    0x00409818 /* GENERAL PURPOSE I/O INTERRUPT TYPE [20:0] */
+#define BCHP_GIO_AON_STAT_LO                     0x0040981c /* GENERAL PURPOSE I/O INTERRUPT STATUS [20:0] */
+#define BCHP_GIO_AON_ODEN_EXT                    0x00409840 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE [69:64] (SGPIO[5:0]) */
+#define BCHP_GIO_AON_DATA_EXT                    0x00409844 /* GENERAL PURPOSE I/O DATA [69:64] (SGPIO[5:0]) */
+#define BCHP_GIO_AON_IODIR_EXT                   0x00409848 /* GENERAL PURPOSE I/O DIRECTION [69:64] (SGPIO[5:0]) */
+#define BCHP_GIO_AON_EC_EXT                      0x0040984c /* GENERAL PURPOSE I/O EDGE CONFIGURATION [69:64] (SGPIO[5:0]) */
+#define BCHP_GIO_AON_EI_EXT                      0x00409850 /* GENERAL PURPOSE I/O EDGE INSENSITIVE [69:64] (SGPIO[5:0]) */
+#define BCHP_GIO_AON_MASK_EXT                    0x00409854 /* GENERAL PURPOSE I/O INTERRUPT MASK [69:64] (SGPIO[5:0]) */
+#define BCHP_GIO_AON_LEVEL_EXT                   0x00409858 /* GENERAL PURPOSE I/O INTERRUPT TYPE [69:64] (SGPIO[5:0]) */
+#define BCHP_GIO_AON_STAT_EXT                    0x0040985c /* GENERAL PURPOSE I/O INTERRUPT STATUS [69:64] (SGPIO[5:0]) */
+
+/***************************************************************************
+ *ODEN_LO - GENERAL PURPOSE I/O OPEN DRAIN ENABLE [20:0]
+ ***************************************************************************/
+/* GIO_AON :: ODEN_LO :: spare [31:21] */
+#define BCHP_GIO_AON_ODEN_LO_spare_MASK                            0xffe00000
+#define BCHP_GIO_AON_ODEN_LO_spare_SHIFT                           21
+#define BCHP_GIO_AON_ODEN_LO_spare_DEFAULT                         0x00000000
+
+/* GIO_AON :: ODEN_LO :: oden [20:00] */
+#define BCHP_GIO_AON_ODEN_LO_oden_MASK                             0x001fffff
+#define BCHP_GIO_AON_ODEN_LO_oden_SHIFT                            0
+#define BCHP_GIO_AON_ODEN_LO_oden_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *DATA_LO - GENERAL PURPOSE I/O DATA [20:0]
+ ***************************************************************************/
+/* GIO_AON :: DATA_LO :: spare [31:21] */
+#define BCHP_GIO_AON_DATA_LO_spare_MASK                            0xffe00000
+#define BCHP_GIO_AON_DATA_LO_spare_SHIFT                           21
+#define BCHP_GIO_AON_DATA_LO_spare_DEFAULT                         0x00000000
+
+/* GIO_AON :: DATA_LO :: data [20:00] */
+#define BCHP_GIO_AON_DATA_LO_data_MASK                             0x001fffff
+#define BCHP_GIO_AON_DATA_LO_data_SHIFT                            0
+#define BCHP_GIO_AON_DATA_LO_data_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *IODIR_LO - GENERAL PURPOSE I/O DIRECTION [20:0]
+ ***************************************************************************/
+/* GIO_AON :: IODIR_LO :: spare [31:21] */
+#define BCHP_GIO_AON_IODIR_LO_spare_MASK                           0xffe00000
+#define BCHP_GIO_AON_IODIR_LO_spare_SHIFT                          21
+#define BCHP_GIO_AON_IODIR_LO_spare_DEFAULT                        0x000007ff
+
+/* GIO_AON :: IODIR_LO :: iodir [20:00] */
+#define BCHP_GIO_AON_IODIR_LO_iodir_MASK                           0x001fffff
+#define BCHP_GIO_AON_IODIR_LO_iodir_SHIFT                          0
+#define BCHP_GIO_AON_IODIR_LO_iodir_DEFAULT                        0x001fffff
+
+/***************************************************************************
+ *EC_LO - GENERAL PURPOSE I/O EDGE CONFIGURATION [20:0]
+ ***************************************************************************/
+/* GIO_AON :: EC_LO :: spare [31:21] */
+#define BCHP_GIO_AON_EC_LO_spare_MASK                              0xffe00000
+#define BCHP_GIO_AON_EC_LO_spare_SHIFT                             21
+#define BCHP_GIO_AON_EC_LO_spare_DEFAULT                           0x00000000
+
+/* GIO_AON :: EC_LO :: edge_config [20:00] */
+#define BCHP_GIO_AON_EC_LO_edge_config_MASK                        0x001fffff
+#define BCHP_GIO_AON_EC_LO_edge_config_SHIFT                       0
+#define BCHP_GIO_AON_EC_LO_edge_config_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *EI_LO - GENERAL PURPOSE I/O EDGE INSENSITIVE [20:0]
+ ***************************************************************************/
+/* GIO_AON :: EI_LO :: spare [31:21] */
+#define BCHP_GIO_AON_EI_LO_spare_MASK                              0xffe00000
+#define BCHP_GIO_AON_EI_LO_spare_SHIFT                             21
+#define BCHP_GIO_AON_EI_LO_spare_DEFAULT                           0x00000000
+
+/* GIO_AON :: EI_LO :: edge_insensitive [20:00] */
+#define BCHP_GIO_AON_EI_LO_edge_insensitive_MASK                   0x001fffff
+#define BCHP_GIO_AON_EI_LO_edge_insensitive_SHIFT                  0
+#define BCHP_GIO_AON_EI_LO_edge_insensitive_DEFAULT                0x00000000
+
+/***************************************************************************
+ *MASK_LO - GENERAL PURPOSE I/O INTERRUPT MASK [20:0]
+ ***************************************************************************/
+/* GIO_AON :: MASK_LO :: spare [31:21] */
+#define BCHP_GIO_AON_MASK_LO_spare_MASK                            0xffe00000
+#define BCHP_GIO_AON_MASK_LO_spare_SHIFT                           21
+#define BCHP_GIO_AON_MASK_LO_spare_DEFAULT                         0x00000000
+
+/* GIO_AON :: MASK_LO :: irq_mask [20:00] */
+#define BCHP_GIO_AON_MASK_LO_irq_mask_MASK                         0x001fffff
+#define BCHP_GIO_AON_MASK_LO_irq_mask_SHIFT                        0
+#define BCHP_GIO_AON_MASK_LO_irq_mask_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *LEVEL_LO - GENERAL PURPOSE I/O INTERRUPT TYPE [20:0]
+ ***************************************************************************/
+/* GIO_AON :: LEVEL_LO :: spare [31:21] */
+#define BCHP_GIO_AON_LEVEL_LO_spare_MASK                           0xffe00000
+#define BCHP_GIO_AON_LEVEL_LO_spare_SHIFT                          21
+#define BCHP_GIO_AON_LEVEL_LO_spare_DEFAULT                        0x00000000
+
+/* GIO_AON :: LEVEL_LO :: level [20:00] */
+#define BCHP_GIO_AON_LEVEL_LO_level_MASK                           0x001fffff
+#define BCHP_GIO_AON_LEVEL_LO_level_SHIFT                          0
+#define BCHP_GIO_AON_LEVEL_LO_level_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *STAT_LO - GENERAL PURPOSE I/O INTERRUPT STATUS [20:0]
+ ***************************************************************************/
+/* GIO_AON :: STAT_LO :: spare [31:21] */
+#define BCHP_GIO_AON_STAT_LO_spare_MASK                            0xffe00000
+#define BCHP_GIO_AON_STAT_LO_spare_SHIFT                           21
+#define BCHP_GIO_AON_STAT_LO_spare_DEFAULT                         0x00000000
+
+/* GIO_AON :: STAT_LO :: irq_status [20:00] */
+#define BCHP_GIO_AON_STAT_LO_irq_status_MASK                       0x001fffff
+#define BCHP_GIO_AON_STAT_LO_irq_status_SHIFT                      0
+#define BCHP_GIO_AON_STAT_LO_irq_status_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *ODEN_EXT - GENERAL PURPOSE I/O OPEN DRAIN ENABLE [69:64] (SGPIO[5:0])
+ ***************************************************************************/
+/* GIO_AON :: ODEN_EXT :: reserved0 [31:06] */
+#define BCHP_GIO_AON_ODEN_EXT_reserved0_MASK                       0xffffffc0
+#define BCHP_GIO_AON_ODEN_EXT_reserved0_SHIFT                      6
+
+/* GIO_AON :: ODEN_EXT :: oden [05:00] */
+#define BCHP_GIO_AON_ODEN_EXT_oden_MASK                            0x0000003f
+#define BCHP_GIO_AON_ODEN_EXT_oden_SHIFT                           0
+#define BCHP_GIO_AON_ODEN_EXT_oden_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *DATA_EXT - GENERAL PURPOSE I/O DATA [69:64] (SGPIO[5:0])
+ ***************************************************************************/
+/* GIO_AON :: DATA_EXT :: reserved0 [31:06] */
+#define BCHP_GIO_AON_DATA_EXT_reserved0_MASK                       0xffffffc0
+#define BCHP_GIO_AON_DATA_EXT_reserved0_SHIFT                      6
+
+/* GIO_AON :: DATA_EXT :: data [05:00] */
+#define BCHP_GIO_AON_DATA_EXT_data_MASK                            0x0000003f
+#define BCHP_GIO_AON_DATA_EXT_data_SHIFT                           0
+#define BCHP_GIO_AON_DATA_EXT_data_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *IODIR_EXT - GENERAL PURPOSE I/O DIRECTION [69:64] (SGPIO[5:0])
+ ***************************************************************************/
+/* GIO_AON :: IODIR_EXT :: reserved0 [31:06] */
+#define BCHP_GIO_AON_IODIR_EXT_reserved0_MASK                      0xffffffc0
+#define BCHP_GIO_AON_IODIR_EXT_reserved0_SHIFT                     6
+
+/* GIO_AON :: IODIR_EXT :: iodir [05:00] */
+#define BCHP_GIO_AON_IODIR_EXT_iodir_MASK                          0x0000003f
+#define BCHP_GIO_AON_IODIR_EXT_iodir_SHIFT                         0
+#define BCHP_GIO_AON_IODIR_EXT_iodir_DEFAULT                       0x00000003
+
+/***************************************************************************
+ *EC_EXT - GENERAL PURPOSE I/O EDGE CONFIGURATION [69:64] (SGPIO[5:0])
+ ***************************************************************************/
+/* GIO_AON :: EC_EXT :: reserved0 [31:06] */
+#define BCHP_GIO_AON_EC_EXT_reserved0_MASK                         0xffffffc0
+#define BCHP_GIO_AON_EC_EXT_reserved0_SHIFT                        6
+
+/* GIO_AON :: EC_EXT :: edge_config [05:00] */
+#define BCHP_GIO_AON_EC_EXT_edge_config_MASK                       0x0000003f
+#define BCHP_GIO_AON_EC_EXT_edge_config_SHIFT                      0
+#define BCHP_GIO_AON_EC_EXT_edge_config_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *EI_EXT - GENERAL PURPOSE I/O EDGE INSENSITIVE [69:64] (SGPIO[5:0])
+ ***************************************************************************/
+/* GIO_AON :: EI_EXT :: reserved0 [31:06] */
+#define BCHP_GIO_AON_EI_EXT_reserved0_MASK                         0xffffffc0
+#define BCHP_GIO_AON_EI_EXT_reserved0_SHIFT                        6
+
+/* GIO_AON :: EI_EXT :: edge_insensitive [05:00] */
+#define BCHP_GIO_AON_EI_EXT_edge_insensitive_MASK                  0x0000003f
+#define BCHP_GIO_AON_EI_EXT_edge_insensitive_SHIFT                 0
+#define BCHP_GIO_AON_EI_EXT_edge_insensitive_DEFAULT               0x00000000
+
+/***************************************************************************
+ *MASK_EXT - GENERAL PURPOSE I/O INTERRUPT MASK [69:64] (SGPIO[5:0])
+ ***************************************************************************/
+/* GIO_AON :: MASK_EXT :: reserved0 [31:06] */
+#define BCHP_GIO_AON_MASK_EXT_reserved0_MASK                       0xffffffc0
+#define BCHP_GIO_AON_MASK_EXT_reserved0_SHIFT                      6
+
+/* GIO_AON :: MASK_EXT :: irq_mask [05:00] */
+#define BCHP_GIO_AON_MASK_EXT_irq_mask_MASK                        0x0000003f
+#define BCHP_GIO_AON_MASK_EXT_irq_mask_SHIFT                       0
+#define BCHP_GIO_AON_MASK_EXT_irq_mask_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *LEVEL_EXT - GENERAL PURPOSE I/O INTERRUPT TYPE [69:64] (SGPIO[5:0])
+ ***************************************************************************/
+/* GIO_AON :: LEVEL_EXT :: reserved0 [31:06] */
+#define BCHP_GIO_AON_LEVEL_EXT_reserved0_MASK                      0xffffffc0
+#define BCHP_GIO_AON_LEVEL_EXT_reserved0_SHIFT                     6
+
+/* GIO_AON :: LEVEL_EXT :: level [05:00] */
+#define BCHP_GIO_AON_LEVEL_EXT_level_MASK                          0x0000003f
+#define BCHP_GIO_AON_LEVEL_EXT_level_SHIFT                         0
+#define BCHP_GIO_AON_LEVEL_EXT_level_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *STAT_EXT - GENERAL PURPOSE I/O INTERRUPT STATUS [69:64] (SGPIO[5:0])
+ ***************************************************************************/
+/* GIO_AON :: STAT_EXT :: reserved0 [31:06] */
+#define BCHP_GIO_AON_STAT_EXT_reserved0_MASK                       0xffffffc0
+#define BCHP_GIO_AON_STAT_EXT_reserved0_SHIFT                      6
+
+/* GIO_AON :: STAT_EXT :: irq_status [05:00] */
+#define BCHP_GIO_AON_STAT_EXT_irq_status_MASK                      0x0000003f
+#define BCHP_GIO_AON_STAT_EXT_irq_status_SHIFT                     0
+#define BCHP_GIO_AON_STAT_EXT_irq_status_DEFAULT                   0x00000000
+
+#endif /* #ifndef BCHP_GIO_AON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_hif_cpu_intr1.h b/include/linux/brcmstb/7429b0/bchp_hif_cpu_intr1.h
new file mode 100644
index 0000000..85da3bd
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_hif_cpu_intr1.h
@@ -0,0 +1,1552 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:15 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_INTR1_H__
+#define BCHP_HIF_CPU_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_INTR1 - HIF CPU Thread Processor 0 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS        0x00411400 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS        0x00411404 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS        0x00411408 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS   0x0041140c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS   0x00411410 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS   0x00411414 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET      0x00411418 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET      0x0041141c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET      0x00411420 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR    0x00411424 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR    0x00411428 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR    0x0041142c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: RFM_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_RFM_CPU_INTR_MASK        0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_RFM_CPU_INTR_SHIFT       31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_RFM_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: RAAGA_FW_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_RAAGA_FW_CPU_INTR_MASK   0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_RAAGA_FW_CPU_INTR_SHIFT  30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: RAAGA_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_RAAGA_CPU_INTR_MASK      0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_RAAGA_CPU_INTR_SHIFT     29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_RAAGA_CPU_INTR_DEFAULT   0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: NMI_PIN_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_NMI_PIN_CPU_INTR_MASK    0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_NMI_PIN_CPU_INTR_SHIFT   28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: MOCA_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MOCA_CPU_INTR_MASK       0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MOCA_CPU_INTR_SHIFT      27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MOCA_CPU_INTR_DEFAULT    0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: MEMC0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MEMC0_CPU_INTR_MASK      0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MEMC0_CPU_INTR_SHIFT     26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MEMC0_CPU_INTR_DEFAULT   0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: IPI1_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI1_CPU_INTR_MASK       0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI1_CPU_INTR_SHIFT      25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI1_CPU_INTR_DEFAULT    0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: IPI0_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI0_CPU_INTR_MASK       0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI0_CPU_INTR_SHIFT      24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI0_CPU_INTR_DEFAULT    0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK        0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT       22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK    0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT   21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HDMI_RX_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_RX_0_CPU_INTR_MASK  0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_RX_0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GFX_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_MASK        0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_SHIFT       19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_1_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_MASK  0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_1_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_MASK  0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK  0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK  0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: DVP_HR_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_DVP_HR_CPU_INTR_MASK     0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_DVP_HR_CPU_INTR_SHIFT    8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_DVP_HR_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK     0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT    7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK     0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT    6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK     0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT    5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK     0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT    4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK     0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT    3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK     0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT    2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK        0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT       1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK        0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT       0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: USB1_OHCI_1_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: USB1_OHCI_0_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: USB1_EHCI_1_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: USB1_EHCI_0_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: USB1_BRIDGE_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: USB0_OHCI_1_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: USB0_OHCI_0_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: USB0_EHCI_1_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: USB0_EHCI_0_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: USB0_BRIDGE_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART2_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_MASK  0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART1_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_MASK  0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART0_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_MASK  0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK    0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT   18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK    0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT   17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK     0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT    16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MC_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MC_CPU_INTR_MASK     0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MC_CPU_INTR_SHIFT    15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MC_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK   0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT  13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK    0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT   11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_MASK    0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_SHIFT   9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK     0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT    8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK    0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT   7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK        0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT       6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SVD0_0_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_MASK     0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_SHIFT    5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDIO1_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDIO1_0_CPU_INTR_MASK    0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDIO1_0_CPU_INTR_SHIFT   3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDIO1_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDIO0_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDIO0_0_CPU_INTR_MASK    0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDIO0_0_CPU_INTR_SHIFT   2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SATA_GRB_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SATA_AHCI_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: reserved0 [31:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved0_MASK           0xffffff00
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved0_SHIFT          8
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK    0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT   6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK    0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT   5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK    0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT   2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK     0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT    1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK        0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT       0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: RFM_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_RFM_CPU_INTR_MASK   0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_RFM_CPU_INTR_SHIFT  31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_RFM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: RAAGA_FW_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: RAAGA_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: NMI_PIN_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: MOCA_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MOCA_CPU_INTR_MASK  0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MOCA_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MOCA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: MEMC0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MEMC0_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MEMC0_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MEMC0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: IPI1_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI1_CPU_INTR_MASK  0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI1_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: IPI0_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI0_CPU_INTR_MASK  0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI0_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK   0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT  22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_RX_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_RX_0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_RX_0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GFX_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: DVP_HR_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_DVP_HR_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_DVP_HR_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_DVP_HR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: USB1_OHCI_1_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: USB1_OHCI_0_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: USB1_EHCI_1_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: USB1_EHCI_0_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: USB1_BRIDGE_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: USB0_OHCI_1_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: USB0_OHCI_0_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: USB0_EHCI_1_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: USB0_EHCI_0_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: USB0_BRIDGE_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART2_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART1_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART0_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MC_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MC_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MC_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SVD0_0_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDIO1_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDIO1_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDIO1_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDIO1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDIO0_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SATA_GRB_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SATA_AHCI_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: reserved0 [31:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved0_MASK      0xffffff00
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved0_SHIFT     8
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: RFM_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_RFM_CPU_INTR_MASK      0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_RFM_CPU_INTR_SHIFT     31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_RFM_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: RAAGA_FW_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: RAAGA_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_RAAGA_CPU_INTR_MASK    0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_RAAGA_CPU_INTR_SHIFT   29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: NMI_PIN_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_NMI_PIN_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: MOCA_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MOCA_CPU_INTR_MASK     0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MOCA_CPU_INTR_SHIFT    27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MOCA_CPU_INTR_DEFAULT  0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: MEMC0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MEMC0_CPU_INTR_MASK    0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MEMC0_CPU_INTR_SHIFT   26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MEMC0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: IPI1_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI1_CPU_INTR_MASK     0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI1_CPU_INTR_SHIFT    25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI1_CPU_INTR_DEFAULT  0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: IPI0_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI0_CPU_INTR_MASK     0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI0_CPU_INTR_SHIFT    24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI0_CPU_INTR_DEFAULT  0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK  0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK      0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT     22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK  0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HDMI_RX_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_RX_0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_RX_0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GFX_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_MASK      0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_SHIFT     19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_1_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_1_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: DVP_HR_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_DVP_HR_CPU_INTR_MASK   0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_DVP_HR_CPU_INTR_SHIFT  8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_DVP_HR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK      0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT     1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK      0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT     0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: USB1_OHCI_1_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB1_OHCI_1_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB1_OHCI_1_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: USB1_OHCI_0_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB1_OHCI_0_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB1_OHCI_0_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: USB1_EHCI_1_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB1_EHCI_1_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB1_EHCI_1_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: USB1_EHCI_0_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB1_EHCI_0_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB1_EHCI_0_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: USB1_BRIDGE_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB1_BRIDGE_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB1_BRIDGE_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: USB0_OHCI_1_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB0_OHCI_1_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB0_OHCI_1_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: USB0_OHCI_0_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB0_OHCI_0_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB0_OHCI_0_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: USB0_EHCI_1_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB0_EHCI_1_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB0_EHCI_1_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: USB0_EHCI_0_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB0_EHCI_0_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB0_EHCI_0_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: USB0_BRIDGE_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB0_BRIDGE_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB0_BRIDGE_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART2_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART1_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART0_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK  0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK  0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK   0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT  16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MC_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MC_CPU_INTR_MASK   0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MC_CPU_INTR_SHIFT  15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK  0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_MASK  0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK   0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT  8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK  0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK      0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT     6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SVD0_0_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDIO1_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDIO1_0_CPU_INTR_MASK  0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDIO1_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDIO1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDIO0_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDIO0_0_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SATA_GRB_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SATA_AHCI_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: reserved0 [31:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved0_MASK         0xffffff00
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved0_SHIFT        8
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK  0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK  0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK      0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT     0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: RFM_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_RFM_CPU_INTR_MASK    0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_RFM_CPU_INTR_SHIFT   31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_RFM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: RAAGA_FW_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: RAAGA_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_RAAGA_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: NMI_PIN_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: MOCA_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MOCA_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MOCA_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MOCA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: MEMC0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MEMC0_CPU_INTR_MASK  0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MEMC0_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MEMC0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: IPI1_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI1_CPU_INTR_MASK   0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI1_CPU_INTR_SHIFT  25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: IPI0_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI0_CPU_INTR_MASK   0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI0_CPU_INTR_SHIFT  24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK    0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT   22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_RX_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_RX_0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_RX_0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GFX_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_MASK    0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_SHIFT   19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: DVP_HR_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_DVP_HR_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_DVP_HR_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_DVP_HR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: USB1_OHCI_1_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: USB1_OHCI_0_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: USB1_EHCI_1_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: USB1_EHCI_0_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: USB1_BRIDGE_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: USB0_OHCI_1_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: USB0_OHCI_0_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: USB0_EHCI_1_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: USB0_EHCI_0_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: USB0_BRIDGE_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART2_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART1_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART0_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MC_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MC_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MC_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK    0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT   6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SVD0_0_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDIO1_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDIO1_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDIO1_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDIO1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDIO0_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_GRB_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_AHCI_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: reserved0 [31:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved0_MASK       0xffffff00
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved0_SHIFT      8
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 0x00000001
+
+#endif /* #ifndef BCHP_HIF_CPU_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_hif_cpu_tp1_intr1.h b/include/linux/brcmstb/7429b0/bchp_hif_cpu_tp1_intr1.h
new file mode 100644
index 0000000..210afbf
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_hif_cpu_tp1_intr1.h
@@ -0,0 +1,1552 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:14 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_TP1_INTR1_H__
+#define BCHP_HIF_CPU_TP1_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_TP1_INTR1 - HIF CPU Thread Processor 1 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS    0x00411600 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS    0x00411604 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS    0x00411608 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS 0x0041160c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS 0x00411610 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS 0x00411614 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET  0x00411618 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET  0x0041161c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET  0x00411620 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR 0x00411624 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR 0x00411628 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR 0x0041162c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: RFM_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_RFM_CPU_INTR_MASK    0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_RFM_CPU_INTR_SHIFT   31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_RFM_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: RAAGA_FW_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_RAAGA_FW_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_RAAGA_FW_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: RAAGA_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_RAAGA_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_RAAGA_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_RAAGA_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: NMI_PIN_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_NMI_PIN_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_NMI_PIN_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: MOCA_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MOCA_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MOCA_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MOCA_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: MEMC0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC0_CPU_INTR_MASK  0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC0_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: IPI1_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI1_CPU_INTR_MASK   0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI1_CPU_INTR_SHIFT  25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: IPI0_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI0_CPU_INTR_MASK   0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI0_CPU_INTR_SHIFT  24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK    0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT   22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HDMI_RX_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_RX_0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_RX_0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GFX_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_MASK    0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_SHIFT   19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_1_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_1_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: DVP_HR_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_DVP_HR_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_DVP_HR_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_DVP_HR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: USB1_OHCI_1_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: USB1_OHCI_0_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: USB1_EHCI_1_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: USB1_EHCI_0_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: USB1_BRIDGE_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: USB0_OHCI_1_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: USB0_OHCI_0_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: USB0_EHCI_1_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: USB0_EHCI_0_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: USB0_BRIDGE_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_UART2_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_UART1_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_UART0_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MC_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MC_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MC_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_AUX_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK    0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT   6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SVD0_0_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDIO1_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO1_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO1_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO1_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDIO0_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO0_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO0_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SATA_GRB_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SATA_AHCI_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: reserved0 [31:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_reserved0_MASK       0xffffff00
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_reserved0_SHIFT      8
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: RFM_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_RFM_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_RFM_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_RFM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: RAAGA_FW_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: RAAGA_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: NMI_PIN_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: MOCA_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MOCA_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MOCA_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MOCA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: MEMC0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC0_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC0_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: IPI1_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI1_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI1_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: IPI0_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI0_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI0_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_RX_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_RX_0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_RX_0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GFX_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: DVP_HR_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_DVP_HR_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_DVP_HR_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_DVP_HR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: USB1_OHCI_1_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: USB1_OHCI_0_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: USB1_EHCI_1_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: USB1_EHCI_0_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: USB1_BRIDGE_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: USB0_OHCI_1_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: USB0_OHCI_0_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: USB0_EHCI_1_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: USB0_EHCI_0_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: USB0_BRIDGE_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART2_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART1_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART0_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MC_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MC_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MC_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SVD0_0_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDIO1_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO1_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO1_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDIO0_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SATA_GRB_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SATA_AHCI_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: reserved0 [31:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_reserved0_MASK  0xffffff00
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_reserved0_SHIFT 8
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: RFM_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_RFM_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_RFM_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_RFM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: RAAGA_FW_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: RAAGA_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_RAAGA_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_RAAGA_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: NMI_PIN_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_NMI_PIN_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: MOCA_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MOCA_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MOCA_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MOCA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: MEMC0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC0_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC0_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: IPI1_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI1_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI1_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: IPI0_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI0_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI0_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK  0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HDMI_RX_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_RX_0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_RX_0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GFX_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_MASK  0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_1_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_1_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: DVP_HR_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_DVP_HR_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_DVP_HR_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_DVP_HR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: USB1_OHCI_1_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB1_OHCI_1_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB1_OHCI_1_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: USB1_OHCI_0_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB1_OHCI_0_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB1_OHCI_0_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: USB1_EHCI_1_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB1_EHCI_1_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB1_EHCI_1_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: USB1_EHCI_0_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB1_EHCI_0_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB1_EHCI_0_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: USB1_BRIDGE_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB1_BRIDGE_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB1_BRIDGE_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: USB0_OHCI_1_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB0_OHCI_1_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB0_OHCI_1_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: USB0_OHCI_0_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB0_OHCI_0_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB0_OHCI_0_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: USB0_EHCI_1_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB0_EHCI_1_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB0_EHCI_1_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: USB0_EHCI_0_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB0_EHCI_0_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB0_EHCI_0_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: USB0_BRIDGE_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB0_BRIDGE_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB0_BRIDGE_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_UART2_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_UART1_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_UART0_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MC_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MC_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MC_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK  0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SVD0_0_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDIO1_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO1_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO1_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDIO0_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO0_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SATA_GRB_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SATA_AHCI_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: reserved0 [31:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_reserved0_MASK     0xffffff00
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_reserved0_SHIFT    8
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: RFM_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_RFM_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_RFM_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_RFM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: RAAGA_FW_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: RAAGA_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_RAAGA_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: NMI_PIN_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: MOCA_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MOCA_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MOCA_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MOCA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: MEMC0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC0_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC0_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: IPI1_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI1_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI1_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: IPI0_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI0_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI0_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_RX_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_RX_0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_RX_0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GFX_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: DVP_HR_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_DVP_HR_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_DVP_HR_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_DVP_HR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: USB1_OHCI_1_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: USB1_OHCI_0_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: USB1_EHCI_1_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: USB1_EHCI_0_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: USB1_BRIDGE_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: USB0_OHCI_1_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: USB0_OHCI_0_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: USB0_EHCI_1_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: USB0_EHCI_0_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: USB0_BRIDGE_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART2_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART1_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART0_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MC_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MC_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MC_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SVD0_0_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDIO1_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO1_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO1_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDIO0_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_GRB_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_AHCI_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: reserved0 [31:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_reserved0_MASK   0xffffff00
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_reserved0_SHIFT  8
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 0x00000001
+
+#endif /* #ifndef BCHP_HIF_CPU_TP1_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_hif_intr2.h b/include/linux/brcmstb/7429b0/bchp_hif_intr2.h
new file mode 100644
index 0000000..d397b5b
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_hif_intr2.h
@@ -0,0 +1,1152 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:14 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_INTR2_H__
+#define BCHP_HIF_INTR2_H__
+
+/***************************************************************************
+ *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_INTR2_CPU_STATUS                0x00411000 /* CPU interrupt Status Register */
+#define BCHP_HIF_INTR2_CPU_SET                   0x00411004 /* CPU interrupt Set Register */
+#define BCHP_HIF_INTR2_CPU_CLEAR                 0x00411008 /* CPU interrupt Clear Register */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS           0x0041100c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_CPU_MASK_SET              0x00411010 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR            0x00411014 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_INTR2_PCI_STATUS                0x00411018 /* PCI interrupt Status Register */
+#define BCHP_HIF_INTR2_PCI_SET                   0x0041101c /* PCI interrupt Set Register */
+#define BCHP_HIF_INTR2_PCI_CLEAR                 0x00411020 /* PCI interrupt Clear Register */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS           0x00411024 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_PCI_MASK_SET              0x00411028 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR            0x0041102c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_STATUS :: reserved0 [31:30] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK                   0xc0000000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT                  30
+
+/* HIF_INTR2 :: CPU_STATUS :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EDU_DONE_INTR_MASK               0x20000000
+#define BCHP_HIF_INTR2_CPU_STATUS_EDU_DONE_INTR_SHIFT              29
+#define BCHP_HIF_INTR2_CPU_STATUS_EDU_DONE_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EDU_ERR_INTR_MASK                0x10000000
+#define BCHP_HIF_INTR2_CPU_STATUS_EDU_ERR_INTR_SHIFT               28
+#define BCHP_HIF_INTR2_CPU_STATUS_EDU_ERR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_MASK          0x00080000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_SHIFT         19
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_MASK          0x00008000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_SHIFT         15
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK                   0x00007ffe
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_SET :: reserved0 [31:30] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK                      0xc0000000
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT                     30
+
+/* HIF_INTR2 :: CPU_SET :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_CPU_SET_EDU_DONE_INTR_MASK                  0x20000000
+#define BCHP_HIF_INTR2_CPU_SET_EDU_DONE_INTR_SHIFT                 29
+#define BCHP_HIF_INTR2_CPU_SET_EDU_DONE_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_CPU_SET_EDU_ERR_INTR_MASK                   0x10000000
+#define BCHP_HIF_INTR2_CPU_SET_EDU_ERR_INTR_SHIFT                  28
+#define BCHP_HIF_INTR2_CPU_SET_EDU_ERR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_MASK             0x00080000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_SHIFT            19
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_MASK             0x00008000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_SHIFT            15
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK                      0x00007ffe
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: CPU_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [31:30] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK                    0xc0000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT                   30
+
+/* HIF_INTR2 :: CPU_CLEAR :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EDU_DONE_INTR_MASK                0x20000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EDU_DONE_INTR_SHIFT               29
+#define BCHP_HIF_INTR2_CPU_CLEAR_EDU_DONE_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EDU_ERR_INTR_MASK                 0x10000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EDU_ERR_INTR_SHIFT                28
+#define BCHP_HIF_INTR2_CPU_CLEAR_EDU_ERR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_MASK           0x00008000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_SHIFT          15
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK                    0x00007ffe
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:30] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK              0xc0000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT             30
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EDU_DONE_INTR_MASK          0x20000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EDU_DONE_INTR_SHIFT         29
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EDU_DONE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EDU_ERR_INTR_MASK           0x10000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EDU_ERR_INTR_SHIFT          28
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EDU_ERR_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_MASK     0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_SHIFT    19
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_MASK     0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_SHIFT    15
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK              0x00007ffe
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [31:30] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK                 0xc0000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT                30
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EDU_DONE_INTR_MASK             0x20000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EDU_DONE_INTR_SHIFT            29
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EDU_DONE_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EDU_ERR_INTR_MASK              0x10000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EDU_ERR_INTR_SHIFT             28
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EDU_ERR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_MASK        0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_SHIFT       19
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_MASK        0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_SHIFT       15
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK                 0x00007ffe
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:30] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK               0xc0000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT              30
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EDU_DONE_INTR_MASK           0x20000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EDU_DONE_INTR_SHIFT          29
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EDU_DONE_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EDU_ERR_INTR_MASK            0x10000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EDU_ERR_INTR_SHIFT           28
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EDU_ERR_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_MASK      0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_SHIFT     15
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK               0x00007ffe
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_STATUS :: reserved0 [31:30] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK                   0xc0000000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT                  30
+
+/* HIF_INTR2 :: PCI_STATUS :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EDU_DONE_INTR_MASK               0x20000000
+#define BCHP_HIF_INTR2_PCI_STATUS_EDU_DONE_INTR_SHIFT              29
+#define BCHP_HIF_INTR2_PCI_STATUS_EDU_DONE_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EDU_ERR_INTR_MASK                0x10000000
+#define BCHP_HIF_INTR2_PCI_STATUS_EDU_ERR_INTR_SHIFT               28
+#define BCHP_HIF_INTR2_PCI_STATUS_EDU_ERR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_MASK          0x00080000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_SHIFT         19
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_MASK          0x00008000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_SHIFT         15
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK                   0x00007ffe
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_SET :: reserved0 [31:30] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK                      0xc0000000
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT                     30
+
+/* HIF_INTR2 :: PCI_SET :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_PCI_SET_EDU_DONE_INTR_MASK                  0x20000000
+#define BCHP_HIF_INTR2_PCI_SET_EDU_DONE_INTR_SHIFT                 29
+#define BCHP_HIF_INTR2_PCI_SET_EDU_DONE_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_PCI_SET_EDU_ERR_INTR_MASK                   0x10000000
+#define BCHP_HIF_INTR2_PCI_SET_EDU_ERR_INTR_SHIFT                  28
+#define BCHP_HIF_INTR2_PCI_SET_EDU_ERR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_MASK             0x00080000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_SHIFT            19
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_MASK             0x00008000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_SHIFT            15
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK                      0x00007ffe
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: PCI_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [31:30] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK                    0xc0000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT                   30
+
+/* HIF_INTR2 :: PCI_CLEAR :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EDU_DONE_INTR_MASK                0x20000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EDU_DONE_INTR_SHIFT               29
+#define BCHP_HIF_INTR2_PCI_CLEAR_EDU_DONE_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EDU_ERR_INTR_MASK                 0x10000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EDU_ERR_INTR_SHIFT                28
+#define BCHP_HIF_INTR2_PCI_CLEAR_EDU_ERR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_MASK           0x00008000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_SHIFT          15
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK                    0x00007ffe
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:30] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK              0xc0000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT             30
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EDU_DONE_INTR_MASK          0x20000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EDU_DONE_INTR_SHIFT         29
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EDU_DONE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EDU_ERR_INTR_MASK           0x10000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EDU_ERR_INTR_SHIFT          28
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EDU_ERR_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_MASK     0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_SHIFT    19
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_MASK     0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_SHIFT    15
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK              0x00007ffe
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [31:30] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK                 0xc0000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT                30
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EDU_DONE_INTR_MASK             0x20000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EDU_DONE_INTR_SHIFT            29
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EDU_DONE_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EDU_ERR_INTR_MASK              0x10000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EDU_ERR_INTR_SHIFT             28
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EDU_ERR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_MASK        0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_SHIFT       19
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_MASK        0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_SHIFT       15
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK                 0x00007ffe
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:30] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK               0xc0000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT              30
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EDU_DONE_INTR_MASK           0x20000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EDU_DONE_INTR_SHIFT          29
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EDU_DONE_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EDU_ERR_INTR_MASK            0x10000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EDU_ERR_INTR_SHIFT           28
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EDU_ERR_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_MASK      0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_SHIFT     15
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK               0x00007ffe
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  0x00000001
+
+#endif /* #ifndef BCHP_HIF_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_hif_mspi.h b/include/linux/brcmstb/7429b0/bchp_hif_mspi.h
new file mode 100644
index 0000000..2f54ada
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_hif_mspi.h
@@ -0,0 +1,1211 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:15 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_MSPI_H__
+#define BCHP_HIF_MSPI_H__
+
+/***************************************************************************
+ *HIF_MSPI - Public MSPI Registers
+ ***************************************************************************/
+#define BCHP_HIF_MSPI_SPCR0_LSB                  0x00413200 /* SPCR0_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR0_MSB                  0x00413204 /* SPCR0_MSB Register */
+#define BCHP_HIF_MSPI_SPCR1_LSB                  0x00413208 /* SPCR1_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR1_MSB                  0x0041320c /* SPCR1_MSB REGISTER */
+#define BCHP_HIF_MSPI_NEWQP                      0x00413210 /* NEWQP REGISTER */
+#define BCHP_HIF_MSPI_ENDQP                      0x00413214 /* ENDQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR2                      0x00413218 /* SPCR2 REGISTER */
+#define BCHP_HIF_MSPI_MSPI_STATUS                0x00413220 /* MSPI STATUS REGISTER */
+#define BCHP_HIF_MSPI_CPTQP                      0x00413224 /* CPTQP REGISTER */
+#define BCHP_HIF_MSPI_TXRAM00                    0x00413240 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM01                    0x00413244 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM02                    0x00413248 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM03                    0x0041324c /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM04                    0x00413250 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM05                    0x00413254 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM06                    0x00413258 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM07                    0x0041325c /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM08                    0x00413260 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM09                    0x00413264 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM10                    0x00413268 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM11                    0x0041326c /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM12                    0x00413270 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM13                    0x00413274 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM14                    0x00413278 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM15                    0x0041327c /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM16                    0x00413280 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM17                    0x00413284 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM18                    0x00413288 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM19                    0x0041328c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM20                    0x00413290 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM21                    0x00413294 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM22                    0x00413298 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM23                    0x0041329c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM24                    0x004132a0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM25                    0x004132a4 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM26                    0x004132a8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM27                    0x004132ac /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM28                    0x004132b0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM29                    0x004132b4 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM30                    0x004132b8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_TXRAM31                    0x004132bc /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM00                    0x004132c0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM01                    0x004132c4 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM02                    0x004132c8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM03                    0x004132cc /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM04                    0x004132d0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM05                    0x004132d4 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM06                    0x004132d8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM07                    0x004132dc /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM08                    0x004132e0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM09                    0x004132e4 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM10                    0x004132e8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM11                    0x004132ec /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM12                    0x004132f0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM13                    0x004132f4 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM14                    0x004132f8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM15                    0x004132fc /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM16                    0x00413300 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM17                    0x00413304 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM18                    0x00413308 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM19                    0x0041330c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM20                    0x00413310 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM21                    0x00413314 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM22                    0x00413318 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM23                    0x0041331c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM24                    0x00413320 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM25                    0x00413324 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM26                    0x00413328 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM27                    0x0041332c /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM28                    0x00413330 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM29                    0x00413334 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM30                    0x00413338 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM31                    0x0041333c /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_CDRAM00                    0x00413340 /* 8-bit command (queue pointer = 0) */
+#define BCHP_HIF_MSPI_CDRAM01                    0x00413344 /* 8-bit command (queue pointer = 1) */
+#define BCHP_HIF_MSPI_CDRAM02                    0x00413348 /* 8-bit command (queue pointer = 2) */
+#define BCHP_HIF_MSPI_CDRAM03                    0x0041334c /* 8-bit command (queue pointer = 3) */
+#define BCHP_HIF_MSPI_CDRAM04                    0x00413350 /* 8-bit command (queue pointer = 4) */
+#define BCHP_HIF_MSPI_CDRAM05                    0x00413354 /* 8-bit command (queue pointer = 5) */
+#define BCHP_HIF_MSPI_CDRAM06                    0x00413358 /* 8-bit command (queue pointer = 6) */
+#define BCHP_HIF_MSPI_CDRAM07                    0x0041335c /* 8-bit command (queue pointer = 7) */
+#define BCHP_HIF_MSPI_CDRAM08                    0x00413360 /* 8-bit command (queue pointer = 8) */
+#define BCHP_HIF_MSPI_CDRAM09                    0x00413364 /* 8-bit command (queue pointer = 9) */
+#define BCHP_HIF_MSPI_CDRAM10                    0x00413368 /* 8-bit command (queue pointer = a) */
+#define BCHP_HIF_MSPI_CDRAM11                    0x0041336c /* 8-bit command (queue pointer = b) */
+#define BCHP_HIF_MSPI_CDRAM12                    0x00413370 /* 8-bit command (queue pointer = c) */
+#define BCHP_HIF_MSPI_CDRAM13                    0x00413374 /* 8-bit command (queue pointer = d) */
+#define BCHP_HIF_MSPI_CDRAM14                    0x00413378 /* 8-bit command (queue pointer = e) */
+#define BCHP_HIF_MSPI_CDRAM15                    0x0041337c /* 8-bit command (queue pointer = f) */
+#define BCHP_HIF_MSPI_WRITE_LOCK                 0x00413380 /* Control bit to lock group of write commands */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN          0x00413384 /* Debug bit to mask the generation of flush signals from Mspi */
+
+/***************************************************************************
+ *SPCR0_LSB - SPCR0_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK                          0x000000ff
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR0_MSB - SPCR0_MSB Register
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_MSB :: MSTR [07:07] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_MASK                          0x00000080
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_SHIFT                         7
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_DEFAULT                       0x00000001
+
+/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [06:06] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK               0x00000040
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT              6
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT            0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: BitS [05:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_MASK                          0x0000003c
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_SHIFT                         2
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_DEFAULT                       0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK                          0x00000002
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT                         1
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT                       0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK                          0x00000001
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR1_LSB - SPCR1_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT                          0
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *SPCR1_MSB - SPCR1_MSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK                        0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT                       0
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *NEWQP - NEWQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: NEWQP :: newqp [03:00] */
+#define BCHP_HIF_MSPI_NEWQP_newqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT                            0
+#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *ENDQP - ENDQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: ENDQP :: endqp [03:00] */
+#define BCHP_HIF_MSPI_ENDQP_endqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT                            0
+#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *SPCR2 - SPCR2 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK                         0xffffff00
+#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT                        8
+
+/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK                    0x00000080
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT                   7
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT                 0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spe [06:06] */
+#define BCHP_HIF_MSPI_SPCR2_spe_MASK                               0x00000040
+#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT                              6
+#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
+#define BCHP_HIF_MSPI_SPCR2_spifie_MASK                            0x00000020
+#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT                           5
+#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT                         0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wren [04:04] */
+#define BCHP_HIF_MSPI_SPCR2_wren_MASK                              0x00000010
+#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT                             4
+#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
+#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK                              0x00000008
+#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT                             3
+#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
+#define BCHP_HIF_MSPI_SPCR2_loopq_MASK                             0x00000004
+#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT                            2
+#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT                          0x00000000
+
+/* HIF_MSPI :: SPCR2 :: hie [01:01] */
+#define BCHP_HIF_MSPI_SPCR2_hie_MASK                               0x00000002
+#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT                              1
+#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: halt [00:00] */
+#define BCHP_HIF_MSPI_SPCR2_halt_MASK                              0x00000001
+#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT                             0
+#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *MSPI_STATUS - MSPI STATUS REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK                   0xfffffffc
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT                  2
+
+/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK                       0x00000002
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT                      1
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT                    0x00000000
+
+/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK                        0x00000001
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT                       0
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *CPTQP - CPTQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
+#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT                            0
+#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *TXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM00_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM01_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM02_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM03_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM04_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM05_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM06_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM07_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM08_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM09_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM10_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM11_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM12_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM13_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM14_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM15_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM16_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM17_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM18_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM19_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM20_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM21_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM22_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM23_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM24_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM25_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM26_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM27_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM28_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM29_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM30_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM31_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM00 - 8-bit command (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM00 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM01 - 8-bit command (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM01 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM02 - 8-bit command (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM02 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM03 - 8-bit command (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM03 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM04 - 8-bit command (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM04 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM05 - 8-bit command (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM05 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM06 - 8-bit command (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM06 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM07 - 8-bit command (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM07 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM08 - 8-bit command (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM08 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM09 - 8-bit command (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM09 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM10 - 8-bit command (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM10 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM11 - 8-bit command (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM11 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM12 - 8-bit command (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM12 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM13 - 8-bit command (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM13 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM14 - 8-bit command (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM14 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM15 - 8-bit command (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM15 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT                          0
+
+/***************************************************************************
+ *WRITE_LOCK - Control bit to lock group of write commands
+ ***************************************************************************/
+/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK                    0xfffffffe
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT                   1
+
+/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK                    0x00000001
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT                   0
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
+ ***************************************************************************/
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK             0xfffffffe
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT            1
+
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK       0x00000001
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT      0
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT    0x00000000
+
+#endif /* #ifndef BCHP_HIF_MSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/7429b0/bchp_hif_spi_intr2.h
new file mode 100644
index 0000000..10e4b40
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_hif_spi_intr2.h
@@ -0,0 +1,564 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:13 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_SPI_INTR2_H__
+#define BCHP_HIF_SPI_INTR2_H__
+
+/***************************************************************************
+ *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
+ ***************************************************************************/
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS            0x00411d00 /* CPU interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_SET               0x00411d04 /* CPU interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR             0x00411d08 /* CPU interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS       0x00411d0c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET          0x00411d10 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR        0x00411d14 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS            0x00411d18 /* PCI interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_SET               0x00411d1c /* PCI interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR             0x00411d20 /* PCI interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS       0x00411d24 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET          0x00411d28 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR        0x00411d2c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_hif_top_ctrl.h b/include/linux/brcmstb/7429b0/bchp_hif_top_ctrl.h
new file mode 100644
index 0000000..e56a326
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_hif_top_ctrl.h
@@ -0,0 +1,575 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:14 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_TOP_CTRL_H__
+#define BCHP_HIF_TOP_CTRL_H__
+
+/***************************************************************************
+ *HIF_TOP_CTRL - HIF Top Control Registers
+ ***************************************************************************/
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL          0x00412400 /* External IRQ Active Level Control Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0               0x00412404 /* HIF Power Management Control0 Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1               0x00412408 /* HIF Power Management Control1 Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2               0x0041240c /* HIF Power Management Control Register:used to control SDIO_0 (CARD) */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3               0x00412418 /* HIF Power Management Control Register:used to control SDIO_1 (EMMC) */
+#define BCHP_HIF_TOP_CTRL_SCRATCH                0x0041241c /* HIF Scratch Register */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE             0x00412420 /* HIF Decoded Flash Type */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL            0x00412424 /* SPI test port select register */
+#define BCHP_HIF_TOP_CTRL_EMMC_PIN_CTRL          0x00412428 /* EMMC Pin Control register */
+#define BCHP_HIF_TOP_CTRL_SDIO_TIMING_CTRL       0x0041242c /* SDIO IO timing Control register */
+
+/***************************************************************************
+ *EXT_IRQ_LEVEL - External IRQ Active Level Control Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: reserved0 [31:06] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_MASK             0xffffffc0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_SHIFT            6
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_05_level [05:05] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_MASK      0x00000020
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_SHIFT     5
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_04_level [04:04] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_MASK      0x00000010
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_03_level [03:03] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_MASK      0x00000008
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_SHIFT     3
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_02_level [02:02] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_MASK      0x00000004
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_SHIFT     2
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_01_level [01:01] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_MASK      0x00000002
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_SHIFT     1
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_00_level [00:00] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_MASK      0x00000001
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_SHIFT     0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_HIGH      1
+
+/***************************************************************************
+ *PM_CTRL0 - HIF Power Management Control0 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_PM_IN_DRIVE_INACTIVE [31:30] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_MASK   0xc0000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_SHIFT  30
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_IN_DRIVE_INACTIVE [29:28] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x30000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 28
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_CTRL_PM_IN_DRIVE_INACTIVE [27:26] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_MASK 0x0c000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_SHIFT 26
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_NOT_USED 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_DATA_PM_OUT_CTRL [25:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_MASK       0x03000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_SHIFT      24
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_ADDR_PM_OUT_CTRL [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_MASK       0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_SHIFT      22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_CTRL_PM_OUT_CTRL [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_MASK       0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_SHIFT      20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_OUT_CTRL [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_MASK      0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_SHIFT     18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_CTRL_PM_OUT_CTRL [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_MASK      0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_SHIFT     16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS7 [15:14] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_MASK            0x0000c000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_SHIFT           14
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS6 [13:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_MASK            0x00003000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_SHIFT           12
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS5 [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_MASK            0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_SHIFT           10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS4 [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_MASK            0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_SHIFT           8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS3 [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_MASK            0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_SHIFT           6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS2 [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_MASK            0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_SHIFT           4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS1 [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_MASK            0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_SHIFT           2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS0 [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_MASK            0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_SHIFT           0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_Tristate        3
+
+/***************************************************************************
+ *PM_CTRL1 - HIF Power Management Control1 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL1 :: reserved0 [31:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_MASK                  0xfffff000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_PM_IN_DRIVE_INACTIVE [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_WPB_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_MASK        0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_SHIFT       8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_DEFAULT     0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_Tristate    3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_HOLDB_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_MASK      0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_SHIFT     6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MISO_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_MASK       0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_SHIFT      4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MOSI_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_MASK        0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_SHIFT       0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_DEFAULT     0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_Tristate    3
+
+/***************************************************************************
+ *PM_CTRL2 - HIF Power Management Control Register:used to control SDIO_0 (CARD)
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved0 [31:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_MASK                  0xff000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_SHIFT                 24
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_MASK 0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_SHIFT 22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_MASK 0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_SHIFT 20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_IN_DRIVE_INACTIVE [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_IN_DRIVE_INACTIVE [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_MASK 0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_SHIFT 16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved1 [15:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_MASK                  0x0000f000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_VOLTAGE_PM_OUT_CTRL [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_LOW    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_HIGH   2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_POWER_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_MASK     0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_SHIFT    8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_DEFAULT  0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_LOW      1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_HIGH     2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_LED_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_MASK       0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_SHIFT      6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_MASK      0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_MASK       0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_SHIFT      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_Tristate   3
+
+/***************************************************************************
+ *PM_CTRL3 - HIF Power Management Control Register:used to control SDIO_1 (EMMC)
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL3 :: reserved0 [31:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved0_MASK                  0xff000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved0_SHIFT                 24
+
+/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_MASK 0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_SHIFT 22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_MASK 0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_SHIFT 20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_DATA_PM_IN_DRIVE_INACTIVE [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_CMD_PM_IN_DRIVE_INACTIVE [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_MASK 0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_SHIFT 16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL3 :: reserved1 [15:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved1_MASK                  0x0000fc00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved1_SHIFT                 10
+
+/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_POWER_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_MASK     0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_SHIFT    8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_DEFAULT  0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_LOW      1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_HIGH     2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_POWER_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_LED_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_MASK       0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_SHIFT      6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_LED_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_DATA_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_MASK      0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_CMD_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_MASK       0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_SHIFT      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_Tristate   3
+
+/***************************************************************************
+ *SCRATCH - HIF Scratch Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SCRATCH :: SCRATCH_BITS [31:00] */
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BITS_MASK                0xffffffff
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BITS_SHIFT               0
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BITS_DEFAULT             0x00000000
+
+/***************************************************************************
+ *FLASH_TYPE - HIF Decoded Flash Type
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: FLASH_TYPE :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_MASK                0xfffffff8
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_SHIFT               3
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: InvalidStrap [02:02] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_MASK             0x00000004
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_SHIFT            2
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_DEFAULT          0x00000000
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: FLASH_TYPE [01:00] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_MASK               0x00000003
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SHIFT              0
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_ParallelNOR        0
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_Nand               1
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SerialNOR          2
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_eMMC               3
+
+/***************************************************************************
+ *SPI_DBG_SEL - SPI test port select register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_MASK               0xfffffff8
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_SHIFT              3
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: DISABLE_MSPI_FLUSH [02:02] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_MASK      0x00000004
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_SHIFT     2
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_DEFAULT   0x00000000
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SPI_RBUS_TIMER_EN [01:01] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_MASK       0x00000002
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_SHIFT      1
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_DEFAULT    0x00000000
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SDIO_TP_SEL [00:00] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SDIO_TP_SEL_MASK             0x00000001
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SDIO_TP_SEL_SHIFT            0
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SDIO_TP_SEL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *EMMC_PIN_CTRL - EMMC Pin Control register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: EMMC_PIN_CTRL :: reserved0 [31:02] */
+#define BCHP_HIF_TOP_CTRL_EMMC_PIN_CTRL_reserved0_MASK             0xfffffffc
+#define BCHP_HIF_TOP_CTRL_EMMC_PIN_CTRL_reserved0_SHIFT            2
+
+/* HIF_TOP_CTRL :: EMMC_PIN_CTRL :: EMMC_PIN_SEL [01:00] */
+#define BCHP_HIF_TOP_CTRL_EMMC_PIN_CTRL_EMMC_PIN_SEL_MASK          0x00000003
+#define BCHP_HIF_TOP_CTRL_EMMC_PIN_CTRL_EMMC_PIN_SEL_SHIFT         0
+#define BCHP_HIF_TOP_CTRL_EMMC_PIN_CTRL_EMMC_PIN_SEL_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SDIO_TIMING_CTRL - SDIO IO timing Control register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SDIO_TIMING_CTRL :: reserved0 [31:04] */
+#define BCHP_HIF_TOP_CTRL_SDIO_TIMING_CTRL_reserved0_MASK          0xfffffff0
+#define BCHP_HIF_TOP_CTRL_SDIO_TIMING_CTRL_reserved0_SHIFT         4
+
+/* HIF_TOP_CTRL :: SDIO_TIMING_CTRL :: SDIO1_TIMING_SEL [03:02] */
+#define BCHP_HIF_TOP_CTRL_SDIO_TIMING_CTRL_SDIO1_TIMING_SEL_MASK   0x0000000c
+#define BCHP_HIF_TOP_CTRL_SDIO_TIMING_CTRL_SDIO1_TIMING_SEL_SHIFT  2
+#define BCHP_HIF_TOP_CTRL_SDIO_TIMING_CTRL_SDIO1_TIMING_SEL_DEFAULT 0x00000000
+
+/* HIF_TOP_CTRL :: SDIO_TIMING_CTRL :: SDIO0_TIMING_SEL [01:00] */
+#define BCHP_HIF_TOP_CTRL_SDIO_TIMING_CTRL_SDIO0_TIMING_SEL_MASK   0x00000003
+#define BCHP_HIF_TOP_CTRL_SDIO_TIMING_CTRL_SDIO0_TIMING_SEL_SHIFT  0
+#define BCHP_HIF_TOP_CTRL_SDIO_TIMING_CTRL_SDIO0_TIMING_SEL_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_HIF_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_irq0.h b/include/linux/brcmstb/7429b0/bchp_irq0.h
new file mode 100644
index 0000000..9cbfa1d
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_irq0.h
@@ -0,0 +1,204 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:15 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ0_H__
+#define BCHP_IRQ0_H__
+
+/***************************************************************************
+ *IRQ0 - Level 2 CPU Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ0_IRQEN                          0x00406680 /* Interrupt Enable */
+#define BCHP_IRQ0_IRQSTAT                        0x00406684 /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ0 :: IRQEN :: reserved0 [31:29] */
+#define BCHP_IRQ0_IRQEN_reserved0_MASK                             0xe0000000
+#define BCHP_IRQ0_IRQEN_reserved0_SHIFT                            29
+
+/* IRQ0 :: IRQEN :: iice_irqen [28:28] */
+#define BCHP_IRQ0_IRQEN_iice_irqen_MASK                            0x10000000
+#define BCHP_IRQ0_IRQEN_iice_irqen_SHIFT                           28
+#define BCHP_IRQ0_IRQEN_iice_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: iicd_irqen [27:27] */
+#define BCHP_IRQ0_IRQEN_iicd_irqen_MASK                            0x08000000
+#define BCHP_IRQ0_IRQEN_iicd_irqen_SHIFT                           27
+#define BCHP_IRQ0_IRQEN_iicd_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: reserved1 [26:19] */
+#define BCHP_IRQ0_IRQEN_reserved1_MASK                             0x07f80000
+#define BCHP_IRQ0_IRQEN_reserved1_SHIFT                            19
+
+/* IRQ0 :: IRQEN :: uartc_irqen [18:18] */
+#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK                           0x00040000
+#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT                          18
+#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uartb_irqen [17:17] */
+#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK                           0x00020000
+#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT                          17
+#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uarta_irqen [16:16] */
+#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK                           0x00010000
+#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT                          16
+#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQEN_reserved2_MASK                             0x0000fc00
+#define BCHP_IRQ0_IRQEN_reserved2_SHIFT                            10
+
+/* IRQ0 :: IRQEN :: uc_irqen [09:09] */
+#define BCHP_IRQ0_IRQEN_uc_irqen_MASK                              0x00000200
+#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT                             9
+#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQEN_reserved3_MASK                             0x00000180
+#define BCHP_IRQ0_IRQEN_reserved3_SHIFT                            7
+
+/* IRQ0 :: IRQEN :: gio_irqen [06:06] */
+#define BCHP_IRQ0_IRQEN_gio_irqen_MASK                             0x00000040
+#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT                            6
+#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQEN :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQEN_reserved4_MASK                             0x00000020
+#define BCHP_IRQ0_IRQEN_reserved4_SHIFT                            5
+
+/* IRQ0 :: IRQEN :: ua_irqen [04:04] */
+#define BCHP_IRQ0_IRQEN_ua_irqen_MASK                              0x00000010
+#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT                             4
+#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: ub_irqen [03:03] */
+#define BCHP_IRQ0_IRQEN_ub_irqen_MASK                              0x00000008
+#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT                             3
+#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: irb_irqen [02:02] */
+#define BCHP_IRQ0_IRQEN_irb_irqen_MASK                             0x00000004
+#define BCHP_IRQ0_IRQEN_irb_irqen_SHIFT                            2
+#define BCHP_IRQ0_IRQEN_irb_irqen_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQEN :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQEN_reserved5_MASK                             0x00000003
+#define BCHP_IRQ0_IRQEN_reserved5_SHIFT                            0
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ0 :: IRQSTAT :: reserved0 [31:29] */
+#define BCHP_IRQ0_IRQSTAT_reserved0_MASK                           0xe0000000
+#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT                          29
+
+/* IRQ0 :: IRQSTAT :: iiceirq [28:28] */
+#define BCHP_IRQ0_IRQSTAT_iiceirq_MASK                             0x10000000
+#define BCHP_IRQ0_IRQSTAT_iiceirq_SHIFT                            28
+#define BCHP_IRQ0_IRQSTAT_iiceirq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: iicdirq [27:27] */
+#define BCHP_IRQ0_IRQSTAT_iicdirq_MASK                             0x08000000
+#define BCHP_IRQ0_IRQSTAT_iicdirq_SHIFT                            27
+#define BCHP_IRQ0_IRQSTAT_iicdirq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved1 [26:19] */
+#define BCHP_IRQ0_IRQSTAT_reserved1_MASK                           0x07f80000
+#define BCHP_IRQ0_IRQSTAT_reserved1_SHIFT                          19
+
+/* IRQ0 :: IRQSTAT :: uartc_irq [18:18] */
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK                           0x00040000
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT                          18
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uartb_irq [17:17] */
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK                           0x00020000
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT                          17
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uarta_irq [16:16] */
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK                           0x00010000
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT                          16
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQSTAT_reserved2_MASK                           0x0000fc00
+#define BCHP_IRQ0_IRQSTAT_reserved2_SHIFT                          10
+
+/* IRQ0 :: IRQSTAT :: ucirq [09:09] */
+#define BCHP_IRQ0_IRQSTAT_ucirq_MASK                               0x00000200
+#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT                              9
+#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQSTAT_reserved3_MASK                           0x00000180
+#define BCHP_IRQ0_IRQSTAT_reserved3_SHIFT                          7
+
+/* IRQ0 :: IRQSTAT :: gioirq [06:06] */
+#define BCHP_IRQ0_IRQSTAT_gioirq_MASK                              0x00000040
+#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT                             6
+#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQSTAT_reserved4_MASK                           0x00000020
+#define BCHP_IRQ0_IRQSTAT_reserved4_SHIFT                          5
+
+/* IRQ0 :: IRQSTAT :: uairq [04:04] */
+#define BCHP_IRQ0_IRQSTAT_uairq_MASK                               0x00000010
+#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT                              4
+#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: ubirq [03:03] */
+#define BCHP_IRQ0_IRQSTAT_ubirq_MASK                               0x00000008
+#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT                              3
+#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: irbirq [02:02] */
+#define BCHP_IRQ0_IRQSTAT_irbirq_MASK                              0x00000004
+#define BCHP_IRQ0_IRQSTAT_irbirq_SHIFT                             2
+#define BCHP_IRQ0_IRQSTAT_irbirq_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQSTAT_reserved5_MASK                           0x00000003
+#define BCHP_IRQ0_IRQSTAT_reserved5_SHIFT                          0
+
+#endif /* #ifndef BCHP_IRQ0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_irq1.h b/include/linux/brcmstb/7429b0/bchp_irq1.h
new file mode 100644
index 0000000..404eb35
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_irq1.h
@@ -0,0 +1,50 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jul 12 02:40:49 2011
+ *                 MD5 Checksum         c5a82bedc88d370fb68d7daceef9c302
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ1_H__
+#define BCHP_IRQ1_H__
+
+/***************************************************************************
+ *IRQ1 - Level 2 PCI Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ1_IRQEN                          0x00406688 /* Interrupt Enable */
+#define BCHP_IRQ1_IRQSTAT                        0x0040668c /* Interrupt Status */
+
+#endif /* #ifndef BCHP_IRQ1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_mem_dma_0.h b/include/linux/brcmstb/7429b0/bchp_mem_dma_0.h
new file mode 100644
index 0000000..c51e520
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_mem_dma_0.h
@@ -0,0 +1,157 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 13 16:39:03 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7429/rdb/b0/bchp_mem_dma_0.h $
+ * 
+ * Hydra_Software_Devel/1   6/14/12 1:30p pntruong
+ * SW7429-185: Initial version.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEM_DMA_0_H__
+#define BCHP_MEM_DMA_0_H__
+
+/***************************************************************************
+ *MEM_DMA_0 - MEM_DMA_0 Registers
+ ***************************************************************************/
+#define BCHP_MEM_DMA_0_REVISION                  0x00374200 /* MEM_DMA REVISION */
+#define BCHP_MEM_DMA_0_FIRST_DESC                0x00374204 /* MEM_DMA First Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CTRL                      0x00374208 /* MEM_DMA Control Register */
+#define BCHP_MEM_DMA_0_WAKE_CTRL                 0x0037420c /* MEM_DMA Wake Control Register */
+#define BCHP_MEM_DMA_0_STATUS                    0x00374214 /* MEM_DMA Status Register */
+#define BCHP_MEM_DMA_0_CUR_DESC                  0x00374218 /* MEM_DMA Current Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CUR_BYTE                  0x0037421c /* MEM_DMA Current Byte Count Register */
+#define BCHP_MEM_DMA_0_SCRATCH                   0x00374224 /* MEM_DMA Scratch Register */
+
+/***************************************************************************
+ *REVISION - MEM_DMA REVISION
+ ***************************************************************************/
+/* MEM_DMA_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_0_REVISION_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_0_REVISION_reserved0_SHIFT                    16
+
+/* MEM_DMA_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_MASK                         0x0000ff00
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_SHIFT                        8
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_DEFAULT                      0x00000002
+
+/* MEM_DMA_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_MEM_DMA_0_REVISION_MINOR_MASK                         0x000000ff
+#define BCHP_MEM_DMA_0_REVISION_MINOR_SHIFT                        0
+#define BCHP_MEM_DMA_0_REVISION_MINOR_DEFAULT                      0x0000000a
+
+/***************************************************************************
+ *FIRST_DESC - MEM_DMA First Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: FIRST_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_MASK                        0xffffffff
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_SHIFT                       0
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *CTRL - MEM_DMA Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CTRL :: reserved0 [31:01] */
+#define BCHP_MEM_DMA_0_CTRL_reserved0_MASK                         0xfffffffe
+#define BCHP_MEM_DMA_0_CTRL_reserved0_SHIFT                        1
+
+/* MEM_DMA_0 :: CTRL :: RUN [00:00] */
+#define BCHP_MEM_DMA_0_CTRL_RUN_MASK                               0x00000001
+#define BCHP_MEM_DMA_0_CTRL_RUN_SHIFT                              0
+#define BCHP_MEM_DMA_0_CTRL_RUN_DEFAULT                            0x00000000
+
+/***************************************************************************
+ *WAKE_CTRL - MEM_DMA Wake Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: WAKE_CTRL :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_MASK                    0xfffffffc
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_SHIFT                   2
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE_MODE [01:01] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_MASK                    0x00000002
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_SHIFT                   1
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_DEFAULT                 0x00000000
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE [00:00] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MASK                         0x00000001
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_SHIFT                        0
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *STATUS - MEM_DMA Status Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: STATUS :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_MEM_DMA_0_STATUS_reserved0_SHIFT                      2
+
+/* MEM_DMA_0 :: STATUS :: DMA_STATUS [01:00] */
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_MASK                      0x00000003
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_SHIFT                     0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_DEFAULT                   0x00000000
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Idle                      0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Busy                      1
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Sleep                     2
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Reserved                  3
+
+/***************************************************************************
+ *CUR_DESC - MEM_DMA Current Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_MASK                          0xffffffff
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_SHIFT                         0
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *CUR_BYTE - MEM_DMA Current Byte Count Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_BYTE :: reserved0 [31:25] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_MASK                     0xfe000000
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_SHIFT                    25
+
+/* MEM_DMA_0 :: CUR_BYTE :: COUNT [24:00] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_MASK                         0x01ffffff
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_SHIFT                        0
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *SCRATCH - MEM_DMA Scratch Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_MASK                    0xffffffff
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_SHIFT                   0
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_DEFAULT                 0x00000000
+
+#endif /* #ifndef BCHP_MEM_DMA_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_memc_ddr23_shim_addr_cntl_0.h b/include/linux/brcmstb/7429b0/bchp_memc_ddr23_shim_addr_cntl_0.h
new file mode 100644
index 0000000..75b28bd
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_memc_ddr23_shim_addr_cntl_0.h
@@ -0,0 +1,1075 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:14 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_H__
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_H__
+
+/***************************************************************************
+ *MEMC_DDR23_SHIM_ADDR_CNTL_0 - DDR23 SHIM Control Registers 0
+ ***************************************************************************/
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG  0x003b8000 /* DDR23_SHIM Config register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID 0x003b8004 /* DDR23_SHIM Revision ID Register. */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET   0x003b8008 /* DDR soft reset register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG 0x003b8038 /* ODT Configuration register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL 0x003b8044 /* DDR PHY USE DYN VDL Control register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING 0x003b8048 /* DDR PHY Idle power saving Control register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT 0x003b804c /* DDR PHY standby exit register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL 0x003b806c /* Analog macro register bypass control */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL 0x003b8070 /* DDR PLL external clock select register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_TEST_MODE_CNTRL_REG 0x003b8074 /* DDR23_SHIM testport control register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL 0x003b807c /* DDR bypass pll mode disable register. */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL 0x003b8088 /* DDR VECTOR PLL bypass mode clock select */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL 0x003b808c /* DDR Pad control register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE 0x003b8098 /* CLK_667_ENABLE Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS 0x003b809c /* DDR23_SHIM Status Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO 0x003b8028 /* Command and Data FIFO Status Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH 0x003b802c /* Read Datapath Status Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_FLAG_BUS 0x003b8030 /* TP_OUT bus value Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC    0x003b8034 /* Miscellaneous Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RW 0x003b80a4 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RW 0x003b80a8 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RO 0x003b80ac /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RO 0x003b80b0 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL 0x003b80b4 /* FORCE_DDR3_RESET Deassert  Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS 0x003b80b8 /* SYS PLL P and N Divider Controls */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN 0x003b80bc /* SYS PLL Gain Controls */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL 0x003b80c0 /* SYS PLL Control Vector */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP 0x003b80c4 /* SSC Step Size for all 6-chan PLLs */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT 0x003b80c8 /* SSC Limit for all 6-chan PLLs */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0 0x003b80cc /* SYS PLL M Divider Controls for Channel0 */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX 0x003b80d0 /* SYS PLL M Divider Controls for Extra Unused Channels */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT 0x003b80d4 /* SYS PLL Status */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel 0x003b80d8 /* SYS PLL power-down and reference clock selection */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET 0x003b80dc /* SYS PLL Reset and post-resetb selcection */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR 0x003b80e0 /* SYS PLL control and SR selcection */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK 0x003b80e4 /* Shim to PHY gated bypass_clock selection */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG0 0x003b80e8 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG1 0x003b80ec /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG2 0x003b80f0 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG3 0x003b80f4 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG4 0x003b80f8 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG5 0x003b80fc /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG6 0x003b8100 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG7 0x003b8104 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG8 0x003b8108 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG9 0x003b810c /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG10 0x003b8110 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG11 0x003b8114 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG12 0x003b8118 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG13 0x003b811c /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG14 0x003b8120 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG15 0x003b8124 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY 0x003b8128 /* Delay on phy_dyn_vdl to the PHY */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_0 0x003b812c /* DDR PHY data storage register 0 */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_1 0x003b8130 /* DDR PHY data storage register 0 */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_2 0x003b8134 /* DDR PHY data storage register 0 */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_3 0x003b8138 /* DDR PHY data storage register 0 */
+
+/***************************************************************************
+ *CONFIG - DDR23_SHIM Config register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: reserved0 [31:27] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_reserved0_MASK     0xf8000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_reserved0_SHIFT    27
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: LAST_RD_STRETCH [26:26] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_RD_STRETCH_MASK 0x04000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_RD_STRETCH_SHIFT 26
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_RD_STRETCH_DEFAULT 0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: ODT_LATENCY [25:21] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_ODT_LATENCY_MASK   0x03e00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_ODT_LATENCY_SHIFT  21
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_ODT_LATENCY_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: LAST_READ_LATENCY [20:15] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_READ_LATENCY_MASK 0x001f8000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_READ_LATENCY_SHIFT 15
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_READ_LATENCY_DEFAULT 0x0000000b
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: READ_LATENCY [14:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_READ_LATENCY_MASK  0x00007f00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_READ_LATENCY_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_READ_LATENCY_DEFAULT 0x00000007
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: WRITE_LATENCY [07:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_WRITE_LATENCY_MASK 0x000000f8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_WRITE_LATENCY_SHIFT 3
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_WRITE_LATENCY_DEFAULT 0x0000000e
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: DRAM_WIDTH [02:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DRAM_WIDTH_MASK    0x00000006
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DRAM_WIDTH_SHIFT   1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DRAM_WIDTH_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: DDR_MODE [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DDR_MODE_MASK      0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DDR_MODE_SHIFT     0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DDR_MODE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *DDR23_SHIM_REV_ID - DDR23_SHIM Revision ID Register.
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_REV_ID :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_reserved0_MASK 0xffff0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_reserved0_SHIFT 16
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_REV_ID :: MAJOR_ID [15:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MAJOR_ID_MASK 0x0000ff00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MAJOR_ID_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MAJOR_ID_DEFAULT 0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_REV_ID :: MINOR_ID [07:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MINOR_ID_MASK 0x000000ff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MINOR_ID_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MINOR_ID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET - DDR soft reset register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RESET :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_reserved0_MASK      0xfffffff8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_reserved0_SHIFT     3
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RESET :: DATAPATH_216_RESET [02:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_216_RESET_MASK 0x00000004
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_216_RESET_SHIFT 2
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_216_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RESET :: DATAPATH_DDR_RESET [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_DDR_RESET_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_DDR_RESET_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_DDR_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RESET :: PHY_PWRUP_RSB [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_PHY_PWRUP_RSB_MASK  0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_PHY_PWRUP_RSB_SHIFT 0
+
+/***************************************************************************
+ *ODT_CONFIG - ODT Configuration register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_reserved0_MASK 0xffff0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_reserved0_SHIFT 16
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: ODT_TIE_HIGH [15:15] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_TIE_HIGH_MASK 0x00008000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_TIE_HIGH_SHIFT 15
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_TIE_HIGH_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: ODT_ENABLE [14:14] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_ENABLE_MASK 0x00004000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_ENABLE_SHIFT 14
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_ENABLE_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: STRETCH [13:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_STRETCH_MASK   0x00003800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_STRETCH_SHIFT  11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_STRETCH_DEFAULT 0x00000003
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: EARLY [10:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_EARLY_MASK     0x000007c0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_EARLY_SHIFT    6
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_EARLY_DEFAULT  0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: DELAY [05:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_DELAY_MASK     0x0000003f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_DELAY_SHIFT    0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_DELAY_DEFAULT  0x00000002
+
+/***************************************************************************
+ *PHY_USE_DYN_VDL - DDR PHY USE DYN VDL Control register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_USE_DYN_VDL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_USE_DYN_VDL :: DISABLE [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL_DISABLE_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL_DISABLE_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL_DISABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_POWER_SAVING - DDR PHY Idle power saving Control register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: reserved0 [31:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_reserved0_MASK 0xffffffc0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_reserved0_SHIFT 6
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: PhyAddrCntl [05:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_PhyAddrCntl_MASK 0x00000030
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_PhyAddrCntl_SHIFT 4
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_PhyAddrCntl_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane3 [03:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane3_MASK 0x00000008
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane3_SHIFT 3
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane3_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane2 [02:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane2_MASK 0x00000004
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane2_SHIFT 2
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane2_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane1 [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane1_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane1_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane1_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane0 [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane0_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHY_STANDBY_EXIT - DDR PHY standby exit register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_STANDBY_EXIT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_STANDBY_EXIT :: ENABLE [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT_ENABLE_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT_ENABLE_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *ANALOG_BYPASS_CNTRL - Analog macro register bypass control
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ANALOG_BYPASS_CNTRL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ANALOG_BYPASS_CNTRL :: BYPASS_PLL [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_BYPASS_PLL_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_BYPASS_PLL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_BYPASS_PLL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DDR_PLL_EXT_CLKSEL - DDR PLL external clock select register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PLL_EXT_CLKSEL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PLL_EXT_CLKSEL :: EXT_CLK_SEL [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TEST_MODE_CNTRL_REG - DDR23_SHIM testport control register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: TEST_MODE_CNTRL_REG :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_TEST_MODE_CNTRL_REG_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_TEST_MODE_CNTRL_REG_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_TEST_MODE_CNTRL_REG_reserved_for_eco0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DISABLE_CHIP_BYPASS_PLL - DDR bypass pll mode disable register.
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DISABLE_CHIP_BYPASS_PLL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DISABLE_CHIP_BYPASS_PLL :: DISABLE_BYPASS_PLL [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VECTOR_MODE_CLK_SEL - DDR VECTOR PLL bypass mode clock select
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: VECTOR_MODE_CLK_SEL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: VECTOR_MODE_CLK_SEL :: SEL [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_SEL_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_SEL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DDR_PAD_CNTRL - DDR Pad control register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_reserved0_MASK 0xffffff80
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_reserved0_SHIFT 7
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: IDDQ_MODE_ON_SELFREF [06:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK 0x00000040
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_SHIFT 6
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: PHY_IDLE_ENABLE [05:05] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_MASK 0x00000020
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_SHIFT 5
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: HIZ_ON_SELFREF [04:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_HIZ_ON_SELFREF_MASK 0x00000010
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_HIZ_ON_SELFREF_SHIFT 4
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_HIZ_ON_SELFREF_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: CNTRL [03:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_CNTRL_MASK  0x0000000f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_CNTRL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_CNTRL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CLK_GATE - CLK_667_ENABLE Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CLK_GATE :: UNUSED [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_UNUSED_MASK      0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_UNUSED_SHIFT     1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_UNUSED_DEFAULT   0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CLK_GATE :: CLK_667_ENABLE [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_CLK_667_ENABLE_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_CLK_667_ENABLE_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_CLK_667_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DDR23_SHIM_STATUS - DDR23_SHIM Status Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_STATUS :: reserved0 [31:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_reserved0_SHIFT 4
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_STATUS :: BL0_AND_BL1_RDY_SLIP [03:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL0_AND_BL1_RDY_SLIP_MASK 0x00000008
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL0_AND_BL1_RDY_SLIP_SHIFT 3
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_STATUS :: BL0_RDY_SLIP [02:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL0_RDY_SLIP_MASK 0x00000004
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL0_RDY_SLIP_SHIFT 2
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_STATUS :: BL1_RDY_SLIP [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL1_RDY_SLIP_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL1_RDY_SLIP_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_STATUS :: READY [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_READY_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_READY_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_READY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CMD_DATA_FIFO - Command and Data FIFO Status Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: reserved0 [31:26] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_reserved0_MASK 0xfc000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_reserved0_SHIFT 26
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: FIFO_FULL [25:25] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_FULL_MASK 0x02000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_FULL_SHIFT 25
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: FIFO_EMPTY [24:24] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_EMPTY_MASK 0x01000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_EMPTY_SHIFT 24
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: reserved1 [23:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_reserved1_MASK 0x00ffff00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_reserved1_SHIFT 8
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: WR_PNTR [07:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_WR_PNTR_MASK 0x000000f0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_WR_PNTR_SHIFT 4
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: RD_PNTR [03:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_RD_PNTR_MASK 0x0000000f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_RD_PNTR_SHIFT 0
+
+/***************************************************************************
+ *RD_DATAPATH - Read Datapath Status Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: reserved0 [31:28] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_reserved0_MASK 0xf0000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_reserved0_SHIFT 28
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: F_RDY_3 [27:27] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_3_MASK  0x08000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_3_SHIFT 27
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: F_RDY_2 [26:26] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_2_MASK  0x04000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_2_SHIFT 26
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: F_RDY_1 [25:25] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_1_MASK  0x02000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_1_SHIFT 25
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: F_RDY_0 [24:24] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_0_MASK  0x01000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_0_SHIFT 24
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: DWORD3_CNT [23:20] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD3_CNT_MASK 0x00f00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD3_CNT_SHIFT 20
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: DWORD2_CNT [19:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD2_CNT_MASK 0x000f0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD2_CNT_SHIFT 16
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: DWORD1_CNT [15:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD1_CNT_MASK 0x0000f000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD1_CNT_SHIFT 12
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: DWORD0_CNT [11:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD0_CNT_MASK 0x00000f00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD0_CNT_SHIFT 8
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: WR_PNTR [07:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_WR_PNTR_MASK  0x000000f0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_WR_PNTR_SHIFT 4
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: RD_PNTR [03:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_RD_PNTR_MASK  0x0000000f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_RD_PNTR_SHIFT 0
+
+/***************************************************************************
+ *FLAG_BUS - TP_OUT bus value Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: FLAG_BUS :: FLAG_BUS [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_FLAG_BUS_FLAG_BUS_MASK    0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_FLAG_BUS_FLAG_BUS_SHIFT   0
+
+/***************************************************************************
+ *MISC - Miscellaneous Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: reserved_for_eco0 [31:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_reserved_for_eco0_MASK 0xfffff000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_reserved_for_eco0_SHIFT 12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_reserved_for_eco0_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: BL0_AND_BL1_RDY_SLIP_CLR [11:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_AND_BL1_RDY_SLIP_CLR_MASK 0x00000800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_AND_BL1_RDY_SLIP_CLR_SHIFT 11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_AND_BL1_RDY_SLIP_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: BL0_RDY_SLIP_CLR [10:10] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_RDY_SLIP_CLR_MASK 0x00000400
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_RDY_SLIP_CLR_SHIFT 10
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_RDY_SLIP_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: BL1_RDY_SLIP_CLR [09:09] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL1_RDY_SLIP_CLR_MASK 0x00000200
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL1_RDY_SLIP_CLR_SHIFT 9
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL1_RDY_SLIP_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: FUNC1 [08:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC1_MASK           0x00000100
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC1_SHIFT          8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC1_DEFAULT        0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: FUNC0 [07:07] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC0_MASK           0x00000080
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC0_SHIFT          7
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC0_DEFAULT        0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: C2IO_INIT_RDY_OVR [06:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_C2IO_INIT_RDY_OVR_MASK 0x00000040
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_C2IO_INIT_RDY_OVR_SHIFT 6
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_C2IO_INIT_RDY_OVR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: RD_FIFO_HOLD_CLR [05:05] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_RD_FIFO_HOLD_CLR_MASK 0x00000020
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_RD_FIFO_HOLD_CLR_SHIFT 5
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_RD_FIFO_HOLD_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: CMD_FIFO_HOLD_CLR [04:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_CMD_FIFO_HOLD_CLR_MASK 0x00000010
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_CMD_FIFO_HOLD_CLR_SHIFT 4
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_CMD_FIFO_HOLD_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: DWORD3_OVERRUN_CLR [03:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD3_OVERRUN_CLR_MASK 0x00000008
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD3_OVERRUN_CLR_SHIFT 3
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD3_OVERRUN_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: DWORD2_OVERRUN_CLR [02:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD2_OVERRUN_CLR_MASK 0x00000004
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD2_OVERRUN_CLR_SHIFT 2
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD2_OVERRUN_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: DWORD1_OVERRUN_CLR [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD1_OVERRUN_CLR_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD1_OVERRUN_CLR_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD1_OVERRUN_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: DWORD0_OVERRUN_CLR [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD0_OVERRUN_CLR_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD0_OVERRUN_CLR_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD0_OVERRUN_CLR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE0_RW - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SPARE0_RW :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RW_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RW_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RW_reserved_for_eco0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE1_RW - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SPARE1_RW :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RW_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RW_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RW_reserved_for_eco0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE0_RO - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SPARE0_RO :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RO_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RO_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RO_reserved_for_eco0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE1_RO - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SPARE1_RO :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RO_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RO_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RO_reserved_for_eco0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DDR3_RESET_CNTRL - FORCE_DDR3_RESET Deassert  Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR3_RESET_CNTRL :: UNUSED [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_UNUSED_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_UNUSED_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_UNUSED_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR3_RESET_CNTRL :: FORCE_DDR3_RESET [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PLL6CH_PNDIV_SYS - SYS PLL P and N Divider Controls
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PLL6CH_PNDIV_SYS :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_reserved0_MASK 0x80000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_reserved0_SHIFT 31
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PLL6CH_PNDIV_SYS :: PDIV [30:28] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_PDIV_MASK 0x70000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_PDIV_SHIFT 28
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_PDIV_DEFAULT 0x00000002
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PLL6CH_PNDIV_SYS :: NDIV_INT [27:20] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_INT_MASK 0x0ff00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_INT_SHIFT 20
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_INT_DEFAULT 0x0000004e
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PLL6CH_PNDIV_SYS :: NDIV_FRAC [19:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_FRAC_MASK 0x000fffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_FRAC_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_FRAC_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_PLL_GAIN - SYS PLL Gain Controls
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: reserved0 [31:23] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_reserved0_MASK 0xff800000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_reserved0_SHIFT 23
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: FB_PHASE_ENA [22:22] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_ENA_MASK 0x00400000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_ENA_SHIFT 22
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_ENA_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: FB_PHASE_OFFSET [21:10] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_OFFSET_MASK 0x003ffc00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_OFFSET_SHIFT 10
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_OFFSET_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: KP [09:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KP_MASK      0x000003c0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KP_SHIFT     6
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KP_DEFAULT   0x00000008
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: KI [05:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KI_MASK      0x00000038
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KI_SHIFT     3
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KI_DEFAULT   0x00000003
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: KA [02:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KA_MASK      0x00000007
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KA_SHIFT     0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KA_DEFAULT   0x00000001
+
+/***************************************************************************
+ *SYS_PLL_CTRL - SYS PLL Control Vector
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: reserved0 [31:23] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_reserved0_MASK 0xff800000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_reserved0_SHIFT 23
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: ENA_8PHASE [22:22] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_8PHASE_MASK 0x00400000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_8PHASE_SHIFT 22
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_8PHASE_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: ENA_SSC [21:21] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_SSC_MASK 0x00200000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_SSC_SHIFT 21
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_SSC_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: VCO_DIV2_EN [20:20] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_VCO_DIV2_EN_MASK 0x00100000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_VCO_DIV2_EN_SHIFT 20
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_VCO_DIV2_EN_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: AUX_CTRL [19:19] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_AUX_CTRL_MASK 0x00080000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_AUX_CTRL_SHIFT 19
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_AUX_CTRL_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: REFCLK_OUT [18:18] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_REFCLK_OUT_MASK 0x00040000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_REFCLK_OUT_SHIFT 18
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_REFCLK_OUT_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: STAT_UPDATE [17:17] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_UPDATE_MASK 0x00020000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_UPDATE_SHIFT 17
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_UPDATE_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: STAT_SELECT [16:14] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_SELECT_MASK 0x0001c000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_SELECT_SHIFT 14
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_SELECT_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: STAT_RESET [13:13] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_RESET_MASK 0x00002000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_RESET_SHIFT 13
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: DCO_CTRL_BYPASS_ENA [12:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_ENA_MASK 0x00001000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_ENA_SHIFT 12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_ENA_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_MASK 0x00000fff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SSC_STEP - SSC Step Size for all 6-chan PLLs
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SSC_STEP :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP_reserved0_MASK   0xffff0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP_reserved0_SHIFT  16
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SSC_STEP :: SSC_STEP [15:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP_SSC_STEP_MASK    0x0000ffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP_SSC_STEP_SHIFT   0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SSC_LIMIT - SSC Limit for all 6-chan PLLs
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SSC_LIMIT :: reserved0 [31:22] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT_reserved0_MASK  0xffc00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT_reserved0_SHIFT 22
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SSC_LIMIT :: SSC_LIMIT [21:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT_SSC_LIMIT_MASK  0x003fffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT_SSC_LIMIT_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_PLL_MDIV0 - SYS PLL M Divider Controls for Channel0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: reserved0 [31:14] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_reserved0_MASK 0xffffc000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_reserved0_SHIFT 14
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: CHAN_HOLD_OUTPUT [13:13] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_HOLD_OUTPUT_MASK 0x00002000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_HOLD_OUTPUT_SHIFT 13
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_HOLD_OUTPUT_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: CHAN_LOAD_MDIV [12:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_LOAD_MDIV_MASK 0x00001000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_LOAD_MDIV_SHIFT 12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_LOAD_MDIV_DEFAULT 0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: CHAN_ENA [11:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_ENA_MASK 0x00000800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_ENA_SHIFT 11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_ENA_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: CHAN_MDEL [10:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDEL_MASK 0x00000700
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDEL_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDEL_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: CHAN_MDIV [07:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDIV_MASK 0x000000ff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDIV_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDIV_DEFAULT 0x00000008
+
+/***************************************************************************
+ *SYS_PLL_MDIVX - SYS PLL M Divider Controls for Extra Unused Channels
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: reserved0 [31:14] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_reserved0_MASK 0xffffc000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_reserved0_SHIFT 14
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: CHAN_HOLD_OUTPUT [13:13] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_HOLD_OUTPUT_MASK 0x00002000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_HOLD_OUTPUT_SHIFT 13
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_HOLD_OUTPUT_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: CHAN_LOAD_MDIV [12:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_LOAD_MDIV_MASK 0x00001000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_LOAD_MDIV_SHIFT 12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_LOAD_MDIV_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: CHAN_ENA [11:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_ENA_MASK 0x00000800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_ENA_SHIFT 11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_ENA_DEFAULT 0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: CHAN_MDEL [10:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDEL_MASK 0x00000700
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDEL_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDEL_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: CHAN_MDIV [07:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDIV_MASK 0x000000ff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDIV_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDIV_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_PLL_STAT - SYS PLL Status
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_STAT :: reserved0 [31:25] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_reserved0_MASK 0xfe000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_reserved0_SHIFT 25
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_STAT :: DEBUG_OUTPUT [24:13] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_DEBUG_OUTPUT_MASK 0x01ffe000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_DEBUG_OUTPUT_SHIFT 13
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_DEBUG_OUTPUT_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_STAT :: LOCK [12:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_LOCK_MASK    0x00001000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_LOCK_SHIFT   12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_LOCK_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_STAT :: UNLOCK_COUNT [11:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_UNLOCK_COUNT_MASK 0x00000fff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_UNLOCK_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_UNLOCK_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_PLL_PWRDN_ref_clk_sel - SYS PLL power-down and reference clock selection
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_PWRDN_ref_clk_sel :: reserved0 [31:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_reserved0_MASK 0xfffffffc
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_reserved0_SHIFT 2
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_PWRDN_ref_clk_sel :: REFCLK_SEL [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_REFCLK_SEL_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_REFCLK_SEL_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_REFCLK_SEL_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_PWRDN_ref_clk_sel :: PWRDN [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_PWRDN_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_PWRDN_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_PWRDN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_PLL_RESET_POST_RESET - SYS PLL Reset and post-resetb selcection
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_RESET_POST_RESET :: reserved0 [31:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_reserved0_MASK 0xfffffffc
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_reserved0_SHIFT 2
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_RESET_POST_RESET :: POST_RESETB [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_POST_RESETB_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_POST_RESETB_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_POST_RESETB_DEFAULT 0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_RESET_POST_RESET :: GLOBAL_RESETB [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_GLOBAL_RESETB_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_GLOBAL_RESETB_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_GLOBAL_RESETB_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SYS_PLL_CTRL_SR - SYS PLL control and SR selcection
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL_SR :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_reserved0_MASK 0xe0000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_reserved0_SHIFT 29
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL_SR :: PLL_SR [28:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_SR_MASK 0x1ffff800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_SR_SHIFT 11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_SR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL_SR :: PLL_CTRL_1 [10:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_CTRL_1_MASK 0x000007fc
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_CTRL_1_SHIFT 2
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_CTRL_1_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL_SR :: NDIV_INT_1 [01:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_NDIV_INT_1_MASK 0x00000003
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_NDIV_INT_1_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_NDIV_INT_1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SHIM_TO_PHY_GATED_BYPASS_CLK - Shim to PHY gated bypass_clock selection
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SHIM_TO_PHY_GATED_BYPASS_CLK :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SHIM_TO_PHY_GATED_BYPASS_CLK :: BYPASS_CLK_GATED_TO_SHIM_PHY [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK_BYPASS_CLK_GATED_TO_SHIM_PHY_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK_BYPASS_CLK_GATED_TO_SHIM_PHY_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK_BYPASS_CLK_GATED_TO_SHIM_PHY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG0 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG0 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG0_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG0_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG0_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG1 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG1 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG1_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG1_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG1_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG2 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG2 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG2_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG2_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG2_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG3 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG3 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG3_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG3_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG3_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG4 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG4 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG4_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG4_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG4_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG5 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG5 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG5_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG5_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG5_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG6 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG6 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG6_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG6_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG6_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG7 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG7 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG7_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG7_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG7_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG8 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG8 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG8_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG8_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG8_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG9 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG9 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG9_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG9_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG9_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG10 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG10 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG10_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG10_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG10_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG11 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG11 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG11_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG11_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG11_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG12 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG12 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG12_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG12_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG12_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG13 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG13 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG13_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG13_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG13_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG14 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG14 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG14_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG14_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG14_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG15 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG15 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG15_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG15_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG15_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHY_DYN_VDL_DLY - Delay on phy_dyn_vdl to the PHY
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: reserved0 [31:28] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved0_MASK 0xf0000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved0_SHIFT 28
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: DYN_VDL_DEASSERT_TO_READ_ENB_DLY [27:24] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_READ_ENB_DLY_MASK 0x0f000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_READ_ENB_DLY_SHIFT 24
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_READ_ENB_DLY_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: reserved1 [23:20] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved1_MASK 0x00f00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved1_SHIFT 20
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: DYN_VDL_ASSERT_TO_READ_ENB_DLY [19:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_READ_ENB_DLY_MASK 0x000f0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_READ_ENB_DLY_SHIFT 16
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_READ_ENB_DLY_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: reserved2 [15:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved2_MASK 0x0000f000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved2_SHIFT 12
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: DYN_VDL_DEASSERT_TO_WR_VALID_DLY [11:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_WR_VALID_DLY_MASK 0x00000f00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_WR_VALID_DLY_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_WR_VALID_DLY_DEFAULT 0x00000002
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: reserved3 [07:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved3_MASK 0x000000f0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved3_SHIFT 4
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: DYN_VDL_ASSERT_TO_WR_VALID_DLY [03:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_WR_VALID_DLY_MASK 0x0000000f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_WR_VALID_DLY_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_WR_VALID_DLY_DEFAULT 0x00000002
+
+/***************************************************************************
+ *AON_STORAGE_IN_PHY_0 - DDR PHY data storage register 0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: AON_STORAGE_IN_PHY_0 :: DTATA [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_0_DTATA_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_0_DTATA_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_0_DTATA_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AON_STORAGE_IN_PHY_1 - DDR PHY data storage register 0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: AON_STORAGE_IN_PHY_1 :: DTATA [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_1_DTATA_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_1_DTATA_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_1_DTATA_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AON_STORAGE_IN_PHY_2 - DDR PHY data storage register 0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: AON_STORAGE_IN_PHY_2 :: DTATA [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_2_DTATA_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_2_DTATA_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_2_DTATA_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AON_STORAGE_IN_PHY_3 - DDR PHY data storage register 0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: AON_STORAGE_IN_PHY_3 :: DTATA [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_3_DTATA_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_3_DTATA_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_3_DTATA_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_memc_ddr_0.h b/include/linux/brcmstb/7429b0/bchp_memc_ddr_0.h
new file mode 100644
index 0000000..0895577
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_memc_ddr_0.h
@@ -0,0 +1,2662 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:14 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR_0_H__
+#define BCHP_MEMC_DDR_0_H__
+
+/***************************************************************************
+ *MEMC_DDR_0 - Memory Controller Sequencer (DDR Param/Control) Registers 0
+ ***************************************************************************/
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG            0x003b2000 /* Memory Controller Mode-Configuration Register. */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL          0x003b2004 /* Dram iniitialization control */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS         0x003b2008 /* Dram iniitialization status */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0              0x003b200c /* Dram Mode0 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1              0x003b2010 /* Dram Mode1 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2              0x003b2014 /* Dram Mode2 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3              0x003b2018 /* Dram Mode3 register */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG               0x003b201c /* Precharge power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG              0x003b2020 /* Self-refresh power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SSPD_CMD                 0x003b2024 /* Software standby power down mode */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS        0x003b2028 /* Power down status */
+#define BCHP_MEMC_DDR_0_WARM_BOOT                0x003b202c /* Warm boot control registers */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0            0x003b2030 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1            0x003b2034 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2            0x003b2038 /* Read to Write & write to read timing register */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3            0x003b203c /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4            0x003b2040 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5            0x003b2044 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ         0x003b2048 /* Memory Controller Sequencer Enable */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT        0x003b204c /* Memory Controller , state machine timeout register. */
+#define BCHP_MEMC_DDR_0_BANK_STATUS              0x003b2050 /* Memory Controller, Bank Status Register. */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY           0x003b2054 /* Memory Controller, Tester Latency Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0               0x003b2058 /* Memory Controller, DATA_PINMAP_BYTE0_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1               0x003b205c /* Memory Controller, DATA_PINMAP_BYTE1_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2               0x003b2060 /* Memory Controller, DATA_PINMAP_BYTE2_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3               0x003b2064 /* Memory Controller, DATA_PINMAP_BYTE3_SEL Register. */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD   0x003b2068 /* Memory Controller, DDR3 DRAM reset Register. */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL             0x003b206c /* Statistics Control register */
+#define BCHP_MEMC_DDR_0_STAT_TIMER               0x003b2070 /* Statistics Timer */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP            0x003b2074 /* DRAM Idle_NOP Cycle Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP        0x003b2078 /* Maximum DRAM idle_NOP cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL             0x003b207c /* CAS Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL         0x003b2080 /* Maximum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL         0x003b2084 /* DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL 0x003b2088 /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL      0x003b208c /* Number of overall system memory read transactions. */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL     0x003b2090 /* Number of overall system memory write transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL       0x003b2094 /* Maximum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL       0x003b2098 /* Minimum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS  0x003b209c /* Service CAS Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS 0x003b20a0 /* Maximum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS 0x003b20a4 /* Minimum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY 0x003b20a8 /* Service Intra DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY 0x003b20ac /* Service Post DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES 0x003b20b0 /* Maximum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES 0x003b20b4 /* Minimum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ 0x003b20b8 /* Service Read Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE 0x003b20bc /* Service Write Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS 0x003b20c0 /* Maximum service Transaction count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS 0x003b20c4 /* Minimum service cycle Transaction register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY 0x003b20c8 /* Service Latency Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY 0x003b20cc /* Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY 0x003b20d0 /* Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x003b20d4 /* Absolute Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x003b20d8 /* Absolute Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH             0x003b20dc /* Total number of refreshes issuedr. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0        0x003b20e0 /* CAS cycle count register for client 0. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1        0x003b20e4 /* CAS cycle count register for client 1. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2        0x003b20e8 /* CAS cycle count register for client 2. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3        0x003b20ec /* CAS cycle count register for client 3. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4        0x003b20f0 /* CAS cycle count register for client 4. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5        0x003b20f4 /* CAS cycle count register for client 5. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6        0x003b20f8 /* CAS cycle count register for client 6. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7        0x003b20fc /* CAS cycle count register for client 7. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8        0x003b2100 /* CAS cycle count register for client 8. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9        0x003b2104 /* CAS cycle count register for client 9. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10       0x003b2108 /* CAS cycle count register for client 10. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11       0x003b210c /* CAS cycle count register for client 11. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12       0x003b2110 /* CAS cycle count register for client 12. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13       0x003b2114 /* CAS cycle count register for client 13. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14       0x003b2118 /* CAS cycle count register for client 14. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15       0x003b211c /* CAS cycle count register for client 15. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16       0x003b2120 /* CAS cycle count register for client 16. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17       0x003b2124 /* CAS cycle count register for client 17. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18       0x003b2128 /* CAS cycle count register for client 18. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19       0x003b212c /* CAS cycle count register for client 19. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20       0x003b2130 /* CAS cycle count register for client 20. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21       0x003b2134 /* CAS cycle count register for client 21. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22       0x003b2138 /* CAS cycle count register for client 22. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23       0x003b213c /* CAS cycle count register for client 23. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24       0x003b2140 /* CAS cycle count register for client 24. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25       0x003b2144 /* CAS cycle count register for client 25. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26       0x003b2148 /* CAS cycle count register for client 26. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27       0x003b214c /* CAS cycle count register for client 27. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28       0x003b2150 /* CAS cycle count register for client 28. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29       0x003b2154 /* CAS cycle count register for client 29. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30       0x003b2158 /* CAS cycle count register for client 30. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31       0x003b215c /* CAS cycle count register for client 31. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32       0x003b2160 /* CAS cycle count register for client 32. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33       0x003b2164 /* CAS cycle count register for client 33. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34       0x003b2168 /* CAS cycle count register for client 34. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35       0x003b216c /* CAS cycle count register for client 35. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36       0x003b2170 /* CAS cycle count register for client 36. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37       0x003b2174 /* CAS cycle count register for client 37. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38       0x003b2178 /* CAS cycle count register for client 38. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39       0x003b217c /* CAS cycle count register for client 39. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40       0x003b2180 /* CAS cycle count register for client 40. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41       0x003b2184 /* CAS cycle count register for client 41. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42       0x003b2188 /* CAS cycle count register for client 42. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43       0x003b218c /* CAS cycle count register for client 43. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44       0x003b2190 /* CAS cycle count register for client 44. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45       0x003b2194 /* CAS cycle count register for client 45. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46       0x003b2198 /* CAS cycle count register for client 46. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47       0x003b219c /* CAS cycle count register for client 47. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48       0x003b21a0 /* CAS cycle count register for client 48. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49       0x003b21a4 /* CAS cycle count register for client 49. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50       0x003b21a8 /* CAS cycle count register for client 50. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51       0x003b21ac /* CAS cycle count register for client 51. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52       0x003b21b0 /* CAS cycle count register for client 52. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53       0x003b21b4 /* CAS cycle count register for client 53. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54       0x003b21b8 /* CAS cycle count register for client 54. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55       0x003b21bc /* CAS cycle count register for client 55. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56       0x003b21c0 /* CAS cycle count register for client 56. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57       0x003b21c4 /* CAS cycle count register for client 57. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58       0x003b21c8 /* CAS cycle count register for client 58. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59       0x003b21cc /* CAS cycle count register for client 59. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60       0x003b21d0 /* CAS cycle count register for client 60. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61       0x003b21d4 /* CAS cycle count register for client 61. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62       0x003b21d8 /* CAS cycle count register for client 62. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63       0x003b21dc /* CAS cycle count register for client 63. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64       0x003b21e0 /* CAS cycle count register for client 64. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65       0x003b21e4 /* CAS cycle count register for client 65. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66       0x003b21e8 /* CAS cycle count register for client 66. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67       0x003b21ec /* CAS cycle count register for client 67. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68       0x003b21f0 /* CAS cycle count register for client 68. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69       0x003b21f4 /* CAS cycle count register for client 69. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70       0x003b21f8 /* CAS cycle count register for client 70. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71       0x003b21fc /* CAS cycle count register for client 71. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72       0x003b2200 /* CAS cycle count register for client 72. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73       0x003b2204 /* CAS cycle count register for client 73. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74       0x003b2208 /* CAS cycle count register for client 74. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75       0x003b220c /* CAS cycle count register for client 75. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76       0x003b2210 /* CAS cycle count register for client 76. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77       0x003b2214 /* CAS cycle count register for client 77. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78       0x003b2218 /* CAS cycle count register for client 78. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79       0x003b221c /* CAS cycle count register for client 79. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80       0x003b2220 /* CAS cycle count register for client 80. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81       0x003b2224 /* CAS cycle count register for client 81. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82       0x003b2228 /* CAS cycle count register for client 82. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83       0x003b222c /* CAS cycle count register for client 83. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84       0x003b2230 /* CAS cycle count register for client 84. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85       0x003b2234 /* CAS cycle count register for client 85. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86       0x003b2238 /* CAS cycle count register for client 86. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87       0x003b223c /* CAS cycle count register for client 87. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88       0x003b2240 /* CAS cycle count register for client 88. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89       0x003b2244 /* CAS cycle count register for client 89. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90       0x003b2248 /* CAS cycle count register for client 90. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91       0x003b224c /* CAS cycle count register for client 91. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92       0x003b2250 /* CAS cycle count register for client 92. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93       0x003b2254 /* CAS cycle count register for client 93. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94       0x003b2258 /* CAS cycle count register for client 94. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95       0x003b225c /* CAS cycle count register for client 95. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96       0x003b2260 /* CAS cycle count register for client 96. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97       0x003b2264 /* CAS cycle count register for client 97. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98       0x003b2268 /* CAS cycle count register for client 98. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99       0x003b226c /* CAS cycle count register for client 99. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100      0x003b2270 /* CAS cycle count register for client 100. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101      0x003b2274 /* CAS cycle count register for client 101. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102      0x003b2278 /* CAS cycle count register for client 102. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103      0x003b227c /* CAS cycle count register for client 103. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104      0x003b2280 /* CAS cycle count register for client 104. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105      0x003b2284 /* CAS cycle count register for client 105. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106      0x003b2288 /* CAS cycle count register for client 106. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107      0x003b228c /* CAS cycle count register for client 107. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108      0x003b2290 /* CAS cycle count register for client 108. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109      0x003b2294 /* CAS cycle count register for client 109. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110      0x003b2298 /* CAS cycle count register for client 110. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111      0x003b229c /* CAS cycle count register for client 111. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112      0x003b22a0 /* CAS cycle count register for client 112. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113      0x003b22a4 /* CAS cycle count register for client 113. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114      0x003b22a8 /* CAS cycle count register for client 114. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115      0x003b22ac /* CAS cycle count register for client 115. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116      0x003b22b0 /* CAS cycle count register for client 116. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117      0x003b22b4 /* CAS cycle count register for client 117. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118      0x003b22b8 /* CAS cycle count register for client 118. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119      0x003b22bc /* CAS cycle count register for client 119. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120      0x003b22c0 /* CAS cycle count register for client 120. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121      0x003b22c4 /* CAS cycle count register for client 121. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122      0x003b22c8 /* CAS cycle count register for client 122. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123      0x003b22cc /* CAS cycle count register for client 123. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124      0x003b22d0 /* CAS cycle count register for client 124. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125      0x003b22d4 /* CAS cycle count register for client 125. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126      0x003b22d8 /* CAS cycle count register for client 126. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127      0x003b22dc /* CAS cycle count register for client 127. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL         0x003b22e0 /* Minimum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL 0x003b22e4 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL 0x003b22e8 /* MEMSYS Auto Init Control. */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS  0x003b22ec /* MEMSYS Auto Init Status. */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE 0x003b22f0 /* PHY VDL calibrate override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE 0x003b22f4 /* SHIM PLL pndiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE 0x003b22f8 /* SHIM PLL mdiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY          0x003b22fc /* Dynamic VDL shmoo command delay. */
+
+/***************************************************************************
+ *CNTRLR_CONFIG - Memory Controller Mode-Configuration Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_MASK               0xfffffff8
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_SHIFT              3
+
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DEVICE_TECH [02:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_SHIFT            0
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_DEFAULT          0x00000003
+
+/***************************************************************************
+ *DRAM_INIT_CNTRL - Dram iniitialization control
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_MASK             0xfffffff8
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_SHIFT            3
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: BYPASS_PHY_INIT_RDY [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_MASK   0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_SHIFT  2
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR_TECH [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DEFAULT           0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR2              0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR3              1
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR3_INIT_MODE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_MASK        0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_SHIFT       0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *DRAM_INIT_STATUS - Dram iniitialization status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_SHIFT           0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_DEFAULT         0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_0 - Dram Mode0 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: PD_EXIT [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_MASK              0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_SHIFT             12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_DEFAULT         0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: CL [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_MASK                   0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_DEFAULT                0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BL [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_DEFAULT                0x00000002
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK        0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT       12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT     0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT         0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_MASK               0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_SHIFT              4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT            0x00000004
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_DEFAULT               0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_MASK                 0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_SHIFT                2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_DEFAULT              0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_MASK                   0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_1 - Dram Mode1 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DEFAULT             0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: RDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DQSB [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_MASK                 0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_SHIFT                10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_ENABLE               0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DISABLE              1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: OCD_CAL [09:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_MASK              0x00000380
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_SHIFT             7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_DEFAULT       0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: AL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_MASK                   0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DRV_IMP [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DISABLE            1
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT             0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_MASK             0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_SHIFT            10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK          0x00000200
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT         9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_MASK             0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT            7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT          0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE           1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK   0x00000020
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT  5
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_MASK                   0x00000018
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT       0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK   0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT  1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DISABLE            1
+
+/***************************************************************************
+ *DRAM_MODE_2 - Dram Mode2 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_1 [12:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_MASK             0x00001f00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: HT_SRF [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_ENABLE             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DISABLE            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_2 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_MASK             0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_SHIFT            4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: DCC_ENABLE [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_MASK           0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_SHIFT          3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DEFAULT        0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_ENABLE         1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DISABLE        0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_DEFAULT              0x00000000
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_MASK             0x00001800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_SHIFT            11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_MASK               0x00000600
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_SHIFT              9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT            0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT            0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT             6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_MASK                  0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_DEFAULT               0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_3 - Dram Mode3 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: unused_0 [15:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_MASK                  0x0000fff8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR2 :: unused_1 [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_SHIFT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_DEFAULT          0x00000000
+
+/* union - case DDR3 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_MASK                  0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_SHIFT                 2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_DEFAULT               0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_MASK              0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PPD_CONFIG - Precharge power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PPD_CONFIG :: reserved0 [31:13] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_MASK                  0xffffe000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_SHIFT                 13
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_EN [12:12] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_MASK                     0x00001000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_SHIFT                    12
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_DEFAULT                  0x00000000
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: INACT_COUNT [11:00] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_MASK                0x00000fff
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *SRPD_CONFIG - Self-refresh power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SRPD_CONFIG :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_MASK                 0xfffe0000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_SHIFT                17
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: SRPD_EN [16:16] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_MASK                   0x00010000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_SHIFT                  16
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_DEFAULT                0x00000000
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SSPD_CMD - Software standby power down mode
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SSPD_CMD :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_MASK                    0xfffffffe
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_SHIFT                   1
+
+/* MEMC_DDR_0 :: SSPD_CMD :: SSPD [00:00] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK                         0x00000001
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_SHIFT                        0
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *POWER_DOWN_STATUS - Power down status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_MASK           0xfffffff8
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_SHIFT          3
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SSPD [02:02] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK                0x00000004
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_SHIFT               2
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_DEFAULT             0x00000000
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SRPD [01:01] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_MASK                0x00000002
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_SHIFT               1
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_DEFAULT             0x00000000
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: PPD [00:00] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_MASK                 0x00000001
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_SHIFT                0
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_DEFAULT              0x00000000
+
+/***************************************************************************
+ *WARM_BOOT - Warm boot control registers
+ ***************************************************************************/
+/* MEMC_DDR_0 :: WARM_BOOT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_MASK                   0xfffffffe
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_SHIFT                  1
+
+/* MEMC_DDR_0 :: WARM_BOOT :: WARM_BOOT [00:00] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_MASK                   0x00000001
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_TIMING_0 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_MASK                0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_SHIFT               24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_DEFAULT             0x00000006
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_MASK                0x00ff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_SHIFT               16
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_DEFAULT             0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_MASK                 0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_SHIFT                8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_DEFAULT              0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_DEFAULT             0x00000014
+
+/***************************************************************************
+ *DRAM_TIMING_1 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_MASK                0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_SHIFT               8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_DEFAULT             0x0000001b
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_DEFAULT             0x00000004
+
+/***************************************************************************
+ *DRAM_TIMING_2 - Read to Write & write to read timing register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_MASK               0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_SHIFT              8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_DEFAULT            0x0000000e
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_MASK               0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_DEFAULT            0x00000009
+
+/***************************************************************************
+ *DRAM_TIMING_3 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: reserved0 [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_MASK               0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_SHIFT              24
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT      0x0000000c
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: POWERUP_CKE_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_MASK       0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_SHIFT      10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_DEFAULT    0x0000005e
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: DLL_LOCK_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_MASK          0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_SHIFT         0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_DEFAULT       0x00000200
+
+/***************************************************************************
+ *DRAM_TIMING_4 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: PRECHARGE_ALL_DELAY [28:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_MASK     0x1f000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_SHIFT    24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_DEFAULT  0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: LOAD_MODE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_DEFAULT      0x0000000c
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: REFRESH_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_MASK           0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_SHIFT          10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT        0x00000058
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_MASK           0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT          0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT        0x00000200
+
+/***************************************************************************
+ *DRAM_TIMING_5 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_ASSETION_DELAY [28:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_MASK      0x1ff80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_SHIFT     19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_DEFAULT   0x00000105
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [18:15] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK           0x00078000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT          15
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT        0x00000003
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [14:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK         0x00007c00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT        10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT      0x0000000d
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK      0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT     0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT   0x00000200
+
+/***************************************************************************
+ *CNTRLR_START_SEQ - Memory Controller Sequencer Enable
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: START_SEQ [00:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_SHIFT           0
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_MASK           0xfffe0000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_SHIFT          17
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_MASK              0x00010000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT             16
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT            0x0000ffff
+
+/***************************************************************************
+ *BANK_STATUS - Memory Controller, Bank Status Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: BANK_STATUS :: reserved0 [31:08] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_SHIFT                8
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK7_STATUS [07:07] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_SHIFT             7
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK6_STATUS [06:06] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_SHIFT             6
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK5_STATUS [05:05] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_MASK              0x00000020
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_SHIFT             5
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK4_STATUS [04:04] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_MASK              0x00000010
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_SHIFT             4
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK3_STATUS [03:03] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_MASK              0x00000008
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_SHIFT             3
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK2_STATUS [02:02] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_MASK              0x00000004
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_SHIFT             2
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK1_STATUS [01:01] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_SHIFT             1
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK0_STATUS [00:00] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_MASK              0x00000001
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_SHIFT             0
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_DEFAULT           0x00000001
+
+/***************************************************************************
+ *TESTER_LATENCY - Memory Controller, Tester Latency Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: TESTER_LATENCY :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_MASK              0xffffff80
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_SHIFT             7
+
+/* MEMC_DDR_0 :: TESTER_LATENCY :: TLATENCY_SEL [06:00] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_MASK           0x0000007f
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_SHIFT          0
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE0 - Memory Controller, DATA_PINMAP_BYTE0_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE1 - Memory Controller, DATA_PINMAP_BYTE1_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE2 - Memory Controller, DATA_PINMAP_BYTE2_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE3 - Memory Controller, DATA_PINMAP_BYTE3_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_DDR3_RESET_PERIOD - Memory Controller, DDR3 DRAM reset Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: reserved0 [31:20] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_MASK      0xfff00000
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_SHIFT     20
+
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: DRAM_RESET_PERIOD [19:00] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_MASK 0x000fffff
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_SHIFT 0
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_DEFAULT 0x0000a8c0
+
+/***************************************************************************
+ *STAT_CONTROL - Statistics Control register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CONTROL :: reserved0 [31:09] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_MASK                0xfffffe00
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_SHIFT               9
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: COUNTER_MODE [08:08] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_SHIFT            8
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_DEFAULT          0x00000000
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT    1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_NORMAL           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: STAT_ENABLE [07:07] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_SHIFT             7
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DEFAULT           0x00000000
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_ENABLE            1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DISABLE           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: CLIENT_ID [06:00] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_MASK                0x0000007f
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_TIMER - Statistics Timer
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TIMER :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_MASK                      0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_SHIFT                     0
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_MASK                   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_ALL - CAS Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_PENALTY_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_MASK            0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_SHIFT           0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_DEFAULT           0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_MASK         0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT        0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_REFRESH - Total number of refreshes issuedr.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_REFRESH :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_0 - CAS cycle count register for client 0.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_1 - CAS cycle count register for client 1.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_2 - CAS cycle count register for client 2.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_3 - CAS cycle count register for client 3.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_4 - CAS cycle count register for client 4.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_5 - CAS cycle count register for client 5.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_6 - CAS cycle count register for client 6.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_7 - CAS cycle count register for client 7.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_8 - CAS cycle count register for client 8.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_9 - CAS cycle count register for client 9.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_10 - CAS cycle count register for client 10.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_11 - CAS cycle count register for client 11.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_12 - CAS cycle count register for client 12.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_13 - CAS cycle count register for client 13.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_14 - CAS cycle count register for client 14.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_15 - CAS cycle count register for client 15.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_16 - CAS cycle count register for client 16.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_17 - CAS cycle count register for client 17.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_18 - CAS cycle count register for client 18.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_19 - CAS cycle count register for client 19.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_20 - CAS cycle count register for client 20.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_21 - CAS cycle count register for client 21.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_22 - CAS cycle count register for client 22.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_23 - CAS cycle count register for client 23.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_24 - CAS cycle count register for client 24.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_25 - CAS cycle count register for client 25.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_26 - CAS cycle count register for client 26.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_27 - CAS cycle count register for client 27.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_28 - CAS cycle count register for client 28.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_29 - CAS cycle count register for client 29.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_30 - CAS cycle count register for client 30.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_31 - CAS cycle count register for client 31.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_32 - CAS cycle count register for client 32.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_33 - CAS cycle count register for client 33.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_34 - CAS cycle count register for client 34.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_35 - CAS cycle count register for client 35.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_36 - CAS cycle count register for client 36.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_37 - CAS cycle count register for client 37.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_38 - CAS cycle count register for client 38.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_39 - CAS cycle count register for client 39.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_40 - CAS cycle count register for client 40.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_41 - CAS cycle count register for client 41.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_42 - CAS cycle count register for client 42.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_43 - CAS cycle count register for client 43.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_44 - CAS cycle count register for client 44.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_45 - CAS cycle count register for client 45.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_46 - CAS cycle count register for client 46.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_47 - CAS cycle count register for client 47.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_48 - CAS cycle count register for client 48.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_49 - CAS cycle count register for client 49.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_50 - CAS cycle count register for client 50.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_51 - CAS cycle count register for client 51.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_52 - CAS cycle count register for client 52.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_53 - CAS cycle count register for client 53.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_54 - CAS cycle count register for client 54.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_55 - CAS cycle count register for client 55.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_56 - CAS cycle count register for client 56.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_57 - CAS cycle count register for client 57.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_58 - CAS cycle count register for client 58.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_59 - CAS cycle count register for client 59.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_60 - CAS cycle count register for client 60.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_61 - CAS cycle count register for client 61.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_62 - CAS cycle count register for client 62.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_63 - CAS cycle count register for client 63.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_64 - CAS cycle count register for client 64.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_65 - CAS cycle count register for client 65.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_66 - CAS cycle count register for client 66.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_67 - CAS cycle count register for client 67.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_68 - CAS cycle count register for client 68.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_69 - CAS cycle count register for client 69.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_70 - CAS cycle count register for client 70.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_71 - CAS cycle count register for client 71.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_72 - CAS cycle count register for client 72.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_73 - CAS cycle count register for client 73.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_74 - CAS cycle count register for client 74.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_75 - CAS cycle count register for client 75.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_76 - CAS cycle count register for client 76.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_77 - CAS cycle count register for client 77.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_78 - CAS cycle count register for client 78.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_79 - CAS cycle count register for client 79.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_80 - CAS cycle count register for client 80.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_81 - CAS cycle count register for client 81.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_82 - CAS cycle count register for client 82.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_83 - CAS cycle count register for client 83.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_84 - CAS cycle count register for client 84.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_85 - CAS cycle count register for client 85.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_86 - CAS cycle count register for client 86.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_87 - CAS cycle count register for client 87.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_88 - CAS cycle count register for client 88.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_89 - CAS cycle count register for client 89.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_90 - CAS cycle count register for client 90.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_91 - CAS cycle count register for client 91.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_92 - CAS cycle count register for client 92.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_93 - CAS cycle count register for client 93.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_94 - CAS cycle count register for client 94.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_95 - CAS cycle count register for client 95.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_96 - CAS cycle count register for client 96.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_97 - CAS cycle count register for client 97.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_98 - CAS cycle count register for client 98.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_99 - CAS cycle count register for client 99.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_100 - CAS cycle count register for client 100.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_101 - CAS cycle count register for client 101.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_102 - CAS cycle count register for client 102.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_103 - CAS cycle count register for client 103.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_104 - CAS cycle count register for client 104.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_105 - CAS cycle count register for client 105.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_106 - CAS cycle count register for client 106.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_107 - CAS cycle count register for client 107.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_108 - CAS cycle count register for client 108.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_109 - CAS cycle count register for client 109.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_110 - CAS cycle count register for client 110.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_111 - CAS cycle count register for client 111.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_112 - CAS cycle count register for client 112.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_113 - CAS cycle count register for client 113.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_114 - CAS cycle count register for client 114.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_115 - CAS cycle count register for client 115.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_116 - CAS cycle count register for client 116.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_117 - CAS cycle count register for client 117.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_118 - CAS cycle count register for client 118.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_119 - CAS cycle count register for client 119.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_120 - CAS cycle count register for client 120.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_121 - CAS cycle count register for client 121.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_122 - CAS cycle count register for client 122.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_123 - CAS cycle count register for client 123.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_124 - CAS cycle count register for client 124.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_125 - CAS cycle count register for client 125.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_126 - CAS cycle count register for client 126.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_127 - CAS cycle count register for client 127.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_DEFAULT             0xffffffff
+
+/***************************************************************************
+ *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT    0xffffffff
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_CONTROL - MEMSYS Auto Init Control.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: reserved0 [31:10] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_MASK    0xfffffc00
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_SHIFT   10
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_DIVIDER [09:09] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_MASK 0x00000200
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_SHIFT 9
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_VDL_CALIB_AUTO_INIT [08:08] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_MASK 0x00000100
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_SHIFT 8
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_DRAM_INIT_DONE_SET [07:07] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_MASK 0x00000080
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_SHIFT 7
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_RESET [06:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_MASK 0x00000040
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_SET [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_READY_SET [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_AUTO_INIT_ACTIVE_RESET [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_MASK 0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_SHIFT 3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: SKIP_PHY_AUTO_INIT [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: MEMSYS_AUTO_INIT_START [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_STATUS - MEMSYS Auto Init Status.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_MASK     0xfffff000
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_SHIFT    12
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMC_AUTO_INIT_STATES [11:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_MASK 0x00000fc0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: AUTO_INIT_ACTIVE [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_STRAP_VALID [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_READY [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_MASK     0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_SHIFT    3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_DEFAULT  0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: DRAM_INIT_DONE [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_FAIL [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHY_VDL_CALIB_AUTO_INIT_OVERRIDE - PHY VDL calibrate override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PHY_VDL_CALIB_AUTO_INIT_OVERRIDE :: PHY_VDL_CALIB_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_DEFAULT 0x10000000
+
+/***************************************************************************
+ *SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE - SHIM PLL pndiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_PNDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_DEFAULT 0x23b00000
+
+/***************************************************************************
+ *SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE - SHIM PLL mdiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_MDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_DEFAULT 0x00001003
+
+/***************************************************************************
+ *DYN_VDL_CMD_DLY - Dynamic VDL shmoo command delay.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_MASK             0xfffff000
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_SHIFT            12
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: END_CAS_DLY [11:06] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_MASK           0x00000fc0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_SHIFT          6
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_DEFAULT        0x00000000
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: START_CAS_DLY [05:00] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_MASK         0x0000003f
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_SHIFT        0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_DEFAULT      0x00000000
+
+#endif /* #ifndef BCHP_MEMC_DDR_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_moca_hostmisc.h b/include/linux/brcmstb/7429b0/bchp_moca_hostmisc.h
new file mode 100644
index 0000000..8e3da02
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_moca_hostmisc.h
@@ -0,0 +1,483 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:14 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MOCA_HOSTMISC_H__
+#define BCHP_MOCA_HOSTMISC_H__
+
+/***************************************************************************
+ *MOCA_HOSTMISC - MOCA_HOSTMISC registers
+ ***************************************************************************/
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL             0x00bffd00 /* Moca Software Reset */
+#define BCHP_MOCA_HOSTMISC_SCRATCH               0x00bffd04 /* Moca Scratch Register */
+#define BCHP_MOCA_HOSTMISC_VERSION               0x00bffd08 /* MoCA version register */
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG          0x00bffd0c /* Host-to-MoCA Interrupt Trigger */
+#define BCHP_MOCA_HOSTMISC_WAKEUP                0x00bffd10 /* Host-to-MoCA Wakeup Interrupt */
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG            0x00bffd14 /* Moca Subsystem configuration */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0      0x00bffd18 /* Host to MoCA MMP outbox registes , register set index 0. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1      0x00bffd1c /* Host to MoCA MMP outbox registes , register set index 1. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2      0x00bffd20 /* Host to MoCA MMP outbox registes , register set index 2. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3      0x00bffd24 /* Host to MoCA MMP outbox registes , register set index 3. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4      0x00bffd28 /* Host to MoCA MMP outbox registes , register set index 4. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5      0x00bffd2c /* Host to MoCA MMP outbox registes , register set index 5. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6      0x00bffd30 /* Host to MoCA MMP outbox registes , register set index 6. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7      0x00bffd34 /* Host to MoCA MMP outbox registes , register set index 7. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8      0x00bffd38 /* Host to MoCA MMP outbox registes , register set index 8. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9      0x00bffd3c /* Host to MoCA MMP outbox registes , register set index 9. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10     0x00bffd40 /* Host to MoCA MMP outbox registes , register set index 10. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11     0x00bffd44 /* Host to MoCA MMP outbox registes , register set index 11. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12     0x00bffd48 /* Host to MoCA MMP outbox registes , register set index 12. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13     0x00bffd4c /* Host to MoCA MMP outbox registes , register set index 13. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14     0x00bffd50 /* Host to MoCA MMP outbox registes , register set index 14. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15     0x00bffd54 /* Host to MoCA MMP outbox registes , register set index 15. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0       0x00bffd58 /* MoCA to Host MMP inbox registers , register set index 0. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1       0x00bffd5c /* MoCA to Host MMP inbox registers , register set index 1. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2       0x00bffd60 /* MoCA to Host MMP inbox registers , register set index 2. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3       0x00bffd64 /* MoCA to Host MMP inbox registers , register set index 3. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4       0x00bffd68 /* MoCA to Host MMP inbox registers , register set index 4. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5       0x00bffd6c /* MoCA to Host MMP inbox registers , register set index 5. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6       0x00bffd70 /* MoCA to Host MMP inbox registers , register set index 6. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7       0x00bffd74 /* MoCA to Host MMP inbox registers , register set index 7. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8       0x00bffd78 /* MoCA to Host MMP inbox registers , register set index 8. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9       0x00bffd7c /* MoCA to Host MMP inbox registers , register set index 9. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10      0x00bffd80 /* MoCA to Host MMP inbox registers , register set index 10. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11      0x00bffd84 /* MoCA to Host MMP inbox registers , register set index 11. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12      0x00bffd88 /* MoCA to Host MMP inbox registers , register set index 12. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13      0x00bffd8c /* MoCA to Host MMP inbox registers , register set index 13. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14      0x00bffd90 /* MoCA to Host MMP inbox registers , register set index 14. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15      0x00bffd94 /* MoCA to Host MMP inbox registers , register set index 15. */
+
+/***************************************************************************
+ *MISC_CTRL - Moca Software Reset
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: MISC_CTRL :: spare_ctrl [31:15] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_ctrl_MASK               0xffff8000
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_ctrl_SHIFT              15
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_ctrl_DEFAULT            0x0001ffff
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: spare_status [14:10] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_status_MASK             0x00007c00
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_status_SHIFT            10
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_status_DEFAULT          0x0000001f
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: spare_reset2 [09:08] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset2_MASK             0x00000300
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset2_SHIFT            8
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset2_DEFAULT          0x00000003
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: moca_disable_clocks [07:07] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_disable_clocks_MASK      0x00000080
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_disable_clocks_SHIFT     7
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_disable_clocks_DEFAULT   0x00000000
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: spare_reset [06:04] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset_MASK              0x00000070
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset_SHIFT             4
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset_DEFAULT           0x00000007
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: moca_gmii_sw_init [03:03] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_gmii_sw_init_MASK        0x00000008
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_gmii_sw_init_SHIFT       3
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_gmii_sw_init_DEFAULT     0x00000000
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: moca_cpu_l_reset [02:02] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_l_reset_MASK         0x00000004
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_l_reset_SHIFT        2
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_l_reset_DEFAULT      0x00000001
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: moca_sys_reset [01:01] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_sys_reset_MASK           0x00000002
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_sys_reset_SHIFT          1
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_sys_reset_DEFAULT        0x00000001
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: moca_cpu_h_reset [00:00] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_h_reset_MASK         0x00000001
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_h_reset_SHIFT        0
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_h_reset_DEFAULT      0x00000001
+
+/***************************************************************************
+ *SCRATCH - Moca Scratch Register
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: SCRATCH :: value [31:00] */
+#define BCHP_MOCA_HOSTMISC_SCRATCH_value_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_SCRATCH_value_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_SCRATCH_value_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *VERSION - MoCA version register
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: VERSION :: moca_id [31:16] */
+#define BCHP_MOCA_HOSTMISC_VERSION_moca_id_MASK                    0xffff0000
+#define BCHP_MOCA_HOSTMISC_VERSION_moca_id_SHIFT                   16
+#define BCHP_MOCA_HOSTMISC_VERSION_moca_id_DEFAULT                 0x00006622
+
+/* MOCA_HOSTMISC :: VERSION :: moca_spec_ver [15:12] */
+#define BCHP_MOCA_HOSTMISC_VERSION_moca_spec_ver_MASK              0x0000f000
+#define BCHP_MOCA_HOSTMISC_VERSION_moca_spec_ver_SHIFT             12
+#define BCHP_MOCA_HOSTMISC_VERSION_moca_spec_ver_DEFAULT           0x00000002
+
+/* MOCA_HOSTMISC :: VERSION :: core_version [11:08] */
+#define BCHP_MOCA_HOSTMISC_VERSION_core_version_MASK               0x00000f00
+#define BCHP_MOCA_HOSTMISC_VERSION_core_version_SHIFT              8
+#define BCHP_MOCA_HOSTMISC_VERSION_core_version_DEFAULT            0x00000003
+
+/* MOCA_HOSTMISC :: VERSION :: core_revision [07:04] */
+#define BCHP_MOCA_HOSTMISC_VERSION_core_revision_MASK              0x000000f0
+#define BCHP_MOCA_HOSTMISC_VERSION_core_revision_SHIFT             4
+#define BCHP_MOCA_HOSTMISC_VERSION_core_revision_DEFAULT           0x00000000
+
+/* MOCA_HOSTMISC :: VERSION :: core_mask [03:00] */
+#define BCHP_MOCA_HOSTMISC_VERSION_core_mask_MASK                  0x0000000f
+#define BCHP_MOCA_HOSTMISC_VERSION_core_mask_SHIFT                 0
+#define BCHP_MOCA_HOSTMISC_VERSION_core_mask_DEFAULT               0x00000000
+
+/***************************************************************************
+ *H2M_INT_TRIG - Host-to-MoCA Interrupt Trigger
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_INT_TRIG :: reserved0 [31:08] */
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_reserved0_MASK             0xffffff00
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_reserved0_SHIFT            8
+
+/* MOCA_HOSTMISC :: H2M_INT_TRIG :: INT_TRIG [07:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_MASK              0x000000ff
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_SHIFT             0
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_DEFAULT           0x00000000
+
+/***************************************************************************
+ *WAKEUP - Host-to-MoCA Wakeup Interrupt
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: WAKEUP :: reserved0 [31:02] */
+#define BCHP_MOCA_HOSTMISC_WAKEUP_reserved0_MASK                   0xfffffffc
+#define BCHP_MOCA_HOSTMISC_WAKEUP_reserved0_SHIFT                  2
+
+/* MOCA_HOSTMISC :: WAKEUP :: cpu_l_wakeup_int [01:01] */
+#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_l_wakeup_int_MASK            0x00000002
+#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_l_wakeup_int_SHIFT           1
+#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_l_wakeup_int_DEFAULT         0x00000000
+
+/* MOCA_HOSTMISC :: WAKEUP :: cpu_h_wakeup_int [00:00] */
+#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_h_wakeup_int_MASK            0x00000001
+#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_h_wakeup_int_SHIFT           0
+#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_h_wakeup_int_DEFAULT         0x00000000
+
+/***************************************************************************
+ *SUBSYS_CFG - Moca Subsystem configuration
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: SUBSYS_CFG :: spare_cfg [31:10] */
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_spare_cfg_MASK               0xfffffc00
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_spare_cfg_SHIFT              10
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_spare_cfg_DEFAULT            0x00000000
+
+/* MOCA_HOSTMISC :: SUBSYS_CFG :: moca_ctl_mem_split_reg [09:07] */
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_ctl_mem_split_reg_MASK  0x00000380
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_ctl_mem_split_reg_SHIFT 7
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_ctl_mem_split_reg_DEFAULT 0x00000004
+
+/* MOCA_HOSTMISC :: SUBSYS_CFG :: moca_cpu_dmem_split_reg [06:04] */
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_cpu_dmem_split_reg_MASK 0x00000070
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_cpu_dmem_split_reg_SHIFT 4
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_cpu_dmem_split_reg_DEFAULT 0x00000002
+
+/* MOCA_HOSTMISC :: SUBSYS_CFG :: moca_cpu_imem_split_reg [03:01] */
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_cpu_imem_split_reg_MASK 0x0000000e
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_cpu_imem_split_reg_SHIFT 1
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_cpu_imem_split_reg_DEFAULT 0x00000002
+
+/* MOCA_HOSTMISC :: SUBSYS_CFG :: moca_arb_rr_sel [00:00] */
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_arb_rr_sel_MASK         0x00000001
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_arb_rr_sel_SHIFT        0
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_arb_rr_sel_DEFAULT      0x00000001
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_0 - Host to MoCA MMP outbox registes , register set index 0.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_0 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_1 - Host to MoCA MMP outbox registes , register set index 1.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_1 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_2 - Host to MoCA MMP outbox registes , register set index 2.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_2 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_3 - Host to MoCA MMP outbox registes , register set index 3.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_3 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_4 - Host to MoCA MMP outbox registes , register set index 4.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_4 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_5 - Host to MoCA MMP outbox registes , register set index 5.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_5 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_6 - Host to MoCA MMP outbox registes , register set index 6.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_6 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_7 - Host to MoCA MMP outbox registes , register set index 7.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_7 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_8 - Host to MoCA MMP outbox registes , register set index 8.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_8 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_9 - Host to MoCA MMP outbox registes , register set index 9.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_9 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_10 - Host to MoCA MMP outbox registes , register set index 10.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_10 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10_m2h_mmp_outbox_MASK   0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10_m2h_mmp_outbox_SHIFT  0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_11 - Host to MoCA MMP outbox registes , register set index 11.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_11 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11_m2h_mmp_outbox_MASK   0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11_m2h_mmp_outbox_SHIFT  0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_12 - Host to MoCA MMP outbox registes , register set index 12.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_12 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12_m2h_mmp_outbox_MASK   0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12_m2h_mmp_outbox_SHIFT  0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_13 - Host to MoCA MMP outbox registes , register set index 13.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_13 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13_m2h_mmp_outbox_MASK   0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13_m2h_mmp_outbox_SHIFT  0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_14 - Host to MoCA MMP outbox registes , register set index 14.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_14 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14_m2h_mmp_outbox_MASK   0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14_m2h_mmp_outbox_SHIFT  0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_15 - Host to MoCA MMP outbox registes , register set index 15.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_15 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15_m2h_mmp_outbox_MASK   0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15_m2h_mmp_outbox_SHIFT  0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_0 - MoCA to Host MMP inbox registers , register set index 0.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_0 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_1 - MoCA to Host MMP inbox registers , register set index 1.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_1 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_2 - MoCA to Host MMP inbox registers , register set index 2.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_2 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_3 - MoCA to Host MMP inbox registers , register set index 3.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_3 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_4 - MoCA to Host MMP inbox registers , register set index 4.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_4 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_5 - MoCA to Host MMP inbox registers , register set index 5.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_5 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_6 - MoCA to Host MMP inbox registers , register set index 6.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_6 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_7 - MoCA to Host MMP inbox registers , register set index 7.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_7 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_8 - MoCA to Host MMP inbox registers , register set index 8.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_8 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_9 - MoCA to Host MMP inbox registers , register set index 9.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_9 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_10 - MoCA to Host MMP inbox registers , register set index 10.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_10 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10_h2m_mmp_inbox_MASK     0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10_h2m_mmp_inbox_SHIFT    0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10_h2m_mmp_inbox_DEFAULT  0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_11 - MoCA to Host MMP inbox registers , register set index 11.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_11 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11_h2m_mmp_inbox_MASK     0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11_h2m_mmp_inbox_SHIFT    0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11_h2m_mmp_inbox_DEFAULT  0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_12 - MoCA to Host MMP inbox registers , register set index 12.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_12 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12_h2m_mmp_inbox_MASK     0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12_h2m_mmp_inbox_SHIFT    0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12_h2m_mmp_inbox_DEFAULT  0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_13 - MoCA to Host MMP inbox registers , register set index 13.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_13 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13_h2m_mmp_inbox_MASK     0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13_h2m_mmp_inbox_SHIFT    0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13_h2m_mmp_inbox_DEFAULT  0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_14 - MoCA to Host MMP inbox registers , register set index 14.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_14 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14_h2m_mmp_inbox_MASK     0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14_h2m_mmp_inbox_SHIFT    0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14_h2m_mmp_inbox_DEFAULT  0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_15 - MoCA to Host MMP inbox registers , register set index 15.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_15 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15_h2m_mmp_inbox_MASK     0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15_h2m_mmp_inbox_SHIFT    0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15_h2m_mmp_inbox_DEFAULT  0x00000000
+
+#endif /* #ifndef BCHP_MOCA_HOSTMISC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_nand.h b/include/linux/brcmstb/7429b0/bchp_nand.h
new file mode 100644
index 0000000..8f6f926
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_nand.h
@@ -0,0 +1,2883 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:16 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_NAND_H__
+#define BCHP_NAND_H__
+
+/***************************************************************************
+ *NAND - Nand Flash Control Registers
+ ***************************************************************************/
+#define BCHP_NAND_REVISION                       0x00412800 /* NAND Revision */
+#define BCHP_NAND_CMD_START                      0x00412804 /* Nand Flash Command Start */
+#define BCHP_NAND_CMD_EXT_ADDRESS                0x00412808 /* Nand Flash Command Extended Address */
+#define BCHP_NAND_CMD_ADDRESS                    0x0041280c /* Nand Flash Command Address */
+#define BCHP_NAND_CMD_END_ADDRESS                0x00412810 /* Nand Flash Command End Address */
+#define BCHP_NAND_INTFC_STATUS                   0x00412814 /* Nand Flash Interface Status */
+#define BCHP_NAND_CS_NAND_SELECT                 0x00412818 /* Nand Flash EBI CS Select */
+#define BCHP_NAND_CS_NAND_XOR                    0x0041281c /* Nand Flash EBI CS Address XOR with 1FC0 Control */
+#define BCHP_NAND_LL_OP                          0x00412820 /* Nand Flash Low Level Operation */
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS        0x00412824 /* Nand Flash Multiplane base address */
+#define BCHP_NAND_MPLANE_BASE_ADDRESS            0x00412828 /* Nand Flash Multiplane base address */
+#define BCHP_NAND_ACC_CONTROL_CS0                0x00412850 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS0                     0x00412854 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS0                   0x00412858 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS0                   0x0041285c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS1                0x00412860 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS1                     0x00412864 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS1                   0x00412868 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS1                   0x0041286c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS2                0x00412870 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS2                     0x00412874 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS2                   0x00412878 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS2                   0x0041287c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS3                0x00412880 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS3                     0x00412884 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS3                   0x00412888 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS3                   0x0041288c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS4                0x00412890 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS4                     0x00412894 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS4                   0x00412898 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS4                   0x0041289c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_CORR_STAT_THRESHOLD            0x004128c0 /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_BLK_WR_PROTECT                 0x004128c8 /* Block Write Protect Enable and Size for EBI_CS0b */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1           0x004128cc /* Nand Flash Multiplane Customerized Opcodes */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2           0x004128d0 /* Nand Flash Multiplane Customerized Opcodes */
+#define BCHP_NAND_MULTIPLANE_CTRL                0x004128d4 /* Nand Flash Multiplane Control */
+#define BCHP_NAND_UNCORR_ERROR_COUNT             0x004128fc /* Read Uncorrectable Event Count */
+#define BCHP_NAND_CORR_ERROR_COUNT               0x00412900 /* Read Error Count */
+#define BCHP_NAND_READ_ERROR_COUNT               0x00412904 /* Read Error Count */
+#define BCHP_NAND_BLOCK_LOCK_STATUS              0x00412908 /* Nand Flash Block Lock Status */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR              0x0041290c /* ECC Correctable Error Extended Address */
+#define BCHP_NAND_ECC_CORR_ADDR                  0x00412910 /* ECC Correctable Error Address */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR               0x00412914 /* ECC Uncorrectable Error Extended Address */
+#define BCHP_NAND_ECC_UNC_ADDR                   0x00412918 /* ECC Uncorrectable Error Address */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR            0x0041291c /* Flash Read Data Extended Address */
+#define BCHP_NAND_FLASH_READ_ADDR                0x00412920 /* Flash Read Data Address */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR          0x00412924 /* Page Program Extended Address */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR              0x00412928 /* Page Program Address */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR             0x0041292c /* Copy Back Extended Address */
+#define BCHP_NAND_COPY_BACK_ADDR                 0x00412930 /* Copy Back Address */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR           0x00412934 /* Block Erase Extended Address */
+#define BCHP_NAND_BLOCK_ERASE_ADDR               0x00412938 /* Block Erase Address */
+#define BCHP_NAND_INV_READ_EXT_ADDR              0x0041293c /* Flash Invalid Data Extended Address */
+#define BCHP_NAND_INV_READ_ADDR                  0x00412940 /* Flash Invalid Data Address */
+#define BCHP_NAND_INIT_STATUS                    0x00412944 /* Initialization status */
+#define BCHP_NAND_ONFI_STATUS                    0x00412948 /* ONFI Status */
+#define BCHP_NAND_ONFI_DEBUG_DATA                0x0041294c /* ONFI Debug Data */
+#define BCHP_NAND_SEMAPHORE                      0x00412950 /* Semaphore */
+#define BCHP_NAND_FLASH_DEVICE_ID                0x00412994 /* Nand Flash Device ID */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT            0x00412998 /* Nand Flash Extended Device ID */
+#define BCHP_NAND_LL_RDDATA                      0x0041299c /* Nand Flash Low Level Read Data */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0          0x00412a00 /* Nand Flash Spare Area Read Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4          0x00412a04 /* Nand Flash Spare Area Read Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8          0x00412a08 /* Nand Flash Spare Area Read Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C          0x00412a0c /* Nand Flash Spare Area Read Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10         0x00412a10 /* Nand Flash Spare Area Read Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14         0x00412a14 /* Nand Flash Spare Area Read Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18         0x00412a18 /* Nand Flash Spare Area Read Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C         0x00412a1c /* Nand Flash Spare Area Read Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20         0x00412a20 /* Nand Flash Spare Area Read Bytes 32-35 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24         0x00412a24 /* Nand Flash Spare Area Read Bytes 36-39 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28         0x00412a28 /* Nand Flash Spare Area Read Bytes 40-43 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C         0x00412a2c /* Nand Flash Spare Area Read Bytes 44-47 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30         0x00412a30 /* Nand Flash Spare Area Read Bytes 48-51 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34         0x00412a34 /* Nand Flash Spare Area Read Bytes 52-55 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38         0x00412a38 /* Nand Flash Spare Area Read Bytes 56-59 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C         0x00412a3c /* Nand Flash Spare Area Read Bytes 60-63 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0         0x00412a80 /* Nand Flash Spare Area Write Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4         0x00412a84 /* Nand Flash Spare Area Write Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8         0x00412a88 /* Nand Flash Spare Area Write Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C         0x00412a8c /* Nand Flash Spare Area Write Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10        0x00412a90 /* Nand Flash Spare Area Write Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14        0x00412a94 /* Nand Flash Spare Area Write Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18        0x00412a98 /* Nand Flash Spare Area Write Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C        0x00412a9c /* Nand Flash Spare Area Write Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20        0x00412aa0 /* Nand Flash Spare Area Write Bytes 32-35 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24        0x00412aa4 /* Nand Flash Spare Area Write Bytes 36-39 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28        0x00412aa8 /* Nand Flash Spare Area Write Bytes 40-43 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C        0x00412aac /* Nand Flash Spare Area Write Bytes 44-47 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30        0x00412ab0 /* Nand Flash Spare Area Write Bytes 48-51 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34        0x00412ab4 /* Nand Flash Spare Area Write Bytes 52-55 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38        0x00412ab8 /* Nand Flash Spare Area Write Bytes 56-59 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C        0x00412abc /* Nand Flash Spare Area Write Bytes 60-63 */
+
+/***************************************************************************
+ *REVISION - NAND Revision
+ ***************************************************************************/
+/* NAND :: REVISION :: 8KB_PAGE_SUPPORT [31:31] */
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_MASK                   0x80000000
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_SHIFT                  31
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_DEFAULT                0x00000001
+
+/* NAND :: REVISION :: reserved0 [30:16] */
+#define BCHP_NAND_REVISION_reserved0_MASK                          0x7fff0000
+#define BCHP_NAND_REVISION_reserved0_SHIFT                         16
+
+/* NAND :: REVISION :: MAJOR [15:08] */
+#define BCHP_NAND_REVISION_MAJOR_MASK                              0x0000ff00
+#define BCHP_NAND_REVISION_MAJOR_SHIFT                             8
+#define BCHP_NAND_REVISION_MAJOR_DEFAULT                           0x00000006
+
+/* NAND :: REVISION :: MINOR [07:00] */
+#define BCHP_NAND_REVISION_MINOR_MASK                              0x000000ff
+#define BCHP_NAND_REVISION_MINOR_SHIFT                             0
+#define BCHP_NAND_REVISION_MINOR_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *CMD_START - Nand Flash Command Start
+ ***************************************************************************/
+/* NAND :: CMD_START :: reserved0 [31:29] */
+#define BCHP_NAND_CMD_START_reserved0_MASK                         0xe0000000
+#define BCHP_NAND_CMD_START_reserved0_SHIFT                        29
+
+/* NAND :: CMD_START :: OPCODE [28:24] */
+#define BCHP_NAND_CMD_START_OPCODE_MASK                            0x1f000000
+#define BCHP_NAND_CMD_START_OPCODE_SHIFT                           24
+#define BCHP_NAND_CMD_START_OPCODE_DEFAULT                         0x00000000
+#define BCHP_NAND_CMD_START_OPCODE_NULL                            0
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ                       1
+#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ                 2
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ                     3
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE                    4
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA              5
+#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK                       6
+#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ                  7
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE                     8
+#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET                     9
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK                     10
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN                11
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK                   12
+#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS         13
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ                  14
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL            15
+#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP                    16
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ_MULTI                 17
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ_MULTI               18
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE_MULTI              19
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE_MULTI_CACHE        20
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE_MULTI               21
+
+/* NAND :: CMD_START :: reserved1 [23:00] */
+#define BCHP_NAND_CMD_START_reserved1_MASK                         0x00ffffff
+#define BCHP_NAND_CMD_START_reserved1_SHIFT                        0
+
+/***************************************************************************
+ *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
+ ***************************************************************************/
+/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK                   0xfff80000
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT                  19
+
+/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK                      0x00070000
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT                     16
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT                   0x00000000
+
+/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK                 0x0000ffff
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT                0
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CMD_ADDRESS - Nand Flash Command Address
+ ***************************************************************************/
+/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK                         0xffffffff
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT                        0
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *CMD_END_ADDRESS - Nand Flash Command End Address
+ ***************************************************************************/
+/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT                    0
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *INTFC_STATUS - Nand Flash Interface Status
+ ***************************************************************************/
+/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK                     0x80000000
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT                    31
+
+/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK                    0x40000000
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT                   30
+
+/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK                    0x20000000
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT                   29
+
+/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK               0x10000000
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT              28
+
+/* NAND :: INTFC_STATUS :: ERASED [27:27] */
+#define BCHP_NAND_INTFC_STATUS_ERASED_MASK                         0x08000000
+#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT                        27
+
+/* NAND :: INTFC_STATUS :: PLANE_READY [26:26] */
+#define BCHP_NAND_INTFC_STATUS_PLANE_READY_MASK                    0x04000000
+#define BCHP_NAND_INTFC_STATUS_PLANE_READY_SHIFT                   26
+
+/* NAND :: INTFC_STATUS :: reserved0 [25:08] */
+#define BCHP_NAND_INTFC_STATUS_reserved0_MASK                      0x03ffff00
+#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT                     8
+
+/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK                   0x000000ff
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT                  0
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *CS_NAND_SELECT - Nand Flash EBI CS Select
+ ***************************************************************************/
+/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT                     31
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK        0x40000000
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT       30
+
+/* NAND :: CS_NAND_SELECT :: reserved0 [29:29] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK                    0x20000000
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT                   29
+
+/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK              0x10000000
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT             28
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT           0x00000000
+
+/* NAND :: CS_NAND_SELECT :: reserved1 [27:16] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_MASK                    0x0fff0000
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_SHIFT                   16
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK           0x00008000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT          15
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK           0x00004000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT          14
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK           0x00002000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT          13
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK           0x00001000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT          12
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK           0x00000800
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT          11
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK           0x00000400
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT          10
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK           0x00000200
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT          9
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK           0x00000100
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT          8
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK                 0x00000080
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT                7
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK                 0x00000040
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT                6
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK                 0x00000020
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT                5
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK                 0x00000010
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT                4
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK                 0x00000008
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT                3
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK                 0x00000004
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT                2
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK                 0x00000002
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT                1
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK                 0x00000001
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT                0
+
+/***************************************************************************
+ *CS_NAND_XOR - Nand Flash EBI CS Address XOR with 1FC0 Control
+ ***************************************************************************/
+/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_1FC0_XOR [31:31] */
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_MASK           0x80000000
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_SHIFT          31
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
+#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK                       0x7fffff00
+#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT                      8
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_1FC0_XOR [07:07] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_MASK          0x00000080
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_SHIFT         7
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_1FC0_XOR [06:06] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_MASK          0x00000040
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_SHIFT         6
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_1FC0_XOR [05:05] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_MASK          0x00000020
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_SHIFT         5
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_1FC0_XOR [04:04] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_MASK          0x00000010
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_SHIFT         4
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_1FC0_XOR [03:03] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_MASK          0x00000008
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_SHIFT         3
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_1FC0_XOR [02:02] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_MASK          0x00000004
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_SHIFT         2
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_1FC0_XOR [01:01] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_MASK          0x00000002
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_SHIFT         1
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_1FC0_XOR [00:00] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_MASK          0x00000001
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_SHIFT         0
+
+/***************************************************************************
+ *LL_OP - Nand Flash Low Level Operation
+ ***************************************************************************/
+/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
+#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK                           0x80000000
+#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT                          31
+#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT                        0x00000000
+
+/* NAND :: LL_OP :: reserved0 [30:20] */
+#define BCHP_NAND_LL_OP_reserved0_MASK                             0x7ff00000
+#define BCHP_NAND_LL_OP_reserved0_SHIFT                            20
+
+/* NAND :: LL_OP :: CLE [19:19] */
+#define BCHP_NAND_LL_OP_CLE_MASK                                   0x00080000
+#define BCHP_NAND_LL_OP_CLE_SHIFT                                  19
+#define BCHP_NAND_LL_OP_CLE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: ALE [18:18] */
+#define BCHP_NAND_LL_OP_ALE_MASK                                   0x00040000
+#define BCHP_NAND_LL_OP_ALE_SHIFT                                  18
+#define BCHP_NAND_LL_OP_ALE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: WE [17:17] */
+#define BCHP_NAND_LL_OP_WE_MASK                                    0x00020000
+#define BCHP_NAND_LL_OP_WE_SHIFT                                   17
+#define BCHP_NAND_LL_OP_WE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: RE [16:16] */
+#define BCHP_NAND_LL_OP_RE_MASK                                    0x00010000
+#define BCHP_NAND_LL_OP_RE_SHIFT                                   16
+#define BCHP_NAND_LL_OP_RE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: DATA [15:00] */
+#define BCHP_NAND_LL_OP_DATA_MASK                                  0x0000ffff
+#define BCHP_NAND_LL_OP_DATA_SHIFT                                 0
+#define BCHP_NAND_LL_OP_DATA_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *MPLANE_BASE_EXT_ADDRESS - Nand Flash Multiplane base address
+ ***************************************************************************/
+/* NAND :: MPLANE_BASE_EXT_ADDRESS :: reserved0 [31:16] */
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_reserved0_MASK           0xffff0000
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_reserved0_SHIFT          16
+
+/* NAND :: MPLANE_BASE_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_MASK         0x0000ffff
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_SHIFT        0
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_DEFAULT      0x00000000
+
+/***************************************************************************
+ *MPLANE_BASE_ADDRESS - Nand Flash Multiplane base address
+ ***************************************************************************/
+/* NAND :: MPLANE_BASE_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_MASK                 0xffffffff
+#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_SHIFT                0
+#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *ACC_CONTROL_CS0 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS0 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS0_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS0_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS0_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: CACHE_MODE_LAST_PAGE [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_LAST_PAGE_MASK        0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_LAST_PAGE_SHIFT       21
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_LAST_PAGE_DEFAULT     0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS0 :: reserved0 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved0_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved0_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS0 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS0 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS0 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS0 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_512KB              4
+#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_256KB              3
+#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_128KB              2
+#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_16KB               1
+#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_8KB                0
+
+/* NAND :: CONFIG_CS0 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS0 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS0 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS0_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS0_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS0 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS0 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS0_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS0_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS0 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS0_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS0_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS0 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS0_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS0_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS0 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS0_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS0_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS0 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS0_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS0_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS0 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS0_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS0_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS0 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS0_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS0_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS0 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS0 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS0_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS0_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS0_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS0 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS0_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS0_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS0_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS0 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS0_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS0_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS0_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS0 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS0_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS0_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS0_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS0 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS0_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS0_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS0_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS0 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS0_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS0_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS0_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS0 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS0_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS0_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS0_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS0 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS0_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS0_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS0_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS0 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS0 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS0 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS0_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS0_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS0 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS0_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS0_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS0_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS0 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS0_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS0_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS0_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS0 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS0_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS0_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS0_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS1 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: CACHE_MODE_LAST_PAGE [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_LAST_PAGE_MASK        0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_LAST_PAGE_SHIFT       21
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_LAST_PAGE_DEFAULT     0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved0 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS1 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS1 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_512KB              4
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_256KB              3
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_128KB              2
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_16KB               1
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_8KB                0
+
+/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS1 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS1_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS1 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS1 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS1_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS1_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS1_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS1_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS1_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS1_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS1_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS1_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS1_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS1_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS1_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS1 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS1 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS1_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS2 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: CACHE_MODE_LAST_PAGE [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_LAST_PAGE_MASK        0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_LAST_PAGE_SHIFT       21
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_LAST_PAGE_DEFAULT     0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved0 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS2 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS2 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_512KB              4
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_256KB              3
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_128KB              2
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_16KB               1
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_8KB                0
+
+/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS2 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS2_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS2 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS2 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS2_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS2_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS2_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS2_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS2 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS2_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS2_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS2_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS2_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS2_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS2_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS2_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS2_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS3 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: CACHE_MODE_LAST_PAGE [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_LAST_PAGE_MASK        0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_LAST_PAGE_SHIFT       21
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_LAST_PAGE_DEFAULT     0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved0 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS3 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS3 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_512KB              4
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_256KB              3
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_128KB              2
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_16KB               1
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_8KB                0
+
+/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS3 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS3_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS3 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS3 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS3_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS3_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS3_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS3_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS3 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS3_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS3_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS3_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS3_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS3_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS3_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS3_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS3 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS3 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS3_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS4 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: CACHE_MODE_LAST_PAGE [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_LAST_PAGE_MASK        0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_LAST_PAGE_SHIFT       21
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_LAST_PAGE_DEFAULT     0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved0 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS4 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS4 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_512KB              4
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_256KB              3
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_128KB              2
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_16KB               1
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_8KB                0
+
+/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS4 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS4_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS4 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS4 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS4_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS4_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS4_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS4_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS4 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS4_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS4_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS4_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS4_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS4_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS4_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS4_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS4 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS4 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS4_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:30] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK               0xc0000000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT              30
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS4 [29:24] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_MASK 0x3f000000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_SHIFT 24
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS3 [23:18] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_MASK 0x00fc0000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_SHIFT 18
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS2 [17:12] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_MASK 0x0003f000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_SHIFT 12
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS1 [11:06] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_MASK 0x00000fc0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_SHIFT 6
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS0 [05:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_MASK 0x0000003f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_SHIFT 0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_DEFAULT 0x00000001
+
+/***************************************************************************
+ *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
+ ***************************************************************************/
+/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK                 0xffffffff
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT                0
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *MULTIPLANE_OPCODES_1 - Nand Flash Multiplane Customerized Opcodes
+ ***************************************************************************/
+/* NAND :: MULTIPLANE_OPCODES_1 :: ERASE_CYC2_OPCODE [31:24] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_MASK      0xff000000
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_SHIFT     24
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_DEFAULT   0x000000d1
+
+/* NAND :: MULTIPLANE_OPCODES_1 :: READ_STATUS_OPCODE [23:16] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_MASK     0x00ff0000
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_SHIFT    16
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_DEFAULT  0x00000070
+
+/* NAND :: MULTIPLANE_OPCODES_1 :: PROG_ODD_PLANE_OPCODE [15:08] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_MASK  0x0000ff00
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_SHIFT 8
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_DEFAULT 0x00000080
+
+/* NAND :: MULTIPLANE_OPCODES_1 :: PROG_TR_OPCODE [07:00] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_MASK         0x000000ff
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_SHIFT        0
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_DEFAULT      0x00000010
+
+/***************************************************************************
+ *MULTIPLANE_OPCODES_2 - Nand Flash Multiplane Customerized Opcodes
+ ***************************************************************************/
+/* NAND :: MULTIPLANE_OPCODES_2 :: PROG_CACHE_TR_OPCODE [31:24] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_MASK   0xff000000
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_SHIFT  24
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_DEFAULT 0x00000015
+
+/* NAND :: MULTIPLANE_OPCODES_2 :: TWO_PLANE_READ_STATUS_OPCODE [23:16] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_MASK 0x00ff0000
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_SHIFT 16
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_DEFAULT 0x00000078
+
+/* NAND :: MULTIPLANE_OPCODES_2 :: READ_OPCODE [15:08] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_MASK            0x0000ff00
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_SHIFT           8
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_DEFAULT         0x00000000
+
+/* NAND :: MULTIPLANE_OPCODES_2 :: READ_RAND_OPCODE [07:00] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_MASK       0x000000ff
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_SHIFT      0
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *MULTIPLANE_CTRL - Nand Flash Multiplane Control
+ ***************************************************************************/
+/* NAND :: MULTIPLANE_CTRL :: ERASE_CYC2_OP_ENABLE [31:31] */
+#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_MASK        0x80000000
+#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_SHIFT       31
+#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_DEFAULT     0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: READ_ADR_SIZE [30:30] */
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_MASK               0x40000000
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_SHIFT              30
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_DEFAULT            0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: READ_CYC_ADR_FLAG [29:29] */
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_MASK           0x20000000
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_SHIFT          29
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_DEFAULT        0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: READ_NEXT_PAGE_FLAG [28:28] */
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_MASK         0x10000000
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_SHIFT        28
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_DEFAULT      0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: reserved0 [27:00] */
+#define BCHP_NAND_MULTIPLANE_CTRL_reserved0_MASK                   0x0fffffff
+#define BCHP_NAND_MULTIPLANE_CTRL_reserved0_SHIFT                  0
+
+/***************************************************************************
+ *UNCORR_ERROR_COUNT - Read Uncorrectable Event Count
+ ***************************************************************************/
+/* NAND :: UNCORR_ERROR_COUNT :: UNCORR_ERROR_COUNT [31:00] */
+#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_MASK       0xffffffff
+#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_SHIFT      0
+#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *CORR_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: CORR_ERROR_COUNT :: CORR_ERROR_COUNT [31:00] */
+#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *READ_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
+ ***************************************************************************/
+/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT                8
+
+/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK                    0x000000ff
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT                   0
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ECC_CORR_ADDR - ECC Correctable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK                  0xfff80000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT                 19
+
+/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK                     0x00070000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT                    16
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT                  0x00000000
+
+/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK                0x0000ffff
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT               0
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT             0x00000000
+
+/***************************************************************************
+ *ECC_UNC_ADDR - ECC Uncorrectable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK                        0xffffffff
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT                       0
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK               0xfff80000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT              19
+
+/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK                  0x00070000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT                 16
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT               0x00000000
+
+/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK             0x0000ffff
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT            0
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT          0x00000000
+
+/***************************************************************************
+ *FLASH_READ_ADDR - Flash Read Data Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT                    0
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK             0xfff80000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT            19
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK                0x00070000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT               16
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT             0x00000000
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK           0x0000ffff
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT          0
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_ADDR - Page Program Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK                   0xffffffff
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT                  0
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *COPY_BACK_EXT_ADDR - Copy Back Extended Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK                0xfff80000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT               19
+
+/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK                   0x00070000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT                  16
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT                0x00000000
+
+/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK              0x0000ffff
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT             0
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT           0x00000000
+
+/***************************************************************************
+ *COPY_BACK_ADDR - Copy Back Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK                      0xffffffff
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT                     0
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK              0xfff80000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT             19
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK                 0x00070000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT                16
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT              0x00000000
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK            0x0000ffff
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT           0
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_ADDR - Block Erase Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK                    0xffffffff
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT                   0
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
+ ***************************************************************************/
+/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *INV_READ_ADDR - Flash Invalid Data Address
+ ***************************************************************************/
+/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *INIT_STATUS - Initialization status
+ ***************************************************************************/
+/* NAND :: INIT_STATUS :: ONFI_INIT_DONE [31:31] */
+#define BCHP_NAND_INIT_STATUS_ONFI_INIT_DONE_MASK                  0x80000000
+#define BCHP_NAND_INIT_STATUS_ONFI_INIT_DONE_SHIFT                 31
+
+/* NAND :: INIT_STATUS :: DEVICE_ID_INIT_DONE [30:30] */
+#define BCHP_NAND_INIT_STATUS_DEVICE_ID_INIT_DONE_MASK             0x40000000
+#define BCHP_NAND_INIT_STATUS_DEVICE_ID_INIT_DONE_SHIFT            30
+
+/* NAND :: INIT_STATUS :: INIT_SUCCESS [29:29] */
+#define BCHP_NAND_INIT_STATUS_INIT_SUCCESS_MASK                    0x20000000
+#define BCHP_NAND_INIT_STATUS_INIT_SUCCESS_SHIFT                   29
+
+/* NAND :: INIT_STATUS :: INIT_FAIL [28:28] */
+#define BCHP_NAND_INIT_STATUS_INIT_FAIL_MASK                       0x10000000
+#define BCHP_NAND_INIT_STATUS_INIT_FAIL_SHIFT                      28
+
+/* NAND :: INIT_STATUS :: INIT_BLANK [27:27] */
+#define BCHP_NAND_INIT_STATUS_INIT_BLANK_MASK                      0x08000000
+#define BCHP_NAND_INIT_STATUS_INIT_BLANK_SHIFT                     27
+
+/* NAND :: INIT_STATUS :: INIT_TIMEOUT [26:26] */
+#define BCHP_NAND_INIT_STATUS_INIT_TIMEOUT_MASK                    0x04000000
+#define BCHP_NAND_INIT_STATUS_INIT_TIMEOUT_SHIFT                   26
+
+/* NAND :: INIT_STATUS :: INIT_UNC_ERROR [25:25] */
+#define BCHP_NAND_INIT_STATUS_INIT_UNC_ERROR_MASK                  0x02000000
+#define BCHP_NAND_INIT_STATUS_INIT_UNC_ERROR_SHIFT                 25
+
+/* NAND :: INIT_STATUS :: INIT_CORR_ERROR [24:24] */
+#define BCHP_NAND_INIT_STATUS_INIT_CORR_ERROR_MASK                 0x01000000
+#define BCHP_NAND_INIT_STATUS_INIT_CORR_ERROR_SHIFT                24
+
+/* NAND :: INIT_STATUS :: PARAMETER_READY [23:23] */
+#define BCHP_NAND_INIT_STATUS_PARAMETER_READY_MASK                 0x00800000
+#define BCHP_NAND_INIT_STATUS_PARAMETER_READY_SHIFT                23
+
+/* NAND :: INIT_STATUS :: AUTHENTICATION_FAIL [22:22] */
+#define BCHP_NAND_INIT_STATUS_AUTHENTICATION_FAIL_MASK             0x00400000
+#define BCHP_NAND_INIT_STATUS_AUTHENTICATION_FAIL_SHIFT            22
+
+/* NAND :: INIT_STATUS :: reserved0 [21:00] */
+#define BCHP_NAND_INIT_STATUS_reserved0_MASK                       0x003fffff
+#define BCHP_NAND_INIT_STATUS_reserved0_SHIFT                      0
+
+/***************************************************************************
+ *ONFI_STATUS - ONFI Status
+ ***************************************************************************/
+/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK                  0xf0000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT                 28
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT               0x00000000
+
+/* NAND :: ONFI_STATUS :: ONFI_detected [27:27] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_detected_MASK                   0x08000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_detected_SHIFT                  27
+
+/* NAND :: ONFI_STATUS :: reserved0 [26:06] */
+#define BCHP_NAND_ONFI_STATUS_reserved0_MASK                       0x07ffffc0
+#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT                      6
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK              0x00000020
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT             5
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK              0x00000010
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT             4
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK              0x00000008
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT             3
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK              0x00000004
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT             2
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK              0x00000002
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT             1
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK              0x00000001
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT             0
+
+/***************************************************************************
+ *ONFI_DEBUG_DATA - ONFI Debug Data
+ ***************************************************************************/
+/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK             0xffffffff
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT            0
+
+/***************************************************************************
+ *SEMAPHORE - Semaphore
+ ***************************************************************************/
+/* NAND :: SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_NAND_SEMAPHORE_reserved0_MASK                         0xffffff00
+#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT                        8
+
+/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK                    0x000000ff
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT                   0
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *FLASH_DEVICE_ID - Nand Flash Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK                      0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT                     24
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK                      0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT                     16
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK                      0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT                     8
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK                      0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT                     0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK                  0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT                 24
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK                  0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT                 16
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK                  0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT                 8
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK                  0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT                 0
+
+/***************************************************************************
+ *LL_RDDATA - Nand Flash Low Level Read Data
+ ***************************************************************************/
+/* NAND :: LL_RDDATA :: reserved0 [31:16] */
+#define BCHP_NAND_LL_RDDATA_reserved0_MASK                         0xffff0000
+#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT                        16
+
+/* NAND :: LL_RDDATA :: DATA [15:00] */
+#define BCHP_NAND_LL_RDDATA_DATA_MASK                              0x0000ffff
+#define BCHP_NAND_LL_RDDATA_DATA_SHIFT                             0
+#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_20 - Nand Flash Spare Area Read Bytes 32-35
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_32 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_33 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_34 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_35 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_24 - Nand Flash Spare Area Read Bytes 36-39
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_36 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_37 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_38 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_39 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_28 - Nand Flash Spare Area Read Bytes 40-43
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_40 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_41 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_42 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_43 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_2C - Nand Flash Spare Area Read Bytes 44-47
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_44 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_45 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_46 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_47 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_30 - Nand Flash Spare Area Read Bytes 48-51
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_48 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_49 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_50 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_51 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_34 - Nand Flash Spare Area Read Bytes 52-55
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_52 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_53 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_54 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_55 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_38 - Nand Flash Spare Area Read Bytes 56-59
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_56 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_57 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_58 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_59 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_3C - Nand Flash Spare Area Read Bytes 60-63
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_60 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_61 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_62 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_63 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_20 - Nand Flash Spare Area Write Bytes 32-35
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_32 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_33 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_34 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_35 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_24 - Nand Flash Spare Area Write Bytes 36-39
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_36 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_37 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_38 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_39 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_28 - Nand Flash Spare Area Write Bytes 40-43
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_40 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_41 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_42 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_43 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_2C - Nand Flash Spare Area Write Bytes 44-47
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_44 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_45 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_46 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_47 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_30 - Nand Flash Spare Area Write Bytes 48-51
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_48 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_49 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_50 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_51 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_34 - Nand Flash Spare Area Write Bytes 52-55
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_52 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_53 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_54 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_55 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_38 - Nand Flash Spare Area Write Bytes 56-59
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_56 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_57 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_58 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_59 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_3C - Nand Flash Spare Area Write Bytes 60-63
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_60 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_61 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_62 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_63 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE                          0x00412c00
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_START                         0
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_END                           127
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE                  32
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+/* NAND :: FLASH_CACHEi :: WORD [31:00] */
+#define BCHP_NAND_FLASH_CACHEi_WORD_MASK                           0xffffffff
+#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT                          0
+
+
+#endif /* #ifndef BCHP_NAND_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_sata_top_ctrl.h b/include/linux/brcmstb/7429b0/bchp_sata_top_ctrl.h
new file mode 100644
index 0000000..3b7e345
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_sata_top_ctrl.h
@@ -0,0 +1,161 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:17 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SATA_TOP_CTRL_H__
+#define BCHP_SATA_TOP_CTRL_H__
+
+/***************************************************************************
+ *SATA_TOP_CTRL - SATA3 MISC Control Registers
+ ***************************************************************************/
+#define BCHP_SATA_TOP_CTRL_Version               0x00180020 /* SATA3 Version Register */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL              0x00180024 /* SATA3 System Bus Access Control Register */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL               0x00180028 /* SATA3 Test Port Control register */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1            0x0018002c /* SATA3 phy interface control 1 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2            0x00180030 /* SATA3 phy interface control 2 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3            0x00180034 /* SATA3 phy interface control 3 */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT           0x00180038 /* SATA3 TP OUT */
+
+/***************************************************************************
+ *Version - SATA3 Version Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: Version :: reserved0 [31:08] */
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_MASK                  0xffffff00
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_SHIFT                 8
+
+/* SATA_TOP_CTRL :: Version :: major_version [07:04] */
+#define BCHP_SATA_TOP_CTRL_Version_major_version_MASK              0x000000f0
+#define BCHP_SATA_TOP_CTRL_Version_major_version_SHIFT             4
+#define BCHP_SATA_TOP_CTRL_Version_major_version_DEFAULT           0x00000000
+
+/* SATA_TOP_CTRL :: Version :: minor_version [03:00] */
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_MASK              0x0000000f
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_SHIFT             0
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_DEFAULT           0x00000001
+
+/***************************************************************************
+ *BUS_CTRL - SATA3 System Bus Access Control Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_31_17 [31:17] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_MASK            0xfffe0000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_SHIFT           17
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_DEFAULT         0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: overide_hwinit_registers [16:16] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_MASK  0x00010000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_SHIFT 16
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_DEFAULT 0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_15_8 [15:08] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_MASK             0x0000ff00
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_SHIFT            8
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_DEFAULT          0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: piodata_endian_ctrl [07:06] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_MASK       0x000000c0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SHIFT      6
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadata_endian_ctrl [05:04] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_MASK       0x00000030
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SHIFT      4
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadesc_endian_ctrl [03:02] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_MASK       0x0000000c
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SHIFT      2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: reg_endian_ctrl [01:00] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_MASK           0x00000003
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SHIFT          0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_DEFAULT        0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SwapEndianess  2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_HalfWordSwap   1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_NoSwap         0
+
+/***************************************************************************
+ *TP_CTRL - SATA3 Test Port Control register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: TP_CTRL :: tp_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_MASK                    0xffffffff
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_SHIFT                   0
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_1 - SATA3 phy interface control 1
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_1 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_2 - SATA3 phy interface control 2
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_2 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_3 - SATA3 phy interface control 3
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_3 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *SATA_TP_OUT - SATA3 TP OUT
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: SATA_TP_OUT :: TP_OUT [31:00] */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_MASK                 0xffffffff
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_SHIFT                0
+
+#endif /* #ifndef BCHP_SATA_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_sdio_0_cfg.h b/include/linux/brcmstb/7429b0/bchp_sdio_0_cfg.h
new file mode 100644
index 0000000..71ff23a
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_sdio_0_cfg.h
@@ -0,0 +1,635 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:17 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SDIO_0_CFG_H__
+#define BCHP_SDIO_0_CFG_H__
+
+/***************************************************************************
+ *SDIO_0_CFG - SDIO (CARD) Configuration Registers
+ ***************************************************************************/
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1          0x00413600 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2          0x00413604 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL               0x00413608 /* SDIO TP_OUT Control Register */
+#define BCHP_SDIO_0_CFG_CAP_REG0                 0x0041360c /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_CAP_REG1                 0x00413610 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET1                  0x00413614 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET2                  0x00413618 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY           0x0041361c /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV               0x00413620 /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_IP_DLY                   0x00413630 /* SDIO Host input delay register */
+#define BCHP_SDIO_0_CFG_OP_DLY                   0x00413634 /* SDIO Host output delay register */
+#define BCHP_SDIO_0_CFG_TUNING                   0x00413638 /* SDIO Host tuning configuration register */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL                0x0041363c /* SDIO Host 1p8V control logic select register */
+#define BCHP_SDIO_0_CFG_SCRATCH                  0x004136fc /* SDIO Scratch Register */
+#define BCHP_SDIO_0_CFG_VERSION                  0x004136f0 /* SDIO VERSION Register */
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL1 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_SEL_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_MASK    0x80000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_SHIFT   31
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_DEFAULT 0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_LEV [30:30] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_MASK       0x40000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_SHIFT      30
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved0 [29:29] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved0_MASK             0x20000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved0_SHIFT            29
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: RETUNING_REQ [28:28] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_MASK          0x10000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_SHIFT         28
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DDR_TAP_DELAY [27:24] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_MASK         0x0f000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_SHIFT        24
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_DEFAULT      0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DELAY_CTRL [23:21] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_MASK            0x00e00000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_SHIFT           21
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_DEFAULT         0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_ENA [20:20] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_MASK       0x00100000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_SHIFT      20
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_PULSE [19:19] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_MASK     0x00080000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_SHIFT    19
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DATA_PENDING [18:18] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_MASK          0x00040000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_SHIFT         18
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WR_FLUSH [17:17] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_MASK              0x00020000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_SHIFT             17
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: MF_NUM_WR [16:16] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_MASK             0x00010000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_SHIFT            16
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WORD_ABO [15:15] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_MASK              0x00008000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_SHIFT             15
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NBO [14:14] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_MASK             0x00004000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_SHIFT            14
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NHW [13:13] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_MASK             0x00002000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_SHIFT            13
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: BUFFER_ABO [12:12] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_MASK            0x00001000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_SHIFT           12
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_DEFAULT         0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_BUF_ACC [11:11] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_MASK           0x00000800
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_SHIFT          11
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_DEFAULT        0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SEQ_EN [10:10] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_MASK            0x00000400
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_SHIFT           10
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_DEFAULT         0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_RD_THRESH [09:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_MASK         0x000003e0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_SHIFT        5
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_DEFAULT      0x00000002
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SIZE [04:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_MASK              0x0000001f
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_SHIFT             0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_DEFAULT           0x00000004
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL2 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved0 [31:08] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_MASK             0xffffff00
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_SHIFT            8
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_BYTE [07:06] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_MASK     0x000000c0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_SHIFT    6
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved1 [05:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_MASK             0x00000020
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_SHIFT            5
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_HW [04:04] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_MASK       0x00000010
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_SHIFT      4
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_DEFAULT    0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_RD [03:02] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_MASK      0x0000000c
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_SHIFT     2
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_DEFAULT   0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_WR [01:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_MASK      0x00000003
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_SHIFT     0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_DEFAULT   0x00000000
+
+/***************************************************************************
+ *TP_OUT_SEL - SDIO TP_OUT Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TP_OUT_SEL :: reserved0 [31:01] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_MASK                  0xfffffffe
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_SHIFT                 1
+
+/* SDIO_0_CFG :: TP_OUT_SEL :: TP_OUT_SELECT [00:00] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_MASK              0x00000001
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_SHIFT             0
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *CAP_REG0 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG0 :: DDR50_SUPPORT [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_SHIFT               31
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_DEFAULT             0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SD104_SUPPORT [30:30] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_MASK                0x40000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_SHIFT               30
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDR50 [29:29] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_MASK                        0x20000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_SHIFT                       29
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_DEFAULT                     0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SLOT_TYPE [28:27] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_MASK                    0x18000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_SHIFT                   27
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_DEFAULT                 0x00000002
+
+/* SDIO_0_CFG :: CAP_REG0 :: ASYNCH_INT_SUPPORT [26:26] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_MASK           0x04000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_SHIFT          26
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_DEFAULT        0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 64B_SYS_BUS_SUPPORT [25:25] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_MASK          0x02000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_SHIFT         25
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 1_8V_SUPPORT [24:24] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_MASK                 0x01000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_SHIFT                24
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_DEFAULT              0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_0V_SUPPORT [23:23] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_MASK                 0x00800000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_SHIFT                23
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_3V_SUPPORT [22:22] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_MASK                 0x00400000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_SHIFT                22
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_DEFAULT              0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SUSP_RES_SUPPORT [21:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_MASK             0x00200000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_SHIFT            21
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDMA_SUPPORT [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_MASK                 0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_SHIFT                20
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_DEFAULT              0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: HIGH_SPEED_SUPPORT [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_MASK           0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_SHIFT          19
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_DEFAULT        0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: ADMA2_SUPPORT [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_MASK                0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_SHIFT               18
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_DEFAULT             0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: EXTENDED_MEDIA_SUPPORT [17:17] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_MASK       0x00020000
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_SHIFT      17
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: MAX_BL [16:15] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_MASK                       0x00018000
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_SHIFT                      15
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_DEFAULT                    0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: BASE_FREQ [14:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_MASK                    0x00007f80
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_SHIFT                   7
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_DEFAULT                 0x00000064
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_CLK_UNIT [06:06] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_MASK             0x00000040
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_SHIFT            6
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_FREQ [05:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_MASK                 0x0000003f
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_SHIFT                0
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_DEFAULT              0x00000032
+
+/***************************************************************************
+ *CAP_REG1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_REG_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_MASK             0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_SHIFT            31
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved0 [30:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_MASK                    0x7fe00000
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_SHIFT                   21
+
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_1_stuff [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_MASK                  0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_SHIFT                 20
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_BLK_MODE [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_MASK                 0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_SHIFT                19
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_MODE [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_MASK                     0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_SHIFT                    18
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_DEFAULT                  0x00000001
+
+/* SDIO_0_CFG :: CAP_REG1 :: CLK_MULT [17:10] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_MASK                     0x0003fc00
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_SHIFT                    10
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_MODES [09:08] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_MASK               0x00000300
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_SHIFT              8
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_DEFAULT            0x00000002
+
+/* SDIO_0_CFG :: CAP_REG1 :: USE_TUNING [07:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_MASK                   0x00000080
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_SHIFT                  7
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_DEFAULT                0x00000001
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_TIMER [06:03] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_MASK               0x00000078
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_SHIFT              3
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_DEFAULT            0x0000000a
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_D_SUPPORT [02:02] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_MASK             0x00000004
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_SHIFT            2
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_C_SUPPORT [01:01] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_MASK             0x00000002
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_SHIFT            1
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_A_SUPPORT [00:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_MASK             0x00000001
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_SHIFT            0
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PRESET1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET1 :: PRESET1_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET100 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_MASK                     0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_SHIFT                    16
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET50 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_MASK                      0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_SHIFT                     0
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_DEFAULT                   0x00000001
+
+/***************************************************************************
+ *PRESET2 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET2 :: PRESET2_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET2 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET25 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_MASK                      0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_SHIFT                     16
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_DEFAULT                   0x00000002
+
+/* SDIO_0_CFG :: PRESET2 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET12P5 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_MASK                    0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_SHIFT                   0
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_DEFAULT                 0x00000003
+
+/***************************************************************************
+ *SD_CLOCK_DELAY - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved0 [31:31] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_SHIFT             31
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: CLOCK_DELAY_OVERRIDE [30:30] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_MASK   0x40000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_SHIFT  30
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_DEFAULT 0x00000001
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_SEL [29:29] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_MASK        0x20000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_SHIFT       29
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_DEFAULT     0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved1 [28:12] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved1_MASK              0x1ffff000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved1_SHIFT             12
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: OUTPUT_CLOCK_DELAY [11:08] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_MASK     0x00000f00
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_SHIFT    8
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INTERNAL_CLOCK_DELAY [07:04] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_MASK   0x000000f0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_SHIFT  4
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_DEFAULT 0x0000000f
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_MASK      0x0000000f
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_SHIFT     0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_DEFAULT   0x0000000f
+
+/***************************************************************************
+ *SD_PAD_DRV - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_PAD_DRV :: OVERRIDE_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_SHIFT               31
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved0 [30:23] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_MASK                  0x7f800000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_SHIFT                 23
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CLK_VAL [22:20] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_MASK                    0x00700000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_SHIFT                   20
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved1 [19:19] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_MASK                  0x00080000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_SHIFT                 19
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CMD_VAL [18:16] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_MASK                    0x00070000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_SHIFT                   16
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved2 [15:15] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_MASK                  0x00008000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_SHIFT                 15
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT3_VAL [14:12] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_MASK                   0x00007000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_SHIFT                  12
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved3 [11:11] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_MASK                  0x00000800
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_SHIFT                 11
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT2_VAL [10:08] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_MASK                   0x00000700
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_SHIFT                  8
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved4 [07:07] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_MASK                  0x00000080
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_SHIFT                 7
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT1_VAL [06:04] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_MASK                   0x00000070
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_SHIFT                  4
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved5 [03:03] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_MASK                  0x00000008
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_SHIFT                 3
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT0_VAL [02:00] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_MASK                   0x00000007
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_SHIFT                  0
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_DEFAULT                0x00000005
+
+/***************************************************************************
+ *IP_DLY - SDIO Host input delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_DEFAULT                   0x00000000
+
+/* SDIO_0_CFG :: IP_DLY :: FORCE_USE_IP_TUNE_CLK [30:30] */
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_MASK          0x40000000
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_SHIFT         30
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: IP_DLY :: reserved0 [29:18] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_MASK                      0x3ffc0000
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: IP_DLY :: IP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_DEFAULT               0x00000003
+
+/* SDIO_0_CFG :: IP_DLY :: reserved1 [15:06] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_MASK                      0x0000ffc0
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_SHIFT                     6
+
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_DELAY [05:00] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_MASK                   0x0000003f
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_DEFAULT                0x00000028
+
+/***************************************************************************
+ *OP_DLY - SDIO Host output delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_DEFAULT                   0x00000000
+
+/* SDIO_0_CFG :: OP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: OP_DLY :: OP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: OP_DLY :: reserved1 [15:04] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_MASK                      0x0000fff0
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_SHIFT                     4
+
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_MASK                   0x0000000f
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TUNING - SDIO Host tuning configuration register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TUNING :: reserved0 [31:04] */
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_MASK                      0xfffffff0
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_SHIFT                     4
+
+/* SDIO_0_CFG :: TUNING :: TUNING_CMD_SUCCESS_CNT [03:00] */
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_MASK         0x0000000f
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_SHIFT        0
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_DEFAULT      0x00000008
+
+/***************************************************************************
+ *VOLT_CTRL - SDIO Host 1p8V control logic select register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VOLT_CTRL :: reserved0 [31:05] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_MASK                   0xffffffe0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_SHIFT                  5
+
+/* SDIO_0_CFG :: VOLT_CTRL :: POW_INV_EN [04:04] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_MASK                  0x00000010
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_SHIFT                 4
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_VAL [03:03] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_MASK                    0x00000008
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_SHIFT                   3
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_DEFAULT                 0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_INV_EN [02:02] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_MASK                 0x00000004
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_SHIFT                2
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_CTRL_SEL [01:00] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_MASK               0x00000003
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_SHIFT              0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SCRATCH - SDIO Scratch Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SCRATCH :: SCRATCH_BITS [31:00] */
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_MASK                  0xffffffff
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_SHIFT                 0
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_DEFAULT               0x00000000
+
+/***************************************************************************
+ *VERSION - SDIO VERSION Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VERSION :: SD_VER [31:24] */
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_MASK                        0xff000000
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_SHIFT                       24
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_DEFAULT                     0x00000030
+
+/* SDIO_0_CFG :: VERSION :: MMC_VER [23:16] */
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_MASK                       0x00ff0000
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_SHIFT                      16
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_DEFAULT                    0x00000044
+
+/* SDIO_0_CFG :: VERSION :: REV [15:08] */
+#define BCHP_SDIO_0_CFG_VERSION_REV_MASK                           0x0000ff00
+#define BCHP_SDIO_0_CFG_VERSION_REV_SHIFT                          8
+#define BCHP_SDIO_0_CFG_VERSION_REV_DEFAULT                        0x000000a9
+
+/* SDIO_0_CFG :: VERSION :: A2S_VER [07:00] */
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_MASK                       0x000000ff
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_SHIFT                      0
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_DEFAULT                    0x00000001
+
+#endif /* #ifndef BCHP_SDIO_0_CFG_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/7429b0/bchp_sun_top_ctrl.h
new file mode 100644
index 0000000..c75bfad
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_sun_top_ctrl.h
@@ -0,0 +1,7147 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:17 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SUN_TOP_CTRL_H__
+#define BCHP_SUN_TOP_CTRL_H__
+
+/***************************************************************************
+ *SUN_TOP_CTRL - Top Control registers
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID         0x00404000 /* Chip family ID */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID             0x00404004 /* Product Revision ID */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x0040401c /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x00404020 /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x00404024 /* Bond option value register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x00404028 /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x0040402c /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x00404030 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x00404034 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x00404038 /* Semaphore channel 0 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x0040403c /* Semaphore channel 1 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x00404040 /* Semaphore channel 2 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x00404044 /* Semaphore channel 3 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x00404048 /* Semaphore channel 4 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x0040404c /* Semaphore channel 5 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x00404050 /* Semaphore channel 6 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x00404054 /* Semaphore channel 7 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x00404058 /* Semaphore channel 8 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x0040405c /* Semaphore channel 9 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x00404060 /* Semaphore channel 10 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x00404064 /* Semaphore channel 11 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x00404068 /* Semaphore channel 12 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x0040406c /* Semaphore channel 13 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x00404070 /* Semaphore channel 14 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x00404074 /* Semaphore channel 15 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x00404078 /* General watchdog timer 0 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x0040407c /* General watchdog timer 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x00404080 /* General control register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x00404084 /* General control register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x00404088 /* General control register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x0040408c /* General control register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x00404090 /* General control register 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x00404094 /* General control register 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x00404098 /* General status register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x0040409c /* General status register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x004040a0 /* General status register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x00404100 /* Pinmux control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x00404104 /* Pinmux control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x00404108 /* Pinmux control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x0040410c /* Pinmux control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x00404110 /* Pinmux control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x00404114 /* Pinmux control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x00404118 /* Pinmux control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x0040411c /* Pinmux control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x00404120 /* Pinmux control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x00404124 /* Pinmux control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10        0x00404128 /* Pinmux control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11        0x0040412c /* Pinmux control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12        0x00404130 /* Pinmux control register 12 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13        0x00404134 /* Pinmux control register 13 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14        0x00404138 /* Pinmux control register 14 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15        0x0040413c /* Pinmux control register 15 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16        0x00404140 /* Pinmux control register 16 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17        0x00404144 /* Pinmux control register 17 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18        0x00404148 /* Pinmux control register 18 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x0040414c /* Pad pull-up/pull-down control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x00404150 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x00404154 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x00404158 /* Pad pull-up/pull-down control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x0040415c /* Pad pull-up/pull-down control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5     0x00404160 /* Pad pull-up/pull-down control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6     0x00404164 /* Pad pull-up/pull-down control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7     0x00404168 /* Pad pull-up/pull-down control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8     0x0040416c /* Pad pull-up/pull-down control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9     0x00404170 /* Pad pull-up/pull-down control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10    0x00404174 /* Pad pull-up/pull-down control register 10 */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x00404178 /* Bypass clock unselect register 0 */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x00404300 /* Reset control */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE    0x00404304 /* Reset source enable */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET        0x00404308 /* Software master reset */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION     0x0040430c /* Hardware reset extension */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR          0x00404310 /* Reset Monitor */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x00404314 /* Reset history */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET          0x00404318 /* Software init 0 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR        0x0040431c /* Software init 0 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS       0x00404320 /* Software init 0 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR  0x00404324 /* Security software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET          0x00404330 /* Software init 1 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR        0x00404334 /* Software init 1 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS       0x00404338 /* Software init 1 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR  0x0040433c /* Security software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x00404364 /* Scratch register */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x00404368 /* Spare control bits reserved for future use */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x00404380 /* Test port control */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x00404384 /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x00404388 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x0040438c /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x00404390 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x00404394 /* EJTAG input bus enables */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x00404398 /* EJTAG output select */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL        0x0040439c /* UART Router select */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL             0x004043a0 /* VTRAP Control */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS           0x004043a4 /* VTRAP Status */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x00404400 /* Serial Slave Port configuration register */
+#define BCHP_SUN_TOP_CTRL_SERS_REV               0x00404420 /* SERS Revision Register */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x00404424 /* SERS Configuration Register */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x00404514 /* Block select for RO testmode */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION     0x00404518 /* Test configuration */
+
+/***************************************************************************
+ *CHIP_FAMILY_ID - Chip family ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT    0x74290010
+
+/***************************************************************************
+ *PRODUCT_ID - Product Revision ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK               0xffffffff
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT            0x74290010
+
+/***************************************************************************
+ *BSP_FEATURE_TABLE_ADDR - BSP feature table address
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_VALUE_0 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [07:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [03:03] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_multi_a_config [02:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_multi_a_config_MASK  0x00000006
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_multi_a_config_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_multi_a_config_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_0_MASK          0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_0_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_0_DEFAULT       0x00000000
+
+/***************************************************************************
+ *STRAP_VALUE_1 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xfffffff0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            4
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias_sel [03:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_MASK  0x0000000e
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_DEFAULT 0x00000004
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK     0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT  0x00000000
+
+/***************************************************************************
+ *BOND_STATUS - Bond option value register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1
+
+/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_0 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_3 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_2 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_1 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_0 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_out_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_out_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_out_disable_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_out_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_genet0_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet0_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet0_disable_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet0_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_svc_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rfm_output_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rfm_output_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rfm_output_disable_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rfm_output_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_mtsif_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_mtsif_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_mtsif_disable_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_mtsif_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_moca_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_rx_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_rx_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_rx_disable_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_rx_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hd_display_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sata_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ephy_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_tx_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_tx_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_tx_disable_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_tx_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdmi_passthru_disable [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_passthru_disable_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_passthru_disable_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_passthru_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdmi_rx_disable [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_moca20_disable [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca20_disable_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca20_disable_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca20_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb23_otg_disable [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb23_otg_disable_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb23_otg_disable_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb23_otg_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb01_otg_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb01_otg_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb01_otg_disable_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb01_otg_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 0x00000003
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_TEST_1 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_23 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_22 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_21 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_20 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_19 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_18 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_17 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_16 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_15 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_14 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_0 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_pwm_pair_disable [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pwm_pair_disable_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pwm_pair_disable_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pwm_pair_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb3_disable [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb2_disable [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb2_disable_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb2_disable_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb2_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb1_disable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb1_disable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb1_disable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb1_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb0_disable [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb0_disable_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb0_disable_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb0_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_genet1_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_genet1_disable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_genet1_disable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_genet1_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rv9_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_sc_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_sc_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_sc_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_sc_disable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_0 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_3 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_3_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_3_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_2 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_2_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_2_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_1 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_0 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_out_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_out_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_out_disable_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_genet0_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet0_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet0_disable_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_svc_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_svc_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_svc_disable_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rfm_output_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rfm_output_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rfm_output_disable_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_mtsif_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_mtsif_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_mtsif_disable_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_moca_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_rx_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_rx_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_rx_disable_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hd_display_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sata_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ephy_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_tx_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_tx_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_tx_disable_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdmi_passthru_disable [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_passthru_disable_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_passthru_disable_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdmi_rx_disable [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_rx_disable_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_rx_disable_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_moca20_disable [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca20_disable_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca20_disable_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb23_otg_disable [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb23_otg_disable_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb23_otg_disable_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb01_otg_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb01_otg_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb01_otg_disable_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_1 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_23 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_22 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_21 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_20 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_19 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_18 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_17 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_16 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_15 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_14 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_0 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_pwm_pair_disable [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pwm_pair_disable_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pwm_pair_disable_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb3_disable [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb3_disable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb3_disable_SHIFT 6
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb2_disable [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb2_disable_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb2_disable_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb1_disable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb1_disable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb1_disable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb0_disable [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb0_disable_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb0_disable_SHIFT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_genet1_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_genet1_disable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_genet1_disable_SHIFT 2
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rv9_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_SHIFT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_sc_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_sc_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_sc_disable_SHIFT 0
+
+/***************************************************************************
+ *SEMAPHORE_0 - Semaphore channel 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_1 - Semaphore channel 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_2 - Semaphore channel 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_3 - Semaphore channel 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_4 - Semaphore channel 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_5 - Semaphore channel 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_6 - Semaphore channel 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_7 - Semaphore channel 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_8 - Semaphore channel 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_9 - Semaphore channel 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_10 - Semaphore channel 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_11 - Semaphore channel 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_12 - Semaphore channel 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_13 - Semaphore channel 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_14 - Semaphore channel 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_15 - Semaphore channel 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_0 - General watchdog timer 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_1 - General watchdog timer 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK     0x80000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT    31
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK     0x40000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT    30
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK     0x20000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT    29
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK     0x10000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT    28
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK     0x02000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT    25
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK     0x01000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT    24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK     0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT    23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK     0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT    22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK     0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT    21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK     0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT    20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK     0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT    19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK     0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT    18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK     0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT    17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK     0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT    16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: mii_genet_mac_select [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_genet_mac_select_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_genet_mac_select_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_genet_mac_select_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb1_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_mode_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_mode_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_mode_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb0_mode [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_DEFAULT         0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_1 - General control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_2 - General control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_3 - General control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_4 - General control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_5 - General control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK          0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT         8
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_1 - General status register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_2 - General status register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xffc00000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   22
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_slew_14 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_14_MASK  0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_14_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_14_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_slew_13 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_13_MASK  0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_13_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_13_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_slew_12 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_12_MASK  0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_12_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_12_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_slew_11 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_11_MASK  0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_11_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_11_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_slew_10 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_10_MASK  0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_10_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_10_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_slew_9 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_9_MASK   0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_9_SHIFT  16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_9_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_slew_8 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_8_MASK   0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_8_SHIFT  15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_8_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_slew_7 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_7_MASK   0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_7_SHIFT  14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_7_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_slew_6 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_6_MASK   0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_6_SHIFT  13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_6_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_slew_5 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_5_MASK   0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_5_SHIFT  12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_5_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_slew_4 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_4_MASK   0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_4_SHIFT  11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_4_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_slew_3 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_3_MASK   0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_3_SHIFT  10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_3_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_slew_2 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_2_MASK   0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_2_SHIFT  9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_2_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_slew_1 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_1_MASK   0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_1_SHIFT  8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_slew_0 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_0_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_0_SHIFT  7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_slew_0_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_amp_en [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_sel [05:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_GMII_CMOS_3P3V 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_RGMII_CMOS_2P5V 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_HSTL_CLASS1_1P5V 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_HSTL_CLASS1_1P8V 3
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_rx_pad_amp_en [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_rx_pad_amp_en_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_rx_pad_amp_en_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_rx_pad_amp_en_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_tx_pad_amp_en [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_tx_pad_amp_en_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_tx_pad_amp_en_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_tx_pad_amp_en_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_sel [01:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_GMII_CMOS_3P3V 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_RGMII_CMOS_2P5V 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_HSTL_CLASS1_1P5V 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_HSTL_CLASS1_1P8V 3
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK    0xf0000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT   28
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_073 [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_073_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_073_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_073_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_072 [26:26] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_072_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_072_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_072_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_071 [25:25] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_071_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_071_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_071_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_070 [24:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_070_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_070_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_070_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_069 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_069_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_069_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_069_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_068 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_068_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_068_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_068_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_067 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_067_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_067_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_067_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_066 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_066_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_066_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_066_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_065 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_065_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_065_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_065_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_064 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_064_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_064_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_064_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_063 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_063_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_063_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_063_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_062 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_062_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_062_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_062_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_061 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_061_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_061_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_061_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_060 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_060_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_060_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_060_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_059 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_059_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_059_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_059_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_058 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_058_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_058_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_058_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_057 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_056 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_055 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_054 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_053 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_052 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_051 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_050 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_049 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_048 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_047 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_046 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xffffff80
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_hys_en [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_oeb [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_do [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_src [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DEFAULT 0x00000005
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_16MA 7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_007 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_007_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_007_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_007_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_007_GPIO_007         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_007_EBI_ADDR7        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_007_MTSIF0_DATA4     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_007_ALT_TP_IN_27     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_007_PM_GPIO_007      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_006 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_006_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_006_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_006_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_006_GPIO_006         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_006_EBI_ADDR6        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_006_MTSIF0_DATA3     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_006_ALT_TP_IN_26     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_006_PM_GPIO_006      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_005 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_005_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_005_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_005_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_005_GPIO_005         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_005_EBI_ADDR5        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_005_MTSIF0_DATA2     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_005_ALT_TP_IN_25     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_005_PM_GPIO_005      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_004 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_004_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_004_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_004_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_004_GPIO_004         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_004_EBI_ADDR4        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_004_MTSIF_ATS_INC    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_004_ALT_TP_IN_24     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_004_PM_GPIO_004      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_003 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_003_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_003_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_003_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_003_GPIO_003         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_003_EBI_ADDR3        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_003_MTSIF0_DATA1     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_003_ALT_TP_IN_23     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_003_PM_GPIO_003      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_002 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_002_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_002_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_002_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_002_GPIO_002         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_002_EBI_ADDR2        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_002_MTSIF0_SYNC      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_002_ALT_TP_IN_22     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_002_PM_GPIO_002      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_001 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_001_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_001_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_001_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_001_GPIO_001         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_001_EBI_ADDR1        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_001_MTSIF0_DATA0     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_001_ALT_TP_IN_21     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_001_PM_GPIO_001      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_000 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_000_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_000_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_000_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_000_GPIO_000         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_000_EBI_ADDR0        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_000_MTSIF0_CLK       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_000_ALT_TP_IN_20     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_000_PM_GPIO_000      4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_015 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_015_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_015_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_015_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_015_GPIO_015         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_015_EBI_WAITB        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_015_SPI_M_SS1B       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_015_PM_GPIO_015      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_014 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_014_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_014_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_014_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_014_GPIO_014         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_014_EBI_ADDR14       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_014_SD1_DAT3         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_014_PM_GPIO_014      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_013 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_013_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_013_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_013_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_013_GPIO_013         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_013_EBI_ADDR13       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_013_SD1_DAT2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_013_PM_GPIO_013      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_012 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_012_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_012_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_012_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_012_GPIO_012         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_012_EBI_ADDR12       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_012_SD1_DAT1         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_012_PM_GPIO_012      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_011 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_011_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_011_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_011_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_011_GPIO_011         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_011_EBI_ADDR11       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_011_MTSIF_ATS_RST    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_011_ALT_TP_IN_31     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_011_PM_GPIO_011      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_010 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_010_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_010_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_010_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_010_GPIO_010         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_010_EBI_ADDR10       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_010_MTSIF0_DATA7     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_010_ALT_TP_IN_30     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_010_PM_GPIO_010      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_009 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_009_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_009_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_009_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_009_GPIO_009         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_009_EBI_ADDR9        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_009_MTSIF0_DATA6     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_009_ALT_TP_IN_29     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_009_PM_GPIO_009      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_008 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_008_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_008_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_008_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_008_GPIO_008         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_008_EBI_ADDR8        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_008_MTSIF0_DATA5     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_008_ALT_TP_IN_28     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_008_PM_GPIO_008      4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_023 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_023_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_023_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_023_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_023_GPIO_023         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_023_EBI_CS3B         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_023_PM_GPIO_023      2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_022 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_022_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_022_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_022_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_022_GPIO_022         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_022_EBI_CS2B         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_022_PM_GPIO_022      2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_021 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_021_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_021_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_021_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_021_GPIO_021         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_021_EBI_CS1B         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_021_PM_GPIO_021      2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_020 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_020_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_020_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_020_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_020_GPIO_020         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_020_EBI_CS0B         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_020_PM_GPIO_020      2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_019 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_019_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_019_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_019_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_019_GPIO_019         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_019_EBI_RWB          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_019_PM_GPIO_019      2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_018 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_018_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_018_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_018_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_018_GPIO_018         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_018_LED_LD1          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_018_SD1_WPROT        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_018_PM_GPIO_018      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_017 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_017_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_017_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_017_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_017_GPIO_017         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_017_LED_LD0          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_017_SD1_PRES         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_017_PM_GPIO_017      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_016 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_016_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_016_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_016_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_016_GPIO_016         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_016_EBI_WE1B         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_016_PM_GPIO_016      2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_031 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_031_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_031_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_031_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_031_GPIO_031         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_031_EBI_DATA6        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_031_PM_GPIO_031      2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_030 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_030_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_030_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_030_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_030_GPIO_030         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_030_EBI_DATA5        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_030_PM_GPIO_030      2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_029 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_029_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_029_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_029_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_029_GPIO_029         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_029_EBI_DATA4        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_029_PM_GPIO_029      2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_028 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_028_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_028_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_028_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_028_GPIO_028         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_028_EBI_DATA3        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_028_PM_GPIO_028      2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_027 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_027_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_027_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_027_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_027_GPIO_027         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_027_EBI_DATA2        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_027_PM_GPIO_027      2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_026 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_026_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_026_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_026_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_026_GPIO_026         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_026_EBI_DATA1        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_026_PM_GPIO_026      2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_025 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_025_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_025_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_025_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_025_GPIO_025         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_025_EBI_DATA0        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_025_PM_GPIO_025      2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_024 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_024_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_024_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_024_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_024_GPIO_024         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_024_EBI_CS4B         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_024_SPI_M_SS0B       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_024_SD1_LED          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_024_SD1_PWR0         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_024_PM_GPIO_024      5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_4 - Pinmux control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_039 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_039_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_039_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_039_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_039_GPIO_039         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_039_EBI_DATA14       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_039_SPI_M_MISO       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_039_SD1_CLK          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_039_POD_EBI_WE0B     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_039_TP_IN_06         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_039_PM_GPIO_039      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_038 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_038_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_038_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_038_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_038_GPIO_038         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_038_EBI_DATA13       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_038_SPI_M_MOSI       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_038_SD1_CMD          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_038_POD_EBI_RDB      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_038_TP_IN_05         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_038_PM_GPIO_038      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_037 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_037_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_037_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_037_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_037_GPIO_037         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_037_EBI_DATA12       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_037_SC1_PRES         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_037_SC0_PRES         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_037_SD1_PRES         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_037_TP_IN_04         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_037_PM_GPIO_037      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_036 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_036_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_036_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_036_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_036_GPIO_036         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_036_EBI_DATA11       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_036_SC1_IO           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_036_SC0_IO           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_036_SD1_WPROT        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_036_TP_IN_03         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_036_PM_GPIO_036      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_035 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_035_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_035_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_035_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_035_GPIO_035         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_035_EBI_DATA10       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_035_SC1_RST          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_035_SC0_RST          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_035_SD1_DAT3         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_035_TP_IN_02         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_035_PM_GPIO_035      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_034 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_034_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_034_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_034_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_034_GPIO_034         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_034_EBI_DATA9        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_034_SC1_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_034_SC0_CLK          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_034_SD1_DAT2         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_034_TP_IN_01         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_034_PM_GPIO_034      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_033 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_033_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_033_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_033_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_033_GPIO_033         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_033_EBI_DATA8        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_033_SC1_VCC          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_033_SC0_VCC          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_033_SD1_DAT1         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_033_TP_IN_00         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_033_PM_GPIO_033      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_032 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_032_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_032_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_032_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_032_GPIO_032         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_032_EBI_DATA7        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_032_PM_GPIO_032      2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_5 - Pinmux control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_047 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_047_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_047_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_047_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_047_GPIO_047         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_047_POD2CHIP_MDI0    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_047_PPKT_I_DATA_0    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_047_PKT1_CLK         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_047_TP_OUT_25        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_047_PM_GPIO_047      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_046 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_046_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_046_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_046_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_046_GPIO_046         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_046_POD2CHIP_MCLKI   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_046_PPKT_I_CLK       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_046_EBI_ADDR14       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_046_PKT1_VALID       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_046_TP_OUT_24        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_046_PM_GPIO_046      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_045 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_045_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_045_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_045_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_045_GPIO_045         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_045_EBI_NAND_RBB     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_045_PM_GPIO_045      2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_044 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_044_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_044_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_044_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_044_GPIO_044         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_044_EBI_TSB          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_044_PM_GPIO_044      2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_043 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_043_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_043_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_043_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_043_GPIO_043         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_043_EBI_DSB          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_043_POD_EBI_DSB      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_043_PM_GPIO_043      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_042 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_042_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_042_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_042_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_042_GPIO_042         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_042_EBI_WE0B         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_042_POD_EBI_WE0B     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_042_PM_GPIO_042      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_041 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_041_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_041_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_041_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_041_GPIO_041         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_041_EBI_RDB          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_041_POD_EBI_RDB      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_041_PM_GPIO_041      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_040 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_040_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_040_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_040_DEFAULT          0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_040_GPIO_040         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_040_EBI_DATA15       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_040_SPI_M_SCK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_040_SD1_DAT0         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_040_POD_EBI_DSB      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_040_TP_IN_07         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_040_PM_GPIO_040      6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_6 - Pinmux control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_055 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_055_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_055_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_055_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_055_GPIO_055         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_055_POD2CHIP_MISTRT  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_055_PPKT_I_SYNC      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_055_PKT2_SYNC        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_055_TP_OUT_17        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_055_PM_GPIO_055      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_054 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_054_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_054_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_054_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_054_GPIO_054         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_054_POD2CHIP_MDI7    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_054_PPKT_I_DATA_7    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_054_PKT2_CLK         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_054_TP_OUT_16        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_054_PM_GPIO_054      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_053 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_053_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_053_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_053_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_053_GPIO_053         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_053_POD2CHIP_MDI6    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_053_PPKT_I_DATA_6    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_053_PKT2_ERROR       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_053_TP_OUT_31        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_053_PM_GPIO_053      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_052 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_052_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_052_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_052_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_052_GPIO_052         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_052_POD2CHIP_MDI5    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_052_PPKT_I_DATA_5    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_052_PKT2_VALID       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_052_TP_OUT_30        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_052_PM_GPIO_052      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_051 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_051_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_051_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_051_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_051_GPIO_051         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_051_POD2CHIP_MDI4    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_051_PPKT_I_DATA_4    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_051_PKT1_DATA        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_051_TP_OUT_29        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_051_PM_GPIO_051      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_050 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_050_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_050_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_050_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_050_GPIO_050         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_050_POD2CHIP_MDI3    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_050_PPKT_I_DATA_3    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_050_TP_OUT_28        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_050_PM_GPIO_050      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_049 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_049_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_049_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_049_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_049_GPIO_049         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_049_POD2CHIP_MDI2    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_049_PPKT_I_DATA_2    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_049_PKT1_SYNC        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_049_TP_OUT_27        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_049_PM_GPIO_049      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_048 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_048_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_048_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_048_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_048_GPIO_048         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_048_POD2CHIP_MDI1    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_048_PPKT_I_DATA_1    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_048_PKT1_ERROR       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_048_TP_OUT_26        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_048_PM_GPIO_048      5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_7 - Pinmux control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_063 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_063_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_063_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_063_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_063_GPIO_063         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_063_CHIP2POD_MDO5    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_063_RMXP_DATA5       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_063_EBI_ADDR23       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_063_SC0_AUX2         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_063_SC1_VPP          5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_063_TP_IN_09         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_063_PM_GPIO_063      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_062 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_062_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_062_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_062_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_062_GPIO_062         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_062_CHIP2POD_MDO4    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_062_RMXP_DATA4       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_062_EBI_ADDR22       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_062_SC0_AUX1         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_062_TP_OUT_08        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_062_PM_GPIO_062      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_061 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_061_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_061_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_061_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_061_GPIO_061         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_061_CHIP2POD_MDO3    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_061_RMXP_DATA3       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_061_EBI_ADDR21       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_061_SC0_PRES         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_061_TP_OUT_23        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_061_PM_GPIO_061      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_060 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_060_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_060_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_060_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_060_GPIO_060         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_060_CHIP2POD_MDO2    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_060_RMXP_DATA2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_060_EBI_ADDR20       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_060_SC0_IO           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_060_TP_OUT_22        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_060_PM_GPIO_060      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_059 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_059_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_059_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_059_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_059_GPIO_059         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_059_CHIP2POD_MDO1    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_059_RMXP_DATA1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_059_EBI_ADDR19       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_059_SC0_RST          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_059_TP_OUT_21        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_059_PM_GPIO_059      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_058 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_058_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_058_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_058_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_058_GPIO_058         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_058_CHIP2POD_MDO0    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_058_RMXP_DATA0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_058_EBI_ADDR18       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_058_SC0_CLK          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_058_TP_OUT_20        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_058_PM_GPIO_058      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_057 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_057_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_057_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_057_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_057_GPIO_057         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_057_CHIP2POD_MCLKO   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_057_RMXP_CLK         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_057_EBI_ADDR15       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_057_SC0_VCC          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_057_TP_OUT_19        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_057_PM_GPIO_057      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_056 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_056_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_056_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_056_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_056_GPIO_056         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_056_POD2CHIP_MIVAL   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_056_PPKT_I_VALID     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_056_PKT2_DATA        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_056_TP_OUT_18        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_056_PM_GPIO_056      5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_8 - Pinmux control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_071 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_071_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_071_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_071_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_071_GPIO_071         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_071_CHIP2POD_SCLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_071_TTX0_REQ         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_071_EBI_ADDR1        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_071_RMX0_SYNC        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_071_MOCA_ACTIVITY    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_071_TP_IN_13         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_071_PM_GPIO_071      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_070 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_070_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_070_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_070_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_070_GPIO_070         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_070_CHIP2POD_SCTL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_070_EBI_ADDR2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_070_VEC_VSYNC        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_070_RMX0_DATA        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_070_TP_IN_12         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_070_PM_GPIO_070      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_069 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_069_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_069_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_069_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_069_GPIO_069         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_069_CHIP2POD_MOCLK   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_069_RMXP_CLK         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_069_EBI_ADDR12       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_069_VEC_HSYNC        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_069_RMX0_CLK         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_069_TP_IN_11         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_069_PM_GPIO_069      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_068 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_068_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_068_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_068_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_068_GPIO_068         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_068_POD2CHIP_MICLK   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_068_PPKT_I_ERROR     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_068_EBI_ADDR13       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_068_UART_RX2         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_068_UART_CTS1        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_068_ALT_TP_IN_03     6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_068_PM_GPIO_068      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_067 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_067_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_067_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_067_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_067_GPIO_067         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_067_CHIP2POD_MOVAL   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_067_RMXP_VALID       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_067_EBI_ADDR16       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_067_UART_TX2         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_067_UART_RTS1        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_067_ALT_TP_OUT_03    6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_067_PM_GPIO_067      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_066 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_066_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_066_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_066_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_066_GPIO_066         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_066_CHIP2POD_MOSTRT  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_066_RMXP_SYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_066_EBI_ADDR17       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_066_UART_RX1         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_066_UART_CTS0        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_066_ALT_TP_IN_02     6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_066_PM_GPIO_066      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_065 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_065_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_065_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_065_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_065_GPIO_065         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_065_CHIP2POD_MDO7    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_065_RMXP_DATA7       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_065_EBI_ADDR25       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_065_UART_TX1         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_065_UART_RTS0        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_065_ALT_TP_OUT_02    6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_065_PM_GPIO_065      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_064 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_064_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_064_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_064_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_064_GPIO_064         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_064_CHIP2POD_MDO6    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_064_RMXP_DATA6       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_064_EBI_ADDR24       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_064_SC0_VPP          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_064_TP_IN_10         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_064_PM_GPIO_064      6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_9 - Pinmux control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_079 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_079_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_079_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_079_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_079_GPIO_079         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_079_SC0_VCC          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_079_TEST_THP         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_079_PKT1_CLK         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_079_UART_TX1         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_079_SDIO0_PWR0       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_079_ALT_TP_OUT_04    6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_079_PM_GPIO_079      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_078 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_078_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_078_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_078_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_078_GPIO_078         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_078_RMX0_PAUSE       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_078_I2S_LR0_IN       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_078_P1_INTR_1        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_078_PWM1             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_078_SC1_VPP          5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_078_ALT_TP_OUT_24    6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_078_PM_GPIO_078      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_077 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_077_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_077_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_077_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_077_GPIO_077         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_077_RMX0_VALID       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_077_SPI_M_SS1B       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_077_SDIO0_LED        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_077_ALT_TP_OUT_23    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_077_PM_GPIO_077      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_076 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_076_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_076_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_076_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_076_GPIO_076         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_076_RMX0_SYNC        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_076_CLK_OBSRV3       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_076_SDIO0_VCTL       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_076_ALT_TP_OUT_22    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_076_PM_GPIO_076      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_075 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_075_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_075_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_075_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_075_GPIO_075         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_075_RMX0_DATA        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_075_CLK_OBSRV2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_075_ALT_TP_OUT_21    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_075_PM_GPIO_075      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_074 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_074_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_074_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_074_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_074_GPIO_074         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_074_RMX0_CLK         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_074_RO_OBSRV         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_074_CLK_OBSRV1       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_074_ALT_TP_OUT_20    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_074_PM_GPIO_074      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_073 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_073_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_073_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_073_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_073_GPIO_073         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_073_POD2CHIP_SDI     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_073_RMX0_PAUSE       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_073_TP_IN_15         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_073_PM_GPIO_073      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_072 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_072_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_072_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_072_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_072_GPIO_072         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_072_CHIP2POD_SDO     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_072_TTX0_DATA        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_072_EBI_ADDR0        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_072_RMX0_VALID       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_072_MOCA_LINK        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_072_TP_IN_14         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_072_PM_GPIO_072      7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_10 - Pinmux control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_087 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_087_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_087_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_087_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_087_GPIO_087        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_087_PKT1_CLK        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_087_PPKT_I_CLK      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_087_MTSIF0_CLK      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_087_ALT_TP_OUT_15   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_087_PM_GPIO_087     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_086 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_086_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_086_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_086_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_086_GPIO_086        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_086_SC0_VPP         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_086_POD_EBI_DSB     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_086_I2S_LR0_OUT     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_086_ALT_TP_OUT_14   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_086_PM_GPIO_086     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_085 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_085_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_085_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_085_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_085_GPIO_085        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_085_SC0_AUX2        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_085_POD_EBI_WE0B    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_085_I2S_DATA0_OUT   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_085_ALT_TP_OUT_13   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_085_PM_GPIO_085     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_084 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_084_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_084_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_084_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_084_GPIO_084        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_084_SC0_AUX1        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_084_POD_EBI_RDB     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_084_I2S_CLK0_OUT    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_084_ALT_TP_OUT_12   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_084_PM_GPIO_084     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_083 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_083_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_083_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_083_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_083_GPIO_083        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_083_SC0_PRES        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_083_PKT1_ERROR      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_083_ALT_TP_OUT_11   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_083_PM_GPIO_083     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_082 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_082_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_082_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_082_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_082_GPIO_082        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_082_SC0_IO          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_082_PKT1_VALID      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_082_UART_RX2        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_082_ALT_TP_IN_05    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_082_PM_GPIO_082     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_081 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_081_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_081_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_081_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_081_GPIO_081        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_081_SC0_RST         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_081_PKT1_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_081_UART_TX2        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_081_ALT_TP_OUT_05   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_081_PM_GPIO_081     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_080 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_080_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_080_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_080_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_080_GPIO_080        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_080_SC0_CLK         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_080_PKT1_DATA       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_080_UART_RX1        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_080_ALT_TP_IN_04    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_080_PM_GPIO_080     5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_11 - Pinmux control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_095 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_095_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_095_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_095_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_095_GPIO_095        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_095_UART_RX1        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_095_VEC_VSYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_095_I2S_CLK0_OUT    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_095_POD_EBI_WE0B    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_095_ALT_TP_IN_07    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_095_PM_GPIO_095     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_094 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_094_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_094_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_094_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_094_GPIO_094        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_094_UART_TX1        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_094_VEC_HSYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_094_SDIO0_VCTL      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_094_POD_EBI_RDB     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_094_ALT_TP_OUT_07   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_094_PM_GPIO_094     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_093 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_093_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_093_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_093_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_093_GPIO_093        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_093_SPI_S_SSB       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_093_UART_RX0        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_093_UART_RX1        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_093_MOCA_LINK       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_093_SDIO0_PRES      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_093_ALT_TP_IN_06    6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_093_PM_GPIO_093     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_092 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_092_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_092_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_092_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_092_GPIO_092        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_092_SPI_S_MISO      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_092_UART_TX0        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_092_UART_TX1        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_092_MOCA_ACTIVITY   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_092_SDIO0_VCTL      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_092_TEST_THP        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_092_ALT_TP_OUT_06   7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_092_PM_GPIO_092     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_091 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_091_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_091_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_091_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_091_GPIO_091        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_091_PKT1_ERROR      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_091_PKT3_DATA       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_091_MTSIF0_DATA1    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_091_ALT_TP_OUT_19   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_091_PM_GPIO_091     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_090 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_090_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_090_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_090_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_090_GPIO_090        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_090_PKT1_VALID      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_090_PKT3_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_090_PPKT_I_ERROR    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_090_ALT_TP_OUT_18   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_090_PM_GPIO_090     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_089 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_089_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_089_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_089_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_089_GPIO_089        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_089_PKT1_SYNC       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_089_PPKT_I_SYNC     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_089_MTSIF0_SYNC     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_089_ALT_TP_OUT_17   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_089_PM_GPIO_089     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_088 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_088_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_088_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_088_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_088_GPIO_088        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_088_PKT1_DATA       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_088_PPKT_I_VALID    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_088_MTSIF0_DATA0    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_088_ALT_TP_OUT_16   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_088_PM_GPIO_088     5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_12 - Pinmux control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_104 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_GPIO_104        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_PKT2_VALID      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_PKT3_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_IR_OUT          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_UART_RX2        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_CODEC_SDI       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_SPI_M_MISO      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_MTSIF_ATS_RST   7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_ALT_TP_IN_11    8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_PM_GPIO_104     9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_103 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_GPIO_103        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_PKT2_SYNC       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_CODEC_MCLK      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_SPI_M_SCK       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_MTSIF0_DATA4    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_ALT_TP_OUT_27   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_PM_GPIO_103     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_102 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_GPIO_102        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_PKT2_DATA       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_HD_DVI0_0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_SATA_MDCLK      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_UART_RTS2       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_CODEC_SDO       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_SPI_M_SS0B      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_MTSIF0_DATA3    7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_ALT_TP_IN_09    8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_PM_GPIO_102     9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_101 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_GPIO_101        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_PKT2_CLK        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_HD_DVI0_10      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SATA_MDIO       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_UART_TX2        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_CODEC_SCLK      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SPI_M_MOSI      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_MTSIF0_DATA2    7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_ALT_TP_OUT_09   8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_PM_GPIO_101     9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_099 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_099_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_099_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_099_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_099_GPIO_099        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_099_SF_WPB          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_099_EXT_IRQB_3      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_099_PWM0            3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_099_UART_RTS0       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_099_I2S_DATA0_IN    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_099_ALT_TP_OUT_26   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_099_PM_GPIO_099     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_098 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_098_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_098_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_098_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_098_GPIO_098        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_098_SF_HOLDB        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_098_EXT_IRQB_2      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_098_VEC_VSYNC       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_098_UART_CTS0       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_098_I2S_CLK0_IN     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_098_ALT_TP_OUT_25   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_098_PM_GPIO_098     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_097 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_097_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_097_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_097_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_097_GPIO_097        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_097_UART_RX2        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_097_IR_OUT          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_097_I2S_LR0_OUT     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_097_POD2CHIP_MCLKI  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_097_I2S_LR0_IN      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_097_ALT_TP_IN_08    6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_097_PM_GPIO_097     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_096 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_096_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_096_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_096_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_096_GPIO_096        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_096_UART_TX2        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_096_PWM0            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_096_I2S_DATA0_OUT   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_096_POD_EBI_DSB     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_096_ALT_TP_OUT_08   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_096_PM_GPIO_096     6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_13 - Pinmux control register 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_112 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_GPIO_112        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_USB2_PWRFLT     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_RMX1_PAUSE      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_P1_INTR_1       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_ALT_TP_IN_13    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_PM_GPIO_112     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_111 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_GPIO_111        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_USB1_PWRFLT     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_EXT_IRQB_5      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_SDIO0_VCTL      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_TP_IN_30        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_PM_GPIO_111     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_110 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_GPIO_110        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_USB0_PWRFLT     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_EXT_IRQB_4      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_P1_INTR_1       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_TP_IN_29        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_PM_GPIO_110     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_109 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_GPIO_109        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_USB3_PWRON      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_RMX1_DATA       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_ALT_TP_IN_12    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_PM_GPIO_109     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_108 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_GPIO_108        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_USB2_PWRON      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_RMX1_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_PWM0            3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_ALT_TP_OUT_31   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_PM_GPIO_108     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_107 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_GPIO_107        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_USB1_PWRON      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_ALT_TP_OUT_30   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_PM_GPIO_107     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_106 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_106_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_106_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_106_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_106_GPIO_106        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_106_USB0_PWRON      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_106_ALT_TP_OUT_29   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_106_PM_GPIO_106     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_105 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_GPIO_105        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_PKT2_ERROR      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_VEC_HSYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_UART_CTS2       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_CODEC_FSYNCB    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_SPI_M_SS1B      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_MTSIF0_DATA5    6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_ALT_TP_OUT_28   7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_PM_GPIO_105     8
+
+/***************************************************************************
+ *PIN_MUX_CTRL_14 - Pinmux control register 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_124 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_GPIO_124        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_SDIO0_PWR0      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_VO0_656_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_PPKT_I_DATA_1   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_TP_IN_18        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_PM_GPIO_124     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_123 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_GPIO_123        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_SDIO0_WPROT     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_VO0_656_0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_PPKT_I_DATA_0   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_TP_IN_17        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_PM_GPIO_123     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_122 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_122_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_122_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_122_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_122_GPIO_122        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_122_SDIO0_CMD       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_122_VO0_656_CLK     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_122_TP_IN_16        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_122_PM_GPIO_122     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_118 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_GPIO_118        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_PKT4_SYNC       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_I2S_LR0_IN      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_I2S_LR0_OUT     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_EXT_IRQB_2      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_HD_DVI0_11      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SC1_AUX2        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_MTSIF0_DATA7    7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_ALT_TP_IN_17    8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_PM_GPIO_118     9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_117 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_GPIO_117        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_PKT4_DATA       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_I2S_DATA0_IN    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_I2S_DATA0_OUT   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_EXT_IRQB_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_HD_DVI0_20      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SC1_AUX1        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_MTSIF0_DATA6    7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_ALT_TP_IN_16    8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_PM_GPIO_117     9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_116 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_GPIO_116        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_PKT4_CLK        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_I2S_CLK0_IN     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_I2S_CLK0_OUT    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_EXT_IRQB_0      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_HD_DVI0_21      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SC1_VPP         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_MTSIF_ATS_INC   7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_ALT_TP_IN_15    8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_PM_GPIO_116     9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_114 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_GPIO_114        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_ENET0_ACTIVITY  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_PWM1            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_CLK_OBSRV       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_CLK_27M         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_AUD_FS_CLK0     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_SC_CLK_OUT      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_ENET1_ACTIVITY  7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_ENET1_LINK      8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_PM_GPIO_114     9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_113 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_GPIO_113        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_USB3_PWRFLT     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_RMX1_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_ALT_TP_IN_14    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_PM_GPIO_113     4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_15 - Pinmux control register 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_132 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_GPIO_132        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_MII_RX_DV       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_EBI_ADDR16      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_HD_DVI0_24      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_MTSIF0_DATA0    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_PM_GPIO_132     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_131 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_GPIO_131        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_SDIO0_LED       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_VEC_HSYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_SD1_PWR0        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_ALT_TP_IN_19    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_PM_GPIO_131     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_130 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_GPIO_130        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_SDIO0_PRES      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_I2S_LR0_IN      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_VO0_656_7       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_PPKT_I_DATA_7   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_ALT_TP_IN_18    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_PM_GPIO_130     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_129 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_GPIO_129        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_SDIO0_DAT3      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_I2S_DATA0_IN    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_VO0_656_6       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_PPKT_I_DATA_6   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_TP_IN_23        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_PM_GPIO_129     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_128 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_GPIO_128        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_SDIO0_DAT2      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_I2S_CLK0_IN     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_VO0_656_5       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_PPKT_I_DATA_5   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_TP_IN_22        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_PM_GPIO_128     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_127 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_GPIO_127        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_SDIO0_DAT1      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_I2S_LR0_OUT     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_VO0_656_4       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_PPKT_I_DATA_4   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_TP_IN_21        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_PM_GPIO_127     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_126 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_126_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_126_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_126_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_126_GPIO_126        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_126_SDIO0_DAT0      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_126_I2S_DATA0_OUT   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_126_VO0_656_3       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_126_PPKT_I_DATA_3   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_126_TP_IN_20        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_126_PM_GPIO_126     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_125 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_125_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_125_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_125_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_125_GPIO_125        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_125_SDIO0_CLK       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_125_I2S_CLK0_OUT    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_125_VO0_656_2       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_125_PPKT_I_DATA_2   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_125_TP_IN_19        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_125_PM_GPIO_125     6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_16 - Pinmux control register 16
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_140 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_GPIO_140        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_MII_RXD_02      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_EBI_ADDR20      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_SPI_M_SCK       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_HD_DVI0_HS      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_PM_GPIO_140     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_139 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_GPIO_139        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_MII_RXD_03      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_EBI_ADDR19      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_SPI_M_SS0B      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_MTSIF0_DATA2    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_PM_GPIO_139     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_138 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_GPIO_138        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_MII_TX_CLK      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_EBI_ADDR18      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_SPI_M_MISO      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_HD_DVI0_CLK     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_MTSIF0_DATA3    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_PM_GPIO_138     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_137 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_137_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_137_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_137_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_137_GPIO_137        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_137_MII_MDIO        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_137_MTSIF_ATS_INC   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_137_TP_IN_27        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_137_PM_GPIO_137     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_136 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_GPIO_136        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_MII_CRS         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_EBI_ADDR15      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_POD_EBI_RDB     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_PKT4_SYNC       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_HD_DVI0_18      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_MTSIF_ATS_RST   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_TP_IN_26        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_PM_GPIO_136     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_135 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_GPIO_135        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_MII_COL         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_POD_EBI_DSB     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_PKT4_DATA       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_HD_DVI0_19      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_SD1_WPROT       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_TP_IN_25        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_PM_GPIO_135     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_134 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_134_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_134_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_134_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_134_GPIO_134        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_134_MII_RX_CLK      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_134_EBI_ADDR17      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_134_HD_DVI0_22      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_134_MTSIF0_CLK      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_134_PM_GPIO_134     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_133 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_133_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_133_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_133_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_133_GPIO_133        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_133_MII_RX_ER       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_133_POD_EBI_WE0B    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_133_PKT4_CLK        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_133_HD_DVI0_23      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_133_SD1_PRES        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_133_TP_IN_24        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_133_PM_GPIO_133     7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_17 - Pinmux control register 17
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_148 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_GPIO_148        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_MII_TX_ER       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_POD2CHIP_MCLKI  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_HD_DVI0_25      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_TP_IN_28        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_PM_GPIO_148     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_147 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_GPIO_147        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_MII_TX_EN       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_EBI_ADDR27      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_SPI_M_MOSI      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_PM_GPIO_147     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_146 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_GPIO_146        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_MII_TXD_00      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_EBI_ADDR26      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_SC1_IO          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_HD_DVI0_26      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_MTSIF0_DATA4    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_PM_GPIO_146     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_145 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_GPIO_145        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_MII_TXD_01      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_EBI_ADDR25      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_SC1_RST         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_HD_DVI0_27      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_MTSIF0_DATA5    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_PM_GPIO_145     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_144 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_GPIO_144        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_MII_TXD_02      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_EBI_ADDR24      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_SC1_CLK         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_HD_DVI0_28      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_MTSIF0_DATA6    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_PM_GPIO_144     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_143 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_GPIO_143        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_MII_TXD_03      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_EBI_ADDR23      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_SC1_VCC         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_HD_DVI0_29      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_MTSIF0_DATA7    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_PM_GPIO_143     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_142 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_142_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_142_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_142_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_142_GPIO_142        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_142_MII_RXD_00      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_142_EBI_ADDR22      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_142_SC1_PRES        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_142_HD_DVI0_DE      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_142_MTSIF0_SYNC     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_142_PM_GPIO_142     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_141 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_141_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_141_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_141_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_141_GPIO_141        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_141_MII_RXD_01      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_141_EBI_ADDR21      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_141_HD_DVI0_VS      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_141_MTSIF0_DATA1    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_141_PM_GPIO_141     5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_18 - Pinmux control register 18
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: reserved0 [31:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_reserved0_MASK           0xfff00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_reserved0_SHIFT          20
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: sgpio_03 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_03_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_03_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_03_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_03_SGPIO_03        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_03_BSC_M4_SDA      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_03_EXT_IRQB_1      2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: sgpio_02 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_02_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_02_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_02_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_02_SGPIO_02        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_02_BSC_M4_SCL      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: sgpio_01 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_01_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_01_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_01_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_01_SGPIO_01        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_01_BSC_M3_SDA      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_01_EXT_IRQB_1      2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: sgpio_00 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_00_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_00_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_00_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_00_SGPIO_00        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_00_BSC_M3_SCL      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_149 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_149_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_149_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_149_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_149_GPIO_149        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_149_MII_MDC         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_149_SPI_M_SCK       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_149_TP_IN_31        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_149_PM_GPIO_149     4
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_005_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_005_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_005_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_005_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_005_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_005_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_005_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_004_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_004_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_004_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_004_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_004_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_004_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_004_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_003_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_003_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_003_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_003_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_003_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_003_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_003_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_002_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_002_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_002_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_002_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_002_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_002_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_002_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_001_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_001_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_001_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_001_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_001_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_001_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_001_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_000_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_000_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_000_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_000_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_000_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_000_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_000_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [17:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x0003c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       14
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: vcxo27a_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_vcxo27a_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_vcxo27a_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_vcxo27a_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_vcxo27a_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_vcxo27a_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_vcxo27a_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: clk27_out_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_clk27_out_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_clk27_out_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_clk27_out_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_clk27_out_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_clk27_out_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_clk27_out_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_wpb_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_wpb_pad_ctrl_MASK  0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_wpb_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_wpb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_wpb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_wpb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_wpb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_holdb_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_holdb_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_holdb_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_holdb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_holdb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_holdb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_holdb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_sck_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_MASK  0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_mosi_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_miso_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_020_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_020_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_020_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_020_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_020_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_020_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_020_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_019_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_019_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_019_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_019_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_019_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_019_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_019_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_018_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_018_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_018_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_018_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_018_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_018_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_018_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_017_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_017_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_017_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_017_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_017_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_017_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_017_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_016_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_016_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_016_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_016_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_016_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_016_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_016_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_015_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_015_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_015_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_015_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_015_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_015_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_015_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_014_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_014_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_014_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_014_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_014_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_014_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_014_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_013_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_013_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_013_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_013_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_013_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_013_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_013_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_012_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_012_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_012_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_012_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_012_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_012_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_012_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_011_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_011_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_011_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_011_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_011_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_011_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_011_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_010_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_010_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_010_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_010_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_010_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_010_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_010_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_009_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_009_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_009_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_009_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_009_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_009_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_009_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_008_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_008_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_008_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_008_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_008_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_008_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_008_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_007_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_007_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_007_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_007_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_007_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_007_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_007_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_006_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_006_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_006_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_006_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_006_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_006_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_006_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_035_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_035_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_035_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_035_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_035_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_035_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_035_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_034_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_034_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_034_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_034_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_034_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_034_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_034_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_033_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_033_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_033_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_033_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_033_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_033_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_033_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_032_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_032_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_032_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_032_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_032_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_032_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_032_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_031_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_031_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_031_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_031_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_031_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_031_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_031_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_030_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_030_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_030_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_030_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_030_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_030_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_030_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_029_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_029_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_029_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_029_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_029_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_029_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_029_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_028_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_028_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_028_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_028_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_028_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_028_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_028_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_027_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_027_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_027_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_027_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_027_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_027_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_027_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_026_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_026_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_026_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_026_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_026_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_026_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_026_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_025_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_025_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_025_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_025_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_025_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_025_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_025_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_024_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_024_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_024_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_024_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_024_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_024_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_024_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_023_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_023_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_023_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_023_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_023_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_023_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_023_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_022_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_022_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_022_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_022_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_022_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_022_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_022_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_021_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_021_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_021_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_021_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_021_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_021_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_021_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_050_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_050_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_050_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_050_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_050_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_050_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_050_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_049_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_049_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_049_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_049_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_049_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_049_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_049_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_048_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_048_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_048_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_048_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_048_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_048_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_048_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_047_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_047_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_047_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_047_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_047_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_047_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_047_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_046_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_046_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_046_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_046_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_046_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_046_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_046_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_045_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_045_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_045_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_045_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_045_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_045_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_045_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_044_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_044_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_044_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_044_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_044_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_044_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_044_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_043_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_043_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_043_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_043_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_043_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_043_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_043_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_042_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_042_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_042_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_042_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_042_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_042_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_042_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_041_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_041_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_041_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_041_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_041_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_041_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_041_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_040_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_040_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_040_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_040_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_040_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_040_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_040_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_039_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_039_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_039_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_039_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_039_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_039_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_039_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_038_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_038_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_038_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_038_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_038_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_038_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_038_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_037_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_037_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_037_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_037_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_037_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_037_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_037_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_036_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_036_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_036_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_036_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_036_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_036_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_036_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_065_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_065_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_065_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_065_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_065_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_065_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_065_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_064_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_064_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_064_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_064_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_064_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_064_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_064_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_063_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_063_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_063_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_063_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_063_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_063_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_063_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_062_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_062_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_062_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_062_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_062_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_062_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_062_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_061_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_061_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_061_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_061_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_061_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_061_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_061_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_060_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_060_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_060_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_060_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_060_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_060_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_060_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_059_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_059_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_059_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_059_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_059_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_059_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_059_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_058_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_058_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_058_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_058_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_058_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_058_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_058_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_057_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_057_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_057_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_057_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_057_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_057_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_057_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_056_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_056_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_056_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_056_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_056_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_056_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_056_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_055_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_055_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_055_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_055_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_055_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_055_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_055_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_054_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_054_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_054_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_054_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_054_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_054_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_054_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_053_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_053_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_053_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_053_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_053_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_053_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_053_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_052_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_052_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_052_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_052_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_052_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_052_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_052_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_051_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_051_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_051_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_051_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_051_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_051_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_051_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_080_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_080_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_080_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_080_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_080_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_080_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_080_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_079_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_079_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_079_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_079_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_079_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_079_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_079_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_078_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_078_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_078_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_078_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_078_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_078_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_078_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_077_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_077_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_077_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_077_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_077_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_077_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_077_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_076_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_076_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_076_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_076_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_076_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_076_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_076_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_075_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_075_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_075_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_075_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_075_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_075_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_075_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_074_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_074_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_074_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_074_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_074_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_074_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_074_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_073_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_073_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_073_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_073_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_073_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_073_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_073_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_072_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_072_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_072_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_072_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_072_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_072_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_072_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_071_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_071_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_071_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_071_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_071_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_071_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_071_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_070_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_070_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_070_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_070_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_070_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_070_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_070_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_069_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_069_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_069_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_069_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_069_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_069_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_069_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_068_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_068_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_068_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_068_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_068_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_068_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_068_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_067_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_067_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_067_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_067_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_067_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_067_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_067_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_066_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_066_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_066_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_066_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_066_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_066_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_066_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_095_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_095_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_095_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_095_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_095_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_095_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_095_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_094_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_094_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_094_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_094_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_094_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_094_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_094_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_093_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_093_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_093_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_093_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_093_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_093_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_093_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_092_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_092_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_092_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_092_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_092_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_092_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_092_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_091_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_091_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_091_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_091_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_091_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_091_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_091_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_090_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_090_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_090_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_090_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_090_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_090_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_090_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_089_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_089_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_089_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_089_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_089_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_089_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_089_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_088_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_088_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_088_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_088_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_088_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_088_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_088_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_087_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_087_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_087_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_087_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_087_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_087_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_087_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_086_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_086_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_086_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_086_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_086_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_086_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_086_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_085_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_085_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_085_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_085_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_085_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_085_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_085_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_084_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_084_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_084_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_084_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_084_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_084_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_084_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_083_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_083_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_083_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_083_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_083_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_083_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_083_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_082_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_082_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_082_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_082_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_082_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_082_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_082_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_081_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_081_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_081_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_081_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_081_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_081_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_081_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_110_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_109_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_108_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_107_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_106_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_106_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_106_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_106_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_106_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_106_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_106_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_105_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_104_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_103_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_102_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_101_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_100_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_100_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_100_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_100_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_100_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_100_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_100_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_099_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_099_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_099_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_099_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_099_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_099_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_099_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_098_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_098_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_098_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_098_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_098_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_098_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_098_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_097_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_097_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_097_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_097_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_097_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_097_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_097_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_096_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_096_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_096_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_096_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_096_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_096_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_096_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_129_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_129_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_129_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_129_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_129_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_129_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_129_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_128_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_128_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_128_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_128_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_128_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_128_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_128_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_127_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_127_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_127_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_127_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_127_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_127_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_127_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_126_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_126_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_126_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_126_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_126_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_126_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_126_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_125_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_125_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_125_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_125_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_125_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_125_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_125_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_124_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_123_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_122_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_118_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_117_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_116_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_116_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_116_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_116_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_116_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_116_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_116_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_114_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_114_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_114_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_114_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_114_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_114_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_114_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_113_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_113_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_113_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_113_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_113_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_113_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_113_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_112_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_112_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_112_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_112_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_112_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_112_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_112_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_111_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_111_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_111_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_111_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_111_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_111_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_111_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_9 - Pad pull-up/pull-down control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: spare_pad_ctrl_9 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_144_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_144_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_144_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_144_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_144_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_144_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_144_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_143_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_143_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_143_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_143_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_143_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_143_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_143_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_142_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_142_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_142_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_142_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_142_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_142_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_142_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_141_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_141_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_141_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_141_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_141_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_141_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_141_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_140_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_140_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_140_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_140_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_140_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_140_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_140_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_139_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_139_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_139_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_139_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_139_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_139_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_139_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_138_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_138_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_138_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_138_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_138_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_138_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_138_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_137_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_137_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_137_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_137_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_137_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_137_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_137_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_136_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_136_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_136_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_136_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_136_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_136_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_136_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_135_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_135_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_135_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_135_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_135_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_135_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_135_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_134_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_134_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_134_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_134_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_134_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_134_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_134_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_133_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_133_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_133_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_133_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_133_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_133_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_133_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_132_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_132_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_132_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_132_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_132_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_132_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_132_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_131_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_131_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_131_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_131_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_131_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_131_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_131_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_130_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_130_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_130_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_130_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_130_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_130_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_130_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_10 - Pad pull-up/pull-down control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: reserved0 [31:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_reserved0_MASK       0xfff00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_reserved0_SHIFT      20
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: spare_pad_ctrl_10 [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: reserved1 [17:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_reserved1_MASK       0x0003fc00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_reserved1_SHIFT      10
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_149_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_149_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_149_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_149_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_149_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_149_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_149_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_148_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_148_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_148_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_148_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_148_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_148_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_148_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_147_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_147_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_147_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_147_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_147_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_147_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_147_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_146_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_146_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_146_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_146_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_146_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_146_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_146_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_145_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_145_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_145_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_145_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_145_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_145_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_145_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xffffff00
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       8
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_01 [07:07] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_00 [06:06] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_111 [05:05] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_111_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_111_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_111_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_065 [04:04] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_065_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_065_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_065_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_024 [03:03] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_024_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_024_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_024_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_023 [02:02] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_023_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_023_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_023_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_020 [01:01] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_020_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_020_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_020_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_015 [00:00] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_015_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_015_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_015_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_CTRL - Reset control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0xfffffffe
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               1
+
+/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT   0x00000000
+
+/***************************************************************************
+ *RESET_SOURCE_ENABLE - Reset source enable
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK       0xfffffc00
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT      10
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_MASTER_RESET - Software master reset
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK           0xfffffffe
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT          1
+
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HW_RESET_EXTENSION - Hardware reset extension
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_MONITOR - Reset Monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT  7
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT   6
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT   4
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset history
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:17] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xfffe0000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            17
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [16:16] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 16
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [15:15] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 15
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [14:14] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 14
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [13:13] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 13
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_reset [12:12] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_MASK    0x00001000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT   12
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_reset [11:11] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT    11
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [10:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT       10
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK       0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT      9
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_dl_sw_reset [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK  0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT 8
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 7
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 6
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK   0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT  4
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0
+
+/***************************************************************************
+ *SW_INIT_0_SET - Software init 0 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_MASK           0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_SHIFT          31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_MASK   0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_SHIFT  30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_MASK          0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_MASK          0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_SHIFT         28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_MASK        0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_SHIFT       27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK        0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT       26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_MASK          0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_SHIFT         25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK          0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK   0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT  23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_MASK   0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_SHIFT  22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK          0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT         21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_MASK   0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_SHIFT  20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK         0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT        19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK           0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT          18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK   0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT  17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_MASK         0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_SHIFT        16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK           0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT          15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK           0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT          14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_MASK   0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_SHIFT  13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_MASK          0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_MASK        0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_SHIFT       11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT       10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK           0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT          9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK           0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK           0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT          6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_SHIFT   4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT   0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_CLEAR - Software init 0 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_MASK         0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_SHIFT        31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_MASK        0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_SHIFT       29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_MASK        0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_SHIFT       28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_MASK      0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_SHIFT     27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK      0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT     26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_MASK        0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_SHIFT       25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK        0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT       24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK        0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT       21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK       0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT      19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK         0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT        18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_MASK       0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK         0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT        15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK         0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT        14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_MASK        0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_SHIFT       12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_MASK      0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_SHIFT     11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK      0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT     10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK         0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT        9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK         0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK         0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT        6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_STATUS - Software init 0 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_MASK        0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_SHIFT       31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_MASK       0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_SHIFT      29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_MASK       0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_SHIFT      28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_MASK       0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_SHIFT      25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK       0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK       0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT      21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK      0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT     19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK        0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT       18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_MASK      0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK        0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT       15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK        0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT       14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_MASK       0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK        0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT   2
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT       1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_MASK   0x80000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT  31
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_MASK  0x20000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_MASK  0x10000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_MASK  0x02000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK  0x01000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK  0x00200000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK   0x00040000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT  18
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK   0x00008000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT  15
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK   0x00004000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT  14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_svd0_sw_init_MASK  0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK   0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT  9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK   0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT  8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT  6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_1_SET - Software init 1 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK             0xfffffff8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT            3
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK        0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT       2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT       1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_DEFAULT        0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_CLEAR - Software init 1 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK           0xfffffff8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT          3
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_MASK         0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_STATUS - Software init 1 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK          0xfffffff8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT         3
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK     0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT    1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_DEFAULT     0x00000001
+
+/***************************************************************************
+ *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK     0xfffffff8
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT    3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_SHIFT  0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xfffffff8
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK   0xfffffff8
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT  3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK  0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xfffffff8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 3
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xfffffff8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 3
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL - Spare control bits reserved for future use
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT         0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTRL - Test port control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SOFT_MODEM_TP 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_ICID_TP_OUT 14
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0  0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET1  1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU     2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SATA    3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RFM     4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS     16
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK     17
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON     18
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     20
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     21
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE    22
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM    23
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC     25
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SVD0    27
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GFX     29
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO     30
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA   31
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     33
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0   35
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0    45
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB1    46
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MOCA    47
+
+/***************************************************************************
+ *TEST_PORT_OUT_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_OUT_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TEST_PORT_IN_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EJTAG_INPUT_EN - EJTAG input bus enables
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xffffffe0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           5
+
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [04:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x0000001f
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA0_CPU_ONE_HOT 4
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA1_CPU_ONE_HOT 8
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 16
+
+/***************************************************************************
+ *EJTAG_OUTPUT_SEL - EJTAG output select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         3
+
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA0_CPU 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA1_CPU 3
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 4
+
+/***************************************************************************
+ *UART_ROUTER_SEL - UART Router select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK      0xf0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT     28
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK      0x0f000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT     24
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK      0x00f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK      0x000f0000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK      0x0000f000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK      0x00000f00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK      0x0000000f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15
+
+/***************************************************************************
+ *VTRAP_CTRL - VTRAP Control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK                0xfffff000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT               12
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_threshold [11:11] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_threshold [10:10] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_threshold [09:09] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [08:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x000001f8
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 0x00000018
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_status_clear [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_status_clear [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_status_clear [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VTRAP_STATUS - VTRAP Status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK              0xfffffff8
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT             3
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_status [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_status [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_status [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SSP_CONFIG - Serial Slave Port configuration register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT        0x00000004
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT           0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT     0x00000001
+
+/***************************************************************************
+ *SERS_REV - SERS Revision Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16
+
+/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT     0x00000000
+
+/***************************************************************************
+ *SERS_CFG - SERS Configuration Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT                0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT           0x00000000
+
+/* union - case mapped_buffer_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0x00000000
+
+/* union - case cmd_fifo_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 0x0000001f
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 0x00000010
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT                 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x00404428
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0
+
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x00404448
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0
+
+
+/***************************************************************************
+ *RO_TEST_BLOCK_SEL - Block select for RO testmode
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xffffffe0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        5
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_pwenb [04:04] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DEFAULT  0x00000001
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_ENABLED  0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DISABLED 1
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [03:02] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MIN_LOAD 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MED_LOAD 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MAX_LOAD 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SVT_MIN_LOAD 3
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
+
+/***************************************************************************
+ *TEST_CONFIGURATION - Test configuration
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_timer.h b/include/linux/brcmstb/7429b0/bchp_timer.h
new file mode 100644
index 0000000..87257d4
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_timer.h
@@ -0,0 +1,337 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:15 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_TIMER_H__
+#define BCHP_TIMER_H__
+
+/***************************************************************************
+ *TIMER - Watchdog & Programmable Timers
+ ***************************************************************************/
+#define BCHP_TIMER_TIMER_IS                      0x004066c0 /* TIMER INTERRUPT STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE0                     0x004066c4 /* TIMER CPU INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_TIMER0_CTRL                   0x004066c8 /* TIMER0 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER1_CTRL                   0x004066cc /* TIMER1 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER2_CTRL                   0x004066d0 /* TIMER2 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER3_CTRL                   0x004066d4 /* TIMER3 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER0_STAT                   0x004066d8 /* TIMER0 STATUS REGISTER */
+#define BCHP_TIMER_TIMER1_STAT                   0x004066dc /* TIMER1 STATUS REGISTER */
+#define BCHP_TIMER_TIMER2_STAT                   0x004066e0 /* TIMER2 STATUS REGISTER */
+#define BCHP_TIMER_TIMER3_STAT                   0x004066e4 /* TIMER3 STATUS REGISTER */
+#define BCHP_TIMER_WDTIMEOUT                     0x004066e8 /* WATCHDOG TIMEOUT REGISTER */
+#define BCHP_TIMER_WDCMD                         0x004066ec /* WATCHDOG COMMAND REGISTER */
+#define BCHP_TIMER_WDCHIPRST_CNT                 0x004066f0 /* WATCHDOG CHIP RESET COUNT REGISTER */
+#define BCHP_TIMER_WDCRS                         0x004066f4 /* WATCHDOG CHIP RESET STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE1                     0x004066f8 /* TIMER PCI INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_WDCTRL                        0x004066fc /* WATCHDOG CONTROL REGISTER */
+
+/***************************************************************************
+ *TIMER_IS - TIMER INTERRUPT STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IS :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IS_reserved0_MASK                         0xffffffe0
+#define BCHP_TIMER_TIMER_IS_reserved0_SHIFT                        5
+
+/* TIMER :: TIMER_IS :: WDINT [04:04] */
+#define BCHP_TIMER_TIMER_IS_WDINT_MASK                             0x00000010
+#define BCHP_TIMER_TIMER_IS_WDINT_SHIFT                            4
+#define BCHP_TIMER_TIMER_IS_WDINT_DEFAULT                          0x00000000
+
+/* TIMER :: TIMER_IS :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IS_TMR3TO_MASK                            0x00000008
+#define BCHP_TIMER_TIMER_IS_TMR3TO_SHIFT                           3
+#define BCHP_TIMER_TIMER_IS_TMR3TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IS_TMR2TO_MASK                            0x00000004
+#define BCHP_TIMER_TIMER_IS_TMR2TO_SHIFT                           2
+#define BCHP_TIMER_TIMER_IS_TMR2TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IS_TMR1TO_MASK                            0x00000002
+#define BCHP_TIMER_TIMER_IS_TMR1TO_SHIFT                           1
+#define BCHP_TIMER_TIMER_IS_TMR1TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IS_TMR0TO_MASK                            0x00000001
+#define BCHP_TIMER_TIMER_IS_TMR0TO_SHIFT                           0
+#define BCHP_TIMER_TIMER_IS_TMR0TO_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *TIMER_IE0 - TIMER CPU INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE0 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE0_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE0_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE0 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_DEFAULT                     0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *TIMER0_CTRL - TIMER0 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER0_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER0_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER0_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER0_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER0_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER0_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER0_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER0_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER1_CTRL - TIMER1 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER1_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER1_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER1_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER1_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER1_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER1_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER1_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER1_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER2_CTRL - TIMER2 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER2_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER2_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER2_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER2_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER2_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER2_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER2_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER2_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER3_CTRL - TIMER3 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER3_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER3_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER3_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER3_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER3_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER3_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER3_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER3_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER0_STAT - TIMER0 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER0_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER0_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER0_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER1_STAT - TIMER1 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER1_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER1_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER1_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER2_STAT - TIMER2 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER2_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER2_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER2_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER3_STAT - TIMER3 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER3_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER3_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER3_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *WDTIMEOUT - WATCHDOG TIMEOUT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDTIMEOUT :: WDTIMEOUT_VAL [31:00] */
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_MASK                    0xffffffff
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *WDCMD - WATCHDOG COMMAND REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCMD :: WDCMD [31:00] */
+#define BCHP_TIMER_WDCMD_WDCMD_MASK                                0xffffffff
+#define BCHP_TIMER_WDCMD_WDCMD_SHIFT                               0
+#define BCHP_TIMER_WDCMD_WDCMD_DEFAULT                             0x00000000
+
+/***************************************************************************
+ *WDCHIPRST_CNT - WATCHDOG CHIP RESET COUNT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCHIPRST_CNT :: reserved0 [31:26] */
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_MASK                    0xfc000000
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_SHIFT                   26
+
+/* TIMER :: WDCHIPRST_CNT :: WDCHIPRST_CNT [25:00] */
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_MASK                0x03ffffff
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_SHIFT               0
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_DEFAULT             0x02ffffff
+
+/***************************************************************************
+ *WDCRS - WATCHDOG CHIP RESET STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCRS :: reserved0 [31:01] */
+#define BCHP_TIMER_WDCRS_reserved0_MASK                            0xfffffffe
+#define BCHP_TIMER_WDCRS_reserved0_SHIFT                           1
+
+/* TIMER :: WDCRS :: WDCR [00:00] */
+#define BCHP_TIMER_WDCRS_WDCR_MASK                                 0x00000001
+#define BCHP_TIMER_WDCRS_WDCR_SHIFT                                0
+#define BCHP_TIMER_WDCRS_WDCR_DEFAULT                              0x00000000
+
+/***************************************************************************
+ *TIMER_IE1 - TIMER PCI INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE1 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE1_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE1_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE1 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_DEFAULT                     0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *WDCTRL - WATCHDOG CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCTRL :: reserved0 [31:03] */
+#define BCHP_TIMER_WDCTRL_reserved0_MASK                           0xfffffff8
+#define BCHP_TIMER_WDCTRL_reserved0_SHIFT                          3
+
+/* TIMER :: WDCTRL :: WD_COUNT_MODE [02:02] */
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_MASK                       0x00000004
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_SHIFT                      2
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_DEFAULT                    0x00000000
+
+/* TIMER :: WDCTRL :: WD_EVENT_MODE [01:00] */
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_MASK                       0x00000003
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_SHIFT                      0
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_DEFAULT                    0x00000000
+
+#endif /* #ifndef BCHP_TIMER_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_uarta.h b/include/linux/brcmstb/7429b0/bchp_uarta.h
new file mode 100644
index 0000000..de14729
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_uarta.h
@@ -0,0 +1,391 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:17 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTA_H__
+#define BCHP_UARTA_H__
+
+/***************************************************************************
+ *UARTA - UART A
+ ***************************************************************************/
+#define BCHP_UARTA_RBR                           0x00406700 /* Receive Buffer Register */
+#define BCHP_UARTA_THR                           0x00406700 /* Transmit Holding Register */
+#define BCHP_UARTA_DLH                           0x00406704 /* Divisor Latch High */
+#define BCHP_UARTA_DLL                           0x00406700 /* Divisor Latch Low */
+#define BCHP_UARTA_IER                           0x00406704 /* Interrupt Enable Register */
+#define BCHP_UARTA_IIR                           0x00406708 /* Interrupt Identity Register */
+#define BCHP_UARTA_FCR                           0x00406708 /* FIFO Control Register */
+#define BCHP_UARTA_LCR                           0x0040670c /* Line Control Register */
+#define BCHP_UARTA_MCR                           0x00406710 /* Modem Control Register */
+#define BCHP_UARTA_LSR                           0x00406714 /* Line Status Register */
+#define BCHP_UARTA_MSR                           0x00406718 /* Modem Status Register */
+#define BCHP_UARTA_SCR                           0x0040671c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTA :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTA_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_RBR_reserved0_SHIFT                             8
+
+/* UARTA :: RBR :: RBR [07:00] */
+#define BCHP_UARTA_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTA_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTA_RBR_RBR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTA :: THR :: reserved0 [31:08] */
+#define BCHP_UARTA_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_THR_reserved0_SHIFT                             8
+
+/* UARTA :: THR :: THR [07:00] */
+#define BCHP_UARTA_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTA_THR_THR_SHIFT                                   0
+#define BCHP_UARTA_THR_THR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTA :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTA_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLH_reserved0_SHIFT                             8
+
+/* UARTA :: DLH :: DLH [07:00] */
+#define BCHP_UARTA_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTA_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTA_DLH_DLH_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTA :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTA_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLL_reserved0_SHIFT                             8
+
+/* UARTA :: DLL :: DLL [07:00] */
+#define BCHP_UARTA_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTA_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTA_DLL_DLL_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTA :: IER :: reserved0 [31:08] */
+#define BCHP_UARTA_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IER_reserved0_SHIFT                             8
+
+/* UARTA :: IER :: PTIME [07:07] */
+#define BCHP_UARTA_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTA_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTA_IER_PTIME_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: reserved1 [06:04] */
+#define BCHP_UARTA_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTA_IER_reserved1_SHIFT                             4
+
+/* UARTA :: IER :: EDSSI [03:03] */
+#define BCHP_UARTA_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTA_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTA_IER_EDSSI_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: ELSI [02:02] */
+#define BCHP_UARTA_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTA_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTA_IER_ELSI_DEFAULT                                0x00000000
+
+/* UARTA :: IER :: ETBEI [01:01] */
+#define BCHP_UARTA_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTA_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTA_IER_ETBEI_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: ERBFI [00:00] */
+#define BCHP_UARTA_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTA_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTA_IER_ERBFI_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTA :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTA_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IIR_reserved0_SHIFT                             8
+
+/* UARTA :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTA_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTA_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTA_IIR_FIFOSE_DEFAULT                              0x00000000
+
+/* UARTA :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTA_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTA_IIR_reserved1_SHIFT                             4
+
+/* UARTA :: IIR :: IID [03:00] */
+#define BCHP_UARTA_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTA_IIR_IID_SHIFT                                   0
+#define BCHP_UARTA_IIR_IID_DEFAULT                                 0x00000001
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTA :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTA_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_FCR_reserved0_SHIFT                             8
+
+/* UARTA :: FCR :: RT [07:06] */
+#define BCHP_UARTA_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTA_FCR_RT_SHIFT                                    6
+#define BCHP_UARTA_FCR_RT_DEFAULT                                  0x00000000
+
+/* UARTA :: FCR :: TET [05:04] */
+#define BCHP_UARTA_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTA_FCR_TET_SHIFT                                   4
+#define BCHP_UARTA_FCR_TET_DEFAULT                                 0x00000000
+
+/* UARTA :: FCR :: DMAM [03:03] */
+#define BCHP_UARTA_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTA_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTA_FCR_DMAM_DEFAULT                                0x00000000
+
+/* UARTA :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTA_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTA_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTA_FCR_XFIFOR_DEFAULT                              0x00000000
+
+/* UARTA :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTA_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTA_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTA_FCR_RFIFOR_DEFAULT                              0x00000000
+
+/* UARTA :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTA_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTA_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTA_FCR_FIFOE_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTA :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTA_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LCR_reserved0_SHIFT                             8
+
+/* UARTA :: LCR :: DLAB [07:07] */
+#define BCHP_UARTA_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTA_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTA_LCR_DLAB_DEFAULT                                0x00000000
+
+/* UARTA :: LCR :: BC [06:06] */
+#define BCHP_UARTA_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTA_LCR_BC_SHIFT                                    6
+#define BCHP_UARTA_LCR_BC_DEFAULT                                  0x00000000
+
+/* UARTA :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTA_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTA_LCR_reserved1_SHIFT                             5
+
+/* UARTA :: LCR :: EPS [04:04] */
+#define BCHP_UARTA_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTA_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTA_LCR_EPS_DEFAULT                                 0x00000000
+
+/* UARTA :: LCR :: PEN [03:03] */
+#define BCHP_UARTA_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTA_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTA_LCR_PEN_DEFAULT                                 0x00000000
+
+/* UARTA :: LCR :: STOP [02:02] */
+#define BCHP_UARTA_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTA_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTA_LCR_STOP_DEFAULT                                0x00000000
+
+/* UARTA :: LCR :: DLS [01:00] */
+#define BCHP_UARTA_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTA_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTA_LCR_DLS_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTA :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTA_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTA_MCR_reserved0_SHIFT                             7
+
+/* UARTA :: MCR :: SIRE [06:06] */
+#define BCHP_UARTA_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTA_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTA_MCR_SIRE_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: AFCE [05:05] */
+#define BCHP_UARTA_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTA_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTA_MCR_AFCE_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: LB [04:04] */
+#define BCHP_UARTA_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTA_MCR_LB_SHIFT                                    4
+#define BCHP_UARTA_MCR_LB_DEFAULT                                  0x00000000
+
+/* UARTA :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTA_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTA_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTA_MCR_OUT2_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTA_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTA_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTA_MCR_OUT1_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: RTS [01:01] */
+#define BCHP_UARTA_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTA_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTA_MCR_RTS_DEFAULT                                 0x00000000
+
+/* UARTA :: MCR :: DTR [00:00] */
+#define BCHP_UARTA_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTA_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTA_MCR_DTR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTA :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTA_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LSR_reserved0_SHIFT                             8
+
+/* UARTA :: LSR :: RFE [07:07] */
+#define BCHP_UARTA_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTA_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTA_LSR_RFE_DEFAULT                                 0x00000000
+
+/* UARTA :: LSR :: TEMT [06:06] */
+#define BCHP_UARTA_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTA_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTA_LSR_TEMT_DEFAULT                                0x00000001
+
+/* UARTA :: LSR :: THRE [05:05] */
+#define BCHP_UARTA_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTA_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTA_LSR_THRE_DEFAULT                                0x00000001
+
+/* UARTA :: LSR :: BI [04:04] */
+#define BCHP_UARTA_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTA_LSR_BI_SHIFT                                    4
+#define BCHP_UARTA_LSR_BI_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: FE [03:03] */
+#define BCHP_UARTA_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTA_LSR_FE_SHIFT                                    3
+#define BCHP_UARTA_LSR_FE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: PE [02:02] */
+#define BCHP_UARTA_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTA_LSR_PE_SHIFT                                    2
+#define BCHP_UARTA_LSR_PE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: OE [01:01] */
+#define BCHP_UARTA_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTA_LSR_OE_SHIFT                                    1
+#define BCHP_UARTA_LSR_OE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: DR [00:00] */
+#define BCHP_UARTA_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTA_LSR_DR_SHIFT                                    0
+#define BCHP_UARTA_LSR_DR_DEFAULT                                  0x00000000
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTA :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTA_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_MSR_reserved0_SHIFT                             8
+
+/* UARTA :: MSR :: DCD [07:07] */
+#define BCHP_UARTA_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTA_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTA_MSR_DCD_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: RI [06:06] */
+#define BCHP_UARTA_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTA_MSR_RI_SHIFT                                    6
+#define BCHP_UARTA_MSR_RI_DEFAULT                                  0x00000000
+
+/* UARTA :: MSR :: DSR [05:05] */
+#define BCHP_UARTA_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTA_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTA_MSR_DSR_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: CTS [04:04] */
+#define BCHP_UARTA_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTA_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTA_MSR_CTS_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: DDCD [03:03] */
+#define BCHP_UARTA_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTA_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTA_MSR_DDCD_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: TERI [02:02] */
+#define BCHP_UARTA_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTA_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTA_MSR_TERI_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: DDSR [01:01] */
+#define BCHP_UARTA_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTA_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTA_MSR_DDSR_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: DCTS [00:00] */
+#define BCHP_UARTA_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTA_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTA_MSR_DCTS_DEFAULT                                0x00000000
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTA :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTA_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_SCR_reserved0_SHIFT                             8
+
+/* UARTA :: SCR :: SCR [07:00] */
+#define BCHP_UARTA_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTA_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTA_SCR_SCR_DEFAULT                                 0x00000000
+
+#endif /* #ifndef BCHP_UARTA_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_uartb.h b/include/linux/brcmstb/7429b0/bchp_uartb.h
new file mode 100644
index 0000000..3fec38b
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_uartb.h
@@ -0,0 +1,60 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jul 12 02:56:24 2011
+ *                 MD5 Checksum         c5a82bedc88d370fb68d7daceef9c302
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTB_H__
+#define BCHP_UARTB_H__
+
+/***************************************************************************
+ *UARTB - UART B
+ ***************************************************************************/
+#define BCHP_UARTB_RBR                           0x00406740 /* Receive Buffer Register */
+#define BCHP_UARTB_THR                           0x00406740 /* Transmit Holding Register */
+#define BCHP_UARTB_DLH                           0x00406744 /* Divisor Latch High */
+#define BCHP_UARTB_DLL                           0x00406740 /* Divisor Latch Low */
+#define BCHP_UARTB_IER                           0x00406744 /* Interrupt Enable Register */
+#define BCHP_UARTB_IIR                           0x00406748 /* Interrupt Identity Register */
+#define BCHP_UARTB_FCR                           0x00406748 /* FIFO Control Register */
+#define BCHP_UARTB_LCR                           0x0040674c /* Line Control Register */
+#define BCHP_UARTB_MCR                           0x00406750 /* Modem Control Register */
+#define BCHP_UARTB_LSR                           0x00406754 /* Line Status Register */
+#define BCHP_UARTB_MSR                           0x00406758 /* Modem Status Register */
+#define BCHP_UARTB_SCR                           0x0040675c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTB_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_uartc.h b/include/linux/brcmstb/7429b0/bchp_uartc.h
new file mode 100644
index 0000000..3a2dd29
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_uartc.h
@@ -0,0 +1,60 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jul 12 02:47:02 2011
+ *                 MD5 Checksum         c5a82bedc88d370fb68d7daceef9c302
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTC_H__
+#define BCHP_UARTC_H__
+
+/***************************************************************************
+ *UARTC - UART C
+ ***************************************************************************/
+#define BCHP_UARTC_RBR                           0x00406780 /* Receive Buffer Register */
+#define BCHP_UARTC_THR                           0x00406780 /* Transmit Holding Register */
+#define BCHP_UARTC_DLH                           0x00406784 /* Divisor Latch High */
+#define BCHP_UARTC_DLL                           0x00406780 /* Divisor Latch Low */
+#define BCHP_UARTC_IER                           0x00406784 /* Interrupt Enable Register */
+#define BCHP_UARTC_IIR                           0x00406788 /* Interrupt Identity Register */
+#define BCHP_UARTC_FCR                           0x00406788 /* FIFO Control Register */
+#define BCHP_UARTC_LCR                           0x0040678c /* Line Control Register */
+#define BCHP_UARTC_MCR                           0x00406790 /* Modem Control Register */
+#define BCHP_UARTC_LSR                           0x00406794 /* Line Status Register */
+#define BCHP_UARTC_MSR                           0x00406798 /* Modem Status Register */
+#define BCHP_UARTC_SCR                           0x0040679c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_usb1_ctrl.h b/include/linux/brcmstb/7429b0/bchp_usb1_ctrl.h
new file mode 100644
index 0000000..f343c90
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_usb1_ctrl.h
@@ -0,0 +1,66 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Feb 22 17:28:07 2011
+ *                 MD5 Checksum         13b50036766a17118468ab754c6bd032
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7425/rdb/b0/bchp_usb1_ctrl.h $
+ * 
+ * Hydra_Software_Devel/1   2/23/11 1:44p yuxiaz
+ * SW7425-112: Added rdb files for 7425 B0.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB1_CTRL_H__
+#define BCHP_USB1_CTRL_H__
+
+/***************************************************************************
+ *USB1_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB1_CTRL_SETUP                     0x00490200 /* Setup Register */
+#define BCHP_USB1_CTRL_PLL_CTL                   0x00490204 /* PLL Control Register */
+#define BCHP_USB1_CTRL_FLADJ_VALUE               0x00490208 /* Frame Adjust Value */
+#define BCHP_USB1_CTRL_EBRIDGE                   0x0049020c /* Control Register for EHCI Bridge */
+#define BCHP_USB1_CTRL_OBRIDGE                   0x00490210 /* Control Register for OHCI Bridge */
+#define BCHP_USB1_CTRL_MDIO                      0x00490214 /* MDIO Interface Programming Register */
+#define BCHP_USB1_CTRL_MDIO2                     0x00490218 /* MDIO Interface Read Register */
+#define BCHP_USB1_CTRL_TEST_PORT_CTL             0x0049021c /* Test Port Control Register */
+#define BCHP_USB1_CTRL_USB_SIMCTL                0x00490220 /* Simulation Register */
+#define BCHP_USB1_CTRL_USB_TESTCTL               0x00490224 /* Throutput Test Control */
+#define BCHP_USB1_CTRL_USB_TESTMON               0x00490228 /* Throughput Test Monitor */
+#define BCHP_USB1_CTRL_UTMI_CTL_1                0x0049022c /* UTMI Control Register */
+#define BCHP_USB1_CTRL_UTMI_CTL_2                0x00490230 /* UTMI Control 2 Register */
+#define BCHP_USB1_CTRL_SPARE1                    0x00490234 /* Spare1 Register for future use */
+#define BCHP_USB1_CTRL_SPARE2                    0x00490238 /* Spare2 Register for future use */
+
+#endif /* #ifndef BCHP_USB1_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_usb_ctrl.h b/include/linux/brcmstb/7429b0/bchp_usb_ctrl.h
new file mode 100644
index 0000000..3c4f3df
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_usb_ctrl.h
@@ -0,0 +1,672 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:16 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB_CTRL_H__
+#define BCHP_USB_CTRL_H__
+
+/***************************************************************************
+ *USB_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB_CTRL_SETUP                      0x00480200 /* Setup Register */
+#define BCHP_USB_CTRL_PLL_CTL                    0x00480204 /* PLL Control Register */
+#define BCHP_USB_CTRL_FLADJ_VALUE                0x00480208 /* Frame Adjust Value */
+#define BCHP_USB_CTRL_EBRIDGE                    0x0048020c /* Control Register for EHCI Bridge */
+#define BCHP_USB_CTRL_OBRIDGE                    0x00480210 /* Control Register for OHCI Bridge */
+#define BCHP_USB_CTRL_MDIO                       0x00480214 /* MDIO Interface Programming Register */
+#define BCHP_USB_CTRL_MDIO2                      0x00480218 /* MDIO Interface Read Register */
+#define BCHP_USB_CTRL_TEST_PORT_CTL              0x0048021c /* Test Port Control Register */
+#define BCHP_USB_CTRL_USB_SIMCTL                 0x00480220 /* Simulation Register */
+#define BCHP_USB_CTRL_USB_TESTCTL                0x00480224 /* Throutput Test Control */
+#define BCHP_USB_CTRL_USB_TESTMON                0x00480228 /* Throughput Test Monitor */
+#define BCHP_USB_CTRL_UTMI_CTL_1                 0x0048022c /* UTMI Control Register */
+#define BCHP_USB_CTRL_UTMI_CTL_2                 0x00480230 /* UTMI Control 2 Register */
+#define BCHP_USB_CTRL_SPARE1                     0x00480234 /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE2                     0x00480238 /* Spare2 Register for future use */
+
+/***************************************************************************
+ *SETUP - Setup Register
+ ***************************************************************************/
+/* USB_CTRL :: SETUP :: OC_DISABLE [31:28] */
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK                        0xf0000000
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT                       28
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: SRAM_CS_DIS [27:25] */
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_MASK                       0x0e000000
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_SHIFT                      25
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: SETUP_SPARE [24:15] */
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK                       0x01ff8000
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT                      15
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: scb_client_swap [14:14] */
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_MASK                   0x00004000
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_SHIFT                  14
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_DEFAULT                0x00000000
+
+/* USB_CTRL :: SETUP :: scb1_en [13:13] */
+#define BCHP_USB_CTRL_SETUP_scb1_en_MASK                           0x00002000
+#define BCHP_USB_CTRL_SETUP_scb1_en_SHIFT                          13
+#define BCHP_USB_CTRL_SETUP_scb1_en_DEFAULT                        0x00000000
+
+/* USB_CTRL :: SETUP :: async_expire_dis [12:12] */
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK                  0x00001000
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT                 12
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT               0x00000000
+
+/* USB_CTRL :: SETUP :: discon_intr_en [11:11] */
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_MASK                    0x00000800
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_SHIFT                   11
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: con_intr_en [10:10] */
+#define BCHP_USB_CTRL_SETUP_con_intr_en_MASK                       0x00000400
+#define BCHP_USB_CTRL_SETUP_con_intr_en_SHIFT                      10
+#define BCHP_USB_CTRL_SETUP_con_intr_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: soft_shutdown [09:09] */
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_MASK                     0x00000200
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_SHIFT                    9
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_DEFAULT                  0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK                    0x00000100
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT                   8
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK                       0x00000080
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT                      7
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: soft_reset [06:06] */
+#define BCHP_USB_CTRL_SETUP_soft_reset_MASK                        0x00000040
+#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT                       6
+#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: IPP [05:05] */
+#define BCHP_USB_CTRL_SETUP_IPP_MASK                               0x00000020
+#define BCHP_USB_CTRL_SETUP_IPP_SHIFT                              5
+#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: IOC [04:04] */
+#define BCHP_USB_CTRL_SETUP_IOC_MASK                               0x00000010
+#define BCHP_USB_CTRL_SETUP_IOC_SHIFT                              4
+#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: WABO [03:03] */
+#define BCHP_USB_CTRL_SETUP_WABO_MASK                              0x00000008
+#define BCHP_USB_CTRL_SETUP_WABO_SHIFT                             3
+#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNBO [02:02] */
+#define BCHP_USB_CTRL_SETUP_FNBO_MASK                              0x00000004
+#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT                             2
+#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNHW [01:01] */
+#define BCHP_USB_CTRL_SETUP_FNHW_MASK                              0x00000002
+#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT                             1
+#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: BABO [00:00] */
+#define BCHP_USB_CTRL_SETUP_BABO_MASK                              0x00000001
+#define BCHP_USB_CTRL_SETUP_BABO_SHIFT                             0
+#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *PLL_CTL - PLL Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK                  0x80000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT                 31
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT               0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK                      0x40000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT                     30
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                   0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK                      0x20000000
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                     29
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                   0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                     0x10000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                    28
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                  0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                  0x08000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                 27
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT               0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK                          0x07000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT                         24
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT                       0x00000003
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                   0x00800000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                  23
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK                          0x00700000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT                         20
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT                       0x00000003
+
+/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK                          0x000f0000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT                         16
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT                       0x0000000a
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE2 [15:15] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_MASK                   0x00008000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_SHIFT                  15
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_pdiv [14:12] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK                        0x00007000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT                       12
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                     0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                   0x00000c00
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                  10
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK                        0x000003ff
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT                       0
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                     0x00000028
+
+/***************************************************************************
+ *FLADJ_VALUE - Frame Adjust Value
+ ***************************************************************************/
+/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                   0xffffffff
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                  0
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT                0x000c0020
+
+/***************************************************************************
+ *EBRIDGE - Control Register for EHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_size_sel [28:28] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_DEFAULT                 0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *OBRIDGE - Control Register for OHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_size_sel [28:28] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_DEFAULT                 0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *MDIO - MDIO Interface Programming Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO :: MDIO_CLK_SEL [31:31] */
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_MASK                       0x80000000
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_SHIFT                      31
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_DEFAULT                    0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_XVER_SELECT [30:29] */
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_MASK                   0x60000000
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_SHIFT                  29
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_DEFAULT                0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_TERM_SELECT [28:28] */
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_MASK                   0x10000000
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_SHIFT                  28
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_DEFAULT                0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_FS_XVER_OWN [27:27] */
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_MASK                   0x08000000
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_SHIFT                  27
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_DEFAULT                0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_TESTMODE [26:26] */
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_MASK                      0x04000000
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_SHIFT                     26
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_DEFAULT                   0x00000000
+
+/* USB_CTRL :: MDIO :: WR_START [25:25] */
+#define BCHP_USB_CTRL_MDIO_WR_START_MASK                           0x02000000
+#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT                          25
+#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: RD_START [24:24] */
+#define BCHP_USB_CTRL_MDIO_RD_START_MASK                           0x01000000
+#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT                          24
+#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK                          0x00ff0000
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT                         16
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT                       0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK                          0x0000ffff
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT                         0
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *MDIO2 - MDIO Interface Read Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO2 :: SYNOPSIS_CORE_ID [31:16] */
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_MASK                  0xffff0000
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_SHIFT                 16
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_DEFAULT               0x0000270a
+
+/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK                      0x0000ffff
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                     0
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTL - Test Port Control Register
+ ***************************************************************************/
+/* USB_CTRL :: TEST_PORT_CTL :: TP_EN [31:31] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_MASK                     0x80000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_SHIFT                    31
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [30:26] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK               0x7c000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT              26
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb0_wr_data_sel [25:25] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_MASK          0x02000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_SHIFT         25
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_DEFAULT       0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [24:24] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK                0x01000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT               24
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt2_oe [23:23] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_MASK                0x00800000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_SHIFT               23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron1_tstsel [22:22] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_MASK             0x00400000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_SHIFT            22
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron2_tstsel [21:21] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_MASK             0x00200000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_SHIFT            21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: test_clksel [20:19] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_MASK               0x00180000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_SHIFT              19
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_tstsel [18:16] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_MASK             0x00070000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_SHIFT            16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: UTMI_TEST_SEL [15:08] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_MASK             0x0000ff00
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_SHIFT            8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                 0x000000ff
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT                0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *USB_SIMCTL - Simulation Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK                  0x80000000
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                 31
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK                0x40000000
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT               30
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: otg_scale_down_en [29:28] */
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_MASK            0x30000000
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_SHIFT           28
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK                    0x08000000
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT                   27
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK        0x04000000
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT       26
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT     0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:00] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                 0x03ffffff
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT                0
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT              0x00000000
+
+/***************************************************************************
+ *USB_TESTCTL - Throutput Test Control
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:23] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK              0xff800000
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT             23
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: CTRLLER_SEL [22:21] */
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_MASK                 0x00600000
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_SHIFT                21
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK                     0x00100000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                    20
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK                   0x00080000
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                  19
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT                0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK                    0x00070000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                   16
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK              0x0000fc00
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT             10
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK              0x000003ff
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT             0
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT           0x00000000
+
+/***************************************************************************
+ *USB_TESTMON - Throughput Test Monitor
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [31:00] */
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK                0xffffffff
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT               0
+
+/***************************************************************************
+ *UTMI_CTL_1 - UTMI Control Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB_P1 [31:31] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_MASK              0x80000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_SHIFT             31
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK             0x70000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT            28
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT          0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK_P1 [27:27] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_MASK                0x08000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_SHIFT               27
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE3 [26:25] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_MASK              0x06000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_SHIFT             25
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY_P1 [24:24] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_MASK                0x01000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_SHIFT               24
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK                0x00800000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT               23
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK                0x00400000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT               22
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK                0x00200000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT               21
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK                0x00100000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT               20
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                  0x000c0000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                 18
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT               0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT       0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK           0x00010000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT          16
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT        0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB [15:15] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_MASK                 0x00008000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_SHIFT                15
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_DEFAULT              0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK                0x00007000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT               12
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK [11:11] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_MASK                   0x00000800
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_SHIFT                  11
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE1 [10:09] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_MASK              0x00000600
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_SHIFT             9
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY [08:08] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_MASK                   0x00000100
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_SHIFT                  8
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                   0x00000080
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                  7
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                   0x00000040
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                  6
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                   0x00000020
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                  5
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                   0x00000010
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                  4
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK                     0x0000000c
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                    2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                  0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT          0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK              0x00000001
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT             0
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT           0x00000000
+
+/***************************************************************************
+ *UTMI_CTL_2 - UTMI Control 2 Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK               0xffffffff
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT              0
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SPARE1 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE1 :: SPARE1_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *SPARE2 - Spare2 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE2 :: SPARE2_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_DEFAULT                   0x00000000
+
+#endif /* #ifndef BCHP_USB_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/bchp_wktmr.h b/include/linux/brcmstb/7429b0/bchp_wktmr.h
new file mode 100644
index 0000000..ee25f65
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/bchp_wktmr.h
@@ -0,0 +1,105 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:07:14 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_WKTMR_H__
+#define BCHP_WKTMR_H__
+
+/***************************************************************************
+ *WKTMR - Wakeup timer
+ ***************************************************************************/
+#define BCHP_WKTMR_EVENT                         0x00409a80 /* Wakeup Timer Register */
+#define BCHP_WKTMR_COUNTER                       0x00409a84 /* Wakeup Counter */
+#define BCHP_WKTMR_ALARM                         0x00409a88 /* Wakeup Timer Alarm */
+#define BCHP_WKTMR_PRESCALER                     0x00409a8c /* Wakeup Timer Prescaler */
+#define BCHP_WKTMR_PRESCALER_VAL                 0x00409a90 /* Wakeup Timer Prescaler Value */
+
+/***************************************************************************
+ *EVENT - Wakeup Timer Register
+ ***************************************************************************/
+/* WKTMR :: EVENT :: reserved0 [31:01] */
+#define BCHP_WKTMR_EVENT_reserved0_MASK                            0xfffffffe
+#define BCHP_WKTMR_EVENT_reserved0_SHIFT                           1
+
+/* WKTMR :: EVENT :: wktmr_alarm_event [00:00] */
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_MASK                    0x00000001
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_SHIFT                   0
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *COUNTER - Wakeup Counter
+ ***************************************************************************/
+/* WKTMR :: COUNTER :: wktmr_counter [31:00] */
+#define BCHP_WKTMR_COUNTER_wktmr_counter_MASK                      0xffffffff
+#define BCHP_WKTMR_COUNTER_wktmr_counter_SHIFT                     0
+#define BCHP_WKTMR_COUNTER_wktmr_counter_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *ALARM - Wakeup Timer Alarm
+ ***************************************************************************/
+/* WKTMR :: ALARM :: wktmr_alarm [31:00] */
+#define BCHP_WKTMR_ALARM_wktmr_alarm_MASK                          0xffffffff
+#define BCHP_WKTMR_ALARM_wktmr_alarm_SHIFT                         0
+#define BCHP_WKTMR_ALARM_wktmr_alarm_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *PRESCALER - Wakeup Timer Prescaler
+ ***************************************************************************/
+/* WKTMR :: PRESCALER :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_reserved0_MASK                        0xfe000000
+#define BCHP_WKTMR_PRESCALER_reserved0_SHIFT                       25
+
+/* WKTMR :: PRESCALER :: wktmr_prescaler [24:00] */
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_MASK                  0x01ffffff
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_SHIFT                 0
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_DEFAULT               0x019bfcc0
+
+/***************************************************************************
+ *PRESCALER_VAL - Wakeup Timer Prescaler Value
+ ***************************************************************************/
+/* WKTMR :: PRESCALER_VAL :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_MASK                    0xfe000000
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_SHIFT                   25
+
+/* WKTMR :: PRESCALER_VAL :: wktmr_prescaler_val [24:00] */
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_MASK          0x01ffffff
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_SHIFT         0
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_DEFAULT       0x00000000
+
+#endif /* #ifndef BCHP_WKTMR_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7429b0/brcmirq.h b/include/linux/brcmstb/7429b0/brcmirq.h
new file mode 100644
index 0000000..5586ff1
--- /dev/null
+++ b/include/linux/brcmstb/7429b0/brcmirq.h
@@ -0,0 +1,49 @@
+/*
+ * 7429a0 IRQ header file autogenerated by update_bchp.pl
+ * DO NOT EDIT THIS FILE BY HAND.
+ *
+ * Copyright (C) 2011 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BRCMIRQ_H_
+#define _BRCMIRQ_H_
+
+#define BRCM_IRQ_EHCI0_0	56
+#define BRCM_IRQ_EHCI0_1	57
+#define BRCM_IRQ_EHCI1_0	61
+#define BRCM_IRQ_EHCI1_1	62
+#define BRCM_IRQ_GENET_0_A	16
+#define BRCM_IRQ_GENET_0_B	17
+#define BRCM_IRQ_GENET_1_A	18
+#define BRCM_IRQ_GENET_1_B	19
+#define BRCM_IRQ_HIF		23
+#define BRCM_IRQ_HIF_SPI	24
+#define BRCM_IRQ_MOCA		28
+#define BRCM_IRQ_OHCI0_0	58
+#define BRCM_IRQ_OHCI0_1	59
+#define BRCM_IRQ_OHCI1_0	63
+#define BRCM_IRQ_OHCI1_1	64
+#define BRCM_IRQ_SATA		33
+#define BRCM_IRQ_SDIO0		35
+#define BRCM_IRQ_SDIO1		36
+#define BRCM_IRQ_STANDBY	41
+#define BRCM_IRQ_UARTA		52
+#define BRCM_IRQ_UARTB		53
+#define BRCM_IRQ_UARTC		54
+#define BRCM_IRQLIST_EHCI	{ 56, 57, 61, 62 }
+#define BRCM_IRQLIST_OHCI	{ 58, 59, 63, 64 }
+
+#endif /* _BRCMIRQ_H_ */
diff --git a/include/linux/brcmstb/7435b0/bchp_aon_ctrl.h b/include/linux/brcmstb/7435b0/bchp_aon_ctrl.h
new file mode 100644
index 0000000..de37de32
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_aon_ctrl.h
@@ -0,0 +1,1575 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:10:05 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_CTRL_H__
+#define BCHP_AON_CTRL_H__
+
+/***************************************************************************
+ *AON_CTRL - AON Control Registers
+ ***************************************************************************/
+#define BCHP_AON_CTRL_RESET_CTRL                 0x00408000 /* Reset Control register for AON */
+#define BCHP_AON_CTRL_PM_CTRL                    0x00408004 /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_STATUS                  0x00408008 /* Status register for Power Controller */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS        0x0040800c /* Power Management IRQ input status */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT         0x00408010 /* Power Management Wait counter in place of Wait for MIPS IRQ */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER        0x00408014 /* Deep Standby Assertion Timer */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER         0x00408018 /* Deep Standby Wakeup Timer */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE    0x0040801c /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_LED_CTRL                0x00408020 /* LED set control register */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES     0x00408024 /* LED set control register */
+#define BCHP_AON_CTRL_HLCD_CTRL                  0x00408030 /* HW LED Clock Driver Control */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER    0x00408034 /* Second Fraction Counter Initial value */
+#define BCHP_AON_CTRL_TIME_COUNTER               0x00408038 /* Hour/Minute Counter Initial value */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0           0x0040803c /* Digit Code for digit 0, 1, 2, 3 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1           0x00408040 /* Digit Code for digit 4, 5, 6, 7 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2           0x00408044 /* Digit Code for digit 8, 9 */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET      0x00408048 /* Hour MSD/LSD and minute MSD/LSD address offset */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL            0x0040804c /* LED status control */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0             0x00408050 /* General control register 0 */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0           0x00408054 /* General status register 0 */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0     0x00408058 /* General control register without scan 0 */
+#define BCHP_AON_CTRL_SPARE_CTRL_0               0x00408060 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_SPARE_CTRL_1               0x00408064 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH          0x00408068 /* Scratch register */
+#define BCHP_AON_CTRL_RESET_HISTORY              0x0040806c /* Reset History Register For AON */
+#define BCHP_AON_CTRL_NMI_CTRL                   0x00408070 /* Control register for NMI */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL           0x00408074 /* Ana xtal low cur 40g m7fc gisb control */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL         0x00408078 /* Test_mode control register */
+#define BCHP_AON_CTRL_SUB_TEST_MODE              0x0040807c /* Register source for sub_test_mode */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE          0x00408080 /* Final latched testmode value */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE      0x00408084 /* Final latched sub-testmode value */
+#define BCHP_AON_CTRL_PM_INITIATE                0x00408088 /* Power down initiate */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS             0x0040808c /* Power up restore */
+
+/***************************************************************************
+ *RESET_CTRL - Reset Control register for AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_CTRL :: reserved0 [31:04] */
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_MASK                    0xfffffff0
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_SHIFT                   4
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [03:03] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000008
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 3
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable [02:02] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_MASK     0x00000004
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT    2
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_polarity [01:01] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK   0x00000002
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT  1
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_MASK          0x00000001
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_SHIFT         0
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PM_CTRL - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_CTRL :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_MASK                       0xffffff00
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_SHIFT                      8
+
+/* AON_CTRL :: PM_CTRL :: min_s3_width_timer_bypass [07:07] */
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_MASK       0x00000080
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_SHIFT      7
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_DEFAULT    0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_fast_power_down [06:06] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_MASK              0x00000040
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_SHIFT             6
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_DEFAULT           0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_warm_boot [05:05] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_MASK                    0x00000020
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_SHIFT                   5
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_DEFAULT                 0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_deep_standby [04:04] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_MASK                 0x00000010
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_SHIFT                4
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_DEFAULT              0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_clk_divider_reset_en [03:03] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK         0x00000008
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_SHIFT        3
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_DEFAULT      0x00000001
+
+/* AON_CTRL :: PM_CTRL :: pm_use_mips_ready_ctrl [02:02] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_MASK          0x00000004
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_SHIFT         2
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_DEFAULT       0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK             0x00000002
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT            1
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_DEFAULT          0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_MASK                  0x00000001
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT                 0
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PM_STATUS - Status register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_STATUS :: pm_wait_count_upper_bits [31:26] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_MASK      0xfc000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_SHIFT     26
+
+/* AON_CTRL :: PM_STATUS :: pm_wait_counter_active [25:25] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_MASK        0x02000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_SHIFT       25
+
+/* AON_CTRL :: PM_STATUS :: pm_s3_wakeup_reset_ [24:24] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__MASK           0x01000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__SHIFT          24
+
+/* AON_CTRL :: PM_STATUS :: pm_boundary_scan_request [23:23] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_MASK      0x00800000
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_SHIFT     23
+
+/* AON_CTRL :: PM_STATUS :: pm_fast_pd_precharge_valid [22:22] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_MASK    0x00400000
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_SHIFT   22
+
+/* AON_CTRL :: PM_STATUS :: pm_led_out [21:21] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_MASK                    0x00200000
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_SHIFT                   21
+
+/* AON_CTRL :: PM_STATUS :: pm_standby_b [20:20] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_MASK                  0x00100000
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_SHIFT                 20
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs_ng [19:19] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_MASK           0x00080000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_SHIFT          19
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs [18:18] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_MASK              0x00040000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_SHIFT             18
+
+/* AON_CTRL :: PM_STATUS :: pm_rst_clock_div [17:17] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_MASK              0x00020000
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_SHIFT             17
+
+/* AON_CTRL :: PM_STATUS :: pm_pwrdn_pll_req [16:16] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_MASK              0x00010000
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_SHIFT             16
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_xtal_clocks [15:15] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_MASK            0x00008000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_SHIFT           15
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_all_clocks [14:14] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_MASK             0x00004000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_SHIFT            14
+
+/* AON_CTRL :: PM_STATUS :: pm_dphy_standby [13:13] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_MASK               0x00002000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_SHIFT              13
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_cpu_clock [12:12] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_MASK              0x00001000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_SHIFT             12
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_avd_rptd_clock [11:11] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_MASK         0x00000800
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_SHIFT        11
+
+/* AON_CTRL :: PM_STATUS :: pm_power_ctrl_disable [10:10] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_MASK         0x00000400
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_SHIFT        10
+
+/* AON_CTRL :: PM_STATUS :: pm_pll_lock [09:09] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_MASK                   0x00000200
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_SHIFT                  9
+
+/* AON_CTRL :: PM_STATUS :: pm_dram_ready_for_pwrdn [08:08] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_MASK       0x00000100
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_SHIFT      8
+
+/* AON_CTRL :: PM_STATUS :: pm_bsp_ready_for_pwrdn [07:07] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK        0x00000080
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_SHIFT       7
+
+/* AON_CTRL :: PM_STATUS :: pm_mips_ready_for_pwrdn [06:06] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_MASK       0x00000040
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_SHIFT      6
+
+/* AON_CTRL :: PM_STATUS :: pm_sec_avd_rptd_clk_disable [05:05] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_MASK   0x00000020
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_SHIFT  5
+
+/* AON_CTRL :: PM_STATUS :: pm_state [04:00] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_MASK                      0x0000001f
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_SHIFT                     0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_ACTIVE                 0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_PWRDN_RDY              1
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_AVD_RPTD       2
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_CPU            3
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_STANDBY  4
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY                5
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY_WITH_PLLS_ON   6
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_RESET_216_108_CLKS     7
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_ACTIVE   8
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_FAST_PWRDN             9
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S1  10
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_COLD_ENTRY_S2 11
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_WARM_ENTRY_S2 12
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S3  13
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY           14
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S1   15
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S2   16
+
+/***************************************************************************
+ *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
+ ***************************************************************************/
+/* AON_CTRL :: PM_IRQ_INPUT_STATUS :: pm_irq_input_status [31:00] */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_MASK 0xffffffff
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_SHIFT 0
+
+/***************************************************************************
+ *PM_MIPS_WAIT_COUNT - Power Management Wait counter in place of Wait for MIPS IRQ
+ ***************************************************************************/
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_MASK            0xffff0000
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_SHIFT           16
+
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: counter_start_value [15:00] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_MASK  0x0000ffff
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_DEFAULT 0x00000010
+
+/***************************************************************************
+ *PM_S3_STANDBY_TIMER - Deep Standby Assertion Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_MASK           0xf8000000
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_SHIFT          27
+
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_MASK 0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_DEFAULT 0x00083d60
+
+/***************************************************************************
+ *PM_S3_WAKEUP_TIMER - Deep Standby Wakeup Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_MASK            0xf8000000
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_SHIFT           27
+
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_MASK  0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_DEFAULT 0x00083d60
+
+/***************************************************************************
+ *PM_FAST_PWRDN_PRECHARGE - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: reserved0 [31:24] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_MASK       0xff000000
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_SHIFT      24
+
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: pm_fast_power_down_precharge [23:00] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_MASK 0x00ffffff
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_SHIFT 0
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PM_LED_CTRL - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_CTRL :: reserved0 [31:03] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_MASK                   0xfffffff8
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_SHIFT                  3
+
+/* AON_CTRL :: PM_LED_CTRL :: led_status [02:02] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_MASK                  0x00000004
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_SHIFT                 2
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_on [01:01] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_MASK                 0x00000002
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_SHIFT                1
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_off [00:00] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_MASK                0x00000001
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_SHIFT               0
+
+/***************************************************************************
+ *PM_LED_AUTO_ON_ENABLES - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_AUTO_ON_ENABLES :: led_status [31:00] */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_MASK       0xffffffff
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_SHIFT      0
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_DEFAULT    0x00000000
+
+/***************************************************************************
+ *HLCD_CTRL - HW LED Clock Driver Control
+ ***************************************************************************/
+/* AON_CTRL :: HLCD_CTRL :: reserved0 [31:02] */
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_MASK                     0xfffffffc
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_SHIFT                    2
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable_status [01:01] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_MASK            0x00000002
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_SHIFT           1
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable [00:00] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_MASK                   0x00000001
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_SHIFT                  0
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_DEFAULT                0x00000000
+
+/***************************************************************************
+ *SECOND_FRACTION_COUNTER - Second Fraction Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: reserved0 [31:25] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_MASK       0xfe000000
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_SHIFT      25
+
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: second_fraction_counter_init [24:00] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_MASK 0x01ffffff
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_SHIFT 0
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TIME_COUNTER - Hour/Minute Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: TIME_COUNTER :: reserved0 [31:20] */
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_MASK                  0xfff00000
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_SHIFT                 20
+
+/* AON_CTRL :: TIME_COUNTER :: hour_display_mode [19:19] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_MASK          0x00080000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_SHIFT         19
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: mode_12h_24h_init [18:18] */
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_MASK          0x00040000
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_SHIFT         18
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: am_pm_counter_init [17:17] */
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_MASK         0x00020000
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_SHIFT        17
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_DEFAULT      0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: hour_counter_init [16:12] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_MASK          0x0001f000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_SHIFT         12
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: minute_counter_init [11:06] */
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_MASK        0x00000fc0
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_SHIFT       6
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_DEFAULT     0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: second_counter_init [05:00] */
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_MASK        0x0000003f
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_SHIFT       0
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_DEFAULT     0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_0 - Digit Code for digit 0, 1, 2, 3
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_3 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_2 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_1 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_0 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_1 - Digit Code for digit 4, 5, 6, 7
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_7 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_6 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_5 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_4 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_2 - Digit Code for digit 8, 9
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_MASK              0xffff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_SHIFT             16
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_9 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_8 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_ADDR_OFFSET - Hour MSD/LSD and minute MSD/LSD address offset
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_msd_addr_offset [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_MASK 0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_SHIFT 24
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_DEFAULT 0x00000020
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_lsd_addr_offset [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_MASK 0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_SHIFT 16
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_DEFAULT 0x00000024
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_msd_addr_offset [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_MASK 0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_SHIFT 8
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_DEFAULT 0x00000018
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_lsd_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_MASK 0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_SHIFT 0
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_DEFAULT 0x0000001c
+
+/***************************************************************************
+ *LED_STATUS_CTRL - LED status control
+ ***************************************************************************/
+/* AON_CTRL :: LED_STATUS_CTRL :: reserved0 [31:28] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_MASK               0xf0000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_SHIFT              28
+
+/* AON_CTRL :: LED_STATUS_CTRL :: hlcd_state [27:25] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_MASK              0x0e000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_SHIFT             25
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_IDLE         0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_COUNT        1
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_LSD 2
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_MSD 3
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_LSD 4
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_MSD 5
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_STATUS 6
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_update_enable [24:24] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_MASK    0x01000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_SHIFT   24
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_DEFAULT 0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_mask [23:12] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_MASK             0x00fff000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_SHIFT            12
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_DEFAULT          0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_bit_offset [11:08] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_MASK       0x00000f00
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_SHIFT      8
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_DEFAULT    0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_MASK      0x000000ff
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_SHIFT     0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK         0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT        31
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK         0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT        30
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK         0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT        29
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK         0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT        28
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK         0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT        27
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK         0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT        26
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK         0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT        25
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK         0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT        24
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK         0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT        23
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK         0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT        22
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK         0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT        21
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK         0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT        20
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK         0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT        19
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK         0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT        18
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK         0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT        17
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK         0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT        16
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK         0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT        15
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK         0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT        14
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK         0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT        13
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK         0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT        12
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK         0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT        11
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK         0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT        10
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK          0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT         9
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK          0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT         8
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK          0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT         7
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK          0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT         6
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK          0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT         5
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK          0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT         4
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK          0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT         3
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK          0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT         2
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK          0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT         1
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK          0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT         0
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT       0x00000000
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_MASK              0xffffff00
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_SHIFT             8
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_MASK      0x00000080
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT     7
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_MASK      0x00000040
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT     6
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_MASK      0x00000020
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT     5
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_MASK      0x00000010
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT     4
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_MASK      0x00000008
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT     3
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_MASK      0x00000004
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT     2
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_MASK      0x00000002
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT     1
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: ejtag_ce_wakeup_event [00:00] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_MASK  0x00000001
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_MASK 0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_SHIFT 31
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_MASK 0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_SHIFT 30
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_MASK 0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_SHIFT 29
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_MASK 0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_SHIFT 28
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_MASK 0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_SHIFT 27
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_MASK 0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_SHIFT 26
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_MASK 0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_SHIFT 25
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_MASK 0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_SHIFT 24
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_MASK 0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_SHIFT 23
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_MASK 0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_SHIFT 22
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_MASK 0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_SHIFT 21
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_MASK 0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_SHIFT 20
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_MASK 0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_SHIFT 19
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_MASK 0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_SHIFT 18
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_MASK 0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_SHIFT 17
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_MASK 0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_SHIFT 16
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_MASK 0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_SHIFT 15
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_MASK 0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_SHIFT 14
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_MASK 0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_SHIFT 13
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_MASK 0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_SHIFT 12
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_MASK 0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_SHIFT 11
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_MASK 0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_SHIFT 10
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_MASK 0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_SHIFT 5
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_MASK 0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_SHIFT 4
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_MASK 0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_SHIFT 3
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_MASK 0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_SHIFT 2
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_MASK 0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_SHIFT 0
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL_0 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_DEFAULT           0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL_1 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_DEFAULT           0x00000000
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* AON_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK     0xffffffff
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT    0
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT  0x00000000
+
+/***************************************************************************
+ *RESET_HISTORY - Reset History Register For AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_HISTORY :: reserved0 [31:20] */
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_MASK                 0xfff00000
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_SHIFT                20
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [19:19] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK    0x00080000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT   19
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [18:18] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK    0x00040000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT   18
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [17:17] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK     0x00020000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT    17
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [16:16] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK     0x00010000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT    16
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: scpu_ejtag_reset [15:15] */
+#define BCHP_AON_CTRL_RESET_HISTORY_scpu_ejtag_reset_MASK          0x00008000
+#define BCHP_AON_CTRL_RESET_HISTORY_scpu_ejtag_reset_SHIFT         15
+#define BCHP_AON_CTRL_RESET_HISTORY_scpu_ejtag_reset_DEFAULT       0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [14:14] */
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK           0x00004000
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT          14
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_DEFAULT        0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: overtemp_reset [13:13] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_MASK            0x00002000
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_SHIFT           13
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_DEFAULT         0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: overvoltage_reset [12:12] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_MASK         0x00001000
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT        12
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_DEFAULT      0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: undervoltage_reset [11:11] */
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_MASK        0x00000800
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT       11
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_DEFAULT     0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: security_master_reset [10:10] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_MASK     0x00000400
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_SHIFT    10
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: software_master_reset [09:09] */
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_MASK     0x00000200
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_SHIFT    9
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: pcie_1_hot_boot_reset [08:08] */
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_MASK     0x00000100
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_SHIFT    8
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: pcie_0_hot_boot_reset [07:07] */
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_MASK     0x00000080
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_SHIFT    7
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: watchdog_timer_reset [06:06] */
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK      0x00000040
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT     6
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_DEFAULT   0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: smartcard_insert_reset [05:05] */
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK    0x00000020
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT   5
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: s3_wakeup_reset [04:04] */
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_MASK           0x00000010
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_SHIFT          4
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_DEFAULT        0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [03:03] */
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK    0x00000008
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT   3
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: tap_in_system_reset [02:02] */
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_MASK       0x00000004
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_SHIFT      2
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_DEFAULT    0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_MASK     0x00000002
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT    1
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_MASK            0x00000001
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_SHIFT           0
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_DEFAULT         0x00000001
+
+/***************************************************************************
+ *NMI_CTRL - Control register for NMI
+ ***************************************************************************/
+/* AON_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_MASK                0x80000000
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_SHIFT               31
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_DEFAULT             0x00000000
+
+/* AON_CTRL :: NMI_CTRL :: reserved0 [30:03] */
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_MASK                      0x7ffffff8
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_SHIFT                     3
+
+/* AON_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_MASK                0x00000004
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT               2
+
+/* AON_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_MASK            0x00000002
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT           1
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_DEFAULT         0x00000000
+
+/* AON_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_MASK                0x00000001
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT               0
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_DEFAULT             0x00000001
+
+/***************************************************************************
+ *ANA_XTAL_CONTROL - Ana xtal low cur 40g m7fc gisb control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_CONTROL :: reserved0 [31:07] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_MASK              0xffffff80
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_SHIFT             7
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_test_select_gisb_control [06:06] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_MASK 0x00000040
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_SHIFT 6
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_select_current_gisb_control [05:05] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_MASK 0x00000020
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_SHIFT 5
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_cml_sel_pd [04:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_MASK         0x00000018
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_SHIFT        3
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_DEFAULT      0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_d2cbias_gisb_control [02:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_MASK 0x00000007
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_SHIFT 0
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_DEFAULT 0x00000004
+
+/***************************************************************************
+ *SUB_TEST_MODE_CTRL - Test_mode control register
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: reserved0 [31:01] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_MASK            0xfffffffe
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_SHIFT           1
+
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: use_sub_test_mode_reg_src [00:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_MASK 0x00000001
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_SHIFT 0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SUB_TEST_MODE - Register source for sub_test_mode
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_MASK                 0xffffff00
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_SHIFT                8
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [07:07] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK     0x00000080
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT    7
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_DEFAULT  0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [06:06] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK     0x00000040
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT    6
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_DEFAULT  0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [05:05] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK   0x00000020
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT  5
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_mips_in_reset [04:04] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_MASK 0x00000010
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_SHIFT 4
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [03:03] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000008
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 3
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [02:02] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000004
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 2
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK   0x00000003
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT  0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_DEFAULT 0x00000000
+
+/***************************************************************************
+ *LATCHED_TEST_MODE - Final latched testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK     0xffffffff
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT    0
+
+/***************************************************************************
+ *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0
+
+/***************************************************************************
+ *PM_INITIATE - Power down initiate
+ ***************************************************************************/
+/* AON_CTRL :: PM_INITIATE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_MASK                   0xffffff00
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_SHIFT                  8
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_7 [07:07] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_MASK               0x00000080
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_SHIFT              7
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_6 [06:06] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_MASK               0x00000040
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_SHIFT              6
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_5 [05:05] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_MASK               0x00000020
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_SHIFT              5
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_4 [04:04] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_MASK               0x00000010
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_SHIFT              4
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_3 [03:03] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_MASK               0x00000008
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_SHIFT              3
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_2 [02:02] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_MASK               0x00000004
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_SHIFT              2
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_1 [01:01] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_MASK               0x00000002
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_SHIFT              1
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_0 [00:00] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_MASK               0x00000001
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_SHIFT              0
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_DEFAULT            0x00000000
+
+/***************************************************************************
+ *HOST_MISC_CMDS - Power up restore
+ ***************************************************************************/
+/* AON_CTRL :: HOST_MISC_CMDS :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_MASK                0xffffff00
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_SHIFT               8
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_7 [07:07] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_MASK         0x00000080
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_SHIFT        7
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_6 [06:06] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_MASK         0x00000040
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_SHIFT        6
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_5 [05:05] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_MASK         0x00000020
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_SHIFT        5
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_4 [04:04] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_MASK         0x00000010
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_SHIFT        4
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_3 [03:03] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_MASK         0x00000008
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_SHIFT        3
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_2 [02:02] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_MASK         0x00000004
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_SHIFT        2
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: dram_scram_key_reuse_req [01:01] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_MASK 0x00000002
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_SHIFT 1
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_DEFAULT 0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: pm_restore [00:00] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_MASK               0x00000001
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_SHIFT              0
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_BASE                  0x00408200
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_START                 0
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_END                   127
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_ELEMENT_SIZE          32
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_RAMi :: SYSTEM_DATA_RAM [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_MASK        0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_SHIFT       0
+
+
+#endif /* #ifndef BCHP_AON_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_aon_pin_ctrl.h b/include/linux/brcmstb/7435b0/bchp_aon_pin_ctrl.h
new file mode 100644
index 0000000..2f4f186
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_aon_pin_ctrl.h
@@ -0,0 +1,554 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:27 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_aon_pin_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 1:27p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PIN_CTRL_H__
+#define BCHP_AON_PIN_CTRL_H__
+
+/***************************************************************************
+ *AON_PIN_CTRL - AON Pinmux Control Registers
+ ***************************************************************************/
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0         0x00408500 /* Pinmux control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1         0x00408504 /* Pinmux control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2         0x00408508 /* Pinmux control register 2 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3         0x0040850c /* Pinmux control register 3 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0     0x00408510 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1     0x00408514 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2     0x00408518 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0     0x0040851c /* Bypass clock unselect register 0 */
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_07 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_AON_GPIO_07   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_LED_LS_3      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_UART_CTS_0    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_SATA_MDCLK    3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_06 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_AON_GPIO_06   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_LED_LS_2      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_UART_TXD_0    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_MDIO_SATA     3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_05 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_AON_GPIO_05   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_LS_1      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_UART_RXD_0    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SPI_M_SS1B    3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_04 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_AON_GPIO_04   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_LS_0      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_EMAC0_IRQ     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_EMAC1_IRQ     3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_03 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_GPIO_03   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_KD_3      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_I2S_LR0_IN    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_I2S_LR0_OUT   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MDC_PCIE      4
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_02 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_AON_GPIO_02   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_LED_KD_2      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_I2S_DATA0_IN  2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_I2S_DATA0_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_MDIO_PCIE     4
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_01 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AON_GPIO_01   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_LED_KD_1      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_I2S_CLK0_IN   2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_I2S_CLK0_OUT  3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_00 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AON_GPIO_00   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_LED_KD_0      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_EMAC0_IRQ     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_EMAC1_IRQ     3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_15 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_AON_GPIO_15   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_LED_LD_6      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_UART_CTS_2    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_SPI_M_MISO    3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_14 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_AON_GPIO_14   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_LED_LD_5      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_UART_TXD_2    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_SPI_M_MOSI    3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_13 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_AON_GPIO_13   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_LED_LD_4      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_UART_RXD_2    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SPI_M_SCK     3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_12 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_AON_GPIO_12   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_LD_3      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_UART_CTS_1    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_I2S_LR0_OUT   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_I2S_LR0_IN    4
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_11 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_GPIO_11   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_LED_LD_2      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_UART_RTS_1    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_I2S_DATA0_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_I2S_DATA0_IN  4
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_10 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_AON_GPIO_10   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_LED_LD_1      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_UART_TXD_1    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_I2S_CLK0_OUT  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_I2S_CLK0_IN   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SPI_M_SS2B    5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_09 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_AON_GPIO_09   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_LED_LD_0      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_UART_RXD_1    2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_08 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_AON_GPIO_08   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_LED_LS_4      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_UART_RTS_0    2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_01 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_MASK         0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_SHIFT        28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_AON_SGPIO_01 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_BSC_M0_SDA   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_HDMI_TX_BSC_SDA 2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_00 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_MASK         0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SHIFT        24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_AON_SGPIO_00 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_BSC_M0_SCL   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_HDMI_TX_BSC_SCL 2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: gpio_102 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_102_MASK             0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_102_SHIFT            20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_102_DEFAULT          0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_102_GPIO_102         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_102_VO0_656_0        1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_102_VO1_656_0        2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_102_RMX_CLK0         3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_102_TP_OUT_03        4
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: gpio_101 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_101_MASK             0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_101_SHIFT            16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_101_DEFAULT          0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_101_GPIO_101         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_101_IR_INT           1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_101_SC_CLK_OUT       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_101_BT_CLK_26087     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_101_LED_LD_12        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_101_TP_OUT_02        5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: gpio_100 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_100_MASK             0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_100_SHIFT            12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_100_DEFAULT          0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_100_GPIO_100         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_100_PWM_1            1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_100_AUD_FS_CLK1      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_100_VEC_VSYNC_1      3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_100_SPI_M_SS2B       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_100_SDIO0_VOLT       5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_100_TP_OUT_01        6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: gpio_099 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_099_MASK             0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_099_SHIFT            8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_099_DEFAULT          0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_099_GPIO_099         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_099_PWM_0            1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_099_AUD_FS_CLK0      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_099_VEC_VSYNC_0      3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_099_LED_LD_11        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_gpio_099_TP_OUT_00        5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_17 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_DEFAULT       0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_AON_GPIO_17   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_LED_OUT       1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_16 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_AON_GPIO_16   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_LED_LD_7      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_UART_RTS_2    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SPI_M_SS0B    3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: reserved0 [31:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_MASK            0xffff0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_SHIFT           16
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_05 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_MASK         0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_SHIFT        12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_AON_SGPIO_05 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_05_BSC_M4_SDA   1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_04 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_MASK         0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_SHIFT        8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_AON_SGPIO_04 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_04_BSC_M4_SCL   1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_03 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_MASK         0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_SHIFT        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_AON_SGPIO_03 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_BSC_M1_SDA   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_03_BSC_S1_SDA   2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_02 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_02_MASK         0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_02_SHIFT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_02_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_02_AON_SGPIO_02 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_02_BSC_M1_SCL   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_02_BSC_S1_SCL   2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_09_pad_ctrl [29:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_MASK 0x30000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_SHIFT 28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_08_pad_ctrl [27:26] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_MASK 0x0c000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_SHIFT 26
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_07_pad_ctrl [25:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_MASK 0x03000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_SHIFT 24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_06_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_05_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_04_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_03_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_02_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_01_pad_ctrl [13:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_MASK 0x00003000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_SHIFT 12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_00_pad_ctrl [11:10] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_MASK 0x00000c00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_SHIFT 10
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [09:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x000003ff
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0x3fff0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       16
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_17_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_16_pad_ctrl [13:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_MASK 0x00003000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_SHIFT 12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_15_pad_ctrl [11:10] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_MASK 0x00000c00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_SHIFT 10
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_14_pad_ctrl [09:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_MASK 0x00000300
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_SHIFT 8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_13_pad_ctrl [07:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_MASK 0x000000c0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_SHIFT 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_12_pad_ctrl [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_11_pad_ctrl [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_10_pad_ctrl [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_MASK 0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_SHIFT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [31:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK        0xffffff00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT       8
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [07:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0x000000c0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved1 [05:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_MASK        0x0000003f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_SHIFT       0
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:05] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xffffffe0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       5
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_10 [04:04] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_10_MASK 0x00000010
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_10_SHIFT 4
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_10_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_09 [03:03] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_09_MASK 0x00000008
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_09_SHIFT 3
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_09_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_07 [02:02] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_07_MASK 0x00000004
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_07_SHIFT 2
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_07_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_05 [01:01] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_05_MASK 0x00000002
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_05_SHIFT 1
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_05_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_03 [00:00] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_03_MASK 0x00000001
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_03_SHIFT 0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_03_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_AON_PIN_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_aon_pm_l2.h b/include/linux/brcmstb/7435b0/bchp_aon_pm_l2.h
new file mode 100644
index 0000000..c7bbd4b
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_aon_pm_l2.h
@@ -0,0 +1,1167 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:09 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_aon_pm_l2.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 1:28p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PM_L2_H__
+#define BCHP_AON_PM_L2_H__
+
+/***************************************************************************
+ *AON_PM_L2 - AON Power Management L2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_AON_PM_L2_CPU_STATUS                0x00408440 /* CPU interrupt Status Register */
+#define BCHP_AON_PM_L2_CPU_SET                   0x00408444 /* CPU interrupt Set Register */
+#define BCHP_AON_PM_L2_CPU_CLEAR                 0x00408448 /* CPU interrupt Clear Register */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS           0x0040844c /* CPU interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_CPU_MASK_SET              0x00408450 /* CPU interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR            0x00408454 /* CPU interrupt Mask Clear Register */
+#define BCHP_AON_PM_L2_PCI_STATUS                0x00408458 /* PCI interrupt Status Register */
+#define BCHP_AON_PM_L2_PCI_SET                   0x0040845c /* PCI interrupt Set Register */
+#define BCHP_AON_PM_L2_PCI_CLEAR                 0x00408460 /* PCI interrupt Clear Register */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS           0x00408464 /* PCI interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_PCI_MASK_SET              0x00408468 /* PCI interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR            0x0040846c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_STATUS :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_MASK                   0xfffe0000
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_SHIFT                  17
+
+/* AON_PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x00010000
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       16
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_MASK                    0x00008000
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_SHIFT                   15
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00004000
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_SHIFT          14
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_MASK                        0x00002000
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_SHIFT                       13
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_MASK                        0x00001000
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_SHIFT                       12
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_MASK                        0x00000800
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_SHIFT                       11
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_MASK                     0x00000400
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_SHIFT                    10
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: CAP [09:09] */
+#define BCHP_AON_PM_L2_CPU_STATUS_CAP_MASK                         0x00000200
+#define BCHP_AON_PM_L2_CPU_STATUS_CAP_SHIFT                        9
+#define BCHP_AON_PM_L2_CPU_STATUS_CAP_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_MASK                    0x00000100
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_SHIFT                   8
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_MASK                    0x00000080
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_SHIFT                   7
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_STATUS_UHFR_MASK                        0x00000040
+#define BCHP_AON_PM_L2_CPU_STATUS_UHFR_SHIFT                       6
+#define BCHP_AON_PM_L2_CPU_STATUS_UHFR_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_SET :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_MASK                      0xfffe0000
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_SHIFT                     17
+
+/* AON_PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_MASK           0x00010000
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_SHIFT          16
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_MASK                       0x00008000
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_SHIFT                      15
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_MASK              0x00004000
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_SHIFT             14
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_DEFAULT           0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_CPU_SET_USB1_MASK                           0x00002000
+#define BCHP_AON_PM_L2_CPU_SET_USB1_SHIFT                          13
+#define BCHP_AON_PM_L2_CPU_SET_USB1_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_CPU_SET_USB0_MASK                           0x00001000
+#define BCHP_AON_PM_L2_CPU_SET_USB0_SHIFT                          12
+#define BCHP_AON_PM_L2_CPU_SET_USB0_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_MASK                           0x00000800
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_SHIFT                          11
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_MASK                        0x00000400
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_SHIFT                       10
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: CAP [09:09] */
+#define BCHP_AON_PM_L2_CPU_SET_CAP_MASK                            0x00000200
+#define BCHP_AON_PM_L2_CPU_SET_CAP_SHIFT                           9
+#define BCHP_AON_PM_L2_CPU_SET_CAP_DEFAULT                         0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_MASK                       0x00000100
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_SHIFT                      8
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_MOCA_MASK                       0x00000080
+#define BCHP_AON_PM_L2_CPU_SET_WOL_MOCA_SHIFT                      7
+#define BCHP_AON_PM_L2_CPU_SET_WOL_MOCA_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_SET_UHFR_MASK                           0x00000040
+#define BCHP_AON_PM_L2_CPU_SET_UHFR_SHIFT                          6
+#define BCHP_AON_PM_L2_CPU_SET_UHFR_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_CLEAR :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_MASK                    0xfffe0000
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_SHIFT                   17
+
+/* AON_PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x00010000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        16
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_MASK                     0x00008000
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_SHIFT                    15
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00004000
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           14
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_MASK                         0x00002000
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_SHIFT                        13
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_MASK                         0x00001000
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_SHIFT                        12
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_MASK                         0x00000800
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_SHIFT                        11
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_MASK                      0x00000400
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT                     10
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: CAP [09:09] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_CAP_MASK                          0x00000200
+#define BCHP_AON_PM_L2_CPU_CLEAR_CAP_SHIFT                         9
+#define BCHP_AON_PM_L2_CPU_CLEAR_CAP_DEFAULT                       0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_MASK                     0x00000100
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_SHIFT                    8
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_MOCA_MASK                     0x00000080
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_MOCA_SHIFT                    7
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_MOCA_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_UHFR_MASK                         0x00000040
+#define BCHP_AON_PM_L2_CPU_CLEAR_UHFR_SHIFT                        6
+#define BCHP_AON_PM_L2_CPU_CLEAR_UHFR_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_MASK              0xfffe0000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT             17
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x00010000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  16
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_MASK               0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_SHIFT              15
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     14
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_MASK                   0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_SHIFT                  13
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_MASK                   0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_SHIFT                  12
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_MASK                   0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_SHIFT                  11
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK                0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT               10
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: CAP [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CAP_MASK                    0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CAP_SHIFT                   9
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CAP_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_MASK               0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_SHIFT              8
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_MOCA_MASK               0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_MOCA_SHIFT              7
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_MOCA_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_UHFR_MASK                   0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_UHFR_SHIFT                  6
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_UHFR_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_DEFAULT            0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_SET :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_MASK                 0xfffe0000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_SHIFT                17
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x00010000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     16
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_MASK                  0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_SHIFT                 15
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        14
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_MASK                      0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_SHIFT                     13
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_MASK                      0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_SHIFT                     12
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_MASK                      0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_SHIFT                     11
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_MASK                   0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT                  10
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: CAP [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CAP_MASK                       0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CAP_SHIFT                      9
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CAP_DEFAULT                    0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_MASK                  0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_SHIFT                 8
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_MOCA_MASK                  0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_MOCA_SHIFT                 7
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_MOCA_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_UHFR_MASK                      0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_SET_UHFR_SHIFT                     6
+#define BCHP_AON_PM_L2_CPU_MASK_SET_UHFR_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_DEFAULT               0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_MASK               0xfffe0000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT              17
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x00010000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   16
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_MASK                0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_SHIFT               15
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      14
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_MASK                    0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_SHIFT                   13
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_MASK                    0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_SHIFT                   12
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_MASK                    0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_SHIFT                   11
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK                 0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT                10
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: CAP [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CAP_MASK                     0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CAP_SHIFT                    9
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CAP_DEFAULT                  0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_MASK                0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_SHIFT               8
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_MASK                0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_SHIFT               7
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_UHFR_MASK                    0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_UHFR_SHIFT                   6
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_UHFR_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_DEFAULT             0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_STATUS :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_MASK                   0xfffe0000
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_SHIFT                  17
+
+/* AON_PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x00010000
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       16
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_MASK                    0x00008000
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_SHIFT                   15
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00004000
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_SHIFT          14
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_MASK                        0x00002000
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_SHIFT                       13
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_MASK                        0x00001000
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_SHIFT                       12
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_MASK                        0x00000800
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_SHIFT                       11
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_MASK                     0x00000400
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_SHIFT                    10
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: CAP [09:09] */
+#define BCHP_AON_PM_L2_PCI_STATUS_CAP_MASK                         0x00000200
+#define BCHP_AON_PM_L2_PCI_STATUS_CAP_SHIFT                        9
+#define BCHP_AON_PM_L2_PCI_STATUS_CAP_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_MASK                    0x00000100
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_SHIFT                   8
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_MOCA_MASK                    0x00000080
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_MOCA_SHIFT                   7
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_MOCA_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_STATUS_UHFR_MASK                        0x00000040
+#define BCHP_AON_PM_L2_PCI_STATUS_UHFR_SHIFT                       6
+#define BCHP_AON_PM_L2_PCI_STATUS_UHFR_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_SET :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_MASK                      0xfffe0000
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_SHIFT                     17
+
+/* AON_PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_MASK           0x00010000
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_SHIFT          16
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_MASK                       0x00008000
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_SHIFT                      15
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_MASK              0x00004000
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_SHIFT             14
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_DEFAULT           0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_PCI_SET_USB1_MASK                           0x00002000
+#define BCHP_AON_PM_L2_PCI_SET_USB1_SHIFT                          13
+#define BCHP_AON_PM_L2_PCI_SET_USB1_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_PCI_SET_USB0_MASK                           0x00001000
+#define BCHP_AON_PM_L2_PCI_SET_USB0_SHIFT                          12
+#define BCHP_AON_PM_L2_PCI_SET_USB0_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_MASK                           0x00000800
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_SHIFT                          11
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_MASK                        0x00000400
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_SHIFT                       10
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: CAP [09:09] */
+#define BCHP_AON_PM_L2_PCI_SET_CAP_MASK                            0x00000200
+#define BCHP_AON_PM_L2_PCI_SET_CAP_SHIFT                           9
+#define BCHP_AON_PM_L2_PCI_SET_CAP_DEFAULT                         0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_MASK                       0x00000100
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_SHIFT                      8
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_MOCA_MASK                       0x00000080
+#define BCHP_AON_PM_L2_PCI_SET_WOL_MOCA_SHIFT                      7
+#define BCHP_AON_PM_L2_PCI_SET_WOL_MOCA_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_SET_UHFR_MASK                           0x00000040
+#define BCHP_AON_PM_L2_PCI_SET_UHFR_SHIFT                          6
+#define BCHP_AON_PM_L2_PCI_SET_UHFR_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_CLEAR :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_MASK                    0xfffe0000
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_SHIFT                   17
+
+/* AON_PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x00010000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        16
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_MASK                     0x00008000
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_SHIFT                    15
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00004000
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           14
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_MASK                         0x00002000
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_SHIFT                        13
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_MASK                         0x00001000
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_SHIFT                        12
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_MASK                         0x00000800
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_SHIFT                        11
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_MASK                      0x00000400
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT                     10
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: CAP [09:09] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_CAP_MASK                          0x00000200
+#define BCHP_AON_PM_L2_PCI_CLEAR_CAP_SHIFT                         9
+#define BCHP_AON_PM_L2_PCI_CLEAR_CAP_DEFAULT                       0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_MASK                     0x00000100
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_SHIFT                    8
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_MOCA_MASK                     0x00000080
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_MOCA_SHIFT                    7
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_MOCA_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_UHFR_MASK                         0x00000040
+#define BCHP_AON_PM_L2_PCI_CLEAR_UHFR_SHIFT                        6
+#define BCHP_AON_PM_L2_PCI_CLEAR_UHFR_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_MASK              0xfffe0000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT             17
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x00010000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  16
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_MASK               0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_SHIFT              15
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     14
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_MASK                   0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_SHIFT                  13
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_MASK                   0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_SHIFT                  12
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_MASK                   0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_SHIFT                  11
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK                0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT               10
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: CAP [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CAP_MASK                    0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CAP_SHIFT                   9
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CAP_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_MASK               0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_SHIFT              8
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_MOCA_MASK               0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_MOCA_SHIFT              7
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_MOCA_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_UHFR_MASK                   0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_UHFR_SHIFT                  6
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_UHFR_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_DEFAULT            0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_SET :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_MASK                 0xfffe0000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_SHIFT                17
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x00010000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     16
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_MASK                  0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_SHIFT                 15
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        14
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_MASK                      0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_SHIFT                     13
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_MASK                      0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_SHIFT                     12
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_MASK                      0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_SHIFT                     11
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_MASK                   0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT                  10
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: CAP [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CAP_MASK                       0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CAP_SHIFT                      9
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CAP_DEFAULT                    0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_MASK                  0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_SHIFT                 8
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_MOCA_MASK                  0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_MOCA_SHIFT                 7
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_MOCA_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_UHFR_MASK                      0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_SET_UHFR_SHIFT                     6
+#define BCHP_AON_PM_L2_PCI_MASK_SET_UHFR_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_DEFAULT               0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_MASK               0xfffe0000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT              17
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x00010000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   16
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_MASK                0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_SHIFT               15
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      14
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_MASK                    0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_SHIFT                   13
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_MASK                    0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_SHIFT                   12
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_MASK                    0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_SHIFT                   11
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK                 0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT                10
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: CAP [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CAP_MASK                     0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CAP_SHIFT                    9
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CAP_DEFAULT                  0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_MASK                0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_SHIFT               8
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_MASK                0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_SHIFT               7
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_UHFR_MASK                    0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_UHFR_SHIFT                   6
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_UHFR_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_DEFAULT             0x00000001
+
+#endif /* #ifndef BCHP_AON_PM_L2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_bspi.h b/include/linux/brcmstb/7435b0/bchp_bspi.h
new file mode 100644
index 0000000..35bc793
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_bspi.h
@@ -0,0 +1,443 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:10:04 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_H__
+#define BCHP_BSPI_H__
+
+/***************************************************************************
+ *BSPI - Public BSPI Control Registers
+ ***************************************************************************/
+#define BCHP_BSPI_REVISION_ID                    0x0041d200 /* Revision ID */
+#define BCHP_BSPI_SCRATCH                        0x0041d204 /* Revision ID */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL               0x0041d208 /* Master/Boot SPI Control Register */
+#define BCHP_BSPI_BUSY_STATUS                    0x0041d20c /* BSPI Busy Status Register */
+#define BCHP_BSPI_INTR_STATUS                    0x0041d210 /* Interrupt Status Register */
+#define BCHP_BSPI_B0_STATUS                      0x0041d214 /* Prefetch Buffer 0 Status Register */
+#define BCHP_BSPI_B0_CTRL                        0x0041d218 /* Prefetch Buffer 0 Control Register */
+#define BCHP_BSPI_B1_STATUS                      0x0041d21c /* Prefetch Buffer 1 Status Register */
+#define BCHP_BSPI_B1_CTRL                        0x0041d220 /* Prefetch Buffer 1 Control Register */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL            0x0041d224 /* Dual/Single Receive Mode Control Register */
+#define BCHP_BSPI_FLEX_MODE_ENABLE               0x0041d228 /* Flexible Control Mode Enable Register */
+#define BCHP_BSPI_BITS_PER_CYCLE                 0x0041d22c /* Bits per cycle "b-p-c" Control Register */
+#define BCHP_BSPI_BITS_PER_PHASE                 0x0041d230 /* Bits per Phase "b-p-p" Control Register */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE              0x0041d234 /* Command and Mode Data Register */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE     0x0041d238 /* Bspi FLash upper address byte register */
+#define BCHP_BSPI_BSPI_XOR_VALUE                 0x0041d23c /* BSPI FLASH XOR Value Register */
+#define BCHP_BSPI_BSPI_XOR_ENABLE                0x0041d240 /* BSPI FLASH XOR Enable Register */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE           0x0041d244 /* BSPI Pin  Programmed IO Mode Enable Register */
+#define BCHP_BSPI_BSPI_PIO_IODIR                 0x0041d248 /* BSPI Pin  Programmed IO Mode Direction Register */
+#define BCHP_BSPI_BSPI_PIO_DATA                  0x0041d24c /* BSPI Pin  Programmed IO Mode Data Register */
+
+/***************************************************************************
+ *REVISION_ID - Revision ID
+ ***************************************************************************/
+/* BSPI :: REVISION_ID :: reserved0 [31:16] */
+#define BCHP_BSPI_REVISION_ID_reserved0_MASK                       0xffff0000
+#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT                      16
+
+/* BSPI :: REVISION_ID :: MAJOR [15:08] */
+#define BCHP_BSPI_REVISION_ID_MAJOR_MASK                           0x0000ff00
+#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT                          8
+#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT                        0x00000004
+
+/* BSPI :: REVISION_ID :: MINOR [07:00] */
+#define BCHP_BSPI_REVISION_ID_MINOR_MASK                           0x000000ff
+#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT                          0
+#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT                        0x00000001
+
+/***************************************************************************
+ *SCRATCH - Revision ID
+ ***************************************************************************/
+/* BSPI :: SCRATCH :: SCRATCH [31:00] */
+#define BCHP_BSPI_SCRATCH_SCRATCH_MASK                             0xffffffff
+#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT                            0
+#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
+ ***************************************************************************/
+/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT                 1
+
+/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK                0x00000001
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT               0
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT             0x00000000
+
+/***************************************************************************
+ *BUSY_STATUS - BSPI Busy Status Register
+ ***************************************************************************/
+/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
+#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK                       0xfffffffe
+#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT                      1
+
+/* BSPI :: BUSY_STATUS :: busy [00:00] */
+#define BCHP_BSPI_BUSY_STATUS_busy_MASK                            0x00000001
+#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT                           0
+#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *INTR_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
+#define BCHP_BSPI_INTR_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT                      2
+
+/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
+#define BCHP_BSPI_INTR_STATUS_intr_1_MASK                          0x00000002
+#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT                         1
+#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT                       0x00000000
+
+/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
+#define BCHP_BSPI_INTR_STATUS_intr_0_MASK                          0x00000001
+#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT                         0
+#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *B0_STATUS - Prefetch Buffer 0 Status Register
+ ***************************************************************************/
+/* BSPI :: B0_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B0_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B0_STATUS :: b0_full [29:29] */
+#define BCHP_BSPI_B0_STATUS_b0_full_MASK                           0x20000000
+#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT                          29
+#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_empty [28:28] */
+#define BCHP_BSPI_B0_STATUS_b0_empty_MASK                          0x10000000
+#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT                         28
+#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B0_STATUS :: b0_miss [27:27] */
+#define BCHP_BSPI_B0_STATUS_b0_miss_MASK                           0x08000000
+#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT                          27
+#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_hit [26:26] */
+#define BCHP_BSPI_B0_STATUS_b0_hit_MASK                            0x04000000
+#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT                           26
+#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B0_STATUS :: b0_address [25:00] */
+#define BCHP_BSPI_B0_STATUS_b0_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT                       0
+#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B0_CTRL - Prefetch Buffer 0 Control Register
+ ***************************************************************************/
+/* BSPI :: B0_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B0_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B0_CTRL :: b0_flush [00:00] */
+#define BCHP_BSPI_B0_CTRL_b0_flush_MASK                            0x00000001
+#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT                           0
+#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *B1_STATUS - Prefetch Buffer 1 Status Register
+ ***************************************************************************/
+/* BSPI :: B1_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B1_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B1_STATUS :: b1_full [29:29] */
+#define BCHP_BSPI_B1_STATUS_b1_full_MASK                           0x20000000
+#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT                          29
+#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_empty [28:28] */
+#define BCHP_BSPI_B1_STATUS_b1_empty_MASK                          0x10000000
+#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT                         28
+#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B1_STATUS :: b1_miss [27:27] */
+#define BCHP_BSPI_B1_STATUS_b1_miss_MASK                           0x08000000
+#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT                          27
+#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_hit [26:26] */
+#define BCHP_BSPI_B1_STATUS_b1_hit_MASK                            0x04000000
+#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT                           26
+#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B1_STATUS :: b1_address [25:00] */
+#define BCHP_BSPI_B1_STATUS_b1_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT                       0
+#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B1_CTRL - Prefetch Buffer 1 Control Register
+ ***************************************************************************/
+/* BSPI :: B1_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B1_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B1_CTRL :: b1_flush [00:00] */
+#define BCHP_BSPI_B1_CTRL_b1_flush_MASK                            0x00000001
+#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT                           0
+#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
+ ***************************************************************************/
+/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK               0xffffffe0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT              5
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK             0x00000010
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT            4
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT          0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK               0x00000008
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT              3
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT            0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK      0x00000004
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT     2
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT   0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK         0x00000002
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT        1
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT      0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK                0x00000001
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT               0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT             0x00000000
+
+/***************************************************************************
+ *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT                 1
+
+/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK      0x00000001
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT     0
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT   0x00000000
+
+/***************************************************************************
+ *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK                    0xfc000000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT                   26
+
+/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK               0x03000000
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK                    0x00fc0000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT                   18
+
+/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK              0x00030000
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK                    0x0000fc00
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT                   10
+
+/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK              0x00000300
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT             8
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK                    0x000000fc
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT                   2
+
+/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK              0x00000003
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT             0
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT           0x00000000
+
+/***************************************************************************
+ *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK                    0xfe000000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT                   25
+
+/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK               0x01000000
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK                    0x00fe0000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT                   17
+
+/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK              0x00010000
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK                    0x0000fe00
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT                   9
+
+/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK                     0x00000100
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT                    8
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT                  0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK                 0x000000ff
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT                0
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT              0x00000008
+
+/***************************************************************************
+ *CMD_AND_MODE_BYTE - Command and Mode Data Register
+ ***************************************************************************/
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK                 0xff000000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT                24
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK            0x00ff0000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT           16
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT         0x00000000
+
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK                 0x0000ff00
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT                8
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK             0x000000ff
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT            0
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT          0x0000000b
+
+/***************************************************************************
+ *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
+ ***************************************************************************/
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0x00000000
+
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK        0x00ffffff
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT       0
+
+/***************************************************************************
+ *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK               0xfff00000
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT              20
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT            0x00000000
+
+/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK                    0x000fffff
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT                  1
+
+/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK             0x00000001
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT            0
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT          0x00000000
+
+/***************************************************************************
+ *BSPI_PIO_MODE_ENABLE - BSPI Pin  Programmed IO Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK              0xfffffffe
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT             1
+
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK          0x00000001
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT         0
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT       0x00000000
+
+/***************************************************************************
+ *BSPI_PIO_IODIR - BSPI Pin  Programmed IO Mode Direction Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK                    0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT                   3
+
+/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT              0x00000003
+
+/***************************************************************************
+ *BSPI_PIO_DATA - BSPI Pin  Programmed IO Mode Data Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK                     0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT                    3
+
+/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT              0x00000000
+
+#endif /* #ifndef BCHP_BSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_bspi_raf.h b/include/linux/brcmstb/7435b0/bchp_bspi_raf.h
new file mode 100644
index 0000000..d9a6519
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_bspi_raf.h
@@ -0,0 +1,163 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:35 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_bspi_raf.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 1:50p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_RAF_H__
+#define BCHP_BSPI_RAF_H__
+
+/***************************************************************************
+ *BSPI_RAF - Public Linear Read BSPI Pipe Registers
+ ***************************************************************************/
+#define BCHP_BSPI_RAF_START_ADDR                 0x0041d300 /* Physical Starting Address Location in Flash device */
+#define BCHP_BSPI_RAF_NUM_WORDS                  0x0041d304 /* Number of Words to be fetched */
+#define BCHP_BSPI_RAF_CTRL                       0x0041d308 /* RAF Session Control Register */
+#define BCHP_BSPI_RAF_FULLNESS                   0x0041d30c /* Fullness indicator for the read ahead buffer */
+#define BCHP_BSPI_RAF_WATERMARK                  0x0041d310 /* Watermark level in the read ahead buffer that triggers an interrupt */
+#define BCHP_BSPI_RAF_STATUS                     0x0041d314 /* Linear Read Status Register */
+#define BCHP_BSPI_RAF_READ_DATA                  0x0041d318 /* Read data from Raf-buffer */
+#define BCHP_BSPI_RAF_WORD_CNT                   0x0041d31c /* Current number of words fetched from Flash */
+#define BCHP_BSPI_RAF_CURR_ADDR                  0x0041d320 /* Current read address for the linear read session */
+
+/***************************************************************************
+ *START_ADDR - Physical Starting Address Location in Flash device
+ ***************************************************************************/
+/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK                   0xffffffff
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT                  0
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT                0x00000000
+
+/***************************************************************************
+ *NUM_WORDS - Number of Words to be fetched
+ ***************************************************************************/
+/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK                      0xffffffff
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT                     0
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *CTRL - RAF Session Control Register
+ ***************************************************************************/
+/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT                         2
+
+/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
+#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK                              0x00000002
+#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT                             1
+#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT                           0x00000000
+
+/* BSPI_RAF :: CTRL :: START [00:00] */
+#define BCHP_BSPI_RAF_CTRL_START_MASK                              0x00000001
+#define BCHP_BSPI_RAF_CTRL_START_SHIFT                             0
+#define BCHP_BSPI_RAF_CTRL_START_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *FULLNESS - Fullness indicator for the read ahead buffer
+ ***************************************************************************/
+/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK                      0xffffff80
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT                     7
+
+/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK                       0x0000007f
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT                      0
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
+ ***************************************************************************/
+/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK                     0xfffffffc
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT                    2
+
+/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK            0x00000003
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT           0
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STATUS - Linear Read Status Register
+ ***************************************************************************/
+/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
+#define BCHP_BSPI_RAF_STATUS_reserved0_MASK                        0xfffffff8
+#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT                       3
+
+/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK                        0x00000004
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT                       2
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT                     0x00000000
+
+/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK                       0x00000002
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT                      1
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT                    0x00000001
+
+/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK                     0x00000001
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT                    0
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *READ_DATA - Read data from Raf-buffer
+ ***************************************************************************/
+/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
+#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK                          0xffffffff
+#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT                         0
+#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *WORD_CNT - Current number of words fetched from Flash
+ ***************************************************************************/
+/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK             0xffffffff
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT            0
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *CURR_ADDR - Current read address for the linear read session
+ ***************************************************************************/
+/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK               0xffffffff
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT              0
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT            0x00000000
+
+#endif /* #ifndef BCHP_BSPI_RAF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_clkgen.h b/include/linux/brcmstb/7435b0/bchp_clkgen.h
new file mode 100644
index 0000000..3483199
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_clkgen.h
@@ -0,0 +1,9092 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Jul 20 15:43:16 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_CLKGEN_H__
+#define BCHP_CLKGEN_H__
+
+/***************************************************************************
+ *CLKGEN - clkgen registers
+ ***************************************************************************/
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL       0x00430000 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV           0x00430004 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN          0x00430008 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS   0x0043000c /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN         0x00430010 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET         0x00430014 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x00430018 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x0043001c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS        0x00430020 /* Test Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL       0x00430024 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV           0x00430028 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN          0x0043002c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS   0x00430030 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN         0x00430034 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET         0x00430038 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x0043003c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x00430040 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS        0x00430044 /* Test Status */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL       0x00430048 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV           0x0043004c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN          0x00430050 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS   0x00430054 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN         0x00430058 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET         0x0043005c /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH 0x00430060 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW 0x00430064 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS        0x00430068 /* Test Status */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 0x0043006c /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 0x00430070 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 0x00430074 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 0x00430078 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4 0x0043007c /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_5 0x00430080 /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL         0x00430084 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV             0x00430088 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN            0x0043008c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_LDO_PWRDN       0x00430090 /* LDO Powerdowns */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS     0x00430094 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC            0x00430098 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2           0x0043009c /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN           0x004300a0 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET           0x004300a4 /* Resets */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH 0x004300a8 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW 0x004300ac /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_STATUS          0x004300b0 /* Test Status */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0 0x004300b4 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL          0x004300b8 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_HIF_PLL_DIV              0x004300bc /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_HIF_PLL_FRAC             0x004300c0 /* Fractional */
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN             0x004300c4 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_HIF_PLL_LOCK_STATUS      0x004300c8 /* Lock Status */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC             0x004300cc /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN            0x004300d0 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET            0x004300d4 /* Resets */
+#define BCHP_CLKGEN_PLL_HIF_PLL_STATUS           0x004300d8 /* Test Status */
+#define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN           0x004300dc /* Cml buffer Tristate enable */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 0x004300e0 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 0x004300e4 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL         0x004300e8 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV             0x004300ec /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_FRAC            0x004300f0 /* Fractional */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN            0x004300f4 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LDO_PWRDN       0x004300f8 /* LDO Powerdowns */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS     0x004300fc /* Lock Status */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC            0x00430100 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2           0x00430104 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN           0x00430108 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET           0x0043010c /* Resets */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x00430110 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x00430114 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS          0x00430118 /* Test Status */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 0x0043011c /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 0x00430120 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 0x00430124 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 0x00430128 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 0x0043012c /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL         0x00430130 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV             0x00430134 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN            0x00430138 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRDN       0x0043013c /* LDO Powerdowns */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS     0x00430140 /* Lock Status */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC            0x00430144 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2           0x00430148 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN           0x0043014c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET           0x00430150 /* Resets */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH 0x00430154 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW 0x00430158 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS          0x0043015c /* Test Status */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 0x00430160 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 0x00430164 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 0x00430168 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3 0x0043016c /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL      0x00430170 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV          0x00430174 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN         0x00430178 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRDN    0x0043017c /* LDO Powerdowns */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS  0x00430180 /* Lock Status */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC         0x00430184 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2        0x00430188 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN        0x0043018c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET        0x00430190 /* Resets */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH 0x00430194 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW 0x00430198 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS       0x0043019c /* Test Status */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 0x004301a0 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 0x004301a4 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL        0x004301a8 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV            0x004301ac /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN           0x004301b0 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRDN      0x004301b4 /* LDO Powerdowns */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS    0x004301b8 /* Lock Status */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC           0x004301bc /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2          0x004301c0 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN          0x004301c4 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET          0x004301c8 /* Resets */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH 0x004301cc /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW 0x004301d0 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS         0x004301d4 /* Test Status */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0 0x004301d8 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CONTROL          0x004301dc /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV              0x004301e0 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC             0x004301e4 /* Fractional */
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN             0x004301e8 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS      0x004301ec /* Lock Status */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC             0x004301f0 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SC0_PLL_PWRDN            0x004301f4 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET            0x004301f8 /* Resets */
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH 0x004301fc /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW 0x00430200 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS           0x00430204 /* Test Status */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0 0x00430208 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CONTROL          0x0043020c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV              0x00430210 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC             0x00430214 /* Fractional */
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN             0x00430218 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS      0x0043021c /* Lock Status */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC             0x00430220 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SC1_PLL_PWRDN            0x00430224 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET            0x00430228 /* Resets */
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH 0x0043022c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW 0x00430230 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS           0x00430234 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x00430238 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x0043023c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x00430240 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x00430244 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL         0x00430248 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV             0x0043024c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN            0x00430250 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRDN       0x00430254 /* LDO Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS     0x00430258 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC            0x0043025c /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2           0x00430260 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN           0x00430264 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET           0x00430268 /* Resets */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x0043026c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x00430270 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS          0x00430274 /* Test Status */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 0x00430278 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 0x0043027c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 0x00430280 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL        0x00430284 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV            0x00430288 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC           0x0043028c /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN           0x00430290 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS    0x00430294 /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC           0x00430298 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN          0x0043029c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET          0x004302a0 /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH 0x004302a4 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW 0x004302a8 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS         0x004302ac /* Test Status */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 0x004302b0 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 0x004302b4 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 0x004302b8 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL        0x004302bc /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV            0x004302c0 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC           0x004302c4 /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN           0x004302c8 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS    0x004302cc /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC           0x004302d0 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN          0x004302d4 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET          0x004302d8 /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH 0x004302dc /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW 0x004302e0 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS         0x004302e4 /* Test Status */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 0x004302e8 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 0x004302ec /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 0x004302f0 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL        0x004302f4 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV            0x004302f8 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC           0x004302fc /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN           0x00430300 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS    0x00430304 /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC           0x00430308 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN          0x0043030c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET          0x00430310 /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH 0x00430314 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW 0x00430318 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS         0x0043031c /* Test Status */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0 0x00430320 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1 0x00430324 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2 0x00430328 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3 0x0043032c /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CONTROL          0x00430330 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_XPT_PLL_DIV              0x00430334 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN             0x00430338 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRDN        0x0043033c /* LDO Powerdowns */
+#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS      0x00430340 /* Lock Status */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC             0x00430344 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2            0x00430348 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_XPT_PLL_PWRDN            0x0043034c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_XPT_PLL_RESET            0x00430350 /* Resets */
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH 0x00430354 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW 0x00430358 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS           0x0043035c /* Test Status */
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE   0x00430360 /* Avd0 top inst clock enable */
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_SID 0x00430364 /* Avd0 top inst clock enable sid */
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_SID_STATUS 0x00430368 /* Clock Enable Status */
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_STATUS 0x0043036c /* Clock Enable Status */
+#define BCHP_CLKGEN_AVD0_TOP_INST_MEMORY_STANDBY_ENABLE 0x00430370 /* Avd0 top inst memory standby enable */
+#define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK  0x00430374 /* Avd0 top inst observe clock */
+#define BCHP_CLKGEN_AVD0_TOP_INST_POWER_SWITCH_MEMORY 0x00430378 /* Avd0 top inst power switch memory */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE 0x0043037c /* Bvn mvp top inst clock enable */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS 0x00430380 /* Clock Enable Status */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_MEMORY_STANDBY_ENABLE 0x00430384 /* Bvn mvp top inst memory standby enable */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_POWER_SWITCH_MEMORY 0x00430388 /* Bvn mvp top inst power switch memory */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE    0x0043038c /* Bvn top inst clock enable */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS 0x00430390 /* Clock Enable Status */
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE 0x00430394 /* Bvn top inst memory standby enable */
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY 0x00430398 /* Bvn top inst power switch memory */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE         0x0043039c /* Disable CLKGEN's clocks */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS  0x004303a0 /* Clock Disable Status */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL        0x004303a4 /* Clock Monitor Control */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT      0x004303a8 /* Clock Monitor Max Reference Count */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER    0x004303ac /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE       0x004303b0 /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER   0x004303b4 /* Clock Monitor View Counter */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE  0x004303b8 /* Disable CORE_XPT_INST's clocks */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS 0x004303bc /* Clock Disable Status */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE   0x004303c0 /* Core xpt inst clock enable */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS 0x004303c4 /* Clock Enable Status */
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE 0x004303c8 /* Core xpt inst memory standby enable */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK  0x004303cc /* Core xpt inst observe clock */
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY 0x004303d0 /* Core xpt inst power switch memory */
+#define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_INST_MEMORY_STANDBY_ENABLE 0x004303dc /* Cpuwrap 3375 bcm mips inst memory standby enable */
+#define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_INST_OBSERVE_CLOCK 0x004303e0 /* Cpuwrap 3375 bcm mips inst observe clock */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE 0x004303e4 /* Disable DUAL_GENET_TOP_DUAL_RGMII_INST's clocks */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS 0x004303e8 /* Clock Disable Status */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE 0x004303ec /* Dual genet top dual rgmii inst clock enable */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 0x004303f0 /* Dual genet top dual rgmii inst clock enable genet0 */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS 0x004303f4 /* Clock Enable Status */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 0x004303f8 /* Dual genet top dual rgmii inst clock enable genet1 */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS 0x004303fc /* Clock Enable Status */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS 0x00430400 /* Clock Enable Status */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0 0x00430404 /* Dual genet top dual rgmii inst clock select genet0 */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1 0x00430408 /* Dual genet top dual rgmii inst clock select genet1 */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK 0x0043040c /* Dual genet top dual rgmii inst observe clock */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE    0x00430410 /* Disable DVP_HR_INST's clocks */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS 0x00430414 /* Clock Disable Status */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE     0x00430418 /* Dvp hr inst clock enable */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS 0x0043041c /* Clock Enable Status */
+#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE 0x00430420 /* Dvp hr inst memory standby enable */
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK    0x00430424 /* Dvp hr inst observe clock */
+#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY 0x00430428 /* Dvp hr inst power switch memory */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE    0x0043042c /* Disable DVP_HT_INST's clocks */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS 0x00430430 /* Clock Disable Status */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE     0x00430434 /* Dvp ht inst clock enable */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS 0x00430438 /* Clock Enable Status */
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE           0x0043043c /* Dvp ht inst enable */
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE 0x00430440 /* Dvp ht inst memory standby enable */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK    0x00430444 /* Dvp ht inst observe clock */
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY 0x00430448 /* Dvp ht inst power switch memory */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0 0x0043044c /* Graphics inst clock enable m2mc0 */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS 0x00430450 /* Clock Enable Status */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1 0x00430454 /* Graphics inst clock enable m2mc1 */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS 0x00430458 /* Clock Enable Status */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC0 0x0043045c /* Graphics inst memory standby enable m2mc0 */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC1 0x00430460 /* Graphics inst memory standby enable m2mc1 */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK  0x00430464 /* Graphics inst observe clock */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC0 0x00430468 /* Graphics inst power switch memory m2mc0 */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC1 0x0043046c /* Graphics inst power switch memory m2mc1 */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE       0x00430470 /* Disable HIF_INST's clocks */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS 0x00430474 /* Clock Disable Status */
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE 0x00430478 /* Hif inst memory standby enable */
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK       0x0043047c /* Hif inst observe clock */
+#define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH 0x00430480 /* Hif inst pll hif ssc mode control high */
+#define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW 0x00430484 /* Hif inst pll hif ssc mode control low */
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY 0x00430488 /* Hif inst power switch memory */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT          0x0043048c /* Mux selects for Internal clocks */
+#define BCHP_CLKGEN_ITU656_0_MUX_SELECT          0x00430490 /* Mux selects for itu656_0 clocks */
+#define BCHP_CLKGEN_ITU656_1_MUX_SELECT          0x00430494 /* Mux selects for itu656_1 clocks */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE 0x00430498 /* Memsys 32 0 inst clock enable */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS 0x0043049c /* Clock Enable Status */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE 0x004304a0 /* Memsys 32 0 inst memory standby enable */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK 0x004304a4 /* Memsys 32 0 inst observe clock */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY 0x004304a8 /* Memsys 32 0 inst power switch memory */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS      0x004304ac /* Memsys 32 0 inst status */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE 0x004304b0 /* Memsys 32 1 inst clock enable */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS 0x004304b4 /* Clock Enable Status */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE 0x004304b8 /* Memsys 32 1 inst memory standby enable */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK 0x004304bc /* Memsys 32 1 inst observe clock */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY 0x004304c0 /* Memsys 32 1 inst power switch memory */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_STATUS      0x004304c4 /* Memsys 32 1 inst status */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE 0x004304c8 /* Mocamac top inst clock enable */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS 0x004304cc /* Clock Enable Status */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_MEMORY_STANDBY_ENABLE 0x004304d0 /* Mocamac top inst memory standby enable */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK 0x004304d4 /* Mocamac top inst observe clock */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE 0x004304d8 /* Mocaphy top inst clock enable */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS 0x004304dc /* Clock Enable Status */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_MEMORY_STANDBY_ENABLE 0x004304e0 /* Mocaphy top inst memory standby enable */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK 0x004304e4 /* Mocaphy top inst observe clock */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION        0x004304e8 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE            0x004304ec /* Disable PAD's clocks */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS     0x004304f0 /* Clock Disable Status */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION   0x004304f4 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_MUX_SELECT               0x004304f8 /* Mux selects for Pad clocks */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION       0x004304fc /* Select observation clk */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS  0x00430500 /* PLL_AUDIO0 Reset Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS  0x00430504 /* PLL_AUDIO1 Reset Status */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS  0x00430508 /* PLL_AUDIO2 Reset Status */
+#define BCHP_CLKGEN_PLL_AVD1_RDB_MACRO_CTRL      0x0043050c /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS     0x00430510 /* PLL_HIF Reset Status */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST 0x00430514 /* PLL_MIPS Glitchless Clock Switching */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS 0x00430518 /* PLL_MIPS Glitchless Switching */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS    0x0043051c /* PLL_MIPS Reset Status */
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL      0x00430520 /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS    0x00430524 /* PLL_MOCA Reset Status */
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL      0x00430528 /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS 0x0043052c /* PLL_NETWORK Reset Status */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS   0x00430530 /* PLL_RAAGA Reset Status */
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL     0x00430534 /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS     0x00430538 /* PLL_SC0 Reset Status */
+#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL       0x0043053c /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS     0x00430540 /* PLL_SC1 Reset Status */
+#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL       0x00430544 /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE           0x00430548 /* Disable */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS   0x0043054c /* PLL_VCXO0 Reset Status */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS   0x00430550 /* PLL_VCXO1 Reset Status */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS   0x00430554 /* PLL_VCXO2 Reset Status */
+#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL     0x00430558 /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x0043055c /* PLL Alive in Standby Mode */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP           0x00430560 /* Power management LDO PLL */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM        0x00430564 /* Power management LDO PLL state machine */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE 0x00430568 /* Raaga dsp top 0 inst clock enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS 0x0043056c /* Clock Enable Status */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_MEMORY_STANDBY_ENABLE 0x00430570 /* Raaga dsp top 0 inst memory standby enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK 0x00430574 /* Raaga dsp top 0 inst observe clock */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_POWER_SWITCH_MEMORY 0x00430578 /* Raaga dsp top 0 inst power switch memory */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE 0x0043057c /* Raaga dsp top 1 inst clock enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS 0x00430580 /* Clock Enable Status */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_MEMORY_STANDBY_ENABLE 0x00430584 /* Raaga dsp top 1 inst memory standby enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK 0x00430588 /* Raaga dsp top 1 inst observe clock */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_POWER_SWITCH_MEMORY 0x0043058c /* Raaga dsp top 1 inst power switch memory */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE 0x00430590 /* Disable SATA3_TOP_INST's clocks */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS 0x00430594 /* Clock Disable Status */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE  0x00430598 /* Sata3 top inst clock enable */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS 0x0043059c /* Clock Enable Status */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT  0x004305a0 /* Sata3 top inst clock select */
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE 0x004305a4 /* Sata3 top inst memory standby enable */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK 0x004305a8 /* Sata3 top inst observe clock */
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY 0x004305ac /* Sata3 top inst power switch memory */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA 0x004305b0 /* Sectop inst clock enable m2mdma */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_STATUS 0x004305b4 /* Clock Enable Status */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK    0x004305b8 /* Sectop inst observe clock */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT         0x004305bc /* Mux selects for Smartcard clocks */
+#define BCHP_CLKGEN_SPARE                        0x004305c0 /* Spares */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE   0x004305c4 /* Svd0 top inst clock enable */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS 0x004305c8 /* Clock Enable Status */
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE 0x004305cc /* Svd0 top inst memory standby enable */
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY 0x004305d0 /* Svd0 top inst power switch memory */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK   0x004305d4 /* Sys aon inst observe clock */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE  0x004305d8 /* Disable SYS_CTRL_INST's clocks */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS 0x004305dc /* Clock Disable Status */
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE 0x004305e0 /* Sys ctrl inst memory standby enable */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK  0x004305e4 /* Sys ctrl inst observe clock */
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY 0x004305e8 /* Sys ctrl inst power switch memory */
+#define BCHP_CLKGEN_TESTPORT                     0x004305ec /* Special Testport Controls */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE  0x004305f0 /* Disable UHFR_TOP_INST's clocks */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_STATUS 0x004305f4 /* Clock Disable Status */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE   0x004305f8 /* Uhfr top inst clock enable */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_STATUS 0x004305fc /* Clock Enable Status */
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE 0x00430600 /* Uhfr top inst memory standby enable */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK  0x00430604 /* Uhfr top inst observe clock */
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY 0x00430608 /* Uhfr top inst power switch memory */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE      0x0043060c /* Disable USB0_INST's clocks */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_STATUS 0x00430610 /* Clock Disable Status */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE       0x00430614 /* Usb0 inst clock enable */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_STATUS 0x00430618 /* Clock Enable Status */
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE 0x0043061c /* Usb0 inst memory standby enable */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK      0x00430620 /* Usb0 inst observe clock */
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY 0x00430624 /* Usb0 inst power switch memory */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE      0x00430628 /* Disable USB1_INST's clocks */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_STATUS 0x0043062c /* Clock Disable Status */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE       0x00430630 /* Usb1 inst clock enable */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_STATUS 0x00430634 /* Clock Enable Status */
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE 0x00430638 /* Usb1 inst memory standby enable */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK      0x0043063c /* Usb1 inst observe clock */
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY 0x00430640 /* Usb1 inst power switch memory */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE    0x00430644 /* V3d top inst clock enable */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS 0x00430648 /* Clock Enable Status */
+#define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE 0x0043064c /* V3d top inst memory standby enable */
+#define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY 0x00430650 /* V3d top inst power switch memory */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE 0x00430654 /* Disable VEC_AIO_TOP_INST's clocks */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS 0x00430658 /* Clock Disable Status */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO 0x0043065c /* Vec aio top inst clock enable aio */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS 0x00430660 /* Clock Enable Status */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC 0x00430664 /* Vec aio top inst clock enable vec */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS 0x00430668 /* Clock Enable Status */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO 0x0043066c /* Vec aio top inst memory standby enable aio */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC 0x00430670 /* Vec aio top inst memory standby enable vec */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK 0x00430674 /* Vec aio top inst observe clock */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO 0x00430678 /* Vec aio top inst power switch memory aio */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC 0x0043067c /* Vec aio top inst power switch memory vec */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE    0x00430680 /* Vice2 1 inst clock enable */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS 0x00430684 /* Clock Enable Status */
+#define BCHP_CLKGEN_VICE2_1_INST_MEMORY_STANDBY_ENABLE 0x00430688 /* Vice2 1 inst memory standby enable */
+#define BCHP_CLKGEN_VICE2_1_INST_POWER_SWITCH_MEMORY 0x0043068c /* Vice2 1 inst power switch memory */
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE      0x00430690 /* Vice2 inst clock enable */
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_STATUS 0x00430694 /* Clock Enable Status */
+#define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE 0x00430698 /* Vice2 inst memory standby enable */
+#define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY 0x0043069c /* Vice2 inst power switch memory */
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_DISABLE 0x004306a0 /* Disable ZCPU_DUAL_TOP_INST's clocks */
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_STATUS 0x004306a4 /* Clock Disable Status */
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE 0x004306a8 /* Zcpu dual top inst clock enable */
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS 0x004306ac /* Clock Enable Status */
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK 0x004306b0 /* Zcpu dual top inst observe clock */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS 0x004306b8 /* Bypass GENET_TOP_DUAL_RGMII_INST's clocks */
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT                0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000001
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT                0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000001
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO2_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL_REF_SEL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO2_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_PDIV_DEFAULT                0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000001
+
+/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO2_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO2_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN_PWRDN_PLL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO2_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETD_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AUDIO2_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO2_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x0000007b
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AVD1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_AVD1_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_PDIV_DEFAULT                  0x00000003
+
+/* CLKGEN :: PLL_AVD1_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_NDIV_INT_DEFAULT              0x000000a4
+
+/***************************************************************************
+ *PLL_AVD1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_AVD1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_AVD1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000002
+
+/* CLKGEN :: PLL_AVD1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AVD1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_LDO_PWRDN - LDO Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_LDO_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_LDO_PWRDN_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD1_PLL_LDO_PWRDN_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AVD1_PLL_LDO_PWRDN :: LDO_PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_LDO_PWRDN_LDO_PWRDN_PLL_MASK      0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_LDO_PWRDN_LDO_PWRDN_PLL_SHIFT     0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_LDO_PWRDN_LDO_PWRDN_PLL_DEFAULT   0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_AVD1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_AVD1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_AVD1_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCODIV2_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_PWM_RATE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_POR_BYPASS_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_LDO_REF_SEL_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_AVD1_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2_SPARE_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_AVD1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_RESET :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_AVD1_PLL_RESET :: RESETD [00:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_RESETD_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_RESETD_SHIFT                0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_RESETD_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_AVD1_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_AVD1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AVD1_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_AVD1_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_HIF_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:15] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xffff8000
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  15
+
+/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [14:14] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00004000
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 14
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [12:10] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00001c00
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 10
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [09:02] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000003fc
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   2
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000001b
+
+/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: CML_CLOCK_EN_CH0 [01:01] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CML_CLOCK_EN_CH0_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CML_CLOCK_EN_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CML_CLOCK_EN_CH0_DEFAULT 0x00000001
+
+/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_HIF_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_HIF_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL_REF_SEL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL_REF_SEL_SHIFT              0
+#define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL_REF_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_HIF_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_DIV :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_reserved0_MASK                 0xfffff800
+#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_reserved0_SHIFT                11
+
+/* CLKGEN :: PLL_HIF_PLL_DIV :: PDIV [10:08] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_PDIV_MASK                      0x00000700
+#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_PDIV_SHIFT                     8
+#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_PDIV_DEFAULT                   0x00000001
+
+/* CLKGEN :: PLL_HIF_PLL_DIV :: NDIV_INT [07:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_NDIV_INT_MASK                  0x000000ff
+#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_NDIV_INT_SHIFT                 0
+#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_NDIV_INT_DEFAULT               0x00000032
+
+/***************************************************************************
+ *PLL_HIF_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_FRAC_reserved0_MASK                0xfff00000
+#define BCHP_CLKGEN_PLL_HIF_PLL_FRAC_reserved0_SHIFT               20
+
+/* CLKGEN :: PLL_HIF_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_FRAC_FRAC_CONTROL_MASK             0x000fffff
+#define BCHP_CLKGEN_PLL_HIF_PLL_FRAC_FRAC_CONTROL_SHIFT            0
+#define BCHP_CLKGEN_PLL_HIF_PLL_FRAC_FRAC_CONTROL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_HIF_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_GAIN :: reserved0 [31:10] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_reserved0_MASK                0xfffffc00
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_reserved0_SHIFT               10
+
+/* CLKGEN :: PLL_HIF_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x0000000b
+
+/* CLKGEN :: PLL_HIF_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x00000038
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       3
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     0x00000003
+
+/* CLKGEN :: PLL_HIF_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
+#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003
+
+/***************************************************************************
+ *PLL_HIF_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_PLL_HIF_PLL_LOCK_STATUS_reserved0_SHIFT        1
+
+/* CLKGEN :: PLL_HIF_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_HIF_PLL_LOCK_STATUS_LOCK_SHIFT             0
+
+/***************************************************************************
+ *PLL_HIF_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_MISC :: reserved0 [31:28] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_reserved0_MASK                0xf0000000
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_reserved0_SHIFT               28
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: VCODIV2 [27:27] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_VCODIV2_MASK                  0x08000000
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_VCODIV2_SHIFT                 27
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_VCODIV2_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: STAT_UPDATE [26:26] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_UPDATE_MASK              0x04000000
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_UPDATE_SHIFT             26
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_UPDATE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: STAT_SELECT [25:23] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_SELECT_MASK              0x03800000
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_SELECT_SHIFT             23
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_SELECT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: STAT_RESET_ [22:22] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_RESET__MASK              0x00400000
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_RESET__SHIFT             22
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_RESET__DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: REFCLKOUT [21:21] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_REFCLKOUT_MASK                0x00200000
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_REFCLKOUT_SHIFT               21
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_REFCLKOUT_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: LDO_CONTROL [20:19] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_LDO_CONTROL_MASK              0x00180000
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_LDO_CONTROL_SHIFT             19
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_LDO_CONTROL_DEFAULT           0x00000001
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: HYST_EN [18:18] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_HYST_EN_MASK                  0x00040000
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_HYST_EN_SHIFT                 18
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_HYST_EN_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: DIGITAL_LDO_CONTROL [17:16] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DIGITAL_LDO_CONTROL_MASK      0x00030000
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DIGITAL_LDO_CONTROL_SHIFT     16
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DIGITAL_LDO_CONTROL_DEFAULT   0x00000001
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [15:15] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00008000
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  15
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: DCO_CTRL_BYPASS [14:03] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00007ff8
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         3
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: AUX_CTRL [02:02] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_AUX_CTRL_MASK                 0x00000004
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_AUX_CTRL_SHIFT                2
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_AUX_CTRL_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_MISC :: ANALOG_LDO_CONTROL [01:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_ANALOG_LDO_CONTROL_MASK       0x00000003
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_ANALOG_LDO_CONTROL_SHIFT      0
+#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_ANALOG_LDO_CONTROL_DEFAULT    0x00000001
+
+/***************************************************************************
+ *PLL_HIF_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_HIF_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN_PWRDN_PLL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN_PWRDN_PLL_SHIFT              0
+#define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN_PWRDN_PLL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_HIF_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_reserved0_MASK               0xfffffffc
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_reserved0_SHIFT              2
+
+/* CLKGEN :: PLL_HIF_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETD_MASK                  0x00000002
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETD_SHIFT                 1
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETD_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_HIF_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETA_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETA_SHIFT                 0
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETA_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_HIF_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_STATUS_reserved0_MASK              0xfffff000
+#define BCHP_CLKGEN_PLL_HIF_PLL_STATUS_reserved0_SHIFT             12
+
+/* CLKGEN :: PLL_HIF_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
+#define BCHP_CLKGEN_PLL_HIF_PLL_STATUS_TEST_STATUS_SHIFT           0
+
+/***************************************************************************
+ *PLL_HIF_PLL_TRI_EN - Cml buffer Tristate enable
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_TRI_EN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_HIF_PLL_TRI_EN :: TRI_EN [00:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN_TRI_EN_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN_TRI_EN_SHIFT                0
+#define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN_TRI_EN_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000064
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PLL_MIPS_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_MIPS_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_DEFAULT                  0x00000002
+
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_DEFAULT              0x00000068
+
+/***************************************************************************
+ *PLL_MIPS_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_FRAC_reserved0_MASK               0xfff00000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_FRAC_reserved0_SHIFT              20
+
+/* CLKGEN :: PLL_MIPS_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_FRAC_FRAC_CONTROL_MASK            0x000fffff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_FRAC_FRAC_CONTROL_SHIFT           0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_FRAC_FRAC_CONTROL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000002
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_LDO_PWRDN - LDO Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_LDO_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LDO_PWRDN_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LDO_PWRDN_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_MIPS_PLL_LDO_PWRDN :: LDO_PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LDO_PWRDN_LDO_PWRDN_PLL_MASK      0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LDO_PWRDN_LDO_PWRDN_PLL_SHIFT     0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LDO_PWRDN_LDO_PWRDN_PLL_DEFAULT   0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MIPS_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000c
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000024
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_MOCA_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_DEFAULT                  0x00000003
+
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_DEFAULT              0x000000c8
+
+/***************************************************************************
+ *PLL_MOCA_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000002
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_LDO_PWRDN - LDO Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_LDO_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRDN_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRDN_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_MOCA_PLL_LDO_PWRDN :: LDO_PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRDN_LDO_PWRDN_PLL_MASK      0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRDN_LDO_PWRDN_PLL_SHIFT     0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRDN_LDO_PWRDN_PLL_DEFAULT   0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_DEFAULT              0x00000001
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_DEFAULT             0x00000002
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MOCA_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_MOCA_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000012
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000005a
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000001c
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL_reserved0_SHIFT        1
+
+/* CLKGEN :: PLL_NETWORK_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL_REF_SEL_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL_REF_SEL_SHIFT          0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL_REF_SEL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_reserved0_MASK             0xffffe000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_reserved0_SHIFT            13
+
+/* CLKGEN :: PLL_NETWORK_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_PDIV_MASK                  0x00001c00
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_PDIV_SHIFT                 10
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_PDIV_DEFAULT               0x00000003
+
+/* CLKGEN :: PLL_NETWORK_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_NDIV_INT_MASK              0x000003ff
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_NDIV_INT_SHIFT             0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_NDIV_INT_DEFAULT           0x0000007d
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_reserved0_MASK            0xff000000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_reserved0_SHIFT           24
+
+/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK    0x000000e0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT   5
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_LDO_PWRDN - LDO Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_LDO_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRDN_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRDN_reserved0_SHIFT      1
+
+/* CLKGEN :: PLL_NETWORK_PLL_LDO_PWRDN :: LDO_PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRDN_LDO_PWRDN_PLL_MASK   0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRDN_LDO_PWRDN_PLL_SHIFT  0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRDN_LDO_PWRDN_PLL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_NETWORK_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_LOST_MASK     0x00000002
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_LOST_SHIFT    1
+
+/* CLKGEN :: PLL_NETWORK_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_SHIFT         0
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_reserved0_MASK            0x80000000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_reserved0_SHIFT           31
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_DLY_MASK              0x60000000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_DLY_SHIFT             29
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_DLY_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCODIV2_MASK              0x10000000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCODIV2_SHIFT             28
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCODIV2_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_UPDATE_MASK          0x08000000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_UPDATE_SHIFT         27
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_UPDATE_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_SELECT_MASK          0x07000000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_SELECT_SHIFT         24
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_SELECT_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_RESET__MASK          0x00800000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_RESET__SHIFT         23
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_RESET__DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_MODE_MASK            0x00600000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_MODE_SHIFT           21
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_MODE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_REFCLKOUT_MASK            0x00100000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_REFCLKOUT_SHIFT           20
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_REFCLKOUT_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PWM_RATE_MASK             0x000c0000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PWM_RATE_SHIFT            18
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PWM_RATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_POR_BYPASS_MASK           0x00020000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_POR_BYPASS_SHIFT          17
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_POR_BYPASS_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_NDIV_RELOCK_MASK          0x00010000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_NDIV_RELOCK_SHIFT         16
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_NDIV_RELOCK_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_LDO_REF_SEL_MASK          0x00008000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_LDO_REF_SEL_SHIFT         15
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_LDO_REF_SEL_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_FAST_LOCK_MASK            0x00004000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_FAST_LOCK_SHIFT           14
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_FAST_LOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_MASK      0x00001ffe
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_SHIFT     1
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT   0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_AUX_CTRL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_AUX_CTRL_SHIFT            0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_AUX_CTRL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_SPARE_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_SPARE_SHIFT              0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_SPARE_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_NETWORK_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN_PWRDN_PLL_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN_PWRDN_PLL_SHIFT          0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN_PWRDN_PLL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_reserved0_MASK           0xfffffffc
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_reserved0_SHIFT          2
+
+/* CLKGEN :: PLL_NETWORK_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETD_MASK              0x00000002
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETD_SHIFT             1
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETD_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETA_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETA_SHIFT             0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETA_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_reserved0_MASK          0xfffff000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_reserved0_SHIFT         12
+
+/* CLKGEN :: PLL_NETWORK_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_TEST_STATUS_MASK        0x00000fff
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_TEST_STATUS_SHIFT       0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_RAAGA_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_SHIFT            0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_MASK               0xffffe000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_SHIFT              13
+
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_MASK                    0x00001c00
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_SHIFT                   10
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_DEFAULT                 0x00000002
+
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_MASK                0x000003ff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_SHIFT               0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_DEFAULT             0x0000008f
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_MASK              0xff000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_SHIFT             24
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x000000e0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     5
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000002
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_LDO_PWRDN - LDO Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_LDO_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRDN_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRDN_reserved0_SHIFT        1
+
+/* CLKGEN :: PLL_RAAGA_PLL_LDO_PWRDN :: LDO_PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRDN_LDO_PWRDN_PLL_MASK     0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRDN_LDO_PWRDN_PLL_SHIFT    0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRDN_LDO_PWRDN_PLL_DEFAULT  0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_MASK       0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT      1
+
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_SHIFT           0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_reserved0_MASK              0x80000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_reserved0_SHIFT             31
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_MASK                0x60000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_SHIFT               29
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_MASK                0x10000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_SHIFT               28
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_DEFAULT             0x00000001
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_SHIFT           27
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_MASK            0x07000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_SHIFT           24
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__MASK            0x00800000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__SHIFT           23
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_MASK              0x00600000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_SHIFT             21
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_MASK              0x00100000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_SHIFT             20
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_MASK               0x000c0000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_SHIFT              18
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_DEFAULT            0x00000002
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_MASK             0x00020000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_SHIFT            17
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_MASK            0x00010000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_SHIFT           16
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_MASK            0x00008000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_SHIFT           15
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_MASK              0x00004000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_SHIFT             14
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00001ffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_SHIFT              0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_SHIFT                0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_RAAGA_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_SHIFT            0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_MASK             0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_SHIFT            2
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_MASK                0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_SHIFT               1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_SHIFT               0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_MASK            0xfffff000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_SHIFT           12
+
+/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_SHIFT         0
+
+/***************************************************************************
+ *PLL_SC0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000030
+
+/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CONTROL_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_SC0_PLL_CONTROL_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_SC0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CONTROL_REF_SEL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC0_PLL_CONTROL_REF_SEL_SHIFT              0
+#define BCHP_CLKGEN_PLL_SC0_PLL_CONTROL_REF_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_reserved0_MASK                 0xffffe000
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_reserved0_SHIFT                13
+
+/* CLKGEN :: PLL_SC0_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_MASK                      0x00001c00
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_SHIFT                     10
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_DEFAULT                   0x00000001
+
+/* CLKGEN :: PLL_SC0_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_MASK                  0x000003ff
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_DEFAULT               0x00000018
+
+/***************************************************************************
+ *PLL_SC0_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_reserved0_MASK                0xfff00000
+#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_reserved0_SHIFT               20
+
+/* CLKGEN :: PLL_SC0_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_MASK             0x000fffff
+#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_SHIFT            0
+#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_reserved0_MASK                0xff000000
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_reserved0_SHIFT               24
+
+/* CLKGEN :: PLL_SC0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x000000e0
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       5
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     0x00000001
+
+/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_SC0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_reserved0_SHIFT        1
+
+/* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_SHIFT             0
+
+/***************************************************************************
+ *PLL_SC0_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_reserved0_MASK                0xc0000000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_reserved0_SHIFT               30
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_DLY_MASK                  0x30000000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_DLY_SHIFT                 28
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_DLY_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCODIV2_POST_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCODIV2_POST_SHIFT            27
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCODIV2_POST_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCODIV2_MASK                  0x04000000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCODIV2_SHIFT                 26
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCODIV2_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_MASK              0x02000000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_SHIFT             25
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_MASK              0x01c00000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_SHIFT             22
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET__MASK              0x00200000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET__SHIFT             21
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET__DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_MASK                0x00180000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_SHIFT               19
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_REFCLKOUT_MASK                0x00040000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_REFCLKOUT_SHIFT               18
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_REFCLKOUT_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_MASK                 0x00030000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_SHIFT                16
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_MDIV_RELOCK_MASK              0x00008000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_MDIV_RELOCK_SHIFT             15
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_MDIV_RELOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_MASK                0x00004000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_SHIFT               14
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00002000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  13
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00001ffe
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         1
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_AUX_CTRL_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_AUX_CTRL_SHIFT                0
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_AUX_CTRL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_PWRDN_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_SC0_PLL_PWRDN_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_SC0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_PWRDN_PWRDN_PLL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC0_PLL_PWRDN_PWRDN_PLL_SHIFT              0
+#define BCHP_CLKGEN_PLL_SC0_PLL_PWRDN_PWRDN_PLL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_reserved0_MASK               0xfffffffc
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_reserved0_SHIFT              2
+
+/* CLKGEN :: PLL_SC0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_MASK                  0x00000002
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_SHIFT                 1
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_reserved0_MASK              0xfffff000
+#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_reserved0_SHIFT             12
+
+/* CLKGEN :: PLL_SC0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
+#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_TEST_STATUS_SHIFT           0
+
+/***************************************************************************
+ *PLL_SC1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000030
+
+/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CONTROL_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_SC1_PLL_CONTROL_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_SC1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CONTROL_REF_SEL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC1_PLL_CONTROL_REF_SEL_SHIFT              0
+#define BCHP_CLKGEN_PLL_SC1_PLL_CONTROL_REF_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_reserved0_MASK                 0xffffe000
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_reserved0_SHIFT                13
+
+/* CLKGEN :: PLL_SC1_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_MASK                      0x00001c00
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_SHIFT                     10
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_DEFAULT                   0x00000001
+
+/* CLKGEN :: PLL_SC1_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_MASK                  0x000003ff
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_DEFAULT               0x00000018
+
+/***************************************************************************
+ *PLL_SC1_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_reserved0_MASK                0xfff00000
+#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_reserved0_SHIFT               20
+
+/* CLKGEN :: PLL_SC1_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_MASK             0x000fffff
+#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_SHIFT            0
+#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_reserved0_MASK                0xff000000
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_reserved0_SHIFT               24
+
+/* CLKGEN :: PLL_SC1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x000000e0
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       5
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     0x00000001
+
+/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_SC1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_reserved0_SHIFT        1
+
+/* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_SHIFT             0
+
+/***************************************************************************
+ *PLL_SC1_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_reserved0_MASK                0xc0000000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_reserved0_SHIFT               30
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_DLY_MASK                  0x30000000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_DLY_SHIFT                 28
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_DLY_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCODIV2_POST_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCODIV2_POST_SHIFT            27
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCODIV2_POST_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCODIV2_MASK                  0x04000000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCODIV2_SHIFT                 26
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCODIV2_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_MASK              0x02000000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_SHIFT             25
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_MASK              0x01c00000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_SHIFT             22
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET__MASK              0x00200000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET__SHIFT             21
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET__DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_MASK                0x00180000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_SHIFT               19
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_REFCLKOUT_MASK                0x00040000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_REFCLKOUT_SHIFT               18
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_REFCLKOUT_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_MASK                 0x00030000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_SHIFT                16
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_MDIV_RELOCK_MASK              0x00008000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_MDIV_RELOCK_SHIFT             15
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_MDIV_RELOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_MASK                0x00004000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_SHIFT               14
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00002000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  13
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00001ffe
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         1
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_AUX_CTRL_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_AUX_CTRL_SHIFT                0
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_AUX_CTRL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_PWRDN_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_SC1_PLL_PWRDN_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_SC1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_PWRDN_PWRDN_PLL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC1_PLL_PWRDN_PWRDN_PLL_SHIFT              0
+#define BCHP_CLKGEN_PLL_SC1_PLL_PWRDN_PWRDN_PLL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_reserved0_MASK               0xfffffffc
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_reserved0_SHIFT              2
+
+/* CLKGEN :: PLL_SC1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_MASK                  0x00000002
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_SHIFT                 1
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_reserved0_MASK              0xfffff000
+#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_reserved0_SHIFT             12
+
+/* CLKGEN :: PLL_SC1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
+#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_TEST_STATUS_SHIFT           0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000012
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000c
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x000000a2
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000e
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT                  0x00000001
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT              0x00000048
+
+/***************************************************************************
+ *PLL_SYS0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x0000000a
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000003
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_LDO_PWRDN - LDO Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_LDO_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRDN_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRDN_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_SYS0_PLL_LDO_PWRDN :: LDO_PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRDN_LDO_PWRDN_PLL_MASK      0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRDN_LDO_PWRDN_PLL_SHIFT     0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRDN_LDO_PWRDN_PLL_DEFAULT   0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT              0x00000001
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT             0x00000002
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_RESET :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_RESET :: RESETD [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000004b
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_VCXO0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_REF_SEL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_REF_SEL_SHIFT            0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_REF_SEL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_reserved0_MASK               0xffffe000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_reserved0_SHIFT              13
+
+/* CLKGEN :: PLL_VCXO0_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_MASK                    0x00001c00
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_SHIFT                   10
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_DEFAULT                 0x00000002
+
+/* CLKGEN :: PLL_VCXO0_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_MASK                0x000003ff
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_DEFAULT             0x00000040
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_reserved0_MASK              0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_reserved0_SHIFT             20
+
+/* CLKGEN :: PLL_VCXO0_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_MASK           0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_SHIFT          0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_reserved0_MASK              0xff000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_reserved0_SHIFT             24
+
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x000000e0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     5
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000001
+
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_reserved0_SHIFT      1
+
+/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_SHIFT           0
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_reserved0_MASK              0xc0000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_reserved0_SHIFT             30
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DLY_MASK                0x30000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DLY_SHIFT               28
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DLY_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_POST_MASK           0x08000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_POST_SHIFT          27
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_POST_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_MASK                0x04000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_SHIFT               26
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_MASK            0x02000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_SHIFT           25
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_MASK            0x01c00000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_SHIFT           22
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET__MASK            0x00200000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET__SHIFT           21
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET__DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_MASK              0x00180000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_SHIFT             19
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REFCLKOUT_MASK              0x00040000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REFCLKOUT_SHIFT             18
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REFCLKOUT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_MASK               0x00030000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_SHIFT              16
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_MDIV_RELOCK_MASK            0x00008000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_MDIV_RELOCK_SHIFT           15
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_MDIV_RELOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_MASK              0x00004000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_SHIFT             14
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00001ffe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_SHIFT              0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_VCXO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_PWRDN_PLL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_PWRDN_PLL_SHIFT            0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_PWRDN_PLL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_reserved0_MASK             0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_reserved0_SHIFT            2
+
+/* CLKGEN :: PLL_VCXO0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_MASK                0x00000002
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_SHIFT               1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_reserved0_MASK            0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_reserved0_SHIFT           12
+
+/* CLKGEN :: PLL_VCXO0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_TEST_STATUS_SHIFT         0
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000004b
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_VCXO1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_REF_SEL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_REF_SEL_SHIFT            0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_REF_SEL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_reserved0_MASK               0xffffe000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_reserved0_SHIFT              13
+
+/* CLKGEN :: PLL_VCXO1_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_MASK                    0x00001c00
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_SHIFT                   10
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_DEFAULT                 0x00000002
+
+/* CLKGEN :: PLL_VCXO1_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_MASK                0x000003ff
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_DEFAULT             0x00000040
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_reserved0_MASK              0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_reserved0_SHIFT             20
+
+/* CLKGEN :: PLL_VCXO1_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_MASK           0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_SHIFT          0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_reserved0_MASK              0xff000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_reserved0_SHIFT             24
+
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x000000e0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     5
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000001
+
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_reserved0_SHIFT      1
+
+/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_SHIFT           0
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_reserved0_MASK              0xc0000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_reserved0_SHIFT             30
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DLY_MASK                0x30000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DLY_SHIFT               28
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DLY_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_POST_MASK           0x08000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_POST_SHIFT          27
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_POST_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_MASK                0x04000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_SHIFT               26
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_MASK            0x02000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_SHIFT           25
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_MASK            0x01c00000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_SHIFT           22
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET__MASK            0x00200000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET__SHIFT           21
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET__DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_MASK              0x00180000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_SHIFT             19
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REFCLKOUT_MASK              0x00040000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REFCLKOUT_SHIFT             18
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REFCLKOUT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_MASK               0x00030000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_SHIFT              16
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_MDIV_RELOCK_MASK            0x00008000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_MDIV_RELOCK_SHIFT           15
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_MDIV_RELOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_MASK              0x00004000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_SHIFT             14
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00001ffe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_SHIFT              0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_VCXO1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_PWRDN_PLL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_PWRDN_PLL_SHIFT            0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_PWRDN_PLL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_reserved0_MASK             0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_reserved0_SHIFT            2
+
+/* CLKGEN :: PLL_VCXO1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_MASK                0x00000002
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_SHIFT               1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_reserved0_MASK            0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_reserved0_SHIFT           12
+
+/* CLKGEN :: PLL_VCXO1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_TEST_STATUS_SHIFT         0
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000004b
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_VCXO2_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL_REF_SEL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL_REF_SEL_SHIFT            0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL_REF_SEL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_reserved0_MASK               0xffffe000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_reserved0_SHIFT              13
+
+/* CLKGEN :: PLL_VCXO2_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_MASK                    0x00001c00
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_SHIFT                   10
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_DEFAULT                 0x00000002
+
+/* CLKGEN :: PLL_VCXO2_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_MASK                0x000003ff
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_DEFAULT             0x00000040
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_reserved0_MASK              0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_reserved0_SHIFT             20
+
+/* CLKGEN :: PLL_VCXO2_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_MASK           0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_SHIFT          0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_reserved0_MASK              0xff000000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_reserved0_SHIFT             24
+
+/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x000000e0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     5
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000001
+
+/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_reserved0_SHIFT      1
+
+/* CLKGEN :: PLL_VCXO2_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_SHIFT           0
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_reserved0_MASK              0xc0000000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_reserved0_SHIFT             30
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DLY_MASK                0x30000000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DLY_SHIFT               28
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DLY_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_POST_MASK           0x08000000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_POST_SHIFT          27
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_POST_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_MASK                0x04000000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_SHIFT               26
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_MASK            0x02000000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_SHIFT           25
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_MASK            0x01c00000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_SHIFT           22
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET__MASK            0x00200000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET__SHIFT           21
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET__DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_MASK              0x00180000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_SHIFT             19
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REFCLKOUT_MASK              0x00040000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REFCLKOUT_SHIFT             18
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REFCLKOUT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_MASK               0x00030000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_SHIFT              16
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_MDIV_RELOCK_MASK            0x00008000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_MDIV_RELOCK_SHIFT           15
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_MDIV_RELOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_MASK              0x00004000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_SHIFT             14
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00001ffe
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       1
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_SHIFT              0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_VCXO2_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN_PWRDN_PLL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN_PWRDN_PLL_SHIFT            0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN_PWRDN_PLL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_reserved0_MASK             0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_reserved0_SHIFT            2
+
+/* CLKGEN :: PLL_VCXO2_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_MASK                0x00000002
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_SHIFT               1
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_reserved0_MASK            0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_reserved0_SHIFT           12
+
+/* CLKGEN :: PLL_VCXO2_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_TEST_STATUS_SHIFT         0
+
+/***************************************************************************
+ *PLL_XPT_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000000d
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT   1
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000a
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT   1
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000000a
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT   1
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000d
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CONTROL_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_XPT_PLL_CONTROL_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_XPT_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CONTROL_REF_SEL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_XPT_PLL_CONTROL_REF_SEL_SHIFT              0
+#define BCHP_CLKGEN_PLL_XPT_PLL_CONTROL_REF_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_reserved0_MASK                 0xffffe000
+#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_reserved0_SHIFT                13
+
+/* CLKGEN :: PLL_XPT_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_MASK                      0x00001c00
+#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_SHIFT                     10
+#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_DEFAULT                   0x00000002
+
+/* CLKGEN :: PLL_XPT_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_MASK                  0x000003ff
+#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_SHIFT                 0
+#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_DEFAULT               0x00000082
+
+/***************************************************************************
+ *PLL_XPT_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_reserved0_MASK                0xff000000
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_reserved0_SHIFT               24
+
+/* CLKGEN :: PLL_XPT_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x000000e0
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       5
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     0x00000002
+
+/* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
+
+/* CLKGEN :: PLL_XPT_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_LDO_PWRDN - LDO Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_LDO_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRDN_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRDN_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_XPT_PLL_LDO_PWRDN :: LDO_PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRDN_LDO_PWRDN_PLL_MASK       0x00000001
+#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRDN_LDO_PWRDN_PLL_SHIFT      0
+#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRDN_LDO_PWRDN_PLL_DEFAULT    0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_LOST_MASK         0x00000002
+#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_LOST_SHIFT        1
+
+/* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_SHIFT             0
+
+/***************************************************************************
+ *PLL_XPT_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_reserved0_MASK                0x80000000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_reserved0_SHIFT               31
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_DLY_MASK                  0x60000000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_DLY_SHIFT                 29
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_DLY_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCODIV2_MASK                  0x10000000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCODIV2_SHIFT                 28
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCODIV2_DEFAULT               0x00000001
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_MASK              0x08000000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_SHIFT             27
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_MASK              0x07000000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_SHIFT             24
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET__MASK              0x00800000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET__SHIFT             23
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET__DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_MASK                0x00600000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_SHIFT               21
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_REFCLKOUT_MASK                0x00100000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_REFCLKOUT_SHIFT               20
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_REFCLKOUT_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_MASK                 0x000c0000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_SHIFT                18
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_DEFAULT              0x00000002
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POR_BYPASS_MASK               0x00020000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POR_BYPASS_SHIFT              17
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POR_BYPASS_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_MASK              0x00010000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_SHIFT             16
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_LDO_REF_SEL_MASK              0x00008000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_LDO_REF_SEL_SHIFT             15
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_LDO_REF_SEL_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_MASK                0x00004000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_SHIFT               14
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00002000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  13
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00001ffe
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         1
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_AUX_CTRL_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_AUX_CTRL_SHIFT                0
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_AUX_CTRL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_XPT_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_SPARE_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_SPARE_SHIFT                  0
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_SPARE_DEFAULT                0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_PWRDN_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_XPT_PLL_PWRDN_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_XPT_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_PWRDN_PWRDN_PLL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_XPT_PLL_PWRDN_PWRDN_PLL_SHIFT              0
+#define BCHP_CLKGEN_PLL_XPT_PLL_PWRDN_PWRDN_PLL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_RESET :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_XPT_PLL_RESET :: RESETD [00:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_SHIFT                 0
+#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_reserved0_MASK              0xfffff000
+#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_reserved0_SHIFT             12
+
+/* CLKGEN :: PLL_XPT_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
+#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_TEST_STATUS_SHIFT           0
+
+/***************************************************************************
+ *AVD0_TOP_INST_CLOCK_ENABLE - Avd0 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffff0
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     4
+
+/* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE :: AVD1_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE :: AVD1_CPU_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_CPU_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_CPU_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_CPU_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE :: AVD1_CORE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_CORE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_CORE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE :: AVD1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_AVD1_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *AVD0_TOP_INST_CLOCK_ENABLE_SID - Avd0 top inst clock enable sid
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE_SID :: reserved0 [31:01] */
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_SID_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_SID_reserved0_SHIFT 1
+
+/* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE_SID :: SID_328_CLOCK_ENABLE_SID [00:00] */
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_SID_SID_328_CLOCK_ENABLE_SID_MASK 0x00000001
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_SID_SID_328_CLOCK_ENABLE_SID_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_SID_SID_328_CLOCK_ENABLE_SID_DEFAULT 0x00000001
+
+/***************************************************************************
+ *AVD0_TOP_INST_CLOCK_ENABLE_SID_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE_SID_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_SID_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_SID_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE_SID_STATUS :: SID_216_CLOCK_ENABLE_SID_STATUS [00:00] */
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_SID_STATUS_SID_216_CLOCK_ENABLE_SID_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_SID_STATUS_SID_216_CLOCK_ENABLE_SID_STATUS_SHIFT 0
+
+/***************************************************************************
+ *AVD0_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
+
+/* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE_STATUS :: AVD1_SCB_CLOCK_ENABLE_STATUS [03:03] */
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_STATUS_AVD1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_STATUS_AVD1_SCB_CLOCK_ENABLE_STATUS_SHIFT 3
+
+/* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE_STATUS :: AVD1_CPU_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_STATUS_AVD1_CPU_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_STATUS_AVD1_CPU_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE_STATUS :: AVD1_CORE_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_STATUS_AVD1_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_STATUS_AVD1_CORE_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: AVD0_TOP_INST_CLOCK_ENABLE_STATUS :: AVD1_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_STATUS_AVD1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_AVD0_TOP_INST_CLOCK_ENABLE_STATUS_AVD1_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *AVD0_TOP_INST_MEMORY_STANDBY_ENABLE - Avd0 top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_AVD0_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_AVD0_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: AVD0_TOP_INST_MEMORY_STANDBY_ENABLE :: AVD1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_AVD0_TOP_INST_MEMORY_STANDBY_ENABLE_AVD1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_AVD0_TOP_INST_MEMORY_STANDBY_ENABLE_AVD1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_INST_MEMORY_STANDBY_ENABLE_AVD1_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AVD0_TOP_INST_OBSERVE_CLOCK - Avd0 top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: AVD0_TOP_INST_OBSERVE_CLOCK :: AVD1_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: AVD0_TOP_INST_OBSERVE_CLOCK :: AVD1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: AVD0_TOP_INST_OBSERVE_CLOCK :: AVD1_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK_AVD1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK_AVD1_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_INST_OBSERVE_CLOCK_AVD1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AVD0_TOP_INST_POWER_SWITCH_MEMORY - Avd0 top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_AVD0_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_AVD0_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: AVD0_TOP_INST_POWER_SWITCH_MEMORY :: AVD1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_AVD0_TOP_INST_POWER_SWITCH_MEMORY_AVD1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_AVD0_TOP_INST_POWER_SWITCH_MEMORY_AVD1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_INST_POWER_SWITCH_MEMORY_AVD1_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BVN_MVP_TOP_INST_CLOCK_ENABLE - Bvn mvp top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffff8
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  3
+
+/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_SCB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_216_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_216_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVP_TOP_INST_MEMORY_STANDBY_ENABLE - Bvn mvp top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_MVP_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: BVN_MVP_TOP_INST_MEMORY_STANDBY_ENABLE :: BVND_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_MEMORY_STANDBY_ENABLE_BVND_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_MEMORY_STANDBY_ENABLE_BVND_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_MEMORY_STANDBY_ENABLE_BVND_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BVN_MVP_TOP_INST_POWER_SWITCH_MEMORY - Bvn mvp top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BVN_MVP_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: BVN_MVP_TOP_INST_POWER_SWITCH_MEMORY :: BVND_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_POWER_SWITCH_MEMORY_BVND_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_POWER_SWITCH_MEMORY_BVND_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_POWER_SWITCH_MEMORY_BVND_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BVN_TOP_INST_CLOCK_ENABLE - Bvn top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffff8
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      3
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *BVN_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_SCB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_216_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_216_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *BVN_TOP_INST_MEMORY_STANDBY_ENABLE - Bvn top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: BVN_TOP_INST_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BVN_TOP_INST_POWER_SWITCH_MEMORY - Bvn top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: BVN_TOP_INST_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks
+ ***************************************************************************/
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT           2
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_OSC_DIGITAL_CLOCK [01:01] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_AVS_CLOCK [00:00] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_MASK    0x00000001
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_SHIFT   0
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CLKGEN_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: DISABLE_OSC_DIGITAL_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_OSC_DIGITAL_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_OSC_DIGITAL_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: DISABLE_AVS_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_AVS_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_AVS_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_CONTROL - Clock Monitor Control
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT          4
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK   0x00000008
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT  3
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK    0x00000004
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT   2
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK      0x00000002
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT     1
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT   0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK  0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT         1
+
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK     0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT    0
+
+/***************************************************************************
+ *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_CLOCK_DISABLE - Disable CORE_XPT_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_MASK     0xffffffe0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_SHIFT    5
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:05] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 5
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_81_CLOCK_STATUS [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_81_CLOCK_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_81_CLOCK_STATUS_SHIFT 4
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_54_CLOCK_STATUS [03:03] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_54_CLOCK_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_54_CLOCK_STATUS_SHIFT 3
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_40P5_CLOCK_STATUS [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_40P5_CLOCK_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_40P5_CLOCK_STATUS_SHIFT 2
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_27_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_27_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_27_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_20P25_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_20P25_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_20P25_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_CLOCK_ENABLE - Core xpt inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffff8
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_SHIFT     3
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_CORE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CORE_XPT_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_SCB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_CORE_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_CORE_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_MEMORY_STANDBY_ENABLE - Core xpt inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: CORE_XPT_INST_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_INST_OBSERVE_CLOCK - Core xpt inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_INST_POWER_SWITCH_MEMORY - Core xpt inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: CORE_XPT_INST_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPUWRAP_3375_BCM_MIPS_INST_MEMORY_STANDBY_ENABLE - Cpuwrap 3375 bcm mips inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: CPUWRAP_3375_BCM_MIPS_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: CPUWRAP_3375_BCM_MIPS_INST_MEMORY_STANDBY_ENABLE :: SCPU_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_INST_MEMORY_STANDBY_ENABLE_SCPU_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_INST_MEMORY_STANDBY_ENABLE_SCPU_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_INST_MEMORY_STANDBY_ENABLE_SCPU_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPUWRAP_3375_BCM_MIPS_INST_OBSERVE_CLOCK - Cpuwrap 3375 bcm mips inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: CPUWRAP_3375_BCM_MIPS_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: CPUWRAP_3375_BCM_MIPS_INST_OBSERVE_CLOCK :: SCPU_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_INST_OBSERVE_CLOCK_SCPU_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_INST_OBSERVE_CLOCK_SCPU_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_INST_OBSERVE_CLOCK_SCPU_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CPUWRAP_3375_BCM_MIPS_INST_OBSERVE_CLOCK :: SCPU_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_INST_OBSERVE_CLOCK_SCPU_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_INST_OBSERVE_CLOCK_SCPU_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_INST_OBSERVE_CLOCK_SCPU_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CPUWRAP_3375_BCM_MIPS_INST_OBSERVE_CLOCK :: SCPU_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_INST_OBSERVE_CLOCK_SCPU_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_INST_OBSERVE_CLOCK_SCPU_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CPUWRAP_3375_BCM_MIPS_INST_OBSERVE_CLOCK_SCPU_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE - Disable DUAL_GENET_TOP_DUAL_RGMII_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: reserved0 [31:09] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_reserved0_SHIFT 9
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET_PLL_CLOCK [08:08] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_PLL_CLOCK_MASK 0x00000100
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_PLL_CLOCK_SHIFT 8
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_PLL_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK [07:07] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_MASK 0x00000080
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_SHIFT 7
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_PM_CLOCK [06:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_MASK 0x00000040
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_SHIFT 6
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_FAST_CLOCK [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_ALWAYSON_CLOCK [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_ALWAYSON_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_ALWAYSON_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_ALWAYSON_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_FAST_CLOCK [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_ALWAYSON_CLOCK [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_ALWAYSON_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_ALWAYSON_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_ALWAYSON_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:09] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 9
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET_PLL_CLOCK_STATUS [08:08] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET_PLL_CLOCK_STATUS_MASK 0x00000100
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET_PLL_CLOCK_STATUS_SHIFT 8
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK_STATUS [07:07] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_STATUS_MASK 0x00000080
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_STATUS_SHIFT 7
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_SYSTEM_PM_CLOCK_STATUS [06:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_PM_CLOCK_STATUS_MASK 0x00000040
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_PM_CLOCK_STATUS_SHIFT 6
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_SYSTEM_FAST_CLOCK_STATUS [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_FAST_CLOCK_STATUS_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_FAST_CLOCK_STATUS_SHIFT 5
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_ALWAYSON_CLOCK_STATUS [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_ALWAYSON_CLOCK_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_ALWAYSON_CLOCK_STATUS_SHIFT 4
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS_SHIFT 3
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS_SHIFT 2
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_ALWAYSON_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_ALWAYSON_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE - Dual genet top dual rgmii inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 - Dual genet top dual rgmii inst clock enable genet0
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: reserved0 [31:09] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_reserved0_SHIFT 9
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0 [08:08] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_MASK 0x00000100
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_SHIFT 8
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0 [07:07] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_MASK 0x00000080
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_SHIFT 7
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_SCB_CLOCK_ENABLE_GENET0 [06:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_SCB_CLOCK_ENABLE_GENET0_MASK 0x00000040
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_SCB_CLOCK_ENABLE_GENET0_SHIFT 6
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_SCB_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_L2INTR_CLOCK_ENABLE_GENET0 [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_L2INTR_CLOCK_ENABLE_GENET0_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_L2INTR_CLOCK_ENABLE_GENET0_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_L2INTR_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_HFB_CLOCK_ENABLE_GENET0 [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_HFB_CLOCK_ENABLE_GENET0_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_HFB_CLOCK_ENABLE_GENET0_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_HFB_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_GMII_CLOCK_ENABLE_GENET0 [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GMII_CLOCK_ENABLE_GENET0_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GMII_CLOCK_ENABLE_GENET0_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GMII_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_EEE_CLOCK_ENABLE_GENET0 [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_EEE_CLOCK_ENABLE_GENET0_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_EEE_CLOCK_ENABLE_GENET0_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_EEE_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_CLK_250_CLOCK_ENABLE_GENET0 [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_CLK_250_CLOCK_ENABLE_GENET0_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_CLK_250_CLOCK_ENABLE_GENET0_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_CLK_250_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_108_CLOCK_ENABLE_GENET0 [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_108_CLOCK_ENABLE_GENET0_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_108_CLOCK_ENABLE_GENET0_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_108_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: reserved0 [31:09] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_reserved0_SHIFT 9
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_STATUS [08:08] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000100
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_STATUS_SHIFT 8
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_STATUS [07:07] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000080
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_STATUS_SHIFT 7
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_SCB_CLOCK_ENABLE_GENET0_STATUS [06:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_SCB_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000040
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_SCB_CLOCK_ENABLE_GENET0_STATUS_SHIFT 6
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_L2INTR_CLOCK_ENABLE_GENET0_STATUS [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_L2INTR_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_L2INTR_CLOCK_ENABLE_GENET0_STATUS_SHIFT 5
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_HFB_CLOCK_ENABLE_GENET0_STATUS [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_HFB_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_HFB_CLOCK_ENABLE_GENET0_STATUS_SHIFT 4
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_GMII_CLOCK_ENABLE_GENET0_STATUS [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_GMII_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_GMII_CLOCK_ENABLE_GENET0_STATUS_SHIFT 3
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_EEE_CLOCK_ENABLE_GENET0_STATUS [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_EEE_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_EEE_CLOCK_ENABLE_GENET0_STATUS_SHIFT 2
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_CLK_250_CLOCK_ENABLE_GENET0_STATUS [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_CLK_250_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_CLK_250_CLOCK_ENABLE_GENET0_STATUS_SHIFT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_108_CLOCK_ENABLE_GENET0_STATUS [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_108_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_108_CLOCK_ENABLE_GENET0_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 - Dual genet top dual rgmii inst clock enable genet1
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: reserved0 [31:09] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_reserved0_SHIFT 9
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1 [08:08] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_MASK 0x00000100
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_SHIFT 8
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1 [07:07] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_MASK 0x00000080
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_SHIFT 7
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_SCB_CLOCK_ENABLE_GENET1 [06:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_SCB_CLOCK_ENABLE_GENET1_MASK 0x00000040
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_SCB_CLOCK_ENABLE_GENET1_SHIFT 6
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_SCB_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_L2INTR_CLOCK_ENABLE_GENET1 [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_L2INTR_CLOCK_ENABLE_GENET1_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_L2INTR_CLOCK_ENABLE_GENET1_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_L2INTR_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_HFB_CLOCK_ENABLE_GENET1 [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_HFB_CLOCK_ENABLE_GENET1_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_HFB_CLOCK_ENABLE_GENET1_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_HFB_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_GMII_CLOCK_ENABLE_GENET1 [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GMII_CLOCK_ENABLE_GENET1_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GMII_CLOCK_ENABLE_GENET1_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GMII_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_EEE_CLOCK_ENABLE_GENET1 [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_EEE_CLOCK_ENABLE_GENET1_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_EEE_CLOCK_ENABLE_GENET1_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_EEE_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_CLK_250_CLOCK_ENABLE_GENET1 [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_CLK_250_CLOCK_ENABLE_GENET1_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_CLK_250_CLOCK_ENABLE_GENET1_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_CLK_250_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_108_CLOCK_ENABLE_GENET1 [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_108_CLOCK_ENABLE_GENET1_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_108_CLOCK_ENABLE_GENET1_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_108_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: reserved0 [31:09] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_reserved0_SHIFT 9
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_STATUS [08:08] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000100
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_STATUS_SHIFT 8
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_STATUS [07:07] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000080
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_STATUS_SHIFT 7
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_SCB_CLOCK_ENABLE_GENET1_STATUS [06:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_SCB_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000040
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_SCB_CLOCK_ENABLE_GENET1_STATUS_SHIFT 6
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_L2INTR_CLOCK_ENABLE_GENET1_STATUS [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_L2INTR_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_L2INTR_CLOCK_ENABLE_GENET1_STATUS_SHIFT 5
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_HFB_CLOCK_ENABLE_GENET1_STATUS [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_HFB_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_HFB_CLOCK_ENABLE_GENET1_STATUS_SHIFT 4
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_GMII_CLOCK_ENABLE_GENET1_STATUS [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_GMII_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_GMII_CLOCK_ENABLE_GENET1_STATUS_SHIFT 3
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_EEE_CLOCK_ENABLE_GENET1_STATUS [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_EEE_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_EEE_CLOCK_ENABLE_GENET1_STATUS_SHIFT 2
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_CLK_250_CLOCK_ENABLE_GENET1_STATUS [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_CLK_250_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_CLK_250_CLOCK_ENABLE_GENET1_STATUS_SHIFT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_108_CLOCK_ENABLE_GENET1_STATUS [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_108_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_108_CLOCK_ENABLE_GENET1_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS :: GENET_SCB_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS_GENET_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_STATUS_GENET_SCB_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0 - Dual genet top dual rgmii inst clock select genet0
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0 :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_reserved0_SHIFT 2
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0 :: GENET0_GMII_CLOCK_SELECT_GENET0 [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_GMII_CLOCK_SELECT_GENET0_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_GMII_CLOCK_SELECT_GENET0_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_GMII_CLOCK_SELECT_GENET0_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0 :: GENET0_CLOCK_SELECT_GENET0 [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_CLOCK_SELECT_GENET0_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_CLOCK_SELECT_GENET0_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_CLOCK_SELECT_GENET0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1 - Dual genet top dual rgmii inst clock select genet1
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1 :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_reserved0_SHIFT 2
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1 :: GENET1_GMII_CLOCK_SELECT_GENET1 [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_GMII_CLOCK_SELECT_GENET1_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_GMII_CLOCK_SELECT_GENET1_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_GMII_CLOCK_SELECT_GENET1_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1 :: GENET1_CLOCK_SELECT_GENET1 [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_CLOCK_SELECT_GENET1_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_CLOCK_SELECT_GENET1_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_CLOCK_SELECT_GENET1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK - Dual genet top dual rgmii inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HR_INST_CLOCK_DISABLE - Disable DVP_HR_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE :: DISABLE_DVPHR_ALWAYSON_CLOCK [00:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HR_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE_STATUS :: DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DVP_HR_INST_CLOCK_ENABLE - Dvp hr inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_reserved0_MASK        0xffffffe0
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_reserved0_SHIFT       5
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_ALTERNATE_216_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE_216_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_ALTERNATE2_108_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE2_108_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE2_108_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE2_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_324_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_324_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_324_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_324_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DVP_HR_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_ALTERNATE_216_CLOCK_ENABLE_STATUS [04:04] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_ALTERNATE_216_CLOCK_ENABLE_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_ALTERNATE_216_CLOCK_ENABLE_STATUS_SHIFT 4
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_ALTERNATE2_108_CLOCK_ENABLE_STATUS [03:03] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_ALTERNATE2_108_CLOCK_ENABLE_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_ALTERNATE2_108_CLOCK_ENABLE_STATUS_SHIFT 3
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_324_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_324_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_324_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_216_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_216_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DVP_HR_INST_MEMORY_STANDBY_ENABLE - Dvp hr inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: DVP_HR_INST_MEMORY_STANDBY_ENABLE :: DVPHR_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_DVPHR_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_DVPHR_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_DVPHR_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HR_INST_OBSERVE_CLOCK - Dvp hr inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HR_INST_POWER_SWITCH_MEMORY - Dvp hr inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: DVP_HR_INST_POWER_SWITCH_MEMORY :: DVPHR_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_DVPHR_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_DVPHR_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_DVPHR_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_INST_CLOCK_DISABLE - Disable DVP_HT_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE_STATUS :: DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DVP_HT_INST_CLOCK_ENABLE - Dvp ht inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffff8
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_SHIFT       3
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_ALTERNATE_216_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DVP_HT_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_ALTERNATE_216_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_ALTERNATE_216_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_ALTERNATE_216_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_216_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_216_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DVP_HT_INST_ENABLE - Dvp ht inst enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE_reserved0_SHIFT             2
+
+/* CLKGEN :: DVP_HT_INST_ENABLE :: DVPHT_CLK_VEC_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE_DVPHT_CLK_VEC_ENABLE_MASK   0x00000002
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE_DVPHT_CLK_VEC_ENABLE_SHIFT  1
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE_DVPHT_CLK_VEC_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_INST_ENABLE :: DVPHT_CLK_MAX_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE_DVPHT_CLK_MAX_ENABLE_MASK   0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE_DVPHT_CLK_MAX_ENABLE_SHIFT  0
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE_DVPHT_CLK_MAX_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DVP_HT_INST_MEMORY_STANDBY_ENABLE - Dvp ht inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: DVP_HT_INST_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_INST_OBSERVE_CLOCK - Dvp ht inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_INST_POWER_SWITCH_MEMORY - Dvp ht inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: DVP_HT_INST_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE_M2MC0 - Graphics inst clock enable m2mc0
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0 :: reserved0 [31:03] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_reserved0_SHIFT 3
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0 :: GFX_M2MC0_SCB_CLOCK_ENABLE_M2MC0 [02:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_SCB_CLOCK_ENABLE_M2MC0_MASK 0x00000004
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_SCB_CLOCK_ENABLE_M2MC0_SHIFT 2
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_SCB_CLOCK_ENABLE_M2MC0_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0 :: GFX_M2MC0_CLOCK_ENABLE_M2MC0 [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_CLOCK_ENABLE_M2MC0_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_CLOCK_ENABLE_M2MC0_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_CLOCK_ENABLE_M2MC0_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0 :: GFX_M2MC0_108_CLOCK_ENABLE_M2MC0 [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_108_CLOCK_ENABLE_M2MC0_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_108_CLOCK_ENABLE_M2MC0_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_108_CLOCK_ENABLE_M2MC0_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS :: GFX_M2MC0_SCB_CLOCK_ENABLE_M2MC0_STATUS [02:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_GFX_M2MC0_SCB_CLOCK_ENABLE_M2MC0_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_GFX_M2MC0_SCB_CLOCK_ENABLE_M2MC0_STATUS_SHIFT 2
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS :: GFX_M2MC0_CLOCK_ENABLE_M2MC0_STATUS [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_GFX_M2MC0_CLOCK_ENABLE_M2MC0_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_GFX_M2MC0_CLOCK_ENABLE_M2MC0_STATUS_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS :: GFX_M2MC0_108_CLOCK_ENABLE_M2MC0_STATUS [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_GFX_M2MC0_108_CLOCK_ENABLE_M2MC0_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_GFX_M2MC0_108_CLOCK_ENABLE_M2MC0_STATUS_SHIFT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE_M2MC1 - Graphics inst clock enable m2mc1
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1 :: reserved0 [31:03] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_reserved0_SHIFT 3
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1 :: GFX_M2MC1_SCB_CLOCK_ENABLE_M2MC1 [02:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_SCB_CLOCK_ENABLE_M2MC1_MASK 0x00000004
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_SCB_CLOCK_ENABLE_M2MC1_SHIFT 2
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_SCB_CLOCK_ENABLE_M2MC1_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1 :: GFX_M2MC1_CLOCK_ENABLE_M2MC1 [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_CLOCK_ENABLE_M2MC1_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_CLOCK_ENABLE_M2MC1_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_CLOCK_ENABLE_M2MC1_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1 :: GFX_M2MC1_108_CLOCK_ENABLE_M2MC1 [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_108_CLOCK_ENABLE_M2MC1_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_108_CLOCK_ENABLE_M2MC1_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_108_CLOCK_ENABLE_M2MC1_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS :: GFX_M2MC1_SCB_CLOCK_ENABLE_M2MC1_STATUS [02:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_M2MC1_SCB_CLOCK_ENABLE_M2MC1_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_M2MC1_SCB_CLOCK_ENABLE_M2MC1_STATUS_SHIFT 2
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS :: GFX_M2MC1_CLOCK_ENABLE_M2MC1_STATUS [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_M2MC1_CLOCK_ENABLE_M2MC1_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_M2MC1_CLOCK_ENABLE_M2MC1_STATUS_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS :: GFX_M2MC1_108_CLOCK_ENABLE_M2MC1_STATUS [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_M2MC1_108_CLOCK_ENABLE_M2MC1_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_M2MC1_108_CLOCK_ENABLE_M2MC1_STATUS_SHIFT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC0 - Graphics inst memory standby enable m2mc0
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC0 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC0_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC0_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC0 :: GFX_M2MC0_MEMORY_STANDBY_ENABLE_M2MC0 [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC0_GFX_M2MC0_MEMORY_STANDBY_ENABLE_M2MC0_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC0_GFX_M2MC0_MEMORY_STANDBY_ENABLE_M2MC0_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC0_GFX_M2MC0_MEMORY_STANDBY_ENABLE_M2MC0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC1 - Graphics inst memory standby enable m2mc1
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC1 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC1_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC1_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC1 :: GFX_M2MC1_MEMORY_STANDBY_ENABLE_M2MC1 [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC1_GFX_M2MC1_MEMORY_STANDBY_ENABLE_M2MC1_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC1_GFX_M2MC1_MEMORY_STANDBY_ENABLE_M2MC1_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_M2MC1_GFX_M2MC1_MEMORY_STANDBY_ENABLE_M2MC1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_INST_OBSERVE_CLOCK - Graphics inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC0 - Graphics inst power switch memory m2mc0
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC0 :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC0_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC0_reserved0_SHIFT 2
+
+/* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC0 :: GFX_M2MC0_POWER_SWITCH_MEMORY_M2MC0 [01:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC0_GFX_M2MC0_POWER_SWITCH_MEMORY_M2MC0_MASK 0x00000003
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC0_GFX_M2MC0_POWER_SWITCH_MEMORY_M2MC0_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC0_GFX_M2MC0_POWER_SWITCH_MEMORY_M2MC0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC1 - Graphics inst power switch memory m2mc1
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC1 :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC1_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC1_reserved0_SHIFT 2
+
+/* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC1 :: GFX_M2MC1_POWER_SWITCH_MEMORY_M2MC1 [01:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC1_GFX_M2MC1_POWER_SWITCH_MEMORY_M2MC1_MASK 0x00000003
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC1_GFX_M2MC1_POWER_SWITCH_MEMORY_M2MC1_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_M2MC1_GFX_M2MC1_POWER_SWITCH_MEMORY_M2MC1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_INST_CLOCK_DISABLE - Disable HIF_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_SHIFT         5
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_EBI_CLOCK [04:04] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [03:03] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_EMMC_CLOCK [02:02] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CARD_CLOCK [01:01] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_ALWAYSON_CLOCK [00:00] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:05] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_reserved0_MASK   0xffffffe0
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT  5
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_EBI_CLOCK_STATUS [04:04] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_EBI_CLOCK_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_EBI_CLOCK_STATUS_SHIFT 4
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SPI_CLOCK_STATUS [03:03] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_SHIFT 3
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS [02:02] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS_SHIFT 2
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_CARD_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_ALWAYSON_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_ALWAYSON_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *HIF_INST_MEMORY_STANDBY_ENABLE - Hif inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: HIF_INST_MEMORY_STANDBY_ENABLE :: HIF_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_INST_OBSERVE_CLOCK - Hif inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH - Hif inst pll hif ssc mode control high
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH :: reserved0 [31:20] */
+#define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xfff00000
+#define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 20
+
+/* CLKGEN :: HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH :: SSC_STEP_PLL_HIF_SSC_MODE_CONTROL_HIGH [19:04] */
+#define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH_SSC_STEP_PLL_HIF_SSC_MODE_CONTROL_HIGH_MASK 0x000ffff0
+#define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH_SSC_STEP_PLL_HIF_SSC_MODE_CONTROL_HIGH_SHIFT 4
+#define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH_SSC_STEP_PLL_HIF_SSC_MODE_CONTROL_HIGH_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH :: SSC_CLK_DIV_PLL_HIF_SSC_MODE_CONTROL_HIGH [03:00] */
+#define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH_SSC_CLK_DIV_PLL_HIF_SSC_MODE_CONTROL_HIGH_MASK 0x0000000f
+#define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH_SSC_CLK_DIV_PLL_HIF_SSC_MODE_CONTROL_HIGH_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_HIGH_SSC_CLK_DIV_PLL_HIF_SSC_MODE_CONTROL_HIGH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW - Hif inst pll hif ssc mode control low
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW :: reserved0 [31:21] */
+#define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xffe00000
+#define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 21
+
+/* CLKGEN :: HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW :: SSC_MODE_PLL_HIF_SSC_MODE_CONTROL_LOW [20:20] */
+#define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW_SSC_MODE_PLL_HIF_SSC_MODE_CONTROL_LOW_MASK 0x00100000
+#define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW_SSC_MODE_PLL_HIF_SSC_MODE_CONTROL_LOW_SHIFT 20
+#define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW_SSC_MODE_PLL_HIF_SSC_MODE_CONTROL_LOW_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW :: SSC_LIMIT_PLL_HIF_SSC_MODE_CONTROL_LOW [19:00] */
+#define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW_SSC_LIMIT_PLL_HIF_SSC_MODE_CONTROL_LOW_MASK 0x000fffff
+#define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW_SSC_LIMIT_PLL_HIF_SSC_MODE_CONTROL_LOW_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_PLL_HIF_SSC_MODE_CONTROL_LOW_SSC_LIMIT_PLL_HIF_SSC_MODE_CONTROL_LOW_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_INST_POWER_SWITCH_MEMORY - Hif inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: HIF_INST_POWER_SWITCH_MEMORY :: HIF_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
+ ***************************************************************************/
+/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:06] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK             0xffffffc0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT            6
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO2_REFERENCE_CLOCK [05:04] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_MASK 0x00000030
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [03:02] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x0000000c
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [01:00] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000003
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ITU656_0_MUX_SELECT - Mux selects for itu656_0 clocks
+ ***************************************************************************/
+/* CLKGEN :: ITU656_0_MUX_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_reserved0_MASK             0xfffffff8
+#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_reserved0_SHIFT            3
+
+/* CLKGEN :: ITU656_0_MUX_SELECT :: VEC_ITU656_0_CLOCK [02:01] */
+#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_MASK    0x00000006
+#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_SHIFT   1
+#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: ITU656_0_MUX_SELECT :: ENABLE_INVERT_VEC_ITU656_0_CLOCK [00:00] */
+#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ITU656_1_MUX_SELECT - Mux selects for itu656_1 clocks
+ ***************************************************************************/
+/* CLKGEN :: ITU656_1_MUX_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_ITU656_1_MUX_SELECT_reserved0_MASK             0xfffffff8
+#define BCHP_CLKGEN_ITU656_1_MUX_SELECT_reserved0_SHIFT            3
+
+/* CLKGEN :: ITU656_1_MUX_SELECT :: VEC_ITU656_1_CLOCK [02:01] */
+#define BCHP_CLKGEN_ITU656_1_MUX_SELECT_VEC_ITU656_1_CLOCK_MASK    0x00000006
+#define BCHP_CLKGEN_ITU656_1_MUX_SELECT_VEC_ITU656_1_CLOCK_SHIFT   1
+#define BCHP_CLKGEN_ITU656_1_MUX_SELECT_VEC_ITU656_1_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: ITU656_1_MUX_SELECT :: ENABLE_INVERT_VEC_ITU656_1_CLOCK [00:00] */
+#define BCHP_CLKGEN_ITU656_1_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_1_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_ITU656_1_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_1_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_ITU656_1_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_1_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_32_0_INST_CLOCK_ENABLE - Memsys 32 0 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_reserved0_SHIFT  2
+
+/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: DDR0_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: DDR0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
+
+/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS :: DDR0_SCB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_DDR0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_DDR0_SCB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS :: DDR0_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_DDR0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_DDR0_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE - Memsys 32 0 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE :: DDR0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE_DDR0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE_DDR0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE_DDR0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_32_0_INST_OBSERVE_CLOCK - Memsys 32 0 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: DDR0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: DDR0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: DDR0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_32_0_INST_POWER_SWITCH_MEMORY - Memsys 32 0 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_0_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: MEMSYS_32_0_INST_POWER_SWITCH_MEMORY :: DDR0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY_DDR0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY_DDR0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY_DDR0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_32_0_INST_STATUS - Memsys 32 0 inst status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_0_INST_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS_reserved0_SHIFT        1
+
+/* CLKGEN :: MEMSYS_32_0_INST_STATUS :: DDR0_PLL_LOCKED_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS_DDR0_PLL_LOCKED_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS_DDR0_PLL_LOCKED_STATUS_SHIFT 0
+
+/***************************************************************************
+ *MEMSYS_32_1_INST_CLOCK_ENABLE - Memsys 32 1 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_reserved0_SHIFT  2
+
+/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE :: DDR1_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE :: DDR1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
+
+/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS :: DDR1_SCB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_DDR1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_DDR1_SCB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS :: DDR1_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_DDR1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_DDR1_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE - Memsys 32 1 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE :: DDR1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_32_1_INST_OBSERVE_CLOCK - Memsys 32 1 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: DDR1_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: DDR1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: DDR1_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_32_1_INST_POWER_SWITCH_MEMORY - Memsys 32 1 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_1_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: MEMSYS_32_1_INST_POWER_SWITCH_MEMORY :: DDR1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_32_1_INST_STATUS - Memsys 32 1 inst status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_1_INST_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_STATUS_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_STATUS_reserved0_SHIFT        1
+
+/* CLKGEN :: MEMSYS_32_1_INST_STATUS :: DDR1_PLL_LOCKED_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_STATUS_DDR1_PLL_LOCKED_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_STATUS_DDR1_PLL_LOCKED_STATUS_SHIFT 0
+
+/***************************************************************************
+ *MOCAMAC_TOP_INST_CLOCK_ENABLE - Mocamac top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  2
+
+/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCA_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
+
+/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCA_SCB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCA_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCA_SCB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCA_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCA_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCA_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *MOCAMAC_TOP_INST_MEMORY_STANDBY_ENABLE - Mocamac top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MOCAMAC_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MOCAMAC_TOP_INST_MEMORY_STANDBY_ENABLE :: MOCA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MOCAMAC_TOP_INST_OBSERVE_CLOCK - Mocamac top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCA_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCA_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MOCAPHY_TOP_INST_CLOCK_ENABLE - Mocaphy top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE :: MOCA0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCA0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCA0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCA0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS :: MOCA0_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCA0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCA0_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *MOCAPHY_TOP_INST_MEMORY_STANDBY_ENABLE - Mocaphy top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MOCAPHY_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MOCAPHY_TOP_INST_MEMORY_STANDBY_ENABLE :: MOCA0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MOCAPHY_TOP_INST_OBSERVE_CLOCK - Mocaphy top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCA0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCA0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCA0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCA0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCA0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCA0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCA0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCA0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCA0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCA0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCA0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCA0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLK27_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_MASK           0xfffffe00
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_SHIFT          9
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_MASK  0x00000100
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_MASK  0x000000fe
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK  0x00000001
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLOCK_DISABLE - Disable PAD's clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK               0xffffffe0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT              5
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_VCXO27_CLOCK [04:04] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_SC_CLOCK [03:03] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [02:02] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLKBT_CLOCK [01:01] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKBT_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKBT_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKBT_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: reserved0 [31:05] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_MASK        0xffffffe0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_SHIFT       5
+
+/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_VCXO27_CLOCK_STATUS [04:04] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_STATUS_SHIFT 4
+
+/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_SC_CLOCK_STATUS [03:03] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_SC_CLOCK_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_SC_CLOCK_STATUS_SHIFT 3
+
+/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_STATUS [02:02] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_STATUS_SHIFT 2
+
+/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CLKBT_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLKBT_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLKBT_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CLK27_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK27_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK27_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PAD_CODEC_MCLK_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_MASK      0xfffffe00
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_SHIFT     9
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_MUX_SELECT - Mux selects for Pad clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:05] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK                  0xffffffe0
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT                 5
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_VCXO27_CLOCK [04:02] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_MASK    0x0000001c
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_SHIFT   2
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_SC_CLOCK [01:01] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_MASK        0x00000002
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_SHIFT       1
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_DEFAULT     0x00000000
+
+/* CLKGEN :: PAD_MUX_SELECT :: ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_VCXO27_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_MASK          0xfffffe00
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_SHIFT         9
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET_STATUS - PLL_AUDIO0 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET_STATUS - PLL_AUDIO1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_RESET_STATUS - PLL_AUDIO2 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO2_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO2_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AVD1_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD1_RDB_MACRO_CTRL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_AVD1_RDB_MACRO_CTRL_reserved0_MASK         0xfffffff0
+#define BCHP_CLKGEN_PLL_AVD1_RDB_MACRO_CTRL_reserved0_SHIFT        4
+
+/* CLKGEN :: PLL_AVD1_RDB_MACRO_CTRL :: PLL_AVD1_OPTIONS_DISABLE_RDB_MACRO [03:03] */
+#define BCHP_CLKGEN_PLL_AVD1_RDB_MACRO_CTRL_PLL_AVD1_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
+#define BCHP_CLKGEN_PLL_AVD1_RDB_MACRO_CTRL_PLL_AVD1_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
+#define BCHP_CLKGEN_PLL_AVD1_RDB_MACRO_CTRL_PLL_AVD1_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD1_RDB_MACRO_CTRL :: OPTIONS [02:00] */
+#define BCHP_CLKGEN_PLL_AVD1_RDB_MACRO_CTRL_OPTIONS_MASK           0x00000007
+#define BCHP_CLKGEN_PLL_AVD1_RDB_MACRO_CTRL_OPTIONS_SHIFT          0
+#define BCHP_CLKGEN_PLL_AVD1_RDB_MACRO_CTRL_OPTIONS_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PLL_HIF_PLL_RESET_STATUS - PLL_HIF Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_HIF_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_HIF_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_HIF_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_MIPS_GLITCHLESS_SWITCH_REQUEST - PLL_MIPS Glitchless Clock Switching
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_reserved0_SHIFT 9
+
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: TRANSACTION_WAIT [08:01] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_DEFAULT 0x0000001f
+
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: PLL_BYPASS_REQUEST [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MIPS_GLITCHLESS_SWITCH_STATUS - PLL_MIPS Glitchless Switching
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_STATUS :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_reserved0_SHIFT 4
+
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_STATUS :: PLL_BYPASS_STATUS [03:00] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_MASK 0x0000000f
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_RESET_STATUS - PLL_MIPS Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_MIPS_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_RDB_MACRO_CTRL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_reserved0_MASK         0xfffffff0
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_reserved0_SHIFT        4
+
+/* CLKGEN :: PLL_MIPS_RDB_MACRO_CTRL :: PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO [03:03] */
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MIPS_RDB_MACRO_CTRL :: OPTIONS [02:00] */
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_OPTIONS_MASK           0x00000007
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_OPTIONS_SHIFT          0
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_OPTIONS_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_RESET_STATUS - PLL_MOCA Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_MOCA_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_reserved0_MASK         0xfffffff8
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_reserved0_SHIFT        3
+
+/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO [02:02] */
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000004
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_SHIFT 2
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: OPTIONS [01:00] */
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_MASK           0x00000003
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_SHIFT          0
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_RESET_STATUS - PLL_NETWORK Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_reserved0_SHIFT   2
+
+/* CLKGEN :: PLL_NETWORK_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_NETWORK_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_RESET_STATUS - PLL_RAAGA Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_SHIFT     2
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_RAAGA_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_MASK        0xfffffff0
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_SHIFT       4
+
+/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO [03:03] */
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: OPTIONS [02:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_MASK          0x00000007
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_SHIFT         0
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_RESET_STATUS - PLL_SC0 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SC0_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: reserved0 [31:05] */
+#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_reserved0_SHIFT         5
+
+/* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: PLL_SC0_OPTIONS_DISABLE_RDB_MACRO [04:04] */
+#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_SHIFT 4
+#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: OPTIONS [03:00] */
+#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_MASK            0x0000000f
+#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_SHIFT           0
+#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_RESET_STATUS - PLL_SC1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SC1_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: reserved0 [31:05] */
+#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_reserved0_SHIFT         5
+
+/* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: PLL_SC1_OPTIONS_DISABLE_RDB_MACRO [04:04] */
+#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_SHIFT 4
+#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: OPTIONS [03:00] */
+#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_MASK            0x0000000f
+#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_SHIFT           0
+#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_STRAP_OVERRIDE - Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_STRAP_OVERRIDE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_STRAP_OVERRIDE :: STRAP_HIFSPI_DISABLE [01:01] */
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_HIFSPI_DISABLE_MASK   0x00000002
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_HIFSPI_DISABLE_SHIFT  1
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_HIFSPI_DISABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_STRAP_OVERRIDE :: STRAP_FREQ_PLLMIPS_DISABLE [00:00] */
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_RESET_STATUS - PLL_VCXO0 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_reserved0_SHIFT     2
+
+/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_RESET_STATUS - PLL_VCXO1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_reserved0_SHIFT     2
+
+/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_RESET_STATUS - PLL_VCXO2 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_reserved0_SHIFT     2
+
+/* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PM_CLOCK_Async_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_Async_ALIVE_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_reserved0_SHIFT       1
+
+/* CLKGEN :: PM_CLOCK_Async_ALIVE_SEL :: CLOCK_Async_CG_XPT [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_MASK 0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_SHIFT 0
+#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:06] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xffffffc0
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               6
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys1_PLL [05:05] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys1_PLL_MASK              0x00000020
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys1_PLL_SHIFT             5
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys1_PLL_DEFAULT           0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys0_PLL [04:04] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_MASK              0x00000010
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_SHIFT             4
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_DEFAULT           0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_XPT [03:03] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_MASK                  0x00000008
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_SHIFT                 3
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_DEFAULT               0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [02:02] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK                 0x00000004
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT                2
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT              0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_MIPS [01:01] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_MASK                 0x00000002
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_SHIFT                1
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_DEFAULT              0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_AVD1 [00:00] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD1_MASK                 0x00000001
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD1_SHIFT                0
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD1_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PM_PLL_LDO_POWERUP - Power management LDO PLL
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_MASK              0xfffffff0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_SHIFT             4
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_RAAGA [03:03] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_MASK    0x00000008
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_SHIFT   3
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_DEFAULT 0x00000001
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_NETWORK [02:02] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_NETWORK_MASK  0x00000004
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_NETWORK_SHIFT 2
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_NETWORK_DEFAULT 0x00000001
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_MOCA [01:01] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_MASK     0x00000002
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_SHIFT    1
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_DEFAULT  0x00000001
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_HIF [00:00] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_HIF_MASK      0x00000001
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_HIF_SHIFT     0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_HIF_DEFAULT   0x00000001
+
+/***************************************************************************
+ *PM_PLL_LDO_POWERUP_SM - Power management LDO PLL state machine
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: reserved0 [31:27] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_MASK           0xf8000000
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_SHIFT          27
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_POWERUP_WAIT_TIME [26:14] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_MASK 0x07ffc000
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_SHIFT 14
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_DEFAULT 0x00001518
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_CLK_STOP_WAIT_TIME [13:01] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_MASK 0x00003ffe
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_SHIFT 1
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_DEFAULT 0x000000c8
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: GISB_OVERRIDE_SM [00:00] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_MASK    0x00000001
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_SHIFT   0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE - Raaga dsp top 0 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_reserved0_SHIFT 3
+
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_DSP_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_DSP_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_DSP_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_DSP_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_SCB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_DSP_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_DSP_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_DSP_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_0_INST_MEMORY_STANDBY_ENABLE - Raaga dsp top 0 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_MEMORY_STANDBY_ENABLE :: RAAGA0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_MEMORY_STANDBY_ENABLE_RAAGA0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_MEMORY_STANDBY_ENABLE_RAAGA0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_MEMORY_STANDBY_ENABLE_RAAGA0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK - Raaga dsp top 0 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK :: RAAGA0_ENABLE_OBSERVE_CLOCK [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_OBSERVE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK :: RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_0_INST_POWER_SWITCH_MEMORY - Raaga dsp top 0 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_POWER_SWITCH_MEMORY :: RAAGA0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_POWER_SWITCH_MEMORY_RAAGA0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_POWER_SWITCH_MEMORY_RAAGA0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_POWER_SWITCH_MEMORY_RAAGA0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE - Raaga dsp top 1 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_reserved0_SHIFT 3
+
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_DSP_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_DSP_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_DSP_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_DSP_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_SCB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_DSP_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_DSP_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_DSP_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_1_INST_MEMORY_STANDBY_ENABLE - Raaga dsp top 1 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_MEMORY_STANDBY_ENABLE :: RAAGA1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_MEMORY_STANDBY_ENABLE_RAAGA1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_MEMORY_STANDBY_ENABLE_RAAGA1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_MEMORY_STANDBY_ENABLE_RAAGA1_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK - Raaga dsp top 1 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK :: RAAGA1_ENABLE_OBSERVE_CLOCK [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_OBSERVE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK :: RAAGA1_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_1_INST_POWER_SWITCH_MEMORY - Raaga dsp top 1 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_POWER_SWITCH_MEMORY :: RAAGA1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_POWER_SWITCH_MEMORY_RAAGA1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_POWER_SWITCH_MEMORY_RAAGA1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_POWER_SWITCH_MEMORY_RAAGA1_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_INST_CLOCK_DISABLE - Disable SATA3_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_reserved0_MASK    0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT   1
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE :: DISABLE_SATA3_AT_SPEED_SCAN_CLOCK [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *SATA3_TOP_INST_CLOCK_ENABLE - Sata3 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT    2
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SATA3_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: SATA3_SCB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_SCB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: SATA3_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *SATA3_TOP_INST_CLOCK_SELECT - Sata3 top inst clock select
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_SHIFT    1
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: SATA3_REF_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SATA3_TOP_INST_MEMORY_STANDBY_ENABLE - Sata3 top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SATA3_TOP_INST_MEMORY_STANDBY_ENABLE :: SATA3_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SATA3_TOP_INST_OBSERVE_CLOCK - Sata3 top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_MASK    0xffffffc0
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT   6
+
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_INST_POWER_SWITCH_MEMORY - Sata3 top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SATA3_TOP_INST_POWER_SWITCH_MEMORY :: SATA3_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SECTOP_INST_CLOCK_ENABLE_M2MDMA - Sectop inst clock enable m2mdma
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_reserved0_SHIFT 1
+
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA :: M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SECTOP_INST_CLOCK_ENABLE_M2MDMA_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA_STATUS :: M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_STATUS [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_STATUS_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_STATUS_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_STATUS_SHIFT 0
+
+/***************************************************************************
+ *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
+ ***************************************************************************/
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT           2
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [01:01] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK            0x00000002
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT           1
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [00:00] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK            0x00000001
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT           0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *SPARE - Spares
+ ***************************************************************************/
+/* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK                     0xfffff000
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT                    12
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT                  0x00000000
+
+/* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK                    0x00000fff
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT                   0
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *SVD0_TOP_INST_CLOCK_ENABLE - Svd0 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffff0
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     4
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD0_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD0_CPU_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CPU_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CPU_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CPU_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD0_CORE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CORE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CORE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SVD0_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE_STATUS :: SVD0_SCB_CLOCK_ENABLE_STATUS [03:03] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD0_SCB_CLOCK_ENABLE_STATUS_SHIFT 3
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE_STATUS :: SVD0_CPU_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD0_CPU_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD0_CPU_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE_STATUS :: SVD0_CORE_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD0_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD0_CORE_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE_STATUS :: SVD0_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_STATUS_SVD0_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *SVD0_TOP_INST_MEMORY_STANDBY_ENABLE - Svd0 top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SVD0_TOP_INST_MEMORY_STANDBY_ENABLE :: SVD0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SVD0_TOP_INST_POWER_SWITCH_MEMORY - Svd0 top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SVD0_TOP_INST_POWER_SWITCH_MEMORY :: SVD0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_AON_INST_OBSERVE_CLOCK - Sys aon inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_INST_CLOCK_DISABLE - Disable SYS_CTRL_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffff0
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_SHIFT    4
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [03:03] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK [02:02] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:04] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 4
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSCTRL_UPG_CLOCK_STATUS [03:03] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_SHIFT 3
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK_STATUS [02:02] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_STATUS_SHIFT 2
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SC1_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SC0_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *SYS_CTRL_INST_MEMORY_STANDBY_ENABLE - Sys ctrl inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SYS_CTRL_INST_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_INST_OBSERVE_CLOCK - Sys ctrl inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_INST_POWER_SWITCH_MEMORY - Sys ctrl inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SYS_CTRL_INST_POWER_SWITCH_MEMORY :: SYS_CTRL_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TESTPORT - Special Testport Controls
+ ***************************************************************************/
+/* CLKGEN :: TESTPORT :: reserved0 [31:04] */
+#define BCHP_CLKGEN_TESTPORT_reserved0_MASK                        0xfffffff0
+#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT                       4
+
+/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [03:00] */
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK           0x0000000f
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT          0
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *UHFR_TOP_INST_CLOCK_DISABLE - Disable UHFR_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1
+
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE :: DISABLE_UHFR_ALWAYSON_CLOCK [00:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UHFR_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_UHFR_ALWAYSON_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UHFR_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UHFR_ALWAYSON_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *UHFR_TOP_INST_CLOCK_ENABLE - Uhfr top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE :: UHFR_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *UHFR_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE_STATUS :: UHFR_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_STATUS_UHFR_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_STATUS_UHFR_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *UHFR_TOP_INST_MEMORY_STANDBY_ENABLE - Uhfr top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: UHFR_TOP_INST_MEMORY_STANDBY_ENABLE :: UHFR_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UHFR_TOP_INST_OBSERVE_CLOCK - Uhfr top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UHFR_TOP_INST_POWER_SWITCH_MEMORY - Uhfr top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: UHFR_TOP_INST_POWER_SWITCH_MEMORY :: UHFR_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB0_INST_CLOCK_DISABLE - Disable USB0_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_reserved0_SHIFT        2
+
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: DISABLE_USB0_FREERUN_CLOCK [01:01] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: DISABLE_USB0_54_MDIO_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB0_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_STATUS_reserved0_MASK  0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
+
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB0_FREERUN_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_FREERUN_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_FREERUN_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB0_54_MDIO_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_54_MDIO_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_54_MDIO_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *USB0_INST_CLOCK_ENABLE - Usb0 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: USB0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *USB0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT  2
+
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE_STATUS :: USB0_SCB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE_STATUS :: USB0_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_STATUS_USB0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_STATUS_USB0_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *USB0_INST_MEMORY_STANDBY_ENABLE - Usb0 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: USB0_INST_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB0_INST_OBSERVE_CLOCK - Usb0 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB0_INST_POWER_SWITCH_MEMORY - Usb0 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: USB0_INST_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB1_INST_CLOCK_DISABLE - Disable USB1_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_reserved0_SHIFT        2
+
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: DISABLE_USB1_FREERUN_CLOCK [01:01] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_FREERUN_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_FREERUN_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_FREERUN_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: DISABLE_USB1_54_MDIO_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB1_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_STATUS_reserved0_MASK  0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
+
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB1_FREERUN_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_STATUS_DISABLE_USB1_FREERUN_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_STATUS_DISABLE_USB1_FREERUN_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB1_54_MDIO_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_STATUS_DISABLE_USB1_54_MDIO_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_STATUS_DISABLE_USB1_54_MDIO_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *USB1_INST_CLOCK_ENABLE - Usb1 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: USB1_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: USB1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *USB1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT  2
+
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE_STATUS :: USB1_SCB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_STATUS_USB1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_STATUS_USB1_SCB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE_STATUS :: USB1_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_STATUS_USB1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_STATUS_USB1_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *USB1_INST_MEMORY_STANDBY_ENABLE - Usb1 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: USB1_INST_MEMORY_STANDBY_ENABLE :: USB1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB1_INST_OBSERVE_CLOCK - Usb1 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB1_INST_POWER_SWITCH_MEMORY - Usb1 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: USB1_INST_POWER_SWITCH_MEMORY :: USB1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *V3D_TOP_INST_CLOCK_ENABLE - V3d top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffff8
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      3
+
+/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_108_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_108_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_108_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: GFX_V3D_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *V3D_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_SCB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_108_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_108_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_108_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: GFX_V3D_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_GFX_V3D_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_GFX_V3D_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *V3D_TOP_INST_MEMORY_STANDBY_ENABLE - V3d top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: V3D_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: V3D_TOP_INST_MEMORY_STANDBY_ENABLE :: V3D_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE_V3D_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE_V3D_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE_V3D_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *V3D_TOP_INST_POWER_SWITCH_MEMORY - V3d top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: V3D_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: V3D_TOP_INST_POWER_SWITCH_MEMORY :: V3D_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY_V3D_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY_V3D_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY_V3D_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_DISABLE - Disable VEC_AIO_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_MASK  0xfffffff0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 4
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_ITU656_1_CLOCK [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_1_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_1_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_1_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_ITU656_0_CLOCK [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_AIO_CLEAN_216_CLOCK [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AIO_CLEAN_216_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AIO_CLEAN_216_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AIO_CLEAN_216_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 4
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_VEC_ITU656_1_CLOCK_STATUS [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_1_CLOCK_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_1_CLOCK_STATUS_SHIFT 3
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_VEC_ITU656_0_CLOCK_STATUS [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_0_CLOCK_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_0_CLOCK_STATUS_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_VEC_DACADC_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_AIO_CLEAN_216_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AIO_CLEAN_216_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AIO_CLEAN_216_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO - Vec aio top inst clock enable aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: reserved0 [31:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_SHIFT 3
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_108_CLOCK_ENABLE_AIO [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_108_CLOCK_ENABLE_AIO_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_108_CLOCK_ENABLE_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_108_CLOCK_ENABLE_AIO_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_STATUS [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_STATUS_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_STATUS [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_STATUS_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: AIO_108_CLOCK_ENABLE_AIO_STATUS [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_108_CLOCK_ENABLE_AIO_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_108_CLOCK_ENABLE_AIO_STATUS_SHIFT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC - Vec aio top inst clock enable vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_SHIFT 6
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_SCB_CLOCK_ENABLE_VEC [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_ALTERNATE_216_CLOCK_ENABLE_VEC [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_ALTERNATE2_108_CLOCK_ENABLE_VEC [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE2_108_CLOCK_ENABLE_VEC_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE2_108_CLOCK_ENABLE_VEC_SHIFT 3
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE2_108_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_324_CLOCK_ENABLE_VEC [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_324_CLOCK_ENABLE_VEC_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_324_CLOCK_ENABLE_VEC_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_324_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_216_CLOCK_ENABLE_VEC [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: QDAC_216_CLOCK_ENABLE_VEC [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_216_CLOCK_ENABLE_VEC_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_216_CLOCK_ENABLE_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_216_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_reserved0_SHIFT 6
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_SCB_CLOCK_ENABLE_VEC_STATUS [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_SCB_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_SCB_CLOCK_ENABLE_VEC_STATUS_SHIFT 5
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_STATUS [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_STATUS_SHIFT 4
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_ALTERNATE2_108_CLOCK_ENABLE_VEC_STATUS [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_ALTERNATE2_108_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_ALTERNATE2_108_CLOCK_ENABLE_VEC_STATUS_SHIFT 3
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_324_CLOCK_ENABLE_VEC_STATUS [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_324_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_324_CLOCK_ENABLE_VEC_STATUS_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_216_CLOCK_ENABLE_VEC_STATUS [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_216_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_216_CLOCK_ENABLE_VEC_STATUS_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: QDAC_216_CLOCK_ENABLE_VEC_STATUS [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_QDAC_216_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_QDAC_216_CLOCK_ENABLE_VEC_STATUS_SHIFT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO - Vec aio top inst memory standby enable aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO :: AIO_MEMORY_STANDBY_ENABLE_AIO [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC - Vec aio top inst memory standby enable vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC :: VEC_MEMORY_STANDBY_ENABLE_VEC [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_OBSERVE_CLOCK - Vec aio top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO - Vec aio top inst power switch memory aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO :: AIO_POWER_SWITCH_MEMORY_AIO [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC - Vec aio top inst power switch memory vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC :: VEC_POWER_SWITCH_MEMORY_VEC [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VICE2_1_INST_CLOCK_ENABLE - Vice2 1 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffff0
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_reserved0_SHIFT      4
+
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE1_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE1_CORE_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_CORE_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_CORE_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE1_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE1_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VICE2_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
+
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE1_SCB_CLOCK_ENABLE_STATUS [03:03] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE1_SCB_CLOCK_ENABLE_STATUS_SHIFT 3
+
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE1_CORE_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE1_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE1_CORE_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE1_216_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE1_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE1_216_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE1_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE1_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *VICE2_1_INST_MEMORY_STANDBY_ENABLE - Vice2 1 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: VICE2_1_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VICE2_1_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VICE2_1_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: VICE2_1_INST_MEMORY_STANDBY_ENABLE :: VICE1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_VICE2_1_INST_MEMORY_STANDBY_ENABLE_VICE1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VICE2_1_INST_MEMORY_STANDBY_ENABLE_VICE1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VICE2_1_INST_MEMORY_STANDBY_ENABLE_VICE1_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VICE2_1_INST_POWER_SWITCH_MEMORY - Vice2 1 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: VICE2_1_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VICE2_1_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VICE2_1_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: VICE2_1_INST_POWER_SWITCH_MEMORY :: VICE1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_VICE2_1_INST_POWER_SWITCH_MEMORY_VICE1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_VICE2_1_INST_POWER_SWITCH_MEMORY_VICE1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_VICE2_1_INST_POWER_SWITCH_MEMORY_VICE1_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VICE2_INST_CLOCK_ENABLE - Vice2 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: VICE2_INST_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_reserved0_MASK         0xfffffff0
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_reserved0_SHIFT        4
+
+/* CLKGEN :: VICE2_INST_CLOCK_ENABLE :: VICE_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VICE2_INST_CLOCK_ENABLE :: VICE_CORE_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_CORE_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_CORE_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VICE2_INST_CLOCK_ENABLE :: VICE_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VICE2_INST_CLOCK_ENABLE :: VICE_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VICE2_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: VICE2_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_STATUS_reserved0_MASK  0xfffffff0
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
+
+/* CLKGEN :: VICE2_INST_CLOCK_ENABLE_STATUS :: VICE_SCB_CLOCK_ENABLE_STATUS [03:03] */
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_STATUS_VICE_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_STATUS_VICE_SCB_CLOCK_ENABLE_STATUS_SHIFT 3
+
+/* CLKGEN :: VICE2_INST_CLOCK_ENABLE_STATUS :: VICE_CORE_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_STATUS_VICE_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_STATUS_VICE_CORE_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: VICE2_INST_CLOCK_ENABLE_STATUS :: VICE_216_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_STATUS_VICE_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_STATUS_VICE_216_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: VICE2_INST_CLOCK_ENABLE_STATUS :: VICE_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_STATUS_VICE_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_STATUS_VICE_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *VICE2_INST_MEMORY_STANDBY_ENABLE - Vice2 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: VICE2_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: VICE2_INST_MEMORY_STANDBY_ENABLE :: VICE_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE_VICE_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE_VICE_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE_VICE_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VICE2_INST_POWER_SWITCH_MEMORY - Vice2 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: VICE2_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY_reserved0_MASK  0xfffffffc
+#define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: VICE2_INST_POWER_SWITCH_MEMORY :: VICE_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY_VICE_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY_VICE_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY_VICE_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ZCPU_DUAL_TOP_INST_CLOCK_DISABLE - Disable ZCPU_DUAL_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_DISABLE :: DISABLE_ZMIPS_SLOWMIPS_CLOCK [00:00] */
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_SLOWMIPS_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_SLOWMIPS_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_SLOWMIPS_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_ZMIPS_SLOWMIPS_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_ZMIPS_SLOWMIPS_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_ZMIPS_SLOWMIPS_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *ZCPU_DUAL_TOP_INST_CLOCK_ENABLE - Zcpu dual top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3
+
+/* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_ENABLE :: ZMIPS_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_ENABLE :: ZMIPS_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_ZMIPS_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_ZMIPS_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_ZMIPS_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_ENABLE :: ZMIPS_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_ZMIPS_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_ZMIPS_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_ZMIPS_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS :: ZMIPS_SCB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS_ZMIPS_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS_ZMIPS_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS :: ZMIPS_216_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS_ZMIPS_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS_ZMIPS_216_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS :: ZMIPS_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS_ZMIPS_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_CLOCK_ENABLE_STATUS_ZMIPS_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK - Zcpu dual top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK :: ZMIPS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK :: ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK :: ZMIPS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_ZCPU_DUAL_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS - Bypass GENET_TOP_DUAL_RGMII_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_reserved0_SHIFT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS :: EEE_25_CLOCK_BYPASS [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_CLKGEN_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_common.h b/include/linux/brcmstb/7435b0/bchp_common.h
new file mode 100644
index 0000000..c2dec99
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_common.h
@@ -0,0 +1,3717 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Jul 20 15:43:02 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_COMMON_H__
+#define BCHP_COMMON_H__
+
+/**
+ * m = memory, c = core, r = register, f = field, d = data.
+ */
+#if !defined(GET_FIELD) && !defined(SET_FIELD)
+#define BRCM_MASK(c,r,f)    c##_##r##_##f##_MASK
+#define BRCM_SHIFT(c,r,f)   c##_##r##_##f##_SHIFT
+
+#define GET_FIELD(m,c,r,f) \
+((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)))
+
+#define SET_FIELD(m,c,r,f,d) \
+((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d)) << BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))))
+
+#define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d)
+#define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d)
+#define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d)
+
+#endif /* GET & SET */
+
+/***************************************************************************
+ *BCM7435_B0
+ ***************************************************************************/
+#define BCHP_PHYSICAL_OFFSET                               0x10000000
+#define BCHP_REGISTER_START                                0x00000000 /* DECODE_RBNODE_REGS_1 is first */
+#define BCHP_REGISTER_END                                  0x00fffd98 /* MOCA_HOSTMISC is last */
+#define BCHP_REGISTER_SIZE                                 0x003fff66 /* Number of registers */
+
+/****************************************************************************
+ * Core instance register start address.
+ ***************************************************************************/
+#define BCHP_DECODE_RBNODE_REGS_1_REG_START                0x00000000
+#define BCHP_DECODE_RBNODE_REGS_1_REG_END                  0x0000007c
+#define BCHP_DECODE_MAIN_1_REG_START                       0x00000100
+#define BCHP_DECODE_MAIN_1_REG_END                         0x000001fc
+#define BCHP_SDRAM_DEBUG_1_REG_START                       0x00000200
+#define BCHP_SDRAM_DEBUG_1_REG_END                         0x0000027c
+#define BCHP_DECODE_MCOM_1_REG_START                       0x00000300
+#define BCHP_DECODE_MCOM_1_REG_END                         0x0000031c
+#define BCHP_DECODE_SPRE_1_REG_START                       0x00000320
+#define BCHP_DECODE_SPRE_1_REG_END                         0x0000033c
+#define BCHP_DECODE_WPRD_1_REG_START                       0x00000340
+#define BCHP_DECODE_WPRD_1_REG_END                         0x0000035c
+#define BCHP_DECODE_DQNT_1_REG_START                       0x00000400
+#define BCHP_DECODE_DQNT_1_REG_END                         0x0000045c
+#define BCHP_DECODE_DQNT_8X8_1_REG_START                   0x00000500
+#define BCHP_DECODE_DQNT_8X8_1_REG_END                     0x0000057c
+#define BCHP_DECODE_VP8_XFRM_1_REG_START                   0x00000600
+#define BCHP_DECODE_VP8_XFRM_1_REG_END                     0x0000060c
+#define BCHP_DECODE_VP6_DCP_1_REG_START                    0x00000620
+#define BCHP_DECODE_VP6_DCP_1_REG_END                      0x0000062c
+#define BCHP_DECODE_XFRM_1_REG_START                       0x00000700
+#define BCHP_DECODE_XFRM_1_REG_END                         0x0000071c
+#define BCHP_DECODE_DBLK_1_REG_START                       0x00000720
+#define BCHP_DECODE_DBLK_1_REG_END                         0x0000073c
+#define BCHP_DECODE_MB_1_REG_START                         0x00000740
+#define BCHP_DECODE_MB_1_REG_END                           0x0000075c
+#define BCHP_REG_CABAC2BINS_1_REG_START                    0x00000b00
+#define BCHP_REG_CABAC2BINS_1_REG_END                      0x00000bfc
+#define BCHP_DECODE_SINT_1_REG_START                       0x00000c00
+#define BCHP_DECODE_SINT_1_REG_END                         0x00000dfc
+#define BCHP_DECODE_RVC_1_REG_START                        0x00000e00
+#define BCHP_DECODE_RVC_1_REG_END                          0x00000efc
+#define BCHP_DECODE_CPUREGS_1_REG_START                    0x00000f00
+#define BCHP_DECODE_CPUREGS_1_REG_END                      0x00000f7c
+#define BCHP_DECODE_CPUREGS2_1_REG_START                   0x00000f80
+#define BCHP_DECODE_CPUREGS2_1_REG_END                     0x00000ffc
+#define BCHP_DECODE_CPUDMA_1_REG_START                     0x00001800
+#define BCHP_DECODE_CPUDMA_1_REG_END                       0x000018fc
+#define BCHP_DECODE_DMAMEM_1_REG_START                     0x00001a00
+#define BCHP_DECODE_DMAMEM_1_REG_END                       0x000021fc
+#define BCHP_REG_CABAC2BINS2_1_REG_START                   0x00002400
+#define BCHP_REG_CABAC2BINS2_1_REG_END                     0x000027fc
+#define BCHP_DECODE_WPTBL_1_REG_START                      0x00003000
+#define BCHP_DECODE_WPTBL_1_REG_END                        0x000031fc
+#define BCHP_DECODE_SINT_OLOOP_1_REG_START                 0x0000cc00
+#define BCHP_DECODE_SINT_OLOOP_1_REG_END                   0x0000ccfc
+#define BCHP_DECODE_SD_1_REG_START                         0x00040800
+#define BCHP_DECODE_SD_1_REG_END                           0x00040ffc
+#define BCHP_DECODE_IND_SDRAM_REGS_1_REG_START             0x00041000
+#define BCHP_DECODE_IND_SDRAM_REGS_1_REG_END               0x0004107c
+#define BCHP_DECODE_CPUCORE_1_REG_START                    0x00044000
+#define BCHP_DECODE_CPUCORE_1_REG_END                      0x00044ffc
+#define BCHP_DECODE_CPUAUX_1_REG_START                     0x00045000
+#define BCHP_DECODE_CPUAUX_1_REG_END                       0x00045ffc
+#define BCHP_DECODE_CPUIMEM_1_REG_START                    0x00046000
+#define BCHP_DECODE_CPUIMEM_1_REG_END                      0x00047ffc
+#define BCHP_DECODE_CPUDMEM_1_REG_START                    0x00048000
+#define BCHP_DECODE_CPUDMEM_1_REG_END                      0x0004fffc
+#define BCHP_DECODE_IND_SDRAM_REGS2_1_REG_START            0x00051000
+#define BCHP_DECODE_IND_SDRAM_REGS2_1_REG_END              0x0005107c
+#define BCHP_DECODE_CPUDMA2_1_REG_START                    0x00051800
+#define BCHP_DECODE_CPUDMA2_1_REG_END                      0x000518fc
+#define BCHP_DECODE_DMAMEM2_1_REG_START                    0x00051a00
+#define BCHP_DECODE_DMAMEM2_1_REG_END                      0x000521fc
+#define BCHP_DECODE_CPUCORE2_1_REG_START                   0x00054000
+#define BCHP_DECODE_CPUCORE2_1_REG_END                     0x00054ffc
+#define BCHP_DECODE_CPUAUX2_1_REG_START                    0x00055000
+#define BCHP_DECODE_CPUAUX2_1_REG_END                      0x00055ffc
+#define BCHP_DECODE_CPUIMEM2_1_REG_START                   0x00056000
+#define BCHP_DECODE_CPUIMEM2_1_REG_END                     0x00057ffc
+#define BCHP_DECODE_CPUDMEM2_1_REG_START                   0x00058000
+#define BCHP_DECODE_CPUDMEM2_1_REG_END                     0x0005fffc
+#define BCHP_DECODE_IP_SHIM_1_REG_START                    0x00060000
+#define BCHP_DECODE_IP_SHIM_1_REG_END                      0x00060090
+#define BCHP_AVD_CACHE_1_REG_START                         0x00062000
+#define BCHP_AVD_CACHE_1_REG_END                           0x0006203c
+#define BCHP_AVD_INTR2_1_REG_START                         0x00080000
+#define BCHP_AVD_INTR2_1_REG_END                           0x0008002c
+#define BCHP_AVD_RGR_1_REG_START                           0x00080400
+#define BCHP_AVD_RGR_1_REG_END                             0x00080410
+#define BCHP_VICH_1_REG_START                              0x00104000
+#define BCHP_VICH_1_REG_END                                0x0010408b
+#define BCHP_SATA_GRB_REG_START                            0x00180000
+#define BCHP_SATA_GRB_REG_END                              0x0018000c
+#define BCHP_SATA_TOP_CTRL_REG_START                       0x00180020
+#define BCHP_SATA_TOP_CTRL_REG_END                         0x00180038
+#define BCHP_SATA3_INTR2_REG_START                         0x00180080
+#define BCHP_SATA3_INTR2_REG_END                           0x001800ac
+#define BCHP_SATA_AHCI_GHC_REG_START                       0x00181000
+#define BCHP_SATA_AHCI_GHC_REG_END                         0x00181028
+#define BCHP_SATA_GLOBAL_RESERVED_REG_START                0x0018102c
+#define BCHP_SATA_GLOBAL_RESERVED_REG_END                  0x0018109c
+#define BCHP_SATA_PORT0_AHCI_S1_REG_START                  0x00181100
+#define BCHP_SATA_PORT0_AHCI_S1_REG_END                    0x0018111c
+#define BCHP_SATA_PORT0_AHCI_S2_REG_START                  0x00181120
+#define BCHP_SATA_PORT0_AHCI_S2_REG_END                    0x00181134
+#define BCHP_SATA_PORT0_AHCI_S3_REG_START                  0x00181138
+#define BCHP_SATA_PORT0_AHCI_S3_REG_END                    0x0018117c
+#define BCHP_SATA_PORT1_AHCI_S1_REG_START                  0x00181180
+#define BCHP_SATA_PORT1_AHCI_S1_REG_END                    0x0018119c
+#define BCHP_SATA_PORT1_AHCI_S2_REG_START                  0x001811a0
+#define BCHP_SATA_PORT1_AHCI_S2_REG_END                    0x001811b4
+#define BCHP_SATA_PORT1_AHCI_S3_REG_START                  0x001811b8
+#define BCHP_SATA_PORT1_AHCI_S3_REG_END                    0x001811fc
+#define BCHP_SATA_AHCI_PCICFG_REG_START                    0x00181600
+#define BCHP_SATA_AHCI_PCICFG_REG_END                      0x00181664
+#define BCHP_SATA_PORT0_CTRL_REG_START                     0x00181700
+#define BCHP_SATA_PORT0_CTRL_REG_END                       0x00181730
+#define BCHP_SATA_PORT0_CJPAT_REG_START                    0x00181740
+#define BCHP_SATA_PORT0_CJPAT_REG_END                      0x00181764
+#define BCHP_SATA_PORT1_CTRL_REG_START                     0x00181780
+#define BCHP_SATA_PORT1_CTRL_REG_END                       0x001817b0
+#define BCHP_SATA_PORT1_CJPAT_REG_START                    0x001817c0
+#define BCHP_SATA_PORT1_CJPAT_REG_END                      0x001817e4
+#define BCHP_SATA_LEG_PCICFG_REG_START                     0x00181800
+#define BCHP_SATA_LEG_PCICFG_REG_END                       0x00181880
+#define BCHP_SATA_PORT0_LEG_S1_REG_START                   0x00181900
+#define BCHP_SATA_PORT0_LEG_S1_REG_END                     0x00181934
+#define BCHP_SATA_PORT0_LEG_S2_REG_START                   0x00181940
+#define BCHP_SATA_PORT0_LEG_S2_REG_END                     0x00181954
+#define BCHP_SATA_PORT0_LEG_S3_REG_START                   0x00181958
+#define BCHP_SATA_PORT0_LEG_S3_REG_END                     0x00181998
+#define BCHP_SATA_PORT1_LEG_S1_REG_START                   0x00181a00
+#define BCHP_SATA_PORT1_LEG_S1_REG_END                     0x00181a34
+#define BCHP_SATA_PORT1_LEG_S2_REG_START                   0x00181a40
+#define BCHP_SATA_PORT1_LEG_S2_REG_END                     0x00181a54
+#define BCHP_SATA_PORT1_LEG_S3_REG_START                   0x00181a58
+#define BCHP_SATA_PORT1_LEG_S3_REG_END                     0x00181a98
+#define BCHP_SCPU_LOCALRAM_REG_START                       0x00300000
+#define BCHP_SCPU_LOCALRAM_REG_END                         0x00307ffc
+#define BCHP_SCPU_GLOBALRAM_REG_START                      0x00308000
+#define BCHP_SCPU_GLOBALRAM_REG_END                        0x003083fc
+#define BCHP_SCPU_MISB_BRIDGE_REG_START                    0x00308400
+#define BCHP_SCPU_MISB_BRIDGE_REG_END                      0x00308410
+#define BCHP_SCPU_RGR_BRIDGE_REG_START                     0x00308420
+#define BCHP_SCPU_RGR_BRIDGE_REG_END                       0x00308430
+#define BCHP_SCPU_INTR1_REG_START                          0x00308440
+#define BCHP_SCPU_INTR1_REG_END                            0x00308458
+#define BCHP_INTERNAL_INTR2_REG_START                      0x00308480
+#define BCHP_INTERNAL_INTR2_REG_END                        0x003084ac
+#define BCHP_BSP_IPI_INTR2_REG_START                       0x003084c0
+#define BCHP_BSP_IPI_INTR2_REG_END                         0x003084ec
+#define BCHP_CPU_IPI_INTR2_REG_START                       0x00308500
+#define BCHP_CPU_IPI_INTR2_REG_END                         0x0030852c
+#define BCHP_SCPU_HOST_INTR2_REG_START                     0x00308540
+#define BCHP_SCPU_HOST_INTR2_REG_END                       0x0030856c
+#define BCHP_SCPU_TOP_CTRL_REG_START                       0x00308580
+#define BCHP_SCPU_TOP_CTRL_REG_END                         0x00308588
+#define BCHP_SCPU_SEC_TIME_REG_START                       0x003085a0
+#define BCHP_SCPU_SEC_TIME_REG_END                         0x003085b4
+#define BCHP_SCPU_PM_REG_START                             0x00308980
+#define BCHP_SCPU_PM_REG_END                               0x00308988
+#define BCHP_SCPU_TIMER_REG_START                          0x00308e80
+#define BCHP_SCPU_TIMER_REG_END                            0x00308ebc
+#define BCHP_S_SCPU_REG_START                              0x00310000
+#define BCHP_S_SCPU_REG_END                                0x0031bffc
+#define BCHP_BSP_CMDBUF_REG_START                          0x00329800
+#define BCHP_BSP_CMDBUF_REG_END                            0x00329ffc
+#define BCHP_BSP_GLB_CONTROL_REG_START                     0x0032b000
+#define BCHP_BSP_GLB_CONTROL_REG_END                       0x0032b0a4
+#define BCHP_BSP_PKL_REG_START                             0x0032b300
+#define BCHP_BSP_PKL_REG_END                               0x0032b37c
+#define BCHP_BSP_INST_PATCH_CTRL_REG_START                 0x0032b400
+#define BCHP_BSP_INST_PATCH_CTRL_REG_END                   0x0032b408
+#define BCHP_BSP_BOOT_PATCH_CTRL_REG_START                 0x0032b410
+#define BCHP_BSP_BOOT_PATCH_CTRL_REG_END                   0x0032b418
+#define BCHP_BSP_CONTROL_INTR2_REG_START                   0x0032b800
+#define BCHP_BSP_CONTROL_INTR2_REG_END                     0x0032b82c
+#define BCHP_XPT_SECURITY_REG_START                        0x00360000
+#define BCHP_XPT_SECURITY_REG_END                          0x0036fffc
+#define BCHP_MMSCRAM_REG_START                             0x00370000
+#define BCHP_MMSCRAM_REG_END                               0x00371ffc
+#define BCHP_MEM_DMA_SECURE_REG_START                      0x00372000
+#define BCHP_MEM_DMA_SECURE_REG_END                        0x0037200c
+#define BCHP_MEM_DMA_SECURE_1_REG_START                    0x00372200
+#define BCHP_MEM_DMA_SECURE_1_REG_END                      0x0037220c
+#define BCHP_MMSCRAM_1_REG_START                           0x00374000
+#define BCHP_MMSCRAM_1_REG_END                             0x00375ffc
+#define BCHP_SECTOP_GRB_REG_START                          0x00376000
+#define BCHP_SECTOP_GRB_REG_END                            0x0037600c
+#define BCHP_JTAG_OTP_REG_START                            0x00376100
+#define BCHP_JTAG_OTP_REG_END                              0x00376138
+#define BCHP_MEM_DMA_0_REG_START                           0x00376200
+#define BCHP_MEM_DMA_0_REG_END                             0x00376224
+#define BCHP_XPT_SECURITY_NS_REG_START                     0x00376300
+#define BCHP_XPT_SECURITY_NS_REG_END                       0x00376310
+#define BCHP_MEM_DMA_1_REG_START                           0x00376400
+#define BCHP_MEM_DMA_1_REG_END                             0x00376424
+#define BCHP_MEMC_GEN_0_REG_START                          0x003b0000
+#define BCHP_MEMC_GEN_0_REG_END                            0x003b04f8
+#define BCHP_MEMC_GEN_2_0_REG_START                        0x003b0600
+#define BCHP_MEMC_GEN_2_0_REG_END                          0x003b06ec
+#define BCHP_MEMC_ARB_0_REG_START                          0x003b1000
+#define BCHP_MEMC_ARB_0_REG_END                            0x003b1244
+#define BCHP_MEMC_DDR_0_REG_START                          0x003b2000
+#define BCHP_MEMC_DDR_0_REG_END                            0x003b22fc
+#define BCHP_MEMC_L2_0_REG_START                           0x003b3000
+#define BCHP_MEMC_L2_0_REG_END                             0x003b302c
+#define BCHP_MEMC_L2_1_0_REG_START                         0x003b3800
+#define BCHP_MEMC_L2_1_0_REG_END                           0x003b382c
+#define BCHP_MEMC_RGRB_0_REG_START                         0x003b4000
+#define BCHP_MEMC_RGRB_0_REG_END                           0x003b4010
+#define BCHP_MEMC_MISC_0_REG_START                         0x003b5000
+#define BCHP_MEMC_MISC_0_REG_END                           0x003b5010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_START            0x003b6000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_END              0x003b60c4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_START             0x003b6200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_END               0x003b63b0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_REG_START             0x003b6400
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_REG_END               0x003b65b0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_START         0x003b8000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_END           0x003b8138
+#define BCHP_S_MEMC_0_REG_START                            0x003ba000
+#define BCHP_S_MEMC_0_REG_END                              0x003ba220
+#define BCHP_MEMC_GEN_1_REG_START                          0x003c0000
+#define BCHP_MEMC_GEN_1_REG_END                            0x003c04f8
+#define BCHP_MEMC_GEN_2_1_REG_START                        0x003c0600
+#define BCHP_MEMC_GEN_2_1_REG_END                          0x003c06ec
+#define BCHP_MEMC_ARB_1_REG_START                          0x003c1000
+#define BCHP_MEMC_ARB_1_REG_END                            0x003c1244
+#define BCHP_MEMC_DDR_1_REG_START                          0x003c2000
+#define BCHP_MEMC_DDR_1_REG_END                            0x003c22fc
+#define BCHP_MEMC_L2_1_REG_START                           0x003c3000
+#define BCHP_MEMC_L2_1_REG_END                             0x003c302c
+#define BCHP_MEMC_L2_1_1_REG_START                         0x003c3800
+#define BCHP_MEMC_L2_1_1_REG_END                           0x003c382c
+#define BCHP_MEMC_RGRB_1_REG_START                         0x003c4000
+#define BCHP_MEMC_RGRB_1_REG_END                           0x003c4010
+#define BCHP_MEMC_MISC_1_REG_START                         0x003c5000
+#define BCHP_MEMC_MISC_1_REG_END                           0x003c5010
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_REG_START            0x003c6000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_REG_END              0x003c60c4
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_REG_START             0x003c6200
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_REG_END               0x003c63b0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_REG_START             0x003c6400
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_REG_END               0x003c65b0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_REG_START         0x003c8000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_REG_END           0x003c8138
+#define BCHP_S_MEMC_1_REG_START                            0x003ca000
+#define BCHP_S_MEMC_1_REG_END                              0x003ca220
+#define BCHP_SUN_GISB_ARB_REG_START                        0x00400000
+#define BCHP_SUN_GISB_ARB_REG_END                          0x00400178
+#define BCHP_SUN_GR_REG_START                              0x00400400
+#define BCHP_SUN_GR_REG_END                                0x0040040c
+#define BCHP_SSP_RG_REG_START                              0x00400600
+#define BCHP_SSP_RG_REG_END                                0x0040060c
+#define BCHP_SUN_RG_REG_START                              0x00400800
+#define BCHP_SUN_RG_REG_END                                0x0040080c
+#define BCHP_TPCAP_REG_START                               0x00400c00
+#define BCHP_TPCAP_REG_END                                 0x00400c84
+#define BCHP_SUN_L2_REG_START                              0x00403000
+#define BCHP_SUN_L2_REG_END                                0x00403044
+#define BCHP_SM_L2_REG_START                               0x00403400
+#define BCHP_SM_L2_REG_END                                 0x0040342c
+#define BCHP_SM_REG_START                                  0x00403800
+#define BCHP_SM_REG_END                                    0x00403824
+#define BCHP_SM_FAST_REG_START                             0x00403c00
+#define BCHP_SM_FAST_REG_END                               0x00403c18
+#define BCHP_SUN_TOP_CTRL_REG_START                        0x00404000
+#define BCHP_SUN_TOP_CTRL_REG_END                          0x00404518
+#define BCHP_IRB_REG_START                                 0x00406000
+#define BCHP_IRB_REG_END                                   0x00406138
+#define BCHP_PM_REG_START                                  0x00406180
+#define BCHP_PM_REG_END                                    0x0040618c
+#define BCHP_BSCC_REG_START                                0x00406200
+#define BCHP_BSCC_REG_END                                  0x00406254
+#define BCHP_BSCD_REG_START                                0x00406280
+#define BCHP_BSCD_REG_END                                  0x004062d4
+#define BCHP_BSCA_REG_START                                0x00406300
+#define BCHP_BSCA_REG_END                                  0x00406354
+#define BCHP_PWM_REG_START                                 0x00406580
+#define BCHP_PWM_REG_END                                   0x004065a4
+#define BCHP_GIO_REG_START                                 0x00406700
+#define BCHP_GIO_REG_END                                   0x0040677c
+#define BCHP_IRQ0_REG_START                                0x00406780
+#define BCHP_IRQ0_REG_END                                  0x00406784
+#define BCHP_IRQ1_REG_START                                0x00406788
+#define BCHP_IRQ1_REG_END                                  0x0040678c
+#define BCHP_TIMER_REG_START                               0x004067c0
+#define BCHP_TIMER_REG_END                                 0x004067fc
+#define BCHP_PWMB_REG_START                                0x00406800
+#define BCHP_PWMB_REG_END                                  0x00406824
+#define BCHP_UARTA_REG_START                               0x00406b00
+#define BCHP_UARTA_REG_END                                 0x00406b1c
+#define BCHP_UARTB_REG_START                               0x00406b40
+#define BCHP_UARTB_REG_END                                 0x00406b5c
+#define BCHP_UARTC_REG_START                               0x00406b80
+#define BCHP_UARTC_REG_END                                 0x00406b9c
+#define BCHP_SCA_REG_START                                 0x00406c00
+#define BCHP_SCA_REG_END                                   0x00406cbc
+#define BCHP_SCB_REG_START                                 0x00406cc0
+#define BCHP_SCB_REG_END                                   0x00406d7c
+#define BCHP_SCIRQ0_REG_START                              0x00406e40
+#define BCHP_SCIRQ0_REG_END                                0x00406e44
+#define BCHP_SCIRQ1_REG_START                              0x00406e48
+#define BCHP_SCIRQ1_REG_END                                0x00406e4c
+#define BCHP_SCIRQ_SCPU_REG_START                          0x00406e50
+#define BCHP_SCIRQ_SCPU_REG_END                            0x00406e54
+#define BCHP_MCIF_REG_START                                0x00407000
+#define BCHP_MCIF_REG_END                                  0x00407020
+#define BCHP_MCIF_INTR2_REG_START                          0x00407080
+#define BCHP_MCIF_INTR2_REG_END                            0x004070c4
+#define BCHP_TMON_REG_START                                0x00407100
+#define BCHP_TMON_REG_END                                  0x00407150
+#define BCHP_UPG_AUX_INTR2_REG_START                       0x00407180
+#define BCHP_UPG_AUX_INTR2_REG_END                         0x004071ac
+#define BCHP_CTK_REG_START                                 0x00407200
+#define BCHP_CTK_REG_END                                   0x00407378
+#define BCHP_UPG_UART_DMA_REG_START                        0x00407400
+#define BCHP_UPG_UART_DMA_REG_END                          0x00407428
+#define BCHP_AON_CTRL_REG_START                            0x00408000
+#define BCHP_AON_CTRL_REG_END                              0x004083fc
+#define BCHP_AON_L2_REG_START                              0x00408400
+#define BCHP_AON_L2_REG_END                                0x0040842c
+#define BCHP_AON_PM_L2_REG_START                           0x00408440
+#define BCHP_AON_PM_L2_REG_END                             0x0040846c
+#define BCHP_AON_PIN_CTRL_REG_START                        0x00408500
+#define BCHP_AON_PIN_CTRL_REG_END                          0x0040851c
+#define BCHP_AON_HDMI_TX_REG_START                         0x00408600
+#define BCHP_AON_HDMI_TX_REG_END                           0x00408698
+#define BCHP_AON_HDMI_RX_REG_START                         0x00408800
+#define BCHP_AON_HDMI_RX_REG_END                           0x00408904
+#define BCHP_LDK_REG_START                                 0x00409000
+#define BCHP_LDK_REG_END                                   0x0040903c
+#define BCHP_PM_AON_REG_START                              0x00409040
+#define BCHP_PM_AON_REG_END                                0x00409048
+#define BCHP_ICAP_REG_START                                0x00409080
+#define BCHP_ICAP_REG_END                                  0x004090bc
+#define BCHP_KBD1_REG_START                                0x004090c0
+#define BCHP_KBD1_REG_END                                  0x004090fc
+#define BCHP_KBD2_REG_START                                0x00409100
+#define BCHP_KBD2_REG_END                                  0x0040913c
+#define BCHP_KBD3_REG_START                                0x00409140
+#define BCHP_KBD3_REG_END                                  0x0040917c
+#define BCHP_BSCE_REG_START                                0x00409180
+#define BCHP_BSCE_REG_END                                  0x004091d4
+#define BCHP_MSPI_REG_START                                0x00409200
+#define BCHP_MSPI_REG_END                                  0x0040937c
+#define BCHP_BSCB_REG_START                                0x00409400
+#define BCHP_BSCB_REG_END                                  0x00409454
+#define BCHP_IRQ0_AON_REG_START                            0x00409480
+#define BCHP_IRQ0_AON_REG_END                              0x00409484
+#define BCHP_IRQ1_AON_REG_START                            0x00409488
+#define BCHP_IRQ1_AON_REG_END                              0x0040948c
+#define BCHP_GIO_AON_REG_START                             0x004094c0
+#define BCHP_GIO_AON_REG_END                               0x004094fc
+#define BCHP_BICAP_REG_START                               0x00409500
+#define BCHP_BICAP_REG_END                                 0x00409538
+#define BCHP_UPG_AUX_AON_INTR2_REG_START                   0x00409540
+#define BCHP_UPG_AUX_AON_INTR2_REG_END                     0x0040956c
+#define BCHP_WKTMR_REG_START                               0x00409580
+#define BCHP_WKTMR_REG_END                                 0x00409590
+#define BCHP_SYS_GISB_ARB_SEC_REG_START                    0x0040e000
+#define BCHP_SYS_GISB_ARB_SEC_REG_END                      0x0040e154
+#define BCHP_SYS_TOP_CTRL_SEC_REG_START                    0x0040e700
+#define BCHP_SYS_TOP_CTRL_SEC_REG_END                      0x0040e704
+#define BCHP_AON_CTRL_SECURE_REG_START                     0x0040e800
+#define BCHP_AON_CTRL_SECURE_REG_END                       0x0040e87c
+#define BCHP_PCIE_RC_CFG_TYPE1_REG_START                   0x00410000
+#define BCHP_PCIE_RC_CFG_TYPE1_REG_END                     0x0041003c
+#define BCHP_PCIE_RC_CFG_PM_REG_START                      0x00410048
+#define BCHP_PCIE_RC_CFG_PM_REG_END                        0x0041004c
+#define BCHP_PCIE_RC_CFG_PCIE_REG_START                    0x004100ac
+#define BCHP_PCIE_RC_CFG_PCIE_REG_END                      0x004100e4
+#define BCHP_PCIE_RC_CFG_AER_REG_START                     0x00410100
+#define BCHP_PCIE_RC_CFG_AER_REG_END                       0x00410134
+#define BCHP_PCIE_RC_CFG_VC_REG_START                      0x00410160
+#define BCHP_PCIE_RC_CFG_VC_REG_END                        0x00410178
+#define BCHP_PCIE_RC_CFG_VENDOR_REG_START                  0x00410180
+#define BCHP_PCIE_RC_CFG_VENDOR_REG_END                    0x004101a4
+#define BCHP_PCIE_RC_CFG_PRIV0_REG_START                   0x00410404
+#define BCHP_PCIE_RC_CFG_PRIV0_REG_END                     0x00410418
+#define BCHP_PCIE_RC_CFG_PRIV1_REG_START                   0x00410428
+#define BCHP_PCIE_RC_CFG_PRIV1_REG_END                     0x00410630
+#define BCHP_PCIE_RC_TL_REG_START                          0x00410800
+#define BCHP_PCIE_RC_TL_REG_END                            0x00410998
+#define BCHP_PCIE_RC_DL_REG_START                          0x00411000
+#define BCHP_PCIE_RC_DL_REG_END                            0x00411424
+#define BCHP_PCIE_RC_PL_REG_START                          0x00411800
+#define BCHP_PCIE_RC_PL_REG_END                            0x00411d30
+#define BCHP_PCIE_EP_CFG_TYPE0_REG_START                   0x00412000
+#define BCHP_PCIE_EP_CFG_TYPE0_REG_END                     0x0041203c
+#define BCHP_PCIE_EP_CFG_PM_REG_START                      0x00412048
+#define BCHP_PCIE_EP_CFG_PM_REG_END                        0x0041204c
+#define BCHP_PCIE_EP_CFG_VPD_REG_START                     0x00412050
+#define BCHP_PCIE_EP_CFG_VPD_REG_END                       0x00412054
+#define BCHP_PCIE_EP_CFG_MSI_REG_START                     0x00412058
+#define BCHP_PCIE_EP_CFG_MSI_REG_END                       0x00412064
+#define BCHP_PCIE_EP_CFG_MSIX_REG_START                    0x004120a0
+#define BCHP_PCIE_EP_CFG_MSIX_REG_END                      0x004120a8
+#define BCHP_PCIE_EP_CFG_PCIE_REG_START                    0x004120ac
+#define BCHP_PCIE_EP_CFG_PCIE_REG_END                      0x004120e4
+#define BCHP_PCIE_EP_CFG_AER_REG_START                     0x00412100
+#define BCHP_PCIE_EP_CFG_AER_REG_END                       0x00412134
+#define BCHP_PCIE_EP_CFG_DEV_REG_START                     0x0041213c
+#define BCHP_PCIE_EP_CFG_DEV_REG_END                       0x00412144
+#define BCHP_PCIE_EP_CFG_PB_REG_START                      0x00412150
+#define BCHP_PCIE_EP_CFG_PB_REG_END                        0x0041215c
+#define BCHP_PCIE_EP_CFG_VC_REG_START                      0x00412160
+#define BCHP_PCIE_EP_CFG_VC_REG_END                        0x00412178
+#define BCHP_PCIE_EP_CFG_VENDOR_REG_START                  0x00412180
+#define BCHP_PCIE_EP_CFG_VENDOR_REG_END                    0x004121a4
+#define BCHP_PCIE_EP_CFG_PRIV0_REG_START                   0x00412404
+#define BCHP_PCIE_EP_CFG_PRIV0_REG_END                     0x00412418
+#define BCHP_PCIE_EP_CFG_PRIV1_REG_START                   0x00412428
+#define BCHP_PCIE_EP_CFG_PRIV1_REG_END                     0x00412630
+#define BCHP_PCIE_EP_TL_REG_START                          0x00412800
+#define BCHP_PCIE_EP_TL_REG_END                            0x00412998
+#define BCHP_PCIE_EP_DL_REG_START                          0x00413000
+#define BCHP_PCIE_EP_DL_REG_END                            0x00413424
+#define BCHP_PCIE_EP_PL_REG_START                          0x00413800
+#define BCHP_PCIE_EP_PL_REG_END                            0x00413d30
+#define BCHP_PCIE_MISC_REG_START                           0x00414000
+#define BCHP_PCIE_MISC_REG_END                             0x00414094
+#define BCHP_PCIE_MISC_PERST_REG_START                     0x00414100
+#define BCHP_PCIE_MISC_PERST_REG_END                       0x00414104
+#define BCHP_PCIE_MISC_HARD_REG_START                      0x00414200
+#define BCHP_PCIE_MISC_HARD_REG_END                        0x00414204
+#define BCHP_PCIE_INTR2_REG_START                          0x00414300
+#define BCHP_PCIE_INTR2_REG_END                            0x0041432c
+#define BCHP_PCIE_DMA_REG_START                            0x00414400
+#define BCHP_PCIE_DMA_REG_END                              0x0041446c
+#define BCHP_PCIE_EXT_CFG_REG_START                        0x00418000
+#define BCHP_PCIE_EXT_CFG_REG_END                          0x00419008
+#define BCHP_HIF_RGR1_REG_START                            0x00419200
+#define BCHP_HIF_RGR1_REG_END                              0x00419210
+#define BCHP_HIF_PCIe_RG_REG_START                         0x00419300
+#define BCHP_HIF_PCIe_RG_REG_END                           0x0041930c
+#define BCHP_SDIO_0_HOST_REG_START                         0x0041a000
+#define BCHP_SDIO_0_HOST_REG_END                           0x0041a0fc
+#define BCHP_SDIO_0_CFG_REG_START                          0x0041a100
+#define BCHP_SDIO_0_CFG_REG_END                            0x0041a1fc
+#define BCHP_SDIO_1_HOST_REG_START                         0x0041a200
+#define BCHP_SDIO_1_HOST_REG_END                           0x0041a2fc
+#define BCHP_SDIO_1_CFG_REG_START                          0x0041a300
+#define BCHP_SDIO_1_CFG_REG_END                            0x0041a3fc
+#define BCHP_SDIO_1_BOOT_REG_START                         0x0041a400
+#define BCHP_SDIO_1_BOOT_REG_END                           0x0041a43c
+#define BCHP_EBI_REG_START                                 0x0041a800
+#define BCHP_EBI_REG_END                                   0x0041abfc
+#define BCHP_HIF_INTR2_REG_START                           0x0041b000
+#define BCHP_HIF_INTR2_REG_END                             0x0041b02c
+#define BCHP_IPI0_INTR2_REG_START                          0x0041b100
+#define BCHP_IPI0_INTR2_REG_END                            0x0041b12c
+#define BCHP_IPI1_INTR2_REG_START                          0x0041b200
+#define BCHP_IPI1_INTR2_REG_END                            0x0041b22c
+#define BCHP_IPI2_INTR2_REG_START                          0x0041b300
+#define BCHP_IPI2_INTR2_REG_END                            0x0041b32c
+#define BCHP_IPI3_INTR2_REG_START                          0x0041b400
+#define BCHP_IPI3_INTR2_REG_END                            0x0041b42c
+#define BCHP_HIF_CPU_INTR1_REG_START                       0x0041b500
+#define BCHP_HIF_CPU_INTR1_REG_END                         0x0041b53c
+#define BCHP_HIF_CPU_TP1_INTR1_REG_START                   0x0041b600
+#define BCHP_HIF_CPU_TP1_INTR1_REG_END                     0x0041b63c
+#define BCHP_HIF_CPU_TP2_INTR1_REG_START                   0x0041b700
+#define BCHP_HIF_CPU_TP2_INTR1_REG_END                     0x0041b73c
+#define BCHP_HIF_CPU_TP3_INTR1_REG_START                   0x0041b800
+#define BCHP_HIF_CPU_TP3_INTR1_REG_END                     0x0041b83c
+#define BCHP_PCI_PCIE_INTR1_REG_START                      0x0041b900
+#define BCHP_PCI_PCIE_INTR1_REG_END                        0x0041b93c
+#define BCHP_HIF_RGR2_REG_START                            0x0041ba00
+#define BCHP_HIF_RGR2_REG_END                              0x0041ba10
+#define BCHP_HIF_SPI_INTR2_REG_START                       0x0041bd00
+#define BCHP_HIF_SPI_INTR2_REG_END                         0x0041bd2c
+#define BCHP_HIF_TOP_CTRL_REG_START                        0x0041c400
+#define BCHP_HIF_TOP_CTRL_REG_END                          0x0041c434
+#define BCHP_WEBHIF_L1_MASK_REG_START                      0x0041c500
+#define BCHP_WEBHIF_L1_MASK_REG_END                        0x0041c50c
+#define BCHP_ZDCBIUREG_PUBLIC_REG_START                    0x0041c600
+#define BCHP_ZDCBIUREG_PUBLIC_REG_END                      0x0041c67c
+#define BCHP_ZDCBIUREG_SwReset_REG_START                   0x0041c700
+#define BCHP_ZDCBIUREG_SwReset_REG_END                     0x0041c714
+#define BCHP_NAND_REG_START                                0x0041c800
+#define BCHP_NAND_REG_END                                  0x0041cdfc
+#define BCHP_FLASH_DMA_REG_START                           0x0041d000
+#define BCHP_FLASH_DMA_REG_END                             0x0041d01c
+#define BCHP_EDU_REG_START                                 0x0041d100
+#define BCHP_EDU_REG_END                                   0x0041d120
+#define BCHP_BSPI_REG_START                                0x0041d200
+#define BCHP_BSPI_REG_END                                  0x0041d24c
+#define BCHP_BSPI_RAF_REG_START                            0x0041d300
+#define BCHP_BSPI_RAF_REG_END                              0x0041d320
+#define BCHP_HIF_MSPI_REG_START                            0x0041d400
+#define BCHP_HIF_MSPI_REG_END                              0x0041d584
+#define BCHP_WEBHIF_RGR1_REG_START                         0x00420000
+#define BCHP_WEBHIF_RGR1_REG_END                           0x00420010
+#define BCHP_WEBHIF_INTR2_REG_START                        0x00420100
+#define BCHP_WEBHIF_INTR2_REG_END                          0x0042012c
+#define BCHP_WEBHIF_IPI0_INTR2_REG_START                   0x00420200
+#define BCHP_WEBHIF_IPI0_INTR2_REG_END                     0x0042022c
+#define BCHP_WEBHIF_IPI1_INTR2_REG_START                   0x00420300
+#define BCHP_WEBHIF_IPI1_INTR2_REG_END                     0x0042032c
+#define BCHP_WEBHIF_STB_IPI0_INTR2_REG_START               0x00420400
+#define BCHP_WEBHIF_STB_IPI0_INTR2_REG_END                 0x0042042c
+#define BCHP_WEBHIF_STB_IPI1_INTR2_REG_START               0x00420500
+#define BCHP_WEBHIF_STB_IPI1_INTR2_REG_END                 0x0042052c
+#define BCHP_WEBHIF_CPU_INTR1_REG_START                    0x00420600
+#define BCHP_WEBHIF_CPU_INTR1_REG_END                      0x0042063c
+#define BCHP_WEBHIF_CPU_TP1_INTR1_REG_START                0x00420700
+#define BCHP_WEBHIF_CPU_TP1_INTR1_REG_END                  0x0042073c
+#define BCHP_WEBHIF_SCRATCH_REG_START                      0x00420800
+#define BCHP_WEBHIF_SCRATCH_REG_END                        0x0042081c
+#define BCHP_WEBHIF_TIMER_REG_START                        0x00420900
+#define BCHP_WEBHIF_TIMER_REG_END                          0x0042093c
+#define BCHP_MICH_REG_START                                0x00429000
+#define BCHP_MICH_REG_END                                  0x00429000
+#define BCHP_HIF_SECURE_CTRL_REG_START                     0x00429100
+#define BCHP_HIF_SECURE_CTRL_REG_END                       0x00429100
+#define BCHP_HIF_SECURE_BSPI_REG_START                     0x00429200
+#define BCHP_HIF_SECURE_BSPI_REG_END                       0x00429200
+#define BCHP_HIF_SECURE_LR_SPI_REG_START                   0x00429300
+#define BCHP_HIF_SECURE_LR_SPI_REG_END                     0x00429300
+#define BCHP_NAND_SECURE_REG_START                         0x00429400
+#define BCHP_NAND_SECURE_REG_END                           0x00429400
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_START        0x00429800
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_END          0x00429800
+#define BCHP_MICH1_REG_START                               0x00429a00
+#define BCHP_MICH1_REG_END                                 0x00429a00
+#define BCHP_ZDCBIUREG_SECURE_REG_START                    0x00429c00
+#define BCHP_ZDCBIUREG_SECURE_REG_END                      0x00429c00
+#define BCHP_CLKGEN_REG_START                              0x00430000
+#define BCHP_CLKGEN_REG_END                                0x004306b8
+#define BCHP_VCXO_0_RM_REG_START                           0x00432800
+#define BCHP_VCXO_0_RM_REG_END                             0x0043282c
+#define BCHP_VCXO_1_RM_REG_START                           0x00432880
+#define BCHP_VCXO_1_RM_REG_END                             0x004328ac
+#define BCHP_VCXO_2_RM_REG_START                           0x00432900
+#define BCHP_VCXO_2_RM_REG_END                             0x0043292c
+#define BCHP_CLKGEN_GR_REG_START                           0x00433000
+#define BCHP_CLKGEN_GR_REG_END                             0x0043300c
+#define BCHP_AVS_HW_MNTR_REG_START                         0x00434000
+#define BCHP_AVS_HW_MNTR_REG_END                           0x00434074
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_START                 0x00434100
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_END                   0x0043411c
+#define BCHP_AVS_ASB_REGISTERS_REG_START                   0x00434200
+#define BCHP_AVS_ASB_REGISTERS_REG_END                     0x00434218
+#define BCHP_AVS_RO_REGISTERS_0_REG_START                  0x00434300
+#define BCHP_AVS_RO_REGISTERS_0_REG_END                    0x004343dc
+#define BCHP_AVS_RO_REGISTERS_1_REG_START                  0x00434400
+#define BCHP_AVS_RO_REGISTERS_1_REG_END                    0x004344b4
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_START                0x00434500
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_END                  0x004345e4
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_START                0x00434600
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_END                  0x004346e4
+#define BCHP_CLKGEN_INTR2_REG_START                        0x00435000
+#define BCHP_CLKGEN_INTR2_REG_END                          0x00435044
+#define BCHP_UHFR_REG_START                                0x00438000
+#define BCHP_UHFR_REG_END                                  0x004380f8
+#define BCHP_UHFR_INTR2_REG_START                          0x00438200
+#define BCHP_UHFR_INTR2_REG_END                            0x0043822c
+#define BCHP_UHFR_GR_BRIDGE_REG_START                      0x00438300
+#define BCHP_UHFR_GR_BRIDGE_REG_END                        0x0043830c
+#define BCHP_USB_CAPS_REG_START                            0x00480000
+#define BCHP_USB_CAPS_REG_END                              0x0048002c
+#define BCHP_USB_GR_BRIDGE_REG_START                       0x00480100
+#define BCHP_USB_GR_BRIDGE_REG_END                         0x0048010c
+#define BCHP_USB_INTR2_REG_START                           0x00480180
+#define BCHP_USB_INTR2_REG_END                             0x004801ac
+#define BCHP_USB_CTRL_REG_START                            0x00480200
+#define BCHP_USB_CTRL_REG_END                              0x00480238
+#define BCHP_USB_EHCI_REG_START                            0x00480300
+#define BCHP_USB_EHCI_REG_END                              0x004803a4
+#define BCHP_USB_OHCI_REG_START                            0x00480400
+#define BCHP_USB_OHCI_REG_END                              0x00480454
+#define BCHP_USB_EHCI1_REG_START                           0x00480500
+#define BCHP_USB_EHCI1_REG_END                             0x004805a4
+#define BCHP_USB_OHCI1_REG_START                           0x00480600
+#define BCHP_USB_OHCI1_REG_END                             0x00480654
+#define BCHP_USB1_CAPS_REG_START                           0x00490000
+#define BCHP_USB1_CAPS_REG_END                             0x0049002c
+#define BCHP_USB1_GR_BRIDGE_REG_START                      0x00490100
+#define BCHP_USB1_GR_BRIDGE_REG_END                        0x0049010c
+#define BCHP_USB1_INTR2_REG_START                          0x00490180
+#define BCHP_USB1_INTR2_REG_END                            0x004901ac
+#define BCHP_USB1_CTRL_REG_START                           0x00490200
+#define BCHP_USB1_CTRL_REG_END                             0x00490238
+#define BCHP_USB1_EHCI_REG_START                           0x00490300
+#define BCHP_USB1_EHCI_REG_END                             0x004903a4
+#define BCHP_USB1_OHCI_REG_START                           0x00490400
+#define BCHP_USB1_OHCI_REG_END                             0x00490454
+#define BCHP_USB1_EHCI1_REG_START                          0x00490500
+#define BCHP_USB1_EHCI1_REG_END                            0x004905a4
+#define BCHP_USB1_OHCI1_REG_START                          0x00490600
+#define BCHP_USB1_OHCI1_REG_END                            0x00490654
+#define BCHP_BOOTROM_REG_START                             0x00500000
+#define BCHP_BOOTROM_REG_END                               0x00500ffc
+#define BCHP_MFD_0_REG_START                               0x00600000
+#define BCHP_MFD_0_REG_END                                 0x00600264
+#define BCHP_MFD_1_REG_START                               0x00600400
+#define BCHP_MFD_1_REG_END                                 0x006005fc
+#define BCHP_MFD_2_REG_START                               0x00600800
+#define BCHP_MFD_2_REG_END                                 0x006009fc
+#define BCHP_MFD_3_REG_START                               0x00600c00
+#define BCHP_MFD_3_REG_END                                 0x00600dfc
+#define BCHP_VFD_0_REG_START                               0x00601000
+#define BCHP_VFD_0_REG_END                                 0x006011fc
+#define BCHP_VFD_1_REG_START                               0x00601200
+#define BCHP_VFD_1_REG_END                                 0x006013fc
+#define BCHP_VFD_2_REG_START                               0x00601400
+#define BCHP_VFD_2_REG_END                                 0x006015fc
+#define BCHP_VFD_3_REG_START                               0x00601600
+#define BCHP_VFD_3_REG_END                                 0x006017fc
+#define BCHP_VFD_4_REG_START                               0x00601800
+#define BCHP_VFD_4_REG_END                                 0x006019fc
+#define BCHP_VFD_5_REG_START                               0x00601a00
+#define BCHP_VFD_5_REG_END                                 0x00601bfc
+#define BCHP_RDC_REG_START                                 0x00602000
+#define BCHP_RDC_REG_END                                   0x006029fc
+#define BCHP_BVNF_INTR2_0_REG_START                        0x00603000
+#define BCHP_BVNF_INTR2_0_REG_END                          0x0060302c
+#define BCHP_BVNF_INTR2_1_REG_START                        0x00603100
+#define BCHP_BVNF_INTR2_1_REG_END                          0x0060312c
+#define BCHP_BVNF_INTR2_3_REG_START                        0x00603300
+#define BCHP_BVNF_INTR2_3_REG_END                          0x0060332c
+#define BCHP_BVNF_INTR2_4_REG_START                        0x00603400
+#define BCHP_BVNF_INTR2_4_REG_END                          0x0060342c
+#define BCHP_BVNF_INTR2_5_REG_START                        0x00603500
+#define BCHP_BVNF_INTR2_5_REG_END                          0x0060352c
+#define BCHP_BVNF_INTR2_6_REG_START                        0x00603600
+#define BCHP_BVNF_INTR2_6_REG_END                          0x0060362c
+#define BCHP_BVNF_INTR2_7_REG_START                        0x00603700
+#define BCHP_BVNF_INTR2_7_REG_END                          0x0060372c
+#define BCHP_FMISC_REG_START                               0x00604000
+#define BCHP_FMISC_REG_END                                 0x00604020
+#define BCHP_SCL_0_REG_START                               0x00620000
+#define BCHP_SCL_0_REG_END                                 0x006203fc
+#define BCHP_SCL_1_REG_START                               0x00620400
+#define BCHP_SCL_1_REG_END                                 0x006207fc
+#define BCHP_SCL_2_REG_START                               0x00620800
+#define BCHP_SCL_2_REG_END                                 0x00620bfc
+#define BCHP_SCL_3_REG_START                               0x00620c00
+#define BCHP_SCL_3_REG_END                                 0x00620ffc
+#define BCHP_SCL_4_REG_START                               0x00621000
+#define BCHP_SCL_4_REG_END                                 0x006213fc
+#define BCHP_SCL_5_REG_START                               0x00621400
+#define BCHP_SCL_5_REG_END                                 0x006217fc
+#define BCHP_VNET_F_REG_START                              0x00622000
+#define BCHP_VNET_F_REG_END                                0x006221fc
+#define BCHP_VNET_B_REG_START                              0x00622200
+#define BCHP_VNET_B_REG_END                                0x006223fc
+#define BCHP_MMISC_REG_START                               0x00622800
+#define BCHP_MMISC_REG_END                                 0x00622820
+#define BCHP_LBOX_0_REG_START                              0x00624000
+#define BCHP_LBOX_0_REG_END                                0x00624070
+#define BCHP_LBOX_1_REG_START                              0x00624200
+#define BCHP_LBOX_1_REG_END                                0x00624270
+#define BCHP_LBOX_2_REG_START                              0x00624400
+#define BCHP_LBOX_2_REG_END                                0x00624470
+#define BCHP_LBOX_3_REG_START                              0x00624600
+#define BCHP_LBOX_3_REG_END                                0x00624670
+#define BCHP_DNR_0_REG_START                               0x00626000
+#define BCHP_DNR_0_REG_END                                 0x006260a4
+#define BCHP_DNR_1_REG_START                               0x00626200
+#define BCHP_DNR_1_REG_END                                 0x006262a4
+#define BCHP_DNR_2_REG_START                               0x00626400
+#define BCHP_DNR_2_REG_END                                 0x006264a4
+#define BCHP_DNR_3_REG_START                               0x00626600
+#define BCHP_DNR_3_REG_END                                 0x006266a4
+#define BCHP_BVNM_INTR2_0_REG_START                        0x00627000
+#define BCHP_BVNM_INTR2_0_REG_END                          0x0062702c
+#define BCHP_BVNM_INTR2_1_REG_START                        0x00627100
+#define BCHP_BVNM_INTR2_1_REG_END                          0x0062712c
+#define BCHP_CAP_0_REG_START                               0x00640000
+#define BCHP_CAP_0_REG_END                                 0x0064007c
+#define BCHP_CAP_1_REG_START                               0x00640200
+#define BCHP_CAP_1_REG_END                                 0x0064027c
+#define BCHP_CAP_2_REG_START                               0x00640400
+#define BCHP_CAP_2_REG_END                                 0x0064047c
+#define BCHP_CAP_3_REG_START                               0x00640600
+#define BCHP_CAP_3_REG_END                                 0x0064067c
+#define BCHP_CAP_4_REG_START                               0x00640800
+#define BCHP_CAP_4_REG_END                                 0x0064087c
+#define BCHP_CAP_5_REG_START                               0x00640a00
+#define BCHP_CAP_5_REG_END                                 0x00640a7c
+#define BCHP_GFD_0_REG_START                               0x00641000
+#define BCHP_GFD_0_REG_END                                 0x00641228
+#define BCHP_GFD_1_REG_START                               0x00641400
+#define BCHP_GFD_1_REG_END                                 0x00641554
+#define BCHP_GFD_2_REG_START                               0x00641800
+#define BCHP_GFD_2_REG_END                                 0x00641a28
+#define BCHP_GFD_3_REG_START                               0x00641c00
+#define BCHP_GFD_3_REG_END                                 0x00641e28
+#define BCHP_GFD_4_REG_START                               0x00642000
+#define BCHP_GFD_4_REG_END                                 0x00642228
+#define BCHP_GFD_5_REG_START                               0x00642400
+#define BCHP_GFD_5_REG_END                                 0x00642628
+#define BCHP_CMP_0_REG_START                               0x00643000
+#define BCHP_CMP_0_REG_END                                 0x006434b4
+#define BCHP_CMP_1_REG_START                               0x00643800
+#define BCHP_CMP_1_REG_END                                 0x00643cb4
+#define BCHP_CMP_2_REG_START                               0x00644000
+#define BCHP_CMP_2_REG_END                                 0x00644264
+#define BCHP_CMP_3_REG_START                               0x00644400
+#define BCHP_CMP_3_REG_END                                 0x00644664
+#define BCHP_CMP_4_REG_START                               0x00644800
+#define BCHP_CMP_4_REG_END                                 0x00644a64
+#define BCHP_CMP_5_REG_START                               0x00644c00
+#define BCHP_CMP_5_REG_END                                 0x00644e64
+#define BCHP_TNT_CMP_0_V0_REG_START                        0x00645000
+#define BCHP_TNT_CMP_0_V0_REG_END                          0x006450a4
+#define BCHP_MASK_0_REG_START                              0x00645400
+#define BCHP_MASK_0_REG_END                                0x00645420
+#define BCHP_PEP_CMP_0_V0_REG_START                        0x00646000
+#define BCHP_PEP_CMP_0_V0_REG_END                          0x00647484
+#define BCHP_BVNB_INTR2_REG_START                          0x00648000
+#define BCHP_BVNB_INTR2_REG_END                            0x0064802c
+#define BCHP_BMISC_REG_START                               0x00648400
+#define BCHP_BMISC_REG_END                                 0x0064841c
+#define BCHP_MVP_TOP_0_REG_START                           0x00660000
+#define BCHP_MVP_TOP_0_REG_END                             0x0066002c
+#define BCHP_SIOB_0_REG_START                              0x00660200
+#define BCHP_SIOB_0_REG_END                                0x006602fc
+#define BCHP_HSCL_0_REG_START                              0x00660400
+#define BCHP_HSCL_0_REG_END                                0x006607fc
+#define BCHP_HD_ANR_MCTF_0_REG_START                       0x00661000
+#define BCHP_HD_ANR_MCTF_0_REG_END                         0x0066127c
+#define BCHP_HD_ANR_AND_0_REG_START                        0x00661800
+#define BCHP_HD_ANR_AND_0_REG_END                          0x00661888
+#define BCHP_MDI_TOP_0_REG_START                           0x00662000
+#define BCHP_MDI_TOP_0_REG_END                             0x006620fc
+#define BCHP_MDI_FCB_0_REG_START                           0x00662400
+#define BCHP_MDI_FCB_0_REG_END                             0x006627fc
+#define BCHP_MDI_PPB_0_REG_START                           0x00662800
+#define BCHP_MDI_PPB_0_REG_END                             0x00662bfc
+#define BCHP_MDI_FCN_0_REG_START                           0x00662c00
+#define BCHP_MDI_FCN_0_REG_END                             0x00662ffc
+#define BCHP_MVP_TOP_1_REG_START                           0x00670000
+#define BCHP_MVP_TOP_1_REG_END                             0x0067002c
+#define BCHP_SIOB_1_REG_START                              0x00670200
+#define BCHP_SIOB_1_REG_END                                0x006702fc
+#define BCHP_HSCL_1_REG_START                              0x00670400
+#define BCHP_HSCL_1_REG_END                                0x006707fc
+#define BCHP_MDI_TOP_1_REG_START                           0x00672000
+#define BCHP_MDI_TOP_1_REG_END                             0x006720fc
+#define BCHP_MDI_PPB_1_REG_START                           0x00672800
+#define BCHP_MDI_PPB_1_REG_END                             0x00672bfc
+#define BCHP_MDI_FCN_1_REG_START                           0x00672c00
+#define BCHP_MDI_FCN_1_REG_END                             0x00672ffc
+#define BCHP_MVP_TOP_2_REG_START                           0x00680000
+#define BCHP_MVP_TOP_2_REG_END                             0x0068002c
+#define BCHP_SIOB_2_REG_START                              0x00680200
+#define BCHP_SIOB_2_REG_END                                0x006802fc
+#define BCHP_HSCL_2_REG_START                              0x00680400
+#define BCHP_HSCL_2_REG_END                                0x006807fc
+#define BCHP_MDI_TOP_2_REG_START                           0x00682000
+#define BCHP_MDI_TOP_2_REG_END                             0x006820fc
+#define BCHP_MDI_PPB_2_REG_START                           0x00682800
+#define BCHP_MDI_PPB_2_REG_END                             0x00682bfc
+#define BCHP_MDI_FCN_2_REG_START                           0x00682c00
+#define BCHP_MDI_FCN_2_REG_END                             0x00682ffc
+#define BCHP_MVP_TOP_3_REG_START                           0x00690000
+#define BCHP_MVP_TOP_3_REG_END                             0x0069002c
+#define BCHP_SIOB_3_REG_START                              0x00690200
+#define BCHP_SIOB_3_REG_END                                0x006902fc
+#define BCHP_HSCL_3_REG_START                              0x00690400
+#define BCHP_HSCL_3_REG_END                                0x006907fc
+#define BCHP_MDI_TOP_3_REG_START                           0x00692000
+#define BCHP_MDI_TOP_3_REG_END                             0x006920fc
+#define BCHP_MDI_PPB_3_REG_START                           0x00692800
+#define BCHP_MDI_PPB_3_REG_END                             0x00692bfc
+#define BCHP_MDI_FCN_3_REG_START                           0x00692c00
+#define BCHP_MDI_FCN_3_REG_END                             0x00692ffc
+#define BCHP_MVP_TOP_4_REG_START                           0x006a0000
+#define BCHP_MVP_TOP_4_REG_END                             0x006a002c
+#define BCHP_SIOB_4_REG_START                              0x006a0200
+#define BCHP_SIOB_4_REG_END                                0x006a02fc
+#define BCHP_HSCL_4_REG_START                              0x006a0400
+#define BCHP_HSCL_4_REG_END                                0x006a07fc
+#define BCHP_MDI_TOP_4_REG_START                           0x006a2000
+#define BCHP_MDI_TOP_4_REG_END                             0x006a20fc
+#define BCHP_MDI_PPB_4_REG_START                           0x006a2800
+#define BCHP_MDI_PPB_4_REG_END                             0x006a2bfc
+#define BCHP_MDI_FCN_4_REG_START                           0x006a2c00
+#define BCHP_MDI_FCN_4_REG_END                             0x006a2ffc
+#define BCHP_MISC_REG_START                                0x006b0000
+#define BCHP_MISC_REG_END                                  0x006b00a8
+#define BCHP_IT_0_REG_START                                0x006b1000
+#define BCHP_IT_0_REG_END                                  0x006b17fc
+#define BCHP_IT_1_REG_START                                0x006b2000
+#define BCHP_IT_1_REG_END                                  0x006b27fc
+#define BCHP_VF_0_REG_START                                0x006b3000
+#define BCHP_VF_0_REG_END                                  0x006b3134
+#define BCHP_VF_1_REG_START                                0x006b3200
+#define BCHP_VF_1_REG_END                                  0x006b3334
+#define BCHP_SECAM_0_REG_START                             0x006b3400
+#define BCHP_SECAM_0_REG_END                               0x006b3414
+#define BCHP_SM_0_REG_START                                0x006b3480
+#define BCHP_SM_0_REG_END                                  0x006b34ac
+#define BCHP_SDSRC_0_REG_START                             0x006b3500
+#define BCHP_SDSRC_0_REG_END                               0x006b350c
+#define BCHP_HDSRC_0_REG_START                             0x006b3520
+#define BCHP_HDSRC_0_REG_END                               0x006b353c
+#define BCHP_CSC_0_REG_START                               0x006b3580
+#define BCHP_CSC_0_REG_END                                 0x006b35b0
+#define BCHP_CSC_1_REG_START                               0x006b3600
+#define BCHP_CSC_1_REG_END                                 0x006b3630
+#define BCHP_RM_0_REG_START                                0x006b3680
+#define BCHP_RM_0_REG_END                                  0x006b36a4
+#define BCHP_RM_1_REG_START                                0x006b36c0
+#define BCHP_RM_1_REG_END                                  0x006b36e4
+#define BCHP_ANA_DEBUG_0_REG_START                         0x006b3700
+#define BCHP_ANA_DEBUG_0_REG_END                           0x006b3744
+#define BCHP_DTRAM_0_REG_START                             0x006b3800
+#define BCHP_DTRAM_0_REG_END                               0x006b3c7c
+#define BCHP_DVI_DTG_0_REG_START                           0x006b4000
+#define BCHP_DVI_DTG_0_REG_END                             0x006b4178
+#define BCHP_DVI_DTG_RM_0_REG_START                        0x006b4800
+#define BCHP_DVI_DTG_RM_0_REG_END                          0x006b4824
+#define BCHP_DVI_CSC_0_REG_START                           0x006b4900
+#define BCHP_DVI_CSC_0_REG_END                             0x006b4930
+#define BCHP_DVI_DVF_0_REG_START                           0x006b4a00
+#define BCHP_DVI_DVF_0_REG_END                             0x006b4a18
+#define BCHP_DVI_DEBUG_0_REG_START                         0x006b4b00
+#define BCHP_DVI_DEBUG_0_REG_END                           0x006b4b44
+#define BCHP_ITU656_DTG_0_REG_START                        0x006b5000
+#define BCHP_ITU656_DTG_0_REG_END                          0x006b5178
+#define BCHP_ITU656_CSC_0_REG_START                        0x006b5200
+#define BCHP_ITU656_CSC_0_REG_END                          0x006b5230
+#define BCHP_ITU656_DVF_0_REG_START                        0x006b5300
+#define BCHP_ITU656_DVF_0_REG_END                          0x006b5318
+#define BCHP_ITU656_0_REG_START                            0x006b5400
+#define BCHP_ITU656_0_REG_END                              0x006b5420
+#define BCHP_ITU656_DTG_1_REG_START                        0x006b5800
+#define BCHP_ITU656_DTG_1_REG_END                          0x006b5978
+#define BCHP_ITU656_CSC_1_REG_START                        0x006b5a00
+#define BCHP_ITU656_CSC_1_REG_END                          0x006b5a30
+#define BCHP_ITU656_DVF_1_REG_START                        0x006b5b00
+#define BCHP_ITU656_DVF_1_REG_END                          0x006b5b18
+#define BCHP_ITU656_1_REG_START                            0x006b5c00
+#define BCHP_ITU656_1_REG_END                              0x006b5c20
+#define BCHP_VEC_CFG_REG_START                             0x006b6000
+#define BCHP_VEC_CFG_REG_END                               0x006b61b4
+#define BCHP_VIDEO_ENC_INTR2_REG_START                     0x006b6400
+#define BCHP_VIDEO_ENC_INTR2_REG_END                       0x006b642c
+#define BCHP_VIDEO_ENC_TPG_0_REG_START                     0x006b6500
+#define BCHP_VIDEO_ENC_TPG_0_REG_END                       0x006b6518
+#define BCHP_VIDEO_ENC_STG_0_REG_START                     0x006b6600
+#define BCHP_VIDEO_ENC_STG_0_REG_END                       0x006b6648
+#define BCHP_VIDEO_ENC_STG_1_REG_START                     0x006b6700
+#define BCHP_VIDEO_ENC_STG_1_REG_END                       0x006b6748
+#define BCHP_VIDEO_ENC_STG_2_REG_START                     0x006b6800
+#define BCHP_VIDEO_ENC_STG_2_REG_END                       0x006b6848
+#define BCHP_VIDEO_ENC_STG_3_REG_START                     0x006b6900
+#define BCHP_VIDEO_ENC_STG_3_REG_END                       0x006b6948
+#define BCHP_DSCL_0_REG_START                              0x006b7000
+#define BCHP_DSCL_0_REG_END                                0x006b73fc
+#define BCHP_VIDEO_ENC_DECIM_0_REG_START                   0x006b7800
+#define BCHP_VIDEO_ENC_DECIM_0_REG_END                     0x006b7808
+#define BCHP_DVP_TVG_0_REG_START                           0x006b7900
+#define BCHP_DVP_TVG_0_REG_END                             0x006b7988
+#define BCHP_VBI_ENC_REG_START                             0x006b8000
+#define BCHP_VBI_ENC_REG_END                               0x006b8094
+#define BCHP_CCE_0_REG_START                               0x006b8400
+#define BCHP_CCE_0_REG_END                                 0x006b8458
+#define BCHP_CCE_1_REG_START                               0x006b8500
+#define BCHP_CCE_1_REG_END                                 0x006b8558
+#define BCHP_WSE_0_REG_START                               0x006b8600
+#define BCHP_WSE_0_REG_END                                 0x006b8614
+#define BCHP_WSE_1_REG_START                               0x006b8700
+#define BCHP_WSE_1_REG_END                                 0x006b8714
+#define BCHP_CGMSAE_0_REG_START                            0x006b8800
+#define BCHP_CGMSAE_0_REG_END                              0x006b8858
+#define BCHP_CGMSAE_1_REG_START                            0x006b8900
+#define BCHP_CGMSAE_1_REG_END                              0x006b8958
+#define BCHP_TTE_0_REG_START                               0x006b8a00
+#define BCHP_TTE_0_REG_END                                 0x006b8a28
+#define BCHP_TTE_1_REG_START                               0x006b8b00
+#define BCHP_TTE_1_REG_END                                 0x006b8b28
+#define BCHP_GSE_0_REG_START                               0x006b8c00
+#define BCHP_GSE_0_REG_END                                 0x006b8c80
+#define BCHP_GSE_1_REG_START                               0x006b8d00
+#define BCHP_GSE_1_REG_END                                 0x006b8d80
+#define BCHP_AMOLE_0_REG_START                             0x006b8e00
+#define BCHP_AMOLE_0_REG_END                               0x006b8e8c
+#define BCHP_AMOLE_1_REG_START                             0x006b8f00
+#define BCHP_AMOLE_1_REG_END                               0x006b8f8c
+#define BCHP_CCE_ANCIL_0_REG_START                         0x006b9000
+#define BCHP_CCE_ANCIL_0_REG_END                           0x006b9054
+#define BCHP_CCE_ANCIL_1_REG_START                         0x006b9100
+#define BCHP_CCE_ANCIL_1_REG_END                           0x006b9154
+#define BCHP_WSE_ANCIL_0_REG_START                         0x006b9200
+#define BCHP_WSE_ANCIL_0_REG_END                           0x006b920c
+#define BCHP_WSE_ANCIL_1_REG_START                         0x006b9300
+#define BCHP_WSE_ANCIL_1_REG_END                           0x006b930c
+#define BCHP_TTE_ANCIL_0_REG_START                         0x006b9400
+#define BCHP_TTE_ANCIL_0_REG_END                           0x006b9428
+#define BCHP_TTE_ANCIL_1_REG_START                         0x006b9500
+#define BCHP_TTE_ANCIL_1_REG_END                           0x006b9528
+#define BCHP_GSE_ANCIL_0_REG_START                         0x006b9600
+#define BCHP_GSE_ANCIL_0_REG_END                           0x006b9680
+#define BCHP_GSE_ANCIL_1_REG_START                         0x006b9700
+#define BCHP_GSE_ANCIL_1_REG_END                           0x006b9780
+#define BCHP_AMOLE_ANCIL_0_REG_START                       0x006b9800
+#define BCHP_AMOLE_ANCIL_0_REG_END                         0x006b988c
+#define BCHP_AMOLE_ANCIL_1_REG_START                       0x006b9900
+#define BCHP_AMOLE_ANCIL_1_REG_END                         0x006b998c
+#define BCHP_ANCI656_ANCIL_0_REG_START                     0x006b9a00
+#define BCHP_ANCI656_ANCIL_0_REG_END                       0x006b9a24
+#define BCHP_ANCI656_ANCIL_1_REG_START                     0x006b9b00
+#define BCHP_ANCI656_ANCIL_1_REG_END                       0x006b9b24
+#define BCHP_DVP_HT_REG_START                              0x006c0000
+#define BCHP_DVP_HT_REG_END                                0x006c0114
+#define BCHP_HDMI_REG_START                                0x006c0800
+#define BCHP_HDMI_REG_END                                  0x006c0994
+#define BCHP_HDMI_TX_PHY_REG_START                         0x006c0a80
+#define BCHP_HDMI_TX_PHY_REG_END                           0x006c0ad8
+#define BCHP_HDMI_RM_REG_START                             0x006c0b00
+#define BCHP_HDMI_RM_REG_END                               0x006c0b2c
+#define BCHP_HDMI_TX_INTR2_REG_START                       0x006c0b40
+#define BCHP_HDMI_TX_INTR2_REG_END                         0x006c0b6c
+#define BCHP_HDMI_RAM_REG_START                            0x006c0c00
+#define BCHP_HDMI_RAM_REG_END                              0x006c0dfc
+#define BCHP_DVP_HR_REG_START                              0x006c6000
+#define BCHP_DVP_HR_REG_END                                0x006c61bc
+#define BCHP_DVP_HR_INTR2_REG_START                        0x006c61c0
+#define BCHP_DVP_HR_INTR2_REG_END                          0x006c61ec
+#define BCHP_DVP_HR_KEY_RAM_REG_START                      0x006c6300
+#define BCHP_DVP_HR_KEY_RAM_REG_END                        0x006c6314
+#define BCHP_HDMI_RX_FE_0_REG_START                        0x006c6400
+#define BCHP_HDMI_RX_FE_0_REG_END                          0x006c65fc
+#define BCHP_HDMI_RX_EQ_0_REG_START                        0x006c6600
+#define BCHP_HDMI_RX_EQ_0_REG_END                          0x006c67fc
+#define BCHP_HDMI_RX_0_REG_START                           0x006c8000
+#define BCHP_HDMI_RX_0_REG_END                             0x006c87bc
+#define BCHP_HDMI_RX_INTR2_0_REG_START                     0x006c87c0
+#define BCHP_HDMI_RX_INTR2_0_REG_END                       0x006c87ec
+#define BCHP_HD_DVI_0_REG_START                            0x006ca000
+#define BCHP_HD_DVI_0_REG_END                              0x006ca1fc
+#define BCHP_DVP_HR_TMR_REG_START                          0x006cacc0
+#define BCHP_DVP_HR_TMR_REG_END                            0x006cacfc
+#define BCHP_BVN_RGR_REG_START                             0x006ce000
+#define BCHP_BVN_RGR_REG_END                               0x006ce010
+#define BCHP_VICE2_CME_0_0_REG_START                       0x00700800
+#define BCHP_VICE2_CME_0_0_REG_END                         0x0070089c
+#define BCHP_VICE2_FME_0_0_REG_START                       0x00700c00
+#define BCHP_VICE2_FME_0_0_REG_END                         0x00700c80
+#define BCHP_VICE2_MC_0_0_REG_START                        0x00701000
+#define BCHP_VICE2_MC_0_0_REG_END                          0x00701080
+#define BCHP_VICE2_MAU_0_0_REG_START                       0x00701400
+#define BCHP_VICE2_MAU_0_0_REG_END                         0x007014f4
+#define BCHP_VICE2_IMD_0_0_REG_START                       0x00701800
+#define BCHP_VICE2_IMD_0_0_REG_END                         0x0070187c
+#define BCHP_VICE2_CABAC_0_0_REG_START                     0x00701c00
+#define BCHP_VICE2_CABAC_0_0_REG_END                       0x00701cec
+#define BCHP_VICE2_HA_0_0_REG_START                        0x00702000
+#define BCHP_VICE2_HA_0_0_REG_END                          0x00702088
+#define BCHP_VICE2_SG_0_0_REG_START                        0x00702400
+#define BCHP_VICE2_SG_0_0_REG_END                          0x00702474
+#define BCHP_VICE2_DBLK_0_0_REG_START                      0x00702800
+#define BCHP_VICE2_DBLK_0_0_REG_END                        0x00702888
+#define BCHP_VICE2_VIP_0_0_REG_START                       0x00703000
+#define BCHP_VICE2_VIP_0_0_REG_END                         0x00703224
+#define BCHP_VICE2_VIP1_0_0_REG_START                      0x00703800
+#define BCHP_VICE2_VIP1_0_0_REG_END                        0x00703a24
+#define BCHP_VICE2_XQ_0_0_REG_START                        0x00704000
+#define BCHP_VICE2_XQ_0_0_REG_END                          0x00706198
+#define BCHP_VICE2_ARCSS_ESS_CTRL_0_0_REG_START            0x00710000
+#define BCHP_VICE2_ARCSS_ESS_CTRL_0_0_REG_END              0x007100a0
+#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_0_0_REG_START      0x00710400
+#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_0_0_REG_END        0x0071042c
+#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_0_0_REG_START        0x00710600
+#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_0_0_REG_END          0x0071062c
+#define BCHP_VICE2_ARCSS_ESS_HOSTIF_0_0_REG_START          0x00712000
+#define BCHP_VICE2_ARCSS_ESS_HOSTIF_0_0_REG_END            0x007133fc
+#define BCHP_VICE2_ARCSS_ESS_DCCM_0_0_REG_START            0x00714000
+#define BCHP_VICE2_ARCSS_ESS_DCCM_0_0_REG_END              0x00717ffc
+#define BCHP_VICE2_ARCSS_ESS_ADI_0_0_REG_START             0x00718000
+#define BCHP_VICE2_ARCSS_ESS_ADI_0_0_REG_END               0x007182ac
+#define BCHP_VICE2_ARCSS_ESS_CTRL_1_0_REG_START            0x00750000
+#define BCHP_VICE2_ARCSS_ESS_CTRL_1_0_REG_END              0x007500a0
+#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_1_0_REG_START      0x00750400
+#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_1_0_REG_END        0x0075042c
+#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_1_0_REG_START        0x00750600
+#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_1_0_REG_END          0x0075062c
+#define BCHP_VICE2_ARCSS_ESS_HOSTIF_1_0_REG_START          0x00752000
+#define BCHP_VICE2_ARCSS_ESS_HOSTIF_1_0_REG_END            0x007533fc
+#define BCHP_VICE2_ARCSS_ESS_DCCM_1_0_REG_START            0x00754000
+#define BCHP_VICE2_ARCSS_ESS_DCCM_1_0_REG_END              0x00757ffc
+#define BCHP_VICE2_ARCSS_ESS_ADI_1_0_REG_START             0x00758000
+#define BCHP_VICE2_ARCSS_ESS_ADI_1_0_REG_END               0x007582a4
+#define BCHP_VICE2_RGR_0_REG_START                         0x00780000
+#define BCHP_VICE2_RGR_0_REG_END                           0x0078000c
+#define BCHP_VICE2_MISC_0_REG_START                        0x00781000
+#define BCHP_VICE2_MISC_0_REG_END                          0x00781020
+#define BCHP_VICE2_L2_0_REG_START                          0x00781100
+#define BCHP_VICE2_L2_0_REG_END                            0x0078112c
+#define BCHP_VICE2_ARCSS_MISC_0_REG_START                  0x00782000
+#define BCHP_VICE2_ARCSS_MISC_0_REG_END                    0x00782030
+#define BCHP_VICE2_CME_0_1_REG_START                       0x00800800
+#define BCHP_VICE2_CME_0_1_REG_END                         0x0080089c
+#define BCHP_VICE2_FME_0_1_REG_START                       0x00800c00
+#define BCHP_VICE2_FME_0_1_REG_END                         0x00800c80
+#define BCHP_VICE2_MC_0_1_REG_START                        0x00801000
+#define BCHP_VICE2_MC_0_1_REG_END                          0x00801080
+#define BCHP_VICE2_MAU_0_1_REG_START                       0x00801400
+#define BCHP_VICE2_MAU_0_1_REG_END                         0x008014f4
+#define BCHP_VICE2_IMD_0_1_REG_START                       0x00801800
+#define BCHP_VICE2_IMD_0_1_REG_END                         0x0080187c
+#define BCHP_VICE2_CABAC_0_1_REG_START                     0x00801c00
+#define BCHP_VICE2_CABAC_0_1_REG_END                       0x00801cec
+#define BCHP_VICE2_HA_0_1_REG_START                        0x00802000
+#define BCHP_VICE2_HA_0_1_REG_END                          0x00802088
+#define BCHP_VICE2_SG_0_1_REG_START                        0x00802400
+#define BCHP_VICE2_SG_0_1_REG_END                          0x00802474
+#define BCHP_VICE2_DBLK_0_1_REG_START                      0x00802800
+#define BCHP_VICE2_DBLK_0_1_REG_END                        0x00802888
+#define BCHP_VICE2_VIP_0_1_REG_START                       0x00803000
+#define BCHP_VICE2_VIP_0_1_REG_END                         0x00803224
+#define BCHP_VICE2_VIP1_0_1_REG_START                      0x00803800
+#define BCHP_VICE2_VIP1_0_1_REG_END                        0x00803a24
+#define BCHP_VICE2_XQ_0_1_REG_START                        0x00804000
+#define BCHP_VICE2_XQ_0_1_REG_END                          0x00806198
+#define BCHP_VICE2_ARCSS_ESS_CTRL_0_1_REG_START            0x00810000
+#define BCHP_VICE2_ARCSS_ESS_CTRL_0_1_REG_END              0x008100a0
+#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_0_1_REG_START      0x00810400
+#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_0_1_REG_END        0x0081042c
+#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_0_1_REG_START        0x00810600
+#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_0_1_REG_END          0x0081062c
+#define BCHP_VICE2_ARCSS_ESS_HOSTIF_0_1_REG_START          0x00812000
+#define BCHP_VICE2_ARCSS_ESS_HOSTIF_0_1_REG_END            0x008133fc
+#define BCHP_VICE2_ARCSS_ESS_DCCM_0_1_REG_START            0x00814000
+#define BCHP_VICE2_ARCSS_ESS_DCCM_0_1_REG_END              0x00817ffc
+#define BCHP_VICE2_ARCSS_ESS_ADI_0_1_REG_START             0x00818000
+#define BCHP_VICE2_ARCSS_ESS_ADI_0_1_REG_END               0x008182ac
+#define BCHP_VICE2_ARCSS_ESS_CTRL_1_1_REG_START            0x00850000
+#define BCHP_VICE2_ARCSS_ESS_CTRL_1_1_REG_END              0x008500a0
+#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_1_1_REG_START      0x00850400
+#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_1_1_REG_END        0x0085042c
+#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_1_1_REG_START        0x00850600
+#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_1_1_REG_END          0x0085062c
+#define BCHP_VICE2_ARCSS_ESS_HOSTIF_1_1_REG_START          0x00852000
+#define BCHP_VICE2_ARCSS_ESS_HOSTIF_1_1_REG_END            0x008533fc
+#define BCHP_VICE2_ARCSS_ESS_DCCM_1_1_REG_START            0x00854000
+#define BCHP_VICE2_ARCSS_ESS_DCCM_1_1_REG_END              0x00857ffc
+#define BCHP_VICE2_ARCSS_ESS_ADI_1_1_REG_START             0x00858000
+#define BCHP_VICE2_ARCSS_ESS_ADI_1_1_REG_END               0x008582a4
+#define BCHP_VICE2_RGR_1_REG_START                         0x00880000
+#define BCHP_VICE2_RGR_1_REG_END                           0x0088000c
+#define BCHP_VICE2_MISC_1_REG_START                        0x00881000
+#define BCHP_VICE2_MISC_1_REG_END                          0x00881020
+#define BCHP_VICE2_L2_1_REG_START                          0x00881100
+#define BCHP_VICE2_L2_1_REG_END                            0x0088112c
+#define BCHP_VICE2_ARCSS_MISC_1_REG_START                  0x00882000
+#define BCHP_VICE2_ARCSS_MISC_1_REG_END                    0x00882030
+#define BCHP_VICE2_SEC_CTRL_0_REG_START                    0x00900000
+#define BCHP_VICE2_SEC_CTRL_0_REG_END                      0x00900080
+#define BCHP_VICE2_SEC_CTRL_1_REG_START                    0x00901000
+#define BCHP_VICE2_SEC_CTRL_1_REG_END                      0x00901080
+#define BCHP_XPT_BUS_IF_REG_START                          0x00940000
+#define BCHP_XPT_BUS_IF_REG_END                            0x00940078
+#define BCHP_XPT_XMEMIF_REG_START                          0x00940100
+#define BCHP_XPT_XMEMIF_REG_END                            0x009401c4
+#define BCHP_XPT_PMU_REG_START                             0x00940200
+#define BCHP_XPT_PMU_REG_END                               0x00940214
+#define BCHP_XPT_GR_REG_START                              0x00940300
+#define BCHP_XPT_GR_REG_END                                0x0094030c
+#define BCHP_XPT_RMX0_IO_REG_START                         0x00940400
+#define BCHP_XPT_RMX0_IO_REG_END                           0x00940420
+#define BCHP_XPT_RMX1_IO_REG_START                         0x00940500
+#define BCHP_XPT_RMX1_IO_REG_END                           0x00940520
+#define BCHP_XPT_WAKEUP_REG_START                          0x00941000
+#define BCHP_XPT_WAKEUP_REG_END                            0x00941fbc
+#define BCHP_XPT_FE_REG_START                              0x00944000
+#define BCHP_XPT_FE_REG_END                                0x009457fc
+#define BCHP_XPT_DPCR0_REG_START                           0x00947000
+#define BCHP_XPT_DPCR0_REG_END                             0x00947074
+#define BCHP_XPT_DPCR1_REG_START                           0x00947080
+#define BCHP_XPT_DPCR1_REG_END                             0x009470f4
+#define BCHP_XPT_DPCR2_REG_START                           0x00947100
+#define BCHP_XPT_DPCR2_REG_END                             0x00947174
+#define BCHP_XPT_DPCR3_REG_START                           0x00947180
+#define BCHP_XPT_DPCR3_REG_END                             0x009471f4
+#define BCHP_XPT_DPCR4_REG_START                           0x00947200
+#define BCHP_XPT_DPCR4_REG_END                             0x00947274
+#define BCHP_XPT_DPCR5_REG_START                           0x00947280
+#define BCHP_XPT_DPCR5_REG_END                             0x009472f4
+#define BCHP_XPT_DPCR6_REG_START                           0x00947300
+#define BCHP_XPT_DPCR6_REG_END                             0x00947374
+#define BCHP_XPT_DPCR7_REG_START                           0x00947380
+#define BCHP_XPT_DPCR7_REG_END                             0x009473f4
+#define BCHP_XPT_DPCR8_REG_START                           0x00947400
+#define BCHP_XPT_DPCR8_REG_END                             0x00947474
+#define BCHP_XPT_DPCR9_REG_START                           0x00947480
+#define BCHP_XPT_DPCR9_REG_END                             0x009474f4
+#define BCHP_XPT_DPCR_PP_REG_START                         0x00947800
+#define BCHP_XPT_DPCR_PP_REG_END                           0x00947804
+#define BCHP_XPT_PSUB_REG_START                            0x00947a00
+#define BCHP_XPT_PSUB_REG_END                              0x00947b88
+#define BCHP_XPT_MPOD_REG_START                            0x00947c00
+#define BCHP_XPT_MPOD_REG_END                              0x00947c20
+#define BCHP_XPT_RMX0_REG_START                            0x00947d00
+#define BCHP_XPT_RMX0_REG_END                              0x00947d08
+#define BCHP_XPT_RMX1_REG_START                            0x00947e00
+#define BCHP_XPT_RMX1_REG_END                              0x00947e08
+#define BCHP_XPT_PB_TOP_REG_START                          0x00948000
+#define BCHP_XPT_PB_TOP_REG_END                            0x009480b4
+#define BCHP_XPT_PB0_REG_START                             0x00948100
+#define BCHP_XPT_PB0_REG_END                               0x00948174
+#define BCHP_XPT_PB1_REG_START                             0x00948180
+#define BCHP_XPT_PB1_REG_END                               0x009481f4
+#define BCHP_XPT_PB2_REG_START                             0x00948200
+#define BCHP_XPT_PB2_REG_END                               0x00948274
+#define BCHP_XPT_PB3_REG_START                             0x00948280
+#define BCHP_XPT_PB3_REG_END                               0x009482f4
+#define BCHP_XPT_PB4_REG_START                             0x00948300
+#define BCHP_XPT_PB4_REG_END                               0x00948374
+#define BCHP_XPT_PB5_REG_START                             0x00948380
+#define BCHP_XPT_PB5_REG_END                               0x009483f4
+#define BCHP_XPT_PB6_REG_START                             0x00948400
+#define BCHP_XPT_PB6_REG_END                               0x00948474
+#define BCHP_XPT_PB7_REG_START                             0x00948480
+#define BCHP_XPT_PB7_REG_END                               0x009484f4
+#define BCHP_XPT_PB8_REG_START                             0x00948500
+#define BCHP_XPT_PB8_REG_END                               0x00948574
+#define BCHP_XPT_PB9_REG_START                             0x00948580
+#define BCHP_XPT_PB9_REG_END                               0x009485f4
+#define BCHP_XPT_PB10_REG_START                            0x00948600
+#define BCHP_XPT_PB10_REG_END                              0x00948674
+#define BCHP_XPT_PB11_REG_START                            0x00948680
+#define BCHP_XPT_PB11_REG_END                              0x009486f4
+#define BCHP_XPT_PB12_REG_START                            0x00948700
+#define BCHP_XPT_PB12_REG_END                              0x00948774
+#define BCHP_XPT_PB13_REG_START                            0x00948780
+#define BCHP_XPT_PB13_REG_END                              0x009487f4
+#define BCHP_XPT_PB14_REG_START                            0x00948800
+#define BCHP_XPT_PB14_REG_END                              0x00948874
+#define BCHP_XPT_PB15_REG_START                            0x00948880
+#define BCHP_XPT_PB15_REG_END                              0x009488f4
+#define BCHP_XPT_PB16_REG_START                            0x00948900
+#define BCHP_XPT_PB16_REG_END                              0x00948974
+#define BCHP_XPT_PB17_REG_START                            0x00948980
+#define BCHP_XPT_PB17_REG_END                              0x009489f4
+#define BCHP_XPT_PB18_REG_START                            0x00948a00
+#define BCHP_XPT_PB18_REG_END                              0x00948a74
+#define BCHP_XPT_PB19_REG_START                            0x00948a80
+#define BCHP_XPT_PB19_REG_END                              0x00948af4
+#define BCHP_XPT_PB20_REG_START                            0x00948b00
+#define BCHP_XPT_PB20_REG_END                              0x00948b74
+#define BCHP_XPT_PB21_REG_START                            0x00948b80
+#define BCHP_XPT_PB21_REG_END                              0x00948bf4
+#define BCHP_XPT_PCROFFSET_REG_START                       0x0094c000
+#define BCHP_XPT_PCROFFSET_REG_END                         0x0094d8fc
+#define BCHP_XPT_FULL_PID_PARSER_REG_START                 0x00950000
+#define BCHP_XPT_FULL_PID_PARSER_REG_END                   0x00952050
+#define BCHP_XPT_RSBUFF_REG_START                          0x00955000
+#define BCHP_XPT_RSBUFF_REG_END                            0x00955b44
+#define BCHP_XPT_XCBUFF_REG_START                          0x00956000
+#define BCHP_XPT_XCBUFF_REG_END                            0x00957ccc
+#define BCHP_XPT_MSG_REG_START                             0x00958000
+#define BCHP_XPT_MSG_REG_END                               0x0095e014
+#define BCHP_XPT_RAVE_REG_START                            0x00960000
+#define BCHP_XPT_RAVE_REG_END                              0x0096c96c
+#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_0_31_REG_START       0x0096ff80
+#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_0_31_REG_END         0x0096ffac
+#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_32_47_REG_START      0x0096ffc0
+#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_32_47_REG_END        0x0096ffec
+#define BCHP_XPT_XPU_REG_START                             0x00970000
+#define BCHP_XPT_XPU_REG_END                               0x009747fc
+#define BCHP_XPT_SECURE_BUS_IF_REG_START                   0x0097f000
+#define BCHP_XPT_SECURE_BUS_IF_REG_END                     0x0097f000
+#define BCHP_DECODE_RBNODE_REGS_0_REG_START                0x00a00000
+#define BCHP_DECODE_RBNODE_REGS_0_REG_END                  0x00a0007c
+#define BCHP_DECODE_MAIN_0_REG_START                       0x00a00100
+#define BCHP_DECODE_MAIN_0_REG_END                         0x00a001fc
+#define BCHP_SDRAM_DEBUG_0_REG_START                       0x00a00200
+#define BCHP_SDRAM_DEBUG_0_REG_END                         0x00a0027c
+#define BCHP_DECODE_MCOM_0_REG_START                       0x00a00300
+#define BCHP_DECODE_MCOM_0_REG_END                         0x00a0031c
+#define BCHP_DECODE_SPRE_0_REG_START                       0x00a00320
+#define BCHP_DECODE_SPRE_0_REG_END                         0x00a0033c
+#define BCHP_DECODE_WPRD_0_REG_START                       0x00a00340
+#define BCHP_DECODE_WPRD_0_REG_END                         0x00a0035c
+#define BCHP_DECODE_DQNT_0_REG_START                       0x00a00400
+#define BCHP_DECODE_DQNT_0_REG_END                         0x00a0045c
+#define BCHP_DECODE_DQNT_8X8_0_REG_START                   0x00a00500
+#define BCHP_DECODE_DQNT_8X8_0_REG_END                     0x00a0057c
+#define BCHP_DECODE_VP8_XFRM_0_REG_START                   0x00a00600
+#define BCHP_DECODE_VP8_XFRM_0_REG_END                     0x00a0060c
+#define BCHP_DECODE_VP6_DCP_0_REG_START                    0x00a00620
+#define BCHP_DECODE_VP6_DCP_0_REG_END                      0x00a0062c
+#define BCHP_DECODE_XFRM_0_REG_START                       0x00a00700
+#define BCHP_DECODE_XFRM_0_REG_END                         0x00a0071c
+#define BCHP_DECODE_DBLK_0_REG_START                       0x00a00720
+#define BCHP_DECODE_DBLK_0_REG_END                         0x00a0073c
+#define BCHP_DECODE_MB_0_REG_START                         0x00a00740
+#define BCHP_DECODE_MB_0_REG_END                           0x00a0075c
+#define BCHP_REG_CABAC2BINS_0_REG_START                    0x00a00b00
+#define BCHP_REG_CABAC2BINS_0_REG_END                      0x00a00bfc
+#define BCHP_DECODE_SINT_0_REG_START                       0x00a00c00
+#define BCHP_DECODE_SINT_0_REG_END                         0x00a00dfc
+#define BCHP_DECODE_RVC_0_REG_START                        0x00a00e00
+#define BCHP_DECODE_RVC_0_REG_END                          0x00a00efc
+#define BCHP_DECODE_CPUREGS_0_REG_START                    0x00a00f00
+#define BCHP_DECODE_CPUREGS_0_REG_END                      0x00a00f7c
+#define BCHP_DECODE_CPUREGS2_0_REG_START                   0x00a00f80
+#define BCHP_DECODE_CPUREGS2_0_REG_END                     0x00a00ffc
+#define BCHP_DECODE_CPUDMA_0_REG_START                     0x00a01800
+#define BCHP_DECODE_CPUDMA_0_REG_END                       0x00a018fc
+#define BCHP_DECODE_DMAMEM_0_REG_START                     0x00a01a00
+#define BCHP_DECODE_DMAMEM_0_REG_END                       0x00a021fc
+#define BCHP_REG_CABAC2BINS2_0_REG_START                   0x00a02400
+#define BCHP_REG_CABAC2BINS2_0_REG_END                     0x00a027fc
+#define BCHP_DECODE_WPTBL_0_REG_START                      0x00a03000
+#define BCHP_DECODE_WPTBL_0_REG_END                        0x00a031fc
+#define BCHP_DECODE_SINT_OLOOP_0_REG_START                 0x00a0cc00
+#define BCHP_DECODE_SINT_OLOOP_0_REG_END                   0x00a0ccfc
+#define BCHP_DECODE_SD_0_REG_START                         0x00a40800
+#define BCHP_DECODE_SD_0_REG_END                           0x00a40ffc
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_START             0x00a41000
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_END               0x00a4107c
+#define BCHP_DECODE_CPUCORE_0_REG_START                    0x00a44000
+#define BCHP_DECODE_CPUCORE_0_REG_END                      0x00a44ffc
+#define BCHP_DECODE_CPUAUX_0_REG_START                     0x00a45000
+#define BCHP_DECODE_CPUAUX_0_REG_END                       0x00a45ffc
+#define BCHP_DECODE_CPUIMEM_0_REG_START                    0x00a46000
+#define BCHP_DECODE_CPUIMEM_0_REG_END                      0x00a47ffc
+#define BCHP_DECODE_CPUDMEM_0_REG_START                    0x00a48000
+#define BCHP_DECODE_CPUDMEM_0_REG_END                      0x00a4fffc
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_START            0x00a51000
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_END              0x00a5107c
+#define BCHP_DECODE_CPUDMA2_0_REG_START                    0x00a51800
+#define BCHP_DECODE_CPUDMA2_0_REG_END                      0x00a518fc
+#define BCHP_DECODE_DMAMEM2_0_REG_START                    0x00a51a00
+#define BCHP_DECODE_DMAMEM2_0_REG_END                      0x00a521fc
+#define BCHP_DECODE_CPUCORE2_0_REG_START                   0x00a54000
+#define BCHP_DECODE_CPUCORE2_0_REG_END                     0x00a54ffc
+#define BCHP_DECODE_CPUAUX2_0_REG_START                    0x00a55000
+#define BCHP_DECODE_CPUAUX2_0_REG_END                      0x00a55ffc
+#define BCHP_DECODE_CPUIMEM2_0_REG_START                   0x00a56000
+#define BCHP_DECODE_CPUIMEM2_0_REG_END                     0x00a57ffc
+#define BCHP_DECODE_CPUDMEM2_0_REG_START                   0x00a58000
+#define BCHP_DECODE_CPUDMEM2_0_REG_END                     0x00a5fffc
+#define BCHP_DECODE_IP_SHIM_0_REG_START                    0x00a60000
+#define BCHP_DECODE_IP_SHIM_0_REG_END                      0x00a60090
+#define BCHP_AVD_CACHE_0_REG_START                         0x00a62000
+#define BCHP_AVD_CACHE_0_REG_END                           0x00a6203c
+#define BCHP_ILS_REGS_0_REG_START                          0x00a70000
+#define BCHP_ILS_REGS_0_REG_END                            0x00a700fc
+#define BCHP_ILS_SCALE_ADDR_0_REG_START                    0x00a70100
+#define BCHP_ILS_SCALE_ADDR_0_REG_END                      0x00a7010c
+#define BCHP_ILS_SPSCALE_FILL_0_REG_START                  0x00a70180
+#define BCHP_ILS_SPSCALE_FILL_0_REG_END                    0x00a70180
+#define BCHP_ILS_MVSCALE_0_REG_START                       0x00a70200
+#define BCHP_ILS_MVSCALE_0_REG_END                         0x00a7038c
+#define BCHP_ILB_REGS_0_REG_START                          0x00a70400
+#define BCHP_ILB_REGS_0_REG_END                            0x00a70404
+#define BCHP_SVD_INTR2_0_REG_START                         0x00a80000
+#define BCHP_SVD_INTR2_0_REG_END                           0x00a8002c
+#define BCHP_SVD_RGR_0_REG_START                           0x00a80400
+#define BCHP_SVD_RGR_0_REG_END                             0x00a80410
+#define BCHP_BLD_DECODE_RBNODE_REGS_0_REG_START            0x00b00000
+#define BCHP_BLD_DECODE_RBNODE_REGS_0_REG_END              0x00b0007c
+#define BCHP_BLD_DECODE_MAIN_0_REG_START                   0x00b00100
+#define BCHP_BLD_DECODE_MAIN_0_REG_END                     0x00b001fc
+#define BCHP_BLD_SDRAM_DEBUG_0_REG_START                   0x00b00200
+#define BCHP_BLD_SDRAM_DEBUG_0_REG_END                     0x00b0027c
+#define BCHP_BLD_DECODE_MCOM_0_REG_START                   0x00b00300
+#define BCHP_BLD_DECODE_MCOM_0_REG_END                     0x00b0031c
+#define BCHP_BLD_DECODE_SPRE_0_REG_START                   0x00b00320
+#define BCHP_BLD_DECODE_SPRE_0_REG_END                     0x00b0033c
+#define BCHP_BLD_DECODE_WPRD_0_REG_START                   0x00b00340
+#define BCHP_BLD_DECODE_WPRD_0_REG_END                     0x00b0035c
+#define BCHP_BLD_DECODE_DQNT_0_REG_START                   0x00b00400
+#define BCHP_BLD_DECODE_DQNT_0_REG_END                     0x00b0045c
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_START               0x00b00500
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_END                 0x00b0057c
+#define BCHP_BLD_DECODE_VP8_XFRM_0_REG_START               0x00b00600
+#define BCHP_BLD_DECODE_VP8_XFRM_0_REG_END                 0x00b0060c
+#define BCHP_BLD_DECODE_VP6_DCP_0_REG_START                0x00b00620
+#define BCHP_BLD_DECODE_VP6_DCP_0_REG_END                  0x00b0062c
+#define BCHP_BLD_DECODE_XFRM_0_REG_START                   0x00b00700
+#define BCHP_BLD_DECODE_XFRM_0_REG_END                     0x00b0071c
+#define BCHP_BLD_DECODE_DBLK_0_REG_START                   0x00b00720
+#define BCHP_BLD_DECODE_DBLK_0_REG_END                     0x00b0073c
+#define BCHP_BLD_DECODE_MB_0_REG_START                     0x00b00740
+#define BCHP_BLD_DECODE_MB_0_REG_END                       0x00b0075c
+#define BCHP_BLD_REG_CABAC2BINS_0_REG_START                0x00b00b00
+#define BCHP_BLD_REG_CABAC2BINS_0_REG_END                  0x00b00bfc
+#define BCHP_BLD_DECODE_SINT_0_REG_START                   0x00b00c00
+#define BCHP_BLD_DECODE_SINT_0_REG_END                     0x00b00dfc
+#define BCHP_BLD_DECODE_RVC_0_REG_START                    0x00b00e00
+#define BCHP_BLD_DECODE_RVC_0_REG_END                      0x00b00efc
+#define BCHP_BLD_DECODE_CPUREGS_0_REG_START                0x00b00f00
+#define BCHP_BLD_DECODE_CPUREGS_0_REG_END                  0x00b00f7c
+#define BCHP_BLD_DECODE_CPUREGS2_0_REG_START               0x00b00f80
+#define BCHP_BLD_DECODE_CPUREGS2_0_REG_END                 0x00b00ffc
+#define BCHP_BLD_DECODE_CPUDMA_0_REG_START                 0x00b01800
+#define BCHP_BLD_DECODE_CPUDMA_0_REG_END                   0x00b018fc
+#define BCHP_BLD_DECODE_DMAMEM_0_REG_START                 0x00b01a00
+#define BCHP_BLD_DECODE_DMAMEM_0_REG_END                   0x00b021fc
+#define BCHP_BLD_REG_CABAC2BINS2_0_REG_START               0x00b02400
+#define BCHP_BLD_REG_CABAC2BINS2_0_REG_END                 0x00b027fc
+#define BCHP_BLD_DECODE_WPTBL_0_REG_START                  0x00b03000
+#define BCHP_BLD_DECODE_WPTBL_0_REG_END                    0x00b031fc
+#define BCHP_BLD_DECODE_SINT_OLOOP_0_REG_START             0x00b0cc00
+#define BCHP_BLD_DECODE_SINT_OLOOP_0_REG_END               0x00b0ccfc
+#define BCHP_BLD_DECODE_SD_0_REG_START                     0x00b40800
+#define BCHP_BLD_DECODE_SD_0_REG_END                       0x00b40ffc
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS_0_REG_START         0x00b41000
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS_0_REG_END           0x00b4107c
+#define BCHP_BLD_DECODE_CPUCORE_0_REG_START                0x00b44000
+#define BCHP_BLD_DECODE_CPUCORE_0_REG_END                  0x00b44ffc
+#define BCHP_BLD_DECODE_CPUAUX_0_REG_START                 0x00b45000
+#define BCHP_BLD_DECODE_CPUAUX_0_REG_END                   0x00b45ffc
+#define BCHP_BLD_DECODE_CPUIMEM_0_REG_START                0x00b46000
+#define BCHP_BLD_DECODE_CPUIMEM_0_REG_END                  0x00b47ffc
+#define BCHP_BLD_DECODE_CPUDMEM_0_REG_START                0x00b48000
+#define BCHP_BLD_DECODE_CPUDMEM_0_REG_END                  0x00b4fffc
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS2_0_REG_START        0x00b51000
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS2_0_REG_END          0x00b5107c
+#define BCHP_BLD_DECODE_CPUDMA2_0_REG_START                0x00b51800
+#define BCHP_BLD_DECODE_CPUDMA2_0_REG_END                  0x00b518fc
+#define BCHP_BLD_DECODE_DMAMEM2_0_REG_START                0x00b51a00
+#define BCHP_BLD_DECODE_DMAMEM2_0_REG_END                  0x00b521fc
+#define BCHP_BLD_DECODE_CPUCORE2_0_REG_START               0x00b54000
+#define BCHP_BLD_DECODE_CPUCORE2_0_REG_END                 0x00b54ffc
+#define BCHP_BLD_DECODE_CPUAUX2_0_REG_START                0x00b55000
+#define BCHP_BLD_DECODE_CPUAUX2_0_REG_END                  0x00b55ffc
+#define BCHP_BLD_DECODE_CPUIMEM2_0_REG_START               0x00b56000
+#define BCHP_BLD_DECODE_CPUIMEM2_0_REG_END                 0x00b57ffc
+#define BCHP_BLD_DECODE_CPUDMEM2_0_REG_START               0x00b58000
+#define BCHP_BLD_DECODE_CPUDMEM2_0_REG_END                 0x00b5fffc
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_START                0x00b60000
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_END                  0x00b60090
+#define BCHP_BLD_AVD_CACHE_0_REG_START                     0x00b62000
+#define BCHP_BLD_AVD_CACHE_0_REG_END                       0x00b6203c
+#define BCHP_VICH_0_REG_START                              0x00b70000
+#define BCHP_VICH_0_REG_END                                0x00b7008b
+#define BCHP_GENET_0_SYS_REG_START                         0x00b80000
+#define BCHP_GENET_0_SYS_REG_END                           0x00b8000c
+#define BCHP_GENET_0_GR_BRIDGE_REG_START                   0x00b80040
+#define BCHP_GENET_0_GR_BRIDGE_REG_END                     0x00b8004c
+#define BCHP_GENET_0_EXT_REG_START                         0x00b80080
+#define BCHP_GENET_0_EXT_REG_END                           0x00b80098
+#define BCHP_GENET_0_INTRL2_0_REG_START                    0x00b80200
+#define BCHP_GENET_0_INTRL2_0_REG_END                      0x00b8022c
+#define BCHP_GENET_0_INTRL2_1_REG_START                    0x00b80240
+#define BCHP_GENET_0_INTRL2_1_REG_END                      0x00b8026c
+#define BCHP_GENET_0_RBUF_REG_START                        0x00b80300
+#define BCHP_GENET_0_RBUF_REG_END                          0x00b803b4
+#define BCHP_GENET_0_TBUF_REG_START                        0x00b80600
+#define BCHP_GENET_0_TBUF_REG_END                          0x00b80628
+#define BCHP_GENET_0_UMAC_REG_START                        0x00b80800
+#define BCHP_GENET_0_UMAC_REG_END                          0x00b80ed8
+#define BCHP_GENET_0_HFB_REG_START                         0x00b88000
+#define BCHP_GENET_0_HFB_REG_END                           0x00b8fc48
+#define BCHP_GENET_0_RDMA_REG_START                        0x00b90000
+#define BCHP_GENET_0_RDMA_REG_END                          0x00b90cd4
+#define BCHP_GENET_0_TDMA_REG_START                        0x00b91000
+#define BCHP_GENET_0_TDMA_REG_END                          0x00b91c84
+#define BCHP_GENET_1_SYS_REG_START                         0x00ba0000
+#define BCHP_GENET_1_SYS_REG_END                           0x00ba000c
+#define BCHP_GENET_1_GR_BRIDGE_REG_START                   0x00ba0040
+#define BCHP_GENET_1_GR_BRIDGE_REG_END                     0x00ba004c
+#define BCHP_GENET_1_EXT_REG_START                         0x00ba0080
+#define BCHP_GENET_1_EXT_REG_END                           0x00ba0098
+#define BCHP_GENET_1_INTRL2_0_REG_START                    0x00ba0200
+#define BCHP_GENET_1_INTRL2_0_REG_END                      0x00ba022c
+#define BCHP_GENET_1_INTRL2_1_REG_START                    0x00ba0240
+#define BCHP_GENET_1_INTRL2_1_REG_END                      0x00ba026c
+#define BCHP_GENET_1_RBUF_REG_START                        0x00ba0300
+#define BCHP_GENET_1_RBUF_REG_END                          0x00ba03b4
+#define BCHP_GENET_1_TBUF_REG_START                        0x00ba0600
+#define BCHP_GENET_1_TBUF_REG_END                          0x00ba0628
+#define BCHP_GENET_1_UMAC_REG_START                        0x00ba0800
+#define BCHP_GENET_1_UMAC_REG_END                          0x00ba0ed8
+#define BCHP_GENET_1_HFB_REG_START                         0x00ba8000
+#define BCHP_GENET_1_HFB_REG_END                           0x00bafc48
+#define BCHP_GENET_1_RDMA_REG_START                        0x00bb0000
+#define BCHP_GENET_1_RDMA_REG_END                          0x00bb0cd4
+#define BCHP_GENET_1_TDMA_REG_START                        0x00bb1000
+#define BCHP_GENET_1_TDMA_REG_END                          0x00bb1c84
+#define BCHP_SID_REG_START                                 0x00bc0100
+#define BCHP_SID_REG_END                                   0x00bc019c
+#define BCHP_SID_RLE_REG_START                             0x00bc0300
+#define BCHP_SID_RLE_REG_END                               0x00bc039c
+#define BCHP_SID_DQ_REG_START                              0x00bc0400
+#define BCHP_SID_DQ_REG_END                                0x00bc04bc
+#define BCHP_SID_STRM_REG_START                            0x00bc0800
+#define BCHP_SID_STRM_REG_END                              0x00bc087c
+#define BCHP_SID_OUTPUT_REG_START                          0x00bc0c00
+#define BCHP_SID_OUTPUT_REG_END                            0x00bc0c40
+#define BCHP_SID_ARC_REG_START                             0x00bc0f00
+#define BCHP_SID_ARC_REG_END                               0x00bc0f3c
+#define BCHP_SID_ARCDMA_REG_START                          0x00bc1800
+#define BCHP_SID_ARCDMA_REG_END                            0x00bc1840
+#define BCHP_SID_DMARAM_REG_START                          0x00bc1a00
+#define BCHP_SID_DMARAM_REG_END                            0x00bc1bfc
+#define BCHP_SID_PEEK_BITS_REG_START                       0x00bc2b00
+#define BCHP_SID_PEEK_BITS_REG_END                         0x00bc2b3c
+#define BCHP_SID_EXTRACT_BITS_REG_START                    0x00bc2b40
+#define BCHP_SID_EXTRACT_BITS_REG_END                      0x00bc2b7c
+#define BCHP_SID_HUFF_SYMB_REG_START                       0x00bc3000
+#define BCHP_SID_HUFF_SYMB_REG_END                         0x00bc37fc
+#define BCHP_SID_HUFF_CODE_REG_START                       0x00bc3900
+#define BCHP_SID_HUFF_CODE_REG_END                         0x00bc39fc
+#define BCHP_SID_SYMB_REG_START                            0x00bc3a00
+#define BCHP_SID_SYMB_REG_END                              0x00bc3a10
+#define BCHP_SID_SYMB_JPEG_REG_START                       0x00bc3a80
+#define BCHP_SID_SYMB_JPEG_REG_END                         0x00bc3a8c
+#define BCHP_SID_BIGRAM_REG_START                          0x00bc8000
+#define BCHP_SID_BIGRAM_REG_END                            0x00bcfffc
+#define BCHP_SID_ARC_DBG_REG_START                         0x00bd1000
+#define BCHP_SID_ARC_DBG_REG_END                           0x00bd1010
+#define BCHP_SID_ARC_CORE_REG_START                        0x00bd5000
+#define BCHP_SID_ARC_CORE_REG_END                          0x00bd5014
+#define BCHP_SID_GR_REG_START                              0x00be0000
+#define BCHP_SID_GR_REG_END                                0x00be000c
+#define BCHP_SID_L2_REG_START                              0x00be0100
+#define BCHP_SID_L2_REG_END                                0x00be012c
+#define BCHP_SICH_REG_START                                0x00be2000
+#define BCHP_SICH_REG_END                                  0x00be203c
+#define BCHP_M2MC_REG_START                                0x00be4000
+#define BCHP_M2MC_REG_END                                  0x00be47fc
+#define BCHP_M2MC_L2_REG_START                             0x00be5000
+#define BCHP_M2MC_L2_REG_END                               0x00be502c
+#define BCHP_M2MC_GR_REG_START                             0x00be5800
+#define BCHP_M2MC_GR_REG_END                               0x00be580c
+#define BCHP_M2MC1_REG_START                               0x00be6000
+#define BCHP_M2MC1_REG_END                                 0x00be67fc
+#define BCHP_M2MC1_L2_REG_START                            0x00be7000
+#define BCHP_M2MC1_L2_REG_END                              0x00be702c
+#define BCHP_M2MC1_GR_REG_START                            0x00be7800
+#define BCHP_M2MC1_GR_REG_END                              0x00be780c
+#define BCHP_V3D_CTL_REG_START                             0x00bea000
+#define BCHP_V3D_CTL_REG_END                               0x00bea040
+#define BCHP_V3D_CLE_REG_START                             0x00bea100
+#define BCHP_V3D_CLE_REG_END                               0x00bea138
+#define BCHP_V3D_PTB_REG_START                             0x00bea300
+#define BCHP_V3D_PTB_REG_END                               0x00bea310
+#define BCHP_V3D_QPS_REG_START                             0x00bea400
+#define BCHP_V3D_QPS_REG_END                               0x00bea43c
+#define BCHP_V3D_VPM_REG_START                             0x00bea500
+#define BCHP_V3D_VPM_REG_END                               0x00bea504
+#define BCHP_V3D_PCTR_REG_START                            0x00bea600
+#define BCHP_V3D_PCTR_REG_END                              0x00bea6fc
+#define BCHP_V3D_TOP_GR_BRIDGE_REG_START                   0x00bea800
+#define BCHP_V3D_TOP_GR_BRIDGE_REG_END                     0x00bea80c
+#define BCHP_V3D_GCA_REG_START                             0x00beaa00
+#define BCHP_V3D_GCA_REG_END                               0x00beaa58
+#define BCHP_V3D_DBG_REG_START                             0x00beae00
+#define BCHP_V3D_DBG_REG_END                               0x00beaf20
+#define BCHP_RAAGA_DSP_SEC0_REG_START                      0x00bf0000
+#define BCHP_RAAGA_DSP_SEC0_REG_END                        0x00bf0000
+#define BCHP_RAAGA_DSP_SEC0_1_REG_START                    0x00bf1000
+#define BCHP_RAAGA_DSP_SEC0_1_REG_END                      0x00bf1000
+#define BCHP_RAAGA_DSP_RGR_REG_START                       0x00c00000
+#define BCHP_RAAGA_DSP_RGR_REG_END                         0x00c00008
+#define BCHP_RAAGA_DSP_MISC_REG_START                      0x00c20000
+#define BCHP_RAAGA_DSP_MISC_REG_END                        0x00c2044c
+#define BCHP_RAAGA_DSP_TIMERS_REG_START                    0x00c21000
+#define BCHP_RAAGA_DSP_TIMERS_REG_END                      0x00c21058
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START             0x00c21080
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END               0x00c2109c
+#define BCHP_RAAGA_DSP_PERI_SW_REG_START                   0x00c21100
+#define BCHP_RAAGA_DSP_PERI_SW_REG_END                     0x00c21154
+#define BCHP_RAAGA_DSP_DMA_REG_START                       0x00c21400
+#define BCHP_RAAGA_DSP_DMA_REG_END                         0x00c21664
+#define BCHP_RAAGA_DSP_ESR_SI_REG_START                    0x00c22000
+#define BCHP_RAAGA_DSP_ESR_SI_REG_END                      0x00c22014
+#define BCHP_RAAGA_DSP_INTH_REG_START                      0x00c22200
+#define BCHP_RAAGA_DSP_INTH_REG_END                        0x00c2222c
+#define BCHP_RAAGA_DSP_FW_INTH_REG_START                   0x00c22400
+#define BCHP_RAAGA_DSP_FW_INTH_REG_END                     0x00c2242c
+#define BCHP_RAAGA_DSP_FW_CFG_REG_START                    0x00c23000
+#define BCHP_RAAGA_DSP_FW_CFG_REG_END                      0x00c2357c
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START             0x00c30000
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END               0x00c3bffc
+#define BCHP_AIO_MISC_REG_START                            0x00c80000
+#define BCHP_AIO_MISC_REG_END                              0x00c80010
+#define BCHP_AIO_INTH_REG_START                            0x00c80100
+#define BCHP_AIO_INTH_REG_END                              0x00c8012c
+#define BCHP_AIO_INTD0_REG_START                           0x00c80200
+#define BCHP_AIO_INTD0_REG_END                             0x00c80214
+#define BCHP_AUD_FMM_MISC_REG_START                        0x00c80400
+#define BCHP_AUD_FMM_MISC_REG_END                          0x00c8050c
+#define BCHP_AUD_FMM_BF_CTRL_REG_START                     0x00c90000
+#define BCHP_AUD_FMM_BF_CTRL_REG_END                       0x00c90d3c
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_START                   0x00c91000
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_END                     0x00c91014
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_START                   0x00c91020
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_END                     0x00c91034
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_START                   0x00c91040
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_END                     0x00c91054
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_START                  0x00c91100
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_END                    0x00c91114
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_START                  0x00c91120
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_END                    0x00c91134
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_START                  0x00c91140
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_END                    0x00c91154
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_START                   0x00c92000
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_END                     0x00c92bfc
+#define BCHP_AUD_FMM_SRC_ESR0_REG_START                    0x00c93000
+#define BCHP_AUD_FMM_SRC_ESR0_REG_END                      0x00c93014
+#define BCHP_AUD_FMM_DP_CTRL0_REG_START                    0x00c94000
+#define BCHP_AUD_FMM_DP_CTRL0_REG_END                      0x00c9612c
+#define BCHP_AUD_FMM_DP_ESR0_H0_REG_START                  0x00c97c00
+#define BCHP_AUD_FMM_DP_ESR0_H0_REG_END                    0x00c97c14
+#define BCHP_AUD_FMM_DP_ESR1_H0_REG_START                  0x00c97c40
+#define BCHP_AUD_FMM_DP_ESR1_H0_REG_END                    0x00c97c54
+#define BCHP_AUD_FMM_DP_ESR0_D00_REG_START                 0x00c97c80
+#define BCHP_AUD_FMM_DP_ESR0_D00_REG_END                   0x00c97c94
+#define BCHP_AUD_FMM_DP_ESR1_D00_REG_START                 0x00c97cc0
+#define BCHP_AUD_FMM_DP_ESR1_D00_REG_END                   0x00c97cd4
+#define BCHP_AUD_FMM_IOP_CTRL_REG_START                    0x00c98000
+#define BCHP_AUD_FMM_IOP_CTRL_REG_END                      0x00c98148
+#define BCHP_AUD_FMM_IOP_ESR_REG_START                     0x00c98400
+#define BCHP_AUD_FMM_IOP_ESR_REG_END                       0x00c98414
+#define BCHP_SPDIF_RCVR_CTRL_REG_START                     0x00c99000
+#define BCHP_SPDIF_RCVR_CTRL_REG_END                       0x00c9907c
+#define BCHP_SPDIF_RCVR_ESR_REG_START                      0x00c99400
+#define BCHP_SPDIF_RCVR_ESR_REG_END                        0x00c99414
+#define BCHP_HDMI_RCVR_CTRL_REG_START                      0x00c99800
+#define BCHP_HDMI_RCVR_CTRL_REG_END                        0x00c9987c
+#define BCHP_HDMI_RCVR_ESR_REG_START                       0x00c99c00
+#define BCHP_HDMI_RCVR_ESR_REG_END                         0x00c99c14
+#define BCHP_AUD_FMM_OP_CTRL_REG_START                     0x00c9a000
+#define BCHP_AUD_FMM_OP_CTRL_REG_END                       0x00c9a1fc
+#define BCHP_AUD_FMM_OP_ESR_REG_START                      0x00c9a400
+#define BCHP_AUD_FMM_OP_ESR_REG_END                        0x00c9a414
+#define BCHP_AUD_FMM_OP_MCLKGEN_REG_START                  0x00c9a500
+#define BCHP_AUD_FMM_OP_MCLKGEN_REG_END                    0x00c9a564
+#define BCHP_AUD_FMM_PLL0_REG_START                        0x00c9a800
+#define BCHP_AUD_FMM_PLL0_REG_END                          0x00c9a834
+#define BCHP_AUD_FMM_PLL1_REG_START                        0x00c9a900
+#define BCHP_AUD_FMM_PLL1_REG_END                          0x00c9a934
+#define BCHP_AUD_FMM_PLL2_REG_START                        0x00c9aa00
+#define BCHP_AUD_FMM_PLL2_REG_END                          0x00c9aa34
+#define BCHP_HIFIDAC_CTRL0_REG_START                       0x00c9b000
+#define BCHP_HIFIDAC_CTRL0_REG_END                         0x00c9b1fc
+#define BCHP_HIFIDAC_RM0_REG_START                         0x00c9b200
+#define BCHP_HIFIDAC_RM0_REG_END                           0x00c9b224
+#define BCHP_HIFIDAC_ESR0_REG_START                        0x00c9b300
+#define BCHP_HIFIDAC_ESR0_REG_END                          0x00c9b314
+#define BCHP_HIFIDAC_CTRL1_REG_START                       0x00c9b400
+#define BCHP_HIFIDAC_CTRL1_REG_END                         0x00c9b5fc
+#define BCHP_HIFIDAC_RM1_REG_START                         0x00c9b600
+#define BCHP_HIFIDAC_RM1_REG_END                           0x00c9b624
+#define BCHP_HIFIDAC_ESR1_REG_START                        0x00c9b700
+#define BCHP_HIFIDAC_ESR1_REG_END                          0x00c9b714
+#define BCHP_AUD_FMM_MS_CTRL_REG_START                     0x00c9c000
+#define BCHP_AUD_FMM_MS_CTRL_REG_END                       0x00c9dbfc
+#define BCHP_AUD_FMM_MS_ESR_REG_START                      0x00c9e000
+#define BCHP_AUD_FMM_MS_ESR_REG_END                        0x00c9e014
+#define BCHP_RAAGA_DSP_RGR_1_REG_START                     0x00d00000
+#define BCHP_RAAGA_DSP_RGR_1_REG_END                       0x00d00008
+#define BCHP_RAAGA_DSP_MISC_1_REG_START                    0x00d20000
+#define BCHP_RAAGA_DSP_MISC_1_REG_END                      0x00d2044c
+#define BCHP_RAAGA_DSP_TIMERS_1_REG_START                  0x00d21000
+#define BCHP_RAAGA_DSP_TIMERS_1_REG_END                    0x00d21058
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_1_REG_START           0x00d21080
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_1_REG_END             0x00d2109c
+#define BCHP_RAAGA_DSP_PERI_SW_1_REG_START                 0x00d21100
+#define BCHP_RAAGA_DSP_PERI_SW_1_REG_END                   0x00d21154
+#define BCHP_RAAGA_DSP_DMA_1_REG_START                     0x00d21400
+#define BCHP_RAAGA_DSP_DMA_1_REG_END                       0x00d21664
+#define BCHP_RAAGA_DSP_ESR_SI_1_REG_START                  0x00d22000
+#define BCHP_RAAGA_DSP_ESR_SI_1_REG_END                    0x00d22014
+#define BCHP_RAAGA_DSP_INTH_1_REG_START                    0x00d22200
+#define BCHP_RAAGA_DSP_INTH_1_REG_END                      0x00d2222c
+#define BCHP_RAAGA_DSP_FW_INTH_1_REG_START                 0x00d22400
+#define BCHP_RAAGA_DSP_FW_INTH_1_REG_END                   0x00d2242c
+#define BCHP_RAAGA_DSP_FW_CFG_1_REG_START                  0x00d23000
+#define BCHP_RAAGA_DSP_FW_CFG_1_REG_END                    0x00d2357c
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_1_REG_START           0x00d30000
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_1_REG_END             0x00d3bffc
+#define BCHP_DATA_MEM_REG_START                            0x00e00000
+#define BCHP_DATA_MEM_REG_END                              0x00e47ffc
+#define BCHP_CNTL_MEM_REG_START                            0x00f20000
+#define BCHP_CNTL_MEM_REG_END                              0x00f67ffc
+#define BCHP_DMA_AHB_ECL_CMD_SCH0_REG_START                0x00fc0000
+#define BCHP_DMA_AHB_ECL_CMD_SCH0_REG_END                  0x00fc0000
+#define BCHP_DMA_AHB_ECL_CMD_SCH1_REG_START                0x00fc0010
+#define BCHP_DMA_AHB_ECL_CMD_SCH1_REG_END                  0x00fc0010
+#define BCHP_DMA_AHB_ECL_CMD_SCH2_REG_START                0x00fc0020
+#define BCHP_DMA_AHB_ECL_CMD_SCH2_REG_END                  0x00fc0020
+#define BCHP_DMA_AHB_ECL_CMD_SCH3_REG_START                0x00fc0030
+#define BCHP_DMA_AHB_ECL_CMD_SCH3_REG_END                  0x00fc0030
+#define BCHP_DMA_AHB_ECL_CMD_SCH4_REG_START                0x00fc0040
+#define BCHP_DMA_AHB_ECL_CMD_SCH4_REG_END                  0x00fc0040
+#define BCHP_DMA_AHB_ECL_CMD_SCH5_REG_START                0x00fc0050
+#define BCHP_DMA_AHB_ECL_CMD_SCH5_REG_END                  0x00fc0050
+#define BCHP_DMA_AHB_ECL_CMD_SCH6_REG_START                0x00fc0060
+#define BCHP_DMA_AHB_ECL_CMD_SCH6_REG_END                  0x00fc0060
+#define BCHP_DMA_AHB_ECL_CMD_SCH7_REG_START                0x00fc0070
+#define BCHP_DMA_AHB_ECL_CMD_SCH7_REG_END                  0x00fc0070
+#define BCHP_DMA_AHB_ECL_CMD_SCH8_REG_START                0x00fc0080
+#define BCHP_DMA_AHB_ECL_CMD_SCH8_REG_END                  0x00fc0080
+#define BCHP_DMA_AHB_ECL_CMD_SCH9_REG_START                0x00fc0090
+#define BCHP_DMA_AHB_ECL_CMD_SCH9_REG_END                  0x00fc0090
+#define BCHP_DMA_AHB_ECL_CMD_SCH10_REG_START               0x00fc00a0
+#define BCHP_DMA_AHB_ECL_CMD_SCH10_REG_END                 0x00fc00a0
+#define BCHP_DMA_AHB_ECL_CMD_SCH11_REG_START               0x00fc00b0
+#define BCHP_DMA_AHB_ECL_CMD_SCH11_REG_END                 0x00fc00b0
+#define BCHP_DMA_AHB_ECL_CMD_SCH12_REG_START               0x00fc00c0
+#define BCHP_DMA_AHB_ECL_CMD_SCH12_REG_END                 0x00fc00c0
+#define BCHP_DMA_AHB_ECL_CMD_SCH13_REG_START               0x00fc00d0
+#define BCHP_DMA_AHB_ECL_CMD_SCH13_REG_END                 0x00fc00d0
+#define BCHP_DMA_AHB_ECL_CMD_SCH14_REG_START               0x00fc00e0
+#define BCHP_DMA_AHB_ECL_CMD_SCH14_REG_END                 0x00fc00e0
+#define BCHP_DMA_AHB_ECL_CMD_SCH15_REG_START               0x00fc00f0
+#define BCHP_DMA_AHB_ECL_CMD_SCH15_REG_END                 0x00fc00f0
+#define BCHP_DMA_AHB_ECL_CMD_SCH16_REG_START               0x00fc0100
+#define BCHP_DMA_AHB_ECL_CMD_SCH16_REG_END                 0x00fc0100
+#define BCHP_DMA_AHB_ECL_CMD_SCH17_REG_START               0x00fc0110
+#define BCHP_DMA_AHB_ECL_CMD_SCH17_REG_END                 0x00fc0110
+#define BCHP_DMA_AHB_ECL_CMD_SCH18_REG_START               0x00fc0120
+#define BCHP_DMA_AHB_ECL_CMD_SCH18_REG_END                 0x00fc0120
+#define BCHP_DMA_AHB_ECL_CMD_SCH19_REG_START               0x00fc0130
+#define BCHP_DMA_AHB_ECL_CMD_SCH19_REG_END                 0x00fc0130
+#define BCHP_DMA_AHB_ECL_CMD_RX_REG_START                  0x00fc0800
+#define BCHP_DMA_AHB_ECL_CMD_RX_REG_END                    0x00fc0800
+#define BCHP_DMA_AHB_CMD_RX_SCH0_REG_START                 0x00fc4000
+#define BCHP_DMA_AHB_CMD_RX_SCH0_REG_END                   0x00fc4000
+#define BCHP_DMA_AHB_CMD_RX_SCH1_REG_START                 0x00fc4010
+#define BCHP_DMA_AHB_CMD_RX_SCH1_REG_END                   0x00fc4010
+#define BCHP_DMA_AHB_CMD_RX_SCH2_REG_START                 0x00fc4020
+#define BCHP_DMA_AHB_CMD_RX_SCH2_REG_END                   0x00fc4020
+#define BCHP_DMA_AHB_CMD_RX_SCH3_REG_START                 0x00fc4030
+#define BCHP_DMA_AHB_CMD_RX_SCH3_REG_END                   0x00fc4030
+#define BCHP_DMA_AHB_CMD_RX_SCH4_REG_START                 0x00fc4040
+#define BCHP_DMA_AHB_CMD_RX_SCH4_REG_END                   0x00fc4040
+#define BCHP_DMA_AHB_CMD_RX_SCH5_REG_START                 0x00fc4050
+#define BCHP_DMA_AHB_CMD_RX_SCH5_REG_END                   0x00fc4050
+#define BCHP_DMA_AHB_CMD_RX_SCH6_REG_START                 0x00fc4060
+#define BCHP_DMA_AHB_CMD_RX_SCH6_REG_END                   0x00fc4060
+#define BCHP_DMA_AHB_CMD_RX_SCH7_REG_START                 0x00fc4070
+#define BCHP_DMA_AHB_CMD_RX_SCH7_REG_END                   0x00fc4070
+#define BCHP_DMA_AHB_CMD_RX_SCH8_REG_START                 0x00fc4080
+#define BCHP_DMA_AHB_CMD_RX_SCH8_REG_END                   0x00fc4080
+#define BCHP_DMA_AHB_CMD_RX_SCH9_REG_START                 0x00fc4090
+#define BCHP_DMA_AHB_CMD_RX_SCH9_REG_END                   0x00fc4090
+#define BCHP_DMA_AHB_CMD_RX_SCH10_REG_START                0x00fc40a0
+#define BCHP_DMA_AHB_CMD_RX_SCH10_REG_END                  0x00fc40a0
+#define BCHP_DMA_AHB_CMD_RX_SCH11_REG_START                0x00fc40b0
+#define BCHP_DMA_AHB_CMD_RX_SCH11_REG_END                  0x00fc40b0
+#define BCHP_DMA_AHB_CMD_RX_SCH12_REG_START                0x00fc40c0
+#define BCHP_DMA_AHB_CMD_RX_SCH12_REG_END                  0x00fc40c0
+#define BCHP_DMA_AHB_CMD_RX_SCH13_REG_START                0x00fc40d0
+#define BCHP_DMA_AHB_CMD_RX_SCH13_REG_END                  0x00fc40d0
+#define BCHP_DMA_AHB_CMD_RX_SCH14_REG_START                0x00fc40e0
+#define BCHP_DMA_AHB_CMD_RX_SCH14_REG_END                  0x00fc40e0
+#define BCHP_DMA_AHB_CMD_RX_SCH15_REG_START                0x00fc40f0
+#define BCHP_DMA_AHB_CMD_RX_SCH15_REG_END                  0x00fc40f0
+#define BCHP_DMA_AHB_CMD_RX_SCH16_REG_START                0x00fc4100
+#define BCHP_DMA_AHB_CMD_RX_SCH16_REG_END                  0x00fc4100
+#define BCHP_DMA_AHB_CMD_RX_SCH17_REG_START                0x00fc4110
+#define BCHP_DMA_AHB_CMD_RX_SCH17_REG_END                  0x00fc4110
+#define BCHP_DMA_AHB_CMD_RX_SCH18_REG_START                0x00fc4120
+#define BCHP_DMA_AHB_CMD_RX_SCH18_REG_END                  0x00fc4120
+#define BCHP_DMA_AHB_CMD_RX_SCH19_REG_START                0x00fc4130
+#define BCHP_DMA_AHB_CMD_RX_SCH19_REG_END                  0x00fc4130
+#define BCHP_DMA_AHB_CMD_RES0_SCH0_REG_START               0x00fc4200
+#define BCHP_DMA_AHB_CMD_RES0_SCH0_REG_END                 0x00fc4200
+#define BCHP_DMA_AHB_CMD_RES0_SCH1_REG_START               0x00fc4210
+#define BCHP_DMA_AHB_CMD_RES0_SCH1_REG_END                 0x00fc4210
+#define BCHP_DMA_AHB_CMD_RES0_SCH2_REG_START               0x00fc4220
+#define BCHP_DMA_AHB_CMD_RES0_SCH2_REG_END                 0x00fc4220
+#define BCHP_DMA_AHB_CMD_RES0_SCH3_REG_START               0x00fc4230
+#define BCHP_DMA_AHB_CMD_RES0_SCH3_REG_END                 0x00fc4230
+#define BCHP_DMA_AHB_CMD_RES0_SCH4_REG_START               0x00fc4240
+#define BCHP_DMA_AHB_CMD_RES0_SCH4_REG_END                 0x00fc4240
+#define BCHP_DMA_AHB_CMD_RES0_SCH5_REG_START               0x00fc4250
+#define BCHP_DMA_AHB_CMD_RES0_SCH5_REG_END                 0x00fc4250
+#define BCHP_DMA_AHB_CMD_RES0_SCH6_REG_START               0x00fc4260
+#define BCHP_DMA_AHB_CMD_RES0_SCH6_REG_END                 0x00fc4260
+#define BCHP_DMA_AHB_CMD_RES0_SCH7_REG_START               0x00fc4270
+#define BCHP_DMA_AHB_CMD_RES0_SCH7_REG_END                 0x00fc4270
+#define BCHP_DMA_AHB_CMD_TX0_REG_START                     0x00fc4800
+#define BCHP_DMA_AHB_CMD_TX0_REG_END                       0x00fc4800
+#define BCHP_DMA_AHB_CMD_TX1_REG_START                     0x00fc4a00
+#define BCHP_DMA_AHB_CMD_TX1_REG_END                       0x00fc4a00
+#define BCHP_DMA_AHB_CMD_CONF0_REG_START                   0x00fc4c00
+#define BCHP_DMA_AHB_CMD_CONF0_REG_END                     0x00fc4c00
+#define BCHP_MAC_AHB_REG_START                             0x00fc5000
+#define BCHP_MAC_AHB_REG_END                               0x00fc500c
+#define BCHP_LLM_AHB_REG_START                             0x00fc8000
+#define BCHP_LLM_AHB_REG_END                               0x00fc805c
+#define BCHP_PHY_REG_START                                 0x00fe0000
+#define BCHP_PHY_REG_END                                   0x00fe47fc
+#define BCHP_ECL_REG_START                                 0x00fe8000
+#define BCHP_ECL_REG_END                                   0x00fec93c
+#define BCHP_DMA_IO2MEM_CH_ECL_TX_Global_REG_START         0x00fed000
+#define BCHP_DMA_IO2MEM_CH_ECL_TX_Global_REG_END           0x00fed014
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH0_REG_START      0x00fed040
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH0_REG_END        0x00fed06c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH1_REG_START      0x00fed080
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH1_REG_END        0x00fed0ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH2_REG_START      0x00fed0c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH2_REG_END        0x00fed0ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH3_REG_START      0x00fed100
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH3_REG_END        0x00fed12c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH4_REG_START      0x00fed140
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH4_REG_END        0x00fed16c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH5_REG_START      0x00fed180
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH5_REG_END        0x00fed1ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH6_REG_START      0x00fed1c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH6_REG_END        0x00fed1ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH7_REG_START      0x00fed200
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH7_REG_END        0x00fed22c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH8_REG_START      0x00fed240
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH8_REG_END        0x00fed26c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH9_REG_START      0x00fed280
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH9_REG_END        0x00fed2ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH10_REG_START     0x00fed2c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH10_REG_END       0x00fed2ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH11_REG_START     0x00fed300
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH11_REG_END       0x00fed32c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH12_REG_START     0x00fed340
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH12_REG_END       0x00fed36c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH13_REG_START     0x00fed380
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH13_REG_END       0x00fed3ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH14_REG_START     0x00fed3c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH14_REG_END       0x00fed3ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH15_REG_START     0x00fed400
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH15_REG_END       0x00fed42c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH16_REG_START     0x00fed440
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH16_REG_END       0x00fed46c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH17_REG_START     0x00fed480
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH17_REG_END       0x00fed4ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH18_REG_START     0x00fed4c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH18_REG_END       0x00fed4ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH19_REG_START     0x00fed500
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH19_REG_END       0x00fed52c
+#define BCHP_DMA_MEM2IO_CH_ECL_RX_REG_START                0x00fed800
+#define BCHP_DMA_MEM2IO_CH_ECL_RX_REG_END                  0x00fed828
+#define BCHP_GMII_REG_START                                0x00fedc00
+#define BCHP_GMII_REG_END                                  0x00fedc58
+#define BCHP_MAC_APB_REG_START                             0x00ff0000
+#define BCHP_MAC_APB_REG_END                               0x00ff14fc
+#define BCHP_DMA_IO2MEM_CH_MAC_RX_Global_REG_START         0x00ff4000
+#define BCHP_DMA_IO2MEM_CH_MAC_RX_Global_REG_END           0x00ff4014
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH0_REG_START      0x00ff4040
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH0_REG_END        0x00ff406c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH1_REG_START      0x00ff4080
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH1_REG_END        0x00ff40ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH2_REG_START      0x00ff40c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH2_REG_END        0x00ff40ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH3_REG_START      0x00ff4100
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH3_REG_END        0x00ff412c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH4_REG_START      0x00ff4140
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH4_REG_END        0x00ff416c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH5_REG_START      0x00ff4180
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH5_REG_END        0x00ff41ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH6_REG_START      0x00ff41c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH6_REG_END        0x00ff41ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH7_REG_START      0x00ff4200
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH7_REG_END        0x00ff422c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH8_REG_START      0x00ff4240
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH8_REG_END        0x00ff426c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH9_REG_START      0x00ff4280
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH9_REG_END        0x00ff42ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH10_REG_START     0x00ff42c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH10_REG_END       0x00ff42ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH11_REG_START     0x00ff4300
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH11_REG_END       0x00ff432c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH12_REG_START     0x00ff4340
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH12_REG_END       0x00ff436c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH13_REG_START     0x00ff4380
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH13_REG_END       0x00ff43ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH14_REG_START     0x00ff43c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH14_REG_END       0x00ff43ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH15_REG_START     0x00ff4400
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH15_REG_END       0x00ff442c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH16_REG_START     0x00ff4440
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH16_REG_END       0x00ff446c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH17_REG_START     0x00ff4480
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH17_REG_END       0x00ff44ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH18_REG_START     0x00ff44c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH18_REG_END       0x00ff44ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH19_REG_START     0x00ff4500
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH19_REG_END       0x00ff452c
+#define BCHP_DMA_IO2MEM_CH_PHY0_Global_REG_START           0x00ff4800
+#define BCHP_DMA_IO2MEM_CH_PHY0_Global_REG_END             0x00ff4814
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH0_REG_START        0x00ff4840
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH0_REG_END          0x00ff486c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH1_REG_START        0x00ff4880
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH1_REG_END          0x00ff48ac
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH2_REG_START        0x00ff48c0
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH2_REG_END          0x00ff48ec
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH3_REG_START        0x00ff4900
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH3_REG_END          0x00ff492c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH4_REG_START        0x00ff4940
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH4_REG_END          0x00ff496c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH5_REG_START        0x00ff4980
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH5_REG_END          0x00ff49ac
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH6_REG_START        0x00ff49c0
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH6_REG_END          0x00ff49ec
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH7_REG_START        0x00ff4a00
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH7_REG_END          0x00ff4a2c
+#define BCHP_DMA_MEM2IO_CH_MAC_TX0_REG_START               0x00ff6000
+#define BCHP_DMA_MEM2IO_CH_MAC_TX0_REG_END                 0x00ff6028
+#define BCHP_DMA_MEM2IO_CH_MAC_TX1_REG_START               0x00ff6400
+#define BCHP_DMA_MEM2IO_CH_MAC_TX1_REG_END                 0x00ff6428
+#define BCHP_DMA_MEM2IO_CH_PHY0_CONFIG_REG_START           0x00ff6800
+#define BCHP_DMA_MEM2IO_CH_PHY0_CONFIG_REG_END             0x00ff6828
+#define BCHP_MOCA_INTC_L2_HI_REG_START                     0x00ff8000
+#define BCHP_MOCA_INTC_L2_HI_REG_END                       0x00ff8584
+#define BCHP_MOCA_INTC_L2_LO_REG_START                     0x00ff8800
+#define BCHP_MOCA_INTC_L2_LO_REG_END                       0x00ff8d84
+#define BCHP_LLM_APB_REG_START                             0x00ffc000
+#define BCHP_LLM_APB_REG_END                               0x00ffd00c
+#define BCHP_TRX_REG_START                                 0x00ffe000
+#define BCHP_TRX_REG_END                                   0x00ffe0dc
+#define BCHP_MOCA_TIMER_REG_START                          0x00ffe400
+#define BCHP_MOCA_TIMER_REG_END                            0x00ffe4ec
+#define BCHP_MOCA_GPIO_REG_START                           0x00ffe800
+#define BCHP_MOCA_GPIO_REG_END                             0x00ffe818
+#define BCHP_EXTRAS_REG_START                              0x00ffec00
+#define BCHP_EXTRAS_REG_END                                0x00ffed18
+#define BCHP_MOCA_HOSTM2M_REG_START                        0x00fffc00
+#define BCHP_MOCA_HOSTM2M_REG_END                          0x00fffc0c
+#define BCHP_AHB_M2M_DMA_REG_START                         0x00fffc20
+#define BCHP_AHB_M2M_DMA_REG_END                           0x00fffc2c
+#define BCHP_MOCA_L2_REG_START                             0x00fffc40
+#define BCHP_MOCA_L2_REG_END                               0x00fffc6c
+#define BCHP_MOCA_GR_BRIDGE_REG_START                      0x00fffc80
+#define BCHP_MOCA_GR_BRIDGE_REG_END                        0x00fffc8c
+#define BCHP_MOCA_PMB_INTF_REG_START                       0x00fffcc0
+#define BCHP_MOCA_PMB_INTF_REG_END                         0x00fffccc
+#define BCHP_MOCA_HOSTMISC_REG_START                       0x00fffd00
+#define BCHP_MOCA_HOSTMISC_REG_END                         0x00fffd94
+
+
+/***************************************************************************
+ *AUD_FMM_MS_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK  0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
+
+/***************************************************************************
+ *AUD_FMM_OP_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
+ ***************************************************************************/
+/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD1
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_VFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *GFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK      0xffffffff
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT     0
+
+/***************************************************************************
+ *GFD_1
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD_1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK    0xffffffff
+#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT   0
+
+/***************************************************************************
+ *HIFIDAC_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_MUTE_USAGE - Mute usage
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *M2MC
+ ***************************************************************************/
+/***************************************************************************
+ *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK          0xffffffff
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT         0
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK              0xf0000000
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT             28
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK          0x0fffffe0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT         5
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK              0x0000001e
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT             1
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK           0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT          0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid   0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK              0xffff8000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT             15
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK   0x00004000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT  14
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK   0x00002000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT  13
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK         0x00000800
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT        11
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE   1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE  0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK  0x00000400
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK  0x00000200
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK          0x00000100
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT         8
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE   0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK   0x00000020
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT  5
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK     0x00000002
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK     0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT    0
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/***************************************************************************
+ *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK        0xffffffff
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT       0
+
+/***************************************************************************
+ *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK         0xffffffff
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT        0
+
+/***************************************************************************
+ *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_11_DST_COLOR_MATRIX_N - Linked-List Packet Word N for group DST_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_11_DST_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_12_OUTPUT_COLOR_MATRIX_N - Linked-List Packet Word N for group OUTPUT_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_12_OUTPUT_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_13_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *LIST_PKT_14_DST_CLUT - Linked-List Packet Word for group DST_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_14_DST_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_14_DST_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *TYPE_CLUT_COLOR_DATA - color data for color look up table
+ ***************************************************************************/
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK                  0xff000000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT                 24
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK                    0x00ff0000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT                   16
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK                  0x0000ff00
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT                 8
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK                   0x000000ff
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT                  0
+
+/***************************************************************************
+ *MEM_DMA
+ ***************************************************************************/
+/***************************************************************************
+ *DESC_WORD0 - MEM DMA Descriptor Word 0
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD0 :: READ_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD1 - MEM DMA Descriptor Word 1
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD1 :: WRITE_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_MASK                    0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD2 - MEM DMA Descriptor Word 2
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD2 :: INTR_ENABLE [31:31] */
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK                   0x80000000
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_SHIFT                  31
+
+/* MEM_DMA :: DESC_WORD2 :: LAST [30:30] */
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_MASK                          0x40000000
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_SHIFT                         30
+
+/* MEM_DMA :: DESC_WORD2 :: AUTO_APPEND [29:29] */
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_MASK                   0x20000000
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_SHIFT                  29
+
+/* MEM_DMA :: DESC_WORD2 :: reserved0 [28:25] */
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_MASK                     0x1e000000
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_SHIFT                    25
+
+/* MEM_DMA :: DESC_WORD2 :: TRANSFER_SIZE [24:00] */
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK                 0x01ffffff
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_SHIFT                0
+
+/***************************************************************************
+ *DESC_WORD3 - MEM DMA Descriptor Word 3
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD3 :: NEXT_DESC_ADDR [31:05] */
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK                0xffffffe0
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_SHIFT               5
+
+/* MEM_DMA :: DESC_WORD3 :: reserved0 [04:03] */
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_MASK                     0x00000018
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_SHIFT                    3
+
+/* MEM_DMA :: DESC_WORD3 :: READ_ENDIAN_MODE [02:02] */
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_MASK              0x00000004
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_SHIFT             2
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_BIG_ENDIAN        0
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_LITTLE_ENDIAN     1
+
+/* MEM_DMA :: DESC_WORD3 :: WRITE_ENDIAN_XLATE_MODE [01:00] */
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_MASK       0x00000003
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_SHIFT      0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_WORD_ALIGNED 0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_HALF_WORD_ALIGNED 1
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_BYTE_ALIGNED 2
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_reserved   3
+
+/***************************************************************************
+ *DESC_WORD4 - MEM DMA Descriptor Word 4
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD4 :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_SHIFT                    16
+
+/* MEM_DMA :: DESC_WORD4 :: SCRAM_CTRL_RSV [15:14] */
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_MASK                0x0000c000
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_SHIFT               14
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_END [13:13] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK                  0x00002000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_SHIFT                 13
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_START [12:12] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK                0x00001000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_SHIFT               12
+
+/* MEM_DMA :: DESC_WORD4 :: SG_ENABLE [11:11] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK                     0x00000800
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_SHIFT                    11
+
+/* MEM_DMA :: DESC_WORD4 :: ENC_DEC_INIT [10:10] */
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_MASK                  0x00000400
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_SHIFT                 10
+
+/* MEM_DMA :: DESC_WORD4 :: MODE_SEL [09:08] */
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_MASK                      0x00000300
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT                     8
+
+/* MEM_DMA :: DESC_WORD4 :: KEY_SELECT [07:00] */
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_MASK                    0x000000ff
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD5 - MEM DMA Descriptor Word 5
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD5 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD6 - MEM DMA Descriptor Word 6
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD6 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD7 - MEM DMA Descriptor Word 7
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD7 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *PCIE_DMA
+ ***************************************************************************/
+/***************************************************************************
+ *DESC_WORD0 - PCIE DMA Descriptor Word 0
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD0 :: MEMORY_ADDRESS [31:02] */
+#define BCHP_PCIE_DMA_DESC_WORD0_MEMORY_ADDRESS_MASK               0xfffffffc
+#define BCHP_PCIE_DMA_DESC_WORD0_MEMORY_ADDRESS_SHIFT              2
+
+/* PCIE_DMA :: DESC_WORD0 :: reserved0 [01:00] */
+#define BCHP_PCIE_DMA_DESC_WORD0_reserved0_MASK                    0x00000003
+#define BCHP_PCIE_DMA_DESC_WORD0_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD1 - PCIE DMA Descriptor Word 1
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD1 :: PCIE_ADDRESS_LO [31:02] */
+#define BCHP_PCIE_DMA_DESC_WORD1_PCIE_ADDRESS_LO_MASK              0xfffffffc
+#define BCHP_PCIE_DMA_DESC_WORD1_PCIE_ADDRESS_LO_SHIFT             2
+
+/* PCIE_DMA :: DESC_WORD1 :: reserved0 [01:00] */
+#define BCHP_PCIE_DMA_DESC_WORD1_reserved0_MASK                    0x00000003
+#define BCHP_PCIE_DMA_DESC_WORD1_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD2 - PCIE DMA Descriptor Word 2
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD2 :: PCIE_ADDRESS_HI [31:00] */
+#define BCHP_PCIE_DMA_DESC_WORD2_PCIE_ADDRESS_HI_MASK              0xffffffff
+#define BCHP_PCIE_DMA_DESC_WORD2_PCIE_ADDRESS_HI_SHIFT             0
+
+/***************************************************************************
+ *DESC_WORD3 - PCIE DMA Descriptor Word 3
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD3 :: INTERRUPT_ENABLE [31:31] */
+#define BCHP_PCIE_DMA_DESC_WORD3_INTERRUPT_ENABLE_MASK             0x80000000
+#define BCHP_PCIE_DMA_DESC_WORD3_INTERRUPT_ENABLE_SHIFT            31
+
+/* PCIE_DMA :: DESC_WORD3 :: reserved0 [30:25] */
+#define BCHP_PCIE_DMA_DESC_WORD3_reserved0_MASK                    0x7e000000
+#define BCHP_PCIE_DMA_DESC_WORD3_reserved0_SHIFT                   25
+
+/* PCIE_DMA :: DESC_WORD3 :: DMA_TRANSFER_SIZE [24:02] */
+#define BCHP_PCIE_DMA_DESC_WORD3_DMA_TRANSFER_SIZE_MASK            0x01fffffc
+#define BCHP_PCIE_DMA_DESC_WORD3_DMA_TRANSFER_SIZE_SHIFT           2
+
+/* PCIE_DMA :: DESC_WORD3 :: reserved1 [01:00] */
+#define BCHP_PCIE_DMA_DESC_WORD3_reserved1_MASK                    0x00000003
+#define BCHP_PCIE_DMA_DESC_WORD3_reserved1_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD4 - PCIE DMA Descriptor Word 4
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD4 :: LAST_RECORD_INDICATOR [31:31] */
+#define BCHP_PCIE_DMA_DESC_WORD4_LAST_RECORD_INDICATOR_MASK        0x80000000
+#define BCHP_PCIE_DMA_DESC_WORD4_LAST_RECORD_INDICATOR_SHIFT       31
+
+/* PCIE_DMA :: DESC_WORD4 :: DMA_DIRECTION [30:30] */
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_MASK                0x40000000
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_SHIFT               30
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_PCIE_TO_MEMORY      1
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_MEMORY_TO_PCIE      0
+
+/* PCIE_DMA :: DESC_WORD4 :: reserved0 [29:03] */
+#define BCHP_PCIE_DMA_DESC_WORD4_reserved0_MASK                    0x3ffffff8
+#define BCHP_PCIE_DMA_DESC_WORD4_reserved0_SHIFT                   3
+
+/* PCIE_DMA :: DESC_WORD4 :: DESC_CONTIGUOUS [02:02] */
+#define BCHP_PCIE_DMA_DESC_WORD4_DESC_CONTIGUOUS_MASK              0x00000004
+#define BCHP_PCIE_DMA_DESC_WORD4_DESC_CONTIGUOUS_SHIFT             2
+
+/* PCIE_DMA :: DESC_WORD4 :: ENDIAN_XLATE_MODE [01:00] */
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_MASK            0x00000003
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SHIFT           0
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_NO_SWAP         0
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SWAP_16_IN_32   1
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SWAP_32         2
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_reserved        3
+
+/***************************************************************************
+ *DESC_WORD5 - PCIE DMA Descriptor Word 5
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD5 :: NEXT_DESC_ADDRESS_LO [31:05] */
+#define BCHP_PCIE_DMA_DESC_WORD5_NEXT_DESC_ADDRESS_LO_MASK         0xffffffe0
+#define BCHP_PCIE_DMA_DESC_WORD5_NEXT_DESC_ADDRESS_LO_SHIFT        5
+
+/* PCIE_DMA :: DESC_WORD5 :: reserved0 [04:00] */
+#define BCHP_PCIE_DMA_DESC_WORD5_reserved0_MASK                    0x0000001f
+#define BCHP_PCIE_DMA_DESC_WORD5_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD6 - PCIE DMA Descriptor Word 6
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD6 :: NEXT_DESC_ADDRESS_HI [31:00] */
+#define BCHP_PCIE_DMA_DESC_WORD6_NEXT_DESC_ADDRESS_HI_MASK         0xffffffff
+#define BCHP_PCIE_DMA_DESC_WORD6_NEXT_DESC_ADDRESS_HI_SHIFT        0
+
+/***************************************************************************
+ *DESC_WORD7 - PCIE DMA Descriptor Word 7
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD7 :: reserved0 [31:00] */
+#define BCHP_PCIE_DMA_DESC_WORD7_reserved0_MASK                    0xffffffff
+#define BCHP_PCIE_DMA_DESC_WORD7_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *RAAGA_REGSET_DSP_CFG
+ ***************************************************************************/
+/***************************************************************************
+ *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK     0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT    0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo   2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono     1
+
+/***************************************************************************
+ *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
+
+/***************************************************************************
+ *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off     0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On      1
+
+/***************************************************************************
+ *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt  1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo  2
+
+/***************************************************************************
+ *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK       0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT      0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono    1
+
+/***************************************************************************
+ *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK   0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *RDC
+ ***************************************************************************/
+/***************************************************************************
+ *EOP_ID_256 - EOP_ID
+ ***************************************************************************/
+/* RDC :: EOP_ID_256 :: eop_id [255:00] */
+#define BCHP_RDC_EOP_ID_256_eop_id_MASK                            0x0000000000000000000000000000000000000000000000000000000000000000
+#define BCHP_RDC_EOP_ID_256_eop_id_SHIFT                           0
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_0                    0
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_1                    1
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_2                    2
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_3                    3
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_4                    4
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_5                    5
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_6                    6
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_7                    7
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_0                    8
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_1                    9
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_2                    10
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_3                    11
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_4                    12
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_5                    13
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_6                    14
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_7                    15
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_0                    16
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_1                    17
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_2                    18
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_3                    19
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_4                    20
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_5                    21
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_6                    22
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_7                    23
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_0                   24
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_1                   25
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_2                   26
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_3                   27
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_4                   28
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_5                   29
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_6                   30
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_pfa_0                    31
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_0                   32
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_1                   33
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_2                   34
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_3                   35
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_4                   36
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_5                   37
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_6                   38
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_7                   39
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_nvp_0                    40
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_s3dh_0                   41
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_v0_be                    42
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_0               43
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_1               44
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_2               45
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_3               46
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_4               47
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_0                    48
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_1                    49
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_2                    50
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_3                    51
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_4                    52
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_5                    53
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_6                    54
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_7                    55
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_8                    56
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_9                    57
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_10                   58
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_11                   59
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_5               60
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_6               61
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_7               62
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_8               63
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_0                           64
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_1                           65
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_2                           66
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_3                           67
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_4                           68
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_5                           69
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_6                           70
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_7                           71
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_0                           72
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_1                           73
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_2                           74
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_3                           75
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_4                           76
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_5                           77
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_6                           78
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_7                           79
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_0                           80
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_1                           81
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_2                           82
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_3                           83
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_4                           84
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_5                           85
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_6                           86
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_7                           87
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_0                           88
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_1                           89
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_2                           90
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_3                           91
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_4                           92
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_5                           93
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_6                           94
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_7                           95
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_0                           96
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_1                           97
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_2                           98
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_3                           99
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_4                           100
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_5                           101
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_6                           102
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_7                           103
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_0                          104
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_1                          105
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_2                          106
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_3                          107
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_4                          108
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_5                          109
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_6                          110
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_7                          111
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_0                           112
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_1                           113
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_2                           114
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_3                           115
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_4                           116
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_5                           117
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_6                           118
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_7                           119
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_0                           120
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_1                           121
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_2                           122
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_3                           123
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_4                           124
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_5                           125
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_6                           126
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_7                           127
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_0                           128
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_1                           129
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_2                           130
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_3                           131
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_4                           132
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_5                           133
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_6                           134
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_7                           135
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_0                        136
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_1                        137
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_2                        138
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_3                        139
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_4                        140
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_5                        141
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_6                        142
+#define BCHP_RDC_EOP_ID_256_eop_id_tpg_0                           143
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_0                           144
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_1                           145
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_2                           146
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_3                           147
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_4                           148
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_5                           149
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_6                           150
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_7                           151
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_0                          152
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_1                          153
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_2                          154
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_3                          155
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_4                          156
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_5                          157
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_6                          158
+#define BCHP_RDC_EOP_ID_256_eop_id_pfa_0                           159
+#define BCHP_RDC_EOP_ID_256_eop_id_crc_0                           160
+#define BCHP_RDC_EOP_ID_256_eop_id_crc_1                           161
+#define BCHP_RDC_EOP_ID_256_eop_id_crc_2                           162
+#define BCHP_RDC_EOP_ID_256_eop_id_crc_3                           163
+#define BCHP_RDC_EOP_ID_256_eop_id_hist_0                          164
+#define BCHP_RDC_EOP_ID_256_eop_id_hist_1                          165
+#define BCHP_RDC_EOP_ID_256_eop_id_psm_0                           166
+#define BCHP_RDC_EOP_ID_256_eop_id_plm_0                           167
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_0                    168
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_1                    169
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_2                    170
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_3                    171
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_4                    172
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_5                    173
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_6                    174
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_7                    175
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_0                    176
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_1                    177
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_2                    178
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_3                    179
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_hist_0                   180
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_hist_1                   181
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_psm_0                    182
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_plm_0                    183
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_0_v0                 184
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_1_v0                 185
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_2_v0                 186
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_3_v0                 187
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_4_v0                 188
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_5_v0                 189
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_6_v0                 190
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_7_v0                 191
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_0_v1                 192
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_1_v1                 193
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_2_v1                 194
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_3_v1                 195
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_4_v1                 196
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_5_v1                 197
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_6_v1                 198
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_7_v1                 199
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_0                   200
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_1                   201
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_2                   202
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_3                   203
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_4                   204
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_5                   205
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_6                   206
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_7                   207
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_b3dc_0                   208
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_frc_0                    209
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_0               210
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_1               211
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_2               212
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_3               213
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_4               214
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_5               215
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_0               216
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_1               217
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_2               218
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_3               219
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_4               220
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_5               221
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_6               222
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_7               223
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_8               224
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_9               225
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_10              226
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_11              227
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_6               228
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_7               229
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_8               230
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_9               231
+#define BCHP_RDC_EOP_ID_256_eop_id_nvp_0                           232
+#define BCHP_RDC_EOP_ID_256_eop_id_s3dh_0                          233
+#define BCHP_RDC_EOP_ID_256_eop_id_v0_be                           234
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_0                      235
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_1                      236
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_2                      237
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_3                      238
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_4                      239
+#define BCHP_RDC_EOP_ID_256_eop_id_b3dc_0                          240
+#define BCHP_RDC_EOP_ID_256_eop_id_frc_0                           241
+#define BCHP_RDC_EOP_ID_256_eop_id_pdpf_0                          242
+#define BCHP_RDC_EOP_ID_256_eop_id_pdpb_0                          243
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_5                      244
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_6                      245
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_7                      246
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_8                      247
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_9                      248
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_10                     249
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_11                     250
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_12                     251
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_13                     252
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_14                     253
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_15                     254
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_16                     255
+
+/***************************************************************************
+ *RUL - RUL Command.
+ ***************************************************************************/
+/* RDC :: RUL :: opcode [31:24] */
+#define BCHP_RDC_RUL_opcode_MASK                                   0xff000000
+#define BCHP_RDC_RUL_opcode_SHIFT                                  24
+#define BCHP_RDC_RUL_opcode_NOP                                    0
+#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM                          1
+#define BCHP_RDC_RUL_opcode_REG_WRITE                              2
+#define BCHP_RDC_RUL_opcode_REG_READ                               3
+#define BCHP_RDC_RUL_opcode_LOAD_IMM                               4
+#define BCHP_RDC_RUL_opcode_WINDOW_WRITE                           5
+#define BCHP_RDC_RUL_opcode_BLOCK_WRITE                            6
+#define BCHP_RDC_RUL_opcode_WINDOW_COPY                            7
+#define BCHP_RDC_RUL_opcode_BLOCK_COPY                             8
+#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK                        9
+#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW                        10
+#define BCHP_RDC_RUL_opcode_AND                                    11
+#define BCHP_RDC_RUL_opcode_AND_IMM                                12
+#define BCHP_RDC_RUL_opcode_OR                                     13
+#define BCHP_RDC_RUL_opcode_OR_IMM                                 14
+#define BCHP_RDC_RUL_opcode_XOR                                    15
+#define BCHP_RDC_RUL_opcode_XOR_IMM                                16
+#define BCHP_RDC_RUL_opcode_NOT                                    17
+#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT                           18
+#define BCHP_RDC_RUL_opcode_SUM                                    19
+#define BCHP_RDC_RUL_opcode_SUM_IMM                                20
+#define BCHP_RDC_RUL_opcode_COND_SKIP                              21
+#define BCHP_RDC_RUL_opcode_SKIP                                   22
+#define BCHP_RDC_RUL_opcode_EXIT                                   23
+#define BCHP_RDC_RUL_opcode_WAIT_EOP                               24
+#define BCHP_RDC_RUL_opcode_PLACEHOLDER                            255
+
+/* RDC :: RUL :: reserved0 [23:23] */
+#define BCHP_RDC_RUL_reserved0_MASK                                0x00800000
+#define BCHP_RDC_RUL_reserved0_SHIFT                               23
+
+/* union - case rdc_args [22:00] */
+/* RDC :: RUL :: rdc_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_rdc_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: rdc_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_rdc_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_rdc_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: rdc_args :: src2 [11:06] */
+#define BCHP_RDC_RUL_rdc_args_src2_MASK                            0x00000fc0
+#define BCHP_RDC_RUL_rdc_args_src2_SHIFT                           6
+
+/* RDC :: RUL :: rdc_args :: dest [05:00] */
+#define BCHP_RDC_RUL_rdc_args_dest_MASK                            0x0000003f
+#define BCHP_RDC_RUL_rdc_args_dest_SHIFT                           0
+
+/* union - case reg_args [22:00] */
+/* RDC :: RUL :: reg_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_reg_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_reg_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: reg_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_reg_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_reg_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: reg_args :: count [11:00] */
+#define BCHP_RDC_RUL_reg_args_count_MASK                           0x00000fff
+#define BCHP_RDC_RUL_reg_args_count_SHIFT                          0
+
+/* union - case eop_args [22:00] */
+/* RDC :: RUL :: eop_args :: reserved0 [22:08] */
+#define BCHP_RDC_RUL_eop_args_reserved0_MASK                       0x007fff00
+#define BCHP_RDC_RUL_eop_args_reserved0_SHIFT                      8
+
+/* RDC :: RUL :: eop_args :: eop [07:00] */
+#define BCHP_RDC_RUL_eop_args_eop_MASK                             0x000000ff
+#define BCHP_RDC_RUL_eop_args_eop_SHIFT                            0
+
+/***************************************************************************
+ *SPDIF_RCVR_ESR
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_INTERRUPT_HANDLING - Interrupt Handling
+ ***************************************************************************/
+/* SPDIF_RCVR_ESR :: ABSTRACT_INTERRUPT_HANDLING :: MORE_INFORMATION [31:00] */
+#define BCHP_SPDIF_RCVR_ESR_ABSTRACT_INTERRUPT_HANDLING_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_SPDIF_RCVR_ESR_ABSTRACT_INTERRUPT_HANDLING_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *VICE2_REGSET_MISC
+ ***************************************************************************/
+/***************************************************************************
+ *DCCM - registers interface address offset in DCCM.
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: DCCM :: INTERFACE [31:16] */
+#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_MASK                 0xffff0000
+#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_SHIFT                16
+#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_HOST2VICE_OFFSET     0
+#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_VICE2HOST_OFFSET     4
+#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_BVN2VICE_OFFSET      8
+#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_MBOX_0_START         16
+#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_MBOX_1_START         44
+
+/* VICE2_REGSET_MISC :: DCCM :: REVISION [15:00] */
+#define BCHP_VICE2_REGSET_MISC_DCCM_REVISION_MASK                  0x0000ffff
+#define BCHP_VICE2_REGSET_MISC_DCCM_REVISION_SHIFT                 0
+#define BCHP_VICE2_REGSET_MISC_DCCM_REVISION_ID                    1
+
+/***************************************************************************
+ *DWORD_00_BVB_PIC_SIZE - BVB Picture Size
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: DWORD_00_BVB_PIC_SIZE :: H_SIZE [31:16] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_H_SIZE_MASK   0xffff0000
+#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_H_SIZE_SHIFT  16
+
+/* VICE2_REGSET_MISC :: DWORD_00_BVB_PIC_SIZE :: V_SIZE [15:00] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_V_SIZE_MASK   0x0000ffff
+#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_V_SIZE_SHIFT  0
+
+/***************************************************************************
+ *DWORD_01_SAMPLE_ASPECT_RATIO - Sample Aspect Ratio
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: DWORD_01_SAMPLE_ASPECT_RATIO :: H_SIZE [31:16] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_H_SIZE_MASK 0xffff0000
+#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_H_SIZE_SHIFT 16
+
+/* VICE2_REGSET_MISC :: DWORD_01_SAMPLE_ASPECT_RATIO :: V_SIZE [15:00] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_V_SIZE_MASK 0x0000ffff
+#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_V_SIZE_SHIFT 0
+
+/***************************************************************************
+ *DWORD_02_PIC_INFO - Picture Information
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: FRAME_RATE [31:16] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_FRAME_RATE_MASK   0xffff0000
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_FRAME_RATE_SHIFT  16
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: SRC_PIC_TYPE [15:12] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_MASK 0x0000f000
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_SHIFT 12
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_UNKNOWN 0
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_I    1
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_P    2
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_B    3
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: POLARITY [11:10] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_MASK     0x00000c00
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_SHIFT    10
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_TOP      0
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_BOT      1
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_FRAME    2
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: REPEAT [09:09] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_MASK       0x00000200
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_SHIFT      9
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_DISABLE    0
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_ENABLE     1
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: IGNORE [08:08] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_MASK       0x00000100
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_SHIFT      8
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_DISABLE    0
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_ENABLE     1
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: LAST [07:07] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_MASK         0x00000080
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_SHIFT        7
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_FALSE        0
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_TRUE         1
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: CHANNELCHANGE [06:06] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_MASK 0x00000040
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_SHIFT 6
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_FALSE 0
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_TRUE 1
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: reserved0 [05:05] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_reserved0_MASK    0x00000020
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_reserved0_SHIFT   5
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: ACTIVEFORMATDATA [04:04] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_MASK 0x00000010
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_SHIFT 4
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_FALSE 0
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_TRUE 1
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: ACTIVEFORMATDATAMODE [03:00] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATAMODE_MASK 0x0000000f
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATAMODE_SHIFT 0
+
+/***************************************************************************
+ *DWORD_03_ORIGINAL_PTS - Source PTS Value
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: DWORD_03_ORIGINAL_PTS :: VAL [31:00] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_03_ORIGINAL_PTS_VAL_MASK      0xffffffff
+#define BCHP_VICE2_REGSET_MISC_DWORD_03_ORIGINAL_PTS_VAL_SHIFT     0
+
+/***************************************************************************
+ *DWORD_04_STG_PICTURE_ID - STG Picture ID
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: DWORD_04_STG_PICTURE_ID :: VAL [31:00] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_04_STG_PICTURE_ID_VAL_MASK    0xffffffff
+#define BCHP_VICE2_REGSET_MISC_DWORD_04_STG_PICTURE_ID_VAL_SHIFT   0
+
+/***************************************************************************
+ *DWORD_05_BARDATA_INFO - bar data Information
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: reserved0 [31:30] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_reserved0_MASK 0xc0000000
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_reserved0_SHIFT 30
+
+/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: TOPLEFTBARVALUE [29:16] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_TOPLEFTBARVALUE_MASK 0x3fff0000
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_TOPLEFTBARVALUE_SHIFT 16
+
+/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: BARDATATYPE [15:14] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_MASK 0x0000c000
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_SHIFT 14
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_invalidBarData 0
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_TopBottom 1
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_LeftRight 2
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_reserved 3
+
+/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: BOTRIGHTBARVALUE [13:00] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BOTRIGHTBARVALUE_MASK 0x00003fff
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BOTRIGHTBARVALUE_SHIFT 0
+
+/***************************************************************************
+ *DWORD_06_FNRT_INFO - fast non real time Information
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: DWORD_06_FNRT_INFO :: reserved0 [31:18] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_06_FNRT_INFO_reserved0_MASK   0xfffc0000
+#define BCHP_VICE2_REGSET_MISC_DWORD_06_FNRT_INFO_reserved0_SHIFT  18
+
+/* VICE2_REGSET_MISC :: DWORD_06_FNRT_INFO :: ENDOFCHUNK [17:17] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_06_FNRT_INFO_ENDOFCHUNK_MASK  0x00020000
+#define BCHP_VICE2_REGSET_MISC_DWORD_06_FNRT_INFO_ENDOFCHUNK_SHIFT 17
+
+/* VICE2_REGSET_MISC :: DWORD_06_FNRT_INFO :: PRECHARGEPICTURE [16:16] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_06_FNRT_INFO_PRECHARGEPICTURE_MASK 0x00010000
+#define BCHP_VICE2_REGSET_MISC_DWORD_06_FNRT_INFO_PRECHARGEPICTURE_SHIFT 16
+
+/* VICE2_REGSET_MISC :: DWORD_06_FNRT_INFO :: reserved1 [15:10] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_06_FNRT_INFO_reserved1_MASK   0x0000fc00
+#define BCHP_VICE2_REGSET_MISC_DWORD_06_FNRT_INFO_reserved1_SHIFT  10
+
+/* VICE2_REGSET_MISC :: DWORD_06_FNRT_INFO :: CHUNKID [09:00] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_06_FNRT_INFO_CHUNKID_MASK     0x000003ff
+#define BCHP_VICE2_REGSET_MISC_DWORD_06_FNRT_INFO_CHUNKID_SHIFT    0
+
+/***************************************************************************
+ *MBOX - MBOX registers interface address offset.
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: MBOX :: INTERFACE [31:16] */
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_MASK                 0xffff0000
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_SHIFT                16
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_00_BVB_PIC_SIZE_OFFSET 0
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_01_SAMPLE_ASPECT_RATIO_OFFSET 4
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_02_PIC_INFO_OFFSET 8
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_03_ORIGINAL_PTS_OFFSET 12
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_04_STG_PICTURE_ID_OFFSET 16
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_05_BARDATA_INFO_OFFSET 20
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_06_FNRT_INFO_OFFSET 24
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_SIZE                 7
+
+/* VICE2_REGSET_MISC :: MBOX :: MAJORREVISION [15:08] */
+#define BCHP_VICE2_REGSET_MISC_MBOX_MAJORREVISION_MASK             0x0000ff00
+#define BCHP_VICE2_REGSET_MISC_MBOX_MAJORREVISION_SHIFT            8
+#define BCHP_VICE2_REGSET_MISC_MBOX_MAJORREVISION_ID               2
+
+/* VICE2_REGSET_MISC :: MBOX :: MINORREVISION [07:00] */
+#define BCHP_VICE2_REGSET_MISC_MBOX_MINORREVISION_MASK             0x000000ff
+#define BCHP_VICE2_REGSET_MISC_MBOX_MINORREVISION_SHIFT            0
+#define BCHP_VICE2_REGSET_MISC_MBOX_MINORREVISION_ID               0
+
+/***************************************************************************
+ *XPT_PB
+ ***************************************************************************/
+/***************************************************************************
+ *DESCRIPTOR_ABSTRACT - Playback Linked-List Descriptor Abstract
+ ***************************************************************************/
+/* XPT_PB :: DESCRIPTOR_ABSTRACT :: DESCRIPTOR_FORMAT [31:00] */
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_MASK     0xffffffff
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_SHIFT    0
+
+/***************************************************************************
+ *DESC_0 - Playback Linked-List Descriptor Word 0
+ ***************************************************************************/
+/* XPT_PB :: DESC_0 :: PB_BUFFER_START_ADDR [31:00] */
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_MASK               0xffffffff
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_SHIFT              0
+
+/***************************************************************************
+ *DESC_1 - Playback Linked-List Descriptor Word 1
+ ***************************************************************************/
+/* XPT_PB :: DESC_1 :: PB_BUFFER_LENGTH [31:00] */
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_MASK                   0xffffffff
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_SHIFT                  0
+
+/***************************************************************************
+ *DESC_2 - Playback Linked-List Descriptor Word 2
+ ***************************************************************************/
+/* XPT_PB :: DESC_2 :: PB_INTERRUPT_ENABLE [31:31] */
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_MASK                0x80000000
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_SHIFT               31
+
+/* XPT_PB :: DESC_2 :: PB_FORCE_RESYNC [30:30] */
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_MASK                    0x40000000
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_SHIFT                   30
+
+/* XPT_PB :: DESC_2 :: PB_HOST_DATA_INS_EN [29:29] */
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_MASK                0x20000000
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_SHIFT               29
+
+/* XPT_PB :: DESC_2 :: PUSH_PARTIAL_PACKET [28:28] */
+#define BCHP_XPT_PB_DESC_2_PUSH_PARTIAL_PACKET_MASK                0x10000000
+#define BCHP_XPT_PB_DESC_2_PUSH_PARTIAL_PACKET_SHIFT               28
+
+/* XPT_PB :: DESC_2 :: PB_DESC_TAG_ID [27:24] */
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_MASK                     0x0f000000
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_SHIFT                    24
+
+/* XPT_PB :: DESC_2 :: PB_DESC_BAND_ID_EN [23:23] */
+#define BCHP_XPT_PB_DESC_2_PB_DESC_BAND_ID_EN_MASK                 0x00800000
+#define BCHP_XPT_PB_DESC_2_PB_DESC_BAND_ID_EN_SHIFT                23
+
+/* XPT_PB :: DESC_2 :: PB_DESC_PARSER_SEL [22:22] */
+#define BCHP_XPT_PB_DESC_2_PB_DESC_PARSER_SEL_MASK                 0x00400000
+#define BCHP_XPT_PB_DESC_2_PB_DESC_PARSER_SEL_SHIFT                22
+
+/* XPT_PB :: DESC_2 :: PB_DESC_BAND_ID [21:16] */
+#define BCHP_XPT_PB_DESC_2_PB_DESC_BAND_ID_MASK                    0x003f0000
+#define BCHP_XPT_PB_DESC_2_PB_DESC_BAND_ID_SHIFT                   16
+
+/* XPT_PB :: DESC_2 :: reserved0 [15:00] */
+#define BCHP_XPT_PB_DESC_2_reserved0_MASK                          0x0000ffff
+#define BCHP_XPT_PB_DESC_2_reserved0_SHIFT                         0
+
+/***************************************************************************
+ *DESC_3 - Playback Linked-List Descriptor Word 3
+ ***************************************************************************/
+/* XPT_PB :: DESC_3 :: PB_NEXT_DESC_ADDR [31:04] */
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_MASK                  0xfffffff0
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_SHIFT                 4
+
+/* XPT_PB :: DESC_3 :: reserved0 [03:01] */
+#define BCHP_XPT_PB_DESC_3_reserved0_MASK                          0x0000000e
+#define BCHP_XPT_PB_DESC_3_reserved0_SHIFT                         1
+
+/* XPT_PB :: DESC_3 :: PB_LAST_DESC_IND [00:00] */
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_MASK                   0x00000001
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_SHIFT                  0
+
+/***************************************************************************
+ *DESC_4 - Playback Linked-List Descriptor Word 4
+ ***************************************************************************/
+/* XPT_PB :: DESC_4 :: reserved0 [31:00] */
+#define BCHP_XPT_PB_DESC_4_reserved0_MASK                          0xffffffff
+#define BCHP_XPT_PB_DESC_4_reserved0_SHIFT                         0
+
+/***************************************************************************
+ *DESC_5 - Playback Linked-List Descriptor Word 5
+ ***************************************************************************/
+/* XPT_PB :: DESC_5 :: reserved0 [31:03] */
+#define BCHP_XPT_PB_DESC_5_reserved0_MASK                          0xfffffff8
+#define BCHP_XPT_PB_DESC_5_reserved0_SHIFT                         3
+
+/* XPT_PB :: DESC_5 :: RANDOM_ACCESS_INDICATION [02:02] */
+#define BCHP_XPT_PB_DESC_5_RANDOM_ACCESS_INDICATION_MASK           0x00000004
+#define BCHP_XPT_PB_DESC_5_RANDOM_ACCESS_INDICATION_SHIFT          2
+
+/* XPT_PB :: DESC_5 :: NEXT_PACKET_PACING_TIMESTAMP_VALID [01:01] */
+#define BCHP_XPT_PB_DESC_5_NEXT_PACKET_PACING_TIMESTAMP_VALID_MASK 0x00000002
+#define BCHP_XPT_PB_DESC_5_NEXT_PACKET_PACING_TIMESTAMP_VALID_SHIFT 1
+
+/* XPT_PB :: DESC_5 :: PKT2PKT_PACING_TIMESTAMP_DELTA_VALID [00:00] */
+#define BCHP_XPT_PB_DESC_5_PKT2PKT_PACING_TIMESTAMP_DELTA_VALID_MASK 0x00000001
+#define BCHP_XPT_PB_DESC_5_PKT2PKT_PACING_TIMESTAMP_DELTA_VALID_SHIFT 0
+
+/***************************************************************************
+ *DESC_6 - Playback Linked-List Descriptor Word 6
+ ***************************************************************************/
+/* XPT_PB :: DESC_6 :: NEXT_PACKET_PACING_TIMESTAMP [31:00] */
+#define BCHP_XPT_PB_DESC_6_NEXT_PACKET_PACING_TIMESTAMP_MASK       0xffffffff
+#define BCHP_XPT_PB_DESC_6_NEXT_PACKET_PACING_TIMESTAMP_SHIFT      0
+
+/***************************************************************************
+ *DESC_7 - Playback Linked-List Descriptor Word 7
+ ***************************************************************************/
+/* XPT_PB :: DESC_7 :: PKT2PKT_PACING_TIMESTAMP_DELTA [31:00] */
+#define BCHP_XPT_PB_DESC_7_PKT2PKT_PACING_TIMESTAMP_DELTA_MASK     0xffffffff
+#define BCHP_XPT_PB_DESC_7_PKT2PKT_PACING_TIMESTAMP_DELTA_SHIFT    0
+
+/***************************************************************************
+ *XPT_RAVE
+ ***************************************************************************/
+/***************************************************************************
+ *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
+
+/***************************************************************************
+ *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
+
+/***************************************************************************
+ *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
+ ***************************************************************************/
+/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_DVD_AC3_AUDIO_ES_SETUP - ES Setup - DVD_AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_DVD_AC3_AUDIO_ES_SETUP :: DVD_AUDIO_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_DVD_AC3_AUDIO_ES_SETUP_DVD_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_DVD_AC3_AUDIO_ES_SETUP_DVD_AUDIO_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEI_DVD_LPCM_AUDIO_ES_SETUP - ES Setup - DVD_LPCM Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEI_DVD_LPCM_AUDIO_ES_SETUP :: DVD_AUDIO_LPCM_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEI_DVD_LPCM_AUDIO_ES_SETUP_DVD_AUDIO_LPCM_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEI_DVD_LPCM_AUDIO_ES_SETUP_DVD_AUDIO_LPCM_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
+
+#endif /* #ifndef BCHP_COMMON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_ddr40_phy_control_regs_0.h b/include/linux/brcmstb/7435b0/bchp_ddr40_phy_control_regs_0.h
new file mode 100644
index 0000000..51ce86f
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_ddr40_phy_control_regs_0.h
@@ -0,0 +1,1513 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:12 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_ddr40_phy_control_regs_0.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 2:04p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_CONTROL_REGS_0 - DDR40 DDR40 physical interface control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION   0x003b6000 /* Address & Control revision register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL 0x003b6004 /* PHY clock power management control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS 0x003b6010 /* PHY PLL status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG 0x003b6014 /* PHY PLL configuration register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL 0x003b6018 /* PHY PLL control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS 0x003b601c /* PHY PLL dividers control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL 0x003b6020 /* Aux Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL 0x003b6030 /* Address & Control coarse VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL 0x003b6034 /* Address & Control fine VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL 0x003b6038 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL 0x003b603c /* PVT Compensation control and status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL 0x003b6040 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS 0x003b6044 /* PHY Auto Init rd_data_dly result register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE 0x003b6048 /* PHY VDL calibration control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS 0x003b604c /* PHY VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS 0x003b6050 /* PHY DQ VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS 0x003b6054 /* PHY Write Channel VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS 0x003b6058 /* PHY Read Enable VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL 0x003b605c /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS 0x003b6060 /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS 0x003b6064 /* Virtual VTT Connections register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE 0x003b6068 /* Virtual VTT Override register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL 0x003b606c /* VREF DAC Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL 0x003b6070 /* PhyBist Control Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED 0x003b6074 /* PhyBist Seed Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS 0x003b6078 /* PhyBist General Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS 0x003b607c /* PhyBist Per-Bit Control Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS 0x003b6080 /* PhyBist Per-Bit DQ Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS 0x003b6084 /* PhyBist Per-Bit DM and CK Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG 0x003b6090 /* DRAM Command Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0  0x003b6094 /* Mode Register 0 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1  0x003b6098 /* Mode Register 1 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2  0x003b609c /* Mode Register 2 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3  0x003b60a0 /* Mode Register 3 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL 0x003b60a4 /* Standby Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL 0x003b60b0 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2 0x003b60b4 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS 0x003b60b8 /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2 0x003b60bc /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE 0x003b60c0 /* Freeze-on-error enable register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK 0x003b60c4 /* Datapth Loopback control register */
+
+/***************************************************************************
+ *REVISION - Address & Control revision register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_MASK      0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_SHIFT     16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_MASK          0x0000ff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_SHIFT         8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_DEFAULT       0x00000040
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_MASK          0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_DEFAULT       0x00000005
+
+/***************************************************************************
+ *CLK_PM_CTRL - PHY clock power management control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_MASK   0xfffffffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_SHIFT  1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_STATUS - PHY PLL status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_MASK    0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_SHIFT   27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK_LOST [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_MASK    0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_SHIFT   26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: DDR_MHZ [25:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_MASK      0x03ffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_SHIFT     14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_4X [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: STATUS [12:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_MASK       0x00001ffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_SHIFT      1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_MASK         0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_CONFIG - PHY PLL configuration register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved0 [31:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_MASK    0xffffff80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_SHIFT   7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LP40_PLL_POST_RESET [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET_POST_DIV [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LDO_CTRL [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_MASK     0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_SHIFT    3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_DEFAULT  0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved1 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_MASK    0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_SHIFT   2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_MASK        0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_SHIFT       1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_DEFAULT     0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PWRDN [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_MASK        0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_SHIFT       0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PLL_CONTROL - PHY PLL control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: reserved0 [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_SHIFT  31
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_kp [30:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_MASK        0x78000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_SHIFT       27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_DEFAULT     0x0000000a
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ki [26:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_MASK        0x07000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_SHIFT       24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_DEFAULT     0x00000003
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ka [23:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_MASK        0x00e00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_SHIFT       21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_DEFAULT     0x00000003
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: PLL_CONTROL [20:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_MASK 0x001fffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_DIVIDERS - PHY PLL dividers control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_MASK  0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_SHIFT 16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_HI [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_MASK 0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_LO [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: POST_DIV [13:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_MASK   0x00003800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_SHIFT  11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_DEFAULT 0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: PDIV [10:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_MASK       0x00000700
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_SHIFT      8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_DEFAULT    0x00000004
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_MASK       0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_DEFAULT    0x00000020
+
+/***************************************************************************
+ *AUX_CONTROL - Aux Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved0 [31:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_MASK   0xfffffc00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_SHIFT  10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_cs [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_MASK       0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_SHIFT      7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_ad [06:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_MASK       0x00000070
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_SHIFT      4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_odt [03:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_MASK      0x0000000e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_SHIFT     1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: override [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_CTL - Address & Control coarse VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BIT_CTL - Address & Control fine VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_SHIFT  31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved0 [30:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ffffe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: rxenb [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_MASK  0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved1 [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_SHIFT 7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_reb [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ZQ_PVT_COMP_CTL - PVT Compensation control and status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: update_mode [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_done [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_done [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_done [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: auto_sample_en [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_MASK 0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_en [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_ovr_en [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_ovr_en [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_comp [17:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_MASK 0x00038000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_comp [14:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_MASK 0x00007000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [11:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_MASK 0x00000e00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [08:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_MASK 0x000001c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: auto_oeb [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a15 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_MASK  0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a14 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_MASK  0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a13 [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_MASK  0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_aux [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_MASK  0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: half_strength [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_MASK     0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_SHIFT    2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_MASK  0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_MASK     0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_SHIFT    0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_DEFAULT  0x00000000
+
+/***************************************************************************
+ *VDL_RD_DATA_DLY_STATUS - PHY Auto Init rd_data_dly result register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_SHIFT 12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: auto_init_state [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_MASK 0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_max [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_min [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_DEFAULT 0x00000007
+
+/***************************************************************************
+ *VDL_CALIBRATE - PHY VDL calibration control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_SHIFT 29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: use_straps [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: auto_init [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: skip_rst [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_MASK  0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_SHIFT 26
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: exit_in_sr [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_dly_cal [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_refresh [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_wr_dq [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: dq0_only [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_MASK  0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_mr_mpr [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_cal [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_MASK   0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_SHIFT  19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_en_cal [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_clocks [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_pair [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_steps [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_auto [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_ftm [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_phybist [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_byte [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_clocks [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_test [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_always [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_once [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_fast [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CALIB_STATUS - PHY VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_MASK 0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_fail [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_MASK 0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_SHIFT 29
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_done [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_rd_data_dly_error [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_read_en_error [26:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_MASK 0x07800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_error [22:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_MASK 0x00780000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_sel [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_total [11:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_MASK 0x00000ffc
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VDL_DQ_CALIB_STATUS - PHY DQ VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_total [25:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_MASK 0x03ff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_clocks [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_mode [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_WR_CHAN_CALIB_STATUS - PHY Write Channel VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_RD_EN_CALIB_STATUS - PHY Read Enable VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: low_vtt [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: high_vtt [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: error_reset [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_ctl_idle [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cs_idle [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cke_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error [18:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_MASK 0x0007fff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_low [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_high [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ready [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_DEFAULT 0x00ffffff
+
+/***************************************************************************
+ *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_DEFAULT 0x0003ffff
+
+/***************************************************************************
+ *VREF_DAC_CONTROL - VREF DAC Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK1_GT_INT [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK0_GT_INT [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_GT_INT [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: EXT_GT_INT [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_TESTOUT_MUX_CTL [16:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_MASK 0x00018000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TEST [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_MASK   0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_SHIFT  14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_MASK   0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_SHIFT  13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_MASK   0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_SHIFT  12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_MASK   0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_SHIFT  6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_DEFAULT 0x00000020
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_MASK   0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_SHIFT  0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_DEFAULT 0x00000020
+
+/***************************************************************************
+ *PHYBIST_CNTRL - PhyBist Control Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_error_sel [13:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_MASK 0x00003f00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved1 [07:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_MASK 0x000000e0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_SHIFT 5
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: bench_mode [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_dat_error [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_ctl_error [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: int_loopback [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHYBIST_SEED - PhyBist Seed Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_SEED :: seed [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_MASK       0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_DEFAULT    0x250e4af6
+
+/***************************************************************************
+ *PHYBIST_STATUS - PhyBist General Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_pass [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_pass [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_SHIFT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_done [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_done [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: ctl_errors [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_DQ_STATUS - PhyBist Per-Bit DQ Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_STATUS :: dat_errors [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_MASK 0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_MISC_STATUS - PhyBist Per-Bit DM and CK Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: ck_errors [07:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_MASK 0x000000f0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: dm_errors [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_SHIFT 0
+
+/***************************************************************************
+ *COMMAND_REG - DRAM Command Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_MASK   0xfe000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_SHIFT  25
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: aux [24:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_MASK         0x01c00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_SHIFT        22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: we [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_MASK          0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_SHIFT         21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_DEFAULT       0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: cas [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_MASK         0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_SHIFT        20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ras [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_MASK         0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_SHIFT        19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ba [18:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_MASK          0x00070000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_SHIFT         16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_DEFAULT       0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_MASK          0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_DEFAULT       0x00000000
+
+/***************************************************************************
+ *MODE_REG0 - Mode Register 0
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG1 - Mode Register 1
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG2 - Mode Register 2
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG3 - Mode Register 3
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STANDBY_CONTROL - Standby Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_ready [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_exit_pin_en [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_active [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: armed [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_MASK   0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_SHIFT  15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: warmstart [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_ldo_volts [13:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_MASK 0x00003000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_skip_mrs [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_rst_n [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_cke [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: ldo_volts [08:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_MASK 0x00000180
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_DEFAULT 0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: skip_mrs [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: rst_n [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_MASK   0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_SHIFT  5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: cke [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_MASK     0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_SHIFT    4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_CONTROL - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: reserved0 [31:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_MASK 0xf0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_MASK       0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_SHIFT      16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_MASK  0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_MASK 0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_MASK     0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_SHIFT    12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_MASK      0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_SHIFT     11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_MASK      0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_SHIFT     8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_CONTROL2 - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_MASK     0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_SHIFT    20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_MASK       0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_SHIFT      17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_MASK       0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_SHIFT      12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_MASK      0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_SHIFT     7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_MASK       0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_DEFAULT    0x00000000
+
+/***************************************************************************
+ *STRAP_STATUS - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_MASK  0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_reg [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_MASK   0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_SHIFT  29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_memc [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_MASK  0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_MASK        0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_SHIFT       16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_MASK   0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_SHIFT  14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_MASK      0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_SHIFT     12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_MASK       0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_SHIFT      11
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_SHIFT 10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_MASK       0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_SHIFT      8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_MASK  0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_SHIFT 0
+
+/***************************************************************************
+ *STRAP_STATUS2 - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_MASK      0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_SHIFT     20
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_MASK        0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_SHIFT       17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_MASK        0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_SHIFT       12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_MASK       0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_SHIFT      7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_MASK        0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_SHIFT       0
+
+/***************************************************************************
+ *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl1 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl0 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl1 [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl0 [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DATAPATH_LOOPBACK - Datapth Loopback control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: xor_dm_rd_en [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: use_addr_ctl [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_ddr40_phy_control_regs_1.h b/include/linux/brcmstb/7435b0/bchp_ddr40_phy_control_regs_1.h
new file mode 100644
index 0000000..3a2b509
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_ddr40_phy_control_regs_1.h
@@ -0,0 +1,1510 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Jul 20 15:43:14 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_CONTROL_REGS_1_H__
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_H__
+
+/***************************************************************************
+ *DDR40_PHY_CONTROL_REGS_1 - DDR40 DDR40 physical interface control registers 1
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_REVISION   0x003c6000 /* Address & Control revision register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_CLK_PM_CTRL 0x003c6004 /* PHY clock power management control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_STATUS 0x003c6010 /* PHY PLL status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG 0x003c6014 /* PHY PLL configuration register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONTROL 0x003c6018 /* PHY PLL control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_DIVIDERS 0x003c601c /* PHY PLL dividers control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_AUX_CONTROL 0x003c6020 /* Aux Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BYTE_CTL 0x003c6030 /* Address & Control coarse VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BIT_CTL 0x003c6034 /* Address & Control fine VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL 0x003c6038 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL 0x003c603c /* PVT Compensation control and status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL 0x003c6040 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_DATA_DLY_STATUS 0x003c6044 /* PHY Auto Init rd_data_dly result register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE 0x003c6048 /* PHY VDL calibration control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS 0x003c604c /* PHY VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS 0x003c6050 /* PHY DQ VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS 0x003c6054 /* PHY Write Channel VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS 0x003c6058 /* PHY Read Enable VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL 0x003c605c /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS 0x003c6060 /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONNECTIONS 0x003c6064 /* Virtual VTT Connections register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_OVERRIDE 0x003c6068 /* Virtual VTT Override register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL 0x003c606c /* VREF DAC Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL 0x003c6070 /* PhyBist Control Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_SEED 0x003c6074 /* PhyBist Seed Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_STATUS 0x003c6078 /* PhyBist General Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CTL_STATUS 0x003c607c /* PhyBist Per-Bit Control Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_DQ_STATUS 0x003c6080 /* PhyBist Per-Bit DQ Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_MISC_STATUS 0x003c6084 /* PhyBist Per-Bit DM and CK Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_COMMAND_REG 0x003c6090 /* DRAM Command Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG0  0x003c6094 /* Mode Register 0 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG1  0x003c6098 /* Mode Register 1 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG2  0x003c609c /* Mode Register 2 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG3  0x003c60a0 /* Mode Register 3 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL 0x003c60a4 /* Standby Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL 0x003c60b0 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL2 0x003c60b4 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS 0x003c60b8 /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS2 0x003c60bc /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE 0x003c60c0 /* Freeze-on-error enable register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DATAPATH_LOOPBACK 0x003c60c4 /* Datapth Loopback control register */
+
+/***************************************************************************
+ *REVISION - Address & Control revision register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: REVISION :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_REVISION_reserved0_MASK      0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_REVISION_reserved0_SHIFT     16
+
+/* DDR40_PHY_CONTROL_REGS_1 :: REVISION :: MAJOR [15:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_REVISION_MAJOR_MASK          0x0000ff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_REVISION_MAJOR_SHIFT         8
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_REVISION_MAJOR_DEFAULT       0x00000040
+
+/* DDR40_PHY_CONTROL_REGS_1 :: REVISION :: MINOR [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_REVISION_MINOR_MASK          0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_REVISION_MINOR_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_REVISION_MINOR_DEFAULT       0x00000005
+
+/***************************************************************************
+ *CLK_PM_CTRL - PHY clock power management control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: CLK_PM_CTRL :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_CLK_PM_CTRL_reserved0_MASK   0xfffffffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_CLK_PM_CTRL_reserved0_SHIFT  1
+
+/* DDR40_PHY_CONTROL_REGS_1 :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_CLK_PM_CTRL_DIS_DDR_CLK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_STATUS - PHY PLL status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_STATUS_reserved0_MASK    0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_STATUS_reserved0_SHIFT   27
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_STATUS :: LOCK_LOST [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_STATUS_LOCK_LOST_MASK    0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_STATUS_LOCK_LOST_SHIFT   26
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_STATUS :: DDR_MHZ [25:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_STATUS_DDR_MHZ_MASK      0x03ffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_STATUS_DDR_MHZ_SHIFT     14
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_STATUS :: CLOCKING_4X [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_STATUS_CLOCKING_4X_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_STATUS_CLOCKING_4X_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_STATUS :: STATUS [12:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_STATUS_STATUS_MASK       0x00001ffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_STATUS_STATUS_SHIFT      1
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_STATUS :: LOCK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_STATUS_LOCK_MASK         0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_CONFIG - PHY PLL configuration register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: reserved0 [31:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG_reserved0_MASK    0xffffff80
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG_reserved0_SHIFT   7
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: LP40_PLL_POST_RESET [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG_LP40_PLL_POST_RESET_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG_LP40_PLL_POST_RESET_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG_LP40_PLL_POST_RESET_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: RESET_POST_DIV [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG_RESET_POST_DIV_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: LDO_CTRL [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG_LDO_CTRL_MASK     0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG_LDO_CTRL_SHIFT    3
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG_LDO_CTRL_DEFAULT  0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: reserved1 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG_reserved1_MASK    0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG_reserved1_SHIFT   2
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: RESET [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG_RESET_MASK        0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG_RESET_SHIFT       1
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG_RESET_DEFAULT     0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_CONFIG :: PWRDN [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG_PWRDN_MASK        0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG_PWRDN_SHIFT       0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG_PWRDN_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PLL_CONTROL - PHY PLL control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_CONTROL :: reserved0 [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONTROL_reserved0_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONTROL_reserved0_SHIFT  31
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_CONTROL :: i_kp [30:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONTROL_i_kp_MASK        0x78000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONTROL_i_kp_SHIFT       27
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONTROL_i_kp_DEFAULT     0x0000000a
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_CONTROL :: i_ki [26:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONTROL_i_ki_MASK        0x07000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONTROL_i_ki_SHIFT       24
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONTROL_i_ki_DEFAULT     0x00000003
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_CONTROL :: i_ka [23:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONTROL_i_ka_MASK        0x00e00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONTROL_i_ka_SHIFT       21
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONTROL_i_ka_DEFAULT     0x00000003
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_CONTROL :: PLL_CONTROL [20:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONTROL_PLL_CONTROL_MASK 0x001fffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONTROL_PLL_CONTROL_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONTROL_PLL_CONTROL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_DIVIDERS - PHY PLL dividers control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_DIVIDERS :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_DIVIDERS_reserved0_MASK  0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_DIVIDERS_reserved0_SHIFT 16
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_DIVIDERS :: NDIV_40LP_HI [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_DIVIDERS_NDIV_40LP_HI_MASK 0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_DIVIDERS_NDIV_40LP_HI_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_DIVIDERS_NDIV_40LP_HI_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_DIVIDERS :: NDIV_40LP_LO [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_DIVIDERS_NDIV_40LP_LO_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_DIVIDERS_NDIV_40LP_LO_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_DIVIDERS_NDIV_40LP_LO_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_DIVIDERS :: POST_DIV [13:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_DIVIDERS_POST_DIV_MASK   0x00003800
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_DIVIDERS_POST_DIV_SHIFT  11
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_DIVIDERS_POST_DIV_DEFAULT 0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_DIVIDERS :: PDIV [10:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_DIVIDERS_PDIV_MASK       0x00000700
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_DIVIDERS_PDIV_SHIFT      8
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_DIVIDERS_PDIV_DEFAULT    0x00000004
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PLL_DIVIDERS :: NDIV [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_DIVIDERS_NDIV_MASK       0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_DIVIDERS_NDIV_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_DIVIDERS_NDIV_DEFAULT    0x00000020
+
+/***************************************************************************
+ *AUX_CONTROL - Aux Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: AUX_CONTROL :: reserved0 [31:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_AUX_CONTROL_reserved0_MASK   0xfffffc00
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_AUX_CONTROL_reserved0_SHIFT  10
+
+/* DDR40_PHY_CONTROL_REGS_1 :: AUX_CONTROL :: is_cs [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_AUX_CONTROL_is_cs_MASK       0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_AUX_CONTROL_is_cs_SHIFT      7
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_AUX_CONTROL_is_cs_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: AUX_CONTROL :: is_ad [06:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_AUX_CONTROL_is_ad_MASK       0x00000070
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_AUX_CONTROL_is_ad_SHIFT      4
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_AUX_CONTROL_is_ad_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: AUX_CONTROL :: is_odt [03:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_AUX_CONTROL_is_odt_MASK      0x0000000e
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_AUX_CONTROL_is_odt_SHIFT     1
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_AUX_CONTROL_is_odt_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: AUX_CONTROL :: override [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_AUX_CONTROL_override_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_AUX_CONTROL_override_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_AUX_CONTROL_override_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_CTL - Address & Control coarse VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_OVRIDE_BYTE_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BYTE_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BYTE_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BYTE_CTL_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_OVRIDE_BYTE_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BYTE_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BYTE_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_OVRIDE_BYTE_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BYTE_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BYTE_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BYTE_CTL_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_OVRIDE_BYTE_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BYTE_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BYTE_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_OVRIDE_BYTE_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BYTE_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BYTE_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BYTE_CTL_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_OVRIDE_BYTE_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BYTE_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BYTE_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_OVRIDE_BYTE_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BYTE_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BYTE_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BYTE_CTL_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BIT_CTL - Address & Control fine VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_OVRIDE_BIT_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BIT_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BIT_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BIT_CTL_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_OVRIDE_BIT_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BIT_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BIT_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_OVRIDE_BIT_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BIT_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BIT_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BIT_CTL_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_OVRIDE_BIT_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BIT_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BIT_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_OVRIDE_BIT_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BIT_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BIT_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BIT_CTL_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_OVRIDE_BIT_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BIT_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BIT_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_OVRIDE_BIT_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BIT_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BIT_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_OVRIDE_BIT_CTL_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_idle_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_idle_SHIFT  31
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: IDLE_PAD_CONTROL :: reserved0 [30:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_reserved0_MASK 0x7ffffe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_reserved0_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_1 :: IDLE_PAD_CONTROL :: rxenb [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_rxenb_MASK  0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_rxenb_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_1 :: IDLE_PAD_CONTROL :: reserved1 [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_reserved1_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_reserved1_SHIFT 7
+
+/* DDR40_PHY_CONTROL_REGS_1 :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_ctl_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_ctl_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_ctl_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_ctl_reb_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_ctl_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_1 :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_ctl_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_ctl_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_ctl_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_1 :: IDLE_PAD_CONTROL :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_1 :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_cke_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_cke_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_cke_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: IDLE_PAD_CONTROL :: cke_reb [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_cke_reb_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_cke_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_1 :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_cke_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_cke_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL_cke_oeb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ZQ_PVT_COMP_CTL - PVT Compensation control and status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: ZQ_PVT_COMP_CTL :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_1 :: ZQ_PVT_COMP_CTL :: update_mode [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_update_mode_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_update_mode_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_update_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: ZQ_PVT_COMP_CTL :: pd_done [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_pd_done_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_pd_done_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_pd_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: ZQ_PVT_COMP_CTL :: nd_done [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_nd_done_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_nd_done_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_nd_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: ZQ_PVT_COMP_CTL :: sample_done [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_sample_done_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_sample_done_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_sample_done_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_1 :: ZQ_PVT_COMP_CTL :: auto_sample_en [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_auto_sample_en_MASK 0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_auto_sample_en_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_auto_sample_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: ZQ_PVT_COMP_CTL :: sample_en [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_sample_en_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_sample_en_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_sample_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: ZQ_PVT_COMP_CTL :: addr_ovr_en [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_addr_ovr_en_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_addr_ovr_en_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_addr_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: ZQ_PVT_COMP_CTL :: dq_ovr_en [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_dq_ovr_en_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_dq_ovr_en_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_dq_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: ZQ_PVT_COMP_CTL :: pd_comp [17:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_pd_comp_MASK 0x00038000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_pd_comp_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_pd_comp_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: ZQ_PVT_COMP_CTL :: nd_comp [14:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_nd_comp_MASK 0x00007000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_nd_comp_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_nd_comp_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [11:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_addr_pd_override_val_MASK 0x00000e00
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_addr_pd_override_val_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_addr_pd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [08:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_addr_nd_override_val_MASK 0x000001c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_addr_nd_override_val_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_addr_nd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_dq_pd_override_val_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_dq_pd_override_val_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_dq_pd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_dq_nd_override_val_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_dq_nd_override_val_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_ZQ_PVT_COMP_CTL_dq_nd_override_val_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: DRIVE_PAD_CTL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_1 :: DRIVE_PAD_CTL :: auto_oeb [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_auto_oeb_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_auto_oeb_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_auto_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: DRIVE_PAD_CTL :: iddq_a15 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_iddq_a15_MASK  0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_iddq_a15_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_iddq_a15_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: DRIVE_PAD_CTL :: iddq_a14 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_iddq_a14_MASK  0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_iddq_a14_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_iddq_a14_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: DRIVE_PAD_CTL :: iddq_a13 [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_iddq_a13_MASK  0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_iddq_a13_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_iddq_a13_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: DRIVE_PAD_CTL :: iddq_aux [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_iddq_aux_MASK  0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_iddq_aux_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_iddq_aux_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: DRIVE_PAD_CTL :: half_strength [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_half_strength_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_half_strength_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_half_strength_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_rt60b_MASK     0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_rt60b_SHIFT    2
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_rt60b_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_rt120b_g_MASK  0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_rt120b_g_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_rt120b_g_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_1 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_g_ddr_MASK     0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_g_ddr_SHIFT    0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DRIVE_PAD_CTL_g_ddr_DEFAULT  0x00000000
+
+/***************************************************************************
+ *VDL_RD_DATA_DLY_STATUS - PHY Auto Init rd_data_dly result register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_RD_DATA_DLY_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_DATA_DLY_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_DATA_DLY_STATUS_reserved0_SHIFT 12
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_RD_DATA_DLY_STATUS :: auto_init_state [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_DATA_DLY_STATUS_auto_init_state_MASK 0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_DATA_DLY_STATUS_auto_init_state_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_DATA_DLY_STATUS_auto_init_state_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_max [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_min [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_DEFAULT 0x00000007
+
+/***************************************************************************
+ *VDL_CALIBRATE - PHY VDL calibration control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_reserved0_SHIFT 29
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: use_straps [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_use_straps_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_use_straps_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_use_straps_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: auto_init [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_auto_init_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_auto_init_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_auto_init_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: skip_rst [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_skip_rst_MASK  0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_skip_rst_SHIFT 26
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_skip_rst_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: exit_in_sr [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_exit_in_sr_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_exit_in_sr_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_exit_in_sr_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: rd_dly_cal [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_rd_dly_cal_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_rd_dly_cal_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_rd_dly_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: bit_refresh [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_bit_refresh_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_bit_refresh_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_bit_refresh_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: set_wr_dq [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_set_wr_dq_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_set_wr_dq_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_set_wr_dq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: dq0_only [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_dq0_only_MASK  0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_dq0_only_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_dq0_only_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: set_mr_mpr [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_set_mr_mpr_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_set_mr_mpr_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_set_mr_mpr_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: bit_cal [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_bit_cal_MASK   0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_bit_cal_SHIFT  19
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_bit_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: rd_en_cal [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_rd_en_cal_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_rd_en_cal_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_rd_en_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: calib_dqs_clocks [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_dqs_clocks_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_dqs_clocks_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_dqs_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: calib_dqs_pair [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_dqs_pair_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_dqs_pair_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_dqs_pair_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: calib_steps [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_steps_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_steps_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_steps_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: calib_auto [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_auto_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_auto_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_auto_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: calib_ftm [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_ftm_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_ftm_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_ftm_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: calib_phybist [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_phybist_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_phybist_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_phybist_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: calib_byte [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_byte_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_byte_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_byte_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: calib_clocks [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_clocks_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_clocks_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: calib_test [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_test_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_test_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_test_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: calib_always [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_always_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_always_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_always_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: calib_once [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_once_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_once_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_once_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIBRATE :: calib_fast [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_fast_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_fast_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIBRATE_calib_fast_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CALIB_STATUS - PHY VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_reserved0_MASK 0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS :: auto_init_fail [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_auto_init_fail_MASK 0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_auto_init_fail_SHIFT 29
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_auto_init_fail_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS :: auto_init_done [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_auto_init_done_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_auto_init_done_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_auto_init_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS :: calib_rd_data_dly_error [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_rd_data_dly_error_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_rd_data_dly_error_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_rd_data_dly_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS :: calib_read_en_error [26:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_read_en_error_MASK 0x07800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_read_en_error_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_read_en_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS :: calib_byte_error [22:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_byte_error_MASK 0x00780000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_byte_error_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_byte_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS :: calib_byte_sel [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_byte_sel_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_byte_sel_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS :: calib_total [11:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_total_MASK 0x00000ffc
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_total_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS :: calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_lock_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_CALIB_STATUS :: calib_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_CALIB_STATUS_calib_idle_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VDL_DQ_CALIB_STATUS - PHY DQ VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_DQ_CALIB_STATUS :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_DQ_CALIB_STATUS :: dqs_calib_total [25:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS_dqs_calib_total_MASK 0x03ff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS_dqs_calib_total_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS_dqs_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_DQ_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_DQ_CALIB_STATUS :: dq_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS_dq_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS_dq_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS_dq_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_DQ_CALIB_STATUS :: dqs_calib_clocks [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_DQ_CALIB_STATUS :: dqs_calib_mode [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS_dqs_calib_mode_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS_dqs_calib_mode_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS_dqs_calib_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_DQ_CALIB_STATUS :: dqs_calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS_dqs_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS_dqs_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS_dqs_calib_lock_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_DQ_CALIB_STATUS :: dq_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS_dq_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS_dq_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_DQ_CALIB_STATUS_dq_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_WR_CHAN_CALIB_STATUS - PHY Write Channel VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_WR_CHAN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_WR_CHAN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_WR_CHAN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_RD_EN_CALIB_STATUS - PHY Read Enable VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_RD_EN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_RD_EN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_RD_EN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_CONTROL :: low_vtt [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_low_vtt_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_low_vtt_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_low_vtt_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_CONTROL :: high_vtt [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_high_vtt_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_high_vtt_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_high_vtt_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_CONTROL :: error_reset [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_error_reset_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_error_reset_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_error_reset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_CONTROL :: enable_ctl_idle [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_enable_ctl_idle_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_enable_ctl_idle_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_enable_ctl_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_CONTROL :: enable_cs_idle [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_enable_cs_idle_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_enable_cs_idle_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_enable_cs_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_CONTROL :: enable_cke_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_enable_cke_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_enable_cke_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONTROL_enable_cke_idle_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_STATUS :: error [18:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_error_MASK 0x0007fff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_STATUS :: error_low [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_error_low_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_error_low_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_error_low_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_STATUS :: error_high [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_error_high_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_error_high_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_error_high_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_STATUS :: ready [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_ready_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_ready_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_STATUS_ready_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_CONNECTIONS :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONNECTIONS_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONNECTIONS_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_CONNECTIONS_mask_DEFAULT 0x00ffffff
+
+/***************************************************************************
+ *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VIRTUAL_VTT_OVERRIDE :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_OVERRIDE_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_OVERRIDE_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VIRTUAL_VTT_OVERRIDE_mask_DEFAULT 0x0003ffff
+
+/***************************************************************************
+ *VREF_DAC_CONTROL - VREF DAC Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: VREF_DAC_CONTROL :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VREF_DAC_CONTROL :: LDO_CK1_GT_INT [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_LDO_CK1_GT_INT_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_LDO_CK1_GT_INT_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_LDO_CK1_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VREF_DAC_CONTROL :: LDO_CK0_GT_INT [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_LDO_CK0_GT_INT_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_LDO_CK0_GT_INT_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_LDO_CK0_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VREF_DAC_CONTROL :: LDO_GT_INT [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_LDO_GT_INT_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_LDO_GT_INT_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_LDO_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VREF_DAC_CONTROL :: EXT_GT_INT [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_EXT_GT_INT_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_EXT_GT_INT_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_EXT_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VREF_DAC_CONTROL :: LDO_TESTOUT_MUX_CTL [16:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_MASK 0x00018000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VREF_DAC_CONTROL :: TEST [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_TEST_MASK   0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_TEST_SHIFT  14
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_TEST_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_PDN1_MASK   0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_PDN1_SHIFT  13
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_PDN1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_PDN0_MASK   0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_PDN0_SHIFT  12
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_PDN0_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_DAC1_MASK   0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_DAC1_SHIFT  6
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_DAC1_DEFAULT 0x00000020
+
+/* DDR40_PHY_CONTROL_REGS_1 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_DAC0_MASK   0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_DAC0_SHIFT  0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_VREF_DAC_CONTROL_DAC0_DEFAULT 0x00000020
+
+/***************************************************************************
+ *PHYBIST_CNTRL - PhyBist Control Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: force_error_sel [13:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_force_error_sel_MASK 0x00003f00
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_force_error_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_force_error_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: reserved1 [07:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_reserved1_MASK 0x000000e0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_reserved1_SHIFT 5
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: bench_mode [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_bench_mode_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_bench_mode_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_bench_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: force_dat_error [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_force_dat_error_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_force_dat_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_force_dat_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: force_ctl_error [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_force_ctl_error_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_force_ctl_error_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_force_ctl_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: int_loopback [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_int_loopback_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_int_loopback_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_int_loopback_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PHYBIST_CNTRL :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_enable_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_enable_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CNTRL_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHYBIST_SEED - PhyBist Seed Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: PHYBIST_SEED :: seed [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_SEED_seed_MASK       0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_SEED_seed_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_SEED_seed_DEFAULT    0x250e4af6
+
+/***************************************************************************
+ *PHYBIST_STATUS - PhyBist General Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: PHYBIST_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_STATUS_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PHYBIST_STATUS :: dat_pass [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_STATUS_dat_pass_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_STATUS_dat_pass_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PHYBIST_STATUS :: ctl_pass [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_STATUS_ctl_pass_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_STATUS_ctl_pass_SHIFT 2
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PHYBIST_STATUS :: dat_done [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_STATUS_dat_done_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_STATUS_dat_done_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PHYBIST_STATUS :: ctl_done [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_STATUS_ctl_done_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_STATUS_ctl_done_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CTL_STATUS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CTL_STATUS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PHYBIST_CTL_STATUS :: ctl_errors [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CTL_STATUS_ctl_errors_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_CTL_STATUS_ctl_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_DQ_STATUS - PhyBist Per-Bit DQ Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: PHYBIST_DQ_STATUS :: dat_errors [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_DQ_STATUS_dat_errors_MASK 0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_DQ_STATUS_dat_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_MISC_STATUS - PhyBist Per-Bit DM and CK Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: PHYBIST_MISC_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_MISC_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_MISC_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PHYBIST_MISC_STATUS :: ck_errors [07:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_MISC_STATUS_ck_errors_MASK 0x000000f0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_MISC_STATUS_ck_errors_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_1 :: PHYBIST_MISC_STATUS :: dm_errors [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_MISC_STATUS_dm_errors_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_PHYBIST_MISC_STATUS_dm_errors_SHIFT 0
+
+/***************************************************************************
+ *COMMAND_REG - DRAM Command Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: COMMAND_REG :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_COMMAND_REG_reserved0_MASK   0xfe000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_COMMAND_REG_reserved0_SHIFT  25
+
+/* DDR40_PHY_CONTROL_REGS_1 :: COMMAND_REG :: aux [24:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_COMMAND_REG_aux_MASK         0x01c00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_COMMAND_REG_aux_SHIFT        22
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_COMMAND_REG_aux_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: COMMAND_REG :: we [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_COMMAND_REG_we_MASK          0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_COMMAND_REG_we_SHIFT         21
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_COMMAND_REG_we_DEFAULT       0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: COMMAND_REG :: cas [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_COMMAND_REG_cas_MASK         0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_COMMAND_REG_cas_SHIFT        20
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_COMMAND_REG_cas_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: COMMAND_REG :: ras [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_COMMAND_REG_ras_MASK         0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_COMMAND_REG_ras_SHIFT        19
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_COMMAND_REG_ras_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: COMMAND_REG :: ba [18:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_COMMAND_REG_ba_MASK          0x00070000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_COMMAND_REG_ba_SHIFT         16
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_COMMAND_REG_ba_DEFAULT       0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: COMMAND_REG :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_COMMAND_REG_ad_MASK          0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_COMMAND_REG_ad_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_COMMAND_REG_ad_DEFAULT       0x00000000
+
+/***************************************************************************
+ *MODE_REG0 - Mode Register 0
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: MODE_REG0 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG0_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG0_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_1 :: MODE_REG0 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG0_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG0_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG0_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: MODE_REG0 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG0_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG0_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG0_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG1 - Mode Register 1
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: MODE_REG1 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG1_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG1_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_1 :: MODE_REG1 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG1_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG1_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG1_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: MODE_REG1 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG1_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG1_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG1_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG2 - Mode Register 2
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: MODE_REG2 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG2_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG2_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_1 :: MODE_REG2 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG2_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG2_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG2_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: MODE_REG2 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG2_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG2_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG2_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG3 - Mode Register 3
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: MODE_REG3 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG3_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG3_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_1 :: MODE_REG3 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG3_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG3_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG3_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: MODE_REG3 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG3_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG3_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_MODE_REG3_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STANDBY_CONTROL - Standby Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: standby_ready [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_standby_ready_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_standby_ready_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_standby_ready_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: standby_exit_pin_en [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_standby_exit_pin_en_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_standby_exit_pin_en_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_standby_exit_pin_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: standby_active [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_standby_active_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_standby_active_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_standby_active_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: armed [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_armed_MASK   0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_armed_SHIFT  15
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_armed_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: warmstart [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_warmstart_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_warmstart_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_warmstart_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: pwrdown_ldo_volts [13:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_pwrdown_ldo_volts_MASK 0x00003000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_pwrdown_ldo_volts_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_pwrdown_ldo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: pwrdown_skip_mrs [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_pwrdown_skip_mrs_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_pwrdown_skip_mrs_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_pwrdown_skip_mrs_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: pwrdown_rst_n [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_pwrdown_rst_n_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_pwrdown_rst_n_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_pwrdown_rst_n_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: pwrdown_cke [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_pwrdown_cke_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_pwrdown_cke_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_pwrdown_cke_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: ldo_volts [08:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_ldo_volts_MASK 0x00000180
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_ldo_volts_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_ldo_volts_DEFAULT 0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: skip_mrs [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_skip_mrs_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_skip_mrs_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_skip_mrs_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: rst_n [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_rst_n_MASK   0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_rst_n_SHIFT  5
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_rst_n_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: cke [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_cke_MASK     0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_cke_SHIFT    4
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_cke_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STANDBY_CONTROL :: standby [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_standby_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_standby_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL_standby_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_CONTROL - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_CONTROL :: reserved0 [31:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_reserved0_MASK 0xf0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_reserved0_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_CONTROL :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_mhz_MASK       0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_mhz_SHIFT      16
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_mhz_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_CONTROL :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_ad_width_MASK  0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_ad_width_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_ad_width_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_CONTROL :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_dual_rank_MASK 0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_dual_rank_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_dual_rank_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_CONTROL :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_bus16_MASK     0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_bus16_SHIFT    12
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_bus16_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_CONTROL :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_bus8_MASK      0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_bus8_SHIFT     11
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_bus8_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_CONTROL :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_chip_width_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_chip_width_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_CONTROL :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_vddq_MASK      0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_vddq_SHIFT     8
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_vddq_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_CONTROL :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_chip_size_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_chip_size_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_chip_size_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_CONTROL :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_jedec_type_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_jedec_type_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_CONTROL :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_straps_valid_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL_straps_valid_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_CONTROL2 - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_CONTROL2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_CONTROL2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL2_ddr3_MASK     0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL2_ddr3_SHIFT    20
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL2_ddr3_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_CONTROL2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL2_al_MASK       0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL2_al_SHIFT      17
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL2_al_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_CONTROL2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL2_wr_MASK       0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL2_wr_SHIFT      12
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL2_wr_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_CONTROL2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL2_cwl_MASK      0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL2_cwl_SHIFT     7
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL2_cwl_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_CONTROL2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL2_cl_MASK       0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL2_cl_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_CONTROL2_cl_DEFAULT    0x00000000
+
+/***************************************************************************
+ *STRAP_STATUS - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_reserved0_MASK  0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_STATUS :: from_reg [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_from_reg_MASK   0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_from_reg_SHIFT  29
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_STATUS :: from_memc [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_from_memc_MASK  0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_from_memc_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_STATUS :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_mhz_MASK        0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_mhz_SHIFT       16
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_STATUS :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_ad_width_MASK   0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_ad_width_SHIFT  14
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_STATUS :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_dual_rank_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_dual_rank_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_STATUS :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_bus16_MASK      0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_bus16_SHIFT     12
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_STATUS :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_bus8_MASK       0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_bus8_SHIFT      11
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_STATUS :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_chip_width_SHIFT 10
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_STATUS :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_vddq_MASK       0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_vddq_SHIFT      8
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_STATUS :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_chip_size_MASK  0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_chip_size_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_STATUS :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_jedec_type_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_STATUS :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS_straps_valid_SHIFT 0
+
+/***************************************************************************
+ *STRAP_STATUS2 - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_STATUS2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_STATUS2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS2_ddr3_MASK      0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS2_ddr3_SHIFT     20
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_STATUS2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS2_al_MASK        0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS2_al_SHIFT       17
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_STATUS2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS2_wr_MASK        0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS2_wr_SHIFT       12
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_STATUS2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS2_cwl_MASK       0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS2_cwl_SHIFT      7
+
+/* DDR40_PHY_CONTROL_REGS_1 :: STRAP_STATUS2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS2_cl_MASK        0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_STRAP_STATUS2_cl_SHIFT       0
+
+/***************************************************************************
+ *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_1 :: DEBUG_FREEZE_ENABLE :: wl1_bl1 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_wl1_bl1_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_wl1_bl1_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_wl1_bl1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: DEBUG_FREEZE_ENABLE :: wl1_bl0 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_wl1_bl0_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_wl1_bl0_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_wl1_bl0_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: DEBUG_FREEZE_ENABLE :: wl0_bl1 [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_wl0_bl1_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_wl0_bl1_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_wl0_bl1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: DEBUG_FREEZE_ENABLE :: wl0_bl0 [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_wl0_bl0_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_wl0_bl0_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DEBUG_FREEZE_ENABLE_wl0_bl0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DATAPATH_LOOPBACK - Datapth Loopback control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_1 :: DATAPATH_LOOPBACK :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DATAPATH_LOOPBACK_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DATAPATH_LOOPBACK_reserved0_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_1 :: DATAPATH_LOOPBACK :: xor_dm_rd_en [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DATAPATH_LOOPBACK_xor_dm_rd_en_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DATAPATH_LOOPBACK_xor_dm_rd_en_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DATAPATH_LOOPBACK_xor_dm_rd_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: DATAPATH_LOOPBACK :: use_addr_ctl [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DATAPATH_LOOPBACK_use_addr_ctl_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DATAPATH_LOOPBACK_use_addr_ctl_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DATAPATH_LOOPBACK_use_addr_ctl_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_1 :: DATAPATH_LOOPBACK :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DATAPATH_LOOPBACK_enable_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DATAPATH_LOOPBACK_enable_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_1_DATAPATH_LOOPBACK_enable_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR40_PHY_CONTROL_REGS_1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_ddr40_phy_word_lane_0_0.h b/include/linux/brcmstb/7435b0/bchp_ddr40_phy_word_lane_0_0.h
new file mode 100644
index 0000000..eb80b9d
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_ddr40_phy_word_lane_0_0.h
@@ -0,0 +1,3334 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:28 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_ddr40_phy_word_lane_0_0.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 2:04p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_0_0 - DDR40 DDR40 word lane #0 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN 0x003b6200 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W 0x003b6204 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P 0x003b6208 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N 0x003b620c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W 0x003b6210 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W 0x003b6214 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W 0x003b6218 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W 0x003b621c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W 0x003b6220 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W 0x003b6224 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W 0x003b6228 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W 0x003b622c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W 0x003b6230 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003b6234 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003b6238 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003b623c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003b6240 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003b6244 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003b6248 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003b624c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003b6250 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003b6254 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003b6258 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003b625c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003b6260 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003b6264 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003b6268 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003b626c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003b6270 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003b6274 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W 0x003b62a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P 0x003b62a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N 0x003b62ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W 0x003b62b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W 0x003b62b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W 0x003b62b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W 0x003b62bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W 0x003b62c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W 0x003b62c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W 0x003b62c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W 0x003b62cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W 0x003b62d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003b62d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003b62d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003b62dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003b62e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003b62e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003b62e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003b62ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003b62f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003b62f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003b62f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003b62fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003b6300 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003b6304 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003b6308 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003b630c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003b6310 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003b6314 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x003b6328 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x003b632c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003b6330 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003b6334 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W 0x003b6338 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003b633c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x003b6348 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x003b634c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003b6350 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003b6354 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W 0x003b6358 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003b635c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY 0x003b6360 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL 0x003b6364 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0 0x003b6370 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1 0x003b6374 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2 0x003b6378 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3 0x003b637c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0 0x003b6380 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1 0x003b6384 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2 0x003b6388 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3 0x003b638c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS 0x003b6390 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR 0x003b6394 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL 0x003b63a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL 0x003b63a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE 0x003b63a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE 0x003b63ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ 0x003b63b0 /* PHYBIST mode VDL step select adjustment register */
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_RD_EN - Read Enable Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_DATA_DLY - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_MASK  0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: rd_data_dly [02:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_MASK 0x00000007
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_DEFAULT 0x00000001
+
+/***************************************************************************
+ *READ_CONTROL - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_MASK   0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_SHIFT  3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_enable [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_te_adj [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_le_adj [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status1 [07:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_MASK 0x000000f0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status0 [03:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_MASK 0x0000000f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: clear [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_MASK    0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_SHIFT   31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_SHIFT 24
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_MASK 0x00c00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_SHIFT 22
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_MASK 0x00300000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_SHIFT 20
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00080000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 19
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00040000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_SHIFT 18
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_MASK  0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_MASK  0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00008000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 15
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00004000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 14
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00002000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 13
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00001000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 12
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_MASK 0x00000008
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_MASK  0xfffff000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_SHIFT 12
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: no_dqs_rd [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_MASK  0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_MASK    0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_SHIFT   6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_MASK      0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_SHIFT     2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_DEFAULT   0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_MASK   0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_SHIFT  1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_MASK      0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_SHIFT     0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_DEFAULT   0x00000000
+
+/***************************************************************************
+ *CLOCK_PAD_DISABLE - Clock pad disable register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffc
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_SHIFT 2
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: long [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_MASK    0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_SHIFT   1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: mode [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHYBIST_VDL_ADJ - PHYBIST mode VDL step select adjustment register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_SHIFT 29
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq1_vdl_adj [28:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_MASK 0x1f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved1 [23:21] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_MASK 0x00e00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_SHIFT 21
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq0_vdl_adj [20:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_MASK 0x001f0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved2 [15:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_MASK 0x0000e000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_SHIFT 13
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs1_vdl_adj [12:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_MASK 0x00001f00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved3 [07:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_MASK 0x000000e0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_SHIFT 5
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs0_vdl_adj [04:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_MASK 0x0000001f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_ddr40_phy_word_lane_0_1.h b/include/linux/brcmstb/7435b0/bchp_ddr40_phy_word_lane_0_1.h
new file mode 100644
index 0000000..63b66bf
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_ddr40_phy_word_lane_0_1.h
@@ -0,0 +1,3331 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Jul 20 15:43:16 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_0_1_H__
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_0_1 - DDR40 DDR40 word lane #0 control registers 1
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN 0x003c6200 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W 0x003c6204 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P 0x003c6208 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N 0x003c620c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W 0x003c6210 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W 0x003c6214 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W 0x003c6218 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W 0x003c621c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W 0x003c6220 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W 0x003c6224 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W 0x003c6228 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W 0x003c622c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W 0x003c6230 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003c6234 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003c6238 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003c623c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003c6240 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003c6244 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003c6248 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003c624c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003c6250 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003c6254 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003c6258 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003c625c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003c6260 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003c6264 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003c6268 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003c626c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003c6270 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003c6274 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W 0x003c62a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P 0x003c62a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N 0x003c62ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W 0x003c62b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W 0x003c62b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W 0x003c62b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W 0x003c62bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W 0x003c62c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W 0x003c62c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W 0x003c62c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W 0x003c62cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W 0x003c62d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003c62d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003c62d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003c62dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003c62e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003c62e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003c62e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003c62ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003c62f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003c62f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003c62f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003c62fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003c6300 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003c6304 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003c6308 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003c630c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003c6310 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003c6314 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_P 0x003c6328 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_N 0x003c632c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003c6330 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003c6334 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_W 0x003c6338 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003c633c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_P 0x003c6348 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_N 0x003c634c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003c6350 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003c6354 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_W 0x003c6358 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003c635c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_DATA_DLY 0x003c6360 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_CONTROL 0x003c6364 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_0 0x003c6370 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_1 0x003c6374 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_2 0x003c6378 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_3 0x003c637c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_0 0x003c6380 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_1 0x003c6384 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_2 0x003c6388 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_3 0x003c638c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_STATUS 0x003c6390 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_CLEAR 0x003c6394 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL 0x003c63a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL 0x003c63a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_CLOCK_PAD_DISABLE 0x003c63a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_WR_PREAMBLE_MODE 0x003c63ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ 0x003c63b0 /* PHYBIST mode VDL step select adjustment register */
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_RD_EN - Read Enable Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_DM_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_DM_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_DATA_DLY - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_DATA_DLY :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_DATA_DLY_reserved0_MASK  0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_DATA_DLY_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_DATA_DLY :: rd_data_dly [02:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_DATA_DLY_rd_data_dly_MASK 0x00000007
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_DATA_DLY_rd_data_dly_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_DATA_DLY_rd_data_dly_DEFAULT 0x00000001
+
+/***************************************************************************
+ *READ_CONTROL - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_CONTROL :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_CONTROL_reserved0_MASK   0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_CONTROL_reserved0_SHIFT  3
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_CONTROL :: dq_odt_enable [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_CONTROL_dq_odt_enable_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_CONTROL_dq_odt_enable_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_CONTROL_dq_odt_enable_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_CONTROL :: dq_odt_te_adj [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_CONTROL_dq_odt_te_adj_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_CONTROL_dq_odt_te_adj_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_CONTROL_dq_odt_te_adj_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_CONTROL :: dq_odt_le_adj [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_CONTROL_dq_odt_le_adj_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_CONTROL_dq_odt_le_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_CONTROL_dq_odt_le_adj_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL0_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_DATA_BL1_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_STATUS :: status1 [07:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_STATUS_status1_MASK 0x000000f0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_STATUS_status1_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_STATUS_status1_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_STATUS :: status0 [03:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_STATUS_status0_MASK 0x0000000f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_STATUS_status0_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_STATUS_status0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR40_PHY_WORD_LANE_0_1 :: READ_FIFO_CLEAR :: clear [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_CLEAR_clear_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_CLEAR_clear_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_READ_FIFO_CLEAR_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_idle_MASK    0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_idle_SHIFT   31
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_reserved0_MASK 0x7f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_reserved0_SHIFT 24
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_MASK 0x00c00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_SHIFT 22
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_auto_dq_iddq_mode_MASK 0x00300000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_auto_dq_iddq_mode_SHIFT 20
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_auto_dq_iddq_mode_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00080000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 19
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dq_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00040000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dq_iddq_SHIFT 18
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dq_iddq_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dq_reb_MASK  0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dq_reb_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dq_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dq_oeb_MASK  0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dq_oeb_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dq_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00008000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 15
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_read_enb_rxenb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00004000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 14
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_read_enb_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00002000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 13
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_read_enb_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00001000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 12
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_read_enb_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dqs_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dqs_iddq_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dqs_reb_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dqs_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_dqs_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk1_rxenb_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk1_rxenb_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk1_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk1_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk1_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk1_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk1_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk1_reb_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk1_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk1_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk1_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk1_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk0_rxenb_MASK 0x00000008
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk0_rxenb_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk0_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk0_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk0_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk0_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk0_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk0_reb_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk0_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_1 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk0_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk0_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL_clk0_oeb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: DRIVE_PAD_CTL :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_reserved0_MASK  0xfffff000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_reserved0_SHIFT 12
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DRIVE_PAD_CTL :: no_dqs_rd [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_no_dqs_rd_MASK  0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_no_dqs_rd_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_no_dqs_rd_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_dqs_always_on_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_dqs_always_on_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_dqs_always_on_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_dqs_tx_dis_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_dqs_tx_dis_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_dqs_tx_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_half_strength_ck_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_half_strength_ck_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_half_strength_ck_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DRIVE_PAD_CTL :: half_strength [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_half_strength_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_half_strength_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_half_strength_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_rdqs_en_MASK    0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_rdqs_en_SHIFT   6
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_rdqs_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_rt60b_MASK      0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_rt60b_SHIFT     2
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_rt60b_DEFAULT   0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_rt120b_g_MASK   0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_rt120b_g_SHIFT  1
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_rt120b_g_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_1 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_g_ddr_MASK      0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_g_ddr_SHIFT     0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_DRIVE_PAD_CTL_g_ddr_DEFAULT   0x00000000
+
+/***************************************************************************
+ *CLOCK_PAD_DISABLE - Clock pad disable register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_CLOCK_PAD_DISABLE_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_1 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_CLOCK_PAD_DISABLE_dm_pad_dis_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_CLOCK_PAD_DISABLE_dm_pad_dis_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_CLOCK_PAD_DISABLE_dm_pad_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_CLOCK_PAD_DISABLE_clk1_pad_dis_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_CLOCK_PAD_DISABLE_clk1_pad_dis_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_CLOCK_PAD_DISABLE_clk1_pad_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_CLOCK_PAD_DISABLE_clk0_pad_dis_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_CLOCK_PAD_DISABLE_clk0_pad_dis_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_CLOCK_PAD_DISABLE_clk0_pad_dis_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffc
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_WR_PREAMBLE_MODE_reserved0_SHIFT 2
+
+/* DDR40_PHY_WORD_LANE_0_1 :: WR_PREAMBLE_MODE :: long [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_WR_PREAMBLE_MODE_long_MASK    0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_WR_PREAMBLE_MODE_long_SHIFT   1
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_WR_PREAMBLE_MODE_long_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: WR_PREAMBLE_MODE :: mode [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_WR_PREAMBLE_MODE_mode_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_WR_PREAMBLE_MODE_mode_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_WR_PREAMBLE_MODE_mode_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHYBIST_VDL_ADJ - PHYBIST mode VDL step select adjustment register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_1 :: PHYBIST_VDL_ADJ :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ_reserved0_SHIFT 29
+
+/* DDR40_PHY_WORD_LANE_0_1 :: PHYBIST_VDL_ADJ :: dq1_vdl_adj [28:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ_dq1_vdl_adj_MASK 0x1f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ_dq1_vdl_adj_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ_dq1_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: PHYBIST_VDL_ADJ :: reserved1 [23:21] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ_reserved1_MASK 0x00e00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ_reserved1_SHIFT 21
+
+/* DDR40_PHY_WORD_LANE_0_1 :: PHYBIST_VDL_ADJ :: dq0_vdl_adj [20:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ_dq0_vdl_adj_MASK 0x001f0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ_dq0_vdl_adj_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ_dq0_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: PHYBIST_VDL_ADJ :: reserved2 [15:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ_reserved2_MASK 0x0000e000
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ_reserved2_SHIFT 13
+
+/* DDR40_PHY_WORD_LANE_0_1 :: PHYBIST_VDL_ADJ :: dqs1_vdl_adj [12:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ_dqs1_vdl_adj_MASK 0x00001f00
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ_dqs1_vdl_adj_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ_dqs1_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_1 :: PHYBIST_VDL_ADJ :: reserved3 [07:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ_reserved3_MASK 0x000000e0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ_reserved3_SHIFT 5
+
+/* DDR40_PHY_WORD_LANE_0_1 :: PHYBIST_VDL_ADJ :: dqs0_vdl_adj [04:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ_dqs0_vdl_adj_MASK 0x0000001f
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ_dqs0_vdl_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_1_PHYBIST_VDL_ADJ_dqs0_vdl_adj_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_0_1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_ddr40_phy_word_lane_1_0.h b/include/linux/brcmstb/7435b0/bchp_ddr40_phy_word_lane_1_0.h
new file mode 100644
index 0000000..0f8d280
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_ddr40_phy_word_lane_1_0.h
@@ -0,0 +1,3331 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Jul 20 15:43:15 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_1_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_1_0 - DDR40 DDR40 word lane #1 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN 0x003b6400 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W 0x003b6404 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P 0x003b6408 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N 0x003b640c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W 0x003b6410 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W 0x003b6414 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W 0x003b6418 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W 0x003b641c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W 0x003b6420 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W 0x003b6424 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W 0x003b6428 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W 0x003b642c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W 0x003b6430 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003b6434 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003b6438 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003b643c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003b6440 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003b6444 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003b6448 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003b644c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003b6450 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003b6454 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003b6458 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003b645c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003b6460 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003b6464 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003b6468 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003b646c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003b6470 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003b6474 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W 0x003b64a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P 0x003b64a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N 0x003b64ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W 0x003b64b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W 0x003b64b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W 0x003b64b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W 0x003b64bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W 0x003b64c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W 0x003b64c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W 0x003b64c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W 0x003b64cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W 0x003b64d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003b64d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003b64d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003b64dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003b64e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003b64e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003b64e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003b64ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003b64f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003b64f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003b64f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003b64fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003b6500 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003b6504 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003b6508 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003b650c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003b6510 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003b6514 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x003b6528 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x003b652c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003b6530 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003b6534 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W 0x003b6538 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003b653c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x003b6548 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x003b654c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003b6550 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003b6554 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W 0x003b6558 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003b655c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_DATA_DLY 0x003b6560 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_CONTROL 0x003b6564 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_0 0x003b6570 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_1 0x003b6574 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_2 0x003b6578 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_3 0x003b657c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_0 0x003b6580 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_1 0x003b6584 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_2 0x003b6588 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_3 0x003b658c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_STATUS 0x003b6590 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_CLEAR 0x003b6594 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL 0x003b65a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL 0x003b65a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_CLOCK_PAD_DISABLE 0x003b65a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_WR_PREAMBLE_MODE 0x003b65ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ 0x003b65b0 /* PHYBIST mode VDL step select adjustment register */
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_RD_EN - Read Enable Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_DATA_DLY - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_DATA_DLY :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_DATA_DLY_reserved0_MASK  0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_DATA_DLY_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_DATA_DLY :: rd_data_dly [02:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_DATA_DLY_rd_data_dly_MASK 0x00000007
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_DATA_DLY_rd_data_dly_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_DATA_DLY_rd_data_dly_DEFAULT 0x00000001
+
+/***************************************************************************
+ *READ_CONTROL - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_CONTROL :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_CONTROL_reserved0_MASK   0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_CONTROL_reserved0_SHIFT  3
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_CONTROL :: dq_odt_enable [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_CONTROL_dq_odt_enable_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_CONTROL_dq_odt_enable_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_CONTROL_dq_odt_enable_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_CONTROL :: dq_odt_te_adj [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_CONTROL_dq_odt_te_adj_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_CONTROL_dq_odt_te_adj_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_CONTROL_dq_odt_te_adj_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_CONTROL :: dq_odt_le_adj [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_CONTROL_dq_odt_le_adj_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_CONTROL_dq_odt_le_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_CONTROL_dq_odt_le_adj_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_STATUS :: status1 [07:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_STATUS_status1_MASK 0x000000f0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_STATUS_status1_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_STATUS_status1_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_STATUS :: status0 [03:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_STATUS_status0_MASK 0x0000000f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_STATUS_status0_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_STATUS_status0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR40_PHY_WORD_LANE_1_0 :: READ_FIFO_CLEAR :: clear [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_CLEAR_clear_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_CLEAR_clear_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_CLEAR_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_idle_MASK    0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_idle_SHIFT   31
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7f000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_reserved0_SHIFT 24
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_MASK 0x00c00000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_SHIFT 22
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_MASK 0x00300000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_SHIFT 20
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00080000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 19
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dq_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00040000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dq_iddq_SHIFT 18
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dq_iddq_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dq_reb_MASK  0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dq_reb_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dq_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dq_oeb_MASK  0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dq_oeb_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dq_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00008000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 15
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_read_enb_rxenb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00004000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 14
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_read_enb_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00002000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 13
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_read_enb_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00001000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 12
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_read_enb_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dqs_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dqs_iddq_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dqs_reb_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dqs_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_dqs_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk1_rxenb_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk1_rxenb_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk1_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk1_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk1_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk1_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk1_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk1_reb_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk1_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk1_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk1_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk1_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk0_rxenb_MASK 0x00000008
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk0_rxenb_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk0_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk0_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk0_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk0_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk0_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk0_reb_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk0_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_0 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk0_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk0_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL_clk0_oeb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: DRIVE_PAD_CTL :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_reserved0_MASK  0xfffff000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_reserved0_SHIFT 12
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DRIVE_PAD_CTL :: no_dqs_rd [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_no_dqs_rd_MASK  0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_no_dqs_rd_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_no_dqs_rd_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_dqs_always_on_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_dqs_always_on_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_dqs_always_on_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_dqs_tx_dis_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_dqs_tx_dis_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_dqs_tx_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_half_strength_ck_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_half_strength_ck_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_half_strength_ck_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DRIVE_PAD_CTL :: half_strength [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_half_strength_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_rdqs_en_MASK    0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_rdqs_en_SHIFT   6
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_rdqs_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_rt60b_MASK      0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_rt60b_SHIFT     2
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_rt60b_DEFAULT   0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_rt120b_g_MASK   0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_rt120b_g_SHIFT  1
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_g_ddr_MASK      0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_g_ddr_SHIFT     0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL_g_ddr_DEFAULT   0x00000000
+
+/***************************************************************************
+ *CLOCK_PAD_DISABLE - Clock pad disable register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_CLOCK_PAD_DISABLE_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_1_0 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_CLOCK_PAD_DISABLE_dm_pad_dis_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_CLOCK_PAD_DISABLE_dm_pad_dis_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_CLOCK_PAD_DISABLE_dm_pad_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_CLOCK_PAD_DISABLE_clk1_pad_dis_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_CLOCK_PAD_DISABLE_clk1_pad_dis_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_CLOCK_PAD_DISABLE_clk1_pad_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_CLOCK_PAD_DISABLE_clk0_pad_dis_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_CLOCK_PAD_DISABLE_clk0_pad_dis_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_CLOCK_PAD_DISABLE_clk0_pad_dis_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffc
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_WR_PREAMBLE_MODE_reserved0_SHIFT 2
+
+/* DDR40_PHY_WORD_LANE_1_0 :: WR_PREAMBLE_MODE :: long [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_WR_PREAMBLE_MODE_long_MASK    0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_WR_PREAMBLE_MODE_long_SHIFT   1
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_WR_PREAMBLE_MODE_long_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: WR_PREAMBLE_MODE :: mode [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_WR_PREAMBLE_MODE_mode_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_WR_PREAMBLE_MODE_mode_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_WR_PREAMBLE_MODE_mode_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHYBIST_VDL_ADJ - PHYBIST mode VDL step select adjustment register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_0 :: PHYBIST_VDL_ADJ :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ_reserved0_SHIFT 29
+
+/* DDR40_PHY_WORD_LANE_1_0 :: PHYBIST_VDL_ADJ :: dq1_vdl_adj [28:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_MASK 0x1f000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: PHYBIST_VDL_ADJ :: reserved1 [23:21] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ_reserved1_MASK 0x00e00000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ_reserved1_SHIFT 21
+
+/* DDR40_PHY_WORD_LANE_1_0 :: PHYBIST_VDL_ADJ :: dq0_vdl_adj [20:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_MASK 0x001f0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: PHYBIST_VDL_ADJ :: reserved2 [15:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ_reserved2_MASK 0x0000e000
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ_reserved2_SHIFT 13
+
+/* DDR40_PHY_WORD_LANE_1_0 :: PHYBIST_VDL_ADJ :: dqs1_vdl_adj [12:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_MASK 0x00001f00
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_0 :: PHYBIST_VDL_ADJ :: reserved3 [07:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ_reserved3_MASK 0x000000e0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ_reserved3_SHIFT 5
+
+/* DDR40_PHY_WORD_LANE_1_0 :: PHYBIST_VDL_ADJ :: dqs0_vdl_adj [04:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_MASK 0x0000001f
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_1_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_ddr40_phy_word_lane_1_1.h b/include/linux/brcmstb/7435b0/bchp_ddr40_phy_word_lane_1_1.h
new file mode 100644
index 0000000..d5bcaff
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_ddr40_phy_word_lane_1_1.h
@@ -0,0 +1,3331 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Jul 20 15:43:15 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_1_1_H__
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_1_1 - DDR40 DDR40 word lane #1 control registers 1
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN 0x003c6400 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W 0x003c6404 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P 0x003c6408 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N 0x003c640c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W 0x003c6410 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W 0x003c6414 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W 0x003c6418 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W 0x003c641c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W 0x003c6420 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W 0x003c6424 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W 0x003c6428 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W 0x003c642c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W 0x003c6430 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003c6434 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003c6438 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003c643c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003c6440 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003c6444 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003c6448 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003c644c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003c6450 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003c6454 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003c6458 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003c645c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003c6460 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003c6464 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003c6468 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003c646c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003c6470 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003c6474 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W 0x003c64a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P 0x003c64a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N 0x003c64ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W 0x003c64b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W 0x003c64b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W 0x003c64b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W 0x003c64bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W 0x003c64c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W 0x003c64c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W 0x003c64c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W 0x003c64cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W 0x003c64d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003c64d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003c64d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003c64dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003c64e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003c64e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003c64e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003c64ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003c64f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003c64f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003c64f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003c64fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003c6500 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003c6504 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003c6508 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003c650c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003c6510 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003c6514 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_P 0x003c6528 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_N 0x003c652c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003c6530 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003c6534 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_W 0x003c6538 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003c653c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_P 0x003c6548 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_N 0x003c654c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003c6550 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003c6554 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_W 0x003c6558 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003c655c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_DATA_DLY 0x003c6560 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_CONTROL 0x003c6564 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_0 0x003c6570 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_1 0x003c6574 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_2 0x003c6578 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_3 0x003c657c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_0 0x003c6580 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_1 0x003c6584 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_2 0x003c6588 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_3 0x003c658c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_STATUS 0x003c6590 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_CLEAR 0x003c6594 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL 0x003c65a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL 0x003c65a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_CLOCK_PAD_DISABLE 0x003c65a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_WR_PREAMBLE_MODE 0x003c65ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ 0x003c65b0 /* PHYBIST mode VDL step select adjustment register */
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_RD_EN - Read Enable Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_DATA_DLY - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_DATA_DLY :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_DATA_DLY_reserved0_MASK  0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_DATA_DLY_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_DATA_DLY :: rd_data_dly [02:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_DATA_DLY_rd_data_dly_MASK 0x00000007
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_DATA_DLY_rd_data_dly_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_DATA_DLY_rd_data_dly_DEFAULT 0x00000001
+
+/***************************************************************************
+ *READ_CONTROL - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_CONTROL :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_CONTROL_reserved0_MASK   0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_CONTROL_reserved0_SHIFT  3
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_CONTROL :: dq_odt_enable [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_CONTROL_dq_odt_enable_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_CONTROL_dq_odt_enable_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_CONTROL_dq_odt_enable_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_CONTROL :: dq_odt_te_adj [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_CONTROL_dq_odt_te_adj_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_CONTROL_dq_odt_te_adj_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_CONTROL_dq_odt_te_adj_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_CONTROL :: dq_odt_le_adj [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_CONTROL_dq_odt_le_adj_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_CONTROL_dq_odt_le_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_CONTROL_dq_odt_le_adj_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_STATUS :: status1 [07:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_STATUS_status1_MASK 0x000000f0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_STATUS_status1_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_STATUS_status1_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_STATUS :: status0 [03:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_STATUS_status0_MASK 0x0000000f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_STATUS_status0_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_STATUS_status0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR40_PHY_WORD_LANE_1_1 :: READ_FIFO_CLEAR :: clear [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_CLEAR_clear_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_CLEAR_clear_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_CLEAR_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_idle_MASK    0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_idle_SHIFT   31
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_reserved0_MASK 0x7f000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_reserved0_SHIFT 24
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_MASK 0x00c00000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_SHIFT 22
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_auto_dq_iddq_mode_MASK 0x00300000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_auto_dq_iddq_mode_SHIFT 20
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_auto_dq_iddq_mode_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00080000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 19
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dq_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00040000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dq_iddq_SHIFT 18
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dq_iddq_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dq_reb_MASK  0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dq_reb_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dq_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dq_oeb_MASK  0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dq_oeb_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dq_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00008000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 15
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_read_enb_rxenb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00004000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 14
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_read_enb_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00002000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 13
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_read_enb_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00001000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 12
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_read_enb_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dqs_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dqs_iddq_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dqs_reb_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dqs_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_dqs_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk1_rxenb_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk1_rxenb_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk1_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk1_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk1_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk1_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk1_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk1_reb_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk1_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk1_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk1_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk1_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk0_rxenb_MASK 0x00000008
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk0_rxenb_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk0_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk0_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk0_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk0_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk0_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk0_reb_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk0_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_1 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk0_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk0_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL_clk0_oeb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: DRIVE_PAD_CTL :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_reserved0_MASK  0xfffff000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_reserved0_SHIFT 12
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DRIVE_PAD_CTL :: no_dqs_rd [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_no_dqs_rd_MASK  0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_no_dqs_rd_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_no_dqs_rd_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_dqs_always_on_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_dqs_always_on_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_dqs_always_on_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_dqs_tx_dis_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_dqs_tx_dis_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_dqs_tx_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_half_strength_ck_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_half_strength_ck_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_half_strength_ck_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DRIVE_PAD_CTL :: half_strength [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_half_strength_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_half_strength_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_half_strength_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_rdqs_en_MASK    0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_rdqs_en_SHIFT   6
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_rdqs_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_rt60b_MASK      0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_rt60b_SHIFT     2
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_rt60b_DEFAULT   0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_rt120b_g_MASK   0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_rt120b_g_SHIFT  1
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_rt120b_g_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_1_1 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_g_ddr_MASK      0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_g_ddr_SHIFT     0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL_g_ddr_DEFAULT   0x00000000
+
+/***************************************************************************
+ *CLOCK_PAD_DISABLE - Clock pad disable register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_CLOCK_PAD_DISABLE_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_1_1 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_CLOCK_PAD_DISABLE_dm_pad_dis_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_CLOCK_PAD_DISABLE_dm_pad_dis_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_CLOCK_PAD_DISABLE_dm_pad_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_CLOCK_PAD_DISABLE_clk1_pad_dis_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_CLOCK_PAD_DISABLE_clk1_pad_dis_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_CLOCK_PAD_DISABLE_clk1_pad_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_CLOCK_PAD_DISABLE_clk0_pad_dis_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_CLOCK_PAD_DISABLE_clk0_pad_dis_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_CLOCK_PAD_DISABLE_clk0_pad_dis_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffc
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_WR_PREAMBLE_MODE_reserved0_SHIFT 2
+
+/* DDR40_PHY_WORD_LANE_1_1 :: WR_PREAMBLE_MODE :: long [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_WR_PREAMBLE_MODE_long_MASK    0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_WR_PREAMBLE_MODE_long_SHIFT   1
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_WR_PREAMBLE_MODE_long_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: WR_PREAMBLE_MODE :: mode [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_WR_PREAMBLE_MODE_mode_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_WR_PREAMBLE_MODE_mode_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_WR_PREAMBLE_MODE_mode_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHYBIST_VDL_ADJ - PHYBIST mode VDL step select adjustment register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_1_1 :: PHYBIST_VDL_ADJ :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ_reserved0_SHIFT 29
+
+/* DDR40_PHY_WORD_LANE_1_1 :: PHYBIST_VDL_ADJ :: dq1_vdl_adj [28:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ_dq1_vdl_adj_MASK 0x1f000000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ_dq1_vdl_adj_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ_dq1_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: PHYBIST_VDL_ADJ :: reserved1 [23:21] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ_reserved1_MASK 0x00e00000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ_reserved1_SHIFT 21
+
+/* DDR40_PHY_WORD_LANE_1_1 :: PHYBIST_VDL_ADJ :: dq0_vdl_adj [20:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ_dq0_vdl_adj_MASK 0x001f0000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ_dq0_vdl_adj_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ_dq0_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: PHYBIST_VDL_ADJ :: reserved2 [15:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ_reserved2_MASK 0x0000e000
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ_reserved2_SHIFT 13
+
+/* DDR40_PHY_WORD_LANE_1_1 :: PHYBIST_VDL_ADJ :: dqs1_vdl_adj [12:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ_dqs1_vdl_adj_MASK 0x00001f00
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ_dqs1_vdl_adj_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ_dqs1_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_1_1 :: PHYBIST_VDL_ADJ :: reserved3 [07:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ_reserved3_MASK 0x000000e0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ_reserved3_SHIFT 5
+
+/* DDR40_PHY_WORD_LANE_1_1 :: PHYBIST_VDL_ADJ :: dqs0_vdl_adj [04:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ_dqs0_vdl_adj_MASK 0x0000001f
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ_dqs0_vdl_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ_dqs0_vdl_adj_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_1_1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_ebi.h b/include/linux/brcmstb/7435b0/bchp_ebi.h
new file mode 100644
index 0000000..6effe54
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_ebi.h
@@ -0,0 +1,1711 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:12 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_ebi.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 2:15p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EBI_H__
+#define BCHP_EBI_H__
+
+/***************************************************************************
+ *EBI - EBI Registers
+ ***************************************************************************/
+#define BCHP_EBI_CS_BASE_0                       0x0041a800 /* EBI CS Base 0 Register */
+#define BCHP_EBI_CS_CONFIG_0                     0x0041a804 /* EBI CS Config 0 Register */
+#define BCHP_EBI_CS_BASE_1                       0x0041a808 /* EBI CS Base 1 Register */
+#define BCHP_EBI_CS_CONFIG_1                     0x0041a80c /* EBI CS Config 1 Register */
+#define BCHP_EBI_CS_BASE_2                       0x0041a810 /* EBI CS Base 2 Register */
+#define BCHP_EBI_CS_CONFIG_2                     0x0041a814 /* EBI CS Config 2 Register */
+#define BCHP_EBI_CS_BASE_3                       0x0041a818 /* EBI CS Base 3 Register */
+#define BCHP_EBI_CS_CONFIG_3                     0x0041a81c /* EBI CS Config 3 Register */
+#define BCHP_EBI_CS_BASE_4                       0x0041a820 /* EBI CS Base 4 Register */
+#define BCHP_EBI_CS_CONFIG_4                     0x0041a824 /* EBI CS Config 4 Register */
+#define BCHP_EBI_CS_BASE_5                       0x0041a828 /* EBI CS Base 5 Register */
+#define BCHP_EBI_CS_CONFIG_5                     0x0041a82c /* EBI CS Config 5 Register */
+#define BCHP_EBI_BURST_CFG_0                     0x0041a840 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_1                     0x0041a844 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_2                     0x0041a848 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_3                     0x0041a84c /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_4                     0x0041a850 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_5                     0x0041a854 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_ECR                             0x0041a900 /* EBI Configuration Register */
+#define BCHP_EBI_CS_TRISTATE_CFG                 0x0041a918 /* EBI CS Tristate Configuration Register */
+#define BCHP_EBI_TA_CFG                          0x0041a91c /* EBI TA Configuration Register */
+#define BCHP_EBI_CS_SPI_SELECT                   0x0041a920 /* SPI CS Select */
+#define BCHP_EBI_ARRAY_ADDRESS                   0x0041a9f0 /* EBI Data Array Address */
+
+/***************************************************************************
+ *CS_BASE_0 - EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_0 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_0_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT                         13
+
+/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_0_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_0 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_0_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_0_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_0 - EBI CS Config 0 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_0_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT                       0x00000001
+
+/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_0_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_0_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_0_le_SHIFT                              10
+
+/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_0_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_0_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT                       4
+
+/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_0_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT                        0x00000001
+
+/***************************************************************************
+ *CS_BASE_1 - EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_1 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_1_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_1_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_1 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_1_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_1_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_1_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_1 - EBI CS Config 1 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_1_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_1_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_1_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_1_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_1_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_1_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_1_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_2 - EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_2 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_2_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_2_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_2 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_2_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_2_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_2_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_2 - EBI CS Config 2 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_2_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_2_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_2_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_2_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_2_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_2_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_2_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_3 - EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_3 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_3_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_3_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_3 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_3_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_3_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_3_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_3 - EBI CS Config 3 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_3_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_3_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_3_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_3_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_3_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_3_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_3_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_4 - EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_4 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_4_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_4_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_4 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_4_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_4_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_4_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_4 - EBI CS Config 4 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_4_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_4_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_4_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_4_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_4_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_4_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_4_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_5 - EBI CS Base 5 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_5 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_5_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_5_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_5_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_5 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_5_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_5_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_5 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_5_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_5_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_5_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_5_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_5_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_5_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_5_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_5 - EBI CS Config 5 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_5 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_5_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_5_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_5_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_5_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_5_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_5_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_5 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_5_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_5_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_5_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_5 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_5_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_5_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_5_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_5_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_5_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_5_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_5_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_5_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_5_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_5 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_5_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_5_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_5_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_5 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_5_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_5_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_5_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_5 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_5_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_5_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_5_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_5 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_5_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_5_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_5_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_5 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_5_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_5_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_5_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_5 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_5_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_5_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_5_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_5 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_5_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_5_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_5_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_5 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_5_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_5_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_5_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_5_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_5_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_5_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_5_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_5_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_5_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_0_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_0_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_0 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_0_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_0_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_0_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_0_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_0_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_1_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_1_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_1 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_1_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_1_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_1_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_1_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_1_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_2_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_2_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_2 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_2_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_2_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_2_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_2_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_2_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_3_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_3_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_3 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_3_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_3_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_3_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_3_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_3_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_4_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_4_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_4 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_4_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_4_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_4_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_4_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_4_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_5 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_5 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_5 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_5_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_5_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_5_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_5 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_5 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_5 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_5 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_5_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_5_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_5 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_5 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_5_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_5_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_5_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_5 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_5 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_5 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_5_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_5_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_5 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_5_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_5_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_5_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_5 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_5_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_5_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_5 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_5_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_5_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_5_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_5 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_5_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_5_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_5_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *ECR - EBI Configuration Register
+ ***************************************************************************/
+/* EBI :: ECR :: reserved0 [31:28] */
+#define BCHP_EBI_ECR_reserved0_MASK                                0xf0000000
+#define BCHP_EBI_ECR_reserved0_SHIFT                               28
+
+/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK                            0x08000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT                           27
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT                         0x00000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only  1
+
+/* EBI :: ECR :: reserved1 [26:26] */
+#define BCHP_EBI_ECR_reserved1_MASK                                0x04000000
+#define BCHP_EBI_ECR_reserved1_SHIFT                               26
+
+/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK                          0x02000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT                         25
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT                       0x00000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10         0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00         1
+
+/* EBI :: ECR :: reserved2 [24:11] */
+#define BCHP_EBI_ECR_reserved2_MASK                                0x01fff800
+#define BCHP_EBI_ECR_reserved2_SHIFT                               11
+
+/* EBI :: ECR :: timeout_count [10:00] */
+#define BCHP_EBI_ECR_timeout_count_MASK                            0x000007ff
+#define BCHP_EBI_ECR_timeout_count_SHIFT                           0
+#define BCHP_EBI_ECR_timeout_count_DEFAULT                         0x00000400
+
+/***************************************************************************
+ *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
+ ***************************************************************************/
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK             0x80000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT            31
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK             0x40000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT            30
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK             0x20000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT            29
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK             0x10000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT            28
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK            0x08000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT           27
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK            0x04000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT           26
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK         0x02000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT        25
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK         0x01000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT        24
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:06] */
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK                    0x00ffffc0
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT                   6
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs5 [05:05] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_MASK             0x00000020
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_SHIFT            5
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK             0x00000010
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT            4
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK             0x00000008
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT            3
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK             0x00000004
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT            2
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK             0x00000002
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT            1
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK             0x00000001
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT            0
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TA_CFG - EBI TA Configuration Register
+ ***************************************************************************/
+/* EBI :: TA_CFG :: reserved0 [31:04] */
+#define BCHP_EBI_TA_CFG_reserved0_MASK                             0xfffffff0
+#define BCHP_EBI_TA_CFG_reserved0_SHIFT                            4
+
+/* EBI :: TA_CFG :: use_ta3 [03:03] */
+#define BCHP_EBI_TA_CFG_use_ta3_MASK                               0x00000008
+#define BCHP_EBI_TA_CFG_use_ta3_SHIFT                              3
+#define BCHP_EBI_TA_CFG_use_ta3_DEFAULT                            0x00000001
+
+/* EBI :: TA_CFG :: use_ta2 [02:02] */
+#define BCHP_EBI_TA_CFG_use_ta2_MASK                               0x00000004
+#define BCHP_EBI_TA_CFG_use_ta2_SHIFT                              2
+#define BCHP_EBI_TA_CFG_use_ta2_DEFAULT                            0x00000000
+
+/* EBI :: TA_CFG :: use_ta1 [01:01] */
+#define BCHP_EBI_TA_CFG_use_ta1_MASK                               0x00000002
+#define BCHP_EBI_TA_CFG_use_ta1_SHIFT                              1
+#define BCHP_EBI_TA_CFG_use_ta1_DEFAULT                            0x00000001
+
+/* EBI :: TA_CFG :: reserved1 [00:00] */
+#define BCHP_EBI_TA_CFG_reserved1_MASK                             0x00000001
+#define BCHP_EBI_TA_CFG_reserved1_SHIFT                            0
+
+/***************************************************************************
+ *CS_SPI_SELECT - SPI CS Select
+ ***************************************************************************/
+/* EBI :: CS_SPI_SELECT :: reserved0 [31:16] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK                      0xffff0000
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT                     16
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_7_USES_SPI [15:15] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_MASK              0x00008000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_SHIFT             15
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK              0x00004000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT             14
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK              0x00002000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT             13
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK              0x00001000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT             12
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK              0x00000800
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT             11
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK              0x00000400
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT             10
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK              0x00000200
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT             9
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK              0x00000100
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT             8
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_7_SEL [07:07] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_MASK               0x00000080
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_SHIFT              7
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK               0x00000040
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT              6
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK               0x00000020
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT              5
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK               0x00000010
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT              4
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK               0x00000008
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT              3
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK               0x00000004
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT              2
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK               0x00000002
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT              1
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK               0x00000001
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT              0
+
+/***************************************************************************
+ *ARRAY_ADDRESS - EBI Data Array Address
+ ***************************************************************************/
+/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK                        0xfffffe00
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT                       9
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT                     0x00000000
+
+/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK                      0x000001f8
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT                     3
+
+/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK                         0x00000007
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT                        0
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE                            0x0041aa00
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_START                           0
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_END                             127
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE                    32
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+/* EBI :: DATA_ARRAYi :: WORD [31:00] */
+#define BCHP_EBI_DATA_ARRAYi_WORD_MASK                             0xffffffff
+#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT                            0
+
+
+#endif /* #ifndef BCHP_EBI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_edu.h b/include/linux/brcmstb/7435b0/bchp_edu.h
new file mode 100644
index 0000000..ae5951a
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_edu.h
@@ -0,0 +1,193 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:13 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_edu.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 2:16p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EDU_H__
+#define BCHP_EDU_H__
+
+/***************************************************************************
+ *EDU - EDU Registers
+ ***************************************************************************/
+#define BCHP_EDU_CONFIG                          0x0041d100 /* EDU Config */
+#define BCHP_EDU_DRAM_ADDR                       0x0041d104 /* DRAM Address for transaction */
+#define BCHP_EDU_EXT_ADDR                        0x0041d108 /* External Address for transaction */
+#define BCHP_EDU_LENGTH                          0x0041d10c /* Length of transaction */
+#define BCHP_EDU_CMD                             0x0041d110 /* Command Type and Start */
+#define BCHP_EDU_STOP                            0x0041d114 /* Stop */
+#define BCHP_EDU_STATUS                          0x0041d118 /* EDU Status bits */
+#define BCHP_EDU_DONE                            0x0041d11c /* EDU Done bits */
+#define BCHP_EDU_ERR_STATUS                      0x0041d120 /* EDU Error Status */
+
+/***************************************************************************
+ *CONFIG - EDU Config
+ ***************************************************************************/
+/* EDU :: CONFIG :: reserved0 [31:03] */
+#define BCHP_EDU_CONFIG_reserved0_MASK                             0xfffffff8
+#define BCHP_EDU_CONFIG_reserved0_SHIFT                            3
+
+/* EDU :: CONFIG :: Swap [02:01] */
+#define BCHP_EDU_CONFIG_Swap_MASK                                  0x00000006
+#define BCHP_EDU_CONFIG_Swap_SHIFT                                 1
+#define BCHP_EDU_CONFIG_Swap_DEFAULT                               0x00000000
+
+/* EDU :: CONFIG :: Mode [00:00] */
+#define BCHP_EDU_CONFIG_Mode_MASK                                  0x00000001
+#define BCHP_EDU_CONFIG_Mode_SHIFT                                 0
+#define BCHP_EDU_CONFIG_Mode_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *DRAM_ADDR - DRAM Address for transaction
+ ***************************************************************************/
+/* EDU :: DRAM_ADDR :: Address [31:02] */
+#define BCHP_EDU_DRAM_ADDR_Address_MASK                            0xfffffffc
+#define BCHP_EDU_DRAM_ADDR_Address_SHIFT                           2
+#define BCHP_EDU_DRAM_ADDR_Address_DEFAULT                         0x00000000
+
+/* EDU :: DRAM_ADDR :: reserved0 [01:00] */
+#define BCHP_EDU_DRAM_ADDR_reserved0_MASK                          0x00000003
+#define BCHP_EDU_DRAM_ADDR_reserved0_SHIFT                         0
+
+/***************************************************************************
+ *EXT_ADDR - External Address for transaction
+ ***************************************************************************/
+/* EDU :: EXT_ADDR :: Address [31:02] */
+#define BCHP_EDU_EXT_ADDR_Address_MASK                             0xfffffffc
+#define BCHP_EDU_EXT_ADDR_Address_SHIFT                            2
+#define BCHP_EDU_EXT_ADDR_Address_DEFAULT                          0x00000000
+
+/* EDU :: EXT_ADDR :: reserved0 [01:00] */
+#define BCHP_EDU_EXT_ADDR_reserved0_MASK                           0x00000003
+#define BCHP_EDU_EXT_ADDR_reserved0_SHIFT                          0
+
+/***************************************************************************
+ *LENGTH - Length of transaction
+ ***************************************************************************/
+/* EDU :: LENGTH :: reserved0 [31:10] */
+#define BCHP_EDU_LENGTH_reserved0_MASK                             0xfffffc00
+#define BCHP_EDU_LENGTH_reserved0_SHIFT                            10
+
+/* EDU :: LENGTH :: Length [09:00] */
+#define BCHP_EDU_LENGTH_Length_MASK                                0x000003ff
+#define BCHP_EDU_LENGTH_Length_SHIFT                               0
+#define BCHP_EDU_LENGTH_Length_DEFAULT                             0x00000000
+
+/***************************************************************************
+ *CMD - Command Type and Start
+ ***************************************************************************/
+/* EDU :: CMD :: reserved0 [31:01] */
+#define BCHP_EDU_CMD_reserved0_MASK                                0xfffffffe
+#define BCHP_EDU_CMD_reserved0_SHIFT                               1
+
+/* EDU :: CMD :: Cmd [00:00] */
+#define BCHP_EDU_CMD_Cmd_MASK                                      0x00000001
+#define BCHP_EDU_CMD_Cmd_SHIFT                                     0
+#define BCHP_EDU_CMD_Cmd_DEFAULT                                   0x00000000
+
+/***************************************************************************
+ *STOP - Stop
+ ***************************************************************************/
+/* EDU :: STOP :: reserved0 [31:01] */
+#define BCHP_EDU_STOP_reserved0_MASK                               0xfffffffe
+#define BCHP_EDU_STOP_reserved0_SHIFT                              1
+
+/* EDU :: STOP :: Stop [00:00] */
+#define BCHP_EDU_STOP_Stop_MASK                                    0x00000001
+#define BCHP_EDU_STOP_Stop_SHIFT                                   0
+#define BCHP_EDU_STOP_Stop_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *STATUS - EDU Status bits
+ ***************************************************************************/
+/* EDU :: STATUS :: reserved0 [31:02] */
+#define BCHP_EDU_STATUS_reserved0_MASK                             0xfffffffc
+#define BCHP_EDU_STATUS_reserved0_SHIFT                            2
+
+/* EDU :: STATUS :: Pending [01:01] */
+#define BCHP_EDU_STATUS_Pending_MASK                               0x00000002
+#define BCHP_EDU_STATUS_Pending_SHIFT                              1
+#define BCHP_EDU_STATUS_Pending_DEFAULT                            0x00000000
+
+/* EDU :: STATUS :: Active [00:00] */
+#define BCHP_EDU_STATUS_Active_MASK                                0x00000001
+#define BCHP_EDU_STATUS_Active_SHIFT                               0
+#define BCHP_EDU_STATUS_Active_DEFAULT                             0x00000000
+
+/***************************************************************************
+ *DONE - EDU Done bits
+ ***************************************************************************/
+/* EDU :: DONE :: reserved0 [31:02] */
+#define BCHP_EDU_DONE_reserved0_MASK                               0xfffffffc
+#define BCHP_EDU_DONE_reserved0_SHIFT                              2
+
+/* EDU :: DONE :: Done [01:00] */
+#define BCHP_EDU_DONE_Done_MASK                                    0x00000003
+#define BCHP_EDU_DONE_Done_SHIFT                                   0
+#define BCHP_EDU_DONE_Done_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *ERR_STATUS - EDU Error Status
+ ***************************************************************************/
+/* EDU :: ERR_STATUS :: reserved0 [31:04] */
+#define BCHP_EDU_ERR_STATUS_reserved0_MASK                         0xfffffff0
+#define BCHP_EDU_ERR_STATUS_reserved0_SHIFT                        4
+
+/* EDU :: ERR_STATUS :: NandWrErr [03:03] */
+#define BCHP_EDU_ERR_STATUS_NandWrErr_MASK                         0x00000008
+#define BCHP_EDU_ERR_STATUS_NandWrErr_SHIFT                        3
+#define BCHP_EDU_ERR_STATUS_NandWrErr_DEFAULT                      0x00000000
+
+/* EDU :: ERR_STATUS :: NandECCuncor [02:02] */
+#define BCHP_EDU_ERR_STATUS_NandECCuncor_MASK                      0x00000004
+#define BCHP_EDU_ERR_STATUS_NandECCuncor_SHIFT                     2
+#define BCHP_EDU_ERR_STATUS_NandECCuncor_DEFAULT                   0x00000000
+
+/* EDU :: ERR_STATUS :: NandECCcor [01:01] */
+#define BCHP_EDU_ERR_STATUS_NandECCcor_MASK                        0x00000002
+#define BCHP_EDU_ERR_STATUS_NandECCcor_SHIFT                       1
+#define BCHP_EDU_ERR_STATUS_NandECCcor_DEFAULT                     0x00000000
+
+/* EDU :: ERR_STATUS :: ErrAck [00:00] */
+#define BCHP_EDU_ERR_STATUS_ErrAck_MASK                            0x00000001
+#define BCHP_EDU_ERR_STATUS_ErrAck_SHIFT                           0
+#define BCHP_EDU_ERR_STATUS_ErrAck_DEFAULT                         0x00000000
+
+#endif /* #ifndef BCHP_EDU_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_flash_dma.h b/include/linux/brcmstb/7435b0/bchp_flash_dma.h
new file mode 100644
index 0000000..bce6025
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_flash_dma.h
@@ -0,0 +1,175 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Thu Mar 15 03:09:23 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_FLASH_DMA_H__
+#define BCHP_FLASH_DMA_H__
+
+/***************************************************************************
+ *FLASH_DMA - Descriptor Flash DMA Registers
+ ***************************************************************************/
+#define BCHP_FLASH_DMA_REVISION                  0x0041d000 /* NAND Revision */
+#define BCHP_FLASH_DMA_FIRST_DESC                0x0041d004 /* DMA First descriptor address */
+#define BCHP_FLASH_DMA_CTRL                      0x0041d008 /* DMA CTRL */
+#define BCHP_FLASH_DMA_MODE                      0x0041d00c /* DMA MODE */
+#define BCHP_FLASH_DMA_STATUS                    0x0041d010 /* DMA STATUS */
+#define BCHP_FLASH_DMA_INTERRUPT_DESC            0x0041d014 /* DMA INTERRUPT DESC */
+#define BCHP_FLASH_DMA_ERROR_STATUS              0x0041d018 /* DMA ERROR STATUS */
+#define BCHP_FLASH_DMA_CURRENT_DESC              0x0041d01c /* DMA CURRENT DESC */
+
+/***************************************************************************
+ *REVISION - NAND Revision
+ ***************************************************************************/
+/* FLASH_DMA :: REVISION :: reserved0 [31:16] */
+#define BCHP_FLASH_DMA_REVISION_reserved0_MASK                     0xffff0000
+#define BCHP_FLASH_DMA_REVISION_reserved0_SHIFT                    16
+
+/* FLASH_DMA :: REVISION :: MAJOR [15:08] */
+#define BCHP_FLASH_DMA_REVISION_MAJOR_MASK                         0x0000ff00
+#define BCHP_FLASH_DMA_REVISION_MAJOR_SHIFT                        8
+#define BCHP_FLASH_DMA_REVISION_MAJOR_DEFAULT                      0x00000000
+
+/* FLASH_DMA :: REVISION :: MINOR [07:00] */
+#define BCHP_FLASH_DMA_REVISION_MINOR_MASK                         0x000000ff
+#define BCHP_FLASH_DMA_REVISION_MINOR_SHIFT                        0
+#define BCHP_FLASH_DMA_REVISION_MINOR_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *FIRST_DESC - DMA First descriptor address
+ ***************************************************************************/
+/* FLASH_DMA :: FIRST_DESC :: ADDR [31:00] */
+#define BCHP_FLASH_DMA_FIRST_DESC_ADDR_MASK                        0xffffffff
+#define BCHP_FLASH_DMA_FIRST_DESC_ADDR_SHIFT                       0
+#define BCHP_FLASH_DMA_FIRST_DESC_ADDR_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *CTRL - DMA CTRL
+ ***************************************************************************/
+/* FLASH_DMA :: CTRL :: reserved0 [31:02] */
+#define BCHP_FLASH_DMA_CTRL_reserved0_MASK                         0xfffffffc
+#define BCHP_FLASH_DMA_CTRL_reserved0_SHIFT                        2
+
+/* FLASH_DMA :: CTRL :: WAKE [01:01] */
+#define BCHP_FLASH_DMA_CTRL_WAKE_MASK                              0x00000002
+#define BCHP_FLASH_DMA_CTRL_WAKE_SHIFT                             1
+#define BCHP_FLASH_DMA_CTRL_WAKE_DEFAULT                           0x00000000
+
+/* FLASH_DMA :: CTRL :: RUN [00:00] */
+#define BCHP_FLASH_DMA_CTRL_RUN_MASK                               0x00000001
+#define BCHP_FLASH_DMA_CTRL_RUN_SHIFT                              0
+#define BCHP_FLASH_DMA_CTRL_RUN_DEFAULT                            0x00000000
+
+/***************************************************************************
+ *MODE - DMA MODE
+ ***************************************************************************/
+/* FLASH_DMA :: MODE :: reserved0 [31:02] */
+#define BCHP_FLASH_DMA_MODE_reserved0_MASK                         0xfffffffc
+#define BCHP_FLASH_DMA_MODE_reserved0_SHIFT                        2
+
+/* FLASH_DMA :: MODE :: STOP_ON_ERROR [01:01] */
+#define BCHP_FLASH_DMA_MODE_STOP_ON_ERROR_MASK                     0x00000002
+#define BCHP_FLASH_DMA_MODE_STOP_ON_ERROR_SHIFT                    1
+#define BCHP_FLASH_DMA_MODE_STOP_ON_ERROR_DEFAULT                  0x00000000
+
+/* FLASH_DMA :: MODE :: MODE [00:00] */
+#define BCHP_FLASH_DMA_MODE_MODE_MASK                              0x00000001
+#define BCHP_FLASH_DMA_MODE_MODE_SHIFT                             0
+#define BCHP_FLASH_DMA_MODE_MODE_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *STATUS - DMA STATUS
+ ***************************************************************************/
+/* FLASH_DMA :: STATUS :: reserved0 [31:28] */
+#define BCHP_FLASH_DMA_STATUS_reserved0_MASK                       0xf0000000
+#define BCHP_FLASH_DMA_STATUS_reserved0_SHIFT                      28
+
+/* FLASH_DMA :: STATUS :: RBUS_STATE [27:19] */
+#define BCHP_FLASH_DMA_STATUS_RBUS_STATE_MASK                      0x0ff80000
+#define BCHP_FLASH_DMA_STATUS_RBUS_STATE_SHIFT                     19
+
+/* FLASH_DMA :: STATUS :: SCB_STATE [18:14] */
+#define BCHP_FLASH_DMA_STATUS_SCB_STATE_MASK                       0x0007c000
+#define BCHP_FLASH_DMA_STATUS_SCB_STATE_SHIFT                      14
+
+/* FLASH_DMA :: STATUS :: PROCESS_STATE [13:07] */
+#define BCHP_FLASH_DMA_STATUS_PROCESS_STATE_MASK                   0x00003f80
+#define BCHP_FLASH_DMA_STATUS_PROCESS_STATE_SHIFT                  7
+
+/* FLASH_DMA :: STATUS :: DMA_STATE [06:02] */
+#define BCHP_FLASH_DMA_STATUS_DMA_STATE_MASK                       0x0000007c
+#define BCHP_FLASH_DMA_STATUS_DMA_STATE_SHIFT                      2
+
+/* FLASH_DMA :: STATUS :: WAKE [01:00] */
+#define BCHP_FLASH_DMA_STATUS_WAKE_MASK                            0x00000003
+#define BCHP_FLASH_DMA_STATUS_WAKE_SHIFT                           0
+
+/***************************************************************************
+ *INTERRUPT_DESC - DMA INTERRUPT DESC
+ ***************************************************************************/
+/* FLASH_DMA :: INTERRUPT_DESC :: ADDR [31:00] */
+#define BCHP_FLASH_DMA_INTERRUPT_DESC_ADDR_MASK                    0xffffffff
+#define BCHP_FLASH_DMA_INTERRUPT_DESC_ADDR_SHIFT                   0
+
+/***************************************************************************
+ *ERROR_STATUS - DMA ERROR STATUS
+ ***************************************************************************/
+/* FLASH_DMA :: ERROR_STATUS :: reserved0 [31:03] */
+#define BCHP_FLASH_DMA_ERROR_STATUS_reserved0_MASK                 0xfffffff8
+#define BCHP_FLASH_DMA_ERROR_STATUS_reserved0_SHIFT                3
+
+/* FLASH_DMA :: ERROR_STATUS :: NAND_ECCuncor [02:02] */
+#define BCHP_FLASH_DMA_ERROR_STATUS_NAND_ECCuncor_MASK             0x00000004
+#define BCHP_FLASH_DMA_ERROR_STATUS_NAND_ECCuncor_SHIFT            2
+
+/* FLASH_DMA :: ERROR_STATUS :: MISMATCH [01:01] */
+#define BCHP_FLASH_DMA_ERROR_STATUS_MISMATCH_MASK                  0x00000002
+#define BCHP_FLASH_DMA_ERROR_STATUS_MISMATCH_SHIFT                 1
+
+/* FLASH_DMA :: ERROR_STATUS :: TIMEOUT [00:00] */
+#define BCHP_FLASH_DMA_ERROR_STATUS_TIMEOUT_MASK                   0x00000001
+#define BCHP_FLASH_DMA_ERROR_STATUS_TIMEOUT_SHIFT                  0
+
+/***************************************************************************
+ *CURRENT_DESC - DMA CURRENT DESC
+ ***************************************************************************/
+/* FLASH_DMA :: CURRENT_DESC :: ADDR [31:00] */
+#define BCHP_FLASH_DMA_CURRENT_DESC_ADDR_MASK                      0xffffffff
+#define BCHP_FLASH_DMA_CURRENT_DESC_ADDR_SHIFT                     0
+
+#endif /* #ifndef BCHP_FLASH_DMA_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_gio.h b/include/linux/brcmstb/7435b0/bchp_gio.h
new file mode 100644
index 0000000..59845c3
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_gio.h
@@ -0,0 +1,371 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:09 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_gio.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 2:24p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_GIO_H__
+#define BCHP_GIO_H__
+
+/***************************************************************************
+ *GIO - GPIO
+ ***************************************************************************/
+#define BCHP_GIO_ODEN_LO                         0x00406700 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE [31:0] */
+#define BCHP_GIO_DATA_LO                         0x00406704 /* GENERAL PURPOSE I/O DATA [31:0] */
+#define BCHP_GIO_IODIR_LO                        0x00406708 /* GENERAL PURPOSE I/O DIRECTION [31:0] */
+#define BCHP_GIO_EC_LO                           0x0040670c /* GENERAL PURPOSE I/O EDGE CONFIGURATION [31:0] */
+#define BCHP_GIO_EI_LO                           0x00406710 /* GENERAL PURPOSE I/O EDGE INSENSITIVE [31:0] */
+#define BCHP_GIO_MASK_LO                         0x00406714 /* GENERAL PURPOSE I/O INTERRUPT MASK [31:0] */
+#define BCHP_GIO_LEVEL_LO                        0x00406718 /* GENERAL PURPOSE I/O INTERRUPT TYPE [31:0] */
+#define BCHP_GIO_STAT_LO                         0x0040671c /* GENERAL PURPOSE I/O INTERRUPT STATUS [31:0] */
+#define BCHP_GIO_ODEN_HI                         0x00406720 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE [63:32] */
+#define BCHP_GIO_DATA_HI                         0x00406724 /* GENERAL PURPOSE I/O DATA [63:32] */
+#define BCHP_GIO_IODIR_HI                        0x00406728 /* GENERAL PURPOSE I/O DIRECTION [63:32] */
+#define BCHP_GIO_EC_HI                           0x0040672c /* GENERAL PURPOSE I/O EDGE CONFIGURATION [63:32] */
+#define BCHP_GIO_EI_HI                           0x00406730 /* GENERAL PURPOSE I/O EDGE INSENSITIVE [63:32] */
+#define BCHP_GIO_MASK_HI                         0x00406734 /* GENERAL PURPOSE I/O INTERRUPT MASK [63:32] */
+#define BCHP_GIO_LEVEL_HI                        0x00406738 /* GENERAL PURPOSE I/O INTERRUPT TYPE [63:32] */
+#define BCHP_GIO_STAT_HI                         0x0040673c /* GENERAL PURPOSE I/O INTERRUPT STATUS [63:32] */
+#define BCHP_GIO_ODEN_EXT                        0x00406740 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE [95:64] (GPIO[89:64], SGPIO[5:0]) */
+#define BCHP_GIO_DATA_EXT                        0x00406744 /* GENERAL PURPOSE I/O DATA [95:64] (GPIO[89:64], SGPIO[5:0]) */
+#define BCHP_GIO_IODIR_EXT                       0x00406748 /* GENERAL PURPOSE I/O DIRECTION [95:64] (GPIO[89:64], SGPIO[5:0]) */
+#define BCHP_GIO_EC_EXT                          0x0040674c /* GENERAL PURPOSE I/O EDGE CONFIGURATION [95:64] (GPIO[89:64], SGPIO[5:0]) */
+#define BCHP_GIO_EI_EXT                          0x00406750 /* GENERAL PURPOSE I/O EDGE INSENSITIVE [95:64] (GPIO[89:64], SGPIO[5:0]) */
+#define BCHP_GIO_MASK_EXT                        0x00406754 /* GENERAL PURPOSE I/O INTERRUPT MASK [95:64] (GPIO[89:64], SGPIO[5:0]) */
+#define BCHP_GIO_LEVEL_EXT                       0x00406758 /* GENERAL PURPOSE I/O INTERRUPT TYPE [95:64] (GPIO[89:64], SGPIO[5:0]) */
+#define BCHP_GIO_STAT_EXT                        0x0040675c /* GENERAL PURPOSE I/O INTERRUPT STATUS [95:64] (GPIO[89:64], SGPIO[5:0]) */
+#define BCHP_GIO_ODEN_EXT_HI                     0x00406760 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE [116:96] (GPIO[110:90]) */
+#define BCHP_GIO_DATA_EXT_HI                     0x00406764 /* GENERAL PURPOSE I/O DATA [116:96] (GPIO[110:90]) */
+#define BCHP_GIO_IODIR_EXT_HI                    0x00406768 /* GENERAL PURPOSE I/O DIRECTION [116:96] (GPIO[110:90]) */
+#define BCHP_GIO_EC_EXT_HI                       0x0040676c /* GENERAL PURPOSE I/O EDGE CONFIGURATION [116:96] (GPIO[110:90]) */
+#define BCHP_GIO_EI_EXT_HI                       0x00406770 /* GENERAL PURPOSE I/O EDGE INSENSITIVE [116:96] (GPIO[110:90]) */
+#define BCHP_GIO_MASK_EXT_HI                     0x00406774 /* GENERAL PURPOSE I/O INTERRUPT MASK [116:96] (GPIO[110:90]) */
+#define BCHP_GIO_LEVEL_EXT_HI                    0x00406778 /* GENERAL PURPOSE I/O INTERRUPT TYPE [116:96] (GPIO[110:90]) */
+#define BCHP_GIO_STAT_EXT_HI                     0x0040677c /* GENERAL PURPOSE I/O INTERRUPT STATUS [116:96] (GPIO[110:90]) */
+
+/***************************************************************************
+ *ODEN_LO - GENERAL PURPOSE I/O OPEN DRAIN ENABLE [31:0]
+ ***************************************************************************/
+/* GIO :: ODEN_LO :: oden [31:00] */
+#define BCHP_GIO_ODEN_LO_oden_MASK                                 0xffffffff
+#define BCHP_GIO_ODEN_LO_oden_SHIFT                                0
+#define BCHP_GIO_ODEN_LO_oden_DEFAULT                              0x00000000
+
+/***************************************************************************
+ *DATA_LO - GENERAL PURPOSE I/O DATA [31:0]
+ ***************************************************************************/
+/* GIO :: DATA_LO :: data [31:00] */
+#define BCHP_GIO_DATA_LO_data_MASK                                 0xffffffff
+#define BCHP_GIO_DATA_LO_data_SHIFT                                0
+#define BCHP_GIO_DATA_LO_data_DEFAULT                              0x00000000
+
+/***************************************************************************
+ *IODIR_LO - GENERAL PURPOSE I/O DIRECTION [31:0]
+ ***************************************************************************/
+/* GIO :: IODIR_LO :: iodir [31:00] */
+#define BCHP_GIO_IODIR_LO_iodir_MASK                               0xffffffff
+#define BCHP_GIO_IODIR_LO_iodir_SHIFT                              0
+#define BCHP_GIO_IODIR_LO_iodir_DEFAULT                            0xffffffff
+
+/***************************************************************************
+ *EC_LO - GENERAL PURPOSE I/O EDGE CONFIGURATION [31:0]
+ ***************************************************************************/
+/* GIO :: EC_LO :: edge_config [31:00] */
+#define BCHP_GIO_EC_LO_edge_config_MASK                            0xffffffff
+#define BCHP_GIO_EC_LO_edge_config_SHIFT                           0
+#define BCHP_GIO_EC_LO_edge_config_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *EI_LO - GENERAL PURPOSE I/O EDGE INSENSITIVE [31:0]
+ ***************************************************************************/
+/* GIO :: EI_LO :: edge_insensitive [31:00] */
+#define BCHP_GIO_EI_LO_edge_insensitive_MASK                       0xffffffff
+#define BCHP_GIO_EI_LO_edge_insensitive_SHIFT                      0
+#define BCHP_GIO_EI_LO_edge_insensitive_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *MASK_LO - GENERAL PURPOSE I/O INTERRUPT MASK [31:0]
+ ***************************************************************************/
+/* GIO :: MASK_LO :: irq_mask [31:00] */
+#define BCHP_GIO_MASK_LO_irq_mask_MASK                             0xffffffff
+#define BCHP_GIO_MASK_LO_irq_mask_SHIFT                            0
+#define BCHP_GIO_MASK_LO_irq_mask_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *LEVEL_LO - GENERAL PURPOSE I/O INTERRUPT TYPE [31:0]
+ ***************************************************************************/
+/* GIO :: LEVEL_LO :: level [31:00] */
+#define BCHP_GIO_LEVEL_LO_level_MASK                               0xffffffff
+#define BCHP_GIO_LEVEL_LO_level_SHIFT                              0
+#define BCHP_GIO_LEVEL_LO_level_DEFAULT                            0x00000000
+
+/***************************************************************************
+ *STAT_LO - GENERAL PURPOSE I/O INTERRUPT STATUS [31:0]
+ ***************************************************************************/
+/* GIO :: STAT_LO :: irq_status [31:00] */
+#define BCHP_GIO_STAT_LO_irq_status_MASK                           0xffffffff
+#define BCHP_GIO_STAT_LO_irq_status_SHIFT                          0
+#define BCHP_GIO_STAT_LO_irq_status_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *ODEN_HI - GENERAL PURPOSE I/O OPEN DRAIN ENABLE [63:32]
+ ***************************************************************************/
+/* GIO :: ODEN_HI :: oden [31:00] */
+#define BCHP_GIO_ODEN_HI_oden_MASK                                 0xffffffff
+#define BCHP_GIO_ODEN_HI_oden_SHIFT                                0
+#define BCHP_GIO_ODEN_HI_oden_DEFAULT                              0x00000000
+
+/***************************************************************************
+ *DATA_HI - GENERAL PURPOSE I/O DATA [63:32]
+ ***************************************************************************/
+/* GIO :: DATA_HI :: data [31:00] */
+#define BCHP_GIO_DATA_HI_data_MASK                                 0xffffffff
+#define BCHP_GIO_DATA_HI_data_SHIFT                                0
+#define BCHP_GIO_DATA_HI_data_DEFAULT                              0x00000000
+
+/***************************************************************************
+ *IODIR_HI - GENERAL PURPOSE I/O DIRECTION [63:32]
+ ***************************************************************************/
+/* GIO :: IODIR_HI :: iodir [31:00] */
+#define BCHP_GIO_IODIR_HI_iodir_MASK                               0xffffffff
+#define BCHP_GIO_IODIR_HI_iodir_SHIFT                              0
+#define BCHP_GIO_IODIR_HI_iodir_DEFAULT                            0x000001ff
+
+/***************************************************************************
+ *EC_HI - GENERAL PURPOSE I/O EDGE CONFIGURATION [63:32]
+ ***************************************************************************/
+/* GIO :: EC_HI :: edge_config [31:00] */
+#define BCHP_GIO_EC_HI_edge_config_MASK                            0xffffffff
+#define BCHP_GIO_EC_HI_edge_config_SHIFT                           0
+#define BCHP_GIO_EC_HI_edge_config_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *EI_HI - GENERAL PURPOSE I/O EDGE INSENSITIVE [63:32]
+ ***************************************************************************/
+/* GIO :: EI_HI :: edge_insensitive [31:00] */
+#define BCHP_GIO_EI_HI_edge_insensitive_MASK                       0xffffffff
+#define BCHP_GIO_EI_HI_edge_insensitive_SHIFT                      0
+#define BCHP_GIO_EI_HI_edge_insensitive_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *MASK_HI - GENERAL PURPOSE I/O INTERRUPT MASK [63:32]
+ ***************************************************************************/
+/* GIO :: MASK_HI :: irq_mask [31:00] */
+#define BCHP_GIO_MASK_HI_irq_mask_MASK                             0xffffffff
+#define BCHP_GIO_MASK_HI_irq_mask_SHIFT                            0
+#define BCHP_GIO_MASK_HI_irq_mask_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *LEVEL_HI - GENERAL PURPOSE I/O INTERRUPT TYPE [63:32]
+ ***************************************************************************/
+/* GIO :: LEVEL_HI :: level [31:00] */
+#define BCHP_GIO_LEVEL_HI_level_MASK                               0xffffffff
+#define BCHP_GIO_LEVEL_HI_level_SHIFT                              0
+#define BCHP_GIO_LEVEL_HI_level_DEFAULT                            0x00000000
+
+/***************************************************************************
+ *STAT_HI - GENERAL PURPOSE I/O INTERRUPT STATUS [63:32]
+ ***************************************************************************/
+/* GIO :: STAT_HI :: irq_status [31:00] */
+#define BCHP_GIO_STAT_HI_irq_status_MASK                           0xffffffff
+#define BCHP_GIO_STAT_HI_irq_status_SHIFT                          0
+#define BCHP_GIO_STAT_HI_irq_status_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *ODEN_EXT - GENERAL PURPOSE I/O OPEN DRAIN ENABLE [95:64] (GPIO[89:64], SGPIO[5:0])
+ ***************************************************************************/
+/* GIO :: ODEN_EXT :: oden [31:00] */
+#define BCHP_GIO_ODEN_EXT_oden_MASK                                0xffffffff
+#define BCHP_GIO_ODEN_EXT_oden_SHIFT                               0
+#define BCHP_GIO_ODEN_EXT_oden_DEFAULT                             0x00000000
+
+/***************************************************************************
+ *DATA_EXT - GENERAL PURPOSE I/O DATA [95:64] (GPIO[89:64], SGPIO[5:0])
+ ***************************************************************************/
+/* GIO :: DATA_EXT :: data [31:00] */
+#define BCHP_GIO_DATA_EXT_data_MASK                                0xffffffff
+#define BCHP_GIO_DATA_EXT_data_SHIFT                               0
+#define BCHP_GIO_DATA_EXT_data_DEFAULT                             0x00000000
+
+/***************************************************************************
+ *IODIR_EXT - GENERAL PURPOSE I/O DIRECTION [95:64] (GPIO[89:64], SGPIO[5:0])
+ ***************************************************************************/
+/* GIO :: IODIR_EXT :: iodir [31:00] */
+#define BCHP_GIO_IODIR_EXT_iodir_MASK                              0xffffffff
+#define BCHP_GIO_IODIR_EXT_iodir_SHIFT                             0
+#define BCHP_GIO_IODIR_EXT_iodir_DEFAULT                           0xffffffff
+
+/***************************************************************************
+ *EC_EXT - GENERAL PURPOSE I/O EDGE CONFIGURATION [95:64] (GPIO[89:64], SGPIO[5:0])
+ ***************************************************************************/
+/* GIO :: EC_EXT :: edge_config [31:00] */
+#define BCHP_GIO_EC_EXT_edge_config_MASK                           0xffffffff
+#define BCHP_GIO_EC_EXT_edge_config_SHIFT                          0
+#define BCHP_GIO_EC_EXT_edge_config_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *EI_EXT - GENERAL PURPOSE I/O EDGE INSENSITIVE [95:64] (GPIO[89:64], SGPIO[5:0])
+ ***************************************************************************/
+/* GIO :: EI_EXT :: edge_insensitive [31:00] */
+#define BCHP_GIO_EI_EXT_edge_insensitive_MASK                      0xffffffff
+#define BCHP_GIO_EI_EXT_edge_insensitive_SHIFT                     0
+#define BCHP_GIO_EI_EXT_edge_insensitive_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *MASK_EXT - GENERAL PURPOSE I/O INTERRUPT MASK [95:64] (GPIO[89:64], SGPIO[5:0])
+ ***************************************************************************/
+/* GIO :: MASK_EXT :: irq_mask [31:00] */
+#define BCHP_GIO_MASK_EXT_irq_mask_MASK                            0xffffffff
+#define BCHP_GIO_MASK_EXT_irq_mask_SHIFT                           0
+#define BCHP_GIO_MASK_EXT_irq_mask_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *LEVEL_EXT - GENERAL PURPOSE I/O INTERRUPT TYPE [95:64] (GPIO[89:64], SGPIO[5:0])
+ ***************************************************************************/
+/* GIO :: LEVEL_EXT :: level [31:00] */
+#define BCHP_GIO_LEVEL_EXT_level_MASK                              0xffffffff
+#define BCHP_GIO_LEVEL_EXT_level_SHIFT                             0
+#define BCHP_GIO_LEVEL_EXT_level_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *STAT_EXT - GENERAL PURPOSE I/O INTERRUPT STATUS [95:64] (GPIO[89:64], SGPIO[5:0])
+ ***************************************************************************/
+/* GIO :: STAT_EXT :: irq_status [31:00] */
+#define BCHP_GIO_STAT_EXT_irq_status_MASK                          0xffffffff
+#define BCHP_GIO_STAT_EXT_irq_status_SHIFT                         0
+#define BCHP_GIO_STAT_EXT_irq_status_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *ODEN_EXT_HI - GENERAL PURPOSE I/O OPEN DRAIN ENABLE [116:96] (GPIO[110:90])
+ ***************************************************************************/
+/* GIO :: ODEN_EXT_HI :: reserved0 [31:21] */
+#define BCHP_GIO_ODEN_EXT_HI_reserved0_MASK                        0xffe00000
+#define BCHP_GIO_ODEN_EXT_HI_reserved0_SHIFT                       21
+
+/* GIO :: ODEN_EXT_HI :: oden [20:00] */
+#define BCHP_GIO_ODEN_EXT_HI_oden_MASK                             0x001fffff
+#define BCHP_GIO_ODEN_EXT_HI_oden_SHIFT                            0
+#define BCHP_GIO_ODEN_EXT_HI_oden_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *DATA_EXT_HI - GENERAL PURPOSE I/O DATA [116:96] (GPIO[110:90])
+ ***************************************************************************/
+/* GIO :: DATA_EXT_HI :: reserved0 [31:21] */
+#define BCHP_GIO_DATA_EXT_HI_reserved0_MASK                        0xffe00000
+#define BCHP_GIO_DATA_EXT_HI_reserved0_SHIFT                       21
+
+/* GIO :: DATA_EXT_HI :: data [20:00] */
+#define BCHP_GIO_DATA_EXT_HI_data_MASK                             0x001fffff
+#define BCHP_GIO_DATA_EXT_HI_data_SHIFT                            0
+#define BCHP_GIO_DATA_EXT_HI_data_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *IODIR_EXT_HI - GENERAL PURPOSE I/O DIRECTION [116:96] (GPIO[110:90])
+ ***************************************************************************/
+/* GIO :: IODIR_EXT_HI :: reserved0 [31:21] */
+#define BCHP_GIO_IODIR_EXT_HI_reserved0_MASK                       0xffe00000
+#define BCHP_GIO_IODIR_EXT_HI_reserved0_SHIFT                      21
+
+/* GIO :: IODIR_EXT_HI :: iodir [20:00] */
+#define BCHP_GIO_IODIR_EXT_HI_iodir_MASK                           0x001fffff
+#define BCHP_GIO_IODIR_EXT_HI_iodir_SHIFT                          0
+#define BCHP_GIO_IODIR_EXT_HI_iodir_DEFAULT                        0x001fffff
+
+/***************************************************************************
+ *EC_EXT_HI - GENERAL PURPOSE I/O EDGE CONFIGURATION [116:96] (GPIO[110:90])
+ ***************************************************************************/
+/* GIO :: EC_EXT_HI :: reserved0 [31:21] */
+#define BCHP_GIO_EC_EXT_HI_reserved0_MASK                          0xffe00000
+#define BCHP_GIO_EC_EXT_HI_reserved0_SHIFT                         21
+
+/* GIO :: EC_EXT_HI :: edge_config [20:00] */
+#define BCHP_GIO_EC_EXT_HI_edge_config_MASK                        0x001fffff
+#define BCHP_GIO_EC_EXT_HI_edge_config_SHIFT                       0
+#define BCHP_GIO_EC_EXT_HI_edge_config_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *EI_EXT_HI - GENERAL PURPOSE I/O EDGE INSENSITIVE [116:96] (GPIO[110:90])
+ ***************************************************************************/
+/* GIO :: EI_EXT_HI :: reserved0 [31:21] */
+#define BCHP_GIO_EI_EXT_HI_reserved0_MASK                          0xffe00000
+#define BCHP_GIO_EI_EXT_HI_reserved0_SHIFT                         21
+
+/* GIO :: EI_EXT_HI :: edge_insensitive [20:00] */
+#define BCHP_GIO_EI_EXT_HI_edge_insensitive_MASK                   0x001fffff
+#define BCHP_GIO_EI_EXT_HI_edge_insensitive_SHIFT                  0
+#define BCHP_GIO_EI_EXT_HI_edge_insensitive_DEFAULT                0x00000000
+
+/***************************************************************************
+ *MASK_EXT_HI - GENERAL PURPOSE I/O INTERRUPT MASK [116:96] (GPIO[110:90])
+ ***************************************************************************/
+/* GIO :: MASK_EXT_HI :: reserved0 [31:21] */
+#define BCHP_GIO_MASK_EXT_HI_reserved0_MASK                        0xffe00000
+#define BCHP_GIO_MASK_EXT_HI_reserved0_SHIFT                       21
+
+/* GIO :: MASK_EXT_HI :: irq_mask [20:00] */
+#define BCHP_GIO_MASK_EXT_HI_irq_mask_MASK                         0x001fffff
+#define BCHP_GIO_MASK_EXT_HI_irq_mask_SHIFT                        0
+#define BCHP_GIO_MASK_EXT_HI_irq_mask_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *LEVEL_EXT_HI - GENERAL PURPOSE I/O INTERRUPT TYPE [116:96] (GPIO[110:90])
+ ***************************************************************************/
+/* GIO :: LEVEL_EXT_HI :: reserved0 [31:21] */
+#define BCHP_GIO_LEVEL_EXT_HI_reserved0_MASK                       0xffe00000
+#define BCHP_GIO_LEVEL_EXT_HI_reserved0_SHIFT                      21
+
+/* GIO :: LEVEL_EXT_HI :: level [20:00] */
+#define BCHP_GIO_LEVEL_EXT_HI_level_MASK                           0x001fffff
+#define BCHP_GIO_LEVEL_EXT_HI_level_SHIFT                          0
+#define BCHP_GIO_LEVEL_EXT_HI_level_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *STAT_EXT_HI - GENERAL PURPOSE I/O INTERRUPT STATUS [116:96] (GPIO[110:90])
+ ***************************************************************************/
+/* GIO :: STAT_EXT_HI :: reserved0 [31:21] */
+#define BCHP_GIO_STAT_EXT_HI_reserved0_MASK                        0xffe00000
+#define BCHP_GIO_STAT_EXT_HI_reserved0_SHIFT                       21
+
+/* GIO :: STAT_EXT_HI :: irq_status [20:00] */
+#define BCHP_GIO_STAT_EXT_HI_irq_status_MASK                       0x001fffff
+#define BCHP_GIO_STAT_EXT_HI_irq_status_SHIFT                      0
+#define BCHP_GIO_STAT_EXT_HI_irq_status_DEFAULT                    0x00000000
+
+#endif /* #ifndef BCHP_GIO_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_gio_aon.h b/include/linux/brcmstb/7435b0/bchp_gio_aon.h
new file mode 100644
index 0000000..6e90c37
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_gio_aon.h
@@ -0,0 +1,259 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:28 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_gio_aon.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 2:25p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_GIO_AON_H__
+#define BCHP_GIO_AON_H__
+
+/***************************************************************************
+ *GIO_AON - GPIO
+ ***************************************************************************/
+#define BCHP_GIO_AON_ODEN_LO                     0x004094c0 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE [17:0] */
+#define BCHP_GIO_AON_DATA_LO                     0x004094c4 /* GENERAL PURPOSE I/O DATA [17:0] */
+#define BCHP_GIO_AON_IODIR_LO                    0x004094c8 /* GENERAL PURPOSE I/O DIRECTION [17:0] */
+#define BCHP_GIO_AON_EC_LO                       0x004094cc /* GENERAL PURPOSE I/O EDGE CONFIGURATION [17:0] */
+#define BCHP_GIO_AON_EI_LO                       0x004094d0 /* GENERAL PURPOSE I/O EDGE INSENSITIVE [17:0] */
+#define BCHP_GIO_AON_MASK_LO                     0x004094d4 /* GENERAL PURPOSE I/O INTERRUPT MASK [17:0] */
+#define BCHP_GIO_AON_LEVEL_LO                    0x004094d8 /* GENERAL PURPOSE I/O INTERRUPT TYPE [17:0] */
+#define BCHP_GIO_AON_STAT_LO                     0x004094dc /* GENERAL PURPOSE I/O INTERRUPT STATUS [17:0] */
+#define BCHP_GIO_AON_ODEN_EXT                    0x004094e0 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE [65:64] (SGPIO[3:0]) */
+#define BCHP_GIO_AON_DATA_EXT                    0x004094e4 /* GENERAL PURPOSE I/O DATA [65:64] (SGPIO[3:0]) */
+#define BCHP_GIO_AON_IODIR_EXT                   0x004094e8 /* GENERAL PURPOSE I/O DIRECTION [65:64] (SGPIO[3:0]) */
+#define BCHP_GIO_AON_EC_EXT                      0x004094ec /* GENERAL PURPOSE I/O EDGE CONFIGURATION [65:64] (SGPIO[3:0]) */
+#define BCHP_GIO_AON_EI_EXT                      0x004094f0 /* GENERAL PURPOSE I/O EDGE INSENSITIVE [65:64] (SGPIO[3:0]) */
+#define BCHP_GIO_AON_MASK_EXT                    0x004094f4 /* GENERAL PURPOSE I/O INTERRUPT MASK [65:64] (SGPIO[3:0]) */
+#define BCHP_GIO_AON_LEVEL_EXT                   0x004094f8 /* GENERAL PURPOSE I/O INTERRUPT TYPE [65:64] (SGPIO[3:0]) */
+#define BCHP_GIO_AON_STAT_EXT                    0x004094fc /* GENERAL PURPOSE I/O INTERRUPT STATUS [65:64] (SGPIO[3:0]) */
+
+/***************************************************************************
+ *ODEN_LO - GENERAL PURPOSE I/O OPEN DRAIN ENABLE [17:0]
+ ***************************************************************************/
+/* GIO_AON :: ODEN_LO :: reserved0 [31:18] */
+#define BCHP_GIO_AON_ODEN_LO_reserved0_MASK                        0xfffc0000
+#define BCHP_GIO_AON_ODEN_LO_reserved0_SHIFT                       18
+
+/* GIO_AON :: ODEN_LO :: oden [17:00] */
+#define BCHP_GIO_AON_ODEN_LO_oden_MASK                             0x0003ffff
+#define BCHP_GIO_AON_ODEN_LO_oden_SHIFT                            0
+#define BCHP_GIO_AON_ODEN_LO_oden_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *DATA_LO - GENERAL PURPOSE I/O DATA [17:0]
+ ***************************************************************************/
+/* GIO_AON :: DATA_LO :: reserved0 [31:18] */
+#define BCHP_GIO_AON_DATA_LO_reserved0_MASK                        0xfffc0000
+#define BCHP_GIO_AON_DATA_LO_reserved0_SHIFT                       18
+
+/* GIO_AON :: DATA_LO :: data [17:00] */
+#define BCHP_GIO_AON_DATA_LO_data_MASK                             0x0003ffff
+#define BCHP_GIO_AON_DATA_LO_data_SHIFT                            0
+#define BCHP_GIO_AON_DATA_LO_data_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *IODIR_LO - GENERAL PURPOSE I/O DIRECTION [17:0]
+ ***************************************************************************/
+/* GIO_AON :: IODIR_LO :: reserved0 [31:18] */
+#define BCHP_GIO_AON_IODIR_LO_reserved0_MASK                       0xfffc0000
+#define BCHP_GIO_AON_IODIR_LO_reserved0_SHIFT                      18
+
+/* GIO_AON :: IODIR_LO :: iodir [17:00] */
+#define BCHP_GIO_AON_IODIR_LO_iodir_MASK                           0x0003ffff
+#define BCHP_GIO_AON_IODIR_LO_iodir_SHIFT                          0
+#define BCHP_GIO_AON_IODIR_LO_iodir_DEFAULT                        0x0003ffff
+
+/***************************************************************************
+ *EC_LO - GENERAL PURPOSE I/O EDGE CONFIGURATION [17:0]
+ ***************************************************************************/
+/* GIO_AON :: EC_LO :: reserved0 [31:18] */
+#define BCHP_GIO_AON_EC_LO_reserved0_MASK                          0xfffc0000
+#define BCHP_GIO_AON_EC_LO_reserved0_SHIFT                         18
+
+/* GIO_AON :: EC_LO :: edge_config [17:00] */
+#define BCHP_GIO_AON_EC_LO_edge_config_MASK                        0x0003ffff
+#define BCHP_GIO_AON_EC_LO_edge_config_SHIFT                       0
+#define BCHP_GIO_AON_EC_LO_edge_config_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *EI_LO - GENERAL PURPOSE I/O EDGE INSENSITIVE [17:0]
+ ***************************************************************************/
+/* GIO_AON :: EI_LO :: reserved0 [31:18] */
+#define BCHP_GIO_AON_EI_LO_reserved0_MASK                          0xfffc0000
+#define BCHP_GIO_AON_EI_LO_reserved0_SHIFT                         18
+
+/* GIO_AON :: EI_LO :: edge_insensitive [17:00] */
+#define BCHP_GIO_AON_EI_LO_edge_insensitive_MASK                   0x0003ffff
+#define BCHP_GIO_AON_EI_LO_edge_insensitive_SHIFT                  0
+#define BCHP_GIO_AON_EI_LO_edge_insensitive_DEFAULT                0x00000000
+
+/***************************************************************************
+ *MASK_LO - GENERAL PURPOSE I/O INTERRUPT MASK [17:0]
+ ***************************************************************************/
+/* GIO_AON :: MASK_LO :: reserved0 [31:18] */
+#define BCHP_GIO_AON_MASK_LO_reserved0_MASK                        0xfffc0000
+#define BCHP_GIO_AON_MASK_LO_reserved0_SHIFT                       18
+
+/* GIO_AON :: MASK_LO :: irq_mask [17:00] */
+#define BCHP_GIO_AON_MASK_LO_irq_mask_MASK                         0x0003ffff
+#define BCHP_GIO_AON_MASK_LO_irq_mask_SHIFT                        0
+#define BCHP_GIO_AON_MASK_LO_irq_mask_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *LEVEL_LO - GENERAL PURPOSE I/O INTERRUPT TYPE [17:0]
+ ***************************************************************************/
+/* GIO_AON :: LEVEL_LO :: reserved0 [31:18] */
+#define BCHP_GIO_AON_LEVEL_LO_reserved0_MASK                       0xfffc0000
+#define BCHP_GIO_AON_LEVEL_LO_reserved0_SHIFT                      18
+
+/* GIO_AON :: LEVEL_LO :: level [17:00] */
+#define BCHP_GIO_AON_LEVEL_LO_level_MASK                           0x0003ffff
+#define BCHP_GIO_AON_LEVEL_LO_level_SHIFT                          0
+#define BCHP_GIO_AON_LEVEL_LO_level_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *STAT_LO - GENERAL PURPOSE I/O INTERRUPT STATUS [17:0]
+ ***************************************************************************/
+/* GIO_AON :: STAT_LO :: reserved0 [31:18] */
+#define BCHP_GIO_AON_STAT_LO_reserved0_MASK                        0xfffc0000
+#define BCHP_GIO_AON_STAT_LO_reserved0_SHIFT                       18
+
+/* GIO_AON :: STAT_LO :: irq_status [17:00] */
+#define BCHP_GIO_AON_STAT_LO_irq_status_MASK                       0x0003ffff
+#define BCHP_GIO_AON_STAT_LO_irq_status_SHIFT                      0
+#define BCHP_GIO_AON_STAT_LO_irq_status_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *ODEN_EXT - GENERAL PURPOSE I/O OPEN DRAIN ENABLE [65:64] (SGPIO[3:0])
+ ***************************************************************************/
+/* GIO_AON :: ODEN_EXT :: reserved0 [31:04] */
+#define BCHP_GIO_AON_ODEN_EXT_reserved0_MASK                       0xfffffff0
+#define BCHP_GIO_AON_ODEN_EXT_reserved0_SHIFT                      4
+
+/* GIO_AON :: ODEN_EXT :: oden [03:00] */
+#define BCHP_GIO_AON_ODEN_EXT_oden_MASK                            0x0000000f
+#define BCHP_GIO_AON_ODEN_EXT_oden_SHIFT                           0
+#define BCHP_GIO_AON_ODEN_EXT_oden_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *DATA_EXT - GENERAL PURPOSE I/O DATA [65:64] (SGPIO[3:0])
+ ***************************************************************************/
+/* GIO_AON :: DATA_EXT :: reserved0 [31:04] */
+#define BCHP_GIO_AON_DATA_EXT_reserved0_MASK                       0xfffffff0
+#define BCHP_GIO_AON_DATA_EXT_reserved0_SHIFT                      4
+
+/* GIO_AON :: DATA_EXT :: data [03:00] */
+#define BCHP_GIO_AON_DATA_EXT_data_MASK                            0x0000000f
+#define BCHP_GIO_AON_DATA_EXT_data_SHIFT                           0
+#define BCHP_GIO_AON_DATA_EXT_data_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *IODIR_EXT - GENERAL PURPOSE I/O DIRECTION [65:64] (SGPIO[3:0])
+ ***************************************************************************/
+/* GIO_AON :: IODIR_EXT :: reserved0 [31:04] */
+#define BCHP_GIO_AON_IODIR_EXT_reserved0_MASK                      0xfffffff0
+#define BCHP_GIO_AON_IODIR_EXT_reserved0_SHIFT                     4
+
+/* GIO_AON :: IODIR_EXT :: iodir [03:00] */
+#define BCHP_GIO_AON_IODIR_EXT_iodir_MASK                          0x0000000f
+#define BCHP_GIO_AON_IODIR_EXT_iodir_SHIFT                         0
+#define BCHP_GIO_AON_IODIR_EXT_iodir_DEFAULT                       0x00000003
+
+/***************************************************************************
+ *EC_EXT - GENERAL PURPOSE I/O EDGE CONFIGURATION [65:64] (SGPIO[3:0])
+ ***************************************************************************/
+/* GIO_AON :: EC_EXT :: reserved0 [31:04] */
+#define BCHP_GIO_AON_EC_EXT_reserved0_MASK                         0xfffffff0
+#define BCHP_GIO_AON_EC_EXT_reserved0_SHIFT                        4
+
+/* GIO_AON :: EC_EXT :: edge_config [03:00] */
+#define BCHP_GIO_AON_EC_EXT_edge_config_MASK                       0x0000000f
+#define BCHP_GIO_AON_EC_EXT_edge_config_SHIFT                      0
+#define BCHP_GIO_AON_EC_EXT_edge_config_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *EI_EXT - GENERAL PURPOSE I/O EDGE INSENSITIVE [65:64] (SGPIO[3:0])
+ ***************************************************************************/
+/* GIO_AON :: EI_EXT :: reserved0 [31:04] */
+#define BCHP_GIO_AON_EI_EXT_reserved0_MASK                         0xfffffff0
+#define BCHP_GIO_AON_EI_EXT_reserved0_SHIFT                        4
+
+/* GIO_AON :: EI_EXT :: edge_insensitive [03:00] */
+#define BCHP_GIO_AON_EI_EXT_edge_insensitive_MASK                  0x0000000f
+#define BCHP_GIO_AON_EI_EXT_edge_insensitive_SHIFT                 0
+#define BCHP_GIO_AON_EI_EXT_edge_insensitive_DEFAULT               0x00000000
+
+/***************************************************************************
+ *MASK_EXT - GENERAL PURPOSE I/O INTERRUPT MASK [65:64] (SGPIO[3:0])
+ ***************************************************************************/
+/* GIO_AON :: MASK_EXT :: reserved0 [31:04] */
+#define BCHP_GIO_AON_MASK_EXT_reserved0_MASK                       0xfffffff0
+#define BCHP_GIO_AON_MASK_EXT_reserved0_SHIFT                      4
+
+/* GIO_AON :: MASK_EXT :: irq_mask [03:00] */
+#define BCHP_GIO_AON_MASK_EXT_irq_mask_MASK                        0x0000000f
+#define BCHP_GIO_AON_MASK_EXT_irq_mask_SHIFT                       0
+#define BCHP_GIO_AON_MASK_EXT_irq_mask_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *LEVEL_EXT - GENERAL PURPOSE I/O INTERRUPT TYPE [65:64] (SGPIO[3:0])
+ ***************************************************************************/
+/* GIO_AON :: LEVEL_EXT :: reserved0 [31:04] */
+#define BCHP_GIO_AON_LEVEL_EXT_reserved0_MASK                      0xfffffff0
+#define BCHP_GIO_AON_LEVEL_EXT_reserved0_SHIFT                     4
+
+/* GIO_AON :: LEVEL_EXT :: level [03:00] */
+#define BCHP_GIO_AON_LEVEL_EXT_level_MASK                          0x0000000f
+#define BCHP_GIO_AON_LEVEL_EXT_level_SHIFT                         0
+#define BCHP_GIO_AON_LEVEL_EXT_level_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *STAT_EXT - GENERAL PURPOSE I/O INTERRUPT STATUS [65:64] (SGPIO[3:0])
+ ***************************************************************************/
+/* GIO_AON :: STAT_EXT :: reserved0 [31:04] */
+#define BCHP_GIO_AON_STAT_EXT_reserved0_MASK                       0xfffffff0
+#define BCHP_GIO_AON_STAT_EXT_reserved0_SHIFT                      4
+
+/* GIO_AON :: STAT_EXT :: irq_status [03:00] */
+#define BCHP_GIO_AON_STAT_EXT_irq_status_MASK                      0x0000000f
+#define BCHP_GIO_AON_STAT_EXT_irq_status_SHIFT                     0
+#define BCHP_GIO_AON_STAT_EXT_irq_status_DEFAULT                   0x00000000
+
+#endif /* #ifndef BCHP_GIO_AON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_hif_cpu_intr1.h b/include/linux/brcmstb/7435b0/bchp_hif_cpu_intr1.h
new file mode 100644
index 0000000..d1e99da
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_hif_cpu_intr1.h
@@ -0,0 +1,2128 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:10:03 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_INTR1_H__
+#define BCHP_HIF_CPU_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_INTR1 - HIF CPU0 Thread Processor 0 (TP0) Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS        0x0041b500 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS        0x0041b504 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS        0x0041b508 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_STATUS        0x0041b50c /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS   0x0041b510 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS   0x0041b514 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS   0x0041b518 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_STATUS   0x0041b51c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET      0x0041b520 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET      0x0041b524 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET      0x0041b528 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_SET      0x0041b52c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR    0x0041b530 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR    0x0041b534 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR    0x0041b538 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_CLEAR    0x0041b53c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: MEMC1_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MEMC1_CPU_INTR_MASK      0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MEMC1_CPU_INTR_SHIFT     31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MEMC1_CPU_INTR_DEFAULT   0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: MEMC0_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MEMC0_CPU_INTR_MASK      0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MEMC0_CPU_INTR_SHIFT     30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MEMC0_CPU_INTR_DEFAULT   0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: IPI3_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI3_CPU_INTR_MASK       0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI3_CPU_INTR_SHIFT      29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI3_CPU_INTR_DEFAULT    0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: IPI2_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI2_CPU_INTR_MASK       0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI2_CPU_INTR_SHIFT      28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI2_CPU_INTR_DEFAULT    0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: IPI1_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI1_CPU_INTR_MASK       0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI1_CPU_INTR_SHIFT      27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI1_CPU_INTR_DEFAULT    0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: IPI0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI0_CPU_INTR_MASK       0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI0_CPU_INTR_SHIFT      26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_IPI0_CPU_INTR_DEFAULT    0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK    0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT   25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK        0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT       24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HDMI_RX_0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_RX_0_CPU_INTR_MASK  0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_RX_0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GFX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_MASK        0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_SHIFT       21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_1_B_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_MASK  0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_1_A_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_MASK  0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK  0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK  0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: DVP_HR_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_DVP_HR_CPU_INTR_MASK     0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_DVP_HR_CPU_INTR_SHIFT    10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_DVP_HR_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK     0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT    9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNM_1_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_1_CPU_INTR_MASK     0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_1_CPU_INTR_SHIFT    8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_1_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK     0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT    7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK     0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT    6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK     0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT    5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK     0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT    4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK     0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT    3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK        0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT       2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: AVD1_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AVD1_0_CPU_INTR_MASK     0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AVD1_0_CPU_INTR_SHIFT    1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AVD1_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK        0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT       0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK     0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT    31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MC_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MC_CPU_INTR_MASK     0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MC_CPU_INTR_SHIFT    30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MC_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK   0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT  28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK    0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT   26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_MASK    0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_SHIFT   24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UHF_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_MASK        0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_SHIFT       23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK     0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT    22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK    0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT   21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK        0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT       20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SVD0_0_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_MASK     0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_SHIFT    19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SID0_0_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SID0_0_CPU_INTR_MASK     0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SID0_0_CPU_INTR_SHIFT    17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SID0_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDIO1_0_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDIO1_0_CPU_INTR_MASK    0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDIO1_0_CPU_INTR_SHIFT   16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDIO1_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDIO0_0_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDIO0_0_CPU_INTR_MASK    0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDIO0_0_CPU_INTR_SHIFT   15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SATA_GRB_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_MASK   0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_SHIFT  14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SATA_AHCI_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_MASK  0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA1_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA1_FW_CPU_INTR_MASK  0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA1_FW_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA1_FW_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA1_CPU_INTR_MASK     0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA1_CPU_INTR_SHIFT    11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA1_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK   0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT  10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK      0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT     9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT   0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: PCIE_NMI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_NMI_CPU_INTR_MASK   0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_NMI_CPU_INTR_SHIFT  8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_NMI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: PCIE_INTR_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTR_CPU_INTR_MASK  0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTR_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: PCIE_INTD_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTD_CPU_INTR_MASK  0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTD_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTD_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: PCIE_INTC_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTC_CPU_INTR_MASK  0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTC_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: PCIE_INTB_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTB_CPU_INTR_MASK  0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTB_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTB_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: PCIE_INTA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTA_CPU_INTR_MASK  0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_INTA_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: PCIE_ERR_ATTN_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_ERR_ATTN_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_ERR_ATTN_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_PCIE_ERR_ATTN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: MOCA_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_MASK       0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_SHIFT      0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_DEFAULT    0x00000000
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK    0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT   29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK   0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT  28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK    0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT   26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK     0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT    25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: WEBHIF_TIMER_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_WEBHIF_TIMER_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_WEBHIF_TIMER_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_WEBHIF_TIMER_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: WEBHIF_STB_IPI1_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_WEBHIF_STB_IPI1_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_WEBHIF_STB_IPI1_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_WEBHIF_STB_IPI1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: WEBHIF_STB_IPI0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_WEBHIF_STB_IPI0_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_WEBHIF_STB_IPI0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_WEBHIF_STB_IPI0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: WEBHIF_IPI1_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_WEBHIF_IPI1_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_WEBHIF_IPI1_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_WEBHIF_IPI1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: WEBHIF_IPI0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_WEBHIF_IPI0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_WEBHIF_IPI0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_WEBHIF_IPI0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: WEBHIF_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_WEBHIF_CPU_INTR_MASK     0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_WEBHIF_CPU_INTR_SHIFT    19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_WEBHIF_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: VICE1_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VICE1_0_CPU_INTR_MASK    0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VICE1_0_CPU_INTR_SHIFT   18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VICE1_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: VICE0_0_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VICE0_0_CPU_INTR_MASK    0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VICE0_0_CPU_INTR_SHIFT   17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VICE0_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK        0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT       16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: V3D_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_V3D_CPU_INTR_MASK        0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_V3D_CPU_INTR_SHIFT       15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_V3D_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_1_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_0_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_BRIDGE_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_BRIDGE_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART2_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_MASK  0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART1_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_MASK  0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_TMR_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_TMR_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_TMR_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_SPI_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_SPI_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_SPI_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_W3_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W3_STATUS :: reserved0 [31:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_STATUS_reserved0_MASK           0xfffffff0
+#define BCHP_HIF_CPU_INTR1_INTR_W3_STATUS_reserved0_SHIFT          4
+
+/* HIF_CPU_INTR1 :: INTR_W3_STATUS :: SCPU_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_STATUS_SCPU_CPU_INTR_MASK       0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W3_STATUS_SCPU_CPU_INTR_SHIFT      3
+#define BCHP_HIF_CPU_INTR1_INTR_W3_STATUS_SCPU_CPU_INTR_DEFAULT    0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W3_STATUS :: M2MC1_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_STATUS_M2MC1_CPU_INTR_MASK      0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W3_STATUS_M2MC1_CPU_INTR_SHIFT     2
+#define BCHP_HIF_CPU_INTR1_INTR_W3_STATUS_M2MC1_CPU_INTR_DEFAULT   0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W3_STATUS :: ZCPU_ACCESS_VIOL1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_STATUS_ZCPU_ACCESS_VIOL1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W3_STATUS_ZCPU_ACCESS_VIOL1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W3_STATUS_ZCPU_ACCESS_VIOL1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W3_STATUS :: ZCPU_ACCESS_VIOL0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_STATUS_ZCPU_ACCESS_VIOL0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W3_STATUS_ZCPU_ACCESS_VIOL0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W3_STATUS_ZCPU_ACCESS_VIOL0_CPU_INTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: MEMC1_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MEMC1_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MEMC1_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MEMC1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: MEMC0_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MEMC0_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MEMC0_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MEMC0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: IPI3_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI3_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI3_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI3_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: IPI2_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI2_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI2_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: IPI1_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI1_CPU_INTR_MASK  0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI1_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: IPI0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI0_CPU_INTR_MASK  0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI0_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK   0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT  24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_RX_0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_RX_0_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_RX_0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GFX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_MASK   0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_SHIFT  21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_B_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_A_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: DVP_HR_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_DVP_HR_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_DVP_HR_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_DVP_HR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_1_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_1_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_1_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: AVD1_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AVD1_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AVD1_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AVD1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MC_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MC_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MC_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UHF_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_MASK   0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_SHIFT  23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK   0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT  20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SVD0_0_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SID0_0_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SID0_0_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SID0_0_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SID0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDIO1_0_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDIO1_0_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDIO1_0_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDIO1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDIO0_0_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SATA_GRB_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SATA_AHCI_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA1_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA1_FW_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA1_FW_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA1_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_NMI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_NMI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_NMI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_NMI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTR_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTR_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTR_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTD_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTD_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTD_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTD_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTC_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTC_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTC_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTB_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTB_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTB_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTA_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_INTA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_ERR_ATTN_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_ERR_ATTN_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_ERR_ATTN_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_PCIE_ERR_ATTN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: MOCA_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: WEBHIF_TIMER_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_WEBHIF_TIMER_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_WEBHIF_TIMER_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_WEBHIF_TIMER_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: WEBHIF_STB_IPI1_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_WEBHIF_STB_IPI1_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_WEBHIF_STB_IPI1_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_WEBHIF_STB_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: WEBHIF_STB_IPI0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_WEBHIF_STB_IPI0_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_WEBHIF_STB_IPI0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_WEBHIF_STB_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: WEBHIF_IPI1_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_WEBHIF_IPI1_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_WEBHIF_IPI1_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_WEBHIF_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: WEBHIF_IPI0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_WEBHIF_IPI0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_WEBHIF_IPI0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_WEBHIF_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: WEBHIF_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_WEBHIF_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_WEBHIF_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_WEBHIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: VICE1_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VICE1_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VICE1_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VICE1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: VICE0_0_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VICE0_0_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VICE0_0_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VICE0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK   0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT  16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: V3D_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_V3D_CPU_INTR_MASK   0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_V3D_CPU_INTR_SHIFT  15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_V3D_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_1_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_0_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_BRIDGE_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_BRIDGE_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART2_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART1_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_TMR_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_SPI_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W3_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W3_MASK_STATUS :: reserved0 [31:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_STATUS_reserved0_MASK      0xfffffff0
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_STATUS_reserved0_SHIFT     4
+
+/* HIF_CPU_INTR1 :: INTR_W3_MASK_STATUS :: SCPU_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_STATUS_SCPU_CPU_INTR_MASK  0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_STATUS_SCPU_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_STATUS_SCPU_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W3_MASK_STATUS :: M2MC1_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_STATUS_M2MC1_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_STATUS_M2MC1_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_STATUS_M2MC1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W3_MASK_STATUS :: ZCPU_ACCESS_VIOL1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_STATUS_ZCPU_ACCESS_VIOL1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_STATUS_ZCPU_ACCESS_VIOL1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_STATUS_ZCPU_ACCESS_VIOL1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W3_MASK_STATUS :: ZCPU_ACCESS_VIOL0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_STATUS_ZCPU_ACCESS_VIOL0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_STATUS_ZCPU_ACCESS_VIOL0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_STATUS_ZCPU_ACCESS_VIOL0_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: MEMC1_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MEMC1_CPU_INTR_MASK    0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MEMC1_CPU_INTR_SHIFT   31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MEMC1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: MEMC0_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MEMC0_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MEMC0_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MEMC0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: IPI3_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI3_CPU_INTR_MASK     0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI3_CPU_INTR_SHIFT    29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI3_CPU_INTR_DEFAULT  0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: IPI2_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI2_CPU_INTR_MASK     0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI2_CPU_INTR_SHIFT    28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI2_CPU_INTR_DEFAULT  0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: IPI1_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI1_CPU_INTR_MASK     0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI1_CPU_INTR_SHIFT    27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI1_CPU_INTR_DEFAULT  0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: IPI0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI0_CPU_INTR_MASK     0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI0_CPU_INTR_SHIFT    26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_IPI0_CPU_INTR_DEFAULT  0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK  0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK      0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT     24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK  0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HDMI_RX_0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_RX_0_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_RX_0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GFX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_MASK      0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_SHIFT     21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_1_B_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_1_A_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: DVP_HR_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_DVP_HR_CPU_INTR_MASK   0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_DVP_HR_CPU_INTR_SHIFT  10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_DVP_HR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK   0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT  9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNM_1_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_1_CPU_INTR_MASK   0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_1_CPU_INTR_SHIFT  8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK      0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT     2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: AVD1_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AVD1_0_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AVD1_0_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AVD1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK      0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT     0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK   0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT  31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MC_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MC_CPU_INTR_MASK   0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MC_CPU_INTR_SHIFT  30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK  0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_MASK  0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UHF_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_MASK      0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_SHIFT     23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK   0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT  22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK  0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK      0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT     20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SVD0_0_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SID0_0_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SID0_0_CPU_INTR_MASK   0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SID0_0_CPU_INTR_SHIFT  17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SID0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDIO1_0_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDIO1_0_CPU_INTR_MASK  0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDIO1_0_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDIO1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDIO0_0_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDIO0_0_CPU_INTR_MASK  0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SATA_GRB_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SATA_AHCI_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA1_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA1_FW_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA1_FW_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA1_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA1_CPU_INTR_MASK   0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA1_CPU_INTR_SHIFT  11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK    0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT   9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: PCIE_NMI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_NMI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_NMI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_NMI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTR_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTR_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTR_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTD_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTD_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTD_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTD_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTC_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTC_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTC_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTB_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTB_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTB_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTA_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_INTA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: PCIE_ERR_ATTN_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_ERR_ATTN_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_ERR_ATTN_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_PCIE_ERR_ATTN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: MOCA_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_MASK     0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_SHIFT    0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_DEFAULT  0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK  0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK   0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT  25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: WEBHIF_TIMER_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_WEBHIF_TIMER_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_WEBHIF_TIMER_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_WEBHIF_TIMER_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: WEBHIF_STB_IPI1_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_WEBHIF_STB_IPI1_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_WEBHIF_STB_IPI1_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_WEBHIF_STB_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: WEBHIF_STB_IPI0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_WEBHIF_STB_IPI0_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_WEBHIF_STB_IPI0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_WEBHIF_STB_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: WEBHIF_IPI1_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_WEBHIF_IPI1_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_WEBHIF_IPI1_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_WEBHIF_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: WEBHIF_IPI0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_WEBHIF_IPI0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_WEBHIF_IPI0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_WEBHIF_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: WEBHIF_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_WEBHIF_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_WEBHIF_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_WEBHIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: VICE1_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VICE1_0_CPU_INTR_MASK  0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VICE1_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VICE1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: VICE0_0_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VICE0_0_CPU_INTR_MASK  0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VICE0_0_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VICE0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK      0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT     16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: V3D_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_V3D_CPU_INTR_MASK      0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_V3D_CPU_INTR_SHIFT     15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_V3D_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_1_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_0_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_BRIDGE_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_BRIDGE_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART2_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART1_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_TMR_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_TMR_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_SPI_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_SPI_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W3_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W3_MASK_SET :: reserved0 [31:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_SET_reserved0_MASK         0xfffffff0
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_SET_reserved0_SHIFT        4
+
+/* HIF_CPU_INTR1 :: INTR_W3_MASK_SET :: SCPU_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_SET_SCPU_CPU_INTR_MASK     0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_SET_SCPU_CPU_INTR_SHIFT    3
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_SET_SCPU_CPU_INTR_DEFAULT  0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W3_MASK_SET :: M2MC1_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_SET_M2MC1_CPU_INTR_MASK    0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_SET_M2MC1_CPU_INTR_SHIFT   2
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_SET_M2MC1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W3_MASK_SET :: ZCPU_ACCESS_VIOL1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_SET_ZCPU_ACCESS_VIOL1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_SET_ZCPU_ACCESS_VIOL1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_SET_ZCPU_ACCESS_VIOL1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W3_MASK_SET :: ZCPU_ACCESS_VIOL0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_SET_ZCPU_ACCESS_VIOL0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_SET_ZCPU_ACCESS_VIOL0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_SET_ZCPU_ACCESS_VIOL0_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: MEMC1_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MEMC1_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MEMC1_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MEMC1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: MEMC0_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MEMC0_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MEMC0_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MEMC0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: IPI3_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI3_CPU_INTR_MASK   0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI3_CPU_INTR_SHIFT  29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI3_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: IPI2_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI2_CPU_INTR_MASK   0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI2_CPU_INTR_SHIFT  28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: IPI1_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI1_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI1_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: IPI0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI0_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI0_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK    0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT   24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_RX_0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_RX_0_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_RX_0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GFX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_MASK    0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_SHIFT   21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_B_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_A_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: DVP_HR_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_DVP_HR_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_DVP_HR_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_DVP_HR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_1_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_1_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_1_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK    0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT   2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: AVD1_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AVD1_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AVD1_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AVD1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MC_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MC_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MC_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UHF_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK    0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT   20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SVD0_0_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SID0_0_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SID0_0_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SID0_0_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SID0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDIO1_0_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDIO1_0_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDIO1_0_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDIO1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDIO0_0_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_GRB_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_AHCI_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA1_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA1_FW_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA1_FW_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA1_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK  0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_NMI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_NMI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_NMI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_NMI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTR_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTR_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTR_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTD_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTD_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTD_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTD_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTC_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTC_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTC_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTB_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTB_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTB_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTA_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_ERR_ATTN_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_ERR_ATTN_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_ERR_ATTN_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_PCIE_ERR_ATTN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: MOCA_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: WEBHIF_TIMER_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_TIMER_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_TIMER_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_TIMER_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: WEBHIF_STB_IPI1_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_STB_IPI1_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_STB_IPI1_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_STB_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: WEBHIF_STB_IPI0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_STB_IPI0_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_STB_IPI0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_STB_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: WEBHIF_IPI1_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_IPI1_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_IPI1_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: WEBHIF_IPI0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_IPI0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_IPI0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: WEBHIF_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: VICE1_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VICE1_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VICE1_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VICE1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: VICE0_0_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VICE0_0_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VICE0_0_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VICE0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK    0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT   16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: V3D_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_V3D_CPU_INTR_MASK    0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_V3D_CPU_INTR_SHIFT   15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_V3D_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_1_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_0_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_BRIDGE_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_BRIDGE_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART2_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART1_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_TMR_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_SPI_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W3_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W3_MASK_CLEAR :: reserved0 [31:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_CLEAR_reserved0_MASK       0xfffffff0
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_CLEAR_reserved0_SHIFT      4
+
+/* HIF_CPU_INTR1 :: INTR_W3_MASK_CLEAR :: SCPU_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_CLEAR_SCPU_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_CLEAR_SCPU_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_CLEAR_SCPU_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W3_MASK_CLEAR :: M2MC1_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_CLEAR_M2MC1_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_CLEAR_M2MC1_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_CLEAR_M2MC1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W3_MASK_CLEAR :: ZCPU_ACCESS_VIOL1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_CLEAR_ZCPU_ACCESS_VIOL1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_CLEAR_ZCPU_ACCESS_VIOL1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_CLEAR_ZCPU_ACCESS_VIOL1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W3_MASK_CLEAR :: ZCPU_ACCESS_VIOL0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_CLEAR_ZCPU_ACCESS_VIOL0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_CLEAR_ZCPU_ACCESS_VIOL0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W3_MASK_CLEAR_ZCPU_ACCESS_VIOL0_CPU_INTR_DEFAULT 0x00000001
+
+#endif /* #ifndef BCHP_HIF_CPU_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_hif_cpu_tp1_intr1.h b/include/linux/brcmstb/7435b0/bchp_hif_cpu_tp1_intr1.h
new file mode 100644
index 0000000..32d5052
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_hif_cpu_tp1_intr1.h
@@ -0,0 +1,2128 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:10:02 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_TP1_INTR1_H__
+#define BCHP_HIF_CPU_TP1_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_TP1_INTR1 - HIF CPU0 Thread Processor 1 (TP1) Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS    0x0041b600 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS    0x0041b604 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS    0x0041b608 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS    0x0041b60c /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS 0x0041b610 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS 0x0041b614 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS 0x0041b618 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS 0x0041b61c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET  0x0041b620 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET  0x0041b624 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET  0x0041b628 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET  0x0041b62c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR 0x0041b630 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR 0x0041b634 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR 0x0041b638 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR 0x0041b63c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: MEMC1_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC1_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC1_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: MEMC0_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC0_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC0_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: IPI3_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI3_CPU_INTR_MASK   0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI3_CPU_INTR_SHIFT  29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI3_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: IPI2_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI2_CPU_INTR_MASK   0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI2_CPU_INTR_SHIFT  28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI2_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: IPI1_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI1_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI1_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: IPI0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI0_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI0_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK    0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT   24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HDMI_RX_0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_RX_0_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_RX_0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GFX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_MASK    0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_SHIFT   21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_1_B_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_1_A_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: DVP_HR_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_DVP_HR_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_DVP_HR_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_DVP_HR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNM_1_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_1_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_1_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK    0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT   2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: AVD1_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AVD1_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AVD1_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AVD1_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MC_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MC_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MC_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_AUX_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UHF_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK    0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT   20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SVD0_0_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SID0_0_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SID0_0_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SID0_0_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SID0_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDIO1_0_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO1_0_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO1_0_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO1_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDIO0_0_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO0_0_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO0_0_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SATA_GRB_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SATA_AHCI_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: RAAGA1_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA1_FW_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA1_FW_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA1_FW_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: RAAGA1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK  0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCIE_NMI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_NMI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_NMI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_NMI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCIE_INTR_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTR_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTR_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCIE_INTD_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTD_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTD_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTD_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCIE_INTC_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTC_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTC_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCIE_INTB_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTB_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTB_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTB_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCIE_INTA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTA_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTA_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCIE_ERR_ATTN_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_ERR_ATTN_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_ERR_ATTN_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_ERR_ATTN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: MOCA_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: WEBHIF_TIMER_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_TIMER_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_TIMER_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_TIMER_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: WEBHIF_STB_IPI1_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_STB_IPI1_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_STB_IPI1_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_STB_IPI1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: WEBHIF_STB_IPI0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_STB_IPI0_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_STB_IPI0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_STB_IPI0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: WEBHIF_IPI1_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_IPI1_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_IPI1_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_IPI1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: WEBHIF_IPI0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_IPI0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_IPI0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_IPI0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: WEBHIF_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: VICE1_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VICE1_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VICE1_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VICE1_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: VICE0_0_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VICE0_0_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VICE0_0_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VICE0_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK    0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT   16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: V3D_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_V3D_CPU_INTR_MASK    0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_V3D_CPU_INTR_SHIFT   15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_V3D_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_1_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_0_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_BRIDGE_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_BRIDGE_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART2_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART1_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_TMR_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_TMR_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_TMR_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_SPI_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_SPI_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_SPI_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_W3_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W3_STATUS :: reserved0 [31:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_reserved0_MASK       0xfffffff0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_reserved0_SHIFT      4
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W3_STATUS :: SCPU_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_SCPU_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_SCPU_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_SCPU_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W3_STATUS :: M2MC1_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_M2MC1_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_M2MC1_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_M2MC1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W3_STATUS :: ZCPU_ACCESS_VIOL1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_ZCPU_ACCESS_VIOL1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_ZCPU_ACCESS_VIOL1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_ZCPU_ACCESS_VIOL1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W3_STATUS :: ZCPU_ACCESS_VIOL0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_ZCPU_ACCESS_VIOL0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_ZCPU_ACCESS_VIOL0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_ZCPU_ACCESS_VIOL0_CPU_INTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: MEMC1_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC1_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC1_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: MEMC0_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC0_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC0_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: IPI3_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI3_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI3_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI3_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: IPI2_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI2_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI2_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: IPI1_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI1_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI1_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: IPI0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI0_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI0_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_RX_0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_RX_0_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_RX_0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GFX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_B_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_A_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: DVP_HR_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_DVP_HR_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_DVP_HR_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_DVP_HR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_1_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_1_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_1_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: AVD1_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AVD1_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AVD1_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AVD1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MC_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MC_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MC_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UHF_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SVD0_0_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SID0_0_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SID0_0_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SID0_0_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SID0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDIO1_0_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO1_0_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO1_0_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDIO0_0_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SATA_GRB_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SATA_AHCI_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA1_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA1_FW_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA1_FW_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA1_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_NMI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_NMI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_NMI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_NMI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTR_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTR_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTR_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTD_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTD_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTD_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTD_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTC_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTC_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTC_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTB_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTB_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTB_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTA_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_ERR_ATTN_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_ERR_ATTN_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_ERR_ATTN_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_ERR_ATTN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: MOCA_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: WEBHIF_TIMER_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_TIMER_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_TIMER_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_TIMER_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: WEBHIF_STB_IPI1_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_STB_IPI1_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_STB_IPI1_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_STB_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: WEBHIF_STB_IPI0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_STB_IPI0_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_STB_IPI0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_STB_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: WEBHIF_IPI1_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_IPI1_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_IPI1_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: WEBHIF_IPI0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_IPI0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_IPI0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: WEBHIF_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: VICE1_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VICE1_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VICE1_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VICE1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: VICE0_0_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VICE0_0_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VICE0_0_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VICE0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: V3D_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_V3D_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_V3D_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_V3D_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_1_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_0_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_BRIDGE_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_BRIDGE_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART2_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART1_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_TMR_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_SPI_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W3_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_STATUS :: reserved0 [31:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_reserved0_MASK  0xfffffff0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_reserved0_SHIFT 4
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_STATUS :: SCPU_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_SCPU_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_SCPU_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_SCPU_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_STATUS :: M2MC1_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_M2MC1_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_M2MC1_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_M2MC1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_STATUS :: ZCPU_ACCESS_VIOL1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_ZCPU_ACCESS_VIOL1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_ZCPU_ACCESS_VIOL1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_ZCPU_ACCESS_VIOL1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_STATUS :: ZCPU_ACCESS_VIOL0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_ZCPU_ACCESS_VIOL0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_ZCPU_ACCESS_VIOL0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_ZCPU_ACCESS_VIOL0_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: MEMC1_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC1_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC1_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: MEMC0_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC0_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC0_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: IPI3_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI3_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI3_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI3_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: IPI2_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI2_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI2_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: IPI1_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI1_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI1_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: IPI0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI0_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI0_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK  0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HDMI_RX_0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_RX_0_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_RX_0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GFX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_MASK  0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_1_B_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_1_A_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: DVP_HR_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_DVP_HR_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_DVP_HR_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_DVP_HR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNM_1_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_1_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_1_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: AVD1_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AVD1_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AVD1_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AVD1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MC_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MC_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MC_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UHF_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_MASK  0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK  0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SVD0_0_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SID0_0_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SID0_0_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SID0_0_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SID0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDIO1_0_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO1_0_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO1_0_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDIO0_0_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO0_0_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SATA_GRB_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SATA_AHCI_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: RAAGA1_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA1_FW_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA1_FW_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA1_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: RAAGA1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCIE_NMI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_NMI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_NMI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_NMI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTR_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTR_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTR_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTD_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTD_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTD_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTD_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTC_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTC_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTC_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTB_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTB_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTB_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTA_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCIE_ERR_ATTN_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_ERR_ATTN_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_ERR_ATTN_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_ERR_ATTN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: MOCA_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: WEBHIF_TIMER_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_TIMER_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_TIMER_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_TIMER_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: WEBHIF_STB_IPI1_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_STB_IPI1_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_STB_IPI1_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_STB_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: WEBHIF_STB_IPI0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_STB_IPI0_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_STB_IPI0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_STB_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: WEBHIF_IPI1_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_IPI1_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_IPI1_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: WEBHIF_IPI0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_IPI0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_IPI0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: WEBHIF_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: VICE1_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VICE1_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VICE1_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VICE1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: VICE0_0_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VICE0_0_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VICE0_0_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VICE0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK  0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: V3D_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_V3D_CPU_INTR_MASK  0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_V3D_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_V3D_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_1_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_0_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_BRIDGE_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_BRIDGE_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART2_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART1_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_TMR_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_TMR_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_SPI_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_SPI_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W3_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_SET :: reserved0 [31:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_reserved0_MASK     0xfffffff0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_reserved0_SHIFT    4
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_SET :: SCPU_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_SCPU_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_SCPU_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_SCPU_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_SET :: M2MC1_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_M2MC1_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_M2MC1_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_M2MC1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_SET :: ZCPU_ACCESS_VIOL1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_ZCPU_ACCESS_VIOL1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_ZCPU_ACCESS_VIOL1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_ZCPU_ACCESS_VIOL1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_SET :: ZCPU_ACCESS_VIOL0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_ZCPU_ACCESS_VIOL0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_ZCPU_ACCESS_VIOL0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_ZCPU_ACCESS_VIOL0_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: MEMC1_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC1_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC1_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: MEMC0_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC0_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC0_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: IPI3_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI3_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI3_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI3_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: IPI2_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI2_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI2_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: IPI1_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI1_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI1_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: IPI0_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI0_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI0_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_RX_0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_RX_0_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_RX_0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GFX_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_B_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_A_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: DVP_HR_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_DVP_HR_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_DVP_HR_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_DVP_HR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_1_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_1_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_1_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: AVD1_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AVD1_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AVD1_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AVD1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MC_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MC_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MC_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UHF_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SVD0_0_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SID0_0_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SID0_0_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SID0_0_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SID0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDIO1_0_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO1_0_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO1_0_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDIO0_0_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_GRB_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_AHCI_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA1_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA1_FW_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA1_FW_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA1_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_NMI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_NMI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_NMI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_NMI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTR_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTR_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTR_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTD_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTD_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTD_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTD_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTC_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTC_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTC_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTB_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTB_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTB_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTA_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_ERR_ATTN_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_ERR_ATTN_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_ERR_ATTN_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_ERR_ATTN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: MOCA_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: WEBHIF_TIMER_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_TIMER_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_TIMER_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_TIMER_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: WEBHIF_STB_IPI1_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_STB_IPI1_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_STB_IPI1_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_STB_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: WEBHIF_STB_IPI0_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_STB_IPI0_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_STB_IPI0_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_STB_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: WEBHIF_IPI1_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_IPI1_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_IPI1_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: WEBHIF_IPI0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_IPI0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_IPI0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: WEBHIF_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: VICE1_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VICE1_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VICE1_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VICE1_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: VICE0_0_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VICE0_0_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VICE0_0_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VICE0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: V3D_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_V3D_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_V3D_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_V3D_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_1_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_0_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_BRIDGE_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_BRIDGE_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART2_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART1_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_TMR_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_SPI_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W3_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_CLEAR :: reserved0 [31:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_reserved0_MASK   0xfffffff0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_reserved0_SHIFT  4
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_CLEAR :: SCPU_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_SCPU_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_SCPU_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_SCPU_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_CLEAR :: M2MC1_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_M2MC1_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_M2MC1_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_M2MC1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_CLEAR :: ZCPU_ACCESS_VIOL1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_ZCPU_ACCESS_VIOL1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_ZCPU_ACCESS_VIOL1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_ZCPU_ACCESS_VIOL1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_CLEAR :: ZCPU_ACCESS_VIOL0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_ZCPU_ACCESS_VIOL0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_ZCPU_ACCESS_VIOL0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_ZCPU_ACCESS_VIOL0_CPU_INTR_DEFAULT 0x00000001
+
+#endif /* #ifndef BCHP_HIF_CPU_TP1_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_hif_intr2.h b/include/linux/brcmstb/7435b0/bchp_hif_intr2.h
new file mode 100644
index 0000000..30ec343
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_hif_intr2.h
@@ -0,0 +1,1692 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:10:03 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_INTR2_H__
+#define BCHP_HIF_INTR2_H__
+
+/***************************************************************************
+ *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_INTR2_CPU_STATUS                0x0041b000 /* CPU interrupt Status Register */
+#define BCHP_HIF_INTR2_CPU_SET                   0x0041b004 /* CPU interrupt Set Register */
+#define BCHP_HIF_INTR2_CPU_CLEAR                 0x0041b008 /* CPU interrupt Clear Register */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS           0x0041b00c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_CPU_MASK_SET              0x0041b010 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR            0x0041b014 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_INTR2_PCI_STATUS                0x0041b018 /* PCI interrupt Status Register */
+#define BCHP_HIF_INTR2_PCI_SET                   0x0041b01c /* PCI interrupt Set Register */
+#define BCHP_HIF_INTR2_PCI_CLEAR                 0x0041b020 /* PCI interrupt Clear Register */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS           0x0041b024 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_PCI_MASK_SET              0x0041b028 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR            0x0041b02c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKDOWN_INTR_MASK          0x80000000
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKDOWN_INTR_SHIFT         31
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKDOWN_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKUP_INTR_MASK            0x40000000
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKUP_INTR_SHIFT           30
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKUP_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EDU_DONE_INTR_MASK               0x20000000
+#define BCHP_HIF_INTR2_CPU_STATUS_EDU_DONE_INTR_SHIFT              29
+#define BCHP_HIF_INTR2_CPU_STATUS_EDU_DONE_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EDU_ERR_INTR_MASK                0x10000000
+#define BCHP_HIF_INTR2_CPU_STATUS_EDU_ERR_INTR_SHIFT               28
+#define BCHP_HIF_INTR2_CPU_STATUS_EDU_ERR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_MASK          0x00080000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_SHIFT         19
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_MASK          0x00008000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_SHIFT         15
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK                   0x00004000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT                  14
+
+/* HIF_INTR2 :: CPU_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RG_BRIDGE_INTR_MASK         0x00002000
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT        13
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RG_BRIDGE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR1_BRIDGE_INTR_MASK        0x00001000
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR1_BRIDGE_INTR_SHIFT       12
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR1_BRIDGE_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved1 [11:06] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK                   0x00000fc0
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT                  6
+
+/* HIF_INTR2 :: CPU_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_MASK          0x00000020
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_SHIFT         5
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_MASK         0x00000010
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_SHIFT        4
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_CPU_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK      0x00000008
+#define BCHP_HIF_INTR2_CPU_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT     3
+#define BCHP_HIF_INTR2_CPU_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH1_INST1_RD_INTR [02:02] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH1_INST1_RD_INTR_MASK         0x00000004
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH1_INST1_RD_INTR_SHIFT        2
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH1_INST1_RD_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH1_INST0_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH1_INST0_RD_INTR_MASK         0x00000002
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH1_INST0_RD_INTR_SHIFT        1
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH1_INST0_RD_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_MASK        0x00000001
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT       0
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_SET :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKDOWN_INTR_MASK             0x80000000
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKDOWN_INTR_SHIFT            31
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKDOWN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKUP_INTR_MASK               0x40000000
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKUP_INTR_SHIFT              30
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKUP_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_CPU_SET_EDU_DONE_INTR_MASK                  0x20000000
+#define BCHP_HIF_INTR2_CPU_SET_EDU_DONE_INTR_SHIFT                 29
+#define BCHP_HIF_INTR2_CPU_SET_EDU_DONE_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_CPU_SET_EDU_ERR_INTR_MASK                   0x10000000
+#define BCHP_HIF_INTR2_CPU_SET_EDU_ERR_INTR_SHIFT                  28
+#define BCHP_HIF_INTR2_CPU_SET_EDU_ERR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_MASK             0x00080000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_SHIFT            19
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_MASK             0x00008000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_SHIFT            15
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK                      0x00004000
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT                     14
+
+/* HIF_INTR2 :: CPU_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_RG_BRIDGE_INTR_MASK            0x00002000
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_RG_BRIDGE_INTR_SHIFT           13
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_RG_BRIDGE_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR1_BRIDGE_INTR_MASK           0x00001000
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR1_BRIDGE_INTR_SHIFT          12
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR1_BRIDGE_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved1 [11:06] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK                      0x00000fc0
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT                     6
+
+/* HIF_INTR2 :: CPU_SET :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_MASK             0x00000020
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_SHIFT            5
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_MASK            0x00000010
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_SHIFT           4
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_CPU_SET_WEBHIF_WD_TIMEOUT_INTR_MASK         0x00000008
+#define BCHP_HIF_INTR2_CPU_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT        3
+#define BCHP_HIF_INTR2_CPU_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: MICH1_INST1_RD_INTR [02:02] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH1_INST1_RD_INTR_MASK            0x00000004
+#define BCHP_HIF_INTR2_CPU_SET_MICH1_INST1_RD_INTR_SHIFT           2
+#define BCHP_HIF_INTR2_CPU_SET_MICH1_INST1_RD_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: MICH1_INST0_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH1_INST0_RD_INTR_MASK            0x00000002
+#define BCHP_HIF_INTR2_CPU_SET_MICH1_INST0_RD_INTR_SHIFT           1
+#define BCHP_HIF_INTR2_CPU_SET_MICH1_INST0_RD_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_MASK           0x00000001
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_SHIFT          0
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT        0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKDOWN_INTR_MASK           0x80000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKDOWN_INTR_SHIFT          31
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKDOWN_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKUP_INTR_MASK             0x40000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKUP_INTR_SHIFT            30
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKUP_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EDU_DONE_INTR_MASK                0x20000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EDU_DONE_INTR_SHIFT               29
+#define BCHP_HIF_INTR2_CPU_CLEAR_EDU_DONE_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EDU_ERR_INTR_MASK                 0x10000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EDU_ERR_INTR_SHIFT                28
+#define BCHP_HIF_INTR2_CPU_CLEAR_EDU_ERR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_MASK           0x00008000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_SHIFT          15
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK                    0x00004000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT                   14
+
+/* HIF_INTR2 :: CPU_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RG_BRIDGE_INTR_MASK          0x00002000
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT         13
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RG_BRIDGE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR1_BRIDGE_INTR_MASK         0x00001000
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR1_BRIDGE_INTR_SHIFT        12
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR1_BRIDGE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [11:06] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK                    0x00000fc0
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT                   6
+
+/* HIF_INTR2 :: CPU_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_MASK           0x00000020
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_SHIFT          5
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_MASK          0x00000010
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_SHIFT         4
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK       0x00000008
+#define BCHP_HIF_INTR2_CPU_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT      3
+#define BCHP_HIF_INTR2_CPU_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH1_INST1_RD_INTR [02:02] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH1_INST1_RD_INTR_MASK          0x00000004
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH1_INST1_RD_INTR_SHIFT         2
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH1_INST1_RD_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH1_INST0_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH1_INST0_RD_INTR_MASK          0x00000002
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH1_INST0_RD_INTR_SHIFT         1
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH1_INST0_RD_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKDOWN_INTR_MASK     0x80000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKDOWN_INTR_SHIFT    31
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKDOWN_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKUP_INTR_MASK       0x40000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKUP_INTR_SHIFT      30
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKUP_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EDU_DONE_INTR_MASK          0x20000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EDU_DONE_INTR_SHIFT         29
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EDU_DONE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EDU_ERR_INTR_MASK           0x10000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EDU_ERR_INTR_SHIFT          28
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EDU_ERR_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_MASK     0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_SHIFT    19
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_MASK     0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_SHIFT    15
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK              0x00004000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT             14
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RG_BRIDGE_INTR_MASK    0x00002000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT   13
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RG_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR1_BRIDGE_INTR_MASK   0x00001000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR1_BRIDGE_INTR_SHIFT  12
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR1_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [11:06] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK              0x00000fc0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT             6
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_MASK     0x00000020
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_SHIFT    5
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_MASK    0x00000010
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_SHIFT   4
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH1_INST1_RD_INTR [02:02] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH1_INST1_RD_INTR_MASK    0x00000004
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH1_INST1_RD_INTR_SHIFT   2
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH1_INST1_RD_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH1_INST0_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH1_INST0_RD_INTR_MASK    0x00000002
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH1_INST0_RD_INTR_SHIFT   1
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH1_INST0_RD_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK   0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT  0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKDOWN_INTR_MASK        0x80000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKDOWN_INTR_SHIFT       31
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKDOWN_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKUP_INTR_MASK          0x40000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKUP_INTR_SHIFT         30
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKUP_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EDU_DONE_INTR_MASK             0x20000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EDU_DONE_INTR_SHIFT            29
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EDU_DONE_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EDU_ERR_INTR_MASK              0x10000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EDU_ERR_INTR_SHIFT             28
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EDU_ERR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_MASK        0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_SHIFT       19
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_MASK        0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_SHIFT       15
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK                 0x00004000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT                14
+
+/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RG_BRIDGE_INTR_MASK       0x00002000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RG_BRIDGE_INTR_SHIFT      13
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RG_BRIDGE_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR1_BRIDGE_INTR_MASK      0x00001000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR1_BRIDGE_INTR_SHIFT     12
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR1_BRIDGE_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [11:06] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK                 0x00000fc0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT                6
+
+/* HIF_INTR2 :: CPU_MASK_SET :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_MASK        0x00000020
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_SHIFT       5
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_MASK       0x00000010
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_SHIFT      4
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_MASK    0x00000008
+#define BCHP_HIF_INTR2_CPU_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT   3
+#define BCHP_HIF_INTR2_CPU_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH1_INST1_RD_INTR [02:02] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH1_INST1_RD_INTR_MASK       0x00000004
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH1_INST1_RD_INTR_SHIFT      2
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH1_INST1_RD_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH1_INST0_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH1_INST0_RD_INTR_MASK       0x00000002
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH1_INST0_RD_INTR_SHIFT      1
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH1_INST0_RD_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK      0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT     0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKDOWN_INTR_MASK      0x80000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKDOWN_INTR_SHIFT     31
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKDOWN_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKUP_INTR_MASK        0x40000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKUP_INTR_SHIFT       30
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKUP_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EDU_DONE_INTR_MASK           0x20000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EDU_DONE_INTR_SHIFT          29
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EDU_DONE_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EDU_ERR_INTR_MASK            0x10000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EDU_ERR_INTR_SHIFT           28
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EDU_ERR_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_MASK      0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_SHIFT     15
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK               0x00004000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT              14
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_MASK     0x00002000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT    13
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR1_BRIDGE_INTR_MASK    0x00001000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR1_BRIDGE_INTR_SHIFT   12
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR1_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [11:06] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK               0x00000fc0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT              6
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_MASK      0x00000020
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_SHIFT     5
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_MASK     0x00000010
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_SHIFT    4
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK  0x00000008
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH1_INST1_RD_INTR [02:02] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH1_INST1_RD_INTR_MASK     0x00000004
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH1_INST1_RD_INTR_SHIFT    2
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH1_INST1_RD_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH1_INST0_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH1_INST0_RD_INTR_MASK     0x00000002
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH1_INST0_RD_INTR_SHIFT    1
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH1_INST0_RD_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKDOWN_INTR_MASK          0x80000000
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKDOWN_INTR_SHIFT         31
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKDOWN_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKUP_INTR_MASK            0x40000000
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKUP_INTR_SHIFT           30
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKUP_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EDU_DONE_INTR_MASK               0x20000000
+#define BCHP_HIF_INTR2_PCI_STATUS_EDU_DONE_INTR_SHIFT              29
+#define BCHP_HIF_INTR2_PCI_STATUS_EDU_DONE_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EDU_ERR_INTR_MASK                0x10000000
+#define BCHP_HIF_INTR2_PCI_STATUS_EDU_ERR_INTR_SHIFT               28
+#define BCHP_HIF_INTR2_PCI_STATUS_EDU_ERR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_MASK          0x00080000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_SHIFT         19
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_MASK          0x00008000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_SHIFT         15
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK                   0x00004000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT                  14
+
+/* HIF_INTR2 :: PCI_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RG_BRIDGE_INTR_MASK         0x00002000
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT        13
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RG_BRIDGE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR1_BRIDGE_INTR_MASK        0x00001000
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR1_BRIDGE_INTR_SHIFT       12
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR1_BRIDGE_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved1 [11:06] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK                   0x00000fc0
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT                  6
+
+/* HIF_INTR2 :: PCI_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_MASK          0x00000020
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_SHIFT         5
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_MASK         0x00000010
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_SHIFT        4
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_PCI_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK      0x00000008
+#define BCHP_HIF_INTR2_PCI_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT     3
+#define BCHP_HIF_INTR2_PCI_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH1_INST1_RD_INTR [02:02] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH1_INST1_RD_INTR_MASK         0x00000004
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH1_INST1_RD_INTR_SHIFT        2
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH1_INST1_RD_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH1_INST0_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH1_INST0_RD_INTR_MASK         0x00000002
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH1_INST0_RD_INTR_SHIFT        1
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH1_INST0_RD_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_MASK        0x00000001
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT       0
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_SET :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKDOWN_INTR_MASK             0x80000000
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKDOWN_INTR_SHIFT            31
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKDOWN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKUP_INTR_MASK               0x40000000
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKUP_INTR_SHIFT              30
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKUP_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_PCI_SET_EDU_DONE_INTR_MASK                  0x20000000
+#define BCHP_HIF_INTR2_PCI_SET_EDU_DONE_INTR_SHIFT                 29
+#define BCHP_HIF_INTR2_PCI_SET_EDU_DONE_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_PCI_SET_EDU_ERR_INTR_MASK                   0x10000000
+#define BCHP_HIF_INTR2_PCI_SET_EDU_ERR_INTR_SHIFT                  28
+#define BCHP_HIF_INTR2_PCI_SET_EDU_ERR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_MASK             0x00080000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_SHIFT            19
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_MASK             0x00008000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_SHIFT            15
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK                      0x00004000
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT                     14
+
+/* HIF_INTR2 :: PCI_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_RG_BRIDGE_INTR_MASK            0x00002000
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_RG_BRIDGE_INTR_SHIFT           13
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_RG_BRIDGE_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR1_BRIDGE_INTR_MASK           0x00001000
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR1_BRIDGE_INTR_SHIFT          12
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR1_BRIDGE_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved1 [11:06] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK                      0x00000fc0
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT                     6
+
+/* HIF_INTR2 :: PCI_SET :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_MASK             0x00000020
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_SHIFT            5
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_MASK            0x00000010
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_SHIFT           4
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_PCI_SET_WEBHIF_WD_TIMEOUT_INTR_MASK         0x00000008
+#define BCHP_HIF_INTR2_PCI_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT        3
+#define BCHP_HIF_INTR2_PCI_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: MICH1_INST1_RD_INTR [02:02] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH1_INST1_RD_INTR_MASK            0x00000004
+#define BCHP_HIF_INTR2_PCI_SET_MICH1_INST1_RD_INTR_SHIFT           2
+#define BCHP_HIF_INTR2_PCI_SET_MICH1_INST1_RD_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: MICH1_INST0_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH1_INST0_RD_INTR_MASK            0x00000002
+#define BCHP_HIF_INTR2_PCI_SET_MICH1_INST0_RD_INTR_SHIFT           1
+#define BCHP_HIF_INTR2_PCI_SET_MICH1_INST0_RD_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_MASK           0x00000001
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_SHIFT          0
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKDOWN_INTR_MASK           0x80000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKDOWN_INTR_SHIFT          31
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKDOWN_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKUP_INTR_MASK             0x40000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKUP_INTR_SHIFT            30
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKUP_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EDU_DONE_INTR_MASK                0x20000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EDU_DONE_INTR_SHIFT               29
+#define BCHP_HIF_INTR2_PCI_CLEAR_EDU_DONE_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EDU_ERR_INTR_MASK                 0x10000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EDU_ERR_INTR_SHIFT                28
+#define BCHP_HIF_INTR2_PCI_CLEAR_EDU_ERR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_MASK           0x00008000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_SHIFT          15
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK                    0x00004000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT                   14
+
+/* HIF_INTR2 :: PCI_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RG_BRIDGE_INTR_MASK          0x00002000
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT         13
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RG_BRIDGE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR1_BRIDGE_INTR_MASK         0x00001000
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR1_BRIDGE_INTR_SHIFT        12
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR1_BRIDGE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [11:06] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK                    0x00000fc0
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT                   6
+
+/* HIF_INTR2 :: PCI_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_MASK           0x00000020
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_SHIFT          5
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_MASK          0x00000010
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_SHIFT         4
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK       0x00000008
+#define BCHP_HIF_INTR2_PCI_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT      3
+#define BCHP_HIF_INTR2_PCI_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH1_INST1_RD_INTR [02:02] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH1_INST1_RD_INTR_MASK          0x00000004
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH1_INST1_RD_INTR_SHIFT         2
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH1_INST1_RD_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH1_INST0_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH1_INST0_RD_INTR_MASK          0x00000002
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH1_INST0_RD_INTR_SHIFT         1
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH1_INST0_RD_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKDOWN_INTR_MASK     0x80000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKDOWN_INTR_SHIFT    31
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKDOWN_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKUP_INTR_MASK       0x40000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKUP_INTR_SHIFT      30
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKUP_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EDU_DONE_INTR_MASK          0x20000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EDU_DONE_INTR_SHIFT         29
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EDU_DONE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EDU_ERR_INTR_MASK           0x10000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EDU_ERR_INTR_SHIFT          28
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EDU_ERR_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_MASK     0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_SHIFT    19
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_MASK     0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_SHIFT    15
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK              0x00004000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT             14
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RG_BRIDGE_INTR_MASK    0x00002000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT   13
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RG_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR1_BRIDGE_INTR_MASK   0x00001000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR1_BRIDGE_INTR_SHIFT  12
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR1_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [11:06] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK              0x00000fc0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT             6
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_MASK     0x00000020
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_SHIFT    5
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_MASK    0x00000010
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_SHIFT   4
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH1_INST1_RD_INTR [02:02] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH1_INST1_RD_INTR_MASK    0x00000004
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH1_INST1_RD_INTR_SHIFT   2
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH1_INST1_RD_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH1_INST0_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH1_INST0_RD_INTR_MASK    0x00000002
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH1_INST0_RD_INTR_SHIFT   1
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH1_INST0_RD_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK   0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT  0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKDOWN_INTR_MASK        0x80000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKDOWN_INTR_SHIFT       31
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKDOWN_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKUP_INTR_MASK          0x40000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKUP_INTR_SHIFT         30
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKUP_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EDU_DONE_INTR_MASK             0x20000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EDU_DONE_INTR_SHIFT            29
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EDU_DONE_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EDU_ERR_INTR_MASK              0x10000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EDU_ERR_INTR_SHIFT             28
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EDU_ERR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_MASK        0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_SHIFT       19
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_MASK        0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_SHIFT       15
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK                 0x00004000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT                14
+
+/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RG_BRIDGE_INTR_MASK       0x00002000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RG_BRIDGE_INTR_SHIFT      13
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RG_BRIDGE_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR1_BRIDGE_INTR_MASK      0x00001000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR1_BRIDGE_INTR_SHIFT     12
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR1_BRIDGE_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [11:06] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK                 0x00000fc0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT                6
+
+/* HIF_INTR2 :: PCI_MASK_SET :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_MASK        0x00000020
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_SHIFT       5
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_MASK       0x00000010
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_SHIFT      4
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_MASK    0x00000008
+#define BCHP_HIF_INTR2_PCI_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT   3
+#define BCHP_HIF_INTR2_PCI_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH1_INST1_RD_INTR [02:02] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH1_INST1_RD_INTR_MASK       0x00000004
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH1_INST1_RD_INTR_SHIFT      2
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH1_INST1_RD_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH1_INST0_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH1_INST0_RD_INTR_MASK       0x00000002
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH1_INST0_RD_INTR_SHIFT      1
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH1_INST0_RD_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK      0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT     0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKDOWN_INTR_MASK      0x80000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKDOWN_INTR_SHIFT     31
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKDOWN_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKUP_INTR_MASK        0x40000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKUP_INTR_SHIFT       30
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKUP_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EDU_DONE_INTR [29:29] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EDU_DONE_INTR_MASK           0x20000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EDU_DONE_INTR_SHIFT          29
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EDU_DONE_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EDU_ERR_INTR [28:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EDU_ERR_INTR_MASK            0x10000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EDU_ERR_INTR_SHIFT           28
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EDU_ERR_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_MASK      0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_SHIFT     15
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [14:14] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK               0x00004000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT              14
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_MASK     0x00002000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT    13
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR1_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR1_BRIDGE_INTR_MASK    0x00001000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR1_BRIDGE_INTR_SHIFT   12
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR1_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [11:06] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK               0x00000fc0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT              6
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_MASK      0x00000020
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_SHIFT     5
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_MASK     0x00000010
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_SHIFT    4
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK  0x00000008
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH1_INST1_RD_INTR [02:02] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH1_INST1_RD_INTR_MASK     0x00000004
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH1_INST1_RD_INTR_SHIFT    2
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH1_INST1_RD_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH1_INST0_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH1_INST0_RD_INTR_MASK     0x00000002
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH1_INST0_RD_INTR_SHIFT    1
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH1_INST0_RD_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+#endif /* #ifndef BCHP_HIF_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_hif_mspi.h b/include/linux/brcmstb/7435b0/bchp_hif_mspi.h
new file mode 100644
index 0000000..d0fc660
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_hif_mspi.h
@@ -0,0 +1,1214 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:22 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_hif_mspi.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 2:35p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_MSPI_H__
+#define BCHP_HIF_MSPI_H__
+
+/***************************************************************************
+ *HIF_MSPI - Public MSPI Registers
+ ***************************************************************************/
+#define BCHP_HIF_MSPI_SPCR0_LSB                  0x0041d400 /* SPCR0_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR0_MSB                  0x0041d404 /* SPCR0_MSB Register */
+#define BCHP_HIF_MSPI_SPCR1_LSB                  0x0041d408 /* SPCR1_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR1_MSB                  0x0041d40c /* SPCR1_MSB REGISTER */
+#define BCHP_HIF_MSPI_NEWQP                      0x0041d410 /* NEWQP REGISTER */
+#define BCHP_HIF_MSPI_ENDQP                      0x0041d414 /* ENDQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR2                      0x0041d418 /* SPCR2 REGISTER */
+#define BCHP_HIF_MSPI_MSPI_STATUS                0x0041d420 /* MSPI STATUS REGISTER */
+#define BCHP_HIF_MSPI_CPTQP                      0x0041d424 /* CPTQP REGISTER */
+#define BCHP_HIF_MSPI_TXRAM00                    0x0041d440 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM01                    0x0041d444 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM02                    0x0041d448 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM03                    0x0041d44c /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM04                    0x0041d450 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM05                    0x0041d454 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM06                    0x0041d458 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM07                    0x0041d45c /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM08                    0x0041d460 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM09                    0x0041d464 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM10                    0x0041d468 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM11                    0x0041d46c /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM12                    0x0041d470 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM13                    0x0041d474 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM14                    0x0041d478 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM15                    0x0041d47c /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM16                    0x0041d480 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM17                    0x0041d484 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM18                    0x0041d488 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM19                    0x0041d48c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM20                    0x0041d490 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM21                    0x0041d494 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM22                    0x0041d498 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM23                    0x0041d49c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM24                    0x0041d4a0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM25                    0x0041d4a4 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM26                    0x0041d4a8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM27                    0x0041d4ac /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM28                    0x0041d4b0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM29                    0x0041d4b4 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM30                    0x0041d4b8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_TXRAM31                    0x0041d4bc /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM00                    0x0041d4c0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM01                    0x0041d4c4 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM02                    0x0041d4c8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM03                    0x0041d4cc /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM04                    0x0041d4d0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM05                    0x0041d4d4 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM06                    0x0041d4d8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM07                    0x0041d4dc /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM08                    0x0041d4e0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM09                    0x0041d4e4 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM10                    0x0041d4e8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM11                    0x0041d4ec /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM12                    0x0041d4f0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM13                    0x0041d4f4 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM14                    0x0041d4f8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM15                    0x0041d4fc /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM16                    0x0041d500 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM17                    0x0041d504 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM18                    0x0041d508 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM19                    0x0041d50c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM20                    0x0041d510 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM21                    0x0041d514 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM22                    0x0041d518 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM23                    0x0041d51c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM24                    0x0041d520 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM25                    0x0041d524 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM26                    0x0041d528 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM27                    0x0041d52c /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM28                    0x0041d530 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM29                    0x0041d534 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM30                    0x0041d538 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM31                    0x0041d53c /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_CDRAM00                    0x0041d540 /* 8-bit command (queue pointer = 0) */
+#define BCHP_HIF_MSPI_CDRAM01                    0x0041d544 /* 8-bit command (queue pointer = 1) */
+#define BCHP_HIF_MSPI_CDRAM02                    0x0041d548 /* 8-bit command (queue pointer = 2) */
+#define BCHP_HIF_MSPI_CDRAM03                    0x0041d54c /* 8-bit command (queue pointer = 3) */
+#define BCHP_HIF_MSPI_CDRAM04                    0x0041d550 /* 8-bit command (queue pointer = 4) */
+#define BCHP_HIF_MSPI_CDRAM05                    0x0041d554 /* 8-bit command (queue pointer = 5) */
+#define BCHP_HIF_MSPI_CDRAM06                    0x0041d558 /* 8-bit command (queue pointer = 6) */
+#define BCHP_HIF_MSPI_CDRAM07                    0x0041d55c /* 8-bit command (queue pointer = 7) */
+#define BCHP_HIF_MSPI_CDRAM08                    0x0041d560 /* 8-bit command (queue pointer = 8) */
+#define BCHP_HIF_MSPI_CDRAM09                    0x0041d564 /* 8-bit command (queue pointer = 9) */
+#define BCHP_HIF_MSPI_CDRAM10                    0x0041d568 /* 8-bit command (queue pointer = a) */
+#define BCHP_HIF_MSPI_CDRAM11                    0x0041d56c /* 8-bit command (queue pointer = b) */
+#define BCHP_HIF_MSPI_CDRAM12                    0x0041d570 /* 8-bit command (queue pointer = c) */
+#define BCHP_HIF_MSPI_CDRAM13                    0x0041d574 /* 8-bit command (queue pointer = d) */
+#define BCHP_HIF_MSPI_CDRAM14                    0x0041d578 /* 8-bit command (queue pointer = e) */
+#define BCHP_HIF_MSPI_CDRAM15                    0x0041d57c /* 8-bit command (queue pointer = f) */
+#define BCHP_HIF_MSPI_WRITE_LOCK                 0x0041d580 /* Control bit to lock group of write commands */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN          0x0041d584 /* Debug bit to mask the generation of flush signals from Mspi */
+
+/***************************************************************************
+ *SPCR0_LSB - SPCR0_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK                          0x000000ff
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR0_MSB - SPCR0_MSB Register
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_MSB :: MSTR [07:07] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_MASK                          0x00000080
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_SHIFT                         7
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_DEFAULT                       0x00000001
+
+/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [06:06] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK               0x00000040
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT              6
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT            0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: BitS [05:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_MASK                          0x0000003c
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_SHIFT                         2
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_DEFAULT                       0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK                          0x00000002
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT                         1
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT                       0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK                          0x00000001
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR1_LSB - SPCR1_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT                          0
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *SPCR1_MSB - SPCR1_MSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK                        0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT                       0
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *NEWQP - NEWQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: NEWQP :: newqp [03:00] */
+#define BCHP_HIF_MSPI_NEWQP_newqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT                            0
+#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *ENDQP - ENDQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: ENDQP :: endqp [03:00] */
+#define BCHP_HIF_MSPI_ENDQP_endqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT                            0
+#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *SPCR2 - SPCR2 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK                         0xffffff00
+#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT                        8
+
+/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK                    0x00000080
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT                   7
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT                 0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spe [06:06] */
+#define BCHP_HIF_MSPI_SPCR2_spe_MASK                               0x00000040
+#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT                              6
+#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
+#define BCHP_HIF_MSPI_SPCR2_spifie_MASK                            0x00000020
+#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT                           5
+#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT                         0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wren [04:04] */
+#define BCHP_HIF_MSPI_SPCR2_wren_MASK                              0x00000010
+#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT                             4
+#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
+#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK                              0x00000008
+#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT                             3
+#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
+#define BCHP_HIF_MSPI_SPCR2_loopq_MASK                             0x00000004
+#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT                            2
+#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT                          0x00000000
+
+/* HIF_MSPI :: SPCR2 :: hie [01:01] */
+#define BCHP_HIF_MSPI_SPCR2_hie_MASK                               0x00000002
+#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT                              1
+#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: halt [00:00] */
+#define BCHP_HIF_MSPI_SPCR2_halt_MASK                              0x00000001
+#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT                             0
+#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *MSPI_STATUS - MSPI STATUS REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK                   0xfffffffc
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT                  2
+
+/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK                       0x00000002
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT                      1
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT                    0x00000000
+
+/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK                        0x00000001
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT                       0
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *CPTQP - CPTQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
+#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT                            0
+#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *TXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM00_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM01_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM02_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM03_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM04_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM05_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM06_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM07_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM08_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM09_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM10_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM11_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM12_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM13_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM14_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM15_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM16_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM17_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM18_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM19_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM20_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM21_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM22_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM23_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM24_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM25_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM26_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM27_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM28_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM29_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM30_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM31_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM00 - 8-bit command (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM00 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM01 - 8-bit command (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM01 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM02 - 8-bit command (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM02 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM03 - 8-bit command (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM03 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM04 - 8-bit command (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM04 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM05 - 8-bit command (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM05 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM06 - 8-bit command (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM06 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM07 - 8-bit command (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM07 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM08 - 8-bit command (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM08 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM09 - 8-bit command (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM09 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM10 - 8-bit command (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM10 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM11 - 8-bit command (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM11 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM12 - 8-bit command (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM12 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM13 - 8-bit command (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM13 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM14 - 8-bit command (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM14 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM15 - 8-bit command (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM15 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT                          0
+
+/***************************************************************************
+ *WRITE_LOCK - Control bit to lock group of write commands
+ ***************************************************************************/
+/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK                    0xfffffffe
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT                   1
+
+/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK                    0x00000001
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT                   0
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
+ ***************************************************************************/
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK             0xfffffffe
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT            1
+
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK       0x00000001
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT      0
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT    0x00000000
+
+#endif /* #ifndef BCHP_HIF_MSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_hif_rgr1.h b/include/linux/brcmstb/7435b0/bchp_hif_rgr1.h
new file mode 100644
index 0000000..f950a73
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_hif_rgr1.h
@@ -0,0 +1,137 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:12 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_hif_rgr1.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 2:36p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_RGR1_H__
+#define BCHP_HIF_RGR1_H__
+
+/***************************************************************************
+ *HIF_RGR1 - HIF RBUS-GISB-RBUS Bridge Registers
+ ***************************************************************************/
+#define BCHP_HIF_RGR1_REVISION                   0x00419200 /* RGR Bridge Revision */
+#define BCHP_HIF_RGR1_CTRL                       0x00419204 /* RGR Bridge Control Register */
+#define BCHP_HIF_RGR1_RBUS_TIMER                 0x00419208 /* RGR Bridge RBUS Timer Register */
+#define BCHP_HIF_RGR1_SW_INIT_0                  0x0041920c /* RGR Bridge Software Reset 0 Register */
+#define BCHP_HIF_RGR1_SW_INIT_1                  0x00419210 /* RGR Bridge Software Reset 1 Register */
+
+/***************************************************************************
+ *REVISION - RGR Bridge Revision
+ ***************************************************************************/
+/* HIF_RGR1 :: REVISION :: reserved0 [31:16] */
+#define BCHP_HIF_RGR1_REVISION_reserved0_MASK                      0xffff0000
+#define BCHP_HIF_RGR1_REVISION_reserved0_SHIFT                     16
+
+/* HIF_RGR1 :: REVISION :: MAJOR [15:08] */
+#define BCHP_HIF_RGR1_REVISION_MAJOR_MASK                          0x0000ff00
+#define BCHP_HIF_RGR1_REVISION_MAJOR_SHIFT                         8
+#define BCHP_HIF_RGR1_REVISION_MAJOR_DEFAULT                       0x00000002
+
+/* HIF_RGR1 :: REVISION :: MINOR [07:00] */
+#define BCHP_HIF_RGR1_REVISION_MINOR_MASK                          0x000000ff
+#define BCHP_HIF_RGR1_REVISION_MINOR_SHIFT                         0
+#define BCHP_HIF_RGR1_REVISION_MINOR_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *CTRL - RGR Bridge Control Register
+ ***************************************************************************/
+/* HIF_RGR1 :: CTRL :: reserved0 [31:02] */
+#define BCHP_HIF_RGR1_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_HIF_RGR1_CTRL_reserved0_SHIFT                         2
+
+/* HIF_RGR1 :: CTRL :: rbus_error_intr [01:01] */
+#define BCHP_HIF_RGR1_CTRL_rbus_error_intr_MASK                    0x00000002
+#define BCHP_HIF_RGR1_CTRL_rbus_error_intr_SHIFT                   1
+#define BCHP_HIF_RGR1_CTRL_rbus_error_intr_DEFAULT                 0x00000000
+#define BCHP_HIF_RGR1_CTRL_rbus_error_intr_INTR_DISABLE            0
+#define BCHP_HIF_RGR1_CTRL_rbus_error_intr_INTR_ENABLE             1
+
+/* HIF_RGR1 :: CTRL :: gisb_error_intr [00:00] */
+#define BCHP_HIF_RGR1_CTRL_gisb_error_intr_MASK                    0x00000001
+#define BCHP_HIF_RGR1_CTRL_gisb_error_intr_SHIFT                   0
+#define BCHP_HIF_RGR1_CTRL_gisb_error_intr_DEFAULT                 0x00000000
+#define BCHP_HIF_RGR1_CTRL_gisb_error_intr_INTR_DISABLE            0
+#define BCHP_HIF_RGR1_CTRL_gisb_error_intr_INTR_ENABLE             1
+
+/***************************************************************************
+ *RBUS_TIMER - RGR Bridge RBUS Timer Register
+ ***************************************************************************/
+/* HIF_RGR1 :: RBUS_TIMER :: timer_value [31:00] */
+#define BCHP_HIF_RGR1_RBUS_TIMER_timer_value_MASK                  0xffffffff
+#define BCHP_HIF_RGR1_RBUS_TIMER_timer_value_SHIFT                 0
+#define BCHP_HIF_RGR1_RBUS_TIMER_timer_value_DEFAULT               0x0e297d00
+
+/***************************************************************************
+ *SW_INIT_0 - RGR Bridge Software Reset 0 Register
+ ***************************************************************************/
+/* HIF_RGR1 :: SW_INIT_0 :: reserved0 [31:01] */
+#define BCHP_HIF_RGR1_SW_INIT_0_reserved0_MASK                     0xfffffffe
+#define BCHP_HIF_RGR1_SW_INIT_0_reserved0_SHIFT                    1
+
+/* HIF_RGR1 :: SW_INIT_0 :: SPARE_SW_INIT [00:00] */
+#define BCHP_HIF_RGR1_SW_INIT_0_SPARE_SW_INIT_MASK                 0x00000001
+#define BCHP_HIF_RGR1_SW_INIT_0_SPARE_SW_INIT_SHIFT                0
+#define BCHP_HIF_RGR1_SW_INIT_0_SPARE_SW_INIT_DEFAULT              0x00000000
+#define BCHP_HIF_RGR1_SW_INIT_0_SPARE_SW_INIT_DEASSERT             0
+#define BCHP_HIF_RGR1_SW_INIT_0_SPARE_SW_INIT_ASSERT               1
+
+/***************************************************************************
+ *SW_INIT_1 - RGR Bridge Software Reset 1 Register
+ ***************************************************************************/
+/* HIF_RGR1 :: SW_INIT_1 :: reserved0 [31:02] */
+#define BCHP_HIF_RGR1_SW_INIT_1_reserved0_MASK                     0xfffffffc
+#define BCHP_HIF_RGR1_SW_INIT_1_reserved0_SHIFT                    2
+
+/* HIF_RGR1 :: SW_INIT_1 :: PCIE_BRIDGE_SW_INIT [01:01] */
+#define BCHP_HIF_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_MASK           0x00000002
+#define BCHP_HIF_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_SHIFT          1
+#define BCHP_HIF_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_DEFAULT        0x00000001
+#define BCHP_HIF_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_DEASSERT       0
+#define BCHP_HIF_RGR1_SW_INIT_1_PCIE_BRIDGE_SW_INIT_ASSERT         1
+
+/* HIF_RGR1 :: SW_INIT_1 :: PCIE_SW_PERST [00:00] */
+#define BCHP_HIF_RGR1_SW_INIT_1_PCIE_SW_PERST_MASK                 0x00000001
+#define BCHP_HIF_RGR1_SW_INIT_1_PCIE_SW_PERST_SHIFT                0
+#define BCHP_HIF_RGR1_SW_INIT_1_PCIE_SW_PERST_DEFAULT              0x00000001
+#define BCHP_HIF_RGR1_SW_INIT_1_PCIE_SW_PERST_DEASSERT             0
+#define BCHP_HIF_RGR1_SW_INIT_1_PCIE_SW_PERST_ASSERT               1
+
+#endif /* #ifndef BCHP_HIF_RGR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/7435b0/bchp_hif_spi_intr2.h
new file mode 100644
index 0000000..776a1a5
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_hif_spi_intr2.h
@@ -0,0 +1,567 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:09 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_hif_spi_intr2.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 2:37p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_SPI_INTR2_H__
+#define BCHP_HIF_SPI_INTR2_H__
+
+/***************************************************************************
+ *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
+ ***************************************************************************/
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS            0x0041bd00 /* CPU interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_SET               0x0041bd04 /* CPU interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR             0x0041bd08 /* CPU interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS       0x0041bd0c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET          0x0041bd10 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR        0x0041bd14 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS            0x0041bd18 /* PCI interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_SET               0x0041bd1c /* PCI interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR             0x0041bd20 /* PCI interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS       0x0041bd24 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET          0x0041bd28 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR        0x0041bd2c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_hif_top_ctrl.h b/include/linux/brcmstb/7435b0/bchp_hif_top_ctrl.h
new file mode 100644
index 0000000..a9c8bff
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_hif_top_ctrl.h
@@ -0,0 +1,548 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:17 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_hif_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 2:38p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_TOP_CTRL_H__
+#define BCHP_HIF_TOP_CTRL_H__
+
+/***************************************************************************
+ *HIF_TOP_CTRL - HIF Top Control Registers
+ ***************************************************************************/
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL          0x0041c400 /* External IRQ Active Level Control Register */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL            0x0041c404 /* SPI test port select register */
+#define BCHP_HIF_TOP_CTRL_SCRATCH                0x0041c408 /* HIF Scratch Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0               0x0041c40c /* HIF Power Management Control0 Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1               0x0041c410 /* HIF Power Management Control1 Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2               0x0041c414 /* HIF Power Management Control Register:used to control SDIO_0 (CARD) */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3               0x0041c418 /* HIF Power Management Control Register:used to control SDIO_1 (EMMC) */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE             0x0041c41c /* HIF Decoded Flash Type */
+#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL          0x0041c430 /* CPU MODE Control register (PUBLIC) */
+#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS        0x0041c434 /* CPU MODE Control status register (PUBLIC) */
+
+/***************************************************************************
+ *EXT_IRQ_LEVEL - External IRQ Active Level Control Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: reserved0 [31:06] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_MASK             0xffffffc0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_SHIFT            6
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_5_level [05:05] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_MASK       0x00000020
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_SHIFT      5
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_LOW        0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_5_level_HIGH       1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_4_level [04:04] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_MASK       0x00000010
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_SHIFT      4
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_LOW        0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_4_level_HIGH       1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_3_level [03:03] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_MASK       0x00000008
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_SHIFT      3
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_LOW        0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_3_level_HIGH       1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_2_level [02:02] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_MASK       0x00000004
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_LOW        0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_2_level_HIGH       1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_1_level [01:01] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_MASK       0x00000002
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_SHIFT      1
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_LOW        0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_1_level_HIGH       1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_0_level [00:00] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_MASK       0x00000001
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_SHIFT      0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_LOW        0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_0_level_HIGH       1
+
+/***************************************************************************
+ *SPI_DBG_SEL - SPI test port select register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_MASK               0xfffffff8
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_SHIFT              3
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: DISABLE_MSPI_FLUSH [02:02] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_MASK      0x00000004
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_SHIFT     2
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_DEFAULT   0x00000000
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SPI_RBUS_TIMER_EN [01:01] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_MASK       0x00000002
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_SHIFT      1
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_DEFAULT    0x00000000
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SDIO_TP_SEL [00:00] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SDIO_TP_SEL_MASK             0x00000001
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SDIO_TP_SEL_SHIFT            0
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SDIO_TP_SEL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *SCRATCH - HIF Scratch Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SCRATCH :: SCRATCH_BITS [31:00] */
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BITS_MASK                0xffffffff
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BITS_SHIFT               0
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BITS_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PM_CTRL0 - HIF Power Management Control0 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_PM_IN_DRIVE_INACTIVE [31:30] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_MASK   0xc0000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_SHIFT  30
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_IN_DRIVE_INACTIVE [29:28] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x30000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 28
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_CTRL_PM_IN_DRIVE_INACTIVE [27:26] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_MASK 0x0c000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_SHIFT 26
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_NOT_USED 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_DATA_PM_OUT_CTRL [25:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_MASK       0x03000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_SHIFT      24
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_ADDR_PM_OUT_CTRL [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_MASK       0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_SHIFT      22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_CTRL_PM_OUT_CTRL [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_MASK       0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_SHIFT      20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_OUT_CTRL [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_MASK      0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_SHIFT     18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_CTRL_PM_OUT_CTRL [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_MASK      0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_SHIFT     16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS7 [15:14] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_MASK            0x0000c000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_SHIFT           14
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS6 [13:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_MASK            0x00003000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_SHIFT           12
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS5 [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_MASK            0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_SHIFT           10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS4 [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_MASK            0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_SHIFT           8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS3 [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_MASK            0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_SHIFT           6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS2 [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_MASK            0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_SHIFT           4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS1 [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_MASK            0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_SHIFT           2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS0 [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_MASK            0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_SHIFT           0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_Tristate        3
+
+/***************************************************************************
+ *PM_CTRL1 - HIF Power Management Control1 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL1 :: reserved0 [31:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_MASK                  0xfffff000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_PM_IN_DRIVE_INACTIVE [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_WPB_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_MASK        0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_SHIFT       8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_DEFAULT     0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_Tristate    3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_HOLDB_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_MASK      0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_SHIFT     6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MISO_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_MASK       0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_SHIFT      4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MOSI_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_MASK        0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_SHIFT       0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_DEFAULT     0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_Tristate    3
+
+/***************************************************************************
+ *PM_CTRL2 - HIF Power Management Control Register:used to control SDIO_0 (CARD)
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved0 [31:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_MASK                  0xff000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_SHIFT                 24
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_MASK 0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_SHIFT 22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_MASK 0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_SHIFT 20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_IN_DRIVE_INACTIVE [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_IN_DRIVE_INACTIVE [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_MASK 0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_SHIFT 16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved1 [15:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_MASK                  0x0000f000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_VOLTAGE_PM_OUT_CTRL [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_LOW    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_HIGH   2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_POWER_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_MASK     0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_SHIFT    8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_DEFAULT  0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_LOW      1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_HIGH     2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_LED_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_MASK       0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_SHIFT      6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_MASK      0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_MASK       0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_SHIFT      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_Tristate   3
+
+/***************************************************************************
+ *PM_CTRL3 - HIF Power Management Control Register:used to control SDIO_1 (EMMC)
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL3 :: reserved0 [31:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved0_MASK                  0xfff00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved0_SHIFT                 20
+
+/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_DATA_PM_IN_DRIVE_INACTIVE [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_CMD_PM_IN_DRIVE_INACTIVE [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_MASK 0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_SHIFT 16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL3 :: reserved1 [15:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved1_MASK                  0x0000ffc0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_reserved1_SHIFT                 6
+
+/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_DATA_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_MASK      0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_CMD_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CMD_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL3 :: SDIO_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_MASK       0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_SHIFT      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL3_SDIO_CLK_PM_OUT_CTRL_Tristate   3
+
+/***************************************************************************
+ *FLASH_TYPE - HIF Decoded Flash Type
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: FLASH_TYPE :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_MASK                0xfffffff8
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_SHIFT               3
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: InvalidStrap [02:02] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_MASK             0x00000004
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_SHIFT            2
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_DEFAULT          0x00000000
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: FLASH_TYPE [01:00] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_MASK               0x00000003
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SHIFT              0
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_ParallelNOR        0
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_Nand               1
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SerialNOR          2
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_eMMC               3
+
+/***************************************************************************
+ *CPU_MODE_CTRL - CPU MODE Control register (PUBLIC)
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: CPU_MODE_CTRL :: reserved0 [31:01] */
+#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_reserved0_MASK             0xfffffffe
+#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_reserved0_SHIFT            1
+
+/* HIF_TOP_CTRL :: CPU_MODE_CTRL :: CPU_MODE [00:00] */
+#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_CPU_MODE_MASK              0x00000001
+#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_CPU_MODE_SHIFT             0
+#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_CPU_MODE_DEFAULT           0x00000000
+#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_CPU_MODE_QuadSMP           0
+#define BCHP_HIF_TOP_CTRL_CPU_MODE_CTRL_CPU_MODE_WebCPU            1
+
+/***************************************************************************
+ *CPU_MODE_STATUS - CPU MODE Control status register (PUBLIC)
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: CPU_MODE_STATUS :: reserved0 [31:08] */
+#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_reserved0_MASK           0xffffff00
+#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_reserved0_SHIFT          8
+
+/* HIF_TOP_CTRL :: CPU_MODE_STATUS :: SPARE_STATUS [07:03] */
+#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_SPARE_STATUS_MASK        0x000000f8
+#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_SPARE_STATUS_SHIFT       3
+
+/* HIF_TOP_CTRL :: CPU_MODE_STATUS :: CPU_MODE_STATUS [02:02] */
+#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_CPU_MODE_STATUS_MASK     0x00000004
+#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_CPU_MODE_STATUS_SHIFT    2
+
+/* HIF_TOP_CTRL :: CPU_MODE_STATUS :: CPU_MODE_OTP [01:00] */
+#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_CPU_MODE_OTP_MASK        0x00000003
+#define BCHP_HIF_TOP_CTRL_CPU_MODE_STATUS_CPU_MODE_OTP_SHIFT       0
+
+#endif /* #ifndef BCHP_HIF_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_irq0.h b/include/linux/brcmstb/7435b0/bchp_irq0.h
new file mode 100644
index 0000000..c34b469
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_irq0.h
@@ -0,0 +1,217 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:27 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_irq0.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 2:46p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ0_H__
+#define BCHP_IRQ0_H__
+
+/***************************************************************************
+ *IRQ0 - Level 2 CPU Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ0_IRQEN                          0x00406780 /* Interrupt Enable */
+#define BCHP_IRQ0_IRQSTAT                        0x00406784 /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ0 :: IRQEN :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQEN_reserved0_MASK                             0xf8000000
+#define BCHP_IRQ0_IRQEN_reserved0_SHIFT                            27
+
+/* IRQ0 :: IRQEN :: iica_irqen [26:26] */
+#define BCHP_IRQ0_IRQEN_iica_irqen_MASK                            0x04000000
+#define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT                           26
+#define BCHP_IRQ0_IRQEN_iica_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: iicd_irqen [25:25] */
+#define BCHP_IRQ0_IRQEN_iicd_irqen_MASK                            0x02000000
+#define BCHP_IRQ0_IRQEN_iicd_irqen_SHIFT                           25
+#define BCHP_IRQ0_IRQEN_iicd_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: iicc_irqen [24:24] */
+#define BCHP_IRQ0_IRQEN_iicc_irqen_MASK                            0x01000000
+#define BCHP_IRQ0_IRQEN_iicc_irqen_SHIFT                           24
+#define BCHP_IRQ0_IRQEN_iicc_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQEN_reserved1_MASK                             0x00f80000
+#define BCHP_IRQ0_IRQEN_reserved1_SHIFT                            19
+
+/* IRQ0 :: IRQEN :: uartc_irqen [18:18] */
+#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK                           0x00040000
+#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT                          18
+#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uartb_irqen [17:17] */
+#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK                           0x00020000
+#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT                          17
+#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uarta_irqen [16:16] */
+#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK                           0x00010000
+#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT                          16
+#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQEN_reserved2_MASK                             0x0000fc00
+#define BCHP_IRQ0_IRQEN_reserved2_SHIFT                            10
+
+/* IRQ0 :: IRQEN :: uc_irqen [09:09] */
+#define BCHP_IRQ0_IRQEN_uc_irqen_MASK                              0x00000200
+#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT                             9
+#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQEN_reserved3_MASK                             0x00000180
+#define BCHP_IRQ0_IRQEN_reserved3_SHIFT                            7
+
+/* IRQ0 :: IRQEN :: gio_irqen [06:06] */
+#define BCHP_IRQ0_IRQEN_gio_irqen_MASK                             0x00000040
+#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT                            6
+#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQEN :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQEN_reserved4_MASK                             0x00000020
+#define BCHP_IRQ0_IRQEN_reserved4_SHIFT                            5
+
+/* IRQ0 :: IRQEN :: ua_irqen [04:04] */
+#define BCHP_IRQ0_IRQEN_ua_irqen_MASK                              0x00000010
+#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT                             4
+#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: ub_irqen [03:03] */
+#define BCHP_IRQ0_IRQEN_ub_irqen_MASK                              0x00000008
+#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT                             3
+#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: irb_irqen [02:02] */
+#define BCHP_IRQ0_IRQEN_irb_irqen_MASK                             0x00000004
+#define BCHP_IRQ0_IRQEN_irb_irqen_SHIFT                            2
+#define BCHP_IRQ0_IRQEN_irb_irqen_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQEN :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQEN_reserved5_MASK                             0x00000003
+#define BCHP_IRQ0_IRQEN_reserved5_SHIFT                            0
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ0 :: IRQSTAT :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQSTAT_reserved0_MASK                           0xf8000000
+#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT                          27
+
+/* IRQ0 :: IRQSTAT :: iicairq [26:26] */
+#define BCHP_IRQ0_IRQSTAT_iicairq_MASK                             0x04000000
+#define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT                            26
+#define BCHP_IRQ0_IRQSTAT_iicairq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: iicdirq [25:25] */
+#define BCHP_IRQ0_IRQSTAT_iicdirq_MASK                             0x02000000
+#define BCHP_IRQ0_IRQSTAT_iicdirq_SHIFT                            25
+#define BCHP_IRQ0_IRQSTAT_iicdirq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: iiccirq [24:24] */
+#define BCHP_IRQ0_IRQSTAT_iiccirq_MASK                             0x01000000
+#define BCHP_IRQ0_IRQSTAT_iiccirq_SHIFT                            24
+#define BCHP_IRQ0_IRQSTAT_iiccirq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQSTAT_reserved1_MASK                           0x00f80000
+#define BCHP_IRQ0_IRQSTAT_reserved1_SHIFT                          19
+
+/* IRQ0 :: IRQSTAT :: uartc_irq [18:18] */
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK                           0x00040000
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT                          18
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uartb_irq [17:17] */
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK                           0x00020000
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT                          17
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uarta_irq [16:16] */
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK                           0x00010000
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT                          16
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQSTAT_reserved2_MASK                           0x0000fc00
+#define BCHP_IRQ0_IRQSTAT_reserved2_SHIFT                          10
+
+/* IRQ0 :: IRQSTAT :: ucirq [09:09] */
+#define BCHP_IRQ0_IRQSTAT_ucirq_MASK                               0x00000200
+#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT                              9
+#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQSTAT_reserved3_MASK                           0x00000180
+#define BCHP_IRQ0_IRQSTAT_reserved3_SHIFT                          7
+
+/* IRQ0 :: IRQSTAT :: gioirq [06:06] */
+#define BCHP_IRQ0_IRQSTAT_gioirq_MASK                              0x00000040
+#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT                             6
+#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQSTAT_reserved4_MASK                           0x00000020
+#define BCHP_IRQ0_IRQSTAT_reserved4_SHIFT                          5
+
+/* IRQ0 :: IRQSTAT :: uairq [04:04] */
+#define BCHP_IRQ0_IRQSTAT_uairq_MASK                               0x00000010
+#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT                              4
+#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: ubirq [03:03] */
+#define BCHP_IRQ0_IRQSTAT_ubirq_MASK                               0x00000008
+#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT                              3
+#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: irbirq [02:02] */
+#define BCHP_IRQ0_IRQSTAT_irbirq_MASK                              0x00000004
+#define BCHP_IRQ0_IRQSTAT_irbirq_SHIFT                             2
+#define BCHP_IRQ0_IRQSTAT_irbirq_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQSTAT_reserved5_MASK                           0x00000003
+#define BCHP_IRQ0_IRQSTAT_reserved5_SHIFT                          0
+
+#endif /* #ifndef BCHP_IRQ0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_irq1.h b/include/linux/brcmstb/7435b0/bchp_irq1.h
new file mode 100644
index 0000000..6b166b0
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_irq1.h
@@ -0,0 +1,214 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Jul 20 15:43:15 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ1_H__
+#define BCHP_IRQ1_H__
+
+/***************************************************************************
+ *IRQ1 - Level 2 PCI Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ1_IRQEN                          0x00406788 /* Interrupt Enable */
+#define BCHP_IRQ1_IRQSTAT                        0x0040678c /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ1 :: IRQEN :: reserved0 [31:27] */
+#define BCHP_IRQ1_IRQEN_reserved0_MASK                             0xf8000000
+#define BCHP_IRQ1_IRQEN_reserved0_SHIFT                            27
+
+/* IRQ1 :: IRQEN :: iica_irqen [26:26] */
+#define BCHP_IRQ1_IRQEN_iica_irqen_MASK                            0x04000000
+#define BCHP_IRQ1_IRQEN_iica_irqen_SHIFT                           26
+#define BCHP_IRQ1_IRQEN_iica_irqen_DEFAULT                         0x00000000
+
+/* IRQ1 :: IRQEN :: iicd_irqen [25:25] */
+#define BCHP_IRQ1_IRQEN_iicd_irqen_MASK                            0x02000000
+#define BCHP_IRQ1_IRQEN_iicd_irqen_SHIFT                           25
+#define BCHP_IRQ1_IRQEN_iicd_irqen_DEFAULT                         0x00000000
+
+/* IRQ1 :: IRQEN :: iicc_irqen [24:24] */
+#define BCHP_IRQ1_IRQEN_iicc_irqen_MASK                            0x01000000
+#define BCHP_IRQ1_IRQEN_iicc_irqen_SHIFT                           24
+#define BCHP_IRQ1_IRQEN_iicc_irqen_DEFAULT                         0x00000000
+
+/* IRQ1 :: IRQEN :: reserved1 [23:19] */
+#define BCHP_IRQ1_IRQEN_reserved1_MASK                             0x00f80000
+#define BCHP_IRQ1_IRQEN_reserved1_SHIFT                            19
+
+/* IRQ1 :: IRQEN :: uartc_irqen [18:18] */
+#define BCHP_IRQ1_IRQEN_uartc_irqen_MASK                           0x00040000
+#define BCHP_IRQ1_IRQEN_uartc_irqen_SHIFT                          18
+#define BCHP_IRQ1_IRQEN_uartc_irqen_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQEN :: uartb_irqen [17:17] */
+#define BCHP_IRQ1_IRQEN_uartb_irqen_MASK                           0x00020000
+#define BCHP_IRQ1_IRQEN_uartb_irqen_SHIFT                          17
+#define BCHP_IRQ1_IRQEN_uartb_irqen_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQEN :: uarta_irqen [16:16] */
+#define BCHP_IRQ1_IRQEN_uarta_irqen_MASK                           0x00010000
+#define BCHP_IRQ1_IRQEN_uarta_irqen_SHIFT                          16
+#define BCHP_IRQ1_IRQEN_uarta_irqen_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQEN :: reserved2 [15:10] */
+#define BCHP_IRQ1_IRQEN_reserved2_MASK                             0x0000fc00
+#define BCHP_IRQ1_IRQEN_reserved2_SHIFT                            10
+
+/* IRQ1 :: IRQEN :: uc_irqen [09:09] */
+#define BCHP_IRQ1_IRQEN_uc_irqen_MASK                              0x00000200
+#define BCHP_IRQ1_IRQEN_uc_irqen_SHIFT                             9
+#define BCHP_IRQ1_IRQEN_uc_irqen_DEFAULT                           0x00000000
+
+/* IRQ1 :: IRQEN :: reserved3 [08:07] */
+#define BCHP_IRQ1_IRQEN_reserved3_MASK                             0x00000180
+#define BCHP_IRQ1_IRQEN_reserved3_SHIFT                            7
+
+/* IRQ1 :: IRQEN :: gio_irqen [06:06] */
+#define BCHP_IRQ1_IRQEN_gio_irqen_MASK                             0x00000040
+#define BCHP_IRQ1_IRQEN_gio_irqen_SHIFT                            6
+#define BCHP_IRQ1_IRQEN_gio_irqen_DEFAULT                          0x00000000
+
+/* IRQ1 :: IRQEN :: reserved4 [05:05] */
+#define BCHP_IRQ1_IRQEN_reserved4_MASK                             0x00000020
+#define BCHP_IRQ1_IRQEN_reserved4_SHIFT                            5
+
+/* IRQ1 :: IRQEN :: ua_irqen [04:04] */
+#define BCHP_IRQ1_IRQEN_ua_irqen_MASK                              0x00000010
+#define BCHP_IRQ1_IRQEN_ua_irqen_SHIFT                             4
+#define BCHP_IRQ1_IRQEN_ua_irqen_DEFAULT                           0x00000000
+
+/* IRQ1 :: IRQEN :: ub_irqen [03:03] */
+#define BCHP_IRQ1_IRQEN_ub_irqen_MASK                              0x00000008
+#define BCHP_IRQ1_IRQEN_ub_irqen_SHIFT                             3
+#define BCHP_IRQ1_IRQEN_ub_irqen_DEFAULT                           0x00000000
+
+/* IRQ1 :: IRQEN :: irb_irqen [02:02] */
+#define BCHP_IRQ1_IRQEN_irb_irqen_MASK                             0x00000004
+#define BCHP_IRQ1_IRQEN_irb_irqen_SHIFT                            2
+#define BCHP_IRQ1_IRQEN_irb_irqen_DEFAULT                          0x00000000
+
+/* IRQ1 :: IRQEN :: reserved5 [01:00] */
+#define BCHP_IRQ1_IRQEN_reserved5_MASK                             0x00000003
+#define BCHP_IRQ1_IRQEN_reserved5_SHIFT                            0
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ1 :: IRQSTAT :: reserved0 [31:27] */
+#define BCHP_IRQ1_IRQSTAT_reserved0_MASK                           0xf8000000
+#define BCHP_IRQ1_IRQSTAT_reserved0_SHIFT                          27
+
+/* IRQ1 :: IRQSTAT :: iicairq [26:26] */
+#define BCHP_IRQ1_IRQSTAT_iicairq_MASK                             0x04000000
+#define BCHP_IRQ1_IRQSTAT_iicairq_SHIFT                            26
+#define BCHP_IRQ1_IRQSTAT_iicairq_DEFAULT                          0x00000000
+
+/* IRQ1 :: IRQSTAT :: iicdirq [25:25] */
+#define BCHP_IRQ1_IRQSTAT_iicdirq_MASK                             0x02000000
+#define BCHP_IRQ1_IRQSTAT_iicdirq_SHIFT                            25
+#define BCHP_IRQ1_IRQSTAT_iicdirq_DEFAULT                          0x00000000
+
+/* IRQ1 :: IRQSTAT :: iiccirq [24:24] */
+#define BCHP_IRQ1_IRQSTAT_iiccirq_MASK                             0x01000000
+#define BCHP_IRQ1_IRQSTAT_iiccirq_SHIFT                            24
+#define BCHP_IRQ1_IRQSTAT_iiccirq_DEFAULT                          0x00000000
+
+/* IRQ1 :: IRQSTAT :: reserved1 [23:19] */
+#define BCHP_IRQ1_IRQSTAT_reserved1_MASK                           0x00f80000
+#define BCHP_IRQ1_IRQSTAT_reserved1_SHIFT                          19
+
+/* IRQ1 :: IRQSTAT :: uartc_irq [18:18] */
+#define BCHP_IRQ1_IRQSTAT_uartc_irq_MASK                           0x00040000
+#define BCHP_IRQ1_IRQSTAT_uartc_irq_SHIFT                          18
+#define BCHP_IRQ1_IRQSTAT_uartc_irq_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQSTAT :: uartb_irq [17:17] */
+#define BCHP_IRQ1_IRQSTAT_uartb_irq_MASK                           0x00020000
+#define BCHP_IRQ1_IRQSTAT_uartb_irq_SHIFT                          17
+#define BCHP_IRQ1_IRQSTAT_uartb_irq_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQSTAT :: uarta_irq [16:16] */
+#define BCHP_IRQ1_IRQSTAT_uarta_irq_MASK                           0x00010000
+#define BCHP_IRQ1_IRQSTAT_uarta_irq_SHIFT                          16
+#define BCHP_IRQ1_IRQSTAT_uarta_irq_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQSTAT :: reserved2 [15:10] */
+#define BCHP_IRQ1_IRQSTAT_reserved2_MASK                           0x0000fc00
+#define BCHP_IRQ1_IRQSTAT_reserved2_SHIFT                          10
+
+/* IRQ1 :: IRQSTAT :: ucirq [09:09] */
+#define BCHP_IRQ1_IRQSTAT_ucirq_MASK                               0x00000200
+#define BCHP_IRQ1_IRQSTAT_ucirq_SHIFT                              9
+#define BCHP_IRQ1_IRQSTAT_ucirq_DEFAULT                            0x00000000
+
+/* IRQ1 :: IRQSTAT :: reserved3 [08:07] */
+#define BCHP_IRQ1_IRQSTAT_reserved3_MASK                           0x00000180
+#define BCHP_IRQ1_IRQSTAT_reserved3_SHIFT                          7
+
+/* IRQ1 :: IRQSTAT :: gioirq [06:06] */
+#define BCHP_IRQ1_IRQSTAT_gioirq_MASK                              0x00000040
+#define BCHP_IRQ1_IRQSTAT_gioirq_SHIFT                             6
+#define BCHP_IRQ1_IRQSTAT_gioirq_DEFAULT                           0x00000000
+
+/* IRQ1 :: IRQSTAT :: reserved4 [05:05] */
+#define BCHP_IRQ1_IRQSTAT_reserved4_MASK                           0x00000020
+#define BCHP_IRQ1_IRQSTAT_reserved4_SHIFT                          5
+
+/* IRQ1 :: IRQSTAT :: uairq [04:04] */
+#define BCHP_IRQ1_IRQSTAT_uairq_MASK                               0x00000010
+#define BCHP_IRQ1_IRQSTAT_uairq_SHIFT                              4
+#define BCHP_IRQ1_IRQSTAT_uairq_DEFAULT                            0x00000000
+
+/* IRQ1 :: IRQSTAT :: ubirq [03:03] */
+#define BCHP_IRQ1_IRQSTAT_ubirq_MASK                               0x00000008
+#define BCHP_IRQ1_IRQSTAT_ubirq_SHIFT                              3
+#define BCHP_IRQ1_IRQSTAT_ubirq_DEFAULT                            0x00000000
+
+/* IRQ1 :: IRQSTAT :: irbirq [02:02] */
+#define BCHP_IRQ1_IRQSTAT_irbirq_MASK                              0x00000004
+#define BCHP_IRQ1_IRQSTAT_irbirq_SHIFT                             2
+#define BCHP_IRQ1_IRQSTAT_irbirq_DEFAULT                           0x00000000
+
+/* IRQ1 :: IRQSTAT :: reserved5 [01:00] */
+#define BCHP_IRQ1_IRQSTAT_reserved5_MASK                           0x00000003
+#define BCHP_IRQ1_IRQSTAT_reserved5_SHIFT                          0
+
+#endif /* #ifndef BCHP_IRQ1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_mem_dma_0.h b/include/linux/brcmstb/7435b0/bchp_mem_dma_0.h
new file mode 100644
index 0000000..04c03d7
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_mem_dma_0.h
@@ -0,0 +1,154 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Jul 27 03:16:53 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEM_DMA_0_H__
+#define BCHP_MEM_DMA_0_H__
+
+/***************************************************************************
+ *MEM_DMA_0 - MEM_DMA_0 Registers
+ ***************************************************************************/
+#define BCHP_MEM_DMA_0_REVISION                  0x00376200 /* MEM_DMA REVISION */
+#define BCHP_MEM_DMA_0_FIRST_DESC                0x00376204 /* MEM_DMA First Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CTRL                      0x00376208 /* MEM_DMA Control Register */
+#define BCHP_MEM_DMA_0_WAKE_CTRL                 0x0037620c /* MEM_DMA Wake Control Register */
+#define BCHP_MEM_DMA_0_STATUS                    0x00376214 /* MEM_DMA Status Register */
+#define BCHP_MEM_DMA_0_CUR_DESC                  0x00376218 /* MEM_DMA Current Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CUR_BYTE                  0x0037621c /* MEM_DMA Current Byte Count Register */
+#define BCHP_MEM_DMA_0_SCRATCH                   0x00376224 /* MEM_DMA Scratch Register */
+
+/***************************************************************************
+ *REVISION - MEM_DMA REVISION
+ ***************************************************************************/
+/* MEM_DMA_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_0_REVISION_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_0_REVISION_reserved0_SHIFT                    16
+
+/* MEM_DMA_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_MASK                         0x0000ff00
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_SHIFT                        8
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_DEFAULT                      0x00000002
+
+/* MEM_DMA_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_MEM_DMA_0_REVISION_MINOR_MASK                         0x000000ff
+#define BCHP_MEM_DMA_0_REVISION_MINOR_SHIFT                        0
+#define BCHP_MEM_DMA_0_REVISION_MINOR_DEFAULT                      0x0000000a
+
+/***************************************************************************
+ *FIRST_DESC - MEM_DMA First Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: FIRST_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_MASK                        0xffffffff
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_SHIFT                       0
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *CTRL - MEM_DMA Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CTRL :: reserved0 [31:01] */
+#define BCHP_MEM_DMA_0_CTRL_reserved0_MASK                         0xfffffffe
+#define BCHP_MEM_DMA_0_CTRL_reserved0_SHIFT                        1
+
+/* MEM_DMA_0 :: CTRL :: RUN [00:00] */
+#define BCHP_MEM_DMA_0_CTRL_RUN_MASK                               0x00000001
+#define BCHP_MEM_DMA_0_CTRL_RUN_SHIFT                              0
+#define BCHP_MEM_DMA_0_CTRL_RUN_DEFAULT                            0x00000000
+
+/***************************************************************************
+ *WAKE_CTRL - MEM_DMA Wake Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: WAKE_CTRL :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_MASK                    0xfffffffc
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_SHIFT                   2
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE_MODE [01:01] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_MASK                    0x00000002
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_SHIFT                   1
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_DEFAULT                 0x00000000
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE [00:00] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MASK                         0x00000001
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_SHIFT                        0
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *STATUS - MEM_DMA Status Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: STATUS :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_MEM_DMA_0_STATUS_reserved0_SHIFT                      2
+
+/* MEM_DMA_0 :: STATUS :: DMA_STATUS [01:00] */
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_MASK                      0x00000003
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_SHIFT                     0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_DEFAULT                   0x00000000
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Idle                      0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Busy                      1
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Sleep                     2
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Reserved                  3
+
+/***************************************************************************
+ *CUR_DESC - MEM_DMA Current Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_MASK                          0xffffffff
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_SHIFT                         0
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *CUR_BYTE - MEM_DMA Current Byte Count Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_BYTE :: reserved0 [31:25] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_MASK                     0xfe000000
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_SHIFT                    25
+
+/* MEM_DMA_0 :: CUR_BYTE :: COUNT [24:00] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_MASK                         0x01ffffff
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_SHIFT                        0
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *SCRATCH - MEM_DMA Scratch Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_MASK                    0xffffffff
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_SHIFT                   0
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_DEFAULT                 0x00000000
+
+#endif /* #ifndef BCHP_MEM_DMA_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_memc_arb_1.h b/include/linux/brcmstb/7435b0/bchp_memc_arb_1.h
new file mode 100644
index 0000000..9e73617
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_memc_arb_1.h
@@ -0,0 +1,4086 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Jul 20 15:43:15 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_ARB_1_H__
+#define BCHP_MEMC_ARB_1_H__
+
+/***************************************************************************
+ *MEMC_ARB_1 - Memory Controller Arbitration & Client Info Registers 1
+ ***************************************************************************/
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER 0x003c1000 /* MEMC CORE and IOBUF Interface Debug Register */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0            0x003c1004 /* Client Programming register for client 0. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1            0x003c1008 /* Client Programming register for client 1. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2            0x003c100c /* Client Programming register for client 2. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3            0x003c1010 /* Client Programming register for client 3. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4            0x003c1014 /* Client Programming register for client 4. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5            0x003c1018 /* Client Programming register for client 5. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6            0x003c101c /* Client Programming register for client 6. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7            0x003c1020 /* Client Programming register for client 7. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8            0x003c1024 /* Client Programming register for client 8. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9            0x003c1028 /* Client Programming register for client 9. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10           0x003c102c /* Client Programming register for client 10. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11           0x003c1030 /* Client Programming register for client 11. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12           0x003c1034 /* Client Programming register for client 12. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13           0x003c1038 /* Client Programming register for client 13. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14           0x003c103c /* Client Programming register for client 14. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15           0x003c1040 /* Client Programming register for client 15. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16           0x003c1044 /* Client Programming register for client 16. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17           0x003c1048 /* Client Programming register for client 17. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18           0x003c104c /* Client Programming register for client 18. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19           0x003c1050 /* Client Programming register for client 19. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20           0x003c1054 /* Client Programming register for client 20. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21           0x003c1058 /* Client Programming register for client 21. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22           0x003c105c /* Client Programming register for client 22. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23           0x003c1060 /* Client Programming register for client 23. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24           0x003c1064 /* Client Programming register for client 24. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25           0x003c1068 /* Client Programming register for client 25. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26           0x003c106c /* Client Programming register for client 26. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27           0x003c1070 /* Client Programming register for client 27. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28           0x003c1074 /* Client Programming register for client 28. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29           0x003c1078 /* Client Programming register for client 29. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30           0x003c107c /* Client Programming register for client 30. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31           0x003c1080 /* Client Programming register for client 31. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32           0x003c1084 /* Client Programming register for client 32. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33           0x003c1088 /* Client Programming register for client 33. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34           0x003c108c /* Client Programming register for client 34. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35           0x003c1090 /* Client Programming register for client 35. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36           0x003c1094 /* Client Programming register for client 36. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37           0x003c1098 /* Client Programming register for client 37. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38           0x003c109c /* Client Programming register for client 38. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39           0x003c10a0 /* Client Programming register for client 39. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40           0x003c10a4 /* Client Programming register for client 40. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41           0x003c10a8 /* Client Programming register for client 41. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42           0x003c10ac /* Client Programming register for client 42. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43           0x003c10b0 /* Client Programming register for client 43. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44           0x003c10b4 /* Client Programming register for client 44. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45           0x003c10b8 /* Client Programming register for client 45. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46           0x003c10bc /* Client Programming register for client 46. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47           0x003c10c0 /* Client Programming register for client 47. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48           0x003c10c4 /* Client Programming register for client 48. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49           0x003c10c8 /* Client Programming register for client 49. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50           0x003c10cc /* Client Programming register for client 50. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51           0x003c10d0 /* Client Programming register for client 51. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52           0x003c10d4 /* Client Programming register for client 52. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53           0x003c10d8 /* Client Programming register for client 53. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54           0x003c10dc /* Client Programming register for client 54. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55           0x003c10e0 /* Client Programming register for client 55. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56           0x003c10e4 /* Client Programming register for client 56. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57           0x003c10e8 /* Client Programming register for client 57. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58           0x003c10ec /* Client Programming register for client 58. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59           0x003c10f0 /* Client Programming register for client 59. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60           0x003c10f4 /* Client Programming register for client 60. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61           0x003c10f8 /* Client Programming register for client 61. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62           0x003c10fc /* Client Programming register for client 62. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63           0x003c1100 /* Client Programming register for client 63. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64           0x003c1104 /* Client Programming register for client 64. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65           0x003c1108 /* Client Programming register for client 65. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66           0x003c110c /* Client Programming register for client 66. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67           0x003c1110 /* Client Programming register for client 67. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68           0x003c1114 /* Client Programming register for client 68. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69           0x003c1118 /* Client Programming register for client 69. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70           0x003c111c /* Client Programming register for client 70. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71           0x003c1120 /* Client Programming register for client 71. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72           0x003c1124 /* Client Programming register for client 72. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73           0x003c1128 /* Client Programming register for client 73. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74           0x003c112c /* Client Programming register for client 74. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75           0x003c1130 /* Client Programming register for client 75. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76           0x003c1134 /* Client Programming register for client 76. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77           0x003c1138 /* Client Programming register for client 77. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78           0x003c113c /* Client Programming register for client 78. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79           0x003c1140 /* Client Programming register for client 79. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80           0x003c1144 /* Client Programming register for client 80. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81           0x003c1148 /* Client Programming register for client 81. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82           0x003c114c /* Client Programming register for client 82. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83           0x003c1150 /* Client Programming register for client 83. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84           0x003c1154 /* Client Programming register for client 84. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85           0x003c1158 /* Client Programming register for client 85. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86           0x003c115c /* Client Programming register for client 86. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87           0x003c1160 /* Client Programming register for client 87. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88           0x003c1164 /* Client Programming register for client 88. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89           0x003c1168 /* Client Programming register for client 89. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90           0x003c116c /* Client Programming register for client 90. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91           0x003c1170 /* Client Programming register for client 91. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92           0x003c1174 /* Client Programming register for client 92. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93           0x003c1178 /* Client Programming register for client 93. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94           0x003c117c /* Client Programming register for client 94. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95           0x003c1180 /* Client Programming register for client 95. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96           0x003c1184 /* Client Programming register for client 96. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97           0x003c1188 /* Client Programming register for client 97. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98           0x003c118c /* Client Programming register for client 98. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99           0x003c1190 /* Client Programming register for client 99. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100          0x003c1194 /* Client Programming register for client 100. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101          0x003c1198 /* Client Programming register for client 101. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102          0x003c119c /* Client Programming register for client 102. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103          0x003c11a0 /* Client Programming register for client 103. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104          0x003c11a4 /* Client Programming register for client 104. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105          0x003c11a8 /* Client Programming register for client 105. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106          0x003c11ac /* Client Programming register for client 106. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107          0x003c11b0 /* Client Programming register for client 107. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108          0x003c11b4 /* Client Programming register for client 108. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109          0x003c11b8 /* Client Programming register for client 109. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110          0x003c11bc /* Client Programming register for client 110. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111          0x003c11c0 /* Client Programming register for client 111. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112          0x003c11c4 /* Client Programming register for client 112. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113          0x003c11c8 /* Client Programming register for client 113. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114          0x003c11cc /* Client Programming register for client 114. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115          0x003c11d0 /* Client Programming register for client 115. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116          0x003c11d4 /* Client Programming register for client 116. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117          0x003c11d8 /* Client Programming register for client 117. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118          0x003c11dc /* Client Programming register for client 118. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119          0x003c11e0 /* Client Programming register for client 119. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120          0x003c11e4 /* Client Programming register for client 120. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121          0x003c11e8 /* Client Programming register for client 121. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122          0x003c11ec /* Client Programming register for client 122. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123          0x003c11f0 /* Client Programming register for client 123. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124          0x003c11f4 /* Client Programming register for client 124. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125          0x003c11f8 /* Client Programming register for client 125. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126          0x003c11fc /* Client Programming register for client 126. */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127          0x003c1200 /* Client Programming register for client 127 */
+#define BCHP_MEMC_ARB_1_REQ_MASK_0               0x003c1204 /* Request Mask register for Clients 0 to 31 */
+#define BCHP_MEMC_ARB_1_REQ_MASK_1               0x003c1208 /* Request Mask register for Clients 32 to 63 */
+#define BCHP_MEMC_ARB_1_REQ_MASK_2               0x003c120c /* Request Mask register for Clients 64 to 95 */
+#define BCHP_MEMC_ARB_1_REQ_MASK_3               0x003c1210 /* Request Mask register for Clients 96 to 127 */
+#define BCHP_MEMC_ARB_1_ARB_WINNER               0x003c1214 /* SCB-Arbitration Winner. */
+#define BCHP_MEMC_ARB_1_RTS_ERR_0                0x003c1218 /* RTS Deadline miss register for Clients 0 to 31 */
+#define BCHP_MEMC_ARB_1_RTS_ERR_1                0x003c121c /* RTS Deadline miss register for Clients 32 to 63 */
+#define BCHP_MEMC_ARB_1_RTS_ERR_2                0x003c1220 /* RTS Deadline miss register for Clients 64 to 95 */
+#define BCHP_MEMC_ARB_1_RTS_ERR_3                0x003c1224 /* RTS Deadline miss register for Clients 96 to 127 */
+#define BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD       0x003c1228 /* Arbiter fullness threshold register */
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE     0x003c122c /* Minimum command size register */
+#define BCHP_MEMC_ARB_1_RTS_ERR_INFO_WRITE_CLEAR 0x003c1230 /* MEMC RTS_ERR_INFO write clear register */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER 0x003c1234 /* MEMC SCB Interface and Arbiter State Machine and FIFO Debug Register */
+#define BCHP_MEMC_ARB_1_SPARE_1                  0x003c1238 /* Spare Register 1 . */
+#define BCHP_MEMC_ARB_1_SPARE_2                  0x003c123c /* Spare Register 2 . */
+#define BCHP_MEMC_ARB_1_SPARE_RO_1               0x003c1240 /* Read only Spare Register 1 . */
+#define BCHP_MEMC_ARB_1_SPARE_RO_2               0x003c1244 /* Read only Spare Register 2 . */
+
+/***************************************************************************
+ *ANALOG_PHY_DEBUG_REGISTER - MEMC CORE and IOBUF Interface Debug Register
+ ***************************************************************************/
+/* MEMC_ARB_1 :: ANALOG_PHY_DEBUG_REGISTER :: reserved0 [31:08] */
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_reserved0_MASK   0xffffff00
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_reserved0_SHIFT  8
+
+/* MEMC_ARB_1 :: ANALOG_PHY_DEBUG_REGISTER :: PMC2MEMC_BSP_RDY [07:07] */
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_PMC2MEMC_BSP_RDY_MASK 0x00000080
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_PMC2MEMC_BSP_RDY_SHIFT 7
+
+/* MEMC_ARB_1 :: ANALOG_PHY_DEBUG_REGISTER :: PHY2CORE_INIT_RDY [06:06] */
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_PHY2CORE_INIT_RDY_MASK 0x00000040
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_PHY2CORE_INIT_RDY_SHIFT 6
+
+/* MEMC_ARB_1 :: ANALOG_PHY_DEBUG_REGISTER :: PHY2CORE_POWERDOWN_RDY [05:05] */
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_PHY2CORE_POWERDOWN_RDY_MASK 0x00000020
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_PHY2CORE_POWERDOWN_RDY_SHIFT 5
+
+/* MEMC_ARB_1 :: ANALOG_PHY_DEBUG_REGISTER :: IO2C_CMD_DATA_FIFO_FULL [04:04] */
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_IO2C_CMD_DATA_FIFO_FULL_MASK 0x00000010
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_IO2C_CMD_DATA_FIFO_FULL_SHIFT 4
+
+/* MEMC_ARB_1 :: ANALOG_PHY_DEBUG_REGISTER :: IO2C_RD_DATA_FIFO_EMPTY [03:03] */
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_IO2C_RD_DATA_FIFO_EMPTY_MASK 0x00000008
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_IO2C_RD_DATA_FIFO_EMPTY_SHIFT 3
+
+/* MEMC_ARB_1 :: ANALOG_PHY_DEBUG_REGISTER :: C2IO_CMD_DATA_FIFO_PUSH [02:02] */
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_C2IO_CMD_DATA_FIFO_PUSH_MASK 0x00000004
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_C2IO_CMD_DATA_FIFO_PUSH_SHIFT 2
+
+/* MEMC_ARB_1 :: ANALOG_PHY_DEBUG_REGISTER :: DRAM_RD_DATA_FIFO_POP [01:01] */
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_DRAM_RD_DATA_FIFO_POP_MASK 0x00000002
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_DRAM_RD_DATA_FIFO_POP_SHIFT 1
+
+/* MEMC_ARB_1 :: ANALOG_PHY_DEBUG_REGISTER :: CORE2PHY_PLL_DLL_SHUTDOWN_REQ [00:00] */
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_CORE2PHY_PLL_DLL_SHUTDOWN_REQ_MASK 0x00000001
+#define BCHP_MEMC_ARB_1_ANALOG_PHY_DEBUG_REGISTER_CORE2PHY_PLL_DLL_SHUTDOWN_REQ_SHIFT 0
+
+/***************************************************************************
+ *CLIENT_INFO_0 - Client Programming register for client 0.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_0 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_RR_EN_MASK                   0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_RR_EN_SHIFT                  31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_RR_EN_DEFAULT                0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_RR_EN_DISABLED               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_RR_EN_ENABLED                1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_0 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_reserved0_MASK               0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_reserved0_SHIFT              27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_0 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_BO_VAL_MASK                  0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_BO_VAL_SHIFT                 12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_BO_VAL_DEFAULT               0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_0 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_reserved1_MASK               0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_reserved1_SHIFT              7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_0 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_PR_TAG_MASK                  0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_PR_TAG_SHIFT                 0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_0_PR_TAG_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_1 - Client Programming register for client 1.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_1 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_RR_EN_MASK                   0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_RR_EN_SHIFT                  31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_RR_EN_DEFAULT                0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_RR_EN_DISABLED               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_RR_EN_ENABLED                1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_1 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_reserved0_MASK               0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_reserved0_SHIFT              27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_1 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_BO_VAL_MASK                  0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_BO_VAL_SHIFT                 12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_BO_VAL_DEFAULT               0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_1 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_reserved1_MASK               0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_reserved1_SHIFT              7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_1 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_PR_TAG_MASK                  0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_PR_TAG_SHIFT                 0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_1_PR_TAG_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_2 - Client Programming register for client 2.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_2 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_RR_EN_MASK                   0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_RR_EN_SHIFT                  31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_RR_EN_DEFAULT                0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_RR_EN_DISABLED               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_RR_EN_ENABLED                1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_2 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_reserved0_MASK               0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_reserved0_SHIFT              27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_2 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_BO_VAL_MASK                  0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_BO_VAL_SHIFT                 12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_BO_VAL_DEFAULT               0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_2 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_reserved1_MASK               0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_reserved1_SHIFT              7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_2 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_PR_TAG_MASK                  0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_PR_TAG_SHIFT                 0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_2_PR_TAG_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_3 - Client Programming register for client 3.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_3 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_RR_EN_MASK                   0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_RR_EN_SHIFT                  31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_RR_EN_DEFAULT                0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_RR_EN_DISABLED               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_RR_EN_ENABLED                1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_3 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_reserved0_MASK               0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_reserved0_SHIFT              27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_3 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_BO_VAL_MASK                  0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_BO_VAL_SHIFT                 12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_BO_VAL_DEFAULT               0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_3 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_reserved1_MASK               0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_reserved1_SHIFT              7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_3 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_PR_TAG_MASK                  0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_PR_TAG_SHIFT                 0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_3_PR_TAG_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_4 - Client Programming register for client 4.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_4 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_RR_EN_MASK                   0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_RR_EN_SHIFT                  31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_RR_EN_DEFAULT                0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_RR_EN_DISABLED               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_RR_EN_ENABLED                1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_4 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_reserved0_MASK               0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_reserved0_SHIFT              27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_4 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_BO_VAL_MASK                  0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_BO_VAL_SHIFT                 12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_BO_VAL_DEFAULT               0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_4 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_reserved1_MASK               0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_reserved1_SHIFT              7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_4 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_PR_TAG_MASK                  0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_PR_TAG_SHIFT                 0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_4_PR_TAG_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_5 - Client Programming register for client 5.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_5 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_RR_EN_MASK                   0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_RR_EN_SHIFT                  31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_RR_EN_DEFAULT                0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_RR_EN_DISABLED               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_RR_EN_ENABLED                1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_5 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_reserved0_MASK               0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_reserved0_SHIFT              27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_5 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_BO_VAL_MASK                  0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_BO_VAL_SHIFT                 12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_BO_VAL_DEFAULT               0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_5 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_reserved1_MASK               0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_reserved1_SHIFT              7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_5 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_PR_TAG_MASK                  0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_PR_TAG_SHIFT                 0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_5_PR_TAG_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_6 - Client Programming register for client 6.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_6 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_RR_EN_MASK                   0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_RR_EN_SHIFT                  31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_RR_EN_DEFAULT                0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_RR_EN_DISABLED               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_RR_EN_ENABLED                1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_6 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_reserved0_MASK               0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_reserved0_SHIFT              27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_6 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_BO_VAL_MASK                  0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_BO_VAL_SHIFT                 12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_BO_VAL_DEFAULT               0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_6 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_reserved1_MASK               0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_reserved1_SHIFT              7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_6 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_PR_TAG_MASK                  0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_PR_TAG_SHIFT                 0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_6_PR_TAG_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_7 - Client Programming register for client 7.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_7 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_RR_EN_MASK                   0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_RR_EN_SHIFT                  31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_RR_EN_DEFAULT                0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_RR_EN_DISABLED               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_RR_EN_ENABLED                1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_7 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_reserved0_MASK               0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_reserved0_SHIFT              27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_7 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_BO_VAL_MASK                  0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_BO_VAL_SHIFT                 12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_BO_VAL_DEFAULT               0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_7 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_reserved1_MASK               0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_reserved1_SHIFT              7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_7 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_PR_TAG_MASK                  0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_PR_TAG_SHIFT                 0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_7_PR_TAG_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_8 - Client Programming register for client 8.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_8 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_RR_EN_MASK                   0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_RR_EN_SHIFT                  31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_RR_EN_DEFAULT                0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_RR_EN_DISABLED               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_RR_EN_ENABLED                1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_8 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_reserved0_MASK               0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_reserved0_SHIFT              27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_8 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_BO_VAL_MASK                  0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_BO_VAL_SHIFT                 12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_BO_VAL_DEFAULT               0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_8 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_reserved1_MASK               0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_reserved1_SHIFT              7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_8 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_PR_TAG_MASK                  0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_PR_TAG_SHIFT                 0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_8_PR_TAG_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_9 - Client Programming register for client 9.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_9 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_RR_EN_MASK                   0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_RR_EN_SHIFT                  31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_RR_EN_DEFAULT                0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_RR_EN_DISABLED               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_RR_EN_ENABLED                1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_9 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_reserved0_MASK               0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_reserved0_SHIFT              27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_9 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_BO_VAL_MASK                  0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_BO_VAL_SHIFT                 12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_BO_VAL_DEFAULT               0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_9 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_reserved1_MASK               0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_reserved1_SHIFT              7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_9 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_PR_TAG_MASK                  0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_PR_TAG_SHIFT                 0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_9_PR_TAG_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_10 - Client Programming register for client 10.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_10 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_10 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_10 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_10 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_10 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_10_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_11 - Client Programming register for client 11.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_11 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_11 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_11 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_11 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_11 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_11_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_12 - Client Programming register for client 12.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_12 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_12 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_12 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_12 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_12 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_12_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_13 - Client Programming register for client 13.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_13 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_13 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_13 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_13 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_13 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_13_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_14 - Client Programming register for client 14.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_14 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_14 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_14 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_14 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_14 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_14_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_15 - Client Programming register for client 15.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_15 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_15 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_15 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_15 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_15 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_15_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_16 - Client Programming register for client 16.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_16 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_16 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_16 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_16 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_16 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_16_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_17 - Client Programming register for client 17.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_17 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_17 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_17 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_17 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_17 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_17_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_18 - Client Programming register for client 18.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_18 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_18 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_18 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_18 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_18 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_18_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_19 - Client Programming register for client 19.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_19 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_19 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_19 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_19 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_19 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_19_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_20 - Client Programming register for client 20.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_20 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_20 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_20 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_20 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_20 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_20_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_21 - Client Programming register for client 21.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_21 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_21 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_21 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_21 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_21 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_21_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_22 - Client Programming register for client 22.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_22 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_22 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_22 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_22 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_22 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_22_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_23 - Client Programming register for client 23.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_23 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_23 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_23 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_23 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_23 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_23_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_24 - Client Programming register for client 24.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_24 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_24 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_24 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_24 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_24 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_24_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_25 - Client Programming register for client 25.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_25 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_25 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_25 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_25 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_25 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_25_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_26 - Client Programming register for client 26.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_26 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_26 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_26 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_26 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_26 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_26_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_27 - Client Programming register for client 27.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_27 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_27 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_27 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_27 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_27 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_27_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_28 - Client Programming register for client 28.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_28 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_28 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_28 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_28 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_28 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_28_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_29 - Client Programming register for client 29.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_29 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_29 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_29 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_29 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_29 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_29_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_30 - Client Programming register for client 30.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_30 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_30 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_30 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_30 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_30 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_30_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_31 - Client Programming register for client 31.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_31 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_31 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_31 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_31 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_31 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_31_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_32 - Client Programming register for client 32.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_32 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_32 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_32 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_32 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_32 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_32_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_33 - Client Programming register for client 33.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_33 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_33 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_33 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_33 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_33 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_33_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_34 - Client Programming register for client 34.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_34 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_34 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_34 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_34 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_34 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_34_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_35 - Client Programming register for client 35.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_35 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_35 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_35 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_35 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_35 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_35_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_36 - Client Programming register for client 36.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_36 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_36 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_36 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_36 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_36 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_36_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_37 - Client Programming register for client 37.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_37 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_37 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_37 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_37 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_37 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_37_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_38 - Client Programming register for client 38.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_38 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_38 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_38 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_38 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_38 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_38_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_39 - Client Programming register for client 39.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_39 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_39 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_39 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_39 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_39 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_39_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_40 - Client Programming register for client 40.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_40 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_40 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_40 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_40 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_40 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_40_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_41 - Client Programming register for client 41.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_41 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_41 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_41 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_41 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_41 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_41_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_42 - Client Programming register for client 42.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_42 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_42 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_42 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_42 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_42 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_42_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_43 - Client Programming register for client 43.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_43 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_43 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_43 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_43 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_43 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_43_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_44 - Client Programming register for client 44.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_44 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_44 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_44 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_44 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_44 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_44_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_45 - Client Programming register for client 45.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_45 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_45 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_45 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_45 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_45 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_45_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_46 - Client Programming register for client 46.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_46 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_46 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_46 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_46 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_46 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_46_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_47 - Client Programming register for client 47.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_47 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_47 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_47 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_47 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_47 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_47_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_48 - Client Programming register for client 48.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_48 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_48 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_48 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_48 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_48 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_48_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_49 - Client Programming register for client 49.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_49 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_49 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_49 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_49 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_49 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_49_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_50 - Client Programming register for client 50.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_50 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_50 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_50 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_50 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_50 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_50_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_51 - Client Programming register for client 51.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_51 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_51 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_51 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_51 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_51 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_51_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_52 - Client Programming register for client 52.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_52 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_52 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_52 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_52 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_52 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_52_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_53 - Client Programming register for client 53.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_53 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_53 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_53 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_53 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_53 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_53_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_54 - Client Programming register for client 54.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_54 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_54 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_54 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_54 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_54 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_54_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_55 - Client Programming register for client 55.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_55 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_55 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_55 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_55 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_55 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_55_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_56 - Client Programming register for client 56.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_56 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_56 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_56 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_56 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_56 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_56_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_57 - Client Programming register for client 57.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_57 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_57 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_57 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_57 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_57 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_57_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_58 - Client Programming register for client 58.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_58 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_58 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_58 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_58 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_58 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_58_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_59 - Client Programming register for client 59.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_59 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_59 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_59 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_59 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_59 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_59_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_60 - Client Programming register for client 60.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_60 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_60 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_60 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_60 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_60 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_60_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_61 - Client Programming register for client 61.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_61 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_61 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_61 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_61 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_61 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_61_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_62 - Client Programming register for client 62.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_62 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_62 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_62 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_62 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_62 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_62_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_63 - Client Programming register for client 63.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_63 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_63 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_63 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_63 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_63 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_63_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_64 - Client Programming register for client 64.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_64 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_64 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_64 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_64 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_64 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_64_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_65 - Client Programming register for client 65.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_65 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_65 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_65 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_65 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_65 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_65_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_66 - Client Programming register for client 66.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_66 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_66 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_66 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_66 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_66 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_66_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_67 - Client Programming register for client 67.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_67 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_67 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_67 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_67 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_67 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_67_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_68 - Client Programming register for client 68.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_68 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_68 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_68 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_68 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_68 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_68_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_69 - Client Programming register for client 69.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_69 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_69 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_69 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_69 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_69 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_69_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_70 - Client Programming register for client 70.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_70 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_70 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_70 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_70 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_70 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_70_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_71 - Client Programming register for client 71.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_71 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_71 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_71 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_71 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_71 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_71_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_72 - Client Programming register for client 72.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_72 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_72 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_72 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_72 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_72 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_72_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_73 - Client Programming register for client 73.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_73 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_73 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_73 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_73 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_73 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_73_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_74 - Client Programming register for client 74.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_74 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_74 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_74 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_74 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_74 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_74_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_75 - Client Programming register for client 75.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_75 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_75 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_75 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_75 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_75 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_75_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_76 - Client Programming register for client 76.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_76 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_76 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_76 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_76 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_76 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_76_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_77 - Client Programming register for client 77.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_77 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_77 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_77 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_77 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_77 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_77_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_78 - Client Programming register for client 78.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_78 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_78 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_78 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_78 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_78 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_78_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_79 - Client Programming register for client 79.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_79 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_79 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_79 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_79 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_79 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_79_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_80 - Client Programming register for client 80.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_80 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_80 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_80 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_80 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_80 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_80_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_81 - Client Programming register for client 81.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_81 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_81 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_81 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_81 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_81 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_81_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_82 - Client Programming register for client 82.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_82 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_82 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_82 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_82 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_82 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_82_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_83 - Client Programming register for client 83.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_83 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_83 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_83 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_83 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_83 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_83_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_84 - Client Programming register for client 84.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_84 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_84 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_84 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_84 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_84 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_84_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_85 - Client Programming register for client 85.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_85 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_85 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_85 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_85 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_85 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_85_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_86 - Client Programming register for client 86.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_86 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_86 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_86 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_86 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_86 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_86_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_87 - Client Programming register for client 87.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_87 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_87 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_87 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_87 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_87 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_87_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_88 - Client Programming register for client 88.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_88 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_88 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_88 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_88 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_88 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_88_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_89 - Client Programming register for client 89.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_89 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_89 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_89 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_89 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_89 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_89_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_90 - Client Programming register for client 90.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_90 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_90 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_90 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_90 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_90 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_90_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_91 - Client Programming register for client 91.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_91 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_91 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_91 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_91 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_91 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_91_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_92 - Client Programming register for client 92.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_92 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_92 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_92 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_92 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_92 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_92_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_93 - Client Programming register for client 93.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_93 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_93 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_93 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_93 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_93 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_93_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_94 - Client Programming register for client 94.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_94 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_94 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_94 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_94 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_94 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_94_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_95 - Client Programming register for client 95.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_95 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_95 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_95 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_95 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_95 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_95_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_96 - Client Programming register for client 96.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_96 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_96 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_96 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_96 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_96 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_96_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_97 - Client Programming register for client 97.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_97 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_97 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_97 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_97 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_97 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_97_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_98 - Client Programming register for client 98.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_98 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_98 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_98 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_98 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_98 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_98_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_99 - Client Programming register for client 99.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_99 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_RR_EN_MASK                  0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_RR_EN_SHIFT                 31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_RR_EN_DEFAULT               0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_RR_EN_DISABLED              0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_RR_EN_ENABLED               1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_99 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_reserved0_MASK              0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_reserved0_SHIFT             27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_99 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_BO_VAL_MASK                 0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_BO_VAL_SHIFT                12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_BO_VAL_DEFAULT              0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_99 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_reserved1_MASK              0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_reserved1_SHIFT             7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_99 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_PR_TAG_MASK                 0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_PR_TAG_SHIFT                0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_99_PR_TAG_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_100 - Client Programming register for client 100.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_100 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_100 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_100 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_100 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_100 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_100_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_101 - Client Programming register for client 101.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_101 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_101 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_101 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_101 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_101 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_101_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_102 - Client Programming register for client 102.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_102 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_102 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_102 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_102 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_102 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_102_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_103 - Client Programming register for client 103.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_103 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_103 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_103 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_103 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_103 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_103_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_104 - Client Programming register for client 104.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_104 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_104 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_104 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_104 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_104 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_104_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_105 - Client Programming register for client 105.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_105 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_105 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_105 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_105 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_105 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_105_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_106 - Client Programming register for client 106.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_106 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_106 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_106 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_106 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_106 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_106_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_107 - Client Programming register for client 107.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_107 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_107 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_107 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_107 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_107 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_107_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_108 - Client Programming register for client 108.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_108 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_108 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_108 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_108 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_108 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_108_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_109 - Client Programming register for client 109.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_109 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_109 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_109 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_109 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_109 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_109_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_110 - Client Programming register for client 110.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_110 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_110 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_110 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_110 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_110 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_110_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_111 - Client Programming register for client 111.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_111 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_111 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_111 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_111 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_111 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_111_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_112 - Client Programming register for client 112.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_112 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_112 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_112 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_112 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_112 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_112_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_113 - Client Programming register for client 113.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_113 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_113 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_113 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_113 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_113 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_113_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_114 - Client Programming register for client 114.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_114 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_114 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_114 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_114 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_114 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_114_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_115 - Client Programming register for client 115.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_115 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_115 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_115 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_115 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_115 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_115_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_116 - Client Programming register for client 116.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_116 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_116 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_116 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_116 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_116 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_116_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_117 - Client Programming register for client 117.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_117 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_117 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_117 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_117 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_117 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_117_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_118 - Client Programming register for client 118.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_118 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_118 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_118 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_118 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_118 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_118_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_119 - Client Programming register for client 119.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_119 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_119 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_119 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_119 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_119 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_119_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_120 - Client Programming register for client 120.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_120 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_120 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_120 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_120 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_120 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_120_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_121 - Client Programming register for client 121.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_121 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_121 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_121 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_121 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_121 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_121_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_122 - Client Programming register for client 122.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_122 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_122 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_122 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_122 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_122 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_122_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_123 - Client Programming register for client 123.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_123 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_123 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_123 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_123 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_123 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_123_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_124 - Client Programming register for client 124.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_124 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_124 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_124 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_124 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_124 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_124_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_125 - Client Programming register for client 125.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_125 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_125 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_125 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_125 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_125 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_125_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_126 - Client Programming register for client 126.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_126 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_RR_EN_DEFAULT              0x00000001
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_126 :: reserved0 [30:27] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_reserved0_MASK             0x78000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_reserved0_SHIFT            27
+
+/* MEMC_ARB_1 :: CLIENT_INFO_126 :: BO_VAL [26:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_BO_VAL_MASK                0x07fff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_BO_VAL_SHIFT               12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_BO_VAL_DEFAULT             0x00000000
+
+/* MEMC_ARB_1 :: CLIENT_INFO_126 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_126 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_126_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CLIENT_INFO_127 - Client Programming register for client 127
+ ***************************************************************************/
+/* MEMC_ARB_1 :: CLIENT_INFO_127 :: RR_EN [31:31] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_RR_EN_MASK                 0x80000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_RR_EN_SHIFT                31
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_RR_EN_DEFAULT              0x00000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_RR_EN_DISABLED             0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_RR_EN_ENABLED              1
+
+/* MEMC_ARB_1 :: CLIENT_INFO_127 :: reserved0 [30:30] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_reserved0_MASK             0x40000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_reserved0_SHIFT            30
+
+/* MEMC_ARB_1 :: CLIENT_INFO_127 :: REF_CLUST [29:28] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_REF_CLUST_MASK             0x30000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_REF_CLUST_SHIFT            28
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_REF_CLUST_DEFAULT          0x00000000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_REF_CLUST_NO_CLUSTER       0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_REF_CLUST_CLUSTER_TWO      1
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_REF_CLUST_CLUSTER_FOUR     2
+
+/* MEMC_ARB_1 :: CLIENT_INFO_127 :: REF_PRD [27:12] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_REF_PRD_MASK               0x0ffff000
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_REF_PRD_SHIFT              12
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_REF_PRD_DEFAULT            0x00000818
+
+/* MEMC_ARB_1 :: CLIENT_INFO_127 :: reserved1 [11:07] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_reserved1_MASK             0x00000f80
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_reserved1_SHIFT            7
+
+/* MEMC_ARB_1 :: CLIENT_INFO_127 :: PR_TAG [06:00] */
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_PR_TAG_MASK                0x0000007f
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_PR_TAG_SHIFT               0
+#define BCHP_MEMC_ARB_1_CLIENT_INFO_127_PR_TAG_DEFAULT             0x00000000
+
+/***************************************************************************
+ *REQ_MASK_0 - Request Mask register for Clients 0 to 31
+ ***************************************************************************/
+/* MEMC_ARB_1 :: REQ_MASK_0 :: MASK [31:00] */
+#define BCHP_MEMC_ARB_1_REQ_MASK_0_MASK_MASK                       0xffffffff
+#define BCHP_MEMC_ARB_1_REQ_MASK_0_MASK_SHIFT                      0
+#define BCHP_MEMC_ARB_1_REQ_MASK_0_MASK_DEFAULT                    0x00000000
+#define BCHP_MEMC_ARB_1_REQ_MASK_0_MASK_UNMASK                     0
+
+/***************************************************************************
+ *REQ_MASK_1 - Request Mask register for Clients 32 to 63
+ ***************************************************************************/
+/* MEMC_ARB_1 :: REQ_MASK_1 :: MASK [31:00] */
+#define BCHP_MEMC_ARB_1_REQ_MASK_1_MASK_MASK                       0xffffffff
+#define BCHP_MEMC_ARB_1_REQ_MASK_1_MASK_SHIFT                      0
+#define BCHP_MEMC_ARB_1_REQ_MASK_1_MASK_DEFAULT                    0x00000000
+#define BCHP_MEMC_ARB_1_REQ_MASK_1_MASK_UNMASK                     0
+
+/***************************************************************************
+ *REQ_MASK_2 - Request Mask register for Clients 64 to 95
+ ***************************************************************************/
+/* MEMC_ARB_1 :: REQ_MASK_2 :: MASK [31:00] */
+#define BCHP_MEMC_ARB_1_REQ_MASK_2_MASK_MASK                       0xffffffff
+#define BCHP_MEMC_ARB_1_REQ_MASK_2_MASK_SHIFT                      0
+#define BCHP_MEMC_ARB_1_REQ_MASK_2_MASK_DEFAULT                    0x00000000
+#define BCHP_MEMC_ARB_1_REQ_MASK_2_MASK_UNMASK                     0
+
+/***************************************************************************
+ *REQ_MASK_3 - Request Mask register for Clients 96 to 127
+ ***************************************************************************/
+/* MEMC_ARB_1 :: REQ_MASK_3 :: MASK [31:00] */
+#define BCHP_MEMC_ARB_1_REQ_MASK_3_MASK_MASK                       0xffffffff
+#define BCHP_MEMC_ARB_1_REQ_MASK_3_MASK_SHIFT                      0
+#define BCHP_MEMC_ARB_1_REQ_MASK_3_MASK_DEFAULT                    0x00000000
+#define BCHP_MEMC_ARB_1_REQ_MASK_3_MASK_UNMASK                     0
+
+/***************************************************************************
+ *ARB_WINNER - SCB-Arbitration Winner.
+ ***************************************************************************/
+/* MEMC_ARB_1 :: ARB_WINNER :: reserved0 [31:07] */
+#define BCHP_MEMC_ARB_1_ARB_WINNER_reserved0_MASK                  0xffffff80
+#define BCHP_MEMC_ARB_1_ARB_WINNER_reserved0_SHIFT                 7
+
+/* MEMC_ARB_1 :: ARB_WINNER :: CLIENT_ID [06:00] */
+#define BCHP_MEMC_ARB_1_ARB_WINNER_CLIENT_ID_MASK                  0x0000007f
+#define BCHP_MEMC_ARB_1_ARB_WINNER_CLIENT_ID_SHIFT                 0
+#define BCHP_MEMC_ARB_1_ARB_WINNER_CLIENT_ID_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RTS_ERR_0 - RTS Deadline miss register for Clients 0 to 31
+ ***************************************************************************/
+/* MEMC_ARB_1 :: RTS_ERR_0 :: CLIENT [31:00] */
+#define BCHP_MEMC_ARB_1_RTS_ERR_0_CLIENT_MASK                      0xffffffff
+#define BCHP_MEMC_ARB_1_RTS_ERR_0_CLIENT_SHIFT                     0
+#define BCHP_MEMC_ARB_1_RTS_ERR_0_CLIENT_DEFAULT                   0x00000000
+#define BCHP_MEMC_ARB_1_RTS_ERR_0_CLIENT_UNMASK                    0
+
+/***************************************************************************
+ *RTS_ERR_1 - RTS Deadline miss register for Clients 32 to 63
+ ***************************************************************************/
+/* MEMC_ARB_1 :: RTS_ERR_1 :: CLIENT [31:00] */
+#define BCHP_MEMC_ARB_1_RTS_ERR_1_CLIENT_MASK                      0xffffffff
+#define BCHP_MEMC_ARB_1_RTS_ERR_1_CLIENT_SHIFT                     0
+#define BCHP_MEMC_ARB_1_RTS_ERR_1_CLIENT_DEFAULT                   0x00000000
+#define BCHP_MEMC_ARB_1_RTS_ERR_1_CLIENT_UNMASK                    0
+
+/***************************************************************************
+ *RTS_ERR_2 - RTS Deadline miss register for Clients 64 to 95
+ ***************************************************************************/
+/* MEMC_ARB_1 :: RTS_ERR_2 :: CLIENT [31:00] */
+#define BCHP_MEMC_ARB_1_RTS_ERR_2_CLIENT_MASK                      0xffffffff
+#define BCHP_MEMC_ARB_1_RTS_ERR_2_CLIENT_SHIFT                     0
+#define BCHP_MEMC_ARB_1_RTS_ERR_2_CLIENT_DEFAULT                   0x00000000
+#define BCHP_MEMC_ARB_1_RTS_ERR_2_CLIENT_UNMASK                    0
+
+/***************************************************************************
+ *RTS_ERR_3 - RTS Deadline miss register for Clients 96 to 127
+ ***************************************************************************/
+/* MEMC_ARB_1 :: RTS_ERR_3 :: CLIENT [31:00] */
+#define BCHP_MEMC_ARB_1_RTS_ERR_3_CLIENT_MASK                      0xffffffff
+#define BCHP_MEMC_ARB_1_RTS_ERR_3_CLIENT_SHIFT                     0
+#define BCHP_MEMC_ARB_1_RTS_ERR_3_CLIENT_DEFAULT                   0x00000000
+#define BCHP_MEMC_ARB_1_RTS_ERR_3_CLIENT_UNMASK                    0
+
+/***************************************************************************
+ *FULLNESS_THRESHOLD - Arbiter fullness threshold register
+ ***************************************************************************/
+/* MEMC_ARB_1 :: FULLNESS_THRESHOLD :: reserved0 [31:06] */
+#define BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD_reserved0_MASK          0xffffffc0
+#define BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD_reserved0_SHIFT         6
+
+/* MEMC_ARB_1 :: FULLNESS_THRESHOLD :: FULLNESS_THRESHOLD_VALUE [05:00] */
+#define BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD_FULLNESS_THRESHOLD_VALUE_MASK 0x0000003f
+#define BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD_FULLNESS_THRESHOLD_VALUE_SHIFT 0
+#define BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD_FULLNESS_THRESHOLD_VALUE_DEFAULT 0x00000005
+
+/***************************************************************************
+ *MINIMUM_COMMAND_SIZE - Minimum command size register
+ ***************************************************************************/
+/* MEMC_ARB_1 :: MINIMUM_COMMAND_SIZE :: reserved0 [31:22] */
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_reserved0_MASK        0xffc00000
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_reserved0_SHIFT       22
+
+/* MEMC_ARB_1 :: MINIMUM_COMMAND_SIZE :: MINIMUM_LMB_COMMAND_SIZE [21:16] */
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_LMB_COMMAND_SIZE_MASK 0x003f0000
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_LMB_COMMAND_SIZE_SHIFT 16
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_LMB_COMMAND_SIZE_DEFAULT 0x00000003
+
+/* MEMC_ARB_1 :: MINIMUM_COMMAND_SIZE :: reserved1 [15:14] */
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_reserved1_MASK        0x0000c000
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_reserved1_SHIFT       14
+
+/* MEMC_ARB_1 :: MINIMUM_COMMAND_SIZE :: MINIMUM_PFRI_COMMAND_SIZE [13:08] */
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_PFRI_COMMAND_SIZE_MASK 0x00003f00
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_PFRI_COMMAND_SIZE_SHIFT 8
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_PFRI_COMMAND_SIZE_DEFAULT 0x00000003
+
+/* MEMC_ARB_1 :: MINIMUM_COMMAND_SIZE :: reserved2 [07:06] */
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_reserved2_MASK        0x000000c0
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_reserved2_SHIFT       6
+
+/* MEMC_ARB_1 :: MINIMUM_COMMAND_SIZE :: MINIMUM_SCB_COMMAND_SIZE [05:00] */
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_SCB_COMMAND_SIZE_MASK 0x0000003f
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_SCB_COMMAND_SIZE_SHIFT 0
+#define BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE_MINIMUM_SCB_COMMAND_SIZE_DEFAULT 0x00000003
+
+/***************************************************************************
+ *RTS_ERR_INFO_WRITE_CLEAR - MEMC RTS_ERR_INFO write clear register
+ ***************************************************************************/
+/* MEMC_ARB_1 :: RTS_ERR_INFO_WRITE_CLEAR :: reserved0 [31:01] */
+#define BCHP_MEMC_ARB_1_RTS_ERR_INFO_WRITE_CLEAR_reserved0_MASK    0xfffffffe
+#define BCHP_MEMC_ARB_1_RTS_ERR_INFO_WRITE_CLEAR_reserved0_SHIFT   1
+
+/* MEMC_ARB_1 :: RTS_ERR_INFO_WRITE_CLEAR :: WRITE_CLEAR [00:00] */
+#define BCHP_MEMC_ARB_1_RTS_ERR_INFO_WRITE_CLEAR_WRITE_CLEAR_MASK  0x00000001
+#define BCHP_MEMC_ARB_1_RTS_ERR_INFO_WRITE_CLEAR_WRITE_CLEAR_SHIFT 0
+#define BCHP_MEMC_ARB_1_RTS_ERR_INFO_WRITE_CLEAR_WRITE_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCB_ARBITER_DEBUG_REGISTER - MEMC SCB Interface and Arbiter State Machine and FIFO Debug Register
+ ***************************************************************************/
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: reserved0 [31:30] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved0_MASK  0xc0000000
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved0_SHIFT 30
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_RD_STATE [29:28] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_RD_STATE_MASK 0x30000000
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_RD_STATE_SHIFT 28
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: reserved1 [27:26] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved1_MASK  0x0c000000
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved1_SHIFT 26
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SS_WR_STRB_STATE [25:24] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SS_WR_STRB_STATE_MASK 0x03000000
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SS_WR_STRB_STATE_SHIFT 24
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: reserved2 [23:21] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved2_MASK  0x00e00000
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved2_SHIFT 21
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_LAST_WRITE_STATE [20:20] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_LAST_WRITE_STATE_MASK 0x00100000
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_LAST_WRITE_STATE_SHIFT 20
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: reserved3 [19:17] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved3_MASK  0x000e0000
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved3_SHIFT 17
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_WR_NATIVE_WORD_STATE [16:16] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_NATIVE_WORD_STATE_MASK 0x00010000
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_NATIVE_WORD_STATE_SHIFT 16
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: reserved4 [15:14] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved4_MASK  0x0000c000
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved4_SHIFT 14
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_WR_DATA_FIFO_FULL [13:13] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_DATA_FIFO_FULL_MASK 0x00002000
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_DATA_FIFO_FULL_SHIFT 13
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_WR_DATA_FIFO_EMPTY [12:12] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_DATA_FIFO_EMPTY_MASK 0x00001000
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_DATA_FIFO_EMPTY_SHIFT 12
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_WR_MASK_FIFO_FULL [11:11] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_MASK_FIFO_FULL_MASK 0x00000800
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_MASK_FIFO_FULL_SHIFT 11
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_WR_MASK_FIFO_EMPTY [10:10] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_MASK_FIFO_EMPTY_MASK 0x00000400
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_WR_MASK_FIFO_EMPTY_SHIFT 10
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_CMD_FIFO_FULL [09:09] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_CMD_FIFO_FULL_MASK 0x00000200
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_CMD_FIFO_FULL_SHIFT 9
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: SCB_CMD_FIFO_EMPTY [08:08] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_CMD_FIFO_EMPTY_MASK 0x00000100
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_SCB_CMD_FIFO_EMPTY_SHIFT 8
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: reserved5 [07:03] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved5_MASK  0x000000f8
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_reserved5_SHIFT 3
+
+/* MEMC_ARB_1 :: SCB_ARBITER_DEBUG_REGISTER :: ARB_STATE [02:00] */
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_ARB_STATE_MASK  0x00000007
+#define BCHP_MEMC_ARB_1_SCB_ARBITER_DEBUG_REGISTER_ARB_STATE_SHIFT 0
+
+/***************************************************************************
+ *SPARE_1 - Spare Register 1 .
+ ***************************************************************************/
+/* MEMC_ARB_1 :: SPARE_1 :: SPARE [31:03] */
+#define BCHP_MEMC_ARB_1_SPARE_1_SPARE_MASK                         0xfffffff8
+#define BCHP_MEMC_ARB_1_SPARE_1_SPARE_SHIFT                        3
+#define BCHP_MEMC_ARB_1_SPARE_1_SPARE_DEFAULT                      0x00000000
+
+/* MEMC_ARB_1 :: SPARE_1 :: LMB_PREA_FIX_ENABLE [02:02] */
+#define BCHP_MEMC_ARB_1_SPARE_1_LMB_PREA_FIX_ENABLE_MASK           0x00000004
+#define BCHP_MEMC_ARB_1_SPARE_1_LMB_PREA_FIX_ENABLE_SHIFT          2
+#define BCHP_MEMC_ARB_1_SPARE_1_LMB_PREA_FIX_ENABLE_DEFAULT        0x00000001
+
+/* MEMC_ARB_1 :: SPARE_1 :: FULLNESS_UPDATE_FIX_DISABLE [01:00] */
+#define BCHP_MEMC_ARB_1_SPARE_1_FULLNESS_UPDATE_FIX_DISABLE_MASK   0x00000003
+#define BCHP_MEMC_ARB_1_SPARE_1_FULLNESS_UPDATE_FIX_DISABLE_SHIFT  0
+#define BCHP_MEMC_ARB_1_SPARE_1_FULLNESS_UPDATE_FIX_DISABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE_2 - Spare Register 2 .
+ ***************************************************************************/
+/* MEMC_ARB_1 :: SPARE_2 :: SPARE [31:03] */
+#define BCHP_MEMC_ARB_1_SPARE_2_SPARE_MASK                         0xfffffff8
+#define BCHP_MEMC_ARB_1_SPARE_2_SPARE_SHIFT                        3
+#define BCHP_MEMC_ARB_1_SPARE_2_SPARE_DEFAULT                      0x00000000
+
+/* MEMC_ARB_1 :: SPARE_2 :: LMB_PREA_FIX_ENABLE [02:02] */
+#define BCHP_MEMC_ARB_1_SPARE_2_LMB_PREA_FIX_ENABLE_MASK           0x00000004
+#define BCHP_MEMC_ARB_1_SPARE_2_LMB_PREA_FIX_ENABLE_SHIFT          2
+#define BCHP_MEMC_ARB_1_SPARE_2_LMB_PREA_FIX_ENABLE_DEFAULT        0x00000001
+
+/* MEMC_ARB_1 :: SPARE_2 :: FULLNESS_UPDATE_FIX_DISABLE [01:00] */
+#define BCHP_MEMC_ARB_1_SPARE_2_FULLNESS_UPDATE_FIX_DISABLE_MASK   0x00000003
+#define BCHP_MEMC_ARB_1_SPARE_2_FULLNESS_UPDATE_FIX_DISABLE_SHIFT  0
+#define BCHP_MEMC_ARB_1_SPARE_2_FULLNESS_UPDATE_FIX_DISABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE_RO_1 - Read only Spare Register 1 .
+ ***************************************************************************/
+/* MEMC_ARB_1 :: SPARE_RO_1 :: SPARE_RO [31:00] */
+#define BCHP_MEMC_ARB_1_SPARE_RO_1_SPARE_RO_MASK                   0xffffffff
+#define BCHP_MEMC_ARB_1_SPARE_RO_1_SPARE_RO_SHIFT                  0
+#define BCHP_MEMC_ARB_1_SPARE_RO_1_SPARE_RO_DEFAULT                0x00000000
+
+/***************************************************************************
+ *SPARE_RO_2 - Read only Spare Register 2 .
+ ***************************************************************************/
+/* MEMC_ARB_1 :: SPARE_RO_2 :: SPARE_RO [31:00] */
+#define BCHP_MEMC_ARB_1_SPARE_RO_2_SPARE_RO_MASK                   0xffffffff
+#define BCHP_MEMC_ARB_1_SPARE_RO_2_SPARE_RO_SHIFT                  0
+#define BCHP_MEMC_ARB_1_SPARE_RO_2_SPARE_RO_DEFAULT                0x00000000
+
+#endif /* #ifndef BCHP_MEMC_ARB_1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_memc_ddr23_shim_addr_cntl_0.h b/include/linux/brcmstb/7435b0/bchp_memc_ddr23_shim_addr_cntl_0.h
new file mode 100644
index 0000000..43d4dcf
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_memc_ddr23_shim_addr_cntl_0.h
@@ -0,0 +1,1078 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 19:01:27 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_memc_ddr23_shim_addr_cntl_0.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 3:03p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_H__
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_H__
+
+/***************************************************************************
+ *MEMC_DDR23_SHIM_ADDR_CNTL_0 - DDR23 SHIM Control Registers 0
+ ***************************************************************************/
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG  0x003b8000 /* DDR23_SHIM Config register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID 0x003b8004 /* DDR23_SHIM Revision ID Register. */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET   0x003b8008 /* DDR soft reset register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG 0x003b8038 /* ODT Configuration register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL 0x003b8044 /* DDR PHY USE DYN VDL Control register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING 0x003b8048 /* DDR PHY Idle power saving Control register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT 0x003b804c /* DDR PHY standby exit register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL 0x003b806c /* Analog macro register bypass control */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL 0x003b8070 /* DDR PLL external clock select register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_TEST_MODE_CNTRL_REG 0x003b8074 /* DDR23_SHIM testport control register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL 0x003b807c /* DDR bypass pll mode disable register. */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL 0x003b8088 /* DDR VECTOR PLL bypass mode clock select */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL 0x003b808c /* DDR Pad control register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE 0x003b8098 /* CLK_667_ENABLE Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS 0x003b809c /* DDR23_SHIM Status Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO 0x003b8028 /* Command and Data FIFO Status Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH 0x003b802c /* Read Datapath Status Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_FLAG_BUS 0x003b8030 /* TP_OUT bus value Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC    0x003b8034 /* Miscellaneous Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RW 0x003b80a4 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RW 0x003b80a8 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RO 0x003b80ac /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RO 0x003b80b0 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL 0x003b80b4 /* FORCE_DDR3_RESET Deassert  Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS 0x003b80b8 /* SYS PLL P and N Divider Controls */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN 0x003b80bc /* SYS PLL Gain Controls */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL 0x003b80c0 /* SYS PLL Control Vector */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP 0x003b80c4 /* SSC Step Size for all 6-chan PLLs */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT 0x003b80c8 /* SSC Limit for all 6-chan PLLs */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0 0x003b80cc /* SYS PLL M Divider Controls for Channel0 */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX 0x003b80d0 /* SYS PLL M Divider Controls for Extra Unused Channels */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT 0x003b80d4 /* SYS PLL Status */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel 0x003b80d8 /* SYS PLL power-down and reference clock selection */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET 0x003b80dc /* SYS PLL Reset and post-resetb selcection */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR 0x003b80e0 /* SYS PLL control and SR selcection */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK 0x003b80e4 /* Shim to PHY gated bypass_clock selection */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG0 0x003b80e8 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG1 0x003b80ec /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG2 0x003b80f0 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG3 0x003b80f4 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG4 0x003b80f8 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG5 0x003b80fc /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG6 0x003b8100 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG7 0x003b8104 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG8 0x003b8108 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG9 0x003b810c /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG10 0x003b8110 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG11 0x003b8114 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG12 0x003b8118 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG13 0x003b811c /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG14 0x003b8120 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG15 0x003b8124 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY 0x003b8128 /* Delay on phy_dyn_vdl to the PHY */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_0 0x003b812c /* DDR PHY data storage register 0 */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_1 0x003b8130 /* DDR PHY data storage register 0 */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_2 0x003b8134 /* DDR PHY data storage register 0 */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_3 0x003b8138 /* DDR PHY data storage register 0 */
+
+/***************************************************************************
+ *CONFIG - DDR23_SHIM Config register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: reserved0 [31:27] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_reserved0_MASK     0xf8000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_reserved0_SHIFT    27
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: LAST_RD_STRETCH [26:26] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_RD_STRETCH_MASK 0x04000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_RD_STRETCH_SHIFT 26
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_RD_STRETCH_DEFAULT 0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: ODT_LATENCY [25:21] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_ODT_LATENCY_MASK   0x03e00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_ODT_LATENCY_SHIFT  21
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_ODT_LATENCY_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: LAST_READ_LATENCY [20:15] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_READ_LATENCY_MASK 0x001f8000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_READ_LATENCY_SHIFT 15
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_READ_LATENCY_DEFAULT 0x0000000b
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: READ_LATENCY [14:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_READ_LATENCY_MASK  0x00007f00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_READ_LATENCY_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_READ_LATENCY_DEFAULT 0x00000007
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: WRITE_LATENCY [07:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_WRITE_LATENCY_MASK 0x000000f8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_WRITE_LATENCY_SHIFT 3
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_WRITE_LATENCY_DEFAULT 0x0000000e
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: DRAM_WIDTH [02:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DRAM_WIDTH_MASK    0x00000006
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DRAM_WIDTH_SHIFT   1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DRAM_WIDTH_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: DDR_MODE [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DDR_MODE_MASK      0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DDR_MODE_SHIFT     0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DDR_MODE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *DDR23_SHIM_REV_ID - DDR23_SHIM Revision ID Register.
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_REV_ID :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_reserved0_MASK 0xffff0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_reserved0_SHIFT 16
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_REV_ID :: MAJOR_ID [15:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MAJOR_ID_MASK 0x0000ff00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MAJOR_ID_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MAJOR_ID_DEFAULT 0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_REV_ID :: MINOR_ID [07:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MINOR_ID_MASK 0x000000ff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MINOR_ID_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MINOR_ID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET - DDR soft reset register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RESET :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_reserved0_MASK      0xfffffff8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_reserved0_SHIFT     3
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RESET :: DATAPATH_216_RESET [02:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_216_RESET_MASK 0x00000004
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_216_RESET_SHIFT 2
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_216_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RESET :: DATAPATH_DDR_RESET [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_DDR_RESET_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_DDR_RESET_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_DDR_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RESET :: PHY_PWRUP_RSB [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_PHY_PWRUP_RSB_MASK  0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_PHY_PWRUP_RSB_SHIFT 0
+
+/***************************************************************************
+ *ODT_CONFIG - ODT Configuration register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_reserved0_MASK 0xffff0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_reserved0_SHIFT 16
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: ODT_TIE_HIGH [15:15] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_TIE_HIGH_MASK 0x00008000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_TIE_HIGH_SHIFT 15
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_TIE_HIGH_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: ODT_ENABLE [14:14] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_ENABLE_MASK 0x00004000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_ENABLE_SHIFT 14
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_ENABLE_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: STRETCH [13:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_STRETCH_MASK   0x00003800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_STRETCH_SHIFT  11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_STRETCH_DEFAULT 0x00000003
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: EARLY [10:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_EARLY_MASK     0x000007c0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_EARLY_SHIFT    6
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_EARLY_DEFAULT  0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: DELAY [05:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_DELAY_MASK     0x0000003f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_DELAY_SHIFT    0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_DELAY_DEFAULT  0x00000002
+
+/***************************************************************************
+ *PHY_USE_DYN_VDL - DDR PHY USE DYN VDL Control register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_USE_DYN_VDL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_USE_DYN_VDL :: DISABLE [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL_DISABLE_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL_DISABLE_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL_DISABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_POWER_SAVING - DDR PHY Idle power saving Control register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: reserved0 [31:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_reserved0_MASK 0xffffffc0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_reserved0_SHIFT 6
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: PhyAddrCntl [05:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_PhyAddrCntl_MASK 0x00000030
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_PhyAddrCntl_SHIFT 4
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_PhyAddrCntl_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane3 [03:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane3_MASK 0x00000008
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane3_SHIFT 3
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane3_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane2 [02:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane2_MASK 0x00000004
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane2_SHIFT 2
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane2_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane1 [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane1_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane1_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane1_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane0 [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane0_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHY_STANDBY_EXIT - DDR PHY standby exit register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_STANDBY_EXIT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_STANDBY_EXIT :: ENABLE [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT_ENABLE_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT_ENABLE_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *ANALOG_BYPASS_CNTRL - Analog macro register bypass control
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ANALOG_BYPASS_CNTRL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ANALOG_BYPASS_CNTRL :: BYPASS_PLL [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_BYPASS_PLL_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_BYPASS_PLL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_BYPASS_PLL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DDR_PLL_EXT_CLKSEL - DDR PLL external clock select register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PLL_EXT_CLKSEL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PLL_EXT_CLKSEL :: EXT_CLK_SEL [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TEST_MODE_CNTRL_REG - DDR23_SHIM testport control register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: TEST_MODE_CNTRL_REG :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_TEST_MODE_CNTRL_REG_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_TEST_MODE_CNTRL_REG_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_TEST_MODE_CNTRL_REG_reserved_for_eco0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DISABLE_CHIP_BYPASS_PLL - DDR bypass pll mode disable register.
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DISABLE_CHIP_BYPASS_PLL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DISABLE_CHIP_BYPASS_PLL :: DISABLE_BYPASS_PLL [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VECTOR_MODE_CLK_SEL - DDR VECTOR PLL bypass mode clock select
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: VECTOR_MODE_CLK_SEL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: VECTOR_MODE_CLK_SEL :: SEL [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_SEL_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_SEL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DDR_PAD_CNTRL - DDR Pad control register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_reserved0_MASK 0xffffff80
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_reserved0_SHIFT 7
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: IDDQ_MODE_ON_SELFREF [06:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK 0x00000040
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_SHIFT 6
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: PHY_IDLE_ENABLE [05:05] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_MASK 0x00000020
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_SHIFT 5
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: HIZ_ON_SELFREF [04:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_HIZ_ON_SELFREF_MASK 0x00000010
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_HIZ_ON_SELFREF_SHIFT 4
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_HIZ_ON_SELFREF_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: CNTRL [03:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_CNTRL_MASK  0x0000000f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_CNTRL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_CNTRL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CLK_GATE - CLK_667_ENABLE Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CLK_GATE :: UNUSED [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_UNUSED_MASK      0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_UNUSED_SHIFT     1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_UNUSED_DEFAULT   0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CLK_GATE :: CLK_667_ENABLE [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_CLK_667_ENABLE_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_CLK_667_ENABLE_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_CLK_667_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DDR23_SHIM_STATUS - DDR23_SHIM Status Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_STATUS :: reserved0 [31:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_reserved0_SHIFT 4
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_STATUS :: BL0_AND_BL1_RDY_SLIP [03:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL0_AND_BL1_RDY_SLIP_MASK 0x00000008
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL0_AND_BL1_RDY_SLIP_SHIFT 3
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_STATUS :: BL0_RDY_SLIP [02:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL0_RDY_SLIP_MASK 0x00000004
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL0_RDY_SLIP_SHIFT 2
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_STATUS :: BL1_RDY_SLIP [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL1_RDY_SLIP_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL1_RDY_SLIP_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_STATUS :: READY [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_READY_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_READY_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_READY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CMD_DATA_FIFO - Command and Data FIFO Status Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: reserved0 [31:26] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_reserved0_MASK 0xfc000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_reserved0_SHIFT 26
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: FIFO_FULL [25:25] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_FULL_MASK 0x02000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_FULL_SHIFT 25
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: FIFO_EMPTY [24:24] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_EMPTY_MASK 0x01000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_EMPTY_SHIFT 24
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: reserved1 [23:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_reserved1_MASK 0x00ffff00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_reserved1_SHIFT 8
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: WR_PNTR [07:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_WR_PNTR_MASK 0x000000f0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_WR_PNTR_SHIFT 4
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: RD_PNTR [03:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_RD_PNTR_MASK 0x0000000f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_RD_PNTR_SHIFT 0
+
+/***************************************************************************
+ *RD_DATAPATH - Read Datapath Status Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: reserved0 [31:28] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_reserved0_MASK 0xf0000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_reserved0_SHIFT 28
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: F_RDY_3 [27:27] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_3_MASK  0x08000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_3_SHIFT 27
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: F_RDY_2 [26:26] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_2_MASK  0x04000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_2_SHIFT 26
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: F_RDY_1 [25:25] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_1_MASK  0x02000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_1_SHIFT 25
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: F_RDY_0 [24:24] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_0_MASK  0x01000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_0_SHIFT 24
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: DWORD3_CNT [23:20] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD3_CNT_MASK 0x00f00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD3_CNT_SHIFT 20
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: DWORD2_CNT [19:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD2_CNT_MASK 0x000f0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD2_CNT_SHIFT 16
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: DWORD1_CNT [15:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD1_CNT_MASK 0x0000f000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD1_CNT_SHIFT 12
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: DWORD0_CNT [11:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD0_CNT_MASK 0x00000f00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD0_CNT_SHIFT 8
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: WR_PNTR [07:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_WR_PNTR_MASK  0x000000f0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_WR_PNTR_SHIFT 4
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: RD_PNTR [03:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_RD_PNTR_MASK  0x0000000f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_RD_PNTR_SHIFT 0
+
+/***************************************************************************
+ *FLAG_BUS - TP_OUT bus value Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: FLAG_BUS :: FLAG_BUS [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_FLAG_BUS_FLAG_BUS_MASK    0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_FLAG_BUS_FLAG_BUS_SHIFT   0
+
+/***************************************************************************
+ *MISC - Miscellaneous Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: reserved_for_eco0 [31:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_reserved_for_eco0_MASK 0xfffff000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_reserved_for_eco0_SHIFT 12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_reserved_for_eco0_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: BL0_AND_BL1_RDY_SLIP_CLR [11:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_AND_BL1_RDY_SLIP_CLR_MASK 0x00000800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_AND_BL1_RDY_SLIP_CLR_SHIFT 11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_AND_BL1_RDY_SLIP_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: BL0_RDY_SLIP_CLR [10:10] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_RDY_SLIP_CLR_MASK 0x00000400
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_RDY_SLIP_CLR_SHIFT 10
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_RDY_SLIP_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: BL1_RDY_SLIP_CLR [09:09] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL1_RDY_SLIP_CLR_MASK 0x00000200
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL1_RDY_SLIP_CLR_SHIFT 9
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL1_RDY_SLIP_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: FUNC1 [08:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC1_MASK           0x00000100
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC1_SHIFT          8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC1_DEFAULT        0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: FUNC0 [07:07] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC0_MASK           0x00000080
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC0_SHIFT          7
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC0_DEFAULT        0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: C2IO_INIT_RDY_OVR [06:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_C2IO_INIT_RDY_OVR_MASK 0x00000040
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_C2IO_INIT_RDY_OVR_SHIFT 6
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_C2IO_INIT_RDY_OVR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: RD_FIFO_HOLD_CLR [05:05] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_RD_FIFO_HOLD_CLR_MASK 0x00000020
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_RD_FIFO_HOLD_CLR_SHIFT 5
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_RD_FIFO_HOLD_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: CMD_FIFO_HOLD_CLR [04:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_CMD_FIFO_HOLD_CLR_MASK 0x00000010
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_CMD_FIFO_HOLD_CLR_SHIFT 4
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_CMD_FIFO_HOLD_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: DWORD3_OVERRUN_CLR [03:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD3_OVERRUN_CLR_MASK 0x00000008
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD3_OVERRUN_CLR_SHIFT 3
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD3_OVERRUN_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: DWORD2_OVERRUN_CLR [02:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD2_OVERRUN_CLR_MASK 0x00000004
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD2_OVERRUN_CLR_SHIFT 2
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD2_OVERRUN_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: DWORD1_OVERRUN_CLR [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD1_OVERRUN_CLR_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD1_OVERRUN_CLR_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD1_OVERRUN_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: DWORD0_OVERRUN_CLR [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD0_OVERRUN_CLR_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD0_OVERRUN_CLR_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD0_OVERRUN_CLR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE0_RW - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SPARE0_RW :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RW_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RW_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RW_reserved_for_eco0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE1_RW - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SPARE1_RW :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RW_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RW_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RW_reserved_for_eco0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE0_RO - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SPARE0_RO :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RO_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RO_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RO_reserved_for_eco0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE1_RO - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SPARE1_RO :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RO_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RO_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RO_reserved_for_eco0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DDR3_RESET_CNTRL - FORCE_DDR3_RESET Deassert  Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR3_RESET_CNTRL :: UNUSED [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_UNUSED_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_UNUSED_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_UNUSED_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR3_RESET_CNTRL :: FORCE_DDR3_RESET [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PLL6CH_PNDIV_SYS - SYS PLL P and N Divider Controls
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PLL6CH_PNDIV_SYS :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_reserved0_MASK 0x80000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_reserved0_SHIFT 31
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PLL6CH_PNDIV_SYS :: PDIV [30:28] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_PDIV_MASK 0x70000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_PDIV_SHIFT 28
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_PDIV_DEFAULT 0x00000002
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PLL6CH_PNDIV_SYS :: NDIV_INT [27:20] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_INT_MASK 0x0ff00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_INT_SHIFT 20
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_INT_DEFAULT 0x0000004e
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PLL6CH_PNDIV_SYS :: NDIV_FRAC [19:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_FRAC_MASK 0x000fffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_FRAC_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_FRAC_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_PLL_GAIN - SYS PLL Gain Controls
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: reserved0 [31:23] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_reserved0_MASK 0xff800000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_reserved0_SHIFT 23
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: FB_PHASE_ENA [22:22] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_ENA_MASK 0x00400000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_ENA_SHIFT 22
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_ENA_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: FB_PHASE_OFFSET [21:10] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_OFFSET_MASK 0x003ffc00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_OFFSET_SHIFT 10
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_OFFSET_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: KP [09:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KP_MASK      0x000003c0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KP_SHIFT     6
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KP_DEFAULT   0x00000008
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: KI [05:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KI_MASK      0x00000038
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KI_SHIFT     3
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KI_DEFAULT   0x00000003
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: KA [02:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KA_MASK      0x00000007
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KA_SHIFT     0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KA_DEFAULT   0x00000001
+
+/***************************************************************************
+ *SYS_PLL_CTRL - SYS PLL Control Vector
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: reserved0 [31:23] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_reserved0_MASK 0xff800000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_reserved0_SHIFT 23
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: ENA_8PHASE [22:22] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_8PHASE_MASK 0x00400000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_8PHASE_SHIFT 22
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_8PHASE_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: ENA_SSC [21:21] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_SSC_MASK 0x00200000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_SSC_SHIFT 21
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_SSC_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: VCO_DIV2_EN [20:20] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_VCO_DIV2_EN_MASK 0x00100000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_VCO_DIV2_EN_SHIFT 20
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_VCO_DIV2_EN_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: AUX_CTRL [19:19] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_AUX_CTRL_MASK 0x00080000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_AUX_CTRL_SHIFT 19
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_AUX_CTRL_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: REFCLK_OUT [18:18] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_REFCLK_OUT_MASK 0x00040000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_REFCLK_OUT_SHIFT 18
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_REFCLK_OUT_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: STAT_UPDATE [17:17] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_UPDATE_MASK 0x00020000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_UPDATE_SHIFT 17
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_UPDATE_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: STAT_SELECT [16:14] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_SELECT_MASK 0x0001c000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_SELECT_SHIFT 14
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_SELECT_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: STAT_RESET [13:13] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_RESET_MASK 0x00002000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_RESET_SHIFT 13
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: DCO_CTRL_BYPASS_ENA [12:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_ENA_MASK 0x00001000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_ENA_SHIFT 12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_ENA_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_MASK 0x00000fff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SSC_STEP - SSC Step Size for all 6-chan PLLs
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SSC_STEP :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP_reserved0_MASK   0xffff0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP_reserved0_SHIFT  16
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SSC_STEP :: SSC_STEP [15:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP_SSC_STEP_MASK    0x0000ffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP_SSC_STEP_SHIFT   0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SSC_LIMIT - SSC Limit for all 6-chan PLLs
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SSC_LIMIT :: reserved0 [31:22] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT_reserved0_MASK  0xffc00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT_reserved0_SHIFT 22
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SSC_LIMIT :: SSC_LIMIT [21:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT_SSC_LIMIT_MASK  0x003fffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT_SSC_LIMIT_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_PLL_MDIV0 - SYS PLL M Divider Controls for Channel0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: reserved0 [31:14] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_reserved0_MASK 0xffffc000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_reserved0_SHIFT 14
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: CHAN_HOLD_OUTPUT [13:13] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_HOLD_OUTPUT_MASK 0x00002000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_HOLD_OUTPUT_SHIFT 13
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_HOLD_OUTPUT_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: CHAN_LOAD_MDIV [12:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_LOAD_MDIV_MASK 0x00001000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_LOAD_MDIV_SHIFT 12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_LOAD_MDIV_DEFAULT 0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: CHAN_ENA [11:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_ENA_MASK 0x00000800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_ENA_SHIFT 11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_ENA_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: CHAN_MDEL [10:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDEL_MASK 0x00000700
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDEL_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDEL_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: CHAN_MDIV [07:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDIV_MASK 0x000000ff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDIV_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDIV_DEFAULT 0x00000008
+
+/***************************************************************************
+ *SYS_PLL_MDIVX - SYS PLL M Divider Controls for Extra Unused Channels
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: reserved0 [31:14] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_reserved0_MASK 0xffffc000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_reserved0_SHIFT 14
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: CHAN_HOLD_OUTPUT [13:13] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_HOLD_OUTPUT_MASK 0x00002000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_HOLD_OUTPUT_SHIFT 13
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_HOLD_OUTPUT_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: CHAN_LOAD_MDIV [12:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_LOAD_MDIV_MASK 0x00001000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_LOAD_MDIV_SHIFT 12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_LOAD_MDIV_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: CHAN_ENA [11:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_ENA_MASK 0x00000800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_ENA_SHIFT 11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_ENA_DEFAULT 0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: CHAN_MDEL [10:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDEL_MASK 0x00000700
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDEL_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDEL_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: CHAN_MDIV [07:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDIV_MASK 0x000000ff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDIV_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDIV_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_PLL_STAT - SYS PLL Status
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_STAT :: reserved0 [31:25] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_reserved0_MASK 0xfe000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_reserved0_SHIFT 25
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_STAT :: DEBUG_OUTPUT [24:13] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_DEBUG_OUTPUT_MASK 0x01ffe000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_DEBUG_OUTPUT_SHIFT 13
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_DEBUG_OUTPUT_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_STAT :: LOCK [12:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_LOCK_MASK    0x00001000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_LOCK_SHIFT   12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_LOCK_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_STAT :: UNLOCK_COUNT [11:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_UNLOCK_COUNT_MASK 0x00000fff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_UNLOCK_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_UNLOCK_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_PLL_PWRDN_ref_clk_sel - SYS PLL power-down and reference clock selection
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_PWRDN_ref_clk_sel :: reserved0 [31:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_reserved0_MASK 0xfffffffc
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_reserved0_SHIFT 2
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_PWRDN_ref_clk_sel :: REFCLK_SEL [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_REFCLK_SEL_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_REFCLK_SEL_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_REFCLK_SEL_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_PWRDN_ref_clk_sel :: PWRDN [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_PWRDN_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_PWRDN_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_PWRDN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_PLL_RESET_POST_RESET - SYS PLL Reset and post-resetb selcection
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_RESET_POST_RESET :: reserved0 [31:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_reserved0_MASK 0xfffffffc
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_reserved0_SHIFT 2
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_RESET_POST_RESET :: POST_RESETB [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_POST_RESETB_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_POST_RESETB_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_POST_RESETB_DEFAULT 0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_RESET_POST_RESET :: GLOBAL_RESETB [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_GLOBAL_RESETB_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_GLOBAL_RESETB_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_GLOBAL_RESETB_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SYS_PLL_CTRL_SR - SYS PLL control and SR selcection
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL_SR :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_reserved0_MASK 0xe0000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_reserved0_SHIFT 29
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL_SR :: PLL_SR [28:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_SR_MASK 0x1ffff800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_SR_SHIFT 11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_SR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL_SR :: PLL_CTRL_1 [10:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_CTRL_1_MASK 0x000007fc
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_CTRL_1_SHIFT 2
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_CTRL_1_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL_SR :: NDIV_INT_1 [01:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_NDIV_INT_1_MASK 0x00000003
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_NDIV_INT_1_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_NDIV_INT_1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SHIM_TO_PHY_GATED_BYPASS_CLK - Shim to PHY gated bypass_clock selection
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SHIM_TO_PHY_GATED_BYPASS_CLK :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SHIM_TO_PHY_GATED_BYPASS_CLK :: BYPASS_CLK_GATED_TO_SHIM_PHY [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK_BYPASS_CLK_GATED_TO_SHIM_PHY_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK_BYPASS_CLK_GATED_TO_SHIM_PHY_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK_BYPASS_CLK_GATED_TO_SHIM_PHY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG0 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG0 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG0_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG0_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG0_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG1 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG1 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG1_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG1_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG1_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG2 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG2 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG2_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG2_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG2_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG3 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG3 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG3_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG3_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG3_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG4 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG4 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG4_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG4_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG4_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG5 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG5 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG5_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG5_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG5_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG6 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG6 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG6_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG6_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG6_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG7 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG7 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG7_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG7_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG7_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG8 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG8 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG8_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG8_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG8_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG9 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG9 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG9_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG9_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG9_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG10 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG10 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG10_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG10_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG10_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG11 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG11 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG11_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG11_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG11_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG12 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG12 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG12_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG12_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG12_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG13 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG13 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG13_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG13_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG13_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG14 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG14 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG14_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG14_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG14_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG15 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG15 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG15_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG15_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG15_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHY_DYN_VDL_DLY - Delay on phy_dyn_vdl to the PHY
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: reserved0 [31:28] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved0_MASK 0xf0000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved0_SHIFT 28
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: DYN_VDL_DEASSERT_TO_READ_ENB_DLY [27:24] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_READ_ENB_DLY_MASK 0x0f000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_READ_ENB_DLY_SHIFT 24
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_READ_ENB_DLY_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: reserved1 [23:20] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved1_MASK 0x00f00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved1_SHIFT 20
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: DYN_VDL_ASSERT_TO_READ_ENB_DLY [19:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_READ_ENB_DLY_MASK 0x000f0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_READ_ENB_DLY_SHIFT 16
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_READ_ENB_DLY_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: reserved2 [15:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved2_MASK 0x0000f000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved2_SHIFT 12
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: DYN_VDL_DEASSERT_TO_WR_VALID_DLY [11:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_WR_VALID_DLY_MASK 0x00000f00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_WR_VALID_DLY_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_WR_VALID_DLY_DEFAULT 0x00000002
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: reserved3 [07:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved3_MASK 0x000000f0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved3_SHIFT 4
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: DYN_VDL_ASSERT_TO_WR_VALID_DLY [03:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_WR_VALID_DLY_MASK 0x0000000f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_WR_VALID_DLY_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_WR_VALID_DLY_DEFAULT 0x00000002
+
+/***************************************************************************
+ *AON_STORAGE_IN_PHY_0 - DDR PHY data storage register 0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: AON_STORAGE_IN_PHY_0 :: DTATA [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_0_DTATA_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_0_DTATA_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_0_DTATA_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AON_STORAGE_IN_PHY_1 - DDR PHY data storage register 0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: AON_STORAGE_IN_PHY_1 :: DTATA [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_1_DTATA_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_1_DTATA_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_1_DTATA_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AON_STORAGE_IN_PHY_2 - DDR PHY data storage register 0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: AON_STORAGE_IN_PHY_2 :: DTATA [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_2_DTATA_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_2_DTATA_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_2_DTATA_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AON_STORAGE_IN_PHY_3 - DDR PHY data storage register 0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: AON_STORAGE_IN_PHY_3 :: DTATA [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_3_DTATA_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_3_DTATA_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_3_DTATA_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_memc_ddr23_shim_addr_cntl_1.h b/include/linux/brcmstb/7435b0/bchp_memc_ddr23_shim_addr_cntl_1.h
new file mode 100644
index 0000000..b81293c
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_memc_ddr23_shim_addr_cntl_1.h
@@ -0,0 +1,1078 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 19:01:51 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_memc_ddr23_shim_addr_cntl_1.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 3:04p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_H__
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_H__
+
+/***************************************************************************
+ *MEMC_DDR23_SHIM_ADDR_CNTL_1 - DDR23 SHIM Control Registers 1
+ ***************************************************************************/
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG  0x003c8000 /* DDR23_SHIM Config register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_REV_ID 0x003c8004 /* DDR23_SHIM Revision ID Register. */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RESET   0x003c8008 /* DDR soft reset register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG 0x003c8038 /* ODT Configuration register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_USE_DYN_VDL 0x003c8044 /* DDR PHY USE DYN VDL Control register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING 0x003c8048 /* DDR PHY Idle power saving Control register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_STANDBY_EXIT 0x003c804c /* DDR PHY standby exit register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ANALOG_BYPASS_CNTRL 0x003c806c /* Analog macro register bypass control */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PLL_EXT_CLKSEL 0x003c8070 /* DDR PLL external clock select register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_TEST_MODE_CNTRL_REG 0x003c8074 /* DDR23_SHIM testport control register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DISABLE_CHIP_BYPASS_PLL 0x003c807c /* DDR bypass pll mode disable register. */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_VECTOR_MODE_CLK_SEL 0x003c8088 /* DDR VECTOR PLL bypass mode clock select */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL 0x003c808c /* DDR Pad control register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CLK_GATE 0x003c8098 /* CLK_667_ENABLE Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS 0x003c809c /* DDR23_SHIM Status Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO 0x003c8028 /* Command and Data FIFO Status Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH 0x003c802c /* Read Datapath Status Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_FLAG_BUS 0x003c8030 /* TP_OUT bus value Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC    0x003c8034 /* Miscellaneous Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE0_RW 0x003c80a4 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE1_RW 0x003c80a8 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE0_RO 0x003c80ac /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE1_RO 0x003c80b0 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR3_RESET_CNTRL 0x003c80b4 /* FORCE_DDR3_RESET Deassert  Register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS 0x003c80b8 /* SYS PLL P and N Divider Controls */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN 0x003c80bc /* SYS PLL Gain Controls */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL 0x003c80c0 /* SYS PLL Control Vector */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_STEP 0x003c80c4 /* SSC Step Size for all 6-chan PLLs */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_LIMIT 0x003c80c8 /* SSC Limit for all 6-chan PLLs */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0 0x003c80cc /* SYS PLL M Divider Controls for Channel0 */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX 0x003c80d0 /* SYS PLL M Divider Controls for Extra Unused Channels */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT 0x003c80d4 /* SYS PLL Status */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel 0x003c80d8 /* SYS PLL power-down and reference clock selection */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_RESET_POST_RESET 0x003c80dc /* SYS PLL Reset and post-resetb selcection */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR 0x003c80e0 /* SYS PLL control and SR selcection */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SHIM_TO_PHY_GATED_BYPASS_CLK 0x003c80e4 /* Shim to PHY gated bypass_clock selection */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG0 0x003c80e8 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG1 0x003c80ec /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG2 0x003c80f0 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG3 0x003c80f4 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG4 0x003c80f8 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG5 0x003c80fc /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG6 0x003c8100 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG7 0x003c8104 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG8 0x003c8108 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG9 0x003c810c /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG10 0x003c8110 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG11 0x003c8114 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG12 0x003c8118 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG13 0x003c811c /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG14 0x003c8120 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG15 0x003c8124 /* Spare register */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY 0x003c8128 /* Delay on phy_dyn_vdl to the PHY */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_0 0x003c812c /* DDR PHY data storage register 0 */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_1 0x003c8130 /* DDR PHY data storage register 0 */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_2 0x003c8134 /* DDR PHY data storage register 0 */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_3 0x003c8138 /* DDR PHY data storage register 0 */
+
+/***************************************************************************
+ *CONFIG - DDR23_SHIM Config register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CONFIG :: reserved0 [31:27] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_reserved0_MASK     0xf8000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_reserved0_SHIFT    27
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CONFIG :: LAST_RD_STRETCH [26:26] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_LAST_RD_STRETCH_MASK 0x04000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_LAST_RD_STRETCH_SHIFT 26
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_LAST_RD_STRETCH_DEFAULT 0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CONFIG :: ODT_LATENCY [25:21] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_ODT_LATENCY_MASK   0x03e00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_ODT_LATENCY_SHIFT  21
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_ODT_LATENCY_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CONFIG :: LAST_READ_LATENCY [20:15] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_LAST_READ_LATENCY_MASK 0x001f8000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_LAST_READ_LATENCY_SHIFT 15
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_LAST_READ_LATENCY_DEFAULT 0x0000000b
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CONFIG :: READ_LATENCY [14:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_READ_LATENCY_MASK  0x00007f00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_READ_LATENCY_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_READ_LATENCY_DEFAULT 0x00000007
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CONFIG :: WRITE_LATENCY [07:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_WRITE_LATENCY_MASK 0x000000f8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_WRITE_LATENCY_SHIFT 3
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_WRITE_LATENCY_DEFAULT 0x0000000e
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CONFIG :: DRAM_WIDTH [02:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_DRAM_WIDTH_MASK    0x00000006
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_DRAM_WIDTH_SHIFT   1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_DRAM_WIDTH_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CONFIG :: DDR_MODE [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_DDR_MODE_MASK      0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_DDR_MODE_SHIFT     0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CONFIG_DDR_MODE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *DDR23_SHIM_REV_ID - DDR23_SHIM Revision ID Register.
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR23_SHIM_REV_ID :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_REV_ID_reserved0_MASK 0xffff0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_REV_ID_reserved0_SHIFT 16
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR23_SHIM_REV_ID :: MAJOR_ID [15:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_REV_ID_MAJOR_ID_MASK 0x0000ff00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_REV_ID_MAJOR_ID_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_REV_ID_MAJOR_ID_DEFAULT 0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR23_SHIM_REV_ID :: MINOR_ID [07:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_REV_ID_MINOR_ID_MASK 0x000000ff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_REV_ID_MINOR_ID_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_REV_ID_MINOR_ID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET - DDR soft reset register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RESET :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RESET_reserved0_MASK      0xfffffff8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RESET_reserved0_SHIFT     3
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RESET :: DATAPATH_216_RESET [02:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RESET_DATAPATH_216_RESET_MASK 0x00000004
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RESET_DATAPATH_216_RESET_SHIFT 2
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RESET_DATAPATH_216_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RESET :: DATAPATH_DDR_RESET [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RESET_DATAPATH_DDR_RESET_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RESET_DATAPATH_DDR_RESET_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RESET_DATAPATH_DDR_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RESET :: PHY_PWRUP_RSB [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RESET_PHY_PWRUP_RSB_MASK  0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RESET_PHY_PWRUP_RSB_SHIFT 0
+
+/***************************************************************************
+ *ODT_CONFIG - ODT Configuration register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: ODT_CONFIG :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_reserved0_MASK 0xffff0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_reserved0_SHIFT 16
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: ODT_CONFIG :: ODT_TIE_HIGH [15:15] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_ODT_TIE_HIGH_MASK 0x00008000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_ODT_TIE_HIGH_SHIFT 15
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_ODT_TIE_HIGH_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: ODT_CONFIG :: ODT_ENABLE [14:14] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_ODT_ENABLE_MASK 0x00004000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_ODT_ENABLE_SHIFT 14
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_ODT_ENABLE_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: ODT_CONFIG :: STRETCH [13:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_STRETCH_MASK   0x00003800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_STRETCH_SHIFT  11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_STRETCH_DEFAULT 0x00000003
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: ODT_CONFIG :: EARLY [10:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_EARLY_MASK     0x000007c0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_EARLY_SHIFT    6
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_EARLY_DEFAULT  0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: ODT_CONFIG :: DELAY [05:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_DELAY_MASK     0x0000003f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_DELAY_SHIFT    0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ODT_CONFIG_DELAY_DEFAULT  0x00000002
+
+/***************************************************************************
+ *PHY_USE_DYN_VDL - DDR PHY USE DYN VDL Control register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_USE_DYN_VDL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_USE_DYN_VDL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_USE_DYN_VDL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_USE_DYN_VDL :: DISABLE [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_USE_DYN_VDL_DISABLE_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_USE_DYN_VDL_DISABLE_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_USE_DYN_VDL_DISABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_POWER_SAVING - DDR PHY Idle power saving Control register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: IDLE_POWER_SAVING :: reserved0 [31:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_reserved0_MASK 0xffffffc0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_reserved0_SHIFT 6
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: IDLE_POWER_SAVING :: PhyAddrCntl [05:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_PhyAddrCntl_MASK 0x00000030
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_PhyAddrCntl_SHIFT 4
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_PhyAddrCntl_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: IDLE_POWER_SAVING :: ByteLane3 [03:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane3_MASK 0x00000008
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane3_SHIFT 3
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane3_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: IDLE_POWER_SAVING :: ByteLane2 [02:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane2_MASK 0x00000004
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane2_SHIFT 2
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane2_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: IDLE_POWER_SAVING :: ByteLane1 [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane1_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane1_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane1_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: IDLE_POWER_SAVING :: ByteLane0 [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane0_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_IDLE_POWER_SAVING_ByteLane0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHY_STANDBY_EXIT - DDR PHY standby exit register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_STANDBY_EXIT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_STANDBY_EXIT_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_STANDBY_EXIT_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_STANDBY_EXIT :: ENABLE [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_STANDBY_EXIT_ENABLE_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_STANDBY_EXIT_ENABLE_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_STANDBY_EXIT_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *ANALOG_BYPASS_CNTRL - Analog macro register bypass control
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: ANALOG_BYPASS_CNTRL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ANALOG_BYPASS_CNTRL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ANALOG_BYPASS_CNTRL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: ANALOG_BYPASS_CNTRL :: BYPASS_PLL [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ANALOG_BYPASS_CNTRL_BYPASS_PLL_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ANALOG_BYPASS_CNTRL_BYPASS_PLL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_ANALOG_BYPASS_CNTRL_BYPASS_PLL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DDR_PLL_EXT_CLKSEL - DDR PLL external clock select register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR_PLL_EXT_CLKSEL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PLL_EXT_CLKSEL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PLL_EXT_CLKSEL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR_PLL_EXT_CLKSEL :: EXT_CLK_SEL [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TEST_MODE_CNTRL_REG - DDR23_SHIM testport control register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: TEST_MODE_CNTRL_REG :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_TEST_MODE_CNTRL_REG_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_TEST_MODE_CNTRL_REG_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_TEST_MODE_CNTRL_REG_reserved_for_eco0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DISABLE_CHIP_BYPASS_PLL - DDR bypass pll mode disable register.
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DISABLE_CHIP_BYPASS_PLL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DISABLE_CHIP_BYPASS_PLL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DISABLE_CHIP_BYPASS_PLL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DISABLE_CHIP_BYPASS_PLL :: DISABLE_BYPASS_PLL [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VECTOR_MODE_CLK_SEL - DDR VECTOR PLL bypass mode clock select
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: VECTOR_MODE_CLK_SEL :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_VECTOR_MODE_CLK_SEL_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_VECTOR_MODE_CLK_SEL_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: VECTOR_MODE_CLK_SEL :: SEL [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_VECTOR_MODE_CLK_SEL_SEL_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_VECTOR_MODE_CLK_SEL_SEL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_VECTOR_MODE_CLK_SEL_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DDR_PAD_CNTRL - DDR Pad control register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR_PAD_CNTRL :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_reserved0_MASK 0xffffff80
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_reserved0_SHIFT 7
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR_PAD_CNTRL :: IDDQ_MODE_ON_SELFREF [06:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK 0x00000040
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_SHIFT 6
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR_PAD_CNTRL :: PHY_IDLE_ENABLE [05:05] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_MASK 0x00000020
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_SHIFT 5
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR_PAD_CNTRL :: HIZ_ON_SELFREF [04:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_HIZ_ON_SELFREF_MASK 0x00000010
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_HIZ_ON_SELFREF_SHIFT 4
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_HIZ_ON_SELFREF_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR_PAD_CNTRL :: CNTRL [03:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_CNTRL_MASK  0x0000000f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_CNTRL_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL_CNTRL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CLK_GATE - CLK_667_ENABLE Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CLK_GATE :: UNUSED [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CLK_GATE_UNUSED_MASK      0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CLK_GATE_UNUSED_SHIFT     1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CLK_GATE_UNUSED_DEFAULT   0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CLK_GATE :: CLK_667_ENABLE [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CLK_GATE_CLK_667_ENABLE_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CLK_GATE_CLK_667_ENABLE_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CLK_GATE_CLK_667_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DDR23_SHIM_STATUS - DDR23_SHIM Status Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR23_SHIM_STATUS :: reserved0 [31:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS_reserved0_SHIFT 4
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR23_SHIM_STATUS :: BL0_AND_BL1_RDY_SLIP [03:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS_BL0_AND_BL1_RDY_SLIP_MASK 0x00000008
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS_BL0_AND_BL1_RDY_SLIP_SHIFT 3
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR23_SHIM_STATUS :: BL0_RDY_SLIP [02:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS_BL0_RDY_SLIP_MASK 0x00000004
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS_BL0_RDY_SLIP_SHIFT 2
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR23_SHIM_STATUS :: BL1_RDY_SLIP [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS_BL1_RDY_SLIP_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS_BL1_RDY_SLIP_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR23_SHIM_STATUS :: READY [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS_READY_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS_READY_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR23_SHIM_STATUS_READY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CMD_DATA_FIFO - Command and Data FIFO Status Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CMD_DATA_FIFO :: reserved0 [31:26] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_reserved0_MASK 0xfc000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_reserved0_SHIFT 26
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CMD_DATA_FIFO :: FIFO_FULL [25:25] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_FIFO_FULL_MASK 0x02000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_FIFO_FULL_SHIFT 25
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CMD_DATA_FIFO :: FIFO_EMPTY [24:24] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_FIFO_EMPTY_MASK 0x01000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_FIFO_EMPTY_SHIFT 24
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CMD_DATA_FIFO :: reserved1 [23:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_reserved1_MASK 0x00ffff00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_reserved1_SHIFT 8
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CMD_DATA_FIFO :: WR_PNTR [07:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_WR_PNTR_MASK 0x000000f0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_WR_PNTR_SHIFT 4
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: CMD_DATA_FIFO :: RD_PNTR [03:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_RD_PNTR_MASK 0x0000000f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_CMD_DATA_FIFO_RD_PNTR_SHIFT 0
+
+/***************************************************************************
+ *RD_DATAPATH - Read Datapath Status Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RD_DATAPATH :: reserved0 [31:28] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_reserved0_MASK 0xf0000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_reserved0_SHIFT 28
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RD_DATAPATH :: F_RDY_3 [27:27] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_F_RDY_3_MASK  0x08000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_F_RDY_3_SHIFT 27
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RD_DATAPATH :: F_RDY_2 [26:26] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_F_RDY_2_MASK  0x04000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_F_RDY_2_SHIFT 26
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RD_DATAPATH :: F_RDY_1 [25:25] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_F_RDY_1_MASK  0x02000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_F_RDY_1_SHIFT 25
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RD_DATAPATH :: F_RDY_0 [24:24] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_F_RDY_0_MASK  0x01000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_F_RDY_0_SHIFT 24
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RD_DATAPATH :: DWORD3_CNT [23:20] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_DWORD3_CNT_MASK 0x00f00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_DWORD3_CNT_SHIFT 20
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RD_DATAPATH :: DWORD2_CNT [19:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_DWORD2_CNT_MASK 0x000f0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_DWORD2_CNT_SHIFT 16
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RD_DATAPATH :: DWORD1_CNT [15:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_DWORD1_CNT_MASK 0x0000f000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_DWORD1_CNT_SHIFT 12
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RD_DATAPATH :: DWORD0_CNT [11:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_DWORD0_CNT_MASK 0x00000f00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_DWORD0_CNT_SHIFT 8
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RD_DATAPATH :: WR_PNTR [07:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_WR_PNTR_MASK  0x000000f0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_WR_PNTR_SHIFT 4
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: RD_DATAPATH :: RD_PNTR [03:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_RD_PNTR_MASK  0x0000000f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_RD_DATAPATH_RD_PNTR_SHIFT 0
+
+/***************************************************************************
+ *FLAG_BUS - TP_OUT bus value Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: FLAG_BUS :: FLAG_BUS [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_FLAG_BUS_FLAG_BUS_MASK    0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_FLAG_BUS_FLAG_BUS_SHIFT   0
+
+/***************************************************************************
+ *MISC - Miscellaneous Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: reserved_for_eco0 [31:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_reserved_for_eco0_MASK 0xfffff000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_reserved_for_eco0_SHIFT 12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_reserved_for_eco0_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: BL0_AND_BL1_RDY_SLIP_CLR [11:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_BL0_AND_BL1_RDY_SLIP_CLR_MASK 0x00000800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_BL0_AND_BL1_RDY_SLIP_CLR_SHIFT 11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_BL0_AND_BL1_RDY_SLIP_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: BL0_RDY_SLIP_CLR [10:10] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_BL0_RDY_SLIP_CLR_MASK 0x00000400
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_BL0_RDY_SLIP_CLR_SHIFT 10
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_BL0_RDY_SLIP_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: BL1_RDY_SLIP_CLR [09:09] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_BL1_RDY_SLIP_CLR_MASK 0x00000200
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_BL1_RDY_SLIP_CLR_SHIFT 9
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_BL1_RDY_SLIP_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: FUNC1 [08:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_FUNC1_MASK           0x00000100
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_FUNC1_SHIFT          8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_FUNC1_DEFAULT        0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: FUNC0 [07:07] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_FUNC0_MASK           0x00000080
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_FUNC0_SHIFT          7
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_FUNC0_DEFAULT        0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: C2IO_INIT_RDY_OVR [06:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_C2IO_INIT_RDY_OVR_MASK 0x00000040
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_C2IO_INIT_RDY_OVR_SHIFT 6
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_C2IO_INIT_RDY_OVR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: RD_FIFO_HOLD_CLR [05:05] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_RD_FIFO_HOLD_CLR_MASK 0x00000020
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_RD_FIFO_HOLD_CLR_SHIFT 5
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_RD_FIFO_HOLD_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: CMD_FIFO_HOLD_CLR [04:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_CMD_FIFO_HOLD_CLR_MASK 0x00000010
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_CMD_FIFO_HOLD_CLR_SHIFT 4
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_CMD_FIFO_HOLD_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: DWORD3_OVERRUN_CLR [03:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD3_OVERRUN_CLR_MASK 0x00000008
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD3_OVERRUN_CLR_SHIFT 3
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD3_OVERRUN_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: DWORD2_OVERRUN_CLR [02:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD2_OVERRUN_CLR_MASK 0x00000004
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD2_OVERRUN_CLR_SHIFT 2
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD2_OVERRUN_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: DWORD1_OVERRUN_CLR [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD1_OVERRUN_CLR_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD1_OVERRUN_CLR_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD1_OVERRUN_CLR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: MISC :: DWORD0_OVERRUN_CLR [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD0_OVERRUN_CLR_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD0_OVERRUN_CLR_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_MISC_DWORD0_OVERRUN_CLR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE0_RW - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SPARE0_RW :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE0_RW_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE0_RW_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE0_RW_reserved_for_eco0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE1_RW - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SPARE1_RW :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE1_RW_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE1_RW_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE1_RW_reserved_for_eco0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE0_RO - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SPARE0_RO :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE0_RO_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE0_RO_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE0_RO_reserved_for_eco0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE1_RO - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SPARE1_RO :: reserved_for_eco0 [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE1_RO_reserved_for_eco0_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE1_RO_reserved_for_eco0_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SPARE1_RO_reserved_for_eco0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DDR3_RESET_CNTRL - FORCE_DDR3_RESET Deassert  Register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR3_RESET_CNTRL :: UNUSED [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR3_RESET_CNTRL_UNUSED_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR3_RESET_CNTRL_UNUSED_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR3_RESET_CNTRL_UNUSED_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: DDR3_RESET_CNTRL :: FORCE_DDR3_RESET [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PLL6CH_PNDIV_SYS - SYS PLL P and N Divider Controls
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PLL6CH_PNDIV_SYS :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS_reserved0_MASK 0x80000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS_reserved0_SHIFT 31
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PLL6CH_PNDIV_SYS :: PDIV [30:28] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS_PDIV_MASK 0x70000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS_PDIV_SHIFT 28
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS_PDIV_DEFAULT 0x00000002
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PLL6CH_PNDIV_SYS :: NDIV_INT [27:20] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS_NDIV_INT_MASK 0x0ff00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS_NDIV_INT_SHIFT 20
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS_NDIV_INT_DEFAULT 0x0000004e
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PLL6CH_PNDIV_SYS :: NDIV_FRAC [19:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS_NDIV_FRAC_MASK 0x000fffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS_NDIV_FRAC_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PLL6CH_PNDIV_SYS_NDIV_FRAC_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_PLL_GAIN - SYS PLL Gain Controls
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_GAIN :: reserved0 [31:23] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_reserved0_MASK 0xff800000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_reserved0_SHIFT 23
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_GAIN :: FB_PHASE_ENA [22:22] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_FB_PHASE_ENA_MASK 0x00400000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_FB_PHASE_ENA_SHIFT 22
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_FB_PHASE_ENA_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_GAIN :: FB_PHASE_OFFSET [21:10] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_FB_PHASE_OFFSET_MASK 0x003ffc00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_FB_PHASE_OFFSET_SHIFT 10
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_FB_PHASE_OFFSET_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_GAIN :: KP [09:06] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_KP_MASK      0x000003c0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_KP_SHIFT     6
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_KP_DEFAULT   0x00000008
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_GAIN :: KI [05:03] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_KI_MASK      0x00000038
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_KI_SHIFT     3
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_KI_DEFAULT   0x00000003
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_GAIN :: KA [02:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_KA_MASK      0x00000007
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_KA_SHIFT     0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_GAIN_KA_DEFAULT   0x00000001
+
+/***************************************************************************
+ *SYS_PLL_CTRL - SYS PLL Control Vector
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL :: reserved0 [31:23] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_reserved0_MASK 0xff800000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_reserved0_SHIFT 23
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL :: ENA_8PHASE [22:22] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_ENA_8PHASE_MASK 0x00400000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_ENA_8PHASE_SHIFT 22
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_ENA_8PHASE_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL :: ENA_SSC [21:21] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_ENA_SSC_MASK 0x00200000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_ENA_SSC_SHIFT 21
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_ENA_SSC_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL :: VCO_DIV2_EN [20:20] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_VCO_DIV2_EN_MASK 0x00100000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_VCO_DIV2_EN_SHIFT 20
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_VCO_DIV2_EN_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL :: AUX_CTRL [19:19] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_AUX_CTRL_MASK 0x00080000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_AUX_CTRL_SHIFT 19
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_AUX_CTRL_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL :: REFCLK_OUT [18:18] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_REFCLK_OUT_MASK 0x00040000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_REFCLK_OUT_SHIFT 18
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_REFCLK_OUT_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL :: STAT_UPDATE [17:17] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_STAT_UPDATE_MASK 0x00020000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_STAT_UPDATE_SHIFT 17
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_STAT_UPDATE_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL :: STAT_SELECT [16:14] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_STAT_SELECT_MASK 0x0001c000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_STAT_SELECT_SHIFT 14
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_STAT_SELECT_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL :: STAT_RESET [13:13] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_STAT_RESET_MASK 0x00002000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_STAT_RESET_SHIFT 13
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_STAT_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL :: DCO_CTRL_BYPASS_ENA [12:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_DCO_CTRL_BYPASS_ENA_MASK 0x00001000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_DCO_CTRL_BYPASS_ENA_SHIFT 12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_DCO_CTRL_BYPASS_ENA_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_DCO_CTRL_BYPASS_MASK 0x00000fff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_DCO_CTRL_BYPASS_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_DCO_CTRL_BYPASS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SSC_STEP - SSC Step Size for all 6-chan PLLs
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SSC_STEP :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_STEP_reserved0_MASK   0xffff0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_STEP_reserved0_SHIFT  16
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SSC_STEP :: SSC_STEP [15:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_STEP_SSC_STEP_MASK    0x0000ffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_STEP_SSC_STEP_SHIFT   0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_STEP_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SSC_LIMIT - SSC Limit for all 6-chan PLLs
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SSC_LIMIT :: reserved0 [31:22] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_LIMIT_reserved0_MASK  0xffc00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_LIMIT_reserved0_SHIFT 22
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SSC_LIMIT :: SSC_LIMIT [21:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_LIMIT_SSC_LIMIT_MASK  0x003fffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_LIMIT_SSC_LIMIT_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SSC_LIMIT_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_PLL_MDIV0 - SYS PLL M Divider Controls for Channel0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIV0 :: reserved0 [31:14] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_reserved0_MASK 0xffffc000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_reserved0_SHIFT 14
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIV0 :: CHAN_HOLD_OUTPUT [13:13] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_HOLD_OUTPUT_MASK 0x00002000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_HOLD_OUTPUT_SHIFT 13
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_HOLD_OUTPUT_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIV0 :: CHAN_LOAD_MDIV [12:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_LOAD_MDIV_MASK 0x00001000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_LOAD_MDIV_SHIFT 12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_LOAD_MDIV_DEFAULT 0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIV0 :: CHAN_ENA [11:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_ENA_MASK 0x00000800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_ENA_SHIFT 11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_ENA_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIV0 :: CHAN_MDEL [10:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_MDEL_MASK 0x00000700
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_MDEL_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_MDEL_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIV0 :: CHAN_MDIV [07:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_MDIV_MASK 0x000000ff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_MDIV_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIV0_CHAN_MDIV_DEFAULT 0x00000008
+
+/***************************************************************************
+ *SYS_PLL_MDIVX - SYS PLL M Divider Controls for Extra Unused Channels
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIVX :: reserved0 [31:14] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_reserved0_MASK 0xffffc000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_reserved0_SHIFT 14
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIVX :: CHAN_HOLD_OUTPUT [13:13] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_HOLD_OUTPUT_MASK 0x00002000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_HOLD_OUTPUT_SHIFT 13
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_HOLD_OUTPUT_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIVX :: CHAN_LOAD_MDIV [12:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_LOAD_MDIV_MASK 0x00001000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_LOAD_MDIV_SHIFT 12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_LOAD_MDIV_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIVX :: CHAN_ENA [11:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_ENA_MASK 0x00000800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_ENA_SHIFT 11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_ENA_DEFAULT 0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIVX :: CHAN_MDEL [10:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_MDEL_MASK 0x00000700
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_MDEL_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_MDEL_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_MDIVX :: CHAN_MDIV [07:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_MDIV_MASK 0x000000ff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_MDIV_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_MDIVX_CHAN_MDIV_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_PLL_STAT - SYS PLL Status
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_STAT :: reserved0 [31:25] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT_reserved0_MASK 0xfe000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT_reserved0_SHIFT 25
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_STAT :: DEBUG_OUTPUT [24:13] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT_DEBUG_OUTPUT_MASK 0x01ffe000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT_DEBUG_OUTPUT_SHIFT 13
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT_DEBUG_OUTPUT_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_STAT :: LOCK [12:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT_LOCK_MASK    0x00001000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT_LOCK_SHIFT   12
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT_LOCK_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_STAT :: UNLOCK_COUNT [11:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT_UNLOCK_COUNT_MASK 0x00000fff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT_UNLOCK_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_STAT_UNLOCK_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_PLL_PWRDN_ref_clk_sel - SYS PLL power-down and reference clock selection
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_PWRDN_ref_clk_sel :: reserved0 [31:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel_reserved0_MASK 0xfffffffc
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel_reserved0_SHIFT 2
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_PWRDN_ref_clk_sel :: REFCLK_SEL [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel_REFCLK_SEL_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel_REFCLK_SEL_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel_REFCLK_SEL_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_PWRDN_ref_clk_sel :: PWRDN [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel_PWRDN_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel_PWRDN_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel_PWRDN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_PLL_RESET_POST_RESET - SYS PLL Reset and post-resetb selcection
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_RESET_POST_RESET :: reserved0 [31:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_RESET_POST_RESET_reserved0_MASK 0xfffffffc
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_RESET_POST_RESET_reserved0_SHIFT 2
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_RESET_POST_RESET :: POST_RESETB [01:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_RESET_POST_RESET_POST_RESETB_MASK 0x00000002
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_RESET_POST_RESET_POST_RESETB_SHIFT 1
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_RESET_POST_RESET_POST_RESETB_DEFAULT 0x00000001
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_RESET_POST_RESET :: GLOBAL_RESETB [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_RESET_POST_RESET_GLOBAL_RESETB_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_RESET_POST_RESET_GLOBAL_RESETB_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_RESET_POST_RESET_GLOBAL_RESETB_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SYS_PLL_CTRL_SR - SYS PLL control and SR selcection
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL_SR :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR_reserved0_MASK 0xe0000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR_reserved0_SHIFT 29
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL_SR :: PLL_SR [28:11] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR_PLL_SR_MASK 0x1ffff800
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR_PLL_SR_SHIFT 11
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR_PLL_SR_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL_SR :: PLL_CTRL_1 [10:02] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR_PLL_CTRL_1_MASK 0x000007fc
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR_PLL_CTRL_1_SHIFT 2
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR_PLL_CTRL_1_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SYS_PLL_CTRL_SR :: NDIV_INT_1 [01:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR_NDIV_INT_1_MASK 0x00000003
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR_NDIV_INT_1_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_CTRL_SR_NDIV_INT_1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SHIM_TO_PHY_GATED_BYPASS_CLK - Shim to PHY gated bypass_clock selection
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SHIM_TO_PHY_GATED_BYPASS_CLK :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SHIM_TO_PHY_GATED_BYPASS_CLK_reserved0_MASK 0xfffffffe
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SHIM_TO_PHY_GATED_BYPASS_CLK_reserved0_SHIFT 1
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SHIM_TO_PHY_GATED_BYPASS_CLK :: BYPASS_CLK_GATED_TO_SHIM_PHY [00:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SHIM_TO_PHY_GATED_BYPASS_CLK_BYPASS_CLK_GATED_TO_SHIM_PHY_MASK 0x00000001
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SHIM_TO_PHY_GATED_BYPASS_CLK_BYPASS_CLK_GATED_TO_SHIM_PHY_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SHIM_TO_PHY_GATED_BYPASS_CLK_BYPASS_CLK_GATED_TO_SHIM_PHY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG0 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG0 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG0_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG0_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG0_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG1 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG1 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG1_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG1_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG1_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG2 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG2 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG2_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG2_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG2_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG3 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG3 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG3_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG3_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG3_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG4 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG4 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG4_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG4_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG4_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG5 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG5 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG5_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG5_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG5_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG6 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG6 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG6_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG6_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG6_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG7 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG7 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG7_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG7_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG7_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG8 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG8 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG8_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG8_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG8_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG9 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG9 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG9_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG9_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG9_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG10 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG10 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG10_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG10_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG10_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG11 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG11 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG11_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG11_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG11_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG12 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG12 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG12_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG12_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG12_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG13 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG13 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG13_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG13_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG13_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG14 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG14 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG14_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG14_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG14_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_REG15 - Spare register
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: SCRATCH_REG15 :: reserved_for_schmoo [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG15_reserved_for_schmoo_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG15_reserved_for_schmoo_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_SCRATCH_REG15_reserved_for_schmoo_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHY_DYN_VDL_DLY - Delay on phy_dyn_vdl to the PHY
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_DYN_VDL_DLY :: reserved0 [31:28] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_reserved0_MASK 0xf0000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_reserved0_SHIFT 28
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_DYN_VDL_DLY :: DYN_VDL_DEASSERT_TO_READ_ENB_DLY [27:24] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_READ_ENB_DLY_MASK 0x0f000000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_READ_ENB_DLY_SHIFT 24
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_READ_ENB_DLY_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_DYN_VDL_DLY :: reserved1 [23:20] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_reserved1_MASK 0x00f00000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_reserved1_SHIFT 20
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_DYN_VDL_DLY :: DYN_VDL_ASSERT_TO_READ_ENB_DLY [19:16] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_READ_ENB_DLY_MASK 0x000f0000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_READ_ENB_DLY_SHIFT 16
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_READ_ENB_DLY_DEFAULT 0x00000000
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_DYN_VDL_DLY :: reserved2 [15:12] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_reserved2_MASK 0x0000f000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_reserved2_SHIFT 12
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_DYN_VDL_DLY :: DYN_VDL_DEASSERT_TO_WR_VALID_DLY [11:08] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_WR_VALID_DLY_MASK 0x00000f00
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_WR_VALID_DLY_SHIFT 8
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_WR_VALID_DLY_DEFAULT 0x00000002
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_DYN_VDL_DLY :: reserved3 [07:04] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_reserved3_MASK 0x000000f0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_reserved3_SHIFT 4
+
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: PHY_DYN_VDL_DLY :: DYN_VDL_ASSERT_TO_WR_VALID_DLY [03:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_WR_VALID_DLY_MASK 0x0000000f
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_WR_VALID_DLY_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_WR_VALID_DLY_DEFAULT 0x00000002
+
+/***************************************************************************
+ *AON_STORAGE_IN_PHY_0 - DDR PHY data storage register 0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: AON_STORAGE_IN_PHY_0 :: DTATA [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_0_DTATA_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_0_DTATA_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_0_DTATA_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AON_STORAGE_IN_PHY_1 - DDR PHY data storage register 0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: AON_STORAGE_IN_PHY_1 :: DTATA [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_1_DTATA_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_1_DTATA_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_1_DTATA_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AON_STORAGE_IN_PHY_2 - DDR PHY data storage register 0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: AON_STORAGE_IN_PHY_2 :: DTATA [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_2_DTATA_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_2_DTATA_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_2_DTATA_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AON_STORAGE_IN_PHY_3 - DDR PHY data storage register 0
+ ***************************************************************************/
+/* MEMC_DDR23_SHIM_ADDR_CNTL_1 :: AON_STORAGE_IN_PHY_3 :: DTATA [31:00] */
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_3_DTATA_MASK 0xffffffff
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_3_DTATA_SHIFT 0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_AON_STORAGE_IN_PHY_3_DTATA_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_memc_ddr_0.h b/include/linux/brcmstb/7435b0/bchp_memc_ddr_0.h
new file mode 100644
index 0000000..8906560
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_memc_ddr_0.h
@@ -0,0 +1,2665 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 19:01:27 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_memc_ddr_0.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 3:05p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR_0_H__
+#define BCHP_MEMC_DDR_0_H__
+
+/***************************************************************************
+ *MEMC_DDR_0 - Memory Controller Sequencer (DDR Param/Control) Registers 0
+ ***************************************************************************/
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG            0x003b2000 /* Memory Controller Mode-Configuration Register. */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL          0x003b2004 /* Dram iniitialization control */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS         0x003b2008 /* Dram iniitialization status */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0              0x003b200c /* Dram Mode0 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1              0x003b2010 /* Dram Mode1 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2              0x003b2014 /* Dram Mode2 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3              0x003b2018 /* Dram Mode3 register */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG               0x003b201c /* Precharge power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG              0x003b2020 /* Self-refresh power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SSPD_CMD                 0x003b2024 /* Software standby power down mode */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS        0x003b2028 /* Power down status */
+#define BCHP_MEMC_DDR_0_WARM_BOOT                0x003b202c /* Warm boot control registers */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0            0x003b2030 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1            0x003b2034 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2            0x003b2038 /* Read to Write & write to read timing register */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3            0x003b203c /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4            0x003b2040 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5            0x003b2044 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ         0x003b2048 /* Memory Controller Sequencer Enable */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT        0x003b204c /* Memory Controller , state machine timeout register. */
+#define BCHP_MEMC_DDR_0_BANK_STATUS              0x003b2050 /* Memory Controller, Bank Status Register. */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY           0x003b2054 /* Memory Controller, Tester Latency Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0               0x003b2058 /* Memory Controller, DATA_PINMAP_BYTE0_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1               0x003b205c /* Memory Controller, DATA_PINMAP_BYTE1_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2               0x003b2060 /* Memory Controller, DATA_PINMAP_BYTE2_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3               0x003b2064 /* Memory Controller, DATA_PINMAP_BYTE3_SEL Register. */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD   0x003b2068 /* Memory Controller, DDR3 DRAM reset Register. */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL             0x003b206c /* Statistics Control register */
+#define BCHP_MEMC_DDR_0_STAT_TIMER               0x003b2070 /* Statistics Timer */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP            0x003b2074 /* DRAM Idle_NOP Cycle Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP        0x003b2078 /* Maximum DRAM idle_NOP cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL             0x003b207c /* CAS Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL         0x003b2080 /* Maximum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL         0x003b2084 /* DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL 0x003b2088 /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL      0x003b208c /* Number of overall system memory read transactions. */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL     0x003b2090 /* Number of overall system memory write transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL       0x003b2094 /* Maximum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL       0x003b2098 /* Minimum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS  0x003b209c /* Service CAS Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS 0x003b20a0 /* Maximum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS 0x003b20a4 /* Minimum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY 0x003b20a8 /* Service Intra DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY 0x003b20ac /* Service Post DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES 0x003b20b0 /* Maximum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES 0x003b20b4 /* Minimum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ 0x003b20b8 /* Service Read Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE 0x003b20bc /* Service Write Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS 0x003b20c0 /* Maximum service Transaction count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS 0x003b20c4 /* Minimum service cycle Transaction register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY 0x003b20c8 /* Service Latency Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY 0x003b20cc /* Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY 0x003b20d0 /* Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x003b20d4 /* Absolute Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x003b20d8 /* Absolute Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH             0x003b20dc /* Total number of refreshes issuedr. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0        0x003b20e0 /* CAS cycle count register for client 0. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1        0x003b20e4 /* CAS cycle count register for client 1. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2        0x003b20e8 /* CAS cycle count register for client 2. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3        0x003b20ec /* CAS cycle count register for client 3. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4        0x003b20f0 /* CAS cycle count register for client 4. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5        0x003b20f4 /* CAS cycle count register for client 5. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6        0x003b20f8 /* CAS cycle count register for client 6. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7        0x003b20fc /* CAS cycle count register for client 7. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8        0x003b2100 /* CAS cycle count register for client 8. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9        0x003b2104 /* CAS cycle count register for client 9. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10       0x003b2108 /* CAS cycle count register for client 10. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11       0x003b210c /* CAS cycle count register for client 11. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12       0x003b2110 /* CAS cycle count register for client 12. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13       0x003b2114 /* CAS cycle count register for client 13. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14       0x003b2118 /* CAS cycle count register for client 14. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15       0x003b211c /* CAS cycle count register for client 15. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16       0x003b2120 /* CAS cycle count register for client 16. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17       0x003b2124 /* CAS cycle count register for client 17. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18       0x003b2128 /* CAS cycle count register for client 18. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19       0x003b212c /* CAS cycle count register for client 19. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20       0x003b2130 /* CAS cycle count register for client 20. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21       0x003b2134 /* CAS cycle count register for client 21. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22       0x003b2138 /* CAS cycle count register for client 22. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23       0x003b213c /* CAS cycle count register for client 23. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24       0x003b2140 /* CAS cycle count register for client 24. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25       0x003b2144 /* CAS cycle count register for client 25. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26       0x003b2148 /* CAS cycle count register for client 26. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27       0x003b214c /* CAS cycle count register for client 27. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28       0x003b2150 /* CAS cycle count register for client 28. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29       0x003b2154 /* CAS cycle count register for client 29. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30       0x003b2158 /* CAS cycle count register for client 30. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31       0x003b215c /* CAS cycle count register for client 31. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32       0x003b2160 /* CAS cycle count register for client 32. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33       0x003b2164 /* CAS cycle count register for client 33. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34       0x003b2168 /* CAS cycle count register for client 34. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35       0x003b216c /* CAS cycle count register for client 35. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36       0x003b2170 /* CAS cycle count register for client 36. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37       0x003b2174 /* CAS cycle count register for client 37. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38       0x003b2178 /* CAS cycle count register for client 38. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39       0x003b217c /* CAS cycle count register for client 39. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40       0x003b2180 /* CAS cycle count register for client 40. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41       0x003b2184 /* CAS cycle count register for client 41. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42       0x003b2188 /* CAS cycle count register for client 42. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43       0x003b218c /* CAS cycle count register for client 43. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44       0x003b2190 /* CAS cycle count register for client 44. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45       0x003b2194 /* CAS cycle count register for client 45. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46       0x003b2198 /* CAS cycle count register for client 46. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47       0x003b219c /* CAS cycle count register for client 47. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48       0x003b21a0 /* CAS cycle count register for client 48. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49       0x003b21a4 /* CAS cycle count register for client 49. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50       0x003b21a8 /* CAS cycle count register for client 50. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51       0x003b21ac /* CAS cycle count register for client 51. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52       0x003b21b0 /* CAS cycle count register for client 52. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53       0x003b21b4 /* CAS cycle count register for client 53. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54       0x003b21b8 /* CAS cycle count register for client 54. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55       0x003b21bc /* CAS cycle count register for client 55. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56       0x003b21c0 /* CAS cycle count register for client 56. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57       0x003b21c4 /* CAS cycle count register for client 57. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58       0x003b21c8 /* CAS cycle count register for client 58. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59       0x003b21cc /* CAS cycle count register for client 59. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60       0x003b21d0 /* CAS cycle count register for client 60. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61       0x003b21d4 /* CAS cycle count register for client 61. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62       0x003b21d8 /* CAS cycle count register for client 62. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63       0x003b21dc /* CAS cycle count register for client 63. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64       0x003b21e0 /* CAS cycle count register for client 64. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65       0x003b21e4 /* CAS cycle count register for client 65. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66       0x003b21e8 /* CAS cycle count register for client 66. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67       0x003b21ec /* CAS cycle count register for client 67. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68       0x003b21f0 /* CAS cycle count register for client 68. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69       0x003b21f4 /* CAS cycle count register for client 69. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70       0x003b21f8 /* CAS cycle count register for client 70. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71       0x003b21fc /* CAS cycle count register for client 71. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72       0x003b2200 /* CAS cycle count register for client 72. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73       0x003b2204 /* CAS cycle count register for client 73. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74       0x003b2208 /* CAS cycle count register for client 74. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75       0x003b220c /* CAS cycle count register for client 75. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76       0x003b2210 /* CAS cycle count register for client 76. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77       0x003b2214 /* CAS cycle count register for client 77. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78       0x003b2218 /* CAS cycle count register for client 78. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79       0x003b221c /* CAS cycle count register for client 79. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80       0x003b2220 /* CAS cycle count register for client 80. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81       0x003b2224 /* CAS cycle count register for client 81. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82       0x003b2228 /* CAS cycle count register for client 82. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83       0x003b222c /* CAS cycle count register for client 83. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84       0x003b2230 /* CAS cycle count register for client 84. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85       0x003b2234 /* CAS cycle count register for client 85. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86       0x003b2238 /* CAS cycle count register for client 86. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87       0x003b223c /* CAS cycle count register for client 87. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88       0x003b2240 /* CAS cycle count register for client 88. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89       0x003b2244 /* CAS cycle count register for client 89. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90       0x003b2248 /* CAS cycle count register for client 90. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91       0x003b224c /* CAS cycle count register for client 91. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92       0x003b2250 /* CAS cycle count register for client 92. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93       0x003b2254 /* CAS cycle count register for client 93. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94       0x003b2258 /* CAS cycle count register for client 94. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95       0x003b225c /* CAS cycle count register for client 95. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96       0x003b2260 /* CAS cycle count register for client 96. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97       0x003b2264 /* CAS cycle count register for client 97. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98       0x003b2268 /* CAS cycle count register for client 98. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99       0x003b226c /* CAS cycle count register for client 99. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100      0x003b2270 /* CAS cycle count register for client 100. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101      0x003b2274 /* CAS cycle count register for client 101. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102      0x003b2278 /* CAS cycle count register for client 102. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103      0x003b227c /* CAS cycle count register for client 103. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104      0x003b2280 /* CAS cycle count register for client 104. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105      0x003b2284 /* CAS cycle count register for client 105. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106      0x003b2288 /* CAS cycle count register for client 106. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107      0x003b228c /* CAS cycle count register for client 107. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108      0x003b2290 /* CAS cycle count register for client 108. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109      0x003b2294 /* CAS cycle count register for client 109. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110      0x003b2298 /* CAS cycle count register for client 110. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111      0x003b229c /* CAS cycle count register for client 111. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112      0x003b22a0 /* CAS cycle count register for client 112. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113      0x003b22a4 /* CAS cycle count register for client 113. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114      0x003b22a8 /* CAS cycle count register for client 114. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115      0x003b22ac /* CAS cycle count register for client 115. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116      0x003b22b0 /* CAS cycle count register for client 116. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117      0x003b22b4 /* CAS cycle count register for client 117. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118      0x003b22b8 /* CAS cycle count register for client 118. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119      0x003b22bc /* CAS cycle count register for client 119. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120      0x003b22c0 /* CAS cycle count register for client 120. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121      0x003b22c4 /* CAS cycle count register for client 121. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122      0x003b22c8 /* CAS cycle count register for client 122. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123      0x003b22cc /* CAS cycle count register for client 123. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124      0x003b22d0 /* CAS cycle count register for client 124. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125      0x003b22d4 /* CAS cycle count register for client 125. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126      0x003b22d8 /* CAS cycle count register for client 126. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127      0x003b22dc /* CAS cycle count register for client 127. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL         0x003b22e0 /* Minimum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL 0x003b22e4 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL 0x003b22e8 /* MEMSYS Auto Init Control. */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS  0x003b22ec /* MEMSYS Auto Init Status. */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE 0x003b22f0 /* PHY VDL calibrate override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE 0x003b22f4 /* SHIM PLL pndiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE 0x003b22f8 /* SHIM PLL mdiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY          0x003b22fc /* Dynamic VDL shmoo command delay. */
+
+/***************************************************************************
+ *CNTRLR_CONFIG - Memory Controller Mode-Configuration Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_MASK               0xfffffff8
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_SHIFT              3
+
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DEVICE_TECH [02:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_SHIFT            0
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_DEFAULT          0x00000003
+
+/***************************************************************************
+ *DRAM_INIT_CNTRL - Dram iniitialization control
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_MASK             0xfffffff8
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_SHIFT            3
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: BYPASS_PHY_INIT_RDY [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_MASK   0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_SHIFT  2
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR_TECH [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DEFAULT           0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR2              0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR3              1
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR3_INIT_MODE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_MASK        0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_SHIFT       0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *DRAM_INIT_STATUS - Dram iniitialization status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_SHIFT           0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_DEFAULT         0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_0 - Dram Mode0 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: PD_EXIT [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_MASK              0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_SHIFT             12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_DEFAULT         0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: CL [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_MASK                   0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_DEFAULT                0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BL [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_DEFAULT                0x00000002
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK        0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT       12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT     0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT         0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_MASK               0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_SHIFT              4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT            0x00000004
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_DEFAULT               0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_MASK                 0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_SHIFT                2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_DEFAULT              0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_MASK                   0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_1 - Dram Mode1 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DEFAULT             0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: RDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DQSB [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_MASK                 0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_SHIFT                10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_ENABLE               0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DISABLE              1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: OCD_CAL [09:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_MASK              0x00000380
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_SHIFT             7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_DEFAULT       0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: AL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_MASK                   0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DRV_IMP [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DISABLE            1
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT             0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_MASK             0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_SHIFT            10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK          0x00000200
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT         9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_MASK             0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT            7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT          0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE           1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK   0x00000020
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT  5
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_MASK                   0x00000018
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT       0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK   0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT  1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DISABLE            1
+
+/***************************************************************************
+ *DRAM_MODE_2 - Dram Mode2 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_1 [12:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_MASK             0x00001f00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: HT_SRF [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_ENABLE             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DISABLE            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_2 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_MASK             0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_SHIFT            4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: DCC_ENABLE [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_MASK           0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_SHIFT          3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DEFAULT        0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_ENABLE         1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DISABLE        0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_DEFAULT              0x00000000
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_MASK             0x00001800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_SHIFT            11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_MASK               0x00000600
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_SHIFT              9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT            0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT            0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT             6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_MASK                  0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_DEFAULT               0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_3 - Dram Mode3 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: unused_0 [15:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_MASK                  0x0000fff8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR2 :: unused_1 [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_SHIFT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_DEFAULT          0x00000000
+
+/* union - case DDR3 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_MASK                  0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_SHIFT                 2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_DEFAULT               0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_MASK              0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PPD_CONFIG - Precharge power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PPD_CONFIG :: reserved0 [31:13] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_MASK                  0xffffe000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_SHIFT                 13
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_EN [12:12] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_MASK                     0x00001000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_SHIFT                    12
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_DEFAULT                  0x00000000
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: INACT_COUNT [11:00] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_MASK                0x00000fff
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *SRPD_CONFIG - Self-refresh power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SRPD_CONFIG :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_MASK                 0xfffe0000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_SHIFT                17
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: SRPD_EN [16:16] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_MASK                   0x00010000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_SHIFT                  16
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_DEFAULT                0x00000000
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SSPD_CMD - Software standby power down mode
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SSPD_CMD :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_MASK                    0xfffffffe
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_SHIFT                   1
+
+/* MEMC_DDR_0 :: SSPD_CMD :: SSPD [00:00] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK                         0x00000001
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_SHIFT                        0
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *POWER_DOWN_STATUS - Power down status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_MASK           0xfffffff8
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_SHIFT          3
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SSPD [02:02] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK                0x00000004
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_SHIFT               2
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_DEFAULT             0x00000000
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SRPD [01:01] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_MASK                0x00000002
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_SHIFT               1
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_DEFAULT             0x00000000
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: PPD [00:00] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_MASK                 0x00000001
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_SHIFT                0
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_DEFAULT              0x00000000
+
+/***************************************************************************
+ *WARM_BOOT - Warm boot control registers
+ ***************************************************************************/
+/* MEMC_DDR_0 :: WARM_BOOT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_MASK                   0xfffffffe
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_SHIFT                  1
+
+/* MEMC_DDR_0 :: WARM_BOOT :: WARM_BOOT [00:00] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_MASK                   0x00000001
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_TIMING_0 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_MASK                0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_SHIFT               24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_DEFAULT             0x00000006
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_MASK                0x00ff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_SHIFT               16
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_DEFAULT             0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_MASK                 0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_SHIFT                8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_DEFAULT              0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_DEFAULT             0x00000014
+
+/***************************************************************************
+ *DRAM_TIMING_1 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_MASK                0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_SHIFT               8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_DEFAULT             0x0000001b
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_DEFAULT             0x00000004
+
+/***************************************************************************
+ *DRAM_TIMING_2 - Read to Write & write to read timing register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_MASK               0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_SHIFT              8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_DEFAULT            0x0000000e
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_MASK               0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_DEFAULT            0x00000009
+
+/***************************************************************************
+ *DRAM_TIMING_3 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: reserved0 [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_MASK               0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_SHIFT              24
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT      0x0000000c
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: POWERUP_CKE_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_MASK       0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_SHIFT      10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_DEFAULT    0x0000005e
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: DLL_LOCK_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_MASK          0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_SHIFT         0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_DEFAULT       0x00000200
+
+/***************************************************************************
+ *DRAM_TIMING_4 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: PRECHARGE_ALL_DELAY [28:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_MASK     0x1f000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_SHIFT    24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_DEFAULT  0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: LOAD_MODE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_DEFAULT      0x0000000c
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: REFRESH_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_MASK           0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_SHIFT          10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT        0x00000058
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_MASK           0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT          0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT        0x00000200
+
+/***************************************************************************
+ *DRAM_TIMING_5 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_ASSETION_DELAY [28:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_MASK      0x1ff80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_SHIFT     19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_DEFAULT   0x00000105
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [18:15] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK           0x00078000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT          15
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT        0x00000003
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [14:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK         0x00007c00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT        10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT      0x0000000d
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK      0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT     0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT   0x00000200
+
+/***************************************************************************
+ *CNTRLR_START_SEQ - Memory Controller Sequencer Enable
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: START_SEQ [00:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_SHIFT           0
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_MASK           0xfffe0000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_SHIFT          17
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_MASK              0x00010000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT             16
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT            0x0000ffff
+
+/***************************************************************************
+ *BANK_STATUS - Memory Controller, Bank Status Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: BANK_STATUS :: reserved0 [31:08] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_SHIFT                8
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK7_STATUS [07:07] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_SHIFT             7
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK6_STATUS [06:06] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_SHIFT             6
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK5_STATUS [05:05] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_MASK              0x00000020
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_SHIFT             5
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK4_STATUS [04:04] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_MASK              0x00000010
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_SHIFT             4
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK3_STATUS [03:03] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_MASK              0x00000008
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_SHIFT             3
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK2_STATUS [02:02] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_MASK              0x00000004
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_SHIFT             2
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK1_STATUS [01:01] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_SHIFT             1
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK0_STATUS [00:00] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_MASK              0x00000001
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_SHIFT             0
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_DEFAULT           0x00000001
+
+/***************************************************************************
+ *TESTER_LATENCY - Memory Controller, Tester Latency Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: TESTER_LATENCY :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_MASK              0xffffff80
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_SHIFT             7
+
+/* MEMC_DDR_0 :: TESTER_LATENCY :: TLATENCY_SEL [06:00] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_MASK           0x0000007f
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_SHIFT          0
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE0 - Memory Controller, DATA_PINMAP_BYTE0_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE1 - Memory Controller, DATA_PINMAP_BYTE1_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE2 - Memory Controller, DATA_PINMAP_BYTE2_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE3 - Memory Controller, DATA_PINMAP_BYTE3_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_DDR3_RESET_PERIOD - Memory Controller, DDR3 DRAM reset Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: reserved0 [31:20] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_MASK      0xfff00000
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_SHIFT     20
+
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: DRAM_RESET_PERIOD [19:00] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_MASK 0x000fffff
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_SHIFT 0
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_DEFAULT 0x0000a8c0
+
+/***************************************************************************
+ *STAT_CONTROL - Statistics Control register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CONTROL :: reserved0 [31:09] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_MASK                0xfffffe00
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_SHIFT               9
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: COUNTER_MODE [08:08] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_SHIFT            8
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_DEFAULT          0x00000000
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT    1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_NORMAL           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: STAT_ENABLE [07:07] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_SHIFT             7
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DEFAULT           0x00000000
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_ENABLE            1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DISABLE           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: CLIENT_ID [06:00] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_MASK                0x0000007f
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_TIMER - Statistics Timer
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TIMER :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_MASK                      0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_SHIFT                     0
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_MASK                   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_ALL - CAS Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_PENALTY_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_MASK            0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_SHIFT           0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_DEFAULT           0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_MASK         0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT        0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_REFRESH - Total number of refreshes issuedr.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_REFRESH :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_0 - CAS cycle count register for client 0.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_1 - CAS cycle count register for client 1.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_2 - CAS cycle count register for client 2.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_3 - CAS cycle count register for client 3.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_4 - CAS cycle count register for client 4.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_5 - CAS cycle count register for client 5.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_6 - CAS cycle count register for client 6.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_7 - CAS cycle count register for client 7.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_8 - CAS cycle count register for client 8.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_9 - CAS cycle count register for client 9.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_10 - CAS cycle count register for client 10.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_11 - CAS cycle count register for client 11.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_12 - CAS cycle count register for client 12.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_13 - CAS cycle count register for client 13.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_14 - CAS cycle count register for client 14.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_15 - CAS cycle count register for client 15.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_16 - CAS cycle count register for client 16.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_17 - CAS cycle count register for client 17.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_18 - CAS cycle count register for client 18.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_19 - CAS cycle count register for client 19.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_20 - CAS cycle count register for client 20.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_21 - CAS cycle count register for client 21.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_22 - CAS cycle count register for client 22.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_23 - CAS cycle count register for client 23.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_24 - CAS cycle count register for client 24.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_25 - CAS cycle count register for client 25.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_26 - CAS cycle count register for client 26.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_27 - CAS cycle count register for client 27.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_28 - CAS cycle count register for client 28.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_29 - CAS cycle count register for client 29.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_30 - CAS cycle count register for client 30.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_31 - CAS cycle count register for client 31.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_32 - CAS cycle count register for client 32.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_33 - CAS cycle count register for client 33.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_34 - CAS cycle count register for client 34.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_35 - CAS cycle count register for client 35.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_36 - CAS cycle count register for client 36.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_37 - CAS cycle count register for client 37.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_38 - CAS cycle count register for client 38.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_39 - CAS cycle count register for client 39.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_40 - CAS cycle count register for client 40.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_41 - CAS cycle count register for client 41.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_42 - CAS cycle count register for client 42.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_43 - CAS cycle count register for client 43.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_44 - CAS cycle count register for client 44.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_45 - CAS cycle count register for client 45.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_46 - CAS cycle count register for client 46.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_47 - CAS cycle count register for client 47.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_48 - CAS cycle count register for client 48.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_49 - CAS cycle count register for client 49.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_50 - CAS cycle count register for client 50.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_51 - CAS cycle count register for client 51.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_52 - CAS cycle count register for client 52.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_53 - CAS cycle count register for client 53.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_54 - CAS cycle count register for client 54.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_55 - CAS cycle count register for client 55.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_56 - CAS cycle count register for client 56.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_57 - CAS cycle count register for client 57.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_58 - CAS cycle count register for client 58.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_59 - CAS cycle count register for client 59.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_60 - CAS cycle count register for client 60.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_61 - CAS cycle count register for client 61.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_62 - CAS cycle count register for client 62.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_63 - CAS cycle count register for client 63.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_64 - CAS cycle count register for client 64.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_65 - CAS cycle count register for client 65.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_66 - CAS cycle count register for client 66.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_67 - CAS cycle count register for client 67.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_68 - CAS cycle count register for client 68.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_69 - CAS cycle count register for client 69.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_70 - CAS cycle count register for client 70.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_71 - CAS cycle count register for client 71.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_72 - CAS cycle count register for client 72.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_73 - CAS cycle count register for client 73.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_74 - CAS cycle count register for client 74.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_75 - CAS cycle count register for client 75.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_76 - CAS cycle count register for client 76.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_77 - CAS cycle count register for client 77.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_78 - CAS cycle count register for client 78.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_79 - CAS cycle count register for client 79.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_80 - CAS cycle count register for client 80.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_81 - CAS cycle count register for client 81.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_82 - CAS cycle count register for client 82.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_83 - CAS cycle count register for client 83.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_84 - CAS cycle count register for client 84.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_85 - CAS cycle count register for client 85.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_86 - CAS cycle count register for client 86.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_87 - CAS cycle count register for client 87.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_88 - CAS cycle count register for client 88.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_89 - CAS cycle count register for client 89.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_90 - CAS cycle count register for client 90.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_91 - CAS cycle count register for client 91.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_92 - CAS cycle count register for client 92.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_93 - CAS cycle count register for client 93.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_94 - CAS cycle count register for client 94.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_95 - CAS cycle count register for client 95.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_96 - CAS cycle count register for client 96.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_97 - CAS cycle count register for client 97.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_98 - CAS cycle count register for client 98.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_99 - CAS cycle count register for client 99.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_100 - CAS cycle count register for client 100.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_101 - CAS cycle count register for client 101.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_102 - CAS cycle count register for client 102.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_103 - CAS cycle count register for client 103.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_104 - CAS cycle count register for client 104.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_105 - CAS cycle count register for client 105.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_106 - CAS cycle count register for client 106.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_107 - CAS cycle count register for client 107.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_108 - CAS cycle count register for client 108.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_109 - CAS cycle count register for client 109.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_110 - CAS cycle count register for client 110.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_111 - CAS cycle count register for client 111.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_112 - CAS cycle count register for client 112.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_113 - CAS cycle count register for client 113.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_114 - CAS cycle count register for client 114.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_115 - CAS cycle count register for client 115.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_116 - CAS cycle count register for client 116.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_117 - CAS cycle count register for client 117.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_118 - CAS cycle count register for client 118.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_119 - CAS cycle count register for client 119.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_120 - CAS cycle count register for client 120.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_121 - CAS cycle count register for client 121.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_122 - CAS cycle count register for client 122.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_123 - CAS cycle count register for client 123.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_124 - CAS cycle count register for client 124.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_125 - CAS cycle count register for client 125.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_126 - CAS cycle count register for client 126.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_127 - CAS cycle count register for client 127.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_DEFAULT             0xffffffff
+
+/***************************************************************************
+ *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT    0xffffffff
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_CONTROL - MEMSYS Auto Init Control.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: reserved0 [31:10] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_MASK    0xfffffc00
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_SHIFT   10
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_DIVIDER [09:09] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_MASK 0x00000200
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_SHIFT 9
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_VDL_CALIB_AUTO_INIT [08:08] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_MASK 0x00000100
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_SHIFT 8
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_DRAM_INIT_DONE_SET [07:07] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_MASK 0x00000080
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_SHIFT 7
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_RESET [06:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_MASK 0x00000040
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_SET [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_READY_SET [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_AUTO_INIT_ACTIVE_RESET [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_MASK 0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_SHIFT 3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: SKIP_PHY_AUTO_INIT [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: MEMSYS_AUTO_INIT_START [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_STATUS - MEMSYS Auto Init Status.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_MASK     0xfffff000
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_SHIFT    12
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMC_AUTO_INIT_STATES [11:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_MASK 0x00000fc0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: AUTO_INIT_ACTIVE [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_STRAP_VALID [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_READY [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_MASK     0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_SHIFT    3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_DEFAULT  0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: DRAM_INIT_DONE [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_FAIL [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHY_VDL_CALIB_AUTO_INIT_OVERRIDE - PHY VDL calibrate override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PHY_VDL_CALIB_AUTO_INIT_OVERRIDE :: PHY_VDL_CALIB_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_DEFAULT 0x10000000
+
+/***************************************************************************
+ *SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE - SHIM PLL pndiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_PNDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_DEFAULT 0x23b00000
+
+/***************************************************************************
+ *SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE - SHIM PLL mdiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_MDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_DEFAULT 0x00001003
+
+/***************************************************************************
+ *DYN_VDL_CMD_DLY - Dynamic VDL shmoo command delay.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_MASK             0xfffff000
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_SHIFT            12
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: END_CAS_DLY [11:06] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_MASK           0x00000fc0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_SHIFT          6
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_DEFAULT        0x00000000
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: START_CAS_DLY [05:00] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_MASK         0x0000003f
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_SHIFT        0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_DEFAULT      0x00000000
+
+#endif /* #ifndef BCHP_MEMC_DDR_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_memc_ddr_1.h b/include/linux/brcmstb/7435b0/bchp_memc_ddr_1.h
new file mode 100644
index 0000000..f266789
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_memc_ddr_1.h
@@ -0,0 +1,2665 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 19:01:54 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_memc_ddr_1.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 3:05p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR_1_H__
+#define BCHP_MEMC_DDR_1_H__
+
+/***************************************************************************
+ *MEMC_DDR_1 - Memory Controller Sequencer (DDR Param/Control) Registers 1
+ ***************************************************************************/
+#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG            0x003c2000 /* Memory Controller Mode-Configuration Register. */
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL          0x003c2004 /* Dram iniitialization control */
+#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS         0x003c2008 /* Dram iniitialization status */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0              0x003c200c /* Dram Mode0 register */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1              0x003c2010 /* Dram Mode1 register */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2              0x003c2014 /* Dram Mode2 register */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3              0x003c2018 /* Dram Mode3 register */
+#define BCHP_MEMC_DDR_1_PPD_CONFIG               0x003c201c /* Precharge power down mode configuration register */
+#define BCHP_MEMC_DDR_1_SRPD_CONFIG              0x003c2020 /* Self-refresh power down mode configuration register */
+#define BCHP_MEMC_DDR_1_SSPD_CMD                 0x003c2024 /* Software standby power down mode */
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS        0x003c2028 /* Power down status */
+#define BCHP_MEMC_DDR_1_WARM_BOOT                0x003c202c /* Warm boot control registers */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0            0x003c2030 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_1            0x003c2034 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_2            0x003c2038 /* Read to Write & write to read timing register */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3            0x003c203c /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4            0x003c2040 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5            0x003c2044 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_1_CNTRLR_START_SEQ         0x003c2048 /* Memory Controller Sequencer Enable */
+#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT        0x003c204c /* Memory Controller , state machine timeout register. */
+#define BCHP_MEMC_DDR_1_BANK_STATUS              0x003c2050 /* Memory Controller, Bank Status Register. */
+#define BCHP_MEMC_DDR_1_TESTER_LATENCY           0x003c2054 /* Memory Controller, Tester Latency Register. */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0               0x003c2058 /* Memory Controller, DATA_PINMAP_BYTE0_SEL Register. */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1               0x003c205c /* Memory Controller, DATA_PINMAP_BYTE1_SEL Register. */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2               0x003c2060 /* Memory Controller, DATA_PINMAP_BYTE2_SEL Register. */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3               0x003c2064 /* Memory Controller, DATA_PINMAP_BYTE3_SEL Register. */
+#define BCHP_MEMC_DDR_1_DRAM_DDR3_RESET_PERIOD   0x003c2068 /* Memory Controller, DDR3 DRAM reset Register. */
+#define BCHP_MEMC_DDR_1_STAT_CONTROL             0x003c206c /* Statistics Control register */
+#define BCHP_MEMC_DDR_1_STAT_TIMER               0x003c2070 /* Statistics Timer */
+#define BCHP_MEMC_DDR_1_STAT_IDLE_NOP            0x003c2074 /* DRAM Idle_NOP Cycle Count Register. */
+#define BCHP_MEMC_DDR_1_STAT_MAX_IDLE_NOP        0x003c2078 /* Maximum DRAM idle_NOP cycle count register. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_ALL             0x003c207c /* CAS Count Register. */
+#define BCHP_MEMC_DDR_1_STAT_MAX_CAS_ALL         0x003c2080 /* Maximum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_1_STAT_PENALTY_ALL         0x003c2084 /* DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_CYCLES_ALL 0x003c2088 /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_1_STAT_TRANS_READ_ALL      0x003c208c /* Number of overall system memory read transactions. */
+#define BCHP_MEMC_DDR_1_STAT_TRANS_WRITE_ALL     0x003c2090 /* Number of overall system memory write transactions. */
+#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_ALL       0x003c2094 /* Maximum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_ALL       0x003c2098 /* Minimum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_CAS  0x003c209c /* Service CAS Cycle Count register. */
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CAS 0x003c20a0 /* Maximum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CAS 0x003c20a4 /* Minimum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_INTR_PENALTY 0x003c20a8 /* Service Intra DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_POST_PENALTY 0x003c20ac /* Service Post DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CYCLES 0x003c20b0 /* Maximum service cycle count register. */
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CYCLES 0x003c20b4 /* Minimum service cycle count register. */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_READ 0x003c20b8 /* Service Read Transaction Count register. */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_WRITE 0x003c20bc /* Service Write Transaction Count register. */
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_TRANS 0x003c20c0 /* Maximum service Transaction count register. */
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_TRANS 0x003c20c4 /* Minimum service cycle Transaction register. */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_LATENCY 0x003c20c8 /* Service Latency Count register. */
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_LATENCY 0x003c20cc /* Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_LATENCY 0x003c20d0 /* Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x003c20d4 /* Absolute Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x003c20d8 /* Absolute Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_1_STAT_REFRESH             0x003c20dc /* Total number of refreshes issuedr. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_0        0x003c20e0 /* CAS cycle count register for client 0. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_1        0x003c20e4 /* CAS cycle count register for client 1. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_2        0x003c20e8 /* CAS cycle count register for client 2. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_3        0x003c20ec /* CAS cycle count register for client 3. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_4        0x003c20f0 /* CAS cycle count register for client 4. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_5        0x003c20f4 /* CAS cycle count register for client 5. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_6        0x003c20f8 /* CAS cycle count register for client 6. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_7        0x003c20fc /* CAS cycle count register for client 7. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_8        0x003c2100 /* CAS cycle count register for client 8. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_9        0x003c2104 /* CAS cycle count register for client 9. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_10       0x003c2108 /* CAS cycle count register for client 10. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_11       0x003c210c /* CAS cycle count register for client 11. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_12       0x003c2110 /* CAS cycle count register for client 12. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_13       0x003c2114 /* CAS cycle count register for client 13. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_14       0x003c2118 /* CAS cycle count register for client 14. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_15       0x003c211c /* CAS cycle count register for client 15. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_16       0x003c2120 /* CAS cycle count register for client 16. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_17       0x003c2124 /* CAS cycle count register for client 17. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_18       0x003c2128 /* CAS cycle count register for client 18. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_19       0x003c212c /* CAS cycle count register for client 19. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_20       0x003c2130 /* CAS cycle count register for client 20. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_21       0x003c2134 /* CAS cycle count register for client 21. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_22       0x003c2138 /* CAS cycle count register for client 22. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_23       0x003c213c /* CAS cycle count register for client 23. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_24       0x003c2140 /* CAS cycle count register for client 24. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_25       0x003c2144 /* CAS cycle count register for client 25. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_26       0x003c2148 /* CAS cycle count register for client 26. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_27       0x003c214c /* CAS cycle count register for client 27. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_28       0x003c2150 /* CAS cycle count register for client 28. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_29       0x003c2154 /* CAS cycle count register for client 29. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_30       0x003c2158 /* CAS cycle count register for client 30. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_31       0x003c215c /* CAS cycle count register for client 31. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_32       0x003c2160 /* CAS cycle count register for client 32. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_33       0x003c2164 /* CAS cycle count register for client 33. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_34       0x003c2168 /* CAS cycle count register for client 34. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_35       0x003c216c /* CAS cycle count register for client 35. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_36       0x003c2170 /* CAS cycle count register for client 36. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_37       0x003c2174 /* CAS cycle count register for client 37. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_38       0x003c2178 /* CAS cycle count register for client 38. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_39       0x003c217c /* CAS cycle count register for client 39. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_40       0x003c2180 /* CAS cycle count register for client 40. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_41       0x003c2184 /* CAS cycle count register for client 41. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_42       0x003c2188 /* CAS cycle count register for client 42. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_43       0x003c218c /* CAS cycle count register for client 43. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_44       0x003c2190 /* CAS cycle count register for client 44. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_45       0x003c2194 /* CAS cycle count register for client 45. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_46       0x003c2198 /* CAS cycle count register for client 46. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_47       0x003c219c /* CAS cycle count register for client 47. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_48       0x003c21a0 /* CAS cycle count register for client 48. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_49       0x003c21a4 /* CAS cycle count register for client 49. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_50       0x003c21a8 /* CAS cycle count register for client 50. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_51       0x003c21ac /* CAS cycle count register for client 51. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_52       0x003c21b0 /* CAS cycle count register for client 52. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_53       0x003c21b4 /* CAS cycle count register for client 53. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_54       0x003c21b8 /* CAS cycle count register for client 54. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_55       0x003c21bc /* CAS cycle count register for client 55. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_56       0x003c21c0 /* CAS cycle count register for client 56. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_57       0x003c21c4 /* CAS cycle count register for client 57. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_58       0x003c21c8 /* CAS cycle count register for client 58. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_59       0x003c21cc /* CAS cycle count register for client 59. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_60       0x003c21d0 /* CAS cycle count register for client 60. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_61       0x003c21d4 /* CAS cycle count register for client 61. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_62       0x003c21d8 /* CAS cycle count register for client 62. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_63       0x003c21dc /* CAS cycle count register for client 63. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_64       0x003c21e0 /* CAS cycle count register for client 64. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_65       0x003c21e4 /* CAS cycle count register for client 65. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_66       0x003c21e8 /* CAS cycle count register for client 66. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_67       0x003c21ec /* CAS cycle count register for client 67. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_68       0x003c21f0 /* CAS cycle count register for client 68. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_69       0x003c21f4 /* CAS cycle count register for client 69. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_70       0x003c21f8 /* CAS cycle count register for client 70. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_71       0x003c21fc /* CAS cycle count register for client 71. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_72       0x003c2200 /* CAS cycle count register for client 72. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_73       0x003c2204 /* CAS cycle count register for client 73. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_74       0x003c2208 /* CAS cycle count register for client 74. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_75       0x003c220c /* CAS cycle count register for client 75. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_76       0x003c2210 /* CAS cycle count register for client 76. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_77       0x003c2214 /* CAS cycle count register for client 77. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_78       0x003c2218 /* CAS cycle count register for client 78. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_79       0x003c221c /* CAS cycle count register for client 79. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_80       0x003c2220 /* CAS cycle count register for client 80. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_81       0x003c2224 /* CAS cycle count register for client 81. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_82       0x003c2228 /* CAS cycle count register for client 82. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_83       0x003c222c /* CAS cycle count register for client 83. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_84       0x003c2230 /* CAS cycle count register for client 84. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_85       0x003c2234 /* CAS cycle count register for client 85. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_86       0x003c2238 /* CAS cycle count register for client 86. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_87       0x003c223c /* CAS cycle count register for client 87. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_88       0x003c2240 /* CAS cycle count register for client 88. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_89       0x003c2244 /* CAS cycle count register for client 89. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_90       0x003c2248 /* CAS cycle count register for client 90. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_91       0x003c224c /* CAS cycle count register for client 91. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_92       0x003c2250 /* CAS cycle count register for client 92. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_93       0x003c2254 /* CAS cycle count register for client 93. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_94       0x003c2258 /* CAS cycle count register for client 94. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_95       0x003c225c /* CAS cycle count register for client 95. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_96       0x003c2260 /* CAS cycle count register for client 96. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_97       0x003c2264 /* CAS cycle count register for client 97. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_98       0x003c2268 /* CAS cycle count register for client 98. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_99       0x003c226c /* CAS cycle count register for client 99. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_100      0x003c2270 /* CAS cycle count register for client 100. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_101      0x003c2274 /* CAS cycle count register for client 101. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_102      0x003c2278 /* CAS cycle count register for client 102. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_103      0x003c227c /* CAS cycle count register for client 103. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_104      0x003c2280 /* CAS cycle count register for client 104. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_105      0x003c2284 /* CAS cycle count register for client 105. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_106      0x003c2288 /* CAS cycle count register for client 106. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_107      0x003c228c /* CAS cycle count register for client 107. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_108      0x003c2290 /* CAS cycle count register for client 108. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_109      0x003c2294 /* CAS cycle count register for client 109. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_110      0x003c2298 /* CAS cycle count register for client 110. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_111      0x003c229c /* CAS cycle count register for client 111. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_112      0x003c22a0 /* CAS cycle count register for client 112. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_113      0x003c22a4 /* CAS cycle count register for client 113. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_114      0x003c22a8 /* CAS cycle count register for client 114. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_115      0x003c22ac /* CAS cycle count register for client 115. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_116      0x003c22b0 /* CAS cycle count register for client 116. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_117      0x003c22b4 /* CAS cycle count register for client 117. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_118      0x003c22b8 /* CAS cycle count register for client 118. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_119      0x003c22bc /* CAS cycle count register for client 119. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_120      0x003c22c0 /* CAS cycle count register for client 120. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_121      0x003c22c4 /* CAS cycle count register for client 121. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_122      0x003c22c8 /* CAS cycle count register for client 122. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_123      0x003c22cc /* CAS cycle count register for client 123. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_124      0x003c22d0 /* CAS cycle count register for client 124. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_125      0x003c22d4 /* CAS cycle count register for client 125. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_126      0x003c22d8 /* CAS cycle count register for client 126. */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_127      0x003c22dc /* CAS cycle count register for client 127. */
+#define BCHP_MEMC_DDR_1_STAT_MIN_CAS_ALL         0x003c22e0 /* Minimum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_CYCLES_ALL 0x003c22e4 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL 0x003c22e8 /* MEMSYS Auto Init Control. */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS  0x003c22ec /* MEMSYS Auto Init Status. */
+#define BCHP_MEMC_DDR_1_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE 0x003c22f0 /* PHY VDL calibrate override from memc auto init. */
+#define BCHP_MEMC_DDR_1_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE 0x003c22f4 /* SHIM PLL pndiv override from memc auto init. */
+#define BCHP_MEMC_DDR_1_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE 0x003c22f8 /* SHIM PLL mdiv override from memc auto init. */
+#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY          0x003c22fc /* Dynamic VDL shmoo command delay. */
+
+/***************************************************************************
+ *CNTRLR_CONFIG - Memory Controller Mode-Configuration Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: CNTRLR_CONFIG :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_reserved0_MASK               0xfffffff8
+#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_reserved0_SHIFT              3
+
+/* MEMC_DDR_1 :: CNTRLR_CONFIG :: DEVICE_TECH [02:00] */
+#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DEVICE_TECH_MASK             0x00000007
+#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DEVICE_TECH_SHIFT            0
+#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DEVICE_TECH_DEFAULT          0x00000003
+
+/***************************************************************************
+ *DRAM_INIT_CNTRL - Dram iniitialization control
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_INIT_CNTRL :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_reserved0_MASK             0xfffffff8
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_reserved0_SHIFT            3
+
+/* MEMC_DDR_1 :: DRAM_INIT_CNTRL :: BYPASS_PHY_INIT_RDY [02:02] */
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_MASK   0x00000004
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_SHIFT  2
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_DEFAULT 0x00000000
+
+/* MEMC_DDR_1 :: DRAM_INIT_CNTRL :: DDR_TECH [01:01] */
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR_TECH_MASK              0x00000002
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR_TECH_SHIFT             1
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR_TECH_DEFAULT           0x00000001
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR_TECH_DDR2              0
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR_TECH_DDR3              1
+
+/* MEMC_DDR_1 :: DRAM_INIT_CNTRL :: DDR3_INIT_MODE [00:00] */
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR3_INIT_MODE_MASK        0x00000001
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR3_INIT_MODE_SHIFT       0
+#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR3_INIT_MODE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *DRAM_INIT_STATUS - Dram iniitialization status
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_INIT_STATUS :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_reserved0_SHIFT           1
+
+/* MEMC_DDR_1 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_INIT_DONE_MASK            0x00000001
+#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_INIT_DONE_SHIFT           0
+#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_INIT_DONE_DEFAULT         0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_0 - Dram Mode0 register
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_reserved0_SHIFT                16
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR2 :: PD_EXIT [12:12] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_PD_EXIT_MASK              0x00001000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_PD_EXIT_SHIFT             12
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_PD_EXIT_DEFAULT           0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR2 :: WR [11:09] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_WR_DEFAULT                0x00000007
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR2 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_DLL_RST_DEFAULT           0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR2 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_TEST_MODE_DEFAULT         0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR2 :: CL [06:04] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_CL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_CL_SHIFT                  4
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_CL_DEFAULT                0x00000007
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR2 :: BT [03:03] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_BT_MASK                   0x00000008
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_BT_SHIFT                  3
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_BT_DEFAULT                0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR2 :: BL [02:00] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_BL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_BL_DEFAULT                0x00000002
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK        0x00001000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT       12
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT     0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_WR_DEFAULT                0x00000004
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT           0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT         0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_3_1_MASK               0x00000070
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_3_1_SHIFT              4
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT            0x00000004
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_RBT_MASK                  0x00000008
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_RBT_SHIFT                 3
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_RBT_DEFAULT               0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_0_MASK                 0x00000004
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_0_SHIFT                2
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_0_DEFAULT              0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_BL_MASK                   0x00000003
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_BL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_1 - Dram Mode1 register
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_reserved0_SHIFT                16
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_Q_OFF_DEFAULT             0x00000000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: RDQS [11:11] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_RDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_RDQS_SHIFT                11
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_RDQS_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_RDQS_ENABLE               1
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_RDQS_DISABLE              0
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: DQSB [10:10] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DQSB_MASK                 0x00000400
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DQSB_SHIFT                10
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DQSB_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DQSB_ENABLE               0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DQSB_DISABLE              1
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: OCD_CAL [09:07] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_OCD_CAL_MASK              0x00000380
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_OCD_CAL_SHIFT             7
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_OCD_CAL_DEFAULT           0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_ODT_CNTRL_1_DEFAULT       0x00000001
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: AL [05:03] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_AL_MASK                   0x00000038
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_AL_DEFAULT                0x00000006
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_ODT_CNTRL_0_DEFAULT       0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: DRV_IMP [01:01] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DRV_IMP_MASK              0x00000002
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DRV_IMP_SHIFT             1
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DRV_IMP_DEFAULT           0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DLL_EN_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DLL_EN_DISABLE            1
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT             0x00000000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_TDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_TDQS_SHIFT                11
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_TDQS_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_TDQS_ENABLE               1
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_TDQS_DISABLE              0
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_1_MASK             0x00000400
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_1_SHIFT            10
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK          0x00000200
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT         9
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT       0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_WR_LEVEL_MASK             0x00000080
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT            7
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT          0x00000000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE           1
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE          0
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT       0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK   0x00000020
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT  5
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_AL_MASK                   0x00000018
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_AL_DEFAULT                0x00000001
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT       0x00000001
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK   0x00000002
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT  1
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DLL_EN_DISABLE            1
+
+/***************************************************************************
+ *DRAM_MODE_2 - Dram Mode2 register
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_reserved0_SHIFT                16
+
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR2 :: unused_1 [12:08] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_unused_1_MASK             0x00001f00
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_unused_1_SHIFT            8
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR2 :: HT_SRF [07:07] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_HT_SRF_MASK               0x00000080
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_HT_SRF_SHIFT              7
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_HT_SRF_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_HT_SRF_ENABLE             1
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_HT_SRF_DISABLE            0
+
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR2 :: unused_2 [06:04] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_unused_2_MASK             0x00000070
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_unused_2_SHIFT            4
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR2 :: DCC_ENABLE [03:03] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_DCC_ENABLE_MASK           0x00000008
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_DCC_ENABLE_SHIFT          3
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_DCC_ENABLE_DEFAULT        0x00000000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_DCC_ENABLE_ENABLE         1
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_DCC_ENABLE_DISABLE        0
+
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR2 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_PASR_DEFAULT              0x00000000
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_1_MASK             0x00001800
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_1_SHIFT            11
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WR_ODT_MASK               0x00000600
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WR_ODT_SHIFT              9
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT            0x00000001
+
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_SRF_TR_MASK               0x00000080
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_SRF_TR_SHIFT              7
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT            0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_AUTO_SR_MASK              0x00000040
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT             6
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT           0x00000001
+
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WCL_MASK                  0x00000038
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WCL_SHIFT                 3
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WCL_DEFAULT               0x00000001
+
+/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_PASR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_3 - Dram Mode3 register
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_MODE_3 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_reserved0_SHIFT                16
+
+/* MEMC_DDR_1 :: DRAM_MODE_3 :: unused_0 [15:03] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_unused_0_MASK                  0x0000fff8
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_unused_0_SHIFT                 3
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [02:00] */
+/* MEMC_DDR_1 :: DRAM_MODE_3 :: DDR2 :: unused_1 [02:00] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR2_unused_1_MASK             0x00000007
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR2_unused_1_SHIFT            0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR2_unused_1_DEFAULT          0x00000000
+
+/* union - case DDR3 [02:00] */
+/* MEMC_DDR_1 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_MASK                  0x00000004
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_SHIFT                 2
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_DEFAULT               0x00000000
+
+/* MEMC_DDR_1 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_LOC_MASK              0x00000003
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT             0
+#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PPD_CONFIG - Precharge power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_1 :: PPD_CONFIG :: reserved0 [31:13] */
+#define BCHP_MEMC_DDR_1_PPD_CONFIG_reserved0_MASK                  0xffffe000
+#define BCHP_MEMC_DDR_1_PPD_CONFIG_reserved0_SHIFT                 13
+
+/* MEMC_DDR_1 :: PPD_CONFIG :: PPD_EN [12:12] */
+#define BCHP_MEMC_DDR_1_PPD_CONFIG_PPD_EN_MASK                     0x00001000
+#define BCHP_MEMC_DDR_1_PPD_CONFIG_PPD_EN_SHIFT                    12
+#define BCHP_MEMC_DDR_1_PPD_CONFIG_PPD_EN_DEFAULT                  0x00000000
+
+/* MEMC_DDR_1 :: PPD_CONFIG :: INACT_COUNT [11:00] */
+#define BCHP_MEMC_DDR_1_PPD_CONFIG_INACT_COUNT_MASK                0x00000fff
+#define BCHP_MEMC_DDR_1_PPD_CONFIG_INACT_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_1_PPD_CONFIG_INACT_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *SRPD_CONFIG - Self-refresh power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_1 :: SRPD_CONFIG :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_1_SRPD_CONFIG_reserved0_MASK                 0xfffe0000
+#define BCHP_MEMC_DDR_1_SRPD_CONFIG_reserved0_SHIFT                17
+
+/* MEMC_DDR_1 :: SRPD_CONFIG :: SRPD_EN [16:16] */
+#define BCHP_MEMC_DDR_1_SRPD_CONFIG_SRPD_EN_MASK                   0x00010000
+#define BCHP_MEMC_DDR_1_SRPD_CONFIG_SRPD_EN_SHIFT                  16
+#define BCHP_MEMC_DDR_1_SRPD_CONFIG_SRPD_EN_DEFAULT                0x00000000
+
+/* MEMC_DDR_1 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
+#define BCHP_MEMC_DDR_1_SRPD_CONFIG_INACT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_1_SRPD_CONFIG_INACT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_SRPD_CONFIG_INACT_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SSPD_CMD - Software standby power down mode
+ ***************************************************************************/
+/* MEMC_DDR_1 :: SSPD_CMD :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_1_SSPD_CMD_reserved0_MASK                    0xfffffffe
+#define BCHP_MEMC_DDR_1_SSPD_CMD_reserved0_SHIFT                   1
+
+/* MEMC_DDR_1 :: SSPD_CMD :: SSPD [00:00] */
+#define BCHP_MEMC_DDR_1_SSPD_CMD_SSPD_MASK                         0x00000001
+#define BCHP_MEMC_DDR_1_SSPD_CMD_SSPD_SHIFT                        0
+#define BCHP_MEMC_DDR_1_SSPD_CMD_SSPD_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *POWER_DOWN_STATUS - Power down status
+ ***************************************************************************/
+/* MEMC_DDR_1 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_reserved0_MASK           0xfffffff8
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_reserved0_SHIFT          3
+
+/* MEMC_DDR_1 :: POWER_DOWN_STATUS :: SSPD [02:02] */
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SSPD_MASK                0x00000004
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SSPD_SHIFT               2
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SSPD_DEFAULT             0x00000000
+
+/* MEMC_DDR_1 :: POWER_DOWN_STATUS :: SRPD [01:01] */
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SRPD_MASK                0x00000002
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SRPD_SHIFT               1
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SRPD_DEFAULT             0x00000000
+
+/* MEMC_DDR_1 :: POWER_DOWN_STATUS :: PPD [00:00] */
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_PPD_MASK                 0x00000001
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_PPD_SHIFT                0
+#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_PPD_DEFAULT              0x00000000
+
+/***************************************************************************
+ *WARM_BOOT - Warm boot control registers
+ ***************************************************************************/
+/* MEMC_DDR_1 :: WARM_BOOT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_1_WARM_BOOT_reserved0_MASK                   0xfffffffe
+#define BCHP_MEMC_DDR_1_WARM_BOOT_reserved0_SHIFT                  1
+
+/* MEMC_DDR_1 :: WARM_BOOT :: WARM_BOOT [00:00] */
+#define BCHP_MEMC_DDR_1_WARM_BOOT_WARM_BOOT_MASK                   0x00000001
+#define BCHP_MEMC_DDR_1_WARM_BOOT_WARM_BOOT_SHIFT                  0
+#define BCHP_MEMC_DDR_1_WARM_BOOT_WARM_BOOT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_TIMING_0 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRRD_NOP_MASK                0xff000000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRRD_NOP_SHIFT               24
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRRD_NOP_DEFAULT             0x00000006
+
+/* MEMC_DDR_1 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRCD_NOP_MASK                0x00ff0000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRCD_NOP_SHIFT               16
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRCD_NOP_DEFAULT             0x00000008
+
+/* MEMC_DDR_1 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRP_NOP_MASK                 0x0000ff00
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRP_NOP_SHIFT                8
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRP_NOP_DEFAULT              0x00000008
+
+/* MEMC_DDR_1 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRAS_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRAS_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRAS_NOP_DEFAULT             0x00000014
+
+/***************************************************************************
+ *DRAM_TIMING_1 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_TIMING_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_reserved0_SHIFT              16
+
+/* MEMC_DDR_1 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TFAW_NOP_MASK                0x0000ff00
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TFAW_NOP_SHIFT               8
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TFAW_NOP_DEFAULT             0x0000001b
+
+/* MEMC_DDR_1 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TRTP_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TRTP_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TRTP_NOP_DEFAULT             0x00000004
+
+/***************************************************************************
+ *DRAM_TIMING_2 - Read to Write & write to read timing register
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_TIMING_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_reserved0_SHIFT              16
+
+/* MEMC_DDR_1 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_WR2RD_NOP_MASK               0x0000ff00
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_WR2RD_NOP_SHIFT              8
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_WR2RD_NOP_DEFAULT            0x0000000e
+
+/* MEMC_DDR_1 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_RD2WR_NOP_MASK               0x000000ff
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_RD2WR_NOP_SHIFT              0
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_RD2WR_NOP_DEFAULT            0x00000009
+
+/***************************************************************************
+ *DRAM_TIMING_3 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_TIMING_3 :: reserved0 [31:24] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_reserved0_MASK               0xff000000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_reserved0_SHIFT              24
+
+/* MEMC_DDR_1 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT      0x0000000c
+
+/* MEMC_DDR_1 :: DRAM_TIMING_3 :: POWERUP_CKE_DELAY [18:10] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_POWERUP_CKE_DELAY_MASK       0x0007fc00
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_POWERUP_CKE_DELAY_SHIFT      10
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_POWERUP_CKE_DELAY_DEFAULT    0x0000005e
+
+/* MEMC_DDR_1 :: DRAM_TIMING_3 :: DLL_LOCK_DELAY [09:00] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_DLL_LOCK_DELAY_MASK          0x000003ff
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_DLL_LOCK_DELAY_SHIFT         0
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_DLL_LOCK_DELAY_DEFAULT       0x00000200
+
+/***************************************************************************
+ *DRAM_TIMING_4 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_TIMING_4 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_reserved0_SHIFT              29
+
+/* MEMC_DDR_1 :: DRAM_TIMING_4 :: PRECHARGE_ALL_DELAY [28:24] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_MASK     0x1f000000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_SHIFT    24
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_DEFAULT  0x00000008
+
+/* MEMC_DDR_1 :: DRAM_TIMING_4 :: LOAD_MODE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_LOAD_MODE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_LOAD_MODE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_LOAD_MODE_DELAY_DEFAULT      0x0000000c
+
+/* MEMC_DDR_1 :: DRAM_TIMING_4 :: REFRESH_DELAY [18:10] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_REFRESH_DELAY_MASK           0x0007fc00
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_REFRESH_DELAY_SHIFT          10
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT        0x00000058
+
+/* MEMC_DDR_1 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [09:00] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_ZQCALIB_DELAY_MASK           0x000003ff
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT          0
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT        0x00000200
+
+/***************************************************************************
+ *DRAM_TIMING_5 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_TIMING_5 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_reserved0_SHIFT              29
+
+/* MEMC_DDR_1 :: DRAM_TIMING_5 :: CKE_ASSETION_DELAY [28:19] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_ASSETION_DELAY_MASK      0x1ff80000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_ASSETION_DELAY_SHIFT     19
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_ASSETION_DELAY_DEFAULT   0x00000105
+
+/* MEMC_DDR_1 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [18:15] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK           0x00078000
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT          15
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT        0x00000003
+
+/* MEMC_DDR_1 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [14:10] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK         0x00007c00
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT        10
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT      0x0000000d
+
+/* MEMC_DDR_1 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [09:00] */
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK      0x000003ff
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT     0
+#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT   0x00000200
+
+/***************************************************************************
+ *CNTRLR_START_SEQ - Memory Controller Sequencer Enable
+ ***************************************************************************/
+/* MEMC_DDR_1 :: CNTRLR_START_SEQ :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_1_CNTRLR_START_SEQ_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_1_CNTRLR_START_SEQ_reserved0_SHIFT           1
+
+/* MEMC_DDR_1 :: CNTRLR_START_SEQ :: START_SEQ [00:00] */
+#define BCHP_MEMC_DDR_1_CNTRLR_START_SEQ_START_SEQ_MASK            0x00000001
+#define BCHP_MEMC_DDR_1_CNTRLR_START_SEQ_START_SEQ_SHIFT           0
+#define BCHP_MEMC_DDR_1_CNTRLR_START_SEQ_START_SEQ_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_reserved0_MASK           0xfffe0000
+#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_reserved0_SHIFT          17
+
+/* MEMC_DDR_1 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
+#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_ENABLE_MASK              0x00010000
+#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT             16
+#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT           0x00000000
+
+/* MEMC_DDR_1 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
+#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT            0x0000ffff
+
+/***************************************************************************
+ *BANK_STATUS - Memory Controller, Bank Status Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: BANK_STATUS :: reserved0 [31:08] */
+#define BCHP_MEMC_DDR_1_BANK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_MEMC_DDR_1_BANK_STATUS_reserved0_SHIFT                8
+
+/* MEMC_DDR_1 :: BANK_STATUS :: BANK7_STATUS [07:07] */
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK7_STATUS_MASK              0x00000080
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK7_STATUS_SHIFT             7
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK7_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_1 :: BANK_STATUS :: BANK6_STATUS [06:06] */
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK6_STATUS_MASK              0x00000040
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK6_STATUS_SHIFT             6
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK6_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_1 :: BANK_STATUS :: BANK5_STATUS [05:05] */
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK5_STATUS_MASK              0x00000020
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK5_STATUS_SHIFT             5
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK5_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_1 :: BANK_STATUS :: BANK4_STATUS [04:04] */
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK4_STATUS_MASK              0x00000010
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK4_STATUS_SHIFT             4
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK4_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_1 :: BANK_STATUS :: BANK3_STATUS [03:03] */
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK3_STATUS_MASK              0x00000008
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK3_STATUS_SHIFT             3
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK3_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_1 :: BANK_STATUS :: BANK2_STATUS [02:02] */
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK2_STATUS_MASK              0x00000004
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK2_STATUS_SHIFT             2
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK2_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_1 :: BANK_STATUS :: BANK1_STATUS [01:01] */
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK1_STATUS_MASK              0x00000002
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK1_STATUS_SHIFT             1
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK1_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_1 :: BANK_STATUS :: BANK0_STATUS [00:00] */
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK0_STATUS_MASK              0x00000001
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK0_STATUS_SHIFT             0
+#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK0_STATUS_DEFAULT           0x00000001
+
+/***************************************************************************
+ *TESTER_LATENCY - Memory Controller, Tester Latency Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: TESTER_LATENCY :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR_1_TESTER_LATENCY_reserved0_MASK              0xffffff80
+#define BCHP_MEMC_DDR_1_TESTER_LATENCY_reserved0_SHIFT             7
+
+/* MEMC_DDR_1 :: TESTER_LATENCY :: TLATENCY_SEL [06:00] */
+#define BCHP_MEMC_DDR_1_TESTER_LATENCY_TLATENCY_SEL_MASK           0x0000007f
+#define BCHP_MEMC_DDR_1_TESTER_LATENCY_TLATENCY_SEL_SHIFT          0
+#define BCHP_MEMC_DDR_1_TESTER_LATENCY_TLATENCY_SEL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE0 - Memory Controller, DATA_PINMAP_BYTE0_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved0_SHIFT                 31
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved1_SHIFT                 27
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved2_SHIFT                 23
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved3_SHIFT                 19
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved4_SHIFT                 15
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved5_SHIFT                 11
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved6_SHIFT                 7
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved7_SHIFT                 3
+
+/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE1 - Memory Controller, DATA_PINMAP_BYTE1_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved0_SHIFT                 31
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved1_SHIFT                 27
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved2_SHIFT                 23
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved3_SHIFT                 19
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved4_SHIFT                 15
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved5_SHIFT                 11
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved6_SHIFT                 7
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved7_SHIFT                 3
+
+/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE2 - Memory Controller, DATA_PINMAP_BYTE2_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved0_SHIFT                 31
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved1_SHIFT                 27
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved2_SHIFT                 23
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved3_SHIFT                 19
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved4_SHIFT                 15
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved5_SHIFT                 11
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved6_SHIFT                 7
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved7_SHIFT                 3
+
+/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE3 - Memory Controller, DATA_PINMAP_BYTE3_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved0_SHIFT                 31
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved1_SHIFT                 27
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved2_SHIFT                 23
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved3_SHIFT                 19
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved4_SHIFT                 15
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved5_SHIFT                 11
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved6_SHIFT                 7
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved7_SHIFT                 3
+
+/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_DDR3_RESET_PERIOD - Memory Controller, DDR3 DRAM reset Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DRAM_DDR3_RESET_PERIOD :: reserved0 [31:20] */
+#define BCHP_MEMC_DDR_1_DRAM_DDR3_RESET_PERIOD_reserved0_MASK      0xfff00000
+#define BCHP_MEMC_DDR_1_DRAM_DDR3_RESET_PERIOD_reserved0_SHIFT     20
+
+/* MEMC_DDR_1 :: DRAM_DDR3_RESET_PERIOD :: DRAM_RESET_PERIOD [19:00] */
+#define BCHP_MEMC_DDR_1_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_MASK 0x000fffff
+#define BCHP_MEMC_DDR_1_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_SHIFT 0
+#define BCHP_MEMC_DDR_1_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_DEFAULT 0x0000a8c0
+
+/***************************************************************************
+ *STAT_CONTROL - Statistics Control register
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CONTROL :: reserved0 [31:09] */
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_reserved0_MASK                0xfffffe00
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_reserved0_SHIFT               9
+
+/* MEMC_DDR_1 :: STAT_CONTROL :: COUNTER_MODE [08:08] */
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_COUNTER_MODE_MASK             0x00000100
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_COUNTER_MODE_SHIFT            8
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_COUNTER_MODE_DEFAULT          0x00000000
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT    1
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_COUNTER_MODE_NORMAL           0
+
+/* MEMC_DDR_1 :: STAT_CONTROL :: STAT_ENABLE [07:07] */
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_STAT_ENABLE_MASK              0x00000080
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_STAT_ENABLE_SHIFT             7
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_STAT_ENABLE_DEFAULT           0x00000000
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_STAT_ENABLE_ENABLE            1
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_STAT_ENABLE_DISABLE           0
+
+/* MEMC_DDR_1 :: STAT_CONTROL :: CLIENT_ID [06:00] */
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_CLIENT_ID_MASK                0x0000007f
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_CLIENT_ID_SHIFT               0
+#define BCHP_MEMC_DDR_1_STAT_CONTROL_CLIENT_ID_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_TIMER - Statistics Timer
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_TIMER :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_TIMER_COUNT_MASK                      0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_TIMER_COUNT_SHIFT                     0
+#define BCHP_MEMC_DDR_1_STAT_TIMER_COUNT_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_IDLE_NOP_COUNT_MASK                   0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_IDLE_NOP_COUNT_SHIFT                  0
+#define BCHP_MEMC_DDR_1_STAT_IDLE_NOP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MAX_IDLE_NOP_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MAX_IDLE_NOP_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_STAT_MAX_IDLE_NOP_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_ALL - CAS Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_ALL_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_ALL_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_1_STAT_CAS_ALL_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MAX_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MAX_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_1_STAT_MAX_CAS_ALL_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_PENALTY_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_PENALTY_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_PENALTY_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_1_STAT_PENALTY_ALL_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_TRANS_READ_ALL_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_TRANS_READ_ALL_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_TRANS_READ_ALL_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_TRANS_WRITE_ALL_COUNT_MASK            0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_TRANS_WRITE_ALL_COUNT_SHIFT           0
+#define BCHP_MEMC_DDR_1_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_ALL_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_ALL_COUNT_DEFAULT           0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_CAS_COUNT_MASK         0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT        0
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_REFRESH - Total number of refreshes issuedr.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_REFRESH :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_REFRESH_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_REFRESH_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_1_STAT_REFRESH_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_0 - CAS cycle count register for client 0.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_0_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_0_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_0_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_1 - CAS cycle count register for client 1.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_1_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_1_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_1_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_2 - CAS cycle count register for client 2.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_2_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_2_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_2_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_3 - CAS cycle count register for client 3.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_3_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_3_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_3_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_4 - CAS cycle count register for client 4.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_4_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_4_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_4_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_5 - CAS cycle count register for client 5.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_5_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_5_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_5_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_6 - CAS cycle count register for client 6.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_6_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_6_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_6_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_7 - CAS cycle count register for client 7.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_7_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_7_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_7_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_8 - CAS cycle count register for client 8.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_8_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_8_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_8_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_9 - CAS cycle count register for client 9.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_9_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_9_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_9_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_10 - CAS cycle count register for client 10.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_10_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_10_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_10_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_11 - CAS cycle count register for client 11.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_11_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_11_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_11_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_12 - CAS cycle count register for client 12.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_12_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_12_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_12_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_13 - CAS cycle count register for client 13.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_13_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_13_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_13_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_14 - CAS cycle count register for client 14.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_14_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_14_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_14_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_15 - CAS cycle count register for client 15.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_15_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_15_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_15_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_16 - CAS cycle count register for client 16.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_16_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_16_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_16_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_17 - CAS cycle count register for client 17.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_17_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_17_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_17_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_18 - CAS cycle count register for client 18.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_18_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_18_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_18_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_19 - CAS cycle count register for client 19.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_19_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_19_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_19_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_20 - CAS cycle count register for client 20.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_20_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_20_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_20_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_21 - CAS cycle count register for client 21.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_21_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_21_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_21_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_22 - CAS cycle count register for client 22.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_22_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_22_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_22_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_23 - CAS cycle count register for client 23.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_23_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_23_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_23_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_24 - CAS cycle count register for client 24.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_24_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_24_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_24_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_25 - CAS cycle count register for client 25.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_25_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_25_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_25_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_26 - CAS cycle count register for client 26.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_26_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_26_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_26_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_27 - CAS cycle count register for client 27.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_27_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_27_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_27_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_28 - CAS cycle count register for client 28.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_28_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_28_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_28_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_29 - CAS cycle count register for client 29.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_29_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_29_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_29_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_30 - CAS cycle count register for client 30.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_30_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_30_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_30_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_31 - CAS cycle count register for client 31.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_31_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_31_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_31_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_32 - CAS cycle count register for client 32.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_32_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_32_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_32_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_33 - CAS cycle count register for client 33.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_33_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_33_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_33_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_34 - CAS cycle count register for client 34.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_34_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_34_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_34_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_35 - CAS cycle count register for client 35.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_35_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_35_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_35_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_36 - CAS cycle count register for client 36.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_36_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_36_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_36_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_37 - CAS cycle count register for client 37.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_37_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_37_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_37_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_38 - CAS cycle count register for client 38.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_38_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_38_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_38_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_39 - CAS cycle count register for client 39.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_39_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_39_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_39_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_40 - CAS cycle count register for client 40.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_40_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_40_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_40_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_41 - CAS cycle count register for client 41.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_41_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_41_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_41_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_42 - CAS cycle count register for client 42.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_42_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_42_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_42_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_43 - CAS cycle count register for client 43.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_43_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_43_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_43_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_44 - CAS cycle count register for client 44.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_44_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_44_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_44_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_45 - CAS cycle count register for client 45.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_45_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_45_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_45_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_46 - CAS cycle count register for client 46.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_46_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_46_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_46_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_47 - CAS cycle count register for client 47.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_47_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_47_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_47_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_48 - CAS cycle count register for client 48.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_48_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_48_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_48_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_49 - CAS cycle count register for client 49.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_49_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_49_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_49_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_50 - CAS cycle count register for client 50.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_50_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_50_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_50_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_51 - CAS cycle count register for client 51.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_51_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_51_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_51_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_52 - CAS cycle count register for client 52.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_52_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_52_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_52_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_53 - CAS cycle count register for client 53.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_53_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_53_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_53_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_54 - CAS cycle count register for client 54.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_54_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_54_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_54_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_55 - CAS cycle count register for client 55.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_55_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_55_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_55_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_56 - CAS cycle count register for client 56.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_56_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_56_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_56_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_57 - CAS cycle count register for client 57.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_57_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_57_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_57_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_58 - CAS cycle count register for client 58.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_58_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_58_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_58_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_59 - CAS cycle count register for client 59.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_59_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_59_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_59_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_60 - CAS cycle count register for client 60.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_60_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_60_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_60_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_61 - CAS cycle count register for client 61.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_61_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_61_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_61_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_62 - CAS cycle count register for client 62.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_62_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_62_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_62_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_63 - CAS cycle count register for client 63.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_63_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_63_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_63_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_64 - CAS cycle count register for client 64.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_64_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_64_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_64_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_65 - CAS cycle count register for client 65.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_65_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_65_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_65_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_66 - CAS cycle count register for client 66.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_66_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_66_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_66_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_67 - CAS cycle count register for client 67.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_67_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_67_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_67_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_68 - CAS cycle count register for client 68.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_68_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_68_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_68_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_69 - CAS cycle count register for client 69.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_69_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_69_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_69_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_70 - CAS cycle count register for client 70.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_70_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_70_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_70_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_71 - CAS cycle count register for client 71.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_71_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_71_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_71_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_72 - CAS cycle count register for client 72.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_72_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_72_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_72_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_73 - CAS cycle count register for client 73.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_73_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_73_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_73_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_74 - CAS cycle count register for client 74.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_74_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_74_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_74_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_75 - CAS cycle count register for client 75.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_75_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_75_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_75_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_76 - CAS cycle count register for client 76.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_76_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_76_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_76_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_77 - CAS cycle count register for client 77.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_77_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_77_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_77_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_78 - CAS cycle count register for client 78.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_78_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_78_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_78_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_79 - CAS cycle count register for client 79.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_79_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_79_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_79_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_80 - CAS cycle count register for client 80.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_80_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_80_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_80_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_81 - CAS cycle count register for client 81.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_81_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_81_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_81_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_82 - CAS cycle count register for client 82.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_82_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_82_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_82_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_83 - CAS cycle count register for client 83.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_83_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_83_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_83_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_84 - CAS cycle count register for client 84.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_84_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_84_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_84_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_85 - CAS cycle count register for client 85.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_85_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_85_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_85_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_86 - CAS cycle count register for client 86.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_86_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_86_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_86_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_87 - CAS cycle count register for client 87.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_87_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_87_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_87_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_88 - CAS cycle count register for client 88.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_88_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_88_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_88_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_89 - CAS cycle count register for client 89.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_89_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_89_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_89_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_90 - CAS cycle count register for client 90.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_90_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_90_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_90_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_91 - CAS cycle count register for client 91.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_91_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_91_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_91_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_92 - CAS cycle count register for client 92.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_92_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_92_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_92_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_93 - CAS cycle count register for client 93.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_93_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_93_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_93_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_94 - CAS cycle count register for client 94.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_94_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_94_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_94_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_95 - CAS cycle count register for client 95.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_95_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_95_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_95_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_96 - CAS cycle count register for client 96.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_96_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_96_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_96_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_97 - CAS cycle count register for client 97.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_97_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_97_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_97_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_98 - CAS cycle count register for client 98.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_98_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_98_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_98_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_99 - CAS cycle count register for client 99.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_99_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_99_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_99_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_100 - CAS cycle count register for client 100.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_100_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_100_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_100_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_101 - CAS cycle count register for client 101.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_101_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_101_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_101_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_102 - CAS cycle count register for client 102.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_102_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_102_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_102_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_103 - CAS cycle count register for client 103.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_103_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_103_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_103_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_104 - CAS cycle count register for client 104.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_104_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_104_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_104_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_105 - CAS cycle count register for client 105.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_105_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_105_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_105_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_106 - CAS cycle count register for client 106.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_106_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_106_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_106_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_107 - CAS cycle count register for client 107.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_107_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_107_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_107_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_108 - CAS cycle count register for client 108.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_108_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_108_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_108_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_109 - CAS cycle count register for client 109.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_109_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_109_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_109_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_110 - CAS cycle count register for client 110.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_110_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_110_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_110_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_111 - CAS cycle count register for client 111.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_111_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_111_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_111_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_112 - CAS cycle count register for client 112.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_112_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_112_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_112_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_113 - CAS cycle count register for client 113.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_113_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_113_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_113_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_114 - CAS cycle count register for client 114.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_114_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_114_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_114_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_115 - CAS cycle count register for client 115.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_115_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_115_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_115_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_116 - CAS cycle count register for client 116.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_116_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_116_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_116_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_117 - CAS cycle count register for client 117.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_117_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_117_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_117_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_118 - CAS cycle count register for client 118.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_118_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_118_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_118_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_119 - CAS cycle count register for client 119.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_119_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_119_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_119_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_120 - CAS cycle count register for client 120.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_120_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_120_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_120_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_121 - CAS cycle count register for client 121.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_121_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_121_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_121_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_122 - CAS cycle count register for client 122.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_122_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_122_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_122_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_123 - CAS cycle count register for client 123.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_123_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_123_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_123_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_124 - CAS cycle count register for client 124.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_124_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_124_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_124_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_125 - CAS cycle count register for client 125.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_125_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_125_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_125_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_126 - CAS cycle count register for client 126.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_126_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_126_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_126_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_127 - CAS cycle count register for client 127.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_127_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_127_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_127_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MIN_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MIN_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_1_STAT_MIN_CAS_ALL_COUNT_DEFAULT             0xffffffff
+
+/***************************************************************************
+ *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_1 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT    0xffffffff
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_CONTROL - MEMSYS Auto Init Control.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: reserved0 [31:10] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_reserved0_MASK    0xfffffc00
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_reserved0_SHIFT   10
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_DIVIDER [09:09] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_MASK 0x00000200
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_SHIFT 9
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_DEFAULT 0x00000000
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_VDL_CALIB_AUTO_INIT [08:08] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_MASK 0x00000100
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_SHIFT 8
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_DEFAULT 0x00000000
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_DRAM_INIT_DONE_SET [07:07] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_MASK 0x00000080
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_SHIFT 7
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_RESET [06:06] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_MASK 0x00000040
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_SHIFT 6
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_SET [05:05] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_MASK 0x00000020
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_SHIFT 5
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_READY_SET [04:04] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_MASK 0x00000010
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_SHIFT 4
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_AUTO_INIT_ACTIVE_RESET [03:03] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_MASK 0x00000008
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_SHIFT 3
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET [02:02] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_MASK 0x00000004
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_SHIFT 2
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: SKIP_PHY_AUTO_INIT [01:01] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_MASK 0x00000002
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_SHIFT 1
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_DEFAULT 0x00000000
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: MEMSYS_AUTO_INIT_START [00:00] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_MASK 0x00000001
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_SHIFT 0
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_STATUS - MEMSYS Auto Init Status.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_reserved0_MASK     0xfffff000
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_reserved0_SHIFT    12
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: MEMC_AUTO_INIT_STATES [11:06] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_MASK 0x00000fc0
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_SHIFT 6
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_DEFAULT 0x00000000
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: AUTO_INIT_ACTIVE [05:05] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_MASK 0x00000020
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_SHIFT 5
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_DEFAULT 0x00000000
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: PHY_STRAP_VALID [04:04] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_MASK 0x00000010
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_SHIFT 4
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_DEFAULT 0x00000000
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: PHY_READY [03:03] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_PHY_READY_MASK     0x00000008
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_PHY_READY_SHIFT    3
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_PHY_READY_DEFAULT  0x00000000
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: DRAM_INIT_DONE [02:02] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_MASK 0x00000004
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_SHIFT 2
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_DEFAULT 0x00000000
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_FAIL [01:01] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_MASK 0x00000002
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_SHIFT 1
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_DEFAULT 0x00000000
+
+/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_MASK 0x00000001
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_SHIFT 0
+#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHY_VDL_CALIB_AUTO_INIT_OVERRIDE - PHY VDL calibrate override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: PHY_VDL_CALIB_AUTO_INIT_OVERRIDE :: PHY_VDL_CALIB_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_1_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_1_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_1_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_DEFAULT 0x10000000
+
+/***************************************************************************
+ *SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE - SHIM PLL pndiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_PNDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_1_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_1_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_1_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_DEFAULT 0x23b00000
+
+/***************************************************************************
+ *SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE - SHIM PLL mdiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_MDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_1_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_1_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_1_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_DEFAULT 0x00001003
+
+/***************************************************************************
+ *DYN_VDL_CMD_DLY - Dynamic VDL shmoo command delay.
+ ***************************************************************************/
+/* MEMC_DDR_1 :: DYN_VDL_CMD_DLY :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_reserved0_MASK             0xfffff000
+#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_reserved0_SHIFT            12
+
+/* MEMC_DDR_1 :: DYN_VDL_CMD_DLY :: END_CAS_DLY [11:06] */
+#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_END_CAS_DLY_MASK           0x00000fc0
+#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_END_CAS_DLY_SHIFT          6
+#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_END_CAS_DLY_DEFAULT        0x00000000
+
+/* MEMC_DDR_1 :: DYN_VDL_CMD_DLY :: START_CAS_DLY [05:00] */
+#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_START_CAS_DLY_MASK         0x0000003f
+#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_START_CAS_DLY_SHIFT        0
+#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_START_CAS_DLY_DEFAULT      0x00000000
+
+#endif /* #ifndef BCHP_MEMC_DDR_1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_memc_misc_1.h b/include/linux/brcmstb/7435b0/bchp_memc_misc_1.h
new file mode 100644
index 0000000..e95bd5f
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_memc_misc_1.h
@@ -0,0 +1,128 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Jul 20 15:43:16 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_MISC_1_H__
+#define BCHP_MEMC_MISC_1_H__
+
+/***************************************************************************
+ *MEMC_MISC_1 - MEMSYS Misc (Soft-Resets/Configuration) Registers 1
+ ***************************************************************************/
+#define BCHP_MEMC_MISC_1_SOFT_RESET              0x003c5000 /* MEMC_TOP layout block Soft Reset */
+#define BCHP_MEMC_MISC_1_MEMC_STRAP_DDR_CONFIG   0x003c5004 /* MEMC_STRAP_DDR_CONFIG Control Register */
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL       0x003c5008 /* MEMC MBIST TM Control Register */
+#define BCHP_MEMC_MISC_1_SCRATCH_0               0x003c5010 /* Scratch Register */
+
+/***************************************************************************
+ *SOFT_RESET - MEMC_TOP layout block Soft Reset
+ ***************************************************************************/
+/* MEMC_MISC_1 :: SOFT_RESET :: reserved0 [31:05] */
+#define BCHP_MEMC_MISC_1_SOFT_RESET_reserved0_MASK                 0xffffffe0
+#define BCHP_MEMC_MISC_1_SOFT_RESET_reserved0_SHIFT                5
+
+/* MEMC_MISC_1 :: SOFT_RESET :: MEMC_IOBUF_RBUS [04:04] */
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_IOBUF_RBUS_MASK           0x00000010
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_IOBUF_RBUS_SHIFT          4
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_IOBUF_RBUS_DEFAULT        0x00000000
+
+/* MEMC_MISC_1 :: SOFT_RESET :: MEMC_IOBUF [03:03] */
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_IOBUF_MASK                0x00000008
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_IOBUF_SHIFT               3
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_IOBUF_DEFAULT             0x00000000
+
+/* MEMC_MISC_1 :: SOFT_RESET :: MEMC_DRAM_INIT [02:02] */
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_DRAM_INIT_MASK            0x00000004
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_DRAM_INIT_SHIFT           2
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_DRAM_INIT_DEFAULT         0x00000000
+
+/* MEMC_MISC_1 :: SOFT_RESET :: MEMC_RBUS [01:01] */
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_RBUS_MASK                 0x00000002
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_RBUS_SHIFT                1
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_RBUS_DEFAULT              0x00000000
+
+/* MEMC_MISC_1 :: SOFT_RESET :: MEMC_CORE [00:00] */
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_CORE_MASK                 0x00000001
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_CORE_SHIFT                0
+#define BCHP_MEMC_MISC_1_SOFT_RESET_MEMC_CORE_DEFAULT              0x00000000
+
+/***************************************************************************
+ *MEMC_STRAP_DDR_CONFIG - MEMC_STRAP_DDR_CONFIG Control Register
+ ***************************************************************************/
+/* MEMC_MISC_1 :: MEMC_STRAP_DDR_CONFIG :: reserved0 [31:02] */
+#define BCHP_MEMC_MISC_1_MEMC_STRAP_DDR_CONFIG_reserved0_MASK      0xfffffffc
+#define BCHP_MEMC_MISC_1_MEMC_STRAP_DDR_CONFIG_reserved0_SHIFT     2
+
+/* MEMC_MISC_1 :: MEMC_STRAP_DDR_CONFIG :: DDR_CONFIG [01:00] */
+#define BCHP_MEMC_MISC_1_MEMC_STRAP_DDR_CONFIG_DDR_CONFIG_MASK     0x00000003
+#define BCHP_MEMC_MISC_1_MEMC_STRAP_DDR_CONFIG_DDR_CONFIG_SHIFT    0
+#define BCHP_MEMC_MISC_1_MEMC_STRAP_DDR_CONFIG_DDR_CONFIG_DEFAULT  0x00000001
+#define BCHP_MEMC_MISC_1_MEMC_STRAP_DDR_CONFIG_DDR_CONFIG_DDR32BIT 1
+#define BCHP_MEMC_MISC_1_MEMC_STRAP_DDR_CONFIG_DDR_CONFIG_DDR16BIT 2
+
+/***************************************************************************
+ *MEMC_TOP_TM_CNTRL - MEMC MBIST TM Control Register
+ ***************************************************************************/
+/* MEMC_MISC_1 :: MEMC_TOP_TM_CNTRL :: reserved0 [31:06] */
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_reserved0_MASK          0xffffffc0
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_reserved0_SHIFT         6
+
+/* MEMC_MISC_1 :: MEMC_TOP_TM_CNTRL :: MEMC_PFRI_FIFO_2 [05:04] */
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_2_MASK   0x00000030
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_2_SHIFT  4
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_2_DEFAULT 0x00000000
+
+/* MEMC_MISC_1 :: MEMC_TOP_TM_CNTRL :: MEMC_PFRI_FIFO_1 [03:02] */
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_1_MASK   0x0000000c
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_1_SHIFT  2
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_1_DEFAULT 0x00000000
+
+/* MEMC_MISC_1 :: MEMC_TOP_TM_CNTRL :: MEMC_PFRI_FIFO_0 [01:00] */
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_0_MASK   0x00000003
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_0_SHIFT  0
+#define BCHP_MEMC_MISC_1_MEMC_TOP_TM_CNTRL_MEMC_PFRI_FIFO_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCRATCH_0 - Scratch Register
+ ***************************************************************************/
+/* MEMC_MISC_1 :: SCRATCH_0 :: VALUE [31:00] */
+#define BCHP_MEMC_MISC_1_SCRATCH_0_VALUE_MASK                      0xffffffff
+#define BCHP_MEMC_MISC_1_SCRATCH_0_VALUE_SHIFT                     0
+#define BCHP_MEMC_MISC_1_SCRATCH_0_VALUE_DEFAULT                   0x00000000
+
+#endif /* #ifndef BCHP_MEMC_MISC_1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_moca_hostmisc.h b/include/linux/brcmstb/7435b0/bchp_moca_hostmisc.h
new file mode 100644
index 0000000..732e35d4
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_moca_hostmisc.h
@@ -0,0 +1,503 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:10:02 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MOCA_HOSTMISC_H__
+#define BCHP_MOCA_HOSTMISC_H__
+
+/***************************************************************************
+ *MOCA_HOSTMISC - MOCA_HOSTMISC registers
+ ***************************************************************************/
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL             0x00fffd00 /* Moca Software Reset */
+#define BCHP_MOCA_HOSTMISC_SCRATCH               0x00fffd04 /* Moca Scratch Register */
+#define BCHP_MOCA_HOSTMISC_VERSION               0x00fffd08 /* MoCA version register */
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG          0x00fffd0c /* Host-to-MoCA Interrupt Trigger */
+#define BCHP_MOCA_HOSTMISC_WAKEUP                0x00fffd10 /* Host-to-MoCA Wakeup Interrupt */
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG            0x00fffd14 /* Moca Subsystem configuration */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0      0x00fffd18 /* Host to MoCA MMP outbox registes , register set index 0. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1      0x00fffd1c /* Host to MoCA MMP outbox registes , register set index 1. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2      0x00fffd20 /* Host to MoCA MMP outbox registes , register set index 2. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3      0x00fffd24 /* Host to MoCA MMP outbox registes , register set index 3. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4      0x00fffd28 /* Host to MoCA MMP outbox registes , register set index 4. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5      0x00fffd2c /* Host to MoCA MMP outbox registes , register set index 5. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6      0x00fffd30 /* Host to MoCA MMP outbox registes , register set index 6. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7      0x00fffd34 /* Host to MoCA MMP outbox registes , register set index 7. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8      0x00fffd38 /* Host to MoCA MMP outbox registes , register set index 8. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9      0x00fffd3c /* Host to MoCA MMP outbox registes , register set index 9. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10     0x00fffd40 /* Host to MoCA MMP outbox registes , register set index 10. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11     0x00fffd44 /* Host to MoCA MMP outbox registes , register set index 11. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12     0x00fffd48 /* Host to MoCA MMP outbox registes , register set index 12. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13     0x00fffd4c /* Host to MoCA MMP outbox registes , register set index 13. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14     0x00fffd50 /* Host to MoCA MMP outbox registes , register set index 14. */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15     0x00fffd54 /* Host to MoCA MMP outbox registes , register set index 15. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0       0x00fffd58 /* MoCA to Host MMP inbox registers , register set index 0. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1       0x00fffd5c /* MoCA to Host MMP inbox registers , register set index 1. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2       0x00fffd60 /* MoCA to Host MMP inbox registers , register set index 2. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3       0x00fffd64 /* MoCA to Host MMP inbox registers , register set index 3. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4       0x00fffd68 /* MoCA to Host MMP inbox registers , register set index 4. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5       0x00fffd6c /* MoCA to Host MMP inbox registers , register set index 5. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6       0x00fffd70 /* MoCA to Host MMP inbox registers , register set index 6. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7       0x00fffd74 /* MoCA to Host MMP inbox registers , register set index 7. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8       0x00fffd78 /* MoCA to Host MMP inbox registers , register set index 8. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9       0x00fffd7c /* MoCA to Host MMP inbox registers , register set index 9. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10      0x00fffd80 /* MoCA to Host MMP inbox registers , register set index 10. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11      0x00fffd84 /* MoCA to Host MMP inbox registers , register set index 11. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12      0x00fffd88 /* MoCA to Host MMP inbox registers , register set index 12. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13      0x00fffd8c /* MoCA to Host MMP inbox registers , register set index 13. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14      0x00fffd90 /* MoCA to Host MMP inbox registers , register set index 14. */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15      0x00fffd94 /* MoCA to Host MMP inbox registers , register set index 15. */
+
+/***************************************************************************
+ *MISC_CTRL - Moca Software Reset
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: MISC_CTRL :: spare_ctrl [31:15] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_ctrl_MASK               0xffff8000
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_ctrl_SHIFT              15
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_ctrl_DEFAULT            0x0001ffff
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: spare_status [14:10] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_status_MASK             0x00007c00
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_status_SHIFT            10
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_status_DEFAULT          0x0000001f
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: moca_phy1_disable_clk [09:09] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_disable_clk_MASK    0x00000200
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_disable_clk_SHIFT   9
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_disable_clk_DEFAULT 0x00000000
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: moca_phy0_disable_clk [08:08] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_disable_clk_MASK    0x00000100
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_disable_clk_SHIFT   8
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_disable_clk_DEFAULT 0x00000000
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: moca_disable_clocks [07:07] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_disable_clocks_MASK      0x00000080
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_disable_clocks_SHIFT     7
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_disable_clocks_DEFAULT   0x00000000
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: spare_reset [06:06] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset_MASK              0x00000040
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset_SHIFT             6
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_spare_reset_DEFAULT           0x00000001
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: moca_phy1_reset [05:05] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_reset_MASK          0x00000020
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_reset_SHIFT         5
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy1_reset_DEFAULT       0x00000000
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: moca_phy0_reset [04:04] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_reset_MASK          0x00000010
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_reset_SHIFT         4
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_phy0_reset_DEFAULT       0x00000000
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: moca_gmii_sw_init [03:03] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_gmii_sw_init_MASK        0x00000008
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_gmii_sw_init_SHIFT       3
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_gmii_sw_init_DEFAULT     0x00000000
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: moca_cpu_l_reset [02:02] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_l_reset_MASK         0x00000004
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_l_reset_SHIFT        2
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_l_reset_DEFAULT      0x00000001
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: moca_sys_reset [01:01] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_sys_reset_MASK           0x00000002
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_sys_reset_SHIFT          1
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_sys_reset_DEFAULT        0x00000001
+
+/* MOCA_HOSTMISC :: MISC_CTRL :: moca_cpu_h_reset [00:00] */
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_h_reset_MASK         0x00000001
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_h_reset_SHIFT        0
+#define BCHP_MOCA_HOSTMISC_MISC_CTRL_moca_cpu_h_reset_DEFAULT      0x00000001
+
+/***************************************************************************
+ *SCRATCH - Moca Scratch Register
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: SCRATCH :: value [31:00] */
+#define BCHP_MOCA_HOSTMISC_SCRATCH_value_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_SCRATCH_value_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_SCRATCH_value_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *VERSION - MoCA version register
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: VERSION :: moca_id [31:16] */
+#define BCHP_MOCA_HOSTMISC_VERSION_moca_id_MASK                    0xffff0000
+#define BCHP_MOCA_HOSTMISC_VERSION_moca_id_SHIFT                   16
+#define BCHP_MOCA_HOSTMISC_VERSION_moca_id_DEFAULT                 0x00006622
+
+/* MOCA_HOSTMISC :: VERSION :: moca_spec_ver [15:12] */
+#define BCHP_MOCA_HOSTMISC_VERSION_moca_spec_ver_MASK              0x0000f000
+#define BCHP_MOCA_HOSTMISC_VERSION_moca_spec_ver_SHIFT             12
+#define BCHP_MOCA_HOSTMISC_VERSION_moca_spec_ver_DEFAULT           0x00000003
+
+/* MOCA_HOSTMISC :: VERSION :: core_version [11:08] */
+#define BCHP_MOCA_HOSTMISC_VERSION_core_version_MASK               0x00000f00
+#define BCHP_MOCA_HOSTMISC_VERSION_core_version_SHIFT              8
+#define BCHP_MOCA_HOSTMISC_VERSION_core_version_DEFAULT            0x00000000
+
+/* MOCA_HOSTMISC :: VERSION :: core_revision [07:04] */
+#define BCHP_MOCA_HOSTMISC_VERSION_core_revision_MASK              0x000000f0
+#define BCHP_MOCA_HOSTMISC_VERSION_core_revision_SHIFT             4
+#define BCHP_MOCA_HOSTMISC_VERSION_core_revision_DEFAULT           0x00000000
+
+/* MOCA_HOSTMISC :: VERSION :: core_mask [03:00] */
+#define BCHP_MOCA_HOSTMISC_VERSION_core_mask_MASK                  0x0000000f
+#define BCHP_MOCA_HOSTMISC_VERSION_core_mask_SHIFT                 0
+#define BCHP_MOCA_HOSTMISC_VERSION_core_mask_DEFAULT               0x00000000
+
+/***************************************************************************
+ *H2M_INT_TRIG - Host-to-MoCA Interrupt Trigger
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_INT_TRIG :: reserved0 [31:08] */
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_reserved0_MASK             0xffffff00
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_reserved0_SHIFT            8
+
+/* MOCA_HOSTMISC :: H2M_INT_TRIG :: INT_TRIG [07:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_MASK              0x000000ff
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_SHIFT             0
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_DEFAULT           0x00000000
+
+/***************************************************************************
+ *WAKEUP - Host-to-MoCA Wakeup Interrupt
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: WAKEUP :: reserved0 [31:02] */
+#define BCHP_MOCA_HOSTMISC_WAKEUP_reserved0_MASK                   0xfffffffc
+#define BCHP_MOCA_HOSTMISC_WAKEUP_reserved0_SHIFT                  2
+
+/* MOCA_HOSTMISC :: WAKEUP :: cpu_l_wakeup_int [01:01] */
+#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_l_wakeup_int_MASK            0x00000002
+#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_l_wakeup_int_SHIFT           1
+#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_l_wakeup_int_DEFAULT         0x00000000
+
+/* MOCA_HOSTMISC :: WAKEUP :: cpu_h_wakeup_int [00:00] */
+#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_h_wakeup_int_MASK            0x00000001
+#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_h_wakeup_int_SHIFT           0
+#define BCHP_MOCA_HOSTMISC_WAKEUP_cpu_h_wakeup_int_DEFAULT         0x00000000
+
+/***************************************************************************
+ *SUBSYS_CFG - Moca Subsystem configuration
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: SUBSYS_CFG :: spare_cfg [31:12] */
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_spare_cfg_MASK               0xfffff000
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_spare_cfg_SHIFT              12
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_spare_cfg_DEFAULT            0x00000000
+
+/* MOCA_HOSTMISC :: SUBSYS_CFG :: psm_vdd_sp_pd_mask [11:11] */
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_psm_vdd_sp_pd_mask_MASK      0x00000800
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_psm_vdd_sp_pd_mask_SHIFT     11
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_psm_vdd_sp_pd_mask_DEFAULT   0x00000000
+
+/* MOCA_HOSTMISC :: SUBSYS_CFG :: psm_vdd_regfile_mask [10:10] */
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_psm_vdd_regfile_mask_MASK    0x00000400
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_psm_vdd_regfile_mask_SHIFT   10
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_psm_vdd_regfile_mask_DEFAULT 0x00000000
+
+/* MOCA_HOSTMISC :: SUBSYS_CFG :: moca_ctl_mem_split_reg [09:07] */
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_ctl_mem_split_reg_MASK  0x00000380
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_ctl_mem_split_reg_SHIFT 7
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_ctl_mem_split_reg_DEFAULT 0x00000004
+
+/* MOCA_HOSTMISC :: SUBSYS_CFG :: spare_cfg0 [06:01] */
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_spare_cfg0_MASK              0x0000007e
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_spare_cfg0_SHIFT             1
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_spare_cfg0_DEFAULT           0x00000000
+
+/* MOCA_HOSTMISC :: SUBSYS_CFG :: moca_arb_rr_sel [00:00] */
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_arb_rr_sel_MASK         0x00000001
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_arb_rr_sel_SHIFT        0
+#define BCHP_MOCA_HOSTMISC_SUBSYS_CFG_moca_arb_rr_sel_DEFAULT      0x00000001
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_0 - Host to MoCA MMP outbox registes , register set index 0.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_0 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_0_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_1 - Host to MoCA MMP outbox registes , register set index 1.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_1 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_1_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_2 - Host to MoCA MMP outbox registes , register set index 2.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_2 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_2_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_3 - Host to MoCA MMP outbox registes , register set index 3.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_3 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_3_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_4 - Host to MoCA MMP outbox registes , register set index 4.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_4 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_4_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_5 - Host to MoCA MMP outbox registes , register set index 5.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_5 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_5_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_6 - Host to MoCA MMP outbox registes , register set index 6.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_6 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_6_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_7 - Host to MoCA MMP outbox registes , register set index 7.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_7 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_7_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_8 - Host to MoCA MMP outbox registes , register set index 8.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_8 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_8_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_9 - Host to MoCA MMP outbox registes , register set index 9.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_9 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9_m2h_mmp_outbox_MASK    0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9_m2h_mmp_outbox_SHIFT   0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_9_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_10 - Host to MoCA MMP outbox registes , register set index 10.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_10 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10_m2h_mmp_outbox_MASK   0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10_m2h_mmp_outbox_SHIFT  0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_10_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_11 - Host to MoCA MMP outbox registes , register set index 11.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_11 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11_m2h_mmp_outbox_MASK   0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11_m2h_mmp_outbox_SHIFT  0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_11_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_12 - Host to MoCA MMP outbox registes , register set index 12.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_12 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12_m2h_mmp_outbox_MASK   0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12_m2h_mmp_outbox_SHIFT  0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_12_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_13 - Host to MoCA MMP outbox registes , register set index 13.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_13 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13_m2h_mmp_outbox_MASK   0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13_m2h_mmp_outbox_SHIFT  0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_13_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_14 - Host to MoCA MMP outbox registes , register set index 14.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_14 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14_m2h_mmp_outbox_MASK   0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14_m2h_mmp_outbox_SHIFT  0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_14_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *H2M_MMP_OUTBOX_15 - Host to MoCA MMP outbox registes , register set index 15.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_MMP_OUTBOX_15 :: m2h_mmp_outbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15_m2h_mmp_outbox_MASK   0xffffffff
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15_m2h_mmp_outbox_SHIFT  0
+#define BCHP_MOCA_HOSTMISC_H2M_MMP_OUTBOX_15_m2h_mmp_outbox_DEFAULT 0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_0 - MoCA to Host MMP inbox registers , register set index 0.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_0 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_0_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_1 - MoCA to Host MMP inbox registers , register set index 1.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_1 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_1_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_2 - MoCA to Host MMP inbox registers , register set index 2.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_2 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_2_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_3 - MoCA to Host MMP inbox registers , register set index 3.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_3 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_3_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_4 - MoCA to Host MMP inbox registers , register set index 4.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_4 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_4_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_5 - MoCA to Host MMP inbox registers , register set index 5.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_5 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_5_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_6 - MoCA to Host MMP inbox registers , register set index 6.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_6 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_6_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_7 - MoCA to Host MMP inbox registers , register set index 7.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_7 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_7_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_8 - MoCA to Host MMP inbox registers , register set index 8.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_8 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_8_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_9 - MoCA to Host MMP inbox registers , register set index 9.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_9 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9_h2m_mmp_inbox_MASK      0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9_h2m_mmp_inbox_SHIFT     0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_9_h2m_mmp_inbox_DEFAULT   0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_10 - MoCA to Host MMP inbox registers , register set index 10.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_10 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10_h2m_mmp_inbox_MASK     0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10_h2m_mmp_inbox_SHIFT    0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_10_h2m_mmp_inbox_DEFAULT  0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_11 - MoCA to Host MMP inbox registers , register set index 11.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_11 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11_h2m_mmp_inbox_MASK     0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11_h2m_mmp_inbox_SHIFT    0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_11_h2m_mmp_inbox_DEFAULT  0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_12 - MoCA to Host MMP inbox registers , register set index 12.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_12 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12_h2m_mmp_inbox_MASK     0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12_h2m_mmp_inbox_SHIFT    0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_12_h2m_mmp_inbox_DEFAULT  0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_13 - MoCA to Host MMP inbox registers , register set index 13.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_13 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13_h2m_mmp_inbox_MASK     0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13_h2m_mmp_inbox_SHIFT    0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_13_h2m_mmp_inbox_DEFAULT  0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_14 - MoCA to Host MMP inbox registers , register set index 14.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_14 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14_h2m_mmp_inbox_MASK     0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14_h2m_mmp_inbox_SHIFT    0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_14_h2m_mmp_inbox_DEFAULT  0x00000000
+
+/***************************************************************************
+ *M2H_MMP_INBOX_15 - MoCA to Host MMP inbox registers , register set index 15.
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: M2H_MMP_INBOX_15 :: h2m_mmp_inbox [31:00] */
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15_h2m_mmp_inbox_MASK     0xffffffff
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15_h2m_mmp_inbox_SHIFT    0
+#define BCHP_MOCA_HOSTMISC_M2H_MMP_INBOX_15_h2m_mmp_inbox_DEFAULT  0x00000000
+
+#endif /* #ifndef BCHP_MOCA_HOSTMISC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_nand.h b/include/linux/brcmstb/7435b0/bchp_nand.h
new file mode 100644
index 0000000..b66779a
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_nand.h
@@ -0,0 +1,3133 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:28 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_nand.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 3:21p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_NAND_H__
+#define BCHP_NAND_H__
+
+/***************************************************************************
+ *NAND - Nand Flash Control Registers
+ ***************************************************************************/
+#define BCHP_NAND_REVISION                       0x0041c800 /* NAND Revision */
+#define BCHP_NAND_CMD_START                      0x0041c804 /* Nand Flash Command Start */
+#define BCHP_NAND_CMD_EXT_ADDRESS                0x0041c808 /* Nand Flash Command Extended Address */
+#define BCHP_NAND_CMD_ADDRESS                    0x0041c80c /* Nand Flash Command Address */
+#define BCHP_NAND_CMD_END_ADDRESS                0x0041c810 /* Nand Flash Command End Address */
+#define BCHP_NAND_INTFC_STATUS                   0x0041c814 /* Nand Flash Interface Status */
+#define BCHP_NAND_CS_NAND_SELECT                 0x0041c818 /* Nand Flash EBI CS Select */
+#define BCHP_NAND_CS_NAND_XOR                    0x0041c81c /* Nand Flash EBI CS Address XOR with 1FC0 Control */
+#define BCHP_NAND_LL_OP                          0x0041c820 /* Nand Flash Low Level Operation */
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS        0x0041c824 /* Nand Flash Multiplane base address */
+#define BCHP_NAND_MPLANE_BASE_ADDRESS            0x0041c828 /* Nand Flash Multiplane base address */
+#define BCHP_NAND_ACC_CONTROL_CS0                0x0041c850 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS0                     0x0041c854 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS0                   0x0041c858 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS0                   0x0041c85c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS1                0x0041c860 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS1                     0x0041c864 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS1                   0x0041c868 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS1                   0x0041c86c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS2                0x0041c870 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS2                     0x0041c874 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS2                   0x0041c878 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS2                   0x0041c87c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS3                0x0041c880 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS3                     0x0041c884 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS3                   0x0041c888 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS3                   0x0041c88c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS4                0x0041c890 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS4                     0x0041c894 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS4                   0x0041c898 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS4                   0x0041c89c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS5                0x0041c8a0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS5                     0x0041c8a4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS5                   0x0041c8a8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS5                   0x0041c8ac /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_CORR_STAT_THRESHOLD            0x0041c8c0 /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT        0x0041c8c4 /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_BLK_WR_PROTECT                 0x0041c8c8 /* Block Write Protect Enable and Size for EBI_CS0b */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1           0x0041c8cc /* Nand Flash Multiplane Customerized Opcodes */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2           0x0041c8d0 /* Nand Flash Multiplane Customerized Opcodes */
+#define BCHP_NAND_MULTIPLANE_CTRL                0x0041c8d4 /* Nand Flash Multiplane Control */
+#define BCHP_NAND_UNCORR_ERROR_COUNT             0x0041c8fc /* Read Uncorrectable Event Count */
+#define BCHP_NAND_CORR_ERROR_COUNT               0x0041c900 /* Read Error Count */
+#define BCHP_NAND_READ_ERROR_COUNT               0x0041c904 /* Read Error Count */
+#define BCHP_NAND_BLOCK_LOCK_STATUS              0x0041c908 /* Nand Flash Block Lock Status */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR              0x0041c90c /* ECC Correctable Error Extended Address */
+#define BCHP_NAND_ECC_CORR_ADDR                  0x0041c910 /* ECC Correctable Error Address */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR               0x0041c914 /* ECC Uncorrectable Error Extended Address */
+#define BCHP_NAND_ECC_UNC_ADDR                   0x0041c918 /* ECC Uncorrectable Error Address */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR            0x0041c91c /* Flash Read Data Extended Address */
+#define BCHP_NAND_FLASH_READ_ADDR                0x0041c920 /* Flash Read Data Address */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR          0x0041c924 /* Page Program Extended Address */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR              0x0041c928 /* Page Program Address */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR             0x0041c92c /* Copy Back Extended Address */
+#define BCHP_NAND_COPY_BACK_ADDR                 0x0041c930 /* Copy Back Address */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR           0x0041c934 /* Block Erase Extended Address */
+#define BCHP_NAND_BLOCK_ERASE_ADDR               0x0041c938 /* Block Erase Address */
+#define BCHP_NAND_INV_READ_EXT_ADDR              0x0041c93c /* Flash Invalid Data Extended Address */
+#define BCHP_NAND_INV_READ_ADDR                  0x0041c940 /* Flash Invalid Data Address */
+#define BCHP_NAND_INIT_STATUS                    0x0041c944 /* Initialization status */
+#define BCHP_NAND_ONFI_STATUS                    0x0041c948 /* ONFI Status */
+#define BCHP_NAND_ONFI_DEBUG_DATA                0x0041c94c /* ONFI Debug Data */
+#define BCHP_NAND_SEMAPHORE                      0x0041c950 /* Semaphore */
+#define BCHP_NAND_FLASH_DEVICE_ID                0x0041c994 /* Nand Flash Device ID */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT            0x0041c998 /* Nand Flash Extended Device ID */
+#define BCHP_NAND_LL_RDDATA                      0x0041c99c /* Nand Flash Low Level Read Data */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0          0x0041ca00 /* Nand Flash Spare Area Read Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4          0x0041ca04 /* Nand Flash Spare Area Read Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8          0x0041ca08 /* Nand Flash Spare Area Read Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C          0x0041ca0c /* Nand Flash Spare Area Read Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10         0x0041ca10 /* Nand Flash Spare Area Read Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14         0x0041ca14 /* Nand Flash Spare Area Read Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18         0x0041ca18 /* Nand Flash Spare Area Read Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C         0x0041ca1c /* Nand Flash Spare Area Read Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20         0x0041ca20 /* Nand Flash Spare Area Read Bytes 32-35 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24         0x0041ca24 /* Nand Flash Spare Area Read Bytes 36-39 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28         0x0041ca28 /* Nand Flash Spare Area Read Bytes 40-43 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C         0x0041ca2c /* Nand Flash Spare Area Read Bytes 44-47 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30         0x0041ca30 /* Nand Flash Spare Area Read Bytes 48-51 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34         0x0041ca34 /* Nand Flash Spare Area Read Bytes 52-55 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38         0x0041ca38 /* Nand Flash Spare Area Read Bytes 56-59 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C         0x0041ca3c /* Nand Flash Spare Area Read Bytes 60-63 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0         0x0041ca80 /* Nand Flash Spare Area Write Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4         0x0041ca84 /* Nand Flash Spare Area Write Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8         0x0041ca88 /* Nand Flash Spare Area Write Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C         0x0041ca8c /* Nand Flash Spare Area Write Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10        0x0041ca90 /* Nand Flash Spare Area Write Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14        0x0041ca94 /* Nand Flash Spare Area Write Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18        0x0041ca98 /* Nand Flash Spare Area Write Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C        0x0041ca9c /* Nand Flash Spare Area Write Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20        0x0041caa0 /* Nand Flash Spare Area Write Bytes 32-35 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24        0x0041caa4 /* Nand Flash Spare Area Write Bytes 36-39 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28        0x0041caa8 /* Nand Flash Spare Area Write Bytes 40-43 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C        0x0041caac /* Nand Flash Spare Area Write Bytes 44-47 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30        0x0041cab0 /* Nand Flash Spare Area Write Bytes 48-51 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34        0x0041cab4 /* Nand Flash Spare Area Write Bytes 52-55 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38        0x0041cab8 /* Nand Flash Spare Area Write Bytes 56-59 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C        0x0041cabc /* Nand Flash Spare Area Write Bytes 60-63 */
+
+/***************************************************************************
+ *REVISION - NAND Revision
+ ***************************************************************************/
+/* NAND :: REVISION :: 8KB_PAGE_SUPPORT [31:31] */
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_MASK                   0x80000000
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_SHIFT                  31
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_DEFAULT                0x00000001
+
+/* NAND :: REVISION :: reserved0 [30:16] */
+#define BCHP_NAND_REVISION_reserved0_MASK                          0x7fff0000
+#define BCHP_NAND_REVISION_reserved0_SHIFT                         16
+
+/* NAND :: REVISION :: MAJOR [15:08] */
+#define BCHP_NAND_REVISION_MAJOR_MASK                              0x0000ff00
+#define BCHP_NAND_REVISION_MAJOR_SHIFT                             8
+#define BCHP_NAND_REVISION_MAJOR_DEFAULT                           0x00000006
+
+/* NAND :: REVISION :: MINOR [07:00] */
+#define BCHP_NAND_REVISION_MINOR_MASK                              0x000000ff
+#define BCHP_NAND_REVISION_MINOR_SHIFT                             0
+#define BCHP_NAND_REVISION_MINOR_DEFAULT                           0x00000002
+
+/***************************************************************************
+ *CMD_START - Nand Flash Command Start
+ ***************************************************************************/
+/* NAND :: CMD_START :: reserved0 [31:05] */
+#define BCHP_NAND_CMD_START_reserved0_MASK                         0xffffffe0
+#define BCHP_NAND_CMD_START_reserved0_SHIFT                        5
+
+/* NAND :: CMD_START :: OPCODE [04:00] */
+#define BCHP_NAND_CMD_START_OPCODE_MASK                            0x0000001f
+#define BCHP_NAND_CMD_START_OPCODE_SHIFT                           0
+#define BCHP_NAND_CMD_START_OPCODE_DEFAULT                         0x00000000
+#define BCHP_NAND_CMD_START_OPCODE_NULL                            0
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ                       1
+#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ                 2
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ                     3
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE                    4
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA              5
+#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK                       6
+#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ                  7
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE                     8
+#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET                     9
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK                     10
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN                11
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK                   12
+#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS         13
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ                  14
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL            15
+#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP                    16
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ_MULTI                 17
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ_MULTI               18
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE_MULTI              19
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE_MULTI_CACHE        20
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE_MULTI               21
+
+/***************************************************************************
+ *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
+ ***************************************************************************/
+/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK                   0xfff80000
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT                  19
+
+/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK                      0x00070000
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT                     16
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT                   0x00000000
+
+/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK                 0x0000ffff
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT                0
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CMD_ADDRESS - Nand Flash Command Address
+ ***************************************************************************/
+/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK                         0xffffffff
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT                        0
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *CMD_END_ADDRESS - Nand Flash Command End Address
+ ***************************************************************************/
+/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT                    0
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *INTFC_STATUS - Nand Flash Interface Status
+ ***************************************************************************/
+/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK                     0x80000000
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT                    31
+
+/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK                    0x40000000
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT                   30
+
+/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK                    0x20000000
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT                   29
+
+/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK               0x10000000
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT              28
+
+/* NAND :: INTFC_STATUS :: ERASED [27:27] */
+#define BCHP_NAND_INTFC_STATUS_ERASED_MASK                         0x08000000
+#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT                        27
+
+/* NAND :: INTFC_STATUS :: PLANE_READY [26:26] */
+#define BCHP_NAND_INTFC_STATUS_PLANE_READY_MASK                    0x04000000
+#define BCHP_NAND_INTFC_STATUS_PLANE_READY_SHIFT                   26
+
+/* NAND :: INTFC_STATUS :: reserved0 [25:08] */
+#define BCHP_NAND_INTFC_STATUS_reserved0_MASK                      0x03ffff00
+#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT                     8
+
+/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK                   0x000000ff
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT                  0
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *CS_NAND_SELECT - Nand Flash EBI CS Select
+ ***************************************************************************/
+/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT                     31
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK        0x40000000
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT       30
+
+/* NAND :: CS_NAND_SELECT :: reserved0 [29:29] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK                    0x20000000
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT                   29
+
+/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK              0x10000000
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT             28
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT           0x00000000
+
+/* NAND :: CS_NAND_SELECT :: reserved1 [27:16] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_MASK                    0x0fff0000
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_SHIFT                   16
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK           0x00008000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT          15
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK           0x00004000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT          14
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK           0x00002000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT          13
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK           0x00001000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT          12
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK           0x00000800
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT          11
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK           0x00000400
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT          10
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK           0x00000200
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT          9
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK           0x00000100
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT          8
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK                 0x00000080
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT                7
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK                 0x00000040
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT                6
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK                 0x00000020
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT                5
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK                 0x00000010
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT                4
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK                 0x00000008
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT                3
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK                 0x00000004
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT                2
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK                 0x00000002
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT                1
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK                 0x00000001
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT                0
+
+/***************************************************************************
+ *CS_NAND_XOR - Nand Flash EBI CS Address XOR with 1FC0 Control
+ ***************************************************************************/
+/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_1FC0_XOR [31:31] */
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_MASK           0x80000000
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_SHIFT          31
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
+#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK                       0x7fffff00
+#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT                      8
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_1FC0_XOR [07:07] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_MASK          0x00000080
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_SHIFT         7
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_1FC0_XOR [06:06] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_MASK          0x00000040
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_SHIFT         6
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_1FC0_XOR [05:05] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_MASK          0x00000020
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_SHIFT         5
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_1FC0_XOR [04:04] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_MASK          0x00000010
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_SHIFT         4
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_1FC0_XOR [03:03] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_MASK          0x00000008
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_SHIFT         3
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_1FC0_XOR [02:02] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_MASK          0x00000004
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_SHIFT         2
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_1FC0_XOR [01:01] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_MASK          0x00000002
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_SHIFT         1
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_1FC0_XOR [00:00] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_MASK          0x00000001
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_SHIFT         0
+
+/***************************************************************************
+ *LL_OP - Nand Flash Low Level Operation
+ ***************************************************************************/
+/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
+#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK                           0x80000000
+#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT                          31
+#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT                        0x00000000
+
+/* NAND :: LL_OP :: reserved0 [30:20] */
+#define BCHP_NAND_LL_OP_reserved0_MASK                             0x7ff00000
+#define BCHP_NAND_LL_OP_reserved0_SHIFT                            20
+
+/* NAND :: LL_OP :: CLE [19:19] */
+#define BCHP_NAND_LL_OP_CLE_MASK                                   0x00080000
+#define BCHP_NAND_LL_OP_CLE_SHIFT                                  19
+#define BCHP_NAND_LL_OP_CLE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: ALE [18:18] */
+#define BCHP_NAND_LL_OP_ALE_MASK                                   0x00040000
+#define BCHP_NAND_LL_OP_ALE_SHIFT                                  18
+#define BCHP_NAND_LL_OP_ALE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: WE [17:17] */
+#define BCHP_NAND_LL_OP_WE_MASK                                    0x00020000
+#define BCHP_NAND_LL_OP_WE_SHIFT                                   17
+#define BCHP_NAND_LL_OP_WE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: RE [16:16] */
+#define BCHP_NAND_LL_OP_RE_MASK                                    0x00010000
+#define BCHP_NAND_LL_OP_RE_SHIFT                                   16
+#define BCHP_NAND_LL_OP_RE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: DATA [15:00] */
+#define BCHP_NAND_LL_OP_DATA_MASK                                  0x0000ffff
+#define BCHP_NAND_LL_OP_DATA_SHIFT                                 0
+#define BCHP_NAND_LL_OP_DATA_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *MPLANE_BASE_EXT_ADDRESS - Nand Flash Multiplane base address
+ ***************************************************************************/
+/* NAND :: MPLANE_BASE_EXT_ADDRESS :: reserved0 [31:16] */
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_reserved0_MASK           0xffff0000
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_reserved0_SHIFT          16
+
+/* NAND :: MPLANE_BASE_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_MASK         0x0000ffff
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_SHIFT        0
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_DEFAULT      0x00000000
+
+/***************************************************************************
+ *MPLANE_BASE_ADDRESS - Nand Flash Multiplane base address
+ ***************************************************************************/
+/* NAND :: MPLANE_BASE_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_MASK                 0xffffffff
+#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_SHIFT                0
+#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *ACC_CONTROL_CS0 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS0 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS0_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS0_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS0_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: CACHE_MODE_LAST_PAGE [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_LAST_PAGE_MASK        0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_LAST_PAGE_SHIFT       21
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_LAST_PAGE_DEFAULT     0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS0 :: reserved0 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved0_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved0_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS0 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS0 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS0 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS0 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_512KB              4
+#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_256KB              3
+#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_128KB              2
+#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_16KB               1
+#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_8KB                0
+
+/* NAND :: CONFIG_CS0 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS0 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS0 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS0_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS0_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS0 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS0 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS0_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS0_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS0 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS0_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS0_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS0 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS0_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS0_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS0 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS0_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS0_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS0 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS0_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS0_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS0 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS0_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS0_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS0 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS0_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS0_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS0 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS0 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS0_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS0_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS0_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS0 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS0_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS0_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS0_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS0 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS0_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS0_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS0_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS0 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS0_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS0_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS0_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS0 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS0_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS0_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS0_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS0 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS0_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS0_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS0_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS0 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS0_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS0_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS0_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS0 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS0_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS0_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS0_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS0 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS0 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS0 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS0_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS0_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS0 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS0_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS0_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS0_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS0 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS0_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS0_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS0_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS0 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS0_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS0_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS0_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS1 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: CACHE_MODE_LAST_PAGE [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_LAST_PAGE_MASK        0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_LAST_PAGE_SHIFT       21
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_LAST_PAGE_DEFAULT     0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved0 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS1 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS1 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_512KB              4
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_256KB              3
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_128KB              2
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_16KB               1
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_8KB                0
+
+/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS1 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS1_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS1 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS1 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS1_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS1_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS1_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS1_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS1_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS1_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS1_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS1_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS1_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS1_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS1_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS1 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS1 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS1_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS2 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: CACHE_MODE_LAST_PAGE [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_LAST_PAGE_MASK        0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_LAST_PAGE_SHIFT       21
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_LAST_PAGE_DEFAULT     0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved0 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS2 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS2 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_512KB              4
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_256KB              3
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_128KB              2
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_16KB               1
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_8KB                0
+
+/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS2 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS2_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS2 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS2 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS2_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS2_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS2_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS2_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS2 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS2_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS2_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS2_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS2_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS2_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS2_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS2_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS2_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS3 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: CACHE_MODE_LAST_PAGE [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_LAST_PAGE_MASK        0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_LAST_PAGE_SHIFT       21
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_LAST_PAGE_DEFAULT     0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved0 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS3 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS3 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_512KB              4
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_256KB              3
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_128KB              2
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_16KB               1
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_8KB                0
+
+/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS3 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS3_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS3 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS3 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS3_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS3_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS3_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS3_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS3 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS3_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS3_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS3_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS3_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS3_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS3_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS3_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS3 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS3 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS3_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS4 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: CACHE_MODE_LAST_PAGE [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_LAST_PAGE_MASK        0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_LAST_PAGE_SHIFT       21
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_LAST_PAGE_DEFAULT     0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved0 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS4 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS4 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_512KB              4
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_256KB              3
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_128KB              2
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_16KB               1
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_8KB                0
+
+/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS4 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS4_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS4 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS4 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS4_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS4_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS4_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS4_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS4 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS4_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS4_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS4_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS4_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS4_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS4_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS4_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS4 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS4 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS4_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS5 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS5 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: CACHE_MODE_LAST_PAGE [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_LAST_PAGE_MASK        0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_LAST_PAGE_SHIFT       21
+#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_LAST_PAGE_DEFAULT     0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved0 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS5 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS5 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS5 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS5 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_512KB              4
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_256KB              3
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_128KB              2
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_16KB               1
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_8KB                0
+
+/* NAND :: CONFIG_CS5 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS5 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS5 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS5_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS5_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS5 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS5 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS5_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS5_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS5 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS5 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS5_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS5_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS5 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS5 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS5_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS5_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS5 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS5 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS5_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS5_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS5 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS5 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS5_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS5_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS5_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS5 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS5_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS5_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS5_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS5 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS5_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS5_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS5_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS5 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS5_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS5_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS5_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS5 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS5_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS5_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS5_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS5 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS5_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS5_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS5_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS5 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS5_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS5_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS5_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS5 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS5_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS5_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS5_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS5 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS5 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS5 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS5_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS5_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS5 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS5_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS5_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS5_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS5 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS5_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS5_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS5_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS5 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS5_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS5_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS5_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:30] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK               0xc0000000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT              30
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS4 [29:24] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_MASK 0x3f000000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_SHIFT 24
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS3 [23:18] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_MASK 0x00fc0000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_SHIFT 18
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS2 [17:12] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_MASK 0x0003f000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_SHIFT 12
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS1 [11:06] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_MASK 0x00000fc0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_SHIFT 6
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS0 [05:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_MASK 0x0000003f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_SHIFT 0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD_EXT - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD_EXT :: reserved0 [31:06] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_reserved0_MASK           0xffffffc0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_reserved0_SHIFT          6
+
+/* NAND :: CORR_STAT_THRESHOLD_EXT :: CORR_STAT_THRESHOLD_CS5 [05:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_MASK 0x0000003f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_SHIFT 0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_DEFAULT 0x00000001
+
+/***************************************************************************
+ *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
+ ***************************************************************************/
+/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK                 0xffffffff
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT                0
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *MULTIPLANE_OPCODES_1 - Nand Flash Multiplane Customerized Opcodes
+ ***************************************************************************/
+/* NAND :: MULTIPLANE_OPCODES_1 :: ERASE_CYC2_OPCODE [31:24] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_MASK      0xff000000
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_SHIFT     24
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_DEFAULT   0x000000d1
+
+/* NAND :: MULTIPLANE_OPCODES_1 :: READ_STATUS_OPCODE [23:16] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_MASK     0x00ff0000
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_SHIFT    16
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_DEFAULT  0x00000070
+
+/* NAND :: MULTIPLANE_OPCODES_1 :: PROG_ODD_PLANE_OPCODE [15:08] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_MASK  0x0000ff00
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_SHIFT 8
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_DEFAULT 0x00000080
+
+/* NAND :: MULTIPLANE_OPCODES_1 :: PROG_TR_OPCODE [07:00] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_MASK         0x000000ff
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_SHIFT        0
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_DEFAULT      0x00000010
+
+/***************************************************************************
+ *MULTIPLANE_OPCODES_2 - Nand Flash Multiplane Customerized Opcodes
+ ***************************************************************************/
+/* NAND :: MULTIPLANE_OPCODES_2 :: PROG_CACHE_TR_OPCODE [31:24] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_MASK   0xff000000
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_SHIFT  24
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_DEFAULT 0x00000015
+
+/* NAND :: MULTIPLANE_OPCODES_2 :: TWO_PLANE_READ_STATUS_OPCODE [23:16] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_MASK 0x00ff0000
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_SHIFT 16
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_DEFAULT 0x00000078
+
+/* NAND :: MULTIPLANE_OPCODES_2 :: READ_OPCODE [15:08] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_MASK            0x0000ff00
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_SHIFT           8
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_DEFAULT         0x00000000
+
+/* NAND :: MULTIPLANE_OPCODES_2 :: READ_RAND_OPCODE [07:00] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_MASK       0x000000ff
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_SHIFT      0
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *MULTIPLANE_CTRL - Nand Flash Multiplane Control
+ ***************************************************************************/
+/* NAND :: MULTIPLANE_CTRL :: ERASE_CYC2_OP_ENABLE [31:31] */
+#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_MASK        0x80000000
+#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_SHIFT       31
+#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_DEFAULT     0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: READ_ADR_SIZE [30:30] */
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_MASK               0x40000000
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_SHIFT              30
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_DEFAULT            0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: READ_CYC_ADR_FLAG [29:29] */
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_MASK           0x20000000
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_SHIFT          29
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_DEFAULT        0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: READ_NEXT_PAGE_FLAG [28:28] */
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_MASK         0x10000000
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_SHIFT        28
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_DEFAULT      0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: reserved0 [27:00] */
+#define BCHP_NAND_MULTIPLANE_CTRL_reserved0_MASK                   0x0fffffff
+#define BCHP_NAND_MULTIPLANE_CTRL_reserved0_SHIFT                  0
+
+/***************************************************************************
+ *UNCORR_ERROR_COUNT - Read Uncorrectable Event Count
+ ***************************************************************************/
+/* NAND :: UNCORR_ERROR_COUNT :: UNCORR_ERROR_COUNT [31:00] */
+#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_MASK       0xffffffff
+#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_SHIFT      0
+#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *CORR_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: CORR_ERROR_COUNT :: CORR_ERROR_COUNT [31:00] */
+#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *READ_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
+ ***************************************************************************/
+/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT                8
+
+/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK                    0x000000ff
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT                   0
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ECC_CORR_ADDR - ECC Correctable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK                  0xfff80000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT                 19
+
+/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK                     0x00070000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT                    16
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT                  0x00000000
+
+/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK                0x0000ffff
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT               0
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT             0x00000000
+
+/***************************************************************************
+ *ECC_UNC_ADDR - ECC Uncorrectable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK                        0xffffffff
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT                       0
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK               0xfff80000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT              19
+
+/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK                  0x00070000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT                 16
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT               0x00000000
+
+/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK             0x0000ffff
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT            0
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT          0x00000000
+
+/***************************************************************************
+ *FLASH_READ_ADDR - Flash Read Data Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT                    0
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK             0xfff80000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT            19
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK                0x00070000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT               16
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT             0x00000000
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK           0x0000ffff
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT          0
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_ADDR - Page Program Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK                   0xffffffff
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT                  0
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *COPY_BACK_EXT_ADDR - Copy Back Extended Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK                0xfff80000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT               19
+
+/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK                   0x00070000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT                  16
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT                0x00000000
+
+/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK              0x0000ffff
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT             0
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT           0x00000000
+
+/***************************************************************************
+ *COPY_BACK_ADDR - Copy Back Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK                      0xffffffff
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT                     0
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK              0xfff80000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT             19
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK                 0x00070000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT                16
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT              0x00000000
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK            0x0000ffff
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT           0
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_ADDR - Block Erase Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK                    0xffffffff
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT                   0
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
+ ***************************************************************************/
+/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *INV_READ_ADDR - Flash Invalid Data Address
+ ***************************************************************************/
+/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *INIT_STATUS - Initialization status
+ ***************************************************************************/
+/* NAND :: INIT_STATUS :: ONFI_INIT_DONE [31:31] */
+#define BCHP_NAND_INIT_STATUS_ONFI_INIT_DONE_MASK                  0x80000000
+#define BCHP_NAND_INIT_STATUS_ONFI_INIT_DONE_SHIFT                 31
+
+/* NAND :: INIT_STATUS :: DEVICE_ID_INIT_DONE [30:30] */
+#define BCHP_NAND_INIT_STATUS_DEVICE_ID_INIT_DONE_MASK             0x40000000
+#define BCHP_NAND_INIT_STATUS_DEVICE_ID_INIT_DONE_SHIFT            30
+
+/* NAND :: INIT_STATUS :: INIT_SUCCESS [29:29] */
+#define BCHP_NAND_INIT_STATUS_INIT_SUCCESS_MASK                    0x20000000
+#define BCHP_NAND_INIT_STATUS_INIT_SUCCESS_SHIFT                   29
+
+/* NAND :: INIT_STATUS :: INIT_FAIL [28:28] */
+#define BCHP_NAND_INIT_STATUS_INIT_FAIL_MASK                       0x10000000
+#define BCHP_NAND_INIT_STATUS_INIT_FAIL_SHIFT                      28
+
+/* NAND :: INIT_STATUS :: INIT_BLANK [27:27] */
+#define BCHP_NAND_INIT_STATUS_INIT_BLANK_MASK                      0x08000000
+#define BCHP_NAND_INIT_STATUS_INIT_BLANK_SHIFT                     27
+
+/* NAND :: INIT_STATUS :: INIT_TIMEOUT [26:26] */
+#define BCHP_NAND_INIT_STATUS_INIT_TIMEOUT_MASK                    0x04000000
+#define BCHP_NAND_INIT_STATUS_INIT_TIMEOUT_SHIFT                   26
+
+/* NAND :: INIT_STATUS :: INIT_UNC_ERROR [25:25] */
+#define BCHP_NAND_INIT_STATUS_INIT_UNC_ERROR_MASK                  0x02000000
+#define BCHP_NAND_INIT_STATUS_INIT_UNC_ERROR_SHIFT                 25
+
+/* NAND :: INIT_STATUS :: INIT_CORR_ERROR [24:24] */
+#define BCHP_NAND_INIT_STATUS_INIT_CORR_ERROR_MASK                 0x01000000
+#define BCHP_NAND_INIT_STATUS_INIT_CORR_ERROR_SHIFT                24
+
+/* NAND :: INIT_STATUS :: PARAMETER_READY [23:23] */
+#define BCHP_NAND_INIT_STATUS_PARAMETER_READY_MASK                 0x00800000
+#define BCHP_NAND_INIT_STATUS_PARAMETER_READY_SHIFT                23
+
+/* NAND :: INIT_STATUS :: AUTHENTICATION_FAIL [22:22] */
+#define BCHP_NAND_INIT_STATUS_AUTHENTICATION_FAIL_MASK             0x00400000
+#define BCHP_NAND_INIT_STATUS_AUTHENTICATION_FAIL_SHIFT            22
+
+/* NAND :: INIT_STATUS :: reserved0 [21:00] */
+#define BCHP_NAND_INIT_STATUS_reserved0_MASK                       0x003fffff
+#define BCHP_NAND_INIT_STATUS_reserved0_SHIFT                      0
+
+/***************************************************************************
+ *ONFI_STATUS - ONFI Status
+ ***************************************************************************/
+/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK                  0xf0000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT                 28
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT               0x00000000
+
+/* NAND :: ONFI_STATUS :: ONFI_detected [27:27] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_detected_MASK                   0x08000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_detected_SHIFT                  27
+
+/* NAND :: ONFI_STATUS :: reserved0 [26:06] */
+#define BCHP_NAND_ONFI_STATUS_reserved0_MASK                       0x07ffffc0
+#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT                      6
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK              0x00000020
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT             5
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK              0x00000010
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT             4
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK              0x00000008
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT             3
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK              0x00000004
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT             2
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK              0x00000002
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT             1
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK              0x00000001
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT             0
+
+/***************************************************************************
+ *ONFI_DEBUG_DATA - ONFI Debug Data
+ ***************************************************************************/
+/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK             0xffffffff
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT            0
+
+/***************************************************************************
+ *SEMAPHORE - Semaphore
+ ***************************************************************************/
+/* NAND :: SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_NAND_SEMAPHORE_reserved0_MASK                         0xffffff00
+#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT                        8
+
+/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK                    0x000000ff
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT                   0
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *FLASH_DEVICE_ID - Nand Flash Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK                      0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT                     24
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK                      0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT                     16
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK                      0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT                     8
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK                      0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT                     0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK                  0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT                 24
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK                  0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT                 16
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK                  0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT                 8
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK                  0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT                 0
+
+/***************************************************************************
+ *LL_RDDATA - Nand Flash Low Level Read Data
+ ***************************************************************************/
+/* NAND :: LL_RDDATA :: reserved0 [31:16] */
+#define BCHP_NAND_LL_RDDATA_reserved0_MASK                         0xffff0000
+#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT                        16
+
+/* NAND :: LL_RDDATA :: DATA [15:00] */
+#define BCHP_NAND_LL_RDDATA_DATA_MASK                              0x0000ffff
+#define BCHP_NAND_LL_RDDATA_DATA_SHIFT                             0
+#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_20 - Nand Flash Spare Area Read Bytes 32-35
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_32 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_33 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_34 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_35 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_24 - Nand Flash Spare Area Read Bytes 36-39
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_36 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_37 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_38 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_39 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_28 - Nand Flash Spare Area Read Bytes 40-43
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_40 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_41 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_42 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_43 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_2C - Nand Flash Spare Area Read Bytes 44-47
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_44 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_45 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_46 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_47 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_30 - Nand Flash Spare Area Read Bytes 48-51
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_48 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_49 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_50 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_51 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_34 - Nand Flash Spare Area Read Bytes 52-55
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_52 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_53 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_54 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_55 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_38 - Nand Flash Spare Area Read Bytes 56-59
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_56 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_57 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_58 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_59 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_3C - Nand Flash Spare Area Read Bytes 60-63
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_60 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_61 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_62 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_63 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_20 - Nand Flash Spare Area Write Bytes 32-35
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_32 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_33 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_34 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_35 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_24 - Nand Flash Spare Area Write Bytes 36-39
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_36 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_37 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_38 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_39 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_28 - Nand Flash Spare Area Write Bytes 40-43
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_40 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_41 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_42 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_43 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_2C - Nand Flash Spare Area Write Bytes 44-47
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_44 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_45 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_46 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_47 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_30 - Nand Flash Spare Area Write Bytes 48-51
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_48 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_49 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_50 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_51 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_34 - Nand Flash Spare Area Write Bytes 52-55
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_52 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_53 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_54 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_55 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_38 - Nand Flash Spare Area Write Bytes 56-59
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_56 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_57 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_58 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_59 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_3C - Nand Flash Spare Area Write Bytes 60-63
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_60 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_61 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_62 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_63 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE                          0x0041cc00
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_START                         0
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_END                           127
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE                  32
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+/* NAND :: FLASH_CACHEi :: WORD [31:00] */
+#define BCHP_NAND_FLASH_CACHEi_WORD_MASK                           0xffffffff
+#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT                          0
+
+
+#endif /* #ifndef BCHP_NAND_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_pcie_dma.h b/include/linux/brcmstb/7435b0/bchp_pcie_dma.h
new file mode 100644
index 0000000..ee1c3bf
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_pcie_dma.h
@@ -0,0 +1,710 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:31 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_pcie_dma.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 3:22p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_PCIE_DMA_H__
+#define BCHP_PCIE_DMA_H__
+
+/***************************************************************************
+ *PCIE_DMA - PCI-E DMA Registers
+ ***************************************************************************/
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST0 0x00414400 /* Tx Descriptor List0 First Descriptor lower Address */
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_U_ADDR_LIST0 0x00414404 /* Tx Descriptor List0 First Descriptor Upper Address */
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST1 0x00414408 /* Tx Descriptor List1 First Descriptor Lower Address */
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_U_ADDR_LIST1 0x0041440c /* Tx Descriptor List1 First Descriptor Upper Address */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS   0x00414410 /* Tx Software Descriptor List Control and Status */
+#define BCHP_PCIE_DMA_TX_WAKE_CTRL               0x00414414 /* Tx Wake Control */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS            0x00414418 /* Tx Engine Error Status */
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR   0x0041441c /* Tx List0 Current Descriptor Lower Address */
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_U_ADDR   0x00414420 /* Tx List0 Current Descriptor Upper Address */
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_BYTE_CNT      0x00414424 /* Tx List0 Current Descriptor Byte Count */
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR   0x00414428 /* Tx List1 Current Descriptor Lower Address */
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_U_ADDR   0x0041442c /* Tx List1 Current Descriptor Upper Address */
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_BYTE_CNT      0x00414430 /* Tx List1 Current Descriptor Byte Count */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST0 0x00414434 /* Rx Descriptor List0 First Descriptor Lower Address */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_U_ADDR_LIST0 0x00414438 /* Rx Descriptor List0 First Descriptor Upper Address */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST1 0x0041443c /* Rx Descriptor List1 First Descriptor Lower Address */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_U_ADDR_LIST1 0x00414440 /* Rx Descriptor List1 First Descriptor Upper Address */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS   0x00414444 /* Rx Software Descriptor List Control and Status */
+#define BCHP_PCIE_DMA_RX_WAKE_CTRL               0x00414448 /* Rx DMA Wake Control */
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS            0x0041444c /* Rx Engine Error Status */
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR   0x00414450 /* Rx List0 Current Descriptor Lower Address */
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_U_ADDR   0x00414454 /* Rx List0 Current Descriptor Upper Address */
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_BYTE_CNT      0x00414458 /* Rx List0 Current Descriptor Byte Count */
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR   0x0041445c /* Rx List1 Current Descriptor Lower address */
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_U_ADDR   0x00414460 /* Rx List1 Current Descriptor Upper address */
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_BYTE_CNT      0x00414464 /* Rx List1 Current Descriptor Byte Count */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG      0x00414468 /* DMA Debug Options Register */
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS  0x0041446c /* Read Channel Error Status */
+
+/***************************************************************************
+ *TX_FIRST_DESC_L_ADDR_LIST0 - Tx Descriptor List0 First Descriptor lower Address
+ ***************************************************************************/
+/* PCIE_DMA :: TX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK    0xffffffe0
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT   5
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK    0x0000001e
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT   1
+
+/* PCIE_DMA :: TX_FIRST_DESC_L_ADDR_LIST0 :: TX_DESC_LIST0_VALID [00:00] */
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_MASK 0x00000001
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_SHIFT 0
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TX_FIRST_DESC_U_ADDR_LIST0 - Tx Descriptor List0 First Descriptor Upper Address
+ ***************************************************************************/
+/* PCIE_DMA :: TX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK    0xffffffff
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT   0
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TX_FIRST_DESC_L_ADDR_LIST1 - Tx Descriptor List1 First Descriptor Lower Address
+ ***************************************************************************/
+/* PCIE_DMA :: TX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK    0xffffffe0
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT   5
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK    0x0000001e
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT   1
+
+/* PCIE_DMA :: TX_FIRST_DESC_L_ADDR_LIST1 :: TX_DESC_LIST1_VALID [00:00] */
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_MASK 0x00000001
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_SHIFT 0
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TX_FIRST_DESC_U_ADDR_LIST1 - Tx Descriptor List1 First Descriptor Upper Address
+ ***************************************************************************/
+/* PCIE_DMA :: TX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK    0xffffffff
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT   0
+#define BCHP_PCIE_DMA_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TX_SW_DESC_LIST_CTRL_STS - Tx Software Descriptor List Control and Status
+ ***************************************************************************/
+/* PCIE_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:14] */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved0_MASK      0xffffc000
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT     14
+
+/* PCIE_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DESC_ENDIAN_MODE [13:12] */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_MASK 0x00003000
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_SHIFT 12
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved1 [11:10] */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved1_MASK      0x00000c00
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved1_SHIFT     10
+
+/* PCIE_DMA :: TX_SW_DESC_LIST_CTRL_STS :: LOCAL_DESC [09:09] */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_MASK     0x00000200
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_SHIFT    9
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_DEFAULT  0x00000000
+
+/* PCIE_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DMA_MODE [08:08] */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_MODE_MASK       0x00000100
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_MODE_SHIFT      8
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_MODE_DEFAULT    0x00000000
+
+/* PCIE_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved2 [07:06] */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved2_MASK      0x000000c0
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved2_SHIFT     6
+
+/* PCIE_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DMA_STATUS [05:04] */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_MASK     0x00000030
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_SHIFT    4
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_DEFAULT  0x00000000
+
+/* PCIE_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK  0x00000004
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_SW_DESC_LIST_CTRL_STS :: reserved3 [01:01] */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved3_MASK      0x00000002
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_reserved3_SHIFT     1
+
+/* PCIE_DMA :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_RUN_STOP [00:00] */
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK 0x00000001
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_SHIFT 0
+#define BCHP_PCIE_DMA_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TX_WAKE_CTRL - Tx Wake Control
+ ***************************************************************************/
+/* PCIE_DMA :: TX_WAKE_CTRL :: reserved0 [31:02] */
+#define BCHP_PCIE_DMA_TX_WAKE_CTRL_reserved0_MASK                  0xfffffffc
+#define BCHP_PCIE_DMA_TX_WAKE_CTRL_reserved0_SHIFT                 2
+
+/* PCIE_DMA :: TX_WAKE_CTRL :: WAKE_MODE [01:01] */
+#define BCHP_PCIE_DMA_TX_WAKE_CTRL_WAKE_MODE_MASK                  0x00000002
+#define BCHP_PCIE_DMA_TX_WAKE_CTRL_WAKE_MODE_SHIFT                 1
+#define BCHP_PCIE_DMA_TX_WAKE_CTRL_WAKE_MODE_DEFAULT               0x00000000
+
+/* PCIE_DMA :: TX_WAKE_CTRL :: WAKE [00:00] */
+#define BCHP_PCIE_DMA_TX_WAKE_CTRL_WAKE_MASK                       0x00000001
+#define BCHP_PCIE_DMA_TX_WAKE_CTRL_WAKE_SHIFT                      0
+#define BCHP_PCIE_DMA_TX_WAKE_CTRL_WAKE_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *TX_ERROR_STATUS - Tx Engine Error Status
+ ***************************************************************************/
+/* PCIE_DMA :: TX_ERROR_STATUS :: reserved0 [31:10] */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_reserved0_MASK               0xfffffc00
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_reserved0_SHIFT              10
+
+/* PCIE_DMA :: TX_ERROR_STATUS :: TX_L1_DESC_TX_ABORT_ERRORS [09:09] */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_ERROR_STATUS :: reserved1 [08:08] */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_reserved1_MASK               0x00000100
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_reserved1_SHIFT              8
+
+/* PCIE_DMA :: TX_ERROR_STATUS :: TX_L0_DESC_TX_ABORT_ERRORS [07:07] */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_ERROR_STATUS :: reserved2 [06:06] */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_reserved2_MASK               0x00000040
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_reserved2_SHIFT              6
+
+/* PCIE_DMA :: TX_ERROR_STATUS :: TX_L1_DATA_TX_ABORT_ERRORS [05:05] */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L1_DATA_TX_ABORT_ERRORS_MASK 0x00000020
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L1_DATA_TX_ABORT_ERRORS_SHIFT 5
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L1_DATA_TX_ABORT_ERRORS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_ERROR_STATUS :: TX_L1_REPIN_ERRORS [04:04] */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L1_REPIN_ERRORS_MASK      0x00000010
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L1_REPIN_ERRORS_SHIFT     4
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L1_REPIN_ERRORS_DEFAULT   0x00000000
+
+/* PCIE_DMA :: TX_ERROR_STATUS :: reserved3 [03:03] */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_reserved3_MASK               0x00000008
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_reserved3_SHIFT              3
+
+/* PCIE_DMA :: TX_ERROR_STATUS :: TX_L0_DATA_TX_ABORT_ERRORS [02:02] */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L0_DATA_TX_ABORT_ERRORS_MASK 0x00000004
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L0_DATA_TX_ABORT_ERRORS_SHIFT 2
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L0_DATA_TX_ABORT_ERRORS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_ERROR_STATUS :: TX_L0_REPIN_ERRORS [01:01] */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L0_REPIN_ERRORS_MASK      0x00000002
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L0_REPIN_ERRORS_SHIFT     1
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_TX_L0_REPIN_ERRORS_DEFAULT   0x00000000
+
+/* PCIE_DMA :: TX_ERROR_STATUS :: reserved4 [00:00] */
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_reserved4_MASK               0x00000001
+#define BCHP_PCIE_DMA_TX_ERROR_STATUS_reserved4_SHIFT              0
+
+/***************************************************************************
+ *TX_LIST0_CUR_DESC_L_ADDR - Tx List0 Current Descriptor Lower Address
+ ***************************************************************************/
+/* PCIE_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: TX_L0_CUR_DESC_L_ADDR [31:05] */
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_DESC_L_ADDR_SHIFT 5
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_DESC_L_ADDR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:04] */
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK      0x00000010
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT     4
+
+/* PCIE_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: TX_L0_CUR_LIST [03:03] */
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_LIST_MASK 0x00000008
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_LIST_SHIFT 3
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_LIST_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: TX_L0_CUR_IN_PROGRESS [02:02] */
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_IN_PROGRESS_MASK 0x00000004
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_IN_PROGRESS_SHIFT 2
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_IN_PROGRESS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_LIST0_CUR_DESC_L_ADDR :: TX_L0_CUR_STATUS [01:00] */
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_STATUS_MASK 0x00000003
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_STATUS_SHIFT 0
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_L_ADDR_TX_L0_CUR_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TX_LIST0_CUR_DESC_U_ADDR - Tx List0 Current Descriptor Upper Address
+ ***************************************************************************/
+/* PCIE_DMA :: TX_LIST0_CUR_DESC_U_ADDR :: TX_L0_CUR_DESC_U_ADDR [31:00] */
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_U_ADDR_TX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_U_ADDR_TX_L0_CUR_DESC_U_ADDR_SHIFT 0
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_DESC_U_ADDR_TX_L0_CUR_DESC_U_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TX_LIST0_CUR_BYTE_CNT - Tx List0 Current Descriptor Byte Count
+ ***************************************************************************/
+/* PCIE_DMA :: TX_LIST0_CUR_BYTE_CNT :: TX_L0_CUR_BYTE_CNT [31:00] */
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_BYTE_CNT_TX_L0_CUR_BYTE_CNT_MASK 0xffffffff
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_BYTE_CNT_TX_L0_CUR_BYTE_CNT_SHIFT 0
+#define BCHP_PCIE_DMA_TX_LIST0_CUR_BYTE_CNT_TX_L0_CUR_BYTE_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TX_LIST1_CUR_DESC_L_ADDR - Tx List1 Current Descriptor Lower Address
+ ***************************************************************************/
+/* PCIE_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: TX_L1_CUR_DESC_L_ADDR [31:05] */
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_DESC_L_ADDR_SHIFT 5
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_DESC_L_ADDR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:04] */
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK      0x00000010
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT     4
+
+/* PCIE_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: TX_L1_CUR_LIST [03:03] */
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_LIST_MASK 0x00000008
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_LIST_SHIFT 3
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_LIST_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: TX_L1_CUR_IN_PROGRESS [02:02] */
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_IN_PROGRESS_MASK 0x00000004
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_IN_PROGRESS_SHIFT 2
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_IN_PROGRESS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: TX_LIST1_CUR_DESC_L_ADDR :: TX_L1_CUR_STATUS [01:00] */
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_STATUS_MASK 0x00000003
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_STATUS_SHIFT 0
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_L_ADDR_TX_L1_CUR_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TX_LIST1_CUR_DESC_U_ADDR - Tx List1 Current Descriptor Upper Address
+ ***************************************************************************/
+/* PCIE_DMA :: TX_LIST1_CUR_DESC_U_ADDR :: TX_L1_CUR_DESC_U_ADDR [31:00] */
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_U_ADDR_TX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_U_ADDR_TX_L1_CUR_DESC_U_ADDR_SHIFT 0
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_DESC_U_ADDR_TX_L1_CUR_DESC_U_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TX_LIST1_CUR_BYTE_CNT - Tx List1 Current Descriptor Byte Count
+ ***************************************************************************/
+/* PCIE_DMA :: TX_LIST1_CUR_BYTE_CNT :: TX_L1_CUR_BYTE_CNT [31:00] */
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_BYTE_CNT_TX_L1_CUR_BYTE_CNT_MASK 0xffffffff
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_BYTE_CNT_TX_L1_CUR_BYTE_CNT_SHIFT 0
+#define BCHP_PCIE_DMA_TX_LIST1_CUR_BYTE_CNT_TX_L1_CUR_BYTE_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_FIRST_DESC_L_ADDR_LIST0 - Rx Descriptor List0 First Descriptor Lower Address
+ ***************************************************************************/
+/* PCIE_DMA :: RX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK    0xffffffe0
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT   5
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK    0x0000001e
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT   1
+
+/* PCIE_DMA :: RX_FIRST_DESC_L_ADDR_LIST0 :: RX_DESC_LIST0_VALID [00:00] */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_MASK 0x00000001
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_SHIFT 0
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_FIRST_DESC_U_ADDR_LIST0 - Rx Descriptor List0 First Descriptor Upper Address
+ ***************************************************************************/
+/* PCIE_DMA :: RX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK    0xffffffff
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT   0
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_FIRST_DESC_L_ADDR_LIST1 - Rx Descriptor List1 First Descriptor Lower Address
+ ***************************************************************************/
+/* PCIE_DMA :: RX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK    0xffffffe0
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT   5
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK    0x0000001e
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT   1
+
+/* PCIE_DMA :: RX_FIRST_DESC_L_ADDR_LIST1 :: RX_DESC_LIST1_VALID [00:00] */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_MASK 0x00000001
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_SHIFT 0
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_FIRST_DESC_U_ADDR_LIST1 - Rx Descriptor List1 First Descriptor Upper Address
+ ***************************************************************************/
+/* PCIE_DMA :: RX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK    0xffffffff
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT   0
+#define BCHP_PCIE_DMA_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_SW_DESC_LIST_CTRL_STS - Rx Software Descriptor List Control and Status
+ ***************************************************************************/
+/* PCIE_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:14] */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved0_MASK      0xffffc000
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT     14
+
+/* PCIE_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DESC_ENDIAN_MODE [13:12] */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_MASK 0x00003000
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_SHIFT 12
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_ENDIAN_MODE_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved1 [11:10] */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved1_MASK      0x00000c00
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved1_SHIFT     10
+
+/* PCIE_DMA :: RX_SW_DESC_LIST_CTRL_STS :: LOCAL_DESC [09:09] */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_MASK     0x00000200
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_SHIFT    9
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_LOCAL_DESC_DEFAULT  0x00000000
+
+/* PCIE_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DMA_MODE [08:08] */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_MODE_MASK       0x00000100
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_MODE_SHIFT      8
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_MODE_DEFAULT    0x00000000
+
+/* PCIE_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved2 [07:06] */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved2_MASK      0x000000c0
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved2_SHIFT     6
+
+/* PCIE_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DMA_STATUS [05:04] */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_MASK     0x00000030
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_SHIFT    4
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_STATUS_DEFAULT  0x00000000
+
+/* PCIE_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK  0x00000004
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_SW_DESC_LIST_CTRL_STS :: reserved3 [01:01] */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved3_MASK      0x00000002
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_reserved3_SHIFT     1
+
+/* PCIE_DMA :: RX_SW_DESC_LIST_CTRL_STS :: RX_DMA_RUN_STOP [00:00] */
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_RX_DMA_RUN_STOP_MASK 0x00000001
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_RX_DMA_RUN_STOP_SHIFT 0
+#define BCHP_PCIE_DMA_RX_SW_DESC_LIST_CTRL_STS_RX_DMA_RUN_STOP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_WAKE_CTRL - Rx DMA Wake Control
+ ***************************************************************************/
+/* PCIE_DMA :: RX_WAKE_CTRL :: reserved0 [31:02] */
+#define BCHP_PCIE_DMA_RX_WAKE_CTRL_reserved0_MASK                  0xfffffffc
+#define BCHP_PCIE_DMA_RX_WAKE_CTRL_reserved0_SHIFT                 2
+
+/* PCIE_DMA :: RX_WAKE_CTRL :: WAKE_MODE [01:01] */
+#define BCHP_PCIE_DMA_RX_WAKE_CTRL_WAKE_MODE_MASK                  0x00000002
+#define BCHP_PCIE_DMA_RX_WAKE_CTRL_WAKE_MODE_SHIFT                 1
+#define BCHP_PCIE_DMA_RX_WAKE_CTRL_WAKE_MODE_DEFAULT               0x00000000
+
+/* PCIE_DMA :: RX_WAKE_CTRL :: WAKE [00:00] */
+#define BCHP_PCIE_DMA_RX_WAKE_CTRL_WAKE_MASK                       0x00000001
+#define BCHP_PCIE_DMA_RX_WAKE_CTRL_WAKE_SHIFT                      0
+#define BCHP_PCIE_DMA_RX_WAKE_CTRL_WAKE_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *RX_ERROR_STATUS - Rx Engine Error Status
+ ***************************************************************************/
+/* PCIE_DMA :: RX_ERROR_STATUS :: reserved0 [31:10] */
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_reserved0_MASK               0xfffffc00
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_reserved0_SHIFT              10
+
+/* PCIE_DMA :: RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_ERROR_STATUS :: reserved1 [08:08] */
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_reserved1_MASK               0x00000100
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_reserved1_SHIFT              8
+
+/* PCIE_DMA :: RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_ERROR_STATUS :: reserved2 [06:06] */
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_reserved2_MASK               0x00000040
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_reserved2_SHIFT              6
+
+/* PCIE_DMA :: RX_ERROR_STATUS :: RX_L1_DATA_TX_ABORT_ERRORS [05:05] */
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L1_DATA_TX_ABORT_ERRORS_MASK 0x00000020
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L1_DATA_TX_ABORT_ERRORS_SHIFT 5
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L1_DATA_TX_ABORT_ERRORS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_ERROR_STATUS :: reserved3 [04:03] */
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_reserved3_MASK               0x00000018
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_reserved3_SHIFT              3
+
+/* PCIE_DMA :: RX_ERROR_STATUS :: RX_L0_DATA_TX_ABORT_ERRORS [02:02] */
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L0_DATA_TX_ABORT_ERRORS_MASK 0x00000004
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L0_DATA_TX_ABORT_ERRORS_SHIFT 2
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_RX_L0_DATA_TX_ABORT_ERRORS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_ERROR_STATUS :: reserved4 [01:00] */
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_reserved4_MASK               0x00000003
+#define BCHP_PCIE_DMA_RX_ERROR_STATUS_reserved4_SHIFT              0
+
+/***************************************************************************
+ *RX_LIST0_CUR_DESC_L_ADDR - Rx List0 Current Descriptor Lower Address
+ ***************************************************************************/
+/* PCIE_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_DESC_L_ADDR [31:05] */
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_SHIFT 5
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:04] */
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK      0x00000010
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT     4
+
+/* PCIE_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_LIST [03:03] */
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_LIST_MASK 0x00000008
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_LIST_SHIFT 3
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_LIST_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_IN_PROGRESS [02:02] */
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_IN_PROGRESS_MASK 0x00000004
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_IN_PROGRESS_SHIFT 2
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_IN_PROGRESS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_STATUS [01:00] */
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_STATUS_MASK 0x00000003
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_STATUS_SHIFT 0
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_LIST0_CUR_DESC_U_ADDR - Rx List0 Current Descriptor Upper Address
+ ***************************************************************************/
+/* PCIE_DMA :: RX_LIST0_CUR_DESC_U_ADDR :: RX_L0_CUR_DESC_U_ADDR [31:00] */
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_SHIFT 0
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_LIST0_CUR_BYTE_CNT - Rx List0 Current Descriptor Byte Count
+ ***************************************************************************/
+/* PCIE_DMA :: RX_LIST0_CUR_BYTE_CNT :: RX_L0_CUR_BYTE_CNT [31:00] */
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_MASK 0xffffffff
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_SHIFT 0
+#define BCHP_PCIE_DMA_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_LIST1_CUR_DESC_L_ADDR - Rx List1 Current Descriptor Lower address
+ ***************************************************************************/
+/* PCIE_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_DESC_L_ADDR [31:05] */
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_SHIFT 5
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:04] */
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK      0x00000010
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT     4
+
+/* PCIE_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_LIST [03:03] */
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_LIST_MASK 0x00000008
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_LIST_SHIFT 3
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_LIST_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_IN_PROGRESS [02:02] */
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_IN_PROGRESS_MASK 0x00000004
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_IN_PROGRESS_SHIFT 2
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_IN_PROGRESS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_STATUS [01:00] */
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_STATUS_MASK 0x00000003
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_STATUS_SHIFT 0
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_LIST1_CUR_DESC_U_ADDR - Rx List1 Current Descriptor Upper address
+ ***************************************************************************/
+/* PCIE_DMA :: RX_LIST1_CUR_DESC_U_ADDR :: RX_L1_CUR_DESC_U_ADDR [31:00] */
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_SHIFT 0
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_LIST1_CUR_BYTE_CNT - Rx List1 Current Descriptor Byte Count
+ ***************************************************************************/
+/* PCIE_DMA :: RX_LIST1_CUR_BYTE_CNT :: RX_L1_CUR_BYTE_CNT [31:00] */
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_MASK 0xffffffff
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_SHIFT 0
+#define BCHP_PCIE_DMA_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DMA_DEBUG_OPTIONS_REG - DMA Debug Options Register
+ ***************************************************************************/
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_SOFT_RST [31:31] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_MASK 0x80000000
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_SHIFT 31
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_SOFT_RST [30:30] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_MASK 0x40000000
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_SHIFT 30
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST [29:29] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_MASK 0x20000000
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_SHIFT 29
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST [28:28] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_MASK 0x10000000
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_SHIFT 28
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_0 [27:10] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_MASK  0x0ffffc00
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_SHIFT 10
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SPQ_SNAP_PW_DIS [09:09] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SPQ_SNAP_PW_DIS_MASK 0x00000200
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SPQ_SNAP_PW_DIS_SHIFT 9
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SPQ_SNAP_PW_DIS_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_OUTCP_Q_RO [08:08] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_OUTCP_Q_RO_MASK 0x00000100
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_OUTCP_Q_RO_SHIFT 8
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_OUTCP_Q_RO_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_NO_TX_DESC [07:07] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_TX_DESC_MASK 0x00000080
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_TX_DESC_SHIFT 7
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_TX_DESC_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_NO_RX_DESC [06:06] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_RX_DESC_MASK 0x00000040
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_RX_DESC_SHIFT 6
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_NO_RX_DESC_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SEL_RX_CNT [05:05] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_RX_CNT_MASK 0x00000020
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_RX_CNT_SHIFT 5
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_RX_CNT_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_EN_RX_DMA_XFER_CNT [04:04] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_MASK 0x00000010
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_SHIFT 4
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SEL_TX_CNT [03:03] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_TX_CNT_MASK 0x00000008
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_TX_CNT_SHIFT 3
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SEL_TX_CNT_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_RD_Q [02:02] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_MASK 0x00000004
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_SHIFT 2
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_WR_Q [01:01] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_MASK 0x00000002
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_SHIFT 1
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_DEFAULT 0x00000000
+
+/* PCIE_DMA :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RD_Q_RO [00:00] */
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RD_Q_RO_MASK 0x00000001
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RD_Q_RO_SHIFT 0
+#define BCHP_PCIE_DMA_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RD_Q_RO_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_CHANNEL_ERROR_STATUS - Read Channel Error Status
+ ***************************************************************************/
+/* PCIE_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_7 [31:28] */
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_MASK 0xf0000000
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_SHIFT 28
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_DEFAULT 0x00000000
+
+/* PCIE_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_6 [27:24] */
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_MASK 0x0f000000
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_SHIFT 24
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_DEFAULT 0x00000000
+
+/* PCIE_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_5 [23:20] */
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_MASK 0x00f00000
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_SHIFT 20
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_DEFAULT 0x00000000
+
+/* PCIE_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_4 [19:16] */
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_MASK 0x000f0000
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_SHIFT 16
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_DEFAULT 0x00000000
+
+/* PCIE_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_3 [15:12] */
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_MASK 0x0000f000
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_SHIFT 12
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_DEFAULT 0x00000000
+
+/* PCIE_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_2 [11:08] */
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_MASK 0x00000f00
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_SHIFT 8
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_DEFAULT 0x00000000
+
+/* PCIE_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_1 [07:04] */
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_MASK 0x000000f0
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_SHIFT 4
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_DEFAULT 0x00000000
+
+/* PCIE_DMA :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_0 [03:00] */
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_MASK 0x0000000f
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_SHIFT 0
+#define BCHP_PCIE_DMA_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_PCIE_DMA_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_pcie_ext_cfg.h b/include/linux/brcmstb/7435b0/bchp_pcie_ext_cfg.h
new file mode 100644
index 0000000..6739b69
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_pcie_ext_cfg.h
@@ -0,0 +1,116 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Mar  7 03:16:58 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_PCIE_EXT_CFG_H__
+#define BCHP_PCIE_EXT_CFG_H__
+
+/***************************************************************************
+ *PCIE_EXT_CFG - HIF PCIE EXTERNAL CFG Registers
+ ***************************************************************************/
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_DATA_0    0x00418000 /* PCIe External Configuration Space Data[0] */
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_DATA_1023 0x00418ffc /* PCIe External Configuration Space Data[1023] */
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX     0x00419000 /* PCIE External Configuration Access Index */
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_DATA      0x00419004 /* PCIE External Configuration Access Data */
+#define BCHP_PCIE_EXT_CFG_SCRATCH                0x00419008 /* Scratch Register */
+
+/***************************************************************************
+ *PCIE_EXT_CFG_DATA_0 - PCIe External Configuration Space Data[0]
+ ***************************************************************************/
+/* PCIE_EXT_CFG :: PCIE_EXT_CFG_DATA_0 :: DATA [31:00] */
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_DATA_0_DATA_MASK            0xffffffff
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_DATA_0_DATA_SHIFT           0
+
+/***************************************************************************
+ *PCIE_EXT_CFG_DATA_1023 - PCIe External Configuration Space Data[1023]
+ ***************************************************************************/
+/* PCIE_EXT_CFG :: PCIE_EXT_CFG_DATA_1023 :: DATA [31:00] */
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_DATA_1023_DATA_MASK         0xffffffff
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_DATA_1023_DATA_SHIFT        0
+
+/***************************************************************************
+ *PCIE_EXT_CFG_INDEX - PCIE External Configuration Access Index
+ ***************************************************************************/
+/* PCIE_EXT_CFG :: PCIE_EXT_CFG_INDEX :: UNUSED_1 [31:28] */
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_1_MASK         0xf0000000
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_1_SHIFT        28
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_1_DEFAULT      0x00000000
+
+/* PCIE_EXT_CFG :: PCIE_EXT_CFG_INDEX :: BUS_NUM [27:20] */
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_BUS_NUM_MASK          0x0ff00000
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_BUS_NUM_SHIFT         20
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_BUS_NUM_DEFAULT       0x00000000
+
+/* PCIE_EXT_CFG :: PCIE_EXT_CFG_INDEX :: DEV_NUM [19:15] */
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_DEV_NUM_MASK          0x000f8000
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_DEV_NUM_SHIFT         15
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_DEV_NUM_DEFAULT       0x00000000
+
+/* PCIE_EXT_CFG :: PCIE_EXT_CFG_INDEX :: FUNC_NUM [14:12] */
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_FUNC_NUM_MASK         0x00007000
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_FUNC_NUM_SHIFT        12
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_FUNC_NUM_DEFAULT      0x00000000
+
+/* PCIE_EXT_CFG :: PCIE_EXT_CFG_INDEX :: REG_NUM [11:02] */
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_REG_NUM_MASK          0x00000ffc
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_REG_NUM_SHIFT         2
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_REG_NUM_DEFAULT       0x00000000
+
+/* PCIE_EXT_CFG :: PCIE_EXT_CFG_INDEX :: UNUSED_0 [01:00] */
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_0_MASK         0x00000003
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_0_SHIFT        0
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX_UNUSED_0_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PCIE_EXT_CFG_DATA - PCIE External Configuration Access Data
+ ***************************************************************************/
+/* PCIE_EXT_CFG :: PCIE_EXT_CFG_DATA :: DATA [31:00] */
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_DATA_DATA_MASK              0xffffffff
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_DATA_DATA_SHIFT             0
+#define BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_DATA_DATA_DEFAULT           0x00000000
+
+/***************************************************************************
+ *SCRATCH - Scratch Register
+ ***************************************************************************/
+/* PCIE_EXT_CFG :: SCRATCH :: DATA [31:00] */
+#define BCHP_PCIE_EXT_CFG_SCRATCH_DATA_MASK                        0xffffffff
+#define BCHP_PCIE_EXT_CFG_SCRATCH_DATA_SHIFT                       0
+#define BCHP_PCIE_EXT_CFG_SCRATCH_DATA_DEFAULT                     0x00000000
+
+#endif /* #ifndef BCHP_PCIE_EXT_CFG_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_pcie_intr2.h b/include/linux/brcmstb/7435b0/bchp_pcie_intr2.h
new file mode 100644
index 0000000..d569779
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_pcie_intr2.h
@@ -0,0 +1,2019 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:26 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_pcie_intr2.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 3:31p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_PCIE_INTR2_H__
+#define BCHP_PCIE_INTR2_H__
+
+/***************************************************************************
+ *PCIE_INTR2 - PCI-E L2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_PCIE_INTR2_CPU_STATUS               0x00414300 /* CPU interrupt Status Register */
+#define BCHP_PCIE_INTR2_CPU_SET                  0x00414304 /* CPU interrupt Set Register */
+#define BCHP_PCIE_INTR2_CPU_CLEAR                0x00414308 /* CPU interrupt Clear Register */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS          0x0041430c /* CPU interrupt Mask Status Register */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET             0x00414310 /* CPU interrupt Mask Set Register */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR           0x00414314 /* CPU interrupt Mask Clear Register */
+#define BCHP_PCIE_INTR2_PCI_STATUS               0x00414318 /* PCI interrupt Status Register */
+#define BCHP_PCIE_INTR2_PCI_SET                  0x0041431c /* PCI interrupt Set Register */
+#define BCHP_PCIE_INTR2_PCI_CLEAR                0x00414320 /* PCI interrupt Clear Register */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS          0x00414324 /* PCI interrupt Mask Status Register */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET             0x00414328 /* PCI interrupt Mask Set Register */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR           0x0041432c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: CPU_STATUS :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR07_MASK                 0x80000000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR07_SHIFT                31
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR07_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR06_MASK                 0x40000000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR06_SHIFT                30
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR06_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR05_MASK                 0x20000000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR05_SHIFT                29
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR05_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR04_MASK                 0x10000000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR04_SHIFT                28
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR04_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR03_MASK                 0x08000000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR03_SHIFT                27
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR03_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR02_MASK                 0x04000000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR02_SHIFT                26
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR02_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR01_MASK                 0x02000000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR01_SHIFT                25
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR01_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR00_MASK                 0x01000000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR00_SHIFT                24
+#define BCHP_PCIE_INTR2_CPU_STATUS_MSI_INTR00_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_23_MASK              0x00800000
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_23_SHIFT             23
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_23_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_22_MASK              0x00400000
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_22_SHIFT             22
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_22_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_21_MASK              0x00200000
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_21_SHIFT             21
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_21_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_20_MASK              0x00100000
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_20_SHIFT             20
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_20_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_3_MASK                  0x00080000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_3_SHIFT                 19
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_3_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_2_MASK                  0x00040000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_2_SHIFT                 18
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_2_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_1_MASK                  0x00020000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_1_SHIFT                 17
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_1_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_0_MASK                  0x00010000
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_0_SHIFT                 16
+#define BCHP_PCIE_INTR2_CPU_STATUS_MAILBOX_0_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_FWD_ERR_MASK          0x00008000
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_FWD_ERR_SHIFT         15
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_FWD_ERR_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_RETRY_TIMEOUT_MASK    0x00004000
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_RETRY_TIMEOUT_SHIFT   14
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_CA_ATTN_MASK          0x00002000
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_CA_ATTN_SHIFT         13
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_CA_ATTN_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_UR_ATTN_MASK          0x00001000
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_UR_ATTN_SHIFT         12
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_MSTR_UR_ATTN_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_11_MASK              0x00000800
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_11_SHIFT             11
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_11_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_10_MASK              0x00000400
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_10_SHIFT             10
+#define BCHP_PCIE_INTR2_CPU_STATUS_UNASSIGNED_10_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_TGT_BAD_ACCESS_MASK        0x00000200
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_TGT_BAD_ACCESS_SHIFT       9
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_TGT_BAD_ACCESS_DEFAULT     0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_TGT_BAD_ADDRESS_MASK       0x00000100
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_TGT_BAD_ADDRESS_SHIFT      8
+#define BCHP_PCIE_INTR2_CPU_STATUS_PCIE_TGT_BAD_ADDRESS_DEFAULT    0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_RX_DMA_ERR_INTR_MASK         0x00000080
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_RX_DMA_ERR_INTR_SHIFT        7
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_RX_DMA_ERR_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_RX_DMA_DONE_INTR_MASK        0x00000040
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_RX_DMA_DONE_INTR_SHIFT       6
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_RX_DMA_DONE_INTR_DEFAULT     0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_TX_DMA_ERR_INTR_MASK         0x00000020
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_TX_DMA_ERR_INTR_SHIFT        5
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_TX_DMA_ERR_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_TX_DMA_DONE_INTR_MASK        0x00000010
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_TX_DMA_DONE_INTR_SHIFT       4
+#define BCHP_PCIE_INTR2_CPU_STATUS_L1_TX_DMA_DONE_INTR_DEFAULT     0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_RX_DMA_ERR_INTR_MASK         0x00000008
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_RX_DMA_ERR_INTR_SHIFT        3
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_RX_DMA_ERR_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_RX_DMA_DONE_INTR_MASK        0x00000004
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_RX_DMA_DONE_INTR_SHIFT       2
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_RX_DMA_DONE_INTR_DEFAULT     0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_TX_DMA_ERR_INTR_MASK         0x00000002
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_TX_DMA_ERR_INTR_SHIFT        1
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_TX_DMA_ERR_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: CPU_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_TX_DMA_DONE_INTR_MASK        0x00000001
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_TX_DMA_DONE_INTR_SHIFT       0
+#define BCHP_PCIE_INTR2_CPU_STATUS_L0_TX_DMA_DONE_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: CPU_SET :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR07_MASK                    0x80000000
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR07_SHIFT                   31
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR07_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR06_MASK                    0x40000000
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR06_SHIFT                   30
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR06_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR05_MASK                    0x20000000
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR05_SHIFT                   29
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR05_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR04_MASK                    0x10000000
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR04_SHIFT                   28
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR04_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR03_MASK                    0x08000000
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR03_SHIFT                   27
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR03_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR02_MASK                    0x04000000
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR02_SHIFT                   26
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR02_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR01_MASK                    0x02000000
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR01_SHIFT                   25
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR01_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR00_MASK                    0x01000000
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR00_SHIFT                   24
+#define BCHP_PCIE_INTR2_CPU_SET_MSI_INTR00_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_23_MASK                 0x00800000
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_23_SHIFT                23
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_23_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_22_MASK                 0x00400000
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_22_SHIFT                22
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_22_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_21_MASK                 0x00200000
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_21_SHIFT                21
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_21_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_20_MASK                 0x00100000
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_20_SHIFT                20
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_20_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_3_MASK                     0x00080000
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_3_SHIFT                    19
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_3_DEFAULT                  0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_2_MASK                     0x00040000
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_2_SHIFT                    18
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_2_DEFAULT                  0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_1_MASK                     0x00020000
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_1_SHIFT                    17
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_1_DEFAULT                  0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_0_MASK                     0x00010000
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_0_SHIFT                    16
+#define BCHP_PCIE_INTR2_CPU_SET_MAILBOX_0_DEFAULT                  0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_FWD_ERR_MASK             0x00008000
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_FWD_ERR_SHIFT            15
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_FWD_ERR_DEFAULT          0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_RETRY_TIMEOUT_MASK       0x00004000
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_RETRY_TIMEOUT_SHIFT      14
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT    0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_CA_ATTN_MASK             0x00002000
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_CA_ATTN_SHIFT            13
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_CA_ATTN_DEFAULT          0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_UR_ATTN_MASK             0x00001000
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_UR_ATTN_SHIFT            12
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_MSTR_UR_ATTN_DEFAULT          0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_11_MASK                 0x00000800
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_11_SHIFT                11
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_11_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_10_MASK                 0x00000400
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_10_SHIFT                10
+#define BCHP_PCIE_INTR2_CPU_SET_UNASSIGNED_10_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_TGT_BAD_ACCESS_MASK           0x00000200
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_TGT_BAD_ACCESS_SHIFT          9
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_TGT_BAD_ACCESS_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_TGT_BAD_ADDRESS_MASK          0x00000100
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_TGT_BAD_ADDRESS_SHIFT         8
+#define BCHP_PCIE_INTR2_CPU_SET_PCIE_TGT_BAD_ADDRESS_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_CPU_SET_L1_RX_DMA_ERR_INTR_MASK            0x00000080
+#define BCHP_PCIE_INTR2_CPU_SET_L1_RX_DMA_ERR_INTR_SHIFT           7
+#define BCHP_PCIE_INTR2_CPU_SET_L1_RX_DMA_ERR_INTR_DEFAULT         0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_CPU_SET_L1_RX_DMA_DONE_INTR_MASK           0x00000040
+#define BCHP_PCIE_INTR2_CPU_SET_L1_RX_DMA_DONE_INTR_SHIFT          6
+#define BCHP_PCIE_INTR2_CPU_SET_L1_RX_DMA_DONE_INTR_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_CPU_SET_L1_TX_DMA_ERR_INTR_MASK            0x00000020
+#define BCHP_PCIE_INTR2_CPU_SET_L1_TX_DMA_ERR_INTR_SHIFT           5
+#define BCHP_PCIE_INTR2_CPU_SET_L1_TX_DMA_ERR_INTR_DEFAULT         0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_CPU_SET_L1_TX_DMA_DONE_INTR_MASK           0x00000010
+#define BCHP_PCIE_INTR2_CPU_SET_L1_TX_DMA_DONE_INTR_SHIFT          4
+#define BCHP_PCIE_INTR2_CPU_SET_L1_TX_DMA_DONE_INTR_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_CPU_SET_L0_RX_DMA_ERR_INTR_MASK            0x00000008
+#define BCHP_PCIE_INTR2_CPU_SET_L0_RX_DMA_ERR_INTR_SHIFT           3
+#define BCHP_PCIE_INTR2_CPU_SET_L0_RX_DMA_ERR_INTR_DEFAULT         0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_CPU_SET_L0_RX_DMA_DONE_INTR_MASK           0x00000004
+#define BCHP_PCIE_INTR2_CPU_SET_L0_RX_DMA_DONE_INTR_SHIFT          2
+#define BCHP_PCIE_INTR2_CPU_SET_L0_RX_DMA_DONE_INTR_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_CPU_SET_L0_TX_DMA_ERR_INTR_MASK            0x00000002
+#define BCHP_PCIE_INTR2_CPU_SET_L0_TX_DMA_ERR_INTR_SHIFT           1
+#define BCHP_PCIE_INTR2_CPU_SET_L0_TX_DMA_ERR_INTR_DEFAULT         0x00000000
+
+/* PCIE_INTR2 :: CPU_SET :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_CPU_SET_L0_TX_DMA_DONE_INTR_MASK           0x00000001
+#define BCHP_PCIE_INTR2_CPU_SET_L0_TX_DMA_DONE_INTR_SHIFT          0
+#define BCHP_PCIE_INTR2_CPU_SET_L0_TX_DMA_DONE_INTR_DEFAULT        0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: CPU_CLEAR :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR07_MASK                  0x80000000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR07_SHIFT                 31
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR07_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR06_MASK                  0x40000000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR06_SHIFT                 30
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR06_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR05_MASK                  0x20000000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR05_SHIFT                 29
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR05_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR04_MASK                  0x10000000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR04_SHIFT                 28
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR04_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR03_MASK                  0x08000000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR03_SHIFT                 27
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR03_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR02_MASK                  0x04000000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR02_SHIFT                 26
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR02_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR01_MASK                  0x02000000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR01_SHIFT                 25
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR01_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR00_MASK                  0x01000000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR00_SHIFT                 24
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MSI_INTR00_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_23_MASK               0x00800000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_23_SHIFT              23
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_23_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_22_MASK               0x00400000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_22_SHIFT              22
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_22_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_21_MASK               0x00200000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_21_SHIFT              21
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_21_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_20_MASK               0x00100000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_20_SHIFT              20
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_20_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_3_MASK                   0x00080000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_3_SHIFT                  19
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_3_DEFAULT                0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_2_MASK                   0x00040000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_2_SHIFT                  18
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_2_DEFAULT                0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_1_MASK                   0x00020000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_1_SHIFT                  17
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_1_DEFAULT                0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_0_MASK                   0x00010000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_0_SHIFT                  16
+#define BCHP_PCIE_INTR2_CPU_CLEAR_MAILBOX_0_DEFAULT                0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_FWD_ERR_MASK           0x00008000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_FWD_ERR_SHIFT          15
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_FWD_ERR_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_MASK     0x00004000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_SHIFT    14
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT  0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_CA_ATTN_MASK           0x00002000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_CA_ATTN_SHIFT          13
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_CA_ATTN_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_UR_ATTN_MASK           0x00001000
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_UR_ATTN_SHIFT          12
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_MSTR_UR_ATTN_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_11_MASK               0x00000800
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_11_SHIFT              11
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_11_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_10_MASK               0x00000400
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_10_SHIFT              10
+#define BCHP_PCIE_INTR2_CPU_CLEAR_UNASSIGNED_10_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ACCESS_MASK         0x00000200
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ACCESS_SHIFT        9
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ACCESS_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ADDRESS_MASK        0x00000100
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ADDRESS_SHIFT       8
+#define BCHP_PCIE_INTR2_CPU_CLEAR_PCIE_TGT_BAD_ADDRESS_DEFAULT     0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_RX_DMA_ERR_INTR_MASK          0x00000080
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_RX_DMA_ERR_INTR_SHIFT         7
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_RX_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_RX_DMA_DONE_INTR_MASK         0x00000040
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_RX_DMA_DONE_INTR_SHIFT        6
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_RX_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_TX_DMA_ERR_INTR_MASK          0x00000020
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_TX_DMA_ERR_INTR_SHIFT         5
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_TX_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_TX_DMA_DONE_INTR_MASK         0x00000010
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_TX_DMA_DONE_INTR_SHIFT        4
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L1_TX_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_RX_DMA_ERR_INTR_MASK          0x00000008
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_RX_DMA_ERR_INTR_SHIFT         3
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_RX_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_RX_DMA_DONE_INTR_MASK         0x00000004
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_RX_DMA_DONE_INTR_SHIFT        2
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_RX_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_TX_DMA_ERR_INTR_MASK          0x00000002
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_TX_DMA_ERR_INTR_SHIFT         1
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_TX_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: CPU_CLEAR :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_TX_DMA_DONE_INTR_MASK         0x00000001
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_TX_DMA_DONE_INTR_SHIFT        0
+#define BCHP_PCIE_INTR2_CPU_CLEAR_L0_TX_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR07_MASK            0x80000000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR07_SHIFT           31
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR07_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR06_MASK            0x40000000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR06_SHIFT           30
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR06_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR05_MASK            0x20000000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR05_SHIFT           29
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR05_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR04_MASK            0x10000000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR04_SHIFT           28
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR04_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR03_MASK            0x08000000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR03_SHIFT           27
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR03_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR02_MASK            0x04000000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR02_SHIFT           26
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR02_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR01_MASK            0x02000000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR01_SHIFT           25
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR01_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR00_MASK            0x01000000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR00_SHIFT           24
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MSI_INTR00_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_23_MASK         0x00800000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_23_SHIFT        23
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_23_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_22_MASK         0x00400000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_22_SHIFT        22
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_22_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_21_MASK         0x00200000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_21_SHIFT        21
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_21_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_20_MASK         0x00100000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_20_SHIFT        20
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_20_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_3_MASK             0x00080000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_3_SHIFT            19
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_3_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_2_MASK             0x00040000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_2_SHIFT            18
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_2_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_1_MASK             0x00020000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_1_SHIFT            17
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_1_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_0_MASK             0x00010000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_0_SHIFT            16
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_MAILBOX_0_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_FWD_ERR_MASK     0x00008000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_FWD_ERR_SHIFT    15
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_FWD_ERR_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_CA_ATTN_MASK     0x00002000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_CA_ATTN_SHIFT    13
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_CA_ATTN_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_UR_ATTN_MASK     0x00001000
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_UR_ATTN_SHIFT    12
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_MSTR_UR_ATTN_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_11_MASK         0x00000800
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_11_SHIFT        11
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_11_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_10_MASK         0x00000400
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_10_SHIFT        10
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_UNASSIGNED_10_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ACCESS_MASK   0x00000200
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ACCESS_SHIFT  9
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_MASK  0x00000100
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_SHIFT 8
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_RX_DMA_ERR_INTR_MASK    0x00000080
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_RX_DMA_ERR_INTR_SHIFT   7
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_RX_DMA_DONE_INTR_MASK   0x00000040
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_RX_DMA_DONE_INTR_SHIFT  6
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_TX_DMA_ERR_INTR_MASK    0x00000020
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_TX_DMA_ERR_INTR_SHIFT   5
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_TX_DMA_DONE_INTR_MASK   0x00000010
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_TX_DMA_DONE_INTR_SHIFT  4
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_RX_DMA_ERR_INTR_MASK    0x00000008
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_RX_DMA_ERR_INTR_SHIFT   3
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_RX_DMA_DONE_INTR_MASK   0x00000004
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_RX_DMA_DONE_INTR_SHIFT  2
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_TX_DMA_ERR_INTR_MASK    0x00000002
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_TX_DMA_ERR_INTR_SHIFT   1
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_TX_DMA_DONE_INTR_MASK   0x00000001
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_TX_DMA_DONE_INTR_SHIFT  0
+#define BCHP_PCIE_INTR2_CPU_MASK_STATUS_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: CPU_MASK_SET :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR07_MASK               0x80000000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR07_SHIFT              31
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR07_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR06_MASK               0x40000000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR06_SHIFT              30
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR06_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR05_MASK               0x20000000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR05_SHIFT              29
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR05_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR04_MASK               0x10000000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR04_SHIFT              28
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR04_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR03_MASK               0x08000000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR03_SHIFT              27
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR03_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR02_MASK               0x04000000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR02_SHIFT              26
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR02_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR01_MASK               0x02000000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR01_SHIFT              25
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR01_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR00_MASK               0x01000000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR00_SHIFT              24
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MSI_INTR00_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_23_MASK            0x00800000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_23_SHIFT           23
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_23_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_22_MASK            0x00400000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_22_SHIFT           22
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_22_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_21_MASK            0x00200000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_21_SHIFT           21
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_21_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_20_MASK            0x00100000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_20_SHIFT           20
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_20_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_3_MASK                0x00080000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_3_SHIFT               19
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_3_DEFAULT             0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_2_MASK                0x00040000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_2_SHIFT               18
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_2_DEFAULT             0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_1_MASK                0x00020000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_1_SHIFT               17
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_1_DEFAULT             0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_0_MASK                0x00010000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_0_SHIFT               16
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_MAILBOX_0_DEFAULT             0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_FWD_ERR_MASK        0x00008000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_FWD_ERR_SHIFT       15
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_FWD_ERR_DEFAULT     0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_MASK  0x00004000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_CA_ATTN_MASK        0x00002000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_CA_ATTN_SHIFT       13
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_CA_ATTN_DEFAULT     0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_UR_ATTN_MASK        0x00001000
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_UR_ATTN_SHIFT       12
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_MSTR_UR_ATTN_DEFAULT     0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_11_MASK            0x00000800
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_11_SHIFT           11
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_11_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_10_MASK            0x00000400
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_10_SHIFT           10
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_UNASSIGNED_10_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ACCESS_MASK      0x00000200
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ACCESS_SHIFT     9
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ACCESS_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ADDRESS_MASK     0x00000100
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ADDRESS_SHIFT    8
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_PCIE_TGT_BAD_ADDRESS_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_RX_DMA_ERR_INTR_MASK       0x00000080
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_RX_DMA_ERR_INTR_SHIFT      7
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_RX_DMA_ERR_INTR_DEFAULT    0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_RX_DMA_DONE_INTR_MASK      0x00000040
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_RX_DMA_DONE_INTR_SHIFT     6
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_RX_DMA_DONE_INTR_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_TX_DMA_ERR_INTR_MASK       0x00000020
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_TX_DMA_ERR_INTR_SHIFT      5
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_TX_DMA_ERR_INTR_DEFAULT    0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_TX_DMA_DONE_INTR_MASK      0x00000010
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_TX_DMA_DONE_INTR_SHIFT     4
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L1_TX_DMA_DONE_INTR_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_RX_DMA_ERR_INTR_MASK       0x00000008
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_RX_DMA_ERR_INTR_SHIFT      3
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_RX_DMA_ERR_INTR_DEFAULT    0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_RX_DMA_DONE_INTR_MASK      0x00000004
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_RX_DMA_DONE_INTR_SHIFT     2
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_RX_DMA_DONE_INTR_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_TX_DMA_ERR_INTR_MASK       0x00000002
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_TX_DMA_ERR_INTR_SHIFT      1
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_TX_DMA_ERR_INTR_DEFAULT    0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_SET :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_TX_DMA_DONE_INTR_MASK      0x00000001
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_TX_DMA_DONE_INTR_SHIFT     0
+#define BCHP_PCIE_INTR2_CPU_MASK_SET_L0_TX_DMA_DONE_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR07_MASK             0x80000000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR07_SHIFT            31
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR07_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR06_MASK             0x40000000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR06_SHIFT            30
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR06_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR05_MASK             0x20000000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR05_SHIFT            29
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR05_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR04_MASK             0x10000000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR04_SHIFT            28
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR04_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR03_MASK             0x08000000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR03_SHIFT            27
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR03_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR02_MASK             0x04000000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR02_SHIFT            26
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR02_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR01_MASK             0x02000000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR01_SHIFT            25
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR01_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR00_MASK             0x01000000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR00_SHIFT            24
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MSI_INTR00_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_23_MASK          0x00800000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_23_SHIFT         23
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_23_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_22_MASK          0x00400000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_22_SHIFT         22
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_22_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_21_MASK          0x00200000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_21_SHIFT         21
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_21_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_20_MASK          0x00100000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_20_SHIFT         20
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_20_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_3_MASK              0x00080000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_3_SHIFT             19
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_3_DEFAULT           0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_2_MASK              0x00040000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_2_SHIFT             18
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_2_DEFAULT           0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_1_MASK              0x00020000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_1_SHIFT             17
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_1_DEFAULT           0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_0_MASK              0x00010000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_0_SHIFT             16
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_MAILBOX_0_DEFAULT           0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_FWD_ERR_MASK      0x00008000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_FWD_ERR_SHIFT     15
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_FWD_ERR_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_CA_ATTN_MASK      0x00002000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_CA_ATTN_SHIFT     13
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_CA_ATTN_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_UR_ATTN_MASK      0x00001000
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_UR_ATTN_SHIFT     12
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_MSTR_UR_ATTN_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_11_MASK          0x00000800
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_11_SHIFT         11
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_11_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_10_MASK          0x00000400
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_10_SHIFT         10
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_UNASSIGNED_10_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_MASK    0x00000200
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_SHIFT   9
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_MASK   0x00000100
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_SHIFT  8
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_ERR_INTR_MASK     0x00000080
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_ERR_INTR_SHIFT    7
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_ERR_INTR_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_DONE_INTR_MASK    0x00000040
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_DONE_INTR_SHIFT   6
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_ERR_INTR_MASK     0x00000020
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_ERR_INTR_SHIFT    5
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_ERR_INTR_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_DONE_INTR_MASK    0x00000010
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_DONE_INTR_SHIFT   4
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_ERR_INTR_MASK     0x00000008
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_ERR_INTR_SHIFT    3
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_ERR_INTR_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_DONE_INTR_MASK    0x00000004
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_DONE_INTR_SHIFT   2
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_ERR_INTR_MASK     0x00000002
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_ERR_INTR_SHIFT    1
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_ERR_INTR_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: CPU_MASK_CLEAR :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_DONE_INTR_MASK    0x00000001
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_DONE_INTR_SHIFT   0
+#define BCHP_PCIE_INTR2_CPU_MASK_CLEAR_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: PCI_STATUS :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR07_MASK                 0x80000000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR07_SHIFT                31
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR07_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR06_MASK                 0x40000000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR06_SHIFT                30
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR06_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR05_MASK                 0x20000000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR05_SHIFT                29
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR05_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR04_MASK                 0x10000000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR04_SHIFT                28
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR04_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR03_MASK                 0x08000000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR03_SHIFT                27
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR03_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR02_MASK                 0x04000000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR02_SHIFT                26
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR02_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR01_MASK                 0x02000000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR01_SHIFT                25
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR01_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR00_MASK                 0x01000000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR00_SHIFT                24
+#define BCHP_PCIE_INTR2_PCI_STATUS_MSI_INTR00_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_23_MASK              0x00800000
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_23_SHIFT             23
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_23_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_22_MASK              0x00400000
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_22_SHIFT             22
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_22_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_21_MASK              0x00200000
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_21_SHIFT             21
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_21_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_20_MASK              0x00100000
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_20_SHIFT             20
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_20_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_3_MASK                  0x00080000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_3_SHIFT                 19
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_3_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_2_MASK                  0x00040000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_2_SHIFT                 18
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_2_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_1_MASK                  0x00020000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_1_SHIFT                 17
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_1_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_0_MASK                  0x00010000
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_0_SHIFT                 16
+#define BCHP_PCIE_INTR2_PCI_STATUS_MAILBOX_0_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_FWD_ERR_MASK          0x00008000
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_FWD_ERR_SHIFT         15
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_FWD_ERR_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_RETRY_TIMEOUT_MASK    0x00004000
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_RETRY_TIMEOUT_SHIFT   14
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_CA_ATTN_MASK          0x00002000
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_CA_ATTN_SHIFT         13
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_CA_ATTN_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_UR_ATTN_MASK          0x00001000
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_UR_ATTN_SHIFT         12
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_MSTR_UR_ATTN_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_11_MASK              0x00000800
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_11_SHIFT             11
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_11_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_10_MASK              0x00000400
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_10_SHIFT             10
+#define BCHP_PCIE_INTR2_PCI_STATUS_UNASSIGNED_10_DEFAULT           0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_TGT_BAD_ACCESS_MASK        0x00000200
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_TGT_BAD_ACCESS_SHIFT       9
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_TGT_BAD_ACCESS_DEFAULT     0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_TGT_BAD_ADDRESS_MASK       0x00000100
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_TGT_BAD_ADDRESS_SHIFT      8
+#define BCHP_PCIE_INTR2_PCI_STATUS_PCIE_TGT_BAD_ADDRESS_DEFAULT    0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_RX_DMA_ERR_INTR_MASK         0x00000080
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_RX_DMA_ERR_INTR_SHIFT        7
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_RX_DMA_ERR_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_RX_DMA_DONE_INTR_MASK        0x00000040
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_RX_DMA_DONE_INTR_SHIFT       6
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_RX_DMA_DONE_INTR_DEFAULT     0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_TX_DMA_ERR_INTR_MASK         0x00000020
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_TX_DMA_ERR_INTR_SHIFT        5
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_TX_DMA_ERR_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_TX_DMA_DONE_INTR_MASK        0x00000010
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_TX_DMA_DONE_INTR_SHIFT       4
+#define BCHP_PCIE_INTR2_PCI_STATUS_L1_TX_DMA_DONE_INTR_DEFAULT     0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_RX_DMA_ERR_INTR_MASK         0x00000008
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_RX_DMA_ERR_INTR_SHIFT        3
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_RX_DMA_ERR_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_RX_DMA_DONE_INTR_MASK        0x00000004
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_RX_DMA_DONE_INTR_SHIFT       2
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_RX_DMA_DONE_INTR_DEFAULT     0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_TX_DMA_ERR_INTR_MASK         0x00000002
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_TX_DMA_ERR_INTR_SHIFT        1
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_TX_DMA_ERR_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: PCI_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_TX_DMA_DONE_INTR_MASK        0x00000001
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_TX_DMA_DONE_INTR_SHIFT       0
+#define BCHP_PCIE_INTR2_PCI_STATUS_L0_TX_DMA_DONE_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: PCI_SET :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR07_MASK                    0x80000000
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR07_SHIFT                   31
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR07_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR06_MASK                    0x40000000
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR06_SHIFT                   30
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR06_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR05_MASK                    0x20000000
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR05_SHIFT                   29
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR05_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR04_MASK                    0x10000000
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR04_SHIFT                   28
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR04_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR03_MASK                    0x08000000
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR03_SHIFT                   27
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR03_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR02_MASK                    0x04000000
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR02_SHIFT                   26
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR02_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR01_MASK                    0x02000000
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR01_SHIFT                   25
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR01_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR00_MASK                    0x01000000
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR00_SHIFT                   24
+#define BCHP_PCIE_INTR2_PCI_SET_MSI_INTR00_DEFAULT                 0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_23_MASK                 0x00800000
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_23_SHIFT                23
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_23_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_22_MASK                 0x00400000
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_22_SHIFT                22
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_22_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_21_MASK                 0x00200000
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_21_SHIFT                21
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_21_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_20_MASK                 0x00100000
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_20_SHIFT                20
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_20_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_3_MASK                     0x00080000
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_3_SHIFT                    19
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_3_DEFAULT                  0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_2_MASK                     0x00040000
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_2_SHIFT                    18
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_2_DEFAULT                  0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_1_MASK                     0x00020000
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_1_SHIFT                    17
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_1_DEFAULT                  0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_0_MASK                     0x00010000
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_0_SHIFT                    16
+#define BCHP_PCIE_INTR2_PCI_SET_MAILBOX_0_DEFAULT                  0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_FWD_ERR_MASK             0x00008000
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_FWD_ERR_SHIFT            15
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_FWD_ERR_DEFAULT          0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_RETRY_TIMEOUT_MASK       0x00004000
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_RETRY_TIMEOUT_SHIFT      14
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT    0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_CA_ATTN_MASK             0x00002000
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_CA_ATTN_SHIFT            13
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_CA_ATTN_DEFAULT          0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_UR_ATTN_MASK             0x00001000
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_UR_ATTN_SHIFT            12
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_MSTR_UR_ATTN_DEFAULT          0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_11_MASK                 0x00000800
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_11_SHIFT                11
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_11_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_10_MASK                 0x00000400
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_10_SHIFT                10
+#define BCHP_PCIE_INTR2_PCI_SET_UNASSIGNED_10_DEFAULT              0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_TGT_BAD_ACCESS_MASK           0x00000200
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_TGT_BAD_ACCESS_SHIFT          9
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_TGT_BAD_ACCESS_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_TGT_BAD_ADDRESS_MASK          0x00000100
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_TGT_BAD_ADDRESS_SHIFT         8
+#define BCHP_PCIE_INTR2_PCI_SET_PCIE_TGT_BAD_ADDRESS_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_PCI_SET_L1_RX_DMA_ERR_INTR_MASK            0x00000080
+#define BCHP_PCIE_INTR2_PCI_SET_L1_RX_DMA_ERR_INTR_SHIFT           7
+#define BCHP_PCIE_INTR2_PCI_SET_L1_RX_DMA_ERR_INTR_DEFAULT         0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_PCI_SET_L1_RX_DMA_DONE_INTR_MASK           0x00000040
+#define BCHP_PCIE_INTR2_PCI_SET_L1_RX_DMA_DONE_INTR_SHIFT          6
+#define BCHP_PCIE_INTR2_PCI_SET_L1_RX_DMA_DONE_INTR_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_PCI_SET_L1_TX_DMA_ERR_INTR_MASK            0x00000020
+#define BCHP_PCIE_INTR2_PCI_SET_L1_TX_DMA_ERR_INTR_SHIFT           5
+#define BCHP_PCIE_INTR2_PCI_SET_L1_TX_DMA_ERR_INTR_DEFAULT         0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_PCI_SET_L1_TX_DMA_DONE_INTR_MASK           0x00000010
+#define BCHP_PCIE_INTR2_PCI_SET_L1_TX_DMA_DONE_INTR_SHIFT          4
+#define BCHP_PCIE_INTR2_PCI_SET_L1_TX_DMA_DONE_INTR_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_PCI_SET_L0_RX_DMA_ERR_INTR_MASK            0x00000008
+#define BCHP_PCIE_INTR2_PCI_SET_L0_RX_DMA_ERR_INTR_SHIFT           3
+#define BCHP_PCIE_INTR2_PCI_SET_L0_RX_DMA_ERR_INTR_DEFAULT         0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_PCI_SET_L0_RX_DMA_DONE_INTR_MASK           0x00000004
+#define BCHP_PCIE_INTR2_PCI_SET_L0_RX_DMA_DONE_INTR_SHIFT          2
+#define BCHP_PCIE_INTR2_PCI_SET_L0_RX_DMA_DONE_INTR_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_PCI_SET_L0_TX_DMA_ERR_INTR_MASK            0x00000002
+#define BCHP_PCIE_INTR2_PCI_SET_L0_TX_DMA_ERR_INTR_SHIFT           1
+#define BCHP_PCIE_INTR2_PCI_SET_L0_TX_DMA_ERR_INTR_DEFAULT         0x00000000
+
+/* PCIE_INTR2 :: PCI_SET :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_PCI_SET_L0_TX_DMA_DONE_INTR_MASK           0x00000001
+#define BCHP_PCIE_INTR2_PCI_SET_L0_TX_DMA_DONE_INTR_SHIFT          0
+#define BCHP_PCIE_INTR2_PCI_SET_L0_TX_DMA_DONE_INTR_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: PCI_CLEAR :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR07_MASK                  0x80000000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR07_SHIFT                 31
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR07_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR06_MASK                  0x40000000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR06_SHIFT                 30
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR06_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR05_MASK                  0x20000000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR05_SHIFT                 29
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR05_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR04_MASK                  0x10000000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR04_SHIFT                 28
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR04_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR03_MASK                  0x08000000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR03_SHIFT                 27
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR03_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR02_MASK                  0x04000000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR02_SHIFT                 26
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR02_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR01_MASK                  0x02000000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR01_SHIFT                 25
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR01_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR00_MASK                  0x01000000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR00_SHIFT                 24
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MSI_INTR00_DEFAULT               0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_23_MASK               0x00800000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_23_SHIFT              23
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_23_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_22_MASK               0x00400000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_22_SHIFT              22
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_22_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_21_MASK               0x00200000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_21_SHIFT              21
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_21_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_20_MASK               0x00100000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_20_SHIFT              20
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_20_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_3_MASK                   0x00080000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_3_SHIFT                  19
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_3_DEFAULT                0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_2_MASK                   0x00040000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_2_SHIFT                  18
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_2_DEFAULT                0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_1_MASK                   0x00020000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_1_SHIFT                  17
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_1_DEFAULT                0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_0_MASK                   0x00010000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_0_SHIFT                  16
+#define BCHP_PCIE_INTR2_PCI_CLEAR_MAILBOX_0_DEFAULT                0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_FWD_ERR_MASK           0x00008000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_FWD_ERR_SHIFT          15
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_FWD_ERR_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_MASK     0x00004000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_SHIFT    14
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT  0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_CA_ATTN_MASK           0x00002000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_CA_ATTN_SHIFT          13
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_CA_ATTN_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_UR_ATTN_MASK           0x00001000
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_UR_ATTN_SHIFT          12
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_MSTR_UR_ATTN_DEFAULT        0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_11_MASK               0x00000800
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_11_SHIFT              11
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_11_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_10_MASK               0x00000400
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_10_SHIFT              10
+#define BCHP_PCIE_INTR2_PCI_CLEAR_UNASSIGNED_10_DEFAULT            0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ACCESS_MASK         0x00000200
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ACCESS_SHIFT        9
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ACCESS_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ADDRESS_MASK        0x00000100
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ADDRESS_SHIFT       8
+#define BCHP_PCIE_INTR2_PCI_CLEAR_PCIE_TGT_BAD_ADDRESS_DEFAULT     0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_RX_DMA_ERR_INTR_MASK          0x00000080
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_RX_DMA_ERR_INTR_SHIFT         7
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_RX_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_RX_DMA_DONE_INTR_MASK         0x00000040
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_RX_DMA_DONE_INTR_SHIFT        6
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_RX_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_TX_DMA_ERR_INTR_MASK          0x00000020
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_TX_DMA_ERR_INTR_SHIFT         5
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_TX_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_TX_DMA_DONE_INTR_MASK         0x00000010
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_TX_DMA_DONE_INTR_SHIFT        4
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L1_TX_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_RX_DMA_ERR_INTR_MASK          0x00000008
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_RX_DMA_ERR_INTR_SHIFT         3
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_RX_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_RX_DMA_DONE_INTR_MASK         0x00000004
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_RX_DMA_DONE_INTR_SHIFT        2
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_RX_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_TX_DMA_ERR_INTR_MASK          0x00000002
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_TX_DMA_ERR_INTR_SHIFT         1
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_TX_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* PCIE_INTR2 :: PCI_CLEAR :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_TX_DMA_DONE_INTR_MASK         0x00000001
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_TX_DMA_DONE_INTR_SHIFT        0
+#define BCHP_PCIE_INTR2_PCI_CLEAR_L0_TX_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR07_MASK            0x80000000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR07_SHIFT           31
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR07_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR06_MASK            0x40000000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR06_SHIFT           30
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR06_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR05_MASK            0x20000000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR05_SHIFT           29
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR05_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR04_MASK            0x10000000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR04_SHIFT           28
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR04_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR03_MASK            0x08000000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR03_SHIFT           27
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR03_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR02_MASK            0x04000000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR02_SHIFT           26
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR02_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR01_MASK            0x02000000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR01_SHIFT           25
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR01_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR00_MASK            0x01000000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR00_SHIFT           24
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MSI_INTR00_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_23_MASK         0x00800000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_23_SHIFT        23
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_23_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_22_MASK         0x00400000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_22_SHIFT        22
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_22_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_21_MASK         0x00200000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_21_SHIFT        21
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_21_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_20_MASK         0x00100000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_20_SHIFT        20
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_20_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_3_MASK             0x00080000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_3_SHIFT            19
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_3_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_2_MASK             0x00040000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_2_SHIFT            18
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_2_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_1_MASK             0x00020000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_1_SHIFT            17
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_1_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_0_MASK             0x00010000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_0_SHIFT            16
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_MAILBOX_0_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_FWD_ERR_MASK     0x00008000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_FWD_ERR_SHIFT    15
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_FWD_ERR_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_CA_ATTN_MASK     0x00002000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_CA_ATTN_SHIFT    13
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_CA_ATTN_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_UR_ATTN_MASK     0x00001000
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_UR_ATTN_SHIFT    12
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_MSTR_UR_ATTN_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_11_MASK         0x00000800
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_11_SHIFT        11
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_11_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_10_MASK         0x00000400
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_10_SHIFT        10
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_UNASSIGNED_10_DEFAULT      0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ACCESS_MASK   0x00000200
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ACCESS_SHIFT  9
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_MASK  0x00000100
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_SHIFT 8
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_RX_DMA_ERR_INTR_MASK    0x00000080
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_RX_DMA_ERR_INTR_SHIFT   7
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_RX_DMA_ERR_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_RX_DMA_DONE_INTR_MASK   0x00000040
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_RX_DMA_DONE_INTR_SHIFT  6
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_TX_DMA_ERR_INTR_MASK    0x00000020
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_TX_DMA_ERR_INTR_SHIFT   5
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_TX_DMA_ERR_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_TX_DMA_DONE_INTR_MASK   0x00000010
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_TX_DMA_DONE_INTR_SHIFT  4
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_RX_DMA_ERR_INTR_MASK    0x00000008
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_RX_DMA_ERR_INTR_SHIFT   3
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_RX_DMA_ERR_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_RX_DMA_DONE_INTR_MASK   0x00000004
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_RX_DMA_DONE_INTR_SHIFT  2
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_TX_DMA_ERR_INTR_MASK    0x00000002
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_TX_DMA_ERR_INTR_SHIFT   1
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_TX_DMA_ERR_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_TX_DMA_DONE_INTR_MASK   0x00000001
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_TX_DMA_DONE_INTR_SHIFT  0
+#define BCHP_PCIE_INTR2_PCI_MASK_STATUS_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: PCI_MASK_SET :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR07_MASK               0x80000000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR07_SHIFT              31
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR07_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR06_MASK               0x40000000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR06_SHIFT              30
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR06_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR05_MASK               0x20000000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR05_SHIFT              29
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR05_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR04_MASK               0x10000000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR04_SHIFT              28
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR04_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR03_MASK               0x08000000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR03_SHIFT              27
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR03_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR02_MASK               0x04000000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR02_SHIFT              26
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR02_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR01_MASK               0x02000000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR01_SHIFT              25
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR01_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR00_MASK               0x01000000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR00_SHIFT              24
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MSI_INTR00_DEFAULT            0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_23_MASK            0x00800000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_23_SHIFT           23
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_23_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_22_MASK            0x00400000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_22_SHIFT           22
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_22_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_21_MASK            0x00200000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_21_SHIFT           21
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_21_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_20_MASK            0x00100000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_20_SHIFT           20
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_20_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_3_MASK                0x00080000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_3_SHIFT               19
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_3_DEFAULT             0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_2_MASK                0x00040000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_2_SHIFT               18
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_2_DEFAULT             0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_1_MASK                0x00020000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_1_SHIFT               17
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_1_DEFAULT             0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_0_MASK                0x00010000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_0_SHIFT               16
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_MAILBOX_0_DEFAULT             0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_FWD_ERR_MASK        0x00008000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_FWD_ERR_SHIFT       15
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_FWD_ERR_DEFAULT     0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_MASK  0x00004000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_CA_ATTN_MASK        0x00002000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_CA_ATTN_SHIFT       13
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_CA_ATTN_DEFAULT     0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_UR_ATTN_MASK        0x00001000
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_UR_ATTN_SHIFT       12
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_MSTR_UR_ATTN_DEFAULT     0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_11_MASK            0x00000800
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_11_SHIFT           11
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_11_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_10_MASK            0x00000400
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_10_SHIFT           10
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_UNASSIGNED_10_DEFAULT         0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ACCESS_MASK      0x00000200
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ACCESS_SHIFT     9
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ACCESS_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ADDRESS_MASK     0x00000100
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ADDRESS_SHIFT    8
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_PCIE_TGT_BAD_ADDRESS_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_RX_DMA_ERR_INTR_MASK       0x00000080
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_RX_DMA_ERR_INTR_SHIFT      7
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_RX_DMA_ERR_INTR_DEFAULT    0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_RX_DMA_DONE_INTR_MASK      0x00000040
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_RX_DMA_DONE_INTR_SHIFT     6
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_RX_DMA_DONE_INTR_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_TX_DMA_ERR_INTR_MASK       0x00000020
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_TX_DMA_ERR_INTR_SHIFT      5
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_TX_DMA_ERR_INTR_DEFAULT    0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_TX_DMA_DONE_INTR_MASK      0x00000010
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_TX_DMA_DONE_INTR_SHIFT     4
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L1_TX_DMA_DONE_INTR_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_RX_DMA_ERR_INTR_MASK       0x00000008
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_RX_DMA_ERR_INTR_SHIFT      3
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_RX_DMA_ERR_INTR_DEFAULT    0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_RX_DMA_DONE_INTR_MASK      0x00000004
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_RX_DMA_DONE_INTR_SHIFT     2
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_RX_DMA_DONE_INTR_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_TX_DMA_ERR_INTR_MASK       0x00000002
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_TX_DMA_ERR_INTR_SHIFT      1
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_TX_DMA_ERR_INTR_DEFAULT    0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_SET :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_TX_DMA_DONE_INTR_MASK      0x00000001
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_TX_DMA_DONE_INTR_SHIFT     0
+#define BCHP_PCIE_INTR2_PCI_MASK_SET_L0_TX_DMA_DONE_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR07 [31:31] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR07_MASK             0x80000000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR07_SHIFT            31
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR07_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR06 [30:30] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR06_MASK             0x40000000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR06_SHIFT            30
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR06_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR05 [29:29] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR05_MASK             0x20000000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR05_SHIFT            29
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR05_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR04 [28:28] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR04_MASK             0x10000000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR04_SHIFT            28
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR04_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR03 [27:27] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR03_MASK             0x08000000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR03_SHIFT            27
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR03_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR02 [26:26] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR02_MASK             0x04000000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR02_SHIFT            26
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR02_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR01 [25:25] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR01_MASK             0x02000000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR01_SHIFT            25
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR01_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MSI_INTR00 [24:24] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR00_MASK             0x01000000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR00_SHIFT            24
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MSI_INTR00_DEFAULT          0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_23 [23:23] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_23_MASK          0x00800000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_23_SHIFT         23
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_23_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_22 [22:22] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_22_MASK          0x00400000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_22_SHIFT         22
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_22_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_21 [21:21] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_21_MASK          0x00200000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_21_SHIFT         21
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_21_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_20 [20:20] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_20_MASK          0x00100000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_20_SHIFT         20
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_20_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MAILBOX_3 [19:19] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_3_MASK              0x00080000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_3_SHIFT             19
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_3_DEFAULT           0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MAILBOX_2 [18:18] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_2_MASK              0x00040000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_2_SHIFT             18
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_2_DEFAULT           0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MAILBOX_1 [17:17] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_1_MASK              0x00020000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_1_SHIFT             17
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_1_DEFAULT           0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: MAILBOX_0 [16:16] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_0_MASK              0x00010000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_0_SHIFT             16
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_MAILBOX_0_DEFAULT           0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: PCIE_MSTR_FWD_ERR [15:15] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_FWD_ERR_MASK      0x00008000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_FWD_ERR_SHIFT     15
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_FWD_ERR_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: PCIE_MSTR_RETRY_TIMEOUT [14:14] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_MASK 0x00004000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_SHIFT 14
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_RETRY_TIMEOUT_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: PCIE_MSTR_CA_ATTN [13:13] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_CA_ATTN_MASK      0x00002000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_CA_ATTN_SHIFT     13
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_CA_ATTN_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: PCIE_MSTR_UR_ATTN [12:12] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_UR_ATTN_MASK      0x00001000
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_UR_ATTN_SHIFT     12
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_MSTR_UR_ATTN_DEFAULT   0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_11 [11:11] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_11_MASK          0x00000800
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_11_SHIFT         11
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_11_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: UNASSIGNED_10 [10:10] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_10_MASK          0x00000400
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_10_SHIFT         10
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_UNASSIGNED_10_DEFAULT       0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: PCIE_TGT_BAD_ACCESS [09:09] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_MASK    0x00000200
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_SHIFT   9
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ACCESS_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: PCIE_TGT_BAD_ADDRESS [08:08] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_MASK   0x00000100
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_SHIFT  8
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_PCIE_TGT_BAD_ADDRESS_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: L1_RX_DMA_ERR_INTR [07:07] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_ERR_INTR_MASK     0x00000080
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_ERR_INTR_SHIFT    7
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_ERR_INTR_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: L1_RX_DMA_DONE_INTR [06:06] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_DONE_INTR_MASK    0x00000040
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_DONE_INTR_SHIFT   6
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_RX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: L1_TX_DMA_ERR_INTR [05:05] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_ERR_INTR_MASK     0x00000020
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_ERR_INTR_SHIFT    5
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_ERR_INTR_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: L1_TX_DMA_DONE_INTR [04:04] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_DONE_INTR_MASK    0x00000010
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_DONE_INTR_SHIFT   4
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L1_TX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: L0_RX_DMA_ERR_INTR [03:03] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_ERR_INTR_MASK     0x00000008
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_ERR_INTR_SHIFT    3
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_ERR_INTR_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: L0_RX_DMA_DONE_INTR [02:02] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_DONE_INTR_MASK    0x00000004
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_DONE_INTR_SHIFT   2
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_RX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: L0_TX_DMA_ERR_INTR [01:01] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_ERR_INTR_MASK     0x00000002
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_ERR_INTR_SHIFT    1
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_ERR_INTR_DEFAULT  0x00000001
+
+/* PCIE_INTR2 :: PCI_MASK_CLEAR :: L0_TX_DMA_DONE_INTR [00:00] */
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_DONE_INTR_MASK    0x00000001
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_DONE_INTR_SHIFT   0
+#define BCHP_PCIE_INTR2_PCI_MASK_CLEAR_L0_TX_DMA_DONE_INTR_DEFAULT 0x00000001
+
+#endif /* #ifndef BCHP_PCIE_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_pcie_misc.h b/include/linux/brcmstb/7435b0/bchp_pcie_misc.h
new file mode 100644
index 0000000..fbf5e13
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_pcie_misc.h
@@ -0,0 +1,796 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:26 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_pcie_misc.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 3:32p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_PCIE_MISC_H__
+#define BCHP_PCIE_MISC_H__
+
+/***************************************************************************
+ *PCIE_MISC - PCI-E Miscellaneous Registers
+ ***************************************************************************/
+#define BCHP_PCIE_MISC_RESET_CTRL                0x00414000 /* Reset Control Register */
+#define BCHP_PCIE_MISC_ECO_CTRL_CORE             0x00414004 /* ECO Core Reset Control Register */
+#define BCHP_PCIE_MISC_MISC_CTRL                 0x00414008 /* MISC Control Register */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO    0x0041400c /* CPU to PCIe Memory Window 0 Low */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI    0x00414010 /* CPU to PCIe Memory Window 0 High */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_LO    0x00414014 /* CPU to PCIe Memory Window 1 Low */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_HI    0x00414018 /* CPU to PCIe Memory Window 1 High */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_LO    0x0041401c /* CPU to PCIe Memory Window 2 Low */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_HI    0x00414020 /* CPU to PCIe Memory Window 2 High */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_LO    0x00414024 /* CPU to PCIe Memory Window 3 Low */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_HI    0x00414028 /* CPU to PCIe Memory Window 3 High */
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_LO         0x0041402c /* RC BAR1 Configuration Low Register */
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_HI         0x00414030 /* RC BAR1 Configuration High Register */
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_LO         0x00414034 /* RC BAR2 Configuration Low Register */
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_HI         0x00414038 /* RC BAR2 Configuration High Register */
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_LO         0x0041403c /* RC BAR3 Configuration Low Register */
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_HI         0x00414040 /* RC BAR3 Configuration High Register */
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_LO         0x00414044 /* Message Signaled Interrupt Base Address Low Register */
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_HI         0x00414048 /* Message Signaled Interrupt Base Address High Register */
+#define BCHP_PCIE_MISC_MSI_DATA_CONFIG           0x0041404c /* Message Signaled Interrupt Data Configuration Register */
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_LO         0x00414050 /* RC Bad Address Register Low */
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_HI         0x00414054 /* RC Bad Address Register High */
+#define BCHP_PCIE_MISC_RC_BAD_DATA               0x00414058 /* RC Bad Data Register */
+#define BCHP_PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT   0x0041405c /* RC Configuration Retry Timeout Register */
+#define BCHP_PCIE_MISC_EOI_CTRL                  0x00414060 /* End of Interrupt Control Register */
+#define BCHP_PCIE_MISC_PCIE_CTRL                 0x00414064 /* PCIe Control */
+#define BCHP_PCIE_MISC_PCIE_STATUS               0x00414068 /* PCIe Status */
+#define BCHP_PCIE_MISC_REVISION                  0x0041406c /* PCIe Revision */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x00414070 /* CPU to PCIe Memory Window 0 base/limit */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT 0x00414074 /* CPU to PCIe Memory Window 1 base/limit */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT 0x00414078 /* CPU to PCIe Memory Window 2 base/limit */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT 0x0041407c /* CPU to PCIe Memory Window 3 base/limit */
+#define BCHP_PCIE_MISC_UBUS_CTRL                 0x00414080 /* UBUS Control */
+#define BCHP_PCIE_MISC_UBUS_TIMEOUT              0x00414084 /* UBUS Timeout */
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP    0x00414088 /* UBUS BAR1 System Bus Address Remap Register */
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP    0x0041408c /* UBUS BAR2 System Bus Address Remap Register */
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP    0x00414090 /* UBUS BAR3 System Bus Address Remap Register */
+#define BCHP_PCIE_MISC_UBUS_STATUS               0x00414094 /* UBUS Status */
+
+/***************************************************************************
+ *RESET_CTRL - Reset Control Register
+ ***************************************************************************/
+/* PCIE_MISC :: RESET_CTRL :: reserved0 [31:01] */
+#define BCHP_PCIE_MISC_RESET_CTRL_reserved0_MASK                   0xfffffffe
+#define BCHP_PCIE_MISC_RESET_CTRL_reserved0_SHIFT                  1
+
+/* PCIE_MISC :: RESET_CTRL :: CORE_RESET [00:00] */
+#define BCHP_PCIE_MISC_RESET_CTRL_CORE_RESET_MASK                  0x00000001
+#define BCHP_PCIE_MISC_RESET_CTRL_CORE_RESET_SHIFT                 0
+#define BCHP_PCIE_MISC_RESET_CTRL_CORE_RESET_DEFAULT               0x00000000
+
+/***************************************************************************
+ *ECO_CTRL_CORE - ECO Core Reset Control Register
+ ***************************************************************************/
+/* PCIE_MISC :: ECO_CTRL_CORE :: reserved0 [31:16] */
+#define BCHP_PCIE_MISC_ECO_CTRL_CORE_reserved0_MASK                0xffff0000
+#define BCHP_PCIE_MISC_ECO_CTRL_CORE_reserved0_SHIFT               16
+
+/* PCIE_MISC :: ECO_CTRL_CORE :: ECO_CORE_RST_N [15:00] */
+#define BCHP_PCIE_MISC_ECO_CTRL_CORE_ECO_CORE_RST_N_MASK           0x0000ffff
+#define BCHP_PCIE_MISC_ECO_CTRL_CORE_ECO_CORE_RST_N_SHIFT          0
+#define BCHP_PCIE_MISC_ECO_CTRL_CORE_ECO_CORE_RST_N_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MISC_CTRL - MISC Control Register
+ ***************************************************************************/
+/* PCIE_MISC :: MISC_CTRL :: SCB0_SIZE [31:27] */
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK                    0xf8000000
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT                   27
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB0_SIZE_DEFAULT                 0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: SCB1_SIZE [26:22] */
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK                    0x07c00000
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT                   22
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB1_SIZE_DEFAULT                 0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: TBD_OPTION_21 [21:21] */
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_21_MASK                0x00200000
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_21_SHIFT               21
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_21_DEFAULT             0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: SCB_MAX_BURST_SIZE [20:20] */
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB_MAX_BURST_SIZE_MASK           0x00100000
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB_MAX_BURST_SIZE_SHIFT          20
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB_MAX_BURST_SIZE_DEFAULT        0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: TBD_OPTION_19 [19:19] */
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_19_MASK                0x00080000
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_19_SHIFT               19
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_19_DEFAULT             0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: TBD_OPTION_18 [18:18] */
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_18_MASK                0x00040000
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_18_SHIFT               18
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_18_DEFAULT             0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: CSR_CFG_MODE [17:17] */
+#define BCHP_PCIE_MISC_MISC_CTRL_CSR_CFG_MODE_MASK                 0x00020000
+#define BCHP_PCIE_MISC_MISC_CTRL_CSR_CFG_MODE_SHIFT                17
+#define BCHP_PCIE_MISC_MISC_CTRL_CSR_CFG_MODE_DEFAULT              0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: CSR_CFG_RETRY_EN [16:16] */
+#define BCHP_PCIE_MISC_MISC_CTRL_CSR_CFG_RETRY_EN_MASK             0x00010000
+#define BCHP_PCIE_MISC_MISC_CTRL_CSR_CFG_RETRY_EN_SHIFT            16
+#define BCHP_PCIE_MISC_MISC_CTRL_CSR_CFG_RETRY_EN_DEFAULT          0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: TBD_OPTION_15 [15:15] */
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_15_MASK                0x00008000
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_15_SHIFT               15
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_15_DEFAULT             0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: TBD_OPTION_14 [14:14] */
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_14_MASK                0x00004000
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_14_SHIFT               14
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_14_DEFAULT             0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: CFG_READ_UR_MODE [13:13] */
+#define BCHP_PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK             0x00002000
+#define BCHP_PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT            13
+#define BCHP_PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_DEFAULT          0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: SCB_ACCESS_EN [12:12] */
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK                0x00001000
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT               12
+#define BCHP_PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_DEFAULT             0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: TBD_OPTION_11 [11:11] */
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_11_MASK                0x00000800
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_11_SHIFT               11
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_11_DEFAULT             0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: TBD_OPTION_10 [10:10] */
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_10_MASK                0x00000400
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_10_SHIFT               10
+#define BCHP_PCIE_MISC_MISC_CTRL_TBD_OPTION_10_DEFAULT             0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: DESC_PRIORITY_EN [09:09] */
+#define BCHP_PCIE_MISC_MISC_CTRL_DESC_PRIORITY_EN_MASK             0x00000200
+#define BCHP_PCIE_MISC_MISC_CTRL_DESC_PRIORITY_EN_SHIFT            9
+#define BCHP_PCIE_MISC_MISC_CTRL_DESC_PRIORITY_EN_DEFAULT          0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: READ_PRIORITY_EN [08:08] */
+#define BCHP_PCIE_MISC_MISC_CTRL_READ_PRIORITY_EN_MASK             0x00000100
+#define BCHP_PCIE_MISC_MISC_CTRL_READ_PRIORITY_EN_SHIFT            8
+#define BCHP_PCIE_MISC_MISC_CTRL_READ_PRIORITY_EN_DEFAULT          0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: PCIE_RCB_64B_MODE [07:07] */
+#define BCHP_PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK            0x00000080
+#define BCHP_PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_SHIFT           7
+#define BCHP_PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_DEFAULT         0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: PCIE_OUT_CPL_RO [06:06] */
+#define BCHP_PCIE_MISC_MISC_CTRL_PCIE_OUT_CPL_RO_MASK              0x00000040
+#define BCHP_PCIE_MISC_MISC_CTRL_PCIE_OUT_CPL_RO_SHIFT             6
+#define BCHP_PCIE_MISC_MISC_CTRL_PCIE_OUT_CPL_RO_DEFAULT           0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: PCIE_IN_CPL_RO [05:05] */
+#define BCHP_PCIE_MISC_MISC_CTRL_PCIE_IN_CPL_RO_MASK               0x00000020
+#define BCHP_PCIE_MISC_MISC_CTRL_PCIE_IN_CPL_RO_SHIFT              5
+#define BCHP_PCIE_MISC_MISC_CTRL_PCIE_IN_CPL_RO_DEFAULT            0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: RELAXED_ORDERING [04:04] */
+#define BCHP_PCIE_MISC_MISC_CTRL_RELAXED_ORDERING_MASK             0x00000010
+#define BCHP_PCIE_MISC_MISC_CTRL_RELAXED_ORDERING_SHIFT            4
+#define BCHP_PCIE_MISC_MISC_CTRL_RELAXED_ORDERING_DEFAULT          0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: NO_SNOOP [03:03] */
+#define BCHP_PCIE_MISC_MISC_CTRL_NO_SNOOP_MASK                     0x00000008
+#define BCHP_PCIE_MISC_MISC_CTRL_NO_SNOOP_SHIFT                    3
+#define BCHP_PCIE_MISC_MISC_CTRL_NO_SNOOP_DEFAULT                  0x00000000
+
+/* PCIE_MISC :: MISC_CTRL :: TRAFFIC_CLASS [02:00] */
+#define BCHP_PCIE_MISC_MISC_CTRL_TRAFFIC_CLASS_MASK                0x00000007
+#define BCHP_PCIE_MISC_MISC_CTRL_TRAFFIC_CLASS_SHIFT               0
+#define BCHP_PCIE_MISC_MISC_CTRL_TRAFFIC_CLASS_DEFAULT             0x00000000
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN0_LO - CPU to PCIe Memory Window 0 Low
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN0_LO :: BASE_ADDR [31:20] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO_BASE_ADDR_MASK       0xfff00000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO_BASE_ADDR_SHIFT      20
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO_BASE_ADDR_DEFAULT    0x00000000
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN0_LO :: reserved0 [19:02] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO_reserved0_MASK       0x000ffffc
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO_reserved0_SHIFT      2
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN0_LO :: ENDIAN_MODE [01:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO_ENDIAN_MODE_MASK     0x00000003
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO_ENDIAN_MODE_SHIFT    0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO_ENDIAN_MODE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN0_HI - CPU to PCIe Memory Window 0 High
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN0_HI :: BASE_ADDR [31:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI_BASE_ADDR_MASK       0xffffffff
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI_BASE_ADDR_SHIFT      0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI_BASE_ADDR_DEFAULT    0x00000000
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN1_LO - CPU to PCIe Memory Window 1 Low
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN1_LO :: BASE_ADDR [31:20] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_LO_BASE_ADDR_MASK       0xfff00000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_LO_BASE_ADDR_SHIFT      20
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_LO_BASE_ADDR_DEFAULT    0x00000000
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN1_LO :: reserved0 [19:02] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_LO_reserved0_MASK       0x000ffffc
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_LO_reserved0_SHIFT      2
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN1_LO :: ENDIAN_MODE [01:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_LO_ENDIAN_MODE_MASK     0x00000003
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_LO_ENDIAN_MODE_SHIFT    0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_LO_ENDIAN_MODE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN1_HI - CPU to PCIe Memory Window 1 High
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN1_HI :: BASE_ADDR [31:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_HI_BASE_ADDR_MASK       0xffffffff
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_HI_BASE_ADDR_SHIFT      0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_HI_BASE_ADDR_DEFAULT    0x00000000
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN2_LO - CPU to PCIe Memory Window 2 Low
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN2_LO :: BASE_ADDR [31:20] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_LO_BASE_ADDR_MASK       0xfff00000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_LO_BASE_ADDR_SHIFT      20
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_LO_BASE_ADDR_DEFAULT    0x00000000
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN2_LO :: reserved0 [19:02] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_LO_reserved0_MASK       0x000ffffc
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_LO_reserved0_SHIFT      2
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN2_LO :: ENDIAN_MODE [01:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_LO_ENDIAN_MODE_MASK     0x00000003
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_LO_ENDIAN_MODE_SHIFT    0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_LO_ENDIAN_MODE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN2_HI - CPU to PCIe Memory Window 2 High
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN2_HI :: BASE_ADDR [31:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_HI_BASE_ADDR_MASK       0xffffffff
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_HI_BASE_ADDR_SHIFT      0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_HI_BASE_ADDR_DEFAULT    0x00000000
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN3_LO - CPU to PCIe Memory Window 3 Low
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN3_LO :: BASE_ADDR [31:20] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_LO_BASE_ADDR_MASK       0xfff00000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_LO_BASE_ADDR_SHIFT      20
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_LO_BASE_ADDR_DEFAULT    0x00000000
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN3_LO :: reserved0 [19:02] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_LO_reserved0_MASK       0x000ffffc
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_LO_reserved0_SHIFT      2
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN3_LO :: ENDIAN_MODE [01:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_LO_ENDIAN_MODE_MASK     0x00000003
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_LO_ENDIAN_MODE_SHIFT    0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_LO_ENDIAN_MODE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN3_HI - CPU to PCIe Memory Window 3 High
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN3_HI :: BASE_ADDR [31:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_HI_BASE_ADDR_MASK       0xffffffff
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_HI_BASE_ADDR_SHIFT      0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_HI_BASE_ADDR_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RC_BAR1_CONFIG_LO - RC BAR1 Configuration Low Register
+ ***************************************************************************/
+/* PCIE_MISC :: RC_BAR1_CONFIG_LO :: MATCH_ADDRESS [31:12] */
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_LO_MATCH_ADDRESS_MASK        0xfffff000
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_LO_MATCH_ADDRESS_SHIFT       12
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_LO_MATCH_ADDRESS_DEFAULT     0x00000000
+
+/* PCIE_MISC :: RC_BAR1_CONFIG_LO :: reserved0 [11:05] */
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_LO_reserved0_MASK            0x00000fe0
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_LO_reserved0_SHIFT           5
+
+/* PCIE_MISC :: RC_BAR1_CONFIG_LO :: SIZE [04:00] */
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK                 0x0000001f
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT                0
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RC_BAR1_CONFIG_HI - RC BAR1 Configuration High Register
+ ***************************************************************************/
+/* PCIE_MISC :: RC_BAR1_CONFIG_HI :: MATCH_ADDRESS [31:00] */
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_HI_MATCH_ADDRESS_MASK        0xffffffff
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_HI_MATCH_ADDRESS_SHIFT       0
+#define BCHP_PCIE_MISC_RC_BAR1_CONFIG_HI_MATCH_ADDRESS_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RC_BAR2_CONFIG_LO - RC BAR2 Configuration Low Register
+ ***************************************************************************/
+/* PCIE_MISC :: RC_BAR2_CONFIG_LO :: MATCH_ADDRESS [31:12] */
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_LO_MATCH_ADDRESS_MASK        0xfffff000
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_LO_MATCH_ADDRESS_SHIFT       12
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_LO_MATCH_ADDRESS_DEFAULT     0x00000000
+
+/* PCIE_MISC :: RC_BAR2_CONFIG_LO :: reserved0 [11:05] */
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_LO_reserved0_MASK            0x00000fe0
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_LO_reserved0_SHIFT           5
+
+/* PCIE_MISC :: RC_BAR2_CONFIG_LO :: SIZE [04:00] */
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK                 0x0000001f
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT                0
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RC_BAR2_CONFIG_HI - RC BAR2 Configuration High Register
+ ***************************************************************************/
+/* PCIE_MISC :: RC_BAR2_CONFIG_HI :: MATCH_ADDRESS [31:00] */
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_HI_MATCH_ADDRESS_MASK        0xffffffff
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_HI_MATCH_ADDRESS_SHIFT       0
+#define BCHP_PCIE_MISC_RC_BAR2_CONFIG_HI_MATCH_ADDRESS_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RC_BAR3_CONFIG_LO - RC BAR3 Configuration Low Register
+ ***************************************************************************/
+/* PCIE_MISC :: RC_BAR3_CONFIG_LO :: MATCH_ADDRESS [31:12] */
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_LO_MATCH_ADDRESS_MASK        0xfffff000
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_LO_MATCH_ADDRESS_SHIFT       12
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_LO_MATCH_ADDRESS_DEFAULT     0x00000000
+
+/* PCIE_MISC :: RC_BAR3_CONFIG_LO :: reserved0 [11:05] */
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_LO_reserved0_MASK            0x00000fe0
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_LO_reserved0_SHIFT           5
+
+/* PCIE_MISC :: RC_BAR3_CONFIG_LO :: SIZE [04:00] */
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK                 0x0000001f
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT                0
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RC_BAR3_CONFIG_HI - RC BAR3 Configuration High Register
+ ***************************************************************************/
+/* PCIE_MISC :: RC_BAR3_CONFIG_HI :: MATCH_ADDRESS [31:00] */
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_HI_MATCH_ADDRESS_MASK        0xffffffff
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_HI_MATCH_ADDRESS_SHIFT       0
+#define BCHP_PCIE_MISC_RC_BAR3_CONFIG_HI_MATCH_ADDRESS_DEFAULT     0x00000000
+
+/***************************************************************************
+ *MSI_BAR_CONFIG_LO - Message Signaled Interrupt Base Address Low Register
+ ***************************************************************************/
+/* PCIE_MISC :: MSI_BAR_CONFIG_LO :: MATCH_ADDRESS [31:02] */
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_LO_MATCH_ADDRESS_MASK        0xfffffffc
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_LO_MATCH_ADDRESS_SHIFT       2
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_LO_MATCH_ADDRESS_DEFAULT     0x00000000
+
+/* PCIE_MISC :: MSI_BAR_CONFIG_LO :: reserved0 [01:01] */
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_LO_reserved0_MASK            0x00000002
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_LO_reserved0_SHIFT           1
+
+/* PCIE_MISC :: MSI_BAR_CONFIG_LO :: ENABLE [00:00] */
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_LO_ENABLE_MASK               0x00000001
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_LO_ENABLE_SHIFT              0
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_LO_ENABLE_DEFAULT            0x00000000
+
+/***************************************************************************
+ *MSI_BAR_CONFIG_HI - Message Signaled Interrupt Base Address High Register
+ ***************************************************************************/
+/* PCIE_MISC :: MSI_BAR_CONFIG_HI :: MATCH_ADDRESS [31:00] */
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_HI_MATCH_ADDRESS_MASK        0xffffffff
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_HI_MATCH_ADDRESS_SHIFT       0
+#define BCHP_PCIE_MISC_MSI_BAR_CONFIG_HI_MATCH_ADDRESS_DEFAULT     0x00000000
+
+/***************************************************************************
+ *MSI_DATA_CONFIG - Message Signaled Interrupt Data Configuration Register
+ ***************************************************************************/
+/* PCIE_MISC :: MSI_DATA_CONFIG :: MASK [31:16] */
+#define BCHP_PCIE_MISC_MSI_DATA_CONFIG_MASK_MASK                   0xffff0000
+#define BCHP_PCIE_MISC_MSI_DATA_CONFIG_MASK_SHIFT                  16
+#define BCHP_PCIE_MISC_MSI_DATA_CONFIG_MASK_DEFAULT                0x00000000
+
+/* PCIE_MISC :: MSI_DATA_CONFIG :: DATA [15:00] */
+#define BCHP_PCIE_MISC_MSI_DATA_CONFIG_DATA_MASK                   0x0000ffff
+#define BCHP_PCIE_MISC_MSI_DATA_CONFIG_DATA_SHIFT                  0
+#define BCHP_PCIE_MISC_MSI_DATA_CONFIG_DATA_DEFAULT                0x00000000
+
+/***************************************************************************
+ *RC_BAD_ADDRESS_LO - RC Bad Address Register Low
+ ***************************************************************************/
+/* PCIE_MISC :: RC_BAD_ADDRESS_LO :: ADDRESS [31:02] */
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_LO_ADDRESS_MASK              0xfffffffc
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_LO_ADDRESS_SHIFT             2
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_LO_ADDRESS_DEFAULT           0x00000000
+
+/* PCIE_MISC :: RC_BAD_ADDRESS_LO :: reserved0 [01:01] */
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_LO_reserved0_MASK            0x00000002
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_LO_reserved0_SHIFT           1
+
+/* PCIE_MISC :: RC_BAD_ADDRESS_LO :: VALID [00:00] */
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_LO_VALID_MASK                0x00000001
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_LO_VALID_SHIFT               0
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_LO_VALID_DEFAULT             0x00000000
+
+/***************************************************************************
+ *RC_BAD_ADDRESS_HI - RC Bad Address Register High
+ ***************************************************************************/
+/* PCIE_MISC :: RC_BAD_ADDRESS_HI :: ADDRESS [31:00] */
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_HI_ADDRESS_MASK              0xffffffff
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_HI_ADDRESS_SHIFT             0
+#define BCHP_PCIE_MISC_RC_BAD_ADDRESS_HI_ADDRESS_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RC_BAD_DATA - RC Bad Data Register
+ ***************************************************************************/
+/* PCIE_MISC :: RC_BAD_DATA :: DATA [31:00] */
+#define BCHP_PCIE_MISC_RC_BAD_DATA_DATA_MASK                       0xffffffff
+#define BCHP_PCIE_MISC_RC_BAD_DATA_DATA_SHIFT                      0
+#define BCHP_PCIE_MISC_RC_BAD_DATA_DATA_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *RC_CONFIG_RETRY_TIMEOUT - RC Configuration Retry Timeout Register
+ ***************************************************************************/
+/* PCIE_MISC :: RC_CONFIG_RETRY_TIMEOUT :: TIMER_VALUE [31:00] */
+#define BCHP_PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT_TIMER_VALUE_MASK    0xffffffff
+#define BCHP_PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT_TIMER_VALUE_SHIFT   0
+#define BCHP_PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT_TIMER_VALUE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EOI_CTRL - End of Interrupt Control Register
+ ***************************************************************************/
+/* PCIE_MISC :: EOI_CTRL :: reserved0 [31:01] */
+#define BCHP_PCIE_MISC_EOI_CTRL_reserved0_MASK                     0xfffffffe
+#define BCHP_PCIE_MISC_EOI_CTRL_reserved0_SHIFT                    1
+
+/* PCIE_MISC :: EOI_CTRL :: EOI [00:00] */
+#define BCHP_PCIE_MISC_EOI_CTRL_EOI_MASK                           0x00000001
+#define BCHP_PCIE_MISC_EOI_CTRL_EOI_SHIFT                          0
+#define BCHP_PCIE_MISC_EOI_CTRL_EOI_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *PCIE_CTRL - PCIe Control
+ ***************************************************************************/
+/* PCIE_MISC :: PCIE_CTRL :: reserved0 [31:02] */
+#define BCHP_PCIE_MISC_PCIE_CTRL_reserved0_MASK                    0xfffffffc
+#define BCHP_PCIE_MISC_PCIE_CTRL_reserved0_SHIFT                   2
+
+/* PCIE_MISC :: PCIE_CTRL :: PCIE_PME_REQUEST [01:01] */
+#define BCHP_PCIE_MISC_PCIE_CTRL_PCIE_PME_REQUEST_MASK             0x00000002
+#define BCHP_PCIE_MISC_PCIE_CTRL_PCIE_PME_REQUEST_SHIFT            1
+#define BCHP_PCIE_MISC_PCIE_CTRL_PCIE_PME_REQUEST_DEFAULT          0x00000000
+
+/* PCIE_MISC :: PCIE_CTRL :: PCIE_L23_REQUEST [00:00] */
+#define BCHP_PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK             0x00000001
+#define BCHP_PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT            0
+#define BCHP_PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PCIE_STATUS - PCIe Status
+ ***************************************************************************/
+/* PCIE_MISC :: PCIE_STATUS :: reserved0 [31:13] */
+#define BCHP_PCIE_MISC_PCIE_STATUS_reserved0_MASK                  0xffffe000
+#define BCHP_PCIE_MISC_PCIE_STATUS_reserved0_SHIFT                 13
+
+/* PCIE_MISC :: PCIE_STATUS :: PCIE_SSC_STATUS [12:12] */
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_SSC_STATUS_MASK            0x00001000
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_SSC_STATUS_SHIFT           12
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_SSC_STATUS_DEFAULT         0x00000000
+
+/* PCIE_MISC :: PCIE_STATUS :: PCIE_PM_STATE [11:10] */
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_PM_STATE_MASK              0x00000c00
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_PM_STATE_SHIFT             10
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_PM_STATE_DEFAULT           0x00000000
+
+/* PCIE_MISC :: PCIE_STATUS :: PCIE_WAKE [09:09] */
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_WAKE_MASK                  0x00000200
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_WAKE_SHIFT                 9
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_WAKE_DEFAULT               0x00000000
+
+/* PCIE_MISC :: PCIE_STATUS :: PCIE_PME_EVENT [08:08] */
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_PME_EVENT_MASK             0x00000100
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_PME_EVENT_SHIFT            8
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_PME_EVENT_DEFAULT          0x00000000
+
+/* PCIE_MISC :: PCIE_STATUS :: PCIE_PORT [07:07] */
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK                  0x00000080
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT                 7
+
+/* PCIE_MISC :: PCIE_STATUS :: PCIE_LINK_IN_L23 [06:06] */
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK           0x00000040
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT          6
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_DEFAULT        0x00000000
+
+/* PCIE_MISC :: PCIE_STATUS :: PCIE_DL_ACTIVE [05:05] */
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK             0x00000020
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT            5
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_DEFAULT          0x00000000
+
+/* PCIE_MISC :: PCIE_STATUS :: PCIE_PHYLINKUP [04:04] */
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK             0x00000010
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT            4
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_DEFAULT          0x00000000
+
+/* PCIE_MISC :: PCIE_STATUS :: PCIE_ERR_STATUS [03:00] */
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_ERR_STATUS_MASK            0x0000000f
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_ERR_STATUS_SHIFT           0
+#define BCHP_PCIE_MISC_PCIE_STATUS_PCIE_ERR_STATUS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *REVISION - PCIe Revision
+ ***************************************************************************/
+/* PCIE_MISC :: REVISION :: reserved0 [31:16] */
+#define BCHP_PCIE_MISC_REVISION_reserved0_MASK                     0xffff0000
+#define BCHP_PCIE_MISC_REVISION_reserved0_SHIFT                    16
+
+/* PCIE_MISC :: REVISION :: MAJOR [15:08] */
+#define BCHP_PCIE_MISC_REVISION_MAJOR_MASK                         0x0000ff00
+#define BCHP_PCIE_MISC_REVISION_MAJOR_SHIFT                        8
+#define BCHP_PCIE_MISC_REVISION_MAJOR_DEFAULT                      0x00000002
+
+/* PCIE_MISC :: REVISION :: MINOR [07:00] */
+#define BCHP_PCIE_MISC_REVISION_MINOR_MASK                         0x000000ff
+#define BCHP_PCIE_MISC_REVISION_MINOR_SHIFT                        0
+#define BCHP_PCIE_MISC_REVISION_MINOR_DEFAULT                      0x00000003
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN0_BASE_LIMIT - CPU to PCIe Memory Window 0 base/limit
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_LIMIT :: LIMIT [31:20] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK   0xfff00000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT  20
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_DEFAULT 0x00000000
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_LIMIT :: reserved0 [19:16] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_reserved0_MASK 0x000f0000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_reserved0_SHIFT 16
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_LIMIT :: BASE [15:04] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK    0x0000fff0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT   4
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_DEFAULT 0x00000001
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN0_BASE_LIMIT :: reserved1 [03:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_reserved1_MASK 0x0000000f
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_reserved1_SHIFT 0
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN1_BASE_LIMIT - CPU to PCIe Memory Window 1 base/limit
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_LIMIT :: LIMIT [31:20] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_LIMIT_MASK   0xfff00000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_LIMIT_SHIFT  20
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_LIMIT_DEFAULT 0x00000000
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_LIMIT :: reserved0 [19:16] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_reserved0_MASK 0x000f0000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_reserved0_SHIFT 16
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_LIMIT :: BASE [15:04] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_BASE_MASK    0x0000fff0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_BASE_SHIFT   4
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_BASE_DEFAULT 0x00000001
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN1_BASE_LIMIT :: reserved1 [03:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_reserved1_MASK 0x0000000f
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN1_BASE_LIMIT_reserved1_SHIFT 0
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN2_BASE_LIMIT - CPU to PCIe Memory Window 2 base/limit
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_LIMIT :: LIMIT [31:20] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_LIMIT_MASK   0xfff00000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_LIMIT_SHIFT  20
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_LIMIT_DEFAULT 0x00000000
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_LIMIT :: reserved0 [19:16] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_reserved0_MASK 0x000f0000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_reserved0_SHIFT 16
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_LIMIT :: BASE [15:04] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_BASE_MASK    0x0000fff0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_BASE_SHIFT   4
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_BASE_DEFAULT 0x00000001
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN2_BASE_LIMIT :: reserved1 [03:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_reserved1_MASK 0x0000000f
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN2_BASE_LIMIT_reserved1_SHIFT 0
+
+/***************************************************************************
+ *CPU_2_PCIE_MEM_WIN3_BASE_LIMIT - CPU to PCIe Memory Window 3 base/limit
+ ***************************************************************************/
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_LIMIT :: LIMIT [31:20] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_LIMIT_MASK   0xfff00000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_LIMIT_SHIFT  20
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_LIMIT_DEFAULT 0x00000000
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_LIMIT :: reserved0 [19:16] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_reserved0_MASK 0x000f0000
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_reserved0_SHIFT 16
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_LIMIT :: BASE [15:04] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_BASE_MASK    0x0000fff0
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_BASE_SHIFT   4
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_BASE_DEFAULT 0x00000001
+
+/* PCIE_MISC :: CPU_2_PCIE_MEM_WIN3_BASE_LIMIT :: reserved1 [03:00] */
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_reserved1_MASK 0x0000000f
+#define BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN3_BASE_LIMIT_reserved1_SHIFT 0
+
+/***************************************************************************
+ *UBUS_CTRL - UBUS Control
+ ***************************************************************************/
+/* PCIE_MISC :: UBUS_CTRL :: TBD_OPTION_31_17 [31:17] */
+#define BCHP_PCIE_MISC_UBUS_CTRL_TBD_OPTION_31_17_MASK             0xfffe0000
+#define BCHP_PCIE_MISC_UBUS_CTRL_TBD_OPTION_31_17_SHIFT            17
+#define BCHP_PCIE_MISC_UBUS_CTRL_TBD_OPTION_31_17_DEFAULT          0x00000000
+
+/* PCIE_MISC :: UBUS_CTRL :: UBUS_DMA_WR_WITH_REPLY [16:15] */
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_DMA_WR_WITH_REPLY_MASK       0x00018000
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_DMA_WR_WITH_REPLY_SHIFT      15
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_DMA_WR_WITH_REPLY_DEFAULT    0x00000000
+
+/* PCIE_MISC :: UBUS_CTRL :: UBUS_WR_WITH_REPLY [14:14] */
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_WR_WITH_REPLY_MASK           0x00004000
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_WR_WITH_REPLY_SHIFT          14
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_WR_WITH_REPLY_DEFAULT        0x00000000
+
+/* PCIE_MISC :: UBUS_CTRL :: UBUS_PCIE_REPLY_ERR_DIS [13:13] */
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK      0x00002000
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_SHIFT     13
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_DEFAULT   0x00000000
+
+/* PCIE_MISC :: UBUS_CTRL :: UBUS_REG_ACCESS_RO [12:12] */
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_REG_ACCESS_RO_MASK           0x00001000
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_REG_ACCESS_RO_SHIFT          12
+#define BCHP_PCIE_MISC_UBUS_CTRL_UBUS_REG_ACCESS_RO_DEFAULT        0x00000000
+
+/* PCIE_MISC :: UBUS_CTRL :: REQIN_HDR_THRESHOLD [11:06] */
+#define BCHP_PCIE_MISC_UBUS_CTRL_REQIN_HDR_THRESHOLD_MASK          0x00000fc0
+#define BCHP_PCIE_MISC_UBUS_CTRL_REQIN_HDR_THRESHOLD_SHIFT         6
+#define BCHP_PCIE_MISC_UBUS_CTRL_REQIN_HDR_THRESHOLD_DEFAULT       0x00000008
+
+/* PCIE_MISC :: UBUS_CTRL :: REQIN_WR_DATA_THRESHOLD [05:00] */
+#define BCHP_PCIE_MISC_UBUS_CTRL_REQIN_WR_DATA_THRESHOLD_MASK      0x0000003f
+#define BCHP_PCIE_MISC_UBUS_CTRL_REQIN_WR_DATA_THRESHOLD_SHIFT     0
+#define BCHP_PCIE_MISC_UBUS_CTRL_REQIN_WR_DATA_THRESHOLD_DEFAULT   0x00000020
+
+/***************************************************************************
+ *UBUS_TIMEOUT - UBUS Timeout
+ ***************************************************************************/
+/* PCIE_MISC :: UBUS_TIMEOUT :: TIMER_VALUE [31:00] */
+#define BCHP_PCIE_MISC_UBUS_TIMEOUT_TIMER_VALUE_MASK               0xffffffff
+#define BCHP_PCIE_MISC_UBUS_TIMEOUT_TIMER_VALUE_SHIFT              0
+#define BCHP_PCIE_MISC_UBUS_TIMEOUT_TIMER_VALUE_DEFAULT            0x00080000
+
+/***************************************************************************
+ *UBUS_BAR1_CONFIG_REMAP - UBUS BAR1 System Bus Address Remap Register
+ ***************************************************************************/
+/* PCIE_MISC :: UBUS_BAR1_CONFIG_REMAP :: OFFSET [31:12] */
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_OFFSET_MASK          0xfffff000
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_OFFSET_SHIFT         12
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_OFFSET_DEFAULT       0x00000000
+
+/* PCIE_MISC :: UBUS_BAR1_CONFIG_REMAP :: reserved0 [11:04] */
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_reserved0_MASK       0x00000ff0
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_reserved0_SHIFT      4
+
+/* PCIE_MISC :: UBUS_BAR1_CONFIG_REMAP :: UNUSED_3_1 [03:01] */
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_UNUSED_3_1_MASK      0x0000000e
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_UNUSED_3_1_SHIFT     1
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_UNUSED_3_1_DEFAULT   0x00000000
+
+/* PCIE_MISC :: UBUS_BAR1_CONFIG_REMAP :: ACCESS_EN [00:00] */
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_MASK       0x00000001
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_SHIFT      0
+#define BCHP_PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_DEFAULT    0x00000000
+
+/***************************************************************************
+ *UBUS_BAR2_CONFIG_REMAP - UBUS BAR2 System Bus Address Remap Register
+ ***************************************************************************/
+/* PCIE_MISC :: UBUS_BAR2_CONFIG_REMAP :: OFFSET [31:12] */
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_OFFSET_MASK          0xfffff000
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_OFFSET_SHIFT         12
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_OFFSET_DEFAULT       0x00000000
+
+/* PCIE_MISC :: UBUS_BAR2_CONFIG_REMAP :: reserved0 [11:04] */
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_reserved0_MASK       0x00000ff0
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_reserved0_SHIFT      4
+
+/* PCIE_MISC :: UBUS_BAR2_CONFIG_REMAP :: UNUSED_3_1 [03:01] */
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_UNUSED_3_1_MASK      0x0000000e
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_UNUSED_3_1_SHIFT     1
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_UNUSED_3_1_DEFAULT   0x00000000
+
+/* PCIE_MISC :: UBUS_BAR2_CONFIG_REMAP :: ACCESS_EN [00:00] */
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_EN_MASK       0x00000001
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_EN_SHIFT      0
+#define BCHP_PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_EN_DEFAULT    0x00000000
+
+/***************************************************************************
+ *UBUS_BAR3_CONFIG_REMAP - UBUS BAR3 System Bus Address Remap Register
+ ***************************************************************************/
+/* PCIE_MISC :: UBUS_BAR3_CONFIG_REMAP :: OFFSET [31:12] */
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP_OFFSET_MASK          0xfffff000
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP_OFFSET_SHIFT         12
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP_OFFSET_DEFAULT       0x00000000
+
+/* PCIE_MISC :: UBUS_BAR3_CONFIG_REMAP :: reserved0 [11:04] */
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP_reserved0_MASK       0x00000ff0
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP_reserved0_SHIFT      4
+
+/* PCIE_MISC :: UBUS_BAR3_CONFIG_REMAP :: UNUSED_3_1 [03:01] */
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP_UNUSED_3_1_MASK      0x0000000e
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP_UNUSED_3_1_SHIFT     1
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP_UNUSED_3_1_DEFAULT   0x00000000
+
+/* PCIE_MISC :: UBUS_BAR3_CONFIG_REMAP :: ACCESS_EN [00:00] */
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP_ACCESS_EN_MASK       0x00000001
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP_ACCESS_EN_SHIFT      0
+#define BCHP_PCIE_MISC_UBUS_BAR3_CONFIG_REMAP_ACCESS_EN_DEFAULT    0x00000000
+
+/***************************************************************************
+ *UBUS_STATUS - UBUS Status
+ ***************************************************************************/
+/* PCIE_MISC :: UBUS_STATUS :: SLAVE_REPOUT_HSPACE [31:24] */
+#define BCHP_PCIE_MISC_UBUS_STATUS_SLAVE_REPOUT_HSPACE_MASK        0xff000000
+#define BCHP_PCIE_MISC_UBUS_STATUS_SLAVE_REPOUT_HSPACE_SHIFT       24
+#define BCHP_PCIE_MISC_UBUS_STATUS_SLAVE_REPOUT_HSPACE_DEFAULT     0x00000010
+
+/* PCIE_MISC :: UBUS_STATUS :: SLAVE_REPOUT_DSPACE [23:16] */
+#define BCHP_PCIE_MISC_UBUS_STATUS_SLAVE_REPOUT_DSPACE_MASK        0x00ff0000
+#define BCHP_PCIE_MISC_UBUS_STATUS_SLAVE_REPOUT_DSPACE_SHIFT       16
+#define BCHP_PCIE_MISC_UBUS_STATUS_SLAVE_REPOUT_DSPACE_DEFAULT     0x00000020
+
+/* PCIE_MISC :: UBUS_STATUS :: MASTER_REQOUT_HSPACE [15:08] */
+#define BCHP_PCIE_MISC_UBUS_STATUS_MASTER_REQOUT_HSPACE_MASK       0x0000ff00
+#define BCHP_PCIE_MISC_UBUS_STATUS_MASTER_REQOUT_HSPACE_SHIFT      8
+#define BCHP_PCIE_MISC_UBUS_STATUS_MASTER_REQOUT_HSPACE_DEFAULT    0x00000010
+
+/* PCIE_MISC :: UBUS_STATUS :: MASTER_REQOUT_DSPACE [07:00] */
+#define BCHP_PCIE_MISC_UBUS_STATUS_MASTER_REQOUT_DSPACE_MASK       0x000000ff
+#define BCHP_PCIE_MISC_UBUS_STATUS_MASTER_REQOUT_DSPACE_SHIFT      0
+#define BCHP_PCIE_MISC_UBUS_STATUS_MASTER_REQOUT_DSPACE_DEFAULT    0x00000020
+
+#endif /* #ifndef BCHP_PCIE_MISC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_pcie_misc_hard.h b/include/linux/brcmstb/7435b0/bchp_pcie_misc_hard.h
new file mode 100644
index 0000000..f127545
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_pcie_misc_hard.h
@@ -0,0 +1,153 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Jul 27 03:16:52 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_PCIE_MISC_HARD_H__
+#define BCHP_PCIE_MISC_HARD_H__
+
+/***************************************************************************
+ *PCIE_MISC_HARD - PCI-E Miscellaneous Registers (Hard reset)
+ ***************************************************************************/
+#define BCHP_PCIE_MISC_HARD_ECO_CTRL_HARD        0x00414200 /* ECO Hard Reset Control Register */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG      0x00414204 /* PCIE Hard Debug Register */
+
+/***************************************************************************
+ *ECO_CTRL_HARD - ECO Hard Reset Control Register
+ ***************************************************************************/
+/* PCIE_MISC_HARD :: ECO_CTRL_HARD :: reserved0 [31:16] */
+#define BCHP_PCIE_MISC_HARD_ECO_CTRL_HARD_reserved0_MASK           0xffff0000
+#define BCHP_PCIE_MISC_HARD_ECO_CTRL_HARD_reserved0_SHIFT          16
+
+/* PCIE_MISC_HARD :: ECO_CTRL_HARD :: ECO_HARD [15:00] */
+#define BCHP_PCIE_MISC_HARD_ECO_CTRL_HARD_ECO_HARD_MASK            0x0000ffff
+#define BCHP_PCIE_MISC_HARD_ECO_CTRL_HARD_ECO_HARD_SHIFT           0
+#define BCHP_PCIE_MISC_HARD_ECO_CTRL_HARD_ECO_HARD_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PCIE_HARD_DEBUG - PCIE Hard Debug Register
+ ***************************************************************************/
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: reserved0 [31:24] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_reserved0_MASK         0xff000000
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_reserved0_SHIFT        24
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: SERDES_IDDQ [23:23] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK       0x00800000
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT      23
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_DEFAULT    0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: SERDES_RESET [22:22] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_RESET_MASK      0x00400000
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_RESET_SHIFT     22
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_RESET_DEFAULT   0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: SERDES_MDIO_RESET [21:21] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_MDIO_RESET_MASK 0x00200000
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_MDIO_RESET_SHIFT 21
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_MDIO_RESET_DEFAULT 0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: SERDES_TEST_MODE [20:20] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_TEST_MODE_MASK  0x00100000
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_TEST_MODE_SHIFT 20
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_TEST_MODE_DEFAULT 0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: reserved1 [19:19] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_reserved1_MASK         0x00080000
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_reserved1_SHIFT        19
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: REFCLK_OVERRIDE_OUT [18:18] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVERRIDE_OUT_MASK 0x00040000
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVERRIDE_OUT_SHIFT 18
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVERRIDE_OUT_DEFAULT 0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: REFCLK_OVERRIDE_IN [17:17] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVERRIDE_IN_MASK 0x00020000
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVERRIDE_IN_SHIFT 17
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVERRIDE_IN_DEFAULT 0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: REFCLK_OVERRIDE [16:16] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVERRIDE_MASK   0x00010000
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVERRIDE_SHIFT  16
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVERRIDE_DEFAULT 0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: PCIE_TMUX_SEL [15:08] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_PCIE_TMUX_SEL_MASK     0x0000ff00
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_PCIE_TMUX_SEL_SHIFT    8
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_PCIE_TMUX_SEL_DEFAULT  0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: WATCHDOG_PERST_CTRL [07:07] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_WATCHDOG_PERST_CTRL_MASK 0x00000080
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_WATCHDOG_PERST_CTRL_SHIFT 7
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_WATCHDOG_PERST_CTRL_DEFAULT 0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: LOCAL_PERST_CTRL [06:06] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_LOCAL_PERST_CTRL_MASK  0x00000040
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_LOCAL_PERST_CTRL_SHIFT 6
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_LOCAL_PERST_CTRL_DEFAULT 0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: LOCAL_BRIDGE_RESET_CTRL [05:05] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_LOCAL_BRIDGE_RESET_CTRL_MASK 0x00000020
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_LOCAL_BRIDGE_RESET_CTRL_SHIFT 5
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_LOCAL_BRIDGE_RESET_CTRL_DEFAULT 0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: AUXCLK_ENABLE [04:04] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_AUXCLK_ENABLE_MASK     0x00000010
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_AUXCLK_ENABLE_SHIFT    4
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_AUXCLK_ENABLE_DEFAULT  0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: DOWNSTREAM_PERST_DISABLE [03:03] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_DOWNSTREAM_PERST_DISABLE_MASK 0x00000008
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_DOWNSTREAM_PERST_DISABLE_SHIFT 3
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_DOWNSTREAM_PERST_DISABLE_DEFAULT 0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: PCIECORE_ADDR_MODE [02:02] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_PCIECORE_ADDR_MODE_MASK 0x00000004
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_PCIECORE_ADDR_MODE_SHIFT 2
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_PCIECORE_ADDR_MODE_DEFAULT 0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: CLKREQ_DEBUG_ENABLE [01:01] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x00000002
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_SHIFT 1
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_DEFAULT 0x00000000
+
+/* PCIE_MISC_HARD :: PCIE_HARD_DEBUG :: HOTRESET_DISABLE [00:00] */
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_HOTRESET_DISABLE_MASK  0x00000001
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_HOTRESET_DISABLE_SHIFT 0
+#define BCHP_PCIE_MISC_HARD_PCIE_HARD_DEBUG_HOTRESET_DISABLE_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_PCIE_MISC_HARD_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_pcie_misc_perst.h b/include/linux/brcmstb/7435b0/bchp_pcie_misc_perst.h
new file mode 100644
index 0000000..1cc2b36
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_pcie_misc_perst.h
@@ -0,0 +1,88 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:43 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_pcie_misc_perst.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 3:33p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_PCIE_MISC_PERST_H__
+#define BCHP_PCIE_MISC_PERST_H__
+
+/***************************************************************************
+ *PCIE_MISC_PERST - PCI-E Miscellaneous Registers (Fundamental reset)
+ ***************************************************************************/
+#define BCHP_PCIE_MISC_PERST_ECO_CTRL_PERST      0x00414100 /* ECO PCIE Reset Control Register */
+#define BCHP_PCIE_MISC_PERST_CCE_STATUS          0x00414104 /* Config Copy Engine Status */
+
+/***************************************************************************
+ *ECO_CTRL_PERST - ECO PCIE Reset Control Register
+ ***************************************************************************/
+/* PCIE_MISC_PERST :: ECO_CTRL_PERST :: reserved0 [31:16] */
+#define BCHP_PCIE_MISC_PERST_ECO_CTRL_PERST_reserved0_MASK         0xffff0000
+#define BCHP_PCIE_MISC_PERST_ECO_CTRL_PERST_reserved0_SHIFT        16
+
+/* PCIE_MISC_PERST :: ECO_CTRL_PERST :: ECO_PERST_N [15:00] */
+#define BCHP_PCIE_MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_MASK       0x0000ffff
+#define BCHP_PCIE_MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_SHIFT      0
+#define BCHP_PCIE_MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_DEFAULT    0x00000000
+
+/***************************************************************************
+ *CCE_STATUS - Config Copy Engine Status
+ ***************************************************************************/
+/* PCIE_MISC_PERST :: CCE_STATUS :: CCE_DONE [31:31] */
+#define BCHP_PCIE_MISC_PERST_CCE_STATUS_CCE_DONE_MASK              0x80000000
+#define BCHP_PCIE_MISC_PERST_CCE_STATUS_CCE_DONE_SHIFT             31
+
+/* PCIE_MISC_PERST :: CCE_STATUS :: reserved0 [30:03] */
+#define BCHP_PCIE_MISC_PERST_CCE_STATUS_reserved0_MASK             0x7ffffff8
+#define BCHP_PCIE_MISC_PERST_CCE_STATUS_reserved0_SHIFT            3
+
+/* PCIE_MISC_PERST :: CCE_STATUS :: CCE_BAD_GISB_ACCESS [02:02] */
+#define BCHP_PCIE_MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_MASK   0x00000004
+#define BCHP_PCIE_MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_SHIFT  2
+
+/* PCIE_MISC_PERST :: CCE_STATUS :: CCE_BAD_I2C_ACCESS [01:01] */
+#define BCHP_PCIE_MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_MASK    0x00000002
+#define BCHP_PCIE_MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_SHIFT   1
+
+/* PCIE_MISC_PERST :: CCE_STATUS :: CCE_BAD_SECTION_ID [00:00] */
+#define BCHP_PCIE_MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_MASK    0x00000001
+#define BCHP_PCIE_MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_SHIFT   0
+
+#endif /* #ifndef BCHP_PCIE_MISC_PERST_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_pcie_rc_cfg_pcie.h b/include/linux/brcmstb/7435b0/bchp_pcie_rc_cfg_pcie.h
new file mode 100644
index 0000000..867c364
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_pcie_rc_cfg_pcie.h
@@ -0,0 +1,647 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:39 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_pcie_rc_cfg_pcie.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 3:34p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_PCIE_RC_CFG_PCIE_H__
+#define BCHP_PCIE_RC_CFG_PCIE_H__
+
+/***************************************************************************
+ *PCIE_RC_CFG_PCIE
+ ***************************************************************************/
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY    0x004100ac /* pcie_capability */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY  0x004100b0 /* device_capability */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL 0x004100b4 /* device_status_control */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY    0x004100b8 /* link_capability */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL 0x004100bc /* link_status_control */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY    0x004100c0 /* slot_capability */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS 0x004100c4 /* slot_control_status */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL   0x004100c8 /* root_cap_control */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS        0x004100cc /* root_status */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_2 0x004100d0 /* device_capability_2 */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2 0x004100d4 /* device_status_control_2 */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_2  0x004100d8 /* link_capability_2 */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2 0x004100dc /* link_status_control_2 */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_2  0x004100e0 /* slot_capability_2 */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2 0x004100e4 /* slot_status_control_2 */
+
+/***************************************************************************
+ *PCIE_CAPABILITY - pcie_capability
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: PCIE_CAPABILITY :: RESERVED0 [31:30] */
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_RESERVED0_MASK       0xc0000000
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_RESERVED0_SHIFT      30
+
+/* PCIE_RC_CFG_PCIE :: PCIE_CAPABILITY :: MSG_NUM [29:25] */
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_MSG_NUM_MASK         0x3e000000
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_MSG_NUM_SHIFT        25
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_MSG_NUM_DEFAULT      0x00000000
+
+/* PCIE_RC_CFG_PCIE :: PCIE_CAPABILITY :: SLOT_IMPLEMENTED [24:24] */
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_SLOT_IMPLEMENTED_MASK 0x01000000
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_SLOT_IMPLEMENTED_SHIFT 24
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_SLOT_IMPLEMENTED_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: PCIE_CAPABILITY :: TYPE [23:20] */
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_TYPE_MASK            0x00f00000
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_TYPE_SHIFT           20
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_TYPE_DEFAULT         0x00000004
+
+/* PCIE_RC_CFG_PCIE :: PCIE_CAPABILITY :: VER [19:16] */
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_VER_MASK             0x000f0000
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_VER_SHIFT            16
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_VER_DEFAULT          0x00000002
+
+/* PCIE_RC_CFG_PCIE :: PCIE_CAPABILITY :: PCIE_NEXT_CAP_PTR [15:08] */
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_NEXT_CAP_PTR_MASK 0x0000ff00
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_NEXT_CAP_PTR_SHIFT 8
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_NEXT_CAP_PTR_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: PCIE_CAPABILITY :: PCIE_CAP_ID [07:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_CAP_ID_MASK     0x000000ff
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_CAP_ID_SHIFT    0
+#define BCHP_PCIE_RC_CFG_PCIE_PCIE_CAPABILITY_PCIE_CAP_ID_DEFAULT  0x00000010
+
+/***************************************************************************
+ *DEVICE_CAPABILITY - device_capability
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY :: RESERVED3 [31:28] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED3_MASK     0xf0000000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED3_SHIFT    28
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY :: CAPTURED_SLOT_PWR_SCALE [27:26] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_SCALE_MASK 0x0c000000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_SCALE_SHIFT 26
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_SCALE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY :: CAPTURED_SLOT_PWR_VAL [25:18] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_VAL_MASK 0x03fc0000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_VAL_SHIFT 18
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_VAL_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY :: RESERVED2 [17:16] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED2_MASK     0x00030000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED2_SHIFT    16
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY :: ROLE_BASED_ERR_RPT [15:15] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT_MASK 0x00008000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT_SHIFT 15
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY :: RESERVED1 [14:12] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED1_MASK     0x00007000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED1_SHIFT    12
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY :: L1_ACCEPTABLE_LATENCY [11:09] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_MASK 0x00000e00
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_SHIFT 9
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY :: L0S_ACCEPTABLE_LATENCY [08:06] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY_MASK 0x000001c0
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY_SHIFT 6
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY :: EXTENDED_TAG_SUPPORT [05:05] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT_MASK 0x00000020
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT_SHIFT 5
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY :: RESERVED0 [04:03] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED0_MASK     0x00000018
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_RESERVED0_SHIFT    3
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY :: MAX_PL_SIZE_SUPPORTED [02:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_MASK 0x00000007
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_SHIFT 0
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DEVICE_STATUS_CONTROL - device_status_control
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: RESERVED2 [31:22] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED2_MASK 0xffc00000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED2_SHIFT 22
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: NP_TRANSACTION_PEND [21:21] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NP_TRANSACTION_PEND_MASK 0x00200000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NP_TRANSACTION_PEND_SHIFT 21
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NP_TRANSACTION_PEND_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: AUX_PWR_DET [20:20] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_DET_MASK 0x00100000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_DET_SHIFT 20
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_DET_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: UNSUP_REQ_DET [19:19] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_UNSUP_REQ_DET_MASK 0x00080000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_UNSUP_REQ_DET_SHIFT 19
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_UNSUP_REQ_DET_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: FATAL_ERR_DET [18:18] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_DET_MASK 0x00040000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_DET_SHIFT 18
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_DET_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: NON_FATAL_ERR_DET [17:17] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NON_FATAL_ERR_DET_MASK 0x00020000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NON_FATAL_ERR_DET_SHIFT 17
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NON_FATAL_ERR_DET_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: CORR_ERR_DET [16:16] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_DET_MASK 0x00010000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_DET_SHIFT 16
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_DET_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: RESERVED1 [15:15] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED1_MASK 0x00008000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED1_SHIFT 15
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: MAX_READ_REQ_SIZ [14:12] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_READ_REQ_SIZ_MASK 0x00007000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_READ_REQ_SIZ_SHIFT 12
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_READ_REQ_SIZ_DEFAULT 0x00000002
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: NO_SNOOP_ENABLE [11:11] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NO_SNOOP_ENABLE_MASK 0x00000800
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NO_SNOOP_ENABLE_SHIFT 11
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NO_SNOOP_ENABLE_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: AUX_PWR_PM_ENA [10:10] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_PM_ENA_MASK 0x00000400
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_PM_ENA_SHIFT 10
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_AUX_PWR_PM_ENA_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: RESERVED0 [09:09] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED0_MASK 0x00000200
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RESERVED0_SHIFT 9
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: EXTENDED_TAG_EN [08:08] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_EXTENDED_TAG_EN_MASK 0x00000100
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_EXTENDED_TAG_EN_SHIFT 8
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_EXTENDED_TAG_EN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: MAX_PAYLOAD_SIZE [07:05] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_MASK 0x000000e0
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_SHIFT 5
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: RELAX_ORDERING_ENABLE [04:04] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RELAX_ORDERING_ENABLE_MASK 0x00000010
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RELAX_ORDERING_ENABLE_SHIFT 4
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_RELAX_ORDERING_ENABLE_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: U_REQ_REPORT_EN [03:03] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_U_REQ_REPORT_EN_MASK 0x00000008
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_U_REQ_REPORT_EN_SHIFT 3
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_U_REQ_REPORT_EN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: FATAL_ERR_REPORT_EN [02:02] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_REPORT_EN_MASK 0x00000004
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_REPORT_EN_SHIFT 2
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_FATAL_ERR_REPORT_EN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: NFATAL_ERR_REPORT_EN [01:01] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NFATAL_ERR_REPORT_EN_MASK 0x00000002
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NFATAL_ERR_REPORT_EN_SHIFT 1
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_NFATAL_ERR_REPORT_EN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL :: CORR_ERR_REPORT_EN [00:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_REPORT_EN_MASK 0x00000001
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_REPORT_EN_SHIFT 0
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_CORR_ERR_REPORT_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *LINK_CAPABILITY - link_capability
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: PORT_NUMBER [31:24] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_PORT_NUMBER_MASK     0xff000000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_PORT_NUMBER_SHIFT    24
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_PORT_NUMBER_DEFAULT  0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: RESERVED0 [23:23] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_RESERVED0_MASK       0x00800000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_RESERVED0_SHIFT      23
+
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: ASPM_OPTIONALITY [22:22] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_OPTIONALITY_MASK 0x00400000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_OPTIONALITY_SHIFT 22
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_OPTIONALITY_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: LINK_BW_NOTIFY [21:21] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_LINK_BW_NOTIFY_MASK  0x00200000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_LINK_BW_NOTIFY_SHIFT 21
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_LINK_BW_NOTIFY_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: DL_ACTIVE_REP [20:20] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_DL_ACTIVE_REP_MASK   0x00100000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_DL_ACTIVE_REP_SHIFT  20
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_DL_ACTIVE_REP_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: SUR_DWN_ERR_REP [19:19] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_SUR_DWN_ERR_REP_MASK 0x00080000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_SUR_DWN_ERR_REP_SHIFT 19
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_SUR_DWN_ERR_REP_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: CLK_PWR_MGMT [18:18] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_CLK_PWR_MGMT_MASK    0x00040000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_CLK_PWR_MGMT_SHIFT   18
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_CLK_PWR_MGMT_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: L1_EXIT_LAT [17:15] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_L1_EXIT_LAT_MASK     0x00038000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_L1_EXIT_LAT_SHIFT    15
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_L1_EXIT_LAT_DEFAULT  0x00000002
+
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: L0S_EXIT_LAT [14:12] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_L0S_EXIT_LAT_MASK    0x00007000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_L0S_EXIT_LAT_SHIFT   12
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_L0S_EXIT_LAT_DEFAULT 0x00000005
+
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: ASPM_SUPT [11:10] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_SUPT_MASK       0x00000c00
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_SUPT_SHIFT      10
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_ASPM_SUPT_DEFAULT    0x00000003
+
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: MAX_LINK_WIDTH [09:04] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_WIDTH_MASK  0x000003f0
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_WIDTH_SHIFT 4
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_WIDTH_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY :: MAX_LINK_SPEED [03:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_SPEED_MASK  0x0000000f
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_SPEED_SHIFT 0
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_SPEED_DEFAULT 0x00000002
+
+/***************************************************************************
+ *LINK_STATUS_CONTROL - link_status_control
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RESERVED3 [31:30] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED3_MASK   0xc0000000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED3_SHIFT  30
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: DL_ACTIVE [29:29] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_DL_ACTIVE_MASK   0x20000000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_DL_ACTIVE_SHIFT  29
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_DL_ACTIVE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: SLOT_CLK_CONFIG [28:28] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_SLOT_CLK_CONFIG_MASK 0x10000000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_SLOT_CLK_CONFIG_SHIFT 28
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_SLOT_CLK_CONFIG_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_TRAINING [27:27] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_TRAINING_MASK 0x08000000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_TRAINING_SHIFT 27
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_TRAINING_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RESERVED2 [26:26] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED2_MASK   0x04000000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED2_SHIFT  26
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: NEG_LINK_WIDTH [25:20] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_MASK 0x03f00000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_SHIFT 20
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: NEG_LINK_SPEED [19:16] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_SPEED_MASK 0x000f0000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_SPEED_SHIFT 16
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_SPEED_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RESERVED1 [15:12] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED1_MASK   0x0000f000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED1_SHIFT  12
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_BW_INT_EN [11:11] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_INT_EN_MASK 0x00000800
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_INT_EN_SHIFT 11
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_INT_EN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_BW_MGMT_INT_EN [10:10] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_MGMT_INT_EN_MASK 0x00000400
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_MGMT_INT_EN_SHIFT 10
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_BW_MGMT_INT_EN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: HW_AUTO_WIDTH_DIS [09:09] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_HW_AUTO_WIDTH_DIS_MASK 0x00000200
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_HW_AUTO_WIDTH_DIS_SHIFT 9
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_HW_AUTO_WIDTH_DIS_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: EN_CLK_PW_MGMT [08:08] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_EN_CLK_PW_MGMT_MASK 0x00000100
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_EN_CLK_PW_MGMT_SHIFT 8
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_EN_CLK_PW_MGMT_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_CR_EXT_SYNC [07:07] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_EXT_SYNC_MASK 0x00000080
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_EXT_SYNC_SHIFT 7
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_EXT_SYNC_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: LINK_CR_COMMON_CLK [06:06] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_COMMON_CLK_MASK 0x00000040
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_COMMON_CLK_SHIFT 6
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_LINK_CR_COMMON_CLK_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: CFG_PSM_RETRAIN_LINK [05:05] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_RETRAIN_LINK_MASK 0x00000020
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_RETRAIN_LINK_SHIFT 5
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_RETRAIN_LINK_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: CFG_PSM_LINK_DISABLE [04:04] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_LINK_DISABLE_MASK 0x00000010
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_LINK_DISABLE_SHIFT 4
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_CFG_PSM_LINK_DISABLE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RCB [03:03] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_RCB_MASK         0x00000008
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_RCB_SHIFT        3
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_RCB_DEFAULT      0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: RESERVED0 [02:02] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED0_MASK   0x00000004
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_RESERVED0_SHIFT  2
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL :: ASPM_CTRL [01:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_ASPM_CTRL_MASK   0x00000003
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_ASPM_CTRL_SHIFT  0
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_ASPM_CTRL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SLOT_CAPABILITY - slot_capability
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: SLOT_CAPABILITY :: PHYSICAL_SLOT_NUMBER [31:19] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_PHYSICAL_SLOT_NUMBER_MASK 0xfff80000
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_PHYSICAL_SLOT_NUMBER_SHIFT 19
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_PHYSICAL_SLOT_NUMBER_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: SLOT_CAPABILITY :: UNUSED [18:17] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_MASK          0x00060000
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_SHIFT         17
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_DEFAULT       0x00000000
+
+/* PCIE_RC_CFG_PCIE :: SLOT_CAPABILITY :: SLOT_POWER_LIMIT_SCALE [16:15] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_SCALE_MASK 0x00018000
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_SCALE_SHIFT 15
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_SCALE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: SLOT_CAPABILITY :: SLOT_POWER_LIMIT_VALUE [14:07] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_VALUE_MASK 0x00007f80
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_VALUE_SHIFT 7
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_SLOT_POWER_LIMIT_VALUE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: SLOT_CAPABILITY :: UNUSED_2 [06:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_2_MASK        0x0000007f
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_2_SHIFT       0
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_UNUSED_2_DEFAULT     0x00000000
+
+/***************************************************************************
+ *SLOT_CONTROL_STATUS - slot_control_status
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: SLOT_CONTROL_STATUS :: SLOT_STATUS [31:23] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_STATUS_MASK 0xff800000
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_STATUS_SHIFT 23
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_STATUS_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: SLOT_CONTROL_STATUS :: PRESENCE_DETECT [22:22] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_PRESENCE_DETECT_MASK 0x00400000
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_PRESENCE_DETECT_SHIFT 22
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_PRESENCE_DETECT_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: SLOT_CONTROL_STATUS :: UNUSED_1 [21:16] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_UNUSED_1_MASK    0x003f0000
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_UNUSED_1_SHIFT   16
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_UNUSED_1_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: SLOT_CONTROL_STATUS :: SLOT_CONTROL [15:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_CONTROL_MASK 0x0000ffff
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_CONTROL_SHIFT 0
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CONTROL_STATUS_SLOT_CONTROL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ROOT_CAP_CONTROL - root_cap_control
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RESERVED1 [31:17] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RESERVED1_MASK      0xfffe0000
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RESERVED1_SHIFT     17
+
+/* PCIE_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_CRS_VISIBILITY [16:16] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_VISIBILITY_MASK 0x00010000
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_VISIBILITY_SHIFT 16
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_VISIBILITY_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RESERVED0 [15:05] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RESERVED0_MASK      0x0000ffe0
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RESERVED0_SHIFT     5
+
+/* PCIE_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_CRS_EN [04:04] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_MASK      0x00000010
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_SHIFT     4
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_DEFAULT   0x00000000
+
+/* PCIE_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_PME_INT_EN [03:03] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_PME_INT_EN_MASK  0x00000008
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_PME_INT_EN_SHIFT 3
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_PME_INT_EN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_FATAL_SERR_EN [02:02] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_FATAL_SERR_EN_MASK 0x00000004
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_FATAL_SERR_EN_SHIFT 2
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_FATAL_SERR_EN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_NONFATAL_SERR_EN [01:01] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_NONFATAL_SERR_EN_MASK 0x00000002
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_NONFATAL_SERR_EN_SHIFT 1
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_NONFATAL_SERR_EN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: ROOT_CAP_CONTROL :: RC_CORR_SERR_EN [00:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CORR_SERR_EN_MASK 0x00000001
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CORR_SERR_EN_SHIFT 0
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CORR_SERR_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ROOT_STATUS - root_status
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: ROOT_STATUS :: RESERVED0 [31:18] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS_RESERVED0_MASK           0xfffc0000
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS_RESERVED0_SHIFT          18
+
+/* PCIE_RC_CFG_PCIE :: ROOT_STATUS :: RC_PME_PENDING [17:17] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS_RC_PME_PENDING_MASK      0x00020000
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS_RC_PME_PENDING_SHIFT     17
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS_RC_PME_PENDING_DEFAULT   0x00000000
+
+/* PCIE_RC_CFG_PCIE :: ROOT_STATUS :: RC_PME_STATUS [16:16] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS_RC_PME_STATUS_MASK       0x00010000
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS_RC_PME_STATUS_SHIFT      16
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS_RC_PME_STATUS_DEFAULT    0x00000000
+
+/* PCIE_RC_CFG_PCIE :: ROOT_STATUS :: RC_PME_REQ_ID [15:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS_RC_PME_REQ_ID_MASK       0x0000ffff
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS_RC_PME_REQ_ID_SHIFT      0
+#define BCHP_PCIE_RC_CFG_PCIE_ROOT_STATUS_RC_PME_REQ_ID_DEFAULT    0x00000000
+
+/***************************************************************************
+ *DEVICE_CAPABILITY_2 - device_capability_2
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY_2 :: RESERVED0 [31:05] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_2_RESERVED0_MASK   0xffffffe0
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_2_RESERVED0_SHIFT  5
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY_2 :: CMPL_TIMEOUT_DISABL_SUPPORTED [04:04] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_DISABL_SUPPORTED_MASK 0x00000010
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_DISABL_SUPPORTED_SHIFT 4
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_DISABL_SUPPORTED_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_CAPABILITY_2 :: CMPL_TIMEOUT_RANGES_SUPPORTED [03:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_RANGES_SUPPORTED_MASK 0x0000000f
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_RANGES_SUPPORTED_SHIFT 0
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_RANGES_SUPPORTED_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *DEVICE_STATUS_CONTROL_2 - device_status_control_2
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL_2 :: DEVICE_STATUS_2 [31:16] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_DEVICE_STATUS_2_MASK 0xffff0000
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_DEVICE_STATUS_2_SHIFT 16
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_DEVICE_STATUS_2_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL_2 :: RESERVED0 [15:05] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_RESERVED0_MASK 0x0000ffe0
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_RESERVED0_SHIFT 5
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL_2 :: CMPL_TIMEOUT_DISABLE [04:04] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_DISABLE_MASK 0x00000010
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_DISABLE_SHIFT 4
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_DISABLE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: DEVICE_STATUS_CONTROL_2 :: CMPL_TIMEOUT_VALUE [03:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_VALUE_MASK 0x0000000f
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_VALUE_SHIFT 0
+#define BCHP_PCIE_RC_CFG_PCIE_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_VALUE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *LINK_CAPABILITY_2 - link_capability_2
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: LINK_CAPABILITY_2 :: LINK_CAPABILITY_2 [31:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_2_LINK_CAPABILITY_2_MASK 0xffffffff
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_2_LINK_CAPABILITY_2_SHIFT 0
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_CAPABILITY_2_LINK_CAPABILITY_2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *LINK_STATUS_CONTROL_2 - link_status_control_2
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: LINK_STATUS_2 [31:17] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_LINK_STATUS_2_MASK 0xfffe0000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_LINK_STATUS_2_SHIFT 17
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_LINK_STATUS_2_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CURR_DEEMPH_LEVEL [16:16] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CURR_DEEMPH_LEVEL_MASK 0x00010000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CURR_DEEMPH_LEVEL_SHIFT 16
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CURR_DEEMPH_LEVEL_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: RESERVED0 [15:13] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_RESERVED0_MASK 0x0000e000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_RESERVED0_SHIFT 13
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CFG_COMPLIANCE_DEEMPH [12:12] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_DEEMPH_MASK 0x00001000
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_DEEMPH_SHIFT 12
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_DEEMPH_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CFG_COMPLIANCE_SOS [11:11] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_SOS_MASK 0x00000800
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_SOS_SHIFT 11
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_SOS_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CFG_ENTER_MOD_COMPLIANCE [10:10] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_ENTER_MOD_COMPLIANCE_MASK 0x00000400
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_ENTER_MOD_COMPLIANCE_SHIFT 10
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_ENTER_MOD_COMPLIANCE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: CFG_TX_MARGIN [09:07] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_TX_MARGIN_MASK 0x00000380
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_TX_MARGIN_SHIFT 7
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_CFG_TX_MARGIN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: SEL_DEEMPHASIS [06:06] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_SEL_DEEMPHASIS_MASK 0x00000040
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_SEL_DEEMPHASIS_SHIFT 6
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_SEL_DEEMPHASIS_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: HW_AUTO_SPEED_DISABLE [05:05] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_HW_AUTO_SPEED_DISABLE_MASK 0x00000020
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_HW_AUTO_SPEED_DISABLE_SHIFT 5
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_HW_AUTO_SPEED_DISABLE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: ENTER_COMPLIANCE [04:04] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_ENTER_COMPLIANCE_MASK 0x00000010
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_ENTER_COMPLIANCE_SHIFT 4
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_ENTER_COMPLIANCE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: LINK_STATUS_CONTROL_2 :: TARGET_LINK_SPEED [03:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_MASK 0x0000000f
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_SHIFT 0
+#define BCHP_PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SLOT_CAPABILITY_2 - slot_capability_2
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: SLOT_CAPABILITY_2 :: SLOT_CAPABILITY_2 [31:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_2_SLOT_CAPABILITY_2_MASK 0xffffffff
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_2_SLOT_CAPABILITY_2_SHIFT 0
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_CAPABILITY_2_SLOT_CAPABILITY_2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SLOT_STATUS_CONTROL_2 - slot_status_control_2
+ ***************************************************************************/
+/* PCIE_RC_CFG_PCIE :: SLOT_STATUS_CONTROL_2 :: SLOT_STATUS_2 [31:16] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_STATUS_2_MASK 0xffff0000
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_STATUS_2_SHIFT 16
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_STATUS_2_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_PCIE :: SLOT_STATUS_CONTROL_2 :: SLOT_CONTROL_2 [15:00] */
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_CONTROL_2_MASK 0x0000ffff
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_CONTROL_2_SHIFT 0
+#define BCHP_PCIE_RC_CFG_PCIE_SLOT_STATUS_CONTROL_2_SLOT_CONTROL_2_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_PCIE_RC_CFG_PCIE_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_pcie_rc_cfg_type1.h b/include/linux/brcmstb/7435b0/bchp_pcie_rc_cfg_type1.h
new file mode 100644
index 0000000..dfc80e9
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_pcie_rc_cfg_type1.h
@@ -0,0 +1,529 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:35 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_pcie_rc_cfg_type1.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 3:36p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_PCIE_RC_CFG_TYPE1_H__
+#define BCHP_PCIE_RC_CFG_TYPE1_H__
+
+/***************************************************************************
+ *PCIE_RC_CFG_TYPE1
+ ***************************************************************************/
+#define BCHP_PCIE_RC_CFG_TYPE1_DEVICE_VENDOR_ID  0x00410000 /* device_vendor_id */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND    0x00410004 /* status_command */
+#define BCHP_PCIE_RC_CFG_TYPE1_REV_ID_CLASS_CODE 0x00410008 /* rev_id_class_code */
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE 0x0041000c /* headertype_lat_cachelinesize */
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1             0x00410010 /* bar_1 */
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_2             0x00410014 /* bar_2 */
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO    0x00410018 /* pri_sec_bus_no */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT 0x0041001c /* sec_status_io_base_limit */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT 0x00410020 /* rc_mem_base_limit */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT 0x00410024 /* rc_pref_base_limit */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_HI   0x00410028 /* rc_pref_base_hi */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_LIM_HI    0x0041002c /* rc_pref_lim_hi */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_IO_BASE_LIMIT  0x00410030 /* rc_io_base_limit */
+#define BCHP_PCIE_RC_CFG_TYPE1_CAP_POINTER       0x00410034 /* cap_pointer */
+#define BCHP_PCIE_RC_CFG_TYPE1_EXP_ROM_BAR       0x00410038 /* exp_rom_bar */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL    0x0041003c /* bridge_control */
+
+/***************************************************************************
+ *DEVICE_VENDOR_ID - device_vendor_id
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: DEVICE_VENDOR_ID :: DEVICE_ID [31:16] */
+#define BCHP_PCIE_RC_CFG_TYPE1_DEVICE_VENDOR_ID_DEVICE_ID_MASK     0xffff0000
+#define BCHP_PCIE_RC_CFG_TYPE1_DEVICE_VENDOR_ID_DEVICE_ID_SHIFT    16
+
+/* PCIE_RC_CFG_TYPE1 :: DEVICE_VENDOR_ID :: VENDOR_ID [15:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_DEVICE_VENDOR_ID_VENDOR_ID_MASK     0x0000ffff
+#define BCHP_PCIE_RC_CFG_TYPE1_DEVICE_VENDOR_ID_VENDOR_ID_SHIFT    0
+#define BCHP_PCIE_RC_CFG_TYPE1_DEVICE_VENDOR_ID_VENDOR_ID_DEFAULT  0x000014e4
+
+/***************************************************************************
+ *STATUS_COMMAND - status_command
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: PAR_ERR [31:31] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_PAR_ERR_MASK         0x80000000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_PAR_ERR_SHIFT        31
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_PAR_ERR_DEFAULT      0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: SIG_SERR [30:30] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SIG_SERR_MASK        0x40000000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SIG_SERR_SHIFT       30
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SIG_SERR_DEFAULT     0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: RCV_MSTR_ABT [29:29] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RCV_MSTR_ABT_MASK    0x20000000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RCV_MSTR_ABT_SHIFT   29
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RCV_MSTR_ABT_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: RCV_TGT_ABT [28:28] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RCV_TGT_ABT_MASK     0x10000000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RCV_TGT_ABT_SHIFT    28
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RCV_TGT_ABT_DEFAULT  0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: SIG_TGT_ABT [27:27] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SIG_TGT_ABT_MASK     0x08000000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SIG_TGT_ABT_SHIFT    27
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SIG_TGT_ABT_DEFAULT  0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: DEVSEL_TIMING [26:25] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_DEVSEL_TIMING_MASK   0x06000000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_DEVSEL_TIMING_SHIFT  25
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_DEVSEL_TIMING_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: MSTR_PERR [24:24] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_MSTR_PERR_MASK       0x01000000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_MSTR_PERR_SHIFT      24
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_MSTR_PERR_DEFAULT    0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: FAST_B2B_CAP [23:23] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_CAP_MASK    0x00800000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_CAP_SHIFT   23
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_CAP_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: RESERVED1 [22:22] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED1_MASK       0x00400000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED1_SHIFT      22
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED1_DEFAULT    0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: CAP_66MHZ [21:21] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_CAP_66MHZ_MASK       0x00200000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_CAP_66MHZ_SHIFT      21
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_CAP_66MHZ_DEFAULT    0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: CAP_LIST [20:20] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_CAP_LIST_MASK        0x00100000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_CAP_LIST_SHIFT       20
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_CAP_LIST_DEFAULT     0x00000001
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: INT_STATUS [19:19] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_INT_STATUS_MASK      0x00080000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_INT_STATUS_SHIFT     19
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_INT_STATUS_DEFAULT   0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: RESERVED2 [18:16] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED2_MASK       0x00070000
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED2_SHIFT      16
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED2_DEFAULT    0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: RESERVED [15:11] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED_MASK        0x0000f800
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED_SHIFT       11
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_RESERVED_DEFAULT     0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: INT_DISABLE [10:10] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_INT_DISABLE_MASK     0x00000400
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_INT_DISABLE_SHIFT    10
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_INT_DISABLE_DEFAULT  0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: FAST_B2B [09:09] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_MASK        0x00000200
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_SHIFT       9
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_FAST_B2B_DEFAULT     0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: SERR_ENA [08:08] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SERR_ENA_MASK        0x00000100
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SERR_ENA_SHIFT       8
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SERR_ENA_DEFAULT     0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: STEPPING [07:07] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_STEPPING_MASK        0x00000080
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_STEPPING_SHIFT       7
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_STEPPING_DEFAULT     0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: PERR_ENA [06:06] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_PERR_ENA_MASK        0x00000040
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_PERR_ENA_SHIFT       6
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_PERR_ENA_DEFAULT     0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: VGA_SNOOP [05:05] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_VGA_SNOOP_MASK       0x00000020
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_VGA_SNOOP_SHIFT      5
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_VGA_SNOOP_DEFAULT    0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: MWI_CYCLES [04:04] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_MWI_CYCLES_MASK      0x00000010
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_MWI_CYCLES_SHIFT     4
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_MWI_CYCLES_DEFAULT   0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: SPECIAL_CYCLES [03:03] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SPECIAL_CYCLES_MASK  0x00000008
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SPECIAL_CYCLES_SHIFT 3
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_SPECIAL_CYCLES_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: BUS_MASTER [02:02] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_BUS_MASTER_MASK      0x00000004
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_BUS_MASTER_SHIFT     2
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_BUS_MASTER_DEFAULT   0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: MEM_SPACE [01:01] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_MEM_SPACE_MASK       0x00000002
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_MEM_SPACE_SHIFT      1
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_MEM_SPACE_DEFAULT    0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: STATUS_COMMAND :: IO_SPACE [00:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_IO_SPACE_MASK        0x00000001
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_IO_SPACE_SHIFT       0
+#define BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND_IO_SPACE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *REV_ID_CLASS_CODE - rev_id_class_code
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: REV_ID_CLASS_CODE :: CLASS_CODE [31:08] */
+#define BCHP_PCIE_RC_CFG_TYPE1_REV_ID_CLASS_CODE_CLASS_CODE_MASK   0xffffff00
+#define BCHP_PCIE_RC_CFG_TYPE1_REV_ID_CLASS_CODE_CLASS_CODE_SHIFT  8
+#define BCHP_PCIE_RC_CFG_TYPE1_REV_ID_CLASS_CODE_CLASS_CODE_DEFAULT 0x00020000
+
+/* PCIE_RC_CFG_TYPE1 :: REV_ID_CLASS_CODE :: REV_ID [07:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_REV_ID_CLASS_CODE_REV_ID_MASK       0x000000ff
+#define BCHP_PCIE_RC_CFG_TYPE1_REV_ID_CLASS_CODE_REV_ID_SHIFT      0
+
+/***************************************************************************
+ *HEADERTYPE_LAT_CACHELINESIZE - headertype_lat_cachelinesize
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: HEADERTYPE_LAT_CACHELINESIZE :: BIST [31:24] */
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_BIST_MASK 0xff000000
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_BIST_SHIFT 24
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_BIST_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: HEADERTYPE_LAT_CACHELINESIZE :: HEADER_TYPE [23:16] */
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_HEADER_TYPE_MASK 0x00ff0000
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_HEADER_TYPE_SHIFT 16
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_HEADER_TYPE_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_TYPE1 :: HEADERTYPE_LAT_CACHELINESIZE :: LATENCY_TIMER [15:08] */
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_LATENCY_TIMER_MASK 0x0000ff00
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_LATENCY_TIMER_SHIFT 8
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_LATENCY_TIMER_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: HEADERTYPE_LAT_CACHELINESIZE :: CACHE_LINE_SIZE [07:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_CACHE_LINE_SIZE_MASK 0x000000ff
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_CACHE_LINE_SIZE_SHIFT 0
+#define BCHP_PCIE_RC_CFG_TYPE1_HEADERTYPE_LAT_CACHELINESIZE_CACHE_LINE_SIZE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BAR_1 - bar_1
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: BAR_1 :: ADDRESS [31:04] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_ADDRESS_MASK                  0xfffffff0
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_ADDRESS_SHIFT                 4
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_ADDRESS_DEFAULT               0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: BAR_1 :: PREFETCH [03:03] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_PREFETCH_MASK                 0x00000008
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_PREFETCH_SHIFT                3
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_PREFETCH_DEFAULT              0x00000001
+
+/* PCIE_RC_CFG_TYPE1 :: BAR_1 :: SPACE_TYPE [02:01] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_SPACE_TYPE_MASK               0x00000006
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_SPACE_TYPE_SHIFT              1
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_SPACE_TYPE_DEFAULT            0x00000002
+
+/* PCIE_RC_CFG_TYPE1 :: BAR_1 :: MEM_SPACE [00:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_MEM_SPACE_MASK                0x00000001
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_MEM_SPACE_SHIFT               0
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_1_MEM_SPACE_DEFAULT             0x00000000
+
+/***************************************************************************
+ *BAR_2 - bar_2
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: BAR_2 :: ADDR [31:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_2_ADDR_MASK                     0xffffffff
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_2_ADDR_SHIFT                    0
+#define BCHP_PCIE_RC_CFG_TYPE1_BAR_2_ADDR_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PRI_SEC_BUS_NO - pri_sec_bus_no
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: PRI_SEC_BUS_NO :: SEC_LATENCY_TIMER [31:24] */
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_LATENCY_TIMER_MASK 0xff000000
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_LATENCY_TIMER_SHIFT 24
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_LATENCY_TIMER_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: PRI_SEC_BUS_NO :: SUB_BUS_NO [23:16] */
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_MASK      0x00ff0000
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_SHIFT     16
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_DEFAULT   0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: PRI_SEC_BUS_NO :: SEC_BUS_NO [15:08] */
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_MASK      0x0000ff00
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_SHIFT     8
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_DEFAULT   0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: PRI_SEC_BUS_NO :: PRI_BUS_NO [07:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_MASK      0x000000ff
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_SHIFT     0
+#define BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_DEFAULT   0x00000000
+
+/***************************************************************************
+ *SEC_STATUS_IO_BASE_LIMIT - sec_status_io_base_limit
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_DETECTED_PARITY_ERROR [31:31] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_DETECTED_PARITY_ERROR_MASK 0x80000000
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_DETECTED_PARITY_ERROR_SHIFT 31
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_DETECTED_PARITY_ERROR_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_RECEIVED_SYSTEM_ERROR [30:30] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_SYSTEM_ERROR_MASK 0x40000000
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_SYSTEM_ERROR_SHIFT 30
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_SYSTEM_ERROR_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_RECEIVED_MASTER_ABORT [29:29] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_MASTER_ABORT_MASK 0x20000000
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_MASTER_ABORT_SHIFT 29
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_MASTER_ABORT_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_RECEIVED_TARGET_ABORT [28:28] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_TARGET_ABORT_MASK 0x10000000
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_TARGET_ABORT_SHIFT 28
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_RECEIVED_TARGET_ABORT_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_SIGNALED_TARGET_ABORT [27:27] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_SIGNALED_TARGET_ABORT_MASK 0x08000000
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_SIGNALED_TARGET_ABORT_SHIFT 27
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_SIGNALED_TARGET_ABORT_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: DEVICE_TIMING [26:25] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_DEVICE_TIMING_MASK 0x06000000
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_DEVICE_TIMING_SHIFT 25
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_DEVICE_TIMING_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: SEC_MASTER_DATA_PARITY_ERROR [24:24] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_MASTER_DATA_PARITY_ERROR_MASK 0x01000000
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_MASTER_DATA_PARITY_ERROR_SHIFT 24
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_SEC_MASTER_DATA_PARITY_ERROR_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: FAST_B2B [23:23] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_FAST_B2B_MASK 0x00800000
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_FAST_B2B_SHIFT 23
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_FAST_B2B_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: RESERVED3 [22:22] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED3_MASK 0x00400000
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED3_SHIFT 22
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED3_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: CAP_66_MHZ [21:21] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_CAP_66_MHZ_MASK 0x00200000
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_CAP_66_MHZ_SHIFT 21
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_CAP_66_MHZ_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: RESERVED4 [20:16] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED4_MASK 0x001f0000
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED4_SHIFT 16
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_RESERVED4_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: IO_LIMIT [15:08] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_LIMIT_MASK 0x0000ff00
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_LIMIT_SHIFT 8
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_LIMIT_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: SEC_STATUS_IO_BASE_LIMIT :: IO_BASE [07:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_BASE_MASK 0x000000ff
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_BASE_SHIFT 0
+#define BCHP_PCIE_RC_CFG_TYPE1_SEC_STATUS_IO_BASE_LIMIT_IO_BASE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RC_MEM_BASE_LIMIT - rc_mem_base_limit
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: RC_MEM_BASE_LIMIT :: RC_MEM_LIMIT [31:20] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_MASK 0xfff00000
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_SHIFT 20
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: RC_MEM_BASE_LIMIT :: RC_MEM_LIMIT_3TO0 [19:16] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_3TO0_MASK 0x000f0000
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_3TO0_SHIFT 16
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_LIMIT_3TO0_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: RC_MEM_BASE_LIMIT :: RC_MEM_BASE [15:04] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_MASK  0x0000fff0
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_SHIFT 4
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: RC_MEM_BASE_LIMIT :: RC_MEM_BASE_3TO0 [03:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_3TO0_MASK 0x0000000f
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_3TO0_SHIFT 0
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT_RC_MEM_BASE_3TO0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RC_PREF_BASE_LIMIT - rc_pref_base_limit
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: RC_PREF_BASE_LIMIT :: RC_PREF_LIM [31:20] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIM_MASK 0xfff00000
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIM_SHIFT 20
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIM_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: RC_PREF_BASE_LIMIT :: RC_PREF_LIMIT_3TO0 [19:16] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIMIT_3TO0_MASK 0x000f0000
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIMIT_3TO0_SHIFT 16
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_LIMIT_3TO0_DEFAULT 0x00000001
+
+/* PCIE_RC_CFG_TYPE1 :: RC_PREF_BASE_LIMIT :: RC_PREF_BASE [15:04] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_MASK 0x0000fff0
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_SHIFT 4
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: RC_PREF_BASE_LIMIT :: RC_PREF_BASE_3TO0 [03:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_3TO0_MASK 0x0000000f
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_3TO0_SHIFT 0
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT_RC_PREF_BASE_3TO0_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RC_PREF_BASE_HI - rc_pref_base_hi
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: RC_PREF_BASE_HI :: RC_PREF_BASE_HI [31:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_HI_RC_PREF_BASE_HI_MASK 0xffffffff
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_HI_RC_PREF_BASE_HI_SHIFT 0
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_HI_RC_PREF_BASE_HI_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RC_PREF_LIM_HI - rc_pref_lim_hi
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: RC_PREF_LIM_HI :: RC_PREF_BASE_HI [31:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_LIM_HI_RC_PREF_BASE_HI_MASK 0xffffffff
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_LIM_HI_RC_PREF_BASE_HI_SHIFT 0
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_LIM_HI_RC_PREF_BASE_HI_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RC_IO_BASE_LIMIT - rc_io_base_limit
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: RC_IO_BASE_LIMIT :: RC_IO_LIM_HI [31:16] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_LIM_HI_MASK  0xffff0000
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_LIM_HI_SHIFT 16
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_LIM_HI_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: RC_IO_BASE_LIMIT :: RC_IO_BASE_HI [15:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_BASE_HI_MASK 0x0000ffff
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_BASE_HI_SHIFT 0
+#define BCHP_PCIE_RC_CFG_TYPE1_RC_IO_BASE_LIMIT_RC_IO_BASE_HI_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CAP_POINTER - cap_pointer
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: CAP_POINTER :: RESERVED0 [31:08] */
+#define BCHP_PCIE_RC_CFG_TYPE1_CAP_POINTER_RESERVED0_MASK          0xffffff00
+#define BCHP_PCIE_RC_CFG_TYPE1_CAP_POINTER_RESERVED0_SHIFT         8
+
+/* PCIE_RC_CFG_TYPE1 :: CAP_POINTER :: CAP_POINTER [07:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_CAP_POINTER_CAP_POINTER_MASK        0x000000ff
+#define BCHP_PCIE_RC_CFG_TYPE1_CAP_POINTER_CAP_POINTER_SHIFT       0
+#define BCHP_PCIE_RC_CFG_TYPE1_CAP_POINTER_CAP_POINTER_DEFAULT     0x00000048
+
+/***************************************************************************
+ *EXP_ROM_BAR - exp_rom_bar
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: EXP_ROM_BAR :: RESERVED0 [31:08] */
+#define BCHP_PCIE_RC_CFG_TYPE1_EXP_ROM_BAR_RESERVED0_MASK          0xffffff00
+#define BCHP_PCIE_RC_CFG_TYPE1_EXP_ROM_BAR_RESERVED0_SHIFT         8
+
+/* PCIE_RC_CFG_TYPE1 :: EXP_ROM_BAR :: EXP_ROM_BAR [07:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_EXP_ROM_BAR_EXP_ROM_BAR_MASK        0x000000ff
+#define BCHP_PCIE_RC_CFG_TYPE1_EXP_ROM_BAR_EXP_ROM_BAR_SHIFT       0
+#define BCHP_PCIE_RC_CFG_TYPE1_EXP_ROM_BAR_EXP_ROM_BAR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *BRIDGE_CONTROL - bridge_control
+ ***************************************************************************/
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: RESERVED1 [31:28] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_RESERVED1_MASK       0xf0000000
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_RESERVED1_SHIFT      28
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: DISCARD_TIMER_SERR_EN [27:27] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_SERR_EN_MASK 0x08000000
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_SERR_EN_SHIFT 27
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_SERR_EN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: DISCARD_TIMER_STATUS [26:26] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_STATUS_MASK 0x04000000
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_STATUS_SHIFT 26
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_DISCARD_TIMER_STATUS_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: SEC_DISCARD_TIMER [25:25] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_DISCARD_TIMER_MASK 0x02000000
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_DISCARD_TIMER_SHIFT 25
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_DISCARD_TIMER_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: PRIM_DISCARD_TIMER [24:24] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_PRIM_DISCARD_TIMER_MASK 0x01000000
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_PRIM_DISCARD_TIMER_SHIFT 24
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_PRIM_DISCARD_TIMER_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: FAST_B2B_EN [23:23] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_FAST_B2B_EN_MASK     0x00800000
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_FAST_B2B_EN_SHIFT    23
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_FAST_B2B_EN_DEFAULT  0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: SEC_BUS_RESET [22:22] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_BUS_RESET_MASK   0x00400000
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_BUS_RESET_SHIFT  22
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_BUS_RESET_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: MASTER_ABORT_MODE [21:21] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_MASTER_ABORT_MODE_MASK 0x00200000
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_MASTER_ABORT_MODE_SHIFT 21
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_MASTER_ABORT_MODE_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: RESERVED0 [20:18] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_RESERVED0_MASK       0x001c0000
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_RESERVED0_SHIFT      18
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: SEC_SERR_EN [17:17] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_SERR_EN_MASK     0x00020000
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_SERR_EN_SHIFT    17
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_SERR_EN_DEFAULT  0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: SEC_PERR_RESP_EN [16:16] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_PERR_RESP_EN_MASK 0x00010000
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_PERR_RESP_EN_SHIFT 16
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_SEC_PERR_RESP_EN_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: INT_PIN [15:08] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_PIN_MASK         0x0000ff00
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_PIN_SHIFT        8
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_PIN_DEFAULT      0x00000001
+
+/* PCIE_RC_CFG_TYPE1 :: BRIDGE_CONTROL :: INT_LINE [07:00] */
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_LINE_MASK        0x000000ff
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_LINE_SHIFT       0
+#define BCHP_PCIE_RC_CFG_TYPE1_BRIDGE_CONTROL_INT_LINE_DEFAULT     0x00000000
+
+#endif /* #ifndef BCHP_PCIE_RC_CFG_TYPE1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_pcie_rc_cfg_vendor.h b/include/linux/brcmstb/7435b0/bchp_pcie_rc_cfg_vendor.h
new file mode 100644
index 0000000..61ab59c
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_pcie_rc_cfg_vendor.h
@@ -0,0 +1,176 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:13 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_pcie_rc_cfg_vendor.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 3:37p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_PCIE_RC_CFG_VENDOR_H__
+#define BCHP_PCIE_RC_CFG_VENDOR_H__
+
+/***************************************************************************
+ *PCIE_RC_CFG_VENDOR
+ ***************************************************************************/
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_CAP       0x00410180 /* vendor_cap */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER 0x00410184 /* vendor_specific_header */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x00410188 /* Vendor Specific User Register 1 */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG2 0x0041018c /* Vendor Specific User Register 2 */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG3 0x00410190 /* Vendor Specific User Register 3 */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG4 0x00410194 /* Vendor Specific User Register 4 */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG5 0x00410198 /* Vendor Specific User Register 5 */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG6 0x0041019c /* Vendor Specific User Register 6 */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG7 0x004101a0 /* Vendor Specific User Register 7 */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG8 0x004101a4 /* Vendor Specific User Register 8 */
+
+/***************************************************************************
+ *VENDOR_CAP - vendor_cap
+ ***************************************************************************/
+/* PCIE_RC_CFG_VENDOR :: VENDOR_CAP :: NEXT [31:20] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_CAP_NEXT_MASK               0xfff00000
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_CAP_NEXT_SHIFT              20
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_CAP_NEXT_DEFAULT            0x00000000
+
+/* PCIE_RC_CFG_VENDOR :: VENDOR_CAP :: CAP_VER [19:16] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_CAP_CAP_VER_MASK            0x000f0000
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_CAP_CAP_VER_SHIFT           16
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_CAP_CAP_VER_DEFAULT         0x00000001
+
+/* PCIE_RC_CFG_VENDOR :: VENDOR_CAP :: VENDOR_SPEC_CAP_ID [15:00] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_CAP_VENDOR_SPEC_CAP_ID_MASK 0x0000ffff
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_CAP_VENDOR_SPEC_CAP_ID_SHIFT 0
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_CAP_VENDOR_SPEC_CAP_ID_DEFAULT 0x0000000b
+
+/***************************************************************************
+ *VENDOR_SPECIFIC_HEADER - vendor_specific_header
+ ***************************************************************************/
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_HEADER :: VSEC_LENGTH [31:20] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH_MASK 0xfff00000
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH_SHIFT 20
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH_DEFAULT 0x00000028
+
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_HEADER :: VSEC_REV [19:16] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_REV_MASK 0x000f0000
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_REV_SHIFT 16
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_REV_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_HEADER :: VSEC_ID [15:00] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_ID_MASK 0x0000ffff
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_ID_SHIFT 0
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_HEADER_VSEC_ID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VENDOR_SPECIFIC_REG1 - Vendor Specific User Register 1
+ ***************************************************************************/
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG1 :: Undefined [31:06] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_Undefined_MASK 0xffffffc0
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_Undefined_SHIFT 6
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_Undefined_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG1 :: ENDIAN_MODE_BAR3 [05:04] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3_MASK 0x00000030
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3_SHIFT 4
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG1 :: ENDIAN_MODE_BAR2 [03:02] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0x0000000c
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT 2
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_DEFAULT 0x00000000
+
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG1 :: ENDIAN_MODE_BAR1 [01:00] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1_MASK 0x00000003
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1_SHIFT 0
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VENDOR_SPECIFIC_REG2 - Vendor Specific User Register 2
+ ***************************************************************************/
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG2 :: Undefined [31:00] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG2_Undefined_MASK 0xffffffff
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG2_Undefined_SHIFT 0
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG2_Undefined_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VENDOR_SPECIFIC_REG3 - Vendor Specific User Register 3
+ ***************************************************************************/
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG3 :: Undefined [31:00] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG3_Undefined_MASK 0xffffffff
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG3_Undefined_SHIFT 0
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG3_Undefined_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VENDOR_SPECIFIC_REG4 - Vendor Specific User Register 4
+ ***************************************************************************/
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG4 :: Undefined [31:00] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG4_Undefined_MASK 0xffffffff
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG4_Undefined_SHIFT 0
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG4_Undefined_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VENDOR_SPECIFIC_REG5 - Vendor Specific User Register 5
+ ***************************************************************************/
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG5 :: Undefined [31:00] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG5_Undefined_MASK 0xffffffff
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG5_Undefined_SHIFT 0
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG5_Undefined_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VENDOR_SPECIFIC_REG6 - Vendor Specific User Register 6
+ ***************************************************************************/
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG6 :: Undefined [31:00] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG6_Undefined_MASK 0xffffffff
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG6_Undefined_SHIFT 0
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG6_Undefined_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VENDOR_SPECIFIC_REG7 - Vendor Specific User Register 7
+ ***************************************************************************/
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG7 :: Undefined [31:00] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG7_Undefined_MASK 0xffffffff
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG7_Undefined_SHIFT 0
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG7_Undefined_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VENDOR_SPECIFIC_REG8 - Vendor Specific User Register 8
+ ***************************************************************************/
+/* PCIE_RC_CFG_VENDOR :: VENDOR_SPECIFIC_REG8 :: Undefined [31:00] */
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG8_Undefined_MASK 0xffffffff
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG8_Undefined_SHIFT 0
+#define BCHP_PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG8_Undefined_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_PCIE_RC_CFG_VENDOR_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_sata_top_ctrl.h b/include/linux/brcmstb/7435b0/bchp_sata_top_ctrl.h
new file mode 100644
index 0000000..7e58587
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_sata_top_ctrl.h
@@ -0,0 +1,164 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:31 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_sata_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 3:57p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SATA_TOP_CTRL_H__
+#define BCHP_SATA_TOP_CTRL_H__
+
+/***************************************************************************
+ *SATA_TOP_CTRL - SATA3 MISC Control Registers
+ ***************************************************************************/
+#define BCHP_SATA_TOP_CTRL_Version               0x00180020 /* SATA3 Version Register */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL              0x00180024 /* SATA3 System Bus Access Control Register */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL               0x00180028 /* SATA3 Test Port Control register */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1            0x0018002c /* SATA3 phy interface control 1 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2            0x00180030 /* SATA3 phy interface control 2 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3            0x00180034 /* SATA3 phy interface control 3 */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT           0x00180038 /* SATA3 TP OUT */
+
+/***************************************************************************
+ *Version - SATA3 Version Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: Version :: reserved0 [31:08] */
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_MASK                  0xffffff00
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_SHIFT                 8
+
+/* SATA_TOP_CTRL :: Version :: major_version [07:04] */
+#define BCHP_SATA_TOP_CTRL_Version_major_version_MASK              0x000000f0
+#define BCHP_SATA_TOP_CTRL_Version_major_version_SHIFT             4
+#define BCHP_SATA_TOP_CTRL_Version_major_version_DEFAULT           0x00000000
+
+/* SATA_TOP_CTRL :: Version :: minor_version [03:00] */
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_MASK              0x0000000f
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_SHIFT             0
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_DEFAULT           0x00000001
+
+/***************************************************************************
+ *BUS_CTRL - SATA3 System Bus Access Control Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_31_17 [31:17] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_MASK            0xfffe0000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_SHIFT           17
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_DEFAULT         0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: overide_hwinit_registers [16:16] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_MASK  0x00010000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_SHIFT 16
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_DEFAULT 0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_15_8 [15:08] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_MASK             0x0000ff00
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_SHIFT            8
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_DEFAULT          0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: piodata_endian_ctrl [07:06] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_MASK       0x000000c0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SHIFT      6
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadata_endian_ctrl [05:04] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_MASK       0x00000030
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SHIFT      4
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadesc_endian_ctrl [03:02] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_MASK       0x0000000c
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SHIFT      2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: reg_endian_ctrl [01:00] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_MASK           0x00000003
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SHIFT          0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_DEFAULT        0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SwapEndianess  2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_HalfWordSwap   1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_NoSwap         0
+
+/***************************************************************************
+ *TP_CTRL - SATA3 Test Port Control register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: TP_CTRL :: tp_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_MASK                    0xffffffff
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_SHIFT                   0
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_1 - SATA3 phy interface control 1
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_1 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_2 - SATA3 phy interface control 2
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_2 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_3 - SATA3 phy interface control 3
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_3 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *SATA_TP_OUT - SATA3 TP OUT
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: SATA_TP_OUT :: TP_OUT [31:00] */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_MASK                 0xffffffff
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_SHIFT                0
+
+#endif /* #ifndef BCHP_SATA_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_sdio_0_cfg.h b/include/linux/brcmstb/7435b0/bchp_sdio_0_cfg.h
new file mode 100644
index 0000000..dbd486b
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_sdio_0_cfg.h
@@ -0,0 +1,638 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:39 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_sdio_0_cfg.h $
+ * 
+ * Hydra_Software_Devel/3   12/7/11 4:03p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SDIO_0_CFG_H__
+#define BCHP_SDIO_0_CFG_H__
+
+/***************************************************************************
+ *SDIO_0_CFG - SDIO (CARD) Configuration Registers
+ ***************************************************************************/
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1          0x0041a100 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2          0x0041a104 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL               0x0041a108 /* SDIO TP_OUT Control Register */
+#define BCHP_SDIO_0_CFG_CAP_REG0                 0x0041a10c /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_CAP_REG1                 0x0041a110 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET1                  0x0041a114 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET2                  0x0041a118 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY           0x0041a11c /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV               0x0041a120 /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_IP_DLY                   0x0041a130 /* SDIO Host input delay register */
+#define BCHP_SDIO_0_CFG_OP_DLY                   0x0041a134 /* SDIO Host output delay register */
+#define BCHP_SDIO_0_CFG_TUNING                   0x0041a138 /* SDIO Host tuning configuration register */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL                0x0041a13c /* SDIO Host 1p8V control logic select register */
+#define BCHP_SDIO_0_CFG_SCRATCH                  0x0041a1fc /* SDIO Scratch Register */
+#define BCHP_SDIO_0_CFG_VERSION                  0x0041a1f0 /* SDIO VERSION Register */
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL1 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_SEL_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_MASK    0x80000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_SHIFT   31
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_DEFAULT 0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_LEV [30:30] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_MASK       0x40000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_SHIFT      30
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved0 [29:29] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved0_MASK             0x20000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved0_SHIFT            29
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: RETUNING_REQ [28:28] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_MASK          0x10000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_SHIFT         28
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DDR_TAP_DELAY [27:24] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_MASK         0x0f000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_SHIFT        24
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_DEFAULT      0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DELAY_CTRL [23:21] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_MASK            0x00e00000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_SHIFT           21
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_DEFAULT         0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_ENA [20:20] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_MASK       0x00100000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_SHIFT      20
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_PULSE [19:19] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_MASK     0x00080000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_SHIFT    19
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DATA_PENDING [18:18] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_MASK          0x00040000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_SHIFT         18
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WR_FLUSH [17:17] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_MASK              0x00020000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_SHIFT             17
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: MF_NUM_WR [16:16] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_MASK             0x00010000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_SHIFT            16
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WORD_ABO [15:15] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_MASK              0x00008000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_SHIFT             15
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NBO [14:14] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_MASK             0x00004000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_SHIFT            14
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NHW [13:13] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_MASK             0x00002000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_SHIFT            13
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: BUFFER_ABO [12:12] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_MASK            0x00001000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_SHIFT           12
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_DEFAULT         0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_BUF_ACC [11:11] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_MASK           0x00000800
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_SHIFT          11
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_DEFAULT        0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SEQ_EN [10:10] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_MASK            0x00000400
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_SHIFT           10
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_DEFAULT         0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_RD_THRESH [09:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_MASK         0x000003e0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_SHIFT        5
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_DEFAULT      0x00000002
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SIZE [04:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_MASK              0x0000001f
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_SHIFT             0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_DEFAULT           0x00000004
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL2 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved0 [31:08] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_MASK             0xffffff00
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_SHIFT            8
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_BYTE [07:06] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_MASK     0x000000c0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_SHIFT    6
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved1 [05:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_MASK             0x00000020
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_SHIFT            5
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_HW [04:04] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_MASK       0x00000010
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_SHIFT      4
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_DEFAULT    0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_RD [03:02] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_MASK      0x0000000c
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_SHIFT     2
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_DEFAULT   0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_WR [01:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_MASK      0x00000003
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_SHIFT     0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_DEFAULT   0x00000000
+
+/***************************************************************************
+ *TP_OUT_SEL - SDIO TP_OUT Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TP_OUT_SEL :: reserved0 [31:01] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_MASK                  0xfffffffe
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_SHIFT                 1
+
+/* SDIO_0_CFG :: TP_OUT_SEL :: TP_OUT_SELECT [00:00] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_MASK              0x00000001
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_SHIFT             0
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *CAP_REG0 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG0 :: DDR50_SUPPORT [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_SHIFT               31
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_DEFAULT             0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SD104_SUPPORT [30:30] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_MASK                0x40000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_SHIFT               30
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDR50 [29:29] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_MASK                        0x20000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_SHIFT                       29
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_DEFAULT                     0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SLOT_TYPE [28:27] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_MASK                    0x18000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_SHIFT                   27
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_DEFAULT                 0x00000002
+
+/* SDIO_0_CFG :: CAP_REG0 :: ASYNCH_INT_SUPPORT [26:26] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_MASK           0x04000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_SHIFT          26
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_DEFAULT        0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 64B_SYS_BUS_SUPPORT [25:25] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_MASK          0x02000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_SHIFT         25
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 1_8V_SUPPORT [24:24] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_MASK                 0x01000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_SHIFT                24
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_DEFAULT              0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_0V_SUPPORT [23:23] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_MASK                 0x00800000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_SHIFT                23
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_3V_SUPPORT [22:22] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_MASK                 0x00400000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_SHIFT                22
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_DEFAULT              0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SUSP_RES_SUPPORT [21:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_MASK             0x00200000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_SHIFT            21
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDMA_SUPPORT [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_MASK                 0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_SHIFT                20
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_DEFAULT              0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: HIGH_SPEED_SUPPORT [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_MASK           0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_SHIFT          19
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_DEFAULT        0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: ADMA2_SUPPORT [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_MASK                0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_SHIFT               18
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_DEFAULT             0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: EXTENDED_MEDIA_SUPPORT [17:17] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_MASK       0x00020000
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_SHIFT      17
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: MAX_BL [16:15] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_MASK                       0x00018000
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_SHIFT                      15
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_DEFAULT                    0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: BASE_FREQ [14:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_MASK                    0x00007f80
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_SHIFT                   7
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_DEFAULT                 0x00000064
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_CLK_UNIT [06:06] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_MASK             0x00000040
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_SHIFT            6
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_FREQ [05:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_MASK                 0x0000003f
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_SHIFT                0
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_DEFAULT              0x00000032
+
+/***************************************************************************
+ *CAP_REG1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_REG_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_MASK             0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_SHIFT            31
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved0 [30:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_MASK                    0x7fe00000
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_SHIFT                   21
+
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_1_stuff [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_MASK                  0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_SHIFT                 20
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_BLK_MODE [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_MASK                 0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_SHIFT                19
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_MODE [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_MASK                     0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_SHIFT                    18
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_DEFAULT                  0x00000001
+
+/* SDIO_0_CFG :: CAP_REG1 :: CLK_MULT [17:10] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_MASK                     0x0003fc00
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_SHIFT                    10
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_MODES [09:08] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_MASK               0x00000300
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_SHIFT              8
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_DEFAULT            0x00000002
+
+/* SDIO_0_CFG :: CAP_REG1 :: USE_TUNING [07:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_MASK                   0x00000080
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_SHIFT                  7
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_DEFAULT                0x00000001
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_TIMER [06:03] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_MASK               0x00000078
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_SHIFT              3
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_DEFAULT            0x0000000a
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_D_SUPPORT [02:02] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_MASK             0x00000004
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_SHIFT            2
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_C_SUPPORT [01:01] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_MASK             0x00000002
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_SHIFT            1
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_A_SUPPORT [00:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_MASK             0x00000001
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_SHIFT            0
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PRESET1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET1 :: PRESET1_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET100 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_MASK                     0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_SHIFT                    16
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET50 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_MASK                      0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_SHIFT                     0
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_DEFAULT                   0x00000001
+
+/***************************************************************************
+ *PRESET2 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET2 :: PRESET2_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET2 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET25 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_MASK                      0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_SHIFT                     16
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_DEFAULT                   0x00000002
+
+/* SDIO_0_CFG :: PRESET2 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET12P5 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_MASK                    0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_SHIFT                   0
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_DEFAULT                 0x00000003
+
+/***************************************************************************
+ *SD_CLOCK_DELAY - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved0 [31:31] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_SHIFT             31
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: CLOCK_DELAY_OVERRIDE [30:30] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_MASK   0x40000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_SHIFT  30
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_DEFAULT 0x00000001
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_SEL [29:29] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_MASK        0x20000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_SHIFT       29
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_DEFAULT     0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved1 [28:12] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved1_MASK              0x1ffff000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved1_SHIFT             12
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: OUTPUT_CLOCK_DELAY [11:08] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_MASK     0x00000f00
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_SHIFT    8
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INTERNAL_CLOCK_DELAY [07:04] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_MASK   0x000000f0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_SHIFT  4
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_DEFAULT 0x0000000f
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_MASK      0x0000000f
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_SHIFT     0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_DEFAULT   0x0000000f
+
+/***************************************************************************
+ *SD_PAD_DRV - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_PAD_DRV :: OVERRIDE_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_SHIFT               31
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved0 [30:23] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_MASK                  0x7f800000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_SHIFT                 23
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CLK_VAL [22:20] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_MASK                    0x00700000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_SHIFT                   20
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved1 [19:19] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_MASK                  0x00080000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_SHIFT                 19
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CMD_VAL [18:16] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_MASK                    0x00070000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_SHIFT                   16
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved2 [15:15] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_MASK                  0x00008000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_SHIFT                 15
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT3_VAL [14:12] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_MASK                   0x00007000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_SHIFT                  12
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved3 [11:11] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_MASK                  0x00000800
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_SHIFT                 11
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT2_VAL [10:08] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_MASK                   0x00000700
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_SHIFT                  8
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved4 [07:07] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_MASK                  0x00000080
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_SHIFT                 7
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT1_VAL [06:04] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_MASK                   0x00000070
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_SHIFT                  4
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved5 [03:03] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_MASK                  0x00000008
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_SHIFT                 3
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT0_VAL [02:00] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_MASK                   0x00000007
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_SHIFT                  0
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_DEFAULT                0x00000005
+
+/***************************************************************************
+ *IP_DLY - SDIO Host input delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_DEFAULT                   0x00000000
+
+/* SDIO_0_CFG :: IP_DLY :: FORCE_USE_IP_TUNE_CLK [30:30] */
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_MASK          0x40000000
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_SHIFT         30
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: IP_DLY :: reserved0 [29:18] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_MASK                      0x3ffc0000
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: IP_DLY :: IP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_DEFAULT               0x00000003
+
+/* SDIO_0_CFG :: IP_DLY :: reserved1 [15:06] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_MASK                      0x0000ffc0
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_SHIFT                     6
+
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_DELAY [05:00] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_MASK                   0x0000003f
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_DEFAULT                0x00000028
+
+/***************************************************************************
+ *OP_DLY - SDIO Host output delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_DEFAULT                   0x00000000
+
+/* SDIO_0_CFG :: OP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: OP_DLY :: OP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: OP_DLY :: reserved1 [15:04] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_MASK                      0x0000fff0
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_SHIFT                     4
+
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_MASK                   0x0000000f
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TUNING - SDIO Host tuning configuration register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TUNING :: reserved0 [31:04] */
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_MASK                      0xfffffff0
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_SHIFT                     4
+
+/* SDIO_0_CFG :: TUNING :: TUNING_CMD_SUCCESS_CNT [03:00] */
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_MASK         0x0000000f
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_SHIFT        0
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_DEFAULT      0x00000008
+
+/***************************************************************************
+ *VOLT_CTRL - SDIO Host 1p8V control logic select register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VOLT_CTRL :: reserved0 [31:05] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_MASK                   0xffffffe0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_SHIFT                  5
+
+/* SDIO_0_CFG :: VOLT_CTRL :: POW_INV_EN [04:04] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_MASK                  0x00000010
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_SHIFT                 4
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_VAL [03:03] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_MASK                    0x00000008
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_SHIFT                   3
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_DEFAULT                 0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_INV_EN [02:02] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_MASK                 0x00000004
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_SHIFT                2
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_CTRL_SEL [01:00] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_MASK               0x00000003
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_SHIFT              0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SCRATCH - SDIO Scratch Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SCRATCH :: SCRATCH_BITS [31:00] */
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_MASK                  0xffffffff
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_SHIFT                 0
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_DEFAULT               0x00000000
+
+/***************************************************************************
+ *VERSION - SDIO VERSION Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VERSION :: SD_VER [31:24] */
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_MASK                        0xff000000
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_SHIFT                       24
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_DEFAULT                     0x00000030
+
+/* SDIO_0_CFG :: VERSION :: MMC_VER [23:16] */
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_MASK                       0x00ff0000
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_SHIFT                      16
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_DEFAULT                    0x00000044
+
+/* SDIO_0_CFG :: VERSION :: REV [15:08] */
+#define BCHP_SDIO_0_CFG_VERSION_REV_MASK                           0x0000ff00
+#define BCHP_SDIO_0_CFG_VERSION_REV_SHIFT                          8
+#define BCHP_SDIO_0_CFG_VERSION_REV_DEFAULT                        0x000000a9
+
+/* SDIO_0_CFG :: VERSION :: A2S_VER [07:00] */
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_MASK                       0x000000ff
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_SHIFT                      0
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_DEFAULT                    0x00000001
+
+#endif /* #ifndef BCHP_SDIO_0_CFG_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/7435b0/bchp_sun_top_ctrl.h
new file mode 100644
index 0000000..d726dc1
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_sun_top_ctrl.h
@@ -0,0 +1,7432 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Sat May  5 03:10:05 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SUN_TOP_CTRL_H__
+#define BCHP_SUN_TOP_CTRL_H__
+
+/***************************************************************************
+ *SUN_TOP_CTRL - Top Control registers
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID         0x00404000 /* Chip family ID */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID             0x00404004 /* Product Revision ID */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x0040401c /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x00404020 /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x00404024 /* Bond option value register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x00404028 /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x0040402c /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x00404030 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x00404034 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x00404038 /* Semaphore channel 0 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x0040403c /* Semaphore channel 1 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x00404040 /* Semaphore channel 2 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x00404044 /* Semaphore channel 3 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x00404048 /* Semaphore channel 4 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x0040404c /* Semaphore channel 5 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x00404050 /* Semaphore channel 6 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x00404054 /* Semaphore channel 7 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x00404058 /* Semaphore channel 8 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x0040405c /* Semaphore channel 9 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x00404060 /* Semaphore channel 10 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x00404064 /* Semaphore channel 11 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x00404068 /* Semaphore channel 12 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x0040406c /* Semaphore channel 13 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x00404070 /* Semaphore channel 14 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x00404074 /* Semaphore channel 15 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x00404078 /* General watchdog timer 0 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x0040407c /* General watchdog timer 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x00404080 /* General control register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x00404084 /* General control register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x00404088 /* General control register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x0040408c /* General control register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x00404090 /* General control register 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x00404094 /* General control register 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x00404098 /* General status register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x0040409c /* General status register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x004040a0 /* General status register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x00404100 /* Pinmux control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x00404104 /* Pinmux control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x00404108 /* Pinmux control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x0040410c /* Pinmux control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x00404110 /* Pinmux control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x00404114 /* Pinmux control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x00404118 /* Pinmux control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x0040411c /* Pinmux control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x00404120 /* Pinmux control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x00404124 /* Pinmux control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10        0x00404128 /* Pinmux control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11        0x0040412c /* Pinmux control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12        0x00404130 /* Pinmux control register 12 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13        0x00404134 /* Pinmux control register 13 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14        0x00404138 /* Pinmux control register 14 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15        0x0040413c /* Pinmux control register 15 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16        0x00404140 /* Pinmux control register 16 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17        0x00404144 /* Pinmux control register 17 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18        0x00404148 /* Pinmux control register 18 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19        0x0040414c /* Pinmux control register 19 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x00404150 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x00404154 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x00404158 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x0040415c /* Pad pull-up/pull-down control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x00404160 /* Pad pull-up/pull-down control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5     0x00404164 /* Pad pull-up/pull-down control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6     0x00404168 /* Pad pull-up/pull-down control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7     0x0040416c /* Pad pull-up/pull-down control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8     0x00404170 /* Pad pull-up/pull-down control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9     0x00404174 /* Pad pull-up/pull-down control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10    0x00404178 /* Pad pull-up/pull-down control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11    0x0040417c /* Pad pull-up/pull-down control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12    0x00404180 /* Pad pull-up/pull-down control register 12 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13    0x00404184 /* Pad pull-up/pull-down control register 13 */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x00404188 /* Bypass clock unselect register 0 */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x00404300 /* Reset control */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE    0x00404304 /* Reset source enable */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET        0x00404308 /* Software master reset */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION     0x0040430c /* Hardware reset extension */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR          0x00404310 /* Reset Monitor */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x00404314 /* Reset history */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET          0x00404318 /* Software init 0 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR        0x0040431c /* Software init 0 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS       0x00404320 /* Software init 0 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR  0x00404324 /* Security software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET          0x00404330 /* Software init 1 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR        0x00404334 /* Software init 1 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS       0x00404338 /* Software init 1 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR  0x0040433c /* Security software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x00404364 /* Scratch register */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x00404368 /* Spare control bits reserved for future use */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x00404380 /* Test port control */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x00404384 /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x00404388 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x0040438c /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x00404390 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x00404394 /* EJTAG input bus enables */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x00404398 /* EJTAG output select */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL        0x0040439c /* UART Router select */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL             0x004043a0 /* VTRAP Control */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS           0x004043a4 /* VTRAP Status */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x00404400 /* Serial Slave Port configuration register */
+#define BCHP_SUN_TOP_CTRL_SERS_REV               0x00404420 /* SERS Revision Register */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x00404424 /* SERS Configuration Register */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x00404514 /* Block select for RO testmode */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION     0x00404518 /* Test configuration */
+
+/***************************************************************************
+ *CHIP_FAMILY_ID - Chip family ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT    0x74350010
+
+/***************************************************************************
+ *PRODUCT_ID - Product Revision ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK               0xffffffff
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT            0x74350010
+
+/***************************************************************************
+ *BSP_FEATURE_TABLE_ADDR - BSP feature table address
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_VALUE_0 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:13] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xffffe000
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            13
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd [12:09] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_MASK            0x00001e00
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_SHIFT           9
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_ebi_pad_config [08:07] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_pad_config_MASK  0x00000180
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_pad_config_SHIFT 7
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_reset_outb_def_val [06:06] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_SHIFT 6
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rc_ep [05:05] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rc_ep_MASK           0x00000020
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rc_ep_SHIFT          5
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [04:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK      0x0000001e
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT   0x0000000a
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 0
+
+/***************************************************************************
+ *STRAP_VALUE_1 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xffffffe0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            5
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias [04:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_MASK      0x0000001e
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_SHIFT     1
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK     0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT    0
+
+/***************************************************************************
+ *BOND_STATUS - Bond option value register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1
+
+/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_0 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb2_disable [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb2_disable_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb2_disable_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb2_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb1_disable [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb1_disable_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb1_disable_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb1_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_temp_sensor_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avc_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_svc_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_transcode_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_transcode_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_transcode_disable_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_transcode_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_capsense_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_capsense_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_capsense_disable_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_capsense_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_moca_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_pcie_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie_disable_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_uhf_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_uhf_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_uhf_disable_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_uhf_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sata_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ephy_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_moca2_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca2_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca2_disable_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca2_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_chip_variant [14:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_chip_variant_MASK 0x00007800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_chip_variant_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_chip_variant_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [07:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x000000c0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 0x00000003
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [04:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000001e
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_pcie_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_pcie_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_pcie_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_pcie_enable_DEFAULT 0x00000001
+
+/***************************************************************************
+ *OTP_OPTION_TEST_1 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_27 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_26 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_25 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_24 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_23 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_22 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_21 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_20 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_19 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_18 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_17 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_16 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_15 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_14 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_0 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_2nd_raaga_disable [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_2nd_raaga_disable_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_2nd_raaga_disable_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_2nd_raaga_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_pwm_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pwm_disable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pwm_disable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pwm_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb3_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_0 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb2_disable [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb2_disable_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb2_disable_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb1_disable [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb1_disable_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb1_disable_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_temp_sensor_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_temp_sensor_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_temp_sensor_disable_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avc_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avc_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avc_disable_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_svc_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_svc_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_svc_disable_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_transcode_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_transcode_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_transcode_disable_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_capsense_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_capsense_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_capsense_disable_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_moca_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_pcie_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pcie_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pcie_disable_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_uhf_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_uhf_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_uhf_disable_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sata_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ephy_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_moca2_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca2_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca2_disable_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_chip_variant [14:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_chip_variant_MASK 0x00007800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_chip_variant_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [07:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 6
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [04:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000001e
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_pcie_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_pcie_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_pcie_enable_SHIFT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_1 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_27 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_26 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_25 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_24 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_23 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_22 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_21 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_20 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_19 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_18 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_17 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_16 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_15 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_14 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 6
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_0 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_2nd_raaga_disable [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_2nd_raaga_disable_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_2nd_raaga_disable_SHIFT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_pwm_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pwm_disable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pwm_disable_SHIFT 2
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb3_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb3_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb3_disable_SHIFT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_SHIFT 0
+
+/***************************************************************************
+ *SEMAPHORE_0 - Semaphore channel 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_1 - Semaphore channel 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_2 - Semaphore channel 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_3 - Semaphore channel 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_4 - Semaphore channel 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_5 - Semaphore channel 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_6 - Semaphore channel 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_7 - Semaphore channel 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_8 - Semaphore channel 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_9 - Semaphore channel 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_10 - Semaphore channel 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_11 - Semaphore channel 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_12 - Semaphore channel 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_13 - Semaphore channel 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_14 - Semaphore channel 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_15 - Semaphore channel 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_0 - General watchdog timer 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_1 - General watchdog timer 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK     0x80000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT    31
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK     0x40000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT    30
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK     0x20000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT    29
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK     0x10000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT    28
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK     0x02000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT    25
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK     0x01000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT    24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK     0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT    23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK     0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT    22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK     0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT    21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK     0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT    20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK     0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT    19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK     0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT    18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK     0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT    17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK     0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT    16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb1_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_mode_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_mode_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_mode_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb0_mode [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_DEFAULT         0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_1 - General control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_2 - General control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_3 - General control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_4 - General control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_5 - General control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK          0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT         8
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_1 - General status register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_2 - General status register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xffff0000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   16
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: ebi_4_pad_slew [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_4_pad_slew_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_4_pad_slew_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_4_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: ebi_3_pad_slew [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_3_pad_slew_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_3_pad_slew_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_3_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: ebi_2_pad_slew [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_2_pad_slew_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_2_pad_slew_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_2_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: ebi_1_pad_slew [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_1_pad_slew_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_1_pad_slew_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_1_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: ebi_0_pad_slew [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_0_pad_slew_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_0_pad_slew_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_ebi_0_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: emmc_pad_slew [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_emmc_pad_slew_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_emmc_pad_slew_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_emmc_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: bspi_pad_slew [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_bspi_pad_slew_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_bspi_pad_slew_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_bspi_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_1_pad_slew [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_slew_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_slew_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_1_pad_sel [07:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_GMII_CMOS_3P3V 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_RGMII_CMOS_2P5V 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_HSTL_CLASS1_1P5V 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_HSTL_CLASS1_1P8V 3
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_slew [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_slew_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_slew_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_sel [04:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_MASK 0x00000018
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_GMII_CMOS_3P3V 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_RGMII_CMOS_2P5V 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_HSTL_CLASS1_1P5V 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_HSTL_CLASS1_1P8V 3
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_slew [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_slew_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_slew_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_sel [01:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_GMII_CMOS_3P3V 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_RGMII_CMOS_2P5V 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_HSTL_CLASS1_1P5V 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_HSTL_CLASS1_1P8V 3
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK    0xf0000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT   28
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_057 [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_056 [26:26] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_055 [25:25] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_054 [24:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_053 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_052 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_051 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_050 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_049 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_048 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_047 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_046 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_045 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_044 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_043 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_042 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_041 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_040 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_039 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_038 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_037 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_036 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_035 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_034 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_033 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_032 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_031 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_031_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_031_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_031_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_030 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_030_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_030_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_030_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xffffff80
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_hys_en [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_oeb [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_do [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_src [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_16MA 7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_07 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_MASK          0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_SHIFT         28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_EBI_DATA_07   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_ALT_TP_IN_07  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_06 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_MASK          0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_EBI_DATA_06   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_ALT_TP_IN_06  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_05 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_MASK          0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_SHIFT         20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_EBI_DATA_05   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_ALT_TP_IN_05  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_04 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_MASK          0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_SHIFT         16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_EBI_DATA_04   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_ALT_TP_IN_04  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_03 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_MASK          0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_EBI_DATA_03   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_ALT_TP_IN_03  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_02 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_MASK          0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_EBI_DATA_02   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_ALT_TP_IN_02  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_01 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_MASK          0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_SHIFT         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_EBI_DATA_01   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_ALT_TP_IN_01  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_00 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_MASK          0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_EBI_DATA_00   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_ALT_TP_IN_00  1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_15 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_15_MASK          0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_15_SHIFT         28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_15_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_15_EBI_DATA_15   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_15_ALT_TP_IN_15  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_14 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_14_MASK          0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_14_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_14_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_14_EBI_DATA_14   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_14_ALT_TP_IN_14  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_13 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_13_MASK          0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_13_SHIFT         20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_13_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_13_EBI_DATA_13   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_13_ALT_TP_IN_13  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_12 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_12_MASK          0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_12_SHIFT         16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_12_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_12_EBI_DATA_12   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_12_ALT_TP_IN_12  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_11 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_11_MASK          0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_11_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_11_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_11_EBI_DATA_11   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_11_ALT_TP_IN_11  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_10 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_10_MASK          0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_10_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_10_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_10_EBI_DATA_10   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_10_ALT_TP_IN_10  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_09 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_09_MASK          0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_09_SHIFT         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_09_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_09_EBI_DATA_09   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_09_ALT_TP_IN_09  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_08 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_08_MASK          0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_08_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_08_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_08_EBI_DATA_08   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_08_ALT_TP_IN_08  1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_07 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_07_MASK          0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_07_SHIFT         28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_07_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_07_EBI_ADDR_07   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_07_ALT_TP_OUT_07 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_06 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_06_MASK          0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_06_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_06_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_06_EBI_ADDR_06   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_06_ALT_TP_OUT_06 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_05 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_05_MASK          0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_05_SHIFT         20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_05_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_05_EBI_ADDR_05   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_05_ALT_TP_OUT_05 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_04 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_04_MASK          0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_04_SHIFT         16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_04_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_04_EBI_ADDR_04   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_04_ALT_TP_OUT_04 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_03 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_03_MASK          0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_03_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_03_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_03_EBI_ADDR_03   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_03_ALT_TP_OUT_03 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_02 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_02_MASK          0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_02_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_02_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_02_EBI_ADDR_02   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_02_ALT_TP_OUT_02 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_01 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_01_MASK          0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_01_SHIFT         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_01_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_01_EBI_ADDR_01   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_01_ALT_TP_OUT_01 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_00 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_00_MASK          0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_00_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_00_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_00_EBI_ADDR_00   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_00_ALT_TP_OUT_00 1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_23 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_23_MASK          0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_23_SHIFT         28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_23_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_23_EBI_ADDR_23   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_23_ALT_TP_OUT_23 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_22 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_22_MASK          0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_22_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_22_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_22_EBI_ADDR_22   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_22_ALT_TP_OUT_22 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_21 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_21_MASK          0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_21_SHIFT         20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_21_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_21_EBI_ADDR_21   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_21_ALT_TP_OUT_21 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_20 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_20_MASK          0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_20_SHIFT         16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_20_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_20_EBI_ADDR_20   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_20_ALT_TP_OUT_20 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_19 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_19_MASK          0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_19_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_19_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_19_EBI_ADDR_19   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_19_ALT_TP_OUT_19 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_18 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_18_MASK          0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_18_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_18_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_18_EBI_ADDR_18   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_18_ALT_TP_OUT_18 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_17 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_17_MASK          0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_17_SHIFT         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_17_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_17_EBI_ADDR_17   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_17_ALT_TP_OUT_17 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_16 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_16_MASK          0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_16_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_16_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_16_EBI_ADDR_16   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_16_ALT_TP_OUT_16 1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_4 - Pinmux control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_cs3b [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs3b_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs3b_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs3b_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs3b_EBI_CS3B         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs3b_ALT_TP_OUT_31    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_cs2b [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs2b_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs2b_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs2b_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs2b_EBI_CS2B         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs2b_ALT_TP_OUT_30    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_cs1b [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs1b_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs1b_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs1b_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs1b_EBI_CS1B         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs1b_ALT_TP_OUT_29    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_cs0b [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs0b_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs0b_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs0b_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs0b_EBI_CS0B         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_cs0b_ALT_TP_OUT_28    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr_27 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_27_MASK          0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_27_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_27_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_27_EBI_ADDR_27   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_27_ALT_TP_OUT_27 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr_26 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_26_MASK          0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_26_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_26_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_26_EBI_ADDR_26   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_26_ALT_TP_OUT_26 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr_25 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_25_MASK          0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_25_SHIFT         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_25_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_25_EBI_ADDR_25   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_25_ALT_TP_OUT_25 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr_24 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_24_MASK          0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_24_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_24_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_24_EBI_ADDR_24   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_24_ALT_TP_OUT_24 1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_5 - Pinmux control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_003 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_003_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_003_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_003_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_003_GPIO_003         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_003_EMAC0_RX_EN_CTL  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_003_UART_TXD_0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_003_PKT_DATA0        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_003_TP_OUT_15        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_003_PM_GPIO_003      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_002 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_002_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_002_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_002_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_002_GPIO_002         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_002_EMAC0_RX_CLK     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_002_UART_RXD_0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_002_PKT_CLK0         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_002_IR_IN1           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_002_TP_IN_05         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_002_PM_GPIO_002      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_001 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_001_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_001_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_001_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_001_GPIO_001         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_001_ENET_LINK        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_001_ENET_ACTIVITY    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_001_MII0_TX_ERR      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_001_TP_OUT_13        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_001_PM_GPIO_001      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_000 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_000_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_000_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_000_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_000_GPIO_000         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_000_ENET_ACTIVITY    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_000_ENET_LINK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_000_MII0_RX_ERR      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_000_TEST_THP         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_000_TP_OUT_12        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_000_PM_GPIO_000      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: sdio1_clk [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_sdio1_clk_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_sdio1_clk_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_sdio1_clk_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_sdio1_clk_SDIO1_CLK       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_sdio1_clk_PM_SDIO1_CLK    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: sdio1_cmd [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_sdio1_cmd_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_sdio1_cmd_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_sdio1_cmd_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_sdio1_cmd_SDIO1_CMD       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_sdio1_cmd_PM_SDIO1_CMD    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_waitb [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_waitb_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_waitb_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_waitb_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_waitb_EBI_WAITB       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_waitb_PM_EBI_WAITB    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_nand_rbb [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_nand_rbb_MASK         0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_nand_rbb_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_nand_rbb_DEFAULT      0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_nand_rbb_EBI_NAND_RBB 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_nand_rbb_PM_EBI_NAND_RBB 1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_6 - Pinmux control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_011 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_011_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_011_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_011_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_011_GPIO_011         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_011_EMAC0_TXD_01     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_011_UART_TXD_2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_011_PKT_VALID1       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_011_TTX0_DATA        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_011_TP_OUT_23        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_011_PM_GPIO_011      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_010 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_010_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_010_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_010_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_010_GPIO_010         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_010_EMAC0_TXD_00     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_010_UART_RXD_2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_010_PKT_ERROR1       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_010_TTX0_REQ         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_010_TP_IN_22         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_010_PM_GPIO_010      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_009 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_009_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_009_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_009_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_009_GPIO_009         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_009_EMAC0_TX_EN_CTL  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_009_UART_RTS_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_009_PKT_SYNC1        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_009_VEC_VSYNC_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_009_TP_OUT_21        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_009_PM_GPIO_009      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_008 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_008_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_008_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_008_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_008_GPIO_008         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_008_EMAC0_TX_CLK     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_008_UART_CTS_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_008_PKT_DATA1        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_008_VEC_VSYNC_0      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_008_TP_IN_20         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_008_PM_GPIO_008      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_007 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_007_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_007_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_007_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_007_GPIO_007         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_007_EMAC0_RXD_03     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_007_UART_TXD_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_007_PKT_CLK1         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_007_EXT_IRQB_4       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_007_TP_OUT_19        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_007_PM_GPIO_007      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_006 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_006_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_006_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_006_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_006_GPIO_006         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_006_EMAC0_RXD_02     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_006_UART_RXD_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_006_PKT_VALID0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_006_EXT_IRQB_3       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_006_TP_IN_18         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_006_PM_GPIO_006      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_005 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_005_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_005_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_005_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_005_GPIO_005         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_005_EMAC0_RXD_01     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_005_UART_RTS_0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_005_PKT_ERROR0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_005_VEC_HSYNC_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_005_TP_OUT_17        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_005_PM_GPIO_005      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_004 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_004_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_004_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_004_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_004_GPIO_004         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_004_EMAC0_RXD_00     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_004_UART_CTS_0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_004_PKT_SYNC0        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_004_VEC_HSYNC_0      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_004_TP_OUT_16        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_004_PM_GPIO_004      6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_7 - Pinmux control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_019 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_019_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_019_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_019_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_019_GPIO_019         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_019_PKT_ERROR0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_019_MTSIF0_DATA1     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_019_EMAC1_RXD_01     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_019_UART_RXD_0       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_019_PPKT_DATA1       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_019_PM_GPIO_019      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_018 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_018_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_018_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_018_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_018_GPIO_018         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_018_PKT_SYNC0        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_018_MTSIF0_SYNC      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_018_EMAC1_RXD_00     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_018_UART_RTS_0       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_018_PPKT_SYNC        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_018_TP_OUT_30        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_018_PM_GPIO_018      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_017 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_017_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_017_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_017_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_017_GPIO_017         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_017_PKT_DATA0        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_017_MTSIF0_DATA0     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_017_EMAC1_RX_EN_CTL  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_017_UART_CTS_0       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_017_PPKT_DATA0       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_017_TP_OUT_29        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_017_PM_GPIO_017      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_016 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_016_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_016_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_016_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_016_GPIO_016         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_016_PKT_CLK0         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_016_MTSIF0_CLK       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_016_EMAC1_RX_CLK     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_016_EXT_IRQB_0       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_016_PPKT_CLK         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_016_TP_OUT_28        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_016_PM_GPIO_016      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_015 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_015_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_015_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_015_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_015_GPIO_015         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_015_PKT_VALID5       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_015_EMAC0_MDC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_015_TTX0_DATA        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_015_PM_GPIO_015      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_014 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_014_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_014_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_014_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_014_GPIO_014         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_014_PKT_ERROR5       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_014_EMAC0_MDIO       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_014_TTX0_REQ         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_014_TP_OUT_26        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_014_PM_GPIO_014      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_013 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_013_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_013_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_013_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_013_GPIO_013         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_013_EMAC0_TXD_03     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_013_UART_RTS_2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_013_PKT_VALID2       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_013_TTX1_DATA        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_013_TP_OUT_25        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_013_PM_GPIO_013      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_012 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_012_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_012_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_012_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_012_GPIO_012         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_012_EMAC0_TXD_02     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_012_UART_CTS_2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_012_PKT_ERROR2       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_012_TTX1_REQ         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_012_TP_OUT_24        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_012_PM_GPIO_012      6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_8 - Pinmux control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_027 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_027_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_027_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_027_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_027_GPIO_027         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_027_PKT_VALID2       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_027_MTSIF0_DATA7     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_027_EMAC1_TXD_03     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_027_PPKT_DATA7       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_027_TP_IN_07         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_027_PM_GPIO_027      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_026 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_026_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_026_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_026_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_026_GPIO_026         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_026_PKT_ERROR2       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_026_MTSIF0_DATA6     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_026_EMAC1_TXD_02     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_026_PPKT_DATA6       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_026_TP_IN_06         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_026_PM_GPIO_026      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_025 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_025_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_025_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_025_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_025_GPIO_025         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_025_PKT_VALID1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_025_MTSIF_ATS_RST    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_025_EMAC1_TXD_01     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_025_UART_TXD_1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_025_TP_OUT_14        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_025_PM_GPIO_025      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_024 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_024_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_024_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_024_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_024_GPIO_024         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_024_PKT_ERROR1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_024_MTSIF0_DATA5     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_024_EMAC1_TXD_00     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_024_UART_RXD_1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_024_PPKT_DATA5       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_024_PM_GPIO_024      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_023 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_023_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_023_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_023_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_023_GPIO_023         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_023_PKT_SYNC1        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_023_MTSIF0_DATA4     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_023_EMAC1_TX_EN_CTL  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_023_UART_RTS_1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_023_PPKT_DATA4       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_023_PM_GPIO_023      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_022 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_022_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_022_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_022_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_022_GPIO_022         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_022_PKT_DATA1        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_022_MTSIF0_DATA3     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_022_EMAC1_TX_CLK     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_022_UART_CTS_1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_022_PPKT_DATA3       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_022_TP_IN_02         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_022_PM_GPIO_022      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_021 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_021_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_021_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_021_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_021_GPIO_021         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_021_PKT_CLK1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_021_MTSIF0_DATA2     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_021_EMAC1_RXD_03     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_021_EXT_IRQB_1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_021_PPKT_DATA2       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_021_TP_IN_01         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_021_PM_GPIO_021      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_020 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_020_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_020_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_020_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_020_GPIO_020         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_020_PKT_VALID0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_020_MTSIF0_VALID     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_020_EMAC1_RXD_02     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_020_UART_TXD_0       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_020_PPKT_VALID       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_020_PM_GPIO_020      6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_9 - Pinmux control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_035 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_035_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_035_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_035_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_035_GPIO_035         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_035_CHIP2POD_SCTL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_035_SPI_M_SS0B       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_035_EBI_ADDR_02      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_035_VEC_VSYNC_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_035_TP_IN_15         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_035_PM_GPIO_035      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_034 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_034_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_034_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_034_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_034_GPIO_034         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_034_CHIP2POD_SDO     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_034_SPI_M_MISO       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_034_EBI_ADDR_00      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_034_SC0_VPP          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_034_SC1_VPP          5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_034_TP_IN_14         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_034_PM_GPIO_034      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_033 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_GPIO_033         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_POD2CHIP_SDI     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_SPI_M_MOSI       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_LED_LD_11        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_SC0_AUX2         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_SC1_AUX2         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_VEC_VSYNC_0      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_TP_IN_13         7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_033_PM_GPIO_033      8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_032 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_032_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_032_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_032_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_032_GPIO_032         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_032_CHIP2POD_SCLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_032_SPI_M_SCK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_032_EBI_ADDR_01      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_032_SC0_AUX1         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_032_SC1_AUX1         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_032_VEC_VSYNC_0      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_032_PM_GPIO_032      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_031 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_031_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_031_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_031_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_031_GPIO_031         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_031_CHIP2POD_MCLKO   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_031_RMXP_CLK         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_031_EBI_ADDR_15      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_031_SPI_S_MISO       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_031_PM_GPIO_031      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_030 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_030_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_030_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_030_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_030_GPIO_030         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_030_POD2CHIP_MCLKI   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_030_PPKT_CLK         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_030_EBI_ADDR_14      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_030_SPI_S_SS0B       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_030_PM_GPIO_030      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_029 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_029_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_029_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_029_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_029_GPIO_029         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_029_PKT_SYNC3        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_029_EMAC1_MDC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_029_TP_IN_09         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_029_PM_GPIO_029      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_028 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_028_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_028_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_028_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_028_GPIO_028         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_028_PKT_DATA3        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_028_EMAC1_MDIO       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_028_TP_IN_08         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_028_PM_GPIO_028      4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_10 - Pinmux control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_043 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_043_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_043_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_043_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_043_GPIO_043        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_043_POD2CHIP_MDI5   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_043_PPKT_DATA5      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_043_VO1_656_5       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_043_SC0_AUX1        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_043_SC1_AUX1        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_043_TP_IN_23        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_043_PM_GPIO_043     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_042 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_042_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_042_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_042_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_042_GPIO_042        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_042_POD2CHIP_MDI4   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_042_PPKT_DATA4      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_042_VO1_656_4       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_042_UART_TXD_2      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_042_TP_OUT_22       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_042_PM_GPIO_042     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_041 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_041_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_041_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_041_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_041_GPIO_041        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_041_POD2CHIP_MDI3   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_041_PPKT_DATA3      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_041_VO1_656_3       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_041_UART_RXD_2      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_041_TP_IN_21        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_041_PM_GPIO_041     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_040 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_040_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_040_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_040_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_040_GPIO_040        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_040_POD2CHIP_MDI2   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_040_PPKT_DATA2      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_040_VO1_656_2       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_040_UART_TXD_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_040_TP_OUT_20       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_040_PM_GPIO_040     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_039 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_039_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_039_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_039_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_039_GPIO_039        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_039_POD2CHIP_MDI1   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_039_PPKT_DATA1      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_039_VO1_656_1       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_039_UART_RXD_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_039_TP_IN_19        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_039_PM_GPIO_039     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_038 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_038_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_038_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_038_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_038_GPIO_038        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_038_POD2CHIP_MDI0   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_038_PPKT_DATA0      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_038_VO1_656_0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_038_UART_TXD_0      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_038_TP_OUT_18       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_038_PM_GPIO_038     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_037 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_037_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_037_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_037_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_037_GPIO_037        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_037_POD2CHIP_MIVAL  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_037_PPKT_VALID      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_037_VO1_656_CLK     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_037_UART_RXD_0      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_037_TP_IN_17        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_037_PM_GPIO_037     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_036 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_036_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_036_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_036_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_036_GPIO_036        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_036_POD2CHIP_MISTRT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_036_PPKT_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_036_PM_GPIO_036     3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_11 - Pinmux control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_051 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_051_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_051_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_051_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_051_GPIO_051        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_051_CHIP2POD_MDO2   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_051_RMXP_DATA2      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_051_EBI_ADDR_20     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_051_LED_LD_4        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_051_TP_IN_31        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_051_PM_GPIO_051     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_050 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_050_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_050_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_050_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_050_GPIO_050        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_050_CHIP2POD_MDO1   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_050_RMXP_DATA1      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_050_EBI_ADDR_19     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_050_LED_LD_3        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_050_TP_IN_30        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_050_PM_GPIO_050     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_049 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_GPIO_049        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_CHIP2POD_MDO0   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_RMXP_DATA0      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_EBI_ADDR_18     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_LED_LD_2        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_SC0_VPP         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_SC1_VPP         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_TP_IN_29        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_049_PM_GPIO_049     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_048 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_GPIO_048        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_CHIP2POD_MOSTRT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_RMXP_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_EBI_ADDR_17     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_LED_LD_1        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_SC0_AUX2        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_SC1_AUX2        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_TP_IN_28        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_048_PM_GPIO_048     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_047 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_GPIO_047        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_CHIP2POD_MOVAL  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_RMXP_VALID      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_EBI_ADDR_16     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_LED_LD_0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_SC0_AUX1        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_SC1_AUX1        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_TP_IN_27        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_047_PM_GPIO_047     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_046 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_046_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_046_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_046_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_046_GPIO_046        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_046_POD2CHIP_MICLK  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_046_PPKT_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_046_EBI_ADDR_13     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_046_SPI_S_SS0B      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_046_POD2CHIP_MCLKI  5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_046_TP_IN_26        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_046_PM_GPIO_046     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_045 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_045_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_045_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_045_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_045_GPIO_045        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_045_POD2CHIP_MDI7   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_045_PPKT_DATA7      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_045_VO1_656_7       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_045_SC0_VPP         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_045_SC1_VPP         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_045_TP_IN_25        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_045_PM_GPIO_045     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_044 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_044_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_044_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_044_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_044_GPIO_044        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_044_POD2CHIP_MDI6   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_044_PPKT_DATA6      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_044_VO1_656_6       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_044_SC0_AUX2        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_044_SC1_AUX2        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_044_TP_IN_24        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_044_PM_GPIO_044     7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_12 - Pinmux control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_059 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_059_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_059_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_059_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_059_GPIO_059        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_059_PKT_DATA2       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_059_MTSIF1_CLK      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_059_ALT_TP_IN_22    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_059_PM_GPIO_059     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_058 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_058_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_058_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_058_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_058_GPIO_058        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_058_PKT_CLK2        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_058_MTSIF_ATS_INC   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_058_ALT_TP_IN_21    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_058_PM_GPIO_058     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_057 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_GPIO_057        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_CHIP2POD_MOCLK  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_RMXP_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_EBI_ADDR_12     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_LED_LD_10       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_I2S_CLK1        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_SPI_S_MISO      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_CHIP2POD_MCLKO  7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_ALT_TP_IN_20    8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_057_PM_GPIO_057     9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_056 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_056_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_056_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_056_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_056_GPIO_056        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_056_CHIP2POD_MDO7   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_056_RMXP_DATA7      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_056_EBI_ADDR_25     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_056_LED_LD_9        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_056_I2S_LR1         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_056_ALT_TP_IN_19    6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_056_PM_GPIO_056     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_055 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_055_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_055_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_055_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_055_GPIO_055        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_055_CHIP2POD_MDO6   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_055_RMXP_DATA6      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_055_EBI_ADDR_24     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_055_LED_LD_8        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_055_I2S_DATA1       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_055_ALT_TP_IN_18    6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_055_PM_GPIO_055     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_054 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_054_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_054_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_054_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_054_GPIO_054        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_054_CHIP2POD_MDO5   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_054_RMXP_DATA5      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_054_EBI_ADDR_23     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_054_LED_LD_7        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_054_ALT_TP_IN_17    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_054_PM_GPIO_054     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_053 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_053_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_053_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_053_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_053_GPIO_053        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_053_CHIP2POD_MDO4   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_053_RMXP_DATA4      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_053_EBI_ADDR_22     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_053_LED_LD_6        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_053_ALT_TP_IN_16    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_053_PM_GPIO_053     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_052 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_052_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_052_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_052_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_052_GPIO_052        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_052_CHIP2POD_MDO3   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_052_RMXP_DATA3      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_052_EBI_ADDR_21     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_052_LED_LD_5        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_052_PM_GPIO_052     5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_13 - Pinmux control register 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_067 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_GPIO_067        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_PKT_ERROR4      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_MTSIF_ATS_INC   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_UART_CTS_2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_UART_RXD_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_MII0_CRS        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_TTX1_REQ        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_ALT_TP_IN_29    7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_067_PM_GPIO_067     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_066 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_066_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_066_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_066_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_066_GPIO_066        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_066_PKT_SYNC4       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_066_MTSIF1_DATA4    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_066_ALT_TP_IN_28    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_066_PM_GPIO_066     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_065 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_065_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_065_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_065_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_065_GPIO_065        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_065_PKT_DATA4       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_065_MTSIF1_DATA3    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_065_PM_GPIO_065     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_064 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_064_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_064_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_064_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_064_GPIO_064        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_064_PKT_CLK4        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_064_MTSIF1_DATA2    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_064_ALT_TP_IN_26    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_064_PM_GPIO_064     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_063 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_063_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_063_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_063_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_063_GPIO_063        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_063_PKT_VALID3      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_063_MTSIF1_VALID    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_063_UART_TXD_2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_063_UART_RTS_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_063_MII1_COL        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_063_TP_OUT_31       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_063_PM_GPIO_063     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_062 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_062_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_062_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_062_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_062_GPIO_062        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_062_PKT_ERROR3      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_062_MTSIF1_DATA1    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_062_UART_RXD_2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_062_UART_CTS_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_062_MII1_CRS        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_062_ALT_TP_IN_25    6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_062_PM_GPIO_062     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_061 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_061_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_061_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_061_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_061_GPIO_061        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_061_PKT_CLK3        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_061_MTSIF1_SYNC     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_061_ALT_TP_IN_24    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_061_PM_GPIO_061     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_060 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_060_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_060_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_060_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_060_GPIO_060        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_060_PKT_SYNC2       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_060_MTSIF1_DATA0    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_060_ALT_TP_IN_23    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_060_PM_GPIO_060     4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_14 - Pinmux control register 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_075 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_075_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_075_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_075_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_075_GPIO_075        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_075_PKT_ERROR6      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_075_SDIO0_CLK       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_075_RMX_PAUSE0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_075_PWM_2           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_075_TP_IN_10        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_075_PM_GPIO_075     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_074 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_074_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_074_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_074_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_074_GPIO_074        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_074_PKT_SYNC6       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_074_SDIO0_PWR0      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_074_SC0_VPP         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_074_SC1_VPP         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_074_PM_GPIO_074     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_073 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_073_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_073_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_073_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_073_GPIO_073        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_073_PKT_DATA6       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_073_SDIO0_WPROT     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_073_SC0_AUX2        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_073_SC1_AUX2        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_073_PM_GPIO_073     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_072 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_072_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_072_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_072_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_072_GPIO_072        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_072_PKT_CLK6        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_072_SDIO0_CMD       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_072_SC0_AUX1        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_072_SC1_AUX1        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_072_ALT_TP_OUT_14   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_072_PM_GPIO_072     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_071 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_071_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_071_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_071_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_071_GPIO_071        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_071_PKT_SYNC5       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_071_MTSIF1_DATA5    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_071_ALT_TP_OUT_13   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_071_PM_GPIO_071     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_070 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_070_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_070_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_070_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_070_GPIO_070        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_070_PKT_DATA5       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_070_MTSIF1_DATA7    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_070_ALT_TP_IN_31    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_070_PM_GPIO_070     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_069 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_069_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_069_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_069_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_069_GPIO_069        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_069_PKT_CLK5        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_069_MTSIF1_DATA6    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_069_ALT_TP_IN_30    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_069_PM_GPIO_069     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_068 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_GPIO_068        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_PKT_VALID4      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_MTSIF_ATS_RST   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_UART_RTS_2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_UART_TXD_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_MII0_COL        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_TTX1_DATA       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_TP_OUT_27       7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_068_PM_GPIO_068     8
+
+/***************************************************************************
+ *PIN_MUX_CTRL_15 - Pinmux control register 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_083 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_083_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_083_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_083_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_083_GPIO_083        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_083_CODEC_SCLK      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_083_SC1_AUX1        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_083_SC0_AUX1        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_083_LED_LD_9        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_083_SPI_M_SS1B      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_083_TP_IN_16        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_083_PM_GPIO_083     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_082 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_082_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_082_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_082_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_082_GPIO_082        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_082_CODEC_SDI       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_082_SC_EXT_CLK      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_082_EXT_IRQB_5      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_082_LED_LD_8        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_082_SPI_M_SS1B      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_082_PM_GPIO_082     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_081 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_081_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_081_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_081_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_081_GPIO_081        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_081_PKT_VALID7      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_081_SDIO0_LED       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_081_EXT_IRQB_4      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_081_PWM_3           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_081_UART_TXD_0      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_081_ALT_TP_OUT_11   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_081_PM_GPIO_081     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_080 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_080_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_080_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_080_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_080_GPIO_080        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_080_PKT_ERROR7      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_080_SDIO0_PRES      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_080_EXT_IRQB_3      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_080_UART_CTS_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_080_UART_RXD_0      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_080_TP_IN_04        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_080_PM_GPIO_080     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_079 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_079_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_079_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_079_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_079_GPIO_079        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_079_PKT_SYNC7       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_079_SDIO0_DAT3      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_079_EXT_IRQB_2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_079_UART_RTS_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_079_TP_IN_03        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_079_PM_GPIO_079     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_078 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_078_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_078_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_078_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_078_GPIO_078        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_078_PKT_DATA7       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_078_SDIO0_DAT2      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_078_EXT_IRQB_1      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_078_UART_TXD_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_078_PM_GPIO_078     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_077 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_077_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_077_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_077_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_077_GPIO_077        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_077_PKT_CLK7        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_077_SDIO0_DAT1      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_077_EXT_IRQB_0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_077_UART_RXD_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_077_TP_IN_00        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_077_PM_GPIO_077     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_076 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_076_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_076_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_076_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_076_GPIO_076        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_076_PKT_VALID6      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_076_SDIO0_DAT0      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_076_RMX_PAUSE1      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_076_IR_IN1          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_076_TP_IN_11        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_076_PM_GPIO_076     6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_16 - Pinmux control register 16
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_091 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_091_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_091_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_091_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_091_GPIO_091        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_091_SC0_RST         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_091_PM_GPIO_091     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_090 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_090_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_090_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_090_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_090_GPIO_090        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_090_SC0_CLK         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_090_PWM_3           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_090_PM_GPIO_090     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_089 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_089_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_089_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_089_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_089_GPIO_089        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_089_SC0_IO          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_089_PWM_2           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_089_PM_GPIO_089     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_088 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_088_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_088_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_088_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_088_GPIO_088        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_088_MOCA_LINK       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_088_MOCA_ACTIVITY   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_088_MII1_TX_ERR     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_088_TP_IN_12        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_088_PM_GPIO_088     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_087 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_087_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_087_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_087_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_087_GPIO_087        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_087_MOCA_ACTIVITY   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_087_MOCA_LINK       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_087_MII1_RX_ERR     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_087_ALT_TP_OUT_10   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_087_PM_GPIO_087     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_086 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_086_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_086_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_086_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_086_GPIO_086        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_086_CODEC_SDO       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_086_IR_IN1          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_086_ALT_TP_OUT_09   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_086_PM_GPIO_086     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_085 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_085_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_085_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_085_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_085_GPIO_085        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_085_CODEC_MCLK      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_085_SC1_VPP         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_085_SC0_VPP         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_085_SPI_M_SS2B      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_085_ALT_TP_OUT_08   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_085_PM_GPIO_085     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_084 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_084_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_084_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_084_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_084_GPIO_084        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_084_CODEC_FSYNCB    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_084_SC1_AUX2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_084_SC0_AUX2        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_084_LED_LD_10       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_084_ALT_TP_IN_27    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_084_PM_GPIO_084     6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_17 - Pinmux control register 17
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_103 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_103_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_103_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_103_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_103_GPIO_103        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_103_VO0_656_1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_103_VO1_656_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_103_RMX_DATA0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_103_TP_OUT_04       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_103_PM_GPIO_103     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_098 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_098_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_098_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_098_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_098_GPIO_098        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_098_SC1_VCC         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_098_PM_GPIO_098     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_097 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_097_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_097_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_097_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_097_GPIO_097        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_097_SC1_PRES        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_097_PM_GPIO_097     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_096 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_096_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_096_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_096_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_096_GPIO_096        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_096_SC1_RST         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_096_ALT_TP_OUT_15   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_096_PM_GPIO_096     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_095 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_095_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_095_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_095_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_095_GPIO_095        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_095_SC1_CLK         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_095_ALT_TP_OUT_12   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_095_PM_GPIO_095     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_094 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_094_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_094_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_094_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_094_GPIO_094        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_094_SC1_IO          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_094_PM_GPIO_094     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_093 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_093_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_093_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_093_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_093_GPIO_093        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_093_SC0_VCC         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_093_PM_GPIO_093     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_092 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_092_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_092_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_092_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_092_GPIO_092        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_092_SC0_PRES        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_092_PM_GPIO_092     2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_18 - Pinmux control register 18
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: sgpio_00 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_00_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_00_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_00_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_00_SGPIO_00        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_00_BSC_M2_SCL      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_110 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_110_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_110_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_110_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_110_GPIO_110        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_110_VO0_656_CLK     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_110_VO1_656_CLK     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_110_BT_CLK_26087    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_110_LED_LD_15       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_110_TP_OUT_11       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_110_PM_GPIO_110     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_109 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_109_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_109_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_109_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_109_GPIO_109        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_109_VO0_656_7       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_109_VO1_656_7       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_109_PWM_2           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_109_LED_LD_14       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_109_TP_OUT_10       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_109_PM_GPIO_109     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_108 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_108_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_108_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_108_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_108_GPIO_108        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_108_VO0_656_6       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_108_VO1_656_6       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_108_UHF_LNA_PWRDN   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_108_LED_LD_13       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_108_TP_OUT_09       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_108_PM_GPIO_108     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_107 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_107_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_107_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_107_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_107_GPIO_107        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_107_VO0_656_5       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_107_VO1_656_5       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_107_RMX_SYNC1       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_107_TP_OUT_08       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_107_PM_GPIO_107     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_106 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_106_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_106_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_106_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_106_GPIO_106        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_106_VO0_656_4       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_106_VO1_656_4       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_106_RMX_DATA1       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_106_TP_OUT_07       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_106_PM_GPIO_106     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_105 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_105_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_105_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_105_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_105_GPIO_105        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_105_VO0_656_3       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_105_VO1_656_3       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_105_RMX_CLK1        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_105_TP_OUT_06       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_105_PM_GPIO_105     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_104 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_104_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_104_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_104_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_104_GPIO_104        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_104_VO0_656_2       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_104_VO1_656_2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_104_RMX_SYNC0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_104_TP_OUT_05       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_104_PM_GPIO_104     5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_19 - Pinmux control register 19
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_reserved0_MASK           0xfffff000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_reserved0_SHIFT          12
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: sgpio_03 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_03_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_03_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_03_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_03_SGPIO_03        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_03_BSC_M3_SDA      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_03_EMAC0_IRQ       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_03_EMAC1_IRQ       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: sgpio_02 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_02_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_02_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_02_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_02_SGPIO_02        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_02_BSC_M3_SCL      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_02_EMAC0_IRQ       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_02_EMAC1_IRQ       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: sgpio_01 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_01_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_01_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_01_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_01_SGPIO_01        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_sgpio_01_BSC_M2_SDA      1
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_11_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_11_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_11_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_11_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_11_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_11_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_10_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_10_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_10_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_10_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_10_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_10_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_09_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_09_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_09_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_09_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_09_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_09_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_08_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_08_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_08_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_08_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_08_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_08_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_07_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_06_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_05_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_04_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_03_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_02_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_01_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_00_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [05:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x0000003f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_10_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_10_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_10_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_10_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_10_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_10_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_09_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_09_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_09_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_09_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_09_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_09_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_08_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_08_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_08_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_08_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_08_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_08_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_07_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_07_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_07_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_07_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_07_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_07_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_06_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_06_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_06_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_06_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_06_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_06_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_05_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_05_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_05_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_05_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_05_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_05_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_04_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_04_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_04_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_04_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_04_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_04_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_03_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_03_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_03_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_03_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_03_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_03_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_02_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_02_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_02_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_02_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_02_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_02_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_01_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_01_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_01_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_01_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_01_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_01_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_00_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_00_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_00_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_00_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_00_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_00_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_data_15_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_15_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_15_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_15_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_15_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_15_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_data_14_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_14_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_14_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_14_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_14_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_14_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_data_13_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_13_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_13_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_13_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_13_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_13_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_data_12_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_12_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_12_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_12_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_12_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_12_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_25_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_25_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_25_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_25_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_25_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_25_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_25_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_24_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_24_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_24_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_24_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_24_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_24_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_24_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_23_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_23_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_23_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_23_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_23_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_23_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_23_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_22_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_22_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_22_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_22_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_22_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_22_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_22_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_21_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_21_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_21_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_21_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_21_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_21_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_21_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_20_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_20_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_20_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_20_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_20_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_20_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_19_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_19_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_19_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_19_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_19_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_19_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_18_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_18_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_18_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_18_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_18_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_18_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_18_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_17_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_17_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_17_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_17_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_17_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_17_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_16_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_16_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_16_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_16_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_16_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_16_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_15_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_15_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_15_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_15_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_15_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_15_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_14_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_14_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_14_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_14_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_14_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_14_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_13_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_13_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_13_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_13_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_13_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_13_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_12_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_12_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_12_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_12_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_12_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_12_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_11_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_11_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_11_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_11_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_11_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_11_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_nand_rbb_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_dsb_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_tsb_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_rdb_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_we1b_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_we0b_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_rwb_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_cs5b_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs5b_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs5b_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs5b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs5b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs5b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs5b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_cs4b_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs4b_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs4b_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs4b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs4b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs4b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs4b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_cs3b_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs3b_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs3b_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs3b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs3b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs3b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs3b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_cs2b_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs2b_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs2b_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs2b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs2b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs2b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs2b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_cs1b_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs1b_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs1b_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs1b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs1b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs1b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs1b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_cs0b_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs0b_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs0b_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs0b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs0b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs0b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs0b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_addr_27_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_27_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_27_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_27_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_27_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_27_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_27_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_addr_26_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_26_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_26_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_26_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_26_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_26_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_26_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved0 [29:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_MASK        0x3ff00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_SHIFT       20
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: pcie_clkreqb_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_clkreqb_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_clkreqb_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_clkreqb_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_clkreqb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_clkreqb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_clkreqb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: pcie_rstb_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_rstb_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_rstb_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_rstb_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_rstb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_rstb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_rstb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: sdio1_clk_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_clk_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_clk_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_clk_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_clk_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_clk_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_clk_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: sdio1_cmd_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_cmd_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_cmd_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_cmd_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_cmd_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_cmd_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sdio1_cmd_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: sf_wpb_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_wpb_pad_ctrl_MASK  0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_wpb_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_wpb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_wpb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_wpb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_wpb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: sf_holdb_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_holdb_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_holdb_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_holdb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_holdb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_holdb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_holdb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: sf_mosi_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_mosi_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_mosi_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_mosi_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_mosi_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_mosi_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_mosi_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: sf_miso_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_miso_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_miso_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_miso_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_miso_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_miso_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_miso_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: sf_sck_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_sck_pad_ctrl_MASK  0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_sck_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_sck_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_sck_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_sck_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_sck_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_waitb_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_waitb_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_waitb_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_waitb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_waitb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_waitb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_waitb_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_011_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_011_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_011_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_011_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_011_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_011_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_011_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_010_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_010_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_010_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_010_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_010_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_010_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_010_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_009_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_009_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_009_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_009_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_009_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_009_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_009_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_008_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_008_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_008_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_008_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_008_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_008_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_008_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_007_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_007_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_007_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_007_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_007_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_007_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_007_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_006_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_006_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_006_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_006_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_006_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_006_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_006_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_005_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_005_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_005_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_005_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_005_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_005_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_005_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_004_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_004_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_004_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_004_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_004_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_004_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_004_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_003_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_003_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_003_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_003_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_003_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_003_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_003_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_002_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_002_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_002_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_002_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_002_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_002_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_002_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_001_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_000_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: reserved0 [05:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_MASK        0x0000003f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_026_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_026_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_026_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_026_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_026_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_026_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_026_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_025_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_025_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_025_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_025_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_025_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_025_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_025_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_024_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_024_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_024_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_024_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_024_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_024_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_024_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_023_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_023_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_023_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_023_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_023_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_023_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_023_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_022_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_022_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_022_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_022_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_022_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_022_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_022_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_021_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_021_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_021_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_021_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_021_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_021_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_021_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_020_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_020_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_020_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_020_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_020_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_020_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_020_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_019_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_019_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_019_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_019_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_019_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_019_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_019_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_018_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_018_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_018_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_018_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_018_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_018_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_018_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_017_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_017_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_017_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_017_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_017_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_017_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_017_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_016_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_015_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_014_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_013_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_012_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_012_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_012_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_012_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_012_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_012_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_012_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_041_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_041_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_041_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_041_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_041_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_041_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_041_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_040_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_040_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_040_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_040_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_040_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_040_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_040_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_039_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_039_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_039_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_039_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_039_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_039_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_039_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_038_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_038_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_038_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_038_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_038_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_038_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_038_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_037_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_037_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_037_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_037_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_037_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_037_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_037_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_036_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_036_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_036_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_036_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_036_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_036_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_036_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_035_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_035_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_035_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_035_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_035_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_035_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_035_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_034_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_034_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_034_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_034_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_034_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_034_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_034_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_033_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_033_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_033_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_033_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_033_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_033_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_033_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_032_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_032_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_032_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_032_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_032_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_032_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_032_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_031_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_030_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_029_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_028_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_027_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_056_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_056_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_056_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_056_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_056_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_056_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_056_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_055_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_055_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_055_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_055_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_055_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_055_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_055_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_054_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_054_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_054_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_054_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_054_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_054_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_054_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_053_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_053_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_053_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_053_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_053_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_053_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_053_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_052_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_052_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_052_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_052_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_052_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_052_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_052_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_051_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_051_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_051_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_051_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_051_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_051_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_051_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_050_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_050_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_050_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_050_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_050_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_050_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_050_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_049_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_049_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_049_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_049_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_049_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_049_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_049_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_048_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_048_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_048_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_048_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_048_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_048_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_048_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_047_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_047_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_047_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_047_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_047_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_047_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_047_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_046_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_045_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_044_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_043_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_042_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_9 - Pad pull-up/pull-down control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: spare_pad_ctrl_9 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_071_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_071_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_071_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_071_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_071_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_071_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_071_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_070_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_070_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_070_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_070_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_070_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_070_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_070_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_069_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_069_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_069_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_069_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_069_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_069_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_069_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_068_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_068_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_068_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_068_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_068_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_068_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_068_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_067_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_067_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_067_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_067_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_067_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_067_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_067_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_066_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_066_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_066_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_066_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_066_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_066_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_066_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_065_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_065_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_065_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_065_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_065_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_065_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_065_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_064_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_064_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_064_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_064_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_064_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_064_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_064_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_063_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_063_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_063_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_063_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_063_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_063_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_063_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_062_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_062_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_062_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_062_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_062_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_062_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_062_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_061_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_060_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_059_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_058_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_057_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_10 - Pad pull-up/pull-down control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: spare_pad_ctrl_10 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_086_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_086_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_086_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_086_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_086_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_086_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_086_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_085_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_085_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_085_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_085_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_085_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_085_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_085_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_084_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_084_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_084_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_084_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_084_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_084_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_084_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_083_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_083_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_083_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_083_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_083_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_083_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_083_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_082_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_082_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_082_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_082_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_082_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_082_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_082_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_081_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_081_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_081_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_081_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_081_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_081_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_081_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_080_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_080_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_080_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_080_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_080_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_080_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_080_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_079_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_079_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_079_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_079_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_079_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_079_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_079_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_078_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_078_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_078_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_078_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_078_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_078_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_078_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_077_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_077_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_077_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_077_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_077_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_077_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_077_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_076_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_075_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_074_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_073_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_072_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_072_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_072_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_072_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_072_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_072_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_072_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_11 - Pad pull-up/pull-down control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: spare_pad_ctrl_11 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: reserved0 [29:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved0_MASK       0x3f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved0_SHIFT      24
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_098_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_098_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_098_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_098_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_098_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_098_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_098_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_097_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_097_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_097_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_097_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_097_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_097_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_097_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_096_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_096_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_096_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_096_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_096_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_096_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_096_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_095_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_095_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_095_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_095_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_095_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_095_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_095_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_094_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_094_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_094_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_094_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_094_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_094_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_094_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_093_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_093_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_093_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_093_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_093_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_093_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_093_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_092_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_092_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_092_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_092_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_092_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_092_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_092_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_091_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_090_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_089_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_088_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_087_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_087_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_087_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_087_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_087_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_087_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_087_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_12 - Pad pull-up/pull-down control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: spare_pad_ctrl_12 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: reserved0 [29:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_reserved0_MASK       0x3fffffff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_reserved0_SHIFT      0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_13 - Pad pull-up/pull-down control register 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_13 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_reserved0_MASK       0xfffffff0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_reserved0_SHIFT      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_13 :: spare_pad_ctrl_13 [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_13 :: reserved1 [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_reserved1_MASK       0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_reserved1_SHIFT      0
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_324_clk [31:31] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_324_clk_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_324_clk_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_324_clk_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_216_clk [30:30] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_216_clk_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_216_clk_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_216_clk_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_108_clk [29:29] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_108_clk_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_108_clk_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_108_clk_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_mips_clk [28:28] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_mips_clk_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_mips_clk_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_mips_clk_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_098 [27:27] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_098_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_098_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_098_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_097 [26:26] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_097_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_097_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_097_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_089 [25:25] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_089_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_089_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_089_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_082 [24:24] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_082_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_082_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_082_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_074 [23:23] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_074_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_074_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_074_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_073 [22:22] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_073_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_073_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_073_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_065 [21:21] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_065_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_065_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_065_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_036 [20:20] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_036_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_036_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_036_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_032 [19:19] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_032_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_032_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_032_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_024 [18:18] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_024_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_024_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_024_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_023 [17:17] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_023_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_023_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_023_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_019 [16:16] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_019_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_019_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_019_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_015 [15:15] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_015_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_015_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_015_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sf_wpb [14:14] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_wpb_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_wpb_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_wpb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sf_holdb [13:13] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_holdb_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_holdb_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_holdb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_waitb [12:12] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_waitb_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_waitb_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_waitb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_dsb [11:11] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_dsb_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_dsb_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_dsb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_tsb [10:10] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_tsb_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_tsb_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_tsb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_we0b [09:09] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_we0b_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_we0b_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_we0b_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_rwb [08:08] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_rwb_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_rwb_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_rwb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_addr_15 [07:07] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_15_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_15_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_addr_14 [06:06] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_14_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_14_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_addr_13 [05:05] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_13_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_13_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_addr_12 [04:04] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_12_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_12_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_addr_11 [03:03] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_11_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_11_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_addr_10 [02:02] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_10_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_10_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_addr_09 [01:01] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_09_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_09_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_09_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_addr_08 [00:00] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_08_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_08_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_addr_08_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_CTRL - Reset control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0xfffffffe
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               1
+
+/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT   0x00000000
+
+/***************************************************************************
+ *RESET_SOURCE_ENABLE - Reset source enable
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK       0xfffffc00
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT      10
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_MASTER_RESET - Software master reset
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK           0xfffffffe
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT          1
+
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HW_RESET_EXTENSION - Hardware reset extension
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_MONITOR - Reset Monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT  7
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT   6
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT   4
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset history
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:18] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xfffc0000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            18
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [17:17] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 17
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [16:16] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 16
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [15:15] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 15
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [14:14] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 14
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_reset [13:13] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_MASK    0x00002000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT   13
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_reset [12:12] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT    12
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [11:11] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK        0x00000800
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT       11
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: scpu_ejtag_reset [10:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_MASK      0x00000400
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_SHIFT     10
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK       0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT      9
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 8
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 7
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 6
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_1_hot_boot_reset [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_0_hot_boot_reset [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_SHIFT 4
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0
+
+/***************************************************************************
+ *SW_INIT_0_SET - Software init 0 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved0_MASK             0xc0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved0_SHIFT            30
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_MASK          0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_MASK          0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_SHIFT         28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_MASK        0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_SHIFT       27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK        0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT       26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_MASK          0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_SHIFT         25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK          0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK   0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT  23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_MASK          0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_SHIFT         22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK          0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT         21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc1_sw_init_MASK         0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc1_sw_init_SHIFT        20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc1_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK         0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT        19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK           0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT          18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga1_sw_init [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga1_sw_init_MASK        0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga1_sw_init_SHIFT       17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_MASK        0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_SHIFT       16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK           0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT          15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK           0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT          14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_MASK          0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_SHIFT         13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_MASK          0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_MASK        0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_SHIFT       11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT       10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK           0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT          9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK           0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK           0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT          6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: pcie_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie_sw_init_MASK          0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie_sw_init_SHIFT         5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: webcpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_start_sw_init_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_start_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_start_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: webcpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_sw_init_MASK        0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_sw_init_SHIFT       3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT   0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_CLEAR - Software init 0 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved0_MASK           0xc0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved0_SHIFT          30
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_MASK        0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_SHIFT       29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_MASK        0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_SHIFT       28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_MASK      0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_SHIFT     27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK      0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT     26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_MASK        0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_SHIFT       25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK        0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT       24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_MASK        0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_SHIFT       22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK        0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT       21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc1_sw_init_MASK       0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc1_sw_init_SHIFT      20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc1_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK       0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT      19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK         0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT        18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga1_sw_init [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga1_sw_init_MASK      0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga1_sw_init_SHIFT     17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga1_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_MASK      0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK         0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT        15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK         0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT        14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_MASK        0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_SHIFT       13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_MASK        0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_SHIFT       12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_MASK      0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_SHIFT     11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK      0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT     10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK         0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT        9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK         0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK         0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT        6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: pcie_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie_sw_init_MASK        0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie_sw_init_SHIFT       5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: webcpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_start_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_start_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_start_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: webcpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_sw_init_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_sw_init_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_STATUS - Software init 0 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved0_MASK          0xc0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved0_SHIFT         30
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_MASK       0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_SHIFT      29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_MASK       0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_SHIFT      28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_MASK       0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_SHIFT      25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK       0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_MASK       0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_SHIFT      22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK       0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT      21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc1_sw_init_MASK      0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc1_sw_init_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc1_sw_init_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK      0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT     19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK        0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT       18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga1_sw_init [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga1_sw_init_MASK     0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga1_sw_init_SHIFT    17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga1_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_MASK     0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_SHIFT    16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK        0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT       15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK        0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT       14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_MASK       0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_SHIFT      13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_MASK       0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK        0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: pcie_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie_sw_init_MASK       0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie_sw_init_SHIFT      5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: webcpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_start_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_start_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_start_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: webcpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_sw_init_MASK     0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_sw_init_SHIFT    3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT   2
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT       1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved0_MASK     0xc0000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved0_SHIFT    30
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_MASK  0x20000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_MASK  0x10000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_MASK  0x02000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK  0x01000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr1_sw_init_MASK  0x00400000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK  0x00200000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc1_sw_init_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc1_sw_init_SHIFT 20
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK   0x00040000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT  18
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga1_sw_init [17:17] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga1_sw_init_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga1_sw_init_SHIFT 17
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK   0x00008000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT  15
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK   0x00004000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT  14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_avd0_sw_init_MASK  0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_svd0_sw_init_MASK  0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK   0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT  9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK   0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT  8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT  6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: pcie_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_pcie_sw_init_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_pcie_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: webcpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_webcpu_start_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_webcpu_start_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: webcpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_webcpu_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_webcpu_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved0_SHIFT 30
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr1_sw_init_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc1_sw_init_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc1_sw_init_SHIFT 20
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga1_sw_init [17:17] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga1_sw_init_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga1_sw_init_SHIFT 17
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: pcie_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_pcie_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_pcie_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: webcpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_webcpu_start_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_webcpu_start_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: webcpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_webcpu_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_webcpu_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved0_MASK   0xc0000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved0_SHIFT  30
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr1_sw_init_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc1_sw_init_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc1_sw_init_SHIFT 20
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga1_sw_init [17:17] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga1_sw_init_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga1_sw_init_SHIFT 17
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: pcie_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_pcie_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_pcie_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: webcpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_webcpu_start_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_webcpu_start_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: webcpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_webcpu_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_webcpu_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_1_SET - Software init 1 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK             0xffffff80
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT            7
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: m2mc1_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_m2mc1_sw_init_MASK         0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_m2mc1_sw_init_SHIFT        5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_m2mc1_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sid_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_MASK           0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_SHIFT          4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: v3d_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_MASK       0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_SHIFT      3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: vice21_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice21_sw_init_MASK        0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice21_sw_init_SHIFT       2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice21_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: vice20_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice20_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice20_sw_init_SHIFT       1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice20_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_uhfr_sw_init_MASK          0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_uhfr_sw_init_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_uhfr_sw_init_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_CLEAR - Software init 1 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT          7
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: m2mc1_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_m2mc1_sw_init_MASK       0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_m2mc1_sw_init_SHIFT      5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_m2mc1_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sid_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_MASK         0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_SHIFT        4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: v3d_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_MASK     0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_SHIFT    3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: vice21_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice21_sw_init_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice21_sw_init_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice21_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: vice20_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice20_sw_init_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice20_sw_init_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice20_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_uhfr_sw_init_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_uhfr_sw_init_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_uhfr_sw_init_DEFAULT     0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_STATUS - Software init 1 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT         7
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK     0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT    6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: m2mc1_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_m2mc1_sw_init_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_m2mc1_sw_init_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_m2mc1_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sid_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_MASK        0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_SHIFT       4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: v3d_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: vice21_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice21_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice21_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice21_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: vice20_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice20_sw_init_MASK     0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice20_sw_init_SHIFT    1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice20_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_uhfr_sw_init_MASK       0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_uhfr_sw_init_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_uhfr_sw_init_DEFAULT    0x00000001
+
+/***************************************************************************
+ *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK     0xffffff80
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT    7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: m2mc1_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_m2mc1_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_m2mc1_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sid_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_MASK   0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_SHIFT  4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: v3d_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: vice21_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vice21_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vice21_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: vice20_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vice20_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vice20_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_uhfr_sw_init_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_uhfr_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xffffff80
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: m2mc1_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_m2mc1_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_m2mc1_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sid_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: v3d_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: vice21_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vice21_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vice21_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: vice20_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vice20_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vice20_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_uhfr_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK   0xffffff80
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT  7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: m2mc1_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_m2mc1_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_m2mc1_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sid_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: v3d_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: vice21_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vice21_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vice21_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: vice20_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vice20_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vice20_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_uhfr_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK  0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved0_SHIFT 30
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc1_sw_init_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc1_sw_init_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga1_sw_init [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga1_sw_init_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga1_sw_init_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: pcie_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie_sw_init_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: webcpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_start_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_start_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_start_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: webcpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xffffff80
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 7
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: m2mc1_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_m2mc1_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_m2mc1_sw_init_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_m2mc1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sid_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: v3d_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: vice21_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice21_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice21_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice21_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: vice20_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice20_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice20_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice20_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_uhfr_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_uhfr_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved0_SHIFT 30
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc1_sw_init_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc1_sw_init_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga1_sw_init [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga1_sw_init_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga1_sw_init_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: pcie_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie_sw_init_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: webcpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_start_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_start_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_start_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: webcpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xffffff80
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 7
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: m2mc1_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_m2mc1_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_m2mc1_sw_init_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_m2mc1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sid_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: v3d_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: vice21_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice21_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice21_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice21_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: vice20_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice20_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice20_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice20_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_uhfr_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_uhfr_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL - Spare control bits reserved for future use
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT         0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTRL - Test port control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SOFT_MODEM_TP 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_ICID_TP_OUT 14
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0  0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET1  1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU     2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SATA    3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SCPU    5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS     16
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK     17
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON     18
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     21
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE    22
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM    23
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC     25
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SVD0    27
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVD0    28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO     30
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA0  31
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA1  32
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     33
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0   35
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC1   36
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VICE20  37
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VICE21  38
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0    45
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB1    46
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MOCA    47
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_UHFR    50
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_V3D_TOP 54
+
+/***************************************************************************
+ *TEST_PORT_OUT_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_OUT_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TEST_PORT_IN_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EJTAG_INPUT_EN - EJTAG input bus enables
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xfffffc00
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           10
+
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [09:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x000003ff
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA0_CPU_ONE_HOT 4
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA1_CPU_ONE_HOT 8
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_VICE20_ARC0_ONE_HOT 16
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_VICE20_ARC1_ONE_HOT 32
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_VICE21_ARC0_ONE_HOT 64
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_VICE21_ARC1_ONE_HOT 128
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SCPU_CPU_ONE_HOT 256
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 512
+
+/***************************************************************************
+ *EJTAG_OUTPUT_SEL - EJTAG output select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         4
+
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [03:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x0000000f
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA0_CPU 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA1_CPU 3
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_VICE20_ARC0_CPU 4
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_VICE20_ARC1_CPU 5
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_VICE21_ARC0_CPU 6
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_VICE21_ARC1_CPU 7
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SCPU_CPU 8
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 9
+
+/***************************************************************************
+ *UART_ROUTER_SEL - UART Router select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK      0xf0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT     28
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AUDIO_FP1 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_OL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_IL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_BL   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AVD0_OL   6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AVD0_IL   7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SID       8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_VICE20_ARC0 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_VICE20_ARC1 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_VICE21_ARC0 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_VICE21_ARC1 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK      0x0f000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT     24
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AUDIO_FP1 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_OL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_IL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_BL   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AVD0_OL   6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AVD0_IL   7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SID       8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_VICE20_ARC0 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_VICE20_ARC1 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_VICE21_ARC0 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_VICE21_ARC1 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK      0x00f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AUDIO_FP1 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_OL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_IL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_BL   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AVD0_OL   6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AVD0_IL   7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SID       8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_VICE20_ARC0 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_VICE20_ARC1 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_VICE21_ARC0 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_VICE21_ARC1 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK      0x000f0000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AUDIO_FP1 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_OL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_IL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_BL   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AVD0_OL   6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AVD0_IL   7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SID       8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_VICE20_ARC0 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_VICE20_ARC1 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_VICE21_ARC0 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_VICE21_ARC1 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK      0x0000f000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AUDIO_FP1 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_OL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_IL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_BL   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AVD0_OL   6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AVD0_IL   7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SID       8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_VICE20_ARC0 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_VICE20_ARC1 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_VICE21_ARC0 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_VICE21_ARC1 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK      0x00000f00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_FP1 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_OL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_IL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_BL   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_OL   6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_IL   7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SID       8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_VICE20_ARC0 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_VICE20_ARC1 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_VICE21_ARC0 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_VICE21_ARC1 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_FP1 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_OL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_IL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_BL   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_OL   6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_IL   7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SID       8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_VICE20_ARC0 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_VICE20_ARC1 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_VICE21_ARC0 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_VICE21_ARC1 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK      0x0000000f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_FP1 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_OL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_IL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_BL   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_OL   6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_IL   7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SID       8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_VICE20_ARC0 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_VICE20_ARC1 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_VICE21_ARC0 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_VICE21_ARC1 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15
+
+/***************************************************************************
+ *VTRAP_CTRL - VTRAP Control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK                0xfffff000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT               12
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_threshold [11:11] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_threshold [10:10] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_threshold [09:09] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [08:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x000001f8
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 0x00000018
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_status_clear [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_status_clear [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_status_clear [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VTRAP_STATUS - VTRAP Status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK              0xfffffff8
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT             3
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_status [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_status [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_status [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SSP_CONFIG - Serial Slave Port configuration register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT        0x00000004
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT           0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT     0x00000001
+
+/***************************************************************************
+ *SERS_REV - SERS Revision Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16
+
+/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT     0x00000000
+
+/***************************************************************************
+ *SERS_CFG - SERS Configuration Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT                0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT           0x00000000
+
+/* union - case mapped_buffer_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0x00000000
+
+/* union - case cmd_fifo_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 0x0000001f
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 0x00000010
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT                 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x00404428
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0
+
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x00404448
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0
+
+
+/***************************************************************************
+ *RO_TEST_BLOCK_SEL - Block select for RO testmode
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xffffffe0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        5
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_pwenb [04:04] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DEFAULT  0x00000001
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_ENABLED  0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DISABLED 1
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [03:02] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MIN_LOAD 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MED_LOAD 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MAX_LOAD 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SVT_MIN_LOAD 3
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
+
+/***************************************************************************
+ *TEST_CONFIGURATION - Test configuration
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_timer.h b/include/linux/brcmstb/7435b0/bchp_timer.h
new file mode 100644
index 0000000..7819764
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_timer.h
@@ -0,0 +1,327 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:26 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_timer.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 4:20p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_TIMER_H__
+#define BCHP_TIMER_H__
+
+/***************************************************************************
+ *TIMER - Watchdog & Programmable Timers
+ ***************************************************************************/
+#define BCHP_TIMER_TIMER_IS                      0x004067c0 /* TIMER INTERRUPT STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE0                     0x004067c4 /* TIMER CPU INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_TIMER0_CTRL                   0x004067c8 /* TIMER0 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER1_CTRL                   0x004067cc /* TIMER1 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER2_CTRL                   0x004067d0 /* TIMER2 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER3_CTRL                   0x004067d4 /* TIMER3 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER0_STAT                   0x004067d8 /* TIMER0 STATUS REGISTER */
+#define BCHP_TIMER_TIMER1_STAT                   0x004067dc /* TIMER1 STATUS REGISTER */
+#define BCHP_TIMER_TIMER2_STAT                   0x004067e0 /* TIMER2 STATUS REGISTER */
+#define BCHP_TIMER_TIMER3_STAT                   0x004067e4 /* TIMER3 STATUS REGISTER */
+#define BCHP_TIMER_WDTIMEOUT                     0x004067e8 /* WATCHDOG TIMEOUT REGISTER */
+#define BCHP_TIMER_WDCMD                         0x004067ec /* WATCHDOG COMMAND REGISTER */
+#define BCHP_TIMER_WDCHIPRST_CNT                 0x004067f0 /* WATCHDOG CHIP RESET COUNT REGISTER */
+#define BCHP_TIMER_TIMER_IE1                     0x004067f8 /* TIMER PCI INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_WDCTRL                        0x004067fc /* WATCHDOG CONTROL REGISTER */
+
+/***************************************************************************
+ *TIMER_IS - TIMER INTERRUPT STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IS :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IS_reserved0_MASK                         0xffffffe0
+#define BCHP_TIMER_TIMER_IS_reserved0_SHIFT                        5
+
+/* TIMER :: TIMER_IS :: WDINT [04:04] */
+#define BCHP_TIMER_TIMER_IS_WDINT_MASK                             0x00000010
+#define BCHP_TIMER_TIMER_IS_WDINT_SHIFT                            4
+#define BCHP_TIMER_TIMER_IS_WDINT_DEFAULT                          0x00000000
+
+/* TIMER :: TIMER_IS :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IS_TMR3TO_MASK                            0x00000008
+#define BCHP_TIMER_TIMER_IS_TMR3TO_SHIFT                           3
+#define BCHP_TIMER_TIMER_IS_TMR3TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IS_TMR2TO_MASK                            0x00000004
+#define BCHP_TIMER_TIMER_IS_TMR2TO_SHIFT                           2
+#define BCHP_TIMER_TIMER_IS_TMR2TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IS_TMR1TO_MASK                            0x00000002
+#define BCHP_TIMER_TIMER_IS_TMR1TO_SHIFT                           1
+#define BCHP_TIMER_TIMER_IS_TMR1TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IS_TMR0TO_MASK                            0x00000001
+#define BCHP_TIMER_TIMER_IS_TMR0TO_SHIFT                           0
+#define BCHP_TIMER_TIMER_IS_TMR0TO_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *TIMER_IE0 - TIMER CPU INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE0 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE0_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE0_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE0 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_DEFAULT                     0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *TIMER0_CTRL - TIMER0 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER0_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER0_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER0_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER0_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER0_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER0_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER0_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER0_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER1_CTRL - TIMER1 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER1_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER1_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER1_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER1_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER1_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER1_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER1_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER1_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER2_CTRL - TIMER2 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER2_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER2_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER2_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER2_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER2_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER2_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER2_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER2_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER3_CTRL - TIMER3 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER3_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER3_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER3_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER3_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER3_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER3_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER3_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER3_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER0_STAT - TIMER0 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER0_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER0_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER0_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER1_STAT - TIMER1 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER1_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER1_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER1_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER2_STAT - TIMER2 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER2_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER2_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER2_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER3_STAT - TIMER3 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER3_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER3_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER3_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *WDTIMEOUT - WATCHDOG TIMEOUT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDTIMEOUT :: WDTIMEOUT_VAL [31:00] */
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_MASK                    0xffffffff
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *WDCMD - WATCHDOG COMMAND REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCMD :: WDCMD [31:00] */
+#define BCHP_TIMER_WDCMD_WDCMD_MASK                                0xffffffff
+#define BCHP_TIMER_WDCMD_WDCMD_SHIFT                               0
+#define BCHP_TIMER_WDCMD_WDCMD_DEFAULT                             0x00000000
+
+/***************************************************************************
+ *WDCHIPRST_CNT - WATCHDOG CHIP RESET COUNT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCHIPRST_CNT :: reserved0 [31:26] */
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_MASK                    0xfc000000
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_SHIFT                   26
+
+/* TIMER :: WDCHIPRST_CNT :: WDCHIPRST_CNT [25:00] */
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_MASK                0x03ffffff
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_SHIFT               0
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_DEFAULT             0x02ffffff
+
+/***************************************************************************
+ *TIMER_IE1 - TIMER PCI INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE1 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE1_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE1_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE1 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_DEFAULT                     0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *WDCTRL - WATCHDOG CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCTRL :: reserved0 [31:03] */
+#define BCHP_TIMER_WDCTRL_reserved0_MASK                           0xfffffff8
+#define BCHP_TIMER_WDCTRL_reserved0_SHIFT                          3
+
+/* TIMER :: WDCTRL :: WD_COUNT_MODE [02:02] */
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_MASK                       0x00000004
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_SHIFT                      2
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_DEFAULT                    0x00000000
+
+/* TIMER :: WDCTRL :: WD_EVENT_MODE [01:00] */
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_MASK                       0x00000003
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_SHIFT                      0
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_DEFAULT                    0x00000000
+
+#endif /* #ifndef BCHP_TIMER_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_uarta.h b/include/linux/brcmstb/7435b0/bchp_uarta.h
new file mode 100644
index 0000000..780a78e
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_uarta.h
@@ -0,0 +1,394 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:35 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_uarta.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 4:24p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTA_H__
+#define BCHP_UARTA_H__
+
+/***************************************************************************
+ *UARTA - UART A
+ ***************************************************************************/
+#define BCHP_UARTA_RBR                           0x00406b00 /* Receive Buffer Register */
+#define BCHP_UARTA_THR                           0x00406b00 /* Transmit Holding Register */
+#define BCHP_UARTA_DLH                           0x00406b04 /* Divisor Latch High */
+#define BCHP_UARTA_DLL                           0x00406b00 /* Divisor Latch Low */
+#define BCHP_UARTA_IER                           0x00406b04 /* Interrupt Enable Register */
+#define BCHP_UARTA_IIR                           0x00406b08 /* Interrupt Identity Register */
+#define BCHP_UARTA_FCR                           0x00406b08 /* FIFO Control Register */
+#define BCHP_UARTA_LCR                           0x00406b0c /* Line Control Register */
+#define BCHP_UARTA_MCR                           0x00406b10 /* Modem Control Register */
+#define BCHP_UARTA_LSR                           0x00406b14 /* Line Status Register */
+#define BCHP_UARTA_MSR                           0x00406b18 /* Modem Status Register */
+#define BCHP_UARTA_SCR                           0x00406b1c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTA :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTA_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_RBR_reserved0_SHIFT                             8
+
+/* UARTA :: RBR :: RBR [07:00] */
+#define BCHP_UARTA_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTA_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTA_RBR_RBR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTA :: THR :: reserved0 [31:08] */
+#define BCHP_UARTA_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_THR_reserved0_SHIFT                             8
+
+/* UARTA :: THR :: THR [07:00] */
+#define BCHP_UARTA_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTA_THR_THR_SHIFT                                   0
+#define BCHP_UARTA_THR_THR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTA :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTA_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLH_reserved0_SHIFT                             8
+
+/* UARTA :: DLH :: DLH [07:00] */
+#define BCHP_UARTA_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTA_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTA_DLH_DLH_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTA :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTA_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLL_reserved0_SHIFT                             8
+
+/* UARTA :: DLL :: DLL [07:00] */
+#define BCHP_UARTA_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTA_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTA_DLL_DLL_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTA :: IER :: reserved0 [31:08] */
+#define BCHP_UARTA_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IER_reserved0_SHIFT                             8
+
+/* UARTA :: IER :: PTIME [07:07] */
+#define BCHP_UARTA_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTA_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTA_IER_PTIME_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: reserved1 [06:04] */
+#define BCHP_UARTA_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTA_IER_reserved1_SHIFT                             4
+
+/* UARTA :: IER :: EDSSI [03:03] */
+#define BCHP_UARTA_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTA_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTA_IER_EDSSI_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: ELSI [02:02] */
+#define BCHP_UARTA_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTA_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTA_IER_ELSI_DEFAULT                                0x00000000
+
+/* UARTA :: IER :: ETBEI [01:01] */
+#define BCHP_UARTA_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTA_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTA_IER_ETBEI_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: ERBFI [00:00] */
+#define BCHP_UARTA_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTA_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTA_IER_ERBFI_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTA :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTA_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IIR_reserved0_SHIFT                             8
+
+/* UARTA :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTA_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTA_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTA_IIR_FIFOSE_DEFAULT                              0x00000000
+
+/* UARTA :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTA_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTA_IIR_reserved1_SHIFT                             4
+
+/* UARTA :: IIR :: IID [03:00] */
+#define BCHP_UARTA_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTA_IIR_IID_SHIFT                                   0
+#define BCHP_UARTA_IIR_IID_DEFAULT                                 0x00000001
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTA :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTA_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_FCR_reserved0_SHIFT                             8
+
+/* UARTA :: FCR :: RT [07:06] */
+#define BCHP_UARTA_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTA_FCR_RT_SHIFT                                    6
+#define BCHP_UARTA_FCR_RT_DEFAULT                                  0x00000000
+
+/* UARTA :: FCR :: TET [05:04] */
+#define BCHP_UARTA_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTA_FCR_TET_SHIFT                                   4
+#define BCHP_UARTA_FCR_TET_DEFAULT                                 0x00000000
+
+/* UARTA :: FCR :: DMAM [03:03] */
+#define BCHP_UARTA_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTA_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTA_FCR_DMAM_DEFAULT                                0x00000000
+
+/* UARTA :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTA_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTA_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTA_FCR_XFIFOR_DEFAULT                              0x00000000
+
+/* UARTA :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTA_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTA_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTA_FCR_RFIFOR_DEFAULT                              0x00000000
+
+/* UARTA :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTA_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTA_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTA_FCR_FIFOE_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTA :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTA_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LCR_reserved0_SHIFT                             8
+
+/* UARTA :: LCR :: DLAB [07:07] */
+#define BCHP_UARTA_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTA_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTA_LCR_DLAB_DEFAULT                                0x00000000
+
+/* UARTA :: LCR :: BC [06:06] */
+#define BCHP_UARTA_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTA_LCR_BC_SHIFT                                    6
+#define BCHP_UARTA_LCR_BC_DEFAULT                                  0x00000000
+
+/* UARTA :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTA_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTA_LCR_reserved1_SHIFT                             5
+
+/* UARTA :: LCR :: EPS [04:04] */
+#define BCHP_UARTA_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTA_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTA_LCR_EPS_DEFAULT                                 0x00000000
+
+/* UARTA :: LCR :: PEN [03:03] */
+#define BCHP_UARTA_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTA_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTA_LCR_PEN_DEFAULT                                 0x00000000
+
+/* UARTA :: LCR :: STOP [02:02] */
+#define BCHP_UARTA_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTA_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTA_LCR_STOP_DEFAULT                                0x00000000
+
+/* UARTA :: LCR :: DLS [01:00] */
+#define BCHP_UARTA_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTA_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTA_LCR_DLS_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTA :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTA_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTA_MCR_reserved0_SHIFT                             7
+
+/* UARTA :: MCR :: SIRE [06:06] */
+#define BCHP_UARTA_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTA_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTA_MCR_SIRE_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: AFCE [05:05] */
+#define BCHP_UARTA_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTA_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTA_MCR_AFCE_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: LB [04:04] */
+#define BCHP_UARTA_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTA_MCR_LB_SHIFT                                    4
+#define BCHP_UARTA_MCR_LB_DEFAULT                                  0x00000000
+
+/* UARTA :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTA_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTA_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTA_MCR_OUT2_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTA_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTA_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTA_MCR_OUT1_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: RTS [01:01] */
+#define BCHP_UARTA_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTA_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTA_MCR_RTS_DEFAULT                                 0x00000000
+
+/* UARTA :: MCR :: DTR [00:00] */
+#define BCHP_UARTA_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTA_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTA_MCR_DTR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTA :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTA_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LSR_reserved0_SHIFT                             8
+
+/* UARTA :: LSR :: RFE [07:07] */
+#define BCHP_UARTA_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTA_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTA_LSR_RFE_DEFAULT                                 0x00000000
+
+/* UARTA :: LSR :: TEMT [06:06] */
+#define BCHP_UARTA_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTA_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTA_LSR_TEMT_DEFAULT                                0x00000001
+
+/* UARTA :: LSR :: THRE [05:05] */
+#define BCHP_UARTA_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTA_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTA_LSR_THRE_DEFAULT                                0x00000001
+
+/* UARTA :: LSR :: BI [04:04] */
+#define BCHP_UARTA_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTA_LSR_BI_SHIFT                                    4
+#define BCHP_UARTA_LSR_BI_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: FE [03:03] */
+#define BCHP_UARTA_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTA_LSR_FE_SHIFT                                    3
+#define BCHP_UARTA_LSR_FE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: PE [02:02] */
+#define BCHP_UARTA_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTA_LSR_PE_SHIFT                                    2
+#define BCHP_UARTA_LSR_PE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: OE [01:01] */
+#define BCHP_UARTA_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTA_LSR_OE_SHIFT                                    1
+#define BCHP_UARTA_LSR_OE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: DR [00:00] */
+#define BCHP_UARTA_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTA_LSR_DR_SHIFT                                    0
+#define BCHP_UARTA_LSR_DR_DEFAULT                                  0x00000000
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTA :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTA_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_MSR_reserved0_SHIFT                             8
+
+/* UARTA :: MSR :: DCD [07:07] */
+#define BCHP_UARTA_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTA_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTA_MSR_DCD_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: RI [06:06] */
+#define BCHP_UARTA_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTA_MSR_RI_SHIFT                                    6
+#define BCHP_UARTA_MSR_RI_DEFAULT                                  0x00000000
+
+/* UARTA :: MSR :: DSR [05:05] */
+#define BCHP_UARTA_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTA_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTA_MSR_DSR_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: CTS [04:04] */
+#define BCHP_UARTA_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTA_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTA_MSR_CTS_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: DDCD [03:03] */
+#define BCHP_UARTA_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTA_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTA_MSR_DDCD_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: TERI [02:02] */
+#define BCHP_UARTA_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTA_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTA_MSR_TERI_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: DDSR [01:01] */
+#define BCHP_UARTA_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTA_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTA_MSR_DDSR_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: DCTS [00:00] */
+#define BCHP_UARTA_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTA_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTA_MSR_DCTS_DEFAULT                                0x00000000
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTA :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTA_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_SCR_reserved0_SHIFT                             8
+
+/* UARTA :: SCR :: SCR [07:00] */
+#define BCHP_UARTA_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTA_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTA_SCR_SCR_DEFAULT                                 0x00000000
+
+#endif /* #ifndef BCHP_UARTA_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_uartb.h b/include/linux/brcmstb/7435b0/bchp_uartb.h
new file mode 100644
index 0000000..72fc9a6
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_uartb.h
@@ -0,0 +1,391 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Jul 20 15:43:17 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTB_H__
+#define BCHP_UARTB_H__
+
+/***************************************************************************
+ *UARTB - UART B
+ ***************************************************************************/
+#define BCHP_UARTB_RBR                           0x00406b40 /* Receive Buffer Register */
+#define BCHP_UARTB_THR                           0x00406b40 /* Transmit Holding Register */
+#define BCHP_UARTB_DLH                           0x00406b44 /* Divisor Latch High */
+#define BCHP_UARTB_DLL                           0x00406b40 /* Divisor Latch Low */
+#define BCHP_UARTB_IER                           0x00406b44 /* Interrupt Enable Register */
+#define BCHP_UARTB_IIR                           0x00406b48 /* Interrupt Identity Register */
+#define BCHP_UARTB_FCR                           0x00406b48 /* FIFO Control Register */
+#define BCHP_UARTB_LCR                           0x00406b4c /* Line Control Register */
+#define BCHP_UARTB_MCR                           0x00406b50 /* Modem Control Register */
+#define BCHP_UARTB_LSR                           0x00406b54 /* Line Status Register */
+#define BCHP_UARTB_MSR                           0x00406b58 /* Modem Status Register */
+#define BCHP_UARTB_SCR                           0x00406b5c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTB :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTB_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_RBR_reserved0_SHIFT                             8
+
+/* UARTB :: RBR :: RBR [07:00] */
+#define BCHP_UARTB_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTB_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTB_RBR_RBR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTB :: THR :: reserved0 [31:08] */
+#define BCHP_UARTB_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_THR_reserved0_SHIFT                             8
+
+/* UARTB :: THR :: THR [07:00] */
+#define BCHP_UARTB_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTB_THR_THR_SHIFT                                   0
+#define BCHP_UARTB_THR_THR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTB :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTB_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_DLH_reserved0_SHIFT                             8
+
+/* UARTB :: DLH :: DLH [07:00] */
+#define BCHP_UARTB_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTB_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTB_DLH_DLH_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTB :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTB_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_DLL_reserved0_SHIFT                             8
+
+/* UARTB :: DLL :: DLL [07:00] */
+#define BCHP_UARTB_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTB_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTB_DLL_DLL_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTB :: IER :: reserved0 [31:08] */
+#define BCHP_UARTB_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_IER_reserved0_SHIFT                             8
+
+/* UARTB :: IER :: PTIME [07:07] */
+#define BCHP_UARTB_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTB_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTB_IER_PTIME_DEFAULT                               0x00000000
+
+/* UARTB :: IER :: reserved1 [06:04] */
+#define BCHP_UARTB_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTB_IER_reserved1_SHIFT                             4
+
+/* UARTB :: IER :: EDSSI [03:03] */
+#define BCHP_UARTB_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTB_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTB_IER_EDSSI_DEFAULT                               0x00000000
+
+/* UARTB :: IER :: ELSI [02:02] */
+#define BCHP_UARTB_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTB_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTB_IER_ELSI_DEFAULT                                0x00000000
+
+/* UARTB :: IER :: ETBEI [01:01] */
+#define BCHP_UARTB_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTB_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTB_IER_ETBEI_DEFAULT                               0x00000000
+
+/* UARTB :: IER :: ERBFI [00:00] */
+#define BCHP_UARTB_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTB_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTB_IER_ERBFI_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTB :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTB_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_IIR_reserved0_SHIFT                             8
+
+/* UARTB :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTB_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTB_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTB_IIR_FIFOSE_DEFAULT                              0x00000000
+
+/* UARTB :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTB_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTB_IIR_reserved1_SHIFT                             4
+
+/* UARTB :: IIR :: IID [03:00] */
+#define BCHP_UARTB_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTB_IIR_IID_SHIFT                                   0
+#define BCHP_UARTB_IIR_IID_DEFAULT                                 0x00000001
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTB :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTB_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_FCR_reserved0_SHIFT                             8
+
+/* UARTB :: FCR :: RT [07:06] */
+#define BCHP_UARTB_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTB_FCR_RT_SHIFT                                    6
+#define BCHP_UARTB_FCR_RT_DEFAULT                                  0x00000000
+
+/* UARTB :: FCR :: TET [05:04] */
+#define BCHP_UARTB_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTB_FCR_TET_SHIFT                                   4
+#define BCHP_UARTB_FCR_TET_DEFAULT                                 0x00000000
+
+/* UARTB :: FCR :: DMAM [03:03] */
+#define BCHP_UARTB_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTB_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTB_FCR_DMAM_DEFAULT                                0x00000000
+
+/* UARTB :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTB_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTB_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTB_FCR_XFIFOR_DEFAULT                              0x00000000
+
+/* UARTB :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTB_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTB_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTB_FCR_RFIFOR_DEFAULT                              0x00000000
+
+/* UARTB :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTB_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTB_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTB_FCR_FIFOE_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTB :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTB_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_LCR_reserved0_SHIFT                             8
+
+/* UARTB :: LCR :: DLAB [07:07] */
+#define BCHP_UARTB_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTB_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTB_LCR_DLAB_DEFAULT                                0x00000000
+
+/* UARTB :: LCR :: BC [06:06] */
+#define BCHP_UARTB_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTB_LCR_BC_SHIFT                                    6
+#define BCHP_UARTB_LCR_BC_DEFAULT                                  0x00000000
+
+/* UARTB :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTB_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTB_LCR_reserved1_SHIFT                             5
+
+/* UARTB :: LCR :: EPS [04:04] */
+#define BCHP_UARTB_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTB_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTB_LCR_EPS_DEFAULT                                 0x00000000
+
+/* UARTB :: LCR :: PEN [03:03] */
+#define BCHP_UARTB_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTB_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTB_LCR_PEN_DEFAULT                                 0x00000000
+
+/* UARTB :: LCR :: STOP [02:02] */
+#define BCHP_UARTB_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTB_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTB_LCR_STOP_DEFAULT                                0x00000000
+
+/* UARTB :: LCR :: DLS [01:00] */
+#define BCHP_UARTB_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTB_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTB_LCR_DLS_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTB :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTB_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTB_MCR_reserved0_SHIFT                             7
+
+/* UARTB :: MCR :: SIRE [06:06] */
+#define BCHP_UARTB_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTB_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTB_MCR_SIRE_DEFAULT                                0x00000000
+
+/* UARTB :: MCR :: AFCE [05:05] */
+#define BCHP_UARTB_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTB_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTB_MCR_AFCE_DEFAULT                                0x00000000
+
+/* UARTB :: MCR :: LB [04:04] */
+#define BCHP_UARTB_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTB_MCR_LB_SHIFT                                    4
+#define BCHP_UARTB_MCR_LB_DEFAULT                                  0x00000000
+
+/* UARTB :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTB_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTB_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTB_MCR_OUT2_DEFAULT                                0x00000000
+
+/* UARTB :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTB_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTB_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTB_MCR_OUT1_DEFAULT                                0x00000000
+
+/* UARTB :: MCR :: RTS [01:01] */
+#define BCHP_UARTB_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTB_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTB_MCR_RTS_DEFAULT                                 0x00000000
+
+/* UARTB :: MCR :: DTR [00:00] */
+#define BCHP_UARTB_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTB_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTB_MCR_DTR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTB :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTB_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_LSR_reserved0_SHIFT                             8
+
+/* UARTB :: LSR :: RFE [07:07] */
+#define BCHP_UARTB_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTB_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTB_LSR_RFE_DEFAULT                                 0x00000000
+
+/* UARTB :: LSR :: TEMT [06:06] */
+#define BCHP_UARTB_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTB_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTB_LSR_TEMT_DEFAULT                                0x00000001
+
+/* UARTB :: LSR :: THRE [05:05] */
+#define BCHP_UARTB_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTB_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTB_LSR_THRE_DEFAULT                                0x00000001
+
+/* UARTB :: LSR :: BI [04:04] */
+#define BCHP_UARTB_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTB_LSR_BI_SHIFT                                    4
+#define BCHP_UARTB_LSR_BI_DEFAULT                                  0x00000000
+
+/* UARTB :: LSR :: FE [03:03] */
+#define BCHP_UARTB_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTB_LSR_FE_SHIFT                                    3
+#define BCHP_UARTB_LSR_FE_DEFAULT                                  0x00000000
+
+/* UARTB :: LSR :: PE [02:02] */
+#define BCHP_UARTB_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTB_LSR_PE_SHIFT                                    2
+#define BCHP_UARTB_LSR_PE_DEFAULT                                  0x00000000
+
+/* UARTB :: LSR :: OE [01:01] */
+#define BCHP_UARTB_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTB_LSR_OE_SHIFT                                    1
+#define BCHP_UARTB_LSR_OE_DEFAULT                                  0x00000000
+
+/* UARTB :: LSR :: DR [00:00] */
+#define BCHP_UARTB_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTB_LSR_DR_SHIFT                                    0
+#define BCHP_UARTB_LSR_DR_DEFAULT                                  0x00000000
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTB :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTB_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_MSR_reserved0_SHIFT                             8
+
+/* UARTB :: MSR :: DCD [07:07] */
+#define BCHP_UARTB_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTB_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTB_MSR_DCD_DEFAULT                                 0x00000000
+
+/* UARTB :: MSR :: RI [06:06] */
+#define BCHP_UARTB_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTB_MSR_RI_SHIFT                                    6
+#define BCHP_UARTB_MSR_RI_DEFAULT                                  0x00000000
+
+/* UARTB :: MSR :: DSR [05:05] */
+#define BCHP_UARTB_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTB_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTB_MSR_DSR_DEFAULT                                 0x00000000
+
+/* UARTB :: MSR :: CTS [04:04] */
+#define BCHP_UARTB_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTB_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTB_MSR_CTS_DEFAULT                                 0x00000000
+
+/* UARTB :: MSR :: DDCD [03:03] */
+#define BCHP_UARTB_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTB_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTB_MSR_DDCD_DEFAULT                                0x00000000
+
+/* UARTB :: MSR :: TERI [02:02] */
+#define BCHP_UARTB_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTB_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTB_MSR_TERI_DEFAULT                                0x00000000
+
+/* UARTB :: MSR :: DDSR [01:01] */
+#define BCHP_UARTB_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTB_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTB_MSR_DDSR_DEFAULT                                0x00000000
+
+/* UARTB :: MSR :: DCTS [00:00] */
+#define BCHP_UARTB_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTB_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTB_MSR_DCTS_DEFAULT                                0x00000000
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTB :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTB_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_SCR_reserved0_SHIFT                             8
+
+/* UARTB :: SCR :: SCR [07:00] */
+#define BCHP_UARTB_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTB_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTB_SCR_SCR_DEFAULT                                 0x00000000
+
+#endif /* #ifndef BCHP_UARTB_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_uartc.h b/include/linux/brcmstb/7435b0/bchp_uartc.h
new file mode 100644
index 0000000..c3b1165
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_uartc.h
@@ -0,0 +1,391 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Jul 20 15:43:16 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTC_H__
+#define BCHP_UARTC_H__
+
+/***************************************************************************
+ *UARTC - UART C
+ ***************************************************************************/
+#define BCHP_UARTC_RBR                           0x00406b80 /* Receive Buffer Register */
+#define BCHP_UARTC_THR                           0x00406b80 /* Transmit Holding Register */
+#define BCHP_UARTC_DLH                           0x00406b84 /* Divisor Latch High */
+#define BCHP_UARTC_DLL                           0x00406b80 /* Divisor Latch Low */
+#define BCHP_UARTC_IER                           0x00406b84 /* Interrupt Enable Register */
+#define BCHP_UARTC_IIR                           0x00406b88 /* Interrupt Identity Register */
+#define BCHP_UARTC_FCR                           0x00406b88 /* FIFO Control Register */
+#define BCHP_UARTC_LCR                           0x00406b8c /* Line Control Register */
+#define BCHP_UARTC_MCR                           0x00406b90 /* Modem Control Register */
+#define BCHP_UARTC_LSR                           0x00406b94 /* Line Status Register */
+#define BCHP_UARTC_MSR                           0x00406b98 /* Modem Status Register */
+#define BCHP_UARTC_SCR                           0x00406b9c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTC :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTC_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_RBR_reserved0_SHIFT                             8
+
+/* UARTC :: RBR :: RBR [07:00] */
+#define BCHP_UARTC_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTC_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTC_RBR_RBR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTC :: THR :: reserved0 [31:08] */
+#define BCHP_UARTC_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_THR_reserved0_SHIFT                             8
+
+/* UARTC :: THR :: THR [07:00] */
+#define BCHP_UARTC_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTC_THR_THR_SHIFT                                   0
+#define BCHP_UARTC_THR_THR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTC :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTC_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_DLH_reserved0_SHIFT                             8
+
+/* UARTC :: DLH :: DLH [07:00] */
+#define BCHP_UARTC_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTC_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTC_DLH_DLH_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTC :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTC_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_DLL_reserved0_SHIFT                             8
+
+/* UARTC :: DLL :: DLL [07:00] */
+#define BCHP_UARTC_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTC_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTC_DLL_DLL_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTC :: IER :: reserved0 [31:08] */
+#define BCHP_UARTC_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_IER_reserved0_SHIFT                             8
+
+/* UARTC :: IER :: PTIME [07:07] */
+#define BCHP_UARTC_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTC_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTC_IER_PTIME_DEFAULT                               0x00000000
+
+/* UARTC :: IER :: reserved1 [06:04] */
+#define BCHP_UARTC_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTC_IER_reserved1_SHIFT                             4
+
+/* UARTC :: IER :: EDSSI [03:03] */
+#define BCHP_UARTC_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTC_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTC_IER_EDSSI_DEFAULT                               0x00000000
+
+/* UARTC :: IER :: ELSI [02:02] */
+#define BCHP_UARTC_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTC_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTC_IER_ELSI_DEFAULT                                0x00000000
+
+/* UARTC :: IER :: ETBEI [01:01] */
+#define BCHP_UARTC_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTC_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTC_IER_ETBEI_DEFAULT                               0x00000000
+
+/* UARTC :: IER :: ERBFI [00:00] */
+#define BCHP_UARTC_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTC_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTC_IER_ERBFI_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTC :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTC_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_IIR_reserved0_SHIFT                             8
+
+/* UARTC :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTC_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTC_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTC_IIR_FIFOSE_DEFAULT                              0x00000000
+
+/* UARTC :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTC_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTC_IIR_reserved1_SHIFT                             4
+
+/* UARTC :: IIR :: IID [03:00] */
+#define BCHP_UARTC_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTC_IIR_IID_SHIFT                                   0
+#define BCHP_UARTC_IIR_IID_DEFAULT                                 0x00000001
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTC :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTC_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_FCR_reserved0_SHIFT                             8
+
+/* UARTC :: FCR :: RT [07:06] */
+#define BCHP_UARTC_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTC_FCR_RT_SHIFT                                    6
+#define BCHP_UARTC_FCR_RT_DEFAULT                                  0x00000000
+
+/* UARTC :: FCR :: TET [05:04] */
+#define BCHP_UARTC_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTC_FCR_TET_SHIFT                                   4
+#define BCHP_UARTC_FCR_TET_DEFAULT                                 0x00000000
+
+/* UARTC :: FCR :: DMAM [03:03] */
+#define BCHP_UARTC_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTC_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTC_FCR_DMAM_DEFAULT                                0x00000000
+
+/* UARTC :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTC_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTC_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTC_FCR_XFIFOR_DEFAULT                              0x00000000
+
+/* UARTC :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTC_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTC_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTC_FCR_RFIFOR_DEFAULT                              0x00000000
+
+/* UARTC :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTC_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTC_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTC_FCR_FIFOE_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTC :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTC_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_LCR_reserved0_SHIFT                             8
+
+/* UARTC :: LCR :: DLAB [07:07] */
+#define BCHP_UARTC_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTC_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTC_LCR_DLAB_DEFAULT                                0x00000000
+
+/* UARTC :: LCR :: BC [06:06] */
+#define BCHP_UARTC_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTC_LCR_BC_SHIFT                                    6
+#define BCHP_UARTC_LCR_BC_DEFAULT                                  0x00000000
+
+/* UARTC :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTC_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTC_LCR_reserved1_SHIFT                             5
+
+/* UARTC :: LCR :: EPS [04:04] */
+#define BCHP_UARTC_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTC_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTC_LCR_EPS_DEFAULT                                 0x00000000
+
+/* UARTC :: LCR :: PEN [03:03] */
+#define BCHP_UARTC_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTC_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTC_LCR_PEN_DEFAULT                                 0x00000000
+
+/* UARTC :: LCR :: STOP [02:02] */
+#define BCHP_UARTC_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTC_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTC_LCR_STOP_DEFAULT                                0x00000000
+
+/* UARTC :: LCR :: DLS [01:00] */
+#define BCHP_UARTC_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTC_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTC_LCR_DLS_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTC :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTC_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTC_MCR_reserved0_SHIFT                             7
+
+/* UARTC :: MCR :: SIRE [06:06] */
+#define BCHP_UARTC_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTC_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTC_MCR_SIRE_DEFAULT                                0x00000000
+
+/* UARTC :: MCR :: AFCE [05:05] */
+#define BCHP_UARTC_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTC_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTC_MCR_AFCE_DEFAULT                                0x00000000
+
+/* UARTC :: MCR :: LB [04:04] */
+#define BCHP_UARTC_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTC_MCR_LB_SHIFT                                    4
+#define BCHP_UARTC_MCR_LB_DEFAULT                                  0x00000000
+
+/* UARTC :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTC_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTC_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTC_MCR_OUT2_DEFAULT                                0x00000000
+
+/* UARTC :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTC_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTC_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTC_MCR_OUT1_DEFAULT                                0x00000000
+
+/* UARTC :: MCR :: RTS [01:01] */
+#define BCHP_UARTC_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTC_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTC_MCR_RTS_DEFAULT                                 0x00000000
+
+/* UARTC :: MCR :: DTR [00:00] */
+#define BCHP_UARTC_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTC_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTC_MCR_DTR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTC :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTC_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_LSR_reserved0_SHIFT                             8
+
+/* UARTC :: LSR :: RFE [07:07] */
+#define BCHP_UARTC_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTC_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTC_LSR_RFE_DEFAULT                                 0x00000000
+
+/* UARTC :: LSR :: TEMT [06:06] */
+#define BCHP_UARTC_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTC_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTC_LSR_TEMT_DEFAULT                                0x00000001
+
+/* UARTC :: LSR :: THRE [05:05] */
+#define BCHP_UARTC_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTC_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTC_LSR_THRE_DEFAULT                                0x00000001
+
+/* UARTC :: LSR :: BI [04:04] */
+#define BCHP_UARTC_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTC_LSR_BI_SHIFT                                    4
+#define BCHP_UARTC_LSR_BI_DEFAULT                                  0x00000000
+
+/* UARTC :: LSR :: FE [03:03] */
+#define BCHP_UARTC_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTC_LSR_FE_SHIFT                                    3
+#define BCHP_UARTC_LSR_FE_DEFAULT                                  0x00000000
+
+/* UARTC :: LSR :: PE [02:02] */
+#define BCHP_UARTC_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTC_LSR_PE_SHIFT                                    2
+#define BCHP_UARTC_LSR_PE_DEFAULT                                  0x00000000
+
+/* UARTC :: LSR :: OE [01:01] */
+#define BCHP_UARTC_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTC_LSR_OE_SHIFT                                    1
+#define BCHP_UARTC_LSR_OE_DEFAULT                                  0x00000000
+
+/* UARTC :: LSR :: DR [00:00] */
+#define BCHP_UARTC_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTC_LSR_DR_SHIFT                                    0
+#define BCHP_UARTC_LSR_DR_DEFAULT                                  0x00000000
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTC :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTC_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_MSR_reserved0_SHIFT                             8
+
+/* UARTC :: MSR :: DCD [07:07] */
+#define BCHP_UARTC_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTC_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTC_MSR_DCD_DEFAULT                                 0x00000000
+
+/* UARTC :: MSR :: RI [06:06] */
+#define BCHP_UARTC_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTC_MSR_RI_SHIFT                                    6
+#define BCHP_UARTC_MSR_RI_DEFAULT                                  0x00000000
+
+/* UARTC :: MSR :: DSR [05:05] */
+#define BCHP_UARTC_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTC_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTC_MSR_DSR_DEFAULT                                 0x00000000
+
+/* UARTC :: MSR :: CTS [04:04] */
+#define BCHP_UARTC_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTC_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTC_MSR_CTS_DEFAULT                                 0x00000000
+
+/* UARTC :: MSR :: DDCD [03:03] */
+#define BCHP_UARTC_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTC_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTC_MSR_DDCD_DEFAULT                                0x00000000
+
+/* UARTC :: MSR :: TERI [02:02] */
+#define BCHP_UARTC_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTC_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTC_MSR_TERI_DEFAULT                                0x00000000
+
+/* UARTC :: MSR :: DDSR [01:01] */
+#define BCHP_UARTC_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTC_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTC_MSR_DDSR_DEFAULT                                0x00000000
+
+/* UARTC :: MSR :: DCTS [00:00] */
+#define BCHP_UARTC_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTC_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTC_MSR_DCTS_DEFAULT                                0x00000000
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTC :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTC_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_SCR_reserved0_SHIFT                             8
+
+/* UARTC :: SCR :: SCR [07:00] */
+#define BCHP_UARTC_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTC_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTC_SCR_SCR_DEFAULT                                 0x00000000
+
+#endif /* #ifndef BCHP_UARTC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_usb1_ctrl.h b/include/linux/brcmstb/7435b0/bchp_usb1_ctrl.h
new file mode 100644
index 0000000..0f75136
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_usb1_ctrl.h
@@ -0,0 +1,682 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Jul 20 15:43:14 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB1_CTRL_H__
+#define BCHP_USB1_CTRL_H__
+
+/***************************************************************************
+ *USB1_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB1_CTRL_SETUP                     0x00490200 /* Setup Register */
+#define BCHP_USB1_CTRL_PLL_CTL                   0x00490204 /* PLL Control Register */
+#define BCHP_USB1_CTRL_FLADJ_VALUE               0x00490208 /* Frame Adjust Value */
+#define BCHP_USB1_CTRL_EBRIDGE                   0x0049020c /* Control Register for EHCI Bridge */
+#define BCHP_USB1_CTRL_OBRIDGE                   0x00490210 /* Control Register for OHCI Bridge */
+#define BCHP_USB1_CTRL_MDIO                      0x00490214 /* MDIO Interface Programming Register */
+#define BCHP_USB1_CTRL_MDIO2                     0x00490218 /* MDIO Interface Read Register */
+#define BCHP_USB1_CTRL_TEST_PORT_CTL             0x0049021c /* Test Port Control Register */
+#define BCHP_USB1_CTRL_USB_SIMCTL                0x00490220 /* Simulation Register */
+#define BCHP_USB1_CTRL_USB_TESTCTL               0x00490224 /* Throutput Test Control */
+#define BCHP_USB1_CTRL_USB_TESTMON               0x00490228 /* Throughput Test Monitor */
+#define BCHP_USB1_CTRL_UTMI_CTL_1                0x0049022c /* UTMI Control Register */
+#define BCHP_USB1_CTRL_UTMI_CTL_2                0x00490230 /* UTMI Control 2 Register */
+#define BCHP_USB1_CTRL_SPARE1                    0x00490234 /* Spare1 Register for future use */
+#define BCHP_USB1_CTRL_SPARE2                    0x00490238 /* Spare2 Register for future use */
+
+/***************************************************************************
+ *SETUP - Setup Register
+ ***************************************************************************/
+/* USB1_CTRL :: SETUP :: OC_DISABLE [31:28] */
+#define BCHP_USB1_CTRL_SETUP_OC_DISABLE_MASK                       0xf0000000
+#define BCHP_USB1_CTRL_SETUP_OC_DISABLE_SHIFT                      28
+#define BCHP_USB1_CTRL_SETUP_OC_DISABLE_DEFAULT                    0x00000000
+
+/* USB1_CTRL :: SETUP :: SRAM_CS_DIS [27:25] */
+#define BCHP_USB1_CTRL_SETUP_SRAM_CS_DIS_MASK                      0x0e000000
+#define BCHP_USB1_CTRL_SETUP_SRAM_CS_DIS_SHIFT                     25
+#define BCHP_USB1_CTRL_SETUP_SRAM_CS_DIS_DEFAULT                   0x00000000
+
+/* USB1_CTRL :: SETUP :: SETUP_SPARE [24:15] */
+#define BCHP_USB1_CTRL_SETUP_SETUP_SPARE_MASK                      0x01ff8000
+#define BCHP_USB1_CTRL_SETUP_SETUP_SPARE_SHIFT                     15
+#define BCHP_USB1_CTRL_SETUP_SETUP_SPARE_DEFAULT                   0x00000000
+
+/* USB1_CTRL :: SETUP :: scb1_en [14:14] */
+#define BCHP_USB1_CTRL_SETUP_scb1_en_MASK                          0x00004000
+#define BCHP_USB1_CTRL_SETUP_scb1_en_SHIFT                         14
+#define BCHP_USB1_CTRL_SETUP_scb1_en_DEFAULT                       0x00000000
+
+/* USB1_CTRL :: SETUP :: scb_client_swap [13:13] */
+#define BCHP_USB1_CTRL_SETUP_scb_client_swap_MASK                  0x00002000
+#define BCHP_USB1_CTRL_SETUP_scb_client_swap_SHIFT                 13
+#define BCHP_USB1_CTRL_SETUP_scb_client_swap_DEFAULT               0x00000000
+
+/* USB1_CTRL :: SETUP :: async_expire_dis [12:12] */
+#define BCHP_USB1_CTRL_SETUP_async_expire_dis_MASK                 0x00001000
+#define BCHP_USB1_CTRL_SETUP_async_expire_dis_SHIFT                12
+#define BCHP_USB1_CTRL_SETUP_async_expire_dis_DEFAULT              0x00000000
+
+/* USB1_CTRL :: SETUP :: discon_intr_en [11:11] */
+#define BCHP_USB1_CTRL_SETUP_discon_intr_en_MASK                   0x00000800
+#define BCHP_USB1_CTRL_SETUP_discon_intr_en_SHIFT                  11
+#define BCHP_USB1_CTRL_SETUP_discon_intr_en_DEFAULT                0x00000000
+
+/* USB1_CTRL :: SETUP :: con_intr_en [10:10] */
+#define BCHP_USB1_CTRL_SETUP_con_intr_en_MASK                      0x00000400
+#define BCHP_USB1_CTRL_SETUP_con_intr_en_SHIFT                     10
+#define BCHP_USB1_CTRL_SETUP_con_intr_en_DEFAULT                   0x00000000
+
+/* USB1_CTRL :: SETUP :: soft_shutdown [09:09] */
+#define BCHP_USB1_CTRL_SETUP_soft_shutdown_MASK                    0x00000200
+#define BCHP_USB1_CTRL_SETUP_soft_shutdown_SHIFT                   9
+#define BCHP_USB1_CTRL_SETUP_soft_shutdown_DEFAULT                 0x00000000
+
+/* USB1_CTRL :: SETUP :: utmi_bkward_en [08:08] */
+#define BCHP_USB1_CTRL_SETUP_utmi_bkward_en_MASK                   0x00000100
+#define BCHP_USB1_CTRL_SETUP_utmi_bkward_en_SHIFT                  8
+#define BCHP_USB1_CTRL_SETUP_utmi_bkward_en_DEFAULT                0x00000000
+
+/* USB1_CTRL :: SETUP :: utmi_pls_en [07:07] */
+#define BCHP_USB1_CTRL_SETUP_utmi_pls_en_MASK                      0x00000080
+#define BCHP_USB1_CTRL_SETUP_utmi_pls_en_SHIFT                     7
+#define BCHP_USB1_CTRL_SETUP_utmi_pls_en_DEFAULT                   0x00000000
+
+/* USB1_CTRL :: SETUP :: soft_reset [06:06] */
+#define BCHP_USB1_CTRL_SETUP_soft_reset_MASK                       0x00000040
+#define BCHP_USB1_CTRL_SETUP_soft_reset_SHIFT                      6
+#define BCHP_USB1_CTRL_SETUP_soft_reset_DEFAULT                    0x00000000
+
+/* USB1_CTRL :: SETUP :: IPP [05:05] */
+#define BCHP_USB1_CTRL_SETUP_IPP_MASK                              0x00000020
+#define BCHP_USB1_CTRL_SETUP_IPP_SHIFT                             5
+#define BCHP_USB1_CTRL_SETUP_IPP_DEFAULT                           0x00000000
+
+/* USB1_CTRL :: SETUP :: IOC [04:04] */
+#define BCHP_USB1_CTRL_SETUP_IOC_MASK                              0x00000010
+#define BCHP_USB1_CTRL_SETUP_IOC_SHIFT                             4
+#define BCHP_USB1_CTRL_SETUP_IOC_DEFAULT                           0x00000000
+
+/* USB1_CTRL :: SETUP :: WABO [03:03] */
+#define BCHP_USB1_CTRL_SETUP_WABO_MASK                             0x00000008
+#define BCHP_USB1_CTRL_SETUP_WABO_SHIFT                            3
+#define BCHP_USB1_CTRL_SETUP_WABO_DEFAULT                          0x00000000
+
+/* USB1_CTRL :: SETUP :: FNBO [02:02] */
+#define BCHP_USB1_CTRL_SETUP_FNBO_MASK                             0x00000004
+#define BCHP_USB1_CTRL_SETUP_FNBO_SHIFT                            2
+#define BCHP_USB1_CTRL_SETUP_FNBO_DEFAULT                          0x00000000
+
+/* USB1_CTRL :: SETUP :: FNHW [01:01] */
+#define BCHP_USB1_CTRL_SETUP_FNHW_MASK                             0x00000002
+#define BCHP_USB1_CTRL_SETUP_FNHW_SHIFT                            1
+#define BCHP_USB1_CTRL_SETUP_FNHW_DEFAULT                          0x00000000
+
+/* USB1_CTRL :: SETUP :: BABO [00:00] */
+#define BCHP_USB1_CTRL_SETUP_BABO_MASK                             0x00000001
+#define BCHP_USB1_CTRL_SETUP_BABO_SHIFT                            0
+#define BCHP_USB1_CTRL_SETUP_BABO_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *PLL_CTL - PLL Control Register
+ ***************************************************************************/
+/* USB1_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK                 0x80000000
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT                31
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT              0x00000000
+
+/* USB1_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_RESETB_MASK                     0x40000000
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_RESETB_SHIFT                    30
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                  0x00000001
+
+/* USB1_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
+#define BCHP_USB1_CTRL_PLL_CTL_PHYPLL_BYP_MASK                     0x20000000
+#define BCHP_USB1_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                    29
+#define BCHP_USB1_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                  0x00000000
+
+/* USB1_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                    0x10000000
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                   28
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                 0x00000001
+
+/* USB1_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                 0x08000000
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                27
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT              0x00000000
+
+/* USB1_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_Ka_MASK                         0x07000000
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_Ka_SHIFT                        24
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_Ka_DEFAULT                      0x00000001
+
+/* USB1_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
+#define BCHP_USB1_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                  0x00800000
+#define BCHP_USB1_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                 23
+#define BCHP_USB1_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT               0x00000000
+
+/* USB1_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_Ki_MASK                         0x00700000
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_Ki_SHIFT                        20
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_Ki_DEFAULT                      0x00000002
+
+/* USB1_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_Kp_MASK                         0x000f0000
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_Kp_SHIFT                        16
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_Kp_DEFAULT                      0x00000007
+
+/* USB1_CTRL :: PLL_CTL :: PLLCTL_SPARE2 [15:15] */
+#define BCHP_USB1_CTRL_PLL_CTL_PLLCTL_SPARE2_MASK                  0x00008000
+#define BCHP_USB1_CTRL_PLL_CTL_PLLCTL_SPARE2_SHIFT                 15
+#define BCHP_USB1_CTRL_PLL_CTL_PLLCTL_SPARE2_DEFAULT               0x00000000
+
+/* USB1_CTRL :: PLL_CTL :: PLL_pdiv [14:12] */
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_pdiv_MASK                       0x00007000
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_pdiv_SHIFT                      12
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                    0x00000001
+
+/* USB1_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
+#define BCHP_USB1_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                  0x00000c00
+#define BCHP_USB1_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                 10
+#define BCHP_USB1_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT               0x00000000
+
+/* USB1_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_ndiv_MASK                       0x000003ff
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_ndiv_SHIFT                      0
+#define BCHP_USB1_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                    0x00000050
+
+/***************************************************************************
+ *FLADJ_VALUE - Frame Adjust Value
+ ***************************************************************************/
+/* USB1_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
+#define BCHP_USB1_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                  0xffffffff
+#define BCHP_USB1_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                 0
+#define BCHP_USB1_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT               0x000c0020
+
+/***************************************************************************
+ *EBRIDGE - Control Register for EHCI Bridge
+ ***************************************************************************/
+/* USB1_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
+#define BCHP_USB1_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                 0x80000000
+#define BCHP_USB1_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                31
+#define BCHP_USB1_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT              0x00000000
+
+/* USB1_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
+#define BCHP_USB1_CTRL_EBRIDGE_ebrff_reset_MASK                    0x40000000
+#define BCHP_USB1_CTRL_EBRIDGE_ebrff_reset_SHIFT                   30
+#define BCHP_USB1_CTRL_EBRIDGE_ebrff_reset_DEFAULT                 0x00000000
+
+/* USB1_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB1_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK             0x20000000
+#define BCHP_USB1_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT            29
+#define BCHP_USB1_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT          0x00000000
+
+/* USB1_CTRL :: EBRIDGE :: ebr_size_sel [28:28] */
+#define BCHP_USB1_CTRL_EBRIDGE_ebr_size_sel_MASK                   0x10000000
+#define BCHP_USB1_CTRL_EBRIDGE_ebr_size_sel_SHIFT                  28
+#define BCHP_USB1_CTRL_EBRIDGE_ebr_size_sel_DEFAULT                0x00000000
+
+/* USB1_CTRL :: EBRIDGE :: EBR_SPARE [27:17] */
+#define BCHP_USB1_CTRL_EBRIDGE_EBR_SPARE_MASK                      0x0ffe0000
+#define BCHP_USB1_CTRL_EBRIDGE_EBR_SPARE_SHIFT                     17
+#define BCHP_USB1_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                   0x00000000
+
+/* USB1_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
+#define BCHP_USB1_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                  0x0001f000
+#define BCHP_USB1_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                 12
+#define BCHP_USB1_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT               0x00000002
+
+/* USB1_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
+#define BCHP_USB1_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                   0x00000f80
+#define BCHP_USB1_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                  7
+#define BCHP_USB1_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                0x00000004
+
+/* USB1_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
+#define BCHP_USB1_CTRL_EBRIDGE_EBR_MISC_MASK                       0x0000007e
+#define BCHP_USB1_CTRL_EBRIDGE_EBR_MISC_SHIFT                      1
+#define BCHP_USB1_CTRL_EBRIDGE_EBR_MISC_DEFAULT                    0x00000000
+
+/* USB1_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
+#define BCHP_USB1_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                     0x00000001
+#define BCHP_USB1_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                    0
+#define BCHP_USB1_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *OBRIDGE - Control Register for OHCI Bridge
+ ***************************************************************************/
+/* USB1_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
+#define BCHP_USB1_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                 0x80000000
+#define BCHP_USB1_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                31
+#define BCHP_USB1_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT              0x00000000
+
+/* USB1_CTRL :: OBRIDGE :: obrff_reset [30:30] */
+#define BCHP_USB1_CTRL_OBRIDGE_obrff_reset_MASK                    0x40000000
+#define BCHP_USB1_CTRL_OBRIDGE_obrff_reset_SHIFT                   30
+#define BCHP_USB1_CTRL_OBRIDGE_obrff_reset_DEFAULT                 0x00000000
+
+/* USB1_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB1_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK             0x20000000
+#define BCHP_USB1_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT            29
+#define BCHP_USB1_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT          0x00000000
+
+/* USB1_CTRL :: OBRIDGE :: obr_size_sel [28:28] */
+#define BCHP_USB1_CTRL_OBRIDGE_obr_size_sel_MASK                   0x10000000
+#define BCHP_USB1_CTRL_OBRIDGE_obr_size_sel_SHIFT                  28
+#define BCHP_USB1_CTRL_OBRIDGE_obr_size_sel_DEFAULT                0x00000000
+
+/* USB1_CTRL :: OBRIDGE :: OBR_SPARE [27:17] */
+#define BCHP_USB1_CTRL_OBRIDGE_OBR_SPARE_MASK                      0x0ffe0000
+#define BCHP_USB1_CTRL_OBRIDGE_OBR_SPARE_SHIFT                     17
+#define BCHP_USB1_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                   0x00000000
+
+/* USB1_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
+#define BCHP_USB1_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                  0x0001f000
+#define BCHP_USB1_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                 12
+#define BCHP_USB1_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT               0x00000002
+
+/* USB1_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
+#define BCHP_USB1_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                   0x00000f80
+#define BCHP_USB1_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                  7
+#define BCHP_USB1_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                0x00000004
+
+/* USB1_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
+#define BCHP_USB1_CTRL_OBRIDGE_OBR_MISC_MASK                       0x0000007e
+#define BCHP_USB1_CTRL_OBRIDGE_OBR_MISC_SHIFT                      1
+#define BCHP_USB1_CTRL_OBRIDGE_OBR_MISC_DEFAULT                    0x00000000
+
+/* USB1_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
+#define BCHP_USB1_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                     0x00000001
+#define BCHP_USB1_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                    0
+#define BCHP_USB1_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *MDIO - MDIO Interface Programming Register
+ ***************************************************************************/
+/* USB1_CTRL :: MDIO :: MDIO_CLK_SEL [31:31] */
+#define BCHP_USB1_CTRL_MDIO_MDIO_CLK_SEL_MASK                      0x80000000
+#define BCHP_USB1_CTRL_MDIO_MDIO_CLK_SEL_SHIFT                     31
+#define BCHP_USB1_CTRL_MDIO_MDIO_CLK_SEL_DEFAULT                   0x00000000
+
+/* USB1_CTRL :: MDIO :: MDIO_XVER_SELECT [30:29] */
+#define BCHP_USB1_CTRL_MDIO_MDIO_XVER_SELECT_MASK                  0x60000000
+#define BCHP_USB1_CTRL_MDIO_MDIO_XVER_SELECT_SHIFT                 29
+#define BCHP_USB1_CTRL_MDIO_MDIO_XVER_SELECT_DEFAULT               0x00000000
+
+/* USB1_CTRL :: MDIO :: MDIO_TERM_SELECT [28:28] */
+#define BCHP_USB1_CTRL_MDIO_MDIO_TERM_SELECT_MASK                  0x10000000
+#define BCHP_USB1_CTRL_MDIO_MDIO_TERM_SELECT_SHIFT                 28
+#define BCHP_USB1_CTRL_MDIO_MDIO_TERM_SELECT_DEFAULT               0x00000000
+
+/* USB1_CTRL :: MDIO :: MDIO_FS_XVER_OWN [27:27] */
+#define BCHP_USB1_CTRL_MDIO_MDIO_FS_XVER_OWN_MASK                  0x08000000
+#define BCHP_USB1_CTRL_MDIO_MDIO_FS_XVER_OWN_SHIFT                 27
+#define BCHP_USB1_CTRL_MDIO_MDIO_FS_XVER_OWN_DEFAULT               0x00000000
+
+/* USB1_CTRL :: MDIO :: MDIO_TESTMODE [26:26] */
+#define BCHP_USB1_CTRL_MDIO_MDIO_TESTMODE_MASK                     0x04000000
+#define BCHP_USB1_CTRL_MDIO_MDIO_TESTMODE_SHIFT                    26
+#define BCHP_USB1_CTRL_MDIO_MDIO_TESTMODE_DEFAULT                  0x00000000
+
+/* USB1_CTRL :: MDIO :: WR_START [25:25] */
+#define BCHP_USB1_CTRL_MDIO_WR_START_MASK                          0x02000000
+#define BCHP_USB1_CTRL_MDIO_WR_START_SHIFT                         25
+#define BCHP_USB1_CTRL_MDIO_WR_START_DEFAULT                       0x00000000
+
+/* USB1_CTRL :: MDIO :: RD_START [24:24] */
+#define BCHP_USB1_CTRL_MDIO_RD_START_MASK                          0x01000000
+#define BCHP_USB1_CTRL_MDIO_RD_START_SHIFT                         24
+#define BCHP_USB1_CTRL_MDIO_RD_START_DEFAULT                       0x00000000
+
+/* USB1_CTRL :: MDIO :: MDIO_ADDR [23:16] */
+#define BCHP_USB1_CTRL_MDIO_MDIO_ADDR_MASK                         0x00ff0000
+#define BCHP_USB1_CTRL_MDIO_MDIO_ADDR_SHIFT                        16
+#define BCHP_USB1_CTRL_MDIO_MDIO_ADDR_DEFAULT                      0x00000000
+
+/* USB1_CTRL :: MDIO :: MDIO_DATA [15:00] */
+#define BCHP_USB1_CTRL_MDIO_MDIO_DATA_MASK                         0x0000ffff
+#define BCHP_USB1_CTRL_MDIO_MDIO_DATA_SHIFT                        0
+#define BCHP_USB1_CTRL_MDIO_MDIO_DATA_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *MDIO2 - MDIO Interface Read Register
+ ***************************************************************************/
+/* USB1_CTRL :: MDIO2 :: SYNOPSIS_CORE_ID [31:16] */
+#define BCHP_USB1_CTRL_MDIO2_SYNOPSIS_CORE_ID_MASK                 0xffff0000
+#define BCHP_USB1_CTRL_MDIO2_SYNOPSIS_CORE_ID_SHIFT                16
+#define BCHP_USB1_CTRL_MDIO2_SYNOPSIS_CORE_ID_DEFAULT              0x0000270a
+
+/* USB1_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
+#define BCHP_USB1_CTRL_MDIO2_MDIO_RD_DATA_MASK                     0x0000ffff
+#define BCHP_USB1_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                    0
+#define BCHP_USB1_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTL - Test Port Control Register
+ ***************************************************************************/
+/* USB1_CTRL :: TEST_PORT_CTL :: TP_EN [31:31] */
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_TP_EN_MASK                    0x80000000
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_TP_EN_SHIFT                   31
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_TP_EN_DEFAULT                 0x00000000
+
+/* USB1_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [30:27] */
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK              0x78000000
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT             27
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT           0x00000000
+
+/* USB1_CTRL :: TEST_PORT_CTL :: scb1_wr_data_sel [26:26] */
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_MASK         0x04000000
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_SHIFT        26
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_DEFAULT      0x00000000
+
+/* USB1_CTRL :: TEST_PORT_CTL :: scb0_wr_data_sel [25:25] */
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_MASK         0x02000000
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_SHIFT        25
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_DEFAULT      0x00000000
+
+/* USB1_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [24:24] */
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK               0x01000000
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT              24
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT            0x00000000
+
+/* USB1_CTRL :: TEST_PORT_CTL :: pwrflt2_oe [23:23] */
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwrflt2_oe_MASK               0x00800000
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwrflt2_oe_SHIFT              23
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwrflt2_oe_DEFAULT            0x00000000
+
+/* USB1_CTRL :: TEST_PORT_CTL :: pwron1_tstsel [22:22] */
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwron1_tstsel_MASK            0x00400000
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwron1_tstsel_SHIFT           22
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwron1_tstsel_DEFAULT         0x00000000
+
+/* USB1_CTRL :: TEST_PORT_CTL :: pwron2_tstsel [21:21] */
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwron2_tstsel_MASK            0x00200000
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwron2_tstsel_SHIFT           21
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwron2_tstsel_DEFAULT         0x00000000
+
+/* USB1_CTRL :: TEST_PORT_CTL :: test_clksel [20:19] */
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_test_clksel_MASK              0x00180000
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_test_clksel_SHIFT             19
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_test_clksel_DEFAULT           0x00000000
+
+/* USB1_CTRL :: TEST_PORT_CTL :: pwrflt_tstsel [18:16] */
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwrflt_tstsel_MASK            0x00070000
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwrflt_tstsel_SHIFT           16
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwrflt_tstsel_DEFAULT         0x00000000
+
+/* USB1_CTRL :: TEST_PORT_CTL :: UTMI_TEST_SEL [15:08] */
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_MASK            0x0000ff00
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_SHIFT           8
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_DEFAULT         0x00000000
+
+/* USB1_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                0x000000ff
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT               0
+#define BCHP_USB1_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *USB_SIMCTL - Simulation Register
+ ***************************************************************************/
+/* USB1_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
+#define BCHP_USB1_CTRL_USB_SIMCTL_sim_mode_en_MASK                 0x80000000
+#define BCHP_USB1_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                31
+#define BCHP_USB1_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT              0x00000000
+
+/* USB1_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
+#define BCHP_USB1_CTRL_USB_SIMCTL_scale_down_en_MASK               0x40000000
+#define BCHP_USB1_CTRL_USB_SIMCTL_scale_down_en_SHIFT              30
+#define BCHP_USB1_CTRL_USB_SIMCTL_scale_down_en_DEFAULT            0x00000000
+
+/* USB1_CTRL :: USB_SIMCTL :: otg_scale_down_en [29:28] */
+#define BCHP_USB1_CTRL_USB_SIMCTL_otg_scale_down_en_MASK           0x30000000
+#define BCHP_USB1_CTRL_USB_SIMCTL_otg_scale_down_en_SHIFT          28
+#define BCHP_USB1_CTRL_USB_SIMCTL_otg_scale_down_en_DEFAULT        0x00000000
+
+/* USB1_CTRL :: USB_SIMCTL :: intr_test [27:27] */
+#define BCHP_USB1_CTRL_USB_SIMCTL_intr_test_MASK                   0x08000000
+#define BCHP_USB1_CTRL_USB_SIMCTL_intr_test_SHIFT                  27
+#define BCHP_USB1_CTRL_USB_SIMCTL_intr_test_DEFAULT                0x00000000
+
+/* USB1_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
+#define BCHP_USB1_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK       0x04000000
+#define BCHP_USB1_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT      26
+#define BCHP_USB1_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT    0x00000000
+
+/* USB1_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:04] */
+#define BCHP_USB1_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                0x03fffff0
+#define BCHP_USB1_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT               4
+#define BCHP_USB1_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT             0x00000000
+
+/* USB1_CTRL :: USB_SIMCTL :: wkonlan_en [03:00] */
+#define BCHP_USB1_CTRL_USB_SIMCTL_wkonlan_en_MASK                  0x0000000f
+#define BCHP_USB1_CTRL_USB_SIMCTL_wkonlan_en_SHIFT                 0
+#define BCHP_USB1_CTRL_USB_SIMCTL_wkonlan_en_DEFAULT               0x00000000
+
+/***************************************************************************
+ *USB_TESTCTL - Throutput Test Control
+ ***************************************************************************/
+/* USB1_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:23] */
+#define BCHP_USB1_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK             0xff800000
+#define BCHP_USB1_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT            23
+#define BCHP_USB1_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT          0x00000000
+
+/* USB1_CTRL :: USB_TESTCTL :: CTRLLER_SEL [22:21] */
+#define BCHP_USB1_CTRL_USB_TESTCTL_CTRLLER_SEL_MASK                0x00600000
+#define BCHP_USB1_CTRL_USB_TESTCTL_CTRLLER_SEL_SHIFT               21
+#define BCHP_USB1_CTRL_USB_TESTCTL_CTRLLER_SEL_DEFAULT             0x00000000
+
+/* USB1_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
+#define BCHP_USB1_CTRL_USB_TESTCTL_DCNT_EN_MASK                    0x00100000
+#define BCHP_USB1_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                   20
+#define BCHP_USB1_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                 0x00000000
+
+/* USB1_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
+#define BCHP_USB1_CTRL_USB_TESTCTL_SPEED_SEL_MASK                  0x00080000
+#define BCHP_USB1_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                 19
+#define BCHP_USB1_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT               0x00000000
+
+/* USB1_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
+#define BCHP_USB1_CTRL_USB_TESTCTL_DCNT_SEL_MASK                   0x00070000
+#define BCHP_USB1_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                  16
+#define BCHP_USB1_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                0x00000000
+
+/* USB1_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
+#define BCHP_USB1_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK             0x0000fc00
+#define BCHP_USB1_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT            10
+#define BCHP_USB1_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT          0x00000000
+
+/* USB1_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
+#define BCHP_USB1_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK             0x000003ff
+#define BCHP_USB1_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT            0
+#define BCHP_USB1_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT          0x00000000
+
+/***************************************************************************
+ *USB_TESTMON - Throughput Test Monitor
+ ***************************************************************************/
+/* USB1_CTRL :: USB_TESTMON :: TESTMON_STAT [31:00] */
+#define BCHP_USB1_CTRL_USB_TESTMON_TESTMON_STAT_MASK               0xffffffff
+#define BCHP_USB1_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT              0
+
+/***************************************************************************
+ *UTMI_CTL_1 - UTMI Control Register
+ ***************************************************************************/
+/* USB1_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB_P1 [31:31] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_MASK             0x80000000
+#define BCHP_USB1_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_SHIFT            31
+#define BCHP_USB1_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_DEFAULT          0x00000000
+
+/* USB1_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK            0x70000000
+#define BCHP_USB1_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT           28
+#define BCHP_USB1_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT         0x00000000
+
+/* USB1_CTRL :: UTMI_CTL_1 :: DFE_LPBACK_P1 [27:27] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_MASK               0x08000000
+#define BCHP_USB1_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_SHIFT              27
+#define BCHP_USB1_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_DEFAULT            0x00000000
+
+/* USB1_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE3 [26:25] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_MASK             0x06000000
+#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_SHIFT            25
+#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_DEFAULT          0x00000000
+
+/* USB1_CTRL :: UTMI_CTL_1 :: DISCON_PHY_P1 [24:24] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_DISCON_PHY_P1_MASK               0x01000000
+#define BCHP_USB1_CTRL_UTMI_CTL_1_DISCON_PHY_P1_SHIFT              24
+#define BCHP_USB1_CTRL_UTMI_CTL_1_DISCON_PHY_P1_DEFAULT            0x00000000
+
+/* USB1_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK               0x00800000
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT              23
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT            0x00000000
+
+/* USB1_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK               0x00400000
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT              22
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT            0x00000000
+
+/* USB1_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK               0x00200000
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT              21
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT            0x00000000
+
+/* USB1_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK               0x00100000
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT              20
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT            0x00000000
+
+/* USB1_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                 0x000c0000
+#define BCHP_USB1_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                18
+#define BCHP_USB1_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT              0x00000000
+
+/* USB1_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK         0x00020000
+#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT        17
+#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT      0x00000001
+
+/* USB1_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK          0x00010000
+#define BCHP_USB1_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT         16
+#define BCHP_USB1_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT       0x00000000
+
+/* USB1_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB [15:15] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_USB11_TX_OEB_MASK                0x00008000
+#define BCHP_USB1_CTRL_UTMI_CTL_1_USB11_TX_OEB_SHIFT               15
+#define BCHP_USB1_CTRL_UTMI_CTL_1_USB11_TX_OEB_DEFAULT             0x00000000
+
+/* USB1_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK               0x00007000
+#define BCHP_USB1_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT              12
+#define BCHP_USB1_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT            0x00000000
+
+/* USB1_CTRL :: UTMI_CTL_1 :: DFE_LPBACK [11:11] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_DFE_LPBACK_MASK                  0x00000800
+#define BCHP_USB1_CTRL_UTMI_CTL_1_DFE_LPBACK_SHIFT                 11
+#define BCHP_USB1_CTRL_UTMI_CTL_1_DFE_LPBACK_DEFAULT               0x00000000
+
+/* USB1_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE1 [10:09] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_MASK             0x00000600
+#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_SHIFT            9
+#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_DEFAULT          0x00000000
+
+/* USB1_CTRL :: UTMI_CTL_1 :: DISCON_PHY [08:08] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_DISCON_PHY_MASK                  0x00000100
+#define BCHP_USB1_CTRL_UTMI_CTL_1_DISCON_PHY_SHIFT                 8
+#define BCHP_USB1_CTRL_UTMI_CTL_1_DISCON_PHY_DEFAULT               0x00000000
+
+/* USB1_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                  0x00000080
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                 7
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT               0x00000000
+
+/* USB1_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                  0x00000040
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                 6
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT               0x00000000
+
+/* USB1_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                  0x00000020
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                 5
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT               0x00000000
+
+/* USB1_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                  0x00000010
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                 4
+#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT               0x00000000
+
+/* USB1_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_PHY_MODE_MASK                    0x0000000c
+#define BCHP_USB1_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                   2
+#define BCHP_USB1_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                 0x00000000
+
+/* USB1_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK            0x00000002
+#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT           1
+#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT         0x00000001
+
+/* USB1_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
+#define BCHP_USB1_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK             0x00000001
+#define BCHP_USB1_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT            0
+#define BCHP_USB1_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT          0x00000000
+
+/***************************************************************************
+ *UTMI_CTL_2 - UTMI Control 2 Register
+ ***************************************************************************/
+/* USB1_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
+#define BCHP_USB1_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK              0xffffffff
+#define BCHP_USB1_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT             0
+#define BCHP_USB1_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT           0x00000000
+
+/***************************************************************************
+ *SPARE1 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB1_CTRL :: SPARE1 :: SPARE1_BITS [31:00] */
+#define BCHP_USB1_CTRL_SPARE1_SPARE1_BITS_MASK                     0xffffffff
+#define BCHP_USB1_CTRL_SPARE1_SPARE1_BITS_SHIFT                    0
+#define BCHP_USB1_CTRL_SPARE1_SPARE1_BITS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *SPARE2 - Spare2 Register for future use
+ ***************************************************************************/
+/* USB1_CTRL :: SPARE2 :: SPARE2_BITS [31:00] */
+#define BCHP_USB1_CTRL_SPARE2_SPARE2_BITS_MASK                     0xffffffff
+#define BCHP_USB1_CTRL_SPARE2_SPARE2_BITS_SHIFT                    0
+#define BCHP_USB1_CTRL_SPARE2_SPARE2_BITS_DEFAULT                  0x00000000
+
+#endif /* #ifndef BCHP_USB1_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_usb_ctrl.h b/include/linux/brcmstb/7435b0/bchp_usb_ctrl.h
new file mode 100644
index 0000000..91302a9
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_usb_ctrl.h
@@ -0,0 +1,685 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:28 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_usb_ctrl.h $
+ * 
+ * Hydra_Software_Devel/3   12/7/11 4:28p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB_CTRL_H__
+#define BCHP_USB_CTRL_H__
+
+/***************************************************************************
+ *USB_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB_CTRL_SETUP                      0x00480200 /* Setup Register */
+#define BCHP_USB_CTRL_PLL_CTL                    0x00480204 /* PLL Control Register */
+#define BCHP_USB_CTRL_FLADJ_VALUE                0x00480208 /* Frame Adjust Value */
+#define BCHP_USB_CTRL_EBRIDGE                    0x0048020c /* Control Register for EHCI Bridge */
+#define BCHP_USB_CTRL_OBRIDGE                    0x00480210 /* Control Register for OHCI Bridge */
+#define BCHP_USB_CTRL_MDIO                       0x00480214 /* MDIO Interface Programming Register */
+#define BCHP_USB_CTRL_MDIO2                      0x00480218 /* MDIO Interface Read Register */
+#define BCHP_USB_CTRL_TEST_PORT_CTL              0x0048021c /* Test Port Control Register */
+#define BCHP_USB_CTRL_USB_SIMCTL                 0x00480220 /* Simulation Register */
+#define BCHP_USB_CTRL_USB_TESTCTL                0x00480224 /* Throutput Test Control */
+#define BCHP_USB_CTRL_USB_TESTMON                0x00480228 /* Throughput Test Monitor */
+#define BCHP_USB_CTRL_UTMI_CTL_1                 0x0048022c /* UTMI Control Register */
+#define BCHP_USB_CTRL_UTMI_CTL_2                 0x00480230 /* UTMI Control 2 Register */
+#define BCHP_USB_CTRL_SPARE1                     0x00480234 /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE2                     0x00480238 /* Spare2 Register for future use */
+
+/***************************************************************************
+ *SETUP - Setup Register
+ ***************************************************************************/
+/* USB_CTRL :: SETUP :: OC_DISABLE [31:28] */
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK                        0xf0000000
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT                       28
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: SRAM_CS_DIS [27:25] */
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_MASK                       0x0e000000
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_SHIFT                      25
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: SETUP_SPARE [24:15] */
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK                       0x01ff8000
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT                      15
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: scb1_en [14:14] */
+#define BCHP_USB_CTRL_SETUP_scb1_en_MASK                           0x00004000
+#define BCHP_USB_CTRL_SETUP_scb1_en_SHIFT                          14
+#define BCHP_USB_CTRL_SETUP_scb1_en_DEFAULT                        0x00000000
+
+/* USB_CTRL :: SETUP :: scb_client_swap [13:13] */
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_MASK                   0x00002000
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_SHIFT                  13
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_DEFAULT                0x00000000
+
+/* USB_CTRL :: SETUP :: async_expire_dis [12:12] */
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK                  0x00001000
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT                 12
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT               0x00000000
+
+/* USB_CTRL :: SETUP :: discon_intr_en [11:11] */
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_MASK                    0x00000800
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_SHIFT                   11
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: con_intr_en [10:10] */
+#define BCHP_USB_CTRL_SETUP_con_intr_en_MASK                       0x00000400
+#define BCHP_USB_CTRL_SETUP_con_intr_en_SHIFT                      10
+#define BCHP_USB_CTRL_SETUP_con_intr_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: soft_shutdown [09:09] */
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_MASK                     0x00000200
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_SHIFT                    9
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_DEFAULT                  0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK                    0x00000100
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT                   8
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK                       0x00000080
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT                      7
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: soft_reset [06:06] */
+#define BCHP_USB_CTRL_SETUP_soft_reset_MASK                        0x00000040
+#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT                       6
+#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: IPP [05:05] */
+#define BCHP_USB_CTRL_SETUP_IPP_MASK                               0x00000020
+#define BCHP_USB_CTRL_SETUP_IPP_SHIFT                              5
+#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: IOC [04:04] */
+#define BCHP_USB_CTRL_SETUP_IOC_MASK                               0x00000010
+#define BCHP_USB_CTRL_SETUP_IOC_SHIFT                              4
+#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: WABO [03:03] */
+#define BCHP_USB_CTRL_SETUP_WABO_MASK                              0x00000008
+#define BCHP_USB_CTRL_SETUP_WABO_SHIFT                             3
+#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNBO [02:02] */
+#define BCHP_USB_CTRL_SETUP_FNBO_MASK                              0x00000004
+#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT                             2
+#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNHW [01:01] */
+#define BCHP_USB_CTRL_SETUP_FNHW_MASK                              0x00000002
+#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT                             1
+#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: BABO [00:00] */
+#define BCHP_USB_CTRL_SETUP_BABO_MASK                              0x00000001
+#define BCHP_USB_CTRL_SETUP_BABO_SHIFT                             0
+#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *PLL_CTL - PLL Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK                  0x80000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT                 31
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT               0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK                      0x40000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT                     30
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                   0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK                      0x20000000
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                     29
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                   0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                     0x10000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                    28
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                  0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                  0x08000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                 27
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT               0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK                          0x07000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT                         24
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT                       0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                   0x00800000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                  23
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK                          0x00700000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT                         20
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT                       0x00000002
+
+/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK                          0x000f0000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT                         16
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT                       0x00000007
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE2 [15:15] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_MASK                   0x00008000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_SHIFT                  15
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_pdiv [14:12] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK                        0x00007000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT                       12
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                     0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                   0x00000c00
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                  10
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK                        0x000003ff
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT                       0
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                     0x00000050
+
+/***************************************************************************
+ *FLADJ_VALUE - Frame Adjust Value
+ ***************************************************************************/
+/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                   0xffffffff
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                  0
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT                0x000c0020
+
+/***************************************************************************
+ *EBRIDGE - Control Register for EHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_size_sel [28:28] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_DEFAULT                 0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *OBRIDGE - Control Register for OHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_size_sel [28:28] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_DEFAULT                 0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *MDIO - MDIO Interface Programming Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO :: MDIO_CLK_SEL [31:31] */
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_MASK                       0x80000000
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_SHIFT                      31
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_DEFAULT                    0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_XVER_SELECT [30:29] */
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_MASK                   0x60000000
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_SHIFT                  29
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_DEFAULT                0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_TERM_SELECT [28:28] */
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_MASK                   0x10000000
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_SHIFT                  28
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_DEFAULT                0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_FS_XVER_OWN [27:27] */
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_MASK                   0x08000000
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_SHIFT                  27
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_DEFAULT                0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_TESTMODE [26:26] */
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_MASK                      0x04000000
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_SHIFT                     26
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_DEFAULT                   0x00000000
+
+/* USB_CTRL :: MDIO :: WR_START [25:25] */
+#define BCHP_USB_CTRL_MDIO_WR_START_MASK                           0x02000000
+#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT                          25
+#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: RD_START [24:24] */
+#define BCHP_USB_CTRL_MDIO_RD_START_MASK                           0x01000000
+#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT                          24
+#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK                          0x00ff0000
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT                         16
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT                       0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK                          0x0000ffff
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT                         0
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *MDIO2 - MDIO Interface Read Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO2 :: SYNOPSIS_CORE_ID [31:16] */
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_MASK                  0xffff0000
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_SHIFT                 16
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_DEFAULT               0x0000270a
+
+/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK                      0x0000ffff
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                     0
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTL - Test Port Control Register
+ ***************************************************************************/
+/* USB_CTRL :: TEST_PORT_CTL :: TP_EN [31:31] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_MASK                     0x80000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_SHIFT                    31
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [30:27] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK               0x78000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT              27
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb1_wr_data_sel [26:26] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_MASK          0x04000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_SHIFT         26
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_DEFAULT       0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb0_wr_data_sel [25:25] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_MASK          0x02000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_SHIFT         25
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_DEFAULT       0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [24:24] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK                0x01000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT               24
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt2_oe [23:23] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_MASK                0x00800000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_SHIFT               23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron1_tstsel [22:22] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_MASK             0x00400000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_SHIFT            22
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron2_tstsel [21:21] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_MASK             0x00200000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_SHIFT            21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: test_clksel [20:19] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_MASK               0x00180000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_SHIFT              19
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_tstsel [18:16] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_MASK             0x00070000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_SHIFT            16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: UTMI_TEST_SEL [15:08] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_MASK             0x0000ff00
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_SHIFT            8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                 0x000000ff
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT                0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *USB_SIMCTL - Simulation Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK                  0x80000000
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                 31
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK                0x40000000
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT               30
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: otg_scale_down_en [29:28] */
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_MASK            0x30000000
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_SHIFT           28
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK                    0x08000000
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT                   27
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK        0x04000000
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT       26
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT     0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:04] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                 0x03fffff0
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT                4
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: wkonlan_en [03:00] */
+#define BCHP_USB_CTRL_USB_SIMCTL_wkonlan_en_MASK                   0x0000000f
+#define BCHP_USB_CTRL_USB_SIMCTL_wkonlan_en_SHIFT                  0
+#define BCHP_USB_CTRL_USB_SIMCTL_wkonlan_en_DEFAULT                0x00000000
+
+/***************************************************************************
+ *USB_TESTCTL - Throutput Test Control
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:23] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK              0xff800000
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT             23
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: CTRLLER_SEL [22:21] */
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_MASK                 0x00600000
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_SHIFT                21
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK                     0x00100000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                    20
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK                   0x00080000
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                  19
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT                0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK                    0x00070000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                   16
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK              0x0000fc00
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT             10
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK              0x000003ff
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT             0
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT           0x00000000
+
+/***************************************************************************
+ *USB_TESTMON - Throughput Test Monitor
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [31:00] */
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK                0xffffffff
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT               0
+
+/***************************************************************************
+ *UTMI_CTL_1 - UTMI Control Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB_P1 [31:31] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_MASK              0x80000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_SHIFT             31
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK             0x70000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT            28
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT          0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK_P1 [27:27] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_MASK                0x08000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_SHIFT               27
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE3 [26:25] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_MASK              0x06000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_SHIFT             25
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY_P1 [24:24] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_MASK                0x01000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_SHIFT               24
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK                0x00800000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT               23
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK                0x00400000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT               22
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK                0x00200000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT               21
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK                0x00100000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT               20
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                  0x000c0000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                 18
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT               0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT       0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK           0x00010000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT          16
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT        0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB [15:15] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_MASK                 0x00008000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_SHIFT                15
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_DEFAULT              0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK                0x00007000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT               12
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK [11:11] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_MASK                   0x00000800
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_SHIFT                  11
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE1 [10:09] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_MASK              0x00000600
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_SHIFT             9
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY [08:08] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_MASK                   0x00000100
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_SHIFT                  8
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                   0x00000080
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                  7
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                   0x00000040
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                  6
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                   0x00000020
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                  5
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                   0x00000010
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                  4
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK                     0x0000000c
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                    2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                  0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT          0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK              0x00000001
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT             0
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT           0x00000000
+
+/***************************************************************************
+ *UTMI_CTL_2 - UTMI Control 2 Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK               0xffffffff
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT              0
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SPARE1 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE1 :: SPARE1_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *SPARE2 - Spare2 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE2 :: SPARE2_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_DEFAULT                   0x00000000
+
+#endif /* #ifndef BCHP_USB_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/bchp_wktmr.h b/include/linux/brcmstb/7435b0/bchp_wktmr.h
new file mode 100644
index 0000000..5f8a022
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/bchp_wktmr.h
@@ -0,0 +1,108 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Dec  6 18:45:09 2011
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_wktmr.h $
+ * 
+ * Hydra_Software_Devel/2   12/7/11 5:06p mward
+ * SW7435-3: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_WKTMR_H__
+#define BCHP_WKTMR_H__
+
+/***************************************************************************
+ *WKTMR - Wakeup timer
+ ***************************************************************************/
+#define BCHP_WKTMR_EVENT                         0x00409580 /* Wakeup Timer Register */
+#define BCHP_WKTMR_COUNTER                       0x00409584 /* Wakeup Counter */
+#define BCHP_WKTMR_ALARM                         0x00409588 /* Wakeup Timer Alarm */
+#define BCHP_WKTMR_PRESCALER                     0x0040958c /* Wakeup Timer Prescaler */
+#define BCHP_WKTMR_PRESCALER_VAL                 0x00409590 /* Wakeup Timer Prescaler Value */
+
+/***************************************************************************
+ *EVENT - Wakeup Timer Register
+ ***************************************************************************/
+/* WKTMR :: EVENT :: reserved0 [31:01] */
+#define BCHP_WKTMR_EVENT_reserved0_MASK                            0xfffffffe
+#define BCHP_WKTMR_EVENT_reserved0_SHIFT                           1
+
+/* WKTMR :: EVENT :: wktmr_alarm_event [00:00] */
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_MASK                    0x00000001
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_SHIFT                   0
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *COUNTER - Wakeup Counter
+ ***************************************************************************/
+/* WKTMR :: COUNTER :: wktmr_counter [31:00] */
+#define BCHP_WKTMR_COUNTER_wktmr_counter_MASK                      0xffffffff
+#define BCHP_WKTMR_COUNTER_wktmr_counter_SHIFT                     0
+#define BCHP_WKTMR_COUNTER_wktmr_counter_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *ALARM - Wakeup Timer Alarm
+ ***************************************************************************/
+/* WKTMR :: ALARM :: wktmr_alarm [31:00] */
+#define BCHP_WKTMR_ALARM_wktmr_alarm_MASK                          0xffffffff
+#define BCHP_WKTMR_ALARM_wktmr_alarm_SHIFT                         0
+#define BCHP_WKTMR_ALARM_wktmr_alarm_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *PRESCALER - Wakeup Timer Prescaler
+ ***************************************************************************/
+/* WKTMR :: PRESCALER :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_reserved0_MASK                        0xfe000000
+#define BCHP_WKTMR_PRESCALER_reserved0_SHIFT                       25
+
+/* WKTMR :: PRESCALER :: wktmr_prescaler [24:00] */
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_MASK                  0x01ffffff
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_SHIFT                 0
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_DEFAULT               0x019bfcc0
+
+/***************************************************************************
+ *PRESCALER_VAL - Wakeup Timer Prescaler Value
+ ***************************************************************************/
+/* WKTMR :: PRESCALER_VAL :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_MASK                    0xfe000000
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_SHIFT                   25
+
+/* WKTMR :: PRESCALER_VAL :: wktmr_prescaler_val [24:00] */
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_MASK          0x01ffffff
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_SHIFT         0
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_DEFAULT       0x00000000
+
+#endif /* #ifndef BCHP_WKTMR_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7435b0/brcmirq.h b/include/linux/brcmstb/7435b0/brcmirq.h
new file mode 100644
index 0000000..30928bd
--- /dev/null
+++ b/include/linux/brcmstb/7435b0/brcmirq.h
@@ -0,0 +1,53 @@
+/*
+ * 7435a0 IRQ header file autogenerated by update_bchp.pl
+ * DO NOT EDIT THIS FILE BY HAND.
+ *
+ * Copyright (C) 2011 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BRCMIRQ_H_
+#define _BRCMIRQ_H_
+
+#define BRCM_IRQ_EHCI0_0	71
+#define BRCM_IRQ_EHCI0_1	72
+#define BRCM_IRQ_EHCI1_0	76
+#define BRCM_IRQ_EHCI1_1	77
+#define BRCM_IRQ_GENET_0_A	18
+#define BRCM_IRQ_GENET_0_B	19
+#define BRCM_IRQ_GENET_1_A	20
+#define BRCM_IRQ_GENET_1_B	21
+#define BRCM_IRQ_HIF		25
+#define BRCM_IRQ_HIF_SPI	26
+#define BRCM_IRQ_MOCA		33
+#define BRCM_IRQ_OHCI0_0	73
+#define BRCM_IRQ_OHCI0_1	74
+#define BRCM_IRQ_OHCI1_0	78
+#define BRCM_IRQ_OHCI1_1	79
+#define BRCM_IRQ_PCIE_INTA	36
+#define BRCM_IRQ_PCIE_INTB	37
+#define BRCM_IRQ_PCIE_INTC	38
+#define BRCM_IRQ_PCIE_INTD	39
+#define BRCM_IRQ_SATA		46
+#define BRCM_IRQ_SDIO0		48
+#define BRCM_IRQ_SDIO1		49
+#define BRCM_IRQ_STANDBY	55
+#define BRCM_IRQ_UARTA		67
+#define BRCM_IRQ_UARTB		68
+#define BRCM_IRQ_UARTC		69
+#define BRCM_IRQLIST_EHCI	{ 71, 72, 76, 77 }
+#define BRCM_IRQLIST_OHCI	{ 73, 74, 78, 79 }
+
+#endif /* _BRCMIRQ_H_ */
diff --git a/include/linux/brcmstb/7445a0/bchp_aon_ctrl.h b/include/linux/brcmstb/7445a0/bchp_aon_ctrl.h
new file mode 100644
index 0000000..cd353ed
--- /dev/null
+++ b/include/linux/brcmstb/7445a0/bchp_aon_ctrl.h
@@ -0,0 +1,1630 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Oct 17 03:11:32 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_CTRL_H__
+#define BCHP_AON_CTRL_H__
+
+/***************************************************************************
+ *AON_CTRL - AON Control Registers
+ ***************************************************************************/
+#define BCHP_AON_CTRL_RESET_CTRL                 0x00410000 /* Reset Control register for AON */
+#define BCHP_AON_CTRL_PM_CTRL                    0x00410004 /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_STATUS                  0x00410008 /* Status register for Power Controller */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS        0x0041000c /* Power Management IRQ input status */
+#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT          0x00410010 /* Power Management Wait counter in place of Wait for Host CPU IRQ */
+#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER     0x00410014 /* Power Good Guardband Timer for Host CPU */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER        0x00410018 /* Deep Standby Assertion Timer */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER         0x0041001c /* Deep Standby Wakeup Timer */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE    0x00410020 /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_LED_CTRL                0x00410024 /* LED set control register */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES     0x00410028 /* LED set control register */
+#define BCHP_AON_CTRL_HLCD_CTRL                  0x00410030 /* HW LED Clock Driver Control */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER    0x00410034 /* Second Fraction Counter Initial value */
+#define BCHP_AON_CTRL_TIME_COUNTER               0x00410038 /* Hour/Minute Counter Initial value */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0           0x0041003c /* Digit Code for digit 0, 1, 2, 3 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1           0x00410040 /* Digit Code for digit 4, 5, 6, 7 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2           0x00410044 /* Digit Code for digit 8, 9 */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET      0x00410048 /* Hour MSD/LSD and minute MSD/LSD address offset */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL            0x0041004c /* LED status control */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0             0x00410050 /* General control register 0 */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0           0x00410054 /* General status register 0 */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0     0x00410058 /* General control register without scan 0 */
+#define BCHP_AON_CTRL_SPARE_CTRL_0               0x00410060 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_SPARE_CTRL_1               0x00410064 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH          0x00410068 /* Scratch register */
+#define BCHP_AON_CTRL_RESET_HISTORY              0x0041006c /* Reset History Register For AON */
+#define BCHP_AON_CTRL_NMI_CTRL                   0x00410070 /* Control register for NMI */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL           0x00410074 /* Ana xtal low cur 40g m7fc gisb control */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL         0x00410078 /* Test_mode control register */
+#define BCHP_AON_CTRL_SUB_TEST_MODE              0x0041007c /* Register source for sub_test_mode */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE          0x00410080 /* Final latched testmode value */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE      0x00410084 /* Final latched sub-testmode value */
+#define BCHP_AON_CTRL_PM_INITIATE                0x00410088 /* Power down initiate */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS             0x0041008c /* Power up restore */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL   0x00410090 /* Ana xtal low cur 40g m7fc external CML control */
+
+/***************************************************************************
+ *RESET_CTRL - Reset Control register for AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_CTRL :: reserved0 [31:04] */
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_MASK                    0xfffffff0
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_SHIFT                   4
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [03:03] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000008
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 3
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable [02:02] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_MASK     0x00000004
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT    2
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_polarity [01:01] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK   0x00000002
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT  1
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_MASK          0x00000001
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_SHIFT         0
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PM_CTRL - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_CTRL :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_MASK                       0xffffff00
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_SHIFT                      8
+
+/* AON_CTRL :: PM_CTRL :: min_s3_width_timer_bypass [07:07] */
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_MASK       0x00000080
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_SHIFT      7
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_DEFAULT    0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_fast_power_down [06:06] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_MASK              0x00000040
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_SHIFT             6
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_DEFAULT           0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_warm_boot [05:05] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_MASK                    0x00000020
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_SHIFT                   5
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_DEFAULT                 0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_deep_standby [04:04] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_MASK                 0x00000010
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_SHIFT                4
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_DEFAULT              0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_enable_cpu_pwrdn [03:03] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_cpu_pwrdn_MASK             0x00000008
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_cpu_pwrdn_SHIFT            3
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_cpu_pwrdn_DEFAULT          0x00000001
+
+/* AON_CTRL :: PM_CTRL :: pm_use_cpu_ready_ctrl [02:02] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_cpu_ready_ctrl_MASK           0x00000004
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_cpu_ready_ctrl_SHIFT          2
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_cpu_ready_ctrl_DEFAULT        0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK             0x00000002
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT            1
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_DEFAULT          0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_MASK                  0x00000001
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT                 0
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PM_STATUS - Status register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_STATUS :: pm_wait_count_upper_bits [31:28] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_MASK      0xf0000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_SHIFT     28
+
+/* AON_CTRL :: PM_STATUS :: pm_wait_counter_active [27:27] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_MASK        0x08000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_SHIFT       27
+
+/* AON_CTRL :: PM_STATUS :: pm_power_down_cpu [26:26] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_down_cpu_MASK             0x04000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_down_cpu_SHIFT            26
+
+/* AON_CTRL :: PM_STATUS :: pm_cpu_reset_b [25:25] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_cpu_reset_b_MASK                0x02000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_cpu_reset_b_SHIFT               25
+
+/* AON_CTRL :: PM_STATUS :: pm_s3_wakeup_reset_ [24:24] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__MASK           0x01000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__SHIFT          24
+
+/* AON_CTRL :: PM_STATUS :: pm_boundary_scan_request [23:23] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_MASK      0x00800000
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_SHIFT     23
+
+/* AON_CTRL :: PM_STATUS :: pm_fast_pd_precharge_valid [22:22] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_MASK    0x00400000
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_SHIFT   22
+
+/* AON_CTRL :: PM_STATUS :: pm_led_out [21:21] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_MASK                    0x00200000
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_SHIFT                   21
+
+/* AON_CTRL :: PM_STATUS :: pm_standby_b [20:20] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_MASK                  0x00100000
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_SHIFT                 20
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs_ng [19:19] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_MASK           0x00080000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_SHIFT          19
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs [18:18] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_MASK              0x00040000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_SHIFT             18
+
+/* AON_CTRL :: PM_STATUS :: pm_s2_standby [17:17] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_s2_standby_MASK                 0x00020000
+#define BCHP_AON_CTRL_PM_STATUS_pm_s2_standby_SHIFT                17
+
+/* AON_CTRL :: PM_STATUS :: pm_pwrdn_pll_req [16:16] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_MASK              0x00010000
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_SHIFT             16
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_xtal_clocks [15:15] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_MASK            0x00008000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_SHIFT           15
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_all_clocks [14:14] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_MASK             0x00004000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_SHIFT            14
+
+/* AON_CTRL :: PM_STATUS :: pm_dphy_standby [13:13] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_MASK               0x00002000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_SHIFT              13
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_cpu_clock [12:12] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_MASK              0x00001000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_SHIFT             12
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_avd_rptd_clock [11:11] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_MASK         0x00000800
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_SHIFT        11
+
+/* AON_CTRL :: PM_STATUS :: pm_power_ctrl_disable [10:10] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_MASK         0x00000400
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_SHIFT        10
+
+/* AON_CTRL :: PM_STATUS :: pm_pll_lock [09:09] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_MASK                   0x00000200
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_SHIFT                  9
+
+/* AON_CTRL :: PM_STATUS :: pm_dram_ready_for_pwrdn [08:08] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_MASK       0x00000100
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_SHIFT      8
+
+/* AON_CTRL :: PM_STATUS :: pm_bsp_ready_for_pwrdn [07:07] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK        0x00000080
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_SHIFT       7
+
+/* AON_CTRL :: PM_STATUS :: pm_cpu_ready_for_pwrdn [06:06] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_cpu_ready_for_pwrdn_MASK        0x00000040
+#define BCHP_AON_CTRL_PM_STATUS_pm_cpu_ready_for_pwrdn_SHIFT       6
+
+/* AON_CTRL :: PM_STATUS :: pm_sec_avd_rptd_clk_disable [05:05] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_MASK   0x00000020
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_SHIFT  5
+
+/* AON_CTRL :: PM_STATUS :: pm_state [04:00] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_MASK                      0x0000001f
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_SHIFT                     0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_ACTIVE                 0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_PWRDN_RDY              1
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_AVD_RPTD       2
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_CPU            3
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_STANDBY  4
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY                5
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY_WITH_PLLS_ON   6
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_HOLD_CPU_POWERED_DOWN  7
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_POWER_UP_CPU           8
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_ACTIVE   9
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_FAST_PWRDN             10
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S1  11
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_COLD_ENTRY_S2 12
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_WARM_ENTRY_S2 13
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S3  14
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY           15
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S1   16
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S2   17
+
+/***************************************************************************
+ *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
+ ***************************************************************************/
+/* AON_CTRL :: PM_IRQ_INPUT_STATUS :: pm_irq_input_status [31:00] */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_MASK 0xffffffff
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_SHIFT 0
+
+/***************************************************************************
+ *PM_CPU_WAIT_COUNT - Power Management Wait counter in place of Wait for Host CPU IRQ
+ ***************************************************************************/
+/* AON_CTRL :: PM_CPU_WAIT_COUNT :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT_reserved0_MASK             0xffff0000
+#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT_reserved0_SHIFT            16
+
+/* AON_CTRL :: PM_CPU_WAIT_COUNT :: counter_start_value [15:00] */
+#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT_counter_start_value_MASK   0x0000ffff
+#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT_counter_start_value_SHIFT  0
+#define BCHP_AON_CTRL_PM_CPU_WAIT_COUNT_counter_start_value_DEFAULT 0x00000010
+
+/***************************************************************************
+ *PM_CPU_GUARDBAND_TIMER - Power Good Guardband Timer for Host CPU
+ ***************************************************************************/
+/* AON_CTRL :: PM_CPU_GUARDBAND_TIMER :: reserved0 [31:10] */
+#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER_reserved0_MASK        0xfffffc00
+#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER_reserved0_SHIFT       10
+
+/* AON_CTRL :: PM_CPU_GUARDBAND_TIMER :: counter_start_value [09:00] */
+#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER_counter_start_value_MASK 0x000003ff
+#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_CPU_GUARDBAND_TIMER_counter_start_value_DEFAULT 0x0000007f
+
+/***************************************************************************
+ *PM_S3_STANDBY_TIMER - Deep Standby Assertion Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_MASK           0xf8000000
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_SHIFT          27
+
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_MASK 0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_DEFAULT 0x00083d60
+
+/***************************************************************************
+ *PM_S3_WAKEUP_TIMER - Deep Standby Wakeup Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_MASK            0xf8000000
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_SHIFT           27
+
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_MASK  0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_DEFAULT 0x00083d60
+
+/***************************************************************************
+ *PM_FAST_PWRDN_PRECHARGE - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: reserved0 [31:24] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_MASK       0xff000000
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_SHIFT      24
+
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: pm_fast_power_down_precharge [23:00] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_MASK 0x00ffffff
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_SHIFT 0
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PM_LED_CTRL - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_CTRL :: reserved0 [31:03] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_MASK                   0xfffffff8
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_SHIFT                  3
+
+/* AON_CTRL :: PM_LED_CTRL :: led_status [02:02] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_MASK                  0x00000004
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_SHIFT                 2
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_on [01:01] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_MASK                 0x00000002
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_SHIFT                1
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_off [00:00] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_MASK                0x00000001
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_SHIFT               0
+
+/***************************************************************************
+ *PM_LED_AUTO_ON_ENABLES - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_AUTO_ON_ENABLES :: led_status [31:00] */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_MASK       0xffffffff
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_SHIFT      0
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_DEFAULT    0x00000000
+
+/***************************************************************************
+ *HLCD_CTRL - HW LED Clock Driver Control
+ ***************************************************************************/
+/* AON_CTRL :: HLCD_CTRL :: reserved0 [31:02] */
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_MASK                     0xfffffffc
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_SHIFT                    2
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable_status [01:01] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_MASK            0x00000002
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_SHIFT           1
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable [00:00] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_MASK                   0x00000001
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_SHIFT                  0
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_DEFAULT                0x00000000
+
+/***************************************************************************
+ *SECOND_FRACTION_COUNTER - Second Fraction Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: reserved0 [31:25] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_MASK       0xfe000000
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_SHIFT      25
+
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: second_fraction_counter_init [24:00] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_MASK 0x01ffffff
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_SHIFT 0
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TIME_COUNTER - Hour/Minute Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: TIME_COUNTER :: reserved0 [31:20] */
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_MASK                  0xfff00000
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_SHIFT                 20
+
+/* AON_CTRL :: TIME_COUNTER :: hour_display_mode [19:19] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_MASK          0x00080000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_SHIFT         19
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: mode_12h_24h_init [18:18] */
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_MASK          0x00040000
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_SHIFT         18
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: am_pm_counter_init [17:17] */
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_MASK         0x00020000
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_SHIFT        17
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_DEFAULT      0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: hour_counter_init [16:12] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_MASK          0x0001f000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_SHIFT         12
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: minute_counter_init [11:06] */
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_MASK        0x00000fc0
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_SHIFT       6
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_DEFAULT     0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: second_counter_init [05:00] */
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_MASK        0x0000003f
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_SHIFT       0
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_DEFAULT     0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_0 - Digit Code for digit 0, 1, 2, 3
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_3 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_2 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_1 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_0 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_1 - Digit Code for digit 4, 5, 6, 7
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_7 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_6 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_5 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_4 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_2 - Digit Code for digit 8, 9
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_MASK              0xffff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_SHIFT             16
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_9 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_8 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_ADDR_OFFSET - Hour MSD/LSD and minute MSD/LSD address offset
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_msd_addr_offset [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_MASK 0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_SHIFT 24
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_DEFAULT 0x00000020
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_lsd_addr_offset [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_MASK 0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_SHIFT 16
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_DEFAULT 0x00000024
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_msd_addr_offset [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_MASK 0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_SHIFT 8
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_DEFAULT 0x00000018
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_lsd_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_MASK 0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_SHIFT 0
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_DEFAULT 0x0000001c
+
+/***************************************************************************
+ *LED_STATUS_CTRL - LED status control
+ ***************************************************************************/
+/* AON_CTRL :: LED_STATUS_CTRL :: reserved0 [31:28] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_MASK               0xf0000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_SHIFT              28
+
+/* AON_CTRL :: LED_STATUS_CTRL :: hlcd_state [27:25] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_MASK              0x0e000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_SHIFT             25
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_IDLE         0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_COUNT        1
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_LSD 2
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_MSD 3
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_LSD 4
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_MSD 5
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_STATUS 6
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_update_enable [24:24] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_MASK    0x01000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_SHIFT   24
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_DEFAULT 0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_mask [23:12] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_MASK             0x00fff000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_SHIFT            12
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_DEFAULT          0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_bit_offset [11:08] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_MASK       0x00000f00
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_SHIFT      8
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_DEFAULT    0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_MASK      0x000000ff
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_SHIFT     0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK         0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT        31
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK         0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT        30
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK         0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT        29
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK         0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT        28
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK         0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT        27
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK         0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT        26
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK         0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT        25
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK         0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT        24
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK         0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT        23
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK         0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT        22
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK         0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT        21
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK         0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT        20
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK         0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT        19
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK         0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT        18
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK         0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT        17
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK         0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT        16
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK         0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT        15
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK         0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT        14
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK         0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT        13
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK         0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT        12
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK         0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT        11
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK         0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT        10
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK          0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT         9
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK          0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT         8
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK          0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT         7
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK          0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT         6
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK          0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT         5
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK          0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT         4
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK          0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT         3
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK          0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT         2
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK          0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT         1
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK          0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT         0
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT       0x00000000
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_MASK              0xffffff00
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_SHIFT             8
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_MASK      0x00000080
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT     7
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_MASK      0x00000040
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT     6
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_MASK      0x00000020
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT     5
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_MASK      0x00000010
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT     4
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_MASK      0x00000008
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT     3
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_MASK      0x00000004
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT     2
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_MASK      0x00000002
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT     1
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: ejtag_ce_wakeup_event [00:00] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_MASK  0x00000001
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_MASK 0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_SHIFT 31
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_MASK 0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_SHIFT 30
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_MASK 0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_SHIFT 29
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_MASK 0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_SHIFT 28
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_MASK 0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_SHIFT 27
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_MASK 0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_SHIFT 26
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_MASK 0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_SHIFT 25
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_MASK 0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_SHIFT 24
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_MASK 0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_SHIFT 23
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_MASK 0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_SHIFT 22
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_MASK 0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_SHIFT 21
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_MASK 0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_SHIFT 20
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_MASK 0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_SHIFT 19
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_MASK 0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_SHIFT 18
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_MASK 0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_SHIFT 17
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_MASK 0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_SHIFT 16
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_MASK 0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_SHIFT 15
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_MASK 0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_SHIFT 14
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_MASK 0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_SHIFT 13
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_MASK 0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_SHIFT 12
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_MASK 0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_SHIFT 11
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_MASK 0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_SHIFT 10
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_MASK 0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_SHIFT 5
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_MASK 0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_SHIFT 4
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_MASK 0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_SHIFT 3
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_MASK 0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_SHIFT 2
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_MASK 0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_SHIFT 0
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL_0 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_DEFAULT           0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL_1 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_DEFAULT           0x00000000
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* AON_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK     0xffffffff
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT    0
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT  0x00000000
+
+/***************************************************************************
+ *RESET_HISTORY - Reset History Register For AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_HISTORY :: reserved0 [31:21] */
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_MASK                 0xffe00000
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_SHIFT                21
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [20:20] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK    0x00100000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT   20
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [19:19] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK    0x00080000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT   19
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [18:18] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK     0x00040000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT    18
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [17:17] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK     0x00020000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT    17
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: scpu_ejtag_reset [16:16] */
+#define BCHP_AON_CTRL_RESET_HISTORY_scpu_ejtag_reset_MASK          0x00010000
+#define BCHP_AON_CTRL_RESET_HISTORY_scpu_ejtag_reset_SHIFT         16
+#define BCHP_AON_CTRL_RESET_HISTORY_scpu_ejtag_reset_DEFAULT       0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [15:15] */
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK           0x00008000
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT          15
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_DEFAULT        0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: overtemp_reset [14:14] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_MASK            0x00004000
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_SHIFT           14
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_DEFAULT         0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: overvoltage_1_reset [13:13] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_1_reset_MASK       0x00002000
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_1_reset_SHIFT      13
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_1_reset_DEFAULT    0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: undervoltage_1_reset [12:12] */
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_1_reset_MASK      0x00001000
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_1_reset_SHIFT     12
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_1_reset_DEFAULT   0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: undervoltage_0_reset [11:11] */
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_0_reset_MASK      0x00000800
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_0_reset_SHIFT     11
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_0_reset_DEFAULT   0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: security_master_reset [10:10] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_MASK     0x00000400
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_SHIFT    10
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: software_master_reset [09:09] */
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_MASK     0x00000200
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_SHIFT    9
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: pcie_1_hot_boot_reset [08:08] */
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_MASK     0x00000100
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_SHIFT    8
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: pcie_0_hot_boot_reset [07:07] */
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_MASK     0x00000080
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_SHIFT    7
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: watchdog_timer_reset [06:06] */
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK      0x00000040
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT     6
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_DEFAULT   0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: smartcard_insert_reset [05:05] */
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK    0x00000020
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT   5
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: s3_wakeup_reset [04:04] */
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_MASK           0x00000010
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_SHIFT          4
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_DEFAULT        0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [03:03] */
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK    0x00000008
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT   3
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: tap_in_system_reset [02:02] */
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_MASK       0x00000004
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_SHIFT      2
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_DEFAULT    0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_MASK     0x00000002
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT    1
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_MASK            0x00000001
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_SHIFT           0
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_DEFAULT         0x00000001
+
+/***************************************************************************
+ *NMI_CTRL - Control register for NMI
+ ***************************************************************************/
+/* AON_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_MASK                0x80000000
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_SHIFT               31
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_DEFAULT             0x00000000
+
+/* AON_CTRL :: NMI_CTRL :: reserved0 [30:03] */
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_MASK                      0x7ffffff8
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_SHIFT                     3
+
+/* AON_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_MASK                0x00000004
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT               2
+
+/* AON_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_MASK            0x00000002
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT           1
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_DEFAULT         0x00000000
+
+/* AON_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_MASK                0x00000001
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT               0
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_DEFAULT             0x00000001
+
+/***************************************************************************
+ *ANA_XTAL_CONTROL - Ana xtal low cur 40g m7fc gisb control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_CONTROL :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_MASK              0xffffff00
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_SHIFT             8
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_select_current_gisb_control [07:07] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_MASK 0x00000080
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_SHIFT 7
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_cml_sel_pd [06:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_MASK         0x00000078
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_SHIFT        3
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_DEFAULT      0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_d2cbias_gisb_control [02:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_MASK 0x00000007
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_SHIFT 0
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_DEFAULT 0x00000004
+
+/***************************************************************************
+ *SUB_TEST_MODE_CTRL - Test_mode control register
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: reserved0 [31:01] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_MASK            0xfffffffe
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_SHIFT           1
+
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: use_sub_test_mode_reg_src [00:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_MASK 0x00000001
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_SHIFT 0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SUB_TEST_MODE - Register source for sub_test_mode
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_MASK                 0xffffff00
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_SHIFT                8
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [07:07] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK     0x00000080
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT    7
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_DEFAULT  0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [06:06] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK     0x00000040
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT    6
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_DEFAULT  0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [05:05] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK   0x00000020
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT  5
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_cpu_in_reset [04:04] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_cpu_in_reset_MASK 0x00000010
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_cpu_in_reset_SHIFT 4
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_cpu_in_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [03:03] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000008
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 3
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [02:02] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000004
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 2
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK   0x00000003
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT  0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_DEFAULT 0x00000000
+
+/***************************************************************************
+ *LATCHED_TEST_MODE - Final latched testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK     0xffffffff
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT    0
+
+/***************************************************************************
+ *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0
+
+/***************************************************************************
+ *PM_INITIATE - Power down initiate
+ ***************************************************************************/
+/* AON_CTRL :: PM_INITIATE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_MASK                   0xffffff00
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_SHIFT                  8
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_7 [07:07] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_MASK               0x00000080
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_SHIFT              7
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_6 [06:06] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_MASK               0x00000040
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_SHIFT              6
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_5 [05:05] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_MASK               0x00000020
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_SHIFT              5
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_4 [04:04] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_MASK               0x00000010
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_SHIFT              4
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_3 [03:03] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_MASK               0x00000008
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_SHIFT              3
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_2 [02:02] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_MASK               0x00000004
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_SHIFT              2
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_1 [01:01] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_MASK               0x00000002
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_SHIFT              1
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_0 [00:00] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_MASK               0x00000001
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_SHIFT              0
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_DEFAULT            0x00000000
+
+/***************************************************************************
+ *HOST_MISC_CMDS - Power up restore
+ ***************************************************************************/
+/* AON_CTRL :: HOST_MISC_CMDS :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_MASK                0xffffff00
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_SHIFT               8
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_7 [07:07] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_MASK         0x00000080
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_SHIFT        7
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_6 [06:06] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_MASK         0x00000040
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_SHIFT        6
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_5 [05:05] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_MASK         0x00000020
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_SHIFT        5
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_4 [04:04] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_MASK         0x00000010
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_SHIFT        4
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_3 [03:03] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_MASK         0x00000008
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_SHIFT        3
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_2 [02:02] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_MASK         0x00000004
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_SHIFT        2
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: dram_scram_key_reuse_req [01:01] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_MASK 0x00000002
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_SHIFT 1
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_DEFAULT 0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: pm_restore [00:00] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_MASK               0x00000001
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_SHIFT              0
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ANA_XTAL_EXT_CML_CONTROL - Ana xtal low cur 40g m7fc external CML control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: reserved0 [31:06] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_reserved0_MASK      0xffffffc0
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_reserved0_SHIFT     6
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_PMSM_S3_pd_buffer [05:05] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_MASK 0x00000020
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_SHIFT 5
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_override_strap [04:04] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_MASK 0x00000010
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_SHIFT 4
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_pd_buffer [03:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_MASK  0x00000008
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_SHIFT 3
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_div2_sel [02:02] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_MASK   0x00000004
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_SHIFT  2
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_DEFAULT 0x00000001
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_current [01:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_MASK    0x00000003
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_SHIFT   0
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_BASE                  0x00410200
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_START                 0
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_END                   127
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_ELEMENT_SIZE          32
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_RAMi :: SYSTEM_DATA_RAM [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_MASK        0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_SHIFT       0
+
+
+#endif /* #ifndef BCHP_AON_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7445a0/bchp_aon_pin_ctrl.h b/include/linux/brcmstb/7445a0/bchp_aon_pin_ctrl.h
new file mode 100644
index 0000000..3acd3d0
--- /dev/null
+++ b/include/linux/brcmstb/7445a0/bchp_aon_pin_ctrl.h
@@ -0,0 +1,424 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Oct 17 03:11:31 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PIN_CTRL_H__
+#define BCHP_AON_PIN_CTRL_H__
+
+/***************************************************************************
+ *AON_PIN_CTRL - AON Pinmux Control Registers
+ ***************************************************************************/
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0         0x00410500 /* Pinmux control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1         0x00410504 /* Pinmux control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2         0x00410508 /* Pinmux control register 2 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0     0x0041050c /* Pad pull-up/pull-down control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1     0x00410510 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0     0x00410514 /* Bypass clock unselect register 0 */
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_07 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_AON_GPIO_07   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_LED_LS_3      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_UART_RTS_0    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_07_LED_LD_15     3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_06 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_AON_GPIO_06   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_LED_LS_2      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_LED_LD_14     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_06_SPI_M_SS2B    3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_05 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_AON_GPIO_05   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_LS_1      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_LD_13     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SPI_M_SS1B    3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_04 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_AON_GPIO_04   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_LS_0      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_LD_12     2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_03 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_GPIO_03   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_KD_3      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_LD_11     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_I2S_LR0_IN    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_I2S_LR0_OUT   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_ENET0_ACTIVITY 5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PM_AON_GPIO_03 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_02 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_AON_GPIO_02   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_LED_KD_2      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_LED_LD_10     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_I2S_DATA0_IN  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_I2S_DATA0_OUT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_MDIO_SATA     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_PM_AON_GPIO_02 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_01 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AON_GPIO_01   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_LED_KD_1      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_LED_LD_9      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_I2S_CLK0_IN   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_I2S_CLK0_OUT  4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SATA_MDCLK    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_PM_AON_GPIO_01 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_00 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AON_GPIO_00   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_LED_KD_0      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_LED_LD_8      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_PM_AON_GPIO_00 3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_15 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_AON_GPIO_15   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_LED_LD_6      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_UART_CTS_2    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_SPI_M_MISO    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_ENET0_ACTIVITY 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_ENET1_ACTIVITY 5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_ENET2_ACTIVITY 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_PM_AON_GPIO_15 7
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_14 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_AON_GPIO_14   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_LED_LD_5      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_UART_TXD_2    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_14_SPI_M_MOSI    3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_13 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_AON_GPIO_13   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_LED_LD_4      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_UART_RXD_2    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SPI_M_SCK     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_ENET0_LINK    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_ENET1_LINK    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_ENET2_LINK    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PM_AON_GPIO_13 7
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_12 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_AON_GPIO_12   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_LD_3      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_UART_CTS_1    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_I2S_LR0_OUT   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_I2S_LR0_IN    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PM_AON_GPIO_12 5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_11 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_GPIO_11   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_LED_LD_2      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_UART_RTS_1    2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_10 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_AON_GPIO_10   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_LED_LD_1      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_UART_CTS_0    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_I2S_DATA0_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_I2S_DATA0_IN  4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_PM_AON_GPIO_10 5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_09 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_AON_GPIO_09   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_LED_LD_0      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_UART_RXD_1    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_I2S_CLK0_OUT  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_I2S_CLK0_IN   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_IR_IN1        5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_PM_AON_GPIO_09 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_08 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_AON_GPIO_08   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_LED_LS_4      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_UART_TXD_1    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_ENET0_LINK    3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_05 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_05_MASK         0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_05_SHIFT        28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_05_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_05_AON_SGPIO_05 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_05_BSC_M2_SDA   1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_04 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_04_MASK         0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_04_SHIFT        24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_04_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_04_AON_SGPIO_04 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_04_BSC_M2_SCL   1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_03 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_MASK         0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_SHIFT        20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_AON_SGPIO_03 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_BSC_M1_SDA   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_HDMI_RX_BSC_SDA 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_BSC_S1_SDA   3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_02 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_MASK         0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_SHIFT        16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_AON_SGPIO_02 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_BSC_M1_SCL   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_HDMI_RX_BSC_SCL 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_BSC_S1_SCL   3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_01 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_MASK         0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_SHIFT        12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_AON_SGPIO_01 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_BSC_M0_SDA   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_HDMI_TX_BSC_SDA 2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_00 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_MASK         0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SHIFT        8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_AON_SGPIO_00 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_BSC_M0_SCL   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_HDMI_TX_BSC_SCL 2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_17 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_DEFAULT       0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_AON_GPIO_17   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_LED_OUT       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_ENET1_LINK    2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_16 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_AON_GPIO_16   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_LED_LD_7      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_UART_RTS_2    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SPI_M_SS0B    3
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_12_pad_ctrl [29:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_MASK 0x30000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_SHIFT 28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [27:26] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x0c000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       26
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_10_pad_ctrl [25:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_10_pad_ctrl_MASK 0x03000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_10_pad_ctrl_SHIFT 24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_10_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_10_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_09_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved1 [21:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_MASK        0x003ff000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_SHIFT       12
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_03_pad_ctrl [11:10] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_MASK 0x00000c00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_SHIFT 10
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_02_pad_ctrl [09:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_MASK 0x00000300
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_SHIFT 8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_01_pad_ctrl [07:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_MASK 0x000000c0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_SHIFT 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_00_pad_ctrl [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved2 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved2_MASK        0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved2_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [31:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0xff000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       24
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved1 [21:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved1_MASK        0x003fffc0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved1_SHIFT       6
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_15_pad_ctrl [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved2 [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved2_MASK        0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved2_SHIFT       2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_13_pad_ctrl [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_MASK 0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_SHIFT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:01] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffffe
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       1
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_01 [00:00] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_01_MASK 0x00000001
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_01_SHIFT 0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_01_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_AON_PIN_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7445a0/bchp_aon_pm_l2.h b/include/linux/brcmstb/7445a0/bchp_aon_pm_l2.h
new file mode 100644
index 0000000..8bf628a
--- /dev/null
+++ b/include/linux/brcmstb/7445a0/bchp_aon_pm_l2.h
@@ -0,0 +1,1152 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Oct 17 03:11:32 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PM_L2_H__
+#define BCHP_AON_PM_L2_H__
+
+/***************************************************************************
+ *AON_PM_L2 - AON Power Management L2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_AON_PM_L2_CPU_STATUS                0x00410440 /* CPU interrupt Status Register */
+#define BCHP_AON_PM_L2_CPU_SET                   0x00410444 /* CPU interrupt Set Register */
+#define BCHP_AON_PM_L2_CPU_CLEAR                 0x00410448 /* CPU interrupt Clear Register */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS           0x0041044c /* CPU interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_CPU_MASK_SET              0x00410450 /* CPU interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR            0x00410454 /* CPU interrupt Mask Clear Register */
+#define BCHP_AON_PM_L2_PCI_STATUS                0x00410458 /* PCI interrupt Status Register */
+#define BCHP_AON_PM_L2_PCI_SET                   0x0041045c /* PCI interrupt Set Register */
+#define BCHP_AON_PM_L2_PCI_CLEAR                 0x00410460 /* PCI interrupt Clear Register */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS           0x00410464 /* PCI interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_PCI_MASK_SET              0x00410468 /* PCI interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR            0x0041046c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_STATUS :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_MASK                   0xfffe0000
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_SHIFT                  17
+
+/* AON_PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x00010000
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       16
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_MASK                    0x00008000
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_SHIFT                   15
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00004000
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_SHIFT          14
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_MASK                        0x00002000
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_SHIFT                       13
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_MASK                        0x00001000
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_SHIFT                       12
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_MASK                        0x00000800
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_SHIFT                       11
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_MASK                     0x00000400
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_SHIFT                    10
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: CAP [09:09] */
+#define BCHP_AON_PM_L2_CPU_STATUS_CAP_MASK                         0x00000200
+#define BCHP_AON_PM_L2_CPU_STATUS_CAP_SHIFT                        9
+#define BCHP_AON_PM_L2_CPU_STATUS_CAP_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_GENET2 [08:08] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET2_MASK                  0x00000100
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET2_SHIFT                 8
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_GENET1 [07:07] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET1_MASK                  0x00000080
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET1_SHIFT                 7
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET1_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_GENET0 [06:06] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET0_MASK                  0x00000040
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET0_SHIFT                 6
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_GENET0_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_SET :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_MASK                      0xfffe0000
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_SHIFT                     17
+
+/* AON_PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_MASK           0x00010000
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_SHIFT          16
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_MASK                       0x00008000
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_SHIFT                      15
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_MASK              0x00004000
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_SHIFT             14
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_DEFAULT           0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_CPU_SET_USB1_MASK                           0x00002000
+#define BCHP_AON_PM_L2_CPU_SET_USB1_SHIFT                          13
+#define BCHP_AON_PM_L2_CPU_SET_USB1_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_CPU_SET_USB0_MASK                           0x00001000
+#define BCHP_AON_PM_L2_CPU_SET_USB0_SHIFT                          12
+#define BCHP_AON_PM_L2_CPU_SET_USB0_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_MASK                           0x00000800
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_SHIFT                          11
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_MASK                        0x00000400
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_SHIFT                       10
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: CAP [09:09] */
+#define BCHP_AON_PM_L2_CPU_SET_CAP_MASK                            0x00000200
+#define BCHP_AON_PM_L2_CPU_SET_CAP_SHIFT                           9
+#define BCHP_AON_PM_L2_CPU_SET_CAP_DEFAULT                         0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: WOL_GENET2 [08:08] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET2_MASK                     0x00000100
+#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET2_SHIFT                    8
+
+/* AON_PM_L2 :: CPU_SET :: WOL_GENET1 [07:07] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET1_MASK                     0x00000080
+#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET1_SHIFT                    7
+#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET1_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: WOL_GENET0 [06:06] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET0_MASK                     0x00000040
+#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET0_SHIFT                    6
+#define BCHP_AON_PM_L2_CPU_SET_WOL_GENET0_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_CLEAR :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_MASK                    0xfffe0000
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_SHIFT                   17
+
+/* AON_PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x00010000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        16
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_MASK                     0x00008000
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_SHIFT                    15
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00004000
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           14
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_MASK                         0x00002000
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_SHIFT                        13
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_MASK                         0x00001000
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_SHIFT                        12
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_MASK                         0x00000800
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_SHIFT                        11
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_MASK                      0x00000400
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT                     10
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: CAP [09:09] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_CAP_MASK                          0x00000200
+#define BCHP_AON_PM_L2_CPU_CLEAR_CAP_SHIFT                         9
+#define BCHP_AON_PM_L2_CPU_CLEAR_CAP_DEFAULT                       0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_GENET2 [08:08] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET2_MASK                   0x00000100
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET2_SHIFT                  8
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_GENET1 [07:07] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET1_MASK                   0x00000080
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET1_SHIFT                  7
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET1_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_GENET0 [06:06] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET0_MASK                   0x00000040
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET0_SHIFT                  6
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_GENET0_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_MASK              0xfffe0000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT             17
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x00010000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  16
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_MASK               0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_SHIFT              15
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     14
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_MASK                   0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_SHIFT                  13
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_MASK                   0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_SHIFT                  12
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_MASK                   0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_SHIFT                  11
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK                0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT               10
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: CAP [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CAP_MASK                    0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CAP_SHIFT                   9
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CAP_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_GENET2 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET2_MASK             0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET2_SHIFT            8
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_GENET1 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET1_MASK             0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET1_SHIFT            7
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET1_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_GENET0 [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET0_MASK             0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET0_SHIFT            6
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_GENET0_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_DEFAULT            0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_SET :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_MASK                 0xfffe0000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_SHIFT                17
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x00010000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     16
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_MASK                  0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_SHIFT                 15
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        14
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_MASK                      0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_SHIFT                     13
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_MASK                      0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_SHIFT                     12
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_MASK                      0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_SHIFT                     11
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_MASK                   0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT                  10
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: CAP [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CAP_MASK                       0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CAP_SHIFT                      9
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CAP_DEFAULT                    0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_GENET2 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET2_MASK                0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET2_SHIFT               8
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_GENET1 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET1_MASK                0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET1_SHIFT               7
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET1_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_GENET0 [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET0_MASK                0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET0_SHIFT               6
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_GENET0_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_DEFAULT               0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_MASK               0xfffe0000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT              17
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x00010000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   16
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_MASK                0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_SHIFT               15
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      14
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_MASK                    0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_SHIFT                   13
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_MASK                    0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_SHIFT                   12
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_MASK                    0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_SHIFT                   11
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK                 0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT                10
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: CAP [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CAP_MASK                     0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CAP_SHIFT                    9
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CAP_DEFAULT                  0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_GENET2 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET2_MASK              0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET2_SHIFT             8
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_GENET1 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET1_MASK              0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET1_SHIFT             7
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET1_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_GENET0 [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET0_MASK              0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET0_SHIFT             6
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_GENET0_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_DEFAULT             0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_STATUS :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_MASK                   0xfffe0000
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_SHIFT                  17
+
+/* AON_PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x00010000
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       16
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_MASK                    0x00008000
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_SHIFT                   15
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00004000
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_SHIFT          14
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_MASK                        0x00002000
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_SHIFT                       13
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_MASK                        0x00001000
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_SHIFT                       12
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_MASK                        0x00000800
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_SHIFT                       11
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_MASK                     0x00000400
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_SHIFT                    10
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: CAP [09:09] */
+#define BCHP_AON_PM_L2_PCI_STATUS_CAP_MASK                         0x00000200
+#define BCHP_AON_PM_L2_PCI_STATUS_CAP_SHIFT                        9
+#define BCHP_AON_PM_L2_PCI_STATUS_CAP_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_GENET2 [08:08] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET2_MASK                  0x00000100
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET2_SHIFT                 8
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_GENET1 [07:07] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET1_MASK                  0x00000080
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET1_SHIFT                 7
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET1_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_GENET0 [06:06] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET0_MASK                  0x00000040
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET0_SHIFT                 6
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_GENET0_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_SET :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_MASK                      0xfffe0000
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_SHIFT                     17
+
+/* AON_PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_MASK           0x00010000
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_SHIFT          16
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_MASK                       0x00008000
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_SHIFT                      15
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_MASK              0x00004000
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_SHIFT             14
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_DEFAULT           0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_PCI_SET_USB1_MASK                           0x00002000
+#define BCHP_AON_PM_L2_PCI_SET_USB1_SHIFT                          13
+#define BCHP_AON_PM_L2_PCI_SET_USB1_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_PCI_SET_USB0_MASK                           0x00001000
+#define BCHP_AON_PM_L2_PCI_SET_USB0_SHIFT                          12
+#define BCHP_AON_PM_L2_PCI_SET_USB0_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_MASK                           0x00000800
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_SHIFT                          11
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_MASK                        0x00000400
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_SHIFT                       10
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: CAP [09:09] */
+#define BCHP_AON_PM_L2_PCI_SET_CAP_MASK                            0x00000200
+#define BCHP_AON_PM_L2_PCI_SET_CAP_SHIFT                           9
+#define BCHP_AON_PM_L2_PCI_SET_CAP_DEFAULT                         0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: WOL_GENET2 [08:08] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET2_MASK                     0x00000100
+#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET2_SHIFT                    8
+
+/* AON_PM_L2 :: PCI_SET :: WOL_GENET1 [07:07] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET1_MASK                     0x00000080
+#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET1_SHIFT                    7
+#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET1_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: WOL_GENET0 [06:06] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET0_MASK                     0x00000040
+#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET0_SHIFT                    6
+#define BCHP_AON_PM_L2_PCI_SET_WOL_GENET0_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_CLEAR :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_MASK                    0xfffe0000
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_SHIFT                   17
+
+/* AON_PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x00010000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        16
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_MASK                     0x00008000
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_SHIFT                    15
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00004000
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           14
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_MASK                         0x00002000
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_SHIFT                        13
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_MASK                         0x00001000
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_SHIFT                        12
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_MASK                         0x00000800
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_SHIFT                        11
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_MASK                      0x00000400
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT                     10
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: CAP [09:09] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_CAP_MASK                          0x00000200
+#define BCHP_AON_PM_L2_PCI_CLEAR_CAP_SHIFT                         9
+#define BCHP_AON_PM_L2_PCI_CLEAR_CAP_DEFAULT                       0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_GENET2 [08:08] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET2_MASK                   0x00000100
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET2_SHIFT                  8
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_GENET1 [07:07] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET1_MASK                   0x00000080
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET1_SHIFT                  7
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET1_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_GENET0 [06:06] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET0_MASK                   0x00000040
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET0_SHIFT                  6
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_GENET0_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_MASK              0xfffe0000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT             17
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x00010000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  16
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_MASK               0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_SHIFT              15
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     14
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_MASK                   0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_SHIFT                  13
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_MASK                   0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_SHIFT                  12
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_MASK                   0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_SHIFT                  11
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK                0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT               10
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: CAP [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CAP_MASK                    0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CAP_SHIFT                   9
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CAP_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_GENET2 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET2_MASK             0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET2_SHIFT            8
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_GENET1 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET1_MASK             0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET1_SHIFT            7
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET1_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_GENET0 [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET0_MASK             0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET0_SHIFT            6
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_GENET0_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_DEFAULT            0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_SET :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_MASK                 0xfffe0000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_SHIFT                17
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x00010000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     16
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_MASK                  0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_SHIFT                 15
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        14
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_MASK                      0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_SHIFT                     13
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_MASK                      0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_SHIFT                     12
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_MASK                      0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_SHIFT                     11
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_MASK                   0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT                  10
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: CAP [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CAP_MASK                       0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CAP_SHIFT                      9
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CAP_DEFAULT                    0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_GENET2 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET2_MASK                0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET2_SHIFT               8
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_GENET1 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET1_MASK                0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET1_SHIFT               7
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET1_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_GENET0 [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET0_MASK                0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET0_SHIFT               6
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_GENET0_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_DEFAULT               0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:17] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_MASK               0xfffe0000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT              17
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x00010000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   16
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FP_RESET [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_MASK                0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_SHIFT               15
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: BOUNDARY_SCAN_REQ [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      14
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB1 [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_MASK                    0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_SHIFT                   13
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB0 [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_MASK                    0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_SHIFT                   12
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: MOCA [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_MASK                    0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_SHIFT                   11
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK                 0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT                10
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: CAP [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CAP_MASK                     0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CAP_SHIFT                    9
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CAP_DEFAULT                  0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_GENET2 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET2_MASK              0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET2_SHIFT             8
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_GENET1 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET1_MASK              0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET1_SHIFT             7
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET1_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_GENET0 [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET0_MASK              0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET0_SHIFT             6
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_GENET0_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_DEFAULT             0x00000001
+
+#endif /* #ifndef BCHP_AON_PM_L2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7445a0/bchp_bspi.h b/include/linux/brcmstb/7445a0/bchp_bspi.h
new file mode 100644
index 0000000..dbcf2c9
--- /dev/null
+++ b/include/linux/brcmstb/7445a0/bchp_bspi.h
@@ -0,0 +1,443 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Oct 17 03:11:31 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_H__
+#define BCHP_BSPI_H__
+
+/***************************************************************************
+ *BSPI - Public BSPI Control Registers
+ ***************************************************************************/
+#define BCHP_BSPI_REVISION_ID                    0x00443200 /* Revision ID */
+#define BCHP_BSPI_SCRATCH                        0x00443204 /* Revision ID */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL               0x00443208 /* Master/Boot SPI Control Register */
+#define BCHP_BSPI_BUSY_STATUS                    0x0044320c /* BSPI Busy Status Register */
+#define BCHP_BSPI_INTR_STATUS                    0x00443210 /* Interrupt Status Register */
+#define BCHP_BSPI_B0_STATUS                      0x00443214 /* Prefetch Buffer 0 Status Register */
+#define BCHP_BSPI_B0_CTRL                        0x00443218 /* Prefetch Buffer 0 Control Register */
+#define BCHP_BSPI_B1_STATUS                      0x0044321c /* Prefetch Buffer 1 Status Register */
+#define BCHP_BSPI_B1_CTRL                        0x00443220 /* Prefetch Buffer 1 Control Register */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL            0x00443224 /* Dual/Single Receive Mode Control Register */
+#define BCHP_BSPI_FLEX_MODE_ENABLE               0x00443228 /* Flexible Control Mode Enable Register */
+#define BCHP_BSPI_BITS_PER_CYCLE                 0x0044322c /* Bits per cycle "b-p-c" Control Register */
+#define BCHP_BSPI_BITS_PER_PHASE                 0x00443230 /* Bits per Phase "b-p-p" Control Register */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE              0x00443234 /* Command and Mode Data Register */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE     0x00443238 /* Bspi FLash upper address byte register */
+#define BCHP_BSPI_BSPI_XOR_VALUE                 0x0044323c /* BSPI FLASH XOR Value Register */
+#define BCHP_BSPI_BSPI_XOR_ENABLE                0x00443240 /* BSPI FLASH XOR Enable Register */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE           0x00443244 /* BSPI Pin  Programmed IO Mode Enable Register */
+#define BCHP_BSPI_BSPI_PIO_IODIR                 0x00443248 /* BSPI Pin  Programmed IO Mode Direction Register */
+#define BCHP_BSPI_BSPI_PIO_DATA                  0x0044324c /* BSPI Pin  Programmed IO Mode Data Register */
+
+/***************************************************************************
+ *REVISION_ID - Revision ID
+ ***************************************************************************/
+/* BSPI :: REVISION_ID :: reserved0 [31:16] */
+#define BCHP_BSPI_REVISION_ID_reserved0_MASK                       0xffff0000
+#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT                      16
+
+/* BSPI :: REVISION_ID :: MAJOR [15:08] */
+#define BCHP_BSPI_REVISION_ID_MAJOR_MASK                           0x0000ff00
+#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT                          8
+#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT                        0x00000004
+
+/* BSPI :: REVISION_ID :: MINOR [07:00] */
+#define BCHP_BSPI_REVISION_ID_MINOR_MASK                           0x000000ff
+#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT                          0
+#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT                        0x00000001
+
+/***************************************************************************
+ *SCRATCH - Revision ID
+ ***************************************************************************/
+/* BSPI :: SCRATCH :: SCRATCH [31:00] */
+#define BCHP_BSPI_SCRATCH_SCRATCH_MASK                             0xffffffff
+#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT                            0
+#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
+ ***************************************************************************/
+/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT                 1
+
+/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK                0x00000001
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT               0
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT             0x00000000
+
+/***************************************************************************
+ *BUSY_STATUS - BSPI Busy Status Register
+ ***************************************************************************/
+/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
+#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK                       0xfffffffe
+#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT                      1
+
+/* BSPI :: BUSY_STATUS :: busy [00:00] */
+#define BCHP_BSPI_BUSY_STATUS_busy_MASK                            0x00000001
+#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT                           0
+#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *INTR_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
+#define BCHP_BSPI_INTR_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT                      2
+
+/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
+#define BCHP_BSPI_INTR_STATUS_intr_1_MASK                          0x00000002
+#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT                         1
+#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT                       0x00000000
+
+/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
+#define BCHP_BSPI_INTR_STATUS_intr_0_MASK                          0x00000001
+#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT                         0
+#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *B0_STATUS - Prefetch Buffer 0 Status Register
+ ***************************************************************************/
+/* BSPI :: B0_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B0_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B0_STATUS :: b0_full [29:29] */
+#define BCHP_BSPI_B0_STATUS_b0_full_MASK                           0x20000000
+#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT                          29
+#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_empty [28:28] */
+#define BCHP_BSPI_B0_STATUS_b0_empty_MASK                          0x10000000
+#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT                         28
+#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B0_STATUS :: b0_miss [27:27] */
+#define BCHP_BSPI_B0_STATUS_b0_miss_MASK                           0x08000000
+#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT                          27
+#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_hit [26:26] */
+#define BCHP_BSPI_B0_STATUS_b0_hit_MASK                            0x04000000
+#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT                           26
+#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B0_STATUS :: b0_address [25:00] */
+#define BCHP_BSPI_B0_STATUS_b0_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT                       0
+#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B0_CTRL - Prefetch Buffer 0 Control Register
+ ***************************************************************************/
+/* BSPI :: B0_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B0_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B0_CTRL :: b0_flush [00:00] */
+#define BCHP_BSPI_B0_CTRL_b0_flush_MASK                            0x00000001
+#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT                           0
+#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *B1_STATUS - Prefetch Buffer 1 Status Register
+ ***************************************************************************/
+/* BSPI :: B1_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B1_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B1_STATUS :: b1_full [29:29] */
+#define BCHP_BSPI_B1_STATUS_b1_full_MASK                           0x20000000
+#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT                          29
+#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_empty [28:28] */
+#define BCHP_BSPI_B1_STATUS_b1_empty_MASK                          0x10000000
+#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT                         28
+#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B1_STATUS :: b1_miss [27:27] */
+#define BCHP_BSPI_B1_STATUS_b1_miss_MASK                           0x08000000
+#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT                          27
+#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_hit [26:26] */
+#define BCHP_BSPI_B1_STATUS_b1_hit_MASK                            0x04000000
+#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT                           26
+#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B1_STATUS :: b1_address [25:00] */
+#define BCHP_BSPI_B1_STATUS_b1_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT                       0
+#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B1_CTRL - Prefetch Buffer 1 Control Register
+ ***************************************************************************/
+/* BSPI :: B1_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B1_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B1_CTRL :: b1_flush [00:00] */
+#define BCHP_BSPI_B1_CTRL_b1_flush_MASK                            0x00000001
+#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT                           0
+#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
+ ***************************************************************************/
+/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK               0xffffffe0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT              5
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK             0x00000010
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT            4
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT          0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK               0x00000008
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT              3
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT            0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK      0x00000004
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT     2
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT   0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK         0x00000002
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT        1
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT      0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK                0x00000001
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT               0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT             0x00000000
+
+/***************************************************************************
+ *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT                 1
+
+/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK      0x00000001
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT     0
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT   0x00000000
+
+/***************************************************************************
+ *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK                    0xfc000000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT                   26
+
+/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK               0x03000000
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK                    0x00fc0000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT                   18
+
+/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK              0x00030000
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK                    0x0000fc00
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT                   10
+
+/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK              0x00000300
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT             8
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK                    0x000000fc
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT                   2
+
+/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK              0x00000003
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT             0
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT           0x00000000
+
+/***************************************************************************
+ *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK                    0xfe000000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT                   25
+
+/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK               0x01000000
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK                    0x00fe0000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT                   17
+
+/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK              0x00010000
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK                    0x0000fe00
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT                   9
+
+/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK                     0x00000100
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT                    8
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT                  0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK                 0x000000ff
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT                0
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT              0x00000008
+
+/***************************************************************************
+ *CMD_AND_MODE_BYTE - Command and Mode Data Register
+ ***************************************************************************/
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK                 0xff000000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT                24
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK            0x00ff0000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT           16
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT         0x00000000
+
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK                 0x0000ff00
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT                8
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK             0x000000ff
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT            0
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT          0x0000000b
+
+/***************************************************************************
+ *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
+ ***************************************************************************/
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0x00000000
+
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK        0x00ffffff
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT       0
+
+/***************************************************************************
+ *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK               0xfff00000
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT              20
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT            0x00000e00
+
+/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK                    0x000fffff
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT                  1
+
+/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK             0x00000001
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT            0
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT          0x00000001
+
+/***************************************************************************
+ *BSPI_PIO_MODE_ENABLE - BSPI Pin  Programmed IO Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK              0xfffffffe
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT             1
+
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK          0x00000001
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT         0
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT       0x00000000
+
+/***************************************************************************
+ *BSPI_PIO_IODIR - BSPI Pin  Programmed IO Mode Direction Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK                    0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT                   3
+
+/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT              0x00000003
+
+/***************************************************************************
+ *BSPI_PIO_DATA - BSPI Pin  Programmed IO Mode Data Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK                     0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT                    3
+
+/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT              0x00000000
+
+#endif /* #ifndef BCHP_BSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7445a0/bchp_bspi_raf.h b/include/linux/brcmstb/7445a0/bchp_bspi_raf.h
new file mode 100644
index 0000000..21fadaa
--- /dev/null
+++ b/include/linux/brcmstb/7445a0/bchp_bspi_raf.h
@@ -0,0 +1,160 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Oct 17 03:11:33 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_RAF_H__
+#define BCHP_BSPI_RAF_H__
+
+/***************************************************************************
+ *BSPI_RAF - Public Linear Read BSPI Pipe Registers
+ ***************************************************************************/
+#define BCHP_BSPI_RAF_START_ADDR                 0x00443300 /* Physical Starting Address Location in Flash device */
+#define BCHP_BSPI_RAF_NUM_WORDS                  0x00443304 /* Number of Words to be fetched */
+#define BCHP_BSPI_RAF_CTRL                       0x00443308 /* RAF Session Control Register */
+#define BCHP_BSPI_RAF_FULLNESS                   0x0044330c /* Fullness indicator for the read ahead buffer */
+#define BCHP_BSPI_RAF_WATERMARK                  0x00443310 /* Watermark level in the read ahead buffer that triggers an interrupt */
+#define BCHP_BSPI_RAF_STATUS                     0x00443314 /* Linear Read Status Register */
+#define BCHP_BSPI_RAF_READ_DATA                  0x00443318 /* Read data from Raf-buffer */
+#define BCHP_BSPI_RAF_WORD_CNT                   0x0044331c /* Current number of words fetched from Flash */
+#define BCHP_BSPI_RAF_CURR_ADDR                  0x00443320 /* Current read address for the linear read session */
+
+/***************************************************************************
+ *START_ADDR - Physical Starting Address Location in Flash device
+ ***************************************************************************/
+/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK                   0xffffffff
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT                  0
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT                0x00000000
+
+/***************************************************************************
+ *NUM_WORDS - Number of Words to be fetched
+ ***************************************************************************/
+/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK                      0xffffffff
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT                     0
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *CTRL - RAF Session Control Register
+ ***************************************************************************/
+/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT                         2
+
+/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
+#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK                              0x00000002
+#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT                             1
+#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT                           0x00000000
+
+/* BSPI_RAF :: CTRL :: START [00:00] */
+#define BCHP_BSPI_RAF_CTRL_START_MASK                              0x00000001
+#define BCHP_BSPI_RAF_CTRL_START_SHIFT                             0
+#define BCHP_BSPI_RAF_CTRL_START_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *FULLNESS - Fullness indicator for the read ahead buffer
+ ***************************************************************************/
+/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK                      0xffffff80
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT                     7
+
+/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK                       0x0000007f
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT                      0
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
+ ***************************************************************************/
+/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK                     0xfffffffc
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT                    2
+
+/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK            0x00000003
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT           0
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STATUS - Linear Read Status Register
+ ***************************************************************************/
+/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
+#define BCHP_BSPI_RAF_STATUS_reserved0_MASK                        0xfffffff8
+#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT                       3
+
+/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK                        0x00000004
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT                       2
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT                     0x00000000
+
+/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK                       0x00000002
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT                      1
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT                    0x00000001
+
+/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK                     0x00000001
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT                    0
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *READ_DATA - Read data from Raf-buffer
+ ***************************************************************************/
+/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
+#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK                          0xffffffff
+#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT                         0
+#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *WORD_CNT - Current number of words fetched from Flash
+ ***************************************************************************/
+/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK             0xffffffff
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT            0
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *CURR_ADDR - Current read address for the linear read session
+ ***************************************************************************/
+/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK               0xffffffff
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT              0
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT            0x00000000
+
+#endif /* #ifndef BCHP_BSPI_RAF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7445a0/bchp_clkgen.h b/include/linux/brcmstb/7445a0/bchp_clkgen.h
new file mode 100644
index 0000000..1048101
--- /dev/null
+++ b/include/linux/brcmstb/7445a0/bchp_clkgen.h
@@ -0,0 +1,9457 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Oct 17 03:11:31 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_CLKGEN_H__
+#define BCHP_CLKGEN_H__
+
+/***************************************************************************
+ *CLKGEN - clkgen registers
+ ***************************************************************************/
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_BG_PWRON      0x004e0000 /* Bandgap Power on */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV           0x004e0004 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN          0x004e0008 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_CTRL      0x004e000c /* Ldo voltage control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_PWRON     0x004e0010 /* LDO Power on */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS   0x004e0014 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRON         0x004e001c /* Poweron */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET         0x004e0020 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x004e0024 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x004e0028 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS        0x004e002c /* Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_BG_PWRON      0x004e0030 /* Bandgap Power on */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV           0x004e0034 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN          0x004e0038 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_CTRL      0x004e003c /* Ldo voltage control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_PWRON     0x004e0040 /* LDO Power on */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS   0x004e0044 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRON         0x004e004c /* Poweron */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET         0x004e0050 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x004e0054 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x004e0058 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS        0x004e005c /* Status */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_BG_PWRON      0x004e0060 /* Bandgap Power on */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV           0x004e0064 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN          0x004e0068 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_CTRL      0x004e006c /* Ldo voltage control */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_PWRON     0x004e0070 /* LDO Power on */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS   0x004e0074 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRON         0x004e007c /* Poweron */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET         0x004e0080 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH 0x004e0084 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW 0x004e0088 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS        0x004e008c /* Status */
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0 0x004e0090 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1 0x004e0094 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_CPU_PLL_DIV              0x004e0098 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_CPU_PLL_FRAC             0x004e009c /* Fractional */
+#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN             0x004e00a0 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_CPU_PLL_LDO_PWRON        0x004e00a4 /* LDO Power on */
+#define BCHP_CLKGEN_PLL_CPU_PLL_LOCK_STATUS      0x004e00a8 /* Lock Status */
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC             0x004e00ac /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC2            0x004e00b0 /* Mscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_CPU_PLL_PWRON            0x004e00b4 /* Poweron */
+#define BCHP_CLKGEN_PLL_CPU_PLL_RESET            0x004e00b8 /* Resets */
+#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH 0x004e00bc /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW 0x004e00c0 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_CPU_PLL_STATUS           0x004e00c4 /* Status */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0 0x004e00c8 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1 0x004e00cc /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_2 0x004e00d0 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3 0x004e00d4 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4 0x004e00d8 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_HVD_PLL_DIV              0x004e00dc /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_HVD_PLL_FRAC             0x004e00e0 /* Fractional */
+#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN             0x004e00e4 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_HVD_PLL_LDO_PWRON        0x004e00e8 /* LDO Power on */
+#define BCHP_CLKGEN_PLL_HVD_PLL_LOCK_STATUS      0x004e00ec /* Lock Status */
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC             0x004e00f0 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC2            0x004e00f4 /* Mscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_HVD_PLL_PWRON            0x004e00f8 /* Poweron */
+#define BCHP_CLKGEN_PLL_HVD_PLL_RESET            0x004e00fc /* Resets */
+#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH 0x004e0100 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW 0x004e0104 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_HVD_PLL_STATUS           0x004e0108 /* Status */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0 0x004e010c /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1 0x004e0110 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2 0x004e0114 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4 0x004e0118 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5 0x004e011c /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL           0x004e0120 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_LC_PLL_DIV               0x004e0124 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_LC_PLL_GAIN              0x004e0128 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL       0x004e012c /* Hold PLL all channels */
+#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL          0x004e0130 /* Ldo voltage control */
+#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON         0x004e0134 /* LDO Power on */
+#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS       0x004e0138 /* Lock Status */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC              0x004e013c /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2             0x004e0140 /* Mscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL        0x004e0144 /* selection of the output clock from the PLL core */
+#define BCHP_CLKGEN_PLL_LC_PLL_PWRON             0x004e0148 /* Poweron */
+#define BCHP_CLKGEN_PLL_LC_PLL_RESET             0x004e014c /* Resets */
+#define BCHP_CLKGEN_PLL_LC_PLL_STATUS            0x004e0150 /* Status */
+#define BCHP_CLKGEN_PLL_LC_PLL_TEST              0x004e0154 /* enable and selection pf PLL test */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 0x004e0158 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 0x004e015c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 0x004e0160 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 0x004e0164 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 0x004e0168 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 0x004e016c /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV             0x004e0170 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN            0x004e0174 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON       0x004e0178 /* LDO Power on */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS     0x004e017c /* Lock Status */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC            0x004e0180 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2           0x004e0184 /* Mscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON           0x004e0188 /* Poweron */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET           0x004e018c /* Resets */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH 0x004e0190 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW 0x004e0194 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS          0x004e0198 /* Status */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 0x004e019c /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 0x004e01a0 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 0x004e01a4 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV          0x004e01a8 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN         0x004e01ac /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRON    0x004e01b0 /* LDO Power on */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS  0x004e01b4 /* Lock Status */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC         0x004e01b8 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2        0x004e01bc /* Mscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRON        0x004e01c0 /* Poweron */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET        0x004e01c4 /* Resets */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH 0x004e01c8 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW 0x004e01cc /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS       0x004e01d0 /* Status */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 0x004e01d4 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 0x004e01d8 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 0x004e01dc /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 0x004e01e0 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 0x004e01e4 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV            0x004e01e8 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN           0x004e01ec /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON      0x004e01f0 /* LDO Power on */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS    0x004e01f4 /* Lock Status */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC           0x004e01f8 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2          0x004e01fc /* Mscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON          0x004e0200 /* Poweron */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET          0x004e0204 /* Resets */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH 0x004e0208 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW 0x004e020c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS         0x004e0210 /* Status */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0 0x004e0214 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV              0x004e0218 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC             0x004e021c /* Fractional */
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN             0x004e0220 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON        0x004e0224 /* LDO Power on */
+#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS      0x004e0228 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC             0x004e022c /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2            0x004e0230 /* Mscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON            0x004e0234 /* Poweron */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET            0x004e0238 /* Resets */
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH 0x004e023c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW 0x004e0240 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS           0x004e0244 /* Status */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0 0x004e0248 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV              0x004e024c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC             0x004e0250 /* Fractional */
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN             0x004e0254 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON        0x004e0258 /* LDO Power on */
+#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS      0x004e025c /* Lock Status */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC             0x004e0260 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2            0x004e0264 /* Mscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON            0x004e0268 /* Poweron */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET            0x004e026c /* Resets */
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH 0x004e0270 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW 0x004e0274 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS           0x004e0278 /* Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON        0x004e027c /* Bandgap Power on */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x004e0280 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x004e0284 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x004e0288 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x004e028c /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV             0x004e0290 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN            0x004e0294 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL     0x004e0298 /* Hold PLL all channels */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL        0x004e029c /* Ldo voltage control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON       0x004e02a0 /* LDO Power on */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS     0x004e02a4 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC            0x004e02a8 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2           0x004e02ac /* Mscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON           0x004e02b0 /* Poweron */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET           0x004e02b4 /* Resets */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x004e02b8 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x004e02bc /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS          0x004e02c0 /* Status */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON       0x004e02c4 /* Bandgap Power on */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 0x004e02c8 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 0x004e02cc /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 0x004e02d0 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV            0x004e02d4 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC           0x004e02d8 /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN           0x004e02dc /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL    0x004e02e0 /* Hold PLL all channels */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL       0x004e02e4 /* Ldo voltage control */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON      0x004e02e8 /* LDO Power on */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS    0x004e02ec /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC           0x004e02f0 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2          0x004e02f4 /* Mscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON          0x004e02f8 /* Poweron */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET          0x004e02fc /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH 0x004e0300 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW 0x004e0304 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS         0x004e0308 /* Status */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON       0x004e030c /* Bandgap Power on */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 0x004e0310 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 0x004e0314 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 0x004e0318 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV            0x004e031c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC           0x004e0320 /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN           0x004e0324 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL    0x004e0328 /* Hold PLL all channels */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL       0x004e032c /* Ldo voltage control */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON      0x004e0330 /* LDO Power on */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS    0x004e0334 /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC           0x004e0338 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2          0x004e033c /* Mscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON          0x004e0340 /* Poweron */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET          0x004e0344 /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH 0x004e0348 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW 0x004e034c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS         0x004e0350 /* Status */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON       0x004e0354 /* Bandgap Power on */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 0x004e0358 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 0x004e035c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 0x004e0360 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV            0x004e0364 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC           0x004e0368 /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN           0x004e036c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL    0x004e0370 /* Hold PLL all channels */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL       0x004e0374 /* Ldo voltage control */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON      0x004e0378 /* LDO Power on */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS    0x004e037c /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC           0x004e0380 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2          0x004e0384 /* Mscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON          0x004e0388 /* Poweron */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET          0x004e038c /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH 0x004e0390 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW 0x004e0394 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS         0x004e0398 /* Status */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0 0x004e039c /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1 0x004e03a0 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2 0x004e03a4 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3 0x004e03a8 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4 0x004e03ac /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_XPT_PLL_DIV              0x004e03b0 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN             0x004e03b4 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON        0x004e03b8 /* LDO Power on */
+#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS      0x004e03bc /* Lock Status */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC             0x004e03c0 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2            0x004e03c4 /* Mscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON            0x004e03c8 /* Poweron */
+#define BCHP_CLKGEN_PLL_XPT_PLL_RESET            0x004e03cc /* Resets */
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH 0x004e03d0 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW 0x004e03d4 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS           0x004e03d8 /* Status */
+#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE 0x004e03dc /* Disable ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST's clocks */
+#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS 0x004e03e0 /* Clock Disable Status */
+#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE 0x004e03e4 /* Disable ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST's clocks */
+#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS 0x004e03e8 /* Clock Disable Status */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE 0x004e03ec /* Bvn mvp top inst clock enable */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS 0x004e03f0 /* Clock Enable Status */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE    0x004e03f4 /* Bvn top inst clock enable */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS 0x004e03f8 /* Clock Enable Status */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE         0x004e03fc /* Disable CLKGEN's clocks */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS  0x004e0400 /* Clock Disable Status */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL        0x004e0404 /* Clock Monitor Control */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT      0x004e0408 /* Clock Monitor Max Reference Count */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER    0x004e040c /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE       0x004e0410 /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER   0x004e0414 /* Clock Monitor View Counter */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE  0x004e0418 /* Disable CORE_XPT_INST's clocks */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS 0x004e041c /* Clock Disable Status */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE   0x004e0420 /* Core xpt inst clock enable */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS 0x004e0424 /* Clock Enable Status */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK  0x004e0428 /* Core xpt inst observe clock */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE    0x004e042c /* Disable DVP_HR_INST's clocks */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS 0x004e0430 /* Clock Disable Status */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE     0x004e0434 /* Dvp hr inst clock enable */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0    0x004e0438 /* Dvp hr inst clock enable0 */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_STATUS 0x004e043c /* Clock Enable Status */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE2    0x004e0440 /* Dvp hr inst clock enable2 */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE2_STATUS 0x004e0444 /* Clock Enable Status */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS 0x004e0448 /* Clock Enable Status */
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK    0x004e044c /* Dvp hr inst observe clock */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE    0x004e0450 /* Disable DVP_HT_INST's clocks */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS 0x004e0454 /* Clock Disable Status */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE     0x004e0458 /* Dvp ht inst clock enable */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS 0x004e045c /* Clock Enable Status */
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE           0x004e0460 /* Dvp ht inst enable */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK    0x004e0464 /* Dvp ht inst observe clock */
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE 0x004e0468 /* Disable EAGLET_TOP_INST's clocks */
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS 0x004e046c /* Clock Disable Status */
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE 0x004e0470 /* Eaglet top inst clock enable */
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS 0x004e0474 /* Clock Enable Status */
+#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_DIV5 0x004e0478 /* Egphy28 1port 33v 90o fc inst div5 */
+#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_SEL 0x004e047c /* Egphy28 1port 33v 90o fc inst sel */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE   0x004e0480 /* Graphics inst clock enable */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0  0x004e0484 /* Graphics inst clock enable0 */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_STATUS 0x004e0488 /* Clock Enable Status */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1  0x004e048c /* Graphics inst clock enable1 */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_STATUS 0x004e0490 /* Clock Enable Status */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0 0x004e0494 /* Graphics inst clock enable m2mc0 */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS 0x004e0498 /* Clock Enable Status */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1 0x004e049c /* Graphics inst clock enable m2mc1 */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS 0x004e04a0 /* Clock Enable Status */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS 0x004e04a4 /* Clock Enable Status */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK  0x004e04a8 /* Graphics inst observe clock */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE       0x004e04ac /* Disable HIF_INST's clocks */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS 0x004e04b0 /* Clock Disable Status */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE        0x004e04b4 /* Hif inst clock enable */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS 0x004e04b8 /* Clock Enable Status */
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK       0x004e04bc /* Hif inst observe clock */
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE   0x004e04c0 /* Hvd2 top inst clock enable */
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_STATUS 0x004e04c4 /* Clock Enable Status */
+#define BCHP_CLKGEN_HVD2_TOP_INST_OBSERVE_CLOCK  0x004e04c8 /* Hvd2 top inst observe clock */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE 0x004e04cc /* Hvd sid1 top inst clock enable */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_SID 0x004e04d0 /* Hvd sid1 top inst clock enable sid */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS 0x004e04d4 /* Clock Enable Status */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS 0x004e04d8 /* Clock Enable Status */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK 0x004e04dc /* Hvd sid1 top inst observe clock */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT          0x004e04e0 /* Mux selects for Internal clocks */
+#define BCHP_CLKGEN_ITU656_0_MUX_SELECT          0x004e04e4 /* Mux selects for itu656_0 clocks */
+#define BCHP_CLKGEN_ITU656_1_MUX_SELECT          0x004e04e8 /* Mux selects for itu656_1 clocks */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE 0x004e04ec /* Memsys 32 0 inst clock enable */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS 0x004e04f0 /* Clock Enable Status */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK 0x004e04f4 /* Memsys 32 0 inst observe clock */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS      0x004e04f8 /* Memsys 32 0 inst status */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE 0x004e04fc /* Memsys 32 1 inst clock enable */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS 0x004e0500 /* Clock Enable Status */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK 0x004e0504 /* Memsys 32 1 inst observe clock */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_STATUS      0x004e0508 /* Memsys 32 1 inst status */
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_CLOCK_ENABLE 0x004e050c /* Memsys 32 2 inst clock enable */
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_CLOCK_ENABLE_STATUS 0x004e0510 /* Clock Enable Status */
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_OBSERVE_CLOCK 0x004e0514 /* Memsys 32 2 inst observe clock */
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_STATUS      0x004e0518 /* Memsys 32 2 inst status */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE 0x004e051c /* Mocamac top inst clock enable */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS 0x004e0520 /* Clock Enable Status */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK 0x004e0524 /* Mocamac top inst observe clock */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE 0x004e0528 /* Mocaphy top inst clock enable */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS 0x004e052c /* Clock Enable Status */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK 0x004e0530 /* Mocaphy top inst observe clock */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION        0x004e0534 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE            0x004e0538 /* Disable PAD's clocks */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS     0x004e053c /* Clock Disable Status */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION   0x004e0540 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_MUX_SELECT               0x004e0544 /* Mux selects for Pad clocks */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION       0x004e0548 /* Select observation clk */
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE 0x004e054c /* Disable PCIE_X1_TOP_INST's clocks */
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS 0x004e0550 /* Clock Disable Status */
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE 0x004e0554 /* Pcie x1 top inst clock enable */
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS 0x004e0558 /* Clock Enable Status */
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK 0x004e055c /* Pcie x1 top inst observe clock */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS  0x004e0560 /* PLL_AUDIO0 Reset Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS  0x004e0564 /* PLL_AUDIO1 Reset Status */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS  0x004e0568 /* PLL_AUDIO2 Reset Status */
+#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST 0x004e056c /* PLL_CPU Glitchless Clock Switching */
+#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_STATUS 0x004e0570 /* PLL_CPU Glitchless Switching */
+#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_STATUS     0x004e0574 /* PLL_CPU Reset Status */
+#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL       0x004e0578 /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_STATUS     0x004e057c /* PLL_HVD Reset Status */
+#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL       0x004e0580 /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS      0x004e0584 /* PLL_LC Reset Status */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS    0x004e0588 /* PLL_MOCA Reset Status */
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL      0x004e058c /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS 0x004e0590 /* PLL_NETWORK Reset Status */
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT            0x004e0594 /* spi clock control */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS   0x004e0598 /* PLL_RAAGA Reset Status */
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL     0x004e059c /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS     0x004e05a0 /* PLL_SC0 Reset Status */
+#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL       0x004e05a4 /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS     0x004e05a8 /* PLL_SC1 Reset Status */
+#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL       0x004e05ac /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS   0x004e05b4 /* PLL_VCXO0 Reset Status */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS   0x004e05b8 /* PLL_VCXO1 Reset Status */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS   0x004e05bc /* PLL_VCXO2 Reset Status */
+#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL     0x004e05c0 /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x004e05c4 /* PLL Alive in Standby Mode */
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE  0x004e05c8 /* Disable PROD_OTP_INST's clocks */
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS 0x004e05cc /* Clock Disable Status */
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE   0x004e05d0 /* Prod otp inst clock enable */
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS 0x004e05d4 /* Clock Enable Status */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE 0x004e05d8 /* Raaga dsp top 0 inst clock enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS 0x004e05dc /* Clock Enable Status */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK 0x004e05e0 /* Raaga dsp top 0 inst observe clock */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE 0x004e05e4 /* Raaga dsp top 1 inst clock enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS 0x004e05e8 /* Clock Enable Status */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK 0x004e05ec /* Raaga dsp top 1 inst observe clock */
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE    0x004e05f0 /* Rfm top inst clock enable */
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS 0x004e05f4 /* Clock Enable Status */
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK   0x004e05f8 /* Rfm top inst observe clock */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE 0x004e05fc /* Disable SATA3_TOP_INST's clocks */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS 0x004e0600 /* Clock Disable Status */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE  0x004e0604 /* Sata3 top inst clock enable */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS 0x004e0608 /* Clock Enable Status */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT  0x004e060c /* Sata3 top inst clock select */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK 0x004e0610 /* Sata3 top inst observe clock */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK    0x004e0614 /* Sectop inst observe clock */
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE  0x004e0618 /* Shvd0 top inst clock enable */
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_STATUS 0x004e061c /* Clock Enable Status */
+#define BCHP_CLKGEN_SHVD0_TOP_INST_OBSERVE_CLOCK 0x004e0620 /* Shvd0 top inst observe clock */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT         0x004e0624 /* Mux selects for Smartcard clocks */
+#define BCHP_CLKGEN_SPARE                        0x004e0628 /* Spares */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK   0x004e062c /* Sys aon inst observe clock */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE  0x004e0630 /* Disable SYS_CTRL_INST's clocks */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS 0x004e0634 /* Clock Disable Status */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK  0x004e0638 /* Sys ctrl inst observe clock */
+#define BCHP_CLKGEN_TESTPORT                     0x004e063c /* Special Testport Controls */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE 0x004e0640 /* Disable TRIPLE_GENET_TOP_RGMII_INST's clocks */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS 0x004e0644 /* Clock Disable Status */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE 0x004e0648 /* Triple genet top rgmii inst clock enable */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 0x004e064c /* Triple genet top rgmii inst clock enable genet0 */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS 0x004e0650 /* Clock Enable Status */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 0x004e0654 /* Triple genet top rgmii inst clock enable genet1 */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS 0x004e0658 /* Clock Enable Status */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 0x004e065c /* Triple genet top rgmii inst clock enable genet2 */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS 0x004e0660 /* Clock Enable Status */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS 0x004e0664 /* Clock Enable Status */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0 0x004e0668 /* Triple genet top rgmii inst clock select genet0 */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1 0x004e066c /* Triple genet top rgmii inst clock select genet1 */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2 0x004e0670 /* Triple genet top rgmii inst clock select genet2 */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK 0x004e0674 /* Triple genet top rgmii inst observe clock */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE  0x004e0678 /* Disable USB0_TOP_INST's clocks */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS 0x004e067c /* Clock Disable Status */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE   0x004e0680 /* Usb0 top inst clock enable */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB 0x004e0684 /* Usb0 top inst clock enable ahb */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS 0x004e0688 /* Clock Enable Status */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI 0x004e068c /* Usb0 top inst clock enable axi */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS 0x004e0690 /* Clock Enable Status */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS 0x004e0694 /* Clock Enable Status */
+#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK  0x004e0698 /* Usb0 top inst observe clock */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE  0x004e069c /* Disable USB1_TOP_INST's clocks */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_STATUS 0x004e06a0 /* Clock Disable Status */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE   0x004e06a4 /* Usb1 top inst clock enable */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB 0x004e06a8 /* Usb1 top inst clock enable ahb */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS 0x004e06ac /* Clock Enable Status */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI 0x004e06b0 /* Usb1 top inst clock enable axi */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS 0x004e06b4 /* Clock Enable Status */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS 0x004e06b8 /* Clock Enable Status */
+#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK  0x004e06bc /* Usb1 top inst observe clock */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE    0x004e06c0 /* V3d top inst clock enable */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS 0x004e06c4 /* Clock Enable Status */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE 0x004e06c8 /* Disable VEC_AIO_TOP_INST's clocks */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS 0x004e06cc /* Clock Disable Status */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE 0x004e06d0 /* Vec aio top inst clock enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO 0x004e06d4 /* Vec aio top inst clock enable aio */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS 0x004e06d8 /* Clock Enable Status */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS 0x004e06dc /* Clock Enable Status */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC 0x004e06e0 /* Vec aio top inst clock enable vec */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF 0x004e06e4 /* Vec aio top inst clock enable vec qdac intf */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS 0x004e06e8 /* Clock Enable Status */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS 0x004e06ec /* Clock Enable Status */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK 0x004e06f0 /* Vec aio top inst observe clock */
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE    0x004e06f4 /* Vice2 0 inst clock enable */
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS 0x004e06f8 /* Clock Enable Status */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE    0x004e06fc /* Vice2 1 inst clock enable */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS 0x004e0700 /* Clock Enable Status */
+#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE 0x004e0704 /* Could be set at start up to guarantee that AVS_TOP is clock gated in S2 */
+#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2    0x004e0708 /* disable AVS_TOP 54MHz clocks during S2 */
+#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS      0x004e070c /* bypass USBPHY reference clocks */
+#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS        0x004e0710 /* bypass EPHY reference clocks */
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_BG_PWRON - Bandgap Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_BG_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_BG_PWRON_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_BG_PWRON_reserved0_SHIFT        1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_BG_PWRON_BG_PWRON_PLL_MASK      0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT     0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT   0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK              0xfffffff0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT             4
+
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [03:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK                   0x0000000f
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT                0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:10] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK             0xfffffc00
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT            10
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x00000038
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    3
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_LDO_CTRL - Ldo voltage control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_LDO_CTRL :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_CTRL_reserved0_MASK         0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_CTRL_reserved0_SHIFT        16
+
+/* CLKGEN :: PLL_AUDIO0_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_CTRL_LDO_CTRL_MASK          0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_CTRL_LDO_CTRL_SHIFT         0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_CTRL_LDO_CTRL_DEFAULT       0x00000005
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_LDO_PWRON - LDO Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_LDO_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_PWRON_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_PWRON_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK    0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT   0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT     2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_LOST_MASK      0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_PWRON - Poweron
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRON_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRON_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRON :: PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRON_PWRON_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRON_PWRON_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRON_PWRON_PLL_DEFAULT         0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_BG_PWRON - Bandgap Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_BG_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_BG_PWRON_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_BG_PWRON_reserved0_SHIFT        1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_BG_PWRON_BG_PWRON_PLL_MASK      0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT     0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT   0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK              0xfffffff0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT             4
+
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [03:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK                   0x0000000f
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT                0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:10] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK             0xfffffc00
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT            10
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x00000038
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    3
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_LDO_CTRL - Ldo voltage control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_LDO_CTRL :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_CTRL_reserved0_MASK         0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_CTRL_reserved0_SHIFT        16
+
+/* CLKGEN :: PLL_AUDIO1_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_CTRL_LDO_CTRL_MASK          0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_CTRL_LDO_CTRL_SHIFT         0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_CTRL_LDO_CTRL_DEFAULT       0x00000005
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_LDO_PWRON - LDO Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_LDO_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_PWRON_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_PWRON_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK    0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT   0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT     2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_LOST_MASK      0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_PWRON - Poweron
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRON_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRON_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRON :: PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRON_PWRON_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRON_PWRON_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRON_PWRON_PLL_DEFAULT         0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_BG_PWRON - Bandgap Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_BG_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_BG_PWRON_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_BG_PWRON_reserved0_SHIFT        1
+
+/* CLKGEN :: PLL_AUDIO2_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_BG_PWRON_BG_PWRON_PLL_MASK      0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT     0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT   0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_DIV :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_reserved0_MASK              0xfffffff0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_reserved0_SHIFT             4
+
+/* CLKGEN :: PLL_AUDIO2_PLL_DIV :: PDIV [03:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_PDIV_MASK                   0x0000000f
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_PDIV_DEFAULT                0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: reserved0 [31:10] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_reserved0_MASK             0xfffffc00
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_reserved0_SHIFT            10
+
+/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x00000038
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    3
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000000
+
+/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_LDO_CTRL - Ldo voltage control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_LDO_CTRL :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_CTRL_reserved0_MASK         0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_CTRL_reserved0_SHIFT        16
+
+/* CLKGEN :: PLL_AUDIO2_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_CTRL_LDO_CTRL_MASK          0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_CTRL_LDO_CTRL_SHIFT         0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_CTRL_LDO_CTRL_DEFAULT       0x00000005
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_LDO_PWRON - LDO Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_LDO_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_PWRON_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_PWRON_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_AUDIO2_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK    0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT   0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_reserved0_SHIFT     2
+
+/* CLKGEN :: PLL_AUDIO2_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_LOCK_LOST_MASK      0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_LOCK_LOST_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO2_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_PWRON - Poweron
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRON_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRON_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO2_PLL_PWRON :: PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRON_PWRON_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRON_PWRON_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRON_PWRON_PLL_DEFAULT         0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO2_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETD_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AUDIO2_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO2_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_CPU_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xfffff800
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  11
+
+/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_CPU_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK   0xfffff800
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT  11
+
+/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT   1
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000064
+
+/* CLKGEN :: PLL_CPU_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_CPU_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PLL_CPU_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_CPU_PLL_DIV :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_reserved0_MASK                 0xffffc000
+#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_reserved0_SHIFT                14
+
+/* CLKGEN :: PLL_CPU_PLL_DIV :: PDIV [13:10] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_PDIV_MASK                      0x00003c00
+#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_PDIV_SHIFT                     10
+#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_PDIV_DEFAULT                   0x00000003
+
+/* CLKGEN :: PLL_CPU_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_NDIV_INT_MASK                  0x000003ff
+#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_NDIV_INT_SHIFT                 0
+#define BCHP_CLKGEN_PLL_CPU_PLL_DIV_NDIV_INT_DEFAULT               0x000000a7
+
+/***************************************************************************
+ *PLL_CPU_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_CPU_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_FRAC_reserved0_MASK                0xfff00000
+#define BCHP_CLKGEN_PLL_CPU_PLL_FRAC_reserved0_SHIFT               20
+
+/* CLKGEN :: PLL_CPU_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_FRAC_FRAC_CONTROL_MASK             0x000fffff
+#define BCHP_CLKGEN_PLL_CPU_PLL_FRAC_FRAC_CONTROL_SHIFT            0
+#define BCHP_CLKGEN_PLL_CPU_PLL_FRAC_FRAC_CONTROL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_CPU_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_CPU_PLL_GAIN :: reserved0 [31:10] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_reserved0_MASK                0xfffffc00
+#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_reserved0_SHIFT               10
+
+/* CLKGEN :: PLL_CPU_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
+
+/* CLKGEN :: PLL_CPU_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x00000038
+#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       3
+#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     0x00000000
+
+/* CLKGEN :: PLL_CPU_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
+#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
+#define BCHP_CLKGEN_PLL_CPU_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/***************************************************************************
+ *PLL_CPU_PLL_LDO_PWRON - LDO Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_CPU_PLL_LDO_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_LDO_PWRON_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_CPU_PLL_LDO_PWRON_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_CPU_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK       0x00000001
+#define BCHP_CLKGEN_PLL_CPU_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT      0
+#define BCHP_CLKGEN_PLL_CPU_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT    0x00000001
+
+/***************************************************************************
+ *PLL_CPU_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_CPU_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_CPU_PLL_LOCK_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_CPU_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_LOCK_STATUS_LOCK_LOST_MASK         0x00000002
+#define BCHP_CLKGEN_PLL_CPU_PLL_LOCK_STATUS_LOCK_LOST_SHIFT        1
+
+/* CLKGEN :: PLL_CPU_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_CPU_PLL_LOCK_STATUS_LOCK_SHIFT             0
+
+/***************************************************************************
+ *PLL_CPU_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_CPU_PLL_MISC :: VCO_RANGE [31:30] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_VCO_RANGE_MASK                0xc0000000
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_VCO_RANGE_SHIFT               30
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_VCO_RANGE_DEFAULT             0x00000002
+
+/* CLKGEN :: PLL_CPU_PLL_MISC :: VCO_FB_DIV2 [29:29] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_VCO_FB_DIV2_MASK              0x20000000
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_VCO_FB_DIV2_SHIFT             29
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_VCO_FB_DIV2_DEFAULT           0x00000001
+
+/* CLKGEN :: PLL_CPU_PLL_MISC :: STAT_UPDATE [28:28] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_UPDATE_MASK              0x10000000
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_UPDATE_SHIFT             28
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_UPDATE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_CPU_PLL_MISC :: STAT_SELECT [27:25] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_SELECT_MASK              0x0e000000
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_SELECT_SHIFT             25
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_SELECT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_CPU_PLL_MISC :: STAT_RESET [24:24] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_RESET_MASK               0x01000000
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_RESET_SHIFT              24
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_RESET_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_CPU_PLL_MISC :: STAT_MODE [23:22] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_MODE_MASK                0x00c00000
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_MODE_SHIFT               22
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_STAT_MODE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_CPU_PLL_MISC :: PWM_RATE [21:20] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PWM_RATE_MASK                 0x00300000
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PWM_RATE_SHIFT                20
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PWM_RATE_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_CPU_PLL_MISC :: POST_CTRL_RESETB [19:18] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_POST_CTRL_RESETB_MASK         0x000c0000
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_POST_CTRL_RESETB_SHIFT        18
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_POST_CTRL_RESETB_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_CPU_PLL_MISC :: PLLRESERVED2 [17:16] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PLLRESERVED2_MASK             0x00030000
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PLLRESERVED2_SHIFT            16
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PLLRESERVED2_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_CPU_PLL_MISC :: PLLRESERVED1 [15:15] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PLLRESERVED1_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PLLRESERVED1_SHIFT            15
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_PLLRESERVED1_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_CPU_PLL_MISC :: NDIV_RELOCK [14:14] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_NDIV_RELOCK_MASK              0x00004000
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_NDIV_RELOCK_SHIFT             14
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_NDIV_RELOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_CPU_PLL_MISC :: FAST_LOCK [13:13] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_FAST_LOCK_MASK                0x00002000
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_FAST_LOCK_SHIFT               13
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_FAST_LOCK_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_CPU_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00001000
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  12
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_CPU_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         0
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_CPU_PLL_MISC2 - Mscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_CPU_PLL_MISC2 :: PLLRESERVED0 [31:02] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC2_PLLRESERVED0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC2_PLLRESERVED0_SHIFT           2
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC2_PLLRESERVED0_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_CPU_PLL_MISC2 :: LDO [01:00] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC2_LDO_MASK                     0x00000003
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC2_LDO_SHIFT                    0
+#define BCHP_CLKGEN_PLL_CPU_PLL_MISC2_LDO_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PLL_CPU_PLL_PWRON - Poweron
+ ***************************************************************************/
+/* CLKGEN :: PLL_CPU_PLL_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_PWRON_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_CPU_PLL_PWRON_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_CPU_PLL_PWRON :: PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_PWRON_PWRON_PLL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_CPU_PLL_PWRON_PWRON_PLL_SHIFT              0
+#define BCHP_CLKGEN_PLL_CPU_PLL_PWRON_PWRON_PLL_DEFAULT            0x00000001
+
+/***************************************************************************
+ *PLL_CPU_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_CPU_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_reserved0_MASK               0xfffffffc
+#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_reserved0_SHIFT              2
+
+/* CLKGEN :: PLL_CPU_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_RESETD_MASK                  0x00000002
+#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_RESETD_SHIFT                 1
+#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_RESETD_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_CPU_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_RESETA_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_RESETA_SHIFT                 0
+#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_RESETA_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_CPU_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_CPU_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_CPU_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_CPU_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_CPU_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_CPU_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_CPU_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_STATUS_reserved0_MASK              0xfffff000
+#define BCHP_CLKGEN_PLL_CPU_PLL_STATUS_reserved0_SHIFT             12
+
+/* CLKGEN :: PLL_CPU_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
+#define BCHP_CLKGEN_PLL_CPU_PLL_STATUS_TEST_STATUS_SHIFT           0
+
+/***************************************************************************
+ *PLL_HVD_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xfffff800
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  11
+
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_HVD_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK   0xfffff800
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT  11
+
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT   1
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_HVD_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK   0xfffff800
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT  11
+
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT   1
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_HVD_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK   0xfffff800
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT  11
+
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT   1
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_HVD_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK   0xfffff800
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT  11
+
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT   1
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000064
+
+/* CLKGEN :: PLL_HVD_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_HVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_HVD_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_HVD_PLL_DIV :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_reserved0_MASK                 0xffffc000
+#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_reserved0_SHIFT                14
+
+/* CLKGEN :: PLL_HVD_PLL_DIV :: PDIV [13:10] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_PDIV_MASK                      0x00003c00
+#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_PDIV_SHIFT                     10
+#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_PDIV_DEFAULT                   0x00000003
+
+/* CLKGEN :: PLL_HVD_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_NDIV_INT_MASK                  0x000003ff
+#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_NDIV_INT_SHIFT                 0
+#define BCHP_CLKGEN_PLL_HVD_PLL_DIV_NDIV_INT_DEFAULT               0x00000094
+
+/***************************************************************************
+ *PLL_HVD_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_HVD_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_FRAC_reserved0_MASK                0xfff00000
+#define BCHP_CLKGEN_PLL_HVD_PLL_FRAC_reserved0_SHIFT               20
+
+/* CLKGEN :: PLL_HVD_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_FRAC_FRAC_CONTROL_MASK             0x000fffff
+#define BCHP_CLKGEN_PLL_HVD_PLL_FRAC_FRAC_CONTROL_SHIFT            0
+#define BCHP_CLKGEN_PLL_HVD_PLL_FRAC_FRAC_CONTROL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_HVD_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_HVD_PLL_GAIN :: reserved0 [31:10] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_reserved0_MASK                0xfffffc00
+#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_reserved0_SHIFT               10
+
+/* CLKGEN :: PLL_HVD_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
+
+/* CLKGEN :: PLL_HVD_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x00000038
+#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       3
+#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
+#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
+#define BCHP_CLKGEN_PLL_HVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/***************************************************************************
+ *PLL_HVD_PLL_LDO_PWRON - LDO Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_HVD_PLL_LDO_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_LDO_PWRON_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_HVD_PLL_LDO_PWRON_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_HVD_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK       0x00000001
+#define BCHP_CLKGEN_PLL_HVD_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT      0
+#define BCHP_CLKGEN_PLL_HVD_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT    0x00000001
+
+/***************************************************************************
+ *PLL_HVD_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_HVD_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_HVD_PLL_LOCK_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_HVD_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_LOCK_STATUS_LOCK_LOST_MASK         0x00000002
+#define BCHP_CLKGEN_PLL_HVD_PLL_LOCK_STATUS_LOCK_LOST_SHIFT        1
+
+/* CLKGEN :: PLL_HVD_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_HVD_PLL_LOCK_STATUS_LOCK_SHIFT             0
+
+/***************************************************************************
+ *PLL_HVD_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_HVD_PLL_MISC :: VCO_RANGE [31:30] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_VCO_RANGE_MASK                0xc0000000
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_VCO_RANGE_SHIFT               30
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_VCO_RANGE_DEFAULT             0x00000002
+
+/* CLKGEN :: PLL_HVD_PLL_MISC :: VCO_FB_DIV2 [29:29] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_VCO_FB_DIV2_MASK              0x20000000
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_VCO_FB_DIV2_SHIFT             29
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_VCO_FB_DIV2_DEFAULT           0x00000001
+
+/* CLKGEN :: PLL_HVD_PLL_MISC :: STAT_UPDATE [28:28] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_UPDATE_MASK              0x10000000
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_UPDATE_SHIFT             28
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_UPDATE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_MISC :: STAT_SELECT [27:25] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_SELECT_MASK              0x0e000000
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_SELECT_SHIFT             25
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_SELECT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_MISC :: STAT_RESET [24:24] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_RESET_MASK               0x01000000
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_RESET_SHIFT              24
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_RESET_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_MISC :: STAT_MODE [23:22] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_MODE_MASK                0x00c00000
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_MODE_SHIFT               22
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_STAT_MODE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_MISC :: PWM_RATE [21:20] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PWM_RATE_MASK                 0x00300000
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PWM_RATE_SHIFT                20
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PWM_RATE_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_MISC :: POST_CTRL_RESETB [19:18] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_POST_CTRL_RESETB_MASK         0x000c0000
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_POST_CTRL_RESETB_SHIFT        18
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_POST_CTRL_RESETB_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_MISC :: PLLRESERVED2 [17:16] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PLLRESERVED2_MASK             0x00030000
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PLLRESERVED2_SHIFT            16
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PLLRESERVED2_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_MISC :: PLLRESERVED1 [15:15] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PLLRESERVED1_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PLLRESERVED1_SHIFT            15
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_PLLRESERVED1_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_MISC :: NDIV_RELOCK [14:14] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_NDIV_RELOCK_MASK              0x00004000
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_NDIV_RELOCK_SHIFT             14
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_NDIV_RELOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_MISC :: FAST_LOCK [13:13] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_FAST_LOCK_MASK                0x00002000
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_FAST_LOCK_SHIFT               13
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_FAST_LOCK_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00001000
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  12
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         0
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_HVD_PLL_MISC2 - Mscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_HVD_PLL_MISC2 :: PLLRESERVED0 [31:02] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC2_PLLRESERVED0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC2_PLLRESERVED0_SHIFT           2
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC2_PLLRESERVED0_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_MISC2 :: LDO [01:00] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC2_LDO_MASK                     0x00000003
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC2_LDO_SHIFT                    0
+#define BCHP_CLKGEN_PLL_HVD_PLL_MISC2_LDO_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PLL_HVD_PLL_PWRON - Poweron
+ ***************************************************************************/
+/* CLKGEN :: PLL_HVD_PLL_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_PWRON_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_HVD_PLL_PWRON_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_HVD_PLL_PWRON :: PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_PWRON_PWRON_PLL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_HVD_PLL_PWRON_PWRON_PLL_SHIFT              0
+#define BCHP_CLKGEN_PLL_HVD_PLL_PWRON_PWRON_PLL_DEFAULT            0x00000001
+
+/***************************************************************************
+ *PLL_HVD_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_HVD_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_reserved0_MASK               0xfffffffc
+#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_reserved0_SHIFT              2
+
+/* CLKGEN :: PLL_HVD_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_RESETD_MASK                  0x00000002
+#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_RESETD_SHIFT                 1
+#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_RESETD_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_RESETA_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_RESETA_SHIFT                 0
+#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_RESETA_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_HVD_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_HVD_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_HVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_HVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_HVD_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_HVD_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_STATUS_reserved0_MASK              0xfffff000
+#define BCHP_CLKGEN_PLL_HVD_PLL_STATUS_reserved0_SHIFT             12
+
+/* CLKGEN :: PLL_HVD_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
+#define BCHP_CLKGEN_PLL_HVD_PLL_STATUS_TEST_STATUS_SHIFT           0
+
+/***************************************************************************
+ *PLL_LC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK    0xfffff800
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT   11
+
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT    1
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT  0x0000006c
+
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_LC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK    0xfffff800
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT   11
+
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT    1
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT  0x0000002d
+
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_LC_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK    0xfffff800
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT   11
+
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT    1
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT  0x0000002d
+
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_LC_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK    0xfffff800
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT   11
+
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT    1
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT  0x00000036
+
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_LC_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK    0xfffff800
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT   11
+
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT    1
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT  0x00000036
+
+/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PLL_LC_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_LC_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_LC_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_REF_SEL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_REF_SEL_SHIFT               0
+#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_REF_SEL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_LC_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_LC_PLL_DIV :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_LC_PLL_DIV_reserved0_MASK                  0xffffc000
+#define BCHP_CLKGEN_PLL_LC_PLL_DIV_reserved0_SHIFT                 14
+
+/* CLKGEN :: PLL_LC_PLL_DIV :: PDIV [13:10] */
+#define BCHP_CLKGEN_PLL_LC_PLL_DIV_PDIV_MASK                       0x00003c00
+#define BCHP_CLKGEN_PLL_LC_PLL_DIV_PDIV_SHIFT                      10
+#define BCHP_CLKGEN_PLL_LC_PLL_DIV_PDIV_DEFAULT                    0x00000002
+
+/* CLKGEN :: PLL_LC_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_LC_PLL_DIV_NDIV_INT_MASK                   0x000003ff
+#define BCHP_CLKGEN_PLL_LC_PLL_DIV_NDIV_INT_SHIFT                  0
+#define BCHP_CLKGEN_PLL_LC_PLL_DIV_NDIV_INT_DEFAULT                0x00000064
+
+/***************************************************************************
+ *PLL_LC_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_LC_PLL_GAIN :: reserved0 [31:07] */
+#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_reserved0_MASK                 0xffffff80
+#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_reserved0_SHIFT                7
+
+/* CLKGEN :: PLL_LC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [06:03] */
+#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000078
+#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_LC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
+#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
+#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
+#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/***************************************************************************
+ *PLL_LC_PLL_HOLD_CH_ALL - Hold PLL all channels
+ ***************************************************************************/
+/* CLKGEN :: PLL_LC_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_LC_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
+#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT       0
+#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PLL_LC_PLL_LDO_CTRL - Ldo voltage control
+ ***************************************************************************/
+/* CLKGEN :: PLL_LC_PLL_LDO_CTRL :: reserved0 [31:06] */
+#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_reserved0_MASK             0xffffffc0
+#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_reserved0_SHIFT            6
+
+/* CLKGEN :: PLL_LC_PLL_LDO_CTRL :: LDO_CTRL [05:00] */
+#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_LDO_CTRL_MASK              0x0000003f
+#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_LDO_CTRL_SHIFT             0
+#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_LDO_CTRL_DEFAULT           0x00000004
+
+/***************************************************************************
+ *PLL_LC_PLL_LDO_PWRON - LDO Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_LC_PLL_LDO_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_LC_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT       0
+#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT     0x00000001
+
+/***************************************************************************
+ *PLL_LC_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_LC_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_LC_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_LOCK_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_LOCK_SHIFT              0
+
+/***************************************************************************
+ *PLL_LC_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_LC_PLL_MISC :: VCO_PREDIV_RATIO [31:31] */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_VCO_PREDIV_RATIO_MASK          0x80000000
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_VCO_PREDIV_RATIO_SHIFT         31
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_VCO_PREDIV_RATIO_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_MISC :: T2D_DELAY_SEL_LOW [30:28] */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_T2D_DELAY_SEL_LOW_MASK         0x70000000
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_T2D_DELAY_SEL_LOW_SHIFT        28
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_T2D_DELAY_SEL_LOW_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_MISC :: SEL_MEASURE_UNIT [27:25] */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_SEL_MEASURE_UNIT_MASK          0x0e000000
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_SEL_MEASURE_UNIT_SHIFT         25
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_SEL_MEASURE_UNIT_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_MISC :: RESET_MEASURE_MODE [24:24] */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_RESET_MEASURE_MODE_MASK        0x01000000
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_RESET_MEASURE_MODE_SHIFT       24
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_RESET_MEASURE_MODE_DEFAULT     0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_MISC :: LOAD_DCO_BYP_WORD [23:23] */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_LOAD_DCO_BYP_WORD_MASK         0x00800000
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_LOAD_DCO_BYP_WORD_SHIFT        23
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_LOAD_DCO_BYP_WORD_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_MISC :: FREQ_BYP_WORD [22:07] */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_FREQ_BYP_WORD_MASK             0x007fff80
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_FREQ_BYP_WORD_SHIFT            7
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_FREQ_BYP_WORD_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_MISC :: EN_VCO_OUTPUT [06:06] */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_VCO_OUTPUT_MASK             0x00000040
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_VCO_OUTPUT_SHIFT            6
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_VCO_OUTPUT_DEFAULT          0x00000001
+
+/* CLKGEN :: PLL_LC_PLL_MISC :: EN_DCO_BYP_WORD [05:05] */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_BYP_WORD_MASK           0x00000020
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_BYP_WORD_SHIFT          5
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_BYP_WORD_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_MISC :: EN_BANGBANG_MODE [04:04] */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_BANGBANG_MODE_MASK          0x00000010
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_BANGBANG_MODE_SHIFT         4
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_BANGBANG_MODE_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_MISC :: CTRL_MEASURE_MODE [03:02] */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CTRL_MEASURE_MODE_MASK         0x0000000c
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CTRL_MEASURE_MODE_SHIFT        2
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CTRL_MEASURE_MODE_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_MISC :: CHANGE_MEASURE_UNIT [01:01] */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CHANGE_MEASURE_UNIT_MASK       0x00000002
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CHANGE_MEASURE_UNIT_SHIFT      1
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CHANGE_MEASURE_UNIT_DEFAULT    0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_MISC :: BOOST_BIAS_CIRCUIT [00:00] */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_BOOST_BIAS_CIRCUIT_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_BOOST_BIAS_CIRCUIT_SHIFT       0
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC_BOOST_BIAS_CIRCUIT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PLL_LC_PLL_MISC2 - Mscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_LC_PLL_MISC2 :: T2D_DELAY_SEL_HIGH [31:31] */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_T2D_DELAY_SEL_HIGH_MASK       0x80000000
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_T2D_DELAY_SEL_HIGH_SHIFT      31
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_T2D_DELAY_SEL_HIGH_DEFAULT    0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_MISC2 :: SEL_TEST_CLK [30:30] */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_TEST_CLK_MASK             0x40000000
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_TEST_CLK_SHIFT            30
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_TEST_CLK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_MISC2 :: SEL_DIFF_REFCLK_SRC [29:29] */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_DIFF_REFCLK_SRC_MASK      0x20000000
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_DIFF_REFCLK_SRC_SHIFT     29
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_DIFF_REFCLK_SRC_DEFAULT   0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_MISC2 :: PLLRESERVED0 [28:11] */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_PLLRESERVED0_MASK             0x1ffff800
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_PLLRESERVED0_SHIFT            11
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_PLLRESERVED0_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_MISC2 :: INTERNAL_RESET_MODE [10:09] */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_INTERNAL_RESET_MODE_MASK      0x00000600
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_INTERNAL_RESET_MODE_SHIFT     9
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_INTERNAL_RESET_MODE_DEFAULT   0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_MISC2 :: EN_TEST_CLK [08:08] */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_TEST_CLK_MASK              0x00000100
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_TEST_CLK_SHIFT             8
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_TEST_CLK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_MISC2 :: EN_BYPCLK_1 [07:07] */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_1_MASK              0x00000080
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_1_SHIFT             7
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_1_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_MISC2 :: EN_BYPCLK_0 [06:06] */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_0_MASK              0x00000040
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_0_SHIFT             6
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_0_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_MISC2 :: DCO_PWM_RATE_CTRL [05:04] */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_DCO_PWM_RATE_CTRL_MASK        0x00000030
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_DCO_PWM_RATE_CTRL_SHIFT       4
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_DCO_PWM_RATE_CTRL_DEFAULT     0x00000002
+
+/* CLKGEN :: PLL_LC_PLL_MISC2 :: CTRL_2ND_POLE [03:00] */
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_CTRL_2ND_POLE_MASK            0x0000000f
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_CTRL_2ND_POLE_SHIFT           0
+#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_CTRL_2ND_POLE_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_LC_PLL_OUTSEL_SEL - selection of the output clock from the PLL core
+ ***************************************************************************/
+/* CLKGEN :: PLL_LC_PLL_OUTSEL_SEL :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_reserved0_MASK           0xfffffff8
+#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_reserved0_SHIFT          3
+
+/* CLKGEN :: PLL_LC_PLL_OUTSEL_SEL :: OUTPUT_SEL [02:00] */
+#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_OUTPUT_SEL_MASK          0x00000007
+#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_OUTPUT_SEL_SHIFT         0
+#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_OUTPUT_SEL_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_LC_PLL_PWRON - Poweron
+ ***************************************************************************/
+/* CLKGEN :: PLL_LC_PLL_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_reserved0_SHIFT               1
+
+/* CLKGEN :: PLL_LC_PLL_PWRON :: PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_PWRON_PLL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_PWRON_PLL_SHIFT               0
+#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_PWRON_PLL_DEFAULT             0x00000001
+
+/***************************************************************************
+ *PLL_LC_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_LC_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_LC_PLL_RESET_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_PLL_LC_PLL_RESET_reserved0_SHIFT               2
+
+/* CLKGEN :: PLL_LC_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETD_MASK                   0x00000002
+#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETD_SHIFT                  1
+#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETD_DEFAULT                0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETA_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETA_SHIFT                  0
+#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETA_DEFAULT                0x00000000
+
+/***************************************************************************
+ *PLL_LC_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_LC_PLL_STATUS :: TEST_STATUS [31:00] */
+#define BCHP_CLKGEN_PLL_LC_PLL_STATUS_TEST_STATUS_MASK             0xffffffff
+#define BCHP_CLKGEN_PLL_LC_PLL_STATUS_TEST_STATUS_SHIFT            0
+
+/***************************************************************************
+ *PLL_LC_PLL_TEST - enable and selection pf PLL test
+ ***************************************************************************/
+/* CLKGEN :: PLL_LC_PLL_TEST :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_LC_PLL_TEST_reserved0_MASK                 0xfffffff0
+#define BCHP_CLKGEN_PLL_LC_PLL_TEST_reserved0_SHIFT                4
+
+/* CLKGEN :: PLL_LC_PLL_TEST :: TEST_SEL [03:01] */
+#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_SEL_MASK                  0x0000000e
+#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_SEL_SHIFT                 1
+#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_SEL_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_LC_PLL_TEST :: TEST_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_ENABLE_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_ENABLE_SHIFT              0
+#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_ENABLE_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xfffff800
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xfffff800
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xfffff800
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000001b
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xfffff800
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xfffff800
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xfffff800
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x0000001b
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_MASK                0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_SHIFT               14
+
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: PDIV [13:10] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_MASK                     0x00003c00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_DEFAULT                  0x00000002
+
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_DEFAULT              0x00000064
+
+/***************************************************************************
+ *PLL_MOCA_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: reserved0 [31:10] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_MASK               0xfffffc00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_SHIFT              10
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000038
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      3
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/***************************************************************************
+ *PLL_MOCA_PLL_LDO_PWRON - LDO Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_LDO_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_MOCA_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK      0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT     0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT   0x00000001
+
+/***************************************************************************
+ *PLL_MOCA_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_RANGE [31:30] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_RANGE_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_RANGE_SHIFT              30
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_RANGE_DEFAULT            0x00000002
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_FB_DIV2 [29:29] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_FB_DIV2_MASK             0x20000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_FB_DIV2_SHIFT            29
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_FB_DIV2_DEFAULT          0x00000001
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_UPDATE [28:28] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_MASK             0x10000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_SHIFT            28
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_SELECT [27:25] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_MASK             0x0e000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_SHIFT            25
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_RESET [24:24] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET_MASK              0x01000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET_SHIFT             24
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_MODE [23:22] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_MASK               0x00c00000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_SHIFT              22
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: PWM_RATE [21:20] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_MASK                0x00300000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_SHIFT               20
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: POST_CTRL_RESETB [19:18] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POST_CTRL_RESETB_MASK        0x000c0000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POST_CTRL_RESETB_SHIFT       18
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POST_CTRL_RESETB_DEFAULT     0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: PLLRESERVED2 [17:16] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED2_MASK            0x00030000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED2_SHIFT           16
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED2_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: PLLRESERVED1 [15:15] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED1_MASK            0x00008000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED1_SHIFT           15
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED1_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: NDIV_RELOCK [14:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_MASK             0x00004000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_SHIFT            14
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: FAST_LOCK [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_MASK               0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_SHIFT              13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_MISC2 - Mscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: PLLRESERVED0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_PLLRESERVED0_MASK           0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_PLLRESERVED0_SHIFT          2
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_PLLRESERVED0_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: LDO [01:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_LDO_MASK                    0x00000003
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_LDO_SHIFT                   0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_LDO_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_PWRON - Poweron
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MOCA_PLL_PWRON :: PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_PWRON_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_PWRON_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_PWRON_PLL_DEFAULT           0x00000001
+
+/***************************************************************************
+ *PLL_MOCA_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_MOCA_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_MOCA_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000012
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000053
+
+/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_DIV :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_reserved0_MASK             0xffffc000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_reserved0_SHIFT            14
+
+/* CLKGEN :: PLL_NETWORK_PLL_DIV :: PDIV [13:10] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_PDIV_MASK                  0x00003c00
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_PDIV_SHIFT                 10
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_PDIV_DEFAULT               0x00000003
+
+/* CLKGEN :: PLL_NETWORK_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_NDIV_INT_MASK              0x000003ff
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_NDIV_INT_SHIFT             0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_NDIV_INT_DEFAULT           0x0000007d
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: reserved0 [31:10] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_reserved0_MASK            0xfffffc00
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_reserved0_SHIFT           10
+
+/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
+
+/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK    0x00000038
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT   3
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_LDO_PWRON - LDO Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_LDO_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRON_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRON_reserved0_SHIFT      1
+
+/* CLKGEN :: PLL_NETWORK_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK   0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT  0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_NETWORK_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_LOST_MASK     0x00000002
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_LOST_SHIFT    1
+
+/* CLKGEN :: PLL_NETWORK_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_SHIFT         0
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: VCO_RANGE [31:30] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_RANGE_MASK            0xc0000000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_RANGE_SHIFT           30
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_RANGE_DEFAULT         0x00000002
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: VCO_FB_DIV2 [29:29] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_FB_DIV2_MASK          0x20000000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_FB_DIV2_SHIFT         29
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_FB_DIV2_DEFAULT       0x00000001
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_UPDATE [28:28] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_UPDATE_MASK          0x10000000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_UPDATE_SHIFT         28
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_UPDATE_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_SELECT [27:25] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_SELECT_MASK          0x0e000000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_SELECT_SHIFT         25
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_SELECT_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_RESET [24:24] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_RESET_MASK           0x01000000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_RESET_SHIFT          24
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_RESET_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_MODE [23:22] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_MODE_MASK            0x00c00000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_MODE_SHIFT           22
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_MODE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: PWM_RATE [21:20] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PWM_RATE_MASK             0x00300000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PWM_RATE_SHIFT            20
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PWM_RATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: POST_CTRL_RESETB [19:18] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_POST_CTRL_RESETB_MASK     0x000c0000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_POST_CTRL_RESETB_SHIFT    18
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_POST_CTRL_RESETB_DEFAULT  0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: PLLRESERVED2 [17:16] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PLLRESERVED2_MASK         0x00030000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PLLRESERVED2_SHIFT        16
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PLLRESERVED2_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: PLLRESERVED1 [15:15] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PLLRESERVED1_MASK         0x00008000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PLLRESERVED1_SHIFT        15
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PLLRESERVED1_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: NDIV_RELOCK [14:14] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_NDIV_RELOCK_MASK          0x00004000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_NDIV_RELOCK_SHIFT         14
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_NDIV_RELOCK_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: FAST_LOCK [13:13] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_FAST_LOCK_MASK            0x00002000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_FAST_LOCK_SHIFT           13
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_FAST_LOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_MASK      0x00000fff
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_SHIFT     0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT   0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_MISC2 - Mscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_MISC2 :: PLLRESERVED0 [31:02] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_PLLRESERVED0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_PLLRESERVED0_SHIFT       2
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_PLLRESERVED0_DEFAULT     0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_MISC2 :: LDO [01:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_LDO_MASK                 0x00000003
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_LDO_SHIFT                0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_LDO_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_PWRON - Poweron
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRON_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRON_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_NETWORK_PLL_PWRON :: PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRON_PWRON_PLL_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRON_PWRON_PLL_SHIFT          0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRON_PWRON_PLL_DEFAULT        0x00000001
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_reserved0_MASK           0xfffffffc
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_reserved0_SHIFT          2
+
+/* CLKGEN :: PLL_NETWORK_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETD_MASK              0x00000002
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETD_SHIFT             1
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETD_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETA_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETA_SHIFT             0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETA_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_reserved0_MASK          0xfffff000
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_reserved0_SHIFT         12
+
+/* CLKGEN :: PLL_NETWORK_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_TEST_STATUS_MASK        0x00000fff
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_TEST_STATUS_SHIFT       0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000004
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000004
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000064
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_MASK               0xffffc000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_SHIFT              14
+
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: PDIV [13:10] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_MASK                    0x00003c00
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_SHIFT                   10
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_DEFAULT                 0x00000002
+
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_MASK                0x000003ff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_SHIFT               0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_DEFAULT             0x0000004e
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: reserved0 [31:10] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_MASK              0xfffffc00
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_SHIFT             10
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x00000038
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     3
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_LDO_PWRON - LDO Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_LDO_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_reserved0_SHIFT        1
+
+/* CLKGEN :: PLL_RAAGA_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK     0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT    0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT  0x00000001
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_MASK       0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT      1
+
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_SHIFT           0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_RANGE [31:30] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_RANGE_MASK              0xc0000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_RANGE_SHIFT             30
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_RANGE_DEFAULT           0x00000002
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_FB_DIV2 [29:29] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_FB_DIV2_MASK            0x20000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_FB_DIV2_SHIFT           29
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_FB_DIV2_DEFAULT         0x00000001
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_UPDATE [28:28] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_MASK            0x10000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_SHIFT           28
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_SELECT [27:25] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_MASK            0x0e000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_SHIFT           25
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_RESET [24:24] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET_MASK             0x01000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET_SHIFT            24
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_MODE [23:22] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_MASK              0x00c00000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_SHIFT             22
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PWM_RATE [21:20] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_MASK               0x00300000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_SHIFT              20
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: POST_CTRL_RESETB [19:18] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POST_CTRL_RESETB_MASK       0x000c0000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POST_CTRL_RESETB_SHIFT      18
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POST_CTRL_RESETB_DEFAULT    0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PLLRESERVED2 [17:16] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED2_MASK           0x00030000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED2_SHIFT          16
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED2_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PLLRESERVED1 [15:15] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED1_MASK           0x00008000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED1_SHIFT          15
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED1_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: NDIV_RELOCK [14:14] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_MASK            0x00004000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_SHIFT           14
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: FAST_LOCK [13:13] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_MASK              0x00002000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_SHIFT             13
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00000fff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_MISC2 - Mscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: PLLRESERVED0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_PLLRESERVED0_MASK          0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_PLLRESERVED0_SHIFT         2
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_PLLRESERVED0_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: LDO [01:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_LDO_MASK                   0x00000003
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_LDO_SHIFT                  0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_LDO_DEFAULT                0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_PWRON - Poweron
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_RAAGA_PLL_PWRON :: PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_PWRON_PLL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_PWRON_PLL_SHIFT            0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_PWRON_PLL_DEFAULT          0x00000001
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_MASK             0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_SHIFT            2
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_MASK                0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_SHIFT               1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_SHIFT               0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_MASK            0xfffff000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_SHIFT           12
+
+/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_SHIFT         0
+
+/***************************************************************************
+ *PLL_SC0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xfffff800
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  11
+
+/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000030
+
+/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_DIV :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_reserved0_MASK                 0xffffc000
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_reserved0_SHIFT                14
+
+/* CLKGEN :: PLL_SC0_PLL_DIV :: PDIV [13:10] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_MASK                      0x00003c00
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_SHIFT                     10
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_DEFAULT                   0x00000002
+
+/* CLKGEN :: PLL_SC0_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_MASK                  0x000003ff
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_DEFAULT               0x00000030
+
+/***************************************************************************
+ *PLL_SC0_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_reserved0_MASK                0xfff00000
+#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_reserved0_SHIFT               20
+
+/* CLKGEN :: PLL_SC0_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_MASK             0x000fffff
+#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_SHIFT            0
+#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_GAIN :: reserved0 [31:10] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_reserved0_MASK                0xfffffc00
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_reserved0_SHIFT               10
+
+/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
+
+/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x00000038
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       3
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/***************************************************************************
+ *PLL_SC0_PLL_LDO_PWRON - LDO Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_LDO_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_SC0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK       0x00000001
+#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT      0
+#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT    0x00000001
+
+/***************************************************************************
+ *PLL_SC0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_LOST_MASK         0x00000002
+#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT        1
+
+/* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_SHIFT             0
+
+/***************************************************************************
+ *PLL_SC0_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_MISC :: VCO_RANGE [31:30] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_RANGE_MASK                0xc0000000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_RANGE_SHIFT               30
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_RANGE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: VCO_FB_DIV2 [29:29] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_FB_DIV2_MASK              0x20000000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_FB_DIV2_SHIFT             29
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_FB_DIV2_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_UPDATE [28:28] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_MASK              0x10000000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_SHIFT             28
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_SELECT [27:25] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_MASK              0x0e000000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_SHIFT             25
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_RESET [24:24] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET_MASK               0x01000000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET_SHIFT              24
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_MODE [23:22] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_MASK                0x00c00000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_SHIFT               22
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: PWM_RATE [21:20] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_MASK                 0x00300000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_SHIFT                20
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: POST_CTRL_RESETB [19:18] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_POST_CTRL_RESETB_MASK         0x000c0000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_POST_CTRL_RESETB_SHIFT        18
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_POST_CTRL_RESETB_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: PLLRESERVED2 [17:16] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED2_MASK             0x00030000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED2_SHIFT            16
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED2_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: PLLRESERVED1 [15:15] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED1_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED1_SHIFT            15
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED1_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: NDIV_RELOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_NDIV_RELOCK_MASK              0x00004000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_NDIV_RELOCK_SHIFT             14
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_NDIV_RELOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: FAST_LOCK [13:13] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_MASK                0x00002000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_SHIFT               13
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00001000
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  12
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         0
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_MISC2 - Mscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_MISC2 :: PLLRESERVED0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_PLLRESERVED0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_PLLRESERVED0_SHIFT           2
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_PLLRESERVED0_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_MISC2 :: LDO [01:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_LDO_MASK                     0x00000003
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_LDO_SHIFT                    0
+#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_LDO_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_PWRON - Poweron
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_SC0_PLL_PWRON :: PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_PWRON_PLL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_PWRON_PLL_SHIFT              0
+#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_PWRON_PLL_DEFAULT            0x00000001
+
+/***************************************************************************
+ *PLL_SC0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_reserved0_MASK               0xfffffffc
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_reserved0_SHIFT              2
+
+/* CLKGEN :: PLL_SC0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_MASK                  0x00000002
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_SHIFT                 1
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_reserved0_MASK              0xfffff000
+#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_reserved0_SHIFT             12
+
+/* CLKGEN :: PLL_SC0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
+#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_TEST_STATUS_SHIFT           0
+
+/***************************************************************************
+ *PLL_SC1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xfffff800
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  11
+
+/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000030
+
+/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_DIV :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_reserved0_MASK                 0xffffc000
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_reserved0_SHIFT                14
+
+/* CLKGEN :: PLL_SC1_PLL_DIV :: PDIV [13:10] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_MASK                      0x00003c00
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_SHIFT                     10
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_DEFAULT                   0x00000002
+
+/* CLKGEN :: PLL_SC1_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_MASK                  0x000003ff
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_DEFAULT               0x00000030
+
+/***************************************************************************
+ *PLL_SC1_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_reserved0_MASK                0xfff00000
+#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_reserved0_SHIFT               20
+
+/* CLKGEN :: PLL_SC1_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_MASK             0x000fffff
+#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_SHIFT            0
+#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_GAIN :: reserved0 [31:10] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_reserved0_MASK                0xfffffc00
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_reserved0_SHIFT               10
+
+/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
+
+/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x00000038
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       3
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/***************************************************************************
+ *PLL_SC1_PLL_LDO_PWRON - LDO Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_LDO_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_SC1_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK       0x00000001
+#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT      0
+#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT    0x00000001
+
+/***************************************************************************
+ *PLL_SC1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_LOST_MASK         0x00000002
+#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT        1
+
+/* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_SHIFT             0
+
+/***************************************************************************
+ *PLL_SC1_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_MISC :: VCO_RANGE [31:30] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_RANGE_MASK                0xc0000000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_RANGE_SHIFT               30
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_RANGE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: VCO_FB_DIV2 [29:29] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_FB_DIV2_MASK              0x20000000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_FB_DIV2_SHIFT             29
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_FB_DIV2_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_UPDATE [28:28] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_MASK              0x10000000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_SHIFT             28
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_SELECT [27:25] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_MASK              0x0e000000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_SHIFT             25
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_RESET [24:24] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET_MASK               0x01000000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET_SHIFT              24
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_MODE [23:22] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_MASK                0x00c00000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_SHIFT               22
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: PWM_RATE [21:20] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_MASK                 0x00300000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_SHIFT                20
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: POST_CTRL_RESETB [19:18] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_POST_CTRL_RESETB_MASK         0x000c0000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_POST_CTRL_RESETB_SHIFT        18
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_POST_CTRL_RESETB_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: PLLRESERVED2 [17:16] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED2_MASK             0x00030000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED2_SHIFT            16
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED2_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: PLLRESERVED1 [15:15] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED1_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED1_SHIFT            15
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED1_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: NDIV_RELOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_NDIV_RELOCK_MASK              0x00004000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_NDIV_RELOCK_SHIFT             14
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_NDIV_RELOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: FAST_LOCK [13:13] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_MASK                0x00002000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_SHIFT               13
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00001000
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  12
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         0
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_MISC2 - Mscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_MISC2 :: PLLRESERVED0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_PLLRESERVED0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_PLLRESERVED0_SHIFT           2
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_PLLRESERVED0_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_MISC2 :: LDO [01:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_LDO_MASK                     0x00000003
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_LDO_SHIFT                    0
+#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_LDO_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_PWRON - Poweron
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_SC1_PLL_PWRON :: PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_PWRON_PLL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_PWRON_PLL_SHIFT              0
+#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_PWRON_PLL_DEFAULT            0x00000001
+
+/***************************************************************************
+ *PLL_SC1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_reserved0_MASK               0xfffffffc
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_reserved0_SHIFT              2
+
+/* CLKGEN :: PLL_SC1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_MASK                  0x00000002
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_SHIFT                 1
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_reserved0_MASK              0xfffff000
+#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_reserved0_SHIFT             12
+
+/* CLKGEN :: PLL_SC1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
+#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_TEST_STATUS_SHIFT           0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_BG_PWRON - Bandgap Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_BG_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_SYS0_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT       0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT     0x00000001
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xfffff800
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000000f
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xfffff800
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000a
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xfffff800
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000000a
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xfffff800
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000a
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK                0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT               14
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [13:10] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK                     0x00003c00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT                  0x00000002
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT              0x00000078
+
+/***************************************************************************
+ *PLL_SYS0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:10] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK               0xfffffc00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT              10
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000038
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      3
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
+
+/***************************************************************************
+ *PLL_SYS0_PLL_HOLD_CH_ALL - Hold PLL all channels
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_SYS0_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK      0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT     0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT   0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_LDO_CTRL - Ldo voltage control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_LDO_CTRL :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_reserved0_MASK           0xffff0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_reserved0_SHIFT          16
+
+/* CLKGEN :: PLL_SYS0_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_MASK            0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_SHIFT           0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_DEFAULT         0x00000005
+
+/***************************************************************************
+ *PLL_SYS0_PLL_LDO_PWRON - LDO Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_LDO_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_SYS0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK      0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT     0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT   0x00000001
+
+/***************************************************************************
+ *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_RANGE_LOW [31:31] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_MASK           0x80000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_SHIFT          31
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_MASK          0x40000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_SHIFT         30
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_DEFAULT       0x00000001
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DIV2 [29:29] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DIV2_MASK                0x20000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DIV2_SHIFT               29
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DIV2_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [28:28] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK             0x10000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT            28
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [27:25] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK             0x0e000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT            25
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET [24:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET_MASK              0x01000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET_SHIFT             24
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [23:22] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK               0x00c00000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT              22
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: REF_ALT_OFFS [21:21] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_MASK            0x00200000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_SHIFT           21
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [20:19] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK                0x00180000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT               19
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: POST_CTRL_RESETB [18:17] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_MASK        0x00060000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_SHIFT       17
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_DEFAULT     0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK               0x00008000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT              15
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DITHER_DISABLE [14:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DITHER_DISABLE_MASK          0x00004000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DITHER_DISABLE_SHIFT         14
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DITHER_DISABLE_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC2 - Mscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: PLLRESERVED0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_PLLRESERVED0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_PLLRESERVED0_SHIFT          1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_PLLRESERVED0_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_SHIFT         0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_PWRON - Poweron
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_PWRON :: PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_PWRON_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_PWRON_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_PWRON_PLL_DEFAULT           0x00000001
+
+/***************************************************************************
+ *PLL_SYS0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_RESET :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_RESET :: RESETD [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_BG_PWRON - Bandgap Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_BG_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_VCXO0_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_BG_PWRON_PLL_MASK       0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT      0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT    0x00000001
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000007d
+
+/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_DIV :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_reserved0_MASK               0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_reserved0_SHIFT              14
+
+/* CLKGEN :: PLL_VCXO0_PLL_DIV :: PDIV [13:10] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_MASK                    0x00003c00
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_SHIFT                   10
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_DEFAULT                 0x00000002
+
+/* CLKGEN :: PLL_VCXO0_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_MASK                0x000003ff
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_DEFAULT             0x00000040
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_reserved0_MASK              0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_reserved0_SHIFT             20
+
+/* CLKGEN :: PLL_VCXO0_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_MASK           0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_SHIFT          0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: reserved0 [31:10] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_reserved0_MASK              0xfffffc00
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_reserved0_SHIFT             10
+
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x00000038
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     3
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_HOLD_CH_ALL - Hold PLL all channels
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_reserved0_SHIFT      1
+
+/* CLKGEN :: PLL_VCXO0_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK     0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT    0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT  0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_LDO_CTRL - Ldo voltage control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_LDO_CTRL :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_reserved0_MASK          0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_reserved0_SHIFT         16
+
+/* CLKGEN :: PLL_VCXO0_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_LDO_CTRL_MASK           0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_LDO_CTRL_SHIFT          0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_LDO_CTRL_DEFAULT        0x00000005
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_LDO_PWRON - LDO Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_LDO_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_reserved0_SHIFT        1
+
+/* CLKGEN :: PLL_VCXO0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK     0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT    0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT  0x00000001
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_LOST_MASK       0x00000002
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT      1
+
+/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_SHIFT           0
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_RANGE_LOW [31:31] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_LOW_MASK          0x80000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_LOW_SHIFT         31
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_LOW_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_HIGH_MASK         0x40000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_HIGH_SHIFT        30
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_HIGH_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_DIV2 [29:29] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DIV2_MASK               0x20000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DIV2_SHIFT              29
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DIV2_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_UPDATE [28:28] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_MASK            0x10000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_SHIFT           28
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_SELECT [27:25] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_MASK            0x0e000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_SHIFT           25
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_RESET [24:24] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET_MASK             0x01000000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET_SHIFT            24
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_MODE [23:22] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_MASK              0x00c00000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_SHIFT             22
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: REF_ALT_OFFS [21:21] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REF_ALT_OFFS_MASK           0x00200000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REF_ALT_OFFS_SHIFT          21
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REF_ALT_OFFS_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: PWM_RATE [20:19] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_SHIFT              19
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: POST_CTRL_RESETB [18:17] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_POST_CTRL_RESETB_MASK       0x00060000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_POST_CTRL_RESETB_SHIFT      17
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_POST_CTRL_RESETB_DEFAULT    0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_NDIV_RELOCK_MASK            0x00010000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_NDIV_RELOCK_SHIFT           16
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_NDIV_RELOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: FAST_LOCK [15:15] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_MASK              0x00008000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_SHIFT             15
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DITHER_DISABLE [14:14] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DITHER_DISABLE_MASK         0x00004000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DITHER_DISABLE_SHIFT        14
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DITHER_DISABLE_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00001ffe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_SHIFT              0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_MISC2 - Mscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_MISC2 :: PLLRESERVED0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_PLLRESERVED0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_PLLRESERVED0_SHIFT         1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_PLLRESERVED0_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_DIG_INPUT_SEL_MASK         0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_DIG_INPUT_SEL_SHIFT        0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_DIG_INPUT_SEL_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_PWRON - Poweron
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_VCXO0_PLL_PWRON :: PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_PWRON_PLL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_PWRON_PLL_SHIFT            0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_PWRON_PLL_DEFAULT          0x00000001
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_reserved0_MASK             0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_reserved0_SHIFT            2
+
+/* CLKGEN :: PLL_VCXO0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_MASK                0x00000002
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_SHIFT               1
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_reserved0_MASK            0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_reserved0_SHIFT           12
+
+/* CLKGEN :: PLL_VCXO0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_TEST_STATUS_SHIFT         0
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_BG_PWRON - Bandgap Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_BG_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_VCXO1_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_BG_PWRON_PLL_MASK       0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT      0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT    0x00000001
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000007d
+
+/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_DIV :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_reserved0_MASK               0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_reserved0_SHIFT              14
+
+/* CLKGEN :: PLL_VCXO1_PLL_DIV :: PDIV [13:10] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_MASK                    0x00003c00
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_SHIFT                   10
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_DEFAULT                 0x00000002
+
+/* CLKGEN :: PLL_VCXO1_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_MASK                0x000003ff
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_DEFAULT             0x00000040
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_reserved0_MASK              0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_reserved0_SHIFT             20
+
+/* CLKGEN :: PLL_VCXO1_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_MASK           0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_SHIFT          0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: reserved0 [31:10] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_reserved0_MASK              0xfffffc00
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_reserved0_SHIFT             10
+
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x00000038
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     3
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_HOLD_CH_ALL - Hold PLL all channels
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_reserved0_SHIFT      1
+
+/* CLKGEN :: PLL_VCXO1_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK     0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT    0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT  0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_LDO_CTRL - Ldo voltage control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_LDO_CTRL :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_reserved0_MASK          0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_reserved0_SHIFT         16
+
+/* CLKGEN :: PLL_VCXO1_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_LDO_CTRL_MASK           0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_LDO_CTRL_SHIFT          0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_LDO_CTRL_DEFAULT        0x00000005
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_LDO_PWRON - LDO Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_LDO_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_reserved0_SHIFT        1
+
+/* CLKGEN :: PLL_VCXO1_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK     0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT    0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT  0x00000001
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_LOST_MASK       0x00000002
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT      1
+
+/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_SHIFT           0
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_RANGE_LOW [31:31] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_LOW_MASK          0x80000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_LOW_SHIFT         31
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_LOW_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_HIGH_MASK         0x40000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_HIGH_SHIFT        30
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_HIGH_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_DIV2 [29:29] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DIV2_MASK               0x20000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DIV2_SHIFT              29
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DIV2_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_UPDATE [28:28] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_MASK            0x10000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_SHIFT           28
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_SELECT [27:25] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_MASK            0x0e000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_SHIFT           25
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_RESET [24:24] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET_MASK             0x01000000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET_SHIFT            24
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_MODE [23:22] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_MASK              0x00c00000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_SHIFT             22
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: REF_ALT_OFFS [21:21] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REF_ALT_OFFS_MASK           0x00200000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REF_ALT_OFFS_SHIFT          21
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REF_ALT_OFFS_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: PWM_RATE [20:19] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_SHIFT              19
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: POST_CTRL_RESETB [18:17] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_POST_CTRL_RESETB_MASK       0x00060000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_POST_CTRL_RESETB_SHIFT      17
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_POST_CTRL_RESETB_DEFAULT    0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_NDIV_RELOCK_MASK            0x00010000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_NDIV_RELOCK_SHIFT           16
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_NDIV_RELOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: FAST_LOCK [15:15] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_MASK              0x00008000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_SHIFT             15
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DITHER_DISABLE [14:14] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DITHER_DISABLE_MASK         0x00004000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DITHER_DISABLE_SHIFT        14
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DITHER_DISABLE_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00001ffe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_SHIFT              0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_MISC2 - Mscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_MISC2 :: PLLRESERVED0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_PLLRESERVED0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_PLLRESERVED0_SHIFT         1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_PLLRESERVED0_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_DIG_INPUT_SEL_MASK         0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_DIG_INPUT_SEL_SHIFT        0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_DIG_INPUT_SEL_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_PWRON - Poweron
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_VCXO1_PLL_PWRON :: PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_PWRON_PLL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_PWRON_PLL_SHIFT            0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_PWRON_PLL_DEFAULT          0x00000001
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_reserved0_MASK             0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_reserved0_SHIFT            2
+
+/* CLKGEN :: PLL_VCXO1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_MASK                0x00000002
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_SHIFT               1
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_reserved0_MASK            0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_reserved0_SHIFT           12
+
+/* CLKGEN :: PLL_VCXO1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_TEST_STATUS_SHIFT         0
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_BG_PWRON - Bandgap Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_BG_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_VCXO2_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON_BG_PWRON_PLL_MASK       0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT      0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT    0x00000001
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000007d
+
+/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_DIV :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_reserved0_MASK               0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_reserved0_SHIFT              14
+
+/* CLKGEN :: PLL_VCXO2_PLL_DIV :: PDIV [13:10] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_MASK                    0x00003c00
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_SHIFT                   10
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_DEFAULT                 0x00000002
+
+/* CLKGEN :: PLL_VCXO2_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_MASK                0x000003ff
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_DEFAULT             0x00000040
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_reserved0_MASK              0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_reserved0_SHIFT             20
+
+/* CLKGEN :: PLL_VCXO2_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_MASK           0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_SHIFT          0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: reserved0 [31:10] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_reserved0_MASK              0xfffffc00
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_reserved0_SHIFT             10
+
+/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x00000038
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     3
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_HOLD_CH_ALL - Hold PLL all channels
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL_reserved0_SHIFT      1
+
+/* CLKGEN :: PLL_VCXO2_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK     0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT    0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT  0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_LDO_CTRL - Ldo voltage control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_LDO_CTRL :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL_reserved0_MASK          0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL_reserved0_SHIFT         16
+
+/* CLKGEN :: PLL_VCXO2_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL_LDO_CTRL_MASK           0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL_LDO_CTRL_SHIFT          0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL_LDO_CTRL_DEFAULT        0x00000005
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_LDO_PWRON - LDO Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_LDO_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON_reserved0_SHIFT        1
+
+/* CLKGEN :: PLL_VCXO2_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK     0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT    0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT  0x00000001
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_VCXO2_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_LOST_MASK       0x00000002
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_LOST_SHIFT      1
+
+/* CLKGEN :: PLL_VCXO2_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_SHIFT           0
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCO_RANGE_LOW [31:31] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_LOW_MASK          0x80000000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_LOW_SHIFT         31
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_LOW_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_HIGH_MASK         0x40000000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_HIGH_SHIFT        30
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_HIGH_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCO_DIV2 [29:29] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DIV2_MASK               0x20000000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DIV2_SHIFT              29
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DIV2_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_UPDATE [28:28] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_MASK            0x10000000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_SHIFT           28
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_SELECT [27:25] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_MASK            0x0e000000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_SHIFT           25
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_RESET [24:24] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET_MASK             0x01000000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET_SHIFT            24
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_MODE [23:22] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_MASK              0x00c00000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_SHIFT             22
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: REF_ALT_OFFS [21:21] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REF_ALT_OFFS_MASK           0x00200000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REF_ALT_OFFS_SHIFT          21
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REF_ALT_OFFS_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: PWM_RATE [20:19] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_SHIFT              19
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: POST_CTRL_RESETB [18:17] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_POST_CTRL_RESETB_MASK       0x00060000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_POST_CTRL_RESETB_SHIFT      17
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_POST_CTRL_RESETB_DEFAULT    0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_NDIV_RELOCK_MASK            0x00010000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_NDIV_RELOCK_SHIFT           16
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_NDIV_RELOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: FAST_LOCK [15:15] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_MASK              0x00008000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_SHIFT             15
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: DITHER_DISABLE [14:14] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DITHER_DISABLE_MASK         0x00004000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DITHER_DISABLE_SHIFT        14
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DITHER_DISABLE_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00001ffe
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       1
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_SHIFT              0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_MISC2 - Mscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_MISC2 :: PLLRESERVED0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_PLLRESERVED0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_PLLRESERVED0_SHIFT         1
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_PLLRESERVED0_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_DIG_INPUT_SEL_MASK         0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_DIG_INPUT_SEL_SHIFT        0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_DIG_INPUT_SEL_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_PWRON - Poweron
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_VCXO2_PLL_PWRON :: PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON_PWRON_PLL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON_PWRON_PLL_SHIFT            0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON_PWRON_PLL_DEFAULT          0x00000001
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_reserved0_MASK             0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_reserved0_SHIFT            2
+
+/* CLKGEN :: PLL_VCXO2_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_MASK                0x00000002
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_SHIFT               1
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_reserved0_MASK            0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_reserved0_SHIFT           12
+
+/* CLKGEN :: PLL_VCXO2_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_TEST_STATUS_SHIFT         0
+
+/***************************************************************************
+ *PLL_XPT_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xfffff800
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  11
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK   0xfffff800
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT  11
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT   1
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK   0xfffff800
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT  11
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT   1
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000000f
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK   0xfffff800
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT  11
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT   1
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000c
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK   0xfffff800
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT  11
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT   1
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000064
+
+/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_DIV :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_reserved0_MASK                 0xffffc000
+#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_reserved0_SHIFT                14
+
+/* CLKGEN :: PLL_XPT_PLL_DIV :: PDIV [13:10] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_MASK                      0x00003c00
+#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_SHIFT                     10
+#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_DEFAULT                   0x00000002
+
+/* CLKGEN :: PLL_XPT_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_MASK                  0x000003ff
+#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_SHIFT                 0
+#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_DEFAULT               0x00000078
+
+/***************************************************************************
+ *PLL_XPT_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_GAIN :: reserved0 [31:10] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_reserved0_MASK                0xfffffc00
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_reserved0_SHIFT               10
+
+/* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005
+
+/* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x00000038
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       3
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
+#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/***************************************************************************
+ *PLL_XPT_PLL_LDO_PWRON - LDO Power on
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_LDO_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_XPT_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK       0x00000001
+#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT      0
+#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT    0x00000001
+
+/***************************************************************************
+ *PLL_XPT_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_LOST_MASK         0x00000002
+#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_LOST_SHIFT        1
+
+/* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_SHIFT             0
+
+/***************************************************************************
+ *PLL_XPT_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_MISC :: VCO_RANGE [31:30] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_RANGE_MASK                0xc0000000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_RANGE_SHIFT               30
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_RANGE_DEFAULT             0x00000002
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: VCO_FB_DIV2 [29:29] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_FB_DIV2_MASK              0x20000000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_FB_DIV2_SHIFT             29
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_FB_DIV2_DEFAULT           0x00000001
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_UPDATE [28:28] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_MASK              0x10000000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_SHIFT             28
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_SELECT [27:25] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_MASK              0x0e000000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_SHIFT             25
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_RESET [24:24] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET_MASK               0x01000000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET_SHIFT              24
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_MODE [23:22] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_MASK                0x00c00000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_SHIFT               22
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: PWM_RATE [21:20] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_MASK                 0x00300000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_SHIFT                20
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: POST_CTRL_RESETB [19:18] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POST_CTRL_RESETB_MASK         0x000c0000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POST_CTRL_RESETB_SHIFT        18
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POST_CTRL_RESETB_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: PLLRESERVED2 [17:16] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED2_MASK             0x00030000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED2_SHIFT            16
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED2_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: PLLRESERVED1 [15:15] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED1_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED1_SHIFT            15
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED1_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: NDIV_RELOCK [14:14] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_MASK              0x00004000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_SHIFT             14
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: FAST_LOCK [13:13] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_MASK                0x00002000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_SHIFT               13
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00001000
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  12
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         0
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_MISC2 - Mscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_MISC2 :: PLLRESERVED0 [31:02] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_PLLRESERVED0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_PLLRESERVED0_SHIFT           2
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_PLLRESERVED0_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_MISC2 :: LDO [01:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_LDO_MASK                     0x00000003
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_LDO_SHIFT                    0
+#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_LDO_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_PWRON - Poweron
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_PWRON :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_XPT_PLL_PWRON :: PWRON_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_PWRON_PLL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_PWRON_PLL_SHIFT              0
+#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_PWRON_PLL_DEFAULT            0x00000001
+
+/***************************************************************************
+ *PLL_XPT_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_RESET :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_XPT_PLL_RESET :: RESETD [00:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_SHIFT                 0
+#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_XPT_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_XPT_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_reserved0_MASK              0xfffff000
+#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_reserved0_SHIFT             12
+
+/* CLKGEN :: PLL_XPT_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
+#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_TEST_STATUS_SHIFT           0
+
+/***************************************************************************
+ *ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE - Disable ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: DISABLE_QDAC_DACADC_CLOCK [00:00] */
+#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_QDAC_DACADC_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_QDAC_DACADC_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_QDAC_DACADC_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: DISABLE_QDAC_DACADC_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_QDAC_DACADC_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_QDAC_DACADC_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE - Disable ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: DISABLE_SYSTEM_54_VR_CLOCK [00:00] */
+#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_SYSTEM_54_VR_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_SYSTEM_54_VR_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_SYSTEM_54_VR_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSTEM_54_VR_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSTEM_54_VR_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSTEM_54_VR_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVP_TOP_INST_CLOCK_ENABLE - Bvn mvp top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffff0
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  4
+
+/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_BVB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_BVB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_BVB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_BVB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_54_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_54_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_54_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
+
+/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_SCB_CLOCK_ENABLE_STATUS [03:03] */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_SCB_CLOCK_ENABLE_STATUS_SHIFT 3
+
+/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_BVB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_BVB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_BVB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_54_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_54_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *BVN_TOP_INST_CLOCK_ENABLE - Bvn top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffff0
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      4
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_GISB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_GISB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_GISB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_BVB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_BVB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_BVB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_BVB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_54_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_54_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_54_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *BVN_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_SCB_CLOCK_ENABLE_STATUS [03:03] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_SCB_CLOCK_ENABLE_STATUS_SHIFT 3
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_GISB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_GISB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_BVB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_BVB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_BVB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_54_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_54_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks
+ ***************************************************************************/
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT           1
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_OSC_DIGITAL_CLOCK [00:00] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CLKGEN_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_SHIFT    1
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: DISABLE_OSC_DIGITAL_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_OSC_DIGITAL_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_OSC_DIGITAL_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_CONTROL - Clock Monitor Control
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT          4
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK   0x00000008
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT  3
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK    0x00000004
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT   2
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK      0x00000002
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT     1
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT   0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK  0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT         1
+
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK     0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT    0
+
+/***************************************************************************
+ *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_CLOCK_DISABLE - Disable CORE_XPT_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_MASK     0xffffffe0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_SHIFT    5
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:05] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 5
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_81_CLOCK_STATUS [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_81_CLOCK_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_81_CLOCK_STATUS_SHIFT 4
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_54_CLOCK_STATUS [03:03] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_54_CLOCK_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_54_CLOCK_STATUS_SHIFT 3
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_40P5_CLOCK_STATUS [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_40P5_CLOCK_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_40P5_CLOCK_STATUS_SHIFT 2
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_27_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_27_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_27_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE_STATUS :: DISABLE_XPT_20P25_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_20P25_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_STATUS_DISABLE_XPT_20P25_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_CLOCK_ENABLE - Core xpt inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_MASK      0xffffffe0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_SHIFT     5
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_GISB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_GISB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_GISB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_CORE_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_54_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_54_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_54_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CORE_XPT_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_SCB_CLOCK_ENABLE_STATUS [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_SCB_CLOCK_ENABLE_STATUS_SHIFT 4
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_GISB_CLOCK_ENABLE_STATUS [03:03] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_GISB_CLOCK_ENABLE_STATUS_SHIFT 3
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_CORE_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_CORE_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_54_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_54_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_OBSERVE_CLOCK - Core xpt inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HR_INST_CLOCK_DISABLE - Disable DVP_HR_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE :: DISABLE_DVPHR_ALWAYSON_CLOCK [00:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HR_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE_STATUS :: DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DVP_HR_INST_CLOCK_ENABLE - Dvp hr inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffff8
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_reserved0_SHIFT       3
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_HD_DVI_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_HD_DVI_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_HD_DVI_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_HD_DVI_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_BVB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_BVB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_BVB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_BVB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_54_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_54_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_54_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DVP_HR_INST_CLOCK_ENABLE0 - Dvp hr inst clock enable0
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE0 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_reserved0_SHIFT      1
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE0 :: DVPHR_108_CLOCK_ENABLE0 [00:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_DVPHR_108_CLOCK_ENABLE0_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_DVPHR_108_CLOCK_ENABLE0_SHIFT 0
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_DVPHR_108_CLOCK_ENABLE0_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DVP_HR_INST_CLOCK_ENABLE0_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE0_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE0_STATUS :: DVPHR_108_CLOCK_ENABLE0_STATUS [00:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_STATUS_DVPHR_108_CLOCK_ENABLE0_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE0_STATUS_DVPHR_108_CLOCK_ENABLE0_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DVP_HR_INST_CLOCK_ENABLE2 - Dvp hr inst clock enable2
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE2_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE2_reserved0_SHIFT      1
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE2 :: DVPHR_108_CLOCK_ENABLE2 [00:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE2_DVPHR_108_CLOCK_ENABLE2_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE2_DVPHR_108_CLOCK_ENABLE2_SHIFT 0
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE2_DVPHR_108_CLOCK_ENABLE2_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DVP_HR_INST_CLOCK_ENABLE2_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE2_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE2_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE2_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE2_STATUS :: DVPHR_108_CLOCK_ENABLE2_STATUS [00:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE2_STATUS_DVPHR_108_CLOCK_ENABLE2_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE2_STATUS_DVPHR_108_CLOCK_ENABLE2_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DVP_HR_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_HD_DVI_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_HD_DVI_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_HD_DVI_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_BVB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_BVB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_BVB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_54_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_54_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DVP_HR_INST_OBSERVE_CLOCK - Dvp hr inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_INST_CLOCK_DISABLE - Disable DVP_HT_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE_STATUS :: DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DVP_HT_INST_CLOCK_ENABLE - Dvp ht inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_SHIFT       2
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_54_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_54_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_54_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DVP_HT_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_54_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_54_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DVP_HT_INST_ENABLE - Dvp ht inst enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE_reserved0_SHIFT             1
+
+/* CLKGEN :: DVP_HT_INST_ENABLE :: DVPHT_CLK_VEC_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE_DVPHT_CLK_VEC_ENABLE_MASK   0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE_DVPHT_CLK_VEC_ENABLE_SHIFT  0
+#define BCHP_CLKGEN_DVP_HT_INST_ENABLE_DVPHT_CLK_VEC_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DVP_HT_INST_OBSERVE_CLOCK - Dvp ht inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EAGLET_TOP_INST_CLOCK_DISABLE - Disable EAGLET_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: EAGLET_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: EAGLET_TOP_INST_CLOCK_DISABLE :: DISABLE_CPU_SLOWCPU_CLOCK [00:00] */
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_DISABLE_CPU_SLOWCPU_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_DISABLE_CPU_SLOWCPU_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_DISABLE_CPU_SLOWCPU_CLOCK_DEFAULT 0x00000001
+
+/***************************************************************************
+ *EAGLET_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: EAGLET_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: EAGLET_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_CPU_SLOWCPU_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CPU_SLOWCPU_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CPU_SLOWCPU_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *EAGLET_TOP_INST_CLOCK_ENABLE - Eaglet top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_reserved0_MASK    0xfffffff8
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT   3
+
+/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE :: CPU_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE :: CPU_GISB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_GISB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_GISB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE :: CPU_54_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_54_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_54_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_CPU_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *EAGLET_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE_STATUS :: CPU_SCB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_CPU_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_CPU_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE_STATUS :: CPU_GISB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_CPU_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_CPU_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: EAGLET_TOP_INST_CLOCK_ENABLE_STATUS :: CPU_54_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_CPU_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_EAGLET_TOP_INST_CLOCK_ENABLE_STATUS_CPU_54_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *EGPHY28_1PORT_33V_90O_FC_INST_DIV5 - Egphy28 1port 33v 90o fc inst div5
+ ***************************************************************************/
+/* CLKGEN :: EGPHY28_1PORT_33V_90O_FC_INST_DIV5 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_DIV5_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_DIV5_reserved0_SHIFT 1
+
+/* CLKGEN :: EGPHY28_1PORT_33V_90O_FC_INST_DIV5 :: EGPHY_PLL_SEL_DIV5 [00:00] */
+#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_DIV5_EGPHY_PLL_SEL_DIV5_MASK 0x00000001
+#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_DIV5_EGPHY_PLL_SEL_DIV5_SHIFT 0
+#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_DIV5_EGPHY_PLL_SEL_DIV5_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGPHY28_1PORT_33V_90O_FC_INST_SEL - Egphy28 1port 33v 90o fc inst sel
+ ***************************************************************************/
+/* CLKGEN :: EGPHY28_1PORT_33V_90O_FC_INST_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_SEL_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_SEL_reserved0_SHIFT 1
+
+/* CLKGEN :: EGPHY28_1PORT_33V_90O_FC_INST_SEL :: EGPHY_PLL_CLK_SEL [00:00] */
+#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_SEL_EGPHY_PLL_CLK_SEL_MASK 0x00000001
+#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_SEL_EGPHY_PLL_CLK_SEL_SHIFT 0
+#define BCHP_CLKGEN_EGPHY28_1PORT_33V_90O_FC_INST_SEL_EGPHY_PLL_CLK_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE - Graphics inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_54_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_54_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_54_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE0 - Graphics inst clock enable0
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE0 :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_reserved0_SHIFT    2
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE0 :: GFX_M2MC0_SCB_CLOCK_ENABLE0 [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_GFX_M2MC0_SCB_CLOCK_ENABLE0_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_GFX_M2MC0_SCB_CLOCK_ENABLE0_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_GFX_M2MC0_SCB_CLOCK_ENABLE0_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE0 :: GFX_M2MC0_GISB_CLOCK_ENABLE0 [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_GFX_M2MC0_GISB_CLOCK_ENABLE0_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_GFX_M2MC0_GISB_CLOCK_ENABLE0_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_GFX_M2MC0_GISB_CLOCK_ENABLE0_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE0_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE0_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_STATUS_reserved0_SHIFT 2
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE0_STATUS :: GFX_M2MC0_SCB_CLOCK_ENABLE0_STATUS [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_STATUS_GFX_M2MC0_SCB_CLOCK_ENABLE0_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_STATUS_GFX_M2MC0_SCB_CLOCK_ENABLE0_STATUS_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE0_STATUS :: GFX_M2MC0_GISB_CLOCK_ENABLE0_STATUS [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_STATUS_GFX_M2MC0_GISB_CLOCK_ENABLE0_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_STATUS_GFX_M2MC0_GISB_CLOCK_ENABLE0_STATUS_SHIFT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE1 - Graphics inst clock enable1
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE1 :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_reserved0_SHIFT    2
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE1 :: GFX_M2MC1_SCB_CLOCK_ENABLE1 [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_GFX_M2MC1_SCB_CLOCK_ENABLE1_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_GFX_M2MC1_SCB_CLOCK_ENABLE1_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_GFX_M2MC1_SCB_CLOCK_ENABLE1_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE1 :: GFX_M2MC1_GISB_CLOCK_ENABLE1 [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_GFX_M2MC1_GISB_CLOCK_ENABLE1_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_GFX_M2MC1_GISB_CLOCK_ENABLE1_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_GFX_M2MC1_GISB_CLOCK_ENABLE1_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE1_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE1_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_STATUS_reserved0_SHIFT 2
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE1_STATUS :: GFX_M2MC1_SCB_CLOCK_ENABLE1_STATUS [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_STATUS_GFX_M2MC1_SCB_CLOCK_ENABLE1_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_STATUS_GFX_M2MC1_SCB_CLOCK_ENABLE1_STATUS_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE1_STATUS :: GFX_M2MC1_GISB_CLOCK_ENABLE1_STATUS [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_STATUS_GFX_M2MC1_GISB_CLOCK_ENABLE1_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_STATUS_GFX_M2MC1_GISB_CLOCK_ENABLE1_STATUS_SHIFT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE_M2MC0 - Graphics inst clock enable m2mc0
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0 :: GFX_M2MC0_CLOCK_ENABLE_M2MC0 [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_CLOCK_ENABLE_M2MC0_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_CLOCK_ENABLE_M2MC0_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_CLOCK_ENABLE_M2MC0_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS :: GFX_M2MC0_CLOCK_ENABLE_M2MC0_STATUS [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_GFX_M2MC0_CLOCK_ENABLE_M2MC0_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_GFX_M2MC0_CLOCK_ENABLE_M2MC0_STATUS_SHIFT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE_M2MC1 - Graphics inst clock enable m2mc1
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1 :: GFX_M2MC1_CLOCK_ENABLE_M2MC1 [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_CLOCK_ENABLE_M2MC1_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_CLOCK_ENABLE_M2MC1_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_CLOCK_ENABLE_M2MC1_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS :: GFX_M2MC1_CLOCK_ENABLE_M2MC1_STATUS [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_M2MC1_CLOCK_ENABLE_M2MC1_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_M2MC1_CLOCK_ENABLE_M2MC1_STATUS_SHIFT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_STATUS :: GFX_54_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_GFX_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_GFX_54_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_OBSERVE_CLOCK - Graphics inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_INST_CLOCK_DISABLE - Disable HIF_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: reserved0 [31:06] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_SHIFT         6
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_EBI_CLOCK [05:05] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_NAND_DDR_CLOCK [04:04] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_NAND_DDR_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_NAND_DDR_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_NAND_DDR_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [03:03] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_EMMC_CLOCK [02:02] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CARD_CLOCK [01:01] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_ALWAYSON_CLOCK [00:00] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:06] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_reserved0_MASK   0xffffffc0
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT  6
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_EBI_CLOCK_STATUS [05:05] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_EBI_CLOCK_STATUS_MASK 0x00000020
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_EBI_CLOCK_STATUS_SHIFT 5
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_NAND_DDR_CLOCK_STATUS [04:04] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_NAND_DDR_CLOCK_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_NAND_DDR_CLOCK_STATUS_SHIFT 4
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SPI_CLOCK_STATUS [03:03] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_SHIFT 3
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS [02:02] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS_SHIFT 2
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_CARD_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_ALWAYSON_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_ALWAYSON_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *HIF_INST_CLOCK_ENABLE - Hif inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_reserved0_SHIFT          1
+
+/* CLKGEN :: HIF_INST_CLOCK_ENABLE :: HIF_54_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_HIF_54_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_HIF_54_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_HIF_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *HIF_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS_reserved0_MASK    0xfffffffe
+#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT   1
+
+/* CLKGEN :: HIF_INST_CLOCK_ENABLE_STATUS :: HIF_54_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS_HIF_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS_HIF_54_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *HIF_INST_OBSERVE_CLOCK - Hif inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HVD2_TOP_INST_CLOCK_ENABLE - Hvd2 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: HVD2_TOP_INST_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xffffffe0
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     5
+
+/* CLKGEN :: HVD2_TOP_INST_CLOCK_ENABLE :: HVD2_SCB_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_HVD2_SCB_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_HVD2_SCB_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_HVD2_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: HVD2_TOP_INST_CLOCK_ENABLE :: HVD2_GISB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_HVD2_GISB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_HVD2_GISB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_HVD2_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: HVD2_TOP_INST_CLOCK_ENABLE :: HVD2_CPU_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_HVD2_CPU_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_HVD2_CPU_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_HVD2_CPU_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: HVD2_TOP_INST_CLOCK_ENABLE :: HVD2_CORE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_HVD2_CORE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_HVD2_CORE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_HVD2_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: HVD2_TOP_INST_CLOCK_ENABLE :: HVD2_54_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_HVD2_54_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_HVD2_54_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_HVD2_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *HVD2_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: HVD2_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5
+
+/* CLKGEN :: HVD2_TOP_INST_CLOCK_ENABLE_STATUS :: HVD2_SCB_CLOCK_ENABLE_STATUS [04:04] */
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_STATUS_HVD2_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_STATUS_HVD2_SCB_CLOCK_ENABLE_STATUS_SHIFT 4
+
+/* CLKGEN :: HVD2_TOP_INST_CLOCK_ENABLE_STATUS :: HVD2_GISB_CLOCK_ENABLE_STATUS [03:03] */
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_STATUS_HVD2_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_STATUS_HVD2_GISB_CLOCK_ENABLE_STATUS_SHIFT 3
+
+/* CLKGEN :: HVD2_TOP_INST_CLOCK_ENABLE_STATUS :: HVD2_CPU_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_STATUS_HVD2_CPU_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_STATUS_HVD2_CPU_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: HVD2_TOP_INST_CLOCK_ENABLE_STATUS :: HVD2_CORE_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_STATUS_HVD2_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_STATUS_HVD2_CORE_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: HVD2_TOP_INST_CLOCK_ENABLE_STATUS :: HVD2_54_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_STATUS_HVD2_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_HVD2_TOP_INST_CLOCK_ENABLE_STATUS_HVD2_54_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *HVD2_TOP_INST_OBSERVE_CLOCK - Hvd2 top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: HVD2_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_HVD2_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_HVD2_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: HVD2_TOP_INST_OBSERVE_CLOCK :: HVD2_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_HVD2_TOP_INST_OBSERVE_CLOCK_HVD2_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_HVD2_TOP_INST_OBSERVE_CLOCK_HVD2_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_HVD2_TOP_INST_OBSERVE_CLOCK_HVD2_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HVD2_TOP_INST_OBSERVE_CLOCK :: HVD2_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_HVD2_TOP_INST_OBSERVE_CLOCK_HVD2_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_HVD2_TOP_INST_OBSERVE_CLOCK_HVD2_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_HVD2_TOP_INST_OBSERVE_CLOCK_HVD2_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HVD2_TOP_INST_OBSERVE_CLOCK :: HVD2_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_HVD2_TOP_INST_OBSERVE_CLOCK_HVD2_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_HVD2_TOP_INST_OBSERVE_CLOCK_HVD2_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_HVD2_TOP_INST_OBSERVE_CLOCK_HVD2_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HVD_SID1_TOP_INST_CLOCK_ENABLE - Hvd sid1 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_reserved0_MASK  0xffffffe0
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 5
+
+/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE :: HVD1_SCB_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD1_SCB_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD1_SCB_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE :: HVD1_GISB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD1_GISB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD1_GISB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD1_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE :: HVD1_CPU_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD1_CPU_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD1_CPU_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD1_CPU_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE :: HVD1_CORE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD1_CORE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD1_CORE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD1_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE :: HVD1_54_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD1_54_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD1_54_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_HVD1_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *HVD_SID1_TOP_INST_CLOCK_ENABLE_SID - Hvd sid1 top inst clock enable sid
+ ***************************************************************************/
+/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE_SID :: reserved0 [31:01] */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_reserved0_SHIFT 1
+
+/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE_SID :: SID_CORE_CLOCK_ENABLE_SID [00:00] */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_SID_CORE_CLOCK_ENABLE_SID_MASK 0x00000001
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_SID_CORE_CLOCK_ENABLE_SID_SHIFT 0
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_SID_CORE_CLOCK_ENABLE_SID_DEFAULT 0x00000001
+
+/***************************************************************************
+ *HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS :: SID_CORE_CLOCK_ENABLE_SID_STATUS [00:00] */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS_SID_CORE_CLOCK_ENABLE_SID_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS_SID_CORE_CLOCK_ENABLE_SID_STATUS_SHIFT 0
+
+/***************************************************************************
+ *HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5
+
+/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: HVD1_SCB_CLOCK_ENABLE_STATUS [04:04] */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD1_SCB_CLOCK_ENABLE_STATUS_SHIFT 4
+
+/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: HVD1_GISB_CLOCK_ENABLE_STATUS [03:03] */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD1_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD1_GISB_CLOCK_ENABLE_STATUS_SHIFT 3
+
+/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: HVD1_CPU_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD1_CPU_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD1_CPU_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: HVD1_CORE_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD1_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD1_CORE_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: HVD1_54_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD1_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_HVD1_54_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *HVD_SID1_TOP_INST_OBSERVE_CLOCK - Hvd sid1 top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: HVD_SID1_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: HVD_SID1_TOP_INST_OBSERVE_CLOCK :: HVD1_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK_HVD1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK_HVD1_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK_HVD1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HVD_SID1_TOP_INST_OBSERVE_CLOCK :: HVD1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK_HVD1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK_HVD1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK_HVD1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HVD_SID1_TOP_INST_OBSERVE_CLOCK :: HVD1_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK_HVD1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK_HVD1_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_HVD_SID1_TOP_INST_OBSERVE_CLOCK_HVD1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
+ ***************************************************************************/
+/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:06] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK             0xffffffc0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT            6
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO2_REFERENCE_CLOCK [05:04] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_MASK 0x00000030
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_DEFAULT 0x00000001
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [03:02] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x0000000c
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0x00000001
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [01:00] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000003
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0x00000001
+
+/***************************************************************************
+ *ITU656_0_MUX_SELECT - Mux selects for itu656_0 clocks
+ ***************************************************************************/
+/* CLKGEN :: ITU656_0_MUX_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_reserved0_MASK             0xfffffff8
+#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_reserved0_SHIFT            3
+
+/* CLKGEN :: ITU656_0_MUX_SELECT :: VEC_ITU656_0_CLOCK [02:01] */
+#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_MASK    0x00000006
+#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_SHIFT   1
+#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: ITU656_0_MUX_SELECT :: ENABLE_INVERT_VEC_ITU656_0_CLOCK [00:00] */
+#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ITU656_1_MUX_SELECT - Mux selects for itu656_1 clocks
+ ***************************************************************************/
+/* CLKGEN :: ITU656_1_MUX_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_ITU656_1_MUX_SELECT_reserved0_MASK             0xfffffff8
+#define BCHP_CLKGEN_ITU656_1_MUX_SELECT_reserved0_SHIFT            3
+
+/* CLKGEN :: ITU656_1_MUX_SELECT :: VEC_ITU656_1_CLOCK [02:01] */
+#define BCHP_CLKGEN_ITU656_1_MUX_SELECT_VEC_ITU656_1_CLOCK_MASK    0x00000006
+#define BCHP_CLKGEN_ITU656_1_MUX_SELECT_VEC_ITU656_1_CLOCK_SHIFT   1
+#define BCHP_CLKGEN_ITU656_1_MUX_SELECT_VEC_ITU656_1_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: ITU656_1_MUX_SELECT :: ENABLE_INVERT_VEC_ITU656_1_CLOCK [00:00] */
+#define BCHP_CLKGEN_ITU656_1_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_1_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_ITU656_1_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_1_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_ITU656_1_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_1_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_32_0_INST_CLOCK_ENABLE - Memsys 32 0 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffff8
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_reserved0_SHIFT  3
+
+/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: MEMSYS0_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS0_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS0_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: MEMSYS0_GISB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS0_GISB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS0_GISB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: MEMSYS0_54_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS0_54_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS0_54_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_MEMSYS0_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS :: MEMSYS0_SCB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS :: MEMSYS0_GISB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS :: MEMSYS0_54_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_54_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *MEMSYS_32_0_INST_OBSERVE_CLOCK - Memsys 32 0 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: MEMSYS0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: MEMSYS0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: MEMSYS0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_MEMSYS0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_32_0_INST_STATUS - Memsys 32 0 inst status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_0_INST_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS_reserved0_SHIFT        1
+
+/* CLKGEN :: MEMSYS_32_0_INST_STATUS :: MEMSYS0_PLL_LOCKED_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS_MEMSYS0_PLL_LOCKED_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_0_INST_STATUS_MEMSYS0_PLL_LOCKED_STATUS_SHIFT 0
+
+/***************************************************************************
+ *MEMSYS_32_1_INST_CLOCK_ENABLE - Memsys 32 1 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffff8
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_reserved0_SHIFT  3
+
+/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE :: MEMSYS1_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_MEMSYS1_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_MEMSYS1_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_MEMSYS1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE :: MEMSYS1_GISB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_MEMSYS1_GISB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_MEMSYS1_GISB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_MEMSYS1_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE :: MEMSYS1_54_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_MEMSYS1_54_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_MEMSYS1_54_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_MEMSYS1_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS :: MEMSYS1_SCB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS :: MEMSYS1_GISB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS :: MEMSYS1_54_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_54_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *MEMSYS_32_1_INST_OBSERVE_CLOCK - Memsys 32 1 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: MEMSYS1_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: MEMSYS1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: MEMSYS1_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_MEMSYS1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_MEMSYS1_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_MEMSYS1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_32_1_INST_STATUS - Memsys 32 1 inst status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_1_INST_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_STATUS_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_STATUS_reserved0_SHIFT        1
+
+/* CLKGEN :: MEMSYS_32_1_INST_STATUS :: MEMSYS1_PLL_LOCKED_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_STATUS_MEMSYS1_PLL_LOCKED_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_1_INST_STATUS_MEMSYS1_PLL_LOCKED_STATUS_SHIFT 0
+
+/***************************************************************************
+ *MEMSYS_32_2_INST_CLOCK_ENABLE - Memsys 32 2 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_2_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffff8
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_CLOCK_ENABLE_reserved0_SHIFT  3
+
+/* CLKGEN :: MEMSYS_32_2_INST_CLOCK_ENABLE :: MEMSYS2_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_CLOCK_ENABLE_MEMSYS2_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_CLOCK_ENABLE_MEMSYS2_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_CLOCK_ENABLE_MEMSYS2_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: MEMSYS_32_2_INST_CLOCK_ENABLE :: MEMSYS2_GISB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_CLOCK_ENABLE_MEMSYS2_GISB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_CLOCK_ENABLE_MEMSYS2_GISB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_CLOCK_ENABLE_MEMSYS2_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: MEMSYS_32_2_INST_CLOCK_ENABLE :: MEMSYS2_54_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_CLOCK_ENABLE_MEMSYS2_54_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_CLOCK_ENABLE_MEMSYS2_54_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_CLOCK_ENABLE_MEMSYS2_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *MEMSYS_32_2_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_2_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: MEMSYS_32_2_INST_CLOCK_ENABLE_STATUS :: MEMSYS2_SCB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_CLOCK_ENABLE_STATUS_MEMSYS2_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_CLOCK_ENABLE_STATUS_MEMSYS2_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: MEMSYS_32_2_INST_CLOCK_ENABLE_STATUS :: MEMSYS2_GISB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_CLOCK_ENABLE_STATUS_MEMSYS2_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_CLOCK_ENABLE_STATUS_MEMSYS2_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: MEMSYS_32_2_INST_CLOCK_ENABLE_STATUS :: MEMSYS2_54_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_CLOCK_ENABLE_STATUS_MEMSYS2_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_CLOCK_ENABLE_STATUS_MEMSYS2_54_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *MEMSYS_32_2_INST_OBSERVE_CLOCK - Memsys 32 2 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_2_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: MEMSYS_32_2_INST_OBSERVE_CLOCK :: MEMSYS2_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_OBSERVE_CLOCK_MEMSYS2_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_OBSERVE_CLOCK_MEMSYS2_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_OBSERVE_CLOCK_MEMSYS2_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_32_2_INST_OBSERVE_CLOCK :: MEMSYS2_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_OBSERVE_CLOCK_MEMSYS2_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_OBSERVE_CLOCK_MEMSYS2_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_OBSERVE_CLOCK_MEMSYS2_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_32_2_INST_OBSERVE_CLOCK :: MEMSYS2_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_OBSERVE_CLOCK_MEMSYS2_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_OBSERVE_CLOCK_MEMSYS2_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_OBSERVE_CLOCK_MEMSYS2_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_32_2_INST_STATUS - Memsys 32 2 inst status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_2_INST_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_STATUS_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_STATUS_reserved0_SHIFT        1
+
+/* CLKGEN :: MEMSYS_32_2_INST_STATUS :: MEMSYS2_PLL_LOCKED_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_STATUS_MEMSYS2_PLL_LOCKED_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_2_INST_STATUS_MEMSYS2_PLL_LOCKED_STATUS_SHIFT 0
+
+/***************************************************************************
+ *MOCAMAC_TOP_INST_CLOCK_ENABLE - Mocamac top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffff8
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  3
+
+/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCAMAC_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCAMAC_GISB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_GISB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_GISB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCAMAC_54_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_54_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_54_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAMAC_SCB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAMAC_GISB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAMAC_54_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_54_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *MOCAMAC_TOP_INST_OBSERVE_CLOCK - Mocamac top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCAMAC_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCAMAC_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MOCAPHY_TOP_INST_CLOCK_ENABLE - Mocaphy top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  2
+
+/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE :: MOCAPHY_GISB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_GISB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_GISB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE :: MOCAPHY_54_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_54_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_54_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
+
+/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAPHY_GISB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAPHY_54_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_54_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *MOCAPHY_TOP_INST_OBSERVE_CLOCK - Mocaphy top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCAPHY_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCAPHY_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLK27_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_MASK           0xfffffe00
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_SHIFT          9
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_MASK  0x00000100
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_MASK  0x000000fe
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK  0x00000001
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLOCK_DISABLE - Disable PAD's clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK               0xfffffff0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT              4
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_VCXO27_CLOCK [03:03] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_SC_CLOCK [02:02] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_MASK        0xfffffff0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_SHIFT       4
+
+/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_VCXO27_CLOCK_STATUS [03:03] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_STATUS_SHIFT 3
+
+/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_SC_CLOCK_STATUS [02:02] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_SC_CLOCK_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_SC_CLOCK_STATUS_SHIFT 2
+
+/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CLK27_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK27_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK27_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PAD_CODEC_MCLK_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_MASK      0xfffffe00
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_SHIFT     9
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_MUX_SELECT - Mux selects for Pad clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:05] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK                  0xffffffe0
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT                 5
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_VCXO27_CLOCK [04:02] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_MASK    0x0000001c
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_SHIFT   2
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_SC_CLOCK [01:01] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_MASK        0x00000002
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_SHIFT       1
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_DEFAULT     0x00000000
+
+/* CLKGEN :: PAD_MUX_SELECT :: ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_VCXO27_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_MASK          0xfffffe00
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_SHIFT         9
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCIE_X1_TOP_INST_CLOCK_DISABLE - Disable PCIE_X1_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_DISABLE :: DISABLE_PCIE_ALWAYSON_CLOCK [00:00] */
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_ALWAYSON_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_ALWAYSON_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_ALWAYSON_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_PCIE_ALWAYSON_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_PCIE_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_PCIE_ALWAYSON_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PCIE_X1_TOP_INST_CLOCK_ENABLE - Pcie x1 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffff8
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  3
+
+/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE :: PCIE_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE :: PCIE_GISB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_GISB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_GISB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE :: PCIE_54_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_54_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_54_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_PCIE_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_SCB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_GISB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_54_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_54_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PCIE_X1_TOP_INST_OBSERVE_CLOCK - Pcie x1 top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: PCIE_X1_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: PCIE_X1_TOP_INST_OBSERVE_CLOCK :: PCIE_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PCIE_X1_TOP_INST_OBSERVE_CLOCK :: PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PCIE_X1_TOP_INST_OBSERVE_CLOCK :: PCIE_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PCIE_X1_TOP_INST_OBSERVE_CLOCK_PCIE_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET_STATUS - PLL_AUDIO0 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET_STATUS - PLL_AUDIO1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AUDIO2_PLL_RESET_STATUS - PLL_AUDIO2 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO2_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO2_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO2_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_CPU_GLITCHLESS_SWITCH_REQUEST - PLL_CPU Glitchless Clock Switching
+ ***************************************************************************/
+/* CLKGEN :: PLL_CPU_GLITCHLESS_SWITCH_REQUEST :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_reserved0_SHIFT 9
+
+/* CLKGEN :: PLL_CPU_GLITCHLESS_SWITCH_REQUEST :: TRANSACTION_WAIT [08:01] */
+#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_DEFAULT 0x0000001f
+
+/* CLKGEN :: PLL_CPU_GLITCHLESS_SWITCH_REQUEST :: PLL_BYPASS_REQUEST [00:00] */
+#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_SHIFT 0
+#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_CPU_GLITCHLESS_SWITCH_STATUS - PLL_CPU Glitchless Switching
+ ***************************************************************************/
+/* CLKGEN :: PLL_CPU_GLITCHLESS_SWITCH_STATUS :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_STATUS_reserved0_SHIFT 4
+
+/* CLKGEN :: PLL_CPU_GLITCHLESS_SWITCH_STATUS :: PLL_BYPASS_STATUS [03:00] */
+#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_MASK 0x0000000f
+#define BCHP_CLKGEN_PLL_CPU_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_CPU_PLL_RESET_STATUS - PLL_CPU Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_CPU_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_CPU_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_CPU_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_CPU_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_CPU_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_CPU_RDB_MACRO_CTRL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_reserved0_MASK          0xfffffff0
+#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_reserved0_SHIFT         4
+
+/* CLKGEN :: PLL_CPU_RDB_MACRO_CTRL :: PLL_CPU_OPTIONS_DISABLE_RDB_MACRO [03:03] */
+#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_PLL_CPU_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
+#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_PLL_CPU_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
+#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_PLL_CPU_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_CPU_RDB_MACRO_CTRL :: OPTIONS [02:00] */
+#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_OPTIONS_MASK            0x00000007
+#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_OPTIONS_SHIFT           0
+#define BCHP_CLKGEN_PLL_CPU_RDB_MACRO_CTRL_OPTIONS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_HVD_PLL_RESET_STATUS - PLL_HVD Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_HVD_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_HVD_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_HVD_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_HVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_HVD_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_HVD_RDB_MACRO_CTRL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_reserved0_MASK          0xfffffff0
+#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_reserved0_SHIFT         4
+
+/* CLKGEN :: PLL_HVD_RDB_MACRO_CTRL :: PLL_HVD_OPTIONS_DISABLE_RDB_MACRO [03:03] */
+#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_PLL_HVD_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
+#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_PLL_HVD_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
+#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_PLL_HVD_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_HVD_RDB_MACRO_CTRL :: OPTIONS [02:00] */
+#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_OPTIONS_MASK            0x00000007
+#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_OPTIONS_SHIFT           0
+#define BCHP_CLKGEN_PLL_HVD_RDB_MACRO_CTRL_OPTIONS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_LC_PLL_RESET_STATUS - PLL_LC Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_LC_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_LC_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_LC_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_RESET_STATUS - PLL_MOCA Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_MOCA_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_reserved0_MASK         0xfffffff8
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_reserved0_SHIFT        3
+
+/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO [02:02] */
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000004
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_SHIFT 2
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: OPTIONS [01:00] */
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_MASK           0x00000003
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_SHIFT          0
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PLL_NETWORK_PLL_RESET_STATUS - PLL_NETWORK Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_NETWORK_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_reserved0_SHIFT   2
+
+/* CLKGEN :: PLL_NETWORK_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_NETWORK_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *BSPI_CLOCK_SELECT - spi clock control
+ ***************************************************************************/
+/* CLKGEN :: BSPI_CLOCK_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_MASK               0xfffffff8
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_SHIFT              3
+
+/* CLKGEN :: BSPI_CLOCK_SELECT :: SPI_CLOCK_FREQ_SEL [02:01] */
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_MASK      0x00000006
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_SHIFT     1
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_DEFAULT   0x00000000
+
+/* CLKGEN :: BSPI_CLOCK_SELECT :: SPI_CLOCK_OVERRIDE_STRAP [00:00] */
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_MASK 0x00000001
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_SHIFT 0
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_RESET_STATUS - PLL_RAAGA Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_SHIFT     2
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_RAAGA_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_MASK        0xfffffff0
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_SHIFT       4
+
+/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO [03:03] */
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: OPTIONS [02:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_MASK          0x00000007
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_SHIFT         0
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_SC0_PLL_RESET_STATUS - PLL_SC0 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SC0_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: reserved0 [31:05] */
+#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_reserved0_SHIFT         5
+
+/* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: PLL_SC0_OPTIONS_DISABLE_RDB_MACRO [04:04] */
+#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_SHIFT 4
+#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: OPTIONS [03:00] */
+#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_MASK            0x0000000f
+#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_SHIFT           0
+#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_SC1_PLL_RESET_STATUS - PLL_SC1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SC1_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: reserved0 [31:05] */
+#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_reserved0_SHIFT         5
+
+/* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: PLL_SC1_OPTIONS_DISABLE_RDB_MACRO [04:04] */
+#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_SHIFT 4
+#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: OPTIONS [03:00] */
+#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_MASK            0x0000000f
+#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_SHIFT           0
+#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_VCXO0_PLL_RESET_STATUS - PLL_VCXO0 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_reserved0_SHIFT     2
+
+/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_VCXO1_PLL_RESET_STATUS - PLL_VCXO1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_reserved0_SHIFT     2
+
+/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_VCXO2_PLL_RESET_STATUS - PLL_VCXO2 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_reserved0_SHIFT     2
+
+/* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PM_CLOCK_Async_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_Async_ALIVE_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_reserved0_SHIFT       1
+
+/* CLKGEN :: PM_CLOCK_Async_ALIVE_SEL :: CLOCK_Async_CG_XPT [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_MASK 0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_SHIFT 0
+#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:06] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xffffffc0
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               6
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys2_PLL [05:05] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys2_PLL_MASK              0x00000020
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys2_PLL_SHIFT             5
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys2_PLL_DEFAULT           0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys1_PLL [04:04] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys1_PLL_MASK              0x00000010
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys1_PLL_SHIFT             4
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys1_PLL_DEFAULT           0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys0_PLL [03:03] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_MASK              0x00000008
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_SHIFT             3
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_DEFAULT           0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_XPT [02:02] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_MASK                  0x00000004
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_SHIFT                 2
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_DEFAULT               0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [01:01] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK                 0x00000002
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT                1
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT              0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_CPU [00:00] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_CPU_MASK                  0x00000001
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_CPU_SHIFT                 0
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_CPU_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PROD_OTP_INST_CLOCK_DISABLE - Disable PROD_OTP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_reserved0_SHIFT    2
+
+/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE :: DISABLE_POTP_JTAGOTP_CLOCK [01:01] */
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_JTAGOTP_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_JTAGOTP_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_JTAGOTP_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE :: DISABLE_POTP_ALWAYSON_CLOCK [00:00] */
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_ALWAYSON_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_ALWAYSON_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_ALWAYSON_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PROD_OTP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
+
+/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE_STATUS :: DISABLE_POTP_JTAGOTP_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_JTAGOTP_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_JTAGOTP_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE_STATUS :: DISABLE_POTP_ALWAYSON_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_ALWAYSON_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PROD_OTP_INST_CLOCK_ENABLE - Prod otp inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_reserved0_SHIFT     2
+
+/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE :: POTP_GISB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_GISB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_GISB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE :: POTP_54_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_54_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_54_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PROD_OTP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
+
+/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE_STATUS :: POTP_GISB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE_STATUS :: POTP_54_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_54_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE - Raaga dsp top 0 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_reserved0_SHIFT 5
+
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_SCB_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_SCB_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_SCB_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_GISB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_GISB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_GISB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_DSP_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_DSP_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_DSP_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_DSP_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_54_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_54_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_54_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5
+
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_SCB_CLOCK_ENABLE_STATUS [04:04] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_SCB_CLOCK_ENABLE_STATUS_SHIFT 4
+
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_GISB_CLOCK_ENABLE_STATUS [03:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_GISB_CLOCK_ENABLE_STATUS_SHIFT 3
+
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_DSP_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_DSP_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_DSP_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_54_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_54_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK - Raaga dsp top 0 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK :: RAAGA0_ENABLE_OBSERVE_CLOCK [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_OBSERVE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK :: RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE - Raaga dsp top 1 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_reserved0_SHIFT 5
+
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_SCB_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_SCB_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_SCB_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_GISB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_GISB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_GISB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_DSP_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_DSP_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_DSP_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_DSP_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_54_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_54_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_54_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5
+
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_SCB_CLOCK_ENABLE_STATUS [04:04] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_SCB_CLOCK_ENABLE_STATUS_SHIFT 4
+
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_GISB_CLOCK_ENABLE_STATUS [03:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_GISB_CLOCK_ENABLE_STATUS_SHIFT 3
+
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_DSP_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_DSP_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_DSP_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_54_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_54_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK - Raaga dsp top 1 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK :: RAAGA1_ENABLE_OBSERVE_CLOCK [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_OBSERVE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK :: RAAGA1_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RFM_TOP_INST_CLOCK_ENABLE - Rfm top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffff8
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      3
+
+/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: RFM_GISB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_GISB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_GISB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: RFM_54_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_54_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_54_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: RFM_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RFM_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: RFM_GISB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_GISB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: RFM_54_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_54_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: RFM_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *RFM_TOP_INST_OBSERVE_CLOCK - Rfm top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: RFM_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: RFM_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: RFM_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_INST_CLOCK_DISABLE - Disable SATA3_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_reserved0_MASK    0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT   1
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE :: DISABLE_SATA3_AT_SPEED_SCAN_CLOCK [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *SATA3_TOP_INST_CLOCK_ENABLE - Sata3 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_MASK     0xfffffff8
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT    3
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_GISB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_GISB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_GISB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_54_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_54_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_54_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SATA3_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: SATA3_SCB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: SATA3_GISB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: SATA3_54_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_54_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *SATA3_TOP_INST_CLOCK_SELECT - Sata3 top inst clock select
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_MASK     0xfffffff8
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_SHIFT    3
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: SATA3_REF_CLOCK_SELECT [02:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_MASK 0x00000007
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_INST_OBSERVE_CLOCK - Sata3 top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_MASK    0xffffffc0
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT   6
+
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SHVD0_TOP_INST_CLOCK_ENABLE - Shvd0 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SHVD0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_reserved0_MASK     0xffffffe0
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT    5
+
+/* CLKGEN :: SHVD0_TOP_INST_CLOCK_ENABLE :: SHVD0_SCB_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_SHVD0_SCB_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_SHVD0_SCB_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_SHVD0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SHVD0_TOP_INST_CLOCK_ENABLE :: SHVD0_GISB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_SHVD0_GISB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_SHVD0_GISB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_SHVD0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SHVD0_TOP_INST_CLOCK_ENABLE :: SHVD0_CPU_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_SHVD0_CPU_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_SHVD0_CPU_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_SHVD0_CPU_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SHVD0_TOP_INST_CLOCK_ENABLE :: SHVD0_CORE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_SHVD0_CORE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_SHVD0_CORE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_SHVD0_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SHVD0_TOP_INST_CLOCK_ENABLE :: SHVD0_54_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_SHVD0_54_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_SHVD0_54_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_SHVD0_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SHVD0_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: SHVD0_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5
+
+/* CLKGEN :: SHVD0_TOP_INST_CLOCK_ENABLE_STATUS :: SHVD0_SCB_CLOCK_ENABLE_STATUS [04:04] */
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_STATUS_SHVD0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_STATUS_SHVD0_SCB_CLOCK_ENABLE_STATUS_SHIFT 4
+
+/* CLKGEN :: SHVD0_TOP_INST_CLOCK_ENABLE_STATUS :: SHVD0_GISB_CLOCK_ENABLE_STATUS [03:03] */
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_STATUS_SHVD0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_STATUS_SHVD0_GISB_CLOCK_ENABLE_STATUS_SHIFT 3
+
+/* CLKGEN :: SHVD0_TOP_INST_CLOCK_ENABLE_STATUS :: SHVD0_CPU_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_STATUS_SHVD0_CPU_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_STATUS_SHVD0_CPU_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: SHVD0_TOP_INST_CLOCK_ENABLE_STATUS :: SHVD0_CORE_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_STATUS_SHVD0_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_STATUS_SHVD0_CORE_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: SHVD0_TOP_INST_CLOCK_ENABLE_STATUS :: SHVD0_54_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_STATUS_SHVD0_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_SHVD0_TOP_INST_CLOCK_ENABLE_STATUS_SHVD0_54_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *SHVD0_TOP_INST_OBSERVE_CLOCK - Shvd0 top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SHVD0_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SHVD0_TOP_INST_OBSERVE_CLOCK_reserved0_MASK    0xffffffc0
+#define BCHP_CLKGEN_SHVD0_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT   6
+
+/* CLKGEN :: SHVD0_TOP_INST_OBSERVE_CLOCK :: SHVD0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SHVD0_TOP_INST_OBSERVE_CLOCK_SHVD0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SHVD0_TOP_INST_OBSERVE_CLOCK_SHVD0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SHVD0_TOP_INST_OBSERVE_CLOCK_SHVD0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SHVD0_TOP_INST_OBSERVE_CLOCK :: SHVD0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SHVD0_TOP_INST_OBSERVE_CLOCK_SHVD0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SHVD0_TOP_INST_OBSERVE_CLOCK_SHVD0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SHVD0_TOP_INST_OBSERVE_CLOCK_SHVD0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SHVD0_TOP_INST_OBSERVE_CLOCK :: SHVD0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SHVD0_TOP_INST_OBSERVE_CLOCK_SHVD0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SHVD0_TOP_INST_OBSERVE_CLOCK_SHVD0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SHVD0_TOP_INST_OBSERVE_CLOCK_SHVD0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
+ ***************************************************************************/
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT           2
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [01:01] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK            0x00000002
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT           1
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [00:00] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK            0x00000001
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT           0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *SPARE - Spares
+ ***************************************************************************/
+/* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK                     0xfffff000
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT                    12
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT                  0x00000000
+
+/* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK                    0x00000fff
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT                   0
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *SYS_AON_INST_OBSERVE_CLOCK - Sys aon inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_INST_CLOCK_DISABLE - Disable SYS_CTRL_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_SHIFT    6
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [03:03] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [02:02] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_AVSTOP_PVTMON_CLOCK [01:01] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_AVSTOP_PVTMON_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_AVSTOP_PVTMON_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_AVSTOP_PVTMON_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_AVSTOP_27_UART_CLOCK [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_AVSTOP_27_UART_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_AVSTOP_27_UART_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_AVSTOP_27_UART_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 6
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSCTRL_UPG_CLOCK_STATUS [05:05] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_SHIFT 5
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK_STATUS [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_STATUS_SHIFT 4
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SC1_CLOCK_STATUS [03:03] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_SHIFT 3
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SC0_CLOCK_STATUS [02:02] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_SHIFT 2
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_AVSTOP_PVTMON_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_AVSTOP_PVTMON_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_AVSTOP_PVTMON_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_AVSTOP_27_UART_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_AVSTOP_27_UART_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_AVSTOP_27_UART_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *SYS_CTRL_INST_OBSERVE_CLOCK - Sys ctrl inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: reserved0 [31:12] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_MASK     0xfffff000
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_SHIFT    12
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [11:11] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000800
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_DIVIDER_OBSERVE_CLOCK [10:10] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_CONTROL_OBSERVE_CLOCK [09:06] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_MASK 0x000003c0
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_SHIFT 6
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: AVS_TOP_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: AVS_TOP_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_AVS_TOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TESTPORT - Special Testport Controls
+ ***************************************************************************/
+/* CLKGEN :: TESTPORT :: reserved0 [31:04] */
+#define BCHP_CLKGEN_TESTPORT_reserved0_MASK                        0xfffffff0
+#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT                       4
+
+/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [03:00] */
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK           0x0000000f
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT          0
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE - Disable TRIPLE_GENET_TOP_RGMII_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: reserved0 [31:12] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_MASK 0xfffff000
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_SHIFT 12
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET2_SYSTEM_SLOW_CLOCK [11:11] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_SYSTEM_SLOW_CLOCK_MASK 0x00000800
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_SYSTEM_SLOW_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET2_SYSTEM_PM_CLOCK [10:10] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_SYSTEM_PM_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_SYSTEM_PM_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_SYSTEM_PM_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET2_SYSTEM_FAST_CLOCK [09:09] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_SYSTEM_FAST_CLOCK_MASK 0x00000200
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_SYSTEM_FAST_CLOCK_SHIFT 9
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_SYSTEM_FAST_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET2_ALWAYSON_CLOCK [08:08] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_ALWAYSON_CLOCK_MASK 0x00000100
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_ALWAYSON_CLOCK_SHIFT 8
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET2_ALWAYSON_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK [07:07] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_MASK 0x00000080
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_SHIFT 7
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_PM_CLOCK [06:06] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_MASK 0x00000040
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_SHIFT 6
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_FAST_CLOCK [05:05] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_ALWAYSON_CLOCK [04:04] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_ALWAYSON_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_ALWAYSON_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_ALWAYSON_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [03:03] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [02:02] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_FAST_CLOCK [01:01] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_ALWAYSON_CLOCK [00:00] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_ALWAYSON_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_ALWAYSON_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_ALWAYSON_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 12
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET2_SYSTEM_SLOW_CLOCK_STATUS [11:11] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET2_SYSTEM_SLOW_CLOCK_STATUS_MASK 0x00000800
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET2_SYSTEM_SLOW_CLOCK_STATUS_SHIFT 11
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET2_SYSTEM_PM_CLOCK_STATUS [10:10] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET2_SYSTEM_PM_CLOCK_STATUS_MASK 0x00000400
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET2_SYSTEM_PM_CLOCK_STATUS_SHIFT 10
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET2_SYSTEM_FAST_CLOCK_STATUS [09:09] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET2_SYSTEM_FAST_CLOCK_STATUS_MASK 0x00000200
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET2_SYSTEM_FAST_CLOCK_STATUS_SHIFT 9
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET2_ALWAYSON_CLOCK_STATUS [08:08] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET2_ALWAYSON_CLOCK_STATUS_MASK 0x00000100
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET2_ALWAYSON_CLOCK_STATUS_SHIFT 8
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK_STATUS [07:07] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_STATUS_MASK 0x00000080
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_STATUS_SHIFT 7
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_SYSTEM_PM_CLOCK_STATUS [06:06] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_PM_CLOCK_STATUS_MASK 0x00000040
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_PM_CLOCK_STATUS_SHIFT 6
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_SYSTEM_FAST_CLOCK_STATUS [05:05] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_FAST_CLOCK_STATUS_MASK 0x00000020
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_SYSTEM_FAST_CLOCK_STATUS_SHIFT 5
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET1_ALWAYSON_CLOCK_STATUS [04:04] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_ALWAYSON_CLOCK_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET1_ALWAYSON_CLOCK_STATUS_SHIFT 4
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS [03:03] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_STATUS_SHIFT 3
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS [02:02] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_PM_CLOCK_STATUS_SHIFT 2
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_SYSTEM_FAST_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS :: DISABLE_GENET0_ALWAYSON_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_DISABLE_STATUS_DISABLE_GENET0_ALWAYSON_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE - Triple genet top rgmii inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_SHIFT 2
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_54_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_54_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_54_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 - Triple genet top rgmii inst clock enable genet0
+ ***************************************************************************/
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: reserved0 [31:08] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_reserved0_MASK 0xffffff00
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_reserved0_SHIFT 8
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0 [07:07] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_MASK 0x00000080
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_SHIFT 7
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0 [06:06] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_MASK 0x00000040
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_SHIFT 6
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_SCB_CLOCK_ENABLE_GENET0 [05:05] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_SCB_CLOCK_ENABLE_GENET0_MASK 0x00000020
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_SCB_CLOCK_ENABLE_GENET0_SHIFT 5
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_SCB_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_L2INTR_CLOCK_ENABLE_GENET0 [04:04] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_L2INTR_CLOCK_ENABLE_GENET0_MASK 0x00000010
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_L2INTR_CLOCK_ENABLE_GENET0_SHIFT 4
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_L2INTR_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_HFB_CLOCK_ENABLE_GENET0 [03:03] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_HFB_CLOCK_ENABLE_GENET0_MASK 0x00000008
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_HFB_CLOCK_ENABLE_GENET0_SHIFT 3
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_HFB_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_GMII_CLOCK_ENABLE_GENET0 [02:02] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GMII_CLOCK_ENABLE_GENET0_MASK 0x00000004
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GMII_CLOCK_ENABLE_GENET0_SHIFT 2
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GMII_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_GISB_CLOCK_ENABLE_GENET0 [01:01] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GISB_CLOCK_ENABLE_GENET0_MASK 0x00000002
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GISB_CLOCK_ENABLE_GENET0_SHIFT 1
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_GISB_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0 :: GENET0_EEE_CLOCK_ENABLE_GENET0 [00:00] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_EEE_CLOCK_ENABLE_GENET0_MASK 0x00000001
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_EEE_CLOCK_ENABLE_GENET0_SHIFT 0
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GENET0_EEE_CLOCK_ENABLE_GENET0_DEFAULT 0x00000001
+
+/***************************************************************************
+ *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: reserved0 [31:08] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_reserved0_SHIFT 8
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_STATUS [07:07] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000080
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET0_STATUS_SHIFT 7
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_STATUS [06:06] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000040
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET0_STATUS_SHIFT 6
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_SCB_CLOCK_ENABLE_GENET0_STATUS [05:05] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_SCB_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000020
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_SCB_CLOCK_ENABLE_GENET0_STATUS_SHIFT 5
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_L2INTR_CLOCK_ENABLE_GENET0_STATUS [04:04] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_L2INTR_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_L2INTR_CLOCK_ENABLE_GENET0_STATUS_SHIFT 4
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_HFB_CLOCK_ENABLE_GENET0_STATUS [03:03] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_HFB_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_HFB_CLOCK_ENABLE_GENET0_STATUS_SHIFT 3
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_GMII_CLOCK_ENABLE_GENET0_STATUS [02:02] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_GMII_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_GMII_CLOCK_ENABLE_GENET0_STATUS_SHIFT 2
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_GISB_CLOCK_ENABLE_GENET0_STATUS [01:01] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_GISB_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_GISB_CLOCK_ENABLE_GENET0_STATUS_SHIFT 1
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS :: GENET0_EEE_CLOCK_ENABLE_GENET0_STATUS [00:00] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_EEE_CLOCK_ENABLE_GENET0_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_STATUS_GENET0_EEE_CLOCK_ENABLE_GENET0_STATUS_SHIFT 0
+
+/***************************************************************************
+ *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 - Triple genet top rgmii inst clock enable genet1
+ ***************************************************************************/
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: reserved0 [31:09] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_reserved0_SHIFT 9
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1 [08:08] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_MASK 0x00000100
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_SHIFT 8
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1 [07:07] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_MASK 0x00000080
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_SHIFT 7
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_SCB_CLOCK_ENABLE_GENET1 [06:06] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_SCB_CLOCK_ENABLE_GENET1_MASK 0x00000040
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_SCB_CLOCK_ENABLE_GENET1_SHIFT 6
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_SCB_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_L2INTR_CLOCK_ENABLE_GENET1 [05:05] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_L2INTR_CLOCK_ENABLE_GENET1_MASK 0x00000020
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_L2INTR_CLOCK_ENABLE_GENET1_SHIFT 5
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_L2INTR_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_HFB_CLOCK_ENABLE_GENET1 [04:04] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_HFB_CLOCK_ENABLE_GENET1_MASK 0x00000010
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_HFB_CLOCK_ENABLE_GENET1_SHIFT 4
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_HFB_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_GMII_CLOCK_ENABLE_GENET1 [03:03] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GMII_CLOCK_ENABLE_GENET1_MASK 0x00000008
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GMII_CLOCK_ENABLE_GENET1_SHIFT 3
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GMII_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_GISB_CLOCK_ENABLE_GENET1 [02:02] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GISB_CLOCK_ENABLE_GENET1_MASK 0x00000004
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GISB_CLOCK_ENABLE_GENET1_SHIFT 2
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_GISB_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_EEE_CLOCK_ENABLE_GENET1 [01:01] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_EEE_CLOCK_ENABLE_GENET1_MASK 0x00000002
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_EEE_CLOCK_ENABLE_GENET1_SHIFT 1
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_EEE_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1 :: GENET1_CLK_250_CLOCK_ENABLE_GENET1 [00:00] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_CLK_250_CLOCK_ENABLE_GENET1_MASK 0x00000001
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_CLK_250_CLOCK_ENABLE_GENET1_SHIFT 0
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GENET1_CLK_250_CLOCK_ENABLE_GENET1_DEFAULT 0x00000001
+
+/***************************************************************************
+ *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: reserved0 [31:09] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_reserved0_SHIFT 9
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_STATUS [08:08] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000100
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET1_STATUS_SHIFT 8
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_STATUS [07:07] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000080
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET1_STATUS_SHIFT 7
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_SCB_CLOCK_ENABLE_GENET1_STATUS [06:06] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_SCB_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000040
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_SCB_CLOCK_ENABLE_GENET1_STATUS_SHIFT 6
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_L2INTR_CLOCK_ENABLE_GENET1_STATUS [05:05] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_L2INTR_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000020
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_L2INTR_CLOCK_ENABLE_GENET1_STATUS_SHIFT 5
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_HFB_CLOCK_ENABLE_GENET1_STATUS [04:04] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_HFB_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_HFB_CLOCK_ENABLE_GENET1_STATUS_SHIFT 4
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_GMII_CLOCK_ENABLE_GENET1_STATUS [03:03] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_GMII_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_GMII_CLOCK_ENABLE_GENET1_STATUS_SHIFT 3
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_GISB_CLOCK_ENABLE_GENET1_STATUS [02:02] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_GISB_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_GISB_CLOCK_ENABLE_GENET1_STATUS_SHIFT 2
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_EEE_CLOCK_ENABLE_GENET1_STATUS [01:01] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_EEE_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_EEE_CLOCK_ENABLE_GENET1_STATUS_SHIFT 1
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS :: GENET1_CLK_250_CLOCK_ENABLE_GENET1_STATUS [00:00] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_CLK_250_CLOCK_ENABLE_GENET1_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_STATUS_GENET1_CLK_250_CLOCK_ENABLE_GENET1_STATUS_SHIFT 0
+
+/***************************************************************************
+ *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 - Triple genet top rgmii inst clock enable genet2
+ ***************************************************************************/
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 :: reserved0 [31:09] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_reserved0_SHIFT 9
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 :: GENET2_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET2 [08:08] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET2_MASK 0x00000100
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET2_SHIFT 8
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET2_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 :: GENET2_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET2 [07:07] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET2_MASK 0x00000080
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET2_SHIFT 7
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET2_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 :: GENET2_SCB_CLOCK_ENABLE_GENET2 [06:06] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_SCB_CLOCK_ENABLE_GENET2_MASK 0x00000040
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_SCB_CLOCK_ENABLE_GENET2_SHIFT 6
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_SCB_CLOCK_ENABLE_GENET2_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 :: GENET2_L2INTR_CLOCK_ENABLE_GENET2 [05:05] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_L2INTR_CLOCK_ENABLE_GENET2_MASK 0x00000020
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_L2INTR_CLOCK_ENABLE_GENET2_SHIFT 5
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_L2INTR_CLOCK_ENABLE_GENET2_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 :: GENET2_HFB_CLOCK_ENABLE_GENET2 [04:04] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_HFB_CLOCK_ENABLE_GENET2_MASK 0x00000010
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_HFB_CLOCK_ENABLE_GENET2_SHIFT 4
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_HFB_CLOCK_ENABLE_GENET2_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 :: GENET2_GMII_CLOCK_ENABLE_GENET2 [03:03] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_GMII_CLOCK_ENABLE_GENET2_MASK 0x00000008
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_GMII_CLOCK_ENABLE_GENET2_SHIFT 3
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_GMII_CLOCK_ENABLE_GENET2_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 :: GENET2_GISB_CLOCK_ENABLE_GENET2 [02:02] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_GISB_CLOCK_ENABLE_GENET2_MASK 0x00000004
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_GISB_CLOCK_ENABLE_GENET2_SHIFT 2
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_GISB_CLOCK_ENABLE_GENET2_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 :: GENET2_EEE_CLOCK_ENABLE_GENET2 [01:01] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_EEE_CLOCK_ENABLE_GENET2_MASK 0x00000002
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_EEE_CLOCK_ENABLE_GENET2_SHIFT 1
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_EEE_CLOCK_ENABLE_GENET2_DEFAULT 0x00000001
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2 :: GENET2_CLK_250_CLOCK_ENABLE_GENET2 [00:00] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_CLK_250_CLOCK_ENABLE_GENET2_MASK 0x00000001
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_CLK_250_CLOCK_ENABLE_GENET2_SHIFT 0
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_GENET2_CLK_250_CLOCK_ENABLE_GENET2_DEFAULT 0x00000001
+
+/***************************************************************************
+ *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: reserved0 [31:09] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_reserved0_SHIFT 9
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: GENET2_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET2_STATUS [08:08] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET2_STATUS_MASK 0x00000100
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_UNIMAC_SYS_TX_CLOCK_ENABLE_GENET2_STATUS_SHIFT 8
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: GENET2_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET2_STATUS [07:07] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET2_STATUS_MASK 0x00000080
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_UNIMAC_SYS_RX_CLOCK_ENABLE_GENET2_STATUS_SHIFT 7
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: GENET2_SCB_CLOCK_ENABLE_GENET2_STATUS [06:06] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_SCB_CLOCK_ENABLE_GENET2_STATUS_MASK 0x00000040
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_SCB_CLOCK_ENABLE_GENET2_STATUS_SHIFT 6
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: GENET2_L2INTR_CLOCK_ENABLE_GENET2_STATUS [05:05] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_L2INTR_CLOCK_ENABLE_GENET2_STATUS_MASK 0x00000020
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_L2INTR_CLOCK_ENABLE_GENET2_STATUS_SHIFT 5
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: GENET2_HFB_CLOCK_ENABLE_GENET2_STATUS [04:04] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_HFB_CLOCK_ENABLE_GENET2_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_HFB_CLOCK_ENABLE_GENET2_STATUS_SHIFT 4
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: GENET2_GMII_CLOCK_ENABLE_GENET2_STATUS [03:03] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_GMII_CLOCK_ENABLE_GENET2_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_GMII_CLOCK_ENABLE_GENET2_STATUS_SHIFT 3
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: GENET2_GISB_CLOCK_ENABLE_GENET2_STATUS [02:02] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_GISB_CLOCK_ENABLE_GENET2_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_GISB_CLOCK_ENABLE_GENET2_STATUS_SHIFT 2
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: GENET2_EEE_CLOCK_ENABLE_GENET2_STATUS [01:01] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_EEE_CLOCK_ENABLE_GENET2_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_EEE_CLOCK_ENABLE_GENET2_STATUS_SHIFT 1
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS :: GENET2_CLK_250_CLOCK_ENABLE_GENET2_STATUS [00:00] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_CLK_250_CLOCK_ENABLE_GENET2_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET2_STATUS_GENET2_CLK_250_CLOCK_ENABLE_GENET2_STATUS_SHIFT 0
+
+/***************************************************************************
+ *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS :: GENET_SCB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET_SCB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS :: GENET_54_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_ENABLE_STATUS_GENET_54_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0 - Triple genet top rgmii inst clock select genet0
+ ***************************************************************************/
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0 :: reserved0 [31:02] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_reserved0_SHIFT 2
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0 :: GENET0_GMII_CLOCK_SELECT_GENET0 [01:01] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_GMII_CLOCK_SELECT_GENET0_MASK 0x00000002
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_GMII_CLOCK_SELECT_GENET0_SHIFT 1
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_GMII_CLOCK_SELECT_GENET0_DEFAULT 0x00000000
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0 :: GENET0_CLOCK_SELECT_GENET0 [00:00] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_CLOCK_SELECT_GENET0_MASK 0x00000001
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_CLOCK_SELECT_GENET0_SHIFT 0
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GENET0_CLOCK_SELECT_GENET0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1 - Triple genet top rgmii inst clock select genet1
+ ***************************************************************************/
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1 :: reserved0 [31:02] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_reserved0_SHIFT 2
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1 :: GENET1_GMII_CLOCK_SELECT_GENET1 [01:01] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_GMII_CLOCK_SELECT_GENET1_MASK 0x00000002
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_GMII_CLOCK_SELECT_GENET1_SHIFT 1
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_GMII_CLOCK_SELECT_GENET1_DEFAULT 0x00000000
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1 :: GENET1_CLOCK_SELECT_GENET1 [00:00] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_CLOCK_SELECT_GENET1_MASK 0x00000001
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_CLOCK_SELECT_GENET1_SHIFT 0
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GENET1_CLOCK_SELECT_GENET1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2 - Triple genet top rgmii inst clock select genet2
+ ***************************************************************************/
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2 :: reserved0 [31:02] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2_reserved0_SHIFT 2
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2 :: GENET2_GMII_CLOCK_SELECT_GENET2 [01:01] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2_GENET2_GMII_CLOCK_SELECT_GENET2_MASK 0x00000002
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2_GENET2_GMII_CLOCK_SELECT_GENET2_SHIFT 1
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2_GENET2_GMII_CLOCK_SELECT_GENET2_DEFAULT 0x00000000
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2 :: GENET2_CLOCK_SELECT_GENET2 [00:00] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2_GENET2_CLOCK_SELECT_GENET2_MASK 0x00000001
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2_GENET2_CLOCK_SELECT_GENET2_SHIFT 0
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET2_GENET2_CLOCK_SELECT_GENET2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK - Triple genet top rgmii inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: GENET_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_TRIPLE_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB0_TOP_INST_CLOCK_DISABLE - Disable USB0_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    2
+
+/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE :: DISABLE_USB0_FREERUN_CLOCK [01:01] */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE :: DISABLE_USB0_54_MDIO_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB0_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
+
+/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB0_FREERUN_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_FREERUN_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_FREERUN_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB0_54_MDIO_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_54_MDIO_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_54_MDIO_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *USB0_TOP_INST_CLOCK_ENABLE - Usb0 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffff8
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     3
+
+/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: USB0_GISB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_GISB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_GISB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: USB0_54_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_54_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_54_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *USB0_TOP_INST_CLOCK_ENABLE_AHB - Usb0 top inst clock enable ahb
+ ***************************************************************************/
+/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_reserved0_SHIFT 1
+
+/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB :: USB0_108_CLOCK_ENABLE_AHB [00:00] */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_USB0_108_CLOCK_ENABLE_AHB_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_USB0_108_CLOCK_ENABLE_AHB_SHIFT 0
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_USB0_108_CLOCK_ENABLE_AHB_DEFAULT 0x00000001
+
+/***************************************************************************
+ *USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS :: USB0_108_CLOCK_ENABLE_AHB_STATUS [00:00] */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_USB0_108_CLOCK_ENABLE_AHB_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_USB0_108_CLOCK_ENABLE_AHB_STATUS_SHIFT 0
+
+/***************************************************************************
+ *USB0_TOP_INST_CLOCK_ENABLE_AXI - Usb0 top inst clock enable axi
+ ***************************************************************************/
+/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_reserved0_SHIFT 1
+
+/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI :: USB0_108_CLOCK_ENABLE_AXI [00:00] */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_USB0_108_CLOCK_ENABLE_AXI_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_USB0_108_CLOCK_ENABLE_AXI_SHIFT 0
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_USB0_108_CLOCK_ENABLE_AXI_DEFAULT 0x00000001
+
+/***************************************************************************
+ *USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS :: USB0_108_CLOCK_ENABLE_AXI_STATUS [00:00] */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_USB0_108_CLOCK_ENABLE_AXI_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_USB0_108_CLOCK_ENABLE_AXI_STATUS_SHIFT 0
+
+/***************************************************************************
+ *USB0_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: USB0_SCB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: USB0_GISB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: USB0_54_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_54_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *USB0_TOP_INST_OBSERVE_CLOCK - Usb0 top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB1_TOP_INST_CLOCK_DISABLE - Disable USB1_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB1_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    2
+
+/* CLKGEN :: USB1_TOP_INST_CLOCK_DISABLE :: DISABLE_USB1_FREERUN_CLOCK [01:01] */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_DISABLE_USB1_FREERUN_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_DISABLE_USB1_FREERUN_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_DISABLE_USB1_FREERUN_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB1_TOP_INST_CLOCK_DISABLE :: DISABLE_USB1_54_MDIO_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB1_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: USB1_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2
+
+/* CLKGEN :: USB1_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB1_FREERUN_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB1_FREERUN_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB1_FREERUN_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: USB1_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB1_54_MDIO_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB1_54_MDIO_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB1_54_MDIO_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *USB1_TOP_INST_CLOCK_ENABLE - Usb1 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffff8
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     3
+
+/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE :: USB1_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE :: USB1_GISB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_GISB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_GISB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE :: USB1_54_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_54_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_54_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_USB1_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *USB1_TOP_INST_CLOCK_ENABLE_AHB - Usb1 top inst clock enable ahb
+ ***************************************************************************/
+/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AHB :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_reserved0_SHIFT 1
+
+/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AHB :: USB1_108_CLOCK_ENABLE_AHB [00:00] */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_USB1_108_CLOCK_ENABLE_AHB_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_USB1_108_CLOCK_ENABLE_AHB_SHIFT 0
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_USB1_108_CLOCK_ENABLE_AHB_DEFAULT 0x00000001
+
+/***************************************************************************
+ *USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS :: USB1_108_CLOCK_ENABLE_AHB_STATUS [00:00] */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS_USB1_108_CLOCK_ENABLE_AHB_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AHB_STATUS_USB1_108_CLOCK_ENABLE_AHB_STATUS_SHIFT 0
+
+/***************************************************************************
+ *USB1_TOP_INST_CLOCK_ENABLE_AXI - Usb1 top inst clock enable axi
+ ***************************************************************************/
+/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AXI :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_reserved0_SHIFT 1
+
+/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AXI :: USB1_108_CLOCK_ENABLE_AXI [00:00] */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_USB1_108_CLOCK_ENABLE_AXI_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_USB1_108_CLOCK_ENABLE_AXI_SHIFT 0
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_USB1_108_CLOCK_ENABLE_AXI_DEFAULT 0x00000001
+
+/***************************************************************************
+ *USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS :: USB1_108_CLOCK_ENABLE_AXI_STATUS [00:00] */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS_USB1_108_CLOCK_ENABLE_AXI_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_AXI_STATUS_USB1_108_CLOCK_ENABLE_AXI_STATUS_SHIFT 0
+
+/***************************************************************************
+ *USB1_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3
+
+/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_STATUS :: USB1_SCB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_USB1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_USB1_SCB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_STATUS :: USB1_GISB_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_USB1_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_USB1_GISB_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: USB1_TOP_INST_CLOCK_ENABLE_STATUS :: USB1_54_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_USB1_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_TOP_INST_CLOCK_ENABLE_STATUS_USB1_54_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *USB1_TOP_INST_OBSERVE_CLOCK - Usb1 top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB1_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: USB1_TOP_INST_OBSERVE_CLOCK :: USB1_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB1_TOP_INST_OBSERVE_CLOCK :: USB1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB1_TOP_INST_OBSERVE_CLOCK :: USB1_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB1_TOP_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *V3D_TOP_INST_CLOCK_ENABLE - V3d top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffff0
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      4
+
+/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_GISB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_GISB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_GISB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_54_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_54_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_54_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *V3D_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4
+
+/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_SCB_CLOCK_ENABLE_STATUS [03:03] */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_SCB_CLOCK_ENABLE_STATUS_SHIFT 3
+
+/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_GISB_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_GISB_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_54_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_54_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_DISABLE - Disable VEC_AIO_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_MASK  0xffffffe0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 5
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_ITU656_0_CLOCK [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_AUDIO_DAC_DSM_DEM_DIV8_CLOCK [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_DIV8_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_DIV8_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_DIV8_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_AUDIO_DAC_DSM_DEM_DIV2_CLOCK [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_DIV2_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_DIV2_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_DIV2_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_AUDIO_DAC_DSM_DEM_CLOCK [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 5
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_VEC_ITU656_0_CLOCK_STATUS [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_0_CLOCK_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_0_CLOCK_STATUS_SHIFT 4
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_VEC_DACADC_CLOCK_STATUS [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_SHIFT 3
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_AUDIO_DAC_DSM_DEM_DIV8_CLOCK_STATUS [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AUDIO_DAC_DSM_DEM_DIV8_CLOCK_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AUDIO_DAC_DSM_DEM_DIV8_CLOCK_STATUS_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_AUDIO_DAC_DSM_DEM_DIV2_CLOCK_STATUS [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AUDIO_DAC_DSM_DEM_DIV2_CLOCK_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AUDIO_DAC_DSM_DEM_DIV2_CLOCK_STATUS_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_AUDIO_DAC_DSM_DEM_CLOCK_STATUS [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AUDIO_DAC_DSM_DEM_CLOCK_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AUDIO_DAC_DSM_DEM_CLOCK_STATUS_SHIFT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE - Vec aio top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_AIO_54_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_54_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_54_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO - Vec aio top inst clock enable aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE_108_CLOCK_ENABLE_AIO [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_STATUS [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_STATUS_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS :: AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_STATUS [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_STATUS_AIO_ALTERNATE_108_CLOCK_ENABLE_AIO_STATUS_SHIFT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: VEC_AIO_54_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_AIO_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_AIO_54_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC - Vec aio top inst clock enable vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: reserved0 [31:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_SHIFT 5
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_SCB_CLOCK_ENABLE_VEC [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_GISB_CLOCK_ENABLE_VEC [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_GISB_CLOCK_ENABLE_VEC_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_GISB_CLOCK_ENABLE_VEC_SHIFT 3
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_GISB_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_BVB_CLOCK_ENABLE_VEC [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_CLOCK_ENABLE_VEC_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_CLOCK_ENABLE_VEC_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_BVB_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_108_CLOCK_ENABLE_VEC [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: QDAC_GISB_CLOCK_ENABLE_VEC [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_GISB_CLOCK_ENABLE_VEC_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_GISB_CLOCK_ENABLE_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_GISB_CLOCK_ENABLE_VEC_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF - Vec aio top inst clock enable vec qdac intf
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF :: VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS :: VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_VEC_GISB_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_SHIFT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: reserved0 [31:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_reserved0_SHIFT 5
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_SCB_CLOCK_ENABLE_VEC_STATUS [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_SCB_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_SCB_CLOCK_ENABLE_VEC_STATUS_SHIFT 4
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_GISB_CLOCK_ENABLE_VEC_STATUS [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_GISB_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_GISB_CLOCK_ENABLE_VEC_STATUS_SHIFT 3
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_BVB_CLOCK_ENABLE_VEC_STATUS [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_BVB_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_BVB_CLOCK_ENABLE_VEC_STATUS_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: VEC_108_CLOCK_ENABLE_VEC_STATUS [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_108_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_VEC_108_CLOCK_ENABLE_VEC_STATUS_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS :: QDAC_GISB_CLOCK_ENABLE_VEC_STATUS [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_QDAC_GISB_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_STATUS_QDAC_GISB_CLOCK_ENABLE_VEC_STATUS_SHIFT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_OBSERVE_CLOCK - Vec aio top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:12] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_MASK  0xfffff000
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 12
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_ENABLE_OBSERVE_CLOCK [11:11] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_MASK 0x00000800
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_ENABLE_DIVIDER_OBSERVE_CLOCK [10:10] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_CONTROL_OBSERVE_CLOCK [09:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_CONTROL_OBSERVE_CLOCK_MASK 0x000003c0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_CONTROL_OBSERVE_CLOCK_SHIFT 6
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VICE2_0_INST_CLOCK_ENABLE - Vice2 0 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_reserved0_SHIFT      6
+
+/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_SCB_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_SCB_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_SCB_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_GISB_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_GISB_ALTERNATE_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_ALTERNATE_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_ALTERNATE_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_ALTERNATE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_CORE_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_CORE_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_CORE_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_54_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_54_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_54_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VICE2_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 6
+
+/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_SCB_CLOCK_ENABLE_STATUS [05:05] */
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000020
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_SCB_CLOCK_ENABLE_STATUS_SHIFT 5
+
+/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_GISB_CLOCK_ENABLE_STATUS [04:04] */
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_GISB_CLOCK_ENABLE_STATUS_SHIFT 4
+
+/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_GISB_ALTERNATE_CLOCK_ENABLE_STATUS [03:03] */
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_GISB_ALTERNATE_CLOCK_ENABLE_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_GISB_ALTERNATE_CLOCK_ENABLE_STATUS_SHIFT 3
+
+/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_CORE_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_CORE_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_54_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_54_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *VICE2_1_INST_CLOCK_ENABLE - Vice2 1 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_reserved0_SHIFT      6
+
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_SCB_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_SCB_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_SCB_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_GISB_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_GISB_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_GISB_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_GISB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_GISB_ALTERNATE_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_GISB_ALTERNATE_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_GISB_ALTERNATE_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_GISB_ALTERNATE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_CORE_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_CORE_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_CORE_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_CORE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_54_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_54_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_54_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_54_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VICE2_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
+ ***************************************************************************/
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 6
+
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_SCB_CLOCK_ENABLE_STATUS [05:05] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000020
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_SCB_CLOCK_ENABLE_STATUS_SHIFT 5
+
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_GISB_CLOCK_ENABLE_STATUS [04:04] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000010
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_GISB_CLOCK_ENABLE_STATUS_SHIFT 4
+
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_GISB_ALTERNATE_CLOCK_ENABLE_STATUS [03:03] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_GISB_ALTERNATE_CLOCK_ENABLE_STATUS_MASK 0x00000008
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_GISB_ALTERNATE_CLOCK_ENABLE_STATUS_SHIFT 3
+
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_CORE_CLOCK_ENABLE_STATUS [02:02] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000004
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_CORE_CLOCK_ENABLE_STATUS_SHIFT 2
+
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_54_CLOCK_ENABLE_STATUS [01:01] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_54_CLOCK_ENABLE_STATUS_SHIFT 1
+
+/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_108_CLOCK_ENABLE_STATUS [00:00] */
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_108_CLOCK_ENABLE_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DISABLE_AVS_TOP_DURING_S2_SECURE - Could be set at start up to guarantee that AVS_TOP is clock gated in S2
+ ***************************************************************************/
+/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2_SECURE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_reserved0_SHIFT 1
+
+/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2_SECURE :: DISABLE_AVS_TOP [00:00] */
+#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_DISABLE_AVS_TOP_MASK 0x00000001
+#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_DISABLE_AVS_TOP_SHIFT 0
+#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_DISABLE_AVS_TOP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DISABLE_AVS_TOP_DURING_S2 - disable AVS_TOP 54MHz clocks during S2
+ ***************************************************************************/
+/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_reserved0_SHIFT      1
+
+/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2 :: DISABLE_AVS_TOP [00:00] */
+#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_DISABLE_AVS_TOP_MASK 0x00000001
+#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_DISABLE_AVS_TOP_SHIFT 0
+#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_DISABLE_AVS_TOP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USBPHY_REF_CLOCK_BYPASS - bypass USBPHY reference clocks
+ ***************************************************************************/
+/* CLKGEN :: USBPHY_REF_CLOCK_BYPASS :: reserved0 [31:03] */
+#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_reserved0_MASK         0xfffffff8
+#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_reserved0_SHIFT        3
+
+/* CLKGEN :: USBPHY_REF_CLOCK_BYPASS :: BYP_USB1_USB20_60MHZ_REFCLK [02:02] */
+#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB1_USB20_60MHZ_REFCLK_MASK 0x00000004
+#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB1_USB20_60MHZ_REFCLK_SHIFT 2
+#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB1_USB20_60MHZ_REFCLK_DEFAULT 0x00000000
+
+/* CLKGEN :: USBPHY_REF_CLOCK_BYPASS :: BYP_USB0_USB20_60MHZ_REFCLK [01:01] */
+#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB0_USB20_60MHZ_REFCLK_MASK 0x00000002
+#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB0_USB20_60MHZ_REFCLK_SHIFT 1
+#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB0_USB20_60MHZ_REFCLK_DEFAULT 0x00000000
+
+/* CLKGEN :: USBPHY_REF_CLOCK_BYPASS :: BYP_USB0_USB30_50MHZ_REFCLK [00:00] */
+#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB0_USB30_50MHZ_REFCLK_MASK 0x00000001
+#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB0_USB30_50MHZ_REFCLK_SHIFT 0
+#define BCHP_CLKGEN_USBPHY_REF_CLOCK_BYPASS_BYP_USB0_USB30_50MHZ_REFCLK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EPHY_REF_CLOCK_BYPASS - bypass EPHY reference clocks
+ ***************************************************************************/
+/* CLKGEN :: EPHY_REF_CLOCK_BYPASS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS_reserved0_MASK           0xfffffffc
+#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS_reserved0_SHIFT          2
+
+/* CLKGEN :: EPHY_REF_CLOCK_BYPASS :: SEL_54MHZ_REFCLK [01:01] */
+#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS_SEL_54MHZ_REFCLK_MASK    0x00000002
+#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS_SEL_54MHZ_REFCLK_SHIFT   1
+#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS_SEL_54MHZ_REFCLK_DEFAULT 0x00000000
+
+/* CLKGEN :: EPHY_REF_CLOCK_BYPASS :: BYP_EN_EPHY_REFCLK [00:00] */
+#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS_BYP_EN_EPHY_REFCLK_MASK  0x00000001
+#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS_BYP_EN_EPHY_REFCLK_SHIFT 0
+#define BCHP_CLKGEN_EPHY_REF_CLOCK_BYPASS_BYP_EN_EPHY_REFCLK_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_CLKGEN_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7445a0/bchp_common.h b/include/linux/brcmstb/7445a0/bchp_common.h
new file mode 100644
index 0000000..fa3fc6d
--- /dev/null
+++ b/include/linux/brcmstb/7445a0/bchp_common.h
@@ -0,0 +1,3927 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Oct 17 03:11:12 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_COMMON_H__
+#define BCHP_COMMON_H__
+
+/**
+ * m = memory, c = core, r = register, f = field, d = data.
+ */
+#if !defined(GET_FIELD) && !defined(SET_FIELD)
+#define BRCM_MASK(c,r,f)    c##_##r##_##f##_MASK
+#define BRCM_SHIFT(c,r,f)   c##_##r##_##f##_SHIFT
+
+#define GET_FIELD(m,c,r,f) \
+((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)))
+
+#define SET_FIELD(m,c,r,f,d) \
+((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d)) << BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))))
+
+#define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d)
+#define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d)
+#define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d)
+
+#endif /* GET & SET */
+
+/***************************************************************************
+ *BCM7445_A0
+ ***************************************************************************/
+#define BCHP_PHYSICAL_OFFSET                               0xf0000000
+#define BCHP_REGISTER_START                                0x00000000 /* HEVD_OL_CPU_REGS_0 is first */
+#define BCHP_REGISTER_END                                  0x00fffda0 /* MOCA_HOSTMISC is last */
+#define BCHP_REGISTER_SIZE                                 0x003fff68 /* Number of registers */
+
+/****************************************************************************
+ * Core instance register start address.
+ ***************************************************************************/
+#define BCHP_HEVD_OL_CPU_REGS_0_REG_START                  0x00000000
+#define BCHP_HEVD_OL_CPU_REGS_0_REG_END                    0x00000108
+#define BCHP_HEVD_OL_CPU_DMA_0_REG_START                   0x00000400
+#define BCHP_HEVD_OL_CPU_DMA_0_REG_END                     0x00000440
+#define BCHP_HEVD_OL_CPU_DEBUG_0_REG_START                 0x00000800
+#define BCHP_HEVD_OL_CPU_DEBUG_0_REG_END                   0x00000ffc
+#define BCHP_HEVD_OL_SINT_0_REG_START                      0x00001000
+#define BCHP_HEVD_OL_SINT_0_REG_END                        0x00001028
+#define BCHP_HEVD_OL_LDST_0_REG_START                      0x00008000
+#define BCHP_HEVD_OL_LDST_0_REG_END                        0x0000fffc
+#define BCHP_REG_CABAC2BINS_0_REG_START                    0x00010b00
+#define BCHP_REG_CABAC2BINS_0_REG_END                      0x00010bfc
+#define BCHP_REG_CABAC2BINS2_0_REG_START                   0x00012400
+#define BCHP_REG_CABAC2BINS2_0_REG_END                     0x000127fc
+#define BCHP_HEVD_CABAC_0_REG_START                        0x00013000
+#define BCHP_HEVD_CABAC_0_REG_END                          0x000130bc
+#define BCHP_HEVD_OL_CTL_0_REG_START                       0x00014000
+#define BCHP_HEVD_OL_CTL_0_REG_END                         0x000151fc
+#define BCHP_DECODE_MAIN_0_REG_START                       0x00020100
+#define BCHP_DECODE_MAIN_0_REG_END                         0x000201fc
+#define BCHP_DECODE_MCOM_0_REG_START                       0x00020300
+#define BCHP_DECODE_MCOM_0_REG_END                         0x0002031c
+#define BCHP_DECODE_SPRE_0_REG_START                       0x00020320
+#define BCHP_DECODE_SPRE_0_REG_END                         0x0002033c
+#define BCHP_DECODE_WPRD_0_REG_START                       0x00020340
+#define BCHP_DECODE_WPRD_0_REG_END                         0x0002035c
+#define BCHP_DECODE_DQNT_0_REG_START                       0x00020400
+#define BCHP_DECODE_DQNT_0_REG_END                         0x0002045c
+#define BCHP_DECODE_DQNT_8X8_0_REG_START                   0x00020500
+#define BCHP_DECODE_DQNT_8X8_0_REG_END                     0x0002057c
+#define BCHP_DECODE_VP8_XFRM_0_REG_START                   0x00020600
+#define BCHP_DECODE_VP8_XFRM_0_REG_END                     0x0002060c
+#define BCHP_DECODE_VP6_DCP_0_REG_START                    0x00020620
+#define BCHP_DECODE_VP6_DCP_0_REG_END                      0x0002062c
+#define BCHP_DECODE_XFRM_0_REG_START                       0x00020700
+#define BCHP_DECODE_XFRM_0_REG_END                         0x0002071c
+#define BCHP_DECODE_DBLK_0_REG_START                       0x00020720
+#define BCHP_DECODE_DBLK_0_REG_END                         0x0002073c
+#define BCHP_DECODE_MB_0_REG_START                         0x00020740
+#define BCHP_DECODE_MB_0_REG_END                           0x0002075c
+#define BCHP_DECODE_SINT_0_REG_START                       0x00020c00
+#define BCHP_DECODE_SINT_0_REG_END                         0x00020dfc
+#define BCHP_DECODE_RVC_0_REG_START                        0x00020e00
+#define BCHP_DECODE_RVC_0_REG_END                          0x00020efc
+#define BCHP_DECODE_WPTBL_0_REG_START                      0x00023000
+#define BCHP_DECODE_WPTBL_0_REG_END                        0x000231fc
+#define BCHP_HEVD_BE_GLOBAL_0_REG_START                    0x00024000
+#define BCHP_HEVD_BE_GLOBAL_0_REG_END                      0x00024030
+#define BCHP_HEVD_IXFORM_0_REG_START                       0x00024100
+#define BCHP_HEVD_IXFORM_0_REG_END                         0x000241fc
+#define BCHP_HEVD_MCOMP_0_REG_START                        0x00024200
+#define BCHP_HEVD_MCOMP_0_REG_END                          0x000242fc
+#define BCHP_HEVD_SPRED_0_REG_START                        0x00024300
+#define BCHP_HEVD_SPRED_0_REG_END                          0x000243f0
+#define BCHP_HEVD_FILTER_0_REG_START                       0x00024400
+#define BCHP_HEVD_FILTER_0_REG_END                         0x000244fc
+#define BCHP_HEVD_OUTPUT_0_REG_START                       0x00024500
+#define BCHP_HEVD_OUTPUT_0_REG_END                         0x000245fc
+#define BCHP_HEVD_MARKER_0_REG_START                       0x00024f00
+#define BCHP_HEVD_MARKER_0_REG_END                         0x00024f7c
+#define BCHP_HEVD_FE_CTRL_0_REG_START                      0x00025000
+#define BCHP_HEVD_FE_CTRL_0_REG_END                        0x00025034
+#define BCHP_HEVD_STRM_IN_0_REG_START                      0x00025100
+#define BCHP_HEVD_STRM_IN_0_REG_END                        0x00025118
+#define BCHP_HEVD_CMDBUS_XMIT_0_REG_START                  0x00025200
+#define BCHP_HEVD_CMDBUS_XMIT_0_REG_END                    0x00025210
+#define BCHP_HEVD_VECGEN_0_REG_START                       0x00025400
+#define BCHP_HEVD_VECGEN_0_REG_END                         0x00025698
+#define BCHP_DCD_PIPE_CTL_0_REG_START                      0x00026000
+#define BCHP_DCD_PIPE_CTL_0_REG_END                        0x00026404
+#define BCHP_HEVD_PCACHE_0_REG_START                       0x00026800
+#define BCHP_HEVD_PCACHE_0_REG_END                         0x00026834
+#define BCHP_HEVD_PFRI_0_REG_START                         0x00026a00
+#define BCHP_HEVD_PFRI_0_REG_END                           0x00026b58
+#define BCHP_RVC_0_REG_START                               0x00026c00
+#define BCHP_RVC_0_REG_END                                 0x00026c20
+#define BCHP_ILS_REGS_0_REG_START                          0x00027000
+#define BCHP_ILS_REGS_0_REG_END                            0x000270fc
+#define BCHP_ILS_SCALE_ADDR_0_REG_START                    0x00027100
+#define BCHP_ILS_SCALE_ADDR_0_REG_END                      0x0002710c
+#define BCHP_ILS_SPSCALE_FILL_0_REG_START                  0x00027180
+#define BCHP_ILS_SPSCALE_FILL_0_REG_END                    0x00027184
+#define BCHP_ILS_MVSCALE_0_REG_START                       0x00027200
+#define BCHP_ILS_MVSCALE_0_REG_END                         0x0002738c
+#define BCHP_ILB_REGS_0_REG_START                          0x00027400
+#define BCHP_ILB_REGS_0_REG_END                            0x00027410
+#define BCHP_BLD_DECODE_MAIN_0_REG_START                   0x00028100
+#define BCHP_BLD_DECODE_MAIN_0_REG_END                     0x000281fc
+#define BCHP_BLD_DECODE_MCOM_0_REG_START                   0x00028300
+#define BCHP_BLD_DECODE_MCOM_0_REG_END                     0x0002831c
+#define BCHP_BLD_DECODE_SPRE_0_REG_START                   0x00028320
+#define BCHP_BLD_DECODE_SPRE_0_REG_END                     0x0002833c
+#define BCHP_BLD_DECODE_DQNT_0_REG_START                   0x00028400
+#define BCHP_BLD_DECODE_DQNT_0_REG_END                     0x0002845c
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_START               0x00028500
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_END                 0x0002857c
+#define BCHP_BLD_DECODE_XFRM_0_REG_START                   0x00028700
+#define BCHP_BLD_DECODE_XFRM_0_REG_END                     0x0002871c
+#define BCHP_BLD_DECODE_DBLK_0_REG_START                   0x00028720
+#define BCHP_BLD_DECODE_DBLK_0_REG_END                     0x0002873c
+#define BCHP_BLD_DECODE_MB_0_REG_START                     0x00028740
+#define BCHP_BLD_DECODE_MB_0_REG_END                       0x0002875c
+#define BCHP_BLD_DECODE_SINT_0_REG_START                   0x00028c00
+#define BCHP_BLD_DECODE_SINT_0_REG_END                     0x00028dfc
+#define BCHP_BLD_DECODE_RVC_0_REG_START                    0x00028e00
+#define BCHP_BLD_DECODE_RVC_0_REG_END                      0x00028efc
+#define BCHP_BLD_BL_CPU_REGS_0_REG_START                   0x0002c000
+#define BCHP_BLD_BL_CPU_REGS_0_REG_END                     0x0002c108
+#define BCHP_BLD_BL_CPU_DMA_0_REG_START                    0x0002c400
+#define BCHP_BLD_BL_CPU_DMA_0_REG_END                      0x0002c440
+#define BCHP_BLD_BL_CPU_DEBUG_0_REG_START                  0x0002c800
+#define BCHP_BLD_BL_CPU_DEBUG_0_REG_END                    0x0002cffc
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_START                0x0002d000
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_END                  0x0002d090
+#define BCHP_HEVD_IL_CPU_REGS_0_REG_START                  0x00030000
+#define BCHP_HEVD_IL_CPU_REGS_0_REG_END                    0x00030108
+#define BCHP_HEVD_IL_CPU_DMA_0_REG_START                   0x00030400
+#define BCHP_HEVD_IL_CPU_DMA_0_REG_END                     0x00030440
+#define BCHP_HEVD_IL_CPU_DEBUG_0_REG_START                 0x00030800
+#define BCHP_HEVD_IL_CPU_DEBUG_0_REG_END                   0x00030ffc
+#define BCHP_HEVD_IL_SLICE_DMA_0_REG_START                 0x00031000
+#define BCHP_HEVD_IL_SLICE_DMA_0_REG_END                   0x0003100c
+#define BCHP_HEVD_IL_LDST_0_REG_START                      0x00034000
+#define BCHP_HEVD_IL_LDST_0_REG_END                        0x00037ffc
+#define BCHP_SHVD_INTR2_0_REG_START                        0x00080000
+#define BCHP_SHVD_INTR2_0_REG_END                          0x0008002c
+#define BCHP_SHVD_RGR_0_REG_START                          0x00080400
+#define BCHP_SHVD_RGR_0_REG_END                            0x00080410
+#define BCHP_VICH_0_REG_START                              0x000a0000
+#define BCHP_VICH_0_REG_END                                0x000a008b
+#define BCHP_HEVD_OL_CPU_REGS_1_REG_START                  0x00100000
+#define BCHP_HEVD_OL_CPU_REGS_1_REG_END                    0x00100108
+#define BCHP_HEVD_OL_CPU_DMA_1_REG_START                   0x00100400
+#define BCHP_HEVD_OL_CPU_DMA_1_REG_END                     0x00100440
+#define BCHP_HEVD_OL_CPU_DEBUG_1_REG_START                 0x00100800
+#define BCHP_HEVD_OL_CPU_DEBUG_1_REG_END                   0x00100ffc
+#define BCHP_HEVD_OL_SINT_1_REG_START                      0x00101000
+#define BCHP_HEVD_OL_SINT_1_REG_END                        0x00101028
+#define BCHP_HEVD_OL_LDST_1_REG_START                      0x00108000
+#define BCHP_HEVD_OL_LDST_1_REG_END                        0x0010fffc
+#define BCHP_REG_CABAC2BINS_1_REG_START                    0x00110b00
+#define BCHP_REG_CABAC2BINS_1_REG_END                      0x00110bfc
+#define BCHP_REG_CABAC2BINS2_1_REG_START                   0x00112400
+#define BCHP_REG_CABAC2BINS2_1_REG_END                     0x001127fc
+#define BCHP_HEVD_CABAC_1_REG_START                        0x00113000
+#define BCHP_HEVD_CABAC_1_REG_END                          0x001130bc
+#define BCHP_HEVD_OL_CTL_1_REG_START                       0x00114000
+#define BCHP_HEVD_OL_CTL_1_REG_END                         0x001151fc
+#define BCHP_DECODE_MAIN_1_REG_START                       0x00120100
+#define BCHP_DECODE_MAIN_1_REG_END                         0x001201fc
+#define BCHP_DECODE_MCOM_1_REG_START                       0x00120300
+#define BCHP_DECODE_MCOM_1_REG_END                         0x0012031c
+#define BCHP_DECODE_SPRE_1_REG_START                       0x00120320
+#define BCHP_DECODE_SPRE_1_REG_END                         0x0012033c
+#define BCHP_DECODE_WPRD_1_REG_START                       0x00120340
+#define BCHP_DECODE_WPRD_1_REG_END                         0x0012035c
+#define BCHP_DECODE_DQNT_1_REG_START                       0x00120400
+#define BCHP_DECODE_DQNT_1_REG_END                         0x0012045c
+#define BCHP_DECODE_DQNT_8X8_1_REG_START                   0x00120500
+#define BCHP_DECODE_DQNT_8X8_1_REG_END                     0x0012057c
+#define BCHP_DECODE_VP8_XFRM_1_REG_START                   0x00120600
+#define BCHP_DECODE_VP8_XFRM_1_REG_END                     0x0012060c
+#define BCHP_DECODE_VP6_DCP_1_REG_START                    0x00120620
+#define BCHP_DECODE_VP6_DCP_1_REG_END                      0x0012062c
+#define BCHP_DECODE_XFRM_1_REG_START                       0x00120700
+#define BCHP_DECODE_XFRM_1_REG_END                         0x0012071c
+#define BCHP_DECODE_DBLK_1_REG_START                       0x00120720
+#define BCHP_DECODE_DBLK_1_REG_END                         0x0012073c
+#define BCHP_DECODE_MB_1_REG_START                         0x00120740
+#define BCHP_DECODE_MB_1_REG_END                           0x0012075c
+#define BCHP_DECODE_SINT_1_REG_START                       0x00120c00
+#define BCHP_DECODE_SINT_1_REG_END                         0x00120dfc
+#define BCHP_DECODE_RVC_1_REG_START                        0x00120e00
+#define BCHP_DECODE_RVC_1_REG_END                          0x00120efc
+#define BCHP_DECODE_WPTBL_1_REG_START                      0x00123000
+#define BCHP_DECODE_WPTBL_1_REG_END                        0x001231fc
+#define BCHP_HEVD_BE_GLOBAL_1_REG_START                    0x00124000
+#define BCHP_HEVD_BE_GLOBAL_1_REG_END                      0x00124030
+#define BCHP_HEVD_IXFORM_1_REG_START                       0x00124100
+#define BCHP_HEVD_IXFORM_1_REG_END                         0x001241fc
+#define BCHP_HEVD_MCOMP_1_REG_START                        0x00124200
+#define BCHP_HEVD_MCOMP_1_REG_END                          0x001242fc
+#define BCHP_HEVD_SPRED_1_REG_START                        0x00124300
+#define BCHP_HEVD_SPRED_1_REG_END                          0x001243f0
+#define BCHP_HEVD_FILTER_1_REG_START                       0x00124400
+#define BCHP_HEVD_FILTER_1_REG_END                         0x001244fc
+#define BCHP_HEVD_OUTPUT_1_REG_START                       0x00124500
+#define BCHP_HEVD_OUTPUT_1_REG_END                         0x001245fc
+#define BCHP_HEVD_MARKER_1_REG_START                       0x00124f00
+#define BCHP_HEVD_MARKER_1_REG_END                         0x00124f7c
+#define BCHP_HEVD_FE_CTRL_1_REG_START                      0x00125000
+#define BCHP_HEVD_FE_CTRL_1_REG_END                        0x00125034
+#define BCHP_HEVD_STRM_IN_1_REG_START                      0x00125100
+#define BCHP_HEVD_STRM_IN_1_REG_END                        0x00125118
+#define BCHP_HEVD_CMDBUS_XMIT_1_REG_START                  0x00125200
+#define BCHP_HEVD_CMDBUS_XMIT_1_REG_END                    0x00125210
+#define BCHP_HEVD_VECGEN_1_REG_START                       0x00125400
+#define BCHP_HEVD_VECGEN_1_REG_END                         0x00125698
+#define BCHP_DCD_PIPE_CTL_1_REG_START                      0x00126000
+#define BCHP_DCD_PIPE_CTL_1_REG_END                        0x00126404
+#define BCHP_HEVD_PCACHE_1_REG_START                       0x00126800
+#define BCHP_HEVD_PCACHE_1_REG_END                         0x00126834
+#define BCHP_HEVD_PFRI_1_REG_START                         0x00126a00
+#define BCHP_HEVD_PFRI_1_REG_END                           0x00126b58
+#define BCHP_RVC_1_REG_START                               0x00126c00
+#define BCHP_RVC_1_REG_END                                 0x00126c20
+#define BCHP_ILS_REGS_1_REG_START                          0x00127000
+#define BCHP_ILS_REGS_1_REG_END                            0x001270fc
+#define BCHP_ILS_SCALE_ADDR_1_REG_START                    0x00127100
+#define BCHP_ILS_SCALE_ADDR_1_REG_END                      0x0012710c
+#define BCHP_ILS_SPSCALE_FILL_1_REG_START                  0x00127180
+#define BCHP_ILS_SPSCALE_FILL_1_REG_END                    0x00127184
+#define BCHP_ILS_MVSCALE_1_REG_START                       0x00127200
+#define BCHP_ILS_MVSCALE_1_REG_END                         0x0012738c
+#define BCHP_ILB_REGS_1_REG_START                          0x00127400
+#define BCHP_ILB_REGS_1_REG_END                            0x00127410
+#define BCHP_BLD_DECODE_MAIN_1_REG_START                   0x00128100
+#define BCHP_BLD_DECODE_MAIN_1_REG_END                     0x001281fc
+#define BCHP_BLD_DECODE_MCOM_1_REG_START                   0x00128300
+#define BCHP_BLD_DECODE_MCOM_1_REG_END                     0x0012831c
+#define BCHP_BLD_DECODE_SPRE_1_REG_START                   0x00128320
+#define BCHP_BLD_DECODE_SPRE_1_REG_END                     0x0012833c
+#define BCHP_BLD_DECODE_DQNT_1_REG_START                   0x00128400
+#define BCHP_BLD_DECODE_DQNT_1_REG_END                     0x0012845c
+#define BCHP_BLD_DECODE_DQNT_8X8_1_REG_START               0x00128500
+#define BCHP_BLD_DECODE_DQNT_8X8_1_REG_END                 0x0012857c
+#define BCHP_BLD_DECODE_XFRM_1_REG_START                   0x00128700
+#define BCHP_BLD_DECODE_XFRM_1_REG_END                     0x0012871c
+#define BCHP_BLD_DECODE_DBLK_1_REG_START                   0x00128720
+#define BCHP_BLD_DECODE_DBLK_1_REG_END                     0x0012873c
+#define BCHP_BLD_DECODE_MB_1_REG_START                     0x00128740
+#define BCHP_BLD_DECODE_MB_1_REG_END                       0x0012875c
+#define BCHP_BLD_DECODE_SINT_1_REG_START                   0x00128c00
+#define BCHP_BLD_DECODE_SINT_1_REG_END                     0x00128dfc
+#define BCHP_BLD_DECODE_RVC_1_REG_START                    0x00128e00
+#define BCHP_BLD_DECODE_RVC_1_REG_END                      0x00128efc
+#define BCHP_BLD_BL_CPU_REGS_1_REG_START                   0x0012c000
+#define BCHP_BLD_BL_CPU_REGS_1_REG_END                     0x0012c108
+#define BCHP_BLD_BL_CPU_DMA_1_REG_START                    0x0012c400
+#define BCHP_BLD_BL_CPU_DMA_1_REG_END                      0x0012c440
+#define BCHP_BLD_BL_CPU_DEBUG_1_REG_START                  0x0012c800
+#define BCHP_BLD_BL_CPU_DEBUG_1_REG_END                    0x0012cffc
+#define BCHP_BLD_DECODE_IP_SHIM_1_REG_START                0x0012d000
+#define BCHP_BLD_DECODE_IP_SHIM_1_REG_END                  0x0012d090
+#define BCHP_HEVD_IL_CPU_REGS_1_REG_START                  0x00130000
+#define BCHP_HEVD_IL_CPU_REGS_1_REG_END                    0x00130108
+#define BCHP_HEVD_IL_CPU_DMA_1_REG_START                   0x00130400
+#define BCHP_HEVD_IL_CPU_DMA_1_REG_END                     0x00130440
+#define BCHP_HEVD_IL_CPU_DEBUG_1_REG_START                 0x00130800
+#define BCHP_HEVD_IL_CPU_DEBUG_1_REG_END                   0x00130ffc
+#define BCHP_HEVD_IL_SLICE_DMA_1_REG_START                 0x00131000
+#define BCHP_HEVD_IL_SLICE_DMA_1_REG_END                   0x0013100c
+#define BCHP_HEVD_IL_LDST_1_REG_START                      0x00134000
+#define BCHP_HEVD_IL_LDST_1_REG_END                        0x00137ffc
+#define BCHP_SHVD_INTR2_1_REG_START                        0x00180000
+#define BCHP_SHVD_INTR2_1_REG_END                          0x0018002c
+#define BCHP_SHVD_RGR_1_REG_START                          0x00180400
+#define BCHP_SHVD_RGR_1_REG_END                            0x00180410
+#define BCHP_VICH_1_REG_START                              0x001a0000
+#define BCHP_VICH_1_REG_END                                0x001a008b
+#define BCHP_HEVD_OL_CPU_REGS_2_REG_START                  0x00200000
+#define BCHP_HEVD_OL_CPU_REGS_2_REG_END                    0x00200108
+#define BCHP_HEVD_OL_CPU_DMA_2_REG_START                   0x00200400
+#define BCHP_HEVD_OL_CPU_DMA_2_REG_END                     0x00200440
+#define BCHP_HEVD_OL_CPU_DEBUG_2_REG_START                 0x00200800
+#define BCHP_HEVD_OL_CPU_DEBUG_2_REG_END                   0x00200ffc
+#define BCHP_HEVD_OL_SINT_2_REG_START                      0x00201000
+#define BCHP_HEVD_OL_SINT_2_REG_END                        0x00201028
+#define BCHP_HEVD_OL_LDST_2_REG_START                      0x00208000
+#define BCHP_HEVD_OL_LDST_2_REG_END                        0x0020fffc
+#define BCHP_REG_CABAC2BINS_2_REG_START                    0x00210b00
+#define BCHP_REG_CABAC2BINS_2_REG_END                      0x00210bfc
+#define BCHP_REG_CABAC2BINS2_2_REG_START                   0x00212400
+#define BCHP_REG_CABAC2BINS2_2_REG_END                     0x002127fc
+#define BCHP_HEVD_CABAC_2_REG_START                        0x00213000
+#define BCHP_HEVD_CABAC_2_REG_END                          0x002130bc
+#define BCHP_HEVD_OL_CTL_2_REG_START                       0x00214000
+#define BCHP_HEVD_OL_CTL_2_REG_END                         0x002151fc
+#define BCHP_DECODE_MAIN_2_REG_START                       0x00220100
+#define BCHP_DECODE_MAIN_2_REG_END                         0x002201fc
+#define BCHP_DECODE_MCOM_2_REG_START                       0x00220300
+#define BCHP_DECODE_MCOM_2_REG_END                         0x0022031c
+#define BCHP_DECODE_SPRE_2_REG_START                       0x00220320
+#define BCHP_DECODE_SPRE_2_REG_END                         0x0022033c
+#define BCHP_DECODE_WPRD_2_REG_START                       0x00220340
+#define BCHP_DECODE_WPRD_2_REG_END                         0x0022035c
+#define BCHP_DECODE_DQNT_2_REG_START                       0x00220400
+#define BCHP_DECODE_DQNT_2_REG_END                         0x0022045c
+#define BCHP_DECODE_DQNT_8X8_2_REG_START                   0x00220500
+#define BCHP_DECODE_DQNT_8X8_2_REG_END                     0x0022057c
+#define BCHP_DECODE_VP8_XFRM_2_REG_START                   0x00220600
+#define BCHP_DECODE_VP8_XFRM_2_REG_END                     0x0022060c
+#define BCHP_DECODE_VP6_DCP_2_REG_START                    0x00220620
+#define BCHP_DECODE_VP6_DCP_2_REG_END                      0x0022062c
+#define BCHP_DECODE_XFRM_2_REG_START                       0x00220700
+#define BCHP_DECODE_XFRM_2_REG_END                         0x0022071c
+#define BCHP_DECODE_DBLK_2_REG_START                       0x00220720
+#define BCHP_DECODE_DBLK_2_REG_END                         0x0022073c
+#define BCHP_DECODE_MB_2_REG_START                         0x00220740
+#define BCHP_DECODE_MB_2_REG_END                           0x0022075c
+#define BCHP_DECODE_SINT_2_REG_START                       0x00220c00
+#define BCHP_DECODE_SINT_2_REG_END                         0x00220dfc
+#define BCHP_DECODE_RVC_2_REG_START                        0x00220e00
+#define BCHP_DECODE_RVC_2_REG_END                          0x00220efc
+#define BCHP_DECODE_WPTBL_2_REG_START                      0x00223000
+#define BCHP_DECODE_WPTBL_2_REG_END                        0x002231fc
+#define BCHP_HEVD_BE_GLOBAL_2_REG_START                    0x00224000
+#define BCHP_HEVD_BE_GLOBAL_2_REG_END                      0x00224030
+#define BCHP_HEVD_IXFORM_2_REG_START                       0x00224100
+#define BCHP_HEVD_IXFORM_2_REG_END                         0x002241fc
+#define BCHP_HEVD_MCOMP_2_REG_START                        0x00224200
+#define BCHP_HEVD_MCOMP_2_REG_END                          0x002242fc
+#define BCHP_HEVD_SPRED_2_REG_START                        0x00224300
+#define BCHP_HEVD_SPRED_2_REG_END                          0x002243f0
+#define BCHP_HEVD_FILTER_2_REG_START                       0x00224400
+#define BCHP_HEVD_FILTER_2_REG_END                         0x002244fc
+#define BCHP_HEVD_OUTPUT_2_REG_START                       0x00224500
+#define BCHP_HEVD_OUTPUT_2_REG_END                         0x002245fc
+#define BCHP_HEVD_MARKER_2_REG_START                       0x00224f00
+#define BCHP_HEVD_MARKER_2_REG_END                         0x00224f7c
+#define BCHP_HEVD_FE_CTRL_2_REG_START                      0x00225000
+#define BCHP_HEVD_FE_CTRL_2_REG_END                        0x00225034
+#define BCHP_HEVD_STRM_IN_2_REG_START                      0x00225100
+#define BCHP_HEVD_STRM_IN_2_REG_END                        0x00225118
+#define BCHP_HEVD_CMDBUS_XMIT_2_REG_START                  0x00225200
+#define BCHP_HEVD_CMDBUS_XMIT_2_REG_END                    0x00225210
+#define BCHP_HEVD_VECGEN_2_REG_START                       0x00225400
+#define BCHP_HEVD_VECGEN_2_REG_END                         0x00225698
+#define BCHP_DCD_PIPE_CTL_2_REG_START                      0x00226000
+#define BCHP_DCD_PIPE_CTL_2_REG_END                        0x00226404
+#define BCHP_HEVD_PCACHE_2_REG_START                       0x00226800
+#define BCHP_HEVD_PCACHE_2_REG_END                         0x00226834
+#define BCHP_HEVD_PFRI_2_REG_START                         0x00226a00
+#define BCHP_HEVD_PFRI_2_REG_END                           0x00226b58
+#define BCHP_RVC_2_REG_START                               0x00226c00
+#define BCHP_RVC_2_REG_END                                 0x00226c20
+#define BCHP_ILS_REGS_2_REG_START                          0x00227000
+#define BCHP_ILS_REGS_2_REG_END                            0x002270fc
+#define BCHP_ILS_SCALE_ADDR_2_REG_START                    0x00227100
+#define BCHP_ILS_SCALE_ADDR_2_REG_END                      0x0022710c
+#define BCHP_ILS_SPSCALE_FILL_2_REG_START                  0x00227180
+#define BCHP_ILS_SPSCALE_FILL_2_REG_END                    0x00227184
+#define BCHP_ILS_MVSCALE_2_REG_START                       0x00227200
+#define BCHP_ILS_MVSCALE_2_REG_END                         0x0022738c
+#define BCHP_ILB_REGS_2_REG_START                          0x00227400
+#define BCHP_ILB_REGS_2_REG_END                            0x00227410
+#define BCHP_BLD_DECODE_MAIN_2_REG_START                   0x00228100
+#define BCHP_BLD_DECODE_MAIN_2_REG_END                     0x002281fc
+#define BCHP_BLD_DECODE_MCOM_2_REG_START                   0x00228300
+#define BCHP_BLD_DECODE_MCOM_2_REG_END                     0x0022831c
+#define BCHP_BLD_DECODE_SPRE_2_REG_START                   0x00228320
+#define BCHP_BLD_DECODE_SPRE_2_REG_END                     0x0022833c
+#define BCHP_BLD_DECODE_DQNT_2_REG_START                   0x00228400
+#define BCHP_BLD_DECODE_DQNT_2_REG_END                     0x0022845c
+#define BCHP_BLD_DECODE_DQNT_8X8_2_REG_START               0x00228500
+#define BCHP_BLD_DECODE_DQNT_8X8_2_REG_END                 0x0022857c
+#define BCHP_BLD_DECODE_XFRM_2_REG_START                   0x00228700
+#define BCHP_BLD_DECODE_XFRM_2_REG_END                     0x0022871c
+#define BCHP_BLD_DECODE_DBLK_2_REG_START                   0x00228720
+#define BCHP_BLD_DECODE_DBLK_2_REG_END                     0x0022873c
+#define BCHP_BLD_DECODE_MB_2_REG_START                     0x00228740
+#define BCHP_BLD_DECODE_MB_2_REG_END                       0x0022875c
+#define BCHP_BLD_DECODE_SINT_2_REG_START                   0x00228c00
+#define BCHP_BLD_DECODE_SINT_2_REG_END                     0x00228dfc
+#define BCHP_BLD_DECODE_RVC_2_REG_START                    0x00228e00
+#define BCHP_BLD_DECODE_RVC_2_REG_END                      0x00228efc
+#define BCHP_BLD_BL_CPU_REGS_2_REG_START                   0x0022c000
+#define BCHP_BLD_BL_CPU_REGS_2_REG_END                     0x0022c108
+#define BCHP_BLD_BL_CPU_DMA_2_REG_START                    0x0022c400
+#define BCHP_BLD_BL_CPU_DMA_2_REG_END                      0x0022c440
+#define BCHP_BLD_BL_CPU_DEBUG_2_REG_START                  0x0022c800
+#define BCHP_BLD_BL_CPU_DEBUG_2_REG_END                    0x0022cffc
+#define BCHP_BLD_DECODE_IP_SHIM_2_REG_START                0x0022d000
+#define BCHP_BLD_DECODE_IP_SHIM_2_REG_END                  0x0022d090
+#define BCHP_HEVD_IL_CPU_REGS_2_REG_START                  0x00230000
+#define BCHP_HEVD_IL_CPU_REGS_2_REG_END                    0x00230108
+#define BCHP_HEVD_IL_CPU_DMA_2_REG_START                   0x00230400
+#define BCHP_HEVD_IL_CPU_DMA_2_REG_END                     0x00230440
+#define BCHP_HEVD_IL_CPU_DEBUG_2_REG_START                 0x00230800
+#define BCHP_HEVD_IL_CPU_DEBUG_2_REG_END                   0x00230ffc
+#define BCHP_HEVD_IL_SLICE_DMA_2_REG_START                 0x00231000
+#define BCHP_HEVD_IL_SLICE_DMA_2_REG_END                   0x0023100c
+#define BCHP_HEVD_IL_LDST_2_REG_START                      0x00234000
+#define BCHP_HEVD_IL_LDST_2_REG_END                        0x00237ffc
+#define BCHP_SHVD_INTR2_2_REG_START                        0x00280000
+#define BCHP_SHVD_INTR2_2_REG_END                          0x0028002c
+#define BCHP_SHVD_RGR_2_REG_START                          0x00280400
+#define BCHP_SHVD_RGR_2_REG_END                            0x00280410
+#define BCHP_VICH_2_REG_START                              0x002a0000
+#define BCHP_VICH_2_REG_END                                0x002a008b
+#define BCHP_SCPU_LOCALRAM_REG_START                       0x00300000
+#define BCHP_SCPU_LOCALRAM_REG_END                         0x00307ffc
+#define BCHP_SCPU_GLOBALRAM_REG_START                      0x00308000
+#define BCHP_SCPU_GLOBALRAM_REG_END                        0x003083fc
+#define BCHP_SCPU_MISB_BRIDGE_REG_START                    0x00308400
+#define BCHP_SCPU_MISB_BRIDGE_REG_END                      0x00308410
+#define BCHP_SCPU_RGR_BRIDGE_REG_START                     0x00308420
+#define BCHP_SCPU_RGR_BRIDGE_REG_END                       0x00308430
+#define BCHP_SCPU_INTR1_REG_START                          0x00308440
+#define BCHP_SCPU_INTR1_REG_END                            0x00308458
+#define BCHP_INTERNAL_INTR2_REG_START                      0x00308480
+#define BCHP_INTERNAL_INTR2_REG_END                        0x003084ac
+#define BCHP_BSP_IPI_INTR2_REG_START                       0x003084c0
+#define BCHP_BSP_IPI_INTR2_REG_END                         0x003084ec
+#define BCHP_CPU_IPI_INTR2_REG_START                       0x00308500
+#define BCHP_CPU_IPI_INTR2_REG_END                         0x0030852c
+#define BCHP_SCPU_HOST_INTR2_REG_START                     0x00308540
+#define BCHP_SCPU_HOST_INTR2_REG_END                       0x0030856c
+#define BCHP_SCPU_TOP_CTRL_REG_START                       0x00308580
+#define BCHP_SCPU_TOP_CTRL_REG_END                         0x00308588
+#define BCHP_SCPU_SEC_TIME_REG_START                       0x003085a0
+#define BCHP_SCPU_SEC_TIME_REG_END                         0x003085b4
+#define BCHP_SCPU_PM_REG_START                             0x00308980
+#define BCHP_SCPU_PM_REG_END                               0x00308988
+#define BCHP_SCPU_TIMER_REG_START                          0x00308e80
+#define BCHP_SCPU_TIMER_REG_END                            0x00308ebc
+#define BCHP_S_SCPU_REG_START                              0x00310000
+#define BCHP_S_SCPU_REG_END                                0x0031bffc
+#define BCHP_BSP_CMDBUF_REG_START                          0x00329800
+#define BCHP_BSP_CMDBUF_REG_END                            0x00329ffc
+#define BCHP_BSP_GLB_CONTROL_REG_START                     0x0032b000
+#define BCHP_BSP_GLB_CONTROL_REG_END                       0x0032b0a4
+#define BCHP_BSP_PKL_REG_START                             0x0032b300
+#define BCHP_BSP_PKL_REG_END                               0x0032b37c
+#define BCHP_BSP_INST_PATCH_CTRL_REG_START                 0x0032b400
+#define BCHP_BSP_INST_PATCH_CTRL_REG_END                   0x0032b408
+#define BCHP_BSP_BOOT_PATCH_CTRL_REG_START                 0x0032b410
+#define BCHP_BSP_BOOT_PATCH_CTRL_REG_END                   0x0032b418
+#define BCHP_BSP_CONTROL_INTR2_REG_START                   0x0032b800
+#define BCHP_BSP_CONTROL_INTR2_REG_END                     0x0032b82c
+#define BCHP_BSP_VISTA_GENACC_REG_START                    0x0032b900
+#define BCHP_BSP_VISTA_GENACC_REG_END                      0x0032b9fc
+#define BCHP_BSP_VISTA_GENACC2_REG_START                   0x0032ba00
+#define BCHP_BSP_VISTA_GENACC2_REG_END                     0x0032bafc
+#define BCHP_BSP_OTP_SCRATCH_REG_START                     0x0032c000
+#define BCHP_BSP_OTP_SCRATCH_REG_END                       0x0032dffc
+#define BCHP_XPT_SECURITY_REG_START                        0x00360000
+#define BCHP_XPT_SECURITY_REG_END                          0x0037fffc
+#define BCHP_SECTOP_GRB_REG_START                          0x00380000
+#define BCHP_SECTOP_GRB_REG_END                            0x0038000c
+#define BCHP_XPT_SECURITY_NS_REG_START                     0x00380200
+#define BCHP_XPT_SECURITY_NS_REG_END                       0x00380224
+#define BCHP_MEMC_GEN_0_REG_START                          0x003b0000
+#define BCHP_MEMC_GEN_0_REG_END                            0x003b040c
+#define BCHP_MEMC_EDIS_0_0_REG_START                       0x003b0800
+#define BCHP_MEMC_EDIS_0_0_REG_END                         0x003b08fc
+#define BCHP_MEMC_EDIS_1_0_REG_START                       0x003b0a00
+#define BCHP_MEMC_EDIS_1_0_REG_END                         0x003b0afc
+#define BCHP_MEMC_GEN_2_0_REG_START                        0x003b0c00
+#define BCHP_MEMC_GEN_2_0_REG_END                          0x003b0f74
+#define BCHP_MEMC_ARB_0_REG_START                          0x003b1000
+#define BCHP_MEMC_ARB_0_REG_END                            0x003b1488
+#define BCHP_MEMC_DDR_0_REG_START                          0x003b2000
+#define BCHP_MEMC_DDR_0_REG_END                            0x003b250c
+#define BCHP_MEMC_L2_0_REG_START                           0x003b3000
+#define BCHP_MEMC_L2_0_REG_END                             0x003b3044
+#define BCHP_MEMC_L2_1_0_REG_START                         0x003b3800
+#define BCHP_MEMC_L2_1_0_REG_END                           0x003b3844
+#define BCHP_MEMC_L2_2_0_REG_START                         0x003b3900
+#define BCHP_MEMC_L2_2_0_REG_END                           0x003b3944
+#define BCHP_MEMC_RGRB_0_REG_START                         0x003b4000
+#define BCHP_MEMC_RGRB_0_REG_END                           0x003b4010
+#define BCHP_MEMC_MISC_0_REG_START                         0x003b5000
+#define BCHP_MEMC_MISC_0_REG_END                           0x003b5010
+#define BCHP_DDR34_PHY_CONTROL_REGS_0_REG_START            0x003b6000
+#define BCHP_DDR34_PHY_CONTROL_REGS_0_REG_END              0x003b6248
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_REG_START             0x003b6400
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_REG_END               0x003b6510
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_REG_START             0x003b6600
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_REG_END               0x003b6710
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_REG_START             0x003b6800
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_REG_END               0x003b6910
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_REG_START             0x003b6a00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_REG_END               0x003b6b10
+#define BCHP_DDR34_PHY_ECC_LANE_0_REG_START                0x003b6c00
+#define BCHP_DDR34_PHY_ECC_LANE_0_REG_END                  0x003b6d10
+#define BCHP_SHIMPHY_ADDR_CNTL_0_REG_START                 0x003b8000
+#define BCHP_SHIMPHY_ADDR_CNTL_0_REG_END                   0x003b80b4
+#define BCHP_S_MEMC_0_REG_START                            0x003bc000
+#define BCHP_S_MEMC_0_REG_END                              0x003bc5b0
+#define BCHP_MEMC_GEN_1_REG_START                          0x003c0000
+#define BCHP_MEMC_GEN_1_REG_END                            0x003c040c
+#define BCHP_MEMC_EDIS_0_1_REG_START                       0x003c0800
+#define BCHP_MEMC_EDIS_0_1_REG_END                         0x003c08fc
+#define BCHP_MEMC_EDIS_1_1_REG_START                       0x003c0a00
+#define BCHP_MEMC_EDIS_1_1_REG_END                         0x003c0afc
+#define BCHP_MEMC_GEN_2_1_REG_START                        0x003c0c00
+#define BCHP_MEMC_GEN_2_1_REG_END                          0x003c0f74
+#define BCHP_MEMC_ARB_1_REG_START                          0x003c1000
+#define BCHP_MEMC_ARB_1_REG_END                            0x003c1488
+#define BCHP_MEMC_DDR_1_REG_START                          0x003c2000
+#define BCHP_MEMC_DDR_1_REG_END                            0x003c250c
+#define BCHP_MEMC_L2_1_REG_START                           0x003c3000
+#define BCHP_MEMC_L2_1_REG_END                             0x003c3044
+#define BCHP_MEMC_L2_1_1_REG_START                         0x003c3800
+#define BCHP_MEMC_L2_1_1_REG_END                           0x003c3844
+#define BCHP_MEMC_L2_2_1_REG_START                         0x003c3900
+#define BCHP_MEMC_L2_2_1_REG_END                           0x003c3944
+#define BCHP_MEMC_RGRB_1_REG_START                         0x003c4000
+#define BCHP_MEMC_RGRB_1_REG_END                           0x003c4010
+#define BCHP_MEMC_MISC_1_REG_START                         0x003c5000
+#define BCHP_MEMC_MISC_1_REG_END                           0x003c5010
+#define BCHP_DDR34_PHY_CONTROL_REGS_1_REG_START            0x003c6000
+#define BCHP_DDR34_PHY_CONTROL_REGS_1_REG_END              0x003c6248
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_REG_START             0x003c6400
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_REG_END               0x003c6510
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_REG_START             0x003c6600
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_REG_END               0x003c6710
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_REG_START             0x003c6800
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_REG_END               0x003c6910
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_REG_START             0x003c6a00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_REG_END               0x003c6b10
+#define BCHP_DDR34_PHY_ECC_LANE_1_REG_START                0x003c6c00
+#define BCHP_DDR34_PHY_ECC_LANE_1_REG_END                  0x003c6d10
+#define BCHP_SHIMPHY_ADDR_CNTL_1_REG_START                 0x003c8000
+#define BCHP_SHIMPHY_ADDR_CNTL_1_REG_END                   0x003c80b4
+#define BCHP_S_MEMC_1_REG_START                            0x003cc000
+#define BCHP_S_MEMC_1_REG_END                              0x003cc5b0
+#define BCHP_MEMC_GEN_2_REG_START                          0x003d0000
+#define BCHP_MEMC_GEN_2_REG_END                            0x003d040c
+#define BCHP_MEMC_EDIS_0_2_REG_START                       0x003d0800
+#define BCHP_MEMC_EDIS_0_2_REG_END                         0x003d08fc
+#define BCHP_MEMC_EDIS_1_2_REG_START                       0x003d0a00
+#define BCHP_MEMC_EDIS_1_2_REG_END                         0x003d0afc
+#define BCHP_MEMC_GEN_2_2_REG_START                        0x003d0c00
+#define BCHP_MEMC_GEN_2_2_REG_END                          0x003d0f74
+#define BCHP_MEMC_ARB_2_REG_START                          0x003d1000
+#define BCHP_MEMC_ARB_2_REG_END                            0x003d1488
+#define BCHP_MEMC_DDR_2_REG_START                          0x003d2000
+#define BCHP_MEMC_DDR_2_REG_END                            0x003d250c
+#define BCHP_MEMC_L2_2_REG_START                           0x003d3000
+#define BCHP_MEMC_L2_2_REG_END                             0x003d3044
+#define BCHP_MEMC_L2_1_2_REG_START                         0x003d3800
+#define BCHP_MEMC_L2_1_2_REG_END                           0x003d3844
+#define BCHP_MEMC_L2_2_2_REG_START                         0x003d3900
+#define BCHP_MEMC_L2_2_2_REG_END                           0x003d3944
+#define BCHP_MEMC_RGRB_2_REG_START                         0x003d4000
+#define BCHP_MEMC_RGRB_2_REG_END                           0x003d4010
+#define BCHP_MEMC_MISC_2_REG_START                         0x003d5000
+#define BCHP_MEMC_MISC_2_REG_END                           0x003d5010
+#define BCHP_DDR34_PHY_CONTROL_REGS_2_REG_START            0x003d6000
+#define BCHP_DDR34_PHY_CONTROL_REGS_2_REG_END              0x003d6248
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_REG_START             0x003d6400
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_REG_END               0x003d6510
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_REG_START             0x003d6600
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_REG_END               0x003d6710
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_REG_START             0x003d6800
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_REG_END               0x003d6910
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_REG_START             0x003d6a00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_REG_END               0x003d6b10
+#define BCHP_DDR34_PHY_ECC_LANE_2_REG_START                0x003d6c00
+#define BCHP_DDR34_PHY_ECC_LANE_2_REG_END                  0x003d6d10
+#define BCHP_SHIMPHY_ADDR_CNTL_2_REG_START                 0x003d8000
+#define BCHP_SHIMPHY_ADDR_CNTL_2_REG_END                   0x003d80b4
+#define BCHP_S_MEMC_2_REG_START                            0x003dc000
+#define BCHP_S_MEMC_2_REG_END                              0x003dc5b0
+#define BCHP_SUN_GISB_ARB_REG_START                        0x00400000
+#define BCHP_SUN_GISB_ARB_REG_END                          0x004007fc
+#define BCHP_SUN_GR_REG_START                              0x00401000
+#define BCHP_SUN_GR_REG_END                                0x0040100c
+#define BCHP_SSP_RG_REG_START                              0x00401200
+#define BCHP_SSP_RG_REG_END                                0x0040120c
+#define BCHP_SUN_RG_REG_START                              0x00401400
+#define BCHP_SUN_RG_REG_END                                0x0040140c
+#define BCHP_TPCAP_REG_START                               0x00401800
+#define BCHP_TPCAP_REG_END                                 0x0040189c
+#define BCHP_SUN_L2_REG_START                              0x00403000
+#define BCHP_SUN_L2_REG_END                                0x00403044
+#define BCHP_SM_L2_REG_START                               0x00403400
+#define BCHP_SM_L2_REG_END                                 0x0040342c
+#define BCHP_SM_REG_START                                  0x00403800
+#define BCHP_SM_REG_END                                    0x00403824
+#define BCHP_SM_FAST_REG_START                             0x00403c00
+#define BCHP_SM_FAST_REG_END                               0x00403c18
+#define BCHP_SUN_TOP_CTRL_REG_START                        0x00404000
+#define BCHP_SUN_TOP_CTRL_REG_END                          0x00404518
+#define BCHP_IRB_REG_START                                 0x00406000
+#define BCHP_IRB_REG_END                                   0x00406138
+#define BCHP_PM_REG_START                                  0x00406180
+#define BCHP_PM_REG_END                                    0x0040618c
+#define BCHP_BSCA_REG_START                                0x00406200
+#define BCHP_BSCA_REG_END                                  0x00406254
+#define BCHP_BSCD_REG_START                                0x00406280
+#define BCHP_BSCD_REG_END                                  0x004062d4
+#define BCHP_BSCE_REG_START                                0x00406300
+#define BCHP_BSCE_REG_END                                  0x00406354
+#define BCHP_PWM_REG_START                                 0x00406580
+#define BCHP_PWM_REG_END                                   0x004065a4
+#define BCHP_GIO_REG_START                                 0x00406700
+#define BCHP_GIO_REG_END                                   0x0040677c
+#define BCHP_IRQ0_REG_START                                0x00406780
+#define BCHP_IRQ0_REG_END                                  0x00406784
+#define BCHP_IRQ1_REG_START                                0x00406788
+#define BCHP_IRQ1_REG_END                                  0x0040678c
+#define BCHP_TIMER_REG_START                               0x004067c0
+#define BCHP_TIMER_REG_END                                 0x004067fc
+#define BCHP_PWMB_REG_START                                0x00406800
+#define BCHP_PWMB_REG_END                                  0x00406824
+#define BCHP_UARTA_REG_START                               0x00406b00
+#define BCHP_UARTA_REG_END                                 0x00406b1c
+#define BCHP_UARTB_REG_START                               0x00406b40
+#define BCHP_UARTB_REG_END                                 0x00406b5c
+#define BCHP_UARTC_REG_START                               0x00406b80
+#define BCHP_UARTC_REG_END                                 0x00406b9c
+#define BCHP_SCA_REG_START                                 0x00406c00
+#define BCHP_SCA_REG_END                                   0x00406cbc
+#define BCHP_SCB_REG_START                                 0x00406cc0
+#define BCHP_SCB_REG_END                                   0x00406d7c
+#define BCHP_SCIRQ0_REG_START                              0x00406e40
+#define BCHP_SCIRQ0_REG_END                                0x00406e44
+#define BCHP_SCIRQ1_REG_START                              0x00406e48
+#define BCHP_SCIRQ1_REG_END                                0x00406e4c
+#define BCHP_SCIRQ_SCPU_REG_START                          0x00406e50
+#define BCHP_SCIRQ_SCPU_REG_END                            0x00406e54
+#define BCHP_MCIF_REG_START                                0x00407000
+#define BCHP_MCIF_REG_END                                  0x00407028
+#define BCHP_MCIF_INTR2_REG_START                          0x00407080
+#define BCHP_MCIF_INTR2_REG_END                            0x004070c4
+#define BCHP_TMON_REG_START                                0x00407100
+#define BCHP_TMON_REG_END                                  0x00407154
+#define BCHP_UPG_AUX_INTR2_REG_START                       0x00407180
+#define BCHP_UPG_AUX_INTR2_REG_END                         0x004071ac
+#define BCHP_CTK_REG_START                                 0x00407200
+#define BCHP_CTK_REG_END                                   0x00407378
+#define BCHP_UPG_UART_DMA_REG_START                        0x00407600
+#define BCHP_UPG_UART_DMA_REG_END                          0x00407630
+#define BCHP_AON_CTRL_REG_START                            0x00410000
+#define BCHP_AON_CTRL_REG_END                              0x004103fc
+#define BCHP_AON_L2_REG_START                              0x00410400
+#define BCHP_AON_L2_REG_END                                0x0041042c
+#define BCHP_AON_PM_L2_REG_START                           0x00410440
+#define BCHP_AON_PM_L2_REG_END                             0x0041046c
+#define BCHP_AON_PIN_CTRL_REG_START                        0x00410500
+#define BCHP_AON_PIN_CTRL_REG_END                          0x00410514
+#define BCHP_AON_HDMI_TX_REG_START                         0x00410600
+#define BCHP_AON_HDMI_TX_REG_END                           0x00410698
+#define BCHP_AON_HDMI_RX_REG_START                         0x00410800
+#define BCHP_AON_HDMI_RX_REG_END                           0x00410900
+#define BCHP_LDK_REG_START                                 0x00411000
+#define BCHP_LDK_REG_END                                   0x0041103c
+#define BCHP_PM_AON_REG_START                              0x00411040
+#define BCHP_PM_AON_REG_END                                0x00411048
+#define BCHP_ICAP_REG_START                                0x00411080
+#define BCHP_ICAP_REG_END                                  0x004110bc
+#define BCHP_KBD1_REG_START                                0x004110c0
+#define BCHP_KBD1_REG_END                                  0x004110fc
+#define BCHP_KBD2_REG_START                                0x00411100
+#define BCHP_KBD2_REG_END                                  0x0041113c
+#define BCHP_KBD3_REG_START                                0x00411140
+#define BCHP_KBD3_REG_END                                  0x0041117c
+#define BCHP_BSCB_REG_START                                0x00411180
+#define BCHP_BSCB_REG_END                                  0x004111d4
+#define BCHP_MSPI_REG_START                                0x00411200
+#define BCHP_MSPI_REG_END                                  0x0041137c
+#define BCHP_BSCC_REG_START                                0x00411400
+#define BCHP_BSCC_REG_END                                  0x00411454
+#define BCHP_IRQ0_AON_REG_START                            0x00411480
+#define BCHP_IRQ0_AON_REG_END                              0x00411484
+#define BCHP_IRQ1_AON_REG_START                            0x00411488
+#define BCHP_IRQ1_AON_REG_END                              0x0041148c
+#define BCHP_GIO_AON_REG_START                             0x004114c0
+#define BCHP_GIO_AON_REG_END                               0x004114fc
+#define BCHP_BICAP_REG_START                               0x00411500
+#define BCHP_BICAP_REG_END                                 0x00411538
+#define BCHP_UPG_AUX_AON_INTR2_REG_START                   0x00411540
+#define BCHP_UPG_AUX_AON_INTR2_REG_END                     0x0041156c
+#define BCHP_WKTMR_REG_START                               0x00411580
+#define BCHP_WKTMR_REG_END                                 0x00411590
+#define BCHP_CNTControlBase_REG_START                      0x00414000
+#define BCHP_CNTControlBase_REG_END                        0x00414ffc
+#define BCHP_CNTReadBase_REG_START                         0x00416000
+#define BCHP_CNTReadBase_REG_END                           0x00416ffc
+#define BCHP_SYS_GISB_ARB_SEC_REG_START                    0x0041e000
+#define BCHP_SYS_GISB_ARB_SEC_REG_END                      0x0041e7fc
+#define BCHP_SYS_TOP_CTRL_SEC_REG_START                    0x0041e800
+#define BCHP_SYS_TOP_CTRL_SEC_REG_END                      0x0041e804
+#define BCHP_AON_CTRL_SECURE_REG_START                     0x0041e900
+#define BCHP_AON_CTRL_SECURE_REG_END                       0x0041e97c
+#define BCHP_BOOTSRAM_SECURE_REG_START                     0x00420000
+#define BCHP_BOOTSRAM_SECURE_REG_END                       0x0042fffc
+#define BCHP_ITCH0_REG_START                               0x00430000
+#define BCHP_ITCH0_REG_END                                 0x00430000
+#define BCHP_HIF_SECURE_CTRL_REG_START                     0x00430400
+#define BCHP_HIF_SECURE_CTRL_REG_END                       0x00430400
+#define BCHP_HIF_SECURE_BSPI_REG_START                     0x00430500
+#define BCHP_HIF_SECURE_BSPI_REG_END                       0x00430500
+#define BCHP_HIF_SECURE_LR_SPI_REG_START                   0x00430600
+#define BCHP_HIF_SECURE_LR_SPI_REG_END                     0x00430600
+#define BCHP_NAND_SECURE_REG_START                         0x00430800
+#define BCHP_NAND_SECURE_REG_END                           0x00430800
+#define BCHP_HIF_SECURE_INDIRECT_MSPI_PIPE_REG_START       0x00430c00
+#define BCHP_HIF_SECURE_INDIRECT_MSPI_PIPE_REG_END         0x00430c00
+#define BCHP_HIF_CPUBIUARCH_SECURE_REG_START               0x00430e00
+#define BCHP_HIF_CPUBIUARCH_SECURE_REG_END                 0x00430ffc
+#define BCHP_HIF_CONTINUATION_SECURE_REG_START             0x00431000
+#define BCHP_HIF_CONTINUATION_SECURE_REG_END               0x00431000
+#define BCHP_ITCH1_REG_START                               0x00431200
+#define BCHP_ITCH1_REG_END                                 0x00431200
+#define BCHP_SDIO_0_HOST_REG_START                         0x00440000
+#define BCHP_SDIO_0_HOST_REG_END                           0x004400fc
+#define BCHP_SDIO_0_CFG_REG_START                          0x00440100
+#define BCHP_SDIO_0_CFG_REG_END                            0x004401fc
+#define BCHP_SDIO_1_HOST_REG_START                         0x00440200
+#define BCHP_SDIO_1_HOST_REG_END                           0x004402fc
+#define BCHP_SDIO_1_CFG_REG_START                          0x00440300
+#define BCHP_SDIO_1_CFG_REG_END                            0x004403fc
+#define BCHP_SDIO_1_BOOT_REG_START                         0x00440400
+#define BCHP_SDIO_1_BOOT_REG_END                           0x0044043c
+#define BCHP_EBI_REG_START                                 0x00440800
+#define BCHP_EBI_REG_END                                   0x00440bfc
+#define BCHP_HIF_INTR2_REG_START                           0x00441000
+#define BCHP_HIF_INTR2_REG_END                             0x0044102c
+#define BCHP_IPI0_INTR2_REG_START                          0x00441100
+#define BCHP_IPI0_INTR2_REG_END                            0x0044112c
+#define BCHP_IPI1_INTR2_REG_START                          0x00441200
+#define BCHP_IPI1_INTR2_REG_END                            0x0044122c
+#define BCHP_IPI2_INTR2_REG_START                          0x00441300
+#define BCHP_IPI2_INTR2_REG_END                            0x0044132c
+#define BCHP_IPI3_INTR2_REG_START                          0x00441400
+#define BCHP_IPI3_INTR2_REG_END                            0x0044142c
+#define BCHP_HIF_CPU_INTR1_REG_START                       0x00441500
+#define BCHP_HIF_CPU_INTR1_REG_END                         0x0044153c
+#define BCHP_PCI_PCIE_INTR1_REG_START                      0x00441600
+#define BCHP_PCI_PCIE_INTR1_REG_END                        0x0044163c
+#define BCHP_HIF_RGR2_REG_START                            0x00441700
+#define BCHP_HIF_RGR2_REG_END                              0x00441710
+#define BCHP_HIF_SPI_INTR2_REG_START                       0x00441a00
+#define BCHP_HIF_SPI_INTR2_REG_END                         0x00441a2c
+#define BCHP_HIF_TOP_CTRL_REG_START                        0x00442000
+#define BCHP_HIF_TOP_CTRL_REG_END                          0x00442038
+#define BCHP_WEBHIF_L1_MASK_REG_START                      0x00442100
+#define BCHP_WEBHIF_L1_MASK_REG_END                        0x0044210c
+#define BCHP_HIF_CPUBIUARCH_REG_START                      0x00442200
+#define BCHP_HIF_CPUBIUARCH_REG_END                        0x0044227c
+#define BCHP_HIF_CPUBIUCTRL_REG_START                      0x00442400
+#define BCHP_HIF_CPUBIUCTRL_REG_END                        0x004425b0
+#define BCHP_NAND_REG_START                                0x00442800
+#define BCHP_NAND_REG_END                                  0x00442dfc
+#define BCHP_FLASH_DMA_REG_START                           0x00443000
+#define BCHP_FLASH_DMA_REG_END                             0x00443028
+#define BCHP_BSPI_REG_START                                0x00443200
+#define BCHP_BSPI_REG_END                                  0x0044324c
+#define BCHP_BSPI_RAF_REG_START                            0x00443300
+#define BCHP_BSPI_RAF_REG_END                              0x00443320
+#define BCHP_HIF_MSPI_REG_START                            0x00443400
+#define BCHP_HIF_MSPI_REG_END                              0x00443584
+#define BCHP_WEBHIF_RGR1_REG_START                         0x00450000
+#define BCHP_WEBHIF_RGR1_REG_END                           0x00450010
+#define BCHP_WEBHIF_INTR2_REG_START                        0x00450100
+#define BCHP_WEBHIF_INTR2_REG_END                          0x0045012c
+#define BCHP_WEBHIF_IPI0_INTR2_REG_START                   0x00450200
+#define BCHP_WEBHIF_IPI0_INTR2_REG_END                     0x0045022c
+#define BCHP_WEBHIF_IPI1_INTR2_REG_START                   0x00450300
+#define BCHP_WEBHIF_IPI1_INTR2_REG_END                     0x0045032c
+#define BCHP_WEBHIF_STB_IPI0_INTR2_REG_START               0x00450400
+#define BCHP_WEBHIF_STB_IPI0_INTR2_REG_END                 0x0045042c
+#define BCHP_WEBHIF_STB_IPI1_INTR2_REG_START               0x00450500
+#define BCHP_WEBHIF_STB_IPI1_INTR2_REG_END                 0x0045052c
+#define BCHP_WEBHIF_CPU_INTR1_REG_START                    0x00450600
+#define BCHP_WEBHIF_CPU_INTR1_REG_END                      0x0045063c
+#define BCHP_WEBHIF_SCRATCH_REG_START                      0x00450800
+#define BCHP_WEBHIF_SCRATCH_REG_END                        0x0045081c
+#define BCHP_WEBHIF_TIMER_REG_START                        0x00450900
+#define BCHP_WEBHIF_TIMER_REG_END                          0x0045093c
+#define BCHP_WEBHIF_TOP_CTRL_REG_START                     0x00450a00
+#define BCHP_WEBHIF_TOP_CTRL_REG_END                       0x00450a08
+#define BCHP_HIF_CONTINUATION_REG_START                    0x00452000
+#define BCHP_HIF_CONTINUATION_REG_END                      0x004520fc
+#define BCHP_WEBHIF_CONTINUATION_REG_START                 0x00452800
+#define BCHP_WEBHIF_CONTINUATION_REG_END                   0x00452814
+#define BCHP_SATA_GRB_REG_START                            0x00458000
+#define BCHP_SATA_GRB_REG_END                              0x0045800c
+#define BCHP_SATA_TOP_CTRL_REG_START                       0x00458040
+#define BCHP_SATA_TOP_CTRL_REG_END                         0x00458060
+#define BCHP_SATA3_INTR2_REG_START                         0x00458080
+#define BCHP_SATA3_INTR2_REG_END                           0x004580ac
+#define BCHP_PORT0_SATA3_PCB_REG_START                     0x00458100
+#define BCHP_PORT0_SATA3_PCB_REG_END                       0x00458ffc
+#define BCHP_PORT1_SATA3_PCB_REG_START                     0x00459100
+#define BCHP_PORT1_SATA3_PCB_REG_END                       0x00459ffc
+#define BCHP_SATA_AHCI_GHC_REG_START                       0x0045a000
+#define BCHP_SATA_AHCI_GHC_REG_END                         0x0045a028
+#define BCHP_SATA_GLOBAL_RESERVED_REG_START                0x0045a02c
+#define BCHP_SATA_GLOBAL_RESERVED_REG_END                  0x0045a09c
+#define BCHP_SATA_PORT0_AHCI_S1_REG_START                  0x0045a100
+#define BCHP_SATA_PORT0_AHCI_S1_REG_END                    0x0045a11c
+#define BCHP_SATA_PORT0_AHCI_S2_REG_START                  0x0045a120
+#define BCHP_SATA_PORT0_AHCI_S2_REG_END                    0x0045a134
+#define BCHP_SATA_PORT0_AHCI_S3_REG_START                  0x0045a138
+#define BCHP_SATA_PORT0_AHCI_S3_REG_END                    0x0045a17c
+#define BCHP_SATA_PORT1_AHCI_S1_REG_START                  0x0045a180
+#define BCHP_SATA_PORT1_AHCI_S1_REG_END                    0x0045a19c
+#define BCHP_SATA_PORT1_AHCI_S2_REG_START                  0x0045a1a0
+#define BCHP_SATA_PORT1_AHCI_S2_REG_END                    0x0045a1b4
+#define BCHP_SATA_PORT1_AHCI_S3_REG_START                  0x0045a1b8
+#define BCHP_SATA_PORT1_AHCI_S3_REG_END                    0x0045a1fc
+#define BCHP_SATA_AHCI_PCICFG_REG_START                    0x0045a600
+#define BCHP_SATA_AHCI_PCICFG_REG_END                      0x0045a664
+#define BCHP_SATA_PORT0_CTRL_REG_START                     0x0045a700
+#define BCHP_SATA_PORT0_CTRL_REG_END                       0x0045a730
+#define BCHP_SATA_PORT0_CJPAT_REG_START                    0x0045a740
+#define BCHP_SATA_PORT0_CJPAT_REG_END                      0x0045a764
+#define BCHP_SATA_PORT1_CTRL_REG_START                     0x0045a780
+#define BCHP_SATA_PORT1_CTRL_REG_END                       0x0045a7b0
+#define BCHP_SATA_PORT1_CJPAT_REG_START                    0x0045a7c0
+#define BCHP_SATA_PORT1_CJPAT_REG_END                      0x0045a7e4
+#define BCHP_SATA_LEG_PCICFG_REG_START                     0x0045a800
+#define BCHP_SATA_LEG_PCICFG_REG_END                       0x0045a880
+#define BCHP_SATA_PORT0_LEG_S1_REG_START                   0x0045a900
+#define BCHP_SATA_PORT0_LEG_S1_REG_END                     0x0045a934
+#define BCHP_SATA_PORT0_LEG_S2_REG_START                   0x0045a940
+#define BCHP_SATA_PORT0_LEG_S2_REG_END                     0x0045a954
+#define BCHP_SATA_PORT0_LEG_S3_REG_START                   0x0045a958
+#define BCHP_SATA_PORT0_LEG_S3_REG_END                     0x0045a998
+#define BCHP_SATA_PORT1_LEG_S1_REG_START                   0x0045aa00
+#define BCHP_SATA_PORT1_LEG_S1_REG_END                     0x0045aa34
+#define BCHP_SATA_PORT1_LEG_S2_REG_START                   0x0045aa40
+#define BCHP_SATA_PORT1_LEG_S2_REG_END                     0x0045aa54
+#define BCHP_SATA_PORT1_LEG_S3_REG_START                   0x0045aa58
+#define BCHP_SATA_PORT1_LEG_S3_REG_END                     0x0045aa98
+#define BCHP_RFM_SYSCLK_REG_START                          0x0045c000
+#define BCHP_RFM_SYSCLK_REG_END                            0x0045c124
+#define BCHP_RFM_CLK27_REG_START                           0x0045c000
+#define BCHP_RFM_CLK27_REG_END                             0x0045c470
+#define BCHP_RFM_L2_REG_START                              0x0045cc00
+#define BCHP_RFM_L2_REG_END                                0x0045cc2c
+#define BCHP_RFM_GRB_REG_START                             0x0045d000
+#define BCHP_RFM_GRB_REG_END                               0x0045d00c
+#define BCHP_PCIE_0_RC_CFG_TYPE1_REG_START                 0x00460000
+#define BCHP_PCIE_0_RC_CFG_TYPE1_REG_END                   0x0046003c
+#define BCHP_PCIE_0_RC_CFG_PM_REG_START                    0x00460048
+#define BCHP_PCIE_0_RC_CFG_PM_REG_END                      0x0046004c
+#define BCHP_PCIE_0_RC_CFG_PCIE_REG_START                  0x004600ac
+#define BCHP_PCIE_0_RC_CFG_PCIE_REG_END                    0x004600e4
+#define BCHP_PCIE_0_RC_CFG_AER_REG_START                   0x00460100
+#define BCHP_PCIE_0_RC_CFG_AER_REG_END                     0x00460134
+#define BCHP_PCIE_0_RC_CFG_VC_REG_START                    0x00460160
+#define BCHP_PCIE_0_RC_CFG_VC_REG_END                      0x00460178
+#define BCHP_PCIE_0_RC_CFG_VENDOR_REG_START                0x00460180
+#define BCHP_PCIE_0_RC_CFG_VENDOR_REG_END                  0x004601a4
+#define BCHP_PCIE_0_RC_CFG_PRIV0_REG_START                 0x00460404
+#define BCHP_PCIE_0_RC_CFG_PRIV0_REG_END                   0x00460418
+#define BCHP_PCIE_0_RC_CFG_PRIV1_REG_START                 0x00460428
+#define BCHP_PCIE_0_RC_CFG_PRIV1_REG_END                   0x00460630
+#define BCHP_PCIE_0_RC_TL_REG_START                        0x00460800
+#define BCHP_PCIE_0_RC_TL_REG_END                          0x00460998
+#define BCHP_PCIE_0_RC_DL_REG_START                        0x00461000
+#define BCHP_PCIE_0_RC_DL_REG_END                          0x00461424
+#define BCHP_PCIE_0_RC_PL_REG_START                        0x00461800
+#define BCHP_PCIE_0_RC_PL_REG_END                          0x00461e1c
+#define BCHP_PCIE_0_EP_CFG_TYPE0_REG_START                 0x00462000
+#define BCHP_PCIE_0_EP_CFG_TYPE0_REG_END                   0x0046203c
+#define BCHP_PCIE_0_EP_CFG_PM_REG_START                    0x00462048
+#define BCHP_PCIE_0_EP_CFG_PM_REG_END                      0x0046204c
+#define BCHP_PCIE_0_EP_CFG_VPD_REG_START                   0x00462050
+#define BCHP_PCIE_0_EP_CFG_VPD_REG_END                     0x00462054
+#define BCHP_PCIE_0_EP_CFG_MSI_REG_START                   0x00462058
+#define BCHP_PCIE_0_EP_CFG_MSI_REG_END                     0x00462064
+#define BCHP_PCIE_0_EP_CFG_MSIX_REG_START                  0x004620a0
+#define BCHP_PCIE_0_EP_CFG_MSIX_REG_END                    0x004620a8
+#define BCHP_PCIE_0_EP_CFG_PCIE_REG_START                  0x004620ac
+#define BCHP_PCIE_0_EP_CFG_PCIE_REG_END                    0x004620e4
+#define BCHP_PCIE_0_EP_CFG_AER_REG_START                   0x00462100
+#define BCHP_PCIE_0_EP_CFG_AER_REG_END                     0x00462134
+#define BCHP_PCIE_0_EP_CFG_DEV_REG_START                   0x0046213c
+#define BCHP_PCIE_0_EP_CFG_DEV_REG_END                     0x00462144
+#define BCHP_PCIE_0_EP_CFG_PB_REG_START                    0x00462150
+#define BCHP_PCIE_0_EP_CFG_PB_REG_END                      0x0046215c
+#define BCHP_PCIE_0_EP_CFG_VC_REG_START                    0x00462160
+#define BCHP_PCIE_0_EP_CFG_VC_REG_END                      0x00462178
+#define BCHP_PCIE_0_EP_CFG_VENDOR_REG_START                0x00462180
+#define BCHP_PCIE_0_EP_CFG_VENDOR_REG_END                  0x004621a4
+#define BCHP_PCIE_0_EP_CFG_PRIV0_REG_START                 0x00462404
+#define BCHP_PCIE_0_EP_CFG_PRIV0_REG_END                   0x00462418
+#define BCHP_PCIE_0_EP_CFG_PRIV1_REG_START                 0x00462428
+#define BCHP_PCIE_0_EP_CFG_PRIV1_REG_END                   0x00462630
+#define BCHP_PCIE_0_EP_TL_REG_START                        0x00462800
+#define BCHP_PCIE_0_EP_TL_REG_END                          0x00462998
+#define BCHP_PCIE_0_EP_DL_REG_START                        0x00463000
+#define BCHP_PCIE_0_EP_DL_REG_END                          0x00463424
+#define BCHP_PCIE_0_EP_PL_REG_START                        0x00463800
+#define BCHP_PCIE_0_EP_PL_REG_END                          0x00463e1c
+#define BCHP_PCIE_0_MISC_REG_START                         0x00464000
+#define BCHP_PCIE_0_MISC_REG_END                           0x004640c4
+#define BCHP_PCIE_0_MISC_PERST_REG_START                   0x00464100
+#define BCHP_PCIE_0_MISC_PERST_REG_END                     0x00464104
+#define BCHP_PCIE_0_MISC_HARD_REG_START                    0x00464200
+#define BCHP_PCIE_0_MISC_HARD_REG_END                      0x00464204
+#define BCHP_PCIE_0_INTR2_REG_START                        0x00464300
+#define BCHP_PCIE_0_INTR2_REG_END                          0x0046432c
+#define BCHP_PCIE_0_DMA_REG_START                          0x00464400
+#define BCHP_PCIE_0_DMA_REG_END                            0x0046446c
+#define BCHP_PCIE_0_EXT_CFG_REG_START                      0x00468000
+#define BCHP_PCIE_0_EXT_CFG_REG_END                        0x00469008
+#define BCHP_PCIE_0_RGR1_REG_START                         0x00469200
+#define BCHP_PCIE_0_RGR1_REG_END                           0x00469210
+#define BCHP_PCIE_0_RG_REG_START                           0x00469300
+#define BCHP_PCIE_0_RG_REG_END                             0x0046930c
+#define BCHP_USB_CAPS_REG_START                            0x00470000
+#define BCHP_USB_CAPS_REG_END                              0x0047002c
+#define BCHP_USB_GR_BRIDGE_REG_START                       0x00470100
+#define BCHP_USB_GR_BRIDGE_REG_END                         0x0047010c
+#define BCHP_USB_INTR2_REG_START                           0x00470180
+#define BCHP_USB_INTR2_REG_END                             0x004701ac
+#define BCHP_USB_CTRL_REG_START                            0x00470200
+#define BCHP_USB_CTRL_REG_END                              0x00470274
+#define BCHP_USB_EHCI_REG_START                            0x00470300
+#define BCHP_USB_EHCI_REG_END                              0x004703a4
+#define BCHP_USB_OHCI_REG_START                            0x00470400
+#define BCHP_USB_OHCI_REG_END                              0x00470454
+#define BCHP_USB_EHCI1_REG_START                           0x00470500
+#define BCHP_USB_EHCI1_REG_END                             0x004705a4
+#define BCHP_USB_OHCI1_REG_START                           0x00470600
+#define BCHP_USB_OHCI1_REG_END                             0x00470654
+#define BCHP_USB_XHCI_REG_START                            0x00471000
+#define BCHP_USB_XHCI_REG_END                              0x004718c4
+#define BCHP_USB_XHCI_EC_REG_START                         0x00471940
+#define BCHP_USB_XHCI_EC_REG_END                           0x00471fc0
+#define BCHP_USB1_CAPS_REG_START                           0x00480000
+#define BCHP_USB1_CAPS_REG_END                             0x0048002c
+#define BCHP_USB1_GR_BRIDGE_REG_START                      0x00480100
+#define BCHP_USB1_GR_BRIDGE_REG_END                        0x0048010c
+#define BCHP_USB1_INTR2_REG_START                          0x00480180
+#define BCHP_USB1_INTR2_REG_END                            0x004801ac
+#define BCHP_USB1_CTRL_REG_START                           0x00480200
+#define BCHP_USB1_CTRL_REG_END                             0x00480274
+#define BCHP_USB1_EHCI_REG_START                           0x00480300
+#define BCHP_USB1_EHCI_REG_END                             0x004803a4
+#define BCHP_USB1_OHCI_REG_START                           0x00480400
+#define BCHP_USB1_OHCI_REG_END                             0x00480454
+#define BCHP_USB1_EHCI1_REG_START                          0x00480500
+#define BCHP_USB1_EHCI1_REG_END                            0x004805a4
+#define BCHP_USB1_OHCI1_REG_START                          0x00480600
+#define BCHP_USB1_OHCI1_REG_END                            0x00480654
+#define BCHP_AVS_CPU_PROG_MEM_REG_START                    0x004c0000
+#define BCHP_AVS_CPU_PROG_MEM_REG_END                      0x004c2ffc
+#define BCHP_AVS_CPU_DATA_MEM_REG_START                    0x004c4000
+#define BCHP_AVS_CPU_DATA_MEM_REG_END                      0x004c4bfc
+#define BCHP_AVS_CPU_CORE_REGS_REG_START                   0x004c8000
+#define BCHP_AVS_CPU_CORE_REGS_REG_END                     0x004c80fc
+#define BCHP_AVS_CPU_AUX_REGS_REG_START                    0x004ca000
+#define BCHP_AVS_CPU_AUX_REGS_REG_END                      0x004cb058
+#define BCHP_AVS_UART_REG_START                            0x004d0000
+#define BCHP_AVS_UART_REG_END                              0x004d0ffc
+#define BCHP_AVS_CPU_L2_REG_START                          0x004d1100
+#define BCHP_AVS_CPU_L2_REG_END                            0x004d112c
+#define BCHP_AVS_HOST_L2_REG_START                         0x004d1200
+#define BCHP_AVS_HOST_L2_REG_END                           0x004d122c
+#define BCHP_AVS_CPU_CTRL_REG_START                        0x004d1300
+#define BCHP_AVS_CPU_CTRL_REG_END                          0x004d1330
+#define BCHP_AVS_BSTI_REG_START                            0x004d1400
+#define BCHP_AVS_BSTI_REG_END                              0x004d1404
+#define BCHP_AVS_TOP_CTRL_REG_START                        0x004d1500
+#define BCHP_AVS_TOP_CTRL_REG_END                          0x004d15b0
+#define BCHP_AVS_HW_MNTR_REG_START                         0x004d2000
+#define BCHP_AVS_HW_MNTR_REG_END                           0x004d20c8
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_START                 0x004d2100
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_END                   0x004d2124
+#define BCHP_AVS_RO_REGISTERS_0_REG_START                  0x004d2200
+#define BCHP_AVS_RO_REGISTERS_0_REG_END                    0x004d22e0
+#define BCHP_AVS_RO_REGISTERS_1_REG_START                  0x004d2800
+#define BCHP_AVS_RO_REGISTERS_1_REG_END                    0x004d28fc
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_START                0x004d2d00
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_END                  0x004d2dfc
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_START                0x004d2e00
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_END                  0x004d2efc
+#define BCHP_AVS_PMB_S_000_REG_START                       0x004d4000
+#define BCHP_AVS_PMB_S_000_REG_END                         0x004d4024
+#define BCHP_AVS_PMB_S_001_REG_START                       0x004d4040
+#define BCHP_AVS_PMB_S_001_REG_END                         0x004d4064
+#define BCHP_AVS_PMB_S_002_REG_START                       0x004d4080
+#define BCHP_AVS_PMB_S_002_REG_END                         0x004d40a4
+#define BCHP_AVS_PMB_S_003_REG_START                       0x004d40c0
+#define BCHP_AVS_PMB_S_003_REG_END                         0x004d40e4
+#define BCHP_AVS_PMB_S_004_REG_START                       0x004d4100
+#define BCHP_AVS_PMB_S_004_REG_END                         0x004d4124
+#define BCHP_AVS_PMB_S_005_REG_START                       0x004d4140
+#define BCHP_AVS_PMB_S_005_REG_END                         0x004d4164
+#define BCHP_AVS_PMB_S_006_REG_START                       0x004d4180
+#define BCHP_AVS_PMB_S_006_REG_END                         0x004d41a4
+#define BCHP_AVS_PMB_S_007_REG_START                       0x004d41c0
+#define BCHP_AVS_PMB_S_007_REG_END                         0x004d41e4
+#define BCHP_AVS_PMB_S_008_REG_START                       0x004d4200
+#define BCHP_AVS_PMB_S_008_REG_END                         0x004d4224
+#define BCHP_AVS_PMB_S_009_REG_START                       0x004d4240
+#define BCHP_AVS_PMB_S_009_REG_END                         0x004d4264
+#define BCHP_AVS_PMB_S_010_REG_START                       0x004d4280
+#define BCHP_AVS_PMB_S_010_REG_END                         0x004d42a4
+#define BCHP_AVS_PMB_S_011_REG_START                       0x004d42c0
+#define BCHP_AVS_PMB_S_011_REG_END                         0x004d42e4
+#define BCHP_AVS_PMB_S_012_REG_START                       0x004d4300
+#define BCHP_AVS_PMB_S_012_REG_END                         0x004d4324
+#define BCHP_AVS_PMB_S_013_REG_START                       0x004d4340
+#define BCHP_AVS_PMB_S_013_REG_END                         0x004d4364
+#define BCHP_AVS_PMB_S_014_REG_START                       0x004d4380
+#define BCHP_AVS_PMB_S_014_REG_END                         0x004d43a4
+#define BCHP_AVS_PMB_S_015_REG_START                       0x004d43c0
+#define BCHP_AVS_PMB_S_015_REG_END                         0x004d43e4
+#define BCHP_AVS_PMB_S_016_REG_START                       0x004d4400
+#define BCHP_AVS_PMB_S_016_REG_END                         0x004d4424
+#define BCHP_AVS_PMB_S_017_REG_START                       0x004d4440
+#define BCHP_AVS_PMB_S_017_REG_END                         0x004d4464
+#define BCHP_AVS_PMB_S_018_REG_START                       0x004d4480
+#define BCHP_AVS_PMB_S_018_REG_END                         0x004d44a4
+#define BCHP_AVS_PMB_S_019_REG_START                       0x004d44c0
+#define BCHP_AVS_PMB_S_019_REG_END                         0x004d44e4
+#define BCHP_AVS_PMB_S_020_REG_START                       0x004d4500
+#define BCHP_AVS_PMB_S_020_REG_END                         0x004d4524
+#define BCHP_AVS_PMB_S_021_REG_START                       0x004d4540
+#define BCHP_AVS_PMB_S_021_REG_END                         0x004d4564
+#define BCHP_AVS_PMB_S_022_REG_START                       0x004d4580
+#define BCHP_AVS_PMB_S_022_REG_END                         0x004d45a4
+#define BCHP_AVS_PMB_S_023_REG_START                       0x004d45c0
+#define BCHP_AVS_PMB_S_023_REG_END                         0x004d45e4
+#define BCHP_AVS_PMB_S_024_REG_START                       0x004d4600
+#define BCHP_AVS_PMB_S_024_REG_END                         0x004d4624
+#define BCHP_AVS_PMB_S_025_REG_START                       0x004d4640
+#define BCHP_AVS_PMB_S_025_REG_END                         0x004d4664
+#define BCHP_AVS_PMB_S_026_REG_START                       0x004d4680
+#define BCHP_AVS_PMB_S_026_REG_END                         0x004d46a4
+#define BCHP_AVS_PMB_S_027_REG_START                       0x004d46c0
+#define BCHP_AVS_PMB_S_027_REG_END                         0x004d46e4
+#define BCHP_AVS_PMB_REGISTERS_REG_START                   0x004d6000
+#define BCHP_AVS_PMB_REGISTERS_REG_END                     0x004d6008
+#define BCHP_CLKGEN_REG_START                              0x004e0000
+#define BCHP_CLKGEN_REG_END                                0x004e0710
+#define BCHP_VCXO_0_RM_REG_START                           0x004e2800
+#define BCHP_VCXO_0_RM_REG_END                             0x004e282c
+#define BCHP_VCXO_1_RM_REG_START                           0x004e2880
+#define BCHP_VCXO_1_RM_REG_END                             0x004e28ac
+#define BCHP_VCXO_2_RM_REG_START                           0x004e2900
+#define BCHP_VCXO_2_RM_REG_END                             0x004e292c
+#define BCHP_CLKGEN_GR_REG_START                           0x004e3000
+#define BCHP_CLKGEN_GR_REG_END                             0x004e300c
+#define BCHP_CLKGEN_INTR2_REG_START                        0x004e4000
+#define BCHP_CLKGEN_INTR2_REG_END                          0x004e4044
+#define BCHP_AVS_RANGE_BLOCKER_REG_START                   0x004e5000
+#define BCHP_AVS_RANGE_BLOCKER_REG_END                     0x004e5054
+#define BCHP_PROD_OTP_GRB_REG_START                        0x004e6000
+#define BCHP_PROD_OTP_GRB_REG_END                          0x004e600c
+#define BCHP_JTAG_OTP_REG_START                            0x004e6100
+#define BCHP_JTAG_OTP_REG_END                              0x004e6138
+#define BCHP_MFD_0_REG_START                               0x00600000
+#define BCHP_MFD_0_REG_END                                 0x00600264
+#define BCHP_MFD_1_REG_START                               0x00600400
+#define BCHP_MFD_1_REG_END                                 0x006005fc
+#define BCHP_MFD_2_REG_START                               0x00600800
+#define BCHP_MFD_2_REG_END                                 0x006009fc
+#define BCHP_MFD_3_REG_START                               0x00600c00
+#define BCHP_MFD_3_REG_END                                 0x00600dfc
+#define BCHP_MFD_4_REG_START                               0x00601000
+#define BCHP_MFD_4_REG_END                                 0x006011fc
+#define BCHP_MFD_5_REG_START                               0x00601400
+#define BCHP_MFD_5_REG_END                                 0x006015fc
+#define BCHP_VFD_0_REG_START                               0x00602000
+#define BCHP_VFD_0_REG_END                                 0x006021fc
+#define BCHP_VFD_1_REG_START                               0x00602200
+#define BCHP_VFD_1_REG_END                                 0x006023fc
+#define BCHP_VFD_2_REG_START                               0x00602400
+#define BCHP_VFD_2_REG_END                                 0x006025fc
+#define BCHP_VFD_3_REG_START                               0x00602600
+#define BCHP_VFD_3_REG_END                                 0x006027fc
+#define BCHP_VFD_4_REG_START                               0x00602800
+#define BCHP_VFD_4_REG_END                                 0x006029fc
+#define BCHP_VFD_5_REG_START                               0x00602a00
+#define BCHP_VFD_5_REG_END                                 0x00602bfc
+#define BCHP_VFD_6_REG_START                               0x00602c00
+#define BCHP_VFD_6_REG_END                                 0x00602dfc
+#define BCHP_VFD_7_REG_START                               0x00602e00
+#define BCHP_VFD_7_REG_END                                 0x00602ffc
+#define BCHP_RDC_REG_START                                 0x00603000
+#define BCHP_RDC_REG_END                                   0x00603cfc
+#define BCHP_BVNF_INTR2_0_REG_START                        0x00604000
+#define BCHP_BVNF_INTR2_0_REG_END                          0x0060402c
+#define BCHP_BVNF_INTR2_1_REG_START                        0x00604100
+#define BCHP_BVNF_INTR2_1_REG_END                          0x0060412c
+#define BCHP_BVNF_INTR2_3_REG_START                        0x00604300
+#define BCHP_BVNF_INTR2_3_REG_END                          0x00604344
+#define BCHP_BVNF_INTR2_4_REG_START                        0x00604400
+#define BCHP_BVNF_INTR2_4_REG_END                          0x00604444
+#define BCHP_BVNF_INTR2_5_REG_START                        0x00604500
+#define BCHP_BVNF_INTR2_5_REG_END                          0x0060452c
+#define BCHP_BVNF_INTR2_6_REG_START                        0x00604600
+#define BCHP_BVNF_INTR2_6_REG_END                          0x0060462c
+#define BCHP_BVNF_INTR2_7_REG_START                        0x00604700
+#define BCHP_BVNF_INTR2_7_REG_END                          0x0060472c
+#define BCHP_BVNF_INTR2_8_REG_START                        0x00604800
+#define BCHP_BVNF_INTR2_8_REG_END                          0x0060482c
+#define BCHP_BVNF_INTR2_9_REG_START                        0x00604900
+#define BCHP_BVNF_INTR2_9_REG_END                          0x0060492c
+#define BCHP_BVNF_INTR2_11_REG_START                       0x00604b00
+#define BCHP_BVNF_INTR2_11_REG_END                         0x00604b44
+#define BCHP_BVNF_INTR2_12_REG_START                       0x00604c00
+#define BCHP_BVNF_INTR2_12_REG_END                         0x00604c44
+#define BCHP_BVNF_INTR2_14_REG_START                       0x00604e00
+#define BCHP_BVNF_INTR2_14_REG_END                         0x00604e2c
+#define BCHP_BVNF_INTR2_15_REG_START                       0x00604f00
+#define BCHP_BVNF_INTR2_15_REG_END                         0x00604f2c
+#define BCHP_FMISC_REG_START                               0x00605000
+#define BCHP_FMISC_REG_END                                 0x00605020
+#define BCHP_SCL_0_REG_START                               0x00620000
+#define BCHP_SCL_0_REG_END                                 0x006203fc
+#define BCHP_SCL_1_REG_START                               0x00620400
+#define BCHP_SCL_1_REG_END                                 0x006207fc
+#define BCHP_SCL_2_REG_START                               0x00620800
+#define BCHP_SCL_2_REG_END                                 0x00620bfc
+#define BCHP_SCL_3_REG_START                               0x00620c00
+#define BCHP_SCL_3_REG_END                                 0x00620ffc
+#define BCHP_SCL_4_REG_START                               0x00621000
+#define BCHP_SCL_4_REG_END                                 0x006213fc
+#define BCHP_SCL_5_REG_START                               0x00621400
+#define BCHP_SCL_5_REG_END                                 0x006217fc
+#define BCHP_SCL_6_REG_START                               0x00621800
+#define BCHP_SCL_6_REG_END                                 0x00621bfc
+#define BCHP_SCL_7_REG_START                               0x00621c00
+#define BCHP_SCL_7_REG_END                                 0x00621ffc
+#define BCHP_VNET_F_REG_START                              0x00622000
+#define BCHP_VNET_F_REG_END                                0x006221fc
+#define BCHP_VNET_B_REG_START                              0x00622200
+#define BCHP_VNET_B_REG_END                                0x006223fc
+#define BCHP_MMISC_REG_START                               0x00622800
+#define BCHP_MMISC_REG_END                                 0x00622828
+#define BCHP_LBOX_0_REG_START                              0x00624000
+#define BCHP_LBOX_0_REG_END                                0x00624070
+#define BCHP_LBOX_1_REG_START                              0x00624200
+#define BCHP_LBOX_1_REG_END                                0x00624270
+#define BCHP_LBOX_2_REG_START                              0x00624400
+#define BCHP_LBOX_2_REG_END                                0x00624470
+#define BCHP_LBOX_3_REG_START                              0x00624600
+#define BCHP_LBOX_3_REG_END                                0x00624670
+#define BCHP_LBOX_4_REG_START                              0x00624800
+#define BCHP_LBOX_4_REG_END                                0x00624870
+#define BCHP_LBOX_5_REG_START                              0x00624a00
+#define BCHP_LBOX_5_REG_END                                0x00624a70
+#define BCHP_DNR_0_REG_START                               0x00626000
+#define BCHP_DNR_0_REG_END                                 0x006260a4
+#define BCHP_DNR_1_REG_START                               0x00626200
+#define BCHP_DNR_1_REG_END                                 0x006262a4
+#define BCHP_DNR_2_REG_START                               0x00626400
+#define BCHP_DNR_2_REG_END                                 0x006264a4
+#define BCHP_DNR_3_REG_START                               0x00626600
+#define BCHP_DNR_3_REG_END                                 0x006266a4
+#define BCHP_DNR_4_REG_START                               0x00626800
+#define BCHP_DNR_4_REG_END                                 0x006268a4
+#define BCHP_BVNM_INTR2_0_REG_START                        0x00627000
+#define BCHP_BVNM_INTR2_0_REG_END                          0x0062702c
+#define BCHP_BVNM_INTR2_1_REG_START                        0x00627100
+#define BCHP_BVNM_INTR2_1_REG_END                          0x0062712c
+#define BCHP_CAP_0_REG_START                               0x00640000
+#define BCHP_CAP_0_REG_END                                 0x0064007c
+#define BCHP_CAP_1_REG_START                               0x00640200
+#define BCHP_CAP_1_REG_END                                 0x0064027c
+#define BCHP_CAP_2_REG_START                               0x00640400
+#define BCHP_CAP_2_REG_END                                 0x0064047c
+#define BCHP_CAP_3_REG_START                               0x00640600
+#define BCHP_CAP_3_REG_END                                 0x0064067c
+#define BCHP_CAP_4_REG_START                               0x00640800
+#define BCHP_CAP_4_REG_END                                 0x0064087c
+#define BCHP_CAP_5_REG_START                               0x00640a00
+#define BCHP_CAP_5_REG_END                                 0x00640a7c
+#define BCHP_CAP_6_REG_START                               0x00640c00
+#define BCHP_CAP_6_REG_END                                 0x00640c7c
+#define BCHP_CAP_7_REG_START                               0x00640e00
+#define BCHP_CAP_7_REG_END                                 0x00640e7c
+#define BCHP_GFD_0_REG_START                               0x00641000
+#define BCHP_GFD_0_REG_END                                 0x0064122c
+#define BCHP_GFD_1_REG_START                               0x00641400
+#define BCHP_GFD_1_REG_END                                 0x0064162c
+#define BCHP_GFD_2_REG_START                               0x00641800
+#define BCHP_GFD_2_REG_END                                 0x00641a2c
+#define BCHP_GFD_3_REG_START                               0x00641c00
+#define BCHP_GFD_3_REG_END                                 0x00641e2c
+#define BCHP_GFD_4_REG_START                               0x00642000
+#define BCHP_GFD_4_REG_END                                 0x0064222c
+#define BCHP_GFD_5_REG_START                               0x00642400
+#define BCHP_GFD_5_REG_END                                 0x0064262c
+#define BCHP_GFD_6_REG_START                               0x00642800
+#define BCHP_GFD_6_REG_END                                 0x00642a2c
+#define BCHP_CMP_0_REG_START                               0x00643000
+#define BCHP_CMP_0_REG_END                                 0x006434b4
+#define BCHP_CMP_1_REG_START                               0x00643800
+#define BCHP_CMP_1_REG_END                                 0x00643cb4
+#define BCHP_CMP_2_REG_START                               0x00644000
+#define BCHP_CMP_2_REG_END                                 0x00644264
+#define BCHP_CMP_3_REG_START                               0x00644400
+#define BCHP_CMP_3_REG_END                                 0x00644664
+#define BCHP_CMP_4_REG_START                               0x00644800
+#define BCHP_CMP_4_REG_END                                 0x00644a64
+#define BCHP_CMP_5_REG_START                               0x00644c00
+#define BCHP_CMP_5_REG_END                                 0x00644e64
+#define BCHP_CMP_6_REG_START                               0x00645000
+#define BCHP_CMP_6_REG_END                                 0x00645264
+#define BCHP_TNT_CMP_0_V0_REG_START                        0x00645800
+#define BCHP_TNT_CMP_0_V0_REG_END                          0x006458a4
+#define BCHP_MASK_0_REG_START                              0x00645c00
+#define BCHP_MASK_0_REG_END                                0x00645c20
+#define BCHP_PEP_CMP_0_V0_REG_START                        0x00646000
+#define BCHP_PEP_CMP_0_V0_REG_END                          0x00647484
+#define BCHP_BVNB_INTR2_REG_START                          0x00648000
+#define BCHP_BVNB_INTR2_REG_END                            0x0064802c
+#define BCHP_BVNB_INTR2_1_REG_START                        0x00648100
+#define BCHP_BVNB_INTR2_1_REG_END                          0x0064812c
+#define BCHP_BMISC_REG_START                               0x00648400
+#define BCHP_BMISC_REG_END                                 0x0064841c
+#define BCHP_MVP_TOP_0_REG_START                           0x00660000
+#define BCHP_MVP_TOP_0_REG_END                             0x0066002c
+#define BCHP_SIOB_0_REG_START                              0x00660200
+#define BCHP_SIOB_0_REG_END                                0x006602fc
+#define BCHP_HSCL_0_REG_START                              0x00660400
+#define BCHP_HSCL_0_REG_END                                0x006607fc
+#define BCHP_HD_ANR_MCTF_0_REG_START                       0x00661000
+#define BCHP_HD_ANR_MCTF_0_REG_END                         0x0066127c
+#define BCHP_HD_ANR_AND_0_REG_START                        0x00661800
+#define BCHP_HD_ANR_AND_0_REG_END                          0x00661888
+#define BCHP_MDI_TOP_0_REG_START                           0x00662000
+#define BCHP_MDI_TOP_0_REG_END                             0x006620fc
+#define BCHP_MDI_FCB_0_REG_START                           0x00662400
+#define BCHP_MDI_FCB_0_REG_END                             0x006627fc
+#define BCHP_MDI_PPB_0_REG_START                           0x00662800
+#define BCHP_MDI_PPB_0_REG_END                             0x00662bfc
+#define BCHP_MDI_FCN_0_REG_START                           0x00662c00
+#define BCHP_MDI_FCN_0_REG_END                             0x00662ffc
+#define BCHP_MVP_TOP_1_REG_START                           0x00670000
+#define BCHP_MVP_TOP_1_REG_END                             0x0067002c
+#define BCHP_SIOB_1_REG_START                              0x00670200
+#define BCHP_SIOB_1_REG_END                                0x006702fc
+#define BCHP_HSCL_1_REG_START                              0x00670400
+#define BCHP_HSCL_1_REG_END                                0x006707fc
+#define BCHP_MDI_TOP_1_REG_START                           0x00672000
+#define BCHP_MDI_TOP_1_REG_END                             0x006720fc
+#define BCHP_MDI_PPB_1_REG_START                           0x00672800
+#define BCHP_MDI_PPB_1_REG_END                             0x00672bfc
+#define BCHP_MDI_FCN_1_REG_START                           0x00672c00
+#define BCHP_MDI_FCN_1_REG_END                             0x00672ffc
+#define BCHP_MVP_TOP_2_REG_START                           0x00680000
+#define BCHP_MVP_TOP_2_REG_END                             0x0068002c
+#define BCHP_SIOB_2_REG_START                              0x00680200
+#define BCHP_SIOB_2_REG_END                                0x006802fc
+#define BCHP_HSCL_2_REG_START                              0x00680400
+#define BCHP_HSCL_2_REG_END                                0x006807fc
+#define BCHP_MDI_TOP_2_REG_START                           0x00682000
+#define BCHP_MDI_TOP_2_REG_END                             0x006820fc
+#define BCHP_MDI_PPB_2_REG_START                           0x00682800
+#define BCHP_MDI_PPB_2_REG_END                             0x00682bfc
+#define BCHP_MDI_FCN_2_REG_START                           0x00682c00
+#define BCHP_MDI_FCN_2_REG_END                             0x00682ffc
+#define BCHP_MVP_TOP_3_REG_START                           0x00690000
+#define BCHP_MVP_TOP_3_REG_END                             0x0069002c
+#define BCHP_SIOB_3_REG_START                              0x00690200
+#define BCHP_SIOB_3_REG_END                                0x006902fc
+#define BCHP_HSCL_3_REG_START                              0x00690400
+#define BCHP_HSCL_3_REG_END                                0x006907fc
+#define BCHP_MDI_TOP_3_REG_START                           0x00692000
+#define BCHP_MDI_TOP_3_REG_END                             0x006920fc
+#define BCHP_MDI_PPB_3_REG_START                           0x00692800
+#define BCHP_MDI_PPB_3_REG_END                             0x00692bfc
+#define BCHP_MDI_FCN_3_REG_START                           0x00692c00
+#define BCHP_MDI_FCN_3_REG_END                             0x00692ffc
+#define BCHP_MVP_TOP_4_REG_START                           0x006a0000
+#define BCHP_MVP_TOP_4_REG_END                             0x006a002c
+#define BCHP_SIOB_4_REG_START                              0x006a0200
+#define BCHP_SIOB_4_REG_END                                0x006a02fc
+#define BCHP_HSCL_4_REG_START                              0x006a0400
+#define BCHP_HSCL_4_REG_END                                0x006a07fc
+#define BCHP_MDI_TOP_4_REG_START                           0x006a2000
+#define BCHP_MDI_TOP_4_REG_END                             0x006a20fc
+#define BCHP_MDI_PPB_4_REG_START                           0x006a2800
+#define BCHP_MDI_PPB_4_REG_END                             0x006a2bfc
+#define BCHP_MDI_FCN_4_REG_START                           0x006a2c00
+#define BCHP_MDI_FCN_4_REG_END                             0x006a2ffc
+#define BCHP_MISC_REG_START                                0x006b0000
+#define BCHP_MISC_REG_END                                  0x006b00a8
+#define BCHP_IT_0_REG_START                                0x006b1000
+#define BCHP_IT_0_REG_END                                  0x006b17fc
+#define BCHP_IT_1_REG_START                                0x006b2000
+#define BCHP_IT_1_REG_END                                  0x006b27fc
+#define BCHP_VF_0_REG_START                                0x006b3000
+#define BCHP_VF_0_REG_END                                  0x006b3134
+#define BCHP_VF_1_REG_START                                0x006b3200
+#define BCHP_VF_1_REG_END                                  0x006b3334
+#define BCHP_SECAM_0_REG_START                             0x006b3400
+#define BCHP_SECAM_0_REG_END                               0x006b3414
+#define BCHP_SM_0_REG_START                                0x006b3480
+#define BCHP_SM_0_REG_END                                  0x006b34ac
+#define BCHP_SDSRC_0_REG_START                             0x006b3500
+#define BCHP_SDSRC_0_REG_END                               0x006b350c
+#define BCHP_HDSRC_0_REG_START                             0x006b3520
+#define BCHP_HDSRC_0_REG_END                               0x006b353c
+#define BCHP_CSC_0_REG_START                               0x006b3580
+#define BCHP_CSC_0_REG_END                                 0x006b35b0
+#define BCHP_CSC_1_REG_START                               0x006b3600
+#define BCHP_CSC_1_REG_END                                 0x006b3630
+#define BCHP_RM_0_REG_START                                0x006b3680
+#define BCHP_RM_0_REG_END                                  0x006b36a4
+#define BCHP_RM_1_REG_START                                0x006b36c0
+#define BCHP_RM_1_REG_END                                  0x006b36e4
+#define BCHP_ANA_DEBUG_0_REG_START                         0x006b3700
+#define BCHP_ANA_DEBUG_0_REG_END                           0x006b3744
+#define BCHP_DTRAM_0_REG_START                             0x006b3800
+#define BCHP_DTRAM_0_REG_END                               0x006b3e7c
+#define BCHP_DVI_DTG_0_REG_START                           0x006b4000
+#define BCHP_DVI_DTG_0_REG_END                             0x006b4178
+#define BCHP_DVI_DTG_RM_0_REG_START                        0x006b4800
+#define BCHP_DVI_DTG_RM_0_REG_END                          0x006b4824
+#define BCHP_DVI_CSC_0_REG_START                           0x006b4900
+#define BCHP_DVI_CSC_0_REG_END                             0x006b4930
+#define BCHP_DVI_DVF_0_REG_START                           0x006b4a00
+#define BCHP_DVI_DVF_0_REG_END                             0x006b4a18
+#define BCHP_DVI_DEBUG_0_REG_START                         0x006b4b00
+#define BCHP_DVI_DEBUG_0_REG_END                           0x006b4b44
+#define BCHP_ITU656_DTG_0_REG_START                        0x006b5000
+#define BCHP_ITU656_DTG_0_REG_END                          0x006b5178
+#define BCHP_ITU656_CSC_0_REG_START                        0x006b5200
+#define BCHP_ITU656_CSC_0_REG_END                          0x006b5230
+#define BCHP_ITU656_DVF_0_REG_START                        0x006b5300
+#define BCHP_ITU656_DVF_0_REG_END                          0x006b5318
+#define BCHP_ITU656_0_REG_START                            0x006b5400
+#define BCHP_ITU656_0_REG_END                              0x006b5420
+#define BCHP_VEC_CFG_REG_START                             0x006b5800
+#define BCHP_VEC_CFG_REG_END                               0x006b5984
+#define BCHP_VIDEO_ENC_INTR2_REG_START                     0x006b5c00
+#define BCHP_VIDEO_ENC_INTR2_REG_END                       0x006b5c2c
+#define BCHP_VIDEO_ENC_TPG_0_REG_START                     0x006b5d00
+#define BCHP_VIDEO_ENC_TPG_0_REG_END                       0x006b5d18
+#define BCHP_VIDEO_ENC_STG_0_REG_START                     0x006b5e00
+#define BCHP_VIDEO_ENC_STG_0_REG_END                       0x006b5e48
+#define BCHP_VIDEO_ENC_STG_1_REG_START                     0x006b5f00
+#define BCHP_VIDEO_ENC_STG_1_REG_END                       0x006b5f48
+#define BCHP_VIDEO_ENC_STG_2_REG_START                     0x006b6000
+#define BCHP_VIDEO_ENC_STG_2_REG_END                       0x006b6048
+#define BCHP_VIDEO_ENC_STG_3_REG_START                     0x006b6100
+#define BCHP_VIDEO_ENC_STG_3_REG_END                       0x006b6148
+#define BCHP_VIDEO_ENC_DECIM_0_REG_START                   0x006b6200
+#define BCHP_VIDEO_ENC_DECIM_0_REG_END                     0x006b6208
+#define BCHP_DVP_TVG_0_REG_START                           0x006b6300
+#define BCHP_DVP_TVG_0_REG_END                             0x006b6388
+#define BCHP_VBI_ENC_REG_START                             0x006b8000
+#define BCHP_VBI_ENC_REG_END                               0x006b8074
+#define BCHP_CCE_0_REG_START                               0x006b8400
+#define BCHP_CCE_0_REG_END                                 0x006b8458
+#define BCHP_CCE_1_REG_START                               0x006b8500
+#define BCHP_CCE_1_REG_END                                 0x006b8558
+#define BCHP_WSE_0_REG_START                               0x006b8600
+#define BCHP_WSE_0_REG_END                                 0x006b8614
+#define BCHP_WSE_1_REG_START                               0x006b8700
+#define BCHP_WSE_1_REG_END                                 0x006b8714
+#define BCHP_CGMSAE_0_REG_START                            0x006b8800
+#define BCHP_CGMSAE_0_REG_END                              0x006b8858
+#define BCHP_CGMSAE_1_REG_START                            0x006b8900
+#define BCHP_CGMSAE_1_REG_END                              0x006b8958
+#define BCHP_TTE_0_REG_START                               0x006b8a00
+#define BCHP_TTE_0_REG_END                                 0x006b8a28
+#define BCHP_TTE_1_REG_START                               0x006b8b00
+#define BCHP_TTE_1_REG_END                                 0x006b8b28
+#define BCHP_GSE_0_REG_START                               0x006b8c00
+#define BCHP_GSE_0_REG_END                                 0x006b8c80
+#define BCHP_GSE_1_REG_START                               0x006b8d00
+#define BCHP_GSE_1_REG_END                                 0x006b8d80
+#define BCHP_AMOLE_0_REG_START                             0x006b8e00
+#define BCHP_AMOLE_0_REG_END                               0x006b8e8c
+#define BCHP_AMOLE_1_REG_START                             0x006b8f00
+#define BCHP_AMOLE_1_REG_END                               0x006b8f8c
+#define BCHP_CCE_ANCIL_0_REG_START                         0x006b9000
+#define BCHP_CCE_ANCIL_0_REG_END                           0x006b9054
+#define BCHP_WSE_ANCIL_0_REG_START                         0x006b9100
+#define BCHP_WSE_ANCIL_0_REG_END                           0x006b910c
+#define BCHP_TTE_ANCIL_0_REG_START                         0x006b9200
+#define BCHP_TTE_ANCIL_0_REG_END                           0x006b9228
+#define BCHP_GSE_ANCIL_0_REG_START                         0x006b9300
+#define BCHP_GSE_ANCIL_0_REG_END                           0x006b9380
+#define BCHP_AMOLE_ANCIL_0_REG_START                       0x006b9400
+#define BCHP_AMOLE_ANCIL_0_REG_END                         0x006b948c
+#define BCHP_ANCI656_ANCIL_0_REG_START                     0x006b9500
+#define BCHP_ANCI656_ANCIL_0_REG_END                       0x006b9524
+#define BCHP_DVP_HR_REG_START                              0x006c0000
+#define BCHP_DVP_HR_REG_END                                0x006c03fc
+#define BCHP_DVP_HR_INTR2_REG_START                        0x006c0400
+#define BCHP_DVP_HR_INTR2_REG_END                          0x006c042c
+#define BCHP_DVP_HR_KEY_RAM_REG_START                      0x006c0600
+#define BCHP_DVP_HR_KEY_RAM_REG_END                        0x006c0614
+#define BCHP_HDMI_RX_FE_SHARED_REG_START                   0x006c0800
+#define BCHP_HDMI_RX_FE_SHARED_REG_END                     0x006c090c
+#define BCHP_HDMI_RX_SHARED_REG_START                      0x006c0c00
+#define BCHP_HDMI_RX_SHARED_REG_END                        0x006c0c24
+#define BCHP_HDMI_RX_FE_0_REG_START                        0x006c1000
+#define BCHP_HDMI_RX_FE_0_REG_END                          0x006c11fc
+#define BCHP_HDMI_RX_EQ_0_REG_START                        0x006c1200
+#define BCHP_HDMI_RX_EQ_0_REG_END                          0x006c13fc
+#define BCHP_HDMI_RX_0_REG_START                           0x006c2000
+#define BCHP_HDMI_RX_0_REG_END                             0x006c27bc
+#define BCHP_HDMI_RX_INTR2_0_REG_START                     0x006c27c0
+#define BCHP_HDMI_RX_INTR2_0_REG_END                       0x006c27ec
+#define BCHP_HD_DVI_0_REG_START                            0x006c4000
+#define BCHP_HD_DVI_0_REG_END                              0x006c41fc
+#define BCHP_DVP_HR_TMR_REG_START                          0x006c4cc0
+#define BCHP_DVP_HR_TMR_REG_END                            0x006c4cfc
+#define BCHP_DVP_HT_REG_START                              0x006c8000
+#define BCHP_DVP_HT_REG_END                                0x006c8118
+#define BCHP_HDMI_REG_START                                0x006c8800
+#define BCHP_HDMI_REG_END                                  0x006c8994
+#define BCHP_HDMI_TX_PHY_REG_START                         0x006c8a80
+#define BCHP_HDMI_TX_PHY_REG_END                           0x006c8ae0
+#define BCHP_HDMI_RM_REG_START                             0x006c8b00
+#define BCHP_HDMI_RM_REG_END                               0x006c8b2c
+#define BCHP_HDMI_TX_INTR2_REG_START                       0x006c8b40
+#define BCHP_HDMI_TX_INTR2_REG_END                         0x006c8b6c
+#define BCHP_HDMI_RAM_REG_START                            0x006c8c00
+#define BCHP_HDMI_RAM_REG_END                              0x006c8dfc
+#define BCHP_BVN_RGR_REG_START                             0x006ce000
+#define BCHP_BVN_RGR_REG_END                               0x006ce010
+#define BCHP_VICE2_CME_0_0_REG_START                       0x00700800
+#define BCHP_VICE2_CME_0_0_REG_END                         0x007008a0
+#define BCHP_VICE2_FME_0_0_REG_START                       0x00700c00
+#define BCHP_VICE2_FME_0_0_REG_END                         0x00700c88
+#define BCHP_VICE2_MC_0_0_REG_START                        0x00701000
+#define BCHP_VICE2_MC_0_0_REG_END                          0x0070108c
+#define BCHP_VICE2_MAU_0_0_REG_START                       0x00701400
+#define BCHP_VICE2_MAU_0_0_REG_END                         0x00701510
+#define BCHP_VICE2_IMD_0_0_REG_START                       0x00701800
+#define BCHP_VICE2_IMD_0_0_REG_END                         0x0070187c
+#define BCHP_VICE2_CABAC_0_0_REG_START                     0x00701c00
+#define BCHP_VICE2_CABAC_0_0_REG_END                       0x00701dec
+#define BCHP_VICE2_HA_0_0_REG_START                        0x00702000
+#define BCHP_VICE2_HA_0_0_REG_END                          0x0070208c
+#define BCHP_VICE2_SG_0_0_REG_START                        0x00702400
+#define BCHP_VICE2_SG_0_0_REG_END                          0x007024ac
+#define BCHP_VICE2_DBLK_0_0_REG_START                      0x00702800
+#define BCHP_VICE2_DBLK_0_0_REG_END                        0x0070288c
+#define BCHP_VICE2_VIP_0_0_REG_START                       0x00703000
+#define BCHP_VICE2_VIP_0_0_REG_END                         0x00703224
+#define BCHP_VICE2_VIP1_0_0_REG_START                      0x00703800
+#define BCHP_VICE2_VIP1_0_0_REG_END                        0x00703a24
+#define BCHP_VICE2_XQ_0_0_REG_START                        0x00704000
+#define BCHP_VICE2_XQ_0_0_REG_END                          0x007054c8
+#define BCHP_VICE2_ARCSS_ESS_ADI_0_0_REG_START             0x00718000
+#define BCHP_VICE2_ARCSS_ESS_ADI_0_0_REG_END               0x007182b4
+#define BCHP_VICE2_ARCSS_ESS_CTRL_0_0_REG_START            0x00720000
+#define BCHP_VICE2_ARCSS_ESS_CTRL_0_0_REG_END              0x007200a4
+#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_0_0_REG_START      0x00720400
+#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_0_0_REG_END        0x0072042c
+#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_0_0_REG_START        0x00720600
+#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_0_0_REG_END          0x0072062c
+#define BCHP_VICE2_ARCSS_ESS_HOSTIF_0_0_REG_START          0x00722000
+#define BCHP_VICE2_ARCSS_ESS_HOSTIF_0_0_REG_END            0x007233fc
+#define BCHP_VICE2_ARCSS_ESS_DCCM_0_0_REG_START            0x00730000
+#define BCHP_VICE2_ARCSS_ESS_DCCM_0_0_REG_END              0x0073fffc
+#define BCHP_VICE2_ARCSS_ESS_ADI_1_0_REG_START             0x00758000
+#define BCHP_VICE2_ARCSS_ESS_ADI_1_0_REG_END               0x007582a8
+#define BCHP_VICE2_ARCSS_ESS_CTRL_1_0_REG_START            0x00760000
+#define BCHP_VICE2_ARCSS_ESS_CTRL_1_0_REG_END              0x007600a4
+#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_1_0_REG_START      0x00760400
+#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_1_0_REG_END        0x0076042c
+#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_1_0_REG_START        0x00760600
+#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_1_0_REG_END          0x0076062c
+#define BCHP_VICE2_ARCSS_ESS_HOSTIF_1_0_REG_START          0x00762000
+#define BCHP_VICE2_ARCSS_ESS_HOSTIF_1_0_REG_END            0x007633fc
+#define BCHP_VICE2_ARCSS_ESS_DCCM_1_0_REG_START            0x00770000
+#define BCHP_VICE2_ARCSS_ESS_DCCM_1_0_REG_END              0x0077fffc
+#define BCHP_VICE2_RGR_0_REG_START                         0x00780000
+#define BCHP_VICE2_RGR_0_REG_END                           0x0078000c
+#define BCHP_VICE2_MISC_0_REG_START                        0x00781000
+#define BCHP_VICE2_MISC_0_REG_END                          0x0078102c
+#define BCHP_VICE2_L2_0_REG_START                          0x00781100
+#define BCHP_VICE2_L2_0_REG_END                            0x0078112c
+#define BCHP_VICE2_ARCSS_MISC_0_REG_START                  0x00782000
+#define BCHP_VICE2_ARCSS_MISC_0_REG_END                    0x007820b8
+#define BCHP_VICE2_CME_0_1_REG_START                       0x00800800
+#define BCHP_VICE2_CME_0_1_REG_END                         0x008008a0
+#define BCHP_VICE2_FME_0_1_REG_START                       0x00800c00
+#define BCHP_VICE2_FME_0_1_REG_END                         0x00800c88
+#define BCHP_VICE2_MC_0_1_REG_START                        0x00801000
+#define BCHP_VICE2_MC_0_1_REG_END                          0x0080108c
+#define BCHP_VICE2_MAU_0_1_REG_START                       0x00801400
+#define BCHP_VICE2_MAU_0_1_REG_END                         0x00801510
+#define BCHP_VICE2_IMD_0_1_REG_START                       0x00801800
+#define BCHP_VICE2_IMD_0_1_REG_END                         0x0080187c
+#define BCHP_VICE2_CABAC_0_1_REG_START                     0x00801c00
+#define BCHP_VICE2_CABAC_0_1_REG_END                       0x00801dec
+#define BCHP_VICE2_HA_0_1_REG_START                        0x00802000
+#define BCHP_VICE2_HA_0_1_REG_END                          0x0080208c
+#define BCHP_VICE2_SG_0_1_REG_START                        0x00802400
+#define BCHP_VICE2_SG_0_1_REG_END                          0x008024ac
+#define BCHP_VICE2_DBLK_0_1_REG_START                      0x00802800
+#define BCHP_VICE2_DBLK_0_1_REG_END                        0x0080288c
+#define BCHP_VICE2_VIP_0_1_REG_START                       0x00803000
+#define BCHP_VICE2_VIP_0_1_REG_END                         0x00803224
+#define BCHP_VICE2_VIP1_0_1_REG_START                      0x00803800
+#define BCHP_VICE2_VIP1_0_1_REG_END                        0x00803a24
+#define BCHP_VICE2_XQ_0_1_REG_START                        0x00804000
+#define BCHP_VICE2_XQ_0_1_REG_END                          0x008054c8
+#define BCHP_VICE2_ARCSS_ESS_ADI_0_1_REG_START             0x00818000
+#define BCHP_VICE2_ARCSS_ESS_ADI_0_1_REG_END               0x008182b4
+#define BCHP_VICE2_ARCSS_ESS_CTRL_0_1_REG_START            0x00820000
+#define BCHP_VICE2_ARCSS_ESS_CTRL_0_1_REG_END              0x008200a4
+#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_0_1_REG_START      0x00820400
+#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_0_1_REG_END        0x0082042c
+#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_0_1_REG_START        0x00820600
+#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_0_1_REG_END          0x0082062c
+#define BCHP_VICE2_ARCSS_ESS_HOSTIF_0_1_REG_START          0x00822000
+#define BCHP_VICE2_ARCSS_ESS_HOSTIF_0_1_REG_END            0x008233fc
+#define BCHP_VICE2_ARCSS_ESS_DCCM_0_1_REG_START            0x00830000
+#define BCHP_VICE2_ARCSS_ESS_DCCM_0_1_REG_END              0x0083fffc
+#define BCHP_VICE2_ARCSS_ESS_ADI_1_1_REG_START             0x00858000
+#define BCHP_VICE2_ARCSS_ESS_ADI_1_1_REG_END               0x008582a8
+#define BCHP_VICE2_ARCSS_ESS_CTRL_1_1_REG_START            0x00860000
+#define BCHP_VICE2_ARCSS_ESS_CTRL_1_1_REG_END              0x008600a4
+#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_1_1_REG_START      0x00860400
+#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_1_1_REG_END        0x0086042c
+#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_1_1_REG_START        0x00860600
+#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_1_1_REG_END          0x0086062c
+#define BCHP_VICE2_ARCSS_ESS_HOSTIF_1_1_REG_START          0x00862000
+#define BCHP_VICE2_ARCSS_ESS_HOSTIF_1_1_REG_END            0x008633fc
+#define BCHP_VICE2_ARCSS_ESS_DCCM_1_1_REG_START            0x00870000
+#define BCHP_VICE2_ARCSS_ESS_DCCM_1_1_REG_END              0x0087fffc
+#define BCHP_VICE2_RGR_1_REG_START                         0x00880000
+#define BCHP_VICE2_RGR_1_REG_END                           0x0088000c
+#define BCHP_VICE2_MISC_1_REG_START                        0x00881000
+#define BCHP_VICE2_MISC_1_REG_END                          0x0088102c
+#define BCHP_VICE2_L2_1_REG_START                          0x00881100
+#define BCHP_VICE2_L2_1_REG_END                            0x0088112c
+#define BCHP_VICE2_ARCSS_MISC_1_REG_START                  0x00882000
+#define BCHP_VICE2_ARCSS_MISC_1_REG_END                    0x008820b8
+#define BCHP_VICE2_SEC_CTRL_0_REG_START                    0x00900000
+#define BCHP_VICE2_SEC_CTRL_0_REG_END                      0x00900080
+#define BCHP_VICE2_SEC_CTRL_1_REG_START                    0x00901000
+#define BCHP_VICE2_SEC_CTRL_1_REG_END                      0x00901080
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DONE_INTR2_REG_START 0x00a00000
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DONE_INTR2_REG_END 0x00a0002c
+#define BCHP_XPT_BUS_IF_REG_START                          0x00a00080
+#define BCHP_XPT_BUS_IF_REG_END                            0x00a000fc
+#define BCHP_XPT_XMEMIF_REG_START                          0x00a00100
+#define BCHP_XPT_XMEMIF_REG_END                            0x00a0019c
+#define BCHP_XPT_PMU_REG_START                             0x00a00200
+#define BCHP_XPT_PMU_REG_END                               0x00a00214
+#define BCHP_XPT_GR_REG_START                              0x00a00300
+#define BCHP_XPT_GR_REG_END                                0x00a0030c
+#define BCHP_XPT_RMX0_IO_REG_START                         0x00a00400
+#define BCHP_XPT_RMX0_IO_REG_END                           0x00a00420
+#define BCHP_XPT_RMX1_IO_REG_START                         0x00a00500
+#define BCHP_XPT_RMX1_IO_REG_END                           0x00a00520
+#define BCHP_XPT_WAKEUP_REG_START                          0x00a01000
+#define BCHP_XPT_WAKEUP_REG_END                            0x00a01fbc
+#define BCHP_XPT_DPCR0_REG_START                           0x00a02000
+#define BCHP_XPT_DPCR0_REG_END                             0x00a02074
+#define BCHP_XPT_DPCR1_REG_START                           0x00a02080
+#define BCHP_XPT_DPCR1_REG_END                             0x00a020f4
+#define BCHP_XPT_DPCR2_REG_START                           0x00a02100
+#define BCHP_XPT_DPCR2_REG_END                             0x00a02174
+#define BCHP_XPT_DPCR3_REG_START                           0x00a02180
+#define BCHP_XPT_DPCR3_REG_END                             0x00a021f4
+#define BCHP_XPT_DPCR4_REG_START                           0x00a02200
+#define BCHP_XPT_DPCR4_REG_END                             0x00a02274
+#define BCHP_XPT_DPCR5_REG_START                           0x00a02280
+#define BCHP_XPT_DPCR5_REG_END                             0x00a022f4
+#define BCHP_XPT_DPCR6_REG_START                           0x00a02300
+#define BCHP_XPT_DPCR6_REG_END                             0x00a02374
+#define BCHP_XPT_DPCR7_REG_START                           0x00a02380
+#define BCHP_XPT_DPCR7_REG_END                             0x00a023f4
+#define BCHP_XPT_DPCR8_REG_START                           0x00a02400
+#define BCHP_XPT_DPCR8_REG_END                             0x00a02474
+#define BCHP_XPT_DPCR9_REG_START                           0x00a02480
+#define BCHP_XPT_DPCR9_REG_END                             0x00a024f4
+#define BCHP_XPT_DPCR10_REG_START                          0x00a02500
+#define BCHP_XPT_DPCR10_REG_END                            0x00a02574
+#define BCHP_XPT_DPCR11_REG_START                          0x00a02580
+#define BCHP_XPT_DPCR11_REG_END                            0x00a025f4
+#define BCHP_XPT_DPCR12_REG_START                          0x00a02600
+#define BCHP_XPT_DPCR12_REG_END                            0x00a02674
+#define BCHP_XPT_DPCR13_REG_START                          0x00a02680
+#define BCHP_XPT_DPCR13_REG_END                            0x00a026f4
+#define BCHP_XPT_DPCR_PP_REG_START                         0x00a02800
+#define BCHP_XPT_DPCR_PP_REG_END                           0x00a02804
+#define BCHP_XPT_PSUB_REG_START                            0x00a02a00
+#define BCHP_XPT_PSUB_REG_END                              0x00a02b88
+#define BCHP_XPT_MPOD_REG_START                            0x00a02c00
+#define BCHP_XPT_MPOD_REG_END                              0x00a02c20
+#define BCHP_XPT_RMX0_REG_START                            0x00a02d00
+#define BCHP_XPT_RMX0_REG_END                              0x00a02d08
+#define BCHP_XPT_RMX1_REG_START                            0x00a02e00
+#define BCHP_XPT_RMX1_REG_END                              0x00a02e08
+#define BCHP_XPT_RSBUFF_REG_START                          0x00a03000
+#define BCHP_XPT_RSBUFF_REG_END                            0x00a03e54
+#define BCHP_XPT_XCBUFF_REG_START                          0x00a04000
+#define BCHP_XPT_XCBUFF_REG_END                            0x00a05cd0
+#define BCHP_XPT_PCROFFSET_REG_START                       0x00a08000
+#define BCHP_XPT_PCROFFSET_REG_END                         0x00a0aafc
+#define BCHP_XPT_TSIO_CONFIG_REGISTERS_REG_START           0x00a0c000
+#define BCHP_XPT_TSIO_CONFIG_REGISTERS_REG_END             0x00a0f3fc
+#define BCHP_XPT_TSIO_INTR_L2_REG_START                    0x00a0f400
+#define BCHP_XPT_TSIO_INTR_L2_REG_END                      0x00a0f42c
+#define BCHP_XPT_FULL_PID_PARSER_REG_START                 0x00a10000
+#define BCHP_XPT_FULL_PID_PARSER_REG_END                   0x00a14050
+#define BCHP_XPT_FE_REG_START                              0x00a20000
+#define BCHP_XPT_FE_REG_END                                0x00a25ffc
+#define BCHP_XPT_MSG_REG_START                             0x00a30000
+#define BCHP_XPT_MSG_REG_END                               0x00a36014
+#define BCHP_XPT_RAVE_REG_START                            0x00a40000
+#define BCHP_XPT_RAVE_REG_END                              0x00a4d6f4
+#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_0_31_REG_START       0x00a4ff80
+#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_0_31_REG_END         0x00a4ffac
+#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_32_47_REG_START      0x00a4ffc0
+#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_32_47_REG_END        0x00a4ffec
+#define BCHP_XPT_MEMDMA_MCPB_CPU_INTR_AGGREGATOR_REG_START 0x00a60000
+#define BCHP_XPT_MEMDMA_MCPB_CPU_INTR_AGGREGATOR_REG_END   0x00a6001c
+#define BCHP_XPT_MEMDMA_MCPB_PCI_INTR_AGGREGATOR_REG_START 0x00a60020
+#define BCHP_XPT_MEMDMA_MCPB_PCI_INTR_AGGREGATOR_REG_END   0x00a6003c
+#define BCHP_XPT_MEMDMA_MCPB_DESC_DONE_INTR_L2_REG_START   0x00a60040
+#define BCHP_XPT_MEMDMA_MCPB_DESC_DONE_INTR_L2_REG_END     0x00a6006c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_START 0x00a60080
+#define BCHP_XPT_MEMDMA_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_END 0x00a600ac
+#define BCHP_XPT_MEMDMA_MCPB_MISC_OOS_INTR_L2_REG_START    0x00a600c0
+#define BCHP_XPT_MEMDMA_MCPB_MISC_OOS_INTR_L2_REG_END      0x00a600ec
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_START 0x00a60100
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_END 0x00a6012c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TEI_INTR_L2_REG_START    0x00a60140
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TEI_INTR_L2_REG_END      0x00a6016c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_START 0x00a60180
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_END 0x00a601ac
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_FATAL_ERR_INTR_L2_REG_START 0x00a601c0
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_FATAL_ERR_INTR_L2_REG_END 0x00a601ec
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_START 0x00a60200
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_END 0x00a6022c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_START 0x00a60240
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_END 0x00a6026c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_START 0x00a60280
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_END 0x00a602ac
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_START 0x00a602c0
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_END 0x00a602ec
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_START 0x00a60300
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_END 0x00a6032c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_START 0x00a60340
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_END 0x00a6036c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_START 0x00a60380
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_END 0x00a603ac
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_START 0x00a603c0
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_END 0x00a603ec
+#define BCHP_XPT_MEMDMA_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_START 0x00a60400
+#define BCHP_XPT_MEMDMA_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_END 0x00a6042c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_START 0x00a60440
+#define BCHP_XPT_MEMDMA_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_END 0x00a6046c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_START 0x00a60480
+#define BCHP_XPT_MEMDMA_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_END 0x00a604ac
+#define BCHP_XPT_MEMDMA_MCPB_REG_START                     0x00a60800
+#define BCHP_XPT_MEMDMA_MCPB_REG_END                       0x00a60b08
+#define BCHP_XPT_MEMDMA_MCPB_CH0_REG_START                 0x00a60c00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_REG_END                   0x00a60d48
+#define BCHP_XPT_MEMDMA_MCPB_CH1_REG_START                 0x00a60e00
+#define BCHP_XPT_MEMDMA_MCPB_CH1_REG_END                   0x00a60f48
+#define BCHP_XPT_MEMDMA_MCPB_CH2_REG_START                 0x00a61000
+#define BCHP_XPT_MEMDMA_MCPB_CH2_REG_END                   0x00a61148
+#define BCHP_XPT_MEMDMA_MCPB_CH3_REG_START                 0x00a61200
+#define BCHP_XPT_MEMDMA_MCPB_CH3_REG_END                   0x00a61348
+#define BCHP_XPT_MEMDMA_MCPB_CH4_REG_START                 0x00a61400
+#define BCHP_XPT_MEMDMA_MCPB_CH4_REG_END                   0x00a61548
+#define BCHP_XPT_MEMDMA_MCPB_CH5_REG_START                 0x00a61600
+#define BCHP_XPT_MEMDMA_MCPB_CH5_REG_END                   0x00a61748
+#define BCHP_XPT_MEMDMA_MCPB_CH6_REG_START                 0x00a61800
+#define BCHP_XPT_MEMDMA_MCPB_CH6_REG_END                   0x00a61948
+#define BCHP_XPT_MEMDMA_MCPB_CH7_REG_START                 0x00a61a00
+#define BCHP_XPT_MEMDMA_MCPB_CH7_REG_END                   0x00a61b48
+#define BCHP_XPT_MEMDMA_MCPB_CH8_REG_START                 0x00a61c00
+#define BCHP_XPT_MEMDMA_MCPB_CH8_REG_END                   0x00a61d48
+#define BCHP_XPT_MEMDMA_MCPB_CH9_REG_START                 0x00a61e00
+#define BCHP_XPT_MEMDMA_MCPB_CH9_REG_END                   0x00a61f48
+#define BCHP_XPT_MEMDMA_MCPB_CH10_REG_START                0x00a62000
+#define BCHP_XPT_MEMDMA_MCPB_CH10_REG_END                  0x00a62148
+#define BCHP_XPT_MEMDMA_MCPB_CH11_REG_START                0x00a62200
+#define BCHP_XPT_MEMDMA_MCPB_CH11_REG_END                  0x00a62348
+#define BCHP_XPT_MEMDMA_MCPB_CH12_REG_START                0x00a62400
+#define BCHP_XPT_MEMDMA_MCPB_CH12_REG_END                  0x00a62548
+#define BCHP_XPT_MEMDMA_MCPB_CH13_REG_START                0x00a62600
+#define BCHP_XPT_MEMDMA_MCPB_CH13_REG_END                  0x00a62748
+#define BCHP_XPT_MEMDMA_MCPB_CH14_REG_START                0x00a62800
+#define BCHP_XPT_MEMDMA_MCPB_CH14_REG_END                  0x00a62948
+#define BCHP_XPT_MEMDMA_MCPB_CH15_REG_START                0x00a62a00
+#define BCHP_XPT_MEMDMA_MCPB_CH15_REG_END                  0x00a62b48
+#define BCHP_XPT_MEMDMA_MCPB_CH16_REG_START                0x00a62c00
+#define BCHP_XPT_MEMDMA_MCPB_CH16_REG_END                  0x00a62d48
+#define BCHP_XPT_MEMDMA_MCPB_CH17_REG_START                0x00a62e00
+#define BCHP_XPT_MEMDMA_MCPB_CH17_REG_END                  0x00a62f48
+#define BCHP_XPT_MEMDMA_MCPB_CH18_REG_START                0x00a63000
+#define BCHP_XPT_MEMDMA_MCPB_CH18_REG_END                  0x00a63148
+#define BCHP_XPT_MEMDMA_MCPB_CH19_REG_START                0x00a63200
+#define BCHP_XPT_MEMDMA_MCPB_CH19_REG_END                  0x00a63348
+#define BCHP_XPT_MEMDMA_MCPB_CH20_REG_START                0x00a63400
+#define BCHP_XPT_MEMDMA_MCPB_CH20_REG_END                  0x00a63548
+#define BCHP_XPT_MEMDMA_MCPB_CH21_REG_START                0x00a63600
+#define BCHP_XPT_MEMDMA_MCPB_CH21_REG_END                  0x00a63748
+#define BCHP_XPT_MEMDMA_MCPB_CH22_REG_START                0x00a63800
+#define BCHP_XPT_MEMDMA_MCPB_CH22_REG_END                  0x00a63948
+#define BCHP_XPT_MEMDMA_MCPB_CH23_REG_START                0x00a63a00
+#define BCHP_XPT_MEMDMA_MCPB_CH23_REG_END                  0x00a63b48
+#define BCHP_XPT_MEMDMA_MCPB_CH24_REG_START                0x00a63c00
+#define BCHP_XPT_MEMDMA_MCPB_CH24_REG_END                  0x00a63d48
+#define BCHP_XPT_MEMDMA_MCPB_CH25_REG_START                0x00a63e00
+#define BCHP_XPT_MEMDMA_MCPB_CH25_REG_END                  0x00a63f48
+#define BCHP_XPT_MEMDMA_MCPB_CH26_REG_START                0x00a64000
+#define BCHP_XPT_MEMDMA_MCPB_CH26_REG_END                  0x00a64148
+#define BCHP_XPT_MEMDMA_MCPB_CH27_REG_START                0x00a64200
+#define BCHP_XPT_MEMDMA_MCPB_CH27_REG_END                  0x00a64348
+#define BCHP_XPT_MEMDMA_MCPB_CH28_REG_START                0x00a64400
+#define BCHP_XPT_MEMDMA_MCPB_CH28_REG_END                  0x00a64548
+#define BCHP_XPT_MEMDMA_MCPB_CH29_REG_START                0x00a64600
+#define BCHP_XPT_MEMDMA_MCPB_CH29_REG_END                  0x00a64748
+#define BCHP_XPT_MEMDMA_MCPB_CH30_REG_START                0x00a64800
+#define BCHP_XPT_MEMDMA_MCPB_CH30_REG_END                  0x00a64948
+#define BCHP_XPT_MEMDMA_MCPB_CH31_REG_START                0x00a64a00
+#define BCHP_XPT_MEMDMA_MCPB_CH31_REG_END                  0x00a64b48
+#define BCHP_XPT_WDMA_PCI_INTR_AGGREGATOR_REG_START        0x00a68000
+#define BCHP_XPT_WDMA_PCI_INTR_AGGREGATOR_REG_END          0x00a6801c
+#define BCHP_XPT_WDMA_CPU_INTR_AGGREGATOR_REG_START        0x00a68020
+#define BCHP_XPT_WDMA_CPU_INTR_AGGREGATOR_REG_END          0x00a6803c
+#define BCHP_XPT_WDMA_BTP_INTR_L2_REG_START                0x00a68040
+#define BCHP_XPT_WDMA_BTP_INTR_L2_REG_END                  0x00a6806c
+#define BCHP_XPT_WDMA_OVERFLOW_INTR_L2_REG_START           0x00a68080
+#define BCHP_XPT_WDMA_OVERFLOW_INTR_L2_REG_END             0x00a680ac
+#define BCHP_XPT_WDMA_DESC_DONE_INTR_L2_REG_START          0x00a680c0
+#define BCHP_XPT_WDMA_DESC_DONE_INTR_L2_REG_END            0x00a680ec
+#define BCHP_XPT_WDMA_REGS_REG_START                       0x00a69000
+#define BCHP_XPT_WDMA_REGS_REG_END                         0x00a69088
+#define BCHP_XPT_WDMA_RAMS_REG_START                       0x00a6a000
+#define BCHP_XPT_WDMA_RAMS_REG_END                         0x00a6bffc
+#define BCHP_XPT_MEMDMA_XMEMIF_REG_START                   0x00a6ff00
+#define BCHP_XPT_MEMDMA_XMEMIF_REG_END                     0x00a6ff9c
+#define BCHP_XPT_MCPB_CPU_INTR_AGGREGATOR_REG_START        0x00a70000
+#define BCHP_XPT_MCPB_CPU_INTR_AGGREGATOR_REG_END          0x00a7001c
+#define BCHP_XPT_MCPB_PCI_INTR_AGGREGATOR_REG_START        0x00a70020
+#define BCHP_XPT_MCPB_PCI_INTR_AGGREGATOR_REG_END          0x00a7003c
+#define BCHP_XPT_MCPB_DESC_DONE_INTR_L2_REG_START          0x00a70040
+#define BCHP_XPT_MCPB_DESC_DONE_INTR_L2_REG_END            0x00a7006c
+#define BCHP_XPT_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_START    0x00a70080
+#define BCHP_XPT_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_END      0x00a700ac
+#define BCHP_XPT_MCPB_MISC_OOS_INTR_L2_REG_START           0x00a700c0
+#define BCHP_XPT_MCPB_MISC_OOS_INTR_L2_REG_END             0x00a700ec
+#define BCHP_XPT_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_START 0x00a70100
+#define BCHP_XPT_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_END   0x00a7012c
+#define BCHP_XPT_MCPB_MISC_TEI_INTR_L2_REG_START           0x00a70140
+#define BCHP_XPT_MCPB_MISC_TEI_INTR_L2_REG_END             0x00a7016c
+#define BCHP_XPT_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_START   0x00a70180
+#define BCHP_XPT_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_END     0x00a701ac
+#define BCHP_XPT_MCPB_MISC_ASF_FATAL_ERR_INTR_L2_REG_START 0x00a701c0
+#define BCHP_XPT_MCPB_MISC_ASF_FATAL_ERR_INTR_L2_REG_END   0x00a701ec
+#define BCHP_XPT_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_START 0x00a70200
+#define BCHP_XPT_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_END 0x00a7022c
+#define BCHP_XPT_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_START 0x00a70240
+#define BCHP_XPT_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_END 0x00a7026c
+#define BCHP_XPT_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_START 0x00a70280
+#define BCHP_XPT_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_END 0x00a702ac
+#define BCHP_XPT_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_START  0x00a702c0
+#define BCHP_XPT_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_END    0x00a702ec
+#define BCHP_XPT_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_START 0x00a70300
+#define BCHP_XPT_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_END 0x00a7032c
+#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_START 0x00a70340
+#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_END 0x00a7036c
+#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_START 0x00a70380
+#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_END 0x00a703ac
+#define BCHP_XPT_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_START 0x00a703c0
+#define BCHP_XPT_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_END 0x00a703ec
+#define BCHP_XPT_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_START 0x00a70400
+#define BCHP_XPT_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_END 0x00a7042c
+#define BCHP_XPT_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_START 0x00a70440
+#define BCHP_XPT_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_END 0x00a7046c
+#define BCHP_XPT_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_START 0x00a70480
+#define BCHP_XPT_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_END 0x00a704ac
+#define BCHP_XPT_MCPB_REG_START                            0x00a70800
+#define BCHP_XPT_MCPB_REG_END                              0x00a70b08
+#define BCHP_XPT_MCPB_CH0_REG_START                        0x00a70c00
+#define BCHP_XPT_MCPB_CH0_REG_END                          0x00a70d48
+#define BCHP_XPT_MCPB_CH1_REG_START                        0x00a70e00
+#define BCHP_XPT_MCPB_CH1_REG_END                          0x00a70f48
+#define BCHP_XPT_MCPB_CH2_REG_START                        0x00a71000
+#define BCHP_XPT_MCPB_CH2_REG_END                          0x00a71148
+#define BCHP_XPT_MCPB_CH3_REG_START                        0x00a71200
+#define BCHP_XPT_MCPB_CH3_REG_END                          0x00a71348
+#define BCHP_XPT_MCPB_CH4_REG_START                        0x00a71400
+#define BCHP_XPT_MCPB_CH4_REG_END                          0x00a71548
+#define BCHP_XPT_MCPB_CH5_REG_START                        0x00a71600
+#define BCHP_XPT_MCPB_CH5_REG_END                          0x00a71748
+#define BCHP_XPT_MCPB_CH6_REG_START                        0x00a71800
+#define BCHP_XPT_MCPB_CH6_REG_END                          0x00a71948
+#define BCHP_XPT_MCPB_CH7_REG_START                        0x00a71a00
+#define BCHP_XPT_MCPB_CH7_REG_END                          0x00a71b48
+#define BCHP_XPT_MCPB_CH8_REG_START                        0x00a71c00
+#define BCHP_XPT_MCPB_CH8_REG_END                          0x00a71d48
+#define BCHP_XPT_MCPB_CH9_REG_START                        0x00a71e00
+#define BCHP_XPT_MCPB_CH9_REG_END                          0x00a71f48
+#define BCHP_XPT_MCPB_CH10_REG_START                       0x00a72000
+#define BCHP_XPT_MCPB_CH10_REG_END                         0x00a72148
+#define BCHP_XPT_MCPB_CH11_REG_START                       0x00a72200
+#define BCHP_XPT_MCPB_CH11_REG_END                         0x00a72348
+#define BCHP_XPT_MCPB_CH12_REG_START                       0x00a72400
+#define BCHP_XPT_MCPB_CH12_REG_END                         0x00a72548
+#define BCHP_XPT_MCPB_CH13_REG_START                       0x00a72600
+#define BCHP_XPT_MCPB_CH13_REG_END                         0x00a72748
+#define BCHP_XPT_MCPB_CH14_REG_START                       0x00a72800
+#define BCHP_XPT_MCPB_CH14_REG_END                         0x00a72948
+#define BCHP_XPT_MCPB_CH15_REG_START                       0x00a72a00
+#define BCHP_XPT_MCPB_CH15_REG_END                         0x00a72b48
+#define BCHP_XPT_MCPB_CH16_REG_START                       0x00a72c00
+#define BCHP_XPT_MCPB_CH16_REG_END                         0x00a72d48
+#define BCHP_XPT_MCPB_CH17_REG_START                       0x00a72e00
+#define BCHP_XPT_MCPB_CH17_REG_END                         0x00a72f48
+#define BCHP_XPT_MCPB_CH18_REG_START                       0x00a73000
+#define BCHP_XPT_MCPB_CH18_REG_END                         0x00a73148
+#define BCHP_XPT_MCPB_CH19_REG_START                       0x00a73200
+#define BCHP_XPT_MCPB_CH19_REG_END                         0x00a73348
+#define BCHP_XPT_MCPB_CH20_REG_START                       0x00a73400
+#define BCHP_XPT_MCPB_CH20_REG_END                         0x00a73548
+#define BCHP_XPT_MCPB_CH21_REG_START                       0x00a73600
+#define BCHP_XPT_MCPB_CH21_REG_END                         0x00a73748
+#define BCHP_XPT_MCPB_CH22_REG_START                       0x00a73800
+#define BCHP_XPT_MCPB_CH22_REG_END                         0x00a73948
+#define BCHP_XPT_MCPB_CH23_REG_START                       0x00a73a00
+#define BCHP_XPT_MCPB_CH23_REG_END                         0x00a73b48
+#define BCHP_XPT_MCPB_CH24_REG_START                       0x00a73c00
+#define BCHP_XPT_MCPB_CH24_REG_END                         0x00a73d48
+#define BCHP_XPT_MCPB_CH25_REG_START                       0x00a73e00
+#define BCHP_XPT_MCPB_CH25_REG_END                         0x00a73f48
+#define BCHP_XPT_MCPB_CH26_REG_START                       0x00a74000
+#define BCHP_XPT_MCPB_CH26_REG_END                         0x00a74148
+#define BCHP_XPT_MCPB_CH27_REG_START                       0x00a74200
+#define BCHP_XPT_MCPB_CH27_REG_END                         0x00a74348
+#define BCHP_XPT_MCPB_CH28_REG_START                       0x00a74400
+#define BCHP_XPT_MCPB_CH28_REG_END                         0x00a74548
+#define BCHP_XPT_MCPB_CH29_REG_START                       0x00a74600
+#define BCHP_XPT_MCPB_CH29_REG_END                         0x00a74748
+#define BCHP_XPT_MCPB_CH30_REG_START                       0x00a74800
+#define BCHP_XPT_MCPB_CH30_REG_END                         0x00a74948
+#define BCHP_XPT_MCPB_CH31_REG_START                       0x00a74a00
+#define BCHP_XPT_MCPB_CH31_REG_END                         0x00a74b48
+#define BCHP_XPT_XPU_REG_START                             0x00a78000
+#define BCHP_XPT_XPU_REG_END                               0x00a7c7fc
+#define BCHP_XPT_SECURE_BUS_IF_REG_START                   0x00a7f000
+#define BCHP_XPT_SECURE_BUS_IF_REG_END                     0x00a7f000
+#define BCHP_GENET_0_SYS_REG_START                         0x00b60000
+#define BCHP_GENET_0_SYS_REG_END                           0x00b6000c
+#define BCHP_GENET_0_GR_BRIDGE_REG_START                   0x00b60040
+#define BCHP_GENET_0_GR_BRIDGE_REG_END                     0x00b6004c
+#define BCHP_GENET_0_EXT_REG_START                         0x00b60080
+#define BCHP_GENET_0_EXT_REG_END                           0x00b600a0
+#define BCHP_GENET_0_INTRL2_0_REG_START                    0x00b60200
+#define BCHP_GENET_0_INTRL2_0_REG_END                      0x00b6022c
+#define BCHP_GENET_0_INTRL2_1_REG_START                    0x00b60240
+#define BCHP_GENET_0_INTRL2_1_REG_END                      0x00b6026c
+#define BCHP_GENET_0_RBUF_REG_START                        0x00b60300
+#define BCHP_GENET_0_RBUF_REG_END                          0x00b603b4
+#define BCHP_GENET_0_TBUF_REG_START                        0x00b60600
+#define BCHP_GENET_0_TBUF_REG_END                          0x00b60628
+#define BCHP_GENET_0_UMAC_REG_START                        0x00b60800
+#define BCHP_GENET_0_UMAC_REG_END                          0x00b60ed8
+#define BCHP_GENET_0_RDMA_REG_START                        0x00b62000
+#define BCHP_GENET_0_RDMA_REG_END                          0x00b630d4
+#define BCHP_GENET_0_TDMA_REG_START                        0x00b64000
+#define BCHP_GENET_0_TDMA_REG_END                          0x00b65084
+#define BCHP_GENET_0_HFB_REG_START                         0x00b68000
+#define BCHP_GENET_0_HFB_REG_END                           0x00b6fc48
+#define BCHP_GENET_1_SYS_REG_START                         0x00b80000
+#define BCHP_GENET_1_SYS_REG_END                           0x00b8000c
+#define BCHP_GENET_1_GR_BRIDGE_REG_START                   0x00b80040
+#define BCHP_GENET_1_GR_BRIDGE_REG_END                     0x00b8004c
+#define BCHP_GENET_1_EXT_REG_START                         0x00b80080
+#define BCHP_GENET_1_EXT_REG_END                           0x00b800a0
+#define BCHP_GENET_1_INTRL2_0_REG_START                    0x00b80200
+#define BCHP_GENET_1_INTRL2_0_REG_END                      0x00b8022c
+#define BCHP_GENET_1_INTRL2_1_REG_START                    0x00b80240
+#define BCHP_GENET_1_INTRL2_1_REG_END                      0x00b8026c
+#define BCHP_GENET_1_RBUF_REG_START                        0x00b80300
+#define BCHP_GENET_1_RBUF_REG_END                          0x00b803b4
+#define BCHP_GENET_1_TBUF_REG_START                        0x00b80600
+#define BCHP_GENET_1_TBUF_REG_END                          0x00b80628
+#define BCHP_GENET_1_UMAC_REG_START                        0x00b80800
+#define BCHP_GENET_1_UMAC_REG_END                          0x00b80ed8
+#define BCHP_GENET_1_RDMA_REG_START                        0x00b82000
+#define BCHP_GENET_1_RDMA_REG_END                          0x00b830d4
+#define BCHP_GENET_1_TDMA_REG_START                        0x00b84000
+#define BCHP_GENET_1_TDMA_REG_END                          0x00b85084
+#define BCHP_GENET_1_HFB_REG_START                         0x00b88000
+#define BCHP_GENET_1_HFB_REG_END                           0x00b8fc48
+#define BCHP_GENET_2_SYS_REG_START                         0x00ba0000
+#define BCHP_GENET_2_SYS_REG_END                           0x00ba000c
+#define BCHP_GENET_2_GR_BRIDGE_REG_START                   0x00ba0040
+#define BCHP_GENET_2_GR_BRIDGE_REG_END                     0x00ba004c
+#define BCHP_GENET_2_EXT_REG_START                         0x00ba0080
+#define BCHP_GENET_2_EXT_REG_END                           0x00ba00a0
+#define BCHP_GENET_2_INTRL2_0_REG_START                    0x00ba0200
+#define BCHP_GENET_2_INTRL2_0_REG_END                      0x00ba022c
+#define BCHP_GENET_2_INTRL2_1_REG_START                    0x00ba0240
+#define BCHP_GENET_2_INTRL2_1_REG_END                      0x00ba026c
+#define BCHP_GENET_2_RBUF_REG_START                        0x00ba0300
+#define BCHP_GENET_2_RBUF_REG_END                          0x00ba03b4
+#define BCHP_GENET_2_TBUF_REG_START                        0x00ba0600
+#define BCHP_GENET_2_TBUF_REG_END                          0x00ba0628
+#define BCHP_GENET_2_UMAC_REG_START                        0x00ba0800
+#define BCHP_GENET_2_UMAC_REG_END                          0x00ba0ed8
+#define BCHP_GENET_2_RDMA_REG_START                        0x00ba2000
+#define BCHP_GENET_2_RDMA_REG_END                          0x00ba30d4
+#define BCHP_GENET_2_TDMA_REG_START                        0x00ba4000
+#define BCHP_GENET_2_TDMA_REG_END                          0x00ba5084
+#define BCHP_GENET_2_HFB_REG_START                         0x00ba8000
+#define BCHP_GENET_2_HFB_REG_END                           0x00bafc48
+#define BCHP_SID_REG_START                                 0x00bc0100
+#define BCHP_SID_REG_END                                   0x00bc019c
+#define BCHP_SID_RLE_REG_START                             0x00bc0300
+#define BCHP_SID_RLE_REG_END                               0x00bc039c
+#define BCHP_SID_DQ_REG_START                              0x00bc0400
+#define BCHP_SID_DQ_REG_END                                0x00bc04bc
+#define BCHP_SID_STRM_REG_START                            0x00bc0800
+#define BCHP_SID_STRM_REG_END                              0x00bc087c
+#define BCHP_SID_OUTPUT_REG_START                          0x00bc0c00
+#define BCHP_SID_OUTPUT_REG_END                            0x00bc0c40
+#define BCHP_SID_ARC_REG_START                             0x00bc0f00
+#define BCHP_SID_ARC_REG_END                               0x00bc0f3c
+#define BCHP_SID_ARCDMA_REG_START                          0x00bc1800
+#define BCHP_SID_ARCDMA_REG_END                            0x00bc1840
+#define BCHP_SID_DMARAM_REG_START                          0x00bc1a00
+#define BCHP_SID_DMARAM_REG_END                            0x00bc1bfc
+#define BCHP_SID_PEEK_BITS_REG_START                       0x00bc2b00
+#define BCHP_SID_PEEK_BITS_REG_END                         0x00bc2b3c
+#define BCHP_SID_EXTRACT_BITS_REG_START                    0x00bc2b40
+#define BCHP_SID_EXTRACT_BITS_REG_END                      0x00bc2b7c
+#define BCHP_SID_HUFF_SYMB_REG_START                       0x00bc3000
+#define BCHP_SID_HUFF_SYMB_REG_END                         0x00bc37fc
+#define BCHP_SID_HUFF_CODE_REG_START                       0x00bc3900
+#define BCHP_SID_HUFF_CODE_REG_END                         0x00bc39fc
+#define BCHP_SID_SYMB_REG_START                            0x00bc3a00
+#define BCHP_SID_SYMB_REG_END                              0x00bc3a10
+#define BCHP_SID_SYMB_JPEG_REG_START                       0x00bc3a80
+#define BCHP_SID_SYMB_JPEG_REG_END                         0x00bc3a8c
+#define BCHP_SID_BIGRAM_REG_START                          0x00bc8000
+#define BCHP_SID_BIGRAM_REG_END                            0x00bcfffc
+#define BCHP_SID_ARC_DBG_REG_START                         0x00bd1000
+#define BCHP_SID_ARC_DBG_REG_END                           0x00bd1010
+#define BCHP_SID_ARC_CORE_REG_START                        0x00bd5000
+#define BCHP_SID_ARC_CORE_REG_END                          0x00bd5014
+#define BCHP_SID_GR_REG_START                              0x00be0000
+#define BCHP_SID_GR_REG_END                                0x00be000c
+#define BCHP_SID_L2_REG_START                              0x00be0100
+#define BCHP_SID_L2_REG_END                                0x00be012c
+#define BCHP_SICH_REG_START                                0x00be2000
+#define BCHP_SICH_REG_END                                  0x00be203c
+#define BCHP_M2MC_REG_START                                0x00be4000
+#define BCHP_M2MC_REG_END                                  0x00be47fc
+#define BCHP_M2MC_L2_REG_START                             0x00be5000
+#define BCHP_M2MC_L2_REG_END                               0x00be502c
+#define BCHP_M2MC_GR_REG_START                             0x00be5800
+#define BCHP_M2MC_GR_REG_END                               0x00be580c
+#define BCHP_M2MC1_REG_START                               0x00be6000
+#define BCHP_M2MC1_REG_END                                 0x00be67fc
+#define BCHP_M2MC1_L2_REG_START                            0x00be7000
+#define BCHP_M2MC1_L2_REG_END                              0x00be702c
+#define BCHP_M2MC1_GR_REG_START                            0x00be7800
+#define BCHP_M2MC1_GR_REG_END                              0x00be780c
+#define BCHP_V3D_CTL_REG_START                             0x00bea000
+#define BCHP_V3D_CTL_REG_END                               0x00bea040
+#define BCHP_V3D_CLE_REG_START                             0x00bea100
+#define BCHP_V3D_CLE_REG_END                               0x00bea138
+#define BCHP_V3D_PTB_REG_START                             0x00bea300
+#define BCHP_V3D_PTB_REG_END                               0x00bea310
+#define BCHP_V3D_QPS_REG_START                             0x00bea400
+#define BCHP_V3D_QPS_REG_END                               0x00bea43c
+#define BCHP_V3D_VPM_REG_START                             0x00bea500
+#define BCHP_V3D_VPM_REG_END                               0x00bea504
+#define BCHP_V3D_PCTR_REG_START                            0x00bea600
+#define BCHP_V3D_PCTR_REG_END                              0x00bea6fc
+#define BCHP_V3D_TOP_GR_BRIDGE_REG_START                   0x00bea800
+#define BCHP_V3D_TOP_GR_BRIDGE_REG_END                     0x00bea80c
+#define BCHP_V3D_GCA_REG_START                             0x00beaa00
+#define BCHP_V3D_GCA_REG_END                               0x00beaa58
+#define BCHP_V3D_DBG_REG_START                             0x00beae00
+#define BCHP_V3D_DBG_REG_END                               0x00beaf20
+#define BCHP_RAAGA_DSP_SEC0_REG_START                      0x00bf0000
+#define BCHP_RAAGA_DSP_SEC0_REG_END                        0x00bf0000
+#define BCHP_RAAGA_DSP_SEC0_1_REG_START                    0x00bf1000
+#define BCHP_RAAGA_DSP_SEC0_1_REG_END                      0x00bf1000
+#define BCHP_RAAGA_DSP_RGR_REG_START                       0x00c00000
+#define BCHP_RAAGA_DSP_RGR_REG_END                         0x00c00008
+#define BCHP_RAAGA_DSP_MISC_REG_START                      0x00c20000
+#define BCHP_RAAGA_DSP_MISC_REG_END                        0x00c2044c
+#define BCHP_RAAGA_DSP_TIMERS_REG_START                    0x00c21000
+#define BCHP_RAAGA_DSP_TIMERS_REG_END                      0x00c21058
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START             0x00c21080
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END               0x00c2109c
+#define BCHP_RAAGA_DSP_PERI_SW_REG_START                   0x00c21100
+#define BCHP_RAAGA_DSP_PERI_SW_REG_END                     0x00c21154
+#define BCHP_RAAGA_DSP_DMA_REG_START                       0x00c21400
+#define BCHP_RAAGA_DSP_DMA_REG_END                         0x00c21664
+#define BCHP_RAAGA_DSP_ESR_SI_REG_START                    0x00c22000
+#define BCHP_RAAGA_DSP_ESR_SI_REG_END                      0x00c22014
+#define BCHP_RAAGA_DSP_INTH_REG_START                      0x00c22200
+#define BCHP_RAAGA_DSP_INTH_REG_END                        0x00c2222c
+#define BCHP_RAAGA_DSP_FW_INTH_REG_START                   0x00c22400
+#define BCHP_RAAGA_DSP_FW_INTH_REG_END                     0x00c2242c
+#define BCHP_RAAGA_DSP_FW_CFG_REG_START                    0x00c23000
+#define BCHP_RAAGA_DSP_FW_CFG_REG_END                      0x00c2357c
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START             0x00c30000
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END               0x00c3bffc
+#define BCHP_AUD_MISC_REG_START                            0x00c80000
+#define BCHP_AUD_MISC_REG_END                              0x00c80118
+#define BCHP_AUD_INTH_REG_START                            0x00c80800
+#define BCHP_AUD_INTH_REG_END                              0x00c8082c
+#define BCHP_AUD_FMM_BF_CTRL_REG_START                     0x00ca0000
+#define BCHP_AUD_FMM_BF_CTRL_REG_END                       0x00ca0d3c
+#define BCHP_AUD_FMM_BF_ESR_REG_START                      0x00ca1000
+#define BCHP_AUD_FMM_BF_ESR_REG_END                        0x00ca1074
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_START                   0x00ca2000
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_END                     0x00ca2bfc
+#define BCHP_AUD_FMM_SRC_ESR0_REG_START                    0x00ca3000
+#define BCHP_AUD_FMM_SRC_ESR0_REG_END                      0x00ca3014
+#define BCHP_AUD_FMM_DP_CTRL0_REG_START                    0x00ca4000
+#define BCHP_AUD_FMM_DP_CTRL0_REG_END                      0x00ca612c
+#define BCHP_AUD_FMM_DP_ESR0_REG_START                     0x00ca7c00
+#define BCHP_AUD_FMM_DP_ESR0_REG_END                       0x00ca7c2c
+#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_0_REG_START        0x00cb0000
+#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_0_REG_END          0x00cb0084
+#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_1_REG_START        0x00cb0100
+#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_1_REG_END          0x00cb0184
+#define BCHP_AUD_FMM_IOP_OUT_SPDIF_0_REG_START             0x00cb0200
+#define BCHP_AUD_FMM_IOP_OUT_SPDIF_0_REG_END               0x00cb0284
+#define BCHP_AUD_FMM_IOP_OUT_MAI_0_REG_START               0x00cb0300
+#define BCHP_AUD_FMM_IOP_OUT_MAI_0_REG_END                 0x00cb0384
+#define BCHP_HIFIDAC_CTRL_0_REG_START                      0x00cb0800
+#define BCHP_HIFIDAC_CTRL_0_REG_END                        0x00cb09fc
+#define BCHP_HIFIDAC_RM_0_REG_START                        0x00cb0a00
+#define BCHP_HIFIDAC_RM_0_REG_END                          0x00cb0a24
+#define BCHP_HIFIDAC_ESR_0_REG_START                       0x00cb0b00
+#define BCHP_HIFIDAC_ESR_0_REG_END                         0x00cb0b14
+#define BCHP_AUD_FMM_IOP_OUT_DAC_CTRL_0_REG_START          0x00cb0c00
+#define BCHP_AUD_FMM_IOP_OUT_DAC_CTRL_0_REG_END            0x00cb0c94
+#define BCHP_AUD_FMM_IOP_PLL_0_REG_START                   0x00cb0d00
+#define BCHP_AUD_FMM_IOP_PLL_0_REG_END                     0x00cb0d58
+#define BCHP_AUD_FMM_IOP_PLL_1_REG_START                   0x00cb0e00
+#define BCHP_AUD_FMM_IOP_PLL_1_REG_END                     0x00cb0e58
+#define BCHP_AUD_FMM_IOP_PLL_2_REG_START                   0x00cb0f00
+#define BCHP_AUD_FMM_IOP_PLL_2_REG_END                     0x00cb0f58
+#define BCHP_AUD_FMM_IOP_NCO_0_REG_START                   0x00cb1000
+#define BCHP_AUD_FMM_IOP_NCO_0_REG_END                     0x00cb1024
+#define BCHP_AUD_FMM_IOP_NCO_1_REG_START                   0x00cb1100
+#define BCHP_AUD_FMM_IOP_NCO_1_REG_END                     0x00cb1124
+#define BCHP_AUD_FMM_IOP_NCO_2_REG_START                   0x00cb1200
+#define BCHP_AUD_FMM_IOP_NCO_2_REG_END                     0x00cb1224
+#define BCHP_AUD_FMM_IOP_NCO_3_REG_START                   0x00cb1300
+#define BCHP_AUD_FMM_IOP_NCO_3_REG_END                     0x00cb1324
+#define BCHP_AUD_FMM_IOP_NCO_4_REG_START                   0x00cb1400
+#define BCHP_AUD_FMM_IOP_NCO_4_REG_END                     0x00cb1424
+#define BCHP_AUD_FMM_IOP_LOOPBACK_0_REG_START              0x00cb1600
+#define BCHP_AUD_FMM_IOP_LOOPBACK_0_REG_END                0x00cb1724
+#define BCHP_AUD_FMM_IOP_DUMMYSINK_0_REG_START             0x00cb1800
+#define BCHP_AUD_FMM_IOP_DUMMYSINK_0_REG_END               0x00cb1854
+#define BCHP_AUD_FMM_IOP_IN_SPDIF_0_REG_START              0x00cb2000
+#define BCHP_AUD_FMM_IOP_IN_SPDIF_0_REG_END                0x00cb20fc
+#define BCHP_AUD_FMM_IOP_IN_HDMI_0_REG_START               0x00cb2800
+#define BCHP_AUD_FMM_IOP_IN_HDMI_0_REG_END                 0x00cb28ac
+#define BCHP_AUD_FMM_IOP_IN_I2S_STEREO_0_REG_START         0x00cb3000
+#define BCHP_AUD_FMM_IOP_IN_I2S_STEREO_0_REG_END           0x00cb3064
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_0_REG_START       0x00cb4000
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_0_REG_END         0x00cb41fc
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_0_REG_START       0x00cb4400
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_0_REG_END         0x00cb4414
+#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_0_REG_START           0x00cb6000
+#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_0_REG_END             0x00cb7bfc
+#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_0_REG_START            0x00cb7d00
+#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_0_REG_END              0x00cb7d14
+#define BCHP_AUD_FMM_IOP_MISC_REG_START                    0x00cb8100
+#define BCHP_AUD_FMM_IOP_MISC_REG_END                      0x00cb8154
+#define BCHP_RAAGA_DSP_RGR_1_REG_START                     0x00d00000
+#define BCHP_RAAGA_DSP_RGR_1_REG_END                       0x00d00008
+#define BCHP_RAAGA_DSP_MISC_1_REG_START                    0x00d20000
+#define BCHP_RAAGA_DSP_MISC_1_REG_END                      0x00d2044c
+#define BCHP_RAAGA_DSP_TIMERS_1_REG_START                  0x00d21000
+#define BCHP_RAAGA_DSP_TIMERS_1_REG_END                    0x00d21058
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_1_REG_START           0x00d21080
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_1_REG_END             0x00d2109c
+#define BCHP_RAAGA_DSP_PERI_SW_1_REG_START                 0x00d21100
+#define BCHP_RAAGA_DSP_PERI_SW_1_REG_END                   0x00d21154
+#define BCHP_RAAGA_DSP_DMA_1_REG_START                     0x00d21400
+#define BCHP_RAAGA_DSP_DMA_1_REG_END                       0x00d21664
+#define BCHP_RAAGA_DSP_ESR_SI_1_REG_START                  0x00d22000
+#define BCHP_RAAGA_DSP_ESR_SI_1_REG_END                    0x00d22014
+#define BCHP_RAAGA_DSP_INTH_1_REG_START                    0x00d22200
+#define BCHP_RAAGA_DSP_INTH_1_REG_END                      0x00d2222c
+#define BCHP_RAAGA_DSP_FW_INTH_1_REG_START                 0x00d22400
+#define BCHP_RAAGA_DSP_FW_INTH_1_REG_END                   0x00d2242c
+#define BCHP_RAAGA_DSP_FW_CFG_1_REG_START                  0x00d23000
+#define BCHP_RAAGA_DSP_FW_CFG_1_REG_END                    0x00d2357c
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_1_REG_START           0x00d30000
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_1_REG_END             0x00d3bffc
+#define BCHP_DATA_MEM_REG_START                            0x00e00000
+#define BCHP_DATA_MEM_REG_END                              0x00e47ffc
+#define BCHP_CNTL_MEM_REG_START                            0x00f20000
+#define BCHP_CNTL_MEM_REG_END                              0x00f67ffc
+#define BCHP_DMA_AHB_ECL_CMD_SCH0_REG_START                0x00fc0000
+#define BCHP_DMA_AHB_ECL_CMD_SCH0_REG_END                  0x00fc0000
+#define BCHP_DMA_AHB_ECL_CMD_SCH1_REG_START                0x00fc0010
+#define BCHP_DMA_AHB_ECL_CMD_SCH1_REG_END                  0x00fc0010
+#define BCHP_DMA_AHB_ECL_CMD_SCH2_REG_START                0x00fc0020
+#define BCHP_DMA_AHB_ECL_CMD_SCH2_REG_END                  0x00fc0020
+#define BCHP_DMA_AHB_ECL_CMD_SCH3_REG_START                0x00fc0030
+#define BCHP_DMA_AHB_ECL_CMD_SCH3_REG_END                  0x00fc0030
+#define BCHP_DMA_AHB_ECL_CMD_SCH4_REG_START                0x00fc0040
+#define BCHP_DMA_AHB_ECL_CMD_SCH4_REG_END                  0x00fc0040
+#define BCHP_DMA_AHB_ECL_CMD_SCH5_REG_START                0x00fc0050
+#define BCHP_DMA_AHB_ECL_CMD_SCH5_REG_END                  0x00fc0050
+#define BCHP_DMA_AHB_ECL_CMD_SCH6_REG_START                0x00fc0060
+#define BCHP_DMA_AHB_ECL_CMD_SCH6_REG_END                  0x00fc0060
+#define BCHP_DMA_AHB_ECL_CMD_SCH7_REG_START                0x00fc0070
+#define BCHP_DMA_AHB_ECL_CMD_SCH7_REG_END                  0x00fc0070
+#define BCHP_DMA_AHB_ECL_CMD_SCH8_REG_START                0x00fc0080
+#define BCHP_DMA_AHB_ECL_CMD_SCH8_REG_END                  0x00fc0080
+#define BCHP_DMA_AHB_ECL_CMD_SCH9_REG_START                0x00fc0090
+#define BCHP_DMA_AHB_ECL_CMD_SCH9_REG_END                  0x00fc0090
+#define BCHP_DMA_AHB_ECL_CMD_SCH10_REG_START               0x00fc00a0
+#define BCHP_DMA_AHB_ECL_CMD_SCH10_REG_END                 0x00fc00a0
+#define BCHP_DMA_AHB_ECL_CMD_SCH11_REG_START               0x00fc00b0
+#define BCHP_DMA_AHB_ECL_CMD_SCH11_REG_END                 0x00fc00b0
+#define BCHP_DMA_AHB_ECL_CMD_SCH12_REG_START               0x00fc00c0
+#define BCHP_DMA_AHB_ECL_CMD_SCH12_REG_END                 0x00fc00c0
+#define BCHP_DMA_AHB_ECL_CMD_SCH13_REG_START               0x00fc00d0
+#define BCHP_DMA_AHB_ECL_CMD_SCH13_REG_END                 0x00fc00d0
+#define BCHP_DMA_AHB_ECL_CMD_SCH14_REG_START               0x00fc00e0
+#define BCHP_DMA_AHB_ECL_CMD_SCH14_REG_END                 0x00fc00e0
+#define BCHP_DMA_AHB_ECL_CMD_SCH15_REG_START               0x00fc00f0
+#define BCHP_DMA_AHB_ECL_CMD_SCH15_REG_END                 0x00fc00f0
+#define BCHP_DMA_AHB_ECL_CMD_SCH16_REG_START               0x00fc0100
+#define BCHP_DMA_AHB_ECL_CMD_SCH16_REG_END                 0x00fc0100
+#define BCHP_DMA_AHB_ECL_CMD_SCH17_REG_START               0x00fc0110
+#define BCHP_DMA_AHB_ECL_CMD_SCH17_REG_END                 0x00fc0110
+#define BCHP_DMA_AHB_ECL_CMD_SCH18_REG_START               0x00fc0120
+#define BCHP_DMA_AHB_ECL_CMD_SCH18_REG_END                 0x00fc0120
+#define BCHP_DMA_AHB_ECL_CMD_SCH19_REG_START               0x00fc0130
+#define BCHP_DMA_AHB_ECL_CMD_SCH19_REG_END                 0x00fc0130
+#define BCHP_DMA_AHB_ECL_CMD_RX_REG_START                  0x00fc0800
+#define BCHP_DMA_AHB_ECL_CMD_RX_REG_END                    0x00fc0800
+#define BCHP_DMA_AHB_CMD_RX_SCH0_REG_START                 0x00fc4000
+#define BCHP_DMA_AHB_CMD_RX_SCH0_REG_END                   0x00fc4000
+#define BCHP_DMA_AHB_CMD_RX_SCH1_REG_START                 0x00fc4010
+#define BCHP_DMA_AHB_CMD_RX_SCH1_REG_END                   0x00fc4010
+#define BCHP_DMA_AHB_CMD_RX_SCH2_REG_START                 0x00fc4020
+#define BCHP_DMA_AHB_CMD_RX_SCH2_REG_END                   0x00fc4020
+#define BCHP_DMA_AHB_CMD_RX_SCH3_REG_START                 0x00fc4030
+#define BCHP_DMA_AHB_CMD_RX_SCH3_REG_END                   0x00fc4030
+#define BCHP_DMA_AHB_CMD_RX_SCH4_REG_START                 0x00fc4040
+#define BCHP_DMA_AHB_CMD_RX_SCH4_REG_END                   0x00fc4040
+#define BCHP_DMA_AHB_CMD_RX_SCH5_REG_START                 0x00fc4050
+#define BCHP_DMA_AHB_CMD_RX_SCH5_REG_END                   0x00fc4050
+#define BCHP_DMA_AHB_CMD_RX_SCH6_REG_START                 0x00fc4060
+#define BCHP_DMA_AHB_CMD_RX_SCH6_REG_END                   0x00fc4060
+#define BCHP_DMA_AHB_CMD_RX_SCH7_REG_START                 0x00fc4070
+#define BCHP_DMA_AHB_CMD_RX_SCH7_REG_END                   0x00fc4070
+#define BCHP_DMA_AHB_CMD_RX_SCH8_REG_START                 0x00fc4080
+#define BCHP_DMA_AHB_CMD_RX_SCH8_REG_END                   0x00fc4080
+#define BCHP_DMA_AHB_CMD_RX_SCH9_REG_START                 0x00fc4090
+#define BCHP_DMA_AHB_CMD_RX_SCH9_REG_END                   0x00fc4090
+#define BCHP_DMA_AHB_CMD_RX_SCH10_REG_START                0x00fc40a0
+#define BCHP_DMA_AHB_CMD_RX_SCH10_REG_END                  0x00fc40a0
+#define BCHP_DMA_AHB_CMD_RX_SCH11_REG_START                0x00fc40b0
+#define BCHP_DMA_AHB_CMD_RX_SCH11_REG_END                  0x00fc40b0
+#define BCHP_DMA_AHB_CMD_RX_SCH12_REG_START                0x00fc40c0
+#define BCHP_DMA_AHB_CMD_RX_SCH12_REG_END                  0x00fc40c0
+#define BCHP_DMA_AHB_CMD_RX_SCH13_REG_START                0x00fc40d0
+#define BCHP_DMA_AHB_CMD_RX_SCH13_REG_END                  0x00fc40d0
+#define BCHP_DMA_AHB_CMD_RX_SCH14_REG_START                0x00fc40e0
+#define BCHP_DMA_AHB_CMD_RX_SCH14_REG_END                  0x00fc40e0
+#define BCHP_DMA_AHB_CMD_RX_SCH15_REG_START                0x00fc40f0
+#define BCHP_DMA_AHB_CMD_RX_SCH15_REG_END                  0x00fc40f0
+#define BCHP_DMA_AHB_CMD_RX_SCH16_REG_START                0x00fc4100
+#define BCHP_DMA_AHB_CMD_RX_SCH16_REG_END                  0x00fc4100
+#define BCHP_DMA_AHB_CMD_RX_SCH17_REG_START                0x00fc4110
+#define BCHP_DMA_AHB_CMD_RX_SCH17_REG_END                  0x00fc4110
+#define BCHP_DMA_AHB_CMD_RX_SCH18_REG_START                0x00fc4120
+#define BCHP_DMA_AHB_CMD_RX_SCH18_REG_END                  0x00fc4120
+#define BCHP_DMA_AHB_CMD_RX_SCH19_REG_START                0x00fc4130
+#define BCHP_DMA_AHB_CMD_RX_SCH19_REG_END                  0x00fc4130
+#define BCHP_DMA_AHB_CMD_RES0_SCH0_REG_START               0x00fc4200
+#define BCHP_DMA_AHB_CMD_RES0_SCH0_REG_END                 0x00fc4200
+#define BCHP_DMA_AHB_CMD_RES0_SCH1_REG_START               0x00fc4210
+#define BCHP_DMA_AHB_CMD_RES0_SCH1_REG_END                 0x00fc4210
+#define BCHP_DMA_AHB_CMD_RES0_SCH2_REG_START               0x00fc4220
+#define BCHP_DMA_AHB_CMD_RES0_SCH2_REG_END                 0x00fc4220
+#define BCHP_DMA_AHB_CMD_RES0_SCH3_REG_START               0x00fc4230
+#define BCHP_DMA_AHB_CMD_RES0_SCH3_REG_END                 0x00fc4230
+#define BCHP_DMA_AHB_CMD_RES0_SCH4_REG_START               0x00fc4240
+#define BCHP_DMA_AHB_CMD_RES0_SCH4_REG_END                 0x00fc4240
+#define BCHP_DMA_AHB_CMD_RES0_SCH5_REG_START               0x00fc4250
+#define BCHP_DMA_AHB_CMD_RES0_SCH5_REG_END                 0x00fc4250
+#define BCHP_DMA_AHB_CMD_RES0_SCH6_REG_START               0x00fc4260
+#define BCHP_DMA_AHB_CMD_RES0_SCH6_REG_END                 0x00fc4260
+#define BCHP_DMA_AHB_CMD_RES0_SCH7_REG_START               0x00fc4270
+#define BCHP_DMA_AHB_CMD_RES0_SCH7_REG_END                 0x00fc4270
+#define BCHP_DMA_AHB_CMD_TX0_REG_START                     0x00fc4800
+#define BCHP_DMA_AHB_CMD_TX0_REG_END                       0x00fc4800
+#define BCHP_DMA_AHB_CMD_TX1_REG_START                     0x00fc4a00
+#define BCHP_DMA_AHB_CMD_TX1_REG_END                       0x00fc4a00
+#define BCHP_DMA_AHB_CMD_CONF0_REG_START                   0x00fc4c00
+#define BCHP_DMA_AHB_CMD_CONF0_REG_END                     0x00fc4c00
+#define BCHP_MAC_AHB_REG_START                             0x00fc5000
+#define BCHP_MAC_AHB_REG_END                               0x00fc500c
+#define BCHP_LLM_AHB_REG_START                             0x00fc8000
+#define BCHP_LLM_AHB_REG_END                               0x00fc805c
+#define BCHP_PHY_REG_START                                 0x00fe0000
+#define BCHP_PHY_REG_END                                   0x00fe47fc
+#define BCHP_ECL_REG_START                                 0x00fe8000
+#define BCHP_ECL_REG_END                                   0x00fec940
+#define BCHP_DMA_IO2MEM_CH_ECL_TX_Global_REG_START         0x00fed000
+#define BCHP_DMA_IO2MEM_CH_ECL_TX_Global_REG_END           0x00fed014
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH0_REG_START      0x00fed040
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH0_REG_END        0x00fed06c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH1_REG_START      0x00fed080
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH1_REG_END        0x00fed0ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH2_REG_START      0x00fed0c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH2_REG_END        0x00fed0ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH3_REG_START      0x00fed100
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH3_REG_END        0x00fed12c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH4_REG_START      0x00fed140
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH4_REG_END        0x00fed16c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH5_REG_START      0x00fed180
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH5_REG_END        0x00fed1ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH6_REG_START      0x00fed1c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH6_REG_END        0x00fed1ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH7_REG_START      0x00fed200
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH7_REG_END        0x00fed22c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH8_REG_START      0x00fed240
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH8_REG_END        0x00fed26c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH9_REG_START      0x00fed280
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH9_REG_END        0x00fed2ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH10_REG_START     0x00fed2c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH10_REG_END       0x00fed2ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH11_REG_START     0x00fed300
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH11_REG_END       0x00fed32c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH12_REG_START     0x00fed340
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH12_REG_END       0x00fed36c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH13_REG_START     0x00fed380
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH13_REG_END       0x00fed3ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH14_REG_START     0x00fed3c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH14_REG_END       0x00fed3ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH15_REG_START     0x00fed400
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH15_REG_END       0x00fed42c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH16_REG_START     0x00fed440
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH16_REG_END       0x00fed46c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH17_REG_START     0x00fed480
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH17_REG_END       0x00fed4ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH18_REG_START     0x00fed4c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH18_REG_END       0x00fed4ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH19_REG_START     0x00fed500
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH19_REG_END       0x00fed52c
+#define BCHP_DMA_MEM2IO_CH_ECL_RX_REG_START                0x00fed800
+#define BCHP_DMA_MEM2IO_CH_ECL_RX_REG_END                  0x00fed828
+#define BCHP_GMII_REG_START                                0x00fedc00
+#define BCHP_GMII_REG_END                                  0x00fedc58
+#define BCHP_MAC_APB_REG_START                             0x00ff0000
+#define BCHP_MAC_APB_REG_END                               0x00ff14fc
+#define BCHP_DMA_IO2MEM_CH_MAC_RX_Global_REG_START         0x00ff4000
+#define BCHP_DMA_IO2MEM_CH_MAC_RX_Global_REG_END           0x00ff4014
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH0_REG_START      0x00ff4040
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH0_REG_END        0x00ff406c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH1_REG_START      0x00ff4080
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH1_REG_END        0x00ff40ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH2_REG_START      0x00ff40c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH2_REG_END        0x00ff40ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH3_REG_START      0x00ff4100
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH3_REG_END        0x00ff412c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH4_REG_START      0x00ff4140
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH4_REG_END        0x00ff416c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH5_REG_START      0x00ff4180
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH5_REG_END        0x00ff41ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH6_REG_START      0x00ff41c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH6_REG_END        0x00ff41ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH7_REG_START      0x00ff4200
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH7_REG_END        0x00ff422c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH8_REG_START      0x00ff4240
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH8_REG_END        0x00ff426c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH9_REG_START      0x00ff4280
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH9_REG_END        0x00ff42ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH10_REG_START     0x00ff42c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH10_REG_END       0x00ff42ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH11_REG_START     0x00ff4300
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH11_REG_END       0x00ff432c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH12_REG_START     0x00ff4340
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH12_REG_END       0x00ff436c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH13_REG_START     0x00ff4380
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH13_REG_END       0x00ff43ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH14_REG_START     0x00ff43c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH14_REG_END       0x00ff43ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH15_REG_START     0x00ff4400
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH15_REG_END       0x00ff442c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH16_REG_START     0x00ff4440
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH16_REG_END       0x00ff446c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH17_REG_START     0x00ff4480
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH17_REG_END       0x00ff44ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH18_REG_START     0x00ff44c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH18_REG_END       0x00ff44ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH19_REG_START     0x00ff4500
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH19_REG_END       0x00ff452c
+#define BCHP_DMA_IO2MEM_CH_PHY0_Global_REG_START           0x00ff4800
+#define BCHP_DMA_IO2MEM_CH_PHY0_Global_REG_END             0x00ff4814
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH0_REG_START        0x00ff4840
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH0_REG_END          0x00ff486c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH1_REG_START        0x00ff4880
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH1_REG_END          0x00ff48ac
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH2_REG_START        0x00ff48c0
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH2_REG_END          0x00ff48ec
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH3_REG_START        0x00ff4900
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH3_REG_END          0x00ff492c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH4_REG_START        0x00ff4940
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH4_REG_END          0x00ff496c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH5_REG_START        0x00ff4980
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH5_REG_END          0x00ff49ac
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH6_REG_START        0x00ff49c0
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH6_REG_END          0x00ff49ec
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH7_REG_START        0x00ff4a00
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH7_REG_END          0x00ff4a2c
+#define BCHP_DMA_MEM2IO_CH_MAC_TX0_REG_START               0x00ff6000
+#define BCHP_DMA_MEM2IO_CH_MAC_TX0_REG_END                 0x00ff6028
+#define BCHP_DMA_MEM2IO_CH_MAC_TX1_REG_START               0x00ff6400
+#define BCHP_DMA_MEM2IO_CH_MAC_TX1_REG_END                 0x00ff6428
+#define BCHP_DMA_MEM2IO_CH_PHY0_CONFIG_REG_START           0x00ff6800
+#define BCHP_DMA_MEM2IO_CH_PHY0_CONFIG_REG_END             0x00ff6828
+#define BCHP_MOCA_INTC_L2_HI_REG_START                     0x00ff8000
+#define BCHP_MOCA_INTC_L2_HI_REG_END                       0x00ff8584
+#define BCHP_MOCA_INTC_L2_LO_REG_START                     0x00ff8800
+#define BCHP_MOCA_INTC_L2_LO_REG_END                       0x00ff8d84
+#define BCHP_LLM_APB_REG_START                             0x00ffc000
+#define BCHP_LLM_APB_REG_END                               0x00ffd00c
+#define BCHP_TRX_REG_START                                 0x00ffe000
+#define BCHP_TRX_REG_END                                   0x00ffe174
+#define BCHP_MOCA_TIMER_REG_START                          0x00ffe400
+#define BCHP_MOCA_TIMER_REG_END                            0x00ffe4ec
+#define BCHP_MOCA_GPIO_REG_START                           0x00ffe800
+#define BCHP_MOCA_GPIO_REG_END                             0x00ffe818
+#define BCHP_EXTRAS_REG_START                              0x00ffec00
+#define BCHP_EXTRAS_REG_END                                0x00ffed18
+#define BCHP_MOCA_BSC_REG_START                            0x00fff000
+#define BCHP_MOCA_BSC_REG_END                              0x00fff058
+#define BCHP_MOCA_HOSTM2M_REG_START                        0x00fffc00
+#define BCHP_MOCA_HOSTM2M_REG_END                          0x00fffc14
+#define BCHP_AHB_M2M_DMA_REG_START                         0x00fffc20
+#define BCHP_AHB_M2M_DMA_REG_END                           0x00fffc2c
+#define BCHP_MOCA_L2_REG_START                             0x00fffc40
+#define BCHP_MOCA_L2_REG_END                               0x00fffc6c
+#define BCHP_MOCA_GR_BRIDGE_REG_START                      0x00fffc80
+#define BCHP_MOCA_GR_BRIDGE_REG_END                        0x00fffc8c
+#define BCHP_MOCA_HOSTMISC_REG_START                       0x00fffd00
+#define BCHP_MOCA_HOSTMISC_REG_END                         0x00fffd9c
+
+
+/***************************************************************************
+ *AUD_FMM_MS_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK  0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
+
+/***************************************************************************
+ *AUD_FMM_OP_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
+ ***************************************************************************/
+/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD1
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_VFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *GFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK      0xffffffff
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT     0
+
+/***************************************************************************
+ *GFD_1
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD_1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK    0xffffffff
+#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT   0
+
+/***************************************************************************
+ *HIFIDAC_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_MUTE_USAGE - Mute usage
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *M2MC
+ ***************************************************************************/
+/***************************************************************************
+ *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK          0xffffffff
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT         0
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK              0xf0000000
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT             28
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK          0x0fffffe0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT         5
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK              0x0000001e
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT             1
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK           0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT          0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid   0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK              0xffff8000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT             15
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK   0x00004000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT  14
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK   0x00002000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT  13
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK         0x00000800
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT        11
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE   1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE  0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK  0x00000400
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK  0x00000200
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK          0x00000100
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT         8
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE   0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK   0x00000020
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT  5
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK     0x00000002
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK     0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT    0
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/***************************************************************************
+ *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK        0xffffffff
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT       0
+
+/***************************************************************************
+ *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK         0xffffffff
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT        0
+
+/***************************************************************************
+ *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_11_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_11_SRC_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_11_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *TYPE_CLUT_COLOR_DATA - color data for color look up table
+ ***************************************************************************/
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK                  0xff000000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT                 24
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK                    0x00ff0000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT                   16
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK                  0x0000ff00
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT                 8
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK                   0x000000ff
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT                  0
+
+/***************************************************************************
+ *PCIE_DMA
+ ***************************************************************************/
+/***************************************************************************
+ *DESC_WORD0 - PCIE DMA Descriptor Word 0
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD0 :: MEMORY_ADDRESS [31:00] */
+#define BCHP_PCIE_DMA_DESC_WORD0_MEMORY_ADDRESS_MASK               0xffffffff
+#define BCHP_PCIE_DMA_DESC_WORD0_MEMORY_ADDRESS_SHIFT              0
+
+/***************************************************************************
+ *DESC_WORD1 - PCIE DMA Descriptor Word 1
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD1 :: PCIE_ADDRESS_LO [31:00] */
+#define BCHP_PCIE_DMA_DESC_WORD1_PCIE_ADDRESS_LO_MASK              0xffffffff
+#define BCHP_PCIE_DMA_DESC_WORD1_PCIE_ADDRESS_LO_SHIFT             0
+
+/***************************************************************************
+ *DESC_WORD2 - PCIE DMA Descriptor Word 2
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD2 :: PCIE_ADDRESS_HI [31:00] */
+#define BCHP_PCIE_DMA_DESC_WORD2_PCIE_ADDRESS_HI_MASK              0xffffffff
+#define BCHP_PCIE_DMA_DESC_WORD2_PCIE_ADDRESS_HI_SHIFT             0
+
+/***************************************************************************
+ *DESC_WORD3 - PCIE DMA Descriptor Word 3
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD3 :: INTERRUPT_ENABLE [31:31] */
+#define BCHP_PCIE_DMA_DESC_WORD3_INTERRUPT_ENABLE_MASK             0x80000000
+#define BCHP_PCIE_DMA_DESC_WORD3_INTERRUPT_ENABLE_SHIFT            31
+
+/* PCIE_DMA :: DESC_WORD3 :: reserved0 [30:25] */
+#define BCHP_PCIE_DMA_DESC_WORD3_reserved0_MASK                    0x7e000000
+#define BCHP_PCIE_DMA_DESC_WORD3_reserved0_SHIFT                   25
+
+/* PCIE_DMA :: DESC_WORD3 :: DMA_TRANSFER_SIZE [24:00] */
+#define BCHP_PCIE_DMA_DESC_WORD3_DMA_TRANSFER_SIZE_MASK            0x01ffffff
+#define BCHP_PCIE_DMA_DESC_WORD3_DMA_TRANSFER_SIZE_SHIFT           0
+
+/***************************************************************************
+ *DESC_WORD4 - PCIE DMA Descriptor Word 4
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD4 :: LAST_RECORD_INDICATOR [31:31] */
+#define BCHP_PCIE_DMA_DESC_WORD4_LAST_RECORD_INDICATOR_MASK        0x80000000
+#define BCHP_PCIE_DMA_DESC_WORD4_LAST_RECORD_INDICATOR_SHIFT       31
+
+/* PCIE_DMA :: DESC_WORD4 :: DMA_DIRECTION [30:30] */
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_MASK                0x40000000
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_SHIFT               30
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_PCIE_TO_MEMORY      1
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_MEMORY_TO_PCIE      0
+
+/* PCIE_DMA :: DESC_WORD4 :: reserved0 [29:03] */
+#define BCHP_PCIE_DMA_DESC_WORD4_reserved0_MASK                    0x3ffffff8
+#define BCHP_PCIE_DMA_DESC_WORD4_reserved0_SHIFT                   3
+
+/* PCIE_DMA :: DESC_WORD4 :: DESC_CONTIGUOUS [02:02] */
+#define BCHP_PCIE_DMA_DESC_WORD4_DESC_CONTIGUOUS_MASK              0x00000004
+#define BCHP_PCIE_DMA_DESC_WORD4_DESC_CONTIGUOUS_SHIFT             2
+
+/* PCIE_DMA :: DESC_WORD4 :: ENDIAN_XLATE_MODE [01:00] */
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_MASK            0x00000003
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SHIFT           0
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_NO_SWAP         0
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SWAP_16_IN_32   1
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SWAP_32         2
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_reserved        3
+
+/***************************************************************************
+ *DESC_WORD5 - PCIE DMA Descriptor Word 5
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD5 :: NEXT_DESC_ADDRESS_LO [31:05] */
+#define BCHP_PCIE_DMA_DESC_WORD5_NEXT_DESC_ADDRESS_LO_MASK         0xffffffe0
+#define BCHP_PCIE_DMA_DESC_WORD5_NEXT_DESC_ADDRESS_LO_SHIFT        5
+
+/* PCIE_DMA :: DESC_WORD5 :: reserved0 [04:00] */
+#define BCHP_PCIE_DMA_DESC_WORD5_reserved0_MASK                    0x0000001f
+#define BCHP_PCIE_DMA_DESC_WORD5_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD6 - PCIE DMA Descriptor Word 6
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD6 :: NEXT_DESC_ADDRESS_HI [31:00] */
+#define BCHP_PCIE_DMA_DESC_WORD6_NEXT_DESC_ADDRESS_HI_MASK         0xffffffff
+#define BCHP_PCIE_DMA_DESC_WORD6_NEXT_DESC_ADDRESS_HI_SHIFT        0
+
+/***************************************************************************
+ *DESC_WORD7 - PCIE DMA Descriptor Word 7
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD7 :: reserved0 [31:08] */
+#define BCHP_PCIE_DMA_DESC_WORD7_reserved0_MASK                    0xffffff00
+#define BCHP_PCIE_DMA_DESC_WORD7_reserved0_SHIFT                   8
+
+/* PCIE_DMA :: DESC_WORD7 :: MEMORY_ADDRESS_HI [07:00] */
+#define BCHP_PCIE_DMA_DESC_WORD7_MEMORY_ADDRESS_HI_MASK            0x000000ff
+#define BCHP_PCIE_DMA_DESC_WORD7_MEMORY_ADDRESS_HI_SHIFT           0
+
+/***************************************************************************
+ *RAAGA_REGSET_DSP_CFG
+ ***************************************************************************/
+/***************************************************************************
+ *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK     0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT    0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo   2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono     1
+
+/***************************************************************************
+ *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
+
+/***************************************************************************
+ *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off     0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On      1
+
+/***************************************************************************
+ *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt  1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo  2
+
+/***************************************************************************
+ *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK       0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT      0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono    1
+
+/***************************************************************************
+ *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK   0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *RDC
+ ***************************************************************************/
+/***************************************************************************
+ *EOP_ID_256 - EOP_ID
+ ***************************************************************************/
+/* RDC :: EOP_ID_256 :: eop_id [255:00] */
+#define BCHP_RDC_EOP_ID_256_eop_id_MASK                            0x0000000000000000000000000000000000000000000000000000000000000000
+#define BCHP_RDC_EOP_ID_256_eop_id_SHIFT                           0
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_0                    0
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_1                    1
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_2                    2
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_3                    3
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_4                    4
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_5                    5
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_6                    6
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_7                    7
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_0                    8
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_1                    9
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_2                    10
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_3                    11
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_4                    12
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_5                    13
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_6                    14
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_7                    15
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_0                    16
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_1                    17
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_2                    18
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_3                    19
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_4                    20
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_5                    21
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_6                    22
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_7                    23
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_0                   24
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_1                   25
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_2                   26
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_3                   27
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_4                   28
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_5                   29
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_6                   30
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_pfa_0                    31
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_0                   32
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_1                   33
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_2                   34
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_3                   35
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_4                   36
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_5                   37
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_6                   38
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_7                   39
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_nvp_0                    40
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_s3dh_0                   41
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_v0_be                    42
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_0               43
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_1               44
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_2               45
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_3               46
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_4               47
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_0                    48
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_1                    49
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_2                    50
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_3                    51
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_4                    52
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_5                    53
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_6                    54
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_7                    55
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_8                    56
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_9                    57
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_10                   58
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_11                   59
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_12                   60
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_13                   61
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_7               62
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_8               63
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_0                           64
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_1                           65
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_2                           66
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_3                           67
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_4                           68
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_5                           69
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_6                           70
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_7                           71
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_0                           72
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_1                           73
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_2                           74
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_3                           75
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_4                           76
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_5                           77
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_6                           78
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_7                           79
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_0                           80
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_1                           81
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_2                           82
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_3                           83
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_4                           84
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_5                           85
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_6                           86
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_7                           87
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_0                           88
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_1                           89
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_2                           90
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_3                           91
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_4                           92
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_5                           93
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_6                           94
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_7                           95
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_0                           96
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_1                           97
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_2                           98
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_3                           99
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_4                           100
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_5                           101
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_6                           102
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_7                           103
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_0                          104
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_1                          105
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_2                          106
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_3                          107
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_4                          108
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_5                          109
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_6                          110
+#define BCHP_RDC_EOP_ID_256_eop_id_hscl_7                          111
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_0                           112
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_1                           113
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_2                           114
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_3                           115
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_4                           116
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_5                           117
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_6                           118
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_7                           119
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_0                           120
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_1                           121
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_2                           122
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_3                           123
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_4                           124
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_5                           125
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_6                           126
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_7                           127
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_0                           128
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_1                           129
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_2                           130
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_3                           131
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_4                           132
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_5                           133
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_6                           134
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_7                           135
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_0                        136
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_1                        137
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_2                        138
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_3                        139
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_4                        140
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_5                        141
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_6                        142
+#define BCHP_RDC_EOP_ID_256_eop_id_tpg_0                           143
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_0                           144
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_1                           145
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_2                           146
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_3                           147
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_4                           148
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_5                           149
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_6                           150
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_7                           151
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_0                          152
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_1                          153
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_2                          154
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_3                          155
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_4                          156
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_5                          157
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_6                          158
+#define BCHP_RDC_EOP_ID_256_eop_id_pfa_0                           159
+#define BCHP_RDC_EOP_ID_256_eop_id_crc_0                           160
+#define BCHP_RDC_EOP_ID_256_eop_id_crc_1                           161
+#define BCHP_RDC_EOP_ID_256_eop_id_crc_2                           162
+#define BCHP_RDC_EOP_ID_256_eop_id_crc_3                           163
+#define BCHP_RDC_EOP_ID_256_eop_id_hist_0                          164
+#define BCHP_RDC_EOP_ID_256_eop_id_hist_1                          165
+#define BCHP_RDC_EOP_ID_256_eop_id_psm_0                           166
+#define BCHP_RDC_EOP_ID_256_eop_id_plm_0                           167
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_0                    168
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_1                    169
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_2                    170
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_3                    171
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_4                    172
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_5                    173
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_6                    174
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_7                    175
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_0                    176
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_1                    177
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_2                    178
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_3                    179
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_hist_0                   180
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_hist_1                   181
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_psm_0                    182
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_plm_0                    183
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_0_v0                 184
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_1_v0                 185
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_2_v0                 186
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_3_v0                 187
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_4_v0                 188
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_5_v0                 189
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_6_v0                 190
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_7_v0                 191
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_0_v1                 192
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_1_v1                 193
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_2_v1                 194
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_3_v1                 195
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_4_v1                 196
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_5_v1                 197
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_6_v1                 198
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_7_v1                 199
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_0                   200
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_1                   201
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_2                   202
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_3                   203
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_4                   204
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_5                   205
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_6                   206
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_7                   207
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_b3dc_0                   208
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_frc_0                    209
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_0               210
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_1               211
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_2               212
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_3               213
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_4               214
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_5               215
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_0               216
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_1               217
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_2               218
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_3               219
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_4               220
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_5               221
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_6               222
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_7               223
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_8               224
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_9               225
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_10              226
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_11              227
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_6               228
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_7               229
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_8               230
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_9               231
+#define BCHP_RDC_EOP_ID_256_eop_id_nvp_0                           232
+#define BCHP_RDC_EOP_ID_256_eop_id_s3dh_0                          233
+#define BCHP_RDC_EOP_ID_256_eop_id_v0_be                           234
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_0                      235
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_1                      236
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_2                      237
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_3                      238
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_4                      239
+#define BCHP_RDC_EOP_ID_256_eop_id_b3dc_0                          240
+#define BCHP_RDC_EOP_ID_256_eop_id_frc_0                           241
+#define BCHP_RDC_EOP_ID_256_eop_id_pdpf_0                          242
+#define BCHP_RDC_EOP_ID_256_eop_id_pdpb_0                          243
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_5                      244
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_6                      245
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_7                      246
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_8                      247
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_9                      248
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_10                     249
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_11                     250
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_12                     251
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_13                     252
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_14                     253
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_15                     254
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_16                     255
+
+/***************************************************************************
+ *RUL - RUL Command.
+ ***************************************************************************/
+/* RDC :: RUL :: opcode [31:24] */
+#define BCHP_RDC_RUL_opcode_MASK                                   0xff000000
+#define BCHP_RDC_RUL_opcode_SHIFT                                  24
+#define BCHP_RDC_RUL_opcode_NOP                                    0
+#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM                          1
+#define BCHP_RDC_RUL_opcode_REG_WRITE                              2
+#define BCHP_RDC_RUL_opcode_REG_READ                               3
+#define BCHP_RDC_RUL_opcode_LOAD_IMM                               4
+#define BCHP_RDC_RUL_opcode_WINDOW_WRITE                           5
+#define BCHP_RDC_RUL_opcode_BLOCK_WRITE                            6
+#define BCHP_RDC_RUL_opcode_WINDOW_COPY                            7
+#define BCHP_RDC_RUL_opcode_BLOCK_COPY                             8
+#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK                        9
+#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW                        10
+#define BCHP_RDC_RUL_opcode_AND                                    11
+#define BCHP_RDC_RUL_opcode_AND_IMM                                12
+#define BCHP_RDC_RUL_opcode_OR                                     13
+#define BCHP_RDC_RUL_opcode_OR_IMM                                 14
+#define BCHP_RDC_RUL_opcode_XOR                                    15
+#define BCHP_RDC_RUL_opcode_XOR_IMM                                16
+#define BCHP_RDC_RUL_opcode_NOT                                    17
+#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT                           18
+#define BCHP_RDC_RUL_opcode_SUM                                    19
+#define BCHP_RDC_RUL_opcode_SUM_IMM                                20
+#define BCHP_RDC_RUL_opcode_COND_SKIP                              21
+#define BCHP_RDC_RUL_opcode_SKIP                                   22
+#define BCHP_RDC_RUL_opcode_EXIT                                   23
+#define BCHP_RDC_RUL_opcode_WAIT_EOP                               24
+#define BCHP_RDC_RUL_opcode_PLACEHOLDER                            255
+
+/* RDC :: RUL :: reserved0 [23:23] */
+#define BCHP_RDC_RUL_reserved0_MASK                                0x00800000
+#define BCHP_RDC_RUL_reserved0_SHIFT                               23
+
+/* union - case rdc_args [22:00] */
+/* RDC :: RUL :: rdc_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_rdc_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: rdc_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_rdc_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_rdc_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: rdc_args :: src2 [11:06] */
+#define BCHP_RDC_RUL_rdc_args_src2_MASK                            0x00000fc0
+#define BCHP_RDC_RUL_rdc_args_src2_SHIFT                           6
+
+/* RDC :: RUL :: rdc_args :: dest [05:00] */
+#define BCHP_RDC_RUL_rdc_args_dest_MASK                            0x0000003f
+#define BCHP_RDC_RUL_rdc_args_dest_SHIFT                           0
+
+/* union - case reg_args [22:00] */
+/* RDC :: RUL :: reg_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_reg_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_reg_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: reg_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_reg_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_reg_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: reg_args :: count [11:00] */
+#define BCHP_RDC_RUL_reg_args_count_MASK                           0x00000fff
+#define BCHP_RDC_RUL_reg_args_count_SHIFT                          0
+
+/* union - case eop_args [22:00] */
+/* RDC :: RUL :: eop_args :: reserved0 [22:08] */
+#define BCHP_RDC_RUL_eop_args_reserved0_MASK                       0x007fff00
+#define BCHP_RDC_RUL_eop_args_reserved0_SHIFT                      8
+
+/* RDC :: RUL :: eop_args :: eop [07:00] */
+#define BCHP_RDC_RUL_eop_args_eop_MASK                             0x000000ff
+#define BCHP_RDC_RUL_eop_args_eop_SHIFT                            0
+
+/***************************************************************************
+ *SPDIF_RCVR_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_INTERRUPT_HANDLING - Interrupt Handling
+ ***************************************************************************/
+/* SPDIF_RCVR_CTRL :: ABSTRACT_INTERRUPT_HANDLING :: MORE_INFORMATION [31:00] */
+#define BCHP_SPDIF_RCVR_CTRL_ABSTRACT_INTERRUPT_HANDLING_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_SPDIF_RCVR_CTRL_ABSTRACT_INTERRUPT_HANDLING_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *VICE2_REGSET_MISC
+ ***************************************************************************/
+/***************************************************************************
+ *DCCM - registers interface address offset in DCCM.
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: DCCM :: INTERFACE [31:16] */
+#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_MASK                 0xffff0000
+#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_SHIFT                16
+#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_HOST2VICE_OFFSET     0
+#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_VICE2HOST_OFFSET     4
+#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_BVN2VICE_OFFSET      8
+#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_MBOX_0_START         16
+#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_MBOX_1_START         40
+
+/* VICE2_REGSET_MISC :: DCCM :: REVISION [15:00] */
+#define BCHP_VICE2_REGSET_MISC_DCCM_REVISION_MASK                  0x0000ffff
+#define BCHP_VICE2_REGSET_MISC_DCCM_REVISION_SHIFT                 0
+#define BCHP_VICE2_REGSET_MISC_DCCM_REVISION_ID                    1
+
+/***************************************************************************
+ *DWORD_00_BVB_PIC_SIZE - BVB Picture Size
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: DWORD_00_BVB_PIC_SIZE :: H_SIZE [31:16] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_H_SIZE_MASK   0xffff0000
+#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_H_SIZE_SHIFT  16
+
+/* VICE2_REGSET_MISC :: DWORD_00_BVB_PIC_SIZE :: V_SIZE [15:00] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_V_SIZE_MASK   0x0000ffff
+#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_V_SIZE_SHIFT  0
+
+/***************************************************************************
+ *DWORD_01_SAMPLE_ASPECT_RATIO - Sample Aspect Ratio
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: DWORD_01_SAMPLE_ASPECT_RATIO :: H_SIZE [31:16] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_H_SIZE_MASK 0xffff0000
+#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_H_SIZE_SHIFT 16
+
+/* VICE2_REGSET_MISC :: DWORD_01_SAMPLE_ASPECT_RATIO :: V_SIZE [15:00] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_V_SIZE_MASK 0x0000ffff
+#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_V_SIZE_SHIFT 0
+
+/***************************************************************************
+ *DWORD_02_PIC_INFO - Picture Information
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: FRAME_RATE [31:16] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_FRAME_RATE_MASK   0xffff0000
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_FRAME_RATE_SHIFT  16
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: SRC_PIC_TYPE [15:12] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_MASK 0x0000f000
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_SHIFT 12
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_UNKNOWN 0
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_I    1
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_P    2
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_B    3
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: POLARITY [11:10] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_MASK     0x00000c00
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_SHIFT    10
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_TOP      0
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_BOT      1
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_FRAME    2
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: REPEAT [09:09] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_MASK       0x00000200
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_SHIFT      9
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_DISABLE    0
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_ENABLE     1
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: IGNORE [08:08] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_MASK       0x00000100
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_SHIFT      8
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_DISABLE    0
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_ENABLE     1
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: LAST [07:07] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_MASK         0x00000080
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_SHIFT        7
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_FALSE        0
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_TRUE         1
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: CHANNELCHANGE [06:06] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_MASK 0x00000040
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_SHIFT 6
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_FALSE 0
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_TRUE 1
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: reserved0 [05:05] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_reserved0_MASK    0x00000020
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_reserved0_SHIFT   5
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: ACTIVEFORMATDATA [04:04] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_MASK 0x00000010
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_SHIFT 4
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_FALSE 0
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_TRUE 1
+
+/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: ACTIVEFORMATDATAMODE [03:00] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATAMODE_MASK 0x0000000f
+#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATAMODE_SHIFT 0
+
+/***************************************************************************
+ *DWORD_03_ORIGINAL_PTS - Source PTS Value
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: DWORD_03_ORIGINAL_PTS :: VAL [31:00] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_03_ORIGINAL_PTS_VAL_MASK      0xffffffff
+#define BCHP_VICE2_REGSET_MISC_DWORD_03_ORIGINAL_PTS_VAL_SHIFT     0
+
+/***************************************************************************
+ *DWORD_04_STG_PICTURE_ID - STG Picture ID
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: DWORD_04_STG_PICTURE_ID :: VAL [31:00] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_04_STG_PICTURE_ID_VAL_MASK    0xffffffff
+#define BCHP_VICE2_REGSET_MISC_DWORD_04_STG_PICTURE_ID_VAL_SHIFT   0
+
+/***************************************************************************
+ *DWORD_05_BARDATA_INFO - bar data Information
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: reserved0 [31:30] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_reserved0_MASK 0xc0000000
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_reserved0_SHIFT 30
+
+/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: TOPLEFTBARVALUE [29:16] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_TOPLEFTBARVALUE_MASK 0x3fff0000
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_TOPLEFTBARVALUE_SHIFT 16
+
+/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: BARDATATYPE [15:14] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_MASK 0x0000c000
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_SHIFT 14
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_invalidBarData 0
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_TopBottom 1
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_LeftRight 2
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_reserved 3
+
+/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: BOTRIGHTBARVALUE [13:00] */
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BOTRIGHTBARVALUE_MASK 0x00003fff
+#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BOTRIGHTBARVALUE_SHIFT 0
+
+/***************************************************************************
+ *MBOX - MBOX registers interface address offset.
+ ***************************************************************************/
+/* VICE2_REGSET_MISC :: MBOX :: INTERFACE [31:16] */
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_MASK                 0xffff0000
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_SHIFT                16
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_00_BVB_PIC_SIZE_OFFSET 0
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_01_SAMPLE_ASPECT_RATIO_OFFSET 4
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_02_PIC_INFO_OFFSET 8
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_03_ORIGINAL_PTS_OFFSET 12
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_04_STG_PICTURE_ID_OFFSET 16
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_05_BARDATA_INFO_OFFSET 20
+#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_SIZE                 6
+
+/* VICE2_REGSET_MISC :: MBOX :: MAJORREVISION [15:08] */
+#define BCHP_VICE2_REGSET_MISC_MBOX_MAJORREVISION_MASK             0x0000ff00
+#define BCHP_VICE2_REGSET_MISC_MBOX_MAJORREVISION_SHIFT            8
+#define BCHP_VICE2_REGSET_MISC_MBOX_MAJORREVISION_ID               1
+
+/* VICE2_REGSET_MISC :: MBOX :: MINORREVISION [07:00] */
+#define BCHP_VICE2_REGSET_MISC_MBOX_MINORREVISION_MASK             0x000000ff
+#define BCHP_VICE2_REGSET_MISC_MBOX_MINORREVISION_SHIFT            0
+#define BCHP_VICE2_REGSET_MISC_MBOX_MINORREVISION_ID               0
+
+/***************************************************************************
+ *XPT_RAVE
+ ***************************************************************************/
+/***************************************************************************
+ *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
+
+/***************************************************************************
+ *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
+
+/***************************************************************************
+ *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
+ ***************************************************************************/
+/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
+
+#endif /* #ifndef BCHP_COMMON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_0_0.h b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_0_0.h
new file mode 100644
index 0000000..551ab605
--- /dev/null
+++ b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_0_0.h
@@ -0,0 +1,2074 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Oct 17 03:11:31 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR34_PHY_BYTE_LANE_0_0_H__
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_H__
+
+/***************************************************************************
+ *DDR34_PHY_BYTE_LANE_0_0 - DDR34 DDR34 Byte Lane #0 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P 0x003b6400 /* Write channel DQS-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N 0x003b6404 /* Write channel DQS-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0 0x003b6408 /* Write channel DQ0 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1 0x003b640c /* Write channel DQ1 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2 0x003b6410 /* Write channel DQ2 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3 0x003b6414 /* Write channel DQ3 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4 0x003b6418 /* Write channel DQ4 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5 0x003b641c /* Write channel DQ5 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6 0x003b6420 /* Write channel DQ6 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7 0x003b6424 /* Write channel DQ7 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM 0x003b6428 /* Write channel DM VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC 0x003b642c /* Write channel EDC VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP 0x003b6430 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN 0x003b6434 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P 0x003b6438 /* Read channel DQ0-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N 0x003b643c /* Read channel DQ0-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P 0x003b6440 /* Read channel DQ1-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N 0x003b6444 /* Read channel DQ1-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P 0x003b6448 /* Read channel DQ2-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N 0x003b644c /* Read channel DQ2-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P 0x003b6450 /* Read channel DQ3-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N 0x003b6454 /* Read channel DQ3-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P 0x003b6458 /* Read channel DQ4-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N 0x003b645c /* Read channel DQ4-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P 0x003b6460 /* Read channel DQ5-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N 0x003b6464 /* Read channel DQ5-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P 0x003b6468 /* Read channel DQ6-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N 0x003b646c /* Read channel DQ6-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P 0x003b6470 /* Read channel DQ7-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N 0x003b6474 /* Read channel DQ7-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP 0x003b6478 /* Read channel DM-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN 0x003b647c /* Read channel DM-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP 0x003b6480 /* Read channel EDC-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN 0x003b6484 /* Read channel EDC-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0 0x003b6488 /* Read channel CS_N[0] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1 0x003b648c /* Read channel CS_N[1] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL 0x003b6490 /* Write leveling VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC 0x003b64a0 /* Read enable bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC 0x003b64a4 /* Write leveling bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL 0x003b64b0 /* Read channel datapath control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR 0x003b64b4 /* Read fifo addresss pointer register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DATA 0x003b64b8 /* Read fifo data register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI 0x003b64bc /* Read fifo dm/dbi register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS 0x003b64c0 /* Read fifo status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR 0x003b64c4 /* Read fifo status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL 0x003b64c8 /* Idle mode SSTL pad control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL 0x003b64cc /* SSTL pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL 0x003b64d0 /* SSTL read enable pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL 0x003b64d4 /* pad rx and tx characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE 0x003b64d8 /* Write cycle preamble control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL 0x003b64e0 /* Read channel ODT control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL 0x003b64f0 /* GDDR5M EDC digital phase detector control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS 0x003b64f4 /* GDDR5M EDC digital phase detector status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL 0x003b64f8 /* GDDR5M EDC digital phase detector output signal control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS 0x003b64fc /* GDDR5M EDC digital phase detector output signal status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR 0x003b6500 /* GDDR5M EDC digital phase detector output signal status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL 0x003b6504 /* GDDR5M EDC signal path CRC control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS 0x003b6508 /* GDDR5M EDC signal path CRC status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT 0x003b650c /* GDDR5M EDC signal path CRC counter register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR 0x003b6510 /* GDDR5M EDC signal path CRC counter register */
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DM - Write channel DM VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_BUSY_MASK   0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_BUSY_SHIFT  31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_FORCE_MASK  0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CLK_CONTROL - Write leveling VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_ADJ_EN_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_BUSY_MASK       0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_BUSY_SHIFT      31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_BUSY_DEFAULT    0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_reserved0_MASK  0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_FORCE_MASK      0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_FORCE_SHIFT     16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_FORCE_DEFAULT   0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_reserved1_MASK  0x0000ff00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_reserved1_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_CYCLES_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_CYCLES_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_CONTROL - Read channel datapath control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: READ_CONTROL :: reserved0 [31:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_reserved0_MASK   0xffffffe0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_reserved0_SHIFT  5
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: READ_CONTROL :: MODE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_MODE_MASK        0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_MODE_SHIFT       4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_MODE_DEFAULT     0x00000001
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: READ_CONTROL :: reserved1 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_reserved1_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_reserved1_SHIFT  3
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_RD_DATA_DLY_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
+
+/***************************************************************************
+ *READ_FIFO_ADDR - Read fifo addresss pointer register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_reserved0_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_ADDR :: ADDR [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_ADDR_MASK      0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_ADDR_SHIFT     0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_ADDR_DEFAULT   0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA - Read fifo data register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_DATA :: DATA [31:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DATA_DATA_MASK      0xffffffff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DATA_DATA_SHIFT     0
+
+/***************************************************************************
+ *READ_FIFO_DM_DBI - Read fifo dm/dbi register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI_DM_DBI_MASK  0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_STATUS :: reserved0 [31:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_reserved0_SHIFT 2
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_CLEAR_MASK    0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_CLEAR_SHIFT   0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDLE_MASK    0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDLE_SHIFT   31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved1 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_reserved1_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_reserved1_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_RXENB_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_RXENB_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDDQ_MASK    0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDDQ_SHIFT   2
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_N_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_P_MASK  0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: reserved0 [31:29] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved0_MASK  0xe0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved0_SHIFT 29
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [28:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x1e000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: reserved1 [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved1_MASK  0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved1_SHIFT 24
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [23:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x00f00000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: reserved2 [19:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved2_MASK  0x00080000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved2_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: reserved3 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved3_MASK  0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved3_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: reserved4 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved4_MASK  0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved4_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: reserved5 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved5_MASK  0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved5_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff80000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: reserved1 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_reserved1_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_reserved1_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: reserved2 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_reserved2_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: reserved3 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_reserved3_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_reserved3_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *STATIC_PAD_CTL - pad rx and tx characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved0 [31:21] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved0_SHIFT 21
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_MODE_MASK  0x00100000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved1 [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved1_SHIFT 18
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_EDC_MODE_MASK  0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved2 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved2_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved2_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DM_MODE_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DM_MODE_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved3 [11:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved3_MASK 0x00000c00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved3_SHIFT 10
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: RX_LS [08:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RX_LS_MASK     0x00000100
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RX_LS_SHIFT    8
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RX_LS_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_TX_MODE_MASK   0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_TX_MODE_SHIFT  4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved4 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved4_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved4_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RX_MODE_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RX_MODE_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_reserved0_SHIFT 16
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQS [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_MASK     0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_SHIFT    8
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_DEFAULT  0x0000000e
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_reserved1_SHIFT 5
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
+
+/***************************************************************************
+ *ODT_CONTROL - Read channel ODT control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: reserved0 [31:07] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_reserved0_MASK    0xffffff80
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_reserved0_SHIFT   7
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: ODT_ENABLE [06:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_ENABLE_MASK   0x00000040
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_ENABLE_SHIFT  6
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
+
+/***************************************************************************
+ *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_reserved0_SHIFT 6
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_UPDATE_MASK   0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_UPDATE_SHIFT  2
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_MONITOR_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_MONITOR_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: INIT [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_INIT_MASK     0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_INIT_SHIFT    0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_INIT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: reserved0 [31:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_reserved0_SHIFT 25
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved1_SHIFT 11
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCWL_MASK    0x00000700
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCWL_SHIFT   8
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved2_SHIFT 6
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCRL_MASK    0x00000030
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCRL_SHIFT   4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved3_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_FAIL_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_FAIL_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_PASS_MASK   0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_PASS_SHIFT  2
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_FAIL_MASK   0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_FAIL_SHIFT  1
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_PASS_MASK   0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_PASS_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_COUNT :: reserved0 [31:28] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_reserved0_MASK  0xf0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_reserved0_SHIFT 28
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_WR_COUNT_MASK   0x0fff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_WR_COUNT_SHIFT  16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_COUNT :: reserved1 [15:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_reserved1_MASK  0x0000f000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_reserved1_SHIFT 12
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_RD_COUNT_MASK   0x00000fff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_RD_COUNT_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_0_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_0_1.h b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_0_1.h
new file mode 100644
index 0000000..6b23507
--- /dev/null
+++ b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_0_1.h
@@ -0,0 +1,2074 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Oct 17 03:11:32 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR34_PHY_BYTE_LANE_0_1_H__
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_H__
+
+/***************************************************************************
+ *DDR34_PHY_BYTE_LANE_0_1 - DDR34 DDR34 Byte Lane #0 control registers 1
+ ***************************************************************************/
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P 0x003c6400 /* Write channel DQS-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N 0x003c6404 /* Write channel DQS-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0 0x003c6408 /* Write channel DQ0 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1 0x003c640c /* Write channel DQ1 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2 0x003c6410 /* Write channel DQ2 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3 0x003c6414 /* Write channel DQ3 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4 0x003c6418 /* Write channel DQ4 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5 0x003c641c /* Write channel DQ5 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6 0x003c6420 /* Write channel DQ6 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7 0x003c6424 /* Write channel DQ7 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM 0x003c6428 /* Write channel DM VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC 0x003c642c /* Write channel EDC VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP 0x003c6430 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN 0x003c6434 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P 0x003c6438 /* Read channel DQ0-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N 0x003c643c /* Read channel DQ0-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P 0x003c6440 /* Read channel DQ1-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N 0x003c6444 /* Read channel DQ1-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P 0x003c6448 /* Read channel DQ2-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N 0x003c644c /* Read channel DQ2-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P 0x003c6450 /* Read channel DQ3-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N 0x003c6454 /* Read channel DQ3-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P 0x003c6458 /* Read channel DQ4-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N 0x003c645c /* Read channel DQ4-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P 0x003c6460 /* Read channel DQ5-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N 0x003c6464 /* Read channel DQ5-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P 0x003c6468 /* Read channel DQ6-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N 0x003c646c /* Read channel DQ6-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P 0x003c6470 /* Read channel DQ7-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N 0x003c6474 /* Read channel DQ7-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP 0x003c6478 /* Read channel DM-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN 0x003c647c /* Read channel DM-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP 0x003c6480 /* Read channel EDC-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN 0x003c6484 /* Read channel EDC-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0 0x003c6488 /* Read channel CS_N[0] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1 0x003c648c /* Read channel CS_N[1] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL 0x003c6490 /* Write leveling VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC 0x003c64a0 /* Read enable bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC 0x003c64a4 /* Write leveling bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_CONTROL 0x003c64b0 /* Read channel datapath control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_ADDR 0x003c64b4 /* Read fifo addresss pointer register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_DATA 0x003c64b8 /* Read fifo data register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_DM_DBI 0x003c64bc /* Read fifo dm/dbi register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_STATUS 0x003c64c0 /* Read fifo status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_CLEAR 0x003c64c4 /* Read fifo status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL 0x003c64c8 /* Idle mode SSTL pad control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL 0x003c64cc /* SSTL pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL 0x003c64d0 /* SSTL read enable pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL 0x003c64d4 /* pad rx and tx characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE 0x003c64d8 /* Write cycle preamble control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL 0x003c64e0 /* Read channel ODT control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL 0x003c64f0 /* GDDR5M EDC digital phase detector control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS 0x003c64f4 /* GDDR5M EDC digital phase detector status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL 0x003c64f8 /* GDDR5M EDC digital phase detector output signal control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS 0x003c64fc /* GDDR5M EDC digital phase detector output signal status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_CLEAR 0x003c6500 /* GDDR5M EDC digital phase detector output signal status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL 0x003c6504 /* GDDR5M EDC signal path CRC control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS 0x003c6508 /* GDDR5M EDC signal path CRC status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_COUNT 0x003c650c /* GDDR5M EDC signal path CRC counter register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_CLEAR 0x003c6510 /* GDDR5M EDC signal path CRC counter register */
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DM - Write channel DM VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_BUSY_MASK   0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_BUSY_SHIFT  31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_FORCE_MASK  0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DM :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_DM :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_EDC :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_WR_EDC :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CLK_CONTROL - Write leveling VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CLK_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CLK_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_ADJ_EN_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_ADJ_EN_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_BUSY_MASK       0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_BUSY_SHIFT      31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_BUSY_DEFAULT    0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_reserved0_MASK  0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_FORCE_MASK      0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_FORCE_SHIFT     16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_FORCE_DEFAULT   0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_reserved1_MASK  0x0000ff00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_reserved1_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_CYCLES_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_CYCLES_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_CONTROL - Read channel datapath control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: READ_CONTROL :: reserved0 [31:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_CONTROL_reserved0_MASK   0xffffffe0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_CONTROL_reserved0_SHIFT  5
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: READ_CONTROL :: MODE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_CONTROL_MODE_MASK        0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_CONTROL_MODE_SHIFT       4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_CONTROL_MODE_DEFAULT     0x00000001
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: READ_CONTROL :: reserved1 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_CONTROL_reserved1_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_CONTROL_reserved1_SHIFT  3
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_CONTROL_RD_DATA_DLY_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
+
+/***************************************************************************
+ *READ_FIFO_ADDR - Read fifo addresss pointer register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: READ_FIFO_ADDR :: reserved0 [31:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_ADDR_reserved0_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: READ_FIFO_ADDR :: ADDR [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_ADDR_ADDR_MASK      0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_ADDR_ADDR_SHIFT     0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_ADDR_ADDR_DEFAULT   0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA - Read fifo data register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: READ_FIFO_DATA :: DATA [31:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_DATA_DATA_MASK      0xffffffff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_DATA_DATA_SHIFT     0
+
+/***************************************************************************
+ *READ_FIFO_DM_DBI - Read fifo dm/dbi register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_DM_DBI_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_DM_DBI_DM_DBI_MASK  0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: READ_FIFO_STATUS :: reserved0 [31:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_STATUS_reserved0_SHIFT 2
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_CLEAR_CLEAR_MASK    0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_CLEAR_CLEAR_SHIFT   0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_IDLE_MASK    0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_IDLE_SHIFT   31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: IDLE_PAD_CONTROL :: reserved1 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_reserved1_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_reserved1_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_RXENB_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_RXENB_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_IDDQ_MASK    0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_IDDQ_SHIFT   2
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_DOUT_N_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_DOUT_P_MASK  0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: DRIVE_PAD_CTL :: reserved0 [31:29] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_reserved0_MASK  0xe0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_reserved0_SHIFT 29
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [28:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x1e000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: DRIVE_PAD_CTL :: reserved1 [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_reserved1_MASK  0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_reserved1_SHIFT 24
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [23:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x00f00000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: DRIVE_PAD_CTL :: reserved2 [19:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_reserved2_MASK  0x00080000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_reserved2_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: DRIVE_PAD_CTL :: reserved3 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_reserved3_MASK  0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_reserved3_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: DRIVE_PAD_CTL :: reserved4 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_reserved4_MASK  0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_reserved4_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: DRIVE_PAD_CTL :: reserved5 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_reserved5_MASK  0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_reserved5_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff80000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DRIVE_PAD_CTL :: reserved1 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_reserved1_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_reserved1_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DRIVE_PAD_CTL :: reserved2 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_reserved2_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DRIVE_PAD_CTL :: reserved3 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_reserved3_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_reserved3_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *STATIC_PAD_CTL - pad rx and tx characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: reserved0 [31:21] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_reserved0_SHIFT 21
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_DQS_MODE_MASK  0x00100000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: reserved1 [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_reserved1_SHIFT 18
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_EDC_MODE_MASK  0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: reserved2 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_reserved2_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_reserved2_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_DM_MODE_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_DM_MODE_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: reserved3 [11:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_reserved3_MASK 0x00000c00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_reserved3_SHIFT 10
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: RX_LS [08:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_RX_LS_MASK     0x00000100
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_RX_LS_SHIFT    8
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_RX_LS_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_TX_MODE_MASK   0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_TX_MODE_SHIFT  4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: reserved4 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_reserved4_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_reserved4_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_RX_MODE_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_RX_MODE_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_reserved0_SHIFT 16
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: WR_PREAMBLE_MODE :: DQS [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQS_MASK     0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQS_SHIFT    8
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQS_DEFAULT  0x0000000e
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_reserved1_SHIFT 5
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
+
+/***************************************************************************
+ *ODT_CONTROL - Read channel ODT control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: ODT_CONTROL :: reserved0 [31:07] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_reserved0_MASK    0xffffff80
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_reserved0_SHIFT   7
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: ODT_CONTROL :: ODT_ENABLE [06:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_ODT_ENABLE_MASK   0x00000040
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_ODT_ENABLE_SHIFT  6
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
+
+/***************************************************************************
+ *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_reserved0_SHIFT 6
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_UPDATE_MASK   0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_UPDATE_SHIFT  2
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_MONITOR_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_MONITOR_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_CONTROL :: INIT [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_INIT_MASK     0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_INIT_SHIFT    0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_CONTROL_INIT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_STATUS :: reserved0 [31:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_reserved0_SHIFT 25
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_STATUS :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_reserved1_SHIFT 11
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_CRCWL_MASK    0x00000700
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_CRCWL_SHIFT   8
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_reserved2_SHIFT 6
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_CRCRL_MASK    0x00000030
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_CRCRL_SHIFT   4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_reserved3_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_WR_FAIL_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_WR_FAIL_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_WR_PASS_MASK   0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_WR_PASS_SHIFT  2
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_RD_FAIL_MASK   0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_RD_FAIL_SHIFT  1
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_RD_PASS_MASK   0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_RD_PASS_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_COUNT :: reserved0 [31:28] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_COUNT_reserved0_MASK  0xf0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_COUNT_reserved0_SHIFT 28
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_COUNT_WR_COUNT_MASK   0x0fff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_COUNT_WR_COUNT_SHIFT  16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_COUNT :: reserved1 [15:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_COUNT_reserved1_MASK  0x0000f000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_COUNT_reserved1_SHIFT 12
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_COUNT_RD_COUNT_MASK   0x00000fff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_COUNT_RD_COUNT_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_0_1 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_1_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_0_1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_0_2.h b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_0_2.h
new file mode 100644
index 0000000..c097899
--- /dev/null
+++ b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_0_2.h
@@ -0,0 +1,2074 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Oct 17 03:11:32 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR34_PHY_BYTE_LANE_0_2_H__
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_H__
+
+/***************************************************************************
+ *DDR34_PHY_BYTE_LANE_0_2 - DDR34 DDR34 Byte Lane #0 control registers 2
+ ***************************************************************************/
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_P 0x003d6400 /* Write channel DQS-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_N 0x003d6404 /* Write channel DQS-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ0 0x003d6408 /* Write channel DQ0 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ1 0x003d640c /* Write channel DQ1 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ2 0x003d6410 /* Write channel DQ2 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ3 0x003d6414 /* Write channel DQ3 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ4 0x003d6418 /* Write channel DQ4 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ5 0x003d641c /* Write channel DQ5 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ6 0x003d6420 /* Write channel DQ6 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ7 0x003d6424 /* Write channel DQ7 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DM 0x003d6428 /* Write channel DM VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_EDC 0x003d642c /* Write channel EDC VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSP 0x003d6430 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSN 0x003d6434 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0P 0x003d6438 /* Read channel DQ0-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0N 0x003d643c /* Read channel DQ0-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1P 0x003d6440 /* Read channel DQ1-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1N 0x003d6444 /* Read channel DQ1-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2P 0x003d6448 /* Read channel DQ2-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2N 0x003d644c /* Read channel DQ2-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3P 0x003d6450 /* Read channel DQ3-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3N 0x003d6454 /* Read channel DQ3-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4P 0x003d6458 /* Read channel DQ4-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4N 0x003d645c /* Read channel DQ4-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5P 0x003d6460 /* Read channel DQ5-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5N 0x003d6464 /* Read channel DQ5-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6P 0x003d6468 /* Read channel DQ6-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6N 0x003d646c /* Read channel DQ6-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7P 0x003d6470 /* Read channel DQ7-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7N 0x003d6474 /* Read channel DQ7-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMP 0x003d6478 /* Read channel DM-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMN 0x003d647c /* Read channel DM-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCP 0x003d6480 /* Read channel EDC-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCN 0x003d6484 /* Read channel EDC-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS0 0x003d6488 /* Read channel CS_N[0] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS1 0x003d648c /* Read channel CS_N[1] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CLK_CONTROL 0x003d6490 /* Write leveling VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DLY_CYC 0x003d64a0 /* Read enable bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_CHAN_DLY_CYC 0x003d64a4 /* Write leveling bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_CONTROL 0x003d64b0 /* Read channel datapath control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_ADDR 0x003d64b4 /* Read fifo addresss pointer register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_DATA 0x003d64b8 /* Read fifo data register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_DM_DBI 0x003d64bc /* Read fifo dm/dbi register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_STATUS 0x003d64c0 /* Read fifo status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_CLEAR 0x003d64c4 /* Read fifo status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL 0x003d64c8 /* Idle mode SSTL pad control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL 0x003d64cc /* SSTL pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DRIVE_PAD_CTL 0x003d64d0 /* SSTL read enable pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL 0x003d64d4 /* pad rx and tx characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_PREAMBLE_MODE 0x003d64d8 /* Write cycle preamble control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_ODT_CONTROL 0x003d64e0 /* Read channel ODT control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_CONTROL 0x003d64f0 /* GDDR5M EDC digital phase detector control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS 0x003d64f4 /* GDDR5M EDC digital phase detector status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_CONTROL 0x003d64f8 /* GDDR5M EDC digital phase detector output signal control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_STATUS 0x003d64fc /* GDDR5M EDC digital phase detector output signal status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_STATUS_CLEAR 0x003d6500 /* GDDR5M EDC digital phase detector output signal status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL 0x003d6504 /* GDDR5M EDC signal path CRC control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_STATUS 0x003d6508 /* GDDR5M EDC signal path CRC status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_COUNT 0x003d650c /* GDDR5M EDC signal path CRC counter register */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_STATUS_CLEAR 0x003d6510 /* GDDR5M EDC signal path CRC counter register */
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ0_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ1_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ2_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ3_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ4_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ5_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ6_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ7_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DM - Write channel DM VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DM_BUSY_MASK   0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DM_BUSY_SHIFT  31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DM_FORCE_MASK  0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DM :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DM_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_DM :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_EDC_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_EDC :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_EDC_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_WR_EDC :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMP_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMN_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CLK_CONTROL - Write leveling VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CLK_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CLK_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CLK_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CLK_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CLK_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CLK_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CLK_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CLK_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CLK_CONTROL_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CLK_CONTROL_ADJ_EN_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CLK_CONTROL_ADJ_EN_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CLK_CONTROL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: RD_EN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DLY_CYC_BUSY_MASK       0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DLY_CYC_BUSY_SHIFT      31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DLY_CYC_BUSY_DEFAULT    0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DLY_CYC_reserved0_MASK  0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: RD_EN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DLY_CYC_FORCE_MASK      0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DLY_CYC_FORCE_SHIFT     16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DLY_CYC_FORCE_DEFAULT   0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DLY_CYC_reserved1_MASK  0x0000ff00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DLY_CYC_reserved1_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_CHAN_DLY_CYC_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_CHAN_DLY_CYC_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_CHAN_DLY_CYC_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_CHAN_DLY_CYC_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_CHAN_DLY_CYC_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_CHAN_DLY_CYC_CYCLES_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_CHAN_DLY_CYC_CYCLES_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_CONTROL - Read channel datapath control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: READ_CONTROL :: reserved0 [31:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_CONTROL_reserved0_MASK   0xffffffe0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_CONTROL_reserved0_SHIFT  5
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: READ_CONTROL :: MODE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_CONTROL_MODE_MASK        0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_CONTROL_MODE_SHIFT       4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_CONTROL_MODE_DEFAULT     0x00000001
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: READ_CONTROL :: reserved1 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_CONTROL_reserved1_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_CONTROL_reserved1_SHIFT  3
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_CONTROL_RD_DATA_DLY_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
+
+/***************************************************************************
+ *READ_FIFO_ADDR - Read fifo addresss pointer register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: READ_FIFO_ADDR :: reserved0 [31:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_ADDR_reserved0_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: READ_FIFO_ADDR :: ADDR [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_ADDR_ADDR_MASK      0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_ADDR_ADDR_SHIFT     0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_ADDR_ADDR_DEFAULT   0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA - Read fifo data register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: READ_FIFO_DATA :: DATA [31:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_DATA_DATA_MASK      0xffffffff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_DATA_DATA_SHIFT     0
+
+/***************************************************************************
+ *READ_FIFO_DM_DBI - Read fifo dm/dbi register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_DM_DBI_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_DM_DBI_DM_DBI_MASK  0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: READ_FIFO_STATUS :: reserved0 [31:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_STATUS_reserved0_SHIFT 2
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_CLEAR_CLEAR_MASK    0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_CLEAR_CLEAR_SHIFT   0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_IDLE_MASK    0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_IDLE_SHIFT   31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: IDLE_PAD_CONTROL :: reserved1 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_reserved1_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_reserved1_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_RXENB_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_RXENB_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_IDDQ_MASK    0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_IDDQ_SHIFT   2
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_DOUT_N_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_DOUT_P_MASK  0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: DRIVE_PAD_CTL :: reserved0 [31:29] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_reserved0_MASK  0xe0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_reserved0_SHIFT 29
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [28:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x1e000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: DRIVE_PAD_CTL :: reserved1 [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_reserved1_MASK  0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_reserved1_SHIFT 24
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [23:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x00f00000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: DRIVE_PAD_CTL :: reserved2 [19:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_reserved2_MASK  0x00080000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_reserved2_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: DRIVE_PAD_CTL :: reserved3 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_reserved3_MASK  0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_reserved3_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: DRIVE_PAD_CTL :: reserved4 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_reserved4_MASK  0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_reserved4_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: DRIVE_PAD_CTL :: reserved5 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_reserved5_MASK  0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_reserved5_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff80000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: RD_EN_DRIVE_PAD_CTL :: reserved1 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DRIVE_PAD_CTL_reserved1_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DRIVE_PAD_CTL_reserved1_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: RD_EN_DRIVE_PAD_CTL :: reserved2 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DRIVE_PAD_CTL_reserved2_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DRIVE_PAD_CTL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: RD_EN_DRIVE_PAD_CTL :: reserved3 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DRIVE_PAD_CTL_reserved3_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DRIVE_PAD_CTL_reserved3_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *STATIC_PAD_CTL - pad rx and tx characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: STATIC_PAD_CTL :: reserved0 [31:21] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_reserved0_SHIFT 21
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_DQS_MODE_MASK  0x00100000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: STATIC_PAD_CTL :: reserved1 [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_reserved1_SHIFT 18
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_EDC_MODE_MASK  0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: STATIC_PAD_CTL :: reserved2 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_reserved2_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_reserved2_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_DM_MODE_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_DM_MODE_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: STATIC_PAD_CTL :: reserved3 [11:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_reserved3_MASK 0x00000c00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_reserved3_SHIFT 10
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: STATIC_PAD_CTL :: RX_LS [08:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_RX_LS_MASK     0x00000100
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_RX_LS_SHIFT    8
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_RX_LS_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_TX_MODE_MASK   0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_TX_MODE_SHIFT  4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: STATIC_PAD_CTL :: reserved4 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_reserved4_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_reserved4_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_RX_MODE_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_RX_MODE_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_PREAMBLE_MODE_reserved0_SHIFT 16
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: WR_PREAMBLE_MODE :: DQS [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_PREAMBLE_MODE_DQS_MASK     0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_PREAMBLE_MODE_DQS_SHIFT    8
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_PREAMBLE_MODE_DQS_DEFAULT  0x0000000e
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_PREAMBLE_MODE_reserved1_SHIFT 5
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
+
+/***************************************************************************
+ *ODT_CONTROL - Read channel ODT control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: ODT_CONTROL :: reserved0 [31:07] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_ODT_CONTROL_reserved0_MASK    0xffffff80
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_ODT_CONTROL_reserved0_SHIFT   7
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: ODT_CONTROL :: ODT_ENABLE [06:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_ODT_CONTROL_ODT_ENABLE_MASK   0x00000040
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_ODT_CONTROL_ODT_ENABLE_SHIFT  6
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
+
+/***************************************************************************
+ *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_CONTROL_reserved0_SHIFT 6
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_CONTROL_UPDATE_MASK   0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_CONTROL_UPDATE_SHIFT  2
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_CONTROL_MONITOR_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_CONTROL_MONITOR_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_CONTROL :: INIT [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_CONTROL_INIT_MASK     0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_CONTROL_INIT_SHIFT    0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_CONTROL_INIT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_STATUS :: reserved0 [31:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_reserved0_SHIFT 25
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_STATUS :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_CRC_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_CRC_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_reserved1_SHIFT 11
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_CRCWL_MASK    0x00000700
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_CRCWL_SHIFT   8
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_reserved2_SHIFT 6
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_CRCRL_MASK    0x00000030
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_CRCRL_SHIFT   4
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_reserved3_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_CRC_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_STATUS_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_STATUS_WR_FAIL_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_STATUS_WR_FAIL_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_STATUS_WR_PASS_MASK   0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_STATUS_WR_PASS_SHIFT  2
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_STATUS_RD_FAIL_MASK   0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_STATUS_RD_FAIL_SHIFT  1
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_STATUS_RD_PASS_MASK   0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_STATUS_RD_PASS_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_CRC_COUNT :: reserved0 [31:28] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_COUNT_reserved0_MASK  0xf0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_COUNT_reserved0_SHIFT 28
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_COUNT_WR_COUNT_MASK   0x0fff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_COUNT_WR_COUNT_SHIFT  16
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_CRC_COUNT :: reserved1 [15:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_COUNT_reserved1_MASK  0x0000f000
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_COUNT_reserved1_SHIFT 12
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_COUNT_RD_COUNT_MASK   0x00000fff
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_COUNT_RD_COUNT_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_0_2 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_0_2_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_0_2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_1_0.h b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_1_0.h
new file mode 100644
index 0000000..f0aea5d
--- /dev/null
+++ b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_1_0.h
@@ -0,0 +1,2074 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Oct 17 03:11:32 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR34_PHY_BYTE_LANE_1_0_H__
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_H__
+
+/***************************************************************************
+ *DDR34_PHY_BYTE_LANE_1_0 - DDR34 DDR34 Byte Lane #1 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P 0x003b6600 /* Write channel DQS-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N 0x003b6604 /* Write channel DQS-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0 0x003b6608 /* Write channel DQ0 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1 0x003b660c /* Write channel DQ1 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2 0x003b6610 /* Write channel DQ2 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3 0x003b6614 /* Write channel DQ3 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4 0x003b6618 /* Write channel DQ4 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5 0x003b661c /* Write channel DQ5 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6 0x003b6620 /* Write channel DQ6 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7 0x003b6624 /* Write channel DQ7 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM 0x003b6628 /* Write channel DM VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC 0x003b662c /* Write channel EDC VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP 0x003b6630 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN 0x003b6634 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P 0x003b6638 /* Read channel DQ0-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N 0x003b663c /* Read channel DQ0-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P 0x003b6640 /* Read channel DQ1-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N 0x003b6644 /* Read channel DQ1-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P 0x003b6648 /* Read channel DQ2-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N 0x003b664c /* Read channel DQ2-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P 0x003b6650 /* Read channel DQ3-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N 0x003b6654 /* Read channel DQ3-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P 0x003b6658 /* Read channel DQ4-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N 0x003b665c /* Read channel DQ4-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P 0x003b6660 /* Read channel DQ5-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N 0x003b6664 /* Read channel DQ5-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P 0x003b6668 /* Read channel DQ6-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N 0x003b666c /* Read channel DQ6-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P 0x003b6670 /* Read channel DQ7-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N 0x003b6674 /* Read channel DQ7-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP 0x003b6678 /* Read channel DM-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN 0x003b667c /* Read channel DM-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP 0x003b6680 /* Read channel EDC-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN 0x003b6684 /* Read channel EDC-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0 0x003b6688 /* Read channel CS_N[0] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1 0x003b668c /* Read channel CS_N[1] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL 0x003b6690 /* Write leveling VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC 0x003b66a0 /* Read enable bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC 0x003b66a4 /* Write leveling bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL 0x003b66b0 /* Read channel datapath control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR 0x003b66b4 /* Read fifo addresss pointer register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DATA 0x003b66b8 /* Read fifo data register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DM_DBI 0x003b66bc /* Read fifo dm/dbi register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS 0x003b66c0 /* Read fifo status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR 0x003b66c4 /* Read fifo status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL 0x003b66c8 /* Idle mode SSTL pad control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL 0x003b66cc /* SSTL pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL 0x003b66d0 /* SSTL read enable pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL 0x003b66d4 /* pad rx and tx characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE 0x003b66d8 /* Write cycle preamble control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL 0x003b66e0 /* Read channel ODT control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL 0x003b66f0 /* GDDR5M EDC digital phase detector control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS 0x003b66f4 /* GDDR5M EDC digital phase detector status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL 0x003b66f8 /* GDDR5M EDC digital phase detector output signal control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS 0x003b66fc /* GDDR5M EDC digital phase detector output signal status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR 0x003b6700 /* GDDR5M EDC digital phase detector output signal status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL 0x003b6704 /* GDDR5M EDC signal path CRC control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS 0x003b6708 /* GDDR5M EDC signal path CRC status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT 0x003b670c /* GDDR5M EDC signal path CRC counter register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR 0x003b6710 /* GDDR5M EDC signal path CRC counter register */
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DM - Write channel DM VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_BUSY_MASK   0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_BUSY_SHIFT  31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_FORCE_MASK  0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_DM :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_WR_EDC :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CLK_CONTROL - Write leveling VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_ADJ_EN_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_BUSY_MASK       0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_BUSY_SHIFT      31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_BUSY_DEFAULT    0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_reserved0_MASK  0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_FORCE_MASK      0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_FORCE_SHIFT     16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_FORCE_DEFAULT   0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_reserved1_MASK  0x0000ff00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_reserved1_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_CYCLES_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_CYCLES_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_CONTROL - Read channel datapath control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: READ_CONTROL :: reserved0 [31:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_reserved0_MASK   0xffffffe0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_reserved0_SHIFT  5
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: READ_CONTROL :: MODE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_MODE_MASK        0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_MODE_SHIFT       4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_MODE_DEFAULT     0x00000001
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: READ_CONTROL :: reserved1 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_reserved1_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_reserved1_SHIFT  3
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_RD_DATA_DLY_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
+
+/***************************************************************************
+ *READ_FIFO_ADDR - Read fifo addresss pointer register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR_reserved0_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_ADDR :: ADDR [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR_ADDR_MASK      0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR_ADDR_SHIFT     0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_ADDR_ADDR_DEFAULT   0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA - Read fifo data register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_DATA :: DATA [31:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DATA_DATA_MASK      0xffffffff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DATA_DATA_SHIFT     0
+
+/***************************************************************************
+ *READ_FIFO_DM_DBI - Read fifo dm/dbi register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DM_DBI_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DM_DBI_DM_DBI_MASK  0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_STATUS :: reserved0 [31:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_reserved0_SHIFT 2
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR_CLEAR_MASK    0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR_CLEAR_SHIFT   0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDLE_MASK    0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDLE_SHIFT   31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: reserved1 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_reserved1_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_reserved1_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_RXENB_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_RXENB_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDDQ_MASK    0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDDQ_SHIFT   2
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_DOUT_N_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_DOUT_P_MASK  0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: reserved0 [31:29] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_reserved0_MASK  0xe0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_reserved0_SHIFT 29
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [28:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x1e000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: reserved1 [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_reserved1_MASK  0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_reserved1_SHIFT 24
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [23:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x00f00000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: reserved2 [19:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_reserved2_MASK  0x00080000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_reserved2_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: reserved3 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_reserved3_MASK  0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_reserved3_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: reserved4 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_reserved4_MASK  0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_reserved4_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: reserved5 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_reserved5_MASK  0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_reserved5_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff80000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: reserved1 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_reserved1_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_reserved1_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: reserved2 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_reserved2_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: reserved3 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_reserved3_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_reserved3_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *STATIC_PAD_CTL - pad rx and tx characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved0 [31:21] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved0_SHIFT 21
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_MODE_MASK  0x00100000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved1 [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved1_SHIFT 18
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_EDC_MODE_MASK  0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved2 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved2_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved2_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DM_MODE_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DM_MODE_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved3 [11:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved3_MASK 0x00000c00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved3_SHIFT 10
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: RX_LS [08:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RX_LS_MASK     0x00000100
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RX_LS_SHIFT    8
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RX_LS_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_TX_MODE_MASK   0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_TX_MODE_SHIFT  4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: reserved4 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved4_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_reserved4_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RX_MODE_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RX_MODE_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_reserved0_SHIFT 16
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: DQS [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_MASK     0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_SHIFT    8
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_DEFAULT  0x0000000e
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_reserved1_SHIFT 5
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
+
+/***************************************************************************
+ *ODT_CONTROL - Read channel ODT control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: ODT_CONTROL :: reserved0 [31:07] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_reserved0_MASK    0xffffff80
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_reserved0_SHIFT   7
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: ODT_CONTROL :: ODT_ENABLE [06:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_ENABLE_MASK   0x00000040
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_ENABLE_SHIFT  6
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
+
+/***************************************************************************
+ *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_reserved0_SHIFT 6
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_UPDATE_MASK   0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_UPDATE_SHIFT  2
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_MONITOR_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_MONITOR_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_CONTROL :: INIT [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_INIT_MASK     0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_INIT_SHIFT    0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_CONTROL_INIT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: reserved0 [31:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_reserved0_SHIFT 25
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved1_SHIFT 11
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCWL_MASK    0x00000700
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCWL_SHIFT   8
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved2_SHIFT 6
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCRL_MASK    0x00000030
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCRL_SHIFT   4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_reserved3_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_WR_FAIL_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_WR_FAIL_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_WR_PASS_MASK   0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_WR_PASS_SHIFT  2
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_RD_FAIL_MASK   0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_RD_FAIL_SHIFT  1
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_RD_PASS_MASK   0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_RD_PASS_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_COUNT :: reserved0 [31:28] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_reserved0_MASK  0xf0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_reserved0_SHIFT 28
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_WR_COUNT_MASK   0x0fff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_WR_COUNT_SHIFT  16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_COUNT :: reserved1 [15:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_reserved1_MASK  0x0000f000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_reserved1_SHIFT 12
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_RD_COUNT_MASK   0x00000fff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_RD_COUNT_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_1_0 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_1_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_1_1.h b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_1_1.h
new file mode 100644
index 0000000..887c6d0
--- /dev/null
+++ b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_1_1.h
@@ -0,0 +1,2074 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Oct 17 03:11:32 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR34_PHY_BYTE_LANE_1_1_H__
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_H__
+
+/***************************************************************************
+ *DDR34_PHY_BYTE_LANE_1_1 - DDR34 DDR34 Byte Lane #1 control registers 1
+ ***************************************************************************/
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P 0x003c6600 /* Write channel DQS-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N 0x003c6604 /* Write channel DQS-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0 0x003c6608 /* Write channel DQ0 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1 0x003c660c /* Write channel DQ1 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2 0x003c6610 /* Write channel DQ2 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3 0x003c6614 /* Write channel DQ3 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4 0x003c6618 /* Write channel DQ4 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5 0x003c661c /* Write channel DQ5 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6 0x003c6620 /* Write channel DQ6 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7 0x003c6624 /* Write channel DQ7 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM 0x003c6628 /* Write channel DM VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC 0x003c662c /* Write channel EDC VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP 0x003c6630 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN 0x003c6634 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P 0x003c6638 /* Read channel DQ0-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N 0x003c663c /* Read channel DQ0-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P 0x003c6640 /* Read channel DQ1-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N 0x003c6644 /* Read channel DQ1-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P 0x003c6648 /* Read channel DQ2-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N 0x003c664c /* Read channel DQ2-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P 0x003c6650 /* Read channel DQ3-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N 0x003c6654 /* Read channel DQ3-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P 0x003c6658 /* Read channel DQ4-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N 0x003c665c /* Read channel DQ4-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P 0x003c6660 /* Read channel DQ5-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N 0x003c6664 /* Read channel DQ5-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P 0x003c6668 /* Read channel DQ6-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N 0x003c666c /* Read channel DQ6-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P 0x003c6670 /* Read channel DQ7-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N 0x003c6674 /* Read channel DQ7-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP 0x003c6678 /* Read channel DM-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN 0x003c667c /* Read channel DM-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP 0x003c6680 /* Read channel EDC-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN 0x003c6684 /* Read channel EDC-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0 0x003c6688 /* Read channel CS_N[0] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1 0x003c668c /* Read channel CS_N[1] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL 0x003c6690 /* Write leveling VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC 0x003c66a0 /* Read enable bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC 0x003c66a4 /* Write leveling bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_CONTROL 0x003c66b0 /* Read channel datapath control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_ADDR 0x003c66b4 /* Read fifo addresss pointer register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_DATA 0x003c66b8 /* Read fifo data register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_DM_DBI 0x003c66bc /* Read fifo dm/dbi register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_STATUS 0x003c66c0 /* Read fifo status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_CLEAR 0x003c66c4 /* Read fifo status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL 0x003c66c8 /* Idle mode SSTL pad control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL 0x003c66cc /* SSTL pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL 0x003c66d0 /* SSTL read enable pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL 0x003c66d4 /* pad rx and tx characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE 0x003c66d8 /* Write cycle preamble control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL 0x003c66e0 /* Read channel ODT control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL 0x003c66f0 /* GDDR5M EDC digital phase detector control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS 0x003c66f4 /* GDDR5M EDC digital phase detector status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL 0x003c66f8 /* GDDR5M EDC digital phase detector output signal control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS 0x003c66fc /* GDDR5M EDC digital phase detector output signal status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_CLEAR 0x003c6700 /* GDDR5M EDC digital phase detector output signal status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL 0x003c6704 /* GDDR5M EDC signal path CRC control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS 0x003c6708 /* GDDR5M EDC signal path CRC status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_COUNT 0x003c670c /* GDDR5M EDC signal path CRC counter register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_CLEAR 0x003c6710 /* GDDR5M EDC signal path CRC counter register */
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DM - Write channel DM VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_BUSY_MASK   0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_BUSY_SHIFT  31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_FORCE_MASK  0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DM :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_DM :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_EDC :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_WR_EDC :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CLK_CONTROL - Write leveling VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CLK_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CLK_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_ADJ_EN_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_ADJ_EN_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_BUSY_MASK       0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_BUSY_SHIFT      31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_BUSY_DEFAULT    0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_reserved0_MASK  0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_FORCE_MASK      0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_FORCE_SHIFT     16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_FORCE_DEFAULT   0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_reserved1_MASK  0x0000ff00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_reserved1_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_CYCLES_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_CYCLES_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_CONTROL - Read channel datapath control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: READ_CONTROL :: reserved0 [31:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_CONTROL_reserved0_MASK   0xffffffe0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_CONTROL_reserved0_SHIFT  5
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: READ_CONTROL :: MODE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_CONTROL_MODE_MASK        0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_CONTROL_MODE_SHIFT       4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_CONTROL_MODE_DEFAULT     0x00000001
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: READ_CONTROL :: reserved1 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_CONTROL_reserved1_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_CONTROL_reserved1_SHIFT  3
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_CONTROL_RD_DATA_DLY_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
+
+/***************************************************************************
+ *READ_FIFO_ADDR - Read fifo addresss pointer register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: READ_FIFO_ADDR :: reserved0 [31:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_ADDR_reserved0_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: READ_FIFO_ADDR :: ADDR [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_ADDR_ADDR_MASK      0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_ADDR_ADDR_SHIFT     0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_ADDR_ADDR_DEFAULT   0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA - Read fifo data register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: READ_FIFO_DATA :: DATA [31:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_DATA_DATA_MASK      0xffffffff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_DATA_DATA_SHIFT     0
+
+/***************************************************************************
+ *READ_FIFO_DM_DBI - Read fifo dm/dbi register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_DM_DBI_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_DM_DBI_DM_DBI_MASK  0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: READ_FIFO_STATUS :: reserved0 [31:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_STATUS_reserved0_SHIFT 2
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_CLEAR_CLEAR_MASK    0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_CLEAR_CLEAR_SHIFT   0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_IDLE_MASK    0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_IDLE_SHIFT   31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: IDLE_PAD_CONTROL :: reserved1 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_reserved1_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_reserved1_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_RXENB_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_RXENB_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_IDDQ_MASK    0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_IDDQ_SHIFT   2
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_DOUT_N_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_DOUT_P_MASK  0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: DRIVE_PAD_CTL :: reserved0 [31:29] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_reserved0_MASK  0xe0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_reserved0_SHIFT 29
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [28:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x1e000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: DRIVE_PAD_CTL :: reserved1 [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_reserved1_MASK  0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_reserved1_SHIFT 24
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [23:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x00f00000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: DRIVE_PAD_CTL :: reserved2 [19:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_reserved2_MASK  0x00080000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_reserved2_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: DRIVE_PAD_CTL :: reserved3 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_reserved3_MASK  0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_reserved3_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: DRIVE_PAD_CTL :: reserved4 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_reserved4_MASK  0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_reserved4_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: DRIVE_PAD_CTL :: reserved5 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_reserved5_MASK  0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_reserved5_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff80000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DRIVE_PAD_CTL :: reserved1 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_reserved1_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_reserved1_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DRIVE_PAD_CTL :: reserved2 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_reserved2_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DRIVE_PAD_CTL :: reserved3 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_reserved3_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_reserved3_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *STATIC_PAD_CTL - pad rx and tx characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: reserved0 [31:21] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_reserved0_SHIFT 21
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_DQS_MODE_MASK  0x00100000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: reserved1 [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_reserved1_SHIFT 18
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_EDC_MODE_MASK  0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: reserved2 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_reserved2_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_reserved2_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_DM_MODE_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_DM_MODE_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: reserved3 [11:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_reserved3_MASK 0x00000c00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_reserved3_SHIFT 10
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: RX_LS [08:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_RX_LS_MASK     0x00000100
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_RX_LS_SHIFT    8
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_RX_LS_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_TX_MODE_MASK   0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_TX_MODE_SHIFT  4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: reserved4 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_reserved4_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_reserved4_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_RX_MODE_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_RX_MODE_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_reserved0_SHIFT 16
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: WR_PREAMBLE_MODE :: DQS [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQS_MASK     0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQS_SHIFT    8
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQS_DEFAULT  0x0000000e
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_reserved1_SHIFT 5
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
+
+/***************************************************************************
+ *ODT_CONTROL - Read channel ODT control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: ODT_CONTROL :: reserved0 [31:07] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_reserved0_MASK    0xffffff80
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_reserved0_SHIFT   7
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: ODT_CONTROL :: ODT_ENABLE [06:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_ODT_ENABLE_MASK   0x00000040
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_ODT_ENABLE_SHIFT  6
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
+
+/***************************************************************************
+ *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_reserved0_SHIFT 6
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_UPDATE_MASK   0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_UPDATE_SHIFT  2
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_MONITOR_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_MONITOR_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_CONTROL :: INIT [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_INIT_MASK     0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_INIT_SHIFT    0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_CONTROL_INIT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_STATUS :: reserved0 [31:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_reserved0_SHIFT 25
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_STATUS :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_reserved1_SHIFT 11
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_CRCWL_MASK    0x00000700
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_CRCWL_SHIFT   8
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_reserved2_SHIFT 6
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_CRCRL_MASK    0x00000030
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_CRCRL_SHIFT   4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_reserved3_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_WR_FAIL_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_WR_FAIL_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_WR_PASS_MASK   0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_WR_PASS_SHIFT  2
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_RD_FAIL_MASK   0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_RD_FAIL_SHIFT  1
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_RD_PASS_MASK   0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_RD_PASS_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_COUNT :: reserved0 [31:28] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_COUNT_reserved0_MASK  0xf0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_COUNT_reserved0_SHIFT 28
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_COUNT_WR_COUNT_MASK   0x0fff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_COUNT_WR_COUNT_SHIFT  16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_COUNT :: reserved1 [15:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_COUNT_reserved1_MASK  0x0000f000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_COUNT_reserved1_SHIFT 12
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_COUNT_RD_COUNT_MASK   0x00000fff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_COUNT_RD_COUNT_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_1_1 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_1_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_1_1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_1_2.h b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_1_2.h
new file mode 100644
index 0000000..b08b24e
--- /dev/null
+++ b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_1_2.h
@@ -0,0 +1,2074 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Oct 17 03:11:32 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR34_PHY_BYTE_LANE_1_2_H__
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_H__
+
+/***************************************************************************
+ *DDR34_PHY_BYTE_LANE_1_2 - DDR34 DDR34 Byte Lane #1 control registers 2
+ ***************************************************************************/
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_P 0x003d6600 /* Write channel DQS-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_N 0x003d6604 /* Write channel DQS-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ0 0x003d6608 /* Write channel DQ0 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ1 0x003d660c /* Write channel DQ1 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ2 0x003d6610 /* Write channel DQ2 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ3 0x003d6614 /* Write channel DQ3 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ4 0x003d6618 /* Write channel DQ4 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ5 0x003d661c /* Write channel DQ5 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ6 0x003d6620 /* Write channel DQ6 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ7 0x003d6624 /* Write channel DQ7 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DM 0x003d6628 /* Write channel DM VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_EDC 0x003d662c /* Write channel EDC VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSP 0x003d6630 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSN 0x003d6634 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0P 0x003d6638 /* Read channel DQ0-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0N 0x003d663c /* Read channel DQ0-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1P 0x003d6640 /* Read channel DQ1-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1N 0x003d6644 /* Read channel DQ1-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2P 0x003d6648 /* Read channel DQ2-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2N 0x003d664c /* Read channel DQ2-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3P 0x003d6650 /* Read channel DQ3-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3N 0x003d6654 /* Read channel DQ3-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4P 0x003d6658 /* Read channel DQ4-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4N 0x003d665c /* Read channel DQ4-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5P 0x003d6660 /* Read channel DQ5-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5N 0x003d6664 /* Read channel DQ5-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6P 0x003d6668 /* Read channel DQ6-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6N 0x003d666c /* Read channel DQ6-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7P 0x003d6670 /* Read channel DQ7-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7N 0x003d6674 /* Read channel DQ7-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMP 0x003d6678 /* Read channel DM-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMN 0x003d667c /* Read channel DM-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCP 0x003d6680 /* Read channel EDC-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCN 0x003d6684 /* Read channel EDC-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS0 0x003d6688 /* Read channel CS_N[0] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS1 0x003d668c /* Read channel CS_N[1] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CLK_CONTROL 0x003d6690 /* Write leveling VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DLY_CYC 0x003d66a0 /* Read enable bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_CHAN_DLY_CYC 0x003d66a4 /* Write leveling bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_CONTROL 0x003d66b0 /* Read channel datapath control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_ADDR 0x003d66b4 /* Read fifo addresss pointer register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_DATA 0x003d66b8 /* Read fifo data register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_DM_DBI 0x003d66bc /* Read fifo dm/dbi register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_STATUS 0x003d66c0 /* Read fifo status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_CLEAR 0x003d66c4 /* Read fifo status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL 0x003d66c8 /* Idle mode SSTL pad control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL 0x003d66cc /* SSTL pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DRIVE_PAD_CTL 0x003d66d0 /* SSTL read enable pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL 0x003d66d4 /* pad rx and tx characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_PREAMBLE_MODE 0x003d66d8 /* Write cycle preamble control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_ODT_CONTROL 0x003d66e0 /* Read channel ODT control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_CONTROL 0x003d66f0 /* GDDR5M EDC digital phase detector control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS 0x003d66f4 /* GDDR5M EDC digital phase detector status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_CONTROL 0x003d66f8 /* GDDR5M EDC digital phase detector output signal control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_STATUS 0x003d66fc /* GDDR5M EDC digital phase detector output signal status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_STATUS_CLEAR 0x003d6700 /* GDDR5M EDC digital phase detector output signal status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL 0x003d6704 /* GDDR5M EDC signal path CRC control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_STATUS 0x003d6708 /* GDDR5M EDC signal path CRC status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_COUNT 0x003d670c /* GDDR5M EDC signal path CRC counter register */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_STATUS_CLEAR 0x003d6710 /* GDDR5M EDC signal path CRC counter register */
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ0_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ1_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ2_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ3_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ4_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ5_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ6_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ7_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DM - Write channel DM VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DM_BUSY_MASK   0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DM_BUSY_SHIFT  31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DM_FORCE_MASK  0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DM :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DM_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_DM :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_EDC_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_EDC :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_EDC_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_WR_EDC :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMP_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMN_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CLK_CONTROL - Write leveling VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CLK_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CLK_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CLK_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CLK_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CLK_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CLK_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CLK_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CLK_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CLK_CONTROL_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CLK_CONTROL_ADJ_EN_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CLK_CONTROL_ADJ_EN_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CLK_CONTROL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: RD_EN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DLY_CYC_BUSY_MASK       0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DLY_CYC_BUSY_SHIFT      31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DLY_CYC_BUSY_DEFAULT    0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DLY_CYC_reserved0_MASK  0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: RD_EN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DLY_CYC_FORCE_MASK      0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DLY_CYC_FORCE_SHIFT     16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DLY_CYC_FORCE_DEFAULT   0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DLY_CYC_reserved1_MASK  0x0000ff00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DLY_CYC_reserved1_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_CHAN_DLY_CYC_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_CHAN_DLY_CYC_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_CHAN_DLY_CYC_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_CHAN_DLY_CYC_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_CHAN_DLY_CYC_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_CHAN_DLY_CYC_CYCLES_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_CHAN_DLY_CYC_CYCLES_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_CONTROL - Read channel datapath control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: READ_CONTROL :: reserved0 [31:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_CONTROL_reserved0_MASK   0xffffffe0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_CONTROL_reserved0_SHIFT  5
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: READ_CONTROL :: MODE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_CONTROL_MODE_MASK        0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_CONTROL_MODE_SHIFT       4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_CONTROL_MODE_DEFAULT     0x00000001
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: READ_CONTROL :: reserved1 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_CONTROL_reserved1_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_CONTROL_reserved1_SHIFT  3
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_CONTROL_RD_DATA_DLY_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
+
+/***************************************************************************
+ *READ_FIFO_ADDR - Read fifo addresss pointer register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: READ_FIFO_ADDR :: reserved0 [31:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_ADDR_reserved0_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: READ_FIFO_ADDR :: ADDR [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_ADDR_ADDR_MASK      0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_ADDR_ADDR_SHIFT     0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_ADDR_ADDR_DEFAULT   0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA - Read fifo data register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: READ_FIFO_DATA :: DATA [31:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_DATA_DATA_MASK      0xffffffff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_DATA_DATA_SHIFT     0
+
+/***************************************************************************
+ *READ_FIFO_DM_DBI - Read fifo dm/dbi register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_DM_DBI_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_DM_DBI_DM_DBI_MASK  0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: READ_FIFO_STATUS :: reserved0 [31:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_STATUS_reserved0_SHIFT 2
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_CLEAR_CLEAR_MASK    0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_CLEAR_CLEAR_SHIFT   0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_IDLE_MASK    0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_IDLE_SHIFT   31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: IDLE_PAD_CONTROL :: reserved1 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_reserved1_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_reserved1_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_RXENB_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_RXENB_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_IDDQ_MASK    0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_IDDQ_SHIFT   2
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_DOUT_N_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_DOUT_P_MASK  0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: DRIVE_PAD_CTL :: reserved0 [31:29] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_reserved0_MASK  0xe0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_reserved0_SHIFT 29
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [28:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x1e000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: DRIVE_PAD_CTL :: reserved1 [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_reserved1_MASK  0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_reserved1_SHIFT 24
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [23:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x00f00000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: DRIVE_PAD_CTL :: reserved2 [19:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_reserved2_MASK  0x00080000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_reserved2_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: DRIVE_PAD_CTL :: reserved3 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_reserved3_MASK  0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_reserved3_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: DRIVE_PAD_CTL :: reserved4 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_reserved4_MASK  0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_reserved4_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: DRIVE_PAD_CTL :: reserved5 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_reserved5_MASK  0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_reserved5_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff80000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: RD_EN_DRIVE_PAD_CTL :: reserved1 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DRIVE_PAD_CTL_reserved1_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DRIVE_PAD_CTL_reserved1_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: RD_EN_DRIVE_PAD_CTL :: reserved2 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DRIVE_PAD_CTL_reserved2_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DRIVE_PAD_CTL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: RD_EN_DRIVE_PAD_CTL :: reserved3 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DRIVE_PAD_CTL_reserved3_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DRIVE_PAD_CTL_reserved3_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *STATIC_PAD_CTL - pad rx and tx characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: STATIC_PAD_CTL :: reserved0 [31:21] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_reserved0_SHIFT 21
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_DQS_MODE_MASK  0x00100000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: STATIC_PAD_CTL :: reserved1 [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_reserved1_SHIFT 18
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_EDC_MODE_MASK  0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: STATIC_PAD_CTL :: reserved2 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_reserved2_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_reserved2_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_DM_MODE_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_DM_MODE_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: STATIC_PAD_CTL :: reserved3 [11:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_reserved3_MASK 0x00000c00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_reserved3_SHIFT 10
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: STATIC_PAD_CTL :: RX_LS [08:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_RX_LS_MASK     0x00000100
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_RX_LS_SHIFT    8
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_RX_LS_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_TX_MODE_MASK   0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_TX_MODE_SHIFT  4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: STATIC_PAD_CTL :: reserved4 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_reserved4_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_reserved4_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_RX_MODE_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_RX_MODE_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_PREAMBLE_MODE_reserved0_SHIFT 16
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: WR_PREAMBLE_MODE :: DQS [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_PREAMBLE_MODE_DQS_MASK     0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_PREAMBLE_MODE_DQS_SHIFT    8
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_PREAMBLE_MODE_DQS_DEFAULT  0x0000000e
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_PREAMBLE_MODE_reserved1_SHIFT 5
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
+
+/***************************************************************************
+ *ODT_CONTROL - Read channel ODT control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: ODT_CONTROL :: reserved0 [31:07] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_ODT_CONTROL_reserved0_MASK    0xffffff80
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_ODT_CONTROL_reserved0_SHIFT   7
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: ODT_CONTROL :: ODT_ENABLE [06:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_ODT_CONTROL_ODT_ENABLE_MASK   0x00000040
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_ODT_CONTROL_ODT_ENABLE_SHIFT  6
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
+
+/***************************************************************************
+ *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_CONTROL_reserved0_SHIFT 6
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_CONTROL_UPDATE_MASK   0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_CONTROL_UPDATE_SHIFT  2
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_CONTROL_MONITOR_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_CONTROL_MONITOR_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_CONTROL :: INIT [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_CONTROL_INIT_MASK     0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_CONTROL_INIT_SHIFT    0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_CONTROL_INIT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_STATUS :: reserved0 [31:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_reserved0_SHIFT 25
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_STATUS :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_CRC_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_CRC_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_reserved1_SHIFT 11
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_CRCWL_MASK    0x00000700
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_CRCWL_SHIFT   8
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_reserved2_SHIFT 6
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_CRCRL_MASK    0x00000030
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_CRCRL_SHIFT   4
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_reserved3_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_CRC_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_STATUS_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_STATUS_WR_FAIL_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_STATUS_WR_FAIL_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_STATUS_WR_PASS_MASK   0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_STATUS_WR_PASS_SHIFT  2
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_STATUS_RD_FAIL_MASK   0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_STATUS_RD_FAIL_SHIFT  1
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_STATUS_RD_PASS_MASK   0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_STATUS_RD_PASS_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_CRC_COUNT :: reserved0 [31:28] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_COUNT_reserved0_MASK  0xf0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_COUNT_reserved0_SHIFT 28
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_COUNT_WR_COUNT_MASK   0x0fff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_COUNT_WR_COUNT_SHIFT  16
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_CRC_COUNT :: reserved1 [15:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_COUNT_reserved1_MASK  0x0000f000
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_COUNT_reserved1_SHIFT 12
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_COUNT_RD_COUNT_MASK   0x00000fff
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_COUNT_RD_COUNT_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_1_2 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_1_2_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_1_2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_2_0.h b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_2_0.h
new file mode 100644
index 0000000..93238ff
--- /dev/null
+++ b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_2_0.h
@@ -0,0 +1,2074 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Oct 17 03:11:32 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR34_PHY_BYTE_LANE_2_0_H__
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_H__
+
+/***************************************************************************
+ *DDR34_PHY_BYTE_LANE_2_0 - DDR34 DDR34 Byte Lane #2 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P 0x003b6800 /* Write channel DQS-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N 0x003b6804 /* Write channel DQS-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0 0x003b6808 /* Write channel DQ0 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1 0x003b680c /* Write channel DQ1 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2 0x003b6810 /* Write channel DQ2 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3 0x003b6814 /* Write channel DQ3 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4 0x003b6818 /* Write channel DQ4 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5 0x003b681c /* Write channel DQ5 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6 0x003b6820 /* Write channel DQ6 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7 0x003b6824 /* Write channel DQ7 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM 0x003b6828 /* Write channel DM VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC 0x003b682c /* Write channel EDC VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP 0x003b6830 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN 0x003b6834 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P 0x003b6838 /* Read channel DQ0-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N 0x003b683c /* Read channel DQ0-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P 0x003b6840 /* Read channel DQ1-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N 0x003b6844 /* Read channel DQ1-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P 0x003b6848 /* Read channel DQ2-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N 0x003b684c /* Read channel DQ2-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P 0x003b6850 /* Read channel DQ3-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N 0x003b6854 /* Read channel DQ3-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P 0x003b6858 /* Read channel DQ4-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N 0x003b685c /* Read channel DQ4-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P 0x003b6860 /* Read channel DQ5-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N 0x003b6864 /* Read channel DQ5-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P 0x003b6868 /* Read channel DQ6-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N 0x003b686c /* Read channel DQ6-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P 0x003b6870 /* Read channel DQ7-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N 0x003b6874 /* Read channel DQ7-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP 0x003b6878 /* Read channel DM-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN 0x003b687c /* Read channel DM-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP 0x003b6880 /* Read channel EDC-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN 0x003b6884 /* Read channel EDC-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0 0x003b6888 /* Read channel CS_N[0] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1 0x003b688c /* Read channel CS_N[1] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL 0x003b6890 /* Write leveling VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC 0x003b68a0 /* Read enable bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC 0x003b68a4 /* Write leveling bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL 0x003b68b0 /* Read channel datapath control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR 0x003b68b4 /* Read fifo addresss pointer register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DATA 0x003b68b8 /* Read fifo data register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI 0x003b68bc /* Read fifo dm/dbi register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS 0x003b68c0 /* Read fifo status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR 0x003b68c4 /* Read fifo status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL 0x003b68c8 /* Idle mode SSTL pad control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL 0x003b68cc /* SSTL pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL 0x003b68d0 /* SSTL read enable pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL 0x003b68d4 /* pad rx and tx characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE 0x003b68d8 /* Write cycle preamble control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL 0x003b68e0 /* Read channel ODT control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL 0x003b68f0 /* GDDR5M EDC digital phase detector control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS 0x003b68f4 /* GDDR5M EDC digital phase detector status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL 0x003b68f8 /* GDDR5M EDC digital phase detector output signal control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS 0x003b68fc /* GDDR5M EDC digital phase detector output signal status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR 0x003b6900 /* GDDR5M EDC digital phase detector output signal status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL 0x003b6904 /* GDDR5M EDC signal path CRC control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS 0x003b6908 /* GDDR5M EDC signal path CRC status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT 0x003b690c /* GDDR5M EDC signal path CRC counter register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR 0x003b6910 /* GDDR5M EDC signal path CRC counter register */
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DM - Write channel DM VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_BUSY_MASK   0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_BUSY_SHIFT  31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_FORCE_MASK  0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_DM :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_WR_EDC :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CLK_CONTROL - Write leveling VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_ADJ_EN_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_BUSY_MASK       0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_BUSY_SHIFT      31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_BUSY_DEFAULT    0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved0_MASK  0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_FORCE_MASK      0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_FORCE_SHIFT     16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_FORCE_DEFAULT   0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved1_MASK  0x0000ff00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_reserved1_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_CYCLES_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_CYCLES_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_CONTROL - Read channel datapath control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: READ_CONTROL :: reserved0 [31:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_reserved0_MASK   0xffffffe0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_reserved0_SHIFT  5
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: READ_CONTROL :: MODE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_MODE_MASK        0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_MODE_SHIFT       4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_MODE_DEFAULT     0x00000001
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: READ_CONTROL :: reserved1 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_reserved1_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_reserved1_SHIFT  3
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_RD_DATA_DLY_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
+
+/***************************************************************************
+ *READ_FIFO_ADDR - Read fifo addresss pointer register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_reserved0_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_ADDR :: ADDR [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_ADDR_MASK      0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_ADDR_SHIFT     0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_ADDR_ADDR_DEFAULT   0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA - Read fifo data register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_DATA :: DATA [31:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DATA_DATA_MASK      0xffffffff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DATA_DATA_SHIFT     0
+
+/***************************************************************************
+ *READ_FIFO_DM_DBI - Read fifo dm/dbi register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI_DM_DBI_MASK  0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_STATUS :: reserved0 [31:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_reserved0_SHIFT 2
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_CLEAR_MASK    0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_CLEAR_SHIFT   0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDLE_MASK    0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDLE_SHIFT   31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: reserved1 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_reserved1_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_reserved1_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_RXENB_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_RXENB_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDDQ_MASK    0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDDQ_SHIFT   2
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_N_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_P_MASK  0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: reserved0 [31:29] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_reserved0_MASK  0xe0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_reserved0_SHIFT 29
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [28:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x1e000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: reserved1 [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_reserved1_MASK  0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_reserved1_SHIFT 24
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [23:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x00f00000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: reserved2 [19:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_reserved2_MASK  0x00080000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_reserved2_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: reserved3 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_reserved3_MASK  0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_reserved3_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: reserved4 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_reserved4_MASK  0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_reserved4_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: reserved5 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_reserved5_MASK  0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_reserved5_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff80000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: reserved1 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_reserved1_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_reserved1_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: reserved2 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_reserved2_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: reserved3 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_reserved3_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_reserved3_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *STATIC_PAD_CTL - pad rx and tx characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved0 [31:21] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved0_SHIFT 21
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_MODE_MASK  0x00100000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved1 [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved1_SHIFT 18
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_EDC_MODE_MASK  0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved2 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved2_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved2_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DM_MODE_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DM_MODE_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved3 [11:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved3_MASK 0x00000c00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved3_SHIFT 10
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: RX_LS [08:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RX_LS_MASK     0x00000100
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RX_LS_SHIFT    8
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RX_LS_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_TX_MODE_MASK   0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_TX_MODE_SHIFT  4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: reserved4 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved4_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_reserved4_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RX_MODE_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RX_MODE_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_reserved0_SHIFT 16
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQS [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_MASK     0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_SHIFT    8
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_DEFAULT  0x0000000e
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_reserved1_SHIFT 5
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
+
+/***************************************************************************
+ *ODT_CONTROL - Read channel ODT control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: reserved0 [31:07] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_reserved0_MASK    0xffffff80
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_reserved0_SHIFT   7
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: ODT_ENABLE [06:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_ENABLE_MASK   0x00000040
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_ENABLE_SHIFT  6
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
+
+/***************************************************************************
+ *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_reserved0_SHIFT 6
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_UPDATE_MASK   0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_UPDATE_SHIFT  2
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_MONITOR_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_MONITOR_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_CONTROL :: INIT [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_INIT_MASK     0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_INIT_SHIFT    0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_CONTROL_INIT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: reserved0 [31:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved0_SHIFT 25
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved1_SHIFT 11
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCWL_MASK    0x00000700
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCWL_SHIFT   8
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved2_SHIFT 6
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCRL_MASK    0x00000030
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCRL_SHIFT   4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_reserved3_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_FAIL_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_FAIL_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_PASS_MASK   0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_PASS_SHIFT  2
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_FAIL_MASK   0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_FAIL_SHIFT  1
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_PASS_MASK   0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_PASS_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_COUNT :: reserved0 [31:28] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_reserved0_MASK  0xf0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_reserved0_SHIFT 28
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_WR_COUNT_MASK   0x0fff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_WR_COUNT_SHIFT  16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_COUNT :: reserved1 [15:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_reserved1_MASK  0x0000f000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_reserved1_SHIFT 12
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_RD_COUNT_MASK   0x00000fff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_RD_COUNT_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_2_0 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_2_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_2_1.h b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_2_1.h
new file mode 100644
index 0000000..72caf65
--- /dev/null
+++ b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_2_1.h
@@ -0,0 +1,2074 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Oct 17 03:11:31 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR34_PHY_BYTE_LANE_2_1_H__
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_H__
+
+/***************************************************************************
+ *DDR34_PHY_BYTE_LANE_2_1 - DDR34 DDR34 Byte Lane #2 control registers 1
+ ***************************************************************************/
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P 0x003c6800 /* Write channel DQS-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N 0x003c6804 /* Write channel DQS-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0 0x003c6808 /* Write channel DQ0 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1 0x003c680c /* Write channel DQ1 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2 0x003c6810 /* Write channel DQ2 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3 0x003c6814 /* Write channel DQ3 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4 0x003c6818 /* Write channel DQ4 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5 0x003c681c /* Write channel DQ5 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6 0x003c6820 /* Write channel DQ6 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7 0x003c6824 /* Write channel DQ7 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM 0x003c6828 /* Write channel DM VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC 0x003c682c /* Write channel EDC VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP 0x003c6830 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN 0x003c6834 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P 0x003c6838 /* Read channel DQ0-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N 0x003c683c /* Read channel DQ0-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P 0x003c6840 /* Read channel DQ1-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N 0x003c6844 /* Read channel DQ1-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P 0x003c6848 /* Read channel DQ2-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N 0x003c684c /* Read channel DQ2-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P 0x003c6850 /* Read channel DQ3-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N 0x003c6854 /* Read channel DQ3-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P 0x003c6858 /* Read channel DQ4-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N 0x003c685c /* Read channel DQ4-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P 0x003c6860 /* Read channel DQ5-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N 0x003c6864 /* Read channel DQ5-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P 0x003c6868 /* Read channel DQ6-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N 0x003c686c /* Read channel DQ6-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P 0x003c6870 /* Read channel DQ7-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N 0x003c6874 /* Read channel DQ7-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP 0x003c6878 /* Read channel DM-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN 0x003c687c /* Read channel DM-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP 0x003c6880 /* Read channel EDC-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN 0x003c6884 /* Read channel EDC-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0 0x003c6888 /* Read channel CS_N[0] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1 0x003c688c /* Read channel CS_N[1] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL 0x003c6890 /* Write leveling VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC 0x003c68a0 /* Read enable bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC 0x003c68a4 /* Write leveling bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_CONTROL 0x003c68b0 /* Read channel datapath control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_ADDR 0x003c68b4 /* Read fifo addresss pointer register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_DATA 0x003c68b8 /* Read fifo data register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_DM_DBI 0x003c68bc /* Read fifo dm/dbi register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_STATUS 0x003c68c0 /* Read fifo status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_CLEAR 0x003c68c4 /* Read fifo status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL 0x003c68c8 /* Idle mode SSTL pad control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL 0x003c68cc /* SSTL pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL 0x003c68d0 /* SSTL read enable pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL 0x003c68d4 /* pad rx and tx characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE 0x003c68d8 /* Write cycle preamble control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL 0x003c68e0 /* Read channel ODT control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL 0x003c68f0 /* GDDR5M EDC digital phase detector control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS 0x003c68f4 /* GDDR5M EDC digital phase detector status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL 0x003c68f8 /* GDDR5M EDC digital phase detector output signal control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS 0x003c68fc /* GDDR5M EDC digital phase detector output signal status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_CLEAR 0x003c6900 /* GDDR5M EDC digital phase detector output signal status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL 0x003c6904 /* GDDR5M EDC signal path CRC control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS 0x003c6908 /* GDDR5M EDC signal path CRC status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_COUNT 0x003c690c /* GDDR5M EDC signal path CRC counter register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_CLEAR 0x003c6910 /* GDDR5M EDC signal path CRC counter register */
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DM - Write channel DM VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_BUSY_MASK   0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_BUSY_SHIFT  31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_FORCE_MASK  0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DM :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_DM :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_EDC :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_WR_EDC :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CLK_CONTROL - Write leveling VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CLK_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CLK_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_ADJ_EN_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_ADJ_EN_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_BUSY_MASK       0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_BUSY_SHIFT      31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_BUSY_DEFAULT    0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_reserved0_MASK  0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_FORCE_MASK      0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_FORCE_SHIFT     16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_FORCE_DEFAULT   0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_reserved1_MASK  0x0000ff00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_reserved1_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_CYCLES_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_CYCLES_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_CONTROL - Read channel datapath control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: READ_CONTROL :: reserved0 [31:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_CONTROL_reserved0_MASK   0xffffffe0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_CONTROL_reserved0_SHIFT  5
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: READ_CONTROL :: MODE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_CONTROL_MODE_MASK        0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_CONTROL_MODE_SHIFT       4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_CONTROL_MODE_DEFAULT     0x00000001
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: READ_CONTROL :: reserved1 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_CONTROL_reserved1_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_CONTROL_reserved1_SHIFT  3
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_CONTROL_RD_DATA_DLY_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
+
+/***************************************************************************
+ *READ_FIFO_ADDR - Read fifo addresss pointer register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: READ_FIFO_ADDR :: reserved0 [31:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_ADDR_reserved0_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: READ_FIFO_ADDR :: ADDR [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_ADDR_ADDR_MASK      0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_ADDR_ADDR_SHIFT     0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_ADDR_ADDR_DEFAULT   0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA - Read fifo data register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: READ_FIFO_DATA :: DATA [31:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_DATA_DATA_MASK      0xffffffff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_DATA_DATA_SHIFT     0
+
+/***************************************************************************
+ *READ_FIFO_DM_DBI - Read fifo dm/dbi register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_DM_DBI_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_DM_DBI_DM_DBI_MASK  0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: READ_FIFO_STATUS :: reserved0 [31:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_STATUS_reserved0_SHIFT 2
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_CLEAR_CLEAR_MASK    0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_CLEAR_CLEAR_SHIFT   0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_IDLE_MASK    0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_IDLE_SHIFT   31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: IDLE_PAD_CONTROL :: reserved1 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_reserved1_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_reserved1_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_RXENB_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_RXENB_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_IDDQ_MASK    0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_IDDQ_SHIFT   2
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_DOUT_N_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_DOUT_P_MASK  0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: DRIVE_PAD_CTL :: reserved0 [31:29] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_reserved0_MASK  0xe0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_reserved0_SHIFT 29
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [28:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x1e000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: DRIVE_PAD_CTL :: reserved1 [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_reserved1_MASK  0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_reserved1_SHIFT 24
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [23:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x00f00000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: DRIVE_PAD_CTL :: reserved2 [19:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_reserved2_MASK  0x00080000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_reserved2_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: DRIVE_PAD_CTL :: reserved3 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_reserved3_MASK  0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_reserved3_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: DRIVE_PAD_CTL :: reserved4 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_reserved4_MASK  0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_reserved4_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: DRIVE_PAD_CTL :: reserved5 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_reserved5_MASK  0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_reserved5_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff80000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DRIVE_PAD_CTL :: reserved1 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_reserved1_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_reserved1_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DRIVE_PAD_CTL :: reserved2 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_reserved2_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DRIVE_PAD_CTL :: reserved3 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_reserved3_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_reserved3_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *STATIC_PAD_CTL - pad rx and tx characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: reserved0 [31:21] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_reserved0_SHIFT 21
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_DQS_MODE_MASK  0x00100000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: reserved1 [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_reserved1_SHIFT 18
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_EDC_MODE_MASK  0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: reserved2 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_reserved2_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_reserved2_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_DM_MODE_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_DM_MODE_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: reserved3 [11:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_reserved3_MASK 0x00000c00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_reserved3_SHIFT 10
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: RX_LS [08:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_RX_LS_MASK     0x00000100
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_RX_LS_SHIFT    8
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_RX_LS_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_TX_MODE_MASK   0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_TX_MODE_SHIFT  4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: reserved4 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_reserved4_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_reserved4_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_RX_MODE_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_RX_MODE_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_reserved0_SHIFT 16
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: WR_PREAMBLE_MODE :: DQS [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQS_MASK     0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQS_SHIFT    8
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQS_DEFAULT  0x0000000e
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_reserved1_SHIFT 5
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
+
+/***************************************************************************
+ *ODT_CONTROL - Read channel ODT control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: ODT_CONTROL :: reserved0 [31:07] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_reserved0_MASK    0xffffff80
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_reserved0_SHIFT   7
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: ODT_CONTROL :: ODT_ENABLE [06:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_ODT_ENABLE_MASK   0x00000040
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_ODT_ENABLE_SHIFT  6
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
+
+/***************************************************************************
+ *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_reserved0_SHIFT 6
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_UPDATE_MASK   0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_UPDATE_SHIFT  2
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_MONITOR_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_MONITOR_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_CONTROL :: INIT [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_INIT_MASK     0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_INIT_SHIFT    0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_CONTROL_INIT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_STATUS :: reserved0 [31:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_reserved0_SHIFT 25
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_STATUS :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_reserved1_SHIFT 11
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_CRCWL_MASK    0x00000700
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_CRCWL_SHIFT   8
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_reserved2_SHIFT 6
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_CRCRL_MASK    0x00000030
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_CRCRL_SHIFT   4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_reserved3_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_WR_FAIL_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_WR_FAIL_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_WR_PASS_MASK   0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_WR_PASS_SHIFT  2
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_RD_FAIL_MASK   0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_RD_FAIL_SHIFT  1
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_RD_PASS_MASK   0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_RD_PASS_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_COUNT :: reserved0 [31:28] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_COUNT_reserved0_MASK  0xf0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_COUNT_reserved0_SHIFT 28
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_COUNT_WR_COUNT_MASK   0x0fff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_COUNT_WR_COUNT_SHIFT  16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_COUNT :: reserved1 [15:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_COUNT_reserved1_MASK  0x0000f000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_COUNT_reserved1_SHIFT 12
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_COUNT_RD_COUNT_MASK   0x00000fff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_COUNT_RD_COUNT_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_2_1 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_1_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_2_1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_2_2.h b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_2_2.h
new file mode 100644
index 0000000..4cadf0a
--- /dev/null
+++ b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_2_2.h
@@ -0,0 +1,2074 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Oct 17 03:11:31 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR34_PHY_BYTE_LANE_2_2_H__
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_H__
+
+/***************************************************************************
+ *DDR34_PHY_BYTE_LANE_2_2 - DDR34 DDR34 Byte Lane #2 control registers 2
+ ***************************************************************************/
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_P 0x003d6800 /* Write channel DQS-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_N 0x003d6804 /* Write channel DQS-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ0 0x003d6808 /* Write channel DQ0 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ1 0x003d680c /* Write channel DQ1 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ2 0x003d6810 /* Write channel DQ2 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ3 0x003d6814 /* Write channel DQ3 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ4 0x003d6818 /* Write channel DQ4 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ5 0x003d681c /* Write channel DQ5 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ6 0x003d6820 /* Write channel DQ6 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ7 0x003d6824 /* Write channel DQ7 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DM 0x003d6828 /* Write channel DM VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_EDC 0x003d682c /* Write channel EDC VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSP 0x003d6830 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSN 0x003d6834 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0P 0x003d6838 /* Read channel DQ0-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0N 0x003d683c /* Read channel DQ0-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1P 0x003d6840 /* Read channel DQ1-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1N 0x003d6844 /* Read channel DQ1-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2P 0x003d6848 /* Read channel DQ2-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2N 0x003d684c /* Read channel DQ2-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3P 0x003d6850 /* Read channel DQ3-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3N 0x003d6854 /* Read channel DQ3-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4P 0x003d6858 /* Read channel DQ4-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4N 0x003d685c /* Read channel DQ4-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5P 0x003d6860 /* Read channel DQ5-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5N 0x003d6864 /* Read channel DQ5-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6P 0x003d6868 /* Read channel DQ6-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6N 0x003d686c /* Read channel DQ6-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7P 0x003d6870 /* Read channel DQ7-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7N 0x003d6874 /* Read channel DQ7-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMP 0x003d6878 /* Read channel DM-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMN 0x003d687c /* Read channel DM-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCP 0x003d6880 /* Read channel EDC-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCN 0x003d6884 /* Read channel EDC-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS0 0x003d6888 /* Read channel CS_N[0] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS1 0x003d688c /* Read channel CS_N[1] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CLK_CONTROL 0x003d6890 /* Write leveling VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DLY_CYC 0x003d68a0 /* Read enable bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_CHAN_DLY_CYC 0x003d68a4 /* Write leveling bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_CONTROL 0x003d68b0 /* Read channel datapath control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_ADDR 0x003d68b4 /* Read fifo addresss pointer register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_DATA 0x003d68b8 /* Read fifo data register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_DM_DBI 0x003d68bc /* Read fifo dm/dbi register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_STATUS 0x003d68c0 /* Read fifo status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_CLEAR 0x003d68c4 /* Read fifo status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL 0x003d68c8 /* Idle mode SSTL pad control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL 0x003d68cc /* SSTL pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DRIVE_PAD_CTL 0x003d68d0 /* SSTL read enable pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL 0x003d68d4 /* pad rx and tx characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_PREAMBLE_MODE 0x003d68d8 /* Write cycle preamble control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_ODT_CONTROL 0x003d68e0 /* Read channel ODT control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_CONTROL 0x003d68f0 /* GDDR5M EDC digital phase detector control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS 0x003d68f4 /* GDDR5M EDC digital phase detector status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_CONTROL 0x003d68f8 /* GDDR5M EDC digital phase detector output signal control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_STATUS 0x003d68fc /* GDDR5M EDC digital phase detector output signal status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_STATUS_CLEAR 0x003d6900 /* GDDR5M EDC digital phase detector output signal status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL 0x003d6904 /* GDDR5M EDC signal path CRC control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_STATUS 0x003d6908 /* GDDR5M EDC signal path CRC status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_COUNT 0x003d690c /* GDDR5M EDC signal path CRC counter register */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_STATUS_CLEAR 0x003d6910 /* GDDR5M EDC signal path CRC counter register */
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ0_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ1_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ2_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ3_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ4_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ5_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ6_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ7_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DM - Write channel DM VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DM_BUSY_MASK   0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DM_BUSY_SHIFT  31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DM_FORCE_MASK  0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DM :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DM_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_DM :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_EDC_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_EDC :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_EDC_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_WR_EDC :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMP_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMN_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CLK_CONTROL - Write leveling VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CLK_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CLK_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CLK_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CLK_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CLK_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CLK_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CLK_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CLK_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CLK_CONTROL_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CLK_CONTROL_ADJ_EN_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CLK_CONTROL_ADJ_EN_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CLK_CONTROL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: RD_EN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DLY_CYC_BUSY_MASK       0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DLY_CYC_BUSY_SHIFT      31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DLY_CYC_BUSY_DEFAULT    0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DLY_CYC_reserved0_MASK  0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: RD_EN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DLY_CYC_FORCE_MASK      0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DLY_CYC_FORCE_SHIFT     16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DLY_CYC_FORCE_DEFAULT   0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DLY_CYC_reserved1_MASK  0x0000ff00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DLY_CYC_reserved1_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_CHAN_DLY_CYC_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_CHAN_DLY_CYC_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_CHAN_DLY_CYC_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_CHAN_DLY_CYC_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_CHAN_DLY_CYC_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_CHAN_DLY_CYC_CYCLES_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_CHAN_DLY_CYC_CYCLES_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_CONTROL - Read channel datapath control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: READ_CONTROL :: reserved0 [31:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_CONTROL_reserved0_MASK   0xffffffe0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_CONTROL_reserved0_SHIFT  5
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: READ_CONTROL :: MODE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_CONTROL_MODE_MASK        0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_CONTROL_MODE_SHIFT       4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_CONTROL_MODE_DEFAULT     0x00000001
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: READ_CONTROL :: reserved1 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_CONTROL_reserved1_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_CONTROL_reserved1_SHIFT  3
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_CONTROL_RD_DATA_DLY_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
+
+/***************************************************************************
+ *READ_FIFO_ADDR - Read fifo addresss pointer register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: READ_FIFO_ADDR :: reserved0 [31:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_ADDR_reserved0_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: READ_FIFO_ADDR :: ADDR [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_ADDR_ADDR_MASK      0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_ADDR_ADDR_SHIFT     0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_ADDR_ADDR_DEFAULT   0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA - Read fifo data register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: READ_FIFO_DATA :: DATA [31:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_DATA_DATA_MASK      0xffffffff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_DATA_DATA_SHIFT     0
+
+/***************************************************************************
+ *READ_FIFO_DM_DBI - Read fifo dm/dbi register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_DM_DBI_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_DM_DBI_DM_DBI_MASK  0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: READ_FIFO_STATUS :: reserved0 [31:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_STATUS_reserved0_SHIFT 2
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_CLEAR_CLEAR_MASK    0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_CLEAR_CLEAR_SHIFT   0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_IDLE_MASK    0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_IDLE_SHIFT   31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: IDLE_PAD_CONTROL :: reserved1 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_reserved1_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_reserved1_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_RXENB_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_RXENB_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_IDDQ_MASK    0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_IDDQ_SHIFT   2
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_DOUT_N_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_DOUT_P_MASK  0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: DRIVE_PAD_CTL :: reserved0 [31:29] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_reserved0_MASK  0xe0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_reserved0_SHIFT 29
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [28:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x1e000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: DRIVE_PAD_CTL :: reserved1 [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_reserved1_MASK  0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_reserved1_SHIFT 24
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [23:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x00f00000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: DRIVE_PAD_CTL :: reserved2 [19:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_reserved2_MASK  0x00080000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_reserved2_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: DRIVE_PAD_CTL :: reserved3 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_reserved3_MASK  0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_reserved3_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: DRIVE_PAD_CTL :: reserved4 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_reserved4_MASK  0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_reserved4_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: DRIVE_PAD_CTL :: reserved5 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_reserved5_MASK  0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_reserved5_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff80000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: RD_EN_DRIVE_PAD_CTL :: reserved1 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DRIVE_PAD_CTL_reserved1_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DRIVE_PAD_CTL_reserved1_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: RD_EN_DRIVE_PAD_CTL :: reserved2 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DRIVE_PAD_CTL_reserved2_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DRIVE_PAD_CTL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: RD_EN_DRIVE_PAD_CTL :: reserved3 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DRIVE_PAD_CTL_reserved3_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DRIVE_PAD_CTL_reserved3_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *STATIC_PAD_CTL - pad rx and tx characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: STATIC_PAD_CTL :: reserved0 [31:21] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_reserved0_SHIFT 21
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_DQS_MODE_MASK  0x00100000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: STATIC_PAD_CTL :: reserved1 [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_reserved1_SHIFT 18
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_EDC_MODE_MASK  0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: STATIC_PAD_CTL :: reserved2 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_reserved2_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_reserved2_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_DM_MODE_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_DM_MODE_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: STATIC_PAD_CTL :: reserved3 [11:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_reserved3_MASK 0x00000c00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_reserved3_SHIFT 10
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: STATIC_PAD_CTL :: RX_LS [08:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_RX_LS_MASK     0x00000100
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_RX_LS_SHIFT    8
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_RX_LS_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_TX_MODE_MASK   0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_TX_MODE_SHIFT  4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: STATIC_PAD_CTL :: reserved4 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_reserved4_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_reserved4_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_RX_MODE_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_RX_MODE_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_PREAMBLE_MODE_reserved0_SHIFT 16
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: WR_PREAMBLE_MODE :: DQS [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_PREAMBLE_MODE_DQS_MASK     0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_PREAMBLE_MODE_DQS_SHIFT    8
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_PREAMBLE_MODE_DQS_DEFAULT  0x0000000e
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_PREAMBLE_MODE_reserved1_SHIFT 5
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
+
+/***************************************************************************
+ *ODT_CONTROL - Read channel ODT control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: ODT_CONTROL :: reserved0 [31:07] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_ODT_CONTROL_reserved0_MASK    0xffffff80
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_ODT_CONTROL_reserved0_SHIFT   7
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: ODT_CONTROL :: ODT_ENABLE [06:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_ODT_CONTROL_ODT_ENABLE_MASK   0x00000040
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_ODT_CONTROL_ODT_ENABLE_SHIFT  6
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
+
+/***************************************************************************
+ *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_CONTROL_reserved0_SHIFT 6
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_CONTROL_UPDATE_MASK   0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_CONTROL_UPDATE_SHIFT  2
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_CONTROL_MONITOR_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_CONTROL_MONITOR_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_CONTROL :: INIT [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_CONTROL_INIT_MASK     0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_CONTROL_INIT_SHIFT    0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_CONTROL_INIT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_STATUS :: reserved0 [31:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_reserved0_SHIFT 25
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_STATUS :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_CRC_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_CRC_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_reserved1_SHIFT 11
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_CRCWL_MASK    0x00000700
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_CRCWL_SHIFT   8
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_reserved2_SHIFT 6
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_CRCRL_MASK    0x00000030
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_CRCRL_SHIFT   4
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_reserved3_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_CRC_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_STATUS_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_STATUS_WR_FAIL_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_STATUS_WR_FAIL_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_STATUS_WR_PASS_MASK   0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_STATUS_WR_PASS_SHIFT  2
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_STATUS_RD_FAIL_MASK   0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_STATUS_RD_FAIL_SHIFT  1
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_STATUS_RD_PASS_MASK   0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_STATUS_RD_PASS_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_CRC_COUNT :: reserved0 [31:28] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_COUNT_reserved0_MASK  0xf0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_COUNT_reserved0_SHIFT 28
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_COUNT_WR_COUNT_MASK   0x0fff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_COUNT_WR_COUNT_SHIFT  16
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_CRC_COUNT :: reserved1 [15:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_COUNT_reserved1_MASK  0x0000f000
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_COUNT_reserved1_SHIFT 12
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_COUNT_RD_COUNT_MASK   0x00000fff
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_COUNT_RD_COUNT_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_2_2 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_2_2_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_2_2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_3_0.h b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_3_0.h
new file mode 100644
index 0000000..7e71999
--- /dev/null
+++ b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_3_0.h
@@ -0,0 +1,2074 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Oct 17 03:11:31 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR34_PHY_BYTE_LANE_3_0_H__
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_H__
+
+/***************************************************************************
+ *DDR34_PHY_BYTE_LANE_3_0 - DDR34 DDR34 Byte Lane #3 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P 0x003b6a00 /* Write channel DQS-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N 0x003b6a04 /* Write channel DQS-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0 0x003b6a08 /* Write channel DQ0 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1 0x003b6a0c /* Write channel DQ1 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2 0x003b6a10 /* Write channel DQ2 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3 0x003b6a14 /* Write channel DQ3 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4 0x003b6a18 /* Write channel DQ4 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5 0x003b6a1c /* Write channel DQ5 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6 0x003b6a20 /* Write channel DQ6 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7 0x003b6a24 /* Write channel DQ7 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM 0x003b6a28 /* Write channel DM VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC 0x003b6a2c /* Write channel EDC VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP 0x003b6a30 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN 0x003b6a34 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P 0x003b6a38 /* Read channel DQ0-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N 0x003b6a3c /* Read channel DQ0-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P 0x003b6a40 /* Read channel DQ1-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N 0x003b6a44 /* Read channel DQ1-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P 0x003b6a48 /* Read channel DQ2-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N 0x003b6a4c /* Read channel DQ2-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P 0x003b6a50 /* Read channel DQ3-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N 0x003b6a54 /* Read channel DQ3-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P 0x003b6a58 /* Read channel DQ4-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N 0x003b6a5c /* Read channel DQ4-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P 0x003b6a60 /* Read channel DQ5-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N 0x003b6a64 /* Read channel DQ5-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P 0x003b6a68 /* Read channel DQ6-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N 0x003b6a6c /* Read channel DQ6-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P 0x003b6a70 /* Read channel DQ7-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N 0x003b6a74 /* Read channel DQ7-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP 0x003b6a78 /* Read channel DM-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN 0x003b6a7c /* Read channel DM-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP 0x003b6a80 /* Read channel EDC-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN 0x003b6a84 /* Read channel EDC-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0 0x003b6a88 /* Read channel CS_N[0] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1 0x003b6a8c /* Read channel CS_N[1] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL 0x003b6a90 /* Write leveling VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC 0x003b6aa0 /* Read enable bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC 0x003b6aa4 /* Write leveling bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL 0x003b6ab0 /* Read channel datapath control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR 0x003b6ab4 /* Read fifo addresss pointer register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DATA 0x003b6ab8 /* Read fifo data register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DM_DBI 0x003b6abc /* Read fifo dm/dbi register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS 0x003b6ac0 /* Read fifo status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR 0x003b6ac4 /* Read fifo status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL 0x003b6ac8 /* Idle mode SSTL pad control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL 0x003b6acc /* SSTL pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL 0x003b6ad0 /* SSTL read enable pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL 0x003b6ad4 /* pad rx and tx characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE 0x003b6ad8 /* Write cycle preamble control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL 0x003b6ae0 /* Read channel ODT control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL 0x003b6af0 /* GDDR5M EDC digital phase detector control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS 0x003b6af4 /* GDDR5M EDC digital phase detector status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL 0x003b6af8 /* GDDR5M EDC digital phase detector output signal control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS 0x003b6afc /* GDDR5M EDC digital phase detector output signal status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR 0x003b6b00 /* GDDR5M EDC digital phase detector output signal status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL 0x003b6b04 /* GDDR5M EDC signal path CRC control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS 0x003b6b08 /* GDDR5M EDC signal path CRC status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT 0x003b6b0c /* GDDR5M EDC signal path CRC counter register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR 0x003b6b10 /* GDDR5M EDC signal path CRC counter register */
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DM - Write channel DM VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_BUSY_MASK   0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_BUSY_SHIFT  31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_FORCE_MASK  0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_DM :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_WR_EDC :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CLK_CONTROL - Write leveling VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_ADJ_EN_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_BUSY_MASK       0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_BUSY_SHIFT      31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_BUSY_DEFAULT    0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_reserved0_MASK  0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_FORCE_MASK      0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_FORCE_SHIFT     16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_FORCE_DEFAULT   0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_reserved1_MASK  0x0000ff00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_reserved1_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_CYCLES_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_CYCLES_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_CONTROL - Read channel datapath control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: READ_CONTROL :: reserved0 [31:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_reserved0_MASK   0xffffffe0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_reserved0_SHIFT  5
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: READ_CONTROL :: MODE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_MODE_MASK        0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_MODE_SHIFT       4
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_MODE_DEFAULT     0x00000001
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: READ_CONTROL :: reserved1 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_reserved1_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_reserved1_SHIFT  3
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_RD_DATA_DLY_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
+
+/***************************************************************************
+ *READ_FIFO_ADDR - Read fifo addresss pointer register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR_reserved0_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_ADDR :: ADDR [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR_ADDR_MASK      0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR_ADDR_SHIFT     0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_ADDR_ADDR_DEFAULT   0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA - Read fifo data register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_DATA :: DATA [31:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DATA_DATA_MASK      0xffffffff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DATA_DATA_SHIFT     0
+
+/***************************************************************************
+ *READ_FIFO_DM_DBI - Read fifo dm/dbi register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DM_DBI_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DM_DBI_DM_DBI_MASK  0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_STATUS :: reserved0 [31:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_reserved0_SHIFT 2
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR_CLEAR_MASK    0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR_CLEAR_SHIFT   0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDLE_MASK    0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDLE_SHIFT   31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: reserved1 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_reserved1_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_reserved1_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_RXENB_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_RXENB_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDDQ_MASK    0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDDQ_SHIFT   2
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_DOUT_N_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_DOUT_P_MASK  0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: reserved0 [31:29] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_reserved0_MASK  0xe0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_reserved0_SHIFT 29
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [28:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x1e000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: reserved1 [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_reserved1_MASK  0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_reserved1_SHIFT 24
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [23:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x00f00000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: reserved2 [19:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_reserved2_MASK  0x00080000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_reserved2_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: reserved3 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_reserved3_MASK  0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_reserved3_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: reserved4 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_reserved4_MASK  0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_reserved4_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: reserved5 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_reserved5_MASK  0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_reserved5_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff80000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: reserved1 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_reserved1_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_reserved1_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: reserved2 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_reserved2_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: reserved3 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_reserved3_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_reserved3_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *STATIC_PAD_CTL - pad rx and tx characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved0 [31:21] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved0_SHIFT 21
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_MODE_MASK  0x00100000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved1 [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved1_SHIFT 18
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_EDC_MODE_MASK  0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved2 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved2_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved2_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DM_MODE_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DM_MODE_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved3 [11:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved3_MASK 0x00000c00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved3_SHIFT 10
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: RX_LS [08:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RX_LS_MASK     0x00000100
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RX_LS_SHIFT    8
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RX_LS_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_TX_MODE_MASK   0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_TX_MODE_SHIFT  4
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: reserved4 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved4_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_reserved4_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RX_MODE_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RX_MODE_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_reserved0_SHIFT 16
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: DQS [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_MASK     0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_SHIFT    8
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_DEFAULT  0x0000000e
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_reserved1_SHIFT 5
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
+
+/***************************************************************************
+ *ODT_CONTROL - Read channel ODT control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: ODT_CONTROL :: reserved0 [31:07] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_reserved0_MASK    0xffffff80
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_reserved0_SHIFT   7
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: ODT_CONTROL :: ODT_ENABLE [06:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_ENABLE_MASK   0x00000040
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_ENABLE_SHIFT  6
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
+
+/***************************************************************************
+ *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_reserved0_SHIFT 6
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_UPDATE_MASK   0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_UPDATE_SHIFT  2
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_MONITOR_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_MONITOR_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_CONTROL :: INIT [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_INIT_MASK     0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_INIT_SHIFT    0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_CONTROL_INIT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: reserved0 [31:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_reserved0_SHIFT 25
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved1_SHIFT 11
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCWL_MASK    0x00000700
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCWL_SHIFT   8
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved2_SHIFT 6
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCRL_MASK    0x00000030
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCRL_SHIFT   4
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_reserved3_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_WR_FAIL_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_WR_FAIL_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_WR_PASS_MASK   0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_WR_PASS_SHIFT  2
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_RD_FAIL_MASK   0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_RD_FAIL_SHIFT  1
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_RD_PASS_MASK   0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_RD_PASS_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_COUNT :: reserved0 [31:28] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_reserved0_MASK  0xf0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_reserved0_SHIFT 28
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_WR_COUNT_MASK   0x0fff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_WR_COUNT_SHIFT  16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_COUNT :: reserved1 [15:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_reserved1_MASK  0x0000f000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_reserved1_SHIFT 12
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_RD_COUNT_MASK   0x00000fff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_RD_COUNT_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_3_0 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_3_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_3_1.h b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_3_1.h
new file mode 100644
index 0000000..41e7444
--- /dev/null
+++ b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_3_1.h
@@ -0,0 +1,2074 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Oct 17 03:11:30 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR34_PHY_BYTE_LANE_3_1_H__
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_H__
+
+/***************************************************************************
+ *DDR34_PHY_BYTE_LANE_3_1 - DDR34 DDR34 Byte Lane #3 control registers 1
+ ***************************************************************************/
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P 0x003c6a00 /* Write channel DQS-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N 0x003c6a04 /* Write channel DQS-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0 0x003c6a08 /* Write channel DQ0 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1 0x003c6a0c /* Write channel DQ1 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2 0x003c6a10 /* Write channel DQ2 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3 0x003c6a14 /* Write channel DQ3 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4 0x003c6a18 /* Write channel DQ4 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5 0x003c6a1c /* Write channel DQ5 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6 0x003c6a20 /* Write channel DQ6 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7 0x003c6a24 /* Write channel DQ7 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM 0x003c6a28 /* Write channel DM VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC 0x003c6a2c /* Write channel EDC VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP 0x003c6a30 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN 0x003c6a34 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P 0x003c6a38 /* Read channel DQ0-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N 0x003c6a3c /* Read channel DQ0-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P 0x003c6a40 /* Read channel DQ1-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N 0x003c6a44 /* Read channel DQ1-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P 0x003c6a48 /* Read channel DQ2-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N 0x003c6a4c /* Read channel DQ2-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P 0x003c6a50 /* Read channel DQ3-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N 0x003c6a54 /* Read channel DQ3-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P 0x003c6a58 /* Read channel DQ4-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N 0x003c6a5c /* Read channel DQ4-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P 0x003c6a60 /* Read channel DQ5-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N 0x003c6a64 /* Read channel DQ5-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P 0x003c6a68 /* Read channel DQ6-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N 0x003c6a6c /* Read channel DQ6-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P 0x003c6a70 /* Read channel DQ7-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N 0x003c6a74 /* Read channel DQ7-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP 0x003c6a78 /* Read channel DM-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN 0x003c6a7c /* Read channel DM-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP 0x003c6a80 /* Read channel EDC-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN 0x003c6a84 /* Read channel EDC-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0 0x003c6a88 /* Read channel CS_N[0] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1 0x003c6a8c /* Read channel CS_N[1] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL 0x003c6a90 /* Write leveling VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC 0x003c6aa0 /* Read enable bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC 0x003c6aa4 /* Write leveling bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_CONTROL 0x003c6ab0 /* Read channel datapath control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_ADDR 0x003c6ab4 /* Read fifo addresss pointer register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_DATA 0x003c6ab8 /* Read fifo data register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_DM_DBI 0x003c6abc /* Read fifo dm/dbi register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_STATUS 0x003c6ac0 /* Read fifo status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_CLEAR 0x003c6ac4 /* Read fifo status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL 0x003c6ac8 /* Idle mode SSTL pad control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL 0x003c6acc /* SSTL pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL 0x003c6ad0 /* SSTL read enable pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL 0x003c6ad4 /* pad rx and tx characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE 0x003c6ad8 /* Write cycle preamble control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL 0x003c6ae0 /* Read channel ODT control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL 0x003c6af0 /* GDDR5M EDC digital phase detector control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS 0x003c6af4 /* GDDR5M EDC digital phase detector status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL 0x003c6af8 /* GDDR5M EDC digital phase detector output signal control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS 0x003c6afc /* GDDR5M EDC digital phase detector output signal status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_CLEAR 0x003c6b00 /* GDDR5M EDC digital phase detector output signal status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL 0x003c6b04 /* GDDR5M EDC signal path CRC control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS 0x003c6b08 /* GDDR5M EDC signal path CRC status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_COUNT 0x003c6b0c /* GDDR5M EDC signal path CRC counter register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_CLEAR 0x003c6b10 /* GDDR5M EDC signal path CRC counter register */
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DM - Write channel DM VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_BUSY_MASK   0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_BUSY_SHIFT  31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_FORCE_MASK  0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DM :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_DM :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_EDC :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_WR_EDC :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CLK_CONTROL - Write leveling VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CLK_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CLK_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_ADJ_EN_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_ADJ_EN_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_BUSY_MASK       0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_BUSY_SHIFT      31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_BUSY_DEFAULT    0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_reserved0_MASK  0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_FORCE_MASK      0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_FORCE_SHIFT     16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_FORCE_DEFAULT   0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_reserved1_MASK  0x0000ff00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_reserved1_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_CYCLES_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_CYCLES_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_CONTROL - Read channel datapath control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: READ_CONTROL :: reserved0 [31:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_CONTROL_reserved0_MASK   0xffffffe0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_CONTROL_reserved0_SHIFT  5
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: READ_CONTROL :: MODE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_CONTROL_MODE_MASK        0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_CONTROL_MODE_SHIFT       4
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_CONTROL_MODE_DEFAULT     0x00000001
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: READ_CONTROL :: reserved1 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_CONTROL_reserved1_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_CONTROL_reserved1_SHIFT  3
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_CONTROL_RD_DATA_DLY_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
+
+/***************************************************************************
+ *READ_FIFO_ADDR - Read fifo addresss pointer register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: READ_FIFO_ADDR :: reserved0 [31:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_ADDR_reserved0_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: READ_FIFO_ADDR :: ADDR [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_ADDR_ADDR_MASK      0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_ADDR_ADDR_SHIFT     0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_ADDR_ADDR_DEFAULT   0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA - Read fifo data register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: READ_FIFO_DATA :: DATA [31:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_DATA_DATA_MASK      0xffffffff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_DATA_DATA_SHIFT     0
+
+/***************************************************************************
+ *READ_FIFO_DM_DBI - Read fifo dm/dbi register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_DM_DBI_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_DM_DBI_DM_DBI_MASK  0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: READ_FIFO_STATUS :: reserved0 [31:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_STATUS_reserved0_SHIFT 2
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_CLEAR_CLEAR_MASK    0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_CLEAR_CLEAR_SHIFT   0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_IDLE_MASK    0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_IDLE_SHIFT   31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: IDLE_PAD_CONTROL :: reserved1 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_reserved1_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_reserved1_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_RXENB_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_RXENB_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_IDDQ_MASK    0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_IDDQ_SHIFT   2
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_DOUT_N_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_DOUT_P_MASK  0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: DRIVE_PAD_CTL :: reserved0 [31:29] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_reserved0_MASK  0xe0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_reserved0_SHIFT 29
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [28:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x1e000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: DRIVE_PAD_CTL :: reserved1 [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_reserved1_MASK  0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_reserved1_SHIFT 24
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [23:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x00f00000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: DRIVE_PAD_CTL :: reserved2 [19:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_reserved2_MASK  0x00080000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_reserved2_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: DRIVE_PAD_CTL :: reserved3 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_reserved3_MASK  0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_reserved3_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: DRIVE_PAD_CTL :: reserved4 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_reserved4_MASK  0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_reserved4_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: DRIVE_PAD_CTL :: reserved5 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_reserved5_MASK  0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_reserved5_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff80000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DRIVE_PAD_CTL :: reserved1 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_reserved1_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_reserved1_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DRIVE_PAD_CTL :: reserved2 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_reserved2_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DRIVE_PAD_CTL :: reserved3 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_reserved3_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_reserved3_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *STATIC_PAD_CTL - pad rx and tx characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: reserved0 [31:21] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_reserved0_SHIFT 21
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_DQS_MODE_MASK  0x00100000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: reserved1 [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_reserved1_SHIFT 18
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_EDC_MODE_MASK  0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: reserved2 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_reserved2_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_reserved2_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_DM_MODE_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_DM_MODE_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: reserved3 [11:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_reserved3_MASK 0x00000c00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_reserved3_SHIFT 10
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: RX_LS [08:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_RX_LS_MASK     0x00000100
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_RX_LS_SHIFT    8
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_RX_LS_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: TX_MODE [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_TX_MODE_MASK   0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_TX_MODE_SHIFT  4
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: reserved4 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_reserved4_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_reserved4_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: STATIC_PAD_CTL :: RX_MODE [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_RX_MODE_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_RX_MODE_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_reserved0_SHIFT 16
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: WR_PREAMBLE_MODE :: DQS [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQS_MASK     0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQS_SHIFT    8
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQS_DEFAULT  0x0000000e
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_reserved1_SHIFT 5
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
+
+/***************************************************************************
+ *ODT_CONTROL - Read channel ODT control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: ODT_CONTROL :: reserved0 [31:07] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_reserved0_MASK    0xffffff80
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_reserved0_SHIFT   7
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: ODT_CONTROL :: ODT_ENABLE [06:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_ODT_ENABLE_MASK   0x00000040
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_ODT_ENABLE_SHIFT  6
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
+
+/***************************************************************************
+ *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_reserved0_SHIFT 6
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_UPDATE_MASK   0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_UPDATE_SHIFT  2
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_MONITOR_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_MONITOR_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_CONTROL :: INIT [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_INIT_MASK     0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_INIT_SHIFT    0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_CONTROL_INIT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_STATUS :: reserved0 [31:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_reserved0_SHIFT 25
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_STATUS :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_reserved1_SHIFT 11
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_CRCWL_MASK    0x00000700
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_CRCWL_SHIFT   8
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_reserved2_SHIFT 6
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_CRCRL_MASK    0x00000030
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_CRCRL_SHIFT   4
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_reserved3_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_WR_FAIL_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_WR_FAIL_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_WR_PASS_MASK   0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_WR_PASS_SHIFT  2
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_RD_FAIL_MASK   0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_RD_FAIL_SHIFT  1
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_RD_PASS_MASK   0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_RD_PASS_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_COUNT :: reserved0 [31:28] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_COUNT_reserved0_MASK  0xf0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_COUNT_reserved0_SHIFT 28
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_COUNT_WR_COUNT_MASK   0x0fff0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_COUNT_WR_COUNT_SHIFT  16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_COUNT :: reserved1 [15:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_COUNT_reserved1_MASK  0x0000f000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_COUNT_reserved1_SHIFT 12
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_COUNT_RD_COUNT_MASK   0x00000fff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_COUNT_RD_COUNT_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_3_1 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_1_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_3_1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_3_2.h b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_3_2.h
new file mode 100644
index 0000000..767061e
--- /dev/null
+++ b/include/linux/brcmstb/7445a0/bchp_ddr34_phy_byte_lane_3_2.h
@@ -0,0 +1,2074 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Oct 17 03:11:30 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR34_PHY_BYTE_LANE_3_2_H__
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_H__
+
+/***************************************************************************
+ *DDR34_PHY_BYTE_LANE_3_2 - DDR34 DDR34 Byte Lane #3 control registers 2
+ ***************************************************************************/
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_P 0x003d6a00 /* Write channel DQS-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_N 0x003d6a04 /* Write channel DQS-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ0 0x003d6a08 /* Write channel DQ0 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ1 0x003d6a0c /* Write channel DQ1 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ2 0x003d6a10 /* Write channel DQ2 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ3 0x003d6a14 /* Write channel DQ3 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ4 0x003d6a18 /* Write channel DQ4 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ5 0x003d6a1c /* Write channel DQ5 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ6 0x003d6a20 /* Write channel DQ6 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ7 0x003d6a24 /* Write channel DQ7 VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DM 0x003d6a28 /* Write channel DM VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_EDC 0x003d6a2c /* Write channel EDC VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSP 0x003d6a30 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSN 0x003d6a34 /* Read channel DQSP VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0P 0x003d6a38 /* Read channel DQ0-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0N 0x003d6a3c /* Read channel DQ0-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1P 0x003d6a40 /* Read channel DQ1-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1N 0x003d6a44 /* Read channel DQ1-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2P 0x003d6a48 /* Read channel DQ2-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2N 0x003d6a4c /* Read channel DQ2-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3P 0x003d6a50 /* Read channel DQ3-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3N 0x003d6a54 /* Read channel DQ3-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4P 0x003d6a58 /* Read channel DQ4-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4N 0x003d6a5c /* Read channel DQ4-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5P 0x003d6a60 /* Read channel DQ5-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5N 0x003d6a64 /* Read channel DQ5-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6P 0x003d6a68 /* Read channel DQ6-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6N 0x003d6a6c /* Read channel DQ6-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7P 0x003d6a70 /* Read channel DQ7-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7N 0x003d6a74 /* Read channel DQ7-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMP 0x003d6a78 /* Read channel DM-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMN 0x003d6a7c /* Read channel DM-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCP 0x003d6a80 /* Read channel EDC-P VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCN 0x003d6a84 /* Read channel EDC-N VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS0 0x003d6a88 /* Read channel CS_N[0] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS1 0x003d6a8c /* Read channel CS_N[1] read enable VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CLK_CONTROL 0x003d6a90 /* Write leveling VDL control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DLY_CYC 0x003d6aa0 /* Read enable bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_WR_CHAN_DLY_CYC 0x003d6aa4 /* Write leveling bit-clock cycle delay control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_CONTROL 0x003d6ab0 /* Read channel datapath control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_ADDR 0x003d6ab4 /* Read fifo addresss pointer register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_DATA 0x003d6ab8 /* Read fifo data register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_DM_DBI 0x003d6abc /* Read fifo dm/dbi register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_STATUS 0x003d6ac0 /* Read fifo status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_CLEAR 0x003d6ac4 /* Read fifo status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL 0x003d6ac8 /* Idle mode SSTL pad control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL 0x003d6acc /* SSTL pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DRIVE_PAD_CTL 0x003d6ad0 /* SSTL read enable pad drive characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_STATIC_PAD_CTL 0x003d6ad4 /* pad rx and tx characteristics control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_WR_PREAMBLE_MODE 0x003d6ad8 /* Write cycle preamble control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_ODT_CONTROL 0x003d6ae0 /* Read channel ODT control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_EDC_DPD_CONTROL 0x003d6af0 /* GDDR5M EDC digital phase detector control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_EDC_DPD_STATUS 0x003d6af4 /* GDDR5M EDC digital phase detector status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_EDC_DPD_OUT_CONTROL 0x003d6af8 /* GDDR5M EDC digital phase detector output signal control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_EDC_DPD_OUT_STATUS 0x003d6afc /* GDDR5M EDC digital phase detector output signal status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_EDC_DPD_OUT_STATUS_CLEAR 0x003d6b00 /* GDDR5M EDC digital phase detector output signal status clear register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_EDC_CRC_CONTROL 0x003d6b04 /* GDDR5M EDC signal path CRC control register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_EDC_CRC_STATUS 0x003d6b08 /* GDDR5M EDC signal path CRC status register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_EDC_CRC_COUNT 0x003d6b0c /* GDDR5M EDC signal path CRC counter register */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_EDC_CRC_STATUS_CLEAR 0x003d6b10 /* GDDR5M EDC signal path CRC counter register */
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ0_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ1_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ2_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ3_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ4_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ5_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ6_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ7_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_DM - Write channel DM VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DM_BUSY_MASK   0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DM_BUSY_SHIFT  31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DM_FORCE_MASK  0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DM :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DM_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_DM :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_EDC_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_EDC :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_EDC_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_WR_EDC :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMP_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMN_BUSY_MASK  0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CLK_CONTROL - Write leveling VDL control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CLK_CONTROL :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CLK_CONTROL_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CLK_CONTROL_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CLK_CONTROL_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CLK_CONTROL_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CLK_CONTROL :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CLK_CONTROL_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CLK_CONTROL_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CLK_CONTROL_reserved1_SHIFT 13
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CLK_CONTROL_ADJ_EN_MASK   0x00001000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CLK_CONTROL_ADJ_EN_SHIFT  12
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CLK_CONTROL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: RD_EN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DLY_CYC_BUSY_MASK       0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DLY_CYC_BUSY_SHIFT      31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DLY_CYC_BUSY_DEFAULT    0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DLY_CYC_reserved0_MASK  0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: RD_EN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DLY_CYC_FORCE_MASK      0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DLY_CYC_FORCE_SHIFT     16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DLY_CYC_FORCE_DEFAULT   0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DLY_CYC_reserved1_MASK  0x0000ff00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DLY_CYC_reserved1_SHIFT 8
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_WR_CHAN_DLY_CYC_BUSY_MASK     0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_WR_CHAN_DLY_CYC_BUSY_SHIFT    31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_WR_CHAN_DLY_CYC_BUSY_DEFAULT  0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_WR_CHAN_DLY_CYC_FORCE_MASK    0x00010000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_WR_CHAN_DLY_CYC_FORCE_SHIFT   16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_WR_CHAN_DLY_CYC_CYCLES_MASK   0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_WR_CHAN_DLY_CYC_CYCLES_SHIFT  0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_CONTROL - Read channel datapath control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: READ_CONTROL :: reserved0 [31:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_CONTROL_reserved0_MASK   0xffffffe0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_CONTROL_reserved0_SHIFT  5
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: READ_CONTROL :: MODE [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_CONTROL_MODE_MASK        0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_CONTROL_MODE_SHIFT       4
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_CONTROL_MODE_DEFAULT     0x00000001
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: READ_CONTROL :: reserved1 [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_CONTROL_reserved1_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_CONTROL_reserved1_SHIFT  3
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_CONTROL_RD_DATA_DLY_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
+
+/***************************************************************************
+ *READ_FIFO_ADDR - Read fifo addresss pointer register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: READ_FIFO_ADDR :: reserved0 [31:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_ADDR_reserved0_SHIFT 3
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: READ_FIFO_ADDR :: ADDR [02:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_ADDR_ADDR_MASK      0x00000007
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_ADDR_ADDR_SHIFT     0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_ADDR_ADDR_DEFAULT   0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA - Read fifo data register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: READ_FIFO_DATA :: DATA [31:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_DATA_DATA_MASK      0xffffffff
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_DATA_DATA_SHIFT     0
+
+/***************************************************************************
+ *READ_FIFO_DM_DBI - Read fifo dm/dbi register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_DM_DBI_reserved0_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_DM_DBI_DM_DBI_MASK  0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: READ_FIFO_STATUS :: reserved0 [31:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_STATUS_reserved0_SHIFT 2
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_CLEAR_CLEAR_MASK    0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_CLEAR_CLEAR_SHIFT   0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_IDLE_MASK    0x80000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_IDLE_SHIFT   31
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_reserved0_SHIFT 20
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: IDLE_PAD_CONTROL :: reserved1 [15:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_reserved1_MASK 0x00008000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_reserved1_SHIFT 15
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_RXENB_MASK   0x00000008
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_RXENB_SHIFT  3
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_IDDQ_MASK    0x00000004
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_IDDQ_SHIFT   2
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_DOUT_N_MASK  0x00000002
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_DOUT_P_MASK  0x00000001
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: DRIVE_PAD_CTL :: reserved0 [31:29] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_reserved0_MASK  0xe0000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_reserved0_SHIFT 29
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [28:25] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x1e000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: DRIVE_PAD_CTL :: reserved1 [24:24] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_reserved1_MASK  0x01000000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_reserved1_SHIFT 24
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [23:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x00f00000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: DRIVE_PAD_CTL :: reserved2 [19:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_reserved2_MASK  0x00080000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_reserved2_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: DRIVE_PAD_CTL :: reserved3 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_reserved3_MASK  0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_reserved3_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000004
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: DRIVE_PAD_CTL :: reserved4 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_reserved4_MASK  0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_reserved4_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: DRIVE_PAD_CTL :: reserved5 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_reserved5_MASK  0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_reserved5_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:19] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff80000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 19
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [18:15] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x00078000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: RD_EN_DRIVE_PAD_CTL :: reserved1 [14:14] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DRIVE_PAD_CTL_reserved1_MASK 0x00004000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DRIVE_PAD_CTL_reserved1_SHIFT 14
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [13:10] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00003c00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: RD_EN_DRIVE_PAD_CTL :: reserved2 [09:09] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DRIVE_PAD_CTL_reserved2_MASK 0x00000200
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DRIVE_PAD_CTL_reserved2_SHIFT 9
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [08:05] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000001e0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: RD_EN_DRIVE_PAD_CTL :: reserved3 [04:04] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DRIVE_PAD_CTL_reserved3_MASK 0x00000010
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DRIVE_PAD_CTL_reserved3_SHIFT 4
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [03:00] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000000f
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *STATIC_PAD_CTL - pad rx and tx characteristics control register
+ ***************************************************************************/
+/* DDR34_PHY_BYTE_LANE_3_2 :: STATIC_PAD_CTL :: reserved0 [31:21] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_STATIC_PAD_CTL_reserved0_SHIFT 21
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_STATIC_PAD_CTL_DQS_MODE_MASK  0x00100000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: STATIC_PAD_CTL :: reserved1 [19:18] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_STATIC_PAD_CTL_reserved1_SHIFT 18
+
+/* DDR34_PHY_BYTE_LANE_3_2 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_STATIC_PAD_CTL_EDC_MODE_MASK  0x00030000
+#define BCHP_DDR34_PHY_BYTE_LANE_3_2_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
+#defi